1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
139 /* Used to turn off indicated flags. */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 i386_cpu_flags flags
; /* cpu feature flags */
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
157 static void pe_directive_secrel (int);
159 static void signed_cons (int);
160 static char *output_invalid (int c
);
161 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
163 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS
*);
168 static int i386_intel_parse_name (const char *, expressionS
*);
169 static const reg_entry
*parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template
*match_template (char);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry
*build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS
*, offsetT
);
188 static void output_disp (fragS
*, offsetT
);
190 static void s_bss (int);
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
196 static const char *default_arch
= DEFAULT_ARCH
;
198 /* This struct describes rounding control and SAE in the instruction. */
212 static struct RC_Operation rc_op
;
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
219 const reg_entry
*mask
;
220 unsigned int zeroing
;
221 /* The operand where this operation is associated. */
225 static struct Mask_Operation mask_op
;
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
229 struct Broadcast_Operation
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
234 /* Index of broadcasted operand. */
238 static struct Broadcast_Operation broadcast_op
;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes
[4];
246 /* Destination or source register specifier. */
247 const reg_entry
*register_specifier
;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry
*regs
;
262 operand_size_mismatch
,
263 operand_type_mismatch
,
264 register_type_mismatch
,
265 number_of_operands_mismatch
,
266 invalid_instruction_suffix
,
269 unsupported_with_intel_mnemonic
,
272 invalid_vsib_address
,
273 invalid_vector_register_set
,
274 unsupported_vector_index_register
,
275 unsupported_broadcast
,
276 broadcast_not_on_src_operand
,
279 mask_not_on_destination
,
282 rc_sae_operand_not_last_imm
,
283 invalid_register_operand
,
288 /* TM holds the template for the insn were currently assembling. */
291 /* SUFFIX holds the instruction size suffix for byte, word, dword
292 or qword, if given. */
295 /* OPERANDS gives the number of given operands. */
296 unsigned int operands
;
298 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
299 of given register, displacement, memory operands and immediate
301 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
303 /* TYPES [i] is the type (see above #defines) which tells us how to
304 use OP[i] for the corresponding operand. */
305 i386_operand_type types
[MAX_OPERANDS
];
307 /* Displacement expression, immediate expression, or register for each
309 union i386_op op
[MAX_OPERANDS
];
311 /* Flags for operands. */
312 unsigned int flags
[MAX_OPERANDS
];
313 #define Operand_PCrel 1
315 /* Relocation type for operand */
316 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
318 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
319 the base index byte below. */
320 const reg_entry
*base_reg
;
321 const reg_entry
*index_reg
;
322 unsigned int log2_scale_factor
;
324 /* SEG gives the seg_entries of this insn. They are zero unless
325 explicit segment overrides are given. */
326 const seg_entry
*seg
[2];
328 /* Copied first memory operand string, for re-checking. */
331 /* PREFIX holds all the given prefix opcodes (usually null).
332 PREFIXES is the number of prefix opcodes. */
333 unsigned int prefixes
;
334 unsigned char prefix
[MAX_PREFIXES
];
336 /* RM and SIB are the modrm byte and the sib byte where the
337 addressing modes of this insn are encoded. */
344 /* Masking attributes. */
345 struct Mask_Operation
*mask
;
347 /* Rounding control and SAE attributes. */
348 struct RC_Operation
*rounding
;
350 /* Broadcasting attributes. */
351 struct Broadcast_Operation
*broadcast
;
353 /* Compressed disp8*N attribute. */
354 unsigned int memshift
;
356 /* Prefer load or store in encoding. */
359 dir_encoding_default
= 0,
364 /* Prefer 8bit or 32bit displacement in encoding. */
367 disp_encoding_default
= 0,
372 /* Prefer the REX byte in encoding. */
373 bfd_boolean rex_encoding
;
375 /* Disable instruction size optimization. */
376 bfd_boolean no_optimize
;
378 /* How to encode vector instructions. */
381 vex_encoding_default
= 0,
388 const char *rep_prefix
;
391 const char *hle_prefix
;
393 /* Have BND prefix. */
394 const char *bnd_prefix
;
396 /* Have NOTRACK prefix. */
397 const char *notrack_prefix
;
400 enum i386_error error
;
403 typedef struct _i386_insn i386_insn
;
405 /* Link RC type with corresponding string, that'll be looked for in
414 static const struct RC_name RC_NamesTable
[] =
416 { rne
, STRING_COMMA_LEN ("rn-sae") },
417 { rd
, STRING_COMMA_LEN ("rd-sae") },
418 { ru
, STRING_COMMA_LEN ("ru-sae") },
419 { rz
, STRING_COMMA_LEN ("rz-sae") },
420 { saeonly
, STRING_COMMA_LEN ("sae") },
423 /* List of chars besides those in app.c:symbol_chars that can start an
424 operand. Used to prevent the scrubber eating vital white-space. */
425 const char extra_symbol_chars
[] = "*%-([{}"
434 #if (defined (TE_I386AIX) \
435 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
436 && !defined (TE_GNU) \
437 && !defined (TE_LINUX) \
438 && !defined (TE_NACL) \
439 && !defined (TE_NETWARE) \
440 && !defined (TE_FreeBSD) \
441 && !defined (TE_DragonFly) \
442 && !defined (TE_NetBSD)))
443 /* This array holds the chars that always start a comment. If the
444 pre-processor is disabled, these aren't very useful. The option
445 --divide will remove '/' from this list. */
446 const char *i386_comment_chars
= "#/";
447 #define SVR4_COMMENT_CHARS 1
448 #define PREFIX_SEPARATOR '\\'
451 const char *i386_comment_chars
= "#";
452 #define PREFIX_SEPARATOR '/'
455 /* This array holds the chars that only start a comment at the beginning of
456 a line. If the line seems to have the form '# 123 filename'
457 .line and .file directives will appear in the pre-processed output.
458 Note that input_file.c hand checks for '#' at the beginning of the
459 first line of the input file. This is because the compiler outputs
460 #NO_APP at the beginning of its output.
461 Also note that comments started like this one will always work if
462 '/' isn't otherwise defined. */
463 const char line_comment_chars
[] = "#/";
465 const char line_separator_chars
[] = ";";
467 /* Chars that can be used to separate mant from exp in floating point
469 const char EXP_CHARS
[] = "eE";
471 /* Chars that mean this number is a floating point constant
474 const char FLT_CHARS
[] = "fFdDxX";
476 /* Tables for lexical analysis. */
477 static char mnemonic_chars
[256];
478 static char register_chars
[256];
479 static char operand_chars
[256];
480 static char identifier_chars
[256];
481 static char digit_chars
[256];
483 /* Lexical macros. */
484 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
485 #define is_operand_char(x) (operand_chars[(unsigned char) x])
486 #define is_register_char(x) (register_chars[(unsigned char) x])
487 #define is_space_char(x) ((x) == ' ')
488 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
489 #define is_digit_char(x) (digit_chars[(unsigned char) x])
491 /* All non-digit non-letter characters that may occur in an operand. */
492 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
494 /* md_assemble() always leaves the strings it's passed unaltered. To
495 effect this we maintain a stack of saved characters that we've smashed
496 with '\0's (indicating end of strings for various sub-fields of the
497 assembler instruction). */
498 static char save_stack
[32];
499 static char *save_stack_p
;
500 #define END_STRING_AND_SAVE(s) \
501 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
502 #define RESTORE_END_STRING(s) \
503 do { *(s) = *--save_stack_p; } while (0)
505 /* The instruction we're assembling. */
508 /* Possible templates for current insn. */
509 static const templates
*current_templates
;
511 /* Per instruction expressionS buffers: max displacements & immediates. */
512 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
513 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
515 /* Current operand we are working on. */
516 static int this_operand
= -1;
518 /* We support four different modes. FLAG_CODE variable is used to distinguish
526 static enum flag_code flag_code
;
527 static unsigned int object_64bit
;
528 static unsigned int disallow_64bit_reloc
;
529 static int use_rela_relocations
= 0;
531 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
532 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
533 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
535 /* The ELF ABI to use. */
543 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
546 #if defined (TE_PE) || defined (TE_PEP)
547 /* Use big object file format. */
548 static int use_big_obj
= 0;
551 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
552 /* 1 if generating code for a shared library. */
553 static int shared
= 0;
556 /* 1 for intel syntax,
558 static int intel_syntax
= 0;
560 /* 1 for Intel64 ISA,
564 /* 1 for intel mnemonic,
565 0 if att mnemonic. */
566 static int intel_mnemonic
= !SYSV386_COMPAT
;
568 /* 1 if support old (<= 2.8.1) versions of gcc. */
569 static int old_gcc
= OLDGCC_COMPAT
;
571 /* 1 if pseudo registers are permitted. */
572 static int allow_pseudo_reg
= 0;
574 /* 1 if register prefix % not required. */
575 static int allow_naked_reg
= 0;
577 /* 1 if the assembler should add BND prefix for all control-transferring
578 instructions supporting it, even if this prefix wasn't specified
580 static int add_bnd_prefix
= 0;
582 /* 1 if pseudo index register, eiz/riz, is allowed . */
583 static int allow_index_reg
= 0;
585 /* 1 if the assembler should ignore LOCK prefix, even if it was
586 specified explicitly. */
587 static int omit_lock_prefix
= 0;
589 /* 1 if the assembler should encode lfence, mfence, and sfence as
590 "lock addl $0, (%{re}sp)". */
591 static int avoid_fence
= 0;
593 /* 1 if the assembler should generate relax relocations. */
595 static int generate_relax_relocations
596 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
598 static enum check_kind
604 sse_check
, operand_check
= check_warning
;
607 1. Clear the REX_W bit with register operand if possible.
608 2. Above plus use 128bit vector instruction to clear the full vector
611 static int optimize
= 0;
614 1. Clear the REX_W bit with register operand if possible.
615 2. Above plus use 128bit vector instruction to clear the full vector
617 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
620 static int optimize_for_space
= 0;
622 /* Register prefix used for error message. */
623 static const char *register_prefix
= "%";
625 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
626 leave, push, and pop instructions so that gcc has the same stack
627 frame as in 32 bit mode. */
628 static char stackop_size
= '\0';
630 /* Non-zero to optimize code alignment. */
631 int optimize_align_code
= 1;
633 /* Non-zero to quieten some warnings. */
634 static int quiet_warnings
= 0;
637 static const char *cpu_arch_name
= NULL
;
638 static char *cpu_sub_arch_name
= NULL
;
640 /* CPU feature flags. */
641 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
643 /* If we have selected a cpu we are generating instructions for. */
644 static int cpu_arch_tune_set
= 0;
646 /* Cpu we are generating instructions for. */
647 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
649 /* CPU feature flags of cpu we are generating instructions for. */
650 static i386_cpu_flags cpu_arch_tune_flags
;
652 /* CPU instruction set architecture used. */
653 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
655 /* CPU feature flags of instruction set architecture used. */
656 i386_cpu_flags cpu_arch_isa_flags
;
658 /* If set, conditional jumps are not automatically promoted to handle
659 larger than a byte offset. */
660 static unsigned int no_cond_jump_promotion
= 0;
662 /* Encode SSE instructions with VEX prefix. */
663 static unsigned int sse2avx
;
665 /* Encode scalar AVX instructions with specific vector length. */
672 /* Encode scalar EVEX LIG instructions with specific vector length. */
680 /* Encode EVEX WIG instructions with specific evex.w. */
687 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
688 static enum rc_type evexrcig
= rne
;
690 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
691 static symbolS
*GOT_symbol
;
693 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
694 unsigned int x86_dwarf2_return_column
;
696 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
697 int x86_cie_data_alignment
;
699 /* Interface to relax_segment.
700 There are 3 major relax states for 386 jump insns because the
701 different types of jumps add different sizes to frags when we're
702 figuring out what sort of jump to choose to reach a given label. */
705 #define UNCOND_JUMP 0
707 #define COND_JUMP86 2
712 #define SMALL16 (SMALL | CODE16)
714 #define BIG16 (BIG | CODE16)
718 #define INLINE __inline__
724 #define ENCODE_RELAX_STATE(type, size) \
725 ((relax_substateT) (((type) << 2) | (size)))
726 #define TYPE_FROM_RELAX_STATE(s) \
728 #define DISP_SIZE_FROM_RELAX_STATE(s) \
729 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
731 /* This table is used by relax_frag to promote short jumps to long
732 ones where necessary. SMALL (short) jumps may be promoted to BIG
733 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
734 don't allow a short jump in a 32 bit code segment to be promoted to
735 a 16 bit offset jump because it's slower (requires data size
736 prefix), and doesn't work, unless the destination is in the bottom
737 64k of the code segment (The top 16 bits of eip are zeroed). */
739 const relax_typeS md_relax_table
[] =
742 1) most positive reach of this state,
743 2) most negative reach of this state,
744 3) how many bytes this mode will have in the variable part of the frag
745 4) which index into the table to try if we can't fit into this one. */
747 /* UNCOND_JUMP states. */
748 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
749 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
750 /* dword jmp adds 4 bytes to frag:
751 0 extra opcode bytes, 4 displacement bytes. */
753 /* word jmp adds 2 byte2 to frag:
754 0 extra opcode bytes, 2 displacement bytes. */
757 /* COND_JUMP states. */
758 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
759 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
760 /* dword conditionals adds 5 bytes to frag:
761 1 extra opcode byte, 4 displacement bytes. */
763 /* word conditionals add 3 bytes to frag:
764 1 extra opcode byte, 2 displacement bytes. */
767 /* COND_JUMP86 states. */
768 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
769 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
770 /* dword conditionals adds 5 bytes to frag:
771 1 extra opcode byte, 4 displacement bytes. */
773 /* word conditionals add 4 bytes to frag:
774 1 displacement byte and a 3 byte long branch insn. */
778 static const arch_entry cpu_arch
[] =
780 /* Do not replace the first two entries - i386_target_format()
781 relies on them being there in this order. */
782 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
783 CPU_GENERIC32_FLAGS
, 0 },
784 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
785 CPU_GENERIC64_FLAGS
, 0 },
786 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
788 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
790 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
792 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
794 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
796 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
798 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
800 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
802 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
803 CPU_PENTIUMPRO_FLAGS
, 0 },
804 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
806 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
808 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
810 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
812 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
813 CPU_NOCONA_FLAGS
, 0 },
814 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
816 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
818 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
819 CPU_CORE2_FLAGS
, 1 },
820 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
821 CPU_CORE2_FLAGS
, 0 },
822 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
823 CPU_COREI7_FLAGS
, 0 },
824 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
826 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
828 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
829 CPU_IAMCU_FLAGS
, 0 },
830 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
832 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
834 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
835 CPU_ATHLON_FLAGS
, 0 },
836 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
838 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
840 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
842 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
843 CPU_AMDFAM10_FLAGS
, 0 },
844 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
845 CPU_BDVER1_FLAGS
, 0 },
846 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
847 CPU_BDVER2_FLAGS
, 0 },
848 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
849 CPU_BDVER3_FLAGS
, 0 },
850 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
851 CPU_BDVER4_FLAGS
, 0 },
852 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
853 CPU_ZNVER1_FLAGS
, 0 },
854 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
855 CPU_BTVER1_FLAGS
, 0 },
856 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
857 CPU_BTVER2_FLAGS
, 0 },
858 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
860 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
862 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
864 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
866 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
868 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
870 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
872 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
874 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
875 CPU_SSSE3_FLAGS
, 0 },
876 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
877 CPU_SSE4_1_FLAGS
, 0 },
878 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
879 CPU_SSE4_2_FLAGS
, 0 },
880 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
881 CPU_SSE4_2_FLAGS
, 0 },
882 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
884 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
886 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
887 CPU_AVX512F_FLAGS
, 0 },
888 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
889 CPU_AVX512CD_FLAGS
, 0 },
890 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
891 CPU_AVX512ER_FLAGS
, 0 },
892 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
893 CPU_AVX512PF_FLAGS
, 0 },
894 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
895 CPU_AVX512DQ_FLAGS
, 0 },
896 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
897 CPU_AVX512BW_FLAGS
, 0 },
898 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
899 CPU_AVX512VL_FLAGS
, 0 },
900 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
902 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
903 CPU_VMFUNC_FLAGS
, 0 },
904 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
906 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
907 CPU_XSAVE_FLAGS
, 0 },
908 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
909 CPU_XSAVEOPT_FLAGS
, 0 },
910 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
911 CPU_XSAVEC_FLAGS
, 0 },
912 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
913 CPU_XSAVES_FLAGS
, 0 },
914 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
916 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
917 CPU_PCLMUL_FLAGS
, 0 },
918 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
919 CPU_PCLMUL_FLAGS
, 1 },
920 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
921 CPU_FSGSBASE_FLAGS
, 0 },
922 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
923 CPU_RDRND_FLAGS
, 0 },
924 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
926 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
928 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
930 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
932 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
934 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
936 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
937 CPU_MOVBE_FLAGS
, 0 },
938 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
940 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
942 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
943 CPU_LZCNT_FLAGS
, 0 },
944 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
946 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
948 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
949 CPU_INVPCID_FLAGS
, 0 },
950 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
951 CPU_CLFLUSH_FLAGS
, 0 },
952 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
954 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
955 CPU_SYSCALL_FLAGS
, 0 },
956 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
957 CPU_RDTSCP_FLAGS
, 0 },
958 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
959 CPU_3DNOW_FLAGS
, 0 },
960 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
961 CPU_3DNOWA_FLAGS
, 0 },
962 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
963 CPU_PADLOCK_FLAGS
, 0 },
964 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
966 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
968 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
969 CPU_SSE4A_FLAGS
, 0 },
970 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
972 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
974 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
976 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
978 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
979 CPU_RDSEED_FLAGS
, 0 },
980 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
981 CPU_PRFCHW_FLAGS
, 0 },
982 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
984 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
986 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
988 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
989 CPU_CLFLUSHOPT_FLAGS
, 0 },
990 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
991 CPU_PREFETCHWT1_FLAGS
, 0 },
992 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
994 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
996 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
997 CPU_AVX512IFMA_FLAGS
, 0 },
998 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
999 CPU_AVX512VBMI_FLAGS
, 0 },
1000 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1001 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1002 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1003 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1004 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1005 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1006 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1007 CPU_AVX512_VBMI2_FLAGS
, 0 },
1008 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1009 CPU_AVX512_VNNI_FLAGS
, 0 },
1010 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1011 CPU_AVX512_BITALG_FLAGS
, 0 },
1012 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1013 CPU_CLZERO_FLAGS
, 0 },
1014 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1015 CPU_MWAITX_FLAGS
, 0 },
1016 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1017 CPU_OSPKE_FLAGS
, 0 },
1018 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1019 CPU_RDPID_FLAGS
, 0 },
1020 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1021 CPU_PTWRITE_FLAGS
, 0 },
1022 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1024 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1025 CPU_SHSTK_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1027 CPU_GFNI_FLAGS
, 0 },
1028 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1029 CPU_VAES_FLAGS
, 0 },
1030 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1031 CPU_VPCLMULQDQ_FLAGS
, 0 },
1032 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1033 CPU_WBNOINVD_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1035 CPU_PCONFIG_FLAGS
, 0 },
1038 static const noarch_entry cpu_noarch
[] =
1040 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1041 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1042 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1043 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1044 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1045 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1046 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1047 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1048 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1049 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1050 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1051 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1052 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1053 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1054 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1055 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1056 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1057 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1058 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1059 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1060 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1061 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1062 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1063 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1064 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1065 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1066 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1067 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1068 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1069 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1070 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1074 /* Like s_lcomm_internal in gas/read.c but the alignment string
1075 is allowed to be optional. */
1078 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1085 && *input_line_pointer
== ',')
1087 align
= parse_align (needs_align
- 1);
1089 if (align
== (addressT
) -1)
1104 bss_alloc (symbolP
, size
, align
);
1109 pe_lcomm (int needs_align
)
1111 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1115 const pseudo_typeS md_pseudo_table
[] =
1117 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1118 {"align", s_align_bytes
, 0},
1120 {"align", s_align_ptwo
, 0},
1122 {"arch", set_cpu_arch
, 0},
1126 {"lcomm", pe_lcomm
, 1},
1128 {"ffloat", float_cons
, 'f'},
1129 {"dfloat", float_cons
, 'd'},
1130 {"tfloat", float_cons
, 'x'},
1132 {"slong", signed_cons
, 4},
1133 {"noopt", s_ignore
, 0},
1134 {"optim", s_ignore
, 0},
1135 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1136 {"code16", set_code_flag
, CODE_16BIT
},
1137 {"code32", set_code_flag
, CODE_32BIT
},
1139 {"code64", set_code_flag
, CODE_64BIT
},
1141 {"intel_syntax", set_intel_syntax
, 1},
1142 {"att_syntax", set_intel_syntax
, 0},
1143 {"intel_mnemonic", set_intel_mnemonic
, 1},
1144 {"att_mnemonic", set_intel_mnemonic
, 0},
1145 {"allow_index_reg", set_allow_index_reg
, 1},
1146 {"disallow_index_reg", set_allow_index_reg
, 0},
1147 {"sse_check", set_check
, 0},
1148 {"operand_check", set_check
, 1},
1149 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1150 {"largecomm", handle_large_common
, 0},
1152 {"file", dwarf2_directive_file
, 0},
1153 {"loc", dwarf2_directive_loc
, 0},
1154 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1157 {"secrel32", pe_directive_secrel
, 0},
1162 /* For interface with expression (). */
1163 extern char *input_line_pointer
;
1165 /* Hash table for instruction mnemonic lookup. */
1166 static struct hash_control
*op_hash
;
1168 /* Hash table for register lookup. */
1169 static struct hash_control
*reg_hash
;
1171 /* Various efficient no-op patterns for aligning code labels.
1172 Note: Don't try to assemble the instructions in the comments.
1173 0L and 0w are not legal. */
1174 static const unsigned char f32_1
[] =
1176 static const unsigned char f32_2
[] =
1177 {0x66,0x90}; /* xchg %ax,%ax */
1178 static const unsigned char f32_3
[] =
1179 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1180 static const unsigned char f32_4
[] =
1181 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1182 static const unsigned char f32_6
[] =
1183 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1184 static const unsigned char f32_7
[] =
1185 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1186 static const unsigned char f16_3
[] =
1187 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1188 static const unsigned char f16_4
[] =
1189 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1190 static const unsigned char jump_disp8
[] =
1191 {0xeb}; /* jmp disp8 */
1192 static const unsigned char jump32_disp32
[] =
1193 {0xe9}; /* jmp disp32 */
1194 static const unsigned char jump16_disp32
[] =
1195 {0x66,0xe9}; /* jmp disp32 */
1196 /* 32-bit NOPs patterns. */
1197 static const unsigned char *const f32_patt
[] = {
1198 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1200 /* 16-bit NOPs patterns. */
1201 static const unsigned char *const f16_patt
[] = {
1202 f32_1
, f32_2
, f16_3
, f16_4
1204 /* nopl (%[re]ax) */
1205 static const unsigned char alt_3
[] =
1207 /* nopl 0(%[re]ax) */
1208 static const unsigned char alt_4
[] =
1209 {0x0f,0x1f,0x40,0x00};
1210 /* nopl 0(%[re]ax,%[re]ax,1) */
1211 static const unsigned char alt_5
[] =
1212 {0x0f,0x1f,0x44,0x00,0x00};
1213 /* nopw 0(%[re]ax,%[re]ax,1) */
1214 static const unsigned char alt_6
[] =
1215 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1216 /* nopl 0L(%[re]ax) */
1217 static const unsigned char alt_7
[] =
1218 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1219 /* nopl 0L(%[re]ax,%[re]ax,1) */
1220 static const unsigned char alt_8
[] =
1221 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1222 /* nopw 0L(%[re]ax,%[re]ax,1) */
1223 static const unsigned char alt_9
[] =
1224 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1225 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1226 static const unsigned char alt_10
[] =
1227 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1228 /* data16 nopw %cs:0L(%eax,%eax,1) */
1229 static const unsigned char alt_11
[] =
1230 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1231 /* 32-bit and 64-bit NOPs patterns. */
1232 static const unsigned char *const alt_patt
[] = {
1233 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1234 alt_9
, alt_10
, alt_11
1237 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1238 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1241 i386_output_nops (char *where
, const unsigned char *const *patt
,
1242 int count
, int max_single_nop_size
)
1245 /* Place the longer NOP first. */
1248 const unsigned char *nops
= patt
[max_single_nop_size
- 1];
1250 /* Use the smaller one if the requsted one isn't available. */
1253 max_single_nop_size
--;
1254 nops
= patt
[max_single_nop_size
- 1];
1257 last
= count
% max_single_nop_size
;
1260 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1261 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1265 nops
= patt
[last
- 1];
1268 /* Use the smaller one plus one-byte NOP if the needed one
1271 nops
= patt
[last
- 1];
1272 memcpy (where
+ offset
, nops
, last
);
1273 where
[offset
+ last
] = *patt
[0];
1276 memcpy (where
+ offset
, nops
, last
);
1281 fits_in_imm7 (offsetT num
)
1283 return (num
& 0x7f) == num
;
1287 fits_in_imm31 (offsetT num
)
1289 return (num
& 0x7fffffff) == num
;
1292 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1293 single NOP instruction LIMIT. */
1296 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1298 const unsigned char *const *patt
= NULL
;
1299 int max_single_nop_size
;
1300 /* Maximum number of NOPs before switching to jump over NOPs. */
1301 int max_number_of_nops
;
1303 switch (fragP
->fr_type
)
1312 /* We need to decide which NOP sequence to use for 32bit and
1313 64bit. When -mtune= is used:
1315 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1316 PROCESSOR_GENERIC32, f32_patt will be used.
1317 2. For the rest, alt_patt will be used.
1319 When -mtune= isn't used, alt_patt will be used if
1320 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1323 When -march= or .arch is used, we can't use anything beyond
1324 cpu_arch_isa_flags. */
1326 if (flag_code
== CODE_16BIT
)
1329 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1330 /* Limit number of NOPs to 2 in 16-bit mode. */
1331 max_number_of_nops
= 2;
1335 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1337 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1338 switch (cpu_arch_tune
)
1340 case PROCESSOR_UNKNOWN
:
1341 /* We use cpu_arch_isa_flags to check if we SHOULD
1342 optimize with nops. */
1343 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1348 case PROCESSOR_PENTIUM4
:
1349 case PROCESSOR_NOCONA
:
1350 case PROCESSOR_CORE
:
1351 case PROCESSOR_CORE2
:
1352 case PROCESSOR_COREI7
:
1353 case PROCESSOR_L1OM
:
1354 case PROCESSOR_K1OM
:
1355 case PROCESSOR_GENERIC64
:
1357 case PROCESSOR_ATHLON
:
1359 case PROCESSOR_AMDFAM10
:
1361 case PROCESSOR_ZNVER
:
1365 case PROCESSOR_I386
:
1366 case PROCESSOR_I486
:
1367 case PROCESSOR_PENTIUM
:
1368 case PROCESSOR_PENTIUMPRO
:
1369 case PROCESSOR_IAMCU
:
1370 case PROCESSOR_GENERIC32
:
1377 switch (fragP
->tc_frag_data
.tune
)
1379 case PROCESSOR_UNKNOWN
:
1380 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1381 PROCESSOR_UNKNOWN. */
1385 case PROCESSOR_I386
:
1386 case PROCESSOR_I486
:
1387 case PROCESSOR_PENTIUM
:
1388 case PROCESSOR_IAMCU
:
1390 case PROCESSOR_ATHLON
:
1392 case PROCESSOR_AMDFAM10
:
1394 case PROCESSOR_ZNVER
:
1396 case PROCESSOR_GENERIC32
:
1397 /* We use cpu_arch_isa_flags to check if we CAN optimize
1399 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1404 case PROCESSOR_PENTIUMPRO
:
1405 case PROCESSOR_PENTIUM4
:
1406 case PROCESSOR_NOCONA
:
1407 case PROCESSOR_CORE
:
1408 case PROCESSOR_CORE2
:
1409 case PROCESSOR_COREI7
:
1410 case PROCESSOR_L1OM
:
1411 case PROCESSOR_K1OM
:
1412 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1417 case PROCESSOR_GENERIC64
:
1423 if (patt
== f32_patt
)
1425 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1426 /* Limit number of NOPs to 2 for older processors. */
1427 max_number_of_nops
= 2;
1431 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1432 /* Limit number of NOPs to 7 for newer processors. */
1433 max_number_of_nops
= 7;
1438 limit
= max_single_nop_size
;
1440 if (fragP
->fr_type
== rs_fill_nop
)
1442 /* Output NOPs for .nop directive. */
1443 if (limit
> max_single_nop_size
)
1445 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1446 _("invalid single nop size: %d "
1447 "(expect within [0, %d])"),
1448 limit
, max_single_nop_size
);
1453 fragP
->fr_var
= count
;
1455 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1457 /* Generate jump over NOPs. */
1458 offsetT disp
= count
- 2;
1459 if (fits_in_imm7 (disp
))
1461 /* Use "jmp disp8" if possible. */
1463 where
[0] = jump_disp8
[0];
1469 unsigned int size_of_jump
;
1471 if (flag_code
== CODE_16BIT
)
1473 where
[0] = jump16_disp32
[0];
1474 where
[1] = jump16_disp32
[1];
1479 where
[0] = jump32_disp32
[0];
1483 count
-= size_of_jump
+ 4;
1484 if (!fits_in_imm31 (count
))
1486 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1487 _("jump over nop padding out of range"));
1491 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1492 where
+= size_of_jump
+ 4;
1496 /* Generate multiple NOPs. */
1497 i386_output_nops (where
, patt
, count
, limit
);
1501 operand_type_all_zero (const union i386_operand_type
*x
)
1503 switch (ARRAY_SIZE(x
->array
))
1514 return !x
->array
[0];
1521 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1523 switch (ARRAY_SIZE(x
->array
))
1541 operand_type_equal (const union i386_operand_type
*x
,
1542 const union i386_operand_type
*y
)
1544 switch (ARRAY_SIZE(x
->array
))
1547 if (x
->array
[2] != y
->array
[2])
1551 if (x
->array
[1] != y
->array
[1])
1555 return x
->array
[0] == y
->array
[0];
1563 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1565 switch (ARRAY_SIZE(x
->array
))
1580 return !x
->array
[0];
1587 cpu_flags_equal (const union i386_cpu_flags
*x
,
1588 const union i386_cpu_flags
*y
)
1590 switch (ARRAY_SIZE(x
->array
))
1593 if (x
->array
[3] != y
->array
[3])
1597 if (x
->array
[2] != y
->array
[2])
1601 if (x
->array
[1] != y
->array
[1])
1605 return x
->array
[0] == y
->array
[0];
1613 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1615 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1616 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1619 static INLINE i386_cpu_flags
1620 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1622 switch (ARRAY_SIZE (x
.array
))
1625 x
.array
[3] &= y
.array
[3];
1628 x
.array
[2] &= y
.array
[2];
1631 x
.array
[1] &= y
.array
[1];
1634 x
.array
[0] &= y
.array
[0];
1642 static INLINE i386_cpu_flags
1643 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1645 switch (ARRAY_SIZE (x
.array
))
1648 x
.array
[3] |= y
.array
[3];
1651 x
.array
[2] |= y
.array
[2];
1654 x
.array
[1] |= y
.array
[1];
1657 x
.array
[0] |= y
.array
[0];
1665 static INLINE i386_cpu_flags
1666 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1668 switch (ARRAY_SIZE (x
.array
))
1671 x
.array
[3] &= ~y
.array
[3];
1674 x
.array
[2] &= ~y
.array
[2];
1677 x
.array
[1] &= ~y
.array
[1];
1680 x
.array
[0] &= ~y
.array
[0];
1688 #define CPU_FLAGS_ARCH_MATCH 0x1
1689 #define CPU_FLAGS_64BIT_MATCH 0x2
1690 #define CPU_FLAGS_AES_MATCH 0x4
1691 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1692 #define CPU_FLAGS_AVX_MATCH 0x10
1694 #define CPU_FLAGS_32BIT_MATCH \
1695 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1696 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1697 #define CPU_FLAGS_PERFECT_MATCH \
1698 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1700 /* Return CPU flags match bits. */
1703 cpu_flags_match (const insn_template
*t
)
1705 i386_cpu_flags x
= t
->cpu_flags
;
1706 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1708 x
.bitfield
.cpu64
= 0;
1709 x
.bitfield
.cpuno64
= 0;
1711 if (cpu_flags_all_zero (&x
))
1713 /* This instruction is available on all archs. */
1714 match
|= CPU_FLAGS_32BIT_MATCH
;
1718 /* This instruction is available only on some archs. */
1719 i386_cpu_flags cpu
= cpu_arch_flags
;
1721 cpu
= cpu_flags_and (x
, cpu
);
1722 if (!cpu_flags_all_zero (&cpu
))
1724 if (x
.bitfield
.cpuavx
)
1726 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1727 if (cpu
.bitfield
.cpuavx
)
1729 /* Check SSE2AVX. */
1730 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1732 match
|= (CPU_FLAGS_ARCH_MATCH
1733 | CPU_FLAGS_AVX_MATCH
);
1735 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1736 match
|= CPU_FLAGS_AES_MATCH
;
1738 if (!x
.bitfield
.cpupclmul
1739 || cpu
.bitfield
.cpupclmul
)
1740 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1744 match
|= CPU_FLAGS_ARCH_MATCH
;
1746 else if (x
.bitfield
.cpuavx512vl
)
1748 /* Match AVX512VL. */
1749 if (cpu
.bitfield
.cpuavx512vl
)
1751 /* Need another match. */
1752 cpu
.bitfield
.cpuavx512vl
= 0;
1753 if (!cpu_flags_all_zero (&cpu
))
1754 match
|= CPU_FLAGS_32BIT_MATCH
;
1756 match
|= CPU_FLAGS_ARCH_MATCH
;
1759 match
|= CPU_FLAGS_ARCH_MATCH
;
1762 match
|= CPU_FLAGS_32BIT_MATCH
;
1768 static INLINE i386_operand_type
1769 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1771 switch (ARRAY_SIZE (x
.array
))
1774 x
.array
[2] &= y
.array
[2];
1777 x
.array
[1] &= y
.array
[1];
1780 x
.array
[0] &= y
.array
[0];
1788 static INLINE i386_operand_type
1789 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1791 switch (ARRAY_SIZE (x
.array
))
1794 x
.array
[2] &= ~y
.array
[2];
1797 x
.array
[1] &= ~y
.array
[1];
1800 x
.array
[0] &= ~y
.array
[0];
1808 static INLINE i386_operand_type
1809 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1811 switch (ARRAY_SIZE (x
.array
))
1814 x
.array
[2] |= y
.array
[2];
1817 x
.array
[1] |= y
.array
[1];
1820 x
.array
[0] |= y
.array
[0];
1828 static INLINE i386_operand_type
1829 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1831 switch (ARRAY_SIZE (x
.array
))
1834 x
.array
[2] ^= y
.array
[2];
1837 x
.array
[1] ^= y
.array
[1];
1840 x
.array
[0] ^= y
.array
[0];
1848 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1849 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1850 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1851 static const i386_operand_type inoutportreg
1852 = OPERAND_TYPE_INOUTPORTREG
;
1853 static const i386_operand_type reg16_inoutportreg
1854 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1855 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1856 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1857 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1858 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1859 static const i386_operand_type anydisp
1860 = OPERAND_TYPE_ANYDISP
;
1861 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1862 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1863 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1864 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1865 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1866 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1867 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1868 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1869 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1870 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1871 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1872 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1883 operand_type_check (i386_operand_type t
, enum operand_type c
)
1888 return t
.bitfield
.reg
;
1891 return (t
.bitfield
.imm8
1895 || t
.bitfield
.imm32s
1896 || t
.bitfield
.imm64
);
1899 return (t
.bitfield
.disp8
1900 || t
.bitfield
.disp16
1901 || t
.bitfield
.disp32
1902 || t
.bitfield
.disp32s
1903 || t
.bitfield
.disp64
);
1906 return (t
.bitfield
.disp8
1907 || t
.bitfield
.disp16
1908 || t
.bitfield
.disp32
1909 || t
.bitfield
.disp32s
1910 || t
.bitfield
.disp64
1911 || t
.bitfield
.baseindex
);
1920 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1921 operand J for instruction template T. */
1924 match_reg_size (const insn_template
*t
, unsigned int j
)
1926 return !((i
.types
[j
].bitfield
.byte
1927 && !t
->operand_types
[j
].bitfield
.byte
)
1928 || (i
.types
[j
].bitfield
.word
1929 && !t
->operand_types
[j
].bitfield
.word
)
1930 || (i
.types
[j
].bitfield
.dword
1931 && !t
->operand_types
[j
].bitfield
.dword
)
1932 || (i
.types
[j
].bitfield
.qword
1933 && !t
->operand_types
[j
].bitfield
.qword
)
1934 || (i
.types
[j
].bitfield
.tbyte
1935 && !t
->operand_types
[j
].bitfield
.tbyte
));
1938 /* Return 1 if there is no conflict in SIMD register on
1939 operand J for instruction template T. */
1942 match_simd_size (const insn_template
*t
, unsigned int j
)
1944 return !((i
.types
[j
].bitfield
.xmmword
1945 && !t
->operand_types
[j
].bitfield
.xmmword
)
1946 || (i
.types
[j
].bitfield
.ymmword
1947 && !t
->operand_types
[j
].bitfield
.ymmword
)
1948 || (i
.types
[j
].bitfield
.zmmword
1949 && !t
->operand_types
[j
].bitfield
.zmmword
));
1952 /* Return 1 if there is no conflict in any size on operand J for
1953 instruction template T. */
1956 match_mem_size (const insn_template
*t
, unsigned int j
)
1958 return (match_reg_size (t
, j
)
1959 && !((i
.types
[j
].bitfield
.unspecified
1961 && !t
->operand_types
[j
].bitfield
.unspecified
)
1962 || (i
.types
[j
].bitfield
.fword
1963 && !t
->operand_types
[j
].bitfield
.fword
)
1964 /* For scalar opcode templates to allow register and memory
1965 operands at the same time, some special casing is needed
1967 || ((t
->operand_types
[j
].bitfield
.regsimd
1968 && !t
->opcode_modifier
.broadcast
1969 && (t
->operand_types
[j
].bitfield
.dword
1970 || t
->operand_types
[j
].bitfield
.qword
))
1971 ? (i
.types
[j
].bitfield
.xmmword
1972 || i
.types
[j
].bitfield
.ymmword
1973 || i
.types
[j
].bitfield
.zmmword
)
1974 : !match_simd_size(t
, j
))));
1977 /* Return 1 if there is no size conflict on any operands for
1978 instruction template T. */
1981 operand_size_match (const insn_template
*t
)
1986 /* Don't check jump instructions. */
1987 if (t
->opcode_modifier
.jump
1988 || t
->opcode_modifier
.jumpbyte
1989 || t
->opcode_modifier
.jumpdword
1990 || t
->opcode_modifier
.jumpintersegment
)
1993 /* Check memory and accumulator operand size. */
1994 for (j
= 0; j
< i
.operands
; j
++)
1996 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
1997 && t
->operand_types
[j
].bitfield
.anysize
)
2000 if (t
->operand_types
[j
].bitfield
.reg
2001 && !match_reg_size (t
, j
))
2007 if (t
->operand_types
[j
].bitfield
.regsimd
2008 && !match_simd_size (t
, j
))
2014 if (t
->operand_types
[j
].bitfield
.acc
2015 && (!match_reg_size (t
, j
) || !match_simd_size (t
, j
)))
2021 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
2030 else if (!t
->opcode_modifier
.d
)
2033 i
.error
= operand_size_mismatch
;
2037 /* Check reverse. */
2038 gas_assert (i
.operands
== 2);
2041 for (j
= 0; j
< 2; j
++)
2043 if ((t
->operand_types
[j
].bitfield
.reg
2044 || t
->operand_types
[j
].bitfield
.acc
)
2045 && !match_reg_size (t
, j
? 0 : 1))
2048 if (i
.types
[j
].bitfield
.mem
2049 && !match_mem_size (t
, j
? 0 : 1))
2057 operand_type_match (i386_operand_type overlap
,
2058 i386_operand_type given
)
2060 i386_operand_type temp
= overlap
;
2062 temp
.bitfield
.jumpabsolute
= 0;
2063 temp
.bitfield
.unspecified
= 0;
2064 temp
.bitfield
.byte
= 0;
2065 temp
.bitfield
.word
= 0;
2066 temp
.bitfield
.dword
= 0;
2067 temp
.bitfield
.fword
= 0;
2068 temp
.bitfield
.qword
= 0;
2069 temp
.bitfield
.tbyte
= 0;
2070 temp
.bitfield
.xmmword
= 0;
2071 temp
.bitfield
.ymmword
= 0;
2072 temp
.bitfield
.zmmword
= 0;
2073 if (operand_type_all_zero (&temp
))
2076 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2077 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2081 i
.error
= operand_type_mismatch
;
2085 /* If given types g0 and g1 are registers they must be of the same type
2086 unless the expected operand type register overlap is null.
2087 Memory operand size of certain SIMD instructions is also being checked
2091 operand_type_register_match (i386_operand_type g0
,
2092 i386_operand_type t0
,
2093 i386_operand_type g1
,
2094 i386_operand_type t1
)
2096 if (!g0
.bitfield
.reg
2097 && !g0
.bitfield
.regsimd
2098 && (!operand_type_check (g0
, anymem
)
2099 || g0
.bitfield
.unspecified
2100 || !t0
.bitfield
.regsimd
))
2103 if (!g1
.bitfield
.reg
2104 && !g1
.bitfield
.regsimd
2105 && (!operand_type_check (g1
, anymem
)
2106 || g1
.bitfield
.unspecified
2107 || !t1
.bitfield
.regsimd
))
2110 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2111 && g0
.bitfield
.word
== g1
.bitfield
.word
2112 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2113 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2114 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2115 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2116 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2119 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2120 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2121 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2122 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2123 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2124 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2125 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2128 i
.error
= register_type_mismatch
;
2133 static INLINE
unsigned int
2134 register_number (const reg_entry
*r
)
2136 unsigned int nr
= r
->reg_num
;
2138 if (r
->reg_flags
& RegRex
)
2141 if (r
->reg_flags
& RegVRex
)
2147 static INLINE
unsigned int
2148 mode_from_disp_size (i386_operand_type t
)
2150 if (t
.bitfield
.disp8
)
2152 else if (t
.bitfield
.disp16
2153 || t
.bitfield
.disp32
2154 || t
.bitfield
.disp32s
)
2161 fits_in_signed_byte (addressT num
)
2163 return num
+ 0x80 <= 0xff;
2167 fits_in_unsigned_byte (addressT num
)
2173 fits_in_unsigned_word (addressT num
)
2175 return num
<= 0xffff;
2179 fits_in_signed_word (addressT num
)
2181 return num
+ 0x8000 <= 0xffff;
2185 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2190 return num
+ 0x80000000 <= 0xffffffff;
2192 } /* fits_in_signed_long() */
2195 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2200 return num
<= 0xffffffff;
2202 } /* fits_in_unsigned_long() */
2205 fits_in_disp8 (offsetT num
)
2207 int shift
= i
.memshift
;
2213 mask
= (1 << shift
) - 1;
2215 /* Return 0 if NUM isn't properly aligned. */
2219 /* Check if NUM will fit in 8bit after shift. */
2220 return fits_in_signed_byte (num
>> shift
);
2224 fits_in_imm4 (offsetT num
)
2226 return (num
& 0xf) == num
;
2229 static i386_operand_type
2230 smallest_imm_type (offsetT num
)
2232 i386_operand_type t
;
2234 operand_type_set (&t
, 0);
2235 t
.bitfield
.imm64
= 1;
2237 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2239 /* This code is disabled on the 486 because all the Imm1 forms
2240 in the opcode table are slower on the i486. They're the
2241 versions with the implicitly specified single-position
2242 displacement, which has another syntax if you really want to
2244 t
.bitfield
.imm1
= 1;
2245 t
.bitfield
.imm8
= 1;
2246 t
.bitfield
.imm8s
= 1;
2247 t
.bitfield
.imm16
= 1;
2248 t
.bitfield
.imm32
= 1;
2249 t
.bitfield
.imm32s
= 1;
2251 else if (fits_in_signed_byte (num
))
2253 t
.bitfield
.imm8
= 1;
2254 t
.bitfield
.imm8s
= 1;
2255 t
.bitfield
.imm16
= 1;
2256 t
.bitfield
.imm32
= 1;
2257 t
.bitfield
.imm32s
= 1;
2259 else if (fits_in_unsigned_byte (num
))
2261 t
.bitfield
.imm8
= 1;
2262 t
.bitfield
.imm16
= 1;
2263 t
.bitfield
.imm32
= 1;
2264 t
.bitfield
.imm32s
= 1;
2266 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2268 t
.bitfield
.imm16
= 1;
2269 t
.bitfield
.imm32
= 1;
2270 t
.bitfield
.imm32s
= 1;
2272 else if (fits_in_signed_long (num
))
2274 t
.bitfield
.imm32
= 1;
2275 t
.bitfield
.imm32s
= 1;
2277 else if (fits_in_unsigned_long (num
))
2278 t
.bitfield
.imm32
= 1;
2284 offset_in_range (offsetT val
, int size
)
2290 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2291 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2292 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2294 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2300 /* If BFD64, sign extend val for 32bit address mode. */
2301 if (flag_code
!= CODE_64BIT
2302 || i
.prefix
[ADDR_PREFIX
])
2303 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2304 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2307 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2309 char buf1
[40], buf2
[40];
2311 sprint_value (buf1
, val
);
2312 sprint_value (buf2
, val
& mask
);
2313 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2328 a. PREFIX_EXIST if attempting to add a prefix where one from the
2329 same class already exists.
2330 b. PREFIX_LOCK if lock prefix is added.
2331 c. PREFIX_REP if rep/repne prefix is added.
2332 d. PREFIX_DS if ds prefix is added.
2333 e. PREFIX_OTHER if other prefix is added.
2336 static enum PREFIX_GROUP
2337 add_prefix (unsigned int prefix
)
2339 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2342 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2343 && flag_code
== CODE_64BIT
)
2345 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2346 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2347 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2358 case DS_PREFIX_OPCODE
:
2361 case CS_PREFIX_OPCODE
:
2362 case ES_PREFIX_OPCODE
:
2363 case FS_PREFIX_OPCODE
:
2364 case GS_PREFIX_OPCODE
:
2365 case SS_PREFIX_OPCODE
:
2369 case REPNE_PREFIX_OPCODE
:
2370 case REPE_PREFIX_OPCODE
:
2375 case LOCK_PREFIX_OPCODE
:
2384 case ADDR_PREFIX_OPCODE
:
2388 case DATA_PREFIX_OPCODE
:
2392 if (i
.prefix
[q
] != 0)
2400 i
.prefix
[q
] |= prefix
;
2403 as_bad (_("same type of prefix used twice"));
2409 update_code_flag (int value
, int check
)
2411 PRINTF_LIKE ((*as_error
));
2413 flag_code
= (enum flag_code
) value
;
2414 if (flag_code
== CODE_64BIT
)
2416 cpu_arch_flags
.bitfield
.cpu64
= 1;
2417 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2421 cpu_arch_flags
.bitfield
.cpu64
= 0;
2422 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2424 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2427 as_error
= as_fatal
;
2430 (*as_error
) (_("64bit mode not supported on `%s'."),
2431 cpu_arch_name
? cpu_arch_name
: default_arch
);
2433 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2436 as_error
= as_fatal
;
2439 (*as_error
) (_("32bit mode not supported on `%s'."),
2440 cpu_arch_name
? cpu_arch_name
: default_arch
);
2442 stackop_size
= '\0';
2446 set_code_flag (int value
)
2448 update_code_flag (value
, 0);
2452 set_16bit_gcc_code_flag (int new_code_flag
)
2454 flag_code
= (enum flag_code
) new_code_flag
;
2455 if (flag_code
!= CODE_16BIT
)
2457 cpu_arch_flags
.bitfield
.cpu64
= 0;
2458 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2459 stackop_size
= LONG_MNEM_SUFFIX
;
2463 set_intel_syntax (int syntax_flag
)
2465 /* Find out if register prefixing is specified. */
2466 int ask_naked_reg
= 0;
2469 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2472 int e
= get_symbol_name (&string
);
2474 if (strcmp (string
, "prefix") == 0)
2476 else if (strcmp (string
, "noprefix") == 0)
2479 as_bad (_("bad argument to syntax directive."));
2480 (void) restore_line_pointer (e
);
2482 demand_empty_rest_of_line ();
2484 intel_syntax
= syntax_flag
;
2486 if (ask_naked_reg
== 0)
2487 allow_naked_reg
= (intel_syntax
2488 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2490 allow_naked_reg
= (ask_naked_reg
< 0);
2492 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2494 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2495 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2496 register_prefix
= allow_naked_reg
? "" : "%";
2500 set_intel_mnemonic (int mnemonic_flag
)
2502 intel_mnemonic
= mnemonic_flag
;
2506 set_allow_index_reg (int flag
)
2508 allow_index_reg
= flag
;
2512 set_check (int what
)
2514 enum check_kind
*kind
;
2519 kind
= &operand_check
;
2530 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2533 int e
= get_symbol_name (&string
);
2535 if (strcmp (string
, "none") == 0)
2537 else if (strcmp (string
, "warning") == 0)
2538 *kind
= check_warning
;
2539 else if (strcmp (string
, "error") == 0)
2540 *kind
= check_error
;
2542 as_bad (_("bad argument to %s_check directive."), str
);
2543 (void) restore_line_pointer (e
);
2546 as_bad (_("missing argument for %s_check directive"), str
);
2548 demand_empty_rest_of_line ();
2552 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2553 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2555 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2556 static const char *arch
;
2558 /* Intel LIOM is only supported on ELF. */
2564 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2565 use default_arch. */
2566 arch
= cpu_arch_name
;
2568 arch
= default_arch
;
2571 /* If we are targeting Intel MCU, we must enable it. */
2572 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2573 || new_flag
.bitfield
.cpuiamcu
)
2576 /* If we are targeting Intel L1OM, we must enable it. */
2577 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2578 || new_flag
.bitfield
.cpul1om
)
2581 /* If we are targeting Intel K1OM, we must enable it. */
2582 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2583 || new_flag
.bitfield
.cpuk1om
)
2586 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2591 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2595 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2598 int e
= get_symbol_name (&string
);
2600 i386_cpu_flags flags
;
2602 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2604 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2606 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2610 cpu_arch_name
= cpu_arch
[j
].name
;
2611 cpu_sub_arch_name
= NULL
;
2612 cpu_arch_flags
= cpu_arch
[j
].flags
;
2613 if (flag_code
== CODE_64BIT
)
2615 cpu_arch_flags
.bitfield
.cpu64
= 1;
2616 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2620 cpu_arch_flags
.bitfield
.cpu64
= 0;
2621 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2623 cpu_arch_isa
= cpu_arch
[j
].type
;
2624 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2625 if (!cpu_arch_tune_set
)
2627 cpu_arch_tune
= cpu_arch_isa
;
2628 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2633 flags
= cpu_flags_or (cpu_arch_flags
,
2636 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2638 if (cpu_sub_arch_name
)
2640 char *name
= cpu_sub_arch_name
;
2641 cpu_sub_arch_name
= concat (name
,
2643 (const char *) NULL
);
2647 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2648 cpu_arch_flags
= flags
;
2649 cpu_arch_isa_flags
= flags
;
2651 (void) restore_line_pointer (e
);
2652 demand_empty_rest_of_line ();
2657 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2659 /* Disable an ISA extension. */
2660 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2661 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2663 flags
= cpu_flags_and_not (cpu_arch_flags
,
2664 cpu_noarch
[j
].flags
);
2665 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2667 if (cpu_sub_arch_name
)
2669 char *name
= cpu_sub_arch_name
;
2670 cpu_sub_arch_name
= concat (name
, string
,
2671 (const char *) NULL
);
2675 cpu_sub_arch_name
= xstrdup (string
);
2676 cpu_arch_flags
= flags
;
2677 cpu_arch_isa_flags
= flags
;
2679 (void) restore_line_pointer (e
);
2680 demand_empty_rest_of_line ();
2684 j
= ARRAY_SIZE (cpu_arch
);
2687 if (j
>= ARRAY_SIZE (cpu_arch
))
2688 as_bad (_("no such architecture: `%s'"), string
);
2690 *input_line_pointer
= e
;
2693 as_bad (_("missing cpu architecture"));
2695 no_cond_jump_promotion
= 0;
2696 if (*input_line_pointer
== ','
2697 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2702 ++input_line_pointer
;
2703 e
= get_symbol_name (&string
);
2705 if (strcmp (string
, "nojumps") == 0)
2706 no_cond_jump_promotion
= 1;
2707 else if (strcmp (string
, "jumps") == 0)
2710 as_bad (_("no such architecture modifier: `%s'"), string
);
2712 (void) restore_line_pointer (e
);
2715 demand_empty_rest_of_line ();
2718 enum bfd_architecture
2721 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2723 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2724 || flag_code
!= CODE_64BIT
)
2725 as_fatal (_("Intel L1OM is 64bit ELF only"));
2726 return bfd_arch_l1om
;
2728 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2730 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2731 || flag_code
!= CODE_64BIT
)
2732 as_fatal (_("Intel K1OM is 64bit ELF only"));
2733 return bfd_arch_k1om
;
2735 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2737 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2738 || flag_code
== CODE_64BIT
)
2739 as_fatal (_("Intel MCU is 32bit ELF only"));
2740 return bfd_arch_iamcu
;
2743 return bfd_arch_i386
;
2749 if (!strncmp (default_arch
, "x86_64", 6))
2751 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2753 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2754 || default_arch
[6] != '\0')
2755 as_fatal (_("Intel L1OM is 64bit ELF only"));
2756 return bfd_mach_l1om
;
2758 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2760 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2761 || default_arch
[6] != '\0')
2762 as_fatal (_("Intel K1OM is 64bit ELF only"));
2763 return bfd_mach_k1om
;
2765 else if (default_arch
[6] == '\0')
2766 return bfd_mach_x86_64
;
2768 return bfd_mach_x64_32
;
2770 else if (!strcmp (default_arch
, "i386")
2771 || !strcmp (default_arch
, "iamcu"))
2773 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2775 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2776 as_fatal (_("Intel MCU is 32bit ELF only"));
2777 return bfd_mach_i386_iamcu
;
2780 return bfd_mach_i386_i386
;
2783 as_fatal (_("unknown architecture"));
2789 const char *hash_err
;
2791 /* Support pseudo prefixes like {disp32}. */
2792 lex_type
['{'] = LEX_BEGIN_NAME
;
2794 /* Initialize op_hash hash table. */
2795 op_hash
= hash_new ();
2798 const insn_template
*optab
;
2799 templates
*core_optab
;
2801 /* Setup for loop. */
2803 core_optab
= XNEW (templates
);
2804 core_optab
->start
= optab
;
2809 if (optab
->name
== NULL
2810 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2812 /* different name --> ship out current template list;
2813 add to hash table; & begin anew. */
2814 core_optab
->end
= optab
;
2815 hash_err
= hash_insert (op_hash
,
2817 (void *) core_optab
);
2820 as_fatal (_("can't hash %s: %s"),
2824 if (optab
->name
== NULL
)
2826 core_optab
= XNEW (templates
);
2827 core_optab
->start
= optab
;
2832 /* Initialize reg_hash hash table. */
2833 reg_hash
= hash_new ();
2835 const reg_entry
*regtab
;
2836 unsigned int regtab_size
= i386_regtab_size
;
2838 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2840 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2842 as_fatal (_("can't hash %s: %s"),
2848 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2853 for (c
= 0; c
< 256; c
++)
2858 mnemonic_chars
[c
] = c
;
2859 register_chars
[c
] = c
;
2860 operand_chars
[c
] = c
;
2862 else if (ISLOWER (c
))
2864 mnemonic_chars
[c
] = c
;
2865 register_chars
[c
] = c
;
2866 operand_chars
[c
] = c
;
2868 else if (ISUPPER (c
))
2870 mnemonic_chars
[c
] = TOLOWER (c
);
2871 register_chars
[c
] = mnemonic_chars
[c
];
2872 operand_chars
[c
] = c
;
2874 else if (c
== '{' || c
== '}')
2876 mnemonic_chars
[c
] = c
;
2877 operand_chars
[c
] = c
;
2880 if (ISALPHA (c
) || ISDIGIT (c
))
2881 identifier_chars
[c
] = c
;
2884 identifier_chars
[c
] = c
;
2885 operand_chars
[c
] = c
;
2890 identifier_chars
['@'] = '@';
2893 identifier_chars
['?'] = '?';
2894 operand_chars
['?'] = '?';
2896 digit_chars
['-'] = '-';
2897 mnemonic_chars
['_'] = '_';
2898 mnemonic_chars
['-'] = '-';
2899 mnemonic_chars
['.'] = '.';
2900 identifier_chars
['_'] = '_';
2901 identifier_chars
['.'] = '.';
2903 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2904 operand_chars
[(unsigned char) *p
] = *p
;
2907 if (flag_code
== CODE_64BIT
)
2909 #if defined (OBJ_COFF) && defined (TE_PE)
2910 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2913 x86_dwarf2_return_column
= 16;
2915 x86_cie_data_alignment
= -8;
2919 x86_dwarf2_return_column
= 8;
2920 x86_cie_data_alignment
= -4;
2925 i386_print_statistics (FILE *file
)
2927 hash_print_statistics (file
, "i386 opcode", op_hash
);
2928 hash_print_statistics (file
, "i386 register", reg_hash
);
2933 /* Debugging routines for md_assemble. */
2934 static void pte (insn_template
*);
2935 static void pt (i386_operand_type
);
2936 static void pe (expressionS
*);
2937 static void ps (symbolS
*);
2940 pi (char *line
, i386_insn
*x
)
2944 fprintf (stdout
, "%s: template ", line
);
2946 fprintf (stdout
, " address: base %s index %s scale %x\n",
2947 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2948 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2949 x
->log2_scale_factor
);
2950 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2951 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2952 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2953 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2954 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2955 (x
->rex
& REX_W
) != 0,
2956 (x
->rex
& REX_R
) != 0,
2957 (x
->rex
& REX_X
) != 0,
2958 (x
->rex
& REX_B
) != 0);
2959 for (j
= 0; j
< x
->operands
; j
++)
2961 fprintf (stdout
, " #%d: ", j
+ 1);
2963 fprintf (stdout
, "\n");
2964 if (x
->types
[j
].bitfield
.reg
2965 || x
->types
[j
].bitfield
.regmmx
2966 || x
->types
[j
].bitfield
.regsimd
2967 || x
->types
[j
].bitfield
.sreg2
2968 || x
->types
[j
].bitfield
.sreg3
2969 || x
->types
[j
].bitfield
.control
2970 || x
->types
[j
].bitfield
.debug
2971 || x
->types
[j
].bitfield
.test
)
2972 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2973 if (operand_type_check (x
->types
[j
], imm
))
2975 if (operand_type_check (x
->types
[j
], disp
))
2976 pe (x
->op
[j
].disps
);
2981 pte (insn_template
*t
)
2984 fprintf (stdout
, " %d operands ", t
->operands
);
2985 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2986 if (t
->extension_opcode
!= None
)
2987 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2988 if (t
->opcode_modifier
.d
)
2989 fprintf (stdout
, "D");
2990 if (t
->opcode_modifier
.w
)
2991 fprintf (stdout
, "W");
2992 fprintf (stdout
, "\n");
2993 for (j
= 0; j
< t
->operands
; j
++)
2995 fprintf (stdout
, " #%d type ", j
+ 1);
2996 pt (t
->operand_types
[j
]);
2997 fprintf (stdout
, "\n");
3004 fprintf (stdout
, " operation %d\n", e
->X_op
);
3005 fprintf (stdout
, " add_number %ld (%lx)\n",
3006 (long) e
->X_add_number
, (long) e
->X_add_number
);
3007 if (e
->X_add_symbol
)
3009 fprintf (stdout
, " add_symbol ");
3010 ps (e
->X_add_symbol
);
3011 fprintf (stdout
, "\n");
3015 fprintf (stdout
, " op_symbol ");
3016 ps (e
->X_op_symbol
);
3017 fprintf (stdout
, "\n");
3024 fprintf (stdout
, "%s type %s%s",
3026 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3027 segment_name (S_GET_SEGMENT (s
)));
3030 static struct type_name
3032 i386_operand_type mask
;
3035 const type_names
[] =
3037 { OPERAND_TYPE_REG8
, "r8" },
3038 { OPERAND_TYPE_REG16
, "r16" },
3039 { OPERAND_TYPE_REG32
, "r32" },
3040 { OPERAND_TYPE_REG64
, "r64" },
3041 { OPERAND_TYPE_IMM8
, "i8" },
3042 { OPERAND_TYPE_IMM8
, "i8s" },
3043 { OPERAND_TYPE_IMM16
, "i16" },
3044 { OPERAND_TYPE_IMM32
, "i32" },
3045 { OPERAND_TYPE_IMM32S
, "i32s" },
3046 { OPERAND_TYPE_IMM64
, "i64" },
3047 { OPERAND_TYPE_IMM1
, "i1" },
3048 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3049 { OPERAND_TYPE_DISP8
, "d8" },
3050 { OPERAND_TYPE_DISP16
, "d16" },
3051 { OPERAND_TYPE_DISP32
, "d32" },
3052 { OPERAND_TYPE_DISP32S
, "d32s" },
3053 { OPERAND_TYPE_DISP64
, "d64" },
3054 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3055 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3056 { OPERAND_TYPE_CONTROL
, "control reg" },
3057 { OPERAND_TYPE_TEST
, "test reg" },
3058 { OPERAND_TYPE_DEBUG
, "debug reg" },
3059 { OPERAND_TYPE_FLOATREG
, "FReg" },
3060 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3061 { OPERAND_TYPE_SREG2
, "SReg2" },
3062 { OPERAND_TYPE_SREG3
, "SReg3" },
3063 { OPERAND_TYPE_ACC
, "Acc" },
3064 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3065 { OPERAND_TYPE_REGMMX
, "rMMX" },
3066 { OPERAND_TYPE_REGXMM
, "rXMM" },
3067 { OPERAND_TYPE_REGYMM
, "rYMM" },
3068 { OPERAND_TYPE_REGZMM
, "rZMM" },
3069 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3070 { OPERAND_TYPE_ESSEG
, "es" },
3074 pt (i386_operand_type t
)
3077 i386_operand_type a
;
3079 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3081 a
= operand_type_and (t
, type_names
[j
].mask
);
3082 if (!operand_type_all_zero (&a
))
3083 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3088 #endif /* DEBUG386 */
3090 static bfd_reloc_code_real_type
3091 reloc (unsigned int size
,
3094 bfd_reloc_code_real_type other
)
3096 if (other
!= NO_RELOC
)
3098 reloc_howto_type
*rel
;
3103 case BFD_RELOC_X86_64_GOT32
:
3104 return BFD_RELOC_X86_64_GOT64
;
3106 case BFD_RELOC_X86_64_GOTPLT64
:
3107 return BFD_RELOC_X86_64_GOTPLT64
;
3109 case BFD_RELOC_X86_64_PLTOFF64
:
3110 return BFD_RELOC_X86_64_PLTOFF64
;
3112 case BFD_RELOC_X86_64_GOTPC32
:
3113 other
= BFD_RELOC_X86_64_GOTPC64
;
3115 case BFD_RELOC_X86_64_GOTPCREL
:
3116 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3118 case BFD_RELOC_X86_64_TPOFF32
:
3119 other
= BFD_RELOC_X86_64_TPOFF64
;
3121 case BFD_RELOC_X86_64_DTPOFF32
:
3122 other
= BFD_RELOC_X86_64_DTPOFF64
;
3128 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3129 if (other
== BFD_RELOC_SIZE32
)
3132 other
= BFD_RELOC_SIZE64
;
3135 as_bad (_("there are no pc-relative size relocations"));
3141 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3142 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3145 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3147 as_bad (_("unknown relocation (%u)"), other
);
3148 else if (size
!= bfd_get_reloc_size (rel
))
3149 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3150 bfd_get_reloc_size (rel
),
3152 else if (pcrel
&& !rel
->pc_relative
)
3153 as_bad (_("non-pc-relative relocation for pc-relative field"));
3154 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3156 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3158 as_bad (_("relocated field and relocation type differ in signedness"));
3167 as_bad (_("there are no unsigned pc-relative relocations"));
3170 case 1: return BFD_RELOC_8_PCREL
;
3171 case 2: return BFD_RELOC_16_PCREL
;
3172 case 4: return BFD_RELOC_32_PCREL
;
3173 case 8: return BFD_RELOC_64_PCREL
;
3175 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3182 case 4: return BFD_RELOC_X86_64_32S
;
3187 case 1: return BFD_RELOC_8
;
3188 case 2: return BFD_RELOC_16
;
3189 case 4: return BFD_RELOC_32
;
3190 case 8: return BFD_RELOC_64
;
3192 as_bad (_("cannot do %s %u byte relocation"),
3193 sign
> 0 ? "signed" : "unsigned", size
);
3199 /* Here we decide which fixups can be adjusted to make them relative to
3200 the beginning of the section instead of the symbol. Basically we need
3201 to make sure that the dynamic relocations are done correctly, so in
3202 some cases we force the original symbol to be used. */
3205 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3207 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3211 /* Don't adjust pc-relative references to merge sections in 64-bit
3213 if (use_rela_relocations
3214 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3218 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3219 and changed later by validate_fix. */
3220 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3221 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3224 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3225 for size relocations. */
3226 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3227 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3228 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3229 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3230 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3231 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3232 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3233 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3234 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3235 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3236 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3237 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3238 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3239 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3240 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3241 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3242 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3243 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3244 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3245 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3246 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3247 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3248 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3249 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3250 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3251 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3252 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3253 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3254 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3255 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3256 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3257 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3258 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3265 intel_float_operand (const char *mnemonic
)
3267 /* Note that the value returned is meaningful only for opcodes with (memory)
3268 operands, hence the code here is free to improperly handle opcodes that
3269 have no operands (for better performance and smaller code). */
3271 if (mnemonic
[0] != 'f')
3272 return 0; /* non-math */
3274 switch (mnemonic
[1])
3276 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3277 the fs segment override prefix not currently handled because no
3278 call path can make opcodes without operands get here */
3280 return 2 /* integer op */;
3282 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3283 return 3; /* fldcw/fldenv */
3286 if (mnemonic
[2] != 'o' /* fnop */)
3287 return 3; /* non-waiting control op */
3290 if (mnemonic
[2] == 's')
3291 return 3; /* frstor/frstpm */
3294 if (mnemonic
[2] == 'a')
3295 return 3; /* fsave */
3296 if (mnemonic
[2] == 't')
3298 switch (mnemonic
[3])
3300 case 'c': /* fstcw */
3301 case 'd': /* fstdw */
3302 case 'e': /* fstenv */
3303 case 's': /* fsts[gw] */
3309 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3310 return 0; /* fxsave/fxrstor are not really math ops */
3317 /* Build the VEX prefix. */
3320 build_vex_prefix (const insn_template
*t
)
3322 unsigned int register_specifier
;
3323 unsigned int implied_prefix
;
3324 unsigned int vector_length
;
3326 /* Check register specifier. */
3327 if (i
.vex
.register_specifier
)
3329 register_specifier
=
3330 ~register_number (i
.vex
.register_specifier
) & 0xf;
3331 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3334 register_specifier
= 0xf;
3336 /* Use 2-byte VEX prefix by swapping destination and source
3338 if (i
.vec_encoding
!= vex_encoding_vex3
3339 && i
.dir_encoding
== dir_encoding_default
3340 && i
.operands
== i
.reg_operands
3341 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3342 && i
.tm
.opcode_modifier
.load
3345 unsigned int xchg
= i
.operands
- 1;
3346 union i386_op temp_op
;
3347 i386_operand_type temp_type
;
3349 temp_type
= i
.types
[xchg
];
3350 i
.types
[xchg
] = i
.types
[0];
3351 i
.types
[0] = temp_type
;
3352 temp_op
= i
.op
[xchg
];
3353 i
.op
[xchg
] = i
.op
[0];
3356 gas_assert (i
.rm
.mode
== 3);
3360 i
.rm
.regmem
= i
.rm
.reg
;
3363 /* Use the next insn. */
3367 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3368 vector_length
= avxscalar
;
3369 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3376 for (op
= 0; op
< t
->operands
; ++op
)
3377 if (t
->operand_types
[op
].bitfield
.xmmword
3378 && t
->operand_types
[op
].bitfield
.ymmword
3379 && i
.types
[op
].bitfield
.ymmword
)
3386 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3391 case DATA_PREFIX_OPCODE
:
3394 case REPE_PREFIX_OPCODE
:
3397 case REPNE_PREFIX_OPCODE
:
3404 /* Use 2-byte VEX prefix if possible. */
3405 if (i
.vec_encoding
!= vex_encoding_vex3
3406 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3407 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3408 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3410 /* 2-byte VEX prefix. */
3414 i
.vex
.bytes
[0] = 0xc5;
3416 /* Check the REX.R bit. */
3417 r
= (i
.rex
& REX_R
) ? 0 : 1;
3418 i
.vex
.bytes
[1] = (r
<< 7
3419 | register_specifier
<< 3
3420 | vector_length
<< 2
3425 /* 3-byte VEX prefix. */
3430 switch (i
.tm
.opcode_modifier
.vexopcode
)
3434 i
.vex
.bytes
[0] = 0xc4;
3438 i
.vex
.bytes
[0] = 0xc4;
3442 i
.vex
.bytes
[0] = 0xc4;
3446 i
.vex
.bytes
[0] = 0x8f;
3450 i
.vex
.bytes
[0] = 0x8f;
3454 i
.vex
.bytes
[0] = 0x8f;
3460 /* The high 3 bits of the second VEX byte are 1's compliment
3461 of RXB bits from REX. */
3462 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3464 /* Check the REX.W bit. */
3465 w
= (i
.rex
& REX_W
) ? 1 : 0;
3466 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3469 i
.vex
.bytes
[2] = (w
<< 7
3470 | register_specifier
<< 3
3471 | vector_length
<< 2
3476 /* Build the EVEX prefix. */
3479 build_evex_prefix (void)
3481 unsigned int register_specifier
;
3482 unsigned int implied_prefix
;
3484 rex_byte vrex_used
= 0;
3486 /* Check register specifier. */
3487 if (i
.vex
.register_specifier
)
3489 gas_assert ((i
.vrex
& REX_X
) == 0);
3491 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3492 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3493 register_specifier
+= 8;
3494 /* The upper 16 registers are encoded in the fourth byte of the
3496 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3497 i
.vex
.bytes
[3] = 0x8;
3498 register_specifier
= ~register_specifier
& 0xf;
3502 register_specifier
= 0xf;
3504 /* Encode upper 16 vector index register in the fourth byte of
3506 if (!(i
.vrex
& REX_X
))
3507 i
.vex
.bytes
[3] = 0x8;
3512 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3517 case DATA_PREFIX_OPCODE
:
3520 case REPE_PREFIX_OPCODE
:
3523 case REPNE_PREFIX_OPCODE
:
3530 /* 4 byte EVEX prefix. */
3532 i
.vex
.bytes
[0] = 0x62;
3535 switch (i
.tm
.opcode_modifier
.vexopcode
)
3551 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3553 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3555 /* The fifth bit of the second EVEX byte is 1's compliment of the
3556 REX_R bit in VREX. */
3557 if (!(i
.vrex
& REX_R
))
3558 i
.vex
.bytes
[1] |= 0x10;
3562 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3564 /* When all operands are registers, the REX_X bit in REX is not
3565 used. We reuse it to encode the upper 16 registers, which is
3566 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3567 as 1's compliment. */
3568 if ((i
.vrex
& REX_B
))
3571 i
.vex
.bytes
[1] &= ~0x40;
3575 /* EVEX instructions shouldn't need the REX prefix. */
3576 i
.vrex
&= ~vrex_used
;
3577 gas_assert (i
.vrex
== 0);
3579 /* Check the REX.W bit. */
3580 w
= (i
.rex
& REX_W
) ? 1 : 0;
3581 if (i
.tm
.opcode_modifier
.vexw
)
3583 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3586 /* If w is not set it means we are dealing with WIG instruction. */
3589 if (evexwig
== evexw1
)
3593 /* Encode the U bit. */
3594 implied_prefix
|= 0x4;
3596 /* The third byte of the EVEX prefix. */
3597 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3599 /* The fourth byte of the EVEX prefix. */
3600 /* The zeroing-masking bit. */
3601 if (i
.mask
&& i
.mask
->zeroing
)
3602 i
.vex
.bytes
[3] |= 0x80;
3604 /* Don't always set the broadcast bit if there is no RC. */
3607 /* Encode the vector length. */
3608 unsigned int vec_length
;
3610 switch (i
.tm
.opcode_modifier
.evex
)
3612 case EVEXLIG
: /* LL' is ignored */
3613 vec_length
= evexlig
<< 5;
3616 vec_length
= 0 << 5;
3619 vec_length
= 1 << 5;
3622 vec_length
= 2 << 5;
3628 i
.vex
.bytes
[3] |= vec_length
;
3629 /* Encode the broadcast bit. */
3631 i
.vex
.bytes
[3] |= 0x10;
3635 if (i
.rounding
->type
!= saeonly
)
3636 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3638 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3641 if (i
.mask
&& i
.mask
->mask
)
3642 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3646 process_immext (void)
3650 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3653 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3654 with an opcode suffix which is coded in the same place as an
3655 8-bit immediate field would be.
3656 Here we check those operands and remove them afterwards. */
3659 for (x
= 0; x
< i
.operands
; x
++)
3660 if (register_number (i
.op
[x
].regs
) != x
)
3661 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3662 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3668 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3670 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3671 suffix which is coded in the same place as an 8-bit immediate
3673 Here we check those operands and remove them afterwards. */
3676 if (i
.operands
!= 3)
3679 for (x
= 0; x
< 2; x
++)
3680 if (register_number (i
.op
[x
].regs
) != x
)
3681 goto bad_register_operand
;
3683 /* Check for third operand for mwaitx/monitorx insn. */
3684 if (register_number (i
.op
[x
].regs
)
3685 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3687 bad_register_operand
:
3688 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3689 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3696 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3697 which is coded in the same place as an 8-bit immediate field
3698 would be. Here we fake an 8-bit immediate operand from the
3699 opcode suffix stored in tm.extension_opcode.
3701 AVX instructions also use this encoding, for some of
3702 3 argument instructions. */
3704 gas_assert (i
.imm_operands
<= 1
3706 || ((i
.tm
.opcode_modifier
.vex
3707 || i
.tm
.opcode_modifier
.evex
)
3708 && i
.operands
<= 4)));
3710 exp
= &im_expressions
[i
.imm_operands
++];
3711 i
.op
[i
.operands
].imms
= exp
;
3712 i
.types
[i
.operands
] = imm8
;
3714 exp
->X_op
= O_constant
;
3715 exp
->X_add_number
= i
.tm
.extension_opcode
;
3716 i
.tm
.extension_opcode
= None
;
3723 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3728 as_bad (_("invalid instruction `%s' after `%s'"),
3729 i
.tm
.name
, i
.hle_prefix
);
3732 if (i
.prefix
[LOCK_PREFIX
])
3734 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3738 case HLEPrefixRelease
:
3739 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3741 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3745 if (i
.mem_operands
== 0
3746 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3748 as_bad (_("memory destination needed for instruction `%s'"
3749 " after `xrelease'"), i
.tm
.name
);
3756 /* Try the shortest encoding by shortening operand size. */
3759 optimize_encoding (void)
3763 if (optimize_for_space
3764 && i
.reg_operands
== 1
3765 && i
.imm_operands
== 1
3766 && !i
.types
[1].bitfield
.byte
3767 && i
.op
[0].imms
->X_op
== O_constant
3768 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3769 && ((i
.tm
.base_opcode
== 0xa8
3770 && i
.tm
.extension_opcode
== None
)
3771 || (i
.tm
.base_opcode
== 0xf6
3772 && i
.tm
.extension_opcode
== 0x0)))
3775 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3777 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3778 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3780 i
.types
[1].bitfield
.byte
= 1;
3781 /* Ignore the suffix. */
3783 if (base_regnum
>= 4
3784 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3786 /* Handle SP, BP, SI and DI registers. */
3787 if (i
.types
[1].bitfield
.word
)
3789 else if (i
.types
[1].bitfield
.dword
)
3797 else if (flag_code
== CODE_64BIT
3798 && ((i
.reg_operands
== 1
3799 && i
.imm_operands
== 1
3800 && i
.op
[0].imms
->X_op
== O_constant
3801 && ((i
.tm
.base_opcode
== 0xb0
3802 && i
.tm
.extension_opcode
== None
3803 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3804 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3805 && (((i
.tm
.base_opcode
== 0x24
3806 || i
.tm
.base_opcode
== 0xa8)
3807 && i
.tm
.extension_opcode
== None
)
3808 || (i
.tm
.base_opcode
== 0x80
3809 && i
.tm
.extension_opcode
== 0x4)
3810 || ((i
.tm
.base_opcode
== 0xf6
3811 || i
.tm
.base_opcode
== 0xc6)
3812 && i
.tm
.extension_opcode
== 0x0)))))
3813 || (i
.reg_operands
== 2
3814 && i
.op
[0].regs
== i
.op
[1].regs
3815 && ((i
.tm
.base_opcode
== 0x30
3816 || i
.tm
.base_opcode
== 0x28)
3817 && i
.tm
.extension_opcode
== None
)))
3818 && i
.types
[1].bitfield
.qword
)
3821 andq $imm31, %r64 -> andl $imm31, %r32
3822 testq $imm31, %r64 -> testl $imm31, %r32
3823 xorq %r64, %r64 -> xorl %r32, %r32
3824 subq %r64, %r64 -> subl %r32, %r32
3825 movq $imm31, %r64 -> movl $imm31, %r32
3826 movq $imm32, %r64 -> movl $imm32, %r32
3828 i
.tm
.opcode_modifier
.norex64
= 1;
3829 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
3832 movq $imm31, %r64 -> movl $imm31, %r32
3833 movq $imm32, %r64 -> movl $imm32, %r32
3835 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3836 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3837 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3838 i
.types
[0].bitfield
.imm32
= 1;
3839 i
.types
[0].bitfield
.imm32s
= 0;
3840 i
.types
[0].bitfield
.imm64
= 0;
3841 i
.types
[1].bitfield
.dword
= 1;
3842 i
.types
[1].bitfield
.qword
= 0;
3843 if (i
.tm
.base_opcode
== 0xc6)
3846 movq $imm31, %r64 -> movl $imm31, %r32
3848 i
.tm
.base_opcode
= 0xb0;
3849 i
.tm
.extension_opcode
= None
;
3850 i
.tm
.opcode_modifier
.shortform
= 1;
3851 i
.tm
.opcode_modifier
.modrm
= 0;
3855 else if (optimize
> 1
3856 && i
.reg_operands
== 3
3857 && i
.op
[0].regs
== i
.op
[1].regs
3858 && !i
.types
[2].bitfield
.xmmword
3859 && (i
.tm
.opcode_modifier
.vex
3862 && i
.tm
.opcode_modifier
.evex
3863 && cpu_arch_flags
.bitfield
.cpuavx512vl
))
3864 && ((i
.tm
.base_opcode
== 0x55
3865 || i
.tm
.base_opcode
== 0x6655
3866 || i
.tm
.base_opcode
== 0x66df
3867 || i
.tm
.base_opcode
== 0x57
3868 || i
.tm
.base_opcode
== 0x6657
3869 || i
.tm
.base_opcode
== 0x66ef
3870 || i
.tm
.base_opcode
== 0x66f8
3871 || i
.tm
.base_opcode
== 0x66f9
3872 || i
.tm
.base_opcode
== 0x66fa
3873 || i
.tm
.base_opcode
== 0x66fb)
3874 && i
.tm
.extension_opcode
== None
))
3877 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3879 EVEX VOP %zmmM, %zmmM, %zmmN
3880 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3881 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3882 EVEX VOP %ymmM, %ymmM, %ymmN
3883 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3884 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3885 VEX VOP %ymmM, %ymmM, %ymmN
3886 -> VEX VOP %xmmM, %xmmM, %xmmN
3887 VOP, one of vpandn and vpxor:
3888 VEX VOP %ymmM, %ymmM, %ymmN
3889 -> VEX VOP %xmmM, %xmmM, %xmmN
3890 VOP, one of vpandnd and vpandnq:
3891 EVEX VOP %zmmM, %zmmM, %zmmN
3892 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3893 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3894 EVEX VOP %ymmM, %ymmM, %ymmN
3895 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3896 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3897 VOP, one of vpxord and vpxorq:
3898 EVEX VOP %zmmM, %zmmM, %zmmN
3899 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3900 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3901 EVEX VOP %ymmM, %ymmM, %ymmN
3902 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3903 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3905 if (i
.tm
.opcode_modifier
.evex
)
3907 /* If only lower 16 vector registers are used, we can use
3909 for (j
= 0; j
< 3; j
++)
3910 if (register_number (i
.op
[j
].regs
) > 15)
3914 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3917 i
.tm
.opcode_modifier
.vex
= VEX128
;
3918 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
3919 i
.tm
.opcode_modifier
.evex
= 0;
3923 i
.tm
.opcode_modifier
.vex
= VEX128
;
3925 if (i
.tm
.opcode_modifier
.vex
)
3926 for (j
= 0; j
< 3; j
++)
3928 i
.types
[j
].bitfield
.xmmword
= 1;
3929 i
.types
[j
].bitfield
.ymmword
= 0;
3934 /* This is the guts of the machine-dependent assembler. LINE points to a
3935 machine dependent instruction. This function is supposed to emit
3936 the frags/bytes it assembles to. */
3939 md_assemble (char *line
)
3942 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
3943 const insn_template
*t
;
3945 /* Initialize globals. */
3946 memset (&i
, '\0', sizeof (i
));
3947 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3948 i
.reloc
[j
] = NO_RELOC
;
3949 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3950 memset (im_expressions
, '\0', sizeof (im_expressions
));
3951 save_stack_p
= save_stack
;
3953 /* First parse an instruction mnemonic & call i386_operand for the operands.
3954 We assume that the scrubber has arranged it so that line[0] is the valid
3955 start of a (possibly prefixed) mnemonic. */
3957 line
= parse_insn (line
, mnemonic
);
3960 mnem_suffix
= i
.suffix
;
3962 line
= parse_operands (line
, mnemonic
);
3964 xfree (i
.memop1_string
);
3965 i
.memop1_string
= NULL
;
3969 /* Now we've parsed the mnemonic into a set of templates, and have the
3970 operands at hand. */
3972 /* All intel opcodes have reversed operands except for "bound" and
3973 "enter". We also don't reverse intersegment "jmp" and "call"
3974 instructions with 2 immediate operands so that the immediate segment
3975 precedes the offset, as it does when in AT&T mode. */
3978 && (strcmp (mnemonic
, "bound") != 0)
3979 && (strcmp (mnemonic
, "invlpga") != 0)
3980 && !(operand_type_check (i
.types
[0], imm
)
3981 && operand_type_check (i
.types
[1], imm
)))
3984 /* The order of the immediates should be reversed
3985 for 2 immediates extrq and insertq instructions */
3986 if (i
.imm_operands
== 2
3987 && (strcmp (mnemonic
, "extrq") == 0
3988 || strcmp (mnemonic
, "insertq") == 0))
3989 swap_2_operands (0, 1);
3994 /* Don't optimize displacement for movabs since it only takes 64bit
3997 && i
.disp_encoding
!= disp_encoding_32bit
3998 && (flag_code
!= CODE_64BIT
3999 || strcmp (mnemonic
, "movabs") != 0))
4002 /* Next, we find a template that matches the given insn,
4003 making sure the overlap of the given operands types is consistent
4004 with the template operand types. */
4006 if (!(t
= match_template (mnem_suffix
)))
4009 if (sse_check
!= check_none
4010 && !i
.tm
.opcode_modifier
.noavx
4011 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4012 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4013 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4014 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4015 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4016 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
4018 (sse_check
== check_warning
4020 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4023 /* Zap movzx and movsx suffix. The suffix has been set from
4024 "word ptr" or "byte ptr" on the source operand in Intel syntax
4025 or extracted from mnemonic in AT&T syntax. But we'll use
4026 the destination register to choose the suffix for encoding. */
4027 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4029 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4030 there is no suffix, the default will be byte extension. */
4031 if (i
.reg_operands
!= 2
4034 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4039 if (i
.tm
.opcode_modifier
.fwait
)
4040 if (!add_prefix (FWAIT_OPCODE
))
4043 /* Check if REP prefix is OK. */
4044 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4046 as_bad (_("invalid instruction `%s' after `%s'"),
4047 i
.tm
.name
, i
.rep_prefix
);
4051 /* Check for lock without a lockable instruction. Destination operand
4052 must be memory unless it is xchg (0x86). */
4053 if (i
.prefix
[LOCK_PREFIX
]
4054 && (!i
.tm
.opcode_modifier
.islockable
4055 || i
.mem_operands
== 0
4056 || (i
.tm
.base_opcode
!= 0x86
4057 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4059 as_bad (_("expecting lockable instruction after `lock'"));
4063 /* Check if HLE prefix is OK. */
4064 if (i
.hle_prefix
&& !check_hle ())
4067 /* Check BND prefix. */
4068 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4069 as_bad (_("expecting valid branch instruction after `bnd'"));
4071 /* Check NOTRACK prefix. */
4072 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4073 as_bad (_("expecting indirect branch instruction after `notrack'"));
4075 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4077 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4078 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4079 else if (flag_code
!= CODE_16BIT
4080 ? i
.prefix
[ADDR_PREFIX
]
4081 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4082 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4085 /* Insert BND prefix. */
4087 && i
.tm
.opcode_modifier
.bndprefixok
4088 && !i
.prefix
[BND_PREFIX
])
4089 add_prefix (BND_PREFIX_OPCODE
);
4091 /* Check string instruction segment overrides. */
4092 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4094 if (!check_string ())
4096 i
.disp_operands
= 0;
4099 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4100 optimize_encoding ();
4102 if (!process_suffix ())
4105 /* Update operand types. */
4106 for (j
= 0; j
< i
.operands
; j
++)
4107 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4109 /* Make still unresolved immediate matches conform to size of immediate
4110 given in i.suffix. */
4111 if (!finalize_imm ())
4114 if (i
.types
[0].bitfield
.imm1
)
4115 i
.imm_operands
= 0; /* kludge for shift insns. */
4117 /* We only need to check those implicit registers for instructions
4118 with 3 operands or less. */
4119 if (i
.operands
<= 3)
4120 for (j
= 0; j
< i
.operands
; j
++)
4121 if (i
.types
[j
].bitfield
.inoutportreg
4122 || i
.types
[j
].bitfield
.shiftcount
4123 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4126 /* ImmExt should be processed after SSE2AVX. */
4127 if (!i
.tm
.opcode_modifier
.sse2avx
4128 && i
.tm
.opcode_modifier
.immext
)
4131 /* For insns with operands there are more diddles to do to the opcode. */
4134 if (!process_operands ())
4137 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4139 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4140 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4143 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
4145 if (flag_code
== CODE_16BIT
)
4147 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4152 if (i
.tm
.opcode_modifier
.vex
)
4153 build_vex_prefix (t
);
4155 build_evex_prefix ();
4158 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4159 instructions may define INT_OPCODE as well, so avoid this corner
4160 case for those instructions that use MODRM. */
4161 if (i
.tm
.base_opcode
== INT_OPCODE
4162 && !i
.tm
.opcode_modifier
.modrm
4163 && i
.op
[0].imms
->X_add_number
== 3)
4165 i
.tm
.base_opcode
= INT3_OPCODE
;
4169 if ((i
.tm
.opcode_modifier
.jump
4170 || i
.tm
.opcode_modifier
.jumpbyte
4171 || i
.tm
.opcode_modifier
.jumpdword
)
4172 && i
.op
[0].disps
->X_op
== O_constant
)
4174 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4175 the absolute address given by the constant. Since ix86 jumps and
4176 calls are pc relative, we need to generate a reloc. */
4177 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4178 i
.op
[0].disps
->X_op
= O_symbol
;
4181 if (i
.tm
.opcode_modifier
.rex64
)
4184 /* For 8 bit registers we need an empty rex prefix. Also if the
4185 instruction already has a prefix, we need to convert old
4186 registers to new ones. */
4188 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4189 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4190 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4191 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4192 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4193 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4198 i
.rex
|= REX_OPCODE
;
4199 for (x
= 0; x
< 2; x
++)
4201 /* Look for 8 bit operand that uses old registers. */
4202 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4203 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4205 /* In case it is "hi" register, give up. */
4206 if (i
.op
[x
].regs
->reg_num
> 3)
4207 as_bad (_("can't encode register '%s%s' in an "
4208 "instruction requiring REX prefix."),
4209 register_prefix
, i
.op
[x
].regs
->reg_name
);
4211 /* Otherwise it is equivalent to the extended register.
4212 Since the encoding doesn't change this is merely
4213 cosmetic cleanup for debug output. */
4215 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4220 if (i
.rex
== 0 && i
.rex_encoding
)
4222 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4223 that uses legacy register. If it is "hi" register, don't add
4224 the REX_OPCODE byte. */
4226 for (x
= 0; x
< 2; x
++)
4227 if (i
.types
[x
].bitfield
.reg
4228 && i
.types
[x
].bitfield
.byte
4229 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4230 && i
.op
[x
].regs
->reg_num
> 3)
4232 i
.rex_encoding
= FALSE
;
4241 add_prefix (REX_OPCODE
| i
.rex
);
4243 /* We are ready to output the insn. */
4248 parse_insn (char *line
, char *mnemonic
)
4251 char *token_start
= l
;
4254 const insn_template
*t
;
4260 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4265 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4267 as_bad (_("no such instruction: `%s'"), token_start
);
4272 if (!is_space_char (*l
)
4273 && *l
!= END_OF_INSN
4275 || (*l
!= PREFIX_SEPARATOR
4278 as_bad (_("invalid character %s in mnemonic"),
4279 output_invalid (*l
));
4282 if (token_start
== l
)
4284 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4285 as_bad (_("expecting prefix; got nothing"));
4287 as_bad (_("expecting mnemonic; got nothing"));
4291 /* Look up instruction (or prefix) via hash table. */
4292 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4294 if (*l
!= END_OF_INSN
4295 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4296 && current_templates
4297 && current_templates
->start
->opcode_modifier
.isprefix
)
4299 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4301 as_bad ((flag_code
!= CODE_64BIT
4302 ? _("`%s' is only supported in 64-bit mode")
4303 : _("`%s' is not supported in 64-bit mode")),
4304 current_templates
->start
->name
);
4307 /* If we are in 16-bit mode, do not allow addr16 or data16.
4308 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4309 if ((current_templates
->start
->opcode_modifier
.size16
4310 || current_templates
->start
->opcode_modifier
.size32
)
4311 && flag_code
!= CODE_64BIT
4312 && (current_templates
->start
->opcode_modifier
.size32
4313 ^ (flag_code
== CODE_16BIT
)))
4315 as_bad (_("redundant %s prefix"),
4316 current_templates
->start
->name
);
4319 if (current_templates
->start
->opcode_length
== 0)
4321 /* Handle pseudo prefixes. */
4322 switch (current_templates
->start
->base_opcode
)
4326 i
.disp_encoding
= disp_encoding_8bit
;
4330 i
.disp_encoding
= disp_encoding_32bit
;
4334 i
.dir_encoding
= dir_encoding_load
;
4338 i
.dir_encoding
= dir_encoding_store
;
4342 i
.vec_encoding
= vex_encoding_vex2
;
4346 i
.vec_encoding
= vex_encoding_vex3
;
4350 i
.vec_encoding
= vex_encoding_evex
;
4354 i
.rex_encoding
= TRUE
;
4358 i
.no_optimize
= TRUE
;
4366 /* Add prefix, checking for repeated prefixes. */
4367 switch (add_prefix (current_templates
->start
->base_opcode
))
4372 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4373 i
.notrack_prefix
= current_templates
->start
->name
;
4376 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4377 i
.hle_prefix
= current_templates
->start
->name
;
4378 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4379 i
.bnd_prefix
= current_templates
->start
->name
;
4381 i
.rep_prefix
= current_templates
->start
->name
;
4387 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4394 if (!current_templates
)
4396 /* Check if we should swap operand or force 32bit displacement in
4398 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4399 i
.dir_encoding
= dir_encoding_store
;
4400 else if (mnem_p
- 3 == dot_p
4403 i
.disp_encoding
= disp_encoding_8bit
;
4404 else if (mnem_p
- 4 == dot_p
4408 i
.disp_encoding
= disp_encoding_32bit
;
4413 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4416 if (!current_templates
)
4419 /* See if we can get a match by trimming off a suffix. */
4422 case WORD_MNEM_SUFFIX
:
4423 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4424 i
.suffix
= SHORT_MNEM_SUFFIX
;
4427 case BYTE_MNEM_SUFFIX
:
4428 case QWORD_MNEM_SUFFIX
:
4429 i
.suffix
= mnem_p
[-1];
4431 current_templates
= (const templates
*) hash_find (op_hash
,
4434 case SHORT_MNEM_SUFFIX
:
4435 case LONG_MNEM_SUFFIX
:
4438 i
.suffix
= mnem_p
[-1];
4440 current_templates
= (const templates
*) hash_find (op_hash
,
4449 if (intel_float_operand (mnemonic
) == 1)
4450 i
.suffix
= SHORT_MNEM_SUFFIX
;
4452 i
.suffix
= LONG_MNEM_SUFFIX
;
4454 current_templates
= (const templates
*) hash_find (op_hash
,
4459 if (!current_templates
)
4461 as_bad (_("no such instruction: `%s'"), token_start
);
4466 if (current_templates
->start
->opcode_modifier
.jump
4467 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4469 /* Check for a branch hint. We allow ",pt" and ",pn" for
4470 predict taken and predict not taken respectively.
4471 I'm not sure that branch hints actually do anything on loop
4472 and jcxz insns (JumpByte) for current Pentium4 chips. They
4473 may work in the future and it doesn't hurt to accept them
4475 if (l
[0] == ',' && l
[1] == 'p')
4479 if (!add_prefix (DS_PREFIX_OPCODE
))
4483 else if (l
[2] == 'n')
4485 if (!add_prefix (CS_PREFIX_OPCODE
))
4491 /* Any other comma loses. */
4494 as_bad (_("invalid character %s in mnemonic"),
4495 output_invalid (*l
));
4499 /* Check if instruction is supported on specified architecture. */
4501 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4503 supported
|= cpu_flags_match (t
);
4504 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4508 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4510 as_bad (flag_code
== CODE_64BIT
4511 ? _("`%s' is not supported in 64-bit mode")
4512 : _("`%s' is only supported in 64-bit mode"),
4513 current_templates
->start
->name
);
4516 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
4518 as_bad (_("`%s' is not supported on `%s%s'"),
4519 current_templates
->start
->name
,
4520 cpu_arch_name
? cpu_arch_name
: default_arch
,
4521 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4526 if (!cpu_arch_flags
.bitfield
.cpui386
4527 && (flag_code
!= CODE_16BIT
))
4529 as_warn (_("use .code16 to ensure correct addressing mode"));
4536 parse_operands (char *l
, const char *mnemonic
)
4540 /* 1 if operand is pending after ','. */
4541 unsigned int expecting_operand
= 0;
4543 /* Non-zero if operand parens not balanced. */
4544 unsigned int paren_not_balanced
;
4546 while (*l
!= END_OF_INSN
)
4548 /* Skip optional white space before operand. */
4549 if (is_space_char (*l
))
4551 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4553 as_bad (_("invalid character %s before operand %d"),
4554 output_invalid (*l
),
4558 token_start
= l
; /* After white space. */
4559 paren_not_balanced
= 0;
4560 while (paren_not_balanced
|| *l
!= ',')
4562 if (*l
== END_OF_INSN
)
4564 if (paren_not_balanced
)
4567 as_bad (_("unbalanced parenthesis in operand %d."),
4570 as_bad (_("unbalanced brackets in operand %d."),
4575 break; /* we are done */
4577 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4579 as_bad (_("invalid character %s in operand %d"),
4580 output_invalid (*l
),
4587 ++paren_not_balanced
;
4589 --paren_not_balanced
;
4594 ++paren_not_balanced
;
4596 --paren_not_balanced
;
4600 if (l
!= token_start
)
4601 { /* Yes, we've read in another operand. */
4602 unsigned int operand_ok
;
4603 this_operand
= i
.operands
++;
4604 if (i
.operands
> MAX_OPERANDS
)
4606 as_bad (_("spurious operands; (%d operands/instruction max)"),
4610 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4611 /* Now parse operand adding info to 'i' as we go along. */
4612 END_STRING_AND_SAVE (l
);
4616 i386_intel_operand (token_start
,
4617 intel_float_operand (mnemonic
));
4619 operand_ok
= i386_att_operand (token_start
);
4621 RESTORE_END_STRING (l
);
4627 if (expecting_operand
)
4629 expecting_operand_after_comma
:
4630 as_bad (_("expecting operand after ','; got nothing"));
4635 as_bad (_("expecting operand before ','; got nothing"));
4640 /* Now *l must be either ',' or END_OF_INSN. */
4643 if (*++l
== END_OF_INSN
)
4645 /* Just skip it, if it's \n complain. */
4646 goto expecting_operand_after_comma
;
4648 expecting_operand
= 1;
4655 swap_2_operands (int xchg1
, int xchg2
)
4657 union i386_op temp_op
;
4658 i386_operand_type temp_type
;
4659 enum bfd_reloc_code_real temp_reloc
;
4661 temp_type
= i
.types
[xchg2
];
4662 i
.types
[xchg2
] = i
.types
[xchg1
];
4663 i
.types
[xchg1
] = temp_type
;
4664 temp_op
= i
.op
[xchg2
];
4665 i
.op
[xchg2
] = i
.op
[xchg1
];
4666 i
.op
[xchg1
] = temp_op
;
4667 temp_reloc
= i
.reloc
[xchg2
];
4668 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4669 i
.reloc
[xchg1
] = temp_reloc
;
4673 if (i
.mask
->operand
== xchg1
)
4674 i
.mask
->operand
= xchg2
;
4675 else if (i
.mask
->operand
== xchg2
)
4676 i
.mask
->operand
= xchg1
;
4680 if (i
.broadcast
->operand
== xchg1
)
4681 i
.broadcast
->operand
= xchg2
;
4682 else if (i
.broadcast
->operand
== xchg2
)
4683 i
.broadcast
->operand
= xchg1
;
4687 if (i
.rounding
->operand
== xchg1
)
4688 i
.rounding
->operand
= xchg2
;
4689 else if (i
.rounding
->operand
== xchg2
)
4690 i
.rounding
->operand
= xchg1
;
4695 swap_operands (void)
4701 swap_2_operands (1, i
.operands
- 2);
4705 swap_2_operands (0, i
.operands
- 1);
4711 if (i
.mem_operands
== 2)
4713 const seg_entry
*temp_seg
;
4714 temp_seg
= i
.seg
[0];
4715 i
.seg
[0] = i
.seg
[1];
4716 i
.seg
[1] = temp_seg
;
4720 /* Try to ensure constant immediates are represented in the smallest
4725 char guess_suffix
= 0;
4729 guess_suffix
= i
.suffix
;
4730 else if (i
.reg_operands
)
4732 /* Figure out a suffix from the last register operand specified.
4733 We can't do this properly yet, ie. excluding InOutPortReg,
4734 but the following works for instructions with immediates.
4735 In any case, we can't set i.suffix yet. */
4736 for (op
= i
.operands
; --op
>= 0;)
4737 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
4739 guess_suffix
= BYTE_MNEM_SUFFIX
;
4742 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
4744 guess_suffix
= WORD_MNEM_SUFFIX
;
4747 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
4749 guess_suffix
= LONG_MNEM_SUFFIX
;
4752 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
4754 guess_suffix
= QWORD_MNEM_SUFFIX
;
4758 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4759 guess_suffix
= WORD_MNEM_SUFFIX
;
4761 for (op
= i
.operands
; --op
>= 0;)
4762 if (operand_type_check (i
.types
[op
], imm
))
4764 switch (i
.op
[op
].imms
->X_op
)
4767 /* If a suffix is given, this operand may be shortened. */
4768 switch (guess_suffix
)
4770 case LONG_MNEM_SUFFIX
:
4771 i
.types
[op
].bitfield
.imm32
= 1;
4772 i
.types
[op
].bitfield
.imm64
= 1;
4774 case WORD_MNEM_SUFFIX
:
4775 i
.types
[op
].bitfield
.imm16
= 1;
4776 i
.types
[op
].bitfield
.imm32
= 1;
4777 i
.types
[op
].bitfield
.imm32s
= 1;
4778 i
.types
[op
].bitfield
.imm64
= 1;
4780 case BYTE_MNEM_SUFFIX
:
4781 i
.types
[op
].bitfield
.imm8
= 1;
4782 i
.types
[op
].bitfield
.imm8s
= 1;
4783 i
.types
[op
].bitfield
.imm16
= 1;
4784 i
.types
[op
].bitfield
.imm32
= 1;
4785 i
.types
[op
].bitfield
.imm32s
= 1;
4786 i
.types
[op
].bitfield
.imm64
= 1;
4790 /* If this operand is at most 16 bits, convert it
4791 to a signed 16 bit number before trying to see
4792 whether it will fit in an even smaller size.
4793 This allows a 16-bit operand such as $0xffe0 to
4794 be recognised as within Imm8S range. */
4795 if ((i
.types
[op
].bitfield
.imm16
)
4796 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4798 i
.op
[op
].imms
->X_add_number
=
4799 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4802 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4803 if ((i
.types
[op
].bitfield
.imm32
)
4804 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4807 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4808 ^ ((offsetT
) 1 << 31))
4809 - ((offsetT
) 1 << 31));
4813 = operand_type_or (i
.types
[op
],
4814 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4816 /* We must avoid matching of Imm32 templates when 64bit
4817 only immediate is available. */
4818 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4819 i
.types
[op
].bitfield
.imm32
= 0;
4826 /* Symbols and expressions. */
4828 /* Convert symbolic operand to proper sizes for matching, but don't
4829 prevent matching a set of insns that only supports sizes other
4830 than those matching the insn suffix. */
4832 i386_operand_type mask
, allowed
;
4833 const insn_template
*t
;
4835 operand_type_set (&mask
, 0);
4836 operand_type_set (&allowed
, 0);
4838 for (t
= current_templates
->start
;
4839 t
< current_templates
->end
;
4841 allowed
= operand_type_or (allowed
,
4842 t
->operand_types
[op
]);
4843 switch (guess_suffix
)
4845 case QWORD_MNEM_SUFFIX
:
4846 mask
.bitfield
.imm64
= 1;
4847 mask
.bitfield
.imm32s
= 1;
4849 case LONG_MNEM_SUFFIX
:
4850 mask
.bitfield
.imm32
= 1;
4852 case WORD_MNEM_SUFFIX
:
4853 mask
.bitfield
.imm16
= 1;
4855 case BYTE_MNEM_SUFFIX
:
4856 mask
.bitfield
.imm8
= 1;
4861 allowed
= operand_type_and (mask
, allowed
);
4862 if (!operand_type_all_zero (&allowed
))
4863 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4870 /* Try to use the smallest displacement type too. */
4872 optimize_disp (void)
4876 for (op
= i
.operands
; --op
>= 0;)
4877 if (operand_type_check (i
.types
[op
], disp
))
4879 if (i
.op
[op
].disps
->X_op
== O_constant
)
4881 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4883 if (i
.types
[op
].bitfield
.disp16
4884 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4886 /* If this operand is at most 16 bits, convert
4887 to a signed 16 bit number and don't use 64bit
4889 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4890 i
.types
[op
].bitfield
.disp64
= 0;
4893 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4894 if (i
.types
[op
].bitfield
.disp32
4895 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4897 /* If this operand is at most 32 bits, convert
4898 to a signed 32 bit number and don't use 64bit
4900 op_disp
&= (((offsetT
) 2 << 31) - 1);
4901 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4902 i
.types
[op
].bitfield
.disp64
= 0;
4905 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4907 i
.types
[op
].bitfield
.disp8
= 0;
4908 i
.types
[op
].bitfield
.disp16
= 0;
4909 i
.types
[op
].bitfield
.disp32
= 0;
4910 i
.types
[op
].bitfield
.disp32s
= 0;
4911 i
.types
[op
].bitfield
.disp64
= 0;
4915 else if (flag_code
== CODE_64BIT
)
4917 if (fits_in_signed_long (op_disp
))
4919 i
.types
[op
].bitfield
.disp64
= 0;
4920 i
.types
[op
].bitfield
.disp32s
= 1;
4922 if (i
.prefix
[ADDR_PREFIX
]
4923 && fits_in_unsigned_long (op_disp
))
4924 i
.types
[op
].bitfield
.disp32
= 1;
4926 if ((i
.types
[op
].bitfield
.disp32
4927 || i
.types
[op
].bitfield
.disp32s
4928 || i
.types
[op
].bitfield
.disp16
)
4929 && fits_in_disp8 (op_disp
))
4930 i
.types
[op
].bitfield
.disp8
= 1;
4932 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4933 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4935 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4936 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4937 i
.types
[op
].bitfield
.disp8
= 0;
4938 i
.types
[op
].bitfield
.disp16
= 0;
4939 i
.types
[op
].bitfield
.disp32
= 0;
4940 i
.types
[op
].bitfield
.disp32s
= 0;
4941 i
.types
[op
].bitfield
.disp64
= 0;
4944 /* We only support 64bit displacement on constants. */
4945 i
.types
[op
].bitfield
.disp64
= 0;
4949 /* Check if operands are valid for the instruction. */
4952 check_VecOperands (const insn_template
*t
)
4956 /* Without VSIB byte, we can't have a vector register for index. */
4957 if (!t
->opcode_modifier
.vecsib
4959 && (i
.index_reg
->reg_type
.bitfield
.xmmword
4960 || i
.index_reg
->reg_type
.bitfield
.ymmword
4961 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
4963 i
.error
= unsupported_vector_index_register
;
4967 /* Check if default mask is allowed. */
4968 if (t
->opcode_modifier
.nodefmask
4969 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4971 i
.error
= no_default_mask
;
4975 /* For VSIB byte, we need a vector register for index, and all vector
4976 registers must be distinct. */
4977 if (t
->opcode_modifier
.vecsib
)
4980 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4981 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
4982 || (t
->opcode_modifier
.vecsib
== VecSIB256
4983 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
4984 || (t
->opcode_modifier
.vecsib
== VecSIB512
4985 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
4987 i
.error
= invalid_vsib_address
;
4991 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4992 if (i
.reg_operands
== 2 && !i
.mask
)
4994 gas_assert (i
.types
[0].bitfield
.regsimd
);
4995 gas_assert (i
.types
[0].bitfield
.xmmword
4996 || i
.types
[0].bitfield
.ymmword
);
4997 gas_assert (i
.types
[2].bitfield
.regsimd
);
4998 gas_assert (i
.types
[2].bitfield
.xmmword
4999 || i
.types
[2].bitfield
.ymmword
);
5000 if (operand_check
== check_none
)
5002 if (register_number (i
.op
[0].regs
)
5003 != register_number (i
.index_reg
)
5004 && register_number (i
.op
[2].regs
)
5005 != register_number (i
.index_reg
)
5006 && register_number (i
.op
[0].regs
)
5007 != register_number (i
.op
[2].regs
))
5009 if (operand_check
== check_error
)
5011 i
.error
= invalid_vector_register_set
;
5014 as_warn (_("mask, index, and destination registers should be distinct"));
5016 else if (i
.reg_operands
== 1 && i
.mask
)
5018 if (i
.types
[1].bitfield
.regsimd
5019 && (i
.types
[1].bitfield
.xmmword
5020 || i
.types
[1].bitfield
.ymmword
5021 || i
.types
[1].bitfield
.zmmword
)
5022 && (register_number (i
.op
[1].regs
)
5023 == register_number (i
.index_reg
)))
5025 if (operand_check
== check_error
)
5027 i
.error
= invalid_vector_register_set
;
5030 if (operand_check
!= check_none
)
5031 as_warn (_("index and destination registers should be distinct"));
5036 /* Check if broadcast is supported by the instruction and is applied
5037 to the memory operand. */
5040 int broadcasted_opnd_size
;
5042 /* Check if specified broadcast is supported in this instruction,
5043 and it's applied to memory operand of DWORD or QWORD type,
5044 depending on VecESize. */
5045 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
5046 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
5047 || (t
->opcode_modifier
.vecesize
== 0
5048 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
5049 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
5050 || (t
->opcode_modifier
.vecesize
== 1
5051 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
5052 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
5055 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
5056 if (i
.broadcast
->type
== BROADCAST_1TO16
)
5057 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
5058 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
5059 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
5060 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
5061 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
5062 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
5063 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
5067 if ((broadcasted_opnd_size
== 256
5068 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
5069 || (broadcasted_opnd_size
== 512
5070 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
5073 i
.error
= unsupported_broadcast
;
5077 /* If broadcast is supported in this instruction, we need to check if
5078 operand of one-element size isn't specified without broadcast. */
5079 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5081 /* Find memory operand. */
5082 for (op
= 0; op
< i
.operands
; op
++)
5083 if (operand_type_check (i
.types
[op
], anymem
))
5085 gas_assert (op
< i
.operands
);
5086 /* Check size of the memory operand. */
5087 if ((t
->opcode_modifier
.vecesize
== 0
5088 && i
.types
[op
].bitfield
.dword
)
5089 || (t
->opcode_modifier
.vecesize
== 1
5090 && i
.types
[op
].bitfield
.qword
))
5092 i
.error
= broadcast_needed
;
5097 /* Check if requested masking is supported. */
5099 && (!t
->opcode_modifier
.masking
5101 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
5103 i
.error
= unsupported_masking
;
5107 /* Check if masking is applied to dest operand. */
5108 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5110 i
.error
= mask_not_on_destination
;
5117 if ((i
.rounding
->type
!= saeonly
5118 && !t
->opcode_modifier
.staticrounding
)
5119 || (i
.rounding
->type
== saeonly
5120 && (t
->opcode_modifier
.staticrounding
5121 || !t
->opcode_modifier
.sae
)))
5123 i
.error
= unsupported_rc_sae
;
5126 /* If the instruction has several immediate operands and one of
5127 them is rounding, the rounding operand should be the last
5128 immediate operand. */
5129 if (i
.imm_operands
> 1
5130 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5132 i
.error
= rc_sae_operand_not_last_imm
;
5137 /* Check vector Disp8 operand. */
5138 if (t
->opcode_modifier
.disp8memshift
5139 && i
.disp_encoding
!= disp_encoding_32bit
)
5142 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
5144 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5146 for (op
= 0; op
< i
.operands
; op
++)
5147 if (operand_type_check (i
.types
[op
], disp
)
5148 && i
.op
[op
].disps
->X_op
== O_constant
)
5150 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5152 i
.types
[op
].bitfield
.disp8
= 1;
5155 i
.types
[op
].bitfield
.disp8
= 0;
5164 /* Check if operands are valid for the instruction. Update VEX
5168 VEX_check_operands (const insn_template
*t
)
5170 if (i
.vec_encoding
== vex_encoding_evex
)
5172 /* This instruction must be encoded with EVEX prefix. */
5173 if (!t
->opcode_modifier
.evex
)
5175 i
.error
= unsupported
;
5181 if (!t
->opcode_modifier
.vex
)
5183 /* This instruction template doesn't have VEX prefix. */
5184 if (i
.vec_encoding
!= vex_encoding_default
)
5186 i
.error
= unsupported
;
5192 /* Only check VEX_Imm4, which must be the first operand. */
5193 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5195 if (i
.op
[0].imms
->X_op
!= O_constant
5196 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5202 /* Turn off Imm8 so that update_imm won't complain. */
5203 i
.types
[0] = vec_imm4
;
5209 static const insn_template
*
5210 match_template (char mnem_suffix
)
5212 /* Points to template once we've found it. */
5213 const insn_template
*t
;
5214 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5215 i386_operand_type overlap4
;
5216 unsigned int found_reverse_match
;
5217 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5218 i386_operand_type operand_types
[MAX_OPERANDS
];
5219 int addr_prefix_disp
;
5221 unsigned int found_cpu_match
;
5222 unsigned int check_register
;
5223 enum i386_error specific_error
= 0;
5225 #if MAX_OPERANDS != 5
5226 # error "MAX_OPERANDS must be 5."
5229 found_reverse_match
= 0;
5230 addr_prefix_disp
= -1;
5232 memset (&suffix_check
, 0, sizeof (suffix_check
));
5233 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5234 suffix_check
.no_bsuf
= 1;
5235 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5236 suffix_check
.no_wsuf
= 1;
5237 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5238 suffix_check
.no_ssuf
= 1;
5239 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5240 suffix_check
.no_lsuf
= 1;
5241 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5242 suffix_check
.no_qsuf
= 1;
5243 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5244 suffix_check
.no_ldsuf
= 1;
5246 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5249 switch (mnem_suffix
)
5251 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5252 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5253 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5254 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5255 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5259 /* Must have right number of operands. */
5260 i
.error
= number_of_operands_mismatch
;
5262 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5264 addr_prefix_disp
= -1;
5266 if (i
.operands
!= t
->operands
)
5269 /* Check processor support. */
5270 i
.error
= unsupported
;
5271 found_cpu_match
= (cpu_flags_match (t
)
5272 == CPU_FLAGS_PERFECT_MATCH
);
5273 if (!found_cpu_match
)
5276 /* Check old gcc support. */
5277 i
.error
= old_gcc_only
;
5278 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
5281 /* Check AT&T mnemonic. */
5282 i
.error
= unsupported_with_intel_mnemonic
;
5283 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5286 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5287 i
.error
= unsupported_syntax
;
5288 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5289 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5290 || (intel64
&& t
->opcode_modifier
.amd64
)
5291 || (!intel64
&& t
->opcode_modifier
.intel64
))
5294 /* Check the suffix, except for some instructions in intel mode. */
5295 i
.error
= invalid_instruction_suffix
;
5296 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5297 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5298 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5299 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5300 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5301 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5302 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5304 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5305 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5306 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5307 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5308 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5309 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5310 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5313 if (!operand_size_match (t
))
5316 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5317 operand_types
[j
] = t
->operand_types
[j
];
5319 /* In general, don't allow 64-bit operands in 32-bit mode. */
5320 if (i
.suffix
== QWORD_MNEM_SUFFIX
5321 && flag_code
!= CODE_64BIT
5323 ? (!t
->opcode_modifier
.ignoresize
5324 && !intel_float_operand (t
->name
))
5325 : intel_float_operand (t
->name
) != 2)
5326 && ((!operand_types
[0].bitfield
.regmmx
5327 && !operand_types
[0].bitfield
.regsimd
)
5328 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5329 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5330 && (t
->base_opcode
!= 0x0fc7
5331 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5334 /* In general, don't allow 32-bit operands on pre-386. */
5335 else if (i
.suffix
== LONG_MNEM_SUFFIX
5336 && !cpu_arch_flags
.bitfield
.cpui386
5338 ? (!t
->opcode_modifier
.ignoresize
5339 && !intel_float_operand (t
->name
))
5340 : intel_float_operand (t
->name
) != 2)
5341 && ((!operand_types
[0].bitfield
.regmmx
5342 && !operand_types
[0].bitfield
.regsimd
)
5343 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5344 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5347 /* Do not verify operands when there are none. */
5351 /* We've found a match; break out of loop. */
5355 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5356 into Disp32/Disp16/Disp32 operand. */
5357 if (i
.prefix
[ADDR_PREFIX
] != 0)
5359 /* There should be only one Disp operand. */
5363 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5365 if (operand_types
[j
].bitfield
.disp16
)
5367 addr_prefix_disp
= j
;
5368 operand_types
[j
].bitfield
.disp32
= 1;
5369 operand_types
[j
].bitfield
.disp16
= 0;
5375 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5377 if (operand_types
[j
].bitfield
.disp32
)
5379 addr_prefix_disp
= j
;
5380 operand_types
[j
].bitfield
.disp32
= 0;
5381 operand_types
[j
].bitfield
.disp16
= 1;
5387 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5389 if (operand_types
[j
].bitfield
.disp64
)
5391 addr_prefix_disp
= j
;
5392 operand_types
[j
].bitfield
.disp64
= 0;
5393 operand_types
[j
].bitfield
.disp32
= 1;
5401 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5402 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5405 /* We check register size if needed. */
5406 check_register
= t
->opcode_modifier
.checkregsize
;
5407 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5408 switch (t
->operands
)
5411 if (!operand_type_match (overlap0
, i
.types
[0]))
5415 /* xchg %eax, %eax is a special case. It is an alias for nop
5416 only in 32bit mode and we can use opcode 0x90. In 64bit
5417 mode, we can't use 0x90 for xchg %eax, %eax since it should
5418 zero-extend %eax to %rax. */
5419 if (flag_code
== CODE_64BIT
5420 && t
->base_opcode
== 0x90
5421 && operand_type_equal (&i
.types
[0], &acc32
)
5422 && operand_type_equal (&i
.types
[1], &acc32
))
5424 /* If we want store form, we reverse direction of operands. */
5425 if (i
.dir_encoding
== dir_encoding_store
5426 && t
->opcode_modifier
.d
)
5431 /* If we want store form, we skip the current load. */
5432 if (i
.dir_encoding
== dir_encoding_store
5433 && i
.mem_operands
== 0
5434 && t
->opcode_modifier
.load
)
5439 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5440 if (!operand_type_match (overlap0
, i
.types
[0])
5441 || !operand_type_match (overlap1
, i
.types
[1])
5443 && !operand_type_register_match (i
.types
[0],
5448 /* Check if other direction is valid ... */
5449 if (!t
->opcode_modifier
.d
)
5453 /* Try reversing direction of operands. */
5454 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
5455 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
5456 if (!operand_type_match (overlap0
, i
.types
[0])
5457 || !operand_type_match (overlap1
, i
.types
[1])
5459 && !operand_type_register_match (i
.types
[0],
5464 /* Does not match either direction. */
5467 /* found_reverse_match holds which of D or FloatR
5469 if (!t
->opcode_modifier
.d
)
5470 found_reverse_match
= 0;
5471 else if (operand_types
[0].bitfield
.tbyte
)
5472 found_reverse_match
= Opcode_FloatD
;
5474 found_reverse_match
= Opcode_D
;
5475 if (t
->opcode_modifier
.floatr
)
5476 found_reverse_match
|= Opcode_FloatR
;
5480 /* Found a forward 2 operand match here. */
5481 switch (t
->operands
)
5484 overlap4
= operand_type_and (i
.types
[4],
5488 overlap3
= operand_type_and (i
.types
[3],
5492 overlap2
= operand_type_and (i
.types
[2],
5497 switch (t
->operands
)
5500 if (!operand_type_match (overlap4
, i
.types
[4])
5501 || !operand_type_register_match (i
.types
[3],
5508 if (!operand_type_match (overlap3
, i
.types
[3])
5510 && !operand_type_register_match (i
.types
[2],
5517 /* Here we make use of the fact that there are no
5518 reverse match 3 operand instructions, and all 3
5519 operand instructions only need to be checked for
5520 register consistency between operands 2 and 3. */
5521 if (!operand_type_match (overlap2
, i
.types
[2])
5523 && !operand_type_register_match (i
.types
[1],
5531 /* Found either forward/reverse 2, 3 or 4 operand match here:
5532 slip through to break. */
5534 if (!found_cpu_match
)
5536 found_reverse_match
= 0;
5540 /* Check if vector and VEX operands are valid. */
5541 if (check_VecOperands (t
) || VEX_check_operands (t
))
5543 specific_error
= i
.error
;
5547 /* We've found a match; break out of loop. */
5551 if (t
== current_templates
->end
)
5553 /* We found no match. */
5554 const char *err_msg
;
5555 switch (specific_error
? specific_error
: i
.error
)
5559 case operand_size_mismatch
:
5560 err_msg
= _("operand size mismatch");
5562 case operand_type_mismatch
:
5563 err_msg
= _("operand type mismatch");
5565 case register_type_mismatch
:
5566 err_msg
= _("register type mismatch");
5568 case number_of_operands_mismatch
:
5569 err_msg
= _("number of operands mismatch");
5571 case invalid_instruction_suffix
:
5572 err_msg
= _("invalid instruction suffix");
5575 err_msg
= _("constant doesn't fit in 4 bits");
5578 err_msg
= _("only supported with old gcc");
5580 case unsupported_with_intel_mnemonic
:
5581 err_msg
= _("unsupported with Intel mnemonic");
5583 case unsupported_syntax
:
5584 err_msg
= _("unsupported syntax");
5587 as_bad (_("unsupported instruction `%s'"),
5588 current_templates
->start
->name
);
5590 case invalid_vsib_address
:
5591 err_msg
= _("invalid VSIB address");
5593 case invalid_vector_register_set
:
5594 err_msg
= _("mask, index, and destination registers must be distinct");
5596 case unsupported_vector_index_register
:
5597 err_msg
= _("unsupported vector index register");
5599 case unsupported_broadcast
:
5600 err_msg
= _("unsupported broadcast");
5602 case broadcast_not_on_src_operand
:
5603 err_msg
= _("broadcast not on source memory operand");
5605 case broadcast_needed
:
5606 err_msg
= _("broadcast is needed for operand of such type");
5608 case unsupported_masking
:
5609 err_msg
= _("unsupported masking");
5611 case mask_not_on_destination
:
5612 err_msg
= _("mask not on destination operand");
5614 case no_default_mask
:
5615 err_msg
= _("default mask isn't allowed");
5617 case unsupported_rc_sae
:
5618 err_msg
= _("unsupported static rounding/sae");
5620 case rc_sae_operand_not_last_imm
:
5622 err_msg
= _("RC/SAE operand must precede immediate operands");
5624 err_msg
= _("RC/SAE operand must follow immediate operands");
5626 case invalid_register_operand
:
5627 err_msg
= _("invalid register operand");
5630 as_bad (_("%s for `%s'"), err_msg
,
5631 current_templates
->start
->name
);
5635 if (!quiet_warnings
)
5638 && (i
.types
[0].bitfield
.jumpabsolute
5639 != operand_types
[0].bitfield
.jumpabsolute
))
5641 as_warn (_("indirect %s without `*'"), t
->name
);
5644 if (t
->opcode_modifier
.isprefix
5645 && t
->opcode_modifier
.ignoresize
)
5647 /* Warn them that a data or address size prefix doesn't
5648 affect assembly of the next line of code. */
5649 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5653 /* Copy the template we found. */
5656 if (addr_prefix_disp
!= -1)
5657 i
.tm
.operand_types
[addr_prefix_disp
]
5658 = operand_types
[addr_prefix_disp
];
5660 if (found_reverse_match
)
5662 /* If we found a reverse match we must alter the opcode
5663 direction bit. found_reverse_match holds bits to change
5664 (different for int & float insns). */
5666 i
.tm
.base_opcode
^= found_reverse_match
;
5668 i
.tm
.operand_types
[0] = operand_types
[1];
5669 i
.tm
.operand_types
[1] = operand_types
[0];
5678 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5679 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5681 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5683 as_bad (_("`%s' operand %d must use `%ses' segment"),
5689 /* There's only ever one segment override allowed per instruction.
5690 This instruction possibly has a legal segment override on the
5691 second operand, so copy the segment to where non-string
5692 instructions store it, allowing common code. */
5693 i
.seg
[0] = i
.seg
[1];
5695 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5697 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5699 as_bad (_("`%s' operand %d must use `%ses' segment"),
5710 process_suffix (void)
5712 /* If matched instruction specifies an explicit instruction mnemonic
5714 if (i
.tm
.opcode_modifier
.size16
)
5715 i
.suffix
= WORD_MNEM_SUFFIX
;
5716 else if (i
.tm
.opcode_modifier
.size32
)
5717 i
.suffix
= LONG_MNEM_SUFFIX
;
5718 else if (i
.tm
.opcode_modifier
.size64
)
5719 i
.suffix
= QWORD_MNEM_SUFFIX
;
5720 else if (i
.reg_operands
)
5722 /* If there's no instruction mnemonic suffix we try to invent one
5723 based on register operands. */
5726 /* We take i.suffix from the last register operand specified,
5727 Destination register type is more significant than source
5728 register type. crc32 in SSE4.2 prefers source register
5730 if (i
.tm
.base_opcode
== 0xf20f38f1)
5732 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.word
)
5733 i
.suffix
= WORD_MNEM_SUFFIX
;
5734 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.dword
)
5735 i
.suffix
= LONG_MNEM_SUFFIX
;
5736 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.qword
)
5737 i
.suffix
= QWORD_MNEM_SUFFIX
;
5739 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5741 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
5742 i
.suffix
= BYTE_MNEM_SUFFIX
;
5749 if (i
.tm
.base_opcode
== 0xf20f38f1
5750 || i
.tm
.base_opcode
== 0xf20f38f0)
5752 /* We have to know the operand size for crc32. */
5753 as_bad (_("ambiguous memory operand size for `%s`"),
5758 for (op
= i
.operands
; --op
>= 0;)
5759 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
5760 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
5762 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
5764 i
.suffix
= BYTE_MNEM_SUFFIX
;
5767 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
5769 i
.suffix
= WORD_MNEM_SUFFIX
;
5772 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
5774 i
.suffix
= LONG_MNEM_SUFFIX
;
5777 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
5779 i
.suffix
= QWORD_MNEM_SUFFIX
;
5785 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5788 && i
.tm
.opcode_modifier
.ignoresize
5789 && i
.tm
.opcode_modifier
.no_bsuf
)
5791 else if (!check_byte_reg ())
5794 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5797 && i
.tm
.opcode_modifier
.ignoresize
5798 && i
.tm
.opcode_modifier
.no_lsuf
)
5800 else if (!check_long_reg ())
5803 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5806 && i
.tm
.opcode_modifier
.ignoresize
5807 && i
.tm
.opcode_modifier
.no_qsuf
)
5809 else if (!check_qword_reg ())
5812 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5815 && i
.tm
.opcode_modifier
.ignoresize
5816 && i
.tm
.opcode_modifier
.no_wsuf
)
5818 else if (!check_word_reg ())
5821 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5822 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5823 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5825 /* Skip if the instruction has x/y/z suffix. match_template
5826 should check if it is a valid suffix. */
5828 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5829 /* Do nothing if the instruction is going to ignore the prefix. */
5834 else if (i
.tm
.opcode_modifier
.defaultsize
5836 /* exclude fldenv/frstor/fsave/fstenv */
5837 && i
.tm
.opcode_modifier
.no_ssuf
)
5839 i
.suffix
= stackop_size
;
5841 else if (intel_syntax
5843 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5844 || i
.tm
.opcode_modifier
.jumpbyte
5845 || i
.tm
.opcode_modifier
.jumpintersegment
5846 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5847 && i
.tm
.extension_opcode
<= 3)))
5852 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5854 i
.suffix
= QWORD_MNEM_SUFFIX
;
5859 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5860 i
.suffix
= LONG_MNEM_SUFFIX
;
5863 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5864 i
.suffix
= WORD_MNEM_SUFFIX
;
5873 if (i
.tm
.opcode_modifier
.w
)
5875 as_bad (_("no instruction mnemonic suffix given and "
5876 "no register operands; can't size instruction"));
5882 unsigned int suffixes
;
5884 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5885 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5887 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5889 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5891 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5893 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
5896 /* There are more than suffix matches. */
5897 if (i
.tm
.opcode_modifier
.w
5898 || ((suffixes
& (suffixes
- 1))
5899 && !i
.tm
.opcode_modifier
.defaultsize
5900 && !i
.tm
.opcode_modifier
.ignoresize
))
5902 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5908 /* Change the opcode based on the operand size given by i.suffix;
5909 We don't need to change things for byte insns. */
5912 && i
.suffix
!= BYTE_MNEM_SUFFIX
5913 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5914 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5915 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5917 /* It's not a byte, select word/dword operation. */
5918 if (i
.tm
.opcode_modifier
.w
)
5920 if (i
.tm
.opcode_modifier
.shortform
)
5921 i
.tm
.base_opcode
|= 8;
5923 i
.tm
.base_opcode
|= 1;
5926 /* Now select between word & dword operations via the operand
5927 size prefix, except for instructions that will ignore this
5929 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5931 /* The address size override prefix changes the size of the
5933 if ((flag_code
== CODE_32BIT
5934 && i
.op
->regs
[0].reg_type
.bitfield
.word
)
5935 || (flag_code
!= CODE_32BIT
5936 && i
.op
->regs
[0].reg_type
.bitfield
.dword
))
5937 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5940 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5941 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5942 && !i
.tm
.opcode_modifier
.ignoresize
5943 && !i
.tm
.opcode_modifier
.floatmf
5944 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5945 || (flag_code
== CODE_64BIT
5946 && i
.tm
.opcode_modifier
.jumpbyte
)))
5948 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5950 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5951 prefix
= ADDR_PREFIX_OPCODE
;
5953 if (!add_prefix (prefix
))
5957 /* Set mode64 for an operand. */
5958 if (i
.suffix
== QWORD_MNEM_SUFFIX
5959 && flag_code
== CODE_64BIT
5960 && !i
.tm
.opcode_modifier
.norex64
)
5962 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5963 need rex64. cmpxchg8b is also a special case. */
5964 if (! (i
.operands
== 2
5965 && i
.tm
.base_opcode
== 0x90
5966 && i
.tm
.extension_opcode
== None
5967 && operand_type_equal (&i
.types
[0], &acc64
)
5968 && operand_type_equal (&i
.types
[1], &acc64
))
5969 && ! (i
.operands
== 1
5970 && i
.tm
.base_opcode
== 0xfc7
5971 && i
.tm
.extension_opcode
== 1
5972 && !operand_type_check (i
.types
[0], reg
)
5973 && operand_type_check (i
.types
[0], anymem
)))
5977 /* Size floating point instruction. */
5978 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5979 if (i
.tm
.opcode_modifier
.floatmf
)
5980 i
.tm
.base_opcode
^= 4;
5987 check_byte_reg (void)
5991 for (op
= i
.operands
; --op
>= 0;)
5993 /* Skip non-register operands. */
5994 if (!i
.types
[op
].bitfield
.reg
)
5997 /* If this is an eight bit register, it's OK. If it's the 16 or
5998 32 bit version of an eight bit register, we will just use the
5999 low portion, and that's OK too. */
6000 if (i
.types
[op
].bitfield
.byte
)
6003 /* I/O port address operands are OK too. */
6004 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6007 /* crc32 doesn't generate this warning. */
6008 if (i
.tm
.base_opcode
== 0xf20f38f0)
6011 if ((i
.types
[op
].bitfield
.word
6012 || i
.types
[op
].bitfield
.dword
6013 || i
.types
[op
].bitfield
.qword
)
6014 && i
.op
[op
].regs
->reg_num
< 4
6015 /* Prohibit these changes in 64bit mode, since the lowering
6016 would be more complicated. */
6017 && flag_code
!= CODE_64BIT
)
6019 #if REGISTER_WARNINGS
6020 if (!quiet_warnings
)
6021 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6023 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6024 ? REGNAM_AL
- REGNAM_AX
6025 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6027 i
.op
[op
].regs
->reg_name
,
6032 /* Any other register is bad. */
6033 if (i
.types
[op
].bitfield
.reg
6034 || i
.types
[op
].bitfield
.regmmx
6035 || i
.types
[op
].bitfield
.regsimd
6036 || i
.types
[op
].bitfield
.sreg2
6037 || i
.types
[op
].bitfield
.sreg3
6038 || i
.types
[op
].bitfield
.control
6039 || i
.types
[op
].bitfield
.debug
6040 || i
.types
[op
].bitfield
.test
)
6042 as_bad (_("`%s%s' not allowed with `%s%c'"),
6044 i
.op
[op
].regs
->reg_name
,
6054 check_long_reg (void)
6058 for (op
= i
.operands
; --op
>= 0;)
6059 /* Skip non-register operands. */
6060 if (!i
.types
[op
].bitfield
.reg
)
6062 /* Reject eight bit registers, except where the template requires
6063 them. (eg. movzb) */
6064 else if (i
.types
[op
].bitfield
.byte
6065 && (i
.tm
.operand_types
[op
].bitfield
.reg
6066 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6067 && (i
.tm
.operand_types
[op
].bitfield
.word
6068 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6070 as_bad (_("`%s%s' not allowed with `%s%c'"),
6072 i
.op
[op
].regs
->reg_name
,
6077 /* Warn if the e prefix on a general reg is missing. */
6078 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6079 && i
.types
[op
].bitfield
.word
6080 && (i
.tm
.operand_types
[op
].bitfield
.reg
6081 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6082 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6084 /* Prohibit these changes in the 64bit mode, since the
6085 lowering is more complicated. */
6086 if (flag_code
== CODE_64BIT
)
6088 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6089 register_prefix
, i
.op
[op
].regs
->reg_name
,
6093 #if REGISTER_WARNINGS
6094 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6096 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6097 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6100 /* Warn if the r prefix on a general reg is present. */
6101 else if (i
.types
[op
].bitfield
.qword
6102 && (i
.tm
.operand_types
[op
].bitfield
.reg
6103 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6104 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6107 && i
.tm
.opcode_modifier
.toqword
6108 && !i
.types
[0].bitfield
.regsimd
)
6110 /* Convert to QWORD. We want REX byte. */
6111 i
.suffix
= QWORD_MNEM_SUFFIX
;
6115 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6116 register_prefix
, i
.op
[op
].regs
->reg_name
,
6125 check_qword_reg (void)
6129 for (op
= i
.operands
; --op
>= 0; )
6130 /* Skip non-register operands. */
6131 if (!i
.types
[op
].bitfield
.reg
)
6133 /* Reject eight bit registers, except where the template requires
6134 them. (eg. movzb) */
6135 else if (i
.types
[op
].bitfield
.byte
6136 && (i
.tm
.operand_types
[op
].bitfield
.reg
6137 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6138 && (i
.tm
.operand_types
[op
].bitfield
.word
6139 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6141 as_bad (_("`%s%s' not allowed with `%s%c'"),
6143 i
.op
[op
].regs
->reg_name
,
6148 /* Warn if the r prefix on a general reg is missing. */
6149 else if ((i
.types
[op
].bitfield
.word
6150 || i
.types
[op
].bitfield
.dword
)
6151 && (i
.tm
.operand_types
[op
].bitfield
.reg
6152 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6153 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6155 /* Prohibit these changes in the 64bit mode, since the
6156 lowering is more complicated. */
6158 && i
.tm
.opcode_modifier
.todword
6159 && !i
.types
[0].bitfield
.regsimd
)
6161 /* Convert to DWORD. We don't want REX byte. */
6162 i
.suffix
= LONG_MNEM_SUFFIX
;
6166 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6167 register_prefix
, i
.op
[op
].regs
->reg_name
,
6176 check_word_reg (void)
6179 for (op
= i
.operands
; --op
>= 0;)
6180 /* Skip non-register operands. */
6181 if (!i
.types
[op
].bitfield
.reg
)
6183 /* Reject eight bit registers, except where the template requires
6184 them. (eg. movzb) */
6185 else if (i
.types
[op
].bitfield
.byte
6186 && (i
.tm
.operand_types
[op
].bitfield
.reg
6187 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6188 && (i
.tm
.operand_types
[op
].bitfield
.word
6189 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6191 as_bad (_("`%s%s' not allowed with `%s%c'"),
6193 i
.op
[op
].regs
->reg_name
,
6198 /* Warn if the e or r prefix on a general reg is present. */
6199 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6200 && (i
.types
[op
].bitfield
.dword
6201 || i
.types
[op
].bitfield
.qword
)
6202 && (i
.tm
.operand_types
[op
].bitfield
.reg
6203 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6204 && i
.tm
.operand_types
[op
].bitfield
.word
)
6206 /* Prohibit these changes in the 64bit mode, since the
6207 lowering is more complicated. */
6208 if (flag_code
== CODE_64BIT
)
6210 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6211 register_prefix
, i
.op
[op
].regs
->reg_name
,
6215 #if REGISTER_WARNINGS
6216 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6218 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6219 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6226 update_imm (unsigned int j
)
6228 i386_operand_type overlap
= i
.types
[j
];
6229 if ((overlap
.bitfield
.imm8
6230 || overlap
.bitfield
.imm8s
6231 || overlap
.bitfield
.imm16
6232 || overlap
.bitfield
.imm32
6233 || overlap
.bitfield
.imm32s
6234 || overlap
.bitfield
.imm64
)
6235 && !operand_type_equal (&overlap
, &imm8
)
6236 && !operand_type_equal (&overlap
, &imm8s
)
6237 && !operand_type_equal (&overlap
, &imm16
)
6238 && !operand_type_equal (&overlap
, &imm32
)
6239 && !operand_type_equal (&overlap
, &imm32s
)
6240 && !operand_type_equal (&overlap
, &imm64
))
6244 i386_operand_type temp
;
6246 operand_type_set (&temp
, 0);
6247 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6249 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6250 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6252 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6253 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6254 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6256 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6257 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6260 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6263 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6264 || operand_type_equal (&overlap
, &imm16_32
)
6265 || operand_type_equal (&overlap
, &imm16_32s
))
6267 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6272 if (!operand_type_equal (&overlap
, &imm8
)
6273 && !operand_type_equal (&overlap
, &imm8s
)
6274 && !operand_type_equal (&overlap
, &imm16
)
6275 && !operand_type_equal (&overlap
, &imm32
)
6276 && !operand_type_equal (&overlap
, &imm32s
)
6277 && !operand_type_equal (&overlap
, &imm64
))
6279 as_bad (_("no instruction mnemonic suffix given; "
6280 "can't determine immediate size"));
6284 i
.types
[j
] = overlap
;
6294 /* Update the first 2 immediate operands. */
6295 n
= i
.operands
> 2 ? 2 : i
.operands
;
6298 for (j
= 0; j
< n
; j
++)
6299 if (update_imm (j
) == 0)
6302 /* The 3rd operand can't be immediate operand. */
6303 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6310 process_operands (void)
6312 /* Default segment register this instruction will use for memory
6313 accesses. 0 means unknown. This is only for optimizing out
6314 unnecessary segment overrides. */
6315 const seg_entry
*default_seg
= 0;
6317 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6319 unsigned int dupl
= i
.operands
;
6320 unsigned int dest
= dupl
- 1;
6323 /* The destination must be an xmm register. */
6324 gas_assert (i
.reg_operands
6325 && MAX_OPERANDS
> dupl
6326 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6328 if (i
.tm
.operand_types
[0].bitfield
.acc
6329 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6331 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6333 /* Keep xmm0 for instructions with VEX prefix and 3
6335 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6336 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6341 /* We remove the first xmm0 and keep the number of
6342 operands unchanged, which in fact duplicates the
6344 for (j
= 1; j
< i
.operands
; j
++)
6346 i
.op
[j
- 1] = i
.op
[j
];
6347 i
.types
[j
- 1] = i
.types
[j
];
6348 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6352 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6354 gas_assert ((MAX_OPERANDS
- 1) > dupl
6355 && (i
.tm
.opcode_modifier
.vexsources
6358 /* Add the implicit xmm0 for instructions with VEX prefix
6360 for (j
= i
.operands
; j
> 0; j
--)
6362 i
.op
[j
] = i
.op
[j
- 1];
6363 i
.types
[j
] = i
.types
[j
- 1];
6364 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6367 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6368 i
.types
[0] = regxmm
;
6369 i
.tm
.operand_types
[0] = regxmm
;
6372 i
.reg_operands
+= 2;
6377 i
.op
[dupl
] = i
.op
[dest
];
6378 i
.types
[dupl
] = i
.types
[dest
];
6379 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6388 i
.op
[dupl
] = i
.op
[dest
];
6389 i
.types
[dupl
] = i
.types
[dest
];
6390 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6393 if (i
.tm
.opcode_modifier
.immext
)
6396 else if (i
.tm
.operand_types
[0].bitfield
.acc
6397 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6401 for (j
= 1; j
< i
.operands
; j
++)
6403 i
.op
[j
- 1] = i
.op
[j
];
6404 i
.types
[j
- 1] = i
.types
[j
];
6406 /* We need to adjust fields in i.tm since they are used by
6407 build_modrm_byte. */
6408 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6415 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6417 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6419 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6420 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6421 regnum
= register_number (i
.op
[1].regs
);
6422 first_reg_in_group
= regnum
& ~3;
6423 last_reg_in_group
= first_reg_in_group
+ 3;
6424 if (regnum
!= first_reg_in_group
)
6425 as_warn (_("source register `%s%s' implicitly denotes"
6426 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6427 register_prefix
, i
.op
[1].regs
->reg_name
,
6428 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6429 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6432 else if (i
.tm
.opcode_modifier
.regkludge
)
6434 /* The imul $imm, %reg instruction is converted into
6435 imul $imm, %reg, %reg, and the clr %reg instruction
6436 is converted into xor %reg, %reg. */
6438 unsigned int first_reg_op
;
6440 if (operand_type_check (i
.types
[0], reg
))
6444 /* Pretend we saw the extra register operand. */
6445 gas_assert (i
.reg_operands
== 1
6446 && i
.op
[first_reg_op
+ 1].regs
== 0);
6447 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6448 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6453 if (i
.tm
.opcode_modifier
.shortform
)
6455 if (i
.types
[0].bitfield
.sreg2
6456 || i
.types
[0].bitfield
.sreg3
)
6458 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6459 && i
.op
[0].regs
->reg_num
== 1)
6461 as_bad (_("you can't `pop %scs'"), register_prefix
);
6464 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6465 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6470 /* The register or float register operand is in operand
6474 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
6475 || operand_type_check (i
.types
[0], reg
))
6479 /* Register goes in low 3 bits of opcode. */
6480 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6481 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6483 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6485 /* Warn about some common errors, but press on regardless.
6486 The first case can be generated by gcc (<= 2.8.1). */
6487 if (i
.operands
== 2)
6489 /* Reversed arguments on faddp, fsubp, etc. */
6490 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6491 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6492 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6496 /* Extraneous `l' suffix on fp insn. */
6497 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6498 register_prefix
, i
.op
[0].regs
->reg_name
);
6503 else if (i
.tm
.opcode_modifier
.modrm
)
6505 /* The opcode is completed (modulo i.tm.extension_opcode which
6506 must be put into the modrm byte). Now, we make the modrm and
6507 index base bytes based on all the info we've collected. */
6509 default_seg
= build_modrm_byte ();
6511 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6515 else if (i
.tm
.opcode_modifier
.isstring
)
6517 /* For the string instructions that allow a segment override
6518 on one of their operands, the default segment is ds. */
6522 if (i
.tm
.base_opcode
== 0x8d /* lea */
6525 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6527 /* If a segment was explicitly specified, and the specified segment
6528 is not the default, use an opcode prefix to select it. If we
6529 never figured out what the default segment is, then default_seg
6530 will be zero at this point, and the specified segment prefix will
6532 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6534 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6540 static const seg_entry
*
6541 build_modrm_byte (void)
6543 const seg_entry
*default_seg
= 0;
6544 unsigned int source
, dest
;
6547 /* The first operand of instructions with VEX prefix and 3 sources
6548 must be VEX_Imm4. */
6549 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6552 unsigned int nds
, reg_slot
;
6555 if (i
.tm
.opcode_modifier
.veximmext
6556 && i
.tm
.opcode_modifier
.immext
)
6558 dest
= i
.operands
- 2;
6559 gas_assert (dest
== 3);
6562 dest
= i
.operands
- 1;
6565 /* There are 2 kinds of instructions:
6566 1. 5 operands: 4 register operands or 3 register operands
6567 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6568 VexW0 or VexW1. The destination must be either XMM, YMM or
6570 2. 4 operands: 4 register operands or 3 register operands
6571 plus 1 memory operand, VexXDS, and VexImmExt */
6572 gas_assert ((i
.reg_operands
== 4
6573 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6574 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6575 && (i
.tm
.opcode_modifier
.veximmext
6576 || (i
.imm_operands
== 1
6577 && i
.types
[0].bitfield
.vec_imm4
6578 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
6579 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6580 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
)));
6582 if (i
.imm_operands
== 0)
6584 /* When there is no immediate operand, generate an 8bit
6585 immediate operand to encode the first operand. */
6586 exp
= &im_expressions
[i
.imm_operands
++];
6587 i
.op
[i
.operands
].imms
= exp
;
6588 i
.types
[i
.operands
] = imm8
;
6590 /* If VexW1 is set, the first operand is the source and
6591 the second operand is encoded in the immediate operand. */
6592 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6603 /* FMA swaps REG and NDS. */
6604 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6612 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6613 exp
->X_op
= O_constant
;
6614 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6615 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6619 unsigned int imm_slot
;
6621 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6623 /* If VexW0 is set, the third operand is the source and
6624 the second operand is encoded in the immediate
6631 /* VexW1 is set, the second operand is the source and
6632 the third operand is encoded in the immediate
6638 if (i
.tm
.opcode_modifier
.immext
)
6640 /* When ImmExt is set, the immediate byte is the last
6642 imm_slot
= i
.operands
- 1;
6650 /* Turn on Imm8 so that output_imm will generate it. */
6651 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6654 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6655 i
.op
[imm_slot
].imms
->X_add_number
6656 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6657 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6660 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
6661 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6666 /* i.reg_operands MUST be the number of real register operands;
6667 implicit registers do not count. If there are 3 register
6668 operands, it must be a instruction with VexNDS. For a
6669 instruction with VexNDD, the destination register is encoded
6670 in VEX prefix. If there are 4 register operands, it must be
6671 a instruction with VEX prefix and 3 sources. */
6672 if (i
.mem_operands
== 0
6673 && ((i
.reg_operands
== 2
6674 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6675 || (i
.reg_operands
== 3
6676 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6677 || (i
.reg_operands
== 4 && vex_3_sources
)))
6685 /* When there are 3 operands, one of them may be immediate,
6686 which may be the first or the last operand. Otherwise,
6687 the first operand must be shift count register (cl) or it
6688 is an instruction with VexNDS. */
6689 gas_assert (i
.imm_operands
== 1
6690 || (i
.imm_operands
== 0
6691 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6692 || i
.types
[0].bitfield
.shiftcount
)));
6693 if (operand_type_check (i
.types
[0], imm
)
6694 || i
.types
[0].bitfield
.shiftcount
)
6700 /* When there are 4 operands, the first two must be 8bit
6701 immediate operands. The source operand will be the 3rd
6704 For instructions with VexNDS, if the first operand
6705 an imm8, the source operand is the 2nd one. If the last
6706 operand is imm8, the source operand is the first one. */
6707 gas_assert ((i
.imm_operands
== 2
6708 && i
.types
[0].bitfield
.imm8
6709 && i
.types
[1].bitfield
.imm8
)
6710 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6711 && i
.imm_operands
== 1
6712 && (i
.types
[0].bitfield
.imm8
6713 || i
.types
[i
.operands
- 1].bitfield
.imm8
6715 if (i
.imm_operands
== 2)
6719 if (i
.types
[0].bitfield
.imm8
)
6726 if (i
.tm
.opcode_modifier
.evex
)
6728 /* For EVEX instructions, when there are 5 operands, the
6729 first one must be immediate operand. If the second one
6730 is immediate operand, the source operand is the 3th
6731 one. If the last one is immediate operand, the source
6732 operand is the 2nd one. */
6733 gas_assert (i
.imm_operands
== 2
6734 && i
.tm
.opcode_modifier
.sae
6735 && operand_type_check (i
.types
[0], imm
));
6736 if (operand_type_check (i
.types
[1], imm
))
6738 else if (operand_type_check (i
.types
[4], imm
))
6752 /* RC/SAE operand could be between DEST and SRC. That happens
6753 when one operand is GPR and the other one is XMM/YMM/ZMM
6755 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6758 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6760 /* For instructions with VexNDS, the register-only source
6761 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6762 register. It is encoded in VEX prefix. We need to
6763 clear RegMem bit before calling operand_type_equal. */
6765 i386_operand_type op
;
6768 /* Check register-only source operand when two source
6769 operands are swapped. */
6770 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6771 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6779 op
= i
.tm
.operand_types
[vvvv
];
6780 op
.bitfield
.regmem
= 0;
6781 if ((dest
+ 1) >= i
.operands
6782 || ((!op
.bitfield
.reg
6783 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
6784 && !op
.bitfield
.regsimd
6785 && !operand_type_equal (&op
, ®mask
)))
6787 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6793 /* One of the register operands will be encoded in the i.tm.reg
6794 field, the other in the combined i.tm.mode and i.tm.regmem
6795 fields. If no form of this instruction supports a memory
6796 destination operand, then we assume the source operand may
6797 sometimes be a memory operand and so we need to store the
6798 destination in the i.rm.reg field. */
6799 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6800 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6802 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6803 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6804 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6806 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6808 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6810 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6815 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6816 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6817 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6819 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6821 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6823 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6826 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6828 if (!i
.types
[0].bitfield
.control
6829 && !i
.types
[1].bitfield
.control
)
6831 i
.rex
&= ~(REX_R
| REX_B
);
6832 add_prefix (LOCK_PREFIX_OPCODE
);
6836 { /* If it's not 2 reg operands... */
6841 unsigned int fake_zero_displacement
= 0;
6844 for (op
= 0; op
< i
.operands
; op
++)
6845 if (operand_type_check (i
.types
[op
], anymem
))
6847 gas_assert (op
< i
.operands
);
6849 if (i
.tm
.opcode_modifier
.vecsib
)
6851 if (i
.index_reg
->reg_num
== RegEiz
6852 || i
.index_reg
->reg_num
== RegRiz
)
6855 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6858 i
.sib
.base
= NO_BASE_REGISTER
;
6859 i
.sib
.scale
= i
.log2_scale_factor
;
6860 i
.types
[op
].bitfield
.disp8
= 0;
6861 i
.types
[op
].bitfield
.disp16
= 0;
6862 i
.types
[op
].bitfield
.disp64
= 0;
6863 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
6865 /* Must be 32 bit */
6866 i
.types
[op
].bitfield
.disp32
= 1;
6867 i
.types
[op
].bitfield
.disp32s
= 0;
6871 i
.types
[op
].bitfield
.disp32
= 0;
6872 i
.types
[op
].bitfield
.disp32s
= 1;
6875 i
.sib
.index
= i
.index_reg
->reg_num
;
6876 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6878 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6884 if (i
.base_reg
== 0)
6887 if (!i
.disp_operands
)
6888 fake_zero_displacement
= 1;
6889 if (i
.index_reg
== 0)
6891 i386_operand_type newdisp
;
6893 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6894 /* Operand is just <disp> */
6895 if (flag_code
== CODE_64BIT
)
6897 /* 64bit mode overwrites the 32bit absolute
6898 addressing by RIP relative addressing and
6899 absolute addressing is encoded by one of the
6900 redundant SIB forms. */
6901 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6902 i
.sib
.base
= NO_BASE_REGISTER
;
6903 i
.sib
.index
= NO_INDEX_REGISTER
;
6904 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
6906 else if ((flag_code
== CODE_16BIT
)
6907 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6909 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6914 i
.rm
.regmem
= NO_BASE_REGISTER
;
6917 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6918 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
6920 else if (!i
.tm
.opcode_modifier
.vecsib
)
6922 /* !i.base_reg && i.index_reg */
6923 if (i
.index_reg
->reg_num
== RegEiz
6924 || i
.index_reg
->reg_num
== RegRiz
)
6925 i
.sib
.index
= NO_INDEX_REGISTER
;
6927 i
.sib
.index
= i
.index_reg
->reg_num
;
6928 i
.sib
.base
= NO_BASE_REGISTER
;
6929 i
.sib
.scale
= i
.log2_scale_factor
;
6930 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6931 i
.types
[op
].bitfield
.disp8
= 0;
6932 i
.types
[op
].bitfield
.disp16
= 0;
6933 i
.types
[op
].bitfield
.disp64
= 0;
6934 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
6936 /* Must be 32 bit */
6937 i
.types
[op
].bitfield
.disp32
= 1;
6938 i
.types
[op
].bitfield
.disp32s
= 0;
6942 i
.types
[op
].bitfield
.disp32
= 0;
6943 i
.types
[op
].bitfield
.disp32s
= 1;
6945 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6949 /* RIP addressing for 64bit mode. */
6950 else if (i
.base_reg
->reg_num
== RegRip
||
6951 i
.base_reg
->reg_num
== RegEip
)
6953 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6954 i
.rm
.regmem
= NO_BASE_REGISTER
;
6955 i
.types
[op
].bitfield
.disp8
= 0;
6956 i
.types
[op
].bitfield
.disp16
= 0;
6957 i
.types
[op
].bitfield
.disp32
= 0;
6958 i
.types
[op
].bitfield
.disp32s
= 1;
6959 i
.types
[op
].bitfield
.disp64
= 0;
6960 i
.flags
[op
] |= Operand_PCrel
;
6961 if (! i
.disp_operands
)
6962 fake_zero_displacement
= 1;
6964 else if (i
.base_reg
->reg_type
.bitfield
.word
)
6966 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6967 switch (i
.base_reg
->reg_num
)
6970 if (i
.index_reg
== 0)
6972 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6973 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6977 if (i
.index_reg
== 0)
6980 if (operand_type_check (i
.types
[op
], disp
) == 0)
6982 /* fake (%bp) into 0(%bp) */
6983 i
.types
[op
].bitfield
.disp8
= 1;
6984 fake_zero_displacement
= 1;
6987 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6988 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6990 default: /* (%si) -> 4 or (%di) -> 5 */
6991 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6993 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6995 else /* i.base_reg and 32/64 bit mode */
6997 if (flag_code
== CODE_64BIT
6998 && operand_type_check (i
.types
[op
], disp
))
7000 i
.types
[op
].bitfield
.disp16
= 0;
7001 i
.types
[op
].bitfield
.disp64
= 0;
7002 if (i
.prefix
[ADDR_PREFIX
] == 0)
7004 i
.types
[op
].bitfield
.disp32
= 0;
7005 i
.types
[op
].bitfield
.disp32s
= 1;
7009 i
.types
[op
].bitfield
.disp32
= 1;
7010 i
.types
[op
].bitfield
.disp32s
= 0;
7014 if (!i
.tm
.opcode_modifier
.vecsib
)
7015 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7016 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7018 i
.sib
.base
= i
.base_reg
->reg_num
;
7019 /* x86-64 ignores REX prefix bit here to avoid decoder
7021 if (!(i
.base_reg
->reg_flags
& RegRex
)
7022 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7023 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7025 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7027 fake_zero_displacement
= 1;
7028 i
.types
[op
].bitfield
.disp8
= 1;
7030 i
.sib
.scale
= i
.log2_scale_factor
;
7031 if (i
.index_reg
== 0)
7033 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7034 /* <disp>(%esp) becomes two byte modrm with no index
7035 register. We've already stored the code for esp
7036 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7037 Any base register besides %esp will not use the
7038 extra modrm byte. */
7039 i
.sib
.index
= NO_INDEX_REGISTER
;
7041 else if (!i
.tm
.opcode_modifier
.vecsib
)
7043 if (i
.index_reg
->reg_num
== RegEiz
7044 || i
.index_reg
->reg_num
== RegRiz
)
7045 i
.sib
.index
= NO_INDEX_REGISTER
;
7047 i
.sib
.index
= i
.index_reg
->reg_num
;
7048 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7049 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7054 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7055 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7059 if (!fake_zero_displacement
7063 fake_zero_displacement
= 1;
7064 if (i
.disp_encoding
== disp_encoding_8bit
)
7065 i
.types
[op
].bitfield
.disp8
= 1;
7067 i
.types
[op
].bitfield
.disp32
= 1;
7069 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7073 if (fake_zero_displacement
)
7075 /* Fakes a zero displacement assuming that i.types[op]
7076 holds the correct displacement size. */
7079 gas_assert (i
.op
[op
].disps
== 0);
7080 exp
= &disp_expressions
[i
.disp_operands
++];
7081 i
.op
[op
].disps
= exp
;
7082 exp
->X_op
= O_constant
;
7083 exp
->X_add_number
= 0;
7084 exp
->X_add_symbol
= (symbolS
*) 0;
7085 exp
->X_op_symbol
= (symbolS
*) 0;
7093 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7095 if (operand_type_check (i
.types
[0], imm
))
7096 i
.vex
.register_specifier
= NULL
;
7099 /* VEX.vvvv encodes one of the sources when the first
7100 operand is not an immediate. */
7101 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7102 i
.vex
.register_specifier
= i
.op
[0].regs
;
7104 i
.vex
.register_specifier
= i
.op
[1].regs
;
7107 /* Destination is a XMM register encoded in the ModRM.reg
7109 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7110 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7113 /* ModRM.rm and VEX.B encodes the other source. */
7114 if (!i
.mem_operands
)
7118 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7119 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7121 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7123 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7127 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7129 i
.vex
.register_specifier
= i
.op
[2].regs
;
7130 if (!i
.mem_operands
)
7133 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7134 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7138 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7139 (if any) based on i.tm.extension_opcode. Again, we must be
7140 careful to make sure that segment/control/debug/test/MMX
7141 registers are coded into the i.rm.reg field. */
7142 else if (i
.reg_operands
)
7145 unsigned int vex_reg
= ~0;
7147 for (op
= 0; op
< i
.operands
; op
++)
7148 if (i
.types
[op
].bitfield
.reg
7149 || i
.types
[op
].bitfield
.regmmx
7150 || i
.types
[op
].bitfield
.regsimd
7151 || i
.types
[op
].bitfield
.regbnd
7152 || i
.types
[op
].bitfield
.regmask
7153 || i
.types
[op
].bitfield
.sreg2
7154 || i
.types
[op
].bitfield
.sreg3
7155 || i
.types
[op
].bitfield
.control
7156 || i
.types
[op
].bitfield
.debug
7157 || i
.types
[op
].bitfield
.test
)
7162 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7164 /* For instructions with VexNDS, the register-only
7165 source operand is encoded in VEX prefix. */
7166 gas_assert (mem
!= (unsigned int) ~0);
7171 gas_assert (op
< i
.operands
);
7175 /* Check register-only source operand when two source
7176 operands are swapped. */
7177 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7178 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7182 gas_assert (mem
== (vex_reg
+ 1)
7183 && op
< i
.operands
);
7188 gas_assert (vex_reg
< i
.operands
);
7192 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7194 /* For instructions with VexNDD, the register destination
7195 is encoded in VEX prefix. */
7196 if (i
.mem_operands
== 0)
7198 /* There is no memory operand. */
7199 gas_assert ((op
+ 2) == i
.operands
);
7204 /* There are only 2 operands. */
7205 gas_assert (op
< 2 && i
.operands
== 2);
7210 gas_assert (op
< i
.operands
);
7212 if (vex_reg
!= (unsigned int) ~0)
7214 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7216 if ((!type
->bitfield
.reg
7217 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7218 && !type
->bitfield
.regsimd
7219 && !operand_type_equal (type
, ®mask
))
7222 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7225 /* Don't set OP operand twice. */
7228 /* If there is an extension opcode to put here, the
7229 register number must be put into the regmem field. */
7230 if (i
.tm
.extension_opcode
!= None
)
7232 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7233 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7235 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7240 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7241 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7243 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7248 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7249 must set it to 3 to indicate this is a register operand
7250 in the regmem field. */
7251 if (!i
.mem_operands
)
7255 /* Fill in i.rm.reg field with extension opcode (if any). */
7256 if (i
.tm
.extension_opcode
!= None
)
7257 i
.rm
.reg
= i
.tm
.extension_opcode
;
7263 output_branch (void)
7269 relax_substateT subtype
;
7273 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7274 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7277 if (i
.prefix
[DATA_PREFIX
] != 0)
7283 /* Pentium4 branch hints. */
7284 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7285 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7290 if (i
.prefix
[REX_PREFIX
] != 0)
7296 /* BND prefixed jump. */
7297 if (i
.prefix
[BND_PREFIX
] != 0)
7299 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7303 if (i
.prefixes
!= 0 && !intel_syntax
)
7304 as_warn (_("skipping prefixes on this instruction"));
7306 /* It's always a symbol; End frag & setup for relax.
7307 Make sure there is enough room in this frag for the largest
7308 instruction we may generate in md_convert_frag. This is 2
7309 bytes for the opcode and room for the prefix and largest
7311 frag_grow (prefix
+ 2 + 4);
7312 /* Prefix and 1 opcode byte go in fr_fix. */
7313 p
= frag_more (prefix
+ 1);
7314 if (i
.prefix
[DATA_PREFIX
] != 0)
7315 *p
++ = DATA_PREFIX_OPCODE
;
7316 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7317 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7318 *p
++ = i
.prefix
[SEG_PREFIX
];
7319 if (i
.prefix
[REX_PREFIX
] != 0)
7320 *p
++ = i
.prefix
[REX_PREFIX
];
7321 *p
= i
.tm
.base_opcode
;
7323 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7324 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7325 else if (cpu_arch_flags
.bitfield
.cpui386
)
7326 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7328 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7331 sym
= i
.op
[0].disps
->X_add_symbol
;
7332 off
= i
.op
[0].disps
->X_add_number
;
7334 if (i
.op
[0].disps
->X_op
!= O_constant
7335 && i
.op
[0].disps
->X_op
!= O_symbol
)
7337 /* Handle complex expressions. */
7338 sym
= make_expr_symbol (i
.op
[0].disps
);
7342 /* 1 possible extra opcode + 4 byte displacement go in var part.
7343 Pass reloc in fr_var. */
7344 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7347 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7348 /* Return TRUE iff PLT32 relocation should be used for branching to
7352 need_plt32_p (symbolS
*s
)
7354 /* PLT32 relocation is ELF only. */
7358 /* Since there is no need to prepare for PLT branch on x86-64, we
7359 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7360 be used as a marker for 32-bit PC-relative branches. */
7364 /* Weak or undefined symbol need PLT32 relocation. */
7365 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7368 /* Non-global symbol doesn't need PLT32 relocation. */
7369 if (! S_IS_EXTERNAL (s
))
7372 /* Other global symbols need PLT32 relocation. NB: Symbol with
7373 non-default visibilities are treated as normal global symbol
7374 so that PLT32 relocation can be used as a marker for 32-bit
7375 PC-relative branches. It is useful for linker relaxation. */
7386 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7388 if (i
.tm
.opcode_modifier
.jumpbyte
)
7390 /* This is a loop or jecxz type instruction. */
7392 if (i
.prefix
[ADDR_PREFIX
] != 0)
7394 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7397 /* Pentium4 branch hints. */
7398 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7399 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7401 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7410 if (flag_code
== CODE_16BIT
)
7413 if (i
.prefix
[DATA_PREFIX
] != 0)
7415 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7425 if (i
.prefix
[REX_PREFIX
] != 0)
7427 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7431 /* BND prefixed jump. */
7432 if (i
.prefix
[BND_PREFIX
] != 0)
7434 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7438 if (i
.prefixes
!= 0 && !intel_syntax
)
7439 as_warn (_("skipping prefixes on this instruction"));
7441 p
= frag_more (i
.tm
.opcode_length
+ size
);
7442 switch (i
.tm
.opcode_length
)
7445 *p
++ = i
.tm
.base_opcode
>> 8;
7448 *p
++ = i
.tm
.base_opcode
;
7454 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7456 && jump_reloc
== NO_RELOC
7457 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7458 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7461 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7463 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7464 i
.op
[0].disps
, 1, jump_reloc
);
7466 /* All jumps handled here are signed, but don't use a signed limit
7467 check for 32 and 16 bit jumps as we want to allow wrap around at
7468 4G and 64k respectively. */
7470 fixP
->fx_signed
= 1;
7474 output_interseg_jump (void)
7482 if (flag_code
== CODE_16BIT
)
7486 if (i
.prefix
[DATA_PREFIX
] != 0)
7492 if (i
.prefix
[REX_PREFIX
] != 0)
7502 if (i
.prefixes
!= 0 && !intel_syntax
)
7503 as_warn (_("skipping prefixes on this instruction"));
7505 /* 1 opcode; 2 segment; offset */
7506 p
= frag_more (prefix
+ 1 + 2 + size
);
7508 if (i
.prefix
[DATA_PREFIX
] != 0)
7509 *p
++ = DATA_PREFIX_OPCODE
;
7511 if (i
.prefix
[REX_PREFIX
] != 0)
7512 *p
++ = i
.prefix
[REX_PREFIX
];
7514 *p
++ = i
.tm
.base_opcode
;
7515 if (i
.op
[1].imms
->X_op
== O_constant
)
7517 offsetT n
= i
.op
[1].imms
->X_add_number
;
7520 && !fits_in_unsigned_word (n
)
7521 && !fits_in_signed_word (n
))
7523 as_bad (_("16-bit jump out of range"));
7526 md_number_to_chars (p
, n
, size
);
7529 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7530 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7531 if (i
.op
[0].imms
->X_op
!= O_constant
)
7532 as_bad (_("can't handle non absolute segment in `%s'"),
7534 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7540 fragS
*insn_start_frag
;
7541 offsetT insn_start_off
;
7543 /* Tie dwarf2 debug info to the address at the start of the insn.
7544 We can't do this after the insn has been output as the current
7545 frag may have been closed off. eg. by frag_var. */
7546 dwarf2_emit_insn (0);
7548 insn_start_frag
= frag_now
;
7549 insn_start_off
= frag_now_fix ();
7552 if (i
.tm
.opcode_modifier
.jump
)
7554 else if (i
.tm
.opcode_modifier
.jumpbyte
7555 || i
.tm
.opcode_modifier
.jumpdword
)
7557 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7558 output_interseg_jump ();
7561 /* Output normal instructions here. */
7565 unsigned int prefix
;
7568 && i
.tm
.base_opcode
== 0xfae
7570 && i
.imm_operands
== 1
7571 && (i
.op
[0].imms
->X_add_number
== 0xe8
7572 || i
.op
[0].imms
->X_add_number
== 0xf0
7573 || i
.op
[0].imms
->X_add_number
== 0xf8))
7575 /* Encode lfence, mfence, and sfence as
7576 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7577 offsetT val
= 0x240483f0ULL
;
7579 md_number_to_chars (p
, val
, 5);
7583 /* Some processors fail on LOCK prefix. This options makes
7584 assembler ignore LOCK prefix and serves as a workaround. */
7585 if (omit_lock_prefix
)
7587 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7589 i
.prefix
[LOCK_PREFIX
] = 0;
7592 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7593 don't need the explicit prefix. */
7594 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7596 switch (i
.tm
.opcode_length
)
7599 if (i
.tm
.base_opcode
& 0xff000000)
7601 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7606 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7608 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7609 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7612 if (prefix
!= REPE_PREFIX_OPCODE
7613 || (i
.prefix
[REP_PREFIX
]
7614 != REPE_PREFIX_OPCODE
))
7615 add_prefix (prefix
);
7618 add_prefix (prefix
);
7624 /* Check for pseudo prefixes. */
7625 as_bad_where (insn_start_frag
->fr_file
,
7626 insn_start_frag
->fr_line
,
7627 _("pseudo prefix without instruction"));
7633 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7634 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7635 R_X86_64_GOTTPOFF relocation so that linker can safely
7636 perform IE->LE optimization. */
7637 if (x86_elf_abi
== X86_64_X32_ABI
7639 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7640 && i
.prefix
[REX_PREFIX
] == 0)
7641 add_prefix (REX_OPCODE
);
7644 /* The prefix bytes. */
7645 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7647 FRAG_APPEND_1_CHAR (*q
);
7651 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7656 /* REX byte is encoded in VEX prefix. */
7660 FRAG_APPEND_1_CHAR (*q
);
7663 /* There should be no other prefixes for instructions
7668 /* For EVEX instructions i.vrex should become 0 after
7669 build_evex_prefix. For VEX instructions upper 16 registers
7670 aren't available, so VREX should be 0. */
7673 /* Now the VEX prefix. */
7674 p
= frag_more (i
.vex
.length
);
7675 for (j
= 0; j
< i
.vex
.length
; j
++)
7676 p
[j
] = i
.vex
.bytes
[j
];
7679 /* Now the opcode; be careful about word order here! */
7680 if (i
.tm
.opcode_length
== 1)
7682 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7686 switch (i
.tm
.opcode_length
)
7690 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7691 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7695 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7705 /* Put out high byte first: can't use md_number_to_chars! */
7706 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7707 *p
= i
.tm
.base_opcode
& 0xff;
7710 /* Now the modrm byte and sib byte (if present). */
7711 if (i
.tm
.opcode_modifier
.modrm
)
7713 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7716 /* If i.rm.regmem == ESP (4)
7717 && i.rm.mode != (Register mode)
7719 ==> need second modrm byte. */
7720 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7722 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
7723 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7725 | i
.sib
.scale
<< 6));
7728 if (i
.disp_operands
)
7729 output_disp (insn_start_frag
, insn_start_off
);
7732 output_imm (insn_start_frag
, insn_start_off
);
7738 pi ("" /*line*/, &i
);
7740 #endif /* DEBUG386 */
7743 /* Return the size of the displacement operand N. */
7746 disp_size (unsigned int n
)
7750 if (i
.types
[n
].bitfield
.disp64
)
7752 else if (i
.types
[n
].bitfield
.disp8
)
7754 else if (i
.types
[n
].bitfield
.disp16
)
7759 /* Return the size of the immediate operand N. */
7762 imm_size (unsigned int n
)
7765 if (i
.types
[n
].bitfield
.imm64
)
7767 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7769 else if (i
.types
[n
].bitfield
.imm16
)
7775 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7780 for (n
= 0; n
< i
.operands
; n
++)
7782 if (operand_type_check (i
.types
[n
], disp
))
7784 if (i
.op
[n
].disps
->X_op
== O_constant
)
7786 int size
= disp_size (n
);
7787 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7789 val
= offset_in_range (val
>> i
.memshift
, size
);
7790 p
= frag_more (size
);
7791 md_number_to_chars (p
, val
, size
);
7795 enum bfd_reloc_code_real reloc_type
;
7796 int size
= disp_size (n
);
7797 int sign
= i
.types
[n
].bitfield
.disp32s
;
7798 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7801 /* We can't have 8 bit displacement here. */
7802 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7804 /* The PC relative address is computed relative
7805 to the instruction boundary, so in case immediate
7806 fields follows, we need to adjust the value. */
7807 if (pcrel
&& i
.imm_operands
)
7812 for (n1
= 0; n1
< i
.operands
; n1
++)
7813 if (operand_type_check (i
.types
[n1
], imm
))
7815 /* Only one immediate is allowed for PC
7816 relative address. */
7817 gas_assert (sz
== 0);
7819 i
.op
[n
].disps
->X_add_number
-= sz
;
7821 /* We should find the immediate. */
7822 gas_assert (sz
!= 0);
7825 p
= frag_more (size
);
7826 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7828 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7829 && (((reloc_type
== BFD_RELOC_32
7830 || reloc_type
== BFD_RELOC_X86_64_32S
7831 || (reloc_type
== BFD_RELOC_64
7833 && (i
.op
[n
].disps
->X_op
== O_symbol
7834 || (i
.op
[n
].disps
->X_op
== O_add
7835 && ((symbol_get_value_expression
7836 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7838 || reloc_type
== BFD_RELOC_32_PCREL
))
7842 if (insn_start_frag
== frag_now
)
7843 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7848 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7849 for (fr
= insn_start_frag
->fr_next
;
7850 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7852 add
+= p
- frag_now
->fr_literal
;
7857 reloc_type
= BFD_RELOC_386_GOTPC
;
7858 i
.op
[n
].imms
->X_add_number
+= add
;
7860 else if (reloc_type
== BFD_RELOC_64
)
7861 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7863 /* Don't do the adjustment for x86-64, as there
7864 the pcrel addressing is relative to the _next_
7865 insn, and that is taken care of in other code. */
7866 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7868 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7869 size
, i
.op
[n
].disps
, pcrel
,
7871 /* Check for "call/jmp *mem", "mov mem, %reg",
7872 "test %reg, mem" and "binop mem, %reg" where binop
7873 is one of adc, add, and, cmp, or, sbb, sub, xor
7874 instructions. Always generate R_386_GOT32X for
7875 "sym*GOT" operand in 32-bit mode. */
7876 if ((generate_relax_relocations
7879 && i
.rm
.regmem
== 5))
7881 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7882 && ((i
.operands
== 1
7883 && i
.tm
.base_opcode
== 0xff
7884 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7886 && (i
.tm
.base_opcode
== 0x8b
7887 || i
.tm
.base_opcode
== 0x85
7888 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7892 fixP
->fx_tcbit
= i
.rex
!= 0;
7894 && (i
.base_reg
->reg_num
== RegRip
7895 || i
.base_reg
->reg_num
== RegEip
))
7896 fixP
->fx_tcbit2
= 1;
7899 fixP
->fx_tcbit2
= 1;
7907 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7912 for (n
= 0; n
< i
.operands
; n
++)
7914 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7915 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7918 if (operand_type_check (i
.types
[n
], imm
))
7920 if (i
.op
[n
].imms
->X_op
== O_constant
)
7922 int size
= imm_size (n
);
7925 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7927 p
= frag_more (size
);
7928 md_number_to_chars (p
, val
, size
);
7932 /* Not absolute_section.
7933 Need a 32-bit fixup (don't support 8bit
7934 non-absolute imms). Try to support other
7936 enum bfd_reloc_code_real reloc_type
;
7937 int size
= imm_size (n
);
7940 if (i
.types
[n
].bitfield
.imm32s
7941 && (i
.suffix
== QWORD_MNEM_SUFFIX
7942 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7947 p
= frag_more (size
);
7948 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7950 /* This is tough to explain. We end up with this one if we
7951 * have operands that look like
7952 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7953 * obtain the absolute address of the GOT, and it is strongly
7954 * preferable from a performance point of view to avoid using
7955 * a runtime relocation for this. The actual sequence of
7956 * instructions often look something like:
7961 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7963 * The call and pop essentially return the absolute address
7964 * of the label .L66 and store it in %ebx. The linker itself
7965 * will ultimately change the first operand of the addl so
7966 * that %ebx points to the GOT, but to keep things simple, the
7967 * .o file must have this operand set so that it generates not
7968 * the absolute address of .L66, but the absolute address of
7969 * itself. This allows the linker itself simply treat a GOTPC
7970 * relocation as asking for a pcrel offset to the GOT to be
7971 * added in, and the addend of the relocation is stored in the
7972 * operand field for the instruction itself.
7974 * Our job here is to fix the operand so that it would add
7975 * the correct offset so that %ebx would point to itself. The
7976 * thing that is tricky is that .-.L66 will point to the
7977 * beginning of the instruction, so we need to further modify
7978 * the operand so that it will point to itself. There are
7979 * other cases where you have something like:
7981 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7983 * and here no correction would be required. Internally in
7984 * the assembler we treat operands of this form as not being
7985 * pcrel since the '.' is explicitly mentioned, and I wonder
7986 * whether it would simplify matters to do it this way. Who
7987 * knows. In earlier versions of the PIC patches, the
7988 * pcrel_adjust field was used to store the correction, but
7989 * since the expression is not pcrel, I felt it would be
7990 * confusing to do it this way. */
7992 if ((reloc_type
== BFD_RELOC_32
7993 || reloc_type
== BFD_RELOC_X86_64_32S
7994 || reloc_type
== BFD_RELOC_64
)
7996 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7997 && (i
.op
[n
].imms
->X_op
== O_symbol
7998 || (i
.op
[n
].imms
->X_op
== O_add
7999 && ((symbol_get_value_expression
8000 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8005 if (insn_start_frag
== frag_now
)
8006 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8011 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8012 for (fr
= insn_start_frag
->fr_next
;
8013 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8015 add
+= p
- frag_now
->fr_literal
;
8019 reloc_type
= BFD_RELOC_386_GOTPC
;
8021 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8023 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8024 i
.op
[n
].imms
->X_add_number
+= add
;
8026 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8027 i
.op
[n
].imms
, 0, reloc_type
);
8033 /* x86_cons_fix_new is called via the expression parsing code when a
8034 reloc is needed. We use this hook to get the correct .got reloc. */
8035 static int cons_sign
= -1;
8038 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8039 expressionS
*exp
, bfd_reloc_code_real_type r
)
8041 r
= reloc (len
, 0, cons_sign
, r
);
8044 if (exp
->X_op
== O_secrel
)
8046 exp
->X_op
= O_symbol
;
8047 r
= BFD_RELOC_32_SECREL
;
8051 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8054 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8055 purpose of the `.dc.a' internal pseudo-op. */
8058 x86_address_bytes (void)
8060 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8062 return stdoutput
->arch_info
->bits_per_address
/ 8;
8065 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8067 # define lex_got(reloc, adjust, types) NULL
8069 /* Parse operands of the form
8070 <symbol>@GOTOFF+<nnn>
8071 and similar .plt or .got references.
8073 If we find one, set up the correct relocation in RELOC and copy the
8074 input string, minus the `@GOTOFF' into a malloc'd buffer for
8075 parsing by the calling routine. Return this buffer, and if ADJUST
8076 is non-null set it to the length of the string we removed from the
8077 input line. Otherwise return NULL. */
8079 lex_got (enum bfd_reloc_code_real
*rel
,
8081 i386_operand_type
*types
)
8083 /* Some of the relocations depend on the size of what field is to
8084 be relocated. But in our callers i386_immediate and i386_displacement
8085 we don't yet know the operand size (this will be set by insn
8086 matching). Hence we record the word32 relocation here,
8087 and adjust the reloc according to the real size in reloc(). */
8088 static const struct {
8091 const enum bfd_reloc_code_real rel
[2];
8092 const i386_operand_type types64
;
8094 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8095 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8097 OPERAND_TYPE_IMM32_64
},
8099 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8100 BFD_RELOC_X86_64_PLTOFF64
},
8101 OPERAND_TYPE_IMM64
},
8102 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8103 BFD_RELOC_X86_64_PLT32
},
8104 OPERAND_TYPE_IMM32_32S_DISP32
},
8105 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8106 BFD_RELOC_X86_64_GOTPLT64
},
8107 OPERAND_TYPE_IMM64_DISP64
},
8108 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8109 BFD_RELOC_X86_64_GOTOFF64
},
8110 OPERAND_TYPE_IMM64_DISP64
},
8111 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8112 BFD_RELOC_X86_64_GOTPCREL
},
8113 OPERAND_TYPE_IMM32_32S_DISP32
},
8114 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8115 BFD_RELOC_X86_64_TLSGD
},
8116 OPERAND_TYPE_IMM32_32S_DISP32
},
8117 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8118 _dummy_first_bfd_reloc_code_real
},
8119 OPERAND_TYPE_NONE
},
8120 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8121 BFD_RELOC_X86_64_TLSLD
},
8122 OPERAND_TYPE_IMM32_32S_DISP32
},
8123 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8124 BFD_RELOC_X86_64_GOTTPOFF
},
8125 OPERAND_TYPE_IMM32_32S_DISP32
},
8126 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8127 BFD_RELOC_X86_64_TPOFF32
},
8128 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8129 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8130 _dummy_first_bfd_reloc_code_real
},
8131 OPERAND_TYPE_NONE
},
8132 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8133 BFD_RELOC_X86_64_DTPOFF32
},
8134 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8135 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8136 _dummy_first_bfd_reloc_code_real
},
8137 OPERAND_TYPE_NONE
},
8138 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8139 _dummy_first_bfd_reloc_code_real
},
8140 OPERAND_TYPE_NONE
},
8141 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8142 BFD_RELOC_X86_64_GOT32
},
8143 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8144 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8145 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8146 OPERAND_TYPE_IMM32_32S_DISP32
},
8147 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8148 BFD_RELOC_X86_64_TLSDESC_CALL
},
8149 OPERAND_TYPE_IMM32_32S_DISP32
},
8154 #if defined (OBJ_MAYBE_ELF)
8159 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8160 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8163 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8165 int len
= gotrel
[j
].len
;
8166 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8168 if (gotrel
[j
].rel
[object_64bit
] != 0)
8171 char *tmpbuf
, *past_reloc
;
8173 *rel
= gotrel
[j
].rel
[object_64bit
];
8177 if (flag_code
!= CODE_64BIT
)
8179 types
->bitfield
.imm32
= 1;
8180 types
->bitfield
.disp32
= 1;
8183 *types
= gotrel
[j
].types64
;
8186 if (j
!= 0 && GOT_symbol
== NULL
)
8187 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8189 /* The length of the first part of our input line. */
8190 first
= cp
- input_line_pointer
;
8192 /* The second part goes from after the reloc token until
8193 (and including) an end_of_line char or comma. */
8194 past_reloc
= cp
+ 1 + len
;
8196 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8198 second
= cp
+ 1 - past_reloc
;
8200 /* Allocate and copy string. The trailing NUL shouldn't
8201 be necessary, but be safe. */
8202 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8203 memcpy (tmpbuf
, input_line_pointer
, first
);
8204 if (second
!= 0 && *past_reloc
!= ' ')
8205 /* Replace the relocation token with ' ', so that
8206 errors like foo@GOTOFF1 will be detected. */
8207 tmpbuf
[first
++] = ' ';
8209 /* Increment length by 1 if the relocation token is
8214 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8215 tmpbuf
[first
+ second
] = '\0';
8219 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8220 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8225 /* Might be a symbol version string. Don't as_bad here. */
8234 /* Parse operands of the form
8235 <symbol>@SECREL32+<nnn>
8237 If we find one, set up the correct relocation in RELOC and copy the
8238 input string, minus the `@SECREL32' into a malloc'd buffer for
8239 parsing by the calling routine. Return this buffer, and if ADJUST
8240 is non-null set it to the length of the string we removed from the
8241 input line. Otherwise return NULL.
8243 This function is copied from the ELF version above adjusted for PE targets. */
8246 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8247 int *adjust ATTRIBUTE_UNUSED
,
8248 i386_operand_type
*types
)
8254 const enum bfd_reloc_code_real rel
[2];
8255 const i386_operand_type types64
;
8259 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8260 BFD_RELOC_32_SECREL
},
8261 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8267 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8268 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8271 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8273 int len
= gotrel
[j
].len
;
8275 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8277 if (gotrel
[j
].rel
[object_64bit
] != 0)
8280 char *tmpbuf
, *past_reloc
;
8282 *rel
= gotrel
[j
].rel
[object_64bit
];
8288 if (flag_code
!= CODE_64BIT
)
8290 types
->bitfield
.imm32
= 1;
8291 types
->bitfield
.disp32
= 1;
8294 *types
= gotrel
[j
].types64
;
8297 /* The length of the first part of our input line. */
8298 first
= cp
- input_line_pointer
;
8300 /* The second part goes from after the reloc token until
8301 (and including) an end_of_line char or comma. */
8302 past_reloc
= cp
+ 1 + len
;
8304 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8306 second
= cp
+ 1 - past_reloc
;
8308 /* Allocate and copy string. The trailing NUL shouldn't
8309 be necessary, but be safe. */
8310 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8311 memcpy (tmpbuf
, input_line_pointer
, first
);
8312 if (second
!= 0 && *past_reloc
!= ' ')
8313 /* Replace the relocation token with ' ', so that
8314 errors like foo@SECLREL321 will be detected. */
8315 tmpbuf
[first
++] = ' ';
8316 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8317 tmpbuf
[first
+ second
] = '\0';
8321 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8322 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8327 /* Might be a symbol version string. Don't as_bad here. */
8333 bfd_reloc_code_real_type
8334 x86_cons (expressionS
*exp
, int size
)
8336 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
8338 intel_syntax
= -intel_syntax
;
8341 if (size
== 4 || (object_64bit
&& size
== 8))
8343 /* Handle @GOTOFF and the like in an expression. */
8345 char *gotfree_input_line
;
8348 save
= input_line_pointer
;
8349 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
8350 if (gotfree_input_line
)
8351 input_line_pointer
= gotfree_input_line
;
8355 if (gotfree_input_line
)
8357 /* expression () has merrily parsed up to the end of line,
8358 or a comma - in the wrong buffer. Transfer how far
8359 input_line_pointer has moved to the right buffer. */
8360 input_line_pointer
= (save
8361 + (input_line_pointer
- gotfree_input_line
)
8363 free (gotfree_input_line
);
8364 if (exp
->X_op
== O_constant
8365 || exp
->X_op
== O_absent
8366 || exp
->X_op
== O_illegal
8367 || exp
->X_op
== O_register
8368 || exp
->X_op
== O_big
)
8370 char c
= *input_line_pointer
;
8371 *input_line_pointer
= 0;
8372 as_bad (_("missing or invalid expression `%s'"), save
);
8373 *input_line_pointer
= c
;
8380 intel_syntax
= -intel_syntax
;
8383 i386_intel_simplify (exp
);
8389 signed_cons (int size
)
8391 if (flag_code
== CODE_64BIT
)
8399 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
8406 if (exp
.X_op
== O_symbol
)
8407 exp
.X_op
= O_secrel
;
8409 emit_expr (&exp
, 4);
8411 while (*input_line_pointer
++ == ',');
8413 input_line_pointer
--;
8414 demand_empty_rest_of_line ();
8418 /* Handle Vector operations. */
8421 check_VecOperations (char *op_string
, char *op_end
)
8423 const reg_entry
*mask
;
8428 && (op_end
== NULL
|| op_string
< op_end
))
8431 if (*op_string
== '{')
8435 /* Check broadcasts. */
8436 if (strncmp (op_string
, "1to", 3) == 0)
8441 goto duplicated_vec_op
;
8444 if (*op_string
== '8')
8445 bcst_type
= BROADCAST_1TO8
;
8446 else if (*op_string
== '4')
8447 bcst_type
= BROADCAST_1TO4
;
8448 else if (*op_string
== '2')
8449 bcst_type
= BROADCAST_1TO2
;
8450 else if (*op_string
== '1'
8451 && *(op_string
+1) == '6')
8453 bcst_type
= BROADCAST_1TO16
;
8458 as_bad (_("Unsupported broadcast: `%s'"), saved
);
8463 broadcast_op
.type
= bcst_type
;
8464 broadcast_op
.operand
= this_operand
;
8465 i
.broadcast
= &broadcast_op
;
8467 /* Check masking operation. */
8468 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
8470 /* k0 can't be used for write mask. */
8471 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
8473 as_bad (_("`%s%s' can't be used for write mask"),
8474 register_prefix
, mask
->reg_name
);
8480 mask_op
.mask
= mask
;
8481 mask_op
.zeroing
= 0;
8482 mask_op
.operand
= this_operand
;
8488 goto duplicated_vec_op
;
8490 i
.mask
->mask
= mask
;
8492 /* Only "{z}" is allowed here. No need to check
8493 zeroing mask explicitly. */
8494 if (i
.mask
->operand
!= this_operand
)
8496 as_bad (_("invalid write mask `%s'"), saved
);
8503 /* Check zeroing-flag for masking operation. */
8504 else if (*op_string
== 'z')
8508 mask_op
.mask
= NULL
;
8509 mask_op
.zeroing
= 1;
8510 mask_op
.operand
= this_operand
;
8515 if (i
.mask
->zeroing
)
8518 as_bad (_("duplicated `%s'"), saved
);
8522 i
.mask
->zeroing
= 1;
8524 /* Only "{%k}" is allowed here. No need to check mask
8525 register explicitly. */
8526 if (i
.mask
->operand
!= this_operand
)
8528 as_bad (_("invalid zeroing-masking `%s'"),
8537 goto unknown_vec_op
;
8539 if (*op_string
!= '}')
8541 as_bad (_("missing `}' in `%s'"), saved
);
8548 /* We don't know this one. */
8549 as_bad (_("unknown vector operation: `%s'"), saved
);
8553 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
8555 as_bad (_("zeroing-masking only allowed with write mask"));
8563 i386_immediate (char *imm_start
)
8565 char *save_input_line_pointer
;
8566 char *gotfree_input_line
;
8569 i386_operand_type types
;
8571 operand_type_set (&types
, ~0);
8573 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8575 as_bad (_("at most %d immediate operands are allowed"),
8576 MAX_IMMEDIATE_OPERANDS
);
8580 exp
= &im_expressions
[i
.imm_operands
++];
8581 i
.op
[this_operand
].imms
= exp
;
8583 if (is_space_char (*imm_start
))
8586 save_input_line_pointer
= input_line_pointer
;
8587 input_line_pointer
= imm_start
;
8589 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8590 if (gotfree_input_line
)
8591 input_line_pointer
= gotfree_input_line
;
8593 exp_seg
= expression (exp
);
8597 /* Handle vector operations. */
8598 if (*input_line_pointer
== '{')
8600 input_line_pointer
= check_VecOperations (input_line_pointer
,
8602 if (input_line_pointer
== NULL
)
8606 if (*input_line_pointer
)
8607 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8609 input_line_pointer
= save_input_line_pointer
;
8610 if (gotfree_input_line
)
8612 free (gotfree_input_line
);
8614 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8615 exp
->X_op
= O_illegal
;
8618 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8622 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8623 i386_operand_type types
, const char *imm_start
)
8625 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8628 as_bad (_("missing or invalid immediate expression `%s'"),
8632 else if (exp
->X_op
== O_constant
)
8634 /* Size it properly later. */
8635 i
.types
[this_operand
].bitfield
.imm64
= 1;
8636 /* If not 64bit, sign extend val. */
8637 if (flag_code
!= CODE_64BIT
8638 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8640 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8642 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8643 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8644 && exp_seg
!= absolute_section
8645 && exp_seg
!= text_section
8646 && exp_seg
!= data_section
8647 && exp_seg
!= bss_section
8648 && exp_seg
!= undefined_section
8649 && !bfd_is_com_section (exp_seg
))
8651 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8655 else if (!intel_syntax
&& exp_seg
== reg_section
)
8658 as_bad (_("illegal immediate register operand %s"), imm_start
);
8663 /* This is an address. The size of the address will be
8664 determined later, depending on destination register,
8665 suffix, or the default for the section. */
8666 i
.types
[this_operand
].bitfield
.imm8
= 1;
8667 i
.types
[this_operand
].bitfield
.imm16
= 1;
8668 i
.types
[this_operand
].bitfield
.imm32
= 1;
8669 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8670 i
.types
[this_operand
].bitfield
.imm64
= 1;
8671 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8679 i386_scale (char *scale
)
8682 char *save
= input_line_pointer
;
8684 input_line_pointer
= scale
;
8685 val
= get_absolute_expression ();
8690 i
.log2_scale_factor
= 0;
8693 i
.log2_scale_factor
= 1;
8696 i
.log2_scale_factor
= 2;
8699 i
.log2_scale_factor
= 3;
8703 char sep
= *input_line_pointer
;
8705 *input_line_pointer
= '\0';
8706 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8708 *input_line_pointer
= sep
;
8709 input_line_pointer
= save
;
8713 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8715 as_warn (_("scale factor of %d without an index register"),
8716 1 << i
.log2_scale_factor
);
8717 i
.log2_scale_factor
= 0;
8719 scale
= input_line_pointer
;
8720 input_line_pointer
= save
;
8725 i386_displacement (char *disp_start
, char *disp_end
)
8729 char *save_input_line_pointer
;
8730 char *gotfree_input_line
;
8732 i386_operand_type bigdisp
, types
= anydisp
;
8735 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8737 as_bad (_("at most %d displacement operands are allowed"),
8738 MAX_MEMORY_OPERANDS
);
8742 operand_type_set (&bigdisp
, 0);
8743 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8744 || (!current_templates
->start
->opcode_modifier
.jump
8745 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8747 bigdisp
.bitfield
.disp32
= 1;
8748 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8749 if (flag_code
== CODE_64BIT
)
8753 bigdisp
.bitfield
.disp32s
= 1;
8754 bigdisp
.bitfield
.disp64
= 1;
8757 else if ((flag_code
== CODE_16BIT
) ^ override
)
8759 bigdisp
.bitfield
.disp32
= 0;
8760 bigdisp
.bitfield
.disp16
= 1;
8765 /* For PC-relative branches, the width of the displacement
8766 is dependent upon data size, not address size. */
8767 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8768 if (flag_code
== CODE_64BIT
)
8770 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8771 bigdisp
.bitfield
.disp16
= 1;
8774 bigdisp
.bitfield
.disp32
= 1;
8775 bigdisp
.bitfield
.disp32s
= 1;
8781 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8783 : LONG_MNEM_SUFFIX
));
8784 bigdisp
.bitfield
.disp32
= 1;
8785 if ((flag_code
== CODE_16BIT
) ^ override
)
8787 bigdisp
.bitfield
.disp32
= 0;
8788 bigdisp
.bitfield
.disp16
= 1;
8792 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8795 exp
= &disp_expressions
[i
.disp_operands
];
8796 i
.op
[this_operand
].disps
= exp
;
8798 save_input_line_pointer
= input_line_pointer
;
8799 input_line_pointer
= disp_start
;
8800 END_STRING_AND_SAVE (disp_end
);
8802 #ifndef GCC_ASM_O_HACK
8803 #define GCC_ASM_O_HACK 0
8806 END_STRING_AND_SAVE (disp_end
+ 1);
8807 if (i
.types
[this_operand
].bitfield
.baseIndex
8808 && displacement_string_end
[-1] == '+')
8810 /* This hack is to avoid a warning when using the "o"
8811 constraint within gcc asm statements.
8814 #define _set_tssldt_desc(n,addr,limit,type) \
8815 __asm__ __volatile__ ( \
8817 "movw %w1,2+%0\n\t" \
8819 "movb %b1,4+%0\n\t" \
8820 "movb %4,5+%0\n\t" \
8821 "movb $0,6+%0\n\t" \
8822 "movb %h1,7+%0\n\t" \
8824 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8826 This works great except that the output assembler ends
8827 up looking a bit weird if it turns out that there is
8828 no offset. You end up producing code that looks like:
8841 So here we provide the missing zero. */
8843 *displacement_string_end
= '0';
8846 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8847 if (gotfree_input_line
)
8848 input_line_pointer
= gotfree_input_line
;
8850 exp_seg
= expression (exp
);
8853 if (*input_line_pointer
)
8854 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8856 RESTORE_END_STRING (disp_end
+ 1);
8858 input_line_pointer
= save_input_line_pointer
;
8859 if (gotfree_input_line
)
8861 free (gotfree_input_line
);
8863 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8864 exp
->X_op
= O_illegal
;
8867 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8869 RESTORE_END_STRING (disp_end
);
8875 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8876 i386_operand_type types
, const char *disp_start
)
8878 i386_operand_type bigdisp
;
8881 /* We do this to make sure that the section symbol is in
8882 the symbol table. We will ultimately change the relocation
8883 to be relative to the beginning of the section. */
8884 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8885 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8886 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8888 if (exp
->X_op
!= O_symbol
)
8891 if (S_IS_LOCAL (exp
->X_add_symbol
)
8892 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8893 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8894 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8895 exp
->X_op
= O_subtract
;
8896 exp
->X_op_symbol
= GOT_symbol
;
8897 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8898 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8899 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8900 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8902 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8905 else if (exp
->X_op
== O_absent
8906 || exp
->X_op
== O_illegal
8907 || exp
->X_op
== O_big
)
8910 as_bad (_("missing or invalid displacement expression `%s'"),
8915 else if (flag_code
== CODE_64BIT
8916 && !i
.prefix
[ADDR_PREFIX
]
8917 && exp
->X_op
== O_constant
)
8919 /* Since displacement is signed extended to 64bit, don't allow
8920 disp32 and turn off disp32s if they are out of range. */
8921 i
.types
[this_operand
].bitfield
.disp32
= 0;
8922 if (!fits_in_signed_long (exp
->X_add_number
))
8924 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8925 if (i
.types
[this_operand
].bitfield
.baseindex
)
8927 as_bad (_("0x%lx out range of signed 32bit displacement"),
8928 (long) exp
->X_add_number
);
8934 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8935 else if (exp
->X_op
!= O_constant
8936 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8937 && exp_seg
!= absolute_section
8938 && exp_seg
!= text_section
8939 && exp_seg
!= data_section
8940 && exp_seg
!= bss_section
8941 && exp_seg
!= undefined_section
8942 && !bfd_is_com_section (exp_seg
))
8944 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8949 /* Check if this is a displacement only operand. */
8950 bigdisp
= i
.types
[this_operand
];
8951 bigdisp
.bitfield
.disp8
= 0;
8952 bigdisp
.bitfield
.disp16
= 0;
8953 bigdisp
.bitfield
.disp32
= 0;
8954 bigdisp
.bitfield
.disp32s
= 0;
8955 bigdisp
.bitfield
.disp64
= 0;
8956 if (operand_type_all_zero (&bigdisp
))
8957 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8963 /* Return the active addressing mode, taking address override and
8964 registers forming the address into consideration. Update the
8965 address override prefix if necessary. */
8967 static enum flag_code
8968 i386_addressing_mode (void)
8970 enum flag_code addr_mode
;
8972 if (i
.prefix
[ADDR_PREFIX
])
8973 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8976 addr_mode
= flag_code
;
8978 #if INFER_ADDR_PREFIX
8979 if (i
.mem_operands
== 0)
8981 /* Infer address prefix from the first memory operand. */
8982 const reg_entry
*addr_reg
= i
.base_reg
;
8984 if (addr_reg
== NULL
)
8985 addr_reg
= i
.index_reg
;
8989 if (addr_reg
->reg_num
== RegEip
8990 || addr_reg
->reg_num
== RegEiz
8991 || addr_reg
->reg_type
.bitfield
.dword
)
8992 addr_mode
= CODE_32BIT
;
8993 else if (flag_code
!= CODE_64BIT
8994 && addr_reg
->reg_type
.bitfield
.word
)
8995 addr_mode
= CODE_16BIT
;
8997 if (addr_mode
!= flag_code
)
8999 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9001 /* Change the size of any displacement too. At most one
9002 of Disp16 or Disp32 is set.
9003 FIXME. There doesn't seem to be any real need for
9004 separate Disp16 and Disp32 flags. The same goes for
9005 Imm16 and Imm32. Removing them would probably clean
9006 up the code quite a lot. */
9007 if (flag_code
!= CODE_64BIT
9008 && (i
.types
[this_operand
].bitfield
.disp16
9009 || i
.types
[this_operand
].bitfield
.disp32
))
9010 i
.types
[this_operand
]
9011 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9021 /* Make sure the memory operand we've been dealt is valid.
9022 Return 1 on success, 0 on a failure. */
9025 i386_index_check (const char *operand_string
)
9027 const char *kind
= "base/index";
9028 enum flag_code addr_mode
= i386_addressing_mode ();
9030 if (current_templates
->start
->opcode_modifier
.isstring
9031 && !current_templates
->start
->opcode_modifier
.immext
9032 && (current_templates
->end
[-1].opcode_modifier
.isstring
9035 /* Memory operands of string insns are special in that they only allow
9036 a single register (rDI, rSI, or rBX) as their memory address. */
9037 const reg_entry
*expected_reg
;
9038 static const char *di_si
[][2] =
9044 static const char *bx
[] = { "ebx", "bx", "rbx" };
9046 kind
= "string address";
9048 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9050 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9052 if (!type
.bitfield
.baseindex
9053 || ((!i
.mem_operands
!= !intel_syntax
)
9054 && current_templates
->end
[-1].operand_types
[1]
9055 .bitfield
.baseindex
))
9056 type
= current_templates
->end
[-1].operand_types
[1];
9057 expected_reg
= hash_find (reg_hash
,
9058 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9062 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9064 if (i
.base_reg
!= expected_reg
9066 || operand_type_check (i
.types
[this_operand
], disp
))
9068 /* The second memory operand must have the same size as
9072 && !((addr_mode
== CODE_64BIT
9073 && i
.base_reg
->reg_type
.bitfield
.qword
)
9074 || (addr_mode
== CODE_32BIT
9075 ? i
.base_reg
->reg_type
.bitfield
.dword
9076 : i
.base_reg
->reg_type
.bitfield
.word
)))
9079 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9081 intel_syntax
? '[' : '(',
9083 expected_reg
->reg_name
,
9084 intel_syntax
? ']' : ')');
9091 as_bad (_("`%s' is not a valid %s expression"),
9092 operand_string
, kind
);
9097 if (addr_mode
!= CODE_16BIT
)
9099 /* 32-bit/64-bit checks. */
9101 && (addr_mode
== CODE_64BIT
9102 ? !i
.base_reg
->reg_type
.bitfield
.qword
9103 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9105 || (i
.base_reg
->reg_num
9106 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
9108 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9109 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9110 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9111 && ((addr_mode
== CODE_64BIT
9112 ? !(i
.index_reg
->reg_type
.bitfield
.qword
9113 || i
.index_reg
->reg_num
== RegRiz
)
9114 : !(i
.index_reg
->reg_type
.bitfield
.dword
9115 || i
.index_reg
->reg_num
== RegEiz
))
9116 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9119 /* bndmk, bndldx, and bndstx have special restrictions. */
9120 if (current_templates
->start
->base_opcode
== 0xf30f1b
9121 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9123 /* They cannot use RIP-relative addressing. */
9124 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegRip
)
9126 as_bad (_("`%s' cannot be used here"), operand_string
);
9130 /* bndldx and bndstx ignore their scale factor. */
9131 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9132 && i
.log2_scale_factor
)
9133 as_warn (_("register scaling is being ignored here"));
9138 /* 16-bit checks. */
9140 && (!i
.base_reg
->reg_type
.bitfield
.word
9141 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9143 && (!i
.index_reg
->reg_type
.bitfield
.word
9144 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9146 && i
.base_reg
->reg_num
< 6
9147 && i
.index_reg
->reg_num
>= 6
9148 && i
.log2_scale_factor
== 0))))
9155 /* Handle vector immediates. */
9158 RC_SAE_immediate (const char *imm_start
)
9160 unsigned int match_found
, j
;
9161 const char *pstr
= imm_start
;
9169 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9171 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9175 rc_op
.type
= RC_NamesTable
[j
].type
;
9176 rc_op
.operand
= this_operand
;
9177 i
.rounding
= &rc_op
;
9181 as_bad (_("duplicated `%s'"), imm_start
);
9184 pstr
+= RC_NamesTable
[j
].len
;
9194 as_bad (_("Missing '}': '%s'"), imm_start
);
9197 /* RC/SAE immediate string should contain nothing more. */;
9200 as_bad (_("Junk after '}': '%s'"), imm_start
);
9204 exp
= &im_expressions
[i
.imm_operands
++];
9205 i
.op
[this_operand
].imms
= exp
;
9207 exp
->X_op
= O_constant
;
9208 exp
->X_add_number
= 0;
9209 exp
->X_add_symbol
= (symbolS
*) 0;
9210 exp
->X_op_symbol
= (symbolS
*) 0;
9212 i
.types
[this_operand
].bitfield
.imm8
= 1;
9216 /* Only string instructions can have a second memory operand, so
9217 reduce current_templates to just those if it contains any. */
9219 maybe_adjust_templates (void)
9221 const insn_template
*t
;
9223 gas_assert (i
.mem_operands
== 1);
9225 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9226 if (t
->opcode_modifier
.isstring
)
9229 if (t
< current_templates
->end
)
9231 static templates aux_templates
;
9232 bfd_boolean recheck
;
9234 aux_templates
.start
= t
;
9235 for (; t
< current_templates
->end
; ++t
)
9236 if (!t
->opcode_modifier
.isstring
)
9238 aux_templates
.end
= t
;
9240 /* Determine whether to re-check the first memory operand. */
9241 recheck
= (aux_templates
.start
!= current_templates
->start
9242 || t
!= current_templates
->end
);
9244 current_templates
= &aux_templates
;
9249 if (i
.memop1_string
!= NULL
9250 && i386_index_check (i
.memop1_string
) == 0)
9259 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9263 i386_att_operand (char *operand_string
)
9267 char *op_string
= operand_string
;
9269 if (is_space_char (*op_string
))
9272 /* We check for an absolute prefix (differentiating,
9273 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9274 if (*op_string
== ABSOLUTE_PREFIX
)
9277 if (is_space_char (*op_string
))
9279 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9282 /* Check if operand is a register. */
9283 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
9285 i386_operand_type temp
;
9287 /* Check for a segment override by searching for ':' after a
9288 segment register. */
9290 if (is_space_char (*op_string
))
9292 if (*op_string
== ':'
9293 && (r
->reg_type
.bitfield
.sreg2
9294 || r
->reg_type
.bitfield
.sreg3
))
9299 i
.seg
[i
.mem_operands
] = &es
;
9302 i
.seg
[i
.mem_operands
] = &cs
;
9305 i
.seg
[i
.mem_operands
] = &ss
;
9308 i
.seg
[i
.mem_operands
] = &ds
;
9311 i
.seg
[i
.mem_operands
] = &fs
;
9314 i
.seg
[i
.mem_operands
] = &gs
;
9318 /* Skip the ':' and whitespace. */
9320 if (is_space_char (*op_string
))
9323 if (!is_digit_char (*op_string
)
9324 && !is_identifier_char (*op_string
)
9325 && *op_string
!= '('
9326 && *op_string
!= ABSOLUTE_PREFIX
)
9328 as_bad (_("bad memory operand `%s'"), op_string
);
9331 /* Handle case of %es:*foo. */
9332 if (*op_string
== ABSOLUTE_PREFIX
)
9335 if (is_space_char (*op_string
))
9337 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9339 goto do_memory_reference
;
9342 /* Handle vector operations. */
9343 if (*op_string
== '{')
9345 op_string
= check_VecOperations (op_string
, NULL
);
9346 if (op_string
== NULL
)
9352 as_bad (_("junk `%s' after register"), op_string
);
9356 temp
.bitfield
.baseindex
= 0;
9357 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9359 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9360 i
.op
[this_operand
].regs
= r
;
9363 else if (*op_string
== REGISTER_PREFIX
)
9365 as_bad (_("bad register name `%s'"), op_string
);
9368 else if (*op_string
== IMMEDIATE_PREFIX
)
9371 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
9373 as_bad (_("immediate operand illegal with absolute jump"));
9376 if (!i386_immediate (op_string
))
9379 else if (RC_SAE_immediate (operand_string
))
9381 /* If it is a RC or SAE immediate, do nothing. */
9384 else if (is_digit_char (*op_string
)
9385 || is_identifier_char (*op_string
)
9386 || *op_string
== '"'
9387 || *op_string
== '(')
9389 /* This is a memory reference of some sort. */
9392 /* Start and end of displacement string expression (if found). */
9393 char *displacement_string_start
;
9394 char *displacement_string_end
;
9397 do_memory_reference
:
9398 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
9400 if ((i
.mem_operands
== 1
9401 && !current_templates
->start
->opcode_modifier
.isstring
)
9402 || i
.mem_operands
== 2)
9404 as_bad (_("too many memory references for `%s'"),
9405 current_templates
->start
->name
);
9409 /* Check for base index form. We detect the base index form by
9410 looking for an ')' at the end of the operand, searching
9411 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9413 base_string
= op_string
+ strlen (op_string
);
9415 /* Handle vector operations. */
9416 vop_start
= strchr (op_string
, '{');
9417 if (vop_start
&& vop_start
< base_string
)
9419 if (check_VecOperations (vop_start
, base_string
) == NULL
)
9421 base_string
= vop_start
;
9425 if (is_space_char (*base_string
))
9428 /* If we only have a displacement, set-up for it to be parsed later. */
9429 displacement_string_start
= op_string
;
9430 displacement_string_end
= base_string
+ 1;
9432 if (*base_string
== ')')
9435 unsigned int parens_balanced
= 1;
9436 /* We've already checked that the number of left & right ()'s are
9437 equal, so this loop will not be infinite. */
9441 if (*base_string
== ')')
9443 if (*base_string
== '(')
9446 while (parens_balanced
);
9448 temp_string
= base_string
;
9450 /* Skip past '(' and whitespace. */
9452 if (is_space_char (*base_string
))
9455 if (*base_string
== ','
9456 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
9459 displacement_string_end
= temp_string
;
9461 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9465 base_string
= end_op
;
9466 if (is_space_char (*base_string
))
9470 /* There may be an index reg or scale factor here. */
9471 if (*base_string
== ',')
9474 if (is_space_char (*base_string
))
9477 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
9480 base_string
= end_op
;
9481 if (is_space_char (*base_string
))
9483 if (*base_string
== ',')
9486 if (is_space_char (*base_string
))
9489 else if (*base_string
!= ')')
9491 as_bad (_("expecting `,' or `)' "
9492 "after index register in `%s'"),
9497 else if (*base_string
== REGISTER_PREFIX
)
9499 end_op
= strchr (base_string
, ',');
9502 as_bad (_("bad register name `%s'"), base_string
);
9506 /* Check for scale factor. */
9507 if (*base_string
!= ')')
9509 char *end_scale
= i386_scale (base_string
);
9514 base_string
= end_scale
;
9515 if (is_space_char (*base_string
))
9517 if (*base_string
!= ')')
9519 as_bad (_("expecting `)' "
9520 "after scale factor in `%s'"),
9525 else if (!i
.index_reg
)
9527 as_bad (_("expecting index register or scale factor "
9528 "after `,'; got '%c'"),
9533 else if (*base_string
!= ')')
9535 as_bad (_("expecting `,' or `)' "
9536 "after base register in `%s'"),
9541 else if (*base_string
== REGISTER_PREFIX
)
9543 end_op
= strchr (base_string
, ',');
9546 as_bad (_("bad register name `%s'"), base_string
);
9551 /* If there's an expression beginning the operand, parse it,
9552 assuming displacement_string_start and
9553 displacement_string_end are meaningful. */
9554 if (displacement_string_start
!= displacement_string_end
)
9556 if (!i386_displacement (displacement_string_start
,
9557 displacement_string_end
))
9561 /* Special case for (%dx) while doing input/output op. */
9563 && operand_type_equal (&i
.base_reg
->reg_type
,
9564 ®16_inoutportreg
)
9566 && i
.log2_scale_factor
== 0
9567 && i
.seg
[i
.mem_operands
] == 0
9568 && !operand_type_check (i
.types
[this_operand
], disp
))
9570 i
.types
[this_operand
] = inoutportreg
;
9574 if (i386_index_check (operand_string
) == 0)
9576 i
.types
[this_operand
].bitfield
.mem
= 1;
9577 if (i
.mem_operands
== 0)
9578 i
.memop1_string
= xstrdup (operand_string
);
9583 /* It's not a memory operand; argh! */
9584 as_bad (_("invalid char %s beginning operand %d `%s'"),
9585 output_invalid (*op_string
),
9590 return 1; /* Normal return. */
9593 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9594 that an rs_machine_dependent frag may reach. */
9597 i386_frag_max_var (fragS
*frag
)
9599 /* The only relaxable frags are for jumps.
9600 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9601 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9602 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9605 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9607 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9609 /* STT_GNU_IFUNC symbol must go through PLT. */
9610 if ((symbol_get_bfdsym (fr_symbol
)->flags
9611 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9614 if (!S_IS_EXTERNAL (fr_symbol
))
9615 /* Symbol may be weak or local. */
9616 return !S_IS_WEAK (fr_symbol
);
9618 /* Global symbols with non-default visibility can't be preempted. */
9619 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9622 if (fr_var
!= NO_RELOC
)
9623 switch ((enum bfd_reloc_code_real
) fr_var
)
9625 case BFD_RELOC_386_PLT32
:
9626 case BFD_RELOC_X86_64_PLT32
:
9627 /* Symbol with PLT relocation may be preempted. */
9633 /* Global symbols with default visibility in a shared library may be
9634 preempted by another definition. */
9639 /* md_estimate_size_before_relax()
9641 Called just before relax() for rs_machine_dependent frags. The x86
9642 assembler uses these frags to handle variable size jump
9645 Any symbol that is now undefined will not become defined.
9646 Return the correct fr_subtype in the frag.
9647 Return the initial "guess for variable size of frag" to caller.
9648 The guess is actually the growth beyond the fixed part. Whatever
9649 we do to grow the fixed or variable part contributes to our
9653 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9655 /* We've already got fragP->fr_subtype right; all we have to do is
9656 check for un-relaxable symbols. On an ELF system, we can't relax
9657 an externally visible symbol, because it may be overridden by a
9659 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9660 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9662 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9665 #if defined (OBJ_COFF) && defined (TE_PE)
9666 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9667 && S_IS_WEAK (fragP
->fr_symbol
))
9671 /* Symbol is undefined in this segment, or we need to keep a
9672 reloc so that weak symbols can be overridden. */
9673 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9674 enum bfd_reloc_code_real reloc_type
;
9675 unsigned char *opcode
;
9678 if (fragP
->fr_var
!= NO_RELOC
)
9679 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9681 reloc_type
= BFD_RELOC_16_PCREL
;
9682 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9683 else if (need_plt32_p (fragP
->fr_symbol
))
9684 reloc_type
= BFD_RELOC_X86_64_PLT32
;
9687 reloc_type
= BFD_RELOC_32_PCREL
;
9689 old_fr_fix
= fragP
->fr_fix
;
9690 opcode
= (unsigned char *) fragP
->fr_opcode
;
9692 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9695 /* Make jmp (0xeb) a (d)word displacement jump. */
9697 fragP
->fr_fix
+= size
;
9698 fix_new (fragP
, old_fr_fix
, size
,
9700 fragP
->fr_offset
, 1,
9706 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9708 /* Negate the condition, and branch past an
9709 unconditional jump. */
9712 /* Insert an unconditional jump. */
9714 /* We added two extra opcode bytes, and have a two byte
9716 fragP
->fr_fix
+= 2 + 2;
9717 fix_new (fragP
, old_fr_fix
+ 2, 2,
9719 fragP
->fr_offset
, 1,
9726 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9731 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9733 fragP
->fr_offset
, 1,
9735 fixP
->fx_signed
= 1;
9739 /* This changes the byte-displacement jump 0x7N
9740 to the (d)word-displacement jump 0x0f,0x8N. */
9741 opcode
[1] = opcode
[0] + 0x10;
9742 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9743 /* We've added an opcode byte. */
9744 fragP
->fr_fix
+= 1 + size
;
9745 fix_new (fragP
, old_fr_fix
+ 1, size
,
9747 fragP
->fr_offset
, 1,
9752 BAD_CASE (fragP
->fr_subtype
);
9756 return fragP
->fr_fix
- old_fr_fix
;
9759 /* Guess size depending on current relax state. Initially the relax
9760 state will correspond to a short jump and we return 1, because
9761 the variable part of the frag (the branch offset) is one byte
9762 long. However, we can relax a section more than once and in that
9763 case we must either set fr_subtype back to the unrelaxed state,
9764 or return the value for the appropriate branch. */
9765 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9768 /* Called after relax() is finished.
9770 In: Address of frag.
9771 fr_type == rs_machine_dependent.
9772 fr_subtype is what the address relaxed to.
9774 Out: Any fixSs and constants are set up.
9775 Caller will turn frag into a ".space 0". */
9778 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9781 unsigned char *opcode
;
9782 unsigned char *where_to_put_displacement
= NULL
;
9783 offsetT target_address
;
9784 offsetT opcode_address
;
9785 unsigned int extension
= 0;
9786 offsetT displacement_from_opcode_start
;
9788 opcode
= (unsigned char *) fragP
->fr_opcode
;
9790 /* Address we want to reach in file space. */
9791 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9793 /* Address opcode resides at in file space. */
9794 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9796 /* Displacement from opcode start to fill into instruction. */
9797 displacement_from_opcode_start
= target_address
- opcode_address
;
9799 if ((fragP
->fr_subtype
& BIG
) == 0)
9801 /* Don't have to change opcode. */
9802 extension
= 1; /* 1 opcode + 1 displacement */
9803 where_to_put_displacement
= &opcode
[1];
9807 if (no_cond_jump_promotion
9808 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9809 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9810 _("long jump required"));
9812 switch (fragP
->fr_subtype
)
9814 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9815 extension
= 4; /* 1 opcode + 4 displacement */
9817 where_to_put_displacement
= &opcode
[1];
9820 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9821 extension
= 2; /* 1 opcode + 2 displacement */
9823 where_to_put_displacement
= &opcode
[1];
9826 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9827 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9828 extension
= 5; /* 2 opcode + 4 displacement */
9829 opcode
[1] = opcode
[0] + 0x10;
9830 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9831 where_to_put_displacement
= &opcode
[2];
9834 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9835 extension
= 3; /* 2 opcode + 2 displacement */
9836 opcode
[1] = opcode
[0] + 0x10;
9837 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9838 where_to_put_displacement
= &opcode
[2];
9841 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9846 where_to_put_displacement
= &opcode
[3];
9850 BAD_CASE (fragP
->fr_subtype
);
9855 /* If size if less then four we are sure that the operand fits,
9856 but if it's 4, then it could be that the displacement is larger
9858 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9860 && ((addressT
) (displacement_from_opcode_start
- extension
9861 + ((addressT
) 1 << 31))
9862 > (((addressT
) 2 << 31) - 1)))
9864 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9865 _("jump target out of range"));
9866 /* Make us emit 0. */
9867 displacement_from_opcode_start
= extension
;
9869 /* Now put displacement after opcode. */
9870 md_number_to_chars ((char *) where_to_put_displacement
,
9871 (valueT
) (displacement_from_opcode_start
- extension
),
9872 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9873 fragP
->fr_fix
+= extension
;
9876 /* Apply a fixup (fixP) to segment data, once it has been determined
9877 by our caller that we have all the info we need to fix it up.
9879 Parameter valP is the pointer to the value of the bits.
9881 On the 386, immediates, displacements, and data pointers are all in
9882 the same (little-endian) format, so we don't need to care about which
9886 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9888 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9889 valueT value
= *valP
;
9891 #if !defined (TE_Mach)
9894 switch (fixP
->fx_r_type
)
9900 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9903 case BFD_RELOC_X86_64_32S
:
9904 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9907 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9910 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9915 if (fixP
->fx_addsy
!= NULL
9916 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9917 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9918 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9919 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9920 && !use_rela_relocations
)
9922 /* This is a hack. There should be a better way to handle this.
9923 This covers for the fact that bfd_install_relocation will
9924 subtract the current location (for partial_inplace, PC relative
9925 relocations); see more below. */
9929 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9932 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9934 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9937 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9940 || (symbol_section_p (fixP
->fx_addsy
)
9941 && sym_seg
!= absolute_section
))
9942 && !generic_force_reloc (fixP
))
9944 /* Yes, we add the values in twice. This is because
9945 bfd_install_relocation subtracts them out again. I think
9946 bfd_install_relocation is broken, but I don't dare change
9948 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9952 #if defined (OBJ_COFF) && defined (TE_PE)
9953 /* For some reason, the PE format does not store a
9954 section address offset for a PC relative symbol. */
9955 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9956 || S_IS_WEAK (fixP
->fx_addsy
))
9957 value
+= md_pcrel_from (fixP
);
9960 #if defined (OBJ_COFF) && defined (TE_PE)
9961 if (fixP
->fx_addsy
!= NULL
9962 && S_IS_WEAK (fixP
->fx_addsy
)
9963 /* PR 16858: Do not modify weak function references. */
9964 && ! fixP
->fx_pcrel
)
9966 #if !defined (TE_PEP)
9967 /* For x86 PE weak function symbols are neither PC-relative
9968 nor do they set S_IS_FUNCTION. So the only reliable way
9969 to detect them is to check the flags of their containing
9971 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9972 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9976 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9980 /* Fix a few things - the dynamic linker expects certain values here,
9981 and we must not disappoint it. */
9982 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9983 if (IS_ELF
&& fixP
->fx_addsy
)
9984 switch (fixP
->fx_r_type
)
9986 case BFD_RELOC_386_PLT32
:
9987 case BFD_RELOC_X86_64_PLT32
:
9988 /* Make the jump instruction point to the address of the operand. At
9989 runtime we merely add the offset to the actual PLT entry. */
9993 case BFD_RELOC_386_TLS_GD
:
9994 case BFD_RELOC_386_TLS_LDM
:
9995 case BFD_RELOC_386_TLS_IE_32
:
9996 case BFD_RELOC_386_TLS_IE
:
9997 case BFD_RELOC_386_TLS_GOTIE
:
9998 case BFD_RELOC_386_TLS_GOTDESC
:
9999 case BFD_RELOC_X86_64_TLSGD
:
10000 case BFD_RELOC_X86_64_TLSLD
:
10001 case BFD_RELOC_X86_64_GOTTPOFF
:
10002 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10003 value
= 0; /* Fully resolved at runtime. No addend. */
10005 case BFD_RELOC_386_TLS_LE
:
10006 case BFD_RELOC_386_TLS_LDO_32
:
10007 case BFD_RELOC_386_TLS_LE_32
:
10008 case BFD_RELOC_X86_64_DTPOFF32
:
10009 case BFD_RELOC_X86_64_DTPOFF64
:
10010 case BFD_RELOC_X86_64_TPOFF32
:
10011 case BFD_RELOC_X86_64_TPOFF64
:
10012 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10015 case BFD_RELOC_386_TLS_DESC_CALL
:
10016 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10017 value
= 0; /* Fully resolved at runtime. No addend. */
10018 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10022 case BFD_RELOC_VTABLE_INHERIT
:
10023 case BFD_RELOC_VTABLE_ENTRY
:
10030 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10032 #endif /* !defined (TE_Mach) */
10034 /* Are we finished with this relocation now? */
10035 if (fixP
->fx_addsy
== NULL
)
10037 #if defined (OBJ_COFF) && defined (TE_PE)
10038 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10041 /* Remember value for tc_gen_reloc. */
10042 fixP
->fx_addnumber
= value
;
10043 /* Clear out the frag for now. */
10047 else if (use_rela_relocations
)
10049 fixP
->fx_no_overflow
= 1;
10050 /* Remember value for tc_gen_reloc. */
10051 fixP
->fx_addnumber
= value
;
10055 md_number_to_chars (p
, value
, fixP
->fx_size
);
10059 md_atof (int type
, char *litP
, int *sizeP
)
10061 /* This outputs the LITTLENUMs in REVERSE order;
10062 in accord with the bigendian 386. */
10063 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10066 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10069 output_invalid (int c
)
10072 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10075 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10076 "(0x%x)", (unsigned char) c
);
10077 return output_invalid_buf
;
10080 /* REG_STRING starts *before* REGISTER_PREFIX. */
10082 static const reg_entry
*
10083 parse_real_register (char *reg_string
, char **end_op
)
10085 char *s
= reg_string
;
10087 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10088 const reg_entry
*r
;
10090 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10091 if (*s
== REGISTER_PREFIX
)
10094 if (is_space_char (*s
))
10097 p
= reg_name_given
;
10098 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10100 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10101 return (const reg_entry
*) NULL
;
10105 /* For naked regs, make sure that we are not dealing with an identifier.
10106 This prevents confusing an identifier like `eax_var' with register
10108 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10109 return (const reg_entry
*) NULL
;
10113 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10115 /* Handle floating point regs, allowing spaces in the (i) part. */
10116 if (r
== i386_regtab
/* %st is first entry of table */)
10118 if (is_space_char (*s
))
10123 if (is_space_char (*s
))
10125 if (*s
>= '0' && *s
<= '7')
10127 int fpr
= *s
- '0';
10129 if (is_space_char (*s
))
10134 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10139 /* We have "%st(" then garbage. */
10140 return (const reg_entry
*) NULL
;
10144 if (r
== NULL
|| allow_pseudo_reg
)
10147 if (operand_type_all_zero (&r
->reg_type
))
10148 return (const reg_entry
*) NULL
;
10150 if ((r
->reg_type
.bitfield
.dword
10151 || r
->reg_type
.bitfield
.sreg3
10152 || r
->reg_type
.bitfield
.control
10153 || r
->reg_type
.bitfield
.debug
10154 || r
->reg_type
.bitfield
.test
)
10155 && !cpu_arch_flags
.bitfield
.cpui386
)
10156 return (const reg_entry
*) NULL
;
10158 if (r
->reg_type
.bitfield
.tbyte
10159 && !cpu_arch_flags
.bitfield
.cpu8087
10160 && !cpu_arch_flags
.bitfield
.cpu287
10161 && !cpu_arch_flags
.bitfield
.cpu387
)
10162 return (const reg_entry
*) NULL
;
10164 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpuregmmx
)
10165 return (const reg_entry
*) NULL
;
10167 if (r
->reg_type
.bitfield
.xmmword
&& !cpu_arch_flags
.bitfield
.cpuregxmm
)
10168 return (const reg_entry
*) NULL
;
10170 if (r
->reg_type
.bitfield
.ymmword
&& !cpu_arch_flags
.bitfield
.cpuregymm
)
10171 return (const reg_entry
*) NULL
;
10173 if (r
->reg_type
.bitfield
.zmmword
&& !cpu_arch_flags
.bitfield
.cpuregzmm
)
10174 return (const reg_entry
*) NULL
;
10176 if (r
->reg_type
.bitfield
.regmask
10177 && !cpu_arch_flags
.bitfield
.cpuregmask
)
10178 return (const reg_entry
*) NULL
;
10180 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10181 if (!allow_index_reg
10182 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
10183 return (const reg_entry
*) NULL
;
10185 /* Upper 16 vector register is only available with VREX in 64bit
10187 if ((r
->reg_flags
& RegVRex
))
10189 if (i
.vec_encoding
== vex_encoding_default
)
10190 i
.vec_encoding
= vex_encoding_evex
;
10192 if (!cpu_arch_flags
.bitfield
.cpuvrex
10193 || i
.vec_encoding
!= vex_encoding_evex
10194 || flag_code
!= CODE_64BIT
)
10195 return (const reg_entry
*) NULL
;
10198 if (((r
->reg_flags
& (RegRex64
| RegRex
))
10199 || r
->reg_type
.bitfield
.qword
)
10200 && (!cpu_arch_flags
.bitfield
.cpulm
10201 || !operand_type_equal (&r
->reg_type
, &control
))
10202 && flag_code
!= CODE_64BIT
)
10203 return (const reg_entry
*) NULL
;
10205 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10206 return (const reg_entry
*) NULL
;
10211 /* REG_STRING starts *before* REGISTER_PREFIX. */
10213 static const reg_entry
*
10214 parse_register (char *reg_string
, char **end_op
)
10216 const reg_entry
*r
;
10218 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10219 r
= parse_real_register (reg_string
, end_op
);
10224 char *save
= input_line_pointer
;
10228 input_line_pointer
= reg_string
;
10229 c
= get_symbol_name (®_string
);
10230 symbolP
= symbol_find (reg_string
);
10231 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10233 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10235 know (e
->X_op
== O_register
);
10236 know (e
->X_add_number
>= 0
10237 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10238 r
= i386_regtab
+ e
->X_add_number
;
10239 if ((r
->reg_flags
& RegVRex
))
10240 i
.vec_encoding
= vex_encoding_evex
;
10241 *end_op
= input_line_pointer
;
10243 *input_line_pointer
= c
;
10244 input_line_pointer
= save
;
10250 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10252 const reg_entry
*r
;
10253 char *end
= input_line_pointer
;
10256 r
= parse_register (name
, &input_line_pointer
);
10257 if (r
&& end
<= input_line_pointer
)
10259 *nextcharP
= *input_line_pointer
;
10260 *input_line_pointer
= 0;
10261 e
->X_op
= O_register
;
10262 e
->X_add_number
= r
- i386_regtab
;
10265 input_line_pointer
= end
;
10267 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
10271 md_operand (expressionS
*e
)
10274 const reg_entry
*r
;
10276 switch (*input_line_pointer
)
10278 case REGISTER_PREFIX
:
10279 r
= parse_real_register (input_line_pointer
, &end
);
10282 e
->X_op
= O_register
;
10283 e
->X_add_number
= r
- i386_regtab
;
10284 input_line_pointer
= end
;
10289 gas_assert (intel_syntax
);
10290 end
= input_line_pointer
++;
10292 if (*input_line_pointer
== ']')
10294 ++input_line_pointer
;
10295 e
->X_op_symbol
= make_expr_symbol (e
);
10296 e
->X_add_symbol
= NULL
;
10297 e
->X_add_number
= 0;
10302 e
->X_op
= O_absent
;
10303 input_line_pointer
= end
;
10310 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10311 const char *md_shortopts
= "kVQ:sqnO::";
10313 const char *md_shortopts
= "qnO::";
10316 #define OPTION_32 (OPTION_MD_BASE + 0)
10317 #define OPTION_64 (OPTION_MD_BASE + 1)
10318 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10319 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10320 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10321 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10322 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10323 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10324 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10325 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
10326 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10327 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10328 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10329 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10330 #define OPTION_X32 (OPTION_MD_BASE + 14)
10331 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10332 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10333 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10334 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10335 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10336 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10337 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10338 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10339 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10340 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10341 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
10343 struct option md_longopts
[] =
10345 {"32", no_argument
, NULL
, OPTION_32
},
10346 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10347 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10348 {"64", no_argument
, NULL
, OPTION_64
},
10350 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10351 {"x32", no_argument
, NULL
, OPTION_X32
},
10352 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10354 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
10355 {"march", required_argument
, NULL
, OPTION_MARCH
},
10356 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10357 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
10358 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
10359 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
10360 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
10361 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
10362 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
10363 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
10364 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
10365 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
10366 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
10367 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
10368 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
10369 # if defined (TE_PE) || defined (TE_PEP)
10370 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
10372 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
10373 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
10374 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
10375 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
10376 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
10377 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
10378 {NULL
, no_argument
, NULL
, 0}
10380 size_t md_longopts_size
= sizeof (md_longopts
);
10383 md_parse_option (int c
, const char *arg
)
10386 char *arch
, *next
, *saved
;
10391 optimize_align_code
= 0;
10395 quiet_warnings
= 1;
10398 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10399 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10400 should be emitted or not. FIXME: Not implemented. */
10404 /* -V: SVR4 argument to print version ID. */
10406 print_version_id ();
10409 /* -k: Ignore for FreeBSD compatibility. */
10414 /* -s: On i386 Solaris, this tells the native assembler to use
10415 .stab instead of .stab.excl. We always use .stab anyhow. */
10418 case OPTION_MSHARED
:
10422 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10423 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10426 const char **list
, **l
;
10428 list
= bfd_target_list ();
10429 for (l
= list
; *l
!= NULL
; l
++)
10430 if (CONST_STRNEQ (*l
, "elf64-x86-64")
10431 || strcmp (*l
, "coff-x86-64") == 0
10432 || strcmp (*l
, "pe-x86-64") == 0
10433 || strcmp (*l
, "pei-x86-64") == 0
10434 || strcmp (*l
, "mach-o-x86-64") == 0)
10436 default_arch
= "x86_64";
10440 as_fatal (_("no compiled in support for x86_64"));
10446 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10450 const char **list
, **l
;
10452 list
= bfd_target_list ();
10453 for (l
= list
; *l
!= NULL
; l
++)
10454 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
10456 default_arch
= "x86_64:32";
10460 as_fatal (_("no compiled in support for 32bit x86_64"));
10464 as_fatal (_("32bit x86_64 is only supported for ELF"));
10469 default_arch
= "i386";
10472 case OPTION_DIVIDE
:
10473 #ifdef SVR4_COMMENT_CHARS
10478 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
10480 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
10484 i386_comment_chars
= n
;
10490 saved
= xstrdup (arg
);
10492 /* Allow -march=+nosse. */
10498 as_fatal (_("invalid -march= option: `%s'"), arg
);
10499 next
= strchr (arch
, '+');
10502 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10504 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
10507 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10510 cpu_arch_name
= cpu_arch
[j
].name
;
10511 cpu_sub_arch_name
= NULL
;
10512 cpu_arch_flags
= cpu_arch
[j
].flags
;
10513 cpu_arch_isa
= cpu_arch
[j
].type
;
10514 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
10515 if (!cpu_arch_tune_set
)
10517 cpu_arch_tune
= cpu_arch_isa
;
10518 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10522 else if (*cpu_arch
[j
].name
== '.'
10523 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
10525 /* ISA extension. */
10526 i386_cpu_flags flags
;
10528 flags
= cpu_flags_or (cpu_arch_flags
,
10529 cpu_arch
[j
].flags
);
10531 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10533 if (cpu_sub_arch_name
)
10535 char *name
= cpu_sub_arch_name
;
10536 cpu_sub_arch_name
= concat (name
,
10538 (const char *) NULL
);
10542 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
10543 cpu_arch_flags
= flags
;
10544 cpu_arch_isa_flags
= flags
;
10550 if (j
>= ARRAY_SIZE (cpu_arch
))
10552 /* Disable an ISA extension. */
10553 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10554 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
10556 i386_cpu_flags flags
;
10558 flags
= cpu_flags_and_not (cpu_arch_flags
,
10559 cpu_noarch
[j
].flags
);
10560 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10562 if (cpu_sub_arch_name
)
10564 char *name
= cpu_sub_arch_name
;
10565 cpu_sub_arch_name
= concat (arch
,
10566 (const char *) NULL
);
10570 cpu_sub_arch_name
= xstrdup (arch
);
10571 cpu_arch_flags
= flags
;
10572 cpu_arch_isa_flags
= flags
;
10577 if (j
>= ARRAY_SIZE (cpu_noarch
))
10578 j
= ARRAY_SIZE (cpu_arch
);
10581 if (j
>= ARRAY_SIZE (cpu_arch
))
10582 as_fatal (_("invalid -march= option: `%s'"), arg
);
10586 while (next
!= NULL
);
10592 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10593 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10595 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
10597 cpu_arch_tune_set
= 1;
10598 cpu_arch_tune
= cpu_arch
[j
].type
;
10599 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10603 if (j
>= ARRAY_SIZE (cpu_arch
))
10604 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10607 case OPTION_MMNEMONIC
:
10608 if (strcasecmp (arg
, "att") == 0)
10609 intel_mnemonic
= 0;
10610 else if (strcasecmp (arg
, "intel") == 0)
10611 intel_mnemonic
= 1;
10613 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10616 case OPTION_MSYNTAX
:
10617 if (strcasecmp (arg
, "att") == 0)
10619 else if (strcasecmp (arg
, "intel") == 0)
10622 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10625 case OPTION_MINDEX_REG
:
10626 allow_index_reg
= 1;
10629 case OPTION_MNAKED_REG
:
10630 allow_naked_reg
= 1;
10633 case OPTION_MOLD_GCC
:
10637 case OPTION_MSSE2AVX
:
10641 case OPTION_MSSE_CHECK
:
10642 if (strcasecmp (arg
, "error") == 0)
10643 sse_check
= check_error
;
10644 else if (strcasecmp (arg
, "warning") == 0)
10645 sse_check
= check_warning
;
10646 else if (strcasecmp (arg
, "none") == 0)
10647 sse_check
= check_none
;
10649 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10652 case OPTION_MOPERAND_CHECK
:
10653 if (strcasecmp (arg
, "error") == 0)
10654 operand_check
= check_error
;
10655 else if (strcasecmp (arg
, "warning") == 0)
10656 operand_check
= check_warning
;
10657 else if (strcasecmp (arg
, "none") == 0)
10658 operand_check
= check_none
;
10660 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10663 case OPTION_MAVXSCALAR
:
10664 if (strcasecmp (arg
, "128") == 0)
10665 avxscalar
= vex128
;
10666 else if (strcasecmp (arg
, "256") == 0)
10667 avxscalar
= vex256
;
10669 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10672 case OPTION_MADD_BND_PREFIX
:
10673 add_bnd_prefix
= 1;
10676 case OPTION_MEVEXLIG
:
10677 if (strcmp (arg
, "128") == 0)
10678 evexlig
= evexl128
;
10679 else if (strcmp (arg
, "256") == 0)
10680 evexlig
= evexl256
;
10681 else if (strcmp (arg
, "512") == 0)
10682 evexlig
= evexl512
;
10684 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10687 case OPTION_MEVEXRCIG
:
10688 if (strcmp (arg
, "rne") == 0)
10690 else if (strcmp (arg
, "rd") == 0)
10692 else if (strcmp (arg
, "ru") == 0)
10694 else if (strcmp (arg
, "rz") == 0)
10697 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10700 case OPTION_MEVEXWIG
:
10701 if (strcmp (arg
, "0") == 0)
10703 else if (strcmp (arg
, "1") == 0)
10706 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10709 # if defined (TE_PE) || defined (TE_PEP)
10710 case OPTION_MBIG_OBJ
:
10715 case OPTION_MOMIT_LOCK_PREFIX
:
10716 if (strcasecmp (arg
, "yes") == 0)
10717 omit_lock_prefix
= 1;
10718 else if (strcasecmp (arg
, "no") == 0)
10719 omit_lock_prefix
= 0;
10721 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10724 case OPTION_MFENCE_AS_LOCK_ADD
:
10725 if (strcasecmp (arg
, "yes") == 0)
10727 else if (strcasecmp (arg
, "no") == 0)
10730 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10733 case OPTION_MRELAX_RELOCATIONS
:
10734 if (strcasecmp (arg
, "yes") == 0)
10735 generate_relax_relocations
= 1;
10736 else if (strcasecmp (arg
, "no") == 0)
10737 generate_relax_relocations
= 0;
10739 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10742 case OPTION_MAMD64
:
10746 case OPTION_MINTEL64
:
10754 /* Turn off -Os. */
10755 optimize_for_space
= 0;
10757 else if (*arg
== 's')
10759 optimize_for_space
= 1;
10760 /* Turn on all encoding optimizations. */
10765 optimize
= atoi (arg
);
10766 /* Turn off -Os. */
10767 optimize_for_space
= 0;
10777 #define MESSAGE_TEMPLATE \
10781 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10782 int *left_p
, const char *name
, int len
)
10784 int size
= sizeof (MESSAGE_TEMPLATE
);
10785 int left
= *left_p
;
10787 /* Reserve 2 spaces for ", " or ",\0" */
10790 /* Check if there is any room. */
10798 p
= mempcpy (p
, name
, len
);
10802 /* Output the current message now and start a new one. */
10805 fprintf (stream
, "%s\n", message
);
10807 left
= size
- (start
- message
) - len
- 2;
10809 gas_assert (left
>= 0);
10811 p
= mempcpy (p
, name
, len
);
10819 show_arch (FILE *stream
, int ext
, int check
)
10821 static char message
[] = MESSAGE_TEMPLATE
;
10822 char *start
= message
+ 27;
10824 int size
= sizeof (MESSAGE_TEMPLATE
);
10831 left
= size
- (start
- message
);
10832 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10834 /* Should it be skipped? */
10835 if (cpu_arch
[j
].skip
)
10838 name
= cpu_arch
[j
].name
;
10839 len
= cpu_arch
[j
].len
;
10842 /* It is an extension. Skip if we aren't asked to show it. */
10853 /* It is an processor. Skip if we show only extension. */
10856 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10858 /* It is an impossible processor - skip. */
10862 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10865 /* Display disabled extensions. */
10867 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10869 name
= cpu_noarch
[j
].name
;
10870 len
= cpu_noarch
[j
].len
;
10871 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10876 fprintf (stream
, "%s\n", message
);
10880 md_show_usage (FILE *stream
)
10882 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10883 fprintf (stream
, _("\
10885 -V print assembler version number\n\
10888 fprintf (stream
, _("\
10889 -n Do not optimize code alignment\n\
10890 -q quieten some warnings\n"));
10891 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10892 fprintf (stream
, _("\
10895 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10896 || defined (TE_PE) || defined (TE_PEP))
10897 fprintf (stream
, _("\
10898 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10900 #ifdef SVR4_COMMENT_CHARS
10901 fprintf (stream
, _("\
10902 --divide do not treat `/' as a comment character\n"));
10904 fprintf (stream
, _("\
10905 --divide ignored\n"));
10907 fprintf (stream
, _("\
10908 -march=CPU[,+EXTENSION...]\n\
10909 generate code for CPU and EXTENSION, CPU is one of:\n"));
10910 show_arch (stream
, 0, 1);
10911 fprintf (stream
, _("\
10912 EXTENSION is combination of:\n"));
10913 show_arch (stream
, 1, 0);
10914 fprintf (stream
, _("\
10915 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10916 show_arch (stream
, 0, 0);
10917 fprintf (stream
, _("\
10918 -msse2avx encode SSE instructions with VEX prefix\n"));
10919 fprintf (stream
, _("\
10920 -msse-check=[none|error|warning]\n\
10921 check SSE instructions\n"));
10922 fprintf (stream
, _("\
10923 -moperand-check=[none|error|warning]\n\
10924 check operand combinations for validity\n"));
10925 fprintf (stream
, _("\
10926 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10928 fprintf (stream
, _("\
10929 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10931 fprintf (stream
, _("\
10932 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10933 for EVEX.W bit ignored instructions\n"));
10934 fprintf (stream
, _("\
10935 -mevexrcig=[rne|rd|ru|rz]\n\
10936 encode EVEX instructions with specific EVEX.RC value\n\
10937 for SAE-only ignored instructions\n"));
10938 fprintf (stream
, _("\
10939 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10940 fprintf (stream
, _("\
10941 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10942 fprintf (stream
, _("\
10943 -mindex-reg support pseudo index registers\n"));
10944 fprintf (stream
, _("\
10945 -mnaked-reg don't require `%%' prefix for registers\n"));
10946 fprintf (stream
, _("\
10947 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10948 fprintf (stream
, _("\
10949 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10950 fprintf (stream
, _("\
10951 -mshared disable branch optimization for shared code\n"));
10952 # if defined (TE_PE) || defined (TE_PEP)
10953 fprintf (stream
, _("\
10954 -mbig-obj generate big object files\n"));
10956 fprintf (stream
, _("\
10957 -momit-lock-prefix=[no|yes]\n\
10958 strip all lock prefixes\n"));
10959 fprintf (stream
, _("\
10960 -mfence-as-lock-add=[no|yes]\n\
10961 encode lfence, mfence and sfence as\n\
10962 lock addl $0x0, (%%{re}sp)\n"));
10963 fprintf (stream
, _("\
10964 -mrelax-relocations=[no|yes]\n\
10965 generate relax relocations\n"));
10966 fprintf (stream
, _("\
10967 -mamd64 accept only AMD64 ISA\n"));
10968 fprintf (stream
, _("\
10969 -mintel64 accept only Intel64 ISA\n"));
10972 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10973 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10974 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10976 /* Pick the target format to use. */
10979 i386_target_format (void)
10981 if (!strncmp (default_arch
, "x86_64", 6))
10983 update_code_flag (CODE_64BIT
, 1);
10984 if (default_arch
[6] == '\0')
10985 x86_elf_abi
= X86_64_ABI
;
10987 x86_elf_abi
= X86_64_X32_ABI
;
10989 else if (!strcmp (default_arch
, "i386"))
10990 update_code_flag (CODE_32BIT
, 1);
10991 else if (!strcmp (default_arch
, "iamcu"))
10993 update_code_flag (CODE_32BIT
, 1);
10994 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10996 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10997 cpu_arch_name
= "iamcu";
10998 cpu_sub_arch_name
= NULL
;
10999 cpu_arch_flags
= iamcu_flags
;
11000 cpu_arch_isa
= PROCESSOR_IAMCU
;
11001 cpu_arch_isa_flags
= iamcu_flags
;
11002 if (!cpu_arch_tune_set
)
11004 cpu_arch_tune
= cpu_arch_isa
;
11005 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11008 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11009 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11013 as_fatal (_("unknown architecture"));
11015 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11016 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11017 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11018 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11020 switch (OUTPUT_FLAVOR
)
11022 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11023 case bfd_target_aout_flavour
:
11024 return AOUT_TARGET_FORMAT
;
11026 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11027 # if defined (TE_PE) || defined (TE_PEP)
11028 case bfd_target_coff_flavour
:
11029 if (flag_code
== CODE_64BIT
)
11030 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11033 # elif defined (TE_GO32)
11034 case bfd_target_coff_flavour
:
11035 return "coff-go32";
11037 case bfd_target_coff_flavour
:
11038 return "coff-i386";
11041 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11042 case bfd_target_elf_flavour
:
11044 const char *format
;
11046 switch (x86_elf_abi
)
11049 format
= ELF_TARGET_FORMAT
;
11052 use_rela_relocations
= 1;
11054 format
= ELF_TARGET_FORMAT64
;
11056 case X86_64_X32_ABI
:
11057 use_rela_relocations
= 1;
11059 disallow_64bit_reloc
= 1;
11060 format
= ELF_TARGET_FORMAT32
;
11063 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11065 if (x86_elf_abi
!= X86_64_ABI
)
11066 as_fatal (_("Intel L1OM is 64bit only"));
11067 return ELF_TARGET_L1OM_FORMAT
;
11069 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11071 if (x86_elf_abi
!= X86_64_ABI
)
11072 as_fatal (_("Intel K1OM is 64bit only"));
11073 return ELF_TARGET_K1OM_FORMAT
;
11075 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11077 if (x86_elf_abi
!= I386_ABI
)
11078 as_fatal (_("Intel MCU is 32bit only"));
11079 return ELF_TARGET_IAMCU_FORMAT
;
11085 #if defined (OBJ_MACH_O)
11086 case bfd_target_mach_o_flavour
:
11087 if (flag_code
== CODE_64BIT
)
11089 use_rela_relocations
= 1;
11091 return "mach-o-x86-64";
11094 return "mach-o-i386";
11102 #endif /* OBJ_MAYBE_ more than one */
11105 md_undefined_symbol (char *name
)
11107 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11108 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11109 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11110 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11114 if (symbol_find (name
))
11115 as_bad (_("GOT already in symbol table"));
11116 GOT_symbol
= symbol_new (name
, undefined_section
,
11117 (valueT
) 0, &zero_address_frag
);
11124 /* Round up a section size to the appropriate boundary. */
11127 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11129 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11130 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11132 /* For a.out, force the section size to be aligned. If we don't do
11133 this, BFD will align it for us, but it will not write out the
11134 final bytes of the section. This may be a bug in BFD, but it is
11135 easier to fix it here since that is how the other a.out targets
11139 align
= bfd_get_section_alignment (stdoutput
, segment
);
11140 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11147 /* On the i386, PC-relative offsets are relative to the start of the
11148 next instruction. That is, the address of the offset, plus its
11149 size, since the offset is always the last part of the insn. */
11152 md_pcrel_from (fixS
*fixP
)
11154 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11160 s_bss (int ignore ATTRIBUTE_UNUSED
)
11164 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11166 obj_elf_section_change_hook ();
11168 temp
= get_absolute_expression ();
11169 subseg_set (bss_section
, (subsegT
) temp
);
11170 demand_empty_rest_of_line ();
11176 i386_validate_fix (fixS
*fixp
)
11178 if (fixp
->fx_subsy
)
11180 if (fixp
->fx_subsy
== GOT_symbol
)
11182 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11186 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11187 if (fixp
->fx_tcbit2
)
11188 fixp
->fx_r_type
= (fixp
->fx_tcbit
11189 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11190 : BFD_RELOC_X86_64_GOTPCRELX
);
11193 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11198 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11200 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11202 fixp
->fx_subsy
= 0;
11205 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11206 else if (!object_64bit
)
11208 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11209 && fixp
->fx_tcbit2
)
11210 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11216 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11219 bfd_reloc_code_real_type code
;
11221 switch (fixp
->fx_r_type
)
11223 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11224 case BFD_RELOC_SIZE32
:
11225 case BFD_RELOC_SIZE64
:
11226 if (S_IS_DEFINED (fixp
->fx_addsy
)
11227 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
11229 /* Resolve size relocation against local symbol to size of
11230 the symbol plus addend. */
11231 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
11232 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
11233 && !fits_in_unsigned_long (value
))
11234 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11235 _("symbol size computation overflow"));
11236 fixp
->fx_addsy
= NULL
;
11237 fixp
->fx_subsy
= NULL
;
11238 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
11242 /* Fall through. */
11244 case BFD_RELOC_X86_64_PLT32
:
11245 case BFD_RELOC_X86_64_GOT32
:
11246 case BFD_RELOC_X86_64_GOTPCREL
:
11247 case BFD_RELOC_X86_64_GOTPCRELX
:
11248 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11249 case BFD_RELOC_386_PLT32
:
11250 case BFD_RELOC_386_GOT32
:
11251 case BFD_RELOC_386_GOT32X
:
11252 case BFD_RELOC_386_GOTOFF
:
11253 case BFD_RELOC_386_GOTPC
:
11254 case BFD_RELOC_386_TLS_GD
:
11255 case BFD_RELOC_386_TLS_LDM
:
11256 case BFD_RELOC_386_TLS_LDO_32
:
11257 case BFD_RELOC_386_TLS_IE_32
:
11258 case BFD_RELOC_386_TLS_IE
:
11259 case BFD_RELOC_386_TLS_GOTIE
:
11260 case BFD_RELOC_386_TLS_LE_32
:
11261 case BFD_RELOC_386_TLS_LE
:
11262 case BFD_RELOC_386_TLS_GOTDESC
:
11263 case BFD_RELOC_386_TLS_DESC_CALL
:
11264 case BFD_RELOC_X86_64_TLSGD
:
11265 case BFD_RELOC_X86_64_TLSLD
:
11266 case BFD_RELOC_X86_64_DTPOFF32
:
11267 case BFD_RELOC_X86_64_DTPOFF64
:
11268 case BFD_RELOC_X86_64_GOTTPOFF
:
11269 case BFD_RELOC_X86_64_TPOFF32
:
11270 case BFD_RELOC_X86_64_TPOFF64
:
11271 case BFD_RELOC_X86_64_GOTOFF64
:
11272 case BFD_RELOC_X86_64_GOTPC32
:
11273 case BFD_RELOC_X86_64_GOT64
:
11274 case BFD_RELOC_X86_64_GOTPCREL64
:
11275 case BFD_RELOC_X86_64_GOTPC64
:
11276 case BFD_RELOC_X86_64_GOTPLT64
:
11277 case BFD_RELOC_X86_64_PLTOFF64
:
11278 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11279 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11280 case BFD_RELOC_RVA
:
11281 case BFD_RELOC_VTABLE_ENTRY
:
11282 case BFD_RELOC_VTABLE_INHERIT
:
11284 case BFD_RELOC_32_SECREL
:
11286 code
= fixp
->fx_r_type
;
11288 case BFD_RELOC_X86_64_32S
:
11289 if (!fixp
->fx_pcrel
)
11291 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11292 code
= fixp
->fx_r_type
;
11295 /* Fall through. */
11297 if (fixp
->fx_pcrel
)
11299 switch (fixp
->fx_size
)
11302 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11303 _("can not do %d byte pc-relative relocation"),
11305 code
= BFD_RELOC_32_PCREL
;
11307 case 1: code
= BFD_RELOC_8_PCREL
; break;
11308 case 2: code
= BFD_RELOC_16_PCREL
; break;
11309 case 4: code
= BFD_RELOC_32_PCREL
; break;
11311 case 8: code
= BFD_RELOC_64_PCREL
; break;
11317 switch (fixp
->fx_size
)
11320 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11321 _("can not do %d byte relocation"),
11323 code
= BFD_RELOC_32
;
11325 case 1: code
= BFD_RELOC_8
; break;
11326 case 2: code
= BFD_RELOC_16
; break;
11327 case 4: code
= BFD_RELOC_32
; break;
11329 case 8: code
= BFD_RELOC_64
; break;
11336 if ((code
== BFD_RELOC_32
11337 || code
== BFD_RELOC_32_PCREL
11338 || code
== BFD_RELOC_X86_64_32S
)
11340 && fixp
->fx_addsy
== GOT_symbol
)
11343 code
= BFD_RELOC_386_GOTPC
;
11345 code
= BFD_RELOC_X86_64_GOTPC32
;
11347 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
11349 && fixp
->fx_addsy
== GOT_symbol
)
11351 code
= BFD_RELOC_X86_64_GOTPC64
;
11354 rel
= XNEW (arelent
);
11355 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
11356 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11358 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11360 if (!use_rela_relocations
)
11362 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11363 vtable entry to be used in the relocation's section offset. */
11364 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11365 rel
->address
= fixp
->fx_offset
;
11366 #if defined (OBJ_COFF) && defined (TE_PE)
11367 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
11368 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
11373 /* Use the rela in 64bit mode. */
11376 if (disallow_64bit_reloc
)
11379 case BFD_RELOC_X86_64_DTPOFF64
:
11380 case BFD_RELOC_X86_64_TPOFF64
:
11381 case BFD_RELOC_64_PCREL
:
11382 case BFD_RELOC_X86_64_GOTOFF64
:
11383 case BFD_RELOC_X86_64_GOT64
:
11384 case BFD_RELOC_X86_64_GOTPCREL64
:
11385 case BFD_RELOC_X86_64_GOTPC64
:
11386 case BFD_RELOC_X86_64_GOTPLT64
:
11387 case BFD_RELOC_X86_64_PLTOFF64
:
11388 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11389 _("cannot represent relocation type %s in x32 mode"),
11390 bfd_get_reloc_code_name (code
));
11396 if (!fixp
->fx_pcrel
)
11397 rel
->addend
= fixp
->fx_offset
;
11401 case BFD_RELOC_X86_64_PLT32
:
11402 case BFD_RELOC_X86_64_GOT32
:
11403 case BFD_RELOC_X86_64_GOTPCREL
:
11404 case BFD_RELOC_X86_64_GOTPCRELX
:
11405 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11406 case BFD_RELOC_X86_64_TLSGD
:
11407 case BFD_RELOC_X86_64_TLSLD
:
11408 case BFD_RELOC_X86_64_GOTTPOFF
:
11409 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11410 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11411 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
11414 rel
->addend
= (section
->vma
11416 + fixp
->fx_addnumber
11417 + md_pcrel_from (fixp
));
11422 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11423 if (rel
->howto
== NULL
)
11425 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11426 _("cannot represent relocation type %s"),
11427 bfd_get_reloc_code_name (code
));
11428 /* Set howto to a garbage value so that we can keep going. */
11429 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
11430 gas_assert (rel
->howto
!= NULL
);
11436 #include "tc-i386-intel.c"
11439 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
11441 int saved_naked_reg
;
11442 char saved_register_dot
;
11444 saved_naked_reg
= allow_naked_reg
;
11445 allow_naked_reg
= 1;
11446 saved_register_dot
= register_chars
['.'];
11447 register_chars
['.'] = '.';
11448 allow_pseudo_reg
= 1;
11449 expression_and_evaluate (exp
);
11450 allow_pseudo_reg
= 0;
11451 register_chars
['.'] = saved_register_dot
;
11452 allow_naked_reg
= saved_naked_reg
;
11454 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
11456 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
11458 exp
->X_op
= O_constant
;
11459 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
11460 .dw2_regnum
[flag_code
>> 1];
11463 exp
->X_op
= O_illegal
;
11468 tc_x86_frame_initial_instructions (void)
11470 static unsigned int sp_regno
[2];
11472 if (!sp_regno
[flag_code
>> 1])
11474 char *saved_input
= input_line_pointer
;
11475 char sp
[][4] = {"esp", "rsp"};
11478 input_line_pointer
= sp
[flag_code
>> 1];
11479 tc_x86_parse_to_dw2regnum (&exp
);
11480 gas_assert (exp
.X_op
== O_constant
);
11481 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
11482 input_line_pointer
= saved_input
;
11485 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
11486 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
11490 x86_dwarf2_addr_size (void)
11492 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11493 if (x86_elf_abi
== X86_64_X32_ABI
)
11496 return bfd_arch_bits_per_address (stdoutput
) / 8;
11500 i386_elf_section_type (const char *str
, size_t len
)
11502 if (flag_code
== CODE_64BIT
11503 && len
== sizeof ("unwind") - 1
11504 && strncmp (str
, "unwind", 6) == 0)
11505 return SHT_X86_64_UNWIND
;
11512 i386_solaris_fix_up_eh_frame (segT sec
)
11514 if (flag_code
== CODE_64BIT
)
11515 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
11521 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
11525 exp
.X_op
= O_secrel
;
11526 exp
.X_add_symbol
= symbol
;
11527 exp
.X_add_number
= 0;
11528 emit_expr (&exp
, size
);
11532 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11533 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11536 x86_64_section_letter (int letter
, const char **ptr_msg
)
11538 if (flag_code
== CODE_64BIT
)
11541 return SHF_X86_64_LARGE
;
11543 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11546 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
11551 x86_64_section_word (char *str
, size_t len
)
11553 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
11554 return SHF_X86_64_LARGE
;
11560 handle_large_common (int small ATTRIBUTE_UNUSED
)
11562 if (flag_code
!= CODE_64BIT
)
11564 s_comm_internal (0, elf_common_parse
);
11565 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11569 static segT lbss_section
;
11570 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
11571 asection
*saved_bss_section
= bss_section
;
11573 if (lbss_section
== NULL
)
11575 flagword applicable
;
11576 segT seg
= now_seg
;
11577 subsegT subseg
= now_subseg
;
11579 /* The .lbss section is for local .largecomm symbols. */
11580 lbss_section
= subseg_new (".lbss", 0);
11581 applicable
= bfd_applicable_section_flags (stdoutput
);
11582 bfd_set_section_flags (stdoutput
, lbss_section
,
11583 applicable
& SEC_ALLOC
);
11584 seg_info (lbss_section
)->bss
= 1;
11586 subseg_set (seg
, subseg
);
11589 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
11590 bss_section
= lbss_section
;
11592 s_comm_internal (0, elf_common_parse
);
11594 elf_com_section_ptr
= saved_com_section_ptr
;
11595 bss_section
= saved_bss_section
;
11598 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */