1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const template *start
;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem
; /* codes register or memory operand */
109 unsigned int reg
; /* codes register operand (or extended opcode) */
110 unsigned int mode
; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte
;
117 /* The SSE5 instructions have a two bit instruction modifier (OC) that
118 is stored in two separate bytes in the instruction. Pick apart OC
119 into the 2 separate bits for instruction. */
120 #define DREX_OC0(x) (((x) & 1) != 0)
121 #define DREX_OC1(x) (((x) & 2) != 0)
123 #define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
124 #define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
127 #define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
128 #define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
129 #define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
130 #define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
132 #define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
133 #define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
135 /* Information needed to create the DREX byte in SSE5 instructions. */
138 unsigned int reg
; /* register */
139 unsigned int rex
; /* REX flags */
140 unsigned int modrm_reg
; /* which arg goes in the modrm.reg field */
141 unsigned int modrm_regmem
; /* which arg goes in the modrm.regmem field */
144 /* 386 opcode byte to code indirect addressing. */
159 PROCESSOR_PENTIUMPRO
,
172 /* x86 arch names, types and features */
175 const char *name
; /* arch name */
176 enum processor_type type
; /* arch type */
177 i386_cpu_flags flags
; /* cpu feature flags */
181 static void set_code_flag (int);
182 static void set_16bit_gcc_code_flag (int);
183 static void set_intel_syntax (int);
184 static void set_intel_mnemonic (int);
185 static void set_allow_index_reg (int);
186 static void set_cpu_arch (int);
188 static void pe_directive_secrel (int);
190 static void signed_cons (int);
191 static char *output_invalid (int c
);
192 static int i386_att_operand (char *);
193 static int i386_intel_operand (char *, int);
194 static const reg_entry
*parse_register (char *, char **);
195 static char *parse_insn (char *, char *);
196 static char *parse_operands (char *, const char *);
197 static void swap_operands (void);
198 static void swap_2_operands (int, int);
199 static void optimize_imm (void);
200 static void optimize_disp (void);
201 static int match_template (void);
202 static int check_string (void);
203 static int process_suffix (void);
204 static int check_byte_reg (void);
205 static int check_long_reg (void);
206 static int check_qword_reg (void);
207 static int check_word_reg (void);
208 static int finalize_imm (void);
209 static void process_drex (void);
210 static int process_operands (void);
211 static const seg_entry
*build_modrm_byte (void);
212 static void output_insn (void);
213 static void output_imm (fragS
*, offsetT
);
214 static void output_disp (fragS
*, offsetT
);
216 static void s_bss (int);
218 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
219 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
222 static const char *default_arch
= DEFAULT_ARCH
;
227 /* VEX prefix is either 2 byte or 3 byte. */
228 unsigned char bytes
[3];
230 /* Destination or source register specifier. */
231 const reg_entry
*register_specifier
;
234 /* 'md_assemble ()' gathers together information and puts it into a
241 const reg_entry
*regs
;
246 /* TM holds the template for the insn were currently assembling. */
249 /* SUFFIX holds the instruction size suffix for byte, word, dword
250 or qword, if given. */
253 /* OPERANDS gives the number of given operands. */
254 unsigned int operands
;
256 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
257 of given register, displacement, memory operands and immediate
259 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
261 /* TYPES [i] is the type (see above #defines) which tells us how to
262 use OP[i] for the corresponding operand. */
263 i386_operand_type types
[MAX_OPERANDS
];
265 /* Displacement expression, immediate expression, or register for each
267 union i386_op op
[MAX_OPERANDS
];
269 /* Flags for operands. */
270 unsigned int flags
[MAX_OPERANDS
];
271 #define Operand_PCrel 1
273 /* Relocation type for operand */
274 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
276 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
277 the base index byte below. */
278 const reg_entry
*base_reg
;
279 const reg_entry
*index_reg
;
280 unsigned int log2_scale_factor
;
282 /* SEG gives the seg_entries of this insn. They are zero unless
283 explicit segment overrides are given. */
284 const seg_entry
*seg
[2];
286 /* PREFIX holds all the given prefix opcodes (usually null).
287 PREFIXES is the number of prefix opcodes. */
288 unsigned int prefixes
;
289 unsigned char prefix
[MAX_PREFIXES
];
291 /* RM and SIB are the modrm byte and the sib byte where the
292 addressing modes of this insn are encoded. DREX is the byte
293 added by the SSE5 instructions. */
302 typedef struct _i386_insn i386_insn
;
304 /* List of chars besides those in app.c:symbol_chars that can start an
305 operand. Used to prevent the scrubber eating vital white-space. */
306 const char extra_symbol_chars
[] = "*%-(["
315 #if (defined (TE_I386AIX) \
316 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
317 && !defined (TE_GNU) \
318 && !defined (TE_LINUX) \
319 && !defined (TE_NETWARE) \
320 && !defined (TE_FreeBSD) \
321 && !defined (TE_NetBSD)))
322 /* This array holds the chars that always start a comment. If the
323 pre-processor is disabled, these aren't very useful. The option
324 --divide will remove '/' from this list. */
325 const char *i386_comment_chars
= "#/";
326 #define SVR4_COMMENT_CHARS 1
327 #define PREFIX_SEPARATOR '\\'
330 const char *i386_comment_chars
= "#";
331 #define PREFIX_SEPARATOR '/'
334 /* This array holds the chars that only start a comment at the beginning of
335 a line. If the line seems to have the form '# 123 filename'
336 .line and .file directives will appear in the pre-processed output.
337 Note that input_file.c hand checks for '#' at the beginning of the
338 first line of the input file. This is because the compiler outputs
339 #NO_APP at the beginning of its output.
340 Also note that comments started like this one will always work if
341 '/' isn't otherwise defined. */
342 const char line_comment_chars
[] = "#/";
344 const char line_separator_chars
[] = ";";
346 /* Chars that can be used to separate mant from exp in floating point
348 const char EXP_CHARS
[] = "eE";
350 /* Chars that mean this number is a floating point constant
353 const char FLT_CHARS
[] = "fFdDxX";
355 /* Tables for lexical analysis. */
356 static char mnemonic_chars
[256];
357 static char register_chars
[256];
358 static char operand_chars
[256];
359 static char identifier_chars
[256];
360 static char digit_chars
[256];
362 /* Lexical macros. */
363 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
364 #define is_operand_char(x) (operand_chars[(unsigned char) x])
365 #define is_register_char(x) (register_chars[(unsigned char) x])
366 #define is_space_char(x) ((x) == ' ')
367 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
368 #define is_digit_char(x) (digit_chars[(unsigned char) x])
370 /* All non-digit non-letter characters that may occur in an operand. */
371 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
373 /* md_assemble() always leaves the strings it's passed unaltered. To
374 effect this we maintain a stack of saved characters that we've smashed
375 with '\0's (indicating end of strings for various sub-fields of the
376 assembler instruction). */
377 static char save_stack
[32];
378 static char *save_stack_p
;
379 #define END_STRING_AND_SAVE(s) \
380 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
381 #define RESTORE_END_STRING(s) \
382 do { *(s) = *--save_stack_p; } while (0)
384 /* The instruction we're assembling. */
387 /* Possible templates for current insn. */
388 static const templates
*current_templates
;
390 /* Per instruction expressionS buffers: max displacements & immediates. */
391 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
392 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
394 /* Current operand we are working on. */
395 static int this_operand
;
397 /* We support four different modes. FLAG_CODE variable is used to distinguish
405 static enum flag_code flag_code
;
406 static unsigned int object_64bit
;
407 static int use_rela_relocations
= 0;
409 /* The names used to print error messages. */
410 static const char *flag_code_names
[] =
417 /* 1 for intel syntax,
419 static int intel_syntax
= 0;
421 /* 1 for intel mnemonic,
422 0 if att mnemonic. */
423 static int intel_mnemonic
= !SYSV386_COMPAT
;
425 /* 1 if support old (<= 2.8.1) versions of gcc. */
426 static int old_gcc
= OLDGCC_COMPAT
;
428 /* 1 if pseudo registers are permitted. */
429 static int allow_pseudo_reg
= 0;
431 /* 1 if register prefix % not required. */
432 static int allow_naked_reg
= 0;
434 /* 1 if pseudo index register, eiz/riz, is allowed . */
435 static int allow_index_reg
= 0;
445 /* Register prefix used for error message. */
446 static const char *register_prefix
= "%";
448 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
449 leave, push, and pop instructions so that gcc has the same stack
450 frame as in 32 bit mode. */
451 static char stackop_size
= '\0';
453 /* Non-zero to optimize code alignment. */
454 int optimize_align_code
= 1;
456 /* Non-zero to quieten some warnings. */
457 static int quiet_warnings
= 0;
460 static const char *cpu_arch_name
= NULL
;
461 static char *cpu_sub_arch_name
= NULL
;
463 /* CPU feature flags. */
464 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
466 /* If we have selected a cpu we are generating instructions for. */
467 static int cpu_arch_tune_set
= 0;
469 /* Cpu we are generating instructions for. */
470 static enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
472 /* CPU feature flags of cpu we are generating instructions for. */
473 static i386_cpu_flags cpu_arch_tune_flags
;
475 /* CPU instruction set architecture used. */
476 static enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
478 /* CPU feature flags of instruction set architecture used. */
479 static i386_cpu_flags cpu_arch_isa_flags
;
481 /* If set, conditional jumps are not automatically promoted to handle
482 larger than a byte offset. */
483 static unsigned int no_cond_jump_promotion
= 0;
485 /* Encode SSE instructions with VEX prefix. */
486 static unsigned int sse2avx
;
488 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
489 static symbolS
*GOT_symbol
;
491 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
492 unsigned int x86_dwarf2_return_column
;
494 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
495 int x86_cie_data_alignment
;
497 /* Interface to relax_segment.
498 There are 3 major relax states for 386 jump insns because the
499 different types of jumps add different sizes to frags when we're
500 figuring out what sort of jump to choose to reach a given label. */
503 #define UNCOND_JUMP 0
505 #define COND_JUMP86 2
510 #define SMALL16 (SMALL | CODE16)
512 #define BIG16 (BIG | CODE16)
516 #define INLINE __inline__
522 #define ENCODE_RELAX_STATE(type, size) \
523 ((relax_substateT) (((type) << 2) | (size)))
524 #define TYPE_FROM_RELAX_STATE(s) \
526 #define DISP_SIZE_FROM_RELAX_STATE(s) \
527 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
529 /* This table is used by relax_frag to promote short jumps to long
530 ones where necessary. SMALL (short) jumps may be promoted to BIG
531 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
532 don't allow a short jump in a 32 bit code segment to be promoted to
533 a 16 bit offset jump because it's slower (requires data size
534 prefix), and doesn't work, unless the destination is in the bottom
535 64k of the code segment (The top 16 bits of eip are zeroed). */
537 const relax_typeS md_relax_table
[] =
540 1) most positive reach of this state,
541 2) most negative reach of this state,
542 3) how many bytes this mode will have in the variable part of the frag
543 4) which index into the table to try if we can't fit into this one. */
545 /* UNCOND_JUMP states. */
546 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
547 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
548 /* dword jmp adds 4 bytes to frag:
549 0 extra opcode bytes, 4 displacement bytes. */
551 /* word jmp adds 2 byte2 to frag:
552 0 extra opcode bytes, 2 displacement bytes. */
555 /* COND_JUMP states. */
556 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
557 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
558 /* dword conditionals adds 5 bytes to frag:
559 1 extra opcode byte, 4 displacement bytes. */
561 /* word conditionals add 3 bytes to frag:
562 1 extra opcode byte, 2 displacement bytes. */
565 /* COND_JUMP86 states. */
566 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
567 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
568 /* dword conditionals adds 5 bytes to frag:
569 1 extra opcode byte, 4 displacement bytes. */
571 /* word conditionals add 4 bytes to frag:
572 1 displacement byte and a 3 byte long branch insn. */
576 static const arch_entry cpu_arch
[] =
578 { "generic32", PROCESSOR_GENERIC32
,
579 CPU_GENERIC32_FLAGS
},
580 { "generic64", PROCESSOR_GENERIC64
,
581 CPU_GENERIC64_FLAGS
},
582 { "i8086", PROCESSOR_UNKNOWN
,
584 { "i186", PROCESSOR_UNKNOWN
,
586 { "i286", PROCESSOR_UNKNOWN
,
588 { "i386", PROCESSOR_I386
,
590 { "i486", PROCESSOR_I486
,
592 { "i586", PROCESSOR_PENTIUM
,
594 { "i686", PROCESSOR_PENTIUMPRO
,
596 { "pentium", PROCESSOR_PENTIUM
,
598 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
600 { "pentiumii", PROCESSOR_PENTIUMPRO
,
602 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
604 { "pentium4", PROCESSOR_PENTIUM4
,
606 { "prescott", PROCESSOR_NOCONA
,
608 { "nocona", PROCESSOR_NOCONA
,
610 { "yonah", PROCESSOR_CORE
,
612 { "core", PROCESSOR_CORE
,
614 { "merom", PROCESSOR_CORE2
,
616 { "core2", PROCESSOR_CORE2
,
618 { "k6", PROCESSOR_K6
,
620 { "k6_2", PROCESSOR_K6
,
622 { "athlon", PROCESSOR_ATHLON
,
624 { "sledgehammer", PROCESSOR_K8
,
626 { "opteron", PROCESSOR_K8
,
628 { "k8", PROCESSOR_K8
,
630 { "amdfam10", PROCESSOR_AMDFAM10
,
631 CPU_AMDFAM10_FLAGS
},
632 { ".mmx", PROCESSOR_UNKNOWN
,
634 { ".sse", PROCESSOR_UNKNOWN
,
636 { ".sse2", PROCESSOR_UNKNOWN
,
638 { ".sse3", PROCESSOR_UNKNOWN
,
640 { ".ssse3", PROCESSOR_UNKNOWN
,
642 { ".sse4.1", PROCESSOR_UNKNOWN
,
644 { ".sse4.2", PROCESSOR_UNKNOWN
,
646 { ".sse4", PROCESSOR_UNKNOWN
,
648 { ".avx", PROCESSOR_UNKNOWN
,
650 { ".vmx", PROCESSOR_UNKNOWN
,
652 { ".smx", PROCESSOR_UNKNOWN
,
654 { ".xsave", PROCESSOR_UNKNOWN
,
656 { ".aes", PROCESSOR_UNKNOWN
,
658 { ".pclmul", PROCESSOR_UNKNOWN
,
660 { ".clmul", PROCESSOR_UNKNOWN
,
662 { ".fma", PROCESSOR_UNKNOWN
,
664 { ".movbe", PROCESSOR_UNKNOWN
,
666 { ".ept", PROCESSOR_UNKNOWN
,
668 { ".3dnow", PROCESSOR_UNKNOWN
,
670 { ".3dnowa", PROCESSOR_UNKNOWN
,
672 { ".padlock", PROCESSOR_UNKNOWN
,
674 { ".pacifica", PROCESSOR_UNKNOWN
,
676 { ".svme", PROCESSOR_UNKNOWN
,
678 { ".sse4a", PROCESSOR_UNKNOWN
,
680 { ".abm", PROCESSOR_UNKNOWN
,
682 { ".sse5", PROCESSOR_UNKNOWN
,
686 const pseudo_typeS md_pseudo_table
[] =
688 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
689 {"align", s_align_bytes
, 0},
691 {"align", s_align_ptwo
, 0},
693 {"arch", set_cpu_arch
, 0},
697 {"ffloat", float_cons
, 'f'},
698 {"dfloat", float_cons
, 'd'},
699 {"tfloat", float_cons
, 'x'},
701 {"slong", signed_cons
, 4},
702 {"noopt", s_ignore
, 0},
703 {"optim", s_ignore
, 0},
704 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
705 {"code16", set_code_flag
, CODE_16BIT
},
706 {"code32", set_code_flag
, CODE_32BIT
},
707 {"code64", set_code_flag
, CODE_64BIT
},
708 {"intel_syntax", set_intel_syntax
, 1},
709 {"att_syntax", set_intel_syntax
, 0},
710 {"intel_mnemonic", set_intel_mnemonic
, 1},
711 {"att_mnemonic", set_intel_mnemonic
, 0},
712 {"allow_index_reg", set_allow_index_reg
, 1},
713 {"disallow_index_reg", set_allow_index_reg
, 0},
714 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
715 {"largecomm", handle_large_common
, 0},
717 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
718 {"loc", dwarf2_directive_loc
, 0},
719 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
722 {"secrel32", pe_directive_secrel
, 0},
727 /* For interface with expression (). */
728 extern char *input_line_pointer
;
730 /* Hash table for instruction mnemonic lookup. */
731 static struct hash_control
*op_hash
;
733 /* Hash table for register lookup. */
734 static struct hash_control
*reg_hash
;
737 i386_align_code (fragS
*fragP
, int count
)
739 /* Various efficient no-op patterns for aligning code labels.
740 Note: Don't try to assemble the instructions in the comments.
741 0L and 0w are not legal. */
742 static const char f32_1
[] =
744 static const char f32_2
[] =
745 {0x66,0x90}; /* xchg %ax,%ax */
746 static const char f32_3
[] =
747 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
748 static const char f32_4
[] =
749 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
750 static const char f32_5
[] =
752 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
753 static const char f32_6
[] =
754 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
755 static const char f32_7
[] =
756 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
757 static const char f32_8
[] =
759 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
760 static const char f32_9
[] =
761 {0x89,0xf6, /* movl %esi,%esi */
762 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
763 static const char f32_10
[] =
764 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
765 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
766 static const char f32_11
[] =
767 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
768 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
769 static const char f32_12
[] =
770 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
771 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
772 static const char f32_13
[] =
773 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
774 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
775 static const char f32_14
[] =
776 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
777 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
778 static const char f16_3
[] =
779 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
780 static const char f16_4
[] =
781 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
782 static const char f16_5
[] =
784 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
785 static const char f16_6
[] =
786 {0x89,0xf6, /* mov %si,%si */
787 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
788 static const char f16_7
[] =
789 {0x8d,0x74,0x00, /* lea 0(%si),%si */
790 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
791 static const char f16_8
[] =
792 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
793 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
794 static const char jump_31
[] =
795 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
796 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
797 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
798 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
799 static const char *const f32_patt
[] = {
800 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
801 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
803 static const char *const f16_patt
[] = {
804 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
807 static const char alt_3
[] =
809 /* nopl 0(%[re]ax) */
810 static const char alt_4
[] =
811 {0x0f,0x1f,0x40,0x00};
812 /* nopl 0(%[re]ax,%[re]ax,1) */
813 static const char alt_5
[] =
814 {0x0f,0x1f,0x44,0x00,0x00};
815 /* nopw 0(%[re]ax,%[re]ax,1) */
816 static const char alt_6
[] =
817 {0x66,0x0f,0x1f,0x44,0x00,0x00};
818 /* nopl 0L(%[re]ax) */
819 static const char alt_7
[] =
820 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
821 /* nopl 0L(%[re]ax,%[re]ax,1) */
822 static const char alt_8
[] =
823 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
824 /* nopw 0L(%[re]ax,%[re]ax,1) */
825 static const char alt_9
[] =
826 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
827 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
828 static const char alt_10
[] =
829 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
831 nopw %cs:0L(%[re]ax,%[re]ax,1) */
832 static const char alt_long_11
[] =
834 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
837 nopw %cs:0L(%[re]ax,%[re]ax,1) */
838 static const char alt_long_12
[] =
841 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
845 nopw %cs:0L(%[re]ax,%[re]ax,1) */
846 static const char alt_long_13
[] =
850 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
855 nopw %cs:0L(%[re]ax,%[re]ax,1) */
856 static const char alt_long_14
[] =
861 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
867 nopw %cs:0L(%[re]ax,%[re]ax,1) */
868 static const char alt_long_15
[] =
874 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
875 /* nopl 0(%[re]ax,%[re]ax,1)
876 nopw 0(%[re]ax,%[re]ax,1) */
877 static const char alt_short_11
[] =
878 {0x0f,0x1f,0x44,0x00,0x00,
879 0x66,0x0f,0x1f,0x44,0x00,0x00};
880 /* nopw 0(%[re]ax,%[re]ax,1)
881 nopw 0(%[re]ax,%[re]ax,1) */
882 static const char alt_short_12
[] =
883 {0x66,0x0f,0x1f,0x44,0x00,0x00,
884 0x66,0x0f,0x1f,0x44,0x00,0x00};
885 /* nopw 0(%[re]ax,%[re]ax,1)
887 static const char alt_short_13
[] =
888 {0x66,0x0f,0x1f,0x44,0x00,0x00,
889 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
892 static const char alt_short_14
[] =
893 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
894 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
896 nopl 0L(%[re]ax,%[re]ax,1) */
897 static const char alt_short_15
[] =
898 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
899 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
900 static const char *const alt_short_patt
[] = {
901 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
902 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
903 alt_short_14
, alt_short_15
905 static const char *const alt_long_patt
[] = {
906 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
907 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
908 alt_long_14
, alt_long_15
911 /* Only align for at least a positive non-zero boundary. */
912 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
915 /* We need to decide which NOP sequence to use for 32bit and
916 64bit. When -mtune= is used:
918 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
919 PROCESSOR_GENERIC32, f32_patt will be used.
920 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
921 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
922 alt_long_patt will be used.
923 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
924 PROCESSOR_AMDFAM10, alt_short_patt will be used.
926 When -mtune= isn't used, alt_long_patt will be used if
927 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
930 When -march= or .arch is used, we can't use anything beyond
931 cpu_arch_isa_flags. */
933 if (flag_code
== CODE_16BIT
)
937 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
939 /* Adjust jump offset. */
940 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
943 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
944 f16_patt
[count
- 1], count
);
948 const char *const *patt
= NULL
;
950 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
952 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
953 switch (cpu_arch_tune
)
955 case PROCESSOR_UNKNOWN
:
956 /* We use cpu_arch_isa_flags to check if we SHOULD
957 optimize for Cpu686. */
958 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
959 patt
= alt_long_patt
;
963 case PROCESSOR_PENTIUMPRO
:
964 case PROCESSOR_PENTIUM4
:
965 case PROCESSOR_NOCONA
:
967 case PROCESSOR_CORE2
:
968 case PROCESSOR_GENERIC64
:
969 patt
= alt_long_patt
;
972 case PROCESSOR_ATHLON
:
974 case PROCESSOR_AMDFAM10
:
975 patt
= alt_short_patt
;
979 case PROCESSOR_PENTIUM
:
980 case PROCESSOR_GENERIC32
:
987 switch (cpu_arch_tune
)
989 case PROCESSOR_UNKNOWN
:
990 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
991 PROCESSOR_UNKNOWN. */
997 case PROCESSOR_PENTIUM
:
999 case PROCESSOR_ATHLON
:
1001 case PROCESSOR_AMDFAM10
:
1002 case PROCESSOR_GENERIC32
:
1003 /* We use cpu_arch_isa_flags to check if we CAN optimize
1005 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
1006 patt
= alt_short_patt
;
1010 case PROCESSOR_PENTIUMPRO
:
1011 case PROCESSOR_PENTIUM4
:
1012 case PROCESSOR_NOCONA
:
1013 case PROCESSOR_CORE
:
1014 case PROCESSOR_CORE2
:
1015 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
1016 patt
= alt_long_patt
;
1020 case PROCESSOR_GENERIC64
:
1021 patt
= alt_long_patt
;
1026 if (patt
== f32_patt
)
1028 /* If the padding is less than 15 bytes, we use the normal
1029 ones. Otherwise, we use a jump instruction and adjust
1032 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1033 patt
[count
- 1], count
);
1036 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1038 /* Adjust jump offset. */
1039 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1044 /* Maximum length of an instruction is 15 byte. If the
1045 padding is greater than 15 bytes and we don't use jump,
1046 we have to break it into smaller pieces. */
1047 int padding
= count
;
1048 while (padding
> 15)
1051 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1056 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1057 patt
[padding
- 1], padding
);
1060 fragP
->fr_var
= count
;
1064 operand_type_all_zero (const union i386_operand_type
*x
)
1066 switch (ARRAY_SIZE(x
->array
))
1075 return !x
->array
[0];
1082 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1084 switch (ARRAY_SIZE(x
->array
))
1099 operand_type_equal (const union i386_operand_type
*x
,
1100 const union i386_operand_type
*y
)
1102 switch (ARRAY_SIZE(x
->array
))
1105 if (x
->array
[2] != y
->array
[2])
1108 if (x
->array
[1] != y
->array
[1])
1111 return x
->array
[0] == y
->array
[0];
1119 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1121 switch (ARRAY_SIZE(x
->array
))
1130 return !x
->array
[0];
1137 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1139 switch (ARRAY_SIZE(x
->array
))
1154 cpu_flags_equal (const union i386_cpu_flags
*x
,
1155 const union i386_cpu_flags
*y
)
1157 switch (ARRAY_SIZE(x
->array
))
1160 if (x
->array
[2] != y
->array
[2])
1163 if (x
->array
[1] != y
->array
[1])
1166 return x
->array
[0] == y
->array
[0];
1174 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1176 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1177 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1180 static INLINE i386_cpu_flags
1181 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1183 switch (ARRAY_SIZE (x
.array
))
1186 x
.array
[2] &= y
.array
[2];
1188 x
.array
[1] &= y
.array
[1];
1190 x
.array
[0] &= y
.array
[0];
1198 static INLINE i386_cpu_flags
1199 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1201 switch (ARRAY_SIZE (x
.array
))
1204 x
.array
[2] |= y
.array
[2];
1206 x
.array
[1] |= y
.array
[1];
1208 x
.array
[0] |= y
.array
[0];
1216 #define CPU_FLAGS_ARCH_MATCH 0x1
1217 #define CPU_FLAGS_64BIT_MATCH 0x2
1219 #define CPU_FLAGS_32BIT_MATCH CPU_FLAGS_ARCH_MATCH
1220 #define CPU_FLAGS_PERFECT_MATCH \
1221 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1223 /* Return CPU flags match bits. */
1226 cpu_flags_match (const template *t
)
1228 i386_cpu_flags x
= t
->cpu_flags
;
1229 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1231 x
.bitfield
.cpu64
= 0;
1232 x
.bitfield
.cpuno64
= 0;
1234 if (cpu_flags_all_zero (&x
))
1236 /* This instruction is available on all archs. */
1237 match
|= CPU_FLAGS_32BIT_MATCH
;
1241 /* This instruction is available only on some archs. */
1242 i386_cpu_flags cpu
= cpu_arch_flags
;
1244 cpu
.bitfield
.cpu64
= 0;
1245 cpu
.bitfield
.cpuno64
= 0;
1246 cpu
= cpu_flags_and (x
, cpu
);
1247 if (!cpu_flags_all_zero (&cpu
))
1250 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1251 match
|= CPU_FLAGS_32BIT_MATCH
;
1257 static INLINE i386_operand_type
1258 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1260 switch (ARRAY_SIZE (x
.array
))
1263 x
.array
[2] &= y
.array
[2];
1265 x
.array
[1] &= y
.array
[1];
1267 x
.array
[0] &= y
.array
[0];
1275 static INLINE i386_operand_type
1276 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1278 switch (ARRAY_SIZE (x
.array
))
1281 x
.array
[2] |= y
.array
[2];
1283 x
.array
[1] |= y
.array
[1];
1285 x
.array
[0] |= y
.array
[0];
1293 static INLINE i386_operand_type
1294 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1296 switch (ARRAY_SIZE (x
.array
))
1299 x
.array
[2] ^= y
.array
[2];
1301 x
.array
[1] ^= y
.array
[1];
1303 x
.array
[0] ^= y
.array
[0];
1311 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1312 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1313 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1314 static const i386_operand_type inoutportreg
1315 = OPERAND_TYPE_INOUTPORTREG
;
1316 static const i386_operand_type reg16_inoutportreg
1317 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1318 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1319 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1320 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1321 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1322 static const i386_operand_type anydisp
1323 = OPERAND_TYPE_ANYDISP
;
1324 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1325 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1326 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1327 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1328 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1329 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1330 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1331 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1332 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1333 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1334 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1335 static const i386_operand_type vex_imm4
= OPERAND_TYPE_VEX_IMM4
;
1346 operand_type_check (i386_operand_type t
, enum operand_type c
)
1351 return (t
.bitfield
.reg8
1354 || t
.bitfield
.reg64
);
1357 return (t
.bitfield
.imm8
1361 || t
.bitfield
.imm32s
1362 || t
.bitfield
.imm64
);
1365 return (t
.bitfield
.disp8
1366 || t
.bitfield
.disp16
1367 || t
.bitfield
.disp32
1368 || t
.bitfield
.disp32s
1369 || t
.bitfield
.disp64
);
1372 return (t
.bitfield
.disp8
1373 || t
.bitfield
.disp16
1374 || t
.bitfield
.disp32
1375 || t
.bitfield
.disp32s
1376 || t
.bitfield
.disp64
1377 || t
.bitfield
.baseindex
);
1384 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1385 operand J for instruction template T. */
1388 match_reg_size (const template *t
, unsigned int j
)
1390 return !((i
.types
[j
].bitfield
.byte
1391 && !t
->operand_types
[j
].bitfield
.byte
)
1392 || (i
.types
[j
].bitfield
.word
1393 && !t
->operand_types
[j
].bitfield
.word
)
1394 || (i
.types
[j
].bitfield
.dword
1395 && !t
->operand_types
[j
].bitfield
.dword
)
1396 || (i
.types
[j
].bitfield
.qword
1397 && !t
->operand_types
[j
].bitfield
.qword
));
1400 /* Return 1 if there is no conflict in any size on operand J for
1401 instruction template T. */
1404 match_mem_size (const template *t
, unsigned int j
)
1406 return (match_reg_size (t
, j
)
1407 && !((i
.types
[j
].bitfield
.unspecified
1408 && !t
->operand_types
[j
].bitfield
.unspecified
)
1409 || (i
.types
[j
].bitfield
.fword
1410 && !t
->operand_types
[j
].bitfield
.fword
)
1411 || (i
.types
[j
].bitfield
.tbyte
1412 && !t
->operand_types
[j
].bitfield
.tbyte
)
1413 || (i
.types
[j
].bitfield
.xmmword
1414 && !t
->operand_types
[j
].bitfield
.xmmword
)
1415 || (i
.types
[j
].bitfield
.ymmword
1416 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1419 /* Return 1 if there is no size conflict on any operands for
1420 instruction template T. */
1423 operand_size_match (const template *t
)
1428 /* Don't check jump instructions. */
1429 if (t
->opcode_modifier
.jump
1430 || t
->opcode_modifier
.jumpbyte
1431 || t
->opcode_modifier
.jumpdword
1432 || t
->opcode_modifier
.jumpintersegment
)
1435 /* Check memory and accumulator operand size. */
1436 for (j
= 0; j
< i
.operands
; j
++)
1438 if (t
->operand_types
[j
].bitfield
.anysize
)
1441 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1447 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1455 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1458 /* Check reverse. */
1459 assert (i
.operands
== 2);
1462 for (j
= 0; j
< 2; j
++)
1464 if (t
->operand_types
[j
].bitfield
.acc
1465 && !match_reg_size (t
, j
? 0 : 1))
1471 if (i
.types
[j
].bitfield
.mem
1472 && !match_mem_size (t
, j
? 0 : 1))
1483 operand_type_match (i386_operand_type overlap
,
1484 i386_operand_type given
)
1486 i386_operand_type temp
= overlap
;
1488 temp
.bitfield
.jumpabsolute
= 0;
1489 temp
.bitfield
.unspecified
= 0;
1490 temp
.bitfield
.byte
= 0;
1491 temp
.bitfield
.word
= 0;
1492 temp
.bitfield
.dword
= 0;
1493 temp
.bitfield
.fword
= 0;
1494 temp
.bitfield
.qword
= 0;
1495 temp
.bitfield
.tbyte
= 0;
1496 temp
.bitfield
.xmmword
= 0;
1497 temp
.bitfield
.ymmword
= 0;
1498 if (operand_type_all_zero (&temp
))
1501 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1502 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1505 /* If given types g0 and g1 are registers they must be of the same type
1506 unless the expected operand type register overlap is null.
1507 Note that Acc in a template matches every size of reg. */
1510 operand_type_register_match (i386_operand_type m0
,
1511 i386_operand_type g0
,
1512 i386_operand_type t0
,
1513 i386_operand_type m1
,
1514 i386_operand_type g1
,
1515 i386_operand_type t1
)
1517 if (!operand_type_check (g0
, reg
))
1520 if (!operand_type_check (g1
, reg
))
1523 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1524 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1525 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1526 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1529 if (m0
.bitfield
.acc
)
1531 t0
.bitfield
.reg8
= 1;
1532 t0
.bitfield
.reg16
= 1;
1533 t0
.bitfield
.reg32
= 1;
1534 t0
.bitfield
.reg64
= 1;
1537 if (m1
.bitfield
.acc
)
1539 t1
.bitfield
.reg8
= 1;
1540 t1
.bitfield
.reg16
= 1;
1541 t1
.bitfield
.reg32
= 1;
1542 t1
.bitfield
.reg64
= 1;
1545 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1546 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1547 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1548 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1551 static INLINE
unsigned int
1552 mode_from_disp_size (i386_operand_type t
)
1554 if (t
.bitfield
.disp8
)
1556 else if (t
.bitfield
.disp16
1557 || t
.bitfield
.disp32
1558 || t
.bitfield
.disp32s
)
1565 fits_in_signed_byte (offsetT num
)
1567 return (num
>= -128) && (num
<= 127);
1571 fits_in_unsigned_byte (offsetT num
)
1573 return (num
& 0xff) == num
;
1577 fits_in_unsigned_word (offsetT num
)
1579 return (num
& 0xffff) == num
;
1583 fits_in_signed_word (offsetT num
)
1585 return (-32768 <= num
) && (num
<= 32767);
1589 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1594 return (!(((offsetT
) -1 << 31) & num
)
1595 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1597 } /* fits_in_signed_long() */
1600 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1605 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1607 } /* fits_in_unsigned_long() */
1610 fits_in_imm4 (offsetT num
)
1612 return (num
& 0xf) == num
;
1615 static i386_operand_type
1616 smallest_imm_type (offsetT num
)
1618 i386_operand_type t
;
1620 operand_type_set (&t
, 0);
1621 t
.bitfield
.imm64
= 1;
1623 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1625 /* This code is disabled on the 486 because all the Imm1 forms
1626 in the opcode table are slower on the i486. They're the
1627 versions with the implicitly specified single-position
1628 displacement, which has another syntax if you really want to
1630 t
.bitfield
.imm1
= 1;
1631 t
.bitfield
.imm8
= 1;
1632 t
.bitfield
.imm8s
= 1;
1633 t
.bitfield
.imm16
= 1;
1634 t
.bitfield
.imm32
= 1;
1635 t
.bitfield
.imm32s
= 1;
1637 else if (fits_in_signed_byte (num
))
1639 t
.bitfield
.imm8
= 1;
1640 t
.bitfield
.imm8s
= 1;
1641 t
.bitfield
.imm16
= 1;
1642 t
.bitfield
.imm32
= 1;
1643 t
.bitfield
.imm32s
= 1;
1645 else if (fits_in_unsigned_byte (num
))
1647 t
.bitfield
.imm8
= 1;
1648 t
.bitfield
.imm16
= 1;
1649 t
.bitfield
.imm32
= 1;
1650 t
.bitfield
.imm32s
= 1;
1652 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1654 t
.bitfield
.imm16
= 1;
1655 t
.bitfield
.imm32
= 1;
1656 t
.bitfield
.imm32s
= 1;
1658 else if (fits_in_signed_long (num
))
1660 t
.bitfield
.imm32
= 1;
1661 t
.bitfield
.imm32s
= 1;
1663 else if (fits_in_unsigned_long (num
))
1664 t
.bitfield
.imm32
= 1;
1670 offset_in_range (offsetT val
, int size
)
1676 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1677 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1678 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1680 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1685 /* If BFD64, sign extend val. */
1686 if (!use_rela_relocations
)
1687 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1688 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1690 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1692 char buf1
[40], buf2
[40];
1694 sprint_value (buf1
, val
);
1695 sprint_value (buf2
, val
& mask
);
1696 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1701 /* Returns 0 if attempting to add a prefix where one from the same
1702 class already exists, 1 if non rep/repne added, 2 if rep/repne
1705 add_prefix (unsigned int prefix
)
1710 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1711 && flag_code
== CODE_64BIT
)
1713 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1714 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1715 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1726 case CS_PREFIX_OPCODE
:
1727 case DS_PREFIX_OPCODE
:
1728 case ES_PREFIX_OPCODE
:
1729 case FS_PREFIX_OPCODE
:
1730 case GS_PREFIX_OPCODE
:
1731 case SS_PREFIX_OPCODE
:
1735 case REPNE_PREFIX_OPCODE
:
1736 case REPE_PREFIX_OPCODE
:
1739 case LOCK_PREFIX_OPCODE
:
1747 case ADDR_PREFIX_OPCODE
:
1751 case DATA_PREFIX_OPCODE
:
1755 if (i
.prefix
[q
] != 0)
1763 i
.prefix
[q
] |= prefix
;
1766 as_bad (_("same type of prefix used twice"));
1772 set_code_flag (int value
)
1775 if (flag_code
== CODE_64BIT
)
1777 cpu_arch_flags
.bitfield
.cpu64
= 1;
1778 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1782 cpu_arch_flags
.bitfield
.cpu64
= 0;
1783 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1785 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1787 as_bad (_("64bit mode not supported on this CPU."));
1789 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1791 as_bad (_("32bit mode not supported on this CPU."));
1793 stackop_size
= '\0';
1797 set_16bit_gcc_code_flag (int new_code_flag
)
1799 flag_code
= new_code_flag
;
1800 if (flag_code
!= CODE_16BIT
)
1802 cpu_arch_flags
.bitfield
.cpu64
= 0;
1803 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1804 stackop_size
= LONG_MNEM_SUFFIX
;
1808 set_intel_syntax (int syntax_flag
)
1810 /* Find out if register prefixing is specified. */
1811 int ask_naked_reg
= 0;
1814 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1816 char *string
= input_line_pointer
;
1817 int e
= get_symbol_end ();
1819 if (strcmp (string
, "prefix") == 0)
1821 else if (strcmp (string
, "noprefix") == 0)
1824 as_bad (_("bad argument to syntax directive."));
1825 *input_line_pointer
= e
;
1827 demand_empty_rest_of_line ();
1829 intel_syntax
= syntax_flag
;
1831 if (ask_naked_reg
== 0)
1832 allow_naked_reg
= (intel_syntax
1833 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1835 allow_naked_reg
= (ask_naked_reg
< 0);
1837 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1838 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1839 register_prefix
= allow_naked_reg
? "" : "%";
1843 set_intel_mnemonic (int mnemonic_flag
)
1845 intel_mnemonic
= mnemonic_flag
;
1849 set_allow_index_reg (int flag
)
1851 allow_index_reg
= flag
;
1855 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1859 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1861 char *string
= input_line_pointer
;
1862 int e
= get_symbol_end ();
1864 i386_cpu_flags flags
;
1866 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1868 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1872 cpu_arch_name
= cpu_arch
[i
].name
;
1873 cpu_sub_arch_name
= NULL
;
1874 cpu_arch_flags
= cpu_arch
[i
].flags
;
1875 if (flag_code
== CODE_64BIT
)
1877 cpu_arch_flags
.bitfield
.cpu64
= 1;
1878 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1882 cpu_arch_flags
.bitfield
.cpu64
= 0;
1883 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1885 cpu_arch_isa
= cpu_arch
[i
].type
;
1886 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1887 if (!cpu_arch_tune_set
)
1889 cpu_arch_tune
= cpu_arch_isa
;
1890 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1895 flags
= cpu_flags_or (cpu_arch_flags
,
1897 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
1899 if (cpu_sub_arch_name
)
1901 char *name
= cpu_sub_arch_name
;
1902 cpu_sub_arch_name
= concat (name
,
1904 (const char *) NULL
);
1908 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
1909 cpu_arch_flags
= flags
;
1911 *input_line_pointer
= e
;
1912 demand_empty_rest_of_line ();
1916 if (i
>= ARRAY_SIZE (cpu_arch
))
1917 as_bad (_("no such architecture: `%s'"), string
);
1919 *input_line_pointer
= e
;
1922 as_bad (_("missing cpu architecture"));
1924 no_cond_jump_promotion
= 0;
1925 if (*input_line_pointer
== ','
1926 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
1928 char *string
= ++input_line_pointer
;
1929 int e
= get_symbol_end ();
1931 if (strcmp (string
, "nojumps") == 0)
1932 no_cond_jump_promotion
= 1;
1933 else if (strcmp (string
, "jumps") == 0)
1936 as_bad (_("no such architecture modifier: `%s'"), string
);
1938 *input_line_pointer
= e
;
1941 demand_empty_rest_of_line ();
1947 if (!strcmp (default_arch
, "x86_64"))
1948 return bfd_mach_x86_64
;
1949 else if (!strcmp (default_arch
, "i386"))
1950 return bfd_mach_i386_i386
;
1952 as_fatal (_("Unknown architecture"));
1958 const char *hash_err
;
1960 /* Initialize op_hash hash table. */
1961 op_hash
= hash_new ();
1964 const template *optab
;
1965 templates
*core_optab
;
1967 /* Setup for loop. */
1969 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1970 core_optab
->start
= optab
;
1975 if (optab
->name
== NULL
1976 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
1978 /* different name --> ship out current template list;
1979 add to hash table; & begin anew. */
1980 core_optab
->end
= optab
;
1981 hash_err
= hash_insert (op_hash
,
1986 as_fatal (_("Internal Error: Can't hash %s: %s"),
1990 if (optab
->name
== NULL
)
1992 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1993 core_optab
->start
= optab
;
1998 /* Initialize reg_hash hash table. */
1999 reg_hash
= hash_new ();
2001 const reg_entry
*regtab
;
2002 unsigned int regtab_size
= i386_regtab_size
;
2004 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2006 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
2008 as_fatal (_("Internal Error: Can't hash %s: %s"),
2014 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2019 for (c
= 0; c
< 256; c
++)
2024 mnemonic_chars
[c
] = c
;
2025 register_chars
[c
] = c
;
2026 operand_chars
[c
] = c
;
2028 else if (ISLOWER (c
))
2030 mnemonic_chars
[c
] = c
;
2031 register_chars
[c
] = c
;
2032 operand_chars
[c
] = c
;
2034 else if (ISUPPER (c
))
2036 mnemonic_chars
[c
] = TOLOWER (c
);
2037 register_chars
[c
] = mnemonic_chars
[c
];
2038 operand_chars
[c
] = c
;
2041 if (ISALPHA (c
) || ISDIGIT (c
))
2042 identifier_chars
[c
] = c
;
2045 identifier_chars
[c
] = c
;
2046 operand_chars
[c
] = c
;
2051 identifier_chars
['@'] = '@';
2054 identifier_chars
['?'] = '?';
2055 operand_chars
['?'] = '?';
2057 digit_chars
['-'] = '-';
2058 mnemonic_chars
['_'] = '_';
2059 mnemonic_chars
['-'] = '-';
2060 mnemonic_chars
['.'] = '.';
2061 identifier_chars
['_'] = '_';
2062 identifier_chars
['.'] = '.';
2064 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2065 operand_chars
[(unsigned char) *p
] = *p
;
2068 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2071 record_alignment (text_section
, 2);
2072 record_alignment (data_section
, 2);
2073 record_alignment (bss_section
, 2);
2077 if (flag_code
== CODE_64BIT
)
2079 x86_dwarf2_return_column
= 16;
2080 x86_cie_data_alignment
= -8;
2084 x86_dwarf2_return_column
= 8;
2085 x86_cie_data_alignment
= -4;
2090 i386_print_statistics (FILE *file
)
2092 hash_print_statistics (file
, "i386 opcode", op_hash
);
2093 hash_print_statistics (file
, "i386 register", reg_hash
);
2098 /* Debugging routines for md_assemble. */
2099 static void pte (template *);
2100 static void pt (i386_operand_type
);
2101 static void pe (expressionS
*);
2102 static void ps (symbolS
*);
2105 pi (char *line
, i386_insn
*x
)
2109 fprintf (stdout
, "%s: template ", line
);
2111 fprintf (stdout
, " address: base %s index %s scale %x\n",
2112 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2113 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2114 x
->log2_scale_factor
);
2115 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2116 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2117 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2118 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2119 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2120 (x
->rex
& REX_W
) != 0,
2121 (x
->rex
& REX_R
) != 0,
2122 (x
->rex
& REX_X
) != 0,
2123 (x
->rex
& REX_B
) != 0);
2124 fprintf (stdout
, " drex: reg %d rex 0x%x\n",
2125 x
->drex
.reg
, x
->drex
.rex
);
2126 for (i
= 0; i
< x
->operands
; i
++)
2128 fprintf (stdout
, " #%d: ", i
+ 1);
2130 fprintf (stdout
, "\n");
2131 if (x
->types
[i
].bitfield
.reg8
2132 || x
->types
[i
].bitfield
.reg16
2133 || x
->types
[i
].bitfield
.reg32
2134 || x
->types
[i
].bitfield
.reg64
2135 || x
->types
[i
].bitfield
.regmmx
2136 || x
->types
[i
].bitfield
.regxmm
2137 || x
->types
[i
].bitfield
.regymm
2138 || x
->types
[i
].bitfield
.sreg2
2139 || x
->types
[i
].bitfield
.sreg3
2140 || x
->types
[i
].bitfield
.control
2141 || x
->types
[i
].bitfield
.debug
2142 || x
->types
[i
].bitfield
.test
)
2143 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2144 if (operand_type_check (x
->types
[i
], imm
))
2146 if (operand_type_check (x
->types
[i
], disp
))
2147 pe (x
->op
[i
].disps
);
2155 fprintf (stdout
, " %d operands ", t
->operands
);
2156 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2157 if (t
->extension_opcode
!= None
)
2158 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2159 if (t
->opcode_modifier
.d
)
2160 fprintf (stdout
, "D");
2161 if (t
->opcode_modifier
.w
)
2162 fprintf (stdout
, "W");
2163 fprintf (stdout
, "\n");
2164 for (i
= 0; i
< t
->operands
; i
++)
2166 fprintf (stdout
, " #%d type ", i
+ 1);
2167 pt (t
->operand_types
[i
]);
2168 fprintf (stdout
, "\n");
2175 fprintf (stdout
, " operation %d\n", e
->X_op
);
2176 fprintf (stdout
, " add_number %ld (%lx)\n",
2177 (long) e
->X_add_number
, (long) e
->X_add_number
);
2178 if (e
->X_add_symbol
)
2180 fprintf (stdout
, " add_symbol ");
2181 ps (e
->X_add_symbol
);
2182 fprintf (stdout
, "\n");
2186 fprintf (stdout
, " op_symbol ");
2187 ps (e
->X_op_symbol
);
2188 fprintf (stdout
, "\n");
2195 fprintf (stdout
, "%s type %s%s",
2197 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2198 segment_name (S_GET_SEGMENT (s
)));
2201 static struct type_name
2203 i386_operand_type mask
;
2206 const type_names
[] =
2208 { OPERAND_TYPE_REG8
, "r8" },
2209 { OPERAND_TYPE_REG16
, "r16" },
2210 { OPERAND_TYPE_REG32
, "r32" },
2211 { OPERAND_TYPE_REG64
, "r64" },
2212 { OPERAND_TYPE_IMM8
, "i8" },
2213 { OPERAND_TYPE_IMM8
, "i8s" },
2214 { OPERAND_TYPE_IMM16
, "i16" },
2215 { OPERAND_TYPE_IMM32
, "i32" },
2216 { OPERAND_TYPE_IMM32S
, "i32s" },
2217 { OPERAND_TYPE_IMM64
, "i64" },
2218 { OPERAND_TYPE_IMM1
, "i1" },
2219 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2220 { OPERAND_TYPE_DISP8
, "d8" },
2221 { OPERAND_TYPE_DISP16
, "d16" },
2222 { OPERAND_TYPE_DISP32
, "d32" },
2223 { OPERAND_TYPE_DISP32S
, "d32s" },
2224 { OPERAND_TYPE_DISP64
, "d64" },
2225 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2226 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2227 { OPERAND_TYPE_CONTROL
, "control reg" },
2228 { OPERAND_TYPE_TEST
, "test reg" },
2229 { OPERAND_TYPE_DEBUG
, "debug reg" },
2230 { OPERAND_TYPE_FLOATREG
, "FReg" },
2231 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2232 { OPERAND_TYPE_SREG2
, "SReg2" },
2233 { OPERAND_TYPE_SREG3
, "SReg3" },
2234 { OPERAND_TYPE_ACC
, "Acc" },
2235 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2236 { OPERAND_TYPE_REGMMX
, "rMMX" },
2237 { OPERAND_TYPE_REGXMM
, "rXMM" },
2238 { OPERAND_TYPE_ESSEG
, "es" },
2239 { OPERAND_TYPE_VEX_IMM4
, "VEX i4" },
2243 pt (i386_operand_type t
)
2246 i386_operand_type a
;
2248 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2250 a
= operand_type_and (t
, type_names
[j
].mask
);
2251 if (!UINTS_ALL_ZERO (a
))
2252 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2257 #endif /* DEBUG386 */
2259 static bfd_reloc_code_real_type
2260 reloc (unsigned int size
,
2263 bfd_reloc_code_real_type other
)
2265 if (other
!= NO_RELOC
)
2267 reloc_howto_type
*reloc
;
2272 case BFD_RELOC_X86_64_GOT32
:
2273 return BFD_RELOC_X86_64_GOT64
;
2275 case BFD_RELOC_X86_64_PLTOFF64
:
2276 return BFD_RELOC_X86_64_PLTOFF64
;
2278 case BFD_RELOC_X86_64_GOTPC32
:
2279 other
= BFD_RELOC_X86_64_GOTPC64
;
2281 case BFD_RELOC_X86_64_GOTPCREL
:
2282 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2284 case BFD_RELOC_X86_64_TPOFF32
:
2285 other
= BFD_RELOC_X86_64_TPOFF64
;
2287 case BFD_RELOC_X86_64_DTPOFF32
:
2288 other
= BFD_RELOC_X86_64_DTPOFF64
;
2294 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2295 if (size
== 4 && flag_code
!= CODE_64BIT
)
2298 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2300 as_bad (_("unknown relocation (%u)"), other
);
2301 else if (size
!= bfd_get_reloc_size (reloc
))
2302 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2303 bfd_get_reloc_size (reloc
),
2305 else if (pcrel
&& !reloc
->pc_relative
)
2306 as_bad (_("non-pc-relative relocation for pc-relative field"));
2307 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2309 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2311 as_bad (_("relocated field and relocation type differ in signedness"));
2320 as_bad (_("there are no unsigned pc-relative relocations"));
2323 case 1: return BFD_RELOC_8_PCREL
;
2324 case 2: return BFD_RELOC_16_PCREL
;
2325 case 4: return BFD_RELOC_32_PCREL
;
2326 case 8: return BFD_RELOC_64_PCREL
;
2328 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2335 case 4: return BFD_RELOC_X86_64_32S
;
2340 case 1: return BFD_RELOC_8
;
2341 case 2: return BFD_RELOC_16
;
2342 case 4: return BFD_RELOC_32
;
2343 case 8: return BFD_RELOC_64
;
2345 as_bad (_("cannot do %s %u byte relocation"),
2346 sign
> 0 ? "signed" : "unsigned", size
);
2350 return BFD_RELOC_NONE
;
2353 /* Here we decide which fixups can be adjusted to make them relative to
2354 the beginning of the section instead of the symbol. Basically we need
2355 to make sure that the dynamic relocations are done correctly, so in
2356 some cases we force the original symbol to be used. */
2359 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2361 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2365 /* Don't adjust pc-relative references to merge sections in 64-bit
2367 if (use_rela_relocations
2368 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2372 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2373 and changed later by validate_fix. */
2374 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2375 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2378 /* adjust_reloc_syms doesn't know about the GOT. */
2379 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2380 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2381 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2382 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2383 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2384 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2385 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2386 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2387 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2388 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2389 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2390 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2391 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2392 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2393 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2394 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2395 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2396 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2397 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2398 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2399 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2400 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2401 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2402 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2403 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2404 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2405 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2406 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2413 intel_float_operand (const char *mnemonic
)
2415 /* Note that the value returned is meaningful only for opcodes with (memory)
2416 operands, hence the code here is free to improperly handle opcodes that
2417 have no operands (for better performance and smaller code). */
2419 if (mnemonic
[0] != 'f')
2420 return 0; /* non-math */
2422 switch (mnemonic
[1])
2424 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2425 the fs segment override prefix not currently handled because no
2426 call path can make opcodes without operands get here */
2428 return 2 /* integer op */;
2430 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2431 return 3; /* fldcw/fldenv */
2434 if (mnemonic
[2] != 'o' /* fnop */)
2435 return 3; /* non-waiting control op */
2438 if (mnemonic
[2] == 's')
2439 return 3; /* frstor/frstpm */
2442 if (mnemonic
[2] == 'a')
2443 return 3; /* fsave */
2444 if (mnemonic
[2] == 't')
2446 switch (mnemonic
[3])
2448 case 'c': /* fstcw */
2449 case 'd': /* fstdw */
2450 case 'e': /* fstenv */
2451 case 's': /* fsts[gw] */
2457 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2458 return 0; /* fxsave/fxrstor are not really math ops */
2465 /* Build the VEX prefix. */
2468 build_vex_prefix (void)
2470 unsigned int register_specifier
;
2471 unsigned int implied_prefix
;
2472 unsigned int vector_length
;
2474 /* Check register specifier. */
2475 if (i
.vex
.register_specifier
)
2477 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2478 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2479 register_specifier
+= 8;
2480 register_specifier
= ~register_specifier
& 0xf;
2483 register_specifier
= 0xf;
2485 vector_length
= i
.tm
.opcode_modifier
.vex256
? 1 : 0;
2487 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2492 case DATA_PREFIX_OPCODE
:
2495 case REPE_PREFIX_OPCODE
:
2498 case REPNE_PREFIX_OPCODE
:
2505 /* Use 2-byte VEX prefix if possible. */
2506 if (i
.tm
.opcode_modifier
.vex0f
2507 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2509 /* 2-byte VEX prefix. */
2513 i
.vex
.bytes
[0] = 0xc5;
2515 /* Check the REX.R bit. */
2516 r
= (i
.rex
& REX_R
) ? 0 : 1;
2517 i
.vex
.bytes
[1] = (r
<< 7
2518 | register_specifier
<< 3
2519 | vector_length
<< 2
2524 /* 3-byte VEX prefix. */
2527 if (i
.tm
.opcode_modifier
.vex0f
)
2529 else if (i
.tm
.opcode_modifier
.vex0f38
)
2531 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2537 i
.vex
.bytes
[0] = 0xc4;
2539 /* The high 3 bits of the second VEX byte are 1's compliment
2540 of RXB bits from REX. */
2541 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2543 /* Check the REX.W bit. */
2544 w
= (i
.rex
& REX_W
) ? 1 : 0;
2545 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2550 if (i
.tm
.opcode_modifier
.vexw1
)
2554 i
.vex
.bytes
[2] = (w
<< 7
2555 | register_specifier
<< 3
2556 | vector_length
<< 2
2562 process_immext (void)
2566 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2568 /* SSE3 Instructions have the fixed operands with an opcode
2569 suffix which is coded in the same place as an 8-bit immediate
2570 field would be. Here we check those operands and remove them
2574 for (x
= 0; x
< i
.operands
; x
++)
2575 if (i
.op
[x
].regs
->reg_num
!= x
)
2576 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2577 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2583 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2584 which is coded in the same place as an 8-bit immediate field
2585 would be. Here we fake an 8-bit immediate operand from the
2586 opcode suffix stored in tm.extension_opcode.
2588 SSE5 and AVX instructions also use this encoding, for some of
2589 3 argument instructions. */
2591 assert (i
.imm_operands
== 0
2593 || (i
.tm
.cpu_flags
.bitfield
.cpusse5
2595 || (i
.tm
.opcode_modifier
.vex
2596 && i
.operands
<= 4)));
2598 exp
= &im_expressions
[i
.imm_operands
++];
2599 i
.op
[i
.operands
].imms
= exp
;
2600 i
.types
[i
.operands
] = imm8
;
2602 exp
->X_op
= O_constant
;
2603 exp
->X_add_number
= i
.tm
.extension_opcode
;
2604 i
.tm
.extension_opcode
= None
;
2607 /* This is the guts of the machine-dependent assembler. LINE points to a
2608 machine dependent instruction. This function is supposed to emit
2609 the frags/bytes it assembles to. */
2612 md_assemble (char *line
)
2615 char mnemonic
[MAX_MNEM_SIZE
];
2617 /* Initialize globals. */
2618 memset (&i
, '\0', sizeof (i
));
2619 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2620 i
.reloc
[j
] = NO_RELOC
;
2621 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2622 memset (im_expressions
, '\0', sizeof (im_expressions
));
2623 save_stack_p
= save_stack
;
2625 /* First parse an instruction mnemonic & call i386_operand for the operands.
2626 We assume that the scrubber has arranged it so that line[0] is the valid
2627 start of a (possibly prefixed) mnemonic. */
2629 line
= parse_insn (line
, mnemonic
);
2633 line
= parse_operands (line
, mnemonic
);
2637 /* Now we've parsed the mnemonic into a set of templates, and have the
2638 operands at hand. */
2640 /* All intel opcodes have reversed operands except for "bound" and
2641 "enter". We also don't reverse intersegment "jmp" and "call"
2642 instructions with 2 immediate operands so that the immediate segment
2643 precedes the offset, as it does when in AT&T mode. */
2646 && (strcmp (mnemonic
, "bound") != 0)
2647 && (strcmp (mnemonic
, "invlpga") != 0)
2648 && !(operand_type_check (i
.types
[0], imm
)
2649 && operand_type_check (i
.types
[1], imm
)))
2652 /* The order of the immediates should be reversed
2653 for 2 immediates extrq and insertq instructions */
2654 if (i
.imm_operands
== 2
2655 && (strcmp (mnemonic
, "extrq") == 0
2656 || strcmp (mnemonic
, "insertq") == 0))
2657 swap_2_operands (0, 1);
2662 /* Don't optimize displacement for movabs since it only takes 64bit
2665 && (flag_code
!= CODE_64BIT
2666 || strcmp (mnemonic
, "movabs") != 0))
2669 /* Next, we find a template that matches the given insn,
2670 making sure the overlap of the given operands types is consistent
2671 with the template operand types. */
2673 if (!match_template ())
2676 if (sse_check
!= sse_check_none
2677 && !i
.tm
.opcode_modifier
.noavx
2678 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2679 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2680 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2681 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2682 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2683 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2685 (sse_check
== sse_check_warning
2687 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2690 /* Zap movzx and movsx suffix. The suffix has been set from
2691 "word ptr" or "byte ptr" on the source operand in Intel syntax
2692 or extracted from mnemonic in AT&T syntax. But we'll use
2693 the destination register to choose the suffix for encoding. */
2694 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2696 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2697 there is no suffix, the default will be byte extension. */
2698 if (i
.reg_operands
!= 2
2701 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2706 if (i
.tm
.opcode_modifier
.fwait
)
2707 if (!add_prefix (FWAIT_OPCODE
))
2710 /* Check string instruction segment overrides. */
2711 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2713 if (!check_string ())
2717 if (!process_suffix ())
2720 /* Make still unresolved immediate matches conform to size of immediate
2721 given in i.suffix. */
2722 if (!finalize_imm ())
2725 if (i
.types
[0].bitfield
.imm1
)
2726 i
.imm_operands
= 0; /* kludge for shift insns. */
2728 for (j
= 0; j
< 3; j
++)
2729 if (i
.types
[j
].bitfield
.inoutportreg
2730 || i
.types
[j
].bitfield
.shiftcount
2731 || i
.types
[j
].bitfield
.acc
2732 || i
.types
[j
].bitfield
.floatacc
)
2735 /* ImmExt should be processed after SSE2AVX. */
2736 if (!i
.tm
.opcode_modifier
.sse2avx
2737 && i
.tm
.opcode_modifier
.immext
)
2740 /* For insns with operands there are more diddles to do to the opcode. */
2743 if (!process_operands ())
2746 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2748 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2749 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2752 if (i
.tm
.opcode_modifier
.vex
)
2753 build_vex_prefix ();
2755 /* Handle conversion of 'int $3' --> special int3 insn. */
2756 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2758 i
.tm
.base_opcode
= INT3_OPCODE
;
2762 if ((i
.tm
.opcode_modifier
.jump
2763 || i
.tm
.opcode_modifier
.jumpbyte
2764 || i
.tm
.opcode_modifier
.jumpdword
)
2765 && i
.op
[0].disps
->X_op
== O_constant
)
2767 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2768 the absolute address given by the constant. Since ix86 jumps and
2769 calls are pc relative, we need to generate a reloc. */
2770 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2771 i
.op
[0].disps
->X_op
= O_symbol
;
2774 if (i
.tm
.opcode_modifier
.rex64
)
2777 /* For 8 bit registers we need an empty rex prefix. Also if the
2778 instruction already has a prefix, we need to convert old
2779 registers to new ones. */
2781 if ((i
.types
[0].bitfield
.reg8
2782 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2783 || (i
.types
[1].bitfield
.reg8
2784 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2785 || ((i
.types
[0].bitfield
.reg8
2786 || i
.types
[1].bitfield
.reg8
)
2791 i
.rex
|= REX_OPCODE
;
2792 for (x
= 0; x
< 2; x
++)
2794 /* Look for 8 bit operand that uses old registers. */
2795 if (i
.types
[x
].bitfield
.reg8
2796 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2798 /* In case it is "hi" register, give up. */
2799 if (i
.op
[x
].regs
->reg_num
> 3)
2800 as_bad (_("can't encode register '%s%s' in an "
2801 "instruction requiring REX prefix."),
2802 register_prefix
, i
.op
[x
].regs
->reg_name
);
2804 /* Otherwise it is equivalent to the extended register.
2805 Since the encoding doesn't change this is merely
2806 cosmetic cleanup for debug output. */
2808 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2813 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2815 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
2820 else if (i
.rex
!= 0)
2821 add_prefix (REX_OPCODE
| i
.rex
);
2823 /* We are ready to output the insn. */
2828 parse_insn (char *line
, char *mnemonic
)
2831 char *token_start
= l
;
2836 /* Non-zero if we found a prefix only acceptable with string insns. */
2837 const char *expecting_string_instruction
= NULL
;
2842 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
2845 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
2847 as_bad (_("no such instruction: `%s'"), token_start
);
2852 if (!is_space_char (*l
)
2853 && *l
!= END_OF_INSN
2855 || (*l
!= PREFIX_SEPARATOR
2858 as_bad (_("invalid character %s in mnemonic"),
2859 output_invalid (*l
));
2862 if (token_start
== l
)
2864 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
2865 as_bad (_("expecting prefix; got nothing"));
2867 as_bad (_("expecting mnemonic; got nothing"));
2871 /* Look up instruction (or prefix) via hash table. */
2872 current_templates
= hash_find (op_hash
, mnemonic
);
2874 if (*l
!= END_OF_INSN
2875 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
2876 && current_templates
2877 && current_templates
->start
->opcode_modifier
.isprefix
)
2879 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
2881 as_bad ((flag_code
!= CODE_64BIT
2882 ? _("`%s' is only supported in 64-bit mode")
2883 : _("`%s' is not supported in 64-bit mode")),
2884 current_templates
->start
->name
);
2887 /* If we are in 16-bit mode, do not allow addr16 or data16.
2888 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2889 if ((current_templates
->start
->opcode_modifier
.size16
2890 || current_templates
->start
->opcode_modifier
.size32
)
2891 && flag_code
!= CODE_64BIT
2892 && (current_templates
->start
->opcode_modifier
.size32
2893 ^ (flag_code
== CODE_16BIT
)))
2895 as_bad (_("redundant %s prefix"),
2896 current_templates
->start
->name
);
2899 /* Add prefix, checking for repeated prefixes. */
2900 switch (add_prefix (current_templates
->start
->base_opcode
))
2905 expecting_string_instruction
= current_templates
->start
->name
;
2908 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2915 if (!current_templates
)
2917 /* See if we can get a match by trimming off a suffix. */
2920 case WORD_MNEM_SUFFIX
:
2921 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
2922 i
.suffix
= SHORT_MNEM_SUFFIX
;
2924 case BYTE_MNEM_SUFFIX
:
2925 case QWORD_MNEM_SUFFIX
:
2926 i
.suffix
= mnem_p
[-1];
2928 current_templates
= hash_find (op_hash
, mnemonic
);
2930 case SHORT_MNEM_SUFFIX
:
2931 case LONG_MNEM_SUFFIX
:
2934 i
.suffix
= mnem_p
[-1];
2936 current_templates
= hash_find (op_hash
, mnemonic
);
2944 if (intel_float_operand (mnemonic
) == 1)
2945 i
.suffix
= SHORT_MNEM_SUFFIX
;
2947 i
.suffix
= LONG_MNEM_SUFFIX
;
2949 current_templates
= hash_find (op_hash
, mnemonic
);
2953 if (!current_templates
)
2955 as_bad (_("no such instruction: `%s'"), token_start
);
2960 if (current_templates
->start
->opcode_modifier
.jump
2961 || current_templates
->start
->opcode_modifier
.jumpbyte
)
2963 /* Check for a branch hint. We allow ",pt" and ",pn" for
2964 predict taken and predict not taken respectively.
2965 I'm not sure that branch hints actually do anything on loop
2966 and jcxz insns (JumpByte) for current Pentium4 chips. They
2967 may work in the future and it doesn't hurt to accept them
2969 if (l
[0] == ',' && l
[1] == 'p')
2973 if (!add_prefix (DS_PREFIX_OPCODE
))
2977 else if (l
[2] == 'n')
2979 if (!add_prefix (CS_PREFIX_OPCODE
))
2985 /* Any other comma loses. */
2988 as_bad (_("invalid character %s in mnemonic"),
2989 output_invalid (*l
));
2993 /* Check if instruction is supported on specified architecture. */
2995 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2997 supported
|= cpu_flags_match (t
);
2998 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3002 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3004 as_bad (flag_code
== CODE_64BIT
3005 ? _("`%s' is not supported in 64-bit mode")
3006 : _("`%s' is only supported in 64-bit mode"),
3007 current_templates
->start
->name
);
3010 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3012 as_bad (_("`%s' is not supported on `%s%s'"),
3013 current_templates
->start
->name
, cpu_arch_name
,
3014 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3019 if (!cpu_arch_flags
.bitfield
.cpui386
3020 && (flag_code
!= CODE_16BIT
))
3022 as_warn (_("use .code16 to ensure correct addressing mode"));
3025 /* Check for rep/repne without a string instruction. */
3026 if (expecting_string_instruction
)
3028 static templates override
;
3030 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3031 if (t
->opcode_modifier
.isstring
)
3033 if (t
>= current_templates
->end
)
3035 as_bad (_("expecting string instruction after `%s'"),
3036 expecting_string_instruction
);
3039 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3040 if (!t
->opcode_modifier
.isstring
)
3043 current_templates
= &override
;
3050 parse_operands (char *l
, const char *mnemonic
)
3054 /* 1 if operand is pending after ','. */
3055 unsigned int expecting_operand
= 0;
3057 /* Non-zero if operand parens not balanced. */
3058 unsigned int paren_not_balanced
;
3060 while (*l
!= END_OF_INSN
)
3062 /* Skip optional white space before operand. */
3063 if (is_space_char (*l
))
3065 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3067 as_bad (_("invalid character %s before operand %d"),
3068 output_invalid (*l
),
3072 token_start
= l
; /* after white space */
3073 paren_not_balanced
= 0;
3074 while (paren_not_balanced
|| *l
!= ',')
3076 if (*l
== END_OF_INSN
)
3078 if (paren_not_balanced
)
3081 as_bad (_("unbalanced parenthesis in operand %d."),
3084 as_bad (_("unbalanced brackets in operand %d."),
3089 break; /* we are done */
3091 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3093 as_bad (_("invalid character %s in operand %d"),
3094 output_invalid (*l
),
3101 ++paren_not_balanced
;
3103 --paren_not_balanced
;
3108 ++paren_not_balanced
;
3110 --paren_not_balanced
;
3114 if (l
!= token_start
)
3115 { /* Yes, we've read in another operand. */
3116 unsigned int operand_ok
;
3117 this_operand
= i
.operands
++;
3118 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3119 if (i
.operands
> MAX_OPERANDS
)
3121 as_bad (_("spurious operands; (%d operands/instruction max)"),
3125 /* Now parse operand adding info to 'i' as we go along. */
3126 END_STRING_AND_SAVE (l
);
3130 i386_intel_operand (token_start
,
3131 intel_float_operand (mnemonic
));
3133 operand_ok
= i386_att_operand (token_start
);
3135 RESTORE_END_STRING (l
);
3141 if (expecting_operand
)
3143 expecting_operand_after_comma
:
3144 as_bad (_("expecting operand after ','; got nothing"));
3149 as_bad (_("expecting operand before ','; got nothing"));
3154 /* Now *l must be either ',' or END_OF_INSN. */
3157 if (*++l
== END_OF_INSN
)
3159 /* Just skip it, if it's \n complain. */
3160 goto expecting_operand_after_comma
;
3162 expecting_operand
= 1;
3169 swap_2_operands (int xchg1
, int xchg2
)
3171 union i386_op temp_op
;
3172 i386_operand_type temp_type
;
3173 enum bfd_reloc_code_real temp_reloc
;
3175 temp_type
= i
.types
[xchg2
];
3176 i
.types
[xchg2
] = i
.types
[xchg1
];
3177 i
.types
[xchg1
] = temp_type
;
3178 temp_op
= i
.op
[xchg2
];
3179 i
.op
[xchg2
] = i
.op
[xchg1
];
3180 i
.op
[xchg1
] = temp_op
;
3181 temp_reloc
= i
.reloc
[xchg2
];
3182 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3183 i
.reloc
[xchg1
] = temp_reloc
;
3187 swap_operands (void)
3193 swap_2_operands (1, i
.operands
- 2);
3196 swap_2_operands (0, i
.operands
- 1);
3202 if (i
.mem_operands
== 2)
3204 const seg_entry
*temp_seg
;
3205 temp_seg
= i
.seg
[0];
3206 i
.seg
[0] = i
.seg
[1];
3207 i
.seg
[1] = temp_seg
;
3211 /* Try to ensure constant immediates are represented in the smallest
3216 char guess_suffix
= 0;
3220 guess_suffix
= i
.suffix
;
3221 else if (i
.reg_operands
)
3223 /* Figure out a suffix from the last register operand specified.
3224 We can't do this properly yet, ie. excluding InOutPortReg,
3225 but the following works for instructions with immediates.
3226 In any case, we can't set i.suffix yet. */
3227 for (op
= i
.operands
; --op
>= 0;)
3228 if (i
.types
[op
].bitfield
.reg8
)
3230 guess_suffix
= BYTE_MNEM_SUFFIX
;
3233 else if (i
.types
[op
].bitfield
.reg16
)
3235 guess_suffix
= WORD_MNEM_SUFFIX
;
3238 else if (i
.types
[op
].bitfield
.reg32
)
3240 guess_suffix
= LONG_MNEM_SUFFIX
;
3243 else if (i
.types
[op
].bitfield
.reg64
)
3245 guess_suffix
= QWORD_MNEM_SUFFIX
;
3249 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3250 guess_suffix
= WORD_MNEM_SUFFIX
;
3252 for (op
= i
.operands
; --op
>= 0;)
3253 if (operand_type_check (i
.types
[op
], imm
))
3255 switch (i
.op
[op
].imms
->X_op
)
3258 /* If a suffix is given, this operand may be shortened. */
3259 switch (guess_suffix
)
3261 case LONG_MNEM_SUFFIX
:
3262 i
.types
[op
].bitfield
.imm32
= 1;
3263 i
.types
[op
].bitfield
.imm64
= 1;
3265 case WORD_MNEM_SUFFIX
:
3266 i
.types
[op
].bitfield
.imm16
= 1;
3267 i
.types
[op
].bitfield
.imm32
= 1;
3268 i
.types
[op
].bitfield
.imm32s
= 1;
3269 i
.types
[op
].bitfield
.imm64
= 1;
3271 case BYTE_MNEM_SUFFIX
:
3272 i
.types
[op
].bitfield
.imm8
= 1;
3273 i
.types
[op
].bitfield
.imm8s
= 1;
3274 i
.types
[op
].bitfield
.imm16
= 1;
3275 i
.types
[op
].bitfield
.imm32
= 1;
3276 i
.types
[op
].bitfield
.imm32s
= 1;
3277 i
.types
[op
].bitfield
.imm64
= 1;
3281 /* If this operand is at most 16 bits, convert it
3282 to a signed 16 bit number before trying to see
3283 whether it will fit in an even smaller size.
3284 This allows a 16-bit operand such as $0xffe0 to
3285 be recognised as within Imm8S range. */
3286 if ((i
.types
[op
].bitfield
.imm16
)
3287 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3289 i
.op
[op
].imms
->X_add_number
=
3290 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3292 if ((i
.types
[op
].bitfield
.imm32
)
3293 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3296 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3297 ^ ((offsetT
) 1 << 31))
3298 - ((offsetT
) 1 << 31));
3301 = operand_type_or (i
.types
[op
],
3302 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3304 /* We must avoid matching of Imm32 templates when 64bit
3305 only immediate is available. */
3306 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3307 i
.types
[op
].bitfield
.imm32
= 0;
3314 /* Symbols and expressions. */
3316 /* Convert symbolic operand to proper sizes for matching, but don't
3317 prevent matching a set of insns that only supports sizes other
3318 than those matching the insn suffix. */
3320 i386_operand_type mask
, allowed
;
3323 operand_type_set (&mask
, 0);
3324 operand_type_set (&allowed
, 0);
3326 for (t
= current_templates
->start
;
3327 t
< current_templates
->end
;
3329 allowed
= operand_type_or (allowed
,
3330 t
->operand_types
[op
]);
3331 switch (guess_suffix
)
3333 case QWORD_MNEM_SUFFIX
:
3334 mask
.bitfield
.imm64
= 1;
3335 mask
.bitfield
.imm32s
= 1;
3337 case LONG_MNEM_SUFFIX
:
3338 mask
.bitfield
.imm32
= 1;
3340 case WORD_MNEM_SUFFIX
:
3341 mask
.bitfield
.imm16
= 1;
3343 case BYTE_MNEM_SUFFIX
:
3344 mask
.bitfield
.imm8
= 1;
3349 allowed
= operand_type_and (mask
, allowed
);
3350 if (!operand_type_all_zero (&allowed
))
3351 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3358 /* Try to use the smallest displacement type too. */
3360 optimize_disp (void)
3364 for (op
= i
.operands
; --op
>= 0;)
3365 if (operand_type_check (i
.types
[op
], disp
))
3367 if (i
.op
[op
].disps
->X_op
== O_constant
)
3369 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3371 if (i
.types
[op
].bitfield
.disp16
3372 && (disp
& ~(offsetT
) 0xffff) == 0)
3374 /* If this operand is at most 16 bits, convert
3375 to a signed 16 bit number and don't use 64bit
3377 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3378 i
.types
[op
].bitfield
.disp64
= 0;
3380 if (i
.types
[op
].bitfield
.disp32
3381 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3383 /* If this operand is at most 32 bits, convert
3384 to a signed 32 bit number and don't use 64bit
3386 disp
&= (((offsetT
) 2 << 31) - 1);
3387 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3388 i
.types
[op
].bitfield
.disp64
= 0;
3390 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3392 i
.types
[op
].bitfield
.disp8
= 0;
3393 i
.types
[op
].bitfield
.disp16
= 0;
3394 i
.types
[op
].bitfield
.disp32
= 0;
3395 i
.types
[op
].bitfield
.disp32s
= 0;
3396 i
.types
[op
].bitfield
.disp64
= 0;
3400 else if (flag_code
== CODE_64BIT
)
3402 if (fits_in_signed_long (disp
))
3404 i
.types
[op
].bitfield
.disp64
= 0;
3405 i
.types
[op
].bitfield
.disp32s
= 1;
3407 if (fits_in_unsigned_long (disp
))
3408 i
.types
[op
].bitfield
.disp32
= 1;
3410 if ((i
.types
[op
].bitfield
.disp32
3411 || i
.types
[op
].bitfield
.disp32s
3412 || i
.types
[op
].bitfield
.disp16
)
3413 && fits_in_signed_byte (disp
))
3414 i
.types
[op
].bitfield
.disp8
= 1;
3416 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3417 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3419 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3420 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3421 i
.types
[op
].bitfield
.disp8
= 0;
3422 i
.types
[op
].bitfield
.disp16
= 0;
3423 i
.types
[op
].bitfield
.disp32
= 0;
3424 i
.types
[op
].bitfield
.disp32s
= 0;
3425 i
.types
[op
].bitfield
.disp64
= 0;
3428 /* We only support 64bit displacement on constants. */
3429 i
.types
[op
].bitfield
.disp64
= 0;
3433 /* Check if operands are valid for the instrucrtion. Update VEX
3437 VEX_check_operands (const template *t
)
3439 if (!t
->opcode_modifier
.vex
)
3442 /* Only check VEX_Imm4, which must be the first operand. */
3443 if (t
->operand_types
[0].bitfield
.vex_imm4
)
3445 if (i
.op
[0].imms
->X_op
!= O_constant
3446 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
3449 /* Turn off Imm8 so that update_imm won't complain. */
3450 i
.types
[0] = vex_imm4
;
3457 match_template (void)
3459 /* Points to template once we've found it. */
3461 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3462 i386_operand_type overlap4
;
3463 unsigned int found_reverse_match
;
3464 i386_opcode_modifier suffix_check
;
3465 i386_operand_type operand_types
[MAX_OPERANDS
];
3466 int addr_prefix_disp
;
3468 unsigned int found_cpu_match
;
3469 unsigned int check_register
;
3471 #if MAX_OPERANDS != 5
3472 # error "MAX_OPERANDS must be 5."
3475 found_reverse_match
= 0;
3476 addr_prefix_disp
= -1;
3478 memset (&suffix_check
, 0, sizeof (suffix_check
));
3479 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3480 suffix_check
.no_bsuf
= 1;
3481 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3482 suffix_check
.no_wsuf
= 1;
3483 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3484 suffix_check
.no_ssuf
= 1;
3485 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3486 suffix_check
.no_lsuf
= 1;
3487 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3488 suffix_check
.no_qsuf
= 1;
3489 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3490 suffix_check
.no_ldsuf
= 1;
3492 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3494 addr_prefix_disp
= -1;
3496 /* Must have right number of operands. */
3497 if (i
.operands
!= t
->operands
)
3500 /* Check processor support. */
3501 found_cpu_match
= (cpu_flags_match (t
)
3502 == CPU_FLAGS_PERFECT_MATCH
);
3503 if (!found_cpu_match
)
3506 /* Check old gcc support. */
3507 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3510 /* Check AT&T mnemonic. */
3511 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3514 /* Check AT&T syntax Intel syntax. */
3515 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3516 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3519 /* Check the suffix, except for some instructions in intel mode. */
3520 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3521 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3522 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3523 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3524 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3525 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3526 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3529 if (!operand_size_match (t
))
3532 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3533 operand_types
[j
] = t
->operand_types
[j
];
3535 /* In general, don't allow 64-bit operands in 32-bit mode. */
3536 if (i
.suffix
== QWORD_MNEM_SUFFIX
3537 && flag_code
!= CODE_64BIT
3539 ? (!t
->opcode_modifier
.ignoresize
3540 && !intel_float_operand (t
->name
))
3541 : intel_float_operand (t
->name
) != 2)
3542 && ((!operand_types
[0].bitfield
.regmmx
3543 && !operand_types
[0].bitfield
.regxmm
3544 && !operand_types
[0].bitfield
.regymm
)
3545 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3546 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3547 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3548 && (t
->base_opcode
!= 0x0fc7
3549 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3552 /* In general, don't allow 32-bit operands on pre-386. */
3553 else if (i
.suffix
== LONG_MNEM_SUFFIX
3554 && !cpu_arch_flags
.bitfield
.cpui386
3556 ? (!t
->opcode_modifier
.ignoresize
3557 && !intel_float_operand (t
->name
))
3558 : intel_float_operand (t
->name
) != 2)
3559 && ((!operand_types
[0].bitfield
.regmmx
3560 && !operand_types
[0].bitfield
.regxmm
)
3561 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3562 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3565 /* Do not verify operands when there are none. */
3569 /* We've found a match; break out of loop. */
3573 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3574 into Disp32/Disp16/Disp32 operand. */
3575 if (i
.prefix
[ADDR_PREFIX
] != 0)
3577 /* There should be only one Disp operand. */
3581 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3583 if (operand_types
[j
].bitfield
.disp16
)
3585 addr_prefix_disp
= j
;
3586 operand_types
[j
].bitfield
.disp32
= 1;
3587 operand_types
[j
].bitfield
.disp16
= 0;
3593 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3595 if (operand_types
[j
].bitfield
.disp32
)
3597 addr_prefix_disp
= j
;
3598 operand_types
[j
].bitfield
.disp32
= 0;
3599 operand_types
[j
].bitfield
.disp16
= 1;
3605 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3607 if (operand_types
[j
].bitfield
.disp64
)
3609 addr_prefix_disp
= j
;
3610 operand_types
[j
].bitfield
.disp64
= 0;
3611 operand_types
[j
].bitfield
.disp32
= 1;
3619 /* We check register size only if size of operands can be
3620 encoded the canonical way. */
3621 check_register
= t
->opcode_modifier
.w
;
3622 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3623 switch (t
->operands
)
3626 if (!operand_type_match (overlap0
, i
.types
[0]))
3630 /* xchg %eax, %eax is a special case. It is an aliase for nop
3631 only in 32bit mode and we can use opcode 0x90. In 64bit
3632 mode, we can't use 0x90 for xchg %eax, %eax since it should
3633 zero-extend %eax to %rax. */
3634 if (flag_code
== CODE_64BIT
3635 && t
->base_opcode
== 0x90
3636 && operand_type_equal (&i
.types
[0], &acc32
)
3637 && operand_type_equal (&i
.types
[1], &acc32
))
3642 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3643 if (!operand_type_match (overlap0
, i
.types
[0])
3644 || !operand_type_match (overlap1
, i
.types
[1])
3646 && !operand_type_register_match (overlap0
, i
.types
[0],
3648 overlap1
, i
.types
[1],
3651 /* Check if other direction is valid ... */
3652 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3655 /* Try reversing direction of operands. */
3656 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3657 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3658 if (!operand_type_match (overlap0
, i
.types
[0])
3659 || !operand_type_match (overlap1
, i
.types
[1])
3661 && !operand_type_register_match (overlap0
,
3668 /* Does not match either direction. */
3671 /* found_reverse_match holds which of D or FloatDR
3673 if (t
->opcode_modifier
.d
)
3674 found_reverse_match
= Opcode_D
;
3675 else if (t
->opcode_modifier
.floatd
)
3676 found_reverse_match
= Opcode_FloatD
;
3678 found_reverse_match
= 0;
3679 if (t
->opcode_modifier
.floatr
)
3680 found_reverse_match
|= Opcode_FloatR
;
3684 /* Found a forward 2 operand match here. */
3685 switch (t
->operands
)
3688 overlap4
= operand_type_and (i
.types
[4],
3691 overlap3
= operand_type_and (i
.types
[3],
3694 overlap2
= operand_type_and (i
.types
[2],
3699 switch (t
->operands
)
3702 if (!operand_type_match (overlap4
, i
.types
[4])
3703 || !operand_type_register_match (overlap3
,
3711 if (!operand_type_match (overlap3
, i
.types
[3])
3713 && !operand_type_register_match (overlap2
,
3721 /* Here we make use of the fact that there are no
3722 reverse match 3 operand instructions, and all 3
3723 operand instructions only need to be checked for
3724 register consistency between operands 2 and 3. */
3725 if (!operand_type_match (overlap2
, i
.types
[2])
3727 && !operand_type_register_match (overlap1
,
3737 /* Found either forward/reverse 2, 3 or 4 operand match here:
3738 slip through to break. */
3740 if (!found_cpu_match
)
3742 found_reverse_match
= 0;
3746 /* Check if VEX operands are valid. */
3747 if (VEX_check_operands (t
))
3750 /* We've found a match; break out of loop. */
3754 if (t
== current_templates
->end
)
3756 /* We found no match. */
3757 as_bad (_("suffix or operands invalid for `%s'"),
3758 current_templates
->start
->name
);
3762 if (!quiet_warnings
)
3765 && (i
.types
[0].bitfield
.jumpabsolute
3766 != operand_types
[0].bitfield
.jumpabsolute
))
3768 as_warn (_("indirect %s without `*'"), t
->name
);
3771 if (t
->opcode_modifier
.isprefix
3772 && t
->opcode_modifier
.ignoresize
)
3774 /* Warn them that a data or address size prefix doesn't
3775 affect assembly of the next line of code. */
3776 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3780 /* Copy the template we found. */
3783 if (addr_prefix_disp
!= -1)
3784 i
.tm
.operand_types
[addr_prefix_disp
]
3785 = operand_types
[addr_prefix_disp
];
3787 if (found_reverse_match
)
3789 /* If we found a reverse match we must alter the opcode
3790 direction bit. found_reverse_match holds bits to change
3791 (different for int & float insns). */
3793 i
.tm
.base_opcode
^= found_reverse_match
;
3795 i
.tm
.operand_types
[0] = operand_types
[1];
3796 i
.tm
.operand_types
[1] = operand_types
[0];
3805 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
3806 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
3808 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
3810 as_bad (_("`%s' operand %d must use `%%es' segment"),
3815 /* There's only ever one segment override allowed per instruction.
3816 This instruction possibly has a legal segment override on the
3817 second operand, so copy the segment to where non-string
3818 instructions store it, allowing common code. */
3819 i
.seg
[0] = i
.seg
[1];
3821 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
3823 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
3825 as_bad (_("`%s' operand %d must use `%%es' segment"),
3835 process_suffix (void)
3837 /* If matched instruction specifies an explicit instruction mnemonic
3839 if (i
.tm
.opcode_modifier
.size16
)
3840 i
.suffix
= WORD_MNEM_SUFFIX
;
3841 else if (i
.tm
.opcode_modifier
.size32
)
3842 i
.suffix
= LONG_MNEM_SUFFIX
;
3843 else if (i
.tm
.opcode_modifier
.size64
)
3844 i
.suffix
= QWORD_MNEM_SUFFIX
;
3845 else if (i
.reg_operands
)
3847 /* If there's no instruction mnemonic suffix we try to invent one
3848 based on register operands. */
3851 /* We take i.suffix from the last register operand specified,
3852 Destination register type is more significant than source
3853 register type. crc32 in SSE4.2 prefers source register
3855 if (i
.tm
.base_opcode
== 0xf20f38f1)
3857 if (i
.types
[0].bitfield
.reg16
)
3858 i
.suffix
= WORD_MNEM_SUFFIX
;
3859 else if (i
.types
[0].bitfield
.reg32
)
3860 i
.suffix
= LONG_MNEM_SUFFIX
;
3861 else if (i
.types
[0].bitfield
.reg64
)
3862 i
.suffix
= QWORD_MNEM_SUFFIX
;
3864 else if (i
.tm
.base_opcode
== 0xf20f38f0)
3866 if (i
.types
[0].bitfield
.reg8
)
3867 i
.suffix
= BYTE_MNEM_SUFFIX
;
3874 if (i
.tm
.base_opcode
== 0xf20f38f1
3875 || i
.tm
.base_opcode
== 0xf20f38f0)
3877 /* We have to know the operand size for crc32. */
3878 as_bad (_("ambiguous memory operand size for `%s`"),
3883 for (op
= i
.operands
; --op
>= 0;)
3884 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
3886 if (i
.types
[op
].bitfield
.reg8
)
3888 i
.suffix
= BYTE_MNEM_SUFFIX
;
3891 else if (i
.types
[op
].bitfield
.reg16
)
3893 i
.suffix
= WORD_MNEM_SUFFIX
;
3896 else if (i
.types
[op
].bitfield
.reg32
)
3898 i
.suffix
= LONG_MNEM_SUFFIX
;
3901 else if (i
.types
[op
].bitfield
.reg64
)
3903 i
.suffix
= QWORD_MNEM_SUFFIX
;
3909 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3911 if (!check_byte_reg ())
3914 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3916 if (!check_long_reg ())
3919 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3922 && i
.tm
.opcode_modifier
.ignoresize
3923 && i
.tm
.opcode_modifier
.no_qsuf
)
3925 else if (!check_qword_reg ())
3928 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3930 if (!check_word_reg ())
3933 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
3934 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
3936 /* Skip if the instruction has x/y suffix. match_template
3937 should check if it is a valid suffix. */
3939 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
3940 /* Do nothing if the instruction is going to ignore the prefix. */
3945 else if (i
.tm
.opcode_modifier
.defaultsize
3947 /* exclude fldenv/frstor/fsave/fstenv */
3948 && i
.tm
.opcode_modifier
.no_ssuf
)
3950 i
.suffix
= stackop_size
;
3952 else if (intel_syntax
3954 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
3955 || i
.tm
.opcode_modifier
.jumpbyte
3956 || i
.tm
.opcode_modifier
.jumpintersegment
3957 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
3958 && i
.tm
.extension_opcode
<= 3)))
3963 if (!i
.tm
.opcode_modifier
.no_qsuf
)
3965 i
.suffix
= QWORD_MNEM_SUFFIX
;
3969 if (!i
.tm
.opcode_modifier
.no_lsuf
)
3970 i
.suffix
= LONG_MNEM_SUFFIX
;
3973 if (!i
.tm
.opcode_modifier
.no_wsuf
)
3974 i
.suffix
= WORD_MNEM_SUFFIX
;
3983 if (i
.tm
.opcode_modifier
.w
)
3985 as_bad (_("no instruction mnemonic suffix given and "
3986 "no register operands; can't size instruction"));
3992 unsigned int suffixes
;
3994 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
3995 if (!i
.tm
.opcode_modifier
.no_wsuf
)
3997 if (!i
.tm
.opcode_modifier
.no_lsuf
)
3999 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4001 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4003 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4006 /* There are more than suffix matches. */
4007 if (i
.tm
.opcode_modifier
.w
4008 || ((suffixes
& (suffixes
- 1))
4009 && !i
.tm
.opcode_modifier
.defaultsize
4010 && !i
.tm
.opcode_modifier
.ignoresize
))
4012 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4018 /* Change the opcode based on the operand size given by i.suffix;
4019 We don't need to change things for byte insns. */
4022 && i
.suffix
!= BYTE_MNEM_SUFFIX
4023 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4024 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4026 /* It's not a byte, select word/dword operation. */
4027 if (i
.tm
.opcode_modifier
.w
)
4029 if (i
.tm
.opcode_modifier
.shortform
)
4030 i
.tm
.base_opcode
|= 8;
4032 i
.tm
.base_opcode
|= 1;
4035 /* Now select between word & dword operations via the operand
4036 size prefix, except for instructions that will ignore this
4038 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4040 /* The address size override prefix changes the size of the
4042 if ((flag_code
== CODE_32BIT
4043 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4044 || (flag_code
!= CODE_32BIT
4045 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4046 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4049 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4050 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4051 && !i
.tm
.opcode_modifier
.ignoresize
4052 && !i
.tm
.opcode_modifier
.floatmf
4053 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4054 || (flag_code
== CODE_64BIT
4055 && i
.tm
.opcode_modifier
.jumpbyte
)))
4057 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4059 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4060 prefix
= ADDR_PREFIX_OPCODE
;
4062 if (!add_prefix (prefix
))
4066 /* Set mode64 for an operand. */
4067 if (i
.suffix
== QWORD_MNEM_SUFFIX
4068 && flag_code
== CODE_64BIT
4069 && !i
.tm
.opcode_modifier
.norex64
)
4071 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4072 need rex64. cmpxchg8b is also a special case. */
4073 if (! (i
.operands
== 2
4074 && i
.tm
.base_opcode
== 0x90
4075 && i
.tm
.extension_opcode
== None
4076 && operand_type_equal (&i
.types
[0], &acc64
)
4077 && operand_type_equal (&i
.types
[1], &acc64
))
4078 && ! (i
.operands
== 1
4079 && i
.tm
.base_opcode
== 0xfc7
4080 && i
.tm
.extension_opcode
== 1
4081 && !operand_type_check (i
.types
[0], reg
)
4082 && operand_type_check (i
.types
[0], anymem
)))
4086 /* Size floating point instruction. */
4087 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4088 if (i
.tm
.opcode_modifier
.floatmf
)
4089 i
.tm
.base_opcode
^= 4;
4096 check_byte_reg (void)
4100 for (op
= i
.operands
; --op
>= 0;)
4102 /* If this is an eight bit register, it's OK. If it's the 16 or
4103 32 bit version of an eight bit register, we will just use the
4104 low portion, and that's OK too. */
4105 if (i
.types
[op
].bitfield
.reg8
)
4108 /* Don't generate this warning if not needed. */
4109 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4112 /* crc32 doesn't generate this warning. */
4113 if (i
.tm
.base_opcode
== 0xf20f38f0)
4116 if ((i
.types
[op
].bitfield
.reg16
4117 || i
.types
[op
].bitfield
.reg32
4118 || i
.types
[op
].bitfield
.reg64
)
4119 && i
.op
[op
].regs
->reg_num
< 4)
4121 /* Prohibit these changes in the 64bit mode, since the
4122 lowering is more complicated. */
4123 if (flag_code
== CODE_64BIT
4124 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4126 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4127 register_prefix
, i
.op
[op
].regs
->reg_name
,
4131 #if REGISTER_WARNINGS
4133 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4134 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4136 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4137 ? REGNAM_AL
- REGNAM_AX
4138 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4140 i
.op
[op
].regs
->reg_name
,
4145 /* Any other register is bad. */
4146 if (i
.types
[op
].bitfield
.reg16
4147 || i
.types
[op
].bitfield
.reg32
4148 || i
.types
[op
].bitfield
.reg64
4149 || i
.types
[op
].bitfield
.regmmx
4150 || i
.types
[op
].bitfield
.regxmm
4151 || i
.types
[op
].bitfield
.regymm
4152 || i
.types
[op
].bitfield
.sreg2
4153 || i
.types
[op
].bitfield
.sreg3
4154 || i
.types
[op
].bitfield
.control
4155 || i
.types
[op
].bitfield
.debug
4156 || i
.types
[op
].bitfield
.test
4157 || i
.types
[op
].bitfield
.floatreg
4158 || i
.types
[op
].bitfield
.floatacc
)
4160 as_bad (_("`%s%s' not allowed with `%s%c'"),
4162 i
.op
[op
].regs
->reg_name
,
4172 check_long_reg (void)
4176 for (op
= i
.operands
; --op
>= 0;)
4177 /* Reject eight bit registers, except where the template requires
4178 them. (eg. movzb) */
4179 if (i
.types
[op
].bitfield
.reg8
4180 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4181 || i
.tm
.operand_types
[op
].bitfield
.reg32
4182 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4184 as_bad (_("`%s%s' not allowed with `%s%c'"),
4186 i
.op
[op
].regs
->reg_name
,
4191 /* Warn if the e prefix on a general reg is missing. */
4192 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4193 && i
.types
[op
].bitfield
.reg16
4194 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4195 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4197 /* Prohibit these changes in the 64bit mode, since the
4198 lowering is more complicated. */
4199 if (flag_code
== CODE_64BIT
)
4201 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4202 register_prefix
, i
.op
[op
].regs
->reg_name
,
4206 #if REGISTER_WARNINGS
4208 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4210 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4212 i
.op
[op
].regs
->reg_name
,
4216 /* Warn if the r prefix on a general reg is missing. */
4217 else if (i
.types
[op
].bitfield
.reg64
4218 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4219 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4222 && i
.tm
.opcode_modifier
.toqword
4223 && !i
.types
[0].bitfield
.regxmm
)
4225 /* Convert to QWORD. We want REX byte. */
4226 i
.suffix
= QWORD_MNEM_SUFFIX
;
4230 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4231 register_prefix
, i
.op
[op
].regs
->reg_name
,
4240 check_qword_reg (void)
4244 for (op
= i
.operands
; --op
>= 0; )
4245 /* Reject eight bit registers, except where the template requires
4246 them. (eg. movzb) */
4247 if (i
.types
[op
].bitfield
.reg8
4248 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4249 || i
.tm
.operand_types
[op
].bitfield
.reg32
4250 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4252 as_bad (_("`%s%s' not allowed with `%s%c'"),
4254 i
.op
[op
].regs
->reg_name
,
4259 /* Warn if the e prefix on a general reg is missing. */
4260 else if ((i
.types
[op
].bitfield
.reg16
4261 || i
.types
[op
].bitfield
.reg32
)
4262 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4263 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4265 /* Prohibit these changes in the 64bit mode, since the
4266 lowering is more complicated. */
4268 && i
.tm
.opcode_modifier
.todword
4269 && !i
.types
[0].bitfield
.regxmm
)
4271 /* Convert to DWORD. We don't want REX byte. */
4272 i
.suffix
= LONG_MNEM_SUFFIX
;
4276 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4277 register_prefix
, i
.op
[op
].regs
->reg_name
,
4286 check_word_reg (void)
4289 for (op
= i
.operands
; --op
>= 0;)
4290 /* Reject eight bit registers, except where the template requires
4291 them. (eg. movzb) */
4292 if (i
.types
[op
].bitfield
.reg8
4293 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4294 || i
.tm
.operand_types
[op
].bitfield
.reg32
4295 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4297 as_bad (_("`%s%s' not allowed with `%s%c'"),
4299 i
.op
[op
].regs
->reg_name
,
4304 /* Warn if the e prefix on a general reg is present. */
4305 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4306 && i
.types
[op
].bitfield
.reg32
4307 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4308 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4310 /* Prohibit these changes in the 64bit mode, since the
4311 lowering is more complicated. */
4312 if (flag_code
== CODE_64BIT
)
4314 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4315 register_prefix
, i
.op
[op
].regs
->reg_name
,
4320 #if REGISTER_WARNINGS
4321 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4323 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4325 i
.op
[op
].regs
->reg_name
,
4333 update_imm (unsigned int j
)
4335 i386_operand_type overlap
;
4337 overlap
= operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4338 if ((overlap
.bitfield
.imm8
4339 || overlap
.bitfield
.imm8s
4340 || overlap
.bitfield
.imm16
4341 || overlap
.bitfield
.imm32
4342 || overlap
.bitfield
.imm32s
4343 || overlap
.bitfield
.imm64
)
4344 && !operand_type_equal (&overlap
, &imm8
)
4345 && !operand_type_equal (&overlap
, &imm8s
)
4346 && !operand_type_equal (&overlap
, &imm16
)
4347 && !operand_type_equal (&overlap
, &imm32
)
4348 && !operand_type_equal (&overlap
, &imm32s
)
4349 && !operand_type_equal (&overlap
, &imm64
))
4353 i386_operand_type temp
;
4355 operand_type_set (&temp
, 0);
4356 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4358 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4359 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4361 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4362 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4363 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4365 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4366 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4369 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4372 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4373 || operand_type_equal (&overlap
, &imm16_32
)
4374 || operand_type_equal (&overlap
, &imm16_32s
))
4376 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4381 if (!operand_type_equal (&overlap
, &imm8
)
4382 && !operand_type_equal (&overlap
, &imm8s
)
4383 && !operand_type_equal (&overlap
, &imm16
)
4384 && !operand_type_equal (&overlap
, &imm32
)
4385 && !operand_type_equal (&overlap
, &imm32s
)
4386 && !operand_type_equal (&overlap
, &imm64
))
4388 as_bad (_("no instruction mnemonic suffix given; "
4389 "can't determine immediate size"));
4393 i
.types
[j
] = overlap
;
4403 for (j
= 0; j
< 2; j
++)
4404 if (update_imm (j
) == 0)
4407 i
.types
[2] = operand_type_and (i
.types
[2], i
.tm
.operand_types
[2]);
4408 assert (operand_type_check (i
.types
[2], imm
) == 0);
4416 i
.drex
.modrm_reg
= 0;
4417 i
.drex
.modrm_regmem
= 0;
4419 /* SSE5 4 operand instructions must have the destination the same as
4420 one of the inputs. Figure out the destination register and cache
4421 it away in the drex field, and remember which fields to use for
4423 if (i
.tm
.opcode_modifier
.drex
4424 && i
.tm
.opcode_modifier
.drexv
4427 i
.tm
.extension_opcode
= None
;
4429 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4430 if (i
.types
[0].bitfield
.regxmm
!= 0
4431 && i
.types
[1].bitfield
.regxmm
!= 0
4432 && i
.types
[2].bitfield
.regxmm
!= 0
4433 && i
.types
[3].bitfield
.regxmm
!= 0
4434 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4435 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4437 /* Clear the arguments that are stored in drex. */
4438 operand_type_set (&i
.types
[0], 0);
4439 operand_type_set (&i
.types
[3], 0);
4440 i
.reg_operands
-= 2;
4442 /* There are two different ways to encode a 4 operand
4443 instruction with all registers that uses OC1 set to
4444 0 or 1. Favor setting OC1 to 0 since this mimics the
4445 actions of other SSE5 assemblers. Use modrm encoding 2
4446 for register/register. Include the high order bit that
4447 is normally stored in the REX byte in the register
4449 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4450 i
.drex
.modrm_reg
= 2;
4451 i
.drex
.modrm_regmem
= 1;
4452 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4453 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4456 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4457 else if (i
.types
[0].bitfield
.regxmm
!= 0
4458 && i
.types
[1].bitfield
.regxmm
!= 0
4459 && (i
.types
[2].bitfield
.regxmm
4460 || operand_type_check (i
.types
[2], anymem
))
4461 && i
.types
[3].bitfield
.regxmm
!= 0
4462 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4463 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4465 /* clear the arguments that are stored in drex */
4466 operand_type_set (&i
.types
[0], 0);
4467 operand_type_set (&i
.types
[3], 0);
4468 i
.reg_operands
-= 2;
4470 /* Specify the modrm encoding for memory addressing. Include
4471 the high order bit that is normally stored in the REX byte
4472 in the register field. */
4473 i
.tm
.extension_opcode
= DREX_X1_X2_XMEM_X1
;
4474 i
.drex
.modrm_reg
= 1;
4475 i
.drex
.modrm_regmem
= 2;
4476 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4477 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4480 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4481 else if (i
.types
[0].bitfield
.regxmm
!= 0
4482 && operand_type_check (i
.types
[1], anymem
) != 0
4483 && i
.types
[2].bitfield
.regxmm
!= 0
4484 && i
.types
[3].bitfield
.regxmm
!= 0
4485 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4486 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4488 /* Clear the arguments that are stored in drex. */
4489 operand_type_set (&i
.types
[0], 0);
4490 operand_type_set (&i
.types
[3], 0);
4491 i
.reg_operands
-= 2;
4493 /* Specify the modrm encoding for memory addressing. Include
4494 the high order bit that is normally stored in the REX byte
4495 in the register field. */
4496 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4497 i
.drex
.modrm_reg
= 2;
4498 i
.drex
.modrm_regmem
= 1;
4499 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4500 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4503 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4504 else if (i
.types
[0].bitfield
.regxmm
!= 0
4505 && i
.types
[1].bitfield
.regxmm
!= 0
4506 && i
.types
[2].bitfield
.regxmm
!= 0
4507 && i
.types
[3].bitfield
.regxmm
!= 0
4508 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4509 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4511 /* clear the arguments that are stored in drex */
4512 operand_type_set (&i
.types
[2], 0);
4513 operand_type_set (&i
.types
[3], 0);
4514 i
.reg_operands
-= 2;
4516 /* There are two different ways to encode a 4 operand
4517 instruction with all registers that uses OC1 set to
4518 0 or 1. Favor setting OC1 to 0 since this mimics the
4519 actions of other SSE5 assemblers. Use modrm encoding
4520 2 for register/register. Include the high order bit that
4521 is normally stored in the REX byte in the register
4523 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4524 i
.drex
.modrm_reg
= 1;
4525 i
.drex
.modrm_regmem
= 0;
4527 /* Remember the register, including the upper bits */
4528 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4529 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4532 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4533 else if (i
.types
[0].bitfield
.regxmm
!= 0
4534 && (i
.types
[1].bitfield
.regxmm
4535 || operand_type_check (i
.types
[1], anymem
))
4536 && i
.types
[2].bitfield
.regxmm
!= 0
4537 && i
.types
[3].bitfield
.regxmm
!= 0
4538 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4539 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4541 /* Clear the arguments that are stored in drex. */
4542 operand_type_set (&i
.types
[2], 0);
4543 operand_type_set (&i
.types
[3], 0);
4544 i
.reg_operands
-= 2;
4546 /* Specify the modrm encoding and remember the register
4547 including the bits normally stored in the REX byte. */
4548 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X2
;
4549 i
.drex
.modrm_reg
= 0;
4550 i
.drex
.modrm_regmem
= 1;
4551 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4552 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4555 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4556 else if (operand_type_check (i
.types
[0], anymem
) != 0
4557 && i
.types
[1].bitfield
.regxmm
!= 0
4558 && i
.types
[2].bitfield
.regxmm
!= 0
4559 && i
.types
[3].bitfield
.regxmm
!= 0
4560 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4561 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4563 /* clear the arguments that are stored in drex */
4564 operand_type_set (&i
.types
[2], 0);
4565 operand_type_set (&i
.types
[3], 0);
4566 i
.reg_operands
-= 2;
4568 /* Specify the modrm encoding and remember the register
4569 including the bits normally stored in the REX byte. */
4570 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4571 i
.drex
.modrm_reg
= 1;
4572 i
.drex
.modrm_regmem
= 0;
4573 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4574 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4578 as_bad (_("Incorrect operands for the '%s' instruction"),
4582 /* SSE5 instructions with the DREX byte where the only memory operand
4583 is in the 2nd argument, and the first and last xmm register must
4584 match, and is encoded in the DREX byte. */
4585 else if (i
.tm
.opcode_modifier
.drex
4586 && !i
.tm
.opcode_modifier
.drexv
4589 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4590 if (i
.types
[0].bitfield
.regxmm
!= 0
4591 && (i
.types
[1].bitfield
.regxmm
4592 || operand_type_check(i
.types
[1], anymem
))
4593 && i
.types
[2].bitfield
.regxmm
!= 0
4594 && i
.types
[3].bitfield
.regxmm
!= 0
4595 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4596 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4598 /* clear the arguments that are stored in drex */
4599 operand_type_set (&i
.types
[0], 0);
4600 operand_type_set (&i
.types
[3], 0);
4601 i
.reg_operands
-= 2;
4603 /* Specify the modrm encoding and remember the register
4604 including the high bit normally stored in the REX
4606 i
.drex
.modrm_reg
= 2;
4607 i
.drex
.modrm_regmem
= 1;
4608 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4609 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4613 as_bad (_("Incorrect operands for the '%s' instruction"),
4617 /* SSE5 3 operand instructions that the result is a register, being
4618 either operand can be a memory operand, using OC0 to note which
4619 one is the memory. */
4620 else if (i
.tm
.opcode_modifier
.drex
4621 && i
.tm
.opcode_modifier
.drexv
4624 i
.tm
.extension_opcode
= None
;
4626 /* Case 1: 3 operand insn, src1 = register. */
4627 if (i
.types
[0].bitfield
.regxmm
!= 0
4628 && i
.types
[1].bitfield
.regxmm
!= 0
4629 && i
.types
[2].bitfield
.regxmm
!= 0)
4631 /* Clear the arguments that are stored in drex. */
4632 operand_type_set (&i
.types
[2], 0);
4635 /* Specify the modrm encoding and remember the register
4636 including the high bit normally stored in the REX byte. */
4637 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4638 i
.drex
.modrm_reg
= 1;
4639 i
.drex
.modrm_regmem
= 0;
4640 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4641 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4644 /* Case 2: 3 operand insn, src1 = memory. */
4645 else if (operand_type_check (i
.types
[0], anymem
) != 0
4646 && i
.types
[1].bitfield
.regxmm
!= 0
4647 && i
.types
[2].bitfield
.regxmm
!= 0)
4649 /* Clear the arguments that are stored in drex. */
4650 operand_type_set (&i
.types
[2], 0);
4653 /* Specify the modrm encoding and remember the register
4654 including the high bit normally stored in the REX
4656 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4657 i
.drex
.modrm_reg
= 1;
4658 i
.drex
.modrm_regmem
= 0;
4659 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4660 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4663 /* Case 3: 3 operand insn, src2 = memory. */
4664 else if (i
.types
[0].bitfield
.regxmm
!= 0
4665 && operand_type_check (i
.types
[1], anymem
) != 0
4666 && i
.types
[2].bitfield
.regxmm
!= 0)
4668 /* Clear the arguments that are stored in drex. */
4669 operand_type_set (&i
.types
[2], 0);
4672 /* Specify the modrm encoding and remember the register
4673 including the high bit normally stored in the REX byte. */
4674 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2
;
4675 i
.drex
.modrm_reg
= 0;
4676 i
.drex
.modrm_regmem
= 1;
4677 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4678 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4682 as_bad (_("Incorrect operands for the '%s' instruction"),
4686 /* SSE5 4 operand instructions that are the comparison instructions
4687 where the first operand is the immediate value of the comparison
4689 else if (i
.tm
.opcode_modifier
.drexc
!= 0 && i
.operands
== 4)
4691 /* Case 1: 4 operand insn, src1 = reg/memory. */
4692 if (operand_type_check (i
.types
[0], imm
) != 0
4693 && (i
.types
[1].bitfield
.regxmm
4694 || operand_type_check (i
.types
[1], anymem
))
4695 && i
.types
[2].bitfield
.regxmm
!= 0
4696 && i
.types
[3].bitfield
.regxmm
!= 0)
4698 /* clear the arguments that are stored in drex */
4699 operand_type_set (&i
.types
[3], 0);
4702 /* Specify the modrm encoding and remember the register
4703 including the high bit normally stored in the REX byte. */
4704 i
.drex
.modrm_reg
= 2;
4705 i
.drex
.modrm_regmem
= 1;
4706 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4707 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4710 /* Case 2: 3 operand insn with ImmExt that places the
4711 opcode_extension as an immediate argument. This is used for
4712 all of the varients of comparison that supplies the appropriate
4713 value as part of the instruction. */
4714 else if ((i
.types
[0].bitfield
.regxmm
4715 || operand_type_check (i
.types
[0], anymem
))
4716 && i
.types
[1].bitfield
.regxmm
!= 0
4717 && i
.types
[2].bitfield
.regxmm
!= 0
4718 && operand_type_check (i
.types
[3], imm
) != 0)
4720 /* clear the arguments that are stored in drex */
4721 operand_type_set (&i
.types
[2], 0);
4724 /* Specify the modrm encoding and remember the register
4725 including the high bit normally stored in the REX byte. */
4726 i
.drex
.modrm_reg
= 1;
4727 i
.drex
.modrm_regmem
= 0;
4728 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4729 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4733 as_bad (_("Incorrect operands for the '%s' instruction"),
4737 else if (i
.tm
.opcode_modifier
.drex
4738 || i
.tm
.opcode_modifier
.drexv
4739 || i
.tm
.opcode_modifier
.drexc
)
4740 as_bad (_("Internal error for the '%s' instruction"), i
.tm
.name
);
4744 bad_implicit_operand (int xmm
)
4746 const char *reg
= xmm
? "xmm0" : "ymm0";
4748 as_bad (_("the last operand of `%s' must be `%s%s'"),
4749 i
.tm
.name
, register_prefix
, reg
);
4751 as_bad (_("the first operand of `%s' must be `%s%s'"),
4752 i
.tm
.name
, register_prefix
, reg
);
4757 process_operands (void)
4759 /* Default segment register this instruction will use for memory
4760 accesses. 0 means unknown. This is only for optimizing out
4761 unnecessary segment overrides. */
4762 const seg_entry
*default_seg
= 0;
4764 /* Handle all of the DREX munging that SSE5 needs. */
4765 if (i
.tm
.opcode_modifier
.drex
4766 || i
.tm
.opcode_modifier
.drexv
4767 || i
.tm
.opcode_modifier
.drexc
)
4770 if (i
.tm
.opcode_modifier
.sse2avx
4771 && (i
.tm
.opcode_modifier
.vexnds
4772 || i
.tm
.opcode_modifier
.vexndd
))
4774 unsigned int dup
= i
.operands
;
4775 unsigned int dest
= dup
- 1;
4778 /* The destination must be an xmm register. */
4779 assert (i
.reg_operands
4780 && MAX_OPERANDS
> dup
4781 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4783 if (i
.tm
.opcode_modifier
.firstxmm0
)
4785 /* The first operand is implicit and must be xmm0. */
4786 assert (operand_type_equal (&i
.types
[0], ®xmm
));
4787 if (i
.op
[0].regs
->reg_num
!= 0)
4788 return bad_implicit_operand (1);
4790 if (i
.tm
.opcode_modifier
.vex3sources
)
4792 /* Keep xmm0 for instructions with VEX prefix and 3
4798 /* We remove the first xmm0 and keep the number of
4799 operands unchanged, which in fact duplicates the
4801 for (j
= 1; j
< i
.operands
; j
++)
4803 i
.op
[j
- 1] = i
.op
[j
];
4804 i
.types
[j
- 1] = i
.types
[j
];
4805 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4809 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4811 assert ((MAX_OPERANDS
- 1) > dup
4812 && i
.tm
.opcode_modifier
.vex3sources
);
4814 /* Add the implicit xmm0 for instructions with VEX prefix
4816 for (j
= i
.operands
; j
> 0; j
--)
4818 i
.op
[j
] = i
.op
[j
- 1];
4819 i
.types
[j
] = i
.types
[j
- 1];
4820 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4823 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4824 i
.types
[0] = regxmm
;
4825 i
.tm
.operand_types
[0] = regxmm
;
4828 i
.reg_operands
+= 2;
4833 i
.op
[dup
] = i
.op
[dest
];
4834 i
.types
[dup
] = i
.types
[dest
];
4835 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4844 i
.op
[dup
] = i
.op
[dest
];
4845 i
.types
[dup
] = i
.types
[dest
];
4846 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4849 if (i
.tm
.opcode_modifier
.immext
)
4852 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4856 /* The first operand is implicit and must be xmm0/ymm0. */
4857 assert (i
.reg_operands
4858 && (operand_type_equal (&i
.types
[0], ®xmm
)
4859 || operand_type_equal (&i
.types
[0], ®ymm
)));
4860 if (i
.op
[0].regs
->reg_num
!= 0)
4861 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4863 for (j
= 1; j
< i
.operands
; j
++)
4865 i
.op
[j
- 1] = i
.op
[j
];
4866 i
.types
[j
- 1] = i
.types
[j
];
4868 /* We need to adjust fields in i.tm since they are used by
4869 build_modrm_byte. */
4870 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4877 else if (i
.tm
.opcode_modifier
.regkludge
)
4879 /* The imul $imm, %reg instruction is converted into
4880 imul $imm, %reg, %reg, and the clr %reg instruction
4881 is converted into xor %reg, %reg. */
4883 unsigned int first_reg_op
;
4885 if (operand_type_check (i
.types
[0], reg
))
4889 /* Pretend we saw the extra register operand. */
4890 assert (i
.reg_operands
== 1
4891 && i
.op
[first_reg_op
+ 1].regs
== 0);
4892 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4893 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4898 if (i
.tm
.opcode_modifier
.shortform
)
4900 if (i
.types
[0].bitfield
.sreg2
4901 || i
.types
[0].bitfield
.sreg3
)
4903 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4904 && i
.op
[0].regs
->reg_num
== 1)
4906 as_bad (_("you can't `pop %%cs'"));
4909 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4910 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4915 /* The register or float register operand is in operand
4919 if (i
.types
[0].bitfield
.floatreg
4920 || operand_type_check (i
.types
[0], reg
))
4924 /* Register goes in low 3 bits of opcode. */
4925 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4926 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4928 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4930 /* Warn about some common errors, but press on regardless.
4931 The first case can be generated by gcc (<= 2.8.1). */
4932 if (i
.operands
== 2)
4934 /* Reversed arguments on faddp, fsubp, etc. */
4935 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4936 register_prefix
, i
.op
[1].regs
->reg_name
,
4937 register_prefix
, i
.op
[0].regs
->reg_name
);
4941 /* Extraneous `l' suffix on fp insn. */
4942 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4943 register_prefix
, i
.op
[0].regs
->reg_name
);
4948 else if (i
.tm
.opcode_modifier
.modrm
)
4950 /* The opcode is completed (modulo i.tm.extension_opcode which
4951 must be put into the modrm byte). Now, we make the modrm and
4952 index base bytes based on all the info we've collected. */
4954 default_seg
= build_modrm_byte ();
4956 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4960 else if (i
.tm
.opcode_modifier
.isstring
)
4962 /* For the string instructions that allow a segment override
4963 on one of their operands, the default segment is ds. */
4967 if (i
.tm
.base_opcode
== 0x8d /* lea */
4970 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
4972 /* If a segment was explicitly specified, and the specified segment
4973 is not the default, use an opcode prefix to select it. If we
4974 never figured out what the default segment is, then default_seg
4975 will be zero at this point, and the specified segment prefix will
4977 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4979 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4985 static const seg_entry
*
4986 build_modrm_byte (void)
4988 const seg_entry
*default_seg
= 0;
4989 unsigned int source
, dest
;
4992 /* The first operand of instructions with VEX prefix and 3 sources
4993 must be VEX_Imm4. */
4994 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
4997 unsigned int nds
, reg
;
4999 if (i
.tm
.opcode_modifier
.veximmext
5000 && i
.tm
.opcode_modifier
.immext
)
5002 dest
= i
.operands
- 2;
5006 dest
= i
.operands
- 1;
5009 /* There are 2 kinds of instructions:
5010 1. 5 operands: one immediate operand and 4 register
5011 operands or 3 register operands plus 1 memory operand.
5012 It must have VexNDS and VexW0 or VexW1. The destination
5013 must be either XMM or YMM register.
5014 2. 4 operands: 4 register operands or 3 register operands
5015 plus 1 memory operand. It must have VexNDS and VexImmExt. */
5016 if (!((i
.reg_operands
== 4
5017 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5018 && i
.tm
.opcode_modifier
.vexnds
5019 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5020 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
))
5022 && i
.imm_operands
== 1
5023 && i
.types
[0].bitfield
.vex_imm4
5024 && (i
.tm
.opcode_modifier
.vexw0
5025 || i
.tm
.opcode_modifier
.vexw1
))
5027 && (i
.imm_operands
== 0
5028 || (i
.imm_operands
== 1
5029 && i
.tm
.opcode_modifier
.immext
))
5030 && i
.tm
.opcode_modifier
.veximmext
))))
5033 if (i
.imm_operands
== 0)
5035 /* When there is no immediate operand, generate an 8bit
5036 immediate operand to encode the first operand. */
5037 expressionS
*exp
= &im_expressions
[i
.imm_operands
++];
5038 i
.op
[i
.operands
].imms
= exp
;
5039 i
.types
[i
.operands
] = imm8
;
5041 /* If VexW1 is set, the first operand is the source and
5042 the second operand is encoded in the immediate operand. */
5043 if (i
.tm
.opcode_modifier
.vexw1
)
5054 /* FMA swaps REG and NDS. */
5055 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5063 assert (operand_type_equal (&i
.tm
.operand_types
[reg
], ®xmm
)
5064 || operand_type_equal (&i
.tm
.operand_types
[reg
],
5066 exp
->X_op
= O_constant
;
5068 = ((i
.op
[reg
].regs
->reg_num
5069 + ((i
.op
[reg
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
5075 if (i
.tm
.opcode_modifier
.vexw0
)
5077 /* If VexW0 is set, the third operand is the source and
5078 the second operand is encoded in the immediate
5085 /* VexW1 is set, the second operand is the source and
5086 the third operand is encoded in the immediate
5092 if (i
.tm
.opcode_modifier
.immext
)
5094 /* When ImmExt is set, the immdiate byte is the last
5096 imm
= i
.operands
- 1;
5104 /* Turn on Imm8 so that output_imm will generate it. */
5105 i
.types
[imm
].bitfield
.imm8
= 1;
5108 assert (operand_type_equal (&i
.tm
.operand_types
[reg
], ®xmm
)
5109 || operand_type_equal (&i
.tm
.operand_types
[reg
],
5111 i
.op
[imm
].imms
->X_add_number
5112 |= ((i
.op
[reg
].regs
->reg_num
5113 + ((i
.op
[reg
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
5116 assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
5117 || operand_type_equal (&i
.tm
.operand_types
[nds
], ®ymm
));
5118 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5124 /* SSE5 4 operand instructions are encoded in such a way that one of
5125 the inputs must match the destination register. Process_drex hides
5126 the 3rd argument in the drex field, so that by the time we get
5127 here, it looks to GAS as if this is a 2 operand instruction. */
5128 if ((i
.tm
.opcode_modifier
.drex
5129 || i
.tm
.opcode_modifier
.drexv
5130 || i
.tm
.opcode_modifier
.drexc
)
5131 && i
.reg_operands
== 2)
5133 const reg_entry
*reg
= i
.op
[i
.drex
.modrm_reg
].regs
;
5134 const reg_entry
*regmem
= i
.op
[i
.drex
.modrm_regmem
].regs
;
5136 i
.rm
.reg
= reg
->reg_num
;
5137 i
.rm
.regmem
= regmem
->reg_num
;
5139 if ((reg
->reg_flags
& RegRex
) != 0)
5141 if ((regmem
->reg_flags
& RegRex
) != 0)
5145 /* i.reg_operands MUST be the number of real register operands;
5146 implicit registers do not count. If there are 3 register
5147 operands, it must be a instruction with VexNDS. For a
5148 instruction with VexNDD, the destination register is encoded
5149 in VEX prefix. If there are 4 register operands, it must be
5150 a instruction with VEX prefix and 3 sources. */
5151 else if (i
.mem_operands
== 0
5152 && ((i
.reg_operands
== 2
5153 && !i
.tm
.opcode_modifier
.vexndd
)
5154 || (i
.reg_operands
== 3
5155 && i
.tm
.opcode_modifier
.vexnds
)
5156 || (i
.reg_operands
== 4 && vex_3_sources
)))
5164 /* When there are 3 operands, one of them may be immediate,
5165 which may be the first or the last operand. Otherwise,
5166 the first operand must be shift count register (cl) or it
5167 is an instruction with VexNDS. */
5168 assert (i
.imm_operands
== 1
5169 || (i
.imm_operands
== 0
5170 && (i
.tm
.opcode_modifier
.vexnds
5171 || i
.types
[0].bitfield
.shiftcount
)));
5172 if (operand_type_check (i
.types
[0], imm
)
5173 || i
.types
[0].bitfield
.shiftcount
)
5179 /* When there are 4 operands, the first two must be 8bit
5180 immediate operands. The source operand will be the 3rd
5183 For instructions with VexNDS, if the first operand
5184 an imm8, the source operand is the 2nd one. If the last
5185 operand is imm8, the source operand is the first one. */
5186 assert ((i
.imm_operands
== 2
5187 && i
.types
[0].bitfield
.imm8
5188 && i
.types
[1].bitfield
.imm8
)
5189 || (i
.tm
.opcode_modifier
.vexnds
5190 && i
.imm_operands
== 1
5191 && (i
.types
[0].bitfield
.imm8
5192 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5193 if (i
.tm
.opcode_modifier
.vexnds
)
5195 if (i
.types
[0].bitfield
.imm8
)
5213 if (i
.tm
.opcode_modifier
.vexnds
)
5215 /* For instructions with VexNDS, the register-only
5216 source operand must be XMM or YMM register. It is
5217 encoded in VEX prefix. */
5218 if ((dest
+ 1) >= i
.operands
5219 || (!operand_type_equal (&i
.tm
.operand_types
[dest
],
5221 && !operand_type_equal (&i
.tm
.operand_types
[dest
],
5224 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5230 /* One of the register operands will be encoded in the i.tm.reg
5231 field, the other in the combined i.tm.mode and i.tm.regmem
5232 fields. If no form of this instruction supports a memory
5233 destination operand, then we assume the source operand may
5234 sometimes be a memory operand and so we need to store the
5235 destination in the i.rm.reg field. */
5236 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5237 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5239 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5240 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5241 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5243 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5248 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5249 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5250 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5252 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5255 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5257 if (!i
.types
[0].bitfield
.control
5258 && !i
.types
[1].bitfield
.control
)
5260 i
.rex
&= ~(REX_R
| REX_B
);
5261 add_prefix (LOCK_PREFIX_OPCODE
);
5265 { /* If it's not 2 reg operands... */
5270 unsigned int fake_zero_displacement
= 0;
5273 /* This has been precalculated for SSE5 instructions
5274 that have a DREX field earlier in process_drex. */
5275 if (i
.tm
.opcode_modifier
.drex
5276 || i
.tm
.opcode_modifier
.drexv
5277 || i
.tm
.opcode_modifier
.drexc
)
5278 op
= i
.drex
.modrm_regmem
;
5281 for (op
= 0; op
< i
.operands
; op
++)
5282 if (operand_type_check (i
.types
[op
], anymem
))
5284 assert (op
< i
.operands
);
5289 if (i
.base_reg
== 0)
5292 if (!i
.disp_operands
)
5293 fake_zero_displacement
= 1;
5294 if (i
.index_reg
== 0)
5296 /* Operand is just <disp> */
5297 if (flag_code
== CODE_64BIT
)
5299 /* 64bit mode overwrites the 32bit absolute
5300 addressing by RIP relative addressing and
5301 absolute addressing is encoded by one of the
5302 redundant SIB forms. */
5303 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5304 i
.sib
.base
= NO_BASE_REGISTER
;
5305 i
.sib
.index
= NO_INDEX_REGISTER
;
5306 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5307 ? disp32s
: disp32
);
5309 else if ((flag_code
== CODE_16BIT
)
5310 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5312 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5313 i
.types
[op
] = disp16
;
5317 i
.rm
.regmem
= NO_BASE_REGISTER
;
5318 i
.types
[op
] = disp32
;
5321 else /* !i.base_reg && i.index_reg */
5323 if (i
.index_reg
->reg_num
== RegEiz
5324 || i
.index_reg
->reg_num
== RegRiz
)
5325 i
.sib
.index
= NO_INDEX_REGISTER
;
5327 i
.sib
.index
= i
.index_reg
->reg_num
;
5328 i
.sib
.base
= NO_BASE_REGISTER
;
5329 i
.sib
.scale
= i
.log2_scale_factor
;
5330 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5331 i
.types
[op
].bitfield
.disp8
= 0;
5332 i
.types
[op
].bitfield
.disp16
= 0;
5333 i
.types
[op
].bitfield
.disp64
= 0;
5334 if (flag_code
!= CODE_64BIT
)
5336 /* Must be 32 bit */
5337 i
.types
[op
].bitfield
.disp32
= 1;
5338 i
.types
[op
].bitfield
.disp32s
= 0;
5342 i
.types
[op
].bitfield
.disp32
= 0;
5343 i
.types
[op
].bitfield
.disp32s
= 1;
5345 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5349 /* RIP addressing for 64bit mode. */
5350 else if (i
.base_reg
->reg_num
== RegRip
||
5351 i
.base_reg
->reg_num
== RegEip
)
5353 i
.rm
.regmem
= NO_BASE_REGISTER
;
5354 i
.types
[op
].bitfield
.disp8
= 0;
5355 i
.types
[op
].bitfield
.disp16
= 0;
5356 i
.types
[op
].bitfield
.disp32
= 0;
5357 i
.types
[op
].bitfield
.disp32s
= 1;
5358 i
.types
[op
].bitfield
.disp64
= 0;
5359 i
.flags
[op
] |= Operand_PCrel
;
5360 if (! i
.disp_operands
)
5361 fake_zero_displacement
= 1;
5363 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5365 switch (i
.base_reg
->reg_num
)
5368 if (i
.index_reg
== 0)
5370 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5371 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5375 if (i
.index_reg
== 0)
5378 if (operand_type_check (i
.types
[op
], disp
) == 0)
5380 /* fake (%bp) into 0(%bp) */
5381 i
.types
[op
].bitfield
.disp8
= 1;
5382 fake_zero_displacement
= 1;
5385 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5386 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5388 default: /* (%si) -> 4 or (%di) -> 5 */
5389 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5391 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5393 else /* i.base_reg and 32/64 bit mode */
5395 if (flag_code
== CODE_64BIT
5396 && operand_type_check (i
.types
[op
], disp
))
5398 i386_operand_type temp
;
5399 operand_type_set (&temp
, 0);
5400 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5402 if (i
.prefix
[ADDR_PREFIX
] == 0)
5403 i
.types
[op
].bitfield
.disp32s
= 1;
5405 i
.types
[op
].bitfield
.disp32
= 1;
5408 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5409 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5411 i
.sib
.base
= i
.base_reg
->reg_num
;
5412 /* x86-64 ignores REX prefix bit here to avoid decoder
5414 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5417 if (i
.disp_operands
== 0)
5419 fake_zero_displacement
= 1;
5420 i
.types
[op
].bitfield
.disp8
= 1;
5423 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5427 i
.sib
.scale
= i
.log2_scale_factor
;
5428 if (i
.index_reg
== 0)
5430 /* <disp>(%esp) becomes two byte modrm with no index
5431 register. We've already stored the code for esp
5432 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5433 Any base register besides %esp will not use the
5434 extra modrm byte. */
5435 i
.sib
.index
= NO_INDEX_REGISTER
;
5439 if (i
.index_reg
->reg_num
== RegEiz
5440 || i
.index_reg
->reg_num
== RegRiz
)
5441 i
.sib
.index
= NO_INDEX_REGISTER
;
5443 i
.sib
.index
= i
.index_reg
->reg_num
;
5444 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5445 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5450 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5451 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5454 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5457 if (fake_zero_displacement
)
5459 /* Fakes a zero displacement assuming that i.types[op]
5460 holds the correct displacement size. */
5463 assert (i
.op
[op
].disps
== 0);
5464 exp
= &disp_expressions
[i
.disp_operands
++];
5465 i
.op
[op
].disps
= exp
;
5466 exp
->X_op
= O_constant
;
5467 exp
->X_add_number
= 0;
5468 exp
->X_add_symbol
= (symbolS
*) 0;
5469 exp
->X_op_symbol
= (symbolS
*) 0;
5477 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5478 (if any) based on i.tm.extension_opcode. Again, we must be
5479 careful to make sure that segment/control/debug/test/MMX
5480 registers are coded into the i.rm.reg field. */
5485 /* This has been precalculated for SSE5 instructions
5486 that have a DREX field earlier in process_drex. */
5487 if (i
.tm
.opcode_modifier
.drex
5488 || i
.tm
.opcode_modifier
.drexv
5489 || i
.tm
.opcode_modifier
.drexc
)
5491 op
= i
.drex
.modrm_reg
;
5492 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5493 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5498 unsigned int vex_reg
= ~0;
5500 for (op
= 0; op
< i
.operands
; op
++)
5501 if (i
.types
[op
].bitfield
.reg8
5502 || i
.types
[op
].bitfield
.reg16
5503 || i
.types
[op
].bitfield
.reg32
5504 || i
.types
[op
].bitfield
.reg64
5505 || i
.types
[op
].bitfield
.regmmx
5506 || i
.types
[op
].bitfield
.regxmm
5507 || i
.types
[op
].bitfield
.regymm
5508 || i
.types
[op
].bitfield
.sreg2
5509 || i
.types
[op
].bitfield
.sreg3
5510 || i
.types
[op
].bitfield
.control
5511 || i
.types
[op
].bitfield
.debug
5512 || i
.types
[op
].bitfield
.test
)
5517 else if (i
.tm
.opcode_modifier
.vexnds
)
5519 /* For instructions with VexNDS, the register-only
5520 source operand is encoded in VEX prefix. */
5521 assert (mem
!= (unsigned int) ~0);
5526 assert (op
< i
.operands
);
5531 assert (vex_reg
< i
.operands
);
5534 else if (i
.tm
.opcode_modifier
.vexndd
)
5536 /* For instructions with VexNDD, there should be
5537 no memory operand and the register destination
5538 is encoded in VEX prefix. */
5539 assert (i
.mem_operands
== 0
5540 && (op
+ 2) == i
.operands
);
5544 assert (op
< i
.operands
);
5546 if (vex_reg
!= (unsigned int) ~0)
5548 assert (i
.reg_operands
== 2);
5550 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5552 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5555 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5558 /* If there is an extension opcode to put here, the
5559 register number must be put into the regmem field. */
5560 if (i
.tm
.extension_opcode
!= None
)
5562 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5563 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5568 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5569 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5574 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5575 must set it to 3 to indicate this is a register operand
5576 in the regmem field. */
5577 if (!i
.mem_operands
)
5581 /* Fill in i.rm.reg field with extension opcode (if any). */
5582 if (i
.tm
.extension_opcode
!= None
5583 && !(i
.tm
.opcode_modifier
.drex
5584 || i
.tm
.opcode_modifier
.drexv
5585 || i
.tm
.opcode_modifier
.drexc
))
5586 i
.rm
.reg
= i
.tm
.extension_opcode
;
5592 output_branch (void)
5597 relax_substateT subtype
;
5602 if (flag_code
== CODE_16BIT
)
5606 if (i
.prefix
[DATA_PREFIX
] != 0)
5612 /* Pentium4 branch hints. */
5613 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5614 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5619 if (i
.prefix
[REX_PREFIX
] != 0)
5625 if (i
.prefixes
!= 0 && !intel_syntax
)
5626 as_warn (_("skipping prefixes on this instruction"));
5628 /* It's always a symbol; End frag & setup for relax.
5629 Make sure there is enough room in this frag for the largest
5630 instruction we may generate in md_convert_frag. This is 2
5631 bytes for the opcode and room for the prefix and largest
5633 frag_grow (prefix
+ 2 + 4);
5634 /* Prefix and 1 opcode byte go in fr_fix. */
5635 p
= frag_more (prefix
+ 1);
5636 if (i
.prefix
[DATA_PREFIX
] != 0)
5637 *p
++ = DATA_PREFIX_OPCODE
;
5638 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5639 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5640 *p
++ = i
.prefix
[SEG_PREFIX
];
5641 if (i
.prefix
[REX_PREFIX
] != 0)
5642 *p
++ = i
.prefix
[REX_PREFIX
];
5643 *p
= i
.tm
.base_opcode
;
5645 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5646 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5647 else if (cpu_arch_flags
.bitfield
.cpui386
)
5648 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5650 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5653 sym
= i
.op
[0].disps
->X_add_symbol
;
5654 off
= i
.op
[0].disps
->X_add_number
;
5656 if (i
.op
[0].disps
->X_op
!= O_constant
5657 && i
.op
[0].disps
->X_op
!= O_symbol
)
5659 /* Handle complex expressions. */
5660 sym
= make_expr_symbol (i
.op
[0].disps
);
5664 /* 1 possible extra opcode + 4 byte displacement go in var part.
5665 Pass reloc in fr_var. */
5666 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5676 if (i
.tm
.opcode_modifier
.jumpbyte
)
5678 /* This is a loop or jecxz type instruction. */
5680 if (i
.prefix
[ADDR_PREFIX
] != 0)
5682 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5685 /* Pentium4 branch hints. */
5686 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5687 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5689 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5698 if (flag_code
== CODE_16BIT
)
5701 if (i
.prefix
[DATA_PREFIX
] != 0)
5703 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5713 if (i
.prefix
[REX_PREFIX
] != 0)
5715 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5719 if (i
.prefixes
!= 0 && !intel_syntax
)
5720 as_warn (_("skipping prefixes on this instruction"));
5722 p
= frag_more (1 + size
);
5723 *p
++ = i
.tm
.base_opcode
;
5725 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5726 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5728 /* All jumps handled here are signed, but don't use a signed limit
5729 check for 32 and 16 bit jumps as we want to allow wrap around at
5730 4G and 64k respectively. */
5732 fixP
->fx_signed
= 1;
5736 output_interseg_jump (void)
5744 if (flag_code
== CODE_16BIT
)
5748 if (i
.prefix
[DATA_PREFIX
] != 0)
5754 if (i
.prefix
[REX_PREFIX
] != 0)
5764 if (i
.prefixes
!= 0 && !intel_syntax
)
5765 as_warn (_("skipping prefixes on this instruction"));
5767 /* 1 opcode; 2 segment; offset */
5768 p
= frag_more (prefix
+ 1 + 2 + size
);
5770 if (i
.prefix
[DATA_PREFIX
] != 0)
5771 *p
++ = DATA_PREFIX_OPCODE
;
5773 if (i
.prefix
[REX_PREFIX
] != 0)
5774 *p
++ = i
.prefix
[REX_PREFIX
];
5776 *p
++ = i
.tm
.base_opcode
;
5777 if (i
.op
[1].imms
->X_op
== O_constant
)
5779 offsetT n
= i
.op
[1].imms
->X_add_number
;
5782 && !fits_in_unsigned_word (n
)
5783 && !fits_in_signed_word (n
))
5785 as_bad (_("16-bit jump out of range"));
5788 md_number_to_chars (p
, n
, size
);
5791 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5792 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5793 if (i
.op
[0].imms
->X_op
!= O_constant
)
5794 as_bad (_("can't handle non absolute segment in `%s'"),
5796 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5802 fragS
*insn_start_frag
;
5803 offsetT insn_start_off
;
5805 /* Tie dwarf2 debug info to the address at the start of the insn.
5806 We can't do this after the insn has been output as the current
5807 frag may have been closed off. eg. by frag_var. */
5808 dwarf2_emit_insn (0);
5810 insn_start_frag
= frag_now
;
5811 insn_start_off
= frag_now_fix ();
5814 if (i
.tm
.opcode_modifier
.jump
)
5816 else if (i
.tm
.opcode_modifier
.jumpbyte
5817 || i
.tm
.opcode_modifier
.jumpdword
)
5819 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5820 output_interseg_jump ();
5823 /* Output normal instructions here. */
5827 unsigned int prefix
;
5829 /* Since the VEX prefix contains the implicit prefix, we don't
5830 need the explicit prefix. */
5831 if (!i
.tm
.opcode_modifier
.vex
)
5833 switch (i
.tm
.opcode_length
)
5836 if (i
.tm
.base_opcode
& 0xff000000)
5838 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5843 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5845 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5846 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5849 if (prefix
!= REPE_PREFIX_OPCODE
5850 || (i
.prefix
[LOCKREP_PREFIX
]
5851 != REPE_PREFIX_OPCODE
))
5852 add_prefix (prefix
);
5855 add_prefix (prefix
);
5864 /* The prefix bytes. */
5865 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5867 FRAG_APPEND_1_CHAR (*q
);
5870 if (i
.tm
.opcode_modifier
.vex
)
5872 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5877 /* REX byte is encoded in VEX prefix. */
5881 FRAG_APPEND_1_CHAR (*q
);
5884 /* There should be no other prefixes for instructions
5889 /* Now the VEX prefix. */
5890 p
= frag_more (i
.vex
.length
);
5891 for (j
= 0; j
< i
.vex
.length
; j
++)
5892 p
[j
] = i
.vex
.bytes
[j
];
5895 /* Now the opcode; be careful about word order here! */
5896 if (i
.tm
.opcode_length
== 1)
5898 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5902 switch (i
.tm
.opcode_length
)
5906 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5916 /* Put out high byte first: can't use md_number_to_chars! */
5917 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5918 *p
= i
.tm
.base_opcode
& 0xff;
5920 /* On SSE5, encode the OC1 bit in the DREX field if this
5921 encoding has multiple formats. */
5922 if (i
.tm
.opcode_modifier
.drex
5923 && i
.tm
.opcode_modifier
.drexv
5924 && DREX_OC1 (i
.tm
.extension_opcode
))
5925 *p
|= DREX_OC1_MASK
;
5928 /* Now the modrm byte and sib byte (if present). */
5929 if (i
.tm
.opcode_modifier
.modrm
)
5931 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5934 /* If i.rm.regmem == ESP (4)
5935 && i.rm.mode != (Register mode)
5937 ==> need second modrm byte. */
5938 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5940 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5941 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5943 | i
.sib
.scale
<< 6));
5946 /* Write the DREX byte if needed. */
5947 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
5950 *p
= (((i
.drex
.reg
& 0xf) << 4) | (i
.drex
.rex
& 0x7));
5952 /* Encode the OC0 bit if this encoding has multiple
5954 if ((i
.tm
.opcode_modifier
.drex
5955 || i
.tm
.opcode_modifier
.drexv
)
5956 && DREX_OC0 (i
.tm
.extension_opcode
))
5957 *p
|= DREX_OC0_MASK
;
5960 if (i
.disp_operands
)
5961 output_disp (insn_start_frag
, insn_start_off
);
5964 output_imm (insn_start_frag
, insn_start_off
);
5970 pi ("" /*line*/, &i
);
5972 #endif /* DEBUG386 */
5975 /* Return the size of the displacement operand N. */
5978 disp_size (unsigned int n
)
5981 if (i
.types
[n
].bitfield
.disp64
)
5983 else if (i
.types
[n
].bitfield
.disp8
)
5985 else if (i
.types
[n
].bitfield
.disp16
)
5990 /* Return the size of the immediate operand N. */
5993 imm_size (unsigned int n
)
5996 if (i
.types
[n
].bitfield
.imm64
)
5998 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6000 else if (i
.types
[n
].bitfield
.imm16
)
6006 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6011 for (n
= 0; n
< i
.operands
; n
++)
6013 if (operand_type_check (i
.types
[n
], disp
))
6015 if (i
.op
[n
].disps
->X_op
== O_constant
)
6017 int size
= disp_size (n
);
6020 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6022 p
= frag_more (size
);
6023 md_number_to_chars (p
, val
, size
);
6027 enum bfd_reloc_code_real reloc_type
;
6028 int size
= disp_size (n
);
6029 int sign
= i
.types
[n
].bitfield
.disp32s
;
6030 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6032 /* We can't have 8 bit displacement here. */
6033 assert (!i
.types
[n
].bitfield
.disp8
);
6035 /* The PC relative address is computed relative
6036 to the instruction boundary, so in case immediate
6037 fields follows, we need to adjust the value. */
6038 if (pcrel
&& i
.imm_operands
)
6043 for (n1
= 0; n1
< i
.operands
; n1
++)
6044 if (operand_type_check (i
.types
[n1
], imm
))
6046 /* Only one immediate is allowed for PC
6047 relative address. */
6050 i
.op
[n
].disps
->X_add_number
-= sz
;
6052 /* We should find the immediate. */
6056 p
= frag_more (size
);
6057 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6059 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6060 && (((reloc_type
== BFD_RELOC_32
6061 || reloc_type
== BFD_RELOC_X86_64_32S
6062 || (reloc_type
== BFD_RELOC_64
6064 && (i
.op
[n
].disps
->X_op
== O_symbol
6065 || (i
.op
[n
].disps
->X_op
== O_add
6066 && ((symbol_get_value_expression
6067 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6069 || reloc_type
== BFD_RELOC_32_PCREL
))
6073 if (insn_start_frag
== frag_now
)
6074 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6079 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6080 for (fr
= insn_start_frag
->fr_next
;
6081 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6083 add
+= p
- frag_now
->fr_literal
;
6088 reloc_type
= BFD_RELOC_386_GOTPC
;
6089 i
.op
[n
].imms
->X_add_number
+= add
;
6091 else if (reloc_type
== BFD_RELOC_64
)
6092 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6094 /* Don't do the adjustment for x86-64, as there
6095 the pcrel addressing is relative to the _next_
6096 insn, and that is taken care of in other code. */
6097 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6099 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6100 i
.op
[n
].disps
, pcrel
, reloc_type
);
6107 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6112 for (n
= 0; n
< i
.operands
; n
++)
6114 if (operand_type_check (i
.types
[n
], imm
))
6116 if (i
.op
[n
].imms
->X_op
== O_constant
)
6118 int size
= imm_size (n
);
6121 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6123 p
= frag_more (size
);
6124 md_number_to_chars (p
, val
, size
);
6128 /* Not absolute_section.
6129 Need a 32-bit fixup (don't support 8bit
6130 non-absolute imms). Try to support other
6132 enum bfd_reloc_code_real reloc_type
;
6133 int size
= imm_size (n
);
6136 if (i
.types
[n
].bitfield
.imm32s
6137 && (i
.suffix
== QWORD_MNEM_SUFFIX
6138 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6143 p
= frag_more (size
);
6144 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6146 /* This is tough to explain. We end up with this one if we
6147 * have operands that look like
6148 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6149 * obtain the absolute address of the GOT, and it is strongly
6150 * preferable from a performance point of view to avoid using
6151 * a runtime relocation for this. The actual sequence of
6152 * instructions often look something like:
6157 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6159 * The call and pop essentially return the absolute address
6160 * of the label .L66 and store it in %ebx. The linker itself
6161 * will ultimately change the first operand of the addl so
6162 * that %ebx points to the GOT, but to keep things simple, the
6163 * .o file must have this operand set so that it generates not
6164 * the absolute address of .L66, but the absolute address of
6165 * itself. This allows the linker itself simply treat a GOTPC
6166 * relocation as asking for a pcrel offset to the GOT to be
6167 * added in, and the addend of the relocation is stored in the
6168 * operand field for the instruction itself.
6170 * Our job here is to fix the operand so that it would add
6171 * the correct offset so that %ebx would point to itself. The
6172 * thing that is tricky is that .-.L66 will point to the
6173 * beginning of the instruction, so we need to further modify
6174 * the operand so that it will point to itself. There are
6175 * other cases where you have something like:
6177 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6179 * and here no correction would be required. Internally in
6180 * the assembler we treat operands of this form as not being
6181 * pcrel since the '.' is explicitly mentioned, and I wonder
6182 * whether it would simplify matters to do it this way. Who
6183 * knows. In earlier versions of the PIC patches, the
6184 * pcrel_adjust field was used to store the correction, but
6185 * since the expression is not pcrel, I felt it would be
6186 * confusing to do it this way. */
6188 if ((reloc_type
== BFD_RELOC_32
6189 || reloc_type
== BFD_RELOC_X86_64_32S
6190 || reloc_type
== BFD_RELOC_64
)
6192 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6193 && (i
.op
[n
].imms
->X_op
== O_symbol
6194 || (i
.op
[n
].imms
->X_op
== O_add
6195 && ((symbol_get_value_expression
6196 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6201 if (insn_start_frag
== frag_now
)
6202 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6207 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6208 for (fr
= insn_start_frag
->fr_next
;
6209 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6211 add
+= p
- frag_now
->fr_literal
;
6215 reloc_type
= BFD_RELOC_386_GOTPC
;
6217 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6219 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6220 i
.op
[n
].imms
->X_add_number
+= add
;
6222 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6223 i
.op
[n
].imms
, 0, reloc_type
);
6229 /* x86_cons_fix_new is called via the expression parsing code when a
6230 reloc is needed. We use this hook to get the correct .got reloc. */
6231 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6232 static int cons_sign
= -1;
6235 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6238 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6240 got_reloc
= NO_RELOC
;
6243 if (exp
->X_op
== O_secrel
)
6245 exp
->X_op
= O_symbol
;
6246 r
= BFD_RELOC_32_SECREL
;
6250 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6253 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6254 # define lex_got(reloc, adjust, types) NULL
6256 /* Parse operands of the form
6257 <symbol>@GOTOFF+<nnn>
6258 and similar .plt or .got references.
6260 If we find one, set up the correct relocation in RELOC and copy the
6261 input string, minus the `@GOTOFF' into a malloc'd buffer for
6262 parsing by the calling routine. Return this buffer, and if ADJUST
6263 is non-null set it to the length of the string we removed from the
6264 input line. Otherwise return NULL. */
6266 lex_got (enum bfd_reloc_code_real
*reloc
,
6268 i386_operand_type
*types
)
6270 /* Some of the relocations depend on the size of what field is to
6271 be relocated. But in our callers i386_immediate and i386_displacement
6272 we don't yet know the operand size (this will be set by insn
6273 matching). Hence we record the word32 relocation here,
6274 and adjust the reloc according to the real size in reloc(). */
6275 static const struct {
6277 const enum bfd_reloc_code_real rel
[2];
6278 const i386_operand_type types64
;
6281 BFD_RELOC_X86_64_PLTOFF64
},
6282 OPERAND_TYPE_IMM64
},
6283 { "PLT", { BFD_RELOC_386_PLT32
,
6284 BFD_RELOC_X86_64_PLT32
},
6285 OPERAND_TYPE_IMM32_32S_DISP32
},
6287 BFD_RELOC_X86_64_GOTPLT64
},
6288 OPERAND_TYPE_IMM64_DISP64
},
6289 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6290 BFD_RELOC_X86_64_GOTOFF64
},
6291 OPERAND_TYPE_IMM64_DISP64
},
6293 BFD_RELOC_X86_64_GOTPCREL
},
6294 OPERAND_TYPE_IMM32_32S_DISP32
},
6295 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6296 BFD_RELOC_X86_64_TLSGD
},
6297 OPERAND_TYPE_IMM32_32S_DISP32
},
6298 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6300 OPERAND_TYPE_NONE
},
6302 BFD_RELOC_X86_64_TLSLD
},
6303 OPERAND_TYPE_IMM32_32S_DISP32
},
6304 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6305 BFD_RELOC_X86_64_GOTTPOFF
},
6306 OPERAND_TYPE_IMM32_32S_DISP32
},
6307 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6308 BFD_RELOC_X86_64_TPOFF32
},
6309 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6310 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6312 OPERAND_TYPE_NONE
},
6313 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6314 BFD_RELOC_X86_64_DTPOFF32
},
6316 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6317 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6319 OPERAND_TYPE_NONE
},
6320 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6322 OPERAND_TYPE_NONE
},
6323 { "GOT", { BFD_RELOC_386_GOT32
,
6324 BFD_RELOC_X86_64_GOT32
},
6325 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6326 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6327 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6328 OPERAND_TYPE_IMM32_32S_DISP32
},
6329 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6330 BFD_RELOC_X86_64_TLSDESC_CALL
},
6331 OPERAND_TYPE_IMM32_32S_DISP32
},
6339 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6340 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6343 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6347 len
= strlen (gotrel
[j
].str
);
6348 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6350 if (gotrel
[j
].rel
[object_64bit
] != 0)
6353 char *tmpbuf
, *past_reloc
;
6355 *reloc
= gotrel
[j
].rel
[object_64bit
];
6361 if (flag_code
!= CODE_64BIT
)
6363 types
->bitfield
.imm32
= 1;
6364 types
->bitfield
.disp32
= 1;
6367 *types
= gotrel
[j
].types64
;
6370 if (GOT_symbol
== NULL
)
6371 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6373 /* The length of the first part of our input line. */
6374 first
= cp
- input_line_pointer
;
6376 /* The second part goes from after the reloc token until
6377 (and including) an end_of_line char or comma. */
6378 past_reloc
= cp
+ 1 + len
;
6380 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6382 second
= cp
+ 1 - past_reloc
;
6384 /* Allocate and copy string. The trailing NUL shouldn't
6385 be necessary, but be safe. */
6386 tmpbuf
= xmalloc (first
+ second
+ 2);
6387 memcpy (tmpbuf
, input_line_pointer
, first
);
6388 if (second
!= 0 && *past_reloc
!= ' ')
6389 /* Replace the relocation token with ' ', so that
6390 errors like foo@GOTOFF1 will be detected. */
6391 tmpbuf
[first
++] = ' ';
6392 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6393 tmpbuf
[first
+ second
] = '\0';
6397 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6398 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6403 /* Might be a symbol version string. Don't as_bad here. */
6408 x86_cons (expressionS
*exp
, int size
)
6410 if (size
== 4 || (object_64bit
&& size
== 8))
6412 /* Handle @GOTOFF and the like in an expression. */
6414 char *gotfree_input_line
;
6417 save
= input_line_pointer
;
6418 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6419 if (gotfree_input_line
)
6420 input_line_pointer
= gotfree_input_line
;
6424 if (gotfree_input_line
)
6426 /* expression () has merrily parsed up to the end of line,
6427 or a comma - in the wrong buffer. Transfer how far
6428 input_line_pointer has moved to the right buffer. */
6429 input_line_pointer
= (save
6430 + (input_line_pointer
- gotfree_input_line
)
6432 free (gotfree_input_line
);
6433 if (exp
->X_op
== O_constant
6434 || exp
->X_op
== O_absent
6435 || exp
->X_op
== O_illegal
6436 || exp
->X_op
== O_register
6437 || exp
->X_op
== O_big
)
6439 char c
= *input_line_pointer
;
6440 *input_line_pointer
= 0;
6441 as_bad (_("missing or invalid expression `%s'"), save
);
6442 *input_line_pointer
= c
;
6451 static void signed_cons (int size
)
6453 if (flag_code
== CODE_64BIT
)
6461 pe_directive_secrel (dummy
)
6462 int dummy ATTRIBUTE_UNUSED
;
6469 if (exp
.X_op
== O_symbol
)
6470 exp
.X_op
= O_secrel
;
6472 emit_expr (&exp
, 4);
6474 while (*input_line_pointer
++ == ',');
6476 input_line_pointer
--;
6477 demand_empty_rest_of_line ();
6482 i386_immediate (char *imm_start
)
6484 char *save_input_line_pointer
;
6485 char *gotfree_input_line
;
6488 i386_operand_type types
;
6490 operand_type_set (&types
, ~0);
6492 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6494 as_bad (_("at most %d immediate operands are allowed"),
6495 MAX_IMMEDIATE_OPERANDS
);
6499 exp
= &im_expressions
[i
.imm_operands
++];
6500 i
.op
[this_operand
].imms
= exp
;
6502 if (is_space_char (*imm_start
))
6505 save_input_line_pointer
= input_line_pointer
;
6506 input_line_pointer
= imm_start
;
6508 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6509 if (gotfree_input_line
)
6510 input_line_pointer
= gotfree_input_line
;
6512 exp_seg
= expression (exp
);
6515 if (*input_line_pointer
)
6516 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6518 input_line_pointer
= save_input_line_pointer
;
6519 if (gotfree_input_line
)
6520 free (gotfree_input_line
);
6522 if (exp
->X_op
== O_absent
6523 || exp
->X_op
== O_illegal
6524 || exp
->X_op
== O_big
6525 || (gotfree_input_line
6526 && (exp
->X_op
== O_constant
6527 || exp
->X_op
== O_register
)))
6529 as_bad (_("missing or invalid immediate expression `%s'"),
6533 else if (exp
->X_op
== O_constant
)
6535 /* Size it properly later. */
6536 i
.types
[this_operand
].bitfield
.imm64
= 1;
6537 /* If BFD64, sign extend val. */
6538 if (!use_rela_relocations
6539 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6541 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6543 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6544 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6545 && exp_seg
!= absolute_section
6546 && exp_seg
!= text_section
6547 && exp_seg
!= data_section
6548 && exp_seg
!= bss_section
6549 && exp_seg
!= undefined_section
6550 && !bfd_is_com_section (exp_seg
))
6552 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6556 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6558 as_bad (_("illegal immediate register operand %s"), imm_start
);
6563 /* This is an address. The size of the address will be
6564 determined later, depending on destination register,
6565 suffix, or the default for the section. */
6566 i
.types
[this_operand
].bitfield
.imm8
= 1;
6567 i
.types
[this_operand
].bitfield
.imm16
= 1;
6568 i
.types
[this_operand
].bitfield
.imm32
= 1;
6569 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6570 i
.types
[this_operand
].bitfield
.imm64
= 1;
6571 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6579 i386_scale (char *scale
)
6582 char *save
= input_line_pointer
;
6584 input_line_pointer
= scale
;
6585 val
= get_absolute_expression ();
6590 i
.log2_scale_factor
= 0;
6593 i
.log2_scale_factor
= 1;
6596 i
.log2_scale_factor
= 2;
6599 i
.log2_scale_factor
= 3;
6603 char sep
= *input_line_pointer
;
6605 *input_line_pointer
= '\0';
6606 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6608 *input_line_pointer
= sep
;
6609 input_line_pointer
= save
;
6613 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6615 as_warn (_("scale factor of %d without an index register"),
6616 1 << i
.log2_scale_factor
);
6617 i
.log2_scale_factor
= 0;
6619 scale
= input_line_pointer
;
6620 input_line_pointer
= save
;
6625 i386_displacement (char *disp_start
, char *disp_end
)
6629 char *save_input_line_pointer
;
6630 char *gotfree_input_line
;
6632 i386_operand_type bigdisp
, types
= anydisp
;
6635 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6637 as_bad (_("at most %d displacement operands are allowed"),
6638 MAX_MEMORY_OPERANDS
);
6642 operand_type_set (&bigdisp
, 0);
6643 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6644 || (!current_templates
->start
->opcode_modifier
.jump
6645 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6647 bigdisp
.bitfield
.disp32
= 1;
6648 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6649 if (flag_code
== CODE_64BIT
)
6653 bigdisp
.bitfield
.disp32s
= 1;
6654 bigdisp
.bitfield
.disp64
= 1;
6657 else if ((flag_code
== CODE_16BIT
) ^ override
)
6659 bigdisp
.bitfield
.disp32
= 0;
6660 bigdisp
.bitfield
.disp16
= 1;
6665 /* For PC-relative branches, the width of the displacement
6666 is dependent upon data size, not address size. */
6667 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6668 if (flag_code
== CODE_64BIT
)
6670 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6671 bigdisp
.bitfield
.disp16
= 1;
6674 bigdisp
.bitfield
.disp32
= 1;
6675 bigdisp
.bitfield
.disp32s
= 1;
6681 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6683 : LONG_MNEM_SUFFIX
));
6684 bigdisp
.bitfield
.disp32
= 1;
6685 if ((flag_code
== CODE_16BIT
) ^ override
)
6687 bigdisp
.bitfield
.disp32
= 0;
6688 bigdisp
.bitfield
.disp16
= 1;
6692 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6695 exp
= &disp_expressions
[i
.disp_operands
];
6696 i
.op
[this_operand
].disps
= exp
;
6698 save_input_line_pointer
= input_line_pointer
;
6699 input_line_pointer
= disp_start
;
6700 END_STRING_AND_SAVE (disp_end
);
6702 #ifndef GCC_ASM_O_HACK
6703 #define GCC_ASM_O_HACK 0
6706 END_STRING_AND_SAVE (disp_end
+ 1);
6707 if (i
.types
[this_operand
].bitfield
.baseIndex
6708 && displacement_string_end
[-1] == '+')
6710 /* This hack is to avoid a warning when using the "o"
6711 constraint within gcc asm statements.
6714 #define _set_tssldt_desc(n,addr,limit,type) \
6715 __asm__ __volatile__ ( \
6717 "movw %w1,2+%0\n\t" \
6719 "movb %b1,4+%0\n\t" \
6720 "movb %4,5+%0\n\t" \
6721 "movb $0,6+%0\n\t" \
6722 "movb %h1,7+%0\n\t" \
6724 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6726 This works great except that the output assembler ends
6727 up looking a bit weird if it turns out that there is
6728 no offset. You end up producing code that looks like:
6741 So here we provide the missing zero. */
6743 *displacement_string_end
= '0';
6746 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6747 if (gotfree_input_line
)
6748 input_line_pointer
= gotfree_input_line
;
6750 exp_seg
= expression (exp
);
6753 if (*input_line_pointer
)
6754 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6756 RESTORE_END_STRING (disp_end
+ 1);
6758 input_line_pointer
= save_input_line_pointer
;
6759 if (gotfree_input_line
)
6760 free (gotfree_input_line
);
6763 /* We do this to make sure that the section symbol is in
6764 the symbol table. We will ultimately change the relocation
6765 to be relative to the beginning of the section. */
6766 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6767 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6768 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6770 if (exp
->X_op
!= O_symbol
)
6773 if (S_IS_LOCAL (exp
->X_add_symbol
)
6774 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6775 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6776 exp
->X_op
= O_subtract
;
6777 exp
->X_op_symbol
= GOT_symbol
;
6778 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6779 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6780 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6781 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6783 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6786 else if (exp
->X_op
== O_absent
6787 || exp
->X_op
== O_illegal
6788 || exp
->X_op
== O_big
6789 || (gotfree_input_line
6790 && (exp
->X_op
== O_constant
6791 || exp
->X_op
== O_register
)))
6794 as_bad (_("missing or invalid displacement expression `%s'"),
6799 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6800 else if (exp
->X_op
!= O_constant
6801 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6802 && exp_seg
!= absolute_section
6803 && exp_seg
!= text_section
6804 && exp_seg
!= data_section
6805 && exp_seg
!= bss_section
6806 && exp_seg
!= undefined_section
6807 && !bfd_is_com_section (exp_seg
))
6809 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6814 RESTORE_END_STRING (disp_end
);
6816 /* Check if this is a displacement only operand. */
6817 bigdisp
= i
.types
[this_operand
];
6818 bigdisp
.bitfield
.disp8
= 0;
6819 bigdisp
.bitfield
.disp16
= 0;
6820 bigdisp
.bitfield
.disp32
= 0;
6821 bigdisp
.bitfield
.disp32s
= 0;
6822 bigdisp
.bitfield
.disp64
= 0;
6823 if (operand_type_all_zero (&bigdisp
))
6824 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6830 /* Make sure the memory operand we've been dealt is valid.
6831 Return 1 on success, 0 on a failure. */
6834 i386_index_check (const char *operand_string
)
6837 #if INFER_ADDR_PREFIX
6843 if (flag_code
== CODE_64BIT
)
6846 && ((i
.prefix
[ADDR_PREFIX
] == 0
6847 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6848 || (i
.prefix
[ADDR_PREFIX
]
6849 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6851 || i
.base_reg
->reg_num
!=
6852 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6854 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6855 || (i
.prefix
[ADDR_PREFIX
] == 0
6856 && i
.index_reg
->reg_num
!= RegRiz
6857 && !i
.index_reg
->reg_type
.bitfield
.reg64
6859 || (i
.prefix
[ADDR_PREFIX
]
6860 && i
.index_reg
->reg_num
!= RegEiz
6861 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6866 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6870 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6871 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6873 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6874 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6876 && i
.base_reg
->reg_num
< 6
6877 && i
.index_reg
->reg_num
>= 6
6878 && i
.log2_scale_factor
== 0))))
6885 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6887 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6888 && i
.index_reg
->reg_num
!= RegEiz
)
6889 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
6895 #if INFER_ADDR_PREFIX
6896 if (i
.prefix
[ADDR_PREFIX
] == 0)
6898 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
6900 /* Change the size of any displacement too. At most one of
6901 Disp16 or Disp32 is set.
6902 FIXME. There doesn't seem to be any real need for separate
6903 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6904 Removing them would probably clean up the code quite a lot. */
6905 if (flag_code
!= CODE_64BIT
6906 && (i
.types
[this_operand
].bitfield
.disp16
6907 || i
.types
[this_operand
].bitfield
.disp32
))
6908 i
.types
[this_operand
]
6909 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
6914 as_bad (_("`%s' is not a valid base/index expression"),
6918 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6920 flag_code_names
[flag_code
]);
6925 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
6929 i386_att_operand (char *operand_string
)
6933 char *op_string
= operand_string
;
6935 if (is_space_char (*op_string
))
6938 /* We check for an absolute prefix (differentiating,
6939 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6940 if (*op_string
== ABSOLUTE_PREFIX
)
6943 if (is_space_char (*op_string
))
6945 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6948 /* Check if operand is a register. */
6949 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
6951 i386_operand_type temp
;
6953 /* Check for a segment override by searching for ':' after a
6954 segment register. */
6956 if (is_space_char (*op_string
))
6958 if (*op_string
== ':'
6959 && (r
->reg_type
.bitfield
.sreg2
6960 || r
->reg_type
.bitfield
.sreg3
))
6965 i
.seg
[i
.mem_operands
] = &es
;
6968 i
.seg
[i
.mem_operands
] = &cs
;
6971 i
.seg
[i
.mem_operands
] = &ss
;
6974 i
.seg
[i
.mem_operands
] = &ds
;
6977 i
.seg
[i
.mem_operands
] = &fs
;
6980 i
.seg
[i
.mem_operands
] = &gs
;
6984 /* Skip the ':' and whitespace. */
6986 if (is_space_char (*op_string
))
6989 if (!is_digit_char (*op_string
)
6990 && !is_identifier_char (*op_string
)
6991 && *op_string
!= '('
6992 && *op_string
!= ABSOLUTE_PREFIX
)
6994 as_bad (_("bad memory operand `%s'"), op_string
);
6997 /* Handle case of %es:*foo. */
6998 if (*op_string
== ABSOLUTE_PREFIX
)
7001 if (is_space_char (*op_string
))
7003 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7005 goto do_memory_reference
;
7009 as_bad (_("junk `%s' after register"), op_string
);
7013 temp
.bitfield
.baseindex
= 0;
7014 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7016 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7017 i
.op
[this_operand
].regs
= r
;
7020 else if (*op_string
== REGISTER_PREFIX
)
7022 as_bad (_("bad register name `%s'"), op_string
);
7025 else if (*op_string
== IMMEDIATE_PREFIX
)
7028 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7030 as_bad (_("immediate operand illegal with absolute jump"));
7033 if (!i386_immediate (op_string
))
7036 else if (is_digit_char (*op_string
)
7037 || is_identifier_char (*op_string
)
7038 || *op_string
== '(')
7040 /* This is a memory reference of some sort. */
7043 /* Start and end of displacement string expression (if found). */
7044 char *displacement_string_start
;
7045 char *displacement_string_end
;
7047 do_memory_reference
:
7048 if ((i
.mem_operands
== 1
7049 && !current_templates
->start
->opcode_modifier
.isstring
)
7050 || i
.mem_operands
== 2)
7052 as_bad (_("too many memory references for `%s'"),
7053 current_templates
->start
->name
);
7057 /* Check for base index form. We detect the base index form by
7058 looking for an ')' at the end of the operand, searching
7059 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7061 base_string
= op_string
+ strlen (op_string
);
7064 if (is_space_char (*base_string
))
7067 /* If we only have a displacement, set-up for it to be parsed later. */
7068 displacement_string_start
= op_string
;
7069 displacement_string_end
= base_string
+ 1;
7071 if (*base_string
== ')')
7074 unsigned int parens_balanced
= 1;
7075 /* We've already checked that the number of left & right ()'s are
7076 equal, so this loop will not be infinite. */
7080 if (*base_string
== ')')
7082 if (*base_string
== '(')
7085 while (parens_balanced
);
7087 temp_string
= base_string
;
7089 /* Skip past '(' and whitespace. */
7091 if (is_space_char (*base_string
))
7094 if (*base_string
== ','
7095 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7098 displacement_string_end
= temp_string
;
7100 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7104 base_string
= end_op
;
7105 if (is_space_char (*base_string
))
7109 /* There may be an index reg or scale factor here. */
7110 if (*base_string
== ',')
7113 if (is_space_char (*base_string
))
7116 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7119 base_string
= end_op
;
7120 if (is_space_char (*base_string
))
7122 if (*base_string
== ',')
7125 if (is_space_char (*base_string
))
7128 else if (*base_string
!= ')')
7130 as_bad (_("expecting `,' or `)' "
7131 "after index register in `%s'"),
7136 else if (*base_string
== REGISTER_PREFIX
)
7138 as_bad (_("bad register name `%s'"), base_string
);
7142 /* Check for scale factor. */
7143 if (*base_string
!= ')')
7145 char *end_scale
= i386_scale (base_string
);
7150 base_string
= end_scale
;
7151 if (is_space_char (*base_string
))
7153 if (*base_string
!= ')')
7155 as_bad (_("expecting `)' "
7156 "after scale factor in `%s'"),
7161 else if (!i
.index_reg
)
7163 as_bad (_("expecting index register or scale factor "
7164 "after `,'; got '%c'"),
7169 else if (*base_string
!= ')')
7171 as_bad (_("expecting `,' or `)' "
7172 "after base register in `%s'"),
7177 else if (*base_string
== REGISTER_PREFIX
)
7179 as_bad (_("bad register name `%s'"), base_string
);
7184 /* If there's an expression beginning the operand, parse it,
7185 assuming displacement_string_start and
7186 displacement_string_end are meaningful. */
7187 if (displacement_string_start
!= displacement_string_end
)
7189 if (!i386_displacement (displacement_string_start
,
7190 displacement_string_end
))
7194 /* Special case for (%dx) while doing input/output op. */
7196 && operand_type_equal (&i
.base_reg
->reg_type
,
7197 ®16_inoutportreg
)
7199 && i
.log2_scale_factor
== 0
7200 && i
.seg
[i
.mem_operands
] == 0
7201 && !operand_type_check (i
.types
[this_operand
], disp
))
7203 i
.types
[this_operand
] = inoutportreg
;
7207 if (i386_index_check (operand_string
) == 0)
7209 i
.types
[this_operand
].bitfield
.mem
= 1;
7214 /* It's not a memory operand; argh! */
7215 as_bad (_("invalid char %s beginning operand %d `%s'"),
7216 output_invalid (*op_string
),
7221 return 1; /* Normal return. */
7224 /* md_estimate_size_before_relax()
7226 Called just before relax() for rs_machine_dependent frags. The x86
7227 assembler uses these frags to handle variable size jump
7230 Any symbol that is now undefined will not become defined.
7231 Return the correct fr_subtype in the frag.
7232 Return the initial "guess for variable size of frag" to caller.
7233 The guess is actually the growth beyond the fixed part. Whatever
7234 we do to grow the fixed or variable part contributes to our
7238 md_estimate_size_before_relax (fragP
, segment
)
7242 /* We've already got fragP->fr_subtype right; all we have to do is
7243 check for un-relaxable symbols. On an ELF system, we can't relax
7244 an externally visible symbol, because it may be overridden by a
7246 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7247 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7249 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7250 || S_IS_WEAK (fragP
->fr_symbol
)))
7254 /* Symbol is undefined in this segment, or we need to keep a
7255 reloc so that weak symbols can be overridden. */
7256 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7257 enum bfd_reloc_code_real reloc_type
;
7258 unsigned char *opcode
;
7261 if (fragP
->fr_var
!= NO_RELOC
)
7262 reloc_type
= fragP
->fr_var
;
7264 reloc_type
= BFD_RELOC_16_PCREL
;
7266 reloc_type
= BFD_RELOC_32_PCREL
;
7268 old_fr_fix
= fragP
->fr_fix
;
7269 opcode
= (unsigned char *) fragP
->fr_opcode
;
7271 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7274 /* Make jmp (0xeb) a (d)word displacement jump. */
7276 fragP
->fr_fix
+= size
;
7277 fix_new (fragP
, old_fr_fix
, size
,
7279 fragP
->fr_offset
, 1,
7285 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7287 /* Negate the condition, and branch past an
7288 unconditional jump. */
7291 /* Insert an unconditional jump. */
7293 /* We added two extra opcode bytes, and have a two byte
7295 fragP
->fr_fix
+= 2 + 2;
7296 fix_new (fragP
, old_fr_fix
+ 2, 2,
7298 fragP
->fr_offset
, 1,
7305 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7310 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7312 fragP
->fr_offset
, 1,
7314 fixP
->fx_signed
= 1;
7318 /* This changes the byte-displacement jump 0x7N
7319 to the (d)word-displacement jump 0x0f,0x8N. */
7320 opcode
[1] = opcode
[0] + 0x10;
7321 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7322 /* We've added an opcode byte. */
7323 fragP
->fr_fix
+= 1 + size
;
7324 fix_new (fragP
, old_fr_fix
+ 1, size
,
7326 fragP
->fr_offset
, 1,
7331 BAD_CASE (fragP
->fr_subtype
);
7335 return fragP
->fr_fix
- old_fr_fix
;
7338 /* Guess size depending on current relax state. Initially the relax
7339 state will correspond to a short jump and we return 1, because
7340 the variable part of the frag (the branch offset) is one byte
7341 long. However, we can relax a section more than once and in that
7342 case we must either set fr_subtype back to the unrelaxed state,
7343 or return the value for the appropriate branch. */
7344 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7347 /* Called after relax() is finished.
7349 In: Address of frag.
7350 fr_type == rs_machine_dependent.
7351 fr_subtype is what the address relaxed to.
7353 Out: Any fixSs and constants are set up.
7354 Caller will turn frag into a ".space 0". */
7357 md_convert_frag (abfd
, sec
, fragP
)
7358 bfd
*abfd ATTRIBUTE_UNUSED
;
7359 segT sec ATTRIBUTE_UNUSED
;
7362 unsigned char *opcode
;
7363 unsigned char *where_to_put_displacement
= NULL
;
7364 offsetT target_address
;
7365 offsetT opcode_address
;
7366 unsigned int extension
= 0;
7367 offsetT displacement_from_opcode_start
;
7369 opcode
= (unsigned char *) fragP
->fr_opcode
;
7371 /* Address we want to reach in file space. */
7372 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7374 /* Address opcode resides at in file space. */
7375 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7377 /* Displacement from opcode start to fill into instruction. */
7378 displacement_from_opcode_start
= target_address
- opcode_address
;
7380 if ((fragP
->fr_subtype
& BIG
) == 0)
7382 /* Don't have to change opcode. */
7383 extension
= 1; /* 1 opcode + 1 displacement */
7384 where_to_put_displacement
= &opcode
[1];
7388 if (no_cond_jump_promotion
7389 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7390 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7391 _("long jump required"));
7393 switch (fragP
->fr_subtype
)
7395 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7396 extension
= 4; /* 1 opcode + 4 displacement */
7398 where_to_put_displacement
= &opcode
[1];
7401 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7402 extension
= 2; /* 1 opcode + 2 displacement */
7404 where_to_put_displacement
= &opcode
[1];
7407 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7408 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7409 extension
= 5; /* 2 opcode + 4 displacement */
7410 opcode
[1] = opcode
[0] + 0x10;
7411 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7412 where_to_put_displacement
= &opcode
[2];
7415 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7416 extension
= 3; /* 2 opcode + 2 displacement */
7417 opcode
[1] = opcode
[0] + 0x10;
7418 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7419 where_to_put_displacement
= &opcode
[2];
7422 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7427 where_to_put_displacement
= &opcode
[3];
7431 BAD_CASE (fragP
->fr_subtype
);
7436 /* If size if less then four we are sure that the operand fits,
7437 but if it's 4, then it could be that the displacement is larger
7439 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7441 && ((addressT
) (displacement_from_opcode_start
- extension
7442 + ((addressT
) 1 << 31))
7443 > (((addressT
) 2 << 31) - 1)))
7445 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7446 _("jump target out of range"));
7447 /* Make us emit 0. */
7448 displacement_from_opcode_start
= extension
;
7450 /* Now put displacement after opcode. */
7451 md_number_to_chars ((char *) where_to_put_displacement
,
7452 (valueT
) (displacement_from_opcode_start
- extension
),
7453 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7454 fragP
->fr_fix
+= extension
;
7457 /* Apply a fixup (fixS) to segment data, once it has been determined
7458 by our caller that we have all the info we need to fix it up.
7460 On the 386, immediates, displacements, and data pointers are all in
7461 the same (little-endian) format, so we don't need to care about which
7465 md_apply_fix (fixP
, valP
, seg
)
7466 /* The fix we're to put in. */
7468 /* Pointer to the value of the bits. */
7470 /* Segment fix is from. */
7471 segT seg ATTRIBUTE_UNUSED
;
7473 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7474 valueT value
= *valP
;
7476 #if !defined (TE_Mach)
7479 switch (fixP
->fx_r_type
)
7485 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7488 case BFD_RELOC_X86_64_32S
:
7489 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7492 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7495 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7500 if (fixP
->fx_addsy
!= NULL
7501 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7502 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7503 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7504 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7505 && !use_rela_relocations
)
7507 /* This is a hack. There should be a better way to handle this.
7508 This covers for the fact that bfd_install_relocation will
7509 subtract the current location (for partial_inplace, PC relative
7510 relocations); see more below. */
7514 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7517 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7519 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7522 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7525 || (symbol_section_p (fixP
->fx_addsy
)
7526 && sym_seg
!= absolute_section
))
7527 && !generic_force_reloc (fixP
))
7529 /* Yes, we add the values in twice. This is because
7530 bfd_install_relocation subtracts them out again. I think
7531 bfd_install_relocation is broken, but I don't dare change
7533 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7537 #if defined (OBJ_COFF) && defined (TE_PE)
7538 /* For some reason, the PE format does not store a
7539 section address offset for a PC relative symbol. */
7540 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7541 || S_IS_WEAK (fixP
->fx_addsy
))
7542 value
+= md_pcrel_from (fixP
);
7546 /* Fix a few things - the dynamic linker expects certain values here,
7547 and we must not disappoint it. */
7548 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7549 if (IS_ELF
&& fixP
->fx_addsy
)
7550 switch (fixP
->fx_r_type
)
7552 case BFD_RELOC_386_PLT32
:
7553 case BFD_RELOC_X86_64_PLT32
:
7554 /* Make the jump instruction point to the address of the operand. At
7555 runtime we merely add the offset to the actual PLT entry. */
7559 case BFD_RELOC_386_TLS_GD
:
7560 case BFD_RELOC_386_TLS_LDM
:
7561 case BFD_RELOC_386_TLS_IE_32
:
7562 case BFD_RELOC_386_TLS_IE
:
7563 case BFD_RELOC_386_TLS_GOTIE
:
7564 case BFD_RELOC_386_TLS_GOTDESC
:
7565 case BFD_RELOC_X86_64_TLSGD
:
7566 case BFD_RELOC_X86_64_TLSLD
:
7567 case BFD_RELOC_X86_64_GOTTPOFF
:
7568 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7569 value
= 0; /* Fully resolved at runtime. No addend. */
7571 case BFD_RELOC_386_TLS_LE
:
7572 case BFD_RELOC_386_TLS_LDO_32
:
7573 case BFD_RELOC_386_TLS_LE_32
:
7574 case BFD_RELOC_X86_64_DTPOFF32
:
7575 case BFD_RELOC_X86_64_DTPOFF64
:
7576 case BFD_RELOC_X86_64_TPOFF32
:
7577 case BFD_RELOC_X86_64_TPOFF64
:
7578 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7581 case BFD_RELOC_386_TLS_DESC_CALL
:
7582 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7583 value
= 0; /* Fully resolved at runtime. No addend. */
7584 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7588 case BFD_RELOC_386_GOT32
:
7589 case BFD_RELOC_X86_64_GOT32
:
7590 value
= 0; /* Fully resolved at runtime. No addend. */
7593 case BFD_RELOC_VTABLE_INHERIT
:
7594 case BFD_RELOC_VTABLE_ENTRY
:
7601 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7603 #endif /* !defined (TE_Mach) */
7605 /* Are we finished with this relocation now? */
7606 if (fixP
->fx_addsy
== NULL
)
7608 else if (use_rela_relocations
)
7610 fixP
->fx_no_overflow
= 1;
7611 /* Remember value for tc_gen_reloc. */
7612 fixP
->fx_addnumber
= value
;
7616 md_number_to_chars (p
, value
, fixP
->fx_size
);
7620 md_atof (int type
, char *litP
, int *sizeP
)
7622 /* This outputs the LITTLENUMs in REVERSE order;
7623 in accord with the bigendian 386. */
7624 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7627 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7630 output_invalid (int c
)
7633 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7636 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7637 "(0x%x)", (unsigned char) c
);
7638 return output_invalid_buf
;
7641 /* REG_STRING starts *before* REGISTER_PREFIX. */
7643 static const reg_entry
*
7644 parse_real_register (char *reg_string
, char **end_op
)
7646 char *s
= reg_string
;
7648 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7651 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7652 if (*s
== REGISTER_PREFIX
)
7655 if (is_space_char (*s
))
7659 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7661 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7662 return (const reg_entry
*) NULL
;
7666 /* For naked regs, make sure that we are not dealing with an identifier.
7667 This prevents confusing an identifier like `eax_var' with register
7669 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7670 return (const reg_entry
*) NULL
;
7674 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7676 /* Handle floating point regs, allowing spaces in the (i) part. */
7677 if (r
== i386_regtab
/* %st is first entry of table */)
7679 if (is_space_char (*s
))
7684 if (is_space_char (*s
))
7686 if (*s
>= '0' && *s
<= '7')
7690 if (is_space_char (*s
))
7695 r
= hash_find (reg_hash
, "st(0)");
7700 /* We have "%st(" then garbage. */
7701 return (const reg_entry
*) NULL
;
7705 if (r
== NULL
|| allow_pseudo_reg
)
7708 if (operand_type_all_zero (&r
->reg_type
))
7709 return (const reg_entry
*) NULL
;
7711 if ((r
->reg_type
.bitfield
.reg32
7712 || r
->reg_type
.bitfield
.sreg3
7713 || r
->reg_type
.bitfield
.control
7714 || r
->reg_type
.bitfield
.debug
7715 || r
->reg_type
.bitfield
.test
)
7716 && !cpu_arch_flags
.bitfield
.cpui386
)
7717 return (const reg_entry
*) NULL
;
7719 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7720 return (const reg_entry
*) NULL
;
7722 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7723 return (const reg_entry
*) NULL
;
7725 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7726 return (const reg_entry
*) NULL
;
7728 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7729 if (!allow_index_reg
7730 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7731 return (const reg_entry
*) NULL
;
7733 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7734 || r
->reg_type
.bitfield
.reg64
)
7735 && (!cpu_arch_flags
.bitfield
.cpulm
7736 || !operand_type_equal (&r
->reg_type
, &control
))
7737 && flag_code
!= CODE_64BIT
)
7738 return (const reg_entry
*) NULL
;
7740 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7741 return (const reg_entry
*) NULL
;
7746 /* REG_STRING starts *before* REGISTER_PREFIX. */
7748 static const reg_entry
*
7749 parse_register (char *reg_string
, char **end_op
)
7753 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7754 r
= parse_real_register (reg_string
, end_op
);
7759 char *save
= input_line_pointer
;
7763 input_line_pointer
= reg_string
;
7764 c
= get_symbol_end ();
7765 symbolP
= symbol_find (reg_string
);
7766 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7768 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7770 know (e
->X_op
== O_register
);
7771 know (e
->X_add_number
>= 0
7772 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7773 r
= i386_regtab
+ e
->X_add_number
;
7774 *end_op
= input_line_pointer
;
7776 *input_line_pointer
= c
;
7777 input_line_pointer
= save
;
7783 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7786 char *end
= input_line_pointer
;
7789 r
= parse_register (name
, &input_line_pointer
);
7790 if (r
&& end
<= input_line_pointer
)
7792 *nextcharP
= *input_line_pointer
;
7793 *input_line_pointer
= 0;
7794 e
->X_op
= O_register
;
7795 e
->X_add_number
= r
- i386_regtab
;
7798 input_line_pointer
= end
;
7804 md_operand (expressionS
*e
)
7806 if (*input_line_pointer
== REGISTER_PREFIX
)
7809 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
7813 e
->X_op
= O_register
;
7814 e
->X_add_number
= r
- i386_regtab
;
7815 input_line_pointer
= end
;
7821 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7822 const char *md_shortopts
= "kVQ:sqn";
7824 const char *md_shortopts
= "qn";
7827 #define OPTION_32 (OPTION_MD_BASE + 0)
7828 #define OPTION_64 (OPTION_MD_BASE + 1)
7829 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7830 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7831 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7832 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7833 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7834 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7835 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7836 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7837 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7838 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7840 struct option md_longopts
[] =
7842 {"32", no_argument
, NULL
, OPTION_32
},
7843 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7844 {"64", no_argument
, NULL
, OPTION_64
},
7846 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7847 {"march", required_argument
, NULL
, OPTION_MARCH
},
7848 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7849 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7850 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7851 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7852 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7853 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7854 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7855 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
7856 {NULL
, no_argument
, NULL
, 0}
7858 size_t md_longopts_size
= sizeof (md_longopts
);
7861 md_parse_option (int c
, char *arg
)
7869 optimize_align_code
= 0;
7876 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7877 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7878 should be emitted or not. FIXME: Not implemented. */
7882 /* -V: SVR4 argument to print version ID. */
7884 print_version_id ();
7887 /* -k: Ignore for FreeBSD compatibility. */
7892 /* -s: On i386 Solaris, this tells the native assembler to use
7893 .stab instead of .stab.excl. We always use .stab anyhow. */
7896 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7899 const char **list
, **l
;
7901 list
= bfd_target_list ();
7902 for (l
= list
; *l
!= NULL
; l
++)
7903 if (CONST_STRNEQ (*l
, "elf64-x86-64")
7904 || strcmp (*l
, "coff-x86-64") == 0
7905 || strcmp (*l
, "pe-x86-64") == 0
7906 || strcmp (*l
, "pei-x86-64") == 0)
7908 default_arch
= "x86_64";
7912 as_fatal (_("No compiled in support for x86_64"));
7919 default_arch
= "i386";
7923 #ifdef SVR4_COMMENT_CHARS
7928 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
7930 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
7934 i386_comment_chars
= n
;
7940 arch
= xstrdup (arg
);
7944 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7945 next
= strchr (arch
, '+');
7948 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7950 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
7953 cpu_arch_name
= cpu_arch
[i
].name
;
7954 cpu_sub_arch_name
= NULL
;
7955 cpu_arch_flags
= cpu_arch
[i
].flags
;
7956 cpu_arch_isa
= cpu_arch
[i
].type
;
7957 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
7958 if (!cpu_arch_tune_set
)
7960 cpu_arch_tune
= cpu_arch_isa
;
7961 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
7965 else if (*cpu_arch
[i
].name
== '.'
7966 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
7968 /* ISA entension. */
7969 i386_cpu_flags flags
;
7970 flags
= cpu_flags_or (cpu_arch_flags
,
7972 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
7974 if (cpu_sub_arch_name
)
7976 char *name
= cpu_sub_arch_name
;
7977 cpu_sub_arch_name
= concat (name
,
7979 (const char *) NULL
);
7983 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
7984 cpu_arch_flags
= flags
;
7990 if (i
>= ARRAY_SIZE (cpu_arch
))
7991 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7995 while (next
!= NULL
);
8000 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8001 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
8003 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
8005 cpu_arch_tune_set
= 1;
8006 cpu_arch_tune
= cpu_arch
[i
].type
;
8007 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
8011 if (i
>= ARRAY_SIZE (cpu_arch
))
8012 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8015 case OPTION_MMNEMONIC
:
8016 if (strcasecmp (arg
, "att") == 0)
8018 else if (strcasecmp (arg
, "intel") == 0)
8021 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8024 case OPTION_MSYNTAX
:
8025 if (strcasecmp (arg
, "att") == 0)
8027 else if (strcasecmp (arg
, "intel") == 0)
8030 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8033 case OPTION_MINDEX_REG
:
8034 allow_index_reg
= 1;
8037 case OPTION_MNAKED_REG
:
8038 allow_naked_reg
= 1;
8041 case OPTION_MOLD_GCC
:
8045 case OPTION_MSSE2AVX
:
8049 case OPTION_MSSE_CHECK
:
8050 if (strcasecmp (arg
, "error") == 0)
8051 sse_check
= sse_check_error
;
8052 else if (strcasecmp (arg
, "warning") == 0)
8053 sse_check
= sse_check_warning
;
8054 else if (strcasecmp (arg
, "none") == 0)
8055 sse_check
= sse_check_none
;
8057 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8067 md_show_usage (stream
)
8070 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8071 fprintf (stream
, _("\
8073 -V print assembler version number\n\
8076 fprintf (stream
, _("\
8077 -n Do not optimize code alignment\n\
8078 -q quieten some warnings\n"));
8079 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8080 fprintf (stream
, _("\
8083 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8084 fprintf (stream
, _("\
8085 --32/--64 generate 32bit/64bit code\n"));
8087 #ifdef SVR4_COMMENT_CHARS
8088 fprintf (stream
, _("\
8089 --divide do not treat `/' as a comment character\n"));
8091 fprintf (stream
, _("\
8092 --divide ignored\n"));
8094 fprintf (stream
, _("\
8095 -march=CPU[,+EXTENSION...]\n\
8096 generate code for CPU and EXTENSION, CPU is one of:\n\
8097 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8098 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8099 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8100 generic32, generic64\n\
8101 EXTENSION is combination of:\n\
8102 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
8103 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8104 3dnow, 3dnowa, sse4a, sse5, svme, abm, padlock\n"));
8105 fprintf (stream
, _("\
8106 -mtune=CPU optimize for CPU, CPU is one of:\n\
8107 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8108 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8109 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8110 generic32, generic64\n"));
8111 fprintf (stream
, _("\
8112 -msse2avx encode SSE instructions with VEX prefix\n"));
8113 fprintf (stream
, _("\
8114 -msse-check=[none|error|warning]\n\
8115 check SSE instructions\n"));
8116 fprintf (stream
, _("\
8117 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8118 fprintf (stream
, _("\
8119 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8120 fprintf (stream
, _("\
8121 -mindex-reg support pseudo index registers\n"));
8122 fprintf (stream
, _("\
8123 -mnaked-reg don't require `%%' prefix for registers\n"));
8124 fprintf (stream
, _("\
8125 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8128 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8129 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
8131 /* Pick the target format to use. */
8134 i386_target_format (void)
8136 if (!strcmp (default_arch
, "x86_64"))
8138 set_code_flag (CODE_64BIT
);
8139 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8141 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8142 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8143 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8144 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8145 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8146 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8147 cpu_arch_isa_flags
.bitfield
.cpup4
= 1;
8148 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8149 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8150 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8152 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8154 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8155 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8156 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8157 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8158 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8159 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8160 cpu_arch_tune_flags
.bitfield
.cpup4
= 1;
8161 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8162 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8163 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8166 else if (!strcmp (default_arch
, "i386"))
8168 set_code_flag (CODE_32BIT
);
8169 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8171 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8172 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8173 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8175 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8177 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8178 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8179 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8183 as_fatal (_("Unknown architecture"));
8184 switch (OUTPUT_FLAVOR
)
8187 case bfd_target_coff_flavour
:
8188 return flag_code
== CODE_64BIT
? COFF_TARGET_FORMAT
: "coff-i386";
8191 #ifdef OBJ_MAYBE_AOUT
8192 case bfd_target_aout_flavour
:
8193 return AOUT_TARGET_FORMAT
;
8195 #ifdef OBJ_MAYBE_COFF
8196 case bfd_target_coff_flavour
:
8199 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8200 case bfd_target_elf_flavour
:
8202 if (flag_code
== CODE_64BIT
)
8205 use_rela_relocations
= 1;
8207 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
8216 #endif /* OBJ_MAYBE_ more than one */
8218 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8220 i386_elf_emit_arch_note (void)
8222 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8225 asection
*seg
= now_seg
;
8226 subsegT subseg
= now_subseg
;
8227 Elf_Internal_Note i_note
;
8228 Elf_External_Note e_note
;
8229 asection
*note_secp
;
8232 /* Create the .note section. */
8233 note_secp
= subseg_new (".note", 0);
8234 bfd_set_section_flags (stdoutput
,
8236 SEC_HAS_CONTENTS
| SEC_READONLY
);
8238 /* Process the arch string. */
8239 len
= strlen (cpu_arch_name
);
8241 i_note
.namesz
= len
+ 1;
8243 i_note
.type
= NT_ARCH
;
8244 p
= frag_more (sizeof (e_note
.namesz
));
8245 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8246 p
= frag_more (sizeof (e_note
.descsz
));
8247 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8248 p
= frag_more (sizeof (e_note
.type
));
8249 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8250 p
= frag_more (len
+ 1);
8251 strcpy (p
, cpu_arch_name
);
8253 frag_align (2, 0, 0);
8255 subseg_set (seg
, subseg
);
8261 md_undefined_symbol (name
)
8264 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8265 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8266 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8267 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8271 if (symbol_find (name
))
8272 as_bad (_("GOT already in symbol table"));
8273 GOT_symbol
= symbol_new (name
, undefined_section
,
8274 (valueT
) 0, &zero_address_frag
);
8281 /* Round up a section size to the appropriate boundary. */
8284 md_section_align (segment
, size
)
8285 segT segment ATTRIBUTE_UNUSED
;
8288 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8289 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8291 /* For a.out, force the section size to be aligned. If we don't do
8292 this, BFD will align it for us, but it will not write out the
8293 final bytes of the section. This may be a bug in BFD, but it is
8294 easier to fix it here since that is how the other a.out targets
8298 align
= bfd_get_section_alignment (stdoutput
, segment
);
8299 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8306 /* On the i386, PC-relative offsets are relative to the start of the
8307 next instruction. That is, the address of the offset, plus its
8308 size, since the offset is always the last part of the insn. */
8311 md_pcrel_from (fixS
*fixP
)
8313 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8319 s_bss (int ignore ATTRIBUTE_UNUSED
)
8323 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8325 obj_elf_section_change_hook ();
8327 temp
= get_absolute_expression ();
8328 subseg_set (bss_section
, (subsegT
) temp
);
8329 demand_empty_rest_of_line ();
8335 i386_validate_fix (fixS
*fixp
)
8337 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8339 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8343 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8348 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8350 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8357 tc_gen_reloc (section
, fixp
)
8358 asection
*section ATTRIBUTE_UNUSED
;
8362 bfd_reloc_code_real_type code
;
8364 switch (fixp
->fx_r_type
)
8366 case BFD_RELOC_X86_64_PLT32
:
8367 case BFD_RELOC_X86_64_GOT32
:
8368 case BFD_RELOC_X86_64_GOTPCREL
:
8369 case BFD_RELOC_386_PLT32
:
8370 case BFD_RELOC_386_GOT32
:
8371 case BFD_RELOC_386_GOTOFF
:
8372 case BFD_RELOC_386_GOTPC
:
8373 case BFD_RELOC_386_TLS_GD
:
8374 case BFD_RELOC_386_TLS_LDM
:
8375 case BFD_RELOC_386_TLS_LDO_32
:
8376 case BFD_RELOC_386_TLS_IE_32
:
8377 case BFD_RELOC_386_TLS_IE
:
8378 case BFD_RELOC_386_TLS_GOTIE
:
8379 case BFD_RELOC_386_TLS_LE_32
:
8380 case BFD_RELOC_386_TLS_LE
:
8381 case BFD_RELOC_386_TLS_GOTDESC
:
8382 case BFD_RELOC_386_TLS_DESC_CALL
:
8383 case BFD_RELOC_X86_64_TLSGD
:
8384 case BFD_RELOC_X86_64_TLSLD
:
8385 case BFD_RELOC_X86_64_DTPOFF32
:
8386 case BFD_RELOC_X86_64_DTPOFF64
:
8387 case BFD_RELOC_X86_64_GOTTPOFF
:
8388 case BFD_RELOC_X86_64_TPOFF32
:
8389 case BFD_RELOC_X86_64_TPOFF64
:
8390 case BFD_RELOC_X86_64_GOTOFF64
:
8391 case BFD_RELOC_X86_64_GOTPC32
:
8392 case BFD_RELOC_X86_64_GOT64
:
8393 case BFD_RELOC_X86_64_GOTPCREL64
:
8394 case BFD_RELOC_X86_64_GOTPC64
:
8395 case BFD_RELOC_X86_64_GOTPLT64
:
8396 case BFD_RELOC_X86_64_PLTOFF64
:
8397 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8398 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8400 case BFD_RELOC_VTABLE_ENTRY
:
8401 case BFD_RELOC_VTABLE_INHERIT
:
8403 case BFD_RELOC_32_SECREL
:
8405 code
= fixp
->fx_r_type
;
8407 case BFD_RELOC_X86_64_32S
:
8408 if (!fixp
->fx_pcrel
)
8410 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8411 code
= fixp
->fx_r_type
;
8417 switch (fixp
->fx_size
)
8420 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8421 _("can not do %d byte pc-relative relocation"),
8423 code
= BFD_RELOC_32_PCREL
;
8425 case 1: code
= BFD_RELOC_8_PCREL
; break;
8426 case 2: code
= BFD_RELOC_16_PCREL
; break;
8427 case 4: code
= BFD_RELOC_32_PCREL
; break;
8429 case 8: code
= BFD_RELOC_64_PCREL
; break;
8435 switch (fixp
->fx_size
)
8438 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8439 _("can not do %d byte relocation"),
8441 code
= BFD_RELOC_32
;
8443 case 1: code
= BFD_RELOC_8
; break;
8444 case 2: code
= BFD_RELOC_16
; break;
8445 case 4: code
= BFD_RELOC_32
; break;
8447 case 8: code
= BFD_RELOC_64
; break;
8454 if ((code
== BFD_RELOC_32
8455 || code
== BFD_RELOC_32_PCREL
8456 || code
== BFD_RELOC_X86_64_32S
)
8458 && fixp
->fx_addsy
== GOT_symbol
)
8461 code
= BFD_RELOC_386_GOTPC
;
8463 code
= BFD_RELOC_X86_64_GOTPC32
;
8465 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8467 && fixp
->fx_addsy
== GOT_symbol
)
8469 code
= BFD_RELOC_X86_64_GOTPC64
;
8472 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8473 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8474 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8476 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8478 if (!use_rela_relocations
)
8480 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8481 vtable entry to be used in the relocation's section offset. */
8482 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8483 rel
->address
= fixp
->fx_offset
;
8487 /* Use the rela in 64bit mode. */
8490 if (!fixp
->fx_pcrel
)
8491 rel
->addend
= fixp
->fx_offset
;
8495 case BFD_RELOC_X86_64_PLT32
:
8496 case BFD_RELOC_X86_64_GOT32
:
8497 case BFD_RELOC_X86_64_GOTPCREL
:
8498 case BFD_RELOC_X86_64_TLSGD
:
8499 case BFD_RELOC_X86_64_TLSLD
:
8500 case BFD_RELOC_X86_64_GOTTPOFF
:
8501 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8502 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8503 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8506 rel
->addend
= (section
->vma
8508 + fixp
->fx_addnumber
8509 + md_pcrel_from (fixp
));
8514 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8515 if (rel
->howto
== NULL
)
8517 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8518 _("cannot represent relocation type %s"),
8519 bfd_get_reloc_code_name (code
));
8520 /* Set howto to a garbage value so that we can keep going. */
8521 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8522 assert (rel
->howto
!= NULL
);
8529 /* Parse operands using Intel syntax. This implements a recursive descent
8530 parser based on the BNF grammar published in Appendix B of the MASM 6.1
8533 FIXME: We do not recognize the full operand grammar defined in the MASM
8534 documentation. In particular, all the structure/union and
8535 high-level macro operands are missing.
8537 Uppercase words are terminals, lower case words are non-terminals.
8538 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
8539 bars '|' denote choices. Most grammar productions are implemented in
8540 functions called 'intel_<production>'.
8542 Initial production is 'expr'.
8548 binOp & | AND | \| | OR | ^ | XOR
8550 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
8552 constant digits [[ radixOverride ]]
8554 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD
8592 => expr expr cmpOp e04
8595 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
8596 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
8598 hexdigit a | b | c | d | e | f
8599 | A | B | C | D | E | F
8605 mulOp * | / | % | MOD | << | SHL | >> | SHR
8609 register specialRegister
8613 segmentRegister CS | DS | ES | FS | GS | SS
8615 specialRegister CR0 | CR2 | CR3 | CR4
8616 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
8617 | TR3 | TR4 | TR5 | TR6 | TR7
8619 We simplify the grammar in obvious places (e.g., register parsing is
8620 done by calling parse_register) and eliminate immediate left recursion
8621 to implement a recursive-descent parser.
8625 expr' cmpOp e04 expr'
8677 /* Parsing structure for the intel syntax parser. Used to implement the
8678 semantic actions for the operand grammar. */
8679 struct intel_parser_s
8681 char *op_string
; /* The string being parsed. */
8682 int got_a_float
; /* Whether the operand is a float. */
8683 int op_modifier
; /* Operand modifier. */
8684 int is_mem
; /* 1 if operand is memory reference. */
8685 int in_offset
; /* >=1 if parsing operand of offset. */
8686 int in_bracket
; /* >=1 if parsing operand in brackets. */
8687 const reg_entry
*reg
; /* Last register reference found. */
8688 char *disp
; /* Displacement string being built. */
8689 char *next_operand
; /* Resume point when splitting operands. */
8692 static struct intel_parser_s intel_parser
;
8694 /* Token structure for parsing intel syntax. */
8697 int code
; /* Token code. */
8698 const reg_entry
*reg
; /* Register entry for register tokens. */
8699 char *str
; /* String representation. */
8702 static struct intel_token cur_token
, prev_token
;
8704 /* Token codes for the intel parser. Since T_SHORT is already used
8705 by COFF, undefine it first to prevent a warning. */
8723 #define T_YMMWORD 16
8725 /* Prototypes for intel parser functions. */
8726 static int intel_match_token (int);
8727 static void intel_putback_token (void);
8728 static void intel_get_token (void);
8729 static int intel_expr (void);
8730 static int intel_e04 (void);
8731 static int intel_e05 (void);
8732 static int intel_e06 (void);
8733 static int intel_e09 (void);
8734 static int intel_e10 (void);
8735 static int intel_e11 (void);
8738 i386_intel_operand (char *operand_string
, int got_a_float
)
8743 p
= intel_parser
.op_string
= xstrdup (operand_string
);
8744 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
8748 /* Initialize token holders. */
8749 cur_token
.code
= prev_token
.code
= T_NIL
;
8750 cur_token
.reg
= prev_token
.reg
= NULL
;
8751 cur_token
.str
= prev_token
.str
= NULL
;
8753 /* Initialize parser structure. */
8754 intel_parser
.got_a_float
= got_a_float
;
8755 intel_parser
.op_modifier
= 0;
8756 intel_parser
.is_mem
= 0;
8757 intel_parser
.in_offset
= 0;
8758 intel_parser
.in_bracket
= 0;
8759 intel_parser
.reg
= NULL
;
8760 intel_parser
.disp
[0] = '\0';
8761 intel_parser
.next_operand
= NULL
;
8763 /* Read the first token and start the parser. */
8765 ret
= intel_expr ();
8770 if (cur_token
.code
!= T_NIL
)
8772 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8773 current_templates
->start
->name
, cur_token
.str
);
8776 /* If we found a memory reference, hand it over to i386_displacement
8777 to fill in the rest of the operand fields. */
8778 else if (intel_parser
.is_mem
)
8780 if ((i
.mem_operands
== 1
8781 && !current_templates
->start
->opcode_modifier
.isstring
)
8782 || i
.mem_operands
== 2)
8784 as_bad (_("too many memory references for '%s'"),
8785 current_templates
->start
->name
);
8790 char *s
= intel_parser
.disp
;
8791 i
.types
[this_operand
].bitfield
.mem
= 1;
8794 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
8795 /* See the comments in intel_bracket_expr. */
8796 as_warn (_("Treating `%s' as memory reference"), operand_string
);
8798 /* Add the displacement expression. */
8800 ret
= i386_displacement (s
, s
+ strlen (s
));
8803 /* Swap base and index in 16-bit memory operands like
8804 [si+bx]. Since i386_index_check is also used in AT&T
8805 mode we have to do that here. */
8808 && i
.base_reg
->reg_type
.bitfield
.reg16
8809 && i
.index_reg
->reg_type
.bitfield
.reg16
8810 && i
.base_reg
->reg_num
>= 6
8811 && i
.index_reg
->reg_num
< 6)
8813 const reg_entry
*base
= i
.index_reg
;
8815 i
.index_reg
= i
.base_reg
;
8818 ret
= i386_index_check (operand_string
);
8823 /* Constant and OFFSET expressions are handled by i386_immediate. */
8824 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
8825 || intel_parser
.reg
== NULL
)
8827 if (i
.mem_operands
< 2 && i
.seg
[i
.mem_operands
])
8829 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
8830 as_warn (_("Segment override ignored"));
8831 i
.seg
[i
.mem_operands
] = NULL
;
8833 ret
= i386_immediate (intel_parser
.disp
);
8836 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
8838 if (!ret
|| !intel_parser
.next_operand
)
8840 intel_parser
.op_string
= intel_parser
.next_operand
;
8841 this_operand
= i
.operands
++;
8842 i
.types
[this_operand
].bitfield
.unspecified
= 1;
8846 free (intel_parser
.disp
);
8851 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
8855 expr' cmpOp e04 expr'
8860 /* XXX Implement the comparison operators. */
8861 return intel_e04 ();
8878 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
8879 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
8881 if (cur_token
.code
== '+')
8883 else if (cur_token
.code
== '-')
8884 nregs
= NUM_ADDRESS_REGS
;
8888 strcat (intel_parser
.disp
, cur_token
.str
);
8889 intel_match_token (cur_token
.code
);
8900 int nregs
= ~NUM_ADDRESS_REGS
;
8907 if (cur_token
.code
== '&'
8908 || cur_token
.code
== '|'
8909 || cur_token
.code
== '^')
8913 str
[0] = cur_token
.code
;
8915 strcat (intel_parser
.disp
, str
);
8920 intel_match_token (cur_token
.code
);
8925 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
8926 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
8937 int nregs
= ~NUM_ADDRESS_REGS
;
8944 if (cur_token
.code
== '*'
8945 || cur_token
.code
== '/'
8946 || cur_token
.code
== '%')
8950 str
[0] = cur_token
.code
;
8952 strcat (intel_parser
.disp
, str
);
8954 else if (cur_token
.code
== T_SHL
)
8955 strcat (intel_parser
.disp
, "<<");
8956 else if (cur_token
.code
== T_SHR
)
8957 strcat (intel_parser
.disp
, ">>");
8961 intel_match_token (cur_token
.code
);
8966 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
8967 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
8985 int nregs
= ~NUM_ADDRESS_REGS
;
8990 /* Don't consume constants here. */
8991 if (cur_token
.code
== '+' || cur_token
.code
== '-')
8993 /* Need to look one token ahead - if the next token
8994 is a constant, the current token is its sign. */
8997 intel_match_token (cur_token
.code
);
8998 next_code
= cur_token
.code
;
8999 intel_putback_token ();
9000 if (next_code
== T_CONST
)
9004 /* e09 OFFSET e09 */
9005 if (cur_token
.code
== T_OFFSET
)
9008 ++intel_parser
.in_offset
;
9012 else if (cur_token
.code
== T_SHORT
)
9013 intel_parser
.op_modifier
|= 1 << T_SHORT
;
9016 else if (cur_token
.code
== '+')
9017 strcat (intel_parser
.disp
, "+");
9022 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
9028 str
[0] = cur_token
.code
;
9030 strcat (intel_parser
.disp
, str
);
9037 intel_match_token (cur_token
.code
);
9045 /* e09' PTR e10 e09' */
9046 if (cur_token
.code
== T_PTR
)
9050 if (prev_token
.code
== T_BYTE
)
9052 suffix
= BYTE_MNEM_SUFFIX
;
9053 i
.types
[this_operand
].bitfield
.byte
= 1;
9056 else if (prev_token
.code
== T_WORD
)
9058 if ((current_templates
->start
->name
[0] == 'l'
9059 && current_templates
->start
->name
[2] == 's'
9060 && current_templates
->start
->name
[3] == 0)
9061 || current_templates
->start
->base_opcode
== 0x62 /* bound */)
9062 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9063 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
9064 suffix
= SHORT_MNEM_SUFFIX
;
9066 suffix
= WORD_MNEM_SUFFIX
;
9067 i
.types
[this_operand
].bitfield
.word
= 1;
9070 else if (prev_token
.code
== T_DWORD
)
9072 if ((current_templates
->start
->name
[0] == 'l'
9073 && current_templates
->start
->name
[2] == 's'
9074 && current_templates
->start
->name
[3] == 0)
9075 || current_templates
->start
->base_opcode
== 0x62 /* bound */)
9076 suffix
= WORD_MNEM_SUFFIX
;
9077 else if (flag_code
== CODE_16BIT
9078 && (current_templates
->start
->opcode_modifier
.jump
9079 || current_templates
->start
->opcode_modifier
.jumpdword
))
9080 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9081 else if (intel_parser
.got_a_float
== 1) /* "f..." */
9082 suffix
= SHORT_MNEM_SUFFIX
;
9084 suffix
= LONG_MNEM_SUFFIX
;
9085 i
.types
[this_operand
].bitfield
.dword
= 1;
9088 else if (prev_token
.code
== T_FWORD
)
9090 if (current_templates
->start
->name
[0] == 'l'
9091 && current_templates
->start
->name
[2] == 's'
9092 && current_templates
->start
->name
[3] == 0)
9093 suffix
= LONG_MNEM_SUFFIX
;
9094 else if (!intel_parser
.got_a_float
)
9096 if (flag_code
== CODE_16BIT
)
9097 add_prefix (DATA_PREFIX_OPCODE
);
9098 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9101 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9102 i
.types
[this_operand
].bitfield
.fword
= 1;
9105 else if (prev_token
.code
== T_QWORD
)
9107 if (current_templates
->start
->base_opcode
== 0x62 /* bound */
9108 || intel_parser
.got_a_float
== 1) /* "f..." */
9109 suffix
= LONG_MNEM_SUFFIX
;
9111 suffix
= QWORD_MNEM_SUFFIX
;
9112 i
.types
[this_operand
].bitfield
.qword
= 1;
9115 else if (prev_token
.code
== T_TBYTE
)
9117 if (intel_parser
.got_a_float
== 1)
9118 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9120 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9123 else if (prev_token
.code
== T_XMMWORD
)
9125 suffix
= XMMWORD_MNEM_SUFFIX
;
9126 i
.types
[this_operand
].bitfield
.xmmword
= 1;
9129 else if (prev_token
.code
== T_YMMWORD
)
9131 suffix
= YMMWORD_MNEM_SUFFIX
;
9132 i
.types
[this_operand
].bitfield
.ymmword
= 1;
9137 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
9141 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9143 /* Operands for jump/call using 'ptr' notation denote absolute
9145 if (current_templates
->start
->opcode_modifier
.jump
9146 || current_templates
->start
->opcode_modifier
.jumpdword
)
9147 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9149 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
9153 else if (i
.suffix
!= suffix
)
9155 as_bad (_("Conflicting operand modifiers"));
9161 /* e09' : e10 e09' */
9162 else if (cur_token
.code
== ':')
9164 if (prev_token
.code
!= T_REG
)
9166 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
9167 segment/group identifier (which we don't have), using comma
9168 as the operand separator there is even less consistent, since
9169 there all branches only have a single operand. */
9170 if (this_operand
!= 0
9171 || intel_parser
.in_offset
9172 || intel_parser
.in_bracket
9173 || (!current_templates
->start
->opcode_modifier
.jump
9174 && !current_templates
->start
->opcode_modifier
.jumpdword
9175 && !current_templates
->start
->opcode_modifier
.jumpintersegment
9176 && !current_templates
->start
->operand_types
[0].bitfield
.jumpabsolute
))
9177 return intel_match_token (T_NIL
);
9178 /* Remember the start of the 2nd operand and terminate 1st
9180 XXX This isn't right, yet (when SSSS:OOOO is right operand of
9181 another expression), but it gets at least the simplest case
9182 (a plain number or symbol on the left side) right. */
9183 intel_parser
.next_operand
= intel_parser
.op_string
;
9184 *--intel_parser
.op_string
= '\0';
9185 return intel_match_token (':');
9193 intel_match_token (cur_token
.code
);
9199 --intel_parser
.in_offset
;
9202 if (NUM_ADDRESS_REGS
> nregs
)
9204 as_bad (_("Invalid operand to `OFFSET'"));
9207 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
9210 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9211 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
9216 intel_bracket_expr (void)
9218 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
9219 const char *start
= intel_parser
.op_string
;
9222 if (i
.op
[this_operand
].regs
)
9223 return intel_match_token (T_NIL
);
9225 intel_match_token ('[');
9227 /* Mark as a memory operand only if it's not already known to be an
9228 offset expression. If it's an offset expression, we need to keep
9230 if (!intel_parser
.in_offset
)
9232 ++intel_parser
.in_bracket
;
9234 /* Operands for jump/call inside brackets denote absolute addresses. */
9235 if (current_templates
->start
->opcode_modifier
.jump
9236 || current_templates
->start
->opcode_modifier
.jumpdword
)
9237 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9239 /* Unfortunately gas always diverged from MASM in a respect that can't
9240 be easily fixed without risking to break code sequences likely to be
9241 encountered (the testsuite even check for this): MASM doesn't consider
9242 an expression inside brackets unconditionally as a memory reference.
9243 When that is e.g. a constant, an offset expression, or the sum of the
9244 two, this is still taken as a constant load. gas, however, always
9245 treated these as memory references. As a compromise, we'll try to make
9246 offset expressions inside brackets work the MASM way (since that's
9247 less likely to be found in real world code), but make constants alone
9248 continue to work the traditional gas way. In either case, issue a
9250 intel_parser
.op_modifier
&= ~was_offset
;
9253 strcat (intel_parser
.disp
, "[");
9255 /* Add a '+' to the displacement string if necessary. */
9256 if (*intel_parser
.disp
!= '\0'
9257 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
9258 strcat (intel_parser
.disp
, "+");
9261 && (len
= intel_parser
.op_string
- start
- 1,
9262 intel_match_token (']')))
9264 /* Preserve brackets when the operand is an offset expression. */
9265 if (intel_parser
.in_offset
)
9266 strcat (intel_parser
.disp
, "]");
9269 --intel_parser
.in_bracket
;
9270 if (i
.base_reg
|| i
.index_reg
)
9271 intel_parser
.is_mem
= 1;
9272 if (!intel_parser
.is_mem
)
9274 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
9275 /* Defer the warning until all of the operand was parsed. */
9276 intel_parser
.is_mem
= -1;
9277 else if (!quiet_warnings
)
9278 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
9279 len
, start
, len
, start
);
9282 intel_parser
.op_modifier
|= was_offset
;
9299 while (cur_token
.code
== '[')
9301 if (!intel_bracket_expr ())
9327 switch (cur_token
.code
)
9331 intel_match_token ('(');
9332 strcat (intel_parser
.disp
, "(");
9334 if (intel_expr () && intel_match_token (')'))
9336 strcat (intel_parser
.disp
, ")");
9343 return intel_bracket_expr ();
9348 strcat (intel_parser
.disp
, cur_token
.str
);
9349 intel_match_token (cur_token
.code
);
9351 /* Mark as a memory operand only if it's not already known to be an
9352 offset expression. */
9353 if (!intel_parser
.in_offset
)
9354 intel_parser
.is_mem
= 1;
9361 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
9363 intel_match_token (T_REG
);
9365 /* Check for segment change. */
9366 if (cur_token
.code
== ':')
9368 if (!reg
->reg_type
.bitfield
.sreg2
9369 && !reg
->reg_type
.bitfield
.sreg3
)
9371 as_bad (_("`%s' is not a valid segment register"),
9375 else if (i
.mem_operands
>= 2)
9376 as_warn (_("Segment override ignored"));
9377 else if (i
.seg
[i
.mem_operands
])
9378 as_warn (_("Extra segment override ignored"));
9381 if (!intel_parser
.in_offset
)
9382 intel_parser
.is_mem
= 1;
9383 switch (reg
->reg_num
)
9386 i
.seg
[i
.mem_operands
] = &es
;
9389 i
.seg
[i
.mem_operands
] = &cs
;
9392 i
.seg
[i
.mem_operands
] = &ss
;
9395 i
.seg
[i
.mem_operands
] = &ds
;
9398 i
.seg
[i
.mem_operands
] = &fs
;
9401 i
.seg
[i
.mem_operands
] = &gs
;
9407 else if (reg
->reg_type
.bitfield
.sreg3
&& reg
->reg_num
== RegFlat
)
9409 as_bad (_("cannot use `FLAT' here"));
9413 /* Not a segment register. Check for register scaling. */
9414 else if (cur_token
.code
== '*')
9416 if (!intel_parser
.in_bracket
)
9418 as_bad (_("Register scaling only allowed in memory operands"));
9422 if (reg
->reg_type
.bitfield
.reg16
) /* Disallow things like [si*1]. */
9423 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
9424 else if (i
.index_reg
)
9425 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
9427 /* What follows must be a valid scale. */
9428 intel_match_token ('*');
9430 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9432 /* Set the scale after setting the register (otherwise,
9433 i386_scale will complain) */
9434 if (cur_token
.code
== '+' || cur_token
.code
== '-')
9436 char *str
, sign
= cur_token
.code
;
9437 intel_match_token (cur_token
.code
);
9438 if (cur_token
.code
!= T_CONST
)
9440 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9444 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
9445 strcpy (str
+ 1, cur_token
.str
);
9447 if (!i386_scale (str
))
9451 else if (!i386_scale (cur_token
.str
))
9453 intel_match_token (cur_token
.code
);
9456 /* No scaling. If this is a memory operand, the register is either a
9457 base register (first occurrence) or an index register (second
9459 else if (intel_parser
.in_bracket
)
9464 else if (!i
.index_reg
)
9468 as_bad (_("Too many register references in memory operand"));
9472 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9475 /* It's neither base nor index. */
9476 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
9478 i386_operand_type temp
= reg
->reg_type
;
9479 temp
.bitfield
.baseindex
= 0;
9480 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9482 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9483 i
.op
[this_operand
].regs
= reg
;
9488 as_bad (_("Invalid use of register"));
9492 /* Since registers are not part of the displacement string (except
9493 when we're parsing offset operands), we may need to remove any
9494 preceding '+' from the displacement string. */
9495 if (*intel_parser
.disp
!= '\0'
9496 && !intel_parser
.in_offset
)
9498 char *s
= intel_parser
.disp
;
9499 s
+= strlen (s
) - 1;
9524 intel_match_token (cur_token
.code
);
9526 if (cur_token
.code
== T_PTR
)
9529 /* It must have been an identifier. */
9530 intel_putback_token ();
9531 cur_token
.code
= T_ID
;
9537 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
9541 /* The identifier represents a memory reference only if it's not
9542 preceded by an offset modifier and if it's not an equate. */
9543 symbolP
= symbol_find(cur_token
.str
);
9544 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
9545 intel_parser
.is_mem
= 1;
9553 char *save_str
, sign
= 0;
9555 /* Allow constants that start with `+' or `-'. */
9556 if (cur_token
.code
== '-' || cur_token
.code
== '+')
9558 sign
= cur_token
.code
;
9559 intel_match_token (cur_token
.code
);
9560 if (cur_token
.code
!= T_CONST
)
9562 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9568 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
9569 strcpy (save_str
+ !!sign
, cur_token
.str
);
9573 /* Get the next token to check for register scaling. */
9574 intel_match_token (cur_token
.code
);
9576 /* Check if this constant is a scaling factor for an
9578 if (cur_token
.code
== '*')
9580 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
9582 const reg_entry
*reg
= cur_token
.reg
;
9584 if (!intel_parser
.in_bracket
)
9586 as_bad (_("Register scaling only allowed "
9587 "in memory operands"));
9591 /* Disallow things like [1*si].
9592 sp and esp are invalid as index. */
9593 if (reg
->reg_type
.bitfield
.reg16
)
9594 reg
= i386_regtab
+ REGNAM_AX
+ 4;
9595 else if (i
.index_reg
)
9596 reg
= i386_regtab
+ REGNAM_EAX
+ 4;
9598 /* The constant is followed by `* reg', so it must be
9601 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9603 /* Set the scale after setting the register (otherwise,
9604 i386_scale will complain) */
9605 if (!i386_scale (save_str
))
9607 intel_match_token (T_REG
);
9609 /* Since registers are not part of the displacement
9610 string, we may need to remove any preceding '+' from
9611 the displacement string. */
9612 if (*intel_parser
.disp
!= '\0')
9614 char *s
= intel_parser
.disp
;
9615 s
+= strlen (s
) - 1;
9625 /* The constant was not used for register scaling. Since we have
9626 already consumed the token following `*' we now need to put it
9627 back in the stream. */
9628 intel_putback_token ();
9631 /* Add the constant to the displacement string. */
9632 strcat (intel_parser
.disp
, save_str
);
9639 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
9643 /* Match the given token against cur_token. If they match, read the next
9644 token from the operand string. */
9646 intel_match_token (int code
)
9648 if (cur_token
.code
== code
)
9655 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
9660 /* Read a new token from intel_parser.op_string and store it in cur_token. */
9662 intel_get_token (void)
9665 const reg_entry
*reg
;
9666 struct intel_token new_token
;
9668 new_token
.code
= T_NIL
;
9669 new_token
.reg
= NULL
;
9670 new_token
.str
= NULL
;
9672 /* Free the memory allocated to the previous token and move
9673 cur_token to prev_token. */
9675 free (prev_token
.str
);
9677 prev_token
= cur_token
;
9679 /* Skip whitespace. */
9680 while (is_space_char (*intel_parser
.op_string
))
9681 intel_parser
.op_string
++;
9683 /* Return an empty token if we find nothing else on the line. */
9684 if (*intel_parser
.op_string
== '\0')
9686 cur_token
= new_token
;
9690 /* The new token cannot be larger than the remainder of the operand
9692 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
9693 new_token
.str
[0] = '\0';
9695 if (strchr ("0123456789", *intel_parser
.op_string
))
9697 char *p
= new_token
.str
;
9698 char *q
= intel_parser
.op_string
;
9699 new_token
.code
= T_CONST
;
9701 /* Allow any kind of identifier char to encompass floating point and
9702 hexadecimal numbers. */
9703 while (is_identifier_char (*q
))
9707 /* Recognize special symbol names [0-9][bf]. */
9708 if (strlen (intel_parser
.op_string
) == 2
9709 && (intel_parser
.op_string
[1] == 'b'
9710 || intel_parser
.op_string
[1] == 'f'))
9711 new_token
.code
= T_ID
;
9714 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
9716 size_t len
= end_op
- intel_parser
.op_string
;
9718 new_token
.code
= T_REG
;
9719 new_token
.reg
= reg
;
9721 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
9722 new_token
.str
[len
] = '\0';
9725 else if (is_identifier_char (*intel_parser
.op_string
))
9727 char *p
= new_token
.str
;
9728 char *q
= intel_parser
.op_string
;
9730 /* A '.' or '$' followed by an identifier char is an identifier.
9731 Otherwise, it's operator '.' followed by an expression. */
9732 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
9734 new_token
.code
= '.';
9735 new_token
.str
[0] = '.';
9736 new_token
.str
[1] = '\0';
9740 while (is_identifier_char (*q
) || *q
== '@')
9744 if (strcasecmp (new_token
.str
, "NOT") == 0)
9745 new_token
.code
= '~';
9747 else if (strcasecmp (new_token
.str
, "MOD") == 0)
9748 new_token
.code
= '%';
9750 else if (strcasecmp (new_token
.str
, "AND") == 0)
9751 new_token
.code
= '&';
9753 else if (strcasecmp (new_token
.str
, "OR") == 0)
9754 new_token
.code
= '|';
9756 else if (strcasecmp (new_token
.str
, "XOR") == 0)
9757 new_token
.code
= '^';
9759 else if (strcasecmp (new_token
.str
, "SHL") == 0)
9760 new_token
.code
= T_SHL
;
9762 else if (strcasecmp (new_token
.str
, "SHR") == 0)
9763 new_token
.code
= T_SHR
;
9765 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
9766 new_token
.code
= T_BYTE
;
9768 else if (strcasecmp (new_token
.str
, "WORD") == 0)
9769 new_token
.code
= T_WORD
;
9771 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
9772 new_token
.code
= T_DWORD
;
9774 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
9775 new_token
.code
= T_FWORD
;
9777 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
9778 new_token
.code
= T_QWORD
;
9780 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
9781 /* XXX remove (gcc still uses it) */
9782 || strcasecmp (new_token
.str
, "XWORD") == 0)
9783 new_token
.code
= T_TBYTE
;
9785 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
9786 || strcasecmp (new_token
.str
, "OWORD") == 0)
9787 new_token
.code
= T_XMMWORD
;
9789 else if (strcasecmp (new_token
.str
, "YMMWORD") == 0)
9790 new_token
.code
= T_YMMWORD
;
9792 else if (strcasecmp (new_token
.str
, "PTR") == 0)
9793 new_token
.code
= T_PTR
;
9795 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
9796 new_token
.code
= T_SHORT
;
9798 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
9800 new_token
.code
= T_OFFSET
;
9802 /* ??? This is not mentioned in the MASM grammar but gcc
9803 makes use of it with -mintel-syntax. OFFSET may be
9804 followed by FLAT: */
9805 if (strncasecmp (q
, " FLAT:", 6) == 0)
9806 strcat (new_token
.str
, " FLAT:");
9810 new_token
.code
= T_ID
;
9814 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
9816 new_token
.code
= *intel_parser
.op_string
;
9817 new_token
.str
[0] = *intel_parser
.op_string
;
9818 new_token
.str
[1] = '\0';
9821 else if (strchr ("<>", *intel_parser
.op_string
)
9822 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
9824 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
9825 new_token
.str
[0] = *intel_parser
.op_string
;
9826 new_token
.str
[1] = *intel_parser
.op_string
;
9827 new_token
.str
[2] = '\0';
9831 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
9833 intel_parser
.op_string
+= strlen (new_token
.str
);
9834 cur_token
= new_token
;
9837 /* Put cur_token back into the token stream and make cur_token point to
9840 intel_putback_token (void)
9842 if (cur_token
.code
!= T_NIL
)
9844 intel_parser
.op_string
-= strlen (cur_token
.str
);
9845 free (cur_token
.str
);
9847 cur_token
= prev_token
;
9849 /* Forget prev_token. */
9850 prev_token
.code
= T_NIL
;
9851 prev_token
.reg
= NULL
;
9852 prev_token
.str
= NULL
;
9856 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
9858 int saved_naked_reg
;
9859 char saved_register_dot
;
9861 saved_naked_reg
= allow_naked_reg
;
9862 allow_naked_reg
= 1;
9863 saved_register_dot
= register_chars
['.'];
9864 register_chars
['.'] = '.';
9865 allow_pseudo_reg
= 1;
9866 expression_and_evaluate (exp
);
9867 allow_pseudo_reg
= 0;
9868 register_chars
['.'] = saved_register_dot
;
9869 allow_naked_reg
= saved_naked_reg
;
9871 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
9873 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
9875 exp
->X_op
= O_constant
;
9876 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
9877 .dw2_regnum
[flag_code
>> 1];
9880 exp
->X_op
= O_illegal
;
9885 tc_x86_frame_initial_instructions (void)
9887 static unsigned int sp_regno
[2];
9889 if (!sp_regno
[flag_code
>> 1])
9891 char *saved_input
= input_line_pointer
;
9892 char sp
[][4] = {"esp", "rsp"};
9895 input_line_pointer
= sp
[flag_code
>> 1];
9896 tc_x86_parse_to_dw2regnum (&exp
);
9897 assert (exp
.X_op
== O_constant
);
9898 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
9899 input_line_pointer
= saved_input
;
9902 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
9903 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
9907 i386_elf_section_type (const char *str
, size_t len
)
9909 if (flag_code
== CODE_64BIT
9910 && len
== sizeof ("unwind") - 1
9911 && strncmp (str
, "unwind", 6) == 0)
9912 return SHT_X86_64_UNWIND
;
9919 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
9923 expr
.X_op
= O_secrel
;
9924 expr
.X_add_symbol
= symbol
;
9925 expr
.X_add_number
= 0;
9926 emit_expr (&expr
, size
);
9930 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9931 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9934 x86_64_section_letter (int letter
, char **ptr_msg
)
9936 if (flag_code
== CODE_64BIT
)
9939 return SHF_X86_64_LARGE
;
9941 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
9944 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
9949 x86_64_section_word (char *str
, size_t len
)
9951 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
9952 return SHF_X86_64_LARGE
;
9958 handle_large_common (int small ATTRIBUTE_UNUSED
)
9960 if (flag_code
!= CODE_64BIT
)
9962 s_comm_internal (0, elf_common_parse
);
9963 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9967 static segT lbss_section
;
9968 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
9969 asection
*saved_bss_section
= bss_section
;
9971 if (lbss_section
== NULL
)
9973 flagword applicable
;
9975 subsegT subseg
= now_subseg
;
9977 /* The .lbss section is for local .largecomm symbols. */
9978 lbss_section
= subseg_new (".lbss", 0);
9979 applicable
= bfd_applicable_section_flags (stdoutput
);
9980 bfd_set_section_flags (stdoutput
, lbss_section
,
9981 applicable
& SEC_ALLOC
);
9982 seg_info (lbss_section
)->bss
= 1;
9984 subseg_set (seg
, subseg
);
9987 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
9988 bss_section
= lbss_section
;
9990 s_comm_internal (0, elf_common_parse
);
9992 elf_com_section_ptr
= saved_com_section_ptr
;
9993 bss_section
= saved_bss_section
;
9996 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */