1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef REGISTER_WARNINGS
48 #define REGISTER_WARNINGS 1
51 #ifndef INFER_ADDR_PREFIX
52 #define INFER_ADDR_PREFIX 1
56 #define DEFAULT_ARCH "i386"
61 #define INLINE __inline__
67 /* Prefixes will be emitted in the order defined below.
68 WAIT_PREFIX must be the first prefix since FWAIT is really is an
69 instruction, and so must come before any prefixes.
70 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
71 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
77 #define HLE_PREFIX REP_PREFIX
78 #define BND_PREFIX REP_PREFIX
80 #define REX_PREFIX 6 /* must come last. */
81 #define MAX_PREFIXES 7 /* max prefixes per opcode */
83 /* we define the syntax here (modulo base,index,scale syntax) */
84 #define REGISTER_PREFIX '%'
85 #define IMMEDIATE_PREFIX '$'
86 #define ABSOLUTE_PREFIX '*'
88 /* these are the instruction mnemonic suffixes in AT&T syntax or
89 memory operand size in Intel syntax. */
90 #define WORD_MNEM_SUFFIX 'w'
91 #define BYTE_MNEM_SUFFIX 'b'
92 #define SHORT_MNEM_SUFFIX 's'
93 #define LONG_MNEM_SUFFIX 'l'
94 #define QWORD_MNEM_SUFFIX 'q'
95 /* Intel Syntax. Use a non-ascii letter since since it never appears
97 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
99 #define END_OF_INSN '\0'
101 /* This matches the C -> StaticRounding alias in the opcode table. */
102 #define commutative staticrounding
105 'templates' is for grouping together 'template' structures for opcodes
106 of the same name. This is only used for storing the insns in the grand
107 ole hash table of insns.
108 The templates themselves start at START and range up to (but not including)
113 const insn_template
*start
;
114 const insn_template
*end
;
118 /* 386 operand encoding bytes: see 386 book for details of this. */
121 unsigned int regmem
; /* codes register or memory operand */
122 unsigned int reg
; /* codes register operand (or extended opcode) */
123 unsigned int mode
; /* how to interpret regmem & reg */
127 /* x86-64 extension prefix. */
128 typedef int rex_byte
;
130 /* 386 opcode byte to code indirect addressing. */
139 /* x86 arch names, types and features */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 enum processor_type type
; /* arch type */
145 i386_cpu_flags flags
; /* cpu feature flags */
146 unsigned int skip
; /* show_arch should skip this. */
150 /* Used to turn off indicated flags. */
153 const char *name
; /* arch name */
154 unsigned int len
; /* arch string length */
155 i386_cpu_flags flags
; /* cpu feature flags */
159 static void update_code_flag (int, int);
160 static void set_code_flag (int);
161 static void set_16bit_gcc_code_flag (int);
162 static void set_intel_syntax (int);
163 static void set_intel_mnemonic (int);
164 static void set_allow_index_reg (int);
165 static void set_check (int);
166 static void set_cpu_arch (int);
168 static void pe_directive_secrel (int);
170 static void signed_cons (int);
171 static char *output_invalid (int c
);
172 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
174 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
176 static int i386_att_operand (char *);
177 static int i386_intel_operand (char *, int);
178 static int i386_intel_simplify (expressionS
*);
179 static int i386_intel_parse_name (const char *, expressionS
*);
180 static const reg_entry
*parse_register (char *, char **);
181 static char *parse_insn (char *, char *);
182 static char *parse_operands (char *, const char *);
183 static void swap_operands (void);
184 static void swap_2_operands (int, int);
185 static enum flag_code
i386_addressing_mode (void);
186 static void optimize_imm (void);
187 static void optimize_disp (void);
188 static const insn_template
*match_template (char);
189 static int check_string (void);
190 static int process_suffix (void);
191 static int check_byte_reg (void);
192 static int check_long_reg (void);
193 static int check_qword_reg (void);
194 static int check_word_reg (void);
195 static int finalize_imm (void);
196 static int process_operands (void);
197 static const seg_entry
*build_modrm_byte (void);
198 static void output_insn (void);
199 static void output_imm (fragS
*, offsetT
);
200 static void output_disp (fragS
*, offsetT
);
202 static void s_bss (int);
204 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
205 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
207 /* GNU_PROPERTY_X86_ISA_1_USED. */
208 static unsigned int x86_isa_1_used
;
209 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
210 static unsigned int x86_feature_2_used
;
211 /* Generate x86 used ISA and feature properties. */
212 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
215 static const char *default_arch
= DEFAULT_ARCH
;
217 /* This struct describes rounding control and SAE in the instruction. */
231 static struct RC_Operation rc_op
;
233 /* The struct describes masking, applied to OPERAND in the instruction.
234 MASK is a pointer to the corresponding mask register. ZEROING tells
235 whether merging or zeroing mask is used. */
236 struct Mask_Operation
238 const reg_entry
*mask
;
239 unsigned int zeroing
;
240 /* The operand where this operation is associated. */
244 static struct Mask_Operation mask_op
;
246 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
248 struct Broadcast_Operation
250 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
253 /* Index of broadcasted operand. */
256 /* Number of bytes to broadcast. */
260 static struct Broadcast_Operation broadcast_op
;
265 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
266 unsigned char bytes
[4];
268 /* Destination or source register specifier. */
269 const reg_entry
*register_specifier
;
272 /* 'md_assemble ()' gathers together information and puts it into a
279 const reg_entry
*regs
;
284 operand_size_mismatch
,
285 operand_type_mismatch
,
286 register_type_mismatch
,
287 number_of_operands_mismatch
,
288 invalid_instruction_suffix
,
290 unsupported_with_intel_mnemonic
,
293 invalid_vsib_address
,
294 invalid_vector_register_set
,
295 unsupported_vector_index_register
,
296 unsupported_broadcast
,
299 mask_not_on_destination
,
302 rc_sae_operand_not_last_imm
,
303 invalid_register_operand
,
308 /* TM holds the template for the insn were currently assembling. */
311 /* SUFFIX holds the instruction size suffix for byte, word, dword
312 or qword, if given. */
315 /* OPERANDS gives the number of given operands. */
316 unsigned int operands
;
318 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
319 of given register, displacement, memory operands and immediate
321 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
323 /* TYPES [i] is the type (see above #defines) which tells us how to
324 use OP[i] for the corresponding operand. */
325 i386_operand_type types
[MAX_OPERANDS
];
327 /* Displacement expression, immediate expression, or register for each
329 union i386_op op
[MAX_OPERANDS
];
331 /* Flags for operands. */
332 unsigned int flags
[MAX_OPERANDS
];
333 #define Operand_PCrel 1
334 #define Operand_Mem 2
336 /* Relocation type for operand */
337 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
339 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
340 the base index byte below. */
341 const reg_entry
*base_reg
;
342 const reg_entry
*index_reg
;
343 unsigned int log2_scale_factor
;
345 /* SEG gives the seg_entries of this insn. They are zero unless
346 explicit segment overrides are given. */
347 const seg_entry
*seg
[2];
349 /* Copied first memory operand string, for re-checking. */
352 /* PREFIX holds all the given prefix opcodes (usually null).
353 PREFIXES is the number of prefix opcodes. */
354 unsigned int prefixes
;
355 unsigned char prefix
[MAX_PREFIXES
];
357 /* The operand to a branch insn indicates an absolute branch. */
358 bfd_boolean jumpabsolute
;
360 /* Has MMX register operands. */
361 bfd_boolean has_regmmx
;
363 /* Has XMM register operands. */
364 bfd_boolean has_regxmm
;
366 /* Has YMM register operands. */
367 bfd_boolean has_regymm
;
369 /* Has ZMM register operands. */
370 bfd_boolean has_regzmm
;
372 /* Has GOTPC or TLS relocation. */
373 bfd_boolean has_gotpc_tls_reloc
;
375 /* RM and SIB are the modrm byte and the sib byte where the
376 addressing modes of this insn are encoded. */
383 /* Masking attributes. */
384 struct Mask_Operation
*mask
;
386 /* Rounding control and SAE attributes. */
387 struct RC_Operation
*rounding
;
389 /* Broadcasting attributes. */
390 struct Broadcast_Operation
*broadcast
;
392 /* Compressed disp8*N attribute. */
393 unsigned int memshift
;
395 /* Prefer load or store in encoding. */
398 dir_encoding_default
= 0,
404 /* Prefer 8bit or 32bit displacement in encoding. */
407 disp_encoding_default
= 0,
412 /* Prefer the REX byte in encoding. */
413 bfd_boolean rex_encoding
;
415 /* Disable instruction size optimization. */
416 bfd_boolean no_optimize
;
418 /* How to encode vector instructions. */
421 vex_encoding_default
= 0,
428 const char *rep_prefix
;
431 const char *hle_prefix
;
433 /* Have BND prefix. */
434 const char *bnd_prefix
;
436 /* Have NOTRACK prefix. */
437 const char *notrack_prefix
;
440 enum i386_error error
;
443 typedef struct _i386_insn i386_insn
;
445 /* Link RC type with corresponding string, that'll be looked for in
454 static const struct RC_name RC_NamesTable
[] =
456 { rne
, STRING_COMMA_LEN ("rn-sae") },
457 { rd
, STRING_COMMA_LEN ("rd-sae") },
458 { ru
, STRING_COMMA_LEN ("ru-sae") },
459 { rz
, STRING_COMMA_LEN ("rz-sae") },
460 { saeonly
, STRING_COMMA_LEN ("sae") },
463 /* List of chars besides those in app.c:symbol_chars that can start an
464 operand. Used to prevent the scrubber eating vital white-space. */
465 const char extra_symbol_chars
[] = "*%-([{}"
474 #if (defined (TE_I386AIX) \
475 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
476 && !defined (TE_GNU) \
477 && !defined (TE_LINUX) \
478 && !defined (TE_NACL) \
479 && !defined (TE_FreeBSD) \
480 && !defined (TE_DragonFly) \
481 && !defined (TE_NetBSD)))
482 /* This array holds the chars that always start a comment. If the
483 pre-processor is disabled, these aren't very useful. The option
484 --divide will remove '/' from this list. */
485 const char *i386_comment_chars
= "#/";
486 #define SVR4_COMMENT_CHARS 1
487 #define PREFIX_SEPARATOR '\\'
490 const char *i386_comment_chars
= "#";
491 #define PREFIX_SEPARATOR '/'
494 /* This array holds the chars that only start a comment at the beginning of
495 a line. If the line seems to have the form '# 123 filename'
496 .line and .file directives will appear in the pre-processed output.
497 Note that input_file.c hand checks for '#' at the beginning of the
498 first line of the input file. This is because the compiler outputs
499 #NO_APP at the beginning of its output.
500 Also note that comments started like this one will always work if
501 '/' isn't otherwise defined. */
502 const char line_comment_chars
[] = "#/";
504 const char line_separator_chars
[] = ";";
506 /* Chars that can be used to separate mant from exp in floating point
508 const char EXP_CHARS
[] = "eE";
510 /* Chars that mean this number is a floating point constant
513 const char FLT_CHARS
[] = "fFdDxX";
515 /* Tables for lexical analysis. */
516 static char mnemonic_chars
[256];
517 static char register_chars
[256];
518 static char operand_chars
[256];
519 static char identifier_chars
[256];
520 static char digit_chars
[256];
522 /* Lexical macros. */
523 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
524 #define is_operand_char(x) (operand_chars[(unsigned char) x])
525 #define is_register_char(x) (register_chars[(unsigned char) x])
526 #define is_space_char(x) ((x) == ' ')
527 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
528 #define is_digit_char(x) (digit_chars[(unsigned char) x])
530 /* All non-digit non-letter characters that may occur in an operand. */
531 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
533 /* md_assemble() always leaves the strings it's passed unaltered. To
534 effect this we maintain a stack of saved characters that we've smashed
535 with '\0's (indicating end of strings for various sub-fields of the
536 assembler instruction). */
537 static char save_stack
[32];
538 static char *save_stack_p
;
539 #define END_STRING_AND_SAVE(s) \
540 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
541 #define RESTORE_END_STRING(s) \
542 do { *(s) = *--save_stack_p; } while (0)
544 /* The instruction we're assembling. */
547 /* Possible templates for current insn. */
548 static const templates
*current_templates
;
550 /* Per instruction expressionS buffers: max displacements & immediates. */
551 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
552 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
554 /* Current operand we are working on. */
555 static int this_operand
= -1;
557 /* We support four different modes. FLAG_CODE variable is used to distinguish
565 static enum flag_code flag_code
;
566 static unsigned int object_64bit
;
567 static unsigned int disallow_64bit_reloc
;
568 static int use_rela_relocations
= 0;
569 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
570 static const char *tls_get_addr
;
572 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
573 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
574 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
576 /* The ELF ABI to use. */
584 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
587 #if defined (TE_PE) || defined (TE_PEP)
588 /* Use big object file format. */
589 static int use_big_obj
= 0;
592 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
593 /* 1 if generating code for a shared library. */
594 static int shared
= 0;
597 /* 1 for intel syntax,
599 static int intel_syntax
= 0;
601 /* 1 for Intel64 ISA,
605 /* 1 for intel mnemonic,
606 0 if att mnemonic. */
607 static int intel_mnemonic
= !SYSV386_COMPAT
;
609 /* 1 if pseudo registers are permitted. */
610 static int allow_pseudo_reg
= 0;
612 /* 1 if register prefix % not required. */
613 static int allow_naked_reg
= 0;
615 /* 1 if the assembler should add BND prefix for all control-transferring
616 instructions supporting it, even if this prefix wasn't specified
618 static int add_bnd_prefix
= 0;
620 /* 1 if pseudo index register, eiz/riz, is allowed . */
621 static int allow_index_reg
= 0;
623 /* 1 if the assembler should ignore LOCK prefix, even if it was
624 specified explicitly. */
625 static int omit_lock_prefix
= 0;
627 /* 1 if the assembler should encode lfence, mfence, and sfence as
628 "lock addl $0, (%{re}sp)". */
629 static int avoid_fence
= 0;
631 /* Type of the previous instruction. */
646 /* 1 if the assembler should generate relax relocations. */
648 static int generate_relax_relocations
649 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
651 static enum check_kind
657 sse_check
, operand_check
= check_warning
;
659 /* Non-zero if branches should be aligned within power of 2 boundary. */
660 static int align_branch_power
= 0;
662 /* Types of branches to align. */
663 enum align_branch_kind
665 align_branch_none
= 0,
666 align_branch_jcc
= 1,
667 align_branch_fused
= 2,
668 align_branch_jmp
= 3,
669 align_branch_call
= 4,
670 align_branch_indirect
= 5,
674 /* Type bits of branches to align. */
675 enum align_branch_bit
677 align_branch_jcc_bit
= 1 << align_branch_jcc
,
678 align_branch_fused_bit
= 1 << align_branch_fused
,
679 align_branch_jmp_bit
= 1 << align_branch_jmp
,
680 align_branch_call_bit
= 1 << align_branch_call
,
681 align_branch_indirect_bit
= 1 << align_branch_indirect
,
682 align_branch_ret_bit
= 1 << align_branch_ret
685 static unsigned int align_branch
= (align_branch_jcc_bit
686 | align_branch_fused_bit
687 | align_branch_jmp_bit
);
689 /* The maximum padding size for fused jcc. CMP like instruction can
690 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
692 #define MAX_FUSED_JCC_PADDING_SIZE 20
694 /* The maximum number of prefixes added for an instruction. */
695 static unsigned int align_branch_prefix_size
= 5;
698 1. Clear the REX_W bit with register operand if possible.
699 2. Above plus use 128bit vector instruction to clear the full vector
702 static int optimize
= 0;
705 1. Clear the REX_W bit with register operand if possible.
706 2. Above plus use 128bit vector instruction to clear the full vector
708 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
711 static int optimize_for_space
= 0;
713 /* Register prefix used for error message. */
714 static const char *register_prefix
= "%";
716 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
717 leave, push, and pop instructions so that gcc has the same stack
718 frame as in 32 bit mode. */
719 static char stackop_size
= '\0';
721 /* Non-zero to optimize code alignment. */
722 int optimize_align_code
= 1;
724 /* Non-zero to quieten some warnings. */
725 static int quiet_warnings
= 0;
728 static const char *cpu_arch_name
= NULL
;
729 static char *cpu_sub_arch_name
= NULL
;
731 /* CPU feature flags. */
732 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
734 /* If we have selected a cpu we are generating instructions for. */
735 static int cpu_arch_tune_set
= 0;
737 /* Cpu we are generating instructions for. */
738 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
740 /* CPU feature flags of cpu we are generating instructions for. */
741 static i386_cpu_flags cpu_arch_tune_flags
;
743 /* CPU instruction set architecture used. */
744 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
746 /* CPU feature flags of instruction set architecture used. */
747 i386_cpu_flags cpu_arch_isa_flags
;
749 /* If set, conditional jumps are not automatically promoted to handle
750 larger than a byte offset. */
751 static unsigned int no_cond_jump_promotion
= 0;
753 /* Encode SSE instructions with VEX prefix. */
754 static unsigned int sse2avx
;
756 /* Encode scalar AVX instructions with specific vector length. */
763 /* Encode VEX WIG instructions with specific vex.w. */
770 /* Encode scalar EVEX LIG instructions with specific vector length. */
778 /* Encode EVEX WIG instructions with specific evex.w. */
785 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
786 static enum rc_type evexrcig
= rne
;
788 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
789 static symbolS
*GOT_symbol
;
791 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
792 unsigned int x86_dwarf2_return_column
;
794 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
795 int x86_cie_data_alignment
;
797 /* Interface to relax_segment.
798 There are 3 major relax states for 386 jump insns because the
799 different types of jumps add different sizes to frags when we're
800 figuring out what sort of jump to choose to reach a given label.
802 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
803 branches which are handled by md_estimate_size_before_relax() and
804 i386_generic_table_relax_frag(). */
807 #define UNCOND_JUMP 0
809 #define COND_JUMP86 2
810 #define BRANCH_PADDING 3
811 #define BRANCH_PREFIX 4
812 #define FUSED_JCC_PADDING 5
817 #define SMALL16 (SMALL | CODE16)
819 #define BIG16 (BIG | CODE16)
823 #define INLINE __inline__
829 #define ENCODE_RELAX_STATE(type, size) \
830 ((relax_substateT) (((type) << 2) | (size)))
831 #define TYPE_FROM_RELAX_STATE(s) \
833 #define DISP_SIZE_FROM_RELAX_STATE(s) \
834 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
836 /* This table is used by relax_frag to promote short jumps to long
837 ones where necessary. SMALL (short) jumps may be promoted to BIG
838 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
839 don't allow a short jump in a 32 bit code segment to be promoted to
840 a 16 bit offset jump because it's slower (requires data size
841 prefix), and doesn't work, unless the destination is in the bottom
842 64k of the code segment (The top 16 bits of eip are zeroed). */
844 const relax_typeS md_relax_table
[] =
847 1) most positive reach of this state,
848 2) most negative reach of this state,
849 3) how many bytes this mode will have in the variable part of the frag
850 4) which index into the table to try if we can't fit into this one. */
852 /* UNCOND_JUMP states. */
853 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
854 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
855 /* dword jmp adds 4 bytes to frag:
856 0 extra opcode bytes, 4 displacement bytes. */
858 /* word jmp adds 2 byte2 to frag:
859 0 extra opcode bytes, 2 displacement bytes. */
862 /* COND_JUMP states. */
863 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
864 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
865 /* dword conditionals adds 5 bytes to frag:
866 1 extra opcode byte, 4 displacement bytes. */
868 /* word conditionals add 3 bytes to frag:
869 1 extra opcode byte, 2 displacement bytes. */
872 /* COND_JUMP86 states. */
873 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
874 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
875 /* dword conditionals adds 5 bytes to frag:
876 1 extra opcode byte, 4 displacement bytes. */
878 /* word conditionals add 4 bytes to frag:
879 1 displacement byte and a 3 byte long branch insn. */
883 static const arch_entry cpu_arch
[] =
885 /* Do not replace the first two entries - i386_target_format()
886 relies on them being there in this order. */
887 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
888 CPU_GENERIC32_FLAGS
, 0 },
889 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
890 CPU_GENERIC64_FLAGS
, 0 },
891 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
893 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
895 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
897 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
899 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
901 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
903 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
905 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
907 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
908 CPU_PENTIUMPRO_FLAGS
, 0 },
909 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
911 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
913 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
915 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
917 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
918 CPU_NOCONA_FLAGS
, 0 },
919 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
921 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
923 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
924 CPU_CORE2_FLAGS
, 1 },
925 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
926 CPU_CORE2_FLAGS
, 0 },
927 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
928 CPU_COREI7_FLAGS
, 0 },
929 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
931 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
933 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
934 CPU_IAMCU_FLAGS
, 0 },
935 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
937 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
939 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
940 CPU_ATHLON_FLAGS
, 0 },
941 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
943 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
945 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
947 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
948 CPU_AMDFAM10_FLAGS
, 0 },
949 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
950 CPU_BDVER1_FLAGS
, 0 },
951 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
952 CPU_BDVER2_FLAGS
, 0 },
953 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
954 CPU_BDVER3_FLAGS
, 0 },
955 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
956 CPU_BDVER4_FLAGS
, 0 },
957 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
958 CPU_ZNVER1_FLAGS
, 0 },
959 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
960 CPU_ZNVER2_FLAGS
, 0 },
961 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
962 CPU_BTVER1_FLAGS
, 0 },
963 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
964 CPU_BTVER2_FLAGS
, 0 },
965 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
967 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
969 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
971 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
973 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
975 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
977 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
979 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
981 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
983 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
985 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
986 CPU_SSSE3_FLAGS
, 0 },
987 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
988 CPU_SSE4_1_FLAGS
, 0 },
989 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
990 CPU_SSE4_2_FLAGS
, 0 },
991 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
992 CPU_SSE4_2_FLAGS
, 0 },
993 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
995 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
997 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
998 CPU_AVX512F_FLAGS
, 0 },
999 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1000 CPU_AVX512CD_FLAGS
, 0 },
1001 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1002 CPU_AVX512ER_FLAGS
, 0 },
1003 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1004 CPU_AVX512PF_FLAGS
, 0 },
1005 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1006 CPU_AVX512DQ_FLAGS
, 0 },
1007 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1008 CPU_AVX512BW_FLAGS
, 0 },
1009 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1010 CPU_AVX512VL_FLAGS
, 0 },
1011 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1013 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1014 CPU_VMFUNC_FLAGS
, 0 },
1015 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1017 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1018 CPU_XSAVE_FLAGS
, 0 },
1019 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1020 CPU_XSAVEOPT_FLAGS
, 0 },
1021 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1022 CPU_XSAVEC_FLAGS
, 0 },
1023 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1024 CPU_XSAVES_FLAGS
, 0 },
1025 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1027 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1028 CPU_PCLMUL_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1030 CPU_PCLMUL_FLAGS
, 1 },
1031 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1032 CPU_FSGSBASE_FLAGS
, 0 },
1033 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1034 CPU_RDRND_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1036 CPU_F16C_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1038 CPU_BMI2_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1041 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1042 CPU_FMA4_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1045 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1047 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1048 CPU_MOVBE_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1050 CPU_CX16_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1053 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1054 CPU_LZCNT_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1057 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1059 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1060 CPU_INVPCID_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1062 CPU_CLFLUSH_FLAGS
, 0 },
1063 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1065 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1066 CPU_SYSCALL_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1068 CPU_RDTSCP_FLAGS
, 0 },
1069 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1070 CPU_3DNOW_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1072 CPU_3DNOWA_FLAGS
, 0 },
1073 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1074 CPU_PADLOCK_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1076 CPU_SVME_FLAGS
, 1 },
1077 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1078 CPU_SVME_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1080 CPU_SSE4A_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1083 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1085 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1087 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1089 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1090 CPU_RDSEED_FLAGS
, 0 },
1091 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1092 CPU_PRFCHW_FLAGS
, 0 },
1093 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1094 CPU_SMAP_FLAGS
, 0 },
1095 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1097 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1099 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1100 CPU_CLFLUSHOPT_FLAGS
, 0 },
1101 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1102 CPU_PREFETCHWT1_FLAGS
, 0 },
1103 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1105 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1106 CPU_CLWB_FLAGS
, 0 },
1107 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1108 CPU_AVX512IFMA_FLAGS
, 0 },
1109 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1110 CPU_AVX512VBMI_FLAGS
, 0 },
1111 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1112 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1113 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1114 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1115 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1116 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1117 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1118 CPU_AVX512_VBMI2_FLAGS
, 0 },
1119 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1120 CPU_AVX512_VNNI_FLAGS
, 0 },
1121 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1122 CPU_AVX512_BITALG_FLAGS
, 0 },
1123 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1124 CPU_CLZERO_FLAGS
, 0 },
1125 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1126 CPU_MWAITX_FLAGS
, 0 },
1127 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1128 CPU_OSPKE_FLAGS
, 0 },
1129 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1130 CPU_RDPID_FLAGS
, 0 },
1131 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1132 CPU_PTWRITE_FLAGS
, 0 },
1133 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1135 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1136 CPU_SHSTK_FLAGS
, 0 },
1137 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1138 CPU_GFNI_FLAGS
, 0 },
1139 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1140 CPU_VAES_FLAGS
, 0 },
1141 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1142 CPU_VPCLMULQDQ_FLAGS
, 0 },
1143 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1144 CPU_WBNOINVD_FLAGS
, 0 },
1145 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1146 CPU_PCONFIG_FLAGS
, 0 },
1147 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1148 CPU_WAITPKG_FLAGS
, 0 },
1149 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1150 CPU_CLDEMOTE_FLAGS
, 0 },
1151 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1152 CPU_MOVDIRI_FLAGS
, 0 },
1153 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1154 CPU_MOVDIR64B_FLAGS
, 0 },
1155 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1156 CPU_AVX512_BF16_FLAGS
, 0 },
1157 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1158 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1159 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1160 CPU_ENQCMD_FLAGS
, 0 },
1161 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1162 CPU_RDPRU_FLAGS
, 0 },
1163 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1164 CPU_MCOMMIT_FLAGS
, 0 },
1167 static const noarch_entry cpu_noarch
[] =
1169 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1170 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1171 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1172 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1173 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1174 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1175 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1176 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1177 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1178 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1179 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1180 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1181 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1182 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1183 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1184 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1185 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1186 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1187 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1188 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1189 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1190 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1191 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1192 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1193 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1194 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1195 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1196 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1197 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1198 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1199 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1200 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1201 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1202 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1203 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1204 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1205 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1206 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1210 /* Like s_lcomm_internal in gas/read.c but the alignment string
1211 is allowed to be optional. */
1214 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1221 && *input_line_pointer
== ',')
1223 align
= parse_align (needs_align
- 1);
1225 if (align
== (addressT
) -1)
1240 bss_alloc (symbolP
, size
, align
);
1245 pe_lcomm (int needs_align
)
1247 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1251 const pseudo_typeS md_pseudo_table
[] =
1253 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1254 {"align", s_align_bytes
, 0},
1256 {"align", s_align_ptwo
, 0},
1258 {"arch", set_cpu_arch
, 0},
1262 {"lcomm", pe_lcomm
, 1},
1264 {"ffloat", float_cons
, 'f'},
1265 {"dfloat", float_cons
, 'd'},
1266 {"tfloat", float_cons
, 'x'},
1268 {"slong", signed_cons
, 4},
1269 {"noopt", s_ignore
, 0},
1270 {"optim", s_ignore
, 0},
1271 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1272 {"code16", set_code_flag
, CODE_16BIT
},
1273 {"code32", set_code_flag
, CODE_32BIT
},
1275 {"code64", set_code_flag
, CODE_64BIT
},
1277 {"intel_syntax", set_intel_syntax
, 1},
1278 {"att_syntax", set_intel_syntax
, 0},
1279 {"intel_mnemonic", set_intel_mnemonic
, 1},
1280 {"att_mnemonic", set_intel_mnemonic
, 0},
1281 {"allow_index_reg", set_allow_index_reg
, 1},
1282 {"disallow_index_reg", set_allow_index_reg
, 0},
1283 {"sse_check", set_check
, 0},
1284 {"operand_check", set_check
, 1},
1285 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1286 {"largecomm", handle_large_common
, 0},
1288 {"file", dwarf2_directive_file
, 0},
1289 {"loc", dwarf2_directive_loc
, 0},
1290 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1293 {"secrel32", pe_directive_secrel
, 0},
1298 /* For interface with expression (). */
1299 extern char *input_line_pointer
;
1301 /* Hash table for instruction mnemonic lookup. */
1302 static struct hash_control
*op_hash
;
1304 /* Hash table for register lookup. */
1305 static struct hash_control
*reg_hash
;
1307 /* Various efficient no-op patterns for aligning code labels.
1308 Note: Don't try to assemble the instructions in the comments.
1309 0L and 0w are not legal. */
1310 static const unsigned char f32_1
[] =
1312 static const unsigned char f32_2
[] =
1313 {0x66,0x90}; /* xchg %ax,%ax */
1314 static const unsigned char f32_3
[] =
1315 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1316 static const unsigned char f32_4
[] =
1317 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1318 static const unsigned char f32_6
[] =
1319 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1320 static const unsigned char f32_7
[] =
1321 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1322 static const unsigned char f16_3
[] =
1323 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1324 static const unsigned char f16_4
[] =
1325 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1326 static const unsigned char jump_disp8
[] =
1327 {0xeb}; /* jmp disp8 */
1328 static const unsigned char jump32_disp32
[] =
1329 {0xe9}; /* jmp disp32 */
1330 static const unsigned char jump16_disp32
[] =
1331 {0x66,0xe9}; /* jmp disp32 */
1332 /* 32-bit NOPs patterns. */
1333 static const unsigned char *const f32_patt
[] = {
1334 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1336 /* 16-bit NOPs patterns. */
1337 static const unsigned char *const f16_patt
[] = {
1338 f32_1
, f32_2
, f16_3
, f16_4
1340 /* nopl (%[re]ax) */
1341 static const unsigned char alt_3
[] =
1343 /* nopl 0(%[re]ax) */
1344 static const unsigned char alt_4
[] =
1345 {0x0f,0x1f,0x40,0x00};
1346 /* nopl 0(%[re]ax,%[re]ax,1) */
1347 static const unsigned char alt_5
[] =
1348 {0x0f,0x1f,0x44,0x00,0x00};
1349 /* nopw 0(%[re]ax,%[re]ax,1) */
1350 static const unsigned char alt_6
[] =
1351 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1352 /* nopl 0L(%[re]ax) */
1353 static const unsigned char alt_7
[] =
1354 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1355 /* nopl 0L(%[re]ax,%[re]ax,1) */
1356 static const unsigned char alt_8
[] =
1357 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1358 /* nopw 0L(%[re]ax,%[re]ax,1) */
1359 static const unsigned char alt_9
[] =
1360 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1361 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1362 static const unsigned char alt_10
[] =
1363 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1364 /* data16 nopw %cs:0L(%eax,%eax,1) */
1365 static const unsigned char alt_11
[] =
1366 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1367 /* 32-bit and 64-bit NOPs patterns. */
1368 static const unsigned char *const alt_patt
[] = {
1369 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1370 alt_9
, alt_10
, alt_11
1373 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1374 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1377 i386_output_nops (char *where
, const unsigned char *const *patt
,
1378 int count
, int max_single_nop_size
)
1381 /* Place the longer NOP first. */
1384 const unsigned char *nops
;
1386 if (max_single_nop_size
< 1)
1388 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1389 max_single_nop_size
);
1393 nops
= patt
[max_single_nop_size
- 1];
1395 /* Use the smaller one if the requsted one isn't available. */
1398 max_single_nop_size
--;
1399 nops
= patt
[max_single_nop_size
- 1];
1402 last
= count
% max_single_nop_size
;
1405 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1406 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1410 nops
= patt
[last
- 1];
1413 /* Use the smaller one plus one-byte NOP if the needed one
1416 nops
= patt
[last
- 1];
1417 memcpy (where
+ offset
, nops
, last
);
1418 where
[offset
+ last
] = *patt
[0];
1421 memcpy (where
+ offset
, nops
, last
);
1426 fits_in_imm7 (offsetT num
)
1428 return (num
& 0x7f) == num
;
1432 fits_in_imm31 (offsetT num
)
1434 return (num
& 0x7fffffff) == num
;
1437 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1438 single NOP instruction LIMIT. */
1441 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1443 const unsigned char *const *patt
= NULL
;
1444 int max_single_nop_size
;
1445 /* Maximum number of NOPs before switching to jump over NOPs. */
1446 int max_number_of_nops
;
1448 switch (fragP
->fr_type
)
1453 case rs_machine_dependent
:
1454 /* Allow NOP padding for jumps and calls. */
1455 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1456 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1463 /* We need to decide which NOP sequence to use for 32bit and
1464 64bit. When -mtune= is used:
1466 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1467 PROCESSOR_GENERIC32, f32_patt will be used.
1468 2. For the rest, alt_patt will be used.
1470 When -mtune= isn't used, alt_patt will be used if
1471 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1474 When -march= or .arch is used, we can't use anything beyond
1475 cpu_arch_isa_flags. */
1477 if (flag_code
== CODE_16BIT
)
1480 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1481 /* Limit number of NOPs to 2 in 16-bit mode. */
1482 max_number_of_nops
= 2;
1486 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1488 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1489 switch (cpu_arch_tune
)
1491 case PROCESSOR_UNKNOWN
:
1492 /* We use cpu_arch_isa_flags to check if we SHOULD
1493 optimize with nops. */
1494 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1499 case PROCESSOR_PENTIUM4
:
1500 case PROCESSOR_NOCONA
:
1501 case PROCESSOR_CORE
:
1502 case PROCESSOR_CORE2
:
1503 case PROCESSOR_COREI7
:
1504 case PROCESSOR_L1OM
:
1505 case PROCESSOR_K1OM
:
1506 case PROCESSOR_GENERIC64
:
1508 case PROCESSOR_ATHLON
:
1510 case PROCESSOR_AMDFAM10
:
1512 case PROCESSOR_ZNVER
:
1516 case PROCESSOR_I386
:
1517 case PROCESSOR_I486
:
1518 case PROCESSOR_PENTIUM
:
1519 case PROCESSOR_PENTIUMPRO
:
1520 case PROCESSOR_IAMCU
:
1521 case PROCESSOR_GENERIC32
:
1528 switch (fragP
->tc_frag_data
.tune
)
1530 case PROCESSOR_UNKNOWN
:
1531 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1532 PROCESSOR_UNKNOWN. */
1536 case PROCESSOR_I386
:
1537 case PROCESSOR_I486
:
1538 case PROCESSOR_PENTIUM
:
1539 case PROCESSOR_IAMCU
:
1541 case PROCESSOR_ATHLON
:
1543 case PROCESSOR_AMDFAM10
:
1545 case PROCESSOR_ZNVER
:
1547 case PROCESSOR_GENERIC32
:
1548 /* We use cpu_arch_isa_flags to check if we CAN optimize
1550 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1555 case PROCESSOR_PENTIUMPRO
:
1556 case PROCESSOR_PENTIUM4
:
1557 case PROCESSOR_NOCONA
:
1558 case PROCESSOR_CORE
:
1559 case PROCESSOR_CORE2
:
1560 case PROCESSOR_COREI7
:
1561 case PROCESSOR_L1OM
:
1562 case PROCESSOR_K1OM
:
1563 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1568 case PROCESSOR_GENERIC64
:
1574 if (patt
== f32_patt
)
1576 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1577 /* Limit number of NOPs to 2 for older processors. */
1578 max_number_of_nops
= 2;
1582 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1583 /* Limit number of NOPs to 7 for newer processors. */
1584 max_number_of_nops
= 7;
1589 limit
= max_single_nop_size
;
1591 if (fragP
->fr_type
== rs_fill_nop
)
1593 /* Output NOPs for .nop directive. */
1594 if (limit
> max_single_nop_size
)
1596 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1597 _("invalid single nop size: %d "
1598 "(expect within [0, %d])"),
1599 limit
, max_single_nop_size
);
1603 else if (fragP
->fr_type
!= rs_machine_dependent
)
1604 fragP
->fr_var
= count
;
1606 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1608 /* Generate jump over NOPs. */
1609 offsetT disp
= count
- 2;
1610 if (fits_in_imm7 (disp
))
1612 /* Use "jmp disp8" if possible. */
1614 where
[0] = jump_disp8
[0];
1620 unsigned int size_of_jump
;
1622 if (flag_code
== CODE_16BIT
)
1624 where
[0] = jump16_disp32
[0];
1625 where
[1] = jump16_disp32
[1];
1630 where
[0] = jump32_disp32
[0];
1634 count
-= size_of_jump
+ 4;
1635 if (!fits_in_imm31 (count
))
1637 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1638 _("jump over nop padding out of range"));
1642 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1643 where
+= size_of_jump
+ 4;
1647 /* Generate multiple NOPs. */
1648 i386_output_nops (where
, patt
, count
, limit
);
1652 operand_type_all_zero (const union i386_operand_type
*x
)
1654 switch (ARRAY_SIZE(x
->array
))
1665 return !x
->array
[0];
1672 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1674 switch (ARRAY_SIZE(x
->array
))
1690 x
->bitfield
.class = ClassNone
;
1691 x
->bitfield
.instance
= InstanceNone
;
1695 operand_type_equal (const union i386_operand_type
*x
,
1696 const union i386_operand_type
*y
)
1698 switch (ARRAY_SIZE(x
->array
))
1701 if (x
->array
[2] != y
->array
[2])
1705 if (x
->array
[1] != y
->array
[1])
1709 return x
->array
[0] == y
->array
[0];
1717 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1719 switch (ARRAY_SIZE(x
->array
))
1734 return !x
->array
[0];
1741 cpu_flags_equal (const union i386_cpu_flags
*x
,
1742 const union i386_cpu_flags
*y
)
1744 switch (ARRAY_SIZE(x
->array
))
1747 if (x
->array
[3] != y
->array
[3])
1751 if (x
->array
[2] != y
->array
[2])
1755 if (x
->array
[1] != y
->array
[1])
1759 return x
->array
[0] == y
->array
[0];
1767 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1769 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1770 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1773 static INLINE i386_cpu_flags
1774 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1776 switch (ARRAY_SIZE (x
.array
))
1779 x
.array
[3] &= y
.array
[3];
1782 x
.array
[2] &= y
.array
[2];
1785 x
.array
[1] &= y
.array
[1];
1788 x
.array
[0] &= y
.array
[0];
1796 static INLINE i386_cpu_flags
1797 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1799 switch (ARRAY_SIZE (x
.array
))
1802 x
.array
[3] |= y
.array
[3];
1805 x
.array
[2] |= y
.array
[2];
1808 x
.array
[1] |= y
.array
[1];
1811 x
.array
[0] |= y
.array
[0];
1819 static INLINE i386_cpu_flags
1820 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1822 switch (ARRAY_SIZE (x
.array
))
1825 x
.array
[3] &= ~y
.array
[3];
1828 x
.array
[2] &= ~y
.array
[2];
1831 x
.array
[1] &= ~y
.array
[1];
1834 x
.array
[0] &= ~y
.array
[0];
1842 #define CPU_FLAGS_ARCH_MATCH 0x1
1843 #define CPU_FLAGS_64BIT_MATCH 0x2
1845 #define CPU_FLAGS_PERFECT_MATCH \
1846 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1848 /* Return CPU flags match bits. */
1851 cpu_flags_match (const insn_template
*t
)
1853 i386_cpu_flags x
= t
->cpu_flags
;
1854 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1856 x
.bitfield
.cpu64
= 0;
1857 x
.bitfield
.cpuno64
= 0;
1859 if (cpu_flags_all_zero (&x
))
1861 /* This instruction is available on all archs. */
1862 match
|= CPU_FLAGS_ARCH_MATCH
;
1866 /* This instruction is available only on some archs. */
1867 i386_cpu_flags cpu
= cpu_arch_flags
;
1869 /* AVX512VL is no standalone feature - match it and then strip it. */
1870 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1872 x
.bitfield
.cpuavx512vl
= 0;
1874 cpu
= cpu_flags_and (x
, cpu
);
1875 if (!cpu_flags_all_zero (&cpu
))
1877 if (x
.bitfield
.cpuavx
)
1879 /* We need to check a few extra flags with AVX. */
1880 if (cpu
.bitfield
.cpuavx
1881 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1882 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1883 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1884 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1885 match
|= CPU_FLAGS_ARCH_MATCH
;
1887 else if (x
.bitfield
.cpuavx512f
)
1889 /* We need to check a few extra flags with AVX512F. */
1890 if (cpu
.bitfield
.cpuavx512f
1891 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1892 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1893 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1894 match
|= CPU_FLAGS_ARCH_MATCH
;
1897 match
|= CPU_FLAGS_ARCH_MATCH
;
1903 static INLINE i386_operand_type
1904 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1906 if (x
.bitfield
.class != y
.bitfield
.class)
1907 x
.bitfield
.class = ClassNone
;
1908 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1909 x
.bitfield
.instance
= InstanceNone
;
1911 switch (ARRAY_SIZE (x
.array
))
1914 x
.array
[2] &= y
.array
[2];
1917 x
.array
[1] &= y
.array
[1];
1920 x
.array
[0] &= y
.array
[0];
1928 static INLINE i386_operand_type
1929 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1931 gas_assert (y
.bitfield
.class == ClassNone
);
1932 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1934 switch (ARRAY_SIZE (x
.array
))
1937 x
.array
[2] &= ~y
.array
[2];
1940 x
.array
[1] &= ~y
.array
[1];
1943 x
.array
[0] &= ~y
.array
[0];
1951 static INLINE i386_operand_type
1952 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1954 gas_assert (x
.bitfield
.class == ClassNone
||
1955 y
.bitfield
.class == ClassNone
||
1956 x
.bitfield
.class == y
.bitfield
.class);
1957 gas_assert (x
.bitfield
.instance
== InstanceNone
||
1958 y
.bitfield
.instance
== InstanceNone
||
1959 x
.bitfield
.instance
== y
.bitfield
.instance
);
1961 switch (ARRAY_SIZE (x
.array
))
1964 x
.array
[2] |= y
.array
[2];
1967 x
.array
[1] |= y
.array
[1];
1970 x
.array
[0] |= y
.array
[0];
1978 static INLINE i386_operand_type
1979 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1981 gas_assert (y
.bitfield
.class == ClassNone
);
1982 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1984 switch (ARRAY_SIZE (x
.array
))
1987 x
.array
[2] ^= y
.array
[2];
1990 x
.array
[1] ^= y
.array
[1];
1993 x
.array
[0] ^= y
.array
[0];
2001 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2002 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2003 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2004 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2005 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2006 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2007 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2008 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2009 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2010 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2011 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2012 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2013 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2014 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2015 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2016 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2017 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2028 operand_type_check (i386_operand_type t
, enum operand_type c
)
2033 return t
.bitfield
.class == Reg
;
2036 return (t
.bitfield
.imm8
2040 || t
.bitfield
.imm32s
2041 || t
.bitfield
.imm64
);
2044 return (t
.bitfield
.disp8
2045 || t
.bitfield
.disp16
2046 || t
.bitfield
.disp32
2047 || t
.bitfield
.disp32s
2048 || t
.bitfield
.disp64
);
2051 return (t
.bitfield
.disp8
2052 || t
.bitfield
.disp16
2053 || t
.bitfield
.disp32
2054 || t
.bitfield
.disp32s
2055 || t
.bitfield
.disp64
2056 || t
.bitfield
.baseindex
);
2065 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2066 between operand GIVEN and opeand WANTED for instruction template T. */
2069 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2072 return !((i
.types
[given
].bitfield
.byte
2073 && !t
->operand_types
[wanted
].bitfield
.byte
)
2074 || (i
.types
[given
].bitfield
.word
2075 && !t
->operand_types
[wanted
].bitfield
.word
)
2076 || (i
.types
[given
].bitfield
.dword
2077 && !t
->operand_types
[wanted
].bitfield
.dword
)
2078 || (i
.types
[given
].bitfield
.qword
2079 && !t
->operand_types
[wanted
].bitfield
.qword
)
2080 || (i
.types
[given
].bitfield
.tbyte
2081 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2084 /* Return 1 if there is no conflict in SIMD register between operand
2085 GIVEN and opeand WANTED for instruction template T. */
2088 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2091 return !((i
.types
[given
].bitfield
.xmmword
2092 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2093 || (i
.types
[given
].bitfield
.ymmword
2094 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2095 || (i
.types
[given
].bitfield
.zmmword
2096 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2099 /* Return 1 if there is no conflict in any size between operand GIVEN
2100 and opeand WANTED for instruction template T. */
2103 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2106 return (match_operand_size (t
, wanted
, given
)
2107 && !((i
.types
[given
].bitfield
.unspecified
2109 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2110 || (i
.types
[given
].bitfield
.fword
2111 && !t
->operand_types
[wanted
].bitfield
.fword
)
2112 /* For scalar opcode templates to allow register and memory
2113 operands at the same time, some special casing is needed
2114 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2115 down-conversion vpmov*. */
2116 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2117 && !t
->opcode_modifier
.broadcast
2118 && (t
->operand_types
[wanted
].bitfield
.byte
2119 || t
->operand_types
[wanted
].bitfield
.word
2120 || t
->operand_types
[wanted
].bitfield
.dword
2121 || t
->operand_types
[wanted
].bitfield
.qword
))
2122 ? (i
.types
[given
].bitfield
.xmmword
2123 || i
.types
[given
].bitfield
.ymmword
2124 || i
.types
[given
].bitfield
.zmmword
)
2125 : !match_simd_size(t
, wanted
, given
))));
2128 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2129 operands for instruction template T, and it has MATCH_REVERSE set if there
2130 is no size conflict on any operands for the template with operands reversed
2131 (and the template allows for reversing in the first place). */
2133 #define MATCH_STRAIGHT 1
2134 #define MATCH_REVERSE 2
2136 static INLINE
unsigned int
2137 operand_size_match (const insn_template
*t
)
2139 unsigned int j
, match
= MATCH_STRAIGHT
;
2141 /* Don't check non-absolute jump instructions. */
2142 if (t
->opcode_modifier
.jump
2143 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2146 /* Check memory and accumulator operand size. */
2147 for (j
= 0; j
< i
.operands
; j
++)
2149 if (i
.types
[j
].bitfield
.class != Reg
2150 && i
.types
[j
].bitfield
.class != RegSIMD
2151 && t
->opcode_modifier
.anysize
)
2154 if (t
->operand_types
[j
].bitfield
.class == Reg
2155 && !match_operand_size (t
, j
, j
))
2161 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2162 && !match_simd_size (t
, j
, j
))
2168 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2169 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2175 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2182 if (!t
->opcode_modifier
.d
)
2186 i
.error
= operand_size_mismatch
;
2190 /* Check reverse. */
2191 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2193 for (j
= 0; j
< i
.operands
; j
++)
2195 unsigned int given
= i
.operands
- j
- 1;
2197 if (t
->operand_types
[j
].bitfield
.class == Reg
2198 && !match_operand_size (t
, j
, given
))
2201 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2202 && !match_simd_size (t
, j
, given
))
2205 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2206 && (!match_operand_size (t
, j
, given
)
2207 || !match_simd_size (t
, j
, given
)))
2210 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2214 return match
| MATCH_REVERSE
;
2218 operand_type_match (i386_operand_type overlap
,
2219 i386_operand_type given
)
2221 i386_operand_type temp
= overlap
;
2223 temp
.bitfield
.unspecified
= 0;
2224 temp
.bitfield
.byte
= 0;
2225 temp
.bitfield
.word
= 0;
2226 temp
.bitfield
.dword
= 0;
2227 temp
.bitfield
.fword
= 0;
2228 temp
.bitfield
.qword
= 0;
2229 temp
.bitfield
.tbyte
= 0;
2230 temp
.bitfield
.xmmword
= 0;
2231 temp
.bitfield
.ymmword
= 0;
2232 temp
.bitfield
.zmmword
= 0;
2233 if (operand_type_all_zero (&temp
))
2236 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2240 i
.error
= operand_type_mismatch
;
2244 /* If given types g0 and g1 are registers they must be of the same type
2245 unless the expected operand type register overlap is null.
2246 Memory operand size of certain SIMD instructions is also being checked
2250 operand_type_register_match (i386_operand_type g0
,
2251 i386_operand_type t0
,
2252 i386_operand_type g1
,
2253 i386_operand_type t1
)
2255 if (g0
.bitfield
.class != Reg
2256 && g0
.bitfield
.class != RegSIMD
2257 && (!operand_type_check (g0
, anymem
)
2258 || g0
.bitfield
.unspecified
2259 || t0
.bitfield
.class != RegSIMD
))
2262 if (g1
.bitfield
.class != Reg
2263 && g1
.bitfield
.class != RegSIMD
2264 && (!operand_type_check (g1
, anymem
)
2265 || g1
.bitfield
.unspecified
2266 || t1
.bitfield
.class != RegSIMD
))
2269 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2270 && g0
.bitfield
.word
== g1
.bitfield
.word
2271 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2272 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2273 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2274 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2275 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2278 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2279 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2280 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2281 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2282 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2283 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2284 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2287 i
.error
= register_type_mismatch
;
2292 static INLINE
unsigned int
2293 register_number (const reg_entry
*r
)
2295 unsigned int nr
= r
->reg_num
;
2297 if (r
->reg_flags
& RegRex
)
2300 if (r
->reg_flags
& RegVRex
)
2306 static INLINE
unsigned int
2307 mode_from_disp_size (i386_operand_type t
)
2309 if (t
.bitfield
.disp8
)
2311 else if (t
.bitfield
.disp16
2312 || t
.bitfield
.disp32
2313 || t
.bitfield
.disp32s
)
2320 fits_in_signed_byte (addressT num
)
2322 return num
+ 0x80 <= 0xff;
2326 fits_in_unsigned_byte (addressT num
)
2332 fits_in_unsigned_word (addressT num
)
2334 return num
<= 0xffff;
2338 fits_in_signed_word (addressT num
)
2340 return num
+ 0x8000 <= 0xffff;
2344 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2349 return num
+ 0x80000000 <= 0xffffffff;
2351 } /* fits_in_signed_long() */
2354 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2359 return num
<= 0xffffffff;
2361 } /* fits_in_unsigned_long() */
2364 fits_in_disp8 (offsetT num
)
2366 int shift
= i
.memshift
;
2372 mask
= (1 << shift
) - 1;
2374 /* Return 0 if NUM isn't properly aligned. */
2378 /* Check if NUM will fit in 8bit after shift. */
2379 return fits_in_signed_byte (num
>> shift
);
2383 fits_in_imm4 (offsetT num
)
2385 return (num
& 0xf) == num
;
2388 static i386_operand_type
2389 smallest_imm_type (offsetT num
)
2391 i386_operand_type t
;
2393 operand_type_set (&t
, 0);
2394 t
.bitfield
.imm64
= 1;
2396 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2398 /* This code is disabled on the 486 because all the Imm1 forms
2399 in the opcode table are slower on the i486. They're the
2400 versions with the implicitly specified single-position
2401 displacement, which has another syntax if you really want to
2403 t
.bitfield
.imm1
= 1;
2404 t
.bitfield
.imm8
= 1;
2405 t
.bitfield
.imm8s
= 1;
2406 t
.bitfield
.imm16
= 1;
2407 t
.bitfield
.imm32
= 1;
2408 t
.bitfield
.imm32s
= 1;
2410 else if (fits_in_signed_byte (num
))
2412 t
.bitfield
.imm8
= 1;
2413 t
.bitfield
.imm8s
= 1;
2414 t
.bitfield
.imm16
= 1;
2415 t
.bitfield
.imm32
= 1;
2416 t
.bitfield
.imm32s
= 1;
2418 else if (fits_in_unsigned_byte (num
))
2420 t
.bitfield
.imm8
= 1;
2421 t
.bitfield
.imm16
= 1;
2422 t
.bitfield
.imm32
= 1;
2423 t
.bitfield
.imm32s
= 1;
2425 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2427 t
.bitfield
.imm16
= 1;
2428 t
.bitfield
.imm32
= 1;
2429 t
.bitfield
.imm32s
= 1;
2431 else if (fits_in_signed_long (num
))
2433 t
.bitfield
.imm32
= 1;
2434 t
.bitfield
.imm32s
= 1;
2436 else if (fits_in_unsigned_long (num
))
2437 t
.bitfield
.imm32
= 1;
2443 offset_in_range (offsetT val
, int size
)
2449 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2450 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2451 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2453 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2459 /* If BFD64, sign extend val for 32bit address mode. */
2460 if (flag_code
!= CODE_64BIT
2461 || i
.prefix
[ADDR_PREFIX
])
2462 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2463 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2466 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2468 char buf1
[40], buf2
[40];
2470 sprint_value (buf1
, val
);
2471 sprint_value (buf2
, val
& mask
);
2472 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2487 a. PREFIX_EXIST if attempting to add a prefix where one from the
2488 same class already exists.
2489 b. PREFIX_LOCK if lock prefix is added.
2490 c. PREFIX_REP if rep/repne prefix is added.
2491 d. PREFIX_DS if ds prefix is added.
2492 e. PREFIX_OTHER if other prefix is added.
2495 static enum PREFIX_GROUP
2496 add_prefix (unsigned int prefix
)
2498 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2501 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2502 && flag_code
== CODE_64BIT
)
2504 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2505 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2506 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2507 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2518 case DS_PREFIX_OPCODE
:
2521 case CS_PREFIX_OPCODE
:
2522 case ES_PREFIX_OPCODE
:
2523 case FS_PREFIX_OPCODE
:
2524 case GS_PREFIX_OPCODE
:
2525 case SS_PREFIX_OPCODE
:
2529 case REPNE_PREFIX_OPCODE
:
2530 case REPE_PREFIX_OPCODE
:
2535 case LOCK_PREFIX_OPCODE
:
2544 case ADDR_PREFIX_OPCODE
:
2548 case DATA_PREFIX_OPCODE
:
2552 if (i
.prefix
[q
] != 0)
2560 i
.prefix
[q
] |= prefix
;
2563 as_bad (_("same type of prefix used twice"));
2569 update_code_flag (int value
, int check
)
2571 PRINTF_LIKE ((*as_error
));
2573 flag_code
= (enum flag_code
) value
;
2574 if (flag_code
== CODE_64BIT
)
2576 cpu_arch_flags
.bitfield
.cpu64
= 1;
2577 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2581 cpu_arch_flags
.bitfield
.cpu64
= 0;
2582 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2584 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2587 as_error
= as_fatal
;
2590 (*as_error
) (_("64bit mode not supported on `%s'."),
2591 cpu_arch_name
? cpu_arch_name
: default_arch
);
2593 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2596 as_error
= as_fatal
;
2599 (*as_error
) (_("32bit mode not supported on `%s'."),
2600 cpu_arch_name
? cpu_arch_name
: default_arch
);
2602 stackop_size
= '\0';
2606 set_code_flag (int value
)
2608 update_code_flag (value
, 0);
2612 set_16bit_gcc_code_flag (int new_code_flag
)
2614 flag_code
= (enum flag_code
) new_code_flag
;
2615 if (flag_code
!= CODE_16BIT
)
2617 cpu_arch_flags
.bitfield
.cpu64
= 0;
2618 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2619 stackop_size
= LONG_MNEM_SUFFIX
;
2623 set_intel_syntax (int syntax_flag
)
2625 /* Find out if register prefixing is specified. */
2626 int ask_naked_reg
= 0;
2629 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2632 int e
= get_symbol_name (&string
);
2634 if (strcmp (string
, "prefix") == 0)
2636 else if (strcmp (string
, "noprefix") == 0)
2639 as_bad (_("bad argument to syntax directive."));
2640 (void) restore_line_pointer (e
);
2642 demand_empty_rest_of_line ();
2644 intel_syntax
= syntax_flag
;
2646 if (ask_naked_reg
== 0)
2647 allow_naked_reg
= (intel_syntax
2648 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2650 allow_naked_reg
= (ask_naked_reg
< 0);
2652 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2654 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2655 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2656 register_prefix
= allow_naked_reg
? "" : "%";
2660 set_intel_mnemonic (int mnemonic_flag
)
2662 intel_mnemonic
= mnemonic_flag
;
2666 set_allow_index_reg (int flag
)
2668 allow_index_reg
= flag
;
2672 set_check (int what
)
2674 enum check_kind
*kind
;
2679 kind
= &operand_check
;
2690 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2693 int e
= get_symbol_name (&string
);
2695 if (strcmp (string
, "none") == 0)
2697 else if (strcmp (string
, "warning") == 0)
2698 *kind
= check_warning
;
2699 else if (strcmp (string
, "error") == 0)
2700 *kind
= check_error
;
2702 as_bad (_("bad argument to %s_check directive."), str
);
2703 (void) restore_line_pointer (e
);
2706 as_bad (_("missing argument for %s_check directive"), str
);
2708 demand_empty_rest_of_line ();
2712 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2713 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2715 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2716 static const char *arch
;
2718 /* Intel LIOM is only supported on ELF. */
2724 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2725 use default_arch. */
2726 arch
= cpu_arch_name
;
2728 arch
= default_arch
;
2731 /* If we are targeting Intel MCU, we must enable it. */
2732 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2733 || new_flag
.bitfield
.cpuiamcu
)
2736 /* If we are targeting Intel L1OM, we must enable it. */
2737 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2738 || new_flag
.bitfield
.cpul1om
)
2741 /* If we are targeting Intel K1OM, we must enable it. */
2742 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2743 || new_flag
.bitfield
.cpuk1om
)
2746 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2751 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2755 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2758 int e
= get_symbol_name (&string
);
2760 i386_cpu_flags flags
;
2762 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2764 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2766 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2770 cpu_arch_name
= cpu_arch
[j
].name
;
2771 cpu_sub_arch_name
= NULL
;
2772 cpu_arch_flags
= cpu_arch
[j
].flags
;
2773 if (flag_code
== CODE_64BIT
)
2775 cpu_arch_flags
.bitfield
.cpu64
= 1;
2776 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2780 cpu_arch_flags
.bitfield
.cpu64
= 0;
2781 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2783 cpu_arch_isa
= cpu_arch
[j
].type
;
2784 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2785 if (!cpu_arch_tune_set
)
2787 cpu_arch_tune
= cpu_arch_isa
;
2788 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2793 flags
= cpu_flags_or (cpu_arch_flags
,
2796 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2798 if (cpu_sub_arch_name
)
2800 char *name
= cpu_sub_arch_name
;
2801 cpu_sub_arch_name
= concat (name
,
2803 (const char *) NULL
);
2807 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2808 cpu_arch_flags
= flags
;
2809 cpu_arch_isa_flags
= flags
;
2813 = cpu_flags_or (cpu_arch_isa_flags
,
2815 (void) restore_line_pointer (e
);
2816 demand_empty_rest_of_line ();
2821 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2823 /* Disable an ISA extension. */
2824 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2825 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2827 flags
= cpu_flags_and_not (cpu_arch_flags
,
2828 cpu_noarch
[j
].flags
);
2829 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2831 if (cpu_sub_arch_name
)
2833 char *name
= cpu_sub_arch_name
;
2834 cpu_sub_arch_name
= concat (name
, string
,
2835 (const char *) NULL
);
2839 cpu_sub_arch_name
= xstrdup (string
);
2840 cpu_arch_flags
= flags
;
2841 cpu_arch_isa_flags
= flags
;
2843 (void) restore_line_pointer (e
);
2844 demand_empty_rest_of_line ();
2848 j
= ARRAY_SIZE (cpu_arch
);
2851 if (j
>= ARRAY_SIZE (cpu_arch
))
2852 as_bad (_("no such architecture: `%s'"), string
);
2854 *input_line_pointer
= e
;
2857 as_bad (_("missing cpu architecture"));
2859 no_cond_jump_promotion
= 0;
2860 if (*input_line_pointer
== ','
2861 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2866 ++input_line_pointer
;
2867 e
= get_symbol_name (&string
);
2869 if (strcmp (string
, "nojumps") == 0)
2870 no_cond_jump_promotion
= 1;
2871 else if (strcmp (string
, "jumps") == 0)
2874 as_bad (_("no such architecture modifier: `%s'"), string
);
2876 (void) restore_line_pointer (e
);
2879 demand_empty_rest_of_line ();
2882 enum bfd_architecture
2885 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2887 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2888 || flag_code
!= CODE_64BIT
)
2889 as_fatal (_("Intel L1OM is 64bit ELF only"));
2890 return bfd_arch_l1om
;
2892 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2894 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2895 || flag_code
!= CODE_64BIT
)
2896 as_fatal (_("Intel K1OM is 64bit ELF only"));
2897 return bfd_arch_k1om
;
2899 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2901 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2902 || flag_code
== CODE_64BIT
)
2903 as_fatal (_("Intel MCU is 32bit ELF only"));
2904 return bfd_arch_iamcu
;
2907 return bfd_arch_i386
;
2913 if (!strncmp (default_arch
, "x86_64", 6))
2915 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2917 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2918 || default_arch
[6] != '\0')
2919 as_fatal (_("Intel L1OM is 64bit ELF only"));
2920 return bfd_mach_l1om
;
2922 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2924 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2925 || default_arch
[6] != '\0')
2926 as_fatal (_("Intel K1OM is 64bit ELF only"));
2927 return bfd_mach_k1om
;
2929 else if (default_arch
[6] == '\0')
2930 return bfd_mach_x86_64
;
2932 return bfd_mach_x64_32
;
2934 else if (!strcmp (default_arch
, "i386")
2935 || !strcmp (default_arch
, "iamcu"))
2937 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2939 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2940 as_fatal (_("Intel MCU is 32bit ELF only"));
2941 return bfd_mach_i386_iamcu
;
2944 return bfd_mach_i386_i386
;
2947 as_fatal (_("unknown architecture"));
2953 const char *hash_err
;
2955 /* Support pseudo prefixes like {disp32}. */
2956 lex_type
['{'] = LEX_BEGIN_NAME
;
2958 /* Initialize op_hash hash table. */
2959 op_hash
= hash_new ();
2962 const insn_template
*optab
;
2963 templates
*core_optab
;
2965 /* Setup for loop. */
2967 core_optab
= XNEW (templates
);
2968 core_optab
->start
= optab
;
2973 if (optab
->name
== NULL
2974 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2976 /* different name --> ship out current template list;
2977 add to hash table; & begin anew. */
2978 core_optab
->end
= optab
;
2979 hash_err
= hash_insert (op_hash
,
2981 (void *) core_optab
);
2984 as_fatal (_("can't hash %s: %s"),
2988 if (optab
->name
== NULL
)
2990 core_optab
= XNEW (templates
);
2991 core_optab
->start
= optab
;
2996 /* Initialize reg_hash hash table. */
2997 reg_hash
= hash_new ();
2999 const reg_entry
*regtab
;
3000 unsigned int regtab_size
= i386_regtab_size
;
3002 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3004 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
3006 as_fatal (_("can't hash %s: %s"),
3012 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3017 for (c
= 0; c
< 256; c
++)
3022 mnemonic_chars
[c
] = c
;
3023 register_chars
[c
] = c
;
3024 operand_chars
[c
] = c
;
3026 else if (ISLOWER (c
))
3028 mnemonic_chars
[c
] = c
;
3029 register_chars
[c
] = c
;
3030 operand_chars
[c
] = c
;
3032 else if (ISUPPER (c
))
3034 mnemonic_chars
[c
] = TOLOWER (c
);
3035 register_chars
[c
] = mnemonic_chars
[c
];
3036 operand_chars
[c
] = c
;
3038 else if (c
== '{' || c
== '}')
3040 mnemonic_chars
[c
] = c
;
3041 operand_chars
[c
] = c
;
3044 if (ISALPHA (c
) || ISDIGIT (c
))
3045 identifier_chars
[c
] = c
;
3048 identifier_chars
[c
] = c
;
3049 operand_chars
[c
] = c
;
3054 identifier_chars
['@'] = '@';
3057 identifier_chars
['?'] = '?';
3058 operand_chars
['?'] = '?';
3060 digit_chars
['-'] = '-';
3061 mnemonic_chars
['_'] = '_';
3062 mnemonic_chars
['-'] = '-';
3063 mnemonic_chars
['.'] = '.';
3064 identifier_chars
['_'] = '_';
3065 identifier_chars
['.'] = '.';
3067 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3068 operand_chars
[(unsigned char) *p
] = *p
;
3071 if (flag_code
== CODE_64BIT
)
3073 #if defined (OBJ_COFF) && defined (TE_PE)
3074 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3077 x86_dwarf2_return_column
= 16;
3079 x86_cie_data_alignment
= -8;
3083 x86_dwarf2_return_column
= 8;
3084 x86_cie_data_alignment
= -4;
3087 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3088 can be turned into BRANCH_PREFIX frag. */
3089 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3094 i386_print_statistics (FILE *file
)
3096 hash_print_statistics (file
, "i386 opcode", op_hash
);
3097 hash_print_statistics (file
, "i386 register", reg_hash
);
3102 /* Debugging routines for md_assemble. */
3103 static void pte (insn_template
*);
3104 static void pt (i386_operand_type
);
3105 static void pe (expressionS
*);
3106 static void ps (symbolS
*);
3109 pi (const char *line
, i386_insn
*x
)
3113 fprintf (stdout
, "%s: template ", line
);
3115 fprintf (stdout
, " address: base %s index %s scale %x\n",
3116 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3117 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3118 x
->log2_scale_factor
);
3119 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3120 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3121 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3122 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3123 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3124 (x
->rex
& REX_W
) != 0,
3125 (x
->rex
& REX_R
) != 0,
3126 (x
->rex
& REX_X
) != 0,
3127 (x
->rex
& REX_B
) != 0);
3128 for (j
= 0; j
< x
->operands
; j
++)
3130 fprintf (stdout
, " #%d: ", j
+ 1);
3132 fprintf (stdout
, "\n");
3133 if (x
->types
[j
].bitfield
.class == Reg
3134 || x
->types
[j
].bitfield
.class == RegMMX
3135 || x
->types
[j
].bitfield
.class == RegSIMD
3136 || x
->types
[j
].bitfield
.class == SReg
3137 || x
->types
[j
].bitfield
.class == RegCR
3138 || x
->types
[j
].bitfield
.class == RegDR
3139 || x
->types
[j
].bitfield
.class == RegTR
)
3140 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3141 if (operand_type_check (x
->types
[j
], imm
))
3143 if (operand_type_check (x
->types
[j
], disp
))
3144 pe (x
->op
[j
].disps
);
3149 pte (insn_template
*t
)
3152 fprintf (stdout
, " %d operands ", t
->operands
);
3153 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3154 if (t
->extension_opcode
!= None
)
3155 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3156 if (t
->opcode_modifier
.d
)
3157 fprintf (stdout
, "D");
3158 if (t
->opcode_modifier
.w
)
3159 fprintf (stdout
, "W");
3160 fprintf (stdout
, "\n");
3161 for (j
= 0; j
< t
->operands
; j
++)
3163 fprintf (stdout
, " #%d type ", j
+ 1);
3164 pt (t
->operand_types
[j
]);
3165 fprintf (stdout
, "\n");
3172 fprintf (stdout
, " operation %d\n", e
->X_op
);
3173 fprintf (stdout
, " add_number %ld (%lx)\n",
3174 (long) e
->X_add_number
, (long) e
->X_add_number
);
3175 if (e
->X_add_symbol
)
3177 fprintf (stdout
, " add_symbol ");
3178 ps (e
->X_add_symbol
);
3179 fprintf (stdout
, "\n");
3183 fprintf (stdout
, " op_symbol ");
3184 ps (e
->X_op_symbol
);
3185 fprintf (stdout
, "\n");
3192 fprintf (stdout
, "%s type %s%s",
3194 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3195 segment_name (S_GET_SEGMENT (s
)));
3198 static struct type_name
3200 i386_operand_type mask
;
3203 const type_names
[] =
3205 { OPERAND_TYPE_REG8
, "r8" },
3206 { OPERAND_TYPE_REG16
, "r16" },
3207 { OPERAND_TYPE_REG32
, "r32" },
3208 { OPERAND_TYPE_REG64
, "r64" },
3209 { OPERAND_TYPE_ACC8
, "acc8" },
3210 { OPERAND_TYPE_ACC16
, "acc16" },
3211 { OPERAND_TYPE_ACC32
, "acc32" },
3212 { OPERAND_TYPE_ACC64
, "acc64" },
3213 { OPERAND_TYPE_IMM8
, "i8" },
3214 { OPERAND_TYPE_IMM8
, "i8s" },
3215 { OPERAND_TYPE_IMM16
, "i16" },
3216 { OPERAND_TYPE_IMM32
, "i32" },
3217 { OPERAND_TYPE_IMM32S
, "i32s" },
3218 { OPERAND_TYPE_IMM64
, "i64" },
3219 { OPERAND_TYPE_IMM1
, "i1" },
3220 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3221 { OPERAND_TYPE_DISP8
, "d8" },
3222 { OPERAND_TYPE_DISP16
, "d16" },
3223 { OPERAND_TYPE_DISP32
, "d32" },
3224 { OPERAND_TYPE_DISP32S
, "d32s" },
3225 { OPERAND_TYPE_DISP64
, "d64" },
3226 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3227 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3228 { OPERAND_TYPE_CONTROL
, "control reg" },
3229 { OPERAND_TYPE_TEST
, "test reg" },
3230 { OPERAND_TYPE_DEBUG
, "debug reg" },
3231 { OPERAND_TYPE_FLOATREG
, "FReg" },
3232 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3233 { OPERAND_TYPE_SREG
, "SReg" },
3234 { OPERAND_TYPE_REGMMX
, "rMMX" },
3235 { OPERAND_TYPE_REGXMM
, "rXMM" },
3236 { OPERAND_TYPE_REGYMM
, "rYMM" },
3237 { OPERAND_TYPE_REGZMM
, "rZMM" },
3238 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3242 pt (i386_operand_type t
)
3245 i386_operand_type a
;
3247 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3249 a
= operand_type_and (t
, type_names
[j
].mask
);
3250 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3251 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3256 #endif /* DEBUG386 */
3258 static bfd_reloc_code_real_type
3259 reloc (unsigned int size
,
3262 bfd_reloc_code_real_type other
)
3264 if (other
!= NO_RELOC
)
3266 reloc_howto_type
*rel
;
3271 case BFD_RELOC_X86_64_GOT32
:
3272 return BFD_RELOC_X86_64_GOT64
;
3274 case BFD_RELOC_X86_64_GOTPLT64
:
3275 return BFD_RELOC_X86_64_GOTPLT64
;
3277 case BFD_RELOC_X86_64_PLTOFF64
:
3278 return BFD_RELOC_X86_64_PLTOFF64
;
3280 case BFD_RELOC_X86_64_GOTPC32
:
3281 other
= BFD_RELOC_X86_64_GOTPC64
;
3283 case BFD_RELOC_X86_64_GOTPCREL
:
3284 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3286 case BFD_RELOC_X86_64_TPOFF32
:
3287 other
= BFD_RELOC_X86_64_TPOFF64
;
3289 case BFD_RELOC_X86_64_DTPOFF32
:
3290 other
= BFD_RELOC_X86_64_DTPOFF64
;
3296 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3297 if (other
== BFD_RELOC_SIZE32
)
3300 other
= BFD_RELOC_SIZE64
;
3303 as_bad (_("there are no pc-relative size relocations"));
3309 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3310 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3313 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3315 as_bad (_("unknown relocation (%u)"), other
);
3316 else if (size
!= bfd_get_reloc_size (rel
))
3317 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3318 bfd_get_reloc_size (rel
),
3320 else if (pcrel
&& !rel
->pc_relative
)
3321 as_bad (_("non-pc-relative relocation for pc-relative field"));
3322 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3324 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3326 as_bad (_("relocated field and relocation type differ in signedness"));
3335 as_bad (_("there are no unsigned pc-relative relocations"));
3338 case 1: return BFD_RELOC_8_PCREL
;
3339 case 2: return BFD_RELOC_16_PCREL
;
3340 case 4: return BFD_RELOC_32_PCREL
;
3341 case 8: return BFD_RELOC_64_PCREL
;
3343 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3350 case 4: return BFD_RELOC_X86_64_32S
;
3355 case 1: return BFD_RELOC_8
;
3356 case 2: return BFD_RELOC_16
;
3357 case 4: return BFD_RELOC_32
;
3358 case 8: return BFD_RELOC_64
;
3360 as_bad (_("cannot do %s %u byte relocation"),
3361 sign
> 0 ? "signed" : "unsigned", size
);
3367 /* Here we decide which fixups can be adjusted to make them relative to
3368 the beginning of the section instead of the symbol. Basically we need
3369 to make sure that the dynamic relocations are done correctly, so in
3370 some cases we force the original symbol to be used. */
3373 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3375 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3379 /* Don't adjust pc-relative references to merge sections in 64-bit
3381 if (use_rela_relocations
3382 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3386 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3387 and changed later by validate_fix. */
3388 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3389 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3392 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3393 for size relocations. */
3394 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3395 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3396 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3397 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3398 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3399 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3400 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3401 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3402 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3403 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3404 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3405 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3406 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3407 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3408 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3409 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3410 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3411 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3412 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3413 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3414 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3415 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3416 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3417 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3418 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3419 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3420 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3421 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3422 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3423 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3424 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3425 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3426 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3433 intel_float_operand (const char *mnemonic
)
3435 /* Note that the value returned is meaningful only for opcodes with (memory)
3436 operands, hence the code here is free to improperly handle opcodes that
3437 have no operands (for better performance and smaller code). */
3439 if (mnemonic
[0] != 'f')
3440 return 0; /* non-math */
3442 switch (mnemonic
[1])
3444 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3445 the fs segment override prefix not currently handled because no
3446 call path can make opcodes without operands get here */
3448 return 2 /* integer op */;
3450 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3451 return 3; /* fldcw/fldenv */
3454 if (mnemonic
[2] != 'o' /* fnop */)
3455 return 3; /* non-waiting control op */
3458 if (mnemonic
[2] == 's')
3459 return 3; /* frstor/frstpm */
3462 if (mnemonic
[2] == 'a')
3463 return 3; /* fsave */
3464 if (mnemonic
[2] == 't')
3466 switch (mnemonic
[3])
3468 case 'c': /* fstcw */
3469 case 'd': /* fstdw */
3470 case 'e': /* fstenv */
3471 case 's': /* fsts[gw] */
3477 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3478 return 0; /* fxsave/fxrstor are not really math ops */
3485 /* Build the VEX prefix. */
3488 build_vex_prefix (const insn_template
*t
)
3490 unsigned int register_specifier
;
3491 unsigned int implied_prefix
;
3492 unsigned int vector_length
;
3495 /* Check register specifier. */
3496 if (i
.vex
.register_specifier
)
3498 register_specifier
=
3499 ~register_number (i
.vex
.register_specifier
) & 0xf;
3500 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3503 register_specifier
= 0xf;
3505 /* Use 2-byte VEX prefix by swapping destination and source operand
3506 if there are more than 1 register operand. */
3507 if (i
.reg_operands
> 1
3508 && i
.vec_encoding
!= vex_encoding_vex3
3509 && i
.dir_encoding
== dir_encoding_default
3510 && i
.operands
== i
.reg_operands
3511 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3512 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3513 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3516 unsigned int xchg
= i
.operands
- 1;
3517 union i386_op temp_op
;
3518 i386_operand_type temp_type
;
3520 temp_type
= i
.types
[xchg
];
3521 i
.types
[xchg
] = i
.types
[0];
3522 i
.types
[0] = temp_type
;
3523 temp_op
= i
.op
[xchg
];
3524 i
.op
[xchg
] = i
.op
[0];
3527 gas_assert (i
.rm
.mode
== 3);
3531 i
.rm
.regmem
= i
.rm
.reg
;
3534 if (i
.tm
.opcode_modifier
.d
)
3535 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3536 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3537 else /* Use the next insn. */
3541 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3542 are no memory operands and at least 3 register ones. */
3543 if (i
.reg_operands
>= 3
3544 && i
.vec_encoding
!= vex_encoding_vex3
3545 && i
.reg_operands
== i
.operands
- i
.imm_operands
3546 && i
.tm
.opcode_modifier
.vex
3547 && i
.tm
.opcode_modifier
.commutative
3548 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3550 && i
.vex
.register_specifier
3551 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3553 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3554 union i386_op temp_op
;
3555 i386_operand_type temp_type
;
3557 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3558 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3559 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3560 &i
.types
[i
.operands
- 3]));
3561 gas_assert (i
.rm
.mode
== 3);
3563 temp_type
= i
.types
[xchg
];
3564 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3565 i
.types
[xchg
+ 1] = temp_type
;
3566 temp_op
= i
.op
[xchg
];
3567 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3568 i
.op
[xchg
+ 1] = temp_op
;
3571 xchg
= i
.rm
.regmem
| 8;
3572 i
.rm
.regmem
= ~register_specifier
& 0xf;
3573 gas_assert (!(i
.rm
.regmem
& 8));
3574 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3575 register_specifier
= ~xchg
& 0xf;
3578 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3579 vector_length
= avxscalar
;
3580 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3586 /* Determine vector length from the last multi-length vector
3589 for (op
= t
->operands
; op
--;)
3590 if (t
->operand_types
[op
].bitfield
.xmmword
3591 && t
->operand_types
[op
].bitfield
.ymmword
3592 && i
.types
[op
].bitfield
.ymmword
)
3599 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3604 case DATA_PREFIX_OPCODE
:
3607 case REPE_PREFIX_OPCODE
:
3610 case REPNE_PREFIX_OPCODE
:
3617 /* Check the REX.W bit and VEXW. */
3618 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3619 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3620 else if (i
.tm
.opcode_modifier
.vexw
)
3621 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3623 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3625 /* Use 2-byte VEX prefix if possible. */
3627 && i
.vec_encoding
!= vex_encoding_vex3
3628 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3629 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3631 /* 2-byte VEX prefix. */
3635 i
.vex
.bytes
[0] = 0xc5;
3637 /* Check the REX.R bit. */
3638 r
= (i
.rex
& REX_R
) ? 0 : 1;
3639 i
.vex
.bytes
[1] = (r
<< 7
3640 | register_specifier
<< 3
3641 | vector_length
<< 2
3646 /* 3-byte VEX prefix. */
3651 switch (i
.tm
.opcode_modifier
.vexopcode
)
3655 i
.vex
.bytes
[0] = 0xc4;
3659 i
.vex
.bytes
[0] = 0xc4;
3663 i
.vex
.bytes
[0] = 0xc4;
3667 i
.vex
.bytes
[0] = 0x8f;
3671 i
.vex
.bytes
[0] = 0x8f;
3675 i
.vex
.bytes
[0] = 0x8f;
3681 /* The high 3 bits of the second VEX byte are 1's compliment
3682 of RXB bits from REX. */
3683 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3685 i
.vex
.bytes
[2] = (w
<< 7
3686 | register_specifier
<< 3
3687 | vector_length
<< 2
3692 static INLINE bfd_boolean
3693 is_evex_encoding (const insn_template
*t
)
3695 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3696 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3697 || t
->opcode_modifier
.sae
;
3700 static INLINE bfd_boolean
3701 is_any_vex_encoding (const insn_template
*t
)
3703 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3704 || is_evex_encoding (t
);
3707 /* Build the EVEX prefix. */
3710 build_evex_prefix (void)
3712 unsigned int register_specifier
;
3713 unsigned int implied_prefix
;
3715 rex_byte vrex_used
= 0;
3717 /* Check register specifier. */
3718 if (i
.vex
.register_specifier
)
3720 gas_assert ((i
.vrex
& REX_X
) == 0);
3722 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3723 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3724 register_specifier
+= 8;
3725 /* The upper 16 registers are encoded in the fourth byte of the
3727 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3728 i
.vex
.bytes
[3] = 0x8;
3729 register_specifier
= ~register_specifier
& 0xf;
3733 register_specifier
= 0xf;
3735 /* Encode upper 16 vector index register in the fourth byte of
3737 if (!(i
.vrex
& REX_X
))
3738 i
.vex
.bytes
[3] = 0x8;
3743 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3748 case DATA_PREFIX_OPCODE
:
3751 case REPE_PREFIX_OPCODE
:
3754 case REPNE_PREFIX_OPCODE
:
3761 /* 4 byte EVEX prefix. */
3763 i
.vex
.bytes
[0] = 0x62;
3766 switch (i
.tm
.opcode_modifier
.vexopcode
)
3782 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3784 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3786 /* The fifth bit of the second EVEX byte is 1's compliment of the
3787 REX_R bit in VREX. */
3788 if (!(i
.vrex
& REX_R
))
3789 i
.vex
.bytes
[1] |= 0x10;
3793 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3795 /* When all operands are registers, the REX_X bit in REX is not
3796 used. We reuse it to encode the upper 16 registers, which is
3797 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3798 as 1's compliment. */
3799 if ((i
.vrex
& REX_B
))
3802 i
.vex
.bytes
[1] &= ~0x40;
3806 /* EVEX instructions shouldn't need the REX prefix. */
3807 i
.vrex
&= ~vrex_used
;
3808 gas_assert (i
.vrex
== 0);
3810 /* Check the REX.W bit and VEXW. */
3811 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3812 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3813 else if (i
.tm
.opcode_modifier
.vexw
)
3814 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3816 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3818 /* Encode the U bit. */
3819 implied_prefix
|= 0x4;
3821 /* The third byte of the EVEX prefix. */
3822 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3824 /* The fourth byte of the EVEX prefix. */
3825 /* The zeroing-masking bit. */
3826 if (i
.mask
&& i
.mask
->zeroing
)
3827 i
.vex
.bytes
[3] |= 0x80;
3829 /* Don't always set the broadcast bit if there is no RC. */
3832 /* Encode the vector length. */
3833 unsigned int vec_length
;
3835 if (!i
.tm
.opcode_modifier
.evex
3836 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3840 /* Determine vector length from the last multi-length vector
3843 for (op
= i
.operands
; op
--;)
3844 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3845 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3846 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3848 if (i
.types
[op
].bitfield
.zmmword
)
3850 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3853 else if (i
.types
[op
].bitfield
.ymmword
)
3855 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3858 else if (i
.types
[op
].bitfield
.xmmword
)
3860 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3863 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3865 switch (i
.broadcast
->bytes
)
3868 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3871 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3874 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3883 if (op
>= MAX_OPERANDS
)
3887 switch (i
.tm
.opcode_modifier
.evex
)
3889 case EVEXLIG
: /* LL' is ignored */
3890 vec_length
= evexlig
<< 5;
3893 vec_length
= 0 << 5;
3896 vec_length
= 1 << 5;
3899 vec_length
= 2 << 5;
3905 i
.vex
.bytes
[3] |= vec_length
;
3906 /* Encode the broadcast bit. */
3908 i
.vex
.bytes
[3] |= 0x10;
3912 if (i
.rounding
->type
!= saeonly
)
3913 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3915 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3918 if (i
.mask
&& i
.mask
->mask
)
3919 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3923 process_immext (void)
3927 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3928 which is coded in the same place as an 8-bit immediate field
3929 would be. Here we fake an 8-bit immediate operand from the
3930 opcode suffix stored in tm.extension_opcode.
3932 AVX instructions also use this encoding, for some of
3933 3 argument instructions. */
3935 gas_assert (i
.imm_operands
<= 1
3937 || (is_any_vex_encoding (&i
.tm
)
3938 && i
.operands
<= 4)));
3940 exp
= &im_expressions
[i
.imm_operands
++];
3941 i
.op
[i
.operands
].imms
= exp
;
3942 i
.types
[i
.operands
] = imm8
;
3944 exp
->X_op
= O_constant
;
3945 exp
->X_add_number
= i
.tm
.extension_opcode
;
3946 i
.tm
.extension_opcode
= None
;
3953 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3958 as_bad (_("invalid instruction `%s' after `%s'"),
3959 i
.tm
.name
, i
.hle_prefix
);
3962 if (i
.prefix
[LOCK_PREFIX
])
3964 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3968 case HLEPrefixRelease
:
3969 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3971 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3975 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
3977 as_bad (_("memory destination needed for instruction `%s'"
3978 " after `xrelease'"), i
.tm
.name
);
3985 /* Try the shortest encoding by shortening operand size. */
3988 optimize_encoding (void)
3992 if (optimize_for_space
3993 && !is_any_vex_encoding (&i
.tm
)
3994 && i
.reg_operands
== 1
3995 && i
.imm_operands
== 1
3996 && !i
.types
[1].bitfield
.byte
3997 && i
.op
[0].imms
->X_op
== O_constant
3998 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3999 && (i
.tm
.base_opcode
== 0xa8
4000 || (i
.tm
.base_opcode
== 0xf6
4001 && i
.tm
.extension_opcode
== 0x0)))
4004 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4006 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4007 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4009 i
.types
[1].bitfield
.byte
= 1;
4010 /* Ignore the suffix. */
4012 /* Convert to byte registers. */
4013 if (i
.types
[1].bitfield
.word
)
4015 else if (i
.types
[1].bitfield
.dword
)
4019 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4024 else if (flag_code
== CODE_64BIT
4025 && !is_any_vex_encoding (&i
.tm
)
4026 && ((i
.types
[1].bitfield
.qword
4027 && i
.reg_operands
== 1
4028 && i
.imm_operands
== 1
4029 && i
.op
[0].imms
->X_op
== O_constant
4030 && ((i
.tm
.base_opcode
== 0xb8
4031 && i
.tm
.extension_opcode
== None
4032 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4033 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4034 && ((i
.tm
.base_opcode
== 0x24
4035 || i
.tm
.base_opcode
== 0xa8)
4036 || (i
.tm
.base_opcode
== 0x80
4037 && i
.tm
.extension_opcode
== 0x4)
4038 || ((i
.tm
.base_opcode
== 0xf6
4039 || (i
.tm
.base_opcode
| 1) == 0xc7)
4040 && i
.tm
.extension_opcode
== 0x0)))
4041 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4042 && i
.tm
.base_opcode
== 0x83
4043 && i
.tm
.extension_opcode
== 0x4)))
4044 || (i
.types
[0].bitfield
.qword
4045 && ((i
.reg_operands
== 2
4046 && i
.op
[0].regs
== i
.op
[1].regs
4047 && (i
.tm
.base_opcode
== 0x30
4048 || i
.tm
.base_opcode
== 0x28))
4049 || (i
.reg_operands
== 1
4051 && i
.tm
.base_opcode
== 0x30)))))
4054 andq $imm31, %r64 -> andl $imm31, %r32
4055 andq $imm7, %r64 -> andl $imm7, %r32
4056 testq $imm31, %r64 -> testl $imm31, %r32
4057 xorq %r64, %r64 -> xorl %r32, %r32
4058 subq %r64, %r64 -> subl %r32, %r32
4059 movq $imm31, %r64 -> movl $imm31, %r32
4060 movq $imm32, %r64 -> movl $imm32, %r32
4062 i
.tm
.opcode_modifier
.norex64
= 1;
4063 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4066 movq $imm31, %r64 -> movl $imm31, %r32
4067 movq $imm32, %r64 -> movl $imm32, %r32
4069 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4070 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4071 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4072 i
.types
[0].bitfield
.imm32
= 1;
4073 i
.types
[0].bitfield
.imm32s
= 0;
4074 i
.types
[0].bitfield
.imm64
= 0;
4075 i
.types
[1].bitfield
.dword
= 1;
4076 i
.types
[1].bitfield
.qword
= 0;
4077 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4080 movq $imm31, %r64 -> movl $imm31, %r32
4082 i
.tm
.base_opcode
= 0xb8;
4083 i
.tm
.extension_opcode
= None
;
4084 i
.tm
.opcode_modifier
.w
= 0;
4085 i
.tm
.opcode_modifier
.shortform
= 1;
4086 i
.tm
.opcode_modifier
.modrm
= 0;
4090 else if (optimize
> 1
4091 && !optimize_for_space
4092 && !is_any_vex_encoding (&i
.tm
)
4093 && i
.reg_operands
== 2
4094 && i
.op
[0].regs
== i
.op
[1].regs
4095 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4096 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4097 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4100 andb %rN, %rN -> testb %rN, %rN
4101 andw %rN, %rN -> testw %rN, %rN
4102 andq %rN, %rN -> testq %rN, %rN
4103 orb %rN, %rN -> testb %rN, %rN
4104 orw %rN, %rN -> testw %rN, %rN
4105 orq %rN, %rN -> testq %rN, %rN
4107 and outside of 64-bit mode
4109 andl %rN, %rN -> testl %rN, %rN
4110 orl %rN, %rN -> testl %rN, %rN
4112 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4114 else if (i
.reg_operands
== 3
4115 && i
.op
[0].regs
== i
.op
[1].regs
4116 && !i
.types
[2].bitfield
.xmmword
4117 && (i
.tm
.opcode_modifier
.vex
4118 || ((!i
.mask
|| i
.mask
->zeroing
)
4120 && is_evex_encoding (&i
.tm
)
4121 && (i
.vec_encoding
!= vex_encoding_evex
4122 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4123 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4124 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4125 && i
.types
[2].bitfield
.ymmword
))))
4126 && ((i
.tm
.base_opcode
== 0x55
4127 || i
.tm
.base_opcode
== 0x6655
4128 || i
.tm
.base_opcode
== 0x66df
4129 || i
.tm
.base_opcode
== 0x57
4130 || i
.tm
.base_opcode
== 0x6657
4131 || i
.tm
.base_opcode
== 0x66ef
4132 || i
.tm
.base_opcode
== 0x66f8
4133 || i
.tm
.base_opcode
== 0x66f9
4134 || i
.tm
.base_opcode
== 0x66fa
4135 || i
.tm
.base_opcode
== 0x66fb
4136 || i
.tm
.base_opcode
== 0x42
4137 || i
.tm
.base_opcode
== 0x6642
4138 || i
.tm
.base_opcode
== 0x47
4139 || i
.tm
.base_opcode
== 0x6647)
4140 && i
.tm
.extension_opcode
== None
))
4143 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4145 EVEX VOP %zmmM, %zmmM, %zmmN
4146 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4147 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4148 EVEX VOP %ymmM, %ymmM, %ymmN
4149 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4150 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4151 VEX VOP %ymmM, %ymmM, %ymmN
4152 -> VEX VOP %xmmM, %xmmM, %xmmN
4153 VOP, one of vpandn and vpxor:
4154 VEX VOP %ymmM, %ymmM, %ymmN
4155 -> VEX VOP %xmmM, %xmmM, %xmmN
4156 VOP, one of vpandnd and vpandnq:
4157 EVEX VOP %zmmM, %zmmM, %zmmN
4158 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4159 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4160 EVEX VOP %ymmM, %ymmM, %ymmN
4161 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4162 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4163 VOP, one of vpxord and vpxorq:
4164 EVEX VOP %zmmM, %zmmM, %zmmN
4165 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4166 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4167 EVEX VOP %ymmM, %ymmM, %ymmN
4168 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4169 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4170 VOP, one of kxord and kxorq:
4171 VEX VOP %kM, %kM, %kN
4172 -> VEX kxorw %kM, %kM, %kN
4173 VOP, one of kandnd and kandnq:
4174 VEX VOP %kM, %kM, %kN
4175 -> VEX kandnw %kM, %kM, %kN
4177 if (is_evex_encoding (&i
.tm
))
4179 if (i
.vec_encoding
!= vex_encoding_evex
)
4181 i
.tm
.opcode_modifier
.vex
= VEX128
;
4182 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4183 i
.tm
.opcode_modifier
.evex
= 0;
4185 else if (optimize
> 1)
4186 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4190 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4192 i
.tm
.base_opcode
&= 0xff;
4193 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4196 i
.tm
.opcode_modifier
.vex
= VEX128
;
4198 if (i
.tm
.opcode_modifier
.vex
)
4199 for (j
= 0; j
< 3; j
++)
4201 i
.types
[j
].bitfield
.xmmword
= 1;
4202 i
.types
[j
].bitfield
.ymmword
= 0;
4205 else if (i
.vec_encoding
!= vex_encoding_evex
4206 && !i
.types
[0].bitfield
.zmmword
4207 && !i
.types
[1].bitfield
.zmmword
4210 && is_evex_encoding (&i
.tm
)
4211 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4212 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4213 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4214 || (i
.tm
.base_opcode
& ~4) == 0x66db
4215 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4216 && i
.tm
.extension_opcode
== None
)
4219 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4220 vmovdqu32 and vmovdqu64:
4221 EVEX VOP %xmmM, %xmmN
4222 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4223 EVEX VOP %ymmM, %ymmN
4224 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4226 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4228 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4230 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4232 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4233 VOP, one of vpand, vpandn, vpor, vpxor:
4234 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4235 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4236 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4237 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4238 EVEX VOP{d,q} mem, %xmmM, %xmmN
4239 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4240 EVEX VOP{d,q} mem, %ymmM, %ymmN
4241 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4243 for (j
= 0; j
< i
.operands
; j
++)
4244 if (operand_type_check (i
.types
[j
], disp
)
4245 && i
.op
[j
].disps
->X_op
== O_constant
)
4247 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4248 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4249 bytes, we choose EVEX Disp8 over VEX Disp32. */
4250 int evex_disp8
, vex_disp8
;
4251 unsigned int memshift
= i
.memshift
;
4252 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4254 evex_disp8
= fits_in_disp8 (n
);
4256 vex_disp8
= fits_in_disp8 (n
);
4257 if (evex_disp8
!= vex_disp8
)
4259 i
.memshift
= memshift
;
4263 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4266 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4267 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4268 i
.tm
.opcode_modifier
.vex
4269 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4270 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4271 /* VPAND, VPOR, and VPXOR are commutative. */
4272 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4273 i
.tm
.opcode_modifier
.commutative
= 1;
4274 i
.tm
.opcode_modifier
.evex
= 0;
4275 i
.tm
.opcode_modifier
.masking
= 0;
4276 i
.tm
.opcode_modifier
.broadcast
= 0;
4277 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4280 i
.types
[j
].bitfield
.disp8
4281 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4285 /* This is the guts of the machine-dependent assembler. LINE points to a
4286 machine dependent instruction. This function is supposed to emit
4287 the frags/bytes it assembles to. */
4290 md_assemble (char *line
)
4293 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4294 const insn_template
*t
;
4296 /* Initialize globals. */
4297 memset (&i
, '\0', sizeof (i
));
4298 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4299 i
.reloc
[j
] = NO_RELOC
;
4300 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4301 memset (im_expressions
, '\0', sizeof (im_expressions
));
4302 save_stack_p
= save_stack
;
4304 /* First parse an instruction mnemonic & call i386_operand for the operands.
4305 We assume that the scrubber has arranged it so that line[0] is the valid
4306 start of a (possibly prefixed) mnemonic. */
4308 line
= parse_insn (line
, mnemonic
);
4311 mnem_suffix
= i
.suffix
;
4313 line
= parse_operands (line
, mnemonic
);
4315 xfree (i
.memop1_string
);
4316 i
.memop1_string
= NULL
;
4320 /* Now we've parsed the mnemonic into a set of templates, and have the
4321 operands at hand. */
4323 /* All intel opcodes have reversed operands except for "bound" and
4324 "enter". We also don't reverse intersegment "jmp" and "call"
4325 instructions with 2 immediate operands so that the immediate segment
4326 precedes the offset, as it does when in AT&T mode. */
4329 && (strcmp (mnemonic
, "bound") != 0)
4330 && (strcmp (mnemonic
, "invlpga") != 0)
4331 && !(operand_type_check (i
.types
[0], imm
)
4332 && operand_type_check (i
.types
[1], imm
)))
4335 /* The order of the immediates should be reversed
4336 for 2 immediates extrq and insertq instructions */
4337 if (i
.imm_operands
== 2
4338 && (strcmp (mnemonic
, "extrq") == 0
4339 || strcmp (mnemonic
, "insertq") == 0))
4340 swap_2_operands (0, 1);
4345 /* Don't optimize displacement for movabs since it only takes 64bit
4348 && i
.disp_encoding
!= disp_encoding_32bit
4349 && (flag_code
!= CODE_64BIT
4350 || strcmp (mnemonic
, "movabs") != 0))
4353 /* Next, we find a template that matches the given insn,
4354 making sure the overlap of the given operands types is consistent
4355 with the template operand types. */
4357 if (!(t
= match_template (mnem_suffix
)))
4360 if (sse_check
!= check_none
4361 && !i
.tm
.opcode_modifier
.noavx
4362 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4363 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4364 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4365 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4366 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4367 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4368 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4369 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4370 || i
.tm
.cpu_flags
.bitfield
.cpusse4a
4371 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4372 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4373 || i
.tm
.cpu_flags
.bitfield
.cpusha
4374 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4376 (sse_check
== check_warning
4378 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4381 /* Zap movzx and movsx suffix. The suffix has been set from
4382 "word ptr" or "byte ptr" on the source operand in Intel syntax
4383 or extracted from mnemonic in AT&T syntax. But we'll use
4384 the destination register to choose the suffix for encoding. */
4385 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4387 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4388 there is no suffix, the default will be byte extension. */
4389 if (i
.reg_operands
!= 2
4392 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4397 if (i
.tm
.opcode_modifier
.fwait
)
4398 if (!add_prefix (FWAIT_OPCODE
))
4401 /* Check if REP prefix is OK. */
4402 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4404 as_bad (_("invalid instruction `%s' after `%s'"),
4405 i
.tm
.name
, i
.rep_prefix
);
4409 /* Check for lock without a lockable instruction. Destination operand
4410 must be memory unless it is xchg (0x86). */
4411 if (i
.prefix
[LOCK_PREFIX
]
4412 && (!i
.tm
.opcode_modifier
.islockable
4413 || i
.mem_operands
== 0
4414 || (i
.tm
.base_opcode
!= 0x86
4415 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4417 as_bad (_("expecting lockable instruction after `lock'"));
4421 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4422 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4424 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4428 /* Check if HLE prefix is OK. */
4429 if (i
.hle_prefix
&& !check_hle ())
4432 /* Check BND prefix. */
4433 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4434 as_bad (_("expecting valid branch instruction after `bnd'"));
4436 /* Check NOTRACK prefix. */
4437 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4438 as_bad (_("expecting indirect branch instruction after `notrack'"));
4440 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4442 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4443 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4444 else if (flag_code
!= CODE_16BIT
4445 ? i
.prefix
[ADDR_PREFIX
]
4446 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4447 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4450 /* Insert BND prefix. */
4451 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4453 if (!i
.prefix
[BND_PREFIX
])
4454 add_prefix (BND_PREFIX_OPCODE
);
4455 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4457 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4458 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4462 /* Check string instruction segment overrides. */
4463 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4465 gas_assert (i
.mem_operands
);
4466 if (!check_string ())
4468 i
.disp_operands
= 0;
4471 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4472 optimize_encoding ();
4474 if (!process_suffix ())
4477 /* Update operand types. */
4478 for (j
= 0; j
< i
.operands
; j
++)
4479 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4481 /* Make still unresolved immediate matches conform to size of immediate
4482 given in i.suffix. */
4483 if (!finalize_imm ())
4486 if (i
.types
[0].bitfield
.imm1
)
4487 i
.imm_operands
= 0; /* kludge for shift insns. */
4489 /* We only need to check those implicit registers for instructions
4490 with 3 operands or less. */
4491 if (i
.operands
<= 3)
4492 for (j
= 0; j
< i
.operands
; j
++)
4493 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4494 && !i
.types
[j
].bitfield
.xmmword
)
4497 /* ImmExt should be processed after SSE2AVX. */
4498 if (!i
.tm
.opcode_modifier
.sse2avx
4499 && i
.tm
.opcode_modifier
.immext
)
4502 /* For insns with operands there are more diddles to do to the opcode. */
4505 if (!process_operands ())
4508 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4510 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4511 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4514 if (is_any_vex_encoding (&i
.tm
))
4516 if (!cpu_arch_flags
.bitfield
.cpui286
)
4518 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4523 if (i
.tm
.opcode_modifier
.vex
)
4524 build_vex_prefix (t
);
4526 build_evex_prefix ();
4529 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4530 instructions may define INT_OPCODE as well, so avoid this corner
4531 case for those instructions that use MODRM. */
4532 if (i
.tm
.base_opcode
== INT_OPCODE
4533 && !i
.tm
.opcode_modifier
.modrm
4534 && i
.op
[0].imms
->X_add_number
== 3)
4536 i
.tm
.base_opcode
= INT3_OPCODE
;
4540 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4541 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4542 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4543 && i
.op
[0].disps
->X_op
== O_constant
)
4545 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4546 the absolute address given by the constant. Since ix86 jumps and
4547 calls are pc relative, we need to generate a reloc. */
4548 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4549 i
.op
[0].disps
->X_op
= O_symbol
;
4552 if (i
.tm
.opcode_modifier
.rex64
)
4555 /* For 8 bit registers we need an empty rex prefix. Also if the
4556 instruction already has a prefix, we need to convert old
4557 registers to new ones. */
4559 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4560 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4561 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4562 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4563 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4564 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4569 i
.rex
|= REX_OPCODE
;
4570 for (x
= 0; x
< 2; x
++)
4572 /* Look for 8 bit operand that uses old registers. */
4573 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4574 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4576 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4577 /* In case it is "hi" register, give up. */
4578 if (i
.op
[x
].regs
->reg_num
> 3)
4579 as_bad (_("can't encode register '%s%s' in an "
4580 "instruction requiring REX prefix."),
4581 register_prefix
, i
.op
[x
].regs
->reg_name
);
4583 /* Otherwise it is equivalent to the extended register.
4584 Since the encoding doesn't change this is merely
4585 cosmetic cleanup for debug output. */
4587 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4592 if (i
.rex
== 0 && i
.rex_encoding
)
4594 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4595 that uses legacy register. If it is "hi" register, don't add
4596 the REX_OPCODE byte. */
4598 for (x
= 0; x
< 2; x
++)
4599 if (i
.types
[x
].bitfield
.class == Reg
4600 && i
.types
[x
].bitfield
.byte
4601 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4602 && i
.op
[x
].regs
->reg_num
> 3)
4604 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4605 i
.rex_encoding
= FALSE
;
4614 add_prefix (REX_OPCODE
| i
.rex
);
4616 /* We are ready to output the insn. */
4619 last_insn
.seg
= now_seg
;
4621 if (i
.tm
.opcode_modifier
.isprefix
)
4623 last_insn
.kind
= last_insn_prefix
;
4624 last_insn
.name
= i
.tm
.name
;
4625 last_insn
.file
= as_where (&last_insn
.line
);
4628 last_insn
.kind
= last_insn_other
;
4632 parse_insn (char *line
, char *mnemonic
)
4635 char *token_start
= l
;
4638 const insn_template
*t
;
4644 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4649 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4651 as_bad (_("no such instruction: `%s'"), token_start
);
4656 if (!is_space_char (*l
)
4657 && *l
!= END_OF_INSN
4659 || (*l
!= PREFIX_SEPARATOR
4662 as_bad (_("invalid character %s in mnemonic"),
4663 output_invalid (*l
));
4666 if (token_start
== l
)
4668 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4669 as_bad (_("expecting prefix; got nothing"));
4671 as_bad (_("expecting mnemonic; got nothing"));
4675 /* Look up instruction (or prefix) via hash table. */
4676 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4678 if (*l
!= END_OF_INSN
4679 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4680 && current_templates
4681 && current_templates
->start
->opcode_modifier
.isprefix
)
4683 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4685 as_bad ((flag_code
!= CODE_64BIT
4686 ? _("`%s' is only supported in 64-bit mode")
4687 : _("`%s' is not supported in 64-bit mode")),
4688 current_templates
->start
->name
);
4691 /* If we are in 16-bit mode, do not allow addr16 or data16.
4692 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4693 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4694 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4695 && flag_code
!= CODE_64BIT
4696 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4697 ^ (flag_code
== CODE_16BIT
)))
4699 as_bad (_("redundant %s prefix"),
4700 current_templates
->start
->name
);
4703 if (current_templates
->start
->opcode_length
== 0)
4705 /* Handle pseudo prefixes. */
4706 switch (current_templates
->start
->base_opcode
)
4710 i
.disp_encoding
= disp_encoding_8bit
;
4714 i
.disp_encoding
= disp_encoding_32bit
;
4718 i
.dir_encoding
= dir_encoding_load
;
4722 i
.dir_encoding
= dir_encoding_store
;
4726 i
.vec_encoding
= vex_encoding_vex2
;
4730 i
.vec_encoding
= vex_encoding_vex3
;
4734 i
.vec_encoding
= vex_encoding_evex
;
4738 i
.rex_encoding
= TRUE
;
4742 i
.no_optimize
= TRUE
;
4750 /* Add prefix, checking for repeated prefixes. */
4751 switch (add_prefix (current_templates
->start
->base_opcode
))
4756 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4757 i
.notrack_prefix
= current_templates
->start
->name
;
4760 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4761 i
.hle_prefix
= current_templates
->start
->name
;
4762 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4763 i
.bnd_prefix
= current_templates
->start
->name
;
4765 i
.rep_prefix
= current_templates
->start
->name
;
4771 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4778 if (!current_templates
)
4780 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4781 Check if we should swap operand or force 32bit displacement in
4783 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4784 i
.dir_encoding
= dir_encoding_swap
;
4785 else if (mnem_p
- 3 == dot_p
4788 i
.disp_encoding
= disp_encoding_8bit
;
4789 else if (mnem_p
- 4 == dot_p
4793 i
.disp_encoding
= disp_encoding_32bit
;
4798 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4801 if (!current_templates
)
4804 if (mnem_p
> mnemonic
)
4806 /* See if we can get a match by trimming off a suffix. */
4809 case WORD_MNEM_SUFFIX
:
4810 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4811 i
.suffix
= SHORT_MNEM_SUFFIX
;
4814 case BYTE_MNEM_SUFFIX
:
4815 case QWORD_MNEM_SUFFIX
:
4816 i
.suffix
= mnem_p
[-1];
4818 current_templates
= (const templates
*) hash_find (op_hash
,
4821 case SHORT_MNEM_SUFFIX
:
4822 case LONG_MNEM_SUFFIX
:
4825 i
.suffix
= mnem_p
[-1];
4827 current_templates
= (const templates
*) hash_find (op_hash
,
4836 if (intel_float_operand (mnemonic
) == 1)
4837 i
.suffix
= SHORT_MNEM_SUFFIX
;
4839 i
.suffix
= LONG_MNEM_SUFFIX
;
4841 current_templates
= (const templates
*) hash_find (op_hash
,
4848 if (!current_templates
)
4850 as_bad (_("no such instruction: `%s'"), token_start
);
4855 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
4856 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
4858 /* Check for a branch hint. We allow ",pt" and ",pn" for
4859 predict taken and predict not taken respectively.
4860 I'm not sure that branch hints actually do anything on loop
4861 and jcxz insns (JumpByte) for current Pentium4 chips. They
4862 may work in the future and it doesn't hurt to accept them
4864 if (l
[0] == ',' && l
[1] == 'p')
4868 if (!add_prefix (DS_PREFIX_OPCODE
))
4872 else if (l
[2] == 'n')
4874 if (!add_prefix (CS_PREFIX_OPCODE
))
4880 /* Any other comma loses. */
4883 as_bad (_("invalid character %s in mnemonic"),
4884 output_invalid (*l
));
4888 /* Check if instruction is supported on specified architecture. */
4890 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4892 supported
|= cpu_flags_match (t
);
4893 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4895 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4896 as_warn (_("use .code16 to ensure correct addressing mode"));
4902 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4903 as_bad (flag_code
== CODE_64BIT
4904 ? _("`%s' is not supported in 64-bit mode")
4905 : _("`%s' is only supported in 64-bit mode"),
4906 current_templates
->start
->name
);
4908 as_bad (_("`%s' is not supported on `%s%s'"),
4909 current_templates
->start
->name
,
4910 cpu_arch_name
? cpu_arch_name
: default_arch
,
4911 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4917 parse_operands (char *l
, const char *mnemonic
)
4921 /* 1 if operand is pending after ','. */
4922 unsigned int expecting_operand
= 0;
4924 /* Non-zero if operand parens not balanced. */
4925 unsigned int paren_not_balanced
;
4927 while (*l
!= END_OF_INSN
)
4929 /* Skip optional white space before operand. */
4930 if (is_space_char (*l
))
4932 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4934 as_bad (_("invalid character %s before operand %d"),
4935 output_invalid (*l
),
4939 token_start
= l
; /* After white space. */
4940 paren_not_balanced
= 0;
4941 while (paren_not_balanced
|| *l
!= ',')
4943 if (*l
== END_OF_INSN
)
4945 if (paren_not_balanced
)
4948 as_bad (_("unbalanced parenthesis in operand %d."),
4951 as_bad (_("unbalanced brackets in operand %d."),
4956 break; /* we are done */
4958 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4960 as_bad (_("invalid character %s in operand %d"),
4961 output_invalid (*l
),
4968 ++paren_not_balanced
;
4970 --paren_not_balanced
;
4975 ++paren_not_balanced
;
4977 --paren_not_balanced
;
4981 if (l
!= token_start
)
4982 { /* Yes, we've read in another operand. */
4983 unsigned int operand_ok
;
4984 this_operand
= i
.operands
++;
4985 if (i
.operands
> MAX_OPERANDS
)
4987 as_bad (_("spurious operands; (%d operands/instruction max)"),
4991 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4992 /* Now parse operand adding info to 'i' as we go along. */
4993 END_STRING_AND_SAVE (l
);
4995 if (i
.mem_operands
> 1)
4997 as_bad (_("too many memory references for `%s'"),
5004 i386_intel_operand (token_start
,
5005 intel_float_operand (mnemonic
));
5007 operand_ok
= i386_att_operand (token_start
);
5009 RESTORE_END_STRING (l
);
5015 if (expecting_operand
)
5017 expecting_operand_after_comma
:
5018 as_bad (_("expecting operand after ','; got nothing"));
5023 as_bad (_("expecting operand before ','; got nothing"));
5028 /* Now *l must be either ',' or END_OF_INSN. */
5031 if (*++l
== END_OF_INSN
)
5033 /* Just skip it, if it's \n complain. */
5034 goto expecting_operand_after_comma
;
5036 expecting_operand
= 1;
5043 swap_2_operands (int xchg1
, int xchg2
)
5045 union i386_op temp_op
;
5046 i386_operand_type temp_type
;
5047 unsigned int temp_flags
;
5048 enum bfd_reloc_code_real temp_reloc
;
5050 temp_type
= i
.types
[xchg2
];
5051 i
.types
[xchg2
] = i
.types
[xchg1
];
5052 i
.types
[xchg1
] = temp_type
;
5054 temp_flags
= i
.flags
[xchg2
];
5055 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5056 i
.flags
[xchg1
] = temp_flags
;
5058 temp_op
= i
.op
[xchg2
];
5059 i
.op
[xchg2
] = i
.op
[xchg1
];
5060 i
.op
[xchg1
] = temp_op
;
5062 temp_reloc
= i
.reloc
[xchg2
];
5063 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5064 i
.reloc
[xchg1
] = temp_reloc
;
5068 if (i
.mask
->operand
== xchg1
)
5069 i
.mask
->operand
= xchg2
;
5070 else if (i
.mask
->operand
== xchg2
)
5071 i
.mask
->operand
= xchg1
;
5075 if (i
.broadcast
->operand
== xchg1
)
5076 i
.broadcast
->operand
= xchg2
;
5077 else if (i
.broadcast
->operand
== xchg2
)
5078 i
.broadcast
->operand
= xchg1
;
5082 if (i
.rounding
->operand
== xchg1
)
5083 i
.rounding
->operand
= xchg2
;
5084 else if (i
.rounding
->operand
== xchg2
)
5085 i
.rounding
->operand
= xchg1
;
5090 swap_operands (void)
5096 swap_2_operands (1, i
.operands
- 2);
5100 swap_2_operands (0, i
.operands
- 1);
5106 if (i
.mem_operands
== 2)
5108 const seg_entry
*temp_seg
;
5109 temp_seg
= i
.seg
[0];
5110 i
.seg
[0] = i
.seg
[1];
5111 i
.seg
[1] = temp_seg
;
5115 /* Try to ensure constant immediates are represented in the smallest
5120 char guess_suffix
= 0;
5124 guess_suffix
= i
.suffix
;
5125 else if (i
.reg_operands
)
5127 /* Figure out a suffix from the last register operand specified.
5128 We can't do this properly yet, i.e. excluding special register
5129 instances, but the following works for instructions with
5130 immediates. In any case, we can't set i.suffix yet. */
5131 for (op
= i
.operands
; --op
>= 0;)
5132 if (i
.types
[op
].bitfield
.class != Reg
)
5134 else if (i
.types
[op
].bitfield
.byte
)
5136 guess_suffix
= BYTE_MNEM_SUFFIX
;
5139 else if (i
.types
[op
].bitfield
.word
)
5141 guess_suffix
= WORD_MNEM_SUFFIX
;
5144 else if (i
.types
[op
].bitfield
.dword
)
5146 guess_suffix
= LONG_MNEM_SUFFIX
;
5149 else if (i
.types
[op
].bitfield
.qword
)
5151 guess_suffix
= QWORD_MNEM_SUFFIX
;
5155 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5156 guess_suffix
= WORD_MNEM_SUFFIX
;
5158 for (op
= i
.operands
; --op
>= 0;)
5159 if (operand_type_check (i
.types
[op
], imm
))
5161 switch (i
.op
[op
].imms
->X_op
)
5164 /* If a suffix is given, this operand may be shortened. */
5165 switch (guess_suffix
)
5167 case LONG_MNEM_SUFFIX
:
5168 i
.types
[op
].bitfield
.imm32
= 1;
5169 i
.types
[op
].bitfield
.imm64
= 1;
5171 case WORD_MNEM_SUFFIX
:
5172 i
.types
[op
].bitfield
.imm16
= 1;
5173 i
.types
[op
].bitfield
.imm32
= 1;
5174 i
.types
[op
].bitfield
.imm32s
= 1;
5175 i
.types
[op
].bitfield
.imm64
= 1;
5177 case BYTE_MNEM_SUFFIX
:
5178 i
.types
[op
].bitfield
.imm8
= 1;
5179 i
.types
[op
].bitfield
.imm8s
= 1;
5180 i
.types
[op
].bitfield
.imm16
= 1;
5181 i
.types
[op
].bitfield
.imm32
= 1;
5182 i
.types
[op
].bitfield
.imm32s
= 1;
5183 i
.types
[op
].bitfield
.imm64
= 1;
5187 /* If this operand is at most 16 bits, convert it
5188 to a signed 16 bit number before trying to see
5189 whether it will fit in an even smaller size.
5190 This allows a 16-bit operand such as $0xffe0 to
5191 be recognised as within Imm8S range. */
5192 if ((i
.types
[op
].bitfield
.imm16
)
5193 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5195 i
.op
[op
].imms
->X_add_number
=
5196 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5199 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5200 if ((i
.types
[op
].bitfield
.imm32
)
5201 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5204 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5205 ^ ((offsetT
) 1 << 31))
5206 - ((offsetT
) 1 << 31));
5210 = operand_type_or (i
.types
[op
],
5211 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5213 /* We must avoid matching of Imm32 templates when 64bit
5214 only immediate is available. */
5215 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5216 i
.types
[op
].bitfield
.imm32
= 0;
5223 /* Symbols and expressions. */
5225 /* Convert symbolic operand to proper sizes for matching, but don't
5226 prevent matching a set of insns that only supports sizes other
5227 than those matching the insn suffix. */
5229 i386_operand_type mask
, allowed
;
5230 const insn_template
*t
;
5232 operand_type_set (&mask
, 0);
5233 operand_type_set (&allowed
, 0);
5235 for (t
= current_templates
->start
;
5236 t
< current_templates
->end
;
5239 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5240 allowed
= operand_type_and (allowed
, anyimm
);
5242 switch (guess_suffix
)
5244 case QWORD_MNEM_SUFFIX
:
5245 mask
.bitfield
.imm64
= 1;
5246 mask
.bitfield
.imm32s
= 1;
5248 case LONG_MNEM_SUFFIX
:
5249 mask
.bitfield
.imm32
= 1;
5251 case WORD_MNEM_SUFFIX
:
5252 mask
.bitfield
.imm16
= 1;
5254 case BYTE_MNEM_SUFFIX
:
5255 mask
.bitfield
.imm8
= 1;
5260 allowed
= operand_type_and (mask
, allowed
);
5261 if (!operand_type_all_zero (&allowed
))
5262 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5269 /* Try to use the smallest displacement type too. */
5271 optimize_disp (void)
5275 for (op
= i
.operands
; --op
>= 0;)
5276 if (operand_type_check (i
.types
[op
], disp
))
5278 if (i
.op
[op
].disps
->X_op
== O_constant
)
5280 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5282 if (i
.types
[op
].bitfield
.disp16
5283 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5285 /* If this operand is at most 16 bits, convert
5286 to a signed 16 bit number and don't use 64bit
5288 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5289 i
.types
[op
].bitfield
.disp64
= 0;
5292 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5293 if (i
.types
[op
].bitfield
.disp32
5294 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5296 /* If this operand is at most 32 bits, convert
5297 to a signed 32 bit number and don't use 64bit
5299 op_disp
&= (((offsetT
) 2 << 31) - 1);
5300 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5301 i
.types
[op
].bitfield
.disp64
= 0;
5304 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5306 i
.types
[op
].bitfield
.disp8
= 0;
5307 i
.types
[op
].bitfield
.disp16
= 0;
5308 i
.types
[op
].bitfield
.disp32
= 0;
5309 i
.types
[op
].bitfield
.disp32s
= 0;
5310 i
.types
[op
].bitfield
.disp64
= 0;
5314 else if (flag_code
== CODE_64BIT
)
5316 if (fits_in_signed_long (op_disp
))
5318 i
.types
[op
].bitfield
.disp64
= 0;
5319 i
.types
[op
].bitfield
.disp32s
= 1;
5321 if (i
.prefix
[ADDR_PREFIX
]
5322 && fits_in_unsigned_long (op_disp
))
5323 i
.types
[op
].bitfield
.disp32
= 1;
5325 if ((i
.types
[op
].bitfield
.disp32
5326 || i
.types
[op
].bitfield
.disp32s
5327 || i
.types
[op
].bitfield
.disp16
)
5328 && fits_in_disp8 (op_disp
))
5329 i
.types
[op
].bitfield
.disp8
= 1;
5331 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5332 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5334 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5335 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5336 i
.types
[op
].bitfield
.disp8
= 0;
5337 i
.types
[op
].bitfield
.disp16
= 0;
5338 i
.types
[op
].bitfield
.disp32
= 0;
5339 i
.types
[op
].bitfield
.disp32s
= 0;
5340 i
.types
[op
].bitfield
.disp64
= 0;
5343 /* We only support 64bit displacement on constants. */
5344 i
.types
[op
].bitfield
.disp64
= 0;
5348 /* Return 1 if there is a match in broadcast bytes between operand
5349 GIVEN and instruction template T. */
5352 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5354 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5355 && i
.types
[given
].bitfield
.byte
)
5356 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5357 && i
.types
[given
].bitfield
.word
)
5358 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5359 && i
.types
[given
].bitfield
.dword
)
5360 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5361 && i
.types
[given
].bitfield
.qword
));
5364 /* Check if operands are valid for the instruction. */
5367 check_VecOperands (const insn_template
*t
)
5371 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5373 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5374 any one operand are implicity requiring AVX512VL support if the actual
5375 operand size is YMMword or XMMword. Since this function runs after
5376 template matching, there's no need to check for YMMword/XMMword in
5378 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5379 if (!cpu_flags_all_zero (&cpu
)
5380 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5381 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5383 for (op
= 0; op
< t
->operands
; ++op
)
5385 if (t
->operand_types
[op
].bitfield
.zmmword
5386 && (i
.types
[op
].bitfield
.ymmword
5387 || i
.types
[op
].bitfield
.xmmword
))
5389 i
.error
= unsupported
;
5395 /* Without VSIB byte, we can't have a vector register for index. */
5396 if (!t
->opcode_modifier
.vecsib
5398 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5399 || i
.index_reg
->reg_type
.bitfield
.ymmword
5400 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5402 i
.error
= unsupported_vector_index_register
;
5406 /* Check if default mask is allowed. */
5407 if (t
->opcode_modifier
.nodefmask
5408 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5410 i
.error
= no_default_mask
;
5414 /* For VSIB byte, we need a vector register for index, and all vector
5415 registers must be distinct. */
5416 if (t
->opcode_modifier
.vecsib
)
5419 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5420 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5421 || (t
->opcode_modifier
.vecsib
== VecSIB256
5422 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5423 || (t
->opcode_modifier
.vecsib
== VecSIB512
5424 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5426 i
.error
= invalid_vsib_address
;
5430 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5431 if (i
.reg_operands
== 2 && !i
.mask
)
5433 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5434 gas_assert (i
.types
[0].bitfield
.xmmword
5435 || i
.types
[0].bitfield
.ymmword
);
5436 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5437 gas_assert (i
.types
[2].bitfield
.xmmword
5438 || i
.types
[2].bitfield
.ymmword
);
5439 if (operand_check
== check_none
)
5441 if (register_number (i
.op
[0].regs
)
5442 != register_number (i
.index_reg
)
5443 && register_number (i
.op
[2].regs
)
5444 != register_number (i
.index_reg
)
5445 && register_number (i
.op
[0].regs
)
5446 != register_number (i
.op
[2].regs
))
5448 if (operand_check
== check_error
)
5450 i
.error
= invalid_vector_register_set
;
5453 as_warn (_("mask, index, and destination registers should be distinct"));
5455 else if (i
.reg_operands
== 1 && i
.mask
)
5457 if (i
.types
[1].bitfield
.class == RegSIMD
5458 && (i
.types
[1].bitfield
.xmmword
5459 || i
.types
[1].bitfield
.ymmword
5460 || i
.types
[1].bitfield
.zmmword
)
5461 && (register_number (i
.op
[1].regs
)
5462 == register_number (i
.index_reg
)))
5464 if (operand_check
== check_error
)
5466 i
.error
= invalid_vector_register_set
;
5469 if (operand_check
!= check_none
)
5470 as_warn (_("index and destination registers should be distinct"));
5475 /* Check if broadcast is supported by the instruction and is applied
5476 to the memory operand. */
5479 i386_operand_type type
, overlap
;
5481 /* Check if specified broadcast is supported in this instruction,
5482 and its broadcast bytes match the memory operand. */
5483 op
= i
.broadcast
->operand
;
5484 if (!t
->opcode_modifier
.broadcast
5485 || !(i
.flags
[op
] & Operand_Mem
)
5486 || (!i
.types
[op
].bitfield
.unspecified
5487 && !match_broadcast_size (t
, op
)))
5490 i
.error
= unsupported_broadcast
;
5494 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5495 * i
.broadcast
->type
);
5496 operand_type_set (&type
, 0);
5497 switch (i
.broadcast
->bytes
)
5500 type
.bitfield
.word
= 1;
5503 type
.bitfield
.dword
= 1;
5506 type
.bitfield
.qword
= 1;
5509 type
.bitfield
.xmmword
= 1;
5512 type
.bitfield
.ymmword
= 1;
5515 type
.bitfield
.zmmword
= 1;
5521 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5522 if (operand_type_all_zero (&overlap
))
5525 if (t
->opcode_modifier
.checkregsize
)
5529 type
.bitfield
.baseindex
= 1;
5530 for (j
= 0; j
< i
.operands
; ++j
)
5533 && !operand_type_register_match(i
.types
[j
],
5534 t
->operand_types
[j
],
5536 t
->operand_types
[op
]))
5541 /* If broadcast is supported in this instruction, we need to check if
5542 operand of one-element size isn't specified without broadcast. */
5543 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5545 /* Find memory operand. */
5546 for (op
= 0; op
< i
.operands
; op
++)
5547 if (i
.flags
[op
] & Operand_Mem
)
5549 gas_assert (op
< i
.operands
);
5550 /* Check size of the memory operand. */
5551 if (match_broadcast_size (t
, op
))
5553 i
.error
= broadcast_needed
;
5558 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5560 /* Check if requested masking is supported. */
5563 switch (t
->opcode_modifier
.masking
)
5567 case MERGING_MASKING
:
5568 if (i
.mask
->zeroing
)
5571 i
.error
= unsupported_masking
;
5575 case DYNAMIC_MASKING
:
5576 /* Memory destinations allow only merging masking. */
5577 if (i
.mask
->zeroing
&& i
.mem_operands
)
5579 /* Find memory operand. */
5580 for (op
= 0; op
< i
.operands
; op
++)
5581 if (i
.flags
[op
] & Operand_Mem
)
5583 gas_assert (op
< i
.operands
);
5584 if (op
== i
.operands
- 1)
5586 i
.error
= unsupported_masking
;
5596 /* Check if masking is applied to dest operand. */
5597 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5599 i
.error
= mask_not_on_destination
;
5606 if (!t
->opcode_modifier
.sae
5607 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5609 i
.error
= unsupported_rc_sae
;
5612 /* If the instruction has several immediate operands and one of
5613 them is rounding, the rounding operand should be the last
5614 immediate operand. */
5615 if (i
.imm_operands
> 1
5616 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5618 i
.error
= rc_sae_operand_not_last_imm
;
5623 /* Check vector Disp8 operand. */
5624 if (t
->opcode_modifier
.disp8memshift
5625 && i
.disp_encoding
!= disp_encoding_32bit
)
5628 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5629 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5630 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5633 const i386_operand_type
*type
= NULL
;
5636 for (op
= 0; op
< i
.operands
; op
++)
5637 if (i
.flags
[op
] & Operand_Mem
)
5639 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5640 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5641 else if (t
->operand_types
[op
].bitfield
.xmmword
5642 + t
->operand_types
[op
].bitfield
.ymmword
5643 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5644 type
= &t
->operand_types
[op
];
5645 else if (!i
.types
[op
].bitfield
.unspecified
)
5646 type
= &i
.types
[op
];
5648 else if (i
.types
[op
].bitfield
.class == RegSIMD
5649 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5651 if (i
.types
[op
].bitfield
.zmmword
)
5653 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5655 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5661 if (type
->bitfield
.zmmword
)
5663 else if (type
->bitfield
.ymmword
)
5665 else if (type
->bitfield
.xmmword
)
5669 /* For the check in fits_in_disp8(). */
5670 if (i
.memshift
== 0)
5674 for (op
= 0; op
< i
.operands
; op
++)
5675 if (operand_type_check (i
.types
[op
], disp
)
5676 && i
.op
[op
].disps
->X_op
== O_constant
)
5678 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5680 i
.types
[op
].bitfield
.disp8
= 1;
5683 i
.types
[op
].bitfield
.disp8
= 0;
5692 /* Check if operands are valid for the instruction. Update VEX
5696 VEX_check_operands (const insn_template
*t
)
5698 if (i
.vec_encoding
== vex_encoding_evex
)
5700 /* This instruction must be encoded with EVEX prefix. */
5701 if (!is_evex_encoding (t
))
5703 i
.error
= unsupported
;
5709 if (!t
->opcode_modifier
.vex
)
5711 /* This instruction template doesn't have VEX prefix. */
5712 if (i
.vec_encoding
!= vex_encoding_default
)
5714 i
.error
= unsupported
;
5720 /* Check the special Imm4 cases; must be the first operand. */
5721 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
5723 if (i
.op
[0].imms
->X_op
!= O_constant
5724 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5730 /* Turn off Imm<N> so that update_imm won't complain. */
5731 operand_type_set (&i
.types
[0], 0);
5737 static const insn_template
*
5738 match_template (char mnem_suffix
)
5740 /* Points to template once we've found it. */
5741 const insn_template
*t
;
5742 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5743 i386_operand_type overlap4
;
5744 unsigned int found_reverse_match
;
5745 i386_opcode_modifier suffix_check
;
5746 i386_operand_type operand_types
[MAX_OPERANDS
];
5747 int addr_prefix_disp
;
5749 unsigned int found_cpu_match
, size_match
;
5750 unsigned int check_register
;
5751 enum i386_error specific_error
= 0;
5753 #if MAX_OPERANDS != 5
5754 # error "MAX_OPERANDS must be 5."
5757 found_reverse_match
= 0;
5758 addr_prefix_disp
= -1;
5760 /* Prepare for mnemonic suffix check. */
5761 memset (&suffix_check
, 0, sizeof (suffix_check
));
5762 switch (mnem_suffix
)
5764 case BYTE_MNEM_SUFFIX
:
5765 suffix_check
.no_bsuf
= 1;
5767 case WORD_MNEM_SUFFIX
:
5768 suffix_check
.no_wsuf
= 1;
5770 case SHORT_MNEM_SUFFIX
:
5771 suffix_check
.no_ssuf
= 1;
5773 case LONG_MNEM_SUFFIX
:
5774 suffix_check
.no_lsuf
= 1;
5776 case QWORD_MNEM_SUFFIX
:
5777 suffix_check
.no_qsuf
= 1;
5780 /* NB: In Intel syntax, normally we can check for memory operand
5781 size when there is no mnemonic suffix. But jmp and call have
5782 2 different encodings with Dword memory operand size, one with
5783 No_ldSuf and the other without. i.suffix is set to
5784 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
5785 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5786 suffix_check
.no_ldsuf
= 1;
5789 /* Must have right number of operands. */
5790 i
.error
= number_of_operands_mismatch
;
5792 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5794 addr_prefix_disp
= -1;
5795 found_reverse_match
= 0;
5797 if (i
.operands
!= t
->operands
)
5800 /* Check processor support. */
5801 i
.error
= unsupported
;
5802 found_cpu_match
= (cpu_flags_match (t
)
5803 == CPU_FLAGS_PERFECT_MATCH
);
5804 if (!found_cpu_match
)
5807 /* Check AT&T mnemonic. */
5808 i
.error
= unsupported_with_intel_mnemonic
;
5809 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5812 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5813 i
.error
= unsupported_syntax
;
5814 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5815 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5816 || (intel64
&& t
->opcode_modifier
.amd64
)
5817 || (!intel64
&& t
->opcode_modifier
.intel64
))
5820 /* Check the suffix. */
5821 i
.error
= invalid_instruction_suffix
;
5822 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5823 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5824 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5825 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5826 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5827 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
5830 size_match
= operand_size_match (t
);
5834 /* This is intentionally not
5836 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
5838 as the case of a missing * on the operand is accepted (perhaps with
5839 a warning, issued further down). */
5840 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
5842 i
.error
= operand_type_mismatch
;
5846 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5847 operand_types
[j
] = t
->operand_types
[j
];
5849 /* In general, don't allow 64-bit operands in 32-bit mode. */
5850 if (i
.suffix
== QWORD_MNEM_SUFFIX
5851 && flag_code
!= CODE_64BIT
5853 ? (!t
->opcode_modifier
.ignoresize
5854 && !t
->opcode_modifier
.broadcast
5855 && !intel_float_operand (t
->name
))
5856 : intel_float_operand (t
->name
) != 2)
5857 && ((operand_types
[0].bitfield
.class != RegMMX
5858 && operand_types
[0].bitfield
.class != RegSIMD
)
5859 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5860 && operand_types
[t
->operands
> 1].bitfield
.class != RegSIMD
))
5861 && (t
->base_opcode
!= 0x0fc7
5862 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5865 /* In general, don't allow 32-bit operands on pre-386. */
5866 else if (i
.suffix
== LONG_MNEM_SUFFIX
5867 && !cpu_arch_flags
.bitfield
.cpui386
5869 ? (!t
->opcode_modifier
.ignoresize
5870 && !intel_float_operand (t
->name
))
5871 : intel_float_operand (t
->name
) != 2)
5872 && ((operand_types
[0].bitfield
.class != RegMMX
5873 && operand_types
[0].bitfield
.class != RegSIMD
)
5874 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5875 && operand_types
[t
->operands
> 1].bitfield
.class
5879 /* Do not verify operands when there are none. */
5883 /* We've found a match; break out of loop. */
5887 if (!t
->opcode_modifier
.jump
5888 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
5890 /* There should be only one Disp operand. */
5891 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5892 if (operand_type_check (operand_types
[j
], disp
))
5894 if (j
< MAX_OPERANDS
)
5896 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
5898 addr_prefix_disp
= j
;
5900 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
5901 operand into Disp32/Disp32/Disp16/Disp32 operand. */
5905 override
= !override
;
5908 if (operand_types
[j
].bitfield
.disp32
5909 && operand_types
[j
].bitfield
.disp16
)
5911 operand_types
[j
].bitfield
.disp16
= override
;
5912 operand_types
[j
].bitfield
.disp32
= !override
;
5914 operand_types
[j
].bitfield
.disp32s
= 0;
5915 operand_types
[j
].bitfield
.disp64
= 0;
5919 if (operand_types
[j
].bitfield
.disp32s
5920 || operand_types
[j
].bitfield
.disp64
)
5922 operand_types
[j
].bitfield
.disp64
&= !override
;
5923 operand_types
[j
].bitfield
.disp32s
&= !override
;
5924 operand_types
[j
].bitfield
.disp32
= override
;
5926 operand_types
[j
].bitfield
.disp16
= 0;
5932 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5933 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5936 /* We check register size if needed. */
5937 if (t
->opcode_modifier
.checkregsize
)
5939 check_register
= (1 << t
->operands
) - 1;
5941 check_register
&= ~(1 << i
.broadcast
->operand
);
5946 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5947 switch (t
->operands
)
5950 if (!operand_type_match (overlap0
, i
.types
[0]))
5954 /* xchg %eax, %eax is a special case. It is an alias for nop
5955 only in 32bit mode and we can use opcode 0x90. In 64bit
5956 mode, we can't use 0x90 for xchg %eax, %eax since it should
5957 zero-extend %eax to %rax. */
5958 if (flag_code
== CODE_64BIT
5959 && t
->base_opcode
== 0x90
5960 && i
.types
[0].bitfield
.instance
== Accum
5961 && i
.types
[0].bitfield
.dword
5962 && i
.types
[1].bitfield
.instance
== Accum
5963 && i
.types
[1].bitfield
.dword
)
5965 /* xrelease mov %eax, <disp> is another special case. It must not
5966 match the accumulator-only encoding of mov. */
5967 if (flag_code
!= CODE_64BIT
5969 && t
->base_opcode
== 0xa0
5970 && i
.types
[0].bitfield
.instance
== Accum
5971 && (i
.flags
[1] & Operand_Mem
))
5976 if (!(size_match
& MATCH_STRAIGHT
))
5978 /* Reverse direction of operands if swapping is possible in the first
5979 place (operands need to be symmetric) and
5980 - the load form is requested, and the template is a store form,
5981 - the store form is requested, and the template is a load form,
5982 - the non-default (swapped) form is requested. */
5983 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5984 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5985 && !operand_type_all_zero (&overlap1
))
5986 switch (i
.dir_encoding
)
5988 case dir_encoding_load
:
5989 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5990 || t
->opcode_modifier
.regmem
)
5994 case dir_encoding_store
:
5995 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5996 && !t
->opcode_modifier
.regmem
)
6000 case dir_encoding_swap
:
6003 case dir_encoding_default
:
6006 /* If we want store form, we skip the current load. */
6007 if ((i
.dir_encoding
== dir_encoding_store
6008 || i
.dir_encoding
== dir_encoding_swap
)
6009 && i
.mem_operands
== 0
6010 && t
->opcode_modifier
.load
)
6015 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6016 if (!operand_type_match (overlap0
, i
.types
[0])
6017 || !operand_type_match (overlap1
, i
.types
[1])
6018 || ((check_register
& 3) == 3
6019 && !operand_type_register_match (i
.types
[0],
6024 /* Check if other direction is valid ... */
6025 if (!t
->opcode_modifier
.d
)
6029 if (!(size_match
& MATCH_REVERSE
))
6031 /* Try reversing direction of operands. */
6032 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6033 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6034 if (!operand_type_match (overlap0
, i
.types
[0])
6035 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6037 && !operand_type_register_match (i
.types
[0],
6038 operand_types
[i
.operands
- 1],
6039 i
.types
[i
.operands
- 1],
6042 /* Does not match either direction. */
6045 /* found_reverse_match holds which of D or FloatR
6047 if (!t
->opcode_modifier
.d
)
6048 found_reverse_match
= 0;
6049 else if (operand_types
[0].bitfield
.tbyte
)
6050 found_reverse_match
= Opcode_FloatD
;
6051 else if (operand_types
[0].bitfield
.xmmword
6052 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6053 || operand_types
[0].bitfield
.class == RegMMX
6054 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6055 || is_any_vex_encoding(t
))
6056 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6057 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6059 found_reverse_match
= Opcode_D
;
6060 if (t
->opcode_modifier
.floatr
)
6061 found_reverse_match
|= Opcode_FloatR
;
6065 /* Found a forward 2 operand match here. */
6066 switch (t
->operands
)
6069 overlap4
= operand_type_and (i
.types
[4],
6073 overlap3
= operand_type_and (i
.types
[3],
6077 overlap2
= operand_type_and (i
.types
[2],
6082 switch (t
->operands
)
6085 if (!operand_type_match (overlap4
, i
.types
[4])
6086 || !operand_type_register_match (i
.types
[3],
6093 if (!operand_type_match (overlap3
, i
.types
[3])
6094 || ((check_register
& 0xa) == 0xa
6095 && !operand_type_register_match (i
.types
[1],
6099 || ((check_register
& 0xc) == 0xc
6100 && !operand_type_register_match (i
.types
[2],
6107 /* Here we make use of the fact that there are no
6108 reverse match 3 operand instructions. */
6109 if (!operand_type_match (overlap2
, i
.types
[2])
6110 || ((check_register
& 5) == 5
6111 && !operand_type_register_match (i
.types
[0],
6115 || ((check_register
& 6) == 6
6116 && !operand_type_register_match (i
.types
[1],
6124 /* Found either forward/reverse 2, 3 or 4 operand match here:
6125 slip through to break. */
6127 if (!found_cpu_match
)
6130 /* Check if vector and VEX operands are valid. */
6131 if (check_VecOperands (t
) || VEX_check_operands (t
))
6133 specific_error
= i
.error
;
6137 /* We've found a match; break out of loop. */
6141 if (t
== current_templates
->end
)
6143 /* We found no match. */
6144 const char *err_msg
;
6145 switch (specific_error
? specific_error
: i
.error
)
6149 case operand_size_mismatch
:
6150 err_msg
= _("operand size mismatch");
6152 case operand_type_mismatch
:
6153 err_msg
= _("operand type mismatch");
6155 case register_type_mismatch
:
6156 err_msg
= _("register type mismatch");
6158 case number_of_operands_mismatch
:
6159 err_msg
= _("number of operands mismatch");
6161 case invalid_instruction_suffix
:
6162 err_msg
= _("invalid instruction suffix");
6165 err_msg
= _("constant doesn't fit in 4 bits");
6167 case unsupported_with_intel_mnemonic
:
6168 err_msg
= _("unsupported with Intel mnemonic");
6170 case unsupported_syntax
:
6171 err_msg
= _("unsupported syntax");
6174 as_bad (_("unsupported instruction `%s'"),
6175 current_templates
->start
->name
);
6177 case invalid_vsib_address
:
6178 err_msg
= _("invalid VSIB address");
6180 case invalid_vector_register_set
:
6181 err_msg
= _("mask, index, and destination registers must be distinct");
6183 case unsupported_vector_index_register
:
6184 err_msg
= _("unsupported vector index register");
6186 case unsupported_broadcast
:
6187 err_msg
= _("unsupported broadcast");
6189 case broadcast_needed
:
6190 err_msg
= _("broadcast is needed for operand of such type");
6192 case unsupported_masking
:
6193 err_msg
= _("unsupported masking");
6195 case mask_not_on_destination
:
6196 err_msg
= _("mask not on destination operand");
6198 case no_default_mask
:
6199 err_msg
= _("default mask isn't allowed");
6201 case unsupported_rc_sae
:
6202 err_msg
= _("unsupported static rounding/sae");
6204 case rc_sae_operand_not_last_imm
:
6206 err_msg
= _("RC/SAE operand must precede immediate operands");
6208 err_msg
= _("RC/SAE operand must follow immediate operands");
6210 case invalid_register_operand
:
6211 err_msg
= _("invalid register operand");
6214 as_bad (_("%s for `%s'"), err_msg
,
6215 current_templates
->start
->name
);
6219 if (!quiet_warnings
)
6222 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6223 as_warn (_("indirect %s without `*'"), t
->name
);
6225 if (t
->opcode_modifier
.isprefix
6226 && t
->opcode_modifier
.ignoresize
)
6228 /* Warn them that a data or address size prefix doesn't
6229 affect assembly of the next line of code. */
6230 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6234 /* Copy the template we found. */
6237 if (addr_prefix_disp
!= -1)
6238 i
.tm
.operand_types
[addr_prefix_disp
]
6239 = operand_types
[addr_prefix_disp
];
6241 if (found_reverse_match
)
6243 /* If we found a reverse match we must alter the opcode direction
6244 bit and clear/flip the regmem modifier one. found_reverse_match
6245 holds bits to change (different for int & float insns). */
6247 i
.tm
.base_opcode
^= found_reverse_match
;
6249 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6250 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6252 /* Certain SIMD insns have their load forms specified in the opcode
6253 table, and hence we need to _set_ RegMem instead of clearing it.
6254 We need to avoid setting the bit though on insns like KMOVW. */
6255 i
.tm
.opcode_modifier
.regmem
6256 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6257 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6258 && !i
.tm
.opcode_modifier
.regmem
;
6267 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6268 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6270 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6272 as_bad (_("`%s' operand %u must use `%ses' segment"),
6274 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6279 /* There's only ever one segment override allowed per instruction.
6280 This instruction possibly has a legal segment override on the
6281 second operand, so copy the segment to where non-string
6282 instructions store it, allowing common code. */
6283 i
.seg
[op
] = i
.seg
[1];
6289 process_suffix (void)
6291 /* If matched instruction specifies an explicit instruction mnemonic
6293 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6294 i
.suffix
= WORD_MNEM_SUFFIX
;
6295 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6296 i
.suffix
= LONG_MNEM_SUFFIX
;
6297 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6298 i
.suffix
= QWORD_MNEM_SUFFIX
;
6299 else if (i
.reg_operands
6300 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
))
6302 /* If there's no instruction mnemonic suffix we try to invent one
6303 based on GPR operands. */
6306 /* We take i.suffix from the last register operand specified,
6307 Destination register type is more significant than source
6308 register type. crc32 in SSE4.2 prefers source register
6310 if (i
.tm
.base_opcode
== 0xf20f38f0
6311 && i
.types
[0].bitfield
.class == Reg
)
6313 if (i
.types
[0].bitfield
.byte
)
6314 i
.suffix
= BYTE_MNEM_SUFFIX
;
6315 else if (i
.types
[0].bitfield
.word
)
6316 i
.suffix
= WORD_MNEM_SUFFIX
;
6317 else if (i
.types
[0].bitfield
.dword
)
6318 i
.suffix
= LONG_MNEM_SUFFIX
;
6319 else if (i
.types
[0].bitfield
.qword
)
6320 i
.suffix
= QWORD_MNEM_SUFFIX
;
6327 if (i
.tm
.base_opcode
== 0xf20f38f0)
6329 /* We have to know the operand size for crc32. */
6330 as_bad (_("ambiguous memory operand size for `%s`"),
6335 for (op
= i
.operands
; --op
>= 0;)
6336 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6337 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6339 if (i
.types
[op
].bitfield
.class != Reg
)
6341 if (i
.types
[op
].bitfield
.byte
)
6342 i
.suffix
= BYTE_MNEM_SUFFIX
;
6343 else if (i
.types
[op
].bitfield
.word
)
6344 i
.suffix
= WORD_MNEM_SUFFIX
;
6345 else if (i
.types
[op
].bitfield
.dword
)
6346 i
.suffix
= LONG_MNEM_SUFFIX
;
6347 else if (i
.types
[op
].bitfield
.qword
)
6348 i
.suffix
= QWORD_MNEM_SUFFIX
;
6355 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6358 && i
.tm
.opcode_modifier
.ignoresize
6359 && i
.tm
.opcode_modifier
.no_bsuf
)
6361 else if (!check_byte_reg ())
6364 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6367 && i
.tm
.opcode_modifier
.ignoresize
6368 && i
.tm
.opcode_modifier
.no_lsuf
6369 && !i
.tm
.opcode_modifier
.todword
6370 && !i
.tm
.opcode_modifier
.toqword
)
6372 else if (!check_long_reg ())
6375 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6378 && i
.tm
.opcode_modifier
.ignoresize
6379 && i
.tm
.opcode_modifier
.no_qsuf
6380 && !i
.tm
.opcode_modifier
.todword
6381 && !i
.tm
.opcode_modifier
.toqword
)
6383 else if (!check_qword_reg ())
6386 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6389 && i
.tm
.opcode_modifier
.ignoresize
6390 && i
.tm
.opcode_modifier
.no_wsuf
)
6392 else if (!check_word_reg ())
6395 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6396 /* Do nothing if the instruction is going to ignore the prefix. */
6401 else if (i
.tm
.opcode_modifier
.defaultsize
6403 /* exclude fldenv/frstor/fsave/fstenv */
6404 && i
.tm
.opcode_modifier
.no_ssuf
6405 /* exclude sysret */
6406 && i
.tm
.base_opcode
!= 0x0f07)
6408 i
.suffix
= stackop_size
;
6409 if (stackop_size
== LONG_MNEM_SUFFIX
)
6411 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6412 .code16gcc directive to support 16-bit mode with
6413 32-bit address. For IRET without a suffix, generate
6414 16-bit IRET (opcode 0xcf) to return from an interrupt
6416 if (i
.tm
.base_opcode
== 0xcf)
6418 i
.suffix
= WORD_MNEM_SUFFIX
;
6419 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6421 /* Warn about changed behavior for segment register push/pop. */
6422 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6423 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6427 else if (intel_syntax
6429 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6430 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6431 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6432 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6433 && i
.tm
.extension_opcode
<= 3)))
6438 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6440 i
.suffix
= QWORD_MNEM_SUFFIX
;
6445 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6446 i
.suffix
= LONG_MNEM_SUFFIX
;
6449 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6450 i
.suffix
= WORD_MNEM_SUFFIX
;
6459 if (i
.tm
.opcode_modifier
.w
)
6461 as_bad (_("no instruction mnemonic suffix given and "
6462 "no register operands; can't size instruction"));
6468 unsigned int suffixes
;
6470 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6471 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6473 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6475 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6477 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6479 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6482 /* There are more than suffix matches. */
6483 if (i
.tm
.opcode_modifier
.w
6484 || ((suffixes
& (suffixes
- 1))
6485 && !i
.tm
.opcode_modifier
.defaultsize
6486 && !i
.tm
.opcode_modifier
.ignoresize
))
6488 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6494 /* Change the opcode based on the operand size given by i.suffix. */
6497 /* Size floating point instruction. */
6498 case LONG_MNEM_SUFFIX
:
6499 if (i
.tm
.opcode_modifier
.floatmf
)
6501 i
.tm
.base_opcode
^= 4;
6505 case WORD_MNEM_SUFFIX
:
6506 case QWORD_MNEM_SUFFIX
:
6507 /* It's not a byte, select word/dword operation. */
6508 if (i
.tm
.opcode_modifier
.w
)
6510 if (i
.tm
.opcode_modifier
.shortform
)
6511 i
.tm
.base_opcode
|= 8;
6513 i
.tm
.base_opcode
|= 1;
6516 case SHORT_MNEM_SUFFIX
:
6517 /* Now select between word & dword operations via the operand
6518 size prefix, except for instructions that will ignore this
6520 if (i
.reg_operands
> 0
6521 && i
.types
[0].bitfield
.class == Reg
6522 && i
.tm
.opcode_modifier
.addrprefixopreg
6523 && (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6524 || i
.operands
== 1))
6526 /* The address size override prefix changes the size of the
6528 if ((flag_code
== CODE_32BIT
6529 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6530 || (flag_code
!= CODE_32BIT
6531 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6532 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6535 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6536 && !i
.tm
.opcode_modifier
.ignoresize
6537 && !i
.tm
.opcode_modifier
.floatmf
6538 && !is_any_vex_encoding (&i
.tm
)
6539 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6540 || (flag_code
== CODE_64BIT
6541 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
6543 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6545 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
6546 prefix
= ADDR_PREFIX_OPCODE
;
6548 if (!add_prefix (prefix
))
6552 /* Set mode64 for an operand. */
6553 if (i
.suffix
== QWORD_MNEM_SUFFIX
6554 && flag_code
== CODE_64BIT
6555 && !i
.tm
.opcode_modifier
.norex64
6556 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6558 && ! (i
.operands
== 2
6559 && i
.tm
.base_opcode
== 0x90
6560 && i
.tm
.extension_opcode
== None
6561 && i
.types
[0].bitfield
.instance
== Accum
6562 && i
.types
[0].bitfield
.qword
6563 && i
.types
[1].bitfield
.instance
== Accum
6564 && i
.types
[1].bitfield
.qword
))
6570 if (i
.reg_operands
!= 0
6572 && i
.tm
.opcode_modifier
.addrprefixopreg
6573 && i
.tm
.operand_types
[0].bitfield
.instance
!= Accum
)
6575 /* Check invalid register operand when the address size override
6576 prefix changes the size of register operands. */
6578 enum { need_word
, need_dword
, need_qword
} need
;
6580 if (flag_code
== CODE_32BIT
)
6581 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6584 if (i
.prefix
[ADDR_PREFIX
])
6587 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6590 for (op
= 0; op
< i
.operands
; op
++)
6591 if (i
.types
[op
].bitfield
.class == Reg
6592 && ((need
== need_word
6593 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6594 || (need
== need_dword
6595 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6596 || (need
== need_qword
6597 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6599 as_bad (_("invalid register operand size for `%s'"),
6609 check_byte_reg (void)
6613 for (op
= i
.operands
; --op
>= 0;)
6615 /* Skip non-register operands. */
6616 if (i
.types
[op
].bitfield
.class != Reg
)
6619 /* If this is an eight bit register, it's OK. If it's the 16 or
6620 32 bit version of an eight bit register, we will just use the
6621 low portion, and that's OK too. */
6622 if (i
.types
[op
].bitfield
.byte
)
6625 /* I/O port address operands are OK too. */
6626 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
6627 && i
.tm
.operand_types
[op
].bitfield
.word
)
6630 /* crc32 doesn't generate this warning. */
6631 if (i
.tm
.base_opcode
== 0xf20f38f0)
6634 if ((i
.types
[op
].bitfield
.word
6635 || i
.types
[op
].bitfield
.dword
6636 || i
.types
[op
].bitfield
.qword
)
6637 && i
.op
[op
].regs
->reg_num
< 4
6638 /* Prohibit these changes in 64bit mode, since the lowering
6639 would be more complicated. */
6640 && flag_code
!= CODE_64BIT
)
6642 #if REGISTER_WARNINGS
6643 if (!quiet_warnings
)
6644 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6646 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6647 ? REGNAM_AL
- REGNAM_AX
6648 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6650 i
.op
[op
].regs
->reg_name
,
6655 /* Any other register is bad. */
6656 if (i
.types
[op
].bitfield
.class == Reg
6657 || i
.types
[op
].bitfield
.class == RegMMX
6658 || i
.types
[op
].bitfield
.class == RegSIMD
6659 || i
.types
[op
].bitfield
.class == SReg
6660 || i
.types
[op
].bitfield
.class == RegCR
6661 || i
.types
[op
].bitfield
.class == RegDR
6662 || i
.types
[op
].bitfield
.class == RegTR
)
6664 as_bad (_("`%s%s' not allowed with `%s%c'"),
6666 i
.op
[op
].regs
->reg_name
,
6676 check_long_reg (void)
6680 for (op
= i
.operands
; --op
>= 0;)
6681 /* Skip non-register operands. */
6682 if (i
.types
[op
].bitfield
.class != Reg
)
6684 /* Reject eight bit registers, except where the template requires
6685 them. (eg. movzb) */
6686 else if (i
.types
[op
].bitfield
.byte
6687 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6688 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6689 && (i
.tm
.operand_types
[op
].bitfield
.word
6690 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6692 as_bad (_("`%s%s' not allowed with `%s%c'"),
6694 i
.op
[op
].regs
->reg_name
,
6699 /* Warn if the e prefix on a general reg is missing. */
6700 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6701 && i
.types
[op
].bitfield
.word
6702 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6703 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6704 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6706 /* Prohibit these changes in the 64bit mode, since the
6707 lowering is more complicated. */
6708 if (flag_code
== CODE_64BIT
)
6710 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6711 register_prefix
, i
.op
[op
].regs
->reg_name
,
6715 #if REGISTER_WARNINGS
6716 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6718 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6719 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6722 /* Warn if the r prefix on a general reg is present. */
6723 else if (i
.types
[op
].bitfield
.qword
6724 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6725 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6726 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6729 && i
.tm
.opcode_modifier
.toqword
6730 && i
.types
[0].bitfield
.class != RegSIMD
)
6732 /* Convert to QWORD. We want REX byte. */
6733 i
.suffix
= QWORD_MNEM_SUFFIX
;
6737 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6738 register_prefix
, i
.op
[op
].regs
->reg_name
,
6747 check_qword_reg (void)
6751 for (op
= i
.operands
; --op
>= 0; )
6752 /* Skip non-register operands. */
6753 if (i
.types
[op
].bitfield
.class != Reg
)
6755 /* Reject eight bit registers, except where the template requires
6756 them. (eg. movzb) */
6757 else if (i
.types
[op
].bitfield
.byte
6758 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6759 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6760 && (i
.tm
.operand_types
[op
].bitfield
.word
6761 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6763 as_bad (_("`%s%s' not allowed with `%s%c'"),
6765 i
.op
[op
].regs
->reg_name
,
6770 /* Warn if the r prefix on a general reg is missing. */
6771 else if ((i
.types
[op
].bitfield
.word
6772 || i
.types
[op
].bitfield
.dword
)
6773 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6774 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6775 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6777 /* Prohibit these changes in the 64bit mode, since the
6778 lowering is more complicated. */
6780 && i
.tm
.opcode_modifier
.todword
6781 && i
.types
[0].bitfield
.class != RegSIMD
)
6783 /* Convert to DWORD. We don't want REX byte. */
6784 i
.suffix
= LONG_MNEM_SUFFIX
;
6788 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6789 register_prefix
, i
.op
[op
].regs
->reg_name
,
6798 check_word_reg (void)
6801 for (op
= i
.operands
; --op
>= 0;)
6802 /* Skip non-register operands. */
6803 if (i
.types
[op
].bitfield
.class != Reg
)
6805 /* Reject eight bit registers, except where the template requires
6806 them. (eg. movzb) */
6807 else if (i
.types
[op
].bitfield
.byte
6808 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6809 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6810 && (i
.tm
.operand_types
[op
].bitfield
.word
6811 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6813 as_bad (_("`%s%s' not allowed with `%s%c'"),
6815 i
.op
[op
].regs
->reg_name
,
6820 /* Warn if the e or r prefix on a general reg is present. */
6821 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6822 && (i
.types
[op
].bitfield
.dword
6823 || i
.types
[op
].bitfield
.qword
)
6824 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6825 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6826 && i
.tm
.operand_types
[op
].bitfield
.word
)
6828 /* Prohibit these changes in the 64bit mode, since the
6829 lowering is more complicated. */
6830 if (flag_code
== CODE_64BIT
)
6832 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6833 register_prefix
, i
.op
[op
].regs
->reg_name
,
6837 #if REGISTER_WARNINGS
6838 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6840 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6841 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6848 update_imm (unsigned int j
)
6850 i386_operand_type overlap
= i
.types
[j
];
6851 if ((overlap
.bitfield
.imm8
6852 || overlap
.bitfield
.imm8s
6853 || overlap
.bitfield
.imm16
6854 || overlap
.bitfield
.imm32
6855 || overlap
.bitfield
.imm32s
6856 || overlap
.bitfield
.imm64
)
6857 && !operand_type_equal (&overlap
, &imm8
)
6858 && !operand_type_equal (&overlap
, &imm8s
)
6859 && !operand_type_equal (&overlap
, &imm16
)
6860 && !operand_type_equal (&overlap
, &imm32
)
6861 && !operand_type_equal (&overlap
, &imm32s
)
6862 && !operand_type_equal (&overlap
, &imm64
))
6866 i386_operand_type temp
;
6868 operand_type_set (&temp
, 0);
6869 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6871 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6872 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6874 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6875 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6876 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6878 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6879 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6882 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6885 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6886 || operand_type_equal (&overlap
, &imm16_32
)
6887 || operand_type_equal (&overlap
, &imm16_32s
))
6889 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6894 if (!operand_type_equal (&overlap
, &imm8
)
6895 && !operand_type_equal (&overlap
, &imm8s
)
6896 && !operand_type_equal (&overlap
, &imm16
)
6897 && !operand_type_equal (&overlap
, &imm32
)
6898 && !operand_type_equal (&overlap
, &imm32s
)
6899 && !operand_type_equal (&overlap
, &imm64
))
6901 as_bad (_("no instruction mnemonic suffix given; "
6902 "can't determine immediate size"));
6906 i
.types
[j
] = overlap
;
6916 /* Update the first 2 immediate operands. */
6917 n
= i
.operands
> 2 ? 2 : i
.operands
;
6920 for (j
= 0; j
< n
; j
++)
6921 if (update_imm (j
) == 0)
6924 /* The 3rd operand can't be immediate operand. */
6925 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6932 process_operands (void)
6934 /* Default segment register this instruction will use for memory
6935 accesses. 0 means unknown. This is only for optimizing out
6936 unnecessary segment overrides. */
6937 const seg_entry
*default_seg
= 0;
6939 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6941 unsigned int dupl
= i
.operands
;
6942 unsigned int dest
= dupl
- 1;
6945 /* The destination must be an xmm register. */
6946 gas_assert (i
.reg_operands
6947 && MAX_OPERANDS
> dupl
6948 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6950 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6951 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6953 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6955 /* Keep xmm0 for instructions with VEX prefix and 3
6957 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
6958 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
6963 /* We remove the first xmm0 and keep the number of
6964 operands unchanged, which in fact duplicates the
6966 for (j
= 1; j
< i
.operands
; j
++)
6968 i
.op
[j
- 1] = i
.op
[j
];
6969 i
.types
[j
- 1] = i
.types
[j
];
6970 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6971 i
.flags
[j
- 1] = i
.flags
[j
];
6975 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6977 gas_assert ((MAX_OPERANDS
- 1) > dupl
6978 && (i
.tm
.opcode_modifier
.vexsources
6981 /* Add the implicit xmm0 for instructions with VEX prefix
6983 for (j
= i
.operands
; j
> 0; j
--)
6985 i
.op
[j
] = i
.op
[j
- 1];
6986 i
.types
[j
] = i
.types
[j
- 1];
6987 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6988 i
.flags
[j
] = i
.flags
[j
- 1];
6991 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6992 i
.types
[0] = regxmm
;
6993 i
.tm
.operand_types
[0] = regxmm
;
6996 i
.reg_operands
+= 2;
7001 i
.op
[dupl
] = i
.op
[dest
];
7002 i
.types
[dupl
] = i
.types
[dest
];
7003 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7004 i
.flags
[dupl
] = i
.flags
[dest
];
7013 i
.op
[dupl
] = i
.op
[dest
];
7014 i
.types
[dupl
] = i
.types
[dest
];
7015 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7016 i
.flags
[dupl
] = i
.flags
[dest
];
7019 if (i
.tm
.opcode_modifier
.immext
)
7022 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7023 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7027 for (j
= 1; j
< i
.operands
; j
++)
7029 i
.op
[j
- 1] = i
.op
[j
];
7030 i
.types
[j
- 1] = i
.types
[j
];
7032 /* We need to adjust fields in i.tm since they are used by
7033 build_modrm_byte. */
7034 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7036 i
.flags
[j
- 1] = i
.flags
[j
];
7043 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7045 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7047 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7048 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7049 regnum
= register_number (i
.op
[1].regs
);
7050 first_reg_in_group
= regnum
& ~3;
7051 last_reg_in_group
= first_reg_in_group
+ 3;
7052 if (regnum
!= first_reg_in_group
)
7053 as_warn (_("source register `%s%s' implicitly denotes"
7054 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7055 register_prefix
, i
.op
[1].regs
->reg_name
,
7056 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7057 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7060 else if (i
.tm
.opcode_modifier
.regkludge
)
7062 /* The imul $imm, %reg instruction is converted into
7063 imul $imm, %reg, %reg, and the clr %reg instruction
7064 is converted into xor %reg, %reg. */
7066 unsigned int first_reg_op
;
7068 if (operand_type_check (i
.types
[0], reg
))
7072 /* Pretend we saw the extra register operand. */
7073 gas_assert (i
.reg_operands
== 1
7074 && i
.op
[first_reg_op
+ 1].regs
== 0);
7075 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7076 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7081 if (i
.tm
.opcode_modifier
.modrm
)
7083 /* The opcode is completed (modulo i.tm.extension_opcode which
7084 must be put into the modrm byte). Now, we make the modrm and
7085 index base bytes based on all the info we've collected. */
7087 default_seg
= build_modrm_byte ();
7089 else if (i
.types
[0].bitfield
.class == SReg
)
7091 if (flag_code
!= CODE_64BIT
7092 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7093 && i
.op
[0].regs
->reg_num
== 1
7094 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7095 && i
.op
[0].regs
->reg_num
< 4)
7097 as_bad (_("you can't `%s %s%s'"),
7098 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7101 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7103 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7104 i
.tm
.opcode_length
= 2;
7106 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7108 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7112 else if (i
.tm
.opcode_modifier
.isstring
)
7114 /* For the string instructions that allow a segment override
7115 on one of their operands, the default segment is ds. */
7118 else if (i
.tm
.opcode_modifier
.shortform
)
7120 /* The register or float register operand is in operand
7122 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7124 /* Register goes in low 3 bits of opcode. */
7125 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7126 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7128 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7130 /* Warn about some common errors, but press on regardless.
7131 The first case can be generated by gcc (<= 2.8.1). */
7132 if (i
.operands
== 2)
7134 /* Reversed arguments on faddp, fsubp, etc. */
7135 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7136 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7137 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7141 /* Extraneous `l' suffix on fp insn. */
7142 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7143 register_prefix
, i
.op
[0].regs
->reg_name
);
7148 if (i
.tm
.base_opcode
== 0x8d /* lea */
7151 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7153 /* If a segment was explicitly specified, and the specified segment
7154 is not the default, use an opcode prefix to select it. If we
7155 never figured out what the default segment is, then default_seg
7156 will be zero at this point, and the specified segment prefix will
7158 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
7160 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7166 static const seg_entry
*
7167 build_modrm_byte (void)
7169 const seg_entry
*default_seg
= 0;
7170 unsigned int source
, dest
;
7173 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7176 unsigned int nds
, reg_slot
;
7179 dest
= i
.operands
- 1;
7182 /* There are 2 kinds of instructions:
7183 1. 5 operands: 4 register operands or 3 register operands
7184 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7185 VexW0 or VexW1. The destination must be either XMM, YMM or
7187 2. 4 operands: 4 register operands or 3 register operands
7188 plus 1 memory operand, with VexXDS. */
7189 gas_assert ((i
.reg_operands
== 4
7190 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7191 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7192 && i
.tm
.opcode_modifier
.vexw
7193 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7195 /* If VexW1 is set, the first non-immediate operand is the source and
7196 the second non-immediate one is encoded in the immediate operand. */
7197 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7199 source
= i
.imm_operands
;
7200 reg_slot
= i
.imm_operands
+ 1;
7204 source
= i
.imm_operands
+ 1;
7205 reg_slot
= i
.imm_operands
;
7208 if (i
.imm_operands
== 0)
7210 /* When there is no immediate operand, generate an 8bit
7211 immediate operand to encode the first operand. */
7212 exp
= &im_expressions
[i
.imm_operands
++];
7213 i
.op
[i
.operands
].imms
= exp
;
7214 i
.types
[i
.operands
] = imm8
;
7217 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7218 exp
->X_op
= O_constant
;
7219 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7220 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7224 gas_assert (i
.imm_operands
== 1);
7225 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7226 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7228 /* Turn on Imm8 again so that output_imm will generate it. */
7229 i
.types
[0].bitfield
.imm8
= 1;
7231 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7232 i
.op
[0].imms
->X_add_number
7233 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7234 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7237 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7238 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7243 /* i.reg_operands MUST be the number of real register operands;
7244 implicit registers do not count. If there are 3 register
7245 operands, it must be a instruction with VexNDS. For a
7246 instruction with VexNDD, the destination register is encoded
7247 in VEX prefix. If there are 4 register operands, it must be
7248 a instruction with VEX prefix and 3 sources. */
7249 if (i
.mem_operands
== 0
7250 && ((i
.reg_operands
== 2
7251 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7252 || (i
.reg_operands
== 3
7253 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7254 || (i
.reg_operands
== 4 && vex_3_sources
)))
7262 /* When there are 3 operands, one of them may be immediate,
7263 which may be the first or the last operand. Otherwise,
7264 the first operand must be shift count register (cl) or it
7265 is an instruction with VexNDS. */
7266 gas_assert (i
.imm_operands
== 1
7267 || (i
.imm_operands
== 0
7268 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7269 || (i
.types
[0].bitfield
.instance
== RegC
7270 && i
.types
[0].bitfield
.byte
))));
7271 if (operand_type_check (i
.types
[0], imm
)
7272 || (i
.types
[0].bitfield
.instance
== RegC
7273 && i
.types
[0].bitfield
.byte
))
7279 /* When there are 4 operands, the first two must be 8bit
7280 immediate operands. The source operand will be the 3rd
7283 For instructions with VexNDS, if the first operand
7284 an imm8, the source operand is the 2nd one. If the last
7285 operand is imm8, the source operand is the first one. */
7286 gas_assert ((i
.imm_operands
== 2
7287 && i
.types
[0].bitfield
.imm8
7288 && i
.types
[1].bitfield
.imm8
)
7289 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7290 && i
.imm_operands
== 1
7291 && (i
.types
[0].bitfield
.imm8
7292 || i
.types
[i
.operands
- 1].bitfield
.imm8
7294 if (i
.imm_operands
== 2)
7298 if (i
.types
[0].bitfield
.imm8
)
7305 if (is_evex_encoding (&i
.tm
))
7307 /* For EVEX instructions, when there are 5 operands, the
7308 first one must be immediate operand. If the second one
7309 is immediate operand, the source operand is the 3th
7310 one. If the last one is immediate operand, the source
7311 operand is the 2nd one. */
7312 gas_assert (i
.imm_operands
== 2
7313 && i
.tm
.opcode_modifier
.sae
7314 && operand_type_check (i
.types
[0], imm
));
7315 if (operand_type_check (i
.types
[1], imm
))
7317 else if (operand_type_check (i
.types
[4], imm
))
7331 /* RC/SAE operand could be between DEST and SRC. That happens
7332 when one operand is GPR and the other one is XMM/YMM/ZMM
7334 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7337 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7339 /* For instructions with VexNDS, the register-only source
7340 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7341 register. It is encoded in VEX prefix. */
7343 i386_operand_type op
;
7346 /* Check register-only source operand when two source
7347 operands are swapped. */
7348 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7349 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7357 op
= i
.tm
.operand_types
[vvvv
];
7358 if ((dest
+ 1) >= i
.operands
7359 || ((op
.bitfield
.class != Reg
7360 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7361 && op
.bitfield
.class != RegSIMD
7362 && !operand_type_equal (&op
, ®mask
)))
7364 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7370 /* One of the register operands will be encoded in the i.rm.reg
7371 field, the other in the combined i.rm.mode and i.rm.regmem
7372 fields. If no form of this instruction supports a memory
7373 destination operand, then we assume the source operand may
7374 sometimes be a memory operand and so we need to store the
7375 destination in the i.rm.reg field. */
7376 if (!i
.tm
.opcode_modifier
.regmem
7377 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7379 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7380 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7381 if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegMMX
7382 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegMMX
)
7383 i
.has_regmmx
= TRUE
;
7384 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegSIMD
7385 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegSIMD
)
7387 if (i
.types
[dest
].bitfield
.zmmword
7388 || i
.types
[source
].bitfield
.zmmword
)
7389 i
.has_regzmm
= TRUE
;
7390 else if (i
.types
[dest
].bitfield
.ymmword
7391 || i
.types
[source
].bitfield
.ymmword
)
7392 i
.has_regymm
= TRUE
;
7394 i
.has_regxmm
= TRUE
;
7396 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7398 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7400 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7402 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7407 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7408 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7409 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7411 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7413 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7415 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7418 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7420 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7423 add_prefix (LOCK_PREFIX_OPCODE
);
7427 { /* If it's not 2 reg operands... */
7432 unsigned int fake_zero_displacement
= 0;
7435 for (op
= 0; op
< i
.operands
; op
++)
7436 if (i
.flags
[op
] & Operand_Mem
)
7438 gas_assert (op
< i
.operands
);
7440 if (i
.tm
.opcode_modifier
.vecsib
)
7442 if (i
.index_reg
->reg_num
== RegIZ
)
7445 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7448 i
.sib
.base
= NO_BASE_REGISTER
;
7449 i
.sib
.scale
= i
.log2_scale_factor
;
7450 i
.types
[op
].bitfield
.disp8
= 0;
7451 i
.types
[op
].bitfield
.disp16
= 0;
7452 i
.types
[op
].bitfield
.disp64
= 0;
7453 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7455 /* Must be 32 bit */
7456 i
.types
[op
].bitfield
.disp32
= 1;
7457 i
.types
[op
].bitfield
.disp32s
= 0;
7461 i
.types
[op
].bitfield
.disp32
= 0;
7462 i
.types
[op
].bitfield
.disp32s
= 1;
7465 i
.sib
.index
= i
.index_reg
->reg_num
;
7466 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7468 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7474 if (i
.base_reg
== 0)
7477 if (!i
.disp_operands
)
7478 fake_zero_displacement
= 1;
7479 if (i
.index_reg
== 0)
7481 i386_operand_type newdisp
;
7483 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7484 /* Operand is just <disp> */
7485 if (flag_code
== CODE_64BIT
)
7487 /* 64bit mode overwrites the 32bit absolute
7488 addressing by RIP relative addressing and
7489 absolute addressing is encoded by one of the
7490 redundant SIB forms. */
7491 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7492 i
.sib
.base
= NO_BASE_REGISTER
;
7493 i
.sib
.index
= NO_INDEX_REGISTER
;
7494 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7496 else if ((flag_code
== CODE_16BIT
)
7497 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7499 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7504 i
.rm
.regmem
= NO_BASE_REGISTER
;
7507 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7508 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7510 else if (!i
.tm
.opcode_modifier
.vecsib
)
7512 /* !i.base_reg && i.index_reg */
7513 if (i
.index_reg
->reg_num
== RegIZ
)
7514 i
.sib
.index
= NO_INDEX_REGISTER
;
7516 i
.sib
.index
= i
.index_reg
->reg_num
;
7517 i
.sib
.base
= NO_BASE_REGISTER
;
7518 i
.sib
.scale
= i
.log2_scale_factor
;
7519 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7520 i
.types
[op
].bitfield
.disp8
= 0;
7521 i
.types
[op
].bitfield
.disp16
= 0;
7522 i
.types
[op
].bitfield
.disp64
= 0;
7523 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7525 /* Must be 32 bit */
7526 i
.types
[op
].bitfield
.disp32
= 1;
7527 i
.types
[op
].bitfield
.disp32s
= 0;
7531 i
.types
[op
].bitfield
.disp32
= 0;
7532 i
.types
[op
].bitfield
.disp32s
= 1;
7534 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7538 /* RIP addressing for 64bit mode. */
7539 else if (i
.base_reg
->reg_num
== RegIP
)
7541 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7542 i
.rm
.regmem
= NO_BASE_REGISTER
;
7543 i
.types
[op
].bitfield
.disp8
= 0;
7544 i
.types
[op
].bitfield
.disp16
= 0;
7545 i
.types
[op
].bitfield
.disp32
= 0;
7546 i
.types
[op
].bitfield
.disp32s
= 1;
7547 i
.types
[op
].bitfield
.disp64
= 0;
7548 i
.flags
[op
] |= Operand_PCrel
;
7549 if (! i
.disp_operands
)
7550 fake_zero_displacement
= 1;
7552 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7554 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7555 switch (i
.base_reg
->reg_num
)
7558 if (i
.index_reg
== 0)
7560 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7561 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7565 if (i
.index_reg
== 0)
7568 if (operand_type_check (i
.types
[op
], disp
) == 0)
7570 /* fake (%bp) into 0(%bp) */
7571 i
.types
[op
].bitfield
.disp8
= 1;
7572 fake_zero_displacement
= 1;
7575 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7576 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7578 default: /* (%si) -> 4 or (%di) -> 5 */
7579 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7581 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7583 else /* i.base_reg and 32/64 bit mode */
7585 if (flag_code
== CODE_64BIT
7586 && operand_type_check (i
.types
[op
], disp
))
7588 i
.types
[op
].bitfield
.disp16
= 0;
7589 i
.types
[op
].bitfield
.disp64
= 0;
7590 if (i
.prefix
[ADDR_PREFIX
] == 0)
7592 i
.types
[op
].bitfield
.disp32
= 0;
7593 i
.types
[op
].bitfield
.disp32s
= 1;
7597 i
.types
[op
].bitfield
.disp32
= 1;
7598 i
.types
[op
].bitfield
.disp32s
= 0;
7602 if (!i
.tm
.opcode_modifier
.vecsib
)
7603 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7604 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7606 i
.sib
.base
= i
.base_reg
->reg_num
;
7607 /* x86-64 ignores REX prefix bit here to avoid decoder
7609 if (!(i
.base_reg
->reg_flags
& RegRex
)
7610 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7611 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7613 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7615 fake_zero_displacement
= 1;
7616 i
.types
[op
].bitfield
.disp8
= 1;
7618 i
.sib
.scale
= i
.log2_scale_factor
;
7619 if (i
.index_reg
== 0)
7621 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7622 /* <disp>(%esp) becomes two byte modrm with no index
7623 register. We've already stored the code for esp
7624 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7625 Any base register besides %esp will not use the
7626 extra modrm byte. */
7627 i
.sib
.index
= NO_INDEX_REGISTER
;
7629 else if (!i
.tm
.opcode_modifier
.vecsib
)
7631 if (i
.index_reg
->reg_num
== RegIZ
)
7632 i
.sib
.index
= NO_INDEX_REGISTER
;
7634 i
.sib
.index
= i
.index_reg
->reg_num
;
7635 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7636 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7641 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7642 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7646 if (!fake_zero_displacement
7650 fake_zero_displacement
= 1;
7651 if (i
.disp_encoding
== disp_encoding_8bit
)
7652 i
.types
[op
].bitfield
.disp8
= 1;
7654 i
.types
[op
].bitfield
.disp32
= 1;
7656 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7660 if (fake_zero_displacement
)
7662 /* Fakes a zero displacement assuming that i.types[op]
7663 holds the correct displacement size. */
7666 gas_assert (i
.op
[op
].disps
== 0);
7667 exp
= &disp_expressions
[i
.disp_operands
++];
7668 i
.op
[op
].disps
= exp
;
7669 exp
->X_op
= O_constant
;
7670 exp
->X_add_number
= 0;
7671 exp
->X_add_symbol
= (symbolS
*) 0;
7672 exp
->X_op_symbol
= (symbolS
*) 0;
7680 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7682 if (operand_type_check (i
.types
[0], imm
))
7683 i
.vex
.register_specifier
= NULL
;
7686 /* VEX.vvvv encodes one of the sources when the first
7687 operand is not an immediate. */
7688 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7689 i
.vex
.register_specifier
= i
.op
[0].regs
;
7691 i
.vex
.register_specifier
= i
.op
[1].regs
;
7694 /* Destination is a XMM register encoded in the ModRM.reg
7696 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7697 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7700 /* ModRM.rm and VEX.B encodes the other source. */
7701 if (!i
.mem_operands
)
7705 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7706 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7708 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7710 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7714 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7716 i
.vex
.register_specifier
= i
.op
[2].regs
;
7717 if (!i
.mem_operands
)
7720 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7721 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7725 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7726 (if any) based on i.tm.extension_opcode. Again, we must be
7727 careful to make sure that segment/control/debug/test/MMX
7728 registers are coded into the i.rm.reg field. */
7729 else if (i
.reg_operands
)
7732 unsigned int vex_reg
= ~0;
7734 for (op
= 0; op
< i
.operands
; op
++)
7736 if (i
.types
[op
].bitfield
.class == Reg
7737 || i
.types
[op
].bitfield
.class == RegBND
7738 || i
.types
[op
].bitfield
.class == RegMask
7739 || i
.types
[op
].bitfield
.class == SReg
7740 || i
.types
[op
].bitfield
.class == RegCR
7741 || i
.types
[op
].bitfield
.class == RegDR
7742 || i
.types
[op
].bitfield
.class == RegTR
)
7744 if (i
.types
[op
].bitfield
.class == RegSIMD
)
7746 if (i
.types
[op
].bitfield
.zmmword
)
7747 i
.has_regzmm
= TRUE
;
7748 else if (i
.types
[op
].bitfield
.ymmword
)
7749 i
.has_regymm
= TRUE
;
7751 i
.has_regxmm
= TRUE
;
7754 if (i
.types
[op
].bitfield
.class == RegMMX
)
7756 i
.has_regmmx
= TRUE
;
7763 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7765 /* For instructions with VexNDS, the register-only
7766 source operand is encoded in VEX prefix. */
7767 gas_assert (mem
!= (unsigned int) ~0);
7772 gas_assert (op
< i
.operands
);
7776 /* Check register-only source operand when two source
7777 operands are swapped. */
7778 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7779 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7783 gas_assert (mem
== (vex_reg
+ 1)
7784 && op
< i
.operands
);
7789 gas_assert (vex_reg
< i
.operands
);
7793 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7795 /* For instructions with VexNDD, the register destination
7796 is encoded in VEX prefix. */
7797 if (i
.mem_operands
== 0)
7799 /* There is no memory operand. */
7800 gas_assert ((op
+ 2) == i
.operands
);
7805 /* There are only 2 non-immediate operands. */
7806 gas_assert (op
< i
.imm_operands
+ 2
7807 && i
.operands
== i
.imm_operands
+ 2);
7808 vex_reg
= i
.imm_operands
+ 1;
7812 gas_assert (op
< i
.operands
);
7814 if (vex_reg
!= (unsigned int) ~0)
7816 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7818 if ((type
->bitfield
.class != Reg
7819 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7820 && type
->bitfield
.class != RegSIMD
7821 && !operand_type_equal (type
, ®mask
))
7824 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7827 /* Don't set OP operand twice. */
7830 /* If there is an extension opcode to put here, the
7831 register number must be put into the regmem field. */
7832 if (i
.tm
.extension_opcode
!= None
)
7834 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7835 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7837 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7842 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7843 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7845 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7850 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7851 must set it to 3 to indicate this is a register operand
7852 in the regmem field. */
7853 if (!i
.mem_operands
)
7857 /* Fill in i.rm.reg field with extension opcode (if any). */
7858 if (i
.tm
.extension_opcode
!= None
)
7859 i
.rm
.reg
= i
.tm
.extension_opcode
;
7865 flip_code16 (unsigned int code16
)
7867 gas_assert (i
.tm
.operands
== 1);
7869 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
7870 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
7871 || i
.tm
.operand_types
[0].bitfield
.disp32s
7872 : i
.tm
.operand_types
[0].bitfield
.disp16
)
7877 output_branch (void)
7883 relax_substateT subtype
;
7887 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7888 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7891 if (i
.prefix
[DATA_PREFIX
] != 0)
7895 code16
^= flip_code16(code16
);
7897 /* Pentium4 branch hints. */
7898 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7899 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7904 if (i
.prefix
[REX_PREFIX
] != 0)
7910 /* BND prefixed jump. */
7911 if (i
.prefix
[BND_PREFIX
] != 0)
7917 if (i
.prefixes
!= 0)
7918 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
7920 /* It's always a symbol; End frag & setup for relax.
7921 Make sure there is enough room in this frag for the largest
7922 instruction we may generate in md_convert_frag. This is 2
7923 bytes for the opcode and room for the prefix and largest
7925 frag_grow (prefix
+ 2 + 4);
7926 /* Prefix and 1 opcode byte go in fr_fix. */
7927 p
= frag_more (prefix
+ 1);
7928 if (i
.prefix
[DATA_PREFIX
] != 0)
7929 *p
++ = DATA_PREFIX_OPCODE
;
7930 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7931 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7932 *p
++ = i
.prefix
[SEG_PREFIX
];
7933 if (i
.prefix
[BND_PREFIX
] != 0)
7934 *p
++ = BND_PREFIX_OPCODE
;
7935 if (i
.prefix
[REX_PREFIX
] != 0)
7936 *p
++ = i
.prefix
[REX_PREFIX
];
7937 *p
= i
.tm
.base_opcode
;
7939 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7940 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7941 else if (cpu_arch_flags
.bitfield
.cpui386
)
7942 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7944 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7947 sym
= i
.op
[0].disps
->X_add_symbol
;
7948 off
= i
.op
[0].disps
->X_add_number
;
7950 if (i
.op
[0].disps
->X_op
!= O_constant
7951 && i
.op
[0].disps
->X_op
!= O_symbol
)
7953 /* Handle complex expressions. */
7954 sym
= make_expr_symbol (i
.op
[0].disps
);
7958 /* 1 possible extra opcode + 4 byte displacement go in var part.
7959 Pass reloc in fr_var. */
7960 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7963 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7964 /* Return TRUE iff PLT32 relocation should be used for branching to
7968 need_plt32_p (symbolS
*s
)
7970 /* PLT32 relocation is ELF only. */
7975 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
7976 krtld support it. */
7980 /* Since there is no need to prepare for PLT branch on x86-64, we
7981 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7982 be used as a marker for 32-bit PC-relative branches. */
7986 /* Weak or undefined symbol need PLT32 relocation. */
7987 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7990 /* Non-global symbol doesn't need PLT32 relocation. */
7991 if (! S_IS_EXTERNAL (s
))
7994 /* Other global symbols need PLT32 relocation. NB: Symbol with
7995 non-default visibilities are treated as normal global symbol
7996 so that PLT32 relocation can be used as a marker for 32-bit
7997 PC-relative branches. It is useful for linker relaxation. */
8008 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8010 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8012 /* This is a loop or jecxz type instruction. */
8014 if (i
.prefix
[ADDR_PREFIX
] != 0)
8016 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
8019 /* Pentium4 branch hints. */
8020 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8021 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8023 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
8032 if (flag_code
== CODE_16BIT
)
8035 if (i
.prefix
[DATA_PREFIX
] != 0)
8037 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
8039 code16
^= flip_code16(code16
);
8047 /* BND prefixed jump. */
8048 if (i
.prefix
[BND_PREFIX
] != 0)
8050 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
8054 if (i
.prefix
[REX_PREFIX
] != 0)
8056 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
8060 if (i
.prefixes
!= 0)
8061 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8063 p
= frag_more (i
.tm
.opcode_length
+ size
);
8064 switch (i
.tm
.opcode_length
)
8067 *p
++ = i
.tm
.base_opcode
>> 8;
8070 *p
++ = i
.tm
.base_opcode
;
8076 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8078 && jump_reloc
== NO_RELOC
8079 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8080 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8083 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8085 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8086 i
.op
[0].disps
, 1, jump_reloc
);
8088 /* All jumps handled here are signed, but don't use a signed limit
8089 check for 32 and 16 bit jumps as we want to allow wrap around at
8090 4G and 64k respectively. */
8092 fixP
->fx_signed
= 1;
8096 output_interseg_jump (void)
8104 if (flag_code
== CODE_16BIT
)
8108 if (i
.prefix
[DATA_PREFIX
] != 0)
8115 gas_assert (!i
.prefix
[REX_PREFIX
]);
8121 if (i
.prefixes
!= 0)
8122 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8124 /* 1 opcode; 2 segment; offset */
8125 p
= frag_more (prefix
+ 1 + 2 + size
);
8127 if (i
.prefix
[DATA_PREFIX
] != 0)
8128 *p
++ = DATA_PREFIX_OPCODE
;
8130 if (i
.prefix
[REX_PREFIX
] != 0)
8131 *p
++ = i
.prefix
[REX_PREFIX
];
8133 *p
++ = i
.tm
.base_opcode
;
8134 if (i
.op
[1].imms
->X_op
== O_constant
)
8136 offsetT n
= i
.op
[1].imms
->X_add_number
;
8139 && !fits_in_unsigned_word (n
)
8140 && !fits_in_signed_word (n
))
8142 as_bad (_("16-bit jump out of range"));
8145 md_number_to_chars (p
, n
, size
);
8148 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8149 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8150 if (i
.op
[0].imms
->X_op
!= O_constant
)
8151 as_bad (_("can't handle non absolute segment in `%s'"),
8153 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8156 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8161 asection
*seg
= now_seg
;
8162 subsegT subseg
= now_subseg
;
8164 unsigned int alignment
, align_size_1
;
8165 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8166 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8167 unsigned int padding
;
8169 if (!IS_ELF
|| !x86_used_note
)
8172 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8174 /* The .note.gnu.property section layout:
8176 Field Length Contents
8179 n_descsz 4 The note descriptor size
8180 n_type 4 NT_GNU_PROPERTY_TYPE_0
8182 n_desc n_descsz The program property array
8186 /* Create the .note.gnu.property section. */
8187 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8188 bfd_set_section_flags (sec
,
8195 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8206 bfd_set_section_alignment (sec
, alignment
);
8207 elf_section_type (sec
) = SHT_NOTE
;
8209 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8211 isa_1_descsz_raw
= 4 + 4 + 4;
8212 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8213 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8215 feature_2_descsz_raw
= isa_1_descsz
;
8216 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8218 feature_2_descsz_raw
+= 4 + 4 + 4;
8219 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8220 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8223 descsz
= feature_2_descsz
;
8224 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8225 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8227 /* Write n_namsz. */
8228 md_number_to_chars (p
, (valueT
) 4, 4);
8230 /* Write n_descsz. */
8231 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8234 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8237 memcpy (p
+ 4 * 3, "GNU", 4);
8239 /* Write 4-byte type. */
8240 md_number_to_chars (p
+ 4 * 4,
8241 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8243 /* Write 4-byte data size. */
8244 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8246 /* Write 4-byte data. */
8247 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8249 /* Zero out paddings. */
8250 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8252 memset (p
+ 4 * 7, 0, padding
);
8254 /* Write 4-byte type. */
8255 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8256 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8258 /* Write 4-byte data size. */
8259 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8261 /* Write 4-byte data. */
8262 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8263 (valueT
) x86_feature_2_used
, 4);
8265 /* Zero out paddings. */
8266 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8268 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8270 /* We probably can't restore the current segment, for there likely
8273 subseg_set (seg
, subseg
);
8278 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8279 const char *frag_now_ptr
)
8281 unsigned int len
= 0;
8283 if (start_frag
!= frag_now
)
8285 const fragS
*fr
= start_frag
;
8290 } while (fr
&& fr
!= frag_now
);
8293 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8296 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8297 be macro-fused with conditional jumps. */
8300 maybe_fused_with_jcc_p (void)
8302 /* No RIP address. */
8303 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8306 /* No VEX/EVEX encoding. */
8307 if (is_any_vex_encoding (&i
.tm
))
8310 /* and, add, sub with destination register. */
8311 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8312 || i
.tm
.base_opcode
<= 5
8313 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8314 || ((i
.tm
.base_opcode
| 3) == 0x83
8315 && ((i
.tm
.extension_opcode
| 1) == 0x5
8316 || i
.tm
.extension_opcode
== 0x0)))
8317 return (i
.types
[1].bitfield
.class == Reg
8318 || i
.types
[1].bitfield
.instance
== Accum
);
8320 /* test, cmp with any register. */
8321 if ((i
.tm
.base_opcode
| 1) == 0x85
8322 || (i
.tm
.base_opcode
| 1) == 0xa9
8323 || ((i
.tm
.base_opcode
| 1) == 0xf7
8324 && i
.tm
.extension_opcode
== 0)
8325 || (i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8326 || ((i
.tm
.base_opcode
| 3) == 0x83
8327 && (i
.tm
.extension_opcode
== 0x7)))
8328 return (i
.types
[0].bitfield
.class == Reg
8329 || i
.types
[0].bitfield
.instance
== Accum
8330 || i
.types
[1].bitfield
.class == Reg
8331 || i
.types
[1].bitfield
.instance
== Accum
);
8333 /* inc, dec with any register. */
8334 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8335 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8336 || ((i
.tm
.base_opcode
| 1) == 0xff
8337 && i
.tm
.extension_opcode
<= 0x1))
8338 return (i
.types
[0].bitfield
.class == Reg
8339 || i
.types
[0].bitfield
.instance
== Accum
);
8344 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
8347 add_fused_jcc_padding_frag_p (void)
8349 /* NB: Don't work with COND_JUMP86 without i386. */
8350 if (!align_branch_power
8351 || now_seg
== absolute_section
8352 || !cpu_arch_flags
.bitfield
.cpui386
8353 || !(align_branch
& align_branch_fused_bit
))
8356 if (maybe_fused_with_jcc_p ())
8358 if (last_insn
.kind
== last_insn_other
8359 || last_insn
.seg
!= now_seg
)
8362 as_warn_where (last_insn
.file
, last_insn
.line
,
8363 _("`%s` skips -malign-branch-boundary on `%s`"),
8364 last_insn
.name
, i
.tm
.name
);
8370 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
8373 add_branch_prefix_frag_p (void)
8375 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
8376 to PadLock instructions since they include prefixes in opcode. */
8377 if (!align_branch_power
8378 || !align_branch_prefix_size
8379 || now_seg
== absolute_section
8380 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
8381 || !cpu_arch_flags
.bitfield
.cpui386
)
8384 /* Don't add prefix if it is a prefix or there is no operand in case
8385 that segment prefix is special. */
8386 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
8389 if (last_insn
.kind
== last_insn_other
8390 || last_insn
.seg
!= now_seg
)
8394 as_warn_where (last_insn
.file
, last_insn
.line
,
8395 _("`%s` skips -malign-branch-boundary on `%s`"),
8396 last_insn
.name
, i
.tm
.name
);
8401 /* Return 1 if a BRANCH_PADDING frag should be generated. */
8404 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
)
8408 /* NB: Don't work with COND_JUMP86 without i386. */
8409 if (!align_branch_power
8410 || now_seg
== absolute_section
8411 || !cpu_arch_flags
.bitfield
.cpui386
)
8416 /* Check for jcc and direct jmp. */
8417 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8419 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
8421 *branch_p
= align_branch_jmp
;
8422 add_padding
= align_branch
& align_branch_jmp_bit
;
8426 *branch_p
= align_branch_jcc
;
8427 if ((align_branch
& align_branch_jcc_bit
))
8431 else if (is_any_vex_encoding (&i
.tm
))
8433 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
8436 *branch_p
= align_branch_ret
;
8437 if ((align_branch
& align_branch_ret_bit
))
8442 /* Check for indirect jmp, direct and indirect calls. */
8443 if (i
.tm
.base_opcode
== 0xe8)
8446 *branch_p
= align_branch_call
;
8447 if ((align_branch
& align_branch_call_bit
))
8450 else if (i
.tm
.base_opcode
== 0xff
8451 && (i
.tm
.extension_opcode
== 2
8452 || i
.tm
.extension_opcode
== 4))
8454 /* Indirect call and jmp. */
8455 *branch_p
= align_branch_indirect
;
8456 if ((align_branch
& align_branch_indirect_bit
))
8463 && (i
.op
[0].disps
->X_op
== O_symbol
8464 || (i
.op
[0].disps
->X_op
== O_subtract
8465 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
8467 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
8468 /* No padding to call to global or undefined tls_get_addr. */
8469 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
8470 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
8476 && last_insn
.kind
!= last_insn_other
8477 && last_insn
.seg
== now_seg
)
8480 as_warn_where (last_insn
.file
, last_insn
.line
,
8481 _("`%s` skips -malign-branch-boundary on `%s`"),
8482 last_insn
.name
, i
.tm
.name
);
8492 fragS
*insn_start_frag
;
8493 offsetT insn_start_off
;
8494 fragS
*fragP
= NULL
;
8495 enum align_branch_kind branch
= align_branch_none
;
8497 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8498 if (IS_ELF
&& x86_used_note
)
8500 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8501 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8502 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8503 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8504 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8505 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8506 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8507 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8508 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8509 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8510 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8511 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8512 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8513 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8514 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8515 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8516 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8517 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8518 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8519 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8520 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8521 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8522 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8523 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8524 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8525 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8526 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8527 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8528 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8529 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8530 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8531 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8532 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8533 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8534 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8535 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8536 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8537 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8538 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8539 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8540 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8541 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8542 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8543 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8544 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8545 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8546 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8547 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8548 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8549 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8551 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8552 || i
.tm
.cpu_flags
.bitfield
.cpu287
8553 || i
.tm
.cpu_flags
.bitfield
.cpu387
8554 || i
.tm
.cpu_flags
.bitfield
.cpu687
8555 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8556 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8558 || i
.tm
.base_opcode
== 0xf77 /* emms */
8559 || i
.tm
.base_opcode
== 0xf0e /* femms */)
8560 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8562 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8564 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8566 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8567 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8568 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8569 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8570 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8571 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8572 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8573 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8574 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8578 /* Tie dwarf2 debug info to the address at the start of the insn.
8579 We can't do this after the insn has been output as the current
8580 frag may have been closed off. eg. by frag_var. */
8581 dwarf2_emit_insn (0);
8583 insn_start_frag
= frag_now
;
8584 insn_start_off
= frag_now_fix ();
8586 if (add_branch_padding_frag_p (&branch
))
8589 /* Branch can be 8 bytes. Leave some room for prefixes. */
8590 unsigned int max_branch_padding_size
= 14;
8592 /* Align section to boundary. */
8593 record_alignment (now_seg
, align_branch_power
);
8595 /* Make room for padding. */
8596 frag_grow (max_branch_padding_size
);
8598 /* Start of the padding. */
8603 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
8604 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
8607 fragP
->tc_frag_data
.branch_type
= branch
;
8608 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
8612 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8614 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
8615 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
8617 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
8618 output_interseg_jump ();
8621 /* Output normal instructions here. */
8625 unsigned int prefix
;
8628 && (i
.tm
.base_opcode
== 0xfaee8
8629 || i
.tm
.base_opcode
== 0xfaef0
8630 || i
.tm
.base_opcode
== 0xfaef8))
8632 /* Encode lfence, mfence, and sfence as
8633 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8634 offsetT val
= 0x240483f0ULL
;
8636 md_number_to_chars (p
, val
, 5);
8640 /* Some processors fail on LOCK prefix. This options makes
8641 assembler ignore LOCK prefix and serves as a workaround. */
8642 if (omit_lock_prefix
)
8644 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8646 i
.prefix
[LOCK_PREFIX
] = 0;
8650 /* Skip if this is a branch. */
8652 else if (add_fused_jcc_padding_frag_p ())
8654 /* Make room for padding. */
8655 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
8660 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
8661 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
8664 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
8665 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
8667 else if (add_branch_prefix_frag_p ())
8669 unsigned int max_prefix_size
= align_branch_prefix_size
;
8671 /* Make room for padding. */
8672 frag_grow (max_prefix_size
);
8677 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
8678 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
8681 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
8684 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8685 don't need the explicit prefix. */
8686 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8688 switch (i
.tm
.opcode_length
)
8691 if (i
.tm
.base_opcode
& 0xff000000)
8693 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8694 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8695 || prefix
!= REPE_PREFIX_OPCODE
8696 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8697 add_prefix (prefix
);
8701 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8703 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8704 add_prefix (prefix
);
8710 /* Check for pseudo prefixes. */
8711 as_bad_where (insn_start_frag
->fr_file
,
8712 insn_start_frag
->fr_line
,
8713 _("pseudo prefix without instruction"));
8719 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8720 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8721 R_X86_64_GOTTPOFF relocation so that linker can safely
8722 perform IE->LE optimization. */
8723 if (x86_elf_abi
== X86_64_X32_ABI
8725 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8726 && i
.prefix
[REX_PREFIX
] == 0)
8727 add_prefix (REX_OPCODE
);
8730 /* The prefix bytes. */
8731 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8733 FRAG_APPEND_1_CHAR (*q
);
8737 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8742 /* REX byte is encoded in VEX prefix. */
8746 FRAG_APPEND_1_CHAR (*q
);
8749 /* There should be no other prefixes for instructions
8754 /* For EVEX instructions i.vrex should become 0 after
8755 build_evex_prefix. For VEX instructions upper 16 registers
8756 aren't available, so VREX should be 0. */
8759 /* Now the VEX prefix. */
8760 p
= frag_more (i
.vex
.length
);
8761 for (j
= 0; j
< i
.vex
.length
; j
++)
8762 p
[j
] = i
.vex
.bytes
[j
];
8765 /* Now the opcode; be careful about word order here! */
8766 if (i
.tm
.opcode_length
== 1)
8768 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8772 switch (i
.tm
.opcode_length
)
8776 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8777 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8781 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8791 /* Put out high byte first: can't use md_number_to_chars! */
8792 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8793 *p
= i
.tm
.base_opcode
& 0xff;
8796 /* Now the modrm byte and sib byte (if present). */
8797 if (i
.tm
.opcode_modifier
.modrm
)
8799 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8802 /* If i.rm.regmem == ESP (4)
8803 && i.rm.mode != (Register mode)
8805 ==> need second modrm byte. */
8806 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8808 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8809 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8811 | i
.sib
.scale
<< 6));
8814 if (i
.disp_operands
)
8815 output_disp (insn_start_frag
, insn_start_off
);
8818 output_imm (insn_start_frag
, insn_start_off
);
8821 * frag_now_fix () returning plain abs_section_offset when we're in the
8822 * absolute section, and abs_section_offset not getting updated as data
8823 * gets added to the frag breaks the logic below.
8825 if (now_seg
!= absolute_section
)
8827 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
8829 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
8833 /* NB: Don't add prefix with GOTPC relocation since
8834 output_disp() above depends on the fixed encoding
8835 length. Can't add prefix with TLS relocation since
8836 it breaks TLS linker optimization. */
8837 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
8838 /* Prefix count on the current instruction. */
8839 unsigned int count
= i
.vex
.length
;
8841 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
8842 /* REX byte is encoded in VEX/EVEX prefix. */
8843 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
8846 /* Count prefixes for extended opcode maps. */
8848 switch (i
.tm
.opcode_length
)
8851 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
8854 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
8866 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
8875 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
8878 /* Set the maximum prefix size in BRANCH_PREFIX
8880 if (fragP
->tc_frag_data
.max_bytes
> max
)
8881 fragP
->tc_frag_data
.max_bytes
= max
;
8882 if (fragP
->tc_frag_data
.max_bytes
> count
)
8883 fragP
->tc_frag_data
.max_bytes
-= count
;
8885 fragP
->tc_frag_data
.max_bytes
= 0;
8889 /* Remember the maximum prefix size in FUSED_JCC_PADDING
8891 unsigned int max_prefix_size
;
8892 if (align_branch_prefix_size
> max
)
8893 max_prefix_size
= max
;
8895 max_prefix_size
= align_branch_prefix_size
;
8896 if (max_prefix_size
> count
)
8897 fragP
->tc_frag_data
.max_prefix_length
8898 = max_prefix_size
- count
;
8901 /* Use existing segment prefix if possible. Use CS
8902 segment prefix in 64-bit mode. In 32-bit mode, use SS
8903 segment prefix with ESP/EBP base register and use DS
8904 segment prefix without ESP/EBP base register. */
8905 if (i
.prefix
[SEG_PREFIX
])
8906 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
8907 else if (flag_code
== CODE_64BIT
)
8908 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
8910 && (i
.base_reg
->reg_num
== 4
8911 || i
.base_reg
->reg_num
== 5))
8912 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
8914 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
8919 /* NB: Don't work with COND_JUMP86 without i386. */
8920 if (align_branch_power
8921 && now_seg
!= absolute_section
8922 && cpu_arch_flags
.bitfield
.cpui386
)
8924 /* Terminate each frag so that we can add prefix and check for
8926 frag_wane (frag_now
);
8933 pi ("" /*line*/, &i
);
8935 #endif /* DEBUG386 */
8938 /* Return the size of the displacement operand N. */
8941 disp_size (unsigned int n
)
8945 if (i
.types
[n
].bitfield
.disp64
)
8947 else if (i
.types
[n
].bitfield
.disp8
)
8949 else if (i
.types
[n
].bitfield
.disp16
)
8954 /* Return the size of the immediate operand N. */
8957 imm_size (unsigned int n
)
8960 if (i
.types
[n
].bitfield
.imm64
)
8962 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8964 else if (i
.types
[n
].bitfield
.imm16
)
8970 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8975 for (n
= 0; n
< i
.operands
; n
++)
8977 if (operand_type_check (i
.types
[n
], disp
))
8979 if (i
.op
[n
].disps
->X_op
== O_constant
)
8981 int size
= disp_size (n
);
8982 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8984 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8986 p
= frag_more (size
);
8987 md_number_to_chars (p
, val
, size
);
8991 enum bfd_reloc_code_real reloc_type
;
8992 int size
= disp_size (n
);
8993 int sign
= i
.types
[n
].bitfield
.disp32s
;
8994 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8997 /* We can't have 8 bit displacement here. */
8998 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9000 /* The PC relative address is computed relative
9001 to the instruction boundary, so in case immediate
9002 fields follows, we need to adjust the value. */
9003 if (pcrel
&& i
.imm_operands
)
9008 for (n1
= 0; n1
< i
.operands
; n1
++)
9009 if (operand_type_check (i
.types
[n1
], imm
))
9011 /* Only one immediate is allowed for PC
9012 relative address. */
9013 gas_assert (sz
== 0);
9015 i
.op
[n
].disps
->X_add_number
-= sz
;
9017 /* We should find the immediate. */
9018 gas_assert (sz
!= 0);
9021 p
= frag_more (size
);
9022 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9024 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9025 && (((reloc_type
== BFD_RELOC_32
9026 || reloc_type
== BFD_RELOC_X86_64_32S
9027 || (reloc_type
== BFD_RELOC_64
9029 && (i
.op
[n
].disps
->X_op
== O_symbol
9030 || (i
.op
[n
].disps
->X_op
== O_add
9031 && ((symbol_get_value_expression
9032 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9034 || reloc_type
== BFD_RELOC_32_PCREL
))
9038 reloc_type
= BFD_RELOC_386_GOTPC
;
9039 i
.has_gotpc_tls_reloc
= TRUE
;
9040 i
.op
[n
].imms
->X_add_number
+=
9041 encoding_length (insn_start_frag
, insn_start_off
, p
);
9043 else if (reloc_type
== BFD_RELOC_64
)
9044 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9046 /* Don't do the adjustment for x86-64, as there
9047 the pcrel addressing is relative to the _next_
9048 insn, and that is taken care of in other code. */
9049 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9051 else if (align_branch_power
)
9055 case BFD_RELOC_386_TLS_GD
:
9056 case BFD_RELOC_386_TLS_LDM
:
9057 case BFD_RELOC_386_TLS_IE
:
9058 case BFD_RELOC_386_TLS_IE_32
:
9059 case BFD_RELOC_386_TLS_GOTIE
:
9060 case BFD_RELOC_386_TLS_GOTDESC
:
9061 case BFD_RELOC_386_TLS_DESC_CALL
:
9062 case BFD_RELOC_X86_64_TLSGD
:
9063 case BFD_RELOC_X86_64_TLSLD
:
9064 case BFD_RELOC_X86_64_GOTTPOFF
:
9065 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9066 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9067 i
.has_gotpc_tls_reloc
= TRUE
;
9072 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9073 size
, i
.op
[n
].disps
, pcrel
,
9075 /* Check for "call/jmp *mem", "mov mem, %reg",
9076 "test %reg, mem" and "binop mem, %reg" where binop
9077 is one of adc, add, and, cmp, or, sbb, sub, xor
9078 instructions without data prefix. Always generate
9079 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9080 if (i
.prefix
[DATA_PREFIX
] == 0
9081 && (generate_relax_relocations
9084 && i
.rm
.regmem
== 5))
9086 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9087 && ((i
.operands
== 1
9088 && i
.tm
.base_opcode
== 0xff
9089 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9091 && (i
.tm
.base_opcode
== 0x8b
9092 || i
.tm
.base_opcode
== 0x85
9093 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
9097 fixP
->fx_tcbit
= i
.rex
!= 0;
9099 && (i
.base_reg
->reg_num
== RegIP
))
9100 fixP
->fx_tcbit2
= 1;
9103 fixP
->fx_tcbit2
= 1;
9111 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9116 for (n
= 0; n
< i
.operands
; n
++)
9118 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9119 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9122 if (operand_type_check (i
.types
[n
], imm
))
9124 if (i
.op
[n
].imms
->X_op
== O_constant
)
9126 int size
= imm_size (n
);
9129 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9131 p
= frag_more (size
);
9132 md_number_to_chars (p
, val
, size
);
9136 /* Not absolute_section.
9137 Need a 32-bit fixup (don't support 8bit
9138 non-absolute imms). Try to support other
9140 enum bfd_reloc_code_real reloc_type
;
9141 int size
= imm_size (n
);
9144 if (i
.types
[n
].bitfield
.imm32s
9145 && (i
.suffix
== QWORD_MNEM_SUFFIX
9146 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9151 p
= frag_more (size
);
9152 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9154 /* This is tough to explain. We end up with this one if we
9155 * have operands that look like
9156 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9157 * obtain the absolute address of the GOT, and it is strongly
9158 * preferable from a performance point of view to avoid using
9159 * a runtime relocation for this. The actual sequence of
9160 * instructions often look something like:
9165 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9167 * The call and pop essentially return the absolute address
9168 * of the label .L66 and store it in %ebx. The linker itself
9169 * will ultimately change the first operand of the addl so
9170 * that %ebx points to the GOT, but to keep things simple, the
9171 * .o file must have this operand set so that it generates not
9172 * the absolute address of .L66, but the absolute address of
9173 * itself. This allows the linker itself simply treat a GOTPC
9174 * relocation as asking for a pcrel offset to the GOT to be
9175 * added in, and the addend of the relocation is stored in the
9176 * operand field for the instruction itself.
9178 * Our job here is to fix the operand so that it would add
9179 * the correct offset so that %ebx would point to itself. The
9180 * thing that is tricky is that .-.L66 will point to the
9181 * beginning of the instruction, so we need to further modify
9182 * the operand so that it will point to itself. There are
9183 * other cases where you have something like:
9185 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9187 * and here no correction would be required. Internally in
9188 * the assembler we treat operands of this form as not being
9189 * pcrel since the '.' is explicitly mentioned, and I wonder
9190 * whether it would simplify matters to do it this way. Who
9191 * knows. In earlier versions of the PIC patches, the
9192 * pcrel_adjust field was used to store the correction, but
9193 * since the expression is not pcrel, I felt it would be
9194 * confusing to do it this way. */
9196 if ((reloc_type
== BFD_RELOC_32
9197 || reloc_type
== BFD_RELOC_X86_64_32S
9198 || reloc_type
== BFD_RELOC_64
)
9200 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9201 && (i
.op
[n
].imms
->X_op
== O_symbol
9202 || (i
.op
[n
].imms
->X_op
== O_add
9203 && ((symbol_get_value_expression
9204 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9208 reloc_type
= BFD_RELOC_386_GOTPC
;
9210 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9212 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9213 i
.has_gotpc_tls_reloc
= TRUE
;
9214 i
.op
[n
].imms
->X_add_number
+=
9215 encoding_length (insn_start_frag
, insn_start_off
, p
);
9217 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9218 i
.op
[n
].imms
, 0, reloc_type
);
9224 /* x86_cons_fix_new is called via the expression parsing code when a
9225 reloc is needed. We use this hook to get the correct .got reloc. */
9226 static int cons_sign
= -1;
9229 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9230 expressionS
*exp
, bfd_reloc_code_real_type r
)
9232 r
= reloc (len
, 0, cons_sign
, r
);
9235 if (exp
->X_op
== O_secrel
)
9237 exp
->X_op
= O_symbol
;
9238 r
= BFD_RELOC_32_SECREL
;
9242 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9245 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9246 purpose of the `.dc.a' internal pseudo-op. */
9249 x86_address_bytes (void)
9251 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9253 return stdoutput
->arch_info
->bits_per_address
/ 8;
9256 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9258 # define lex_got(reloc, adjust, types) NULL
9260 /* Parse operands of the form
9261 <symbol>@GOTOFF+<nnn>
9262 and similar .plt or .got references.
9264 If we find one, set up the correct relocation in RELOC and copy the
9265 input string, minus the `@GOTOFF' into a malloc'd buffer for
9266 parsing by the calling routine. Return this buffer, and if ADJUST
9267 is non-null set it to the length of the string we removed from the
9268 input line. Otherwise return NULL. */
9270 lex_got (enum bfd_reloc_code_real
*rel
,
9272 i386_operand_type
*types
)
9274 /* Some of the relocations depend on the size of what field is to
9275 be relocated. But in our callers i386_immediate and i386_displacement
9276 we don't yet know the operand size (this will be set by insn
9277 matching). Hence we record the word32 relocation here,
9278 and adjust the reloc according to the real size in reloc(). */
9279 static const struct {
9282 const enum bfd_reloc_code_real rel
[2];
9283 const i386_operand_type types64
;
9285 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9286 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
9288 OPERAND_TYPE_IMM32_64
},
9290 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
9291 BFD_RELOC_X86_64_PLTOFF64
},
9292 OPERAND_TYPE_IMM64
},
9293 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
9294 BFD_RELOC_X86_64_PLT32
},
9295 OPERAND_TYPE_IMM32_32S_DISP32
},
9296 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
9297 BFD_RELOC_X86_64_GOTPLT64
},
9298 OPERAND_TYPE_IMM64_DISP64
},
9299 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
9300 BFD_RELOC_X86_64_GOTOFF64
},
9301 OPERAND_TYPE_IMM64_DISP64
},
9302 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
9303 BFD_RELOC_X86_64_GOTPCREL
},
9304 OPERAND_TYPE_IMM32_32S_DISP32
},
9305 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
9306 BFD_RELOC_X86_64_TLSGD
},
9307 OPERAND_TYPE_IMM32_32S_DISP32
},
9308 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
9309 _dummy_first_bfd_reloc_code_real
},
9310 OPERAND_TYPE_NONE
},
9311 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
9312 BFD_RELOC_X86_64_TLSLD
},
9313 OPERAND_TYPE_IMM32_32S_DISP32
},
9314 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
9315 BFD_RELOC_X86_64_GOTTPOFF
},
9316 OPERAND_TYPE_IMM32_32S_DISP32
},
9317 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
9318 BFD_RELOC_X86_64_TPOFF32
},
9319 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9320 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
9321 _dummy_first_bfd_reloc_code_real
},
9322 OPERAND_TYPE_NONE
},
9323 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
9324 BFD_RELOC_X86_64_DTPOFF32
},
9325 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9326 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
9327 _dummy_first_bfd_reloc_code_real
},
9328 OPERAND_TYPE_NONE
},
9329 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
9330 _dummy_first_bfd_reloc_code_real
},
9331 OPERAND_TYPE_NONE
},
9332 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
9333 BFD_RELOC_X86_64_GOT32
},
9334 OPERAND_TYPE_IMM32_32S_64_DISP32
},
9335 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
9336 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
9337 OPERAND_TYPE_IMM32_32S_DISP32
},
9338 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
9339 BFD_RELOC_X86_64_TLSDESC_CALL
},
9340 OPERAND_TYPE_IMM32_32S_DISP32
},
9345 #if defined (OBJ_MAYBE_ELF)
9350 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9351 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9354 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9356 int len
= gotrel
[j
].len
;
9357 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9359 if (gotrel
[j
].rel
[object_64bit
] != 0)
9362 char *tmpbuf
, *past_reloc
;
9364 *rel
= gotrel
[j
].rel
[object_64bit
];
9368 if (flag_code
!= CODE_64BIT
)
9370 types
->bitfield
.imm32
= 1;
9371 types
->bitfield
.disp32
= 1;
9374 *types
= gotrel
[j
].types64
;
9377 if (j
!= 0 && GOT_symbol
== NULL
)
9378 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
9380 /* The length of the first part of our input line. */
9381 first
= cp
- input_line_pointer
;
9383 /* The second part goes from after the reloc token until
9384 (and including) an end_of_line char or comma. */
9385 past_reloc
= cp
+ 1 + len
;
9387 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9389 second
= cp
+ 1 - past_reloc
;
9391 /* Allocate and copy string. The trailing NUL shouldn't
9392 be necessary, but be safe. */
9393 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9394 memcpy (tmpbuf
, input_line_pointer
, first
);
9395 if (second
!= 0 && *past_reloc
!= ' ')
9396 /* Replace the relocation token with ' ', so that
9397 errors like foo@GOTOFF1 will be detected. */
9398 tmpbuf
[first
++] = ' ';
9400 /* Increment length by 1 if the relocation token is
9405 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9406 tmpbuf
[first
+ second
] = '\0';
9410 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9411 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9416 /* Might be a symbol version string. Don't as_bad here. */
9425 /* Parse operands of the form
9426 <symbol>@SECREL32+<nnn>
9428 If we find one, set up the correct relocation in RELOC and copy the
9429 input string, minus the `@SECREL32' into a malloc'd buffer for
9430 parsing by the calling routine. Return this buffer, and if ADJUST
9431 is non-null set it to the length of the string we removed from the
9432 input line. Otherwise return NULL.
9434 This function is copied from the ELF version above adjusted for PE targets. */
9437 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
9438 int *adjust ATTRIBUTE_UNUSED
,
9439 i386_operand_type
*types
)
9445 const enum bfd_reloc_code_real rel
[2];
9446 const i386_operand_type types64
;
9450 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
9451 BFD_RELOC_32_SECREL
},
9452 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9458 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9459 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9462 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9464 int len
= gotrel
[j
].len
;
9466 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9468 if (gotrel
[j
].rel
[object_64bit
] != 0)
9471 char *tmpbuf
, *past_reloc
;
9473 *rel
= gotrel
[j
].rel
[object_64bit
];
9479 if (flag_code
!= CODE_64BIT
)
9481 types
->bitfield
.imm32
= 1;
9482 types
->bitfield
.disp32
= 1;
9485 *types
= gotrel
[j
].types64
;
9488 /* The length of the first part of our input line. */
9489 first
= cp
- input_line_pointer
;
9491 /* The second part goes from after the reloc token until
9492 (and including) an end_of_line char or comma. */
9493 past_reloc
= cp
+ 1 + len
;
9495 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9497 second
= cp
+ 1 - past_reloc
;
9499 /* Allocate and copy string. The trailing NUL shouldn't
9500 be necessary, but be safe. */
9501 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9502 memcpy (tmpbuf
, input_line_pointer
, first
);
9503 if (second
!= 0 && *past_reloc
!= ' ')
9504 /* Replace the relocation token with ' ', so that
9505 errors like foo@SECLREL321 will be detected. */
9506 tmpbuf
[first
++] = ' ';
9507 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9508 tmpbuf
[first
+ second
] = '\0';
9512 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9513 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9518 /* Might be a symbol version string. Don't as_bad here. */
9524 bfd_reloc_code_real_type
9525 x86_cons (expressionS
*exp
, int size
)
9527 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9529 intel_syntax
= -intel_syntax
;
9532 if (size
== 4 || (object_64bit
&& size
== 8))
9534 /* Handle @GOTOFF and the like in an expression. */
9536 char *gotfree_input_line
;
9539 save
= input_line_pointer
;
9540 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
9541 if (gotfree_input_line
)
9542 input_line_pointer
= gotfree_input_line
;
9546 if (gotfree_input_line
)
9548 /* expression () has merrily parsed up to the end of line,
9549 or a comma - in the wrong buffer. Transfer how far
9550 input_line_pointer has moved to the right buffer. */
9551 input_line_pointer
= (save
9552 + (input_line_pointer
- gotfree_input_line
)
9554 free (gotfree_input_line
);
9555 if (exp
->X_op
== O_constant
9556 || exp
->X_op
== O_absent
9557 || exp
->X_op
== O_illegal
9558 || exp
->X_op
== O_register
9559 || exp
->X_op
== O_big
)
9561 char c
= *input_line_pointer
;
9562 *input_line_pointer
= 0;
9563 as_bad (_("missing or invalid expression `%s'"), save
);
9564 *input_line_pointer
= c
;
9566 else if ((got_reloc
== BFD_RELOC_386_PLT32
9567 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9568 && exp
->X_op
!= O_symbol
)
9570 char c
= *input_line_pointer
;
9571 *input_line_pointer
= 0;
9572 as_bad (_("invalid PLT expression `%s'"), save
);
9573 *input_line_pointer
= c
;
9580 intel_syntax
= -intel_syntax
;
9583 i386_intel_simplify (exp
);
9589 signed_cons (int size
)
9591 if (flag_code
== CODE_64BIT
)
9599 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9606 if (exp
.X_op
== O_symbol
)
9607 exp
.X_op
= O_secrel
;
9609 emit_expr (&exp
, 4);
9611 while (*input_line_pointer
++ == ',');
9613 input_line_pointer
--;
9614 demand_empty_rest_of_line ();
9618 /* Handle Vector operations. */
9621 check_VecOperations (char *op_string
, char *op_end
)
9623 const reg_entry
*mask
;
9628 && (op_end
== NULL
|| op_string
< op_end
))
9631 if (*op_string
== '{')
9635 /* Check broadcasts. */
9636 if (strncmp (op_string
, "1to", 3) == 0)
9641 goto duplicated_vec_op
;
9644 if (*op_string
== '8')
9646 else if (*op_string
== '4')
9648 else if (*op_string
== '2')
9650 else if (*op_string
== '1'
9651 && *(op_string
+1) == '6')
9658 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9663 broadcast_op
.type
= bcst_type
;
9664 broadcast_op
.operand
= this_operand
;
9665 broadcast_op
.bytes
= 0;
9666 i
.broadcast
= &broadcast_op
;
9668 /* Check masking operation. */
9669 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9671 /* k0 can't be used for write mask. */
9672 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
9674 as_bad (_("`%s%s' can't be used for write mask"),
9675 register_prefix
, mask
->reg_name
);
9681 mask_op
.mask
= mask
;
9682 mask_op
.zeroing
= 0;
9683 mask_op
.operand
= this_operand
;
9689 goto duplicated_vec_op
;
9691 i
.mask
->mask
= mask
;
9693 /* Only "{z}" is allowed here. No need to check
9694 zeroing mask explicitly. */
9695 if (i
.mask
->operand
!= this_operand
)
9697 as_bad (_("invalid write mask `%s'"), saved
);
9704 /* Check zeroing-flag for masking operation. */
9705 else if (*op_string
== 'z')
9709 mask_op
.mask
= NULL
;
9710 mask_op
.zeroing
= 1;
9711 mask_op
.operand
= this_operand
;
9716 if (i
.mask
->zeroing
)
9719 as_bad (_("duplicated `%s'"), saved
);
9723 i
.mask
->zeroing
= 1;
9725 /* Only "{%k}" is allowed here. No need to check mask
9726 register explicitly. */
9727 if (i
.mask
->operand
!= this_operand
)
9729 as_bad (_("invalid zeroing-masking `%s'"),
9738 goto unknown_vec_op
;
9740 if (*op_string
!= '}')
9742 as_bad (_("missing `}' in `%s'"), saved
);
9747 /* Strip whitespace since the addition of pseudo prefixes
9748 changed how the scrubber treats '{'. */
9749 if (is_space_char (*op_string
))
9755 /* We don't know this one. */
9756 as_bad (_("unknown vector operation: `%s'"), saved
);
9760 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9762 as_bad (_("zeroing-masking only allowed with write mask"));
9770 i386_immediate (char *imm_start
)
9772 char *save_input_line_pointer
;
9773 char *gotfree_input_line
;
9776 i386_operand_type types
;
9778 operand_type_set (&types
, ~0);
9780 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9782 as_bad (_("at most %d immediate operands are allowed"),
9783 MAX_IMMEDIATE_OPERANDS
);
9787 exp
= &im_expressions
[i
.imm_operands
++];
9788 i
.op
[this_operand
].imms
= exp
;
9790 if (is_space_char (*imm_start
))
9793 save_input_line_pointer
= input_line_pointer
;
9794 input_line_pointer
= imm_start
;
9796 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9797 if (gotfree_input_line
)
9798 input_line_pointer
= gotfree_input_line
;
9800 exp_seg
= expression (exp
);
9804 /* Handle vector operations. */
9805 if (*input_line_pointer
== '{')
9807 input_line_pointer
= check_VecOperations (input_line_pointer
,
9809 if (input_line_pointer
== NULL
)
9813 if (*input_line_pointer
)
9814 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9816 input_line_pointer
= save_input_line_pointer
;
9817 if (gotfree_input_line
)
9819 free (gotfree_input_line
);
9821 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9822 exp
->X_op
= O_illegal
;
9825 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9829 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9830 i386_operand_type types
, const char *imm_start
)
9832 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9835 as_bad (_("missing or invalid immediate expression `%s'"),
9839 else if (exp
->X_op
== O_constant
)
9841 /* Size it properly later. */
9842 i
.types
[this_operand
].bitfield
.imm64
= 1;
9843 /* If not 64bit, sign extend val. */
9844 if (flag_code
!= CODE_64BIT
9845 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9847 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9849 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9850 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9851 && exp_seg
!= absolute_section
9852 && exp_seg
!= text_section
9853 && exp_seg
!= data_section
9854 && exp_seg
!= bss_section
9855 && exp_seg
!= undefined_section
9856 && !bfd_is_com_section (exp_seg
))
9858 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9862 else if (!intel_syntax
&& exp_seg
== reg_section
)
9865 as_bad (_("illegal immediate register operand %s"), imm_start
);
9870 /* This is an address. The size of the address will be
9871 determined later, depending on destination register,
9872 suffix, or the default for the section. */
9873 i
.types
[this_operand
].bitfield
.imm8
= 1;
9874 i
.types
[this_operand
].bitfield
.imm16
= 1;
9875 i
.types
[this_operand
].bitfield
.imm32
= 1;
9876 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9877 i
.types
[this_operand
].bitfield
.imm64
= 1;
9878 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9886 i386_scale (char *scale
)
9889 char *save
= input_line_pointer
;
9891 input_line_pointer
= scale
;
9892 val
= get_absolute_expression ();
9897 i
.log2_scale_factor
= 0;
9900 i
.log2_scale_factor
= 1;
9903 i
.log2_scale_factor
= 2;
9906 i
.log2_scale_factor
= 3;
9910 char sep
= *input_line_pointer
;
9912 *input_line_pointer
= '\0';
9913 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9915 *input_line_pointer
= sep
;
9916 input_line_pointer
= save
;
9920 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9922 as_warn (_("scale factor of %d without an index register"),
9923 1 << i
.log2_scale_factor
);
9924 i
.log2_scale_factor
= 0;
9926 scale
= input_line_pointer
;
9927 input_line_pointer
= save
;
9932 i386_displacement (char *disp_start
, char *disp_end
)
9936 char *save_input_line_pointer
;
9937 char *gotfree_input_line
;
9939 i386_operand_type bigdisp
, types
= anydisp
;
9942 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9944 as_bad (_("at most %d displacement operands are allowed"),
9945 MAX_MEMORY_OPERANDS
);
9949 operand_type_set (&bigdisp
, 0);
9951 || i
.types
[this_operand
].bitfield
.baseindex
9952 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
9953 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
9955 i386_addressing_mode ();
9956 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9957 if (flag_code
== CODE_64BIT
)
9961 bigdisp
.bitfield
.disp32s
= 1;
9962 bigdisp
.bitfield
.disp64
= 1;
9965 bigdisp
.bitfield
.disp32
= 1;
9967 else if ((flag_code
== CODE_16BIT
) ^ override
)
9968 bigdisp
.bitfield
.disp16
= 1;
9970 bigdisp
.bitfield
.disp32
= 1;
9974 /* For PC-relative branches, the width of the displacement may be
9975 dependent upon data size, but is never dependent upon address size.
9976 Also make sure to not unintentionally match against a non-PC-relative
9978 static templates aux_templates
;
9979 const insn_template
*t
= current_templates
->start
;
9980 bfd_boolean has_intel64
= FALSE
;
9982 aux_templates
.start
= t
;
9983 while (++t
< current_templates
->end
)
9985 if (t
->opcode_modifier
.jump
9986 != current_templates
->start
->opcode_modifier
.jump
)
9988 if (t
->opcode_modifier
.intel64
)
9991 if (t
< current_templates
->end
)
9993 aux_templates
.end
= t
;
9994 current_templates
= &aux_templates
;
9997 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9998 if (flag_code
== CODE_64BIT
)
10000 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10001 && (!intel64
|| !has_intel64
))
10002 bigdisp
.bitfield
.disp16
= 1;
10004 bigdisp
.bitfield
.disp32s
= 1;
10009 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10011 : LONG_MNEM_SUFFIX
));
10012 bigdisp
.bitfield
.disp32
= 1;
10013 if ((flag_code
== CODE_16BIT
) ^ override
)
10015 bigdisp
.bitfield
.disp32
= 0;
10016 bigdisp
.bitfield
.disp16
= 1;
10020 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10023 exp
= &disp_expressions
[i
.disp_operands
];
10024 i
.op
[this_operand
].disps
= exp
;
10026 save_input_line_pointer
= input_line_pointer
;
10027 input_line_pointer
= disp_start
;
10028 END_STRING_AND_SAVE (disp_end
);
10030 #ifndef GCC_ASM_O_HACK
10031 #define GCC_ASM_O_HACK 0
10034 END_STRING_AND_SAVE (disp_end
+ 1);
10035 if (i
.types
[this_operand
].bitfield
.baseIndex
10036 && displacement_string_end
[-1] == '+')
10038 /* This hack is to avoid a warning when using the "o"
10039 constraint within gcc asm statements.
10042 #define _set_tssldt_desc(n,addr,limit,type) \
10043 __asm__ __volatile__ ( \
10044 "movw %w2,%0\n\t" \
10045 "movw %w1,2+%0\n\t" \
10046 "rorl $16,%1\n\t" \
10047 "movb %b1,4+%0\n\t" \
10048 "movb %4,5+%0\n\t" \
10049 "movb $0,6+%0\n\t" \
10050 "movb %h1,7+%0\n\t" \
10052 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10054 This works great except that the output assembler ends
10055 up looking a bit weird if it turns out that there is
10056 no offset. You end up producing code that looks like:
10069 So here we provide the missing zero. */
10071 *displacement_string_end
= '0';
10074 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10075 if (gotfree_input_line
)
10076 input_line_pointer
= gotfree_input_line
;
10078 exp_seg
= expression (exp
);
10080 SKIP_WHITESPACE ();
10081 if (*input_line_pointer
)
10082 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10084 RESTORE_END_STRING (disp_end
+ 1);
10086 input_line_pointer
= save_input_line_pointer
;
10087 if (gotfree_input_line
)
10089 free (gotfree_input_line
);
10091 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10092 exp
->X_op
= O_illegal
;
10095 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10097 RESTORE_END_STRING (disp_end
);
10103 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10104 i386_operand_type types
, const char *disp_start
)
10106 i386_operand_type bigdisp
;
10109 /* We do this to make sure that the section symbol is in
10110 the symbol table. We will ultimately change the relocation
10111 to be relative to the beginning of the section. */
10112 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10113 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10114 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10116 if (exp
->X_op
!= O_symbol
)
10119 if (S_IS_LOCAL (exp
->X_add_symbol
)
10120 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10121 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10122 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10123 exp
->X_op
= O_subtract
;
10124 exp
->X_op_symbol
= GOT_symbol
;
10125 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10126 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10127 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10128 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10130 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10133 else if (exp
->X_op
== O_absent
10134 || exp
->X_op
== O_illegal
10135 || exp
->X_op
== O_big
)
10138 as_bad (_("missing or invalid displacement expression `%s'"),
10143 else if (flag_code
== CODE_64BIT
10144 && !i
.prefix
[ADDR_PREFIX
]
10145 && exp
->X_op
== O_constant
)
10147 /* Since displacement is signed extended to 64bit, don't allow
10148 disp32 and turn off disp32s if they are out of range. */
10149 i
.types
[this_operand
].bitfield
.disp32
= 0;
10150 if (!fits_in_signed_long (exp
->X_add_number
))
10152 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10153 if (i
.types
[this_operand
].bitfield
.baseindex
)
10155 as_bad (_("0x%lx out range of signed 32bit displacement"),
10156 (long) exp
->X_add_number
);
10162 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10163 else if (exp
->X_op
!= O_constant
10164 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10165 && exp_seg
!= absolute_section
10166 && exp_seg
!= text_section
10167 && exp_seg
!= data_section
10168 && exp_seg
!= bss_section
10169 && exp_seg
!= undefined_section
10170 && !bfd_is_com_section (exp_seg
))
10172 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10177 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10178 /* Constants get taken care of by optimize_disp(). */
10179 && exp
->X_op
!= O_constant
)
10180 i
.types
[this_operand
].bitfield
.disp8
= 1;
10182 /* Check if this is a displacement only operand. */
10183 bigdisp
= i
.types
[this_operand
];
10184 bigdisp
.bitfield
.disp8
= 0;
10185 bigdisp
.bitfield
.disp16
= 0;
10186 bigdisp
.bitfield
.disp32
= 0;
10187 bigdisp
.bitfield
.disp32s
= 0;
10188 bigdisp
.bitfield
.disp64
= 0;
10189 if (operand_type_all_zero (&bigdisp
))
10190 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10196 /* Return the active addressing mode, taking address override and
10197 registers forming the address into consideration. Update the
10198 address override prefix if necessary. */
10200 static enum flag_code
10201 i386_addressing_mode (void)
10203 enum flag_code addr_mode
;
10205 if (i
.prefix
[ADDR_PREFIX
])
10206 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10209 addr_mode
= flag_code
;
10211 #if INFER_ADDR_PREFIX
10212 if (i
.mem_operands
== 0)
10214 /* Infer address prefix from the first memory operand. */
10215 const reg_entry
*addr_reg
= i
.base_reg
;
10217 if (addr_reg
== NULL
)
10218 addr_reg
= i
.index_reg
;
10222 if (addr_reg
->reg_type
.bitfield
.dword
)
10223 addr_mode
= CODE_32BIT
;
10224 else if (flag_code
!= CODE_64BIT
10225 && addr_reg
->reg_type
.bitfield
.word
)
10226 addr_mode
= CODE_16BIT
;
10228 if (addr_mode
!= flag_code
)
10230 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10232 /* Change the size of any displacement too. At most one
10233 of Disp16 or Disp32 is set.
10234 FIXME. There doesn't seem to be any real need for
10235 separate Disp16 and Disp32 flags. The same goes for
10236 Imm16 and Imm32. Removing them would probably clean
10237 up the code quite a lot. */
10238 if (flag_code
!= CODE_64BIT
10239 && (i
.types
[this_operand
].bitfield
.disp16
10240 || i
.types
[this_operand
].bitfield
.disp32
))
10241 i
.types
[this_operand
]
10242 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10252 /* Make sure the memory operand we've been dealt is valid.
10253 Return 1 on success, 0 on a failure. */
10256 i386_index_check (const char *operand_string
)
10258 const char *kind
= "base/index";
10259 enum flag_code addr_mode
= i386_addressing_mode ();
10261 if (current_templates
->start
->opcode_modifier
.isstring
10262 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
10263 && (current_templates
->end
[-1].opcode_modifier
.isstring
10264 || i
.mem_operands
))
10266 /* Memory operands of string insns are special in that they only allow
10267 a single register (rDI, rSI, or rBX) as their memory address. */
10268 const reg_entry
*expected_reg
;
10269 static const char *di_si
[][2] =
10275 static const char *bx
[] = { "ebx", "bx", "rbx" };
10277 kind
= "string address";
10279 if (current_templates
->start
->opcode_modifier
.repprefixok
)
10281 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
10282 - IS_STRING_ES_OP0
;
10285 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
10286 || ((!i
.mem_operands
!= !intel_syntax
)
10287 && current_templates
->end
[-1].operand_types
[1]
10288 .bitfield
.baseindex
))
10290 expected_reg
= hash_find (reg_hash
, di_si
[addr_mode
][op
== es_op
]);
10293 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
10295 if (i
.base_reg
!= expected_reg
10297 || operand_type_check (i
.types
[this_operand
], disp
))
10299 /* The second memory operand must have the same size as
10303 && !((addr_mode
== CODE_64BIT
10304 && i
.base_reg
->reg_type
.bitfield
.qword
)
10305 || (addr_mode
== CODE_32BIT
10306 ? i
.base_reg
->reg_type
.bitfield
.dword
10307 : i
.base_reg
->reg_type
.bitfield
.word
)))
10310 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
10312 intel_syntax
? '[' : '(',
10314 expected_reg
->reg_name
,
10315 intel_syntax
? ']' : ')');
10322 as_bad (_("`%s' is not a valid %s expression"),
10323 operand_string
, kind
);
10328 if (addr_mode
!= CODE_16BIT
)
10330 /* 32-bit/64-bit checks. */
10332 && ((addr_mode
== CODE_64BIT
10333 ? !i
.base_reg
->reg_type
.bitfield
.qword
10334 : !i
.base_reg
->reg_type
.bitfield
.dword
)
10335 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
10336 || i
.base_reg
->reg_num
== RegIZ
))
10338 && !i
.index_reg
->reg_type
.bitfield
.xmmword
10339 && !i
.index_reg
->reg_type
.bitfield
.ymmword
10340 && !i
.index_reg
->reg_type
.bitfield
.zmmword
10341 && ((addr_mode
== CODE_64BIT
10342 ? !i
.index_reg
->reg_type
.bitfield
.qword
10343 : !i
.index_reg
->reg_type
.bitfield
.dword
)
10344 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
10347 /* bndmk, bndldx, and bndstx have special restrictions. */
10348 if (current_templates
->start
->base_opcode
== 0xf30f1b
10349 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
10351 /* They cannot use RIP-relative addressing. */
10352 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
10354 as_bad (_("`%s' cannot be used here"), operand_string
);
10358 /* bndldx and bndstx ignore their scale factor. */
10359 if (current_templates
->start
->base_opcode
!= 0xf30f1b
10360 && i
.log2_scale_factor
)
10361 as_warn (_("register scaling is being ignored here"));
10366 /* 16-bit checks. */
10368 && (!i
.base_reg
->reg_type
.bitfield
.word
10369 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
10371 && (!i
.index_reg
->reg_type
.bitfield
.word
10372 || !i
.index_reg
->reg_type
.bitfield
.baseindex
10374 && i
.base_reg
->reg_num
< 6
10375 && i
.index_reg
->reg_num
>= 6
10376 && i
.log2_scale_factor
== 0))))
10383 /* Handle vector immediates. */
10386 RC_SAE_immediate (const char *imm_start
)
10388 unsigned int match_found
, j
;
10389 const char *pstr
= imm_start
;
10397 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
10399 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
10403 rc_op
.type
= RC_NamesTable
[j
].type
;
10404 rc_op
.operand
= this_operand
;
10405 i
.rounding
= &rc_op
;
10409 as_bad (_("duplicated `%s'"), imm_start
);
10412 pstr
+= RC_NamesTable
[j
].len
;
10420 if (*pstr
++ != '}')
10422 as_bad (_("Missing '}': '%s'"), imm_start
);
10425 /* RC/SAE immediate string should contain nothing more. */;
10428 as_bad (_("Junk after '}': '%s'"), imm_start
);
10432 exp
= &im_expressions
[i
.imm_operands
++];
10433 i
.op
[this_operand
].imms
= exp
;
10435 exp
->X_op
= O_constant
;
10436 exp
->X_add_number
= 0;
10437 exp
->X_add_symbol
= (symbolS
*) 0;
10438 exp
->X_op_symbol
= (symbolS
*) 0;
10440 i
.types
[this_operand
].bitfield
.imm8
= 1;
10444 /* Only string instructions can have a second memory operand, so
10445 reduce current_templates to just those if it contains any. */
10447 maybe_adjust_templates (void)
10449 const insn_template
*t
;
10451 gas_assert (i
.mem_operands
== 1);
10453 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
10454 if (t
->opcode_modifier
.isstring
)
10457 if (t
< current_templates
->end
)
10459 static templates aux_templates
;
10460 bfd_boolean recheck
;
10462 aux_templates
.start
= t
;
10463 for (; t
< current_templates
->end
; ++t
)
10464 if (!t
->opcode_modifier
.isstring
)
10466 aux_templates
.end
= t
;
10468 /* Determine whether to re-check the first memory operand. */
10469 recheck
= (aux_templates
.start
!= current_templates
->start
10470 || t
!= current_templates
->end
);
10472 current_templates
= &aux_templates
;
10476 i
.mem_operands
= 0;
10477 if (i
.memop1_string
!= NULL
10478 && i386_index_check (i
.memop1_string
) == 0)
10480 i
.mem_operands
= 1;
10487 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
10491 i386_att_operand (char *operand_string
)
10493 const reg_entry
*r
;
10495 char *op_string
= operand_string
;
10497 if (is_space_char (*op_string
))
10500 /* We check for an absolute prefix (differentiating,
10501 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
10502 if (*op_string
== ABSOLUTE_PREFIX
)
10505 if (is_space_char (*op_string
))
10507 i
.jumpabsolute
= TRUE
;
10510 /* Check if operand is a register. */
10511 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
10513 i386_operand_type temp
;
10515 /* Check for a segment override by searching for ':' after a
10516 segment register. */
10517 op_string
= end_op
;
10518 if (is_space_char (*op_string
))
10520 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
10522 switch (r
->reg_num
)
10525 i
.seg
[i
.mem_operands
] = &es
;
10528 i
.seg
[i
.mem_operands
] = &cs
;
10531 i
.seg
[i
.mem_operands
] = &ss
;
10534 i
.seg
[i
.mem_operands
] = &ds
;
10537 i
.seg
[i
.mem_operands
] = &fs
;
10540 i
.seg
[i
.mem_operands
] = &gs
;
10544 /* Skip the ':' and whitespace. */
10546 if (is_space_char (*op_string
))
10549 if (!is_digit_char (*op_string
)
10550 && !is_identifier_char (*op_string
)
10551 && *op_string
!= '('
10552 && *op_string
!= ABSOLUTE_PREFIX
)
10554 as_bad (_("bad memory operand `%s'"), op_string
);
10557 /* Handle case of %es:*foo. */
10558 if (*op_string
== ABSOLUTE_PREFIX
)
10561 if (is_space_char (*op_string
))
10563 i
.jumpabsolute
= TRUE
;
10565 goto do_memory_reference
;
10568 /* Handle vector operations. */
10569 if (*op_string
== '{')
10571 op_string
= check_VecOperations (op_string
, NULL
);
10572 if (op_string
== NULL
)
10578 as_bad (_("junk `%s' after register"), op_string
);
10581 temp
= r
->reg_type
;
10582 temp
.bitfield
.baseindex
= 0;
10583 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10585 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10586 i
.op
[this_operand
].regs
= r
;
10589 else if (*op_string
== REGISTER_PREFIX
)
10591 as_bad (_("bad register name `%s'"), op_string
);
10594 else if (*op_string
== IMMEDIATE_PREFIX
)
10597 if (i
.jumpabsolute
)
10599 as_bad (_("immediate operand illegal with absolute jump"));
10602 if (!i386_immediate (op_string
))
10605 else if (RC_SAE_immediate (operand_string
))
10607 /* If it is a RC or SAE immediate, do nothing. */
10610 else if (is_digit_char (*op_string
)
10611 || is_identifier_char (*op_string
)
10612 || *op_string
== '"'
10613 || *op_string
== '(')
10615 /* This is a memory reference of some sort. */
10618 /* Start and end of displacement string expression (if found). */
10619 char *displacement_string_start
;
10620 char *displacement_string_end
;
10623 do_memory_reference
:
10624 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10626 if ((i
.mem_operands
== 1
10627 && !current_templates
->start
->opcode_modifier
.isstring
)
10628 || i
.mem_operands
== 2)
10630 as_bad (_("too many memory references for `%s'"),
10631 current_templates
->start
->name
);
10635 /* Check for base index form. We detect the base index form by
10636 looking for an ')' at the end of the operand, searching
10637 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10639 base_string
= op_string
+ strlen (op_string
);
10641 /* Handle vector operations. */
10642 vop_start
= strchr (op_string
, '{');
10643 if (vop_start
&& vop_start
< base_string
)
10645 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10647 base_string
= vop_start
;
10651 if (is_space_char (*base_string
))
10654 /* If we only have a displacement, set-up for it to be parsed later. */
10655 displacement_string_start
= op_string
;
10656 displacement_string_end
= base_string
+ 1;
10658 if (*base_string
== ')')
10661 unsigned int parens_balanced
= 1;
10662 /* We've already checked that the number of left & right ()'s are
10663 equal, so this loop will not be infinite. */
10667 if (*base_string
== ')')
10669 if (*base_string
== '(')
10672 while (parens_balanced
);
10674 temp_string
= base_string
;
10676 /* Skip past '(' and whitespace. */
10678 if (is_space_char (*base_string
))
10681 if (*base_string
== ','
10682 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10685 displacement_string_end
= temp_string
;
10687 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10691 base_string
= end_op
;
10692 if (is_space_char (*base_string
))
10696 /* There may be an index reg or scale factor here. */
10697 if (*base_string
== ',')
10700 if (is_space_char (*base_string
))
10703 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10706 base_string
= end_op
;
10707 if (is_space_char (*base_string
))
10709 if (*base_string
== ',')
10712 if (is_space_char (*base_string
))
10715 else if (*base_string
!= ')')
10717 as_bad (_("expecting `,' or `)' "
10718 "after index register in `%s'"),
10723 else if (*base_string
== REGISTER_PREFIX
)
10725 end_op
= strchr (base_string
, ',');
10728 as_bad (_("bad register name `%s'"), base_string
);
10732 /* Check for scale factor. */
10733 if (*base_string
!= ')')
10735 char *end_scale
= i386_scale (base_string
);
10740 base_string
= end_scale
;
10741 if (is_space_char (*base_string
))
10743 if (*base_string
!= ')')
10745 as_bad (_("expecting `)' "
10746 "after scale factor in `%s'"),
10751 else if (!i
.index_reg
)
10753 as_bad (_("expecting index register or scale factor "
10754 "after `,'; got '%c'"),
10759 else if (*base_string
!= ')')
10761 as_bad (_("expecting `,' or `)' "
10762 "after base register in `%s'"),
10767 else if (*base_string
== REGISTER_PREFIX
)
10769 end_op
= strchr (base_string
, ',');
10772 as_bad (_("bad register name `%s'"), base_string
);
10777 /* If there's an expression beginning the operand, parse it,
10778 assuming displacement_string_start and
10779 displacement_string_end are meaningful. */
10780 if (displacement_string_start
!= displacement_string_end
)
10782 if (!i386_displacement (displacement_string_start
,
10783 displacement_string_end
))
10787 /* Special case for (%dx) while doing input/output op. */
10789 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
10790 && i
.base_reg
->reg_type
.bitfield
.word
10791 && i
.index_reg
== 0
10792 && i
.log2_scale_factor
== 0
10793 && i
.seg
[i
.mem_operands
] == 0
10794 && !operand_type_check (i
.types
[this_operand
], disp
))
10796 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10800 if (i386_index_check (operand_string
) == 0)
10802 i
.flags
[this_operand
] |= Operand_Mem
;
10803 if (i
.mem_operands
== 0)
10804 i
.memop1_string
= xstrdup (operand_string
);
10809 /* It's not a memory operand; argh! */
10810 as_bad (_("invalid char %s beginning operand %d `%s'"),
10811 output_invalid (*op_string
),
10816 return 1; /* Normal return. */
10819 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10820 that an rs_machine_dependent frag may reach. */
10823 i386_frag_max_var (fragS
*frag
)
10825 /* The only relaxable frags are for jumps.
10826 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10827 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10828 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10831 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10833 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10835 /* STT_GNU_IFUNC symbol must go through PLT. */
10836 if ((symbol_get_bfdsym (fr_symbol
)->flags
10837 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10840 if (!S_IS_EXTERNAL (fr_symbol
))
10841 /* Symbol may be weak or local. */
10842 return !S_IS_WEAK (fr_symbol
);
10844 /* Global symbols with non-default visibility can't be preempted. */
10845 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10848 if (fr_var
!= NO_RELOC
)
10849 switch ((enum bfd_reloc_code_real
) fr_var
)
10851 case BFD_RELOC_386_PLT32
:
10852 case BFD_RELOC_X86_64_PLT32
:
10853 /* Symbol with PLT relocation may be preempted. */
10859 /* Global symbols with default visibility in a shared library may be
10860 preempted by another definition. */
10865 /* Return the next non-empty frag. */
10868 i386_next_non_empty_frag (fragS
*fragP
)
10870 /* There may be a frag with a ".fill 0" when there is no room in
10871 the current frag for frag_grow in output_insn. */
10872 for (fragP
= fragP
->fr_next
;
10874 && fragP
->fr_type
== rs_fill
10875 && fragP
->fr_fix
== 0);
10876 fragP
= fragP
->fr_next
)
10881 /* Return the next jcc frag after BRANCH_PADDING. */
10884 i386_next_jcc_frag (fragS
*fragP
)
10889 if (fragP
->fr_type
== rs_machine_dependent
10890 && (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10891 == BRANCH_PADDING
))
10893 fragP
= i386_next_non_empty_frag (fragP
);
10894 if (fragP
->fr_type
!= rs_machine_dependent
)
10896 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == COND_JUMP
)
10903 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
10906 i386_classify_machine_dependent_frag (fragS
*fragP
)
10910 fragS
*branch_fragP
;
10912 unsigned int max_prefix_length
;
10914 if (fragP
->tc_frag_data
.classified
)
10917 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
10918 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
10919 for (next_fragP
= fragP
;
10920 next_fragP
!= NULL
;
10921 next_fragP
= next_fragP
->fr_next
)
10923 next_fragP
->tc_frag_data
.classified
= 1;
10924 if (next_fragP
->fr_type
== rs_machine_dependent
)
10925 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
10927 case BRANCH_PADDING
:
10928 /* The BRANCH_PADDING frag must be followed by a branch
10930 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
10931 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
10933 case FUSED_JCC_PADDING
:
10934 /* Check if this is a fused jcc:
10936 CMP like instruction
10940 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
10941 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
10942 branch_fragP
= i386_next_jcc_frag (pad_fragP
);
10945 /* The BRANCH_PADDING frag is merged with the
10946 FUSED_JCC_PADDING frag. */
10947 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
10948 /* CMP like instruction size. */
10949 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
10950 frag_wane (pad_fragP
);
10951 /* Skip to branch_fragP. */
10952 next_fragP
= branch_fragP
;
10954 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
10956 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
10958 next_fragP
->fr_subtype
10959 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
10960 next_fragP
->tc_frag_data
.max_bytes
10961 = next_fragP
->tc_frag_data
.max_prefix_length
;
10962 /* This will be updated in the BRANCH_PREFIX scan. */
10963 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
10966 frag_wane (next_fragP
);
10971 /* Stop if there is no BRANCH_PREFIX. */
10972 if (!align_branch_prefix_size
)
10975 /* Scan for BRANCH_PREFIX. */
10976 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
10978 if (fragP
->fr_type
!= rs_machine_dependent
10979 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10983 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
10984 COND_JUMP_PREFIX. */
10985 max_prefix_length
= 0;
10986 for (next_fragP
= fragP
;
10987 next_fragP
!= NULL
;
10988 next_fragP
= next_fragP
->fr_next
)
10990 if (next_fragP
->fr_type
== rs_fill
)
10991 /* Skip rs_fill frags. */
10993 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
10994 /* Stop for all other frags. */
10997 /* rs_machine_dependent frags. */
10998 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11001 /* Count BRANCH_PREFIX frags. */
11002 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11004 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11005 frag_wane (next_fragP
);
11009 += next_fragP
->tc_frag_data
.max_bytes
;
11011 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11013 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11014 == FUSED_JCC_PADDING
))
11016 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11017 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11021 /* Stop for other rs_machine_dependent frags. */
11025 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11027 /* Skip to the next frag. */
11028 fragP
= next_fragP
;
11032 /* Compute padding size for
11035 CMP like instruction
11037 COND_JUMP/UNCOND_JUMP
11042 COND_JUMP/UNCOND_JUMP
11046 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11048 unsigned int offset
, size
, padding_size
;
11049 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11051 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11053 address
= fragP
->fr_address
;
11054 address
+= fragP
->fr_fix
;
11056 /* CMP like instrunction size. */
11057 size
= fragP
->tc_frag_data
.cmp_size
;
11059 /* The base size of the branch frag. */
11060 size
+= branch_fragP
->fr_fix
;
11062 /* Add opcode and displacement bytes for the rs_machine_dependent
11064 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11065 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11067 /* Check if branch is within boundary and doesn't end at the last
11069 offset
= address
& ((1U << align_branch_power
) - 1);
11070 if ((offset
+ size
) >= (1U << align_branch_power
))
11071 /* Padding needed to avoid crossing boundary. */
11072 padding_size
= (1U << align_branch_power
) - offset
;
11074 /* No padding needed. */
11077 /* The return value may be saved in tc_frag_data.length which is
11079 if (!fits_in_unsigned_byte (padding_size
))
11082 return padding_size
;
11085 /* i386_generic_table_relax_frag()
11087 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11088 grow/shrink padding to align branch frags. Hand others to
11092 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11094 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11095 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11097 long padding_size
= i386_branch_padding_size (fragP
, 0);
11098 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11100 /* When the BRANCH_PREFIX frag is used, the computed address
11101 must match the actual address and there should be no padding. */
11102 if (fragP
->tc_frag_data
.padding_address
11103 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11107 /* Update the padding size. */
11109 fragP
->tc_frag_data
.length
= padding_size
;
11113 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11115 fragS
*padding_fragP
, *next_fragP
;
11116 long padding_size
, left_size
, last_size
;
11118 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11119 if (!padding_fragP
)
11120 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11121 return (fragP
->tc_frag_data
.length
11122 - fragP
->tc_frag_data
.last_length
);
11124 /* Compute the relative address of the padding frag in the very
11125 first time where the BRANCH_PREFIX frag sizes are zero. */
11126 if (!fragP
->tc_frag_data
.padding_address
)
11127 fragP
->tc_frag_data
.padding_address
11128 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11130 /* First update the last length from the previous interation. */
11131 left_size
= fragP
->tc_frag_data
.prefix_length
;
11132 for (next_fragP
= fragP
;
11133 next_fragP
!= padding_fragP
;
11134 next_fragP
= next_fragP
->fr_next
)
11135 if (next_fragP
->fr_type
== rs_machine_dependent
11136 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11141 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11145 if (max
> left_size
)
11150 next_fragP
->tc_frag_data
.last_length
= size
;
11154 next_fragP
->tc_frag_data
.last_length
= 0;
11157 /* Check the padding size for the padding frag. */
11158 padding_size
= i386_branch_padding_size
11159 (padding_fragP
, (fragP
->fr_address
11160 + fragP
->tc_frag_data
.padding_address
));
11162 last_size
= fragP
->tc_frag_data
.prefix_length
;
11163 /* Check if there is change from the last interation. */
11164 if (padding_size
== last_size
)
11166 /* Update the expected address of the padding frag. */
11167 padding_fragP
->tc_frag_data
.padding_address
11168 = (fragP
->fr_address
+ padding_size
11169 + fragP
->tc_frag_data
.padding_address
);
11173 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11175 /* No padding if there is no sufficient room. Clear the
11176 expected address of the padding frag. */
11177 padding_fragP
->tc_frag_data
.padding_address
= 0;
11181 /* Store the expected address of the padding frag. */
11182 padding_fragP
->tc_frag_data
.padding_address
11183 = (fragP
->fr_address
+ padding_size
11184 + fragP
->tc_frag_data
.padding_address
);
11186 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11188 /* Update the length for the current interation. */
11189 left_size
= padding_size
;
11190 for (next_fragP
= fragP
;
11191 next_fragP
!= padding_fragP
;
11192 next_fragP
= next_fragP
->fr_next
)
11193 if (next_fragP
->fr_type
== rs_machine_dependent
11194 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11199 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11203 if (max
> left_size
)
11208 next_fragP
->tc_frag_data
.length
= size
;
11212 next_fragP
->tc_frag_data
.length
= 0;
11215 return (fragP
->tc_frag_data
.length
11216 - fragP
->tc_frag_data
.last_length
);
11218 return relax_frag (segment
, fragP
, stretch
);
11221 /* md_estimate_size_before_relax()
11223 Called just before relax() for rs_machine_dependent frags. The x86
11224 assembler uses these frags to handle variable size jump
11227 Any symbol that is now undefined will not become defined.
11228 Return the correct fr_subtype in the frag.
11229 Return the initial "guess for variable size of frag" to caller.
11230 The guess is actually the growth beyond the fixed part. Whatever
11231 we do to grow the fixed or variable part contributes to our
11235 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
11237 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11238 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
11239 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11241 i386_classify_machine_dependent_frag (fragP
);
11242 return fragP
->tc_frag_data
.length
;
11245 /* We've already got fragP->fr_subtype right; all we have to do is
11246 check for un-relaxable symbols. On an ELF system, we can't relax
11247 an externally visible symbol, because it may be overridden by a
11249 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
11250 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11252 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
11255 #if defined (OBJ_COFF) && defined (TE_PE)
11256 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
11257 && S_IS_WEAK (fragP
->fr_symbol
))
11261 /* Symbol is undefined in this segment, or we need to keep a
11262 reloc so that weak symbols can be overridden. */
11263 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
11264 enum bfd_reloc_code_real reloc_type
;
11265 unsigned char *opcode
;
11268 if (fragP
->fr_var
!= NO_RELOC
)
11269 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
11270 else if (size
== 2)
11271 reloc_type
= BFD_RELOC_16_PCREL
;
11272 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11273 else if (need_plt32_p (fragP
->fr_symbol
))
11274 reloc_type
= BFD_RELOC_X86_64_PLT32
;
11277 reloc_type
= BFD_RELOC_32_PCREL
;
11279 old_fr_fix
= fragP
->fr_fix
;
11280 opcode
= (unsigned char *) fragP
->fr_opcode
;
11282 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
11285 /* Make jmp (0xeb) a (d)word displacement jump. */
11287 fragP
->fr_fix
+= size
;
11288 fix_new (fragP
, old_fr_fix
, size
,
11290 fragP
->fr_offset
, 1,
11296 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
11298 /* Negate the condition, and branch past an
11299 unconditional jump. */
11302 /* Insert an unconditional jump. */
11304 /* We added two extra opcode bytes, and have a two byte
11306 fragP
->fr_fix
+= 2 + 2;
11307 fix_new (fragP
, old_fr_fix
+ 2, 2,
11309 fragP
->fr_offset
, 1,
11313 /* Fall through. */
11316 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
11320 fragP
->fr_fix
+= 1;
11321 fixP
= fix_new (fragP
, old_fr_fix
, 1,
11323 fragP
->fr_offset
, 1,
11324 BFD_RELOC_8_PCREL
);
11325 fixP
->fx_signed
= 1;
11329 /* This changes the byte-displacement jump 0x7N
11330 to the (d)word-displacement jump 0x0f,0x8N. */
11331 opcode
[1] = opcode
[0] + 0x10;
11332 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11333 /* We've added an opcode byte. */
11334 fragP
->fr_fix
+= 1 + size
;
11335 fix_new (fragP
, old_fr_fix
+ 1, size
,
11337 fragP
->fr_offset
, 1,
11342 BAD_CASE (fragP
->fr_subtype
);
11346 return fragP
->fr_fix
- old_fr_fix
;
11349 /* Guess size depending on current relax state. Initially the relax
11350 state will correspond to a short jump and we return 1, because
11351 the variable part of the frag (the branch offset) is one byte
11352 long. However, we can relax a section more than once and in that
11353 case we must either set fr_subtype back to the unrelaxed state,
11354 or return the value for the appropriate branch. */
11355 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
11358 /* Called after relax() is finished.
11360 In: Address of frag.
11361 fr_type == rs_machine_dependent.
11362 fr_subtype is what the address relaxed to.
11364 Out: Any fixSs and constants are set up.
11365 Caller will turn frag into a ".space 0". */
11368 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
11371 unsigned char *opcode
;
11372 unsigned char *where_to_put_displacement
= NULL
;
11373 offsetT target_address
;
11374 offsetT opcode_address
;
11375 unsigned int extension
= 0;
11376 offsetT displacement_from_opcode_start
;
11378 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11379 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
11380 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11382 /* Generate nop padding. */
11383 unsigned int size
= fragP
->tc_frag_data
.length
;
11386 if (size
> fragP
->tc_frag_data
.max_bytes
)
11392 const char *branch
= "branch";
11393 const char *prefix
= "";
11394 fragS
*padding_fragP
;
11395 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11398 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11399 switch (fragP
->tc_frag_data
.default_prefix
)
11404 case CS_PREFIX_OPCODE
:
11407 case DS_PREFIX_OPCODE
:
11410 case ES_PREFIX_OPCODE
:
11413 case FS_PREFIX_OPCODE
:
11416 case GS_PREFIX_OPCODE
:
11419 case SS_PREFIX_OPCODE
:
11424 msg
= _("%s:%u: add %d%s at 0x%llx to align "
11425 "%s within %d-byte boundary\n");
11427 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
11428 "align %s within %d-byte boundary\n");
11432 padding_fragP
= fragP
;
11433 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
11434 "%s within %d-byte boundary\n");
11438 switch (padding_fragP
->tc_frag_data
.branch_type
)
11440 case align_branch_jcc
:
11443 case align_branch_fused
:
11444 branch
= "fused jcc";
11446 case align_branch_jmp
:
11449 case align_branch_call
:
11452 case align_branch_indirect
:
11453 branch
= "indiret branch";
11455 case align_branch_ret
:
11462 fprintf (stdout
, msg
,
11463 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
11464 (long long) fragP
->fr_address
, branch
,
11465 1 << align_branch_power
);
11467 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11468 memset (fragP
->fr_opcode
,
11469 fragP
->tc_frag_data
.default_prefix
, size
);
11471 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
11473 fragP
->fr_fix
+= size
;
11478 opcode
= (unsigned char *) fragP
->fr_opcode
;
11480 /* Address we want to reach in file space. */
11481 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
11483 /* Address opcode resides at in file space. */
11484 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
11486 /* Displacement from opcode start to fill into instruction. */
11487 displacement_from_opcode_start
= target_address
- opcode_address
;
11489 if ((fragP
->fr_subtype
& BIG
) == 0)
11491 /* Don't have to change opcode. */
11492 extension
= 1; /* 1 opcode + 1 displacement */
11493 where_to_put_displacement
= &opcode
[1];
11497 if (no_cond_jump_promotion
11498 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
11499 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
11500 _("long jump required"));
11502 switch (fragP
->fr_subtype
)
11504 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
11505 extension
= 4; /* 1 opcode + 4 displacement */
11507 where_to_put_displacement
= &opcode
[1];
11510 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
11511 extension
= 2; /* 1 opcode + 2 displacement */
11513 where_to_put_displacement
= &opcode
[1];
11516 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
11517 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
11518 extension
= 5; /* 2 opcode + 4 displacement */
11519 opcode
[1] = opcode
[0] + 0x10;
11520 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11521 where_to_put_displacement
= &opcode
[2];
11524 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
11525 extension
= 3; /* 2 opcode + 2 displacement */
11526 opcode
[1] = opcode
[0] + 0x10;
11527 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11528 where_to_put_displacement
= &opcode
[2];
11531 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
11536 where_to_put_displacement
= &opcode
[3];
11540 BAD_CASE (fragP
->fr_subtype
);
11545 /* If size if less then four we are sure that the operand fits,
11546 but if it's 4, then it could be that the displacement is larger
11548 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
11550 && ((addressT
) (displacement_from_opcode_start
- extension
11551 + ((addressT
) 1 << 31))
11552 > (((addressT
) 2 << 31) - 1)))
11554 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
11555 _("jump target out of range"));
11556 /* Make us emit 0. */
11557 displacement_from_opcode_start
= extension
;
11559 /* Now put displacement after opcode. */
11560 md_number_to_chars ((char *) where_to_put_displacement
,
11561 (valueT
) (displacement_from_opcode_start
- extension
),
11562 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
11563 fragP
->fr_fix
+= extension
;
11566 /* Apply a fixup (fixP) to segment data, once it has been determined
11567 by our caller that we have all the info we need to fix it up.
11569 Parameter valP is the pointer to the value of the bits.
11571 On the 386, immediates, displacements, and data pointers are all in
11572 the same (little-endian) format, so we don't need to care about which
11573 we are handling. */
11576 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11578 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
11579 valueT value
= *valP
;
11581 #if !defined (TE_Mach)
11582 if (fixP
->fx_pcrel
)
11584 switch (fixP
->fx_r_type
)
11590 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
11593 case BFD_RELOC_X86_64_32S
:
11594 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
11597 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
11600 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
11605 if (fixP
->fx_addsy
!= NULL
11606 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
11607 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
11608 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
11609 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
11610 && !use_rela_relocations
)
11612 /* This is a hack. There should be a better way to handle this.
11613 This covers for the fact that bfd_install_relocation will
11614 subtract the current location (for partial_inplace, PC relative
11615 relocations); see more below. */
11619 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
11622 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11624 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11627 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
11629 if ((sym_seg
== seg
11630 || (symbol_section_p (fixP
->fx_addsy
)
11631 && sym_seg
!= absolute_section
))
11632 && !generic_force_reloc (fixP
))
11634 /* Yes, we add the values in twice. This is because
11635 bfd_install_relocation subtracts them out again. I think
11636 bfd_install_relocation is broken, but I don't dare change
11638 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11642 #if defined (OBJ_COFF) && defined (TE_PE)
11643 /* For some reason, the PE format does not store a
11644 section address offset for a PC relative symbol. */
11645 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
11646 || S_IS_WEAK (fixP
->fx_addsy
))
11647 value
+= md_pcrel_from (fixP
);
11650 #if defined (OBJ_COFF) && defined (TE_PE)
11651 if (fixP
->fx_addsy
!= NULL
11652 && S_IS_WEAK (fixP
->fx_addsy
)
11653 /* PR 16858: Do not modify weak function references. */
11654 && ! fixP
->fx_pcrel
)
11656 #if !defined (TE_PEP)
11657 /* For x86 PE weak function symbols are neither PC-relative
11658 nor do they set S_IS_FUNCTION. So the only reliable way
11659 to detect them is to check the flags of their containing
11661 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
11662 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
11666 value
-= S_GET_VALUE (fixP
->fx_addsy
);
11670 /* Fix a few things - the dynamic linker expects certain values here,
11671 and we must not disappoint it. */
11672 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11673 if (IS_ELF
&& fixP
->fx_addsy
)
11674 switch (fixP
->fx_r_type
)
11676 case BFD_RELOC_386_PLT32
:
11677 case BFD_RELOC_X86_64_PLT32
:
11678 /* Make the jump instruction point to the address of the operand.
11679 At runtime we merely add the offset to the actual PLT entry.
11680 NB: Subtract the offset size only for jump instructions. */
11681 if (fixP
->fx_pcrel
)
11685 case BFD_RELOC_386_TLS_GD
:
11686 case BFD_RELOC_386_TLS_LDM
:
11687 case BFD_RELOC_386_TLS_IE_32
:
11688 case BFD_RELOC_386_TLS_IE
:
11689 case BFD_RELOC_386_TLS_GOTIE
:
11690 case BFD_RELOC_386_TLS_GOTDESC
:
11691 case BFD_RELOC_X86_64_TLSGD
:
11692 case BFD_RELOC_X86_64_TLSLD
:
11693 case BFD_RELOC_X86_64_GOTTPOFF
:
11694 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11695 value
= 0; /* Fully resolved at runtime. No addend. */
11697 case BFD_RELOC_386_TLS_LE
:
11698 case BFD_RELOC_386_TLS_LDO_32
:
11699 case BFD_RELOC_386_TLS_LE_32
:
11700 case BFD_RELOC_X86_64_DTPOFF32
:
11701 case BFD_RELOC_X86_64_DTPOFF64
:
11702 case BFD_RELOC_X86_64_TPOFF32
:
11703 case BFD_RELOC_X86_64_TPOFF64
:
11704 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11707 case BFD_RELOC_386_TLS_DESC_CALL
:
11708 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11709 value
= 0; /* Fully resolved at runtime. No addend. */
11710 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11714 case BFD_RELOC_VTABLE_INHERIT
:
11715 case BFD_RELOC_VTABLE_ENTRY
:
11722 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
11724 #endif /* !defined (TE_Mach) */
11726 /* Are we finished with this relocation now? */
11727 if (fixP
->fx_addsy
== NULL
)
11729 #if defined (OBJ_COFF) && defined (TE_PE)
11730 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
11733 /* Remember value for tc_gen_reloc. */
11734 fixP
->fx_addnumber
= value
;
11735 /* Clear out the frag for now. */
11739 else if (use_rela_relocations
)
11741 fixP
->fx_no_overflow
= 1;
11742 /* Remember value for tc_gen_reloc. */
11743 fixP
->fx_addnumber
= value
;
11747 md_number_to_chars (p
, value
, fixP
->fx_size
);
11751 md_atof (int type
, char *litP
, int *sizeP
)
11753 /* This outputs the LITTLENUMs in REVERSE order;
11754 in accord with the bigendian 386. */
11755 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
11758 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
11761 output_invalid (int c
)
11764 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
11767 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
11768 "(0x%x)", (unsigned char) c
);
11769 return output_invalid_buf
;
11772 /* REG_STRING starts *before* REGISTER_PREFIX. */
11774 static const reg_entry
*
11775 parse_real_register (char *reg_string
, char **end_op
)
11777 char *s
= reg_string
;
11779 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
11780 const reg_entry
*r
;
11782 /* Skip possible REGISTER_PREFIX and possible whitespace. */
11783 if (*s
== REGISTER_PREFIX
)
11786 if (is_space_char (*s
))
11789 p
= reg_name_given
;
11790 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
11792 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
11793 return (const reg_entry
*) NULL
;
11797 /* For naked regs, make sure that we are not dealing with an identifier.
11798 This prevents confusing an identifier like `eax_var' with register
11800 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
11801 return (const reg_entry
*) NULL
;
11805 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
11807 /* Handle floating point regs, allowing spaces in the (i) part. */
11808 if (r
== i386_regtab
/* %st is first entry of table */)
11810 if (!cpu_arch_flags
.bitfield
.cpu8087
11811 && !cpu_arch_flags
.bitfield
.cpu287
11812 && !cpu_arch_flags
.bitfield
.cpu387
)
11813 return (const reg_entry
*) NULL
;
11815 if (is_space_char (*s
))
11820 if (is_space_char (*s
))
11822 if (*s
>= '0' && *s
<= '7')
11824 int fpr
= *s
- '0';
11826 if (is_space_char (*s
))
11831 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
11836 /* We have "%st(" then garbage. */
11837 return (const reg_entry
*) NULL
;
11841 if (r
== NULL
|| allow_pseudo_reg
)
11844 if (operand_type_all_zero (&r
->reg_type
))
11845 return (const reg_entry
*) NULL
;
11847 if ((r
->reg_type
.bitfield
.dword
11848 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
11849 || r
->reg_type
.bitfield
.class == RegCR
11850 || r
->reg_type
.bitfield
.class == RegDR
11851 || r
->reg_type
.bitfield
.class == RegTR
)
11852 && !cpu_arch_flags
.bitfield
.cpui386
)
11853 return (const reg_entry
*) NULL
;
11855 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
11856 return (const reg_entry
*) NULL
;
11858 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
11860 if (r
->reg_type
.bitfield
.zmmword
11861 || r
->reg_type
.bitfield
.class == RegMask
)
11862 return (const reg_entry
*) NULL
;
11864 if (!cpu_arch_flags
.bitfield
.cpuavx
)
11866 if (r
->reg_type
.bitfield
.ymmword
)
11867 return (const reg_entry
*) NULL
;
11869 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
11870 return (const reg_entry
*) NULL
;
11874 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
11875 return (const reg_entry
*) NULL
;
11877 /* Don't allow fake index register unless allow_index_reg isn't 0. */
11878 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
11879 return (const reg_entry
*) NULL
;
11881 /* Upper 16 vector registers are only available with VREX in 64bit
11882 mode, and require EVEX encoding. */
11883 if (r
->reg_flags
& RegVRex
)
11885 if (!cpu_arch_flags
.bitfield
.cpuavx512f
11886 || flag_code
!= CODE_64BIT
)
11887 return (const reg_entry
*) NULL
;
11889 i
.vec_encoding
= vex_encoding_evex
;
11892 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
11893 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
11894 && flag_code
!= CODE_64BIT
)
11895 return (const reg_entry
*) NULL
;
11897 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
11899 return (const reg_entry
*) NULL
;
11904 /* REG_STRING starts *before* REGISTER_PREFIX. */
11906 static const reg_entry
*
11907 parse_register (char *reg_string
, char **end_op
)
11909 const reg_entry
*r
;
11911 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
11912 r
= parse_real_register (reg_string
, end_op
);
11917 char *save
= input_line_pointer
;
11921 input_line_pointer
= reg_string
;
11922 c
= get_symbol_name (®_string
);
11923 symbolP
= symbol_find (reg_string
);
11924 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
11926 const expressionS
*e
= symbol_get_value_expression (symbolP
);
11928 know (e
->X_op
== O_register
);
11929 know (e
->X_add_number
>= 0
11930 && (valueT
) e
->X_add_number
< i386_regtab_size
);
11931 r
= i386_regtab
+ e
->X_add_number
;
11932 if ((r
->reg_flags
& RegVRex
))
11933 i
.vec_encoding
= vex_encoding_evex
;
11934 *end_op
= input_line_pointer
;
11936 *input_line_pointer
= c
;
11937 input_line_pointer
= save
;
11943 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
11945 const reg_entry
*r
;
11946 char *end
= input_line_pointer
;
11949 r
= parse_register (name
, &input_line_pointer
);
11950 if (r
&& end
<= input_line_pointer
)
11952 *nextcharP
= *input_line_pointer
;
11953 *input_line_pointer
= 0;
11954 e
->X_op
= O_register
;
11955 e
->X_add_number
= r
- i386_regtab
;
11958 input_line_pointer
= end
;
11960 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
11964 md_operand (expressionS
*e
)
11967 const reg_entry
*r
;
11969 switch (*input_line_pointer
)
11971 case REGISTER_PREFIX
:
11972 r
= parse_real_register (input_line_pointer
, &end
);
11975 e
->X_op
= O_register
;
11976 e
->X_add_number
= r
- i386_regtab
;
11977 input_line_pointer
= end
;
11982 gas_assert (intel_syntax
);
11983 end
= input_line_pointer
++;
11985 if (*input_line_pointer
== ']')
11987 ++input_line_pointer
;
11988 e
->X_op_symbol
= make_expr_symbol (e
);
11989 e
->X_add_symbol
= NULL
;
11990 e
->X_add_number
= 0;
11995 e
->X_op
= O_absent
;
11996 input_line_pointer
= end
;
12003 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12004 const char *md_shortopts
= "kVQ:sqnO::";
12006 const char *md_shortopts
= "qnO::";
12009 #define OPTION_32 (OPTION_MD_BASE + 0)
12010 #define OPTION_64 (OPTION_MD_BASE + 1)
12011 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12012 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12013 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12014 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12015 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12016 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12017 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12018 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12019 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12020 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12021 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12022 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12023 #define OPTION_X32 (OPTION_MD_BASE + 14)
12024 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12025 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12026 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12027 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12028 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12029 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12030 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12031 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12032 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12033 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12034 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12035 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12036 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12037 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12038 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12039 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12041 struct option md_longopts
[] =
12043 {"32", no_argument
, NULL
, OPTION_32
},
12044 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12045 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12046 {"64", no_argument
, NULL
, OPTION_64
},
12048 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12049 {"x32", no_argument
, NULL
, OPTION_X32
},
12050 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12051 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12053 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12054 {"march", required_argument
, NULL
, OPTION_MARCH
},
12055 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12056 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12057 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12058 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12059 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12060 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12061 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12062 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12063 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12064 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12065 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12066 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12067 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12068 # if defined (TE_PE) || defined (TE_PEP)
12069 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12071 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12072 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12073 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12074 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12075 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12076 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12077 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12078 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12079 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12080 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12081 {NULL
, no_argument
, NULL
, 0}
12083 size_t md_longopts_size
= sizeof (md_longopts
);
12086 md_parse_option (int c
, const char *arg
)
12089 char *arch
, *next
, *saved
, *type
;
12094 optimize_align_code
= 0;
12098 quiet_warnings
= 1;
12101 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12102 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12103 should be emitted or not. FIXME: Not implemented. */
12105 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12109 /* -V: SVR4 argument to print version ID. */
12111 print_version_id ();
12114 /* -k: Ignore for FreeBSD compatibility. */
12119 /* -s: On i386 Solaris, this tells the native assembler to use
12120 .stab instead of .stab.excl. We always use .stab anyhow. */
12123 case OPTION_MSHARED
:
12127 case OPTION_X86_USED_NOTE
:
12128 if (strcasecmp (arg
, "yes") == 0)
12130 else if (strcasecmp (arg
, "no") == 0)
12133 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12138 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12139 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12142 const char **list
, **l
;
12144 list
= bfd_target_list ();
12145 for (l
= list
; *l
!= NULL
; l
++)
12146 if (CONST_STRNEQ (*l
, "elf64-x86-64")
12147 || strcmp (*l
, "coff-x86-64") == 0
12148 || strcmp (*l
, "pe-x86-64") == 0
12149 || strcmp (*l
, "pei-x86-64") == 0
12150 || strcmp (*l
, "mach-o-x86-64") == 0)
12152 default_arch
= "x86_64";
12156 as_fatal (_("no compiled in support for x86_64"));
12162 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12166 const char **list
, **l
;
12168 list
= bfd_target_list ();
12169 for (l
= list
; *l
!= NULL
; l
++)
12170 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
12172 default_arch
= "x86_64:32";
12176 as_fatal (_("no compiled in support for 32bit x86_64"));
12180 as_fatal (_("32bit x86_64 is only supported for ELF"));
12185 default_arch
= "i386";
12188 case OPTION_DIVIDE
:
12189 #ifdef SVR4_COMMENT_CHARS
12194 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
12196 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
12200 i386_comment_chars
= n
;
12206 saved
= xstrdup (arg
);
12208 /* Allow -march=+nosse. */
12214 as_fatal (_("invalid -march= option: `%s'"), arg
);
12215 next
= strchr (arch
, '+');
12218 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12220 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
12223 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12226 cpu_arch_name
= cpu_arch
[j
].name
;
12227 cpu_sub_arch_name
= NULL
;
12228 cpu_arch_flags
= cpu_arch
[j
].flags
;
12229 cpu_arch_isa
= cpu_arch
[j
].type
;
12230 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
12231 if (!cpu_arch_tune_set
)
12233 cpu_arch_tune
= cpu_arch_isa
;
12234 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12238 else if (*cpu_arch
[j
].name
== '.'
12239 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
12241 /* ISA extension. */
12242 i386_cpu_flags flags
;
12244 flags
= cpu_flags_or (cpu_arch_flags
,
12245 cpu_arch
[j
].flags
);
12247 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12249 if (cpu_sub_arch_name
)
12251 char *name
= cpu_sub_arch_name
;
12252 cpu_sub_arch_name
= concat (name
,
12254 (const char *) NULL
);
12258 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
12259 cpu_arch_flags
= flags
;
12260 cpu_arch_isa_flags
= flags
;
12264 = cpu_flags_or (cpu_arch_isa_flags
,
12265 cpu_arch
[j
].flags
);
12270 if (j
>= ARRAY_SIZE (cpu_arch
))
12272 /* Disable an ISA extension. */
12273 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12274 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
12276 i386_cpu_flags flags
;
12278 flags
= cpu_flags_and_not (cpu_arch_flags
,
12279 cpu_noarch
[j
].flags
);
12280 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12282 if (cpu_sub_arch_name
)
12284 char *name
= cpu_sub_arch_name
;
12285 cpu_sub_arch_name
= concat (arch
,
12286 (const char *) NULL
);
12290 cpu_sub_arch_name
= xstrdup (arch
);
12291 cpu_arch_flags
= flags
;
12292 cpu_arch_isa_flags
= flags
;
12297 if (j
>= ARRAY_SIZE (cpu_noarch
))
12298 j
= ARRAY_SIZE (cpu_arch
);
12301 if (j
>= ARRAY_SIZE (cpu_arch
))
12302 as_fatal (_("invalid -march= option: `%s'"), arg
);
12306 while (next
!= NULL
);
12312 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12313 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12315 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
12317 cpu_arch_tune_set
= 1;
12318 cpu_arch_tune
= cpu_arch
[j
].type
;
12319 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
12323 if (j
>= ARRAY_SIZE (cpu_arch
))
12324 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12327 case OPTION_MMNEMONIC
:
12328 if (strcasecmp (arg
, "att") == 0)
12329 intel_mnemonic
= 0;
12330 else if (strcasecmp (arg
, "intel") == 0)
12331 intel_mnemonic
= 1;
12333 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
12336 case OPTION_MSYNTAX
:
12337 if (strcasecmp (arg
, "att") == 0)
12339 else if (strcasecmp (arg
, "intel") == 0)
12342 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
12345 case OPTION_MINDEX_REG
:
12346 allow_index_reg
= 1;
12349 case OPTION_MNAKED_REG
:
12350 allow_naked_reg
= 1;
12353 case OPTION_MSSE2AVX
:
12357 case OPTION_MSSE_CHECK
:
12358 if (strcasecmp (arg
, "error") == 0)
12359 sse_check
= check_error
;
12360 else if (strcasecmp (arg
, "warning") == 0)
12361 sse_check
= check_warning
;
12362 else if (strcasecmp (arg
, "none") == 0)
12363 sse_check
= check_none
;
12365 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
12368 case OPTION_MOPERAND_CHECK
:
12369 if (strcasecmp (arg
, "error") == 0)
12370 operand_check
= check_error
;
12371 else if (strcasecmp (arg
, "warning") == 0)
12372 operand_check
= check_warning
;
12373 else if (strcasecmp (arg
, "none") == 0)
12374 operand_check
= check_none
;
12376 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
12379 case OPTION_MAVXSCALAR
:
12380 if (strcasecmp (arg
, "128") == 0)
12381 avxscalar
= vex128
;
12382 else if (strcasecmp (arg
, "256") == 0)
12383 avxscalar
= vex256
;
12385 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
12388 case OPTION_MVEXWIG
:
12389 if (strcmp (arg
, "0") == 0)
12391 else if (strcmp (arg
, "1") == 0)
12394 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
12397 case OPTION_MADD_BND_PREFIX
:
12398 add_bnd_prefix
= 1;
12401 case OPTION_MEVEXLIG
:
12402 if (strcmp (arg
, "128") == 0)
12403 evexlig
= evexl128
;
12404 else if (strcmp (arg
, "256") == 0)
12405 evexlig
= evexl256
;
12406 else if (strcmp (arg
, "512") == 0)
12407 evexlig
= evexl512
;
12409 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
12412 case OPTION_MEVEXRCIG
:
12413 if (strcmp (arg
, "rne") == 0)
12415 else if (strcmp (arg
, "rd") == 0)
12417 else if (strcmp (arg
, "ru") == 0)
12419 else if (strcmp (arg
, "rz") == 0)
12422 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
12425 case OPTION_MEVEXWIG
:
12426 if (strcmp (arg
, "0") == 0)
12428 else if (strcmp (arg
, "1") == 0)
12431 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
12434 # if defined (TE_PE) || defined (TE_PEP)
12435 case OPTION_MBIG_OBJ
:
12440 case OPTION_MOMIT_LOCK_PREFIX
:
12441 if (strcasecmp (arg
, "yes") == 0)
12442 omit_lock_prefix
= 1;
12443 else if (strcasecmp (arg
, "no") == 0)
12444 omit_lock_prefix
= 0;
12446 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
12449 case OPTION_MFENCE_AS_LOCK_ADD
:
12450 if (strcasecmp (arg
, "yes") == 0)
12452 else if (strcasecmp (arg
, "no") == 0)
12455 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
12458 case OPTION_MRELAX_RELOCATIONS
:
12459 if (strcasecmp (arg
, "yes") == 0)
12460 generate_relax_relocations
= 1;
12461 else if (strcasecmp (arg
, "no") == 0)
12462 generate_relax_relocations
= 0;
12464 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
12467 case OPTION_MALIGN_BRANCH_BOUNDARY
:
12470 long int align
= strtoul (arg
, &end
, 0);
12475 align_branch_power
= 0;
12478 else if (align
>= 16)
12481 for (align_power
= 0;
12483 align
>>= 1, align_power
++)
12485 /* Limit alignment power to 31. */
12486 if (align
== 1 && align_power
< 32)
12488 align_branch_power
= align_power
;
12493 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
12497 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
12500 int align
= strtoul (arg
, &end
, 0);
12501 /* Some processors only support 5 prefixes. */
12502 if (*end
== '\0' && align
>= 0 && align
< 6)
12504 align_branch_prefix_size
= align
;
12507 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
12512 case OPTION_MALIGN_BRANCH
:
12514 saved
= xstrdup (arg
);
12518 next
= strchr (type
, '+');
12521 if (strcasecmp (type
, "jcc") == 0)
12522 align_branch
|= align_branch_jcc_bit
;
12523 else if (strcasecmp (type
, "fused") == 0)
12524 align_branch
|= align_branch_fused_bit
;
12525 else if (strcasecmp (type
, "jmp") == 0)
12526 align_branch
|= align_branch_jmp_bit
;
12527 else if (strcasecmp (type
, "call") == 0)
12528 align_branch
|= align_branch_call_bit
;
12529 else if (strcasecmp (type
, "ret") == 0)
12530 align_branch
|= align_branch_ret_bit
;
12531 else if (strcasecmp (type
, "indirect") == 0)
12532 align_branch
|= align_branch_indirect_bit
;
12534 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
12537 while (next
!= NULL
);
12541 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
12542 align_branch_power
= 5;
12543 align_branch_prefix_size
= 5;
12544 align_branch
= (align_branch_jcc_bit
12545 | align_branch_fused_bit
12546 | align_branch_jmp_bit
);
12549 case OPTION_MAMD64
:
12553 case OPTION_MINTEL64
:
12561 /* Turn off -Os. */
12562 optimize_for_space
= 0;
12564 else if (*arg
== 's')
12566 optimize_for_space
= 1;
12567 /* Turn on all encoding optimizations. */
12568 optimize
= INT_MAX
;
12572 optimize
= atoi (arg
);
12573 /* Turn off -Os. */
12574 optimize_for_space
= 0;
12584 #define MESSAGE_TEMPLATE \
12588 output_message (FILE *stream
, char *p
, char *message
, char *start
,
12589 int *left_p
, const char *name
, int len
)
12591 int size
= sizeof (MESSAGE_TEMPLATE
);
12592 int left
= *left_p
;
12594 /* Reserve 2 spaces for ", " or ",\0" */
12597 /* Check if there is any room. */
12605 p
= mempcpy (p
, name
, len
);
12609 /* Output the current message now and start a new one. */
12612 fprintf (stream
, "%s\n", message
);
12614 left
= size
- (start
- message
) - len
- 2;
12616 gas_assert (left
>= 0);
12618 p
= mempcpy (p
, name
, len
);
12626 show_arch (FILE *stream
, int ext
, int check
)
12628 static char message
[] = MESSAGE_TEMPLATE
;
12629 char *start
= message
+ 27;
12631 int size
= sizeof (MESSAGE_TEMPLATE
);
12638 left
= size
- (start
- message
);
12639 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12641 /* Should it be skipped? */
12642 if (cpu_arch
[j
].skip
)
12645 name
= cpu_arch
[j
].name
;
12646 len
= cpu_arch
[j
].len
;
12649 /* It is an extension. Skip if we aren't asked to show it. */
12660 /* It is an processor. Skip if we show only extension. */
12663 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12665 /* It is an impossible processor - skip. */
12669 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
12672 /* Display disabled extensions. */
12674 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12676 name
= cpu_noarch
[j
].name
;
12677 len
= cpu_noarch
[j
].len
;
12678 p
= output_message (stream
, p
, message
, start
, &left
, name
,
12683 fprintf (stream
, "%s\n", message
);
12687 md_show_usage (FILE *stream
)
12689 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12690 fprintf (stream
, _("\
12691 -Qy, -Qn ignored\n\
12692 -V print assembler version number\n\
12695 fprintf (stream
, _("\
12696 -n Do not optimize code alignment\n\
12697 -q quieten some warnings\n"));
12698 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12699 fprintf (stream
, _("\
12702 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12703 || defined (TE_PE) || defined (TE_PEP))
12704 fprintf (stream
, _("\
12705 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
12707 #ifdef SVR4_COMMENT_CHARS
12708 fprintf (stream
, _("\
12709 --divide do not treat `/' as a comment character\n"));
12711 fprintf (stream
, _("\
12712 --divide ignored\n"));
12714 fprintf (stream
, _("\
12715 -march=CPU[,+EXTENSION...]\n\
12716 generate code for CPU and EXTENSION, CPU is one of:\n"));
12717 show_arch (stream
, 0, 1);
12718 fprintf (stream
, _("\
12719 EXTENSION is combination of:\n"));
12720 show_arch (stream
, 1, 0);
12721 fprintf (stream
, _("\
12722 -mtune=CPU optimize for CPU, CPU is one of:\n"));
12723 show_arch (stream
, 0, 0);
12724 fprintf (stream
, _("\
12725 -msse2avx encode SSE instructions with VEX prefix\n"));
12726 fprintf (stream
, _("\
12727 -msse-check=[none|error|warning] (default: warning)\n\
12728 check SSE instructions\n"));
12729 fprintf (stream
, _("\
12730 -moperand-check=[none|error|warning] (default: warning)\n\
12731 check operand combinations for validity\n"));
12732 fprintf (stream
, _("\
12733 -mavxscalar=[128|256] (default: 128)\n\
12734 encode scalar AVX instructions with specific vector\n\
12736 fprintf (stream
, _("\
12737 -mvexwig=[0|1] (default: 0)\n\
12738 encode VEX instructions with specific VEX.W value\n\
12739 for VEX.W bit ignored instructions\n"));
12740 fprintf (stream
, _("\
12741 -mevexlig=[128|256|512] (default: 128)\n\
12742 encode scalar EVEX instructions with specific vector\n\
12744 fprintf (stream
, _("\
12745 -mevexwig=[0|1] (default: 0)\n\
12746 encode EVEX instructions with specific EVEX.W value\n\
12747 for EVEX.W bit ignored instructions\n"));
12748 fprintf (stream
, _("\
12749 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
12750 encode EVEX instructions with specific EVEX.RC value\n\
12751 for SAE-only ignored instructions\n"));
12752 fprintf (stream
, _("\
12753 -mmnemonic=[att|intel] "));
12754 if (SYSV386_COMPAT
)
12755 fprintf (stream
, _("(default: att)\n"));
12757 fprintf (stream
, _("(default: intel)\n"));
12758 fprintf (stream
, _("\
12759 use AT&T/Intel mnemonic\n"));
12760 fprintf (stream
, _("\
12761 -msyntax=[att|intel] (default: att)\n\
12762 use AT&T/Intel syntax\n"));
12763 fprintf (stream
, _("\
12764 -mindex-reg support pseudo index registers\n"));
12765 fprintf (stream
, _("\
12766 -mnaked-reg don't require `%%' prefix for registers\n"));
12767 fprintf (stream
, _("\
12768 -madd-bnd-prefix add BND prefix for all valid branches\n"));
12769 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12770 fprintf (stream
, _("\
12771 -mshared disable branch optimization for shared code\n"));
12772 fprintf (stream
, _("\
12773 -mx86-used-note=[no|yes] "));
12774 if (DEFAULT_X86_USED_NOTE
)
12775 fprintf (stream
, _("(default: yes)\n"));
12777 fprintf (stream
, _("(default: no)\n"));
12778 fprintf (stream
, _("\
12779 generate x86 used ISA and feature properties\n"));
12781 #if defined (TE_PE) || defined (TE_PEP)
12782 fprintf (stream
, _("\
12783 -mbig-obj generate big object files\n"));
12785 fprintf (stream
, _("\
12786 -momit-lock-prefix=[no|yes] (default: no)\n\
12787 strip all lock prefixes\n"));
12788 fprintf (stream
, _("\
12789 -mfence-as-lock-add=[no|yes] (default: no)\n\
12790 encode lfence, mfence and sfence as\n\
12791 lock addl $0x0, (%%{re}sp)\n"));
12792 fprintf (stream
, _("\
12793 -mrelax-relocations=[no|yes] "));
12794 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
12795 fprintf (stream
, _("(default: yes)\n"));
12797 fprintf (stream
, _("(default: no)\n"));
12798 fprintf (stream
, _("\
12799 generate relax relocations\n"));
12800 fprintf (stream
, _("\
12801 -malign-branch-boundary=NUM (default: 0)\n\
12802 align branches within NUM byte boundary\n"));
12803 fprintf (stream
, _("\
12804 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
12805 TYPE is combination of jcc, fused, jmp, call, ret,\n\
12807 specify types of branches to align\n"));
12808 fprintf (stream
, _("\
12809 -malign-branch-prefix-size=NUM (default: 5)\n\
12810 align branches with NUM prefixes per instruction\n"));
12811 fprintf (stream
, _("\
12812 -mbranches-within-32B-boundaries\n\
12813 align branches within 32 byte boundary\n"));
12814 fprintf (stream
, _("\
12815 -mamd64 accept only AMD64 ISA [default]\n"));
12816 fprintf (stream
, _("\
12817 -mintel64 accept only Intel64 ISA\n"));
12820 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
12821 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12822 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12824 /* Pick the target format to use. */
12827 i386_target_format (void)
12829 if (!strncmp (default_arch
, "x86_64", 6))
12831 update_code_flag (CODE_64BIT
, 1);
12832 if (default_arch
[6] == '\0')
12833 x86_elf_abi
= X86_64_ABI
;
12835 x86_elf_abi
= X86_64_X32_ABI
;
12837 else if (!strcmp (default_arch
, "i386"))
12838 update_code_flag (CODE_32BIT
, 1);
12839 else if (!strcmp (default_arch
, "iamcu"))
12841 update_code_flag (CODE_32BIT
, 1);
12842 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
12844 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
12845 cpu_arch_name
= "iamcu";
12846 cpu_sub_arch_name
= NULL
;
12847 cpu_arch_flags
= iamcu_flags
;
12848 cpu_arch_isa
= PROCESSOR_IAMCU
;
12849 cpu_arch_isa_flags
= iamcu_flags
;
12850 if (!cpu_arch_tune_set
)
12852 cpu_arch_tune
= cpu_arch_isa
;
12853 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12856 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
12857 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
12861 as_fatal (_("unknown architecture"));
12863 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
12864 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
12865 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
12866 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
12868 switch (OUTPUT_FLAVOR
)
12870 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
12871 case bfd_target_aout_flavour
:
12872 return AOUT_TARGET_FORMAT
;
12874 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
12875 # if defined (TE_PE) || defined (TE_PEP)
12876 case bfd_target_coff_flavour
:
12877 if (flag_code
== CODE_64BIT
)
12878 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
12881 # elif defined (TE_GO32)
12882 case bfd_target_coff_flavour
:
12883 return "coff-go32";
12885 case bfd_target_coff_flavour
:
12886 return "coff-i386";
12889 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12890 case bfd_target_elf_flavour
:
12892 const char *format
;
12894 switch (x86_elf_abi
)
12897 format
= ELF_TARGET_FORMAT
;
12899 tls_get_addr
= "___tls_get_addr";
12903 use_rela_relocations
= 1;
12906 tls_get_addr
= "__tls_get_addr";
12908 format
= ELF_TARGET_FORMAT64
;
12910 case X86_64_X32_ABI
:
12911 use_rela_relocations
= 1;
12914 tls_get_addr
= "__tls_get_addr";
12916 disallow_64bit_reloc
= 1;
12917 format
= ELF_TARGET_FORMAT32
;
12920 if (cpu_arch_isa
== PROCESSOR_L1OM
)
12922 if (x86_elf_abi
!= X86_64_ABI
)
12923 as_fatal (_("Intel L1OM is 64bit only"));
12924 return ELF_TARGET_L1OM_FORMAT
;
12926 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
12928 if (x86_elf_abi
!= X86_64_ABI
)
12929 as_fatal (_("Intel K1OM is 64bit only"));
12930 return ELF_TARGET_K1OM_FORMAT
;
12932 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
12934 if (x86_elf_abi
!= I386_ABI
)
12935 as_fatal (_("Intel MCU is 32bit only"));
12936 return ELF_TARGET_IAMCU_FORMAT
;
12942 #if defined (OBJ_MACH_O)
12943 case bfd_target_mach_o_flavour
:
12944 if (flag_code
== CODE_64BIT
)
12946 use_rela_relocations
= 1;
12948 return "mach-o-x86-64";
12951 return "mach-o-i386";
12959 #endif /* OBJ_MAYBE_ more than one */
12962 md_undefined_symbol (char *name
)
12964 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
12965 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
12966 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
12967 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
12971 if (symbol_find (name
))
12972 as_bad (_("GOT already in symbol table"));
12973 GOT_symbol
= symbol_new (name
, undefined_section
,
12974 (valueT
) 0, &zero_address_frag
);
12981 /* Round up a section size to the appropriate boundary. */
12984 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
12986 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12987 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
12989 /* For a.out, force the section size to be aligned. If we don't do
12990 this, BFD will align it for us, but it will not write out the
12991 final bytes of the section. This may be a bug in BFD, but it is
12992 easier to fix it here since that is how the other a.out targets
12996 align
= bfd_section_alignment (segment
);
12997 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13004 /* On the i386, PC-relative offsets are relative to the start of the
13005 next instruction. That is, the address of the offset, plus its
13006 size, since the offset is always the last part of the insn. */
13009 md_pcrel_from (fixS
*fixP
)
13011 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13017 s_bss (int ignore ATTRIBUTE_UNUSED
)
13021 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13023 obj_elf_section_change_hook ();
13025 temp
= get_absolute_expression ();
13026 subseg_set (bss_section
, (subsegT
) temp
);
13027 demand_empty_rest_of_line ();
13032 /* Remember constant directive. */
13035 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13037 if (last_insn
.kind
!= last_insn_directive
13038 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13040 last_insn
.seg
= now_seg
;
13041 last_insn
.kind
= last_insn_directive
;
13042 last_insn
.name
= "constant directive";
13043 last_insn
.file
= as_where (&last_insn
.line
);
13048 i386_validate_fix (fixS
*fixp
)
13050 if (fixp
->fx_subsy
)
13052 if (fixp
->fx_subsy
== GOT_symbol
)
13054 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13058 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13059 if (fixp
->fx_tcbit2
)
13060 fixp
->fx_r_type
= (fixp
->fx_tcbit
13061 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13062 : BFD_RELOC_X86_64_GOTPCRELX
);
13065 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13070 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13072 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13074 fixp
->fx_subsy
= 0;
13077 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13078 else if (!object_64bit
)
13080 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13081 && fixp
->fx_tcbit2
)
13082 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
13088 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13091 bfd_reloc_code_real_type code
;
13093 switch (fixp
->fx_r_type
)
13095 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13096 case BFD_RELOC_SIZE32
:
13097 case BFD_RELOC_SIZE64
:
13098 if (S_IS_DEFINED (fixp
->fx_addsy
)
13099 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
13101 /* Resolve size relocation against local symbol to size of
13102 the symbol plus addend. */
13103 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
13104 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
13105 && !fits_in_unsigned_long (value
))
13106 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13107 _("symbol size computation overflow"));
13108 fixp
->fx_addsy
= NULL
;
13109 fixp
->fx_subsy
= NULL
;
13110 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
13114 /* Fall through. */
13116 case BFD_RELOC_X86_64_PLT32
:
13117 case BFD_RELOC_X86_64_GOT32
:
13118 case BFD_RELOC_X86_64_GOTPCREL
:
13119 case BFD_RELOC_X86_64_GOTPCRELX
:
13120 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13121 case BFD_RELOC_386_PLT32
:
13122 case BFD_RELOC_386_GOT32
:
13123 case BFD_RELOC_386_GOT32X
:
13124 case BFD_RELOC_386_GOTOFF
:
13125 case BFD_RELOC_386_GOTPC
:
13126 case BFD_RELOC_386_TLS_GD
:
13127 case BFD_RELOC_386_TLS_LDM
:
13128 case BFD_RELOC_386_TLS_LDO_32
:
13129 case BFD_RELOC_386_TLS_IE_32
:
13130 case BFD_RELOC_386_TLS_IE
:
13131 case BFD_RELOC_386_TLS_GOTIE
:
13132 case BFD_RELOC_386_TLS_LE_32
:
13133 case BFD_RELOC_386_TLS_LE
:
13134 case BFD_RELOC_386_TLS_GOTDESC
:
13135 case BFD_RELOC_386_TLS_DESC_CALL
:
13136 case BFD_RELOC_X86_64_TLSGD
:
13137 case BFD_RELOC_X86_64_TLSLD
:
13138 case BFD_RELOC_X86_64_DTPOFF32
:
13139 case BFD_RELOC_X86_64_DTPOFF64
:
13140 case BFD_RELOC_X86_64_GOTTPOFF
:
13141 case BFD_RELOC_X86_64_TPOFF32
:
13142 case BFD_RELOC_X86_64_TPOFF64
:
13143 case BFD_RELOC_X86_64_GOTOFF64
:
13144 case BFD_RELOC_X86_64_GOTPC32
:
13145 case BFD_RELOC_X86_64_GOT64
:
13146 case BFD_RELOC_X86_64_GOTPCREL64
:
13147 case BFD_RELOC_X86_64_GOTPC64
:
13148 case BFD_RELOC_X86_64_GOTPLT64
:
13149 case BFD_RELOC_X86_64_PLTOFF64
:
13150 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13151 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13152 case BFD_RELOC_RVA
:
13153 case BFD_RELOC_VTABLE_ENTRY
:
13154 case BFD_RELOC_VTABLE_INHERIT
:
13156 case BFD_RELOC_32_SECREL
:
13158 code
= fixp
->fx_r_type
;
13160 case BFD_RELOC_X86_64_32S
:
13161 if (!fixp
->fx_pcrel
)
13163 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
13164 code
= fixp
->fx_r_type
;
13167 /* Fall through. */
13169 if (fixp
->fx_pcrel
)
13171 switch (fixp
->fx_size
)
13174 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13175 _("can not do %d byte pc-relative relocation"),
13177 code
= BFD_RELOC_32_PCREL
;
13179 case 1: code
= BFD_RELOC_8_PCREL
; break;
13180 case 2: code
= BFD_RELOC_16_PCREL
; break;
13181 case 4: code
= BFD_RELOC_32_PCREL
; break;
13183 case 8: code
= BFD_RELOC_64_PCREL
; break;
13189 switch (fixp
->fx_size
)
13192 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13193 _("can not do %d byte relocation"),
13195 code
= BFD_RELOC_32
;
13197 case 1: code
= BFD_RELOC_8
; break;
13198 case 2: code
= BFD_RELOC_16
; break;
13199 case 4: code
= BFD_RELOC_32
; break;
13201 case 8: code
= BFD_RELOC_64
; break;
13208 if ((code
== BFD_RELOC_32
13209 || code
== BFD_RELOC_32_PCREL
13210 || code
== BFD_RELOC_X86_64_32S
)
13212 && fixp
->fx_addsy
== GOT_symbol
)
13215 code
= BFD_RELOC_386_GOTPC
;
13217 code
= BFD_RELOC_X86_64_GOTPC32
;
13219 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
13221 && fixp
->fx_addsy
== GOT_symbol
)
13223 code
= BFD_RELOC_X86_64_GOTPC64
;
13226 rel
= XNEW (arelent
);
13227 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
13228 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13230 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13232 if (!use_rela_relocations
)
13234 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
13235 vtable entry to be used in the relocation's section offset. */
13236 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13237 rel
->address
= fixp
->fx_offset
;
13238 #if defined (OBJ_COFF) && defined (TE_PE)
13239 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
13240 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
13245 /* Use the rela in 64bit mode. */
13248 if (disallow_64bit_reloc
)
13251 case BFD_RELOC_X86_64_DTPOFF64
:
13252 case BFD_RELOC_X86_64_TPOFF64
:
13253 case BFD_RELOC_64_PCREL
:
13254 case BFD_RELOC_X86_64_GOTOFF64
:
13255 case BFD_RELOC_X86_64_GOT64
:
13256 case BFD_RELOC_X86_64_GOTPCREL64
:
13257 case BFD_RELOC_X86_64_GOTPC64
:
13258 case BFD_RELOC_X86_64_GOTPLT64
:
13259 case BFD_RELOC_X86_64_PLTOFF64
:
13260 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13261 _("cannot represent relocation type %s in x32 mode"),
13262 bfd_get_reloc_code_name (code
));
13268 if (!fixp
->fx_pcrel
)
13269 rel
->addend
= fixp
->fx_offset
;
13273 case BFD_RELOC_X86_64_PLT32
:
13274 case BFD_RELOC_X86_64_GOT32
:
13275 case BFD_RELOC_X86_64_GOTPCREL
:
13276 case BFD_RELOC_X86_64_GOTPCRELX
:
13277 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13278 case BFD_RELOC_X86_64_TLSGD
:
13279 case BFD_RELOC_X86_64_TLSLD
:
13280 case BFD_RELOC_X86_64_GOTTPOFF
:
13281 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13282 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13283 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
13286 rel
->addend
= (section
->vma
13288 + fixp
->fx_addnumber
13289 + md_pcrel_from (fixp
));
13294 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13295 if (rel
->howto
== NULL
)
13297 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13298 _("cannot represent relocation type %s"),
13299 bfd_get_reloc_code_name (code
));
13300 /* Set howto to a garbage value so that we can keep going. */
13301 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
13302 gas_assert (rel
->howto
!= NULL
);
13308 #include "tc-i386-intel.c"
13311 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
13313 int saved_naked_reg
;
13314 char saved_register_dot
;
13316 saved_naked_reg
= allow_naked_reg
;
13317 allow_naked_reg
= 1;
13318 saved_register_dot
= register_chars
['.'];
13319 register_chars
['.'] = '.';
13320 allow_pseudo_reg
= 1;
13321 expression_and_evaluate (exp
);
13322 allow_pseudo_reg
= 0;
13323 register_chars
['.'] = saved_register_dot
;
13324 allow_naked_reg
= saved_naked_reg
;
13326 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
13328 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
13330 exp
->X_op
= O_constant
;
13331 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
13332 .dw2_regnum
[flag_code
>> 1];
13335 exp
->X_op
= O_illegal
;
13340 tc_x86_frame_initial_instructions (void)
13342 static unsigned int sp_regno
[2];
13344 if (!sp_regno
[flag_code
>> 1])
13346 char *saved_input
= input_line_pointer
;
13347 char sp
[][4] = {"esp", "rsp"};
13350 input_line_pointer
= sp
[flag_code
>> 1];
13351 tc_x86_parse_to_dw2regnum (&exp
);
13352 gas_assert (exp
.X_op
== O_constant
);
13353 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
13354 input_line_pointer
= saved_input
;
13357 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
13358 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
13362 x86_dwarf2_addr_size (void)
13364 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13365 if (x86_elf_abi
== X86_64_X32_ABI
)
13368 return bfd_arch_bits_per_address (stdoutput
) / 8;
13372 i386_elf_section_type (const char *str
, size_t len
)
13374 if (flag_code
== CODE_64BIT
13375 && len
== sizeof ("unwind") - 1
13376 && strncmp (str
, "unwind", 6) == 0)
13377 return SHT_X86_64_UNWIND
;
13384 i386_solaris_fix_up_eh_frame (segT sec
)
13386 if (flag_code
== CODE_64BIT
)
13387 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
13393 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
13397 exp
.X_op
= O_secrel
;
13398 exp
.X_add_symbol
= symbol
;
13399 exp
.X_add_number
= 0;
13400 emit_expr (&exp
, size
);
13404 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13405 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
13408 x86_64_section_letter (int letter
, const char **ptr_msg
)
13410 if (flag_code
== CODE_64BIT
)
13413 return SHF_X86_64_LARGE
;
13415 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
13418 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
13423 x86_64_section_word (char *str
, size_t len
)
13425 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
13426 return SHF_X86_64_LARGE
;
13432 handle_large_common (int small ATTRIBUTE_UNUSED
)
13434 if (flag_code
!= CODE_64BIT
)
13436 s_comm_internal (0, elf_common_parse
);
13437 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
13441 static segT lbss_section
;
13442 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
13443 asection
*saved_bss_section
= bss_section
;
13445 if (lbss_section
== NULL
)
13447 flagword applicable
;
13448 segT seg
= now_seg
;
13449 subsegT subseg
= now_subseg
;
13451 /* The .lbss section is for local .largecomm symbols. */
13452 lbss_section
= subseg_new (".lbss", 0);
13453 applicable
= bfd_applicable_section_flags (stdoutput
);
13454 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
13455 seg_info (lbss_section
)->bss
= 1;
13457 subseg_set (seg
, subseg
);
13460 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
13461 bss_section
= lbss_section
;
13463 s_comm_internal (0, elf_common_parse
);
13465 elf_com_section_ptr
= saved_com_section_ptr
;
13466 bss_section
= saved_bss_section
;
13469 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */