1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better.
33 #include "opcode/i386.h"
35 #ifndef REGISTER_WARNINGS
36 #define REGISTER_WARNINGS 1
39 #ifndef INFER_ADDR_PREFIX
40 #define INFER_ADDR_PREFIX 1
43 #ifndef SCALE1_WHEN_NO_INDEX
44 /* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48 #define SCALE1_WHEN_NO_INDEX 1
54 static unsigned int mode_from_disp_size
PARAMS ((unsigned int));
55 static int fits_in_signed_byte
PARAMS ((offsetT
));
56 static int fits_in_unsigned_byte
PARAMS ((offsetT
));
57 static int fits_in_unsigned_word
PARAMS ((offsetT
));
58 static int fits_in_signed_word
PARAMS ((offsetT
));
59 static int smallest_imm_type
PARAMS ((offsetT
));
60 static offsetT offset_in_range
PARAMS ((offsetT
, int));
61 static int add_prefix
PARAMS ((unsigned int));
62 static void set_16bit_code_flag
PARAMS ((int));
63 static void set_16bit_gcc_code_flag
PARAMS((int));
64 static void set_intel_syntax
PARAMS ((int));
65 static void set_cpu_arch
PARAMS ((int));
68 static bfd_reloc_code_real_type reloc
69 PARAMS ((int, int, bfd_reloc_code_real_type
));
72 /* 'md_assemble ()' gathers together information and puts it into a
79 const reg_entry
*regs
;
84 /* TM holds the template for the insn were currently assembling. */
87 /* SUFFIX holds the instruction mnemonic suffix if given.
88 (e.g. 'l' for 'movl') */
91 /* OPERANDS gives the number of given operands. */
92 unsigned int operands
;
94 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
95 of given register, displacement, memory operands and immediate
97 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
99 /* TYPES [i] is the type (see above #defines) which tells us how to
100 use OP[i] for the corresponding operand. */
101 unsigned int types
[MAX_OPERANDS
];
103 /* Displacement expression, immediate expression, or register for each
105 union i386_op op
[MAX_OPERANDS
];
107 /* Relocation type for operand */
109 enum bfd_reloc_code_real disp_reloc
[MAX_OPERANDS
];
111 int disp_reloc
[MAX_OPERANDS
];
114 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
115 the base index byte below. */
116 const reg_entry
*base_reg
;
117 const reg_entry
*index_reg
;
118 unsigned int log2_scale_factor
;
120 /* SEG gives the seg_entries of this insn. They are zero unless
121 explicit segment overrides are given. */
122 const seg_entry
*seg
[2]; /* segments for memory operands (if given) */
124 /* PREFIX holds all the given prefix opcodes (usually null).
125 PREFIXES is the number of prefix opcodes. */
126 unsigned int prefixes
;
127 unsigned char prefix
[MAX_PREFIXES
];
129 /* RM and SIB are the modrm byte and the sib byte where the
130 addressing modes of this insn are encoded. */
136 typedef struct _i386_insn i386_insn
;
138 /* List of chars besides those in app.c:symbol_chars that can start an
139 operand. Used to prevent the scrubber eating vital white-space. */
141 const char extra_symbol_chars
[] = "*%-(@";
143 const char extra_symbol_chars
[] = "*%-(";
146 /* This array holds the chars that always start a comment. If the
147 pre-processor is disabled, these aren't very useful */
148 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
149 /* Putting '/' here makes it impossible to use the divide operator.
150 However, we need it for compatibility with SVR4 systems. */
151 const char comment_chars
[] = "#/";
152 #define PREFIX_SEPARATOR '\\'
154 const char comment_chars
[] = "#";
155 #define PREFIX_SEPARATOR '/'
158 /* This array holds the chars that only start a comment at the beginning of
159 a line. If the line seems to have the form '# 123 filename'
160 .line and .file directives will appear in the pre-processed output */
161 /* Note that input_file.c hand checks for '#' at the beginning of the
162 first line of the input file. This is because the compiler outputs
163 #NO_APP at the beginning of its output. */
164 /* Also note that comments started like this one will always work if
165 '/' isn't otherwise defined. */
166 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
167 const char line_comment_chars
[] = "";
169 const char line_comment_chars
[] = "/";
172 const char line_separator_chars
[] = ";";
174 /* Chars that can be used to separate mant from exp in floating point nums */
175 const char EXP_CHARS
[] = "eE";
177 /* Chars that mean this number is a floating point constant */
180 const char FLT_CHARS
[] = "fFdDxX";
182 /* tables for lexical analysis */
183 static char mnemonic_chars
[256];
184 static char register_chars
[256];
185 static char operand_chars
[256];
186 static char identifier_chars
[256];
187 static char digit_chars
[256];
190 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
191 #define is_operand_char(x) (operand_chars[(unsigned char) x])
192 #define is_register_char(x) (register_chars[(unsigned char) x])
193 #define is_space_char(x) ((x) == ' ')
194 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
195 #define is_digit_char(x) (digit_chars[(unsigned char) x])
197 /* put here all non-digit non-letter charcters that may occur in an operand */
198 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
200 /* md_assemble() always leaves the strings it's passed unaltered. To
201 effect this we maintain a stack of saved characters that we've smashed
202 with '\0's (indicating end of strings for various sub-fields of the
203 assembler instruction). */
204 static char save_stack
[32];
205 static char *save_stack_p
; /* stack pointer */
206 #define END_STRING_AND_SAVE(s) \
207 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
208 #define RESTORE_END_STRING(s) \
209 do { *(s) = *--save_stack_p; } while (0)
211 /* The instruction we're assembling. */
214 /* Possible templates for current insn. */
215 static const templates
*current_templates
;
217 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
218 static expressionS disp_expressions
[2], im_expressions
[2];
220 static int this_operand
; /* Current operand we are working on. */
222 static int flag_16bit_code
; /* 1 if we're writing 16-bit code,
225 static int intel_syntax
= 0; /* 1 for intel syntax, 0 if att syntax. */
227 static int allow_naked_reg
= 0; /* 1 if register prefix % not required */
229 static char stackop_size
= '\0'; /* Used in 16 bit gcc mode to add an l
230 suffix to call, ret, enter, leave, push,
231 and pop instructions so that gcc has the
232 same stack frame as in 32 bit mode. */
234 static int quiet_warnings
= 0; /* Non-zero to quieten some warnings. */
236 static const char *cpu_arch_name
= NULL
; /* cpu name */
238 static unsigned int cpu_arch_flags
= 0; /* cpu feature flags */
240 /* Interface to relax_segment.
241 There are 2 relax states for 386 jump insns: one for conditional &
242 one for unconditional jumps. This is because these two types of
243 jumps add different sizes to frags when we're figuring out what
244 sort of jump to choose to reach a given label. */
247 #define COND_JUMP 1 /* conditional jump */
248 #define UNCOND_JUMP 2 /* unconditional jump */
252 #define SMALL16 (SMALL|CODE16)
254 #define BIG16 (BIG|CODE16)
258 #define INLINE __inline__
264 #define ENCODE_RELAX_STATE(type,size) \
265 ((relax_substateT)((type<<2) | (size)))
266 #define SIZE_FROM_RELAX_STATE(s) \
267 ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) )
269 /* This table is used by relax_frag to promote short jumps to long
270 ones where necessary. SMALL (short) jumps may be promoted to BIG
271 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
272 don't allow a short jump in a 32 bit code segment to be promoted to
273 a 16 bit offset jump because it's slower (requires data size
274 prefix), and doesn't work, unless the destination is in the bottom
275 64k of the code segment (The top 16 bits of eip are zeroed). */
277 const relax_typeS md_relax_table
[] =
280 1) most positive reach of this state,
281 2) most negative reach of this state,
282 3) how many bytes this mode will add to the size of the current frag
283 4) which index into the table to try if we can't fit into this one.
290 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
291 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
292 /* dword conditionals adds 4 bytes to frag:
293 1 extra opcode byte, 3 extra displacement bytes. */
295 /* word conditionals add 2 bytes to frag:
296 1 extra opcode byte, 1 extra displacement byte. */
299 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
300 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
301 /* dword jmp adds 3 bytes to frag:
302 0 extra opcode bytes, 3 extra displacement bytes. */
304 /* word jmp adds 1 byte to frag:
305 0 extra opcode bytes, 1 extra displacement byte. */
310 static const arch_entry cpu_arch
[] = {
312 {"i186", Cpu086
|Cpu186
},
313 {"i286", Cpu086
|Cpu186
|Cpu286
},
314 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
315 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
316 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
317 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
318 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
319 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
320 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
|Cpu3dnow
},
321 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|Cpu3dnow
},
327 i386_align_code (fragP
, count
)
331 /* Various efficient no-op patterns for aligning code labels. */
332 /* Note: Don't try to assemble the instructions in the comments. */
333 /* 0L and 0w are not legal */
334 static const char f32_1
[] =
336 static const char f32_2
[] =
337 {0x89,0xf6}; /* movl %esi,%esi */
338 static const char f32_3
[] =
339 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
340 static const char f32_4
[] =
341 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
342 static const char f32_5
[] =
344 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
345 static const char f32_6
[] =
346 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
347 static const char f32_7
[] =
348 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
349 static const char f32_8
[] =
351 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
352 static const char f32_9
[] =
353 {0x89,0xf6, /* movl %esi,%esi */
354 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
355 static const char f32_10
[] =
356 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
357 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
358 static const char f32_11
[] =
359 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
360 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
361 static const char f32_12
[] =
362 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
363 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
364 static const char f32_13
[] =
365 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
366 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
367 static const char f32_14
[] =
368 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
369 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
370 static const char f32_15
[] =
371 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
372 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
373 static const char f16_3
[] =
374 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
375 static const char f16_4
[] =
376 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
377 static const char f16_5
[] =
379 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
380 static const char f16_6
[] =
381 {0x89,0xf6, /* mov %si,%si */
382 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
383 static const char f16_7
[] =
384 {0x8d,0x74,0x00, /* lea 0(%si),%si */
385 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
386 static const char f16_8
[] =
387 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
388 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
389 static const char *const f32_patt
[] = {
390 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
391 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
393 static const char *const f16_patt
[] = {
394 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
395 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
398 if (count
> 0 && count
<= 15)
402 memcpy(fragP
->fr_literal
+ fragP
->fr_fix
,
403 f16_patt
[count
- 1], count
);
404 if (count
> 8) /* adjust jump offset */
405 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
408 memcpy(fragP
->fr_literal
+ fragP
->fr_fix
,
409 f32_patt
[count
- 1], count
);
410 fragP
->fr_var
= count
;
414 static char *output_invalid
PARAMS ((int c
));
415 static int i386_operand
PARAMS ((char *operand_string
));
416 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
417 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
421 static void s_bss
PARAMS ((int));
424 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
426 static INLINE
unsigned int
427 mode_from_disp_size (t
)
430 return (t
& Disp8
) ? 1 : (t
& (Disp16
|Disp32
)) ? 2 : 0;
434 fits_in_signed_byte (num
)
437 return (num
>= -128) && (num
<= 127);
438 } /* fits_in_signed_byte() */
441 fits_in_unsigned_byte (num
)
444 return (num
& 0xff) == num
;
445 } /* fits_in_unsigned_byte() */
448 fits_in_unsigned_word (num
)
451 return (num
& 0xffff) == num
;
452 } /* fits_in_unsigned_word() */
455 fits_in_signed_word (num
)
458 return (-32768 <= num
) && (num
<= 32767);
459 } /* fits_in_signed_word() */
462 smallest_imm_type (num
)
465 if (cpu_arch_flags
!= 0
466 && cpu_arch_flags
!= (Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
))
468 /* This code is disabled on the 486 because all the Imm1 forms
469 in the opcode table are slower on the i486. They're the
470 versions with the implicitly specified single-position
471 displacement, which has another syntax if you really want to
474 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
;
476 return (fits_in_signed_byte (num
)
477 ? (Imm8S
| Imm8
| Imm16
| Imm32
)
478 : fits_in_unsigned_byte (num
)
479 ? (Imm8
| Imm16
| Imm32
)
480 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
483 } /* smallest_imm_type() */
486 offset_in_range (val
, size
)
494 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
495 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
496 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
500 /* If BFD64, sign extend val. */
501 if ((val
& ~ (((addressT
) 2 << 31) - 1)) == 0)
502 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
504 if ((val
& ~ mask
) != 0 && (val
& ~ mask
) != ~ mask
)
506 char buf1
[40], buf2
[40];
508 sprint_value (buf1
, val
);
509 sprint_value (buf2
, val
& mask
);
510 as_warn (_("%s shortened to %s"), buf1
, buf2
);
515 /* Returns 0 if attempting to add a prefix where one from the same
516 class already exists, 1 if non rep/repne added, 2 if rep/repne
530 case CS_PREFIX_OPCODE
:
531 case DS_PREFIX_OPCODE
:
532 case ES_PREFIX_OPCODE
:
533 case FS_PREFIX_OPCODE
:
534 case GS_PREFIX_OPCODE
:
535 case SS_PREFIX_OPCODE
:
539 case REPNE_PREFIX_OPCODE
:
540 case REPE_PREFIX_OPCODE
:
543 case LOCK_PREFIX_OPCODE
:
551 case ADDR_PREFIX_OPCODE
:
555 case DATA_PREFIX_OPCODE
:
562 as_bad (_("same type of prefix used twice"));
567 i
.prefix
[q
] = prefix
;
572 set_16bit_code_flag (new_16bit_code_flag
)
573 int new_16bit_code_flag
;
575 flag_16bit_code
= new_16bit_code_flag
;
580 set_16bit_gcc_code_flag (new_16bit_code_flag
)
581 int new_16bit_code_flag
;
583 flag_16bit_code
= new_16bit_code_flag
;
584 stackop_size
= new_16bit_code_flag
? 'l' : '\0';
588 set_intel_syntax (syntax_flag
)
591 /* Find out if register prefixing is specified. */
592 int ask_naked_reg
= 0;
595 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
597 char *string
= input_line_pointer
;
598 int e
= get_symbol_end ();
600 if (strcmp(string
, "prefix") == 0)
602 else if (strcmp(string
, "noprefix") == 0)
605 as_bad (_("bad argument to syntax directive."));
606 *input_line_pointer
= e
;
608 demand_empty_rest_of_line ();
610 intel_syntax
= syntax_flag
;
612 if (ask_naked_reg
== 0)
615 allow_naked_reg
= (intel_syntax
616 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
618 allow_naked_reg
= 0; /* conservative default */
622 allow_naked_reg
= (ask_naked_reg
< 0);
627 int dummy ATTRIBUTE_UNUSED
;
631 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
633 char *string
= input_line_pointer
;
634 int e
= get_symbol_end ();
637 for (i
= 0; cpu_arch
[i
].name
; i
++)
639 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
641 cpu_arch_name
= cpu_arch
[i
].name
;
642 cpu_arch_flags
= cpu_arch
[i
].flags
;
646 if (!cpu_arch
[i
].name
)
647 as_bad (_("no such architecture: `%s'"), string
);
649 *input_line_pointer
= e
;
652 as_bad (_("missing cpu architecture"));
654 demand_empty_rest_of_line ();
657 const pseudo_typeS md_pseudo_table
[] =
659 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
660 {"align", s_align_bytes
, 0},
662 {"align", s_align_ptwo
, 0},
664 {"arch", set_cpu_arch
, 0},
668 {"ffloat", float_cons
, 'f'},
669 {"dfloat", float_cons
, 'd'},
670 {"tfloat", float_cons
, 'x'},
672 {"noopt", s_ignore
, 0},
673 {"optim", s_ignore
, 0},
674 {"code16gcc", set_16bit_gcc_code_flag
, 1},
675 {"code16", set_16bit_code_flag
, 1},
676 {"code32", set_16bit_code_flag
, 0},
677 {"intel_syntax", set_intel_syntax
, 1},
678 {"att_syntax", set_intel_syntax
, 0},
682 /* for interface with expression () */
683 extern char *input_line_pointer
;
685 /* hash table for instruction mnemonic lookup */
686 static struct hash_control
*op_hash
;
687 /* hash table for register lookup */
688 static struct hash_control
*reg_hash
;
694 const char *hash_err
;
696 /* initialize op_hash hash table */
697 op_hash
= hash_new ();
700 register const template *optab
;
701 register templates
*core_optab
;
703 optab
= i386_optab
; /* setup for loop */
704 core_optab
= (templates
*) xmalloc (sizeof (templates
));
705 core_optab
->start
= optab
;
710 if (optab
->name
== NULL
711 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
713 /* different name --> ship out current template list;
714 add to hash table; & begin anew */
715 core_optab
->end
= optab
;
716 hash_err
= hash_insert (op_hash
,
722 as_fatal (_("Internal Error: Can't hash %s: %s"),
726 if (optab
->name
== NULL
)
728 core_optab
= (templates
*) xmalloc (sizeof (templates
));
729 core_optab
->start
= optab
;
734 /* initialize reg_hash hash table */
735 reg_hash
= hash_new ();
737 register const reg_entry
*regtab
;
739 for (regtab
= i386_regtab
;
740 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
743 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
749 /* fill in lexical tables: mnemonic_chars, operand_chars. */
754 for (c
= 0; c
< 256; c
++)
759 mnemonic_chars
[c
] = c
;
760 register_chars
[c
] = c
;
761 operand_chars
[c
] = c
;
763 else if (islower (c
))
765 mnemonic_chars
[c
] = c
;
766 register_chars
[c
] = c
;
767 operand_chars
[c
] = c
;
769 else if (isupper (c
))
771 mnemonic_chars
[c
] = tolower (c
);
772 register_chars
[c
] = mnemonic_chars
[c
];
773 operand_chars
[c
] = c
;
776 if (isalpha (c
) || isdigit (c
))
777 identifier_chars
[c
] = c
;
780 identifier_chars
[c
] = c
;
781 operand_chars
[c
] = c
;
786 identifier_chars
['@'] = '@';
788 digit_chars
['-'] = '-';
789 identifier_chars
['_'] = '_';
790 identifier_chars
['.'] = '.';
792 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
793 operand_chars
[(unsigned char) *p
] = *p
;
796 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
797 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
799 record_alignment (text_section
, 2);
800 record_alignment (data_section
, 2);
801 record_alignment (bss_section
, 2);
807 i386_print_statistics (file
)
810 hash_print_statistics (file
, "i386 opcode", op_hash
);
811 hash_print_statistics (file
, "i386 register", reg_hash
);
817 /* debugging routines for md_assemble */
818 static void pi
PARAMS ((char *, i386_insn
*));
819 static void pte
PARAMS ((template *));
820 static void pt
PARAMS ((unsigned int));
821 static void pe
PARAMS ((expressionS
*));
822 static void ps
PARAMS ((symbolS
*));
829 register template *p
;
832 fprintf (stdout
, "%s: template ", line
);
834 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x",
835 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
836 fprintf (stdout
, " base %x index %x scale %x\n",
837 x
->bi
.base
, x
->bi
.index
, x
->bi
.scale
);
838 for (i
= 0; i
< x
->operands
; i
++)
840 fprintf (stdout
, " #%d: ", i
+ 1);
842 fprintf (stdout
, "\n");
844 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
845 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
846 if (x
->types
[i
] & Imm
)
848 if (x
->types
[i
] & Disp
)
858 fprintf (stdout
, " %d operands ", t
->operands
);
859 fprintf (stdout
, "opcode %x ",
861 if (t
->extension_opcode
!= None
)
862 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
863 if (t
->opcode_modifier
& D
)
864 fprintf (stdout
, "D");
865 if (t
->opcode_modifier
& W
)
866 fprintf (stdout
, "W");
867 fprintf (stdout
, "\n");
868 for (i
= 0; i
< t
->operands
; i
++)
870 fprintf (stdout
, " #%d type ", i
+ 1);
871 pt (t
->operand_types
[i
]);
872 fprintf (stdout
, "\n");
880 fprintf (stdout
, " operation %d\n", e
->X_op
);
881 fprintf (stdout
, " add_number %ld (%lx)\n",
882 (long) e
->X_add_number
, (long) e
->X_add_number
);
885 fprintf (stdout
, " add_symbol ");
886 ps (e
->X_add_symbol
);
887 fprintf (stdout
, "\n");
891 fprintf (stdout
, " op_symbol ");
893 fprintf (stdout
, "\n");
901 fprintf (stdout
, "%s type %s%s",
903 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
904 segment_name (S_GET_SEGMENT (s
)));
923 { BaseIndex
, "BaseIndex" },
927 { InOutPortReg
, "InOutPortReg" },
928 { ShiftCount
, "ShiftCount" },
929 { Control
, "control reg" },
930 { Test
, "test reg" },
931 { Debug
, "debug reg" },
932 { FloatReg
, "FReg" },
933 { FloatAcc
, "FAcc" },
937 { JumpAbsolute
, "Jump Absolute" },
948 register struct type_name
*ty
;
952 fprintf (stdout
, _("Unknown"));
956 for (ty
= type_names
; ty
->mask
; ty
++)
958 fprintf (stdout
, "%s, ", ty
->tname
);
963 #endif /* DEBUG386 */
966 tc_i386_force_relocation (fixp
)
970 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
971 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
976 return fixp
->fx_r_type
== 7;
981 static bfd_reloc_code_real_type reloc
982 PARAMS ((int, int, bfd_reloc_code_real_type
));
984 static bfd_reloc_code_real_type
985 reloc (size
, pcrel
, other
)
988 bfd_reloc_code_real_type other
;
990 if (other
!= NO_RELOC
) return other
;
996 case 1: return BFD_RELOC_8_PCREL
;
997 case 2: return BFD_RELOC_16_PCREL
;
998 case 4: return BFD_RELOC_32_PCREL
;
1000 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1006 case 1: return BFD_RELOC_8
;
1007 case 2: return BFD_RELOC_16
;
1008 case 4: return BFD_RELOC_32
;
1010 as_bad (_("can not do %d byte relocation"), size
);
1013 return BFD_RELOC_NONE
;
1017 * Here we decide which fixups can be adjusted to make them relative to
1018 * the beginning of the section instead of the symbol. Basically we need
1019 * to make sure that the dynamic relocations are done correctly, so in
1020 * some cases we force the original symbol to be used.
1023 tc_i386_fix_adjustable (fixP
)
1026 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PE)
1027 /* Prevent all adjustments to global symbols, or else dynamic
1028 linking will not work correctly. */
1029 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1030 || S_IS_WEAK (fixP
->fx_addsy
))
1033 /* adjust_reloc_syms doesn't know about the GOT */
1034 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1035 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1036 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1037 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1038 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1043 #define reloc(SIZE,PCREL,OTHER) 0
1044 #define BFD_RELOC_16 0
1045 #define BFD_RELOC_32 0
1046 #define BFD_RELOC_16_PCREL 0
1047 #define BFD_RELOC_32_PCREL 0
1048 #define BFD_RELOC_386_PLT32 0
1049 #define BFD_RELOC_386_GOT32 0
1050 #define BFD_RELOC_386_GOTOFF 0
1054 intel_float_operand
PARAMS ((char *mnemonic
));
1057 intel_float_operand (mnemonic
)
1060 if (mnemonic
[0] == 'f' && mnemonic
[1] =='i')
1063 if (mnemonic
[0] == 'f')
1069 /* This is the guts of the machine-dependent assembler. LINE points to a
1070 machine dependent instruction. This function is supposed to emit
1071 the frags/bytes it assembles to. */
1077 /* Points to template once we've found it. */
1080 /* Count the size of the instruction generated. */
1085 char mnemonic
[MAX_MNEM_SIZE
];
1087 /* Initialize globals. */
1088 memset (&i
, '\0', sizeof (i
));
1089 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1090 i
.disp_reloc
[j
] = NO_RELOC
;
1091 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1092 memset (im_expressions
, '\0', sizeof (im_expressions
));
1093 save_stack_p
= save_stack
; /* reset stack pointer */
1095 /* First parse an instruction mnemonic & call i386_operand for the operands.
1096 We assume that the scrubber has arranged it so that line[0] is the valid
1097 start of a (possibly prefixed) mnemonic. */
1100 char *token_start
= l
;
1103 /* Non-zero if we found a prefix only acceptable with string insns. */
1104 const char *expecting_string_instruction
= NULL
;
1109 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1112 if (mnem_p
>= mnemonic
+ sizeof (mnemonic
))
1114 as_bad (_("no such instruction: `%s'"), token_start
);
1119 if (!is_space_char (*l
)
1120 && *l
!= END_OF_INSN
1121 && *l
!= PREFIX_SEPARATOR
)
1123 as_bad (_("invalid character %s in mnemonic"),
1124 output_invalid (*l
));
1127 if (token_start
== l
)
1129 if (*l
== PREFIX_SEPARATOR
)
1130 as_bad (_("expecting prefix; got nothing"));
1132 as_bad (_("expecting mnemonic; got nothing"));
1136 /* Look up instruction (or prefix) via hash table. */
1137 current_templates
= hash_find (op_hash
, mnemonic
);
1139 if (*l
!= END_OF_INSN
1140 && (! is_space_char (*l
) || l
[1] != END_OF_INSN
)
1141 && current_templates
1142 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1144 /* If we are in 16-bit mode, do not allow addr16 or data16.
1145 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1146 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1147 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1150 as_bad (_("redundant %s prefix"),
1151 current_templates
->start
->name
);
1154 /* Add prefix, checking for repeated prefixes. */
1155 switch (add_prefix (current_templates
->start
->base_opcode
))
1160 expecting_string_instruction
=
1161 current_templates
->start
->name
;
1164 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1171 if (!current_templates
)
1173 /* See if we can get a match by trimming off a suffix. */
1176 case WORD_MNEM_SUFFIX
:
1177 case BYTE_MNEM_SUFFIX
:
1178 case SHORT_MNEM_SUFFIX
:
1179 case LONG_MNEM_SUFFIX
:
1180 i
.suffix
= mnem_p
[-1];
1182 current_templates
= hash_find (op_hash
, mnemonic
);
1186 case DWORD_MNEM_SUFFIX
:
1189 i
.suffix
= mnem_p
[-1];
1191 current_templates
= hash_find (op_hash
, mnemonic
);
1195 if (!current_templates
)
1197 as_bad (_("no such instruction: `%s'"), token_start
);
1202 /* Check if instruction is supported on specified architecture. */
1203 if (cpu_arch_flags
!= 0)
1205 if (current_templates
->start
->cpu_flags
& ~ cpu_arch_flags
)
1207 as_warn (_("`%s' is not supported on `%s'"),
1208 current_templates
->start
->name
, cpu_arch_name
);
1210 else if ((Cpu386
& ~ cpu_arch_flags
) && !flag_16bit_code
)
1212 as_warn (_("use .code16 to ensure correct addressing mode"));
1216 /* check for rep/repne without a string instruction */
1217 if (expecting_string_instruction
1218 && !(current_templates
->start
->opcode_modifier
& IsString
))
1220 as_bad (_("expecting string instruction after `%s'"),
1221 expecting_string_instruction
);
1225 /* There may be operands to parse. */
1226 if (*l
!= END_OF_INSN
)
1228 /* parse operands */
1230 /* 1 if operand is pending after ','. */
1231 unsigned int expecting_operand
= 0;
1233 /* Non-zero if operand parens not balanced. */
1234 unsigned int paren_not_balanced
;
1238 /* skip optional white space before operand */
1239 if (is_space_char (*l
))
1241 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1243 as_bad (_("invalid character %s before operand %d"),
1244 output_invalid (*l
),
1248 token_start
= l
; /* after white space */
1249 paren_not_balanced
= 0;
1250 while (paren_not_balanced
|| *l
!= ',')
1252 if (*l
== END_OF_INSN
)
1254 if (paren_not_balanced
)
1257 as_bad (_("unbalanced parenthesis in operand %d."),
1260 as_bad (_("unbalanced brackets in operand %d."),
1265 break; /* we are done */
1267 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1269 as_bad (_("invalid character %s in operand %d"),
1270 output_invalid (*l
),
1277 ++paren_not_balanced
;
1279 --paren_not_balanced
;
1284 ++paren_not_balanced
;
1286 --paren_not_balanced
;
1290 if (l
!= token_start
)
1291 { /* yes, we've read in another operand */
1292 unsigned int operand_ok
;
1293 this_operand
= i
.operands
++;
1294 if (i
.operands
> MAX_OPERANDS
)
1296 as_bad (_("spurious operands; (%d operands/instruction max)"),
1300 /* now parse operand adding info to 'i' as we go along */
1301 END_STRING_AND_SAVE (l
);
1304 operand_ok
= i386_intel_operand (token_start
, intel_float_operand (mnemonic
));
1306 operand_ok
= i386_operand (token_start
);
1308 RESTORE_END_STRING (l
); /* restore old contents */
1314 if (expecting_operand
)
1316 expecting_operand_after_comma
:
1317 as_bad (_("expecting operand after ','; got nothing"));
1322 as_bad (_("expecting operand before ','; got nothing"));
1327 /* now *l must be either ',' or END_OF_INSN */
1330 if (*++l
== END_OF_INSN
)
1331 { /* just skip it, if it's \n complain */
1332 goto expecting_operand_after_comma
;
1334 expecting_operand
= 1;
1337 while (*l
!= END_OF_INSN
); /* until we get end of insn */
1341 /* Now we've parsed the mnemonic into a set of templates, and have the
1344 Next, we find a template that matches the given insn,
1345 making sure the overlap of the given operands types is consistent
1346 with the template operand types. */
1348 #define MATCH(overlap, given, template) \
1349 ((overlap & ~JumpAbsolute) \
1350 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1352 /* If given types r0 and r1 are registers they must be of the same type
1353 unless the expected operand type register overlap is null.
1354 Note that Acc in a template matches every size of reg. */
1355 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1356 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1357 ((g0) & Reg) == ((g1) & Reg) || \
1358 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1361 register unsigned int overlap0
, overlap1
;
1362 unsigned int overlap2
;
1363 unsigned int found_reverse_match
;
1366 /* All intel opcodes have reversed operands except for "bound" and
1367 "enter". We also don't reverse intersegment "jmp" and "call"
1368 instructions with 2 immediate operands so that the immediate segment
1369 precedes the offset, as it does when in AT&T mode. "enter" and the
1370 intersegment "jmp" and "call" instructions are the only ones that
1371 have two immediate operands. */
1372 if (intel_syntax
&& i
.operands
> 1
1373 && (strcmp (mnemonic
, "bound") != 0)
1374 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1376 union i386_op temp_op
;
1377 unsigned int temp_type
;
1381 if (i
.operands
== 2)
1386 else if (i
.operands
== 3)
1391 temp_type
= i
.types
[xchg2
];
1392 i
.types
[xchg2
] = i
.types
[xchg1
];
1393 i
.types
[xchg1
] = temp_type
;
1394 temp_op
= i
.op
[xchg2
];
1395 i
.op
[xchg2
] = i
.op
[xchg1
];
1396 i
.op
[xchg1
] = temp_op
;
1398 if (i
.mem_operands
== 2)
1400 const seg_entry
*temp_seg
;
1401 temp_seg
= i
.seg
[0];
1402 i
.seg
[0] = i
.seg
[1];
1403 i
.seg
[1] = temp_seg
;
1409 /* Try to ensure constant immediates are represented in the smallest
1411 char guess_suffix
= 0;
1415 guess_suffix
= i
.suffix
;
1416 else if (i
.reg_operands
)
1418 /* Figure out a suffix from the last register operand specified.
1419 We can't do this properly yet, ie. excluding InOutPortReg,
1420 but the following works for instructions with immediates.
1421 In any case, we can't set i.suffix yet. */
1422 for (op
= i
.operands
; --op
>= 0; )
1423 if (i
.types
[op
] & Reg
)
1425 if (i
.types
[op
] & Reg8
)
1426 guess_suffix
= BYTE_MNEM_SUFFIX
;
1427 else if (i
.types
[op
] & Reg16
)
1428 guess_suffix
= WORD_MNEM_SUFFIX
;
1432 else if (flag_16bit_code
^ (i
.prefix
[DATA_PREFIX
] != 0))
1433 guess_suffix
= WORD_MNEM_SUFFIX
;
1435 for (op
= i
.operands
; --op
>= 0; )
1436 if ((i
.types
[op
] & Imm
)
1437 && i
.op
[op
].imms
->X_op
== O_constant
)
1439 /* If a suffix is given, this operand may be shortened. */
1440 switch (guess_suffix
)
1442 case WORD_MNEM_SUFFIX
:
1443 i
.types
[op
] |= Imm16
;
1445 case BYTE_MNEM_SUFFIX
:
1446 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
;
1450 /* If this operand is at most 16 bits, convert it to a
1451 signed 16 bit number before trying to see whether it will
1452 fit in an even smaller size. This allows a 16-bit operand
1453 such as $0xffe0 to be recognised as within Imm8S range. */
1454 if ((i
.types
[op
] & Imm16
)
1455 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
)0xffff) == 0)
1457 i
.op
[op
].imms
->X_add_number
=
1458 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1460 i
.types
[op
] |= smallest_imm_type ((long) i
.op
[op
].imms
->X_add_number
);
1467 found_reverse_match
= 0;
1468 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1470 : (i
.suffix
== WORD_MNEM_SUFFIX
1472 : (i
.suffix
== SHORT_MNEM_SUFFIX
1474 : (i
.suffix
== LONG_MNEM_SUFFIX
1476 : (i
.suffix
== DWORD_MNEM_SUFFIX
1478 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
? No_xSuf
: 0))))));
1480 for (t
= current_templates
->start
;
1481 t
< current_templates
->end
;
1484 /* Must have right number of operands. */
1485 if (i
.operands
!= t
->operands
)
1488 /* Check the suffix, except for some instructions in intel mode. */
1489 if ((t
->opcode_modifier
& suffix_check
)
1491 && t
->base_opcode
== 0xd9
1492 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1493 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1496 else if (!t
->operands
)
1497 break; /* 0 operands always matches */
1499 overlap0
= i
.types
[0] & t
->operand_types
[0];
1500 switch (t
->operands
)
1503 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1508 overlap1
= i
.types
[1] & t
->operand_types
[1];
1509 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1510 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1511 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1512 t
->operand_types
[0],
1513 overlap1
, i
.types
[1],
1514 t
->operand_types
[1]))
1517 /* check if other direction is valid ... */
1518 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1521 /* try reversing direction of operands */
1522 overlap0
= i
.types
[0] & t
->operand_types
[1];
1523 overlap1
= i
.types
[1] & t
->operand_types
[0];
1524 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1525 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1526 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1527 t
->operand_types
[1],
1528 overlap1
, i
.types
[1],
1529 t
->operand_types
[0]))
1531 /* does not match either direction */
1534 /* found_reverse_match holds which of D or FloatDR
1536 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1539 /* found a forward 2 operand match here */
1540 if (t
->operands
== 3)
1542 /* Here we make use of the fact that there are no
1543 reverse match 3 operand instructions, and all 3
1544 operand instructions only need to be checked for
1545 register consistency between operands 2 and 3. */
1546 overlap2
= i
.types
[2] & t
->operand_types
[2];
1547 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1548 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1549 t
->operand_types
[1],
1550 overlap2
, i
.types
[2],
1551 t
->operand_types
[2]))
1555 /* found either forward/reverse 2 or 3 operand match here:
1556 slip through to break */
1558 break; /* we've found a match; break out of loop */
1559 } /* for (t = ... */
1560 if (t
== current_templates
->end
)
1561 { /* we found no match */
1562 as_bad (_("suffix or operands invalid for `%s'"),
1563 current_templates
->start
->name
);
1567 if (!quiet_warnings
)
1570 && ((i
.types
[0] & JumpAbsolute
)
1571 != (t
->operand_types
[0] & JumpAbsolute
)))
1573 as_warn (_("indirect %s without `*'"), t
->name
);
1576 if ((t
->opcode_modifier
& (IsPrefix
|IgnoreSize
))
1577 == (IsPrefix
|IgnoreSize
))
1579 /* Warn them that a data or address size prefix doesn't
1580 affect assembly of the next line of code. */
1581 as_warn (_("stand-alone `%s' prefix"), t
->name
);
1585 /* Copy the template we found. */
1587 if (found_reverse_match
)
1589 /* If we found a reverse match we must alter the opcode
1590 direction bit. found_reverse_match holds bits to change
1591 (different for int & float insns). */
1593 i
.tm
.base_opcode
^= found_reverse_match
;
1595 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1596 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1599 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1602 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1603 i
.tm
.base_opcode
^= FloatR
;
1605 if (i
.tm
.opcode_modifier
& FWait
)
1606 if (! add_prefix (FWAIT_OPCODE
))
1609 /* Check string instruction segment overrides */
1610 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1612 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1613 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1615 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1617 as_bad (_("`%s' operand %d must use `%%es' segment"),
1622 /* There's only ever one segment override allowed per instruction.
1623 This instruction possibly has a legal segment override on the
1624 second operand, so copy the segment to where non-string
1625 instructions store it, allowing common code. */
1626 i
.seg
[0] = i
.seg
[1];
1628 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1630 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1632 as_bad (_("`%s' operand %d must use `%%es' segment"),
1640 /* If matched instruction specifies an explicit instruction mnemonic
1642 if (i
.tm
.opcode_modifier
& (Size16
| Size32
))
1644 if (i
.tm
.opcode_modifier
& Size16
)
1645 i
.suffix
= WORD_MNEM_SUFFIX
;
1647 i
.suffix
= LONG_MNEM_SUFFIX
;
1649 else if (i
.reg_operands
)
1651 /* If there's no instruction mnemonic suffix we try to invent one
1652 based on register operands. */
1655 /* We take i.suffix from the last register operand specified,
1656 Destination register type is more significant than source
1659 for (op
= i
.operands
; --op
>= 0; )
1660 if ((i
.types
[op
] & Reg
)
1661 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
1663 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
1664 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
1669 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
1672 for (op
= i
.operands
; --op
>= 0; )
1674 /* If this is an eight bit register, it's OK. If it's
1675 the 16 or 32 bit version of an eight bit register,
1676 we will just use the low portion, and that's OK too. */
1677 if (i
.types
[op
] & Reg8
)
1680 /* movzx and movsx should not generate this warning. */
1682 && (i
.tm
.base_opcode
== 0xfb7
1683 || i
.tm
.base_opcode
== 0xfb6
1684 || i
.tm
.base_opcode
== 0xfbe
1685 || i
.tm
.base_opcode
== 0xfbf))
1688 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
1690 /* Check that the template allows eight bit regs
1691 This kills insns such as `orb $1,%edx', which
1692 maybe should be allowed. */
1693 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
1697 #if REGISTER_WARNINGS
1699 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1700 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1701 (i
.op
[op
].regs
- (i
.types
[op
] & Reg16
? 8 : 16))->reg_name
,
1702 i
.op
[op
].regs
->reg_name
,
1707 /* Any other register is bad */
1708 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
1710 | Control
| Debug
| Test
1711 | FloatReg
| FloatAcc
))
1713 as_bad (_("`%%%s' not allowed with `%s%c'"),
1714 i
.op
[op
].regs
->reg_name
,
1721 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
1724 for (op
= i
.operands
; --op
>= 0; )
1725 /* Reject eight bit registers, except where the template
1726 requires them. (eg. movzb) */
1727 if ((i
.types
[op
] & Reg8
) != 0
1728 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
1730 as_bad (_("`%%%s' not allowed with `%s%c'"),
1731 i
.op
[op
].regs
->reg_name
,
1736 #if REGISTER_WARNINGS
1737 /* Warn if the e prefix on a general reg is missing. */
1738 else if (!quiet_warnings
1739 && (i
.types
[op
] & Reg16
) != 0
1740 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
1742 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1743 (i
.op
[op
].regs
+ 8)->reg_name
,
1744 i
.op
[op
].regs
->reg_name
,
1749 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
1752 for (op
= i
.operands
; --op
>= 0; )
1753 /* Reject eight bit registers, except where the template
1754 requires them. (eg. movzb) */
1755 if ((i
.types
[op
] & Reg8
) != 0
1756 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
1758 as_bad (_("`%%%s' not allowed with `%s%c'"),
1759 i
.op
[op
].regs
->reg_name
,
1764 #if REGISTER_WARNINGS
1765 /* Warn if the e prefix on a general reg is present. */
1766 else if (!quiet_warnings
1767 && (i
.types
[op
] & Reg32
) != 0
1768 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
1770 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1771 (i
.op
[op
].regs
- 8)->reg_name
,
1772 i
.op
[op
].regs
->reg_name
,
1780 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
1782 i
.suffix
= stackop_size
;
1785 /* Make still unresolved immediate matches conform to size of immediate
1786 given in i.suffix. Note: overlap2 cannot be an immediate! */
1787 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
))
1788 && overlap0
!= Imm8
&& overlap0
!= Imm8S
1789 && overlap0
!= Imm16
&& overlap0
!= Imm32
)
1793 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
1794 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
: Imm32
));
1796 else if (overlap0
== (Imm16
| Imm32
))
1799 (flag_16bit_code
^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32
;
1803 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
1807 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32
))
1808 && overlap1
!= Imm8
&& overlap1
!= Imm8S
1809 && overlap1
!= Imm16
&& overlap1
!= Imm32
)
1813 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
1814 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
: Imm32
));
1816 else if (overlap1
== (Imm16
| Imm32
))
1819 (flag_16bit_code
^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32
;
1823 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
1827 assert ((overlap2
& Imm
) == 0);
1829 i
.types
[0] = overlap0
;
1830 if (overlap0
& ImplicitRegister
)
1832 if (overlap0
& Imm1
)
1833 i
.imm_operands
= 0; /* kludge for shift insns */
1835 i
.types
[1] = overlap1
;
1836 if (overlap1
& ImplicitRegister
)
1839 i
.types
[2] = overlap2
;
1840 if (overlap2
& ImplicitRegister
)
1843 /* Finalize opcode. First, we change the opcode based on the operand
1844 size given by i.suffix: We need not change things for byte insns. */
1846 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
1848 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
1852 /* For movzx and movsx, need to check the register type */
1854 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
1855 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
1857 unsigned int prefix
= DATA_PREFIX_OPCODE
;
1859 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
1860 if (!add_prefix (prefix
))
1864 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
1866 /* It's not a byte, select word/dword operation. */
1867 if (i
.tm
.opcode_modifier
& W
)
1869 if (i
.tm
.opcode_modifier
& ShortForm
)
1870 i
.tm
.base_opcode
|= 8;
1872 i
.tm
.base_opcode
|= 1;
1874 /* Now select between word & dword operations via the operand
1875 size prefix, except for instructions that will ignore this
1877 if (((intel_syntax
&& (i
.suffix
== DWORD_MNEM_SUFFIX
))
1878 || i
.suffix
== LONG_MNEM_SUFFIX
) == flag_16bit_code
1879 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
1881 unsigned int prefix
= DATA_PREFIX_OPCODE
;
1882 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
1883 prefix
= ADDR_PREFIX_OPCODE
;
1885 if (! add_prefix (prefix
))
1888 /* Size floating point instruction. */
1889 if (i
.suffix
== LONG_MNEM_SUFFIX
1890 || (intel_syntax
&& i
.suffix
== DWORD_MNEM_SUFFIX
))
1892 if (i
.tm
.opcode_modifier
& FloatMF
)
1893 i
.tm
.base_opcode
^= 4;
1897 if (i
.tm
.opcode_modifier
& ImmExt
)
1899 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1900 opcode suffix which is coded in the same place as an 8-bit
1901 immediate field would be. Here we fake an 8-bit immediate
1902 operand from the opcode suffix stored in tm.extension_opcode. */
1906 assert(i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1908 exp
= &im_expressions
[i
.imm_operands
++];
1909 i
.op
[i
.operands
].imms
= exp
;
1910 i
.types
[i
.operands
++] = Imm8
;
1911 exp
->X_op
= O_constant
;
1912 exp
->X_add_number
= i
.tm
.extension_opcode
;
1913 i
.tm
.extension_opcode
= None
;
1916 /* For insns with operands there are more diddles to do to the opcode. */
1919 /* Default segment register this instruction will use
1920 for memory accesses. 0 means unknown.
1921 This is only for optimizing out unnecessary segment overrides. */
1922 const seg_entry
*default_seg
= 0;
1924 /* The imul $imm, %reg instruction is converted into
1925 imul $imm, %reg, %reg, and the clr %reg instruction
1926 is converted into xor %reg, %reg. */
1927 if (i
.tm
.opcode_modifier
& regKludge
)
1929 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
1930 /* Pretend we saw the extra register operand. */
1931 assert (i
.op
[first_reg_op
+1].regs
== 0);
1932 i
.op
[first_reg_op
+1].regs
= i
.op
[first_reg_op
].regs
;
1933 i
.types
[first_reg_op
+1] = i
.types
[first_reg_op
];
1937 if (i
.tm
.opcode_modifier
& ShortForm
)
1939 /* The register or float register operand is in operand 0 or 1. */
1940 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
1941 /* Register goes in low 3 bits of opcode. */
1942 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
1943 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1945 /* Warn about some common errors, but press on regardless.
1946 The first case can be generated by gcc (<= 2.8.1). */
1947 if (i
.operands
== 2)
1949 /* reversed arguments on faddp, fsubp, etc. */
1950 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
1951 i
.op
[1].regs
->reg_name
,
1952 i
.op
[0].regs
->reg_name
);
1956 /* extraneous `l' suffix on fp insn */
1957 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
1958 i
.op
[0].regs
->reg_name
);
1962 else if (i
.tm
.opcode_modifier
& Modrm
)
1964 /* The opcode is completed (modulo i.tm.extension_opcode which
1965 must be put into the modrm byte).
1966 Now, we make the modrm & index base bytes based on all the
1967 info we've collected. */
1969 /* i.reg_operands MUST be the number of real register operands;
1970 implicit registers do not count. */
1971 if (i
.reg_operands
== 2)
1973 unsigned int source
, dest
;
1974 source
= ((i
.types
[0]
1975 & (Reg
| RegMMX
| RegXMM
1977 | Control
| Debug
| Test
))
1982 /* One of the register operands will be encoded in the
1983 i.tm.reg field, the other in the combined i.tm.mode
1984 and i.tm.regmem fields. If no form of this
1985 instruction supports a memory destination operand,
1986 then we assume the source operand may sometimes be
1987 a memory operand and so we need to store the
1988 destination in the i.rm.reg field. */
1989 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
1991 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
1992 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
1996 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
1997 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2001 { /* if it's not 2 reg operands... */
2004 unsigned int fake_zero_displacement
= 0;
2005 unsigned int op
= ((i
.types
[0] & AnyMem
)
2007 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2014 if (! i
.disp_operands
)
2015 fake_zero_displacement
= 1;
2018 /* Operand is just <disp> */
2019 if (flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0))
2021 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2022 i
.types
[op
] &= ~Disp
;
2023 i
.types
[op
] |= Disp16
;
2027 i
.rm
.regmem
= NO_BASE_REGISTER
;
2028 i
.types
[op
] &= ~Disp
;
2029 i
.types
[op
] |= Disp32
;
2032 else /* ! i.base_reg && i.index_reg */
2034 i
.sib
.index
= i
.index_reg
->reg_num
;
2035 i
.sib
.base
= NO_BASE_REGISTER
;
2036 i
.sib
.scale
= i
.log2_scale_factor
;
2037 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2038 i
.types
[op
] &= ~Disp
;
2039 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2042 else if (i
.base_reg
->reg_type
& Reg16
)
2044 switch (i
.base_reg
->reg_num
)
2049 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2050 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2057 if ((i
.types
[op
] & Disp
) == 0)
2059 /* fake (%bp) into 0(%bp) */
2060 i
.types
[op
] |= Disp8
;
2061 fake_zero_displacement
= 1;
2064 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2065 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2067 default: /* (%si) -> 4 or (%di) -> 5 */
2068 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2070 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2072 else /* i.base_reg and 32 bit mode */
2074 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2075 i
.sib
.base
= i
.base_reg
->reg_num
;
2076 if (i
.base_reg
->reg_num
== EBP_REG_NUM
)
2079 if (i
.disp_operands
== 0)
2081 fake_zero_displacement
= 1;
2082 i
.types
[op
] |= Disp8
;
2085 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2089 i
.sib
.scale
= i
.log2_scale_factor
;
2092 /* <disp>(%esp) becomes two byte modrm
2093 with no index register. We've already
2094 stored the code for esp in i.rm.regmem
2095 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2096 base register besides %esp will not use
2097 the extra modrm byte. */
2098 i
.sib
.index
= NO_INDEX_REGISTER
;
2099 #if ! SCALE1_WHEN_NO_INDEX
2100 /* Another case where we force the second
2102 if (i
.log2_scale_factor
)
2103 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2108 i
.sib
.index
= i
.index_reg
->reg_num
;
2109 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2111 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2114 if (fake_zero_displacement
)
2116 /* Fakes a zero displacement assuming that i.types[op]
2117 holds the correct displacement size. */
2120 assert (i
.op
[op
].disps
== 0);
2121 exp
= &disp_expressions
[i
.disp_operands
++];
2122 i
.op
[op
].disps
= exp
;
2123 exp
->X_op
= O_constant
;
2124 exp
->X_add_number
= 0;
2125 exp
->X_add_symbol
= (symbolS
*) 0;
2126 exp
->X_op_symbol
= (symbolS
*) 0;
2130 /* Fill in i.rm.reg or i.rm.regmem field with register
2131 operand (if any) based on i.tm.extension_opcode.
2132 Again, we must be careful to make sure that
2133 segment/control/debug/test/MMX registers are coded
2134 into the i.rm.reg field. */
2139 & (Reg
| RegMMX
| RegXMM
2141 | Control
| Debug
| Test
))
2144 & (Reg
| RegMMX
| RegXMM
2146 | Control
| Debug
| Test
))
2149 /* If there is an extension opcode to put here, the
2150 register number must be put into the regmem field. */
2151 if (i
.tm
.extension_opcode
!= None
)
2152 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2154 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2156 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2157 we must set it to 3 to indicate this is a register
2158 operand in the regmem field. */
2159 if (!i
.mem_operands
)
2163 /* Fill in i.rm.reg field with extension opcode (if any). */
2164 if (i
.tm
.extension_opcode
!= None
)
2165 i
.rm
.reg
= i
.tm
.extension_opcode
;
2168 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2170 if (i
.tm
.base_opcode
== POP_SEG_SHORT
&& i
.op
[0].regs
->reg_num
== 1)
2172 as_bad (_("you can't `pop %%cs'"));
2175 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2177 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
2181 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2183 /* For the string instructions that allow a segment override
2184 on one of their operands, the default segment is ds. */
2188 /* If a segment was explicitly specified,
2189 and the specified segment is not the default,
2190 use an opcode prefix to select it.
2191 If we never figured out what the default segment is,
2192 then default_seg will be zero at this point,
2193 and the specified segment prefix will always be used. */
2194 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2196 if (! add_prefix (i
.seg
[0]->seg_prefix
))
2200 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2202 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2203 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2207 /* Handle conversion of 'int $3' --> special int3 insn. */
2208 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2210 i
.tm
.base_opcode
= INT3_OPCODE
;
2214 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
2215 && i
.op
[0].disps
->X_op
== O_constant
)
2217 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2218 the absolute address given by the constant. Since ix86 jumps and
2219 calls are pc relative, we need to generate a reloc. */
2220 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2221 i
.op
[0].disps
->X_op
= O_symbol
;
2224 /* We are ready to output the insn. */
2229 if (i
.tm
.opcode_modifier
& Jump
)
2236 if (flag_16bit_code
)
2240 if (i
.prefix
[DATA_PREFIX
])
2251 if (i
.prefixes
!= 0 && !intel_syntax
)
2252 as_warn (_("skipping prefixes on this instruction"));
2254 /* It's always a symbol; End frag & setup for relax.
2255 Make sure there is enough room in this frag for the largest
2256 instruction we may generate in md_convert_frag. This is 2
2257 bytes for the opcode and room for the prefix and largest
2259 frag_grow (prefix
+ 2 + size
);
2260 insn_size
+= prefix
+ 1;
2261 /* Prefix and 1 opcode byte go in fr_fix. */
2262 p
= frag_more (prefix
+ 1);
2264 *p
++ = DATA_PREFIX_OPCODE
;
2265 *p
= i
.tm
.base_opcode
;
2266 /* 1 possible extra opcode + displacement go in var part.
2267 Pass reloc in fr_var. */
2268 frag_var (rs_machine_dependent
,
2271 ((unsigned char) *p
== JUMP_PC_RELATIVE
2272 ? ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
) | code16
2273 : ENCODE_RELAX_STATE (COND_JUMP
, SMALL
) | code16
),
2274 i
.op
[0].disps
->X_add_symbol
,
2275 i
.op
[0].disps
->X_add_number
,
2278 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
2282 if (i
.tm
.opcode_modifier
& JumpByte
)
2284 /* This is a loop or jecxz type instruction. */
2286 if (i
.prefix
[ADDR_PREFIX
])
2289 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2298 if (flag_16bit_code
)
2301 if (i
.prefix
[DATA_PREFIX
])
2304 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
2314 if (i
.prefixes
!= 0 && !intel_syntax
)
2315 as_warn (_("skipping prefixes on this instruction"));
2317 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2319 insn_size
+= 1 + size
;
2320 p
= frag_more (1 + size
);
2324 /* opcode can be at most two bytes */
2325 insn_size
+= 2 + size
;
2326 p
= frag_more (2 + size
);
2327 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2329 *p
++ = i
.tm
.base_opcode
& 0xff;
2331 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2332 i
.op
[0].disps
, 1, reloc (size
, 1, i
.disp_reloc
[0]));
2334 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
2341 if (flag_16bit_code
)
2345 if (i
.prefix
[DATA_PREFIX
])
2356 if (i
.prefixes
!= 0 && !intel_syntax
)
2357 as_warn (_("skipping prefixes on this instruction"));
2359 insn_size
+= prefix
+ 1 + 2 + size
; /* 1 opcode; 2 segment; offset */
2360 p
= frag_more (prefix
+ 1 + 2 + size
);
2362 *p
++ = DATA_PREFIX_OPCODE
;
2363 *p
++ = i
.tm
.base_opcode
;
2364 if (i
.op
[1].imms
->X_op
== O_constant
)
2366 offsetT n
= i
.op
[1].imms
->X_add_number
;
2369 && !fits_in_unsigned_word (n
)
2370 && !fits_in_signed_word (n
))
2372 as_bad (_("16-bit jump out of range"));
2375 md_number_to_chars (p
, n
, size
);
2378 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2379 i
.op
[1].imms
, 0, reloc (size
, 0, i
.disp_reloc
[0]));
2380 if (i
.op
[0].imms
->X_op
!= O_constant
)
2381 as_bad (_("can't handle non absolute segment in `%s'"),
2383 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
2387 /* Output normal instructions here. */
2390 /* The prefix bytes. */
2392 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2399 md_number_to_chars (p
, (valueT
) *q
, 1);
2403 /* Now the opcode; be careful about word order here! */
2404 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2407 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2409 else if (fits_in_unsigned_word (i
.tm
.base_opcode
))
2413 /* put out high byte first: can't use md_number_to_chars! */
2414 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2415 *p
= i
.tm
.base_opcode
& 0xff;
2418 { /* opcode is either 3 or 4 bytes */
2419 if (i
.tm
.base_opcode
& 0xff000000)
2423 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
2430 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
2431 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2432 *p
= (i
.tm
.base_opcode
) & 0xff;
2435 /* Now the modrm byte and sib byte (if present). */
2436 if (i
.tm
.opcode_modifier
& Modrm
)
2440 md_number_to_chars (p
,
2441 (valueT
) (i
.rm
.regmem
<< 0
2445 /* If i.rm.regmem == ESP (4)
2446 && i.rm.mode != (Register mode)
2448 ==> need second modrm byte. */
2449 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2451 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2455 md_number_to_chars (p
,
2456 (valueT
) (i
.sib
.base
<< 0
2458 | i
.sib
.scale
<< 6),
2463 if (i
.disp_operands
)
2465 register unsigned int n
;
2467 for (n
= 0; n
< i
.operands
; n
++)
2469 if (i
.types
[n
] & Disp
)
2471 if (i
.op
[n
].disps
->X_op
== O_constant
)
2477 if (i
.types
[n
] & (Disp8
| Disp16
))
2480 if (i
.types
[n
] & Disp8
)
2483 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
2486 p
= frag_more (size
);
2487 md_number_to_chars (p
, val
, size
);
2493 if (i
.types
[n
] & Disp16
)
2497 p
= frag_more (size
);
2498 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2500 reloc (size
, 0, i
.disp_reloc
[n
]));
2504 } /* end displacement output */
2506 /* output immediate */
2509 register unsigned int n
;
2511 for (n
= 0; n
< i
.operands
; n
++)
2513 if (i
.types
[n
] & Imm
)
2515 if (i
.op
[n
].imms
->X_op
== O_constant
)
2521 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
))
2524 if (i
.types
[n
] & (Imm8
| Imm8S
))
2527 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
2530 p
= frag_more (size
);
2531 md_number_to_chars (p
, val
, size
);
2534 { /* not absolute_section */
2535 /* Need a 32-bit fixup (don't support 8bit
2536 non-absolute imms). Try to support other
2538 #ifdef BFD_ASSEMBLER
2539 enum bfd_reloc_code_real reloc_type
;
2545 if (i
.types
[n
] & Imm16
)
2547 else if (i
.types
[n
] & (Imm8
| Imm8S
))
2551 p
= frag_more (size
);
2552 reloc_type
= reloc (size
, 0, i
.disp_reloc
[0]);
2553 #ifdef BFD_ASSEMBLER
2554 if (reloc_type
== BFD_RELOC_32
2556 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
2557 && (i
.op
[n
].imms
->X_op
== O_symbol
2558 || (i
.op
[n
].imms
->X_op
== O_add
2559 && ((symbol_get_value_expression
2560 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
2563 reloc_type
= BFD_RELOC_386_GOTPC
;
2564 i
.op
[n
].imms
->X_add_number
+= 3;
2567 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2568 i
.op
[n
].imms
, 0, reloc_type
);
2572 } /* end immediate output */
2580 #endif /* DEBUG386 */
2584 static int i386_immediate
PARAMS ((char *));
2587 i386_immediate (imm_start
)
2590 char *save_input_line_pointer
;
2594 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
2596 as_bad (_("only 1 or 2 immediate operands are allowed"));
2600 exp
= &im_expressions
[i
.imm_operands
++];
2601 i
.op
[this_operand
].imms
= exp
;
2603 if (is_space_char (*imm_start
))
2606 save_input_line_pointer
= input_line_pointer
;
2607 input_line_pointer
= imm_start
;
2612 * We can have operands of the form
2613 * <symbol>@GOTOFF+<nnn>
2614 * Take the easy way out here and copy everything
2615 * into a temporary buffer...
2619 cp
= strchr (input_line_pointer
, '@');
2626 /* GOT relocations are not supported in 16 bit mode */
2627 if (flag_16bit_code
)
2628 as_bad (_("GOT relocations not supported in 16 bit mode"));
2630 if (GOT_symbol
== NULL
)
2631 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
2633 if (strncmp (cp
+ 1, "PLT", 3) == 0)
2635 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
2638 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
2640 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
2643 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
2645 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
2649 as_bad (_("bad reloc specifier in expression"));
2651 /* Replace the relocation token with ' ', so that errors like
2652 foo@GOTOFF1 will be detected. */
2653 first
= cp
- input_line_pointer
;
2654 tmpbuf
= (char *) alloca (strlen(input_line_pointer
));
2655 memcpy (tmpbuf
, input_line_pointer
, first
);
2656 tmpbuf
[first
] = ' ';
2657 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
2658 input_line_pointer
= tmpbuf
;
2663 exp_seg
= expression (exp
);
2666 if (*input_line_pointer
)
2667 as_bad (_("ignoring junk `%s' after expression"), input_line_pointer
);
2669 input_line_pointer
= save_input_line_pointer
;
2671 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
2673 /* missing or bad expr becomes absolute 0 */
2674 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
2676 exp
->X_op
= O_constant
;
2677 exp
->X_add_number
= 0;
2678 exp
->X_add_symbol
= (symbolS
*) 0;
2679 exp
->X_op_symbol
= (symbolS
*) 0;
2682 if (exp
->X_op
== O_constant
)
2684 i
.types
[this_operand
] |= Imm32
; /* Size it properly later. */
2686 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
2688 #ifdef BFD_ASSEMBLER
2689 OUTPUT_FLAVOR
== bfd_target_aout_flavour
&&
2691 exp_seg
!= text_section
2692 && exp_seg
!= data_section
2693 && exp_seg
!= bss_section
2694 && exp_seg
!= undefined_section
2695 #ifdef BFD_ASSEMBLER
2696 && !bfd_is_com_section (exp_seg
)
2700 #ifdef BFD_ASSEMBLER
2701 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
2703 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
2710 /* This is an address. The size of the address will be
2711 determined later, depending on destination register,
2712 suffix, or the default for the section. We exclude
2713 Imm8S here so that `push $foo' and other instructions
2714 with an Imm8S form will use Imm16 or Imm32. */
2715 i
.types
[this_operand
] |= (Imm8
| Imm16
| Imm32
);
2721 static int i386_scale
PARAMS ((char *));
2727 if (!isdigit (*scale
))
2734 i
.log2_scale_factor
= 0;
2737 i
.log2_scale_factor
= 1;
2740 i
.log2_scale_factor
= 2;
2743 i
.log2_scale_factor
= 3;
2747 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
2751 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
2753 as_warn (_("scale factor of %d without an index register"),
2754 1 << i
.log2_scale_factor
);
2755 #if SCALE1_WHEN_NO_INDEX
2756 i
.log2_scale_factor
= 0;
2762 static int i386_displacement
PARAMS ((char *, char *));
2765 i386_displacement (disp_start
, disp_end
)
2769 register expressionS
*exp
;
2771 char *save_input_line_pointer
;
2772 int bigdisp
= Disp32
;
2774 if (flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0))
2776 i
.types
[this_operand
] |= bigdisp
;
2778 exp
= &disp_expressions
[i
.disp_operands
];
2779 i
.op
[this_operand
].disps
= exp
;
2781 save_input_line_pointer
= input_line_pointer
;
2782 input_line_pointer
= disp_start
;
2783 END_STRING_AND_SAVE (disp_end
);
2785 #ifndef GCC_ASM_O_HACK
2786 #define GCC_ASM_O_HACK 0
2789 END_STRING_AND_SAVE (disp_end
+ 1);
2790 if ((i
.types
[this_operand
] & BaseIndex
) != 0
2791 && displacement_string_end
[-1] == '+')
2793 /* This hack is to avoid a warning when using the "o"
2794 constraint within gcc asm statements.
2797 #define _set_tssldt_desc(n,addr,limit,type) \
2798 __asm__ __volatile__ ( \
2800 "movw %w1,2+%0\n\t" \
2802 "movb %b1,4+%0\n\t" \
2803 "movb %4,5+%0\n\t" \
2804 "movb $0,6+%0\n\t" \
2805 "movb %h1,7+%0\n\t" \
2807 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
2809 This works great except that the output assembler ends
2810 up looking a bit weird if it turns out that there is
2811 no offset. You end up producing code that looks like:
2824 So here we provide the missing zero.
2827 *displacement_string_end
= '0';
2833 * We can have operands of the form
2834 * <symbol>@GOTOFF+<nnn>
2835 * Take the easy way out here and copy everything
2836 * into a temporary buffer...
2840 cp
= strchr (input_line_pointer
, '@');
2847 /* GOT relocations are not supported in 16 bit mode */
2848 if (flag_16bit_code
)
2849 as_bad (_("GOT relocations not supported in 16 bit mode"));
2851 if (GOT_symbol
== NULL
)
2852 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
2854 if (strncmp (cp
+ 1, "PLT", 3) == 0)
2856 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
2859 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
2861 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
2864 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
2866 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
2870 as_bad (_("bad reloc specifier in expression"));
2872 /* Replace the relocation token with ' ', so that errors like
2873 foo@GOTOFF1 will be detected. */
2874 first
= cp
- input_line_pointer
;
2875 tmpbuf
= (char *) alloca (strlen(input_line_pointer
));
2876 memcpy (tmpbuf
, input_line_pointer
, first
);
2877 tmpbuf
[first
] = ' ';
2878 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
2879 input_line_pointer
= tmpbuf
;
2884 exp_seg
= expression (exp
);
2886 #ifdef BFD_ASSEMBLER
2887 /* We do this to make sure that the section symbol is in
2888 the symbol table. We will ultimately change the relocation
2889 to be relative to the beginning of the section */
2890 if (i
.disp_reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
)
2892 if (S_IS_LOCAL(exp
->X_add_symbol
)
2893 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
2894 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
2895 assert (exp
->X_op
== O_symbol
);
2896 exp
->X_op
= O_subtract
;
2897 exp
->X_op_symbol
= GOT_symbol
;
2898 i
.disp_reloc
[this_operand
] = BFD_RELOC_32
;
2903 if (*input_line_pointer
)
2904 as_bad (_("ignoring junk `%s' after expression"),
2905 input_line_pointer
);
2907 RESTORE_END_STRING (disp_end
+ 1);
2909 RESTORE_END_STRING (disp_end
);
2910 input_line_pointer
= save_input_line_pointer
;
2912 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
2914 /* missing or bad expr becomes absolute 0 */
2915 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2917 exp
->X_op
= O_constant
;
2918 exp
->X_add_number
= 0;
2919 exp
->X_add_symbol
= (symbolS
*) 0;
2920 exp
->X_op_symbol
= (symbolS
*) 0;
2923 if (exp
->X_op
== O_constant
)
2925 if (i
.types
[this_operand
] & Disp16
)
2927 /* We know this operand is at most 16 bits, so convert to a
2928 signed 16 bit number before trying to see whether it will
2929 fit in an even smaller size. */
2931 (((exp
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2933 if (fits_in_signed_byte (exp
->X_add_number
))
2934 i
.types
[this_operand
] |= Disp8
;
2936 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
2938 #ifdef BFD_ASSEMBLER
2939 OUTPUT_FLAVOR
== bfd_target_aout_flavour
&&
2941 exp_seg
!= text_section
2942 && exp_seg
!= data_section
2943 && exp_seg
!= bss_section
2944 && exp_seg
!= undefined_section
)
2946 #ifdef BFD_ASSEMBLER
2947 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
2949 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
2957 static int i386_operand_modifier
PARAMS ((char **, int));
2960 i386_operand_modifier (op_string
, got_a_float
)
2964 if (!strncasecmp (*op_string
, "BYTE PTR", 8))
2966 i
.suffix
= BYTE_MNEM_SUFFIX
;
2971 else if (!strncasecmp (*op_string
, "WORD PTR", 8))
2973 if (got_a_float
== 2) /* "fi..." */
2974 i
.suffix
= SHORT_MNEM_SUFFIX
;
2976 i
.suffix
= WORD_MNEM_SUFFIX
;
2981 else if (!strncasecmp (*op_string
, "DWORD PTR", 9))
2983 if (got_a_float
== 1) /* "f..." */
2984 i
.suffix
= SHORT_MNEM_SUFFIX
;
2986 i
.suffix
= LONG_MNEM_SUFFIX
;
2991 else if (!strncasecmp (*op_string
, "QWORD PTR", 9))
2993 i
.suffix
= DWORD_MNEM_SUFFIX
;
2998 else if (!strncasecmp (*op_string
, "XWORD PTR", 9))
3000 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
3005 else if (!strncasecmp (*op_string
, "SHORT", 5))
3011 else if (!strncasecmp (*op_string
, "OFFSET FLAT:", 12))
3017 else if (!strncasecmp (*op_string
, "FLAT", 4))
3023 else return NONE_FOUND
;
3026 static char * build_displacement_string
PARAMS ((int, char *));
3029 build_displacement_string (initial_disp
, op_string
)
3033 char *temp_string
= (char *) malloc (strlen (op_string
) + 1);
3034 char *end_of_operand_string
;
3038 temp_string
[0] = '\0';
3039 tc
= end_of_operand_string
= strchr (op_string
, '[');
3040 if (initial_disp
&& !end_of_operand_string
)
3042 strcpy (temp_string
, op_string
);
3046 /* Build the whole displacement string */
3049 strncpy (temp_string
, op_string
, end_of_operand_string
- op_string
);
3050 temp_string
[end_of_operand_string
- op_string
] = '\0';
3054 temp_disp
= op_string
;
3056 while (*temp_disp
!= '\0')
3059 int add_minus
= (*temp_disp
== '-');
3061 if (*temp_disp
== '+' || *temp_disp
== '-' || *temp_disp
== '[')
3064 if (is_space_char (*temp_disp
))
3067 /* Don't consider registers */
3068 if ( !((*temp_disp
== REGISTER_PREFIX
|| allow_naked_reg
)
3069 && parse_register (temp_disp
, &end_op
)) )
3071 char *string_start
= temp_disp
;
3073 while (*temp_disp
!= ']'
3074 && *temp_disp
!= '+'
3075 && *temp_disp
!= '-'
3076 && *temp_disp
!= '*')
3080 strcat (temp_string
, "-");
3082 strcat (temp_string
, "+");
3084 strncat (temp_string
, string_start
, temp_disp
- string_start
);
3085 if (*temp_disp
== '+' || *temp_disp
== '-')
3089 while (*temp_disp
!= '\0'
3090 && *temp_disp
!= '+'
3091 && *temp_disp
!= '-')
3098 static int i386_parse_seg
PARAMS ((char *));
3101 i386_parse_seg (op_string
)
3104 if (is_space_char (*op_string
))
3107 /* Should be one of es, cs, ss, ds fs or gs */
3108 switch (*op_string
++)
3111 i
.seg
[i
.mem_operands
] = &es
;
3114 i
.seg
[i
.mem_operands
] = &cs
;
3117 i
.seg
[i
.mem_operands
] = &ss
;
3120 i
.seg
[i
.mem_operands
] = &ds
;
3123 i
.seg
[i
.mem_operands
] = &fs
;
3126 i
.seg
[i
.mem_operands
] = &gs
;
3129 as_bad (_("bad segment name `%s'"), op_string
);
3133 if (*op_string
++ != 's')
3135 as_bad (_("bad segment name `%s'"), op_string
);
3139 if (is_space_char (*op_string
))
3142 if (*op_string
!= ':')
3144 as_bad (_("bad segment name `%s'"), op_string
);
3152 static int i386_index_check
PARAMS((const char *));
3154 /* Make sure the memory operand we've been dealt is valid.
3155 Returns 1 on success, 0 on a failure.
3158 i386_index_check (operand_string
)
3159 const char *operand_string
;
3161 #if INFER_ADDR_PREFIX
3166 if (flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0)
3167 /* 16 bit mode checks */
3169 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
))
3170 != (Reg16
|BaseIndex
)))
3172 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
3173 != (Reg16
|BaseIndex
))
3175 && i
.base_reg
->reg_num
< 6
3176 && i
.index_reg
->reg_num
>= 6
3177 && i
.log2_scale_factor
== 0))))
3178 /* 32 bit mode checks */
3180 && (i
.base_reg
->reg_type
& Reg32
) == 0)
3182 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
))
3183 != (Reg32
|BaseIndex
)))))
3185 #if INFER_ADDR_PREFIX
3186 if (i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3188 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3190 /* Change the size of any displacement too. At most one of
3191 Disp16 or Disp32 is set.
3192 FIXME. There doesn't seem to be any real need for separate
3193 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3194 Removing them would probably clean up the code quite a lot.
3196 if (i
.types
[this_operand
] & (Disp16
|Disp32
))
3197 i
.types
[this_operand
] ^= (Disp16
|Disp32
);
3202 as_bad (_("`%s' is not a valid base/index expression"),
3206 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3208 flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0) ? "16" : "32");
3214 static int i386_intel_memory_operand
PARAMS ((char *));
3217 i386_intel_memory_operand (operand_string
)
3218 char *operand_string
;
3220 char *op_string
= operand_string
;
3221 char *end_of_operand_string
;
3223 if ((i
.mem_operands
== 1
3224 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3225 || i
.mem_operands
== 2)
3227 as_bad (_("too many memory references for `%s'"),
3228 current_templates
->start
->name
);
3232 /* First check for a segment override. */
3233 if (*op_string
!= '[')
3237 end_seg
= strchr (op_string
, ':');
3240 if (!i386_parse_seg (op_string
))
3242 op_string
= end_seg
+ 1;
3246 /* Look for displacement preceding open bracket */
3247 if (*op_string
!= '[')
3251 if (i
.disp_operands
)
3254 temp_string
= build_displacement_string (true, op_string
);
3256 if (!i386_displacement (temp_string
, temp_string
+ strlen (temp_string
)))
3263 end_of_operand_string
= strchr (op_string
, '[');
3264 if (!end_of_operand_string
)
3265 end_of_operand_string
= op_string
+ strlen (op_string
);
3267 if (is_space_char (*end_of_operand_string
))
3268 --end_of_operand_string
;
3270 op_string
= end_of_operand_string
;
3273 if (*op_string
== '[')
3277 /* Pick off each component and figure out where it belongs */
3279 end_of_operand_string
= op_string
;
3281 while (*op_string
!= ']')
3283 const reg_entry
*temp_reg
;
3287 while (*end_of_operand_string
!= '+'
3288 && *end_of_operand_string
!= '-'
3289 && *end_of_operand_string
!= '*'
3290 && *end_of_operand_string
!= ']')
3291 end_of_operand_string
++;
3293 temp_string
= op_string
;
3294 if (*temp_string
== '+')
3297 if (is_space_char (*temp_string
))
3301 if ((*temp_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3302 && (temp_reg
= parse_register (temp_string
, &end_op
)) != NULL
)
3304 if (i
.base_reg
== NULL
)
3305 i
.base_reg
= temp_reg
;
3307 i
.index_reg
= temp_reg
;
3309 i
.types
[this_operand
] |= BaseIndex
;
3311 else if (*temp_string
== REGISTER_PREFIX
)
3313 as_bad (_("bad register name `%s'"), temp_string
);
3316 else if (is_digit_char (*op_string
)
3317 || *op_string
== '+' || *op_string
== '-')
3321 if (i
.disp_operands
!= 0)
3324 temp_string
= build_displacement_string (false, op_string
);
3326 temp_str
= temp_string
;
3327 if (*temp_str
== '+')
3330 if (!i386_displacement (temp_str
, temp_str
+ strlen (temp_str
)))
3338 end_of_operand_string
= op_string
;
3339 while (*end_of_operand_string
!= ']'
3340 && *end_of_operand_string
!= '+'
3341 && *end_of_operand_string
!= '-'
3342 && *end_of_operand_string
!= '*')
3343 ++end_of_operand_string
;
3345 else if (*op_string
== '*')
3349 if (i
.base_reg
&& !i
.index_reg
)
3351 i
.index_reg
= i
.base_reg
;
3355 if (!i386_scale (op_string
))
3358 op_string
= end_of_operand_string
;
3359 ++end_of_operand_string
;
3363 if (i386_index_check (operand_string
) == 0)
3371 i386_intel_operand (operand_string
, got_a_float
)
3372 char *operand_string
;
3375 const reg_entry
* r
;
3377 char *op_string
= operand_string
;
3379 int operand_modifier
= i386_operand_modifier (&op_string
, got_a_float
);
3380 if (is_space_char (*op_string
))
3383 switch (operand_modifier
)
3390 if (!i386_intel_memory_operand (op_string
))
3396 if (!i386_immediate (op_string
))
3402 /* Should be register or immediate */
3403 if (is_digit_char (*op_string
)
3404 && strchr (op_string
, '[') == 0)
3406 if (!i386_immediate (op_string
))
3409 else if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3410 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3412 /* Check for a segment override by searching for ':' after a
3413 segment register. */
3415 if (is_space_char (*op_string
))
3417 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3422 i
.seg
[i
.mem_operands
] = &es
;
3425 i
.seg
[i
.mem_operands
] = &cs
;
3428 i
.seg
[i
.mem_operands
] = &ss
;
3431 i
.seg
[i
.mem_operands
] = &ds
;
3434 i
.seg
[i
.mem_operands
] = &fs
;
3437 i
.seg
[i
.mem_operands
] = &gs
;
3442 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3443 i
.op
[this_operand
].regs
= r
;
3446 else if (*op_string
== REGISTER_PREFIX
)
3448 as_bad (_("bad register name `%s'"), op_string
);
3451 else if (!i386_intel_memory_operand (op_string
))
3460 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3464 i386_operand (operand_string
)
3465 char *operand_string
;
3469 char *op_string
= operand_string
;
3471 if (is_space_char (*op_string
))
3474 /* We check for an absolute prefix (differentiating,
3475 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3476 if (*op_string
== ABSOLUTE_PREFIX
)
3479 if (is_space_char (*op_string
))
3481 i
.types
[this_operand
] |= JumpAbsolute
;
3484 /* Check if operand is a register. */
3485 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3486 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3488 /* Check for a segment override by searching for ':' after a
3489 segment register. */
3491 if (is_space_char (*op_string
))
3493 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3498 i
.seg
[i
.mem_operands
] = &es
;
3501 i
.seg
[i
.mem_operands
] = &cs
;
3504 i
.seg
[i
.mem_operands
] = &ss
;
3507 i
.seg
[i
.mem_operands
] = &ds
;
3510 i
.seg
[i
.mem_operands
] = &fs
;
3513 i
.seg
[i
.mem_operands
] = &gs
;
3517 /* Skip the ':' and whitespace. */
3519 if (is_space_char (*op_string
))
3522 if (!is_digit_char (*op_string
)
3523 && !is_identifier_char (*op_string
)
3524 && *op_string
!= '('
3525 && *op_string
!= ABSOLUTE_PREFIX
)
3527 as_bad (_("bad memory operand `%s'"), op_string
);
3530 /* Handle case of %es:*foo. */
3531 if (*op_string
== ABSOLUTE_PREFIX
)
3534 if (is_space_char (*op_string
))
3536 i
.types
[this_operand
] |= JumpAbsolute
;
3538 goto do_memory_reference
;
3542 as_bad (_("junk `%s' after register"), op_string
);
3545 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3546 i
.op
[this_operand
].regs
= r
;
3549 else if (*op_string
== REGISTER_PREFIX
)
3551 as_bad (_("bad register name `%s'"), op_string
);
3554 else if (*op_string
== IMMEDIATE_PREFIX
)
3555 { /* ... or an immediate */
3557 if (i
.types
[this_operand
] & JumpAbsolute
)
3559 as_bad (_("immediate operand illegal with absolute jump"));
3562 if (!i386_immediate (op_string
))
3565 else if (is_digit_char (*op_string
)
3566 || is_identifier_char (*op_string
)
3567 || *op_string
== '(' )
3569 /* This is a memory reference of some sort. */
3572 /* Start and end of displacement string expression (if found). */
3573 char *displacement_string_start
;
3574 char *displacement_string_end
;
3576 do_memory_reference
:
3577 if ((i
.mem_operands
== 1
3578 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3579 || i
.mem_operands
== 2)
3581 as_bad (_("too many memory references for `%s'"),
3582 current_templates
->start
->name
);
3586 /* Check for base index form. We detect the base index form by
3587 looking for an ')' at the end of the operand, searching
3588 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3590 base_string
= op_string
+ strlen (op_string
);
3593 if (is_space_char (*base_string
))
3596 /* If we only have a displacement, set-up for it to be parsed later. */
3597 displacement_string_start
= op_string
;
3598 displacement_string_end
= base_string
+ 1;
3600 if (*base_string
== ')')
3603 unsigned int parens_balanced
= 1;
3604 /* We've already checked that the number of left & right ()'s are
3605 equal, so this loop will not be infinite. */
3609 if (*base_string
== ')')
3611 if (*base_string
== '(')
3614 while (parens_balanced
);
3616 temp_string
= base_string
;
3618 /* Skip past '(' and whitespace. */
3620 if (is_space_char (*base_string
))
3623 if (*base_string
== ','
3624 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3625 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
3627 displacement_string_end
= temp_string
;
3629 i
.types
[this_operand
] |= BaseIndex
;
3633 base_string
= end_op
;
3634 if (is_space_char (*base_string
))
3638 /* There may be an index reg or scale factor here. */
3639 if (*base_string
== ',')
3642 if (is_space_char (*base_string
))
3645 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3646 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
3648 base_string
= end_op
;
3649 if (is_space_char (*base_string
))
3651 if (*base_string
== ',')
3654 if (is_space_char (*base_string
))
3657 else if (*base_string
!= ')' )
3659 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3664 else if (*base_string
== REGISTER_PREFIX
)
3666 as_bad (_("bad register name `%s'"), base_string
);
3670 /* Check for scale factor. */
3671 if (isdigit ((unsigned char) *base_string
))
3673 if (!i386_scale (base_string
))
3677 if (is_space_char (*base_string
))
3679 if (*base_string
!= ')')
3681 as_bad (_("expecting `)' after scale factor in `%s'"),
3686 else if (!i
.index_reg
)
3688 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3693 else if (*base_string
!= ')')
3695 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3700 else if (*base_string
== REGISTER_PREFIX
)
3702 as_bad (_("bad register name `%s'"), base_string
);
3707 /* If there's an expression beginning the operand, parse it,
3708 assuming displacement_string_start and
3709 displacement_string_end are meaningful. */
3710 if (displacement_string_start
!= displacement_string_end
)
3712 if (!i386_displacement (displacement_string_start
,
3713 displacement_string_end
))
3717 /* Special case for (%dx) while doing input/output op. */
3719 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
3721 && i
.log2_scale_factor
== 0
3722 && i
.seg
[i
.mem_operands
] == 0
3723 && (i
.types
[this_operand
] & Disp
) == 0)
3725 i
.types
[this_operand
] = InOutPortReg
;
3729 if (i386_index_check (operand_string
) == 0)
3734 { /* it's not a memory operand; argh! */
3735 as_bad (_("invalid char %s beginning operand %d `%s'"),
3736 output_invalid (*op_string
),
3741 return 1; /* normal return */
3744 /* md_estimate_size_before_relax()
3746 Called just before relax() for rs_machine_dependent frags. The x86
3747 assembler uses these frags to handle variable size jump
3750 Any symbol that is now undefined will not become defined.
3751 Return the correct fr_subtype in the frag.
3752 Return the initial "guess for variable size of frag" to caller.
3753 The guess is actually the growth beyond the fixed part. Whatever
3754 we do to grow the fixed or variable part contributes to our
3758 md_estimate_size_before_relax (fragP
, segment
)
3759 register fragS
*fragP
;
3760 register segT segment
;
3762 /* We've already got fragP->fr_subtype right; all we have to do is
3763 check for un-relaxable symbols. On an ELF system, we can't relax
3764 an externally visible symbol, because it may be overridden by a
3766 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3767 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PE)
3768 || S_IS_EXTERNAL (fragP
->fr_symbol
)
3769 || S_IS_WEAK (fragP
->fr_symbol
)
3773 /* Symbol is undefined in this segment, or we need to keep a
3774 reloc so that weak symbols can be overridden. */
3775 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
3776 #ifdef BFD_ASSEMBLER
3777 enum bfd_reloc_code_real reloc_type
;
3781 unsigned char *opcode
;
3784 if (fragP
->fr_var
!= NO_RELOC
)
3785 reloc_type
= fragP
->fr_var
;
3787 reloc_type
= BFD_RELOC_16_PCREL
;
3789 reloc_type
= BFD_RELOC_32_PCREL
;
3791 old_fr_fix
= fragP
->fr_fix
;
3792 opcode
= (unsigned char *) fragP
->fr_opcode
;
3796 case JUMP_PC_RELATIVE
: /* make jmp (0xeb) a dword displacement jump */
3797 opcode
[0] = 0xe9; /* dword disp jmp */
3798 fragP
->fr_fix
+= size
;
3799 fix_new (fragP
, old_fr_fix
, size
,
3801 fragP
->fr_offset
, 1,
3806 /* This changes the byte-displacement jump 0x7N
3807 to the dword-displacement jump 0x0f,0x8N. */
3808 opcode
[1] = opcode
[0] + 0x10;
3809 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3810 fragP
->fr_fix
+= 1 + size
; /* we've added an opcode byte */
3811 fix_new (fragP
, old_fr_fix
+ 1, size
,
3813 fragP
->fr_offset
, 1,
3818 return fragP
->fr_fix
- old_fr_fix
;
3820 return 1; /* Guess a short jump. */
3824 * md_convert_frag();
3826 * Called after relax() is finished.
3827 * In: Address of frag.
3828 * fr_type == rs_machine_dependent.
3829 * fr_subtype is what the address relaxed to.
3831 * Out: Any fixSs and constants are set up.
3832 * Caller will turn frag into a ".space 0".
3834 #ifndef BFD_ASSEMBLER
3836 md_convert_frag (headers
, sec
, fragP
)
3837 object_headers
*headers ATTRIBUTE_UNUSED
;
3838 segT sec ATTRIBUTE_UNUSED
;
3839 register fragS
*fragP
;
3842 md_convert_frag (abfd
, sec
, fragP
)
3843 bfd
*abfd ATTRIBUTE_UNUSED
;
3844 segT sec ATTRIBUTE_UNUSED
;
3845 register fragS
*fragP
;
3848 register unsigned char *opcode
;
3849 unsigned char *where_to_put_displacement
= NULL
;
3850 offsetT target_address
;
3851 offsetT opcode_address
;
3852 unsigned int extension
= 0;
3853 offsetT displacement_from_opcode_start
;
3855 opcode
= (unsigned char *) fragP
->fr_opcode
;
3857 /* Address we want to reach in file space. */
3858 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
3859 #ifdef BFD_ASSEMBLER /* not needed otherwise? */
3860 target_address
+= symbol_get_frag (fragP
->fr_symbol
)->fr_address
;
3863 /* Address opcode resides at in file space. */
3864 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
3866 /* Displacement from opcode start to fill into instruction. */
3867 displacement_from_opcode_start
= target_address
- opcode_address
;
3869 switch (fragP
->fr_subtype
)
3871 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL
):
3872 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL16
):
3873 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
):
3874 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL16
):
3875 /* don't have to change opcode */
3876 extension
= 1; /* 1 opcode + 1 displacement */
3877 where_to_put_displacement
= &opcode
[1];
3880 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
3881 extension
= 5; /* 2 opcode + 4 displacement */
3882 opcode
[1] = opcode
[0] + 0x10;
3883 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3884 where_to_put_displacement
= &opcode
[2];
3887 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
3888 extension
= 4; /* 1 opcode + 4 displacement */
3890 where_to_put_displacement
= &opcode
[1];
3893 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
3894 extension
= 3; /* 2 opcode + 2 displacement */
3895 opcode
[1] = opcode
[0] + 0x10;
3896 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3897 where_to_put_displacement
= &opcode
[2];
3900 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
3901 extension
= 2; /* 1 opcode + 2 displacement */
3903 where_to_put_displacement
= &opcode
[1];
3907 BAD_CASE (fragP
->fr_subtype
);
3910 /* now put displacement after opcode */
3911 md_number_to_chars ((char *) where_to_put_displacement
,
3912 (valueT
) (displacement_from_opcode_start
- extension
),
3913 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
3914 fragP
->fr_fix
+= extension
;
3918 int md_short_jump_size
= 2; /* size of byte displacement jmp */
3919 int md_long_jump_size
= 5; /* size of dword displacement jmp */
3920 const int md_reloc_size
= 8; /* Size of relocation record */
3923 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
3925 addressT from_addr
, to_addr
;
3926 fragS
*frag ATTRIBUTE_UNUSED
;
3927 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
3931 offset
= to_addr
- (from_addr
+ 2);
3932 md_number_to_chars (ptr
, (valueT
) 0xeb, 1); /* opcode for byte-disp jump */
3933 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
3937 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
3939 addressT from_addr
, to_addr
;
3940 fragS
*frag ATTRIBUTE_UNUSED
;
3941 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
3945 offset
= to_addr
- (from_addr
+ 5);
3946 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
3947 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
3950 /* Apply a fixup (fixS) to segment data, once it has been determined
3951 by our caller that we have all the info we need to fix it up.
3953 On the 386, immediates, displacements, and data pointers are all in
3954 the same (little-endian) format, so we don't need to care about which
3958 md_apply_fix3 (fixP
, valp
, seg
)
3959 fixS
*fixP
; /* The fix we're to put in. */
3960 valueT
*valp
; /* Pointer to the value of the bits. */
3961 segT seg ATTRIBUTE_UNUSED
; /* Segment fix is from. */
3963 register char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3964 valueT value
= *valp
;
3966 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
3969 switch (fixP
->fx_r_type
)
3975 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
3978 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
3981 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
3986 /* This is a hack. There should be a better way to handle this.
3987 This covers for the fact that bfd_install_relocation will
3988 subtract the current location (for partial_inplace, PC relative
3989 relocations); see more below. */
3990 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
3991 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
3992 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
3996 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
3998 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4001 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4003 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4004 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4006 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4009 || (symbol_section_p (fixP
->fx_addsy
)
4010 && fseg
!= absolute_section
))
4011 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
4012 && ! S_IS_WEAK (fixP
->fx_addsy
)
4013 && S_IS_DEFINED (fixP
->fx_addsy
)
4014 && ! S_IS_COMMON (fixP
->fx_addsy
))
4016 /* Yes, we add the values in twice. This is because
4017 bfd_perform_relocation subtracts them out again. I think
4018 bfd_perform_relocation is broken, but I don't dare change
4020 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4024 #if defined (OBJ_COFF) && defined (TE_PE)
4025 /* For some reason, the PE format does not store a section
4026 address offset for a PC relative symbol. */
4027 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4028 value
+= md_pcrel_from (fixP
);
4029 else if (S_IS_EXTERNAL (fixP
->fx_addsy
)
4030 || S_IS_WEAK (fixP
->fx_addsy
))
4032 /* We are generating an external relocation for this defined
4033 symbol. We add the address, because
4034 bfd_install_relocation will subtract it. VALUE already
4035 holds the symbol value, because fixup_segment added it
4036 in. We subtract it out, and then we subtract it out
4037 again because bfd_install_relocation will add it in
4039 value
+= md_pcrel_from (fixP
);
4040 value
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
4045 else if (fixP
->fx_addsy
!= NULL
4046 && S_IS_DEFINED (fixP
->fx_addsy
)
4047 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
4048 || S_IS_WEAK (fixP
->fx_addsy
)))
4050 /* We are generating an external relocation for this defined
4051 symbol. VALUE already holds the symbol value, and
4052 bfd_install_relocation will add it in again. We don't want
4054 value
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
4058 /* Fix a few things - the dynamic linker expects certain values here,
4059 and we must not dissappoint it. */
4060 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4061 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4063 switch (fixP
->fx_r_type
) {
4064 case BFD_RELOC_386_PLT32
:
4065 /* Make the jump instruction point to the address of the operand. At
4066 runtime we merely add the offset to the actual PLT entry. */
4069 case BFD_RELOC_386_GOTPC
:
4071 * This is tough to explain. We end up with this one if we have
4072 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4073 * here is to obtain the absolute address of the GOT, and it is strongly
4074 * preferable from a performance point of view to avoid using a runtime
4075 * relocation for this. The actual sequence of instructions often look
4081 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4083 * The call and pop essentially return the absolute address of
4084 * the label .L66 and store it in %ebx. The linker itself will
4085 * ultimately change the first operand of the addl so that %ebx points to
4086 * the GOT, but to keep things simple, the .o file must have this operand
4087 * set so that it generates not the absolute address of .L66, but the
4088 * absolute address of itself. This allows the linker itself simply
4089 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4090 * added in, and the addend of the relocation is stored in the operand
4091 * field for the instruction itself.
4093 * Our job here is to fix the operand so that it would add the correct
4094 * offset so that %ebx would point to itself. The thing that is tricky is
4095 * that .-.L66 will point to the beginning of the instruction, so we need
4096 * to further modify the operand so that it will point to itself.
4097 * There are other cases where you have something like:
4099 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4101 * and here no correction would be required. Internally in the assembler
4102 * we treat operands of this form as not being pcrel since the '.' is
4103 * explicitly mentioned, and I wonder whether it would simplify matters
4104 * to do it this way. Who knows. In earlier versions of the PIC patches,
4105 * the pcrel_adjust field was used to store the correction, but since the
4106 * expression is not pcrel, I felt it would be confusing to do it this way.
4110 case BFD_RELOC_386_GOT32
:
4111 value
= 0; /* Fully resolved at runtime. No addend. */
4113 case BFD_RELOC_386_GOTOFF
:
4116 case BFD_RELOC_VTABLE_INHERIT
:
4117 case BFD_RELOC_VTABLE_ENTRY
:
4124 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4126 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4127 md_number_to_chars (p
, value
, fixP
->fx_size
);
4133 #define MAX_LITTLENUMS 6
4135 /* Turn the string pointed to by litP into a floating point constant of type
4136 type, and emit the appropriate bytes. The number of LITTLENUMS emitted
4137 is stored in *sizeP . An error message is returned, or NULL on OK. */
4139 md_atof (type
, litP
, sizeP
)
4145 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4146 LITTLENUM_TYPE
*wordP
;
4168 return _("Bad call to md_atof ()");
4170 t
= atof_ieee (input_line_pointer
, type
, words
);
4172 input_line_pointer
= t
;
4174 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4175 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4176 the bigendian 386. */
4177 for (wordP
= words
+ prec
- 1; prec
--;)
4179 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4180 litP
+= sizeof (LITTLENUM_TYPE
);
4185 char output_invalid_buf
[8];
4192 sprintf (output_invalid_buf
, "'%c'", c
);
4194 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4195 return output_invalid_buf
;
4199 /* REG_STRING starts *before* REGISTER_PREFIX. */
4201 static const reg_entry
*
4202 parse_register (reg_string
, end_op
)
4206 char *s
= reg_string
;
4208 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4211 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4212 if (*s
== REGISTER_PREFIX
)
4215 if (is_space_char (*s
))
4219 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4221 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4222 return (const reg_entry
*) NULL
;
4228 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4230 /* Handle floating point regs, allowing spaces in the (i) part. */
4231 if (r
== i386_regtab
/* %st is first entry of table */)
4233 if (is_space_char (*s
))
4238 if (is_space_char (*s
))
4240 if (*s
>= '0' && *s
<= '7')
4242 r
= &i386_float_regtab
[*s
- '0'];
4244 if (is_space_char (*s
))
4252 /* We have "%st(" then garbage */
4253 return (const reg_entry
*) NULL
;
4260 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4261 const char *md_shortopts
= "kVQ:sq";
4263 const char *md_shortopts
= "q";
4265 struct option md_longopts
[] = {
4266 {NULL
, no_argument
, NULL
, 0}
4268 size_t md_longopts_size
= sizeof (md_longopts
);
4271 md_parse_option (c
, arg
)
4273 char *arg ATTRIBUTE_UNUSED
;
4281 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4282 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4283 should be emitted or not. FIXME: Not implemented. */
4287 /* -V: SVR4 argument to print version ID. */
4289 print_version_id ();
4292 /* -k: Ignore for FreeBSD compatibility. */
4297 /* -s: On i386 Solaris, this tells the native assembler to use
4298 .stab instead of .stab.excl. We always use .stab anyhow. */
4309 md_show_usage (stream
)
4312 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4313 fprintf (stream
, _("\
4315 -V print assembler version number\n\
4317 -q quieten some warnings\n\
4320 fprintf (stream
, _("\
4321 -q quieten some warnings\n"));
4325 #ifdef BFD_ASSEMBLER
4326 #if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \
4327 || (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \
4328 || (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)))
4330 /* Pick the target format to use. */
4333 i386_target_format ()
4335 switch (OUTPUT_FLAVOR
)
4337 #ifdef OBJ_MAYBE_AOUT
4338 case bfd_target_aout_flavour
:
4339 return AOUT_TARGET_FORMAT
;
4341 #ifdef OBJ_MAYBE_COFF
4342 case bfd_target_coff_flavour
:
4345 #ifdef OBJ_MAYBE_ELF
4346 case bfd_target_elf_flavour
:
4347 return "elf32-i386";
4355 #endif /* OBJ_MAYBE_ more than one */
4356 #endif /* BFD_ASSEMBLER */
4359 md_undefined_symbol (name
)
4362 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4363 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4364 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4365 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4369 if (symbol_find (name
))
4370 as_bad (_("GOT already in symbol table"));
4371 GOT_symbol
= symbol_new (name
, undefined_section
,
4372 (valueT
) 0, &zero_address_frag
);
4379 /* Round up a section size to the appropriate boundary. */
4381 md_section_align (segment
, size
)
4382 segT segment ATTRIBUTE_UNUSED
;
4385 #ifdef BFD_ASSEMBLER
4386 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4387 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4389 /* For a.out, force the section size to be aligned. If we don't do
4390 this, BFD will align it for us, but it will not write out the
4391 final bytes of the section. This may be a bug in BFD, but it is
4392 easier to fix it here since that is how the other a.out targets
4396 align
= bfd_get_section_alignment (stdoutput
, segment
);
4397 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4405 /* On the i386, PC-relative offsets are relative to the start of the
4406 next instruction. That is, the address of the offset, plus its
4407 size, since the offset is always the last part of the insn. */
4410 md_pcrel_from (fixP
)
4413 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4420 int ignore ATTRIBUTE_UNUSED
;
4424 temp
= get_absolute_expression ();
4425 subseg_set (bss_section
, (subsegT
) temp
);
4426 demand_empty_rest_of_line ();
4432 #ifdef BFD_ASSEMBLER
4435 i386_validate_fix (fixp
)
4438 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
4440 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
4446 tc_gen_reloc (section
, fixp
)
4447 asection
*section ATTRIBUTE_UNUSED
;
4451 bfd_reloc_code_real_type code
;
4453 switch (fixp
->fx_r_type
)
4455 case BFD_RELOC_386_PLT32
:
4456 case BFD_RELOC_386_GOT32
:
4457 case BFD_RELOC_386_GOTOFF
:
4458 case BFD_RELOC_386_GOTPC
:
4460 case BFD_RELOC_VTABLE_ENTRY
:
4461 case BFD_RELOC_VTABLE_INHERIT
:
4462 code
= fixp
->fx_r_type
;
4467 switch (fixp
->fx_size
)
4470 as_bad (_("can not do %d byte pc-relative relocation"),
4472 code
= BFD_RELOC_32_PCREL
;
4474 case 1: code
= BFD_RELOC_8_PCREL
; break;
4475 case 2: code
= BFD_RELOC_16_PCREL
; break;
4476 case 4: code
= BFD_RELOC_32_PCREL
; break;
4481 switch (fixp
->fx_size
)
4484 as_bad (_("can not do %d byte relocation"), fixp
->fx_size
);
4485 code
= BFD_RELOC_32
;
4487 case 1: code
= BFD_RELOC_8
; break;
4488 case 2: code
= BFD_RELOC_16
; break;
4489 case 4: code
= BFD_RELOC_32
; break;
4495 if (code
== BFD_RELOC_32
4497 && fixp
->fx_addsy
== GOT_symbol
)
4498 code
= BFD_RELOC_386_GOTPC
;
4500 rel
= (arelent
*) xmalloc (sizeof (arelent
));
4501 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4502 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4504 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4505 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4506 vtable entry to be used in the relocation's section offset. */
4507 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4508 rel
->address
= fixp
->fx_offset
;
4511 rel
->addend
= fixp
->fx_addnumber
;
4515 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4516 if (rel
->howto
== NULL
)
4518 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4519 _("cannot represent relocation type %s"),
4520 bfd_get_reloc_code_name (code
));
4521 /* Set howto to a garbage value so that we can keep going. */
4522 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
4523 assert (rel
->howto
!= NULL
);
4529 #else /* ! BFD_ASSEMBLER */
4531 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4533 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4536 relax_addressT segment_address_in_file
;
4539 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4540 * Out: GNU LD relocation length code: 0, 1, or 2.
4543 static const unsigned char nbytes_r_length
[] = {42, 0, 1, 42, 2};
4546 know (fixP
->fx_addsy
!= NULL
);
4548 md_number_to_chars (where
,
4549 (valueT
) (fixP
->fx_frag
->fr_address
4550 + fixP
->fx_where
- segment_address_in_file
),
4553 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4554 ? S_GET_TYPE (fixP
->fx_addsy
)
4555 : fixP
->fx_addsy
->sy_number
);
4557 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
4558 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4559 where
[4] = r_symbolnum
& 0x0ff;
4560 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
4561 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
4562 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
4565 #endif /* OBJ_AOUT or OBJ_BOUT */
4567 #if defined (I386COFF)
4570 tc_coff_fix2rtype (fixP
)
4573 if (fixP
->fx_r_type
== R_IMAGEBASE
)
4576 return (fixP
->fx_pcrel
?
4577 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
4578 fixP
->fx_size
== 2 ? R_PCRWORD
:
4580 (fixP
->fx_size
== 1 ? R_RELBYTE
:
4581 fixP
->fx_size
== 2 ? R_RELWORD
:
4586 tc_coff_sizemachdep (frag
)
4590 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
4595 #endif /* I386COFF */
4597 #endif /* ! BFD_ASSEMBLER */
4599 /* end of tc-i386.c */