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x86: drop VexImmExt
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
20
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
27
28 #include "as.h"
29 #include "safe-ctype.h"
30 #include "subsegs.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
35
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
38 #endif
39
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
42 #endif
43
44 #ifndef DEFAULT_ARCH
45 #define DEFAULT_ARCH "i386"
46 #endif
47
48 #ifndef INLINE
49 #if __GNUC__ >= 2
50 #define INLINE __inline__
51 #else
52 #define INLINE
53 #endif
54 #endif
55
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
61 #define WAIT_PREFIX 0
62 #define SEG_PREFIX 1
63 #define ADDR_PREFIX 2
64 #define DATA_PREFIX 3
65 #define REP_PREFIX 4
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
68 #define LOCK_PREFIX 5
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
71
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
76
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
85 in instructions. */
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
87
88 #define END_OF_INSN '\0'
89
90 /*
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
95 END.
96 */
97 typedef struct
98 {
99 const insn_template *start;
100 const insn_template *end;
101 }
102 templates;
103
104 /* 386 operand encoding bytes: see 386 book for details of this. */
105 typedef struct
106 {
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
110 }
111 modrm_byte;
112
113 /* x86-64 extension prefix. */
114 typedef int rex_byte;
115
116 /* 386 opcode byte to code indirect addressing. */
117 typedef struct
118 {
119 unsigned base;
120 unsigned index;
121 unsigned scale;
122 }
123 sib_byte;
124
125 /* x86 arch names, types and features */
126 typedef struct
127 {
128 const char *name; /* arch name */
129 unsigned int len; /* arch string length */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132 unsigned int skip; /* show_arch should skip this. */
133 }
134 arch_entry;
135
136 /* Used to turn off indicated flags. */
137 typedef struct
138 {
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
142 }
143 noarch_entry;
144
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
153 #ifdef TE_PE
154 static void pe_directive_secrel (int);
155 #endif
156 static void signed_cons (int);
157 static char *output_invalid (int c);
158 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
159 const char *);
160 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
161 const char *);
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS *);
165 static int i386_intel_parse_name (const char *, expressionS *);
166 static const reg_entry *parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template *match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry *build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS *, offsetT);
185 static void output_disp (fragS *, offsetT);
186 #ifndef I386COFF
187 static void s_bss (int);
188 #endif
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED);
191 #endif
192
193 static const char *default_arch = DEFAULT_ARCH;
194
195 /* This struct describes rounding control and SAE in the instruction. */
196 struct RC_Operation
197 {
198 enum rc_type
199 {
200 rne = 0,
201 rd,
202 ru,
203 rz,
204 saeonly
205 } type;
206 int operand;
207 };
208
209 static struct RC_Operation rc_op;
210
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
215 {
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
219 int operand;
220 };
221
222 static struct Mask_Operation mask_op;
223
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
225 broadcast factor. */
226 struct Broadcast_Operation
227 {
228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
229 int type;
230
231 /* Index of broadcasted operand. */
232 int operand;
233 };
234
235 static struct Broadcast_Operation broadcast_op;
236
237 /* VEX prefix. */
238 typedef struct
239 {
240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
242 unsigned int length;
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
245 } vex_prefix;
246
247 /* 'md_assemble ()' gathers together information and puts it into a
248 i386_insn. */
249
250 union i386_op
251 {
252 expressionS *disps;
253 expressionS *imms;
254 const reg_entry *regs;
255 };
256
257 enum i386_error
258 {
259 operand_size_mismatch,
260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
264 bad_imm4,
265 unsupported_with_intel_mnemonic,
266 unsupported_syntax,
267 unsupported,
268 invalid_vsib_address,
269 invalid_vector_register_set,
270 unsupported_vector_index_register,
271 unsupported_broadcast,
272 broadcast_not_on_src_operand,
273 broadcast_needed,
274 unsupported_masking,
275 mask_not_on_destination,
276 no_default_mask,
277 unsupported_rc_sae,
278 rc_sae_operand_not_last_imm,
279 invalid_register_operand,
280 };
281
282 struct _i386_insn
283 {
284 /* TM holds the template for the insn were currently assembling. */
285 insn_template tm;
286
287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
289 char suffix;
290
291 /* OPERANDS gives the number of given operands. */
292 unsigned int operands;
293
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
296 operands. */
297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
298
299 /* TYPES [i] is the type (see above #defines) which tells us how to
300 use OP[i] for the corresponding operand. */
301 i386_operand_type types[MAX_OPERANDS];
302
303 /* Displacement expression, immediate expression, or register for each
304 operand. */
305 union i386_op op[MAX_OPERANDS];
306
307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309 #define Operand_PCrel 1
310
311 /* Relocation type for operand */
312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
313
314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
319
320 /* SEG gives the seg_entries of this insn. They are zero unless
321 explicit segment overrides are given. */
322 const seg_entry *seg[2];
323
324 /* Copied first memory operand string, for re-checking. */
325 char *memop1_string;
326
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes;
330 unsigned char prefix[MAX_PREFIXES];
331
332 /* RM and SIB are the modrm byte and the sib byte where the
333 addressing modes of this insn are encoded. */
334 modrm_byte rm;
335 rex_byte rex;
336 rex_byte vrex;
337 sib_byte sib;
338 vex_prefix vex;
339
340 /* Masking attributes. */
341 struct Mask_Operation *mask;
342
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation *rounding;
345
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation *broadcast;
348
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift;
351
352 /* Prefer load or store in encoding. */
353 enum
354 {
355 dir_encoding_default = 0,
356 dir_encoding_load,
357 dir_encoding_store
358 } dir_encoding;
359
360 /* Prefer 8bit or 32bit displacement in encoding. */
361 enum
362 {
363 disp_encoding_default = 0,
364 disp_encoding_8bit,
365 disp_encoding_32bit
366 } disp_encoding;
367
368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding;
370
371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize;
373
374 /* How to encode vector instructions. */
375 enum
376 {
377 vex_encoding_default = 0,
378 vex_encoding_vex2,
379 vex_encoding_vex3,
380 vex_encoding_evex
381 } vec_encoding;
382
383 /* REP prefix. */
384 const char *rep_prefix;
385
386 /* HLE prefix. */
387 const char *hle_prefix;
388
389 /* Have BND prefix. */
390 const char *bnd_prefix;
391
392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix;
394
395 /* Error message. */
396 enum i386_error error;
397 };
398
399 typedef struct _i386_insn i386_insn;
400
401 /* Link RC type with corresponding string, that'll be looked for in
402 asm. */
403 struct RC_name
404 {
405 enum rc_type type;
406 const char *name;
407 unsigned int len;
408 };
409
410 static const struct RC_name RC_NamesTable[] =
411 {
412 { rne, STRING_COMMA_LEN ("rn-sae") },
413 { rd, STRING_COMMA_LEN ("rd-sae") },
414 { ru, STRING_COMMA_LEN ("ru-sae") },
415 { rz, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly, STRING_COMMA_LEN ("sae") },
417 };
418
419 /* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
421 const char extra_symbol_chars[] = "*%-([{}"
422 #ifdef LEX_AT
423 "@"
424 #endif
425 #ifdef LEX_QM
426 "?"
427 #endif
428 ;
429
430 #if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
432 && !defined (TE_GNU) \
433 && !defined (TE_LINUX) \
434 && !defined (TE_NACL) \
435 && !defined (TE_FreeBSD) \
436 && !defined (TE_DragonFly) \
437 && !defined (TE_NetBSD)))
438 /* This array holds the chars that always start a comment. If the
439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441 const char *i386_comment_chars = "#/";
442 #define SVR4_COMMENT_CHARS 1
443 #define PREFIX_SEPARATOR '\\'
444
445 #else
446 const char *i386_comment_chars = "#";
447 #define PREFIX_SEPARATOR '/'
448 #endif
449
450 /* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
454 first line of the input file. This is because the compiler outputs
455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
457 '/' isn't otherwise defined. */
458 const char line_comment_chars[] = "#/";
459
460 const char line_separator_chars[] = ";";
461
462 /* Chars that can be used to separate mant from exp in floating point
463 nums. */
464 const char EXP_CHARS[] = "eE";
465
466 /* Chars that mean this number is a floating point constant
467 As in 0f12.456
468 or 0d1.2345e12. */
469 const char FLT_CHARS[] = "fFdDxX";
470
471 /* Tables for lexical analysis. */
472 static char mnemonic_chars[256];
473 static char register_chars[256];
474 static char operand_chars[256];
475 static char identifier_chars[256];
476 static char digit_chars[256];
477
478 /* Lexical macros. */
479 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480 #define is_operand_char(x) (operand_chars[(unsigned char) x])
481 #define is_register_char(x) (register_chars[(unsigned char) x])
482 #define is_space_char(x) ((x) == ' ')
483 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484 #define is_digit_char(x) (digit_chars[(unsigned char) x])
485
486 /* All non-digit non-letter characters that may occur in an operand. */
487 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
488
489 /* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
492 assembler instruction). */
493 static char save_stack[32];
494 static char *save_stack_p;
495 #define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497 #define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
499
500 /* The instruction we're assembling. */
501 static i386_insn i;
502
503 /* Possible templates for current insn. */
504 static const templates *current_templates;
505
506 /* Per instruction expressionS buffers: max displacements & immediates. */
507 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
508 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
509
510 /* Current operand we are working on. */
511 static int this_operand = -1;
512
513 /* We support four different modes. FLAG_CODE variable is used to distinguish
514 these. */
515
516 enum flag_code {
517 CODE_32BIT,
518 CODE_16BIT,
519 CODE_64BIT };
520
521 static enum flag_code flag_code;
522 static unsigned int object_64bit;
523 static unsigned int disallow_64bit_reloc;
524 static int use_rela_relocations = 0;
525
526 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
529
530 /* The ELF ABI to use. */
531 enum x86_elf_abi
532 {
533 I386_ABI,
534 X86_64_ABI,
535 X86_64_X32_ABI
536 };
537
538 static enum x86_elf_abi x86_elf_abi = I386_ABI;
539 #endif
540
541 #if defined (TE_PE) || defined (TE_PEP)
542 /* Use big object file format. */
543 static int use_big_obj = 0;
544 #endif
545
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 /* 1 if generating code for a shared library. */
548 static int shared = 0;
549 #endif
550
551 /* 1 for intel syntax,
552 0 if att syntax. */
553 static int intel_syntax = 0;
554
555 /* 1 for Intel64 ISA,
556 0 if AMD64 ISA. */
557 static int intel64;
558
559 /* 1 for intel mnemonic,
560 0 if att mnemonic. */
561 static int intel_mnemonic = !SYSV386_COMPAT;
562
563 /* 1 if pseudo registers are permitted. */
564 static int allow_pseudo_reg = 0;
565
566 /* 1 if register prefix % not required. */
567 static int allow_naked_reg = 0;
568
569 /* 1 if the assembler should add BND prefix for all control-transferring
570 instructions supporting it, even if this prefix wasn't specified
571 explicitly. */
572 static int add_bnd_prefix = 0;
573
574 /* 1 if pseudo index register, eiz/riz, is allowed . */
575 static int allow_index_reg = 0;
576
577 /* 1 if the assembler should ignore LOCK prefix, even if it was
578 specified explicitly. */
579 static int omit_lock_prefix = 0;
580
581 /* 1 if the assembler should encode lfence, mfence, and sfence as
582 "lock addl $0, (%{re}sp)". */
583 static int avoid_fence = 0;
584
585 /* 1 if the assembler should generate relax relocations. */
586
587 static int generate_relax_relocations
588 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
589
590 static enum check_kind
591 {
592 check_none = 0,
593 check_warning,
594 check_error
595 }
596 sse_check, operand_check = check_warning;
597
598 /* Optimization:
599 1. Clear the REX_W bit with register operand if possible.
600 2. Above plus use 128bit vector instruction to clear the full vector
601 register.
602 */
603 static int optimize = 0;
604
605 /* Optimization:
606 1. Clear the REX_W bit with register operand if possible.
607 2. Above plus use 128bit vector instruction to clear the full vector
608 register.
609 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
610 "testb $imm7,%r8".
611 */
612 static int optimize_for_space = 0;
613
614 /* Register prefix used for error message. */
615 static const char *register_prefix = "%";
616
617 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
618 leave, push, and pop instructions so that gcc has the same stack
619 frame as in 32 bit mode. */
620 static char stackop_size = '\0';
621
622 /* Non-zero to optimize code alignment. */
623 int optimize_align_code = 1;
624
625 /* Non-zero to quieten some warnings. */
626 static int quiet_warnings = 0;
627
628 /* CPU name. */
629 static const char *cpu_arch_name = NULL;
630 static char *cpu_sub_arch_name = NULL;
631
632 /* CPU feature flags. */
633 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
634
635 /* If we have selected a cpu we are generating instructions for. */
636 static int cpu_arch_tune_set = 0;
637
638 /* Cpu we are generating instructions for. */
639 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
640
641 /* CPU feature flags of cpu we are generating instructions for. */
642 static i386_cpu_flags cpu_arch_tune_flags;
643
644 /* CPU instruction set architecture used. */
645 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
646
647 /* CPU feature flags of instruction set architecture used. */
648 i386_cpu_flags cpu_arch_isa_flags;
649
650 /* If set, conditional jumps are not automatically promoted to handle
651 larger than a byte offset. */
652 static unsigned int no_cond_jump_promotion = 0;
653
654 /* Encode SSE instructions with VEX prefix. */
655 static unsigned int sse2avx;
656
657 /* Encode scalar AVX instructions with specific vector length. */
658 static enum
659 {
660 vex128 = 0,
661 vex256
662 } avxscalar;
663
664 /* Encode scalar EVEX LIG instructions with specific vector length. */
665 static enum
666 {
667 evexl128 = 0,
668 evexl256,
669 evexl512
670 } evexlig;
671
672 /* Encode EVEX WIG instructions with specific evex.w. */
673 static enum
674 {
675 evexw0 = 0,
676 evexw1
677 } evexwig;
678
679 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
680 static enum rc_type evexrcig = rne;
681
682 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
683 static symbolS *GOT_symbol;
684
685 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
686 unsigned int x86_dwarf2_return_column;
687
688 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
689 int x86_cie_data_alignment;
690
691 /* Interface to relax_segment.
692 There are 3 major relax states for 386 jump insns because the
693 different types of jumps add different sizes to frags when we're
694 figuring out what sort of jump to choose to reach a given label. */
695
696 /* Types. */
697 #define UNCOND_JUMP 0
698 #define COND_JUMP 1
699 #define COND_JUMP86 2
700
701 /* Sizes. */
702 #define CODE16 1
703 #define SMALL 0
704 #define SMALL16 (SMALL | CODE16)
705 #define BIG 2
706 #define BIG16 (BIG | CODE16)
707
708 #ifndef INLINE
709 #ifdef __GNUC__
710 #define INLINE __inline__
711 #else
712 #define INLINE
713 #endif
714 #endif
715
716 #define ENCODE_RELAX_STATE(type, size) \
717 ((relax_substateT) (((type) << 2) | (size)))
718 #define TYPE_FROM_RELAX_STATE(s) \
719 ((s) >> 2)
720 #define DISP_SIZE_FROM_RELAX_STATE(s) \
721 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
722
723 /* This table is used by relax_frag to promote short jumps to long
724 ones where necessary. SMALL (short) jumps may be promoted to BIG
725 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
726 don't allow a short jump in a 32 bit code segment to be promoted to
727 a 16 bit offset jump because it's slower (requires data size
728 prefix), and doesn't work, unless the destination is in the bottom
729 64k of the code segment (The top 16 bits of eip are zeroed). */
730
731 const relax_typeS md_relax_table[] =
732 {
733 /* The fields are:
734 1) most positive reach of this state,
735 2) most negative reach of this state,
736 3) how many bytes this mode will have in the variable part of the frag
737 4) which index into the table to try if we can't fit into this one. */
738
739 /* UNCOND_JUMP states. */
740 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
742 /* dword jmp adds 4 bytes to frag:
743 0 extra opcode bytes, 4 displacement bytes. */
744 {0, 0, 4, 0},
745 /* word jmp adds 2 byte2 to frag:
746 0 extra opcode bytes, 2 displacement bytes. */
747 {0, 0, 2, 0},
748
749 /* COND_JUMP states. */
750 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
752 /* dword conditionals adds 5 bytes to frag:
753 1 extra opcode byte, 4 displacement bytes. */
754 {0, 0, 5, 0},
755 /* word conditionals add 3 bytes to frag:
756 1 extra opcode byte, 2 displacement bytes. */
757 {0, 0, 3, 0},
758
759 /* COND_JUMP86 states. */
760 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
762 /* dword conditionals adds 5 bytes to frag:
763 1 extra opcode byte, 4 displacement bytes. */
764 {0, 0, 5, 0},
765 /* word conditionals add 4 bytes to frag:
766 1 displacement byte and a 3 byte long branch insn. */
767 {0, 0, 4, 0}
768 };
769
770 static const arch_entry cpu_arch[] =
771 {
772 /* Do not replace the first two entries - i386_target_format()
773 relies on them being there in this order. */
774 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
775 CPU_GENERIC32_FLAGS, 0 },
776 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
777 CPU_GENERIC64_FLAGS, 0 },
778 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
779 CPU_NONE_FLAGS, 0 },
780 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
781 CPU_I186_FLAGS, 0 },
782 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
783 CPU_I286_FLAGS, 0 },
784 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
785 CPU_I386_FLAGS, 0 },
786 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
787 CPU_I486_FLAGS, 0 },
788 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
789 CPU_I586_FLAGS, 0 },
790 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
791 CPU_I686_FLAGS, 0 },
792 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
793 CPU_I586_FLAGS, 0 },
794 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
795 CPU_PENTIUMPRO_FLAGS, 0 },
796 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
797 CPU_P2_FLAGS, 0 },
798 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
799 CPU_P3_FLAGS, 0 },
800 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
801 CPU_P4_FLAGS, 0 },
802 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
803 CPU_CORE_FLAGS, 0 },
804 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
805 CPU_NOCONA_FLAGS, 0 },
806 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
807 CPU_CORE_FLAGS, 1 },
808 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
809 CPU_CORE_FLAGS, 0 },
810 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
811 CPU_CORE2_FLAGS, 1 },
812 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
813 CPU_CORE2_FLAGS, 0 },
814 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
815 CPU_COREI7_FLAGS, 0 },
816 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
817 CPU_L1OM_FLAGS, 0 },
818 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
819 CPU_K1OM_FLAGS, 0 },
820 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
821 CPU_IAMCU_FLAGS, 0 },
822 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
823 CPU_K6_FLAGS, 0 },
824 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
825 CPU_K6_2_FLAGS, 0 },
826 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
827 CPU_ATHLON_FLAGS, 0 },
828 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
829 CPU_K8_FLAGS, 1 },
830 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
831 CPU_K8_FLAGS, 0 },
832 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
833 CPU_K8_FLAGS, 0 },
834 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
835 CPU_AMDFAM10_FLAGS, 0 },
836 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
837 CPU_BDVER1_FLAGS, 0 },
838 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
839 CPU_BDVER2_FLAGS, 0 },
840 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
841 CPU_BDVER3_FLAGS, 0 },
842 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
843 CPU_BDVER4_FLAGS, 0 },
844 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
845 CPU_ZNVER1_FLAGS, 0 },
846 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
847 CPU_BTVER1_FLAGS, 0 },
848 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
849 CPU_BTVER2_FLAGS, 0 },
850 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
851 CPU_8087_FLAGS, 0 },
852 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
853 CPU_287_FLAGS, 0 },
854 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
855 CPU_387_FLAGS, 0 },
856 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
857 CPU_687_FLAGS, 0 },
858 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
859 CPU_MMX_FLAGS, 0 },
860 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
861 CPU_SSE_FLAGS, 0 },
862 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
863 CPU_SSE2_FLAGS, 0 },
864 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
865 CPU_SSE3_FLAGS, 0 },
866 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
867 CPU_SSSE3_FLAGS, 0 },
868 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
869 CPU_SSE4_1_FLAGS, 0 },
870 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
871 CPU_SSE4_2_FLAGS, 0 },
872 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
873 CPU_SSE4_2_FLAGS, 0 },
874 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
875 CPU_AVX_FLAGS, 0 },
876 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
877 CPU_AVX2_FLAGS, 0 },
878 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
879 CPU_AVX512F_FLAGS, 0 },
880 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
881 CPU_AVX512CD_FLAGS, 0 },
882 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
883 CPU_AVX512ER_FLAGS, 0 },
884 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
885 CPU_AVX512PF_FLAGS, 0 },
886 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
887 CPU_AVX512DQ_FLAGS, 0 },
888 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
889 CPU_AVX512BW_FLAGS, 0 },
890 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
891 CPU_AVX512VL_FLAGS, 0 },
892 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
893 CPU_VMX_FLAGS, 0 },
894 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
895 CPU_VMFUNC_FLAGS, 0 },
896 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
897 CPU_SMX_FLAGS, 0 },
898 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
899 CPU_XSAVE_FLAGS, 0 },
900 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
901 CPU_XSAVEOPT_FLAGS, 0 },
902 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
903 CPU_XSAVEC_FLAGS, 0 },
904 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
905 CPU_XSAVES_FLAGS, 0 },
906 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
907 CPU_AES_FLAGS, 0 },
908 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
909 CPU_PCLMUL_FLAGS, 0 },
910 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
911 CPU_PCLMUL_FLAGS, 1 },
912 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
913 CPU_FSGSBASE_FLAGS, 0 },
914 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
915 CPU_RDRND_FLAGS, 0 },
916 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
917 CPU_F16C_FLAGS, 0 },
918 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
919 CPU_BMI2_FLAGS, 0 },
920 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
921 CPU_FMA_FLAGS, 0 },
922 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
923 CPU_FMA4_FLAGS, 0 },
924 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
925 CPU_XOP_FLAGS, 0 },
926 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
927 CPU_LWP_FLAGS, 0 },
928 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
929 CPU_MOVBE_FLAGS, 0 },
930 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
931 CPU_CX16_FLAGS, 0 },
932 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
933 CPU_EPT_FLAGS, 0 },
934 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
935 CPU_LZCNT_FLAGS, 0 },
936 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
937 CPU_HLE_FLAGS, 0 },
938 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
939 CPU_RTM_FLAGS, 0 },
940 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
941 CPU_INVPCID_FLAGS, 0 },
942 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
943 CPU_CLFLUSH_FLAGS, 0 },
944 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
945 CPU_NOP_FLAGS, 0 },
946 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
947 CPU_SYSCALL_FLAGS, 0 },
948 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
949 CPU_RDTSCP_FLAGS, 0 },
950 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
951 CPU_3DNOW_FLAGS, 0 },
952 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
953 CPU_3DNOWA_FLAGS, 0 },
954 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
955 CPU_PADLOCK_FLAGS, 0 },
956 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
957 CPU_SVME_FLAGS, 1 },
958 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
959 CPU_SVME_FLAGS, 0 },
960 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
961 CPU_SSE4A_FLAGS, 0 },
962 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
963 CPU_ABM_FLAGS, 0 },
964 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
965 CPU_BMI_FLAGS, 0 },
966 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
967 CPU_TBM_FLAGS, 0 },
968 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
969 CPU_ADX_FLAGS, 0 },
970 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
971 CPU_RDSEED_FLAGS, 0 },
972 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
973 CPU_PRFCHW_FLAGS, 0 },
974 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
975 CPU_SMAP_FLAGS, 0 },
976 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
977 CPU_MPX_FLAGS, 0 },
978 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
979 CPU_SHA_FLAGS, 0 },
980 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
981 CPU_CLFLUSHOPT_FLAGS, 0 },
982 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
983 CPU_PREFETCHWT1_FLAGS, 0 },
984 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
985 CPU_SE1_FLAGS, 0 },
986 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
987 CPU_CLWB_FLAGS, 0 },
988 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
989 CPU_AVX512IFMA_FLAGS, 0 },
990 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
991 CPU_AVX512VBMI_FLAGS, 0 },
992 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
993 CPU_AVX512_4FMAPS_FLAGS, 0 },
994 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
995 CPU_AVX512_4VNNIW_FLAGS, 0 },
996 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
997 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
998 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
999 CPU_AVX512_VBMI2_FLAGS, 0 },
1000 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1001 CPU_AVX512_VNNI_FLAGS, 0 },
1002 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1003 CPU_AVX512_BITALG_FLAGS, 0 },
1004 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1005 CPU_CLZERO_FLAGS, 0 },
1006 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1007 CPU_MWAITX_FLAGS, 0 },
1008 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1009 CPU_OSPKE_FLAGS, 0 },
1010 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1011 CPU_RDPID_FLAGS, 0 },
1012 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1013 CPU_PTWRITE_FLAGS, 0 },
1014 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1015 CPU_IBT_FLAGS, 0 },
1016 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1017 CPU_SHSTK_FLAGS, 0 },
1018 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1019 CPU_GFNI_FLAGS, 0 },
1020 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1021 CPU_VAES_FLAGS, 0 },
1022 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1023 CPU_VPCLMULQDQ_FLAGS, 0 },
1024 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1025 CPU_WBNOINVD_FLAGS, 0 },
1026 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1027 CPU_PCONFIG_FLAGS, 0 },
1028 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1029 CPU_WAITPKG_FLAGS, 0 },
1030 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
1031 CPU_CLDEMOTE_FLAGS, 0 },
1032 };
1033
1034 static const noarch_entry cpu_noarch[] =
1035 {
1036 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1037 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1038 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1039 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1040 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1041 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1042 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1043 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1044 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1045 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1046 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1047 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1048 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1049 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1050 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1051 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1052 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1053 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1054 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1055 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1062 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1063 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1064 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1065 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1066 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1067 };
1068
1069 #ifdef I386COFF
1070 /* Like s_lcomm_internal in gas/read.c but the alignment string
1071 is allowed to be optional. */
1072
1073 static symbolS *
1074 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1075 {
1076 addressT align = 0;
1077
1078 SKIP_WHITESPACE ();
1079
1080 if (needs_align
1081 && *input_line_pointer == ',')
1082 {
1083 align = parse_align (needs_align - 1);
1084
1085 if (align == (addressT) -1)
1086 return NULL;
1087 }
1088 else
1089 {
1090 if (size >= 8)
1091 align = 3;
1092 else if (size >= 4)
1093 align = 2;
1094 else if (size >= 2)
1095 align = 1;
1096 else
1097 align = 0;
1098 }
1099
1100 bss_alloc (symbolP, size, align);
1101 return symbolP;
1102 }
1103
1104 static void
1105 pe_lcomm (int needs_align)
1106 {
1107 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1108 }
1109 #endif
1110
1111 const pseudo_typeS md_pseudo_table[] =
1112 {
1113 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1114 {"align", s_align_bytes, 0},
1115 #else
1116 {"align", s_align_ptwo, 0},
1117 #endif
1118 {"arch", set_cpu_arch, 0},
1119 #ifndef I386COFF
1120 {"bss", s_bss, 0},
1121 #else
1122 {"lcomm", pe_lcomm, 1},
1123 #endif
1124 {"ffloat", float_cons, 'f'},
1125 {"dfloat", float_cons, 'd'},
1126 {"tfloat", float_cons, 'x'},
1127 {"value", cons, 2},
1128 {"slong", signed_cons, 4},
1129 {"noopt", s_ignore, 0},
1130 {"optim", s_ignore, 0},
1131 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1132 {"code16", set_code_flag, CODE_16BIT},
1133 {"code32", set_code_flag, CODE_32BIT},
1134 #ifdef BFD64
1135 {"code64", set_code_flag, CODE_64BIT},
1136 #endif
1137 {"intel_syntax", set_intel_syntax, 1},
1138 {"att_syntax", set_intel_syntax, 0},
1139 {"intel_mnemonic", set_intel_mnemonic, 1},
1140 {"att_mnemonic", set_intel_mnemonic, 0},
1141 {"allow_index_reg", set_allow_index_reg, 1},
1142 {"disallow_index_reg", set_allow_index_reg, 0},
1143 {"sse_check", set_check, 0},
1144 {"operand_check", set_check, 1},
1145 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1146 {"largecomm", handle_large_common, 0},
1147 #else
1148 {"file", dwarf2_directive_file, 0},
1149 {"loc", dwarf2_directive_loc, 0},
1150 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1151 #endif
1152 #ifdef TE_PE
1153 {"secrel32", pe_directive_secrel, 0},
1154 #endif
1155 {0, 0, 0}
1156 };
1157
1158 /* For interface with expression (). */
1159 extern char *input_line_pointer;
1160
1161 /* Hash table for instruction mnemonic lookup. */
1162 static struct hash_control *op_hash;
1163
1164 /* Hash table for register lookup. */
1165 static struct hash_control *reg_hash;
1166 \f
1167 /* Various efficient no-op patterns for aligning code labels.
1168 Note: Don't try to assemble the instructions in the comments.
1169 0L and 0w are not legal. */
1170 static const unsigned char f32_1[] =
1171 {0x90}; /* nop */
1172 static const unsigned char f32_2[] =
1173 {0x66,0x90}; /* xchg %ax,%ax */
1174 static const unsigned char f32_3[] =
1175 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1176 static const unsigned char f32_4[] =
1177 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1178 static const unsigned char f32_6[] =
1179 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1180 static const unsigned char f32_7[] =
1181 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1182 static const unsigned char f16_3[] =
1183 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1184 static const unsigned char f16_4[] =
1185 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1186 static const unsigned char jump_disp8[] =
1187 {0xeb}; /* jmp disp8 */
1188 static const unsigned char jump32_disp32[] =
1189 {0xe9}; /* jmp disp32 */
1190 static const unsigned char jump16_disp32[] =
1191 {0x66,0xe9}; /* jmp disp32 */
1192 /* 32-bit NOPs patterns. */
1193 static const unsigned char *const f32_patt[] = {
1194 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1195 };
1196 /* 16-bit NOPs patterns. */
1197 static const unsigned char *const f16_patt[] = {
1198 f32_1, f32_2, f16_3, f16_4
1199 };
1200 /* nopl (%[re]ax) */
1201 static const unsigned char alt_3[] =
1202 {0x0f,0x1f,0x00};
1203 /* nopl 0(%[re]ax) */
1204 static const unsigned char alt_4[] =
1205 {0x0f,0x1f,0x40,0x00};
1206 /* nopl 0(%[re]ax,%[re]ax,1) */
1207 static const unsigned char alt_5[] =
1208 {0x0f,0x1f,0x44,0x00,0x00};
1209 /* nopw 0(%[re]ax,%[re]ax,1) */
1210 static const unsigned char alt_6[] =
1211 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1212 /* nopl 0L(%[re]ax) */
1213 static const unsigned char alt_7[] =
1214 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1215 /* nopl 0L(%[re]ax,%[re]ax,1) */
1216 static const unsigned char alt_8[] =
1217 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1218 /* nopw 0L(%[re]ax,%[re]ax,1) */
1219 static const unsigned char alt_9[] =
1220 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1221 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1222 static const unsigned char alt_10[] =
1223 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1224 /* data16 nopw %cs:0L(%eax,%eax,1) */
1225 static const unsigned char alt_11[] =
1226 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1227 /* 32-bit and 64-bit NOPs patterns. */
1228 static const unsigned char *const alt_patt[] = {
1229 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1230 alt_9, alt_10, alt_11
1231 };
1232
1233 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1234 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1235
1236 static void
1237 i386_output_nops (char *where, const unsigned char *const *patt,
1238 int count, int max_single_nop_size)
1239
1240 {
1241 /* Place the longer NOP first. */
1242 int last;
1243 int offset;
1244 const unsigned char *nops = patt[max_single_nop_size - 1];
1245
1246 /* Use the smaller one if the requsted one isn't available. */
1247 if (nops == NULL)
1248 {
1249 max_single_nop_size--;
1250 nops = patt[max_single_nop_size - 1];
1251 }
1252
1253 last = count % max_single_nop_size;
1254
1255 count -= last;
1256 for (offset = 0; offset < count; offset += max_single_nop_size)
1257 memcpy (where + offset, nops, max_single_nop_size);
1258
1259 if (last)
1260 {
1261 nops = patt[last - 1];
1262 if (nops == NULL)
1263 {
1264 /* Use the smaller one plus one-byte NOP if the needed one
1265 isn't available. */
1266 last--;
1267 nops = patt[last - 1];
1268 memcpy (where + offset, nops, last);
1269 where[offset + last] = *patt[0];
1270 }
1271 else
1272 memcpy (where + offset, nops, last);
1273 }
1274 }
1275
1276 static INLINE int
1277 fits_in_imm7 (offsetT num)
1278 {
1279 return (num & 0x7f) == num;
1280 }
1281
1282 static INLINE int
1283 fits_in_imm31 (offsetT num)
1284 {
1285 return (num & 0x7fffffff) == num;
1286 }
1287
1288 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1289 single NOP instruction LIMIT. */
1290
1291 void
1292 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1293 {
1294 const unsigned char *const *patt = NULL;
1295 int max_single_nop_size;
1296 /* Maximum number of NOPs before switching to jump over NOPs. */
1297 int max_number_of_nops;
1298
1299 switch (fragP->fr_type)
1300 {
1301 case rs_fill_nop:
1302 case rs_align_code:
1303 break;
1304 default:
1305 return;
1306 }
1307
1308 /* We need to decide which NOP sequence to use for 32bit and
1309 64bit. When -mtune= is used:
1310
1311 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1312 PROCESSOR_GENERIC32, f32_patt will be used.
1313 2. For the rest, alt_patt will be used.
1314
1315 When -mtune= isn't used, alt_patt will be used if
1316 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1317 be used.
1318
1319 When -march= or .arch is used, we can't use anything beyond
1320 cpu_arch_isa_flags. */
1321
1322 if (flag_code == CODE_16BIT)
1323 {
1324 patt = f16_patt;
1325 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1326 /* Limit number of NOPs to 2 in 16-bit mode. */
1327 max_number_of_nops = 2;
1328 }
1329 else
1330 {
1331 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1332 {
1333 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1334 switch (cpu_arch_tune)
1335 {
1336 case PROCESSOR_UNKNOWN:
1337 /* We use cpu_arch_isa_flags to check if we SHOULD
1338 optimize with nops. */
1339 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1340 patt = alt_patt;
1341 else
1342 patt = f32_patt;
1343 break;
1344 case PROCESSOR_PENTIUM4:
1345 case PROCESSOR_NOCONA:
1346 case PROCESSOR_CORE:
1347 case PROCESSOR_CORE2:
1348 case PROCESSOR_COREI7:
1349 case PROCESSOR_L1OM:
1350 case PROCESSOR_K1OM:
1351 case PROCESSOR_GENERIC64:
1352 case PROCESSOR_K6:
1353 case PROCESSOR_ATHLON:
1354 case PROCESSOR_K8:
1355 case PROCESSOR_AMDFAM10:
1356 case PROCESSOR_BD:
1357 case PROCESSOR_ZNVER:
1358 case PROCESSOR_BT:
1359 patt = alt_patt;
1360 break;
1361 case PROCESSOR_I386:
1362 case PROCESSOR_I486:
1363 case PROCESSOR_PENTIUM:
1364 case PROCESSOR_PENTIUMPRO:
1365 case PROCESSOR_IAMCU:
1366 case PROCESSOR_GENERIC32:
1367 patt = f32_patt;
1368 break;
1369 }
1370 }
1371 else
1372 {
1373 switch (fragP->tc_frag_data.tune)
1374 {
1375 case PROCESSOR_UNKNOWN:
1376 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1377 PROCESSOR_UNKNOWN. */
1378 abort ();
1379 break;
1380
1381 case PROCESSOR_I386:
1382 case PROCESSOR_I486:
1383 case PROCESSOR_PENTIUM:
1384 case PROCESSOR_IAMCU:
1385 case PROCESSOR_K6:
1386 case PROCESSOR_ATHLON:
1387 case PROCESSOR_K8:
1388 case PROCESSOR_AMDFAM10:
1389 case PROCESSOR_BD:
1390 case PROCESSOR_ZNVER:
1391 case PROCESSOR_BT:
1392 case PROCESSOR_GENERIC32:
1393 /* We use cpu_arch_isa_flags to check if we CAN optimize
1394 with nops. */
1395 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1396 patt = alt_patt;
1397 else
1398 patt = f32_patt;
1399 break;
1400 case PROCESSOR_PENTIUMPRO:
1401 case PROCESSOR_PENTIUM4:
1402 case PROCESSOR_NOCONA:
1403 case PROCESSOR_CORE:
1404 case PROCESSOR_CORE2:
1405 case PROCESSOR_COREI7:
1406 case PROCESSOR_L1OM:
1407 case PROCESSOR_K1OM:
1408 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1409 patt = alt_patt;
1410 else
1411 patt = f32_patt;
1412 break;
1413 case PROCESSOR_GENERIC64:
1414 patt = alt_patt;
1415 break;
1416 }
1417 }
1418
1419 if (patt == f32_patt)
1420 {
1421 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1422 /* Limit number of NOPs to 2 for older processors. */
1423 max_number_of_nops = 2;
1424 }
1425 else
1426 {
1427 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1428 /* Limit number of NOPs to 7 for newer processors. */
1429 max_number_of_nops = 7;
1430 }
1431 }
1432
1433 if (limit == 0)
1434 limit = max_single_nop_size;
1435
1436 if (fragP->fr_type == rs_fill_nop)
1437 {
1438 /* Output NOPs for .nop directive. */
1439 if (limit > max_single_nop_size)
1440 {
1441 as_bad_where (fragP->fr_file, fragP->fr_line,
1442 _("invalid single nop size: %d "
1443 "(expect within [0, %d])"),
1444 limit, max_single_nop_size);
1445 return;
1446 }
1447 }
1448 else
1449 fragP->fr_var = count;
1450
1451 if ((count / max_single_nop_size) > max_number_of_nops)
1452 {
1453 /* Generate jump over NOPs. */
1454 offsetT disp = count - 2;
1455 if (fits_in_imm7 (disp))
1456 {
1457 /* Use "jmp disp8" if possible. */
1458 count = disp;
1459 where[0] = jump_disp8[0];
1460 where[1] = count;
1461 where += 2;
1462 }
1463 else
1464 {
1465 unsigned int size_of_jump;
1466
1467 if (flag_code == CODE_16BIT)
1468 {
1469 where[0] = jump16_disp32[0];
1470 where[1] = jump16_disp32[1];
1471 size_of_jump = 2;
1472 }
1473 else
1474 {
1475 where[0] = jump32_disp32[0];
1476 size_of_jump = 1;
1477 }
1478
1479 count -= size_of_jump + 4;
1480 if (!fits_in_imm31 (count))
1481 {
1482 as_bad_where (fragP->fr_file, fragP->fr_line,
1483 _("jump over nop padding out of range"));
1484 return;
1485 }
1486
1487 md_number_to_chars (where + size_of_jump, count, 4);
1488 where += size_of_jump + 4;
1489 }
1490 }
1491
1492 /* Generate multiple NOPs. */
1493 i386_output_nops (where, patt, count, limit);
1494 }
1495
1496 static INLINE int
1497 operand_type_all_zero (const union i386_operand_type *x)
1498 {
1499 switch (ARRAY_SIZE(x->array))
1500 {
1501 case 3:
1502 if (x->array[2])
1503 return 0;
1504 /* Fall through. */
1505 case 2:
1506 if (x->array[1])
1507 return 0;
1508 /* Fall through. */
1509 case 1:
1510 return !x->array[0];
1511 default:
1512 abort ();
1513 }
1514 }
1515
1516 static INLINE void
1517 operand_type_set (union i386_operand_type *x, unsigned int v)
1518 {
1519 switch (ARRAY_SIZE(x->array))
1520 {
1521 case 3:
1522 x->array[2] = v;
1523 /* Fall through. */
1524 case 2:
1525 x->array[1] = v;
1526 /* Fall through. */
1527 case 1:
1528 x->array[0] = v;
1529 /* Fall through. */
1530 break;
1531 default:
1532 abort ();
1533 }
1534 }
1535
1536 static INLINE int
1537 operand_type_equal (const union i386_operand_type *x,
1538 const union i386_operand_type *y)
1539 {
1540 switch (ARRAY_SIZE(x->array))
1541 {
1542 case 3:
1543 if (x->array[2] != y->array[2])
1544 return 0;
1545 /* Fall through. */
1546 case 2:
1547 if (x->array[1] != y->array[1])
1548 return 0;
1549 /* Fall through. */
1550 case 1:
1551 return x->array[0] == y->array[0];
1552 break;
1553 default:
1554 abort ();
1555 }
1556 }
1557
1558 static INLINE int
1559 cpu_flags_all_zero (const union i386_cpu_flags *x)
1560 {
1561 switch (ARRAY_SIZE(x->array))
1562 {
1563 case 4:
1564 if (x->array[3])
1565 return 0;
1566 /* Fall through. */
1567 case 3:
1568 if (x->array[2])
1569 return 0;
1570 /* Fall through. */
1571 case 2:
1572 if (x->array[1])
1573 return 0;
1574 /* Fall through. */
1575 case 1:
1576 return !x->array[0];
1577 default:
1578 abort ();
1579 }
1580 }
1581
1582 static INLINE int
1583 cpu_flags_equal (const union i386_cpu_flags *x,
1584 const union i386_cpu_flags *y)
1585 {
1586 switch (ARRAY_SIZE(x->array))
1587 {
1588 case 4:
1589 if (x->array[3] != y->array[3])
1590 return 0;
1591 /* Fall through. */
1592 case 3:
1593 if (x->array[2] != y->array[2])
1594 return 0;
1595 /* Fall through. */
1596 case 2:
1597 if (x->array[1] != y->array[1])
1598 return 0;
1599 /* Fall through. */
1600 case 1:
1601 return x->array[0] == y->array[0];
1602 break;
1603 default:
1604 abort ();
1605 }
1606 }
1607
1608 static INLINE int
1609 cpu_flags_check_cpu64 (i386_cpu_flags f)
1610 {
1611 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1612 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1613 }
1614
1615 static INLINE i386_cpu_flags
1616 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1617 {
1618 switch (ARRAY_SIZE (x.array))
1619 {
1620 case 4:
1621 x.array [3] &= y.array [3];
1622 /* Fall through. */
1623 case 3:
1624 x.array [2] &= y.array [2];
1625 /* Fall through. */
1626 case 2:
1627 x.array [1] &= y.array [1];
1628 /* Fall through. */
1629 case 1:
1630 x.array [0] &= y.array [0];
1631 break;
1632 default:
1633 abort ();
1634 }
1635 return x;
1636 }
1637
1638 static INLINE i386_cpu_flags
1639 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1640 {
1641 switch (ARRAY_SIZE (x.array))
1642 {
1643 case 4:
1644 x.array [3] |= y.array [3];
1645 /* Fall through. */
1646 case 3:
1647 x.array [2] |= y.array [2];
1648 /* Fall through. */
1649 case 2:
1650 x.array [1] |= y.array [1];
1651 /* Fall through. */
1652 case 1:
1653 x.array [0] |= y.array [0];
1654 break;
1655 default:
1656 abort ();
1657 }
1658 return x;
1659 }
1660
1661 static INLINE i386_cpu_flags
1662 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1663 {
1664 switch (ARRAY_SIZE (x.array))
1665 {
1666 case 4:
1667 x.array [3] &= ~y.array [3];
1668 /* Fall through. */
1669 case 3:
1670 x.array [2] &= ~y.array [2];
1671 /* Fall through. */
1672 case 2:
1673 x.array [1] &= ~y.array [1];
1674 /* Fall through. */
1675 case 1:
1676 x.array [0] &= ~y.array [0];
1677 break;
1678 default:
1679 abort ();
1680 }
1681 return x;
1682 }
1683
1684 #define CPU_FLAGS_ARCH_MATCH 0x1
1685 #define CPU_FLAGS_64BIT_MATCH 0x2
1686
1687 #define CPU_FLAGS_PERFECT_MATCH \
1688 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1689
1690 /* Return CPU flags match bits. */
1691
1692 static int
1693 cpu_flags_match (const insn_template *t)
1694 {
1695 i386_cpu_flags x = t->cpu_flags;
1696 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1697
1698 x.bitfield.cpu64 = 0;
1699 x.bitfield.cpuno64 = 0;
1700
1701 if (cpu_flags_all_zero (&x))
1702 {
1703 /* This instruction is available on all archs. */
1704 match |= CPU_FLAGS_ARCH_MATCH;
1705 }
1706 else
1707 {
1708 /* This instruction is available only on some archs. */
1709 i386_cpu_flags cpu = cpu_arch_flags;
1710
1711 /* AVX512VL is no standalone feature - match it and then strip it. */
1712 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1713 return match;
1714 x.bitfield.cpuavx512vl = 0;
1715
1716 cpu = cpu_flags_and (x, cpu);
1717 if (!cpu_flags_all_zero (&cpu))
1718 {
1719 if (x.bitfield.cpuavx)
1720 {
1721 /* We need to check a few extra flags with AVX. */
1722 if (cpu.bitfield.cpuavx
1723 && (!t->opcode_modifier.sse2avx || sse2avx)
1724 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1725 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1726 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1727 match |= CPU_FLAGS_ARCH_MATCH;
1728 }
1729 else if (x.bitfield.cpuavx512f)
1730 {
1731 /* We need to check a few extra flags with AVX512F. */
1732 if (cpu.bitfield.cpuavx512f
1733 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1734 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1735 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1736 match |= CPU_FLAGS_ARCH_MATCH;
1737 }
1738 else
1739 match |= CPU_FLAGS_ARCH_MATCH;
1740 }
1741 }
1742 return match;
1743 }
1744
1745 static INLINE i386_operand_type
1746 operand_type_and (i386_operand_type x, i386_operand_type y)
1747 {
1748 switch (ARRAY_SIZE (x.array))
1749 {
1750 case 3:
1751 x.array [2] &= y.array [2];
1752 /* Fall through. */
1753 case 2:
1754 x.array [1] &= y.array [1];
1755 /* Fall through. */
1756 case 1:
1757 x.array [0] &= y.array [0];
1758 break;
1759 default:
1760 abort ();
1761 }
1762 return x;
1763 }
1764
1765 static INLINE i386_operand_type
1766 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1767 {
1768 switch (ARRAY_SIZE (x.array))
1769 {
1770 case 3:
1771 x.array [2] &= ~y.array [2];
1772 /* Fall through. */
1773 case 2:
1774 x.array [1] &= ~y.array [1];
1775 /* Fall through. */
1776 case 1:
1777 x.array [0] &= ~y.array [0];
1778 break;
1779 default:
1780 abort ();
1781 }
1782 return x;
1783 }
1784
1785 static INLINE i386_operand_type
1786 operand_type_or (i386_operand_type x, i386_operand_type y)
1787 {
1788 switch (ARRAY_SIZE (x.array))
1789 {
1790 case 3:
1791 x.array [2] |= y.array [2];
1792 /* Fall through. */
1793 case 2:
1794 x.array [1] |= y.array [1];
1795 /* Fall through. */
1796 case 1:
1797 x.array [0] |= y.array [0];
1798 break;
1799 default:
1800 abort ();
1801 }
1802 return x;
1803 }
1804
1805 static INLINE i386_operand_type
1806 operand_type_xor (i386_operand_type x, i386_operand_type y)
1807 {
1808 switch (ARRAY_SIZE (x.array))
1809 {
1810 case 3:
1811 x.array [2] ^= y.array [2];
1812 /* Fall through. */
1813 case 2:
1814 x.array [1] ^= y.array [1];
1815 /* Fall through. */
1816 case 1:
1817 x.array [0] ^= y.array [0];
1818 break;
1819 default:
1820 abort ();
1821 }
1822 return x;
1823 }
1824
1825 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1826 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1827 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1828 static const i386_operand_type inoutportreg
1829 = OPERAND_TYPE_INOUTPORTREG;
1830 static const i386_operand_type reg16_inoutportreg
1831 = OPERAND_TYPE_REG16_INOUTPORTREG;
1832 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1833 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1834 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1835 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1836 static const i386_operand_type anydisp
1837 = OPERAND_TYPE_ANYDISP;
1838 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1839 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1840 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1841 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1842 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1843 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1844 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1845 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1846 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1847 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1848 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1849 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1850
1851 enum operand_type
1852 {
1853 reg,
1854 imm,
1855 disp,
1856 anymem
1857 };
1858
1859 static INLINE int
1860 operand_type_check (i386_operand_type t, enum operand_type c)
1861 {
1862 switch (c)
1863 {
1864 case reg:
1865 return t.bitfield.reg;
1866
1867 case imm:
1868 return (t.bitfield.imm8
1869 || t.bitfield.imm8s
1870 || t.bitfield.imm16
1871 || t.bitfield.imm32
1872 || t.bitfield.imm32s
1873 || t.bitfield.imm64);
1874
1875 case disp:
1876 return (t.bitfield.disp8
1877 || t.bitfield.disp16
1878 || t.bitfield.disp32
1879 || t.bitfield.disp32s
1880 || t.bitfield.disp64);
1881
1882 case anymem:
1883 return (t.bitfield.disp8
1884 || t.bitfield.disp16
1885 || t.bitfield.disp32
1886 || t.bitfield.disp32s
1887 || t.bitfield.disp64
1888 || t.bitfield.baseindex);
1889
1890 default:
1891 abort ();
1892 }
1893
1894 return 0;
1895 }
1896
1897 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1898 operand J for instruction template T. */
1899
1900 static INLINE int
1901 match_reg_size (const insn_template *t, unsigned int j)
1902 {
1903 return !((i.types[j].bitfield.byte
1904 && !t->operand_types[j].bitfield.byte)
1905 || (i.types[j].bitfield.word
1906 && !t->operand_types[j].bitfield.word)
1907 || (i.types[j].bitfield.dword
1908 && !t->operand_types[j].bitfield.dword)
1909 || (i.types[j].bitfield.qword
1910 && !t->operand_types[j].bitfield.qword)
1911 || (i.types[j].bitfield.tbyte
1912 && !t->operand_types[j].bitfield.tbyte));
1913 }
1914
1915 /* Return 1 if there is no conflict in SIMD register on
1916 operand J for instruction template T. */
1917
1918 static INLINE int
1919 match_simd_size (const insn_template *t, unsigned int j)
1920 {
1921 return !((i.types[j].bitfield.xmmword
1922 && !t->operand_types[j].bitfield.xmmword)
1923 || (i.types[j].bitfield.ymmword
1924 && !t->operand_types[j].bitfield.ymmword)
1925 || (i.types[j].bitfield.zmmword
1926 && !t->operand_types[j].bitfield.zmmword));
1927 }
1928
1929 /* Return 1 if there is no conflict in any size on operand J for
1930 instruction template T. */
1931
1932 static INLINE int
1933 match_mem_size (const insn_template *t, unsigned int j)
1934 {
1935 return (match_reg_size (t, j)
1936 && !((i.types[j].bitfield.unspecified
1937 && !i.broadcast
1938 && !t->operand_types[j].bitfield.unspecified)
1939 || (i.types[j].bitfield.fword
1940 && !t->operand_types[j].bitfield.fword)
1941 /* For scalar opcode templates to allow register and memory
1942 operands at the same time, some special casing is needed
1943 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1944 down-conversion vpmov*. */
1945 || ((t->operand_types[j].bitfield.regsimd
1946 && !t->opcode_modifier.broadcast
1947 && (t->operand_types[j].bitfield.byte
1948 || t->operand_types[j].bitfield.word
1949 || t->operand_types[j].bitfield.dword
1950 || t->operand_types[j].bitfield.qword))
1951 ? (i.types[j].bitfield.xmmword
1952 || i.types[j].bitfield.ymmword
1953 || i.types[j].bitfield.zmmword)
1954 : !match_simd_size(t, j))));
1955 }
1956
1957 /* Return 1 if there is no size conflict on any operands for
1958 instruction template T. */
1959
1960 static INLINE int
1961 operand_size_match (const insn_template *t)
1962 {
1963 unsigned int j;
1964 int match = 1;
1965
1966 /* Don't check jump instructions. */
1967 if (t->opcode_modifier.jump
1968 || t->opcode_modifier.jumpbyte
1969 || t->opcode_modifier.jumpdword
1970 || t->opcode_modifier.jumpintersegment)
1971 return match;
1972
1973 /* Check memory and accumulator operand size. */
1974 for (j = 0; j < i.operands; j++)
1975 {
1976 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1977 && t->operand_types[j].bitfield.anysize)
1978 continue;
1979
1980 if (t->operand_types[j].bitfield.reg
1981 && !match_reg_size (t, j))
1982 {
1983 match = 0;
1984 break;
1985 }
1986
1987 if (t->operand_types[j].bitfield.regsimd
1988 && !match_simd_size (t, j))
1989 {
1990 match = 0;
1991 break;
1992 }
1993
1994 if (t->operand_types[j].bitfield.acc
1995 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
1996 {
1997 match = 0;
1998 break;
1999 }
2000
2001 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
2002 {
2003 match = 0;
2004 break;
2005 }
2006 }
2007
2008 if (match)
2009 return match;
2010 else if (!t->opcode_modifier.d)
2011 {
2012 mismatch:
2013 i.error = operand_size_mismatch;
2014 return 0;
2015 }
2016
2017 /* Check reverse. */
2018 gas_assert (i.operands == 2);
2019
2020 match = 1;
2021 for (j = 0; j < 2; j++)
2022 {
2023 if ((t->operand_types[j].bitfield.reg
2024 || t->operand_types[j].bitfield.acc)
2025 && !match_reg_size (t, j ? 0 : 1))
2026 goto mismatch;
2027
2028 if (i.types[j].bitfield.mem
2029 && !match_mem_size (t, j ? 0 : 1))
2030 goto mismatch;
2031 }
2032
2033 return match;
2034 }
2035
2036 static INLINE int
2037 operand_type_match (i386_operand_type overlap,
2038 i386_operand_type given)
2039 {
2040 i386_operand_type temp = overlap;
2041
2042 temp.bitfield.jumpabsolute = 0;
2043 temp.bitfield.unspecified = 0;
2044 temp.bitfield.byte = 0;
2045 temp.bitfield.word = 0;
2046 temp.bitfield.dword = 0;
2047 temp.bitfield.fword = 0;
2048 temp.bitfield.qword = 0;
2049 temp.bitfield.tbyte = 0;
2050 temp.bitfield.xmmword = 0;
2051 temp.bitfield.ymmword = 0;
2052 temp.bitfield.zmmword = 0;
2053 if (operand_type_all_zero (&temp))
2054 goto mismatch;
2055
2056 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2057 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2058 return 1;
2059
2060 mismatch:
2061 i.error = operand_type_mismatch;
2062 return 0;
2063 }
2064
2065 /* If given types g0 and g1 are registers they must be of the same type
2066 unless the expected operand type register overlap is null.
2067 Memory operand size of certain SIMD instructions is also being checked
2068 here. */
2069
2070 static INLINE int
2071 operand_type_register_match (i386_operand_type g0,
2072 i386_operand_type t0,
2073 i386_operand_type g1,
2074 i386_operand_type t1)
2075 {
2076 if (!g0.bitfield.reg
2077 && !g0.bitfield.regsimd
2078 && (!operand_type_check (g0, anymem)
2079 || g0.bitfield.unspecified
2080 || !t0.bitfield.regsimd))
2081 return 1;
2082
2083 if (!g1.bitfield.reg
2084 && !g1.bitfield.regsimd
2085 && (!operand_type_check (g1, anymem)
2086 || g1.bitfield.unspecified
2087 || !t1.bitfield.regsimd))
2088 return 1;
2089
2090 if (g0.bitfield.byte == g1.bitfield.byte
2091 && g0.bitfield.word == g1.bitfield.word
2092 && g0.bitfield.dword == g1.bitfield.dword
2093 && g0.bitfield.qword == g1.bitfield.qword
2094 && g0.bitfield.xmmword == g1.bitfield.xmmword
2095 && g0.bitfield.ymmword == g1.bitfield.ymmword
2096 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2097 return 1;
2098
2099 if (!(t0.bitfield.byte & t1.bitfield.byte)
2100 && !(t0.bitfield.word & t1.bitfield.word)
2101 && !(t0.bitfield.dword & t1.bitfield.dword)
2102 && !(t0.bitfield.qword & t1.bitfield.qword)
2103 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2104 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2105 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2106 return 1;
2107
2108 i.error = register_type_mismatch;
2109
2110 return 0;
2111 }
2112
2113 static INLINE unsigned int
2114 register_number (const reg_entry *r)
2115 {
2116 unsigned int nr = r->reg_num;
2117
2118 if (r->reg_flags & RegRex)
2119 nr += 8;
2120
2121 if (r->reg_flags & RegVRex)
2122 nr += 16;
2123
2124 return nr;
2125 }
2126
2127 static INLINE unsigned int
2128 mode_from_disp_size (i386_operand_type t)
2129 {
2130 if (t.bitfield.disp8)
2131 return 1;
2132 else if (t.bitfield.disp16
2133 || t.bitfield.disp32
2134 || t.bitfield.disp32s)
2135 return 2;
2136 else
2137 return 0;
2138 }
2139
2140 static INLINE int
2141 fits_in_signed_byte (addressT num)
2142 {
2143 return num + 0x80 <= 0xff;
2144 }
2145
2146 static INLINE int
2147 fits_in_unsigned_byte (addressT num)
2148 {
2149 return num <= 0xff;
2150 }
2151
2152 static INLINE int
2153 fits_in_unsigned_word (addressT num)
2154 {
2155 return num <= 0xffff;
2156 }
2157
2158 static INLINE int
2159 fits_in_signed_word (addressT num)
2160 {
2161 return num + 0x8000 <= 0xffff;
2162 }
2163
2164 static INLINE int
2165 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2166 {
2167 #ifndef BFD64
2168 return 1;
2169 #else
2170 return num + 0x80000000 <= 0xffffffff;
2171 #endif
2172 } /* fits_in_signed_long() */
2173
2174 static INLINE int
2175 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2176 {
2177 #ifndef BFD64
2178 return 1;
2179 #else
2180 return num <= 0xffffffff;
2181 #endif
2182 } /* fits_in_unsigned_long() */
2183
2184 static INLINE int
2185 fits_in_disp8 (offsetT num)
2186 {
2187 int shift = i.memshift;
2188 unsigned int mask;
2189
2190 if (shift == -1)
2191 abort ();
2192
2193 mask = (1 << shift) - 1;
2194
2195 /* Return 0 if NUM isn't properly aligned. */
2196 if ((num & mask))
2197 return 0;
2198
2199 /* Check if NUM will fit in 8bit after shift. */
2200 return fits_in_signed_byte (num >> shift);
2201 }
2202
2203 static INLINE int
2204 fits_in_imm4 (offsetT num)
2205 {
2206 return (num & 0xf) == num;
2207 }
2208
2209 static i386_operand_type
2210 smallest_imm_type (offsetT num)
2211 {
2212 i386_operand_type t;
2213
2214 operand_type_set (&t, 0);
2215 t.bitfield.imm64 = 1;
2216
2217 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2218 {
2219 /* This code is disabled on the 486 because all the Imm1 forms
2220 in the opcode table are slower on the i486. They're the
2221 versions with the implicitly specified single-position
2222 displacement, which has another syntax if you really want to
2223 use that form. */
2224 t.bitfield.imm1 = 1;
2225 t.bitfield.imm8 = 1;
2226 t.bitfield.imm8s = 1;
2227 t.bitfield.imm16 = 1;
2228 t.bitfield.imm32 = 1;
2229 t.bitfield.imm32s = 1;
2230 }
2231 else if (fits_in_signed_byte (num))
2232 {
2233 t.bitfield.imm8 = 1;
2234 t.bitfield.imm8s = 1;
2235 t.bitfield.imm16 = 1;
2236 t.bitfield.imm32 = 1;
2237 t.bitfield.imm32s = 1;
2238 }
2239 else if (fits_in_unsigned_byte (num))
2240 {
2241 t.bitfield.imm8 = 1;
2242 t.bitfield.imm16 = 1;
2243 t.bitfield.imm32 = 1;
2244 t.bitfield.imm32s = 1;
2245 }
2246 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2247 {
2248 t.bitfield.imm16 = 1;
2249 t.bitfield.imm32 = 1;
2250 t.bitfield.imm32s = 1;
2251 }
2252 else if (fits_in_signed_long (num))
2253 {
2254 t.bitfield.imm32 = 1;
2255 t.bitfield.imm32s = 1;
2256 }
2257 else if (fits_in_unsigned_long (num))
2258 t.bitfield.imm32 = 1;
2259
2260 return t;
2261 }
2262
2263 static offsetT
2264 offset_in_range (offsetT val, int size)
2265 {
2266 addressT mask;
2267
2268 switch (size)
2269 {
2270 case 1: mask = ((addressT) 1 << 8) - 1; break;
2271 case 2: mask = ((addressT) 1 << 16) - 1; break;
2272 case 4: mask = ((addressT) 2 << 31) - 1; break;
2273 #ifdef BFD64
2274 case 8: mask = ((addressT) 2 << 63) - 1; break;
2275 #endif
2276 default: abort ();
2277 }
2278
2279 #ifdef BFD64
2280 /* If BFD64, sign extend val for 32bit address mode. */
2281 if (flag_code != CODE_64BIT
2282 || i.prefix[ADDR_PREFIX])
2283 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2284 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2285 #endif
2286
2287 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2288 {
2289 char buf1[40], buf2[40];
2290
2291 sprint_value (buf1, val);
2292 sprint_value (buf2, val & mask);
2293 as_warn (_("%s shortened to %s"), buf1, buf2);
2294 }
2295 return val & mask;
2296 }
2297
2298 enum PREFIX_GROUP
2299 {
2300 PREFIX_EXIST = 0,
2301 PREFIX_LOCK,
2302 PREFIX_REP,
2303 PREFIX_DS,
2304 PREFIX_OTHER
2305 };
2306
2307 /* Returns
2308 a. PREFIX_EXIST if attempting to add a prefix where one from the
2309 same class already exists.
2310 b. PREFIX_LOCK if lock prefix is added.
2311 c. PREFIX_REP if rep/repne prefix is added.
2312 d. PREFIX_DS if ds prefix is added.
2313 e. PREFIX_OTHER if other prefix is added.
2314 */
2315
2316 static enum PREFIX_GROUP
2317 add_prefix (unsigned int prefix)
2318 {
2319 enum PREFIX_GROUP ret = PREFIX_OTHER;
2320 unsigned int q;
2321
2322 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2323 && flag_code == CODE_64BIT)
2324 {
2325 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2326 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2327 && (prefix & (REX_R | REX_X | REX_B))))
2328 ret = PREFIX_EXIST;
2329 q = REX_PREFIX;
2330 }
2331 else
2332 {
2333 switch (prefix)
2334 {
2335 default:
2336 abort ();
2337
2338 case DS_PREFIX_OPCODE:
2339 ret = PREFIX_DS;
2340 /* Fall through. */
2341 case CS_PREFIX_OPCODE:
2342 case ES_PREFIX_OPCODE:
2343 case FS_PREFIX_OPCODE:
2344 case GS_PREFIX_OPCODE:
2345 case SS_PREFIX_OPCODE:
2346 q = SEG_PREFIX;
2347 break;
2348
2349 case REPNE_PREFIX_OPCODE:
2350 case REPE_PREFIX_OPCODE:
2351 q = REP_PREFIX;
2352 ret = PREFIX_REP;
2353 break;
2354
2355 case LOCK_PREFIX_OPCODE:
2356 q = LOCK_PREFIX;
2357 ret = PREFIX_LOCK;
2358 break;
2359
2360 case FWAIT_OPCODE:
2361 q = WAIT_PREFIX;
2362 break;
2363
2364 case ADDR_PREFIX_OPCODE:
2365 q = ADDR_PREFIX;
2366 break;
2367
2368 case DATA_PREFIX_OPCODE:
2369 q = DATA_PREFIX;
2370 break;
2371 }
2372 if (i.prefix[q] != 0)
2373 ret = PREFIX_EXIST;
2374 }
2375
2376 if (ret)
2377 {
2378 if (!i.prefix[q])
2379 ++i.prefixes;
2380 i.prefix[q] |= prefix;
2381 }
2382 else
2383 as_bad (_("same type of prefix used twice"));
2384
2385 return ret;
2386 }
2387
2388 static void
2389 update_code_flag (int value, int check)
2390 {
2391 PRINTF_LIKE ((*as_error));
2392
2393 flag_code = (enum flag_code) value;
2394 if (flag_code == CODE_64BIT)
2395 {
2396 cpu_arch_flags.bitfield.cpu64 = 1;
2397 cpu_arch_flags.bitfield.cpuno64 = 0;
2398 }
2399 else
2400 {
2401 cpu_arch_flags.bitfield.cpu64 = 0;
2402 cpu_arch_flags.bitfield.cpuno64 = 1;
2403 }
2404 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2405 {
2406 if (check)
2407 as_error = as_fatal;
2408 else
2409 as_error = as_bad;
2410 (*as_error) (_("64bit mode not supported on `%s'."),
2411 cpu_arch_name ? cpu_arch_name : default_arch);
2412 }
2413 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2414 {
2415 if (check)
2416 as_error = as_fatal;
2417 else
2418 as_error = as_bad;
2419 (*as_error) (_("32bit mode not supported on `%s'."),
2420 cpu_arch_name ? cpu_arch_name : default_arch);
2421 }
2422 stackop_size = '\0';
2423 }
2424
2425 static void
2426 set_code_flag (int value)
2427 {
2428 update_code_flag (value, 0);
2429 }
2430
2431 static void
2432 set_16bit_gcc_code_flag (int new_code_flag)
2433 {
2434 flag_code = (enum flag_code) new_code_flag;
2435 if (flag_code != CODE_16BIT)
2436 abort ();
2437 cpu_arch_flags.bitfield.cpu64 = 0;
2438 cpu_arch_flags.bitfield.cpuno64 = 1;
2439 stackop_size = LONG_MNEM_SUFFIX;
2440 }
2441
2442 static void
2443 set_intel_syntax (int syntax_flag)
2444 {
2445 /* Find out if register prefixing is specified. */
2446 int ask_naked_reg = 0;
2447
2448 SKIP_WHITESPACE ();
2449 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2450 {
2451 char *string;
2452 int e = get_symbol_name (&string);
2453
2454 if (strcmp (string, "prefix") == 0)
2455 ask_naked_reg = 1;
2456 else if (strcmp (string, "noprefix") == 0)
2457 ask_naked_reg = -1;
2458 else
2459 as_bad (_("bad argument to syntax directive."));
2460 (void) restore_line_pointer (e);
2461 }
2462 demand_empty_rest_of_line ();
2463
2464 intel_syntax = syntax_flag;
2465
2466 if (ask_naked_reg == 0)
2467 allow_naked_reg = (intel_syntax
2468 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2469 else
2470 allow_naked_reg = (ask_naked_reg < 0);
2471
2472 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2473
2474 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2475 identifier_chars['$'] = intel_syntax ? '$' : 0;
2476 register_prefix = allow_naked_reg ? "" : "%";
2477 }
2478
2479 static void
2480 set_intel_mnemonic (int mnemonic_flag)
2481 {
2482 intel_mnemonic = mnemonic_flag;
2483 }
2484
2485 static void
2486 set_allow_index_reg (int flag)
2487 {
2488 allow_index_reg = flag;
2489 }
2490
2491 static void
2492 set_check (int what)
2493 {
2494 enum check_kind *kind;
2495 const char *str;
2496
2497 if (what)
2498 {
2499 kind = &operand_check;
2500 str = "operand";
2501 }
2502 else
2503 {
2504 kind = &sse_check;
2505 str = "sse";
2506 }
2507
2508 SKIP_WHITESPACE ();
2509
2510 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2511 {
2512 char *string;
2513 int e = get_symbol_name (&string);
2514
2515 if (strcmp (string, "none") == 0)
2516 *kind = check_none;
2517 else if (strcmp (string, "warning") == 0)
2518 *kind = check_warning;
2519 else if (strcmp (string, "error") == 0)
2520 *kind = check_error;
2521 else
2522 as_bad (_("bad argument to %s_check directive."), str);
2523 (void) restore_line_pointer (e);
2524 }
2525 else
2526 as_bad (_("missing argument for %s_check directive"), str);
2527
2528 demand_empty_rest_of_line ();
2529 }
2530
2531 static void
2532 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2533 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2534 {
2535 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2536 static const char *arch;
2537
2538 /* Intel LIOM is only supported on ELF. */
2539 if (!IS_ELF)
2540 return;
2541
2542 if (!arch)
2543 {
2544 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2545 use default_arch. */
2546 arch = cpu_arch_name;
2547 if (!arch)
2548 arch = default_arch;
2549 }
2550
2551 /* If we are targeting Intel MCU, we must enable it. */
2552 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2553 || new_flag.bitfield.cpuiamcu)
2554 return;
2555
2556 /* If we are targeting Intel L1OM, we must enable it. */
2557 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2558 || new_flag.bitfield.cpul1om)
2559 return;
2560
2561 /* If we are targeting Intel K1OM, we must enable it. */
2562 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2563 || new_flag.bitfield.cpuk1om)
2564 return;
2565
2566 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2567 #endif
2568 }
2569
2570 static void
2571 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2572 {
2573 SKIP_WHITESPACE ();
2574
2575 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2576 {
2577 char *string;
2578 int e = get_symbol_name (&string);
2579 unsigned int j;
2580 i386_cpu_flags flags;
2581
2582 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2583 {
2584 if (strcmp (string, cpu_arch[j].name) == 0)
2585 {
2586 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2587
2588 if (*string != '.')
2589 {
2590 cpu_arch_name = cpu_arch[j].name;
2591 cpu_sub_arch_name = NULL;
2592 cpu_arch_flags = cpu_arch[j].flags;
2593 if (flag_code == CODE_64BIT)
2594 {
2595 cpu_arch_flags.bitfield.cpu64 = 1;
2596 cpu_arch_flags.bitfield.cpuno64 = 0;
2597 }
2598 else
2599 {
2600 cpu_arch_flags.bitfield.cpu64 = 0;
2601 cpu_arch_flags.bitfield.cpuno64 = 1;
2602 }
2603 cpu_arch_isa = cpu_arch[j].type;
2604 cpu_arch_isa_flags = cpu_arch[j].flags;
2605 if (!cpu_arch_tune_set)
2606 {
2607 cpu_arch_tune = cpu_arch_isa;
2608 cpu_arch_tune_flags = cpu_arch_isa_flags;
2609 }
2610 break;
2611 }
2612
2613 flags = cpu_flags_or (cpu_arch_flags,
2614 cpu_arch[j].flags);
2615
2616 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2617 {
2618 if (cpu_sub_arch_name)
2619 {
2620 char *name = cpu_sub_arch_name;
2621 cpu_sub_arch_name = concat (name,
2622 cpu_arch[j].name,
2623 (const char *) NULL);
2624 free (name);
2625 }
2626 else
2627 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2628 cpu_arch_flags = flags;
2629 cpu_arch_isa_flags = flags;
2630 }
2631 else
2632 cpu_arch_isa_flags
2633 = cpu_flags_or (cpu_arch_isa_flags,
2634 cpu_arch[j].flags);
2635 (void) restore_line_pointer (e);
2636 demand_empty_rest_of_line ();
2637 return;
2638 }
2639 }
2640
2641 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2642 {
2643 /* Disable an ISA extension. */
2644 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2645 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2646 {
2647 flags = cpu_flags_and_not (cpu_arch_flags,
2648 cpu_noarch[j].flags);
2649 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2650 {
2651 if (cpu_sub_arch_name)
2652 {
2653 char *name = cpu_sub_arch_name;
2654 cpu_sub_arch_name = concat (name, string,
2655 (const char *) NULL);
2656 free (name);
2657 }
2658 else
2659 cpu_sub_arch_name = xstrdup (string);
2660 cpu_arch_flags = flags;
2661 cpu_arch_isa_flags = flags;
2662 }
2663 (void) restore_line_pointer (e);
2664 demand_empty_rest_of_line ();
2665 return;
2666 }
2667
2668 j = ARRAY_SIZE (cpu_arch);
2669 }
2670
2671 if (j >= ARRAY_SIZE (cpu_arch))
2672 as_bad (_("no such architecture: `%s'"), string);
2673
2674 *input_line_pointer = e;
2675 }
2676 else
2677 as_bad (_("missing cpu architecture"));
2678
2679 no_cond_jump_promotion = 0;
2680 if (*input_line_pointer == ','
2681 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2682 {
2683 char *string;
2684 char e;
2685
2686 ++input_line_pointer;
2687 e = get_symbol_name (&string);
2688
2689 if (strcmp (string, "nojumps") == 0)
2690 no_cond_jump_promotion = 1;
2691 else if (strcmp (string, "jumps") == 0)
2692 ;
2693 else
2694 as_bad (_("no such architecture modifier: `%s'"), string);
2695
2696 (void) restore_line_pointer (e);
2697 }
2698
2699 demand_empty_rest_of_line ();
2700 }
2701
2702 enum bfd_architecture
2703 i386_arch (void)
2704 {
2705 if (cpu_arch_isa == PROCESSOR_L1OM)
2706 {
2707 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2708 || flag_code != CODE_64BIT)
2709 as_fatal (_("Intel L1OM is 64bit ELF only"));
2710 return bfd_arch_l1om;
2711 }
2712 else if (cpu_arch_isa == PROCESSOR_K1OM)
2713 {
2714 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2715 || flag_code != CODE_64BIT)
2716 as_fatal (_("Intel K1OM is 64bit ELF only"));
2717 return bfd_arch_k1om;
2718 }
2719 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2720 {
2721 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2722 || flag_code == CODE_64BIT)
2723 as_fatal (_("Intel MCU is 32bit ELF only"));
2724 return bfd_arch_iamcu;
2725 }
2726 else
2727 return bfd_arch_i386;
2728 }
2729
2730 unsigned long
2731 i386_mach (void)
2732 {
2733 if (!strncmp (default_arch, "x86_64", 6))
2734 {
2735 if (cpu_arch_isa == PROCESSOR_L1OM)
2736 {
2737 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2738 || default_arch[6] != '\0')
2739 as_fatal (_("Intel L1OM is 64bit ELF only"));
2740 return bfd_mach_l1om;
2741 }
2742 else if (cpu_arch_isa == PROCESSOR_K1OM)
2743 {
2744 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2745 || default_arch[6] != '\0')
2746 as_fatal (_("Intel K1OM is 64bit ELF only"));
2747 return bfd_mach_k1om;
2748 }
2749 else if (default_arch[6] == '\0')
2750 return bfd_mach_x86_64;
2751 else
2752 return bfd_mach_x64_32;
2753 }
2754 else if (!strcmp (default_arch, "i386")
2755 || !strcmp (default_arch, "iamcu"))
2756 {
2757 if (cpu_arch_isa == PROCESSOR_IAMCU)
2758 {
2759 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2760 as_fatal (_("Intel MCU is 32bit ELF only"));
2761 return bfd_mach_i386_iamcu;
2762 }
2763 else
2764 return bfd_mach_i386_i386;
2765 }
2766 else
2767 as_fatal (_("unknown architecture"));
2768 }
2769 \f
2770 void
2771 md_begin (void)
2772 {
2773 const char *hash_err;
2774
2775 /* Support pseudo prefixes like {disp32}. */
2776 lex_type ['{'] = LEX_BEGIN_NAME;
2777
2778 /* Initialize op_hash hash table. */
2779 op_hash = hash_new ();
2780
2781 {
2782 const insn_template *optab;
2783 templates *core_optab;
2784
2785 /* Setup for loop. */
2786 optab = i386_optab;
2787 core_optab = XNEW (templates);
2788 core_optab->start = optab;
2789
2790 while (1)
2791 {
2792 ++optab;
2793 if (optab->name == NULL
2794 || strcmp (optab->name, (optab - 1)->name) != 0)
2795 {
2796 /* different name --> ship out current template list;
2797 add to hash table; & begin anew. */
2798 core_optab->end = optab;
2799 hash_err = hash_insert (op_hash,
2800 (optab - 1)->name,
2801 (void *) core_optab);
2802 if (hash_err)
2803 {
2804 as_fatal (_("can't hash %s: %s"),
2805 (optab - 1)->name,
2806 hash_err);
2807 }
2808 if (optab->name == NULL)
2809 break;
2810 core_optab = XNEW (templates);
2811 core_optab->start = optab;
2812 }
2813 }
2814 }
2815
2816 /* Initialize reg_hash hash table. */
2817 reg_hash = hash_new ();
2818 {
2819 const reg_entry *regtab;
2820 unsigned int regtab_size = i386_regtab_size;
2821
2822 for (regtab = i386_regtab; regtab_size--; regtab++)
2823 {
2824 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2825 if (hash_err)
2826 as_fatal (_("can't hash %s: %s"),
2827 regtab->reg_name,
2828 hash_err);
2829 }
2830 }
2831
2832 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2833 {
2834 int c;
2835 char *p;
2836
2837 for (c = 0; c < 256; c++)
2838 {
2839 if (ISDIGIT (c))
2840 {
2841 digit_chars[c] = c;
2842 mnemonic_chars[c] = c;
2843 register_chars[c] = c;
2844 operand_chars[c] = c;
2845 }
2846 else if (ISLOWER (c))
2847 {
2848 mnemonic_chars[c] = c;
2849 register_chars[c] = c;
2850 operand_chars[c] = c;
2851 }
2852 else if (ISUPPER (c))
2853 {
2854 mnemonic_chars[c] = TOLOWER (c);
2855 register_chars[c] = mnemonic_chars[c];
2856 operand_chars[c] = c;
2857 }
2858 else if (c == '{' || c == '}')
2859 {
2860 mnemonic_chars[c] = c;
2861 operand_chars[c] = c;
2862 }
2863
2864 if (ISALPHA (c) || ISDIGIT (c))
2865 identifier_chars[c] = c;
2866 else if (c >= 128)
2867 {
2868 identifier_chars[c] = c;
2869 operand_chars[c] = c;
2870 }
2871 }
2872
2873 #ifdef LEX_AT
2874 identifier_chars['@'] = '@';
2875 #endif
2876 #ifdef LEX_QM
2877 identifier_chars['?'] = '?';
2878 operand_chars['?'] = '?';
2879 #endif
2880 digit_chars['-'] = '-';
2881 mnemonic_chars['_'] = '_';
2882 mnemonic_chars['-'] = '-';
2883 mnemonic_chars['.'] = '.';
2884 identifier_chars['_'] = '_';
2885 identifier_chars['.'] = '.';
2886
2887 for (p = operand_special_chars; *p != '\0'; p++)
2888 operand_chars[(unsigned char) *p] = *p;
2889 }
2890
2891 if (flag_code == CODE_64BIT)
2892 {
2893 #if defined (OBJ_COFF) && defined (TE_PE)
2894 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2895 ? 32 : 16);
2896 #else
2897 x86_dwarf2_return_column = 16;
2898 #endif
2899 x86_cie_data_alignment = -8;
2900 }
2901 else
2902 {
2903 x86_dwarf2_return_column = 8;
2904 x86_cie_data_alignment = -4;
2905 }
2906 }
2907
2908 void
2909 i386_print_statistics (FILE *file)
2910 {
2911 hash_print_statistics (file, "i386 opcode", op_hash);
2912 hash_print_statistics (file, "i386 register", reg_hash);
2913 }
2914 \f
2915 #ifdef DEBUG386
2916
2917 /* Debugging routines for md_assemble. */
2918 static void pte (insn_template *);
2919 static void pt (i386_operand_type);
2920 static void pe (expressionS *);
2921 static void ps (symbolS *);
2922
2923 static void
2924 pi (char *line, i386_insn *x)
2925 {
2926 unsigned int j;
2927
2928 fprintf (stdout, "%s: template ", line);
2929 pte (&x->tm);
2930 fprintf (stdout, " address: base %s index %s scale %x\n",
2931 x->base_reg ? x->base_reg->reg_name : "none",
2932 x->index_reg ? x->index_reg->reg_name : "none",
2933 x->log2_scale_factor);
2934 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2935 x->rm.mode, x->rm.reg, x->rm.regmem);
2936 fprintf (stdout, " sib: base %x index %x scale %x\n",
2937 x->sib.base, x->sib.index, x->sib.scale);
2938 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2939 (x->rex & REX_W) != 0,
2940 (x->rex & REX_R) != 0,
2941 (x->rex & REX_X) != 0,
2942 (x->rex & REX_B) != 0);
2943 for (j = 0; j < x->operands; j++)
2944 {
2945 fprintf (stdout, " #%d: ", j + 1);
2946 pt (x->types[j]);
2947 fprintf (stdout, "\n");
2948 if (x->types[j].bitfield.reg
2949 || x->types[j].bitfield.regmmx
2950 || x->types[j].bitfield.regsimd
2951 || x->types[j].bitfield.sreg2
2952 || x->types[j].bitfield.sreg3
2953 || x->types[j].bitfield.control
2954 || x->types[j].bitfield.debug
2955 || x->types[j].bitfield.test)
2956 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2957 if (operand_type_check (x->types[j], imm))
2958 pe (x->op[j].imms);
2959 if (operand_type_check (x->types[j], disp))
2960 pe (x->op[j].disps);
2961 }
2962 }
2963
2964 static void
2965 pte (insn_template *t)
2966 {
2967 unsigned int j;
2968 fprintf (stdout, " %d operands ", t->operands);
2969 fprintf (stdout, "opcode %x ", t->base_opcode);
2970 if (t->extension_opcode != None)
2971 fprintf (stdout, "ext %x ", t->extension_opcode);
2972 if (t->opcode_modifier.d)
2973 fprintf (stdout, "D");
2974 if (t->opcode_modifier.w)
2975 fprintf (stdout, "W");
2976 fprintf (stdout, "\n");
2977 for (j = 0; j < t->operands; j++)
2978 {
2979 fprintf (stdout, " #%d type ", j + 1);
2980 pt (t->operand_types[j]);
2981 fprintf (stdout, "\n");
2982 }
2983 }
2984
2985 static void
2986 pe (expressionS *e)
2987 {
2988 fprintf (stdout, " operation %d\n", e->X_op);
2989 fprintf (stdout, " add_number %ld (%lx)\n",
2990 (long) e->X_add_number, (long) e->X_add_number);
2991 if (e->X_add_symbol)
2992 {
2993 fprintf (stdout, " add_symbol ");
2994 ps (e->X_add_symbol);
2995 fprintf (stdout, "\n");
2996 }
2997 if (e->X_op_symbol)
2998 {
2999 fprintf (stdout, " op_symbol ");
3000 ps (e->X_op_symbol);
3001 fprintf (stdout, "\n");
3002 }
3003 }
3004
3005 static void
3006 ps (symbolS *s)
3007 {
3008 fprintf (stdout, "%s type %s%s",
3009 S_GET_NAME (s),
3010 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3011 segment_name (S_GET_SEGMENT (s)));
3012 }
3013
3014 static struct type_name
3015 {
3016 i386_operand_type mask;
3017 const char *name;
3018 }
3019 const type_names[] =
3020 {
3021 { OPERAND_TYPE_REG8, "r8" },
3022 { OPERAND_TYPE_REG16, "r16" },
3023 { OPERAND_TYPE_REG32, "r32" },
3024 { OPERAND_TYPE_REG64, "r64" },
3025 { OPERAND_TYPE_IMM8, "i8" },
3026 { OPERAND_TYPE_IMM8, "i8s" },
3027 { OPERAND_TYPE_IMM16, "i16" },
3028 { OPERAND_TYPE_IMM32, "i32" },
3029 { OPERAND_TYPE_IMM32S, "i32s" },
3030 { OPERAND_TYPE_IMM64, "i64" },
3031 { OPERAND_TYPE_IMM1, "i1" },
3032 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3033 { OPERAND_TYPE_DISP8, "d8" },
3034 { OPERAND_TYPE_DISP16, "d16" },
3035 { OPERAND_TYPE_DISP32, "d32" },
3036 { OPERAND_TYPE_DISP32S, "d32s" },
3037 { OPERAND_TYPE_DISP64, "d64" },
3038 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3039 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3040 { OPERAND_TYPE_CONTROL, "control reg" },
3041 { OPERAND_TYPE_TEST, "test reg" },
3042 { OPERAND_TYPE_DEBUG, "debug reg" },
3043 { OPERAND_TYPE_FLOATREG, "FReg" },
3044 { OPERAND_TYPE_FLOATACC, "FAcc" },
3045 { OPERAND_TYPE_SREG2, "SReg2" },
3046 { OPERAND_TYPE_SREG3, "SReg3" },
3047 { OPERAND_TYPE_ACC, "Acc" },
3048 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3049 { OPERAND_TYPE_REGMMX, "rMMX" },
3050 { OPERAND_TYPE_REGXMM, "rXMM" },
3051 { OPERAND_TYPE_REGYMM, "rYMM" },
3052 { OPERAND_TYPE_REGZMM, "rZMM" },
3053 { OPERAND_TYPE_REGMASK, "Mask reg" },
3054 { OPERAND_TYPE_ESSEG, "es" },
3055 };
3056
3057 static void
3058 pt (i386_operand_type t)
3059 {
3060 unsigned int j;
3061 i386_operand_type a;
3062
3063 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3064 {
3065 a = operand_type_and (t, type_names[j].mask);
3066 if (!operand_type_all_zero (&a))
3067 fprintf (stdout, "%s, ", type_names[j].name);
3068 }
3069 fflush (stdout);
3070 }
3071
3072 #endif /* DEBUG386 */
3073 \f
3074 static bfd_reloc_code_real_type
3075 reloc (unsigned int size,
3076 int pcrel,
3077 int sign,
3078 bfd_reloc_code_real_type other)
3079 {
3080 if (other != NO_RELOC)
3081 {
3082 reloc_howto_type *rel;
3083
3084 if (size == 8)
3085 switch (other)
3086 {
3087 case BFD_RELOC_X86_64_GOT32:
3088 return BFD_RELOC_X86_64_GOT64;
3089 break;
3090 case BFD_RELOC_X86_64_GOTPLT64:
3091 return BFD_RELOC_X86_64_GOTPLT64;
3092 break;
3093 case BFD_RELOC_X86_64_PLTOFF64:
3094 return BFD_RELOC_X86_64_PLTOFF64;
3095 break;
3096 case BFD_RELOC_X86_64_GOTPC32:
3097 other = BFD_RELOC_X86_64_GOTPC64;
3098 break;
3099 case BFD_RELOC_X86_64_GOTPCREL:
3100 other = BFD_RELOC_X86_64_GOTPCREL64;
3101 break;
3102 case BFD_RELOC_X86_64_TPOFF32:
3103 other = BFD_RELOC_X86_64_TPOFF64;
3104 break;
3105 case BFD_RELOC_X86_64_DTPOFF32:
3106 other = BFD_RELOC_X86_64_DTPOFF64;
3107 break;
3108 default:
3109 break;
3110 }
3111
3112 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3113 if (other == BFD_RELOC_SIZE32)
3114 {
3115 if (size == 8)
3116 other = BFD_RELOC_SIZE64;
3117 if (pcrel)
3118 {
3119 as_bad (_("there are no pc-relative size relocations"));
3120 return NO_RELOC;
3121 }
3122 }
3123 #endif
3124
3125 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3126 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3127 sign = -1;
3128
3129 rel = bfd_reloc_type_lookup (stdoutput, other);
3130 if (!rel)
3131 as_bad (_("unknown relocation (%u)"), other);
3132 else if (size != bfd_get_reloc_size (rel))
3133 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3134 bfd_get_reloc_size (rel),
3135 size);
3136 else if (pcrel && !rel->pc_relative)
3137 as_bad (_("non-pc-relative relocation for pc-relative field"));
3138 else if ((rel->complain_on_overflow == complain_overflow_signed
3139 && !sign)
3140 || (rel->complain_on_overflow == complain_overflow_unsigned
3141 && sign > 0))
3142 as_bad (_("relocated field and relocation type differ in signedness"));
3143 else
3144 return other;
3145 return NO_RELOC;
3146 }
3147
3148 if (pcrel)
3149 {
3150 if (!sign)
3151 as_bad (_("there are no unsigned pc-relative relocations"));
3152 switch (size)
3153 {
3154 case 1: return BFD_RELOC_8_PCREL;
3155 case 2: return BFD_RELOC_16_PCREL;
3156 case 4: return BFD_RELOC_32_PCREL;
3157 case 8: return BFD_RELOC_64_PCREL;
3158 }
3159 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3160 }
3161 else
3162 {
3163 if (sign > 0)
3164 switch (size)
3165 {
3166 case 4: return BFD_RELOC_X86_64_32S;
3167 }
3168 else
3169 switch (size)
3170 {
3171 case 1: return BFD_RELOC_8;
3172 case 2: return BFD_RELOC_16;
3173 case 4: return BFD_RELOC_32;
3174 case 8: return BFD_RELOC_64;
3175 }
3176 as_bad (_("cannot do %s %u byte relocation"),
3177 sign > 0 ? "signed" : "unsigned", size);
3178 }
3179
3180 return NO_RELOC;
3181 }
3182
3183 /* Here we decide which fixups can be adjusted to make them relative to
3184 the beginning of the section instead of the symbol. Basically we need
3185 to make sure that the dynamic relocations are done correctly, so in
3186 some cases we force the original symbol to be used. */
3187
3188 int
3189 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3190 {
3191 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3192 if (!IS_ELF)
3193 return 1;
3194
3195 /* Don't adjust pc-relative references to merge sections in 64-bit
3196 mode. */
3197 if (use_rela_relocations
3198 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3199 && fixP->fx_pcrel)
3200 return 0;
3201
3202 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3203 and changed later by validate_fix. */
3204 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3205 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3206 return 0;
3207
3208 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3209 for size relocations. */
3210 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3211 || fixP->fx_r_type == BFD_RELOC_SIZE64
3212 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3213 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3214 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3215 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3216 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3217 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3218 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3219 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3220 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3221 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3222 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3223 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3224 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3225 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3226 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3227 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3228 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3229 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3230 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3231 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3232 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3233 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3234 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3235 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3236 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3237 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3238 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3239 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3240 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3241 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3242 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3243 return 0;
3244 #endif
3245 return 1;
3246 }
3247
3248 static int
3249 intel_float_operand (const char *mnemonic)
3250 {
3251 /* Note that the value returned is meaningful only for opcodes with (memory)
3252 operands, hence the code here is free to improperly handle opcodes that
3253 have no operands (for better performance and smaller code). */
3254
3255 if (mnemonic[0] != 'f')
3256 return 0; /* non-math */
3257
3258 switch (mnemonic[1])
3259 {
3260 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3261 the fs segment override prefix not currently handled because no
3262 call path can make opcodes without operands get here */
3263 case 'i':
3264 return 2 /* integer op */;
3265 case 'l':
3266 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3267 return 3; /* fldcw/fldenv */
3268 break;
3269 case 'n':
3270 if (mnemonic[2] != 'o' /* fnop */)
3271 return 3; /* non-waiting control op */
3272 break;
3273 case 'r':
3274 if (mnemonic[2] == 's')
3275 return 3; /* frstor/frstpm */
3276 break;
3277 case 's':
3278 if (mnemonic[2] == 'a')
3279 return 3; /* fsave */
3280 if (mnemonic[2] == 't')
3281 {
3282 switch (mnemonic[3])
3283 {
3284 case 'c': /* fstcw */
3285 case 'd': /* fstdw */
3286 case 'e': /* fstenv */
3287 case 's': /* fsts[gw] */
3288 return 3;
3289 }
3290 }
3291 break;
3292 case 'x':
3293 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3294 return 0; /* fxsave/fxrstor are not really math ops */
3295 break;
3296 }
3297
3298 return 1;
3299 }
3300
3301 /* Build the VEX prefix. */
3302
3303 static void
3304 build_vex_prefix (const insn_template *t)
3305 {
3306 unsigned int register_specifier;
3307 unsigned int implied_prefix;
3308 unsigned int vector_length;
3309
3310 /* Check register specifier. */
3311 if (i.vex.register_specifier)
3312 {
3313 register_specifier =
3314 ~register_number (i.vex.register_specifier) & 0xf;
3315 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3316 }
3317 else
3318 register_specifier = 0xf;
3319
3320 /* Use 2-byte VEX prefix by swapping destination and source
3321 operand. */
3322 if (i.vec_encoding != vex_encoding_vex3
3323 && i.dir_encoding == dir_encoding_default
3324 && i.operands == i.reg_operands
3325 && i.tm.opcode_modifier.vexopcode == VEX0F
3326 && i.tm.opcode_modifier.load
3327 && i.rex == REX_B)
3328 {
3329 unsigned int xchg = i.operands - 1;
3330 union i386_op temp_op;
3331 i386_operand_type temp_type;
3332
3333 temp_type = i.types[xchg];
3334 i.types[xchg] = i.types[0];
3335 i.types[0] = temp_type;
3336 temp_op = i.op[xchg];
3337 i.op[xchg] = i.op[0];
3338 i.op[0] = temp_op;
3339
3340 gas_assert (i.rm.mode == 3);
3341
3342 i.rex = REX_R;
3343 xchg = i.rm.regmem;
3344 i.rm.regmem = i.rm.reg;
3345 i.rm.reg = xchg;
3346
3347 /* Use the next insn. */
3348 i.tm = t[1];
3349 }
3350
3351 if (i.tm.opcode_modifier.vex == VEXScalar)
3352 vector_length = avxscalar;
3353 else if (i.tm.opcode_modifier.vex == VEX256)
3354 vector_length = 1;
3355 else
3356 {
3357 unsigned int op;
3358
3359 vector_length = 0;
3360 for (op = 0; op < t->operands; ++op)
3361 if (t->operand_types[op].bitfield.xmmword
3362 && t->operand_types[op].bitfield.ymmword
3363 && i.types[op].bitfield.ymmword)
3364 {
3365 vector_length = 1;
3366 break;
3367 }
3368 }
3369
3370 switch ((i.tm.base_opcode >> 8) & 0xff)
3371 {
3372 case 0:
3373 implied_prefix = 0;
3374 break;
3375 case DATA_PREFIX_OPCODE:
3376 implied_prefix = 1;
3377 break;
3378 case REPE_PREFIX_OPCODE:
3379 implied_prefix = 2;
3380 break;
3381 case REPNE_PREFIX_OPCODE:
3382 implied_prefix = 3;
3383 break;
3384 default:
3385 abort ();
3386 }
3387
3388 /* Use 2-byte VEX prefix if possible. */
3389 if (i.vec_encoding != vex_encoding_vex3
3390 && i.tm.opcode_modifier.vexopcode == VEX0F
3391 && i.tm.opcode_modifier.vexw != VEXW1
3392 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3393 {
3394 /* 2-byte VEX prefix. */
3395 unsigned int r;
3396
3397 i.vex.length = 2;
3398 i.vex.bytes[0] = 0xc5;
3399
3400 /* Check the REX.R bit. */
3401 r = (i.rex & REX_R) ? 0 : 1;
3402 i.vex.bytes[1] = (r << 7
3403 | register_specifier << 3
3404 | vector_length << 2
3405 | implied_prefix);
3406 }
3407 else
3408 {
3409 /* 3-byte VEX prefix. */
3410 unsigned int m, w;
3411
3412 i.vex.length = 3;
3413
3414 switch (i.tm.opcode_modifier.vexopcode)
3415 {
3416 case VEX0F:
3417 m = 0x1;
3418 i.vex.bytes[0] = 0xc4;
3419 break;
3420 case VEX0F38:
3421 m = 0x2;
3422 i.vex.bytes[0] = 0xc4;
3423 break;
3424 case VEX0F3A:
3425 m = 0x3;
3426 i.vex.bytes[0] = 0xc4;
3427 break;
3428 case XOP08:
3429 m = 0x8;
3430 i.vex.bytes[0] = 0x8f;
3431 break;
3432 case XOP09:
3433 m = 0x9;
3434 i.vex.bytes[0] = 0x8f;
3435 break;
3436 case XOP0A:
3437 m = 0xa;
3438 i.vex.bytes[0] = 0x8f;
3439 break;
3440 default:
3441 abort ();
3442 }
3443
3444 /* The high 3 bits of the second VEX byte are 1's compliment
3445 of RXB bits from REX. */
3446 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3447
3448 /* Check the REX.W bit. */
3449 w = (i.rex & REX_W) ? 1 : 0;
3450 if (i.tm.opcode_modifier.vexw == VEXW1)
3451 w = 1;
3452
3453 i.vex.bytes[2] = (w << 7
3454 | register_specifier << 3
3455 | vector_length << 2
3456 | implied_prefix);
3457 }
3458 }
3459
3460 static INLINE bfd_boolean
3461 is_evex_encoding (const insn_template *t)
3462 {
3463 return t->opcode_modifier.evex
3464 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3465 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3466 }
3467
3468 /* Build the EVEX prefix. */
3469
3470 static void
3471 build_evex_prefix (void)
3472 {
3473 unsigned int register_specifier;
3474 unsigned int implied_prefix;
3475 unsigned int m, w;
3476 rex_byte vrex_used = 0;
3477
3478 /* Check register specifier. */
3479 if (i.vex.register_specifier)
3480 {
3481 gas_assert ((i.vrex & REX_X) == 0);
3482
3483 register_specifier = i.vex.register_specifier->reg_num;
3484 if ((i.vex.register_specifier->reg_flags & RegRex))
3485 register_specifier += 8;
3486 /* The upper 16 registers are encoded in the fourth byte of the
3487 EVEX prefix. */
3488 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3489 i.vex.bytes[3] = 0x8;
3490 register_specifier = ~register_specifier & 0xf;
3491 }
3492 else
3493 {
3494 register_specifier = 0xf;
3495
3496 /* Encode upper 16 vector index register in the fourth byte of
3497 the EVEX prefix. */
3498 if (!(i.vrex & REX_X))
3499 i.vex.bytes[3] = 0x8;
3500 else
3501 vrex_used |= REX_X;
3502 }
3503
3504 switch ((i.tm.base_opcode >> 8) & 0xff)
3505 {
3506 case 0:
3507 implied_prefix = 0;
3508 break;
3509 case DATA_PREFIX_OPCODE:
3510 implied_prefix = 1;
3511 break;
3512 case REPE_PREFIX_OPCODE:
3513 implied_prefix = 2;
3514 break;
3515 case REPNE_PREFIX_OPCODE:
3516 implied_prefix = 3;
3517 break;
3518 default:
3519 abort ();
3520 }
3521
3522 /* 4 byte EVEX prefix. */
3523 i.vex.length = 4;
3524 i.vex.bytes[0] = 0x62;
3525
3526 /* mmmm bits. */
3527 switch (i.tm.opcode_modifier.vexopcode)
3528 {
3529 case VEX0F:
3530 m = 1;
3531 break;
3532 case VEX0F38:
3533 m = 2;
3534 break;
3535 case VEX0F3A:
3536 m = 3;
3537 break;
3538 default:
3539 abort ();
3540 break;
3541 }
3542
3543 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3544 bits from REX. */
3545 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3546
3547 /* The fifth bit of the second EVEX byte is 1's compliment of the
3548 REX_R bit in VREX. */
3549 if (!(i.vrex & REX_R))
3550 i.vex.bytes[1] |= 0x10;
3551 else
3552 vrex_used |= REX_R;
3553
3554 if ((i.reg_operands + i.imm_operands) == i.operands)
3555 {
3556 /* When all operands are registers, the REX_X bit in REX is not
3557 used. We reuse it to encode the upper 16 registers, which is
3558 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3559 as 1's compliment. */
3560 if ((i.vrex & REX_B))
3561 {
3562 vrex_used |= REX_B;
3563 i.vex.bytes[1] &= ~0x40;
3564 }
3565 }
3566
3567 /* EVEX instructions shouldn't need the REX prefix. */
3568 i.vrex &= ~vrex_used;
3569 gas_assert (i.vrex == 0);
3570
3571 /* Check the REX.W bit. */
3572 w = (i.rex & REX_W) ? 1 : 0;
3573 if (i.tm.opcode_modifier.vexw)
3574 {
3575 if (i.tm.opcode_modifier.vexw == VEXW1)
3576 w = 1;
3577 }
3578 /* If w is not set it means we are dealing with WIG instruction. */
3579 else if (!w)
3580 {
3581 if (evexwig == evexw1)
3582 w = 1;
3583 }
3584
3585 /* Encode the U bit. */
3586 implied_prefix |= 0x4;
3587
3588 /* The third byte of the EVEX prefix. */
3589 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3590
3591 /* The fourth byte of the EVEX prefix. */
3592 /* The zeroing-masking bit. */
3593 if (i.mask && i.mask->zeroing)
3594 i.vex.bytes[3] |= 0x80;
3595
3596 /* Don't always set the broadcast bit if there is no RC. */
3597 if (!i.rounding)
3598 {
3599 /* Encode the vector length. */
3600 unsigned int vec_length;
3601
3602 if (!i.tm.opcode_modifier.evex
3603 || i.tm.opcode_modifier.evex == EVEXDYN)
3604 {
3605 unsigned int op;
3606
3607 vec_length = 0;
3608 for (op = 0; op < i.tm.operands; ++op)
3609 if (i.tm.operand_types[op].bitfield.xmmword
3610 + i.tm.operand_types[op].bitfield.ymmword
3611 + i.tm.operand_types[op].bitfield.zmmword > 1)
3612 {
3613 if (i.types[op].bitfield.zmmword)
3614 i.tm.opcode_modifier.evex = EVEX512;
3615 else if (i.types[op].bitfield.ymmword)
3616 i.tm.opcode_modifier.evex = EVEX256;
3617 else if (i.types[op].bitfield.xmmword)
3618 i.tm.opcode_modifier.evex = EVEX128;
3619 else
3620 continue;
3621 break;
3622 }
3623 }
3624
3625 switch (i.tm.opcode_modifier.evex)
3626 {
3627 case EVEXLIG: /* LL' is ignored */
3628 vec_length = evexlig << 5;
3629 break;
3630 case EVEX128:
3631 vec_length = 0 << 5;
3632 break;
3633 case EVEX256:
3634 vec_length = 1 << 5;
3635 break;
3636 case EVEX512:
3637 vec_length = 2 << 5;
3638 break;
3639 default:
3640 abort ();
3641 break;
3642 }
3643 i.vex.bytes[3] |= vec_length;
3644 /* Encode the broadcast bit. */
3645 if (i.broadcast)
3646 i.vex.bytes[3] |= 0x10;
3647 }
3648 else
3649 {
3650 if (i.rounding->type != saeonly)
3651 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3652 else
3653 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3654 }
3655
3656 if (i.mask && i.mask->mask)
3657 i.vex.bytes[3] |= i.mask->mask->reg_num;
3658 }
3659
3660 static void
3661 process_immext (void)
3662 {
3663 expressionS *exp;
3664
3665 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3666 && i.operands > 0)
3667 {
3668 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3669 with an opcode suffix which is coded in the same place as an
3670 8-bit immediate field would be.
3671 Here we check those operands and remove them afterwards. */
3672 unsigned int x;
3673
3674 for (x = 0; x < i.operands; x++)
3675 if (register_number (i.op[x].regs) != x)
3676 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3677 register_prefix, i.op[x].regs->reg_name, x + 1,
3678 i.tm.name);
3679
3680 i.operands = 0;
3681 }
3682
3683 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3684 {
3685 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3686 suffix which is coded in the same place as an 8-bit immediate
3687 field would be.
3688 Here we check those operands and remove them afterwards. */
3689 unsigned int x;
3690
3691 if (i.operands != 3)
3692 abort();
3693
3694 for (x = 0; x < 2; x++)
3695 if (register_number (i.op[x].regs) != x)
3696 goto bad_register_operand;
3697
3698 /* Check for third operand for mwaitx/monitorx insn. */
3699 if (register_number (i.op[x].regs)
3700 != (x + (i.tm.extension_opcode == 0xfb)))
3701 {
3702 bad_register_operand:
3703 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3704 register_prefix, i.op[x].regs->reg_name, x+1,
3705 i.tm.name);
3706 }
3707
3708 i.operands = 0;
3709 }
3710
3711 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3712 which is coded in the same place as an 8-bit immediate field
3713 would be. Here we fake an 8-bit immediate operand from the
3714 opcode suffix stored in tm.extension_opcode.
3715
3716 AVX instructions also use this encoding, for some of
3717 3 argument instructions. */
3718
3719 gas_assert (i.imm_operands <= 1
3720 && (i.operands <= 2
3721 || ((i.tm.opcode_modifier.vex
3722 || i.tm.opcode_modifier.vexopcode
3723 || is_evex_encoding (&i.tm))
3724 && i.operands <= 4)));
3725
3726 exp = &im_expressions[i.imm_operands++];
3727 i.op[i.operands].imms = exp;
3728 i.types[i.operands] = imm8;
3729 i.operands++;
3730 exp->X_op = O_constant;
3731 exp->X_add_number = i.tm.extension_opcode;
3732 i.tm.extension_opcode = None;
3733 }
3734
3735
3736 static int
3737 check_hle (void)
3738 {
3739 switch (i.tm.opcode_modifier.hleprefixok)
3740 {
3741 default:
3742 abort ();
3743 case HLEPrefixNone:
3744 as_bad (_("invalid instruction `%s' after `%s'"),
3745 i.tm.name, i.hle_prefix);
3746 return 0;
3747 case HLEPrefixLock:
3748 if (i.prefix[LOCK_PREFIX])
3749 return 1;
3750 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3751 return 0;
3752 case HLEPrefixAny:
3753 return 1;
3754 case HLEPrefixRelease:
3755 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3756 {
3757 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3758 i.tm.name);
3759 return 0;
3760 }
3761 if (i.mem_operands == 0
3762 || !operand_type_check (i.types[i.operands - 1], anymem))
3763 {
3764 as_bad (_("memory destination needed for instruction `%s'"
3765 " after `xrelease'"), i.tm.name);
3766 return 0;
3767 }
3768 return 1;
3769 }
3770 }
3771
3772 /* Try the shortest encoding by shortening operand size. */
3773
3774 static void
3775 optimize_encoding (void)
3776 {
3777 int j;
3778
3779 if (optimize_for_space
3780 && i.reg_operands == 1
3781 && i.imm_operands == 1
3782 && !i.types[1].bitfield.byte
3783 && i.op[0].imms->X_op == O_constant
3784 && fits_in_imm7 (i.op[0].imms->X_add_number)
3785 && ((i.tm.base_opcode == 0xa8
3786 && i.tm.extension_opcode == None)
3787 || (i.tm.base_opcode == 0xf6
3788 && i.tm.extension_opcode == 0x0)))
3789 {
3790 /* Optimize: -Os:
3791 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3792 */
3793 unsigned int base_regnum = i.op[1].regs->reg_num;
3794 if (flag_code == CODE_64BIT || base_regnum < 4)
3795 {
3796 i.types[1].bitfield.byte = 1;
3797 /* Ignore the suffix. */
3798 i.suffix = 0;
3799 if (base_regnum >= 4
3800 && !(i.op[1].regs->reg_flags & RegRex))
3801 {
3802 /* Handle SP, BP, SI and DI registers. */
3803 if (i.types[1].bitfield.word)
3804 j = 16;
3805 else if (i.types[1].bitfield.dword)
3806 j = 32;
3807 else
3808 j = 48;
3809 i.op[1].regs -= j;
3810 }
3811 }
3812 }
3813 else if (flag_code == CODE_64BIT
3814 && ((i.types[1].bitfield.qword
3815 && i.reg_operands == 1
3816 && i.imm_operands == 1
3817 && i.op[0].imms->X_op == O_constant
3818 && ((i.tm.base_opcode == 0xb0
3819 && i.tm.extension_opcode == None
3820 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3821 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3822 && (((i.tm.base_opcode == 0x24
3823 || i.tm.base_opcode == 0xa8)
3824 && i.tm.extension_opcode == None)
3825 || (i.tm.base_opcode == 0x80
3826 && i.tm.extension_opcode == 0x4)
3827 || ((i.tm.base_opcode == 0xf6
3828 || i.tm.base_opcode == 0xc6)
3829 && i.tm.extension_opcode == 0x0)))))
3830 || (i.types[0].bitfield.qword
3831 && ((i.reg_operands == 2
3832 && i.op[0].regs == i.op[1].regs
3833 && ((i.tm.base_opcode == 0x30
3834 || i.tm.base_opcode == 0x28)
3835 && i.tm.extension_opcode == None))
3836 || (i.reg_operands == 1
3837 && i.operands == 1
3838 && i.tm.base_opcode == 0x30
3839 && i.tm.extension_opcode == None)))))
3840 {
3841 /* Optimize: -O:
3842 andq $imm31, %r64 -> andl $imm31, %r32
3843 testq $imm31, %r64 -> testl $imm31, %r32
3844 xorq %r64, %r64 -> xorl %r32, %r32
3845 subq %r64, %r64 -> subl %r32, %r32
3846 movq $imm31, %r64 -> movl $imm31, %r32
3847 movq $imm32, %r64 -> movl $imm32, %r32
3848 */
3849 i.tm.opcode_modifier.norex64 = 1;
3850 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3851 {
3852 /* Handle
3853 movq $imm31, %r64 -> movl $imm31, %r32
3854 movq $imm32, %r64 -> movl $imm32, %r32
3855 */
3856 i.tm.operand_types[0].bitfield.imm32 = 1;
3857 i.tm.operand_types[0].bitfield.imm32s = 0;
3858 i.tm.operand_types[0].bitfield.imm64 = 0;
3859 i.types[0].bitfield.imm32 = 1;
3860 i.types[0].bitfield.imm32s = 0;
3861 i.types[0].bitfield.imm64 = 0;
3862 i.types[1].bitfield.dword = 1;
3863 i.types[1].bitfield.qword = 0;
3864 if (i.tm.base_opcode == 0xc6)
3865 {
3866 /* Handle
3867 movq $imm31, %r64 -> movl $imm31, %r32
3868 */
3869 i.tm.base_opcode = 0xb0;
3870 i.tm.extension_opcode = None;
3871 i.tm.opcode_modifier.shortform = 1;
3872 i.tm.opcode_modifier.modrm = 0;
3873 }
3874 }
3875 }
3876 else if (optimize > 1
3877 && i.reg_operands == 3
3878 && i.op[0].regs == i.op[1].regs
3879 && !i.types[2].bitfield.xmmword
3880 && (i.tm.opcode_modifier.vex
3881 || (!i.mask
3882 && !i.rounding
3883 && is_evex_encoding (&i.tm)
3884 && (i.vec_encoding != vex_encoding_evex
3885 || i.tm.cpu_flags.bitfield.cpuavx512vl
3886 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
3887 && ((i.tm.base_opcode == 0x55
3888 || i.tm.base_opcode == 0x6655
3889 || i.tm.base_opcode == 0x66df
3890 || i.tm.base_opcode == 0x57
3891 || i.tm.base_opcode == 0x6657
3892 || i.tm.base_opcode == 0x66ef
3893 || i.tm.base_opcode == 0x66f8
3894 || i.tm.base_opcode == 0x66f9
3895 || i.tm.base_opcode == 0x66fa
3896 || i.tm.base_opcode == 0x66fb)
3897 && i.tm.extension_opcode == None))
3898 {
3899 /* Optimize: -O2:
3900 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3901 vpsubq and vpsubw:
3902 EVEX VOP %zmmM, %zmmM, %zmmN
3903 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3904 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3905 EVEX VOP %ymmM, %ymmM, %ymmN
3906 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3907 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3908 VEX VOP %ymmM, %ymmM, %ymmN
3909 -> VEX VOP %xmmM, %xmmM, %xmmN
3910 VOP, one of vpandn and vpxor:
3911 VEX VOP %ymmM, %ymmM, %ymmN
3912 -> VEX VOP %xmmM, %xmmM, %xmmN
3913 VOP, one of vpandnd and vpandnq:
3914 EVEX VOP %zmmM, %zmmM, %zmmN
3915 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3916 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3917 EVEX VOP %ymmM, %ymmM, %ymmN
3918 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3919 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3920 VOP, one of vpxord and vpxorq:
3921 EVEX VOP %zmmM, %zmmM, %zmmN
3922 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3923 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3924 EVEX VOP %ymmM, %ymmM, %ymmN
3925 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3926 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3927 */
3928 if (is_evex_encoding (&i.tm))
3929 {
3930 if (i.vec_encoding == vex_encoding_evex)
3931 i.tm.opcode_modifier.evex = EVEX128;
3932 else
3933 {
3934 i.tm.opcode_modifier.vex = VEX128;
3935 i.tm.opcode_modifier.vexw = VEXW0;
3936 i.tm.opcode_modifier.evex = 0;
3937 }
3938 }
3939 else
3940 i.tm.opcode_modifier.vex = VEX128;
3941
3942 if (i.tm.opcode_modifier.vex)
3943 for (j = 0; j < 3; j++)
3944 {
3945 i.types[j].bitfield.xmmword = 1;
3946 i.types[j].bitfield.ymmword = 0;
3947 }
3948 }
3949 }
3950
3951 /* This is the guts of the machine-dependent assembler. LINE points to a
3952 machine dependent instruction. This function is supposed to emit
3953 the frags/bytes it assembles to. */
3954
3955 void
3956 md_assemble (char *line)
3957 {
3958 unsigned int j;
3959 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
3960 const insn_template *t;
3961
3962 /* Initialize globals. */
3963 memset (&i, '\0', sizeof (i));
3964 for (j = 0; j < MAX_OPERANDS; j++)
3965 i.reloc[j] = NO_RELOC;
3966 memset (disp_expressions, '\0', sizeof (disp_expressions));
3967 memset (im_expressions, '\0', sizeof (im_expressions));
3968 save_stack_p = save_stack;
3969
3970 /* First parse an instruction mnemonic & call i386_operand for the operands.
3971 We assume that the scrubber has arranged it so that line[0] is the valid
3972 start of a (possibly prefixed) mnemonic. */
3973
3974 line = parse_insn (line, mnemonic);
3975 if (line == NULL)
3976 return;
3977 mnem_suffix = i.suffix;
3978
3979 line = parse_operands (line, mnemonic);
3980 this_operand = -1;
3981 xfree (i.memop1_string);
3982 i.memop1_string = NULL;
3983 if (line == NULL)
3984 return;
3985
3986 /* Now we've parsed the mnemonic into a set of templates, and have the
3987 operands at hand. */
3988
3989 /* All intel opcodes have reversed operands except for "bound" and
3990 "enter". We also don't reverse intersegment "jmp" and "call"
3991 instructions with 2 immediate operands so that the immediate segment
3992 precedes the offset, as it does when in AT&T mode. */
3993 if (intel_syntax
3994 && i.operands > 1
3995 && (strcmp (mnemonic, "bound") != 0)
3996 && (strcmp (mnemonic, "invlpga") != 0)
3997 && !(operand_type_check (i.types[0], imm)
3998 && operand_type_check (i.types[1], imm)))
3999 swap_operands ();
4000
4001 /* The order of the immediates should be reversed
4002 for 2 immediates extrq and insertq instructions */
4003 if (i.imm_operands == 2
4004 && (strcmp (mnemonic, "extrq") == 0
4005 || strcmp (mnemonic, "insertq") == 0))
4006 swap_2_operands (0, 1);
4007
4008 if (i.imm_operands)
4009 optimize_imm ();
4010
4011 /* Don't optimize displacement for movabs since it only takes 64bit
4012 displacement. */
4013 if (i.disp_operands
4014 && i.disp_encoding != disp_encoding_32bit
4015 && (flag_code != CODE_64BIT
4016 || strcmp (mnemonic, "movabs") != 0))
4017 optimize_disp ();
4018
4019 /* Next, we find a template that matches the given insn,
4020 making sure the overlap of the given operands types is consistent
4021 with the template operand types. */
4022
4023 if (!(t = match_template (mnem_suffix)))
4024 return;
4025
4026 if (sse_check != check_none
4027 && !i.tm.opcode_modifier.noavx
4028 && !i.tm.cpu_flags.bitfield.cpuavx
4029 && (i.tm.cpu_flags.bitfield.cpusse
4030 || i.tm.cpu_flags.bitfield.cpusse2
4031 || i.tm.cpu_flags.bitfield.cpusse3
4032 || i.tm.cpu_flags.bitfield.cpussse3
4033 || i.tm.cpu_flags.bitfield.cpusse4_1
4034 || i.tm.cpu_flags.bitfield.cpusse4_2
4035 || i.tm.cpu_flags.bitfield.cpupclmul
4036 || i.tm.cpu_flags.bitfield.cpuaes
4037 || i.tm.cpu_flags.bitfield.cpugfni))
4038 {
4039 (sse_check == check_warning
4040 ? as_warn
4041 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4042 }
4043
4044 /* Zap movzx and movsx suffix. The suffix has been set from
4045 "word ptr" or "byte ptr" on the source operand in Intel syntax
4046 or extracted from mnemonic in AT&T syntax. But we'll use
4047 the destination register to choose the suffix for encoding. */
4048 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4049 {
4050 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4051 there is no suffix, the default will be byte extension. */
4052 if (i.reg_operands != 2
4053 && !i.suffix
4054 && intel_syntax)
4055 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4056
4057 i.suffix = 0;
4058 }
4059
4060 if (i.tm.opcode_modifier.fwait)
4061 if (!add_prefix (FWAIT_OPCODE))
4062 return;
4063
4064 /* Check if REP prefix is OK. */
4065 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4066 {
4067 as_bad (_("invalid instruction `%s' after `%s'"),
4068 i.tm.name, i.rep_prefix);
4069 return;
4070 }
4071
4072 /* Check for lock without a lockable instruction. Destination operand
4073 must be memory unless it is xchg (0x86). */
4074 if (i.prefix[LOCK_PREFIX]
4075 && (!i.tm.opcode_modifier.islockable
4076 || i.mem_operands == 0
4077 || (i.tm.base_opcode != 0x86
4078 && !operand_type_check (i.types[i.operands - 1], anymem))))
4079 {
4080 as_bad (_("expecting lockable instruction after `lock'"));
4081 return;
4082 }
4083
4084 /* Check if HLE prefix is OK. */
4085 if (i.hle_prefix && !check_hle ())
4086 return;
4087
4088 /* Check BND prefix. */
4089 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4090 as_bad (_("expecting valid branch instruction after `bnd'"));
4091
4092 /* Check NOTRACK prefix. */
4093 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4094 as_bad (_("expecting indirect branch instruction after `notrack'"));
4095
4096 if (i.tm.cpu_flags.bitfield.cpumpx)
4097 {
4098 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4099 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4100 else if (flag_code != CODE_16BIT
4101 ? i.prefix[ADDR_PREFIX]
4102 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4103 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4104 }
4105
4106 /* Insert BND prefix. */
4107 if (add_bnd_prefix
4108 && i.tm.opcode_modifier.bndprefixok
4109 && !i.prefix[BND_PREFIX])
4110 add_prefix (BND_PREFIX_OPCODE);
4111
4112 /* Check string instruction segment overrides. */
4113 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4114 {
4115 if (!check_string ())
4116 return;
4117 i.disp_operands = 0;
4118 }
4119
4120 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4121 optimize_encoding ();
4122
4123 if (!process_suffix ())
4124 return;
4125
4126 /* Update operand types. */
4127 for (j = 0; j < i.operands; j++)
4128 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4129
4130 /* Make still unresolved immediate matches conform to size of immediate
4131 given in i.suffix. */
4132 if (!finalize_imm ())
4133 return;
4134
4135 if (i.types[0].bitfield.imm1)
4136 i.imm_operands = 0; /* kludge for shift insns. */
4137
4138 /* We only need to check those implicit registers for instructions
4139 with 3 operands or less. */
4140 if (i.operands <= 3)
4141 for (j = 0; j < i.operands; j++)
4142 if (i.types[j].bitfield.inoutportreg
4143 || i.types[j].bitfield.shiftcount
4144 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4145 i.reg_operands--;
4146
4147 /* ImmExt should be processed after SSE2AVX. */
4148 if (!i.tm.opcode_modifier.sse2avx
4149 && i.tm.opcode_modifier.immext)
4150 process_immext ();
4151
4152 /* For insns with operands there are more diddles to do to the opcode. */
4153 if (i.operands)
4154 {
4155 if (!process_operands ())
4156 return;
4157 }
4158 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4159 {
4160 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4161 as_warn (_("translating to `%sp'"), i.tm.name);
4162 }
4163
4164 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode
4165 || is_evex_encoding (&i.tm))
4166 {
4167 if (flag_code == CODE_16BIT)
4168 {
4169 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4170 i.tm.name);
4171 return;
4172 }
4173
4174 if (i.tm.opcode_modifier.vex)
4175 build_vex_prefix (t);
4176 else
4177 build_evex_prefix ();
4178 }
4179
4180 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4181 instructions may define INT_OPCODE as well, so avoid this corner
4182 case for those instructions that use MODRM. */
4183 if (i.tm.base_opcode == INT_OPCODE
4184 && !i.tm.opcode_modifier.modrm
4185 && i.op[0].imms->X_add_number == 3)
4186 {
4187 i.tm.base_opcode = INT3_OPCODE;
4188 i.imm_operands = 0;
4189 }
4190
4191 if ((i.tm.opcode_modifier.jump
4192 || i.tm.opcode_modifier.jumpbyte
4193 || i.tm.opcode_modifier.jumpdword)
4194 && i.op[0].disps->X_op == O_constant)
4195 {
4196 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4197 the absolute address given by the constant. Since ix86 jumps and
4198 calls are pc relative, we need to generate a reloc. */
4199 i.op[0].disps->X_add_symbol = &abs_symbol;
4200 i.op[0].disps->X_op = O_symbol;
4201 }
4202
4203 if (i.tm.opcode_modifier.rex64)
4204 i.rex |= REX_W;
4205
4206 /* For 8 bit registers we need an empty rex prefix. Also if the
4207 instruction already has a prefix, we need to convert old
4208 registers to new ones. */
4209
4210 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4211 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4212 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4213 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4214 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4215 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4216 && i.rex != 0))
4217 {
4218 int x;
4219
4220 i.rex |= REX_OPCODE;
4221 for (x = 0; x < 2; x++)
4222 {
4223 /* Look for 8 bit operand that uses old registers. */
4224 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4225 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4226 {
4227 /* In case it is "hi" register, give up. */
4228 if (i.op[x].regs->reg_num > 3)
4229 as_bad (_("can't encode register '%s%s' in an "
4230 "instruction requiring REX prefix."),
4231 register_prefix, i.op[x].regs->reg_name);
4232
4233 /* Otherwise it is equivalent to the extended register.
4234 Since the encoding doesn't change this is merely
4235 cosmetic cleanup for debug output. */
4236
4237 i.op[x].regs = i.op[x].regs + 8;
4238 }
4239 }
4240 }
4241
4242 if (i.rex == 0 && i.rex_encoding)
4243 {
4244 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4245 that uses legacy register. If it is "hi" register, don't add
4246 the REX_OPCODE byte. */
4247 int x;
4248 for (x = 0; x < 2; x++)
4249 if (i.types[x].bitfield.reg
4250 && i.types[x].bitfield.byte
4251 && (i.op[x].regs->reg_flags & RegRex64) == 0
4252 && i.op[x].regs->reg_num > 3)
4253 {
4254 i.rex_encoding = FALSE;
4255 break;
4256 }
4257
4258 if (i.rex_encoding)
4259 i.rex = REX_OPCODE;
4260 }
4261
4262 if (i.rex != 0)
4263 add_prefix (REX_OPCODE | i.rex);
4264
4265 /* We are ready to output the insn. */
4266 output_insn ();
4267 }
4268
4269 static char *
4270 parse_insn (char *line, char *mnemonic)
4271 {
4272 char *l = line;
4273 char *token_start = l;
4274 char *mnem_p;
4275 int supported;
4276 const insn_template *t;
4277 char *dot_p = NULL;
4278
4279 while (1)
4280 {
4281 mnem_p = mnemonic;
4282 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4283 {
4284 if (*mnem_p == '.')
4285 dot_p = mnem_p;
4286 mnem_p++;
4287 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4288 {
4289 as_bad (_("no such instruction: `%s'"), token_start);
4290 return NULL;
4291 }
4292 l++;
4293 }
4294 if (!is_space_char (*l)
4295 && *l != END_OF_INSN
4296 && (intel_syntax
4297 || (*l != PREFIX_SEPARATOR
4298 && *l != ',')))
4299 {
4300 as_bad (_("invalid character %s in mnemonic"),
4301 output_invalid (*l));
4302 return NULL;
4303 }
4304 if (token_start == l)
4305 {
4306 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4307 as_bad (_("expecting prefix; got nothing"));
4308 else
4309 as_bad (_("expecting mnemonic; got nothing"));
4310 return NULL;
4311 }
4312
4313 /* Look up instruction (or prefix) via hash table. */
4314 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4315
4316 if (*l != END_OF_INSN
4317 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4318 && current_templates
4319 && current_templates->start->opcode_modifier.isprefix)
4320 {
4321 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4322 {
4323 as_bad ((flag_code != CODE_64BIT
4324 ? _("`%s' is only supported in 64-bit mode")
4325 : _("`%s' is not supported in 64-bit mode")),
4326 current_templates->start->name);
4327 return NULL;
4328 }
4329 /* If we are in 16-bit mode, do not allow addr16 or data16.
4330 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4331 if ((current_templates->start->opcode_modifier.size16
4332 || current_templates->start->opcode_modifier.size32)
4333 && flag_code != CODE_64BIT
4334 && (current_templates->start->opcode_modifier.size32
4335 ^ (flag_code == CODE_16BIT)))
4336 {
4337 as_bad (_("redundant %s prefix"),
4338 current_templates->start->name);
4339 return NULL;
4340 }
4341 if (current_templates->start->opcode_length == 0)
4342 {
4343 /* Handle pseudo prefixes. */
4344 switch (current_templates->start->base_opcode)
4345 {
4346 case 0x0:
4347 /* {disp8} */
4348 i.disp_encoding = disp_encoding_8bit;
4349 break;
4350 case 0x1:
4351 /* {disp32} */
4352 i.disp_encoding = disp_encoding_32bit;
4353 break;
4354 case 0x2:
4355 /* {load} */
4356 i.dir_encoding = dir_encoding_load;
4357 break;
4358 case 0x3:
4359 /* {store} */
4360 i.dir_encoding = dir_encoding_store;
4361 break;
4362 case 0x4:
4363 /* {vex2} */
4364 i.vec_encoding = vex_encoding_vex2;
4365 break;
4366 case 0x5:
4367 /* {vex3} */
4368 i.vec_encoding = vex_encoding_vex3;
4369 break;
4370 case 0x6:
4371 /* {evex} */
4372 i.vec_encoding = vex_encoding_evex;
4373 break;
4374 case 0x7:
4375 /* {rex} */
4376 i.rex_encoding = TRUE;
4377 break;
4378 case 0x8:
4379 /* {nooptimize} */
4380 i.no_optimize = TRUE;
4381 break;
4382 default:
4383 abort ();
4384 }
4385 }
4386 else
4387 {
4388 /* Add prefix, checking for repeated prefixes. */
4389 switch (add_prefix (current_templates->start->base_opcode))
4390 {
4391 case PREFIX_EXIST:
4392 return NULL;
4393 case PREFIX_DS:
4394 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4395 i.notrack_prefix = current_templates->start->name;
4396 break;
4397 case PREFIX_REP:
4398 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4399 i.hle_prefix = current_templates->start->name;
4400 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4401 i.bnd_prefix = current_templates->start->name;
4402 else
4403 i.rep_prefix = current_templates->start->name;
4404 break;
4405 default:
4406 break;
4407 }
4408 }
4409 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4410 token_start = ++l;
4411 }
4412 else
4413 break;
4414 }
4415
4416 if (!current_templates)
4417 {
4418 /* Check if we should swap operand or force 32bit displacement in
4419 encoding. */
4420 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4421 i.dir_encoding = dir_encoding_store;
4422 else if (mnem_p - 3 == dot_p
4423 && dot_p[1] == 'd'
4424 && dot_p[2] == '8')
4425 i.disp_encoding = disp_encoding_8bit;
4426 else if (mnem_p - 4 == dot_p
4427 && dot_p[1] == 'd'
4428 && dot_p[2] == '3'
4429 && dot_p[3] == '2')
4430 i.disp_encoding = disp_encoding_32bit;
4431 else
4432 goto check_suffix;
4433 mnem_p = dot_p;
4434 *dot_p = '\0';
4435 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4436 }
4437
4438 if (!current_templates)
4439 {
4440 check_suffix:
4441 /* See if we can get a match by trimming off a suffix. */
4442 switch (mnem_p[-1])
4443 {
4444 case WORD_MNEM_SUFFIX:
4445 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4446 i.suffix = SHORT_MNEM_SUFFIX;
4447 else
4448 /* Fall through. */
4449 case BYTE_MNEM_SUFFIX:
4450 case QWORD_MNEM_SUFFIX:
4451 i.suffix = mnem_p[-1];
4452 mnem_p[-1] = '\0';
4453 current_templates = (const templates *) hash_find (op_hash,
4454 mnemonic);
4455 break;
4456 case SHORT_MNEM_SUFFIX:
4457 case LONG_MNEM_SUFFIX:
4458 if (!intel_syntax)
4459 {
4460 i.suffix = mnem_p[-1];
4461 mnem_p[-1] = '\0';
4462 current_templates = (const templates *) hash_find (op_hash,
4463 mnemonic);
4464 }
4465 break;
4466
4467 /* Intel Syntax. */
4468 case 'd':
4469 if (intel_syntax)
4470 {
4471 if (intel_float_operand (mnemonic) == 1)
4472 i.suffix = SHORT_MNEM_SUFFIX;
4473 else
4474 i.suffix = LONG_MNEM_SUFFIX;
4475 mnem_p[-1] = '\0';
4476 current_templates = (const templates *) hash_find (op_hash,
4477 mnemonic);
4478 }
4479 break;
4480 }
4481 if (!current_templates)
4482 {
4483 as_bad (_("no such instruction: `%s'"), token_start);
4484 return NULL;
4485 }
4486 }
4487
4488 if (current_templates->start->opcode_modifier.jump
4489 || current_templates->start->opcode_modifier.jumpbyte)
4490 {
4491 /* Check for a branch hint. We allow ",pt" and ",pn" for
4492 predict taken and predict not taken respectively.
4493 I'm not sure that branch hints actually do anything on loop
4494 and jcxz insns (JumpByte) for current Pentium4 chips. They
4495 may work in the future and it doesn't hurt to accept them
4496 now. */
4497 if (l[0] == ',' && l[1] == 'p')
4498 {
4499 if (l[2] == 't')
4500 {
4501 if (!add_prefix (DS_PREFIX_OPCODE))
4502 return NULL;
4503 l += 3;
4504 }
4505 else if (l[2] == 'n')
4506 {
4507 if (!add_prefix (CS_PREFIX_OPCODE))
4508 return NULL;
4509 l += 3;
4510 }
4511 }
4512 }
4513 /* Any other comma loses. */
4514 if (*l == ',')
4515 {
4516 as_bad (_("invalid character %s in mnemonic"),
4517 output_invalid (*l));
4518 return NULL;
4519 }
4520
4521 /* Check if instruction is supported on specified architecture. */
4522 supported = 0;
4523 for (t = current_templates->start; t < current_templates->end; ++t)
4524 {
4525 supported |= cpu_flags_match (t);
4526 if (supported == CPU_FLAGS_PERFECT_MATCH)
4527 {
4528 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4529 as_warn (_("use .code16 to ensure correct addressing mode"));
4530
4531 return l;
4532 }
4533 }
4534
4535 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4536 as_bad (flag_code == CODE_64BIT
4537 ? _("`%s' is not supported in 64-bit mode")
4538 : _("`%s' is only supported in 64-bit mode"),
4539 current_templates->start->name);
4540 else
4541 as_bad (_("`%s' is not supported on `%s%s'"),
4542 current_templates->start->name,
4543 cpu_arch_name ? cpu_arch_name : default_arch,
4544 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4545
4546 return NULL;
4547 }
4548
4549 static char *
4550 parse_operands (char *l, const char *mnemonic)
4551 {
4552 char *token_start;
4553
4554 /* 1 if operand is pending after ','. */
4555 unsigned int expecting_operand = 0;
4556
4557 /* Non-zero if operand parens not balanced. */
4558 unsigned int paren_not_balanced;
4559
4560 while (*l != END_OF_INSN)
4561 {
4562 /* Skip optional white space before operand. */
4563 if (is_space_char (*l))
4564 ++l;
4565 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4566 {
4567 as_bad (_("invalid character %s before operand %d"),
4568 output_invalid (*l),
4569 i.operands + 1);
4570 return NULL;
4571 }
4572 token_start = l; /* After white space. */
4573 paren_not_balanced = 0;
4574 while (paren_not_balanced || *l != ',')
4575 {
4576 if (*l == END_OF_INSN)
4577 {
4578 if (paren_not_balanced)
4579 {
4580 if (!intel_syntax)
4581 as_bad (_("unbalanced parenthesis in operand %d."),
4582 i.operands + 1);
4583 else
4584 as_bad (_("unbalanced brackets in operand %d."),
4585 i.operands + 1);
4586 return NULL;
4587 }
4588 else
4589 break; /* we are done */
4590 }
4591 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4592 {
4593 as_bad (_("invalid character %s in operand %d"),
4594 output_invalid (*l),
4595 i.operands + 1);
4596 return NULL;
4597 }
4598 if (!intel_syntax)
4599 {
4600 if (*l == '(')
4601 ++paren_not_balanced;
4602 if (*l == ')')
4603 --paren_not_balanced;
4604 }
4605 else
4606 {
4607 if (*l == '[')
4608 ++paren_not_balanced;
4609 if (*l == ']')
4610 --paren_not_balanced;
4611 }
4612 l++;
4613 }
4614 if (l != token_start)
4615 { /* Yes, we've read in another operand. */
4616 unsigned int operand_ok;
4617 this_operand = i.operands++;
4618 if (i.operands > MAX_OPERANDS)
4619 {
4620 as_bad (_("spurious operands; (%d operands/instruction max)"),
4621 MAX_OPERANDS);
4622 return NULL;
4623 }
4624 i.types[this_operand].bitfield.unspecified = 1;
4625 /* Now parse operand adding info to 'i' as we go along. */
4626 END_STRING_AND_SAVE (l);
4627
4628 if (intel_syntax)
4629 operand_ok =
4630 i386_intel_operand (token_start,
4631 intel_float_operand (mnemonic));
4632 else
4633 operand_ok = i386_att_operand (token_start);
4634
4635 RESTORE_END_STRING (l);
4636 if (!operand_ok)
4637 return NULL;
4638 }
4639 else
4640 {
4641 if (expecting_operand)
4642 {
4643 expecting_operand_after_comma:
4644 as_bad (_("expecting operand after ','; got nothing"));
4645 return NULL;
4646 }
4647 if (*l == ',')
4648 {
4649 as_bad (_("expecting operand before ','; got nothing"));
4650 return NULL;
4651 }
4652 }
4653
4654 /* Now *l must be either ',' or END_OF_INSN. */
4655 if (*l == ',')
4656 {
4657 if (*++l == END_OF_INSN)
4658 {
4659 /* Just skip it, if it's \n complain. */
4660 goto expecting_operand_after_comma;
4661 }
4662 expecting_operand = 1;
4663 }
4664 }
4665 return l;
4666 }
4667
4668 static void
4669 swap_2_operands (int xchg1, int xchg2)
4670 {
4671 union i386_op temp_op;
4672 i386_operand_type temp_type;
4673 enum bfd_reloc_code_real temp_reloc;
4674
4675 temp_type = i.types[xchg2];
4676 i.types[xchg2] = i.types[xchg1];
4677 i.types[xchg1] = temp_type;
4678 temp_op = i.op[xchg2];
4679 i.op[xchg2] = i.op[xchg1];
4680 i.op[xchg1] = temp_op;
4681 temp_reloc = i.reloc[xchg2];
4682 i.reloc[xchg2] = i.reloc[xchg1];
4683 i.reloc[xchg1] = temp_reloc;
4684
4685 if (i.mask)
4686 {
4687 if (i.mask->operand == xchg1)
4688 i.mask->operand = xchg2;
4689 else if (i.mask->operand == xchg2)
4690 i.mask->operand = xchg1;
4691 }
4692 if (i.broadcast)
4693 {
4694 if (i.broadcast->operand == xchg1)
4695 i.broadcast->operand = xchg2;
4696 else if (i.broadcast->operand == xchg2)
4697 i.broadcast->operand = xchg1;
4698 }
4699 if (i.rounding)
4700 {
4701 if (i.rounding->operand == xchg1)
4702 i.rounding->operand = xchg2;
4703 else if (i.rounding->operand == xchg2)
4704 i.rounding->operand = xchg1;
4705 }
4706 }
4707
4708 static void
4709 swap_operands (void)
4710 {
4711 switch (i.operands)
4712 {
4713 case 5:
4714 case 4:
4715 swap_2_operands (1, i.operands - 2);
4716 /* Fall through. */
4717 case 3:
4718 case 2:
4719 swap_2_operands (0, i.operands - 1);
4720 break;
4721 default:
4722 abort ();
4723 }
4724
4725 if (i.mem_operands == 2)
4726 {
4727 const seg_entry *temp_seg;
4728 temp_seg = i.seg[0];
4729 i.seg[0] = i.seg[1];
4730 i.seg[1] = temp_seg;
4731 }
4732 }
4733
4734 /* Try to ensure constant immediates are represented in the smallest
4735 opcode possible. */
4736 static void
4737 optimize_imm (void)
4738 {
4739 char guess_suffix = 0;
4740 int op;
4741
4742 if (i.suffix)
4743 guess_suffix = i.suffix;
4744 else if (i.reg_operands)
4745 {
4746 /* Figure out a suffix from the last register operand specified.
4747 We can't do this properly yet, ie. excluding InOutPortReg,
4748 but the following works for instructions with immediates.
4749 In any case, we can't set i.suffix yet. */
4750 for (op = i.operands; --op >= 0;)
4751 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4752 {
4753 guess_suffix = BYTE_MNEM_SUFFIX;
4754 break;
4755 }
4756 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4757 {
4758 guess_suffix = WORD_MNEM_SUFFIX;
4759 break;
4760 }
4761 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4762 {
4763 guess_suffix = LONG_MNEM_SUFFIX;
4764 break;
4765 }
4766 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4767 {
4768 guess_suffix = QWORD_MNEM_SUFFIX;
4769 break;
4770 }
4771 }
4772 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4773 guess_suffix = WORD_MNEM_SUFFIX;
4774
4775 for (op = i.operands; --op >= 0;)
4776 if (operand_type_check (i.types[op], imm))
4777 {
4778 switch (i.op[op].imms->X_op)
4779 {
4780 case O_constant:
4781 /* If a suffix is given, this operand may be shortened. */
4782 switch (guess_suffix)
4783 {
4784 case LONG_MNEM_SUFFIX:
4785 i.types[op].bitfield.imm32 = 1;
4786 i.types[op].bitfield.imm64 = 1;
4787 break;
4788 case WORD_MNEM_SUFFIX:
4789 i.types[op].bitfield.imm16 = 1;
4790 i.types[op].bitfield.imm32 = 1;
4791 i.types[op].bitfield.imm32s = 1;
4792 i.types[op].bitfield.imm64 = 1;
4793 break;
4794 case BYTE_MNEM_SUFFIX:
4795 i.types[op].bitfield.imm8 = 1;
4796 i.types[op].bitfield.imm8s = 1;
4797 i.types[op].bitfield.imm16 = 1;
4798 i.types[op].bitfield.imm32 = 1;
4799 i.types[op].bitfield.imm32s = 1;
4800 i.types[op].bitfield.imm64 = 1;
4801 break;
4802 }
4803
4804 /* If this operand is at most 16 bits, convert it
4805 to a signed 16 bit number before trying to see
4806 whether it will fit in an even smaller size.
4807 This allows a 16-bit operand such as $0xffe0 to
4808 be recognised as within Imm8S range. */
4809 if ((i.types[op].bitfield.imm16)
4810 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4811 {
4812 i.op[op].imms->X_add_number =
4813 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4814 }
4815 #ifdef BFD64
4816 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4817 if ((i.types[op].bitfield.imm32)
4818 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4819 == 0))
4820 {
4821 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4822 ^ ((offsetT) 1 << 31))
4823 - ((offsetT) 1 << 31));
4824 }
4825 #endif
4826 i.types[op]
4827 = operand_type_or (i.types[op],
4828 smallest_imm_type (i.op[op].imms->X_add_number));
4829
4830 /* We must avoid matching of Imm32 templates when 64bit
4831 only immediate is available. */
4832 if (guess_suffix == QWORD_MNEM_SUFFIX)
4833 i.types[op].bitfield.imm32 = 0;
4834 break;
4835
4836 case O_absent:
4837 case O_register:
4838 abort ();
4839
4840 /* Symbols and expressions. */
4841 default:
4842 /* Convert symbolic operand to proper sizes for matching, but don't
4843 prevent matching a set of insns that only supports sizes other
4844 than those matching the insn suffix. */
4845 {
4846 i386_operand_type mask, allowed;
4847 const insn_template *t;
4848
4849 operand_type_set (&mask, 0);
4850 operand_type_set (&allowed, 0);
4851
4852 for (t = current_templates->start;
4853 t < current_templates->end;
4854 ++t)
4855 allowed = operand_type_or (allowed,
4856 t->operand_types[op]);
4857 switch (guess_suffix)
4858 {
4859 case QWORD_MNEM_SUFFIX:
4860 mask.bitfield.imm64 = 1;
4861 mask.bitfield.imm32s = 1;
4862 break;
4863 case LONG_MNEM_SUFFIX:
4864 mask.bitfield.imm32 = 1;
4865 break;
4866 case WORD_MNEM_SUFFIX:
4867 mask.bitfield.imm16 = 1;
4868 break;
4869 case BYTE_MNEM_SUFFIX:
4870 mask.bitfield.imm8 = 1;
4871 break;
4872 default:
4873 break;
4874 }
4875 allowed = operand_type_and (mask, allowed);
4876 if (!operand_type_all_zero (&allowed))
4877 i.types[op] = operand_type_and (i.types[op], mask);
4878 }
4879 break;
4880 }
4881 }
4882 }
4883
4884 /* Try to use the smallest displacement type too. */
4885 static void
4886 optimize_disp (void)
4887 {
4888 int op;
4889
4890 for (op = i.operands; --op >= 0;)
4891 if (operand_type_check (i.types[op], disp))
4892 {
4893 if (i.op[op].disps->X_op == O_constant)
4894 {
4895 offsetT op_disp = i.op[op].disps->X_add_number;
4896
4897 if (i.types[op].bitfield.disp16
4898 && (op_disp & ~(offsetT) 0xffff) == 0)
4899 {
4900 /* If this operand is at most 16 bits, convert
4901 to a signed 16 bit number and don't use 64bit
4902 displacement. */
4903 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4904 i.types[op].bitfield.disp64 = 0;
4905 }
4906 #ifdef BFD64
4907 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4908 if (i.types[op].bitfield.disp32
4909 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4910 {
4911 /* If this operand is at most 32 bits, convert
4912 to a signed 32 bit number and don't use 64bit
4913 displacement. */
4914 op_disp &= (((offsetT) 2 << 31) - 1);
4915 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4916 i.types[op].bitfield.disp64 = 0;
4917 }
4918 #endif
4919 if (!op_disp && i.types[op].bitfield.baseindex)
4920 {
4921 i.types[op].bitfield.disp8 = 0;
4922 i.types[op].bitfield.disp16 = 0;
4923 i.types[op].bitfield.disp32 = 0;
4924 i.types[op].bitfield.disp32s = 0;
4925 i.types[op].bitfield.disp64 = 0;
4926 i.op[op].disps = 0;
4927 i.disp_operands--;
4928 }
4929 else if (flag_code == CODE_64BIT)
4930 {
4931 if (fits_in_signed_long (op_disp))
4932 {
4933 i.types[op].bitfield.disp64 = 0;
4934 i.types[op].bitfield.disp32s = 1;
4935 }
4936 if (i.prefix[ADDR_PREFIX]
4937 && fits_in_unsigned_long (op_disp))
4938 i.types[op].bitfield.disp32 = 1;
4939 }
4940 if ((i.types[op].bitfield.disp32
4941 || i.types[op].bitfield.disp32s
4942 || i.types[op].bitfield.disp16)
4943 && fits_in_disp8 (op_disp))
4944 i.types[op].bitfield.disp8 = 1;
4945 }
4946 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4947 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4948 {
4949 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4950 i.op[op].disps, 0, i.reloc[op]);
4951 i.types[op].bitfield.disp8 = 0;
4952 i.types[op].bitfield.disp16 = 0;
4953 i.types[op].bitfield.disp32 = 0;
4954 i.types[op].bitfield.disp32s = 0;
4955 i.types[op].bitfield.disp64 = 0;
4956 }
4957 else
4958 /* We only support 64bit displacement on constants. */
4959 i.types[op].bitfield.disp64 = 0;
4960 }
4961 }
4962
4963 /* Check if operands are valid for the instruction. */
4964
4965 static int
4966 check_VecOperands (const insn_template *t)
4967 {
4968 unsigned int op;
4969
4970 /* Without VSIB byte, we can't have a vector register for index. */
4971 if (!t->opcode_modifier.vecsib
4972 && i.index_reg
4973 && (i.index_reg->reg_type.bitfield.xmmword
4974 || i.index_reg->reg_type.bitfield.ymmword
4975 || i.index_reg->reg_type.bitfield.zmmword))
4976 {
4977 i.error = unsupported_vector_index_register;
4978 return 1;
4979 }
4980
4981 /* Check if default mask is allowed. */
4982 if (t->opcode_modifier.nodefmask
4983 && (!i.mask || i.mask->mask->reg_num == 0))
4984 {
4985 i.error = no_default_mask;
4986 return 1;
4987 }
4988
4989 /* For VSIB byte, we need a vector register for index, and all vector
4990 registers must be distinct. */
4991 if (t->opcode_modifier.vecsib)
4992 {
4993 if (!i.index_reg
4994 || !((t->opcode_modifier.vecsib == VecSIB128
4995 && i.index_reg->reg_type.bitfield.xmmword)
4996 || (t->opcode_modifier.vecsib == VecSIB256
4997 && i.index_reg->reg_type.bitfield.ymmword)
4998 || (t->opcode_modifier.vecsib == VecSIB512
4999 && i.index_reg->reg_type.bitfield.zmmword)))
5000 {
5001 i.error = invalid_vsib_address;
5002 return 1;
5003 }
5004
5005 gas_assert (i.reg_operands == 2 || i.mask);
5006 if (i.reg_operands == 2 && !i.mask)
5007 {
5008 gas_assert (i.types[0].bitfield.regsimd);
5009 gas_assert (i.types[0].bitfield.xmmword
5010 || i.types[0].bitfield.ymmword);
5011 gas_assert (i.types[2].bitfield.regsimd);
5012 gas_assert (i.types[2].bitfield.xmmword
5013 || i.types[2].bitfield.ymmword);
5014 if (operand_check == check_none)
5015 return 0;
5016 if (register_number (i.op[0].regs)
5017 != register_number (i.index_reg)
5018 && register_number (i.op[2].regs)
5019 != register_number (i.index_reg)
5020 && register_number (i.op[0].regs)
5021 != register_number (i.op[2].regs))
5022 return 0;
5023 if (operand_check == check_error)
5024 {
5025 i.error = invalid_vector_register_set;
5026 return 1;
5027 }
5028 as_warn (_("mask, index, and destination registers should be distinct"));
5029 }
5030 else if (i.reg_operands == 1 && i.mask)
5031 {
5032 if (i.types[1].bitfield.regsimd
5033 && (i.types[1].bitfield.xmmword
5034 || i.types[1].bitfield.ymmword
5035 || i.types[1].bitfield.zmmword)
5036 && (register_number (i.op[1].regs)
5037 == register_number (i.index_reg)))
5038 {
5039 if (operand_check == check_error)
5040 {
5041 i.error = invalid_vector_register_set;
5042 return 1;
5043 }
5044 if (operand_check != check_none)
5045 as_warn (_("index and destination registers should be distinct"));
5046 }
5047 }
5048 }
5049
5050 /* Check if broadcast is supported by the instruction and is applied
5051 to the memory operand. */
5052 if (i.broadcast)
5053 {
5054 i386_operand_type type, overlap;
5055
5056 /* Check if specified broadcast is supported in this instruction,
5057 and it's applied to memory operand of DWORD or QWORD type. */
5058 op = i.broadcast->operand;
5059 if (!t->opcode_modifier.broadcast
5060 || !i.types[op].bitfield.mem
5061 || (!i.types[op].bitfield.unspecified
5062 && (t->operand_types[op].bitfield.dword
5063 ? !i.types[op].bitfield.dword
5064 : !i.types[op].bitfield.qword)))
5065 {
5066 bad_broadcast:
5067 i.error = unsupported_broadcast;
5068 return 1;
5069 }
5070
5071 operand_type_set (&type, 0);
5072 switch ((t->operand_types[op].bitfield.dword ? 4 : 8) * i.broadcast->type)
5073 {
5074 case 8:
5075 type.bitfield.qword = 1;
5076 break;
5077 case 16:
5078 type.bitfield.xmmword = 1;
5079 break;
5080 case 32:
5081 type.bitfield.ymmword = 1;
5082 break;
5083 case 64:
5084 type.bitfield.zmmword = 1;
5085 break;
5086 default:
5087 goto bad_broadcast;
5088 }
5089
5090 overlap = operand_type_and (type, t->operand_types[op]);
5091 if (operand_type_all_zero (&overlap))
5092 goto bad_broadcast;
5093
5094 if (t->opcode_modifier.checkregsize)
5095 {
5096 unsigned int j;
5097
5098 for (j = 0; j < i.operands; ++j)
5099 {
5100 if (j != op
5101 && !operand_type_register_match(i.types[j],
5102 t->operand_types[j],
5103 type,
5104 t->operand_types[op]))
5105 goto bad_broadcast;
5106 }
5107 }
5108 }
5109 /* If broadcast is supported in this instruction, we need to check if
5110 operand of one-element size isn't specified without broadcast. */
5111 else if (t->opcode_modifier.broadcast && i.mem_operands)
5112 {
5113 /* Find memory operand. */
5114 for (op = 0; op < i.operands; op++)
5115 if (operand_type_check (i.types[op], anymem))
5116 break;
5117 gas_assert (op < i.operands);
5118 /* Check size of the memory operand. */
5119 if (t->operand_types[op].bitfield.dword
5120 ? i.types[op].bitfield.dword
5121 : i.types[op].bitfield.qword)
5122 {
5123 i.error = broadcast_needed;
5124 return 1;
5125 }
5126 }
5127 else
5128 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
5129
5130 /* Check if requested masking is supported. */
5131 if (i.mask
5132 && (!t->opcode_modifier.masking
5133 || (i.mask->zeroing
5134 && t->opcode_modifier.masking == MERGING_MASKING)))
5135 {
5136 i.error = unsupported_masking;
5137 return 1;
5138 }
5139
5140 /* Check if masking is applied to dest operand. */
5141 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5142 {
5143 i.error = mask_not_on_destination;
5144 return 1;
5145 }
5146
5147 /* Check RC/SAE. */
5148 if (i.rounding)
5149 {
5150 if ((i.rounding->type != saeonly
5151 && !t->opcode_modifier.staticrounding)
5152 || (i.rounding->type == saeonly
5153 && (t->opcode_modifier.staticrounding
5154 || !t->opcode_modifier.sae)))
5155 {
5156 i.error = unsupported_rc_sae;
5157 return 1;
5158 }
5159 /* If the instruction has several immediate operands and one of
5160 them is rounding, the rounding operand should be the last
5161 immediate operand. */
5162 if (i.imm_operands > 1
5163 && i.rounding->operand != (int) (i.imm_operands - 1))
5164 {
5165 i.error = rc_sae_operand_not_last_imm;
5166 return 1;
5167 }
5168 }
5169
5170 /* Check vector Disp8 operand. */
5171 if (t->opcode_modifier.disp8memshift
5172 && i.disp_encoding != disp_encoding_32bit)
5173 {
5174 if (i.broadcast)
5175 i.memshift = t->operand_types[op].bitfield.dword ? 2 : 3;
5176 else
5177 i.memshift = t->opcode_modifier.disp8memshift;
5178
5179 for (op = 0; op < i.operands; op++)
5180 if (operand_type_check (i.types[op], disp)
5181 && i.op[op].disps->X_op == O_constant)
5182 {
5183 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5184 {
5185 i.types[op].bitfield.disp8 = 1;
5186 return 0;
5187 }
5188 i.types[op].bitfield.disp8 = 0;
5189 }
5190 }
5191
5192 i.memshift = 0;
5193
5194 return 0;
5195 }
5196
5197 /* Check if operands are valid for the instruction. Update VEX
5198 operand types. */
5199
5200 static int
5201 VEX_check_operands (const insn_template *t)
5202 {
5203 if (i.vec_encoding == vex_encoding_evex)
5204 {
5205 /* This instruction must be encoded with EVEX prefix. */
5206 if (!is_evex_encoding (t))
5207 {
5208 i.error = unsupported;
5209 return 1;
5210 }
5211 return 0;
5212 }
5213
5214 if (!t->opcode_modifier.vex)
5215 {
5216 /* This instruction template doesn't have VEX prefix. */
5217 if (i.vec_encoding != vex_encoding_default)
5218 {
5219 i.error = unsupported;
5220 return 1;
5221 }
5222 return 0;
5223 }
5224
5225 /* Only check VEX_Imm4, which must be the first operand. */
5226 if (t->operand_types[0].bitfield.vec_imm4)
5227 {
5228 if (i.op[0].imms->X_op != O_constant
5229 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5230 {
5231 i.error = bad_imm4;
5232 return 1;
5233 }
5234
5235 /* Turn off Imm8 so that update_imm won't complain. */
5236 i.types[0] = vec_imm4;
5237 }
5238
5239 return 0;
5240 }
5241
5242 static const insn_template *
5243 match_template (char mnem_suffix)
5244 {
5245 /* Points to template once we've found it. */
5246 const insn_template *t;
5247 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5248 i386_operand_type overlap4;
5249 unsigned int found_reverse_match;
5250 i386_opcode_modifier suffix_check, mnemsuf_check;
5251 i386_operand_type operand_types [MAX_OPERANDS];
5252 int addr_prefix_disp;
5253 unsigned int j;
5254 unsigned int found_cpu_match;
5255 unsigned int check_register;
5256 enum i386_error specific_error = 0;
5257
5258 #if MAX_OPERANDS != 5
5259 # error "MAX_OPERANDS must be 5."
5260 #endif
5261
5262 found_reverse_match = 0;
5263 addr_prefix_disp = -1;
5264
5265 memset (&suffix_check, 0, sizeof (suffix_check));
5266 if (i.suffix == BYTE_MNEM_SUFFIX)
5267 suffix_check.no_bsuf = 1;
5268 else if (i.suffix == WORD_MNEM_SUFFIX)
5269 suffix_check.no_wsuf = 1;
5270 else if (i.suffix == SHORT_MNEM_SUFFIX)
5271 suffix_check.no_ssuf = 1;
5272 else if (i.suffix == LONG_MNEM_SUFFIX)
5273 suffix_check.no_lsuf = 1;
5274 else if (i.suffix == QWORD_MNEM_SUFFIX)
5275 suffix_check.no_qsuf = 1;
5276 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5277 suffix_check.no_ldsuf = 1;
5278
5279 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5280 if (intel_syntax)
5281 {
5282 switch (mnem_suffix)
5283 {
5284 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5285 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5286 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5287 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5288 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5289 }
5290 }
5291
5292 /* Must have right number of operands. */
5293 i.error = number_of_operands_mismatch;
5294
5295 for (t = current_templates->start; t < current_templates->end; t++)
5296 {
5297 addr_prefix_disp = -1;
5298
5299 if (i.operands != t->operands)
5300 continue;
5301
5302 /* Check processor support. */
5303 i.error = unsupported;
5304 found_cpu_match = (cpu_flags_match (t)
5305 == CPU_FLAGS_PERFECT_MATCH);
5306 if (!found_cpu_match)
5307 continue;
5308
5309 /* Check AT&T mnemonic. */
5310 i.error = unsupported_with_intel_mnemonic;
5311 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5312 continue;
5313
5314 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5315 i.error = unsupported_syntax;
5316 if ((intel_syntax && t->opcode_modifier.attsyntax)
5317 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5318 || (intel64 && t->opcode_modifier.amd64)
5319 || (!intel64 && t->opcode_modifier.intel64))
5320 continue;
5321
5322 /* Check the suffix, except for some instructions in intel mode. */
5323 i.error = invalid_instruction_suffix;
5324 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5325 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5326 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5327 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5328 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5329 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5330 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5331 continue;
5332 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5333 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5334 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5335 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5336 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5337 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5338 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5339 continue;
5340
5341 if (!operand_size_match (t))
5342 continue;
5343
5344 for (j = 0; j < MAX_OPERANDS; j++)
5345 operand_types[j] = t->operand_types[j];
5346
5347 /* In general, don't allow 64-bit operands in 32-bit mode. */
5348 if (i.suffix == QWORD_MNEM_SUFFIX
5349 && flag_code != CODE_64BIT
5350 && (intel_syntax
5351 ? (!t->opcode_modifier.ignoresize
5352 && !intel_float_operand (t->name))
5353 : intel_float_operand (t->name) != 2)
5354 && ((!operand_types[0].bitfield.regmmx
5355 && !operand_types[0].bitfield.regsimd)
5356 || (!operand_types[t->operands > 1].bitfield.regmmx
5357 && !operand_types[t->operands > 1].bitfield.regsimd))
5358 && (t->base_opcode != 0x0fc7
5359 || t->extension_opcode != 1 /* cmpxchg8b */))
5360 continue;
5361
5362 /* In general, don't allow 32-bit operands on pre-386. */
5363 else if (i.suffix == LONG_MNEM_SUFFIX
5364 && !cpu_arch_flags.bitfield.cpui386
5365 && (intel_syntax
5366 ? (!t->opcode_modifier.ignoresize
5367 && !intel_float_operand (t->name))
5368 : intel_float_operand (t->name) != 2)
5369 && ((!operand_types[0].bitfield.regmmx
5370 && !operand_types[0].bitfield.regsimd)
5371 || (!operand_types[t->operands > 1].bitfield.regmmx
5372 && !operand_types[t->operands > 1].bitfield.regsimd)))
5373 continue;
5374
5375 /* Do not verify operands when there are none. */
5376 else
5377 {
5378 if (!t->operands)
5379 /* We've found a match; break out of loop. */
5380 break;
5381 }
5382
5383 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5384 into Disp32/Disp16/Disp32 operand. */
5385 if (i.prefix[ADDR_PREFIX] != 0)
5386 {
5387 /* There should be only one Disp operand. */
5388 switch (flag_code)
5389 {
5390 case CODE_16BIT:
5391 for (j = 0; j < MAX_OPERANDS; j++)
5392 {
5393 if (operand_types[j].bitfield.disp16)
5394 {
5395 addr_prefix_disp = j;
5396 operand_types[j].bitfield.disp32 = 1;
5397 operand_types[j].bitfield.disp16 = 0;
5398 break;
5399 }
5400 }
5401 break;
5402 case CODE_32BIT:
5403 for (j = 0; j < MAX_OPERANDS; j++)
5404 {
5405 if (operand_types[j].bitfield.disp32)
5406 {
5407 addr_prefix_disp = j;
5408 operand_types[j].bitfield.disp32 = 0;
5409 operand_types[j].bitfield.disp16 = 1;
5410 break;
5411 }
5412 }
5413 break;
5414 case CODE_64BIT:
5415 for (j = 0; j < MAX_OPERANDS; j++)
5416 {
5417 if (operand_types[j].bitfield.disp64)
5418 {
5419 addr_prefix_disp = j;
5420 operand_types[j].bitfield.disp64 = 0;
5421 operand_types[j].bitfield.disp32 = 1;
5422 break;
5423 }
5424 }
5425 break;
5426 }
5427 }
5428
5429 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5430 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5431 continue;
5432
5433 /* We check register size if needed. */
5434 check_register = t->opcode_modifier.checkregsize;
5435 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5436 switch (t->operands)
5437 {
5438 case 1:
5439 if (!operand_type_match (overlap0, i.types[0]))
5440 continue;
5441 break;
5442 case 2:
5443 /* xchg %eax, %eax is a special case. It is an alias for nop
5444 only in 32bit mode and we can use opcode 0x90. In 64bit
5445 mode, we can't use 0x90 for xchg %eax, %eax since it should
5446 zero-extend %eax to %rax. */
5447 if (flag_code == CODE_64BIT
5448 && t->base_opcode == 0x90
5449 && operand_type_equal (&i.types [0], &acc32)
5450 && operand_type_equal (&i.types [1], &acc32))
5451 continue;
5452 /* xrelease mov %eax, <disp> is another special case. It must not
5453 match the accumulator-only encoding of mov. */
5454 if (flag_code != CODE_64BIT
5455 && i.hle_prefix
5456 && t->base_opcode == 0xa0
5457 && i.types[0].bitfield.acc
5458 && operand_type_check (i.types[1], anymem))
5459 continue;
5460 /* If we want store form, we reverse direction of operands. */
5461 if (i.dir_encoding == dir_encoding_store
5462 && t->opcode_modifier.d)
5463 goto check_reverse;
5464 /* Fall through. */
5465
5466 case 3:
5467 /* If we want store form, we skip the current load. */
5468 if (i.dir_encoding == dir_encoding_store
5469 && i.mem_operands == 0
5470 && t->opcode_modifier.load)
5471 continue;
5472 /* Fall through. */
5473 case 4:
5474 case 5:
5475 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5476 if (!operand_type_match (overlap0, i.types[0])
5477 || !operand_type_match (overlap1, i.types[1])
5478 || (check_register
5479 && !operand_type_register_match (i.types[0],
5480 operand_types[0],
5481 i.types[1],
5482 operand_types[1])))
5483 {
5484 /* Check if other direction is valid ... */
5485 if (!t->opcode_modifier.d)
5486 continue;
5487
5488 check_reverse:
5489 /* Try reversing direction of operands. */
5490 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5491 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5492 if (!operand_type_match (overlap0, i.types[0])
5493 || !operand_type_match (overlap1, i.types[1])
5494 || (check_register
5495 && !operand_type_register_match (i.types[0],
5496 operand_types[1],
5497 i.types[1],
5498 operand_types[0])))
5499 {
5500 /* Does not match either direction. */
5501 continue;
5502 }
5503 /* found_reverse_match holds which of D or FloatR
5504 we've found. */
5505 if (!t->opcode_modifier.d)
5506 found_reverse_match = 0;
5507 else if (operand_types[0].bitfield.tbyte)
5508 found_reverse_match = Opcode_FloatD;
5509 else
5510 found_reverse_match = Opcode_D;
5511 if (t->opcode_modifier.floatr)
5512 found_reverse_match |= Opcode_FloatR;
5513 }
5514 else
5515 {
5516 /* Found a forward 2 operand match here. */
5517 switch (t->operands)
5518 {
5519 case 5:
5520 overlap4 = operand_type_and (i.types[4],
5521 operand_types[4]);
5522 /* Fall through. */
5523 case 4:
5524 overlap3 = operand_type_and (i.types[3],
5525 operand_types[3]);
5526 /* Fall through. */
5527 case 3:
5528 overlap2 = operand_type_and (i.types[2],
5529 operand_types[2]);
5530 break;
5531 }
5532
5533 switch (t->operands)
5534 {
5535 case 5:
5536 if (!operand_type_match (overlap4, i.types[4])
5537 || !operand_type_register_match (i.types[3],
5538 operand_types[3],
5539 i.types[4],
5540 operand_types[4]))
5541 continue;
5542 /* Fall through. */
5543 case 4:
5544 if (!operand_type_match (overlap3, i.types[3])
5545 || (check_register
5546 && (!operand_type_register_match (i.types[1],
5547 operand_types[1],
5548 i.types[3],
5549 operand_types[3])
5550 || !operand_type_register_match (i.types[2],
5551 operand_types[2],
5552 i.types[3],
5553 operand_types[3]))))
5554 continue;
5555 /* Fall through. */
5556 case 3:
5557 /* Here we make use of the fact that there are no
5558 reverse match 3 operand instructions. */
5559 if (!operand_type_match (overlap2, i.types[2])
5560 || (check_register
5561 && (!operand_type_register_match (i.types[0],
5562 operand_types[0],
5563 i.types[2],
5564 operand_types[2])
5565 || !operand_type_register_match (i.types[1],
5566 operand_types[1],
5567 i.types[2],
5568 operand_types[2]))))
5569 continue;
5570 break;
5571 }
5572 }
5573 /* Found either forward/reverse 2, 3 or 4 operand match here:
5574 slip through to break. */
5575 }
5576 if (!found_cpu_match)
5577 {
5578 found_reverse_match = 0;
5579 continue;
5580 }
5581
5582 /* Check if vector and VEX operands are valid. */
5583 if (check_VecOperands (t) || VEX_check_operands (t))
5584 {
5585 specific_error = i.error;
5586 continue;
5587 }
5588
5589 /* We've found a match; break out of loop. */
5590 break;
5591 }
5592
5593 if (t == current_templates->end)
5594 {
5595 /* We found no match. */
5596 const char *err_msg;
5597 switch (specific_error ? specific_error : i.error)
5598 {
5599 default:
5600 abort ();
5601 case operand_size_mismatch:
5602 err_msg = _("operand size mismatch");
5603 break;
5604 case operand_type_mismatch:
5605 err_msg = _("operand type mismatch");
5606 break;
5607 case register_type_mismatch:
5608 err_msg = _("register type mismatch");
5609 break;
5610 case number_of_operands_mismatch:
5611 err_msg = _("number of operands mismatch");
5612 break;
5613 case invalid_instruction_suffix:
5614 err_msg = _("invalid instruction suffix");
5615 break;
5616 case bad_imm4:
5617 err_msg = _("constant doesn't fit in 4 bits");
5618 break;
5619 case unsupported_with_intel_mnemonic:
5620 err_msg = _("unsupported with Intel mnemonic");
5621 break;
5622 case unsupported_syntax:
5623 err_msg = _("unsupported syntax");
5624 break;
5625 case unsupported:
5626 as_bad (_("unsupported instruction `%s'"),
5627 current_templates->start->name);
5628 return NULL;
5629 case invalid_vsib_address:
5630 err_msg = _("invalid VSIB address");
5631 break;
5632 case invalid_vector_register_set:
5633 err_msg = _("mask, index, and destination registers must be distinct");
5634 break;
5635 case unsupported_vector_index_register:
5636 err_msg = _("unsupported vector index register");
5637 break;
5638 case unsupported_broadcast:
5639 err_msg = _("unsupported broadcast");
5640 break;
5641 case broadcast_not_on_src_operand:
5642 err_msg = _("broadcast not on source memory operand");
5643 break;
5644 case broadcast_needed:
5645 err_msg = _("broadcast is needed for operand of such type");
5646 break;
5647 case unsupported_masking:
5648 err_msg = _("unsupported masking");
5649 break;
5650 case mask_not_on_destination:
5651 err_msg = _("mask not on destination operand");
5652 break;
5653 case no_default_mask:
5654 err_msg = _("default mask isn't allowed");
5655 break;
5656 case unsupported_rc_sae:
5657 err_msg = _("unsupported static rounding/sae");
5658 break;
5659 case rc_sae_operand_not_last_imm:
5660 if (intel_syntax)
5661 err_msg = _("RC/SAE operand must precede immediate operands");
5662 else
5663 err_msg = _("RC/SAE operand must follow immediate operands");
5664 break;
5665 case invalid_register_operand:
5666 err_msg = _("invalid register operand");
5667 break;
5668 }
5669 as_bad (_("%s for `%s'"), err_msg,
5670 current_templates->start->name);
5671 return NULL;
5672 }
5673
5674 if (!quiet_warnings)
5675 {
5676 if (!intel_syntax
5677 && (i.types[0].bitfield.jumpabsolute
5678 != operand_types[0].bitfield.jumpabsolute))
5679 {
5680 as_warn (_("indirect %s without `*'"), t->name);
5681 }
5682
5683 if (t->opcode_modifier.isprefix
5684 && t->opcode_modifier.ignoresize)
5685 {
5686 /* Warn them that a data or address size prefix doesn't
5687 affect assembly of the next line of code. */
5688 as_warn (_("stand-alone `%s' prefix"), t->name);
5689 }
5690 }
5691
5692 /* Copy the template we found. */
5693 i.tm = *t;
5694
5695 if (addr_prefix_disp != -1)
5696 i.tm.operand_types[addr_prefix_disp]
5697 = operand_types[addr_prefix_disp];
5698
5699 if (found_reverse_match)
5700 {
5701 /* If we found a reverse match we must alter the opcode
5702 direction bit. found_reverse_match holds bits to change
5703 (different for int & float insns). */
5704
5705 i.tm.base_opcode ^= found_reverse_match;
5706
5707 i.tm.operand_types[0] = operand_types[1];
5708 i.tm.operand_types[1] = operand_types[0];
5709 }
5710
5711 return t;
5712 }
5713
5714 static int
5715 check_string (void)
5716 {
5717 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5718 if (i.tm.operand_types[mem_op].bitfield.esseg)
5719 {
5720 if (i.seg[0] != NULL && i.seg[0] != &es)
5721 {
5722 as_bad (_("`%s' operand %d must use `%ses' segment"),
5723 i.tm.name,
5724 mem_op + 1,
5725 register_prefix);
5726 return 0;
5727 }
5728 /* There's only ever one segment override allowed per instruction.
5729 This instruction possibly has a legal segment override on the
5730 second operand, so copy the segment to where non-string
5731 instructions store it, allowing common code. */
5732 i.seg[0] = i.seg[1];
5733 }
5734 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5735 {
5736 if (i.seg[1] != NULL && i.seg[1] != &es)
5737 {
5738 as_bad (_("`%s' operand %d must use `%ses' segment"),
5739 i.tm.name,
5740 mem_op + 2,
5741 register_prefix);
5742 return 0;
5743 }
5744 }
5745 return 1;
5746 }
5747
5748 static int
5749 process_suffix (void)
5750 {
5751 /* If matched instruction specifies an explicit instruction mnemonic
5752 suffix, use it. */
5753 if (i.tm.opcode_modifier.size16)
5754 i.suffix = WORD_MNEM_SUFFIX;
5755 else if (i.tm.opcode_modifier.size32)
5756 i.suffix = LONG_MNEM_SUFFIX;
5757 else if (i.tm.opcode_modifier.size64)
5758 i.suffix = QWORD_MNEM_SUFFIX;
5759 else if (i.reg_operands)
5760 {
5761 /* If there's no instruction mnemonic suffix we try to invent one
5762 based on register operands. */
5763 if (!i.suffix)
5764 {
5765 /* We take i.suffix from the last register operand specified,
5766 Destination register type is more significant than source
5767 register type. crc32 in SSE4.2 prefers source register
5768 type. */
5769 if (i.tm.base_opcode == 0xf20f38f1)
5770 {
5771 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5772 i.suffix = WORD_MNEM_SUFFIX;
5773 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5774 i.suffix = LONG_MNEM_SUFFIX;
5775 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5776 i.suffix = QWORD_MNEM_SUFFIX;
5777 }
5778 else if (i.tm.base_opcode == 0xf20f38f0)
5779 {
5780 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5781 i.suffix = BYTE_MNEM_SUFFIX;
5782 }
5783
5784 if (!i.suffix)
5785 {
5786 int op;
5787
5788 if (i.tm.base_opcode == 0xf20f38f1
5789 || i.tm.base_opcode == 0xf20f38f0)
5790 {
5791 /* We have to know the operand size for crc32. */
5792 as_bad (_("ambiguous memory operand size for `%s`"),
5793 i.tm.name);
5794 return 0;
5795 }
5796
5797 for (op = i.operands; --op >= 0;)
5798 if (!i.tm.operand_types[op].bitfield.inoutportreg
5799 && !i.tm.operand_types[op].bitfield.shiftcount)
5800 {
5801 if (!i.types[op].bitfield.reg)
5802 continue;
5803 if (i.types[op].bitfield.byte)
5804 i.suffix = BYTE_MNEM_SUFFIX;
5805 else if (i.types[op].bitfield.word)
5806 i.suffix = WORD_MNEM_SUFFIX;
5807 else if (i.types[op].bitfield.dword)
5808 i.suffix = LONG_MNEM_SUFFIX;
5809 else if (i.types[op].bitfield.qword)
5810 i.suffix = QWORD_MNEM_SUFFIX;
5811 else
5812 continue;
5813 break;
5814 }
5815 }
5816 }
5817 else if (i.suffix == BYTE_MNEM_SUFFIX)
5818 {
5819 if (intel_syntax
5820 && i.tm.opcode_modifier.ignoresize
5821 && i.tm.opcode_modifier.no_bsuf)
5822 i.suffix = 0;
5823 else if (!check_byte_reg ())
5824 return 0;
5825 }
5826 else if (i.suffix == LONG_MNEM_SUFFIX)
5827 {
5828 if (intel_syntax
5829 && i.tm.opcode_modifier.ignoresize
5830 && i.tm.opcode_modifier.no_lsuf
5831 && !i.tm.opcode_modifier.todword
5832 && !i.tm.opcode_modifier.toqword)
5833 i.suffix = 0;
5834 else if (!check_long_reg ())
5835 return 0;
5836 }
5837 else if (i.suffix == QWORD_MNEM_SUFFIX)
5838 {
5839 if (intel_syntax
5840 && i.tm.opcode_modifier.ignoresize
5841 && i.tm.opcode_modifier.no_qsuf
5842 && !i.tm.opcode_modifier.todword
5843 && !i.tm.opcode_modifier.toqword)
5844 i.suffix = 0;
5845 else if (!check_qword_reg ())
5846 return 0;
5847 }
5848 else if (i.suffix == WORD_MNEM_SUFFIX)
5849 {
5850 if (intel_syntax
5851 && i.tm.opcode_modifier.ignoresize
5852 && i.tm.opcode_modifier.no_wsuf)
5853 i.suffix = 0;
5854 else if (!check_word_reg ())
5855 return 0;
5856 }
5857 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5858 /* Do nothing if the instruction is going to ignore the prefix. */
5859 ;
5860 else
5861 abort ();
5862 }
5863 else if (i.tm.opcode_modifier.defaultsize
5864 && !i.suffix
5865 /* exclude fldenv/frstor/fsave/fstenv */
5866 && i.tm.opcode_modifier.no_ssuf)
5867 {
5868 i.suffix = stackop_size;
5869 }
5870 else if (intel_syntax
5871 && !i.suffix
5872 && (i.tm.operand_types[0].bitfield.jumpabsolute
5873 || i.tm.opcode_modifier.jumpbyte
5874 || i.tm.opcode_modifier.jumpintersegment
5875 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5876 && i.tm.extension_opcode <= 3)))
5877 {
5878 switch (flag_code)
5879 {
5880 case CODE_64BIT:
5881 if (!i.tm.opcode_modifier.no_qsuf)
5882 {
5883 i.suffix = QWORD_MNEM_SUFFIX;
5884 break;
5885 }
5886 /* Fall through. */
5887 case CODE_32BIT:
5888 if (!i.tm.opcode_modifier.no_lsuf)
5889 i.suffix = LONG_MNEM_SUFFIX;
5890 break;
5891 case CODE_16BIT:
5892 if (!i.tm.opcode_modifier.no_wsuf)
5893 i.suffix = WORD_MNEM_SUFFIX;
5894 break;
5895 }
5896 }
5897
5898 if (!i.suffix)
5899 {
5900 if (!intel_syntax)
5901 {
5902 if (i.tm.opcode_modifier.w)
5903 {
5904 as_bad (_("no instruction mnemonic suffix given and "
5905 "no register operands; can't size instruction"));
5906 return 0;
5907 }
5908 }
5909 else
5910 {
5911 unsigned int suffixes;
5912
5913 suffixes = !i.tm.opcode_modifier.no_bsuf;
5914 if (!i.tm.opcode_modifier.no_wsuf)
5915 suffixes |= 1 << 1;
5916 if (!i.tm.opcode_modifier.no_lsuf)
5917 suffixes |= 1 << 2;
5918 if (!i.tm.opcode_modifier.no_ldsuf)
5919 suffixes |= 1 << 3;
5920 if (!i.tm.opcode_modifier.no_ssuf)
5921 suffixes |= 1 << 4;
5922 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
5923 suffixes |= 1 << 5;
5924
5925 /* There are more than suffix matches. */
5926 if (i.tm.opcode_modifier.w
5927 || ((suffixes & (suffixes - 1))
5928 && !i.tm.opcode_modifier.defaultsize
5929 && !i.tm.opcode_modifier.ignoresize))
5930 {
5931 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5932 return 0;
5933 }
5934 }
5935 }
5936
5937 /* Change the opcode based on the operand size given by i.suffix. */
5938 switch (i.suffix)
5939 {
5940 /* Size floating point instruction. */
5941 case LONG_MNEM_SUFFIX:
5942 if (i.tm.opcode_modifier.floatmf)
5943 {
5944 i.tm.base_opcode ^= 4;
5945 break;
5946 }
5947 /* fall through */
5948 case WORD_MNEM_SUFFIX:
5949 case QWORD_MNEM_SUFFIX:
5950 /* It's not a byte, select word/dword operation. */
5951 if (i.tm.opcode_modifier.w)
5952 {
5953 if (i.tm.opcode_modifier.shortform)
5954 i.tm.base_opcode |= 8;
5955 else
5956 i.tm.base_opcode |= 1;
5957 }
5958 /* fall through */
5959 case SHORT_MNEM_SUFFIX:
5960 /* Now select between word & dword operations via the operand
5961 size prefix, except for instructions that will ignore this
5962 prefix anyway. */
5963 if (i.tm.opcode_modifier.addrprefixop0)
5964 {
5965 /* The address size override prefix changes the size of the
5966 first operand. */
5967 if ((flag_code == CODE_32BIT
5968 && i.op->regs[0].reg_type.bitfield.word)
5969 || (flag_code != CODE_32BIT
5970 && i.op->regs[0].reg_type.bitfield.dword))
5971 if (!add_prefix (ADDR_PREFIX_OPCODE))
5972 return 0;
5973 }
5974 else if (i.suffix != QWORD_MNEM_SUFFIX
5975 && !i.tm.opcode_modifier.ignoresize
5976 && !i.tm.opcode_modifier.floatmf
5977 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5978 || (flag_code == CODE_64BIT
5979 && i.tm.opcode_modifier.jumpbyte)))
5980 {
5981 unsigned int prefix = DATA_PREFIX_OPCODE;
5982
5983 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5984 prefix = ADDR_PREFIX_OPCODE;
5985
5986 if (!add_prefix (prefix))
5987 return 0;
5988 }
5989
5990 /* Set mode64 for an operand. */
5991 if (i.suffix == QWORD_MNEM_SUFFIX
5992 && flag_code == CODE_64BIT
5993 && !i.tm.opcode_modifier.norex64
5994 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5995 need rex64. */
5996 && ! (i.operands == 2
5997 && i.tm.base_opcode == 0x90
5998 && i.tm.extension_opcode == None
5999 && operand_type_equal (&i.types [0], &acc64)
6000 && operand_type_equal (&i.types [1], &acc64)))
6001 i.rex |= REX_W;
6002
6003 break;
6004 }
6005
6006 return 1;
6007 }
6008
6009 static int
6010 check_byte_reg (void)
6011 {
6012 int op;
6013
6014 for (op = i.operands; --op >= 0;)
6015 {
6016 /* Skip non-register operands. */
6017 if (!i.types[op].bitfield.reg)
6018 continue;
6019
6020 /* If this is an eight bit register, it's OK. If it's the 16 or
6021 32 bit version of an eight bit register, we will just use the
6022 low portion, and that's OK too. */
6023 if (i.types[op].bitfield.byte)
6024 continue;
6025
6026 /* I/O port address operands are OK too. */
6027 if (i.tm.operand_types[op].bitfield.inoutportreg)
6028 continue;
6029
6030 /* crc32 doesn't generate this warning. */
6031 if (i.tm.base_opcode == 0xf20f38f0)
6032 continue;
6033
6034 if ((i.types[op].bitfield.word
6035 || i.types[op].bitfield.dword
6036 || i.types[op].bitfield.qword)
6037 && i.op[op].regs->reg_num < 4
6038 /* Prohibit these changes in 64bit mode, since the lowering
6039 would be more complicated. */
6040 && flag_code != CODE_64BIT)
6041 {
6042 #if REGISTER_WARNINGS
6043 if (!quiet_warnings)
6044 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6045 register_prefix,
6046 (i.op[op].regs + (i.types[op].bitfield.word
6047 ? REGNAM_AL - REGNAM_AX
6048 : REGNAM_AL - REGNAM_EAX))->reg_name,
6049 register_prefix,
6050 i.op[op].regs->reg_name,
6051 i.suffix);
6052 #endif
6053 continue;
6054 }
6055 /* Any other register is bad. */
6056 if (i.types[op].bitfield.reg
6057 || i.types[op].bitfield.regmmx
6058 || i.types[op].bitfield.regsimd
6059 || i.types[op].bitfield.sreg2
6060 || i.types[op].bitfield.sreg3
6061 || i.types[op].bitfield.control
6062 || i.types[op].bitfield.debug
6063 || i.types[op].bitfield.test)
6064 {
6065 as_bad (_("`%s%s' not allowed with `%s%c'"),
6066 register_prefix,
6067 i.op[op].regs->reg_name,
6068 i.tm.name,
6069 i.suffix);
6070 return 0;
6071 }
6072 }
6073 return 1;
6074 }
6075
6076 static int
6077 check_long_reg (void)
6078 {
6079 int op;
6080
6081 for (op = i.operands; --op >= 0;)
6082 /* Skip non-register operands. */
6083 if (!i.types[op].bitfield.reg)
6084 continue;
6085 /* Reject eight bit registers, except where the template requires
6086 them. (eg. movzb) */
6087 else if (i.types[op].bitfield.byte
6088 && (i.tm.operand_types[op].bitfield.reg
6089 || i.tm.operand_types[op].bitfield.acc)
6090 && (i.tm.operand_types[op].bitfield.word
6091 || i.tm.operand_types[op].bitfield.dword))
6092 {
6093 as_bad (_("`%s%s' not allowed with `%s%c'"),
6094 register_prefix,
6095 i.op[op].regs->reg_name,
6096 i.tm.name,
6097 i.suffix);
6098 return 0;
6099 }
6100 /* Warn if the e prefix on a general reg is missing. */
6101 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6102 && i.types[op].bitfield.word
6103 && (i.tm.operand_types[op].bitfield.reg
6104 || i.tm.operand_types[op].bitfield.acc)
6105 && i.tm.operand_types[op].bitfield.dword)
6106 {
6107 /* Prohibit these changes in the 64bit mode, since the
6108 lowering is more complicated. */
6109 if (flag_code == CODE_64BIT)
6110 {
6111 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6112 register_prefix, i.op[op].regs->reg_name,
6113 i.suffix);
6114 return 0;
6115 }
6116 #if REGISTER_WARNINGS
6117 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6118 register_prefix,
6119 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6120 register_prefix, i.op[op].regs->reg_name, i.suffix);
6121 #endif
6122 }
6123 /* Warn if the r prefix on a general reg is present. */
6124 else if (i.types[op].bitfield.qword
6125 && (i.tm.operand_types[op].bitfield.reg
6126 || i.tm.operand_types[op].bitfield.acc)
6127 && i.tm.operand_types[op].bitfield.dword)
6128 {
6129 if (intel_syntax
6130 && i.tm.opcode_modifier.toqword
6131 && !i.types[0].bitfield.regsimd)
6132 {
6133 /* Convert to QWORD. We want REX byte. */
6134 i.suffix = QWORD_MNEM_SUFFIX;
6135 }
6136 else
6137 {
6138 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6139 register_prefix, i.op[op].regs->reg_name,
6140 i.suffix);
6141 return 0;
6142 }
6143 }
6144 return 1;
6145 }
6146
6147 static int
6148 check_qword_reg (void)
6149 {
6150 int op;
6151
6152 for (op = i.operands; --op >= 0; )
6153 /* Skip non-register operands. */
6154 if (!i.types[op].bitfield.reg)
6155 continue;
6156 /* Reject eight bit registers, except where the template requires
6157 them. (eg. movzb) */
6158 else if (i.types[op].bitfield.byte
6159 && (i.tm.operand_types[op].bitfield.reg
6160 || i.tm.operand_types[op].bitfield.acc)
6161 && (i.tm.operand_types[op].bitfield.word
6162 || i.tm.operand_types[op].bitfield.dword))
6163 {
6164 as_bad (_("`%s%s' not allowed with `%s%c'"),
6165 register_prefix,
6166 i.op[op].regs->reg_name,
6167 i.tm.name,
6168 i.suffix);
6169 return 0;
6170 }
6171 /* Warn if the r prefix on a general reg is missing. */
6172 else if ((i.types[op].bitfield.word
6173 || i.types[op].bitfield.dword)
6174 && (i.tm.operand_types[op].bitfield.reg
6175 || i.tm.operand_types[op].bitfield.acc)
6176 && i.tm.operand_types[op].bitfield.qword)
6177 {
6178 /* Prohibit these changes in the 64bit mode, since the
6179 lowering is more complicated. */
6180 if (intel_syntax
6181 && i.tm.opcode_modifier.todword
6182 && !i.types[0].bitfield.regsimd)
6183 {
6184 /* Convert to DWORD. We don't want REX byte. */
6185 i.suffix = LONG_MNEM_SUFFIX;
6186 }
6187 else
6188 {
6189 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6190 register_prefix, i.op[op].regs->reg_name,
6191 i.suffix);
6192 return 0;
6193 }
6194 }
6195 return 1;
6196 }
6197
6198 static int
6199 check_word_reg (void)
6200 {
6201 int op;
6202 for (op = i.operands; --op >= 0;)
6203 /* Skip non-register operands. */
6204 if (!i.types[op].bitfield.reg)
6205 continue;
6206 /* Reject eight bit registers, except where the template requires
6207 them. (eg. movzb) */
6208 else if (i.types[op].bitfield.byte
6209 && (i.tm.operand_types[op].bitfield.reg
6210 || i.tm.operand_types[op].bitfield.acc)
6211 && (i.tm.operand_types[op].bitfield.word
6212 || i.tm.operand_types[op].bitfield.dword))
6213 {
6214 as_bad (_("`%s%s' not allowed with `%s%c'"),
6215 register_prefix,
6216 i.op[op].regs->reg_name,
6217 i.tm.name,
6218 i.suffix);
6219 return 0;
6220 }
6221 /* Warn if the e or r prefix on a general reg is present. */
6222 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6223 && (i.types[op].bitfield.dword
6224 || i.types[op].bitfield.qword)
6225 && (i.tm.operand_types[op].bitfield.reg
6226 || i.tm.operand_types[op].bitfield.acc)
6227 && i.tm.operand_types[op].bitfield.word)
6228 {
6229 /* Prohibit these changes in the 64bit mode, since the
6230 lowering is more complicated. */
6231 if (flag_code == CODE_64BIT)
6232 {
6233 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6234 register_prefix, i.op[op].regs->reg_name,
6235 i.suffix);
6236 return 0;
6237 }
6238 #if REGISTER_WARNINGS
6239 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6240 register_prefix,
6241 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6242 register_prefix, i.op[op].regs->reg_name, i.suffix);
6243 #endif
6244 }
6245 return 1;
6246 }
6247
6248 static int
6249 update_imm (unsigned int j)
6250 {
6251 i386_operand_type overlap = i.types[j];
6252 if ((overlap.bitfield.imm8
6253 || overlap.bitfield.imm8s
6254 || overlap.bitfield.imm16
6255 || overlap.bitfield.imm32
6256 || overlap.bitfield.imm32s
6257 || overlap.bitfield.imm64)
6258 && !operand_type_equal (&overlap, &imm8)
6259 && !operand_type_equal (&overlap, &imm8s)
6260 && !operand_type_equal (&overlap, &imm16)
6261 && !operand_type_equal (&overlap, &imm32)
6262 && !operand_type_equal (&overlap, &imm32s)
6263 && !operand_type_equal (&overlap, &imm64))
6264 {
6265 if (i.suffix)
6266 {
6267 i386_operand_type temp;
6268
6269 operand_type_set (&temp, 0);
6270 if (i.suffix == BYTE_MNEM_SUFFIX)
6271 {
6272 temp.bitfield.imm8 = overlap.bitfield.imm8;
6273 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6274 }
6275 else if (i.suffix == WORD_MNEM_SUFFIX)
6276 temp.bitfield.imm16 = overlap.bitfield.imm16;
6277 else if (i.suffix == QWORD_MNEM_SUFFIX)
6278 {
6279 temp.bitfield.imm64 = overlap.bitfield.imm64;
6280 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6281 }
6282 else
6283 temp.bitfield.imm32 = overlap.bitfield.imm32;
6284 overlap = temp;
6285 }
6286 else if (operand_type_equal (&overlap, &imm16_32_32s)
6287 || operand_type_equal (&overlap, &imm16_32)
6288 || operand_type_equal (&overlap, &imm16_32s))
6289 {
6290 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6291 overlap = imm16;
6292 else
6293 overlap = imm32s;
6294 }
6295 if (!operand_type_equal (&overlap, &imm8)
6296 && !operand_type_equal (&overlap, &imm8s)
6297 && !operand_type_equal (&overlap, &imm16)
6298 && !operand_type_equal (&overlap, &imm32)
6299 && !operand_type_equal (&overlap, &imm32s)
6300 && !operand_type_equal (&overlap, &imm64))
6301 {
6302 as_bad (_("no instruction mnemonic suffix given; "
6303 "can't determine immediate size"));
6304 return 0;
6305 }
6306 }
6307 i.types[j] = overlap;
6308
6309 return 1;
6310 }
6311
6312 static int
6313 finalize_imm (void)
6314 {
6315 unsigned int j, n;
6316
6317 /* Update the first 2 immediate operands. */
6318 n = i.operands > 2 ? 2 : i.operands;
6319 if (n)
6320 {
6321 for (j = 0; j < n; j++)
6322 if (update_imm (j) == 0)
6323 return 0;
6324
6325 /* The 3rd operand can't be immediate operand. */
6326 gas_assert (operand_type_check (i.types[2], imm) == 0);
6327 }
6328
6329 return 1;
6330 }
6331
6332 static int
6333 process_operands (void)
6334 {
6335 /* Default segment register this instruction will use for memory
6336 accesses. 0 means unknown. This is only for optimizing out
6337 unnecessary segment overrides. */
6338 const seg_entry *default_seg = 0;
6339
6340 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6341 {
6342 unsigned int dupl = i.operands;
6343 unsigned int dest = dupl - 1;
6344 unsigned int j;
6345
6346 /* The destination must be an xmm register. */
6347 gas_assert (i.reg_operands
6348 && MAX_OPERANDS > dupl
6349 && operand_type_equal (&i.types[dest], &regxmm));
6350
6351 if (i.tm.operand_types[0].bitfield.acc
6352 && i.tm.operand_types[0].bitfield.xmmword)
6353 {
6354 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6355 {
6356 /* Keep xmm0 for instructions with VEX prefix and 3
6357 sources. */
6358 i.tm.operand_types[0].bitfield.acc = 0;
6359 i.tm.operand_types[0].bitfield.regsimd = 1;
6360 goto duplicate;
6361 }
6362 else
6363 {
6364 /* We remove the first xmm0 and keep the number of
6365 operands unchanged, which in fact duplicates the
6366 destination. */
6367 for (j = 1; j < i.operands; j++)
6368 {
6369 i.op[j - 1] = i.op[j];
6370 i.types[j - 1] = i.types[j];
6371 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6372 }
6373 }
6374 }
6375 else if (i.tm.opcode_modifier.implicit1stxmm0)
6376 {
6377 gas_assert ((MAX_OPERANDS - 1) > dupl
6378 && (i.tm.opcode_modifier.vexsources
6379 == VEX3SOURCES));
6380
6381 /* Add the implicit xmm0 for instructions with VEX prefix
6382 and 3 sources. */
6383 for (j = i.operands; j > 0; j--)
6384 {
6385 i.op[j] = i.op[j - 1];
6386 i.types[j] = i.types[j - 1];
6387 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6388 }
6389 i.op[0].regs
6390 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6391 i.types[0] = regxmm;
6392 i.tm.operand_types[0] = regxmm;
6393
6394 i.operands += 2;
6395 i.reg_operands += 2;
6396 i.tm.operands += 2;
6397
6398 dupl++;
6399 dest++;
6400 i.op[dupl] = i.op[dest];
6401 i.types[dupl] = i.types[dest];
6402 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6403 }
6404 else
6405 {
6406 duplicate:
6407 i.operands++;
6408 i.reg_operands++;
6409 i.tm.operands++;
6410
6411 i.op[dupl] = i.op[dest];
6412 i.types[dupl] = i.types[dest];
6413 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6414 }
6415
6416 if (i.tm.opcode_modifier.immext)
6417 process_immext ();
6418 }
6419 else if (i.tm.operand_types[0].bitfield.acc
6420 && i.tm.operand_types[0].bitfield.xmmword)
6421 {
6422 unsigned int j;
6423
6424 for (j = 1; j < i.operands; j++)
6425 {
6426 i.op[j - 1] = i.op[j];
6427 i.types[j - 1] = i.types[j];
6428
6429 /* We need to adjust fields in i.tm since they are used by
6430 build_modrm_byte. */
6431 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6432 }
6433
6434 i.operands--;
6435 i.reg_operands--;
6436 i.tm.operands--;
6437 }
6438 else if (i.tm.opcode_modifier.implicitquadgroup)
6439 {
6440 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6441
6442 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6443 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6444 regnum = register_number (i.op[1].regs);
6445 first_reg_in_group = regnum & ~3;
6446 last_reg_in_group = first_reg_in_group + 3;
6447 if (regnum != first_reg_in_group)
6448 as_warn (_("source register `%s%s' implicitly denotes"
6449 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6450 register_prefix, i.op[1].regs->reg_name,
6451 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6452 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6453 i.tm.name);
6454 }
6455 else if (i.tm.opcode_modifier.regkludge)
6456 {
6457 /* The imul $imm, %reg instruction is converted into
6458 imul $imm, %reg, %reg, and the clr %reg instruction
6459 is converted into xor %reg, %reg. */
6460
6461 unsigned int first_reg_op;
6462
6463 if (operand_type_check (i.types[0], reg))
6464 first_reg_op = 0;
6465 else
6466 first_reg_op = 1;
6467 /* Pretend we saw the extra register operand. */
6468 gas_assert (i.reg_operands == 1
6469 && i.op[first_reg_op + 1].regs == 0);
6470 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6471 i.types[first_reg_op + 1] = i.types[first_reg_op];
6472 i.operands++;
6473 i.reg_operands++;
6474 }
6475
6476 if (i.tm.opcode_modifier.shortform)
6477 {
6478 if (i.types[0].bitfield.sreg2
6479 || i.types[0].bitfield.sreg3)
6480 {
6481 if (i.tm.base_opcode == POP_SEG_SHORT
6482 && i.op[0].regs->reg_num == 1)
6483 {
6484 as_bad (_("you can't `pop %scs'"), register_prefix);
6485 return 0;
6486 }
6487 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6488 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6489 i.rex |= REX_B;
6490 }
6491 else
6492 {
6493 /* The register or float register operand is in operand
6494 0 or 1. */
6495 unsigned int op;
6496
6497 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6498 || operand_type_check (i.types[0], reg))
6499 op = 0;
6500 else
6501 op = 1;
6502 /* Register goes in low 3 bits of opcode. */
6503 i.tm.base_opcode |= i.op[op].regs->reg_num;
6504 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6505 i.rex |= REX_B;
6506 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6507 {
6508 /* Warn about some common errors, but press on regardless.
6509 The first case can be generated by gcc (<= 2.8.1). */
6510 if (i.operands == 2)
6511 {
6512 /* Reversed arguments on faddp, fsubp, etc. */
6513 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6514 register_prefix, i.op[!intel_syntax].regs->reg_name,
6515 register_prefix, i.op[intel_syntax].regs->reg_name);
6516 }
6517 else
6518 {
6519 /* Extraneous `l' suffix on fp insn. */
6520 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6521 register_prefix, i.op[0].regs->reg_name);
6522 }
6523 }
6524 }
6525 }
6526 else if (i.tm.opcode_modifier.modrm)
6527 {
6528 /* The opcode is completed (modulo i.tm.extension_opcode which
6529 must be put into the modrm byte). Now, we make the modrm and
6530 index base bytes based on all the info we've collected. */
6531
6532 default_seg = build_modrm_byte ();
6533 }
6534 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6535 {
6536 default_seg = &ds;
6537 }
6538 else if (i.tm.opcode_modifier.isstring)
6539 {
6540 /* For the string instructions that allow a segment override
6541 on one of their operands, the default segment is ds. */
6542 default_seg = &ds;
6543 }
6544
6545 if (i.tm.base_opcode == 0x8d /* lea */
6546 && i.seg[0]
6547 && !quiet_warnings)
6548 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6549
6550 /* If a segment was explicitly specified, and the specified segment
6551 is not the default, use an opcode prefix to select it. If we
6552 never figured out what the default segment is, then default_seg
6553 will be zero at this point, and the specified segment prefix will
6554 always be used. */
6555 if ((i.seg[0]) && (i.seg[0] != default_seg))
6556 {
6557 if (!add_prefix (i.seg[0]->seg_prefix))
6558 return 0;
6559 }
6560 return 1;
6561 }
6562
6563 static const seg_entry *
6564 build_modrm_byte (void)
6565 {
6566 const seg_entry *default_seg = 0;
6567 unsigned int source, dest;
6568 int vex_3_sources;
6569
6570 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6571 if (vex_3_sources)
6572 {
6573 unsigned int nds, reg_slot;
6574 expressionS *exp;
6575
6576 dest = i.operands - 1;
6577 nds = dest - 1;
6578
6579 /* There are 2 kinds of instructions:
6580 1. 5 operands: 4 register operands or 3 register operands
6581 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6582 VexW0 or VexW1. The destination must be either XMM, YMM or
6583 ZMM register.
6584 2. 4 operands: 4 register operands or 3 register operands
6585 plus 1 memory operand, with VexXDS. */
6586 gas_assert ((i.reg_operands == 4
6587 || (i.reg_operands == 3 && i.mem_operands == 1))
6588 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6589 && i.tm.opcode_modifier.vexw
6590 && i.tm.operand_types[dest].bitfield.regsimd);
6591
6592 if (i.imm_operands == 0)
6593 {
6594 /* When there is no immediate operand, generate an 8bit
6595 immediate operand to encode the first operand. */
6596 exp = &im_expressions[i.imm_operands++];
6597 i.op[i.operands].imms = exp;
6598 i.types[i.operands] = imm8;
6599 i.operands++;
6600 /* If VexW1 is set, the first operand is the source and
6601 the second operand is encoded in the immediate operand. */
6602 if (i.tm.opcode_modifier.vexw == VEXW1)
6603 {
6604 source = 0;
6605 reg_slot = 1;
6606 }
6607 else
6608 {
6609 source = 1;
6610 reg_slot = 0;
6611 }
6612
6613 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6614 exp->X_op = O_constant;
6615 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6616 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6617 }
6618 else
6619 {
6620 unsigned int imm_slot;
6621
6622 gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4);
6623
6624 if (i.tm.opcode_modifier.vexw == VEXW0)
6625 {
6626 /* If VexW0 is set, the third operand is the source and
6627 the second operand is encoded in the immediate
6628 operand. */
6629 source = 2;
6630 reg_slot = 1;
6631 }
6632 else
6633 {
6634 /* VexW1 is set, the second operand is the source and
6635 the third operand is encoded in the immediate
6636 operand. */
6637 source = 1;
6638 reg_slot = 2;
6639 }
6640
6641 if (i.tm.opcode_modifier.immext)
6642 {
6643 /* When ImmExt is set, the immediate byte is the last
6644 operand. */
6645 imm_slot = i.operands - 1;
6646 source--;
6647 reg_slot--;
6648 }
6649 else
6650 {
6651 imm_slot = 0;
6652
6653 /* Turn on Imm8 so that output_imm will generate it. */
6654 i.types[imm_slot].bitfield.imm8 = 1;
6655 }
6656
6657 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6658 i.op[imm_slot].imms->X_add_number
6659 |= register_number (i.op[reg_slot].regs) << 4;
6660 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6661 }
6662
6663 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6664 i.vex.register_specifier = i.op[nds].regs;
6665 }
6666 else
6667 source = dest = 0;
6668
6669 /* i.reg_operands MUST be the number of real register operands;
6670 implicit registers do not count. If there are 3 register
6671 operands, it must be a instruction with VexNDS. For a
6672 instruction with VexNDD, the destination register is encoded
6673 in VEX prefix. If there are 4 register operands, it must be
6674 a instruction with VEX prefix and 3 sources. */
6675 if (i.mem_operands == 0
6676 && ((i.reg_operands == 2
6677 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6678 || (i.reg_operands == 3
6679 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6680 || (i.reg_operands == 4 && vex_3_sources)))
6681 {
6682 switch (i.operands)
6683 {
6684 case 2:
6685 source = 0;
6686 break;
6687 case 3:
6688 /* When there are 3 operands, one of them may be immediate,
6689 which may be the first or the last operand. Otherwise,
6690 the first operand must be shift count register (cl) or it
6691 is an instruction with VexNDS. */
6692 gas_assert (i.imm_operands == 1
6693 || (i.imm_operands == 0
6694 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6695 || i.types[0].bitfield.shiftcount)));
6696 if (operand_type_check (i.types[0], imm)
6697 || i.types[0].bitfield.shiftcount)
6698 source = 1;
6699 else
6700 source = 0;
6701 break;
6702 case 4:
6703 /* When there are 4 operands, the first two must be 8bit
6704 immediate operands. The source operand will be the 3rd
6705 one.
6706
6707 For instructions with VexNDS, if the first operand
6708 an imm8, the source operand is the 2nd one. If the last
6709 operand is imm8, the source operand is the first one. */
6710 gas_assert ((i.imm_operands == 2
6711 && i.types[0].bitfield.imm8
6712 && i.types[1].bitfield.imm8)
6713 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6714 && i.imm_operands == 1
6715 && (i.types[0].bitfield.imm8
6716 || i.types[i.operands - 1].bitfield.imm8
6717 || i.rounding)));
6718 if (i.imm_operands == 2)
6719 source = 2;
6720 else
6721 {
6722 if (i.types[0].bitfield.imm8)
6723 source = 1;
6724 else
6725 source = 0;
6726 }
6727 break;
6728 case 5:
6729 if (is_evex_encoding (&i.tm))
6730 {
6731 /* For EVEX instructions, when there are 5 operands, the
6732 first one must be immediate operand. If the second one
6733 is immediate operand, the source operand is the 3th
6734 one. If the last one is immediate operand, the source
6735 operand is the 2nd one. */
6736 gas_assert (i.imm_operands == 2
6737 && i.tm.opcode_modifier.sae
6738 && operand_type_check (i.types[0], imm));
6739 if (operand_type_check (i.types[1], imm))
6740 source = 2;
6741 else if (operand_type_check (i.types[4], imm))
6742 source = 1;
6743 else
6744 abort ();
6745 }
6746 break;
6747 default:
6748 abort ();
6749 }
6750
6751 if (!vex_3_sources)
6752 {
6753 dest = source + 1;
6754
6755 /* RC/SAE operand could be between DEST and SRC. That happens
6756 when one operand is GPR and the other one is XMM/YMM/ZMM
6757 register. */
6758 if (i.rounding && i.rounding->operand == (int) dest)
6759 dest++;
6760
6761 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6762 {
6763 /* For instructions with VexNDS, the register-only source
6764 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6765 register. It is encoded in VEX prefix. We need to
6766 clear RegMem bit before calling operand_type_equal. */
6767
6768 i386_operand_type op;
6769 unsigned int vvvv;
6770
6771 /* Check register-only source operand when two source
6772 operands are swapped. */
6773 if (!i.tm.operand_types[source].bitfield.baseindex
6774 && i.tm.operand_types[dest].bitfield.baseindex)
6775 {
6776 vvvv = source;
6777 source = dest;
6778 }
6779 else
6780 vvvv = dest;
6781
6782 op = i.tm.operand_types[vvvv];
6783 op.bitfield.regmem = 0;
6784 if ((dest + 1) >= i.operands
6785 || ((!op.bitfield.reg
6786 || (!op.bitfield.dword && !op.bitfield.qword))
6787 && !op.bitfield.regsimd
6788 && !operand_type_equal (&op, &regmask)))
6789 abort ();
6790 i.vex.register_specifier = i.op[vvvv].regs;
6791 dest++;
6792 }
6793 }
6794
6795 i.rm.mode = 3;
6796 /* One of the register operands will be encoded in the i.tm.reg
6797 field, the other in the combined i.tm.mode and i.tm.regmem
6798 fields. If no form of this instruction supports a memory
6799 destination operand, then we assume the source operand may
6800 sometimes be a memory operand and so we need to store the
6801 destination in the i.rm.reg field. */
6802 if (!i.tm.operand_types[dest].bitfield.regmem
6803 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6804 {
6805 i.rm.reg = i.op[dest].regs->reg_num;
6806 i.rm.regmem = i.op[source].regs->reg_num;
6807 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6808 i.rex |= REX_R;
6809 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6810 i.vrex |= REX_R;
6811 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6812 i.rex |= REX_B;
6813 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6814 i.vrex |= REX_B;
6815 }
6816 else
6817 {
6818 i.rm.reg = i.op[source].regs->reg_num;
6819 i.rm.regmem = i.op[dest].regs->reg_num;
6820 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6821 i.rex |= REX_B;
6822 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6823 i.vrex |= REX_B;
6824 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6825 i.rex |= REX_R;
6826 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6827 i.vrex |= REX_R;
6828 }
6829 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6830 {
6831 if (!i.types[0].bitfield.control
6832 && !i.types[1].bitfield.control)
6833 abort ();
6834 i.rex &= ~(REX_R | REX_B);
6835 add_prefix (LOCK_PREFIX_OPCODE);
6836 }
6837 }
6838 else
6839 { /* If it's not 2 reg operands... */
6840 unsigned int mem;
6841
6842 if (i.mem_operands)
6843 {
6844 unsigned int fake_zero_displacement = 0;
6845 unsigned int op;
6846
6847 for (op = 0; op < i.operands; op++)
6848 if (operand_type_check (i.types[op], anymem))
6849 break;
6850 gas_assert (op < i.operands);
6851
6852 if (i.tm.opcode_modifier.vecsib)
6853 {
6854 if (i.index_reg->reg_num == RegEiz
6855 || i.index_reg->reg_num == RegRiz)
6856 abort ();
6857
6858 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6859 if (!i.base_reg)
6860 {
6861 i.sib.base = NO_BASE_REGISTER;
6862 i.sib.scale = i.log2_scale_factor;
6863 i.types[op].bitfield.disp8 = 0;
6864 i.types[op].bitfield.disp16 = 0;
6865 i.types[op].bitfield.disp64 = 0;
6866 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6867 {
6868 /* Must be 32 bit */
6869 i.types[op].bitfield.disp32 = 1;
6870 i.types[op].bitfield.disp32s = 0;
6871 }
6872 else
6873 {
6874 i.types[op].bitfield.disp32 = 0;
6875 i.types[op].bitfield.disp32s = 1;
6876 }
6877 }
6878 i.sib.index = i.index_reg->reg_num;
6879 if ((i.index_reg->reg_flags & RegRex) != 0)
6880 i.rex |= REX_X;
6881 if ((i.index_reg->reg_flags & RegVRex) != 0)
6882 i.vrex |= REX_X;
6883 }
6884
6885 default_seg = &ds;
6886
6887 if (i.base_reg == 0)
6888 {
6889 i.rm.mode = 0;
6890 if (!i.disp_operands)
6891 fake_zero_displacement = 1;
6892 if (i.index_reg == 0)
6893 {
6894 i386_operand_type newdisp;
6895
6896 gas_assert (!i.tm.opcode_modifier.vecsib);
6897 /* Operand is just <disp> */
6898 if (flag_code == CODE_64BIT)
6899 {
6900 /* 64bit mode overwrites the 32bit absolute
6901 addressing by RIP relative addressing and
6902 absolute addressing is encoded by one of the
6903 redundant SIB forms. */
6904 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6905 i.sib.base = NO_BASE_REGISTER;
6906 i.sib.index = NO_INDEX_REGISTER;
6907 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
6908 }
6909 else if ((flag_code == CODE_16BIT)
6910 ^ (i.prefix[ADDR_PREFIX] != 0))
6911 {
6912 i.rm.regmem = NO_BASE_REGISTER_16;
6913 newdisp = disp16;
6914 }
6915 else
6916 {
6917 i.rm.regmem = NO_BASE_REGISTER;
6918 newdisp = disp32;
6919 }
6920 i.types[op] = operand_type_and_not (i.types[op], anydisp);
6921 i.types[op] = operand_type_or (i.types[op], newdisp);
6922 }
6923 else if (!i.tm.opcode_modifier.vecsib)
6924 {
6925 /* !i.base_reg && i.index_reg */
6926 if (i.index_reg->reg_num == RegEiz
6927 || i.index_reg->reg_num == RegRiz)
6928 i.sib.index = NO_INDEX_REGISTER;
6929 else
6930 i.sib.index = i.index_reg->reg_num;
6931 i.sib.base = NO_BASE_REGISTER;
6932 i.sib.scale = i.log2_scale_factor;
6933 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6934 i.types[op].bitfield.disp8 = 0;
6935 i.types[op].bitfield.disp16 = 0;
6936 i.types[op].bitfield.disp64 = 0;
6937 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6938 {
6939 /* Must be 32 bit */
6940 i.types[op].bitfield.disp32 = 1;
6941 i.types[op].bitfield.disp32s = 0;
6942 }
6943 else
6944 {
6945 i.types[op].bitfield.disp32 = 0;
6946 i.types[op].bitfield.disp32s = 1;
6947 }
6948 if ((i.index_reg->reg_flags & RegRex) != 0)
6949 i.rex |= REX_X;
6950 }
6951 }
6952 /* RIP addressing for 64bit mode. */
6953 else if (i.base_reg->reg_num == RegRip ||
6954 i.base_reg->reg_num == RegEip)
6955 {
6956 gas_assert (!i.tm.opcode_modifier.vecsib);
6957 i.rm.regmem = NO_BASE_REGISTER;
6958 i.types[op].bitfield.disp8 = 0;
6959 i.types[op].bitfield.disp16 = 0;
6960 i.types[op].bitfield.disp32 = 0;
6961 i.types[op].bitfield.disp32s = 1;
6962 i.types[op].bitfield.disp64 = 0;
6963 i.flags[op] |= Operand_PCrel;
6964 if (! i.disp_operands)
6965 fake_zero_displacement = 1;
6966 }
6967 else if (i.base_reg->reg_type.bitfield.word)
6968 {
6969 gas_assert (!i.tm.opcode_modifier.vecsib);
6970 switch (i.base_reg->reg_num)
6971 {
6972 case 3: /* (%bx) */
6973 if (i.index_reg == 0)
6974 i.rm.regmem = 7;
6975 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6976 i.rm.regmem = i.index_reg->reg_num - 6;
6977 break;
6978 case 5: /* (%bp) */
6979 default_seg = &ss;
6980 if (i.index_reg == 0)
6981 {
6982 i.rm.regmem = 6;
6983 if (operand_type_check (i.types[op], disp) == 0)
6984 {
6985 /* fake (%bp) into 0(%bp) */
6986 i.types[op].bitfield.disp8 = 1;
6987 fake_zero_displacement = 1;
6988 }
6989 }
6990 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6991 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6992 break;
6993 default: /* (%si) -> 4 or (%di) -> 5 */
6994 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6995 }
6996 i.rm.mode = mode_from_disp_size (i.types[op]);
6997 }
6998 else /* i.base_reg and 32/64 bit mode */
6999 {
7000 if (flag_code == CODE_64BIT
7001 && operand_type_check (i.types[op], disp))
7002 {
7003 i.types[op].bitfield.disp16 = 0;
7004 i.types[op].bitfield.disp64 = 0;
7005 if (i.prefix[ADDR_PREFIX] == 0)
7006 {
7007 i.types[op].bitfield.disp32 = 0;
7008 i.types[op].bitfield.disp32s = 1;
7009 }
7010 else
7011 {
7012 i.types[op].bitfield.disp32 = 1;
7013 i.types[op].bitfield.disp32s = 0;
7014 }
7015 }
7016
7017 if (!i.tm.opcode_modifier.vecsib)
7018 i.rm.regmem = i.base_reg->reg_num;
7019 if ((i.base_reg->reg_flags & RegRex) != 0)
7020 i.rex |= REX_B;
7021 i.sib.base = i.base_reg->reg_num;
7022 /* x86-64 ignores REX prefix bit here to avoid decoder
7023 complications. */
7024 if (!(i.base_reg->reg_flags & RegRex)
7025 && (i.base_reg->reg_num == EBP_REG_NUM
7026 || i.base_reg->reg_num == ESP_REG_NUM))
7027 default_seg = &ss;
7028 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
7029 {
7030 fake_zero_displacement = 1;
7031 i.types[op].bitfield.disp8 = 1;
7032 }
7033 i.sib.scale = i.log2_scale_factor;
7034 if (i.index_reg == 0)
7035 {
7036 gas_assert (!i.tm.opcode_modifier.vecsib);
7037 /* <disp>(%esp) becomes two byte modrm with no index
7038 register. We've already stored the code for esp
7039 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7040 Any base register besides %esp will not use the
7041 extra modrm byte. */
7042 i.sib.index = NO_INDEX_REGISTER;
7043 }
7044 else if (!i.tm.opcode_modifier.vecsib)
7045 {
7046 if (i.index_reg->reg_num == RegEiz
7047 || i.index_reg->reg_num == RegRiz)
7048 i.sib.index = NO_INDEX_REGISTER;
7049 else
7050 i.sib.index = i.index_reg->reg_num;
7051 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7052 if ((i.index_reg->reg_flags & RegRex) != 0)
7053 i.rex |= REX_X;
7054 }
7055
7056 if (i.disp_operands
7057 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7058 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7059 i.rm.mode = 0;
7060 else
7061 {
7062 if (!fake_zero_displacement
7063 && !i.disp_operands
7064 && i.disp_encoding)
7065 {
7066 fake_zero_displacement = 1;
7067 if (i.disp_encoding == disp_encoding_8bit)
7068 i.types[op].bitfield.disp8 = 1;
7069 else
7070 i.types[op].bitfield.disp32 = 1;
7071 }
7072 i.rm.mode = mode_from_disp_size (i.types[op]);
7073 }
7074 }
7075
7076 if (fake_zero_displacement)
7077 {
7078 /* Fakes a zero displacement assuming that i.types[op]
7079 holds the correct displacement size. */
7080 expressionS *exp;
7081
7082 gas_assert (i.op[op].disps == 0);
7083 exp = &disp_expressions[i.disp_operands++];
7084 i.op[op].disps = exp;
7085 exp->X_op = O_constant;
7086 exp->X_add_number = 0;
7087 exp->X_add_symbol = (symbolS *) 0;
7088 exp->X_op_symbol = (symbolS *) 0;
7089 }
7090
7091 mem = op;
7092 }
7093 else
7094 mem = ~0;
7095
7096 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7097 {
7098 if (operand_type_check (i.types[0], imm))
7099 i.vex.register_specifier = NULL;
7100 else
7101 {
7102 /* VEX.vvvv encodes one of the sources when the first
7103 operand is not an immediate. */
7104 if (i.tm.opcode_modifier.vexw == VEXW0)
7105 i.vex.register_specifier = i.op[0].regs;
7106 else
7107 i.vex.register_specifier = i.op[1].regs;
7108 }
7109
7110 /* Destination is a XMM register encoded in the ModRM.reg
7111 and VEX.R bit. */
7112 i.rm.reg = i.op[2].regs->reg_num;
7113 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7114 i.rex |= REX_R;
7115
7116 /* ModRM.rm and VEX.B encodes the other source. */
7117 if (!i.mem_operands)
7118 {
7119 i.rm.mode = 3;
7120
7121 if (i.tm.opcode_modifier.vexw == VEXW0)
7122 i.rm.regmem = i.op[1].regs->reg_num;
7123 else
7124 i.rm.regmem = i.op[0].regs->reg_num;
7125
7126 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7127 i.rex |= REX_B;
7128 }
7129 }
7130 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7131 {
7132 i.vex.register_specifier = i.op[2].regs;
7133 if (!i.mem_operands)
7134 {
7135 i.rm.mode = 3;
7136 i.rm.regmem = i.op[1].regs->reg_num;
7137 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7138 i.rex |= REX_B;
7139 }
7140 }
7141 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7142 (if any) based on i.tm.extension_opcode. Again, we must be
7143 careful to make sure that segment/control/debug/test/MMX
7144 registers are coded into the i.rm.reg field. */
7145 else if (i.reg_operands)
7146 {
7147 unsigned int op;
7148 unsigned int vex_reg = ~0;
7149
7150 for (op = 0; op < i.operands; op++)
7151 if (i.types[op].bitfield.reg
7152 || i.types[op].bitfield.regmmx
7153 || i.types[op].bitfield.regsimd
7154 || i.types[op].bitfield.regbnd
7155 || i.types[op].bitfield.regmask
7156 || i.types[op].bitfield.sreg2
7157 || i.types[op].bitfield.sreg3
7158 || i.types[op].bitfield.control
7159 || i.types[op].bitfield.debug
7160 || i.types[op].bitfield.test)
7161 break;
7162
7163 if (vex_3_sources)
7164 op = dest;
7165 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7166 {
7167 /* For instructions with VexNDS, the register-only
7168 source operand is encoded in VEX prefix. */
7169 gas_assert (mem != (unsigned int) ~0);
7170
7171 if (op > mem)
7172 {
7173 vex_reg = op++;
7174 gas_assert (op < i.operands);
7175 }
7176 else
7177 {
7178 /* Check register-only source operand when two source
7179 operands are swapped. */
7180 if (!i.tm.operand_types[op].bitfield.baseindex
7181 && i.tm.operand_types[op + 1].bitfield.baseindex)
7182 {
7183 vex_reg = op;
7184 op += 2;
7185 gas_assert (mem == (vex_reg + 1)
7186 && op < i.operands);
7187 }
7188 else
7189 {
7190 vex_reg = op + 1;
7191 gas_assert (vex_reg < i.operands);
7192 }
7193 }
7194 }
7195 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7196 {
7197 /* For instructions with VexNDD, the register destination
7198 is encoded in VEX prefix. */
7199 if (i.mem_operands == 0)
7200 {
7201 /* There is no memory operand. */
7202 gas_assert ((op + 2) == i.operands);
7203 vex_reg = op + 1;
7204 }
7205 else
7206 {
7207 /* There are only 2 non-immediate operands. */
7208 gas_assert (op < i.imm_operands + 2
7209 && i.operands == i.imm_operands + 2);
7210 vex_reg = i.imm_operands + 1;
7211 }
7212 }
7213 else
7214 gas_assert (op < i.operands);
7215
7216 if (vex_reg != (unsigned int) ~0)
7217 {
7218 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7219
7220 if ((!type->bitfield.reg
7221 || (!type->bitfield.dword && !type->bitfield.qword))
7222 && !type->bitfield.regsimd
7223 && !operand_type_equal (type, &regmask))
7224 abort ();
7225
7226 i.vex.register_specifier = i.op[vex_reg].regs;
7227 }
7228
7229 /* Don't set OP operand twice. */
7230 if (vex_reg != op)
7231 {
7232 /* If there is an extension opcode to put here, the
7233 register number must be put into the regmem field. */
7234 if (i.tm.extension_opcode != None)
7235 {
7236 i.rm.regmem = i.op[op].regs->reg_num;
7237 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7238 i.rex |= REX_B;
7239 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7240 i.vrex |= REX_B;
7241 }
7242 else
7243 {
7244 i.rm.reg = i.op[op].regs->reg_num;
7245 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7246 i.rex |= REX_R;
7247 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7248 i.vrex |= REX_R;
7249 }
7250 }
7251
7252 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7253 must set it to 3 to indicate this is a register operand
7254 in the regmem field. */
7255 if (!i.mem_operands)
7256 i.rm.mode = 3;
7257 }
7258
7259 /* Fill in i.rm.reg field with extension opcode (if any). */
7260 if (i.tm.extension_opcode != None)
7261 i.rm.reg = i.tm.extension_opcode;
7262 }
7263 return default_seg;
7264 }
7265
7266 static void
7267 output_branch (void)
7268 {
7269 char *p;
7270 int size;
7271 int code16;
7272 int prefix;
7273 relax_substateT subtype;
7274 symbolS *sym;
7275 offsetT off;
7276
7277 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7278 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7279
7280 prefix = 0;
7281 if (i.prefix[DATA_PREFIX] != 0)
7282 {
7283 prefix = 1;
7284 i.prefixes -= 1;
7285 code16 ^= CODE16;
7286 }
7287 /* Pentium4 branch hints. */
7288 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7289 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7290 {
7291 prefix++;
7292 i.prefixes--;
7293 }
7294 if (i.prefix[REX_PREFIX] != 0)
7295 {
7296 prefix++;
7297 i.prefixes--;
7298 }
7299
7300 /* BND prefixed jump. */
7301 if (i.prefix[BND_PREFIX] != 0)
7302 {
7303 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7304 i.prefixes -= 1;
7305 }
7306
7307 if (i.prefixes != 0 && !intel_syntax)
7308 as_warn (_("skipping prefixes on this instruction"));
7309
7310 /* It's always a symbol; End frag & setup for relax.
7311 Make sure there is enough room in this frag for the largest
7312 instruction we may generate in md_convert_frag. This is 2
7313 bytes for the opcode and room for the prefix and largest
7314 displacement. */
7315 frag_grow (prefix + 2 + 4);
7316 /* Prefix and 1 opcode byte go in fr_fix. */
7317 p = frag_more (prefix + 1);
7318 if (i.prefix[DATA_PREFIX] != 0)
7319 *p++ = DATA_PREFIX_OPCODE;
7320 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7321 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7322 *p++ = i.prefix[SEG_PREFIX];
7323 if (i.prefix[REX_PREFIX] != 0)
7324 *p++ = i.prefix[REX_PREFIX];
7325 *p = i.tm.base_opcode;
7326
7327 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7328 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7329 else if (cpu_arch_flags.bitfield.cpui386)
7330 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7331 else
7332 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7333 subtype |= code16;
7334
7335 sym = i.op[0].disps->X_add_symbol;
7336 off = i.op[0].disps->X_add_number;
7337
7338 if (i.op[0].disps->X_op != O_constant
7339 && i.op[0].disps->X_op != O_symbol)
7340 {
7341 /* Handle complex expressions. */
7342 sym = make_expr_symbol (i.op[0].disps);
7343 off = 0;
7344 }
7345
7346 /* 1 possible extra opcode + 4 byte displacement go in var part.
7347 Pass reloc in fr_var. */
7348 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7349 }
7350
7351 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7352 /* Return TRUE iff PLT32 relocation should be used for branching to
7353 symbol S. */
7354
7355 static bfd_boolean
7356 need_plt32_p (symbolS *s)
7357 {
7358 /* PLT32 relocation is ELF only. */
7359 if (!IS_ELF)
7360 return FALSE;
7361
7362 /* Since there is no need to prepare for PLT branch on x86-64, we
7363 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7364 be used as a marker for 32-bit PC-relative branches. */
7365 if (!object_64bit)
7366 return FALSE;
7367
7368 /* Weak or undefined symbol need PLT32 relocation. */
7369 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7370 return TRUE;
7371
7372 /* Non-global symbol doesn't need PLT32 relocation. */
7373 if (! S_IS_EXTERNAL (s))
7374 return FALSE;
7375
7376 /* Other global symbols need PLT32 relocation. NB: Symbol with
7377 non-default visibilities are treated as normal global symbol
7378 so that PLT32 relocation can be used as a marker for 32-bit
7379 PC-relative branches. It is useful for linker relaxation. */
7380 return TRUE;
7381 }
7382 #endif
7383
7384 static void
7385 output_jump (void)
7386 {
7387 char *p;
7388 int size;
7389 fixS *fixP;
7390 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7391
7392 if (i.tm.opcode_modifier.jumpbyte)
7393 {
7394 /* This is a loop or jecxz type instruction. */
7395 size = 1;
7396 if (i.prefix[ADDR_PREFIX] != 0)
7397 {
7398 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7399 i.prefixes -= 1;
7400 }
7401 /* Pentium4 branch hints. */
7402 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7403 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7404 {
7405 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7406 i.prefixes--;
7407 }
7408 }
7409 else
7410 {
7411 int code16;
7412
7413 code16 = 0;
7414 if (flag_code == CODE_16BIT)
7415 code16 = CODE16;
7416
7417 if (i.prefix[DATA_PREFIX] != 0)
7418 {
7419 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7420 i.prefixes -= 1;
7421 code16 ^= CODE16;
7422 }
7423
7424 size = 4;
7425 if (code16)
7426 size = 2;
7427 }
7428
7429 if (i.prefix[REX_PREFIX] != 0)
7430 {
7431 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7432 i.prefixes -= 1;
7433 }
7434
7435 /* BND prefixed jump. */
7436 if (i.prefix[BND_PREFIX] != 0)
7437 {
7438 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7439 i.prefixes -= 1;
7440 }
7441
7442 if (i.prefixes != 0 && !intel_syntax)
7443 as_warn (_("skipping prefixes on this instruction"));
7444
7445 p = frag_more (i.tm.opcode_length + size);
7446 switch (i.tm.opcode_length)
7447 {
7448 case 2:
7449 *p++ = i.tm.base_opcode >> 8;
7450 /* Fall through. */
7451 case 1:
7452 *p++ = i.tm.base_opcode;
7453 break;
7454 default:
7455 abort ();
7456 }
7457
7458 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7459 if (size == 4
7460 && jump_reloc == NO_RELOC
7461 && need_plt32_p (i.op[0].disps->X_add_symbol))
7462 jump_reloc = BFD_RELOC_X86_64_PLT32;
7463 #endif
7464
7465 jump_reloc = reloc (size, 1, 1, jump_reloc);
7466
7467 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7468 i.op[0].disps, 1, jump_reloc);
7469
7470 /* All jumps handled here are signed, but don't use a signed limit
7471 check for 32 and 16 bit jumps as we want to allow wrap around at
7472 4G and 64k respectively. */
7473 if (size == 1)
7474 fixP->fx_signed = 1;
7475 }
7476
7477 static void
7478 output_interseg_jump (void)
7479 {
7480 char *p;
7481 int size;
7482 int prefix;
7483 int code16;
7484
7485 code16 = 0;
7486 if (flag_code == CODE_16BIT)
7487 code16 = CODE16;
7488
7489 prefix = 0;
7490 if (i.prefix[DATA_PREFIX] != 0)
7491 {
7492 prefix = 1;
7493 i.prefixes -= 1;
7494 code16 ^= CODE16;
7495 }
7496 if (i.prefix[REX_PREFIX] != 0)
7497 {
7498 prefix++;
7499 i.prefixes -= 1;
7500 }
7501
7502 size = 4;
7503 if (code16)
7504 size = 2;
7505
7506 if (i.prefixes != 0 && !intel_syntax)
7507 as_warn (_("skipping prefixes on this instruction"));
7508
7509 /* 1 opcode; 2 segment; offset */
7510 p = frag_more (prefix + 1 + 2 + size);
7511
7512 if (i.prefix[DATA_PREFIX] != 0)
7513 *p++ = DATA_PREFIX_OPCODE;
7514
7515 if (i.prefix[REX_PREFIX] != 0)
7516 *p++ = i.prefix[REX_PREFIX];
7517
7518 *p++ = i.tm.base_opcode;
7519 if (i.op[1].imms->X_op == O_constant)
7520 {
7521 offsetT n = i.op[1].imms->X_add_number;
7522
7523 if (size == 2
7524 && !fits_in_unsigned_word (n)
7525 && !fits_in_signed_word (n))
7526 {
7527 as_bad (_("16-bit jump out of range"));
7528 return;
7529 }
7530 md_number_to_chars (p, n, size);
7531 }
7532 else
7533 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7534 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7535 if (i.op[0].imms->X_op != O_constant)
7536 as_bad (_("can't handle non absolute segment in `%s'"),
7537 i.tm.name);
7538 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7539 }
7540
7541 static void
7542 output_insn (void)
7543 {
7544 fragS *insn_start_frag;
7545 offsetT insn_start_off;
7546
7547 /* Tie dwarf2 debug info to the address at the start of the insn.
7548 We can't do this after the insn has been output as the current
7549 frag may have been closed off. eg. by frag_var. */
7550 dwarf2_emit_insn (0);
7551
7552 insn_start_frag = frag_now;
7553 insn_start_off = frag_now_fix ();
7554
7555 /* Output jumps. */
7556 if (i.tm.opcode_modifier.jump)
7557 output_branch ();
7558 else if (i.tm.opcode_modifier.jumpbyte
7559 || i.tm.opcode_modifier.jumpdword)
7560 output_jump ();
7561 else if (i.tm.opcode_modifier.jumpintersegment)
7562 output_interseg_jump ();
7563 else
7564 {
7565 /* Output normal instructions here. */
7566 char *p;
7567 unsigned char *q;
7568 unsigned int j;
7569 unsigned int prefix;
7570
7571 if (avoid_fence
7572 && i.tm.base_opcode == 0xfae
7573 && i.operands == 1
7574 && i.imm_operands == 1
7575 && (i.op[0].imms->X_add_number == 0xe8
7576 || i.op[0].imms->X_add_number == 0xf0
7577 || i.op[0].imms->X_add_number == 0xf8))
7578 {
7579 /* Encode lfence, mfence, and sfence as
7580 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7581 offsetT val = 0x240483f0ULL;
7582 p = frag_more (5);
7583 md_number_to_chars (p, val, 5);
7584 return;
7585 }
7586
7587 /* Some processors fail on LOCK prefix. This options makes
7588 assembler ignore LOCK prefix and serves as a workaround. */
7589 if (omit_lock_prefix)
7590 {
7591 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7592 return;
7593 i.prefix[LOCK_PREFIX] = 0;
7594 }
7595
7596 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7597 don't need the explicit prefix. */
7598 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7599 {
7600 switch (i.tm.opcode_length)
7601 {
7602 case 3:
7603 if (i.tm.base_opcode & 0xff000000)
7604 {
7605 prefix = (i.tm.base_opcode >> 24) & 0xff;
7606 goto check_prefix;
7607 }
7608 break;
7609 case 2:
7610 if ((i.tm.base_opcode & 0xff0000) != 0)
7611 {
7612 prefix = (i.tm.base_opcode >> 16) & 0xff;
7613 if (i.tm.cpu_flags.bitfield.cpupadlock)
7614 {
7615 check_prefix:
7616 if (prefix != REPE_PREFIX_OPCODE
7617 || (i.prefix[REP_PREFIX]
7618 != REPE_PREFIX_OPCODE))
7619 add_prefix (prefix);
7620 }
7621 else
7622 add_prefix (prefix);
7623 }
7624 break;
7625 case 1:
7626 break;
7627 case 0:
7628 /* Check for pseudo prefixes. */
7629 as_bad_where (insn_start_frag->fr_file,
7630 insn_start_frag->fr_line,
7631 _("pseudo prefix without instruction"));
7632 return;
7633 default:
7634 abort ();
7635 }
7636
7637 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7638 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7639 R_X86_64_GOTTPOFF relocation so that linker can safely
7640 perform IE->LE optimization. */
7641 if (x86_elf_abi == X86_64_X32_ABI
7642 && i.operands == 2
7643 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7644 && i.prefix[REX_PREFIX] == 0)
7645 add_prefix (REX_OPCODE);
7646 #endif
7647
7648 /* The prefix bytes. */
7649 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7650 if (*q)
7651 FRAG_APPEND_1_CHAR (*q);
7652 }
7653 else
7654 {
7655 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7656 if (*q)
7657 switch (j)
7658 {
7659 case REX_PREFIX:
7660 /* REX byte is encoded in VEX prefix. */
7661 break;
7662 case SEG_PREFIX:
7663 case ADDR_PREFIX:
7664 FRAG_APPEND_1_CHAR (*q);
7665 break;
7666 default:
7667 /* There should be no other prefixes for instructions
7668 with VEX prefix. */
7669 abort ();
7670 }
7671
7672 /* For EVEX instructions i.vrex should become 0 after
7673 build_evex_prefix. For VEX instructions upper 16 registers
7674 aren't available, so VREX should be 0. */
7675 if (i.vrex)
7676 abort ();
7677 /* Now the VEX prefix. */
7678 p = frag_more (i.vex.length);
7679 for (j = 0; j < i.vex.length; j++)
7680 p[j] = i.vex.bytes[j];
7681 }
7682
7683 /* Now the opcode; be careful about word order here! */
7684 if (i.tm.opcode_length == 1)
7685 {
7686 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7687 }
7688 else
7689 {
7690 switch (i.tm.opcode_length)
7691 {
7692 case 4:
7693 p = frag_more (4);
7694 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7695 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7696 break;
7697 case 3:
7698 p = frag_more (3);
7699 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7700 break;
7701 case 2:
7702 p = frag_more (2);
7703 break;
7704 default:
7705 abort ();
7706 break;
7707 }
7708
7709 /* Put out high byte first: can't use md_number_to_chars! */
7710 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7711 *p = i.tm.base_opcode & 0xff;
7712 }
7713
7714 /* Now the modrm byte and sib byte (if present). */
7715 if (i.tm.opcode_modifier.modrm)
7716 {
7717 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7718 | i.rm.reg << 3
7719 | i.rm.mode << 6));
7720 /* If i.rm.regmem == ESP (4)
7721 && i.rm.mode != (Register mode)
7722 && not 16 bit
7723 ==> need second modrm byte. */
7724 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7725 && i.rm.mode != 3
7726 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7727 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7728 | i.sib.index << 3
7729 | i.sib.scale << 6));
7730 }
7731
7732 if (i.disp_operands)
7733 output_disp (insn_start_frag, insn_start_off);
7734
7735 if (i.imm_operands)
7736 output_imm (insn_start_frag, insn_start_off);
7737 }
7738
7739 #ifdef DEBUG386
7740 if (flag_debug)
7741 {
7742 pi ("" /*line*/, &i);
7743 }
7744 #endif /* DEBUG386 */
7745 }
7746
7747 /* Return the size of the displacement operand N. */
7748
7749 static int
7750 disp_size (unsigned int n)
7751 {
7752 int size = 4;
7753
7754 if (i.types[n].bitfield.disp64)
7755 size = 8;
7756 else if (i.types[n].bitfield.disp8)
7757 size = 1;
7758 else if (i.types[n].bitfield.disp16)
7759 size = 2;
7760 return size;
7761 }
7762
7763 /* Return the size of the immediate operand N. */
7764
7765 static int
7766 imm_size (unsigned int n)
7767 {
7768 int size = 4;
7769 if (i.types[n].bitfield.imm64)
7770 size = 8;
7771 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7772 size = 1;
7773 else if (i.types[n].bitfield.imm16)
7774 size = 2;
7775 return size;
7776 }
7777
7778 static void
7779 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7780 {
7781 char *p;
7782 unsigned int n;
7783
7784 for (n = 0; n < i.operands; n++)
7785 {
7786 if (operand_type_check (i.types[n], disp))
7787 {
7788 if (i.op[n].disps->X_op == O_constant)
7789 {
7790 int size = disp_size (n);
7791 offsetT val = i.op[n].disps->X_add_number;
7792
7793 val = offset_in_range (val >> i.memshift, size);
7794 p = frag_more (size);
7795 md_number_to_chars (p, val, size);
7796 }
7797 else
7798 {
7799 enum bfd_reloc_code_real reloc_type;
7800 int size = disp_size (n);
7801 int sign = i.types[n].bitfield.disp32s;
7802 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7803 fixS *fixP;
7804
7805 /* We can't have 8 bit displacement here. */
7806 gas_assert (!i.types[n].bitfield.disp8);
7807
7808 /* The PC relative address is computed relative
7809 to the instruction boundary, so in case immediate
7810 fields follows, we need to adjust the value. */
7811 if (pcrel && i.imm_operands)
7812 {
7813 unsigned int n1;
7814 int sz = 0;
7815
7816 for (n1 = 0; n1 < i.operands; n1++)
7817 if (operand_type_check (i.types[n1], imm))
7818 {
7819 /* Only one immediate is allowed for PC
7820 relative address. */
7821 gas_assert (sz == 0);
7822 sz = imm_size (n1);
7823 i.op[n].disps->X_add_number -= sz;
7824 }
7825 /* We should find the immediate. */
7826 gas_assert (sz != 0);
7827 }
7828
7829 p = frag_more (size);
7830 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7831 if (GOT_symbol
7832 && GOT_symbol == i.op[n].disps->X_add_symbol
7833 && (((reloc_type == BFD_RELOC_32
7834 || reloc_type == BFD_RELOC_X86_64_32S
7835 || (reloc_type == BFD_RELOC_64
7836 && object_64bit))
7837 && (i.op[n].disps->X_op == O_symbol
7838 || (i.op[n].disps->X_op == O_add
7839 && ((symbol_get_value_expression
7840 (i.op[n].disps->X_op_symbol)->X_op)
7841 == O_subtract))))
7842 || reloc_type == BFD_RELOC_32_PCREL))
7843 {
7844 offsetT add;
7845
7846 if (insn_start_frag == frag_now)
7847 add = (p - frag_now->fr_literal) - insn_start_off;
7848 else
7849 {
7850 fragS *fr;
7851
7852 add = insn_start_frag->fr_fix - insn_start_off;
7853 for (fr = insn_start_frag->fr_next;
7854 fr && fr != frag_now; fr = fr->fr_next)
7855 add += fr->fr_fix;
7856 add += p - frag_now->fr_literal;
7857 }
7858
7859 if (!object_64bit)
7860 {
7861 reloc_type = BFD_RELOC_386_GOTPC;
7862 i.op[n].imms->X_add_number += add;
7863 }
7864 else if (reloc_type == BFD_RELOC_64)
7865 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7866 else
7867 /* Don't do the adjustment for x86-64, as there
7868 the pcrel addressing is relative to the _next_
7869 insn, and that is taken care of in other code. */
7870 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7871 }
7872 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7873 size, i.op[n].disps, pcrel,
7874 reloc_type);
7875 /* Check for "call/jmp *mem", "mov mem, %reg",
7876 "test %reg, mem" and "binop mem, %reg" where binop
7877 is one of adc, add, and, cmp, or, sbb, sub, xor
7878 instructions. Always generate R_386_GOT32X for
7879 "sym*GOT" operand in 32-bit mode. */
7880 if ((generate_relax_relocations
7881 || (!object_64bit
7882 && i.rm.mode == 0
7883 && i.rm.regmem == 5))
7884 && (i.rm.mode == 2
7885 || (i.rm.mode == 0 && i.rm.regmem == 5))
7886 && ((i.operands == 1
7887 && i.tm.base_opcode == 0xff
7888 && (i.rm.reg == 2 || i.rm.reg == 4))
7889 || (i.operands == 2
7890 && (i.tm.base_opcode == 0x8b
7891 || i.tm.base_opcode == 0x85
7892 || (i.tm.base_opcode & 0xc7) == 0x03))))
7893 {
7894 if (object_64bit)
7895 {
7896 fixP->fx_tcbit = i.rex != 0;
7897 if (i.base_reg
7898 && (i.base_reg->reg_num == RegRip
7899 || i.base_reg->reg_num == RegEip))
7900 fixP->fx_tcbit2 = 1;
7901 }
7902 else
7903 fixP->fx_tcbit2 = 1;
7904 }
7905 }
7906 }
7907 }
7908 }
7909
7910 static void
7911 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7912 {
7913 char *p;
7914 unsigned int n;
7915
7916 for (n = 0; n < i.operands; n++)
7917 {
7918 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7919 if (i.rounding && (int) n == i.rounding->operand)
7920 continue;
7921
7922 if (operand_type_check (i.types[n], imm))
7923 {
7924 if (i.op[n].imms->X_op == O_constant)
7925 {
7926 int size = imm_size (n);
7927 offsetT val;
7928
7929 val = offset_in_range (i.op[n].imms->X_add_number,
7930 size);
7931 p = frag_more (size);
7932 md_number_to_chars (p, val, size);
7933 }
7934 else
7935 {
7936 /* Not absolute_section.
7937 Need a 32-bit fixup (don't support 8bit
7938 non-absolute imms). Try to support other
7939 sizes ... */
7940 enum bfd_reloc_code_real reloc_type;
7941 int size = imm_size (n);
7942 int sign;
7943
7944 if (i.types[n].bitfield.imm32s
7945 && (i.suffix == QWORD_MNEM_SUFFIX
7946 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7947 sign = 1;
7948 else
7949 sign = 0;
7950
7951 p = frag_more (size);
7952 reloc_type = reloc (size, 0, sign, i.reloc[n]);
7953
7954 /* This is tough to explain. We end up with this one if we
7955 * have operands that look like
7956 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7957 * obtain the absolute address of the GOT, and it is strongly
7958 * preferable from a performance point of view to avoid using
7959 * a runtime relocation for this. The actual sequence of
7960 * instructions often look something like:
7961 *
7962 * call .L66
7963 * .L66:
7964 * popl %ebx
7965 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7966 *
7967 * The call and pop essentially return the absolute address
7968 * of the label .L66 and store it in %ebx. The linker itself
7969 * will ultimately change the first operand of the addl so
7970 * that %ebx points to the GOT, but to keep things simple, the
7971 * .o file must have this operand set so that it generates not
7972 * the absolute address of .L66, but the absolute address of
7973 * itself. This allows the linker itself simply treat a GOTPC
7974 * relocation as asking for a pcrel offset to the GOT to be
7975 * added in, and the addend of the relocation is stored in the
7976 * operand field for the instruction itself.
7977 *
7978 * Our job here is to fix the operand so that it would add
7979 * the correct offset so that %ebx would point to itself. The
7980 * thing that is tricky is that .-.L66 will point to the
7981 * beginning of the instruction, so we need to further modify
7982 * the operand so that it will point to itself. There are
7983 * other cases where you have something like:
7984 *
7985 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7986 *
7987 * and here no correction would be required. Internally in
7988 * the assembler we treat operands of this form as not being
7989 * pcrel since the '.' is explicitly mentioned, and I wonder
7990 * whether it would simplify matters to do it this way. Who
7991 * knows. In earlier versions of the PIC patches, the
7992 * pcrel_adjust field was used to store the correction, but
7993 * since the expression is not pcrel, I felt it would be
7994 * confusing to do it this way. */
7995
7996 if ((reloc_type == BFD_RELOC_32
7997 || reloc_type == BFD_RELOC_X86_64_32S
7998 || reloc_type == BFD_RELOC_64)
7999 && GOT_symbol
8000 && GOT_symbol == i.op[n].imms->X_add_symbol
8001 && (i.op[n].imms->X_op == O_symbol
8002 || (i.op[n].imms->X_op == O_add
8003 && ((symbol_get_value_expression
8004 (i.op[n].imms->X_op_symbol)->X_op)
8005 == O_subtract))))
8006 {
8007 offsetT add;
8008
8009 if (insn_start_frag == frag_now)
8010 add = (p - frag_now->fr_literal) - insn_start_off;
8011 else
8012 {
8013 fragS *fr;
8014
8015 add = insn_start_frag->fr_fix - insn_start_off;
8016 for (fr = insn_start_frag->fr_next;
8017 fr && fr != frag_now; fr = fr->fr_next)
8018 add += fr->fr_fix;
8019 add += p - frag_now->fr_literal;
8020 }
8021
8022 if (!object_64bit)
8023 reloc_type = BFD_RELOC_386_GOTPC;
8024 else if (size == 4)
8025 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8026 else if (size == 8)
8027 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8028 i.op[n].imms->X_add_number += add;
8029 }
8030 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8031 i.op[n].imms, 0, reloc_type);
8032 }
8033 }
8034 }
8035 }
8036 \f
8037 /* x86_cons_fix_new is called via the expression parsing code when a
8038 reloc is needed. We use this hook to get the correct .got reloc. */
8039 static int cons_sign = -1;
8040
8041 void
8042 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
8043 expressionS *exp, bfd_reloc_code_real_type r)
8044 {
8045 r = reloc (len, 0, cons_sign, r);
8046
8047 #ifdef TE_PE
8048 if (exp->X_op == O_secrel)
8049 {
8050 exp->X_op = O_symbol;
8051 r = BFD_RELOC_32_SECREL;
8052 }
8053 #endif
8054
8055 fix_new_exp (frag, off, len, exp, 0, r);
8056 }
8057
8058 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8059 purpose of the `.dc.a' internal pseudo-op. */
8060
8061 int
8062 x86_address_bytes (void)
8063 {
8064 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8065 return 4;
8066 return stdoutput->arch_info->bits_per_address / 8;
8067 }
8068
8069 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8070 || defined (LEX_AT)
8071 # define lex_got(reloc, adjust, types) NULL
8072 #else
8073 /* Parse operands of the form
8074 <symbol>@GOTOFF+<nnn>
8075 and similar .plt or .got references.
8076
8077 If we find one, set up the correct relocation in RELOC and copy the
8078 input string, minus the `@GOTOFF' into a malloc'd buffer for
8079 parsing by the calling routine. Return this buffer, and if ADJUST
8080 is non-null set it to the length of the string we removed from the
8081 input line. Otherwise return NULL. */
8082 static char *
8083 lex_got (enum bfd_reloc_code_real *rel,
8084 int *adjust,
8085 i386_operand_type *types)
8086 {
8087 /* Some of the relocations depend on the size of what field is to
8088 be relocated. But in our callers i386_immediate and i386_displacement
8089 we don't yet know the operand size (this will be set by insn
8090 matching). Hence we record the word32 relocation here,
8091 and adjust the reloc according to the real size in reloc(). */
8092 static const struct {
8093 const char *str;
8094 int len;
8095 const enum bfd_reloc_code_real rel[2];
8096 const i386_operand_type types64;
8097 } gotrel[] = {
8098 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8099 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8100 BFD_RELOC_SIZE32 },
8101 OPERAND_TYPE_IMM32_64 },
8102 #endif
8103 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8104 BFD_RELOC_X86_64_PLTOFF64 },
8105 OPERAND_TYPE_IMM64 },
8106 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8107 BFD_RELOC_X86_64_PLT32 },
8108 OPERAND_TYPE_IMM32_32S_DISP32 },
8109 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8110 BFD_RELOC_X86_64_GOTPLT64 },
8111 OPERAND_TYPE_IMM64_DISP64 },
8112 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8113 BFD_RELOC_X86_64_GOTOFF64 },
8114 OPERAND_TYPE_IMM64_DISP64 },
8115 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8116 BFD_RELOC_X86_64_GOTPCREL },
8117 OPERAND_TYPE_IMM32_32S_DISP32 },
8118 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8119 BFD_RELOC_X86_64_TLSGD },
8120 OPERAND_TYPE_IMM32_32S_DISP32 },
8121 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8122 _dummy_first_bfd_reloc_code_real },
8123 OPERAND_TYPE_NONE },
8124 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8125 BFD_RELOC_X86_64_TLSLD },
8126 OPERAND_TYPE_IMM32_32S_DISP32 },
8127 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8128 BFD_RELOC_X86_64_GOTTPOFF },
8129 OPERAND_TYPE_IMM32_32S_DISP32 },
8130 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8131 BFD_RELOC_X86_64_TPOFF32 },
8132 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8133 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8134 _dummy_first_bfd_reloc_code_real },
8135 OPERAND_TYPE_NONE },
8136 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8137 BFD_RELOC_X86_64_DTPOFF32 },
8138 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8139 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8140 _dummy_first_bfd_reloc_code_real },
8141 OPERAND_TYPE_NONE },
8142 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8143 _dummy_first_bfd_reloc_code_real },
8144 OPERAND_TYPE_NONE },
8145 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8146 BFD_RELOC_X86_64_GOT32 },
8147 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8148 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8149 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8150 OPERAND_TYPE_IMM32_32S_DISP32 },
8151 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8152 BFD_RELOC_X86_64_TLSDESC_CALL },
8153 OPERAND_TYPE_IMM32_32S_DISP32 },
8154 };
8155 char *cp;
8156 unsigned int j;
8157
8158 #if defined (OBJ_MAYBE_ELF)
8159 if (!IS_ELF)
8160 return NULL;
8161 #endif
8162
8163 for (cp = input_line_pointer; *cp != '@'; cp++)
8164 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8165 return NULL;
8166
8167 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8168 {
8169 int len = gotrel[j].len;
8170 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8171 {
8172 if (gotrel[j].rel[object_64bit] != 0)
8173 {
8174 int first, second;
8175 char *tmpbuf, *past_reloc;
8176
8177 *rel = gotrel[j].rel[object_64bit];
8178
8179 if (types)
8180 {
8181 if (flag_code != CODE_64BIT)
8182 {
8183 types->bitfield.imm32 = 1;
8184 types->bitfield.disp32 = 1;
8185 }
8186 else
8187 *types = gotrel[j].types64;
8188 }
8189
8190 if (j != 0 && GOT_symbol == NULL)
8191 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8192
8193 /* The length of the first part of our input line. */
8194 first = cp - input_line_pointer;
8195
8196 /* The second part goes from after the reloc token until
8197 (and including) an end_of_line char or comma. */
8198 past_reloc = cp + 1 + len;
8199 cp = past_reloc;
8200 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8201 ++cp;
8202 second = cp + 1 - past_reloc;
8203
8204 /* Allocate and copy string. The trailing NUL shouldn't
8205 be necessary, but be safe. */
8206 tmpbuf = XNEWVEC (char, first + second + 2);
8207 memcpy (tmpbuf, input_line_pointer, first);
8208 if (second != 0 && *past_reloc != ' ')
8209 /* Replace the relocation token with ' ', so that
8210 errors like foo@GOTOFF1 will be detected. */
8211 tmpbuf[first++] = ' ';
8212 else
8213 /* Increment length by 1 if the relocation token is
8214 removed. */
8215 len++;
8216 if (adjust)
8217 *adjust = len;
8218 memcpy (tmpbuf + first, past_reloc, second);
8219 tmpbuf[first + second] = '\0';
8220 return tmpbuf;
8221 }
8222
8223 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8224 gotrel[j].str, 1 << (5 + object_64bit));
8225 return NULL;
8226 }
8227 }
8228
8229 /* Might be a symbol version string. Don't as_bad here. */
8230 return NULL;
8231 }
8232 #endif
8233
8234 #ifdef TE_PE
8235 #ifdef lex_got
8236 #undef lex_got
8237 #endif
8238 /* Parse operands of the form
8239 <symbol>@SECREL32+<nnn>
8240
8241 If we find one, set up the correct relocation in RELOC and copy the
8242 input string, minus the `@SECREL32' into a malloc'd buffer for
8243 parsing by the calling routine. Return this buffer, and if ADJUST
8244 is non-null set it to the length of the string we removed from the
8245 input line. Otherwise return NULL.
8246
8247 This function is copied from the ELF version above adjusted for PE targets. */
8248
8249 static char *
8250 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8251 int *adjust ATTRIBUTE_UNUSED,
8252 i386_operand_type *types)
8253 {
8254 static const struct
8255 {
8256 const char *str;
8257 int len;
8258 const enum bfd_reloc_code_real rel[2];
8259 const i386_operand_type types64;
8260 }
8261 gotrel[] =
8262 {
8263 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8264 BFD_RELOC_32_SECREL },
8265 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8266 };
8267
8268 char *cp;
8269 unsigned j;
8270
8271 for (cp = input_line_pointer; *cp != '@'; cp++)
8272 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8273 return NULL;
8274
8275 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8276 {
8277 int len = gotrel[j].len;
8278
8279 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8280 {
8281 if (gotrel[j].rel[object_64bit] != 0)
8282 {
8283 int first, second;
8284 char *tmpbuf, *past_reloc;
8285
8286 *rel = gotrel[j].rel[object_64bit];
8287 if (adjust)
8288 *adjust = len;
8289
8290 if (types)
8291 {
8292 if (flag_code != CODE_64BIT)
8293 {
8294 types->bitfield.imm32 = 1;
8295 types->bitfield.disp32 = 1;
8296 }
8297 else
8298 *types = gotrel[j].types64;
8299 }
8300
8301 /* The length of the first part of our input line. */
8302 first = cp - input_line_pointer;
8303
8304 /* The second part goes from after the reloc token until
8305 (and including) an end_of_line char or comma. */
8306 past_reloc = cp + 1 + len;
8307 cp = past_reloc;
8308 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8309 ++cp;
8310 second = cp + 1 - past_reloc;
8311
8312 /* Allocate and copy string. The trailing NUL shouldn't
8313 be necessary, but be safe. */
8314 tmpbuf = XNEWVEC (char, first + second + 2);
8315 memcpy (tmpbuf, input_line_pointer, first);
8316 if (second != 0 && *past_reloc != ' ')
8317 /* Replace the relocation token with ' ', so that
8318 errors like foo@SECLREL321 will be detected. */
8319 tmpbuf[first++] = ' ';
8320 memcpy (tmpbuf + first, past_reloc, second);
8321 tmpbuf[first + second] = '\0';
8322 return tmpbuf;
8323 }
8324
8325 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8326 gotrel[j].str, 1 << (5 + object_64bit));
8327 return NULL;
8328 }
8329 }
8330
8331 /* Might be a symbol version string. Don't as_bad here. */
8332 return NULL;
8333 }
8334
8335 #endif /* TE_PE */
8336
8337 bfd_reloc_code_real_type
8338 x86_cons (expressionS *exp, int size)
8339 {
8340 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8341
8342 intel_syntax = -intel_syntax;
8343
8344 exp->X_md = 0;
8345 if (size == 4 || (object_64bit && size == 8))
8346 {
8347 /* Handle @GOTOFF and the like in an expression. */
8348 char *save;
8349 char *gotfree_input_line;
8350 int adjust = 0;
8351
8352 save = input_line_pointer;
8353 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8354 if (gotfree_input_line)
8355 input_line_pointer = gotfree_input_line;
8356
8357 expression (exp);
8358
8359 if (gotfree_input_line)
8360 {
8361 /* expression () has merrily parsed up to the end of line,
8362 or a comma - in the wrong buffer. Transfer how far
8363 input_line_pointer has moved to the right buffer. */
8364 input_line_pointer = (save
8365 + (input_line_pointer - gotfree_input_line)
8366 + adjust);
8367 free (gotfree_input_line);
8368 if (exp->X_op == O_constant
8369 || exp->X_op == O_absent
8370 || exp->X_op == O_illegal
8371 || exp->X_op == O_register
8372 || exp->X_op == O_big)
8373 {
8374 char c = *input_line_pointer;
8375 *input_line_pointer = 0;
8376 as_bad (_("missing or invalid expression `%s'"), save);
8377 *input_line_pointer = c;
8378 }
8379 }
8380 }
8381 else
8382 expression (exp);
8383
8384 intel_syntax = -intel_syntax;
8385
8386 if (intel_syntax)
8387 i386_intel_simplify (exp);
8388
8389 return got_reloc;
8390 }
8391
8392 static void
8393 signed_cons (int size)
8394 {
8395 if (flag_code == CODE_64BIT)
8396 cons_sign = 1;
8397 cons (size);
8398 cons_sign = -1;
8399 }
8400
8401 #ifdef TE_PE
8402 static void
8403 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8404 {
8405 expressionS exp;
8406
8407 do
8408 {
8409 expression (&exp);
8410 if (exp.X_op == O_symbol)
8411 exp.X_op = O_secrel;
8412
8413 emit_expr (&exp, 4);
8414 }
8415 while (*input_line_pointer++ == ',');
8416
8417 input_line_pointer--;
8418 demand_empty_rest_of_line ();
8419 }
8420 #endif
8421
8422 /* Handle Vector operations. */
8423
8424 static char *
8425 check_VecOperations (char *op_string, char *op_end)
8426 {
8427 const reg_entry *mask;
8428 const char *saved;
8429 char *end_op;
8430
8431 while (*op_string
8432 && (op_end == NULL || op_string < op_end))
8433 {
8434 saved = op_string;
8435 if (*op_string == '{')
8436 {
8437 op_string++;
8438
8439 /* Check broadcasts. */
8440 if (strncmp (op_string, "1to", 3) == 0)
8441 {
8442 int bcst_type;
8443
8444 if (i.broadcast)
8445 goto duplicated_vec_op;
8446
8447 op_string += 3;
8448 if (*op_string == '8')
8449 bcst_type = 8;
8450 else if (*op_string == '4')
8451 bcst_type = 4;
8452 else if (*op_string == '2')
8453 bcst_type = 2;
8454 else if (*op_string == '1'
8455 && *(op_string+1) == '6')
8456 {
8457 bcst_type = 16;
8458 op_string++;
8459 }
8460 else
8461 {
8462 as_bad (_("Unsupported broadcast: `%s'"), saved);
8463 return NULL;
8464 }
8465 op_string++;
8466
8467 broadcast_op.type = bcst_type;
8468 broadcast_op.operand = this_operand;
8469 i.broadcast = &broadcast_op;
8470 }
8471 /* Check masking operation. */
8472 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8473 {
8474 /* k0 can't be used for write mask. */
8475 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8476 {
8477 as_bad (_("`%s%s' can't be used for write mask"),
8478 register_prefix, mask->reg_name);
8479 return NULL;
8480 }
8481
8482 if (!i.mask)
8483 {
8484 mask_op.mask = mask;
8485 mask_op.zeroing = 0;
8486 mask_op.operand = this_operand;
8487 i.mask = &mask_op;
8488 }
8489 else
8490 {
8491 if (i.mask->mask)
8492 goto duplicated_vec_op;
8493
8494 i.mask->mask = mask;
8495
8496 /* Only "{z}" is allowed here. No need to check
8497 zeroing mask explicitly. */
8498 if (i.mask->operand != this_operand)
8499 {
8500 as_bad (_("invalid write mask `%s'"), saved);
8501 return NULL;
8502 }
8503 }
8504
8505 op_string = end_op;
8506 }
8507 /* Check zeroing-flag for masking operation. */
8508 else if (*op_string == 'z')
8509 {
8510 if (!i.mask)
8511 {
8512 mask_op.mask = NULL;
8513 mask_op.zeroing = 1;
8514 mask_op.operand = this_operand;
8515 i.mask = &mask_op;
8516 }
8517 else
8518 {
8519 if (i.mask->zeroing)
8520 {
8521 duplicated_vec_op:
8522 as_bad (_("duplicated `%s'"), saved);
8523 return NULL;
8524 }
8525
8526 i.mask->zeroing = 1;
8527
8528 /* Only "{%k}" is allowed here. No need to check mask
8529 register explicitly. */
8530 if (i.mask->operand != this_operand)
8531 {
8532 as_bad (_("invalid zeroing-masking `%s'"),
8533 saved);
8534 return NULL;
8535 }
8536 }
8537
8538 op_string++;
8539 }
8540 else
8541 goto unknown_vec_op;
8542
8543 if (*op_string != '}')
8544 {
8545 as_bad (_("missing `}' in `%s'"), saved);
8546 return NULL;
8547 }
8548 op_string++;
8549
8550 /* Strip whitespace since the addition of pseudo prefixes
8551 changed how the scrubber treats '{'. */
8552 if (is_space_char (*op_string))
8553 ++op_string;
8554
8555 continue;
8556 }
8557 unknown_vec_op:
8558 /* We don't know this one. */
8559 as_bad (_("unknown vector operation: `%s'"), saved);
8560 return NULL;
8561 }
8562
8563 if (i.mask && i.mask->zeroing && !i.mask->mask)
8564 {
8565 as_bad (_("zeroing-masking only allowed with write mask"));
8566 return NULL;
8567 }
8568
8569 return op_string;
8570 }
8571
8572 static int
8573 i386_immediate (char *imm_start)
8574 {
8575 char *save_input_line_pointer;
8576 char *gotfree_input_line;
8577 segT exp_seg = 0;
8578 expressionS *exp;
8579 i386_operand_type types;
8580
8581 operand_type_set (&types, ~0);
8582
8583 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8584 {
8585 as_bad (_("at most %d immediate operands are allowed"),
8586 MAX_IMMEDIATE_OPERANDS);
8587 return 0;
8588 }
8589
8590 exp = &im_expressions[i.imm_operands++];
8591 i.op[this_operand].imms = exp;
8592
8593 if (is_space_char (*imm_start))
8594 ++imm_start;
8595
8596 save_input_line_pointer = input_line_pointer;
8597 input_line_pointer = imm_start;
8598
8599 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8600 if (gotfree_input_line)
8601 input_line_pointer = gotfree_input_line;
8602
8603 exp_seg = expression (exp);
8604
8605 SKIP_WHITESPACE ();
8606
8607 /* Handle vector operations. */
8608 if (*input_line_pointer == '{')
8609 {
8610 input_line_pointer = check_VecOperations (input_line_pointer,
8611 NULL);
8612 if (input_line_pointer == NULL)
8613 return 0;
8614 }
8615
8616 if (*input_line_pointer)
8617 as_bad (_("junk `%s' after expression"), input_line_pointer);
8618
8619 input_line_pointer = save_input_line_pointer;
8620 if (gotfree_input_line)
8621 {
8622 free (gotfree_input_line);
8623
8624 if (exp->X_op == O_constant || exp->X_op == O_register)
8625 exp->X_op = O_illegal;
8626 }
8627
8628 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8629 }
8630
8631 static int
8632 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8633 i386_operand_type types, const char *imm_start)
8634 {
8635 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8636 {
8637 if (imm_start)
8638 as_bad (_("missing or invalid immediate expression `%s'"),
8639 imm_start);
8640 return 0;
8641 }
8642 else if (exp->X_op == O_constant)
8643 {
8644 /* Size it properly later. */
8645 i.types[this_operand].bitfield.imm64 = 1;
8646 /* If not 64bit, sign extend val. */
8647 if (flag_code != CODE_64BIT
8648 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8649 exp->X_add_number
8650 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8651 }
8652 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8653 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8654 && exp_seg != absolute_section
8655 && exp_seg != text_section
8656 && exp_seg != data_section
8657 && exp_seg != bss_section
8658 && exp_seg != undefined_section
8659 && !bfd_is_com_section (exp_seg))
8660 {
8661 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8662 return 0;
8663 }
8664 #endif
8665 else if (!intel_syntax && exp_seg == reg_section)
8666 {
8667 if (imm_start)
8668 as_bad (_("illegal immediate register operand %s"), imm_start);
8669 return 0;
8670 }
8671 else
8672 {
8673 /* This is an address. The size of the address will be
8674 determined later, depending on destination register,
8675 suffix, or the default for the section. */
8676 i.types[this_operand].bitfield.imm8 = 1;
8677 i.types[this_operand].bitfield.imm16 = 1;
8678 i.types[this_operand].bitfield.imm32 = 1;
8679 i.types[this_operand].bitfield.imm32s = 1;
8680 i.types[this_operand].bitfield.imm64 = 1;
8681 i.types[this_operand] = operand_type_and (i.types[this_operand],
8682 types);
8683 }
8684
8685 return 1;
8686 }
8687
8688 static char *
8689 i386_scale (char *scale)
8690 {
8691 offsetT val;
8692 char *save = input_line_pointer;
8693
8694 input_line_pointer = scale;
8695 val = get_absolute_expression ();
8696
8697 switch (val)
8698 {
8699 case 1:
8700 i.log2_scale_factor = 0;
8701 break;
8702 case 2:
8703 i.log2_scale_factor = 1;
8704 break;
8705 case 4:
8706 i.log2_scale_factor = 2;
8707 break;
8708 case 8:
8709 i.log2_scale_factor = 3;
8710 break;
8711 default:
8712 {
8713 char sep = *input_line_pointer;
8714
8715 *input_line_pointer = '\0';
8716 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8717 scale);
8718 *input_line_pointer = sep;
8719 input_line_pointer = save;
8720 return NULL;
8721 }
8722 }
8723 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8724 {
8725 as_warn (_("scale factor of %d without an index register"),
8726 1 << i.log2_scale_factor);
8727 i.log2_scale_factor = 0;
8728 }
8729 scale = input_line_pointer;
8730 input_line_pointer = save;
8731 return scale;
8732 }
8733
8734 static int
8735 i386_displacement (char *disp_start, char *disp_end)
8736 {
8737 expressionS *exp;
8738 segT exp_seg = 0;
8739 char *save_input_line_pointer;
8740 char *gotfree_input_line;
8741 int override;
8742 i386_operand_type bigdisp, types = anydisp;
8743 int ret;
8744
8745 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8746 {
8747 as_bad (_("at most %d displacement operands are allowed"),
8748 MAX_MEMORY_OPERANDS);
8749 return 0;
8750 }
8751
8752 operand_type_set (&bigdisp, 0);
8753 if ((i.types[this_operand].bitfield.jumpabsolute)
8754 || (!current_templates->start->opcode_modifier.jump
8755 && !current_templates->start->opcode_modifier.jumpdword))
8756 {
8757 bigdisp.bitfield.disp32 = 1;
8758 override = (i.prefix[ADDR_PREFIX] != 0);
8759 if (flag_code == CODE_64BIT)
8760 {
8761 if (!override)
8762 {
8763 bigdisp.bitfield.disp32s = 1;
8764 bigdisp.bitfield.disp64 = 1;
8765 }
8766 }
8767 else if ((flag_code == CODE_16BIT) ^ override)
8768 {
8769 bigdisp.bitfield.disp32 = 0;
8770 bigdisp.bitfield.disp16 = 1;
8771 }
8772 }
8773 else
8774 {
8775 /* For PC-relative branches, the width of the displacement
8776 is dependent upon data size, not address size. */
8777 override = (i.prefix[DATA_PREFIX] != 0);
8778 if (flag_code == CODE_64BIT)
8779 {
8780 if (override || i.suffix == WORD_MNEM_SUFFIX)
8781 bigdisp.bitfield.disp16 = 1;
8782 else
8783 {
8784 bigdisp.bitfield.disp32 = 1;
8785 bigdisp.bitfield.disp32s = 1;
8786 }
8787 }
8788 else
8789 {
8790 if (!override)
8791 override = (i.suffix == (flag_code != CODE_16BIT
8792 ? WORD_MNEM_SUFFIX
8793 : LONG_MNEM_SUFFIX));
8794 bigdisp.bitfield.disp32 = 1;
8795 if ((flag_code == CODE_16BIT) ^ override)
8796 {
8797 bigdisp.bitfield.disp32 = 0;
8798 bigdisp.bitfield.disp16 = 1;
8799 }
8800 }
8801 }
8802 i.types[this_operand] = operand_type_or (i.types[this_operand],
8803 bigdisp);
8804
8805 exp = &disp_expressions[i.disp_operands];
8806 i.op[this_operand].disps = exp;
8807 i.disp_operands++;
8808 save_input_line_pointer = input_line_pointer;
8809 input_line_pointer = disp_start;
8810 END_STRING_AND_SAVE (disp_end);
8811
8812 #ifndef GCC_ASM_O_HACK
8813 #define GCC_ASM_O_HACK 0
8814 #endif
8815 #if GCC_ASM_O_HACK
8816 END_STRING_AND_SAVE (disp_end + 1);
8817 if (i.types[this_operand].bitfield.baseIndex
8818 && displacement_string_end[-1] == '+')
8819 {
8820 /* This hack is to avoid a warning when using the "o"
8821 constraint within gcc asm statements.
8822 For instance:
8823
8824 #define _set_tssldt_desc(n,addr,limit,type) \
8825 __asm__ __volatile__ ( \
8826 "movw %w2,%0\n\t" \
8827 "movw %w1,2+%0\n\t" \
8828 "rorl $16,%1\n\t" \
8829 "movb %b1,4+%0\n\t" \
8830 "movb %4,5+%0\n\t" \
8831 "movb $0,6+%0\n\t" \
8832 "movb %h1,7+%0\n\t" \
8833 "rorl $16,%1" \
8834 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8835
8836 This works great except that the output assembler ends
8837 up looking a bit weird if it turns out that there is
8838 no offset. You end up producing code that looks like:
8839
8840 #APP
8841 movw $235,(%eax)
8842 movw %dx,2+(%eax)
8843 rorl $16,%edx
8844 movb %dl,4+(%eax)
8845 movb $137,5+(%eax)
8846 movb $0,6+(%eax)
8847 movb %dh,7+(%eax)
8848 rorl $16,%edx
8849 #NO_APP
8850
8851 So here we provide the missing zero. */
8852
8853 *displacement_string_end = '0';
8854 }
8855 #endif
8856 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8857 if (gotfree_input_line)
8858 input_line_pointer = gotfree_input_line;
8859
8860 exp_seg = expression (exp);
8861
8862 SKIP_WHITESPACE ();
8863 if (*input_line_pointer)
8864 as_bad (_("junk `%s' after expression"), input_line_pointer);
8865 #if GCC_ASM_O_HACK
8866 RESTORE_END_STRING (disp_end + 1);
8867 #endif
8868 input_line_pointer = save_input_line_pointer;
8869 if (gotfree_input_line)
8870 {
8871 free (gotfree_input_line);
8872
8873 if (exp->X_op == O_constant || exp->X_op == O_register)
8874 exp->X_op = O_illegal;
8875 }
8876
8877 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8878
8879 RESTORE_END_STRING (disp_end);
8880
8881 return ret;
8882 }
8883
8884 static int
8885 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8886 i386_operand_type types, const char *disp_start)
8887 {
8888 i386_operand_type bigdisp;
8889 int ret = 1;
8890
8891 /* We do this to make sure that the section symbol is in
8892 the symbol table. We will ultimately change the relocation
8893 to be relative to the beginning of the section. */
8894 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8895 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8896 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8897 {
8898 if (exp->X_op != O_symbol)
8899 goto inv_disp;
8900
8901 if (S_IS_LOCAL (exp->X_add_symbol)
8902 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8903 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8904 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8905 exp->X_op = O_subtract;
8906 exp->X_op_symbol = GOT_symbol;
8907 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8908 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8909 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8910 i.reloc[this_operand] = BFD_RELOC_64;
8911 else
8912 i.reloc[this_operand] = BFD_RELOC_32;
8913 }
8914
8915 else if (exp->X_op == O_absent
8916 || exp->X_op == O_illegal
8917 || exp->X_op == O_big)
8918 {
8919 inv_disp:
8920 as_bad (_("missing or invalid displacement expression `%s'"),
8921 disp_start);
8922 ret = 0;
8923 }
8924
8925 else if (flag_code == CODE_64BIT
8926 && !i.prefix[ADDR_PREFIX]
8927 && exp->X_op == O_constant)
8928 {
8929 /* Since displacement is signed extended to 64bit, don't allow
8930 disp32 and turn off disp32s if they are out of range. */
8931 i.types[this_operand].bitfield.disp32 = 0;
8932 if (!fits_in_signed_long (exp->X_add_number))
8933 {
8934 i.types[this_operand].bitfield.disp32s = 0;
8935 if (i.types[this_operand].bitfield.baseindex)
8936 {
8937 as_bad (_("0x%lx out range of signed 32bit displacement"),
8938 (long) exp->X_add_number);
8939 ret = 0;
8940 }
8941 }
8942 }
8943
8944 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8945 else if (exp->X_op != O_constant
8946 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8947 && exp_seg != absolute_section
8948 && exp_seg != text_section
8949 && exp_seg != data_section
8950 && exp_seg != bss_section
8951 && exp_seg != undefined_section
8952 && !bfd_is_com_section (exp_seg))
8953 {
8954 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8955 ret = 0;
8956 }
8957 #endif
8958
8959 /* Check if this is a displacement only operand. */
8960 bigdisp = i.types[this_operand];
8961 bigdisp.bitfield.disp8 = 0;
8962 bigdisp.bitfield.disp16 = 0;
8963 bigdisp.bitfield.disp32 = 0;
8964 bigdisp.bitfield.disp32s = 0;
8965 bigdisp.bitfield.disp64 = 0;
8966 if (operand_type_all_zero (&bigdisp))
8967 i.types[this_operand] = operand_type_and (i.types[this_operand],
8968 types);
8969
8970 return ret;
8971 }
8972
8973 /* Return the active addressing mode, taking address override and
8974 registers forming the address into consideration. Update the
8975 address override prefix if necessary. */
8976
8977 static enum flag_code
8978 i386_addressing_mode (void)
8979 {
8980 enum flag_code addr_mode;
8981
8982 if (i.prefix[ADDR_PREFIX])
8983 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8984 else
8985 {
8986 addr_mode = flag_code;
8987
8988 #if INFER_ADDR_PREFIX
8989 if (i.mem_operands == 0)
8990 {
8991 /* Infer address prefix from the first memory operand. */
8992 const reg_entry *addr_reg = i.base_reg;
8993
8994 if (addr_reg == NULL)
8995 addr_reg = i.index_reg;
8996
8997 if (addr_reg)
8998 {
8999 if (addr_reg->reg_num == RegEip
9000 || addr_reg->reg_num == RegEiz
9001 || addr_reg->reg_type.bitfield.dword)
9002 addr_mode = CODE_32BIT;
9003 else if (flag_code != CODE_64BIT
9004 && addr_reg->reg_type.bitfield.word)
9005 addr_mode = CODE_16BIT;
9006
9007 if (addr_mode != flag_code)
9008 {
9009 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9010 i.prefixes += 1;
9011 /* Change the size of any displacement too. At most one
9012 of Disp16 or Disp32 is set.
9013 FIXME. There doesn't seem to be any real need for
9014 separate Disp16 and Disp32 flags. The same goes for
9015 Imm16 and Imm32. Removing them would probably clean
9016 up the code quite a lot. */
9017 if (flag_code != CODE_64BIT
9018 && (i.types[this_operand].bitfield.disp16
9019 || i.types[this_operand].bitfield.disp32))
9020 i.types[this_operand]
9021 = operand_type_xor (i.types[this_operand], disp16_32);
9022 }
9023 }
9024 }
9025 #endif
9026 }
9027
9028 return addr_mode;
9029 }
9030
9031 /* Make sure the memory operand we've been dealt is valid.
9032 Return 1 on success, 0 on a failure. */
9033
9034 static int
9035 i386_index_check (const char *operand_string)
9036 {
9037 const char *kind = "base/index";
9038 enum flag_code addr_mode = i386_addressing_mode ();
9039
9040 if (current_templates->start->opcode_modifier.isstring
9041 && !current_templates->start->opcode_modifier.immext
9042 && (current_templates->end[-1].opcode_modifier.isstring
9043 || i.mem_operands))
9044 {
9045 /* Memory operands of string insns are special in that they only allow
9046 a single register (rDI, rSI, or rBX) as their memory address. */
9047 const reg_entry *expected_reg;
9048 static const char *di_si[][2] =
9049 {
9050 { "esi", "edi" },
9051 { "si", "di" },
9052 { "rsi", "rdi" }
9053 };
9054 static const char *bx[] = { "ebx", "bx", "rbx" };
9055
9056 kind = "string address";
9057
9058 if (current_templates->start->opcode_modifier.repprefixok)
9059 {
9060 i386_operand_type type = current_templates->end[-1].operand_types[0];
9061
9062 if (!type.bitfield.baseindex
9063 || ((!i.mem_operands != !intel_syntax)
9064 && current_templates->end[-1].operand_types[1]
9065 .bitfield.baseindex))
9066 type = current_templates->end[-1].operand_types[1];
9067 expected_reg = hash_find (reg_hash,
9068 di_si[addr_mode][type.bitfield.esseg]);
9069
9070 }
9071 else
9072 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9073
9074 if (i.base_reg != expected_reg
9075 || i.index_reg
9076 || operand_type_check (i.types[this_operand], disp))
9077 {
9078 /* The second memory operand must have the same size as
9079 the first one. */
9080 if (i.mem_operands
9081 && i.base_reg
9082 && !((addr_mode == CODE_64BIT
9083 && i.base_reg->reg_type.bitfield.qword)
9084 || (addr_mode == CODE_32BIT
9085 ? i.base_reg->reg_type.bitfield.dword
9086 : i.base_reg->reg_type.bitfield.word)))
9087 goto bad_address;
9088
9089 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9090 operand_string,
9091 intel_syntax ? '[' : '(',
9092 register_prefix,
9093 expected_reg->reg_name,
9094 intel_syntax ? ']' : ')');
9095 return 1;
9096 }
9097 else
9098 return 1;
9099
9100 bad_address:
9101 as_bad (_("`%s' is not a valid %s expression"),
9102 operand_string, kind);
9103 return 0;
9104 }
9105 else
9106 {
9107 if (addr_mode != CODE_16BIT)
9108 {
9109 /* 32-bit/64-bit checks. */
9110 if ((i.base_reg
9111 && (addr_mode == CODE_64BIT
9112 ? !i.base_reg->reg_type.bitfield.qword
9113 : !i.base_reg->reg_type.bitfield.dword)
9114 && (i.index_reg
9115 || (i.base_reg->reg_num
9116 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9117 || (i.index_reg
9118 && !i.index_reg->reg_type.bitfield.xmmword
9119 && !i.index_reg->reg_type.bitfield.ymmword
9120 && !i.index_reg->reg_type.bitfield.zmmword
9121 && ((addr_mode == CODE_64BIT
9122 ? !(i.index_reg->reg_type.bitfield.qword
9123 || i.index_reg->reg_num == RegRiz)
9124 : !(i.index_reg->reg_type.bitfield.dword
9125 || i.index_reg->reg_num == RegEiz))
9126 || !i.index_reg->reg_type.bitfield.baseindex)))
9127 goto bad_address;
9128
9129 /* bndmk, bndldx, and bndstx have special restrictions. */
9130 if (current_templates->start->base_opcode == 0xf30f1b
9131 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9132 {
9133 /* They cannot use RIP-relative addressing. */
9134 if (i.base_reg && i.base_reg->reg_num == RegRip)
9135 {
9136 as_bad (_("`%s' cannot be used here"), operand_string);
9137 return 0;
9138 }
9139
9140 /* bndldx and bndstx ignore their scale factor. */
9141 if (current_templates->start->base_opcode != 0xf30f1b
9142 && i.log2_scale_factor)
9143 as_warn (_("register scaling is being ignored here"));
9144 }
9145 }
9146 else
9147 {
9148 /* 16-bit checks. */
9149 if ((i.base_reg
9150 && (!i.base_reg->reg_type.bitfield.word
9151 || !i.base_reg->reg_type.bitfield.baseindex))
9152 || (i.index_reg
9153 && (!i.index_reg->reg_type.bitfield.word
9154 || !i.index_reg->reg_type.bitfield.baseindex
9155 || !(i.base_reg
9156 && i.base_reg->reg_num < 6
9157 && i.index_reg->reg_num >= 6
9158 && i.log2_scale_factor == 0))))
9159 goto bad_address;
9160 }
9161 }
9162 return 1;
9163 }
9164
9165 /* Handle vector immediates. */
9166
9167 static int
9168 RC_SAE_immediate (const char *imm_start)
9169 {
9170 unsigned int match_found, j;
9171 const char *pstr = imm_start;
9172 expressionS *exp;
9173
9174 if (*pstr != '{')
9175 return 0;
9176
9177 pstr++;
9178 match_found = 0;
9179 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9180 {
9181 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9182 {
9183 if (!i.rounding)
9184 {
9185 rc_op.type = RC_NamesTable[j].type;
9186 rc_op.operand = this_operand;
9187 i.rounding = &rc_op;
9188 }
9189 else
9190 {
9191 as_bad (_("duplicated `%s'"), imm_start);
9192 return 0;
9193 }
9194 pstr += RC_NamesTable[j].len;
9195 match_found = 1;
9196 break;
9197 }
9198 }
9199 if (!match_found)
9200 return 0;
9201
9202 if (*pstr++ != '}')
9203 {
9204 as_bad (_("Missing '}': '%s'"), imm_start);
9205 return 0;
9206 }
9207 /* RC/SAE immediate string should contain nothing more. */;
9208 if (*pstr != 0)
9209 {
9210 as_bad (_("Junk after '}': '%s'"), imm_start);
9211 return 0;
9212 }
9213
9214 exp = &im_expressions[i.imm_operands++];
9215 i.op[this_operand].imms = exp;
9216
9217 exp->X_op = O_constant;
9218 exp->X_add_number = 0;
9219 exp->X_add_symbol = (symbolS *) 0;
9220 exp->X_op_symbol = (symbolS *) 0;
9221
9222 i.types[this_operand].bitfield.imm8 = 1;
9223 return 1;
9224 }
9225
9226 /* Only string instructions can have a second memory operand, so
9227 reduce current_templates to just those if it contains any. */
9228 static int
9229 maybe_adjust_templates (void)
9230 {
9231 const insn_template *t;
9232
9233 gas_assert (i.mem_operands == 1);
9234
9235 for (t = current_templates->start; t < current_templates->end; ++t)
9236 if (t->opcode_modifier.isstring)
9237 break;
9238
9239 if (t < current_templates->end)
9240 {
9241 static templates aux_templates;
9242 bfd_boolean recheck;
9243
9244 aux_templates.start = t;
9245 for (; t < current_templates->end; ++t)
9246 if (!t->opcode_modifier.isstring)
9247 break;
9248 aux_templates.end = t;
9249
9250 /* Determine whether to re-check the first memory operand. */
9251 recheck = (aux_templates.start != current_templates->start
9252 || t != current_templates->end);
9253
9254 current_templates = &aux_templates;
9255
9256 if (recheck)
9257 {
9258 i.mem_operands = 0;
9259 if (i.memop1_string != NULL
9260 && i386_index_check (i.memop1_string) == 0)
9261 return 0;
9262 i.mem_operands = 1;
9263 }
9264 }
9265
9266 return 1;
9267 }
9268
9269 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9270 on error. */
9271
9272 static int
9273 i386_att_operand (char *operand_string)
9274 {
9275 const reg_entry *r;
9276 char *end_op;
9277 char *op_string = operand_string;
9278
9279 if (is_space_char (*op_string))
9280 ++op_string;
9281
9282 /* We check for an absolute prefix (differentiating,
9283 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9284 if (*op_string == ABSOLUTE_PREFIX)
9285 {
9286 ++op_string;
9287 if (is_space_char (*op_string))
9288 ++op_string;
9289 i.types[this_operand].bitfield.jumpabsolute = 1;
9290 }
9291
9292 /* Check if operand is a register. */
9293 if ((r = parse_register (op_string, &end_op)) != NULL)
9294 {
9295 i386_operand_type temp;
9296
9297 /* Check for a segment override by searching for ':' after a
9298 segment register. */
9299 op_string = end_op;
9300 if (is_space_char (*op_string))
9301 ++op_string;
9302 if (*op_string == ':'
9303 && (r->reg_type.bitfield.sreg2
9304 || r->reg_type.bitfield.sreg3))
9305 {
9306 switch (r->reg_num)
9307 {
9308 case 0:
9309 i.seg[i.mem_operands] = &es;
9310 break;
9311 case 1:
9312 i.seg[i.mem_operands] = &cs;
9313 break;
9314 case 2:
9315 i.seg[i.mem_operands] = &ss;
9316 break;
9317 case 3:
9318 i.seg[i.mem_operands] = &ds;
9319 break;
9320 case 4:
9321 i.seg[i.mem_operands] = &fs;
9322 break;
9323 case 5:
9324 i.seg[i.mem_operands] = &gs;
9325 break;
9326 }
9327
9328 /* Skip the ':' and whitespace. */
9329 ++op_string;
9330 if (is_space_char (*op_string))
9331 ++op_string;
9332
9333 if (!is_digit_char (*op_string)
9334 && !is_identifier_char (*op_string)
9335 && *op_string != '('
9336 && *op_string != ABSOLUTE_PREFIX)
9337 {
9338 as_bad (_("bad memory operand `%s'"), op_string);
9339 return 0;
9340 }
9341 /* Handle case of %es:*foo. */
9342 if (*op_string == ABSOLUTE_PREFIX)
9343 {
9344 ++op_string;
9345 if (is_space_char (*op_string))
9346 ++op_string;
9347 i.types[this_operand].bitfield.jumpabsolute = 1;
9348 }
9349 goto do_memory_reference;
9350 }
9351
9352 /* Handle vector operations. */
9353 if (*op_string == '{')
9354 {
9355 op_string = check_VecOperations (op_string, NULL);
9356 if (op_string == NULL)
9357 return 0;
9358 }
9359
9360 if (*op_string)
9361 {
9362 as_bad (_("junk `%s' after register"), op_string);
9363 return 0;
9364 }
9365 temp = r->reg_type;
9366 temp.bitfield.baseindex = 0;
9367 i.types[this_operand] = operand_type_or (i.types[this_operand],
9368 temp);
9369 i.types[this_operand].bitfield.unspecified = 0;
9370 i.op[this_operand].regs = r;
9371 i.reg_operands++;
9372 }
9373 else if (*op_string == REGISTER_PREFIX)
9374 {
9375 as_bad (_("bad register name `%s'"), op_string);
9376 return 0;
9377 }
9378 else if (*op_string == IMMEDIATE_PREFIX)
9379 {
9380 ++op_string;
9381 if (i.types[this_operand].bitfield.jumpabsolute)
9382 {
9383 as_bad (_("immediate operand illegal with absolute jump"));
9384 return 0;
9385 }
9386 if (!i386_immediate (op_string))
9387 return 0;
9388 }
9389 else if (RC_SAE_immediate (operand_string))
9390 {
9391 /* If it is a RC or SAE immediate, do nothing. */
9392 ;
9393 }
9394 else if (is_digit_char (*op_string)
9395 || is_identifier_char (*op_string)
9396 || *op_string == '"'
9397 || *op_string == '(')
9398 {
9399 /* This is a memory reference of some sort. */
9400 char *base_string;
9401
9402 /* Start and end of displacement string expression (if found). */
9403 char *displacement_string_start;
9404 char *displacement_string_end;
9405 char *vop_start;
9406
9407 do_memory_reference:
9408 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9409 return 0;
9410 if ((i.mem_operands == 1
9411 && !current_templates->start->opcode_modifier.isstring)
9412 || i.mem_operands == 2)
9413 {
9414 as_bad (_("too many memory references for `%s'"),
9415 current_templates->start->name);
9416 return 0;
9417 }
9418
9419 /* Check for base index form. We detect the base index form by
9420 looking for an ')' at the end of the operand, searching
9421 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9422 after the '('. */
9423 base_string = op_string + strlen (op_string);
9424
9425 /* Handle vector operations. */
9426 vop_start = strchr (op_string, '{');
9427 if (vop_start && vop_start < base_string)
9428 {
9429 if (check_VecOperations (vop_start, base_string) == NULL)
9430 return 0;
9431 base_string = vop_start;
9432 }
9433
9434 --base_string;
9435 if (is_space_char (*base_string))
9436 --base_string;
9437
9438 /* If we only have a displacement, set-up for it to be parsed later. */
9439 displacement_string_start = op_string;
9440 displacement_string_end = base_string + 1;
9441
9442 if (*base_string == ')')
9443 {
9444 char *temp_string;
9445 unsigned int parens_balanced = 1;
9446 /* We've already checked that the number of left & right ()'s are
9447 equal, so this loop will not be infinite. */
9448 do
9449 {
9450 base_string--;
9451 if (*base_string == ')')
9452 parens_balanced++;
9453 if (*base_string == '(')
9454 parens_balanced--;
9455 }
9456 while (parens_balanced);
9457
9458 temp_string = base_string;
9459
9460 /* Skip past '(' and whitespace. */
9461 ++base_string;
9462 if (is_space_char (*base_string))
9463 ++base_string;
9464
9465 if (*base_string == ','
9466 || ((i.base_reg = parse_register (base_string, &end_op))
9467 != NULL))
9468 {
9469 displacement_string_end = temp_string;
9470
9471 i.types[this_operand].bitfield.baseindex = 1;
9472
9473 if (i.base_reg)
9474 {
9475 base_string = end_op;
9476 if (is_space_char (*base_string))
9477 ++base_string;
9478 }
9479
9480 /* There may be an index reg or scale factor here. */
9481 if (*base_string == ',')
9482 {
9483 ++base_string;
9484 if (is_space_char (*base_string))
9485 ++base_string;
9486
9487 if ((i.index_reg = parse_register (base_string, &end_op))
9488 != NULL)
9489 {
9490 base_string = end_op;
9491 if (is_space_char (*base_string))
9492 ++base_string;
9493 if (*base_string == ',')
9494 {
9495 ++base_string;
9496 if (is_space_char (*base_string))
9497 ++base_string;
9498 }
9499 else if (*base_string != ')')
9500 {
9501 as_bad (_("expecting `,' or `)' "
9502 "after index register in `%s'"),
9503 operand_string);
9504 return 0;
9505 }
9506 }
9507 else if (*base_string == REGISTER_PREFIX)
9508 {
9509 end_op = strchr (base_string, ',');
9510 if (end_op)
9511 *end_op = '\0';
9512 as_bad (_("bad register name `%s'"), base_string);
9513 return 0;
9514 }
9515
9516 /* Check for scale factor. */
9517 if (*base_string != ')')
9518 {
9519 char *end_scale = i386_scale (base_string);
9520
9521 if (!end_scale)
9522 return 0;
9523
9524 base_string = end_scale;
9525 if (is_space_char (*base_string))
9526 ++base_string;
9527 if (*base_string != ')')
9528 {
9529 as_bad (_("expecting `)' "
9530 "after scale factor in `%s'"),
9531 operand_string);
9532 return 0;
9533 }
9534 }
9535 else if (!i.index_reg)
9536 {
9537 as_bad (_("expecting index register or scale factor "
9538 "after `,'; got '%c'"),
9539 *base_string);
9540 return 0;
9541 }
9542 }
9543 else if (*base_string != ')')
9544 {
9545 as_bad (_("expecting `,' or `)' "
9546 "after base register in `%s'"),
9547 operand_string);
9548 return 0;
9549 }
9550 }
9551 else if (*base_string == REGISTER_PREFIX)
9552 {
9553 end_op = strchr (base_string, ',');
9554 if (end_op)
9555 *end_op = '\0';
9556 as_bad (_("bad register name `%s'"), base_string);
9557 return 0;
9558 }
9559 }
9560
9561 /* If there's an expression beginning the operand, parse it,
9562 assuming displacement_string_start and
9563 displacement_string_end are meaningful. */
9564 if (displacement_string_start != displacement_string_end)
9565 {
9566 if (!i386_displacement (displacement_string_start,
9567 displacement_string_end))
9568 return 0;
9569 }
9570
9571 /* Special case for (%dx) while doing input/output op. */
9572 if (i.base_reg
9573 && operand_type_equal (&i.base_reg->reg_type,
9574 &reg16_inoutportreg)
9575 && i.index_reg == 0
9576 && i.log2_scale_factor == 0
9577 && i.seg[i.mem_operands] == 0
9578 && !operand_type_check (i.types[this_operand], disp))
9579 {
9580 i.types[this_operand] = inoutportreg;
9581 return 1;
9582 }
9583
9584 if (i386_index_check (operand_string) == 0)
9585 return 0;
9586 i.types[this_operand].bitfield.mem = 1;
9587 if (i.mem_operands == 0)
9588 i.memop1_string = xstrdup (operand_string);
9589 i.mem_operands++;
9590 }
9591 else
9592 {
9593 /* It's not a memory operand; argh! */
9594 as_bad (_("invalid char %s beginning operand %d `%s'"),
9595 output_invalid (*op_string),
9596 this_operand + 1,
9597 op_string);
9598 return 0;
9599 }
9600 return 1; /* Normal return. */
9601 }
9602 \f
9603 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9604 that an rs_machine_dependent frag may reach. */
9605
9606 unsigned int
9607 i386_frag_max_var (fragS *frag)
9608 {
9609 /* The only relaxable frags are for jumps.
9610 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9611 gas_assert (frag->fr_type == rs_machine_dependent);
9612 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9613 }
9614
9615 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9616 static int
9617 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9618 {
9619 /* STT_GNU_IFUNC symbol must go through PLT. */
9620 if ((symbol_get_bfdsym (fr_symbol)->flags
9621 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9622 return 0;
9623
9624 if (!S_IS_EXTERNAL (fr_symbol))
9625 /* Symbol may be weak or local. */
9626 return !S_IS_WEAK (fr_symbol);
9627
9628 /* Global symbols with non-default visibility can't be preempted. */
9629 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9630 return 1;
9631
9632 if (fr_var != NO_RELOC)
9633 switch ((enum bfd_reloc_code_real) fr_var)
9634 {
9635 case BFD_RELOC_386_PLT32:
9636 case BFD_RELOC_X86_64_PLT32:
9637 /* Symbol with PLT relocation may be preempted. */
9638 return 0;
9639 default:
9640 abort ();
9641 }
9642
9643 /* Global symbols with default visibility in a shared library may be
9644 preempted by another definition. */
9645 return !shared;
9646 }
9647 #endif
9648
9649 /* md_estimate_size_before_relax()
9650
9651 Called just before relax() for rs_machine_dependent frags. The x86
9652 assembler uses these frags to handle variable size jump
9653 instructions.
9654
9655 Any symbol that is now undefined will not become defined.
9656 Return the correct fr_subtype in the frag.
9657 Return the initial "guess for variable size of frag" to caller.
9658 The guess is actually the growth beyond the fixed part. Whatever
9659 we do to grow the fixed or variable part contributes to our
9660 returned value. */
9661
9662 int
9663 md_estimate_size_before_relax (fragS *fragP, segT segment)
9664 {
9665 /* We've already got fragP->fr_subtype right; all we have to do is
9666 check for un-relaxable symbols. On an ELF system, we can't relax
9667 an externally visible symbol, because it may be overridden by a
9668 shared library. */
9669 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9670 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9671 || (IS_ELF
9672 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9673 fragP->fr_var))
9674 #endif
9675 #if defined (OBJ_COFF) && defined (TE_PE)
9676 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9677 && S_IS_WEAK (fragP->fr_symbol))
9678 #endif
9679 )
9680 {
9681 /* Symbol is undefined in this segment, or we need to keep a
9682 reloc so that weak symbols can be overridden. */
9683 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9684 enum bfd_reloc_code_real reloc_type;
9685 unsigned char *opcode;
9686 int old_fr_fix;
9687
9688 if (fragP->fr_var != NO_RELOC)
9689 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9690 else if (size == 2)
9691 reloc_type = BFD_RELOC_16_PCREL;
9692 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9693 else if (need_plt32_p (fragP->fr_symbol))
9694 reloc_type = BFD_RELOC_X86_64_PLT32;
9695 #endif
9696 else
9697 reloc_type = BFD_RELOC_32_PCREL;
9698
9699 old_fr_fix = fragP->fr_fix;
9700 opcode = (unsigned char *) fragP->fr_opcode;
9701
9702 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9703 {
9704 case UNCOND_JUMP:
9705 /* Make jmp (0xeb) a (d)word displacement jump. */
9706 opcode[0] = 0xe9;
9707 fragP->fr_fix += size;
9708 fix_new (fragP, old_fr_fix, size,
9709 fragP->fr_symbol,
9710 fragP->fr_offset, 1,
9711 reloc_type);
9712 break;
9713
9714 case COND_JUMP86:
9715 if (size == 2
9716 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9717 {
9718 /* Negate the condition, and branch past an
9719 unconditional jump. */
9720 opcode[0] ^= 1;
9721 opcode[1] = 3;
9722 /* Insert an unconditional jump. */
9723 opcode[2] = 0xe9;
9724 /* We added two extra opcode bytes, and have a two byte
9725 offset. */
9726 fragP->fr_fix += 2 + 2;
9727 fix_new (fragP, old_fr_fix + 2, 2,
9728 fragP->fr_symbol,
9729 fragP->fr_offset, 1,
9730 reloc_type);
9731 break;
9732 }
9733 /* Fall through. */
9734
9735 case COND_JUMP:
9736 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9737 {
9738 fixS *fixP;
9739
9740 fragP->fr_fix += 1;
9741 fixP = fix_new (fragP, old_fr_fix, 1,
9742 fragP->fr_symbol,
9743 fragP->fr_offset, 1,
9744 BFD_RELOC_8_PCREL);
9745 fixP->fx_signed = 1;
9746 break;
9747 }
9748
9749 /* This changes the byte-displacement jump 0x7N
9750 to the (d)word-displacement jump 0x0f,0x8N. */
9751 opcode[1] = opcode[0] + 0x10;
9752 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9753 /* We've added an opcode byte. */
9754 fragP->fr_fix += 1 + size;
9755 fix_new (fragP, old_fr_fix + 1, size,
9756 fragP->fr_symbol,
9757 fragP->fr_offset, 1,
9758 reloc_type);
9759 break;
9760
9761 default:
9762 BAD_CASE (fragP->fr_subtype);
9763 break;
9764 }
9765 frag_wane (fragP);
9766 return fragP->fr_fix - old_fr_fix;
9767 }
9768
9769 /* Guess size depending on current relax state. Initially the relax
9770 state will correspond to a short jump and we return 1, because
9771 the variable part of the frag (the branch offset) is one byte
9772 long. However, we can relax a section more than once and in that
9773 case we must either set fr_subtype back to the unrelaxed state,
9774 or return the value for the appropriate branch. */
9775 return md_relax_table[fragP->fr_subtype].rlx_length;
9776 }
9777
9778 /* Called after relax() is finished.
9779
9780 In: Address of frag.
9781 fr_type == rs_machine_dependent.
9782 fr_subtype is what the address relaxed to.
9783
9784 Out: Any fixSs and constants are set up.
9785 Caller will turn frag into a ".space 0". */
9786
9787 void
9788 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9789 fragS *fragP)
9790 {
9791 unsigned char *opcode;
9792 unsigned char *where_to_put_displacement = NULL;
9793 offsetT target_address;
9794 offsetT opcode_address;
9795 unsigned int extension = 0;
9796 offsetT displacement_from_opcode_start;
9797
9798 opcode = (unsigned char *) fragP->fr_opcode;
9799
9800 /* Address we want to reach in file space. */
9801 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9802
9803 /* Address opcode resides at in file space. */
9804 opcode_address = fragP->fr_address + fragP->fr_fix;
9805
9806 /* Displacement from opcode start to fill into instruction. */
9807 displacement_from_opcode_start = target_address - opcode_address;
9808
9809 if ((fragP->fr_subtype & BIG) == 0)
9810 {
9811 /* Don't have to change opcode. */
9812 extension = 1; /* 1 opcode + 1 displacement */
9813 where_to_put_displacement = &opcode[1];
9814 }
9815 else
9816 {
9817 if (no_cond_jump_promotion
9818 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9819 as_warn_where (fragP->fr_file, fragP->fr_line,
9820 _("long jump required"));
9821
9822 switch (fragP->fr_subtype)
9823 {
9824 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9825 extension = 4; /* 1 opcode + 4 displacement */
9826 opcode[0] = 0xe9;
9827 where_to_put_displacement = &opcode[1];
9828 break;
9829
9830 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9831 extension = 2; /* 1 opcode + 2 displacement */
9832 opcode[0] = 0xe9;
9833 where_to_put_displacement = &opcode[1];
9834 break;
9835
9836 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9837 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9838 extension = 5; /* 2 opcode + 4 displacement */
9839 opcode[1] = opcode[0] + 0x10;
9840 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9841 where_to_put_displacement = &opcode[2];
9842 break;
9843
9844 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9845 extension = 3; /* 2 opcode + 2 displacement */
9846 opcode[1] = opcode[0] + 0x10;
9847 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9848 where_to_put_displacement = &opcode[2];
9849 break;
9850
9851 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9852 extension = 4;
9853 opcode[0] ^= 1;
9854 opcode[1] = 3;
9855 opcode[2] = 0xe9;
9856 where_to_put_displacement = &opcode[3];
9857 break;
9858
9859 default:
9860 BAD_CASE (fragP->fr_subtype);
9861 break;
9862 }
9863 }
9864
9865 /* If size if less then four we are sure that the operand fits,
9866 but if it's 4, then it could be that the displacement is larger
9867 then -/+ 2GB. */
9868 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9869 && object_64bit
9870 && ((addressT) (displacement_from_opcode_start - extension
9871 + ((addressT) 1 << 31))
9872 > (((addressT) 2 << 31) - 1)))
9873 {
9874 as_bad_where (fragP->fr_file, fragP->fr_line,
9875 _("jump target out of range"));
9876 /* Make us emit 0. */
9877 displacement_from_opcode_start = extension;
9878 }
9879 /* Now put displacement after opcode. */
9880 md_number_to_chars ((char *) where_to_put_displacement,
9881 (valueT) (displacement_from_opcode_start - extension),
9882 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9883 fragP->fr_fix += extension;
9884 }
9885 \f
9886 /* Apply a fixup (fixP) to segment data, once it has been determined
9887 by our caller that we have all the info we need to fix it up.
9888
9889 Parameter valP is the pointer to the value of the bits.
9890
9891 On the 386, immediates, displacements, and data pointers are all in
9892 the same (little-endian) format, so we don't need to care about which
9893 we are handling. */
9894
9895 void
9896 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9897 {
9898 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9899 valueT value = *valP;
9900
9901 #if !defined (TE_Mach)
9902 if (fixP->fx_pcrel)
9903 {
9904 switch (fixP->fx_r_type)
9905 {
9906 default:
9907 break;
9908
9909 case BFD_RELOC_64:
9910 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9911 break;
9912 case BFD_RELOC_32:
9913 case BFD_RELOC_X86_64_32S:
9914 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9915 break;
9916 case BFD_RELOC_16:
9917 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9918 break;
9919 case BFD_RELOC_8:
9920 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9921 break;
9922 }
9923 }
9924
9925 if (fixP->fx_addsy != NULL
9926 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9927 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9928 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9929 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9930 && !use_rela_relocations)
9931 {
9932 /* This is a hack. There should be a better way to handle this.
9933 This covers for the fact that bfd_install_relocation will
9934 subtract the current location (for partial_inplace, PC relative
9935 relocations); see more below. */
9936 #ifndef OBJ_AOUT
9937 if (IS_ELF
9938 #ifdef TE_PE
9939 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9940 #endif
9941 )
9942 value += fixP->fx_where + fixP->fx_frag->fr_address;
9943 #endif
9944 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9945 if (IS_ELF)
9946 {
9947 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9948
9949 if ((sym_seg == seg
9950 || (symbol_section_p (fixP->fx_addsy)
9951 && sym_seg != absolute_section))
9952 && !generic_force_reloc (fixP))
9953 {
9954 /* Yes, we add the values in twice. This is because
9955 bfd_install_relocation subtracts them out again. I think
9956 bfd_install_relocation is broken, but I don't dare change
9957 it. FIXME. */
9958 value += fixP->fx_where + fixP->fx_frag->fr_address;
9959 }
9960 }
9961 #endif
9962 #if defined (OBJ_COFF) && defined (TE_PE)
9963 /* For some reason, the PE format does not store a
9964 section address offset for a PC relative symbol. */
9965 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9966 || S_IS_WEAK (fixP->fx_addsy))
9967 value += md_pcrel_from (fixP);
9968 #endif
9969 }
9970 #if defined (OBJ_COFF) && defined (TE_PE)
9971 if (fixP->fx_addsy != NULL
9972 && S_IS_WEAK (fixP->fx_addsy)
9973 /* PR 16858: Do not modify weak function references. */
9974 && ! fixP->fx_pcrel)
9975 {
9976 #if !defined (TE_PEP)
9977 /* For x86 PE weak function symbols are neither PC-relative
9978 nor do they set S_IS_FUNCTION. So the only reliable way
9979 to detect them is to check the flags of their containing
9980 section. */
9981 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9982 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9983 ;
9984 else
9985 #endif
9986 value -= S_GET_VALUE (fixP->fx_addsy);
9987 }
9988 #endif
9989
9990 /* Fix a few things - the dynamic linker expects certain values here,
9991 and we must not disappoint it. */
9992 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9993 if (IS_ELF && fixP->fx_addsy)
9994 switch (fixP->fx_r_type)
9995 {
9996 case BFD_RELOC_386_PLT32:
9997 case BFD_RELOC_X86_64_PLT32:
9998 /* Make the jump instruction point to the address of the operand. At
9999 runtime we merely add the offset to the actual PLT entry. */
10000 value = -4;
10001 break;
10002
10003 case BFD_RELOC_386_TLS_GD:
10004 case BFD_RELOC_386_TLS_LDM:
10005 case BFD_RELOC_386_TLS_IE_32:
10006 case BFD_RELOC_386_TLS_IE:
10007 case BFD_RELOC_386_TLS_GOTIE:
10008 case BFD_RELOC_386_TLS_GOTDESC:
10009 case BFD_RELOC_X86_64_TLSGD:
10010 case BFD_RELOC_X86_64_TLSLD:
10011 case BFD_RELOC_X86_64_GOTTPOFF:
10012 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10013 value = 0; /* Fully resolved at runtime. No addend. */
10014 /* Fallthrough */
10015 case BFD_RELOC_386_TLS_LE:
10016 case BFD_RELOC_386_TLS_LDO_32:
10017 case BFD_RELOC_386_TLS_LE_32:
10018 case BFD_RELOC_X86_64_DTPOFF32:
10019 case BFD_RELOC_X86_64_DTPOFF64:
10020 case BFD_RELOC_X86_64_TPOFF32:
10021 case BFD_RELOC_X86_64_TPOFF64:
10022 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10023 break;
10024
10025 case BFD_RELOC_386_TLS_DESC_CALL:
10026 case BFD_RELOC_X86_64_TLSDESC_CALL:
10027 value = 0; /* Fully resolved at runtime. No addend. */
10028 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10029 fixP->fx_done = 0;
10030 return;
10031
10032 case BFD_RELOC_VTABLE_INHERIT:
10033 case BFD_RELOC_VTABLE_ENTRY:
10034 fixP->fx_done = 0;
10035 return;
10036
10037 default:
10038 break;
10039 }
10040 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10041 *valP = value;
10042 #endif /* !defined (TE_Mach) */
10043
10044 /* Are we finished with this relocation now? */
10045 if (fixP->fx_addsy == NULL)
10046 fixP->fx_done = 1;
10047 #if defined (OBJ_COFF) && defined (TE_PE)
10048 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10049 {
10050 fixP->fx_done = 0;
10051 /* Remember value for tc_gen_reloc. */
10052 fixP->fx_addnumber = value;
10053 /* Clear out the frag for now. */
10054 value = 0;
10055 }
10056 #endif
10057 else if (use_rela_relocations)
10058 {
10059 fixP->fx_no_overflow = 1;
10060 /* Remember value for tc_gen_reloc. */
10061 fixP->fx_addnumber = value;
10062 value = 0;
10063 }
10064
10065 md_number_to_chars (p, value, fixP->fx_size);
10066 }
10067 \f
10068 const char *
10069 md_atof (int type, char *litP, int *sizeP)
10070 {
10071 /* This outputs the LITTLENUMs in REVERSE order;
10072 in accord with the bigendian 386. */
10073 return ieee_md_atof (type, litP, sizeP, FALSE);
10074 }
10075 \f
10076 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10077
10078 static char *
10079 output_invalid (int c)
10080 {
10081 if (ISPRINT (c))
10082 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10083 "'%c'", c);
10084 else
10085 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10086 "(0x%x)", (unsigned char) c);
10087 return output_invalid_buf;
10088 }
10089
10090 /* REG_STRING starts *before* REGISTER_PREFIX. */
10091
10092 static const reg_entry *
10093 parse_real_register (char *reg_string, char **end_op)
10094 {
10095 char *s = reg_string;
10096 char *p;
10097 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10098 const reg_entry *r;
10099
10100 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10101 if (*s == REGISTER_PREFIX)
10102 ++s;
10103
10104 if (is_space_char (*s))
10105 ++s;
10106
10107 p = reg_name_given;
10108 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10109 {
10110 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10111 return (const reg_entry *) NULL;
10112 s++;
10113 }
10114
10115 /* For naked regs, make sure that we are not dealing with an identifier.
10116 This prevents confusing an identifier like `eax_var' with register
10117 `eax'. */
10118 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10119 return (const reg_entry *) NULL;
10120
10121 *end_op = s;
10122
10123 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10124
10125 /* Handle floating point regs, allowing spaces in the (i) part. */
10126 if (r == i386_regtab /* %st is first entry of table */)
10127 {
10128 if (is_space_char (*s))
10129 ++s;
10130 if (*s == '(')
10131 {
10132 ++s;
10133 if (is_space_char (*s))
10134 ++s;
10135 if (*s >= '0' && *s <= '7')
10136 {
10137 int fpr = *s - '0';
10138 ++s;
10139 if (is_space_char (*s))
10140 ++s;
10141 if (*s == ')')
10142 {
10143 *end_op = s + 1;
10144 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10145 know (r);
10146 return r + fpr;
10147 }
10148 }
10149 /* We have "%st(" then garbage. */
10150 return (const reg_entry *) NULL;
10151 }
10152 }
10153
10154 if (r == NULL || allow_pseudo_reg)
10155 return r;
10156
10157 if (operand_type_all_zero (&r->reg_type))
10158 return (const reg_entry *) NULL;
10159
10160 if ((r->reg_type.bitfield.dword
10161 || r->reg_type.bitfield.sreg3
10162 || r->reg_type.bitfield.control
10163 || r->reg_type.bitfield.debug
10164 || r->reg_type.bitfield.test)
10165 && !cpu_arch_flags.bitfield.cpui386)
10166 return (const reg_entry *) NULL;
10167
10168 if (r->reg_type.bitfield.tbyte
10169 && !cpu_arch_flags.bitfield.cpu8087
10170 && !cpu_arch_flags.bitfield.cpu287
10171 && !cpu_arch_flags.bitfield.cpu387)
10172 return (const reg_entry *) NULL;
10173
10174 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
10175 return (const reg_entry *) NULL;
10176
10177 if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
10178 return (const reg_entry *) NULL;
10179
10180 if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
10181 return (const reg_entry *) NULL;
10182
10183 if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
10184 return (const reg_entry *) NULL;
10185
10186 if (r->reg_type.bitfield.regmask
10187 && !cpu_arch_flags.bitfield.cpuregmask)
10188 return (const reg_entry *) NULL;
10189
10190 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10191 if (!allow_index_reg
10192 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10193 return (const reg_entry *) NULL;
10194
10195 /* Upper 16 vector register is only available with VREX in 64bit
10196 mode. */
10197 if ((r->reg_flags & RegVRex))
10198 {
10199 if (i.vec_encoding == vex_encoding_default)
10200 i.vec_encoding = vex_encoding_evex;
10201
10202 if (!cpu_arch_flags.bitfield.cpuvrex
10203 || i.vec_encoding != vex_encoding_evex
10204 || flag_code != CODE_64BIT)
10205 return (const reg_entry *) NULL;
10206 }
10207
10208 if (((r->reg_flags & (RegRex64 | RegRex))
10209 || r->reg_type.bitfield.qword)
10210 && (!cpu_arch_flags.bitfield.cpulm
10211 || !operand_type_equal (&r->reg_type, &control))
10212 && flag_code != CODE_64BIT)
10213 return (const reg_entry *) NULL;
10214
10215 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10216 return (const reg_entry *) NULL;
10217
10218 return r;
10219 }
10220
10221 /* REG_STRING starts *before* REGISTER_PREFIX. */
10222
10223 static const reg_entry *
10224 parse_register (char *reg_string, char **end_op)
10225 {
10226 const reg_entry *r;
10227
10228 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10229 r = parse_real_register (reg_string, end_op);
10230 else
10231 r = NULL;
10232 if (!r)
10233 {
10234 char *save = input_line_pointer;
10235 char c;
10236 symbolS *symbolP;
10237
10238 input_line_pointer = reg_string;
10239 c = get_symbol_name (&reg_string);
10240 symbolP = symbol_find (reg_string);
10241 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10242 {
10243 const expressionS *e = symbol_get_value_expression (symbolP);
10244
10245 know (e->X_op == O_register);
10246 know (e->X_add_number >= 0
10247 && (valueT) e->X_add_number < i386_regtab_size);
10248 r = i386_regtab + e->X_add_number;
10249 if ((r->reg_flags & RegVRex))
10250 i.vec_encoding = vex_encoding_evex;
10251 *end_op = input_line_pointer;
10252 }
10253 *input_line_pointer = c;
10254 input_line_pointer = save;
10255 }
10256 return r;
10257 }
10258
10259 int
10260 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10261 {
10262 const reg_entry *r;
10263 char *end = input_line_pointer;
10264
10265 *end = *nextcharP;
10266 r = parse_register (name, &input_line_pointer);
10267 if (r && end <= input_line_pointer)
10268 {
10269 *nextcharP = *input_line_pointer;
10270 *input_line_pointer = 0;
10271 e->X_op = O_register;
10272 e->X_add_number = r - i386_regtab;
10273 return 1;
10274 }
10275 input_line_pointer = end;
10276 *end = 0;
10277 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10278 }
10279
10280 void
10281 md_operand (expressionS *e)
10282 {
10283 char *end;
10284 const reg_entry *r;
10285
10286 switch (*input_line_pointer)
10287 {
10288 case REGISTER_PREFIX:
10289 r = parse_real_register (input_line_pointer, &end);
10290 if (r)
10291 {
10292 e->X_op = O_register;
10293 e->X_add_number = r - i386_regtab;
10294 input_line_pointer = end;
10295 }
10296 break;
10297
10298 case '[':
10299 gas_assert (intel_syntax);
10300 end = input_line_pointer++;
10301 expression (e);
10302 if (*input_line_pointer == ']')
10303 {
10304 ++input_line_pointer;
10305 e->X_op_symbol = make_expr_symbol (e);
10306 e->X_add_symbol = NULL;
10307 e->X_add_number = 0;
10308 e->X_op = O_index;
10309 }
10310 else
10311 {
10312 e->X_op = O_absent;
10313 input_line_pointer = end;
10314 }
10315 break;
10316 }
10317 }
10318
10319 \f
10320 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10321 const char *md_shortopts = "kVQ:sqnO::";
10322 #else
10323 const char *md_shortopts = "qnO::";
10324 #endif
10325
10326 #define OPTION_32 (OPTION_MD_BASE + 0)
10327 #define OPTION_64 (OPTION_MD_BASE + 1)
10328 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10329 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10330 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10331 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10332 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10333 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10334 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10335 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10336 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10337 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10338 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10339 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10340 #define OPTION_X32 (OPTION_MD_BASE + 14)
10341 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10342 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10343 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10344 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10345 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10346 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10347 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10348 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10349 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10350 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10351
10352 struct option md_longopts[] =
10353 {
10354 {"32", no_argument, NULL, OPTION_32},
10355 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10356 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10357 {"64", no_argument, NULL, OPTION_64},
10358 #endif
10359 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10360 {"x32", no_argument, NULL, OPTION_X32},
10361 {"mshared", no_argument, NULL, OPTION_MSHARED},
10362 #endif
10363 {"divide", no_argument, NULL, OPTION_DIVIDE},
10364 {"march", required_argument, NULL, OPTION_MARCH},
10365 {"mtune", required_argument, NULL, OPTION_MTUNE},
10366 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10367 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10368 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10369 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10370 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10371 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10372 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10373 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10374 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10375 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10376 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10377 # if defined (TE_PE) || defined (TE_PEP)
10378 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10379 #endif
10380 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10381 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10382 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10383 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10384 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10385 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10386 {NULL, no_argument, NULL, 0}
10387 };
10388 size_t md_longopts_size = sizeof (md_longopts);
10389
10390 int
10391 md_parse_option (int c, const char *arg)
10392 {
10393 unsigned int j;
10394 char *arch, *next, *saved;
10395
10396 switch (c)
10397 {
10398 case 'n':
10399 optimize_align_code = 0;
10400 break;
10401
10402 case 'q':
10403 quiet_warnings = 1;
10404 break;
10405
10406 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10407 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10408 should be emitted or not. FIXME: Not implemented. */
10409 case 'Q':
10410 break;
10411
10412 /* -V: SVR4 argument to print version ID. */
10413 case 'V':
10414 print_version_id ();
10415 break;
10416
10417 /* -k: Ignore for FreeBSD compatibility. */
10418 case 'k':
10419 break;
10420
10421 case 's':
10422 /* -s: On i386 Solaris, this tells the native assembler to use
10423 .stab instead of .stab.excl. We always use .stab anyhow. */
10424 break;
10425
10426 case OPTION_MSHARED:
10427 shared = 1;
10428 break;
10429 #endif
10430 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10431 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10432 case OPTION_64:
10433 {
10434 const char **list, **l;
10435
10436 list = bfd_target_list ();
10437 for (l = list; *l != NULL; l++)
10438 if (CONST_STRNEQ (*l, "elf64-x86-64")
10439 || strcmp (*l, "coff-x86-64") == 0
10440 || strcmp (*l, "pe-x86-64") == 0
10441 || strcmp (*l, "pei-x86-64") == 0
10442 || strcmp (*l, "mach-o-x86-64") == 0)
10443 {
10444 default_arch = "x86_64";
10445 break;
10446 }
10447 if (*l == NULL)
10448 as_fatal (_("no compiled in support for x86_64"));
10449 free (list);
10450 }
10451 break;
10452 #endif
10453
10454 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10455 case OPTION_X32:
10456 if (IS_ELF)
10457 {
10458 const char **list, **l;
10459
10460 list = bfd_target_list ();
10461 for (l = list; *l != NULL; l++)
10462 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10463 {
10464 default_arch = "x86_64:32";
10465 break;
10466 }
10467 if (*l == NULL)
10468 as_fatal (_("no compiled in support for 32bit x86_64"));
10469 free (list);
10470 }
10471 else
10472 as_fatal (_("32bit x86_64 is only supported for ELF"));
10473 break;
10474 #endif
10475
10476 case OPTION_32:
10477 default_arch = "i386";
10478 break;
10479
10480 case OPTION_DIVIDE:
10481 #ifdef SVR4_COMMENT_CHARS
10482 {
10483 char *n, *t;
10484 const char *s;
10485
10486 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10487 t = n;
10488 for (s = i386_comment_chars; *s != '\0'; s++)
10489 if (*s != '/')
10490 *t++ = *s;
10491 *t = '\0';
10492 i386_comment_chars = n;
10493 }
10494 #endif
10495 break;
10496
10497 case OPTION_MARCH:
10498 saved = xstrdup (arg);
10499 arch = saved;
10500 /* Allow -march=+nosse. */
10501 if (*arch == '+')
10502 arch++;
10503 do
10504 {
10505 if (*arch == '.')
10506 as_fatal (_("invalid -march= option: `%s'"), arg);
10507 next = strchr (arch, '+');
10508 if (next)
10509 *next++ = '\0';
10510 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10511 {
10512 if (strcmp (arch, cpu_arch [j].name) == 0)
10513 {
10514 /* Processor. */
10515 if (! cpu_arch[j].flags.bitfield.cpui386)
10516 continue;
10517
10518 cpu_arch_name = cpu_arch[j].name;
10519 cpu_sub_arch_name = NULL;
10520 cpu_arch_flags = cpu_arch[j].flags;
10521 cpu_arch_isa = cpu_arch[j].type;
10522 cpu_arch_isa_flags = cpu_arch[j].flags;
10523 if (!cpu_arch_tune_set)
10524 {
10525 cpu_arch_tune = cpu_arch_isa;
10526 cpu_arch_tune_flags = cpu_arch_isa_flags;
10527 }
10528 break;
10529 }
10530 else if (*cpu_arch [j].name == '.'
10531 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10532 {
10533 /* ISA extension. */
10534 i386_cpu_flags flags;
10535
10536 flags = cpu_flags_or (cpu_arch_flags,
10537 cpu_arch[j].flags);
10538
10539 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10540 {
10541 if (cpu_sub_arch_name)
10542 {
10543 char *name = cpu_sub_arch_name;
10544 cpu_sub_arch_name = concat (name,
10545 cpu_arch[j].name,
10546 (const char *) NULL);
10547 free (name);
10548 }
10549 else
10550 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10551 cpu_arch_flags = flags;
10552 cpu_arch_isa_flags = flags;
10553 }
10554 else
10555 cpu_arch_isa_flags
10556 = cpu_flags_or (cpu_arch_isa_flags,
10557 cpu_arch[j].flags);
10558 break;
10559 }
10560 }
10561
10562 if (j >= ARRAY_SIZE (cpu_arch))
10563 {
10564 /* Disable an ISA extension. */
10565 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10566 if (strcmp (arch, cpu_noarch [j].name) == 0)
10567 {
10568 i386_cpu_flags flags;
10569
10570 flags = cpu_flags_and_not (cpu_arch_flags,
10571 cpu_noarch[j].flags);
10572 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10573 {
10574 if (cpu_sub_arch_name)
10575 {
10576 char *name = cpu_sub_arch_name;
10577 cpu_sub_arch_name = concat (arch,
10578 (const char *) NULL);
10579 free (name);
10580 }
10581 else
10582 cpu_sub_arch_name = xstrdup (arch);
10583 cpu_arch_flags = flags;
10584 cpu_arch_isa_flags = flags;
10585 }
10586 break;
10587 }
10588
10589 if (j >= ARRAY_SIZE (cpu_noarch))
10590 j = ARRAY_SIZE (cpu_arch);
10591 }
10592
10593 if (j >= ARRAY_SIZE (cpu_arch))
10594 as_fatal (_("invalid -march= option: `%s'"), arg);
10595
10596 arch = next;
10597 }
10598 while (next != NULL);
10599 free (saved);
10600 break;
10601
10602 case OPTION_MTUNE:
10603 if (*arg == '.')
10604 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10605 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10606 {
10607 if (strcmp (arg, cpu_arch [j].name) == 0)
10608 {
10609 cpu_arch_tune_set = 1;
10610 cpu_arch_tune = cpu_arch [j].type;
10611 cpu_arch_tune_flags = cpu_arch[j].flags;
10612 break;
10613 }
10614 }
10615 if (j >= ARRAY_SIZE (cpu_arch))
10616 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10617 break;
10618
10619 case OPTION_MMNEMONIC:
10620 if (strcasecmp (arg, "att") == 0)
10621 intel_mnemonic = 0;
10622 else if (strcasecmp (arg, "intel") == 0)
10623 intel_mnemonic = 1;
10624 else
10625 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10626 break;
10627
10628 case OPTION_MSYNTAX:
10629 if (strcasecmp (arg, "att") == 0)
10630 intel_syntax = 0;
10631 else if (strcasecmp (arg, "intel") == 0)
10632 intel_syntax = 1;
10633 else
10634 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10635 break;
10636
10637 case OPTION_MINDEX_REG:
10638 allow_index_reg = 1;
10639 break;
10640
10641 case OPTION_MNAKED_REG:
10642 allow_naked_reg = 1;
10643 break;
10644
10645 case OPTION_MSSE2AVX:
10646 sse2avx = 1;
10647 break;
10648
10649 case OPTION_MSSE_CHECK:
10650 if (strcasecmp (arg, "error") == 0)
10651 sse_check = check_error;
10652 else if (strcasecmp (arg, "warning") == 0)
10653 sse_check = check_warning;
10654 else if (strcasecmp (arg, "none") == 0)
10655 sse_check = check_none;
10656 else
10657 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10658 break;
10659
10660 case OPTION_MOPERAND_CHECK:
10661 if (strcasecmp (arg, "error") == 0)
10662 operand_check = check_error;
10663 else if (strcasecmp (arg, "warning") == 0)
10664 operand_check = check_warning;
10665 else if (strcasecmp (arg, "none") == 0)
10666 operand_check = check_none;
10667 else
10668 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10669 break;
10670
10671 case OPTION_MAVXSCALAR:
10672 if (strcasecmp (arg, "128") == 0)
10673 avxscalar = vex128;
10674 else if (strcasecmp (arg, "256") == 0)
10675 avxscalar = vex256;
10676 else
10677 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10678 break;
10679
10680 case OPTION_MADD_BND_PREFIX:
10681 add_bnd_prefix = 1;
10682 break;
10683
10684 case OPTION_MEVEXLIG:
10685 if (strcmp (arg, "128") == 0)
10686 evexlig = evexl128;
10687 else if (strcmp (arg, "256") == 0)
10688 evexlig = evexl256;
10689 else if (strcmp (arg, "512") == 0)
10690 evexlig = evexl512;
10691 else
10692 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10693 break;
10694
10695 case OPTION_MEVEXRCIG:
10696 if (strcmp (arg, "rne") == 0)
10697 evexrcig = rne;
10698 else if (strcmp (arg, "rd") == 0)
10699 evexrcig = rd;
10700 else if (strcmp (arg, "ru") == 0)
10701 evexrcig = ru;
10702 else if (strcmp (arg, "rz") == 0)
10703 evexrcig = rz;
10704 else
10705 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10706 break;
10707
10708 case OPTION_MEVEXWIG:
10709 if (strcmp (arg, "0") == 0)
10710 evexwig = evexw0;
10711 else if (strcmp (arg, "1") == 0)
10712 evexwig = evexw1;
10713 else
10714 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10715 break;
10716
10717 # if defined (TE_PE) || defined (TE_PEP)
10718 case OPTION_MBIG_OBJ:
10719 use_big_obj = 1;
10720 break;
10721 #endif
10722
10723 case OPTION_MOMIT_LOCK_PREFIX:
10724 if (strcasecmp (arg, "yes") == 0)
10725 omit_lock_prefix = 1;
10726 else if (strcasecmp (arg, "no") == 0)
10727 omit_lock_prefix = 0;
10728 else
10729 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10730 break;
10731
10732 case OPTION_MFENCE_AS_LOCK_ADD:
10733 if (strcasecmp (arg, "yes") == 0)
10734 avoid_fence = 1;
10735 else if (strcasecmp (arg, "no") == 0)
10736 avoid_fence = 0;
10737 else
10738 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10739 break;
10740
10741 case OPTION_MRELAX_RELOCATIONS:
10742 if (strcasecmp (arg, "yes") == 0)
10743 generate_relax_relocations = 1;
10744 else if (strcasecmp (arg, "no") == 0)
10745 generate_relax_relocations = 0;
10746 else
10747 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10748 break;
10749
10750 case OPTION_MAMD64:
10751 intel64 = 0;
10752 break;
10753
10754 case OPTION_MINTEL64:
10755 intel64 = 1;
10756 break;
10757
10758 case 'O':
10759 if (arg == NULL)
10760 {
10761 optimize = 1;
10762 /* Turn off -Os. */
10763 optimize_for_space = 0;
10764 }
10765 else if (*arg == 's')
10766 {
10767 optimize_for_space = 1;
10768 /* Turn on all encoding optimizations. */
10769 optimize = -1;
10770 }
10771 else
10772 {
10773 optimize = atoi (arg);
10774 /* Turn off -Os. */
10775 optimize_for_space = 0;
10776 }
10777 break;
10778
10779 default:
10780 return 0;
10781 }
10782 return 1;
10783 }
10784
10785 #define MESSAGE_TEMPLATE \
10786 " "
10787
10788 static char *
10789 output_message (FILE *stream, char *p, char *message, char *start,
10790 int *left_p, const char *name, int len)
10791 {
10792 int size = sizeof (MESSAGE_TEMPLATE);
10793 int left = *left_p;
10794
10795 /* Reserve 2 spaces for ", " or ",\0" */
10796 left -= len + 2;
10797
10798 /* Check if there is any room. */
10799 if (left >= 0)
10800 {
10801 if (p != start)
10802 {
10803 *p++ = ',';
10804 *p++ = ' ';
10805 }
10806 p = mempcpy (p, name, len);
10807 }
10808 else
10809 {
10810 /* Output the current message now and start a new one. */
10811 *p++ = ',';
10812 *p = '\0';
10813 fprintf (stream, "%s\n", message);
10814 p = start;
10815 left = size - (start - message) - len - 2;
10816
10817 gas_assert (left >= 0);
10818
10819 p = mempcpy (p, name, len);
10820 }
10821
10822 *left_p = left;
10823 return p;
10824 }
10825
10826 static void
10827 show_arch (FILE *stream, int ext, int check)
10828 {
10829 static char message[] = MESSAGE_TEMPLATE;
10830 char *start = message + 27;
10831 char *p;
10832 int size = sizeof (MESSAGE_TEMPLATE);
10833 int left;
10834 const char *name;
10835 int len;
10836 unsigned int j;
10837
10838 p = start;
10839 left = size - (start - message);
10840 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10841 {
10842 /* Should it be skipped? */
10843 if (cpu_arch [j].skip)
10844 continue;
10845
10846 name = cpu_arch [j].name;
10847 len = cpu_arch [j].len;
10848 if (*name == '.')
10849 {
10850 /* It is an extension. Skip if we aren't asked to show it. */
10851 if (ext)
10852 {
10853 name++;
10854 len--;
10855 }
10856 else
10857 continue;
10858 }
10859 else if (ext)
10860 {
10861 /* It is an processor. Skip if we show only extension. */
10862 continue;
10863 }
10864 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10865 {
10866 /* It is an impossible processor - skip. */
10867 continue;
10868 }
10869
10870 p = output_message (stream, p, message, start, &left, name, len);
10871 }
10872
10873 /* Display disabled extensions. */
10874 if (ext)
10875 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10876 {
10877 name = cpu_noarch [j].name;
10878 len = cpu_noarch [j].len;
10879 p = output_message (stream, p, message, start, &left, name,
10880 len);
10881 }
10882
10883 *p = '\0';
10884 fprintf (stream, "%s\n", message);
10885 }
10886
10887 void
10888 md_show_usage (FILE *stream)
10889 {
10890 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10891 fprintf (stream, _("\
10892 -Q ignored\n\
10893 -V print assembler version number\n\
10894 -k ignored\n"));
10895 #endif
10896 fprintf (stream, _("\
10897 -n Do not optimize code alignment\n\
10898 -q quieten some warnings\n"));
10899 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10900 fprintf (stream, _("\
10901 -s ignored\n"));
10902 #endif
10903 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10904 || defined (TE_PE) || defined (TE_PEP))
10905 fprintf (stream, _("\
10906 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10907 #endif
10908 #ifdef SVR4_COMMENT_CHARS
10909 fprintf (stream, _("\
10910 --divide do not treat `/' as a comment character\n"));
10911 #else
10912 fprintf (stream, _("\
10913 --divide ignored\n"));
10914 #endif
10915 fprintf (stream, _("\
10916 -march=CPU[,+EXTENSION...]\n\
10917 generate code for CPU and EXTENSION, CPU is one of:\n"));
10918 show_arch (stream, 0, 1);
10919 fprintf (stream, _("\
10920 EXTENSION is combination of:\n"));
10921 show_arch (stream, 1, 0);
10922 fprintf (stream, _("\
10923 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10924 show_arch (stream, 0, 0);
10925 fprintf (stream, _("\
10926 -msse2avx encode SSE instructions with VEX prefix\n"));
10927 fprintf (stream, _("\
10928 -msse-check=[none|error|warning]\n\
10929 check SSE instructions\n"));
10930 fprintf (stream, _("\
10931 -moperand-check=[none|error|warning]\n\
10932 check operand combinations for validity\n"));
10933 fprintf (stream, _("\
10934 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10935 length\n"));
10936 fprintf (stream, _("\
10937 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10938 length\n"));
10939 fprintf (stream, _("\
10940 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10941 for EVEX.W bit ignored instructions\n"));
10942 fprintf (stream, _("\
10943 -mevexrcig=[rne|rd|ru|rz]\n\
10944 encode EVEX instructions with specific EVEX.RC value\n\
10945 for SAE-only ignored instructions\n"));
10946 fprintf (stream, _("\
10947 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10948 fprintf (stream, _("\
10949 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10950 fprintf (stream, _("\
10951 -mindex-reg support pseudo index registers\n"));
10952 fprintf (stream, _("\
10953 -mnaked-reg don't require `%%' prefix for registers\n"));
10954 fprintf (stream, _("\
10955 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10956 fprintf (stream, _("\
10957 -mshared disable branch optimization for shared code\n"));
10958 # if defined (TE_PE) || defined (TE_PEP)
10959 fprintf (stream, _("\
10960 -mbig-obj generate big object files\n"));
10961 #endif
10962 fprintf (stream, _("\
10963 -momit-lock-prefix=[no|yes]\n\
10964 strip all lock prefixes\n"));
10965 fprintf (stream, _("\
10966 -mfence-as-lock-add=[no|yes]\n\
10967 encode lfence, mfence and sfence as\n\
10968 lock addl $0x0, (%%{re}sp)\n"));
10969 fprintf (stream, _("\
10970 -mrelax-relocations=[no|yes]\n\
10971 generate relax relocations\n"));
10972 fprintf (stream, _("\
10973 -mamd64 accept only AMD64 ISA\n"));
10974 fprintf (stream, _("\
10975 -mintel64 accept only Intel64 ISA\n"));
10976 }
10977
10978 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10979 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10980 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10981
10982 /* Pick the target format to use. */
10983
10984 const char *
10985 i386_target_format (void)
10986 {
10987 if (!strncmp (default_arch, "x86_64", 6))
10988 {
10989 update_code_flag (CODE_64BIT, 1);
10990 if (default_arch[6] == '\0')
10991 x86_elf_abi = X86_64_ABI;
10992 else
10993 x86_elf_abi = X86_64_X32_ABI;
10994 }
10995 else if (!strcmp (default_arch, "i386"))
10996 update_code_flag (CODE_32BIT, 1);
10997 else if (!strcmp (default_arch, "iamcu"))
10998 {
10999 update_code_flag (CODE_32BIT, 1);
11000 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
11001 {
11002 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11003 cpu_arch_name = "iamcu";
11004 cpu_sub_arch_name = NULL;
11005 cpu_arch_flags = iamcu_flags;
11006 cpu_arch_isa = PROCESSOR_IAMCU;
11007 cpu_arch_isa_flags = iamcu_flags;
11008 if (!cpu_arch_tune_set)
11009 {
11010 cpu_arch_tune = cpu_arch_isa;
11011 cpu_arch_tune_flags = cpu_arch_isa_flags;
11012 }
11013 }
11014 else if (cpu_arch_isa != PROCESSOR_IAMCU)
11015 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11016 cpu_arch_name);
11017 }
11018 else
11019 as_fatal (_("unknown architecture"));
11020
11021 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11022 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11023 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11024 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11025
11026 switch (OUTPUT_FLAVOR)
11027 {
11028 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11029 case bfd_target_aout_flavour:
11030 return AOUT_TARGET_FORMAT;
11031 #endif
11032 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11033 # if defined (TE_PE) || defined (TE_PEP)
11034 case bfd_target_coff_flavour:
11035 if (flag_code == CODE_64BIT)
11036 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11037 else
11038 return "pe-i386";
11039 # elif defined (TE_GO32)
11040 case bfd_target_coff_flavour:
11041 return "coff-go32";
11042 # else
11043 case bfd_target_coff_flavour:
11044 return "coff-i386";
11045 # endif
11046 #endif
11047 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11048 case bfd_target_elf_flavour:
11049 {
11050 const char *format;
11051
11052 switch (x86_elf_abi)
11053 {
11054 default:
11055 format = ELF_TARGET_FORMAT;
11056 break;
11057 case X86_64_ABI:
11058 use_rela_relocations = 1;
11059 object_64bit = 1;
11060 format = ELF_TARGET_FORMAT64;
11061 break;
11062 case X86_64_X32_ABI:
11063 use_rela_relocations = 1;
11064 object_64bit = 1;
11065 disallow_64bit_reloc = 1;
11066 format = ELF_TARGET_FORMAT32;
11067 break;
11068 }
11069 if (cpu_arch_isa == PROCESSOR_L1OM)
11070 {
11071 if (x86_elf_abi != X86_64_ABI)
11072 as_fatal (_("Intel L1OM is 64bit only"));
11073 return ELF_TARGET_L1OM_FORMAT;
11074 }
11075 else if (cpu_arch_isa == PROCESSOR_K1OM)
11076 {
11077 if (x86_elf_abi != X86_64_ABI)
11078 as_fatal (_("Intel K1OM is 64bit only"));
11079 return ELF_TARGET_K1OM_FORMAT;
11080 }
11081 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11082 {
11083 if (x86_elf_abi != I386_ABI)
11084 as_fatal (_("Intel MCU is 32bit only"));
11085 return ELF_TARGET_IAMCU_FORMAT;
11086 }
11087 else
11088 return format;
11089 }
11090 #endif
11091 #if defined (OBJ_MACH_O)
11092 case bfd_target_mach_o_flavour:
11093 if (flag_code == CODE_64BIT)
11094 {
11095 use_rela_relocations = 1;
11096 object_64bit = 1;
11097 return "mach-o-x86-64";
11098 }
11099 else
11100 return "mach-o-i386";
11101 #endif
11102 default:
11103 abort ();
11104 return NULL;
11105 }
11106 }
11107
11108 #endif /* OBJ_MAYBE_ more than one */
11109 \f
11110 symbolS *
11111 md_undefined_symbol (char *name)
11112 {
11113 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11114 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11115 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11116 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11117 {
11118 if (!GOT_symbol)
11119 {
11120 if (symbol_find (name))
11121 as_bad (_("GOT already in symbol table"));
11122 GOT_symbol = symbol_new (name, undefined_section,
11123 (valueT) 0, &zero_address_frag);
11124 };
11125 return GOT_symbol;
11126 }
11127 return 0;
11128 }
11129
11130 /* Round up a section size to the appropriate boundary. */
11131
11132 valueT
11133 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11134 {
11135 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11136 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11137 {
11138 /* For a.out, force the section size to be aligned. If we don't do
11139 this, BFD will align it for us, but it will not write out the
11140 final bytes of the section. This may be a bug in BFD, but it is
11141 easier to fix it here since that is how the other a.out targets
11142 work. */
11143 int align;
11144
11145 align = bfd_get_section_alignment (stdoutput, segment);
11146 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11147 }
11148 #endif
11149
11150 return size;
11151 }
11152
11153 /* On the i386, PC-relative offsets are relative to the start of the
11154 next instruction. That is, the address of the offset, plus its
11155 size, since the offset is always the last part of the insn. */
11156
11157 long
11158 md_pcrel_from (fixS *fixP)
11159 {
11160 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11161 }
11162
11163 #ifndef I386COFF
11164
11165 static void
11166 s_bss (int ignore ATTRIBUTE_UNUSED)
11167 {
11168 int temp;
11169
11170 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11171 if (IS_ELF)
11172 obj_elf_section_change_hook ();
11173 #endif
11174 temp = get_absolute_expression ();
11175 subseg_set (bss_section, (subsegT) temp);
11176 demand_empty_rest_of_line ();
11177 }
11178
11179 #endif
11180
11181 void
11182 i386_validate_fix (fixS *fixp)
11183 {
11184 if (fixp->fx_subsy)
11185 {
11186 if (fixp->fx_subsy == GOT_symbol)
11187 {
11188 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11189 {
11190 if (!object_64bit)
11191 abort ();
11192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11193 if (fixp->fx_tcbit2)
11194 fixp->fx_r_type = (fixp->fx_tcbit
11195 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11196 : BFD_RELOC_X86_64_GOTPCRELX);
11197 else
11198 #endif
11199 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11200 }
11201 else
11202 {
11203 if (!object_64bit)
11204 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11205 else
11206 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11207 }
11208 fixp->fx_subsy = 0;
11209 }
11210 }
11211 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11212 else if (!object_64bit)
11213 {
11214 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11215 && fixp->fx_tcbit2)
11216 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11217 }
11218 #endif
11219 }
11220
11221 arelent *
11222 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
11223 {
11224 arelent *rel;
11225 bfd_reloc_code_real_type code;
11226
11227 switch (fixp->fx_r_type)
11228 {
11229 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11230 case BFD_RELOC_SIZE32:
11231 case BFD_RELOC_SIZE64:
11232 if (S_IS_DEFINED (fixp->fx_addsy)
11233 && !S_IS_EXTERNAL (fixp->fx_addsy))
11234 {
11235 /* Resolve size relocation against local symbol to size of
11236 the symbol plus addend. */
11237 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11238 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11239 && !fits_in_unsigned_long (value))
11240 as_bad_where (fixp->fx_file, fixp->fx_line,
11241 _("symbol size computation overflow"));
11242 fixp->fx_addsy = NULL;
11243 fixp->fx_subsy = NULL;
11244 md_apply_fix (fixp, (valueT *) &value, NULL);
11245 return NULL;
11246 }
11247 #endif
11248 /* Fall through. */
11249
11250 case BFD_RELOC_X86_64_PLT32:
11251 case BFD_RELOC_X86_64_GOT32:
11252 case BFD_RELOC_X86_64_GOTPCREL:
11253 case BFD_RELOC_X86_64_GOTPCRELX:
11254 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11255 case BFD_RELOC_386_PLT32:
11256 case BFD_RELOC_386_GOT32:
11257 case BFD_RELOC_386_GOT32X:
11258 case BFD_RELOC_386_GOTOFF:
11259 case BFD_RELOC_386_GOTPC:
11260 case BFD_RELOC_386_TLS_GD:
11261 case BFD_RELOC_386_TLS_LDM:
11262 case BFD_RELOC_386_TLS_LDO_32:
11263 case BFD_RELOC_386_TLS_IE_32:
11264 case BFD_RELOC_386_TLS_IE:
11265 case BFD_RELOC_386_TLS_GOTIE:
11266 case BFD_RELOC_386_TLS_LE_32:
11267 case BFD_RELOC_386_TLS_LE:
11268 case BFD_RELOC_386_TLS_GOTDESC:
11269 case BFD_RELOC_386_TLS_DESC_CALL:
11270 case BFD_RELOC_X86_64_TLSGD:
11271 case BFD_RELOC_X86_64_TLSLD:
11272 case BFD_RELOC_X86_64_DTPOFF32:
11273 case BFD_RELOC_X86_64_DTPOFF64:
11274 case BFD_RELOC_X86_64_GOTTPOFF:
11275 case BFD_RELOC_X86_64_TPOFF32:
11276 case BFD_RELOC_X86_64_TPOFF64:
11277 case BFD_RELOC_X86_64_GOTOFF64:
11278 case BFD_RELOC_X86_64_GOTPC32:
11279 case BFD_RELOC_X86_64_GOT64:
11280 case BFD_RELOC_X86_64_GOTPCREL64:
11281 case BFD_RELOC_X86_64_GOTPC64:
11282 case BFD_RELOC_X86_64_GOTPLT64:
11283 case BFD_RELOC_X86_64_PLTOFF64:
11284 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11285 case BFD_RELOC_X86_64_TLSDESC_CALL:
11286 case BFD_RELOC_RVA:
11287 case BFD_RELOC_VTABLE_ENTRY:
11288 case BFD_RELOC_VTABLE_INHERIT:
11289 #ifdef TE_PE
11290 case BFD_RELOC_32_SECREL:
11291 #endif
11292 code = fixp->fx_r_type;
11293 break;
11294 case BFD_RELOC_X86_64_32S:
11295 if (!fixp->fx_pcrel)
11296 {
11297 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11298 code = fixp->fx_r_type;
11299 break;
11300 }
11301 /* Fall through. */
11302 default:
11303 if (fixp->fx_pcrel)
11304 {
11305 switch (fixp->fx_size)
11306 {
11307 default:
11308 as_bad_where (fixp->fx_file, fixp->fx_line,
11309 _("can not do %d byte pc-relative relocation"),
11310 fixp->fx_size);
11311 code = BFD_RELOC_32_PCREL;
11312 break;
11313 case 1: code = BFD_RELOC_8_PCREL; break;
11314 case 2: code = BFD_RELOC_16_PCREL; break;
11315 case 4: code = BFD_RELOC_32_PCREL; break;
11316 #ifdef BFD64
11317 case 8: code = BFD_RELOC_64_PCREL; break;
11318 #endif
11319 }
11320 }
11321 else
11322 {
11323 switch (fixp->fx_size)
11324 {
11325 default:
11326 as_bad_where (fixp->fx_file, fixp->fx_line,
11327 _("can not do %d byte relocation"),
11328 fixp->fx_size);
11329 code = BFD_RELOC_32;
11330 break;
11331 case 1: code = BFD_RELOC_8; break;
11332 case 2: code = BFD_RELOC_16; break;
11333 case 4: code = BFD_RELOC_32; break;
11334 #ifdef BFD64
11335 case 8: code = BFD_RELOC_64; break;
11336 #endif
11337 }
11338 }
11339 break;
11340 }
11341
11342 if ((code == BFD_RELOC_32
11343 || code == BFD_RELOC_32_PCREL
11344 || code == BFD_RELOC_X86_64_32S)
11345 && GOT_symbol
11346 && fixp->fx_addsy == GOT_symbol)
11347 {
11348 if (!object_64bit)
11349 code = BFD_RELOC_386_GOTPC;
11350 else
11351 code = BFD_RELOC_X86_64_GOTPC32;
11352 }
11353 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11354 && GOT_symbol
11355 && fixp->fx_addsy == GOT_symbol)
11356 {
11357 code = BFD_RELOC_X86_64_GOTPC64;
11358 }
11359
11360 rel = XNEW (arelent);
11361 rel->sym_ptr_ptr = XNEW (asymbol *);
11362 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11363
11364 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11365
11366 if (!use_rela_relocations)
11367 {
11368 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11369 vtable entry to be used in the relocation's section offset. */
11370 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11371 rel->address = fixp->fx_offset;
11372 #if defined (OBJ_COFF) && defined (TE_PE)
11373 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11374 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11375 else
11376 #endif
11377 rel->addend = 0;
11378 }
11379 /* Use the rela in 64bit mode. */
11380 else
11381 {
11382 if (disallow_64bit_reloc)
11383 switch (code)
11384 {
11385 case BFD_RELOC_X86_64_DTPOFF64:
11386 case BFD_RELOC_X86_64_TPOFF64:
11387 case BFD_RELOC_64_PCREL:
11388 case BFD_RELOC_X86_64_GOTOFF64:
11389 case BFD_RELOC_X86_64_GOT64:
11390 case BFD_RELOC_X86_64_GOTPCREL64:
11391 case BFD_RELOC_X86_64_GOTPC64:
11392 case BFD_RELOC_X86_64_GOTPLT64:
11393 case BFD_RELOC_X86_64_PLTOFF64:
11394 as_bad_where (fixp->fx_file, fixp->fx_line,
11395 _("cannot represent relocation type %s in x32 mode"),
11396 bfd_get_reloc_code_name (code));
11397 break;
11398 default:
11399 break;
11400 }
11401
11402 if (!fixp->fx_pcrel)
11403 rel->addend = fixp->fx_offset;
11404 else
11405 switch (code)
11406 {
11407 case BFD_RELOC_X86_64_PLT32:
11408 case BFD_RELOC_X86_64_GOT32:
11409 case BFD_RELOC_X86_64_GOTPCREL:
11410 case BFD_RELOC_X86_64_GOTPCRELX:
11411 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11412 case BFD_RELOC_X86_64_TLSGD:
11413 case BFD_RELOC_X86_64_TLSLD:
11414 case BFD_RELOC_X86_64_GOTTPOFF:
11415 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11416 case BFD_RELOC_X86_64_TLSDESC_CALL:
11417 rel->addend = fixp->fx_offset - fixp->fx_size;
11418 break;
11419 default:
11420 rel->addend = (section->vma
11421 - fixp->fx_size
11422 + fixp->fx_addnumber
11423 + md_pcrel_from (fixp));
11424 break;
11425 }
11426 }
11427
11428 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11429 if (rel->howto == NULL)
11430 {
11431 as_bad_where (fixp->fx_file, fixp->fx_line,
11432 _("cannot represent relocation type %s"),
11433 bfd_get_reloc_code_name (code));
11434 /* Set howto to a garbage value so that we can keep going. */
11435 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11436 gas_assert (rel->howto != NULL);
11437 }
11438
11439 return rel;
11440 }
11441
11442 #include "tc-i386-intel.c"
11443
11444 void
11445 tc_x86_parse_to_dw2regnum (expressionS *exp)
11446 {
11447 int saved_naked_reg;
11448 char saved_register_dot;
11449
11450 saved_naked_reg = allow_naked_reg;
11451 allow_naked_reg = 1;
11452 saved_register_dot = register_chars['.'];
11453 register_chars['.'] = '.';
11454 allow_pseudo_reg = 1;
11455 expression_and_evaluate (exp);
11456 allow_pseudo_reg = 0;
11457 register_chars['.'] = saved_register_dot;
11458 allow_naked_reg = saved_naked_reg;
11459
11460 if (exp->X_op == O_register && exp->X_add_number >= 0)
11461 {
11462 if ((addressT) exp->X_add_number < i386_regtab_size)
11463 {
11464 exp->X_op = O_constant;
11465 exp->X_add_number = i386_regtab[exp->X_add_number]
11466 .dw2_regnum[flag_code >> 1];
11467 }
11468 else
11469 exp->X_op = O_illegal;
11470 }
11471 }
11472
11473 void
11474 tc_x86_frame_initial_instructions (void)
11475 {
11476 static unsigned int sp_regno[2];
11477
11478 if (!sp_regno[flag_code >> 1])
11479 {
11480 char *saved_input = input_line_pointer;
11481 char sp[][4] = {"esp", "rsp"};
11482 expressionS exp;
11483
11484 input_line_pointer = sp[flag_code >> 1];
11485 tc_x86_parse_to_dw2regnum (&exp);
11486 gas_assert (exp.X_op == O_constant);
11487 sp_regno[flag_code >> 1] = exp.X_add_number;
11488 input_line_pointer = saved_input;
11489 }
11490
11491 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11492 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11493 }
11494
11495 int
11496 x86_dwarf2_addr_size (void)
11497 {
11498 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11499 if (x86_elf_abi == X86_64_X32_ABI)
11500 return 4;
11501 #endif
11502 return bfd_arch_bits_per_address (stdoutput) / 8;
11503 }
11504
11505 int
11506 i386_elf_section_type (const char *str, size_t len)
11507 {
11508 if (flag_code == CODE_64BIT
11509 && len == sizeof ("unwind") - 1
11510 && strncmp (str, "unwind", 6) == 0)
11511 return SHT_X86_64_UNWIND;
11512
11513 return -1;
11514 }
11515
11516 #ifdef TE_SOLARIS
11517 void
11518 i386_solaris_fix_up_eh_frame (segT sec)
11519 {
11520 if (flag_code == CODE_64BIT)
11521 elf_section_type (sec) = SHT_X86_64_UNWIND;
11522 }
11523 #endif
11524
11525 #ifdef TE_PE
11526 void
11527 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11528 {
11529 expressionS exp;
11530
11531 exp.X_op = O_secrel;
11532 exp.X_add_symbol = symbol;
11533 exp.X_add_number = 0;
11534 emit_expr (&exp, size);
11535 }
11536 #endif
11537
11538 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11539 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11540
11541 bfd_vma
11542 x86_64_section_letter (int letter, const char **ptr_msg)
11543 {
11544 if (flag_code == CODE_64BIT)
11545 {
11546 if (letter == 'l')
11547 return SHF_X86_64_LARGE;
11548
11549 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11550 }
11551 else
11552 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11553 return -1;
11554 }
11555
11556 bfd_vma
11557 x86_64_section_word (char *str, size_t len)
11558 {
11559 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11560 return SHF_X86_64_LARGE;
11561
11562 return -1;
11563 }
11564
11565 static void
11566 handle_large_common (int small ATTRIBUTE_UNUSED)
11567 {
11568 if (flag_code != CODE_64BIT)
11569 {
11570 s_comm_internal (0, elf_common_parse);
11571 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11572 }
11573 else
11574 {
11575 static segT lbss_section;
11576 asection *saved_com_section_ptr = elf_com_section_ptr;
11577 asection *saved_bss_section = bss_section;
11578
11579 if (lbss_section == NULL)
11580 {
11581 flagword applicable;
11582 segT seg = now_seg;
11583 subsegT subseg = now_subseg;
11584
11585 /* The .lbss section is for local .largecomm symbols. */
11586 lbss_section = subseg_new (".lbss", 0);
11587 applicable = bfd_applicable_section_flags (stdoutput);
11588 bfd_set_section_flags (stdoutput, lbss_section,
11589 applicable & SEC_ALLOC);
11590 seg_info (lbss_section)->bss = 1;
11591
11592 subseg_set (seg, subseg);
11593 }
11594
11595 elf_com_section_ptr = &_bfd_elf_large_com_section;
11596 bss_section = lbss_section;
11597
11598 s_comm_internal (0, elf_common_parse);
11599
11600 elf_com_section_ptr = saved_com_section_ptr;
11601 bss_section = saved_bss_section;
11602 }
11603 }
11604 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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