1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
136 unsigned int negated
; /* turn off indicated flags. */
140 static void update_code_flag (int, int);
141 static void set_code_flag (int);
142 static void set_16bit_gcc_code_flag (int);
143 static void set_intel_syntax (int);
144 static void set_intel_mnemonic (int);
145 static void set_allow_index_reg (int);
146 static void set_check (int);
147 static void set_cpu_arch (int);
149 static void pe_directive_secrel (int);
151 static void signed_cons (int);
152 static char *output_invalid (int c
);
153 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
155 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
157 static int i386_att_operand (char *);
158 static int i386_intel_operand (char *, int);
159 static int i386_intel_simplify (expressionS
*);
160 static int i386_intel_parse_name (const char *, expressionS
*);
161 static const reg_entry
*parse_register (char *, char **);
162 static char *parse_insn (char *, char *);
163 static char *parse_operands (char *, const char *);
164 static void swap_operands (void);
165 static void swap_2_operands (int, int);
166 static void optimize_imm (void);
167 static void optimize_disp (void);
168 static const insn_template
*match_template (void);
169 static int check_string (void);
170 static int process_suffix (void);
171 static int check_byte_reg (void);
172 static int check_long_reg (void);
173 static int check_qword_reg (void);
174 static int check_word_reg (void);
175 static int finalize_imm (void);
176 static int process_operands (void);
177 static const seg_entry
*build_modrm_byte (void);
178 static void output_insn (void);
179 static void output_imm (fragS
*, offsetT
);
180 static void output_disp (fragS
*, offsetT
);
182 static void s_bss (int);
184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
188 static const char *default_arch
= DEFAULT_ARCH
;
190 /* This struct describes rounding control and SAE in the instruction. */
204 static struct RC_Operation rc_op
;
206 /* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209 struct Mask_Operation
211 const reg_entry
*mask
;
212 unsigned int zeroing
;
213 /* The operand where this operation is associated. */
217 static struct Mask_Operation mask_op
;
219 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
221 struct Broadcast_Operation
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
226 /* Index of broadcasted operand. */
230 static struct Broadcast_Operation broadcast_op
;
235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes
[4];
238 /* Destination or source register specifier. */
239 const reg_entry
*register_specifier
;
242 /* 'md_assemble ()' gathers together information and puts it into a
249 const reg_entry
*regs
;
254 operand_size_mismatch
,
255 operand_type_mismatch
,
256 register_type_mismatch
,
257 number_of_operands_mismatch
,
258 invalid_instruction_suffix
,
261 unsupported_with_intel_mnemonic
,
264 invalid_vsib_address
,
265 invalid_vector_register_set
,
266 unsupported_vector_index_register
,
267 unsupported_broadcast
,
268 broadcast_not_on_src_operand
,
271 mask_not_on_destination
,
274 rc_sae_operand_not_last_imm
,
275 invalid_register_operand
,
281 /* TM holds the template for the insn were currently assembling. */
284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
288 /* OPERANDS gives the number of given operands. */
289 unsigned int operands
;
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
294 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
296 /* TYPES [i] is the type (see above #defines) which tells us how to
297 use OP[i] for the corresponding operand. */
298 i386_operand_type types
[MAX_OPERANDS
];
300 /* Displacement expression, immediate expression, or register for each
302 union i386_op op
[MAX_OPERANDS
];
304 /* Flags for operands. */
305 unsigned int flags
[MAX_OPERANDS
];
306 #define Operand_PCrel 1
308 /* Relocation type for operand */
309 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry
*base_reg
;
314 const reg_entry
*index_reg
;
315 unsigned int log2_scale_factor
;
317 /* SEG gives the seg_entries of this insn. They are zero unless
318 explicit segment overrides are given. */
319 const seg_entry
*seg
[2];
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes
;
324 unsigned char prefix
[MAX_PREFIXES
];
326 /* RM and SIB are the modrm byte and the sib byte where the
327 addressing modes of this insn are encoded. */
334 /* Masking attributes. */
335 struct Mask_Operation
*mask
;
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation
*rounding
;
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation
*broadcast
;
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift
;
346 /* Swap operand in encoding. */
347 unsigned int swap_operand
;
349 /* Prefer 8bit or 32bit displacement in encoding. */
352 disp_encoding_default
= 0,
358 const char *rep_prefix
;
361 const char *hle_prefix
;
363 /* Have BND prefix. */
364 const char *bnd_prefix
;
366 /* Need VREX to support upper 16 registers. */
370 enum i386_error error
;
373 typedef struct _i386_insn i386_insn
;
375 /* Link RC type with corresponding string, that'll be looked for in
384 static const struct RC_name RC_NamesTable
[] =
386 { rne
, STRING_COMMA_LEN ("rn-sae") },
387 { rd
, STRING_COMMA_LEN ("rd-sae") },
388 { ru
, STRING_COMMA_LEN ("ru-sae") },
389 { rz
, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly
, STRING_COMMA_LEN ("sae") },
393 /* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
395 const char extra_symbol_chars
[] = "*%-([{"
404 #if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
406 && !defined (TE_GNU) \
407 && !defined (TE_LINUX) \
408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
410 && !defined (TE_FreeBSD) \
411 && !defined (TE_DragonFly) \
412 && !defined (TE_NetBSD)))
413 /* This array holds the chars that always start a comment. If the
414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416 const char *i386_comment_chars
= "#/";
417 #define SVR4_COMMENT_CHARS 1
418 #define PREFIX_SEPARATOR '\\'
421 const char *i386_comment_chars
= "#";
422 #define PREFIX_SEPARATOR '/'
425 /* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
429 first line of the input file. This is because the compiler outputs
430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
432 '/' isn't otherwise defined. */
433 const char line_comment_chars
[] = "#/";
435 const char line_separator_chars
[] = ";";
437 /* Chars that can be used to separate mant from exp in floating point
439 const char EXP_CHARS
[] = "eE";
441 /* Chars that mean this number is a floating point constant
444 const char FLT_CHARS
[] = "fFdDxX";
446 /* Tables for lexical analysis. */
447 static char mnemonic_chars
[256];
448 static char register_chars
[256];
449 static char operand_chars
[256];
450 static char identifier_chars
[256];
451 static char digit_chars
[256];
453 /* Lexical macros. */
454 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455 #define is_operand_char(x) (operand_chars[(unsigned char) x])
456 #define is_register_char(x) (register_chars[(unsigned char) x])
457 #define is_space_char(x) ((x) == ' ')
458 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459 #define is_digit_char(x) (digit_chars[(unsigned char) x])
461 /* All non-digit non-letter characters that may occur in an operand. */
462 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
464 /* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
467 assembler instruction). */
468 static char save_stack
[32];
469 static char *save_stack_p
;
470 #define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472 #define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
475 /* The instruction we're assembling. */
478 /* Possible templates for current insn. */
479 static const templates
*current_templates
;
481 /* Per instruction expressionS buffers: max displacements & immediates. */
482 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
483 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
485 /* Current operand we are working on. */
486 static int this_operand
= -1;
488 /* We support four different modes. FLAG_CODE variable is used to distinguish
496 static enum flag_code flag_code
;
497 static unsigned int object_64bit
;
498 static unsigned int disallow_64bit_reloc
;
499 static int use_rela_relocations
= 0;
501 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
505 /* The ELF ABI to use. */
513 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
516 #if defined (TE_PE) || defined (TE_PEP)
517 /* Use big object file format. */
518 static int use_big_obj
= 0;
521 /* 1 for intel syntax,
523 static int intel_syntax
= 0;
525 /* 1 for intel mnemonic,
526 0 if att mnemonic. */
527 static int intel_mnemonic
= !SYSV386_COMPAT
;
529 /* 1 if support old (<= 2.8.1) versions of gcc. */
530 static int old_gcc
= OLDGCC_COMPAT
;
532 /* 1 if pseudo registers are permitted. */
533 static int allow_pseudo_reg
= 0;
535 /* 1 if register prefix % not required. */
536 static int allow_naked_reg
= 0;
538 /* 1 if the assembler should add BND prefix for all control-tranferring
539 instructions supporting it, even if this prefix wasn't specified
541 static int add_bnd_prefix
= 0;
543 /* 1 if pseudo index register, eiz/riz, is allowed . */
544 static int allow_index_reg
= 0;
546 /* 1 if the assembler should ignore LOCK prefix, even if it was
547 specified explicitly. */
548 static int omit_lock_prefix
= 0;
550 static enum check_kind
556 sse_check
, operand_check
= check_warning
;
558 /* Register prefix used for error message. */
559 static const char *register_prefix
= "%";
561 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
562 leave, push, and pop instructions so that gcc has the same stack
563 frame as in 32 bit mode. */
564 static char stackop_size
= '\0';
566 /* Non-zero to optimize code alignment. */
567 int optimize_align_code
= 1;
569 /* Non-zero to quieten some warnings. */
570 static int quiet_warnings
= 0;
573 static const char *cpu_arch_name
= NULL
;
574 static char *cpu_sub_arch_name
= NULL
;
576 /* CPU feature flags. */
577 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
579 /* If we have selected a cpu we are generating instructions for. */
580 static int cpu_arch_tune_set
= 0;
582 /* Cpu we are generating instructions for. */
583 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
585 /* CPU feature flags of cpu we are generating instructions for. */
586 static i386_cpu_flags cpu_arch_tune_flags
;
588 /* CPU instruction set architecture used. */
589 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
591 /* CPU feature flags of instruction set architecture used. */
592 i386_cpu_flags cpu_arch_isa_flags
;
594 /* If set, conditional jumps are not automatically promoted to handle
595 larger than a byte offset. */
596 static unsigned int no_cond_jump_promotion
= 0;
598 /* Encode SSE instructions with VEX prefix. */
599 static unsigned int sse2avx
;
601 /* Encode scalar AVX instructions with specific vector length. */
608 /* Encode scalar EVEX LIG instructions with specific vector length. */
616 /* Encode EVEX WIG instructions with specific evex.w. */
623 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
624 static symbolS
*GOT_symbol
;
626 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
627 unsigned int x86_dwarf2_return_column
;
629 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
630 int x86_cie_data_alignment
;
632 /* Interface to relax_segment.
633 There are 3 major relax states for 386 jump insns because the
634 different types of jumps add different sizes to frags when we're
635 figuring out what sort of jump to choose to reach a given label. */
638 #define UNCOND_JUMP 0
640 #define COND_JUMP86 2
645 #define SMALL16 (SMALL | CODE16)
647 #define BIG16 (BIG | CODE16)
651 #define INLINE __inline__
657 #define ENCODE_RELAX_STATE(type, size) \
658 ((relax_substateT) (((type) << 2) | (size)))
659 #define TYPE_FROM_RELAX_STATE(s) \
661 #define DISP_SIZE_FROM_RELAX_STATE(s) \
662 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
664 /* This table is used by relax_frag to promote short jumps to long
665 ones where necessary. SMALL (short) jumps may be promoted to BIG
666 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
667 don't allow a short jump in a 32 bit code segment to be promoted to
668 a 16 bit offset jump because it's slower (requires data size
669 prefix), and doesn't work, unless the destination is in the bottom
670 64k of the code segment (The top 16 bits of eip are zeroed). */
672 const relax_typeS md_relax_table
[] =
675 1) most positive reach of this state,
676 2) most negative reach of this state,
677 3) how many bytes this mode will have in the variable part of the frag
678 4) which index into the table to try if we can't fit into this one. */
680 /* UNCOND_JUMP states. */
681 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
682 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
683 /* dword jmp adds 4 bytes to frag:
684 0 extra opcode bytes, 4 displacement bytes. */
686 /* word jmp adds 2 byte2 to frag:
687 0 extra opcode bytes, 2 displacement bytes. */
690 /* COND_JUMP states. */
691 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
692 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
693 /* dword conditionals adds 5 bytes to frag:
694 1 extra opcode byte, 4 displacement bytes. */
696 /* word conditionals add 3 bytes to frag:
697 1 extra opcode byte, 2 displacement bytes. */
700 /* COND_JUMP86 states. */
701 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
702 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
703 /* dword conditionals adds 5 bytes to frag:
704 1 extra opcode byte, 4 displacement bytes. */
706 /* word conditionals add 4 bytes to frag:
707 1 displacement byte and a 3 byte long branch insn. */
711 static const arch_entry cpu_arch
[] =
713 /* Do not replace the first two entries - i386_target_format()
714 relies on them being there in this order. */
715 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
716 CPU_GENERIC32_FLAGS
, 0, 0 },
717 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
718 CPU_GENERIC64_FLAGS
, 0, 0 },
719 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
720 CPU_NONE_FLAGS
, 0, 0 },
721 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
722 CPU_I186_FLAGS
, 0, 0 },
723 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
724 CPU_I286_FLAGS
, 0, 0 },
725 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
726 CPU_I386_FLAGS
, 0, 0 },
727 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
728 CPU_I486_FLAGS
, 0, 0 },
729 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
730 CPU_I586_FLAGS
, 0, 0 },
731 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
732 CPU_I686_FLAGS
, 0, 0 },
733 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
734 CPU_I586_FLAGS
, 0, 0 },
735 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
736 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
737 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
738 CPU_P2_FLAGS
, 0, 0 },
739 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
740 CPU_P3_FLAGS
, 0, 0 },
741 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
742 CPU_P4_FLAGS
, 0, 0 },
743 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
744 CPU_CORE_FLAGS
, 0, 0 },
745 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
746 CPU_NOCONA_FLAGS
, 0, 0 },
747 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
748 CPU_CORE_FLAGS
, 1, 0 },
749 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
750 CPU_CORE_FLAGS
, 0, 0 },
751 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
752 CPU_CORE2_FLAGS
, 1, 0 },
753 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
754 CPU_CORE2_FLAGS
, 0, 0 },
755 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
756 CPU_COREI7_FLAGS
, 0, 0 },
757 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
758 CPU_L1OM_FLAGS
, 0, 0 },
759 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
760 CPU_K1OM_FLAGS
, 0, 0 },
761 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
762 CPU_K6_FLAGS
, 0, 0 },
763 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
764 CPU_K6_2_FLAGS
, 0, 0 },
765 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
766 CPU_ATHLON_FLAGS
, 0, 0 },
767 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
768 CPU_K8_FLAGS
, 1, 0 },
769 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
770 CPU_K8_FLAGS
, 0, 0 },
771 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
772 CPU_K8_FLAGS
, 0, 0 },
773 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
774 CPU_AMDFAM10_FLAGS
, 0, 0 },
775 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
776 CPU_BDVER1_FLAGS
, 0, 0 },
777 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
778 CPU_BDVER2_FLAGS
, 0, 0 },
779 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
780 CPU_BDVER3_FLAGS
, 0, 0 },
781 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
782 CPU_BDVER4_FLAGS
, 0, 0 },
783 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
784 CPU_BTVER1_FLAGS
, 0, 0 },
785 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
786 CPU_BTVER2_FLAGS
, 0, 0 },
787 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
788 CPU_8087_FLAGS
, 0, 0 },
789 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
790 CPU_287_FLAGS
, 0, 0 },
791 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
792 CPU_387_FLAGS
, 0, 0 },
793 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
794 CPU_ANY87_FLAGS
, 0, 1 },
795 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
796 CPU_MMX_FLAGS
, 0, 0 },
797 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
798 CPU_3DNOWA_FLAGS
, 0, 1 },
799 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
800 CPU_SSE_FLAGS
, 0, 0 },
801 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
802 CPU_SSE2_FLAGS
, 0, 0 },
803 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
804 CPU_SSE3_FLAGS
, 0, 0 },
805 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
806 CPU_SSSE3_FLAGS
, 0, 0 },
807 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
808 CPU_SSE4_1_FLAGS
, 0, 0 },
809 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
810 CPU_SSE4_2_FLAGS
, 0, 0 },
811 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
812 CPU_SSE4_2_FLAGS
, 0, 0 },
813 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
814 CPU_ANY_SSE_FLAGS
, 0, 1 },
815 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
816 CPU_AVX_FLAGS
, 0, 0 },
817 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
818 CPU_AVX2_FLAGS
, 0, 0 },
819 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
820 CPU_AVX512F_FLAGS
, 0, 0 },
821 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
822 CPU_AVX512CD_FLAGS
, 0, 0 },
823 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
824 CPU_AVX512ER_FLAGS
, 0, 0 },
825 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
826 CPU_AVX512PF_FLAGS
, 0, 0 },
827 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
828 CPU_ANY_AVX_FLAGS
, 0, 1 },
829 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
830 CPU_VMX_FLAGS
, 0, 0 },
831 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
832 CPU_VMFUNC_FLAGS
, 0, 0 },
833 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
834 CPU_SMX_FLAGS
, 0, 0 },
835 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
836 CPU_XSAVE_FLAGS
, 0, 0 },
837 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
838 CPU_XSAVEOPT_FLAGS
, 0, 0 },
839 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
840 CPU_AES_FLAGS
, 0, 0 },
841 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
842 CPU_PCLMUL_FLAGS
, 0, 0 },
843 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
844 CPU_PCLMUL_FLAGS
, 1, 0 },
845 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
846 CPU_FSGSBASE_FLAGS
, 0, 0 },
847 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
848 CPU_RDRND_FLAGS
, 0, 0 },
849 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
850 CPU_F16C_FLAGS
, 0, 0 },
851 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
852 CPU_BMI2_FLAGS
, 0, 0 },
853 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
854 CPU_FMA_FLAGS
, 0, 0 },
855 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
856 CPU_FMA4_FLAGS
, 0, 0 },
857 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
858 CPU_XOP_FLAGS
, 0, 0 },
859 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
860 CPU_LWP_FLAGS
, 0, 0 },
861 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
862 CPU_MOVBE_FLAGS
, 0, 0 },
863 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
864 CPU_CX16_FLAGS
, 0, 0 },
865 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
866 CPU_EPT_FLAGS
, 0, 0 },
867 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
868 CPU_LZCNT_FLAGS
, 0, 0 },
869 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
870 CPU_HLE_FLAGS
, 0, 0 },
871 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
872 CPU_RTM_FLAGS
, 0, 0 },
873 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
874 CPU_INVPCID_FLAGS
, 0, 0 },
875 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
876 CPU_CLFLUSH_FLAGS
, 0, 0 },
877 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
878 CPU_NOP_FLAGS
, 0, 0 },
879 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
880 CPU_SYSCALL_FLAGS
, 0, 0 },
881 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
882 CPU_RDTSCP_FLAGS
, 0, 0 },
883 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
884 CPU_3DNOW_FLAGS
, 0, 0 },
885 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
886 CPU_3DNOWA_FLAGS
, 0, 0 },
887 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
888 CPU_PADLOCK_FLAGS
, 0, 0 },
889 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
890 CPU_SVME_FLAGS
, 1, 0 },
891 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
892 CPU_SVME_FLAGS
, 0, 0 },
893 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
894 CPU_SSE4A_FLAGS
, 0, 0 },
895 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
896 CPU_ABM_FLAGS
, 0, 0 },
897 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
898 CPU_BMI_FLAGS
, 0, 0 },
899 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
900 CPU_TBM_FLAGS
, 0, 0 },
901 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
902 CPU_ADX_FLAGS
, 0, 0 },
903 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
904 CPU_RDSEED_FLAGS
, 0, 0 },
905 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
906 CPU_PRFCHW_FLAGS
, 0, 0 },
907 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
908 CPU_SMAP_FLAGS
, 0, 0 },
909 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
910 CPU_MPX_FLAGS
, 0, 0 },
911 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
912 CPU_SHA_FLAGS
, 0, 0 },
913 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
914 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
915 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
916 CPU_XSAVEC_FLAGS
, 0, 0 },
917 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
918 CPU_XSAVES_FLAGS
, 0, 0 },
919 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
920 CPU_PREFETCHWT1_FLAGS
, 0, 0 },
921 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
922 CPU_SE1_FLAGS
, 0, 0 },
923 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
924 CPU_AVX512DQ_FLAGS
, 0, 0 },
925 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
926 CPU_AVX512BW_FLAGS
, 0, 0 },
927 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
928 CPU_AVX512VL_FLAGS
, 0, 0 },
932 /* Like s_lcomm_internal in gas/read.c but the alignment string
933 is allowed to be optional. */
936 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
943 && *input_line_pointer
== ',')
945 align
= parse_align (needs_align
- 1);
947 if (align
== (addressT
) -1)
962 bss_alloc (symbolP
, size
, align
);
967 pe_lcomm (int needs_align
)
969 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
973 const pseudo_typeS md_pseudo_table
[] =
975 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
976 {"align", s_align_bytes
, 0},
978 {"align", s_align_ptwo
, 0},
980 {"arch", set_cpu_arch
, 0},
984 {"lcomm", pe_lcomm
, 1},
986 {"ffloat", float_cons
, 'f'},
987 {"dfloat", float_cons
, 'd'},
988 {"tfloat", float_cons
, 'x'},
990 {"slong", signed_cons
, 4},
991 {"noopt", s_ignore
, 0},
992 {"optim", s_ignore
, 0},
993 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
994 {"code16", set_code_flag
, CODE_16BIT
},
995 {"code32", set_code_flag
, CODE_32BIT
},
996 {"code64", set_code_flag
, CODE_64BIT
},
997 {"intel_syntax", set_intel_syntax
, 1},
998 {"att_syntax", set_intel_syntax
, 0},
999 {"intel_mnemonic", set_intel_mnemonic
, 1},
1000 {"att_mnemonic", set_intel_mnemonic
, 0},
1001 {"allow_index_reg", set_allow_index_reg
, 1},
1002 {"disallow_index_reg", set_allow_index_reg
, 0},
1003 {"sse_check", set_check
, 0},
1004 {"operand_check", set_check
, 1},
1005 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1006 {"largecomm", handle_large_common
, 0},
1008 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1009 {"loc", dwarf2_directive_loc
, 0},
1010 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1013 {"secrel32", pe_directive_secrel
, 0},
1018 /* For interface with expression (). */
1019 extern char *input_line_pointer
;
1021 /* Hash table for instruction mnemonic lookup. */
1022 static struct hash_control
*op_hash
;
1024 /* Hash table for register lookup. */
1025 static struct hash_control
*reg_hash
;
1028 i386_align_code (fragS
*fragP
, int count
)
1030 /* Various efficient no-op patterns for aligning code labels.
1031 Note: Don't try to assemble the instructions in the comments.
1032 0L and 0w are not legal. */
1033 static const char f32_1
[] =
1035 static const char f32_2
[] =
1036 {0x66,0x90}; /* xchg %ax,%ax */
1037 static const char f32_3
[] =
1038 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1039 static const char f32_4
[] =
1040 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1041 static const char f32_5
[] =
1043 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1044 static const char f32_6
[] =
1045 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1046 static const char f32_7
[] =
1047 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1048 static const char f32_8
[] =
1050 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1051 static const char f32_9
[] =
1052 {0x89,0xf6, /* movl %esi,%esi */
1053 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1054 static const char f32_10
[] =
1055 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1056 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1057 static const char f32_11
[] =
1058 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1059 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1060 static const char f32_12
[] =
1061 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1062 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1063 static const char f32_13
[] =
1064 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1065 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1066 static const char f32_14
[] =
1067 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1068 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1069 static const char f16_3
[] =
1070 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1071 static const char f16_4
[] =
1072 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1073 static const char f16_5
[] =
1075 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1076 static const char f16_6
[] =
1077 {0x89,0xf6, /* mov %si,%si */
1078 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1079 static const char f16_7
[] =
1080 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1081 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1082 static const char f16_8
[] =
1083 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1084 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1085 static const char jump_31
[] =
1086 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1087 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1088 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1089 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1090 static const char *const f32_patt
[] = {
1091 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1092 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1094 static const char *const f16_patt
[] = {
1095 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1097 /* nopl (%[re]ax) */
1098 static const char alt_3
[] =
1100 /* nopl 0(%[re]ax) */
1101 static const char alt_4
[] =
1102 {0x0f,0x1f,0x40,0x00};
1103 /* nopl 0(%[re]ax,%[re]ax,1) */
1104 static const char alt_5
[] =
1105 {0x0f,0x1f,0x44,0x00,0x00};
1106 /* nopw 0(%[re]ax,%[re]ax,1) */
1107 static const char alt_6
[] =
1108 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1109 /* nopl 0L(%[re]ax) */
1110 static const char alt_7
[] =
1111 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1112 /* nopl 0L(%[re]ax,%[re]ax,1) */
1113 static const char alt_8
[] =
1114 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1115 /* nopw 0L(%[re]ax,%[re]ax,1) */
1116 static const char alt_9
[] =
1117 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1118 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1119 static const char alt_10
[] =
1120 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1122 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1123 static const char alt_long_11
[] =
1125 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1128 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1129 static const char alt_long_12
[] =
1132 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1136 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1137 static const char alt_long_13
[] =
1141 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1146 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1147 static const char alt_long_14
[] =
1152 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1158 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1159 static const char alt_long_15
[] =
1165 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1166 /* nopl 0(%[re]ax,%[re]ax,1)
1167 nopw 0(%[re]ax,%[re]ax,1) */
1168 static const char alt_short_11
[] =
1169 {0x0f,0x1f,0x44,0x00,0x00,
1170 0x66,0x0f,0x1f,0x44,0x00,0x00};
1171 /* nopw 0(%[re]ax,%[re]ax,1)
1172 nopw 0(%[re]ax,%[re]ax,1) */
1173 static const char alt_short_12
[] =
1174 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1175 0x66,0x0f,0x1f,0x44,0x00,0x00};
1176 /* nopw 0(%[re]ax,%[re]ax,1)
1178 static const char alt_short_13
[] =
1179 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1180 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1183 static const char alt_short_14
[] =
1184 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1185 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1187 nopl 0L(%[re]ax,%[re]ax,1) */
1188 static const char alt_short_15
[] =
1189 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1190 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1191 static const char *const alt_short_patt
[] = {
1192 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1193 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1194 alt_short_14
, alt_short_15
1196 static const char *const alt_long_patt
[] = {
1197 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1198 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1199 alt_long_14
, alt_long_15
1202 /* Only align for at least a positive non-zero boundary. */
1203 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1206 /* We need to decide which NOP sequence to use for 32bit and
1207 64bit. When -mtune= is used:
1209 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1210 PROCESSOR_GENERIC32, f32_patt will be used.
1211 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1212 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1213 PROCESSOR_GENERIC64, alt_long_patt will be used.
1214 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1215 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1218 When -mtune= isn't used, alt_long_patt will be used if
1219 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1222 When -march= or .arch is used, we can't use anything beyond
1223 cpu_arch_isa_flags. */
1225 if (flag_code
== CODE_16BIT
)
1229 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1231 /* Adjust jump offset. */
1232 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1235 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1236 f16_patt
[count
- 1], count
);
1240 const char *const *patt
= NULL
;
1242 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1244 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1245 switch (cpu_arch_tune
)
1247 case PROCESSOR_UNKNOWN
:
1248 /* We use cpu_arch_isa_flags to check if we SHOULD
1249 optimize with nops. */
1250 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1251 patt
= alt_long_patt
;
1255 case PROCESSOR_PENTIUM4
:
1256 case PROCESSOR_NOCONA
:
1257 case PROCESSOR_CORE
:
1258 case PROCESSOR_CORE2
:
1259 case PROCESSOR_COREI7
:
1260 case PROCESSOR_L1OM
:
1261 case PROCESSOR_K1OM
:
1262 case PROCESSOR_GENERIC64
:
1263 patt
= alt_long_patt
;
1266 case PROCESSOR_ATHLON
:
1268 case PROCESSOR_AMDFAM10
:
1271 patt
= alt_short_patt
;
1273 case PROCESSOR_I386
:
1274 case PROCESSOR_I486
:
1275 case PROCESSOR_PENTIUM
:
1276 case PROCESSOR_PENTIUMPRO
:
1277 case PROCESSOR_GENERIC32
:
1284 switch (fragP
->tc_frag_data
.tune
)
1286 case PROCESSOR_UNKNOWN
:
1287 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1288 PROCESSOR_UNKNOWN. */
1292 case PROCESSOR_I386
:
1293 case PROCESSOR_I486
:
1294 case PROCESSOR_PENTIUM
:
1296 case PROCESSOR_ATHLON
:
1298 case PROCESSOR_AMDFAM10
:
1301 case PROCESSOR_GENERIC32
:
1302 /* We use cpu_arch_isa_flags to check if we CAN optimize
1304 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1305 patt
= alt_short_patt
;
1309 case PROCESSOR_PENTIUMPRO
:
1310 case PROCESSOR_PENTIUM4
:
1311 case PROCESSOR_NOCONA
:
1312 case PROCESSOR_CORE
:
1313 case PROCESSOR_CORE2
:
1314 case PROCESSOR_COREI7
:
1315 case PROCESSOR_L1OM
:
1316 case PROCESSOR_K1OM
:
1317 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1318 patt
= alt_long_patt
;
1322 case PROCESSOR_GENERIC64
:
1323 patt
= alt_long_patt
;
1328 if (patt
== f32_patt
)
1330 /* If the padding is less than 15 bytes, we use the normal
1331 ones. Otherwise, we use a jump instruction and adjust
1335 /* For 64bit, the limit is 3 bytes. */
1336 if (flag_code
== CODE_64BIT
1337 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1342 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1343 patt
[count
- 1], count
);
1346 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1348 /* Adjust jump offset. */
1349 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1354 /* Maximum length of an instruction is 15 byte. If the
1355 padding is greater than 15 bytes and we don't use jump,
1356 we have to break it into smaller pieces. */
1357 int padding
= count
;
1358 while (padding
> 15)
1361 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1366 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1367 patt
[padding
- 1], padding
);
1370 fragP
->fr_var
= count
;
1374 operand_type_all_zero (const union i386_operand_type
*x
)
1376 switch (ARRAY_SIZE(x
->array
))
1385 return !x
->array
[0];
1392 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1394 switch (ARRAY_SIZE(x
->array
))
1409 operand_type_equal (const union i386_operand_type
*x
,
1410 const union i386_operand_type
*y
)
1412 switch (ARRAY_SIZE(x
->array
))
1415 if (x
->array
[2] != y
->array
[2])
1418 if (x
->array
[1] != y
->array
[1])
1421 return x
->array
[0] == y
->array
[0];
1429 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1431 switch (ARRAY_SIZE(x
->array
))
1440 return !x
->array
[0];
1447 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1449 switch (ARRAY_SIZE(x
->array
))
1464 cpu_flags_equal (const union i386_cpu_flags
*x
,
1465 const union i386_cpu_flags
*y
)
1467 switch (ARRAY_SIZE(x
->array
))
1470 if (x
->array
[2] != y
->array
[2])
1473 if (x
->array
[1] != y
->array
[1])
1476 return x
->array
[0] == y
->array
[0];
1484 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1486 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1487 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1490 static INLINE i386_cpu_flags
1491 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1493 switch (ARRAY_SIZE (x
.array
))
1496 x
.array
[2] &= y
.array
[2];
1498 x
.array
[1] &= y
.array
[1];
1500 x
.array
[0] &= y
.array
[0];
1508 static INLINE i386_cpu_flags
1509 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1511 switch (ARRAY_SIZE (x
.array
))
1514 x
.array
[2] |= y
.array
[2];
1516 x
.array
[1] |= y
.array
[1];
1518 x
.array
[0] |= y
.array
[0];
1526 static INLINE i386_cpu_flags
1527 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1529 switch (ARRAY_SIZE (x
.array
))
1532 x
.array
[2] &= ~y
.array
[2];
1534 x
.array
[1] &= ~y
.array
[1];
1536 x
.array
[0] &= ~y
.array
[0];
1544 #define CPU_FLAGS_ARCH_MATCH 0x1
1545 #define CPU_FLAGS_64BIT_MATCH 0x2
1546 #define CPU_FLAGS_AES_MATCH 0x4
1547 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1548 #define CPU_FLAGS_AVX_MATCH 0x10
1550 #define CPU_FLAGS_32BIT_MATCH \
1551 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1552 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1553 #define CPU_FLAGS_PERFECT_MATCH \
1554 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1556 /* Return CPU flags match bits. */
1559 cpu_flags_match (const insn_template
*t
)
1561 i386_cpu_flags x
= t
->cpu_flags
;
1562 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1564 x
.bitfield
.cpu64
= 0;
1565 x
.bitfield
.cpuno64
= 0;
1567 if (cpu_flags_all_zero (&x
))
1569 /* This instruction is available on all archs. */
1570 match
|= CPU_FLAGS_32BIT_MATCH
;
1574 /* This instruction is available only on some archs. */
1575 i386_cpu_flags cpu
= cpu_arch_flags
;
1577 cpu
.bitfield
.cpu64
= 0;
1578 cpu
.bitfield
.cpuno64
= 0;
1579 cpu
= cpu_flags_and (x
, cpu
);
1580 if (!cpu_flags_all_zero (&cpu
))
1582 if (x
.bitfield
.cpuavx
)
1584 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1585 if (cpu
.bitfield
.cpuavx
)
1587 /* Check SSE2AVX. */
1588 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1590 match
|= (CPU_FLAGS_ARCH_MATCH
1591 | CPU_FLAGS_AVX_MATCH
);
1593 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1594 match
|= CPU_FLAGS_AES_MATCH
;
1596 if (!x
.bitfield
.cpupclmul
1597 || cpu
.bitfield
.cpupclmul
)
1598 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1602 match
|= CPU_FLAGS_ARCH_MATCH
;
1605 match
|= CPU_FLAGS_32BIT_MATCH
;
1611 static INLINE i386_operand_type
1612 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1614 switch (ARRAY_SIZE (x
.array
))
1617 x
.array
[2] &= y
.array
[2];
1619 x
.array
[1] &= y
.array
[1];
1621 x
.array
[0] &= y
.array
[0];
1629 static INLINE i386_operand_type
1630 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1632 switch (ARRAY_SIZE (x
.array
))
1635 x
.array
[2] |= y
.array
[2];
1637 x
.array
[1] |= y
.array
[1];
1639 x
.array
[0] |= y
.array
[0];
1647 static INLINE i386_operand_type
1648 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1650 switch (ARRAY_SIZE (x
.array
))
1653 x
.array
[2] ^= y
.array
[2];
1655 x
.array
[1] ^= y
.array
[1];
1657 x
.array
[0] ^= y
.array
[0];
1665 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1666 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1667 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1668 static const i386_operand_type inoutportreg
1669 = OPERAND_TYPE_INOUTPORTREG
;
1670 static const i386_operand_type reg16_inoutportreg
1671 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1672 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1673 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1674 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1675 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1676 static const i386_operand_type anydisp
1677 = OPERAND_TYPE_ANYDISP
;
1678 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1679 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1680 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1681 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1682 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1683 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1684 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1685 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1686 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1687 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1688 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1689 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1690 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1691 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1702 operand_type_check (i386_operand_type t
, enum operand_type c
)
1707 return (t
.bitfield
.reg8
1710 || t
.bitfield
.reg64
);
1713 return (t
.bitfield
.imm8
1717 || t
.bitfield
.imm32s
1718 || t
.bitfield
.imm64
);
1721 return (t
.bitfield
.disp8
1722 || t
.bitfield
.disp16
1723 || t
.bitfield
.disp32
1724 || t
.bitfield
.disp32s
1725 || t
.bitfield
.disp64
);
1728 return (t
.bitfield
.disp8
1729 || t
.bitfield
.disp16
1730 || t
.bitfield
.disp32
1731 || t
.bitfield
.disp32s
1732 || t
.bitfield
.disp64
1733 || t
.bitfield
.baseindex
);
1742 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1743 operand J for instruction template T. */
1746 match_reg_size (const insn_template
*t
, unsigned int j
)
1748 return !((i
.types
[j
].bitfield
.byte
1749 && !t
->operand_types
[j
].bitfield
.byte
)
1750 || (i
.types
[j
].bitfield
.word
1751 && !t
->operand_types
[j
].bitfield
.word
)
1752 || (i
.types
[j
].bitfield
.dword
1753 && !t
->operand_types
[j
].bitfield
.dword
)
1754 || (i
.types
[j
].bitfield
.qword
1755 && !t
->operand_types
[j
].bitfield
.qword
));
1758 /* Return 1 if there is no conflict in any size on operand J for
1759 instruction template T. */
1762 match_mem_size (const insn_template
*t
, unsigned int j
)
1764 return (match_reg_size (t
, j
)
1765 && !((i
.types
[j
].bitfield
.unspecified
1766 && !t
->operand_types
[j
].bitfield
.unspecified
)
1767 || (i
.types
[j
].bitfield
.fword
1768 && !t
->operand_types
[j
].bitfield
.fword
)
1769 || (i
.types
[j
].bitfield
.tbyte
1770 && !t
->operand_types
[j
].bitfield
.tbyte
)
1771 || (i
.types
[j
].bitfield
.xmmword
1772 && !t
->operand_types
[j
].bitfield
.xmmword
)
1773 || (i
.types
[j
].bitfield
.ymmword
1774 && !t
->operand_types
[j
].bitfield
.ymmword
)
1775 || (i
.types
[j
].bitfield
.zmmword
1776 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1779 /* Return 1 if there is no size conflict on any operands for
1780 instruction template T. */
1783 operand_size_match (const insn_template
*t
)
1788 /* Don't check jump instructions. */
1789 if (t
->opcode_modifier
.jump
1790 || t
->opcode_modifier
.jumpbyte
1791 || t
->opcode_modifier
.jumpdword
1792 || t
->opcode_modifier
.jumpintersegment
)
1795 /* Check memory and accumulator operand size. */
1796 for (j
= 0; j
< i
.operands
; j
++)
1798 if (t
->operand_types
[j
].bitfield
.anysize
)
1801 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1807 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1816 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1819 i
.error
= operand_size_mismatch
;
1823 /* Check reverse. */
1824 gas_assert (i
.operands
== 2);
1827 for (j
= 0; j
< 2; j
++)
1829 if (t
->operand_types
[j
].bitfield
.acc
1830 && !match_reg_size (t
, j
? 0 : 1))
1833 if (i
.types
[j
].bitfield
.mem
1834 && !match_mem_size (t
, j
? 0 : 1))
1842 operand_type_match (i386_operand_type overlap
,
1843 i386_operand_type given
)
1845 i386_operand_type temp
= overlap
;
1847 temp
.bitfield
.jumpabsolute
= 0;
1848 temp
.bitfield
.unspecified
= 0;
1849 temp
.bitfield
.byte
= 0;
1850 temp
.bitfield
.word
= 0;
1851 temp
.bitfield
.dword
= 0;
1852 temp
.bitfield
.fword
= 0;
1853 temp
.bitfield
.qword
= 0;
1854 temp
.bitfield
.tbyte
= 0;
1855 temp
.bitfield
.xmmword
= 0;
1856 temp
.bitfield
.ymmword
= 0;
1857 temp
.bitfield
.zmmword
= 0;
1858 if (operand_type_all_zero (&temp
))
1861 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1862 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1866 i
.error
= operand_type_mismatch
;
1870 /* If given types g0 and g1 are registers they must be of the same type
1871 unless the expected operand type register overlap is null.
1872 Note that Acc in a template matches every size of reg. */
1875 operand_type_register_match (i386_operand_type m0
,
1876 i386_operand_type g0
,
1877 i386_operand_type t0
,
1878 i386_operand_type m1
,
1879 i386_operand_type g1
,
1880 i386_operand_type t1
)
1882 if (!operand_type_check (g0
, reg
))
1885 if (!operand_type_check (g1
, reg
))
1888 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1889 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1890 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1891 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1894 if (m0
.bitfield
.acc
)
1896 t0
.bitfield
.reg8
= 1;
1897 t0
.bitfield
.reg16
= 1;
1898 t0
.bitfield
.reg32
= 1;
1899 t0
.bitfield
.reg64
= 1;
1902 if (m1
.bitfield
.acc
)
1904 t1
.bitfield
.reg8
= 1;
1905 t1
.bitfield
.reg16
= 1;
1906 t1
.bitfield
.reg32
= 1;
1907 t1
.bitfield
.reg64
= 1;
1910 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1911 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1912 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1913 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1916 i
.error
= register_type_mismatch
;
1921 static INLINE
unsigned int
1922 register_number (const reg_entry
*r
)
1924 unsigned int nr
= r
->reg_num
;
1926 if (r
->reg_flags
& RegRex
)
1932 static INLINE
unsigned int
1933 mode_from_disp_size (i386_operand_type t
)
1935 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1937 else if (t
.bitfield
.disp16
1938 || t
.bitfield
.disp32
1939 || t
.bitfield
.disp32s
)
1946 fits_in_signed_byte (offsetT num
)
1948 return (num
>= -128) && (num
<= 127);
1952 fits_in_unsigned_byte (offsetT num
)
1954 return (num
& 0xff) == num
;
1958 fits_in_unsigned_word (offsetT num
)
1960 return (num
& 0xffff) == num
;
1964 fits_in_signed_word (offsetT num
)
1966 return (-32768 <= num
) && (num
<= 32767);
1970 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1975 return (!(((offsetT
) -1 << 31) & num
)
1976 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1978 } /* fits_in_signed_long() */
1981 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1986 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1988 } /* fits_in_unsigned_long() */
1991 fits_in_vec_disp8 (offsetT num
)
1993 int shift
= i
.memshift
;
1999 mask
= (1 << shift
) - 1;
2001 /* Return 0 if NUM isn't properly aligned. */
2005 /* Check if NUM will fit in 8bit after shift. */
2006 return fits_in_signed_byte (num
>> shift
);
2010 fits_in_imm4 (offsetT num
)
2012 return (num
& 0xf) == num
;
2015 static i386_operand_type
2016 smallest_imm_type (offsetT num
)
2018 i386_operand_type t
;
2020 operand_type_set (&t
, 0);
2021 t
.bitfield
.imm64
= 1;
2023 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2025 /* This code is disabled on the 486 because all the Imm1 forms
2026 in the opcode table are slower on the i486. They're the
2027 versions with the implicitly specified single-position
2028 displacement, which has another syntax if you really want to
2030 t
.bitfield
.imm1
= 1;
2031 t
.bitfield
.imm8
= 1;
2032 t
.bitfield
.imm8s
= 1;
2033 t
.bitfield
.imm16
= 1;
2034 t
.bitfield
.imm32
= 1;
2035 t
.bitfield
.imm32s
= 1;
2037 else if (fits_in_signed_byte (num
))
2039 t
.bitfield
.imm8
= 1;
2040 t
.bitfield
.imm8s
= 1;
2041 t
.bitfield
.imm16
= 1;
2042 t
.bitfield
.imm32
= 1;
2043 t
.bitfield
.imm32s
= 1;
2045 else if (fits_in_unsigned_byte (num
))
2047 t
.bitfield
.imm8
= 1;
2048 t
.bitfield
.imm16
= 1;
2049 t
.bitfield
.imm32
= 1;
2050 t
.bitfield
.imm32s
= 1;
2052 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2054 t
.bitfield
.imm16
= 1;
2055 t
.bitfield
.imm32
= 1;
2056 t
.bitfield
.imm32s
= 1;
2058 else if (fits_in_signed_long (num
))
2060 t
.bitfield
.imm32
= 1;
2061 t
.bitfield
.imm32s
= 1;
2063 else if (fits_in_unsigned_long (num
))
2064 t
.bitfield
.imm32
= 1;
2070 offset_in_range (offsetT val
, int size
)
2076 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2077 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2078 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2080 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2086 /* If BFD64, sign extend val for 32bit address mode. */
2087 if (flag_code
!= CODE_64BIT
2088 || i
.prefix
[ADDR_PREFIX
])
2089 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2090 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2093 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2095 char buf1
[40], buf2
[40];
2097 sprint_value (buf1
, val
);
2098 sprint_value (buf2
, val
& mask
);
2099 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2113 a. PREFIX_EXIST if attempting to add a prefix where one from the
2114 same class already exists.
2115 b. PREFIX_LOCK if lock prefix is added.
2116 c. PREFIX_REP if rep/repne prefix is added.
2117 d. PREFIX_OTHER if other prefix is added.
2120 static enum PREFIX_GROUP
2121 add_prefix (unsigned int prefix
)
2123 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2126 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2127 && flag_code
== CODE_64BIT
)
2129 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2130 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2131 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2142 case CS_PREFIX_OPCODE
:
2143 case DS_PREFIX_OPCODE
:
2144 case ES_PREFIX_OPCODE
:
2145 case FS_PREFIX_OPCODE
:
2146 case GS_PREFIX_OPCODE
:
2147 case SS_PREFIX_OPCODE
:
2151 case REPNE_PREFIX_OPCODE
:
2152 case REPE_PREFIX_OPCODE
:
2157 case LOCK_PREFIX_OPCODE
:
2166 case ADDR_PREFIX_OPCODE
:
2170 case DATA_PREFIX_OPCODE
:
2174 if (i
.prefix
[q
] != 0)
2182 i
.prefix
[q
] |= prefix
;
2185 as_bad (_("same type of prefix used twice"));
2191 update_code_flag (int value
, int check
)
2193 PRINTF_LIKE ((*as_error
));
2195 flag_code
= (enum flag_code
) value
;
2196 if (flag_code
== CODE_64BIT
)
2198 cpu_arch_flags
.bitfield
.cpu64
= 1;
2199 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2203 cpu_arch_flags
.bitfield
.cpu64
= 0;
2204 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2206 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2209 as_error
= as_fatal
;
2212 (*as_error
) (_("64bit mode not supported on `%s'."),
2213 cpu_arch_name
? cpu_arch_name
: default_arch
);
2215 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2218 as_error
= as_fatal
;
2221 (*as_error
) (_("32bit mode not supported on `%s'."),
2222 cpu_arch_name
? cpu_arch_name
: default_arch
);
2224 stackop_size
= '\0';
2228 set_code_flag (int value
)
2230 update_code_flag (value
, 0);
2234 set_16bit_gcc_code_flag (int new_code_flag
)
2236 flag_code
= (enum flag_code
) new_code_flag
;
2237 if (flag_code
!= CODE_16BIT
)
2239 cpu_arch_flags
.bitfield
.cpu64
= 0;
2240 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2241 stackop_size
= LONG_MNEM_SUFFIX
;
2245 set_intel_syntax (int syntax_flag
)
2247 /* Find out if register prefixing is specified. */
2248 int ask_naked_reg
= 0;
2251 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2253 char *string
= input_line_pointer
;
2254 int e
= get_symbol_end ();
2256 if (strcmp (string
, "prefix") == 0)
2258 else if (strcmp (string
, "noprefix") == 0)
2261 as_bad (_("bad argument to syntax directive."));
2262 *input_line_pointer
= e
;
2264 demand_empty_rest_of_line ();
2266 intel_syntax
= syntax_flag
;
2268 if (ask_naked_reg
== 0)
2269 allow_naked_reg
= (intel_syntax
2270 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2272 allow_naked_reg
= (ask_naked_reg
< 0);
2274 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2276 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2277 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2278 register_prefix
= allow_naked_reg
? "" : "%";
2282 set_intel_mnemonic (int mnemonic_flag
)
2284 intel_mnemonic
= mnemonic_flag
;
2288 set_allow_index_reg (int flag
)
2290 allow_index_reg
= flag
;
2294 set_check (int what
)
2296 enum check_kind
*kind
;
2301 kind
= &operand_check
;
2312 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2314 char *string
= input_line_pointer
;
2315 int e
= get_symbol_end ();
2317 if (strcmp (string
, "none") == 0)
2319 else if (strcmp (string
, "warning") == 0)
2320 *kind
= check_warning
;
2321 else if (strcmp (string
, "error") == 0)
2322 *kind
= check_error
;
2324 as_bad (_("bad argument to %s_check directive."), str
);
2325 *input_line_pointer
= e
;
2328 as_bad (_("missing argument for %s_check directive"), str
);
2330 demand_empty_rest_of_line ();
2334 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2335 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2337 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2338 static const char *arch
;
2340 /* Intel LIOM is only supported on ELF. */
2346 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2347 use default_arch. */
2348 arch
= cpu_arch_name
;
2350 arch
= default_arch
;
2353 /* If we are targeting Intel L1OM, we must enable it. */
2354 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2355 || new_flag
.bitfield
.cpul1om
)
2358 /* If we are targeting Intel K1OM, we must enable it. */
2359 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2360 || new_flag
.bitfield
.cpuk1om
)
2363 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2368 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2372 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2374 char *string
= input_line_pointer
;
2375 int e
= get_symbol_end ();
2377 i386_cpu_flags flags
;
2379 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2381 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2383 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2387 cpu_arch_name
= cpu_arch
[j
].name
;
2388 cpu_sub_arch_name
= NULL
;
2389 cpu_arch_flags
= cpu_arch
[j
].flags
;
2390 if (flag_code
== CODE_64BIT
)
2392 cpu_arch_flags
.bitfield
.cpu64
= 1;
2393 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2397 cpu_arch_flags
.bitfield
.cpu64
= 0;
2398 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2400 cpu_arch_isa
= cpu_arch
[j
].type
;
2401 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2402 if (!cpu_arch_tune_set
)
2404 cpu_arch_tune
= cpu_arch_isa
;
2405 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2410 if (!cpu_arch
[j
].negated
)
2411 flags
= cpu_flags_or (cpu_arch_flags
,
2414 flags
= cpu_flags_and_not (cpu_arch_flags
,
2416 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2418 if (cpu_sub_arch_name
)
2420 char *name
= cpu_sub_arch_name
;
2421 cpu_sub_arch_name
= concat (name
,
2423 (const char *) NULL
);
2427 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2428 cpu_arch_flags
= flags
;
2429 cpu_arch_isa_flags
= flags
;
2431 *input_line_pointer
= e
;
2432 demand_empty_rest_of_line ();
2436 if (j
>= ARRAY_SIZE (cpu_arch
))
2437 as_bad (_("no such architecture: `%s'"), string
);
2439 *input_line_pointer
= e
;
2442 as_bad (_("missing cpu architecture"));
2444 no_cond_jump_promotion
= 0;
2445 if (*input_line_pointer
== ','
2446 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2448 char *string
= ++input_line_pointer
;
2449 int e
= get_symbol_end ();
2451 if (strcmp (string
, "nojumps") == 0)
2452 no_cond_jump_promotion
= 1;
2453 else if (strcmp (string
, "jumps") == 0)
2456 as_bad (_("no such architecture modifier: `%s'"), string
);
2458 *input_line_pointer
= e
;
2461 demand_empty_rest_of_line ();
2464 enum bfd_architecture
2467 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2469 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2470 || flag_code
!= CODE_64BIT
)
2471 as_fatal (_("Intel L1OM is 64bit ELF only"));
2472 return bfd_arch_l1om
;
2474 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2476 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2477 || flag_code
!= CODE_64BIT
)
2478 as_fatal (_("Intel K1OM is 64bit ELF only"));
2479 return bfd_arch_k1om
;
2482 return bfd_arch_i386
;
2488 if (!strncmp (default_arch
, "x86_64", 6))
2490 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2492 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2493 || default_arch
[6] != '\0')
2494 as_fatal (_("Intel L1OM is 64bit ELF only"));
2495 return bfd_mach_l1om
;
2497 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2499 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2500 || default_arch
[6] != '\0')
2501 as_fatal (_("Intel K1OM is 64bit ELF only"));
2502 return bfd_mach_k1om
;
2504 else if (default_arch
[6] == '\0')
2505 return bfd_mach_x86_64
;
2507 return bfd_mach_x64_32
;
2509 else if (!strcmp (default_arch
, "i386"))
2510 return bfd_mach_i386_i386
;
2512 as_fatal (_("unknown architecture"));
2518 const char *hash_err
;
2520 /* Initialize op_hash hash table. */
2521 op_hash
= hash_new ();
2524 const insn_template
*optab
;
2525 templates
*core_optab
;
2527 /* Setup for loop. */
2529 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2530 core_optab
->start
= optab
;
2535 if (optab
->name
== NULL
2536 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2538 /* different name --> ship out current template list;
2539 add to hash table; & begin anew. */
2540 core_optab
->end
= optab
;
2541 hash_err
= hash_insert (op_hash
,
2543 (void *) core_optab
);
2546 as_fatal (_("can't hash %s: %s"),
2550 if (optab
->name
== NULL
)
2552 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2553 core_optab
->start
= optab
;
2558 /* Initialize reg_hash hash table. */
2559 reg_hash
= hash_new ();
2561 const reg_entry
*regtab
;
2562 unsigned int regtab_size
= i386_regtab_size
;
2564 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2566 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2568 as_fatal (_("can't hash %s: %s"),
2574 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2579 for (c
= 0; c
< 256; c
++)
2584 mnemonic_chars
[c
] = c
;
2585 register_chars
[c
] = c
;
2586 operand_chars
[c
] = c
;
2588 else if (ISLOWER (c
))
2590 mnemonic_chars
[c
] = c
;
2591 register_chars
[c
] = c
;
2592 operand_chars
[c
] = c
;
2594 else if (ISUPPER (c
))
2596 mnemonic_chars
[c
] = TOLOWER (c
);
2597 register_chars
[c
] = mnemonic_chars
[c
];
2598 operand_chars
[c
] = c
;
2600 else if (c
== '{' || c
== '}')
2601 operand_chars
[c
] = c
;
2603 if (ISALPHA (c
) || ISDIGIT (c
))
2604 identifier_chars
[c
] = c
;
2607 identifier_chars
[c
] = c
;
2608 operand_chars
[c
] = c
;
2613 identifier_chars
['@'] = '@';
2616 identifier_chars
['?'] = '?';
2617 operand_chars
['?'] = '?';
2619 digit_chars
['-'] = '-';
2620 mnemonic_chars
['_'] = '_';
2621 mnemonic_chars
['-'] = '-';
2622 mnemonic_chars
['.'] = '.';
2623 identifier_chars
['_'] = '_';
2624 identifier_chars
['.'] = '.';
2626 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2627 operand_chars
[(unsigned char) *p
] = *p
;
2630 if (flag_code
== CODE_64BIT
)
2632 #if defined (OBJ_COFF) && defined (TE_PE)
2633 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2636 x86_dwarf2_return_column
= 16;
2638 x86_cie_data_alignment
= -8;
2642 x86_dwarf2_return_column
= 8;
2643 x86_cie_data_alignment
= -4;
2648 i386_print_statistics (FILE *file
)
2650 hash_print_statistics (file
, "i386 opcode", op_hash
);
2651 hash_print_statistics (file
, "i386 register", reg_hash
);
2656 /* Debugging routines for md_assemble. */
2657 static void pte (insn_template
*);
2658 static void pt (i386_operand_type
);
2659 static void pe (expressionS
*);
2660 static void ps (symbolS
*);
2663 pi (char *line
, i386_insn
*x
)
2667 fprintf (stdout
, "%s: template ", line
);
2669 fprintf (stdout
, " address: base %s index %s scale %x\n",
2670 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2671 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2672 x
->log2_scale_factor
);
2673 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2674 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2675 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2676 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2677 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2678 (x
->rex
& REX_W
) != 0,
2679 (x
->rex
& REX_R
) != 0,
2680 (x
->rex
& REX_X
) != 0,
2681 (x
->rex
& REX_B
) != 0);
2682 for (j
= 0; j
< x
->operands
; j
++)
2684 fprintf (stdout
, " #%d: ", j
+ 1);
2686 fprintf (stdout
, "\n");
2687 if (x
->types
[j
].bitfield
.reg8
2688 || x
->types
[j
].bitfield
.reg16
2689 || x
->types
[j
].bitfield
.reg32
2690 || x
->types
[j
].bitfield
.reg64
2691 || x
->types
[j
].bitfield
.regmmx
2692 || x
->types
[j
].bitfield
.regxmm
2693 || x
->types
[j
].bitfield
.regymm
2694 || x
->types
[j
].bitfield
.regzmm
2695 || x
->types
[j
].bitfield
.sreg2
2696 || x
->types
[j
].bitfield
.sreg3
2697 || x
->types
[j
].bitfield
.control
2698 || x
->types
[j
].bitfield
.debug
2699 || x
->types
[j
].bitfield
.test
)
2700 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2701 if (operand_type_check (x
->types
[j
], imm
))
2703 if (operand_type_check (x
->types
[j
], disp
))
2704 pe (x
->op
[j
].disps
);
2709 pte (insn_template
*t
)
2712 fprintf (stdout
, " %d operands ", t
->operands
);
2713 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2714 if (t
->extension_opcode
!= None
)
2715 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2716 if (t
->opcode_modifier
.d
)
2717 fprintf (stdout
, "D");
2718 if (t
->opcode_modifier
.w
)
2719 fprintf (stdout
, "W");
2720 fprintf (stdout
, "\n");
2721 for (j
= 0; j
< t
->operands
; j
++)
2723 fprintf (stdout
, " #%d type ", j
+ 1);
2724 pt (t
->operand_types
[j
]);
2725 fprintf (stdout
, "\n");
2732 fprintf (stdout
, " operation %d\n", e
->X_op
);
2733 fprintf (stdout
, " add_number %ld (%lx)\n",
2734 (long) e
->X_add_number
, (long) e
->X_add_number
);
2735 if (e
->X_add_symbol
)
2737 fprintf (stdout
, " add_symbol ");
2738 ps (e
->X_add_symbol
);
2739 fprintf (stdout
, "\n");
2743 fprintf (stdout
, " op_symbol ");
2744 ps (e
->X_op_symbol
);
2745 fprintf (stdout
, "\n");
2752 fprintf (stdout
, "%s type %s%s",
2754 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2755 segment_name (S_GET_SEGMENT (s
)));
2758 static struct type_name
2760 i386_operand_type mask
;
2763 const type_names
[] =
2765 { OPERAND_TYPE_REG8
, "r8" },
2766 { OPERAND_TYPE_REG16
, "r16" },
2767 { OPERAND_TYPE_REG32
, "r32" },
2768 { OPERAND_TYPE_REG64
, "r64" },
2769 { OPERAND_TYPE_IMM8
, "i8" },
2770 { OPERAND_TYPE_IMM8
, "i8s" },
2771 { OPERAND_TYPE_IMM16
, "i16" },
2772 { OPERAND_TYPE_IMM32
, "i32" },
2773 { OPERAND_TYPE_IMM32S
, "i32s" },
2774 { OPERAND_TYPE_IMM64
, "i64" },
2775 { OPERAND_TYPE_IMM1
, "i1" },
2776 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2777 { OPERAND_TYPE_DISP8
, "d8" },
2778 { OPERAND_TYPE_DISP16
, "d16" },
2779 { OPERAND_TYPE_DISP32
, "d32" },
2780 { OPERAND_TYPE_DISP32S
, "d32s" },
2781 { OPERAND_TYPE_DISP64
, "d64" },
2782 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2783 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2784 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2785 { OPERAND_TYPE_CONTROL
, "control reg" },
2786 { OPERAND_TYPE_TEST
, "test reg" },
2787 { OPERAND_TYPE_DEBUG
, "debug reg" },
2788 { OPERAND_TYPE_FLOATREG
, "FReg" },
2789 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2790 { OPERAND_TYPE_SREG2
, "SReg2" },
2791 { OPERAND_TYPE_SREG3
, "SReg3" },
2792 { OPERAND_TYPE_ACC
, "Acc" },
2793 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2794 { OPERAND_TYPE_REGMMX
, "rMMX" },
2795 { OPERAND_TYPE_REGXMM
, "rXMM" },
2796 { OPERAND_TYPE_REGYMM
, "rYMM" },
2797 { OPERAND_TYPE_REGZMM
, "rZMM" },
2798 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2799 { OPERAND_TYPE_ESSEG
, "es" },
2803 pt (i386_operand_type t
)
2806 i386_operand_type a
;
2808 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2810 a
= operand_type_and (t
, type_names
[j
].mask
);
2811 if (!operand_type_all_zero (&a
))
2812 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2817 #endif /* DEBUG386 */
2819 static bfd_reloc_code_real_type
2820 reloc (unsigned int size
,
2824 bfd_reloc_code_real_type other
)
2826 if (other
!= NO_RELOC
)
2828 reloc_howto_type
*rel
;
2833 case BFD_RELOC_X86_64_GOT32
:
2834 return BFD_RELOC_X86_64_GOT64
;
2836 case BFD_RELOC_X86_64_PLTOFF64
:
2837 return BFD_RELOC_X86_64_PLTOFF64
;
2839 case BFD_RELOC_X86_64_GOTPC32
:
2840 other
= BFD_RELOC_X86_64_GOTPC64
;
2842 case BFD_RELOC_X86_64_GOTPCREL
:
2843 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2845 case BFD_RELOC_X86_64_TPOFF32
:
2846 other
= BFD_RELOC_X86_64_TPOFF64
;
2848 case BFD_RELOC_X86_64_DTPOFF32
:
2849 other
= BFD_RELOC_X86_64_DTPOFF64
;
2855 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2856 if (other
== BFD_RELOC_SIZE32
)
2859 other
= BFD_RELOC_SIZE64
;
2862 as_bad (_("there are no pc-relative size relocations"));
2868 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2869 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2872 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2874 as_bad (_("unknown relocation (%u)"), other
);
2875 else if (size
!= bfd_get_reloc_size (rel
))
2876 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2877 bfd_get_reloc_size (rel
),
2879 else if (pcrel
&& !rel
->pc_relative
)
2880 as_bad (_("non-pc-relative relocation for pc-relative field"));
2881 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2883 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2885 as_bad (_("relocated field and relocation type differ in signedness"));
2894 as_bad (_("there are no unsigned pc-relative relocations"));
2897 case 1: return BFD_RELOC_8_PCREL
;
2898 case 2: return BFD_RELOC_16_PCREL
;
2899 case 4: return (bnd_prefix
&& object_64bit
2900 ? BFD_RELOC_X86_64_PC32_BND
2901 : BFD_RELOC_32_PCREL
);
2902 case 8: return BFD_RELOC_64_PCREL
;
2904 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2911 case 4: return BFD_RELOC_X86_64_32S
;
2916 case 1: return BFD_RELOC_8
;
2917 case 2: return BFD_RELOC_16
;
2918 case 4: return BFD_RELOC_32
;
2919 case 8: return BFD_RELOC_64
;
2921 as_bad (_("cannot do %s %u byte relocation"),
2922 sign
> 0 ? "signed" : "unsigned", size
);
2928 /* Here we decide which fixups can be adjusted to make them relative to
2929 the beginning of the section instead of the symbol. Basically we need
2930 to make sure that the dynamic relocations are done correctly, so in
2931 some cases we force the original symbol to be used. */
2934 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2936 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2940 /* Don't adjust pc-relative references to merge sections in 64-bit
2942 if (use_rela_relocations
2943 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2947 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2948 and changed later by validate_fix. */
2949 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2950 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2953 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2954 for size relocations. */
2955 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2956 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2957 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2958 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2959 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2960 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2961 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2962 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2963 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2964 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2965 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2966 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2967 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2968 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2969 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2970 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2971 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2972 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2973 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2974 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2975 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2976 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2977 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2978 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2979 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2980 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2981 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2982 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2983 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2984 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2991 intel_float_operand (const char *mnemonic
)
2993 /* Note that the value returned is meaningful only for opcodes with (memory)
2994 operands, hence the code here is free to improperly handle opcodes that
2995 have no operands (for better performance and smaller code). */
2997 if (mnemonic
[0] != 'f')
2998 return 0; /* non-math */
3000 switch (mnemonic
[1])
3002 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3003 the fs segment override prefix not currently handled because no
3004 call path can make opcodes without operands get here */
3006 return 2 /* integer op */;
3008 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3009 return 3; /* fldcw/fldenv */
3012 if (mnemonic
[2] != 'o' /* fnop */)
3013 return 3; /* non-waiting control op */
3016 if (mnemonic
[2] == 's')
3017 return 3; /* frstor/frstpm */
3020 if (mnemonic
[2] == 'a')
3021 return 3; /* fsave */
3022 if (mnemonic
[2] == 't')
3024 switch (mnemonic
[3])
3026 case 'c': /* fstcw */
3027 case 'd': /* fstdw */
3028 case 'e': /* fstenv */
3029 case 's': /* fsts[gw] */
3035 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3036 return 0; /* fxsave/fxrstor are not really math ops */
3043 /* Build the VEX prefix. */
3046 build_vex_prefix (const insn_template
*t
)
3048 unsigned int register_specifier
;
3049 unsigned int implied_prefix
;
3050 unsigned int vector_length
;
3052 /* Check register specifier. */
3053 if (i
.vex
.register_specifier
)
3055 register_specifier
=
3056 ~register_number (i
.vex
.register_specifier
) & 0xf;
3057 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3060 register_specifier
= 0xf;
3062 /* Use 2-byte VEX prefix by swappping destination and source
3065 && i
.operands
== i
.reg_operands
3066 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3067 && i
.tm
.opcode_modifier
.s
3070 unsigned int xchg
= i
.operands
- 1;
3071 union i386_op temp_op
;
3072 i386_operand_type temp_type
;
3074 temp_type
= i
.types
[xchg
];
3075 i
.types
[xchg
] = i
.types
[0];
3076 i
.types
[0] = temp_type
;
3077 temp_op
= i
.op
[xchg
];
3078 i
.op
[xchg
] = i
.op
[0];
3081 gas_assert (i
.rm
.mode
== 3);
3085 i
.rm
.regmem
= i
.rm
.reg
;
3088 /* Use the next insn. */
3092 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3093 vector_length
= avxscalar
;
3095 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3097 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3102 case DATA_PREFIX_OPCODE
:
3105 case REPE_PREFIX_OPCODE
:
3108 case REPNE_PREFIX_OPCODE
:
3115 /* Use 2-byte VEX prefix if possible. */
3116 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3117 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3118 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3120 /* 2-byte VEX prefix. */
3124 i
.vex
.bytes
[0] = 0xc5;
3126 /* Check the REX.R bit. */
3127 r
= (i
.rex
& REX_R
) ? 0 : 1;
3128 i
.vex
.bytes
[1] = (r
<< 7
3129 | register_specifier
<< 3
3130 | vector_length
<< 2
3135 /* 3-byte VEX prefix. */
3140 switch (i
.tm
.opcode_modifier
.vexopcode
)
3144 i
.vex
.bytes
[0] = 0xc4;
3148 i
.vex
.bytes
[0] = 0xc4;
3152 i
.vex
.bytes
[0] = 0xc4;
3156 i
.vex
.bytes
[0] = 0x8f;
3160 i
.vex
.bytes
[0] = 0x8f;
3164 i
.vex
.bytes
[0] = 0x8f;
3170 /* The high 3 bits of the second VEX byte are 1's compliment
3171 of RXB bits from REX. */
3172 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3174 /* Check the REX.W bit. */
3175 w
= (i
.rex
& REX_W
) ? 1 : 0;
3176 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3179 i
.vex
.bytes
[2] = (w
<< 7
3180 | register_specifier
<< 3
3181 | vector_length
<< 2
3186 /* Build the EVEX prefix. */
3189 build_evex_prefix (void)
3191 unsigned int register_specifier
;
3192 unsigned int implied_prefix
;
3194 rex_byte vrex_used
= 0;
3196 /* Check register specifier. */
3197 if (i
.vex
.register_specifier
)
3199 gas_assert ((i
.vrex
& REX_X
) == 0);
3201 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3202 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3203 register_specifier
+= 8;
3204 /* The upper 16 registers are encoded in the fourth byte of the
3206 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3207 i
.vex
.bytes
[3] = 0x8;
3208 register_specifier
= ~register_specifier
& 0xf;
3212 register_specifier
= 0xf;
3214 /* Encode upper 16 vector index register in the fourth byte of
3216 if (!(i
.vrex
& REX_X
))
3217 i
.vex
.bytes
[3] = 0x8;
3222 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3227 case DATA_PREFIX_OPCODE
:
3230 case REPE_PREFIX_OPCODE
:
3233 case REPNE_PREFIX_OPCODE
:
3240 /* 4 byte EVEX prefix. */
3242 i
.vex
.bytes
[0] = 0x62;
3245 switch (i
.tm
.opcode_modifier
.vexopcode
)
3261 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3263 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3265 /* The fifth bit of the second EVEX byte is 1's compliment of the
3266 REX_R bit in VREX. */
3267 if (!(i
.vrex
& REX_R
))
3268 i
.vex
.bytes
[1] |= 0x10;
3272 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3274 /* When all operands are registers, the REX_X bit in REX is not
3275 used. We reuse it to encode the upper 16 registers, which is
3276 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3277 as 1's compliment. */
3278 if ((i
.vrex
& REX_B
))
3281 i
.vex
.bytes
[1] &= ~0x40;
3285 /* EVEX instructions shouldn't need the REX prefix. */
3286 i
.vrex
&= ~vrex_used
;
3287 gas_assert (i
.vrex
== 0);
3289 /* Check the REX.W bit. */
3290 w
= (i
.rex
& REX_W
) ? 1 : 0;
3291 if (i
.tm
.opcode_modifier
.vexw
)
3293 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3296 /* If w is not set it means we are dealing with WIG instruction. */
3299 if (evexwig
== evexw1
)
3303 /* Encode the U bit. */
3304 implied_prefix
|= 0x4;
3306 /* The third byte of the EVEX prefix. */
3307 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3309 /* The fourth byte of the EVEX prefix. */
3310 /* The zeroing-masking bit. */
3311 if (i
.mask
&& i
.mask
->zeroing
)
3312 i
.vex
.bytes
[3] |= 0x80;
3314 /* Don't always set the broadcast bit if there is no RC. */
3317 /* Encode the vector length. */
3318 unsigned int vec_length
;
3320 switch (i
.tm
.opcode_modifier
.evex
)
3322 case EVEXLIG
: /* LL' is ignored */
3323 vec_length
= evexlig
<< 5;
3326 vec_length
= 0 << 5;
3329 vec_length
= 1 << 5;
3332 vec_length
= 2 << 5;
3338 i
.vex
.bytes
[3] |= vec_length
;
3339 /* Encode the broadcast bit. */
3341 i
.vex
.bytes
[3] |= 0x10;
3345 if (i
.rounding
->type
!= saeonly
)
3346 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3348 i
.vex
.bytes
[3] |= 0x10;
3351 if (i
.mask
&& i
.mask
->mask
)
3352 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3356 process_immext (void)
3360 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3363 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3364 with an opcode suffix which is coded in the same place as an
3365 8-bit immediate field would be.
3366 Here we check those operands and remove them afterwards. */
3369 for (x
= 0; x
< i
.operands
; x
++)
3370 if (register_number (i
.op
[x
].regs
) != x
)
3371 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3372 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3378 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3379 which is coded in the same place as an 8-bit immediate field
3380 would be. Here we fake an 8-bit immediate operand from the
3381 opcode suffix stored in tm.extension_opcode.
3383 AVX instructions also use this encoding, for some of
3384 3 argument instructions. */
3386 gas_assert (i
.imm_operands
<= 1
3388 || ((i
.tm
.opcode_modifier
.vex
3389 || i
.tm
.opcode_modifier
.evex
)
3390 && i
.operands
<= 4)));
3392 exp
= &im_expressions
[i
.imm_operands
++];
3393 i
.op
[i
.operands
].imms
= exp
;
3394 i
.types
[i
.operands
] = imm8
;
3396 exp
->X_op
= O_constant
;
3397 exp
->X_add_number
= i
.tm
.extension_opcode
;
3398 i
.tm
.extension_opcode
= None
;
3405 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3410 as_bad (_("invalid instruction `%s' after `%s'"),
3411 i
.tm
.name
, i
.hle_prefix
);
3414 if (i
.prefix
[LOCK_PREFIX
])
3416 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3420 case HLEPrefixRelease
:
3421 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3423 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3427 if (i
.mem_operands
== 0
3428 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3430 as_bad (_("memory destination needed for instruction `%s'"
3431 " after `xrelease'"), i
.tm
.name
);
3438 /* This is the guts of the machine-dependent assembler. LINE points to a
3439 machine dependent instruction. This function is supposed to emit
3440 the frags/bytes it assembles to. */
3443 md_assemble (char *line
)
3446 char mnemonic
[MAX_MNEM_SIZE
];
3447 const insn_template
*t
;
3449 /* Initialize globals. */
3450 memset (&i
, '\0', sizeof (i
));
3451 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3452 i
.reloc
[j
] = NO_RELOC
;
3453 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3454 memset (im_expressions
, '\0', sizeof (im_expressions
));
3455 save_stack_p
= save_stack
;
3457 /* First parse an instruction mnemonic & call i386_operand for the operands.
3458 We assume that the scrubber has arranged it so that line[0] is the valid
3459 start of a (possibly prefixed) mnemonic. */
3461 line
= parse_insn (line
, mnemonic
);
3465 line
= parse_operands (line
, mnemonic
);
3470 /* Now we've parsed the mnemonic into a set of templates, and have the
3471 operands at hand. */
3473 /* All intel opcodes have reversed operands except for "bound" and
3474 "enter". We also don't reverse intersegment "jmp" and "call"
3475 instructions with 2 immediate operands so that the immediate segment
3476 precedes the offset, as it does when in AT&T mode. */
3479 && (strcmp (mnemonic
, "bound") != 0)
3480 && (strcmp (mnemonic
, "invlpga") != 0)
3481 && !(operand_type_check (i
.types
[0], imm
)
3482 && operand_type_check (i
.types
[1], imm
)))
3485 /* The order of the immediates should be reversed
3486 for 2 immediates extrq and insertq instructions */
3487 if (i
.imm_operands
== 2
3488 && (strcmp (mnemonic
, "extrq") == 0
3489 || strcmp (mnemonic
, "insertq") == 0))
3490 swap_2_operands (0, 1);
3495 /* Don't optimize displacement for movabs since it only takes 64bit
3498 && i
.disp_encoding
!= disp_encoding_32bit
3499 && (flag_code
!= CODE_64BIT
3500 || strcmp (mnemonic
, "movabs") != 0))
3503 /* Next, we find a template that matches the given insn,
3504 making sure the overlap of the given operands types is consistent
3505 with the template operand types. */
3507 if (!(t
= match_template ()))
3510 if (sse_check
!= check_none
3511 && !i
.tm
.opcode_modifier
.noavx
3512 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3513 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3514 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3515 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3516 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3517 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3519 (sse_check
== check_warning
3521 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3524 /* Zap movzx and movsx suffix. The suffix has been set from
3525 "word ptr" or "byte ptr" on the source operand in Intel syntax
3526 or extracted from mnemonic in AT&T syntax. But we'll use
3527 the destination register to choose the suffix for encoding. */
3528 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3530 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3531 there is no suffix, the default will be byte extension. */
3532 if (i
.reg_operands
!= 2
3535 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3540 if (i
.tm
.opcode_modifier
.fwait
)
3541 if (!add_prefix (FWAIT_OPCODE
))
3544 /* Check if REP prefix is OK. */
3545 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3547 as_bad (_("invalid instruction `%s' after `%s'"),
3548 i
.tm
.name
, i
.rep_prefix
);
3552 /* Check for lock without a lockable instruction. Destination operand
3553 must be memory unless it is xchg (0x86). */
3554 if (i
.prefix
[LOCK_PREFIX
]
3555 && (!i
.tm
.opcode_modifier
.islockable
3556 || i
.mem_operands
== 0
3557 || (i
.tm
.base_opcode
!= 0x86
3558 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3560 as_bad (_("expecting lockable instruction after `lock'"));
3564 /* Check if HLE prefix is OK. */
3565 if (i
.hle_prefix
&& !check_hle ())
3568 /* Check BND prefix. */
3569 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3570 as_bad (_("expecting valid branch instruction after `bnd'"));
3572 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3573 && flag_code
== CODE_64BIT
3574 && i
.prefix
[ADDR_PREFIX
])
3575 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3577 /* Insert BND prefix. */
3579 && i
.tm
.opcode_modifier
.bndprefixok
3580 && !i
.prefix
[BND_PREFIX
])
3581 add_prefix (BND_PREFIX_OPCODE
);
3583 /* Check string instruction segment overrides. */
3584 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3586 if (!check_string ())
3588 i
.disp_operands
= 0;
3591 if (!process_suffix ())
3594 /* Update operand types. */
3595 for (j
= 0; j
< i
.operands
; j
++)
3596 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3598 /* Make still unresolved immediate matches conform to size of immediate
3599 given in i.suffix. */
3600 if (!finalize_imm ())
3603 if (i
.types
[0].bitfield
.imm1
)
3604 i
.imm_operands
= 0; /* kludge for shift insns. */
3606 /* We only need to check those implicit registers for instructions
3607 with 3 operands or less. */
3608 if (i
.operands
<= 3)
3609 for (j
= 0; j
< i
.operands
; j
++)
3610 if (i
.types
[j
].bitfield
.inoutportreg
3611 || i
.types
[j
].bitfield
.shiftcount
3612 || i
.types
[j
].bitfield
.acc
3613 || i
.types
[j
].bitfield
.floatacc
)
3616 /* ImmExt should be processed after SSE2AVX. */
3617 if (!i
.tm
.opcode_modifier
.sse2avx
3618 && i
.tm
.opcode_modifier
.immext
)
3621 /* For insns with operands there are more diddles to do to the opcode. */
3624 if (!process_operands ())
3627 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3629 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3630 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3633 if (i
.tm
.opcode_modifier
.vex
)
3634 build_vex_prefix (t
);
3636 if (i
.tm
.opcode_modifier
.evex
)
3637 build_evex_prefix ();
3639 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3640 instructions may define INT_OPCODE as well, so avoid this corner
3641 case for those instructions that use MODRM. */
3642 if (i
.tm
.base_opcode
== INT_OPCODE
3643 && !i
.tm
.opcode_modifier
.modrm
3644 && i
.op
[0].imms
->X_add_number
== 3)
3646 i
.tm
.base_opcode
= INT3_OPCODE
;
3650 if ((i
.tm
.opcode_modifier
.jump
3651 || i
.tm
.opcode_modifier
.jumpbyte
3652 || i
.tm
.opcode_modifier
.jumpdword
)
3653 && i
.op
[0].disps
->X_op
== O_constant
)
3655 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3656 the absolute address given by the constant. Since ix86 jumps and
3657 calls are pc relative, we need to generate a reloc. */
3658 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3659 i
.op
[0].disps
->X_op
= O_symbol
;
3662 if (i
.tm
.opcode_modifier
.rex64
)
3665 /* For 8 bit registers we need an empty rex prefix. Also if the
3666 instruction already has a prefix, we need to convert old
3667 registers to new ones. */
3669 if ((i
.types
[0].bitfield
.reg8
3670 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3671 || (i
.types
[1].bitfield
.reg8
3672 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3673 || ((i
.types
[0].bitfield
.reg8
3674 || i
.types
[1].bitfield
.reg8
)
3679 i
.rex
|= REX_OPCODE
;
3680 for (x
= 0; x
< 2; x
++)
3682 /* Look for 8 bit operand that uses old registers. */
3683 if (i
.types
[x
].bitfield
.reg8
3684 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3686 /* In case it is "hi" register, give up. */
3687 if (i
.op
[x
].regs
->reg_num
> 3)
3688 as_bad (_("can't encode register '%s%s' in an "
3689 "instruction requiring REX prefix."),
3690 register_prefix
, i
.op
[x
].regs
->reg_name
);
3692 /* Otherwise it is equivalent to the extended register.
3693 Since the encoding doesn't change this is merely
3694 cosmetic cleanup for debug output. */
3696 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3702 add_prefix (REX_OPCODE
| i
.rex
);
3704 /* We are ready to output the insn. */
3709 parse_insn (char *line
, char *mnemonic
)
3712 char *token_start
= l
;
3715 const insn_template
*t
;
3721 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3726 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3728 as_bad (_("no such instruction: `%s'"), token_start
);
3733 if (!is_space_char (*l
)
3734 && *l
!= END_OF_INSN
3736 || (*l
!= PREFIX_SEPARATOR
3739 as_bad (_("invalid character %s in mnemonic"),
3740 output_invalid (*l
));
3743 if (token_start
== l
)
3745 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3746 as_bad (_("expecting prefix; got nothing"));
3748 as_bad (_("expecting mnemonic; got nothing"));
3752 /* Look up instruction (or prefix) via hash table. */
3753 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3755 if (*l
!= END_OF_INSN
3756 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3757 && current_templates
3758 && current_templates
->start
->opcode_modifier
.isprefix
)
3760 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3762 as_bad ((flag_code
!= CODE_64BIT
3763 ? _("`%s' is only supported in 64-bit mode")
3764 : _("`%s' is not supported in 64-bit mode")),
3765 current_templates
->start
->name
);
3768 /* If we are in 16-bit mode, do not allow addr16 or data16.
3769 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3770 if ((current_templates
->start
->opcode_modifier
.size16
3771 || current_templates
->start
->opcode_modifier
.size32
)
3772 && flag_code
!= CODE_64BIT
3773 && (current_templates
->start
->opcode_modifier
.size32
3774 ^ (flag_code
== CODE_16BIT
)))
3776 as_bad (_("redundant %s prefix"),
3777 current_templates
->start
->name
);
3780 /* Add prefix, checking for repeated prefixes. */
3781 switch (add_prefix (current_templates
->start
->base_opcode
))
3786 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3787 i
.hle_prefix
= current_templates
->start
->name
;
3788 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3789 i
.bnd_prefix
= current_templates
->start
->name
;
3791 i
.rep_prefix
= current_templates
->start
->name
;
3796 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3803 if (!current_templates
)
3805 /* Check if we should swap operand or force 32bit displacement in
3807 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3809 else if (mnem_p
- 3 == dot_p
3812 i
.disp_encoding
= disp_encoding_8bit
;
3813 else if (mnem_p
- 4 == dot_p
3817 i
.disp_encoding
= disp_encoding_32bit
;
3822 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3825 if (!current_templates
)
3828 /* See if we can get a match by trimming off a suffix. */
3831 case WORD_MNEM_SUFFIX
:
3832 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3833 i
.suffix
= SHORT_MNEM_SUFFIX
;
3835 case BYTE_MNEM_SUFFIX
:
3836 case QWORD_MNEM_SUFFIX
:
3837 i
.suffix
= mnem_p
[-1];
3839 current_templates
= (const templates
*) hash_find (op_hash
,
3842 case SHORT_MNEM_SUFFIX
:
3843 case LONG_MNEM_SUFFIX
:
3846 i
.suffix
= mnem_p
[-1];
3848 current_templates
= (const templates
*) hash_find (op_hash
,
3857 if (intel_float_operand (mnemonic
) == 1)
3858 i
.suffix
= SHORT_MNEM_SUFFIX
;
3860 i
.suffix
= LONG_MNEM_SUFFIX
;
3862 current_templates
= (const templates
*) hash_find (op_hash
,
3867 if (!current_templates
)
3869 as_bad (_("no such instruction: `%s'"), token_start
);
3874 if (current_templates
->start
->opcode_modifier
.jump
3875 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3877 /* Check for a branch hint. We allow ",pt" and ",pn" for
3878 predict taken and predict not taken respectively.
3879 I'm not sure that branch hints actually do anything on loop
3880 and jcxz insns (JumpByte) for current Pentium4 chips. They
3881 may work in the future and it doesn't hurt to accept them
3883 if (l
[0] == ',' && l
[1] == 'p')
3887 if (!add_prefix (DS_PREFIX_OPCODE
))
3891 else if (l
[2] == 'n')
3893 if (!add_prefix (CS_PREFIX_OPCODE
))
3899 /* Any other comma loses. */
3902 as_bad (_("invalid character %s in mnemonic"),
3903 output_invalid (*l
));
3907 /* Check if instruction is supported on specified architecture. */
3909 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3911 supported
|= cpu_flags_match (t
);
3912 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3916 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3918 as_bad (flag_code
== CODE_64BIT
3919 ? _("`%s' is not supported in 64-bit mode")
3920 : _("`%s' is only supported in 64-bit mode"),
3921 current_templates
->start
->name
);
3924 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3926 as_bad (_("`%s' is not supported on `%s%s'"),
3927 current_templates
->start
->name
,
3928 cpu_arch_name
? cpu_arch_name
: default_arch
,
3929 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3934 if (!cpu_arch_flags
.bitfield
.cpui386
3935 && (flag_code
!= CODE_16BIT
))
3937 as_warn (_("use .code16 to ensure correct addressing mode"));
3944 parse_operands (char *l
, const char *mnemonic
)
3948 /* 1 if operand is pending after ','. */
3949 unsigned int expecting_operand
= 0;
3951 /* Non-zero if operand parens not balanced. */
3952 unsigned int paren_not_balanced
;
3954 while (*l
!= END_OF_INSN
)
3956 /* Skip optional white space before operand. */
3957 if (is_space_char (*l
))
3959 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3961 as_bad (_("invalid character %s before operand %d"),
3962 output_invalid (*l
),
3966 token_start
= l
; /* after white space */
3967 paren_not_balanced
= 0;
3968 while (paren_not_balanced
|| *l
!= ',')
3970 if (*l
== END_OF_INSN
)
3972 if (paren_not_balanced
)
3975 as_bad (_("unbalanced parenthesis in operand %d."),
3978 as_bad (_("unbalanced brackets in operand %d."),
3983 break; /* we are done */
3985 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3987 as_bad (_("invalid character %s in operand %d"),
3988 output_invalid (*l
),
3995 ++paren_not_balanced
;
3997 --paren_not_balanced
;
4002 ++paren_not_balanced
;
4004 --paren_not_balanced
;
4008 if (l
!= token_start
)
4009 { /* Yes, we've read in another operand. */
4010 unsigned int operand_ok
;
4011 this_operand
= i
.operands
++;
4012 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4013 if (i
.operands
> MAX_OPERANDS
)
4015 as_bad (_("spurious operands; (%d operands/instruction max)"),
4019 /* Now parse operand adding info to 'i' as we go along. */
4020 END_STRING_AND_SAVE (l
);
4024 i386_intel_operand (token_start
,
4025 intel_float_operand (mnemonic
));
4027 operand_ok
= i386_att_operand (token_start
);
4029 RESTORE_END_STRING (l
);
4035 if (expecting_operand
)
4037 expecting_operand_after_comma
:
4038 as_bad (_("expecting operand after ','; got nothing"));
4043 as_bad (_("expecting operand before ','; got nothing"));
4048 /* Now *l must be either ',' or END_OF_INSN. */
4051 if (*++l
== END_OF_INSN
)
4053 /* Just skip it, if it's \n complain. */
4054 goto expecting_operand_after_comma
;
4056 expecting_operand
= 1;
4063 swap_2_operands (int xchg1
, int xchg2
)
4065 union i386_op temp_op
;
4066 i386_operand_type temp_type
;
4067 enum bfd_reloc_code_real temp_reloc
;
4069 temp_type
= i
.types
[xchg2
];
4070 i
.types
[xchg2
] = i
.types
[xchg1
];
4071 i
.types
[xchg1
] = temp_type
;
4072 temp_op
= i
.op
[xchg2
];
4073 i
.op
[xchg2
] = i
.op
[xchg1
];
4074 i
.op
[xchg1
] = temp_op
;
4075 temp_reloc
= i
.reloc
[xchg2
];
4076 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4077 i
.reloc
[xchg1
] = temp_reloc
;
4081 if (i
.mask
->operand
== xchg1
)
4082 i
.mask
->operand
= xchg2
;
4083 else if (i
.mask
->operand
== xchg2
)
4084 i
.mask
->operand
= xchg1
;
4088 if (i
.broadcast
->operand
== xchg1
)
4089 i
.broadcast
->operand
= xchg2
;
4090 else if (i
.broadcast
->operand
== xchg2
)
4091 i
.broadcast
->operand
= xchg1
;
4095 if (i
.rounding
->operand
== xchg1
)
4096 i
.rounding
->operand
= xchg2
;
4097 else if (i
.rounding
->operand
== xchg2
)
4098 i
.rounding
->operand
= xchg1
;
4103 swap_operands (void)
4109 swap_2_operands (1, i
.operands
- 2);
4112 swap_2_operands (0, i
.operands
- 1);
4118 if (i
.mem_operands
== 2)
4120 const seg_entry
*temp_seg
;
4121 temp_seg
= i
.seg
[0];
4122 i
.seg
[0] = i
.seg
[1];
4123 i
.seg
[1] = temp_seg
;
4127 /* Try to ensure constant immediates are represented in the smallest
4132 char guess_suffix
= 0;
4136 guess_suffix
= i
.suffix
;
4137 else if (i
.reg_operands
)
4139 /* Figure out a suffix from the last register operand specified.
4140 We can't do this properly yet, ie. excluding InOutPortReg,
4141 but the following works for instructions with immediates.
4142 In any case, we can't set i.suffix yet. */
4143 for (op
= i
.operands
; --op
>= 0;)
4144 if (i
.types
[op
].bitfield
.reg8
)
4146 guess_suffix
= BYTE_MNEM_SUFFIX
;
4149 else if (i
.types
[op
].bitfield
.reg16
)
4151 guess_suffix
= WORD_MNEM_SUFFIX
;
4154 else if (i
.types
[op
].bitfield
.reg32
)
4156 guess_suffix
= LONG_MNEM_SUFFIX
;
4159 else if (i
.types
[op
].bitfield
.reg64
)
4161 guess_suffix
= QWORD_MNEM_SUFFIX
;
4165 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4166 guess_suffix
= WORD_MNEM_SUFFIX
;
4168 for (op
= i
.operands
; --op
>= 0;)
4169 if (operand_type_check (i
.types
[op
], imm
))
4171 switch (i
.op
[op
].imms
->X_op
)
4174 /* If a suffix is given, this operand may be shortened. */
4175 switch (guess_suffix
)
4177 case LONG_MNEM_SUFFIX
:
4178 i
.types
[op
].bitfield
.imm32
= 1;
4179 i
.types
[op
].bitfield
.imm64
= 1;
4181 case WORD_MNEM_SUFFIX
:
4182 i
.types
[op
].bitfield
.imm16
= 1;
4183 i
.types
[op
].bitfield
.imm32
= 1;
4184 i
.types
[op
].bitfield
.imm32s
= 1;
4185 i
.types
[op
].bitfield
.imm64
= 1;
4187 case BYTE_MNEM_SUFFIX
:
4188 i
.types
[op
].bitfield
.imm8
= 1;
4189 i
.types
[op
].bitfield
.imm8s
= 1;
4190 i
.types
[op
].bitfield
.imm16
= 1;
4191 i
.types
[op
].bitfield
.imm32
= 1;
4192 i
.types
[op
].bitfield
.imm32s
= 1;
4193 i
.types
[op
].bitfield
.imm64
= 1;
4197 /* If this operand is at most 16 bits, convert it
4198 to a signed 16 bit number before trying to see
4199 whether it will fit in an even smaller size.
4200 This allows a 16-bit operand such as $0xffe0 to
4201 be recognised as within Imm8S range. */
4202 if ((i
.types
[op
].bitfield
.imm16
)
4203 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4205 i
.op
[op
].imms
->X_add_number
=
4206 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4208 if ((i
.types
[op
].bitfield
.imm32
)
4209 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4212 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4213 ^ ((offsetT
) 1 << 31))
4214 - ((offsetT
) 1 << 31));
4217 = operand_type_or (i
.types
[op
],
4218 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4220 /* We must avoid matching of Imm32 templates when 64bit
4221 only immediate is available. */
4222 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4223 i
.types
[op
].bitfield
.imm32
= 0;
4230 /* Symbols and expressions. */
4232 /* Convert symbolic operand to proper sizes for matching, but don't
4233 prevent matching a set of insns that only supports sizes other
4234 than those matching the insn suffix. */
4236 i386_operand_type mask
, allowed
;
4237 const insn_template
*t
;
4239 operand_type_set (&mask
, 0);
4240 operand_type_set (&allowed
, 0);
4242 for (t
= current_templates
->start
;
4243 t
< current_templates
->end
;
4245 allowed
= operand_type_or (allowed
,
4246 t
->operand_types
[op
]);
4247 switch (guess_suffix
)
4249 case QWORD_MNEM_SUFFIX
:
4250 mask
.bitfield
.imm64
= 1;
4251 mask
.bitfield
.imm32s
= 1;
4253 case LONG_MNEM_SUFFIX
:
4254 mask
.bitfield
.imm32
= 1;
4256 case WORD_MNEM_SUFFIX
:
4257 mask
.bitfield
.imm16
= 1;
4259 case BYTE_MNEM_SUFFIX
:
4260 mask
.bitfield
.imm8
= 1;
4265 allowed
= operand_type_and (mask
, allowed
);
4266 if (!operand_type_all_zero (&allowed
))
4267 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4274 /* Try to use the smallest displacement type too. */
4276 optimize_disp (void)
4280 for (op
= i
.operands
; --op
>= 0;)
4281 if (operand_type_check (i
.types
[op
], disp
))
4283 if (i
.op
[op
].disps
->X_op
== O_constant
)
4285 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4287 if (i
.types
[op
].bitfield
.disp16
4288 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4290 /* If this operand is at most 16 bits, convert
4291 to a signed 16 bit number and don't use 64bit
4293 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4294 i
.types
[op
].bitfield
.disp64
= 0;
4296 if (i
.types
[op
].bitfield
.disp32
4297 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4299 /* If this operand is at most 32 bits, convert
4300 to a signed 32 bit number and don't use 64bit
4302 op_disp
&= (((offsetT
) 2 << 31) - 1);
4303 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4304 i
.types
[op
].bitfield
.disp64
= 0;
4306 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4308 i
.types
[op
].bitfield
.disp8
= 0;
4309 i
.types
[op
].bitfield
.disp16
= 0;
4310 i
.types
[op
].bitfield
.disp32
= 0;
4311 i
.types
[op
].bitfield
.disp32s
= 0;
4312 i
.types
[op
].bitfield
.disp64
= 0;
4316 else if (flag_code
== CODE_64BIT
)
4318 if (fits_in_signed_long (op_disp
))
4320 i
.types
[op
].bitfield
.disp64
= 0;
4321 i
.types
[op
].bitfield
.disp32s
= 1;
4323 if (i
.prefix
[ADDR_PREFIX
]
4324 && fits_in_unsigned_long (op_disp
))
4325 i
.types
[op
].bitfield
.disp32
= 1;
4327 if ((i
.types
[op
].bitfield
.disp32
4328 || i
.types
[op
].bitfield
.disp32s
4329 || i
.types
[op
].bitfield
.disp16
)
4330 && fits_in_signed_byte (op_disp
))
4331 i
.types
[op
].bitfield
.disp8
= 1;
4333 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4334 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4336 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4337 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4338 i
.types
[op
].bitfield
.disp8
= 0;
4339 i
.types
[op
].bitfield
.disp16
= 0;
4340 i
.types
[op
].bitfield
.disp32
= 0;
4341 i
.types
[op
].bitfield
.disp32s
= 0;
4342 i
.types
[op
].bitfield
.disp64
= 0;
4345 /* We only support 64bit displacement on constants. */
4346 i
.types
[op
].bitfield
.disp64
= 0;
4350 /* Check if operands are valid for the instruction. */
4353 check_VecOperands (const insn_template
*t
)
4357 /* Without VSIB byte, we can't have a vector register for index. */
4358 if (!t
->opcode_modifier
.vecsib
4360 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4361 || i
.index_reg
->reg_type
.bitfield
.regymm
4362 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4364 i
.error
= unsupported_vector_index_register
;
4368 /* Check if default mask is allowed. */
4369 if (t
->opcode_modifier
.nodefmask
4370 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4372 i
.error
= no_default_mask
;
4376 /* For VSIB byte, we need a vector register for index, and all vector
4377 registers must be distinct. */
4378 if (t
->opcode_modifier
.vecsib
)
4381 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4382 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4383 || (t
->opcode_modifier
.vecsib
== VecSIB256
4384 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4385 || (t
->opcode_modifier
.vecsib
== VecSIB512
4386 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4388 i
.error
= invalid_vsib_address
;
4392 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4393 if (i
.reg_operands
== 2 && !i
.mask
)
4395 gas_assert (i
.types
[0].bitfield
.regxmm
4396 || i
.types
[0].bitfield
.regymm
);
4397 gas_assert (i
.types
[2].bitfield
.regxmm
4398 || i
.types
[2].bitfield
.regymm
);
4399 if (operand_check
== check_none
)
4401 if (register_number (i
.op
[0].regs
)
4402 != register_number (i
.index_reg
)
4403 && register_number (i
.op
[2].regs
)
4404 != register_number (i
.index_reg
)
4405 && register_number (i
.op
[0].regs
)
4406 != register_number (i
.op
[2].regs
))
4408 if (operand_check
== check_error
)
4410 i
.error
= invalid_vector_register_set
;
4413 as_warn (_("mask, index, and destination registers should be distinct"));
4415 else if (i
.reg_operands
== 1 && i
.mask
)
4417 if ((i
.types
[1].bitfield
.regymm
4418 || i
.types
[1].bitfield
.regzmm
)
4419 && (register_number (i
.op
[1].regs
)
4420 == register_number (i
.index_reg
)))
4422 if (operand_check
== check_error
)
4424 i
.error
= invalid_vector_register_set
;
4427 if (operand_check
!= check_none
)
4428 as_warn (_("index and destination registers should be distinct"));
4433 /* Check if broadcast is supported by the instruction and is applied
4434 to the memory operand. */
4437 int broadcasted_opnd_size
;
4439 /* Check if specified broadcast is supported in this instruction,
4440 and it's applied to memory operand of DWORD or QWORD type,
4441 depending on VecESize. */
4442 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4443 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4444 || (t
->opcode_modifier
.vecesize
== 0
4445 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4446 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4447 || (t
->opcode_modifier
.vecesize
== 1
4448 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4449 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4452 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4453 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4454 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4455 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4456 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4457 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4458 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4459 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4460 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4464 if ((broadcasted_opnd_size
== 256
4465 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4466 || (broadcasted_opnd_size
== 512
4467 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4470 i
.error
= unsupported_broadcast
;
4474 /* If broadcast is supported in this instruction, we need to check if
4475 operand of one-element size isn't specified without broadcast. */
4476 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4478 /* Find memory operand. */
4479 for (op
= 0; op
< i
.operands
; op
++)
4480 if (operand_type_check (i
.types
[op
], anymem
))
4482 gas_assert (op
< i
.operands
);
4483 /* Check size of the memory operand. */
4484 if ((t
->opcode_modifier
.vecesize
== 0
4485 && i
.types
[op
].bitfield
.dword
)
4486 || (t
->opcode_modifier
.vecesize
== 1
4487 && i
.types
[op
].bitfield
.qword
))
4489 i
.error
= broadcast_needed
;
4494 /* Check if requested masking is supported. */
4496 && (!t
->opcode_modifier
.masking
4498 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4500 i
.error
= unsupported_masking
;
4504 /* Check if masking is applied to dest operand. */
4505 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4507 i
.error
= mask_not_on_destination
;
4514 if ((i
.rounding
->type
!= saeonly
4515 && !t
->opcode_modifier
.staticrounding
)
4516 || (i
.rounding
->type
== saeonly
4517 && (t
->opcode_modifier
.staticrounding
4518 || !t
->opcode_modifier
.sae
)))
4520 i
.error
= unsupported_rc_sae
;
4523 /* If the instruction has several immediate operands and one of
4524 them is rounding, the rounding operand should be the last
4525 immediate operand. */
4526 if (i
.imm_operands
> 1
4527 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4529 i
.error
= rc_sae_operand_not_last_imm
;
4534 /* Check vector Disp8 operand. */
4535 if (t
->opcode_modifier
.disp8memshift
)
4538 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4540 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4542 for (op
= 0; op
< i
.operands
; op
++)
4543 if (operand_type_check (i
.types
[op
], disp
)
4544 && i
.op
[op
].disps
->X_op
== O_constant
)
4546 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4547 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4548 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4551 i
.types
[op
].bitfield
.vec_disp8
= 1;
4554 /* Vector insn can only have Vec_Disp8/Disp32 in
4555 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4557 i
.types
[op
].bitfield
.disp8
= 0;
4558 if (flag_code
!= CODE_16BIT
)
4559 i
.types
[op
].bitfield
.disp16
= 0;
4562 else if (flag_code
!= CODE_16BIT
)
4564 /* One form of this instruction supports vector Disp8.
4565 Try vector Disp8 if we need to use Disp32. */
4566 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4568 i
.error
= try_vector_disp8
;
4580 /* Check if operands are valid for the instruction. Update VEX
4584 VEX_check_operands (const insn_template
*t
)
4586 /* VREX is only valid with EVEX prefix. */
4587 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4589 i
.error
= invalid_register_operand
;
4593 if (!t
->opcode_modifier
.vex
)
4596 /* Only check VEX_Imm4, which must be the first operand. */
4597 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4599 if (i
.op
[0].imms
->X_op
!= O_constant
4600 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4606 /* Turn off Imm8 so that update_imm won't complain. */
4607 i
.types
[0] = vec_imm4
;
4613 static const insn_template
*
4614 match_template (void)
4616 /* Points to template once we've found it. */
4617 const insn_template
*t
;
4618 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4619 i386_operand_type overlap4
;
4620 unsigned int found_reverse_match
;
4621 i386_opcode_modifier suffix_check
;
4622 i386_operand_type operand_types
[MAX_OPERANDS
];
4623 int addr_prefix_disp
;
4625 unsigned int found_cpu_match
;
4626 unsigned int check_register
;
4627 enum i386_error specific_error
= 0;
4629 #if MAX_OPERANDS != 5
4630 # error "MAX_OPERANDS must be 5."
4633 found_reverse_match
= 0;
4634 addr_prefix_disp
= -1;
4636 memset (&suffix_check
, 0, sizeof (suffix_check
));
4637 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4638 suffix_check
.no_bsuf
= 1;
4639 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4640 suffix_check
.no_wsuf
= 1;
4641 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4642 suffix_check
.no_ssuf
= 1;
4643 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4644 suffix_check
.no_lsuf
= 1;
4645 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4646 suffix_check
.no_qsuf
= 1;
4647 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4648 suffix_check
.no_ldsuf
= 1;
4650 /* Must have right number of operands. */
4651 i
.error
= number_of_operands_mismatch
;
4653 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4655 addr_prefix_disp
= -1;
4657 if (i
.operands
!= t
->operands
)
4660 /* Check processor support. */
4661 i
.error
= unsupported
;
4662 found_cpu_match
= (cpu_flags_match (t
)
4663 == CPU_FLAGS_PERFECT_MATCH
);
4664 if (!found_cpu_match
)
4667 /* Check old gcc support. */
4668 i
.error
= old_gcc_only
;
4669 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4672 /* Check AT&T mnemonic. */
4673 i
.error
= unsupported_with_intel_mnemonic
;
4674 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4677 /* Check AT&T/Intel syntax. */
4678 i
.error
= unsupported_syntax
;
4679 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4680 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4683 /* Check the suffix, except for some instructions in intel mode. */
4684 i
.error
= invalid_instruction_suffix
;
4685 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4686 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4687 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4688 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4689 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4690 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4691 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4694 if (!operand_size_match (t
))
4697 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4698 operand_types
[j
] = t
->operand_types
[j
];
4700 /* In general, don't allow 64-bit operands in 32-bit mode. */
4701 if (i
.suffix
== QWORD_MNEM_SUFFIX
4702 && flag_code
!= CODE_64BIT
4704 ? (!t
->opcode_modifier
.ignoresize
4705 && !intel_float_operand (t
->name
))
4706 : intel_float_operand (t
->name
) != 2)
4707 && ((!operand_types
[0].bitfield
.regmmx
4708 && !operand_types
[0].bitfield
.regxmm
4709 && !operand_types
[0].bitfield
.regymm
4710 && !operand_types
[0].bitfield
.regzmm
)
4711 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4712 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4713 && operand_types
[t
->operands
> 1].bitfield
.regymm
4714 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4715 && (t
->base_opcode
!= 0x0fc7
4716 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4719 /* In general, don't allow 32-bit operands on pre-386. */
4720 else if (i
.suffix
== LONG_MNEM_SUFFIX
4721 && !cpu_arch_flags
.bitfield
.cpui386
4723 ? (!t
->opcode_modifier
.ignoresize
4724 && !intel_float_operand (t
->name
))
4725 : intel_float_operand (t
->name
) != 2)
4726 && ((!operand_types
[0].bitfield
.regmmx
4727 && !operand_types
[0].bitfield
.regxmm
)
4728 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4729 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4732 /* Do not verify operands when there are none. */
4736 /* We've found a match; break out of loop. */
4740 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4741 into Disp32/Disp16/Disp32 operand. */
4742 if (i
.prefix
[ADDR_PREFIX
] != 0)
4744 /* There should be only one Disp operand. */
4748 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4750 if (operand_types
[j
].bitfield
.disp16
)
4752 addr_prefix_disp
= j
;
4753 operand_types
[j
].bitfield
.disp32
= 1;
4754 operand_types
[j
].bitfield
.disp16
= 0;
4760 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4762 if (operand_types
[j
].bitfield
.disp32
)
4764 addr_prefix_disp
= j
;
4765 operand_types
[j
].bitfield
.disp32
= 0;
4766 operand_types
[j
].bitfield
.disp16
= 1;
4772 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4774 if (operand_types
[j
].bitfield
.disp64
)
4776 addr_prefix_disp
= j
;
4777 operand_types
[j
].bitfield
.disp64
= 0;
4778 operand_types
[j
].bitfield
.disp32
= 1;
4786 /* We check register size if needed. */
4787 check_register
= t
->opcode_modifier
.checkregsize
;
4788 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4789 switch (t
->operands
)
4792 if (!operand_type_match (overlap0
, i
.types
[0]))
4796 /* xchg %eax, %eax is a special case. It is an aliase for nop
4797 only in 32bit mode and we can use opcode 0x90. In 64bit
4798 mode, we can't use 0x90 for xchg %eax, %eax since it should
4799 zero-extend %eax to %rax. */
4800 if (flag_code
== CODE_64BIT
4801 && t
->base_opcode
== 0x90
4802 && operand_type_equal (&i
.types
[0], &acc32
)
4803 && operand_type_equal (&i
.types
[1], &acc32
))
4807 /* If we swap operand in encoding, we either match
4808 the next one or reverse direction of operands. */
4809 if (t
->opcode_modifier
.s
)
4811 else if (t
->opcode_modifier
.d
)
4816 /* If we swap operand in encoding, we match the next one. */
4817 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4821 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4822 if (!operand_type_match (overlap0
, i
.types
[0])
4823 || !operand_type_match (overlap1
, i
.types
[1])
4825 && !operand_type_register_match (overlap0
, i
.types
[0],
4827 overlap1
, i
.types
[1],
4830 /* Check if other direction is valid ... */
4831 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4835 /* Try reversing direction of operands. */
4836 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4837 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4838 if (!operand_type_match (overlap0
, i
.types
[0])
4839 || !operand_type_match (overlap1
, i
.types
[1])
4841 && !operand_type_register_match (overlap0
,
4848 /* Does not match either direction. */
4851 /* found_reverse_match holds which of D or FloatDR
4853 if (t
->opcode_modifier
.d
)
4854 found_reverse_match
= Opcode_D
;
4855 else if (t
->opcode_modifier
.floatd
)
4856 found_reverse_match
= Opcode_FloatD
;
4858 found_reverse_match
= 0;
4859 if (t
->opcode_modifier
.floatr
)
4860 found_reverse_match
|= Opcode_FloatR
;
4864 /* Found a forward 2 operand match here. */
4865 switch (t
->operands
)
4868 overlap4
= operand_type_and (i
.types
[4],
4871 overlap3
= operand_type_and (i
.types
[3],
4874 overlap2
= operand_type_and (i
.types
[2],
4879 switch (t
->operands
)
4882 if (!operand_type_match (overlap4
, i
.types
[4])
4883 || !operand_type_register_match (overlap3
,
4891 if (!operand_type_match (overlap3
, i
.types
[3])
4893 && !operand_type_register_match (overlap2
,
4901 /* Here we make use of the fact that there are no
4902 reverse match 3 operand instructions, and all 3
4903 operand instructions only need to be checked for
4904 register consistency between operands 2 and 3. */
4905 if (!operand_type_match (overlap2
, i
.types
[2])
4907 && !operand_type_register_match (overlap1
,
4917 /* Found either forward/reverse 2, 3 or 4 operand match here:
4918 slip through to break. */
4920 if (!found_cpu_match
)
4922 found_reverse_match
= 0;
4926 /* Check if vector and VEX operands are valid. */
4927 if (check_VecOperands (t
) || VEX_check_operands (t
))
4929 specific_error
= i
.error
;
4933 /* We've found a match; break out of loop. */
4937 if (t
== current_templates
->end
)
4939 /* We found no match. */
4940 const char *err_msg
;
4941 switch (specific_error
? specific_error
: i
.error
)
4945 case operand_size_mismatch
:
4946 err_msg
= _("operand size mismatch");
4948 case operand_type_mismatch
:
4949 err_msg
= _("operand type mismatch");
4951 case register_type_mismatch
:
4952 err_msg
= _("register type mismatch");
4954 case number_of_operands_mismatch
:
4955 err_msg
= _("number of operands mismatch");
4957 case invalid_instruction_suffix
:
4958 err_msg
= _("invalid instruction suffix");
4961 err_msg
= _("constant doesn't fit in 4 bits");
4964 err_msg
= _("only supported with old gcc");
4966 case unsupported_with_intel_mnemonic
:
4967 err_msg
= _("unsupported with Intel mnemonic");
4969 case unsupported_syntax
:
4970 err_msg
= _("unsupported syntax");
4973 as_bad (_("unsupported instruction `%s'"),
4974 current_templates
->start
->name
);
4976 case invalid_vsib_address
:
4977 err_msg
= _("invalid VSIB address");
4979 case invalid_vector_register_set
:
4980 err_msg
= _("mask, index, and destination registers must be distinct");
4982 case unsupported_vector_index_register
:
4983 err_msg
= _("unsupported vector index register");
4985 case unsupported_broadcast
:
4986 err_msg
= _("unsupported broadcast");
4988 case broadcast_not_on_src_operand
:
4989 err_msg
= _("broadcast not on source memory operand");
4991 case broadcast_needed
:
4992 err_msg
= _("broadcast is needed for operand of such type");
4994 case unsupported_masking
:
4995 err_msg
= _("unsupported masking");
4997 case mask_not_on_destination
:
4998 err_msg
= _("mask not on destination operand");
5000 case no_default_mask
:
5001 err_msg
= _("default mask isn't allowed");
5003 case unsupported_rc_sae
:
5004 err_msg
= _("unsupported static rounding/sae");
5006 case rc_sae_operand_not_last_imm
:
5008 err_msg
= _("RC/SAE operand must precede immediate operands");
5010 err_msg
= _("RC/SAE operand must follow immediate operands");
5012 case invalid_register_operand
:
5013 err_msg
= _("invalid register operand");
5016 as_bad (_("%s for `%s'"), err_msg
,
5017 current_templates
->start
->name
);
5021 if (!quiet_warnings
)
5024 && (i
.types
[0].bitfield
.jumpabsolute
5025 != operand_types
[0].bitfield
.jumpabsolute
))
5027 as_warn (_("indirect %s without `*'"), t
->name
);
5030 if (t
->opcode_modifier
.isprefix
5031 && t
->opcode_modifier
.ignoresize
)
5033 /* Warn them that a data or address size prefix doesn't
5034 affect assembly of the next line of code. */
5035 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5039 /* Copy the template we found. */
5042 if (addr_prefix_disp
!= -1)
5043 i
.tm
.operand_types
[addr_prefix_disp
]
5044 = operand_types
[addr_prefix_disp
];
5046 if (found_reverse_match
)
5048 /* If we found a reverse match we must alter the opcode
5049 direction bit. found_reverse_match holds bits to change
5050 (different for int & float insns). */
5052 i
.tm
.base_opcode
^= found_reverse_match
;
5054 i
.tm
.operand_types
[0] = operand_types
[1];
5055 i
.tm
.operand_types
[1] = operand_types
[0];
5064 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5065 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5067 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5069 as_bad (_("`%s' operand %d must use `%ses' segment"),
5075 /* There's only ever one segment override allowed per instruction.
5076 This instruction possibly has a legal segment override on the
5077 second operand, so copy the segment to where non-string
5078 instructions store it, allowing common code. */
5079 i
.seg
[0] = i
.seg
[1];
5081 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5083 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5085 as_bad (_("`%s' operand %d must use `%ses' segment"),
5096 process_suffix (void)
5098 /* If matched instruction specifies an explicit instruction mnemonic
5100 if (i
.tm
.opcode_modifier
.size16
)
5101 i
.suffix
= WORD_MNEM_SUFFIX
;
5102 else if (i
.tm
.opcode_modifier
.size32
)
5103 i
.suffix
= LONG_MNEM_SUFFIX
;
5104 else if (i
.tm
.opcode_modifier
.size64
)
5105 i
.suffix
= QWORD_MNEM_SUFFIX
;
5106 else if (i
.reg_operands
)
5108 /* If there's no instruction mnemonic suffix we try to invent one
5109 based on register operands. */
5112 /* We take i.suffix from the last register operand specified,
5113 Destination register type is more significant than source
5114 register type. crc32 in SSE4.2 prefers source register
5116 if (i
.tm
.base_opcode
== 0xf20f38f1)
5118 if (i
.types
[0].bitfield
.reg16
)
5119 i
.suffix
= WORD_MNEM_SUFFIX
;
5120 else if (i
.types
[0].bitfield
.reg32
)
5121 i
.suffix
= LONG_MNEM_SUFFIX
;
5122 else if (i
.types
[0].bitfield
.reg64
)
5123 i
.suffix
= QWORD_MNEM_SUFFIX
;
5125 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5127 if (i
.types
[0].bitfield
.reg8
)
5128 i
.suffix
= BYTE_MNEM_SUFFIX
;
5135 if (i
.tm
.base_opcode
== 0xf20f38f1
5136 || i
.tm
.base_opcode
== 0xf20f38f0)
5138 /* We have to know the operand size for crc32. */
5139 as_bad (_("ambiguous memory operand size for `%s`"),
5144 for (op
= i
.operands
; --op
>= 0;)
5145 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5147 if (i
.types
[op
].bitfield
.reg8
)
5149 i
.suffix
= BYTE_MNEM_SUFFIX
;
5152 else if (i
.types
[op
].bitfield
.reg16
)
5154 i
.suffix
= WORD_MNEM_SUFFIX
;
5157 else if (i
.types
[op
].bitfield
.reg32
)
5159 i
.suffix
= LONG_MNEM_SUFFIX
;
5162 else if (i
.types
[op
].bitfield
.reg64
)
5164 i
.suffix
= QWORD_MNEM_SUFFIX
;
5170 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5173 && i
.tm
.opcode_modifier
.ignoresize
5174 && i
.tm
.opcode_modifier
.no_bsuf
)
5176 else if (!check_byte_reg ())
5179 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5182 && i
.tm
.opcode_modifier
.ignoresize
5183 && i
.tm
.opcode_modifier
.no_lsuf
)
5185 else if (!check_long_reg ())
5188 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5191 && i
.tm
.opcode_modifier
.ignoresize
5192 && i
.tm
.opcode_modifier
.no_qsuf
)
5194 else if (!check_qword_reg ())
5197 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5200 && i
.tm
.opcode_modifier
.ignoresize
5201 && i
.tm
.opcode_modifier
.no_wsuf
)
5203 else if (!check_word_reg ())
5206 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5207 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5208 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5210 /* Skip if the instruction has x/y/z suffix. match_template
5211 should check if it is a valid suffix. */
5213 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5214 /* Do nothing if the instruction is going to ignore the prefix. */
5219 else if (i
.tm
.opcode_modifier
.defaultsize
5221 /* exclude fldenv/frstor/fsave/fstenv */
5222 && i
.tm
.opcode_modifier
.no_ssuf
)
5224 i
.suffix
= stackop_size
;
5226 else if (intel_syntax
5228 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5229 || i
.tm
.opcode_modifier
.jumpbyte
5230 || i
.tm
.opcode_modifier
.jumpintersegment
5231 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5232 && i
.tm
.extension_opcode
<= 3)))
5237 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5239 i
.suffix
= QWORD_MNEM_SUFFIX
;
5243 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5244 i
.suffix
= LONG_MNEM_SUFFIX
;
5247 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5248 i
.suffix
= WORD_MNEM_SUFFIX
;
5257 if (i
.tm
.opcode_modifier
.w
)
5259 as_bad (_("no instruction mnemonic suffix given and "
5260 "no register operands; can't size instruction"));
5266 unsigned int suffixes
;
5268 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5269 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5271 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5273 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5275 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5277 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5280 /* There are more than suffix matches. */
5281 if (i
.tm
.opcode_modifier
.w
5282 || ((suffixes
& (suffixes
- 1))
5283 && !i
.tm
.opcode_modifier
.defaultsize
5284 && !i
.tm
.opcode_modifier
.ignoresize
))
5286 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5292 /* Change the opcode based on the operand size given by i.suffix;
5293 We don't need to change things for byte insns. */
5296 && i
.suffix
!= BYTE_MNEM_SUFFIX
5297 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5298 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5299 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5301 /* It's not a byte, select word/dword operation. */
5302 if (i
.tm
.opcode_modifier
.w
)
5304 if (i
.tm
.opcode_modifier
.shortform
)
5305 i
.tm
.base_opcode
|= 8;
5307 i
.tm
.base_opcode
|= 1;
5310 /* Now select between word & dword operations via the operand
5311 size prefix, except for instructions that will ignore this
5313 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5315 /* The address size override prefix changes the size of the
5317 if ((flag_code
== CODE_32BIT
5318 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5319 || (flag_code
!= CODE_32BIT
5320 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5321 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5324 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5325 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5326 && !i
.tm
.opcode_modifier
.ignoresize
5327 && !i
.tm
.opcode_modifier
.floatmf
5328 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5329 || (flag_code
== CODE_64BIT
5330 && i
.tm
.opcode_modifier
.jumpbyte
)))
5332 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5334 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5335 prefix
= ADDR_PREFIX_OPCODE
;
5337 if (!add_prefix (prefix
))
5341 /* Set mode64 for an operand. */
5342 if (i
.suffix
== QWORD_MNEM_SUFFIX
5343 && flag_code
== CODE_64BIT
5344 && !i
.tm
.opcode_modifier
.norex64
)
5346 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5347 need rex64. cmpxchg8b is also a special case. */
5348 if (! (i
.operands
== 2
5349 && i
.tm
.base_opcode
== 0x90
5350 && i
.tm
.extension_opcode
== None
5351 && operand_type_equal (&i
.types
[0], &acc64
)
5352 && operand_type_equal (&i
.types
[1], &acc64
))
5353 && ! (i
.operands
== 1
5354 && i
.tm
.base_opcode
== 0xfc7
5355 && i
.tm
.extension_opcode
== 1
5356 && !operand_type_check (i
.types
[0], reg
)
5357 && operand_type_check (i
.types
[0], anymem
)))
5361 /* Size floating point instruction. */
5362 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5363 if (i
.tm
.opcode_modifier
.floatmf
)
5364 i
.tm
.base_opcode
^= 4;
5371 check_byte_reg (void)
5375 for (op
= i
.operands
; --op
>= 0;)
5377 /* If this is an eight bit register, it's OK. If it's the 16 or
5378 32 bit version of an eight bit register, we will just use the
5379 low portion, and that's OK too. */
5380 if (i
.types
[op
].bitfield
.reg8
)
5383 /* I/O port address operands are OK too. */
5384 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5387 /* crc32 doesn't generate this warning. */
5388 if (i
.tm
.base_opcode
== 0xf20f38f0)
5391 if ((i
.types
[op
].bitfield
.reg16
5392 || i
.types
[op
].bitfield
.reg32
5393 || i
.types
[op
].bitfield
.reg64
)
5394 && i
.op
[op
].regs
->reg_num
< 4
5395 /* Prohibit these changes in 64bit mode, since the lowering
5396 would be more complicated. */
5397 && flag_code
!= CODE_64BIT
)
5399 #if REGISTER_WARNINGS
5400 if (!quiet_warnings
)
5401 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5403 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5404 ? REGNAM_AL
- REGNAM_AX
5405 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5407 i
.op
[op
].regs
->reg_name
,
5412 /* Any other register is bad. */
5413 if (i
.types
[op
].bitfield
.reg16
5414 || i
.types
[op
].bitfield
.reg32
5415 || i
.types
[op
].bitfield
.reg64
5416 || i
.types
[op
].bitfield
.regmmx
5417 || i
.types
[op
].bitfield
.regxmm
5418 || i
.types
[op
].bitfield
.regymm
5419 || i
.types
[op
].bitfield
.regzmm
5420 || i
.types
[op
].bitfield
.sreg2
5421 || i
.types
[op
].bitfield
.sreg3
5422 || i
.types
[op
].bitfield
.control
5423 || i
.types
[op
].bitfield
.debug
5424 || i
.types
[op
].bitfield
.test
5425 || i
.types
[op
].bitfield
.floatreg
5426 || i
.types
[op
].bitfield
.floatacc
)
5428 as_bad (_("`%s%s' not allowed with `%s%c'"),
5430 i
.op
[op
].regs
->reg_name
,
5440 check_long_reg (void)
5444 for (op
= i
.operands
; --op
>= 0;)
5445 /* Reject eight bit registers, except where the template requires
5446 them. (eg. movzb) */
5447 if (i
.types
[op
].bitfield
.reg8
5448 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5449 || i
.tm
.operand_types
[op
].bitfield
.reg32
5450 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5452 as_bad (_("`%s%s' not allowed with `%s%c'"),
5454 i
.op
[op
].regs
->reg_name
,
5459 /* Warn if the e prefix on a general reg is missing. */
5460 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5461 && i
.types
[op
].bitfield
.reg16
5462 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5463 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5465 /* Prohibit these changes in the 64bit mode, since the
5466 lowering is more complicated. */
5467 if (flag_code
== CODE_64BIT
)
5469 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5470 register_prefix
, i
.op
[op
].regs
->reg_name
,
5474 #if REGISTER_WARNINGS
5475 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5477 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5478 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5481 /* Warn if the r prefix on a general reg is present. */
5482 else if (i
.types
[op
].bitfield
.reg64
5483 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5484 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5487 && i
.tm
.opcode_modifier
.toqword
5488 && !i
.types
[0].bitfield
.regxmm
)
5490 /* Convert to QWORD. We want REX byte. */
5491 i
.suffix
= QWORD_MNEM_SUFFIX
;
5495 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5496 register_prefix
, i
.op
[op
].regs
->reg_name
,
5505 check_qword_reg (void)
5509 for (op
= i
.operands
; --op
>= 0; )
5510 /* Reject eight bit registers, except where the template requires
5511 them. (eg. movzb) */
5512 if (i
.types
[op
].bitfield
.reg8
5513 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5514 || i
.tm
.operand_types
[op
].bitfield
.reg32
5515 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5517 as_bad (_("`%s%s' not allowed with `%s%c'"),
5519 i
.op
[op
].regs
->reg_name
,
5524 /* Warn if the r prefix on a general reg is missing. */
5525 else if ((i
.types
[op
].bitfield
.reg16
5526 || i
.types
[op
].bitfield
.reg32
)
5527 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5528 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5530 /* Prohibit these changes in the 64bit mode, since the
5531 lowering is more complicated. */
5533 && i
.tm
.opcode_modifier
.todword
5534 && !i
.types
[0].bitfield
.regxmm
)
5536 /* Convert to DWORD. We don't want REX byte. */
5537 i
.suffix
= LONG_MNEM_SUFFIX
;
5541 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5542 register_prefix
, i
.op
[op
].regs
->reg_name
,
5551 check_word_reg (void)
5554 for (op
= i
.operands
; --op
>= 0;)
5555 /* Reject eight bit registers, except where the template requires
5556 them. (eg. movzb) */
5557 if (i
.types
[op
].bitfield
.reg8
5558 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5559 || i
.tm
.operand_types
[op
].bitfield
.reg32
5560 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5562 as_bad (_("`%s%s' not allowed with `%s%c'"),
5564 i
.op
[op
].regs
->reg_name
,
5569 /* Warn if the e or r prefix on a general reg is present. */
5570 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5571 && (i
.types
[op
].bitfield
.reg32
5572 || i
.types
[op
].bitfield
.reg64
)
5573 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5574 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5576 /* Prohibit these changes in the 64bit mode, since the
5577 lowering is more complicated. */
5578 if (flag_code
== CODE_64BIT
)
5580 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5581 register_prefix
, i
.op
[op
].regs
->reg_name
,
5585 #if REGISTER_WARNINGS
5586 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5588 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5589 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5596 update_imm (unsigned int j
)
5598 i386_operand_type overlap
= i
.types
[j
];
5599 if ((overlap
.bitfield
.imm8
5600 || overlap
.bitfield
.imm8s
5601 || overlap
.bitfield
.imm16
5602 || overlap
.bitfield
.imm32
5603 || overlap
.bitfield
.imm32s
5604 || overlap
.bitfield
.imm64
)
5605 && !operand_type_equal (&overlap
, &imm8
)
5606 && !operand_type_equal (&overlap
, &imm8s
)
5607 && !operand_type_equal (&overlap
, &imm16
)
5608 && !operand_type_equal (&overlap
, &imm32
)
5609 && !operand_type_equal (&overlap
, &imm32s
)
5610 && !operand_type_equal (&overlap
, &imm64
))
5614 i386_operand_type temp
;
5616 operand_type_set (&temp
, 0);
5617 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5619 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5620 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5622 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5623 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5624 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5626 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5627 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5630 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5633 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5634 || operand_type_equal (&overlap
, &imm16_32
)
5635 || operand_type_equal (&overlap
, &imm16_32s
))
5637 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5642 if (!operand_type_equal (&overlap
, &imm8
)
5643 && !operand_type_equal (&overlap
, &imm8s
)
5644 && !operand_type_equal (&overlap
, &imm16
)
5645 && !operand_type_equal (&overlap
, &imm32
)
5646 && !operand_type_equal (&overlap
, &imm32s
)
5647 && !operand_type_equal (&overlap
, &imm64
))
5649 as_bad (_("no instruction mnemonic suffix given; "
5650 "can't determine immediate size"));
5654 i
.types
[j
] = overlap
;
5664 /* Update the first 2 immediate operands. */
5665 n
= i
.operands
> 2 ? 2 : i
.operands
;
5668 for (j
= 0; j
< n
; j
++)
5669 if (update_imm (j
) == 0)
5672 /* The 3rd operand can't be immediate operand. */
5673 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5680 bad_implicit_operand (int xmm
)
5682 const char *ireg
= xmm
? "xmm0" : "ymm0";
5685 as_bad (_("the last operand of `%s' must be `%s%s'"),
5686 i
.tm
.name
, register_prefix
, ireg
);
5688 as_bad (_("the first operand of `%s' must be `%s%s'"),
5689 i
.tm
.name
, register_prefix
, ireg
);
5694 process_operands (void)
5696 /* Default segment register this instruction will use for memory
5697 accesses. 0 means unknown. This is only for optimizing out
5698 unnecessary segment overrides. */
5699 const seg_entry
*default_seg
= 0;
5701 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5703 unsigned int dupl
= i
.operands
;
5704 unsigned int dest
= dupl
- 1;
5707 /* The destination must be an xmm register. */
5708 gas_assert (i
.reg_operands
5709 && MAX_OPERANDS
> dupl
5710 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5712 if (i
.tm
.opcode_modifier
.firstxmm0
)
5714 /* The first operand is implicit and must be xmm0. */
5715 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5716 if (register_number (i
.op
[0].regs
) != 0)
5717 return bad_implicit_operand (1);
5719 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5721 /* Keep xmm0 for instructions with VEX prefix and 3
5727 /* We remove the first xmm0 and keep the number of
5728 operands unchanged, which in fact duplicates the
5730 for (j
= 1; j
< i
.operands
; j
++)
5732 i
.op
[j
- 1] = i
.op
[j
];
5733 i
.types
[j
- 1] = i
.types
[j
];
5734 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5738 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5740 gas_assert ((MAX_OPERANDS
- 1) > dupl
5741 && (i
.tm
.opcode_modifier
.vexsources
5744 /* Add the implicit xmm0 for instructions with VEX prefix
5746 for (j
= i
.operands
; j
> 0; j
--)
5748 i
.op
[j
] = i
.op
[j
- 1];
5749 i
.types
[j
] = i
.types
[j
- 1];
5750 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5753 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5754 i
.types
[0] = regxmm
;
5755 i
.tm
.operand_types
[0] = regxmm
;
5758 i
.reg_operands
+= 2;
5763 i
.op
[dupl
] = i
.op
[dest
];
5764 i
.types
[dupl
] = i
.types
[dest
];
5765 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5774 i
.op
[dupl
] = i
.op
[dest
];
5775 i
.types
[dupl
] = i
.types
[dest
];
5776 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5779 if (i
.tm
.opcode_modifier
.immext
)
5782 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5786 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5787 gas_assert (i
.reg_operands
5788 && (operand_type_equal (&i
.types
[0], ®xmm
)
5789 || operand_type_equal (&i
.types
[0], ®ymm
)
5790 || operand_type_equal (&i
.types
[0], ®zmm
)));
5791 if (register_number (i
.op
[0].regs
) != 0)
5792 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5794 for (j
= 1; j
< i
.operands
; j
++)
5796 i
.op
[j
- 1] = i
.op
[j
];
5797 i
.types
[j
- 1] = i
.types
[j
];
5799 /* We need to adjust fields in i.tm since they are used by
5800 build_modrm_byte. */
5801 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5808 else if (i
.tm
.opcode_modifier
.regkludge
)
5810 /* The imul $imm, %reg instruction is converted into
5811 imul $imm, %reg, %reg, and the clr %reg instruction
5812 is converted into xor %reg, %reg. */
5814 unsigned int first_reg_op
;
5816 if (operand_type_check (i
.types
[0], reg
))
5820 /* Pretend we saw the extra register operand. */
5821 gas_assert (i
.reg_operands
== 1
5822 && i
.op
[first_reg_op
+ 1].regs
== 0);
5823 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5824 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5829 if (i
.tm
.opcode_modifier
.shortform
)
5831 if (i
.types
[0].bitfield
.sreg2
5832 || i
.types
[0].bitfield
.sreg3
)
5834 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5835 && i
.op
[0].regs
->reg_num
== 1)
5837 as_bad (_("you can't `pop %scs'"), register_prefix
);
5840 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5841 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5846 /* The register or float register operand is in operand
5850 if (i
.types
[0].bitfield
.floatreg
5851 || operand_type_check (i
.types
[0], reg
))
5855 /* Register goes in low 3 bits of opcode. */
5856 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5857 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5859 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5861 /* Warn about some common errors, but press on regardless.
5862 The first case can be generated by gcc (<= 2.8.1). */
5863 if (i
.operands
== 2)
5865 /* Reversed arguments on faddp, fsubp, etc. */
5866 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5867 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5868 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5872 /* Extraneous `l' suffix on fp insn. */
5873 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5874 register_prefix
, i
.op
[0].regs
->reg_name
);
5879 else if (i
.tm
.opcode_modifier
.modrm
)
5881 /* The opcode is completed (modulo i.tm.extension_opcode which
5882 must be put into the modrm byte). Now, we make the modrm and
5883 index base bytes based on all the info we've collected. */
5885 default_seg
= build_modrm_byte ();
5887 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5891 else if (i
.tm
.opcode_modifier
.isstring
)
5893 /* For the string instructions that allow a segment override
5894 on one of their operands, the default segment is ds. */
5898 if (i
.tm
.base_opcode
== 0x8d /* lea */
5901 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5903 /* If a segment was explicitly specified, and the specified segment
5904 is not the default, use an opcode prefix to select it. If we
5905 never figured out what the default segment is, then default_seg
5906 will be zero at this point, and the specified segment prefix will
5908 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5910 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5916 static const seg_entry
*
5917 build_modrm_byte (void)
5919 const seg_entry
*default_seg
= 0;
5920 unsigned int source
, dest
;
5923 /* The first operand of instructions with VEX prefix and 3 sources
5924 must be VEX_Imm4. */
5925 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5928 unsigned int nds
, reg_slot
;
5931 if (i
.tm
.opcode_modifier
.veximmext
5932 && i
.tm
.opcode_modifier
.immext
)
5934 dest
= i
.operands
- 2;
5935 gas_assert (dest
== 3);
5938 dest
= i
.operands
- 1;
5941 /* There are 2 kinds of instructions:
5942 1. 5 operands: 4 register operands or 3 register operands
5943 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5944 VexW0 or VexW1. The destination must be either XMM, YMM or
5946 2. 4 operands: 4 register operands or 3 register operands
5947 plus 1 memory operand, VexXDS, and VexImmExt */
5948 gas_assert ((i
.reg_operands
== 4
5949 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5950 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5951 && (i
.tm
.opcode_modifier
.veximmext
5952 || (i
.imm_operands
== 1
5953 && i
.types
[0].bitfield
.vec_imm4
5954 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5955 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5956 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5957 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5958 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5960 if (i
.imm_operands
== 0)
5962 /* When there is no immediate operand, generate an 8bit
5963 immediate operand to encode the first operand. */
5964 exp
= &im_expressions
[i
.imm_operands
++];
5965 i
.op
[i
.operands
].imms
= exp
;
5966 i
.types
[i
.operands
] = imm8
;
5968 /* If VexW1 is set, the first operand is the source and
5969 the second operand is encoded in the immediate operand. */
5970 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5981 /* FMA swaps REG and NDS. */
5982 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5990 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5992 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5994 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5996 exp
->X_op
= O_constant
;
5997 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
5998 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6002 unsigned int imm_slot
;
6004 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6006 /* If VexW0 is set, the third operand is the source and
6007 the second operand is encoded in the immediate
6014 /* VexW1 is set, the second operand is the source and
6015 the third operand is encoded in the immediate
6021 if (i
.tm
.opcode_modifier
.immext
)
6023 /* When ImmExt is set, the immdiate byte is the last
6025 imm_slot
= i
.operands
- 1;
6033 /* Turn on Imm8 so that output_imm will generate it. */
6034 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6037 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6039 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6041 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6043 i
.op
[imm_slot
].imms
->X_add_number
6044 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6045 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6048 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6049 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6051 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6053 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6058 /* i.reg_operands MUST be the number of real register operands;
6059 implicit registers do not count. If there are 3 register
6060 operands, it must be a instruction with VexNDS. For a
6061 instruction with VexNDD, the destination register is encoded
6062 in VEX prefix. If there are 4 register operands, it must be
6063 a instruction with VEX prefix and 3 sources. */
6064 if (i
.mem_operands
== 0
6065 && ((i
.reg_operands
== 2
6066 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6067 || (i
.reg_operands
== 3
6068 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6069 || (i
.reg_operands
== 4 && vex_3_sources
)))
6077 /* When there are 3 operands, one of them may be immediate,
6078 which may be the first or the last operand. Otherwise,
6079 the first operand must be shift count register (cl) or it
6080 is an instruction with VexNDS. */
6081 gas_assert (i
.imm_operands
== 1
6082 || (i
.imm_operands
== 0
6083 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6084 || i
.types
[0].bitfield
.shiftcount
)));
6085 if (operand_type_check (i
.types
[0], imm
)
6086 || i
.types
[0].bitfield
.shiftcount
)
6092 /* When there are 4 operands, the first two must be 8bit
6093 immediate operands. The source operand will be the 3rd
6096 For instructions with VexNDS, if the first operand
6097 an imm8, the source operand is the 2nd one. If the last
6098 operand is imm8, the source operand is the first one. */
6099 gas_assert ((i
.imm_operands
== 2
6100 && i
.types
[0].bitfield
.imm8
6101 && i
.types
[1].bitfield
.imm8
)
6102 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6103 && i
.imm_operands
== 1
6104 && (i
.types
[0].bitfield
.imm8
6105 || i
.types
[i
.operands
- 1].bitfield
.imm8
6107 if (i
.imm_operands
== 2)
6111 if (i
.types
[0].bitfield
.imm8
)
6118 if (i
.tm
.opcode_modifier
.evex
)
6120 /* For EVEX instructions, when there are 5 operands, the
6121 first one must be immediate operand. If the second one
6122 is immediate operand, the source operand is the 3th
6123 one. If the last one is immediate operand, the source
6124 operand is the 2nd one. */
6125 gas_assert (i
.imm_operands
== 2
6126 && i
.tm
.opcode_modifier
.sae
6127 && operand_type_check (i
.types
[0], imm
));
6128 if (operand_type_check (i
.types
[1], imm
))
6130 else if (operand_type_check (i
.types
[4], imm
))
6144 /* RC/SAE operand could be between DEST and SRC. That happens
6145 when one operand is GPR and the other one is XMM/YMM/ZMM
6147 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6150 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6152 /* For instructions with VexNDS, the register-only source
6153 operand must be 32/64bit integer, XMM, YMM or ZMM
6154 register. It is encoded in VEX prefix. We need to
6155 clear RegMem bit before calling operand_type_equal. */
6157 i386_operand_type op
;
6160 /* Check register-only source operand when two source
6161 operands are swapped. */
6162 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6163 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6171 op
= i
.tm
.operand_types
[vvvv
];
6172 op
.bitfield
.regmem
= 0;
6173 if ((dest
+ 1) >= i
.operands
6174 || (!op
.bitfield
.reg32
6175 && op
.bitfield
.reg64
6176 && !operand_type_equal (&op
, ®xmm
)
6177 && !operand_type_equal (&op
, ®ymm
)
6178 && !operand_type_equal (&op
, ®zmm
)
6179 && !operand_type_equal (&op
, ®mask
)))
6181 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6187 /* One of the register operands will be encoded in the i.tm.reg
6188 field, the other in the combined i.tm.mode and i.tm.regmem
6189 fields. If no form of this instruction supports a memory
6190 destination operand, then we assume the source operand may
6191 sometimes be a memory operand and so we need to store the
6192 destination in the i.rm.reg field. */
6193 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6194 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6196 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6197 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6198 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6200 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6202 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6204 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6209 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6210 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6211 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6213 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6215 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6217 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6220 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6222 if (!i
.types
[0].bitfield
.control
6223 && !i
.types
[1].bitfield
.control
)
6225 i
.rex
&= ~(REX_R
| REX_B
);
6226 add_prefix (LOCK_PREFIX_OPCODE
);
6230 { /* If it's not 2 reg operands... */
6235 unsigned int fake_zero_displacement
= 0;
6238 for (op
= 0; op
< i
.operands
; op
++)
6239 if (operand_type_check (i
.types
[op
], anymem
))
6241 gas_assert (op
< i
.operands
);
6243 if (i
.tm
.opcode_modifier
.vecsib
)
6245 if (i
.index_reg
->reg_num
== RegEiz
6246 || i
.index_reg
->reg_num
== RegRiz
)
6249 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6252 i
.sib
.base
= NO_BASE_REGISTER
;
6253 i
.sib
.scale
= i
.log2_scale_factor
;
6254 /* No Vec_Disp8 if there is no base. */
6255 i
.types
[op
].bitfield
.vec_disp8
= 0;
6256 i
.types
[op
].bitfield
.disp8
= 0;
6257 i
.types
[op
].bitfield
.disp16
= 0;
6258 i
.types
[op
].bitfield
.disp64
= 0;
6259 if (flag_code
!= CODE_64BIT
)
6261 /* Must be 32 bit */
6262 i
.types
[op
].bitfield
.disp32
= 1;
6263 i
.types
[op
].bitfield
.disp32s
= 0;
6267 i
.types
[op
].bitfield
.disp32
= 0;
6268 i
.types
[op
].bitfield
.disp32s
= 1;
6271 i
.sib
.index
= i
.index_reg
->reg_num
;
6272 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6274 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6280 if (i
.base_reg
== 0)
6283 if (!i
.disp_operands
)
6285 fake_zero_displacement
= 1;
6286 /* Instructions with VSIB byte need 32bit displacement
6287 if there is no base register. */
6288 if (i
.tm
.opcode_modifier
.vecsib
)
6289 i
.types
[op
].bitfield
.disp32
= 1;
6291 if (i
.index_reg
== 0)
6293 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6294 /* Operand is just <disp> */
6295 if (flag_code
== CODE_64BIT
)
6297 /* 64bit mode overwrites the 32bit absolute
6298 addressing by RIP relative addressing and
6299 absolute addressing is encoded by one of the
6300 redundant SIB forms. */
6301 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6302 i
.sib
.base
= NO_BASE_REGISTER
;
6303 i
.sib
.index
= NO_INDEX_REGISTER
;
6304 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6305 ? disp32s
: disp32
);
6307 else if ((flag_code
== CODE_16BIT
)
6308 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6310 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6311 i
.types
[op
] = disp16
;
6315 i
.rm
.regmem
= NO_BASE_REGISTER
;
6316 i
.types
[op
] = disp32
;
6319 else if (!i
.tm
.opcode_modifier
.vecsib
)
6321 /* !i.base_reg && i.index_reg */
6322 if (i
.index_reg
->reg_num
== RegEiz
6323 || i
.index_reg
->reg_num
== RegRiz
)
6324 i
.sib
.index
= NO_INDEX_REGISTER
;
6326 i
.sib
.index
= i
.index_reg
->reg_num
;
6327 i
.sib
.base
= NO_BASE_REGISTER
;
6328 i
.sib
.scale
= i
.log2_scale_factor
;
6329 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6330 /* No Vec_Disp8 if there is no base. */
6331 i
.types
[op
].bitfield
.vec_disp8
= 0;
6332 i
.types
[op
].bitfield
.disp8
= 0;
6333 i
.types
[op
].bitfield
.disp16
= 0;
6334 i
.types
[op
].bitfield
.disp64
= 0;
6335 if (flag_code
!= CODE_64BIT
)
6337 /* Must be 32 bit */
6338 i
.types
[op
].bitfield
.disp32
= 1;
6339 i
.types
[op
].bitfield
.disp32s
= 0;
6343 i
.types
[op
].bitfield
.disp32
= 0;
6344 i
.types
[op
].bitfield
.disp32s
= 1;
6346 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6350 /* RIP addressing for 64bit mode. */
6351 else if (i
.base_reg
->reg_num
== RegRip
||
6352 i
.base_reg
->reg_num
== RegEip
)
6354 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6355 i
.rm
.regmem
= NO_BASE_REGISTER
;
6356 i
.types
[op
].bitfield
.disp8
= 0;
6357 i
.types
[op
].bitfield
.disp16
= 0;
6358 i
.types
[op
].bitfield
.disp32
= 0;
6359 i
.types
[op
].bitfield
.disp32s
= 1;
6360 i
.types
[op
].bitfield
.disp64
= 0;
6361 i
.types
[op
].bitfield
.vec_disp8
= 0;
6362 i
.flags
[op
] |= Operand_PCrel
;
6363 if (! i
.disp_operands
)
6364 fake_zero_displacement
= 1;
6366 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6368 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6369 switch (i
.base_reg
->reg_num
)
6372 if (i
.index_reg
== 0)
6374 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6375 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6379 if (i
.index_reg
== 0)
6382 if (operand_type_check (i
.types
[op
], disp
) == 0)
6384 /* fake (%bp) into 0(%bp) */
6385 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6386 i
.types
[op
].bitfield
.vec_disp8
= 1;
6388 i
.types
[op
].bitfield
.disp8
= 1;
6389 fake_zero_displacement
= 1;
6392 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6393 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6395 default: /* (%si) -> 4 or (%di) -> 5 */
6396 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6398 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6400 else /* i.base_reg and 32/64 bit mode */
6402 if (flag_code
== CODE_64BIT
6403 && operand_type_check (i
.types
[op
], disp
))
6405 i386_operand_type temp
;
6406 operand_type_set (&temp
, 0);
6407 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6408 temp
.bitfield
.vec_disp8
6409 = i
.types
[op
].bitfield
.vec_disp8
;
6411 if (i
.prefix
[ADDR_PREFIX
] == 0)
6412 i
.types
[op
].bitfield
.disp32s
= 1;
6414 i
.types
[op
].bitfield
.disp32
= 1;
6417 if (!i
.tm
.opcode_modifier
.vecsib
)
6418 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6419 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6421 i
.sib
.base
= i
.base_reg
->reg_num
;
6422 /* x86-64 ignores REX prefix bit here to avoid decoder
6424 if (!(i
.base_reg
->reg_flags
& RegRex
)
6425 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6426 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6428 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6430 fake_zero_displacement
= 1;
6431 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6432 i
.types
[op
].bitfield
.vec_disp8
= 1;
6434 i
.types
[op
].bitfield
.disp8
= 1;
6436 i
.sib
.scale
= i
.log2_scale_factor
;
6437 if (i
.index_reg
== 0)
6439 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6440 /* <disp>(%esp) becomes two byte modrm with no index
6441 register. We've already stored the code for esp
6442 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6443 Any base register besides %esp will not use the
6444 extra modrm byte. */
6445 i
.sib
.index
= NO_INDEX_REGISTER
;
6447 else if (!i
.tm
.opcode_modifier
.vecsib
)
6449 if (i
.index_reg
->reg_num
== RegEiz
6450 || i
.index_reg
->reg_num
== RegRiz
)
6451 i
.sib
.index
= NO_INDEX_REGISTER
;
6453 i
.sib
.index
= i
.index_reg
->reg_num
;
6454 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6455 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6460 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6461 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6465 if (!fake_zero_displacement
6469 fake_zero_displacement
= 1;
6470 if (i
.disp_encoding
== disp_encoding_8bit
)
6471 i
.types
[op
].bitfield
.disp8
= 1;
6473 i
.types
[op
].bitfield
.disp32
= 1;
6475 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6479 if (fake_zero_displacement
)
6481 /* Fakes a zero displacement assuming that i.types[op]
6482 holds the correct displacement size. */
6485 gas_assert (i
.op
[op
].disps
== 0);
6486 exp
= &disp_expressions
[i
.disp_operands
++];
6487 i
.op
[op
].disps
= exp
;
6488 exp
->X_op
= O_constant
;
6489 exp
->X_add_number
= 0;
6490 exp
->X_add_symbol
= (symbolS
*) 0;
6491 exp
->X_op_symbol
= (symbolS
*) 0;
6499 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6501 if (operand_type_check (i
.types
[0], imm
))
6502 i
.vex
.register_specifier
= NULL
;
6505 /* VEX.vvvv encodes one of the sources when the first
6506 operand is not an immediate. */
6507 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6508 i
.vex
.register_specifier
= i
.op
[0].regs
;
6510 i
.vex
.register_specifier
= i
.op
[1].regs
;
6513 /* Destination is a XMM register encoded in the ModRM.reg
6515 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6516 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6519 /* ModRM.rm and VEX.B encodes the other source. */
6520 if (!i
.mem_operands
)
6524 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6525 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6527 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6529 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6533 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6535 i
.vex
.register_specifier
= i
.op
[2].regs
;
6536 if (!i
.mem_operands
)
6539 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6540 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6544 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6545 (if any) based on i.tm.extension_opcode. Again, we must be
6546 careful to make sure that segment/control/debug/test/MMX
6547 registers are coded into the i.rm.reg field. */
6548 else if (i
.reg_operands
)
6551 unsigned int vex_reg
= ~0;
6553 for (op
= 0; op
< i
.operands
; op
++)
6554 if (i
.types
[op
].bitfield
.reg8
6555 || i
.types
[op
].bitfield
.reg16
6556 || i
.types
[op
].bitfield
.reg32
6557 || i
.types
[op
].bitfield
.reg64
6558 || i
.types
[op
].bitfield
.regmmx
6559 || i
.types
[op
].bitfield
.regxmm
6560 || i
.types
[op
].bitfield
.regymm
6561 || i
.types
[op
].bitfield
.regbnd
6562 || i
.types
[op
].bitfield
.regzmm
6563 || i
.types
[op
].bitfield
.regmask
6564 || i
.types
[op
].bitfield
.sreg2
6565 || i
.types
[op
].bitfield
.sreg3
6566 || i
.types
[op
].bitfield
.control
6567 || i
.types
[op
].bitfield
.debug
6568 || i
.types
[op
].bitfield
.test
)
6573 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6575 /* For instructions with VexNDS, the register-only
6576 source operand is encoded in VEX prefix. */
6577 gas_assert (mem
!= (unsigned int) ~0);
6582 gas_assert (op
< i
.operands
);
6586 /* Check register-only source operand when two source
6587 operands are swapped. */
6588 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6589 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6593 gas_assert (mem
== (vex_reg
+ 1)
6594 && op
< i
.operands
);
6599 gas_assert (vex_reg
< i
.operands
);
6603 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6605 /* For instructions with VexNDD, the register destination
6606 is encoded in VEX prefix. */
6607 if (i
.mem_operands
== 0)
6609 /* There is no memory operand. */
6610 gas_assert ((op
+ 2) == i
.operands
);
6615 /* There are only 2 operands. */
6616 gas_assert (op
< 2 && i
.operands
== 2);
6621 gas_assert (op
< i
.operands
);
6623 if (vex_reg
!= (unsigned int) ~0)
6625 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6627 if (type
->bitfield
.reg32
!= 1
6628 && type
->bitfield
.reg64
!= 1
6629 && !operand_type_equal (type
, ®xmm
)
6630 && !operand_type_equal (type
, ®ymm
)
6631 && !operand_type_equal (type
, ®zmm
)
6632 && !operand_type_equal (type
, ®mask
))
6635 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6638 /* Don't set OP operand twice. */
6641 /* If there is an extension opcode to put here, the
6642 register number must be put into the regmem field. */
6643 if (i
.tm
.extension_opcode
!= None
)
6645 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6646 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6648 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6653 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6654 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6656 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6661 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6662 must set it to 3 to indicate this is a register operand
6663 in the regmem field. */
6664 if (!i
.mem_operands
)
6668 /* Fill in i.rm.reg field with extension opcode (if any). */
6669 if (i
.tm
.extension_opcode
!= None
)
6670 i
.rm
.reg
= i
.tm
.extension_opcode
;
6676 output_branch (void)
6682 relax_substateT subtype
;
6686 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6687 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6690 if (i
.prefix
[DATA_PREFIX
] != 0)
6696 /* Pentium4 branch hints. */
6697 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6698 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6703 if (i
.prefix
[REX_PREFIX
] != 0)
6709 /* BND prefixed jump. */
6710 if (i
.prefix
[BND_PREFIX
] != 0)
6712 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6716 if (i
.prefixes
!= 0 && !intel_syntax
)
6717 as_warn (_("skipping prefixes on this instruction"));
6719 /* It's always a symbol; End frag & setup for relax.
6720 Make sure there is enough room in this frag for the largest
6721 instruction we may generate in md_convert_frag. This is 2
6722 bytes for the opcode and room for the prefix and largest
6724 frag_grow (prefix
+ 2 + 4);
6725 /* Prefix and 1 opcode byte go in fr_fix. */
6726 p
= frag_more (prefix
+ 1);
6727 if (i
.prefix
[DATA_PREFIX
] != 0)
6728 *p
++ = DATA_PREFIX_OPCODE
;
6729 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6730 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6731 *p
++ = i
.prefix
[SEG_PREFIX
];
6732 if (i
.prefix
[REX_PREFIX
] != 0)
6733 *p
++ = i
.prefix
[REX_PREFIX
];
6734 *p
= i
.tm
.base_opcode
;
6736 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6737 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6738 else if (cpu_arch_flags
.bitfield
.cpui386
)
6739 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6741 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6744 sym
= i
.op
[0].disps
->X_add_symbol
;
6745 off
= i
.op
[0].disps
->X_add_number
;
6747 if (i
.op
[0].disps
->X_op
!= O_constant
6748 && i
.op
[0].disps
->X_op
!= O_symbol
)
6750 /* Handle complex expressions. */
6751 sym
= make_expr_symbol (i
.op
[0].disps
);
6755 /* 1 possible extra opcode + 4 byte displacement go in var part.
6756 Pass reloc in fr_var. */
6757 frag_var (rs_machine_dependent
, 5,
6759 || i
.reloc
[0] != NO_RELOC
6760 || (i
.bnd_prefix
== NULL
&& !add_bnd_prefix
))
6762 : BFD_RELOC_X86_64_PC32_BND
),
6763 subtype
, sym
, off
, p
);
6773 if (i
.tm
.opcode_modifier
.jumpbyte
)
6775 /* This is a loop or jecxz type instruction. */
6777 if (i
.prefix
[ADDR_PREFIX
] != 0)
6779 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6782 /* Pentium4 branch hints. */
6783 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6784 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6786 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6795 if (flag_code
== CODE_16BIT
)
6798 if (i
.prefix
[DATA_PREFIX
] != 0)
6800 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6810 if (i
.prefix
[REX_PREFIX
] != 0)
6812 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6816 /* BND prefixed jump. */
6817 if (i
.prefix
[BND_PREFIX
] != 0)
6819 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6823 if (i
.prefixes
!= 0 && !intel_syntax
)
6824 as_warn (_("skipping prefixes on this instruction"));
6826 p
= frag_more (i
.tm
.opcode_length
+ size
);
6827 switch (i
.tm
.opcode_length
)
6830 *p
++ = i
.tm
.base_opcode
>> 8;
6832 *p
++ = i
.tm
.base_opcode
;
6838 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6839 i
.op
[0].disps
, 1, reloc (size
, 1, 1,
6840 (i
.bnd_prefix
!= NULL
6844 /* All jumps handled here are signed, but don't use a signed limit
6845 check for 32 and 16 bit jumps as we want to allow wrap around at
6846 4G and 64k respectively. */
6848 fixP
->fx_signed
= 1;
6852 output_interseg_jump (void)
6860 if (flag_code
== CODE_16BIT
)
6864 if (i
.prefix
[DATA_PREFIX
] != 0)
6870 if (i
.prefix
[REX_PREFIX
] != 0)
6880 if (i
.prefixes
!= 0 && !intel_syntax
)
6881 as_warn (_("skipping prefixes on this instruction"));
6883 /* 1 opcode; 2 segment; offset */
6884 p
= frag_more (prefix
+ 1 + 2 + size
);
6886 if (i
.prefix
[DATA_PREFIX
] != 0)
6887 *p
++ = DATA_PREFIX_OPCODE
;
6889 if (i
.prefix
[REX_PREFIX
] != 0)
6890 *p
++ = i
.prefix
[REX_PREFIX
];
6892 *p
++ = i
.tm
.base_opcode
;
6893 if (i
.op
[1].imms
->X_op
== O_constant
)
6895 offsetT n
= i
.op
[1].imms
->X_add_number
;
6898 && !fits_in_unsigned_word (n
)
6899 && !fits_in_signed_word (n
))
6901 as_bad (_("16-bit jump out of range"));
6904 md_number_to_chars (p
, n
, size
);
6907 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6908 i
.op
[1].imms
, 0, reloc (size
, 0, 0, 0, i
.reloc
[1]));
6909 if (i
.op
[0].imms
->X_op
!= O_constant
)
6910 as_bad (_("can't handle non absolute segment in `%s'"),
6912 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6918 fragS
*insn_start_frag
;
6919 offsetT insn_start_off
;
6921 /* Tie dwarf2 debug info to the address at the start of the insn.
6922 We can't do this after the insn has been output as the current
6923 frag may have been closed off. eg. by frag_var. */
6924 dwarf2_emit_insn (0);
6926 insn_start_frag
= frag_now
;
6927 insn_start_off
= frag_now_fix ();
6930 if (i
.tm
.opcode_modifier
.jump
)
6932 else if (i
.tm
.opcode_modifier
.jumpbyte
6933 || i
.tm
.opcode_modifier
.jumpdword
)
6935 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6936 output_interseg_jump ();
6939 /* Output normal instructions here. */
6943 unsigned int prefix
;
6945 /* Some processors fail on LOCK prefix. This options makes
6946 assembler ignore LOCK prefix and serves as a workaround. */
6947 if (omit_lock_prefix
)
6949 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
6951 i
.prefix
[LOCK_PREFIX
] = 0;
6954 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6955 don't need the explicit prefix. */
6956 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6958 switch (i
.tm
.opcode_length
)
6961 if (i
.tm
.base_opcode
& 0xff000000)
6963 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6968 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6970 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6971 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6974 if (prefix
!= REPE_PREFIX_OPCODE
6975 || (i
.prefix
[REP_PREFIX
]
6976 != REPE_PREFIX_OPCODE
))
6977 add_prefix (prefix
);
6980 add_prefix (prefix
);
6989 /* The prefix bytes. */
6990 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6992 FRAG_APPEND_1_CHAR (*q
);
6996 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7001 /* REX byte is encoded in VEX prefix. */
7005 FRAG_APPEND_1_CHAR (*q
);
7008 /* There should be no other prefixes for instructions
7013 /* For EVEX instructions i.vrex should become 0 after
7014 build_evex_prefix. For VEX instructions upper 16 registers
7015 aren't available, so VREX should be 0. */
7018 /* Now the VEX prefix. */
7019 p
= frag_more (i
.vex
.length
);
7020 for (j
= 0; j
< i
.vex
.length
; j
++)
7021 p
[j
] = i
.vex
.bytes
[j
];
7024 /* Now the opcode; be careful about word order here! */
7025 if (i
.tm
.opcode_length
== 1)
7027 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7031 switch (i
.tm
.opcode_length
)
7035 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7036 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7040 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7050 /* Put out high byte first: can't use md_number_to_chars! */
7051 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7052 *p
= i
.tm
.base_opcode
& 0xff;
7055 /* Now the modrm byte and sib byte (if present). */
7056 if (i
.tm
.opcode_modifier
.modrm
)
7058 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7061 /* If i.rm.regmem == ESP (4)
7062 && i.rm.mode != (Register mode)
7064 ==> need second modrm byte. */
7065 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7067 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7068 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7070 | i
.sib
.scale
<< 6));
7073 if (i
.disp_operands
)
7074 output_disp (insn_start_frag
, insn_start_off
);
7077 output_imm (insn_start_frag
, insn_start_off
);
7083 pi ("" /*line*/, &i
);
7085 #endif /* DEBUG386 */
7088 /* Return the size of the displacement operand N. */
7091 disp_size (unsigned int n
)
7095 /* Vec_Disp8 has to be 8bit. */
7096 if (i
.types
[n
].bitfield
.vec_disp8
)
7098 else if (i
.types
[n
].bitfield
.disp64
)
7100 else if (i
.types
[n
].bitfield
.disp8
)
7102 else if (i
.types
[n
].bitfield
.disp16
)
7107 /* Return the size of the immediate operand N. */
7110 imm_size (unsigned int n
)
7113 if (i
.types
[n
].bitfield
.imm64
)
7115 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7117 else if (i
.types
[n
].bitfield
.imm16
)
7123 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7128 for (n
= 0; n
< i
.operands
; n
++)
7130 if (i
.types
[n
].bitfield
.vec_disp8
7131 || operand_type_check (i
.types
[n
], disp
))
7133 if (i
.op
[n
].disps
->X_op
== O_constant
)
7135 int size
= disp_size (n
);
7136 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7138 if (i
.types
[n
].bitfield
.vec_disp8
)
7140 val
= offset_in_range (val
, size
);
7141 p
= frag_more (size
);
7142 md_number_to_chars (p
, val
, size
);
7146 enum bfd_reloc_code_real reloc_type
;
7147 int size
= disp_size (n
);
7148 int sign
= i
.types
[n
].bitfield
.disp32s
;
7149 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7151 /* We can't have 8 bit displacement here. */
7152 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7154 /* The PC relative address is computed relative
7155 to the instruction boundary, so in case immediate
7156 fields follows, we need to adjust the value. */
7157 if (pcrel
&& i
.imm_operands
)
7162 for (n1
= 0; n1
< i
.operands
; n1
++)
7163 if (operand_type_check (i
.types
[n1
], imm
))
7165 /* Only one immediate is allowed for PC
7166 relative address. */
7167 gas_assert (sz
== 0);
7169 i
.op
[n
].disps
->X_add_number
-= sz
;
7171 /* We should find the immediate. */
7172 gas_assert (sz
!= 0);
7175 p
= frag_more (size
);
7176 reloc_type
= reloc (size
, pcrel
, sign
,
7177 (i
.bnd_prefix
!= NULL
7181 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7182 && (((reloc_type
== BFD_RELOC_32
7183 || reloc_type
== BFD_RELOC_X86_64_32S
7184 || (reloc_type
== BFD_RELOC_64
7186 && (i
.op
[n
].disps
->X_op
== O_symbol
7187 || (i
.op
[n
].disps
->X_op
== O_add
7188 && ((symbol_get_value_expression
7189 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7191 || reloc_type
== BFD_RELOC_32_PCREL
))
7195 if (insn_start_frag
== frag_now
)
7196 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7201 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7202 for (fr
= insn_start_frag
->fr_next
;
7203 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7205 add
+= p
- frag_now
->fr_literal
;
7210 reloc_type
= BFD_RELOC_386_GOTPC
;
7211 i
.op
[n
].imms
->X_add_number
+= add
;
7213 else if (reloc_type
== BFD_RELOC_64
)
7214 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7216 /* Don't do the adjustment for x86-64, as there
7217 the pcrel addressing is relative to the _next_
7218 insn, and that is taken care of in other code. */
7219 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7221 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7222 i
.op
[n
].disps
, pcrel
, reloc_type
);
7229 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7234 for (n
= 0; n
< i
.operands
; n
++)
7236 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7237 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7240 if (operand_type_check (i
.types
[n
], imm
))
7242 if (i
.op
[n
].imms
->X_op
== O_constant
)
7244 int size
= imm_size (n
);
7247 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7249 p
= frag_more (size
);
7250 md_number_to_chars (p
, val
, size
);
7254 /* Not absolute_section.
7255 Need a 32-bit fixup (don't support 8bit
7256 non-absolute imms). Try to support other
7258 enum bfd_reloc_code_real reloc_type
;
7259 int size
= imm_size (n
);
7262 if (i
.types
[n
].bitfield
.imm32s
7263 && (i
.suffix
== QWORD_MNEM_SUFFIX
7264 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7269 p
= frag_more (size
);
7270 reloc_type
= reloc (size
, 0, sign
, 0, i
.reloc
[n
]);
7272 /* This is tough to explain. We end up with this one if we
7273 * have operands that look like
7274 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7275 * obtain the absolute address of the GOT, and it is strongly
7276 * preferable from a performance point of view to avoid using
7277 * a runtime relocation for this. The actual sequence of
7278 * instructions often look something like:
7283 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7285 * The call and pop essentially return the absolute address
7286 * of the label .L66 and store it in %ebx. The linker itself
7287 * will ultimately change the first operand of the addl so
7288 * that %ebx points to the GOT, but to keep things simple, the
7289 * .o file must have this operand set so that it generates not
7290 * the absolute address of .L66, but the absolute address of
7291 * itself. This allows the linker itself simply treat a GOTPC
7292 * relocation as asking for a pcrel offset to the GOT to be
7293 * added in, and the addend of the relocation is stored in the
7294 * operand field for the instruction itself.
7296 * Our job here is to fix the operand so that it would add
7297 * the correct offset so that %ebx would point to itself. The
7298 * thing that is tricky is that .-.L66 will point to the
7299 * beginning of the instruction, so we need to further modify
7300 * the operand so that it will point to itself. There are
7301 * other cases where you have something like:
7303 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7305 * and here no correction would be required. Internally in
7306 * the assembler we treat operands of this form as not being
7307 * pcrel since the '.' is explicitly mentioned, and I wonder
7308 * whether it would simplify matters to do it this way. Who
7309 * knows. In earlier versions of the PIC patches, the
7310 * pcrel_adjust field was used to store the correction, but
7311 * since the expression is not pcrel, I felt it would be
7312 * confusing to do it this way. */
7314 if ((reloc_type
== BFD_RELOC_32
7315 || reloc_type
== BFD_RELOC_X86_64_32S
7316 || reloc_type
== BFD_RELOC_64
)
7318 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7319 && (i
.op
[n
].imms
->X_op
== O_symbol
7320 || (i
.op
[n
].imms
->X_op
== O_add
7321 && ((symbol_get_value_expression
7322 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7327 if (insn_start_frag
== frag_now
)
7328 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7333 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7334 for (fr
= insn_start_frag
->fr_next
;
7335 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7337 add
+= p
- frag_now
->fr_literal
;
7341 reloc_type
= BFD_RELOC_386_GOTPC
;
7343 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7345 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7346 i
.op
[n
].imms
->X_add_number
+= add
;
7348 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7349 i
.op
[n
].imms
, 0, reloc_type
);
7355 /* x86_cons_fix_new is called via the expression parsing code when a
7356 reloc is needed. We use this hook to get the correct .got reloc. */
7357 static int cons_sign
= -1;
7360 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7361 expressionS
*exp
, bfd_reloc_code_real_type r
)
7363 r
= reloc (len
, 0, cons_sign
, 0, r
);
7366 if (exp
->X_op
== O_secrel
)
7368 exp
->X_op
= O_symbol
;
7369 r
= BFD_RELOC_32_SECREL
;
7373 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7376 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7377 purpose of the `.dc.a' internal pseudo-op. */
7380 x86_address_bytes (void)
7382 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7384 return stdoutput
->arch_info
->bits_per_address
/ 8;
7387 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7389 # define lex_got(reloc, adjust, types, bnd_prefix) NULL
7391 /* Parse operands of the form
7392 <symbol>@GOTOFF+<nnn>
7393 and similar .plt or .got references.
7395 If we find one, set up the correct relocation in RELOC and copy the
7396 input string, minus the `@GOTOFF' into a malloc'd buffer for
7397 parsing by the calling routine. Return this buffer, and if ADJUST
7398 is non-null set it to the length of the string we removed from the
7399 input line. Otherwise return NULL. */
7401 lex_got (enum bfd_reloc_code_real
*rel
,
7403 i386_operand_type
*types
,
7406 /* Some of the relocations depend on the size of what field is to
7407 be relocated. But in our callers i386_immediate and i386_displacement
7408 we don't yet know the operand size (this will be set by insn
7409 matching). Hence we record the word32 relocation here,
7410 and adjust the reloc according to the real size in reloc(). */
7411 static const struct {
7414 const enum bfd_reloc_code_real rel
[2];
7415 const i386_operand_type types64
;
7417 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7418 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7420 OPERAND_TYPE_IMM32_64
},
7422 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7423 BFD_RELOC_X86_64_PLTOFF64
},
7424 OPERAND_TYPE_IMM64
},
7425 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7426 BFD_RELOC_X86_64_PLT32
},
7427 OPERAND_TYPE_IMM32_32S_DISP32
},
7428 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7429 BFD_RELOC_X86_64_GOTPLT64
},
7430 OPERAND_TYPE_IMM64_DISP64
},
7431 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7432 BFD_RELOC_X86_64_GOTOFF64
},
7433 OPERAND_TYPE_IMM64_DISP64
},
7434 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7435 BFD_RELOC_X86_64_GOTPCREL
},
7436 OPERAND_TYPE_IMM32_32S_DISP32
},
7437 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7438 BFD_RELOC_X86_64_TLSGD
},
7439 OPERAND_TYPE_IMM32_32S_DISP32
},
7440 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7441 _dummy_first_bfd_reloc_code_real
},
7442 OPERAND_TYPE_NONE
},
7443 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7444 BFD_RELOC_X86_64_TLSLD
},
7445 OPERAND_TYPE_IMM32_32S_DISP32
},
7446 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7447 BFD_RELOC_X86_64_GOTTPOFF
},
7448 OPERAND_TYPE_IMM32_32S_DISP32
},
7449 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7450 BFD_RELOC_X86_64_TPOFF32
},
7451 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7452 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7453 _dummy_first_bfd_reloc_code_real
},
7454 OPERAND_TYPE_NONE
},
7455 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7456 BFD_RELOC_X86_64_DTPOFF32
},
7457 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7458 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7459 _dummy_first_bfd_reloc_code_real
},
7460 OPERAND_TYPE_NONE
},
7461 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7462 _dummy_first_bfd_reloc_code_real
},
7463 OPERAND_TYPE_NONE
},
7464 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7465 BFD_RELOC_X86_64_GOT32
},
7466 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7467 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7468 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7469 OPERAND_TYPE_IMM32_32S_DISP32
},
7470 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7471 BFD_RELOC_X86_64_TLSDESC_CALL
},
7472 OPERAND_TYPE_IMM32_32S_DISP32
},
7477 #if defined (OBJ_MAYBE_ELF)
7482 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7483 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7486 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7488 int len
= gotrel
[j
].len
;
7489 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7491 if (gotrel
[j
].rel
[object_64bit
] != 0)
7494 char *tmpbuf
, *past_reloc
;
7496 *rel
= gotrel
[j
].rel
[object_64bit
];
7500 if (flag_code
!= CODE_64BIT
)
7502 types
->bitfield
.imm32
= 1;
7503 types
->bitfield
.disp32
= 1;
7506 *types
= gotrel
[j
].types64
;
7509 if (j
!= 0 && GOT_symbol
== NULL
)
7510 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7512 /* The length of the first part of our input line. */
7513 first
= cp
- input_line_pointer
;
7515 /* The second part goes from after the reloc token until
7516 (and including) an end_of_line char or comma. */
7517 past_reloc
= cp
+ 1 + len
;
7519 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7521 second
= cp
+ 1 - past_reloc
;
7523 /* Allocate and copy string. The trailing NUL shouldn't
7524 be necessary, but be safe. */
7525 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7526 memcpy (tmpbuf
, input_line_pointer
, first
);
7527 if (second
!= 0 && *past_reloc
!= ' ')
7528 /* Replace the relocation token with ' ', so that
7529 errors like foo@GOTOFF1 will be detected. */
7530 tmpbuf
[first
++] = ' ';
7532 /* Increment length by 1 if the relocation token is
7537 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7538 tmpbuf
[first
+ second
] = '\0';
7539 if (bnd_prefix
&& *rel
== BFD_RELOC_X86_64_PLT32
)
7540 *rel
= BFD_RELOC_X86_64_PLT32_BND
;
7544 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7545 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7550 /* Might be a symbol version string. Don't as_bad here. */
7559 /* Parse operands of the form
7560 <symbol>@SECREL32+<nnn>
7562 If we find one, set up the correct relocation in RELOC and copy the
7563 input string, minus the `@SECREL32' into a malloc'd buffer for
7564 parsing by the calling routine. Return this buffer, and if ADJUST
7565 is non-null set it to the length of the string we removed from the
7566 input line. Otherwise return NULL.
7568 This function is copied from the ELF version above adjusted for PE targets. */
7571 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7572 int *adjust ATTRIBUTE_UNUSED
,
7573 i386_operand_type
*types
,
7574 int bnd_prefix ATTRIBUTE_UNUSED
)
7580 const enum bfd_reloc_code_real rel
[2];
7581 const i386_operand_type types64
;
7585 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7586 BFD_RELOC_32_SECREL
},
7587 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7593 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7594 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7597 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7599 int len
= gotrel
[j
].len
;
7601 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7603 if (gotrel
[j
].rel
[object_64bit
] != 0)
7606 char *tmpbuf
, *past_reloc
;
7608 *rel
= gotrel
[j
].rel
[object_64bit
];
7614 if (flag_code
!= CODE_64BIT
)
7616 types
->bitfield
.imm32
= 1;
7617 types
->bitfield
.disp32
= 1;
7620 *types
= gotrel
[j
].types64
;
7623 /* The length of the first part of our input line. */
7624 first
= cp
- input_line_pointer
;
7626 /* The second part goes from after the reloc token until
7627 (and including) an end_of_line char or comma. */
7628 past_reloc
= cp
+ 1 + len
;
7630 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7632 second
= cp
+ 1 - past_reloc
;
7634 /* Allocate and copy string. The trailing NUL shouldn't
7635 be necessary, but be safe. */
7636 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7637 memcpy (tmpbuf
, input_line_pointer
, first
);
7638 if (second
!= 0 && *past_reloc
!= ' ')
7639 /* Replace the relocation token with ' ', so that
7640 errors like foo@SECLREL321 will be detected. */
7641 tmpbuf
[first
++] = ' ';
7642 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7643 tmpbuf
[first
+ second
] = '\0';
7647 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7648 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7653 /* Might be a symbol version string. Don't as_bad here. */
7659 bfd_reloc_code_real_type
7660 x86_cons (expressionS
*exp
, int size
)
7662 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7664 intel_syntax
= -intel_syntax
;
7667 if (size
== 4 || (object_64bit
&& size
== 8))
7669 /* Handle @GOTOFF and the like in an expression. */
7671 char *gotfree_input_line
;
7674 save
= input_line_pointer
;
7675 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
, 0);
7676 if (gotfree_input_line
)
7677 input_line_pointer
= gotfree_input_line
;
7681 if (gotfree_input_line
)
7683 /* expression () has merrily parsed up to the end of line,
7684 or a comma - in the wrong buffer. Transfer how far
7685 input_line_pointer has moved to the right buffer. */
7686 input_line_pointer
= (save
7687 + (input_line_pointer
- gotfree_input_line
)
7689 free (gotfree_input_line
);
7690 if (exp
->X_op
== O_constant
7691 || exp
->X_op
== O_absent
7692 || exp
->X_op
== O_illegal
7693 || exp
->X_op
== O_register
7694 || exp
->X_op
== O_big
)
7696 char c
= *input_line_pointer
;
7697 *input_line_pointer
= 0;
7698 as_bad (_("missing or invalid expression `%s'"), save
);
7699 *input_line_pointer
= c
;
7706 intel_syntax
= -intel_syntax
;
7709 i386_intel_simplify (exp
);
7715 signed_cons (int size
)
7717 if (flag_code
== CODE_64BIT
)
7725 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7732 if (exp
.X_op
== O_symbol
)
7733 exp
.X_op
= O_secrel
;
7735 emit_expr (&exp
, 4);
7737 while (*input_line_pointer
++ == ',');
7739 input_line_pointer
--;
7740 demand_empty_rest_of_line ();
7744 /* Handle Vector operations. */
7747 check_VecOperations (char *op_string
, char *op_end
)
7749 const reg_entry
*mask
;
7754 && (op_end
== NULL
|| op_string
< op_end
))
7757 if (*op_string
== '{')
7761 /* Check broadcasts. */
7762 if (strncmp (op_string
, "1to", 3) == 0)
7767 goto duplicated_vec_op
;
7770 if (*op_string
== '8')
7771 bcst_type
= BROADCAST_1TO8
;
7772 else if (*op_string
== '4')
7773 bcst_type
= BROADCAST_1TO4
;
7774 else if (*op_string
== '2')
7775 bcst_type
= BROADCAST_1TO2
;
7776 else if (*op_string
== '1'
7777 && *(op_string
+1) == '6')
7779 bcst_type
= BROADCAST_1TO16
;
7784 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7789 broadcast_op
.type
= bcst_type
;
7790 broadcast_op
.operand
= this_operand
;
7791 i
.broadcast
= &broadcast_op
;
7793 /* Check masking operation. */
7794 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7796 /* k0 can't be used for write mask. */
7797 if (mask
->reg_num
== 0)
7799 as_bad (_("`%s' can't be used for write mask"),
7806 mask_op
.mask
= mask
;
7807 mask_op
.zeroing
= 0;
7808 mask_op
.operand
= this_operand
;
7814 goto duplicated_vec_op
;
7816 i
.mask
->mask
= mask
;
7818 /* Only "{z}" is allowed here. No need to check
7819 zeroing mask explicitly. */
7820 if (i
.mask
->operand
!= this_operand
)
7822 as_bad (_("invalid write mask `%s'"), saved
);
7829 /* Check zeroing-flag for masking operation. */
7830 else if (*op_string
== 'z')
7834 mask_op
.mask
= NULL
;
7835 mask_op
.zeroing
= 1;
7836 mask_op
.operand
= this_operand
;
7841 if (i
.mask
->zeroing
)
7844 as_bad (_("duplicated `%s'"), saved
);
7848 i
.mask
->zeroing
= 1;
7850 /* Only "{%k}" is allowed here. No need to check mask
7851 register explicitly. */
7852 if (i
.mask
->operand
!= this_operand
)
7854 as_bad (_("invalid zeroing-masking `%s'"),
7863 goto unknown_vec_op
;
7865 if (*op_string
!= '}')
7867 as_bad (_("missing `}' in `%s'"), saved
);
7874 /* We don't know this one. */
7875 as_bad (_("unknown vector operation: `%s'"), saved
);
7883 i386_immediate (char *imm_start
)
7885 char *save_input_line_pointer
;
7886 char *gotfree_input_line
;
7889 i386_operand_type types
;
7891 operand_type_set (&types
, ~0);
7893 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7895 as_bad (_("at most %d immediate operands are allowed"),
7896 MAX_IMMEDIATE_OPERANDS
);
7900 exp
= &im_expressions
[i
.imm_operands
++];
7901 i
.op
[this_operand
].imms
= exp
;
7903 if (is_space_char (*imm_start
))
7906 save_input_line_pointer
= input_line_pointer
;
7907 input_line_pointer
= imm_start
;
7909 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
,
7910 (i
.bnd_prefix
!= NULL
7911 || add_bnd_prefix
));
7912 if (gotfree_input_line
)
7913 input_line_pointer
= gotfree_input_line
;
7915 exp_seg
= expression (exp
);
7919 /* Handle vector operations. */
7920 if (*input_line_pointer
== '{')
7922 input_line_pointer
= check_VecOperations (input_line_pointer
,
7924 if (input_line_pointer
== NULL
)
7928 if (*input_line_pointer
)
7929 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7931 input_line_pointer
= save_input_line_pointer
;
7932 if (gotfree_input_line
)
7934 free (gotfree_input_line
);
7936 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7937 exp
->X_op
= O_illegal
;
7940 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7944 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7945 i386_operand_type types
, const char *imm_start
)
7947 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7950 as_bad (_("missing or invalid immediate expression `%s'"),
7954 else if (exp
->X_op
== O_constant
)
7956 /* Size it properly later. */
7957 i
.types
[this_operand
].bitfield
.imm64
= 1;
7958 /* If not 64bit, sign extend val. */
7959 if (flag_code
!= CODE_64BIT
7960 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7962 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7964 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7965 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7966 && exp_seg
!= absolute_section
7967 && exp_seg
!= text_section
7968 && exp_seg
!= data_section
7969 && exp_seg
!= bss_section
7970 && exp_seg
!= undefined_section
7971 && !bfd_is_com_section (exp_seg
))
7973 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7977 else if (!intel_syntax
&& exp
->X_op
== O_register
)
7980 as_bad (_("illegal immediate register operand %s"), imm_start
);
7985 /* This is an address. The size of the address will be
7986 determined later, depending on destination register,
7987 suffix, or the default for the section. */
7988 i
.types
[this_operand
].bitfield
.imm8
= 1;
7989 i
.types
[this_operand
].bitfield
.imm16
= 1;
7990 i
.types
[this_operand
].bitfield
.imm32
= 1;
7991 i
.types
[this_operand
].bitfield
.imm32s
= 1;
7992 i
.types
[this_operand
].bitfield
.imm64
= 1;
7993 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8001 i386_scale (char *scale
)
8004 char *save
= input_line_pointer
;
8006 input_line_pointer
= scale
;
8007 val
= get_absolute_expression ();
8012 i
.log2_scale_factor
= 0;
8015 i
.log2_scale_factor
= 1;
8018 i
.log2_scale_factor
= 2;
8021 i
.log2_scale_factor
= 3;
8025 char sep
= *input_line_pointer
;
8027 *input_line_pointer
= '\0';
8028 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8030 *input_line_pointer
= sep
;
8031 input_line_pointer
= save
;
8035 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8037 as_warn (_("scale factor of %d without an index register"),
8038 1 << i
.log2_scale_factor
);
8039 i
.log2_scale_factor
= 0;
8041 scale
= input_line_pointer
;
8042 input_line_pointer
= save
;
8047 i386_displacement (char *disp_start
, char *disp_end
)
8051 char *save_input_line_pointer
;
8052 char *gotfree_input_line
;
8054 i386_operand_type bigdisp
, types
= anydisp
;
8057 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8059 as_bad (_("at most %d displacement operands are allowed"),
8060 MAX_MEMORY_OPERANDS
);
8064 operand_type_set (&bigdisp
, 0);
8065 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8066 || (!current_templates
->start
->opcode_modifier
.jump
8067 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8069 bigdisp
.bitfield
.disp32
= 1;
8070 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8071 if (flag_code
== CODE_64BIT
)
8075 bigdisp
.bitfield
.disp32s
= 1;
8076 bigdisp
.bitfield
.disp64
= 1;
8079 else if ((flag_code
== CODE_16BIT
) ^ override
)
8081 bigdisp
.bitfield
.disp32
= 0;
8082 bigdisp
.bitfield
.disp16
= 1;
8087 /* For PC-relative branches, the width of the displacement
8088 is dependent upon data size, not address size. */
8089 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8090 if (flag_code
== CODE_64BIT
)
8092 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8093 bigdisp
.bitfield
.disp16
= 1;
8096 bigdisp
.bitfield
.disp32
= 1;
8097 bigdisp
.bitfield
.disp32s
= 1;
8103 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8105 : LONG_MNEM_SUFFIX
));
8106 bigdisp
.bitfield
.disp32
= 1;
8107 if ((flag_code
== CODE_16BIT
) ^ override
)
8109 bigdisp
.bitfield
.disp32
= 0;
8110 bigdisp
.bitfield
.disp16
= 1;
8114 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8117 exp
= &disp_expressions
[i
.disp_operands
];
8118 i
.op
[this_operand
].disps
= exp
;
8120 save_input_line_pointer
= input_line_pointer
;
8121 input_line_pointer
= disp_start
;
8122 END_STRING_AND_SAVE (disp_end
);
8124 #ifndef GCC_ASM_O_HACK
8125 #define GCC_ASM_O_HACK 0
8128 END_STRING_AND_SAVE (disp_end
+ 1);
8129 if (i
.types
[this_operand
].bitfield
.baseIndex
8130 && displacement_string_end
[-1] == '+')
8132 /* This hack is to avoid a warning when using the "o"
8133 constraint within gcc asm statements.
8136 #define _set_tssldt_desc(n,addr,limit,type) \
8137 __asm__ __volatile__ ( \
8139 "movw %w1,2+%0\n\t" \
8141 "movb %b1,4+%0\n\t" \
8142 "movb %4,5+%0\n\t" \
8143 "movb $0,6+%0\n\t" \
8144 "movb %h1,7+%0\n\t" \
8146 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8148 This works great except that the output assembler ends
8149 up looking a bit weird if it turns out that there is
8150 no offset. You end up producing code that looks like:
8163 So here we provide the missing zero. */
8165 *displacement_string_end
= '0';
8168 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
,
8169 (i
.bnd_prefix
!= NULL
8170 || add_bnd_prefix
));
8171 if (gotfree_input_line
)
8172 input_line_pointer
= gotfree_input_line
;
8174 exp_seg
= expression (exp
);
8177 if (*input_line_pointer
)
8178 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8180 RESTORE_END_STRING (disp_end
+ 1);
8182 input_line_pointer
= save_input_line_pointer
;
8183 if (gotfree_input_line
)
8185 free (gotfree_input_line
);
8187 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8188 exp
->X_op
= O_illegal
;
8191 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8193 RESTORE_END_STRING (disp_end
);
8199 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8200 i386_operand_type types
, const char *disp_start
)
8202 i386_operand_type bigdisp
;
8205 /* We do this to make sure that the section symbol is in
8206 the symbol table. We will ultimately change the relocation
8207 to be relative to the beginning of the section. */
8208 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8209 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8210 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8212 if (exp
->X_op
!= O_symbol
)
8215 if (S_IS_LOCAL (exp
->X_add_symbol
)
8216 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8217 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8218 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8219 exp
->X_op
= O_subtract
;
8220 exp
->X_op_symbol
= GOT_symbol
;
8221 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8222 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8223 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8224 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8226 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8229 else if (exp
->X_op
== O_absent
8230 || exp
->X_op
== O_illegal
8231 || exp
->X_op
== O_big
)
8234 as_bad (_("missing or invalid displacement expression `%s'"),
8239 else if (flag_code
== CODE_64BIT
8240 && !i
.prefix
[ADDR_PREFIX
]
8241 && exp
->X_op
== O_constant
)
8243 /* Since displacement is signed extended to 64bit, don't allow
8244 disp32 and turn off disp32s if they are out of range. */
8245 i
.types
[this_operand
].bitfield
.disp32
= 0;
8246 if (!fits_in_signed_long (exp
->X_add_number
))
8248 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8249 if (i
.types
[this_operand
].bitfield
.baseindex
)
8251 as_bad (_("0x%lx out range of signed 32bit displacement"),
8252 (long) exp
->X_add_number
);
8258 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8259 else if (exp
->X_op
!= O_constant
8260 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8261 && exp_seg
!= absolute_section
8262 && exp_seg
!= text_section
8263 && exp_seg
!= data_section
8264 && exp_seg
!= bss_section
8265 && exp_seg
!= undefined_section
8266 && !bfd_is_com_section (exp_seg
))
8268 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8273 /* Check if this is a displacement only operand. */
8274 bigdisp
= i
.types
[this_operand
];
8275 bigdisp
.bitfield
.disp8
= 0;
8276 bigdisp
.bitfield
.disp16
= 0;
8277 bigdisp
.bitfield
.disp32
= 0;
8278 bigdisp
.bitfield
.disp32s
= 0;
8279 bigdisp
.bitfield
.disp64
= 0;
8280 if (operand_type_all_zero (&bigdisp
))
8281 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8287 /* Make sure the memory operand we've been dealt is valid.
8288 Return 1 on success, 0 on a failure. */
8291 i386_index_check (const char *operand_string
)
8293 const char *kind
= "base/index";
8294 enum flag_code addr_mode
;
8296 if (i
.prefix
[ADDR_PREFIX
])
8297 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8300 addr_mode
= flag_code
;
8302 #if INFER_ADDR_PREFIX
8303 if (i
.mem_operands
== 0)
8305 /* Infer address prefix from the first memory operand. */
8306 const reg_entry
*addr_reg
= i
.base_reg
;
8308 if (addr_reg
== NULL
)
8309 addr_reg
= i
.index_reg
;
8313 if (addr_reg
->reg_num
== RegEip
8314 || addr_reg
->reg_num
== RegEiz
8315 || addr_reg
->reg_type
.bitfield
.reg32
)
8316 addr_mode
= CODE_32BIT
;
8317 else if (flag_code
!= CODE_64BIT
8318 && addr_reg
->reg_type
.bitfield
.reg16
)
8319 addr_mode
= CODE_16BIT
;
8321 if (addr_mode
!= flag_code
)
8323 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8325 /* Change the size of any displacement too. At most one
8326 of Disp16 or Disp32 is set.
8327 FIXME. There doesn't seem to be any real need for
8328 separate Disp16 and Disp32 flags. The same goes for
8329 Imm16 and Imm32. Removing them would probably clean
8330 up the code quite a lot. */
8331 if (flag_code
!= CODE_64BIT
8332 && (i
.types
[this_operand
].bitfield
.disp16
8333 || i
.types
[this_operand
].bitfield
.disp32
))
8334 i
.types
[this_operand
]
8335 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8342 if (current_templates
->start
->opcode_modifier
.isstring
8343 && !current_templates
->start
->opcode_modifier
.immext
8344 && (current_templates
->end
[-1].opcode_modifier
.isstring
8347 /* Memory operands of string insns are special in that they only allow
8348 a single register (rDI, rSI, or rBX) as their memory address. */
8349 const reg_entry
*expected_reg
;
8350 static const char *di_si
[][2] =
8356 static const char *bx
[] = { "ebx", "bx", "rbx" };
8358 kind
= "string address";
8360 if (current_templates
->start
->opcode_modifier
.w
)
8362 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8364 if (!type
.bitfield
.baseindex
8365 || ((!i
.mem_operands
!= !intel_syntax
)
8366 && current_templates
->end
[-1].operand_types
[1]
8367 .bitfield
.baseindex
))
8368 type
= current_templates
->end
[-1].operand_types
[1];
8369 expected_reg
= hash_find (reg_hash
,
8370 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8374 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8376 if (i
.base_reg
!= expected_reg
8378 || operand_type_check (i
.types
[this_operand
], disp
))
8380 /* The second memory operand must have the same size as
8384 && !((addr_mode
== CODE_64BIT
8385 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8386 || (addr_mode
== CODE_32BIT
8387 ? i
.base_reg
->reg_type
.bitfield
.reg32
8388 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8391 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8393 intel_syntax
? '[' : '(',
8395 expected_reg
->reg_name
,
8396 intel_syntax
? ']' : ')');
8403 as_bad (_("`%s' is not a valid %s expression"),
8404 operand_string
, kind
);
8409 if (addr_mode
!= CODE_16BIT
)
8411 /* 32-bit/64-bit checks. */
8413 && (addr_mode
== CODE_64BIT
8414 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8415 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8417 || (i
.base_reg
->reg_num
8418 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8420 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8421 && !i
.index_reg
->reg_type
.bitfield
.regymm
8422 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8423 && ((addr_mode
== CODE_64BIT
8424 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8425 || i
.index_reg
->reg_num
== RegRiz
)
8426 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8427 || i
.index_reg
->reg_num
== RegEiz
))
8428 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8433 /* 16-bit checks. */
8435 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8436 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8438 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8439 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8441 && i
.base_reg
->reg_num
< 6
8442 && i
.index_reg
->reg_num
>= 6
8443 && i
.log2_scale_factor
== 0))))
8450 /* Handle vector immediates. */
8453 RC_SAE_immediate (const char *imm_start
)
8455 unsigned int match_found
, j
;
8456 const char *pstr
= imm_start
;
8464 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8466 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8470 rc_op
.type
= RC_NamesTable
[j
].type
;
8471 rc_op
.operand
= this_operand
;
8472 i
.rounding
= &rc_op
;
8476 as_bad (_("duplicated `%s'"), imm_start
);
8479 pstr
+= RC_NamesTable
[j
].len
;
8489 as_bad (_("Missing '}': '%s'"), imm_start
);
8492 /* RC/SAE immediate string should contain nothing more. */;
8495 as_bad (_("Junk after '}': '%s'"), imm_start
);
8499 exp
= &im_expressions
[i
.imm_operands
++];
8500 i
.op
[this_operand
].imms
= exp
;
8502 exp
->X_op
= O_constant
;
8503 exp
->X_add_number
= 0;
8504 exp
->X_add_symbol
= (symbolS
*) 0;
8505 exp
->X_op_symbol
= (symbolS
*) 0;
8507 i
.types
[this_operand
].bitfield
.imm8
= 1;
8511 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8515 i386_att_operand (char *operand_string
)
8519 char *op_string
= operand_string
;
8521 if (is_space_char (*op_string
))
8524 /* We check for an absolute prefix (differentiating,
8525 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8526 if (*op_string
== ABSOLUTE_PREFIX
)
8529 if (is_space_char (*op_string
))
8531 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8534 /* Check if operand is a register. */
8535 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8537 i386_operand_type temp
;
8539 /* Check for a segment override by searching for ':' after a
8540 segment register. */
8542 if (is_space_char (*op_string
))
8544 if (*op_string
== ':'
8545 && (r
->reg_type
.bitfield
.sreg2
8546 || r
->reg_type
.bitfield
.sreg3
))
8551 i
.seg
[i
.mem_operands
] = &es
;
8554 i
.seg
[i
.mem_operands
] = &cs
;
8557 i
.seg
[i
.mem_operands
] = &ss
;
8560 i
.seg
[i
.mem_operands
] = &ds
;
8563 i
.seg
[i
.mem_operands
] = &fs
;
8566 i
.seg
[i
.mem_operands
] = &gs
;
8570 /* Skip the ':' and whitespace. */
8572 if (is_space_char (*op_string
))
8575 if (!is_digit_char (*op_string
)
8576 && !is_identifier_char (*op_string
)
8577 && *op_string
!= '('
8578 && *op_string
!= ABSOLUTE_PREFIX
)
8580 as_bad (_("bad memory operand `%s'"), op_string
);
8583 /* Handle case of %es:*foo. */
8584 if (*op_string
== ABSOLUTE_PREFIX
)
8587 if (is_space_char (*op_string
))
8589 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8591 goto do_memory_reference
;
8594 /* Handle vector operations. */
8595 if (*op_string
== '{')
8597 op_string
= check_VecOperations (op_string
, NULL
);
8598 if (op_string
== NULL
)
8604 as_bad (_("junk `%s' after register"), op_string
);
8608 temp
.bitfield
.baseindex
= 0;
8609 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8611 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8612 i
.op
[this_operand
].regs
= r
;
8615 else if (*op_string
== REGISTER_PREFIX
)
8617 as_bad (_("bad register name `%s'"), op_string
);
8620 else if (*op_string
== IMMEDIATE_PREFIX
)
8623 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8625 as_bad (_("immediate operand illegal with absolute jump"));
8628 if (!i386_immediate (op_string
))
8631 else if (RC_SAE_immediate (operand_string
))
8633 /* If it is a RC or SAE immediate, do nothing. */
8636 else if (is_digit_char (*op_string
)
8637 || is_identifier_char (*op_string
)
8638 || *op_string
== '(')
8640 /* This is a memory reference of some sort. */
8643 /* Start and end of displacement string expression (if found). */
8644 char *displacement_string_start
;
8645 char *displacement_string_end
;
8648 do_memory_reference
:
8649 if ((i
.mem_operands
== 1
8650 && !current_templates
->start
->opcode_modifier
.isstring
)
8651 || i
.mem_operands
== 2)
8653 as_bad (_("too many memory references for `%s'"),
8654 current_templates
->start
->name
);
8658 /* Check for base index form. We detect the base index form by
8659 looking for an ')' at the end of the operand, searching
8660 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8662 base_string
= op_string
+ strlen (op_string
);
8664 /* Handle vector operations. */
8665 vop_start
= strchr (op_string
, '{');
8666 if (vop_start
&& vop_start
< base_string
)
8668 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8670 base_string
= vop_start
;
8674 if (is_space_char (*base_string
))
8677 /* If we only have a displacement, set-up for it to be parsed later. */
8678 displacement_string_start
= op_string
;
8679 displacement_string_end
= base_string
+ 1;
8681 if (*base_string
== ')')
8684 unsigned int parens_balanced
= 1;
8685 /* We've already checked that the number of left & right ()'s are
8686 equal, so this loop will not be infinite. */
8690 if (*base_string
== ')')
8692 if (*base_string
== '(')
8695 while (parens_balanced
);
8697 temp_string
= base_string
;
8699 /* Skip past '(' and whitespace. */
8701 if (is_space_char (*base_string
))
8704 if (*base_string
== ','
8705 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8708 displacement_string_end
= temp_string
;
8710 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8714 base_string
= end_op
;
8715 if (is_space_char (*base_string
))
8719 /* There may be an index reg or scale factor here. */
8720 if (*base_string
== ',')
8723 if (is_space_char (*base_string
))
8726 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8729 base_string
= end_op
;
8730 if (is_space_char (*base_string
))
8732 if (*base_string
== ',')
8735 if (is_space_char (*base_string
))
8738 else if (*base_string
!= ')')
8740 as_bad (_("expecting `,' or `)' "
8741 "after index register in `%s'"),
8746 else if (*base_string
== REGISTER_PREFIX
)
8748 end_op
= strchr (base_string
, ',');
8751 as_bad (_("bad register name `%s'"), base_string
);
8755 /* Check for scale factor. */
8756 if (*base_string
!= ')')
8758 char *end_scale
= i386_scale (base_string
);
8763 base_string
= end_scale
;
8764 if (is_space_char (*base_string
))
8766 if (*base_string
!= ')')
8768 as_bad (_("expecting `)' "
8769 "after scale factor in `%s'"),
8774 else if (!i
.index_reg
)
8776 as_bad (_("expecting index register or scale factor "
8777 "after `,'; got '%c'"),
8782 else if (*base_string
!= ')')
8784 as_bad (_("expecting `,' or `)' "
8785 "after base register in `%s'"),
8790 else if (*base_string
== REGISTER_PREFIX
)
8792 end_op
= strchr (base_string
, ',');
8795 as_bad (_("bad register name `%s'"), base_string
);
8800 /* If there's an expression beginning the operand, parse it,
8801 assuming displacement_string_start and
8802 displacement_string_end are meaningful. */
8803 if (displacement_string_start
!= displacement_string_end
)
8805 if (!i386_displacement (displacement_string_start
,
8806 displacement_string_end
))
8810 /* Special case for (%dx) while doing input/output op. */
8812 && operand_type_equal (&i
.base_reg
->reg_type
,
8813 ®16_inoutportreg
)
8815 && i
.log2_scale_factor
== 0
8816 && i
.seg
[i
.mem_operands
] == 0
8817 && !operand_type_check (i
.types
[this_operand
], disp
))
8819 i
.types
[this_operand
] = inoutportreg
;
8823 if (i386_index_check (operand_string
) == 0)
8825 i
.types
[this_operand
].bitfield
.mem
= 1;
8830 /* It's not a memory operand; argh! */
8831 as_bad (_("invalid char %s beginning operand %d `%s'"),
8832 output_invalid (*op_string
),
8837 return 1; /* Normal return. */
8840 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8841 that an rs_machine_dependent frag may reach. */
8844 i386_frag_max_var (fragS
*frag
)
8846 /* The only relaxable frags are for jumps.
8847 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8848 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8849 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8852 /* md_estimate_size_before_relax()
8854 Called just before relax() for rs_machine_dependent frags. The x86
8855 assembler uses these frags to handle variable size jump
8858 Any symbol that is now undefined will not become defined.
8859 Return the correct fr_subtype in the frag.
8860 Return the initial "guess for variable size of frag" to caller.
8861 The guess is actually the growth beyond the fixed part. Whatever
8862 we do to grow the fixed or variable part contributes to our
8866 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8868 /* We've already got fragP->fr_subtype right; all we have to do is
8869 check for un-relaxable symbols. On an ELF system, we can't relax
8870 an externally visible symbol, because it may be overridden by a
8872 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8873 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8875 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
8876 || S_IS_WEAK (fragP
->fr_symbol
)
8877 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
8878 & BSF_GNU_INDIRECT_FUNCTION
))))
8880 #if defined (OBJ_COFF) && defined (TE_PE)
8881 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8882 && S_IS_WEAK (fragP
->fr_symbol
))
8886 /* Symbol is undefined in this segment, or we need to keep a
8887 reloc so that weak symbols can be overridden. */
8888 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8889 enum bfd_reloc_code_real reloc_type
;
8890 unsigned char *opcode
;
8893 if (fragP
->fr_var
!= NO_RELOC
)
8894 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8896 reloc_type
= BFD_RELOC_16_PCREL
;
8898 reloc_type
= BFD_RELOC_32_PCREL
;
8900 old_fr_fix
= fragP
->fr_fix
;
8901 opcode
= (unsigned char *) fragP
->fr_opcode
;
8903 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
8906 /* Make jmp (0xeb) a (d)word displacement jump. */
8908 fragP
->fr_fix
+= size
;
8909 fix_new (fragP
, old_fr_fix
, size
,
8911 fragP
->fr_offset
, 1,
8917 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
8919 /* Negate the condition, and branch past an
8920 unconditional jump. */
8923 /* Insert an unconditional jump. */
8925 /* We added two extra opcode bytes, and have a two byte
8927 fragP
->fr_fix
+= 2 + 2;
8928 fix_new (fragP
, old_fr_fix
+ 2, 2,
8930 fragP
->fr_offset
, 1,
8937 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8942 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8944 fragP
->fr_offset
, 1,
8946 fixP
->fx_signed
= 1;
8950 /* This changes the byte-displacement jump 0x7N
8951 to the (d)word-displacement jump 0x0f,0x8N. */
8952 opcode
[1] = opcode
[0] + 0x10;
8953 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8954 /* We've added an opcode byte. */
8955 fragP
->fr_fix
+= 1 + size
;
8956 fix_new (fragP
, old_fr_fix
+ 1, size
,
8958 fragP
->fr_offset
, 1,
8963 BAD_CASE (fragP
->fr_subtype
);
8967 return fragP
->fr_fix
- old_fr_fix
;
8970 /* Guess size depending on current relax state. Initially the relax
8971 state will correspond to a short jump and we return 1, because
8972 the variable part of the frag (the branch offset) is one byte
8973 long. However, we can relax a section more than once and in that
8974 case we must either set fr_subtype back to the unrelaxed state,
8975 or return the value for the appropriate branch. */
8976 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
8979 /* Called after relax() is finished.
8981 In: Address of frag.
8982 fr_type == rs_machine_dependent.
8983 fr_subtype is what the address relaxed to.
8985 Out: Any fixSs and constants are set up.
8986 Caller will turn frag into a ".space 0". */
8989 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
8992 unsigned char *opcode
;
8993 unsigned char *where_to_put_displacement
= NULL
;
8994 offsetT target_address
;
8995 offsetT opcode_address
;
8996 unsigned int extension
= 0;
8997 offsetT displacement_from_opcode_start
;
8999 opcode
= (unsigned char *) fragP
->fr_opcode
;
9001 /* Address we want to reach in file space. */
9002 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9004 /* Address opcode resides at in file space. */
9005 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9007 /* Displacement from opcode start to fill into instruction. */
9008 displacement_from_opcode_start
= target_address
- opcode_address
;
9010 if ((fragP
->fr_subtype
& BIG
) == 0)
9012 /* Don't have to change opcode. */
9013 extension
= 1; /* 1 opcode + 1 displacement */
9014 where_to_put_displacement
= &opcode
[1];
9018 if (no_cond_jump_promotion
9019 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9020 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9021 _("long jump required"));
9023 switch (fragP
->fr_subtype
)
9025 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9026 extension
= 4; /* 1 opcode + 4 displacement */
9028 where_to_put_displacement
= &opcode
[1];
9031 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9032 extension
= 2; /* 1 opcode + 2 displacement */
9034 where_to_put_displacement
= &opcode
[1];
9037 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9038 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9039 extension
= 5; /* 2 opcode + 4 displacement */
9040 opcode
[1] = opcode
[0] + 0x10;
9041 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9042 where_to_put_displacement
= &opcode
[2];
9045 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9046 extension
= 3; /* 2 opcode + 2 displacement */
9047 opcode
[1] = opcode
[0] + 0x10;
9048 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9049 where_to_put_displacement
= &opcode
[2];
9052 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9057 where_to_put_displacement
= &opcode
[3];
9061 BAD_CASE (fragP
->fr_subtype
);
9066 /* If size if less then four we are sure that the operand fits,
9067 but if it's 4, then it could be that the displacement is larger
9069 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9071 && ((addressT
) (displacement_from_opcode_start
- extension
9072 + ((addressT
) 1 << 31))
9073 > (((addressT
) 2 << 31) - 1)))
9075 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9076 _("jump target out of range"));
9077 /* Make us emit 0. */
9078 displacement_from_opcode_start
= extension
;
9080 /* Now put displacement after opcode. */
9081 md_number_to_chars ((char *) where_to_put_displacement
,
9082 (valueT
) (displacement_from_opcode_start
- extension
),
9083 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9084 fragP
->fr_fix
+= extension
;
9087 /* Apply a fixup (fixP) to segment data, once it has been determined
9088 by our caller that we have all the info we need to fix it up.
9090 Parameter valP is the pointer to the value of the bits.
9092 On the 386, immediates, displacements, and data pointers are all in
9093 the same (little-endian) format, so we don't need to care about which
9097 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9099 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9100 valueT value
= *valP
;
9102 #if !defined (TE_Mach)
9105 switch (fixP
->fx_r_type
)
9111 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9114 case BFD_RELOC_X86_64_32S
:
9115 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9118 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9121 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9126 if (fixP
->fx_addsy
!= NULL
9127 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9128 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9129 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9130 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
9131 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PC32_BND
)
9132 && !use_rela_relocations
)
9134 /* This is a hack. There should be a better way to handle this.
9135 This covers for the fact that bfd_install_relocation will
9136 subtract the current location (for partial_inplace, PC relative
9137 relocations); see more below. */
9141 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9144 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9146 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9149 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9152 || (symbol_section_p (fixP
->fx_addsy
)
9153 && sym_seg
!= absolute_section
))
9154 && !generic_force_reloc (fixP
))
9156 /* Yes, we add the values in twice. This is because
9157 bfd_install_relocation subtracts them out again. I think
9158 bfd_install_relocation is broken, but I don't dare change
9160 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9164 #if defined (OBJ_COFF) && defined (TE_PE)
9165 /* For some reason, the PE format does not store a
9166 section address offset for a PC relative symbol. */
9167 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9168 || S_IS_WEAK (fixP
->fx_addsy
))
9169 value
+= md_pcrel_from (fixP
);
9172 #if defined (OBJ_COFF) && defined (TE_PE)
9173 if (fixP
->fx_addsy
!= NULL
9174 && S_IS_WEAK (fixP
->fx_addsy
)
9175 /* PR 16858: Do not modify weak function references. */
9176 && ! fixP
->fx_pcrel
)
9178 #if !defined (TE_PEP)
9179 /* For x86 PE weak function symbols are neither PC-relative
9180 nor do they set S_IS_FUNCTION. So the only reliable way
9181 to detect them is to check the flags of their containing
9183 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9184 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9188 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9192 /* Fix a few things - the dynamic linker expects certain values here,
9193 and we must not disappoint it. */
9194 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9195 if (IS_ELF
&& fixP
->fx_addsy
)
9196 switch (fixP
->fx_r_type
)
9198 case BFD_RELOC_386_PLT32
:
9199 case BFD_RELOC_X86_64_PLT32
:
9200 case BFD_RELOC_X86_64_PLT32_BND
:
9201 /* Make the jump instruction point to the address of the operand. At
9202 runtime we merely add the offset to the actual PLT entry. */
9206 case BFD_RELOC_386_TLS_GD
:
9207 case BFD_RELOC_386_TLS_LDM
:
9208 case BFD_RELOC_386_TLS_IE_32
:
9209 case BFD_RELOC_386_TLS_IE
:
9210 case BFD_RELOC_386_TLS_GOTIE
:
9211 case BFD_RELOC_386_TLS_GOTDESC
:
9212 case BFD_RELOC_X86_64_TLSGD
:
9213 case BFD_RELOC_X86_64_TLSLD
:
9214 case BFD_RELOC_X86_64_GOTTPOFF
:
9215 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9216 value
= 0; /* Fully resolved at runtime. No addend. */
9218 case BFD_RELOC_386_TLS_LE
:
9219 case BFD_RELOC_386_TLS_LDO_32
:
9220 case BFD_RELOC_386_TLS_LE_32
:
9221 case BFD_RELOC_X86_64_DTPOFF32
:
9222 case BFD_RELOC_X86_64_DTPOFF64
:
9223 case BFD_RELOC_X86_64_TPOFF32
:
9224 case BFD_RELOC_X86_64_TPOFF64
:
9225 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9228 case BFD_RELOC_386_TLS_DESC_CALL
:
9229 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9230 value
= 0; /* Fully resolved at runtime. No addend. */
9231 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9235 case BFD_RELOC_386_GOT32
:
9236 case BFD_RELOC_X86_64_GOT32
:
9237 value
= 0; /* Fully resolved at runtime. No addend. */
9240 case BFD_RELOC_VTABLE_INHERIT
:
9241 case BFD_RELOC_VTABLE_ENTRY
:
9248 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9250 #endif /* !defined (TE_Mach) */
9252 /* Are we finished with this relocation now? */
9253 if (fixP
->fx_addsy
== NULL
)
9255 #if defined (OBJ_COFF) && defined (TE_PE)
9256 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9259 /* Remember value for tc_gen_reloc. */
9260 fixP
->fx_addnumber
= value
;
9261 /* Clear out the frag for now. */
9265 else if (use_rela_relocations
)
9267 fixP
->fx_no_overflow
= 1;
9268 /* Remember value for tc_gen_reloc. */
9269 fixP
->fx_addnumber
= value
;
9273 md_number_to_chars (p
, value
, fixP
->fx_size
);
9277 md_atof (int type
, char *litP
, int *sizeP
)
9279 /* This outputs the LITTLENUMs in REVERSE order;
9280 in accord with the bigendian 386. */
9281 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9284 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9287 output_invalid (int c
)
9290 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9293 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9294 "(0x%x)", (unsigned char) c
);
9295 return output_invalid_buf
;
9298 /* REG_STRING starts *before* REGISTER_PREFIX. */
9300 static const reg_entry
*
9301 parse_real_register (char *reg_string
, char **end_op
)
9303 char *s
= reg_string
;
9305 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9308 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9309 if (*s
== REGISTER_PREFIX
)
9312 if (is_space_char (*s
))
9316 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9318 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9319 return (const reg_entry
*) NULL
;
9323 /* For naked regs, make sure that we are not dealing with an identifier.
9324 This prevents confusing an identifier like `eax_var' with register
9326 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9327 return (const reg_entry
*) NULL
;
9331 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9333 /* Handle floating point regs, allowing spaces in the (i) part. */
9334 if (r
== i386_regtab
/* %st is first entry of table */)
9336 if (is_space_char (*s
))
9341 if (is_space_char (*s
))
9343 if (*s
>= '0' && *s
<= '7')
9347 if (is_space_char (*s
))
9352 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9357 /* We have "%st(" then garbage. */
9358 return (const reg_entry
*) NULL
;
9362 if (r
== NULL
|| allow_pseudo_reg
)
9365 if (operand_type_all_zero (&r
->reg_type
))
9366 return (const reg_entry
*) NULL
;
9368 if ((r
->reg_type
.bitfield
.reg32
9369 || r
->reg_type
.bitfield
.sreg3
9370 || r
->reg_type
.bitfield
.control
9371 || r
->reg_type
.bitfield
.debug
9372 || r
->reg_type
.bitfield
.test
)
9373 && !cpu_arch_flags
.bitfield
.cpui386
)
9374 return (const reg_entry
*) NULL
;
9376 if (r
->reg_type
.bitfield
.floatreg
9377 && !cpu_arch_flags
.bitfield
.cpu8087
9378 && !cpu_arch_flags
.bitfield
.cpu287
9379 && !cpu_arch_flags
.bitfield
.cpu387
)
9380 return (const reg_entry
*) NULL
;
9382 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9383 return (const reg_entry
*) NULL
;
9385 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9386 return (const reg_entry
*) NULL
;
9388 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9389 return (const reg_entry
*) NULL
;
9391 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9392 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9393 return (const reg_entry
*) NULL
;
9395 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9396 if (!allow_index_reg
9397 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9398 return (const reg_entry
*) NULL
;
9400 /* Upper 16 vector register is only available with VREX in 64bit
9402 if ((r
->reg_flags
& RegVRex
))
9404 if (!cpu_arch_flags
.bitfield
.cpuvrex
9405 || flag_code
!= CODE_64BIT
)
9406 return (const reg_entry
*) NULL
;
9411 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9412 || r
->reg_type
.bitfield
.reg64
)
9413 && (!cpu_arch_flags
.bitfield
.cpulm
9414 || !operand_type_equal (&r
->reg_type
, &control
))
9415 && flag_code
!= CODE_64BIT
)
9416 return (const reg_entry
*) NULL
;
9418 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9419 return (const reg_entry
*) NULL
;
9424 /* REG_STRING starts *before* REGISTER_PREFIX. */
9426 static const reg_entry
*
9427 parse_register (char *reg_string
, char **end_op
)
9431 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9432 r
= parse_real_register (reg_string
, end_op
);
9437 char *save
= input_line_pointer
;
9441 input_line_pointer
= reg_string
;
9442 c
= get_symbol_end ();
9443 symbolP
= symbol_find (reg_string
);
9444 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9446 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9448 know (e
->X_op
== O_register
);
9449 know (e
->X_add_number
>= 0
9450 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9451 r
= i386_regtab
+ e
->X_add_number
;
9452 if ((r
->reg_flags
& RegVRex
))
9454 *end_op
= input_line_pointer
;
9456 *input_line_pointer
= c
;
9457 input_line_pointer
= save
;
9463 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9466 char *end
= input_line_pointer
;
9469 r
= parse_register (name
, &input_line_pointer
);
9470 if (r
&& end
<= input_line_pointer
)
9472 *nextcharP
= *input_line_pointer
;
9473 *input_line_pointer
= 0;
9474 e
->X_op
= O_register
;
9475 e
->X_add_number
= r
- i386_regtab
;
9478 input_line_pointer
= end
;
9480 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9484 md_operand (expressionS
*e
)
9489 switch (*input_line_pointer
)
9491 case REGISTER_PREFIX
:
9492 r
= parse_real_register (input_line_pointer
, &end
);
9495 e
->X_op
= O_register
;
9496 e
->X_add_number
= r
- i386_regtab
;
9497 input_line_pointer
= end
;
9502 gas_assert (intel_syntax
);
9503 end
= input_line_pointer
++;
9505 if (*input_line_pointer
== ']')
9507 ++input_line_pointer
;
9508 e
->X_op_symbol
= make_expr_symbol (e
);
9509 e
->X_add_symbol
= NULL
;
9510 e
->X_add_number
= 0;
9516 input_line_pointer
= end
;
9523 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9524 const char *md_shortopts
= "kVQ:sqn";
9526 const char *md_shortopts
= "qn";
9529 #define OPTION_32 (OPTION_MD_BASE + 0)
9530 #define OPTION_64 (OPTION_MD_BASE + 1)
9531 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9532 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9533 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9534 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9535 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9536 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9537 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9538 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9539 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9540 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9541 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9542 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9543 #define OPTION_X32 (OPTION_MD_BASE + 14)
9544 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9545 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9546 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9547 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9548 #define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9550 struct option md_longopts
[] =
9552 {"32", no_argument
, NULL
, OPTION_32
},
9553 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9554 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9555 {"64", no_argument
, NULL
, OPTION_64
},
9557 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9558 {"x32", no_argument
, NULL
, OPTION_X32
},
9560 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9561 {"march", required_argument
, NULL
, OPTION_MARCH
},
9562 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9563 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9564 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9565 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9566 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9567 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9568 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9569 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9570 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9571 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9572 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9573 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9574 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9575 # if defined (TE_PE) || defined (TE_PEP)
9576 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9578 {"momit-lock-prefix", required_argument
, NULL
, OPTION_OMIT_LOCK_PREFIX
},
9579 {NULL
, no_argument
, NULL
, 0}
9581 size_t md_longopts_size
= sizeof (md_longopts
);
9584 md_parse_option (int c
, char *arg
)
9592 optimize_align_code
= 0;
9599 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9600 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9601 should be emitted or not. FIXME: Not implemented. */
9605 /* -V: SVR4 argument to print version ID. */
9607 print_version_id ();
9610 /* -k: Ignore for FreeBSD compatibility. */
9615 /* -s: On i386 Solaris, this tells the native assembler to use
9616 .stab instead of .stab.excl. We always use .stab anyhow. */
9619 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9620 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9623 const char **list
, **l
;
9625 list
= bfd_target_list ();
9626 for (l
= list
; *l
!= NULL
; l
++)
9627 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9628 || strcmp (*l
, "coff-x86-64") == 0
9629 || strcmp (*l
, "pe-x86-64") == 0
9630 || strcmp (*l
, "pei-x86-64") == 0
9631 || strcmp (*l
, "mach-o-x86-64") == 0)
9633 default_arch
= "x86_64";
9637 as_fatal (_("no compiled in support for x86_64"));
9643 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9647 const char **list
, **l
;
9649 list
= bfd_target_list ();
9650 for (l
= list
; *l
!= NULL
; l
++)
9651 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9653 default_arch
= "x86_64:32";
9657 as_fatal (_("no compiled in support for 32bit x86_64"));
9661 as_fatal (_("32bit x86_64 is only supported for ELF"));
9666 default_arch
= "i386";
9670 #ifdef SVR4_COMMENT_CHARS
9675 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9677 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9681 i386_comment_chars
= n
;
9687 arch
= xstrdup (arg
);
9691 as_fatal (_("invalid -march= option: `%s'"), arg
);
9692 next
= strchr (arch
, '+');
9695 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9697 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9700 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9703 cpu_arch_name
= cpu_arch
[j
].name
;
9704 cpu_sub_arch_name
= NULL
;
9705 cpu_arch_flags
= cpu_arch
[j
].flags
;
9706 cpu_arch_isa
= cpu_arch
[j
].type
;
9707 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9708 if (!cpu_arch_tune_set
)
9710 cpu_arch_tune
= cpu_arch_isa
;
9711 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9715 else if (*cpu_arch
[j
].name
== '.'
9716 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9718 /* ISA entension. */
9719 i386_cpu_flags flags
;
9721 if (!cpu_arch
[j
].negated
)
9722 flags
= cpu_flags_or (cpu_arch_flags
,
9725 flags
= cpu_flags_and_not (cpu_arch_flags
,
9727 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9729 if (cpu_sub_arch_name
)
9731 char *name
= cpu_sub_arch_name
;
9732 cpu_sub_arch_name
= concat (name
,
9734 (const char *) NULL
);
9738 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9739 cpu_arch_flags
= flags
;
9740 cpu_arch_isa_flags
= flags
;
9746 if (j
>= ARRAY_SIZE (cpu_arch
))
9747 as_fatal (_("invalid -march= option: `%s'"), arg
);
9751 while (next
!= NULL
);
9756 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9757 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9759 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9761 cpu_arch_tune_set
= 1;
9762 cpu_arch_tune
= cpu_arch
[j
].type
;
9763 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9767 if (j
>= ARRAY_SIZE (cpu_arch
))
9768 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9771 case OPTION_MMNEMONIC
:
9772 if (strcasecmp (arg
, "att") == 0)
9774 else if (strcasecmp (arg
, "intel") == 0)
9777 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9780 case OPTION_MSYNTAX
:
9781 if (strcasecmp (arg
, "att") == 0)
9783 else if (strcasecmp (arg
, "intel") == 0)
9786 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9789 case OPTION_MINDEX_REG
:
9790 allow_index_reg
= 1;
9793 case OPTION_MNAKED_REG
:
9794 allow_naked_reg
= 1;
9797 case OPTION_MOLD_GCC
:
9801 case OPTION_MSSE2AVX
:
9805 case OPTION_MSSE_CHECK
:
9806 if (strcasecmp (arg
, "error") == 0)
9807 sse_check
= check_error
;
9808 else if (strcasecmp (arg
, "warning") == 0)
9809 sse_check
= check_warning
;
9810 else if (strcasecmp (arg
, "none") == 0)
9811 sse_check
= check_none
;
9813 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9816 case OPTION_MOPERAND_CHECK
:
9817 if (strcasecmp (arg
, "error") == 0)
9818 operand_check
= check_error
;
9819 else if (strcasecmp (arg
, "warning") == 0)
9820 operand_check
= check_warning
;
9821 else if (strcasecmp (arg
, "none") == 0)
9822 operand_check
= check_none
;
9824 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9827 case OPTION_MAVXSCALAR
:
9828 if (strcasecmp (arg
, "128") == 0)
9830 else if (strcasecmp (arg
, "256") == 0)
9833 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9836 case OPTION_MADD_BND_PREFIX
:
9840 case OPTION_MEVEXLIG
:
9841 if (strcmp (arg
, "128") == 0)
9843 else if (strcmp (arg
, "256") == 0)
9845 else if (strcmp (arg
, "512") == 0)
9848 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9851 case OPTION_MEVEXWIG
:
9852 if (strcmp (arg
, "0") == 0)
9854 else if (strcmp (arg
, "1") == 0)
9857 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9860 # if defined (TE_PE) || defined (TE_PEP)
9861 case OPTION_MBIG_OBJ
:
9866 case OPTION_OMIT_LOCK_PREFIX
:
9867 if (strcasecmp (arg
, "yes") == 0)
9868 omit_lock_prefix
= 1;
9869 else if (strcasecmp (arg
, "no") == 0)
9870 omit_lock_prefix
= 0;
9872 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
9881 #define MESSAGE_TEMPLATE \
9885 show_arch (FILE *stream
, int ext
, int check
)
9887 static char message
[] = MESSAGE_TEMPLATE
;
9888 char *start
= message
+ 27;
9890 int size
= sizeof (MESSAGE_TEMPLATE
);
9897 left
= size
- (start
- message
);
9898 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9900 /* Should it be skipped? */
9901 if (cpu_arch
[j
].skip
)
9904 name
= cpu_arch
[j
].name
;
9905 len
= cpu_arch
[j
].len
;
9908 /* It is an extension. Skip if we aren't asked to show it. */
9919 /* It is an processor. Skip if we show only extension. */
9922 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9924 /* It is an impossible processor - skip. */
9928 /* Reserve 2 spaces for ", " or ",\0" */
9931 /* Check if there is any room. */
9939 p
= mempcpy (p
, name
, len
);
9943 /* Output the current message now and start a new one. */
9946 fprintf (stream
, "%s\n", message
);
9948 left
= size
- (start
- message
) - len
- 2;
9950 gas_assert (left
>= 0);
9952 p
= mempcpy (p
, name
, len
);
9957 fprintf (stream
, "%s\n", message
);
9961 md_show_usage (FILE *stream
)
9963 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9964 fprintf (stream
, _("\
9966 -V print assembler version number\n\
9969 fprintf (stream
, _("\
9970 -n Do not optimize code alignment\n\
9971 -q quieten some warnings\n"));
9972 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9973 fprintf (stream
, _("\
9976 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9977 || defined (TE_PE) || defined (TE_PEP))
9978 fprintf (stream
, _("\
9979 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
9981 #ifdef SVR4_COMMENT_CHARS
9982 fprintf (stream
, _("\
9983 --divide do not treat `/' as a comment character\n"));
9985 fprintf (stream
, _("\
9986 --divide ignored\n"));
9988 fprintf (stream
, _("\
9989 -march=CPU[,+EXTENSION...]\n\
9990 generate code for CPU and EXTENSION, CPU is one of:\n"));
9991 show_arch (stream
, 0, 1);
9992 fprintf (stream
, _("\
9993 EXTENSION is combination of:\n"));
9994 show_arch (stream
, 1, 0);
9995 fprintf (stream
, _("\
9996 -mtune=CPU optimize for CPU, CPU is one of:\n"));
9997 show_arch (stream
, 0, 0);
9998 fprintf (stream
, _("\
9999 -msse2avx encode SSE instructions with VEX prefix\n"));
10000 fprintf (stream
, _("\
10001 -msse-check=[none|error|warning]\n\
10002 check SSE instructions\n"));
10003 fprintf (stream
, _("\
10004 -moperand-check=[none|error|warning]\n\
10005 check operand combinations for validity\n"));
10006 fprintf (stream
, _("\
10007 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10009 fprintf (stream
, _("\
10010 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10012 fprintf (stream
, _("\
10013 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10014 for EVEX.W bit ignored instructions\n"));
10015 fprintf (stream
, _("\
10016 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10017 fprintf (stream
, _("\
10018 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10019 fprintf (stream
, _("\
10020 -mindex-reg support pseudo index registers\n"));
10021 fprintf (stream
, _("\
10022 -mnaked-reg don't require `%%' prefix for registers\n"));
10023 fprintf (stream
, _("\
10024 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10025 fprintf (stream
, _("\
10026 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10027 # if defined (TE_PE) || defined (TE_PEP)
10028 fprintf (stream
, _("\
10029 -mbig-obj generate big object files\n"));
10031 fprintf (stream
, _("\
10032 -momit-lock-prefix=[no|yes]\n\
10033 strip all lock prefixes\n"));
10036 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10037 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10038 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10040 /* Pick the target format to use. */
10043 i386_target_format (void)
10045 if (!strncmp (default_arch
, "x86_64", 6))
10047 update_code_flag (CODE_64BIT
, 1);
10048 if (default_arch
[6] == '\0')
10049 x86_elf_abi
= X86_64_ABI
;
10051 x86_elf_abi
= X86_64_X32_ABI
;
10053 else if (!strcmp (default_arch
, "i386"))
10054 update_code_flag (CODE_32BIT
, 1);
10056 as_fatal (_("unknown architecture"));
10058 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10059 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10060 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10061 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10063 switch (OUTPUT_FLAVOR
)
10065 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10066 case bfd_target_aout_flavour
:
10067 return AOUT_TARGET_FORMAT
;
10069 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10070 # if defined (TE_PE) || defined (TE_PEP)
10071 case bfd_target_coff_flavour
:
10072 if (flag_code
== CODE_64BIT
)
10073 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10076 # elif defined (TE_GO32)
10077 case bfd_target_coff_flavour
:
10078 return "coff-go32";
10080 case bfd_target_coff_flavour
:
10081 return "coff-i386";
10084 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10085 case bfd_target_elf_flavour
:
10087 const char *format
;
10089 switch (x86_elf_abi
)
10092 format
= ELF_TARGET_FORMAT
;
10095 use_rela_relocations
= 1;
10097 format
= ELF_TARGET_FORMAT64
;
10099 case X86_64_X32_ABI
:
10100 use_rela_relocations
= 1;
10102 disallow_64bit_reloc
= 1;
10103 format
= ELF_TARGET_FORMAT32
;
10106 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10108 if (x86_elf_abi
!= X86_64_ABI
)
10109 as_fatal (_("Intel L1OM is 64bit only"));
10110 return ELF_TARGET_L1OM_FORMAT
;
10112 if (cpu_arch_isa
== PROCESSOR_K1OM
)
10114 if (x86_elf_abi
!= X86_64_ABI
)
10115 as_fatal (_("Intel K1OM is 64bit only"));
10116 return ELF_TARGET_K1OM_FORMAT
;
10122 #if defined (OBJ_MACH_O)
10123 case bfd_target_mach_o_flavour
:
10124 if (flag_code
== CODE_64BIT
)
10126 use_rela_relocations
= 1;
10128 return "mach-o-x86-64";
10131 return "mach-o-i386";
10139 #endif /* OBJ_MAYBE_ more than one */
10141 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
10143 i386_elf_emit_arch_note (void)
10145 if (IS_ELF
&& cpu_arch_name
!= NULL
)
10148 asection
*seg
= now_seg
;
10149 subsegT subseg
= now_subseg
;
10150 Elf_Internal_Note i_note
;
10151 Elf_External_Note e_note
;
10152 asection
*note_secp
;
10155 /* Create the .note section. */
10156 note_secp
= subseg_new (".note", 0);
10157 bfd_set_section_flags (stdoutput
,
10159 SEC_HAS_CONTENTS
| SEC_READONLY
);
10161 /* Process the arch string. */
10162 len
= strlen (cpu_arch_name
);
10164 i_note
.namesz
= len
+ 1;
10166 i_note
.type
= NT_ARCH
;
10167 p
= frag_more (sizeof (e_note
.namesz
));
10168 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
10169 p
= frag_more (sizeof (e_note
.descsz
));
10170 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
10171 p
= frag_more (sizeof (e_note
.type
));
10172 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
10173 p
= frag_more (len
+ 1);
10174 strcpy (p
, cpu_arch_name
);
10176 frag_align (2, 0, 0);
10178 subseg_set (seg
, subseg
);
10184 md_undefined_symbol (char *name
)
10186 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10187 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10188 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10189 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10193 if (symbol_find (name
))
10194 as_bad (_("GOT already in symbol table"));
10195 GOT_symbol
= symbol_new (name
, undefined_section
,
10196 (valueT
) 0, &zero_address_frag
);
10203 /* Round up a section size to the appropriate boundary. */
10206 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10208 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10209 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10211 /* For a.out, force the section size to be aligned. If we don't do
10212 this, BFD will align it for us, but it will not write out the
10213 final bytes of the section. This may be a bug in BFD, but it is
10214 easier to fix it here since that is how the other a.out targets
10218 align
= bfd_get_section_alignment (stdoutput
, segment
);
10219 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
10226 /* On the i386, PC-relative offsets are relative to the start of the
10227 next instruction. That is, the address of the offset, plus its
10228 size, since the offset is always the last part of the insn. */
10231 md_pcrel_from (fixS
*fixP
)
10233 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10239 s_bss (int ignore ATTRIBUTE_UNUSED
)
10243 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10245 obj_elf_section_change_hook ();
10247 temp
= get_absolute_expression ();
10248 subseg_set (bss_section
, (subsegT
) temp
);
10249 demand_empty_rest_of_line ();
10255 i386_validate_fix (fixS
*fixp
)
10257 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
10259 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10263 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10268 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10270 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10272 fixp
->fx_subsy
= 0;
10277 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10280 bfd_reloc_code_real_type code
;
10282 switch (fixp
->fx_r_type
)
10284 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10285 case BFD_RELOC_SIZE32
:
10286 case BFD_RELOC_SIZE64
:
10287 if (S_IS_DEFINED (fixp
->fx_addsy
)
10288 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10290 /* Resolve size relocation against local symbol to size of
10291 the symbol plus addend. */
10292 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10293 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10294 && !fits_in_unsigned_long (value
))
10295 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10296 _("symbol size computation overflow"));
10297 fixp
->fx_addsy
= NULL
;
10298 fixp
->fx_subsy
= NULL
;
10299 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10304 case BFD_RELOC_X86_64_PLT32
:
10305 case BFD_RELOC_X86_64_PLT32_BND
:
10306 case BFD_RELOC_X86_64_GOT32
:
10307 case BFD_RELOC_X86_64_GOTPCREL
:
10308 case BFD_RELOC_386_PLT32
:
10309 case BFD_RELOC_386_GOT32
:
10310 case BFD_RELOC_386_GOTOFF
:
10311 case BFD_RELOC_386_GOTPC
:
10312 case BFD_RELOC_386_TLS_GD
:
10313 case BFD_RELOC_386_TLS_LDM
:
10314 case BFD_RELOC_386_TLS_LDO_32
:
10315 case BFD_RELOC_386_TLS_IE_32
:
10316 case BFD_RELOC_386_TLS_IE
:
10317 case BFD_RELOC_386_TLS_GOTIE
:
10318 case BFD_RELOC_386_TLS_LE_32
:
10319 case BFD_RELOC_386_TLS_LE
:
10320 case BFD_RELOC_386_TLS_GOTDESC
:
10321 case BFD_RELOC_386_TLS_DESC_CALL
:
10322 case BFD_RELOC_X86_64_TLSGD
:
10323 case BFD_RELOC_X86_64_TLSLD
:
10324 case BFD_RELOC_X86_64_DTPOFF32
:
10325 case BFD_RELOC_X86_64_DTPOFF64
:
10326 case BFD_RELOC_X86_64_GOTTPOFF
:
10327 case BFD_RELOC_X86_64_TPOFF32
:
10328 case BFD_RELOC_X86_64_TPOFF64
:
10329 case BFD_RELOC_X86_64_GOTOFF64
:
10330 case BFD_RELOC_X86_64_GOTPC32
:
10331 case BFD_RELOC_X86_64_GOT64
:
10332 case BFD_RELOC_X86_64_GOTPCREL64
:
10333 case BFD_RELOC_X86_64_GOTPC64
:
10334 case BFD_RELOC_X86_64_GOTPLT64
:
10335 case BFD_RELOC_X86_64_PLTOFF64
:
10336 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10337 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10338 case BFD_RELOC_RVA
:
10339 case BFD_RELOC_VTABLE_ENTRY
:
10340 case BFD_RELOC_VTABLE_INHERIT
:
10342 case BFD_RELOC_32_SECREL
:
10344 code
= fixp
->fx_r_type
;
10346 case BFD_RELOC_X86_64_32S
:
10347 if (!fixp
->fx_pcrel
)
10349 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10350 code
= fixp
->fx_r_type
;
10354 if (fixp
->fx_pcrel
)
10356 switch (fixp
->fx_size
)
10359 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10360 _("can not do %d byte pc-relative relocation"),
10362 code
= BFD_RELOC_32_PCREL
;
10364 case 1: code
= BFD_RELOC_8_PCREL
; break;
10365 case 2: code
= BFD_RELOC_16_PCREL
; break;
10367 code
= (fixp
->fx_r_type
== BFD_RELOC_X86_64_PC32_BND
10368 ? fixp
-> fx_r_type
: BFD_RELOC_32_PCREL
);
10371 case 8: code
= BFD_RELOC_64_PCREL
; break;
10377 switch (fixp
->fx_size
)
10380 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10381 _("can not do %d byte relocation"),
10383 code
= BFD_RELOC_32
;
10385 case 1: code
= BFD_RELOC_8
; break;
10386 case 2: code
= BFD_RELOC_16
; break;
10387 case 4: code
= BFD_RELOC_32
; break;
10389 case 8: code
= BFD_RELOC_64
; break;
10396 if ((code
== BFD_RELOC_32
10397 || code
== BFD_RELOC_32_PCREL
10398 || code
== BFD_RELOC_X86_64_32S
)
10400 && fixp
->fx_addsy
== GOT_symbol
)
10403 code
= BFD_RELOC_386_GOTPC
;
10405 code
= BFD_RELOC_X86_64_GOTPC32
;
10407 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10409 && fixp
->fx_addsy
== GOT_symbol
)
10411 code
= BFD_RELOC_X86_64_GOTPC64
;
10414 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10415 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10416 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10418 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10420 if (!use_rela_relocations
)
10422 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10423 vtable entry to be used in the relocation's section offset. */
10424 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10425 rel
->address
= fixp
->fx_offset
;
10426 #if defined (OBJ_COFF) && defined (TE_PE)
10427 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10428 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10433 /* Use the rela in 64bit mode. */
10436 if (disallow_64bit_reloc
)
10439 case BFD_RELOC_X86_64_DTPOFF64
:
10440 case BFD_RELOC_X86_64_TPOFF64
:
10441 case BFD_RELOC_64_PCREL
:
10442 case BFD_RELOC_X86_64_GOTOFF64
:
10443 case BFD_RELOC_X86_64_GOT64
:
10444 case BFD_RELOC_X86_64_GOTPCREL64
:
10445 case BFD_RELOC_X86_64_GOTPC64
:
10446 case BFD_RELOC_X86_64_GOTPLT64
:
10447 case BFD_RELOC_X86_64_PLTOFF64
:
10448 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10449 _("cannot represent relocation type %s in x32 mode"),
10450 bfd_get_reloc_code_name (code
));
10456 if (!fixp
->fx_pcrel
)
10457 rel
->addend
= fixp
->fx_offset
;
10461 case BFD_RELOC_X86_64_PLT32
:
10462 case BFD_RELOC_X86_64_PLT32_BND
:
10463 case BFD_RELOC_X86_64_GOT32
:
10464 case BFD_RELOC_X86_64_GOTPCREL
:
10465 case BFD_RELOC_X86_64_TLSGD
:
10466 case BFD_RELOC_X86_64_TLSLD
:
10467 case BFD_RELOC_X86_64_GOTTPOFF
:
10468 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10469 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10470 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10473 rel
->addend
= (section
->vma
10475 + fixp
->fx_addnumber
10476 + md_pcrel_from (fixp
));
10481 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10482 if (rel
->howto
== NULL
)
10484 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10485 _("cannot represent relocation type %s"),
10486 bfd_get_reloc_code_name (code
));
10487 /* Set howto to a garbage value so that we can keep going. */
10488 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10489 gas_assert (rel
->howto
!= NULL
);
10495 #include "tc-i386-intel.c"
10498 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10500 int saved_naked_reg
;
10501 char saved_register_dot
;
10503 saved_naked_reg
= allow_naked_reg
;
10504 allow_naked_reg
= 1;
10505 saved_register_dot
= register_chars
['.'];
10506 register_chars
['.'] = '.';
10507 allow_pseudo_reg
= 1;
10508 expression_and_evaluate (exp
);
10509 allow_pseudo_reg
= 0;
10510 register_chars
['.'] = saved_register_dot
;
10511 allow_naked_reg
= saved_naked_reg
;
10513 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10515 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10517 exp
->X_op
= O_constant
;
10518 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10519 .dw2_regnum
[flag_code
>> 1];
10522 exp
->X_op
= O_illegal
;
10527 tc_x86_frame_initial_instructions (void)
10529 static unsigned int sp_regno
[2];
10531 if (!sp_regno
[flag_code
>> 1])
10533 char *saved_input
= input_line_pointer
;
10534 char sp
[][4] = {"esp", "rsp"};
10537 input_line_pointer
= sp
[flag_code
>> 1];
10538 tc_x86_parse_to_dw2regnum (&exp
);
10539 gas_assert (exp
.X_op
== O_constant
);
10540 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10541 input_line_pointer
= saved_input
;
10544 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10545 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10549 x86_dwarf2_addr_size (void)
10551 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10552 if (x86_elf_abi
== X86_64_X32_ABI
)
10555 return bfd_arch_bits_per_address (stdoutput
) / 8;
10559 i386_elf_section_type (const char *str
, size_t len
)
10561 if (flag_code
== CODE_64BIT
10562 && len
== sizeof ("unwind") - 1
10563 && strncmp (str
, "unwind", 6) == 0)
10564 return SHT_X86_64_UNWIND
;
10571 i386_solaris_fix_up_eh_frame (segT sec
)
10573 if (flag_code
== CODE_64BIT
)
10574 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10580 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10584 exp
.X_op
= O_secrel
;
10585 exp
.X_add_symbol
= symbol
;
10586 exp
.X_add_number
= 0;
10587 emit_expr (&exp
, size
);
10591 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10592 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10595 x86_64_section_letter (int letter
, char **ptr_msg
)
10597 if (flag_code
== CODE_64BIT
)
10600 return SHF_X86_64_LARGE
;
10602 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10605 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10610 x86_64_section_word (char *str
, size_t len
)
10612 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10613 return SHF_X86_64_LARGE
;
10619 handle_large_common (int small ATTRIBUTE_UNUSED
)
10621 if (flag_code
!= CODE_64BIT
)
10623 s_comm_internal (0, elf_common_parse
);
10624 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10628 static segT lbss_section
;
10629 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10630 asection
*saved_bss_section
= bss_section
;
10632 if (lbss_section
== NULL
)
10634 flagword applicable
;
10635 segT seg
= now_seg
;
10636 subsegT subseg
= now_subseg
;
10638 /* The .lbss section is for local .largecomm symbols. */
10639 lbss_section
= subseg_new (".lbss", 0);
10640 applicable
= bfd_applicable_section_flags (stdoutput
);
10641 bfd_set_section_flags (stdoutput
, lbss_section
,
10642 applicable
& SEC_ALLOC
);
10643 seg_info (lbss_section
)->bss
= 1;
10645 subseg_set (seg
, subseg
);
10648 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10649 bss_section
= lbss_section
;
10651 s_comm_internal (0, elf_common_parse
);
10653 elf_com_section_ptr
= saved_com_section_ptr
;
10654 bss_section
= saved_bss_section
;
10657 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */