1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
136 unsigned int negated
; /* turn off indicated flags. */
140 static void update_code_flag (int, int);
141 static void set_code_flag (int);
142 static void set_16bit_gcc_code_flag (int);
143 static void set_intel_syntax (int);
144 static void set_intel_mnemonic (int);
145 static void set_allow_index_reg (int);
146 static void set_check (int);
147 static void set_cpu_arch (int);
149 static void pe_directive_secrel (int);
151 static void signed_cons (int);
152 static char *output_invalid (int c
);
153 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
155 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
157 static int i386_att_operand (char *);
158 static int i386_intel_operand (char *, int);
159 static int i386_intel_simplify (expressionS
*);
160 static int i386_intel_parse_name (const char *, expressionS
*);
161 static const reg_entry
*parse_register (char *, char **);
162 static char *parse_insn (char *, char *);
163 static char *parse_operands (char *, const char *);
164 static void swap_operands (void);
165 static void swap_2_operands (int, int);
166 static void optimize_imm (void);
167 static void optimize_disp (void);
168 static const insn_template
*match_template (void);
169 static int check_string (void);
170 static int process_suffix (void);
171 static int check_byte_reg (void);
172 static int check_long_reg (void);
173 static int check_qword_reg (void);
174 static int check_word_reg (void);
175 static int finalize_imm (void);
176 static int process_operands (void);
177 static const seg_entry
*build_modrm_byte (void);
178 static void output_insn (void);
179 static void output_imm (fragS
*, offsetT
);
180 static void output_disp (fragS
*, offsetT
);
182 static void s_bss (int);
184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
188 static const char *default_arch
= DEFAULT_ARCH
;
190 /* This struct describes rounding control and SAE in the instruction. */
204 static struct RC_Operation rc_op
;
206 /* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209 struct Mask_Operation
211 const reg_entry
*mask
;
212 unsigned int zeroing
;
213 /* The operand where this operation is associated. */
217 static struct Mask_Operation mask_op
;
219 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
221 struct Broadcast_Operation
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
226 /* Index of broadcasted operand. */
230 static struct Broadcast_Operation broadcast_op
;
235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes
[4];
238 /* Destination or source register specifier. */
239 const reg_entry
*register_specifier
;
242 /* 'md_assemble ()' gathers together information and puts it into a
249 const reg_entry
*regs
;
254 operand_size_mismatch
,
255 operand_type_mismatch
,
256 register_type_mismatch
,
257 number_of_operands_mismatch
,
258 invalid_instruction_suffix
,
261 unsupported_with_intel_mnemonic
,
264 invalid_vsib_address
,
265 invalid_vector_register_set
,
266 unsupported_vector_index_register
,
267 unsupported_broadcast
,
268 broadcast_not_on_src_operand
,
271 mask_not_on_destination
,
274 rc_sae_operand_not_last_imm
,
275 invalid_register_operand
,
281 /* TM holds the template for the insn were currently assembling. */
284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
288 /* OPERANDS gives the number of given operands. */
289 unsigned int operands
;
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
294 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
296 /* TYPES [i] is the type (see above #defines) which tells us how to
297 use OP[i] for the corresponding operand. */
298 i386_operand_type types
[MAX_OPERANDS
];
300 /* Displacement expression, immediate expression, or register for each
302 union i386_op op
[MAX_OPERANDS
];
304 /* Flags for operands. */
305 unsigned int flags
[MAX_OPERANDS
];
306 #define Operand_PCrel 1
308 /* Relocation type for operand */
309 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry
*base_reg
;
314 const reg_entry
*index_reg
;
315 unsigned int log2_scale_factor
;
317 /* SEG gives the seg_entries of this insn. They are zero unless
318 explicit segment overrides are given. */
319 const seg_entry
*seg
[2];
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes
;
324 unsigned char prefix
[MAX_PREFIXES
];
326 /* RM and SIB are the modrm byte and the sib byte where the
327 addressing modes of this insn are encoded. */
334 /* Masking attributes. */
335 struct Mask_Operation
*mask
;
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation
*rounding
;
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation
*broadcast
;
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift
;
346 /* Swap operand in encoding. */
347 unsigned int swap_operand
;
349 /* Prefer 8bit or 32bit displacement in encoding. */
352 disp_encoding_default
= 0,
358 const char *rep_prefix
;
361 const char *hle_prefix
;
363 /* Have BND prefix. */
364 const char *bnd_prefix
;
366 /* Need VREX to support upper 16 registers. */
370 enum i386_error error
;
373 typedef struct _i386_insn i386_insn
;
375 /* Link RC type with corresponding string, that'll be looked for in
384 static const struct RC_name RC_NamesTable
[] =
386 { rne
, STRING_COMMA_LEN ("rn-sae") },
387 { rd
, STRING_COMMA_LEN ("rd-sae") },
388 { ru
, STRING_COMMA_LEN ("ru-sae") },
389 { rz
, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly
, STRING_COMMA_LEN ("sae") },
393 /* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
395 const char extra_symbol_chars
[] = "*%-([{"
404 #if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
406 && !defined (TE_GNU) \
407 && !defined (TE_LINUX) \
408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
410 && !defined (TE_FreeBSD) \
411 && !defined (TE_DragonFly) \
412 && !defined (TE_NetBSD)))
413 /* This array holds the chars that always start a comment. If the
414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416 const char *i386_comment_chars
= "#/";
417 #define SVR4_COMMENT_CHARS 1
418 #define PREFIX_SEPARATOR '\\'
421 const char *i386_comment_chars
= "#";
422 #define PREFIX_SEPARATOR '/'
425 /* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
429 first line of the input file. This is because the compiler outputs
430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
432 '/' isn't otherwise defined. */
433 const char line_comment_chars
[] = "#/";
435 const char line_separator_chars
[] = ";";
437 /* Chars that can be used to separate mant from exp in floating point
439 const char EXP_CHARS
[] = "eE";
441 /* Chars that mean this number is a floating point constant
444 const char FLT_CHARS
[] = "fFdDxX";
446 /* Tables for lexical analysis. */
447 static char mnemonic_chars
[256];
448 static char register_chars
[256];
449 static char operand_chars
[256];
450 static char identifier_chars
[256];
451 static char digit_chars
[256];
453 /* Lexical macros. */
454 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455 #define is_operand_char(x) (operand_chars[(unsigned char) x])
456 #define is_register_char(x) (register_chars[(unsigned char) x])
457 #define is_space_char(x) ((x) == ' ')
458 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459 #define is_digit_char(x) (digit_chars[(unsigned char) x])
461 /* All non-digit non-letter characters that may occur in an operand. */
462 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
464 /* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
467 assembler instruction). */
468 static char save_stack
[32];
469 static char *save_stack_p
;
470 #define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472 #define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
475 /* The instruction we're assembling. */
478 /* Possible templates for current insn. */
479 static const templates
*current_templates
;
481 /* Per instruction expressionS buffers: max displacements & immediates. */
482 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
483 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
485 /* Current operand we are working on. */
486 static int this_operand
= -1;
488 /* We support four different modes. FLAG_CODE variable is used to distinguish
496 static enum flag_code flag_code
;
497 static unsigned int object_64bit
;
498 static unsigned int disallow_64bit_reloc
;
499 static int use_rela_relocations
= 0;
501 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
505 /* The ELF ABI to use. */
513 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
516 #if defined (TE_PE) || defined (TE_PEP)
517 /* Use big object file format. */
518 static int use_big_obj
= 0;
521 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
522 /* 1 if generating code for a shared library. */
523 static int shared
= 0;
526 /* 1 for intel syntax,
528 static int intel_syntax
= 0;
530 /* 1 for intel mnemonic,
531 0 if att mnemonic. */
532 static int intel_mnemonic
= !SYSV386_COMPAT
;
534 /* 1 if support old (<= 2.8.1) versions of gcc. */
535 static int old_gcc
= OLDGCC_COMPAT
;
537 /* 1 if pseudo registers are permitted. */
538 static int allow_pseudo_reg
= 0;
540 /* 1 if register prefix % not required. */
541 static int allow_naked_reg
= 0;
543 /* 1 if the assembler should add BND prefix for all control-tranferring
544 instructions supporting it, even if this prefix wasn't specified
546 static int add_bnd_prefix
= 0;
548 /* 1 if pseudo index register, eiz/riz, is allowed . */
549 static int allow_index_reg
= 0;
551 /* 1 if the assembler should ignore LOCK prefix, even if it was
552 specified explicitly. */
553 static int omit_lock_prefix
= 0;
555 /* 1 if the assembler should encode lfence, mfence, and sfence as
556 "lock addl $0, (%{re}sp)". */
557 static int avoid_fence
= 0;
559 static enum check_kind
565 sse_check
, operand_check
= check_warning
;
567 /* Register prefix used for error message. */
568 static const char *register_prefix
= "%";
570 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
571 leave, push, and pop instructions so that gcc has the same stack
572 frame as in 32 bit mode. */
573 static char stackop_size
= '\0';
575 /* Non-zero to optimize code alignment. */
576 int optimize_align_code
= 1;
578 /* Non-zero to quieten some warnings. */
579 static int quiet_warnings
= 0;
582 static const char *cpu_arch_name
= NULL
;
583 static char *cpu_sub_arch_name
= NULL
;
585 /* CPU feature flags. */
586 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
588 /* If we have selected a cpu we are generating instructions for. */
589 static int cpu_arch_tune_set
= 0;
591 /* Cpu we are generating instructions for. */
592 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
594 /* CPU feature flags of cpu we are generating instructions for. */
595 static i386_cpu_flags cpu_arch_tune_flags
;
597 /* CPU instruction set architecture used. */
598 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
600 /* CPU feature flags of instruction set architecture used. */
601 i386_cpu_flags cpu_arch_isa_flags
;
603 /* If set, conditional jumps are not automatically promoted to handle
604 larger than a byte offset. */
605 static unsigned int no_cond_jump_promotion
= 0;
607 /* Encode SSE instructions with VEX prefix. */
608 static unsigned int sse2avx
;
610 /* Encode scalar AVX instructions with specific vector length. */
617 /* Encode scalar EVEX LIG instructions with specific vector length. */
625 /* Encode EVEX WIG instructions with specific evex.w. */
632 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
633 static enum rc_type evexrcig
= rne
;
635 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
636 static symbolS
*GOT_symbol
;
638 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
639 unsigned int x86_dwarf2_return_column
;
641 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
642 int x86_cie_data_alignment
;
644 /* Interface to relax_segment.
645 There are 3 major relax states for 386 jump insns because the
646 different types of jumps add different sizes to frags when we're
647 figuring out what sort of jump to choose to reach a given label. */
650 #define UNCOND_JUMP 0
652 #define COND_JUMP86 2
657 #define SMALL16 (SMALL | CODE16)
659 #define BIG16 (BIG | CODE16)
663 #define INLINE __inline__
669 #define ENCODE_RELAX_STATE(type, size) \
670 ((relax_substateT) (((type) << 2) | (size)))
671 #define TYPE_FROM_RELAX_STATE(s) \
673 #define DISP_SIZE_FROM_RELAX_STATE(s) \
674 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
676 /* This table is used by relax_frag to promote short jumps to long
677 ones where necessary. SMALL (short) jumps may be promoted to BIG
678 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
679 don't allow a short jump in a 32 bit code segment to be promoted to
680 a 16 bit offset jump because it's slower (requires data size
681 prefix), and doesn't work, unless the destination is in the bottom
682 64k of the code segment (The top 16 bits of eip are zeroed). */
684 const relax_typeS md_relax_table
[] =
687 1) most positive reach of this state,
688 2) most negative reach of this state,
689 3) how many bytes this mode will have in the variable part of the frag
690 4) which index into the table to try if we can't fit into this one. */
692 /* UNCOND_JUMP states. */
693 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
694 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
695 /* dword jmp adds 4 bytes to frag:
696 0 extra opcode bytes, 4 displacement bytes. */
698 /* word jmp adds 2 byte2 to frag:
699 0 extra opcode bytes, 2 displacement bytes. */
702 /* COND_JUMP states. */
703 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
704 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
705 /* dword conditionals adds 5 bytes to frag:
706 1 extra opcode byte, 4 displacement bytes. */
708 /* word conditionals add 3 bytes to frag:
709 1 extra opcode byte, 2 displacement bytes. */
712 /* COND_JUMP86 states. */
713 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
714 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
715 /* dword conditionals adds 5 bytes to frag:
716 1 extra opcode byte, 4 displacement bytes. */
718 /* word conditionals add 4 bytes to frag:
719 1 displacement byte and a 3 byte long branch insn. */
723 static const arch_entry cpu_arch
[] =
725 /* Do not replace the first two entries - i386_target_format()
726 relies on them being there in this order. */
727 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
728 CPU_GENERIC32_FLAGS
, 0, 0 },
729 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
730 CPU_GENERIC64_FLAGS
, 0, 0 },
731 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
732 CPU_NONE_FLAGS
, 0, 0 },
733 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
734 CPU_I186_FLAGS
, 0, 0 },
735 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
736 CPU_I286_FLAGS
, 0, 0 },
737 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
738 CPU_I386_FLAGS
, 0, 0 },
739 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
740 CPU_I486_FLAGS
, 0, 0 },
741 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
742 CPU_I586_FLAGS
, 0, 0 },
743 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
744 CPU_I686_FLAGS
, 0, 0 },
745 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
746 CPU_I586_FLAGS
, 0, 0 },
747 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
748 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
749 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
750 CPU_P2_FLAGS
, 0, 0 },
751 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
752 CPU_P3_FLAGS
, 0, 0 },
753 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
754 CPU_P4_FLAGS
, 0, 0 },
755 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
756 CPU_CORE_FLAGS
, 0, 0 },
757 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
758 CPU_NOCONA_FLAGS
, 0, 0 },
759 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
760 CPU_CORE_FLAGS
, 1, 0 },
761 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
762 CPU_CORE_FLAGS
, 0, 0 },
763 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
764 CPU_CORE2_FLAGS
, 1, 0 },
765 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
766 CPU_CORE2_FLAGS
, 0, 0 },
767 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
768 CPU_COREI7_FLAGS
, 0, 0 },
769 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
770 CPU_L1OM_FLAGS
, 0, 0 },
771 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
772 CPU_K1OM_FLAGS
, 0, 0 },
773 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
774 CPU_IAMCU_FLAGS
, 0, 0 },
775 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
776 CPU_K6_FLAGS
, 0, 0 },
777 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
778 CPU_K6_2_FLAGS
, 0, 0 },
779 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
780 CPU_ATHLON_FLAGS
, 0, 0 },
781 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
782 CPU_K8_FLAGS
, 1, 0 },
783 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
784 CPU_K8_FLAGS
, 0, 0 },
785 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
786 CPU_K8_FLAGS
, 0, 0 },
787 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
788 CPU_AMDFAM10_FLAGS
, 0, 0 },
789 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
790 CPU_BDVER1_FLAGS
, 0, 0 },
791 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
792 CPU_BDVER2_FLAGS
, 0, 0 },
793 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
794 CPU_BDVER3_FLAGS
, 0, 0 },
795 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
796 CPU_BDVER4_FLAGS
, 0, 0 },
797 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
798 CPU_ZNVER1_FLAGS
, 0, 0 },
799 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
800 CPU_BTVER1_FLAGS
, 0, 0 },
801 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
802 CPU_BTVER2_FLAGS
, 0, 0 },
803 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
804 CPU_8087_FLAGS
, 0, 0 },
805 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
806 CPU_287_FLAGS
, 0, 0 },
807 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
808 CPU_387_FLAGS
, 0, 0 },
809 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
810 CPU_ANY87_FLAGS
, 0, 1 },
811 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
812 CPU_MMX_FLAGS
, 0, 0 },
813 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
814 CPU_3DNOWA_FLAGS
, 0, 1 },
815 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
816 CPU_SSE_FLAGS
, 0, 0 },
817 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
818 CPU_SSE2_FLAGS
, 0, 0 },
819 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
820 CPU_SSE3_FLAGS
, 0, 0 },
821 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
822 CPU_SSSE3_FLAGS
, 0, 0 },
823 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
824 CPU_SSE4_1_FLAGS
, 0, 0 },
825 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
826 CPU_SSE4_2_FLAGS
, 0, 0 },
827 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
828 CPU_SSE4_2_FLAGS
, 0, 0 },
829 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
830 CPU_ANY_SSE_FLAGS
, 0, 1 },
831 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
832 CPU_AVX_FLAGS
, 0, 0 },
833 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
834 CPU_AVX2_FLAGS
, 0, 0 },
835 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
836 CPU_AVX512F_FLAGS
, 0, 0 },
837 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
838 CPU_AVX512CD_FLAGS
, 0, 0 },
839 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
840 CPU_AVX512ER_FLAGS
, 0, 0 },
841 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
842 CPU_AVX512PF_FLAGS
, 0, 0 },
843 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
844 CPU_AVX512DQ_FLAGS
, 0, 0 },
845 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
846 CPU_AVX512BW_FLAGS
, 0, 0 },
847 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
848 CPU_AVX512VL_FLAGS
, 0, 0 },
849 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
850 CPU_ANY_AVX_FLAGS
, 0, 1 },
851 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
852 CPU_VMX_FLAGS
, 0, 0 },
853 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
854 CPU_VMFUNC_FLAGS
, 0, 0 },
855 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
856 CPU_SMX_FLAGS
, 0, 0 },
857 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
858 CPU_XSAVE_FLAGS
, 0, 0 },
859 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
860 CPU_XSAVEOPT_FLAGS
, 0, 0 },
861 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
862 CPU_XSAVEC_FLAGS
, 0, 0 },
863 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
864 CPU_XSAVES_FLAGS
, 0, 0 },
865 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
866 CPU_AES_FLAGS
, 0, 0 },
867 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
868 CPU_PCLMUL_FLAGS
, 0, 0 },
869 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
870 CPU_PCLMUL_FLAGS
, 1, 0 },
871 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
872 CPU_FSGSBASE_FLAGS
, 0, 0 },
873 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
874 CPU_RDRND_FLAGS
, 0, 0 },
875 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
876 CPU_F16C_FLAGS
, 0, 0 },
877 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
878 CPU_BMI2_FLAGS
, 0, 0 },
879 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
880 CPU_FMA_FLAGS
, 0, 0 },
881 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
882 CPU_FMA4_FLAGS
, 0, 0 },
883 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
884 CPU_XOP_FLAGS
, 0, 0 },
885 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
886 CPU_LWP_FLAGS
, 0, 0 },
887 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
888 CPU_MOVBE_FLAGS
, 0, 0 },
889 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
890 CPU_CX16_FLAGS
, 0, 0 },
891 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
892 CPU_EPT_FLAGS
, 0, 0 },
893 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
894 CPU_LZCNT_FLAGS
, 0, 0 },
895 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
896 CPU_HLE_FLAGS
, 0, 0 },
897 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
898 CPU_RTM_FLAGS
, 0, 0 },
899 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
900 CPU_INVPCID_FLAGS
, 0, 0 },
901 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
902 CPU_CLFLUSH_FLAGS
, 0, 0 },
903 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
904 CPU_NOP_FLAGS
, 0, 0 },
905 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
906 CPU_SYSCALL_FLAGS
, 0, 0 },
907 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
908 CPU_RDTSCP_FLAGS
, 0, 0 },
909 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
910 CPU_3DNOW_FLAGS
, 0, 0 },
911 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
912 CPU_3DNOWA_FLAGS
, 0, 0 },
913 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
914 CPU_PADLOCK_FLAGS
, 0, 0 },
915 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
916 CPU_SVME_FLAGS
, 1, 0 },
917 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
918 CPU_SVME_FLAGS
, 0, 0 },
919 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
920 CPU_SSE4A_FLAGS
, 0, 0 },
921 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
922 CPU_ABM_FLAGS
, 0, 0 },
923 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
924 CPU_BMI_FLAGS
, 0, 0 },
925 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
926 CPU_TBM_FLAGS
, 0, 0 },
927 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
928 CPU_ADX_FLAGS
, 0, 0 },
929 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
930 CPU_RDSEED_FLAGS
, 0, 0 },
931 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
932 CPU_PRFCHW_FLAGS
, 0, 0 },
933 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
934 CPU_SMAP_FLAGS
, 0, 0 },
935 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
936 CPU_MPX_FLAGS
, 0, 0 },
937 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
938 CPU_SHA_FLAGS
, 0, 0 },
939 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
940 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
941 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
942 CPU_PREFETCHWT1_FLAGS
, 0, 0 },
943 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
944 CPU_SE1_FLAGS
, 0, 0 },
945 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
946 CPU_CLWB_FLAGS
, 0, 0 },
947 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
948 CPU_PCOMMIT_FLAGS
, 0, 0 },
949 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
950 CPU_AVX512IFMA_FLAGS
, 0, 0 },
951 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
952 CPU_AVX512VBMI_FLAGS
, 0, 0 },
953 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
954 CPU_CLZERO_FLAGS
, 0, 0 },
955 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
956 CPU_MWAITX_FLAGS
, 0, 0 },
957 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
958 CPU_OSPKE_FLAGS
, 0, 0 },
962 /* Like s_lcomm_internal in gas/read.c but the alignment string
963 is allowed to be optional. */
966 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
973 && *input_line_pointer
== ',')
975 align
= parse_align (needs_align
- 1);
977 if (align
== (addressT
) -1)
992 bss_alloc (symbolP
, size
, align
);
997 pe_lcomm (int needs_align
)
999 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1003 const pseudo_typeS md_pseudo_table
[] =
1005 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1006 {"align", s_align_bytes
, 0},
1008 {"align", s_align_ptwo
, 0},
1010 {"arch", set_cpu_arch
, 0},
1014 {"lcomm", pe_lcomm
, 1},
1016 {"ffloat", float_cons
, 'f'},
1017 {"dfloat", float_cons
, 'd'},
1018 {"tfloat", float_cons
, 'x'},
1020 {"slong", signed_cons
, 4},
1021 {"noopt", s_ignore
, 0},
1022 {"optim", s_ignore
, 0},
1023 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1024 {"code16", set_code_flag
, CODE_16BIT
},
1025 {"code32", set_code_flag
, CODE_32BIT
},
1026 {"code64", set_code_flag
, CODE_64BIT
},
1027 {"intel_syntax", set_intel_syntax
, 1},
1028 {"att_syntax", set_intel_syntax
, 0},
1029 {"intel_mnemonic", set_intel_mnemonic
, 1},
1030 {"att_mnemonic", set_intel_mnemonic
, 0},
1031 {"allow_index_reg", set_allow_index_reg
, 1},
1032 {"disallow_index_reg", set_allow_index_reg
, 0},
1033 {"sse_check", set_check
, 0},
1034 {"operand_check", set_check
, 1},
1035 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1036 {"largecomm", handle_large_common
, 0},
1038 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1039 {"loc", dwarf2_directive_loc
, 0},
1040 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1043 {"secrel32", pe_directive_secrel
, 0},
1048 /* For interface with expression (). */
1049 extern char *input_line_pointer
;
1051 /* Hash table for instruction mnemonic lookup. */
1052 static struct hash_control
*op_hash
;
1054 /* Hash table for register lookup. */
1055 static struct hash_control
*reg_hash
;
1058 i386_align_code (fragS
*fragP
, int count
)
1060 /* Various efficient no-op patterns for aligning code labels.
1061 Note: Don't try to assemble the instructions in the comments.
1062 0L and 0w are not legal. */
1063 static const char f32_1
[] =
1065 static const char f32_2
[] =
1066 {0x66,0x90}; /* xchg %ax,%ax */
1067 static const char f32_3
[] =
1068 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1069 static const char f32_4
[] =
1070 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1071 static const char f32_5
[] =
1073 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1074 static const char f32_6
[] =
1075 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1076 static const char f32_7
[] =
1077 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1078 static const char f32_8
[] =
1080 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1081 static const char f32_9
[] =
1082 {0x89,0xf6, /* movl %esi,%esi */
1083 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1084 static const char f32_10
[] =
1085 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1086 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1087 static const char f32_11
[] =
1088 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1089 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1090 static const char f32_12
[] =
1091 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1092 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1093 static const char f32_13
[] =
1094 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1095 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1096 static const char f32_14
[] =
1097 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1098 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1099 static const char f16_3
[] =
1100 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1101 static const char f16_4
[] =
1102 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1103 static const char f16_5
[] =
1105 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1106 static const char f16_6
[] =
1107 {0x89,0xf6, /* mov %si,%si */
1108 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1109 static const char f16_7
[] =
1110 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1111 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1112 static const char f16_8
[] =
1113 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1114 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1115 static const char jump_31
[] =
1116 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1117 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1118 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1119 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1120 static const char *const f32_patt
[] = {
1121 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1122 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1124 static const char *const f16_patt
[] = {
1125 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1127 /* nopl (%[re]ax) */
1128 static const char alt_3
[] =
1130 /* nopl 0(%[re]ax) */
1131 static const char alt_4
[] =
1132 {0x0f,0x1f,0x40,0x00};
1133 /* nopl 0(%[re]ax,%[re]ax,1) */
1134 static const char alt_5
[] =
1135 {0x0f,0x1f,0x44,0x00,0x00};
1136 /* nopw 0(%[re]ax,%[re]ax,1) */
1137 static const char alt_6
[] =
1138 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1139 /* nopl 0L(%[re]ax) */
1140 static const char alt_7
[] =
1141 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1142 /* nopl 0L(%[re]ax,%[re]ax,1) */
1143 static const char alt_8
[] =
1144 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1145 /* nopw 0L(%[re]ax,%[re]ax,1) */
1146 static const char alt_9
[] =
1147 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1148 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1149 static const char alt_10
[] =
1150 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1151 static const char *const alt_patt
[] = {
1152 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1156 /* Only align for at least a positive non-zero boundary. */
1157 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1160 /* We need to decide which NOP sequence to use for 32bit and
1161 64bit. When -mtune= is used:
1163 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1164 PROCESSOR_GENERIC32, f32_patt will be used.
1165 2. For the rest, alt_patt will be used.
1167 When -mtune= isn't used, alt_patt will be used if
1168 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1171 When -march= or .arch is used, we can't use anything beyond
1172 cpu_arch_isa_flags. */
1174 if (flag_code
== CODE_16BIT
)
1178 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1180 /* Adjust jump offset. */
1181 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1184 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1185 f16_patt
[count
- 1], count
);
1189 const char *const *patt
= NULL
;
1191 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1193 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1194 switch (cpu_arch_tune
)
1196 case PROCESSOR_UNKNOWN
:
1197 /* We use cpu_arch_isa_flags to check if we SHOULD
1198 optimize with nops. */
1199 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1204 case PROCESSOR_PENTIUM4
:
1205 case PROCESSOR_NOCONA
:
1206 case PROCESSOR_CORE
:
1207 case PROCESSOR_CORE2
:
1208 case PROCESSOR_COREI7
:
1209 case PROCESSOR_L1OM
:
1210 case PROCESSOR_K1OM
:
1211 case PROCESSOR_GENERIC64
:
1213 case PROCESSOR_ATHLON
:
1215 case PROCESSOR_AMDFAM10
:
1217 case PROCESSOR_ZNVER
:
1221 case PROCESSOR_I386
:
1222 case PROCESSOR_I486
:
1223 case PROCESSOR_PENTIUM
:
1224 case PROCESSOR_PENTIUMPRO
:
1225 case PROCESSOR_IAMCU
:
1226 case PROCESSOR_GENERIC32
:
1233 switch (fragP
->tc_frag_data
.tune
)
1235 case PROCESSOR_UNKNOWN
:
1236 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1237 PROCESSOR_UNKNOWN. */
1241 case PROCESSOR_I386
:
1242 case PROCESSOR_I486
:
1243 case PROCESSOR_PENTIUM
:
1244 case PROCESSOR_IAMCU
:
1246 case PROCESSOR_ATHLON
:
1248 case PROCESSOR_AMDFAM10
:
1250 case PROCESSOR_ZNVER
:
1252 case PROCESSOR_GENERIC32
:
1253 /* We use cpu_arch_isa_flags to check if we CAN optimize
1255 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1260 case PROCESSOR_PENTIUMPRO
:
1261 case PROCESSOR_PENTIUM4
:
1262 case PROCESSOR_NOCONA
:
1263 case PROCESSOR_CORE
:
1264 case PROCESSOR_CORE2
:
1265 case PROCESSOR_COREI7
:
1266 case PROCESSOR_L1OM
:
1267 case PROCESSOR_K1OM
:
1268 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1273 case PROCESSOR_GENERIC64
:
1279 if (patt
== f32_patt
)
1281 /* If the padding is less than 15 bytes, we use the normal
1282 ones. Otherwise, we use a jump instruction and adjust
1286 /* For 64bit, the limit is 3 bytes. */
1287 if (flag_code
== CODE_64BIT
1288 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1293 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1294 patt
[count
- 1], count
);
1297 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1299 /* Adjust jump offset. */
1300 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1305 /* Maximum length of an instruction is 10 byte. If the
1306 padding is greater than 10 bytes and we don't use jump,
1307 we have to break it into smaller pieces. */
1308 int padding
= count
;
1309 while (padding
> 10)
1312 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1317 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1318 patt
[padding
- 1], padding
);
1321 fragP
->fr_var
= count
;
1325 operand_type_all_zero (const union i386_operand_type
*x
)
1327 switch (ARRAY_SIZE(x
->array
))
1336 return !x
->array
[0];
1343 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1345 switch (ARRAY_SIZE(x
->array
))
1360 operand_type_equal (const union i386_operand_type
*x
,
1361 const union i386_operand_type
*y
)
1363 switch (ARRAY_SIZE(x
->array
))
1366 if (x
->array
[2] != y
->array
[2])
1369 if (x
->array
[1] != y
->array
[1])
1372 return x
->array
[0] == y
->array
[0];
1380 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1382 switch (ARRAY_SIZE(x
->array
))
1391 return !x
->array
[0];
1398 cpu_flags_equal (const union i386_cpu_flags
*x
,
1399 const union i386_cpu_flags
*y
)
1401 switch (ARRAY_SIZE(x
->array
))
1404 if (x
->array
[2] != y
->array
[2])
1407 if (x
->array
[1] != y
->array
[1])
1410 return x
->array
[0] == y
->array
[0];
1418 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1420 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1421 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1424 static INLINE i386_cpu_flags
1425 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1427 switch (ARRAY_SIZE (x
.array
))
1430 x
.array
[2] &= y
.array
[2];
1432 x
.array
[1] &= y
.array
[1];
1434 x
.array
[0] &= y
.array
[0];
1442 static INLINE i386_cpu_flags
1443 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1445 switch (ARRAY_SIZE (x
.array
))
1448 x
.array
[2] |= y
.array
[2];
1450 x
.array
[1] |= y
.array
[1];
1452 x
.array
[0] |= y
.array
[0];
1460 static INLINE i386_cpu_flags
1461 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1463 switch (ARRAY_SIZE (x
.array
))
1466 x
.array
[2] &= ~y
.array
[2];
1468 x
.array
[1] &= ~y
.array
[1];
1470 x
.array
[0] &= ~y
.array
[0];
1479 valid_iamcu_cpu_flags (const i386_cpu_flags
*flags
)
1481 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
1483 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_COMPAT_FLAGS
;
1484 i386_cpu_flags compat_flags
;
1485 compat_flags
= cpu_flags_and_not (*flags
, iamcu_flags
);
1486 return cpu_flags_all_zero (&compat_flags
);
1492 #define CPU_FLAGS_ARCH_MATCH 0x1
1493 #define CPU_FLAGS_64BIT_MATCH 0x2
1494 #define CPU_FLAGS_AES_MATCH 0x4
1495 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1496 #define CPU_FLAGS_AVX_MATCH 0x10
1498 #define CPU_FLAGS_32BIT_MATCH \
1499 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1500 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1501 #define CPU_FLAGS_PERFECT_MATCH \
1502 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1504 /* Return CPU flags match bits. */
1507 cpu_flags_match (const insn_template
*t
)
1509 i386_cpu_flags x
= t
->cpu_flags
;
1510 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1512 x
.bitfield
.cpu64
= 0;
1513 x
.bitfield
.cpuno64
= 0;
1515 if (cpu_flags_all_zero (&x
))
1517 /* This instruction is available on all archs. */
1518 match
|= CPU_FLAGS_32BIT_MATCH
;
1522 /* This instruction is available only on some archs. */
1523 i386_cpu_flags cpu
= cpu_arch_flags
;
1525 cpu
.bitfield
.cpu64
= 0;
1526 cpu
.bitfield
.cpuno64
= 0;
1527 cpu
= cpu_flags_and (x
, cpu
);
1528 if (!cpu_flags_all_zero (&cpu
))
1530 if (x
.bitfield
.cpuavx
)
1532 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1533 if (cpu
.bitfield
.cpuavx
)
1535 /* Check SSE2AVX. */
1536 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1538 match
|= (CPU_FLAGS_ARCH_MATCH
1539 | CPU_FLAGS_AVX_MATCH
);
1541 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1542 match
|= CPU_FLAGS_AES_MATCH
;
1544 if (!x
.bitfield
.cpupclmul
1545 || cpu
.bitfield
.cpupclmul
)
1546 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1550 match
|= CPU_FLAGS_ARCH_MATCH
;
1553 match
|= CPU_FLAGS_32BIT_MATCH
;
1559 static INLINE i386_operand_type
1560 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1562 switch (ARRAY_SIZE (x
.array
))
1565 x
.array
[2] &= y
.array
[2];
1567 x
.array
[1] &= y
.array
[1];
1569 x
.array
[0] &= y
.array
[0];
1577 static INLINE i386_operand_type
1578 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1580 switch (ARRAY_SIZE (x
.array
))
1583 x
.array
[2] |= y
.array
[2];
1585 x
.array
[1] |= y
.array
[1];
1587 x
.array
[0] |= y
.array
[0];
1595 static INLINE i386_operand_type
1596 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1598 switch (ARRAY_SIZE (x
.array
))
1601 x
.array
[2] ^= y
.array
[2];
1603 x
.array
[1] ^= y
.array
[1];
1605 x
.array
[0] ^= y
.array
[0];
1613 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1614 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1615 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1616 static const i386_operand_type inoutportreg
1617 = OPERAND_TYPE_INOUTPORTREG
;
1618 static const i386_operand_type reg16_inoutportreg
1619 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1620 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1621 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1622 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1623 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1624 static const i386_operand_type anydisp
1625 = OPERAND_TYPE_ANYDISP
;
1626 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1627 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1628 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1629 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1630 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1631 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1632 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1633 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1634 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1635 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1636 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1637 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1638 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1639 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1650 operand_type_check (i386_operand_type t
, enum operand_type c
)
1655 return (t
.bitfield
.reg8
1658 || t
.bitfield
.reg64
);
1661 return (t
.bitfield
.imm8
1665 || t
.bitfield
.imm32s
1666 || t
.bitfield
.imm64
);
1669 return (t
.bitfield
.disp8
1670 || t
.bitfield
.disp16
1671 || t
.bitfield
.disp32
1672 || t
.bitfield
.disp32s
1673 || t
.bitfield
.disp64
);
1676 return (t
.bitfield
.disp8
1677 || t
.bitfield
.disp16
1678 || t
.bitfield
.disp32
1679 || t
.bitfield
.disp32s
1680 || t
.bitfield
.disp64
1681 || t
.bitfield
.baseindex
);
1690 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1691 operand J for instruction template T. */
1694 match_reg_size (const insn_template
*t
, unsigned int j
)
1696 return !((i
.types
[j
].bitfield
.byte
1697 && !t
->operand_types
[j
].bitfield
.byte
)
1698 || (i
.types
[j
].bitfield
.word
1699 && !t
->operand_types
[j
].bitfield
.word
)
1700 || (i
.types
[j
].bitfield
.dword
1701 && !t
->operand_types
[j
].bitfield
.dword
)
1702 || (i
.types
[j
].bitfield
.qword
1703 && !t
->operand_types
[j
].bitfield
.qword
));
1706 /* Return 1 if there is no conflict in any size on operand J for
1707 instruction template T. */
1710 match_mem_size (const insn_template
*t
, unsigned int j
)
1712 return (match_reg_size (t
, j
)
1713 && !((i
.types
[j
].bitfield
.unspecified
1715 && !t
->operand_types
[j
].bitfield
.unspecified
)
1716 || (i
.types
[j
].bitfield
.fword
1717 && !t
->operand_types
[j
].bitfield
.fword
)
1718 || (i
.types
[j
].bitfield
.tbyte
1719 && !t
->operand_types
[j
].bitfield
.tbyte
)
1720 || (i
.types
[j
].bitfield
.xmmword
1721 && !t
->operand_types
[j
].bitfield
.xmmword
)
1722 || (i
.types
[j
].bitfield
.ymmword
1723 && !t
->operand_types
[j
].bitfield
.ymmword
)
1724 || (i
.types
[j
].bitfield
.zmmword
1725 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1728 /* Return 1 if there is no size conflict on any operands for
1729 instruction template T. */
1732 operand_size_match (const insn_template
*t
)
1737 /* Don't check jump instructions. */
1738 if (t
->opcode_modifier
.jump
1739 || t
->opcode_modifier
.jumpbyte
1740 || t
->opcode_modifier
.jumpdword
1741 || t
->opcode_modifier
.jumpintersegment
)
1744 /* Check memory and accumulator operand size. */
1745 for (j
= 0; j
< i
.operands
; j
++)
1747 if (t
->operand_types
[j
].bitfield
.anysize
)
1750 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1756 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1765 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1768 i
.error
= operand_size_mismatch
;
1772 /* Check reverse. */
1773 gas_assert (i
.operands
== 2);
1776 for (j
= 0; j
< 2; j
++)
1778 if (t
->operand_types
[j
].bitfield
.acc
1779 && !match_reg_size (t
, j
? 0 : 1))
1782 if (i
.types
[j
].bitfield
.mem
1783 && !match_mem_size (t
, j
? 0 : 1))
1791 operand_type_match (i386_operand_type overlap
,
1792 i386_operand_type given
)
1794 i386_operand_type temp
= overlap
;
1796 temp
.bitfield
.jumpabsolute
= 0;
1797 temp
.bitfield
.unspecified
= 0;
1798 temp
.bitfield
.byte
= 0;
1799 temp
.bitfield
.word
= 0;
1800 temp
.bitfield
.dword
= 0;
1801 temp
.bitfield
.fword
= 0;
1802 temp
.bitfield
.qword
= 0;
1803 temp
.bitfield
.tbyte
= 0;
1804 temp
.bitfield
.xmmword
= 0;
1805 temp
.bitfield
.ymmword
= 0;
1806 temp
.bitfield
.zmmword
= 0;
1807 if (operand_type_all_zero (&temp
))
1810 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1811 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1815 i
.error
= operand_type_mismatch
;
1819 /* If given types g0 and g1 are registers they must be of the same type
1820 unless the expected operand type register overlap is null.
1821 Note that Acc in a template matches every size of reg. */
1824 operand_type_register_match (i386_operand_type m0
,
1825 i386_operand_type g0
,
1826 i386_operand_type t0
,
1827 i386_operand_type m1
,
1828 i386_operand_type g1
,
1829 i386_operand_type t1
)
1831 if (!operand_type_check (g0
, reg
))
1834 if (!operand_type_check (g1
, reg
))
1837 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1838 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1839 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1840 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1843 if (m0
.bitfield
.acc
)
1845 t0
.bitfield
.reg8
= 1;
1846 t0
.bitfield
.reg16
= 1;
1847 t0
.bitfield
.reg32
= 1;
1848 t0
.bitfield
.reg64
= 1;
1851 if (m1
.bitfield
.acc
)
1853 t1
.bitfield
.reg8
= 1;
1854 t1
.bitfield
.reg16
= 1;
1855 t1
.bitfield
.reg32
= 1;
1856 t1
.bitfield
.reg64
= 1;
1859 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1860 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1861 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1862 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1865 i
.error
= register_type_mismatch
;
1870 static INLINE
unsigned int
1871 register_number (const reg_entry
*r
)
1873 unsigned int nr
= r
->reg_num
;
1875 if (r
->reg_flags
& RegRex
)
1881 static INLINE
unsigned int
1882 mode_from_disp_size (i386_operand_type t
)
1884 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1886 else if (t
.bitfield
.disp16
1887 || t
.bitfield
.disp32
1888 || t
.bitfield
.disp32s
)
1895 fits_in_signed_byte (addressT num
)
1897 return num
+ 0x80 <= 0xff;
1901 fits_in_unsigned_byte (addressT num
)
1907 fits_in_unsigned_word (addressT num
)
1909 return num
<= 0xffff;
1913 fits_in_signed_word (addressT num
)
1915 return num
+ 0x8000 <= 0xffff;
1919 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1924 return num
+ 0x80000000 <= 0xffffffff;
1926 } /* fits_in_signed_long() */
1929 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
1934 return num
<= 0xffffffff;
1936 } /* fits_in_unsigned_long() */
1939 fits_in_vec_disp8 (offsetT num
)
1941 int shift
= i
.memshift
;
1947 mask
= (1 << shift
) - 1;
1949 /* Return 0 if NUM isn't properly aligned. */
1953 /* Check if NUM will fit in 8bit after shift. */
1954 return fits_in_signed_byte (num
>> shift
);
1958 fits_in_imm4 (offsetT num
)
1960 return (num
& 0xf) == num
;
1963 static i386_operand_type
1964 smallest_imm_type (offsetT num
)
1966 i386_operand_type t
;
1968 operand_type_set (&t
, 0);
1969 t
.bitfield
.imm64
= 1;
1971 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1973 /* This code is disabled on the 486 because all the Imm1 forms
1974 in the opcode table are slower on the i486. They're the
1975 versions with the implicitly specified single-position
1976 displacement, which has another syntax if you really want to
1978 t
.bitfield
.imm1
= 1;
1979 t
.bitfield
.imm8
= 1;
1980 t
.bitfield
.imm8s
= 1;
1981 t
.bitfield
.imm16
= 1;
1982 t
.bitfield
.imm32
= 1;
1983 t
.bitfield
.imm32s
= 1;
1985 else if (fits_in_signed_byte (num
))
1987 t
.bitfield
.imm8
= 1;
1988 t
.bitfield
.imm8s
= 1;
1989 t
.bitfield
.imm16
= 1;
1990 t
.bitfield
.imm32
= 1;
1991 t
.bitfield
.imm32s
= 1;
1993 else if (fits_in_unsigned_byte (num
))
1995 t
.bitfield
.imm8
= 1;
1996 t
.bitfield
.imm16
= 1;
1997 t
.bitfield
.imm32
= 1;
1998 t
.bitfield
.imm32s
= 1;
2000 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2002 t
.bitfield
.imm16
= 1;
2003 t
.bitfield
.imm32
= 1;
2004 t
.bitfield
.imm32s
= 1;
2006 else if (fits_in_signed_long (num
))
2008 t
.bitfield
.imm32
= 1;
2009 t
.bitfield
.imm32s
= 1;
2011 else if (fits_in_unsigned_long (num
))
2012 t
.bitfield
.imm32
= 1;
2018 offset_in_range (offsetT val
, int size
)
2024 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2025 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2026 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2028 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2034 /* If BFD64, sign extend val for 32bit address mode. */
2035 if (flag_code
!= CODE_64BIT
2036 || i
.prefix
[ADDR_PREFIX
])
2037 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2038 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2041 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2043 char buf1
[40], buf2
[40];
2045 sprint_value (buf1
, val
);
2046 sprint_value (buf2
, val
& mask
);
2047 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2061 a. PREFIX_EXIST if attempting to add a prefix where one from the
2062 same class already exists.
2063 b. PREFIX_LOCK if lock prefix is added.
2064 c. PREFIX_REP if rep/repne prefix is added.
2065 d. PREFIX_OTHER if other prefix is added.
2068 static enum PREFIX_GROUP
2069 add_prefix (unsigned int prefix
)
2071 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2074 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2075 && flag_code
== CODE_64BIT
)
2077 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2078 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2079 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2090 case CS_PREFIX_OPCODE
:
2091 case DS_PREFIX_OPCODE
:
2092 case ES_PREFIX_OPCODE
:
2093 case FS_PREFIX_OPCODE
:
2094 case GS_PREFIX_OPCODE
:
2095 case SS_PREFIX_OPCODE
:
2099 case REPNE_PREFIX_OPCODE
:
2100 case REPE_PREFIX_OPCODE
:
2105 case LOCK_PREFIX_OPCODE
:
2114 case ADDR_PREFIX_OPCODE
:
2118 case DATA_PREFIX_OPCODE
:
2122 if (i
.prefix
[q
] != 0)
2130 i
.prefix
[q
] |= prefix
;
2133 as_bad (_("same type of prefix used twice"));
2139 update_code_flag (int value
, int check
)
2141 PRINTF_LIKE ((*as_error
));
2143 flag_code
= (enum flag_code
) value
;
2144 if (flag_code
== CODE_64BIT
)
2146 cpu_arch_flags
.bitfield
.cpu64
= 1;
2147 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2151 cpu_arch_flags
.bitfield
.cpu64
= 0;
2152 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2154 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2157 as_error
= as_fatal
;
2160 (*as_error
) (_("64bit mode not supported on `%s'."),
2161 cpu_arch_name
? cpu_arch_name
: default_arch
);
2163 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2166 as_error
= as_fatal
;
2169 (*as_error
) (_("32bit mode not supported on `%s'."),
2170 cpu_arch_name
? cpu_arch_name
: default_arch
);
2172 stackop_size
= '\0';
2176 set_code_flag (int value
)
2178 update_code_flag (value
, 0);
2182 set_16bit_gcc_code_flag (int new_code_flag
)
2184 flag_code
= (enum flag_code
) new_code_flag
;
2185 if (flag_code
!= CODE_16BIT
)
2187 cpu_arch_flags
.bitfield
.cpu64
= 0;
2188 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2189 stackop_size
= LONG_MNEM_SUFFIX
;
2193 set_intel_syntax (int syntax_flag
)
2195 /* Find out if register prefixing is specified. */
2196 int ask_naked_reg
= 0;
2199 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2202 int e
= get_symbol_name (&string
);
2204 if (strcmp (string
, "prefix") == 0)
2206 else if (strcmp (string
, "noprefix") == 0)
2209 as_bad (_("bad argument to syntax directive."));
2210 (void) restore_line_pointer (e
);
2212 demand_empty_rest_of_line ();
2214 intel_syntax
= syntax_flag
;
2216 if (ask_naked_reg
== 0)
2217 allow_naked_reg
= (intel_syntax
2218 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2220 allow_naked_reg
= (ask_naked_reg
< 0);
2222 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2224 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2225 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2226 register_prefix
= allow_naked_reg
? "" : "%";
2230 set_intel_mnemonic (int mnemonic_flag
)
2232 intel_mnemonic
= mnemonic_flag
;
2236 set_allow_index_reg (int flag
)
2238 allow_index_reg
= flag
;
2242 set_check (int what
)
2244 enum check_kind
*kind
;
2249 kind
= &operand_check
;
2260 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2263 int e
= get_symbol_name (&string
);
2265 if (strcmp (string
, "none") == 0)
2267 else if (strcmp (string
, "warning") == 0)
2268 *kind
= check_warning
;
2269 else if (strcmp (string
, "error") == 0)
2270 *kind
= check_error
;
2272 as_bad (_("bad argument to %s_check directive."), str
);
2273 (void) restore_line_pointer (e
);
2276 as_bad (_("missing argument for %s_check directive"), str
);
2278 demand_empty_rest_of_line ();
2282 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2283 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2285 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2286 static const char *arch
;
2288 /* Intel LIOM is only supported on ELF. */
2294 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2295 use default_arch. */
2296 arch
= cpu_arch_name
;
2298 arch
= default_arch
;
2301 /* If we are targeting Intel MCU, we must enable it. */
2302 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2303 || new_flag
.bitfield
.cpuiamcu
)
2306 /* If we are targeting Intel L1OM, we must enable it. */
2307 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2308 || new_flag
.bitfield
.cpul1om
)
2311 /* If we are targeting Intel K1OM, we must enable it. */
2312 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2313 || new_flag
.bitfield
.cpuk1om
)
2316 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2321 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2325 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2328 int e
= get_symbol_name (&string
);
2330 i386_cpu_flags flags
;
2332 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2334 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2336 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2340 cpu_arch_name
= cpu_arch
[j
].name
;
2341 cpu_sub_arch_name
= NULL
;
2342 cpu_arch_flags
= cpu_arch
[j
].flags
;
2343 if (flag_code
== CODE_64BIT
)
2345 cpu_arch_flags
.bitfield
.cpu64
= 1;
2346 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2350 cpu_arch_flags
.bitfield
.cpu64
= 0;
2351 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2353 cpu_arch_isa
= cpu_arch
[j
].type
;
2354 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2355 if (!cpu_arch_tune_set
)
2357 cpu_arch_tune
= cpu_arch_isa
;
2358 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2363 if (!cpu_arch
[j
].negated
)
2364 flags
= cpu_flags_or (cpu_arch_flags
,
2367 flags
= cpu_flags_and_not (cpu_arch_flags
,
2370 if (!valid_iamcu_cpu_flags (&flags
))
2371 as_fatal (_("`%s' isn't valid for Intel MCU"),
2373 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2375 if (cpu_sub_arch_name
)
2377 char *name
= cpu_sub_arch_name
;
2378 cpu_sub_arch_name
= concat (name
,
2380 (const char *) NULL
);
2384 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2385 cpu_arch_flags
= flags
;
2386 cpu_arch_isa_flags
= flags
;
2388 (void) restore_line_pointer (e
);
2389 demand_empty_rest_of_line ();
2393 if (j
>= ARRAY_SIZE (cpu_arch
))
2394 as_bad (_("no such architecture: `%s'"), string
);
2396 *input_line_pointer
= e
;
2399 as_bad (_("missing cpu architecture"));
2401 no_cond_jump_promotion
= 0;
2402 if (*input_line_pointer
== ','
2403 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2408 ++input_line_pointer
;
2409 e
= get_symbol_name (&string
);
2411 if (strcmp (string
, "nojumps") == 0)
2412 no_cond_jump_promotion
= 1;
2413 else if (strcmp (string
, "jumps") == 0)
2416 as_bad (_("no such architecture modifier: `%s'"), string
);
2418 (void) restore_line_pointer (e
);
2421 demand_empty_rest_of_line ();
2424 enum bfd_architecture
2427 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2429 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2430 || flag_code
!= CODE_64BIT
)
2431 as_fatal (_("Intel L1OM is 64bit ELF only"));
2432 return bfd_arch_l1om
;
2434 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2436 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2437 || flag_code
!= CODE_64BIT
)
2438 as_fatal (_("Intel K1OM is 64bit ELF only"));
2439 return bfd_arch_k1om
;
2441 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2443 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2444 || flag_code
== CODE_64BIT
)
2445 as_fatal (_("Intel MCU is 32bit ELF only"));
2446 return bfd_arch_iamcu
;
2449 return bfd_arch_i386
;
2455 if (!strncmp (default_arch
, "x86_64", 6))
2457 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2459 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2460 || default_arch
[6] != '\0')
2461 as_fatal (_("Intel L1OM is 64bit ELF only"));
2462 return bfd_mach_l1om
;
2464 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2466 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2467 || default_arch
[6] != '\0')
2468 as_fatal (_("Intel K1OM is 64bit ELF only"));
2469 return bfd_mach_k1om
;
2471 else if (default_arch
[6] == '\0')
2472 return bfd_mach_x86_64
;
2474 return bfd_mach_x64_32
;
2476 else if (!strcmp (default_arch
, "i386")
2477 || !strcmp (default_arch
, "iamcu"))
2479 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2481 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2482 as_fatal (_("Intel MCU is 32bit ELF only"));
2483 return bfd_mach_i386_iamcu
;
2486 return bfd_mach_i386_i386
;
2489 as_fatal (_("unknown architecture"));
2495 const char *hash_err
;
2497 /* Initialize op_hash hash table. */
2498 op_hash
= hash_new ();
2501 const insn_template
*optab
;
2502 templates
*core_optab
;
2504 /* Setup for loop. */
2506 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2507 core_optab
->start
= optab
;
2512 if (optab
->name
== NULL
2513 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2515 /* different name --> ship out current template list;
2516 add to hash table; & begin anew. */
2517 core_optab
->end
= optab
;
2518 hash_err
= hash_insert (op_hash
,
2520 (void *) core_optab
);
2523 as_fatal (_("can't hash %s: %s"),
2527 if (optab
->name
== NULL
)
2529 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2530 core_optab
->start
= optab
;
2535 /* Initialize reg_hash hash table. */
2536 reg_hash
= hash_new ();
2538 const reg_entry
*regtab
;
2539 unsigned int regtab_size
= i386_regtab_size
;
2541 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2543 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2545 as_fatal (_("can't hash %s: %s"),
2551 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2556 for (c
= 0; c
< 256; c
++)
2561 mnemonic_chars
[c
] = c
;
2562 register_chars
[c
] = c
;
2563 operand_chars
[c
] = c
;
2565 else if (ISLOWER (c
))
2567 mnemonic_chars
[c
] = c
;
2568 register_chars
[c
] = c
;
2569 operand_chars
[c
] = c
;
2571 else if (ISUPPER (c
))
2573 mnemonic_chars
[c
] = TOLOWER (c
);
2574 register_chars
[c
] = mnemonic_chars
[c
];
2575 operand_chars
[c
] = c
;
2577 else if (c
== '{' || c
== '}')
2578 operand_chars
[c
] = c
;
2580 if (ISALPHA (c
) || ISDIGIT (c
))
2581 identifier_chars
[c
] = c
;
2584 identifier_chars
[c
] = c
;
2585 operand_chars
[c
] = c
;
2590 identifier_chars
['@'] = '@';
2593 identifier_chars
['?'] = '?';
2594 operand_chars
['?'] = '?';
2596 digit_chars
['-'] = '-';
2597 mnemonic_chars
['_'] = '_';
2598 mnemonic_chars
['-'] = '-';
2599 mnemonic_chars
['.'] = '.';
2600 identifier_chars
['_'] = '_';
2601 identifier_chars
['.'] = '.';
2603 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2604 operand_chars
[(unsigned char) *p
] = *p
;
2607 if (flag_code
== CODE_64BIT
)
2609 #if defined (OBJ_COFF) && defined (TE_PE)
2610 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2613 x86_dwarf2_return_column
= 16;
2615 x86_cie_data_alignment
= -8;
2619 x86_dwarf2_return_column
= 8;
2620 x86_cie_data_alignment
= -4;
2625 i386_print_statistics (FILE *file
)
2627 hash_print_statistics (file
, "i386 opcode", op_hash
);
2628 hash_print_statistics (file
, "i386 register", reg_hash
);
2633 /* Debugging routines for md_assemble. */
2634 static void pte (insn_template
*);
2635 static void pt (i386_operand_type
);
2636 static void pe (expressionS
*);
2637 static void ps (symbolS
*);
2640 pi (char *line
, i386_insn
*x
)
2644 fprintf (stdout
, "%s: template ", line
);
2646 fprintf (stdout
, " address: base %s index %s scale %x\n",
2647 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2648 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2649 x
->log2_scale_factor
);
2650 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2651 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2652 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2653 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2654 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2655 (x
->rex
& REX_W
) != 0,
2656 (x
->rex
& REX_R
) != 0,
2657 (x
->rex
& REX_X
) != 0,
2658 (x
->rex
& REX_B
) != 0);
2659 for (j
= 0; j
< x
->operands
; j
++)
2661 fprintf (stdout
, " #%d: ", j
+ 1);
2663 fprintf (stdout
, "\n");
2664 if (x
->types
[j
].bitfield
.reg8
2665 || x
->types
[j
].bitfield
.reg16
2666 || x
->types
[j
].bitfield
.reg32
2667 || x
->types
[j
].bitfield
.reg64
2668 || x
->types
[j
].bitfield
.regmmx
2669 || x
->types
[j
].bitfield
.regxmm
2670 || x
->types
[j
].bitfield
.regymm
2671 || x
->types
[j
].bitfield
.regzmm
2672 || x
->types
[j
].bitfield
.sreg2
2673 || x
->types
[j
].bitfield
.sreg3
2674 || x
->types
[j
].bitfield
.control
2675 || x
->types
[j
].bitfield
.debug
2676 || x
->types
[j
].bitfield
.test
)
2677 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2678 if (operand_type_check (x
->types
[j
], imm
))
2680 if (operand_type_check (x
->types
[j
], disp
))
2681 pe (x
->op
[j
].disps
);
2686 pte (insn_template
*t
)
2689 fprintf (stdout
, " %d operands ", t
->operands
);
2690 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2691 if (t
->extension_opcode
!= None
)
2692 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2693 if (t
->opcode_modifier
.d
)
2694 fprintf (stdout
, "D");
2695 if (t
->opcode_modifier
.w
)
2696 fprintf (stdout
, "W");
2697 fprintf (stdout
, "\n");
2698 for (j
= 0; j
< t
->operands
; j
++)
2700 fprintf (stdout
, " #%d type ", j
+ 1);
2701 pt (t
->operand_types
[j
]);
2702 fprintf (stdout
, "\n");
2709 fprintf (stdout
, " operation %d\n", e
->X_op
);
2710 fprintf (stdout
, " add_number %ld (%lx)\n",
2711 (long) e
->X_add_number
, (long) e
->X_add_number
);
2712 if (e
->X_add_symbol
)
2714 fprintf (stdout
, " add_symbol ");
2715 ps (e
->X_add_symbol
);
2716 fprintf (stdout
, "\n");
2720 fprintf (stdout
, " op_symbol ");
2721 ps (e
->X_op_symbol
);
2722 fprintf (stdout
, "\n");
2729 fprintf (stdout
, "%s type %s%s",
2731 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2732 segment_name (S_GET_SEGMENT (s
)));
2735 static struct type_name
2737 i386_operand_type mask
;
2740 const type_names
[] =
2742 { OPERAND_TYPE_REG8
, "r8" },
2743 { OPERAND_TYPE_REG16
, "r16" },
2744 { OPERAND_TYPE_REG32
, "r32" },
2745 { OPERAND_TYPE_REG64
, "r64" },
2746 { OPERAND_TYPE_IMM8
, "i8" },
2747 { OPERAND_TYPE_IMM8
, "i8s" },
2748 { OPERAND_TYPE_IMM16
, "i16" },
2749 { OPERAND_TYPE_IMM32
, "i32" },
2750 { OPERAND_TYPE_IMM32S
, "i32s" },
2751 { OPERAND_TYPE_IMM64
, "i64" },
2752 { OPERAND_TYPE_IMM1
, "i1" },
2753 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2754 { OPERAND_TYPE_DISP8
, "d8" },
2755 { OPERAND_TYPE_DISP16
, "d16" },
2756 { OPERAND_TYPE_DISP32
, "d32" },
2757 { OPERAND_TYPE_DISP32S
, "d32s" },
2758 { OPERAND_TYPE_DISP64
, "d64" },
2759 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2760 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2761 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2762 { OPERAND_TYPE_CONTROL
, "control reg" },
2763 { OPERAND_TYPE_TEST
, "test reg" },
2764 { OPERAND_TYPE_DEBUG
, "debug reg" },
2765 { OPERAND_TYPE_FLOATREG
, "FReg" },
2766 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2767 { OPERAND_TYPE_SREG2
, "SReg2" },
2768 { OPERAND_TYPE_SREG3
, "SReg3" },
2769 { OPERAND_TYPE_ACC
, "Acc" },
2770 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2771 { OPERAND_TYPE_REGMMX
, "rMMX" },
2772 { OPERAND_TYPE_REGXMM
, "rXMM" },
2773 { OPERAND_TYPE_REGYMM
, "rYMM" },
2774 { OPERAND_TYPE_REGZMM
, "rZMM" },
2775 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2776 { OPERAND_TYPE_ESSEG
, "es" },
2780 pt (i386_operand_type t
)
2783 i386_operand_type a
;
2785 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2787 a
= operand_type_and (t
, type_names
[j
].mask
);
2788 if (!operand_type_all_zero (&a
))
2789 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2794 #endif /* DEBUG386 */
2796 static bfd_reloc_code_real_type
2797 reloc (unsigned int size
,
2800 bfd_reloc_code_real_type other
)
2802 if (other
!= NO_RELOC
)
2804 reloc_howto_type
*rel
;
2809 case BFD_RELOC_X86_64_GOT32
:
2810 return BFD_RELOC_X86_64_GOT64
;
2812 case BFD_RELOC_X86_64_GOTPLT64
:
2813 return BFD_RELOC_X86_64_GOTPLT64
;
2815 case BFD_RELOC_X86_64_PLTOFF64
:
2816 return BFD_RELOC_X86_64_PLTOFF64
;
2818 case BFD_RELOC_X86_64_GOTPC32
:
2819 other
= BFD_RELOC_X86_64_GOTPC64
;
2821 case BFD_RELOC_X86_64_GOTPCREL
:
2822 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2824 case BFD_RELOC_X86_64_TPOFF32
:
2825 other
= BFD_RELOC_X86_64_TPOFF64
;
2827 case BFD_RELOC_X86_64_DTPOFF32
:
2828 other
= BFD_RELOC_X86_64_DTPOFF64
;
2834 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2835 if (other
== BFD_RELOC_SIZE32
)
2838 other
= BFD_RELOC_SIZE64
;
2841 as_bad (_("there are no pc-relative size relocations"));
2847 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2848 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2851 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2853 as_bad (_("unknown relocation (%u)"), other
);
2854 else if (size
!= bfd_get_reloc_size (rel
))
2855 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2856 bfd_get_reloc_size (rel
),
2858 else if (pcrel
&& !rel
->pc_relative
)
2859 as_bad (_("non-pc-relative relocation for pc-relative field"));
2860 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2862 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2864 as_bad (_("relocated field and relocation type differ in signedness"));
2873 as_bad (_("there are no unsigned pc-relative relocations"));
2876 case 1: return BFD_RELOC_8_PCREL
;
2877 case 2: return BFD_RELOC_16_PCREL
;
2878 case 4: return BFD_RELOC_32_PCREL
;
2879 case 8: return BFD_RELOC_64_PCREL
;
2881 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2888 case 4: return BFD_RELOC_X86_64_32S
;
2893 case 1: return BFD_RELOC_8
;
2894 case 2: return BFD_RELOC_16
;
2895 case 4: return BFD_RELOC_32
;
2896 case 8: return BFD_RELOC_64
;
2898 as_bad (_("cannot do %s %u byte relocation"),
2899 sign
> 0 ? "signed" : "unsigned", size
);
2905 /* Here we decide which fixups can be adjusted to make them relative to
2906 the beginning of the section instead of the symbol. Basically we need
2907 to make sure that the dynamic relocations are done correctly, so in
2908 some cases we force the original symbol to be used. */
2911 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2913 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2917 /* Don't adjust pc-relative references to merge sections in 64-bit
2919 if (use_rela_relocations
2920 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2924 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2925 and changed later by validate_fix. */
2926 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2927 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2930 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2931 for size relocations. */
2932 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2933 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2934 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2935 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2936 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2937 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
2938 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2939 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2940 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2941 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2942 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2943 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2944 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2945 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2946 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2947 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2948 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2949 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2950 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2951 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
2952 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
2953 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2954 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2955 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2956 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2957 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2958 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2959 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2960 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2961 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2962 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2963 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2964 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2971 intel_float_operand (const char *mnemonic
)
2973 /* Note that the value returned is meaningful only for opcodes with (memory)
2974 operands, hence the code here is free to improperly handle opcodes that
2975 have no operands (for better performance and smaller code). */
2977 if (mnemonic
[0] != 'f')
2978 return 0; /* non-math */
2980 switch (mnemonic
[1])
2982 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2983 the fs segment override prefix not currently handled because no
2984 call path can make opcodes without operands get here */
2986 return 2 /* integer op */;
2988 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2989 return 3; /* fldcw/fldenv */
2992 if (mnemonic
[2] != 'o' /* fnop */)
2993 return 3; /* non-waiting control op */
2996 if (mnemonic
[2] == 's')
2997 return 3; /* frstor/frstpm */
3000 if (mnemonic
[2] == 'a')
3001 return 3; /* fsave */
3002 if (mnemonic
[2] == 't')
3004 switch (mnemonic
[3])
3006 case 'c': /* fstcw */
3007 case 'd': /* fstdw */
3008 case 'e': /* fstenv */
3009 case 's': /* fsts[gw] */
3015 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3016 return 0; /* fxsave/fxrstor are not really math ops */
3023 /* Build the VEX prefix. */
3026 build_vex_prefix (const insn_template
*t
)
3028 unsigned int register_specifier
;
3029 unsigned int implied_prefix
;
3030 unsigned int vector_length
;
3032 /* Check register specifier. */
3033 if (i
.vex
.register_specifier
)
3035 register_specifier
=
3036 ~register_number (i
.vex
.register_specifier
) & 0xf;
3037 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3040 register_specifier
= 0xf;
3042 /* Use 2-byte VEX prefix by swappping destination and source
3045 && i
.operands
== i
.reg_operands
3046 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3047 && i
.tm
.opcode_modifier
.s
3050 unsigned int xchg
= i
.operands
- 1;
3051 union i386_op temp_op
;
3052 i386_operand_type temp_type
;
3054 temp_type
= i
.types
[xchg
];
3055 i
.types
[xchg
] = i
.types
[0];
3056 i
.types
[0] = temp_type
;
3057 temp_op
= i
.op
[xchg
];
3058 i
.op
[xchg
] = i
.op
[0];
3061 gas_assert (i
.rm
.mode
== 3);
3065 i
.rm
.regmem
= i
.rm
.reg
;
3068 /* Use the next insn. */
3072 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3073 vector_length
= avxscalar
;
3075 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3077 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3082 case DATA_PREFIX_OPCODE
:
3085 case REPE_PREFIX_OPCODE
:
3088 case REPNE_PREFIX_OPCODE
:
3095 /* Use 2-byte VEX prefix if possible. */
3096 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3097 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3098 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3100 /* 2-byte VEX prefix. */
3104 i
.vex
.bytes
[0] = 0xc5;
3106 /* Check the REX.R bit. */
3107 r
= (i
.rex
& REX_R
) ? 0 : 1;
3108 i
.vex
.bytes
[1] = (r
<< 7
3109 | register_specifier
<< 3
3110 | vector_length
<< 2
3115 /* 3-byte VEX prefix. */
3120 switch (i
.tm
.opcode_modifier
.vexopcode
)
3124 i
.vex
.bytes
[0] = 0xc4;
3128 i
.vex
.bytes
[0] = 0xc4;
3132 i
.vex
.bytes
[0] = 0xc4;
3136 i
.vex
.bytes
[0] = 0x8f;
3140 i
.vex
.bytes
[0] = 0x8f;
3144 i
.vex
.bytes
[0] = 0x8f;
3150 /* The high 3 bits of the second VEX byte are 1's compliment
3151 of RXB bits from REX. */
3152 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3154 /* Check the REX.W bit. */
3155 w
= (i
.rex
& REX_W
) ? 1 : 0;
3156 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3159 i
.vex
.bytes
[2] = (w
<< 7
3160 | register_specifier
<< 3
3161 | vector_length
<< 2
3166 /* Build the EVEX prefix. */
3169 build_evex_prefix (void)
3171 unsigned int register_specifier
;
3172 unsigned int implied_prefix
;
3174 rex_byte vrex_used
= 0;
3176 /* Check register specifier. */
3177 if (i
.vex
.register_specifier
)
3179 gas_assert ((i
.vrex
& REX_X
) == 0);
3181 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3182 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3183 register_specifier
+= 8;
3184 /* The upper 16 registers are encoded in the fourth byte of the
3186 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3187 i
.vex
.bytes
[3] = 0x8;
3188 register_specifier
= ~register_specifier
& 0xf;
3192 register_specifier
= 0xf;
3194 /* Encode upper 16 vector index register in the fourth byte of
3196 if (!(i
.vrex
& REX_X
))
3197 i
.vex
.bytes
[3] = 0x8;
3202 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3207 case DATA_PREFIX_OPCODE
:
3210 case REPE_PREFIX_OPCODE
:
3213 case REPNE_PREFIX_OPCODE
:
3220 /* 4 byte EVEX prefix. */
3222 i
.vex
.bytes
[0] = 0x62;
3225 switch (i
.tm
.opcode_modifier
.vexopcode
)
3241 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3243 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3245 /* The fifth bit of the second EVEX byte is 1's compliment of the
3246 REX_R bit in VREX. */
3247 if (!(i
.vrex
& REX_R
))
3248 i
.vex
.bytes
[1] |= 0x10;
3252 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3254 /* When all operands are registers, the REX_X bit in REX is not
3255 used. We reuse it to encode the upper 16 registers, which is
3256 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3257 as 1's compliment. */
3258 if ((i
.vrex
& REX_B
))
3261 i
.vex
.bytes
[1] &= ~0x40;
3265 /* EVEX instructions shouldn't need the REX prefix. */
3266 i
.vrex
&= ~vrex_used
;
3267 gas_assert (i
.vrex
== 0);
3269 /* Check the REX.W bit. */
3270 w
= (i
.rex
& REX_W
) ? 1 : 0;
3271 if (i
.tm
.opcode_modifier
.vexw
)
3273 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3276 /* If w is not set it means we are dealing with WIG instruction. */
3279 if (evexwig
== evexw1
)
3283 /* Encode the U bit. */
3284 implied_prefix
|= 0x4;
3286 /* The third byte of the EVEX prefix. */
3287 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3289 /* The fourth byte of the EVEX prefix. */
3290 /* The zeroing-masking bit. */
3291 if (i
.mask
&& i
.mask
->zeroing
)
3292 i
.vex
.bytes
[3] |= 0x80;
3294 /* Don't always set the broadcast bit if there is no RC. */
3297 /* Encode the vector length. */
3298 unsigned int vec_length
;
3300 switch (i
.tm
.opcode_modifier
.evex
)
3302 case EVEXLIG
: /* LL' is ignored */
3303 vec_length
= evexlig
<< 5;
3306 vec_length
= 0 << 5;
3309 vec_length
= 1 << 5;
3312 vec_length
= 2 << 5;
3318 i
.vex
.bytes
[3] |= vec_length
;
3319 /* Encode the broadcast bit. */
3321 i
.vex
.bytes
[3] |= 0x10;
3325 if (i
.rounding
->type
!= saeonly
)
3326 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3328 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3331 if (i
.mask
&& i
.mask
->mask
)
3332 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3336 process_immext (void)
3340 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3343 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3344 with an opcode suffix which is coded in the same place as an
3345 8-bit immediate field would be.
3346 Here we check those operands and remove them afterwards. */
3349 for (x
= 0; x
< i
.operands
; x
++)
3350 if (register_number (i
.op
[x
].regs
) != x
)
3351 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3352 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3358 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3360 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3361 suffix which is coded in the same place as an 8-bit immediate
3363 Here we check those operands and remove them afterwards. */
3366 if (i
.operands
!= 3)
3369 for (x
= 0; x
< 2; x
++)
3370 if (register_number (i
.op
[x
].regs
) != x
)
3371 goto bad_register_operand
;
3373 /* Check for third operand for mwaitx/monitorx insn. */
3374 if (register_number (i
.op
[x
].regs
)
3375 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3377 bad_register_operand
:
3378 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3379 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3386 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3387 which is coded in the same place as an 8-bit immediate field
3388 would be. Here we fake an 8-bit immediate operand from the
3389 opcode suffix stored in tm.extension_opcode.
3391 AVX instructions also use this encoding, for some of
3392 3 argument instructions. */
3394 gas_assert (i
.imm_operands
<= 1
3396 || ((i
.tm
.opcode_modifier
.vex
3397 || i
.tm
.opcode_modifier
.evex
)
3398 && i
.operands
<= 4)));
3400 exp
= &im_expressions
[i
.imm_operands
++];
3401 i
.op
[i
.operands
].imms
= exp
;
3402 i
.types
[i
.operands
] = imm8
;
3404 exp
->X_op
= O_constant
;
3405 exp
->X_add_number
= i
.tm
.extension_opcode
;
3406 i
.tm
.extension_opcode
= None
;
3413 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3418 as_bad (_("invalid instruction `%s' after `%s'"),
3419 i
.tm
.name
, i
.hle_prefix
);
3422 if (i
.prefix
[LOCK_PREFIX
])
3424 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3428 case HLEPrefixRelease
:
3429 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3431 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3435 if (i
.mem_operands
== 0
3436 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3438 as_bad (_("memory destination needed for instruction `%s'"
3439 " after `xrelease'"), i
.tm
.name
);
3446 /* This is the guts of the machine-dependent assembler. LINE points to a
3447 machine dependent instruction. This function is supposed to emit
3448 the frags/bytes it assembles to. */
3451 md_assemble (char *line
)
3454 char mnemonic
[MAX_MNEM_SIZE
];
3455 const insn_template
*t
;
3457 /* Initialize globals. */
3458 memset (&i
, '\0', sizeof (i
));
3459 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3460 i
.reloc
[j
] = NO_RELOC
;
3461 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3462 memset (im_expressions
, '\0', sizeof (im_expressions
));
3463 save_stack_p
= save_stack
;
3465 /* First parse an instruction mnemonic & call i386_operand for the operands.
3466 We assume that the scrubber has arranged it so that line[0] is the valid
3467 start of a (possibly prefixed) mnemonic. */
3469 line
= parse_insn (line
, mnemonic
);
3473 line
= parse_operands (line
, mnemonic
);
3478 /* Now we've parsed the mnemonic into a set of templates, and have the
3479 operands at hand. */
3481 /* All intel opcodes have reversed operands except for "bound" and
3482 "enter". We also don't reverse intersegment "jmp" and "call"
3483 instructions with 2 immediate operands so that the immediate segment
3484 precedes the offset, as it does when in AT&T mode. */
3487 && (strcmp (mnemonic
, "bound") != 0)
3488 && (strcmp (mnemonic
, "invlpga") != 0)
3489 && !(operand_type_check (i
.types
[0], imm
)
3490 && operand_type_check (i
.types
[1], imm
)))
3493 /* The order of the immediates should be reversed
3494 for 2 immediates extrq and insertq instructions */
3495 if (i
.imm_operands
== 2
3496 && (strcmp (mnemonic
, "extrq") == 0
3497 || strcmp (mnemonic
, "insertq") == 0))
3498 swap_2_operands (0, 1);
3503 /* Don't optimize displacement for movabs since it only takes 64bit
3506 && i
.disp_encoding
!= disp_encoding_32bit
3507 && (flag_code
!= CODE_64BIT
3508 || strcmp (mnemonic
, "movabs") != 0))
3511 /* Next, we find a template that matches the given insn,
3512 making sure the overlap of the given operands types is consistent
3513 with the template operand types. */
3515 if (!(t
= match_template ()))
3518 if (sse_check
!= check_none
3519 && !i
.tm
.opcode_modifier
.noavx
3520 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3521 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3522 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3523 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3524 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3525 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3527 (sse_check
== check_warning
3529 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3532 /* Zap movzx and movsx suffix. The suffix has been set from
3533 "word ptr" or "byte ptr" on the source operand in Intel syntax
3534 or extracted from mnemonic in AT&T syntax. But we'll use
3535 the destination register to choose the suffix for encoding. */
3536 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3538 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3539 there is no suffix, the default will be byte extension. */
3540 if (i
.reg_operands
!= 2
3543 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3548 if (i
.tm
.opcode_modifier
.fwait
)
3549 if (!add_prefix (FWAIT_OPCODE
))
3552 /* Check if REP prefix is OK. */
3553 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3555 as_bad (_("invalid instruction `%s' after `%s'"),
3556 i
.tm
.name
, i
.rep_prefix
);
3560 /* Check for lock without a lockable instruction. Destination operand
3561 must be memory unless it is xchg (0x86). */
3562 if (i
.prefix
[LOCK_PREFIX
]
3563 && (!i
.tm
.opcode_modifier
.islockable
3564 || i
.mem_operands
== 0
3565 || (i
.tm
.base_opcode
!= 0x86
3566 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3568 as_bad (_("expecting lockable instruction after `lock'"));
3572 /* Check if HLE prefix is OK. */
3573 if (i
.hle_prefix
&& !check_hle ())
3576 /* Check BND prefix. */
3577 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3578 as_bad (_("expecting valid branch instruction after `bnd'"));
3580 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3581 && flag_code
== CODE_64BIT
3582 && i
.prefix
[ADDR_PREFIX
])
3583 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3585 /* Insert BND prefix. */
3587 && i
.tm
.opcode_modifier
.bndprefixok
3588 && !i
.prefix
[BND_PREFIX
])
3589 add_prefix (BND_PREFIX_OPCODE
);
3591 /* Check string instruction segment overrides. */
3592 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3594 if (!check_string ())
3596 i
.disp_operands
= 0;
3599 if (!process_suffix ())
3602 /* Update operand types. */
3603 for (j
= 0; j
< i
.operands
; j
++)
3604 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3606 /* Make still unresolved immediate matches conform to size of immediate
3607 given in i.suffix. */
3608 if (!finalize_imm ())
3611 if (i
.types
[0].bitfield
.imm1
)
3612 i
.imm_operands
= 0; /* kludge for shift insns. */
3614 /* We only need to check those implicit registers for instructions
3615 with 3 operands or less. */
3616 if (i
.operands
<= 3)
3617 for (j
= 0; j
< i
.operands
; j
++)
3618 if (i
.types
[j
].bitfield
.inoutportreg
3619 || i
.types
[j
].bitfield
.shiftcount
3620 || i
.types
[j
].bitfield
.acc
3621 || i
.types
[j
].bitfield
.floatacc
)
3624 /* ImmExt should be processed after SSE2AVX. */
3625 if (!i
.tm
.opcode_modifier
.sse2avx
3626 && i
.tm
.opcode_modifier
.immext
)
3629 /* For insns with operands there are more diddles to do to the opcode. */
3632 if (!process_operands ())
3635 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3637 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3638 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3641 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3643 if (flag_code
== CODE_16BIT
)
3645 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3650 if (i
.tm
.opcode_modifier
.vex
)
3651 build_vex_prefix (t
);
3653 build_evex_prefix ();
3656 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3657 instructions may define INT_OPCODE as well, so avoid this corner
3658 case for those instructions that use MODRM. */
3659 if (i
.tm
.base_opcode
== INT_OPCODE
3660 && !i
.tm
.opcode_modifier
.modrm
3661 && i
.op
[0].imms
->X_add_number
== 3)
3663 i
.tm
.base_opcode
= INT3_OPCODE
;
3667 if ((i
.tm
.opcode_modifier
.jump
3668 || i
.tm
.opcode_modifier
.jumpbyte
3669 || i
.tm
.opcode_modifier
.jumpdword
)
3670 && i
.op
[0].disps
->X_op
== O_constant
)
3672 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3673 the absolute address given by the constant. Since ix86 jumps and
3674 calls are pc relative, we need to generate a reloc. */
3675 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3676 i
.op
[0].disps
->X_op
= O_symbol
;
3679 if (i
.tm
.opcode_modifier
.rex64
)
3682 /* For 8 bit registers we need an empty rex prefix. Also if the
3683 instruction already has a prefix, we need to convert old
3684 registers to new ones. */
3686 if ((i
.types
[0].bitfield
.reg8
3687 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3688 || (i
.types
[1].bitfield
.reg8
3689 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3690 || ((i
.types
[0].bitfield
.reg8
3691 || i
.types
[1].bitfield
.reg8
)
3696 i
.rex
|= REX_OPCODE
;
3697 for (x
= 0; x
< 2; x
++)
3699 /* Look for 8 bit operand that uses old registers. */
3700 if (i
.types
[x
].bitfield
.reg8
3701 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3703 /* In case it is "hi" register, give up. */
3704 if (i
.op
[x
].regs
->reg_num
> 3)
3705 as_bad (_("can't encode register '%s%s' in an "
3706 "instruction requiring REX prefix."),
3707 register_prefix
, i
.op
[x
].regs
->reg_name
);
3709 /* Otherwise it is equivalent to the extended register.
3710 Since the encoding doesn't change this is merely
3711 cosmetic cleanup for debug output. */
3713 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3719 add_prefix (REX_OPCODE
| i
.rex
);
3721 /* We are ready to output the insn. */
3726 parse_insn (char *line
, char *mnemonic
)
3729 char *token_start
= l
;
3732 const insn_template
*t
;
3738 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3743 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3745 as_bad (_("no such instruction: `%s'"), token_start
);
3750 if (!is_space_char (*l
)
3751 && *l
!= END_OF_INSN
3753 || (*l
!= PREFIX_SEPARATOR
3756 as_bad (_("invalid character %s in mnemonic"),
3757 output_invalid (*l
));
3760 if (token_start
== l
)
3762 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3763 as_bad (_("expecting prefix; got nothing"));
3765 as_bad (_("expecting mnemonic; got nothing"));
3769 /* Look up instruction (or prefix) via hash table. */
3770 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3772 if (*l
!= END_OF_INSN
3773 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3774 && current_templates
3775 && current_templates
->start
->opcode_modifier
.isprefix
)
3777 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3779 as_bad ((flag_code
!= CODE_64BIT
3780 ? _("`%s' is only supported in 64-bit mode")
3781 : _("`%s' is not supported in 64-bit mode")),
3782 current_templates
->start
->name
);
3785 /* If we are in 16-bit mode, do not allow addr16 or data16.
3786 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3787 if ((current_templates
->start
->opcode_modifier
.size16
3788 || current_templates
->start
->opcode_modifier
.size32
)
3789 && flag_code
!= CODE_64BIT
3790 && (current_templates
->start
->opcode_modifier
.size32
3791 ^ (flag_code
== CODE_16BIT
)))
3793 as_bad (_("redundant %s prefix"),
3794 current_templates
->start
->name
);
3797 /* Add prefix, checking for repeated prefixes. */
3798 switch (add_prefix (current_templates
->start
->base_opcode
))
3803 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3804 i
.hle_prefix
= current_templates
->start
->name
;
3805 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3806 i
.bnd_prefix
= current_templates
->start
->name
;
3808 i
.rep_prefix
= current_templates
->start
->name
;
3813 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3820 if (!current_templates
)
3822 /* Check if we should swap operand or force 32bit displacement in
3824 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3826 else if (mnem_p
- 3 == dot_p
3829 i
.disp_encoding
= disp_encoding_8bit
;
3830 else if (mnem_p
- 4 == dot_p
3834 i
.disp_encoding
= disp_encoding_32bit
;
3839 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3842 if (!current_templates
)
3845 /* See if we can get a match by trimming off a suffix. */
3848 case WORD_MNEM_SUFFIX
:
3849 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3850 i
.suffix
= SHORT_MNEM_SUFFIX
;
3852 case BYTE_MNEM_SUFFIX
:
3853 case QWORD_MNEM_SUFFIX
:
3854 i
.suffix
= mnem_p
[-1];
3856 current_templates
= (const templates
*) hash_find (op_hash
,
3859 case SHORT_MNEM_SUFFIX
:
3860 case LONG_MNEM_SUFFIX
:
3863 i
.suffix
= mnem_p
[-1];
3865 current_templates
= (const templates
*) hash_find (op_hash
,
3874 if (intel_float_operand (mnemonic
) == 1)
3875 i
.suffix
= SHORT_MNEM_SUFFIX
;
3877 i
.suffix
= LONG_MNEM_SUFFIX
;
3879 current_templates
= (const templates
*) hash_find (op_hash
,
3884 if (!current_templates
)
3886 as_bad (_("no such instruction: `%s'"), token_start
);
3891 if (current_templates
->start
->opcode_modifier
.jump
3892 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3894 /* Check for a branch hint. We allow ",pt" and ",pn" for
3895 predict taken and predict not taken respectively.
3896 I'm not sure that branch hints actually do anything on loop
3897 and jcxz insns (JumpByte) for current Pentium4 chips. They
3898 may work in the future and it doesn't hurt to accept them
3900 if (l
[0] == ',' && l
[1] == 'p')
3904 if (!add_prefix (DS_PREFIX_OPCODE
))
3908 else if (l
[2] == 'n')
3910 if (!add_prefix (CS_PREFIX_OPCODE
))
3916 /* Any other comma loses. */
3919 as_bad (_("invalid character %s in mnemonic"),
3920 output_invalid (*l
));
3924 /* Check if instruction is supported on specified architecture. */
3926 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3928 supported
|= cpu_flags_match (t
);
3929 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3933 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3935 as_bad (flag_code
== CODE_64BIT
3936 ? _("`%s' is not supported in 64-bit mode")
3937 : _("`%s' is only supported in 64-bit mode"),
3938 current_templates
->start
->name
);
3941 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3943 as_bad (_("`%s' is not supported on `%s%s'"),
3944 current_templates
->start
->name
,
3945 cpu_arch_name
? cpu_arch_name
: default_arch
,
3946 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3951 if (!cpu_arch_flags
.bitfield
.cpui386
3952 && (flag_code
!= CODE_16BIT
))
3954 as_warn (_("use .code16 to ensure correct addressing mode"));
3961 parse_operands (char *l
, const char *mnemonic
)
3965 /* 1 if operand is pending after ','. */
3966 unsigned int expecting_operand
= 0;
3968 /* Non-zero if operand parens not balanced. */
3969 unsigned int paren_not_balanced
;
3971 while (*l
!= END_OF_INSN
)
3973 /* Skip optional white space before operand. */
3974 if (is_space_char (*l
))
3976 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
3978 as_bad (_("invalid character %s before operand %d"),
3979 output_invalid (*l
),
3983 token_start
= l
; /* After white space. */
3984 paren_not_balanced
= 0;
3985 while (paren_not_balanced
|| *l
!= ',')
3987 if (*l
== END_OF_INSN
)
3989 if (paren_not_balanced
)
3992 as_bad (_("unbalanced parenthesis in operand %d."),
3995 as_bad (_("unbalanced brackets in operand %d."),
4000 break; /* we are done */
4002 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4004 as_bad (_("invalid character %s in operand %d"),
4005 output_invalid (*l
),
4012 ++paren_not_balanced
;
4014 --paren_not_balanced
;
4019 ++paren_not_balanced
;
4021 --paren_not_balanced
;
4025 if (l
!= token_start
)
4026 { /* Yes, we've read in another operand. */
4027 unsigned int operand_ok
;
4028 this_operand
= i
.operands
++;
4029 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4030 if (i
.operands
> MAX_OPERANDS
)
4032 as_bad (_("spurious operands; (%d operands/instruction max)"),
4036 /* Now parse operand adding info to 'i' as we go along. */
4037 END_STRING_AND_SAVE (l
);
4041 i386_intel_operand (token_start
,
4042 intel_float_operand (mnemonic
));
4044 operand_ok
= i386_att_operand (token_start
);
4046 RESTORE_END_STRING (l
);
4052 if (expecting_operand
)
4054 expecting_operand_after_comma
:
4055 as_bad (_("expecting operand after ','; got nothing"));
4060 as_bad (_("expecting operand before ','; got nothing"));
4065 /* Now *l must be either ',' or END_OF_INSN. */
4068 if (*++l
== END_OF_INSN
)
4070 /* Just skip it, if it's \n complain. */
4071 goto expecting_operand_after_comma
;
4073 expecting_operand
= 1;
4080 swap_2_operands (int xchg1
, int xchg2
)
4082 union i386_op temp_op
;
4083 i386_operand_type temp_type
;
4084 enum bfd_reloc_code_real temp_reloc
;
4086 temp_type
= i
.types
[xchg2
];
4087 i
.types
[xchg2
] = i
.types
[xchg1
];
4088 i
.types
[xchg1
] = temp_type
;
4089 temp_op
= i
.op
[xchg2
];
4090 i
.op
[xchg2
] = i
.op
[xchg1
];
4091 i
.op
[xchg1
] = temp_op
;
4092 temp_reloc
= i
.reloc
[xchg2
];
4093 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4094 i
.reloc
[xchg1
] = temp_reloc
;
4098 if (i
.mask
->operand
== xchg1
)
4099 i
.mask
->operand
= xchg2
;
4100 else if (i
.mask
->operand
== xchg2
)
4101 i
.mask
->operand
= xchg1
;
4105 if (i
.broadcast
->operand
== xchg1
)
4106 i
.broadcast
->operand
= xchg2
;
4107 else if (i
.broadcast
->operand
== xchg2
)
4108 i
.broadcast
->operand
= xchg1
;
4112 if (i
.rounding
->operand
== xchg1
)
4113 i
.rounding
->operand
= xchg2
;
4114 else if (i
.rounding
->operand
== xchg2
)
4115 i
.rounding
->operand
= xchg1
;
4120 swap_operands (void)
4126 swap_2_operands (1, i
.operands
- 2);
4129 swap_2_operands (0, i
.operands
- 1);
4135 if (i
.mem_operands
== 2)
4137 const seg_entry
*temp_seg
;
4138 temp_seg
= i
.seg
[0];
4139 i
.seg
[0] = i
.seg
[1];
4140 i
.seg
[1] = temp_seg
;
4144 /* Try to ensure constant immediates are represented in the smallest
4149 char guess_suffix
= 0;
4153 guess_suffix
= i
.suffix
;
4154 else if (i
.reg_operands
)
4156 /* Figure out a suffix from the last register operand specified.
4157 We can't do this properly yet, ie. excluding InOutPortReg,
4158 but the following works for instructions with immediates.
4159 In any case, we can't set i.suffix yet. */
4160 for (op
= i
.operands
; --op
>= 0;)
4161 if (i
.types
[op
].bitfield
.reg8
)
4163 guess_suffix
= BYTE_MNEM_SUFFIX
;
4166 else if (i
.types
[op
].bitfield
.reg16
)
4168 guess_suffix
= WORD_MNEM_SUFFIX
;
4171 else if (i
.types
[op
].bitfield
.reg32
)
4173 guess_suffix
= LONG_MNEM_SUFFIX
;
4176 else if (i
.types
[op
].bitfield
.reg64
)
4178 guess_suffix
= QWORD_MNEM_SUFFIX
;
4182 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4183 guess_suffix
= WORD_MNEM_SUFFIX
;
4185 for (op
= i
.operands
; --op
>= 0;)
4186 if (operand_type_check (i
.types
[op
], imm
))
4188 switch (i
.op
[op
].imms
->X_op
)
4191 /* If a suffix is given, this operand may be shortened. */
4192 switch (guess_suffix
)
4194 case LONG_MNEM_SUFFIX
:
4195 i
.types
[op
].bitfield
.imm32
= 1;
4196 i
.types
[op
].bitfield
.imm64
= 1;
4198 case WORD_MNEM_SUFFIX
:
4199 i
.types
[op
].bitfield
.imm16
= 1;
4200 i
.types
[op
].bitfield
.imm32
= 1;
4201 i
.types
[op
].bitfield
.imm32s
= 1;
4202 i
.types
[op
].bitfield
.imm64
= 1;
4204 case BYTE_MNEM_SUFFIX
:
4205 i
.types
[op
].bitfield
.imm8
= 1;
4206 i
.types
[op
].bitfield
.imm8s
= 1;
4207 i
.types
[op
].bitfield
.imm16
= 1;
4208 i
.types
[op
].bitfield
.imm32
= 1;
4209 i
.types
[op
].bitfield
.imm32s
= 1;
4210 i
.types
[op
].bitfield
.imm64
= 1;
4214 /* If this operand is at most 16 bits, convert it
4215 to a signed 16 bit number before trying to see
4216 whether it will fit in an even smaller size.
4217 This allows a 16-bit operand such as $0xffe0 to
4218 be recognised as within Imm8S range. */
4219 if ((i
.types
[op
].bitfield
.imm16
)
4220 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4222 i
.op
[op
].imms
->X_add_number
=
4223 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4226 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4227 if ((i
.types
[op
].bitfield
.imm32
)
4228 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4231 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4232 ^ ((offsetT
) 1 << 31))
4233 - ((offsetT
) 1 << 31));
4237 = operand_type_or (i
.types
[op
],
4238 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4240 /* We must avoid matching of Imm32 templates when 64bit
4241 only immediate is available. */
4242 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4243 i
.types
[op
].bitfield
.imm32
= 0;
4250 /* Symbols and expressions. */
4252 /* Convert symbolic operand to proper sizes for matching, but don't
4253 prevent matching a set of insns that only supports sizes other
4254 than those matching the insn suffix. */
4256 i386_operand_type mask
, allowed
;
4257 const insn_template
*t
;
4259 operand_type_set (&mask
, 0);
4260 operand_type_set (&allowed
, 0);
4262 for (t
= current_templates
->start
;
4263 t
< current_templates
->end
;
4265 allowed
= operand_type_or (allowed
,
4266 t
->operand_types
[op
]);
4267 switch (guess_suffix
)
4269 case QWORD_MNEM_SUFFIX
:
4270 mask
.bitfield
.imm64
= 1;
4271 mask
.bitfield
.imm32s
= 1;
4273 case LONG_MNEM_SUFFIX
:
4274 mask
.bitfield
.imm32
= 1;
4276 case WORD_MNEM_SUFFIX
:
4277 mask
.bitfield
.imm16
= 1;
4279 case BYTE_MNEM_SUFFIX
:
4280 mask
.bitfield
.imm8
= 1;
4285 allowed
= operand_type_and (mask
, allowed
);
4286 if (!operand_type_all_zero (&allowed
))
4287 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4294 /* Try to use the smallest displacement type too. */
4296 optimize_disp (void)
4300 for (op
= i
.operands
; --op
>= 0;)
4301 if (operand_type_check (i
.types
[op
], disp
))
4303 if (i
.op
[op
].disps
->X_op
== O_constant
)
4305 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4307 if (i
.types
[op
].bitfield
.disp16
4308 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4310 /* If this operand is at most 16 bits, convert
4311 to a signed 16 bit number and don't use 64bit
4313 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4314 i
.types
[op
].bitfield
.disp64
= 0;
4317 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4318 if (i
.types
[op
].bitfield
.disp32
4319 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4321 /* If this operand is at most 32 bits, convert
4322 to a signed 32 bit number and don't use 64bit
4324 op_disp
&= (((offsetT
) 2 << 31) - 1);
4325 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4326 i
.types
[op
].bitfield
.disp64
= 0;
4329 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4331 i
.types
[op
].bitfield
.disp8
= 0;
4332 i
.types
[op
].bitfield
.disp16
= 0;
4333 i
.types
[op
].bitfield
.disp32
= 0;
4334 i
.types
[op
].bitfield
.disp32s
= 0;
4335 i
.types
[op
].bitfield
.disp64
= 0;
4339 else if (flag_code
== CODE_64BIT
)
4341 if (fits_in_signed_long (op_disp
))
4343 i
.types
[op
].bitfield
.disp64
= 0;
4344 i
.types
[op
].bitfield
.disp32s
= 1;
4346 if (i
.prefix
[ADDR_PREFIX
]
4347 && fits_in_unsigned_long (op_disp
))
4348 i
.types
[op
].bitfield
.disp32
= 1;
4350 if ((i
.types
[op
].bitfield
.disp32
4351 || i
.types
[op
].bitfield
.disp32s
4352 || i
.types
[op
].bitfield
.disp16
)
4353 && fits_in_signed_byte (op_disp
))
4354 i
.types
[op
].bitfield
.disp8
= 1;
4356 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4357 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4359 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4360 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4361 i
.types
[op
].bitfield
.disp8
= 0;
4362 i
.types
[op
].bitfield
.disp16
= 0;
4363 i
.types
[op
].bitfield
.disp32
= 0;
4364 i
.types
[op
].bitfield
.disp32s
= 0;
4365 i
.types
[op
].bitfield
.disp64
= 0;
4368 /* We only support 64bit displacement on constants. */
4369 i
.types
[op
].bitfield
.disp64
= 0;
4373 /* Check if operands are valid for the instruction. */
4376 check_VecOperands (const insn_template
*t
)
4380 /* Without VSIB byte, we can't have a vector register for index. */
4381 if (!t
->opcode_modifier
.vecsib
4383 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4384 || i
.index_reg
->reg_type
.bitfield
.regymm
4385 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4387 i
.error
= unsupported_vector_index_register
;
4391 /* Check if default mask is allowed. */
4392 if (t
->opcode_modifier
.nodefmask
4393 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4395 i
.error
= no_default_mask
;
4399 /* For VSIB byte, we need a vector register for index, and all vector
4400 registers must be distinct. */
4401 if (t
->opcode_modifier
.vecsib
)
4404 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4405 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4406 || (t
->opcode_modifier
.vecsib
== VecSIB256
4407 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4408 || (t
->opcode_modifier
.vecsib
== VecSIB512
4409 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4411 i
.error
= invalid_vsib_address
;
4415 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4416 if (i
.reg_operands
== 2 && !i
.mask
)
4418 gas_assert (i
.types
[0].bitfield
.regxmm
4419 || i
.types
[0].bitfield
.regymm
);
4420 gas_assert (i
.types
[2].bitfield
.regxmm
4421 || i
.types
[2].bitfield
.regymm
);
4422 if (operand_check
== check_none
)
4424 if (register_number (i
.op
[0].regs
)
4425 != register_number (i
.index_reg
)
4426 && register_number (i
.op
[2].regs
)
4427 != register_number (i
.index_reg
)
4428 && register_number (i
.op
[0].regs
)
4429 != register_number (i
.op
[2].regs
))
4431 if (operand_check
== check_error
)
4433 i
.error
= invalid_vector_register_set
;
4436 as_warn (_("mask, index, and destination registers should be distinct"));
4438 else if (i
.reg_operands
== 1 && i
.mask
)
4440 if ((i
.types
[1].bitfield
.regymm
4441 || i
.types
[1].bitfield
.regzmm
)
4442 && (register_number (i
.op
[1].regs
)
4443 == register_number (i
.index_reg
)))
4445 if (operand_check
== check_error
)
4447 i
.error
= invalid_vector_register_set
;
4450 if (operand_check
!= check_none
)
4451 as_warn (_("index and destination registers should be distinct"));
4456 /* Check if broadcast is supported by the instruction and is applied
4457 to the memory operand. */
4460 int broadcasted_opnd_size
;
4462 /* Check if specified broadcast is supported in this instruction,
4463 and it's applied to memory operand of DWORD or QWORD type,
4464 depending on VecESize. */
4465 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4466 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4467 || (t
->opcode_modifier
.vecesize
== 0
4468 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4469 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4470 || (t
->opcode_modifier
.vecesize
== 1
4471 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4472 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4475 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4476 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4477 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4478 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4479 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4480 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4481 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4482 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4483 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4487 if ((broadcasted_opnd_size
== 256
4488 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4489 || (broadcasted_opnd_size
== 512
4490 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4493 i
.error
= unsupported_broadcast
;
4497 /* If broadcast is supported in this instruction, we need to check if
4498 operand of one-element size isn't specified without broadcast. */
4499 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4501 /* Find memory operand. */
4502 for (op
= 0; op
< i
.operands
; op
++)
4503 if (operand_type_check (i
.types
[op
], anymem
))
4505 gas_assert (op
< i
.operands
);
4506 /* Check size of the memory operand. */
4507 if ((t
->opcode_modifier
.vecesize
== 0
4508 && i
.types
[op
].bitfield
.dword
)
4509 || (t
->opcode_modifier
.vecesize
== 1
4510 && i
.types
[op
].bitfield
.qword
))
4512 i
.error
= broadcast_needed
;
4517 /* Check if requested masking is supported. */
4519 && (!t
->opcode_modifier
.masking
4521 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4523 i
.error
= unsupported_masking
;
4527 /* Check if masking is applied to dest operand. */
4528 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4530 i
.error
= mask_not_on_destination
;
4537 if ((i
.rounding
->type
!= saeonly
4538 && !t
->opcode_modifier
.staticrounding
)
4539 || (i
.rounding
->type
== saeonly
4540 && (t
->opcode_modifier
.staticrounding
4541 || !t
->opcode_modifier
.sae
)))
4543 i
.error
= unsupported_rc_sae
;
4546 /* If the instruction has several immediate operands and one of
4547 them is rounding, the rounding operand should be the last
4548 immediate operand. */
4549 if (i
.imm_operands
> 1
4550 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4552 i
.error
= rc_sae_operand_not_last_imm
;
4557 /* Check vector Disp8 operand. */
4558 if (t
->opcode_modifier
.disp8memshift
)
4561 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4563 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4565 for (op
= 0; op
< i
.operands
; op
++)
4566 if (operand_type_check (i
.types
[op
], disp
)
4567 && i
.op
[op
].disps
->X_op
== O_constant
)
4569 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4570 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4571 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4574 i
.types
[op
].bitfield
.vec_disp8
= 1;
4577 /* Vector insn can only have Vec_Disp8/Disp32 in
4578 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4580 i
.types
[op
].bitfield
.disp8
= 0;
4581 if (flag_code
!= CODE_16BIT
)
4582 i
.types
[op
].bitfield
.disp16
= 0;
4585 else if (flag_code
!= CODE_16BIT
)
4587 /* One form of this instruction supports vector Disp8.
4588 Try vector Disp8 if we need to use Disp32. */
4589 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4591 i
.error
= try_vector_disp8
;
4603 /* Check if operands are valid for the instruction. Update VEX
4607 VEX_check_operands (const insn_template
*t
)
4609 /* VREX is only valid with EVEX prefix. */
4610 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4612 i
.error
= invalid_register_operand
;
4616 if (!t
->opcode_modifier
.vex
)
4619 /* Only check VEX_Imm4, which must be the first operand. */
4620 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4622 if (i
.op
[0].imms
->X_op
!= O_constant
4623 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4629 /* Turn off Imm8 so that update_imm won't complain. */
4630 i
.types
[0] = vec_imm4
;
4636 static const insn_template
*
4637 match_template (void)
4639 /* Points to template once we've found it. */
4640 const insn_template
*t
;
4641 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4642 i386_operand_type overlap4
;
4643 unsigned int found_reverse_match
;
4644 i386_opcode_modifier suffix_check
;
4645 i386_operand_type operand_types
[MAX_OPERANDS
];
4646 int addr_prefix_disp
;
4648 unsigned int found_cpu_match
;
4649 unsigned int check_register
;
4650 enum i386_error specific_error
= 0;
4652 #if MAX_OPERANDS != 5
4653 # error "MAX_OPERANDS must be 5."
4656 found_reverse_match
= 0;
4657 addr_prefix_disp
= -1;
4659 memset (&suffix_check
, 0, sizeof (suffix_check
));
4660 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4661 suffix_check
.no_bsuf
= 1;
4662 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4663 suffix_check
.no_wsuf
= 1;
4664 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4665 suffix_check
.no_ssuf
= 1;
4666 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4667 suffix_check
.no_lsuf
= 1;
4668 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4669 suffix_check
.no_qsuf
= 1;
4670 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4671 suffix_check
.no_ldsuf
= 1;
4673 /* Must have right number of operands. */
4674 i
.error
= number_of_operands_mismatch
;
4676 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4678 addr_prefix_disp
= -1;
4680 if (i
.operands
!= t
->operands
)
4683 /* Check processor support. */
4684 i
.error
= unsupported
;
4685 found_cpu_match
= (cpu_flags_match (t
)
4686 == CPU_FLAGS_PERFECT_MATCH
);
4687 if (!found_cpu_match
)
4690 /* Check old gcc support. */
4691 i
.error
= old_gcc_only
;
4692 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4695 /* Check AT&T mnemonic. */
4696 i
.error
= unsupported_with_intel_mnemonic
;
4697 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4700 /* Check AT&T/Intel syntax. */
4701 i
.error
= unsupported_syntax
;
4702 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4703 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4706 /* Check the suffix, except for some instructions in intel mode. */
4707 i
.error
= invalid_instruction_suffix
;
4708 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4709 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4710 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4711 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4712 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4713 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4714 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4717 if (!operand_size_match (t
))
4720 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4721 operand_types
[j
] = t
->operand_types
[j
];
4723 /* In general, don't allow 64-bit operands in 32-bit mode. */
4724 if (i
.suffix
== QWORD_MNEM_SUFFIX
4725 && flag_code
!= CODE_64BIT
4727 ? (!t
->opcode_modifier
.ignoresize
4728 && !intel_float_operand (t
->name
))
4729 : intel_float_operand (t
->name
) != 2)
4730 && ((!operand_types
[0].bitfield
.regmmx
4731 && !operand_types
[0].bitfield
.regxmm
4732 && !operand_types
[0].bitfield
.regymm
4733 && !operand_types
[0].bitfield
.regzmm
)
4734 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4735 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4736 && operand_types
[t
->operands
> 1].bitfield
.regymm
4737 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4738 && (t
->base_opcode
!= 0x0fc7
4739 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4742 /* In general, don't allow 32-bit operands on pre-386. */
4743 else if (i
.suffix
== LONG_MNEM_SUFFIX
4744 && !cpu_arch_flags
.bitfield
.cpui386
4746 ? (!t
->opcode_modifier
.ignoresize
4747 && !intel_float_operand (t
->name
))
4748 : intel_float_operand (t
->name
) != 2)
4749 && ((!operand_types
[0].bitfield
.regmmx
4750 && !operand_types
[0].bitfield
.regxmm
)
4751 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4752 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4755 /* Do not verify operands when there are none. */
4759 /* We've found a match; break out of loop. */
4763 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4764 into Disp32/Disp16/Disp32 operand. */
4765 if (i
.prefix
[ADDR_PREFIX
] != 0)
4767 /* There should be only one Disp operand. */
4771 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4773 if (operand_types
[j
].bitfield
.disp16
)
4775 addr_prefix_disp
= j
;
4776 operand_types
[j
].bitfield
.disp32
= 1;
4777 operand_types
[j
].bitfield
.disp16
= 0;
4783 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4785 if (operand_types
[j
].bitfield
.disp32
)
4787 addr_prefix_disp
= j
;
4788 operand_types
[j
].bitfield
.disp32
= 0;
4789 operand_types
[j
].bitfield
.disp16
= 1;
4795 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4797 if (operand_types
[j
].bitfield
.disp64
)
4799 addr_prefix_disp
= j
;
4800 operand_types
[j
].bitfield
.disp64
= 0;
4801 operand_types
[j
].bitfield
.disp32
= 1;
4809 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4810 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
4813 /* We check register size if needed. */
4814 check_register
= t
->opcode_modifier
.checkregsize
;
4815 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4816 switch (t
->operands
)
4819 if (!operand_type_match (overlap0
, i
.types
[0]))
4823 /* xchg %eax, %eax is a special case. It is an aliase for nop
4824 only in 32bit mode and we can use opcode 0x90. In 64bit
4825 mode, we can't use 0x90 for xchg %eax, %eax since it should
4826 zero-extend %eax to %rax. */
4827 if (flag_code
== CODE_64BIT
4828 && t
->base_opcode
== 0x90
4829 && operand_type_equal (&i
.types
[0], &acc32
)
4830 && operand_type_equal (&i
.types
[1], &acc32
))
4834 /* If we swap operand in encoding, we either match
4835 the next one or reverse direction of operands. */
4836 if (t
->opcode_modifier
.s
)
4838 else if (t
->opcode_modifier
.d
)
4843 /* If we swap operand in encoding, we match the next one. */
4844 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4848 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4849 if (!operand_type_match (overlap0
, i
.types
[0])
4850 || !operand_type_match (overlap1
, i
.types
[1])
4852 && !operand_type_register_match (overlap0
, i
.types
[0],
4854 overlap1
, i
.types
[1],
4857 /* Check if other direction is valid ... */
4858 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4862 /* Try reversing direction of operands. */
4863 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4864 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4865 if (!operand_type_match (overlap0
, i
.types
[0])
4866 || !operand_type_match (overlap1
, i
.types
[1])
4868 && !operand_type_register_match (overlap0
,
4875 /* Does not match either direction. */
4878 /* found_reverse_match holds which of D or FloatDR
4880 if (t
->opcode_modifier
.d
)
4881 found_reverse_match
= Opcode_D
;
4882 else if (t
->opcode_modifier
.floatd
)
4883 found_reverse_match
= Opcode_FloatD
;
4885 found_reverse_match
= 0;
4886 if (t
->opcode_modifier
.floatr
)
4887 found_reverse_match
|= Opcode_FloatR
;
4891 /* Found a forward 2 operand match here. */
4892 switch (t
->operands
)
4895 overlap4
= operand_type_and (i
.types
[4],
4898 overlap3
= operand_type_and (i
.types
[3],
4901 overlap2
= operand_type_and (i
.types
[2],
4906 switch (t
->operands
)
4909 if (!operand_type_match (overlap4
, i
.types
[4])
4910 || !operand_type_register_match (overlap3
,
4918 if (!operand_type_match (overlap3
, i
.types
[3])
4920 && !operand_type_register_match (overlap2
,
4928 /* Here we make use of the fact that there are no
4929 reverse match 3 operand instructions, and all 3
4930 operand instructions only need to be checked for
4931 register consistency between operands 2 and 3. */
4932 if (!operand_type_match (overlap2
, i
.types
[2])
4934 && !operand_type_register_match (overlap1
,
4944 /* Found either forward/reverse 2, 3 or 4 operand match here:
4945 slip through to break. */
4947 if (!found_cpu_match
)
4949 found_reverse_match
= 0;
4953 /* Check if vector and VEX operands are valid. */
4954 if (check_VecOperands (t
) || VEX_check_operands (t
))
4956 specific_error
= i
.error
;
4960 /* We've found a match; break out of loop. */
4964 if (t
== current_templates
->end
)
4966 /* We found no match. */
4967 const char *err_msg
;
4968 switch (specific_error
? specific_error
: i
.error
)
4972 case operand_size_mismatch
:
4973 err_msg
= _("operand size mismatch");
4975 case operand_type_mismatch
:
4976 err_msg
= _("operand type mismatch");
4978 case register_type_mismatch
:
4979 err_msg
= _("register type mismatch");
4981 case number_of_operands_mismatch
:
4982 err_msg
= _("number of operands mismatch");
4984 case invalid_instruction_suffix
:
4985 err_msg
= _("invalid instruction suffix");
4988 err_msg
= _("constant doesn't fit in 4 bits");
4991 err_msg
= _("only supported with old gcc");
4993 case unsupported_with_intel_mnemonic
:
4994 err_msg
= _("unsupported with Intel mnemonic");
4996 case unsupported_syntax
:
4997 err_msg
= _("unsupported syntax");
5000 as_bad (_("unsupported instruction `%s'"),
5001 current_templates
->start
->name
);
5003 case invalid_vsib_address
:
5004 err_msg
= _("invalid VSIB address");
5006 case invalid_vector_register_set
:
5007 err_msg
= _("mask, index, and destination registers must be distinct");
5009 case unsupported_vector_index_register
:
5010 err_msg
= _("unsupported vector index register");
5012 case unsupported_broadcast
:
5013 err_msg
= _("unsupported broadcast");
5015 case broadcast_not_on_src_operand
:
5016 err_msg
= _("broadcast not on source memory operand");
5018 case broadcast_needed
:
5019 err_msg
= _("broadcast is needed for operand of such type");
5021 case unsupported_masking
:
5022 err_msg
= _("unsupported masking");
5024 case mask_not_on_destination
:
5025 err_msg
= _("mask not on destination operand");
5027 case no_default_mask
:
5028 err_msg
= _("default mask isn't allowed");
5030 case unsupported_rc_sae
:
5031 err_msg
= _("unsupported static rounding/sae");
5033 case rc_sae_operand_not_last_imm
:
5035 err_msg
= _("RC/SAE operand must precede immediate operands");
5037 err_msg
= _("RC/SAE operand must follow immediate operands");
5039 case invalid_register_operand
:
5040 err_msg
= _("invalid register operand");
5043 as_bad (_("%s for `%s'"), err_msg
,
5044 current_templates
->start
->name
);
5048 if (!quiet_warnings
)
5051 && (i
.types
[0].bitfield
.jumpabsolute
5052 != operand_types
[0].bitfield
.jumpabsolute
))
5054 as_warn (_("indirect %s without `*'"), t
->name
);
5057 if (t
->opcode_modifier
.isprefix
5058 && t
->opcode_modifier
.ignoresize
)
5060 /* Warn them that a data or address size prefix doesn't
5061 affect assembly of the next line of code. */
5062 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5066 /* Copy the template we found. */
5069 if (addr_prefix_disp
!= -1)
5070 i
.tm
.operand_types
[addr_prefix_disp
]
5071 = operand_types
[addr_prefix_disp
];
5073 if (found_reverse_match
)
5075 /* If we found a reverse match we must alter the opcode
5076 direction bit. found_reverse_match holds bits to change
5077 (different for int & float insns). */
5079 i
.tm
.base_opcode
^= found_reverse_match
;
5081 i
.tm
.operand_types
[0] = operand_types
[1];
5082 i
.tm
.operand_types
[1] = operand_types
[0];
5091 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5092 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5094 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5096 as_bad (_("`%s' operand %d must use `%ses' segment"),
5102 /* There's only ever one segment override allowed per instruction.
5103 This instruction possibly has a legal segment override on the
5104 second operand, so copy the segment to where non-string
5105 instructions store it, allowing common code. */
5106 i
.seg
[0] = i
.seg
[1];
5108 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5110 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5112 as_bad (_("`%s' operand %d must use `%ses' segment"),
5123 process_suffix (void)
5125 /* If matched instruction specifies an explicit instruction mnemonic
5127 if (i
.tm
.opcode_modifier
.size16
)
5128 i
.suffix
= WORD_MNEM_SUFFIX
;
5129 else if (i
.tm
.opcode_modifier
.size32
)
5130 i
.suffix
= LONG_MNEM_SUFFIX
;
5131 else if (i
.tm
.opcode_modifier
.size64
)
5132 i
.suffix
= QWORD_MNEM_SUFFIX
;
5133 else if (i
.reg_operands
)
5135 /* If there's no instruction mnemonic suffix we try to invent one
5136 based on register operands. */
5139 /* We take i.suffix from the last register operand specified,
5140 Destination register type is more significant than source
5141 register type. crc32 in SSE4.2 prefers source register
5143 if (i
.tm
.base_opcode
== 0xf20f38f1)
5145 if (i
.types
[0].bitfield
.reg16
)
5146 i
.suffix
= WORD_MNEM_SUFFIX
;
5147 else if (i
.types
[0].bitfield
.reg32
)
5148 i
.suffix
= LONG_MNEM_SUFFIX
;
5149 else if (i
.types
[0].bitfield
.reg64
)
5150 i
.suffix
= QWORD_MNEM_SUFFIX
;
5152 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5154 if (i
.types
[0].bitfield
.reg8
)
5155 i
.suffix
= BYTE_MNEM_SUFFIX
;
5162 if (i
.tm
.base_opcode
== 0xf20f38f1
5163 || i
.tm
.base_opcode
== 0xf20f38f0)
5165 /* We have to know the operand size for crc32. */
5166 as_bad (_("ambiguous memory operand size for `%s`"),
5171 for (op
= i
.operands
; --op
>= 0;)
5172 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5174 if (i
.types
[op
].bitfield
.reg8
)
5176 i
.suffix
= BYTE_MNEM_SUFFIX
;
5179 else if (i
.types
[op
].bitfield
.reg16
)
5181 i
.suffix
= WORD_MNEM_SUFFIX
;
5184 else if (i
.types
[op
].bitfield
.reg32
)
5186 i
.suffix
= LONG_MNEM_SUFFIX
;
5189 else if (i
.types
[op
].bitfield
.reg64
)
5191 i
.suffix
= QWORD_MNEM_SUFFIX
;
5197 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5200 && i
.tm
.opcode_modifier
.ignoresize
5201 && i
.tm
.opcode_modifier
.no_bsuf
)
5203 else if (!check_byte_reg ())
5206 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5209 && i
.tm
.opcode_modifier
.ignoresize
5210 && i
.tm
.opcode_modifier
.no_lsuf
)
5212 else if (!check_long_reg ())
5215 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5218 && i
.tm
.opcode_modifier
.ignoresize
5219 && i
.tm
.opcode_modifier
.no_qsuf
)
5221 else if (!check_qword_reg ())
5224 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5227 && i
.tm
.opcode_modifier
.ignoresize
5228 && i
.tm
.opcode_modifier
.no_wsuf
)
5230 else if (!check_word_reg ())
5233 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5234 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5235 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5237 /* Skip if the instruction has x/y/z suffix. match_template
5238 should check if it is a valid suffix. */
5240 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5241 /* Do nothing if the instruction is going to ignore the prefix. */
5246 else if (i
.tm
.opcode_modifier
.defaultsize
5248 /* exclude fldenv/frstor/fsave/fstenv */
5249 && i
.tm
.opcode_modifier
.no_ssuf
)
5251 i
.suffix
= stackop_size
;
5253 else if (intel_syntax
5255 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5256 || i
.tm
.opcode_modifier
.jumpbyte
5257 || i
.tm
.opcode_modifier
.jumpintersegment
5258 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5259 && i
.tm
.extension_opcode
<= 3)))
5264 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5266 i
.suffix
= QWORD_MNEM_SUFFIX
;
5270 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5271 i
.suffix
= LONG_MNEM_SUFFIX
;
5274 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5275 i
.suffix
= WORD_MNEM_SUFFIX
;
5284 if (i
.tm
.opcode_modifier
.w
)
5286 as_bad (_("no instruction mnemonic suffix given and "
5287 "no register operands; can't size instruction"));
5293 unsigned int suffixes
;
5295 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5296 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5298 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5300 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5302 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5304 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5307 /* There are more than suffix matches. */
5308 if (i
.tm
.opcode_modifier
.w
5309 || ((suffixes
& (suffixes
- 1))
5310 && !i
.tm
.opcode_modifier
.defaultsize
5311 && !i
.tm
.opcode_modifier
.ignoresize
))
5313 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5319 /* Change the opcode based on the operand size given by i.suffix;
5320 We don't need to change things for byte insns. */
5323 && i
.suffix
!= BYTE_MNEM_SUFFIX
5324 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5325 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5326 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5328 /* It's not a byte, select word/dword operation. */
5329 if (i
.tm
.opcode_modifier
.w
)
5331 if (i
.tm
.opcode_modifier
.shortform
)
5332 i
.tm
.base_opcode
|= 8;
5334 i
.tm
.base_opcode
|= 1;
5337 /* Now select between word & dword operations via the operand
5338 size prefix, except for instructions that will ignore this
5340 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5342 /* The address size override prefix changes the size of the
5344 if ((flag_code
== CODE_32BIT
5345 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5346 || (flag_code
!= CODE_32BIT
5347 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5348 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5351 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5352 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5353 && !i
.tm
.opcode_modifier
.ignoresize
5354 && !i
.tm
.opcode_modifier
.floatmf
5355 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5356 || (flag_code
== CODE_64BIT
5357 && i
.tm
.opcode_modifier
.jumpbyte
)))
5359 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5361 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5362 prefix
= ADDR_PREFIX_OPCODE
;
5364 if (!add_prefix (prefix
))
5368 /* Set mode64 for an operand. */
5369 if (i
.suffix
== QWORD_MNEM_SUFFIX
5370 && flag_code
== CODE_64BIT
5371 && !i
.tm
.opcode_modifier
.norex64
)
5373 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5374 need rex64. cmpxchg8b is also a special case. */
5375 if (! (i
.operands
== 2
5376 && i
.tm
.base_opcode
== 0x90
5377 && i
.tm
.extension_opcode
== None
5378 && operand_type_equal (&i
.types
[0], &acc64
)
5379 && operand_type_equal (&i
.types
[1], &acc64
))
5380 && ! (i
.operands
== 1
5381 && i
.tm
.base_opcode
== 0xfc7
5382 && i
.tm
.extension_opcode
== 1
5383 && !operand_type_check (i
.types
[0], reg
)
5384 && operand_type_check (i
.types
[0], anymem
)))
5388 /* Size floating point instruction. */
5389 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5390 if (i
.tm
.opcode_modifier
.floatmf
)
5391 i
.tm
.base_opcode
^= 4;
5398 check_byte_reg (void)
5402 for (op
= i
.operands
; --op
>= 0;)
5404 /* If this is an eight bit register, it's OK. If it's the 16 or
5405 32 bit version of an eight bit register, we will just use the
5406 low portion, and that's OK too. */
5407 if (i
.types
[op
].bitfield
.reg8
)
5410 /* I/O port address operands are OK too. */
5411 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5414 /* crc32 doesn't generate this warning. */
5415 if (i
.tm
.base_opcode
== 0xf20f38f0)
5418 if ((i
.types
[op
].bitfield
.reg16
5419 || i
.types
[op
].bitfield
.reg32
5420 || i
.types
[op
].bitfield
.reg64
)
5421 && i
.op
[op
].regs
->reg_num
< 4
5422 /* Prohibit these changes in 64bit mode, since the lowering
5423 would be more complicated. */
5424 && flag_code
!= CODE_64BIT
)
5426 #if REGISTER_WARNINGS
5427 if (!quiet_warnings
)
5428 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5430 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5431 ? REGNAM_AL
- REGNAM_AX
5432 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5434 i
.op
[op
].regs
->reg_name
,
5439 /* Any other register is bad. */
5440 if (i
.types
[op
].bitfield
.reg16
5441 || i
.types
[op
].bitfield
.reg32
5442 || i
.types
[op
].bitfield
.reg64
5443 || i
.types
[op
].bitfield
.regmmx
5444 || i
.types
[op
].bitfield
.regxmm
5445 || i
.types
[op
].bitfield
.regymm
5446 || i
.types
[op
].bitfield
.regzmm
5447 || i
.types
[op
].bitfield
.sreg2
5448 || i
.types
[op
].bitfield
.sreg3
5449 || i
.types
[op
].bitfield
.control
5450 || i
.types
[op
].bitfield
.debug
5451 || i
.types
[op
].bitfield
.test
5452 || i
.types
[op
].bitfield
.floatreg
5453 || i
.types
[op
].bitfield
.floatacc
)
5455 as_bad (_("`%s%s' not allowed with `%s%c'"),
5457 i
.op
[op
].regs
->reg_name
,
5467 check_long_reg (void)
5471 for (op
= i
.operands
; --op
>= 0;)
5472 /* Reject eight bit registers, except where the template requires
5473 them. (eg. movzb) */
5474 if (i
.types
[op
].bitfield
.reg8
5475 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5476 || i
.tm
.operand_types
[op
].bitfield
.reg32
5477 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5479 as_bad (_("`%s%s' not allowed with `%s%c'"),
5481 i
.op
[op
].regs
->reg_name
,
5486 /* Warn if the e prefix on a general reg is missing. */
5487 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5488 && i
.types
[op
].bitfield
.reg16
5489 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5490 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5492 /* Prohibit these changes in the 64bit mode, since the
5493 lowering is more complicated. */
5494 if (flag_code
== CODE_64BIT
)
5496 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5497 register_prefix
, i
.op
[op
].regs
->reg_name
,
5501 #if REGISTER_WARNINGS
5502 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5504 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5505 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5508 /* Warn if the r prefix on a general reg is present. */
5509 else if (i
.types
[op
].bitfield
.reg64
5510 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5511 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5514 && i
.tm
.opcode_modifier
.toqword
5515 && !i
.types
[0].bitfield
.regxmm
)
5517 /* Convert to QWORD. We want REX byte. */
5518 i
.suffix
= QWORD_MNEM_SUFFIX
;
5522 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5523 register_prefix
, i
.op
[op
].regs
->reg_name
,
5532 check_qword_reg (void)
5536 for (op
= i
.operands
; --op
>= 0; )
5537 /* Reject eight bit registers, except where the template requires
5538 them. (eg. movzb) */
5539 if (i
.types
[op
].bitfield
.reg8
5540 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5541 || i
.tm
.operand_types
[op
].bitfield
.reg32
5542 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5544 as_bad (_("`%s%s' not allowed with `%s%c'"),
5546 i
.op
[op
].regs
->reg_name
,
5551 /* Warn if the r prefix on a general reg is missing. */
5552 else if ((i
.types
[op
].bitfield
.reg16
5553 || i
.types
[op
].bitfield
.reg32
)
5554 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5555 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5557 /* Prohibit these changes in the 64bit mode, since the
5558 lowering is more complicated. */
5560 && i
.tm
.opcode_modifier
.todword
5561 && !i
.types
[0].bitfield
.regxmm
)
5563 /* Convert to DWORD. We don't want REX byte. */
5564 i
.suffix
= LONG_MNEM_SUFFIX
;
5568 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5569 register_prefix
, i
.op
[op
].regs
->reg_name
,
5578 check_word_reg (void)
5581 for (op
= i
.operands
; --op
>= 0;)
5582 /* Reject eight bit registers, except where the template requires
5583 them. (eg. movzb) */
5584 if (i
.types
[op
].bitfield
.reg8
5585 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5586 || i
.tm
.operand_types
[op
].bitfield
.reg32
5587 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5589 as_bad (_("`%s%s' not allowed with `%s%c'"),
5591 i
.op
[op
].regs
->reg_name
,
5596 /* Warn if the e or r prefix on a general reg is present. */
5597 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5598 && (i
.types
[op
].bitfield
.reg32
5599 || i
.types
[op
].bitfield
.reg64
)
5600 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5601 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5603 /* Prohibit these changes in the 64bit mode, since the
5604 lowering is more complicated. */
5605 if (flag_code
== CODE_64BIT
)
5607 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5608 register_prefix
, i
.op
[op
].regs
->reg_name
,
5612 #if REGISTER_WARNINGS
5613 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5615 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5616 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5623 update_imm (unsigned int j
)
5625 i386_operand_type overlap
= i
.types
[j
];
5626 if ((overlap
.bitfield
.imm8
5627 || overlap
.bitfield
.imm8s
5628 || overlap
.bitfield
.imm16
5629 || overlap
.bitfield
.imm32
5630 || overlap
.bitfield
.imm32s
5631 || overlap
.bitfield
.imm64
)
5632 && !operand_type_equal (&overlap
, &imm8
)
5633 && !operand_type_equal (&overlap
, &imm8s
)
5634 && !operand_type_equal (&overlap
, &imm16
)
5635 && !operand_type_equal (&overlap
, &imm32
)
5636 && !operand_type_equal (&overlap
, &imm32s
)
5637 && !operand_type_equal (&overlap
, &imm64
))
5641 i386_operand_type temp
;
5643 operand_type_set (&temp
, 0);
5644 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5646 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5647 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5649 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5650 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5651 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5653 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5654 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5657 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5660 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5661 || operand_type_equal (&overlap
, &imm16_32
)
5662 || operand_type_equal (&overlap
, &imm16_32s
))
5664 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5669 if (!operand_type_equal (&overlap
, &imm8
)
5670 && !operand_type_equal (&overlap
, &imm8s
)
5671 && !operand_type_equal (&overlap
, &imm16
)
5672 && !operand_type_equal (&overlap
, &imm32
)
5673 && !operand_type_equal (&overlap
, &imm32s
)
5674 && !operand_type_equal (&overlap
, &imm64
))
5676 as_bad (_("no instruction mnemonic suffix given; "
5677 "can't determine immediate size"));
5681 i
.types
[j
] = overlap
;
5691 /* Update the first 2 immediate operands. */
5692 n
= i
.operands
> 2 ? 2 : i
.operands
;
5695 for (j
= 0; j
< n
; j
++)
5696 if (update_imm (j
) == 0)
5699 /* The 3rd operand can't be immediate operand. */
5700 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5707 bad_implicit_operand (int xmm
)
5709 const char *ireg
= xmm
? "xmm0" : "ymm0";
5712 as_bad (_("the last operand of `%s' must be `%s%s'"),
5713 i
.tm
.name
, register_prefix
, ireg
);
5715 as_bad (_("the first operand of `%s' must be `%s%s'"),
5716 i
.tm
.name
, register_prefix
, ireg
);
5721 process_operands (void)
5723 /* Default segment register this instruction will use for memory
5724 accesses. 0 means unknown. This is only for optimizing out
5725 unnecessary segment overrides. */
5726 const seg_entry
*default_seg
= 0;
5728 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5730 unsigned int dupl
= i
.operands
;
5731 unsigned int dest
= dupl
- 1;
5734 /* The destination must be an xmm register. */
5735 gas_assert (i
.reg_operands
5736 && MAX_OPERANDS
> dupl
5737 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5739 if (i
.tm
.opcode_modifier
.firstxmm0
)
5741 /* The first operand is implicit and must be xmm0. */
5742 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5743 if (register_number (i
.op
[0].regs
) != 0)
5744 return bad_implicit_operand (1);
5746 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5748 /* Keep xmm0 for instructions with VEX prefix and 3
5754 /* We remove the first xmm0 and keep the number of
5755 operands unchanged, which in fact duplicates the
5757 for (j
= 1; j
< i
.operands
; j
++)
5759 i
.op
[j
- 1] = i
.op
[j
];
5760 i
.types
[j
- 1] = i
.types
[j
];
5761 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5765 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5767 gas_assert ((MAX_OPERANDS
- 1) > dupl
5768 && (i
.tm
.opcode_modifier
.vexsources
5771 /* Add the implicit xmm0 for instructions with VEX prefix
5773 for (j
= i
.operands
; j
> 0; j
--)
5775 i
.op
[j
] = i
.op
[j
- 1];
5776 i
.types
[j
] = i
.types
[j
- 1];
5777 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5780 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5781 i
.types
[0] = regxmm
;
5782 i
.tm
.operand_types
[0] = regxmm
;
5785 i
.reg_operands
+= 2;
5790 i
.op
[dupl
] = i
.op
[dest
];
5791 i
.types
[dupl
] = i
.types
[dest
];
5792 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5801 i
.op
[dupl
] = i
.op
[dest
];
5802 i
.types
[dupl
] = i
.types
[dest
];
5803 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5806 if (i
.tm
.opcode_modifier
.immext
)
5809 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5813 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5814 gas_assert (i
.reg_operands
5815 && (operand_type_equal (&i
.types
[0], ®xmm
)
5816 || operand_type_equal (&i
.types
[0], ®ymm
)
5817 || operand_type_equal (&i
.types
[0], ®zmm
)));
5818 if (register_number (i
.op
[0].regs
) != 0)
5819 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5821 for (j
= 1; j
< i
.operands
; j
++)
5823 i
.op
[j
- 1] = i
.op
[j
];
5824 i
.types
[j
- 1] = i
.types
[j
];
5826 /* We need to adjust fields in i.tm since they are used by
5827 build_modrm_byte. */
5828 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5835 else if (i
.tm
.opcode_modifier
.regkludge
)
5837 /* The imul $imm, %reg instruction is converted into
5838 imul $imm, %reg, %reg, and the clr %reg instruction
5839 is converted into xor %reg, %reg. */
5841 unsigned int first_reg_op
;
5843 if (operand_type_check (i
.types
[0], reg
))
5847 /* Pretend we saw the extra register operand. */
5848 gas_assert (i
.reg_operands
== 1
5849 && i
.op
[first_reg_op
+ 1].regs
== 0);
5850 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5851 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5856 if (i
.tm
.opcode_modifier
.shortform
)
5858 if (i
.types
[0].bitfield
.sreg2
5859 || i
.types
[0].bitfield
.sreg3
)
5861 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5862 && i
.op
[0].regs
->reg_num
== 1)
5864 as_bad (_("you can't `pop %scs'"), register_prefix
);
5867 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5868 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5873 /* The register or float register operand is in operand
5877 if (i
.types
[0].bitfield
.floatreg
5878 || operand_type_check (i
.types
[0], reg
))
5882 /* Register goes in low 3 bits of opcode. */
5883 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5884 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5886 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5888 /* Warn about some common errors, but press on regardless.
5889 The first case can be generated by gcc (<= 2.8.1). */
5890 if (i
.operands
== 2)
5892 /* Reversed arguments on faddp, fsubp, etc. */
5893 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5894 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5895 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5899 /* Extraneous `l' suffix on fp insn. */
5900 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5901 register_prefix
, i
.op
[0].regs
->reg_name
);
5906 else if (i
.tm
.opcode_modifier
.modrm
)
5908 /* The opcode is completed (modulo i.tm.extension_opcode which
5909 must be put into the modrm byte). Now, we make the modrm and
5910 index base bytes based on all the info we've collected. */
5912 default_seg
= build_modrm_byte ();
5914 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5918 else if (i
.tm
.opcode_modifier
.isstring
)
5920 /* For the string instructions that allow a segment override
5921 on one of their operands, the default segment is ds. */
5925 if (i
.tm
.base_opcode
== 0x8d /* lea */
5928 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5930 /* If a segment was explicitly specified, and the specified segment
5931 is not the default, use an opcode prefix to select it. If we
5932 never figured out what the default segment is, then default_seg
5933 will be zero at this point, and the specified segment prefix will
5935 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5937 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5943 static const seg_entry
*
5944 build_modrm_byte (void)
5946 const seg_entry
*default_seg
= 0;
5947 unsigned int source
, dest
;
5950 /* The first operand of instructions with VEX prefix and 3 sources
5951 must be VEX_Imm4. */
5952 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5955 unsigned int nds
, reg_slot
;
5958 if (i
.tm
.opcode_modifier
.veximmext
5959 && i
.tm
.opcode_modifier
.immext
)
5961 dest
= i
.operands
- 2;
5962 gas_assert (dest
== 3);
5965 dest
= i
.operands
- 1;
5968 /* There are 2 kinds of instructions:
5969 1. 5 operands: 4 register operands or 3 register operands
5970 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5971 VexW0 or VexW1. The destination must be either XMM, YMM or
5973 2. 4 operands: 4 register operands or 3 register operands
5974 plus 1 memory operand, VexXDS, and VexImmExt */
5975 gas_assert ((i
.reg_operands
== 4
5976 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5977 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5978 && (i
.tm
.opcode_modifier
.veximmext
5979 || (i
.imm_operands
== 1
5980 && i
.types
[0].bitfield
.vec_imm4
5981 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5982 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5983 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5984 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5985 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5987 if (i
.imm_operands
== 0)
5989 /* When there is no immediate operand, generate an 8bit
5990 immediate operand to encode the first operand. */
5991 exp
= &im_expressions
[i
.imm_operands
++];
5992 i
.op
[i
.operands
].imms
= exp
;
5993 i
.types
[i
.operands
] = imm8
;
5995 /* If VexW1 is set, the first operand is the source and
5996 the second operand is encoded in the immediate operand. */
5997 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6008 /* FMA swaps REG and NDS. */
6009 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6017 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6019 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6021 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6023 exp
->X_op
= O_constant
;
6024 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6025 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6029 unsigned int imm_slot
;
6031 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6033 /* If VexW0 is set, the third operand is the source and
6034 the second operand is encoded in the immediate
6041 /* VexW1 is set, the second operand is the source and
6042 the third operand is encoded in the immediate
6048 if (i
.tm
.opcode_modifier
.immext
)
6050 /* When ImmExt is set, the immdiate byte is the last
6052 imm_slot
= i
.operands
- 1;
6060 /* Turn on Imm8 so that output_imm will generate it. */
6061 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6064 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6066 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6068 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6070 i
.op
[imm_slot
].imms
->X_add_number
6071 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6072 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6075 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6076 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6078 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6080 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6085 /* i.reg_operands MUST be the number of real register operands;
6086 implicit registers do not count. If there are 3 register
6087 operands, it must be a instruction with VexNDS. For a
6088 instruction with VexNDD, the destination register is encoded
6089 in VEX prefix. If there are 4 register operands, it must be
6090 a instruction with VEX prefix and 3 sources. */
6091 if (i
.mem_operands
== 0
6092 && ((i
.reg_operands
== 2
6093 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6094 || (i
.reg_operands
== 3
6095 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6096 || (i
.reg_operands
== 4 && vex_3_sources
)))
6104 /* When there are 3 operands, one of them may be immediate,
6105 which may be the first or the last operand. Otherwise,
6106 the first operand must be shift count register (cl) or it
6107 is an instruction with VexNDS. */
6108 gas_assert (i
.imm_operands
== 1
6109 || (i
.imm_operands
== 0
6110 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6111 || i
.types
[0].bitfield
.shiftcount
)));
6112 if (operand_type_check (i
.types
[0], imm
)
6113 || i
.types
[0].bitfield
.shiftcount
)
6119 /* When there are 4 operands, the first two must be 8bit
6120 immediate operands. The source operand will be the 3rd
6123 For instructions with VexNDS, if the first operand
6124 an imm8, the source operand is the 2nd one. If the last
6125 operand is imm8, the source operand is the first one. */
6126 gas_assert ((i
.imm_operands
== 2
6127 && i
.types
[0].bitfield
.imm8
6128 && i
.types
[1].bitfield
.imm8
)
6129 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6130 && i
.imm_operands
== 1
6131 && (i
.types
[0].bitfield
.imm8
6132 || i
.types
[i
.operands
- 1].bitfield
.imm8
6134 if (i
.imm_operands
== 2)
6138 if (i
.types
[0].bitfield
.imm8
)
6145 if (i
.tm
.opcode_modifier
.evex
)
6147 /* For EVEX instructions, when there are 5 operands, the
6148 first one must be immediate operand. If the second one
6149 is immediate operand, the source operand is the 3th
6150 one. If the last one is immediate operand, the source
6151 operand is the 2nd one. */
6152 gas_assert (i
.imm_operands
== 2
6153 && i
.tm
.opcode_modifier
.sae
6154 && operand_type_check (i
.types
[0], imm
));
6155 if (operand_type_check (i
.types
[1], imm
))
6157 else if (operand_type_check (i
.types
[4], imm
))
6171 /* RC/SAE operand could be between DEST and SRC. That happens
6172 when one operand is GPR and the other one is XMM/YMM/ZMM
6174 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6177 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6179 /* For instructions with VexNDS, the register-only source
6180 operand must be 32/64bit integer, XMM, YMM or ZMM
6181 register. It is encoded in VEX prefix. We need to
6182 clear RegMem bit before calling operand_type_equal. */
6184 i386_operand_type op
;
6187 /* Check register-only source operand when two source
6188 operands are swapped. */
6189 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6190 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6198 op
= i
.tm
.operand_types
[vvvv
];
6199 op
.bitfield
.regmem
= 0;
6200 if ((dest
+ 1) >= i
.operands
6201 || (!op
.bitfield
.reg32
6202 && op
.bitfield
.reg64
6203 && !operand_type_equal (&op
, ®xmm
)
6204 && !operand_type_equal (&op
, ®ymm
)
6205 && !operand_type_equal (&op
, ®zmm
)
6206 && !operand_type_equal (&op
, ®mask
)))
6208 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6214 /* One of the register operands will be encoded in the i.tm.reg
6215 field, the other in the combined i.tm.mode and i.tm.regmem
6216 fields. If no form of this instruction supports a memory
6217 destination operand, then we assume the source operand may
6218 sometimes be a memory operand and so we need to store the
6219 destination in the i.rm.reg field. */
6220 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6221 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6223 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6224 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6225 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6227 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6229 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6231 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6236 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6237 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6238 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6240 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6242 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6244 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6247 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6249 if (!i
.types
[0].bitfield
.control
6250 && !i
.types
[1].bitfield
.control
)
6252 i
.rex
&= ~(REX_R
| REX_B
);
6253 add_prefix (LOCK_PREFIX_OPCODE
);
6257 { /* If it's not 2 reg operands... */
6262 unsigned int fake_zero_displacement
= 0;
6265 for (op
= 0; op
< i
.operands
; op
++)
6266 if (operand_type_check (i
.types
[op
], anymem
))
6268 gas_assert (op
< i
.operands
);
6270 if (i
.tm
.opcode_modifier
.vecsib
)
6272 if (i
.index_reg
->reg_num
== RegEiz
6273 || i
.index_reg
->reg_num
== RegRiz
)
6276 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6279 i
.sib
.base
= NO_BASE_REGISTER
;
6280 i
.sib
.scale
= i
.log2_scale_factor
;
6281 /* No Vec_Disp8 if there is no base. */
6282 i
.types
[op
].bitfield
.vec_disp8
= 0;
6283 i
.types
[op
].bitfield
.disp8
= 0;
6284 i
.types
[op
].bitfield
.disp16
= 0;
6285 i
.types
[op
].bitfield
.disp64
= 0;
6286 if (flag_code
!= CODE_64BIT
)
6288 /* Must be 32 bit */
6289 i
.types
[op
].bitfield
.disp32
= 1;
6290 i
.types
[op
].bitfield
.disp32s
= 0;
6294 i
.types
[op
].bitfield
.disp32
= 0;
6295 i
.types
[op
].bitfield
.disp32s
= 1;
6298 i
.sib
.index
= i
.index_reg
->reg_num
;
6299 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6301 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6307 if (i
.base_reg
== 0)
6310 if (!i
.disp_operands
)
6312 fake_zero_displacement
= 1;
6313 /* Instructions with VSIB byte need 32bit displacement
6314 if there is no base register. */
6315 if (i
.tm
.opcode_modifier
.vecsib
)
6316 i
.types
[op
].bitfield
.disp32
= 1;
6318 if (i
.index_reg
== 0)
6320 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6321 /* Operand is just <disp> */
6322 if (flag_code
== CODE_64BIT
)
6324 /* 64bit mode overwrites the 32bit absolute
6325 addressing by RIP relative addressing and
6326 absolute addressing is encoded by one of the
6327 redundant SIB forms. */
6328 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6329 i
.sib
.base
= NO_BASE_REGISTER
;
6330 i
.sib
.index
= NO_INDEX_REGISTER
;
6331 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6332 ? disp32s
: disp32
);
6334 else if ((flag_code
== CODE_16BIT
)
6335 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6337 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6338 i
.types
[op
] = disp16
;
6342 i
.rm
.regmem
= NO_BASE_REGISTER
;
6343 i
.types
[op
] = disp32
;
6346 else if (!i
.tm
.opcode_modifier
.vecsib
)
6348 /* !i.base_reg && i.index_reg */
6349 if (i
.index_reg
->reg_num
== RegEiz
6350 || i
.index_reg
->reg_num
== RegRiz
)
6351 i
.sib
.index
= NO_INDEX_REGISTER
;
6353 i
.sib
.index
= i
.index_reg
->reg_num
;
6354 i
.sib
.base
= NO_BASE_REGISTER
;
6355 i
.sib
.scale
= i
.log2_scale_factor
;
6356 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6357 /* No Vec_Disp8 if there is no base. */
6358 i
.types
[op
].bitfield
.vec_disp8
= 0;
6359 i
.types
[op
].bitfield
.disp8
= 0;
6360 i
.types
[op
].bitfield
.disp16
= 0;
6361 i
.types
[op
].bitfield
.disp64
= 0;
6362 if (flag_code
!= CODE_64BIT
)
6364 /* Must be 32 bit */
6365 i
.types
[op
].bitfield
.disp32
= 1;
6366 i
.types
[op
].bitfield
.disp32s
= 0;
6370 i
.types
[op
].bitfield
.disp32
= 0;
6371 i
.types
[op
].bitfield
.disp32s
= 1;
6373 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6377 /* RIP addressing for 64bit mode. */
6378 else if (i
.base_reg
->reg_num
== RegRip
||
6379 i
.base_reg
->reg_num
== RegEip
)
6381 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6382 i
.rm
.regmem
= NO_BASE_REGISTER
;
6383 i
.types
[op
].bitfield
.disp8
= 0;
6384 i
.types
[op
].bitfield
.disp16
= 0;
6385 i
.types
[op
].bitfield
.disp32
= 0;
6386 i
.types
[op
].bitfield
.disp32s
= 1;
6387 i
.types
[op
].bitfield
.disp64
= 0;
6388 i
.types
[op
].bitfield
.vec_disp8
= 0;
6389 i
.flags
[op
] |= Operand_PCrel
;
6390 if (! i
.disp_operands
)
6391 fake_zero_displacement
= 1;
6393 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6395 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6396 switch (i
.base_reg
->reg_num
)
6399 if (i
.index_reg
== 0)
6401 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6402 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6406 if (i
.index_reg
== 0)
6409 if (operand_type_check (i
.types
[op
], disp
) == 0)
6411 /* fake (%bp) into 0(%bp) */
6412 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6413 i
.types
[op
].bitfield
.vec_disp8
= 1;
6415 i
.types
[op
].bitfield
.disp8
= 1;
6416 fake_zero_displacement
= 1;
6419 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6420 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6422 default: /* (%si) -> 4 or (%di) -> 5 */
6423 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6425 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6427 else /* i.base_reg and 32/64 bit mode */
6429 if (flag_code
== CODE_64BIT
6430 && operand_type_check (i
.types
[op
], disp
))
6432 i386_operand_type temp
;
6433 operand_type_set (&temp
, 0);
6434 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6435 temp
.bitfield
.vec_disp8
6436 = i
.types
[op
].bitfield
.vec_disp8
;
6438 if (i
.prefix
[ADDR_PREFIX
] == 0)
6439 i
.types
[op
].bitfield
.disp32s
= 1;
6441 i
.types
[op
].bitfield
.disp32
= 1;
6444 if (!i
.tm
.opcode_modifier
.vecsib
)
6445 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6446 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6448 i
.sib
.base
= i
.base_reg
->reg_num
;
6449 /* x86-64 ignores REX prefix bit here to avoid decoder
6451 if (!(i
.base_reg
->reg_flags
& RegRex
)
6452 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6453 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6455 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6457 fake_zero_displacement
= 1;
6458 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6459 i
.types
[op
].bitfield
.vec_disp8
= 1;
6461 i
.types
[op
].bitfield
.disp8
= 1;
6463 i
.sib
.scale
= i
.log2_scale_factor
;
6464 if (i
.index_reg
== 0)
6466 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6467 /* <disp>(%esp) becomes two byte modrm with no index
6468 register. We've already stored the code for esp
6469 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6470 Any base register besides %esp will not use the
6471 extra modrm byte. */
6472 i
.sib
.index
= NO_INDEX_REGISTER
;
6474 else if (!i
.tm
.opcode_modifier
.vecsib
)
6476 if (i
.index_reg
->reg_num
== RegEiz
6477 || i
.index_reg
->reg_num
== RegRiz
)
6478 i
.sib
.index
= NO_INDEX_REGISTER
;
6480 i
.sib
.index
= i
.index_reg
->reg_num
;
6481 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6482 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6487 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6488 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6492 if (!fake_zero_displacement
6496 fake_zero_displacement
= 1;
6497 if (i
.disp_encoding
== disp_encoding_8bit
)
6498 i
.types
[op
].bitfield
.disp8
= 1;
6500 i
.types
[op
].bitfield
.disp32
= 1;
6502 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6506 if (fake_zero_displacement
)
6508 /* Fakes a zero displacement assuming that i.types[op]
6509 holds the correct displacement size. */
6512 gas_assert (i
.op
[op
].disps
== 0);
6513 exp
= &disp_expressions
[i
.disp_operands
++];
6514 i
.op
[op
].disps
= exp
;
6515 exp
->X_op
= O_constant
;
6516 exp
->X_add_number
= 0;
6517 exp
->X_add_symbol
= (symbolS
*) 0;
6518 exp
->X_op_symbol
= (symbolS
*) 0;
6526 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6528 if (operand_type_check (i
.types
[0], imm
))
6529 i
.vex
.register_specifier
= NULL
;
6532 /* VEX.vvvv encodes one of the sources when the first
6533 operand is not an immediate. */
6534 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6535 i
.vex
.register_specifier
= i
.op
[0].regs
;
6537 i
.vex
.register_specifier
= i
.op
[1].regs
;
6540 /* Destination is a XMM register encoded in the ModRM.reg
6542 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6543 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6546 /* ModRM.rm and VEX.B encodes the other source. */
6547 if (!i
.mem_operands
)
6551 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6552 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6554 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6556 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6560 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6562 i
.vex
.register_specifier
= i
.op
[2].regs
;
6563 if (!i
.mem_operands
)
6566 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6567 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6571 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6572 (if any) based on i.tm.extension_opcode. Again, we must be
6573 careful to make sure that segment/control/debug/test/MMX
6574 registers are coded into the i.rm.reg field. */
6575 else if (i
.reg_operands
)
6578 unsigned int vex_reg
= ~0;
6580 for (op
= 0; op
< i
.operands
; op
++)
6581 if (i
.types
[op
].bitfield
.reg8
6582 || i
.types
[op
].bitfield
.reg16
6583 || i
.types
[op
].bitfield
.reg32
6584 || i
.types
[op
].bitfield
.reg64
6585 || i
.types
[op
].bitfield
.regmmx
6586 || i
.types
[op
].bitfield
.regxmm
6587 || i
.types
[op
].bitfield
.regymm
6588 || i
.types
[op
].bitfield
.regbnd
6589 || i
.types
[op
].bitfield
.regzmm
6590 || i
.types
[op
].bitfield
.regmask
6591 || i
.types
[op
].bitfield
.sreg2
6592 || i
.types
[op
].bitfield
.sreg3
6593 || i
.types
[op
].bitfield
.control
6594 || i
.types
[op
].bitfield
.debug
6595 || i
.types
[op
].bitfield
.test
)
6600 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6602 /* For instructions with VexNDS, the register-only
6603 source operand is encoded in VEX prefix. */
6604 gas_assert (mem
!= (unsigned int) ~0);
6609 gas_assert (op
< i
.operands
);
6613 /* Check register-only source operand when two source
6614 operands are swapped. */
6615 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6616 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6620 gas_assert (mem
== (vex_reg
+ 1)
6621 && op
< i
.operands
);
6626 gas_assert (vex_reg
< i
.operands
);
6630 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6632 /* For instructions with VexNDD, the register destination
6633 is encoded in VEX prefix. */
6634 if (i
.mem_operands
== 0)
6636 /* There is no memory operand. */
6637 gas_assert ((op
+ 2) == i
.operands
);
6642 /* There are only 2 operands. */
6643 gas_assert (op
< 2 && i
.operands
== 2);
6648 gas_assert (op
< i
.operands
);
6650 if (vex_reg
!= (unsigned int) ~0)
6652 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6654 if (type
->bitfield
.reg32
!= 1
6655 && type
->bitfield
.reg64
!= 1
6656 && !operand_type_equal (type
, ®xmm
)
6657 && !operand_type_equal (type
, ®ymm
)
6658 && !operand_type_equal (type
, ®zmm
)
6659 && !operand_type_equal (type
, ®mask
))
6662 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6665 /* Don't set OP operand twice. */
6668 /* If there is an extension opcode to put here, the
6669 register number must be put into the regmem field. */
6670 if (i
.tm
.extension_opcode
!= None
)
6672 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6673 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6675 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6680 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6681 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6683 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6688 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6689 must set it to 3 to indicate this is a register operand
6690 in the regmem field. */
6691 if (!i
.mem_operands
)
6695 /* Fill in i.rm.reg field with extension opcode (if any). */
6696 if (i
.tm
.extension_opcode
!= None
)
6697 i
.rm
.reg
= i
.tm
.extension_opcode
;
6703 output_branch (void)
6709 relax_substateT subtype
;
6713 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6714 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6717 if (i
.prefix
[DATA_PREFIX
] != 0)
6723 /* Pentium4 branch hints. */
6724 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6725 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6730 if (i
.prefix
[REX_PREFIX
] != 0)
6736 /* BND prefixed jump. */
6737 if (i
.prefix
[BND_PREFIX
] != 0)
6739 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6743 if (i
.prefixes
!= 0 && !intel_syntax
)
6744 as_warn (_("skipping prefixes on this instruction"));
6746 /* It's always a symbol; End frag & setup for relax.
6747 Make sure there is enough room in this frag for the largest
6748 instruction we may generate in md_convert_frag. This is 2
6749 bytes for the opcode and room for the prefix and largest
6751 frag_grow (prefix
+ 2 + 4);
6752 /* Prefix and 1 opcode byte go in fr_fix. */
6753 p
= frag_more (prefix
+ 1);
6754 if (i
.prefix
[DATA_PREFIX
] != 0)
6755 *p
++ = DATA_PREFIX_OPCODE
;
6756 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6757 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6758 *p
++ = i
.prefix
[SEG_PREFIX
];
6759 if (i
.prefix
[REX_PREFIX
] != 0)
6760 *p
++ = i
.prefix
[REX_PREFIX
];
6761 *p
= i
.tm
.base_opcode
;
6763 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6764 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6765 else if (cpu_arch_flags
.bitfield
.cpui386
)
6766 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6768 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6771 sym
= i
.op
[0].disps
->X_add_symbol
;
6772 off
= i
.op
[0].disps
->X_add_number
;
6774 if (i
.op
[0].disps
->X_op
!= O_constant
6775 && i
.op
[0].disps
->X_op
!= O_symbol
)
6777 /* Handle complex expressions. */
6778 sym
= make_expr_symbol (i
.op
[0].disps
);
6782 /* 1 possible extra opcode + 4 byte displacement go in var part.
6783 Pass reloc in fr_var. */
6784 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6794 if (i
.tm
.opcode_modifier
.jumpbyte
)
6796 /* This is a loop or jecxz type instruction. */
6798 if (i
.prefix
[ADDR_PREFIX
] != 0)
6800 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6803 /* Pentium4 branch hints. */
6804 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6805 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6807 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6816 if (flag_code
== CODE_16BIT
)
6819 if (i
.prefix
[DATA_PREFIX
] != 0)
6821 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6831 if (i
.prefix
[REX_PREFIX
] != 0)
6833 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6837 /* BND prefixed jump. */
6838 if (i
.prefix
[BND_PREFIX
] != 0)
6840 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6844 if (i
.prefixes
!= 0 && !intel_syntax
)
6845 as_warn (_("skipping prefixes on this instruction"));
6847 p
= frag_more (i
.tm
.opcode_length
+ size
);
6848 switch (i
.tm
.opcode_length
)
6851 *p
++ = i
.tm
.base_opcode
>> 8;
6853 *p
++ = i
.tm
.base_opcode
;
6859 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6860 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6862 /* All jumps handled here are signed, but don't use a signed limit
6863 check for 32 and 16 bit jumps as we want to allow wrap around at
6864 4G and 64k respectively. */
6866 fixP
->fx_signed
= 1;
6870 output_interseg_jump (void)
6878 if (flag_code
== CODE_16BIT
)
6882 if (i
.prefix
[DATA_PREFIX
] != 0)
6888 if (i
.prefix
[REX_PREFIX
] != 0)
6898 if (i
.prefixes
!= 0 && !intel_syntax
)
6899 as_warn (_("skipping prefixes on this instruction"));
6901 /* 1 opcode; 2 segment; offset */
6902 p
= frag_more (prefix
+ 1 + 2 + size
);
6904 if (i
.prefix
[DATA_PREFIX
] != 0)
6905 *p
++ = DATA_PREFIX_OPCODE
;
6907 if (i
.prefix
[REX_PREFIX
] != 0)
6908 *p
++ = i
.prefix
[REX_PREFIX
];
6910 *p
++ = i
.tm
.base_opcode
;
6911 if (i
.op
[1].imms
->X_op
== O_constant
)
6913 offsetT n
= i
.op
[1].imms
->X_add_number
;
6916 && !fits_in_unsigned_word (n
)
6917 && !fits_in_signed_word (n
))
6919 as_bad (_("16-bit jump out of range"));
6922 md_number_to_chars (p
, n
, size
);
6925 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6926 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6927 if (i
.op
[0].imms
->X_op
!= O_constant
)
6928 as_bad (_("can't handle non absolute segment in `%s'"),
6930 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6936 fragS
*insn_start_frag
;
6937 offsetT insn_start_off
;
6939 /* Tie dwarf2 debug info to the address at the start of the insn.
6940 We can't do this after the insn has been output as the current
6941 frag may have been closed off. eg. by frag_var. */
6942 dwarf2_emit_insn (0);
6944 insn_start_frag
= frag_now
;
6945 insn_start_off
= frag_now_fix ();
6948 if (i
.tm
.opcode_modifier
.jump
)
6950 else if (i
.tm
.opcode_modifier
.jumpbyte
6951 || i
.tm
.opcode_modifier
.jumpdword
)
6953 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6954 output_interseg_jump ();
6957 /* Output normal instructions here. */
6961 unsigned int prefix
;
6964 && i
.tm
.base_opcode
== 0xfae
6966 && i
.imm_operands
== 1
6967 && (i
.op
[0].imms
->X_add_number
== 0xe8
6968 || i
.op
[0].imms
->X_add_number
== 0xf0
6969 || i
.op
[0].imms
->X_add_number
== 0xf8))
6971 /* Encode lfence, mfence, and sfence as
6972 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
6973 offsetT val
= 0x240483f0ULL
;
6975 md_number_to_chars (p
, val
, 5);
6979 /* Some processors fail on LOCK prefix. This options makes
6980 assembler ignore LOCK prefix and serves as a workaround. */
6981 if (omit_lock_prefix
)
6983 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
6985 i
.prefix
[LOCK_PREFIX
] = 0;
6988 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6989 don't need the explicit prefix. */
6990 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6992 switch (i
.tm
.opcode_length
)
6995 if (i
.tm
.base_opcode
& 0xff000000)
6997 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7002 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7004 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7005 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7008 if (prefix
!= REPE_PREFIX_OPCODE
7009 || (i
.prefix
[REP_PREFIX
]
7010 != REPE_PREFIX_OPCODE
))
7011 add_prefix (prefix
);
7014 add_prefix (prefix
);
7023 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7024 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7025 R_X86_64_GOTTPOFF relocation so that linker can safely
7026 perform IE->LE optimization. */
7027 if (x86_elf_abi
== X86_64_X32_ABI
7029 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7030 && i
.prefix
[REX_PREFIX
] == 0)
7031 add_prefix (REX_OPCODE
);
7034 /* The prefix bytes. */
7035 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7037 FRAG_APPEND_1_CHAR (*q
);
7041 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7046 /* REX byte is encoded in VEX prefix. */
7050 FRAG_APPEND_1_CHAR (*q
);
7053 /* There should be no other prefixes for instructions
7058 /* For EVEX instructions i.vrex should become 0 after
7059 build_evex_prefix. For VEX instructions upper 16 registers
7060 aren't available, so VREX should be 0. */
7063 /* Now the VEX prefix. */
7064 p
= frag_more (i
.vex
.length
);
7065 for (j
= 0; j
< i
.vex
.length
; j
++)
7066 p
[j
] = i
.vex
.bytes
[j
];
7069 /* Now the opcode; be careful about word order here! */
7070 if (i
.tm
.opcode_length
== 1)
7072 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7076 switch (i
.tm
.opcode_length
)
7080 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7081 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7085 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7095 /* Put out high byte first: can't use md_number_to_chars! */
7096 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7097 *p
= i
.tm
.base_opcode
& 0xff;
7100 /* Now the modrm byte and sib byte (if present). */
7101 if (i
.tm
.opcode_modifier
.modrm
)
7103 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7106 /* If i.rm.regmem == ESP (4)
7107 && i.rm.mode != (Register mode)
7109 ==> need second modrm byte. */
7110 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7112 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7113 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7115 | i
.sib
.scale
<< 6));
7118 if (i
.disp_operands
)
7119 output_disp (insn_start_frag
, insn_start_off
);
7122 output_imm (insn_start_frag
, insn_start_off
);
7128 pi ("" /*line*/, &i
);
7130 #endif /* DEBUG386 */
7133 /* Return the size of the displacement operand N. */
7136 disp_size (unsigned int n
)
7140 /* Vec_Disp8 has to be 8bit. */
7141 if (i
.types
[n
].bitfield
.vec_disp8
)
7143 else if (i
.types
[n
].bitfield
.disp64
)
7145 else if (i
.types
[n
].bitfield
.disp8
)
7147 else if (i
.types
[n
].bitfield
.disp16
)
7152 /* Return the size of the immediate operand N. */
7155 imm_size (unsigned int n
)
7158 if (i
.types
[n
].bitfield
.imm64
)
7160 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7162 else if (i
.types
[n
].bitfield
.imm16
)
7168 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7173 for (n
= 0; n
< i
.operands
; n
++)
7175 if (i
.types
[n
].bitfield
.vec_disp8
7176 || operand_type_check (i
.types
[n
], disp
))
7178 if (i
.op
[n
].disps
->X_op
== O_constant
)
7180 int size
= disp_size (n
);
7181 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7183 if (i
.types
[n
].bitfield
.vec_disp8
)
7185 val
= offset_in_range (val
, size
);
7186 p
= frag_more (size
);
7187 md_number_to_chars (p
, val
, size
);
7191 enum bfd_reloc_code_real reloc_type
;
7192 int size
= disp_size (n
);
7193 int sign
= i
.types
[n
].bitfield
.disp32s
;
7194 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7197 /* We can't have 8 bit displacement here. */
7198 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7200 /* The PC relative address is computed relative
7201 to the instruction boundary, so in case immediate
7202 fields follows, we need to adjust the value. */
7203 if (pcrel
&& i
.imm_operands
)
7208 for (n1
= 0; n1
< i
.operands
; n1
++)
7209 if (operand_type_check (i
.types
[n1
], imm
))
7211 /* Only one immediate is allowed for PC
7212 relative address. */
7213 gas_assert (sz
== 0);
7215 i
.op
[n
].disps
->X_add_number
-= sz
;
7217 /* We should find the immediate. */
7218 gas_assert (sz
!= 0);
7221 p
= frag_more (size
);
7222 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7224 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7225 && (((reloc_type
== BFD_RELOC_32
7226 || reloc_type
== BFD_RELOC_X86_64_32S
7227 || (reloc_type
== BFD_RELOC_64
7229 && (i
.op
[n
].disps
->X_op
== O_symbol
7230 || (i
.op
[n
].disps
->X_op
== O_add
7231 && ((symbol_get_value_expression
7232 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7234 || reloc_type
== BFD_RELOC_32_PCREL
))
7238 if (insn_start_frag
== frag_now
)
7239 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7244 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7245 for (fr
= insn_start_frag
->fr_next
;
7246 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7248 add
+= p
- frag_now
->fr_literal
;
7253 reloc_type
= BFD_RELOC_386_GOTPC
;
7254 i
.op
[n
].imms
->X_add_number
+= add
;
7256 else if (reloc_type
== BFD_RELOC_64
)
7257 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7259 /* Don't do the adjustment for x86-64, as there
7260 the pcrel addressing is relative to the _next_
7261 insn, and that is taken care of in other code. */
7262 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7264 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7265 size
, i
.op
[n
].disps
, pcrel
,
7267 /* Check for "call/jmp *mem", "mov mem, %reg",
7268 "test %reg, mem" and "binop mem, %reg" where binop
7269 is one of adc, add, and, cmp, or, sbb, sub, xor
7272 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7273 && ((i
.operands
== 1
7274 && i
.tm
.base_opcode
== 0xff
7275 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7277 && (i
.tm
.base_opcode
== 0x8b
7278 || i
.tm
.base_opcode
== 0x85
7279 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7283 fixP
->fx_tcbit
= i
.rex
!= 0;
7285 && (i
.base_reg
->reg_num
== RegRip
7286 || i
.base_reg
->reg_num
== RegEip
))
7287 fixP
->fx_tcbit2
= 1;
7290 fixP
->fx_tcbit2
= 1;
7298 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7303 for (n
= 0; n
< i
.operands
; n
++)
7305 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7306 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7309 if (operand_type_check (i
.types
[n
], imm
))
7311 if (i
.op
[n
].imms
->X_op
== O_constant
)
7313 int size
= imm_size (n
);
7316 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7318 p
= frag_more (size
);
7319 md_number_to_chars (p
, val
, size
);
7323 /* Not absolute_section.
7324 Need a 32-bit fixup (don't support 8bit
7325 non-absolute imms). Try to support other
7327 enum bfd_reloc_code_real reloc_type
;
7328 int size
= imm_size (n
);
7331 if (i
.types
[n
].bitfield
.imm32s
7332 && (i
.suffix
== QWORD_MNEM_SUFFIX
7333 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7338 p
= frag_more (size
);
7339 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7341 /* This is tough to explain. We end up with this one if we
7342 * have operands that look like
7343 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7344 * obtain the absolute address of the GOT, and it is strongly
7345 * preferable from a performance point of view to avoid using
7346 * a runtime relocation for this. The actual sequence of
7347 * instructions often look something like:
7352 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7354 * The call and pop essentially return the absolute address
7355 * of the label .L66 and store it in %ebx. The linker itself
7356 * will ultimately change the first operand of the addl so
7357 * that %ebx points to the GOT, but to keep things simple, the
7358 * .o file must have this operand set so that it generates not
7359 * the absolute address of .L66, but the absolute address of
7360 * itself. This allows the linker itself simply treat a GOTPC
7361 * relocation as asking for a pcrel offset to the GOT to be
7362 * added in, and the addend of the relocation is stored in the
7363 * operand field for the instruction itself.
7365 * Our job here is to fix the operand so that it would add
7366 * the correct offset so that %ebx would point to itself. The
7367 * thing that is tricky is that .-.L66 will point to the
7368 * beginning of the instruction, so we need to further modify
7369 * the operand so that it will point to itself. There are
7370 * other cases where you have something like:
7372 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7374 * and here no correction would be required. Internally in
7375 * the assembler we treat operands of this form as not being
7376 * pcrel since the '.' is explicitly mentioned, and I wonder
7377 * whether it would simplify matters to do it this way. Who
7378 * knows. In earlier versions of the PIC patches, the
7379 * pcrel_adjust field was used to store the correction, but
7380 * since the expression is not pcrel, I felt it would be
7381 * confusing to do it this way. */
7383 if ((reloc_type
== BFD_RELOC_32
7384 || reloc_type
== BFD_RELOC_X86_64_32S
7385 || reloc_type
== BFD_RELOC_64
)
7387 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7388 && (i
.op
[n
].imms
->X_op
== O_symbol
7389 || (i
.op
[n
].imms
->X_op
== O_add
7390 && ((symbol_get_value_expression
7391 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7396 if (insn_start_frag
== frag_now
)
7397 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7402 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7403 for (fr
= insn_start_frag
->fr_next
;
7404 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7406 add
+= p
- frag_now
->fr_literal
;
7410 reloc_type
= BFD_RELOC_386_GOTPC
;
7412 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7414 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7415 i
.op
[n
].imms
->X_add_number
+= add
;
7417 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7418 i
.op
[n
].imms
, 0, reloc_type
);
7424 /* x86_cons_fix_new is called via the expression parsing code when a
7425 reloc is needed. We use this hook to get the correct .got reloc. */
7426 static int cons_sign
= -1;
7429 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7430 expressionS
*exp
, bfd_reloc_code_real_type r
)
7432 r
= reloc (len
, 0, cons_sign
, r
);
7435 if (exp
->X_op
== O_secrel
)
7437 exp
->X_op
= O_symbol
;
7438 r
= BFD_RELOC_32_SECREL
;
7442 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7445 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7446 purpose of the `.dc.a' internal pseudo-op. */
7449 x86_address_bytes (void)
7451 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7453 return stdoutput
->arch_info
->bits_per_address
/ 8;
7456 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7458 # define lex_got(reloc, adjust, types) NULL
7460 /* Parse operands of the form
7461 <symbol>@GOTOFF+<nnn>
7462 and similar .plt or .got references.
7464 If we find one, set up the correct relocation in RELOC and copy the
7465 input string, minus the `@GOTOFF' into a malloc'd buffer for
7466 parsing by the calling routine. Return this buffer, and if ADJUST
7467 is non-null set it to the length of the string we removed from the
7468 input line. Otherwise return NULL. */
7470 lex_got (enum bfd_reloc_code_real
*rel
,
7472 i386_operand_type
*types
)
7474 /* Some of the relocations depend on the size of what field is to
7475 be relocated. But in our callers i386_immediate and i386_displacement
7476 we don't yet know the operand size (this will be set by insn
7477 matching). Hence we record the word32 relocation here,
7478 and adjust the reloc according to the real size in reloc(). */
7479 static const struct {
7482 const enum bfd_reloc_code_real rel
[2];
7483 const i386_operand_type types64
;
7485 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7486 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7488 OPERAND_TYPE_IMM32_64
},
7490 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7491 BFD_RELOC_X86_64_PLTOFF64
},
7492 OPERAND_TYPE_IMM64
},
7493 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7494 BFD_RELOC_X86_64_PLT32
},
7495 OPERAND_TYPE_IMM32_32S_DISP32
},
7496 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7497 BFD_RELOC_X86_64_GOTPLT64
},
7498 OPERAND_TYPE_IMM64_DISP64
},
7499 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7500 BFD_RELOC_X86_64_GOTOFF64
},
7501 OPERAND_TYPE_IMM64_DISP64
},
7502 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7503 BFD_RELOC_X86_64_GOTPCREL
},
7504 OPERAND_TYPE_IMM32_32S_DISP32
},
7505 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7506 BFD_RELOC_X86_64_TLSGD
},
7507 OPERAND_TYPE_IMM32_32S_DISP32
},
7508 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7509 _dummy_first_bfd_reloc_code_real
},
7510 OPERAND_TYPE_NONE
},
7511 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7512 BFD_RELOC_X86_64_TLSLD
},
7513 OPERAND_TYPE_IMM32_32S_DISP32
},
7514 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7515 BFD_RELOC_X86_64_GOTTPOFF
},
7516 OPERAND_TYPE_IMM32_32S_DISP32
},
7517 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7518 BFD_RELOC_X86_64_TPOFF32
},
7519 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7520 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7521 _dummy_first_bfd_reloc_code_real
},
7522 OPERAND_TYPE_NONE
},
7523 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7524 BFD_RELOC_X86_64_DTPOFF32
},
7525 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7526 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7527 _dummy_first_bfd_reloc_code_real
},
7528 OPERAND_TYPE_NONE
},
7529 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7530 _dummy_first_bfd_reloc_code_real
},
7531 OPERAND_TYPE_NONE
},
7532 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7533 BFD_RELOC_X86_64_GOT32
},
7534 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7535 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7536 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7537 OPERAND_TYPE_IMM32_32S_DISP32
},
7538 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7539 BFD_RELOC_X86_64_TLSDESC_CALL
},
7540 OPERAND_TYPE_IMM32_32S_DISP32
},
7545 #if defined (OBJ_MAYBE_ELF)
7550 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7551 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7554 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7556 int len
= gotrel
[j
].len
;
7557 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7559 if (gotrel
[j
].rel
[object_64bit
] != 0)
7562 char *tmpbuf
, *past_reloc
;
7564 *rel
= gotrel
[j
].rel
[object_64bit
];
7568 if (flag_code
!= CODE_64BIT
)
7570 types
->bitfield
.imm32
= 1;
7571 types
->bitfield
.disp32
= 1;
7574 *types
= gotrel
[j
].types64
;
7577 if (j
!= 0 && GOT_symbol
== NULL
)
7578 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7580 /* The length of the first part of our input line. */
7581 first
= cp
- input_line_pointer
;
7583 /* The second part goes from after the reloc token until
7584 (and including) an end_of_line char or comma. */
7585 past_reloc
= cp
+ 1 + len
;
7587 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7589 second
= cp
+ 1 - past_reloc
;
7591 /* Allocate and copy string. The trailing NUL shouldn't
7592 be necessary, but be safe. */
7593 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7594 memcpy (tmpbuf
, input_line_pointer
, first
);
7595 if (second
!= 0 && *past_reloc
!= ' ')
7596 /* Replace the relocation token with ' ', so that
7597 errors like foo@GOTOFF1 will be detected. */
7598 tmpbuf
[first
++] = ' ';
7600 /* Increment length by 1 if the relocation token is
7605 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7606 tmpbuf
[first
+ second
] = '\0';
7610 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7611 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7616 /* Might be a symbol version string. Don't as_bad here. */
7625 /* Parse operands of the form
7626 <symbol>@SECREL32+<nnn>
7628 If we find one, set up the correct relocation in RELOC and copy the
7629 input string, minus the `@SECREL32' into a malloc'd buffer for
7630 parsing by the calling routine. Return this buffer, and if ADJUST
7631 is non-null set it to the length of the string we removed from the
7632 input line. Otherwise return NULL.
7634 This function is copied from the ELF version above adjusted for PE targets. */
7637 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7638 int *adjust ATTRIBUTE_UNUSED
,
7639 i386_operand_type
*types
)
7645 const enum bfd_reloc_code_real rel
[2];
7646 const i386_operand_type types64
;
7650 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7651 BFD_RELOC_32_SECREL
},
7652 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7658 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7659 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7662 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7664 int len
= gotrel
[j
].len
;
7666 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7668 if (gotrel
[j
].rel
[object_64bit
] != 0)
7671 char *tmpbuf
, *past_reloc
;
7673 *rel
= gotrel
[j
].rel
[object_64bit
];
7679 if (flag_code
!= CODE_64BIT
)
7681 types
->bitfield
.imm32
= 1;
7682 types
->bitfield
.disp32
= 1;
7685 *types
= gotrel
[j
].types64
;
7688 /* The length of the first part of our input line. */
7689 first
= cp
- input_line_pointer
;
7691 /* The second part goes from after the reloc token until
7692 (and including) an end_of_line char or comma. */
7693 past_reloc
= cp
+ 1 + len
;
7695 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7697 second
= cp
+ 1 - past_reloc
;
7699 /* Allocate and copy string. The trailing NUL shouldn't
7700 be necessary, but be safe. */
7701 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7702 memcpy (tmpbuf
, input_line_pointer
, first
);
7703 if (second
!= 0 && *past_reloc
!= ' ')
7704 /* Replace the relocation token with ' ', so that
7705 errors like foo@SECLREL321 will be detected. */
7706 tmpbuf
[first
++] = ' ';
7707 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7708 tmpbuf
[first
+ second
] = '\0';
7712 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7713 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7718 /* Might be a symbol version string. Don't as_bad here. */
7724 bfd_reloc_code_real_type
7725 x86_cons (expressionS
*exp
, int size
)
7727 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7729 intel_syntax
= -intel_syntax
;
7732 if (size
== 4 || (object_64bit
&& size
== 8))
7734 /* Handle @GOTOFF and the like in an expression. */
7736 char *gotfree_input_line
;
7739 save
= input_line_pointer
;
7740 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7741 if (gotfree_input_line
)
7742 input_line_pointer
= gotfree_input_line
;
7746 if (gotfree_input_line
)
7748 /* expression () has merrily parsed up to the end of line,
7749 or a comma - in the wrong buffer. Transfer how far
7750 input_line_pointer has moved to the right buffer. */
7751 input_line_pointer
= (save
7752 + (input_line_pointer
- gotfree_input_line
)
7754 free (gotfree_input_line
);
7755 if (exp
->X_op
== O_constant
7756 || exp
->X_op
== O_absent
7757 || exp
->X_op
== O_illegal
7758 || exp
->X_op
== O_register
7759 || exp
->X_op
== O_big
)
7761 char c
= *input_line_pointer
;
7762 *input_line_pointer
= 0;
7763 as_bad (_("missing or invalid expression `%s'"), save
);
7764 *input_line_pointer
= c
;
7771 intel_syntax
= -intel_syntax
;
7774 i386_intel_simplify (exp
);
7780 signed_cons (int size
)
7782 if (flag_code
== CODE_64BIT
)
7790 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7797 if (exp
.X_op
== O_symbol
)
7798 exp
.X_op
= O_secrel
;
7800 emit_expr (&exp
, 4);
7802 while (*input_line_pointer
++ == ',');
7804 input_line_pointer
--;
7805 demand_empty_rest_of_line ();
7809 /* Handle Vector operations. */
7812 check_VecOperations (char *op_string
, char *op_end
)
7814 const reg_entry
*mask
;
7819 && (op_end
== NULL
|| op_string
< op_end
))
7822 if (*op_string
== '{')
7826 /* Check broadcasts. */
7827 if (strncmp (op_string
, "1to", 3) == 0)
7832 goto duplicated_vec_op
;
7835 if (*op_string
== '8')
7836 bcst_type
= BROADCAST_1TO8
;
7837 else if (*op_string
== '4')
7838 bcst_type
= BROADCAST_1TO4
;
7839 else if (*op_string
== '2')
7840 bcst_type
= BROADCAST_1TO2
;
7841 else if (*op_string
== '1'
7842 && *(op_string
+1) == '6')
7844 bcst_type
= BROADCAST_1TO16
;
7849 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7854 broadcast_op
.type
= bcst_type
;
7855 broadcast_op
.operand
= this_operand
;
7856 i
.broadcast
= &broadcast_op
;
7858 /* Check masking operation. */
7859 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7861 /* k0 can't be used for write mask. */
7862 if (mask
->reg_num
== 0)
7864 as_bad (_("`%s' can't be used for write mask"),
7871 mask_op
.mask
= mask
;
7872 mask_op
.zeroing
= 0;
7873 mask_op
.operand
= this_operand
;
7879 goto duplicated_vec_op
;
7881 i
.mask
->mask
= mask
;
7883 /* Only "{z}" is allowed here. No need to check
7884 zeroing mask explicitly. */
7885 if (i
.mask
->operand
!= this_operand
)
7887 as_bad (_("invalid write mask `%s'"), saved
);
7894 /* Check zeroing-flag for masking operation. */
7895 else if (*op_string
== 'z')
7899 mask_op
.mask
= NULL
;
7900 mask_op
.zeroing
= 1;
7901 mask_op
.operand
= this_operand
;
7906 if (i
.mask
->zeroing
)
7909 as_bad (_("duplicated `%s'"), saved
);
7913 i
.mask
->zeroing
= 1;
7915 /* Only "{%k}" is allowed here. No need to check mask
7916 register explicitly. */
7917 if (i
.mask
->operand
!= this_operand
)
7919 as_bad (_("invalid zeroing-masking `%s'"),
7928 goto unknown_vec_op
;
7930 if (*op_string
!= '}')
7932 as_bad (_("missing `}' in `%s'"), saved
);
7939 /* We don't know this one. */
7940 as_bad (_("unknown vector operation: `%s'"), saved
);
7948 i386_immediate (char *imm_start
)
7950 char *save_input_line_pointer
;
7951 char *gotfree_input_line
;
7954 i386_operand_type types
;
7956 operand_type_set (&types
, ~0);
7958 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7960 as_bad (_("at most %d immediate operands are allowed"),
7961 MAX_IMMEDIATE_OPERANDS
);
7965 exp
= &im_expressions
[i
.imm_operands
++];
7966 i
.op
[this_operand
].imms
= exp
;
7968 if (is_space_char (*imm_start
))
7971 save_input_line_pointer
= input_line_pointer
;
7972 input_line_pointer
= imm_start
;
7974 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7975 if (gotfree_input_line
)
7976 input_line_pointer
= gotfree_input_line
;
7978 exp_seg
= expression (exp
);
7982 /* Handle vector operations. */
7983 if (*input_line_pointer
== '{')
7985 input_line_pointer
= check_VecOperations (input_line_pointer
,
7987 if (input_line_pointer
== NULL
)
7991 if (*input_line_pointer
)
7992 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7994 input_line_pointer
= save_input_line_pointer
;
7995 if (gotfree_input_line
)
7997 free (gotfree_input_line
);
7999 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8000 exp
->X_op
= O_illegal
;
8003 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8007 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8008 i386_operand_type types
, const char *imm_start
)
8010 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8013 as_bad (_("missing or invalid immediate expression `%s'"),
8017 else if (exp
->X_op
== O_constant
)
8019 /* Size it properly later. */
8020 i
.types
[this_operand
].bitfield
.imm64
= 1;
8021 /* If not 64bit, sign extend val. */
8022 if (flag_code
!= CODE_64BIT
8023 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8025 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8027 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8028 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8029 && exp_seg
!= absolute_section
8030 && exp_seg
!= text_section
8031 && exp_seg
!= data_section
8032 && exp_seg
!= bss_section
8033 && exp_seg
!= undefined_section
8034 && !bfd_is_com_section (exp_seg
))
8036 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8040 else if (!intel_syntax
&& exp_seg
== reg_section
)
8043 as_bad (_("illegal immediate register operand %s"), imm_start
);
8048 /* This is an address. The size of the address will be
8049 determined later, depending on destination register,
8050 suffix, or the default for the section. */
8051 i
.types
[this_operand
].bitfield
.imm8
= 1;
8052 i
.types
[this_operand
].bitfield
.imm16
= 1;
8053 i
.types
[this_operand
].bitfield
.imm32
= 1;
8054 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8055 i
.types
[this_operand
].bitfield
.imm64
= 1;
8056 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8064 i386_scale (char *scale
)
8067 char *save
= input_line_pointer
;
8069 input_line_pointer
= scale
;
8070 val
= get_absolute_expression ();
8075 i
.log2_scale_factor
= 0;
8078 i
.log2_scale_factor
= 1;
8081 i
.log2_scale_factor
= 2;
8084 i
.log2_scale_factor
= 3;
8088 char sep
= *input_line_pointer
;
8090 *input_line_pointer
= '\0';
8091 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8093 *input_line_pointer
= sep
;
8094 input_line_pointer
= save
;
8098 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8100 as_warn (_("scale factor of %d without an index register"),
8101 1 << i
.log2_scale_factor
);
8102 i
.log2_scale_factor
= 0;
8104 scale
= input_line_pointer
;
8105 input_line_pointer
= save
;
8110 i386_displacement (char *disp_start
, char *disp_end
)
8114 char *save_input_line_pointer
;
8115 char *gotfree_input_line
;
8117 i386_operand_type bigdisp
, types
= anydisp
;
8120 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8122 as_bad (_("at most %d displacement operands are allowed"),
8123 MAX_MEMORY_OPERANDS
);
8127 operand_type_set (&bigdisp
, 0);
8128 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8129 || (!current_templates
->start
->opcode_modifier
.jump
8130 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8132 bigdisp
.bitfield
.disp32
= 1;
8133 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8134 if (flag_code
== CODE_64BIT
)
8138 bigdisp
.bitfield
.disp32s
= 1;
8139 bigdisp
.bitfield
.disp64
= 1;
8142 else if ((flag_code
== CODE_16BIT
) ^ override
)
8144 bigdisp
.bitfield
.disp32
= 0;
8145 bigdisp
.bitfield
.disp16
= 1;
8150 /* For PC-relative branches, the width of the displacement
8151 is dependent upon data size, not address size. */
8152 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8153 if (flag_code
== CODE_64BIT
)
8155 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8156 bigdisp
.bitfield
.disp16
= 1;
8159 bigdisp
.bitfield
.disp32
= 1;
8160 bigdisp
.bitfield
.disp32s
= 1;
8166 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8168 : LONG_MNEM_SUFFIX
));
8169 bigdisp
.bitfield
.disp32
= 1;
8170 if ((flag_code
== CODE_16BIT
) ^ override
)
8172 bigdisp
.bitfield
.disp32
= 0;
8173 bigdisp
.bitfield
.disp16
= 1;
8177 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8180 exp
= &disp_expressions
[i
.disp_operands
];
8181 i
.op
[this_operand
].disps
= exp
;
8183 save_input_line_pointer
= input_line_pointer
;
8184 input_line_pointer
= disp_start
;
8185 END_STRING_AND_SAVE (disp_end
);
8187 #ifndef GCC_ASM_O_HACK
8188 #define GCC_ASM_O_HACK 0
8191 END_STRING_AND_SAVE (disp_end
+ 1);
8192 if (i
.types
[this_operand
].bitfield
.baseIndex
8193 && displacement_string_end
[-1] == '+')
8195 /* This hack is to avoid a warning when using the "o"
8196 constraint within gcc asm statements.
8199 #define _set_tssldt_desc(n,addr,limit,type) \
8200 __asm__ __volatile__ ( \
8202 "movw %w1,2+%0\n\t" \
8204 "movb %b1,4+%0\n\t" \
8205 "movb %4,5+%0\n\t" \
8206 "movb $0,6+%0\n\t" \
8207 "movb %h1,7+%0\n\t" \
8209 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8211 This works great except that the output assembler ends
8212 up looking a bit weird if it turns out that there is
8213 no offset. You end up producing code that looks like:
8226 So here we provide the missing zero. */
8228 *displacement_string_end
= '0';
8231 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8232 if (gotfree_input_line
)
8233 input_line_pointer
= gotfree_input_line
;
8235 exp_seg
= expression (exp
);
8238 if (*input_line_pointer
)
8239 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8241 RESTORE_END_STRING (disp_end
+ 1);
8243 input_line_pointer
= save_input_line_pointer
;
8244 if (gotfree_input_line
)
8246 free (gotfree_input_line
);
8248 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8249 exp
->X_op
= O_illegal
;
8252 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8254 RESTORE_END_STRING (disp_end
);
8260 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8261 i386_operand_type types
, const char *disp_start
)
8263 i386_operand_type bigdisp
;
8266 /* We do this to make sure that the section symbol is in
8267 the symbol table. We will ultimately change the relocation
8268 to be relative to the beginning of the section. */
8269 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8270 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8271 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8273 if (exp
->X_op
!= O_symbol
)
8276 if (S_IS_LOCAL (exp
->X_add_symbol
)
8277 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8278 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8279 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8280 exp
->X_op
= O_subtract
;
8281 exp
->X_op_symbol
= GOT_symbol
;
8282 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8283 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8284 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8285 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8287 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8290 else if (exp
->X_op
== O_absent
8291 || exp
->X_op
== O_illegal
8292 || exp
->X_op
== O_big
)
8295 as_bad (_("missing or invalid displacement expression `%s'"),
8300 else if (flag_code
== CODE_64BIT
8301 && !i
.prefix
[ADDR_PREFIX
]
8302 && exp
->X_op
== O_constant
)
8304 /* Since displacement is signed extended to 64bit, don't allow
8305 disp32 and turn off disp32s if they are out of range. */
8306 i
.types
[this_operand
].bitfield
.disp32
= 0;
8307 if (!fits_in_signed_long (exp
->X_add_number
))
8309 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8310 if (i
.types
[this_operand
].bitfield
.baseindex
)
8312 as_bad (_("0x%lx out range of signed 32bit displacement"),
8313 (long) exp
->X_add_number
);
8319 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8320 else if (exp
->X_op
!= O_constant
8321 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8322 && exp_seg
!= absolute_section
8323 && exp_seg
!= text_section
8324 && exp_seg
!= data_section
8325 && exp_seg
!= bss_section
8326 && exp_seg
!= undefined_section
8327 && !bfd_is_com_section (exp_seg
))
8329 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8334 /* Check if this is a displacement only operand. */
8335 bigdisp
= i
.types
[this_operand
];
8336 bigdisp
.bitfield
.disp8
= 0;
8337 bigdisp
.bitfield
.disp16
= 0;
8338 bigdisp
.bitfield
.disp32
= 0;
8339 bigdisp
.bitfield
.disp32s
= 0;
8340 bigdisp
.bitfield
.disp64
= 0;
8341 if (operand_type_all_zero (&bigdisp
))
8342 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8348 /* Make sure the memory operand we've been dealt is valid.
8349 Return 1 on success, 0 on a failure. */
8352 i386_index_check (const char *operand_string
)
8354 const char *kind
= "base/index";
8355 enum flag_code addr_mode
;
8357 if (i
.prefix
[ADDR_PREFIX
])
8358 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8361 addr_mode
= flag_code
;
8363 #if INFER_ADDR_PREFIX
8364 if (i
.mem_operands
== 0)
8366 /* Infer address prefix from the first memory operand. */
8367 const reg_entry
*addr_reg
= i
.base_reg
;
8369 if (addr_reg
== NULL
)
8370 addr_reg
= i
.index_reg
;
8374 if (addr_reg
->reg_num
== RegEip
8375 || addr_reg
->reg_num
== RegEiz
8376 || addr_reg
->reg_type
.bitfield
.reg32
)
8377 addr_mode
= CODE_32BIT
;
8378 else if (flag_code
!= CODE_64BIT
8379 && addr_reg
->reg_type
.bitfield
.reg16
)
8380 addr_mode
= CODE_16BIT
;
8382 if (addr_mode
!= flag_code
)
8384 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8386 /* Change the size of any displacement too. At most one
8387 of Disp16 or Disp32 is set.
8388 FIXME. There doesn't seem to be any real need for
8389 separate Disp16 and Disp32 flags. The same goes for
8390 Imm16 and Imm32. Removing them would probably clean
8391 up the code quite a lot. */
8392 if (flag_code
!= CODE_64BIT
8393 && (i
.types
[this_operand
].bitfield
.disp16
8394 || i
.types
[this_operand
].bitfield
.disp32
))
8395 i
.types
[this_operand
]
8396 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8403 if (current_templates
->start
->opcode_modifier
.isstring
8404 && !current_templates
->start
->opcode_modifier
.immext
8405 && (current_templates
->end
[-1].opcode_modifier
.isstring
8408 /* Memory operands of string insns are special in that they only allow
8409 a single register (rDI, rSI, or rBX) as their memory address. */
8410 const reg_entry
*expected_reg
;
8411 static const char *di_si
[][2] =
8417 static const char *bx
[] = { "ebx", "bx", "rbx" };
8419 kind
= "string address";
8421 if (current_templates
->start
->opcode_modifier
.w
)
8423 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8425 if (!type
.bitfield
.baseindex
8426 || ((!i
.mem_operands
!= !intel_syntax
)
8427 && current_templates
->end
[-1].operand_types
[1]
8428 .bitfield
.baseindex
))
8429 type
= current_templates
->end
[-1].operand_types
[1];
8430 expected_reg
= hash_find (reg_hash
,
8431 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8435 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8437 if (i
.base_reg
!= expected_reg
8439 || operand_type_check (i
.types
[this_operand
], disp
))
8441 /* The second memory operand must have the same size as
8445 && !((addr_mode
== CODE_64BIT
8446 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8447 || (addr_mode
== CODE_32BIT
8448 ? i
.base_reg
->reg_type
.bitfield
.reg32
8449 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8452 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8454 intel_syntax
? '[' : '(',
8456 expected_reg
->reg_name
,
8457 intel_syntax
? ']' : ')');
8464 as_bad (_("`%s' is not a valid %s expression"),
8465 operand_string
, kind
);
8470 if (addr_mode
!= CODE_16BIT
)
8472 /* 32-bit/64-bit checks. */
8474 && (addr_mode
== CODE_64BIT
8475 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8476 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8478 || (i
.base_reg
->reg_num
8479 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8481 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8482 && !i
.index_reg
->reg_type
.bitfield
.regymm
8483 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8484 && ((addr_mode
== CODE_64BIT
8485 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8486 || i
.index_reg
->reg_num
== RegRiz
)
8487 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8488 || i
.index_reg
->reg_num
== RegEiz
))
8489 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8494 /* 16-bit checks. */
8496 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8497 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8499 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8500 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8502 && i
.base_reg
->reg_num
< 6
8503 && i
.index_reg
->reg_num
>= 6
8504 && i
.log2_scale_factor
== 0))))
8511 /* Handle vector immediates. */
8514 RC_SAE_immediate (const char *imm_start
)
8516 unsigned int match_found
, j
;
8517 const char *pstr
= imm_start
;
8525 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8527 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8531 rc_op
.type
= RC_NamesTable
[j
].type
;
8532 rc_op
.operand
= this_operand
;
8533 i
.rounding
= &rc_op
;
8537 as_bad (_("duplicated `%s'"), imm_start
);
8540 pstr
+= RC_NamesTable
[j
].len
;
8550 as_bad (_("Missing '}': '%s'"), imm_start
);
8553 /* RC/SAE immediate string should contain nothing more. */;
8556 as_bad (_("Junk after '}': '%s'"), imm_start
);
8560 exp
= &im_expressions
[i
.imm_operands
++];
8561 i
.op
[this_operand
].imms
= exp
;
8563 exp
->X_op
= O_constant
;
8564 exp
->X_add_number
= 0;
8565 exp
->X_add_symbol
= (symbolS
*) 0;
8566 exp
->X_op_symbol
= (symbolS
*) 0;
8568 i
.types
[this_operand
].bitfield
.imm8
= 1;
8572 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8576 i386_att_operand (char *operand_string
)
8580 char *op_string
= operand_string
;
8582 if (is_space_char (*op_string
))
8585 /* We check for an absolute prefix (differentiating,
8586 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8587 if (*op_string
== ABSOLUTE_PREFIX
)
8590 if (is_space_char (*op_string
))
8592 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8595 /* Check if operand is a register. */
8596 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8598 i386_operand_type temp
;
8600 /* Check for a segment override by searching for ':' after a
8601 segment register. */
8603 if (is_space_char (*op_string
))
8605 if (*op_string
== ':'
8606 && (r
->reg_type
.bitfield
.sreg2
8607 || r
->reg_type
.bitfield
.sreg3
))
8612 i
.seg
[i
.mem_operands
] = &es
;
8615 i
.seg
[i
.mem_operands
] = &cs
;
8618 i
.seg
[i
.mem_operands
] = &ss
;
8621 i
.seg
[i
.mem_operands
] = &ds
;
8624 i
.seg
[i
.mem_operands
] = &fs
;
8627 i
.seg
[i
.mem_operands
] = &gs
;
8631 /* Skip the ':' and whitespace. */
8633 if (is_space_char (*op_string
))
8636 if (!is_digit_char (*op_string
)
8637 && !is_identifier_char (*op_string
)
8638 && *op_string
!= '('
8639 && *op_string
!= ABSOLUTE_PREFIX
)
8641 as_bad (_("bad memory operand `%s'"), op_string
);
8644 /* Handle case of %es:*foo. */
8645 if (*op_string
== ABSOLUTE_PREFIX
)
8648 if (is_space_char (*op_string
))
8650 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8652 goto do_memory_reference
;
8655 /* Handle vector operations. */
8656 if (*op_string
== '{')
8658 op_string
= check_VecOperations (op_string
, NULL
);
8659 if (op_string
== NULL
)
8665 as_bad (_("junk `%s' after register"), op_string
);
8669 temp
.bitfield
.baseindex
= 0;
8670 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8672 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8673 i
.op
[this_operand
].regs
= r
;
8676 else if (*op_string
== REGISTER_PREFIX
)
8678 as_bad (_("bad register name `%s'"), op_string
);
8681 else if (*op_string
== IMMEDIATE_PREFIX
)
8684 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8686 as_bad (_("immediate operand illegal with absolute jump"));
8689 if (!i386_immediate (op_string
))
8692 else if (RC_SAE_immediate (operand_string
))
8694 /* If it is a RC or SAE immediate, do nothing. */
8697 else if (is_digit_char (*op_string
)
8698 || is_identifier_char (*op_string
)
8699 || *op_string
== '"'
8700 || *op_string
== '(')
8702 /* This is a memory reference of some sort. */
8705 /* Start and end of displacement string expression (if found). */
8706 char *displacement_string_start
;
8707 char *displacement_string_end
;
8710 do_memory_reference
:
8711 if ((i
.mem_operands
== 1
8712 && !current_templates
->start
->opcode_modifier
.isstring
)
8713 || i
.mem_operands
== 2)
8715 as_bad (_("too many memory references for `%s'"),
8716 current_templates
->start
->name
);
8720 /* Check for base index form. We detect the base index form by
8721 looking for an ')' at the end of the operand, searching
8722 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8724 base_string
= op_string
+ strlen (op_string
);
8726 /* Handle vector operations. */
8727 vop_start
= strchr (op_string
, '{');
8728 if (vop_start
&& vop_start
< base_string
)
8730 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8732 base_string
= vop_start
;
8736 if (is_space_char (*base_string
))
8739 /* If we only have a displacement, set-up for it to be parsed later. */
8740 displacement_string_start
= op_string
;
8741 displacement_string_end
= base_string
+ 1;
8743 if (*base_string
== ')')
8746 unsigned int parens_balanced
= 1;
8747 /* We've already checked that the number of left & right ()'s are
8748 equal, so this loop will not be infinite. */
8752 if (*base_string
== ')')
8754 if (*base_string
== '(')
8757 while (parens_balanced
);
8759 temp_string
= base_string
;
8761 /* Skip past '(' and whitespace. */
8763 if (is_space_char (*base_string
))
8766 if (*base_string
== ','
8767 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8770 displacement_string_end
= temp_string
;
8772 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8776 base_string
= end_op
;
8777 if (is_space_char (*base_string
))
8781 /* There may be an index reg or scale factor here. */
8782 if (*base_string
== ',')
8785 if (is_space_char (*base_string
))
8788 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8791 base_string
= end_op
;
8792 if (is_space_char (*base_string
))
8794 if (*base_string
== ',')
8797 if (is_space_char (*base_string
))
8800 else if (*base_string
!= ')')
8802 as_bad (_("expecting `,' or `)' "
8803 "after index register in `%s'"),
8808 else if (*base_string
== REGISTER_PREFIX
)
8810 end_op
= strchr (base_string
, ',');
8813 as_bad (_("bad register name `%s'"), base_string
);
8817 /* Check for scale factor. */
8818 if (*base_string
!= ')')
8820 char *end_scale
= i386_scale (base_string
);
8825 base_string
= end_scale
;
8826 if (is_space_char (*base_string
))
8828 if (*base_string
!= ')')
8830 as_bad (_("expecting `)' "
8831 "after scale factor in `%s'"),
8836 else if (!i
.index_reg
)
8838 as_bad (_("expecting index register or scale factor "
8839 "after `,'; got '%c'"),
8844 else if (*base_string
!= ')')
8846 as_bad (_("expecting `,' or `)' "
8847 "after base register in `%s'"),
8852 else if (*base_string
== REGISTER_PREFIX
)
8854 end_op
= strchr (base_string
, ',');
8857 as_bad (_("bad register name `%s'"), base_string
);
8862 /* If there's an expression beginning the operand, parse it,
8863 assuming displacement_string_start and
8864 displacement_string_end are meaningful. */
8865 if (displacement_string_start
!= displacement_string_end
)
8867 if (!i386_displacement (displacement_string_start
,
8868 displacement_string_end
))
8872 /* Special case for (%dx) while doing input/output op. */
8874 && operand_type_equal (&i
.base_reg
->reg_type
,
8875 ®16_inoutportreg
)
8877 && i
.log2_scale_factor
== 0
8878 && i
.seg
[i
.mem_operands
] == 0
8879 && !operand_type_check (i
.types
[this_operand
], disp
))
8881 i
.types
[this_operand
] = inoutportreg
;
8885 if (i386_index_check (operand_string
) == 0)
8887 i
.types
[this_operand
].bitfield
.mem
= 1;
8892 /* It's not a memory operand; argh! */
8893 as_bad (_("invalid char %s beginning operand %d `%s'"),
8894 output_invalid (*op_string
),
8899 return 1; /* Normal return. */
8902 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8903 that an rs_machine_dependent frag may reach. */
8906 i386_frag_max_var (fragS
*frag
)
8908 /* The only relaxable frags are for jumps.
8909 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8910 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8911 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8914 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8916 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
8918 /* STT_GNU_IFUNC symbol must go through PLT. */
8919 if ((symbol_get_bfdsym (fr_symbol
)->flags
8920 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
8923 if (!S_IS_EXTERNAL (fr_symbol
))
8924 /* Symbol may be weak or local. */
8925 return !S_IS_WEAK (fr_symbol
);
8927 /* Global symbols with non-default visibility can't be preempted. */
8928 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
8931 if (fr_var
!= NO_RELOC
)
8932 switch ((enum bfd_reloc_code_real
) fr_var
)
8934 case BFD_RELOC_386_PLT32
:
8935 case BFD_RELOC_X86_64_PLT32
:
8936 /* Symbol with PLT relocatin may be preempted. */
8942 /* Global symbols with default visibility in a shared library may be
8943 preempted by another definition. */
8948 /* md_estimate_size_before_relax()
8950 Called just before relax() for rs_machine_dependent frags. The x86
8951 assembler uses these frags to handle variable size jump
8954 Any symbol that is now undefined will not become defined.
8955 Return the correct fr_subtype in the frag.
8956 Return the initial "guess for variable size of frag" to caller.
8957 The guess is actually the growth beyond the fixed part. Whatever
8958 we do to grow the fixed or variable part contributes to our
8962 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8964 /* We've already got fragP->fr_subtype right; all we have to do is
8965 check for un-relaxable symbols. On an ELF system, we can't relax
8966 an externally visible symbol, because it may be overridden by a
8968 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8969 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8971 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
8974 #if defined (OBJ_COFF) && defined (TE_PE)
8975 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8976 && S_IS_WEAK (fragP
->fr_symbol
))
8980 /* Symbol is undefined in this segment, or we need to keep a
8981 reloc so that weak symbols can be overridden. */
8982 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8983 enum bfd_reloc_code_real reloc_type
;
8984 unsigned char *opcode
;
8987 if (fragP
->fr_var
!= NO_RELOC
)
8988 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8990 reloc_type
= BFD_RELOC_16_PCREL
;
8992 reloc_type
= BFD_RELOC_32_PCREL
;
8994 old_fr_fix
= fragP
->fr_fix
;
8995 opcode
= (unsigned char *) fragP
->fr_opcode
;
8997 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9000 /* Make jmp (0xeb) a (d)word displacement jump. */
9002 fragP
->fr_fix
+= size
;
9003 fix_new (fragP
, old_fr_fix
, size
,
9005 fragP
->fr_offset
, 1,
9011 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9013 /* Negate the condition, and branch past an
9014 unconditional jump. */
9017 /* Insert an unconditional jump. */
9019 /* We added two extra opcode bytes, and have a two byte
9021 fragP
->fr_fix
+= 2 + 2;
9022 fix_new (fragP
, old_fr_fix
+ 2, 2,
9024 fragP
->fr_offset
, 1,
9031 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9036 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9038 fragP
->fr_offset
, 1,
9040 fixP
->fx_signed
= 1;
9044 /* This changes the byte-displacement jump 0x7N
9045 to the (d)word-displacement jump 0x0f,0x8N. */
9046 opcode
[1] = opcode
[0] + 0x10;
9047 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9048 /* We've added an opcode byte. */
9049 fragP
->fr_fix
+= 1 + size
;
9050 fix_new (fragP
, old_fr_fix
+ 1, size
,
9052 fragP
->fr_offset
, 1,
9057 BAD_CASE (fragP
->fr_subtype
);
9061 return fragP
->fr_fix
- old_fr_fix
;
9064 /* Guess size depending on current relax state. Initially the relax
9065 state will correspond to a short jump and we return 1, because
9066 the variable part of the frag (the branch offset) is one byte
9067 long. However, we can relax a section more than once and in that
9068 case we must either set fr_subtype back to the unrelaxed state,
9069 or return the value for the appropriate branch. */
9070 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9073 /* Called after relax() is finished.
9075 In: Address of frag.
9076 fr_type == rs_machine_dependent.
9077 fr_subtype is what the address relaxed to.
9079 Out: Any fixSs and constants are set up.
9080 Caller will turn frag into a ".space 0". */
9083 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9086 unsigned char *opcode
;
9087 unsigned char *where_to_put_displacement
= NULL
;
9088 offsetT target_address
;
9089 offsetT opcode_address
;
9090 unsigned int extension
= 0;
9091 offsetT displacement_from_opcode_start
;
9093 opcode
= (unsigned char *) fragP
->fr_opcode
;
9095 /* Address we want to reach in file space. */
9096 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9098 /* Address opcode resides at in file space. */
9099 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9101 /* Displacement from opcode start to fill into instruction. */
9102 displacement_from_opcode_start
= target_address
- opcode_address
;
9104 if ((fragP
->fr_subtype
& BIG
) == 0)
9106 /* Don't have to change opcode. */
9107 extension
= 1; /* 1 opcode + 1 displacement */
9108 where_to_put_displacement
= &opcode
[1];
9112 if (no_cond_jump_promotion
9113 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9114 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9115 _("long jump required"));
9117 switch (fragP
->fr_subtype
)
9119 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9120 extension
= 4; /* 1 opcode + 4 displacement */
9122 where_to_put_displacement
= &opcode
[1];
9125 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9126 extension
= 2; /* 1 opcode + 2 displacement */
9128 where_to_put_displacement
= &opcode
[1];
9131 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9132 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9133 extension
= 5; /* 2 opcode + 4 displacement */
9134 opcode
[1] = opcode
[0] + 0x10;
9135 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9136 where_to_put_displacement
= &opcode
[2];
9139 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9140 extension
= 3; /* 2 opcode + 2 displacement */
9141 opcode
[1] = opcode
[0] + 0x10;
9142 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9143 where_to_put_displacement
= &opcode
[2];
9146 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9151 where_to_put_displacement
= &opcode
[3];
9155 BAD_CASE (fragP
->fr_subtype
);
9160 /* If size if less then four we are sure that the operand fits,
9161 but if it's 4, then it could be that the displacement is larger
9163 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9165 && ((addressT
) (displacement_from_opcode_start
- extension
9166 + ((addressT
) 1 << 31))
9167 > (((addressT
) 2 << 31) - 1)))
9169 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9170 _("jump target out of range"));
9171 /* Make us emit 0. */
9172 displacement_from_opcode_start
= extension
;
9174 /* Now put displacement after opcode. */
9175 md_number_to_chars ((char *) where_to_put_displacement
,
9176 (valueT
) (displacement_from_opcode_start
- extension
),
9177 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9178 fragP
->fr_fix
+= extension
;
9181 /* Apply a fixup (fixP) to segment data, once it has been determined
9182 by our caller that we have all the info we need to fix it up.
9184 Parameter valP is the pointer to the value of the bits.
9186 On the 386, immediates, displacements, and data pointers are all in
9187 the same (little-endian) format, so we don't need to care about which
9191 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9193 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9194 valueT value
= *valP
;
9196 #if !defined (TE_Mach)
9199 switch (fixP
->fx_r_type
)
9205 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9208 case BFD_RELOC_X86_64_32S
:
9209 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9212 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9215 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9220 if (fixP
->fx_addsy
!= NULL
9221 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9222 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9223 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9224 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9225 && !use_rela_relocations
)
9227 /* This is a hack. There should be a better way to handle this.
9228 This covers for the fact that bfd_install_relocation will
9229 subtract the current location (for partial_inplace, PC relative
9230 relocations); see more below. */
9234 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9237 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9239 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9242 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9245 || (symbol_section_p (fixP
->fx_addsy
)
9246 && sym_seg
!= absolute_section
))
9247 && !generic_force_reloc (fixP
))
9249 /* Yes, we add the values in twice. This is because
9250 bfd_install_relocation subtracts them out again. I think
9251 bfd_install_relocation is broken, but I don't dare change
9253 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9257 #if defined (OBJ_COFF) && defined (TE_PE)
9258 /* For some reason, the PE format does not store a
9259 section address offset for a PC relative symbol. */
9260 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9261 || S_IS_WEAK (fixP
->fx_addsy
))
9262 value
+= md_pcrel_from (fixP
);
9265 #if defined (OBJ_COFF) && defined (TE_PE)
9266 if (fixP
->fx_addsy
!= NULL
9267 && S_IS_WEAK (fixP
->fx_addsy
)
9268 /* PR 16858: Do not modify weak function references. */
9269 && ! fixP
->fx_pcrel
)
9271 #if !defined (TE_PEP)
9272 /* For x86 PE weak function symbols are neither PC-relative
9273 nor do they set S_IS_FUNCTION. So the only reliable way
9274 to detect them is to check the flags of their containing
9276 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9277 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9281 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9285 /* Fix a few things - the dynamic linker expects certain values here,
9286 and we must not disappoint it. */
9287 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9288 if (IS_ELF
&& fixP
->fx_addsy
)
9289 switch (fixP
->fx_r_type
)
9291 case BFD_RELOC_386_PLT32
:
9292 case BFD_RELOC_X86_64_PLT32
:
9293 /* Make the jump instruction point to the address of the operand. At
9294 runtime we merely add the offset to the actual PLT entry. */
9298 case BFD_RELOC_386_TLS_GD
:
9299 case BFD_RELOC_386_TLS_LDM
:
9300 case BFD_RELOC_386_TLS_IE_32
:
9301 case BFD_RELOC_386_TLS_IE
:
9302 case BFD_RELOC_386_TLS_GOTIE
:
9303 case BFD_RELOC_386_TLS_GOTDESC
:
9304 case BFD_RELOC_X86_64_TLSGD
:
9305 case BFD_RELOC_X86_64_TLSLD
:
9306 case BFD_RELOC_X86_64_GOTTPOFF
:
9307 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9308 value
= 0; /* Fully resolved at runtime. No addend. */
9310 case BFD_RELOC_386_TLS_LE
:
9311 case BFD_RELOC_386_TLS_LDO_32
:
9312 case BFD_RELOC_386_TLS_LE_32
:
9313 case BFD_RELOC_X86_64_DTPOFF32
:
9314 case BFD_RELOC_X86_64_DTPOFF64
:
9315 case BFD_RELOC_X86_64_TPOFF32
:
9316 case BFD_RELOC_X86_64_TPOFF64
:
9317 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9320 case BFD_RELOC_386_TLS_DESC_CALL
:
9321 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9322 value
= 0; /* Fully resolved at runtime. No addend. */
9323 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9327 case BFD_RELOC_386_GOT32
:
9328 case BFD_RELOC_X86_64_GOT32
:
9329 value
= 0; /* Fully resolved at runtime. No addend. */
9332 case BFD_RELOC_VTABLE_INHERIT
:
9333 case BFD_RELOC_VTABLE_ENTRY
:
9340 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9342 #endif /* !defined (TE_Mach) */
9344 /* Are we finished with this relocation now? */
9345 if (fixP
->fx_addsy
== NULL
)
9347 #if defined (OBJ_COFF) && defined (TE_PE)
9348 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9351 /* Remember value for tc_gen_reloc. */
9352 fixP
->fx_addnumber
= value
;
9353 /* Clear out the frag for now. */
9357 else if (use_rela_relocations
)
9359 fixP
->fx_no_overflow
= 1;
9360 /* Remember value for tc_gen_reloc. */
9361 fixP
->fx_addnumber
= value
;
9365 md_number_to_chars (p
, value
, fixP
->fx_size
);
9369 md_atof (int type
, char *litP
, int *sizeP
)
9371 /* This outputs the LITTLENUMs in REVERSE order;
9372 in accord with the bigendian 386. */
9373 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9376 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9379 output_invalid (int c
)
9382 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9385 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9386 "(0x%x)", (unsigned char) c
);
9387 return output_invalid_buf
;
9390 /* REG_STRING starts *before* REGISTER_PREFIX. */
9392 static const reg_entry
*
9393 parse_real_register (char *reg_string
, char **end_op
)
9395 char *s
= reg_string
;
9397 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9400 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9401 if (*s
== REGISTER_PREFIX
)
9404 if (is_space_char (*s
))
9408 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9410 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9411 return (const reg_entry
*) NULL
;
9415 /* For naked regs, make sure that we are not dealing with an identifier.
9416 This prevents confusing an identifier like `eax_var' with register
9418 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9419 return (const reg_entry
*) NULL
;
9423 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9425 /* Handle floating point regs, allowing spaces in the (i) part. */
9426 if (r
== i386_regtab
/* %st is first entry of table */)
9428 if (is_space_char (*s
))
9433 if (is_space_char (*s
))
9435 if (*s
>= '0' && *s
<= '7')
9439 if (is_space_char (*s
))
9444 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9449 /* We have "%st(" then garbage. */
9450 return (const reg_entry
*) NULL
;
9454 if (r
== NULL
|| allow_pseudo_reg
)
9457 if (operand_type_all_zero (&r
->reg_type
))
9458 return (const reg_entry
*) NULL
;
9460 if ((r
->reg_type
.bitfield
.reg32
9461 || r
->reg_type
.bitfield
.sreg3
9462 || r
->reg_type
.bitfield
.control
9463 || r
->reg_type
.bitfield
.debug
9464 || r
->reg_type
.bitfield
.test
)
9465 && !cpu_arch_flags
.bitfield
.cpui386
)
9466 return (const reg_entry
*) NULL
;
9468 if (r
->reg_type
.bitfield
.floatreg
9469 && !cpu_arch_flags
.bitfield
.cpu8087
9470 && !cpu_arch_flags
.bitfield
.cpu287
9471 && !cpu_arch_flags
.bitfield
.cpu387
)
9472 return (const reg_entry
*) NULL
;
9474 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9475 return (const reg_entry
*) NULL
;
9477 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9478 return (const reg_entry
*) NULL
;
9480 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9481 return (const reg_entry
*) NULL
;
9483 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9484 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9485 return (const reg_entry
*) NULL
;
9487 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9488 if (!allow_index_reg
9489 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9490 return (const reg_entry
*) NULL
;
9492 /* Upper 16 vector register is only available with VREX in 64bit
9494 if ((r
->reg_flags
& RegVRex
))
9496 if (!cpu_arch_flags
.bitfield
.cpuvrex
9497 || flag_code
!= CODE_64BIT
)
9498 return (const reg_entry
*) NULL
;
9503 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9504 || r
->reg_type
.bitfield
.reg64
)
9505 && (!cpu_arch_flags
.bitfield
.cpulm
9506 || !operand_type_equal (&r
->reg_type
, &control
))
9507 && flag_code
!= CODE_64BIT
)
9508 return (const reg_entry
*) NULL
;
9510 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9511 return (const reg_entry
*) NULL
;
9516 /* REG_STRING starts *before* REGISTER_PREFIX. */
9518 static const reg_entry
*
9519 parse_register (char *reg_string
, char **end_op
)
9523 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9524 r
= parse_real_register (reg_string
, end_op
);
9529 char *save
= input_line_pointer
;
9533 input_line_pointer
= reg_string
;
9534 c
= get_symbol_name (®_string
);
9535 symbolP
= symbol_find (reg_string
);
9536 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9538 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9540 know (e
->X_op
== O_register
);
9541 know (e
->X_add_number
>= 0
9542 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9543 r
= i386_regtab
+ e
->X_add_number
;
9544 if ((r
->reg_flags
& RegVRex
))
9546 *end_op
= input_line_pointer
;
9548 *input_line_pointer
= c
;
9549 input_line_pointer
= save
;
9555 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9558 char *end
= input_line_pointer
;
9561 r
= parse_register (name
, &input_line_pointer
);
9562 if (r
&& end
<= input_line_pointer
)
9564 *nextcharP
= *input_line_pointer
;
9565 *input_line_pointer
= 0;
9566 e
->X_op
= O_register
;
9567 e
->X_add_number
= r
- i386_regtab
;
9570 input_line_pointer
= end
;
9572 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9576 md_operand (expressionS
*e
)
9581 switch (*input_line_pointer
)
9583 case REGISTER_PREFIX
:
9584 r
= parse_real_register (input_line_pointer
, &end
);
9587 e
->X_op
= O_register
;
9588 e
->X_add_number
= r
- i386_regtab
;
9589 input_line_pointer
= end
;
9594 gas_assert (intel_syntax
);
9595 end
= input_line_pointer
++;
9597 if (*input_line_pointer
== ']')
9599 ++input_line_pointer
;
9600 e
->X_op_symbol
= make_expr_symbol (e
);
9601 e
->X_add_symbol
= NULL
;
9602 e
->X_add_number
= 0;
9608 input_line_pointer
= end
;
9615 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9616 const char *md_shortopts
= "kVQ:sqn";
9618 const char *md_shortopts
= "qn";
9621 #define OPTION_32 (OPTION_MD_BASE + 0)
9622 #define OPTION_64 (OPTION_MD_BASE + 1)
9623 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9624 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9625 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9626 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9627 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9628 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9629 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9630 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9631 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9632 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9633 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9634 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9635 #define OPTION_X32 (OPTION_MD_BASE + 14)
9636 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9637 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9638 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9639 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9640 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9641 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9642 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9643 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9644 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9645 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9647 struct option md_longopts
[] =
9649 {"32", no_argument
, NULL
, OPTION_32
},
9650 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9651 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9652 {"64", no_argument
, NULL
, OPTION_64
},
9654 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9655 {"x32", no_argument
, NULL
, OPTION_X32
},
9656 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
9658 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9659 {"march", required_argument
, NULL
, OPTION_MARCH
},
9660 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9661 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9662 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9663 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9664 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9665 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9666 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9667 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9668 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9669 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9670 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9671 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9672 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9673 # if defined (TE_PE) || defined (TE_PEP)
9674 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9676 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
9677 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
9678 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9679 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
9680 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
9681 {NULL
, no_argument
, NULL
, 0}
9683 size_t md_longopts_size
= sizeof (md_longopts
);
9686 md_parse_option (int c
, char *arg
)
9694 optimize_align_code
= 0;
9701 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9702 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9703 should be emitted or not. FIXME: Not implemented. */
9707 /* -V: SVR4 argument to print version ID. */
9709 print_version_id ();
9712 /* -k: Ignore for FreeBSD compatibility. */
9717 /* -s: On i386 Solaris, this tells the native assembler to use
9718 .stab instead of .stab.excl. We always use .stab anyhow. */
9721 case OPTION_MSHARED
:
9725 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9726 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9729 const char **list
, **l
;
9731 list
= bfd_target_list ();
9732 for (l
= list
; *l
!= NULL
; l
++)
9733 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9734 || strcmp (*l
, "coff-x86-64") == 0
9735 || strcmp (*l
, "pe-x86-64") == 0
9736 || strcmp (*l
, "pei-x86-64") == 0
9737 || strcmp (*l
, "mach-o-x86-64") == 0)
9739 default_arch
= "x86_64";
9743 as_fatal (_("no compiled in support for x86_64"));
9749 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9753 const char **list
, **l
;
9755 list
= bfd_target_list ();
9756 for (l
= list
; *l
!= NULL
; l
++)
9757 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9759 default_arch
= "x86_64:32";
9763 as_fatal (_("no compiled in support for 32bit x86_64"));
9767 as_fatal (_("32bit x86_64 is only supported for ELF"));
9772 default_arch
= "i386";
9776 #ifdef SVR4_COMMENT_CHARS
9781 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9783 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9787 i386_comment_chars
= n
;
9793 arch
= xstrdup (arg
);
9797 as_fatal (_("invalid -march= option: `%s'"), arg
);
9798 next
= strchr (arch
, '+');
9801 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9803 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9806 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9809 cpu_arch_name
= cpu_arch
[j
].name
;
9810 cpu_sub_arch_name
= NULL
;
9811 cpu_arch_flags
= cpu_arch
[j
].flags
;
9812 cpu_arch_isa
= cpu_arch
[j
].type
;
9813 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9814 if (!cpu_arch_tune_set
)
9816 cpu_arch_tune
= cpu_arch_isa
;
9817 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9821 else if (*cpu_arch
[j
].name
== '.'
9822 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9824 /* ISA entension. */
9825 i386_cpu_flags flags
;
9827 if (!cpu_arch
[j
].negated
)
9828 flags
= cpu_flags_or (cpu_arch_flags
,
9831 flags
= cpu_flags_and_not (cpu_arch_flags
,
9834 if (!valid_iamcu_cpu_flags (&flags
))
9835 as_fatal (_("`%s' isn't valid for Intel MCU"), arch
);
9836 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9838 if (cpu_sub_arch_name
)
9840 char *name
= cpu_sub_arch_name
;
9841 cpu_sub_arch_name
= concat (name
,
9843 (const char *) NULL
);
9847 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9848 cpu_arch_flags
= flags
;
9849 cpu_arch_isa_flags
= flags
;
9855 if (j
>= ARRAY_SIZE (cpu_arch
))
9856 as_fatal (_("invalid -march= option: `%s'"), arg
);
9860 while (next
!= NULL
);
9865 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9866 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9868 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9870 cpu_arch_tune_set
= 1;
9871 cpu_arch_tune
= cpu_arch
[j
].type
;
9872 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9876 if (j
>= ARRAY_SIZE (cpu_arch
))
9877 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9880 case OPTION_MMNEMONIC
:
9881 if (strcasecmp (arg
, "att") == 0)
9883 else if (strcasecmp (arg
, "intel") == 0)
9886 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9889 case OPTION_MSYNTAX
:
9890 if (strcasecmp (arg
, "att") == 0)
9892 else if (strcasecmp (arg
, "intel") == 0)
9895 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9898 case OPTION_MINDEX_REG
:
9899 allow_index_reg
= 1;
9902 case OPTION_MNAKED_REG
:
9903 allow_naked_reg
= 1;
9906 case OPTION_MOLD_GCC
:
9910 case OPTION_MSSE2AVX
:
9914 case OPTION_MSSE_CHECK
:
9915 if (strcasecmp (arg
, "error") == 0)
9916 sse_check
= check_error
;
9917 else if (strcasecmp (arg
, "warning") == 0)
9918 sse_check
= check_warning
;
9919 else if (strcasecmp (arg
, "none") == 0)
9920 sse_check
= check_none
;
9922 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9925 case OPTION_MOPERAND_CHECK
:
9926 if (strcasecmp (arg
, "error") == 0)
9927 operand_check
= check_error
;
9928 else if (strcasecmp (arg
, "warning") == 0)
9929 operand_check
= check_warning
;
9930 else if (strcasecmp (arg
, "none") == 0)
9931 operand_check
= check_none
;
9933 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9936 case OPTION_MAVXSCALAR
:
9937 if (strcasecmp (arg
, "128") == 0)
9939 else if (strcasecmp (arg
, "256") == 0)
9942 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9945 case OPTION_MADD_BND_PREFIX
:
9949 case OPTION_MEVEXLIG
:
9950 if (strcmp (arg
, "128") == 0)
9952 else if (strcmp (arg
, "256") == 0)
9954 else if (strcmp (arg
, "512") == 0)
9957 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9960 case OPTION_MEVEXRCIG
:
9961 if (strcmp (arg
, "rne") == 0)
9963 else if (strcmp (arg
, "rd") == 0)
9965 else if (strcmp (arg
, "ru") == 0)
9967 else if (strcmp (arg
, "rz") == 0)
9970 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
9973 case OPTION_MEVEXWIG
:
9974 if (strcmp (arg
, "0") == 0)
9976 else if (strcmp (arg
, "1") == 0)
9979 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9982 # if defined (TE_PE) || defined (TE_PEP)
9983 case OPTION_MBIG_OBJ
:
9988 case OPTION_MOMIT_LOCK_PREFIX
:
9989 if (strcasecmp (arg
, "yes") == 0)
9990 omit_lock_prefix
= 1;
9991 else if (strcasecmp (arg
, "no") == 0)
9992 omit_lock_prefix
= 0;
9994 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
9997 case OPTION_MFENCE_AS_LOCK_ADD
:
9998 if (strcasecmp (arg
, "yes") == 0)
10000 else if (strcasecmp (arg
, "no") == 0)
10003 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10006 case OPTION_MAMD64
:
10007 cpu_arch_flags
.bitfield
.cpuamd64
= 1;
10008 cpu_arch_flags
.bitfield
.cpuintel64
= 0;
10009 cpu_arch_isa_flags
.bitfield
.cpuamd64
= 1;
10010 cpu_arch_isa_flags
.bitfield
.cpuintel64
= 0;
10013 case OPTION_MINTEL64
:
10014 cpu_arch_flags
.bitfield
.cpuamd64
= 0;
10015 cpu_arch_flags
.bitfield
.cpuintel64
= 1;
10016 cpu_arch_isa_flags
.bitfield
.cpuamd64
= 0;
10017 cpu_arch_isa_flags
.bitfield
.cpuintel64
= 1;
10026 #define MESSAGE_TEMPLATE \
10030 show_arch (FILE *stream
, int ext
, int check
)
10032 static char message
[] = MESSAGE_TEMPLATE
;
10033 char *start
= message
+ 27;
10035 int size
= sizeof (MESSAGE_TEMPLATE
);
10042 left
= size
- (start
- message
);
10043 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10045 /* Should it be skipped? */
10046 if (cpu_arch
[j
].skip
)
10049 name
= cpu_arch
[j
].name
;
10050 len
= cpu_arch
[j
].len
;
10053 /* It is an extension. Skip if we aren't asked to show it. */
10064 /* It is an processor. Skip if we show only extension. */
10067 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10069 /* It is an impossible processor - skip. */
10073 /* Reserve 2 spaces for ", " or ",\0" */
10076 /* Check if there is any room. */
10084 p
= mempcpy (p
, name
, len
);
10088 /* Output the current message now and start a new one. */
10091 fprintf (stream
, "%s\n", message
);
10093 left
= size
- (start
- message
) - len
- 2;
10095 gas_assert (left
>= 0);
10097 p
= mempcpy (p
, name
, len
);
10102 fprintf (stream
, "%s\n", message
);
10106 md_show_usage (FILE *stream
)
10108 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10109 fprintf (stream
, _("\
10111 -V print assembler version number\n\
10114 fprintf (stream
, _("\
10115 -n Do not optimize code alignment\n\
10116 -q quieten some warnings\n"));
10117 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10118 fprintf (stream
, _("\
10121 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10122 || defined (TE_PE) || defined (TE_PEP))
10123 fprintf (stream
, _("\
10124 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10126 #ifdef SVR4_COMMENT_CHARS
10127 fprintf (stream
, _("\
10128 --divide do not treat `/' as a comment character\n"));
10130 fprintf (stream
, _("\
10131 --divide ignored\n"));
10133 fprintf (stream
, _("\
10134 -march=CPU[,+EXTENSION...]\n\
10135 generate code for CPU and EXTENSION, CPU is one of:\n"));
10136 show_arch (stream
, 0, 1);
10137 fprintf (stream
, _("\
10138 EXTENSION is combination of:\n"));
10139 show_arch (stream
, 1, 0);
10140 fprintf (stream
, _("\
10141 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10142 show_arch (stream
, 0, 0);
10143 fprintf (stream
, _("\
10144 -msse2avx encode SSE instructions with VEX prefix\n"));
10145 fprintf (stream
, _("\
10146 -msse-check=[none|error|warning]\n\
10147 check SSE instructions\n"));
10148 fprintf (stream
, _("\
10149 -moperand-check=[none|error|warning]\n\
10150 check operand combinations for validity\n"));
10151 fprintf (stream
, _("\
10152 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10154 fprintf (stream
, _("\
10155 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10157 fprintf (stream
, _("\
10158 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10159 for EVEX.W bit ignored instructions\n"));
10160 fprintf (stream
, _("\
10161 -mevexrcig=[rne|rd|ru|rz]\n\
10162 encode EVEX instructions with specific EVEX.RC value\n\
10163 for SAE-only ignored instructions\n"));
10164 fprintf (stream
, _("\
10165 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10166 fprintf (stream
, _("\
10167 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10168 fprintf (stream
, _("\
10169 -mindex-reg support pseudo index registers\n"));
10170 fprintf (stream
, _("\
10171 -mnaked-reg don't require `%%' prefix for registers\n"));
10172 fprintf (stream
, _("\
10173 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10174 fprintf (stream
, _("\
10175 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10176 fprintf (stream
, _("\
10177 -mshared disable branch optimization for shared code\n"));
10178 # if defined (TE_PE) || defined (TE_PEP)
10179 fprintf (stream
, _("\
10180 -mbig-obj generate big object files\n"));
10182 fprintf (stream
, _("\
10183 -momit-lock-prefix=[no|yes]\n\
10184 strip all lock prefixes\n"));
10185 fprintf (stream
, _("\
10186 -mfence-as-lock-add=[no|yes]\n\
10187 encode lfence, mfence and sfence as\n\
10188 lock addl $0x0, (%%{re}sp)\n"));
10189 fprintf (stream
, _("\
10190 -mamd64 accept only AMD64 ISA\n"));
10191 fprintf (stream
, _("\
10192 -mintel64 accept only Intel64 ISA\n"));
10195 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10196 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10197 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10199 /* Pick the target format to use. */
10202 i386_target_format (void)
10204 if (!strncmp (default_arch
, "x86_64", 6))
10206 update_code_flag (CODE_64BIT
, 1);
10207 if (default_arch
[6] == '\0')
10208 x86_elf_abi
= X86_64_ABI
;
10210 x86_elf_abi
= X86_64_X32_ABI
;
10212 else if (!strcmp (default_arch
, "i386"))
10213 update_code_flag (CODE_32BIT
, 1);
10214 else if (!strcmp (default_arch
, "iamcu"))
10216 update_code_flag (CODE_32BIT
, 1);
10217 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10219 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10220 cpu_arch_name
= "iamcu";
10221 cpu_sub_arch_name
= NULL
;
10222 cpu_arch_flags
= iamcu_flags
;
10223 cpu_arch_isa
= PROCESSOR_IAMCU
;
10224 cpu_arch_isa_flags
= iamcu_flags
;
10225 if (!cpu_arch_tune_set
)
10227 cpu_arch_tune
= cpu_arch_isa
;
10228 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10232 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10236 as_fatal (_("unknown architecture"));
10238 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10239 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10240 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10241 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10243 switch (OUTPUT_FLAVOR
)
10245 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10246 case bfd_target_aout_flavour
:
10247 return AOUT_TARGET_FORMAT
;
10249 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10250 # if defined (TE_PE) || defined (TE_PEP)
10251 case bfd_target_coff_flavour
:
10252 if (flag_code
== CODE_64BIT
)
10253 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10256 # elif defined (TE_GO32)
10257 case bfd_target_coff_flavour
:
10258 return "coff-go32";
10260 case bfd_target_coff_flavour
:
10261 return "coff-i386";
10264 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10265 case bfd_target_elf_flavour
:
10267 const char *format
;
10269 switch (x86_elf_abi
)
10272 format
= ELF_TARGET_FORMAT
;
10275 use_rela_relocations
= 1;
10277 format
= ELF_TARGET_FORMAT64
;
10279 case X86_64_X32_ABI
:
10280 use_rela_relocations
= 1;
10282 disallow_64bit_reloc
= 1;
10283 format
= ELF_TARGET_FORMAT32
;
10286 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10288 if (x86_elf_abi
!= X86_64_ABI
)
10289 as_fatal (_("Intel L1OM is 64bit only"));
10290 return ELF_TARGET_L1OM_FORMAT
;
10292 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10294 if (x86_elf_abi
!= X86_64_ABI
)
10295 as_fatal (_("Intel K1OM is 64bit only"));
10296 return ELF_TARGET_K1OM_FORMAT
;
10298 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10300 if (x86_elf_abi
!= I386_ABI
)
10301 as_fatal (_("Intel MCU is 32bit only"));
10302 return ELF_TARGET_IAMCU_FORMAT
;
10308 #if defined (OBJ_MACH_O)
10309 case bfd_target_mach_o_flavour
:
10310 if (flag_code
== CODE_64BIT
)
10312 use_rela_relocations
= 1;
10314 return "mach-o-x86-64";
10317 return "mach-o-i386";
10325 #endif /* OBJ_MAYBE_ more than one */
10328 md_undefined_symbol (char *name
)
10330 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10331 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10332 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10333 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10337 if (symbol_find (name
))
10338 as_bad (_("GOT already in symbol table"));
10339 GOT_symbol
= symbol_new (name
, undefined_section
,
10340 (valueT
) 0, &zero_address_frag
);
10347 /* Round up a section size to the appropriate boundary. */
10350 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10352 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10353 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10355 /* For a.out, force the section size to be aligned. If we don't do
10356 this, BFD will align it for us, but it will not write out the
10357 final bytes of the section. This may be a bug in BFD, but it is
10358 easier to fix it here since that is how the other a.out targets
10362 align
= bfd_get_section_alignment (stdoutput
, segment
);
10363 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
10370 /* On the i386, PC-relative offsets are relative to the start of the
10371 next instruction. That is, the address of the offset, plus its
10372 size, since the offset is always the last part of the insn. */
10375 md_pcrel_from (fixS
*fixP
)
10377 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10383 s_bss (int ignore ATTRIBUTE_UNUSED
)
10387 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10389 obj_elf_section_change_hook ();
10391 temp
= get_absolute_expression ();
10392 subseg_set (bss_section
, (subsegT
) temp
);
10393 demand_empty_rest_of_line ();
10399 i386_validate_fix (fixS
*fixp
)
10401 if (fixp
->fx_subsy
)
10403 if (fixp
->fx_subsy
== GOT_symbol
)
10405 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10409 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10410 if (fixp
->fx_tcbit2
)
10411 fixp
->fx_r_type
= (fixp
->fx_tcbit
10412 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10413 : BFD_RELOC_X86_64_GOTPCRELX
);
10416 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10421 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10423 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10425 fixp
->fx_subsy
= 0;
10428 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10429 else if (!object_64bit
)
10431 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
10432 && fixp
->fx_tcbit2
)
10433 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
10439 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10442 bfd_reloc_code_real_type code
;
10444 switch (fixp
->fx_r_type
)
10446 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10447 case BFD_RELOC_SIZE32
:
10448 case BFD_RELOC_SIZE64
:
10449 if (S_IS_DEFINED (fixp
->fx_addsy
)
10450 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10452 /* Resolve size relocation against local symbol to size of
10453 the symbol plus addend. */
10454 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10455 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10456 && !fits_in_unsigned_long (value
))
10457 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10458 _("symbol size computation overflow"));
10459 fixp
->fx_addsy
= NULL
;
10460 fixp
->fx_subsy
= NULL
;
10461 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10466 case BFD_RELOC_X86_64_PLT32
:
10467 case BFD_RELOC_X86_64_GOT32
:
10468 case BFD_RELOC_X86_64_GOTPCREL
:
10469 case BFD_RELOC_X86_64_GOTPCRELX
:
10470 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10471 case BFD_RELOC_386_PLT32
:
10472 case BFD_RELOC_386_GOT32
:
10473 case BFD_RELOC_386_GOT32X
:
10474 case BFD_RELOC_386_GOTOFF
:
10475 case BFD_RELOC_386_GOTPC
:
10476 case BFD_RELOC_386_TLS_GD
:
10477 case BFD_RELOC_386_TLS_LDM
:
10478 case BFD_RELOC_386_TLS_LDO_32
:
10479 case BFD_RELOC_386_TLS_IE_32
:
10480 case BFD_RELOC_386_TLS_IE
:
10481 case BFD_RELOC_386_TLS_GOTIE
:
10482 case BFD_RELOC_386_TLS_LE_32
:
10483 case BFD_RELOC_386_TLS_LE
:
10484 case BFD_RELOC_386_TLS_GOTDESC
:
10485 case BFD_RELOC_386_TLS_DESC_CALL
:
10486 case BFD_RELOC_X86_64_TLSGD
:
10487 case BFD_RELOC_X86_64_TLSLD
:
10488 case BFD_RELOC_X86_64_DTPOFF32
:
10489 case BFD_RELOC_X86_64_DTPOFF64
:
10490 case BFD_RELOC_X86_64_GOTTPOFF
:
10491 case BFD_RELOC_X86_64_TPOFF32
:
10492 case BFD_RELOC_X86_64_TPOFF64
:
10493 case BFD_RELOC_X86_64_GOTOFF64
:
10494 case BFD_RELOC_X86_64_GOTPC32
:
10495 case BFD_RELOC_X86_64_GOT64
:
10496 case BFD_RELOC_X86_64_GOTPCREL64
:
10497 case BFD_RELOC_X86_64_GOTPC64
:
10498 case BFD_RELOC_X86_64_GOTPLT64
:
10499 case BFD_RELOC_X86_64_PLTOFF64
:
10500 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10501 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10502 case BFD_RELOC_RVA
:
10503 case BFD_RELOC_VTABLE_ENTRY
:
10504 case BFD_RELOC_VTABLE_INHERIT
:
10506 case BFD_RELOC_32_SECREL
:
10508 code
= fixp
->fx_r_type
;
10510 case BFD_RELOC_X86_64_32S
:
10511 if (!fixp
->fx_pcrel
)
10513 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10514 code
= fixp
->fx_r_type
;
10518 if (fixp
->fx_pcrel
)
10520 switch (fixp
->fx_size
)
10523 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10524 _("can not do %d byte pc-relative relocation"),
10526 code
= BFD_RELOC_32_PCREL
;
10528 case 1: code
= BFD_RELOC_8_PCREL
; break;
10529 case 2: code
= BFD_RELOC_16_PCREL
; break;
10530 case 4: code
= BFD_RELOC_32_PCREL
; break;
10532 case 8: code
= BFD_RELOC_64_PCREL
; break;
10538 switch (fixp
->fx_size
)
10541 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10542 _("can not do %d byte relocation"),
10544 code
= BFD_RELOC_32
;
10546 case 1: code
= BFD_RELOC_8
; break;
10547 case 2: code
= BFD_RELOC_16
; break;
10548 case 4: code
= BFD_RELOC_32
; break;
10550 case 8: code
= BFD_RELOC_64
; break;
10557 if ((code
== BFD_RELOC_32
10558 || code
== BFD_RELOC_32_PCREL
10559 || code
== BFD_RELOC_X86_64_32S
)
10561 && fixp
->fx_addsy
== GOT_symbol
)
10564 code
= BFD_RELOC_386_GOTPC
;
10566 code
= BFD_RELOC_X86_64_GOTPC32
;
10568 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10570 && fixp
->fx_addsy
== GOT_symbol
)
10572 code
= BFD_RELOC_X86_64_GOTPC64
;
10575 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10576 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10577 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10579 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10581 if (!use_rela_relocations
)
10583 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10584 vtable entry to be used in the relocation's section offset. */
10585 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10586 rel
->address
= fixp
->fx_offset
;
10587 #if defined (OBJ_COFF) && defined (TE_PE)
10588 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10589 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10594 /* Use the rela in 64bit mode. */
10597 if (disallow_64bit_reloc
)
10600 case BFD_RELOC_X86_64_DTPOFF64
:
10601 case BFD_RELOC_X86_64_TPOFF64
:
10602 case BFD_RELOC_64_PCREL
:
10603 case BFD_RELOC_X86_64_GOTOFF64
:
10604 case BFD_RELOC_X86_64_GOT64
:
10605 case BFD_RELOC_X86_64_GOTPCREL64
:
10606 case BFD_RELOC_X86_64_GOTPC64
:
10607 case BFD_RELOC_X86_64_GOTPLT64
:
10608 case BFD_RELOC_X86_64_PLTOFF64
:
10609 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10610 _("cannot represent relocation type %s in x32 mode"),
10611 bfd_get_reloc_code_name (code
));
10617 if (!fixp
->fx_pcrel
)
10618 rel
->addend
= fixp
->fx_offset
;
10622 case BFD_RELOC_X86_64_PLT32
:
10623 case BFD_RELOC_X86_64_GOT32
:
10624 case BFD_RELOC_X86_64_GOTPCREL
:
10625 case BFD_RELOC_X86_64_GOTPCRELX
:
10626 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10627 case BFD_RELOC_X86_64_TLSGD
:
10628 case BFD_RELOC_X86_64_TLSLD
:
10629 case BFD_RELOC_X86_64_GOTTPOFF
:
10630 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10631 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10632 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10635 rel
->addend
= (section
->vma
10637 + fixp
->fx_addnumber
10638 + md_pcrel_from (fixp
));
10643 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10644 if (rel
->howto
== NULL
)
10646 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10647 _("cannot represent relocation type %s"),
10648 bfd_get_reloc_code_name (code
));
10649 /* Set howto to a garbage value so that we can keep going. */
10650 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10651 gas_assert (rel
->howto
!= NULL
);
10657 #include "tc-i386-intel.c"
10660 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10662 int saved_naked_reg
;
10663 char saved_register_dot
;
10665 saved_naked_reg
= allow_naked_reg
;
10666 allow_naked_reg
= 1;
10667 saved_register_dot
= register_chars
['.'];
10668 register_chars
['.'] = '.';
10669 allow_pseudo_reg
= 1;
10670 expression_and_evaluate (exp
);
10671 allow_pseudo_reg
= 0;
10672 register_chars
['.'] = saved_register_dot
;
10673 allow_naked_reg
= saved_naked_reg
;
10675 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10677 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10679 exp
->X_op
= O_constant
;
10680 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10681 .dw2_regnum
[flag_code
>> 1];
10684 exp
->X_op
= O_illegal
;
10689 tc_x86_frame_initial_instructions (void)
10691 static unsigned int sp_regno
[2];
10693 if (!sp_regno
[flag_code
>> 1])
10695 char *saved_input
= input_line_pointer
;
10696 char sp
[][4] = {"esp", "rsp"};
10699 input_line_pointer
= sp
[flag_code
>> 1];
10700 tc_x86_parse_to_dw2regnum (&exp
);
10701 gas_assert (exp
.X_op
== O_constant
);
10702 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10703 input_line_pointer
= saved_input
;
10706 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10707 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10711 x86_dwarf2_addr_size (void)
10713 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10714 if (x86_elf_abi
== X86_64_X32_ABI
)
10717 return bfd_arch_bits_per_address (stdoutput
) / 8;
10721 i386_elf_section_type (const char *str
, size_t len
)
10723 if (flag_code
== CODE_64BIT
10724 && len
== sizeof ("unwind") - 1
10725 && strncmp (str
, "unwind", 6) == 0)
10726 return SHT_X86_64_UNWIND
;
10733 i386_solaris_fix_up_eh_frame (segT sec
)
10735 if (flag_code
== CODE_64BIT
)
10736 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10742 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10746 exp
.X_op
= O_secrel
;
10747 exp
.X_add_symbol
= symbol
;
10748 exp
.X_add_number
= 0;
10749 emit_expr (&exp
, size
);
10753 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10754 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10757 x86_64_section_letter (int letter
, char **ptr_msg
)
10759 if (flag_code
== CODE_64BIT
)
10762 return SHF_X86_64_LARGE
;
10764 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10767 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10772 x86_64_section_word (char *str
, size_t len
)
10774 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10775 return SHF_X86_64_LARGE
;
10781 handle_large_common (int small ATTRIBUTE_UNUSED
)
10783 if (flag_code
!= CODE_64BIT
)
10785 s_comm_internal (0, elf_common_parse
);
10786 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10790 static segT lbss_section
;
10791 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10792 asection
*saved_bss_section
= bss_section
;
10794 if (lbss_section
== NULL
)
10796 flagword applicable
;
10797 segT seg
= now_seg
;
10798 subsegT subseg
= now_subseg
;
10800 /* The .lbss section is for local .largecomm symbols. */
10801 lbss_section
= subseg_new (".lbss", 0);
10802 applicable
= bfd_applicable_section_flags (stdoutput
);
10803 bfd_set_section_flags (stdoutput
, lbss_section
,
10804 applicable
& SEC_ALLOC
);
10805 seg_info (lbss_section
)->bss
= 1;
10807 subseg_set (seg
, subseg
);
10810 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10811 bss_section
= lbss_section
;
10813 s_comm_internal (0, elf_common_parse
);
10815 elf_com_section_ptr
= saved_com_section_ptr
;
10816 bss_section
= saved_bss_section
;
10819 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */