1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static INLINE
unsigned int mode_from_disp_size
PARAMS ((unsigned int));
67 static INLINE
int fits_in_signed_byte
PARAMS ((offsetT
));
68 static INLINE
int fits_in_unsigned_byte
PARAMS ((offsetT
));
69 static INLINE
int fits_in_unsigned_word
PARAMS ((offsetT
));
70 static INLINE
int fits_in_signed_word
PARAMS ((offsetT
));
71 static INLINE
int fits_in_unsigned_long
PARAMS ((offsetT
));
72 static INLINE
int fits_in_signed_long
PARAMS ((offsetT
));
73 static int smallest_imm_type
PARAMS ((offsetT
));
74 static offsetT offset_in_range
PARAMS ((offsetT
, int));
75 static int add_prefix
PARAMS ((unsigned int));
76 static void set_code_flag
PARAMS ((int));
77 static void set_16bit_gcc_code_flag
PARAMS ((int));
78 static void set_intel_syntax
PARAMS ((int));
79 static void set_cpu_arch
PARAMS ((int));
81 static void pe_directive_secrel
PARAMS ((int));
83 static void signed_cons
PARAMS ((int));
84 static char *output_invalid
PARAMS ((int c
));
85 static int i386_operand
PARAMS ((char *operand_string
));
86 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
87 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
89 static char *parse_insn
PARAMS ((char *, char *));
90 static char *parse_operands
PARAMS ((char *, const char *));
91 static void swap_operands
PARAMS ((void));
92 static void swap_imm_operands
PARAMS ((void));
93 static void optimize_imm
PARAMS ((void));
94 static void optimize_disp
PARAMS ((void));
95 static int match_template
PARAMS ((void));
96 static int check_string
PARAMS ((void));
97 static int process_suffix
PARAMS ((void));
98 static int check_byte_reg
PARAMS ((void));
99 static int check_long_reg
PARAMS ((void));
100 static int check_qword_reg
PARAMS ((void));
101 static int check_word_reg
PARAMS ((void));
102 static int finalize_imm
PARAMS ((void));
103 static int process_operands
PARAMS ((void));
104 static const seg_entry
*build_modrm_byte
PARAMS ((void));
105 static void output_insn
PARAMS ((void));
106 static void output_branch
PARAMS ((void));
107 static void output_jump
PARAMS ((void));
108 static void output_interseg_jump
PARAMS ((void));
109 static void output_imm
PARAMS ((fragS
*insn_start_frag
,
110 offsetT insn_start_off
));
111 static void output_disp
PARAMS ((fragS
*insn_start_frag
,
112 offsetT insn_start_off
));
114 static void s_bss
PARAMS ((int));
116 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
117 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
120 static const char *default_arch
= DEFAULT_ARCH
;
122 /* 'md_assemble ()' gathers together information and puts it into a
129 const reg_entry
*regs
;
134 /* TM holds the template for the insn were currently assembling. */
137 /* SUFFIX holds the instruction mnemonic suffix if given.
138 (e.g. 'l' for 'movl') */
141 /* OPERANDS gives the number of given operands. */
142 unsigned int operands
;
144 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
145 of given register, displacement, memory operands and immediate
147 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
149 /* TYPES [i] is the type (see above #defines) which tells us how to
150 use OP[i] for the corresponding operand. */
151 unsigned int types
[MAX_OPERANDS
];
153 /* Displacement expression, immediate expression, or register for each
155 union i386_op op
[MAX_OPERANDS
];
157 /* Flags for operands. */
158 unsigned int flags
[MAX_OPERANDS
];
159 #define Operand_PCrel 1
161 /* Relocation type for operand */
162 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
164 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
165 the base index byte below. */
166 const reg_entry
*base_reg
;
167 const reg_entry
*index_reg
;
168 unsigned int log2_scale_factor
;
170 /* SEG gives the seg_entries of this insn. They are zero unless
171 explicit segment overrides are given. */
172 const seg_entry
*seg
[2];
174 /* PREFIX holds all the given prefix opcodes (usually null).
175 PREFIXES is the number of prefix opcodes. */
176 unsigned int prefixes
;
177 unsigned char prefix
[MAX_PREFIXES
];
179 /* RM and SIB are the modrm byte and the sib byte where the
180 addressing modes of this insn are encoded. */
187 typedef struct _i386_insn i386_insn
;
189 /* List of chars besides those in app.c:symbol_chars that can start an
190 operand. Used to prevent the scrubber eating vital white-space. */
191 const char extra_symbol_chars
[] = "*%-(["
200 #if (defined (TE_I386AIX) \
201 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
202 && !defined (TE_GNU) \
203 && !defined (TE_LINUX) \
204 && !defined (TE_NETWARE) \
205 && !defined (TE_FreeBSD) \
206 && !defined (TE_NetBSD)))
207 /* This array holds the chars that always start a comment. If the
208 pre-processor is disabled, these aren't very useful. The option
209 --divide will remove '/' from this list. */
210 const char *i386_comment_chars
= "#/";
211 #define SVR4_COMMENT_CHARS 1
212 #define PREFIX_SEPARATOR '\\'
215 const char *i386_comment_chars
= "#";
216 #define PREFIX_SEPARATOR '/'
219 /* This array holds the chars that only start a comment at the beginning of
220 a line. If the line seems to have the form '# 123 filename'
221 .line and .file directives will appear in the pre-processed output.
222 Note that input_file.c hand checks for '#' at the beginning of the
223 first line of the input file. This is because the compiler outputs
224 #NO_APP at the beginning of its output.
225 Also note that comments started like this one will always work if
226 '/' isn't otherwise defined. */
227 const char line_comment_chars
[] = "#/";
229 const char line_separator_chars
[] = ";";
231 /* Chars that can be used to separate mant from exp in floating point
233 const char EXP_CHARS
[] = "eE";
235 /* Chars that mean this number is a floating point constant
238 const char FLT_CHARS
[] = "fFdDxX";
240 /* Tables for lexical analysis. */
241 static char mnemonic_chars
[256];
242 static char register_chars
[256];
243 static char operand_chars
[256];
244 static char identifier_chars
[256];
245 static char digit_chars
[256];
247 /* Lexical macros. */
248 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
249 #define is_operand_char(x) (operand_chars[(unsigned char) x])
250 #define is_register_char(x) (register_chars[(unsigned char) x])
251 #define is_space_char(x) ((x) == ' ')
252 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
253 #define is_digit_char(x) (digit_chars[(unsigned char) x])
255 /* All non-digit non-letter characters that may occur in an operand. */
256 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
258 /* md_assemble() always leaves the strings it's passed unaltered. To
259 effect this we maintain a stack of saved characters that we've smashed
260 with '\0's (indicating end of strings for various sub-fields of the
261 assembler instruction). */
262 static char save_stack
[32];
263 static char *save_stack_p
;
264 #define END_STRING_AND_SAVE(s) \
265 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
266 #define RESTORE_END_STRING(s) \
267 do { *(s) = *--save_stack_p; } while (0)
269 /* The instruction we're assembling. */
272 /* Possible templates for current insn. */
273 static const templates
*current_templates
;
275 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
276 static expressionS disp_expressions
[2], im_expressions
[2];
278 /* Current operand we are working on. */
279 static int this_operand
;
281 /* We support four different modes. FLAG_CODE variable is used to distinguish
288 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
290 static enum flag_code flag_code
;
291 static unsigned int object_64bit
;
292 static int use_rela_relocations
= 0;
294 /* The names used to print error messages. */
295 static const char *flag_code_names
[] =
302 /* 1 for intel syntax,
304 static int intel_syntax
= 0;
306 /* 1 if register prefix % not required. */
307 static int allow_naked_reg
= 0;
309 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
310 leave, push, and pop instructions so that gcc has the same stack
311 frame as in 32 bit mode. */
312 static char stackop_size
= '\0';
314 /* Non-zero to optimize code alignment. */
315 int optimize_align_code
= 1;
317 /* Non-zero to quieten some warnings. */
318 static int quiet_warnings
= 0;
321 static const char *cpu_arch_name
= NULL
;
322 static const char *cpu_sub_arch_name
= NULL
;
324 /* CPU feature flags. */
325 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
327 /* If we have selected a cpu we are generating instructions for. */
328 static int cpu_arch_tune_set
= 0;
330 /* Cpu we are generating instructions for. */
331 static enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
333 /* CPU feature flags of cpu we are generating instructions for. */
334 static unsigned int cpu_arch_tune_flags
= 0;
336 /* CPU instruction set architecture used. */
337 static enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
339 /* CPU feature flags of instruction set architecture used. */
340 static unsigned int cpu_arch_isa_flags
= 0;
342 /* If set, conditional jumps are not automatically promoted to handle
343 larger than a byte offset. */
344 static unsigned int no_cond_jump_promotion
= 0;
346 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
347 static symbolS
*GOT_symbol
;
349 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
350 unsigned int x86_dwarf2_return_column
;
352 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
353 int x86_cie_data_alignment
;
355 /* Interface to relax_segment.
356 There are 3 major relax states for 386 jump insns because the
357 different types of jumps add different sizes to frags when we're
358 figuring out what sort of jump to choose to reach a given label. */
361 #define UNCOND_JUMP 0
363 #define COND_JUMP86 2
368 #define SMALL16 (SMALL | CODE16)
370 #define BIG16 (BIG | CODE16)
374 #define INLINE __inline__
380 #define ENCODE_RELAX_STATE(type, size) \
381 ((relax_substateT) (((type) << 2) | (size)))
382 #define TYPE_FROM_RELAX_STATE(s) \
384 #define DISP_SIZE_FROM_RELAX_STATE(s) \
385 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
387 /* This table is used by relax_frag to promote short jumps to long
388 ones where necessary. SMALL (short) jumps may be promoted to BIG
389 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
390 don't allow a short jump in a 32 bit code segment to be promoted to
391 a 16 bit offset jump because it's slower (requires data size
392 prefix), and doesn't work, unless the destination is in the bottom
393 64k of the code segment (The top 16 bits of eip are zeroed). */
395 const relax_typeS md_relax_table
[] =
398 1) most positive reach of this state,
399 2) most negative reach of this state,
400 3) how many bytes this mode will have in the variable part of the frag
401 4) which index into the table to try if we can't fit into this one. */
403 /* UNCOND_JUMP states. */
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
406 /* dword jmp adds 4 bytes to frag:
407 0 extra opcode bytes, 4 displacement bytes. */
409 /* word jmp adds 2 byte2 to frag:
410 0 extra opcode bytes, 2 displacement bytes. */
413 /* COND_JUMP states. */
414 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
415 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
416 /* dword conditionals adds 5 bytes to frag:
417 1 extra opcode byte, 4 displacement bytes. */
419 /* word conditionals add 3 bytes to frag:
420 1 extra opcode byte, 2 displacement bytes. */
423 /* COND_JUMP86 states. */
424 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
425 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
426 /* dword conditionals adds 5 bytes to frag:
427 1 extra opcode byte, 4 displacement bytes. */
429 /* word conditionals add 4 bytes to frag:
430 1 displacement byte and a 3 byte long branch insn. */
434 static const arch_entry cpu_arch
[] =
436 {"generic32", PROCESSOR_GENERIC32
,
437 Cpu186
|Cpu286
|Cpu386
},
438 {"generic64", PROCESSOR_GENERIC64
,
439 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
440 |CpuMMX2
|CpuSSE
|CpuSSE2
},
441 {"i8086", PROCESSOR_UNKNOWN
,
443 {"i186", PROCESSOR_UNKNOWN
,
445 {"i286", PROCESSOR_UNKNOWN
,
447 {"i386", PROCESSOR_GENERIC32
,
448 Cpu186
|Cpu286
|Cpu386
},
449 {"i486", PROCESSOR_I486
,
450 Cpu186
|Cpu286
|Cpu386
|Cpu486
},
451 {"i586", PROCESSOR_PENTIUM
,
452 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
453 {"i686", PROCESSOR_PENTIUMPRO
,
454 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
455 {"pentium", PROCESSOR_PENTIUM
,
456 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
457 {"pentiumpro",PROCESSOR_PENTIUMPRO
,
458 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
459 {"pentiumii", PROCESSOR_PENTIUMPRO
,
460 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
},
461 {"pentiumiii",PROCESSOR_PENTIUMPRO
,
462 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuMMX2
|CpuSSE
},
463 {"pentium4", PROCESSOR_PENTIUM4
,
464 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
465 |CpuMMX2
|CpuSSE
|CpuSSE2
},
466 {"prescott", PROCESSOR_NOCONA
,
467 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
468 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
469 {"nocona", PROCESSOR_NOCONA
,
470 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
471 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
472 {"yonah", PROCESSOR_CORE
,
473 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
474 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
475 {"core", PROCESSOR_CORE
,
476 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
477 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
478 {"merom", PROCESSOR_CORE2
,
479 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
480 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
},
481 {"core2", PROCESSOR_CORE2
,
482 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
483 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
},
485 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
},
486 {"k6_2", PROCESSOR_K6
,
487 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
488 {"athlon", PROCESSOR_ATHLON
,
489 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
490 |CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
491 {"sledgehammer", PROCESSOR_K8
,
492 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
493 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
494 {"opteron", PROCESSOR_K8
,
495 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
496 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
498 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
499 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
500 {"amdfam10", PROCESSOR_AMDFAM10
,
501 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuSledgehammer
502 |CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSE4a
504 {".mmx", PROCESSOR_UNKNOWN
,
506 {".sse", PROCESSOR_UNKNOWN
,
507 CpuMMX
|CpuMMX2
|CpuSSE
},
508 {".sse2", PROCESSOR_UNKNOWN
,
509 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
510 {".sse3", PROCESSOR_UNKNOWN
,
511 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
512 {".ssse3", PROCESSOR_UNKNOWN
,
513 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
},
514 {".3dnow", PROCESSOR_UNKNOWN
,
516 {".3dnowa", PROCESSOR_UNKNOWN
,
517 CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
518 {".padlock", PROCESSOR_UNKNOWN
,
520 {".pacifica", PROCESSOR_UNKNOWN
,
522 {".svme", PROCESSOR_UNKNOWN
,
524 {".sse4a", PROCESSOR_UNKNOWN
,
525 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSE4a
},
526 {".abm", PROCESSOR_UNKNOWN
,
530 const pseudo_typeS md_pseudo_table
[] =
532 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
533 {"align", s_align_bytes
, 0},
535 {"align", s_align_ptwo
, 0},
537 {"arch", set_cpu_arch
, 0},
541 {"ffloat", float_cons
, 'f'},
542 {"dfloat", float_cons
, 'd'},
543 {"tfloat", float_cons
, 'x'},
545 {"slong", signed_cons
, 4},
546 {"noopt", s_ignore
, 0},
547 {"optim", s_ignore
, 0},
548 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
549 {"code16", set_code_flag
, CODE_16BIT
},
550 {"code32", set_code_flag
, CODE_32BIT
},
551 {"code64", set_code_flag
, CODE_64BIT
},
552 {"intel_syntax", set_intel_syntax
, 1},
553 {"att_syntax", set_intel_syntax
, 0},
554 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
555 {"largecomm", handle_large_common
, 0},
557 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0},
558 {"loc", dwarf2_directive_loc
, 0},
559 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
562 {"secrel32", pe_directive_secrel
, 0},
567 /* For interface with expression (). */
568 extern char *input_line_pointer
;
570 /* Hash table for instruction mnemonic lookup. */
571 static struct hash_control
*op_hash
;
573 /* Hash table for register lookup. */
574 static struct hash_control
*reg_hash
;
577 i386_align_code (fragP
, count
)
581 /* Various efficient no-op patterns for aligning code labels.
582 Note: Don't try to assemble the instructions in the comments.
583 0L and 0w are not legal. */
584 static const char f32_1
[] =
586 static const char f32_2
[] =
587 {0x66,0x90}; /* xchg %ax,%ax */
588 static const char f32_3
[] =
589 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
590 static const char f32_4
[] =
591 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
592 static const char f32_5
[] =
594 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
595 static const char f32_6
[] =
596 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
597 static const char f32_7
[] =
598 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
599 static const char f32_8
[] =
601 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
602 static const char f32_9
[] =
603 {0x89,0xf6, /* movl %esi,%esi */
604 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
605 static const char f32_10
[] =
606 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
607 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
608 static const char f32_11
[] =
609 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
610 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
611 static const char f32_12
[] =
612 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
613 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
614 static const char f32_13
[] =
615 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
616 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
617 static const char f32_14
[] =
618 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
619 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
620 static const char f32_15
[] =
621 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
622 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
623 static const char f16_3
[] =
624 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
625 static const char f16_4
[] =
626 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
627 static const char f16_5
[] =
629 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
630 static const char f16_6
[] =
631 {0x89,0xf6, /* mov %si,%si */
632 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
633 static const char f16_7
[] =
634 {0x8d,0x74,0x00, /* lea 0(%si),%si */
635 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
636 static const char f16_8
[] =
637 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
638 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
639 static const char *const f32_patt
[] = {
640 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
641 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
643 static const char *const f16_patt
[] = {
644 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
645 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
648 static const char alt_3
[] =
650 /* nopl 0(%[re]ax) */
651 static const char alt_4
[] =
652 {0x0f,0x1f,0x40,0x00};
653 /* nopl 0(%[re]ax,%[re]ax,1) */
654 static const char alt_5
[] =
655 {0x0f,0x1f,0x44,0x00,0x00};
656 /* nopw 0(%[re]ax,%[re]ax,1) */
657 static const char alt_6
[] =
658 {0x66,0x0f,0x1f,0x44,0x00,0x00};
659 /* nopl 0L(%[re]ax) */
660 static const char alt_7
[] =
661 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
662 /* nopl 0L(%[re]ax,%[re]ax,1) */
663 static const char alt_8
[] =
664 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
665 /* nopw 0L(%[re]ax,%[re]ax,1) */
666 static const char alt_9
[] =
667 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
668 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
669 static const char alt_10
[] =
670 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
672 nopw %cs:0L(%[re]ax,%[re]ax,1) */
673 static const char alt_long_11
[] =
675 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
678 nopw %cs:0L(%[re]ax,%[re]ax,1) */
679 static const char alt_long_12
[] =
682 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
686 nopw %cs:0L(%[re]ax,%[re]ax,1) */
687 static const char alt_long_13
[] =
691 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
696 nopw %cs:0L(%[re]ax,%[re]ax,1) */
697 static const char alt_long_14
[] =
702 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
708 nopw %cs:0L(%[re]ax,%[re]ax,1) */
709 static const char alt_long_15
[] =
715 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
716 /* nopl 0(%[re]ax,%[re]ax,1)
717 nopw 0(%[re]ax,%[re]ax,1) */
718 static const char alt_short_11
[] =
719 {0x0f,0x1f,0x44,0x00,0x00,
720 0x66,0x0f,0x1f,0x44,0x00,0x00};
721 /* nopw 0(%[re]ax,%[re]ax,1)
722 nopw 0(%[re]ax,%[re]ax,1) */
723 static const char alt_short_12
[] =
724 {0x66,0x0f,0x1f,0x44,0x00,0x00,
725 0x66,0x0f,0x1f,0x44,0x00,0x00};
726 /* nopw 0(%[re]ax,%[re]ax,1)
728 static const char alt_short_13
[] =
729 {0x66,0x0f,0x1f,0x44,0x00,0x00,
730 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
733 static const char alt_short_14
[] =
734 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
735 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
737 nopl 0L(%[re]ax,%[re]ax,1) */
738 static const char alt_short_15
[] =
739 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
740 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
741 static const char *const alt_short_patt
[] = {
742 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
743 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
744 alt_short_14
, alt_short_15
746 static const char *const alt_long_patt
[] = {
747 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
748 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
749 alt_long_14
, alt_long_15
752 if (count
<= 0 || count
> 15)
755 /* We need to decide which NOP sequence to use for 32bit and
756 64bit. When -mtune= is used:
758 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
759 f32_patt will be used.
760 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with 0x66 prefix will be used.
761 3. For PROCESSOR_CORE2, alt_long_patt will be used.
762 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
763 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
764 and PROCESSOR_GENERIC64, alt_short_patt will be used.
766 When -mtune= isn't used, alt_short_patt will be used if
767 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
769 When -march= or .arch is used, we can't use anything beyond
770 cpu_arch_isa_flags. */
772 if (flag_code
== CODE_16BIT
)
774 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
775 f16_patt
[count
- 1], count
);
777 /* Adjust jump offset. */
778 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
780 else if (flag_code
== CODE_64BIT
&& cpu_arch_tune
== PROCESSOR_K8
)
783 int nnops
= (count
+ 3) / 4;
784 int len
= count
/ nnops
;
785 int remains
= count
- nnops
* len
;
788 /* The recommended way to pad 64bit code is to use NOPs preceded
789 by maximally four 0x66 prefixes. Balance the size of nops. */
790 for (i
= 0; i
< remains
; i
++)
792 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
793 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
796 for (; i
< nnops
; i
++)
798 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
799 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
805 const char *const *patt
= NULL
;
807 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
809 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
810 switch (cpu_arch_tune
)
812 case PROCESSOR_UNKNOWN
:
813 /* We use cpu_arch_isa_flags to check if we SHOULD
814 optimize for Cpu686. */
815 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
816 patt
= alt_short_patt
;
820 case PROCESSOR_CORE2
:
821 patt
= alt_long_patt
;
823 case PROCESSOR_PENTIUMPRO
:
824 case PROCESSOR_PENTIUM4
:
825 case PROCESSOR_NOCONA
:
828 case PROCESSOR_ATHLON
:
830 case PROCESSOR_GENERIC64
:
831 case PROCESSOR_AMDFAM10
:
832 patt
= alt_short_patt
;
835 case PROCESSOR_PENTIUM
:
836 case PROCESSOR_GENERIC32
:
843 switch (cpu_arch_tune
)
845 case PROCESSOR_UNKNOWN
:
846 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
847 PROCESSOR_UNKNOWN. */
852 case PROCESSOR_PENTIUM
:
853 case PROCESSOR_PENTIUMPRO
:
854 case PROCESSOR_PENTIUM4
:
855 case PROCESSOR_NOCONA
:
858 case PROCESSOR_ATHLON
:
860 case PROCESSOR_AMDFAM10
:
861 case PROCESSOR_GENERIC32
:
862 /* We use cpu_arch_isa_flags to check if we CAN optimize
864 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
865 patt
= alt_short_patt
;
869 case PROCESSOR_CORE2
:
870 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
871 patt
= alt_long_patt
;
875 case PROCESSOR_GENERIC64
:
876 patt
= alt_short_patt
;
881 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
882 patt
[count
- 1], count
);
884 fragP
->fr_var
= count
;
887 static INLINE
unsigned int
888 mode_from_disp_size (t
)
891 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
895 fits_in_signed_byte (num
)
898 return (num
>= -128) && (num
<= 127);
902 fits_in_unsigned_byte (num
)
905 return (num
& 0xff) == num
;
909 fits_in_unsigned_word (num
)
912 return (num
& 0xffff) == num
;
916 fits_in_signed_word (num
)
919 return (-32768 <= num
) && (num
<= 32767);
922 fits_in_signed_long (num
)
923 offsetT num ATTRIBUTE_UNUSED
;
928 return (!(((offsetT
) -1 << 31) & num
)
929 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
931 } /* fits_in_signed_long() */
933 fits_in_unsigned_long (num
)
934 offsetT num ATTRIBUTE_UNUSED
;
939 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
941 } /* fits_in_unsigned_long() */
944 smallest_imm_type (num
)
947 if (cpu_arch_flags
!= (Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
949 /* This code is disabled on the 486 because all the Imm1 forms
950 in the opcode table are slower on the i486. They're the
951 versions with the implicitly specified single-position
952 displacement, which has another syntax if you really want to
955 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
957 return (fits_in_signed_byte (num
)
958 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
959 : fits_in_unsigned_byte (num
)
960 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
961 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
962 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
963 : fits_in_signed_long (num
)
964 ? (Imm32
| Imm32S
| Imm64
)
965 : fits_in_unsigned_long (num
)
971 offset_in_range (val
, size
)
979 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
980 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
981 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
983 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
988 /* If BFD64, sign extend val. */
989 if (!use_rela_relocations
)
990 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
991 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
993 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
995 char buf1
[40], buf2
[40];
997 sprint_value (buf1
, val
);
998 sprint_value (buf2
, val
& mask
);
999 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1004 /* Returns 0 if attempting to add a prefix where one from the same
1005 class already exists, 1 if non rep/repne added, 2 if rep/repne
1009 unsigned int prefix
;
1014 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1015 && flag_code
== CODE_64BIT
)
1017 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_MODE64
)
1018 || ((i
.prefix
[REX_PREFIX
] & (REX_EXTX
| REX_EXTY
| REX_EXTZ
))
1019 && (prefix
& (REX_EXTX
| REX_EXTY
| REX_EXTZ
))))
1030 case CS_PREFIX_OPCODE
:
1031 case DS_PREFIX_OPCODE
:
1032 case ES_PREFIX_OPCODE
:
1033 case FS_PREFIX_OPCODE
:
1034 case GS_PREFIX_OPCODE
:
1035 case SS_PREFIX_OPCODE
:
1039 case REPNE_PREFIX_OPCODE
:
1040 case REPE_PREFIX_OPCODE
:
1043 case LOCK_PREFIX_OPCODE
:
1051 case ADDR_PREFIX_OPCODE
:
1055 case DATA_PREFIX_OPCODE
:
1059 if (i
.prefix
[q
] != 0)
1067 i
.prefix
[q
] |= prefix
;
1070 as_bad (_("same type of prefix used twice"));
1076 set_code_flag (value
)
1080 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
1081 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
1082 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
1084 as_bad (_("64bit mode not supported on this CPU."));
1086 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
1088 as_bad (_("32bit mode not supported on this CPU."));
1090 stackop_size
= '\0';
1094 set_16bit_gcc_code_flag (new_code_flag
)
1097 flag_code
= new_code_flag
;
1098 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
1099 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
1100 stackop_size
= LONG_MNEM_SUFFIX
;
1104 set_intel_syntax (syntax_flag
)
1107 /* Find out if register prefixing is specified. */
1108 int ask_naked_reg
= 0;
1111 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1113 char *string
= input_line_pointer
;
1114 int e
= get_symbol_end ();
1116 if (strcmp (string
, "prefix") == 0)
1118 else if (strcmp (string
, "noprefix") == 0)
1121 as_bad (_("bad argument to syntax directive."));
1122 *input_line_pointer
= e
;
1124 demand_empty_rest_of_line ();
1126 intel_syntax
= syntax_flag
;
1128 if (ask_naked_reg
== 0)
1129 allow_naked_reg
= (intel_syntax
1130 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1132 allow_naked_reg
= (ask_naked_reg
< 0);
1134 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1135 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1139 set_cpu_arch (dummy
)
1140 int dummy ATTRIBUTE_UNUSED
;
1144 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1146 char *string
= input_line_pointer
;
1147 int e
= get_symbol_end ();
1150 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1152 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1156 cpu_arch_name
= cpu_arch
[i
].name
;
1157 cpu_sub_arch_name
= NULL
;
1158 cpu_arch_flags
= (cpu_arch
[i
].flags
1159 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
1160 cpu_arch_isa
= cpu_arch
[i
].type
;
1161 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1162 if (!cpu_arch_tune_set
)
1164 cpu_arch_tune
= cpu_arch_isa
;
1165 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1169 if ((cpu_arch_flags
| cpu_arch
[i
].flags
) != cpu_arch_flags
)
1171 cpu_sub_arch_name
= cpu_arch
[i
].name
;
1172 cpu_arch_flags
|= cpu_arch
[i
].flags
;
1174 *input_line_pointer
= e
;
1175 demand_empty_rest_of_line ();
1179 if (i
>= ARRAY_SIZE (cpu_arch
))
1180 as_bad (_("no such architecture: `%s'"), string
);
1182 *input_line_pointer
= e
;
1185 as_bad (_("missing cpu architecture"));
1187 no_cond_jump_promotion
= 0;
1188 if (*input_line_pointer
== ','
1189 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
1191 char *string
= ++input_line_pointer
;
1192 int e
= get_symbol_end ();
1194 if (strcmp (string
, "nojumps") == 0)
1195 no_cond_jump_promotion
= 1;
1196 else if (strcmp (string
, "jumps") == 0)
1199 as_bad (_("no such architecture modifier: `%s'"), string
);
1201 *input_line_pointer
= e
;
1204 demand_empty_rest_of_line ();
1210 if (!strcmp (default_arch
, "x86_64"))
1211 return bfd_mach_x86_64
;
1212 else if (!strcmp (default_arch
, "i386"))
1213 return bfd_mach_i386_i386
;
1215 as_fatal (_("Unknown architecture"));
1221 const char *hash_err
;
1223 /* Initialize op_hash hash table. */
1224 op_hash
= hash_new ();
1227 const template *optab
;
1228 templates
*core_optab
;
1230 /* Setup for loop. */
1232 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1233 core_optab
->start
= optab
;
1238 if (optab
->name
== NULL
1239 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
1241 /* different name --> ship out current template list;
1242 add to hash table; & begin anew. */
1243 core_optab
->end
= optab
;
1244 hash_err
= hash_insert (op_hash
,
1249 as_fatal (_("Internal Error: Can't hash %s: %s"),
1253 if (optab
->name
== NULL
)
1255 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1256 core_optab
->start
= optab
;
1261 /* Initialize reg_hash hash table. */
1262 reg_hash
= hash_new ();
1264 const reg_entry
*regtab
;
1266 for (regtab
= i386_regtab
;
1267 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
1270 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
1272 as_fatal (_("Internal Error: Can't hash %s: %s"),
1278 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1283 for (c
= 0; c
< 256; c
++)
1288 mnemonic_chars
[c
] = c
;
1289 register_chars
[c
] = c
;
1290 operand_chars
[c
] = c
;
1292 else if (ISLOWER (c
))
1294 mnemonic_chars
[c
] = c
;
1295 register_chars
[c
] = c
;
1296 operand_chars
[c
] = c
;
1298 else if (ISUPPER (c
))
1300 mnemonic_chars
[c
] = TOLOWER (c
);
1301 register_chars
[c
] = mnemonic_chars
[c
];
1302 operand_chars
[c
] = c
;
1305 if (ISALPHA (c
) || ISDIGIT (c
))
1306 identifier_chars
[c
] = c
;
1309 identifier_chars
[c
] = c
;
1310 operand_chars
[c
] = c
;
1315 identifier_chars
['@'] = '@';
1318 identifier_chars
['?'] = '?';
1319 operand_chars
['?'] = '?';
1321 digit_chars
['-'] = '-';
1322 mnemonic_chars
['-'] = '-';
1323 identifier_chars
['_'] = '_';
1324 identifier_chars
['.'] = '.';
1326 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1327 operand_chars
[(unsigned char) *p
] = *p
;
1330 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1333 record_alignment (text_section
, 2);
1334 record_alignment (data_section
, 2);
1335 record_alignment (bss_section
, 2);
1339 if (flag_code
== CODE_64BIT
)
1341 x86_dwarf2_return_column
= 16;
1342 x86_cie_data_alignment
= -8;
1346 x86_dwarf2_return_column
= 8;
1347 x86_cie_data_alignment
= -4;
1352 i386_print_statistics (file
)
1355 hash_print_statistics (file
, "i386 opcode", op_hash
);
1356 hash_print_statistics (file
, "i386 register", reg_hash
);
1361 /* Debugging routines for md_assemble. */
1362 static void pi
PARAMS ((char *, i386_insn
*));
1363 static void pte
PARAMS ((template *));
1364 static void pt
PARAMS ((unsigned int));
1365 static void pe
PARAMS ((expressionS
*));
1366 static void ps
PARAMS ((symbolS
*));
1375 fprintf (stdout
, "%s: template ", line
);
1377 fprintf (stdout
, " address: base %s index %s scale %x\n",
1378 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1379 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1380 x
->log2_scale_factor
);
1381 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1382 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1383 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1384 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1385 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1386 (x
->rex
& REX_MODE64
) != 0,
1387 (x
->rex
& REX_EXTX
) != 0,
1388 (x
->rex
& REX_EXTY
) != 0,
1389 (x
->rex
& REX_EXTZ
) != 0);
1390 for (i
= 0; i
< x
->operands
; i
++)
1392 fprintf (stdout
, " #%d: ", i
+ 1);
1394 fprintf (stdout
, "\n");
1396 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1397 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1398 if (x
->types
[i
] & Imm
)
1400 if (x
->types
[i
] & Disp
)
1401 pe (x
->op
[i
].disps
);
1410 fprintf (stdout
, " %d operands ", t
->operands
);
1411 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1412 if (t
->extension_opcode
!= None
)
1413 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1414 if (t
->opcode_modifier
& D
)
1415 fprintf (stdout
, "D");
1416 if (t
->opcode_modifier
& W
)
1417 fprintf (stdout
, "W");
1418 fprintf (stdout
, "\n");
1419 for (i
= 0; i
< t
->operands
; i
++)
1421 fprintf (stdout
, " #%d type ", i
+ 1);
1422 pt (t
->operand_types
[i
]);
1423 fprintf (stdout
, "\n");
1431 fprintf (stdout
, " operation %d\n", e
->X_op
);
1432 fprintf (stdout
, " add_number %ld (%lx)\n",
1433 (long) e
->X_add_number
, (long) e
->X_add_number
);
1434 if (e
->X_add_symbol
)
1436 fprintf (stdout
, " add_symbol ");
1437 ps (e
->X_add_symbol
);
1438 fprintf (stdout
, "\n");
1442 fprintf (stdout
, " op_symbol ");
1443 ps (e
->X_op_symbol
);
1444 fprintf (stdout
, "\n");
1452 fprintf (stdout
, "%s type %s%s",
1454 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1455 segment_name (S_GET_SEGMENT (s
)));
1458 static struct type_name
1463 const type_names
[] =
1476 { BaseIndex
, "BaseIndex" },
1480 { Disp32S
, "d32s" },
1482 { InOutPortReg
, "InOutPortReg" },
1483 { ShiftCount
, "ShiftCount" },
1484 { Control
, "control reg" },
1485 { Test
, "test reg" },
1486 { Debug
, "debug reg" },
1487 { FloatReg
, "FReg" },
1488 { FloatAcc
, "FAcc" },
1492 { JumpAbsolute
, "Jump Absolute" },
1503 const struct type_name
*ty
;
1505 for (ty
= type_names
; ty
->mask
; ty
++)
1507 fprintf (stdout
, "%s, ", ty
->tname
);
1511 #endif /* DEBUG386 */
1513 static bfd_reloc_code_real_type
1514 reloc (unsigned int size
,
1517 bfd_reloc_code_real_type other
)
1519 if (other
!= NO_RELOC
)
1521 reloc_howto_type
*reloc
;
1526 case BFD_RELOC_X86_64_GOT32
:
1527 return BFD_RELOC_X86_64_GOT64
;
1529 case BFD_RELOC_X86_64_PLTOFF64
:
1530 return BFD_RELOC_X86_64_PLTOFF64
;
1532 case BFD_RELOC_X86_64_GOTPC32
:
1533 other
= BFD_RELOC_X86_64_GOTPC64
;
1535 case BFD_RELOC_X86_64_GOTPCREL
:
1536 other
= BFD_RELOC_X86_64_GOTPCREL64
;
1538 case BFD_RELOC_X86_64_TPOFF32
:
1539 other
= BFD_RELOC_X86_64_TPOFF64
;
1541 case BFD_RELOC_X86_64_DTPOFF32
:
1542 other
= BFD_RELOC_X86_64_DTPOFF64
;
1548 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1549 if (size
== 4 && flag_code
!= CODE_64BIT
)
1552 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
1554 as_bad (_("unknown relocation (%u)"), other
);
1555 else if (size
!= bfd_get_reloc_size (reloc
))
1556 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1557 bfd_get_reloc_size (reloc
),
1559 else if (pcrel
&& !reloc
->pc_relative
)
1560 as_bad (_("non-pc-relative relocation for pc-relative field"));
1561 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
1563 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
1565 as_bad (_("relocated field and relocation type differ in signedness"));
1574 as_bad (_("there are no unsigned pc-relative relocations"));
1577 case 1: return BFD_RELOC_8_PCREL
;
1578 case 2: return BFD_RELOC_16_PCREL
;
1579 case 4: return BFD_RELOC_32_PCREL
;
1580 case 8: return BFD_RELOC_64_PCREL
;
1582 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
1589 case 4: return BFD_RELOC_X86_64_32S
;
1594 case 1: return BFD_RELOC_8
;
1595 case 2: return BFD_RELOC_16
;
1596 case 4: return BFD_RELOC_32
;
1597 case 8: return BFD_RELOC_64
;
1599 as_bad (_("cannot do %s %u byte relocation"),
1600 sign
> 0 ? "signed" : "unsigned", size
);
1604 return BFD_RELOC_NONE
;
1607 /* Here we decide which fixups can be adjusted to make them relative to
1608 the beginning of the section instead of the symbol. Basically we need
1609 to make sure that the dynamic relocations are done correctly, so in
1610 some cases we force the original symbol to be used. */
1613 tc_i386_fix_adjustable (fixP
)
1614 fixS
*fixP ATTRIBUTE_UNUSED
;
1616 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1620 /* Don't adjust pc-relative references to merge sections in 64-bit
1622 if (use_rela_relocations
1623 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1627 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1628 and changed later by validate_fix. */
1629 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
1630 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
1633 /* adjust_reloc_syms doesn't know about the GOT. */
1634 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1635 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1636 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1637 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1638 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1639 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1640 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1641 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1642 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1643 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1644 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1645 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
1646 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
1647 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1648 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1649 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1650 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1651 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1652 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1653 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
1654 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1655 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1656 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
1657 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
1658 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
1659 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
1660 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1661 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1667 static int intel_float_operand
PARAMS ((const char *mnemonic
));
1670 intel_float_operand (mnemonic
)
1671 const char *mnemonic
;
1673 /* Note that the value returned is meaningful only for opcodes with (memory)
1674 operands, hence the code here is free to improperly handle opcodes that
1675 have no operands (for better performance and smaller code). */
1677 if (mnemonic
[0] != 'f')
1678 return 0; /* non-math */
1680 switch (mnemonic
[1])
1682 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1683 the fs segment override prefix not currently handled because no
1684 call path can make opcodes without operands get here */
1686 return 2 /* integer op */;
1688 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
1689 return 3; /* fldcw/fldenv */
1692 if (mnemonic
[2] != 'o' /* fnop */)
1693 return 3; /* non-waiting control op */
1696 if (mnemonic
[2] == 's')
1697 return 3; /* frstor/frstpm */
1700 if (mnemonic
[2] == 'a')
1701 return 3; /* fsave */
1702 if (mnemonic
[2] == 't')
1704 switch (mnemonic
[3])
1706 case 'c': /* fstcw */
1707 case 'd': /* fstdw */
1708 case 'e': /* fstenv */
1709 case 's': /* fsts[gw] */
1715 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
1716 return 0; /* fxsave/fxrstor are not really math ops */
1723 /* This is the guts of the machine-dependent assembler. LINE points to a
1724 machine dependent instruction. This function is supposed to emit
1725 the frags/bytes it assembles to. */
1732 char mnemonic
[MAX_MNEM_SIZE
];
1734 /* Initialize globals. */
1735 memset (&i
, '\0', sizeof (i
));
1736 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1737 i
.reloc
[j
] = NO_RELOC
;
1738 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1739 memset (im_expressions
, '\0', sizeof (im_expressions
));
1740 save_stack_p
= save_stack
;
1742 /* First parse an instruction mnemonic & call i386_operand for the operands.
1743 We assume that the scrubber has arranged it so that line[0] is the valid
1744 start of a (possibly prefixed) mnemonic. */
1746 line
= parse_insn (line
, mnemonic
);
1750 line
= parse_operands (line
, mnemonic
);
1754 /* The order of the immediates should be reversed
1755 for 2 immediates extrq and insertq instructions */
1756 if ((i
.imm_operands
== 2) &&
1757 ((strcmp (mnemonic
, "extrq") == 0)
1758 || (strcmp (mnemonic
, "insertq") == 0)))
1760 swap_imm_operands ();
1761 /* "extrq" and insertq" are the only two instructions whose operands
1762 have to be reversed even though they have two immediate operands.
1768 /* Now we've parsed the mnemonic into a set of templates, and have the
1769 operands at hand. */
1771 /* All intel opcodes have reversed operands except for "bound" and
1772 "enter". We also don't reverse intersegment "jmp" and "call"
1773 instructions with 2 immediate operands so that the immediate segment
1774 precedes the offset, as it does when in AT&T mode. */
1775 if (intel_syntax
&& i
.operands
> 1
1776 && (strcmp (mnemonic
, "bound") != 0)
1777 && (strcmp (mnemonic
, "invlpga") != 0)
1778 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1784 /* Don't optimize displacement for movabs since it only takes 64bit
1787 && (flag_code
!= CODE_64BIT
1788 || strcmp (mnemonic
, "movabs") != 0))
1791 /* Next, we find a template that matches the given insn,
1792 making sure the overlap of the given operands types is consistent
1793 with the template operand types. */
1795 if (!match_template ())
1800 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1802 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1803 i
.tm
.base_opcode
^= FloatR
;
1805 /* Zap movzx and movsx suffix. The suffix may have been set from
1806 "word ptr" or "byte ptr" on the source operand, but we'll use
1807 the suffix later to choose the destination register. */
1808 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1810 if (i
.reg_operands
< 2
1812 && (~i
.tm
.opcode_modifier
1819 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
1825 if (i
.tm
.opcode_modifier
& FWait
)
1826 if (!add_prefix (FWAIT_OPCODE
))
1829 /* Check string instruction segment overrides. */
1830 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1832 if (!check_string ())
1836 if (!process_suffix ())
1839 /* Make still unresolved immediate matches conform to size of immediate
1840 given in i.suffix. */
1841 if (!finalize_imm ())
1844 if (i
.types
[0] & Imm1
)
1845 i
.imm_operands
= 0; /* kludge for shift insns. */
1846 if (i
.types
[0] & ImplicitRegister
)
1848 if (i
.types
[1] & ImplicitRegister
)
1850 if (i
.types
[2] & ImplicitRegister
)
1853 if (i
.tm
.opcode_modifier
& ImmExt
)
1857 if ((i
.tm
.cpu_flags
& CpuSSE3
) && i
.operands
> 0)
1859 /* Streaming SIMD extensions 3 Instructions have the fixed
1860 operands with an opcode suffix which is coded in the same
1861 place as an 8-bit immediate field would be. Here we check
1862 those operands and remove them afterwards. */
1865 for (x
= 0; x
< i
.operands
; x
++)
1866 if (i
.op
[x
].regs
->reg_num
!= x
)
1867 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1868 i
.op
[x
].regs
->reg_name
, x
+ 1, i
.tm
.name
);
1872 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1873 opcode suffix which is coded in the same place as an 8-bit
1874 immediate field would be. Here we fake an 8-bit immediate
1875 operand from the opcode suffix stored in tm.extension_opcode. */
1877 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1879 exp
= &im_expressions
[i
.imm_operands
++];
1880 i
.op
[i
.operands
].imms
= exp
;
1881 i
.types
[i
.operands
++] = Imm8
;
1882 exp
->X_op
= O_constant
;
1883 exp
->X_add_number
= i
.tm
.extension_opcode
;
1884 i
.tm
.extension_opcode
= None
;
1887 /* For insns with operands there are more diddles to do to the opcode. */
1890 if (!process_operands ())
1893 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1895 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1896 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1899 /* Handle conversion of 'int $3' --> special int3 insn. */
1900 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1902 i
.tm
.base_opcode
= INT3_OPCODE
;
1906 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1907 && i
.op
[0].disps
->X_op
== O_constant
)
1909 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1910 the absolute address given by the constant. Since ix86 jumps and
1911 calls are pc relative, we need to generate a reloc. */
1912 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1913 i
.op
[0].disps
->X_op
= O_symbol
;
1916 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1917 i
.rex
|= REX_MODE64
;
1919 /* For 8 bit registers we need an empty rex prefix. Also if the
1920 instruction already has a prefix, we need to convert old
1921 registers to new ones. */
1923 if (((i
.types
[0] & Reg8
) != 0
1924 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1925 || ((i
.types
[1] & Reg8
) != 0
1926 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1927 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1932 i
.rex
|= REX_OPCODE
;
1933 for (x
= 0; x
< 2; x
++)
1935 /* Look for 8 bit operand that uses old registers. */
1936 if ((i
.types
[x
] & Reg8
) != 0
1937 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1939 /* In case it is "hi" register, give up. */
1940 if (i
.op
[x
].regs
->reg_num
> 3)
1941 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1942 i
.op
[x
].regs
->reg_name
);
1944 /* Otherwise it is equivalent to the extended register.
1945 Since the encoding doesn't change this is merely
1946 cosmetic cleanup for debug output. */
1948 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1954 add_prefix (REX_OPCODE
| i
.rex
);
1956 /* We are ready to output the insn. */
1961 parse_insn (line
, mnemonic
)
1966 char *token_start
= l
;
1971 /* Non-zero if we found a prefix only acceptable with string insns. */
1972 const char *expecting_string_instruction
= NULL
;
1977 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1980 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1982 as_bad (_("no such instruction: `%s'"), token_start
);
1987 if (!is_space_char (*l
)
1988 && *l
!= END_OF_INSN
1990 || (*l
!= PREFIX_SEPARATOR
1993 as_bad (_("invalid character %s in mnemonic"),
1994 output_invalid (*l
));
1997 if (token_start
== l
)
1999 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
2000 as_bad (_("expecting prefix; got nothing"));
2002 as_bad (_("expecting mnemonic; got nothing"));
2006 /* Look up instruction (or prefix) via hash table. */
2007 current_templates
= hash_find (op_hash
, mnemonic
);
2009 if (*l
!= END_OF_INSN
2010 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
2011 && current_templates
2012 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
2014 if (current_templates
->start
->cpu_flags
2015 & (flag_code
!= CODE_64BIT
? Cpu64
: CpuNo64
))
2017 as_bad ((flag_code
!= CODE_64BIT
2018 ? _("`%s' is only supported in 64-bit mode")
2019 : _("`%s' is not supported in 64-bit mode")),
2020 current_templates
->start
->name
);
2023 /* If we are in 16-bit mode, do not allow addr16 or data16.
2024 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2025 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
2026 && flag_code
!= CODE_64BIT
2027 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
2028 ^ (flag_code
== CODE_16BIT
)))
2030 as_bad (_("redundant %s prefix"),
2031 current_templates
->start
->name
);
2034 /* Add prefix, checking for repeated prefixes. */
2035 switch (add_prefix (current_templates
->start
->base_opcode
))
2040 expecting_string_instruction
= current_templates
->start
->name
;
2043 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2050 if (!current_templates
)
2052 /* See if we can get a match by trimming off a suffix. */
2055 case WORD_MNEM_SUFFIX
:
2056 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
2057 i
.suffix
= SHORT_MNEM_SUFFIX
;
2059 case BYTE_MNEM_SUFFIX
:
2060 case QWORD_MNEM_SUFFIX
:
2061 i
.suffix
= mnem_p
[-1];
2063 current_templates
= hash_find (op_hash
, mnemonic
);
2065 case SHORT_MNEM_SUFFIX
:
2066 case LONG_MNEM_SUFFIX
:
2069 i
.suffix
= mnem_p
[-1];
2071 current_templates
= hash_find (op_hash
, mnemonic
);
2079 if (intel_float_operand (mnemonic
) == 1)
2080 i
.suffix
= SHORT_MNEM_SUFFIX
;
2082 i
.suffix
= LONG_MNEM_SUFFIX
;
2084 current_templates
= hash_find (op_hash
, mnemonic
);
2088 if (!current_templates
)
2090 as_bad (_("no such instruction: `%s'"), token_start
);
2095 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
2097 /* Check for a branch hint. We allow ",pt" and ",pn" for
2098 predict taken and predict not taken respectively.
2099 I'm not sure that branch hints actually do anything on loop
2100 and jcxz insns (JumpByte) for current Pentium4 chips. They
2101 may work in the future and it doesn't hurt to accept them
2103 if (l
[0] == ',' && l
[1] == 'p')
2107 if (!add_prefix (DS_PREFIX_OPCODE
))
2111 else if (l
[2] == 'n')
2113 if (!add_prefix (CS_PREFIX_OPCODE
))
2119 /* Any other comma loses. */
2122 as_bad (_("invalid character %s in mnemonic"),
2123 output_invalid (*l
));
2127 /* Check if instruction is supported on specified architecture. */
2129 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2131 if (!((t
->cpu_flags
& ~(Cpu64
| CpuNo64
))
2132 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
))))
2134 if (!(t
->cpu_flags
& (flag_code
== CODE_64BIT
? CpuNo64
: Cpu64
)))
2137 if (!(supported
& 2))
2139 as_bad (flag_code
== CODE_64BIT
2140 ? _("`%s' is not supported in 64-bit mode")
2141 : _("`%s' is only supported in 64-bit mode"),
2142 current_templates
->start
->name
);
2145 if (!(supported
& 1))
2147 as_warn (_("`%s' is not supported on `%s%s'"),
2148 current_templates
->start
->name
,
2150 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
2152 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
2154 as_warn (_("use .code16 to ensure correct addressing mode"));
2157 /* Check for rep/repne without a string instruction. */
2158 if (expecting_string_instruction
)
2160 static templates override
;
2162 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2163 if (t
->opcode_modifier
& IsString
)
2165 if (t
>= current_templates
->end
)
2167 as_bad (_("expecting string instruction after `%s'"),
2168 expecting_string_instruction
);
2171 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
2172 if (!(t
->opcode_modifier
& IsString
))
2175 current_templates
= &override
;
2182 parse_operands (l
, mnemonic
)
2184 const char *mnemonic
;
2188 /* 1 if operand is pending after ','. */
2189 unsigned int expecting_operand
= 0;
2191 /* Non-zero if operand parens not balanced. */
2192 unsigned int paren_not_balanced
;
2194 while (*l
!= END_OF_INSN
)
2196 /* Skip optional white space before operand. */
2197 if (is_space_char (*l
))
2199 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
2201 as_bad (_("invalid character %s before operand %d"),
2202 output_invalid (*l
),
2206 token_start
= l
; /* after white space */
2207 paren_not_balanced
= 0;
2208 while (paren_not_balanced
|| *l
!= ',')
2210 if (*l
== END_OF_INSN
)
2212 if (paren_not_balanced
)
2215 as_bad (_("unbalanced parenthesis in operand %d."),
2218 as_bad (_("unbalanced brackets in operand %d."),
2223 break; /* we are done */
2225 else if (!is_operand_char (*l
) && !is_space_char (*l
))
2227 as_bad (_("invalid character %s in operand %d"),
2228 output_invalid (*l
),
2235 ++paren_not_balanced
;
2237 --paren_not_balanced
;
2242 ++paren_not_balanced
;
2244 --paren_not_balanced
;
2248 if (l
!= token_start
)
2249 { /* Yes, we've read in another operand. */
2250 unsigned int operand_ok
;
2251 this_operand
= i
.operands
++;
2252 if (i
.operands
> MAX_OPERANDS
)
2254 as_bad (_("spurious operands; (%d operands/instruction max)"),
2258 /* Now parse operand adding info to 'i' as we go along. */
2259 END_STRING_AND_SAVE (l
);
2263 i386_intel_operand (token_start
,
2264 intel_float_operand (mnemonic
));
2266 operand_ok
= i386_operand (token_start
);
2268 RESTORE_END_STRING (l
);
2274 if (expecting_operand
)
2276 expecting_operand_after_comma
:
2277 as_bad (_("expecting operand after ','; got nothing"));
2282 as_bad (_("expecting operand before ','; got nothing"));
2287 /* Now *l must be either ',' or END_OF_INSN. */
2290 if (*++l
== END_OF_INSN
)
2292 /* Just skip it, if it's \n complain. */
2293 goto expecting_operand_after_comma
;
2295 expecting_operand
= 1;
2302 swap_imm_operands ()
2304 union i386_op temp_op
;
2305 unsigned int temp_type
;
2306 enum bfd_reloc_code_real temp_reloc
;
2310 temp_type
= i
.types
[xchg2
];
2311 i
.types
[xchg2
] = i
.types
[xchg1
];
2312 i
.types
[xchg1
] = temp_type
;
2313 temp_op
= i
.op
[xchg2
];
2314 i
.op
[xchg2
] = i
.op
[xchg1
];
2315 i
.op
[xchg1
] = temp_op
;
2316 temp_reloc
= i
.reloc
[xchg2
];
2317 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
2318 i
.reloc
[xchg1
] = temp_reloc
;
2325 union i386_op temp_op
;
2326 unsigned int temp_type
;
2327 enum bfd_reloc_code_real temp_reloc
;
2331 if (i
.operands
== 4)
2332 /* There will be two exchanges in a 4 operand instruction.
2333 First exchange is the done inside this block.(1st and 4rth operand)
2334 The next exchange is done outside this block.(2nd and 3rd operand) */
2338 temp_type
= i
.types
[xchg2
];
2339 i
.types
[xchg2
] = i
.types
[xchg1
];
2340 i
.types
[xchg1
] = temp_type
;
2341 temp_op
= i
.op
[xchg2
];
2342 i
.op
[xchg2
] = i
.op
[xchg1
];
2343 i
.op
[xchg1
] = temp_op
;
2344 temp_reloc
= i
.reloc
[xchg2
];
2345 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
2346 i
.reloc
[xchg1
] = temp_reloc
;
2351 if (i
.operands
== 2)
2356 else if (i
.operands
== 3)
2361 temp_type
= i
.types
[xchg2
];
2362 i
.types
[xchg2
] = i
.types
[xchg1
];
2363 i
.types
[xchg1
] = temp_type
;
2364 temp_op
= i
.op
[xchg2
];
2365 i
.op
[xchg2
] = i
.op
[xchg1
];
2366 i
.op
[xchg1
] = temp_op
;
2367 temp_reloc
= i
.reloc
[xchg2
];
2368 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
2369 i
.reloc
[xchg1
] = temp_reloc
;
2371 if (i
.mem_operands
== 2)
2373 const seg_entry
*temp_seg
;
2374 temp_seg
= i
.seg
[0];
2375 i
.seg
[0] = i
.seg
[1];
2376 i
.seg
[1] = temp_seg
;
2380 /* Try to ensure constant immediates are represented in the smallest
2385 char guess_suffix
= 0;
2389 guess_suffix
= i
.suffix
;
2390 else if (i
.reg_operands
)
2392 /* Figure out a suffix from the last register operand specified.
2393 We can't do this properly yet, ie. excluding InOutPortReg,
2394 but the following works for instructions with immediates.
2395 In any case, we can't set i.suffix yet. */
2396 for (op
= i
.operands
; --op
>= 0;)
2397 if (i
.types
[op
] & Reg
)
2399 if (i
.types
[op
] & Reg8
)
2400 guess_suffix
= BYTE_MNEM_SUFFIX
;
2401 else if (i
.types
[op
] & Reg16
)
2402 guess_suffix
= WORD_MNEM_SUFFIX
;
2403 else if (i
.types
[op
] & Reg32
)
2404 guess_suffix
= LONG_MNEM_SUFFIX
;
2405 else if (i
.types
[op
] & Reg64
)
2406 guess_suffix
= QWORD_MNEM_SUFFIX
;
2410 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
2411 guess_suffix
= WORD_MNEM_SUFFIX
;
2413 for (op
= i
.operands
; --op
>= 0;)
2414 if (i
.types
[op
] & Imm
)
2416 switch (i
.op
[op
].imms
->X_op
)
2419 /* If a suffix is given, this operand may be shortened. */
2420 switch (guess_suffix
)
2422 case LONG_MNEM_SUFFIX
:
2423 i
.types
[op
] |= Imm32
| Imm64
;
2425 case WORD_MNEM_SUFFIX
:
2426 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
2428 case BYTE_MNEM_SUFFIX
:
2429 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
2433 /* If this operand is at most 16 bits, convert it
2434 to a signed 16 bit number before trying to see
2435 whether it will fit in an even smaller size.
2436 This allows a 16-bit operand such as $0xffe0 to
2437 be recognised as within Imm8S range. */
2438 if ((i
.types
[op
] & Imm16
)
2439 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
2441 i
.op
[op
].imms
->X_add_number
=
2442 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2444 if ((i
.types
[op
] & Imm32
)
2445 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2448 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2449 ^ ((offsetT
) 1 << 31))
2450 - ((offsetT
) 1 << 31));
2452 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
2454 /* We must avoid matching of Imm32 templates when 64bit
2455 only immediate is available. */
2456 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2457 i
.types
[op
] &= ~Imm32
;
2464 /* Symbols and expressions. */
2466 /* Convert symbolic operand to proper sizes for matching, but don't
2467 prevent matching a set of insns that only supports sizes other
2468 than those matching the insn suffix. */
2470 unsigned int mask
, allowed
= 0;
2473 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2474 allowed
|= t
->operand_types
[op
];
2475 switch (guess_suffix
)
2477 case QWORD_MNEM_SUFFIX
:
2478 mask
= Imm64
| Imm32S
;
2480 case LONG_MNEM_SUFFIX
:
2483 case WORD_MNEM_SUFFIX
:
2486 case BYTE_MNEM_SUFFIX
:
2494 i
.types
[op
] &= mask
;
2501 /* Try to use the smallest displacement type too. */
2507 for (op
= i
.operands
; --op
>= 0;)
2508 if (i
.types
[op
] & Disp
)
2510 if (i
.op
[op
].disps
->X_op
== O_constant
)
2512 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
2514 if ((i
.types
[op
] & Disp16
)
2515 && (disp
& ~(offsetT
) 0xffff) == 0)
2517 /* If this operand is at most 16 bits, convert
2518 to a signed 16 bit number and don't use 64bit
2520 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
2521 i
.types
[op
] &= ~Disp64
;
2523 if ((i
.types
[op
] & Disp32
)
2524 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
2526 /* If this operand is at most 32 bits, convert
2527 to a signed 32 bit number and don't use 64bit
2529 disp
&= (((offsetT
) 2 << 31) - 1);
2530 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
2531 i
.types
[op
] &= ~Disp64
;
2533 if (!disp
&& (i
.types
[op
] & BaseIndex
))
2535 i
.types
[op
] &= ~Disp
;
2539 else if (flag_code
== CODE_64BIT
)
2541 if (fits_in_signed_long (disp
))
2543 i
.types
[op
] &= ~Disp64
;
2544 i
.types
[op
] |= Disp32S
;
2546 if (fits_in_unsigned_long (disp
))
2547 i
.types
[op
] |= Disp32
;
2549 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
2550 && fits_in_signed_byte (disp
))
2551 i
.types
[op
] |= Disp8
;
2553 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
2554 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
2556 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
2557 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
2558 i
.types
[op
] &= ~Disp
;
2561 /* We only support 64bit displacement on constants. */
2562 i
.types
[op
] &= ~Disp64
;
2569 /* Points to template once we've found it. */
2571 unsigned int overlap0
, overlap1
, overlap2
, overlap3
;
2572 unsigned int found_reverse_match
;
2574 unsigned int operand_types
[MAX_OPERANDS
];
2575 int addr_prefix_disp
;
2578 #if MAX_OPERANDS != 4
2579 # error "MAX_OPERANDS must be 4."
2582 #define MATCH(overlap, given, template) \
2583 ((overlap & ~JumpAbsolute) \
2584 && (((given) & (BaseIndex | JumpAbsolute)) \
2585 == ((overlap) & (BaseIndex | JumpAbsolute))))
2587 /* If given types r0 and r1 are registers they must be of the same type
2588 unless the expected operand type register overlap is null.
2589 Note that Acc in a template matches every size of reg. */
2590 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2591 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2592 || ((g0) & Reg) == ((g1) & Reg) \
2593 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2599 found_reverse_match
= 0;
2600 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2601 operand_types
[j
] = 0;
2602 addr_prefix_disp
= -1;
2603 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
2605 : (i
.suffix
== WORD_MNEM_SUFFIX
2607 : (i
.suffix
== SHORT_MNEM_SUFFIX
2609 : (i
.suffix
== LONG_MNEM_SUFFIX
2611 : (i
.suffix
== QWORD_MNEM_SUFFIX
2613 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
2614 ? No_xSuf
: 0))))));
2616 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
2618 addr_prefix_disp
= -1;
2620 /* Must have right number of operands. */
2621 if (i
.operands
!= t
->operands
)
2624 /* Check the suffix, except for some instructions in intel mode. */
2625 if ((t
->opcode_modifier
& suffix_check
)
2627 && (t
->opcode_modifier
& IgnoreSize
)))
2630 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2631 operand_types
[j
] = t
->operand_types
[j
];
2633 /* In general, don't allow 64-bit operands in 32-bit mode. */
2634 if (i
.suffix
== QWORD_MNEM_SUFFIX
2635 && flag_code
!= CODE_64BIT
2637 ? (!(t
->opcode_modifier
& IgnoreSize
)
2638 && !intel_float_operand (t
->name
))
2639 : intel_float_operand (t
->name
) != 2)
2640 && (!(operand_types
[0] & (RegMMX
| RegXMM
))
2641 || !(operand_types
[t
->operands
> 1] & (RegMMX
| RegXMM
)))
2642 && (t
->base_opcode
!= 0x0fc7
2643 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
2646 /* Do not verify operands when there are none. */
2647 else if (!t
->operands
)
2649 if (t
->cpu_flags
& ~cpu_arch_flags
)
2651 /* We've found a match; break out of loop. */
2655 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2656 into Disp32/Disp16/Disp32 operand. */
2657 if (i
.prefix
[ADDR_PREFIX
] != 0)
2659 unsigned int DispOn
= 0, DispOff
= 0;
2677 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2679 /* There should be only one Disp operand. */
2680 if ((operand_types
[j
] & DispOff
))
2682 addr_prefix_disp
= j
;
2683 operand_types
[j
] |= DispOn
;
2684 operand_types
[j
] &= ~DispOff
;
2690 overlap0
= i
.types
[0] & operand_types
[0];
2691 switch (t
->operands
)
2694 if (!MATCH (overlap0
, i
.types
[0], operand_types
[0]))
2700 overlap1
= i
.types
[1] & operand_types
[1];
2701 if (!MATCH (overlap0
, i
.types
[0], operand_types
[0])
2702 || !MATCH (overlap1
, i
.types
[1], operand_types
[1])
2703 /* monitor in SSE3 is a very special case. The first
2704 register and the second register may have different
2706 || !((t
->base_opcode
== 0x0f01
2707 && t
->extension_opcode
== 0xc8)
2708 || CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2710 overlap1
, i
.types
[1],
2713 /* Check if other direction is valid ... */
2714 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2717 /* Try reversing direction of operands. */
2718 overlap0
= i
.types
[0] & operand_types
[1];
2719 overlap1
= i
.types
[1] & operand_types
[0];
2720 if (!MATCH (overlap0
, i
.types
[0], operand_types
[1])
2721 || !MATCH (overlap1
, i
.types
[1], operand_types
[0])
2722 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2724 overlap1
, i
.types
[1],
2727 /* Does not match either direction. */
2730 /* found_reverse_match holds which of D or FloatDR
2732 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2736 /* Found a forward 2 operand match here. */
2737 switch (t
->operands
)
2740 overlap3
= i
.types
[3] & operand_types
[3];
2742 overlap2
= i
.types
[2] & operand_types
[2];
2746 switch (t
->operands
)
2749 if (!MATCH (overlap3
, i
.types
[3], operand_types
[3])
2750 || !CONSISTENT_REGISTER_MATCH (overlap2
,
2758 /* Here we make use of the fact that there are no
2759 reverse match 3 operand instructions, and all 3
2760 operand instructions only need to be checked for
2761 register consistency between operands 2 and 3. */
2762 if (!MATCH (overlap2
, i
.types
[2], operand_types
[2])
2763 || !CONSISTENT_REGISTER_MATCH (overlap1
,
2773 /* Found either forward/reverse 2, 3 or 4 operand match here:
2774 slip through to break. */
2776 if (t
->cpu_flags
& ~cpu_arch_flags
)
2778 found_reverse_match
= 0;
2781 /* We've found a match; break out of loop. */
2785 if (t
== current_templates
->end
)
2787 /* We found no match. */
2788 as_bad (_("suffix or operands invalid for `%s'"),
2789 current_templates
->start
->name
);
2793 if (!quiet_warnings
)
2796 && ((i
.types
[0] & JumpAbsolute
)
2797 != (operand_types
[0] & JumpAbsolute
)))
2799 as_warn (_("indirect %s without `*'"), t
->name
);
2802 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2803 == (IsPrefix
| IgnoreSize
))
2805 /* Warn them that a data or address size prefix doesn't
2806 affect assembly of the next line of code. */
2807 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2811 /* Copy the template we found. */
2814 if (addr_prefix_disp
!= -1)
2815 i
.tm
.operand_types
[addr_prefix_disp
]
2816 = operand_types
[addr_prefix_disp
];
2818 if (found_reverse_match
)
2820 /* If we found a reverse match we must alter the opcode
2821 direction bit. found_reverse_match holds bits to change
2822 (different for int & float insns). */
2824 i
.tm
.base_opcode
^= found_reverse_match
;
2826 i
.tm
.operand_types
[0] = operand_types
[1];
2827 i
.tm
.operand_types
[1] = operand_types
[0];
2836 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2837 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2839 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2841 as_bad (_("`%s' operand %d must use `%%es' segment"),
2846 /* There's only ever one segment override allowed per instruction.
2847 This instruction possibly has a legal segment override on the
2848 second operand, so copy the segment to where non-string
2849 instructions store it, allowing common code. */
2850 i
.seg
[0] = i
.seg
[1];
2852 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2854 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2856 as_bad (_("`%s' operand %d must use `%%es' segment"),
2866 process_suffix (void)
2868 /* If matched instruction specifies an explicit instruction mnemonic
2870 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2872 if (i
.tm
.opcode_modifier
& Size16
)
2873 i
.suffix
= WORD_MNEM_SUFFIX
;
2874 else if (i
.tm
.opcode_modifier
& Size64
)
2875 i
.suffix
= QWORD_MNEM_SUFFIX
;
2877 i
.suffix
= LONG_MNEM_SUFFIX
;
2879 else if (i
.reg_operands
)
2881 /* If there's no instruction mnemonic suffix we try to invent one
2882 based on register operands. */
2885 /* We take i.suffix from the last register operand specified,
2886 Destination register type is more significant than source
2890 for (op
= i
.operands
; --op
>= 0;)
2891 if ((i
.types
[op
] & Reg
)
2892 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2894 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2895 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2896 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2901 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2903 if (!check_byte_reg ())
2906 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2908 if (!check_long_reg ())
2911 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2913 if (!check_qword_reg ())
2916 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2918 if (!check_word_reg ())
2921 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2922 /* Do nothing if the instruction is going to ignore the prefix. */
2927 else if ((i
.tm
.opcode_modifier
& DefaultSize
)
2929 /* exclude fldenv/frstor/fsave/fstenv */
2930 && (i
.tm
.opcode_modifier
& No_sSuf
))
2932 i
.suffix
= stackop_size
;
2934 else if (intel_syntax
2936 && ((i
.tm
.operand_types
[0] & JumpAbsolute
)
2937 || (i
.tm
.opcode_modifier
& (JumpByte
|JumpInterSegment
))
2938 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
2939 && i
.tm
.extension_opcode
<= 3)))
2944 if (!(i
.tm
.opcode_modifier
& No_qSuf
))
2946 i
.suffix
= QWORD_MNEM_SUFFIX
;
2950 if (!(i
.tm
.opcode_modifier
& No_lSuf
))
2951 i
.suffix
= LONG_MNEM_SUFFIX
;
2954 if (!(i
.tm
.opcode_modifier
& No_wSuf
))
2955 i
.suffix
= WORD_MNEM_SUFFIX
;
2964 if (i
.tm
.opcode_modifier
& W
)
2966 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2972 unsigned int suffixes
= (~i
.tm
.opcode_modifier
2980 if ((i
.tm
.opcode_modifier
& W
)
2981 || ((suffixes
& (suffixes
- 1))
2982 && !(i
.tm
.opcode_modifier
& (DefaultSize
| IgnoreSize
))))
2984 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2990 /* Change the opcode based on the operand size given by i.suffix;
2991 We don't need to change things for byte insns. */
2993 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2995 /* It's not a byte, select word/dword operation. */
2996 if (i
.tm
.opcode_modifier
& W
)
2998 if (i
.tm
.opcode_modifier
& ShortForm
)
2999 i
.tm
.base_opcode
|= 8;
3001 i
.tm
.base_opcode
|= 1;
3004 /* Now select between word & dword operations via the operand
3005 size prefix, except for instructions that will ignore this
3007 if (i
.tm
.base_opcode
== 0x0f01 && i
.tm
.extension_opcode
== 0xc8)
3009 /* monitor in SSE3 is a very special case. The default size
3010 of AX is the size of mode. The address size override
3011 prefix will change the size of AX. */
3012 if (i
.op
->regs
[0].reg_type
&
3013 (flag_code
== CODE_32BIT
? Reg16
: Reg32
))
3014 if (!add_prefix (ADDR_PREFIX_OPCODE
))
3017 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
3018 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
3019 && !(i
.tm
.opcode_modifier
& (IgnoreSize
| FloatMF
))
3020 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
3021 || (flag_code
== CODE_64BIT
3022 && (i
.tm
.opcode_modifier
& JumpByte
))))
3024 unsigned int prefix
= DATA_PREFIX_OPCODE
;
3026 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
3027 prefix
= ADDR_PREFIX_OPCODE
;
3029 if (!add_prefix (prefix
))
3033 /* Set mode64 for an operand. */
3034 if (i
.suffix
== QWORD_MNEM_SUFFIX
3035 && flag_code
== CODE_64BIT
3036 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
3038 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3041 || i
.types
[0] != (Acc
| Reg64
)
3042 || i
.types
[1] != (Acc
| Reg64
)
3043 || strcmp (i
.tm
.name
, "xchg") != 0)
3044 i
.rex
|= REX_MODE64
;
3047 /* Size floating point instruction. */
3048 if (i
.suffix
== LONG_MNEM_SUFFIX
)
3049 if (i
.tm
.opcode_modifier
& FloatMF
)
3050 i
.tm
.base_opcode
^= 4;
3057 check_byte_reg (void)
3061 for (op
= i
.operands
; --op
>= 0;)
3063 /* If this is an eight bit register, it's OK. If it's the 16 or
3064 32 bit version of an eight bit register, we will just use the
3065 low portion, and that's OK too. */
3066 if (i
.types
[op
] & Reg8
)
3069 /* movzx and movsx should not generate this warning. */
3071 && (i
.tm
.base_opcode
== 0xfb7
3072 || i
.tm
.base_opcode
== 0xfb6
3073 || i
.tm
.base_opcode
== 0x63
3074 || i
.tm
.base_opcode
== 0xfbe
3075 || i
.tm
.base_opcode
== 0xfbf))
3078 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4)
3080 /* Prohibit these changes in the 64bit mode, since the
3081 lowering is more complicated. */
3082 if (flag_code
== CODE_64BIT
3083 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
3085 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3086 i
.op
[op
].regs
->reg_name
,
3090 #if REGISTER_WARNINGS
3092 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
3093 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3094 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
3095 ? REGNAM_AL
- REGNAM_AX
3096 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
3097 i
.op
[op
].regs
->reg_name
,
3102 /* Any other register is bad. */
3103 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
3105 | Control
| Debug
| Test
3106 | FloatReg
| FloatAcc
))
3108 as_bad (_("`%%%s' not allowed with `%s%c'"),
3109 i
.op
[op
].regs
->reg_name
,
3123 for (op
= i
.operands
; --op
>= 0;)
3124 /* Reject eight bit registers, except where the template requires
3125 them. (eg. movzb) */
3126 if ((i
.types
[op
] & Reg8
) != 0
3127 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3129 as_bad (_("`%%%s' not allowed with `%s%c'"),
3130 i
.op
[op
].regs
->reg_name
,
3135 /* Warn if the e prefix on a general reg is missing. */
3136 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3137 && (i
.types
[op
] & Reg16
) != 0
3138 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3140 /* Prohibit these changes in the 64bit mode, since the
3141 lowering is more complicated. */
3142 if (flag_code
== CODE_64BIT
)
3144 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3145 i
.op
[op
].regs
->reg_name
,
3149 #if REGISTER_WARNINGS
3151 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3152 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
3153 i
.op
[op
].regs
->reg_name
,
3157 /* Warn if the r prefix on a general reg is missing. */
3158 else if ((i
.types
[op
] & Reg64
) != 0
3159 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3161 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3162 i
.op
[op
].regs
->reg_name
,
3174 for (op
= i
.operands
; --op
>= 0; )
3175 /* Reject eight bit registers, except where the template requires
3176 them. (eg. movzb) */
3177 if ((i
.types
[op
] & Reg8
) != 0
3178 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3180 as_bad (_("`%%%s' not allowed with `%s%c'"),
3181 i
.op
[op
].regs
->reg_name
,
3186 /* Warn if the e prefix on a general reg is missing. */
3187 else if (((i
.types
[op
] & Reg16
) != 0
3188 || (i
.types
[op
] & Reg32
) != 0)
3189 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3191 /* Prohibit these changes in the 64bit mode, since the
3192 lowering is more complicated. */
3193 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3194 i
.op
[op
].regs
->reg_name
,
3205 for (op
= i
.operands
; --op
>= 0;)
3206 /* Reject eight bit registers, except where the template requires
3207 them. (eg. movzb) */
3208 if ((i
.types
[op
] & Reg8
) != 0
3209 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3211 as_bad (_("`%%%s' not allowed with `%s%c'"),
3212 i
.op
[op
].regs
->reg_name
,
3217 /* Warn if the e prefix on a general reg is present. */
3218 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3219 && (i
.types
[op
] & Reg32
) != 0
3220 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
3222 /* Prohibit these changes in the 64bit mode, since the
3223 lowering is more complicated. */
3224 if (flag_code
== CODE_64BIT
)
3226 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3227 i
.op
[op
].regs
->reg_name
,
3232 #if REGISTER_WARNINGS
3233 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3234 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
3235 i
.op
[op
].regs
->reg_name
,
3245 unsigned int overlap0
, overlap1
, overlap2
;
3247 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
3248 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
))
3249 && overlap0
!= Imm8
&& overlap0
!= Imm8S
3250 && overlap0
!= Imm16
&& overlap0
!= Imm32S
3251 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
3255 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
3257 : (i
.suffix
== WORD_MNEM_SUFFIX
3259 : (i
.suffix
== QWORD_MNEM_SUFFIX
3263 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
3264 || overlap0
== (Imm16
| Imm32
)
3265 || overlap0
== (Imm16
| Imm32S
))
3267 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
3270 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
3271 && overlap0
!= Imm16
&& overlap0
!= Imm32S
3272 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
3274 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
3278 i
.types
[0] = overlap0
;
3280 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
3281 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
| Imm64
))
3282 && overlap1
!= Imm8
&& overlap1
!= Imm8S
3283 && overlap1
!= Imm16
&& overlap1
!= Imm32S
3284 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
3288 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
3290 : (i
.suffix
== WORD_MNEM_SUFFIX
3292 : (i
.suffix
== QWORD_MNEM_SUFFIX
3296 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
3297 || overlap1
== (Imm16
| Imm32
)
3298 || overlap1
== (Imm16
| Imm32S
))
3300 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
3303 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
3304 && overlap1
!= Imm16
&& overlap1
!= Imm32S
3305 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
3307 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
3311 i
.types
[1] = overlap1
;
3313 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
3314 assert ((overlap2
& Imm
) == 0);
3315 i
.types
[2] = overlap2
;
3323 /* Default segment register this instruction will use for memory
3324 accesses. 0 means unknown. This is only for optimizing out
3325 unnecessary segment overrides. */
3326 const seg_entry
*default_seg
= 0;
3328 /* The imul $imm, %reg instruction is converted into
3329 imul $imm, %reg, %reg, and the clr %reg instruction
3330 is converted into xor %reg, %reg. */
3331 if (i
.tm
.opcode_modifier
& regKludge
)
3333 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
3334 /* Pretend we saw the extra register operand. */
3335 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
3336 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
3337 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
3341 if (i
.tm
.opcode_modifier
& ShortForm
)
3343 /* The register or float register operand is in operand 0 or 1. */
3344 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
3345 /* Register goes in low 3 bits of opcode. */
3346 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
3347 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3349 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
3351 /* Warn about some common errors, but press on regardless.
3352 The first case can be generated by gcc (<= 2.8.1). */
3353 if (i
.operands
== 2)
3355 /* Reversed arguments on faddp, fsubp, etc. */
3356 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
3357 i
.op
[1].regs
->reg_name
,
3358 i
.op
[0].regs
->reg_name
);
3362 /* Extraneous `l' suffix on fp insn. */
3363 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
3364 i
.op
[0].regs
->reg_name
);
3368 else if (i
.tm
.opcode_modifier
& Modrm
)
3370 /* The opcode is completed (modulo i.tm.extension_opcode which
3371 must be put into the modrm byte). Now, we make the modrm and
3372 index base bytes based on all the info we've collected. */
3374 default_seg
= build_modrm_byte ();
3376 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
3378 if (i
.tm
.base_opcode
== POP_SEG_SHORT
3379 && i
.op
[0].regs
->reg_num
== 1)
3381 as_bad (_("you can't `pop %%cs'"));
3384 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
3385 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
3388 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
3392 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
3394 /* For the string instructions that allow a segment override
3395 on one of their operands, the default segment is ds. */
3399 if ((i
.tm
.base_opcode
== 0x8d /* lea */
3400 || (i
.tm
.cpu_flags
& CpuSVME
))
3401 && i
.seg
[0] && !quiet_warnings
)
3402 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
3404 /* If a segment was explicitly specified, and the specified segment
3405 is not the default, use an opcode prefix to select it. If we
3406 never figured out what the default segment is, then default_seg
3407 will be zero at this point, and the specified segment prefix will
3409 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
3411 if (!add_prefix (i
.seg
[0]->seg_prefix
))
3417 static const seg_entry
*
3420 const seg_entry
*default_seg
= 0;
3422 /* i.reg_operands MUST be the number of real register operands;
3423 implicit registers do not count. */
3424 if (i
.reg_operands
== 2)
3426 unsigned int source
, dest
;
3427 source
= ((i
.types
[0]
3428 & (Reg
| RegMMX
| RegXMM
3430 | Control
| Debug
| Test
))
3433 /* In 4 operands instructions with 2 immediate operands, the first two are immediate
3434 bytes and hence source operand will be in the next byte after the immediates */
3435 if ((i
.operands
== 4)&&(i
.imm_operands
=2)) source
++;
3439 /* One of the register operands will be encoded in the i.tm.reg
3440 field, the other in the combined i.tm.mode and i.tm.regmem
3441 fields. If no form of this instruction supports a memory
3442 destination operand, then we assume the source operand may
3443 sometimes be a memory operand and so we need to store the
3444 destination in the i.rm.reg field. */
3445 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
3447 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
3448 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
3449 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
3451 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
3456 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
3457 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
3458 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
3460 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
3463 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_EXTX
| REX_EXTZ
)))
3465 if (!((i
.types
[0] | i
.types
[1]) & Control
))
3467 i
.rex
&= ~(REX_EXTX
| REX_EXTZ
);
3468 add_prefix (LOCK_PREFIX_OPCODE
);
3472 { /* If it's not 2 reg operands... */
3475 unsigned int fake_zero_displacement
= 0;
3476 unsigned int op
= ((i
.types
[0] & AnyMem
)
3478 : (i
.types
[1] & AnyMem
) ? 1 : 2);
3482 if (i
.base_reg
== 0)
3485 if (!i
.disp_operands
)
3486 fake_zero_displacement
= 1;
3487 if (i
.index_reg
== 0)
3489 /* Operand is just <disp> */
3490 if (flag_code
== CODE_64BIT
)
3492 /* 64bit mode overwrites the 32bit absolute
3493 addressing by RIP relative addressing and
3494 absolute addressing is encoded by one of the
3495 redundant SIB forms. */
3496 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3497 i
.sib
.base
= NO_BASE_REGISTER
;
3498 i
.sib
.index
= NO_INDEX_REGISTER
;
3499 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0) ? Disp32S
: Disp32
);
3501 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3503 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
3504 i
.types
[op
] = Disp16
;
3508 i
.rm
.regmem
= NO_BASE_REGISTER
;
3509 i
.types
[op
] = Disp32
;
3512 else /* !i.base_reg && i.index_reg */
3514 i
.sib
.index
= i
.index_reg
->reg_num
;
3515 i
.sib
.base
= NO_BASE_REGISTER
;
3516 i
.sib
.scale
= i
.log2_scale_factor
;
3517 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3518 i
.types
[op
] &= ~Disp
;
3519 if (flag_code
!= CODE_64BIT
)
3520 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
3522 i
.types
[op
] |= Disp32S
;
3523 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3527 /* RIP addressing for 64bit mode. */
3528 else if (i
.base_reg
->reg_type
== BaseIndex
)
3530 i
.rm
.regmem
= NO_BASE_REGISTER
;
3531 i
.types
[op
] &= ~ Disp
;
3532 i
.types
[op
] |= Disp32S
;
3533 i
.flags
[op
] |= Operand_PCrel
;
3534 if (! i
.disp_operands
)
3535 fake_zero_displacement
= 1;
3537 else if (i
.base_reg
->reg_type
& Reg16
)
3539 switch (i
.base_reg
->reg_num
)
3542 if (i
.index_reg
== 0)
3544 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3545 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
3549 if (i
.index_reg
== 0)
3552 if ((i
.types
[op
] & Disp
) == 0)
3554 /* fake (%bp) into 0(%bp) */
3555 i
.types
[op
] |= Disp8
;
3556 fake_zero_displacement
= 1;
3559 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3560 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
3562 default: /* (%si) -> 4 or (%di) -> 5 */
3563 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
3565 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3567 else /* i.base_reg and 32/64 bit mode */
3569 if (flag_code
== CODE_64BIT
3570 && (i
.types
[op
] & Disp
))
3571 i
.types
[op
] = (i
.types
[op
] & Disp8
) | (i
.prefix
[ADDR_PREFIX
] == 0 ? Disp32S
: Disp32
);
3573 i
.rm
.regmem
= i
.base_reg
->reg_num
;
3574 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
3576 i
.sib
.base
= i
.base_reg
->reg_num
;
3577 /* x86-64 ignores REX prefix bit here to avoid decoder
3579 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
3582 if (i
.disp_operands
== 0)
3584 fake_zero_displacement
= 1;
3585 i
.types
[op
] |= Disp8
;
3588 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
3592 i
.sib
.scale
= i
.log2_scale_factor
;
3593 if (i
.index_reg
== 0)
3595 /* <disp>(%esp) becomes two byte modrm with no index
3596 register. We've already stored the code for esp
3597 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3598 Any base register besides %esp will not use the
3599 extra modrm byte. */
3600 i
.sib
.index
= NO_INDEX_REGISTER
;
3601 #if !SCALE1_WHEN_NO_INDEX
3602 /* Another case where we force the second modrm byte. */
3603 if (i
.log2_scale_factor
)
3604 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3609 i
.sib
.index
= i
.index_reg
->reg_num
;
3610 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3611 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3616 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3617 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
3620 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3623 if (fake_zero_displacement
)
3625 /* Fakes a zero displacement assuming that i.types[op]
3626 holds the correct displacement size. */
3629 assert (i
.op
[op
].disps
== 0);
3630 exp
= &disp_expressions
[i
.disp_operands
++];
3631 i
.op
[op
].disps
= exp
;
3632 exp
->X_op
= O_constant
;
3633 exp
->X_add_number
= 0;
3634 exp
->X_add_symbol
= (symbolS
*) 0;
3635 exp
->X_op_symbol
= (symbolS
*) 0;
3639 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3640 (if any) based on i.tm.extension_opcode. Again, we must be
3641 careful to make sure that segment/control/debug/test/MMX
3642 registers are coded into the i.rm.reg field. */
3647 & (Reg
| RegMMX
| RegXMM
3649 | Control
| Debug
| Test
))
3652 & (Reg
| RegMMX
| RegXMM
3654 | Control
| Debug
| Test
))
3657 /* If there is an extension opcode to put here, the register
3658 number must be put into the regmem field. */
3659 if (i
.tm
.extension_opcode
!= None
)
3661 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
3662 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3667 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
3668 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3672 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3673 must set it to 3 to indicate this is a register operand
3674 in the regmem field. */
3675 if (!i
.mem_operands
)
3679 /* Fill in i.rm.reg field with extension opcode (if any). */
3680 if (i
.tm
.extension_opcode
!= None
)
3681 i
.rm
.reg
= i
.tm
.extension_opcode
;
3692 relax_substateT subtype
;
3697 if (flag_code
== CODE_16BIT
)
3701 if (i
.prefix
[DATA_PREFIX
] != 0)
3707 /* Pentium4 branch hints. */
3708 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3709 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3714 if (i
.prefix
[REX_PREFIX
] != 0)
3720 if (i
.prefixes
!= 0 && !intel_syntax
)
3721 as_warn (_("skipping prefixes on this instruction"));
3723 /* It's always a symbol; End frag & setup for relax.
3724 Make sure there is enough room in this frag for the largest
3725 instruction we may generate in md_convert_frag. This is 2
3726 bytes for the opcode and room for the prefix and largest
3728 frag_grow (prefix
+ 2 + 4);
3729 /* Prefix and 1 opcode byte go in fr_fix. */
3730 p
= frag_more (prefix
+ 1);
3731 if (i
.prefix
[DATA_PREFIX
] != 0)
3732 *p
++ = DATA_PREFIX_OPCODE
;
3733 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
3734 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
3735 *p
++ = i
.prefix
[SEG_PREFIX
];
3736 if (i
.prefix
[REX_PREFIX
] != 0)
3737 *p
++ = i
.prefix
[REX_PREFIX
];
3738 *p
= i
.tm
.base_opcode
;
3740 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
3741 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
3742 else if ((cpu_arch_flags
& Cpu386
) != 0)
3743 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
3745 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
3748 sym
= i
.op
[0].disps
->X_add_symbol
;
3749 off
= i
.op
[0].disps
->X_add_number
;
3751 if (i
.op
[0].disps
->X_op
!= O_constant
3752 && i
.op
[0].disps
->X_op
!= O_symbol
)
3754 /* Handle complex expressions. */
3755 sym
= make_expr_symbol (i
.op
[0].disps
);
3759 /* 1 possible extra opcode + 4 byte displacement go in var part.
3760 Pass reloc in fr_var. */
3761 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
3771 if (i
.tm
.opcode_modifier
& JumpByte
)
3773 /* This is a loop or jecxz type instruction. */
3775 if (i
.prefix
[ADDR_PREFIX
] != 0)
3777 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3780 /* Pentium4 branch hints. */
3781 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3782 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3784 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3793 if (flag_code
== CODE_16BIT
)
3796 if (i
.prefix
[DATA_PREFIX
] != 0)
3798 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3808 if (i
.prefix
[REX_PREFIX
] != 0)
3810 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3814 if (i
.prefixes
!= 0 && !intel_syntax
)
3815 as_warn (_("skipping prefixes on this instruction"));
3817 p
= frag_more (1 + size
);
3818 *p
++ = i
.tm
.base_opcode
;
3820 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3821 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3823 /* All jumps handled here are signed, but don't use a signed limit
3824 check for 32 and 16 bit jumps as we want to allow wrap around at
3825 4G and 64k respectively. */
3827 fixP
->fx_signed
= 1;
3831 output_interseg_jump ()
3839 if (flag_code
== CODE_16BIT
)
3843 if (i
.prefix
[DATA_PREFIX
] != 0)
3849 if (i
.prefix
[REX_PREFIX
] != 0)
3859 if (i
.prefixes
!= 0 && !intel_syntax
)
3860 as_warn (_("skipping prefixes on this instruction"));
3862 /* 1 opcode; 2 segment; offset */
3863 p
= frag_more (prefix
+ 1 + 2 + size
);
3865 if (i
.prefix
[DATA_PREFIX
] != 0)
3866 *p
++ = DATA_PREFIX_OPCODE
;
3868 if (i
.prefix
[REX_PREFIX
] != 0)
3869 *p
++ = i
.prefix
[REX_PREFIX
];
3871 *p
++ = i
.tm
.base_opcode
;
3872 if (i
.op
[1].imms
->X_op
== O_constant
)
3874 offsetT n
= i
.op
[1].imms
->X_add_number
;
3877 && !fits_in_unsigned_word (n
)
3878 && !fits_in_signed_word (n
))
3880 as_bad (_("16-bit jump out of range"));
3883 md_number_to_chars (p
, n
, size
);
3886 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3887 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3888 if (i
.op
[0].imms
->X_op
!= O_constant
)
3889 as_bad (_("can't handle non absolute segment in `%s'"),
3891 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3897 fragS
*insn_start_frag
;
3898 offsetT insn_start_off
;
3900 /* Tie dwarf2 debug info to the address at the start of the insn.
3901 We can't do this after the insn has been output as the current
3902 frag may have been closed off. eg. by frag_var. */
3903 dwarf2_emit_insn (0);
3905 insn_start_frag
= frag_now
;
3906 insn_start_off
= frag_now_fix ();
3909 if (i
.tm
.opcode_modifier
& Jump
)
3911 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3913 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3914 output_interseg_jump ();
3917 /* Output normal instructions here. */
3920 unsigned int prefix
;
3922 /* All opcodes on i386 have either 1 or 2 bytes. Supplemental
3923 Streaming SIMD extensions 3 Instructions have 3 bytes. We may
3924 use one more higher byte to specify a prefix the instruction
3926 if ((i
.tm
.cpu_flags
& CpuSSSE3
) != 0)
3928 if (i
.tm
.base_opcode
& 0xff000000)
3930 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
3934 else if ((i
.tm
.base_opcode
& 0xff0000) != 0)
3936 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
3937 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0)
3940 if (prefix
!= REPE_PREFIX_OPCODE
3941 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
3942 add_prefix (prefix
);
3945 add_prefix (prefix
);
3948 /* The prefix bytes. */
3950 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3956 md_number_to_chars (p
, (valueT
) *q
, 1);
3960 /* Now the opcode; be careful about word order here! */
3961 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3963 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3967 if ((i
.tm
.cpu_flags
& CpuSSSE3
) != 0)
3970 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
3975 /* Put out high byte first: can't use md_number_to_chars! */
3976 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3977 *p
= i
.tm
.base_opcode
& 0xff;
3980 /* Now the modrm byte and sib byte (if present). */
3981 if (i
.tm
.opcode_modifier
& Modrm
)
3984 md_number_to_chars (p
,
3985 (valueT
) (i
.rm
.regmem
<< 0
3989 /* If i.rm.regmem == ESP (4)
3990 && i.rm.mode != (Register mode)
3992 ==> need second modrm byte. */
3993 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3995 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3998 md_number_to_chars (p
,
3999 (valueT
) (i
.sib
.base
<< 0
4001 | i
.sib
.scale
<< 6),
4006 if (i
.disp_operands
)
4007 output_disp (insn_start_frag
, insn_start_off
);
4010 output_imm (insn_start_frag
, insn_start_off
);
4016 pi ("" /*line*/, &i
);
4018 #endif /* DEBUG386 */
4022 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
4027 for (n
= 0; n
< i
.operands
; n
++)
4029 if (i
.types
[n
] & Disp
)
4031 if (i
.op
[n
].disps
->X_op
== O_constant
)
4037 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
4040 if (i
.types
[n
] & Disp8
)
4042 if (i
.types
[n
] & Disp64
)
4045 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
4047 p
= frag_more (size
);
4048 md_number_to_chars (p
, val
, size
);
4052 enum bfd_reloc_code_real reloc_type
;
4055 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
4057 /* The PC relative address is computed relative
4058 to the instruction boundary, so in case immediate
4059 fields follows, we need to adjust the value. */
4060 if (pcrel
&& i
.imm_operands
)
4065 for (n1
= 0; n1
< i
.operands
; n1
++)
4066 if (i
.types
[n1
] & Imm
)
4068 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
4071 if (i
.types
[n1
] & (Imm8
| Imm8S
))
4073 if (i
.types
[n1
] & Imm64
)
4078 /* We should find the immediate. */
4079 if (n1
== i
.operands
)
4081 i
.op
[n
].disps
->X_add_number
-= imm_size
;
4084 if (i
.types
[n
] & Disp32S
)
4087 if (i
.types
[n
] & (Disp16
| Disp64
))
4090 if (i
.types
[n
] & Disp64
)
4094 p
= frag_more (size
);
4095 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
4097 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
4098 && (((reloc_type
== BFD_RELOC_32
4099 || reloc_type
== BFD_RELOC_X86_64_32S
4100 || (reloc_type
== BFD_RELOC_64
4102 && (i
.op
[n
].disps
->X_op
== O_symbol
4103 || (i
.op
[n
].disps
->X_op
== O_add
4104 && ((symbol_get_value_expression
4105 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
4107 || reloc_type
== BFD_RELOC_32_PCREL
))
4111 if (insn_start_frag
== frag_now
)
4112 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
4117 add
= insn_start_frag
->fr_fix
- insn_start_off
;
4118 for (fr
= insn_start_frag
->fr_next
;
4119 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
4121 add
+= p
- frag_now
->fr_literal
;
4126 reloc_type
= BFD_RELOC_386_GOTPC
;
4127 i
.op
[n
].imms
->X_add_number
+= add
;
4129 else if (reloc_type
== BFD_RELOC_64
)
4130 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
4132 /* Don't do the adjustment for x86-64, as there
4133 the pcrel addressing is relative to the _next_
4134 insn, and that is taken care of in other code. */
4135 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
4137 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4138 i
.op
[n
].disps
, pcrel
, reloc_type
);
4145 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
4150 for (n
= 0; n
< i
.operands
; n
++)
4152 if (i
.types
[n
] & Imm
)
4154 if (i
.op
[n
].imms
->X_op
== O_constant
)
4160 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
4163 if (i
.types
[n
] & (Imm8
| Imm8S
))
4165 else if (i
.types
[n
] & Imm64
)
4168 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
4170 p
= frag_more (size
);
4171 md_number_to_chars (p
, val
, size
);
4175 /* Not absolute_section.
4176 Need a 32-bit fixup (don't support 8bit
4177 non-absolute imms). Try to support other
4179 enum bfd_reloc_code_real reloc_type
;
4183 if ((i
.types
[n
] & (Imm32S
))
4184 && (i
.suffix
== QWORD_MNEM_SUFFIX
4185 || (!i
.suffix
&& (i
.tm
.opcode_modifier
& No_lSuf
))))
4187 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
4190 if (i
.types
[n
] & (Imm8
| Imm8S
))
4192 if (i
.types
[n
] & Imm64
)
4196 p
= frag_more (size
);
4197 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
4199 /* This is tough to explain. We end up with this one if we
4200 * have operands that look like
4201 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4202 * obtain the absolute address of the GOT, and it is strongly
4203 * preferable from a performance point of view to avoid using
4204 * a runtime relocation for this. The actual sequence of
4205 * instructions often look something like:
4210 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4212 * The call and pop essentially return the absolute address
4213 * of the label .L66 and store it in %ebx. The linker itself
4214 * will ultimately change the first operand of the addl so
4215 * that %ebx points to the GOT, but to keep things simple, the
4216 * .o file must have this operand set so that it generates not
4217 * the absolute address of .L66, but the absolute address of
4218 * itself. This allows the linker itself simply treat a GOTPC
4219 * relocation as asking for a pcrel offset to the GOT to be
4220 * added in, and the addend of the relocation is stored in the
4221 * operand field for the instruction itself.
4223 * Our job here is to fix the operand so that it would add
4224 * the correct offset so that %ebx would point to itself. The
4225 * thing that is tricky is that .-.L66 will point to the
4226 * beginning of the instruction, so we need to further modify
4227 * the operand so that it will point to itself. There are
4228 * other cases where you have something like:
4230 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4232 * and here no correction would be required. Internally in
4233 * the assembler we treat operands of this form as not being
4234 * pcrel since the '.' is explicitly mentioned, and I wonder
4235 * whether it would simplify matters to do it this way. Who
4236 * knows. In earlier versions of the PIC patches, the
4237 * pcrel_adjust field was used to store the correction, but
4238 * since the expression is not pcrel, I felt it would be
4239 * confusing to do it this way. */
4241 if ((reloc_type
== BFD_RELOC_32
4242 || reloc_type
== BFD_RELOC_X86_64_32S
4243 || reloc_type
== BFD_RELOC_64
)
4245 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
4246 && (i
.op
[n
].imms
->X_op
== O_symbol
4247 || (i
.op
[n
].imms
->X_op
== O_add
4248 && ((symbol_get_value_expression
4249 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
4254 if (insn_start_frag
== frag_now
)
4255 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
4260 add
= insn_start_frag
->fr_fix
- insn_start_off
;
4261 for (fr
= insn_start_frag
->fr_next
;
4262 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
4264 add
+= p
- frag_now
->fr_literal
;
4268 reloc_type
= BFD_RELOC_386_GOTPC
;
4270 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
4272 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
4273 i
.op
[n
].imms
->X_add_number
+= add
;
4275 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4276 i
.op
[n
].imms
, 0, reloc_type
);
4282 /* x86_cons_fix_new is called via the expression parsing code when a
4283 reloc is needed. We use this hook to get the correct .got reloc. */
4284 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
4285 static int cons_sign
= -1;
4288 x86_cons_fix_new (fragS
*frag
,
4293 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
4295 got_reloc
= NO_RELOC
;
4298 if (exp
->X_op
== O_secrel
)
4300 exp
->X_op
= O_symbol
;
4301 r
= BFD_RELOC_32_SECREL
;
4305 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
4308 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4309 # define lex_got(reloc, adjust, types) NULL
4311 /* Parse operands of the form
4312 <symbol>@GOTOFF+<nnn>
4313 and similar .plt or .got references.
4315 If we find one, set up the correct relocation in RELOC and copy the
4316 input string, minus the `@GOTOFF' into a malloc'd buffer for
4317 parsing by the calling routine. Return this buffer, and if ADJUST
4318 is non-null set it to the length of the string we removed from the
4319 input line. Otherwise return NULL. */
4321 lex_got (enum bfd_reloc_code_real
*reloc
,
4323 unsigned int *types
)
4325 /* Some of the relocations depend on the size of what field is to
4326 be relocated. But in our callers i386_immediate and i386_displacement
4327 we don't yet know the operand size (this will be set by insn
4328 matching). Hence we record the word32 relocation here,
4329 and adjust the reloc according to the real size in reloc(). */
4330 static const struct {
4332 const enum bfd_reloc_code_real rel
[2];
4333 const unsigned int types64
;
4335 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64
}, Imm64
},
4336 { "PLT", { BFD_RELOC_386_PLT32
, BFD_RELOC_X86_64_PLT32
}, Imm32
|Imm32S
|Disp32
},
4337 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64
}, Imm64
|Disp64
},
4338 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, BFD_RELOC_X86_64_GOTOFF64
}, Imm64
|Disp64
},
4339 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL
}, Imm32
|Imm32S
|Disp32
},
4340 { "TLSGD", { BFD_RELOC_386_TLS_GD
, BFD_RELOC_X86_64_TLSGD
}, Imm32
|Imm32S
|Disp32
},
4341 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
, 0 }, 0 },
4342 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD
}, Imm32
|Imm32S
|Disp32
},
4343 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
, BFD_RELOC_X86_64_GOTTPOFF
}, Imm32
|Imm32S
|Disp32
},
4344 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
, BFD_RELOC_X86_64_TPOFF32
}, Imm32
|Imm32S
|Imm64
|Disp32
|Disp64
},
4345 { "NTPOFF", { BFD_RELOC_386_TLS_LE
, 0 }, 0 },
4346 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
, BFD_RELOC_X86_64_DTPOFF32
}, Imm32
|Imm32S
|Imm64
|Disp32
|Disp64
},
4347 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
, 0 }, 0 },
4348 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
, 0 }, 0 },
4349 { "GOT", { BFD_RELOC_386_GOT32
, BFD_RELOC_X86_64_GOT32
}, Imm32
|Imm32S
|Disp32
|Imm64
},
4350 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
, BFD_RELOC_X86_64_GOTPC32_TLSDESC
}, Imm32
|Imm32S
|Disp32
},
4351 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
, BFD_RELOC_X86_64_TLSDESC_CALL
}, Imm32
|Imm32S
|Disp32
}
4359 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
4360 if (is_end_of_line
[(unsigned char) *cp
])
4363 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
4367 len
= strlen (gotrel
[j
].str
);
4368 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
4370 if (gotrel
[j
].rel
[object_64bit
] != 0)
4373 char *tmpbuf
, *past_reloc
;
4375 *reloc
= gotrel
[j
].rel
[object_64bit
];
4381 if (flag_code
!= CODE_64BIT
)
4382 *types
= Imm32
|Disp32
;
4384 *types
= gotrel
[j
].types64
;
4387 if (GOT_symbol
== NULL
)
4388 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
4390 /* Replace the relocation token with ' ', so that
4391 errors like foo@GOTOFF1 will be detected. */
4393 /* The length of the first part of our input line. */
4394 first
= cp
- input_line_pointer
;
4396 /* The second part goes from after the reloc token until
4397 (and including) an end_of_line char. Don't use strlen
4398 here as the end_of_line char may not be a NUL. */
4399 past_reloc
= cp
+ 1 + len
;
4400 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
4402 second
= cp
- past_reloc
;
4404 /* Allocate and copy string. The trailing NUL shouldn't
4405 be necessary, but be safe. */
4406 tmpbuf
= xmalloc (first
+ second
+ 2);
4407 memcpy (tmpbuf
, input_line_pointer
, first
);
4408 tmpbuf
[first
] = ' ';
4409 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
4410 tmpbuf
[first
+ second
+ 1] = '\0';
4414 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4415 gotrel
[j
].str
, 1 << (5 + object_64bit
));
4420 /* Might be a symbol version string. Don't as_bad here. */
4425 x86_cons (exp
, size
)
4429 if (size
== 4 || (object_64bit
&& size
== 8))
4431 /* Handle @GOTOFF and the like in an expression. */
4433 char *gotfree_input_line
;
4436 save
= input_line_pointer
;
4437 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
4438 if (gotfree_input_line
)
4439 input_line_pointer
= gotfree_input_line
;
4443 if (gotfree_input_line
)
4445 /* expression () has merrily parsed up to the end of line,
4446 or a comma - in the wrong buffer. Transfer how far
4447 input_line_pointer has moved to the right buffer. */
4448 input_line_pointer
= (save
4449 + (input_line_pointer
- gotfree_input_line
)
4451 free (gotfree_input_line
);
4459 static void signed_cons (int size
)
4461 if (flag_code
== CODE_64BIT
)
4469 pe_directive_secrel (dummy
)
4470 int dummy ATTRIBUTE_UNUSED
;
4477 if (exp
.X_op
== O_symbol
)
4478 exp
.X_op
= O_secrel
;
4480 emit_expr (&exp
, 4);
4482 while (*input_line_pointer
++ == ',');
4484 input_line_pointer
--;
4485 demand_empty_rest_of_line ();
4489 static int i386_immediate
PARAMS ((char *));
4492 i386_immediate (imm_start
)
4495 char *save_input_line_pointer
;
4496 char *gotfree_input_line
;
4499 unsigned int types
= ~0U;
4501 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
4503 as_bad (_("only 1 or 2 immediate operands are allowed"));
4507 exp
= &im_expressions
[i
.imm_operands
++];
4508 i
.op
[this_operand
].imms
= exp
;
4510 if (is_space_char (*imm_start
))
4513 save_input_line_pointer
= input_line_pointer
;
4514 input_line_pointer
= imm_start
;
4516 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4517 if (gotfree_input_line
)
4518 input_line_pointer
= gotfree_input_line
;
4520 exp_seg
= expression (exp
);
4523 if (*input_line_pointer
)
4524 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4526 input_line_pointer
= save_input_line_pointer
;
4527 if (gotfree_input_line
)
4528 free (gotfree_input_line
);
4530 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4532 /* Missing or bad expr becomes absolute 0. */
4533 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
4535 exp
->X_op
= O_constant
;
4536 exp
->X_add_number
= 0;
4537 exp
->X_add_symbol
= (symbolS
*) 0;
4538 exp
->X_op_symbol
= (symbolS
*) 0;
4540 else if (exp
->X_op
== O_constant
)
4542 /* Size it properly later. */
4543 i
.types
[this_operand
] |= Imm64
;
4544 /* If BFD64, sign extend val. */
4545 if (!use_rela_relocations
)
4546 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
4547 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
4549 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4550 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
4551 && exp_seg
!= absolute_section
4552 && exp_seg
!= text_section
4553 && exp_seg
!= data_section
4554 && exp_seg
!= bss_section
4555 && exp_seg
!= undefined_section
4556 && !bfd_is_com_section (exp_seg
))
4558 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4562 else if (!intel_syntax
&& exp
->X_op
== O_register
)
4564 as_bad (_("illegal immediate register operand %s"), imm_start
);
4569 /* This is an address. The size of the address will be
4570 determined later, depending on destination register,
4571 suffix, or the default for the section. */
4572 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
4573 i
.types
[this_operand
] &= types
;
4579 static char *i386_scale
PARAMS ((char *));
4586 char *save
= input_line_pointer
;
4588 input_line_pointer
= scale
;
4589 val
= get_absolute_expression ();
4594 i
.log2_scale_factor
= 0;
4597 i
.log2_scale_factor
= 1;
4600 i
.log2_scale_factor
= 2;
4603 i
.log2_scale_factor
= 3;
4607 char sep
= *input_line_pointer
;
4609 *input_line_pointer
= '\0';
4610 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4612 *input_line_pointer
= sep
;
4613 input_line_pointer
= save
;
4617 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
4619 as_warn (_("scale factor of %d without an index register"),
4620 1 << i
.log2_scale_factor
);
4621 #if SCALE1_WHEN_NO_INDEX
4622 i
.log2_scale_factor
= 0;
4625 scale
= input_line_pointer
;
4626 input_line_pointer
= save
;
4630 static int i386_displacement
PARAMS ((char *, char *));
4633 i386_displacement (disp_start
, disp_end
)
4639 char *save_input_line_pointer
;
4640 char *gotfree_input_line
;
4641 int bigdisp
, override
;
4642 unsigned int types
= Disp
;
4644 if ((i
.types
[this_operand
] & JumpAbsolute
)
4645 || !(current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
)))
4648 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
4652 /* For PC-relative branches, the width of the displacement
4653 is dependent upon data size, not address size. */
4655 override
= (i
.prefix
[DATA_PREFIX
] != 0);
4657 if (flag_code
== CODE_64BIT
)
4660 bigdisp
= ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
4662 : Disp32S
| Disp32
);
4664 bigdisp
= Disp64
| Disp32S
| Disp32
;
4671 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
4673 : LONG_MNEM_SUFFIX
));
4676 if ((flag_code
== CODE_16BIT
) ^ override
)
4679 i
.types
[this_operand
] |= bigdisp
;
4681 exp
= &disp_expressions
[i
.disp_operands
];
4682 i
.op
[this_operand
].disps
= exp
;
4684 save_input_line_pointer
= input_line_pointer
;
4685 input_line_pointer
= disp_start
;
4686 END_STRING_AND_SAVE (disp_end
);
4688 #ifndef GCC_ASM_O_HACK
4689 #define GCC_ASM_O_HACK 0
4692 END_STRING_AND_SAVE (disp_end
+ 1);
4693 if ((i
.types
[this_operand
] & BaseIndex
) != 0
4694 && displacement_string_end
[-1] == '+')
4696 /* This hack is to avoid a warning when using the "o"
4697 constraint within gcc asm statements.
4700 #define _set_tssldt_desc(n,addr,limit,type) \
4701 __asm__ __volatile__ ( \
4703 "movw %w1,2+%0\n\t" \
4705 "movb %b1,4+%0\n\t" \
4706 "movb %4,5+%0\n\t" \
4707 "movb $0,6+%0\n\t" \
4708 "movb %h1,7+%0\n\t" \
4710 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4712 This works great except that the output assembler ends
4713 up looking a bit weird if it turns out that there is
4714 no offset. You end up producing code that looks like:
4727 So here we provide the missing zero. */
4729 *displacement_string_end
= '0';
4732 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4733 if (gotfree_input_line
)
4734 input_line_pointer
= gotfree_input_line
;
4736 exp_seg
= expression (exp
);
4739 if (*input_line_pointer
)
4740 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4742 RESTORE_END_STRING (disp_end
+ 1);
4744 RESTORE_END_STRING (disp_end
);
4745 input_line_pointer
= save_input_line_pointer
;
4746 if (gotfree_input_line
)
4747 free (gotfree_input_line
);
4749 /* We do this to make sure that the section symbol is in
4750 the symbol table. We will ultimately change the relocation
4751 to be relative to the beginning of the section. */
4752 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
4753 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4754 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4756 if (exp
->X_op
!= O_symbol
)
4758 as_bad (_("bad expression used with @%s"),
4759 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4765 if (S_IS_LOCAL (exp
->X_add_symbol
)
4766 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
4767 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
4768 exp
->X_op
= O_subtract
;
4769 exp
->X_op_symbol
= GOT_symbol
;
4770 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
4771 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
4772 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4773 i
.reloc
[this_operand
] = BFD_RELOC_64
;
4775 i
.reloc
[this_operand
] = BFD_RELOC_32
;
4778 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4780 /* Missing or bad expr becomes absolute 0. */
4781 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4783 exp
->X_op
= O_constant
;
4784 exp
->X_add_number
= 0;
4785 exp
->X_add_symbol
= (symbolS
*) 0;
4786 exp
->X_op_symbol
= (symbolS
*) 0;
4789 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4790 if (exp
->X_op
!= O_constant
4791 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
4792 && exp_seg
!= absolute_section
4793 && exp_seg
!= text_section
4794 && exp_seg
!= data_section
4795 && exp_seg
!= bss_section
4796 && exp_seg
!= undefined_section
4797 && !bfd_is_com_section (exp_seg
))
4799 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4804 if (!(i
.types
[this_operand
] & ~Disp
))
4805 i
.types
[this_operand
] &= types
;
4810 static int i386_index_check
PARAMS ((const char *));
4812 /* Make sure the memory operand we've been dealt is valid.
4813 Return 1 on success, 0 on a failure. */
4816 i386_index_check (operand_string
)
4817 const char *operand_string
;
4820 #if INFER_ADDR_PREFIX
4826 if ((current_templates
->start
->cpu_flags
& CpuSVME
)
4827 && current_templates
->end
[-1].operand_types
[0] == AnyMem
)
4829 /* Memory operands of SVME insns are special in that they only allow
4830 rAX as their memory address and ignore any segment override. */
4833 /* SKINIT is even more restrictive: it always requires EAX. */
4834 if (strcmp (current_templates
->start
->name
, "skinit") == 0)
4836 else if (flag_code
== CODE_64BIT
)
4837 RegXX
= i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
;
4839 RegXX
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0)
4843 || !(i
.base_reg
->reg_type
& Acc
)
4844 || !(i
.base_reg
->reg_type
& RegXX
)
4846 || (i
.types
[0] & Disp
))
4849 else if (flag_code
== CODE_64BIT
)
4851 unsigned RegXX
= (i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
);
4854 && ((i
.base_reg
->reg_type
& RegXX
) == 0)
4855 && (i
.base_reg
->reg_type
!= BaseIndex
4858 && ((i
.index_reg
->reg_type
& (RegXX
| BaseIndex
))
4859 != (RegXX
| BaseIndex
))))
4864 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4868 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
4869 != (Reg16
| BaseIndex
)))
4871 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
4872 != (Reg16
| BaseIndex
))
4874 && i
.base_reg
->reg_num
< 6
4875 && i
.index_reg
->reg_num
>= 6
4876 && i
.log2_scale_factor
== 0))))
4883 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
4885 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
4886 != (Reg32
| BaseIndex
))))
4892 #if INFER_ADDR_PREFIX
4893 if (i
.prefix
[ADDR_PREFIX
] == 0)
4895 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
4897 /* Change the size of any displacement too. At most one of
4898 Disp16 or Disp32 is set.
4899 FIXME. There doesn't seem to be any real need for separate
4900 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4901 Removing them would probably clean up the code quite a lot. */
4902 if (flag_code
!= CODE_64BIT
&& (i
.types
[this_operand
] & (Disp16
| Disp32
)))
4903 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
4908 as_bad (_("`%s' is not a valid base/index expression"),
4912 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4914 flag_code_names
[flag_code
]);
4919 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4923 i386_operand (operand_string
)
4924 char *operand_string
;
4928 char *op_string
= operand_string
;
4930 if (is_space_char (*op_string
))
4933 /* We check for an absolute prefix (differentiating,
4934 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4935 if (*op_string
== ABSOLUTE_PREFIX
)
4938 if (is_space_char (*op_string
))
4940 i
.types
[this_operand
] |= JumpAbsolute
;
4943 /* Check if operand is a register. */
4944 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
4946 /* Check for a segment override by searching for ':' after a
4947 segment register. */
4949 if (is_space_char (*op_string
))
4951 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
4956 i
.seg
[i
.mem_operands
] = &es
;
4959 i
.seg
[i
.mem_operands
] = &cs
;
4962 i
.seg
[i
.mem_operands
] = &ss
;
4965 i
.seg
[i
.mem_operands
] = &ds
;
4968 i
.seg
[i
.mem_operands
] = &fs
;
4971 i
.seg
[i
.mem_operands
] = &gs
;
4975 /* Skip the ':' and whitespace. */
4977 if (is_space_char (*op_string
))
4980 if (!is_digit_char (*op_string
)
4981 && !is_identifier_char (*op_string
)
4982 && *op_string
!= '('
4983 && *op_string
!= ABSOLUTE_PREFIX
)
4985 as_bad (_("bad memory operand `%s'"), op_string
);
4988 /* Handle case of %es:*foo. */
4989 if (*op_string
== ABSOLUTE_PREFIX
)
4992 if (is_space_char (*op_string
))
4994 i
.types
[this_operand
] |= JumpAbsolute
;
4996 goto do_memory_reference
;
5000 as_bad (_("junk `%s' after register"), op_string
);
5003 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
5004 i
.op
[this_operand
].regs
= r
;
5007 else if (*op_string
== REGISTER_PREFIX
)
5009 as_bad (_("bad register name `%s'"), op_string
);
5012 else if (*op_string
== IMMEDIATE_PREFIX
)
5015 if (i
.types
[this_operand
] & JumpAbsolute
)
5017 as_bad (_("immediate operand illegal with absolute jump"));
5020 if (!i386_immediate (op_string
))
5023 else if (is_digit_char (*op_string
)
5024 || is_identifier_char (*op_string
)
5025 || *op_string
== '(')
5027 /* This is a memory reference of some sort. */
5030 /* Start and end of displacement string expression (if found). */
5031 char *displacement_string_start
;
5032 char *displacement_string_end
;
5034 do_memory_reference
:
5035 if ((i
.mem_operands
== 1
5036 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5037 || i
.mem_operands
== 2)
5039 as_bad (_("too many memory references for `%s'"),
5040 current_templates
->start
->name
);
5044 /* Check for base index form. We detect the base index form by
5045 looking for an ')' at the end of the operand, searching
5046 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5048 base_string
= op_string
+ strlen (op_string
);
5051 if (is_space_char (*base_string
))
5054 /* If we only have a displacement, set-up for it to be parsed later. */
5055 displacement_string_start
= op_string
;
5056 displacement_string_end
= base_string
+ 1;
5058 if (*base_string
== ')')
5061 unsigned int parens_balanced
= 1;
5062 /* We've already checked that the number of left & right ()'s are
5063 equal, so this loop will not be infinite. */
5067 if (*base_string
== ')')
5069 if (*base_string
== '(')
5072 while (parens_balanced
);
5074 temp_string
= base_string
;
5076 /* Skip past '(' and whitespace. */
5078 if (is_space_char (*base_string
))
5081 if (*base_string
== ','
5082 || ((i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
5084 displacement_string_end
= temp_string
;
5086 i
.types
[this_operand
] |= BaseIndex
;
5090 base_string
= end_op
;
5091 if (is_space_char (*base_string
))
5095 /* There may be an index reg or scale factor here. */
5096 if (*base_string
== ',')
5099 if (is_space_char (*base_string
))
5102 if ((i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
5104 base_string
= end_op
;
5105 if (is_space_char (*base_string
))
5107 if (*base_string
== ',')
5110 if (is_space_char (*base_string
))
5113 else if (*base_string
!= ')')
5115 as_bad (_("expecting `,' or `)' after index register in `%s'"),
5120 else if (*base_string
== REGISTER_PREFIX
)
5122 as_bad (_("bad register name `%s'"), base_string
);
5126 /* Check for scale factor. */
5127 if (*base_string
!= ')')
5129 char *end_scale
= i386_scale (base_string
);
5134 base_string
= end_scale
;
5135 if (is_space_char (*base_string
))
5137 if (*base_string
!= ')')
5139 as_bad (_("expecting `)' after scale factor in `%s'"),
5144 else if (!i
.index_reg
)
5146 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
5151 else if (*base_string
!= ')')
5153 as_bad (_("expecting `,' or `)' after base register in `%s'"),
5158 else if (*base_string
== REGISTER_PREFIX
)
5160 as_bad (_("bad register name `%s'"), base_string
);
5165 /* If there's an expression beginning the operand, parse it,
5166 assuming displacement_string_start and
5167 displacement_string_end are meaningful. */
5168 if (displacement_string_start
!= displacement_string_end
)
5170 if (!i386_displacement (displacement_string_start
,
5171 displacement_string_end
))
5175 /* Special case for (%dx) while doing input/output op. */
5177 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
5179 && i
.log2_scale_factor
== 0
5180 && i
.seg
[i
.mem_operands
] == 0
5181 && (i
.types
[this_operand
] & Disp
) == 0)
5183 i
.types
[this_operand
] = InOutPortReg
;
5187 if (i386_index_check (operand_string
) == 0)
5193 /* It's not a memory operand; argh! */
5194 as_bad (_("invalid char %s beginning operand %d `%s'"),
5195 output_invalid (*op_string
),
5200 return 1; /* Normal return. */
5203 /* md_estimate_size_before_relax()
5205 Called just before relax() for rs_machine_dependent frags. The x86
5206 assembler uses these frags to handle variable size jump
5209 Any symbol that is now undefined will not become defined.
5210 Return the correct fr_subtype in the frag.
5211 Return the initial "guess for variable size of frag" to caller.
5212 The guess is actually the growth beyond the fixed part. Whatever
5213 we do to grow the fixed or variable part contributes to our
5217 md_estimate_size_before_relax (fragP
, segment
)
5221 /* We've already got fragP->fr_subtype right; all we have to do is
5222 check for un-relaxable symbols. On an ELF system, we can't relax
5223 an externally visible symbol, because it may be overridden by a
5225 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
5226 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5228 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
5229 || S_IS_WEAK (fragP
->fr_symbol
)))
5233 /* Symbol is undefined in this segment, or we need to keep a
5234 reloc so that weak symbols can be overridden. */
5235 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
5236 enum bfd_reloc_code_real reloc_type
;
5237 unsigned char *opcode
;
5240 if (fragP
->fr_var
!= NO_RELOC
)
5241 reloc_type
= fragP
->fr_var
;
5243 reloc_type
= BFD_RELOC_16_PCREL
;
5245 reloc_type
= BFD_RELOC_32_PCREL
;
5247 old_fr_fix
= fragP
->fr_fix
;
5248 opcode
= (unsigned char *) fragP
->fr_opcode
;
5250 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
5253 /* Make jmp (0xeb) a (d)word displacement jump. */
5255 fragP
->fr_fix
+= size
;
5256 fix_new (fragP
, old_fr_fix
, size
,
5258 fragP
->fr_offset
, 1,
5264 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
5266 /* Negate the condition, and branch past an
5267 unconditional jump. */
5270 /* Insert an unconditional jump. */
5272 /* We added two extra opcode bytes, and have a two byte
5274 fragP
->fr_fix
+= 2 + 2;
5275 fix_new (fragP
, old_fr_fix
+ 2, 2,
5277 fragP
->fr_offset
, 1,
5284 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
5289 fixP
= fix_new (fragP
, old_fr_fix
, 1,
5291 fragP
->fr_offset
, 1,
5293 fixP
->fx_signed
= 1;
5297 /* This changes the byte-displacement jump 0x7N
5298 to the (d)word-displacement jump 0x0f,0x8N. */
5299 opcode
[1] = opcode
[0] + 0x10;
5300 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5301 /* We've added an opcode byte. */
5302 fragP
->fr_fix
+= 1 + size
;
5303 fix_new (fragP
, old_fr_fix
+ 1, size
,
5305 fragP
->fr_offset
, 1,
5310 BAD_CASE (fragP
->fr_subtype
);
5314 return fragP
->fr_fix
- old_fr_fix
;
5317 /* Guess size depending on current relax state. Initially the relax
5318 state will correspond to a short jump and we return 1, because
5319 the variable part of the frag (the branch offset) is one byte
5320 long. However, we can relax a section more than once and in that
5321 case we must either set fr_subtype back to the unrelaxed state,
5322 or return the value for the appropriate branch. */
5323 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
5326 /* Called after relax() is finished.
5328 In: Address of frag.
5329 fr_type == rs_machine_dependent.
5330 fr_subtype is what the address relaxed to.
5332 Out: Any fixSs and constants are set up.
5333 Caller will turn frag into a ".space 0". */
5336 md_convert_frag (abfd
, sec
, fragP
)
5337 bfd
*abfd ATTRIBUTE_UNUSED
;
5338 segT sec ATTRIBUTE_UNUSED
;
5341 unsigned char *opcode
;
5342 unsigned char *where_to_put_displacement
= NULL
;
5343 offsetT target_address
;
5344 offsetT opcode_address
;
5345 unsigned int extension
= 0;
5346 offsetT displacement_from_opcode_start
;
5348 opcode
= (unsigned char *) fragP
->fr_opcode
;
5350 /* Address we want to reach in file space. */
5351 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
5353 /* Address opcode resides at in file space. */
5354 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
5356 /* Displacement from opcode start to fill into instruction. */
5357 displacement_from_opcode_start
= target_address
- opcode_address
;
5359 if ((fragP
->fr_subtype
& BIG
) == 0)
5361 /* Don't have to change opcode. */
5362 extension
= 1; /* 1 opcode + 1 displacement */
5363 where_to_put_displacement
= &opcode
[1];
5367 if (no_cond_jump_promotion
5368 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
5369 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
5371 switch (fragP
->fr_subtype
)
5373 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
5374 extension
= 4; /* 1 opcode + 4 displacement */
5376 where_to_put_displacement
= &opcode
[1];
5379 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
5380 extension
= 2; /* 1 opcode + 2 displacement */
5382 where_to_put_displacement
= &opcode
[1];
5385 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
5386 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
5387 extension
= 5; /* 2 opcode + 4 displacement */
5388 opcode
[1] = opcode
[0] + 0x10;
5389 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5390 where_to_put_displacement
= &opcode
[2];
5393 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
5394 extension
= 3; /* 2 opcode + 2 displacement */
5395 opcode
[1] = opcode
[0] + 0x10;
5396 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5397 where_to_put_displacement
= &opcode
[2];
5400 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
5405 where_to_put_displacement
= &opcode
[3];
5409 BAD_CASE (fragP
->fr_subtype
);
5414 /* If size if less then four we are sure that the operand fits,
5415 but if it's 4, then it could be that the displacement is larger
5417 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
5419 && ((addressT
) (displacement_from_opcode_start
- extension
5420 + ((addressT
) 1 << 31))
5421 > (((addressT
) 2 << 31) - 1)))
5423 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5424 _("jump target out of range"));
5425 /* Make us emit 0. */
5426 displacement_from_opcode_start
= extension
;
5428 /* Now put displacement after opcode. */
5429 md_number_to_chars ((char *) where_to_put_displacement
,
5430 (valueT
) (displacement_from_opcode_start
- extension
),
5431 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
5432 fragP
->fr_fix
+= extension
;
5435 /* Size of byte displacement jmp. */
5436 int md_short_jump_size
= 2;
5438 /* Size of dword displacement jmp. */
5439 int md_long_jump_size
= 5;
5442 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5444 addressT from_addr
, to_addr
;
5445 fragS
*frag ATTRIBUTE_UNUSED
;
5446 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
5450 offset
= to_addr
- (from_addr
+ 2);
5451 /* Opcode for byte-disp jump. */
5452 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
5453 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
5457 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5459 addressT from_addr
, to_addr
;
5460 fragS
*frag ATTRIBUTE_UNUSED
;
5461 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
5465 offset
= to_addr
- (from_addr
+ 5);
5466 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
5467 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
5470 /* Apply a fixup (fixS) to segment data, once it has been determined
5471 by our caller that we have all the info we need to fix it up.
5473 On the 386, immediates, displacements, and data pointers are all in
5474 the same (little-endian) format, so we don't need to care about which
5478 md_apply_fix (fixP
, valP
, seg
)
5479 /* The fix we're to put in. */
5481 /* Pointer to the value of the bits. */
5483 /* Segment fix is from. */
5484 segT seg ATTRIBUTE_UNUSED
;
5486 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
5487 valueT value
= *valP
;
5489 #if !defined (TE_Mach)
5492 switch (fixP
->fx_r_type
)
5498 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
5501 case BFD_RELOC_X86_64_32S
:
5502 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
5505 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
5508 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
5513 if (fixP
->fx_addsy
!= NULL
5514 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
5515 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
5516 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
5517 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
5518 && !use_rela_relocations
)
5520 /* This is a hack. There should be a better way to handle this.
5521 This covers for the fact that bfd_install_relocation will
5522 subtract the current location (for partial_inplace, PC relative
5523 relocations); see more below. */
5527 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
5530 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5532 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5535 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
5538 || (symbol_section_p (fixP
->fx_addsy
)
5539 && sym_seg
!= absolute_section
))
5540 && !generic_force_reloc (fixP
))
5542 /* Yes, we add the values in twice. This is because
5543 bfd_install_relocation subtracts them out again. I think
5544 bfd_install_relocation is broken, but I don't dare change
5546 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5550 #if defined (OBJ_COFF) && defined (TE_PE)
5551 /* For some reason, the PE format does not store a
5552 section address offset for a PC relative symbol. */
5553 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
5554 || S_IS_WEAK (fixP
->fx_addsy
))
5555 value
+= md_pcrel_from (fixP
);
5559 /* Fix a few things - the dynamic linker expects certain values here,
5560 and we must not disappoint it. */
5561 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5562 if (IS_ELF
&& fixP
->fx_addsy
)
5563 switch (fixP
->fx_r_type
)
5565 case BFD_RELOC_386_PLT32
:
5566 case BFD_RELOC_X86_64_PLT32
:
5567 /* Make the jump instruction point to the address of the operand. At
5568 runtime we merely add the offset to the actual PLT entry. */
5572 case BFD_RELOC_386_TLS_GD
:
5573 case BFD_RELOC_386_TLS_LDM
:
5574 case BFD_RELOC_386_TLS_IE_32
:
5575 case BFD_RELOC_386_TLS_IE
:
5576 case BFD_RELOC_386_TLS_GOTIE
:
5577 case BFD_RELOC_386_TLS_GOTDESC
:
5578 case BFD_RELOC_X86_64_TLSGD
:
5579 case BFD_RELOC_X86_64_TLSLD
:
5580 case BFD_RELOC_X86_64_GOTTPOFF
:
5581 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
5582 value
= 0; /* Fully resolved at runtime. No addend. */
5584 case BFD_RELOC_386_TLS_LE
:
5585 case BFD_RELOC_386_TLS_LDO_32
:
5586 case BFD_RELOC_386_TLS_LE_32
:
5587 case BFD_RELOC_X86_64_DTPOFF32
:
5588 case BFD_RELOC_X86_64_DTPOFF64
:
5589 case BFD_RELOC_X86_64_TPOFF32
:
5590 case BFD_RELOC_X86_64_TPOFF64
:
5591 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5594 case BFD_RELOC_386_TLS_DESC_CALL
:
5595 case BFD_RELOC_X86_64_TLSDESC_CALL
:
5596 value
= 0; /* Fully resolved at runtime. No addend. */
5597 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5601 case BFD_RELOC_386_GOT32
:
5602 case BFD_RELOC_X86_64_GOT32
:
5603 value
= 0; /* Fully resolved at runtime. No addend. */
5606 case BFD_RELOC_VTABLE_INHERIT
:
5607 case BFD_RELOC_VTABLE_ENTRY
:
5614 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5616 #endif /* !defined (TE_Mach) */
5618 /* Are we finished with this relocation now? */
5619 if (fixP
->fx_addsy
== NULL
)
5621 else if (use_rela_relocations
)
5623 fixP
->fx_no_overflow
= 1;
5624 /* Remember value for tc_gen_reloc. */
5625 fixP
->fx_addnumber
= value
;
5629 md_number_to_chars (p
, value
, fixP
->fx_size
);
5632 #define MAX_LITTLENUMS 6
5634 /* Turn the string pointed to by litP into a floating point constant
5635 of type TYPE, and emit the appropriate bytes. The number of
5636 LITTLENUMS emitted is stored in *SIZEP. An error message is
5637 returned, or NULL on OK. */
5640 md_atof (type
, litP
, sizeP
)
5646 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5647 LITTLENUM_TYPE
*wordP
;
5669 return _("Bad call to md_atof ()");
5671 t
= atof_ieee (input_line_pointer
, type
, words
);
5673 input_line_pointer
= t
;
5675 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
5676 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5677 the bigendian 386. */
5678 for (wordP
= words
+ prec
- 1; prec
--;)
5680 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
5681 litP
+= sizeof (LITTLENUM_TYPE
);
5686 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
5693 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
5696 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
5697 "(0x%x)", (unsigned char) c
);
5698 return output_invalid_buf
;
5701 /* REG_STRING starts *before* REGISTER_PREFIX. */
5703 static const reg_entry
*
5704 parse_real_register (char *reg_string
, char **end_op
)
5706 char *s
= reg_string
;
5708 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
5711 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5712 if (*s
== REGISTER_PREFIX
)
5715 if (is_space_char (*s
))
5719 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
5721 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
5722 return (const reg_entry
*) NULL
;
5726 /* For naked regs, make sure that we are not dealing with an identifier.
5727 This prevents confusing an identifier like `eax_var' with register
5729 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
5730 return (const reg_entry
*) NULL
;
5734 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
5736 /* Handle floating point regs, allowing spaces in the (i) part. */
5737 if (r
== i386_regtab
/* %st is first entry of table */)
5739 if (is_space_char (*s
))
5744 if (is_space_char (*s
))
5746 if (*s
>= '0' && *s
<= '7')
5748 r
= &i386_float_regtab
[*s
- '0'];
5750 if (is_space_char (*s
))
5758 /* We have "%st(" then garbage. */
5759 return (const reg_entry
*) NULL
;
5764 && ((r
->reg_flags
& (RegRex64
| RegRex
)) | (r
->reg_type
& Reg64
)) != 0
5765 && (r
->reg_type
!= Control
|| !(cpu_arch_flags
& CpuSledgehammer
))
5766 && flag_code
!= CODE_64BIT
)
5767 return (const reg_entry
*) NULL
;
5772 /* REG_STRING starts *before* REGISTER_PREFIX. */
5774 static const reg_entry
*
5775 parse_register (char *reg_string
, char **end_op
)
5779 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5780 r
= parse_real_register (reg_string
, end_op
);
5785 char *save
= input_line_pointer
;
5789 input_line_pointer
= reg_string
;
5790 c
= get_symbol_end ();
5791 symbolP
= symbol_find (reg_string
);
5792 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
5794 const expressionS
*e
= symbol_get_value_expression (symbolP
);
5796 know (e
->X_op
== O_register
);
5797 know (e
->X_add_number
>= 0 && (valueT
) e
->X_add_number
< ARRAY_SIZE (i386_regtab
));
5798 r
= i386_regtab
+ e
->X_add_number
;
5799 *end_op
= input_line_pointer
;
5801 *input_line_pointer
= c
;
5802 input_line_pointer
= save
;
5808 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
5811 char *end
= input_line_pointer
;
5814 r
= parse_register (name
, &input_line_pointer
);
5815 if (r
&& end
<= input_line_pointer
)
5817 *nextcharP
= *input_line_pointer
;
5818 *input_line_pointer
= 0;
5819 e
->X_op
= O_register
;
5820 e
->X_add_number
= r
- i386_regtab
;
5823 input_line_pointer
= end
;
5829 md_operand (expressionS
*e
)
5831 if (*input_line_pointer
== REGISTER_PREFIX
)
5834 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
5838 e
->X_op
= O_register
;
5839 e
->X_add_number
= r
- i386_regtab
;
5840 input_line_pointer
= end
;
5846 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5847 const char *md_shortopts
= "kVQ:sqn";
5849 const char *md_shortopts
= "qn";
5852 #define OPTION_32 (OPTION_MD_BASE + 0)
5853 #define OPTION_64 (OPTION_MD_BASE + 1)
5854 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5855 #define OPTION_MARCH (OPTION_MD_BASE + 3)
5856 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
5858 struct option md_longopts
[] =
5860 {"32", no_argument
, NULL
, OPTION_32
},
5861 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5862 {"64", no_argument
, NULL
, OPTION_64
},
5864 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
5865 {"march", required_argument
, NULL
, OPTION_MARCH
},
5866 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
5867 {NULL
, no_argument
, NULL
, 0}
5869 size_t md_longopts_size
= sizeof (md_longopts
);
5872 md_parse_option (int c
, char *arg
)
5879 optimize_align_code
= 0;
5886 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5887 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5888 should be emitted or not. FIXME: Not implemented. */
5892 /* -V: SVR4 argument to print version ID. */
5894 print_version_id ();
5897 /* -k: Ignore for FreeBSD compatibility. */
5902 /* -s: On i386 Solaris, this tells the native assembler to use
5903 .stab instead of .stab.excl. We always use .stab anyhow. */
5906 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5909 const char **list
, **l
;
5911 list
= bfd_target_list ();
5912 for (l
= list
; *l
!= NULL
; l
++)
5913 if (CONST_STRNEQ (*l
, "elf64-x86-64")
5914 || strcmp (*l
, "coff-x86-64") == 0
5915 || strcmp (*l
, "pe-x86-64") == 0
5916 || strcmp (*l
, "pei-x86-64") == 0)
5918 default_arch
= "x86_64";
5922 as_fatal (_("No compiled in support for x86_64"));
5929 default_arch
= "i386";
5933 #ifdef SVR4_COMMENT_CHARS
5938 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
5940 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
5944 i386_comment_chars
= n
;
5951 as_fatal (_("Invalid -march= option: `%s'"), arg
);
5952 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
5954 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
5956 cpu_arch_isa
= cpu_arch
[i
].type
;
5957 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
5958 if (!cpu_arch_tune_set
)
5960 cpu_arch_tune
= cpu_arch_isa
;
5961 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
5966 if (i
>= ARRAY_SIZE (cpu_arch
))
5967 as_fatal (_("Invalid -march= option: `%s'"), arg
);
5972 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
5973 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
5975 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
5977 cpu_arch_tune_set
= 1;
5978 cpu_arch_tune
= cpu_arch
[i
].type
;
5979 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
5983 if (i
>= ARRAY_SIZE (cpu_arch
))
5984 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
5994 md_show_usage (stream
)
5997 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5998 fprintf (stream
, _("\
6000 -V print assembler version number\n\
6003 fprintf (stream
, _("\
6004 -n Do not optimize code alignment\n\
6005 -q quieten some warnings\n"));
6006 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6007 fprintf (stream
, _("\
6010 #ifdef SVR4_COMMENT_CHARS
6011 fprintf (stream
, _("\
6012 --divide do not treat `/' as a comment character\n"));
6014 fprintf (stream
, _("\
6015 --divide ignored\n"));
6017 fprintf (stream
, _("\
6018 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6019 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
6020 core, core2, k6, athlon, k8, generic32, generic64\n"));
6026 x86_64_target_format (void)
6028 if (strcmp (default_arch
, "x86_64") == 0)
6030 set_code_flag (CODE_64BIT
);
6031 return COFF_TARGET_FORMAT
;
6033 else if (strcmp (default_arch
, "i386") == 0)
6035 set_code_flag (CODE_32BIT
);
6039 as_fatal (_("Unknown architecture"));
6044 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6045 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6047 /* Pick the target format to use. */
6050 i386_target_format ()
6052 if (!strcmp (default_arch
, "x86_64"))
6054 set_code_flag (CODE_64BIT
);
6055 if (cpu_arch_isa_flags
== 0)
6056 cpu_arch_isa_flags
= Cpu186
|Cpu286
|Cpu386
|Cpu486
6057 |Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
6059 if (cpu_arch_tune_flags
== 0)
6060 cpu_arch_tune_flags
= Cpu186
|Cpu286
|Cpu386
|Cpu486
6061 |Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
6064 else if (!strcmp (default_arch
, "i386"))
6066 set_code_flag (CODE_32BIT
);
6067 if (cpu_arch_isa_flags
== 0)
6068 cpu_arch_isa_flags
= Cpu186
|Cpu286
|Cpu386
;
6069 if (cpu_arch_tune_flags
== 0)
6070 cpu_arch_tune_flags
= Cpu186
|Cpu286
|Cpu386
;
6073 as_fatal (_("Unknown architecture"));
6074 switch (OUTPUT_FLAVOR
)
6076 #ifdef OBJ_MAYBE_AOUT
6077 case bfd_target_aout_flavour
:
6078 return AOUT_TARGET_FORMAT
;
6080 #ifdef OBJ_MAYBE_COFF
6081 case bfd_target_coff_flavour
:
6084 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6085 case bfd_target_elf_flavour
:
6087 if (flag_code
== CODE_64BIT
)
6090 use_rela_relocations
= 1;
6092 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
6101 #endif /* OBJ_MAYBE_ more than one */
6103 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6104 void i386_elf_emit_arch_note ()
6106 if (IS_ELF
&& cpu_arch_name
!= NULL
)
6109 asection
*seg
= now_seg
;
6110 subsegT subseg
= now_subseg
;
6111 Elf_Internal_Note i_note
;
6112 Elf_External_Note e_note
;
6113 asection
*note_secp
;
6116 /* Create the .note section. */
6117 note_secp
= subseg_new (".note", 0);
6118 bfd_set_section_flags (stdoutput
,
6120 SEC_HAS_CONTENTS
| SEC_READONLY
);
6122 /* Process the arch string. */
6123 len
= strlen (cpu_arch_name
);
6125 i_note
.namesz
= len
+ 1;
6127 i_note
.type
= NT_ARCH
;
6128 p
= frag_more (sizeof (e_note
.namesz
));
6129 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
6130 p
= frag_more (sizeof (e_note
.descsz
));
6131 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
6132 p
= frag_more (sizeof (e_note
.type
));
6133 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
6134 p
= frag_more (len
+ 1);
6135 strcpy (p
, cpu_arch_name
);
6137 frag_align (2, 0, 0);
6139 subseg_set (seg
, subseg
);
6145 md_undefined_symbol (name
)
6148 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
6149 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
6150 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
6151 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
6155 if (symbol_find (name
))
6156 as_bad (_("GOT already in symbol table"));
6157 GOT_symbol
= symbol_new (name
, undefined_section
,
6158 (valueT
) 0, &zero_address_frag
);
6165 /* Round up a section size to the appropriate boundary. */
6168 md_section_align (segment
, size
)
6169 segT segment ATTRIBUTE_UNUSED
;
6172 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6173 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
6175 /* For a.out, force the section size to be aligned. If we don't do
6176 this, BFD will align it for us, but it will not write out the
6177 final bytes of the section. This may be a bug in BFD, but it is
6178 easier to fix it here since that is how the other a.out targets
6182 align
= bfd_get_section_alignment (stdoutput
, segment
);
6183 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
6190 /* On the i386, PC-relative offsets are relative to the start of the
6191 next instruction. That is, the address of the offset, plus its
6192 size, since the offset is always the last part of the insn. */
6195 md_pcrel_from (fixP
)
6198 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6205 int ignore ATTRIBUTE_UNUSED
;
6209 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6211 obj_elf_section_change_hook ();
6213 temp
= get_absolute_expression ();
6214 subseg_set (bss_section
, (subsegT
) temp
);
6215 demand_empty_rest_of_line ();
6221 i386_validate_fix (fixp
)
6224 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
6226 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
6230 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
6235 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
6237 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
6244 tc_gen_reloc (section
, fixp
)
6245 asection
*section ATTRIBUTE_UNUSED
;
6249 bfd_reloc_code_real_type code
;
6251 switch (fixp
->fx_r_type
)
6253 case BFD_RELOC_X86_64_PLT32
:
6254 case BFD_RELOC_X86_64_GOT32
:
6255 case BFD_RELOC_X86_64_GOTPCREL
:
6256 case BFD_RELOC_386_PLT32
:
6257 case BFD_RELOC_386_GOT32
:
6258 case BFD_RELOC_386_GOTOFF
:
6259 case BFD_RELOC_386_GOTPC
:
6260 case BFD_RELOC_386_TLS_GD
:
6261 case BFD_RELOC_386_TLS_LDM
:
6262 case BFD_RELOC_386_TLS_LDO_32
:
6263 case BFD_RELOC_386_TLS_IE_32
:
6264 case BFD_RELOC_386_TLS_IE
:
6265 case BFD_RELOC_386_TLS_GOTIE
:
6266 case BFD_RELOC_386_TLS_LE_32
:
6267 case BFD_RELOC_386_TLS_LE
:
6268 case BFD_RELOC_386_TLS_GOTDESC
:
6269 case BFD_RELOC_386_TLS_DESC_CALL
:
6270 case BFD_RELOC_X86_64_TLSGD
:
6271 case BFD_RELOC_X86_64_TLSLD
:
6272 case BFD_RELOC_X86_64_DTPOFF32
:
6273 case BFD_RELOC_X86_64_DTPOFF64
:
6274 case BFD_RELOC_X86_64_GOTTPOFF
:
6275 case BFD_RELOC_X86_64_TPOFF32
:
6276 case BFD_RELOC_X86_64_TPOFF64
:
6277 case BFD_RELOC_X86_64_GOTOFF64
:
6278 case BFD_RELOC_X86_64_GOTPC32
:
6279 case BFD_RELOC_X86_64_GOT64
:
6280 case BFD_RELOC_X86_64_GOTPCREL64
:
6281 case BFD_RELOC_X86_64_GOTPC64
:
6282 case BFD_RELOC_X86_64_GOTPLT64
:
6283 case BFD_RELOC_X86_64_PLTOFF64
:
6284 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
6285 case BFD_RELOC_X86_64_TLSDESC_CALL
:
6287 case BFD_RELOC_VTABLE_ENTRY
:
6288 case BFD_RELOC_VTABLE_INHERIT
:
6290 case BFD_RELOC_32_SECREL
:
6292 code
= fixp
->fx_r_type
;
6294 case BFD_RELOC_X86_64_32S
:
6295 if (!fixp
->fx_pcrel
)
6297 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6298 code
= fixp
->fx_r_type
;
6304 switch (fixp
->fx_size
)
6307 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6308 _("can not do %d byte pc-relative relocation"),
6310 code
= BFD_RELOC_32_PCREL
;
6312 case 1: code
= BFD_RELOC_8_PCREL
; break;
6313 case 2: code
= BFD_RELOC_16_PCREL
; break;
6314 case 4: code
= BFD_RELOC_32_PCREL
; break;
6316 case 8: code
= BFD_RELOC_64_PCREL
; break;
6322 switch (fixp
->fx_size
)
6325 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6326 _("can not do %d byte relocation"),
6328 code
= BFD_RELOC_32
;
6330 case 1: code
= BFD_RELOC_8
; break;
6331 case 2: code
= BFD_RELOC_16
; break;
6332 case 4: code
= BFD_RELOC_32
; break;
6334 case 8: code
= BFD_RELOC_64
; break;
6341 if ((code
== BFD_RELOC_32
6342 || code
== BFD_RELOC_32_PCREL
6343 || code
== BFD_RELOC_X86_64_32S
)
6345 && fixp
->fx_addsy
== GOT_symbol
)
6348 code
= BFD_RELOC_386_GOTPC
;
6350 code
= BFD_RELOC_X86_64_GOTPC32
;
6352 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
6354 && fixp
->fx_addsy
== GOT_symbol
)
6356 code
= BFD_RELOC_X86_64_GOTPC64
;
6359 rel
= (arelent
*) xmalloc (sizeof (arelent
));
6360 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
6361 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6363 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6365 if (!use_rela_relocations
)
6367 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6368 vtable entry to be used in the relocation's section offset. */
6369 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
6370 rel
->address
= fixp
->fx_offset
;
6374 /* Use the rela in 64bit mode. */
6377 if (!fixp
->fx_pcrel
)
6378 rel
->addend
= fixp
->fx_offset
;
6382 case BFD_RELOC_X86_64_PLT32
:
6383 case BFD_RELOC_X86_64_GOT32
:
6384 case BFD_RELOC_X86_64_GOTPCREL
:
6385 case BFD_RELOC_X86_64_TLSGD
:
6386 case BFD_RELOC_X86_64_TLSLD
:
6387 case BFD_RELOC_X86_64_GOTTPOFF
:
6388 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
6389 case BFD_RELOC_X86_64_TLSDESC_CALL
:
6390 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
6393 rel
->addend
= (section
->vma
6395 + fixp
->fx_addnumber
6396 + md_pcrel_from (fixp
));
6401 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
6402 if (rel
->howto
== NULL
)
6404 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6405 _("cannot represent relocation type %s"),
6406 bfd_get_reloc_code_name (code
));
6407 /* Set howto to a garbage value so that we can keep going. */
6408 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
6409 assert (rel
->howto
!= NULL
);
6416 /* Parse operands using Intel syntax. This implements a recursive descent
6417 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6420 FIXME: We do not recognize the full operand grammar defined in the MASM
6421 documentation. In particular, all the structure/union and
6422 high-level macro operands are missing.
6424 Uppercase words are terminals, lower case words are non-terminals.
6425 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6426 bars '|' denote choices. Most grammar productions are implemented in
6427 functions called 'intel_<production>'.
6429 Initial production is 'expr'.
6435 binOp & | AND | \| | OR | ^ | XOR
6437 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6439 constant digits [[ radixOverride ]]
6441 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
6479 => expr expr cmpOp e04
6482 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
6483 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
6485 hexdigit a | b | c | d | e | f
6486 | A | B | C | D | E | F
6492 mulOp * | / | % | MOD | << | SHL | >> | SHR
6496 register specialRegister
6500 segmentRegister CS | DS | ES | FS | GS | SS
6502 specialRegister CR0 | CR2 | CR3 | CR4
6503 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
6504 | TR3 | TR4 | TR5 | TR6 | TR7
6506 We simplify the grammar in obvious places (e.g., register parsing is
6507 done by calling parse_register) and eliminate immediate left recursion
6508 to implement a recursive-descent parser.
6512 expr' cmpOp e04 expr'
6563 /* Parsing structure for the intel syntax parser. Used to implement the
6564 semantic actions for the operand grammar. */
6565 struct intel_parser_s
6567 char *op_string
; /* The string being parsed. */
6568 int got_a_float
; /* Whether the operand is a float. */
6569 int op_modifier
; /* Operand modifier. */
6570 int is_mem
; /* 1 if operand is memory reference. */
6571 int in_offset
; /* >=1 if parsing operand of offset. */
6572 int in_bracket
; /* >=1 if parsing operand in brackets. */
6573 const reg_entry
*reg
; /* Last register reference found. */
6574 char *disp
; /* Displacement string being built. */
6575 char *next_operand
; /* Resume point when splitting operands. */
6578 static struct intel_parser_s intel_parser
;
6580 /* Token structure for parsing intel syntax. */
6583 int code
; /* Token code. */
6584 const reg_entry
*reg
; /* Register entry for register tokens. */
6585 char *str
; /* String representation. */
6588 static struct intel_token cur_token
, prev_token
;
6590 /* Token codes for the intel parser. Since T_SHORT is already used
6591 by COFF, undefine it first to prevent a warning. */
6610 /* Prototypes for intel parser functions. */
6611 static int intel_match_token
PARAMS ((int code
));
6612 static void intel_get_token
PARAMS ((void));
6613 static void intel_putback_token
PARAMS ((void));
6614 static int intel_expr
PARAMS ((void));
6615 static int intel_e04
PARAMS ((void));
6616 static int intel_e05
PARAMS ((void));
6617 static int intel_e06
PARAMS ((void));
6618 static int intel_e09
PARAMS ((void));
6619 static int intel_bracket_expr
PARAMS ((void));
6620 static int intel_e10
PARAMS ((void));
6621 static int intel_e11
PARAMS ((void));
6624 i386_intel_operand (operand_string
, got_a_float
)
6625 char *operand_string
;
6631 p
= intel_parser
.op_string
= xstrdup (operand_string
);
6632 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
6636 /* Initialize token holders. */
6637 cur_token
.code
= prev_token
.code
= T_NIL
;
6638 cur_token
.reg
= prev_token
.reg
= NULL
;
6639 cur_token
.str
= prev_token
.str
= NULL
;
6641 /* Initialize parser structure. */
6642 intel_parser
.got_a_float
= got_a_float
;
6643 intel_parser
.op_modifier
= 0;
6644 intel_parser
.is_mem
= 0;
6645 intel_parser
.in_offset
= 0;
6646 intel_parser
.in_bracket
= 0;
6647 intel_parser
.reg
= NULL
;
6648 intel_parser
.disp
[0] = '\0';
6649 intel_parser
.next_operand
= NULL
;
6651 /* Read the first token and start the parser. */
6653 ret
= intel_expr ();
6658 if (cur_token
.code
!= T_NIL
)
6660 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6661 current_templates
->start
->name
, cur_token
.str
);
6664 /* If we found a memory reference, hand it over to i386_displacement
6665 to fill in the rest of the operand fields. */
6666 else if (intel_parser
.is_mem
)
6668 if ((i
.mem_operands
== 1
6669 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
6670 || i
.mem_operands
== 2)
6672 as_bad (_("too many memory references for '%s'"),
6673 current_templates
->start
->name
);
6678 char *s
= intel_parser
.disp
;
6681 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
6682 /* See the comments in intel_bracket_expr. */
6683 as_warn (_("Treating `%s' as memory reference"), operand_string
);
6685 /* Add the displacement expression. */
6687 ret
= i386_displacement (s
, s
+ strlen (s
));
6690 /* Swap base and index in 16-bit memory operands like
6691 [si+bx]. Since i386_index_check is also used in AT&T
6692 mode we have to do that here. */
6695 && (i
.base_reg
->reg_type
& Reg16
)
6696 && (i
.index_reg
->reg_type
& Reg16
)
6697 && i
.base_reg
->reg_num
>= 6
6698 && i
.index_reg
->reg_num
< 6)
6700 const reg_entry
*base
= i
.index_reg
;
6702 i
.index_reg
= i
.base_reg
;
6705 ret
= i386_index_check (operand_string
);
6710 /* Constant and OFFSET expressions are handled by i386_immediate. */
6711 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
6712 || intel_parser
.reg
== NULL
)
6713 ret
= i386_immediate (intel_parser
.disp
);
6715 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
6717 if (!ret
|| !intel_parser
.next_operand
)
6719 intel_parser
.op_string
= intel_parser
.next_operand
;
6720 this_operand
= i
.operands
++;
6724 free (intel_parser
.disp
);
6729 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6733 expr' cmpOp e04 expr'
6738 /* XXX Implement the comparison operators. */
6739 return intel_e04 ();
6756 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6757 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
6759 if (cur_token
.code
== '+')
6761 else if (cur_token
.code
== '-')
6762 nregs
= NUM_ADDRESS_REGS
;
6766 strcat (intel_parser
.disp
, cur_token
.str
);
6767 intel_match_token (cur_token
.code
);
6778 int nregs
= ~NUM_ADDRESS_REGS
;
6785 if (cur_token
.code
== '&' || cur_token
.code
== '|' || cur_token
.code
== '^')
6789 str
[0] = cur_token
.code
;
6791 strcat (intel_parser
.disp
, str
);
6796 intel_match_token (cur_token
.code
);
6801 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6802 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
6813 int nregs
= ~NUM_ADDRESS_REGS
;
6820 if (cur_token
.code
== '*' || cur_token
.code
== '/' || cur_token
.code
== '%')
6824 str
[0] = cur_token
.code
;
6826 strcat (intel_parser
.disp
, str
);
6828 else if (cur_token
.code
== T_SHL
)
6829 strcat (intel_parser
.disp
, "<<");
6830 else if (cur_token
.code
== T_SHR
)
6831 strcat (intel_parser
.disp
, ">>");
6835 intel_match_token (cur_token
.code
);
6840 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6841 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
6859 int nregs
= ~NUM_ADDRESS_REGS
;
6864 /* Don't consume constants here. */
6865 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6867 /* Need to look one token ahead - if the next token
6868 is a constant, the current token is its sign. */
6871 intel_match_token (cur_token
.code
);
6872 next_code
= cur_token
.code
;
6873 intel_putback_token ();
6874 if (next_code
== T_CONST
)
6878 /* e09 OFFSET e09 */
6879 if (cur_token
.code
== T_OFFSET
)
6882 ++intel_parser
.in_offset
;
6886 else if (cur_token
.code
== T_SHORT
)
6887 intel_parser
.op_modifier
|= 1 << T_SHORT
;
6890 else if (cur_token
.code
== '+')
6891 strcat (intel_parser
.disp
, "+");
6896 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
6902 str
[0] = cur_token
.code
;
6904 strcat (intel_parser
.disp
, str
);
6911 intel_match_token (cur_token
.code
);
6919 /* e09' PTR e10 e09' */
6920 if (cur_token
.code
== T_PTR
)
6924 if (prev_token
.code
== T_BYTE
)
6925 suffix
= BYTE_MNEM_SUFFIX
;
6927 else if (prev_token
.code
== T_WORD
)
6929 if (current_templates
->start
->name
[0] == 'l'
6930 && current_templates
->start
->name
[2] == 's'
6931 && current_templates
->start
->name
[3] == 0)
6932 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6933 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
6934 suffix
= SHORT_MNEM_SUFFIX
;
6936 suffix
= WORD_MNEM_SUFFIX
;
6939 else if (prev_token
.code
== T_DWORD
)
6941 if (current_templates
->start
->name
[0] == 'l'
6942 && current_templates
->start
->name
[2] == 's'
6943 && current_templates
->start
->name
[3] == 0)
6944 suffix
= WORD_MNEM_SUFFIX
;
6945 else if (flag_code
== CODE_16BIT
6946 && (current_templates
->start
->opcode_modifier
6947 & (Jump
| JumpDword
)))
6948 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6949 else if (intel_parser
.got_a_float
== 1) /* "f..." */
6950 suffix
= SHORT_MNEM_SUFFIX
;
6952 suffix
= LONG_MNEM_SUFFIX
;
6955 else if (prev_token
.code
== T_FWORD
)
6957 if (current_templates
->start
->name
[0] == 'l'
6958 && current_templates
->start
->name
[2] == 's'
6959 && current_templates
->start
->name
[3] == 0)
6960 suffix
= LONG_MNEM_SUFFIX
;
6961 else if (!intel_parser
.got_a_float
)
6963 if (flag_code
== CODE_16BIT
)
6964 add_prefix (DATA_PREFIX_OPCODE
);
6965 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6968 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6971 else if (prev_token
.code
== T_QWORD
)
6973 if (intel_parser
.got_a_float
== 1) /* "f..." */
6974 suffix
= LONG_MNEM_SUFFIX
;
6976 suffix
= QWORD_MNEM_SUFFIX
;
6979 else if (prev_token
.code
== T_TBYTE
)
6981 if (intel_parser
.got_a_float
== 1)
6982 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6984 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6987 else if (prev_token
.code
== T_XMMWORD
)
6989 /* XXX ignored for now, but accepted since gcc uses it */
6995 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
6999 /* Operands for jump/call using 'ptr' notation denote absolute
7001 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
))
7002 i
.types
[this_operand
] |= JumpAbsolute
;
7004 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
7008 else if (i
.suffix
!= suffix
)
7010 as_bad (_("Conflicting operand modifiers"));
7016 /* e09' : e10 e09' */
7017 else if (cur_token
.code
== ':')
7019 if (prev_token
.code
!= T_REG
)
7021 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7022 segment/group identifier (which we don't have), using comma
7023 as the operand separator there is even less consistent, since
7024 there all branches only have a single operand. */
7025 if (this_operand
!= 0
7026 || intel_parser
.in_offset
7027 || intel_parser
.in_bracket
7028 || (!(current_templates
->start
->opcode_modifier
7029 & (Jump
|JumpDword
|JumpInterSegment
))
7030 && !(current_templates
->start
->operand_types
[0]
7032 return intel_match_token (T_NIL
);
7033 /* Remember the start of the 2nd operand and terminate 1st
7035 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7036 another expression), but it gets at least the simplest case
7037 (a plain number or symbol on the left side) right. */
7038 intel_parser
.next_operand
= intel_parser
.op_string
;
7039 *--intel_parser
.op_string
= '\0';
7040 return intel_match_token (':');
7048 intel_match_token (cur_token
.code
);
7054 --intel_parser
.in_offset
;
7057 if (NUM_ADDRESS_REGS
> nregs
)
7059 as_bad (_("Invalid operand to `OFFSET'"));
7062 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
7065 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
7066 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
7071 intel_bracket_expr ()
7073 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
7074 const char *start
= intel_parser
.op_string
;
7077 if (i
.op
[this_operand
].regs
)
7078 return intel_match_token (T_NIL
);
7080 intel_match_token ('[');
7082 /* Mark as a memory operand only if it's not already known to be an
7083 offset expression. If it's an offset expression, we need to keep
7085 if (!intel_parser
.in_offset
)
7087 ++intel_parser
.in_bracket
;
7089 /* Operands for jump/call inside brackets denote absolute addresses. */
7090 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
))
7091 i
.types
[this_operand
] |= JumpAbsolute
;
7093 /* Unfortunately gas always diverged from MASM in a respect that can't
7094 be easily fixed without risking to break code sequences likely to be
7095 encountered (the testsuite even check for this): MASM doesn't consider
7096 an expression inside brackets unconditionally as a memory reference.
7097 When that is e.g. a constant, an offset expression, or the sum of the
7098 two, this is still taken as a constant load. gas, however, always
7099 treated these as memory references. As a compromise, we'll try to make
7100 offset expressions inside brackets work the MASM way (since that's
7101 less likely to be found in real world code), but make constants alone
7102 continue to work the traditional gas way. In either case, issue a
7104 intel_parser
.op_modifier
&= ~was_offset
;
7107 strcat (intel_parser
.disp
, "[");
7109 /* Add a '+' to the displacement string if necessary. */
7110 if (*intel_parser
.disp
!= '\0'
7111 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
7112 strcat (intel_parser
.disp
, "+");
7115 && (len
= intel_parser
.op_string
- start
- 1,
7116 intel_match_token (']')))
7118 /* Preserve brackets when the operand is an offset expression. */
7119 if (intel_parser
.in_offset
)
7120 strcat (intel_parser
.disp
, "]");
7123 --intel_parser
.in_bracket
;
7124 if (i
.base_reg
|| i
.index_reg
)
7125 intel_parser
.is_mem
= 1;
7126 if (!intel_parser
.is_mem
)
7128 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
7129 /* Defer the warning until all of the operand was parsed. */
7130 intel_parser
.is_mem
= -1;
7131 else if (!quiet_warnings
)
7132 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len
, start
, len
, start
);
7135 intel_parser
.op_modifier
|= was_offset
;
7152 while (cur_token
.code
== '[')
7154 if (!intel_bracket_expr ())
7179 switch (cur_token
.code
)
7183 intel_match_token ('(');
7184 strcat (intel_parser
.disp
, "(");
7186 if (intel_expr () && intel_match_token (')'))
7188 strcat (intel_parser
.disp
, ")");
7195 return intel_bracket_expr ();
7200 strcat (intel_parser
.disp
, cur_token
.str
);
7201 intel_match_token (cur_token
.code
);
7203 /* Mark as a memory operand only if it's not already known to be an
7204 offset expression. */
7205 if (!intel_parser
.in_offset
)
7206 intel_parser
.is_mem
= 1;
7213 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
7215 intel_match_token (T_REG
);
7217 /* Check for segment change. */
7218 if (cur_token
.code
== ':')
7220 if (!(reg
->reg_type
& (SReg2
| SReg3
)))
7222 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
7225 else if (i
.seg
[i
.mem_operands
])
7226 as_warn (_("Extra segment override ignored"));
7229 if (!intel_parser
.in_offset
)
7230 intel_parser
.is_mem
= 1;
7231 switch (reg
->reg_num
)
7234 i
.seg
[i
.mem_operands
] = &es
;
7237 i
.seg
[i
.mem_operands
] = &cs
;
7240 i
.seg
[i
.mem_operands
] = &ss
;
7243 i
.seg
[i
.mem_operands
] = &ds
;
7246 i
.seg
[i
.mem_operands
] = &fs
;
7249 i
.seg
[i
.mem_operands
] = &gs
;
7255 /* Not a segment register. Check for register scaling. */
7256 else if (cur_token
.code
== '*')
7258 if (!intel_parser
.in_bracket
)
7260 as_bad (_("Register scaling only allowed in memory operands"));
7264 if (reg
->reg_type
& Reg16
) /* Disallow things like [si*1]. */
7265 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
7266 else if (i
.index_reg
)
7267 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
7269 /* What follows must be a valid scale. */
7270 intel_match_token ('*');
7272 i
.types
[this_operand
] |= BaseIndex
;
7274 /* Set the scale after setting the register (otherwise,
7275 i386_scale will complain) */
7276 if (cur_token
.code
== '+' || cur_token
.code
== '-')
7278 char *str
, sign
= cur_token
.code
;
7279 intel_match_token (cur_token
.code
);
7280 if (cur_token
.code
!= T_CONST
)
7282 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7286 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
7287 strcpy (str
+ 1, cur_token
.str
);
7289 if (!i386_scale (str
))
7293 else if (!i386_scale (cur_token
.str
))
7295 intel_match_token (cur_token
.code
);
7298 /* No scaling. If this is a memory operand, the register is either a
7299 base register (first occurrence) or an index register (second
7301 else if (intel_parser
.in_bracket
)
7306 else if (!i
.index_reg
)
7310 as_bad (_("Too many register references in memory operand"));
7314 i
.types
[this_operand
] |= BaseIndex
;
7317 /* It's neither base nor index. */
7318 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
7320 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
7321 i
.op
[this_operand
].regs
= reg
;
7326 as_bad (_("Invalid use of register"));
7330 /* Since registers are not part of the displacement string (except
7331 when we're parsing offset operands), we may need to remove any
7332 preceding '+' from the displacement string. */
7333 if (*intel_parser
.disp
!= '\0'
7334 && !intel_parser
.in_offset
)
7336 char *s
= intel_parser
.disp
;
7337 s
+= strlen (s
) - 1;
7360 intel_match_token (cur_token
.code
);
7362 if (cur_token
.code
== T_PTR
)
7365 /* It must have been an identifier. */
7366 intel_putback_token ();
7367 cur_token
.code
= T_ID
;
7373 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
7377 /* The identifier represents a memory reference only if it's not
7378 preceded by an offset modifier and if it's not an equate. */
7379 symbolP
= symbol_find(cur_token
.str
);
7380 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
7381 intel_parser
.is_mem
= 1;
7389 char *save_str
, sign
= 0;
7391 /* Allow constants that start with `+' or `-'. */
7392 if (cur_token
.code
== '-' || cur_token
.code
== '+')
7394 sign
= cur_token
.code
;
7395 intel_match_token (cur_token
.code
);
7396 if (cur_token
.code
!= T_CONST
)
7398 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7404 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
7405 strcpy (save_str
+ !!sign
, cur_token
.str
);
7409 /* Get the next token to check for register scaling. */
7410 intel_match_token (cur_token
.code
);
7412 /* Check if this constant is a scaling factor for an index register. */
7413 if (cur_token
.code
== '*')
7415 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
7417 const reg_entry
*reg
= cur_token
.reg
;
7419 if (!intel_parser
.in_bracket
)
7421 as_bad (_("Register scaling only allowed in memory operands"));
7425 if (reg
->reg_type
& Reg16
) /* Disallow things like [1*si]. */
7426 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
7427 else if (i
.index_reg
)
7428 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
7430 /* The constant is followed by `* reg', so it must be
7433 i
.types
[this_operand
] |= BaseIndex
;
7435 /* Set the scale after setting the register (otherwise,
7436 i386_scale will complain) */
7437 if (!i386_scale (save_str
))
7439 intel_match_token (T_REG
);
7441 /* Since registers are not part of the displacement
7442 string, we may need to remove any preceding '+' from
7443 the displacement string. */
7444 if (*intel_parser
.disp
!= '\0')
7446 char *s
= intel_parser
.disp
;
7447 s
+= strlen (s
) - 1;
7457 /* The constant was not used for register scaling. Since we have
7458 already consumed the token following `*' we now need to put it
7459 back in the stream. */
7460 intel_putback_token ();
7463 /* Add the constant to the displacement string. */
7464 strcat (intel_parser
.disp
, save_str
);
7471 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
7475 /* Match the given token against cur_token. If they match, read the next
7476 token from the operand string. */
7478 intel_match_token (code
)
7481 if (cur_token
.code
== code
)
7488 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
7493 /* Read a new token from intel_parser.op_string and store it in cur_token. */
7498 const reg_entry
*reg
;
7499 struct intel_token new_token
;
7501 new_token
.code
= T_NIL
;
7502 new_token
.reg
= NULL
;
7503 new_token
.str
= NULL
;
7505 /* Free the memory allocated to the previous token and move
7506 cur_token to prev_token. */
7508 free (prev_token
.str
);
7510 prev_token
= cur_token
;
7512 /* Skip whitespace. */
7513 while (is_space_char (*intel_parser
.op_string
))
7514 intel_parser
.op_string
++;
7516 /* Return an empty token if we find nothing else on the line. */
7517 if (*intel_parser
.op_string
== '\0')
7519 cur_token
= new_token
;
7523 /* The new token cannot be larger than the remainder of the operand
7525 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
7526 new_token
.str
[0] = '\0';
7528 if (strchr ("0123456789", *intel_parser
.op_string
))
7530 char *p
= new_token
.str
;
7531 char *q
= intel_parser
.op_string
;
7532 new_token
.code
= T_CONST
;
7534 /* Allow any kind of identifier char to encompass floating point and
7535 hexadecimal numbers. */
7536 while (is_identifier_char (*q
))
7540 /* Recognize special symbol names [0-9][bf]. */
7541 if (strlen (intel_parser
.op_string
) == 2
7542 && (intel_parser
.op_string
[1] == 'b'
7543 || intel_parser
.op_string
[1] == 'f'))
7544 new_token
.code
= T_ID
;
7547 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
7549 size_t len
= end_op
- intel_parser
.op_string
;
7551 new_token
.code
= T_REG
;
7552 new_token
.reg
= reg
;
7554 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
7555 new_token
.str
[len
] = '\0';
7558 else if (is_identifier_char (*intel_parser
.op_string
))
7560 char *p
= new_token
.str
;
7561 char *q
= intel_parser
.op_string
;
7563 /* A '.' or '$' followed by an identifier char is an identifier.
7564 Otherwise, it's operator '.' followed by an expression. */
7565 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
7567 new_token
.code
= '.';
7568 new_token
.str
[0] = '.';
7569 new_token
.str
[1] = '\0';
7573 while (is_identifier_char (*q
) || *q
== '@')
7577 if (strcasecmp (new_token
.str
, "NOT") == 0)
7578 new_token
.code
= '~';
7580 else if (strcasecmp (new_token
.str
, "MOD") == 0)
7581 new_token
.code
= '%';
7583 else if (strcasecmp (new_token
.str
, "AND") == 0)
7584 new_token
.code
= '&';
7586 else if (strcasecmp (new_token
.str
, "OR") == 0)
7587 new_token
.code
= '|';
7589 else if (strcasecmp (new_token
.str
, "XOR") == 0)
7590 new_token
.code
= '^';
7592 else if (strcasecmp (new_token
.str
, "SHL") == 0)
7593 new_token
.code
= T_SHL
;
7595 else if (strcasecmp (new_token
.str
, "SHR") == 0)
7596 new_token
.code
= T_SHR
;
7598 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
7599 new_token
.code
= T_BYTE
;
7601 else if (strcasecmp (new_token
.str
, "WORD") == 0)
7602 new_token
.code
= T_WORD
;
7604 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
7605 new_token
.code
= T_DWORD
;
7607 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
7608 new_token
.code
= T_FWORD
;
7610 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
7611 new_token
.code
= T_QWORD
;
7613 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
7614 /* XXX remove (gcc still uses it) */
7615 || strcasecmp (new_token
.str
, "XWORD") == 0)
7616 new_token
.code
= T_TBYTE
;
7618 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
7619 || strcasecmp (new_token
.str
, "OWORD") == 0)
7620 new_token
.code
= T_XMMWORD
;
7622 else if (strcasecmp (new_token
.str
, "PTR") == 0)
7623 new_token
.code
= T_PTR
;
7625 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
7626 new_token
.code
= T_SHORT
;
7628 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
7630 new_token
.code
= T_OFFSET
;
7632 /* ??? This is not mentioned in the MASM grammar but gcc
7633 makes use of it with -mintel-syntax. OFFSET may be
7634 followed by FLAT: */
7635 if (strncasecmp (q
, " FLAT:", 6) == 0)
7636 strcat (new_token
.str
, " FLAT:");
7639 /* ??? This is not mentioned in the MASM grammar. */
7640 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
7642 new_token
.code
= T_OFFSET
;
7644 strcat (new_token
.str
, ":");
7646 as_bad (_("`:' expected"));
7650 new_token
.code
= T_ID
;
7654 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
7656 new_token
.code
= *intel_parser
.op_string
;
7657 new_token
.str
[0] = *intel_parser
.op_string
;
7658 new_token
.str
[1] = '\0';
7661 else if (strchr ("<>", *intel_parser
.op_string
)
7662 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
7664 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
7665 new_token
.str
[0] = *intel_parser
.op_string
;
7666 new_token
.str
[1] = *intel_parser
.op_string
;
7667 new_token
.str
[2] = '\0';
7671 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
7673 intel_parser
.op_string
+= strlen (new_token
.str
);
7674 cur_token
= new_token
;
7677 /* Put cur_token back into the token stream and make cur_token point to
7680 intel_putback_token ()
7682 if (cur_token
.code
!= T_NIL
)
7684 intel_parser
.op_string
-= strlen (cur_token
.str
);
7685 free (cur_token
.str
);
7687 cur_token
= prev_token
;
7689 /* Forget prev_token. */
7690 prev_token
.code
= T_NIL
;
7691 prev_token
.reg
= NULL
;
7692 prev_token
.str
= NULL
;
7696 tc_x86_regname_to_dw2regnum (char *regname
)
7698 unsigned int regnum
;
7699 unsigned int regnames_count
;
7700 static const char *const regnames_32
[] =
7702 "eax", "ecx", "edx", "ebx",
7703 "esp", "ebp", "esi", "edi",
7704 "eip", "eflags", NULL
,
7705 "st0", "st1", "st2", "st3",
7706 "st4", "st5", "st6", "st7",
7708 "xmm0", "xmm1", "xmm2", "xmm3",
7709 "xmm4", "xmm5", "xmm6", "xmm7",
7710 "mm0", "mm1", "mm2", "mm3",
7711 "mm4", "mm5", "mm6", "mm7",
7712 "fcw", "fsw", "mxcsr",
7713 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
7716 static const char *const regnames_64
[] =
7718 "rax", "rdx", "rcx", "rbx",
7719 "rsi", "rdi", "rbp", "rsp",
7720 "r8", "r9", "r10", "r11",
7721 "r12", "r13", "r14", "r15",
7723 "xmm0", "xmm1", "xmm2", "xmm3",
7724 "xmm4", "xmm5", "xmm6", "xmm7",
7725 "xmm8", "xmm9", "xmm10", "xmm11",
7726 "xmm12", "xmm13", "xmm14", "xmm15",
7727 "st0", "st1", "st2", "st3",
7728 "st4", "st5", "st6", "st7",
7729 "mm0", "mm1", "mm2", "mm3",
7730 "mm4", "mm5", "mm6", "mm7",
7732 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
7733 "fs.base", "gs.base", NULL
, NULL
,
7735 "mxcsr", "fcw", "fsw"
7737 const char *const *regnames
;
7739 if (flag_code
== CODE_64BIT
)
7741 regnames
= regnames_64
;
7742 regnames_count
= ARRAY_SIZE (regnames_64
);
7746 regnames
= regnames_32
;
7747 regnames_count
= ARRAY_SIZE (regnames_32
);
7750 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
7751 if (regnames
[regnum
] != NULL
7752 && strcmp (regname
, regnames
[regnum
]) == 0)
7759 tc_x86_frame_initial_instructions (void)
7761 static unsigned int sp_regno
;
7764 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
7767 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
7768 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
7772 i386_elf_section_type (const char *str
, size_t len
)
7774 if (flag_code
== CODE_64BIT
7775 && len
== sizeof ("unwind") - 1
7776 && strncmp (str
, "unwind", 6) == 0)
7777 return SHT_X86_64_UNWIND
;
7784 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
7788 expr
.X_op
= O_secrel
;
7789 expr
.X_add_symbol
= symbol
;
7790 expr
.X_add_number
= 0;
7791 emit_expr (&expr
, size
);
7795 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7796 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7799 x86_64_section_letter (int letter
, char **ptr_msg
)
7801 if (flag_code
== CODE_64BIT
)
7804 return SHF_X86_64_LARGE
;
7806 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7809 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
7814 x86_64_section_word (char *str
, size_t len
)
7816 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
7817 return SHF_X86_64_LARGE
;
7823 handle_large_common (int small ATTRIBUTE_UNUSED
)
7825 if (flag_code
!= CODE_64BIT
)
7827 s_comm_internal (0, elf_common_parse
);
7828 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7832 static segT lbss_section
;
7833 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
7834 asection
*saved_bss_section
= bss_section
;
7836 if (lbss_section
== NULL
)
7838 flagword applicable
;
7840 subsegT subseg
= now_subseg
;
7842 /* The .lbss section is for local .largecomm symbols. */
7843 lbss_section
= subseg_new (".lbss", 0);
7844 applicable
= bfd_applicable_section_flags (stdoutput
);
7845 bfd_set_section_flags (stdoutput
, lbss_section
,
7846 applicable
& SEC_ALLOC
);
7847 seg_info (lbss_section
)->bss
= 1;
7849 subseg_set (seg
, subseg
);
7852 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
7853 bss_section
= lbss_section
;
7855 s_comm_internal (0, elf_common_parse
);
7857 elf_com_section_ptr
= saved_com_section_ptr
;
7858 bss_section
= saved_bss_section
;
7861 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */