1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Intel 80386 machine specific gas.
23 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
24 Bugs & suggestions are completely welcome. This is free software.
25 Please help us make it better. */
31 #include "opcode/i386.h"
33 #ifndef REGISTER_WARNINGS
34 #define REGISTER_WARNINGS 1
37 #ifndef INFER_ADDR_PREFIX
38 #define INFER_ADDR_PREFIX 1
41 #ifndef SCALE1_WHEN_NO_INDEX
42 /* Specifying a scale factor besides 1 when there is no index is
43 futile. eg. `mov (%ebx,2),%al' does exactly the same as
44 `mov (%ebx),%al'. To slavishly follow what the programmer
45 specified, set SCALE1_WHEN_NO_INDEX to 0. */
46 #define SCALE1_WHEN_NO_INDEX 1
52 static unsigned int mode_from_disp_size
PARAMS ((unsigned int));
53 static int fits_in_signed_byte
PARAMS ((offsetT
));
54 static int fits_in_unsigned_byte
PARAMS ((offsetT
));
55 static int fits_in_unsigned_word
PARAMS ((offsetT
));
56 static int fits_in_signed_word
PARAMS ((offsetT
));
57 static int smallest_imm_type
PARAMS ((offsetT
));
58 static offsetT offset_in_range
PARAMS ((offsetT
, int));
59 static int add_prefix
PARAMS ((unsigned int));
60 static void set_16bit_code_flag
PARAMS ((int));
61 static void set_16bit_gcc_code_flag
PARAMS ((int));
62 static void set_intel_syntax
PARAMS ((int));
63 static void set_cpu_arch
PARAMS ((int));
66 static bfd_reloc_code_real_type reloc
67 PARAMS ((int, int, bfd_reloc_code_real_type
));
70 /* 'md_assemble ()' gathers together information and puts it into a
77 const reg_entry
*regs
;
82 /* TM holds the template for the insn were currently assembling. */
85 /* SUFFIX holds the instruction mnemonic suffix if given.
86 (e.g. 'l' for 'movl') */
89 /* OPERANDS gives the number of given operands. */
90 unsigned int operands
;
92 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
93 of given register, displacement, memory operands and immediate
95 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
97 /* TYPES [i] is the type (see above #defines) which tells us how to
98 use OP[i] for the corresponding operand. */
99 unsigned int types
[MAX_OPERANDS
];
101 /* Displacement expression, immediate expression, or register for each
103 union i386_op op
[MAX_OPERANDS
];
105 /* Relocation type for operand */
107 enum bfd_reloc_code_real disp_reloc
[MAX_OPERANDS
];
109 int disp_reloc
[MAX_OPERANDS
];
112 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
113 the base index byte below. */
114 const reg_entry
*base_reg
;
115 const reg_entry
*index_reg
;
116 unsigned int log2_scale_factor
;
118 /* SEG gives the seg_entries of this insn. They are zero unless
119 explicit segment overrides are given. */
120 const seg_entry
*seg
[2]; /* segments for memory operands (if given) */
122 /* PREFIX holds all the given prefix opcodes (usually null).
123 PREFIXES is the number of prefix opcodes. */
124 unsigned int prefixes
;
125 unsigned char prefix
[MAX_PREFIXES
];
127 /* RM and SIB are the modrm byte and the sib byte where the
128 addressing modes of this insn are encoded. */
134 typedef struct _i386_insn i386_insn
;
136 /* List of chars besides those in app.c:symbol_chars that can start an
137 operand. Used to prevent the scrubber eating vital white-space. */
139 const char extra_symbol_chars
[] = "*%-(@";
141 const char extra_symbol_chars
[] = "*%-(";
144 /* This array holds the chars that always start a comment. If the
145 pre-processor is disabled, these aren't very useful */
146 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
147 /* Putting '/' here makes it impossible to use the divide operator.
148 However, we need it for compatibility with SVR4 systems. */
149 const char comment_chars
[] = "#/";
150 #define PREFIX_SEPARATOR '\\'
152 const char comment_chars
[] = "#";
153 #define PREFIX_SEPARATOR '/'
156 /* This array holds the chars that only start a comment at the beginning of
157 a line. If the line seems to have the form '# 123 filename'
158 .line and .file directives will appear in the pre-processed output */
159 /* Note that input_file.c hand checks for '#' at the beginning of the
160 first line of the input file. This is because the compiler outputs
161 #NO_APP at the beginning of its output. */
162 /* Also note that comments started like this one will always work if
163 '/' isn't otherwise defined. */
164 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
165 const char line_comment_chars
[] = "";
167 const char line_comment_chars
[] = "/";
170 const char line_separator_chars
[] = ";";
172 /* Chars that can be used to separate mant from exp in floating point nums */
173 const char EXP_CHARS
[] = "eE";
175 /* Chars that mean this number is a floating point constant */
178 const char FLT_CHARS
[] = "fFdDxX";
180 /* tables for lexical analysis */
181 static char mnemonic_chars
[256];
182 static char register_chars
[256];
183 static char operand_chars
[256];
184 static char identifier_chars
[256];
185 static char digit_chars
[256];
188 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
189 #define is_operand_char(x) (operand_chars[(unsigned char) x])
190 #define is_register_char(x) (register_chars[(unsigned char) x])
191 #define is_space_char(x) ((x) == ' ')
192 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
193 #define is_digit_char(x) (digit_chars[(unsigned char) x])
195 /* put here all non-digit non-letter charcters that may occur in an operand */
196 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
198 /* md_assemble() always leaves the strings it's passed unaltered. To
199 effect this we maintain a stack of saved characters that we've smashed
200 with '\0's (indicating end of strings for various sub-fields of the
201 assembler instruction). */
202 static char save_stack
[32];
203 static char *save_stack_p
; /* stack pointer */
204 #define END_STRING_AND_SAVE(s) \
205 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
206 #define RESTORE_END_STRING(s) \
207 do { *(s) = *--save_stack_p; } while (0)
209 /* The instruction we're assembling. */
212 /* Possible templates for current insn. */
213 static const templates
*current_templates
;
215 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
216 static expressionS disp_expressions
[2], im_expressions
[2];
218 /* Current operand we are working on. */
219 static int this_operand
;
221 /* 1 if we're writing 16-bit code,
223 static int flag_16bit_code
;
225 /* 1 for intel syntax,
227 static int intel_syntax
= 0;
229 /* 1 if register prefix % not required. */
230 static int allow_naked_reg
= 0;
232 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
233 leave, push, and pop instructions so that gcc has the same stack
234 frame as in 32 bit mode. */
235 static char stackop_size
= '\0';
237 /* Non-zero to quieten some warnings. */
238 static int quiet_warnings
= 0;
241 static const char *cpu_arch_name
= NULL
;
243 /* CPU feature flags. */
244 static unsigned int cpu_arch_flags
= 0;
246 /* Interface to relax_segment.
247 There are 2 relax states for 386 jump insns: one for conditional &
248 one for unconditional jumps. This is because these two types of
249 jumps add different sizes to frags when we're figuring out what
250 sort of jump to choose to reach a given label. */
253 #define COND_JUMP 1 /* Conditional jump. */
254 #define UNCOND_JUMP 2 /* Unconditional jump. */
258 #define SMALL16 (SMALL|CODE16)
260 #define BIG16 (BIG|CODE16)
264 #define INLINE __inline__
270 #define ENCODE_RELAX_STATE(type,size) \
271 ((relax_substateT)((type<<2) | (size)))
272 #define SIZE_FROM_RELAX_STATE(s) \
273 ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) )
275 /* This table is used by relax_frag to promote short jumps to long
276 ones where necessary. SMALL (short) jumps may be promoted to BIG
277 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
278 don't allow a short jump in a 32 bit code segment to be promoted to
279 a 16 bit offset jump because it's slower (requires data size
280 prefix), and doesn't work, unless the destination is in the bottom
281 64k of the code segment (The top 16 bits of eip are zeroed). */
283 const relax_typeS md_relax_table
[] =
286 1) most positive reach of this state,
287 2) most negative reach of this state,
288 3) how many bytes this mode will add to the size of the current frag
289 4) which index into the table to try if we can't fit into this one.
296 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
297 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
298 /* dword conditionals adds 4 bytes to frag:
299 1 extra opcode byte, 3 extra displacement bytes. */
301 /* word conditionals add 2 bytes to frag:
302 1 extra opcode byte, 1 extra displacement byte. */
305 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
306 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
307 /* dword jmp adds 3 bytes to frag:
308 0 extra opcode bytes, 3 extra displacement bytes. */
310 /* word jmp adds 1 byte to frag:
311 0 extra opcode bytes, 1 extra displacement byte. */
316 static const arch_entry cpu_arch
[] = {
318 {"i186", Cpu086
|Cpu186
},
319 {"i286", Cpu086
|Cpu186
|Cpu286
},
320 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
321 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
322 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
323 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
324 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
325 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
326 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
|Cpu3dnow
},
327 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|Cpu3dnow
},
332 i386_align_code (fragP
, count
)
336 /* Various efficient no-op patterns for aligning code labels. */
337 /* Note: Don't try to assemble the instructions in the comments. */
338 /* 0L and 0w are not legal */
339 static const char f32_1
[] =
341 static const char f32_2
[] =
342 {0x89,0xf6}; /* movl %esi,%esi */
343 static const char f32_3
[] =
344 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
345 static const char f32_4
[] =
346 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
347 static const char f32_5
[] =
349 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
350 static const char f32_6
[] =
351 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
352 static const char f32_7
[] =
353 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
354 static const char f32_8
[] =
356 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
357 static const char f32_9
[] =
358 {0x89,0xf6, /* movl %esi,%esi */
359 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
360 static const char f32_10
[] =
361 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
362 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
363 static const char f32_11
[] =
364 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
365 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
366 static const char f32_12
[] =
367 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
368 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
369 static const char f32_13
[] =
370 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
371 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
372 static const char f32_14
[] =
373 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
374 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
375 static const char f32_15
[] =
376 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
377 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
378 static const char f16_3
[] =
379 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
380 static const char f16_4
[] =
381 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
382 static const char f16_5
[] =
384 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
385 static const char f16_6
[] =
386 {0x89,0xf6, /* mov %si,%si */
387 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
388 static const char f16_7
[] =
389 {0x8d,0x74,0x00, /* lea 0(%si),%si */
390 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
391 static const char f16_8
[] =
392 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
393 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
394 static const char *const f32_patt
[] = {
395 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
396 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
398 static const char *const f16_patt
[] = {
399 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
400 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
403 if (count
> 0 && count
<= 15)
407 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
408 f16_patt
[count
- 1], count
);
410 /* Adjust jump offset. */
411 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
414 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
415 f32_patt
[count
- 1], count
);
416 fragP
->fr_var
= count
;
420 static char *output_invalid
PARAMS ((int c
));
421 static int i386_operand
PARAMS ((char *operand_string
));
422 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
423 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
427 static void s_bss
PARAMS ((int));
430 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
432 static INLINE
unsigned int
433 mode_from_disp_size (t
)
436 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
)) ? 2 : 0;
440 fits_in_signed_byte (num
)
443 return (num
>= -128) && (num
<= 127);
447 fits_in_unsigned_byte (num
)
450 return (num
& 0xff) == num
;
454 fits_in_unsigned_word (num
)
457 return (num
& 0xffff) == num
;
461 fits_in_signed_word (num
)
464 return (-32768 <= num
) && (num
<= 32767);
468 smallest_imm_type (num
)
471 if (cpu_arch_flags
!= 0
472 && cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
))
474 /* This code is disabled on the 486 because all the Imm1 forms
475 in the opcode table are slower on the i486. They're the
476 versions with the implicitly specified single-position
477 displacement, which has another syntax if you really want to
480 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
;
482 return (fits_in_signed_byte (num
)
483 ? (Imm8S
| Imm8
| Imm16
| Imm32
)
484 : fits_in_unsigned_byte (num
)
485 ? (Imm8
| Imm16
| Imm32
)
486 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
492 offset_in_range (val
, size
)
500 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
501 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
502 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
506 /* If BFD64, sign extend val. */
507 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
508 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
510 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
512 char buf1
[40], buf2
[40];
514 sprint_value (buf1
, val
);
515 sprint_value (buf2
, val
& mask
);
516 as_warn (_("%s shortened to %s"), buf1
, buf2
);
521 /* Returns 0 if attempting to add a prefix where one from the same
522 class already exists, 1 if non rep/repne added, 2 if rep/repne
536 case CS_PREFIX_OPCODE
:
537 case DS_PREFIX_OPCODE
:
538 case ES_PREFIX_OPCODE
:
539 case FS_PREFIX_OPCODE
:
540 case GS_PREFIX_OPCODE
:
541 case SS_PREFIX_OPCODE
:
545 case REPNE_PREFIX_OPCODE
:
546 case REPE_PREFIX_OPCODE
:
549 case LOCK_PREFIX_OPCODE
:
557 case ADDR_PREFIX_OPCODE
:
561 case DATA_PREFIX_OPCODE
:
568 as_bad (_("same type of prefix used twice"));
573 i
.prefix
[q
] = prefix
;
578 set_16bit_code_flag (new_16bit_code_flag
)
579 int new_16bit_code_flag
;
581 flag_16bit_code
= new_16bit_code_flag
;
586 set_16bit_gcc_code_flag (new_16bit_code_flag
)
587 int new_16bit_code_flag
;
589 flag_16bit_code
= new_16bit_code_flag
;
590 stackop_size
= new_16bit_code_flag
? 'l' : '\0';
594 set_intel_syntax (syntax_flag
)
597 /* Find out if register prefixing is specified. */
598 int ask_naked_reg
= 0;
601 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
603 char *string
= input_line_pointer
;
604 int e
= get_symbol_end ();
606 if (strcmp (string
, "prefix") == 0)
608 else if (strcmp (string
, "noprefix") == 0)
611 as_bad (_("bad argument to syntax directive."));
612 *input_line_pointer
= e
;
614 demand_empty_rest_of_line ();
616 intel_syntax
= syntax_flag
;
618 if (ask_naked_reg
== 0)
621 allow_naked_reg
= (intel_syntax
622 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
624 /* Conservative default. */
629 allow_naked_reg
= (ask_naked_reg
< 0);
634 int dummy ATTRIBUTE_UNUSED
;
638 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
640 char *string
= input_line_pointer
;
641 int e
= get_symbol_end ();
644 for (i
= 0; cpu_arch
[i
].name
; i
++)
646 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
648 cpu_arch_name
= cpu_arch
[i
].name
;
649 cpu_arch_flags
= cpu_arch
[i
].flags
;
653 if (!cpu_arch
[i
].name
)
654 as_bad (_("no such architecture: `%s'"), string
);
656 *input_line_pointer
= e
;
659 as_bad (_("missing cpu architecture"));
661 demand_empty_rest_of_line ();
664 const pseudo_typeS md_pseudo_table
[] =
666 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
667 {"align", s_align_bytes
, 0},
669 {"align", s_align_ptwo
, 0},
671 {"arch", set_cpu_arch
, 0},
675 {"ffloat", float_cons
, 'f'},
676 {"dfloat", float_cons
, 'd'},
677 {"tfloat", float_cons
, 'x'},
679 {"noopt", s_ignore
, 0},
680 {"optim", s_ignore
, 0},
681 {"code16gcc", set_16bit_gcc_code_flag
, 1},
682 {"code16", set_16bit_code_flag
, 1},
683 {"code32", set_16bit_code_flag
, 0},
684 {"intel_syntax", set_intel_syntax
, 1},
685 {"att_syntax", set_intel_syntax
, 0},
689 /* For interface with expression (). */
690 extern char *input_line_pointer
;
692 /* Hash table for instruction mnemonic lookup. */
693 static struct hash_control
*op_hash
;
695 /* Hash table for register lookup. */
696 static struct hash_control
*reg_hash
;
701 const char *hash_err
;
703 /* Initialize op_hash hash table. */
704 op_hash
= hash_new ();
707 register const template *optab
;
708 register templates
*core_optab
;
710 /* Setup for loop. */
712 core_optab
= (templates
*) xmalloc (sizeof (templates
));
713 core_optab
->start
= optab
;
718 if (optab
->name
== NULL
719 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
721 /* different name --> ship out current template list;
722 add to hash table; & begin anew. */
723 core_optab
->end
= optab
;
724 hash_err
= hash_insert (op_hash
,
730 as_fatal (_("Internal Error: Can't hash %s: %s"),
734 if (optab
->name
== NULL
)
736 core_optab
= (templates
*) xmalloc (sizeof (templates
));
737 core_optab
->start
= optab
;
742 /* Initialize reg_hash hash table. */
743 reg_hash
= hash_new ();
745 register const reg_entry
*regtab
;
747 for (regtab
= i386_regtab
;
748 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
751 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
757 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
762 for (c
= 0; c
< 256; c
++)
767 mnemonic_chars
[c
] = c
;
768 register_chars
[c
] = c
;
769 operand_chars
[c
] = c
;
771 else if (islower (c
))
773 mnemonic_chars
[c
] = c
;
774 register_chars
[c
] = c
;
775 operand_chars
[c
] = c
;
777 else if (isupper (c
))
779 mnemonic_chars
[c
] = tolower (c
);
780 register_chars
[c
] = mnemonic_chars
[c
];
781 operand_chars
[c
] = c
;
784 if (isalpha (c
) || isdigit (c
))
785 identifier_chars
[c
] = c
;
788 identifier_chars
[c
] = c
;
789 operand_chars
[c
] = c
;
794 identifier_chars
['@'] = '@';
796 digit_chars
['-'] = '-';
797 identifier_chars
['_'] = '_';
798 identifier_chars
['.'] = '.';
800 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
801 operand_chars
[(unsigned char) *p
] = *p
;
804 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
805 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
807 record_alignment (text_section
, 2);
808 record_alignment (data_section
, 2);
809 record_alignment (bss_section
, 2);
815 i386_print_statistics (file
)
818 hash_print_statistics (file
, "i386 opcode", op_hash
);
819 hash_print_statistics (file
, "i386 register", reg_hash
);
824 /* debugging routines for md_assemble */
825 static void pi
PARAMS ((char *, i386_insn
*));
826 static void pte
PARAMS ((template *));
827 static void pt
PARAMS ((unsigned int));
828 static void pe
PARAMS ((expressionS
*));
829 static void ps
PARAMS ((symbolS
*));
836 register template *p
;
839 fprintf (stdout
, "%s: template ", line
);
841 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x",
842 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
843 fprintf (stdout
, " base %x index %x scale %x\n",
844 x
->bi
.base
, x
->bi
.index
, x
->bi
.scale
);
845 for (i
= 0; i
< x
->operands
; i
++)
847 fprintf (stdout
, " #%d: ", i
+ 1);
849 fprintf (stdout
, "\n");
851 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
852 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
853 if (x
->types
[i
] & Imm
)
855 if (x
->types
[i
] & Disp
)
865 fprintf (stdout
, " %d operands ", t
->operands
);
866 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
867 if (t
->extension_opcode
!= None
)
868 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
869 if (t
->opcode_modifier
& D
)
870 fprintf (stdout
, "D");
871 if (t
->opcode_modifier
& W
)
872 fprintf (stdout
, "W");
873 fprintf (stdout
, "\n");
874 for (i
= 0; i
< t
->operands
; i
++)
876 fprintf (stdout
, " #%d type ", i
+ 1);
877 pt (t
->operand_types
[i
]);
878 fprintf (stdout
, "\n");
886 fprintf (stdout
, " operation %d\n", e
->X_op
);
887 fprintf (stdout
, " add_number %ld (%lx)\n",
888 (long) e
->X_add_number
, (long) e
->X_add_number
);
891 fprintf (stdout
, " add_symbol ");
892 ps (e
->X_add_symbol
);
893 fprintf (stdout
, "\n");
897 fprintf (stdout
, " op_symbol ");
899 fprintf (stdout
, "\n");
907 fprintf (stdout
, "%s type %s%s",
909 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
910 segment_name (S_GET_SEGMENT (s
)));
929 { BaseIndex
, "BaseIndex" },
933 { InOutPortReg
, "InOutPortReg" },
934 { ShiftCount
, "ShiftCount" },
935 { Control
, "control reg" },
936 { Test
, "test reg" },
937 { Debug
, "debug reg" },
938 { FloatReg
, "FReg" },
939 { FloatAcc
, "FAcc" },
943 { JumpAbsolute
, "Jump Absolute" },
954 register struct type_name
*ty
;
958 fprintf (stdout
, _("Unknown"));
962 for (ty
= type_names
; ty
->mask
; ty
++)
964 fprintf (stdout
, "%s, ", ty
->tname
);
969 #endif /* DEBUG386 */
972 tc_i386_force_relocation (fixp
)
976 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
977 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
982 return fixp
->fx_r_type
== 7;
987 static bfd_reloc_code_real_type reloc
988 PARAMS ((int, int, bfd_reloc_code_real_type
));
990 static bfd_reloc_code_real_type
991 reloc (size
, pcrel
, other
)
994 bfd_reloc_code_real_type other
;
996 if (other
!= NO_RELOC
)
1003 case 1: return BFD_RELOC_8_PCREL
;
1004 case 2: return BFD_RELOC_16_PCREL
;
1005 case 4: return BFD_RELOC_32_PCREL
;
1007 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1013 case 1: return BFD_RELOC_8
;
1014 case 2: return BFD_RELOC_16
;
1015 case 4: return BFD_RELOC_32
;
1017 as_bad (_("can not do %d byte relocation"), size
);
1020 return BFD_RELOC_NONE
;
1023 /* Here we decide which fixups can be adjusted to make them relative to
1024 the beginning of the section instead of the symbol. Basically we need
1025 to make sure that the dynamic relocations are done correctly, so in
1026 some cases we force the original symbol to be used. */
1029 tc_i386_fix_adjustable (fixP
)
1032 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1033 /* Prevent all adjustments to global symbols, or else dynamic
1034 linking will not work correctly. */
1035 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1036 || S_IS_WEAK (fixP
->fx_addsy
))
1039 /* adjust_reloc_syms doesn't know about the GOT */
1040 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1041 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1042 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1043 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1044 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1049 #define reloc(SIZE,PCREL,OTHER) 0
1050 #define BFD_RELOC_16 0
1051 #define BFD_RELOC_32 0
1052 #define BFD_RELOC_16_PCREL 0
1053 #define BFD_RELOC_32_PCREL 0
1054 #define BFD_RELOC_386_PLT32 0
1055 #define BFD_RELOC_386_GOT32 0
1056 #define BFD_RELOC_386_GOTOFF 0
1059 static int intel_float_operand
PARAMS ((char *mnemonic
));
1062 intel_float_operand (mnemonic
)
1065 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1068 if (mnemonic
[0] == 'f')
1074 /* This is the guts of the machine-dependent assembler. LINE points to a
1075 machine dependent instruction. This function is supposed to emit
1076 the frags/bytes it assembles to. */
1082 /* Points to template once we've found it. */
1085 /* Count the size of the instruction generated. */
1090 char mnemonic
[MAX_MNEM_SIZE
];
1092 /* Initialize globals. */
1093 memset (&i
, '\0', sizeof (i
));
1094 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1095 i
.disp_reloc
[j
] = NO_RELOC
;
1096 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1097 memset (im_expressions
, '\0', sizeof (im_expressions
));
1098 save_stack_p
= save_stack
; /* reset stack pointer */
1100 /* First parse an instruction mnemonic & call i386_operand for the operands.
1101 We assume that the scrubber has arranged it so that line[0] is the valid
1102 start of a (possibly prefixed) mnemonic. */
1105 char *token_start
= l
;
1108 /* Non-zero if we found a prefix only acceptable with string insns. */
1109 const char *expecting_string_instruction
= NULL
;
1114 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1117 if (mnem_p
>= mnemonic
+ sizeof (mnemonic
))
1119 as_bad (_("no such instruction: `%s'"), token_start
);
1124 if (!is_space_char (*l
)
1125 && *l
!= END_OF_INSN
1126 && *l
!= PREFIX_SEPARATOR
)
1128 as_bad (_("invalid character %s in mnemonic"),
1129 output_invalid (*l
));
1132 if (token_start
== l
)
1134 if (*l
== PREFIX_SEPARATOR
)
1135 as_bad (_("expecting prefix; got nothing"));
1137 as_bad (_("expecting mnemonic; got nothing"));
1141 /* Look up instruction (or prefix) via hash table. */
1142 current_templates
= hash_find (op_hash
, mnemonic
);
1144 if (*l
!= END_OF_INSN
1145 && (! is_space_char (*l
) || l
[1] != END_OF_INSN
)
1146 && current_templates
1147 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1149 /* If we are in 16-bit mode, do not allow addr16 or data16.
1150 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1151 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1152 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1155 as_bad (_("redundant %s prefix"),
1156 current_templates
->start
->name
);
1159 /* Add prefix, checking for repeated prefixes. */
1160 switch (add_prefix (current_templates
->start
->base_opcode
))
1165 expecting_string_instruction
= current_templates
->start
->name
;
1168 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1175 if (!current_templates
)
1177 /* See if we can get a match by trimming off a suffix. */
1180 case WORD_MNEM_SUFFIX
:
1181 case BYTE_MNEM_SUFFIX
:
1182 case SHORT_MNEM_SUFFIX
:
1183 case LONG_MNEM_SUFFIX
:
1184 i
.suffix
= mnem_p
[-1];
1186 current_templates
= hash_find (op_hash
, mnemonic
);
1190 case DWORD_MNEM_SUFFIX
:
1193 i
.suffix
= mnem_p
[-1];
1195 current_templates
= hash_find (op_hash
, mnemonic
);
1199 if (!current_templates
)
1201 as_bad (_("no such instruction: `%s'"), token_start
);
1206 /* Check if instruction is supported on specified architecture. */
1207 if (cpu_arch_flags
!= 0)
1209 if (current_templates
->start
->cpu_flags
& ~cpu_arch_flags
)
1211 as_warn (_("`%s' is not supported on `%s'"),
1212 current_templates
->start
->name
, cpu_arch_name
);
1214 else if ((Cpu386
& ~cpu_arch_flags
) && !flag_16bit_code
)
1216 as_warn (_("use .code16 to ensure correct addressing mode"));
1220 /* check for rep/repne without a string instruction */
1221 if (expecting_string_instruction
1222 && !(current_templates
->start
->opcode_modifier
& IsString
))
1224 as_bad (_("expecting string instruction after `%s'"),
1225 expecting_string_instruction
);
1229 /* There may be operands to parse. */
1230 if (*l
!= END_OF_INSN
)
1232 /* parse operands */
1234 /* 1 if operand is pending after ','. */
1235 unsigned int expecting_operand
= 0;
1237 /* Non-zero if operand parens not balanced. */
1238 unsigned int paren_not_balanced
;
1242 /* skip optional white space before operand */
1243 if (is_space_char (*l
))
1245 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1247 as_bad (_("invalid character %s before operand %d"),
1248 output_invalid (*l
),
1252 token_start
= l
; /* after white space */
1253 paren_not_balanced
= 0;
1254 while (paren_not_balanced
|| *l
!= ',')
1256 if (*l
== END_OF_INSN
)
1258 if (paren_not_balanced
)
1261 as_bad (_("unbalanced parenthesis in operand %d."),
1264 as_bad (_("unbalanced brackets in operand %d."),
1269 break; /* we are done */
1271 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1273 as_bad (_("invalid character %s in operand %d"),
1274 output_invalid (*l
),
1281 ++paren_not_balanced
;
1283 --paren_not_balanced
;
1288 ++paren_not_balanced
;
1290 --paren_not_balanced
;
1294 if (l
!= token_start
)
1295 { /* Yes, we've read in another operand. */
1296 unsigned int operand_ok
;
1297 this_operand
= i
.operands
++;
1298 if (i
.operands
> MAX_OPERANDS
)
1300 as_bad (_("spurious operands; (%d operands/instruction max)"),
1304 /* Now parse operand adding info to 'i' as we go along. */
1305 END_STRING_AND_SAVE (l
);
1309 i386_intel_operand (token_start
,
1310 intel_float_operand (mnemonic
));
1312 operand_ok
= i386_operand (token_start
);
1314 RESTORE_END_STRING (l
); /* restore old contents */
1320 if (expecting_operand
)
1322 expecting_operand_after_comma
:
1323 as_bad (_("expecting operand after ','; got nothing"));
1328 as_bad (_("expecting operand before ','; got nothing"));
1333 /* now *l must be either ',' or END_OF_INSN */
1336 if (*++l
== END_OF_INSN
)
1337 { /* just skip it, if it's \n complain */
1338 goto expecting_operand_after_comma
;
1340 expecting_operand
= 1;
1343 while (*l
!= END_OF_INSN
); /* until we get end of insn */
1347 /* Now we've parsed the mnemonic into a set of templates, and have the
1350 Next, we find a template that matches the given insn,
1351 making sure the overlap of the given operands types is consistent
1352 with the template operand types. */
1354 #define MATCH(overlap, given, template) \
1355 ((overlap & ~JumpAbsolute) \
1356 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1358 /* If given types r0 and r1 are registers they must be of the same type
1359 unless the expected operand type register overlap is null.
1360 Note that Acc in a template matches every size of reg. */
1361 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1362 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1363 ((g0) & Reg) == ((g1) & Reg) || \
1364 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1367 register unsigned int overlap0
, overlap1
;
1368 unsigned int overlap2
;
1369 unsigned int found_reverse_match
;
1372 /* All intel opcodes have reversed operands except for "bound" and
1373 "enter". We also don't reverse intersegment "jmp" and "call"
1374 instructions with 2 immediate operands so that the immediate segment
1375 precedes the offset, as it does when in AT&T mode. "enter" and the
1376 intersegment "jmp" and "call" instructions are the only ones that
1377 have two immediate operands. */
1378 if (intel_syntax
&& i
.operands
> 1
1379 && (strcmp (mnemonic
, "bound") != 0)
1380 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1382 union i386_op temp_op
;
1383 unsigned int temp_type
;
1387 if (i
.operands
== 2)
1392 else if (i
.operands
== 3)
1397 temp_type
= i
.types
[xchg2
];
1398 i
.types
[xchg2
] = i
.types
[xchg1
];
1399 i
.types
[xchg1
] = temp_type
;
1400 temp_op
= i
.op
[xchg2
];
1401 i
.op
[xchg2
] = i
.op
[xchg1
];
1402 i
.op
[xchg1
] = temp_op
;
1404 if (i
.mem_operands
== 2)
1406 const seg_entry
*temp_seg
;
1407 temp_seg
= i
.seg
[0];
1408 i
.seg
[0] = i
.seg
[1];
1409 i
.seg
[1] = temp_seg
;
1415 /* Try to ensure constant immediates are represented in the smallest
1417 char guess_suffix
= 0;
1421 guess_suffix
= i
.suffix
;
1422 else if (i
.reg_operands
)
1424 /* Figure out a suffix from the last register operand specified.
1425 We can't do this properly yet, ie. excluding InOutPortReg,
1426 but the following works for instructions with immediates.
1427 In any case, we can't set i.suffix yet. */
1428 for (op
= i
.operands
; --op
>= 0;)
1429 if (i
.types
[op
] & Reg
)
1431 if (i
.types
[op
] & Reg8
)
1432 guess_suffix
= BYTE_MNEM_SUFFIX
;
1433 else if (i
.types
[op
] & Reg16
)
1434 guess_suffix
= WORD_MNEM_SUFFIX
;
1438 else if (flag_16bit_code
^ (i
.prefix
[DATA_PREFIX
] != 0))
1439 guess_suffix
= WORD_MNEM_SUFFIX
;
1441 for (op
= i
.operands
; --op
>= 0;)
1442 if ((i
.types
[op
] & Imm
)
1443 && i
.op
[op
].imms
->X_op
== O_constant
)
1445 /* If a suffix is given, this operand may be shortened. */
1446 switch (guess_suffix
)
1448 case WORD_MNEM_SUFFIX
:
1449 i
.types
[op
] |= Imm16
;
1451 case BYTE_MNEM_SUFFIX
:
1452 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
;
1456 /* If this operand is at most 16 bits, convert it to a
1457 signed 16 bit number before trying to see whether it will
1458 fit in an even smaller size. This allows a 16-bit operand
1459 such as $0xffe0 to be recognised as within Imm8S range. */
1460 if ((i
.types
[op
] & Imm16
)
1461 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
)0xffff) == 0)
1463 i
.op
[op
].imms
->X_add_number
=
1464 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1466 i
.types
[op
] |= smallest_imm_type ((long) i
.op
[op
].imms
->X_add_number
);
1470 if (i
.disp_operands
)
1472 /* Try to use the smallest displacement type too. */
1475 for (op
= i
.operands
; --op
>= 0;)
1476 if ((i
.types
[op
] & Disp
)
1477 && i
.op
[op
].imms
->X_op
== O_constant
)
1479 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1481 if (i
.types
[op
] & Disp16
)
1483 /* We know this operand is at most 16 bits, so
1484 convert to a signed 16 bit number before trying
1485 to see whether it will fit in an even smaller
1488 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1490 if (fits_in_signed_byte (disp
))
1491 i
.types
[op
] |= Disp8
;
1498 found_reverse_match
= 0;
1499 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1501 : (i
.suffix
== WORD_MNEM_SUFFIX
1503 : (i
.suffix
== SHORT_MNEM_SUFFIX
1505 : (i
.suffix
== LONG_MNEM_SUFFIX
1507 : (i
.suffix
== DWORD_MNEM_SUFFIX
1509 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
? No_xSuf
: 0))))));
1511 for (t
= current_templates
->start
;
1512 t
< current_templates
->end
;
1515 /* Must have right number of operands. */
1516 if (i
.operands
!= t
->operands
)
1519 /* Check the suffix, except for some instructions in intel mode. */
1520 if ((t
->opcode_modifier
& suffix_check
)
1522 && t
->base_opcode
== 0xd9
1523 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1524 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1527 else if (!t
->operands
)
1528 /* 0 operands always matches. */
1531 overlap0
= i
.types
[0] & t
->operand_types
[0];
1532 switch (t
->operands
)
1535 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1540 overlap1
= i
.types
[1] & t
->operand_types
[1];
1541 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1542 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1543 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1544 t
->operand_types
[0],
1545 overlap1
, i
.types
[1],
1546 t
->operand_types
[1]))
1548 /* Check if other direction is valid ... */
1549 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1552 /* Try reversing direction of operands. */
1553 overlap0
= i
.types
[0] & t
->operand_types
[1];
1554 overlap1
= i
.types
[1] & t
->operand_types
[0];
1555 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1556 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1557 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1558 t
->operand_types
[1],
1559 overlap1
, i
.types
[1],
1560 t
->operand_types
[0]))
1562 /* Does not match either direction. */
1565 /* found_reverse_match holds which of D or FloatDR
1567 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1570 /* Found a forward 2 operand match here. */
1571 if (t
->operands
== 3)
1573 /* Here we make use of the fact that there are no
1574 reverse match 3 operand instructions, and all 3
1575 operand instructions only need to be checked for
1576 register consistency between operands 2 and 3. */
1577 overlap2
= i
.types
[2] & t
->operand_types
[2];
1578 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1579 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1580 t
->operand_types
[1],
1581 overlap2
, i
.types
[2],
1582 t
->operand_types
[2]))
1586 /* Found either forward/reverse 2 or 3 operand match here:
1587 slip through to break */
1589 /* We've found a match; break out of loop. */
1591 } /* for (t = ... */
1592 if (t
== current_templates
->end
)
1594 /* We found no match. */
1595 as_bad (_("suffix or operands invalid for `%s'"),
1596 current_templates
->start
->name
);
1600 if (!quiet_warnings
)
1603 && ((i
.types
[0] & JumpAbsolute
)
1604 != (t
->operand_types
[0] & JumpAbsolute
)))
1606 as_warn (_("indirect %s without `*'"), t
->name
);
1609 if ((t
->opcode_modifier
& (IsPrefix
|IgnoreSize
))
1610 == (IsPrefix
|IgnoreSize
))
1612 /* Warn them that a data or address size prefix doesn't
1613 affect assembly of the next line of code. */
1614 as_warn (_("stand-alone `%s' prefix"), t
->name
);
1618 /* Copy the template we found. */
1620 if (found_reverse_match
)
1622 /* If we found a reverse match we must alter the opcode
1623 direction bit. found_reverse_match holds bits to change
1624 (different for int & float insns). */
1626 i
.tm
.base_opcode
^= found_reverse_match
;
1628 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1629 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1632 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1635 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1636 i
.tm
.base_opcode
^= FloatR
;
1638 if (i
.tm
.opcode_modifier
& FWait
)
1639 if (! add_prefix (FWAIT_OPCODE
))
1642 /* Check string instruction segment overrides */
1643 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1645 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1646 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1648 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1650 as_bad (_("`%s' operand %d must use `%%es' segment"),
1655 /* There's only ever one segment override allowed per instruction.
1656 This instruction possibly has a legal segment override on the
1657 second operand, so copy the segment to where non-string
1658 instructions store it, allowing common code. */
1659 i
.seg
[0] = i
.seg
[1];
1661 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1663 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1665 as_bad (_("`%s' operand %d must use `%%es' segment"),
1673 /* If matched instruction specifies an explicit instruction mnemonic
1675 if (i
.tm
.opcode_modifier
& (Size16
| Size32
))
1677 if (i
.tm
.opcode_modifier
& Size16
)
1678 i
.suffix
= WORD_MNEM_SUFFIX
;
1680 i
.suffix
= LONG_MNEM_SUFFIX
;
1682 else if (i
.reg_operands
)
1684 /* If there's no instruction mnemonic suffix we try to invent one
1685 based on register operands. */
1688 /* We take i.suffix from the last register operand specified,
1689 Destination register type is more significant than source
1692 for (op
= i
.operands
; --op
>= 0;)
1693 if ((i
.types
[op
] & Reg
)
1694 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
1696 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
1697 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
1702 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
1705 for (op
= i
.operands
; --op
>= 0;)
1707 /* If this is an eight bit register, it's OK. If it's
1708 the 16 or 32 bit version of an eight bit register,
1709 we will just use the low portion, and that's OK too. */
1710 if (i
.types
[op
] & Reg8
)
1713 /* movzx and movsx should not generate this warning. */
1715 && (i
.tm
.base_opcode
== 0xfb7
1716 || i
.tm
.base_opcode
== 0xfb6
1717 || i
.tm
.base_opcode
== 0xfbe
1718 || i
.tm
.base_opcode
== 0xfbf))
1721 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
1723 /* Check that the template allows eight bit regs
1724 This kills insns such as `orb $1,%edx', which
1725 maybe should be allowed. */
1726 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
1730 #if REGISTER_WARNINGS
1732 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1733 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1734 (i
.op
[op
].regs
- (i
.types
[op
] & Reg16
? 8 : 16))->reg_name
,
1735 i
.op
[op
].regs
->reg_name
,
1740 /* Any other register is bad */
1741 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
1743 | Control
| Debug
| Test
1744 | FloatReg
| FloatAcc
))
1746 as_bad (_("`%%%s' not allowed with `%s%c'"),
1747 i
.op
[op
].regs
->reg_name
,
1754 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
1758 for (op
= i
.operands
; --op
>= 0;)
1759 /* Reject eight bit registers, except where the template
1760 requires them. (eg. movzb) */
1761 if ((i
.types
[op
] & Reg8
) != 0
1762 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
1764 as_bad (_("`%%%s' not allowed with `%s%c'"),
1765 i
.op
[op
].regs
->reg_name
,
1770 #if REGISTER_WARNINGS
1771 /* Warn if the e prefix on a general reg is missing. */
1772 else if (!quiet_warnings
1773 && (i
.types
[op
] & Reg16
) != 0
1774 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
1776 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1777 (i
.op
[op
].regs
+ 8)->reg_name
,
1778 i
.op
[op
].regs
->reg_name
,
1783 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
1786 for (op
= i
.operands
; --op
>= 0;)
1787 /* Reject eight bit registers, except where the template
1788 requires them. (eg. movzb) */
1789 if ((i
.types
[op
] & Reg8
) != 0
1790 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
1792 as_bad (_("`%%%s' not allowed with `%s%c'"),
1793 i
.op
[op
].regs
->reg_name
,
1798 #if REGISTER_WARNINGS
1799 /* Warn if the e prefix on a general reg is present. */
1800 else if (!quiet_warnings
1801 && (i
.types
[op
] & Reg32
) != 0
1802 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
1804 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1805 (i
.op
[op
].regs
- 8)->reg_name
,
1806 i
.op
[op
].regs
->reg_name
,
1814 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
1816 i
.suffix
= stackop_size
;
1819 /* Make still unresolved immediate matches conform to size of immediate
1820 given in i.suffix. Note: overlap2 cannot be an immediate! */
1821 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
))
1822 && overlap0
!= Imm8
&& overlap0
!= Imm8S
1823 && overlap0
!= Imm16
&& overlap0
!= Imm32
)
1827 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
1828 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
: Imm32
));
1830 else if (overlap0
== (Imm16
| Imm32
))
1833 (flag_16bit_code
^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32
;
1837 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
1841 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32
))
1842 && overlap1
!= Imm8
&& overlap1
!= Imm8S
1843 && overlap1
!= Imm16
&& overlap1
!= Imm32
)
1847 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
1848 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
: Imm32
));
1850 else if (overlap1
== (Imm16
| Imm32
))
1853 (flag_16bit_code
^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32
;
1857 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
1861 assert ((overlap2
& Imm
) == 0);
1863 i
.types
[0] = overlap0
;
1864 if (overlap0
& ImplicitRegister
)
1866 if (overlap0
& Imm1
)
1867 i
.imm_operands
= 0; /* kludge for shift insns */
1869 i
.types
[1] = overlap1
;
1870 if (overlap1
& ImplicitRegister
)
1873 i
.types
[2] = overlap2
;
1874 if (overlap2
& ImplicitRegister
)
1877 /* Finalize opcode. First, we change the opcode based on the operand
1878 size given by i.suffix: We need not change things for byte insns. */
1880 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
1882 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
1886 /* For movzx and movsx, need to check the register type */
1888 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
1889 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
1891 unsigned int prefix
= DATA_PREFIX_OPCODE
;
1893 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
1894 if (!add_prefix (prefix
))
1898 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
1900 /* It's not a byte, select word/dword operation. */
1901 if (i
.tm
.opcode_modifier
& W
)
1903 if (i
.tm
.opcode_modifier
& ShortForm
)
1904 i
.tm
.base_opcode
|= 8;
1906 i
.tm
.base_opcode
|= 1;
1908 /* Now select between word & dword operations via the operand
1909 size prefix, except for instructions that will ignore this
1911 if (((intel_syntax
&& (i
.suffix
== DWORD_MNEM_SUFFIX
))
1912 || i
.suffix
== LONG_MNEM_SUFFIX
) == flag_16bit_code
1913 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
1915 unsigned int prefix
= DATA_PREFIX_OPCODE
;
1916 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
1917 prefix
= ADDR_PREFIX_OPCODE
;
1919 if (! add_prefix (prefix
))
1922 /* Size floating point instruction. */
1923 if (i
.suffix
== LONG_MNEM_SUFFIX
1924 || (intel_syntax
&& i
.suffix
== DWORD_MNEM_SUFFIX
))
1926 if (i
.tm
.opcode_modifier
& FloatMF
)
1927 i
.tm
.base_opcode
^= 4;
1931 if (i
.tm
.opcode_modifier
& ImmExt
)
1933 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1934 opcode suffix which is coded in the same place as an 8-bit
1935 immediate field would be. Here we fake an 8-bit immediate
1936 operand from the opcode suffix stored in tm.extension_opcode. */
1940 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1942 exp
= &im_expressions
[i
.imm_operands
++];
1943 i
.op
[i
.operands
].imms
= exp
;
1944 i
.types
[i
.operands
++] = Imm8
;
1945 exp
->X_op
= O_constant
;
1946 exp
->X_add_number
= i
.tm
.extension_opcode
;
1947 i
.tm
.extension_opcode
= None
;
1950 /* For insns with operands there are more diddles to do to the opcode. */
1953 /* Default segment register this instruction will use
1954 for memory accesses. 0 means unknown.
1955 This is only for optimizing out unnecessary segment overrides. */
1956 const seg_entry
*default_seg
= 0;
1958 /* The imul $imm, %reg instruction is converted into
1959 imul $imm, %reg, %reg, and the clr %reg instruction
1960 is converted into xor %reg, %reg. */
1961 if (i
.tm
.opcode_modifier
& regKludge
)
1963 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
1964 /* Pretend we saw the extra register operand. */
1965 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
1966 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
1967 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
1971 if (i
.tm
.opcode_modifier
& ShortForm
)
1973 /* The register or float register operand is in operand 0 or 1. */
1974 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
1975 /* Register goes in low 3 bits of opcode. */
1976 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
1977 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1979 /* Warn about some common errors, but press on regardless.
1980 The first case can be generated by gcc (<= 2.8.1). */
1981 if (i
.operands
== 2)
1983 /* Reversed arguments on faddp, fsubp, etc. */
1984 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
1985 i
.op
[1].regs
->reg_name
,
1986 i
.op
[0].regs
->reg_name
);
1990 /* Extraneous `l' suffix on fp insn. */
1991 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
1992 i
.op
[0].regs
->reg_name
);
1996 else if (i
.tm
.opcode_modifier
& Modrm
)
1998 /* The opcode is completed (modulo i.tm.extension_opcode which
1999 must be put into the modrm byte).
2000 Now, we make the modrm & index base bytes based on all the
2001 info we've collected. */
2003 /* i.reg_operands MUST be the number of real register operands;
2004 implicit registers do not count. */
2005 if (i
.reg_operands
== 2)
2007 unsigned int source
, dest
;
2008 source
= ((i
.types
[0]
2009 & (Reg
| RegMMX
| RegXMM
2011 | Control
| Debug
| Test
))
2016 /* One of the register operands will be encoded in the
2017 i.tm.reg field, the other in the combined i.tm.mode
2018 and i.tm.regmem fields. If no form of this
2019 instruction supports a memory destination operand,
2020 then we assume the source operand may sometimes be
2021 a memory operand and so we need to store the
2022 destination in the i.rm.reg field. */
2023 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2025 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2026 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2030 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2031 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2035 { /* If it's not 2 reg operands... */
2038 unsigned int fake_zero_displacement
= 0;
2039 unsigned int op
= ((i
.types
[0] & AnyMem
)
2041 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2048 if (! i
.disp_operands
)
2049 fake_zero_displacement
= 1;
2052 /* Operand is just <disp> */
2053 if (flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0))
2055 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2056 i
.types
[op
] &= ~Disp
;
2057 i
.types
[op
] |= Disp16
;
2061 i
.rm
.regmem
= NO_BASE_REGISTER
;
2062 i
.types
[op
] &= ~Disp
;
2063 i
.types
[op
] |= Disp32
;
2066 else /* ! i.base_reg && i.index_reg */
2068 i
.sib
.index
= i
.index_reg
->reg_num
;
2069 i
.sib
.base
= NO_BASE_REGISTER
;
2070 i
.sib
.scale
= i
.log2_scale_factor
;
2071 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2072 i
.types
[op
] &= ~Disp
;
2073 i
.types
[op
] |= Disp32
; /* Must be 32 bit. */
2076 else if (i
.base_reg
->reg_type
& Reg16
)
2078 switch (i
.base_reg
->reg_num
)
2083 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2084 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2091 if ((i
.types
[op
] & Disp
) == 0)
2093 /* fake (%bp) into 0(%bp) */
2094 i
.types
[op
] |= Disp8
;
2095 fake_zero_displacement
= 1;
2098 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2099 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2101 default: /* (%si) -> 4 or (%di) -> 5 */
2102 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2104 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2106 else /* i.base_reg and 32 bit mode */
2108 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2109 i
.sib
.base
= i
.base_reg
->reg_num
;
2110 if (i
.base_reg
->reg_num
== EBP_REG_NUM
)
2113 if (i
.disp_operands
== 0)
2115 fake_zero_displacement
= 1;
2116 i
.types
[op
] |= Disp8
;
2119 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2123 i
.sib
.scale
= i
.log2_scale_factor
;
2126 /* <disp>(%esp) becomes two byte modrm
2127 with no index register. We've already
2128 stored the code for esp in i.rm.regmem
2129 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2130 base register besides %esp will not use
2131 the extra modrm byte. */
2132 i
.sib
.index
= NO_INDEX_REGISTER
;
2133 #if ! SCALE1_WHEN_NO_INDEX
2134 /* Another case where we force the second
2136 if (i
.log2_scale_factor
)
2137 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2142 i
.sib
.index
= i
.index_reg
->reg_num
;
2143 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2145 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2148 if (fake_zero_displacement
)
2150 /* Fakes a zero displacement assuming that i.types[op]
2151 holds the correct displacement size. */
2154 assert (i
.op
[op
].disps
== 0);
2155 exp
= &disp_expressions
[i
.disp_operands
++];
2156 i
.op
[op
].disps
= exp
;
2157 exp
->X_op
= O_constant
;
2158 exp
->X_add_number
= 0;
2159 exp
->X_add_symbol
= (symbolS
*) 0;
2160 exp
->X_op_symbol
= (symbolS
*) 0;
2164 /* Fill in i.rm.reg or i.rm.regmem field with register
2165 operand (if any) based on i.tm.extension_opcode.
2166 Again, we must be careful to make sure that
2167 segment/control/debug/test/MMX registers are coded
2168 into the i.rm.reg field. */
2173 & (Reg
| RegMMX
| RegXMM
2175 | Control
| Debug
| Test
))
2178 & (Reg
| RegMMX
| RegXMM
2180 | Control
| Debug
| Test
))
2183 /* If there is an extension opcode to put here, the
2184 register number must be put into the regmem field. */
2185 if (i
.tm
.extension_opcode
!= None
)
2186 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2188 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2190 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2191 we must set it to 3 to indicate this is a register
2192 operand in the regmem field. */
2193 if (!i
.mem_operands
)
2197 /* Fill in i.rm.reg field with extension opcode (if any). */
2198 if (i
.tm
.extension_opcode
!= None
)
2199 i
.rm
.reg
= i
.tm
.extension_opcode
;
2202 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2204 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2205 && i
.op
[0].regs
->reg_num
== 1)
2207 as_bad (_("you can't `pop %%cs'"));
2210 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2212 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
2216 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2218 /* For the string instructions that allow a segment override
2219 on one of their operands, the default segment is ds. */
2223 /* If a segment was explicitly specified,
2224 and the specified segment is not the default,
2225 use an opcode prefix to select it.
2226 If we never figured out what the default segment is,
2227 then default_seg will be zero at this point,
2228 and the specified segment prefix will always be used. */
2229 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2231 if (! add_prefix (i
.seg
[0]->seg_prefix
))
2235 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2237 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2238 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2242 /* Handle conversion of 'int $3' --> special int3 insn. */
2243 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2245 i
.tm
.base_opcode
= INT3_OPCODE
;
2249 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
2250 && i
.op
[0].disps
->X_op
== O_constant
)
2252 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2253 the absolute address given by the constant. Since ix86 jumps and
2254 calls are pc relative, we need to generate a reloc. */
2255 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2256 i
.op
[0].disps
->X_op
= O_symbol
;
2259 /* We are ready to output the insn. */
2264 if (i
.tm
.opcode_modifier
& Jump
)
2271 if (flag_16bit_code
)
2275 if (i
.prefix
[DATA_PREFIX
])
2286 if (i
.prefixes
!= 0 && !intel_syntax
)
2287 as_warn (_("skipping prefixes on this instruction"));
2289 /* It's always a symbol; End frag & setup for relax.
2290 Make sure there is enough room in this frag for the largest
2291 instruction we may generate in md_convert_frag. This is 2
2292 bytes for the opcode and room for the prefix and largest
2294 frag_grow (prefix
+ 2 + size
);
2295 insn_size
+= prefix
+ 1;
2296 /* Prefix and 1 opcode byte go in fr_fix. */
2297 p
= frag_more (prefix
+ 1);
2299 *p
++ = DATA_PREFIX_OPCODE
;
2300 *p
= i
.tm
.base_opcode
;
2301 /* 1 possible extra opcode + displacement go in var part.
2302 Pass reloc in fr_var. */
2303 frag_var (rs_machine_dependent
,
2306 ((unsigned char) *p
== JUMP_PC_RELATIVE
2307 ? ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
) | code16
2308 : ENCODE_RELAX_STATE (COND_JUMP
, SMALL
) | code16
),
2309 i
.op
[0].disps
->X_add_symbol
,
2310 i
.op
[0].disps
->X_add_number
,
2313 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
2317 if (i
.tm
.opcode_modifier
& JumpByte
)
2319 /* This is a loop or jecxz type instruction. */
2321 if (i
.prefix
[ADDR_PREFIX
])
2324 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2333 if (flag_16bit_code
)
2336 if (i
.prefix
[DATA_PREFIX
])
2339 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
2349 if (i
.prefixes
!= 0 && !intel_syntax
)
2350 as_warn (_("skipping prefixes on this instruction"));
2352 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2354 insn_size
+= 1 + size
;
2355 p
= frag_more (1 + size
);
2359 /* Opcode can be at most two bytes. */
2360 insn_size
+= 2 + size
;
2361 p
= frag_more (2 + size
);
2362 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2364 *p
++ = i
.tm
.base_opcode
& 0xff;
2366 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2367 i
.op
[0].disps
, 1, reloc (size
, 1, i
.disp_reloc
[0]));
2369 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
2376 if (flag_16bit_code
)
2380 if (i
.prefix
[DATA_PREFIX
])
2391 if (i
.prefixes
!= 0 && !intel_syntax
)
2392 as_warn (_("skipping prefixes on this instruction"));
2394 /* 1 opcode; 2 segment; offset */
2395 insn_size
+= prefix
+ 1 + 2 + size
;
2396 p
= frag_more (prefix
+ 1 + 2 + size
);
2398 *p
++ = DATA_PREFIX_OPCODE
;
2399 *p
++ = i
.tm
.base_opcode
;
2400 if (i
.op
[1].imms
->X_op
== O_constant
)
2402 offsetT n
= i
.op
[1].imms
->X_add_number
;
2405 && !fits_in_unsigned_word (n
)
2406 && !fits_in_signed_word (n
))
2408 as_bad (_("16-bit jump out of range"));
2411 md_number_to_chars (p
, n
, size
);
2414 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2415 i
.op
[1].imms
, 0, reloc (size
, 0, i
.disp_reloc
[0]));
2416 if (i
.op
[0].imms
->X_op
!= O_constant
)
2417 as_bad (_("can't handle non absolute segment in `%s'"),
2419 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
2423 /* Output normal instructions here. */
2426 /* The prefix bytes. */
2428 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2435 md_number_to_chars (p
, (valueT
) *q
, 1);
2439 /* Now the opcode; be careful about word order here! */
2440 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2443 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2445 else if (fits_in_unsigned_word (i
.tm
.base_opcode
))
2449 /* Put out high byte first: can't use md_number_to_chars! */
2450 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2451 *p
= i
.tm
.base_opcode
& 0xff;
2454 { /* Opcode is either 3 or 4 bytes. */
2455 if (i
.tm
.base_opcode
& 0xff000000)
2459 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
2466 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
2467 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2468 *p
= (i
.tm
.base_opcode
) & 0xff;
2471 /* Now the modrm byte and sib byte (if present). */
2472 if (i
.tm
.opcode_modifier
& Modrm
)
2476 md_number_to_chars (p
,
2477 (valueT
) (i
.rm
.regmem
<< 0
2481 /* If i.rm.regmem == ESP (4)
2482 && i.rm.mode != (Register mode)
2484 ==> need second modrm byte. */
2485 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2487 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2491 md_number_to_chars (p
,
2492 (valueT
) (i
.sib
.base
<< 0
2494 | i
.sib
.scale
<< 6),
2499 if (i
.disp_operands
)
2501 register unsigned int n
;
2503 for (n
= 0; n
< i
.operands
; n
++)
2505 if (i
.types
[n
] & Disp
)
2507 if (i
.op
[n
].disps
->X_op
== O_constant
)
2513 if (i
.types
[n
] & (Disp8
| Disp16
))
2516 if (i
.types
[n
] & Disp8
)
2519 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
2522 p
= frag_more (size
);
2523 md_number_to_chars (p
, val
, size
);
2529 if (i
.types
[n
] & Disp16
)
2533 p
= frag_more (size
);
2534 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2536 reloc (size
, 0, i
.disp_reloc
[n
]));
2540 } /* End displacement output. */
2542 /* Output immediate. */
2545 register unsigned int n
;
2547 for (n
= 0; n
< i
.operands
; n
++)
2549 if (i
.types
[n
] & Imm
)
2551 if (i
.op
[n
].imms
->X_op
== O_constant
)
2557 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
))
2560 if (i
.types
[n
] & (Imm8
| Imm8S
))
2563 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
2566 p
= frag_more (size
);
2567 md_number_to_chars (p
, val
, size
);
2570 { /* Not absolute_section. */
2571 /* Need a 32-bit fixup (don't support 8bit
2572 non-absolute imms). Try to support other
2574 #ifdef BFD_ASSEMBLER
2575 enum bfd_reloc_code_real reloc_type
;
2581 if (i
.types
[n
] & Imm16
)
2583 else if (i
.types
[n
] & (Imm8
| Imm8S
))
2587 p
= frag_more (size
);
2588 reloc_type
= reloc (size
, 0, i
.disp_reloc
[0]);
2589 #ifdef BFD_ASSEMBLER
2590 if (reloc_type
== BFD_RELOC_32
2592 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
2593 && (i
.op
[n
].imms
->X_op
== O_symbol
2594 || (i
.op
[n
].imms
->X_op
== O_add
2595 && ((symbol_get_value_expression
2596 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
2599 reloc_type
= BFD_RELOC_386_GOTPC
;
2600 i
.op
[n
].imms
->X_add_number
+= 3;
2603 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2604 i
.op
[n
].imms
, 0, reloc_type
);
2608 } /* end immediate output */
2616 #endif /* DEBUG386 */
2620 static int i386_immediate
PARAMS ((char *));
2623 i386_immediate (imm_start
)
2626 char *save_input_line_pointer
;
2630 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
2632 as_bad (_("only 1 or 2 immediate operands are allowed"));
2636 exp
= &im_expressions
[i
.imm_operands
++];
2637 i
.op
[this_operand
].imms
= exp
;
2639 if (is_space_char (*imm_start
))
2642 save_input_line_pointer
= input_line_pointer
;
2643 input_line_pointer
= imm_start
;
2647 /* We can have operands of the form
2648 <symbol>@GOTOFF+<nnn>
2649 Take the easy way out here and copy everything
2650 into a temporary buffer... */
2653 cp
= strchr (input_line_pointer
, '@');
2660 /* GOT relocations are not supported in 16 bit mode. */
2661 if (flag_16bit_code
)
2662 as_bad (_("GOT relocations not supported in 16 bit mode"));
2664 if (GOT_symbol
== NULL
)
2665 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
2667 if (strncmp (cp
+ 1, "PLT", 3) == 0)
2669 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
2672 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
2674 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
2677 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
2679 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
2683 as_bad (_("bad reloc specifier in expression"));
2685 /* Replace the relocation token with ' ', so that errors like
2686 foo@GOTOFF1 will be detected. */
2687 first
= cp
- input_line_pointer
;
2688 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
2689 memcpy (tmpbuf
, input_line_pointer
, first
);
2690 tmpbuf
[first
] = ' ';
2691 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
2692 input_line_pointer
= tmpbuf
;
2697 exp_seg
= expression (exp
);
2700 if (*input_line_pointer
)
2701 as_bad (_("ignoring junk `%s' after expression"), input_line_pointer
);
2703 input_line_pointer
= save_input_line_pointer
;
2705 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
2707 /* Missing or bad expr becomes absolute 0. */
2708 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
2710 exp
->X_op
= O_constant
;
2711 exp
->X_add_number
= 0;
2712 exp
->X_add_symbol
= (symbolS
*) 0;
2713 exp
->X_op_symbol
= (symbolS
*) 0;
2716 if (exp
->X_op
== O_constant
)
2718 /* Size it properly later. */
2719 i
.types
[this_operand
] |= Imm32
;
2721 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
2723 #ifdef BFD_ASSEMBLER
2724 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
2726 && exp_seg
!= text_section
2727 && exp_seg
!= data_section
2728 && exp_seg
!= bss_section
2729 && exp_seg
!= undefined_section
2730 #ifdef BFD_ASSEMBLER
2731 && !bfd_is_com_section (exp_seg
)
2735 #ifdef BFD_ASSEMBLER
2736 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
2738 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
2745 /* This is an address. The size of the address will be
2746 determined later, depending on destination register,
2747 suffix, or the default for the section. We exclude
2748 Imm8S here so that `push $foo' and other instructions
2749 with an Imm8S form will use Imm16 or Imm32. */
2750 i
.types
[this_operand
] |= (Imm8
| Imm16
| Imm32
);
2756 static int i386_scale
PARAMS ((char *));
2762 if (!isdigit (*scale
))
2769 i
.log2_scale_factor
= 0;
2772 i
.log2_scale_factor
= 1;
2775 i
.log2_scale_factor
= 2;
2778 i
.log2_scale_factor
= 3;
2782 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
2786 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
2788 as_warn (_("scale factor of %d without an index register"),
2789 1 << i
.log2_scale_factor
);
2790 #if SCALE1_WHEN_NO_INDEX
2791 i
.log2_scale_factor
= 0;
2797 static int i386_displacement
PARAMS ((char *, char *));
2800 i386_displacement (disp_start
, disp_end
)
2804 register expressionS
*exp
;
2806 char *save_input_line_pointer
;
2807 int bigdisp
= Disp32
;
2809 if (flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0))
2811 i
.types
[this_operand
] |= bigdisp
;
2813 exp
= &disp_expressions
[i
.disp_operands
];
2814 i
.op
[this_operand
].disps
= exp
;
2816 save_input_line_pointer
= input_line_pointer
;
2817 input_line_pointer
= disp_start
;
2818 END_STRING_AND_SAVE (disp_end
);
2820 #ifndef GCC_ASM_O_HACK
2821 #define GCC_ASM_O_HACK 0
2824 END_STRING_AND_SAVE (disp_end
+ 1);
2825 if ((i
.types
[this_operand
] & BaseIndex
) != 0
2826 && displacement_string_end
[-1] == '+')
2828 /* This hack is to avoid a warning when using the "o"
2829 constraint within gcc asm statements.
2832 #define _set_tssldt_desc(n,addr,limit,type) \
2833 __asm__ __volatile__ ( \
2835 "movw %w1,2+%0\n\t" \
2837 "movb %b1,4+%0\n\t" \
2838 "movb %4,5+%0\n\t" \
2839 "movb $0,6+%0\n\t" \
2840 "movb %h1,7+%0\n\t" \
2842 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
2844 This works great except that the output assembler ends
2845 up looking a bit weird if it turns out that there is
2846 no offset. You end up producing code that looks like:
2859 So here we provide the missing zero. */
2861 *displacement_string_end
= '0';
2866 /* We can have operands of the form
2867 <symbol>@GOTOFF+<nnn>
2868 Take the easy way out here and copy everything
2869 into a temporary buffer... */
2872 cp
= strchr (input_line_pointer
, '@');
2879 /* GOT relocations are not supported in 16 bit mode. */
2880 if (flag_16bit_code
)
2881 as_bad (_("GOT relocations not supported in 16 bit mode"));
2883 if (GOT_symbol
== NULL
)
2884 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
2886 if (strncmp (cp
+ 1, "PLT", 3) == 0)
2888 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
2891 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
2893 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
2896 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
2898 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
2902 as_bad (_("bad reloc specifier in expression"));
2904 /* Replace the relocation token with ' ', so that errors like
2905 foo@GOTOFF1 will be detected. */
2906 first
= cp
- input_line_pointer
;
2907 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
2908 memcpy (tmpbuf
, input_line_pointer
, first
);
2909 tmpbuf
[first
] = ' ';
2910 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
2911 input_line_pointer
= tmpbuf
;
2916 exp_seg
= expression (exp
);
2918 #ifdef BFD_ASSEMBLER
2919 /* We do this to make sure that the section symbol is in
2920 the symbol table. We will ultimately change the relocation
2921 to be relative to the beginning of the section. */
2922 if (i
.disp_reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
)
2924 if (S_IS_LOCAL(exp
->X_add_symbol
)
2925 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
2926 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
2927 assert (exp
->X_op
== O_symbol
);
2928 exp
->X_op
= O_subtract
;
2929 exp
->X_op_symbol
= GOT_symbol
;
2930 i
.disp_reloc
[this_operand
] = BFD_RELOC_32
;
2935 if (*input_line_pointer
)
2936 as_bad (_("ignoring junk `%s' after expression"),
2937 input_line_pointer
);
2939 RESTORE_END_STRING (disp_end
+ 1);
2941 RESTORE_END_STRING (disp_end
);
2942 input_line_pointer
= save_input_line_pointer
;
2944 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
2946 /* Missing or bad expr becomes absolute 0. */
2947 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2949 exp
->X_op
= O_constant
;
2950 exp
->X_add_number
= 0;
2951 exp
->X_add_symbol
= (symbolS
*) 0;
2952 exp
->X_op_symbol
= (symbolS
*) 0;
2955 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
2956 if (exp
->X_op
!= O_constant
2957 #ifdef BFD_ASSEMBLER
2958 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
2960 && exp_seg
!= text_section
2961 && exp_seg
!= data_section
2962 && exp_seg
!= bss_section
2963 && exp_seg
!= undefined_section
)
2965 #ifdef BFD_ASSEMBLER
2966 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
2968 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
2976 static int i386_operand_modifier
PARAMS ((char **, int));
2979 i386_operand_modifier (op_string
, got_a_float
)
2983 if (!strncasecmp (*op_string
, "BYTE PTR", 8))
2985 i
.suffix
= BYTE_MNEM_SUFFIX
;
2990 else if (!strncasecmp (*op_string
, "WORD PTR", 8))
2992 if (got_a_float
== 2) /* "fi..." */
2993 i
.suffix
= SHORT_MNEM_SUFFIX
;
2995 i
.suffix
= WORD_MNEM_SUFFIX
;
3000 else if (!strncasecmp (*op_string
, "DWORD PTR", 9))
3002 if (got_a_float
== 1) /* "f..." */
3003 i
.suffix
= SHORT_MNEM_SUFFIX
;
3005 i
.suffix
= LONG_MNEM_SUFFIX
;
3010 else if (!strncasecmp (*op_string
, "QWORD PTR", 9))
3012 i
.suffix
= DWORD_MNEM_SUFFIX
;
3017 else if (!strncasecmp (*op_string
, "XWORD PTR", 9))
3019 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
3024 else if (!strncasecmp (*op_string
, "SHORT", 5))
3030 else if (!strncasecmp (*op_string
, "OFFSET FLAT:", 12))
3036 else if (!strncasecmp (*op_string
, "FLAT", 4))
3042 else return NONE_FOUND
;
3045 static char * build_displacement_string
PARAMS ((int, char *));
3048 build_displacement_string (initial_disp
, op_string
)
3052 char *temp_string
= (char *) malloc (strlen (op_string
) + 1);
3053 char *end_of_operand_string
;
3057 temp_string
[0] = '\0';
3058 tc
= end_of_operand_string
= strchr (op_string
, '[');
3059 if (initial_disp
&& !end_of_operand_string
)
3061 strcpy (temp_string
, op_string
);
3065 /* Build the whole displacement string. */
3068 strncpy (temp_string
, op_string
, end_of_operand_string
- op_string
);
3069 temp_string
[end_of_operand_string
- op_string
] = '\0';
3073 temp_disp
= op_string
;
3075 while (*temp_disp
!= '\0')
3078 int add_minus
= (*temp_disp
== '-');
3080 if (*temp_disp
== '+' || *temp_disp
== '-' || *temp_disp
== '[')
3083 if (is_space_char (*temp_disp
))
3086 /* Don't consider registers. */
3087 if ( !((*temp_disp
== REGISTER_PREFIX
|| allow_naked_reg
)
3088 && parse_register (temp_disp
, &end_op
)) )
3090 char *string_start
= temp_disp
;
3092 while (*temp_disp
!= ']'
3093 && *temp_disp
!= '+'
3094 && *temp_disp
!= '-'
3095 && *temp_disp
!= '*')
3099 strcat (temp_string
, "-");
3101 strcat (temp_string
, "+");
3103 strncat (temp_string
, string_start
, temp_disp
- string_start
);
3104 if (*temp_disp
== '+' || *temp_disp
== '-')
3108 while (*temp_disp
!= '\0'
3109 && *temp_disp
!= '+'
3110 && *temp_disp
!= '-')
3117 static int i386_parse_seg
PARAMS ((char *));
3120 i386_parse_seg (op_string
)
3123 if (is_space_char (*op_string
))
3126 /* Should be one of es, cs, ss, ds fs or gs. */
3127 switch (*op_string
++)
3130 i
.seg
[i
.mem_operands
] = &es
;
3133 i
.seg
[i
.mem_operands
] = &cs
;
3136 i
.seg
[i
.mem_operands
] = &ss
;
3139 i
.seg
[i
.mem_operands
] = &ds
;
3142 i
.seg
[i
.mem_operands
] = &fs
;
3145 i
.seg
[i
.mem_operands
] = &gs
;
3148 as_bad (_("bad segment name `%s'"), op_string
);
3152 if (*op_string
++ != 's')
3154 as_bad (_("bad segment name `%s'"), op_string
);
3158 if (is_space_char (*op_string
))
3161 if (*op_string
!= ':')
3163 as_bad (_("bad segment name `%s'"), op_string
);
3171 static int i386_index_check
PARAMS((const char *));
3173 /* Make sure the memory operand we've been dealt is valid.
3174 Return 1 on success, 0 on a failure. */
3177 i386_index_check (operand_string
)
3178 const char *operand_string
;
3180 #if INFER_ADDR_PREFIX
3185 if (flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0)
3186 /* 16 bit mode checks. */
3188 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
))
3189 != (Reg16
|BaseIndex
)))
3191 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
3192 != (Reg16
|BaseIndex
))
3194 && i
.base_reg
->reg_num
< 6
3195 && i
.index_reg
->reg_num
>= 6
3196 && i
.log2_scale_factor
== 0))))
3197 /* 32 bit mode checks. */
3199 && (i
.base_reg
->reg_type
& Reg32
) == 0)
3201 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
))
3202 != (Reg32
|BaseIndex
)))))
3204 #if INFER_ADDR_PREFIX
3205 if (i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3207 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3209 /* Change the size of any displacement too. At most one of
3210 Disp16 or Disp32 is set.
3211 FIXME. There doesn't seem to be any real need for separate
3212 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3213 Removing them would probably clean up the code quite a lot. */
3214 if (i
.types
[this_operand
] & (Disp16
|Disp32
))
3215 i
.types
[this_operand
] ^= (Disp16
|Disp32
);
3220 as_bad (_("`%s' is not a valid base/index expression"),
3224 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3226 flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0) ? "16" : "32");
3232 static int i386_intel_memory_operand
PARAMS ((char *));
3235 i386_intel_memory_operand (operand_string
)
3236 char *operand_string
;
3238 char *op_string
= operand_string
;
3239 char *end_of_operand_string
;
3241 if ((i
.mem_operands
== 1
3242 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3243 || i
.mem_operands
== 2)
3245 as_bad (_("too many memory references for `%s'"),
3246 current_templates
->start
->name
);
3250 /* First check for a segment override. */
3251 if (*op_string
!= '[')
3255 end_seg
= strchr (op_string
, ':');
3258 if (!i386_parse_seg (op_string
))
3260 op_string
= end_seg
+ 1;
3264 /* Look for displacement preceding open bracket. */
3265 if (*op_string
!= '[')
3269 if (i
.disp_operands
)
3272 temp_string
= build_displacement_string (true, op_string
);
3274 if (!i386_displacement (temp_string
, temp_string
+ strlen (temp_string
)))
3281 end_of_operand_string
= strchr (op_string
, '[');
3282 if (!end_of_operand_string
)
3283 end_of_operand_string
= op_string
+ strlen (op_string
);
3285 if (is_space_char (*end_of_operand_string
))
3286 --end_of_operand_string
;
3288 op_string
= end_of_operand_string
;
3291 if (*op_string
== '[')
3295 /* Pick off each component and figure out where it belongs */
3297 end_of_operand_string
= op_string
;
3299 while (*op_string
!= ']')
3301 const reg_entry
*temp_reg
;
3305 while (*end_of_operand_string
!= '+'
3306 && *end_of_operand_string
!= '-'
3307 && *end_of_operand_string
!= '*'
3308 && *end_of_operand_string
!= ']')
3309 end_of_operand_string
++;
3311 temp_string
= op_string
;
3312 if (*temp_string
== '+')
3315 if (is_space_char (*temp_string
))
3319 if ((*temp_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3320 && (temp_reg
= parse_register (temp_string
, &end_op
)) != NULL
)
3322 if (i
.base_reg
== NULL
)
3323 i
.base_reg
= temp_reg
;
3325 i
.index_reg
= temp_reg
;
3327 i
.types
[this_operand
] |= BaseIndex
;
3329 else if (*temp_string
== REGISTER_PREFIX
)
3331 as_bad (_("bad register name `%s'"), temp_string
);
3334 else if (is_digit_char (*op_string
)
3335 || *op_string
== '+' || *op_string
== '-')
3339 if (i
.disp_operands
!= 0)
3342 temp_string
= build_displacement_string (false, op_string
);
3344 temp_str
= temp_string
;
3345 if (*temp_str
== '+')
3348 if (!i386_displacement (temp_str
, temp_str
+ strlen (temp_str
)))
3356 end_of_operand_string
= op_string
;
3357 while (*end_of_operand_string
!= ']'
3358 && *end_of_operand_string
!= '+'
3359 && *end_of_operand_string
!= '-'
3360 && *end_of_operand_string
!= '*')
3361 ++end_of_operand_string
;
3363 else if (*op_string
== '*')
3367 if (i
.base_reg
&& !i
.index_reg
)
3369 i
.index_reg
= i
.base_reg
;
3373 if (!i386_scale (op_string
))
3376 op_string
= end_of_operand_string
;
3377 ++end_of_operand_string
;
3381 if (i386_index_check (operand_string
) == 0)
3389 i386_intel_operand (operand_string
, got_a_float
)
3390 char *operand_string
;
3395 char *op_string
= operand_string
;
3397 int operand_modifier
= i386_operand_modifier (&op_string
, got_a_float
);
3398 if (is_space_char (*op_string
))
3401 switch (operand_modifier
)
3408 if (!i386_intel_memory_operand (op_string
))
3414 if (!i386_immediate (op_string
))
3420 /* Should be register or immediate */
3421 if (is_digit_char (*op_string
)
3422 && strchr (op_string
, '[') == 0)
3424 if (!i386_immediate (op_string
))
3427 else if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3428 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3430 /* Check for a segment override by searching for ':' after a
3431 segment register. */
3433 if (is_space_char (*op_string
))
3435 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3440 i
.seg
[i
.mem_operands
] = &es
;
3443 i
.seg
[i
.mem_operands
] = &cs
;
3446 i
.seg
[i
.mem_operands
] = &ss
;
3449 i
.seg
[i
.mem_operands
] = &ds
;
3452 i
.seg
[i
.mem_operands
] = &fs
;
3455 i
.seg
[i
.mem_operands
] = &gs
;
3460 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3461 i
.op
[this_operand
].regs
= r
;
3464 else if (*op_string
== REGISTER_PREFIX
)
3466 as_bad (_("bad register name `%s'"), op_string
);
3469 else if (!i386_intel_memory_operand (op_string
))
3478 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3482 i386_operand (operand_string
)
3483 char *operand_string
;
3487 char *op_string
= operand_string
;
3489 if (is_space_char (*op_string
))
3492 /* We check for an absolute prefix (differentiating,
3493 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3494 if (*op_string
== ABSOLUTE_PREFIX
)
3497 if (is_space_char (*op_string
))
3499 i
.types
[this_operand
] |= JumpAbsolute
;
3502 /* Check if operand is a register. */
3503 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3504 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3506 /* Check for a segment override by searching for ':' after a
3507 segment register. */
3509 if (is_space_char (*op_string
))
3511 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3516 i
.seg
[i
.mem_operands
] = &es
;
3519 i
.seg
[i
.mem_operands
] = &cs
;
3522 i
.seg
[i
.mem_operands
] = &ss
;
3525 i
.seg
[i
.mem_operands
] = &ds
;
3528 i
.seg
[i
.mem_operands
] = &fs
;
3531 i
.seg
[i
.mem_operands
] = &gs
;
3535 /* Skip the ':' and whitespace. */
3537 if (is_space_char (*op_string
))
3540 if (!is_digit_char (*op_string
)
3541 && !is_identifier_char (*op_string
)
3542 && *op_string
!= '('
3543 && *op_string
!= ABSOLUTE_PREFIX
)
3545 as_bad (_("bad memory operand `%s'"), op_string
);
3548 /* Handle case of %es:*foo. */
3549 if (*op_string
== ABSOLUTE_PREFIX
)
3552 if (is_space_char (*op_string
))
3554 i
.types
[this_operand
] |= JumpAbsolute
;
3556 goto do_memory_reference
;
3560 as_bad (_("junk `%s' after register"), op_string
);
3563 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3564 i
.op
[this_operand
].regs
= r
;
3567 else if (*op_string
== REGISTER_PREFIX
)
3569 as_bad (_("bad register name `%s'"), op_string
);
3572 else if (*op_string
== IMMEDIATE_PREFIX
)
3573 { /* ... or an immediate */
3575 if (i
.types
[this_operand
] & JumpAbsolute
)
3577 as_bad (_("immediate operand illegal with absolute jump"));
3580 if (!i386_immediate (op_string
))
3583 else if (is_digit_char (*op_string
)
3584 || is_identifier_char (*op_string
)
3585 || *op_string
== '(' )
3587 /* This is a memory reference of some sort. */
3590 /* Start and end of displacement string expression (if found). */
3591 char *displacement_string_start
;
3592 char *displacement_string_end
;
3594 do_memory_reference
:
3595 if ((i
.mem_operands
== 1
3596 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3597 || i
.mem_operands
== 2)
3599 as_bad (_("too many memory references for `%s'"),
3600 current_templates
->start
->name
);
3604 /* Check for base index form. We detect the base index form by
3605 looking for an ')' at the end of the operand, searching
3606 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3608 base_string
= op_string
+ strlen (op_string
);
3611 if (is_space_char (*base_string
))
3614 /* If we only have a displacement, set-up for it to be parsed later. */
3615 displacement_string_start
= op_string
;
3616 displacement_string_end
= base_string
+ 1;
3618 if (*base_string
== ')')
3621 unsigned int parens_balanced
= 1;
3622 /* We've already checked that the number of left & right ()'s are
3623 equal, so this loop will not be infinite. */
3627 if (*base_string
== ')')
3629 if (*base_string
== '(')
3632 while (parens_balanced
);
3634 temp_string
= base_string
;
3636 /* Skip past '(' and whitespace. */
3638 if (is_space_char (*base_string
))
3641 if (*base_string
== ','
3642 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3643 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
3645 displacement_string_end
= temp_string
;
3647 i
.types
[this_operand
] |= BaseIndex
;
3651 base_string
= end_op
;
3652 if (is_space_char (*base_string
))
3656 /* There may be an index reg or scale factor here. */
3657 if (*base_string
== ',')
3660 if (is_space_char (*base_string
))
3663 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3664 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
3666 base_string
= end_op
;
3667 if (is_space_char (*base_string
))
3669 if (*base_string
== ',')
3672 if (is_space_char (*base_string
))
3675 else if (*base_string
!= ')' )
3677 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3682 else if (*base_string
== REGISTER_PREFIX
)
3684 as_bad (_("bad register name `%s'"), base_string
);
3688 /* Check for scale factor. */
3689 if (isdigit ((unsigned char) *base_string
))
3691 if (!i386_scale (base_string
))
3695 if (is_space_char (*base_string
))
3697 if (*base_string
!= ')')
3699 as_bad (_("expecting `)' after scale factor in `%s'"),
3704 else if (!i
.index_reg
)
3706 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3711 else if (*base_string
!= ')')
3713 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3718 else if (*base_string
== REGISTER_PREFIX
)
3720 as_bad (_("bad register name `%s'"), base_string
);
3725 /* If there's an expression beginning the operand, parse it,
3726 assuming displacement_string_start and
3727 displacement_string_end are meaningful. */
3728 if (displacement_string_start
!= displacement_string_end
)
3730 if (!i386_displacement (displacement_string_start
,
3731 displacement_string_end
))
3735 /* Special case for (%dx) while doing input/output op. */
3737 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
3739 && i
.log2_scale_factor
== 0
3740 && i
.seg
[i
.mem_operands
] == 0
3741 && (i
.types
[this_operand
] & Disp
) == 0)
3743 i
.types
[this_operand
] = InOutPortReg
;
3747 if (i386_index_check (operand_string
) == 0)
3752 { /* It's not a memory operand; argh! */
3753 as_bad (_("invalid char %s beginning operand %d `%s'"),
3754 output_invalid (*op_string
),
3759 return 1; /* Normal return. */
3762 /* md_estimate_size_before_relax()
3764 Called just before relax() for rs_machine_dependent frags. The x86
3765 assembler uses these frags to handle variable size jump
3768 Any symbol that is now undefined will not become defined.
3769 Return the correct fr_subtype in the frag.
3770 Return the initial "guess for variable size of frag" to caller.
3771 The guess is actually the growth beyond the fixed part. Whatever
3772 we do to grow the fixed or variable part contributes to our
3776 md_estimate_size_before_relax (fragP
, segment
)
3777 register fragS
*fragP
;
3778 register segT segment
;
3780 /* We've already got fragP->fr_subtype right; all we have to do is
3781 check for un-relaxable symbols. On an ELF system, we can't relax
3782 an externally visible symbol, because it may be overridden by a
3784 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3785 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3786 || S_IS_EXTERNAL (fragP
->fr_symbol
)
3787 || S_IS_WEAK (fragP
->fr_symbol
)
3791 /* Symbol is undefined in this segment, or we need to keep a
3792 reloc so that weak symbols can be overridden. */
3793 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
3794 #ifdef BFD_ASSEMBLER
3795 enum bfd_reloc_code_real reloc_type
;
3799 unsigned char *opcode
;
3802 if (fragP
->fr_var
!= NO_RELOC
)
3803 reloc_type
= fragP
->fr_var
;
3805 reloc_type
= BFD_RELOC_16_PCREL
;
3807 reloc_type
= BFD_RELOC_32_PCREL
;
3809 old_fr_fix
= fragP
->fr_fix
;
3810 opcode
= (unsigned char *) fragP
->fr_opcode
;
3814 case JUMP_PC_RELATIVE
:
3815 /* Make jmp (0xeb) a dword displacement jump. */
3816 /* dword disp jmp */
3818 fragP
->fr_fix
+= size
;
3819 fix_new (fragP
, old_fr_fix
, size
,
3821 fragP
->fr_offset
, 1,
3826 /* This changes the byte-displacement jump 0x7N
3827 to the dword-displacement jump 0x0f,0x8N. */
3828 opcode
[1] = opcode
[0] + 0x10;
3829 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3830 /* We've added an opcode byte. */
3831 fragP
->fr_fix
+= 1 + size
;
3832 fix_new (fragP
, old_fr_fix
+ 1, size
,
3834 fragP
->fr_offset
, 1,
3839 return fragP
->fr_fix
- old_fr_fix
;
3841 /* Guess a short jump. */
3845 /* Called after relax() is finished.
3847 In: Address of frag.
3848 fr_type == rs_machine_dependent.
3849 fr_subtype is what the address relaxed to.
3851 Out: Any fixSs and constants are set up.
3852 Caller will turn frag into a ".space 0". */
3854 #ifndef BFD_ASSEMBLER
3856 md_convert_frag (headers
, sec
, fragP
)
3857 object_headers
*headers ATTRIBUTE_UNUSED
;
3858 segT sec ATTRIBUTE_UNUSED
;
3859 register fragS
*fragP
;
3862 md_convert_frag (abfd
, sec
, fragP
)
3863 bfd
*abfd ATTRIBUTE_UNUSED
;
3864 segT sec ATTRIBUTE_UNUSED
;
3865 register fragS
*fragP
;
3868 register unsigned char *opcode
;
3869 unsigned char *where_to_put_displacement
= NULL
;
3870 offsetT target_address
;
3871 offsetT opcode_address
;
3872 unsigned int extension
= 0;
3873 offsetT displacement_from_opcode_start
;
3875 opcode
= (unsigned char *) fragP
->fr_opcode
;
3877 /* Address we want to reach in file space. */
3878 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
3879 #ifdef BFD_ASSEMBLER
3880 /* Not needed otherwise? */
3881 target_address
+= symbol_get_frag (fragP
->fr_symbol
)->fr_address
;
3884 /* Address opcode resides at in file space. */
3885 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
3887 /* Displacement from opcode start to fill into instruction. */
3888 displacement_from_opcode_start
= target_address
- opcode_address
;
3890 switch (fragP
->fr_subtype
)
3892 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL
):
3893 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL16
):
3894 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
):
3895 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL16
):
3896 /* Don't have to change opcode. */
3897 extension
= 1; /* 1 opcode + 1 displacement */
3898 where_to_put_displacement
= &opcode
[1];
3901 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
3902 extension
= 5; /* 2 opcode + 4 displacement */
3903 opcode
[1] = opcode
[0] + 0x10;
3904 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3905 where_to_put_displacement
= &opcode
[2];
3908 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
3909 extension
= 4; /* 1 opcode + 4 displacement */
3911 where_to_put_displacement
= &opcode
[1];
3914 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
3915 extension
= 3; /* 2 opcode + 2 displacement */
3916 opcode
[1] = opcode
[0] + 0x10;
3917 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3918 where_to_put_displacement
= &opcode
[2];
3921 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
3922 extension
= 2; /* 1 opcode + 2 displacement */
3924 where_to_put_displacement
= &opcode
[1];
3928 BAD_CASE (fragP
->fr_subtype
);
3931 /* Now put displacement after opcode. */
3932 md_number_to_chars ((char *) where_to_put_displacement
,
3933 (valueT
) (displacement_from_opcode_start
- extension
),
3934 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
3935 fragP
->fr_fix
+= extension
;
3938 /* Size of byte displacement jmp. */
3939 int md_short_jump_size
= 2;
3941 /* Size of dword displacement jmp. */
3942 int md_long_jump_size
= 5;
3944 /* Size of relocation record. */
3945 const int md_reloc_size
= 8;
3948 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
3950 addressT from_addr
, to_addr
;
3951 fragS
*frag ATTRIBUTE_UNUSED
;
3952 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
3956 offset
= to_addr
- (from_addr
+ 2);
3957 /* Opcode for byte-disp jump. */
3958 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
3959 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
3963 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
3965 addressT from_addr
, to_addr
;
3966 fragS
*frag ATTRIBUTE_UNUSED
;
3967 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
3971 offset
= to_addr
- (from_addr
+ 5);
3972 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
3973 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
3976 /* Apply a fixup (fixS) to segment data, once it has been determined
3977 by our caller that we have all the info we need to fix it up.
3979 On the 386, immediates, displacements, and data pointers are all in
3980 the same (little-endian) format, so we don't need to care about which
3984 md_apply_fix3 (fixP
, valp
, seg
)
3985 /* The fix we're to put in. */
3988 /* Pointer to the value of the bits. */
3991 /* Segment fix is from. */
3992 segT seg ATTRIBUTE_UNUSED
;
3994 register char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3995 valueT value
= *valp
;
3997 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4000 switch (fixP
->fx_r_type
)
4006 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4009 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4012 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4017 /* This is a hack. There should be a better way to handle this.
4018 This covers for the fact that bfd_install_relocation will
4019 subtract the current location (for partial_inplace, PC relative
4020 relocations); see more below. */
4021 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4022 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4023 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4027 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4029 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4032 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4034 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4035 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4037 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4040 || (symbol_section_p (fixP
->fx_addsy
)
4041 && fseg
!= absolute_section
))
4042 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
4043 && ! S_IS_WEAK (fixP
->fx_addsy
)
4044 && S_IS_DEFINED (fixP
->fx_addsy
)
4045 && ! S_IS_COMMON (fixP
->fx_addsy
))
4047 /* Yes, we add the values in twice. This is because
4048 bfd_perform_relocation subtracts them out again. I think
4049 bfd_perform_relocation is broken, but I don't dare change
4051 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4055 #if defined (OBJ_COFF) && defined (TE_PE)
4056 /* For some reason, the PE format does not store a section
4057 address offset for a PC relative symbol. */
4058 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4059 value
+= md_pcrel_from (fixP
);
4063 /* Fix a few things - the dynamic linker expects certain values here,
4064 and we must not dissappoint it. */
4065 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4066 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4068 switch (fixP
->fx_r_type
)
4070 case BFD_RELOC_386_PLT32
:
4071 /* Make the jump instruction point to the address of the operand. At
4072 runtime we merely add the offset to the actual PLT entry. */
4075 case BFD_RELOC_386_GOTPC
:
4077 /* This is tough to explain. We end up with this one if we have
4078 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4079 * here is to obtain the absolute address of the GOT, and it is strongly
4080 * preferable from a performance point of view to avoid using a runtime
4081 * relocation for this. The actual sequence of instructions often look
4087 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4089 * The call and pop essentially return the absolute address of
4090 * the label .L66 and store it in %ebx. The linker itself will
4091 * ultimately change the first operand of the addl so that %ebx points to
4092 * the GOT, but to keep things simple, the .o file must have this operand
4093 * set so that it generates not the absolute address of .L66, but the
4094 * absolute address of itself. This allows the linker itself simply
4095 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4096 * added in, and the addend of the relocation is stored in the operand
4097 * field for the instruction itself.
4099 * Our job here is to fix the operand so that it would add the correct
4100 * offset so that %ebx would point to itself. The thing that is tricky is
4101 * that .-.L66 will point to the beginning of the instruction, so we need
4102 * to further modify the operand so that it will point to itself.
4103 * There are other cases where you have something like:
4105 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4107 * and here no correction would be required. Internally in the assembler
4108 * we treat operands of this form as not being pcrel since the '.' is
4109 * explicitly mentioned, and I wonder whether it would simplify matters
4110 * to do it this way. Who knows. In earlier versions of the PIC patches,
4111 * the pcrel_adjust field was used to store the correction, but since the
4112 * expression is not pcrel, I felt it would be confusing to do it this
4117 case BFD_RELOC_386_GOT32
:
4118 value
= 0; /* Fully resolved at runtime. No addend. */
4120 case BFD_RELOC_386_GOTOFF
:
4123 case BFD_RELOC_VTABLE_INHERIT
:
4124 case BFD_RELOC_VTABLE_ENTRY
:
4131 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4133 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4134 md_number_to_chars (p
, value
, fixP
->fx_size
);
4139 #define MAX_LITTLENUMS 6
4141 /* Turn the string pointed to by litP into a floating point constant
4142 of type TYPE, and emit the appropriate bytes. The number of
4143 LITTLENUMS emitted is stored in *SIZEP. An error message is
4144 returned, or NULL on OK. */
4147 md_atof (type
, litP
, sizeP
)
4153 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4154 LITTLENUM_TYPE
*wordP
;
4176 return _("Bad call to md_atof ()");
4178 t
= atof_ieee (input_line_pointer
, type
, words
);
4180 input_line_pointer
= t
;
4182 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4183 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4184 the bigendian 386. */
4185 for (wordP
= words
+ prec
- 1; prec
--;)
4187 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4188 litP
+= sizeof (LITTLENUM_TYPE
);
4193 char output_invalid_buf
[8];
4200 sprintf (output_invalid_buf
, "'%c'", c
);
4202 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4203 return output_invalid_buf
;
4206 /* REG_STRING starts *before* REGISTER_PREFIX. */
4208 static const reg_entry
*
4209 parse_register (reg_string
, end_op
)
4213 char *s
= reg_string
;
4215 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4218 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4219 if (*s
== REGISTER_PREFIX
)
4222 if (is_space_char (*s
))
4226 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4228 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4229 return (const reg_entry
*) NULL
;
4235 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4237 /* Handle floating point regs, allowing spaces in the (i) part. */
4238 if (r
== i386_regtab
/* %st is first entry of table */)
4240 if (is_space_char (*s
))
4245 if (is_space_char (*s
))
4247 if (*s
>= '0' && *s
<= '7')
4249 r
= &i386_float_regtab
[*s
- '0'];
4251 if (is_space_char (*s
))
4259 /* We have "%st(" then garbage. */
4260 return (const reg_entry
*) NULL
;
4267 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4268 const char *md_shortopts
= "kVQ:sq";
4270 const char *md_shortopts
= "q";
4272 struct option md_longopts
[] = {
4273 {NULL
, no_argument
, NULL
, 0}
4275 size_t md_longopts_size
= sizeof (md_longopts
);
4278 md_parse_option (c
, arg
)
4280 char *arg ATTRIBUTE_UNUSED
;
4288 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4289 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4290 should be emitted or not. FIXME: Not implemented. */
4294 /* -V: SVR4 argument to print version ID. */
4296 print_version_id ();
4299 /* -k: Ignore for FreeBSD compatibility. */
4304 /* -s: On i386 Solaris, this tells the native assembler to use
4305 .stab instead of .stab.excl. We always use .stab anyhow. */
4316 md_show_usage (stream
)
4319 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4320 fprintf (stream
, _("\
4322 -V print assembler version number\n\
4324 -q quieten some warnings\n\
4327 fprintf (stream
, _("\
4328 -q quieten some warnings\n"));
4332 #ifdef BFD_ASSEMBLER
4333 #if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \
4334 || (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \
4335 || (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)))
4337 /* Pick the target format to use. */
4340 i386_target_format ()
4342 switch (OUTPUT_FLAVOR
)
4344 #ifdef OBJ_MAYBE_AOUT
4345 case bfd_target_aout_flavour
:
4346 return AOUT_TARGET_FORMAT
;
4348 #ifdef OBJ_MAYBE_COFF
4349 case bfd_target_coff_flavour
:
4352 #ifdef OBJ_MAYBE_ELF
4353 case bfd_target_elf_flavour
:
4354 return "elf32-i386";
4362 #endif /* OBJ_MAYBE_ more than one */
4363 #endif /* BFD_ASSEMBLER */
4366 md_undefined_symbol (name
)
4369 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4370 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4371 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4372 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4376 if (symbol_find (name
))
4377 as_bad (_("GOT already in symbol table"));
4378 GOT_symbol
= symbol_new (name
, undefined_section
,
4379 (valueT
) 0, &zero_address_frag
);
4386 /* Round up a section size to the appropriate boundary. */
4389 md_section_align (segment
, size
)
4390 segT segment ATTRIBUTE_UNUSED
;
4393 #ifdef BFD_ASSEMBLER
4394 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4395 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4397 /* For a.out, force the section size to be aligned. If we don't do
4398 this, BFD will align it for us, but it will not write out the
4399 final bytes of the section. This may be a bug in BFD, but it is
4400 easier to fix it here since that is how the other a.out targets
4404 align
= bfd_get_section_alignment (stdoutput
, segment
);
4405 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4413 /* On the i386, PC-relative offsets are relative to the start of the
4414 next instruction. That is, the address of the offset, plus its
4415 size, since the offset is always the last part of the insn. */
4418 md_pcrel_from (fixP
)
4421 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4428 int ignore ATTRIBUTE_UNUSED
;
4432 temp
= get_absolute_expression ();
4433 subseg_set (bss_section
, (subsegT
) temp
);
4434 demand_empty_rest_of_line ();
4439 #ifdef BFD_ASSEMBLER
4442 i386_validate_fix (fixp
)
4445 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
4447 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
4453 tc_gen_reloc (section
, fixp
)
4454 asection
*section ATTRIBUTE_UNUSED
;
4458 bfd_reloc_code_real_type code
;
4460 switch (fixp
->fx_r_type
)
4462 case BFD_RELOC_386_PLT32
:
4463 case BFD_RELOC_386_GOT32
:
4464 case BFD_RELOC_386_GOTOFF
:
4465 case BFD_RELOC_386_GOTPC
:
4467 case BFD_RELOC_VTABLE_ENTRY
:
4468 case BFD_RELOC_VTABLE_INHERIT
:
4469 code
= fixp
->fx_r_type
;
4474 switch (fixp
->fx_size
)
4477 as_bad (_("can not do %d byte pc-relative relocation"),
4479 code
= BFD_RELOC_32_PCREL
;
4481 case 1: code
= BFD_RELOC_8_PCREL
; break;
4482 case 2: code
= BFD_RELOC_16_PCREL
; break;
4483 case 4: code
= BFD_RELOC_32_PCREL
; break;
4488 switch (fixp
->fx_size
)
4491 as_bad (_("can not do %d byte relocation"), fixp
->fx_size
);
4492 code
= BFD_RELOC_32
;
4494 case 1: code
= BFD_RELOC_8
; break;
4495 case 2: code
= BFD_RELOC_16
; break;
4496 case 4: code
= BFD_RELOC_32
; break;
4502 if (code
== BFD_RELOC_32
4504 && fixp
->fx_addsy
== GOT_symbol
)
4505 code
= BFD_RELOC_386_GOTPC
;
4507 rel
= (arelent
*) xmalloc (sizeof (arelent
));
4508 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4509 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4511 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4512 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4513 vtable entry to be used in the relocation's section offset. */
4514 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4515 rel
->address
= fixp
->fx_offset
;
4518 rel
->addend
= fixp
->fx_addnumber
;
4522 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4523 if (rel
->howto
== NULL
)
4525 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4526 _("cannot represent relocation type %s"),
4527 bfd_get_reloc_code_name (code
));
4528 /* Set howto to a garbage value so that we can keep going. */
4529 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
4530 assert (rel
->howto
!= NULL
);
4536 #else /* ! BFD_ASSEMBLER */
4538 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4540 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4543 relax_addressT segment_address_in_file
;
4545 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4546 Out: GNU LD relocation length code: 0, 1, or 2. */
4548 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
4551 know (fixP
->fx_addsy
!= NULL
);
4553 md_number_to_chars (where
,
4554 (valueT
) (fixP
->fx_frag
->fr_address
4555 + fixP
->fx_where
- segment_address_in_file
),
4558 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4559 ? S_GET_TYPE (fixP
->fx_addsy
)
4560 : fixP
->fx_addsy
->sy_number
);
4562 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
4563 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4564 where
[4] = r_symbolnum
& 0x0ff;
4565 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
4566 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
4567 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
4570 #endif /* OBJ_AOUT or OBJ_BOUT. */
4572 #if defined (I386COFF)
4575 tc_coff_fix2rtype (fixP
)
4578 if (fixP
->fx_r_type
== R_IMAGEBASE
)
4581 return (fixP
->fx_pcrel
?
4582 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
4583 fixP
->fx_size
== 2 ? R_PCRWORD
:
4585 (fixP
->fx_size
== 1 ? R_RELBYTE
:
4586 fixP
->fx_size
== 2 ? R_RELWORD
:
4591 tc_coff_sizemachdep (frag
)
4595 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
4600 #endif /* I386COFF */
4602 #endif /* ! BFD_ASSEMBLER */