1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2017 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 /* Only one of NOTRACK_PREFIX and SEG_PREFIX can be used at the same
71 #define NOTRACK_PREFIX 6
72 #define REX_PREFIX 7 /* must come last. */
73 #define MAX_PREFIXES 8 /* max prefixes per opcode */
75 /* we define the syntax here (modulo base,index,scale syntax) */
76 #define REGISTER_PREFIX '%'
77 #define IMMEDIATE_PREFIX '$'
78 #define ABSOLUTE_PREFIX '*'
80 /* these are the instruction mnemonic suffixes in AT&T syntax or
81 memory operand size in Intel syntax. */
82 #define WORD_MNEM_SUFFIX 'w'
83 #define BYTE_MNEM_SUFFIX 'b'
84 #define SHORT_MNEM_SUFFIX 's'
85 #define LONG_MNEM_SUFFIX 'l'
86 #define QWORD_MNEM_SUFFIX 'q'
87 #define XMMWORD_MNEM_SUFFIX 'x'
88 #define YMMWORD_MNEM_SUFFIX 'y'
89 #define ZMMWORD_MNEM_SUFFIX 'z'
90 /* Intel Syntax. Use a non-ascii letter since since it never appears
92 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
94 #define END_OF_INSN '\0'
97 'templates' is for grouping together 'template' structures for opcodes
98 of the same name. This is only used for storing the insns in the grand
99 ole hash table of insns.
100 The templates themselves start at START and range up to (but not including)
105 const insn_template
*start
;
106 const insn_template
*end
;
110 /* 386 operand encoding bytes: see 386 book for details of this. */
113 unsigned int regmem
; /* codes register or memory operand */
114 unsigned int reg
; /* codes register operand (or extended opcode) */
115 unsigned int mode
; /* how to interpret regmem & reg */
119 /* x86-64 extension prefix. */
120 typedef int rex_byte
;
122 /* 386 opcode byte to code indirect addressing. */
131 /* x86 arch names, types and features */
134 const char *name
; /* arch name */
135 unsigned int len
; /* arch string length */
136 enum processor_type type
; /* arch type */
137 i386_cpu_flags flags
; /* cpu feature flags */
138 unsigned int skip
; /* show_arch should skip this. */
142 /* Used to turn off indicated flags. */
145 const char *name
; /* arch name */
146 unsigned int len
; /* arch string length */
147 i386_cpu_flags flags
; /* cpu feature flags */
151 static void update_code_flag (int, int);
152 static void set_code_flag (int);
153 static void set_16bit_gcc_code_flag (int);
154 static void set_intel_syntax (int);
155 static void set_intel_mnemonic (int);
156 static void set_allow_index_reg (int);
157 static void set_check (int);
158 static void set_cpu_arch (int);
160 static void pe_directive_secrel (int);
162 static void signed_cons (int);
163 static char *output_invalid (int c
);
164 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
166 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
168 static int i386_att_operand (char *);
169 static int i386_intel_operand (char *, int);
170 static int i386_intel_simplify (expressionS
*);
171 static int i386_intel_parse_name (const char *, expressionS
*);
172 static const reg_entry
*parse_register (char *, char **);
173 static char *parse_insn (char *, char *);
174 static char *parse_operands (char *, const char *);
175 static void swap_operands (void);
176 static void swap_2_operands (int, int);
177 static void optimize_imm (void);
178 static void optimize_disp (void);
179 static const insn_template
*match_template (char);
180 static int check_string (void);
181 static int process_suffix (void);
182 static int check_byte_reg (void);
183 static int check_long_reg (void);
184 static int check_qword_reg (void);
185 static int check_word_reg (void);
186 static int finalize_imm (void);
187 static int process_operands (void);
188 static const seg_entry
*build_modrm_byte (void);
189 static void output_insn (void);
190 static void output_imm (fragS
*, offsetT
);
191 static void output_disp (fragS
*, offsetT
);
193 static void s_bss (int);
195 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
196 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
199 static const char *default_arch
= DEFAULT_ARCH
;
201 /* This struct describes rounding control and SAE in the instruction. */
215 static struct RC_Operation rc_op
;
217 /* The struct describes masking, applied to OPERAND in the instruction.
218 MASK is a pointer to the corresponding mask register. ZEROING tells
219 whether merging or zeroing mask is used. */
220 struct Mask_Operation
222 const reg_entry
*mask
;
223 unsigned int zeroing
;
224 /* The operand where this operation is associated. */
228 static struct Mask_Operation mask_op
;
230 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
232 struct Broadcast_Operation
234 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
237 /* Index of broadcasted operand. */
241 static struct Broadcast_Operation broadcast_op
;
246 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
247 unsigned char bytes
[4];
249 /* Destination or source register specifier. */
250 const reg_entry
*register_specifier
;
253 /* 'md_assemble ()' gathers together information and puts it into a
260 const reg_entry
*regs
;
265 operand_size_mismatch
,
266 operand_type_mismatch
,
267 register_type_mismatch
,
268 number_of_operands_mismatch
,
269 invalid_instruction_suffix
,
272 unsupported_with_intel_mnemonic
,
275 invalid_vsib_address
,
276 invalid_vector_register_set
,
277 unsupported_vector_index_register
,
278 unsupported_broadcast
,
279 broadcast_not_on_src_operand
,
282 mask_not_on_destination
,
285 rc_sae_operand_not_last_imm
,
286 invalid_register_operand
,
292 /* TM holds the template for the insn were currently assembling. */
295 /* SUFFIX holds the instruction size suffix for byte, word, dword
296 or qword, if given. */
299 /* OPERANDS gives the number of given operands. */
300 unsigned int operands
;
302 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
303 of given register, displacement, memory operands and immediate
305 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
307 /* TYPES [i] is the type (see above #defines) which tells us how to
308 use OP[i] for the corresponding operand. */
309 i386_operand_type types
[MAX_OPERANDS
];
311 /* Displacement expression, immediate expression, or register for each
313 union i386_op op
[MAX_OPERANDS
];
315 /* Flags for operands. */
316 unsigned int flags
[MAX_OPERANDS
];
317 #define Operand_PCrel 1
319 /* Relocation type for operand */
320 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
322 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
323 the base index byte below. */
324 const reg_entry
*base_reg
;
325 const reg_entry
*index_reg
;
326 unsigned int log2_scale_factor
;
328 /* SEG gives the seg_entries of this insn. They are zero unless
329 explicit segment overrides are given. */
330 const seg_entry
*seg
[2];
332 /* Copied first memory operand string, for re-checking. */
335 /* PREFIX holds all the given prefix opcodes (usually null).
336 PREFIXES is the number of prefix opcodes. */
337 unsigned int prefixes
;
338 unsigned char prefix
[MAX_PREFIXES
];
340 /* RM and SIB are the modrm byte and the sib byte where the
341 addressing modes of this insn are encoded. */
348 /* Masking attributes. */
349 struct Mask_Operation
*mask
;
351 /* Rounding control and SAE attributes. */
352 struct RC_Operation
*rounding
;
354 /* Broadcasting attributes. */
355 struct Broadcast_Operation
*broadcast
;
357 /* Compressed disp8*N attribute. */
358 unsigned int memshift
;
360 /* Prefer load or store in encoding. */
363 dir_encoding_default
= 0,
368 /* Prefer 8bit or 32bit displacement in encoding. */
371 disp_encoding_default
= 0,
376 /* How to encode vector instructions. */
379 vex_encoding_default
= 0,
386 const char *rep_prefix
;
389 const char *hle_prefix
;
391 /* Have BND prefix. */
392 const char *bnd_prefix
;
394 /* Have NOTRACK prefix. */
395 const char *notrack_prefix
;
398 enum i386_error error
;
401 typedef struct _i386_insn i386_insn
;
403 /* Link RC type with corresponding string, that'll be looked for in
412 static const struct RC_name RC_NamesTable
[] =
414 { rne
, STRING_COMMA_LEN ("rn-sae") },
415 { rd
, STRING_COMMA_LEN ("rd-sae") },
416 { ru
, STRING_COMMA_LEN ("ru-sae") },
417 { rz
, STRING_COMMA_LEN ("rz-sae") },
418 { saeonly
, STRING_COMMA_LEN ("sae") },
421 /* List of chars besides those in app.c:symbol_chars that can start an
422 operand. Used to prevent the scrubber eating vital white-space. */
423 const char extra_symbol_chars
[] = "*%-([{}"
432 #if (defined (TE_I386AIX) \
433 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
434 && !defined (TE_GNU) \
435 && !defined (TE_LINUX) \
436 && !defined (TE_NACL) \
437 && !defined (TE_NETWARE) \
438 && !defined (TE_FreeBSD) \
439 && !defined (TE_DragonFly) \
440 && !defined (TE_NetBSD)))
441 /* This array holds the chars that always start a comment. If the
442 pre-processor is disabled, these aren't very useful. The option
443 --divide will remove '/' from this list. */
444 const char *i386_comment_chars
= "#/";
445 #define SVR4_COMMENT_CHARS 1
446 #define PREFIX_SEPARATOR '\\'
449 const char *i386_comment_chars
= "#";
450 #define PREFIX_SEPARATOR '/'
453 /* This array holds the chars that only start a comment at the beginning of
454 a line. If the line seems to have the form '# 123 filename'
455 .line and .file directives will appear in the pre-processed output.
456 Note that input_file.c hand checks for '#' at the beginning of the
457 first line of the input file. This is because the compiler outputs
458 #NO_APP at the beginning of its output.
459 Also note that comments started like this one will always work if
460 '/' isn't otherwise defined. */
461 const char line_comment_chars
[] = "#/";
463 const char line_separator_chars
[] = ";";
465 /* Chars that can be used to separate mant from exp in floating point
467 const char EXP_CHARS
[] = "eE";
469 /* Chars that mean this number is a floating point constant
472 const char FLT_CHARS
[] = "fFdDxX";
474 /* Tables for lexical analysis. */
475 static char mnemonic_chars
[256];
476 static char register_chars
[256];
477 static char operand_chars
[256];
478 static char identifier_chars
[256];
479 static char digit_chars
[256];
481 /* Lexical macros. */
482 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
483 #define is_operand_char(x) (operand_chars[(unsigned char) x])
484 #define is_register_char(x) (register_chars[(unsigned char) x])
485 #define is_space_char(x) ((x) == ' ')
486 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
487 #define is_digit_char(x) (digit_chars[(unsigned char) x])
489 /* All non-digit non-letter characters that may occur in an operand. */
490 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
492 /* md_assemble() always leaves the strings it's passed unaltered. To
493 effect this we maintain a stack of saved characters that we've smashed
494 with '\0's (indicating end of strings for various sub-fields of the
495 assembler instruction). */
496 static char save_stack
[32];
497 static char *save_stack_p
;
498 #define END_STRING_AND_SAVE(s) \
499 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
500 #define RESTORE_END_STRING(s) \
501 do { *(s) = *--save_stack_p; } while (0)
503 /* The instruction we're assembling. */
506 /* Possible templates for current insn. */
507 static const templates
*current_templates
;
509 /* Per instruction expressionS buffers: max displacements & immediates. */
510 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
511 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
513 /* Current operand we are working on. */
514 static int this_operand
= -1;
516 /* We support four different modes. FLAG_CODE variable is used to distinguish
524 static enum flag_code flag_code
;
525 static unsigned int object_64bit
;
526 static unsigned int disallow_64bit_reloc
;
527 static int use_rela_relocations
= 0;
529 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
530 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
531 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
533 /* The ELF ABI to use. */
541 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
544 #if defined (TE_PE) || defined (TE_PEP)
545 /* Use big object file format. */
546 static int use_big_obj
= 0;
549 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
550 /* 1 if generating code for a shared library. */
551 static int shared
= 0;
554 /* 1 for intel syntax,
556 static int intel_syntax
= 0;
558 /* 1 for Intel64 ISA,
562 /* 1 for intel mnemonic,
563 0 if att mnemonic. */
564 static int intel_mnemonic
= !SYSV386_COMPAT
;
566 /* 1 if support old (<= 2.8.1) versions of gcc. */
567 static int old_gcc
= OLDGCC_COMPAT
;
569 /* 1 if pseudo registers are permitted. */
570 static int allow_pseudo_reg
= 0;
572 /* 1 if register prefix % not required. */
573 static int allow_naked_reg
= 0;
575 /* 1 if the assembler should add BND prefix for all control-transferring
576 instructions supporting it, even if this prefix wasn't specified
578 static int add_bnd_prefix
= 0;
580 /* 1 if pseudo index register, eiz/riz, is allowed . */
581 static int allow_index_reg
= 0;
583 /* 1 if the assembler should ignore LOCK prefix, even if it was
584 specified explicitly. */
585 static int omit_lock_prefix
= 0;
587 /* 1 if the assembler should encode lfence, mfence, and sfence as
588 "lock addl $0, (%{re}sp)". */
589 static int avoid_fence
= 0;
591 /* 1 if the assembler should generate relax relocations. */
593 static int generate_relax_relocations
594 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
596 static enum check_kind
602 sse_check
, operand_check
= check_warning
;
604 /* Register prefix used for error message. */
605 static const char *register_prefix
= "%";
607 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
608 leave, push, and pop instructions so that gcc has the same stack
609 frame as in 32 bit mode. */
610 static char stackop_size
= '\0';
612 /* Non-zero to optimize code alignment. */
613 int optimize_align_code
= 1;
615 /* Non-zero to quieten some warnings. */
616 static int quiet_warnings
= 0;
619 static const char *cpu_arch_name
= NULL
;
620 static char *cpu_sub_arch_name
= NULL
;
622 /* CPU feature flags. */
623 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
625 /* If we have selected a cpu we are generating instructions for. */
626 static int cpu_arch_tune_set
= 0;
628 /* Cpu we are generating instructions for. */
629 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
631 /* CPU feature flags of cpu we are generating instructions for. */
632 static i386_cpu_flags cpu_arch_tune_flags
;
634 /* CPU instruction set architecture used. */
635 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
637 /* CPU feature flags of instruction set architecture used. */
638 i386_cpu_flags cpu_arch_isa_flags
;
640 /* If set, conditional jumps are not automatically promoted to handle
641 larger than a byte offset. */
642 static unsigned int no_cond_jump_promotion
= 0;
644 /* Encode SSE instructions with VEX prefix. */
645 static unsigned int sse2avx
;
647 /* Encode scalar AVX instructions with specific vector length. */
654 /* Encode scalar EVEX LIG instructions with specific vector length. */
662 /* Encode EVEX WIG instructions with specific evex.w. */
669 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
670 static enum rc_type evexrcig
= rne
;
672 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
673 static symbolS
*GOT_symbol
;
675 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
676 unsigned int x86_dwarf2_return_column
;
678 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
679 int x86_cie_data_alignment
;
681 /* Interface to relax_segment.
682 There are 3 major relax states for 386 jump insns because the
683 different types of jumps add different sizes to frags when we're
684 figuring out what sort of jump to choose to reach a given label. */
687 #define UNCOND_JUMP 0
689 #define COND_JUMP86 2
694 #define SMALL16 (SMALL | CODE16)
696 #define BIG16 (BIG | CODE16)
700 #define INLINE __inline__
706 #define ENCODE_RELAX_STATE(type, size) \
707 ((relax_substateT) (((type) << 2) | (size)))
708 #define TYPE_FROM_RELAX_STATE(s) \
710 #define DISP_SIZE_FROM_RELAX_STATE(s) \
711 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
713 /* This table is used by relax_frag to promote short jumps to long
714 ones where necessary. SMALL (short) jumps may be promoted to BIG
715 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
716 don't allow a short jump in a 32 bit code segment to be promoted to
717 a 16 bit offset jump because it's slower (requires data size
718 prefix), and doesn't work, unless the destination is in the bottom
719 64k of the code segment (The top 16 bits of eip are zeroed). */
721 const relax_typeS md_relax_table
[] =
724 1) most positive reach of this state,
725 2) most negative reach of this state,
726 3) how many bytes this mode will have in the variable part of the frag
727 4) which index into the table to try if we can't fit into this one. */
729 /* UNCOND_JUMP states. */
730 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
731 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
732 /* dword jmp adds 4 bytes to frag:
733 0 extra opcode bytes, 4 displacement bytes. */
735 /* word jmp adds 2 byte2 to frag:
736 0 extra opcode bytes, 2 displacement bytes. */
739 /* COND_JUMP states. */
740 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
742 /* dword conditionals adds 5 bytes to frag:
743 1 extra opcode byte, 4 displacement bytes. */
745 /* word conditionals add 3 bytes to frag:
746 1 extra opcode byte, 2 displacement bytes. */
749 /* COND_JUMP86 states. */
750 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
752 /* dword conditionals adds 5 bytes to frag:
753 1 extra opcode byte, 4 displacement bytes. */
755 /* word conditionals add 4 bytes to frag:
756 1 displacement byte and a 3 byte long branch insn. */
760 static const arch_entry cpu_arch
[] =
762 /* Do not replace the first two entries - i386_target_format()
763 relies on them being there in this order. */
764 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
765 CPU_GENERIC32_FLAGS
, 0 },
766 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
767 CPU_GENERIC64_FLAGS
, 0 },
768 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
770 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
772 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
774 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
776 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
778 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
780 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
782 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
784 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
785 CPU_PENTIUMPRO_FLAGS
, 0 },
786 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
788 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
790 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
792 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
794 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
795 CPU_NOCONA_FLAGS
, 0 },
796 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
798 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
800 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
801 CPU_CORE2_FLAGS
, 1 },
802 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
803 CPU_CORE2_FLAGS
, 0 },
804 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
805 CPU_COREI7_FLAGS
, 0 },
806 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
808 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
810 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
811 CPU_IAMCU_FLAGS
, 0 },
812 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
814 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
816 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
817 CPU_ATHLON_FLAGS
, 0 },
818 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
820 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
822 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
824 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
825 CPU_AMDFAM10_FLAGS
, 0 },
826 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
827 CPU_BDVER1_FLAGS
, 0 },
828 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
829 CPU_BDVER2_FLAGS
, 0 },
830 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
831 CPU_BDVER3_FLAGS
, 0 },
832 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
833 CPU_BDVER4_FLAGS
, 0 },
834 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
835 CPU_ZNVER1_FLAGS
, 0 },
836 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
837 CPU_BTVER1_FLAGS
, 0 },
838 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
839 CPU_BTVER2_FLAGS
, 0 },
840 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
842 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
844 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
846 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
848 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
850 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
852 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
854 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
856 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
857 CPU_SSSE3_FLAGS
, 0 },
858 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
859 CPU_SSE4_1_FLAGS
, 0 },
860 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
861 CPU_SSE4_2_FLAGS
, 0 },
862 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
863 CPU_SSE4_2_FLAGS
, 0 },
864 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
866 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
868 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
869 CPU_AVX512F_FLAGS
, 0 },
870 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
871 CPU_AVX512CD_FLAGS
, 0 },
872 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
873 CPU_AVX512ER_FLAGS
, 0 },
874 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
875 CPU_AVX512PF_FLAGS
, 0 },
876 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
877 CPU_AVX512DQ_FLAGS
, 0 },
878 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
879 CPU_AVX512BW_FLAGS
, 0 },
880 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
881 CPU_AVX512VL_FLAGS
, 0 },
882 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
884 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
885 CPU_VMFUNC_FLAGS
, 0 },
886 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
888 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
889 CPU_XSAVE_FLAGS
, 0 },
890 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
891 CPU_XSAVEOPT_FLAGS
, 0 },
892 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
893 CPU_XSAVEC_FLAGS
, 0 },
894 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
895 CPU_XSAVES_FLAGS
, 0 },
896 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
898 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
899 CPU_PCLMUL_FLAGS
, 0 },
900 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
901 CPU_PCLMUL_FLAGS
, 1 },
902 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
903 CPU_FSGSBASE_FLAGS
, 0 },
904 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
905 CPU_RDRND_FLAGS
, 0 },
906 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
908 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
910 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
912 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
914 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
916 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
918 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
919 CPU_MOVBE_FLAGS
, 0 },
920 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
922 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
924 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
925 CPU_LZCNT_FLAGS
, 0 },
926 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
928 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
930 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
931 CPU_INVPCID_FLAGS
, 0 },
932 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
933 CPU_CLFLUSH_FLAGS
, 0 },
934 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
936 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
937 CPU_SYSCALL_FLAGS
, 0 },
938 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
939 CPU_RDTSCP_FLAGS
, 0 },
940 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
941 CPU_3DNOW_FLAGS
, 0 },
942 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
943 CPU_3DNOWA_FLAGS
, 0 },
944 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
945 CPU_PADLOCK_FLAGS
, 0 },
946 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
948 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
950 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
951 CPU_SSE4A_FLAGS
, 0 },
952 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
954 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
956 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
958 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
960 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
961 CPU_RDSEED_FLAGS
, 0 },
962 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
963 CPU_PRFCHW_FLAGS
, 0 },
964 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
966 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
968 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
970 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
971 CPU_CLFLUSHOPT_FLAGS
, 0 },
972 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
973 CPU_PREFETCHWT1_FLAGS
, 0 },
974 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
976 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
978 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
979 CPU_AVX512IFMA_FLAGS
, 0 },
980 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
981 CPU_AVX512VBMI_FLAGS
, 0 },
982 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
983 CPU_AVX512_4FMAPS_FLAGS
, 0 },
984 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
985 CPU_AVX512_4VNNIW_FLAGS
, 0 },
986 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
987 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
988 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
989 CPU_CLZERO_FLAGS
, 0 },
990 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
991 CPU_MWAITX_FLAGS
, 0 },
992 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
993 CPU_OSPKE_FLAGS
, 0 },
994 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
995 CPU_RDPID_FLAGS
, 0 },
996 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
997 CPU_PTWRITE_FLAGS
, 0 },
998 { STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN
,
1002 static const noarch_entry cpu_noarch
[] =
1004 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1005 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1006 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1007 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1008 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1009 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1010 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1011 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1012 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1013 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1014 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1015 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1016 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1017 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1018 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1019 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1020 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1021 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1022 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1023 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1024 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1025 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1026 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1027 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1028 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1029 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1033 /* Like s_lcomm_internal in gas/read.c but the alignment string
1034 is allowed to be optional. */
1037 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1044 && *input_line_pointer
== ',')
1046 align
= parse_align (needs_align
- 1);
1048 if (align
== (addressT
) -1)
1063 bss_alloc (symbolP
, size
, align
);
1068 pe_lcomm (int needs_align
)
1070 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1074 const pseudo_typeS md_pseudo_table
[] =
1076 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1077 {"align", s_align_bytes
, 0},
1079 {"align", s_align_ptwo
, 0},
1081 {"arch", set_cpu_arch
, 0},
1085 {"lcomm", pe_lcomm
, 1},
1087 {"ffloat", float_cons
, 'f'},
1088 {"dfloat", float_cons
, 'd'},
1089 {"tfloat", float_cons
, 'x'},
1091 {"slong", signed_cons
, 4},
1092 {"noopt", s_ignore
, 0},
1093 {"optim", s_ignore
, 0},
1094 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1095 {"code16", set_code_flag
, CODE_16BIT
},
1096 {"code32", set_code_flag
, CODE_32BIT
},
1097 {"code64", set_code_flag
, CODE_64BIT
},
1098 {"intel_syntax", set_intel_syntax
, 1},
1099 {"att_syntax", set_intel_syntax
, 0},
1100 {"intel_mnemonic", set_intel_mnemonic
, 1},
1101 {"att_mnemonic", set_intel_mnemonic
, 0},
1102 {"allow_index_reg", set_allow_index_reg
, 1},
1103 {"disallow_index_reg", set_allow_index_reg
, 0},
1104 {"sse_check", set_check
, 0},
1105 {"operand_check", set_check
, 1},
1106 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1107 {"largecomm", handle_large_common
, 0},
1109 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1110 {"loc", dwarf2_directive_loc
, 0},
1111 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1114 {"secrel32", pe_directive_secrel
, 0},
1119 /* For interface with expression (). */
1120 extern char *input_line_pointer
;
1122 /* Hash table for instruction mnemonic lookup. */
1123 static struct hash_control
*op_hash
;
1125 /* Hash table for register lookup. */
1126 static struct hash_control
*reg_hash
;
1129 i386_align_code (fragS
*fragP
, int count
)
1131 /* Various efficient no-op patterns for aligning code labels.
1132 Note: Don't try to assemble the instructions in the comments.
1133 0L and 0w are not legal. */
1134 static const unsigned char f32_1
[] =
1136 static const unsigned char f32_2
[] =
1137 {0x66,0x90}; /* xchg %ax,%ax */
1138 static const unsigned char f32_3
[] =
1139 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1140 static const unsigned char f32_4
[] =
1141 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1142 static const unsigned char f32_5
[] =
1144 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1145 static const unsigned char f32_6
[] =
1146 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1147 static const unsigned char f32_7
[] =
1148 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1149 static const unsigned char f32_8
[] =
1151 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1152 static const unsigned char f32_9
[] =
1153 {0x89,0xf6, /* movl %esi,%esi */
1154 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1155 static const unsigned char f32_10
[] =
1156 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1157 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1158 static const unsigned char f32_11
[] =
1159 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1160 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1161 static const unsigned char f32_12
[] =
1162 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1163 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1164 static const unsigned char f32_13
[] =
1165 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1166 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1167 static const unsigned char f32_14
[] =
1168 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1169 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1170 static const unsigned char f16_3
[] =
1171 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1172 static const unsigned char f16_4
[] =
1173 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1174 static const unsigned char f16_5
[] =
1176 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1177 static const unsigned char f16_6
[] =
1178 {0x89,0xf6, /* mov %si,%si */
1179 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1180 static const unsigned char f16_7
[] =
1181 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1182 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1183 static const unsigned char f16_8
[] =
1184 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1185 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1186 static const unsigned char jump_31
[] =
1187 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1188 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1189 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1190 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1191 static const unsigned char *const f32_patt
[] = {
1192 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1193 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1195 static const unsigned char *const f16_patt
[] = {
1196 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1198 /* nopl (%[re]ax) */
1199 static const unsigned char alt_3
[] =
1201 /* nopl 0(%[re]ax) */
1202 static const unsigned char alt_4
[] =
1203 {0x0f,0x1f,0x40,0x00};
1204 /* nopl 0(%[re]ax,%[re]ax,1) */
1205 static const unsigned char alt_5
[] =
1206 {0x0f,0x1f,0x44,0x00,0x00};
1207 /* nopw 0(%[re]ax,%[re]ax,1) */
1208 static const unsigned char alt_6
[] =
1209 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1210 /* nopl 0L(%[re]ax) */
1211 static const unsigned char alt_7
[] =
1212 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1213 /* nopl 0L(%[re]ax,%[re]ax,1) */
1214 static const unsigned char alt_8
[] =
1215 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1216 /* nopw 0L(%[re]ax,%[re]ax,1) */
1217 static const unsigned char alt_9
[] =
1218 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1219 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1220 static const unsigned char alt_10
[] =
1221 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1222 static const unsigned char *const alt_patt
[] = {
1223 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1227 /* Only align for at least a positive non-zero boundary. */
1228 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1231 /* We need to decide which NOP sequence to use for 32bit and
1232 64bit. When -mtune= is used:
1234 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1235 PROCESSOR_GENERIC32, f32_patt will be used.
1236 2. For the rest, alt_patt will be used.
1238 When -mtune= isn't used, alt_patt will be used if
1239 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1242 When -march= or .arch is used, we can't use anything beyond
1243 cpu_arch_isa_flags. */
1245 if (flag_code
== CODE_16BIT
)
1249 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1251 /* Adjust jump offset. */
1252 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1255 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1256 f16_patt
[count
- 1], count
);
1260 const unsigned char *const *patt
= NULL
;
1262 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1264 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1265 switch (cpu_arch_tune
)
1267 case PROCESSOR_UNKNOWN
:
1268 /* We use cpu_arch_isa_flags to check if we SHOULD
1269 optimize with nops. */
1270 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1275 case PROCESSOR_PENTIUM4
:
1276 case PROCESSOR_NOCONA
:
1277 case PROCESSOR_CORE
:
1278 case PROCESSOR_CORE2
:
1279 case PROCESSOR_COREI7
:
1280 case PROCESSOR_L1OM
:
1281 case PROCESSOR_K1OM
:
1282 case PROCESSOR_GENERIC64
:
1284 case PROCESSOR_ATHLON
:
1286 case PROCESSOR_AMDFAM10
:
1288 case PROCESSOR_ZNVER
:
1292 case PROCESSOR_I386
:
1293 case PROCESSOR_I486
:
1294 case PROCESSOR_PENTIUM
:
1295 case PROCESSOR_PENTIUMPRO
:
1296 case PROCESSOR_IAMCU
:
1297 case PROCESSOR_GENERIC32
:
1304 switch (fragP
->tc_frag_data
.tune
)
1306 case PROCESSOR_UNKNOWN
:
1307 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1308 PROCESSOR_UNKNOWN. */
1312 case PROCESSOR_I386
:
1313 case PROCESSOR_I486
:
1314 case PROCESSOR_PENTIUM
:
1315 case PROCESSOR_IAMCU
:
1317 case PROCESSOR_ATHLON
:
1319 case PROCESSOR_AMDFAM10
:
1321 case PROCESSOR_ZNVER
:
1323 case PROCESSOR_GENERIC32
:
1324 /* We use cpu_arch_isa_flags to check if we CAN optimize
1326 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1331 case PROCESSOR_PENTIUMPRO
:
1332 case PROCESSOR_PENTIUM4
:
1333 case PROCESSOR_NOCONA
:
1334 case PROCESSOR_CORE
:
1335 case PROCESSOR_CORE2
:
1336 case PROCESSOR_COREI7
:
1337 case PROCESSOR_L1OM
:
1338 case PROCESSOR_K1OM
:
1339 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1344 case PROCESSOR_GENERIC64
:
1350 if (patt
== f32_patt
)
1352 /* If the padding is less than 15 bytes, we use the normal
1353 ones. Otherwise, we use a jump instruction and adjust
1357 /* For 64bit, the limit is 3 bytes. */
1358 if (flag_code
== CODE_64BIT
1359 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1364 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1365 patt
[count
- 1], count
);
1368 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1370 /* Adjust jump offset. */
1371 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1376 /* Maximum length of an instruction is 10 byte. If the
1377 padding is greater than 10 bytes and we don't use jump,
1378 we have to break it into smaller pieces. */
1379 int padding
= count
;
1380 while (padding
> 10)
1383 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1388 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1389 patt
[padding
- 1], padding
);
1392 fragP
->fr_var
= count
;
1396 operand_type_all_zero (const union i386_operand_type
*x
)
1398 switch (ARRAY_SIZE(x
->array
))
1409 return !x
->array
[0];
1416 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1418 switch (ARRAY_SIZE(x
->array
))
1436 operand_type_equal (const union i386_operand_type
*x
,
1437 const union i386_operand_type
*y
)
1439 switch (ARRAY_SIZE(x
->array
))
1442 if (x
->array
[2] != y
->array
[2])
1446 if (x
->array
[1] != y
->array
[1])
1450 return x
->array
[0] == y
->array
[0];
1458 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1460 switch (ARRAY_SIZE(x
->array
))
1471 return !x
->array
[0];
1478 cpu_flags_equal (const union i386_cpu_flags
*x
,
1479 const union i386_cpu_flags
*y
)
1481 switch (ARRAY_SIZE(x
->array
))
1484 if (x
->array
[2] != y
->array
[2])
1488 if (x
->array
[1] != y
->array
[1])
1492 return x
->array
[0] == y
->array
[0];
1500 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1502 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1503 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1506 static INLINE i386_cpu_flags
1507 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1509 switch (ARRAY_SIZE (x
.array
))
1512 x
.array
[2] &= y
.array
[2];
1515 x
.array
[1] &= y
.array
[1];
1518 x
.array
[0] &= y
.array
[0];
1526 static INLINE i386_cpu_flags
1527 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1529 switch (ARRAY_SIZE (x
.array
))
1532 x
.array
[2] |= y
.array
[2];
1535 x
.array
[1] |= y
.array
[1];
1538 x
.array
[0] |= y
.array
[0];
1546 static INLINE i386_cpu_flags
1547 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1549 switch (ARRAY_SIZE (x
.array
))
1552 x
.array
[2] &= ~y
.array
[2];
1555 x
.array
[1] &= ~y
.array
[1];
1558 x
.array
[0] &= ~y
.array
[0];
1566 #define CPU_FLAGS_ARCH_MATCH 0x1
1567 #define CPU_FLAGS_64BIT_MATCH 0x2
1568 #define CPU_FLAGS_AES_MATCH 0x4
1569 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1570 #define CPU_FLAGS_AVX_MATCH 0x10
1572 #define CPU_FLAGS_32BIT_MATCH \
1573 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1574 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1575 #define CPU_FLAGS_PERFECT_MATCH \
1576 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1578 /* Return CPU flags match bits. */
1581 cpu_flags_match (const insn_template
*t
)
1583 i386_cpu_flags x
= t
->cpu_flags
;
1584 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1586 x
.bitfield
.cpu64
= 0;
1587 x
.bitfield
.cpuno64
= 0;
1589 if (cpu_flags_all_zero (&x
))
1591 /* This instruction is available on all archs. */
1592 match
|= CPU_FLAGS_32BIT_MATCH
;
1596 /* This instruction is available only on some archs. */
1597 i386_cpu_flags cpu
= cpu_arch_flags
;
1599 cpu
= cpu_flags_and (x
, cpu
);
1600 if (!cpu_flags_all_zero (&cpu
))
1602 if (x
.bitfield
.cpuavx
)
1604 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1605 if (cpu
.bitfield
.cpuavx
)
1607 /* Check SSE2AVX. */
1608 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1610 match
|= (CPU_FLAGS_ARCH_MATCH
1611 | CPU_FLAGS_AVX_MATCH
);
1613 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1614 match
|= CPU_FLAGS_AES_MATCH
;
1616 if (!x
.bitfield
.cpupclmul
1617 || cpu
.bitfield
.cpupclmul
)
1618 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1622 match
|= CPU_FLAGS_ARCH_MATCH
;
1624 else if (x
.bitfield
.cpuavx512vl
)
1626 /* Match AVX512VL. */
1627 if (cpu
.bitfield
.cpuavx512vl
)
1629 /* Need another match. */
1630 cpu
.bitfield
.cpuavx512vl
= 0;
1631 if (!cpu_flags_all_zero (&cpu
))
1632 match
|= CPU_FLAGS_32BIT_MATCH
;
1634 match
|= CPU_FLAGS_ARCH_MATCH
;
1637 match
|= CPU_FLAGS_ARCH_MATCH
;
1640 match
|= CPU_FLAGS_32BIT_MATCH
;
1646 static INLINE i386_operand_type
1647 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1649 switch (ARRAY_SIZE (x
.array
))
1652 x
.array
[2] &= y
.array
[2];
1655 x
.array
[1] &= y
.array
[1];
1658 x
.array
[0] &= y
.array
[0];
1666 static INLINE i386_operand_type
1667 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1669 switch (ARRAY_SIZE (x
.array
))
1672 x
.array
[2] |= y
.array
[2];
1675 x
.array
[1] |= y
.array
[1];
1678 x
.array
[0] |= y
.array
[0];
1686 static INLINE i386_operand_type
1687 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1689 switch (ARRAY_SIZE (x
.array
))
1692 x
.array
[2] ^= y
.array
[2];
1695 x
.array
[1] ^= y
.array
[1];
1698 x
.array
[0] ^= y
.array
[0];
1706 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1707 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1708 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1709 static const i386_operand_type inoutportreg
1710 = OPERAND_TYPE_INOUTPORTREG
;
1711 static const i386_operand_type reg16_inoutportreg
1712 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1713 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1714 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1715 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1716 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1717 static const i386_operand_type anydisp
1718 = OPERAND_TYPE_ANYDISP
;
1719 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1720 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1721 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1722 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1723 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1724 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1725 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1726 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1727 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1728 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1729 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1730 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1731 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1732 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1743 operand_type_check (i386_operand_type t
, enum operand_type c
)
1748 return (t
.bitfield
.reg8
1751 || t
.bitfield
.reg64
);
1754 return (t
.bitfield
.imm8
1758 || t
.bitfield
.imm32s
1759 || t
.bitfield
.imm64
);
1762 return (t
.bitfield
.disp8
1763 || t
.bitfield
.disp16
1764 || t
.bitfield
.disp32
1765 || t
.bitfield
.disp32s
1766 || t
.bitfield
.disp64
);
1769 return (t
.bitfield
.disp8
1770 || t
.bitfield
.disp16
1771 || t
.bitfield
.disp32
1772 || t
.bitfield
.disp32s
1773 || t
.bitfield
.disp64
1774 || t
.bitfield
.baseindex
);
1783 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1784 operand J for instruction template T. */
1787 match_reg_size (const insn_template
*t
, unsigned int j
)
1789 return !((i
.types
[j
].bitfield
.byte
1790 && !t
->operand_types
[j
].bitfield
.byte
)
1791 || (i
.types
[j
].bitfield
.word
1792 && !t
->operand_types
[j
].bitfield
.word
)
1793 || (i
.types
[j
].bitfield
.dword
1794 && !t
->operand_types
[j
].bitfield
.dword
)
1795 || (i
.types
[j
].bitfield
.qword
1796 && !t
->operand_types
[j
].bitfield
.qword
));
1799 /* Return 1 if there is no conflict in any size on operand J for
1800 instruction template T. */
1803 match_mem_size (const insn_template
*t
, unsigned int j
)
1805 return (match_reg_size (t
, j
)
1806 && !((i
.types
[j
].bitfield
.unspecified
1808 && !t
->operand_types
[j
].bitfield
.unspecified
)
1809 || (i
.types
[j
].bitfield
.fword
1810 && !t
->operand_types
[j
].bitfield
.fword
)
1811 || (i
.types
[j
].bitfield
.tbyte
1812 && !t
->operand_types
[j
].bitfield
.tbyte
)
1813 || (i
.types
[j
].bitfield
.xmmword
1814 && !t
->operand_types
[j
].bitfield
.xmmword
)
1815 || (i
.types
[j
].bitfield
.ymmword
1816 && !t
->operand_types
[j
].bitfield
.ymmword
)
1817 || (i
.types
[j
].bitfield
.zmmword
1818 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1821 /* Return 1 if there is no size conflict on any operands for
1822 instruction template T. */
1825 operand_size_match (const insn_template
*t
)
1830 /* Don't check jump instructions. */
1831 if (t
->opcode_modifier
.jump
1832 || t
->opcode_modifier
.jumpbyte
1833 || t
->opcode_modifier
.jumpdword
1834 || t
->opcode_modifier
.jumpintersegment
)
1837 /* Check memory and accumulator operand size. */
1838 for (j
= 0; j
< i
.operands
; j
++)
1840 if (t
->operand_types
[j
].bitfield
.anysize
)
1843 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1849 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1858 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1861 i
.error
= operand_size_mismatch
;
1865 /* Check reverse. */
1866 gas_assert (i
.operands
== 2);
1869 for (j
= 0; j
< 2; j
++)
1871 if (t
->operand_types
[j
].bitfield
.acc
1872 && !match_reg_size (t
, j
? 0 : 1))
1875 if (i
.types
[j
].bitfield
.mem
1876 && !match_mem_size (t
, j
? 0 : 1))
1884 operand_type_match (i386_operand_type overlap
,
1885 i386_operand_type given
)
1887 i386_operand_type temp
= overlap
;
1889 temp
.bitfield
.jumpabsolute
= 0;
1890 temp
.bitfield
.unspecified
= 0;
1891 temp
.bitfield
.byte
= 0;
1892 temp
.bitfield
.word
= 0;
1893 temp
.bitfield
.dword
= 0;
1894 temp
.bitfield
.fword
= 0;
1895 temp
.bitfield
.qword
= 0;
1896 temp
.bitfield
.tbyte
= 0;
1897 temp
.bitfield
.xmmword
= 0;
1898 temp
.bitfield
.ymmword
= 0;
1899 temp
.bitfield
.zmmword
= 0;
1900 if (operand_type_all_zero (&temp
))
1903 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1904 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1908 i
.error
= operand_type_mismatch
;
1912 /* If given types g0 and g1 are registers they must be of the same type
1913 unless the expected operand type register overlap is null.
1914 Note that Acc in a template matches every size of reg. */
1917 operand_type_register_match (i386_operand_type m0
,
1918 i386_operand_type g0
,
1919 i386_operand_type t0
,
1920 i386_operand_type m1
,
1921 i386_operand_type g1
,
1922 i386_operand_type t1
)
1924 if (!operand_type_check (g0
, reg
))
1927 if (!operand_type_check (g1
, reg
))
1930 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1931 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1932 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1933 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1936 if (m0
.bitfield
.acc
)
1938 t0
.bitfield
.reg8
= 1;
1939 t0
.bitfield
.reg16
= 1;
1940 t0
.bitfield
.reg32
= 1;
1941 t0
.bitfield
.reg64
= 1;
1944 if (m1
.bitfield
.acc
)
1946 t1
.bitfield
.reg8
= 1;
1947 t1
.bitfield
.reg16
= 1;
1948 t1
.bitfield
.reg32
= 1;
1949 t1
.bitfield
.reg64
= 1;
1952 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1953 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1954 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1955 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1958 i
.error
= register_type_mismatch
;
1963 static INLINE
unsigned int
1964 register_number (const reg_entry
*r
)
1966 unsigned int nr
= r
->reg_num
;
1968 if (r
->reg_flags
& RegRex
)
1971 if (r
->reg_flags
& RegVRex
)
1977 static INLINE
unsigned int
1978 mode_from_disp_size (i386_operand_type t
)
1980 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1982 else if (t
.bitfield
.disp16
1983 || t
.bitfield
.disp32
1984 || t
.bitfield
.disp32s
)
1991 fits_in_signed_byte (addressT num
)
1993 return num
+ 0x80 <= 0xff;
1997 fits_in_unsigned_byte (addressT num
)
2003 fits_in_unsigned_word (addressT num
)
2005 return num
<= 0xffff;
2009 fits_in_signed_word (addressT num
)
2011 return num
+ 0x8000 <= 0xffff;
2015 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2020 return num
+ 0x80000000 <= 0xffffffff;
2022 } /* fits_in_signed_long() */
2025 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2030 return num
<= 0xffffffff;
2032 } /* fits_in_unsigned_long() */
2035 fits_in_vec_disp8 (offsetT num
)
2037 int shift
= i
.memshift
;
2043 mask
= (1 << shift
) - 1;
2045 /* Return 0 if NUM isn't properly aligned. */
2049 /* Check if NUM will fit in 8bit after shift. */
2050 return fits_in_signed_byte (num
>> shift
);
2054 fits_in_imm4 (offsetT num
)
2056 return (num
& 0xf) == num
;
2059 static i386_operand_type
2060 smallest_imm_type (offsetT num
)
2062 i386_operand_type t
;
2064 operand_type_set (&t
, 0);
2065 t
.bitfield
.imm64
= 1;
2067 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2069 /* This code is disabled on the 486 because all the Imm1 forms
2070 in the opcode table are slower on the i486. They're the
2071 versions with the implicitly specified single-position
2072 displacement, which has another syntax if you really want to
2074 t
.bitfield
.imm1
= 1;
2075 t
.bitfield
.imm8
= 1;
2076 t
.bitfield
.imm8s
= 1;
2077 t
.bitfield
.imm16
= 1;
2078 t
.bitfield
.imm32
= 1;
2079 t
.bitfield
.imm32s
= 1;
2081 else if (fits_in_signed_byte (num
))
2083 t
.bitfield
.imm8
= 1;
2084 t
.bitfield
.imm8s
= 1;
2085 t
.bitfield
.imm16
= 1;
2086 t
.bitfield
.imm32
= 1;
2087 t
.bitfield
.imm32s
= 1;
2089 else if (fits_in_unsigned_byte (num
))
2091 t
.bitfield
.imm8
= 1;
2092 t
.bitfield
.imm16
= 1;
2093 t
.bitfield
.imm32
= 1;
2094 t
.bitfield
.imm32s
= 1;
2096 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2098 t
.bitfield
.imm16
= 1;
2099 t
.bitfield
.imm32
= 1;
2100 t
.bitfield
.imm32s
= 1;
2102 else if (fits_in_signed_long (num
))
2104 t
.bitfield
.imm32
= 1;
2105 t
.bitfield
.imm32s
= 1;
2107 else if (fits_in_unsigned_long (num
))
2108 t
.bitfield
.imm32
= 1;
2114 offset_in_range (offsetT val
, int size
)
2120 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2121 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2122 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2124 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2130 /* If BFD64, sign extend val for 32bit address mode. */
2131 if (flag_code
!= CODE_64BIT
2132 || i
.prefix
[ADDR_PREFIX
])
2133 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2134 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2137 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2139 char buf1
[40], buf2
[40];
2141 sprint_value (buf1
, val
);
2142 sprint_value (buf2
, val
& mask
);
2143 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2158 a. PREFIX_EXIST if attempting to add a prefix where one from the
2159 same class already exists.
2160 b. PREFIX_LOCK if lock prefix is added.
2161 c. PREFIX_REP if rep/repne prefix is added.
2162 d. PREFIX_DS if ds prefix is added.
2163 e. PREFIX_OTHER if other prefix is added.
2166 static enum PREFIX_GROUP
2167 add_prefix (unsigned int prefix
)
2169 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2172 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2173 && flag_code
== CODE_64BIT
)
2175 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2176 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2177 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2188 case DS_PREFIX_OPCODE
:
2191 case CS_PREFIX_OPCODE
:
2192 case ES_PREFIX_OPCODE
:
2193 case FS_PREFIX_OPCODE
:
2194 case GS_PREFIX_OPCODE
:
2195 case SS_PREFIX_OPCODE
:
2199 case REPNE_PREFIX_OPCODE
:
2200 case REPE_PREFIX_OPCODE
:
2205 case LOCK_PREFIX_OPCODE
:
2214 case ADDR_PREFIX_OPCODE
:
2218 case DATA_PREFIX_OPCODE
:
2222 if (i
.prefix
[q
] != 0)
2230 i
.prefix
[q
] |= prefix
;
2233 as_bad (_("same type of prefix used twice"));
2239 update_code_flag (int value
, int check
)
2241 PRINTF_LIKE ((*as_error
));
2243 flag_code
= (enum flag_code
) value
;
2244 if (flag_code
== CODE_64BIT
)
2246 cpu_arch_flags
.bitfield
.cpu64
= 1;
2247 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2251 cpu_arch_flags
.bitfield
.cpu64
= 0;
2252 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2254 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2257 as_error
= as_fatal
;
2260 (*as_error
) (_("64bit mode not supported on `%s'."),
2261 cpu_arch_name
? cpu_arch_name
: default_arch
);
2263 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2266 as_error
= as_fatal
;
2269 (*as_error
) (_("32bit mode not supported on `%s'."),
2270 cpu_arch_name
? cpu_arch_name
: default_arch
);
2272 stackop_size
= '\0';
2276 set_code_flag (int value
)
2278 update_code_flag (value
, 0);
2282 set_16bit_gcc_code_flag (int new_code_flag
)
2284 flag_code
= (enum flag_code
) new_code_flag
;
2285 if (flag_code
!= CODE_16BIT
)
2287 cpu_arch_flags
.bitfield
.cpu64
= 0;
2288 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2289 stackop_size
= LONG_MNEM_SUFFIX
;
2293 set_intel_syntax (int syntax_flag
)
2295 /* Find out if register prefixing is specified. */
2296 int ask_naked_reg
= 0;
2299 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2302 int e
= get_symbol_name (&string
);
2304 if (strcmp (string
, "prefix") == 0)
2306 else if (strcmp (string
, "noprefix") == 0)
2309 as_bad (_("bad argument to syntax directive."));
2310 (void) restore_line_pointer (e
);
2312 demand_empty_rest_of_line ();
2314 intel_syntax
= syntax_flag
;
2316 if (ask_naked_reg
== 0)
2317 allow_naked_reg
= (intel_syntax
2318 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2320 allow_naked_reg
= (ask_naked_reg
< 0);
2322 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2324 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2325 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2326 register_prefix
= allow_naked_reg
? "" : "%";
2330 set_intel_mnemonic (int mnemonic_flag
)
2332 intel_mnemonic
= mnemonic_flag
;
2336 set_allow_index_reg (int flag
)
2338 allow_index_reg
= flag
;
2342 set_check (int what
)
2344 enum check_kind
*kind
;
2349 kind
= &operand_check
;
2360 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2363 int e
= get_symbol_name (&string
);
2365 if (strcmp (string
, "none") == 0)
2367 else if (strcmp (string
, "warning") == 0)
2368 *kind
= check_warning
;
2369 else if (strcmp (string
, "error") == 0)
2370 *kind
= check_error
;
2372 as_bad (_("bad argument to %s_check directive."), str
);
2373 (void) restore_line_pointer (e
);
2376 as_bad (_("missing argument for %s_check directive"), str
);
2378 demand_empty_rest_of_line ();
2382 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2383 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2385 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2386 static const char *arch
;
2388 /* Intel LIOM is only supported on ELF. */
2394 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2395 use default_arch. */
2396 arch
= cpu_arch_name
;
2398 arch
= default_arch
;
2401 /* If we are targeting Intel MCU, we must enable it. */
2402 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2403 || new_flag
.bitfield
.cpuiamcu
)
2406 /* If we are targeting Intel L1OM, we must enable it. */
2407 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2408 || new_flag
.bitfield
.cpul1om
)
2411 /* If we are targeting Intel K1OM, we must enable it. */
2412 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2413 || new_flag
.bitfield
.cpuk1om
)
2416 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2421 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2425 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2428 int e
= get_symbol_name (&string
);
2430 i386_cpu_flags flags
;
2432 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2434 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2436 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2440 cpu_arch_name
= cpu_arch
[j
].name
;
2441 cpu_sub_arch_name
= NULL
;
2442 cpu_arch_flags
= cpu_arch
[j
].flags
;
2443 if (flag_code
== CODE_64BIT
)
2445 cpu_arch_flags
.bitfield
.cpu64
= 1;
2446 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2450 cpu_arch_flags
.bitfield
.cpu64
= 0;
2451 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2453 cpu_arch_isa
= cpu_arch
[j
].type
;
2454 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2455 if (!cpu_arch_tune_set
)
2457 cpu_arch_tune
= cpu_arch_isa
;
2458 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2463 flags
= cpu_flags_or (cpu_arch_flags
,
2466 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2468 if (cpu_sub_arch_name
)
2470 char *name
= cpu_sub_arch_name
;
2471 cpu_sub_arch_name
= concat (name
,
2473 (const char *) NULL
);
2477 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2478 cpu_arch_flags
= flags
;
2479 cpu_arch_isa_flags
= flags
;
2481 (void) restore_line_pointer (e
);
2482 demand_empty_rest_of_line ();
2487 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2489 /* Disable an ISA extension. */
2490 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2491 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2493 flags
= cpu_flags_and_not (cpu_arch_flags
,
2494 cpu_noarch
[j
].flags
);
2495 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2497 if (cpu_sub_arch_name
)
2499 char *name
= cpu_sub_arch_name
;
2500 cpu_sub_arch_name
= concat (name
, string
,
2501 (const char *) NULL
);
2505 cpu_sub_arch_name
= xstrdup (string
);
2506 cpu_arch_flags
= flags
;
2507 cpu_arch_isa_flags
= flags
;
2509 (void) restore_line_pointer (e
);
2510 demand_empty_rest_of_line ();
2514 j
= ARRAY_SIZE (cpu_arch
);
2517 if (j
>= ARRAY_SIZE (cpu_arch
))
2518 as_bad (_("no such architecture: `%s'"), string
);
2520 *input_line_pointer
= e
;
2523 as_bad (_("missing cpu architecture"));
2525 no_cond_jump_promotion
= 0;
2526 if (*input_line_pointer
== ','
2527 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2532 ++input_line_pointer
;
2533 e
= get_symbol_name (&string
);
2535 if (strcmp (string
, "nojumps") == 0)
2536 no_cond_jump_promotion
= 1;
2537 else if (strcmp (string
, "jumps") == 0)
2540 as_bad (_("no such architecture modifier: `%s'"), string
);
2542 (void) restore_line_pointer (e
);
2545 demand_empty_rest_of_line ();
2548 enum bfd_architecture
2551 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2553 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2554 || flag_code
!= CODE_64BIT
)
2555 as_fatal (_("Intel L1OM is 64bit ELF only"));
2556 return bfd_arch_l1om
;
2558 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2560 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2561 || flag_code
!= CODE_64BIT
)
2562 as_fatal (_("Intel K1OM is 64bit ELF only"));
2563 return bfd_arch_k1om
;
2565 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2567 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2568 || flag_code
== CODE_64BIT
)
2569 as_fatal (_("Intel MCU is 32bit ELF only"));
2570 return bfd_arch_iamcu
;
2573 return bfd_arch_i386
;
2579 if (!strncmp (default_arch
, "x86_64", 6))
2581 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2583 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2584 || default_arch
[6] != '\0')
2585 as_fatal (_("Intel L1OM is 64bit ELF only"));
2586 return bfd_mach_l1om
;
2588 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2590 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2591 || default_arch
[6] != '\0')
2592 as_fatal (_("Intel K1OM is 64bit ELF only"));
2593 return bfd_mach_k1om
;
2595 else if (default_arch
[6] == '\0')
2596 return bfd_mach_x86_64
;
2598 return bfd_mach_x64_32
;
2600 else if (!strcmp (default_arch
, "i386")
2601 || !strcmp (default_arch
, "iamcu"))
2603 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2605 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2606 as_fatal (_("Intel MCU is 32bit ELF only"));
2607 return bfd_mach_i386_iamcu
;
2610 return bfd_mach_i386_i386
;
2613 as_fatal (_("unknown architecture"));
2619 const char *hash_err
;
2621 /* Support pseudo prefixes like {disp32}. */
2622 lex_type
['{'] = LEX_BEGIN_NAME
;
2624 /* Initialize op_hash hash table. */
2625 op_hash
= hash_new ();
2628 const insn_template
*optab
;
2629 templates
*core_optab
;
2631 /* Setup for loop. */
2633 core_optab
= XNEW (templates
);
2634 core_optab
->start
= optab
;
2639 if (optab
->name
== NULL
2640 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2642 /* different name --> ship out current template list;
2643 add to hash table; & begin anew. */
2644 core_optab
->end
= optab
;
2645 hash_err
= hash_insert (op_hash
,
2647 (void *) core_optab
);
2650 as_fatal (_("can't hash %s: %s"),
2654 if (optab
->name
== NULL
)
2656 core_optab
= XNEW (templates
);
2657 core_optab
->start
= optab
;
2662 /* Initialize reg_hash hash table. */
2663 reg_hash
= hash_new ();
2665 const reg_entry
*regtab
;
2666 unsigned int regtab_size
= i386_regtab_size
;
2668 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2670 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2672 as_fatal (_("can't hash %s: %s"),
2678 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2683 for (c
= 0; c
< 256; c
++)
2688 mnemonic_chars
[c
] = c
;
2689 register_chars
[c
] = c
;
2690 operand_chars
[c
] = c
;
2692 else if (ISLOWER (c
))
2694 mnemonic_chars
[c
] = c
;
2695 register_chars
[c
] = c
;
2696 operand_chars
[c
] = c
;
2698 else if (ISUPPER (c
))
2700 mnemonic_chars
[c
] = TOLOWER (c
);
2701 register_chars
[c
] = mnemonic_chars
[c
];
2702 operand_chars
[c
] = c
;
2704 else if (c
== '{' || c
== '}')
2706 mnemonic_chars
[c
] = c
;
2707 operand_chars
[c
] = c
;
2710 if (ISALPHA (c
) || ISDIGIT (c
))
2711 identifier_chars
[c
] = c
;
2714 identifier_chars
[c
] = c
;
2715 operand_chars
[c
] = c
;
2720 identifier_chars
['@'] = '@';
2723 identifier_chars
['?'] = '?';
2724 operand_chars
['?'] = '?';
2726 digit_chars
['-'] = '-';
2727 mnemonic_chars
['_'] = '_';
2728 mnemonic_chars
['-'] = '-';
2729 mnemonic_chars
['.'] = '.';
2730 identifier_chars
['_'] = '_';
2731 identifier_chars
['.'] = '.';
2733 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2734 operand_chars
[(unsigned char) *p
] = *p
;
2737 if (flag_code
== CODE_64BIT
)
2739 #if defined (OBJ_COFF) && defined (TE_PE)
2740 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2743 x86_dwarf2_return_column
= 16;
2745 x86_cie_data_alignment
= -8;
2749 x86_dwarf2_return_column
= 8;
2750 x86_cie_data_alignment
= -4;
2755 i386_print_statistics (FILE *file
)
2757 hash_print_statistics (file
, "i386 opcode", op_hash
);
2758 hash_print_statistics (file
, "i386 register", reg_hash
);
2763 /* Debugging routines for md_assemble. */
2764 static void pte (insn_template
*);
2765 static void pt (i386_operand_type
);
2766 static void pe (expressionS
*);
2767 static void ps (symbolS
*);
2770 pi (char *line
, i386_insn
*x
)
2774 fprintf (stdout
, "%s: template ", line
);
2776 fprintf (stdout
, " address: base %s index %s scale %x\n",
2777 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2778 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2779 x
->log2_scale_factor
);
2780 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2781 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2782 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2783 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2784 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2785 (x
->rex
& REX_W
) != 0,
2786 (x
->rex
& REX_R
) != 0,
2787 (x
->rex
& REX_X
) != 0,
2788 (x
->rex
& REX_B
) != 0);
2789 for (j
= 0; j
< x
->operands
; j
++)
2791 fprintf (stdout
, " #%d: ", j
+ 1);
2793 fprintf (stdout
, "\n");
2794 if (x
->types
[j
].bitfield
.reg8
2795 || x
->types
[j
].bitfield
.reg16
2796 || x
->types
[j
].bitfield
.reg32
2797 || x
->types
[j
].bitfield
.reg64
2798 || x
->types
[j
].bitfield
.regmmx
2799 || x
->types
[j
].bitfield
.regxmm
2800 || x
->types
[j
].bitfield
.regymm
2801 || x
->types
[j
].bitfield
.regzmm
2802 || x
->types
[j
].bitfield
.sreg2
2803 || x
->types
[j
].bitfield
.sreg3
2804 || x
->types
[j
].bitfield
.control
2805 || x
->types
[j
].bitfield
.debug
2806 || x
->types
[j
].bitfield
.test
)
2807 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2808 if (operand_type_check (x
->types
[j
], imm
))
2810 if (operand_type_check (x
->types
[j
], disp
))
2811 pe (x
->op
[j
].disps
);
2816 pte (insn_template
*t
)
2819 fprintf (stdout
, " %d operands ", t
->operands
);
2820 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2821 if (t
->extension_opcode
!= None
)
2822 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2823 if (t
->opcode_modifier
.d
)
2824 fprintf (stdout
, "D");
2825 if (t
->opcode_modifier
.w
)
2826 fprintf (stdout
, "W");
2827 fprintf (stdout
, "\n");
2828 for (j
= 0; j
< t
->operands
; j
++)
2830 fprintf (stdout
, " #%d type ", j
+ 1);
2831 pt (t
->operand_types
[j
]);
2832 fprintf (stdout
, "\n");
2839 fprintf (stdout
, " operation %d\n", e
->X_op
);
2840 fprintf (stdout
, " add_number %ld (%lx)\n",
2841 (long) e
->X_add_number
, (long) e
->X_add_number
);
2842 if (e
->X_add_symbol
)
2844 fprintf (stdout
, " add_symbol ");
2845 ps (e
->X_add_symbol
);
2846 fprintf (stdout
, "\n");
2850 fprintf (stdout
, " op_symbol ");
2851 ps (e
->X_op_symbol
);
2852 fprintf (stdout
, "\n");
2859 fprintf (stdout
, "%s type %s%s",
2861 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2862 segment_name (S_GET_SEGMENT (s
)));
2865 static struct type_name
2867 i386_operand_type mask
;
2870 const type_names
[] =
2872 { OPERAND_TYPE_REG8
, "r8" },
2873 { OPERAND_TYPE_REG16
, "r16" },
2874 { OPERAND_TYPE_REG32
, "r32" },
2875 { OPERAND_TYPE_REG64
, "r64" },
2876 { OPERAND_TYPE_IMM8
, "i8" },
2877 { OPERAND_TYPE_IMM8
, "i8s" },
2878 { OPERAND_TYPE_IMM16
, "i16" },
2879 { OPERAND_TYPE_IMM32
, "i32" },
2880 { OPERAND_TYPE_IMM32S
, "i32s" },
2881 { OPERAND_TYPE_IMM64
, "i64" },
2882 { OPERAND_TYPE_IMM1
, "i1" },
2883 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2884 { OPERAND_TYPE_DISP8
, "d8" },
2885 { OPERAND_TYPE_DISP16
, "d16" },
2886 { OPERAND_TYPE_DISP32
, "d32" },
2887 { OPERAND_TYPE_DISP32S
, "d32s" },
2888 { OPERAND_TYPE_DISP64
, "d64" },
2889 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2890 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2891 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2892 { OPERAND_TYPE_CONTROL
, "control reg" },
2893 { OPERAND_TYPE_TEST
, "test reg" },
2894 { OPERAND_TYPE_DEBUG
, "debug reg" },
2895 { OPERAND_TYPE_FLOATREG
, "FReg" },
2896 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2897 { OPERAND_TYPE_SREG2
, "SReg2" },
2898 { OPERAND_TYPE_SREG3
, "SReg3" },
2899 { OPERAND_TYPE_ACC
, "Acc" },
2900 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2901 { OPERAND_TYPE_REGMMX
, "rMMX" },
2902 { OPERAND_TYPE_REGXMM
, "rXMM" },
2903 { OPERAND_TYPE_REGYMM
, "rYMM" },
2904 { OPERAND_TYPE_REGZMM
, "rZMM" },
2905 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2906 { OPERAND_TYPE_ESSEG
, "es" },
2910 pt (i386_operand_type t
)
2913 i386_operand_type a
;
2915 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2917 a
= operand_type_and (t
, type_names
[j
].mask
);
2918 if (!operand_type_all_zero (&a
))
2919 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2924 #endif /* DEBUG386 */
2926 static bfd_reloc_code_real_type
2927 reloc (unsigned int size
,
2930 bfd_reloc_code_real_type other
)
2932 if (other
!= NO_RELOC
)
2934 reloc_howto_type
*rel
;
2939 case BFD_RELOC_X86_64_GOT32
:
2940 return BFD_RELOC_X86_64_GOT64
;
2942 case BFD_RELOC_X86_64_GOTPLT64
:
2943 return BFD_RELOC_X86_64_GOTPLT64
;
2945 case BFD_RELOC_X86_64_PLTOFF64
:
2946 return BFD_RELOC_X86_64_PLTOFF64
;
2948 case BFD_RELOC_X86_64_GOTPC32
:
2949 other
= BFD_RELOC_X86_64_GOTPC64
;
2951 case BFD_RELOC_X86_64_GOTPCREL
:
2952 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2954 case BFD_RELOC_X86_64_TPOFF32
:
2955 other
= BFD_RELOC_X86_64_TPOFF64
;
2957 case BFD_RELOC_X86_64_DTPOFF32
:
2958 other
= BFD_RELOC_X86_64_DTPOFF64
;
2964 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2965 if (other
== BFD_RELOC_SIZE32
)
2968 other
= BFD_RELOC_SIZE64
;
2971 as_bad (_("there are no pc-relative size relocations"));
2977 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2978 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2981 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2983 as_bad (_("unknown relocation (%u)"), other
);
2984 else if (size
!= bfd_get_reloc_size (rel
))
2985 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2986 bfd_get_reloc_size (rel
),
2988 else if (pcrel
&& !rel
->pc_relative
)
2989 as_bad (_("non-pc-relative relocation for pc-relative field"));
2990 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2992 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2994 as_bad (_("relocated field and relocation type differ in signedness"));
3003 as_bad (_("there are no unsigned pc-relative relocations"));
3006 case 1: return BFD_RELOC_8_PCREL
;
3007 case 2: return BFD_RELOC_16_PCREL
;
3008 case 4: return BFD_RELOC_32_PCREL
;
3009 case 8: return BFD_RELOC_64_PCREL
;
3011 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3018 case 4: return BFD_RELOC_X86_64_32S
;
3023 case 1: return BFD_RELOC_8
;
3024 case 2: return BFD_RELOC_16
;
3025 case 4: return BFD_RELOC_32
;
3026 case 8: return BFD_RELOC_64
;
3028 as_bad (_("cannot do %s %u byte relocation"),
3029 sign
> 0 ? "signed" : "unsigned", size
);
3035 /* Here we decide which fixups can be adjusted to make them relative to
3036 the beginning of the section instead of the symbol. Basically we need
3037 to make sure that the dynamic relocations are done correctly, so in
3038 some cases we force the original symbol to be used. */
3041 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3043 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3047 /* Don't adjust pc-relative references to merge sections in 64-bit
3049 if (use_rela_relocations
3050 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3054 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3055 and changed later by validate_fix. */
3056 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3057 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3060 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3061 for size relocations. */
3062 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3063 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3064 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3065 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3066 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3067 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3068 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3069 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3070 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3071 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3072 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3073 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3074 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3075 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3076 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3077 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3078 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3079 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3080 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3081 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3082 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3083 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3084 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3085 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3086 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3087 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3088 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3089 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3090 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3091 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3092 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3093 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3094 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3101 intel_float_operand (const char *mnemonic
)
3103 /* Note that the value returned is meaningful only for opcodes with (memory)
3104 operands, hence the code here is free to improperly handle opcodes that
3105 have no operands (for better performance and smaller code). */
3107 if (mnemonic
[0] != 'f')
3108 return 0; /* non-math */
3110 switch (mnemonic
[1])
3112 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3113 the fs segment override prefix not currently handled because no
3114 call path can make opcodes without operands get here */
3116 return 2 /* integer op */;
3118 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3119 return 3; /* fldcw/fldenv */
3122 if (mnemonic
[2] != 'o' /* fnop */)
3123 return 3; /* non-waiting control op */
3126 if (mnemonic
[2] == 's')
3127 return 3; /* frstor/frstpm */
3130 if (mnemonic
[2] == 'a')
3131 return 3; /* fsave */
3132 if (mnemonic
[2] == 't')
3134 switch (mnemonic
[3])
3136 case 'c': /* fstcw */
3137 case 'd': /* fstdw */
3138 case 'e': /* fstenv */
3139 case 's': /* fsts[gw] */
3145 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3146 return 0; /* fxsave/fxrstor are not really math ops */
3153 /* Build the VEX prefix. */
3156 build_vex_prefix (const insn_template
*t
)
3158 unsigned int register_specifier
;
3159 unsigned int implied_prefix
;
3160 unsigned int vector_length
;
3162 /* Check register specifier. */
3163 if (i
.vex
.register_specifier
)
3165 register_specifier
=
3166 ~register_number (i
.vex
.register_specifier
) & 0xf;
3167 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3170 register_specifier
= 0xf;
3172 /* Use 2-byte VEX prefix by swapping destination and source
3174 if (i
.vec_encoding
!= vex_encoding_vex3
3175 && i
.dir_encoding
== dir_encoding_default
3176 && i
.operands
== i
.reg_operands
3177 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3178 && i
.tm
.opcode_modifier
.load
3181 unsigned int xchg
= i
.operands
- 1;
3182 union i386_op temp_op
;
3183 i386_operand_type temp_type
;
3185 temp_type
= i
.types
[xchg
];
3186 i
.types
[xchg
] = i
.types
[0];
3187 i
.types
[0] = temp_type
;
3188 temp_op
= i
.op
[xchg
];
3189 i
.op
[xchg
] = i
.op
[0];
3192 gas_assert (i
.rm
.mode
== 3);
3196 i
.rm
.regmem
= i
.rm
.reg
;
3199 /* Use the next insn. */
3203 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3204 vector_length
= avxscalar
;
3206 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3208 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3213 case DATA_PREFIX_OPCODE
:
3216 case REPE_PREFIX_OPCODE
:
3219 case REPNE_PREFIX_OPCODE
:
3226 /* Use 2-byte VEX prefix if possible. */
3227 if (i
.vec_encoding
!= vex_encoding_vex3
3228 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3229 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3230 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3232 /* 2-byte VEX prefix. */
3236 i
.vex
.bytes
[0] = 0xc5;
3238 /* Check the REX.R bit. */
3239 r
= (i
.rex
& REX_R
) ? 0 : 1;
3240 i
.vex
.bytes
[1] = (r
<< 7
3241 | register_specifier
<< 3
3242 | vector_length
<< 2
3247 /* 3-byte VEX prefix. */
3252 switch (i
.tm
.opcode_modifier
.vexopcode
)
3256 i
.vex
.bytes
[0] = 0xc4;
3260 i
.vex
.bytes
[0] = 0xc4;
3264 i
.vex
.bytes
[0] = 0xc4;
3268 i
.vex
.bytes
[0] = 0x8f;
3272 i
.vex
.bytes
[0] = 0x8f;
3276 i
.vex
.bytes
[0] = 0x8f;
3282 /* The high 3 bits of the second VEX byte are 1's compliment
3283 of RXB bits from REX. */
3284 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3286 /* Check the REX.W bit. */
3287 w
= (i
.rex
& REX_W
) ? 1 : 0;
3288 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3291 i
.vex
.bytes
[2] = (w
<< 7
3292 | register_specifier
<< 3
3293 | vector_length
<< 2
3298 /* Build the EVEX prefix. */
3301 build_evex_prefix (void)
3303 unsigned int register_specifier
;
3304 unsigned int implied_prefix
;
3306 rex_byte vrex_used
= 0;
3308 /* Check register specifier. */
3309 if (i
.vex
.register_specifier
)
3311 gas_assert ((i
.vrex
& REX_X
) == 0);
3313 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3314 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3315 register_specifier
+= 8;
3316 /* The upper 16 registers are encoded in the fourth byte of the
3318 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3319 i
.vex
.bytes
[3] = 0x8;
3320 register_specifier
= ~register_specifier
& 0xf;
3324 register_specifier
= 0xf;
3326 /* Encode upper 16 vector index register in the fourth byte of
3328 if (!(i
.vrex
& REX_X
))
3329 i
.vex
.bytes
[3] = 0x8;
3334 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3339 case DATA_PREFIX_OPCODE
:
3342 case REPE_PREFIX_OPCODE
:
3345 case REPNE_PREFIX_OPCODE
:
3352 /* 4 byte EVEX prefix. */
3354 i
.vex
.bytes
[0] = 0x62;
3357 switch (i
.tm
.opcode_modifier
.vexopcode
)
3373 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3375 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3377 /* The fifth bit of the second EVEX byte is 1's compliment of the
3378 REX_R bit in VREX. */
3379 if (!(i
.vrex
& REX_R
))
3380 i
.vex
.bytes
[1] |= 0x10;
3384 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3386 /* When all operands are registers, the REX_X bit in REX is not
3387 used. We reuse it to encode the upper 16 registers, which is
3388 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3389 as 1's compliment. */
3390 if ((i
.vrex
& REX_B
))
3393 i
.vex
.bytes
[1] &= ~0x40;
3397 /* EVEX instructions shouldn't need the REX prefix. */
3398 i
.vrex
&= ~vrex_used
;
3399 gas_assert (i
.vrex
== 0);
3401 /* Check the REX.W bit. */
3402 w
= (i
.rex
& REX_W
) ? 1 : 0;
3403 if (i
.tm
.opcode_modifier
.vexw
)
3405 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3408 /* If w is not set it means we are dealing with WIG instruction. */
3411 if (evexwig
== evexw1
)
3415 /* Encode the U bit. */
3416 implied_prefix
|= 0x4;
3418 /* The third byte of the EVEX prefix. */
3419 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3421 /* The fourth byte of the EVEX prefix. */
3422 /* The zeroing-masking bit. */
3423 if (i
.mask
&& i
.mask
->zeroing
)
3424 i
.vex
.bytes
[3] |= 0x80;
3426 /* Don't always set the broadcast bit if there is no RC. */
3429 /* Encode the vector length. */
3430 unsigned int vec_length
;
3432 switch (i
.tm
.opcode_modifier
.evex
)
3434 case EVEXLIG
: /* LL' is ignored */
3435 vec_length
= evexlig
<< 5;
3438 vec_length
= 0 << 5;
3441 vec_length
= 1 << 5;
3444 vec_length
= 2 << 5;
3450 i
.vex
.bytes
[3] |= vec_length
;
3451 /* Encode the broadcast bit. */
3453 i
.vex
.bytes
[3] |= 0x10;
3457 if (i
.rounding
->type
!= saeonly
)
3458 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3460 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3463 if (i
.mask
&& i
.mask
->mask
)
3464 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3468 process_immext (void)
3472 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3475 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3476 with an opcode suffix which is coded in the same place as an
3477 8-bit immediate field would be.
3478 Here we check those operands and remove them afterwards. */
3481 for (x
= 0; x
< i
.operands
; x
++)
3482 if (register_number (i
.op
[x
].regs
) != x
)
3483 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3484 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3490 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3492 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3493 suffix which is coded in the same place as an 8-bit immediate
3495 Here we check those operands and remove them afterwards. */
3498 if (i
.operands
!= 3)
3501 for (x
= 0; x
< 2; x
++)
3502 if (register_number (i
.op
[x
].regs
) != x
)
3503 goto bad_register_operand
;
3505 /* Check for third operand for mwaitx/monitorx insn. */
3506 if (register_number (i
.op
[x
].regs
)
3507 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3509 bad_register_operand
:
3510 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3511 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3518 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3519 which is coded in the same place as an 8-bit immediate field
3520 would be. Here we fake an 8-bit immediate operand from the
3521 opcode suffix stored in tm.extension_opcode.
3523 AVX instructions also use this encoding, for some of
3524 3 argument instructions. */
3526 gas_assert (i
.imm_operands
<= 1
3528 || ((i
.tm
.opcode_modifier
.vex
3529 || i
.tm
.opcode_modifier
.evex
)
3530 && i
.operands
<= 4)));
3532 exp
= &im_expressions
[i
.imm_operands
++];
3533 i
.op
[i
.operands
].imms
= exp
;
3534 i
.types
[i
.operands
] = imm8
;
3536 exp
->X_op
= O_constant
;
3537 exp
->X_add_number
= i
.tm
.extension_opcode
;
3538 i
.tm
.extension_opcode
= None
;
3545 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3550 as_bad (_("invalid instruction `%s' after `%s'"),
3551 i
.tm
.name
, i
.hle_prefix
);
3554 if (i
.prefix
[LOCK_PREFIX
])
3556 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3560 case HLEPrefixRelease
:
3561 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3563 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3567 if (i
.mem_operands
== 0
3568 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3570 as_bad (_("memory destination needed for instruction `%s'"
3571 " after `xrelease'"), i
.tm
.name
);
3578 /* This is the guts of the machine-dependent assembler. LINE points to a
3579 machine dependent instruction. This function is supposed to emit
3580 the frags/bytes it assembles to. */
3583 md_assemble (char *line
)
3586 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
3587 const insn_template
*t
;
3589 /* Initialize globals. */
3590 memset (&i
, '\0', sizeof (i
));
3591 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3592 i
.reloc
[j
] = NO_RELOC
;
3593 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3594 memset (im_expressions
, '\0', sizeof (im_expressions
));
3595 save_stack_p
= save_stack
;
3597 /* First parse an instruction mnemonic & call i386_operand for the operands.
3598 We assume that the scrubber has arranged it so that line[0] is the valid
3599 start of a (possibly prefixed) mnemonic. */
3601 line
= parse_insn (line
, mnemonic
);
3604 mnem_suffix
= i
.suffix
;
3606 line
= parse_operands (line
, mnemonic
);
3608 xfree (i
.memop1_string
);
3609 i
.memop1_string
= NULL
;
3613 /* Now we've parsed the mnemonic into a set of templates, and have the
3614 operands at hand. */
3616 /* All intel opcodes have reversed operands except for "bound" and
3617 "enter". We also don't reverse intersegment "jmp" and "call"
3618 instructions with 2 immediate operands so that the immediate segment
3619 precedes the offset, as it does when in AT&T mode. */
3622 && (strcmp (mnemonic
, "bound") != 0)
3623 && (strcmp (mnemonic
, "invlpga") != 0)
3624 && !(operand_type_check (i
.types
[0], imm
)
3625 && operand_type_check (i
.types
[1], imm
)))
3628 /* The order of the immediates should be reversed
3629 for 2 immediates extrq and insertq instructions */
3630 if (i
.imm_operands
== 2
3631 && (strcmp (mnemonic
, "extrq") == 0
3632 || strcmp (mnemonic
, "insertq") == 0))
3633 swap_2_operands (0, 1);
3638 /* Don't optimize displacement for movabs since it only takes 64bit
3641 && i
.disp_encoding
!= disp_encoding_32bit
3642 && (flag_code
!= CODE_64BIT
3643 || strcmp (mnemonic
, "movabs") != 0))
3646 /* Next, we find a template that matches the given insn,
3647 making sure the overlap of the given operands types is consistent
3648 with the template operand types. */
3650 if (!(t
= match_template (mnem_suffix
)))
3653 if (sse_check
!= check_none
3654 && !i
.tm
.opcode_modifier
.noavx
3655 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3656 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3657 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3658 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3659 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3660 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3662 (sse_check
== check_warning
3664 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3667 /* Zap movzx and movsx suffix. The suffix has been set from
3668 "word ptr" or "byte ptr" on the source operand in Intel syntax
3669 or extracted from mnemonic in AT&T syntax. But we'll use
3670 the destination register to choose the suffix for encoding. */
3671 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3673 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3674 there is no suffix, the default will be byte extension. */
3675 if (i
.reg_operands
!= 2
3678 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3683 if (i
.tm
.opcode_modifier
.fwait
)
3684 if (!add_prefix (FWAIT_OPCODE
))
3687 /* Check if REP prefix is OK. */
3688 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3690 as_bad (_("invalid instruction `%s' after `%s'"),
3691 i
.tm
.name
, i
.rep_prefix
);
3695 /* Check for lock without a lockable instruction. Destination operand
3696 must be memory unless it is xchg (0x86). */
3697 if (i
.prefix
[LOCK_PREFIX
]
3698 && (!i
.tm
.opcode_modifier
.islockable
3699 || i
.mem_operands
== 0
3700 || (i
.tm
.base_opcode
!= 0x86
3701 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3703 as_bad (_("expecting lockable instruction after `lock'"));
3707 /* Check if HLE prefix is OK. */
3708 if (i
.hle_prefix
&& !check_hle ())
3711 /* Check BND prefix. */
3712 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3713 as_bad (_("expecting valid branch instruction after `bnd'"));
3715 /* Check NOTRACK prefix. */
3716 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
3717 as_bad (_("expecting indirect branch instruction after `notrack'"));
3719 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
3721 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
3722 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3723 else if (flag_code
!= CODE_16BIT
3724 ? i
.prefix
[ADDR_PREFIX
]
3725 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
3726 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3729 /* Insert BND prefix. */
3731 && i
.tm
.opcode_modifier
.bndprefixok
3732 && !i
.prefix
[BND_PREFIX
])
3733 add_prefix (BND_PREFIX_OPCODE
);
3735 /* Check string instruction segment overrides. */
3736 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3738 if (!check_string ())
3740 i
.disp_operands
= 0;
3743 if (!process_suffix ())
3746 /* Update operand types. */
3747 for (j
= 0; j
< i
.operands
; j
++)
3748 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3750 /* Make still unresolved immediate matches conform to size of immediate
3751 given in i.suffix. */
3752 if (!finalize_imm ())
3755 if (i
.types
[0].bitfield
.imm1
)
3756 i
.imm_operands
= 0; /* kludge for shift insns. */
3758 /* We only need to check those implicit registers for instructions
3759 with 3 operands or less. */
3760 if (i
.operands
<= 3)
3761 for (j
= 0; j
< i
.operands
; j
++)
3762 if (i
.types
[j
].bitfield
.inoutportreg
3763 || i
.types
[j
].bitfield
.shiftcount
3764 || i
.types
[j
].bitfield
.acc
3765 || i
.types
[j
].bitfield
.floatacc
)
3768 /* ImmExt should be processed after SSE2AVX. */
3769 if (!i
.tm
.opcode_modifier
.sse2avx
3770 && i
.tm
.opcode_modifier
.immext
)
3773 /* For insns with operands there are more diddles to do to the opcode. */
3776 if (!process_operands ())
3779 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3781 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3782 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3785 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3787 if (flag_code
== CODE_16BIT
)
3789 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3794 if (i
.tm
.opcode_modifier
.vex
)
3795 build_vex_prefix (t
);
3797 build_evex_prefix ();
3800 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3801 instructions may define INT_OPCODE as well, so avoid this corner
3802 case for those instructions that use MODRM. */
3803 if (i
.tm
.base_opcode
== INT_OPCODE
3804 && !i
.tm
.opcode_modifier
.modrm
3805 && i
.op
[0].imms
->X_add_number
== 3)
3807 i
.tm
.base_opcode
= INT3_OPCODE
;
3811 if ((i
.tm
.opcode_modifier
.jump
3812 || i
.tm
.opcode_modifier
.jumpbyte
3813 || i
.tm
.opcode_modifier
.jumpdword
)
3814 && i
.op
[0].disps
->X_op
== O_constant
)
3816 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3817 the absolute address given by the constant. Since ix86 jumps and
3818 calls are pc relative, we need to generate a reloc. */
3819 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3820 i
.op
[0].disps
->X_op
= O_symbol
;
3823 if (i
.tm
.opcode_modifier
.rex64
)
3826 /* For 8 bit registers we need an empty rex prefix. Also if the
3827 instruction already has a prefix, we need to convert old
3828 registers to new ones. */
3830 if ((i
.types
[0].bitfield
.reg8
3831 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3832 || (i
.types
[1].bitfield
.reg8
3833 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3834 || ((i
.types
[0].bitfield
.reg8
3835 || i
.types
[1].bitfield
.reg8
)
3840 i
.rex
|= REX_OPCODE
;
3841 for (x
= 0; x
< 2; x
++)
3843 /* Look for 8 bit operand that uses old registers. */
3844 if (i
.types
[x
].bitfield
.reg8
3845 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3847 /* In case it is "hi" register, give up. */
3848 if (i
.op
[x
].regs
->reg_num
> 3)
3849 as_bad (_("can't encode register '%s%s' in an "
3850 "instruction requiring REX prefix."),
3851 register_prefix
, i
.op
[x
].regs
->reg_name
);
3853 /* Otherwise it is equivalent to the extended register.
3854 Since the encoding doesn't change this is merely
3855 cosmetic cleanup for debug output. */
3857 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3863 add_prefix (REX_OPCODE
| i
.rex
);
3865 /* We are ready to output the insn. */
3870 parse_insn (char *line
, char *mnemonic
)
3873 char *token_start
= l
;
3876 const insn_template
*t
;
3882 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3887 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3889 as_bad (_("no such instruction: `%s'"), token_start
);
3894 if (!is_space_char (*l
)
3895 && *l
!= END_OF_INSN
3897 || (*l
!= PREFIX_SEPARATOR
3900 as_bad (_("invalid character %s in mnemonic"),
3901 output_invalid (*l
));
3904 if (token_start
== l
)
3906 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3907 as_bad (_("expecting prefix; got nothing"));
3909 as_bad (_("expecting mnemonic; got nothing"));
3913 /* Look up instruction (or prefix) via hash table. */
3914 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3916 if (*l
!= END_OF_INSN
3917 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3918 && current_templates
3919 && current_templates
->start
->opcode_modifier
.isprefix
)
3921 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3923 as_bad ((flag_code
!= CODE_64BIT
3924 ? _("`%s' is only supported in 64-bit mode")
3925 : _("`%s' is not supported in 64-bit mode")),
3926 current_templates
->start
->name
);
3929 /* If we are in 16-bit mode, do not allow addr16 or data16.
3930 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3931 if ((current_templates
->start
->opcode_modifier
.size16
3932 || current_templates
->start
->opcode_modifier
.size32
)
3933 && flag_code
!= CODE_64BIT
3934 && (current_templates
->start
->opcode_modifier
.size32
3935 ^ (flag_code
== CODE_16BIT
)))
3937 as_bad (_("redundant %s prefix"),
3938 current_templates
->start
->name
);
3941 if (current_templates
->start
->opcode_length
== 0)
3943 /* Handle pseudo prefixes. */
3944 switch (current_templates
->start
->base_opcode
)
3948 i
.disp_encoding
= disp_encoding_8bit
;
3952 i
.disp_encoding
= disp_encoding_32bit
;
3956 i
.dir_encoding
= dir_encoding_load
;
3960 i
.dir_encoding
= dir_encoding_store
;
3964 i
.vec_encoding
= vex_encoding_vex2
;
3968 i
.vec_encoding
= vex_encoding_vex3
;
3972 i
.vec_encoding
= vex_encoding_evex
;
3980 /* Add prefix, checking for repeated prefixes. */
3982 = add_prefix (current_templates
->start
->base_opcode
);
3984 && current_templates
->start
->cpu_flags
.bitfield
.cpucet
)
3986 i
.notrack_prefix
= current_templates
->start
->name
;
3987 /* Move NOTRACK_PREFIX_OPCODE to NOTRACK_PREFIX slot so
3988 that it is placed before others. */
3989 i
.prefix
[SEG_PREFIX
] = 0;
3990 i
.prefix
[NOTRACK_PREFIX
] = NOTRACK_PREFIX_OPCODE
;
3999 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4000 i
.hle_prefix
= current_templates
->start
->name
;
4001 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4002 i
.bnd_prefix
= current_templates
->start
->name
;
4004 i
.rep_prefix
= current_templates
->start
->name
;
4010 if (i
.notrack_prefix
!= NULL
)
4012 /* There must be no other prefixes after NOTRACK
4014 as_bad (_("expecting no other prefixes after `notrack'"));
4019 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4026 if (!current_templates
)
4028 /* Check if we should swap operand or force 32bit displacement in
4030 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4031 i
.dir_encoding
= dir_encoding_store
;
4032 else if (mnem_p
- 3 == dot_p
4035 i
.disp_encoding
= disp_encoding_8bit
;
4036 else if (mnem_p
- 4 == dot_p
4040 i
.disp_encoding
= disp_encoding_32bit
;
4045 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4048 if (!current_templates
)
4051 /* See if we can get a match by trimming off a suffix. */
4054 case WORD_MNEM_SUFFIX
:
4055 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4056 i
.suffix
= SHORT_MNEM_SUFFIX
;
4059 case BYTE_MNEM_SUFFIX
:
4060 case QWORD_MNEM_SUFFIX
:
4061 i
.suffix
= mnem_p
[-1];
4063 current_templates
= (const templates
*) hash_find (op_hash
,
4066 case SHORT_MNEM_SUFFIX
:
4067 case LONG_MNEM_SUFFIX
:
4070 i
.suffix
= mnem_p
[-1];
4072 current_templates
= (const templates
*) hash_find (op_hash
,
4081 if (intel_float_operand (mnemonic
) == 1)
4082 i
.suffix
= SHORT_MNEM_SUFFIX
;
4084 i
.suffix
= LONG_MNEM_SUFFIX
;
4086 current_templates
= (const templates
*) hash_find (op_hash
,
4091 if (!current_templates
)
4093 as_bad (_("no such instruction: `%s'"), token_start
);
4098 if (current_templates
->start
->opcode_modifier
.jump
4099 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4101 /* Check for a branch hint. We allow ",pt" and ",pn" for
4102 predict taken and predict not taken respectively.
4103 I'm not sure that branch hints actually do anything on loop
4104 and jcxz insns (JumpByte) for current Pentium4 chips. They
4105 may work in the future and it doesn't hurt to accept them
4107 if (l
[0] == ',' && l
[1] == 'p')
4111 if (!add_prefix (DS_PREFIX_OPCODE
))
4115 else if (l
[2] == 'n')
4117 if (!add_prefix (CS_PREFIX_OPCODE
))
4123 /* Any other comma loses. */
4126 as_bad (_("invalid character %s in mnemonic"),
4127 output_invalid (*l
));
4131 /* Check if instruction is supported on specified architecture. */
4133 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4135 supported
|= cpu_flags_match (t
);
4136 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4140 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4142 as_bad (flag_code
== CODE_64BIT
4143 ? _("`%s' is not supported in 64-bit mode")
4144 : _("`%s' is only supported in 64-bit mode"),
4145 current_templates
->start
->name
);
4148 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
4150 as_bad (_("`%s' is not supported on `%s%s'"),
4151 current_templates
->start
->name
,
4152 cpu_arch_name
? cpu_arch_name
: default_arch
,
4153 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4158 if (!cpu_arch_flags
.bitfield
.cpui386
4159 && (flag_code
!= CODE_16BIT
))
4161 as_warn (_("use .code16 to ensure correct addressing mode"));
4168 parse_operands (char *l
, const char *mnemonic
)
4172 /* 1 if operand is pending after ','. */
4173 unsigned int expecting_operand
= 0;
4175 /* Non-zero if operand parens not balanced. */
4176 unsigned int paren_not_balanced
;
4178 while (*l
!= END_OF_INSN
)
4180 /* Skip optional white space before operand. */
4181 if (is_space_char (*l
))
4183 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4185 as_bad (_("invalid character %s before operand %d"),
4186 output_invalid (*l
),
4190 token_start
= l
; /* After white space. */
4191 paren_not_balanced
= 0;
4192 while (paren_not_balanced
|| *l
!= ',')
4194 if (*l
== END_OF_INSN
)
4196 if (paren_not_balanced
)
4199 as_bad (_("unbalanced parenthesis in operand %d."),
4202 as_bad (_("unbalanced brackets in operand %d."),
4207 break; /* we are done */
4209 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4211 as_bad (_("invalid character %s in operand %d"),
4212 output_invalid (*l
),
4219 ++paren_not_balanced
;
4221 --paren_not_balanced
;
4226 ++paren_not_balanced
;
4228 --paren_not_balanced
;
4232 if (l
!= token_start
)
4233 { /* Yes, we've read in another operand. */
4234 unsigned int operand_ok
;
4235 this_operand
= i
.operands
++;
4236 if (i
.operands
> MAX_OPERANDS
)
4238 as_bad (_("spurious operands; (%d operands/instruction max)"),
4242 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4243 /* Now parse operand adding info to 'i' as we go along. */
4244 END_STRING_AND_SAVE (l
);
4248 i386_intel_operand (token_start
,
4249 intel_float_operand (mnemonic
));
4251 operand_ok
= i386_att_operand (token_start
);
4253 RESTORE_END_STRING (l
);
4259 if (expecting_operand
)
4261 expecting_operand_after_comma
:
4262 as_bad (_("expecting operand after ','; got nothing"));
4267 as_bad (_("expecting operand before ','; got nothing"));
4272 /* Now *l must be either ',' or END_OF_INSN. */
4275 if (*++l
== END_OF_INSN
)
4277 /* Just skip it, if it's \n complain. */
4278 goto expecting_operand_after_comma
;
4280 expecting_operand
= 1;
4287 swap_2_operands (int xchg1
, int xchg2
)
4289 union i386_op temp_op
;
4290 i386_operand_type temp_type
;
4291 enum bfd_reloc_code_real temp_reloc
;
4293 temp_type
= i
.types
[xchg2
];
4294 i
.types
[xchg2
] = i
.types
[xchg1
];
4295 i
.types
[xchg1
] = temp_type
;
4296 temp_op
= i
.op
[xchg2
];
4297 i
.op
[xchg2
] = i
.op
[xchg1
];
4298 i
.op
[xchg1
] = temp_op
;
4299 temp_reloc
= i
.reloc
[xchg2
];
4300 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4301 i
.reloc
[xchg1
] = temp_reloc
;
4305 if (i
.mask
->operand
== xchg1
)
4306 i
.mask
->operand
= xchg2
;
4307 else if (i
.mask
->operand
== xchg2
)
4308 i
.mask
->operand
= xchg1
;
4312 if (i
.broadcast
->operand
== xchg1
)
4313 i
.broadcast
->operand
= xchg2
;
4314 else if (i
.broadcast
->operand
== xchg2
)
4315 i
.broadcast
->operand
= xchg1
;
4319 if (i
.rounding
->operand
== xchg1
)
4320 i
.rounding
->operand
= xchg2
;
4321 else if (i
.rounding
->operand
== xchg2
)
4322 i
.rounding
->operand
= xchg1
;
4327 swap_operands (void)
4333 swap_2_operands (1, i
.operands
- 2);
4337 swap_2_operands (0, i
.operands
- 1);
4343 if (i
.mem_operands
== 2)
4345 const seg_entry
*temp_seg
;
4346 temp_seg
= i
.seg
[0];
4347 i
.seg
[0] = i
.seg
[1];
4348 i
.seg
[1] = temp_seg
;
4352 /* Try to ensure constant immediates are represented in the smallest
4357 char guess_suffix
= 0;
4361 guess_suffix
= i
.suffix
;
4362 else if (i
.reg_operands
)
4364 /* Figure out a suffix from the last register operand specified.
4365 We can't do this properly yet, ie. excluding InOutPortReg,
4366 but the following works for instructions with immediates.
4367 In any case, we can't set i.suffix yet. */
4368 for (op
= i
.operands
; --op
>= 0;)
4369 if (i
.types
[op
].bitfield
.reg8
)
4371 guess_suffix
= BYTE_MNEM_SUFFIX
;
4374 else if (i
.types
[op
].bitfield
.reg16
)
4376 guess_suffix
= WORD_MNEM_SUFFIX
;
4379 else if (i
.types
[op
].bitfield
.reg32
)
4381 guess_suffix
= LONG_MNEM_SUFFIX
;
4384 else if (i
.types
[op
].bitfield
.reg64
)
4386 guess_suffix
= QWORD_MNEM_SUFFIX
;
4390 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4391 guess_suffix
= WORD_MNEM_SUFFIX
;
4393 for (op
= i
.operands
; --op
>= 0;)
4394 if (operand_type_check (i
.types
[op
], imm
))
4396 switch (i
.op
[op
].imms
->X_op
)
4399 /* If a suffix is given, this operand may be shortened. */
4400 switch (guess_suffix
)
4402 case LONG_MNEM_SUFFIX
:
4403 i
.types
[op
].bitfield
.imm32
= 1;
4404 i
.types
[op
].bitfield
.imm64
= 1;
4406 case WORD_MNEM_SUFFIX
:
4407 i
.types
[op
].bitfield
.imm16
= 1;
4408 i
.types
[op
].bitfield
.imm32
= 1;
4409 i
.types
[op
].bitfield
.imm32s
= 1;
4410 i
.types
[op
].bitfield
.imm64
= 1;
4412 case BYTE_MNEM_SUFFIX
:
4413 i
.types
[op
].bitfield
.imm8
= 1;
4414 i
.types
[op
].bitfield
.imm8s
= 1;
4415 i
.types
[op
].bitfield
.imm16
= 1;
4416 i
.types
[op
].bitfield
.imm32
= 1;
4417 i
.types
[op
].bitfield
.imm32s
= 1;
4418 i
.types
[op
].bitfield
.imm64
= 1;
4422 /* If this operand is at most 16 bits, convert it
4423 to a signed 16 bit number before trying to see
4424 whether it will fit in an even smaller size.
4425 This allows a 16-bit operand such as $0xffe0 to
4426 be recognised as within Imm8S range. */
4427 if ((i
.types
[op
].bitfield
.imm16
)
4428 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4430 i
.op
[op
].imms
->X_add_number
=
4431 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4434 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4435 if ((i
.types
[op
].bitfield
.imm32
)
4436 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4439 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4440 ^ ((offsetT
) 1 << 31))
4441 - ((offsetT
) 1 << 31));
4445 = operand_type_or (i
.types
[op
],
4446 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4448 /* We must avoid matching of Imm32 templates when 64bit
4449 only immediate is available. */
4450 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4451 i
.types
[op
].bitfield
.imm32
= 0;
4458 /* Symbols and expressions. */
4460 /* Convert symbolic operand to proper sizes for matching, but don't
4461 prevent matching a set of insns that only supports sizes other
4462 than those matching the insn suffix. */
4464 i386_operand_type mask
, allowed
;
4465 const insn_template
*t
;
4467 operand_type_set (&mask
, 0);
4468 operand_type_set (&allowed
, 0);
4470 for (t
= current_templates
->start
;
4471 t
< current_templates
->end
;
4473 allowed
= operand_type_or (allowed
,
4474 t
->operand_types
[op
]);
4475 switch (guess_suffix
)
4477 case QWORD_MNEM_SUFFIX
:
4478 mask
.bitfield
.imm64
= 1;
4479 mask
.bitfield
.imm32s
= 1;
4481 case LONG_MNEM_SUFFIX
:
4482 mask
.bitfield
.imm32
= 1;
4484 case WORD_MNEM_SUFFIX
:
4485 mask
.bitfield
.imm16
= 1;
4487 case BYTE_MNEM_SUFFIX
:
4488 mask
.bitfield
.imm8
= 1;
4493 allowed
= operand_type_and (mask
, allowed
);
4494 if (!operand_type_all_zero (&allowed
))
4495 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4502 /* Try to use the smallest displacement type too. */
4504 optimize_disp (void)
4508 for (op
= i
.operands
; --op
>= 0;)
4509 if (operand_type_check (i
.types
[op
], disp
))
4511 if (i
.op
[op
].disps
->X_op
== O_constant
)
4513 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4515 if (i
.types
[op
].bitfield
.disp16
4516 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4518 /* If this operand is at most 16 bits, convert
4519 to a signed 16 bit number and don't use 64bit
4521 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4522 i
.types
[op
].bitfield
.disp64
= 0;
4525 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4526 if (i
.types
[op
].bitfield
.disp32
4527 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4529 /* If this operand is at most 32 bits, convert
4530 to a signed 32 bit number and don't use 64bit
4532 op_disp
&= (((offsetT
) 2 << 31) - 1);
4533 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4534 i
.types
[op
].bitfield
.disp64
= 0;
4537 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4539 i
.types
[op
].bitfield
.disp8
= 0;
4540 i
.types
[op
].bitfield
.disp16
= 0;
4541 i
.types
[op
].bitfield
.disp32
= 0;
4542 i
.types
[op
].bitfield
.disp32s
= 0;
4543 i
.types
[op
].bitfield
.disp64
= 0;
4547 else if (flag_code
== CODE_64BIT
)
4549 if (fits_in_signed_long (op_disp
))
4551 i
.types
[op
].bitfield
.disp64
= 0;
4552 i
.types
[op
].bitfield
.disp32s
= 1;
4554 if (i
.prefix
[ADDR_PREFIX
]
4555 && fits_in_unsigned_long (op_disp
))
4556 i
.types
[op
].bitfield
.disp32
= 1;
4558 if ((i
.types
[op
].bitfield
.disp32
4559 || i
.types
[op
].bitfield
.disp32s
4560 || i
.types
[op
].bitfield
.disp16
)
4561 && fits_in_signed_byte (op_disp
))
4562 i
.types
[op
].bitfield
.disp8
= 1;
4564 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4565 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4567 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4568 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4569 i
.types
[op
].bitfield
.disp8
= 0;
4570 i
.types
[op
].bitfield
.disp16
= 0;
4571 i
.types
[op
].bitfield
.disp32
= 0;
4572 i
.types
[op
].bitfield
.disp32s
= 0;
4573 i
.types
[op
].bitfield
.disp64
= 0;
4576 /* We only support 64bit displacement on constants. */
4577 i
.types
[op
].bitfield
.disp64
= 0;
4581 /* Check if operands are valid for the instruction. */
4584 check_VecOperands (const insn_template
*t
)
4588 /* Without VSIB byte, we can't have a vector register for index. */
4589 if (!t
->opcode_modifier
.vecsib
4591 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4592 || i
.index_reg
->reg_type
.bitfield
.regymm
4593 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4595 i
.error
= unsupported_vector_index_register
;
4599 /* Check if default mask is allowed. */
4600 if (t
->opcode_modifier
.nodefmask
4601 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4603 i
.error
= no_default_mask
;
4607 /* For VSIB byte, we need a vector register for index, and all vector
4608 registers must be distinct. */
4609 if (t
->opcode_modifier
.vecsib
)
4612 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4613 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4614 || (t
->opcode_modifier
.vecsib
== VecSIB256
4615 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4616 || (t
->opcode_modifier
.vecsib
== VecSIB512
4617 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4619 i
.error
= invalid_vsib_address
;
4623 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4624 if (i
.reg_operands
== 2 && !i
.mask
)
4626 gas_assert (i
.types
[0].bitfield
.regxmm
4627 || i
.types
[0].bitfield
.regymm
);
4628 gas_assert (i
.types
[2].bitfield
.regxmm
4629 || i
.types
[2].bitfield
.regymm
);
4630 if (operand_check
== check_none
)
4632 if (register_number (i
.op
[0].regs
)
4633 != register_number (i
.index_reg
)
4634 && register_number (i
.op
[2].regs
)
4635 != register_number (i
.index_reg
)
4636 && register_number (i
.op
[0].regs
)
4637 != register_number (i
.op
[2].regs
))
4639 if (operand_check
== check_error
)
4641 i
.error
= invalid_vector_register_set
;
4644 as_warn (_("mask, index, and destination registers should be distinct"));
4646 else if (i
.reg_operands
== 1 && i
.mask
)
4648 if ((i
.types
[1].bitfield
.regymm
4649 || i
.types
[1].bitfield
.regzmm
)
4650 && (register_number (i
.op
[1].regs
)
4651 == register_number (i
.index_reg
)))
4653 if (operand_check
== check_error
)
4655 i
.error
= invalid_vector_register_set
;
4658 if (operand_check
!= check_none
)
4659 as_warn (_("index and destination registers should be distinct"));
4664 /* Check if broadcast is supported by the instruction and is applied
4665 to the memory operand. */
4668 int broadcasted_opnd_size
;
4670 /* Check if specified broadcast is supported in this instruction,
4671 and it's applied to memory operand of DWORD or QWORD type,
4672 depending on VecESize. */
4673 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4674 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4675 || (t
->opcode_modifier
.vecesize
== 0
4676 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4677 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4678 || (t
->opcode_modifier
.vecesize
== 1
4679 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4680 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4683 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4684 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4685 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4686 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4687 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4688 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4689 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4690 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4691 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4695 if ((broadcasted_opnd_size
== 256
4696 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4697 || (broadcasted_opnd_size
== 512
4698 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4701 i
.error
= unsupported_broadcast
;
4705 /* If broadcast is supported in this instruction, we need to check if
4706 operand of one-element size isn't specified without broadcast. */
4707 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4709 /* Find memory operand. */
4710 for (op
= 0; op
< i
.operands
; op
++)
4711 if (operand_type_check (i
.types
[op
], anymem
))
4713 gas_assert (op
< i
.operands
);
4714 /* Check size of the memory operand. */
4715 if ((t
->opcode_modifier
.vecesize
== 0
4716 && i
.types
[op
].bitfield
.dword
)
4717 || (t
->opcode_modifier
.vecesize
== 1
4718 && i
.types
[op
].bitfield
.qword
))
4720 i
.error
= broadcast_needed
;
4725 /* Check if requested masking is supported. */
4727 && (!t
->opcode_modifier
.masking
4729 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4731 i
.error
= unsupported_masking
;
4735 /* Check if masking is applied to dest operand. */
4736 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4738 i
.error
= mask_not_on_destination
;
4745 if ((i
.rounding
->type
!= saeonly
4746 && !t
->opcode_modifier
.staticrounding
)
4747 || (i
.rounding
->type
== saeonly
4748 && (t
->opcode_modifier
.staticrounding
4749 || !t
->opcode_modifier
.sae
)))
4751 i
.error
= unsupported_rc_sae
;
4754 /* If the instruction has several immediate operands and one of
4755 them is rounding, the rounding operand should be the last
4756 immediate operand. */
4757 if (i
.imm_operands
> 1
4758 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4760 i
.error
= rc_sae_operand_not_last_imm
;
4765 /* Check vector Disp8 operand. */
4766 if (t
->opcode_modifier
.disp8memshift
)
4769 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4771 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4773 for (op
= 0; op
< i
.operands
; op
++)
4774 if (operand_type_check (i
.types
[op
], disp
)
4775 && i
.op
[op
].disps
->X_op
== O_constant
)
4777 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4779 = (i
.disp_encoding
!= disp_encoding_32bit
4780 && fits_in_vec_disp8 (value
));
4781 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4784 i
.types
[op
].bitfield
.vec_disp8
= 1;
4787 /* Vector insn can only have Vec_Disp8/Disp32 in
4788 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4790 i
.types
[op
].bitfield
.disp8
= 0;
4791 if (flag_code
!= CODE_16BIT
)
4792 i
.types
[op
].bitfield
.disp16
= 0;
4795 else if (flag_code
!= CODE_16BIT
)
4797 /* One form of this instruction supports vector Disp8.
4798 Try vector Disp8 if we need to use Disp32. */
4799 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4801 i
.error
= try_vector_disp8
;
4813 /* Check if operands are valid for the instruction. Update VEX
4817 VEX_check_operands (const insn_template
*t
)
4819 if (i
.vec_encoding
== vex_encoding_evex
)
4821 /* This instruction must be encoded with EVEX prefix. */
4822 if (!t
->opcode_modifier
.evex
)
4824 i
.error
= unsupported
;
4830 if (!t
->opcode_modifier
.vex
)
4832 /* This instruction template doesn't have VEX prefix. */
4833 if (i
.vec_encoding
!= vex_encoding_default
)
4835 i
.error
= unsupported
;
4841 /* Only check VEX_Imm4, which must be the first operand. */
4842 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4844 if (i
.op
[0].imms
->X_op
!= O_constant
4845 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4851 /* Turn off Imm8 so that update_imm won't complain. */
4852 i
.types
[0] = vec_imm4
;
4858 static const insn_template
*
4859 match_template (char mnem_suffix
)
4861 /* Points to template once we've found it. */
4862 const insn_template
*t
;
4863 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4864 i386_operand_type overlap4
;
4865 unsigned int found_reverse_match
;
4866 i386_opcode_modifier suffix_check
, mnemsuf_check
;
4867 i386_operand_type operand_types
[MAX_OPERANDS
];
4868 int addr_prefix_disp
;
4870 unsigned int found_cpu_match
;
4871 unsigned int check_register
;
4872 enum i386_error specific_error
= 0;
4874 #if MAX_OPERANDS != 5
4875 # error "MAX_OPERANDS must be 5."
4878 found_reverse_match
= 0;
4879 addr_prefix_disp
= -1;
4881 memset (&suffix_check
, 0, sizeof (suffix_check
));
4882 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4883 suffix_check
.no_bsuf
= 1;
4884 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4885 suffix_check
.no_wsuf
= 1;
4886 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4887 suffix_check
.no_ssuf
= 1;
4888 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4889 suffix_check
.no_lsuf
= 1;
4890 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4891 suffix_check
.no_qsuf
= 1;
4892 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4893 suffix_check
.no_ldsuf
= 1;
4895 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
4898 switch (mnem_suffix
)
4900 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
4901 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
4902 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
4903 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
4904 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
4908 /* Must have right number of operands. */
4909 i
.error
= number_of_operands_mismatch
;
4911 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4913 addr_prefix_disp
= -1;
4915 if (i
.operands
!= t
->operands
)
4918 /* Check processor support. */
4919 i
.error
= unsupported
;
4920 found_cpu_match
= (cpu_flags_match (t
)
4921 == CPU_FLAGS_PERFECT_MATCH
);
4922 if (!found_cpu_match
)
4925 /* Check old gcc support. */
4926 i
.error
= old_gcc_only
;
4927 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4930 /* Check AT&T mnemonic. */
4931 i
.error
= unsupported_with_intel_mnemonic
;
4932 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4935 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
4936 i
.error
= unsupported_syntax
;
4937 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4938 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
4939 || (intel64
&& t
->opcode_modifier
.amd64
)
4940 || (!intel64
&& t
->opcode_modifier
.intel64
))
4943 /* Check the suffix, except for some instructions in intel mode. */
4944 i
.error
= invalid_instruction_suffix
;
4945 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4946 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4947 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4948 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4949 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4950 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4951 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4953 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4954 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
4955 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
4956 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
4957 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
4958 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
4959 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
4962 if (!operand_size_match (t
))
4965 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4966 operand_types
[j
] = t
->operand_types
[j
];
4968 /* In general, don't allow 64-bit operands in 32-bit mode. */
4969 if (i
.suffix
== QWORD_MNEM_SUFFIX
4970 && flag_code
!= CODE_64BIT
4972 ? (!t
->opcode_modifier
.ignoresize
4973 && !intel_float_operand (t
->name
))
4974 : intel_float_operand (t
->name
) != 2)
4975 && ((!operand_types
[0].bitfield
.regmmx
4976 && !operand_types
[0].bitfield
.regxmm
4977 && !operand_types
[0].bitfield
.regymm
4978 && !operand_types
[0].bitfield
.regzmm
)
4979 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4980 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4981 && operand_types
[t
->operands
> 1].bitfield
.regymm
4982 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4983 && (t
->base_opcode
!= 0x0fc7
4984 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4987 /* In general, don't allow 32-bit operands on pre-386. */
4988 else if (i
.suffix
== LONG_MNEM_SUFFIX
4989 && !cpu_arch_flags
.bitfield
.cpui386
4991 ? (!t
->opcode_modifier
.ignoresize
4992 && !intel_float_operand (t
->name
))
4993 : intel_float_operand (t
->name
) != 2)
4994 && ((!operand_types
[0].bitfield
.regmmx
4995 && !operand_types
[0].bitfield
.regxmm
)
4996 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4997 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
5000 /* Do not verify operands when there are none. */
5004 /* We've found a match; break out of loop. */
5008 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5009 into Disp32/Disp16/Disp32 operand. */
5010 if (i
.prefix
[ADDR_PREFIX
] != 0)
5012 /* There should be only one Disp operand. */
5016 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5018 if (operand_types
[j
].bitfield
.disp16
)
5020 addr_prefix_disp
= j
;
5021 operand_types
[j
].bitfield
.disp32
= 1;
5022 operand_types
[j
].bitfield
.disp16
= 0;
5028 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5030 if (operand_types
[j
].bitfield
.disp32
)
5032 addr_prefix_disp
= j
;
5033 operand_types
[j
].bitfield
.disp32
= 0;
5034 operand_types
[j
].bitfield
.disp16
= 1;
5040 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5042 if (operand_types
[j
].bitfield
.disp64
)
5044 addr_prefix_disp
= j
;
5045 operand_types
[j
].bitfield
.disp64
= 0;
5046 operand_types
[j
].bitfield
.disp32
= 1;
5054 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5055 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5058 /* We check register size if needed. */
5059 check_register
= t
->opcode_modifier
.checkregsize
;
5060 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5061 switch (t
->operands
)
5064 if (!operand_type_match (overlap0
, i
.types
[0]))
5068 /* xchg %eax, %eax is a special case. It is an alias for nop
5069 only in 32bit mode and we can use opcode 0x90. In 64bit
5070 mode, we can't use 0x90 for xchg %eax, %eax since it should
5071 zero-extend %eax to %rax. */
5072 if (flag_code
== CODE_64BIT
5073 && t
->base_opcode
== 0x90
5074 && operand_type_equal (&i
.types
[0], &acc32
)
5075 && operand_type_equal (&i
.types
[1], &acc32
))
5077 /* If we want store form, we reverse direction of operands. */
5078 if (i
.dir_encoding
== dir_encoding_store
5079 && t
->opcode_modifier
.d
)
5084 /* If we want store form, we skip the current load. */
5085 if (i
.dir_encoding
== dir_encoding_store
5086 && i
.mem_operands
== 0
5087 && t
->opcode_modifier
.load
)
5092 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5093 if (!operand_type_match (overlap0
, i
.types
[0])
5094 || !operand_type_match (overlap1
, i
.types
[1])
5096 && !operand_type_register_match (overlap0
, i
.types
[0],
5098 overlap1
, i
.types
[1],
5101 /* Check if other direction is valid ... */
5102 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
5106 /* Try reversing direction of operands. */
5107 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
5108 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
5109 if (!operand_type_match (overlap0
, i
.types
[0])
5110 || !operand_type_match (overlap1
, i
.types
[1])
5112 && !operand_type_register_match (overlap0
,
5119 /* Does not match either direction. */
5122 /* found_reverse_match holds which of D or FloatDR
5124 if (t
->opcode_modifier
.d
)
5125 found_reverse_match
= Opcode_D
;
5126 else if (t
->opcode_modifier
.floatd
)
5127 found_reverse_match
= Opcode_FloatD
;
5129 found_reverse_match
= 0;
5130 if (t
->opcode_modifier
.floatr
)
5131 found_reverse_match
|= Opcode_FloatR
;
5135 /* Found a forward 2 operand match here. */
5136 switch (t
->operands
)
5139 overlap4
= operand_type_and (i
.types
[4],
5143 overlap3
= operand_type_and (i
.types
[3],
5147 overlap2
= operand_type_and (i
.types
[2],
5152 switch (t
->operands
)
5155 if (!operand_type_match (overlap4
, i
.types
[4])
5156 || !operand_type_register_match (overlap3
,
5165 if (!operand_type_match (overlap3
, i
.types
[3])
5167 && !operand_type_register_match (overlap2
,
5176 /* Here we make use of the fact that there are no
5177 reverse match 3 operand instructions, and all 3
5178 operand instructions only need to be checked for
5179 register consistency between operands 2 and 3. */
5180 if (!operand_type_match (overlap2
, i
.types
[2])
5182 && !operand_type_register_match (overlap1
,
5192 /* Found either forward/reverse 2, 3 or 4 operand match here:
5193 slip through to break. */
5195 if (!found_cpu_match
)
5197 found_reverse_match
= 0;
5201 /* Check if vector and VEX operands are valid. */
5202 if (check_VecOperands (t
) || VEX_check_operands (t
))
5204 specific_error
= i
.error
;
5208 /* We've found a match; break out of loop. */
5212 if (t
== current_templates
->end
)
5214 /* We found no match. */
5215 const char *err_msg
;
5216 switch (specific_error
? specific_error
: i
.error
)
5220 case operand_size_mismatch
:
5221 err_msg
= _("operand size mismatch");
5223 case operand_type_mismatch
:
5224 err_msg
= _("operand type mismatch");
5226 case register_type_mismatch
:
5227 err_msg
= _("register type mismatch");
5229 case number_of_operands_mismatch
:
5230 err_msg
= _("number of operands mismatch");
5232 case invalid_instruction_suffix
:
5233 err_msg
= _("invalid instruction suffix");
5236 err_msg
= _("constant doesn't fit in 4 bits");
5239 err_msg
= _("only supported with old gcc");
5241 case unsupported_with_intel_mnemonic
:
5242 err_msg
= _("unsupported with Intel mnemonic");
5244 case unsupported_syntax
:
5245 err_msg
= _("unsupported syntax");
5248 as_bad (_("unsupported instruction `%s'"),
5249 current_templates
->start
->name
);
5251 case invalid_vsib_address
:
5252 err_msg
= _("invalid VSIB address");
5254 case invalid_vector_register_set
:
5255 err_msg
= _("mask, index, and destination registers must be distinct");
5257 case unsupported_vector_index_register
:
5258 err_msg
= _("unsupported vector index register");
5260 case unsupported_broadcast
:
5261 err_msg
= _("unsupported broadcast");
5263 case broadcast_not_on_src_operand
:
5264 err_msg
= _("broadcast not on source memory operand");
5266 case broadcast_needed
:
5267 err_msg
= _("broadcast is needed for operand of such type");
5269 case unsupported_masking
:
5270 err_msg
= _("unsupported masking");
5272 case mask_not_on_destination
:
5273 err_msg
= _("mask not on destination operand");
5275 case no_default_mask
:
5276 err_msg
= _("default mask isn't allowed");
5278 case unsupported_rc_sae
:
5279 err_msg
= _("unsupported static rounding/sae");
5281 case rc_sae_operand_not_last_imm
:
5283 err_msg
= _("RC/SAE operand must precede immediate operands");
5285 err_msg
= _("RC/SAE operand must follow immediate operands");
5287 case invalid_register_operand
:
5288 err_msg
= _("invalid register operand");
5291 as_bad (_("%s for `%s'"), err_msg
,
5292 current_templates
->start
->name
);
5296 if (!quiet_warnings
)
5299 && (i
.types
[0].bitfield
.jumpabsolute
5300 != operand_types
[0].bitfield
.jumpabsolute
))
5302 as_warn (_("indirect %s without `*'"), t
->name
);
5305 if (t
->opcode_modifier
.isprefix
5306 && t
->opcode_modifier
.ignoresize
)
5308 /* Warn them that a data or address size prefix doesn't
5309 affect assembly of the next line of code. */
5310 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5314 /* Copy the template we found. */
5317 if (addr_prefix_disp
!= -1)
5318 i
.tm
.operand_types
[addr_prefix_disp
]
5319 = operand_types
[addr_prefix_disp
];
5321 if (found_reverse_match
)
5323 /* If we found a reverse match we must alter the opcode
5324 direction bit. found_reverse_match holds bits to change
5325 (different for int & float insns). */
5327 i
.tm
.base_opcode
^= found_reverse_match
;
5329 i
.tm
.operand_types
[0] = operand_types
[1];
5330 i
.tm
.operand_types
[1] = operand_types
[0];
5339 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5340 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5342 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5344 as_bad (_("`%s' operand %d must use `%ses' segment"),
5350 /* There's only ever one segment override allowed per instruction.
5351 This instruction possibly has a legal segment override on the
5352 second operand, so copy the segment to where non-string
5353 instructions store it, allowing common code. */
5354 i
.seg
[0] = i
.seg
[1];
5356 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5358 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5360 as_bad (_("`%s' operand %d must use `%ses' segment"),
5371 process_suffix (void)
5373 /* If matched instruction specifies an explicit instruction mnemonic
5375 if (i
.tm
.opcode_modifier
.size16
)
5376 i
.suffix
= WORD_MNEM_SUFFIX
;
5377 else if (i
.tm
.opcode_modifier
.size32
)
5378 i
.suffix
= LONG_MNEM_SUFFIX
;
5379 else if (i
.tm
.opcode_modifier
.size64
)
5380 i
.suffix
= QWORD_MNEM_SUFFIX
;
5381 else if (i
.reg_operands
)
5383 /* If there's no instruction mnemonic suffix we try to invent one
5384 based on register operands. */
5387 /* We take i.suffix from the last register operand specified,
5388 Destination register type is more significant than source
5389 register type. crc32 in SSE4.2 prefers source register
5391 if (i
.tm
.base_opcode
== 0xf20f38f1)
5393 if (i
.types
[0].bitfield
.reg16
)
5394 i
.suffix
= WORD_MNEM_SUFFIX
;
5395 else if (i
.types
[0].bitfield
.reg32
)
5396 i
.suffix
= LONG_MNEM_SUFFIX
;
5397 else if (i
.types
[0].bitfield
.reg64
)
5398 i
.suffix
= QWORD_MNEM_SUFFIX
;
5400 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5402 if (i
.types
[0].bitfield
.reg8
)
5403 i
.suffix
= BYTE_MNEM_SUFFIX
;
5410 if (i
.tm
.base_opcode
== 0xf20f38f1
5411 || i
.tm
.base_opcode
== 0xf20f38f0)
5413 /* We have to know the operand size for crc32. */
5414 as_bad (_("ambiguous memory operand size for `%s`"),
5419 for (op
= i
.operands
; --op
>= 0;)
5420 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5422 if (i
.types
[op
].bitfield
.reg8
)
5424 i
.suffix
= BYTE_MNEM_SUFFIX
;
5427 else if (i
.types
[op
].bitfield
.reg16
)
5429 i
.suffix
= WORD_MNEM_SUFFIX
;
5432 else if (i
.types
[op
].bitfield
.reg32
)
5434 i
.suffix
= LONG_MNEM_SUFFIX
;
5437 else if (i
.types
[op
].bitfield
.reg64
)
5439 i
.suffix
= QWORD_MNEM_SUFFIX
;
5445 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5448 && i
.tm
.opcode_modifier
.ignoresize
5449 && i
.tm
.opcode_modifier
.no_bsuf
)
5451 else if (!check_byte_reg ())
5454 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5457 && i
.tm
.opcode_modifier
.ignoresize
5458 && i
.tm
.opcode_modifier
.no_lsuf
)
5460 else if (!check_long_reg ())
5463 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5466 && i
.tm
.opcode_modifier
.ignoresize
5467 && i
.tm
.opcode_modifier
.no_qsuf
)
5469 else if (!check_qword_reg ())
5472 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5475 && i
.tm
.opcode_modifier
.ignoresize
5476 && i
.tm
.opcode_modifier
.no_wsuf
)
5478 else if (!check_word_reg ())
5481 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5482 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5483 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5485 /* Skip if the instruction has x/y/z suffix. match_template
5486 should check if it is a valid suffix. */
5488 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5489 /* Do nothing if the instruction is going to ignore the prefix. */
5494 else if (i
.tm
.opcode_modifier
.defaultsize
5496 /* exclude fldenv/frstor/fsave/fstenv */
5497 && i
.tm
.opcode_modifier
.no_ssuf
)
5499 i
.suffix
= stackop_size
;
5501 else if (intel_syntax
5503 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5504 || i
.tm
.opcode_modifier
.jumpbyte
5505 || i
.tm
.opcode_modifier
.jumpintersegment
5506 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5507 && i
.tm
.extension_opcode
<= 3)))
5512 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5514 i
.suffix
= QWORD_MNEM_SUFFIX
;
5519 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5520 i
.suffix
= LONG_MNEM_SUFFIX
;
5523 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5524 i
.suffix
= WORD_MNEM_SUFFIX
;
5533 if (i
.tm
.opcode_modifier
.w
)
5535 as_bad (_("no instruction mnemonic suffix given and "
5536 "no register operands; can't size instruction"));
5542 unsigned int suffixes
;
5544 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5545 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5547 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5549 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5551 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5553 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5556 /* There are more than suffix matches. */
5557 if (i
.tm
.opcode_modifier
.w
5558 || ((suffixes
& (suffixes
- 1))
5559 && !i
.tm
.opcode_modifier
.defaultsize
5560 && !i
.tm
.opcode_modifier
.ignoresize
))
5562 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5568 /* Change the opcode based on the operand size given by i.suffix;
5569 We don't need to change things for byte insns. */
5572 && i
.suffix
!= BYTE_MNEM_SUFFIX
5573 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5574 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5575 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5577 /* It's not a byte, select word/dword operation. */
5578 if (i
.tm
.opcode_modifier
.w
)
5580 if (i
.tm
.opcode_modifier
.shortform
)
5581 i
.tm
.base_opcode
|= 8;
5583 i
.tm
.base_opcode
|= 1;
5586 /* Now select between word & dword operations via the operand
5587 size prefix, except for instructions that will ignore this
5589 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5591 /* The address size override prefix changes the size of the
5593 if ((flag_code
== CODE_32BIT
5594 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5595 || (flag_code
!= CODE_32BIT
5596 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5597 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5600 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5601 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5602 && !i
.tm
.opcode_modifier
.ignoresize
5603 && !i
.tm
.opcode_modifier
.floatmf
5604 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5605 || (flag_code
== CODE_64BIT
5606 && i
.tm
.opcode_modifier
.jumpbyte
)))
5608 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5610 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5611 prefix
= ADDR_PREFIX_OPCODE
;
5613 if (!add_prefix (prefix
))
5617 /* Set mode64 for an operand. */
5618 if (i
.suffix
== QWORD_MNEM_SUFFIX
5619 && flag_code
== CODE_64BIT
5620 && !i
.tm
.opcode_modifier
.norex64
)
5622 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5623 need rex64. cmpxchg8b is also a special case. */
5624 if (! (i
.operands
== 2
5625 && i
.tm
.base_opcode
== 0x90
5626 && i
.tm
.extension_opcode
== None
5627 && operand_type_equal (&i
.types
[0], &acc64
)
5628 && operand_type_equal (&i
.types
[1], &acc64
))
5629 && ! (i
.operands
== 1
5630 && i
.tm
.base_opcode
== 0xfc7
5631 && i
.tm
.extension_opcode
== 1
5632 && !operand_type_check (i
.types
[0], reg
)
5633 && operand_type_check (i
.types
[0], anymem
)))
5637 /* Size floating point instruction. */
5638 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5639 if (i
.tm
.opcode_modifier
.floatmf
)
5640 i
.tm
.base_opcode
^= 4;
5647 check_byte_reg (void)
5651 for (op
= i
.operands
; --op
>= 0;)
5653 /* If this is an eight bit register, it's OK. If it's the 16 or
5654 32 bit version of an eight bit register, we will just use the
5655 low portion, and that's OK too. */
5656 if (i
.types
[op
].bitfield
.reg8
)
5659 /* I/O port address operands are OK too. */
5660 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5663 /* crc32 doesn't generate this warning. */
5664 if (i
.tm
.base_opcode
== 0xf20f38f0)
5667 if ((i
.types
[op
].bitfield
.reg16
5668 || i
.types
[op
].bitfield
.reg32
5669 || i
.types
[op
].bitfield
.reg64
)
5670 && i
.op
[op
].regs
->reg_num
< 4
5671 /* Prohibit these changes in 64bit mode, since the lowering
5672 would be more complicated. */
5673 && flag_code
!= CODE_64BIT
)
5675 #if REGISTER_WARNINGS
5676 if (!quiet_warnings
)
5677 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5679 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5680 ? REGNAM_AL
- REGNAM_AX
5681 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5683 i
.op
[op
].regs
->reg_name
,
5688 /* Any other register is bad. */
5689 if (i
.types
[op
].bitfield
.reg16
5690 || i
.types
[op
].bitfield
.reg32
5691 || i
.types
[op
].bitfield
.reg64
5692 || i
.types
[op
].bitfield
.regmmx
5693 || i
.types
[op
].bitfield
.regxmm
5694 || i
.types
[op
].bitfield
.regymm
5695 || i
.types
[op
].bitfield
.regzmm
5696 || i
.types
[op
].bitfield
.sreg2
5697 || i
.types
[op
].bitfield
.sreg3
5698 || i
.types
[op
].bitfield
.control
5699 || i
.types
[op
].bitfield
.debug
5700 || i
.types
[op
].bitfield
.test
5701 || i
.types
[op
].bitfield
.floatreg
5702 || i
.types
[op
].bitfield
.floatacc
)
5704 as_bad (_("`%s%s' not allowed with `%s%c'"),
5706 i
.op
[op
].regs
->reg_name
,
5716 check_long_reg (void)
5720 for (op
= i
.operands
; --op
>= 0;)
5721 /* Reject eight bit registers, except where the template requires
5722 them. (eg. movzb) */
5723 if (i
.types
[op
].bitfield
.reg8
5724 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5725 || i
.tm
.operand_types
[op
].bitfield
.reg32
5726 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5728 as_bad (_("`%s%s' not allowed with `%s%c'"),
5730 i
.op
[op
].regs
->reg_name
,
5735 /* Warn if the e prefix on a general reg is missing. */
5736 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5737 && i
.types
[op
].bitfield
.reg16
5738 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5739 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5741 /* Prohibit these changes in the 64bit mode, since the
5742 lowering is more complicated. */
5743 if (flag_code
== CODE_64BIT
)
5745 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5746 register_prefix
, i
.op
[op
].regs
->reg_name
,
5750 #if REGISTER_WARNINGS
5751 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5753 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5754 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5757 /* Warn if the r prefix on a general reg is present. */
5758 else if (i
.types
[op
].bitfield
.reg64
5759 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5760 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5763 && i
.tm
.opcode_modifier
.toqword
5764 && !i
.types
[0].bitfield
.regxmm
)
5766 /* Convert to QWORD. We want REX byte. */
5767 i
.suffix
= QWORD_MNEM_SUFFIX
;
5771 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5772 register_prefix
, i
.op
[op
].regs
->reg_name
,
5781 check_qword_reg (void)
5785 for (op
= i
.operands
; --op
>= 0; )
5786 /* Reject eight bit registers, except where the template requires
5787 them. (eg. movzb) */
5788 if (i
.types
[op
].bitfield
.reg8
5789 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5790 || i
.tm
.operand_types
[op
].bitfield
.reg32
5791 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5793 as_bad (_("`%s%s' not allowed with `%s%c'"),
5795 i
.op
[op
].regs
->reg_name
,
5800 /* Warn if the r prefix on a general reg is missing. */
5801 else if ((i
.types
[op
].bitfield
.reg16
5802 || i
.types
[op
].bitfield
.reg32
)
5803 && (i
.tm
.operand_types
[op
].bitfield
.reg64
5804 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5806 /* Prohibit these changes in the 64bit mode, since the
5807 lowering is more complicated. */
5809 && i
.tm
.opcode_modifier
.todword
5810 && !i
.types
[0].bitfield
.regxmm
)
5812 /* Convert to DWORD. We don't want REX byte. */
5813 i
.suffix
= LONG_MNEM_SUFFIX
;
5817 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5818 register_prefix
, i
.op
[op
].regs
->reg_name
,
5827 check_word_reg (void)
5830 for (op
= i
.operands
; --op
>= 0;)
5831 /* Reject eight bit registers, except where the template requires
5832 them. (eg. movzb) */
5833 if (i
.types
[op
].bitfield
.reg8
5834 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5835 || i
.tm
.operand_types
[op
].bitfield
.reg32
5836 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5838 as_bad (_("`%s%s' not allowed with `%s%c'"),
5840 i
.op
[op
].regs
->reg_name
,
5845 /* Warn if the e or r prefix on a general reg is present. */
5846 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5847 && (i
.types
[op
].bitfield
.reg32
5848 || i
.types
[op
].bitfield
.reg64
)
5849 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5850 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5852 /* Prohibit these changes in the 64bit mode, since the
5853 lowering is more complicated. */
5854 if (flag_code
== CODE_64BIT
)
5856 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5857 register_prefix
, i
.op
[op
].regs
->reg_name
,
5861 #if REGISTER_WARNINGS
5862 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5864 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5865 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5872 update_imm (unsigned int j
)
5874 i386_operand_type overlap
= i
.types
[j
];
5875 if ((overlap
.bitfield
.imm8
5876 || overlap
.bitfield
.imm8s
5877 || overlap
.bitfield
.imm16
5878 || overlap
.bitfield
.imm32
5879 || overlap
.bitfield
.imm32s
5880 || overlap
.bitfield
.imm64
)
5881 && !operand_type_equal (&overlap
, &imm8
)
5882 && !operand_type_equal (&overlap
, &imm8s
)
5883 && !operand_type_equal (&overlap
, &imm16
)
5884 && !operand_type_equal (&overlap
, &imm32
)
5885 && !operand_type_equal (&overlap
, &imm32s
)
5886 && !operand_type_equal (&overlap
, &imm64
))
5890 i386_operand_type temp
;
5892 operand_type_set (&temp
, 0);
5893 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5895 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5896 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5898 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5899 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5900 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5902 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5903 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5906 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5909 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5910 || operand_type_equal (&overlap
, &imm16_32
)
5911 || operand_type_equal (&overlap
, &imm16_32s
))
5913 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5918 if (!operand_type_equal (&overlap
, &imm8
)
5919 && !operand_type_equal (&overlap
, &imm8s
)
5920 && !operand_type_equal (&overlap
, &imm16
)
5921 && !operand_type_equal (&overlap
, &imm32
)
5922 && !operand_type_equal (&overlap
, &imm32s
)
5923 && !operand_type_equal (&overlap
, &imm64
))
5925 as_bad (_("no instruction mnemonic suffix given; "
5926 "can't determine immediate size"));
5930 i
.types
[j
] = overlap
;
5940 /* Update the first 2 immediate operands. */
5941 n
= i
.operands
> 2 ? 2 : i
.operands
;
5944 for (j
= 0; j
< n
; j
++)
5945 if (update_imm (j
) == 0)
5948 /* The 3rd operand can't be immediate operand. */
5949 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5956 bad_implicit_operand (int xmm
)
5958 const char *ireg
= xmm
? "xmm0" : "ymm0";
5961 as_bad (_("the last operand of `%s' must be `%s%s'"),
5962 i
.tm
.name
, register_prefix
, ireg
);
5964 as_bad (_("the first operand of `%s' must be `%s%s'"),
5965 i
.tm
.name
, register_prefix
, ireg
);
5970 process_operands (void)
5972 /* Default segment register this instruction will use for memory
5973 accesses. 0 means unknown. This is only for optimizing out
5974 unnecessary segment overrides. */
5975 const seg_entry
*default_seg
= 0;
5977 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5979 unsigned int dupl
= i
.operands
;
5980 unsigned int dest
= dupl
- 1;
5983 /* The destination must be an xmm register. */
5984 gas_assert (i
.reg_operands
5985 && MAX_OPERANDS
> dupl
5986 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5988 if (i
.tm
.opcode_modifier
.firstxmm0
)
5990 /* The first operand is implicit and must be xmm0. */
5991 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5992 if (register_number (i
.op
[0].regs
) != 0)
5993 return bad_implicit_operand (1);
5995 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5997 /* Keep xmm0 for instructions with VEX prefix and 3
6003 /* We remove the first xmm0 and keep the number of
6004 operands unchanged, which in fact duplicates the
6006 for (j
= 1; j
< i
.operands
; j
++)
6008 i
.op
[j
- 1] = i
.op
[j
];
6009 i
.types
[j
- 1] = i
.types
[j
];
6010 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6014 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6016 gas_assert ((MAX_OPERANDS
- 1) > dupl
6017 && (i
.tm
.opcode_modifier
.vexsources
6020 /* Add the implicit xmm0 for instructions with VEX prefix
6022 for (j
= i
.operands
; j
> 0; j
--)
6024 i
.op
[j
] = i
.op
[j
- 1];
6025 i
.types
[j
] = i
.types
[j
- 1];
6026 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6029 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6030 i
.types
[0] = regxmm
;
6031 i
.tm
.operand_types
[0] = regxmm
;
6034 i
.reg_operands
+= 2;
6039 i
.op
[dupl
] = i
.op
[dest
];
6040 i
.types
[dupl
] = i
.types
[dest
];
6041 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6050 i
.op
[dupl
] = i
.op
[dest
];
6051 i
.types
[dupl
] = i
.types
[dest
];
6052 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6055 if (i
.tm
.opcode_modifier
.immext
)
6058 else if (i
.tm
.opcode_modifier
.firstxmm0
)
6062 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
6063 gas_assert (i
.reg_operands
6064 && (operand_type_equal (&i
.types
[0], ®xmm
)
6065 || operand_type_equal (&i
.types
[0], ®ymm
)
6066 || operand_type_equal (&i
.types
[0], ®zmm
)));
6067 if (register_number (i
.op
[0].regs
) != 0)
6068 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
6070 for (j
= 1; j
< i
.operands
; j
++)
6072 i
.op
[j
- 1] = i
.op
[j
];
6073 i
.types
[j
- 1] = i
.types
[j
];
6075 /* We need to adjust fields in i.tm since they are used by
6076 build_modrm_byte. */
6077 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6084 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6086 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6087 gas_assert (i
.operands
>= 2
6088 && (operand_type_equal (&i
.types
[1], ®xmm
)
6089 || operand_type_equal (&i
.types
[1], ®ymm
)
6090 || operand_type_equal (&i
.types
[1], ®zmm
)));
6091 unsigned int regnum
= register_number (i
.op
[1].regs
);
6092 unsigned int first_reg_in_group
= regnum
& ~3;
6093 unsigned int last_reg_in_group
= first_reg_in_group
+ 3;
6094 if (regnum
!= first_reg_in_group
) {
6095 as_warn (_("the second source register `%s%s' implicitly denotes"
6096 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
6097 register_prefix
, i
.op
[1].regs
->reg_name
,
6098 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6099 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6103 else if (i
.tm
.opcode_modifier
.regkludge
)
6105 /* The imul $imm, %reg instruction is converted into
6106 imul $imm, %reg, %reg, and the clr %reg instruction
6107 is converted into xor %reg, %reg. */
6109 unsigned int first_reg_op
;
6111 if (operand_type_check (i
.types
[0], reg
))
6115 /* Pretend we saw the extra register operand. */
6116 gas_assert (i
.reg_operands
== 1
6117 && i
.op
[first_reg_op
+ 1].regs
== 0);
6118 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6119 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6124 if (i
.tm
.opcode_modifier
.shortform
)
6126 if (i
.types
[0].bitfield
.sreg2
6127 || i
.types
[0].bitfield
.sreg3
)
6129 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6130 && i
.op
[0].regs
->reg_num
== 1)
6132 as_bad (_("you can't `pop %scs'"), register_prefix
);
6135 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6136 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6141 /* The register or float register operand is in operand
6145 if (i
.types
[0].bitfield
.floatreg
6146 || operand_type_check (i
.types
[0], reg
))
6150 /* Register goes in low 3 bits of opcode. */
6151 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6152 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6154 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6156 /* Warn about some common errors, but press on regardless.
6157 The first case can be generated by gcc (<= 2.8.1). */
6158 if (i
.operands
== 2)
6160 /* Reversed arguments on faddp, fsubp, etc. */
6161 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6162 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6163 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6167 /* Extraneous `l' suffix on fp insn. */
6168 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6169 register_prefix
, i
.op
[0].regs
->reg_name
);
6174 else if (i
.tm
.opcode_modifier
.modrm
)
6176 /* The opcode is completed (modulo i.tm.extension_opcode which
6177 must be put into the modrm byte). Now, we make the modrm and
6178 index base bytes based on all the info we've collected. */
6180 default_seg
= build_modrm_byte ();
6182 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6186 else if (i
.tm
.opcode_modifier
.isstring
)
6188 /* For the string instructions that allow a segment override
6189 on one of their operands, the default segment is ds. */
6193 if (i
.tm
.base_opcode
== 0x8d /* lea */
6196 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6198 /* If a segment was explicitly specified, and the specified segment
6199 is not the default, use an opcode prefix to select it. If we
6200 never figured out what the default segment is, then default_seg
6201 will be zero at this point, and the specified segment prefix will
6203 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6205 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6211 static const seg_entry
*
6212 build_modrm_byte (void)
6214 const seg_entry
*default_seg
= 0;
6215 unsigned int source
, dest
;
6218 /* The first operand of instructions with VEX prefix and 3 sources
6219 must be VEX_Imm4. */
6220 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6223 unsigned int nds
, reg_slot
;
6226 if (i
.tm
.opcode_modifier
.veximmext
6227 && i
.tm
.opcode_modifier
.immext
)
6229 dest
= i
.operands
- 2;
6230 gas_assert (dest
== 3);
6233 dest
= i
.operands
- 1;
6236 /* There are 2 kinds of instructions:
6237 1. 5 operands: 4 register operands or 3 register operands
6238 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6239 VexW0 or VexW1. The destination must be either XMM, YMM or
6241 2. 4 operands: 4 register operands or 3 register operands
6242 plus 1 memory operand, VexXDS, and VexImmExt */
6243 gas_assert ((i
.reg_operands
== 4
6244 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6245 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6246 && (i
.tm
.opcode_modifier
.veximmext
6247 || (i
.imm_operands
== 1
6248 && i
.types
[0].bitfield
.vec_imm4
6249 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
6250 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6251 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
6252 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
6253 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
6255 if (i
.imm_operands
== 0)
6257 /* When there is no immediate operand, generate an 8bit
6258 immediate operand to encode the first operand. */
6259 exp
= &im_expressions
[i
.imm_operands
++];
6260 i
.op
[i
.operands
].imms
= exp
;
6261 i
.types
[i
.operands
] = imm8
;
6263 /* If VexW1 is set, the first operand is the source and
6264 the second operand is encoded in the immediate operand. */
6265 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6276 /* FMA swaps REG and NDS. */
6277 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6285 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6287 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6289 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6291 exp
->X_op
= O_constant
;
6292 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6293 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6297 unsigned int imm_slot
;
6299 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6301 /* If VexW0 is set, the third operand is the source and
6302 the second operand is encoded in the immediate
6309 /* VexW1 is set, the second operand is the source and
6310 the third operand is encoded in the immediate
6316 if (i
.tm
.opcode_modifier
.immext
)
6318 /* When ImmExt is set, the immediate byte is the last
6320 imm_slot
= i
.operands
- 1;
6328 /* Turn on Imm8 so that output_imm will generate it. */
6329 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6332 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6334 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6336 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6338 i
.op
[imm_slot
].imms
->X_add_number
6339 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6340 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6343 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6344 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6346 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6348 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6353 /* i.reg_operands MUST be the number of real register operands;
6354 implicit registers do not count. If there are 3 register
6355 operands, it must be a instruction with VexNDS. For a
6356 instruction with VexNDD, the destination register is encoded
6357 in VEX prefix. If there are 4 register operands, it must be
6358 a instruction with VEX prefix and 3 sources. */
6359 if (i
.mem_operands
== 0
6360 && ((i
.reg_operands
== 2
6361 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6362 || (i
.reg_operands
== 3
6363 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6364 || (i
.reg_operands
== 4 && vex_3_sources
)))
6372 /* When there are 3 operands, one of them may be immediate,
6373 which may be the first or the last operand. Otherwise,
6374 the first operand must be shift count register (cl) or it
6375 is an instruction with VexNDS. */
6376 gas_assert (i
.imm_operands
== 1
6377 || (i
.imm_operands
== 0
6378 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6379 || i
.types
[0].bitfield
.shiftcount
)));
6380 if (operand_type_check (i
.types
[0], imm
)
6381 || i
.types
[0].bitfield
.shiftcount
)
6387 /* When there are 4 operands, the first two must be 8bit
6388 immediate operands. The source operand will be the 3rd
6391 For instructions with VexNDS, if the first operand
6392 an imm8, the source operand is the 2nd one. If the last
6393 operand is imm8, the source operand is the first one. */
6394 gas_assert ((i
.imm_operands
== 2
6395 && i
.types
[0].bitfield
.imm8
6396 && i
.types
[1].bitfield
.imm8
)
6397 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6398 && i
.imm_operands
== 1
6399 && (i
.types
[0].bitfield
.imm8
6400 || i
.types
[i
.operands
- 1].bitfield
.imm8
6402 if (i
.imm_operands
== 2)
6406 if (i
.types
[0].bitfield
.imm8
)
6413 if (i
.tm
.opcode_modifier
.evex
)
6415 /* For EVEX instructions, when there are 5 operands, the
6416 first one must be immediate operand. If the second one
6417 is immediate operand, the source operand is the 3th
6418 one. If the last one is immediate operand, the source
6419 operand is the 2nd one. */
6420 gas_assert (i
.imm_operands
== 2
6421 && i
.tm
.opcode_modifier
.sae
6422 && operand_type_check (i
.types
[0], imm
));
6423 if (operand_type_check (i
.types
[1], imm
))
6425 else if (operand_type_check (i
.types
[4], imm
))
6439 /* RC/SAE operand could be between DEST and SRC. That happens
6440 when one operand is GPR and the other one is XMM/YMM/ZMM
6442 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6445 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6447 /* For instructions with VexNDS, the register-only source
6448 operand must be 32/64bit integer, XMM, YMM or ZMM
6449 register. It is encoded in VEX prefix. We need to
6450 clear RegMem bit before calling operand_type_equal. */
6452 i386_operand_type op
;
6455 /* Check register-only source operand when two source
6456 operands are swapped. */
6457 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6458 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6466 op
= i
.tm
.operand_types
[vvvv
];
6467 op
.bitfield
.regmem
= 0;
6468 if ((dest
+ 1) >= i
.operands
6469 || (!op
.bitfield
.reg32
6470 && op
.bitfield
.reg64
6471 && !operand_type_equal (&op
, ®xmm
)
6472 && !operand_type_equal (&op
, ®ymm
)
6473 && !operand_type_equal (&op
, ®zmm
)
6474 && !operand_type_equal (&op
, ®mask
)))
6476 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6482 /* One of the register operands will be encoded in the i.tm.reg
6483 field, the other in the combined i.tm.mode and i.tm.regmem
6484 fields. If no form of this instruction supports a memory
6485 destination operand, then we assume the source operand may
6486 sometimes be a memory operand and so we need to store the
6487 destination in the i.rm.reg field. */
6488 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6489 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6491 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6492 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6493 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6495 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6497 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6499 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6504 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6505 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6506 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6508 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6510 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6512 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6515 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6517 if (!i
.types
[0].bitfield
.control
6518 && !i
.types
[1].bitfield
.control
)
6520 i
.rex
&= ~(REX_R
| REX_B
);
6521 add_prefix (LOCK_PREFIX_OPCODE
);
6525 { /* If it's not 2 reg operands... */
6530 unsigned int fake_zero_displacement
= 0;
6533 for (op
= 0; op
< i
.operands
; op
++)
6534 if (operand_type_check (i
.types
[op
], anymem
))
6536 gas_assert (op
< i
.operands
);
6538 if (i
.tm
.opcode_modifier
.vecsib
)
6540 if (i
.index_reg
->reg_num
== RegEiz
6541 || i
.index_reg
->reg_num
== RegRiz
)
6544 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6547 i
.sib
.base
= NO_BASE_REGISTER
;
6548 i
.sib
.scale
= i
.log2_scale_factor
;
6549 /* No Vec_Disp8 if there is no base. */
6550 i
.types
[op
].bitfield
.vec_disp8
= 0;
6551 i
.types
[op
].bitfield
.disp8
= 0;
6552 i
.types
[op
].bitfield
.disp16
= 0;
6553 i
.types
[op
].bitfield
.disp64
= 0;
6554 if (flag_code
!= CODE_64BIT
)
6556 /* Must be 32 bit */
6557 i
.types
[op
].bitfield
.disp32
= 1;
6558 i
.types
[op
].bitfield
.disp32s
= 0;
6562 i
.types
[op
].bitfield
.disp32
= 0;
6563 i
.types
[op
].bitfield
.disp32s
= 1;
6566 i
.sib
.index
= i
.index_reg
->reg_num
;
6567 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6569 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6575 if (i
.base_reg
== 0)
6578 if (!i
.disp_operands
)
6580 fake_zero_displacement
= 1;
6581 /* Instructions with VSIB byte need 32bit displacement
6582 if there is no base register. */
6583 if (i
.tm
.opcode_modifier
.vecsib
)
6584 i
.types
[op
].bitfield
.disp32
= 1;
6586 if (i
.index_reg
== 0)
6588 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6589 /* Operand is just <disp> */
6590 if (flag_code
== CODE_64BIT
)
6592 /* 64bit mode overwrites the 32bit absolute
6593 addressing by RIP relative addressing and
6594 absolute addressing is encoded by one of the
6595 redundant SIB forms. */
6596 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6597 i
.sib
.base
= NO_BASE_REGISTER
;
6598 i
.sib
.index
= NO_INDEX_REGISTER
;
6599 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6600 ? disp32s
: disp32
);
6602 else if ((flag_code
== CODE_16BIT
)
6603 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6605 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6606 i
.types
[op
] = disp16
;
6610 i
.rm
.regmem
= NO_BASE_REGISTER
;
6611 i
.types
[op
] = disp32
;
6614 else if (!i
.tm
.opcode_modifier
.vecsib
)
6616 /* !i.base_reg && i.index_reg */
6617 if (i
.index_reg
->reg_num
== RegEiz
6618 || i
.index_reg
->reg_num
== RegRiz
)
6619 i
.sib
.index
= NO_INDEX_REGISTER
;
6621 i
.sib
.index
= i
.index_reg
->reg_num
;
6622 i
.sib
.base
= NO_BASE_REGISTER
;
6623 i
.sib
.scale
= i
.log2_scale_factor
;
6624 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6625 /* No Vec_Disp8 if there is no base. */
6626 i
.types
[op
].bitfield
.vec_disp8
= 0;
6627 i
.types
[op
].bitfield
.disp8
= 0;
6628 i
.types
[op
].bitfield
.disp16
= 0;
6629 i
.types
[op
].bitfield
.disp64
= 0;
6630 if (flag_code
!= CODE_64BIT
)
6632 /* Must be 32 bit */
6633 i
.types
[op
].bitfield
.disp32
= 1;
6634 i
.types
[op
].bitfield
.disp32s
= 0;
6638 i
.types
[op
].bitfield
.disp32
= 0;
6639 i
.types
[op
].bitfield
.disp32s
= 1;
6641 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6645 /* RIP addressing for 64bit mode. */
6646 else if (i
.base_reg
->reg_num
== RegRip
||
6647 i
.base_reg
->reg_num
== RegEip
)
6649 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6650 i
.rm
.regmem
= NO_BASE_REGISTER
;
6651 i
.types
[op
].bitfield
.disp8
= 0;
6652 i
.types
[op
].bitfield
.disp16
= 0;
6653 i
.types
[op
].bitfield
.disp32
= 0;
6654 i
.types
[op
].bitfield
.disp32s
= 1;
6655 i
.types
[op
].bitfield
.disp64
= 0;
6656 i
.types
[op
].bitfield
.vec_disp8
= 0;
6657 i
.flags
[op
] |= Operand_PCrel
;
6658 if (! i
.disp_operands
)
6659 fake_zero_displacement
= 1;
6661 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6663 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6664 switch (i
.base_reg
->reg_num
)
6667 if (i
.index_reg
== 0)
6669 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6670 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6674 if (i
.index_reg
== 0)
6677 if (operand_type_check (i
.types
[op
], disp
) == 0)
6679 /* fake (%bp) into 0(%bp) */
6680 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6681 i
.types
[op
].bitfield
.vec_disp8
= 1;
6683 i
.types
[op
].bitfield
.disp8
= 1;
6684 fake_zero_displacement
= 1;
6687 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6688 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6690 default: /* (%si) -> 4 or (%di) -> 5 */
6691 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6693 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6695 else /* i.base_reg and 32/64 bit mode */
6697 if (flag_code
== CODE_64BIT
6698 && operand_type_check (i
.types
[op
], disp
))
6700 i386_operand_type temp
;
6701 operand_type_set (&temp
, 0);
6702 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6703 temp
.bitfield
.vec_disp8
6704 = i
.types
[op
].bitfield
.vec_disp8
;
6706 if (i
.prefix
[ADDR_PREFIX
] == 0)
6707 i
.types
[op
].bitfield
.disp32s
= 1;
6709 i
.types
[op
].bitfield
.disp32
= 1;
6712 if (!i
.tm
.opcode_modifier
.vecsib
)
6713 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6714 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6716 i
.sib
.base
= i
.base_reg
->reg_num
;
6717 /* x86-64 ignores REX prefix bit here to avoid decoder
6719 if (!(i
.base_reg
->reg_flags
& RegRex
)
6720 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6721 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6723 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6725 fake_zero_displacement
= 1;
6726 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6727 i
.types
[op
].bitfield
.vec_disp8
= 1;
6729 i
.types
[op
].bitfield
.disp8
= 1;
6731 i
.sib
.scale
= i
.log2_scale_factor
;
6732 if (i
.index_reg
== 0)
6734 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6735 /* <disp>(%esp) becomes two byte modrm with no index
6736 register. We've already stored the code for esp
6737 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6738 Any base register besides %esp will not use the
6739 extra modrm byte. */
6740 i
.sib
.index
= NO_INDEX_REGISTER
;
6742 else if (!i
.tm
.opcode_modifier
.vecsib
)
6744 if (i
.index_reg
->reg_num
== RegEiz
6745 || i
.index_reg
->reg_num
== RegRiz
)
6746 i
.sib
.index
= NO_INDEX_REGISTER
;
6748 i
.sib
.index
= i
.index_reg
->reg_num
;
6749 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6750 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6755 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6756 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6760 if (!fake_zero_displacement
6764 fake_zero_displacement
= 1;
6765 if (i
.disp_encoding
== disp_encoding_8bit
)
6766 i
.types
[op
].bitfield
.disp8
= 1;
6768 i
.types
[op
].bitfield
.disp32
= 1;
6770 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6774 if (fake_zero_displacement
)
6776 /* Fakes a zero displacement assuming that i.types[op]
6777 holds the correct displacement size. */
6780 gas_assert (i
.op
[op
].disps
== 0);
6781 exp
= &disp_expressions
[i
.disp_operands
++];
6782 i
.op
[op
].disps
= exp
;
6783 exp
->X_op
= O_constant
;
6784 exp
->X_add_number
= 0;
6785 exp
->X_add_symbol
= (symbolS
*) 0;
6786 exp
->X_op_symbol
= (symbolS
*) 0;
6794 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6796 if (operand_type_check (i
.types
[0], imm
))
6797 i
.vex
.register_specifier
= NULL
;
6800 /* VEX.vvvv encodes one of the sources when the first
6801 operand is not an immediate. */
6802 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6803 i
.vex
.register_specifier
= i
.op
[0].regs
;
6805 i
.vex
.register_specifier
= i
.op
[1].regs
;
6808 /* Destination is a XMM register encoded in the ModRM.reg
6810 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6811 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6814 /* ModRM.rm and VEX.B encodes the other source. */
6815 if (!i
.mem_operands
)
6819 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6820 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6822 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6824 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6828 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6830 i
.vex
.register_specifier
= i
.op
[2].regs
;
6831 if (!i
.mem_operands
)
6834 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6835 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6839 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6840 (if any) based on i.tm.extension_opcode. Again, we must be
6841 careful to make sure that segment/control/debug/test/MMX
6842 registers are coded into the i.rm.reg field. */
6843 else if (i
.reg_operands
)
6846 unsigned int vex_reg
= ~0;
6848 for (op
= 0; op
< i
.operands
; op
++)
6849 if (i
.types
[op
].bitfield
.reg8
6850 || i
.types
[op
].bitfield
.reg16
6851 || i
.types
[op
].bitfield
.reg32
6852 || i
.types
[op
].bitfield
.reg64
6853 || i
.types
[op
].bitfield
.regmmx
6854 || i
.types
[op
].bitfield
.regxmm
6855 || i
.types
[op
].bitfield
.regymm
6856 || i
.types
[op
].bitfield
.regbnd
6857 || i
.types
[op
].bitfield
.regzmm
6858 || i
.types
[op
].bitfield
.regmask
6859 || i
.types
[op
].bitfield
.sreg2
6860 || i
.types
[op
].bitfield
.sreg3
6861 || i
.types
[op
].bitfield
.control
6862 || i
.types
[op
].bitfield
.debug
6863 || i
.types
[op
].bitfield
.test
)
6868 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6870 /* For instructions with VexNDS, the register-only
6871 source operand is encoded in VEX prefix. */
6872 gas_assert (mem
!= (unsigned int) ~0);
6877 gas_assert (op
< i
.operands
);
6881 /* Check register-only source operand when two source
6882 operands are swapped. */
6883 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6884 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6888 gas_assert (mem
== (vex_reg
+ 1)
6889 && op
< i
.operands
);
6894 gas_assert (vex_reg
< i
.operands
);
6898 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6900 /* For instructions with VexNDD, the register destination
6901 is encoded in VEX prefix. */
6902 if (i
.mem_operands
== 0)
6904 /* There is no memory operand. */
6905 gas_assert ((op
+ 2) == i
.operands
);
6910 /* There are only 2 operands. */
6911 gas_assert (op
< 2 && i
.operands
== 2);
6916 gas_assert (op
< i
.operands
);
6918 if (vex_reg
!= (unsigned int) ~0)
6920 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6922 if (type
->bitfield
.reg32
!= 1
6923 && type
->bitfield
.reg64
!= 1
6924 && !operand_type_equal (type
, ®xmm
)
6925 && !operand_type_equal (type
, ®ymm
)
6926 && !operand_type_equal (type
, ®zmm
)
6927 && !operand_type_equal (type
, ®mask
))
6930 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6933 /* Don't set OP operand twice. */
6936 /* If there is an extension opcode to put here, the
6937 register number must be put into the regmem field. */
6938 if (i
.tm
.extension_opcode
!= None
)
6940 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6941 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6943 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6948 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6949 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6951 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6956 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6957 must set it to 3 to indicate this is a register operand
6958 in the regmem field. */
6959 if (!i
.mem_operands
)
6963 /* Fill in i.rm.reg field with extension opcode (if any). */
6964 if (i
.tm
.extension_opcode
!= None
)
6965 i
.rm
.reg
= i
.tm
.extension_opcode
;
6971 output_branch (void)
6977 relax_substateT subtype
;
6981 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6982 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6985 if (i
.prefix
[DATA_PREFIX
] != 0)
6991 /* Pentium4 branch hints. */
6992 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6993 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6998 if (i
.prefix
[REX_PREFIX
] != 0)
7004 /* BND prefixed jump. */
7005 if (i
.prefix
[BND_PREFIX
] != 0)
7007 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7011 if (i
.prefixes
!= 0 && !intel_syntax
)
7012 as_warn (_("skipping prefixes on this instruction"));
7014 /* It's always a symbol; End frag & setup for relax.
7015 Make sure there is enough room in this frag for the largest
7016 instruction we may generate in md_convert_frag. This is 2
7017 bytes for the opcode and room for the prefix and largest
7019 frag_grow (prefix
+ 2 + 4);
7020 /* Prefix and 1 opcode byte go in fr_fix. */
7021 p
= frag_more (prefix
+ 1);
7022 if (i
.prefix
[DATA_PREFIX
] != 0)
7023 *p
++ = DATA_PREFIX_OPCODE
;
7024 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7025 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7026 *p
++ = i
.prefix
[SEG_PREFIX
];
7027 if (i
.prefix
[REX_PREFIX
] != 0)
7028 *p
++ = i
.prefix
[REX_PREFIX
];
7029 *p
= i
.tm
.base_opcode
;
7031 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7032 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7033 else if (cpu_arch_flags
.bitfield
.cpui386
)
7034 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7036 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7039 sym
= i
.op
[0].disps
->X_add_symbol
;
7040 off
= i
.op
[0].disps
->X_add_number
;
7042 if (i
.op
[0].disps
->X_op
!= O_constant
7043 && i
.op
[0].disps
->X_op
!= O_symbol
)
7045 /* Handle complex expressions. */
7046 sym
= make_expr_symbol (i
.op
[0].disps
);
7050 /* 1 possible extra opcode + 4 byte displacement go in var part.
7051 Pass reloc in fr_var. */
7052 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7062 if (i
.tm
.opcode_modifier
.jumpbyte
)
7064 /* This is a loop or jecxz type instruction. */
7066 if (i
.prefix
[ADDR_PREFIX
] != 0)
7068 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7071 /* Pentium4 branch hints. */
7072 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7073 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7075 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7084 if (flag_code
== CODE_16BIT
)
7087 if (i
.prefix
[DATA_PREFIX
] != 0)
7089 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7099 if (i
.prefix
[REX_PREFIX
] != 0)
7101 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7105 /* BND prefixed jump. */
7106 if (i
.prefix
[BND_PREFIX
] != 0)
7108 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7112 if (i
.prefixes
!= 0 && !intel_syntax
)
7113 as_warn (_("skipping prefixes on this instruction"));
7115 p
= frag_more (i
.tm
.opcode_length
+ size
);
7116 switch (i
.tm
.opcode_length
)
7119 *p
++ = i
.tm
.base_opcode
>> 8;
7122 *p
++ = i
.tm
.base_opcode
;
7128 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7129 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
7131 /* All jumps handled here are signed, but don't use a signed limit
7132 check for 32 and 16 bit jumps as we want to allow wrap around at
7133 4G and 64k respectively. */
7135 fixP
->fx_signed
= 1;
7139 output_interseg_jump (void)
7147 if (flag_code
== CODE_16BIT
)
7151 if (i
.prefix
[DATA_PREFIX
] != 0)
7157 if (i
.prefix
[REX_PREFIX
] != 0)
7167 if (i
.prefixes
!= 0 && !intel_syntax
)
7168 as_warn (_("skipping prefixes on this instruction"));
7170 /* 1 opcode; 2 segment; offset */
7171 p
= frag_more (prefix
+ 1 + 2 + size
);
7173 if (i
.prefix
[DATA_PREFIX
] != 0)
7174 *p
++ = DATA_PREFIX_OPCODE
;
7176 if (i
.prefix
[REX_PREFIX
] != 0)
7177 *p
++ = i
.prefix
[REX_PREFIX
];
7179 *p
++ = i
.tm
.base_opcode
;
7180 if (i
.op
[1].imms
->X_op
== O_constant
)
7182 offsetT n
= i
.op
[1].imms
->X_add_number
;
7185 && !fits_in_unsigned_word (n
)
7186 && !fits_in_signed_word (n
))
7188 as_bad (_("16-bit jump out of range"));
7191 md_number_to_chars (p
, n
, size
);
7194 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7195 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7196 if (i
.op
[0].imms
->X_op
!= O_constant
)
7197 as_bad (_("can't handle non absolute segment in `%s'"),
7199 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7205 fragS
*insn_start_frag
;
7206 offsetT insn_start_off
;
7208 /* Tie dwarf2 debug info to the address at the start of the insn.
7209 We can't do this after the insn has been output as the current
7210 frag may have been closed off. eg. by frag_var. */
7211 dwarf2_emit_insn (0);
7213 insn_start_frag
= frag_now
;
7214 insn_start_off
= frag_now_fix ();
7217 if (i
.tm
.opcode_modifier
.jump
)
7219 else if (i
.tm
.opcode_modifier
.jumpbyte
7220 || i
.tm
.opcode_modifier
.jumpdword
)
7222 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7223 output_interseg_jump ();
7226 /* Output normal instructions here. */
7230 unsigned int prefix
;
7233 && i
.tm
.base_opcode
== 0xfae
7235 && i
.imm_operands
== 1
7236 && (i
.op
[0].imms
->X_add_number
== 0xe8
7237 || i
.op
[0].imms
->X_add_number
== 0xf0
7238 || i
.op
[0].imms
->X_add_number
== 0xf8))
7240 /* Encode lfence, mfence, and sfence as
7241 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7242 offsetT val
= 0x240483f0ULL
;
7244 md_number_to_chars (p
, val
, 5);
7248 /* Some processors fail on LOCK prefix. This options makes
7249 assembler ignore LOCK prefix and serves as a workaround. */
7250 if (omit_lock_prefix
)
7252 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7254 i
.prefix
[LOCK_PREFIX
] = 0;
7257 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7258 don't need the explicit prefix. */
7259 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7261 switch (i
.tm
.opcode_length
)
7264 if (i
.tm
.base_opcode
& 0xff000000)
7266 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7271 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7273 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7274 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7277 if (prefix
!= REPE_PREFIX_OPCODE
7278 || (i
.prefix
[REP_PREFIX
]
7279 != REPE_PREFIX_OPCODE
))
7280 add_prefix (prefix
);
7283 add_prefix (prefix
);
7292 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7293 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7294 R_X86_64_GOTTPOFF relocation so that linker can safely
7295 perform IE->LE optimization. */
7296 if (x86_elf_abi
== X86_64_X32_ABI
7298 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7299 && i
.prefix
[REX_PREFIX
] == 0)
7300 add_prefix (REX_OPCODE
);
7303 /* The prefix bytes. */
7304 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7306 FRAG_APPEND_1_CHAR (*q
);
7310 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7315 /* REX byte is encoded in VEX prefix. */
7319 FRAG_APPEND_1_CHAR (*q
);
7322 /* There should be no other prefixes for instructions
7327 /* For EVEX instructions i.vrex should become 0 after
7328 build_evex_prefix. For VEX instructions upper 16 registers
7329 aren't available, so VREX should be 0. */
7332 /* Now the VEX prefix. */
7333 p
= frag_more (i
.vex
.length
);
7334 for (j
= 0; j
< i
.vex
.length
; j
++)
7335 p
[j
] = i
.vex
.bytes
[j
];
7338 /* Now the opcode; be careful about word order here! */
7339 if (i
.tm
.opcode_length
== 1)
7341 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7345 switch (i
.tm
.opcode_length
)
7349 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7350 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7354 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7364 /* Put out high byte first: can't use md_number_to_chars! */
7365 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7366 *p
= i
.tm
.base_opcode
& 0xff;
7369 /* Now the modrm byte and sib byte (if present). */
7370 if (i
.tm
.opcode_modifier
.modrm
)
7372 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7375 /* If i.rm.regmem == ESP (4)
7376 && i.rm.mode != (Register mode)
7378 ==> need second modrm byte. */
7379 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7381 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7382 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7384 | i
.sib
.scale
<< 6));
7387 if (i
.disp_operands
)
7388 output_disp (insn_start_frag
, insn_start_off
);
7391 output_imm (insn_start_frag
, insn_start_off
);
7397 pi ("" /*line*/, &i
);
7399 #endif /* DEBUG386 */
7402 /* Return the size of the displacement operand N. */
7405 disp_size (unsigned int n
)
7409 /* Vec_Disp8 has to be 8bit. */
7410 if (i
.types
[n
].bitfield
.vec_disp8
)
7412 else if (i
.types
[n
].bitfield
.disp64
)
7414 else if (i
.types
[n
].bitfield
.disp8
)
7416 else if (i
.types
[n
].bitfield
.disp16
)
7421 /* Return the size of the immediate operand N. */
7424 imm_size (unsigned int n
)
7427 if (i
.types
[n
].bitfield
.imm64
)
7429 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7431 else if (i
.types
[n
].bitfield
.imm16
)
7437 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7442 for (n
= 0; n
< i
.operands
; n
++)
7444 if (i
.types
[n
].bitfield
.vec_disp8
7445 || operand_type_check (i
.types
[n
], disp
))
7447 if (i
.op
[n
].disps
->X_op
== O_constant
)
7449 int size
= disp_size (n
);
7450 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7452 if (i
.types
[n
].bitfield
.vec_disp8
)
7454 val
= offset_in_range (val
, size
);
7455 p
= frag_more (size
);
7456 md_number_to_chars (p
, val
, size
);
7460 enum bfd_reloc_code_real reloc_type
;
7461 int size
= disp_size (n
);
7462 int sign
= i
.types
[n
].bitfield
.disp32s
;
7463 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7466 /* We can't have 8 bit displacement here. */
7467 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7469 /* The PC relative address is computed relative
7470 to the instruction boundary, so in case immediate
7471 fields follows, we need to adjust the value. */
7472 if (pcrel
&& i
.imm_operands
)
7477 for (n1
= 0; n1
< i
.operands
; n1
++)
7478 if (operand_type_check (i
.types
[n1
], imm
))
7480 /* Only one immediate is allowed for PC
7481 relative address. */
7482 gas_assert (sz
== 0);
7484 i
.op
[n
].disps
->X_add_number
-= sz
;
7486 /* We should find the immediate. */
7487 gas_assert (sz
!= 0);
7490 p
= frag_more (size
);
7491 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7493 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7494 && (((reloc_type
== BFD_RELOC_32
7495 || reloc_type
== BFD_RELOC_X86_64_32S
7496 || (reloc_type
== BFD_RELOC_64
7498 && (i
.op
[n
].disps
->X_op
== O_symbol
7499 || (i
.op
[n
].disps
->X_op
== O_add
7500 && ((symbol_get_value_expression
7501 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7503 || reloc_type
== BFD_RELOC_32_PCREL
))
7507 if (insn_start_frag
== frag_now
)
7508 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7513 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7514 for (fr
= insn_start_frag
->fr_next
;
7515 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7517 add
+= p
- frag_now
->fr_literal
;
7522 reloc_type
= BFD_RELOC_386_GOTPC
;
7523 i
.op
[n
].imms
->X_add_number
+= add
;
7525 else if (reloc_type
== BFD_RELOC_64
)
7526 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7528 /* Don't do the adjustment for x86-64, as there
7529 the pcrel addressing is relative to the _next_
7530 insn, and that is taken care of in other code. */
7531 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7533 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7534 size
, i
.op
[n
].disps
, pcrel
,
7536 /* Check for "call/jmp *mem", "mov mem, %reg",
7537 "test %reg, mem" and "binop mem, %reg" where binop
7538 is one of adc, add, and, cmp, or, sbb, sub, xor
7539 instructions. Always generate R_386_GOT32X for
7540 "sym*GOT" operand in 32-bit mode. */
7541 if ((generate_relax_relocations
7544 && i
.rm
.regmem
== 5))
7546 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7547 && ((i
.operands
== 1
7548 && i
.tm
.base_opcode
== 0xff
7549 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7551 && (i
.tm
.base_opcode
== 0x8b
7552 || i
.tm
.base_opcode
== 0x85
7553 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7557 fixP
->fx_tcbit
= i
.rex
!= 0;
7559 && (i
.base_reg
->reg_num
== RegRip
7560 || i
.base_reg
->reg_num
== RegEip
))
7561 fixP
->fx_tcbit2
= 1;
7564 fixP
->fx_tcbit2
= 1;
7572 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7577 for (n
= 0; n
< i
.operands
; n
++)
7579 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7580 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7583 if (operand_type_check (i
.types
[n
], imm
))
7585 if (i
.op
[n
].imms
->X_op
== O_constant
)
7587 int size
= imm_size (n
);
7590 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7592 p
= frag_more (size
);
7593 md_number_to_chars (p
, val
, size
);
7597 /* Not absolute_section.
7598 Need a 32-bit fixup (don't support 8bit
7599 non-absolute imms). Try to support other
7601 enum bfd_reloc_code_real reloc_type
;
7602 int size
= imm_size (n
);
7605 if (i
.types
[n
].bitfield
.imm32s
7606 && (i
.suffix
== QWORD_MNEM_SUFFIX
7607 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7612 p
= frag_more (size
);
7613 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7615 /* This is tough to explain. We end up with this one if we
7616 * have operands that look like
7617 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7618 * obtain the absolute address of the GOT, and it is strongly
7619 * preferable from a performance point of view to avoid using
7620 * a runtime relocation for this. The actual sequence of
7621 * instructions often look something like:
7626 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7628 * The call and pop essentially return the absolute address
7629 * of the label .L66 and store it in %ebx. The linker itself
7630 * will ultimately change the first operand of the addl so
7631 * that %ebx points to the GOT, but to keep things simple, the
7632 * .o file must have this operand set so that it generates not
7633 * the absolute address of .L66, but the absolute address of
7634 * itself. This allows the linker itself simply treat a GOTPC
7635 * relocation as asking for a pcrel offset to the GOT to be
7636 * added in, and the addend of the relocation is stored in the
7637 * operand field for the instruction itself.
7639 * Our job here is to fix the operand so that it would add
7640 * the correct offset so that %ebx would point to itself. The
7641 * thing that is tricky is that .-.L66 will point to the
7642 * beginning of the instruction, so we need to further modify
7643 * the operand so that it will point to itself. There are
7644 * other cases where you have something like:
7646 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7648 * and here no correction would be required. Internally in
7649 * the assembler we treat operands of this form as not being
7650 * pcrel since the '.' is explicitly mentioned, and I wonder
7651 * whether it would simplify matters to do it this way. Who
7652 * knows. In earlier versions of the PIC patches, the
7653 * pcrel_adjust field was used to store the correction, but
7654 * since the expression is not pcrel, I felt it would be
7655 * confusing to do it this way. */
7657 if ((reloc_type
== BFD_RELOC_32
7658 || reloc_type
== BFD_RELOC_X86_64_32S
7659 || reloc_type
== BFD_RELOC_64
)
7661 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7662 && (i
.op
[n
].imms
->X_op
== O_symbol
7663 || (i
.op
[n
].imms
->X_op
== O_add
7664 && ((symbol_get_value_expression
7665 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7670 if (insn_start_frag
== frag_now
)
7671 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7676 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7677 for (fr
= insn_start_frag
->fr_next
;
7678 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7680 add
+= p
- frag_now
->fr_literal
;
7684 reloc_type
= BFD_RELOC_386_GOTPC
;
7686 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7688 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7689 i
.op
[n
].imms
->X_add_number
+= add
;
7691 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7692 i
.op
[n
].imms
, 0, reloc_type
);
7698 /* x86_cons_fix_new is called via the expression parsing code when a
7699 reloc is needed. We use this hook to get the correct .got reloc. */
7700 static int cons_sign
= -1;
7703 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7704 expressionS
*exp
, bfd_reloc_code_real_type r
)
7706 r
= reloc (len
, 0, cons_sign
, r
);
7709 if (exp
->X_op
== O_secrel
)
7711 exp
->X_op
= O_symbol
;
7712 r
= BFD_RELOC_32_SECREL
;
7716 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7719 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7720 purpose of the `.dc.a' internal pseudo-op. */
7723 x86_address_bytes (void)
7725 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7727 return stdoutput
->arch_info
->bits_per_address
/ 8;
7730 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7732 # define lex_got(reloc, adjust, types) NULL
7734 /* Parse operands of the form
7735 <symbol>@GOTOFF+<nnn>
7736 and similar .plt or .got references.
7738 If we find one, set up the correct relocation in RELOC and copy the
7739 input string, minus the `@GOTOFF' into a malloc'd buffer for
7740 parsing by the calling routine. Return this buffer, and if ADJUST
7741 is non-null set it to the length of the string we removed from the
7742 input line. Otherwise return NULL. */
7744 lex_got (enum bfd_reloc_code_real
*rel
,
7746 i386_operand_type
*types
)
7748 /* Some of the relocations depend on the size of what field is to
7749 be relocated. But in our callers i386_immediate and i386_displacement
7750 we don't yet know the operand size (this will be set by insn
7751 matching). Hence we record the word32 relocation here,
7752 and adjust the reloc according to the real size in reloc(). */
7753 static const struct {
7756 const enum bfd_reloc_code_real rel
[2];
7757 const i386_operand_type types64
;
7759 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7760 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7762 OPERAND_TYPE_IMM32_64
},
7764 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7765 BFD_RELOC_X86_64_PLTOFF64
},
7766 OPERAND_TYPE_IMM64
},
7767 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7768 BFD_RELOC_X86_64_PLT32
},
7769 OPERAND_TYPE_IMM32_32S_DISP32
},
7770 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7771 BFD_RELOC_X86_64_GOTPLT64
},
7772 OPERAND_TYPE_IMM64_DISP64
},
7773 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7774 BFD_RELOC_X86_64_GOTOFF64
},
7775 OPERAND_TYPE_IMM64_DISP64
},
7776 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7777 BFD_RELOC_X86_64_GOTPCREL
},
7778 OPERAND_TYPE_IMM32_32S_DISP32
},
7779 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7780 BFD_RELOC_X86_64_TLSGD
},
7781 OPERAND_TYPE_IMM32_32S_DISP32
},
7782 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7783 _dummy_first_bfd_reloc_code_real
},
7784 OPERAND_TYPE_NONE
},
7785 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7786 BFD_RELOC_X86_64_TLSLD
},
7787 OPERAND_TYPE_IMM32_32S_DISP32
},
7788 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7789 BFD_RELOC_X86_64_GOTTPOFF
},
7790 OPERAND_TYPE_IMM32_32S_DISP32
},
7791 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7792 BFD_RELOC_X86_64_TPOFF32
},
7793 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7794 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7795 _dummy_first_bfd_reloc_code_real
},
7796 OPERAND_TYPE_NONE
},
7797 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7798 BFD_RELOC_X86_64_DTPOFF32
},
7799 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7800 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7801 _dummy_first_bfd_reloc_code_real
},
7802 OPERAND_TYPE_NONE
},
7803 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7804 _dummy_first_bfd_reloc_code_real
},
7805 OPERAND_TYPE_NONE
},
7806 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7807 BFD_RELOC_X86_64_GOT32
},
7808 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7809 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7810 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7811 OPERAND_TYPE_IMM32_32S_DISP32
},
7812 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7813 BFD_RELOC_X86_64_TLSDESC_CALL
},
7814 OPERAND_TYPE_IMM32_32S_DISP32
},
7819 #if defined (OBJ_MAYBE_ELF)
7824 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7825 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7828 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7830 int len
= gotrel
[j
].len
;
7831 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7833 if (gotrel
[j
].rel
[object_64bit
] != 0)
7836 char *tmpbuf
, *past_reloc
;
7838 *rel
= gotrel
[j
].rel
[object_64bit
];
7842 if (flag_code
!= CODE_64BIT
)
7844 types
->bitfield
.imm32
= 1;
7845 types
->bitfield
.disp32
= 1;
7848 *types
= gotrel
[j
].types64
;
7851 if (j
!= 0 && GOT_symbol
== NULL
)
7852 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7854 /* The length of the first part of our input line. */
7855 first
= cp
- input_line_pointer
;
7857 /* The second part goes from after the reloc token until
7858 (and including) an end_of_line char or comma. */
7859 past_reloc
= cp
+ 1 + len
;
7861 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7863 second
= cp
+ 1 - past_reloc
;
7865 /* Allocate and copy string. The trailing NUL shouldn't
7866 be necessary, but be safe. */
7867 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7868 memcpy (tmpbuf
, input_line_pointer
, first
);
7869 if (second
!= 0 && *past_reloc
!= ' ')
7870 /* Replace the relocation token with ' ', so that
7871 errors like foo@GOTOFF1 will be detected. */
7872 tmpbuf
[first
++] = ' ';
7874 /* Increment length by 1 if the relocation token is
7879 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7880 tmpbuf
[first
+ second
] = '\0';
7884 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7885 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7890 /* Might be a symbol version string. Don't as_bad here. */
7899 /* Parse operands of the form
7900 <symbol>@SECREL32+<nnn>
7902 If we find one, set up the correct relocation in RELOC and copy the
7903 input string, minus the `@SECREL32' into a malloc'd buffer for
7904 parsing by the calling routine. Return this buffer, and if ADJUST
7905 is non-null set it to the length of the string we removed from the
7906 input line. Otherwise return NULL.
7908 This function is copied from the ELF version above adjusted for PE targets. */
7911 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7912 int *adjust ATTRIBUTE_UNUSED
,
7913 i386_operand_type
*types
)
7919 const enum bfd_reloc_code_real rel
[2];
7920 const i386_operand_type types64
;
7924 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7925 BFD_RELOC_32_SECREL
},
7926 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7932 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7933 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7936 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7938 int len
= gotrel
[j
].len
;
7940 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7942 if (gotrel
[j
].rel
[object_64bit
] != 0)
7945 char *tmpbuf
, *past_reloc
;
7947 *rel
= gotrel
[j
].rel
[object_64bit
];
7953 if (flag_code
!= CODE_64BIT
)
7955 types
->bitfield
.imm32
= 1;
7956 types
->bitfield
.disp32
= 1;
7959 *types
= gotrel
[j
].types64
;
7962 /* The length of the first part of our input line. */
7963 first
= cp
- input_line_pointer
;
7965 /* The second part goes from after the reloc token until
7966 (and including) an end_of_line char or comma. */
7967 past_reloc
= cp
+ 1 + len
;
7969 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7971 second
= cp
+ 1 - past_reloc
;
7973 /* Allocate and copy string. The trailing NUL shouldn't
7974 be necessary, but be safe. */
7975 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7976 memcpy (tmpbuf
, input_line_pointer
, first
);
7977 if (second
!= 0 && *past_reloc
!= ' ')
7978 /* Replace the relocation token with ' ', so that
7979 errors like foo@SECLREL321 will be detected. */
7980 tmpbuf
[first
++] = ' ';
7981 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7982 tmpbuf
[first
+ second
] = '\0';
7986 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7987 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7992 /* Might be a symbol version string. Don't as_bad here. */
7998 bfd_reloc_code_real_type
7999 x86_cons (expressionS
*exp
, int size
)
8001 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
8003 intel_syntax
= -intel_syntax
;
8006 if (size
== 4 || (object_64bit
&& size
== 8))
8008 /* Handle @GOTOFF and the like in an expression. */
8010 char *gotfree_input_line
;
8013 save
= input_line_pointer
;
8014 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
8015 if (gotfree_input_line
)
8016 input_line_pointer
= gotfree_input_line
;
8020 if (gotfree_input_line
)
8022 /* expression () has merrily parsed up to the end of line,
8023 or a comma - in the wrong buffer. Transfer how far
8024 input_line_pointer has moved to the right buffer. */
8025 input_line_pointer
= (save
8026 + (input_line_pointer
- gotfree_input_line
)
8028 free (gotfree_input_line
);
8029 if (exp
->X_op
== O_constant
8030 || exp
->X_op
== O_absent
8031 || exp
->X_op
== O_illegal
8032 || exp
->X_op
== O_register
8033 || exp
->X_op
== O_big
)
8035 char c
= *input_line_pointer
;
8036 *input_line_pointer
= 0;
8037 as_bad (_("missing or invalid expression `%s'"), save
);
8038 *input_line_pointer
= c
;
8045 intel_syntax
= -intel_syntax
;
8048 i386_intel_simplify (exp
);
8054 signed_cons (int size
)
8056 if (flag_code
== CODE_64BIT
)
8064 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
8071 if (exp
.X_op
== O_symbol
)
8072 exp
.X_op
= O_secrel
;
8074 emit_expr (&exp
, 4);
8076 while (*input_line_pointer
++ == ',');
8078 input_line_pointer
--;
8079 demand_empty_rest_of_line ();
8083 /* Handle Vector operations. */
8086 check_VecOperations (char *op_string
, char *op_end
)
8088 const reg_entry
*mask
;
8093 && (op_end
== NULL
|| op_string
< op_end
))
8096 if (*op_string
== '{')
8100 /* Check broadcasts. */
8101 if (strncmp (op_string
, "1to", 3) == 0)
8106 goto duplicated_vec_op
;
8109 if (*op_string
== '8')
8110 bcst_type
= BROADCAST_1TO8
;
8111 else if (*op_string
== '4')
8112 bcst_type
= BROADCAST_1TO4
;
8113 else if (*op_string
== '2')
8114 bcst_type
= BROADCAST_1TO2
;
8115 else if (*op_string
== '1'
8116 && *(op_string
+1) == '6')
8118 bcst_type
= BROADCAST_1TO16
;
8123 as_bad (_("Unsupported broadcast: `%s'"), saved
);
8128 broadcast_op
.type
= bcst_type
;
8129 broadcast_op
.operand
= this_operand
;
8130 i
.broadcast
= &broadcast_op
;
8132 /* Check masking operation. */
8133 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
8135 /* k0 can't be used for write mask. */
8136 if (mask
->reg_num
== 0)
8138 as_bad (_("`%s' can't be used for write mask"),
8145 mask_op
.mask
= mask
;
8146 mask_op
.zeroing
= 0;
8147 mask_op
.operand
= this_operand
;
8153 goto duplicated_vec_op
;
8155 i
.mask
->mask
= mask
;
8157 /* Only "{z}" is allowed here. No need to check
8158 zeroing mask explicitly. */
8159 if (i
.mask
->operand
!= this_operand
)
8161 as_bad (_("invalid write mask `%s'"), saved
);
8168 /* Check zeroing-flag for masking operation. */
8169 else if (*op_string
== 'z')
8173 mask_op
.mask
= NULL
;
8174 mask_op
.zeroing
= 1;
8175 mask_op
.operand
= this_operand
;
8180 if (i
.mask
->zeroing
)
8183 as_bad (_("duplicated `%s'"), saved
);
8187 i
.mask
->zeroing
= 1;
8189 /* Only "{%k}" is allowed here. No need to check mask
8190 register explicitly. */
8191 if (i
.mask
->operand
!= this_operand
)
8193 as_bad (_("invalid zeroing-masking `%s'"),
8202 goto unknown_vec_op
;
8204 if (*op_string
!= '}')
8206 as_bad (_("missing `}' in `%s'"), saved
);
8213 /* We don't know this one. */
8214 as_bad (_("unknown vector operation: `%s'"), saved
);
8222 i386_immediate (char *imm_start
)
8224 char *save_input_line_pointer
;
8225 char *gotfree_input_line
;
8228 i386_operand_type types
;
8230 operand_type_set (&types
, ~0);
8232 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8234 as_bad (_("at most %d immediate operands are allowed"),
8235 MAX_IMMEDIATE_OPERANDS
);
8239 exp
= &im_expressions
[i
.imm_operands
++];
8240 i
.op
[this_operand
].imms
= exp
;
8242 if (is_space_char (*imm_start
))
8245 save_input_line_pointer
= input_line_pointer
;
8246 input_line_pointer
= imm_start
;
8248 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8249 if (gotfree_input_line
)
8250 input_line_pointer
= gotfree_input_line
;
8252 exp_seg
= expression (exp
);
8256 /* Handle vector operations. */
8257 if (*input_line_pointer
== '{')
8259 input_line_pointer
= check_VecOperations (input_line_pointer
,
8261 if (input_line_pointer
== NULL
)
8265 if (*input_line_pointer
)
8266 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8268 input_line_pointer
= save_input_line_pointer
;
8269 if (gotfree_input_line
)
8271 free (gotfree_input_line
);
8273 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8274 exp
->X_op
= O_illegal
;
8277 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8281 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8282 i386_operand_type types
, const char *imm_start
)
8284 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8287 as_bad (_("missing or invalid immediate expression `%s'"),
8291 else if (exp
->X_op
== O_constant
)
8293 /* Size it properly later. */
8294 i
.types
[this_operand
].bitfield
.imm64
= 1;
8295 /* If not 64bit, sign extend val. */
8296 if (flag_code
!= CODE_64BIT
8297 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8299 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8301 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8302 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8303 && exp_seg
!= absolute_section
8304 && exp_seg
!= text_section
8305 && exp_seg
!= data_section
8306 && exp_seg
!= bss_section
8307 && exp_seg
!= undefined_section
8308 && !bfd_is_com_section (exp_seg
))
8310 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8314 else if (!intel_syntax
&& exp_seg
== reg_section
)
8317 as_bad (_("illegal immediate register operand %s"), imm_start
);
8322 /* This is an address. The size of the address will be
8323 determined later, depending on destination register,
8324 suffix, or the default for the section. */
8325 i
.types
[this_operand
].bitfield
.imm8
= 1;
8326 i
.types
[this_operand
].bitfield
.imm16
= 1;
8327 i
.types
[this_operand
].bitfield
.imm32
= 1;
8328 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8329 i
.types
[this_operand
].bitfield
.imm64
= 1;
8330 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8338 i386_scale (char *scale
)
8341 char *save
= input_line_pointer
;
8343 input_line_pointer
= scale
;
8344 val
= get_absolute_expression ();
8349 i
.log2_scale_factor
= 0;
8352 i
.log2_scale_factor
= 1;
8355 i
.log2_scale_factor
= 2;
8358 i
.log2_scale_factor
= 3;
8362 char sep
= *input_line_pointer
;
8364 *input_line_pointer
= '\0';
8365 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8367 *input_line_pointer
= sep
;
8368 input_line_pointer
= save
;
8372 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8374 as_warn (_("scale factor of %d without an index register"),
8375 1 << i
.log2_scale_factor
);
8376 i
.log2_scale_factor
= 0;
8378 scale
= input_line_pointer
;
8379 input_line_pointer
= save
;
8384 i386_displacement (char *disp_start
, char *disp_end
)
8388 char *save_input_line_pointer
;
8389 char *gotfree_input_line
;
8391 i386_operand_type bigdisp
, types
= anydisp
;
8394 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8396 as_bad (_("at most %d displacement operands are allowed"),
8397 MAX_MEMORY_OPERANDS
);
8401 operand_type_set (&bigdisp
, 0);
8402 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8403 || (!current_templates
->start
->opcode_modifier
.jump
8404 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8406 bigdisp
.bitfield
.disp32
= 1;
8407 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8408 if (flag_code
== CODE_64BIT
)
8412 bigdisp
.bitfield
.disp32s
= 1;
8413 bigdisp
.bitfield
.disp64
= 1;
8416 else if ((flag_code
== CODE_16BIT
) ^ override
)
8418 bigdisp
.bitfield
.disp32
= 0;
8419 bigdisp
.bitfield
.disp16
= 1;
8424 /* For PC-relative branches, the width of the displacement
8425 is dependent upon data size, not address size. */
8426 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8427 if (flag_code
== CODE_64BIT
)
8429 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8430 bigdisp
.bitfield
.disp16
= 1;
8433 bigdisp
.bitfield
.disp32
= 1;
8434 bigdisp
.bitfield
.disp32s
= 1;
8440 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8442 : LONG_MNEM_SUFFIX
));
8443 bigdisp
.bitfield
.disp32
= 1;
8444 if ((flag_code
== CODE_16BIT
) ^ override
)
8446 bigdisp
.bitfield
.disp32
= 0;
8447 bigdisp
.bitfield
.disp16
= 1;
8451 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8454 exp
= &disp_expressions
[i
.disp_operands
];
8455 i
.op
[this_operand
].disps
= exp
;
8457 save_input_line_pointer
= input_line_pointer
;
8458 input_line_pointer
= disp_start
;
8459 END_STRING_AND_SAVE (disp_end
);
8461 #ifndef GCC_ASM_O_HACK
8462 #define GCC_ASM_O_HACK 0
8465 END_STRING_AND_SAVE (disp_end
+ 1);
8466 if (i
.types
[this_operand
].bitfield
.baseIndex
8467 && displacement_string_end
[-1] == '+')
8469 /* This hack is to avoid a warning when using the "o"
8470 constraint within gcc asm statements.
8473 #define _set_tssldt_desc(n,addr,limit,type) \
8474 __asm__ __volatile__ ( \
8476 "movw %w1,2+%0\n\t" \
8478 "movb %b1,4+%0\n\t" \
8479 "movb %4,5+%0\n\t" \
8480 "movb $0,6+%0\n\t" \
8481 "movb %h1,7+%0\n\t" \
8483 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8485 This works great except that the output assembler ends
8486 up looking a bit weird if it turns out that there is
8487 no offset. You end up producing code that looks like:
8500 So here we provide the missing zero. */
8502 *displacement_string_end
= '0';
8505 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8506 if (gotfree_input_line
)
8507 input_line_pointer
= gotfree_input_line
;
8509 exp_seg
= expression (exp
);
8512 if (*input_line_pointer
)
8513 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8515 RESTORE_END_STRING (disp_end
+ 1);
8517 input_line_pointer
= save_input_line_pointer
;
8518 if (gotfree_input_line
)
8520 free (gotfree_input_line
);
8522 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8523 exp
->X_op
= O_illegal
;
8526 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8528 RESTORE_END_STRING (disp_end
);
8534 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8535 i386_operand_type types
, const char *disp_start
)
8537 i386_operand_type bigdisp
;
8540 /* We do this to make sure that the section symbol is in
8541 the symbol table. We will ultimately change the relocation
8542 to be relative to the beginning of the section. */
8543 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8544 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8545 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8547 if (exp
->X_op
!= O_symbol
)
8550 if (S_IS_LOCAL (exp
->X_add_symbol
)
8551 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8552 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8553 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8554 exp
->X_op
= O_subtract
;
8555 exp
->X_op_symbol
= GOT_symbol
;
8556 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8557 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8558 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8559 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8561 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8564 else if (exp
->X_op
== O_absent
8565 || exp
->X_op
== O_illegal
8566 || exp
->X_op
== O_big
)
8569 as_bad (_("missing or invalid displacement expression `%s'"),
8574 else if (flag_code
== CODE_64BIT
8575 && !i
.prefix
[ADDR_PREFIX
]
8576 && exp
->X_op
== O_constant
)
8578 /* Since displacement is signed extended to 64bit, don't allow
8579 disp32 and turn off disp32s if they are out of range. */
8580 i
.types
[this_operand
].bitfield
.disp32
= 0;
8581 if (!fits_in_signed_long (exp
->X_add_number
))
8583 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8584 if (i
.types
[this_operand
].bitfield
.baseindex
)
8586 as_bad (_("0x%lx out range of signed 32bit displacement"),
8587 (long) exp
->X_add_number
);
8593 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8594 else if (exp
->X_op
!= O_constant
8595 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8596 && exp_seg
!= absolute_section
8597 && exp_seg
!= text_section
8598 && exp_seg
!= data_section
8599 && exp_seg
!= bss_section
8600 && exp_seg
!= undefined_section
8601 && !bfd_is_com_section (exp_seg
))
8603 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8608 /* Check if this is a displacement only operand. */
8609 bigdisp
= i
.types
[this_operand
];
8610 bigdisp
.bitfield
.disp8
= 0;
8611 bigdisp
.bitfield
.disp16
= 0;
8612 bigdisp
.bitfield
.disp32
= 0;
8613 bigdisp
.bitfield
.disp32s
= 0;
8614 bigdisp
.bitfield
.disp64
= 0;
8615 if (operand_type_all_zero (&bigdisp
))
8616 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8622 /* Make sure the memory operand we've been dealt is valid.
8623 Return 1 on success, 0 on a failure. */
8626 i386_index_check (const char *operand_string
)
8628 const char *kind
= "base/index";
8629 enum flag_code addr_mode
;
8631 if (i
.prefix
[ADDR_PREFIX
])
8632 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8635 addr_mode
= flag_code
;
8637 #if INFER_ADDR_PREFIX
8638 if (i
.mem_operands
== 0)
8640 /* Infer address prefix from the first memory operand. */
8641 const reg_entry
*addr_reg
= i
.base_reg
;
8643 if (addr_reg
== NULL
)
8644 addr_reg
= i
.index_reg
;
8648 if (addr_reg
->reg_num
== RegEip
8649 || addr_reg
->reg_num
== RegEiz
8650 || addr_reg
->reg_type
.bitfield
.reg32
)
8651 addr_mode
= CODE_32BIT
;
8652 else if (flag_code
!= CODE_64BIT
8653 && addr_reg
->reg_type
.bitfield
.reg16
)
8654 addr_mode
= CODE_16BIT
;
8656 if (addr_mode
!= flag_code
)
8658 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8660 /* Change the size of any displacement too. At most one
8661 of Disp16 or Disp32 is set.
8662 FIXME. There doesn't seem to be any real need for
8663 separate Disp16 and Disp32 flags. The same goes for
8664 Imm16 and Imm32. Removing them would probably clean
8665 up the code quite a lot. */
8666 if (flag_code
!= CODE_64BIT
8667 && (i
.types
[this_operand
].bitfield
.disp16
8668 || i
.types
[this_operand
].bitfield
.disp32
))
8669 i
.types
[this_operand
]
8670 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8677 if (current_templates
->start
->opcode_modifier
.isstring
8678 && !current_templates
->start
->opcode_modifier
.immext
8679 && (current_templates
->end
[-1].opcode_modifier
.isstring
8682 /* Memory operands of string insns are special in that they only allow
8683 a single register (rDI, rSI, or rBX) as their memory address. */
8684 const reg_entry
*expected_reg
;
8685 static const char *di_si
[][2] =
8691 static const char *bx
[] = { "ebx", "bx", "rbx" };
8693 kind
= "string address";
8695 if (current_templates
->start
->opcode_modifier
.repprefixok
)
8697 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8699 if (!type
.bitfield
.baseindex
8700 || ((!i
.mem_operands
!= !intel_syntax
)
8701 && current_templates
->end
[-1].operand_types
[1]
8702 .bitfield
.baseindex
))
8703 type
= current_templates
->end
[-1].operand_types
[1];
8704 expected_reg
= hash_find (reg_hash
,
8705 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8709 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8711 if (i
.base_reg
!= expected_reg
8713 || operand_type_check (i
.types
[this_operand
], disp
))
8715 /* The second memory operand must have the same size as
8719 && !((addr_mode
== CODE_64BIT
8720 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8721 || (addr_mode
== CODE_32BIT
8722 ? i
.base_reg
->reg_type
.bitfield
.reg32
8723 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8726 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8728 intel_syntax
? '[' : '(',
8730 expected_reg
->reg_name
,
8731 intel_syntax
? ']' : ')');
8738 as_bad (_("`%s' is not a valid %s expression"),
8739 operand_string
, kind
);
8744 if (addr_mode
!= CODE_16BIT
)
8746 /* 32-bit/64-bit checks. */
8748 && (addr_mode
== CODE_64BIT
8749 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8750 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8752 || (i
.base_reg
->reg_num
8753 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8755 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8756 && !i
.index_reg
->reg_type
.bitfield
.regymm
8757 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8758 && ((addr_mode
== CODE_64BIT
8759 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8760 || i
.index_reg
->reg_num
== RegRiz
)
8761 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8762 || i
.index_reg
->reg_num
== RegEiz
))
8763 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8766 /* bndmk, bndldx, and bndstx have special restrictions. */
8767 if (current_templates
->start
->base_opcode
== 0xf30f1b
8768 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
8770 /* They cannot use RIP-relative addressing. */
8771 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegRip
)
8773 as_bad (_("`%s' cannot be used here"), operand_string
);
8777 /* bndldx and bndstx ignore their scale factor. */
8778 if (current_templates
->start
->base_opcode
!= 0xf30f1b
8779 && i
.log2_scale_factor
)
8780 as_warn (_("register scaling is being ignored here"));
8785 /* 16-bit checks. */
8787 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8788 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8790 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8791 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8793 && i
.base_reg
->reg_num
< 6
8794 && i
.index_reg
->reg_num
>= 6
8795 && i
.log2_scale_factor
== 0))))
8802 /* Handle vector immediates. */
8805 RC_SAE_immediate (const char *imm_start
)
8807 unsigned int match_found
, j
;
8808 const char *pstr
= imm_start
;
8816 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8818 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8822 rc_op
.type
= RC_NamesTable
[j
].type
;
8823 rc_op
.operand
= this_operand
;
8824 i
.rounding
= &rc_op
;
8828 as_bad (_("duplicated `%s'"), imm_start
);
8831 pstr
+= RC_NamesTable
[j
].len
;
8841 as_bad (_("Missing '}': '%s'"), imm_start
);
8844 /* RC/SAE immediate string should contain nothing more. */;
8847 as_bad (_("Junk after '}': '%s'"), imm_start
);
8851 exp
= &im_expressions
[i
.imm_operands
++];
8852 i
.op
[this_operand
].imms
= exp
;
8854 exp
->X_op
= O_constant
;
8855 exp
->X_add_number
= 0;
8856 exp
->X_add_symbol
= (symbolS
*) 0;
8857 exp
->X_op_symbol
= (symbolS
*) 0;
8859 i
.types
[this_operand
].bitfield
.imm8
= 1;
8863 /* Only string instructions can have a second memory operand, so
8864 reduce current_templates to just those if it contains any. */
8866 maybe_adjust_templates (void)
8868 const insn_template
*t
;
8870 gas_assert (i
.mem_operands
== 1);
8872 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
8873 if (t
->opcode_modifier
.isstring
)
8876 if (t
< current_templates
->end
)
8878 static templates aux_templates
;
8879 bfd_boolean recheck
;
8881 aux_templates
.start
= t
;
8882 for (; t
< current_templates
->end
; ++t
)
8883 if (!t
->opcode_modifier
.isstring
)
8885 aux_templates
.end
= t
;
8887 /* Determine whether to re-check the first memory operand. */
8888 recheck
= (aux_templates
.start
!= current_templates
->start
8889 || t
!= current_templates
->end
);
8891 current_templates
= &aux_templates
;
8896 if (i
.memop1_string
!= NULL
8897 && i386_index_check (i
.memop1_string
) == 0)
8906 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8910 i386_att_operand (char *operand_string
)
8914 char *op_string
= operand_string
;
8916 if (is_space_char (*op_string
))
8919 /* We check for an absolute prefix (differentiating,
8920 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8921 if (*op_string
== ABSOLUTE_PREFIX
)
8924 if (is_space_char (*op_string
))
8926 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8929 /* Check if operand is a register. */
8930 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8932 i386_operand_type temp
;
8934 /* Check for a segment override by searching for ':' after a
8935 segment register. */
8937 if (is_space_char (*op_string
))
8939 if (*op_string
== ':'
8940 && (r
->reg_type
.bitfield
.sreg2
8941 || r
->reg_type
.bitfield
.sreg3
))
8946 i
.seg
[i
.mem_operands
] = &es
;
8949 i
.seg
[i
.mem_operands
] = &cs
;
8952 i
.seg
[i
.mem_operands
] = &ss
;
8955 i
.seg
[i
.mem_operands
] = &ds
;
8958 i
.seg
[i
.mem_operands
] = &fs
;
8961 i
.seg
[i
.mem_operands
] = &gs
;
8965 /* Skip the ':' and whitespace. */
8967 if (is_space_char (*op_string
))
8970 if (!is_digit_char (*op_string
)
8971 && !is_identifier_char (*op_string
)
8972 && *op_string
!= '('
8973 && *op_string
!= ABSOLUTE_PREFIX
)
8975 as_bad (_("bad memory operand `%s'"), op_string
);
8978 /* Handle case of %es:*foo. */
8979 if (*op_string
== ABSOLUTE_PREFIX
)
8982 if (is_space_char (*op_string
))
8984 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8986 goto do_memory_reference
;
8989 /* Handle vector operations. */
8990 if (*op_string
== '{')
8992 op_string
= check_VecOperations (op_string
, NULL
);
8993 if (op_string
== NULL
)
8999 as_bad (_("junk `%s' after register"), op_string
);
9003 temp
.bitfield
.baseindex
= 0;
9004 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9006 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9007 i
.op
[this_operand
].regs
= r
;
9010 else if (*op_string
== REGISTER_PREFIX
)
9012 as_bad (_("bad register name `%s'"), op_string
);
9015 else if (*op_string
== IMMEDIATE_PREFIX
)
9018 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
9020 as_bad (_("immediate operand illegal with absolute jump"));
9023 if (!i386_immediate (op_string
))
9026 else if (RC_SAE_immediate (operand_string
))
9028 /* If it is a RC or SAE immediate, do nothing. */
9031 else if (is_digit_char (*op_string
)
9032 || is_identifier_char (*op_string
)
9033 || *op_string
== '"'
9034 || *op_string
== '(')
9036 /* This is a memory reference of some sort. */
9039 /* Start and end of displacement string expression (if found). */
9040 char *displacement_string_start
;
9041 char *displacement_string_end
;
9044 do_memory_reference
:
9045 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
9047 if ((i
.mem_operands
== 1
9048 && !current_templates
->start
->opcode_modifier
.isstring
)
9049 || i
.mem_operands
== 2)
9051 as_bad (_("too many memory references for `%s'"),
9052 current_templates
->start
->name
);
9056 /* Check for base index form. We detect the base index form by
9057 looking for an ')' at the end of the operand, searching
9058 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9060 base_string
= op_string
+ strlen (op_string
);
9062 /* Handle vector operations. */
9063 vop_start
= strchr (op_string
, '{');
9064 if (vop_start
&& vop_start
< base_string
)
9066 if (check_VecOperations (vop_start
, base_string
) == NULL
)
9068 base_string
= vop_start
;
9072 if (is_space_char (*base_string
))
9075 /* If we only have a displacement, set-up for it to be parsed later. */
9076 displacement_string_start
= op_string
;
9077 displacement_string_end
= base_string
+ 1;
9079 if (*base_string
== ')')
9082 unsigned int parens_balanced
= 1;
9083 /* We've already checked that the number of left & right ()'s are
9084 equal, so this loop will not be infinite. */
9088 if (*base_string
== ')')
9090 if (*base_string
== '(')
9093 while (parens_balanced
);
9095 temp_string
= base_string
;
9097 /* Skip past '(' and whitespace. */
9099 if (is_space_char (*base_string
))
9102 if (*base_string
== ','
9103 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
9106 displacement_string_end
= temp_string
;
9108 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9112 base_string
= end_op
;
9113 if (is_space_char (*base_string
))
9117 /* There may be an index reg or scale factor here. */
9118 if (*base_string
== ',')
9121 if (is_space_char (*base_string
))
9124 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
9127 base_string
= end_op
;
9128 if (is_space_char (*base_string
))
9130 if (*base_string
== ',')
9133 if (is_space_char (*base_string
))
9136 else if (*base_string
!= ')')
9138 as_bad (_("expecting `,' or `)' "
9139 "after index register in `%s'"),
9144 else if (*base_string
== REGISTER_PREFIX
)
9146 end_op
= strchr (base_string
, ',');
9149 as_bad (_("bad register name `%s'"), base_string
);
9153 /* Check for scale factor. */
9154 if (*base_string
!= ')')
9156 char *end_scale
= i386_scale (base_string
);
9161 base_string
= end_scale
;
9162 if (is_space_char (*base_string
))
9164 if (*base_string
!= ')')
9166 as_bad (_("expecting `)' "
9167 "after scale factor in `%s'"),
9172 else if (!i
.index_reg
)
9174 as_bad (_("expecting index register or scale factor "
9175 "after `,'; got '%c'"),
9180 else if (*base_string
!= ')')
9182 as_bad (_("expecting `,' or `)' "
9183 "after base register in `%s'"),
9188 else if (*base_string
== REGISTER_PREFIX
)
9190 end_op
= strchr (base_string
, ',');
9193 as_bad (_("bad register name `%s'"), base_string
);
9198 /* If there's an expression beginning the operand, parse it,
9199 assuming displacement_string_start and
9200 displacement_string_end are meaningful. */
9201 if (displacement_string_start
!= displacement_string_end
)
9203 if (!i386_displacement (displacement_string_start
,
9204 displacement_string_end
))
9208 /* Special case for (%dx) while doing input/output op. */
9210 && operand_type_equal (&i
.base_reg
->reg_type
,
9211 ®16_inoutportreg
)
9213 && i
.log2_scale_factor
== 0
9214 && i
.seg
[i
.mem_operands
] == 0
9215 && !operand_type_check (i
.types
[this_operand
], disp
))
9217 i
.types
[this_operand
] = inoutportreg
;
9221 if (i386_index_check (operand_string
) == 0)
9223 i
.types
[this_operand
].bitfield
.mem
= 1;
9224 if (i
.mem_operands
== 0)
9225 i
.memop1_string
= xstrdup (operand_string
);
9230 /* It's not a memory operand; argh! */
9231 as_bad (_("invalid char %s beginning operand %d `%s'"),
9232 output_invalid (*op_string
),
9237 return 1; /* Normal return. */
9240 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9241 that an rs_machine_dependent frag may reach. */
9244 i386_frag_max_var (fragS
*frag
)
9246 /* The only relaxable frags are for jumps.
9247 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9248 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9249 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9252 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9254 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9256 /* STT_GNU_IFUNC symbol must go through PLT. */
9257 if ((symbol_get_bfdsym (fr_symbol
)->flags
9258 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9261 if (!S_IS_EXTERNAL (fr_symbol
))
9262 /* Symbol may be weak or local. */
9263 return !S_IS_WEAK (fr_symbol
);
9265 /* Global symbols with non-default visibility can't be preempted. */
9266 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9269 if (fr_var
!= NO_RELOC
)
9270 switch ((enum bfd_reloc_code_real
) fr_var
)
9272 case BFD_RELOC_386_PLT32
:
9273 case BFD_RELOC_X86_64_PLT32
:
9274 /* Symbol with PLT relocation may be preempted. */
9280 /* Global symbols with default visibility in a shared library may be
9281 preempted by another definition. */
9286 /* md_estimate_size_before_relax()
9288 Called just before relax() for rs_machine_dependent frags. The x86
9289 assembler uses these frags to handle variable size jump
9292 Any symbol that is now undefined will not become defined.
9293 Return the correct fr_subtype in the frag.
9294 Return the initial "guess for variable size of frag" to caller.
9295 The guess is actually the growth beyond the fixed part. Whatever
9296 we do to grow the fixed or variable part contributes to our
9300 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9302 /* We've already got fragP->fr_subtype right; all we have to do is
9303 check for un-relaxable symbols. On an ELF system, we can't relax
9304 an externally visible symbol, because it may be overridden by a
9306 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9307 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9309 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9312 #if defined (OBJ_COFF) && defined (TE_PE)
9313 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9314 && S_IS_WEAK (fragP
->fr_symbol
))
9318 /* Symbol is undefined in this segment, or we need to keep a
9319 reloc so that weak symbols can be overridden. */
9320 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9321 enum bfd_reloc_code_real reloc_type
;
9322 unsigned char *opcode
;
9325 if (fragP
->fr_var
!= NO_RELOC
)
9326 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9328 reloc_type
= BFD_RELOC_16_PCREL
;
9330 reloc_type
= BFD_RELOC_32_PCREL
;
9332 old_fr_fix
= fragP
->fr_fix
;
9333 opcode
= (unsigned char *) fragP
->fr_opcode
;
9335 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9338 /* Make jmp (0xeb) a (d)word displacement jump. */
9340 fragP
->fr_fix
+= size
;
9341 fix_new (fragP
, old_fr_fix
, size
,
9343 fragP
->fr_offset
, 1,
9349 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9351 /* Negate the condition, and branch past an
9352 unconditional jump. */
9355 /* Insert an unconditional jump. */
9357 /* We added two extra opcode bytes, and have a two byte
9359 fragP
->fr_fix
+= 2 + 2;
9360 fix_new (fragP
, old_fr_fix
+ 2, 2,
9362 fragP
->fr_offset
, 1,
9369 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9374 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9376 fragP
->fr_offset
, 1,
9378 fixP
->fx_signed
= 1;
9382 /* This changes the byte-displacement jump 0x7N
9383 to the (d)word-displacement jump 0x0f,0x8N. */
9384 opcode
[1] = opcode
[0] + 0x10;
9385 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9386 /* We've added an opcode byte. */
9387 fragP
->fr_fix
+= 1 + size
;
9388 fix_new (fragP
, old_fr_fix
+ 1, size
,
9390 fragP
->fr_offset
, 1,
9395 BAD_CASE (fragP
->fr_subtype
);
9399 return fragP
->fr_fix
- old_fr_fix
;
9402 /* Guess size depending on current relax state. Initially the relax
9403 state will correspond to a short jump and we return 1, because
9404 the variable part of the frag (the branch offset) is one byte
9405 long. However, we can relax a section more than once and in that
9406 case we must either set fr_subtype back to the unrelaxed state,
9407 or return the value for the appropriate branch. */
9408 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9411 /* Called after relax() is finished.
9413 In: Address of frag.
9414 fr_type == rs_machine_dependent.
9415 fr_subtype is what the address relaxed to.
9417 Out: Any fixSs and constants are set up.
9418 Caller will turn frag into a ".space 0". */
9421 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9424 unsigned char *opcode
;
9425 unsigned char *where_to_put_displacement
= NULL
;
9426 offsetT target_address
;
9427 offsetT opcode_address
;
9428 unsigned int extension
= 0;
9429 offsetT displacement_from_opcode_start
;
9431 opcode
= (unsigned char *) fragP
->fr_opcode
;
9433 /* Address we want to reach in file space. */
9434 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9436 /* Address opcode resides at in file space. */
9437 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9439 /* Displacement from opcode start to fill into instruction. */
9440 displacement_from_opcode_start
= target_address
- opcode_address
;
9442 if ((fragP
->fr_subtype
& BIG
) == 0)
9444 /* Don't have to change opcode. */
9445 extension
= 1; /* 1 opcode + 1 displacement */
9446 where_to_put_displacement
= &opcode
[1];
9450 if (no_cond_jump_promotion
9451 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9452 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9453 _("long jump required"));
9455 switch (fragP
->fr_subtype
)
9457 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9458 extension
= 4; /* 1 opcode + 4 displacement */
9460 where_to_put_displacement
= &opcode
[1];
9463 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9464 extension
= 2; /* 1 opcode + 2 displacement */
9466 where_to_put_displacement
= &opcode
[1];
9469 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9470 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9471 extension
= 5; /* 2 opcode + 4 displacement */
9472 opcode
[1] = opcode
[0] + 0x10;
9473 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9474 where_to_put_displacement
= &opcode
[2];
9477 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9478 extension
= 3; /* 2 opcode + 2 displacement */
9479 opcode
[1] = opcode
[0] + 0x10;
9480 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9481 where_to_put_displacement
= &opcode
[2];
9484 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9489 where_to_put_displacement
= &opcode
[3];
9493 BAD_CASE (fragP
->fr_subtype
);
9498 /* If size if less then four we are sure that the operand fits,
9499 but if it's 4, then it could be that the displacement is larger
9501 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9503 && ((addressT
) (displacement_from_opcode_start
- extension
9504 + ((addressT
) 1 << 31))
9505 > (((addressT
) 2 << 31) - 1)))
9507 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9508 _("jump target out of range"));
9509 /* Make us emit 0. */
9510 displacement_from_opcode_start
= extension
;
9512 /* Now put displacement after opcode. */
9513 md_number_to_chars ((char *) where_to_put_displacement
,
9514 (valueT
) (displacement_from_opcode_start
- extension
),
9515 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9516 fragP
->fr_fix
+= extension
;
9519 /* Apply a fixup (fixP) to segment data, once it has been determined
9520 by our caller that we have all the info we need to fix it up.
9522 Parameter valP is the pointer to the value of the bits.
9524 On the 386, immediates, displacements, and data pointers are all in
9525 the same (little-endian) format, so we don't need to care about which
9529 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9531 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9532 valueT value
= *valP
;
9534 #if !defined (TE_Mach)
9537 switch (fixP
->fx_r_type
)
9543 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9546 case BFD_RELOC_X86_64_32S
:
9547 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9550 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9553 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9558 if (fixP
->fx_addsy
!= NULL
9559 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9560 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9561 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9562 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9563 && !use_rela_relocations
)
9565 /* This is a hack. There should be a better way to handle this.
9566 This covers for the fact that bfd_install_relocation will
9567 subtract the current location (for partial_inplace, PC relative
9568 relocations); see more below. */
9572 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9575 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9577 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9580 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9583 || (symbol_section_p (fixP
->fx_addsy
)
9584 && sym_seg
!= absolute_section
))
9585 && !generic_force_reloc (fixP
))
9587 /* Yes, we add the values in twice. This is because
9588 bfd_install_relocation subtracts them out again. I think
9589 bfd_install_relocation is broken, but I don't dare change
9591 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9595 #if defined (OBJ_COFF) && defined (TE_PE)
9596 /* For some reason, the PE format does not store a
9597 section address offset for a PC relative symbol. */
9598 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9599 || S_IS_WEAK (fixP
->fx_addsy
))
9600 value
+= md_pcrel_from (fixP
);
9603 #if defined (OBJ_COFF) && defined (TE_PE)
9604 if (fixP
->fx_addsy
!= NULL
9605 && S_IS_WEAK (fixP
->fx_addsy
)
9606 /* PR 16858: Do not modify weak function references. */
9607 && ! fixP
->fx_pcrel
)
9609 #if !defined (TE_PEP)
9610 /* For x86 PE weak function symbols are neither PC-relative
9611 nor do they set S_IS_FUNCTION. So the only reliable way
9612 to detect them is to check the flags of their containing
9614 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9615 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9619 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9623 /* Fix a few things - the dynamic linker expects certain values here,
9624 and we must not disappoint it. */
9625 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9626 if (IS_ELF
&& fixP
->fx_addsy
)
9627 switch (fixP
->fx_r_type
)
9629 case BFD_RELOC_386_PLT32
:
9630 case BFD_RELOC_X86_64_PLT32
:
9631 /* Make the jump instruction point to the address of the operand. At
9632 runtime we merely add the offset to the actual PLT entry. */
9636 case BFD_RELOC_386_TLS_GD
:
9637 case BFD_RELOC_386_TLS_LDM
:
9638 case BFD_RELOC_386_TLS_IE_32
:
9639 case BFD_RELOC_386_TLS_IE
:
9640 case BFD_RELOC_386_TLS_GOTIE
:
9641 case BFD_RELOC_386_TLS_GOTDESC
:
9642 case BFD_RELOC_X86_64_TLSGD
:
9643 case BFD_RELOC_X86_64_TLSLD
:
9644 case BFD_RELOC_X86_64_GOTTPOFF
:
9645 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9646 value
= 0; /* Fully resolved at runtime. No addend. */
9648 case BFD_RELOC_386_TLS_LE
:
9649 case BFD_RELOC_386_TLS_LDO_32
:
9650 case BFD_RELOC_386_TLS_LE_32
:
9651 case BFD_RELOC_X86_64_DTPOFF32
:
9652 case BFD_RELOC_X86_64_DTPOFF64
:
9653 case BFD_RELOC_X86_64_TPOFF32
:
9654 case BFD_RELOC_X86_64_TPOFF64
:
9655 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9658 case BFD_RELOC_386_TLS_DESC_CALL
:
9659 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9660 value
= 0; /* Fully resolved at runtime. No addend. */
9661 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9665 case BFD_RELOC_VTABLE_INHERIT
:
9666 case BFD_RELOC_VTABLE_ENTRY
:
9673 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9675 #endif /* !defined (TE_Mach) */
9677 /* Are we finished with this relocation now? */
9678 if (fixP
->fx_addsy
== NULL
)
9680 #if defined (OBJ_COFF) && defined (TE_PE)
9681 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9684 /* Remember value for tc_gen_reloc. */
9685 fixP
->fx_addnumber
= value
;
9686 /* Clear out the frag for now. */
9690 else if (use_rela_relocations
)
9692 fixP
->fx_no_overflow
= 1;
9693 /* Remember value for tc_gen_reloc. */
9694 fixP
->fx_addnumber
= value
;
9698 md_number_to_chars (p
, value
, fixP
->fx_size
);
9702 md_atof (int type
, char *litP
, int *sizeP
)
9704 /* This outputs the LITTLENUMs in REVERSE order;
9705 in accord with the bigendian 386. */
9706 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9709 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9712 output_invalid (int c
)
9715 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9718 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9719 "(0x%x)", (unsigned char) c
);
9720 return output_invalid_buf
;
9723 /* REG_STRING starts *before* REGISTER_PREFIX. */
9725 static const reg_entry
*
9726 parse_real_register (char *reg_string
, char **end_op
)
9728 char *s
= reg_string
;
9730 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9733 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9734 if (*s
== REGISTER_PREFIX
)
9737 if (is_space_char (*s
))
9741 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9743 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9744 return (const reg_entry
*) NULL
;
9748 /* For naked regs, make sure that we are not dealing with an identifier.
9749 This prevents confusing an identifier like `eax_var' with register
9751 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9752 return (const reg_entry
*) NULL
;
9756 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9758 /* Handle floating point regs, allowing spaces in the (i) part. */
9759 if (r
== i386_regtab
/* %st is first entry of table */)
9761 if (is_space_char (*s
))
9766 if (is_space_char (*s
))
9768 if (*s
>= '0' && *s
<= '7')
9772 if (is_space_char (*s
))
9777 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9782 /* We have "%st(" then garbage. */
9783 return (const reg_entry
*) NULL
;
9787 if (r
== NULL
|| allow_pseudo_reg
)
9790 if (operand_type_all_zero (&r
->reg_type
))
9791 return (const reg_entry
*) NULL
;
9793 if ((r
->reg_type
.bitfield
.reg32
9794 || r
->reg_type
.bitfield
.sreg3
9795 || r
->reg_type
.bitfield
.control
9796 || r
->reg_type
.bitfield
.debug
9797 || r
->reg_type
.bitfield
.test
)
9798 && !cpu_arch_flags
.bitfield
.cpui386
)
9799 return (const reg_entry
*) NULL
;
9801 if (r
->reg_type
.bitfield
.floatreg
9802 && !cpu_arch_flags
.bitfield
.cpu8087
9803 && !cpu_arch_flags
.bitfield
.cpu287
9804 && !cpu_arch_flags
.bitfield
.cpu387
)
9805 return (const reg_entry
*) NULL
;
9807 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpuregmmx
)
9808 return (const reg_entry
*) NULL
;
9810 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpuregxmm
)
9811 return (const reg_entry
*) NULL
;
9813 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuregymm
)
9814 return (const reg_entry
*) NULL
;
9816 if (r
->reg_type
.bitfield
.regzmm
&& !cpu_arch_flags
.bitfield
.cpuregzmm
)
9817 return (const reg_entry
*) NULL
;
9819 if (r
->reg_type
.bitfield
.regmask
9820 && !cpu_arch_flags
.bitfield
.cpuregmask
)
9821 return (const reg_entry
*) NULL
;
9823 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9824 if (!allow_index_reg
9825 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9826 return (const reg_entry
*) NULL
;
9828 /* Upper 16 vector register is only available with VREX in 64bit
9830 if ((r
->reg_flags
& RegVRex
))
9832 if (i
.vec_encoding
== vex_encoding_default
)
9833 i
.vec_encoding
= vex_encoding_evex
;
9835 if (!cpu_arch_flags
.bitfield
.cpuvrex
9836 || i
.vec_encoding
!= vex_encoding_evex
9837 || flag_code
!= CODE_64BIT
)
9838 return (const reg_entry
*) NULL
;
9841 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9842 || r
->reg_type
.bitfield
.reg64
)
9843 && (!cpu_arch_flags
.bitfield
.cpulm
9844 || !operand_type_equal (&r
->reg_type
, &control
))
9845 && flag_code
!= CODE_64BIT
)
9846 return (const reg_entry
*) NULL
;
9848 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9849 return (const reg_entry
*) NULL
;
9854 /* REG_STRING starts *before* REGISTER_PREFIX. */
9856 static const reg_entry
*
9857 parse_register (char *reg_string
, char **end_op
)
9861 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9862 r
= parse_real_register (reg_string
, end_op
);
9867 char *save
= input_line_pointer
;
9871 input_line_pointer
= reg_string
;
9872 c
= get_symbol_name (®_string
);
9873 symbolP
= symbol_find (reg_string
);
9874 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9876 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9878 know (e
->X_op
== O_register
);
9879 know (e
->X_add_number
>= 0
9880 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9881 r
= i386_regtab
+ e
->X_add_number
;
9882 if ((r
->reg_flags
& RegVRex
))
9883 i
.vec_encoding
= vex_encoding_evex
;
9884 *end_op
= input_line_pointer
;
9886 *input_line_pointer
= c
;
9887 input_line_pointer
= save
;
9893 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9896 char *end
= input_line_pointer
;
9899 r
= parse_register (name
, &input_line_pointer
);
9900 if (r
&& end
<= input_line_pointer
)
9902 *nextcharP
= *input_line_pointer
;
9903 *input_line_pointer
= 0;
9904 e
->X_op
= O_register
;
9905 e
->X_add_number
= r
- i386_regtab
;
9908 input_line_pointer
= end
;
9910 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9914 md_operand (expressionS
*e
)
9919 switch (*input_line_pointer
)
9921 case REGISTER_PREFIX
:
9922 r
= parse_real_register (input_line_pointer
, &end
);
9925 e
->X_op
= O_register
;
9926 e
->X_add_number
= r
- i386_regtab
;
9927 input_line_pointer
= end
;
9932 gas_assert (intel_syntax
);
9933 end
= input_line_pointer
++;
9935 if (*input_line_pointer
== ']')
9937 ++input_line_pointer
;
9938 e
->X_op_symbol
= make_expr_symbol (e
);
9939 e
->X_add_symbol
= NULL
;
9940 e
->X_add_number
= 0;
9946 input_line_pointer
= end
;
9953 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9954 const char *md_shortopts
= "kVQ:sqn";
9956 const char *md_shortopts
= "qn";
9959 #define OPTION_32 (OPTION_MD_BASE + 0)
9960 #define OPTION_64 (OPTION_MD_BASE + 1)
9961 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9962 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9963 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9964 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9965 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9966 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9967 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9968 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9969 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9970 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9971 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9972 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9973 #define OPTION_X32 (OPTION_MD_BASE + 14)
9974 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9975 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9976 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9977 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9978 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9979 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9980 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9981 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9982 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9983 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9984 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
9986 struct option md_longopts
[] =
9988 {"32", no_argument
, NULL
, OPTION_32
},
9989 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9990 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9991 {"64", no_argument
, NULL
, OPTION_64
},
9993 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9994 {"x32", no_argument
, NULL
, OPTION_X32
},
9995 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
9997 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9998 {"march", required_argument
, NULL
, OPTION_MARCH
},
9999 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10000 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
10001 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
10002 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
10003 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
10004 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
10005 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
10006 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
10007 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
10008 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
10009 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
10010 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
10011 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
10012 # if defined (TE_PE) || defined (TE_PEP)
10013 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
10015 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
10016 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
10017 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
10018 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
10019 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
10020 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
10021 {NULL
, no_argument
, NULL
, 0}
10023 size_t md_longopts_size
= sizeof (md_longopts
);
10026 md_parse_option (int c
, const char *arg
)
10029 char *arch
, *next
, *saved
;
10034 optimize_align_code
= 0;
10038 quiet_warnings
= 1;
10041 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10042 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10043 should be emitted or not. FIXME: Not implemented. */
10047 /* -V: SVR4 argument to print version ID. */
10049 print_version_id ();
10052 /* -k: Ignore for FreeBSD compatibility. */
10057 /* -s: On i386 Solaris, this tells the native assembler to use
10058 .stab instead of .stab.excl. We always use .stab anyhow. */
10061 case OPTION_MSHARED
:
10065 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10066 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10069 const char **list
, **l
;
10071 list
= bfd_target_list ();
10072 for (l
= list
; *l
!= NULL
; l
++)
10073 if (CONST_STRNEQ (*l
, "elf64-x86-64")
10074 || strcmp (*l
, "coff-x86-64") == 0
10075 || strcmp (*l
, "pe-x86-64") == 0
10076 || strcmp (*l
, "pei-x86-64") == 0
10077 || strcmp (*l
, "mach-o-x86-64") == 0)
10079 default_arch
= "x86_64";
10083 as_fatal (_("no compiled in support for x86_64"));
10089 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10093 const char **list
, **l
;
10095 list
= bfd_target_list ();
10096 for (l
= list
; *l
!= NULL
; l
++)
10097 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
10099 default_arch
= "x86_64:32";
10103 as_fatal (_("no compiled in support for 32bit x86_64"));
10107 as_fatal (_("32bit x86_64 is only supported for ELF"));
10112 default_arch
= "i386";
10115 case OPTION_DIVIDE
:
10116 #ifdef SVR4_COMMENT_CHARS
10121 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
10123 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
10127 i386_comment_chars
= n
;
10133 saved
= xstrdup (arg
);
10135 /* Allow -march=+nosse. */
10141 as_fatal (_("invalid -march= option: `%s'"), arg
);
10142 next
= strchr (arch
, '+');
10145 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10147 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
10150 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10153 cpu_arch_name
= cpu_arch
[j
].name
;
10154 cpu_sub_arch_name
= NULL
;
10155 cpu_arch_flags
= cpu_arch
[j
].flags
;
10156 cpu_arch_isa
= cpu_arch
[j
].type
;
10157 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
10158 if (!cpu_arch_tune_set
)
10160 cpu_arch_tune
= cpu_arch_isa
;
10161 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10165 else if (*cpu_arch
[j
].name
== '.'
10166 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
10168 /* ISA extension. */
10169 i386_cpu_flags flags
;
10171 flags
= cpu_flags_or (cpu_arch_flags
,
10172 cpu_arch
[j
].flags
);
10174 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10176 if (cpu_sub_arch_name
)
10178 char *name
= cpu_sub_arch_name
;
10179 cpu_sub_arch_name
= concat (name
,
10181 (const char *) NULL
);
10185 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
10186 cpu_arch_flags
= flags
;
10187 cpu_arch_isa_flags
= flags
;
10193 if (j
>= ARRAY_SIZE (cpu_arch
))
10195 /* Disable an ISA extension. */
10196 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10197 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
10199 i386_cpu_flags flags
;
10201 flags
= cpu_flags_and_not (cpu_arch_flags
,
10202 cpu_noarch
[j
].flags
);
10203 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10205 if (cpu_sub_arch_name
)
10207 char *name
= cpu_sub_arch_name
;
10208 cpu_sub_arch_name
= concat (arch
,
10209 (const char *) NULL
);
10213 cpu_sub_arch_name
= xstrdup (arch
);
10214 cpu_arch_flags
= flags
;
10215 cpu_arch_isa_flags
= flags
;
10220 if (j
>= ARRAY_SIZE (cpu_noarch
))
10221 j
= ARRAY_SIZE (cpu_arch
);
10224 if (j
>= ARRAY_SIZE (cpu_arch
))
10225 as_fatal (_("invalid -march= option: `%s'"), arg
);
10229 while (next
!= NULL
);
10235 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10236 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10238 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
10240 cpu_arch_tune_set
= 1;
10241 cpu_arch_tune
= cpu_arch
[j
].type
;
10242 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10246 if (j
>= ARRAY_SIZE (cpu_arch
))
10247 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10250 case OPTION_MMNEMONIC
:
10251 if (strcasecmp (arg
, "att") == 0)
10252 intel_mnemonic
= 0;
10253 else if (strcasecmp (arg
, "intel") == 0)
10254 intel_mnemonic
= 1;
10256 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10259 case OPTION_MSYNTAX
:
10260 if (strcasecmp (arg
, "att") == 0)
10262 else if (strcasecmp (arg
, "intel") == 0)
10265 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10268 case OPTION_MINDEX_REG
:
10269 allow_index_reg
= 1;
10272 case OPTION_MNAKED_REG
:
10273 allow_naked_reg
= 1;
10276 case OPTION_MOLD_GCC
:
10280 case OPTION_MSSE2AVX
:
10284 case OPTION_MSSE_CHECK
:
10285 if (strcasecmp (arg
, "error") == 0)
10286 sse_check
= check_error
;
10287 else if (strcasecmp (arg
, "warning") == 0)
10288 sse_check
= check_warning
;
10289 else if (strcasecmp (arg
, "none") == 0)
10290 sse_check
= check_none
;
10292 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10295 case OPTION_MOPERAND_CHECK
:
10296 if (strcasecmp (arg
, "error") == 0)
10297 operand_check
= check_error
;
10298 else if (strcasecmp (arg
, "warning") == 0)
10299 operand_check
= check_warning
;
10300 else if (strcasecmp (arg
, "none") == 0)
10301 operand_check
= check_none
;
10303 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10306 case OPTION_MAVXSCALAR
:
10307 if (strcasecmp (arg
, "128") == 0)
10308 avxscalar
= vex128
;
10309 else if (strcasecmp (arg
, "256") == 0)
10310 avxscalar
= vex256
;
10312 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10315 case OPTION_MADD_BND_PREFIX
:
10316 add_bnd_prefix
= 1;
10319 case OPTION_MEVEXLIG
:
10320 if (strcmp (arg
, "128") == 0)
10321 evexlig
= evexl128
;
10322 else if (strcmp (arg
, "256") == 0)
10323 evexlig
= evexl256
;
10324 else if (strcmp (arg
, "512") == 0)
10325 evexlig
= evexl512
;
10327 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10330 case OPTION_MEVEXRCIG
:
10331 if (strcmp (arg
, "rne") == 0)
10333 else if (strcmp (arg
, "rd") == 0)
10335 else if (strcmp (arg
, "ru") == 0)
10337 else if (strcmp (arg
, "rz") == 0)
10340 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10343 case OPTION_MEVEXWIG
:
10344 if (strcmp (arg
, "0") == 0)
10346 else if (strcmp (arg
, "1") == 0)
10349 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10352 # if defined (TE_PE) || defined (TE_PEP)
10353 case OPTION_MBIG_OBJ
:
10358 case OPTION_MOMIT_LOCK_PREFIX
:
10359 if (strcasecmp (arg
, "yes") == 0)
10360 omit_lock_prefix
= 1;
10361 else if (strcasecmp (arg
, "no") == 0)
10362 omit_lock_prefix
= 0;
10364 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10367 case OPTION_MFENCE_AS_LOCK_ADD
:
10368 if (strcasecmp (arg
, "yes") == 0)
10370 else if (strcasecmp (arg
, "no") == 0)
10373 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10376 case OPTION_MRELAX_RELOCATIONS
:
10377 if (strcasecmp (arg
, "yes") == 0)
10378 generate_relax_relocations
= 1;
10379 else if (strcasecmp (arg
, "no") == 0)
10380 generate_relax_relocations
= 0;
10382 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10385 case OPTION_MAMD64
:
10389 case OPTION_MINTEL64
:
10399 #define MESSAGE_TEMPLATE \
10403 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10404 int *left_p
, const char *name
, int len
)
10406 int size
= sizeof (MESSAGE_TEMPLATE
);
10407 int left
= *left_p
;
10409 /* Reserve 2 spaces for ", " or ",\0" */
10412 /* Check if there is any room. */
10420 p
= mempcpy (p
, name
, len
);
10424 /* Output the current message now and start a new one. */
10427 fprintf (stream
, "%s\n", message
);
10429 left
= size
- (start
- message
) - len
- 2;
10431 gas_assert (left
>= 0);
10433 p
= mempcpy (p
, name
, len
);
10441 show_arch (FILE *stream
, int ext
, int check
)
10443 static char message
[] = MESSAGE_TEMPLATE
;
10444 char *start
= message
+ 27;
10446 int size
= sizeof (MESSAGE_TEMPLATE
);
10453 left
= size
- (start
- message
);
10454 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10456 /* Should it be skipped? */
10457 if (cpu_arch
[j
].skip
)
10460 name
= cpu_arch
[j
].name
;
10461 len
= cpu_arch
[j
].len
;
10464 /* It is an extension. Skip if we aren't asked to show it. */
10475 /* It is an processor. Skip if we show only extension. */
10478 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10480 /* It is an impossible processor - skip. */
10484 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10487 /* Display disabled extensions. */
10489 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10491 name
= cpu_noarch
[j
].name
;
10492 len
= cpu_noarch
[j
].len
;
10493 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10498 fprintf (stream
, "%s\n", message
);
10502 md_show_usage (FILE *stream
)
10504 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10505 fprintf (stream
, _("\
10507 -V print assembler version number\n\
10510 fprintf (stream
, _("\
10511 -n Do not optimize code alignment\n\
10512 -q quieten some warnings\n"));
10513 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10514 fprintf (stream
, _("\
10517 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10518 || defined (TE_PE) || defined (TE_PEP))
10519 fprintf (stream
, _("\
10520 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10522 #ifdef SVR4_COMMENT_CHARS
10523 fprintf (stream
, _("\
10524 --divide do not treat `/' as a comment character\n"));
10526 fprintf (stream
, _("\
10527 --divide ignored\n"));
10529 fprintf (stream
, _("\
10530 -march=CPU[,+EXTENSION...]\n\
10531 generate code for CPU and EXTENSION, CPU is one of:\n"));
10532 show_arch (stream
, 0, 1);
10533 fprintf (stream
, _("\
10534 EXTENSION is combination of:\n"));
10535 show_arch (stream
, 1, 0);
10536 fprintf (stream
, _("\
10537 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10538 show_arch (stream
, 0, 0);
10539 fprintf (stream
, _("\
10540 -msse2avx encode SSE instructions with VEX prefix\n"));
10541 fprintf (stream
, _("\
10542 -msse-check=[none|error|warning]\n\
10543 check SSE instructions\n"));
10544 fprintf (stream
, _("\
10545 -moperand-check=[none|error|warning]\n\
10546 check operand combinations for validity\n"));
10547 fprintf (stream
, _("\
10548 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10550 fprintf (stream
, _("\
10551 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10553 fprintf (stream
, _("\
10554 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10555 for EVEX.W bit ignored instructions\n"));
10556 fprintf (stream
, _("\
10557 -mevexrcig=[rne|rd|ru|rz]\n\
10558 encode EVEX instructions with specific EVEX.RC value\n\
10559 for SAE-only ignored instructions\n"));
10560 fprintf (stream
, _("\
10561 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10562 fprintf (stream
, _("\
10563 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10564 fprintf (stream
, _("\
10565 -mindex-reg support pseudo index registers\n"));
10566 fprintf (stream
, _("\
10567 -mnaked-reg don't require `%%' prefix for registers\n"));
10568 fprintf (stream
, _("\
10569 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10570 fprintf (stream
, _("\
10571 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10572 fprintf (stream
, _("\
10573 -mshared disable branch optimization for shared code\n"));
10574 # if defined (TE_PE) || defined (TE_PEP)
10575 fprintf (stream
, _("\
10576 -mbig-obj generate big object files\n"));
10578 fprintf (stream
, _("\
10579 -momit-lock-prefix=[no|yes]\n\
10580 strip all lock prefixes\n"));
10581 fprintf (stream
, _("\
10582 -mfence-as-lock-add=[no|yes]\n\
10583 encode lfence, mfence and sfence as\n\
10584 lock addl $0x0, (%%{re}sp)\n"));
10585 fprintf (stream
, _("\
10586 -mrelax-relocations=[no|yes]\n\
10587 generate relax relocations\n"));
10588 fprintf (stream
, _("\
10589 -mamd64 accept only AMD64 ISA\n"));
10590 fprintf (stream
, _("\
10591 -mintel64 accept only Intel64 ISA\n"));
10594 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10595 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10596 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10598 /* Pick the target format to use. */
10601 i386_target_format (void)
10603 if (!strncmp (default_arch
, "x86_64", 6))
10605 update_code_flag (CODE_64BIT
, 1);
10606 if (default_arch
[6] == '\0')
10607 x86_elf_abi
= X86_64_ABI
;
10609 x86_elf_abi
= X86_64_X32_ABI
;
10611 else if (!strcmp (default_arch
, "i386"))
10612 update_code_flag (CODE_32BIT
, 1);
10613 else if (!strcmp (default_arch
, "iamcu"))
10615 update_code_flag (CODE_32BIT
, 1);
10616 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10618 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10619 cpu_arch_name
= "iamcu";
10620 cpu_sub_arch_name
= NULL
;
10621 cpu_arch_flags
= iamcu_flags
;
10622 cpu_arch_isa
= PROCESSOR_IAMCU
;
10623 cpu_arch_isa_flags
= iamcu_flags
;
10624 if (!cpu_arch_tune_set
)
10626 cpu_arch_tune
= cpu_arch_isa
;
10627 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10630 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
10631 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10635 as_fatal (_("unknown architecture"));
10637 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10638 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10639 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10640 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10642 switch (OUTPUT_FLAVOR
)
10644 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10645 case bfd_target_aout_flavour
:
10646 return AOUT_TARGET_FORMAT
;
10648 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10649 # if defined (TE_PE) || defined (TE_PEP)
10650 case bfd_target_coff_flavour
:
10651 if (flag_code
== CODE_64BIT
)
10652 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10655 # elif defined (TE_GO32)
10656 case bfd_target_coff_flavour
:
10657 return "coff-go32";
10659 case bfd_target_coff_flavour
:
10660 return "coff-i386";
10663 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10664 case bfd_target_elf_flavour
:
10666 const char *format
;
10668 switch (x86_elf_abi
)
10671 format
= ELF_TARGET_FORMAT
;
10674 use_rela_relocations
= 1;
10676 format
= ELF_TARGET_FORMAT64
;
10678 case X86_64_X32_ABI
:
10679 use_rela_relocations
= 1;
10681 disallow_64bit_reloc
= 1;
10682 format
= ELF_TARGET_FORMAT32
;
10685 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10687 if (x86_elf_abi
!= X86_64_ABI
)
10688 as_fatal (_("Intel L1OM is 64bit only"));
10689 return ELF_TARGET_L1OM_FORMAT
;
10691 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10693 if (x86_elf_abi
!= X86_64_ABI
)
10694 as_fatal (_("Intel K1OM is 64bit only"));
10695 return ELF_TARGET_K1OM_FORMAT
;
10697 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10699 if (x86_elf_abi
!= I386_ABI
)
10700 as_fatal (_("Intel MCU is 32bit only"));
10701 return ELF_TARGET_IAMCU_FORMAT
;
10707 #if defined (OBJ_MACH_O)
10708 case bfd_target_mach_o_flavour
:
10709 if (flag_code
== CODE_64BIT
)
10711 use_rela_relocations
= 1;
10713 return "mach-o-x86-64";
10716 return "mach-o-i386";
10724 #endif /* OBJ_MAYBE_ more than one */
10727 md_undefined_symbol (char *name
)
10729 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10730 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10731 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10732 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10736 if (symbol_find (name
))
10737 as_bad (_("GOT already in symbol table"));
10738 GOT_symbol
= symbol_new (name
, undefined_section
,
10739 (valueT
) 0, &zero_address_frag
);
10746 /* Round up a section size to the appropriate boundary. */
10749 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10751 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10752 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10754 /* For a.out, force the section size to be aligned. If we don't do
10755 this, BFD will align it for us, but it will not write out the
10756 final bytes of the section. This may be a bug in BFD, but it is
10757 easier to fix it here since that is how the other a.out targets
10761 align
= bfd_get_section_alignment (stdoutput
, segment
);
10762 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
10769 /* On the i386, PC-relative offsets are relative to the start of the
10770 next instruction. That is, the address of the offset, plus its
10771 size, since the offset is always the last part of the insn. */
10774 md_pcrel_from (fixS
*fixP
)
10776 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10782 s_bss (int ignore ATTRIBUTE_UNUSED
)
10786 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10788 obj_elf_section_change_hook ();
10790 temp
= get_absolute_expression ();
10791 subseg_set (bss_section
, (subsegT
) temp
);
10792 demand_empty_rest_of_line ();
10798 i386_validate_fix (fixS
*fixp
)
10800 if (fixp
->fx_subsy
)
10802 if (fixp
->fx_subsy
== GOT_symbol
)
10804 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10808 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10809 if (fixp
->fx_tcbit2
)
10810 fixp
->fx_r_type
= (fixp
->fx_tcbit
10811 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10812 : BFD_RELOC_X86_64_GOTPCRELX
);
10815 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10820 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10822 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10824 fixp
->fx_subsy
= 0;
10827 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10828 else if (!object_64bit
)
10830 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
10831 && fixp
->fx_tcbit2
)
10832 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
10838 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10841 bfd_reloc_code_real_type code
;
10843 switch (fixp
->fx_r_type
)
10845 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10846 case BFD_RELOC_SIZE32
:
10847 case BFD_RELOC_SIZE64
:
10848 if (S_IS_DEFINED (fixp
->fx_addsy
)
10849 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10851 /* Resolve size relocation against local symbol to size of
10852 the symbol plus addend. */
10853 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10854 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10855 && !fits_in_unsigned_long (value
))
10856 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10857 _("symbol size computation overflow"));
10858 fixp
->fx_addsy
= NULL
;
10859 fixp
->fx_subsy
= NULL
;
10860 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10864 /* Fall through. */
10866 case BFD_RELOC_X86_64_PLT32
:
10867 case BFD_RELOC_X86_64_GOT32
:
10868 case BFD_RELOC_X86_64_GOTPCREL
:
10869 case BFD_RELOC_X86_64_GOTPCRELX
:
10870 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10871 case BFD_RELOC_386_PLT32
:
10872 case BFD_RELOC_386_GOT32
:
10873 case BFD_RELOC_386_GOT32X
:
10874 case BFD_RELOC_386_GOTOFF
:
10875 case BFD_RELOC_386_GOTPC
:
10876 case BFD_RELOC_386_TLS_GD
:
10877 case BFD_RELOC_386_TLS_LDM
:
10878 case BFD_RELOC_386_TLS_LDO_32
:
10879 case BFD_RELOC_386_TLS_IE_32
:
10880 case BFD_RELOC_386_TLS_IE
:
10881 case BFD_RELOC_386_TLS_GOTIE
:
10882 case BFD_RELOC_386_TLS_LE_32
:
10883 case BFD_RELOC_386_TLS_LE
:
10884 case BFD_RELOC_386_TLS_GOTDESC
:
10885 case BFD_RELOC_386_TLS_DESC_CALL
:
10886 case BFD_RELOC_X86_64_TLSGD
:
10887 case BFD_RELOC_X86_64_TLSLD
:
10888 case BFD_RELOC_X86_64_DTPOFF32
:
10889 case BFD_RELOC_X86_64_DTPOFF64
:
10890 case BFD_RELOC_X86_64_GOTTPOFF
:
10891 case BFD_RELOC_X86_64_TPOFF32
:
10892 case BFD_RELOC_X86_64_TPOFF64
:
10893 case BFD_RELOC_X86_64_GOTOFF64
:
10894 case BFD_RELOC_X86_64_GOTPC32
:
10895 case BFD_RELOC_X86_64_GOT64
:
10896 case BFD_RELOC_X86_64_GOTPCREL64
:
10897 case BFD_RELOC_X86_64_GOTPC64
:
10898 case BFD_RELOC_X86_64_GOTPLT64
:
10899 case BFD_RELOC_X86_64_PLTOFF64
:
10900 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10901 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10902 case BFD_RELOC_RVA
:
10903 case BFD_RELOC_VTABLE_ENTRY
:
10904 case BFD_RELOC_VTABLE_INHERIT
:
10906 case BFD_RELOC_32_SECREL
:
10908 code
= fixp
->fx_r_type
;
10910 case BFD_RELOC_X86_64_32S
:
10911 if (!fixp
->fx_pcrel
)
10913 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10914 code
= fixp
->fx_r_type
;
10917 /* Fall through. */
10919 if (fixp
->fx_pcrel
)
10921 switch (fixp
->fx_size
)
10924 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10925 _("can not do %d byte pc-relative relocation"),
10927 code
= BFD_RELOC_32_PCREL
;
10929 case 1: code
= BFD_RELOC_8_PCREL
; break;
10930 case 2: code
= BFD_RELOC_16_PCREL
; break;
10931 case 4: code
= BFD_RELOC_32_PCREL
; break;
10933 case 8: code
= BFD_RELOC_64_PCREL
; break;
10939 switch (fixp
->fx_size
)
10942 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10943 _("can not do %d byte relocation"),
10945 code
= BFD_RELOC_32
;
10947 case 1: code
= BFD_RELOC_8
; break;
10948 case 2: code
= BFD_RELOC_16
; break;
10949 case 4: code
= BFD_RELOC_32
; break;
10951 case 8: code
= BFD_RELOC_64
; break;
10958 if ((code
== BFD_RELOC_32
10959 || code
== BFD_RELOC_32_PCREL
10960 || code
== BFD_RELOC_X86_64_32S
)
10962 && fixp
->fx_addsy
== GOT_symbol
)
10965 code
= BFD_RELOC_386_GOTPC
;
10967 code
= BFD_RELOC_X86_64_GOTPC32
;
10969 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10971 && fixp
->fx_addsy
== GOT_symbol
)
10973 code
= BFD_RELOC_X86_64_GOTPC64
;
10976 rel
= XNEW (arelent
);
10977 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
10978 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10980 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10982 if (!use_rela_relocations
)
10984 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10985 vtable entry to be used in the relocation's section offset. */
10986 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10987 rel
->address
= fixp
->fx_offset
;
10988 #if defined (OBJ_COFF) && defined (TE_PE)
10989 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10990 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10995 /* Use the rela in 64bit mode. */
10998 if (disallow_64bit_reloc
)
11001 case BFD_RELOC_X86_64_DTPOFF64
:
11002 case BFD_RELOC_X86_64_TPOFF64
:
11003 case BFD_RELOC_64_PCREL
:
11004 case BFD_RELOC_X86_64_GOTOFF64
:
11005 case BFD_RELOC_X86_64_GOT64
:
11006 case BFD_RELOC_X86_64_GOTPCREL64
:
11007 case BFD_RELOC_X86_64_GOTPC64
:
11008 case BFD_RELOC_X86_64_GOTPLT64
:
11009 case BFD_RELOC_X86_64_PLTOFF64
:
11010 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11011 _("cannot represent relocation type %s in x32 mode"),
11012 bfd_get_reloc_code_name (code
));
11018 if (!fixp
->fx_pcrel
)
11019 rel
->addend
= fixp
->fx_offset
;
11023 case BFD_RELOC_X86_64_PLT32
:
11024 case BFD_RELOC_X86_64_GOT32
:
11025 case BFD_RELOC_X86_64_GOTPCREL
:
11026 case BFD_RELOC_X86_64_GOTPCRELX
:
11027 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11028 case BFD_RELOC_X86_64_TLSGD
:
11029 case BFD_RELOC_X86_64_TLSLD
:
11030 case BFD_RELOC_X86_64_GOTTPOFF
:
11031 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11032 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11033 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
11036 rel
->addend
= (section
->vma
11038 + fixp
->fx_addnumber
11039 + md_pcrel_from (fixp
));
11044 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11045 if (rel
->howto
== NULL
)
11047 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11048 _("cannot represent relocation type %s"),
11049 bfd_get_reloc_code_name (code
));
11050 /* Set howto to a garbage value so that we can keep going. */
11051 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
11052 gas_assert (rel
->howto
!= NULL
);
11058 #include "tc-i386-intel.c"
11061 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
11063 int saved_naked_reg
;
11064 char saved_register_dot
;
11066 saved_naked_reg
= allow_naked_reg
;
11067 allow_naked_reg
= 1;
11068 saved_register_dot
= register_chars
['.'];
11069 register_chars
['.'] = '.';
11070 allow_pseudo_reg
= 1;
11071 expression_and_evaluate (exp
);
11072 allow_pseudo_reg
= 0;
11073 register_chars
['.'] = saved_register_dot
;
11074 allow_naked_reg
= saved_naked_reg
;
11076 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
11078 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
11080 exp
->X_op
= O_constant
;
11081 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
11082 .dw2_regnum
[flag_code
>> 1];
11085 exp
->X_op
= O_illegal
;
11090 tc_x86_frame_initial_instructions (void)
11092 static unsigned int sp_regno
[2];
11094 if (!sp_regno
[flag_code
>> 1])
11096 char *saved_input
= input_line_pointer
;
11097 char sp
[][4] = {"esp", "rsp"};
11100 input_line_pointer
= sp
[flag_code
>> 1];
11101 tc_x86_parse_to_dw2regnum (&exp
);
11102 gas_assert (exp
.X_op
== O_constant
);
11103 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
11104 input_line_pointer
= saved_input
;
11107 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
11108 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
11112 x86_dwarf2_addr_size (void)
11114 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11115 if (x86_elf_abi
== X86_64_X32_ABI
)
11118 return bfd_arch_bits_per_address (stdoutput
) / 8;
11122 i386_elf_section_type (const char *str
, size_t len
)
11124 if (flag_code
== CODE_64BIT
11125 && len
== sizeof ("unwind") - 1
11126 && strncmp (str
, "unwind", 6) == 0)
11127 return SHT_X86_64_UNWIND
;
11134 i386_solaris_fix_up_eh_frame (segT sec
)
11136 if (flag_code
== CODE_64BIT
)
11137 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
11143 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
11147 exp
.X_op
= O_secrel
;
11148 exp
.X_add_symbol
= symbol
;
11149 exp
.X_add_number
= 0;
11150 emit_expr (&exp
, size
);
11154 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11155 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11158 x86_64_section_letter (int letter
, const char **ptr_msg
)
11160 if (flag_code
== CODE_64BIT
)
11163 return SHF_X86_64_LARGE
;
11165 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11168 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
11173 x86_64_section_word (char *str
, size_t len
)
11175 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
11176 return SHF_X86_64_LARGE
;
11182 handle_large_common (int small ATTRIBUTE_UNUSED
)
11184 if (flag_code
!= CODE_64BIT
)
11186 s_comm_internal (0, elf_common_parse
);
11187 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11191 static segT lbss_section
;
11192 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
11193 asection
*saved_bss_section
= bss_section
;
11195 if (lbss_section
== NULL
)
11197 flagword applicable
;
11198 segT seg
= now_seg
;
11199 subsegT subseg
= now_subseg
;
11201 /* The .lbss section is for local .largecomm symbols. */
11202 lbss_section
= subseg_new (".lbss", 0);
11203 applicable
= bfd_applicable_section_flags (stdoutput
);
11204 bfd_set_section_flags (stdoutput
, lbss_section
,
11205 applicable
& SEC_ALLOC
);
11206 seg_info (lbss_section
)->bss
= 1;
11208 subseg_set (seg
, subseg
);
11211 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
11212 bss_section
= lbss_section
;
11214 s_comm_internal (0, elf_common_parse
);
11216 elf_com_section_ptr
= saved_com_section_ptr
;
11217 bss_section
= saved_bss_section
;
11220 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */