1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static INLINE
unsigned int mode_from_disp_size
PARAMS ((unsigned int));
67 static INLINE
int fits_in_signed_byte
PARAMS ((offsetT
));
68 static INLINE
int fits_in_unsigned_byte
PARAMS ((offsetT
));
69 static INLINE
int fits_in_unsigned_word
PARAMS ((offsetT
));
70 static INLINE
int fits_in_signed_word
PARAMS ((offsetT
));
71 static INLINE
int fits_in_unsigned_long
PARAMS ((offsetT
));
72 static INLINE
int fits_in_signed_long
PARAMS ((offsetT
));
73 static int smallest_imm_type
PARAMS ((offsetT
));
74 static offsetT offset_in_range
PARAMS ((offsetT
, int));
75 static int add_prefix
PARAMS ((unsigned int));
76 static void set_code_flag
PARAMS ((int));
77 static void set_16bit_gcc_code_flag
PARAMS ((int));
78 static void set_intel_syntax
PARAMS ((int));
79 static void set_cpu_arch
PARAMS ((int));
81 static void pe_directive_secrel
PARAMS ((int));
83 static void signed_cons
PARAMS ((int));
84 static char *output_invalid
PARAMS ((int c
));
85 static int i386_operand
PARAMS ((char *operand_string
));
86 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
87 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
89 static char *parse_insn
PARAMS ((char *, char *));
90 static char *parse_operands
PARAMS ((char *, const char *));
91 static void swap_operands
PARAMS ((void));
92 static void optimize_imm
PARAMS ((void));
93 static void optimize_disp
PARAMS ((void));
94 static int match_template
PARAMS ((void));
95 static int check_string
PARAMS ((void));
96 static int process_suffix
PARAMS ((void));
97 static int check_byte_reg
PARAMS ((void));
98 static int check_long_reg
PARAMS ((void));
99 static int check_qword_reg
PARAMS ((void));
100 static int check_word_reg
PARAMS ((void));
101 static int finalize_imm
PARAMS ((void));
102 static int process_operands
PARAMS ((void));
103 static const seg_entry
*build_modrm_byte
PARAMS ((void));
104 static void output_insn
PARAMS ((void));
105 static void output_branch
PARAMS ((void));
106 static void output_jump
PARAMS ((void));
107 static void output_interseg_jump
PARAMS ((void));
108 static void output_imm
PARAMS ((fragS
*insn_start_frag
,
109 offsetT insn_start_off
));
110 static void output_disp
PARAMS ((fragS
*insn_start_frag
,
111 offsetT insn_start_off
));
113 static void s_bss
PARAMS ((int));
115 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
116 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
119 static const char *default_arch
= DEFAULT_ARCH
;
121 /* 'md_assemble ()' gathers together information and puts it into a
128 const reg_entry
*regs
;
133 /* TM holds the template for the insn were currently assembling. */
136 /* SUFFIX holds the instruction mnemonic suffix if given.
137 (e.g. 'l' for 'movl') */
140 /* OPERANDS gives the number of given operands. */
141 unsigned int operands
;
143 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
144 of given register, displacement, memory operands and immediate
146 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
148 /* TYPES [i] is the type (see above #defines) which tells us how to
149 use OP[i] for the corresponding operand. */
150 unsigned int types
[MAX_OPERANDS
];
152 /* Displacement expression, immediate expression, or register for each
154 union i386_op op
[MAX_OPERANDS
];
156 /* Flags for operands. */
157 unsigned int flags
[MAX_OPERANDS
];
158 #define Operand_PCrel 1
160 /* Relocation type for operand */
161 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
163 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
164 the base index byte below. */
165 const reg_entry
*base_reg
;
166 const reg_entry
*index_reg
;
167 unsigned int log2_scale_factor
;
169 /* SEG gives the seg_entries of this insn. They are zero unless
170 explicit segment overrides are given. */
171 const seg_entry
*seg
[2];
173 /* PREFIX holds all the given prefix opcodes (usually null).
174 PREFIXES is the number of prefix opcodes. */
175 unsigned int prefixes
;
176 unsigned char prefix
[MAX_PREFIXES
];
178 /* RM and SIB are the modrm byte and the sib byte where the
179 addressing modes of this insn are encoded. */
186 typedef struct _i386_insn i386_insn
;
188 /* List of chars besides those in app.c:symbol_chars that can start an
189 operand. Used to prevent the scrubber eating vital white-space. */
190 const char extra_symbol_chars
[] = "*%-(["
199 #if (defined (TE_I386AIX) \
200 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
201 && !defined (TE_GNU) \
202 && !defined (TE_LINUX) \
203 && !defined (TE_NETWARE) \
204 && !defined (TE_FreeBSD) \
205 && !defined (TE_NetBSD)))
206 /* This array holds the chars that always start a comment. If the
207 pre-processor is disabled, these aren't very useful. The option
208 --divide will remove '/' from this list. */
209 const char *i386_comment_chars
= "#/";
210 #define SVR4_COMMENT_CHARS 1
211 #define PREFIX_SEPARATOR '\\'
214 const char *i386_comment_chars
= "#";
215 #define PREFIX_SEPARATOR '/'
218 /* This array holds the chars that only start a comment at the beginning of
219 a line. If the line seems to have the form '# 123 filename'
220 .line and .file directives will appear in the pre-processed output.
221 Note that input_file.c hand checks for '#' at the beginning of the
222 first line of the input file. This is because the compiler outputs
223 #NO_APP at the beginning of its output.
224 Also note that comments started like this one will always work if
225 '/' isn't otherwise defined. */
226 const char line_comment_chars
[] = "#/";
228 const char line_separator_chars
[] = ";";
230 /* Chars that can be used to separate mant from exp in floating point
232 const char EXP_CHARS
[] = "eE";
234 /* Chars that mean this number is a floating point constant
237 const char FLT_CHARS
[] = "fFdDxX";
239 /* Tables for lexical analysis. */
240 static char mnemonic_chars
[256];
241 static char register_chars
[256];
242 static char operand_chars
[256];
243 static char identifier_chars
[256];
244 static char digit_chars
[256];
246 /* Lexical macros. */
247 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
248 #define is_operand_char(x) (operand_chars[(unsigned char) x])
249 #define is_register_char(x) (register_chars[(unsigned char) x])
250 #define is_space_char(x) ((x) == ' ')
251 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
252 #define is_digit_char(x) (digit_chars[(unsigned char) x])
254 /* All non-digit non-letter characters that may occur in an operand. */
255 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
257 /* md_assemble() always leaves the strings it's passed unaltered. To
258 effect this we maintain a stack of saved characters that we've smashed
259 with '\0's (indicating end of strings for various sub-fields of the
260 assembler instruction). */
261 static char save_stack
[32];
262 static char *save_stack_p
;
263 #define END_STRING_AND_SAVE(s) \
264 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
265 #define RESTORE_END_STRING(s) \
266 do { *(s) = *--save_stack_p; } while (0)
268 /* The instruction we're assembling. */
271 /* Possible templates for current insn. */
272 static const templates
*current_templates
;
274 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
275 static expressionS disp_expressions
[2], im_expressions
[2];
277 /* Current operand we are working on. */
278 static int this_operand
;
280 /* We support four different modes. FLAG_CODE variable is used to distinguish
287 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
289 static enum flag_code flag_code
;
290 static unsigned int object_64bit
;
291 static int use_rela_relocations
= 0;
293 /* The names used to print error messages. */
294 static const char *flag_code_names
[] =
301 /* 1 for intel syntax,
303 static int intel_syntax
= 0;
305 /* 1 if register prefix % not required. */
306 static int allow_naked_reg
= 0;
308 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
309 leave, push, and pop instructions so that gcc has the same stack
310 frame as in 32 bit mode. */
311 static char stackop_size
= '\0';
313 /* Non-zero to optimize code alignment. */
314 int optimize_align_code
= 1;
316 /* Non-zero to quieten some warnings. */
317 static int quiet_warnings
= 0;
320 static const char *cpu_arch_name
= NULL
;
321 static const char *cpu_sub_arch_name
= NULL
;
323 /* CPU feature flags. */
324 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
326 /* If set, conditional jumps are not automatically promoted to handle
327 larger than a byte offset. */
328 static unsigned int no_cond_jump_promotion
= 0;
330 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
331 static symbolS
*GOT_symbol
;
333 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
334 unsigned int x86_dwarf2_return_column
;
336 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
337 int x86_cie_data_alignment
;
339 /* Interface to relax_segment.
340 There are 3 major relax states for 386 jump insns because the
341 different types of jumps add different sizes to frags when we're
342 figuring out what sort of jump to choose to reach a given label. */
345 #define UNCOND_JUMP 0
347 #define COND_JUMP86 2
352 #define SMALL16 (SMALL | CODE16)
354 #define BIG16 (BIG | CODE16)
358 #define INLINE __inline__
364 #define ENCODE_RELAX_STATE(type, size) \
365 ((relax_substateT) (((type) << 2) | (size)))
366 #define TYPE_FROM_RELAX_STATE(s) \
368 #define DISP_SIZE_FROM_RELAX_STATE(s) \
369 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
371 /* This table is used by relax_frag to promote short jumps to long
372 ones where necessary. SMALL (short) jumps may be promoted to BIG
373 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
374 don't allow a short jump in a 32 bit code segment to be promoted to
375 a 16 bit offset jump because it's slower (requires data size
376 prefix), and doesn't work, unless the destination is in the bottom
377 64k of the code segment (The top 16 bits of eip are zeroed). */
379 const relax_typeS md_relax_table
[] =
382 1) most positive reach of this state,
383 2) most negative reach of this state,
384 3) how many bytes this mode will have in the variable part of the frag
385 4) which index into the table to try if we can't fit into this one. */
387 /* UNCOND_JUMP states. */
388 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
389 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
390 /* dword jmp adds 4 bytes to frag:
391 0 extra opcode bytes, 4 displacement bytes. */
393 /* word jmp adds 2 byte2 to frag:
394 0 extra opcode bytes, 2 displacement bytes. */
397 /* COND_JUMP states. */
398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
400 /* dword conditionals adds 5 bytes to frag:
401 1 extra opcode byte, 4 displacement bytes. */
403 /* word conditionals add 3 bytes to frag:
404 1 extra opcode byte, 2 displacement bytes. */
407 /* COND_JUMP86 states. */
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
410 /* dword conditionals adds 5 bytes to frag:
411 1 extra opcode byte, 4 displacement bytes. */
413 /* word conditionals add 4 bytes to frag:
414 1 displacement byte and a 3 byte long branch insn. */
418 static const arch_entry cpu_arch
[] = {
420 {"i186", Cpu086
|Cpu186
},
421 {"i286", Cpu086
|Cpu186
|Cpu286
},
422 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
423 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
424 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
425 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
426 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
427 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
428 {"pentiumii", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
},
429 {"pentiumiii",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuMMX2
|CpuSSE
},
430 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
431 {"prescott", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuPNI
},
432 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
},
433 {"k6_2", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
434 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
435 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
436 {"opteron", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
438 {".sse", CpuMMX
|CpuMMX2
|CpuSSE
},
439 {".sse2", CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
440 {".sse3", CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
441 {".3dnow", CpuMMX
|Cpu3dnow
},
442 {".3dnowa", CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
443 {".padlock", CpuPadLock
},
444 {".pacifica", CpuSVME
},
449 const pseudo_typeS md_pseudo_table
[] =
451 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
452 {"align", s_align_bytes
, 0},
454 {"align", s_align_ptwo
, 0},
456 {"arch", set_cpu_arch
, 0},
460 {"ffloat", float_cons
, 'f'},
461 {"dfloat", float_cons
, 'd'},
462 {"tfloat", float_cons
, 'x'},
464 {"slong", signed_cons
, 4},
465 {"noopt", s_ignore
, 0},
466 {"optim", s_ignore
, 0},
467 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
468 {"code16", set_code_flag
, CODE_16BIT
},
469 {"code32", set_code_flag
, CODE_32BIT
},
470 {"code64", set_code_flag
, CODE_64BIT
},
471 {"intel_syntax", set_intel_syntax
, 1},
472 {"att_syntax", set_intel_syntax
, 0},
473 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
474 {"largecomm", handle_large_common
, 0},
476 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0},
477 {"loc", dwarf2_directive_loc
, 0},
478 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
481 {"secrel32", pe_directive_secrel
, 0},
486 /* For interface with expression (). */
487 extern char *input_line_pointer
;
489 /* Hash table for instruction mnemonic lookup. */
490 static struct hash_control
*op_hash
;
492 /* Hash table for register lookup. */
493 static struct hash_control
*reg_hash
;
496 i386_align_code (fragP
, count
)
500 /* Various efficient no-op patterns for aligning code labels.
501 Note: Don't try to assemble the instructions in the comments.
502 0L and 0w are not legal. */
503 static const char f32_1
[] =
505 static const char f32_2
[] =
506 {0x89,0xf6}; /* movl %esi,%esi */
507 static const char f32_3
[] =
508 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
509 static const char f32_4
[] =
510 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
511 static const char f32_5
[] =
513 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
514 static const char f32_6
[] =
515 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
516 static const char f32_7
[] =
517 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
518 static const char f32_8
[] =
520 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
521 static const char f32_9
[] =
522 {0x89,0xf6, /* movl %esi,%esi */
523 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
524 static const char f32_10
[] =
525 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
526 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
527 static const char f32_11
[] =
528 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
529 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
530 static const char f32_12
[] =
531 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
532 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
533 static const char f32_13
[] =
534 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
535 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
536 static const char f32_14
[] =
537 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
538 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
539 static const char f32_15
[] =
540 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
541 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
542 static const char f16_3
[] =
543 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
544 static const char f16_4
[] =
545 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
546 static const char f16_5
[] =
548 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
549 static const char f16_6
[] =
550 {0x89,0xf6, /* mov %si,%si */
551 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
552 static const char f16_7
[] =
553 {0x8d,0x74,0x00, /* lea 0(%si),%si */
554 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
555 static const char f16_8
[] =
556 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
557 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
558 static const char *const f32_patt
[] = {
559 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
560 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
562 static const char *const f16_patt
[] = {
563 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
564 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
567 if (count
<= 0 || count
> 15)
570 /* The recommended way to pad 64bit code is to use NOPs preceded by
571 maximally four 0x66 prefixes. Balance the size of nops. */
572 if (flag_code
== CODE_64BIT
)
575 int nnops
= (count
+ 3) / 4;
576 int len
= count
/ nnops
;
577 int remains
= count
- nnops
* len
;
580 for (i
= 0; i
< remains
; i
++)
582 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
583 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
586 for (; i
< nnops
; i
++)
588 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
589 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
594 if (flag_code
== CODE_16BIT
)
596 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
597 f16_patt
[count
- 1], count
);
599 /* Adjust jump offset. */
600 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
603 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
604 f32_patt
[count
- 1], count
);
605 fragP
->fr_var
= count
;
608 static INLINE
unsigned int
609 mode_from_disp_size (t
)
612 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
616 fits_in_signed_byte (num
)
619 return (num
>= -128) && (num
<= 127);
623 fits_in_unsigned_byte (num
)
626 return (num
& 0xff) == num
;
630 fits_in_unsigned_word (num
)
633 return (num
& 0xffff) == num
;
637 fits_in_signed_word (num
)
640 return (-32768 <= num
) && (num
<= 32767);
643 fits_in_signed_long (num
)
644 offsetT num ATTRIBUTE_UNUSED
;
649 return (!(((offsetT
) -1 << 31) & num
)
650 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
652 } /* fits_in_signed_long() */
654 fits_in_unsigned_long (num
)
655 offsetT num ATTRIBUTE_UNUSED
;
660 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
662 } /* fits_in_unsigned_long() */
665 smallest_imm_type (num
)
668 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
670 /* This code is disabled on the 486 because all the Imm1 forms
671 in the opcode table are slower on the i486. They're the
672 versions with the implicitly specified single-position
673 displacement, which has another syntax if you really want to
676 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
678 return (fits_in_signed_byte (num
)
679 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
680 : fits_in_unsigned_byte (num
)
681 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
682 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
683 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
684 : fits_in_signed_long (num
)
685 ? (Imm32
| Imm32S
| Imm64
)
686 : fits_in_unsigned_long (num
)
692 offset_in_range (val
, size
)
700 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
701 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
702 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
704 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
709 /* If BFD64, sign extend val. */
710 if (!use_rela_relocations
)
711 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
712 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
714 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
716 char buf1
[40], buf2
[40];
718 sprint_value (buf1
, val
);
719 sprint_value (buf2
, val
& mask
);
720 as_warn (_("%s shortened to %s"), buf1
, buf2
);
725 /* Returns 0 if attempting to add a prefix where one from the same
726 class already exists, 1 if non rep/repne added, 2 if rep/repne
735 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
736 && flag_code
== CODE_64BIT
)
738 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_MODE64
)
739 || ((i
.prefix
[REX_PREFIX
] & (REX_EXTX
| REX_EXTY
| REX_EXTZ
))
740 && (prefix
& (REX_EXTX
| REX_EXTY
| REX_EXTZ
))))
751 case CS_PREFIX_OPCODE
:
752 case DS_PREFIX_OPCODE
:
753 case ES_PREFIX_OPCODE
:
754 case FS_PREFIX_OPCODE
:
755 case GS_PREFIX_OPCODE
:
756 case SS_PREFIX_OPCODE
:
760 case REPNE_PREFIX_OPCODE
:
761 case REPE_PREFIX_OPCODE
:
764 case LOCK_PREFIX_OPCODE
:
772 case ADDR_PREFIX_OPCODE
:
776 case DATA_PREFIX_OPCODE
:
780 if (i
.prefix
[q
] != 0)
788 i
.prefix
[q
] |= prefix
;
791 as_bad (_("same type of prefix used twice"));
797 set_code_flag (value
)
801 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
802 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
803 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
805 as_bad (_("64bit mode not supported on this CPU."));
807 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
809 as_bad (_("32bit mode not supported on this CPU."));
815 set_16bit_gcc_code_flag (new_code_flag
)
818 flag_code
= new_code_flag
;
819 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
820 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
821 stackop_size
= LONG_MNEM_SUFFIX
;
825 set_intel_syntax (syntax_flag
)
828 /* Find out if register prefixing is specified. */
829 int ask_naked_reg
= 0;
832 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
834 char *string
= input_line_pointer
;
835 int e
= get_symbol_end ();
837 if (strcmp (string
, "prefix") == 0)
839 else if (strcmp (string
, "noprefix") == 0)
842 as_bad (_("bad argument to syntax directive."));
843 *input_line_pointer
= e
;
845 demand_empty_rest_of_line ();
847 intel_syntax
= syntax_flag
;
849 if (ask_naked_reg
== 0)
850 allow_naked_reg
= (intel_syntax
851 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
853 allow_naked_reg
= (ask_naked_reg
< 0);
855 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
856 identifier_chars
['$'] = intel_syntax
? '$' : 0;
861 int dummy ATTRIBUTE_UNUSED
;
865 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
867 char *string
= input_line_pointer
;
868 int e
= get_symbol_end ();
871 for (i
= 0; cpu_arch
[i
].name
; i
++)
873 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
877 cpu_arch_name
= cpu_arch
[i
].name
;
878 cpu_sub_arch_name
= NULL
;
879 cpu_arch_flags
= (cpu_arch
[i
].flags
880 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
883 if ((cpu_arch_flags
| cpu_arch
[i
].flags
) != cpu_arch_flags
)
885 cpu_sub_arch_name
= cpu_arch
[i
].name
;
886 cpu_arch_flags
|= cpu_arch
[i
].flags
;
888 *input_line_pointer
= e
;
889 demand_empty_rest_of_line ();
893 if (!cpu_arch
[i
].name
)
894 as_bad (_("no such architecture: `%s'"), string
);
896 *input_line_pointer
= e
;
899 as_bad (_("missing cpu architecture"));
901 no_cond_jump_promotion
= 0;
902 if (*input_line_pointer
== ','
903 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
905 char *string
= ++input_line_pointer
;
906 int e
= get_symbol_end ();
908 if (strcmp (string
, "nojumps") == 0)
909 no_cond_jump_promotion
= 1;
910 else if (strcmp (string
, "jumps") == 0)
913 as_bad (_("no such architecture modifier: `%s'"), string
);
915 *input_line_pointer
= e
;
918 demand_empty_rest_of_line ();
924 if (!strcmp (default_arch
, "x86_64"))
925 return bfd_mach_x86_64
;
926 else if (!strcmp (default_arch
, "i386"))
927 return bfd_mach_i386_i386
;
929 as_fatal (_("Unknown architecture"));
935 const char *hash_err
;
937 /* Initialize op_hash hash table. */
938 op_hash
= hash_new ();
941 const template *optab
;
942 templates
*core_optab
;
944 /* Setup for loop. */
946 core_optab
= (templates
*) xmalloc (sizeof (templates
));
947 core_optab
->start
= optab
;
952 if (optab
->name
== NULL
953 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
955 /* different name --> ship out current template list;
956 add to hash table; & begin anew. */
957 core_optab
->end
= optab
;
958 hash_err
= hash_insert (op_hash
,
963 as_fatal (_("Internal Error: Can't hash %s: %s"),
967 if (optab
->name
== NULL
)
969 core_optab
= (templates
*) xmalloc (sizeof (templates
));
970 core_optab
->start
= optab
;
975 /* Initialize reg_hash hash table. */
976 reg_hash
= hash_new ();
978 const reg_entry
*regtab
;
980 for (regtab
= i386_regtab
;
981 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
984 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
986 as_fatal (_("Internal Error: Can't hash %s: %s"),
992 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
997 for (c
= 0; c
< 256; c
++)
1002 mnemonic_chars
[c
] = c
;
1003 register_chars
[c
] = c
;
1004 operand_chars
[c
] = c
;
1006 else if (ISLOWER (c
))
1008 mnemonic_chars
[c
] = c
;
1009 register_chars
[c
] = c
;
1010 operand_chars
[c
] = c
;
1012 else if (ISUPPER (c
))
1014 mnemonic_chars
[c
] = TOLOWER (c
);
1015 register_chars
[c
] = mnemonic_chars
[c
];
1016 operand_chars
[c
] = c
;
1019 if (ISALPHA (c
) || ISDIGIT (c
))
1020 identifier_chars
[c
] = c
;
1023 identifier_chars
[c
] = c
;
1024 operand_chars
[c
] = c
;
1029 identifier_chars
['@'] = '@';
1032 identifier_chars
['?'] = '?';
1033 operand_chars
['?'] = '?';
1035 digit_chars
['-'] = '-';
1036 mnemonic_chars
['-'] = '-';
1037 identifier_chars
['_'] = '_';
1038 identifier_chars
['.'] = '.';
1040 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1041 operand_chars
[(unsigned char) *p
] = *p
;
1044 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1047 record_alignment (text_section
, 2);
1048 record_alignment (data_section
, 2);
1049 record_alignment (bss_section
, 2);
1053 if (flag_code
== CODE_64BIT
)
1055 x86_dwarf2_return_column
= 16;
1056 x86_cie_data_alignment
= -8;
1060 x86_dwarf2_return_column
= 8;
1061 x86_cie_data_alignment
= -4;
1066 i386_print_statistics (file
)
1069 hash_print_statistics (file
, "i386 opcode", op_hash
);
1070 hash_print_statistics (file
, "i386 register", reg_hash
);
1075 /* Debugging routines for md_assemble. */
1076 static void pi
PARAMS ((char *, i386_insn
*));
1077 static void pte
PARAMS ((template *));
1078 static void pt
PARAMS ((unsigned int));
1079 static void pe
PARAMS ((expressionS
*));
1080 static void ps
PARAMS ((symbolS
*));
1089 fprintf (stdout
, "%s: template ", line
);
1091 fprintf (stdout
, " address: base %s index %s scale %x\n",
1092 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1093 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1094 x
->log2_scale_factor
);
1095 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1096 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1097 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1098 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1099 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1100 (x
->rex
& REX_MODE64
) != 0,
1101 (x
->rex
& REX_EXTX
) != 0,
1102 (x
->rex
& REX_EXTY
) != 0,
1103 (x
->rex
& REX_EXTZ
) != 0);
1104 for (i
= 0; i
< x
->operands
; i
++)
1106 fprintf (stdout
, " #%d: ", i
+ 1);
1108 fprintf (stdout
, "\n");
1110 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1111 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1112 if (x
->types
[i
] & Imm
)
1114 if (x
->types
[i
] & Disp
)
1115 pe (x
->op
[i
].disps
);
1124 fprintf (stdout
, " %d operands ", t
->operands
);
1125 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1126 if (t
->extension_opcode
!= None
)
1127 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1128 if (t
->opcode_modifier
& D
)
1129 fprintf (stdout
, "D");
1130 if (t
->opcode_modifier
& W
)
1131 fprintf (stdout
, "W");
1132 fprintf (stdout
, "\n");
1133 for (i
= 0; i
< t
->operands
; i
++)
1135 fprintf (stdout
, " #%d type ", i
+ 1);
1136 pt (t
->operand_types
[i
]);
1137 fprintf (stdout
, "\n");
1145 fprintf (stdout
, " operation %d\n", e
->X_op
);
1146 fprintf (stdout
, " add_number %ld (%lx)\n",
1147 (long) e
->X_add_number
, (long) e
->X_add_number
);
1148 if (e
->X_add_symbol
)
1150 fprintf (stdout
, " add_symbol ");
1151 ps (e
->X_add_symbol
);
1152 fprintf (stdout
, "\n");
1156 fprintf (stdout
, " op_symbol ");
1157 ps (e
->X_op_symbol
);
1158 fprintf (stdout
, "\n");
1166 fprintf (stdout
, "%s type %s%s",
1168 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1169 segment_name (S_GET_SEGMENT (s
)));
1172 static struct type_name
1177 const type_names
[] =
1190 { BaseIndex
, "BaseIndex" },
1194 { Disp32S
, "d32s" },
1196 { InOutPortReg
, "InOutPortReg" },
1197 { ShiftCount
, "ShiftCount" },
1198 { Control
, "control reg" },
1199 { Test
, "test reg" },
1200 { Debug
, "debug reg" },
1201 { FloatReg
, "FReg" },
1202 { FloatAcc
, "FAcc" },
1206 { JumpAbsolute
, "Jump Absolute" },
1217 const struct type_name
*ty
;
1219 for (ty
= type_names
; ty
->mask
; ty
++)
1221 fprintf (stdout
, "%s, ", ty
->tname
);
1225 #endif /* DEBUG386 */
1227 static bfd_reloc_code_real_type
1228 reloc (unsigned int size
,
1231 bfd_reloc_code_real_type other
)
1233 if (other
!= NO_RELOC
)
1235 reloc_howto_type
*reloc
;
1240 case BFD_RELOC_X86_64_GOT32
:
1241 return BFD_RELOC_X86_64_GOT64
;
1243 case BFD_RELOC_X86_64_PLTOFF64
:
1244 return BFD_RELOC_X86_64_PLTOFF64
;
1246 case BFD_RELOC_X86_64_GOTPC32
:
1247 other
= BFD_RELOC_X86_64_GOTPC64
;
1249 case BFD_RELOC_X86_64_GOTPCREL
:
1250 other
= BFD_RELOC_X86_64_GOTPCREL64
;
1252 case BFD_RELOC_X86_64_TPOFF32
:
1253 other
= BFD_RELOC_X86_64_TPOFF64
;
1255 case BFD_RELOC_X86_64_DTPOFF32
:
1256 other
= BFD_RELOC_X86_64_DTPOFF64
;
1262 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1263 if (size
== 4 && flag_code
!= CODE_64BIT
)
1266 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
1268 as_bad (_("unknown relocation (%u)"), other
);
1269 else if (size
!= bfd_get_reloc_size (reloc
))
1270 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1271 bfd_get_reloc_size (reloc
),
1273 else if (pcrel
&& !reloc
->pc_relative
)
1274 as_bad (_("non-pc-relative relocation for pc-relative field"));
1275 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
1277 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
1279 as_bad (_("relocated field and relocation type differ in signedness"));
1288 as_bad (_("there are no unsigned pc-relative relocations"));
1291 case 1: return BFD_RELOC_8_PCREL
;
1292 case 2: return BFD_RELOC_16_PCREL
;
1293 case 4: return BFD_RELOC_32_PCREL
;
1294 case 8: return BFD_RELOC_64_PCREL
;
1296 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
1303 case 4: return BFD_RELOC_X86_64_32S
;
1308 case 1: return BFD_RELOC_8
;
1309 case 2: return BFD_RELOC_16
;
1310 case 4: return BFD_RELOC_32
;
1311 case 8: return BFD_RELOC_64
;
1313 as_bad (_("cannot do %s %u byte relocation"),
1314 sign
> 0 ? "signed" : "unsigned", size
);
1318 return BFD_RELOC_NONE
;
1321 /* Here we decide which fixups can be adjusted to make them relative to
1322 the beginning of the section instead of the symbol. Basically we need
1323 to make sure that the dynamic relocations are done correctly, so in
1324 some cases we force the original symbol to be used. */
1327 tc_i386_fix_adjustable (fixP
)
1328 fixS
*fixP ATTRIBUTE_UNUSED
;
1330 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1334 /* Don't adjust pc-relative references to merge sections in 64-bit
1336 if (use_rela_relocations
1337 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1341 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1342 and changed later by validate_fix. */
1343 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
1344 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
1347 /* adjust_reloc_syms doesn't know about the GOT. */
1348 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1349 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1350 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1351 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1352 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1353 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1354 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1355 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1356 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1357 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1358 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1359 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
1360 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
1361 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1362 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1363 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1364 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1365 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1366 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1367 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
1368 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1369 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1370 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
1371 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
1372 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
1373 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
1374 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1375 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1381 static int intel_float_operand
PARAMS ((const char *mnemonic
));
1384 intel_float_operand (mnemonic
)
1385 const char *mnemonic
;
1387 /* Note that the value returned is meaningful only for opcodes with (memory)
1388 operands, hence the code here is free to improperly handle opcodes that
1389 have no operands (for better performance and smaller code). */
1391 if (mnemonic
[0] != 'f')
1392 return 0; /* non-math */
1394 switch (mnemonic
[1])
1396 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1397 the fs segment override prefix not currently handled because no
1398 call path can make opcodes without operands get here */
1400 return 2 /* integer op */;
1402 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
1403 return 3; /* fldcw/fldenv */
1406 if (mnemonic
[2] != 'o' /* fnop */)
1407 return 3; /* non-waiting control op */
1410 if (mnemonic
[2] == 's')
1411 return 3; /* frstor/frstpm */
1414 if (mnemonic
[2] == 'a')
1415 return 3; /* fsave */
1416 if (mnemonic
[2] == 't')
1418 switch (mnemonic
[3])
1420 case 'c': /* fstcw */
1421 case 'd': /* fstdw */
1422 case 'e': /* fstenv */
1423 case 's': /* fsts[gw] */
1429 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
1430 return 0; /* fxsave/fxrstor are not really math ops */
1437 /* This is the guts of the machine-dependent assembler. LINE points to a
1438 machine dependent instruction. This function is supposed to emit
1439 the frags/bytes it assembles to. */
1446 char mnemonic
[MAX_MNEM_SIZE
];
1448 /* Initialize globals. */
1449 memset (&i
, '\0', sizeof (i
));
1450 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1451 i
.reloc
[j
] = NO_RELOC
;
1452 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1453 memset (im_expressions
, '\0', sizeof (im_expressions
));
1454 save_stack_p
= save_stack
;
1456 /* First parse an instruction mnemonic & call i386_operand for the operands.
1457 We assume that the scrubber has arranged it so that line[0] is the valid
1458 start of a (possibly prefixed) mnemonic. */
1460 line
= parse_insn (line
, mnemonic
);
1464 line
= parse_operands (line
, mnemonic
);
1468 /* Now we've parsed the mnemonic into a set of templates, and have the
1469 operands at hand. */
1471 /* All intel opcodes have reversed operands except for "bound" and
1472 "enter". We also don't reverse intersegment "jmp" and "call"
1473 instructions with 2 immediate operands so that the immediate segment
1474 precedes the offset, as it does when in AT&T mode. "enter" and the
1475 intersegment "jmp" and "call" instructions are the only ones that
1476 have two immediate operands. */
1477 if (intel_syntax
&& i
.operands
> 1
1478 && (strcmp (mnemonic
, "bound") != 0)
1479 && (strcmp (mnemonic
, "invlpga") != 0)
1480 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1486 /* Don't optimize displacement for movabs since it only takes 64bit
1489 && (flag_code
!= CODE_64BIT
1490 || strcmp (mnemonic
, "movabs") != 0))
1493 /* Next, we find a template that matches the given insn,
1494 making sure the overlap of the given operands types is consistent
1495 with the template operand types. */
1497 if (!match_template ())
1502 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1504 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1505 i
.tm
.base_opcode
^= FloatR
;
1507 /* Zap movzx and movsx suffix. The suffix may have been set from
1508 "word ptr" or "byte ptr" on the source operand, but we'll use
1509 the suffix later to choose the destination register. */
1510 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1512 if (i
.reg_operands
< 2
1514 && (~i
.tm
.opcode_modifier
1521 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
1527 if (i
.tm
.opcode_modifier
& FWait
)
1528 if (!add_prefix (FWAIT_OPCODE
))
1531 /* Check string instruction segment overrides. */
1532 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1534 if (!check_string ())
1538 if (!process_suffix ())
1541 /* Make still unresolved immediate matches conform to size of immediate
1542 given in i.suffix. */
1543 if (!finalize_imm ())
1546 if (i
.types
[0] & Imm1
)
1547 i
.imm_operands
= 0; /* kludge for shift insns. */
1548 if (i
.types
[0] & ImplicitRegister
)
1550 if (i
.types
[1] & ImplicitRegister
)
1552 if (i
.types
[2] & ImplicitRegister
)
1555 if (i
.tm
.opcode_modifier
& ImmExt
)
1559 if ((i
.tm
.cpu_flags
& CpuPNI
) && i
.operands
> 0)
1561 /* These Intel Prescott New Instructions have the fixed
1562 operands with an opcode suffix which is coded in the same
1563 place as an 8-bit immediate field would be. Here we check
1564 those operands and remove them afterwards. */
1567 for (x
= 0; x
< i
.operands
; x
++)
1568 if (i
.op
[x
].regs
->reg_num
!= x
)
1569 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1570 i
.op
[x
].regs
->reg_name
, x
+ 1, i
.tm
.name
);
1574 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1575 opcode suffix which is coded in the same place as an 8-bit
1576 immediate field would be. Here we fake an 8-bit immediate
1577 operand from the opcode suffix stored in tm.extension_opcode. */
1579 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1581 exp
= &im_expressions
[i
.imm_operands
++];
1582 i
.op
[i
.operands
].imms
= exp
;
1583 i
.types
[i
.operands
++] = Imm8
;
1584 exp
->X_op
= O_constant
;
1585 exp
->X_add_number
= i
.tm
.extension_opcode
;
1586 i
.tm
.extension_opcode
= None
;
1589 /* For insns with operands there are more diddles to do to the opcode. */
1592 if (!process_operands ())
1595 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1597 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1598 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1601 /* Handle conversion of 'int $3' --> special int3 insn. */
1602 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1604 i
.tm
.base_opcode
= INT3_OPCODE
;
1608 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1609 && i
.op
[0].disps
->X_op
== O_constant
)
1611 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1612 the absolute address given by the constant. Since ix86 jumps and
1613 calls are pc relative, we need to generate a reloc. */
1614 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1615 i
.op
[0].disps
->X_op
= O_symbol
;
1618 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1619 i
.rex
|= REX_MODE64
;
1621 /* For 8 bit registers we need an empty rex prefix. Also if the
1622 instruction already has a prefix, we need to convert old
1623 registers to new ones. */
1625 if (((i
.types
[0] & Reg8
) != 0
1626 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1627 || ((i
.types
[1] & Reg8
) != 0
1628 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1629 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1634 i
.rex
|= REX_OPCODE
;
1635 for (x
= 0; x
< 2; x
++)
1637 /* Look for 8 bit operand that uses old registers. */
1638 if ((i
.types
[x
] & Reg8
) != 0
1639 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1641 /* In case it is "hi" register, give up. */
1642 if (i
.op
[x
].regs
->reg_num
> 3)
1643 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1644 i
.op
[x
].regs
->reg_name
);
1646 /* Otherwise it is equivalent to the extended register.
1647 Since the encoding doesn't change this is merely
1648 cosmetic cleanup for debug output. */
1650 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1656 add_prefix (REX_OPCODE
| i
.rex
);
1658 /* We are ready to output the insn. */
1663 parse_insn (line
, mnemonic
)
1668 char *token_start
= l
;
1673 /* Non-zero if we found a prefix only acceptable with string insns. */
1674 const char *expecting_string_instruction
= NULL
;
1679 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1682 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1684 as_bad (_("no such instruction: `%s'"), token_start
);
1689 if (!is_space_char (*l
)
1690 && *l
!= END_OF_INSN
1692 || (*l
!= PREFIX_SEPARATOR
1695 as_bad (_("invalid character %s in mnemonic"),
1696 output_invalid (*l
));
1699 if (token_start
== l
)
1701 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
1702 as_bad (_("expecting prefix; got nothing"));
1704 as_bad (_("expecting mnemonic; got nothing"));
1708 /* Look up instruction (or prefix) via hash table. */
1709 current_templates
= hash_find (op_hash
, mnemonic
);
1711 if (*l
!= END_OF_INSN
1712 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1713 && current_templates
1714 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1716 if (current_templates
->start
->cpu_flags
1717 & (flag_code
!= CODE_64BIT
? Cpu64
: CpuNo64
))
1719 as_bad ((flag_code
!= CODE_64BIT
1720 ? _("`%s' is only supported in 64-bit mode")
1721 : _("`%s' is not supported in 64-bit mode")),
1722 current_templates
->start
->name
);
1725 /* If we are in 16-bit mode, do not allow addr16 or data16.
1726 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1727 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1728 && flag_code
!= CODE_64BIT
1729 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1730 ^ (flag_code
== CODE_16BIT
)))
1732 as_bad (_("redundant %s prefix"),
1733 current_templates
->start
->name
);
1736 /* Add prefix, checking for repeated prefixes. */
1737 switch (add_prefix (current_templates
->start
->base_opcode
))
1742 expecting_string_instruction
= current_templates
->start
->name
;
1745 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1752 if (!current_templates
)
1754 /* See if we can get a match by trimming off a suffix. */
1757 case WORD_MNEM_SUFFIX
:
1758 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
1759 i
.suffix
= SHORT_MNEM_SUFFIX
;
1761 case BYTE_MNEM_SUFFIX
:
1762 case QWORD_MNEM_SUFFIX
:
1763 i
.suffix
= mnem_p
[-1];
1765 current_templates
= hash_find (op_hash
, mnemonic
);
1767 case SHORT_MNEM_SUFFIX
:
1768 case LONG_MNEM_SUFFIX
:
1771 i
.suffix
= mnem_p
[-1];
1773 current_templates
= hash_find (op_hash
, mnemonic
);
1781 if (intel_float_operand (mnemonic
) == 1)
1782 i
.suffix
= SHORT_MNEM_SUFFIX
;
1784 i
.suffix
= LONG_MNEM_SUFFIX
;
1786 current_templates
= hash_find (op_hash
, mnemonic
);
1790 if (!current_templates
)
1792 as_bad (_("no such instruction: `%s'"), token_start
);
1797 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1799 /* Check for a branch hint. We allow ",pt" and ",pn" for
1800 predict taken and predict not taken respectively.
1801 I'm not sure that branch hints actually do anything on loop
1802 and jcxz insns (JumpByte) for current Pentium4 chips. They
1803 may work in the future and it doesn't hurt to accept them
1805 if (l
[0] == ',' && l
[1] == 'p')
1809 if (!add_prefix (DS_PREFIX_OPCODE
))
1813 else if (l
[2] == 'n')
1815 if (!add_prefix (CS_PREFIX_OPCODE
))
1821 /* Any other comma loses. */
1824 as_bad (_("invalid character %s in mnemonic"),
1825 output_invalid (*l
));
1829 /* Check if instruction is supported on specified architecture. */
1831 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
1833 if (!((t
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1834 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
))))
1836 if (!(t
->cpu_flags
& (flag_code
== CODE_64BIT
? CpuNo64
: Cpu64
)))
1839 if (!(supported
& 2))
1841 as_bad (flag_code
== CODE_64BIT
1842 ? _("`%s' is not supported in 64-bit mode")
1843 : _("`%s' is only supported in 64-bit mode"),
1844 current_templates
->start
->name
);
1847 if (!(supported
& 1))
1849 as_warn (_("`%s' is not supported on `%s%s'"),
1850 current_templates
->start
->name
,
1852 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
1854 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1856 as_warn (_("use .code16 to ensure correct addressing mode"));
1859 /* Check for rep/repne without a string instruction. */
1860 if (expecting_string_instruction
)
1862 static templates override
;
1864 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
1865 if (t
->opcode_modifier
& IsString
)
1867 if (t
>= current_templates
->end
)
1869 as_bad (_("expecting string instruction after `%s'"),
1870 expecting_string_instruction
);
1873 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
1874 if (!(t
->opcode_modifier
& IsString
))
1877 current_templates
= &override
;
1884 parse_operands (l
, mnemonic
)
1886 const char *mnemonic
;
1890 /* 1 if operand is pending after ','. */
1891 unsigned int expecting_operand
= 0;
1893 /* Non-zero if operand parens not balanced. */
1894 unsigned int paren_not_balanced
;
1896 while (*l
!= END_OF_INSN
)
1898 /* Skip optional white space before operand. */
1899 if (is_space_char (*l
))
1901 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1903 as_bad (_("invalid character %s before operand %d"),
1904 output_invalid (*l
),
1908 token_start
= l
; /* after white space */
1909 paren_not_balanced
= 0;
1910 while (paren_not_balanced
|| *l
!= ',')
1912 if (*l
== END_OF_INSN
)
1914 if (paren_not_balanced
)
1917 as_bad (_("unbalanced parenthesis in operand %d."),
1920 as_bad (_("unbalanced brackets in operand %d."),
1925 break; /* we are done */
1927 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1929 as_bad (_("invalid character %s in operand %d"),
1930 output_invalid (*l
),
1937 ++paren_not_balanced
;
1939 --paren_not_balanced
;
1944 ++paren_not_balanced
;
1946 --paren_not_balanced
;
1950 if (l
!= token_start
)
1951 { /* Yes, we've read in another operand. */
1952 unsigned int operand_ok
;
1953 this_operand
= i
.operands
++;
1954 if (i
.operands
> MAX_OPERANDS
)
1956 as_bad (_("spurious operands; (%d operands/instruction max)"),
1960 /* Now parse operand adding info to 'i' as we go along. */
1961 END_STRING_AND_SAVE (l
);
1965 i386_intel_operand (token_start
,
1966 intel_float_operand (mnemonic
));
1968 operand_ok
= i386_operand (token_start
);
1970 RESTORE_END_STRING (l
);
1976 if (expecting_operand
)
1978 expecting_operand_after_comma
:
1979 as_bad (_("expecting operand after ','; got nothing"));
1984 as_bad (_("expecting operand before ','; got nothing"));
1989 /* Now *l must be either ',' or END_OF_INSN. */
1992 if (*++l
== END_OF_INSN
)
1994 /* Just skip it, if it's \n complain. */
1995 goto expecting_operand_after_comma
;
1997 expecting_operand
= 1;
2006 union i386_op temp_op
;
2007 unsigned int temp_type
;
2008 enum bfd_reloc_code_real temp_reloc
;
2012 if (i
.operands
== 2)
2017 else if (i
.operands
== 3)
2022 temp_type
= i
.types
[xchg2
];
2023 i
.types
[xchg2
] = i
.types
[xchg1
];
2024 i
.types
[xchg1
] = temp_type
;
2025 temp_op
= i
.op
[xchg2
];
2026 i
.op
[xchg2
] = i
.op
[xchg1
];
2027 i
.op
[xchg1
] = temp_op
;
2028 temp_reloc
= i
.reloc
[xchg2
];
2029 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
2030 i
.reloc
[xchg1
] = temp_reloc
;
2032 if (i
.mem_operands
== 2)
2034 const seg_entry
*temp_seg
;
2035 temp_seg
= i
.seg
[0];
2036 i
.seg
[0] = i
.seg
[1];
2037 i
.seg
[1] = temp_seg
;
2041 /* Try to ensure constant immediates are represented in the smallest
2046 char guess_suffix
= 0;
2050 guess_suffix
= i
.suffix
;
2051 else if (i
.reg_operands
)
2053 /* Figure out a suffix from the last register operand specified.
2054 We can't do this properly yet, ie. excluding InOutPortReg,
2055 but the following works for instructions with immediates.
2056 In any case, we can't set i.suffix yet. */
2057 for (op
= i
.operands
; --op
>= 0;)
2058 if (i
.types
[op
] & Reg
)
2060 if (i
.types
[op
] & Reg8
)
2061 guess_suffix
= BYTE_MNEM_SUFFIX
;
2062 else if (i
.types
[op
] & Reg16
)
2063 guess_suffix
= WORD_MNEM_SUFFIX
;
2064 else if (i
.types
[op
] & Reg32
)
2065 guess_suffix
= LONG_MNEM_SUFFIX
;
2066 else if (i
.types
[op
] & Reg64
)
2067 guess_suffix
= QWORD_MNEM_SUFFIX
;
2071 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
2072 guess_suffix
= WORD_MNEM_SUFFIX
;
2074 for (op
= i
.operands
; --op
>= 0;)
2075 if (i
.types
[op
] & Imm
)
2077 switch (i
.op
[op
].imms
->X_op
)
2080 /* If a suffix is given, this operand may be shortened. */
2081 switch (guess_suffix
)
2083 case LONG_MNEM_SUFFIX
:
2084 i
.types
[op
] |= Imm32
| Imm64
;
2086 case WORD_MNEM_SUFFIX
:
2087 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
2089 case BYTE_MNEM_SUFFIX
:
2090 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
2094 /* If this operand is at most 16 bits, convert it
2095 to a signed 16 bit number before trying to see
2096 whether it will fit in an even smaller size.
2097 This allows a 16-bit operand such as $0xffe0 to
2098 be recognised as within Imm8S range. */
2099 if ((i
.types
[op
] & Imm16
)
2100 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
2102 i
.op
[op
].imms
->X_add_number
=
2103 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2105 if ((i
.types
[op
] & Imm32
)
2106 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2109 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2110 ^ ((offsetT
) 1 << 31))
2111 - ((offsetT
) 1 << 31));
2113 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
2115 /* We must avoid matching of Imm32 templates when 64bit
2116 only immediate is available. */
2117 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2118 i
.types
[op
] &= ~Imm32
;
2125 /* Symbols and expressions. */
2127 /* Convert symbolic operand to proper sizes for matching, but don't
2128 prevent matching a set of insns that only supports sizes other
2129 than those matching the insn suffix. */
2131 unsigned int mask
, allowed
= 0;
2134 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2135 allowed
|= t
->operand_types
[op
];
2136 switch (guess_suffix
)
2138 case QWORD_MNEM_SUFFIX
:
2139 mask
= Imm64
| Imm32S
;
2141 case LONG_MNEM_SUFFIX
:
2144 case WORD_MNEM_SUFFIX
:
2147 case BYTE_MNEM_SUFFIX
:
2155 i
.types
[op
] &= mask
;
2162 /* Try to use the smallest displacement type too. */
2168 for (op
= i
.operands
; --op
>= 0;)
2169 if (i
.types
[op
] & Disp
)
2171 if (i
.op
[op
].disps
->X_op
== O_constant
)
2173 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
2175 if ((i
.types
[op
] & Disp16
)
2176 && (disp
& ~(offsetT
) 0xffff) == 0)
2178 /* If this operand is at most 16 bits, convert
2179 to a signed 16 bit number and don't use 64bit
2181 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
2182 i
.types
[op
] &= ~Disp64
;
2184 if ((i
.types
[op
] & Disp32
)
2185 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
2187 /* If this operand is at most 32 bits, convert
2188 to a signed 32 bit number and don't use 64bit
2190 disp
&= (((offsetT
) 2 << 31) - 1);
2191 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
2192 i
.types
[op
] &= ~Disp64
;
2194 if (!disp
&& (i
.types
[op
] & BaseIndex
))
2196 i
.types
[op
] &= ~Disp
;
2200 else if (flag_code
== CODE_64BIT
)
2202 if (fits_in_signed_long (disp
))
2204 i
.types
[op
] &= ~Disp64
;
2205 i
.types
[op
] |= Disp32S
;
2207 if (fits_in_unsigned_long (disp
))
2208 i
.types
[op
] |= Disp32
;
2210 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
2211 && fits_in_signed_byte (disp
))
2212 i
.types
[op
] |= Disp8
;
2214 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
2215 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
2217 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
2218 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
2219 i
.types
[op
] &= ~Disp
;
2222 /* We only support 64bit displacement on constants. */
2223 i
.types
[op
] &= ~Disp64
;
2230 /* Points to template once we've found it. */
2232 unsigned int overlap0
, overlap1
, overlap2
;
2233 unsigned int found_reverse_match
;
2236 #define MATCH(overlap, given, template) \
2237 ((overlap & ~JumpAbsolute) \
2238 && (((given) & (BaseIndex | JumpAbsolute)) \
2239 == ((overlap) & (BaseIndex | JumpAbsolute))))
2241 /* If given types r0 and r1 are registers they must be of the same type
2242 unless the expected operand type register overlap is null.
2243 Note that Acc in a template matches every size of reg. */
2244 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2245 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2246 || ((g0) & Reg) == ((g1) & Reg) \
2247 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2252 found_reverse_match
= 0;
2253 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
2255 : (i
.suffix
== WORD_MNEM_SUFFIX
2257 : (i
.suffix
== SHORT_MNEM_SUFFIX
2259 : (i
.suffix
== LONG_MNEM_SUFFIX
2261 : (i
.suffix
== QWORD_MNEM_SUFFIX
2263 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
2264 ? No_xSuf
: 0))))));
2266 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
2268 /* Must have right number of operands. */
2269 if (i
.operands
!= t
->operands
)
2272 /* Check the suffix, except for some instructions in intel mode. */
2273 if ((t
->opcode_modifier
& suffix_check
)
2275 && (t
->opcode_modifier
& IgnoreSize
)))
2278 /* In general, don't allow 64-bit operands in 32-bit mode. */
2279 if (i
.suffix
== QWORD_MNEM_SUFFIX
2280 && flag_code
!= CODE_64BIT
2282 ? (!(t
->opcode_modifier
& IgnoreSize
)
2283 && !intel_float_operand (t
->name
))
2284 : intel_float_operand (t
->name
) != 2)
2285 && (!(t
->operand_types
[0] & (RegMMX
| RegXMM
))
2286 || !(t
->operand_types
[t
->operands
> 1] & (RegMMX
| RegXMM
)))
2287 && (t
->base_opcode
!= 0x0fc7
2288 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
2291 /* Do not verify operands when there are none. */
2292 else if (!t
->operands
)
2294 if (t
->cpu_flags
& ~cpu_arch_flags
)
2296 /* We've found a match; break out of loop. */
2300 overlap0
= i
.types
[0] & t
->operand_types
[0];
2301 switch (t
->operands
)
2304 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
2309 overlap1
= i
.types
[1] & t
->operand_types
[1];
2310 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
2311 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
2312 /* monitor in SSE3 is a very special case. The first
2313 register and the second register may have different
2315 || !((t
->base_opcode
== 0x0f01
2316 && t
->extension_opcode
== 0xc8)
2317 || CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2318 t
->operand_types
[0],
2319 overlap1
, i
.types
[1],
2320 t
->operand_types
[1])))
2322 /* Check if other direction is valid ... */
2323 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2326 /* Try reversing direction of operands. */
2327 overlap0
= i
.types
[0] & t
->operand_types
[1];
2328 overlap1
= i
.types
[1] & t
->operand_types
[0];
2329 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
2330 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
2331 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2332 t
->operand_types
[1],
2333 overlap1
, i
.types
[1],
2334 t
->operand_types
[0]))
2336 /* Does not match either direction. */
2339 /* found_reverse_match holds which of D or FloatDR
2341 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2343 /* Found a forward 2 operand match here. */
2344 else if (t
->operands
== 3)
2346 /* Here we make use of the fact that there are no
2347 reverse match 3 operand instructions, and all 3
2348 operand instructions only need to be checked for
2349 register consistency between operands 2 and 3. */
2350 overlap2
= i
.types
[2] & t
->operand_types
[2];
2351 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
2352 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
2353 t
->operand_types
[1],
2354 overlap2
, i
.types
[2],
2355 t
->operand_types
[2]))
2359 /* Found either forward/reverse 2 or 3 operand match here:
2360 slip through to break. */
2362 if (t
->cpu_flags
& ~cpu_arch_flags
)
2364 found_reverse_match
= 0;
2367 /* We've found a match; break out of loop. */
2371 if (t
== current_templates
->end
)
2373 /* We found no match. */
2374 as_bad (_("suffix or operands invalid for `%s'"),
2375 current_templates
->start
->name
);
2379 if (!quiet_warnings
)
2382 && ((i
.types
[0] & JumpAbsolute
)
2383 != (t
->operand_types
[0] & JumpAbsolute
)))
2385 as_warn (_("indirect %s without `*'"), t
->name
);
2388 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2389 == (IsPrefix
| IgnoreSize
))
2391 /* Warn them that a data or address size prefix doesn't
2392 affect assembly of the next line of code. */
2393 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2397 /* Copy the template we found. */
2399 if (found_reverse_match
)
2401 /* If we found a reverse match we must alter the opcode
2402 direction bit. found_reverse_match holds bits to change
2403 (different for int & float insns). */
2405 i
.tm
.base_opcode
^= found_reverse_match
;
2407 i
.tm
.operand_types
[0] = t
->operand_types
[1];
2408 i
.tm
.operand_types
[1] = t
->operand_types
[0];
2417 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2418 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2420 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2422 as_bad (_("`%s' operand %d must use `%%es' segment"),
2427 /* There's only ever one segment override allowed per instruction.
2428 This instruction possibly has a legal segment override on the
2429 second operand, so copy the segment to where non-string
2430 instructions store it, allowing common code. */
2431 i
.seg
[0] = i
.seg
[1];
2433 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2435 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2437 as_bad (_("`%s' operand %d must use `%%es' segment"),
2447 process_suffix (void)
2449 /* If matched instruction specifies an explicit instruction mnemonic
2451 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2453 if (i
.tm
.opcode_modifier
& Size16
)
2454 i
.suffix
= WORD_MNEM_SUFFIX
;
2455 else if (i
.tm
.opcode_modifier
& Size64
)
2456 i
.suffix
= QWORD_MNEM_SUFFIX
;
2458 i
.suffix
= LONG_MNEM_SUFFIX
;
2460 else if (i
.reg_operands
)
2462 /* If there's no instruction mnemonic suffix we try to invent one
2463 based on register operands. */
2466 /* We take i.suffix from the last register operand specified,
2467 Destination register type is more significant than source
2471 for (op
= i
.operands
; --op
>= 0;)
2472 if ((i
.types
[op
] & Reg
)
2473 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2475 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2476 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2477 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2482 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2484 if (!check_byte_reg ())
2487 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2489 if (!check_long_reg ())
2492 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2494 if (!check_qword_reg ())
2497 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2499 if (!check_word_reg ())
2502 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2503 /* Do nothing if the instruction is going to ignore the prefix. */
2508 else if ((i
.tm
.opcode_modifier
& DefaultSize
)
2510 /* exclude fldenv/frstor/fsave/fstenv */
2511 && (i
.tm
.opcode_modifier
& No_sSuf
))
2513 i
.suffix
= stackop_size
;
2515 else if (intel_syntax
2517 && ((i
.tm
.operand_types
[0] & JumpAbsolute
)
2518 || (i
.tm
.opcode_modifier
& (JumpByte
|JumpInterSegment
))
2519 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
2520 && i
.tm
.extension_opcode
<= 3)))
2525 if (!(i
.tm
.opcode_modifier
& No_qSuf
))
2527 i
.suffix
= QWORD_MNEM_SUFFIX
;
2531 if (!(i
.tm
.opcode_modifier
& No_lSuf
))
2532 i
.suffix
= LONG_MNEM_SUFFIX
;
2535 if (!(i
.tm
.opcode_modifier
& No_wSuf
))
2536 i
.suffix
= WORD_MNEM_SUFFIX
;
2545 if (i
.tm
.opcode_modifier
& W
)
2547 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2553 unsigned int suffixes
= (~i
.tm
.opcode_modifier
2561 if ((i
.tm
.opcode_modifier
& W
)
2562 || ((suffixes
& (suffixes
- 1))
2563 && !(i
.tm
.opcode_modifier
& (DefaultSize
| IgnoreSize
))))
2565 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2571 /* Change the opcode based on the operand size given by i.suffix;
2572 We don't need to change things for byte insns. */
2574 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2576 /* It's not a byte, select word/dword operation. */
2577 if (i
.tm
.opcode_modifier
& W
)
2579 if (i
.tm
.opcode_modifier
& ShortForm
)
2580 i
.tm
.base_opcode
|= 8;
2582 i
.tm
.base_opcode
|= 1;
2585 /* Now select between word & dword operations via the operand
2586 size prefix, except for instructions that will ignore this
2588 if (i
.tm
.base_opcode
== 0x0f01 && i
.tm
.extension_opcode
== 0xc8)
2590 /* monitor in SSE3 is a very special case. The default size
2591 of AX is the size of mode. The address size override
2592 prefix will change the size of AX. */
2593 if (i
.op
->regs
[0].reg_type
&
2594 (flag_code
== CODE_32BIT
? Reg16
: Reg32
))
2595 if (!add_prefix (ADDR_PREFIX_OPCODE
))
2598 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
2599 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
2600 && !(i
.tm
.opcode_modifier
& (IgnoreSize
| FloatMF
))
2601 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2602 || (flag_code
== CODE_64BIT
2603 && (i
.tm
.opcode_modifier
& JumpByte
))))
2605 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2607 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2608 prefix
= ADDR_PREFIX_OPCODE
;
2610 if (!add_prefix (prefix
))
2614 /* Set mode64 for an operand. */
2615 if (i
.suffix
== QWORD_MNEM_SUFFIX
2616 && flag_code
== CODE_64BIT
2617 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2619 /* Special case for xchg %rax,%rax. It is NOP and doesn't
2622 || i
.types
[0] != (Acc
| Reg64
)
2623 || i
.types
[1] != (Acc
| Reg64
)
2624 || strcmp (i
.tm
.name
, "xchg") != 0)
2625 i
.rex
|= REX_MODE64
;
2628 /* Size floating point instruction. */
2629 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2630 if (i
.tm
.opcode_modifier
& FloatMF
)
2631 i
.tm
.base_opcode
^= 4;
2638 check_byte_reg (void)
2642 for (op
= i
.operands
; --op
>= 0;)
2644 /* If this is an eight bit register, it's OK. If it's the 16 or
2645 32 bit version of an eight bit register, we will just use the
2646 low portion, and that's OK too. */
2647 if (i
.types
[op
] & Reg8
)
2650 /* movzx and movsx should not generate this warning. */
2652 && (i
.tm
.base_opcode
== 0xfb7
2653 || i
.tm
.base_opcode
== 0xfb6
2654 || i
.tm
.base_opcode
== 0x63
2655 || i
.tm
.base_opcode
== 0xfbe
2656 || i
.tm
.base_opcode
== 0xfbf))
2659 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4)
2661 /* Prohibit these changes in the 64bit mode, since the
2662 lowering is more complicated. */
2663 if (flag_code
== CODE_64BIT
2664 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2666 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2667 i
.op
[op
].regs
->reg_name
,
2671 #if REGISTER_WARNINGS
2673 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2674 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2675 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
2676 ? REGNAM_AL
- REGNAM_AX
2677 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2678 i
.op
[op
].regs
->reg_name
,
2683 /* Any other register is bad. */
2684 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2686 | Control
| Debug
| Test
2687 | FloatReg
| FloatAcc
))
2689 as_bad (_("`%%%s' not allowed with `%s%c'"),
2690 i
.op
[op
].regs
->reg_name
,
2704 for (op
= i
.operands
; --op
>= 0;)
2705 /* Reject eight bit registers, except where the template requires
2706 them. (eg. movzb) */
2707 if ((i
.types
[op
] & Reg8
) != 0
2708 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2710 as_bad (_("`%%%s' not allowed with `%s%c'"),
2711 i
.op
[op
].regs
->reg_name
,
2716 /* Warn if the e prefix on a general reg is missing. */
2717 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2718 && (i
.types
[op
] & Reg16
) != 0
2719 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2721 /* Prohibit these changes in the 64bit mode, since the
2722 lowering is more complicated. */
2723 if (flag_code
== CODE_64BIT
)
2725 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2726 i
.op
[op
].regs
->reg_name
,
2730 #if REGISTER_WARNINGS
2732 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2733 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2734 i
.op
[op
].regs
->reg_name
,
2738 /* Warn if the r prefix on a general reg is missing. */
2739 else if ((i
.types
[op
] & Reg64
) != 0
2740 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2742 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2743 i
.op
[op
].regs
->reg_name
,
2755 for (op
= i
.operands
; --op
>= 0; )
2756 /* Reject eight bit registers, except where the template requires
2757 them. (eg. movzb) */
2758 if ((i
.types
[op
] & Reg8
) != 0
2759 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2761 as_bad (_("`%%%s' not allowed with `%s%c'"),
2762 i
.op
[op
].regs
->reg_name
,
2767 /* Warn if the e prefix on a general reg is missing. */
2768 else if (((i
.types
[op
] & Reg16
) != 0
2769 || (i
.types
[op
] & Reg32
) != 0)
2770 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2772 /* Prohibit these changes in the 64bit mode, since the
2773 lowering is more complicated. */
2774 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2775 i
.op
[op
].regs
->reg_name
,
2786 for (op
= i
.operands
; --op
>= 0;)
2787 /* Reject eight bit registers, except where the template requires
2788 them. (eg. movzb) */
2789 if ((i
.types
[op
] & Reg8
) != 0
2790 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2792 as_bad (_("`%%%s' not allowed with `%s%c'"),
2793 i
.op
[op
].regs
->reg_name
,
2798 /* Warn if the e prefix on a general reg is present. */
2799 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2800 && (i
.types
[op
] & Reg32
) != 0
2801 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
2803 /* Prohibit these changes in the 64bit mode, since the
2804 lowering is more complicated. */
2805 if (flag_code
== CODE_64BIT
)
2807 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2808 i
.op
[op
].regs
->reg_name
,
2813 #if REGISTER_WARNINGS
2814 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2815 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2816 i
.op
[op
].regs
->reg_name
,
2826 unsigned int overlap0
, overlap1
, overlap2
;
2828 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
2829 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
))
2830 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2831 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2832 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2836 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2838 : (i
.suffix
== WORD_MNEM_SUFFIX
2840 : (i
.suffix
== QWORD_MNEM_SUFFIX
2844 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2845 || overlap0
== (Imm16
| Imm32
)
2846 || overlap0
== (Imm16
| Imm32S
))
2848 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2851 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2852 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2853 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2855 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2859 i
.types
[0] = overlap0
;
2861 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
2862 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
| Imm64
))
2863 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2864 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2865 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2869 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2871 : (i
.suffix
== WORD_MNEM_SUFFIX
2873 : (i
.suffix
== QWORD_MNEM_SUFFIX
2877 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2878 || overlap1
== (Imm16
| Imm32
)
2879 || overlap1
== (Imm16
| Imm32S
))
2881 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2884 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2885 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2886 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2888 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2892 i
.types
[1] = overlap1
;
2894 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
2895 assert ((overlap2
& Imm
) == 0);
2896 i
.types
[2] = overlap2
;
2904 /* Default segment register this instruction will use for memory
2905 accesses. 0 means unknown. This is only for optimizing out
2906 unnecessary segment overrides. */
2907 const seg_entry
*default_seg
= 0;
2909 /* The imul $imm, %reg instruction is converted into
2910 imul $imm, %reg, %reg, and the clr %reg instruction
2911 is converted into xor %reg, %reg. */
2912 if (i
.tm
.opcode_modifier
& regKludge
)
2914 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2915 /* Pretend we saw the extra register operand. */
2916 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2917 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2918 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2922 if (i
.tm
.opcode_modifier
& ShortForm
)
2924 /* The register or float register operand is in operand 0 or 1. */
2925 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2926 /* Register goes in low 3 bits of opcode. */
2927 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2928 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2930 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2932 /* Warn about some common errors, but press on regardless.
2933 The first case can be generated by gcc (<= 2.8.1). */
2934 if (i
.operands
== 2)
2936 /* Reversed arguments on faddp, fsubp, etc. */
2937 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2938 i
.op
[1].regs
->reg_name
,
2939 i
.op
[0].regs
->reg_name
);
2943 /* Extraneous `l' suffix on fp insn. */
2944 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2945 i
.op
[0].regs
->reg_name
);
2949 else if (i
.tm
.opcode_modifier
& Modrm
)
2951 /* The opcode is completed (modulo i.tm.extension_opcode which
2952 must be put into the modrm byte). Now, we make the modrm and
2953 index base bytes based on all the info we've collected. */
2955 default_seg
= build_modrm_byte ();
2957 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2959 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2960 && i
.op
[0].regs
->reg_num
== 1)
2962 as_bad (_("you can't `pop %%cs'"));
2965 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2966 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
2969 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
2973 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2975 /* For the string instructions that allow a segment override
2976 on one of their operands, the default segment is ds. */
2980 if ((i
.tm
.base_opcode
== 0x8d /* lea */
2981 || (i
.tm
.cpu_flags
& CpuSVME
))
2982 && i
.seg
[0] && !quiet_warnings
)
2983 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
2985 /* If a segment was explicitly specified, and the specified segment
2986 is not the default, use an opcode prefix to select it. If we
2987 never figured out what the default segment is, then default_seg
2988 will be zero at this point, and the specified segment prefix will
2990 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2992 if (!add_prefix (i
.seg
[0]->seg_prefix
))
2998 static const seg_entry
*
3001 const seg_entry
*default_seg
= 0;
3003 /* i.reg_operands MUST be the number of real register operands;
3004 implicit registers do not count. */
3005 if (i
.reg_operands
== 2)
3007 unsigned int source
, dest
;
3008 source
= ((i
.types
[0]
3009 & (Reg
| RegMMX
| RegXMM
3011 | Control
| Debug
| Test
))
3016 /* One of the register operands will be encoded in the i.tm.reg
3017 field, the other in the combined i.tm.mode and i.tm.regmem
3018 fields. If no form of this instruction supports a memory
3019 destination operand, then we assume the source operand may
3020 sometimes be a memory operand and so we need to store the
3021 destination in the i.rm.reg field. */
3022 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
3024 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
3025 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
3026 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
3028 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
3033 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
3034 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
3035 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
3037 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
3040 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_EXTX
| REX_EXTZ
)))
3042 if (!((i
.types
[0] | i
.types
[1]) & Control
))
3044 i
.rex
&= ~(REX_EXTX
| REX_EXTZ
);
3045 add_prefix (LOCK_PREFIX_OPCODE
);
3049 { /* If it's not 2 reg operands... */
3052 unsigned int fake_zero_displacement
= 0;
3053 unsigned int op
= ((i
.types
[0] & AnyMem
)
3055 : (i
.types
[1] & AnyMem
) ? 1 : 2);
3059 if (i
.base_reg
== 0)
3062 if (!i
.disp_operands
)
3063 fake_zero_displacement
= 1;
3064 if (i
.index_reg
== 0)
3066 /* Operand is just <disp> */
3067 if (flag_code
== CODE_64BIT
)
3069 /* 64bit mode overwrites the 32bit absolute
3070 addressing by RIP relative addressing and
3071 absolute addressing is encoded by one of the
3072 redundant SIB forms. */
3073 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3074 i
.sib
.base
= NO_BASE_REGISTER
;
3075 i
.sib
.index
= NO_INDEX_REGISTER
;
3076 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0) ? Disp32S
: Disp32
);
3078 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3080 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
3081 i
.types
[op
] = Disp16
;
3085 i
.rm
.regmem
= NO_BASE_REGISTER
;
3086 i
.types
[op
] = Disp32
;
3089 else /* !i.base_reg && i.index_reg */
3091 i
.sib
.index
= i
.index_reg
->reg_num
;
3092 i
.sib
.base
= NO_BASE_REGISTER
;
3093 i
.sib
.scale
= i
.log2_scale_factor
;
3094 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3095 i
.types
[op
] &= ~Disp
;
3096 if (flag_code
!= CODE_64BIT
)
3097 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
3099 i
.types
[op
] |= Disp32S
;
3100 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3104 /* RIP addressing for 64bit mode. */
3105 else if (i
.base_reg
->reg_type
== BaseIndex
)
3107 i
.rm
.regmem
= NO_BASE_REGISTER
;
3108 i
.types
[op
] &= ~ Disp
;
3109 i
.types
[op
] |= Disp32S
;
3110 i
.flags
[op
] = Operand_PCrel
;
3111 if (! i
.disp_operands
)
3112 fake_zero_displacement
= 1;
3114 else if (i
.base_reg
->reg_type
& Reg16
)
3116 switch (i
.base_reg
->reg_num
)
3119 if (i
.index_reg
== 0)
3121 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3122 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
3126 if (i
.index_reg
== 0)
3129 if ((i
.types
[op
] & Disp
) == 0)
3131 /* fake (%bp) into 0(%bp) */
3132 i
.types
[op
] |= Disp8
;
3133 fake_zero_displacement
= 1;
3136 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3137 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
3139 default: /* (%si) -> 4 or (%di) -> 5 */
3140 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
3142 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3144 else /* i.base_reg and 32/64 bit mode */
3146 if (flag_code
== CODE_64BIT
3147 && (i
.types
[op
] & Disp
))
3148 i
.types
[op
] = (i
.types
[op
] & Disp8
) | (i
.prefix
[ADDR_PREFIX
] == 0 ? Disp32S
: Disp32
);
3150 i
.rm
.regmem
= i
.base_reg
->reg_num
;
3151 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
3153 i
.sib
.base
= i
.base_reg
->reg_num
;
3154 /* x86-64 ignores REX prefix bit here to avoid decoder
3156 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
3159 if (i
.disp_operands
== 0)
3161 fake_zero_displacement
= 1;
3162 i
.types
[op
] |= Disp8
;
3165 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
3169 i
.sib
.scale
= i
.log2_scale_factor
;
3170 if (i
.index_reg
== 0)
3172 /* <disp>(%esp) becomes two byte modrm with no index
3173 register. We've already stored the code for esp
3174 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3175 Any base register besides %esp will not use the
3176 extra modrm byte. */
3177 i
.sib
.index
= NO_INDEX_REGISTER
;
3178 #if !SCALE1_WHEN_NO_INDEX
3179 /* Another case where we force the second modrm byte. */
3180 if (i
.log2_scale_factor
)
3181 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3186 i
.sib
.index
= i
.index_reg
->reg_num
;
3187 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3188 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3193 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3194 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
3197 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3200 if (fake_zero_displacement
)
3202 /* Fakes a zero displacement assuming that i.types[op]
3203 holds the correct displacement size. */
3206 assert (i
.op
[op
].disps
== 0);
3207 exp
= &disp_expressions
[i
.disp_operands
++];
3208 i
.op
[op
].disps
= exp
;
3209 exp
->X_op
= O_constant
;
3210 exp
->X_add_number
= 0;
3211 exp
->X_add_symbol
= (symbolS
*) 0;
3212 exp
->X_op_symbol
= (symbolS
*) 0;
3216 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3217 (if any) based on i.tm.extension_opcode. Again, we must be
3218 careful to make sure that segment/control/debug/test/MMX
3219 registers are coded into the i.rm.reg field. */
3224 & (Reg
| RegMMX
| RegXMM
3226 | Control
| Debug
| Test
))
3229 & (Reg
| RegMMX
| RegXMM
3231 | Control
| Debug
| Test
))
3234 /* If there is an extension opcode to put here, the register
3235 number must be put into the regmem field. */
3236 if (i
.tm
.extension_opcode
!= None
)
3238 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
3239 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3244 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
3245 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3249 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3250 must set it to 3 to indicate this is a register operand
3251 in the regmem field. */
3252 if (!i
.mem_operands
)
3256 /* Fill in i.rm.reg field with extension opcode (if any). */
3257 if (i
.tm
.extension_opcode
!= None
)
3258 i
.rm
.reg
= i
.tm
.extension_opcode
;
3269 relax_substateT subtype
;
3274 if (flag_code
== CODE_16BIT
)
3278 if (i
.prefix
[DATA_PREFIX
] != 0)
3284 /* Pentium4 branch hints. */
3285 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3286 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3291 if (i
.prefix
[REX_PREFIX
] != 0)
3297 if (i
.prefixes
!= 0 && !intel_syntax
)
3298 as_warn (_("skipping prefixes on this instruction"));
3300 /* It's always a symbol; End frag & setup for relax.
3301 Make sure there is enough room in this frag for the largest
3302 instruction we may generate in md_convert_frag. This is 2
3303 bytes for the opcode and room for the prefix and largest
3305 frag_grow (prefix
+ 2 + 4);
3306 /* Prefix and 1 opcode byte go in fr_fix. */
3307 p
= frag_more (prefix
+ 1);
3308 if (i
.prefix
[DATA_PREFIX
] != 0)
3309 *p
++ = DATA_PREFIX_OPCODE
;
3310 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
3311 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
3312 *p
++ = i
.prefix
[SEG_PREFIX
];
3313 if (i
.prefix
[REX_PREFIX
] != 0)
3314 *p
++ = i
.prefix
[REX_PREFIX
];
3315 *p
= i
.tm
.base_opcode
;
3317 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
3318 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
3319 else if ((cpu_arch_flags
& Cpu386
) != 0)
3320 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
3322 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
3325 sym
= i
.op
[0].disps
->X_add_symbol
;
3326 off
= i
.op
[0].disps
->X_add_number
;
3328 if (i
.op
[0].disps
->X_op
!= O_constant
3329 && i
.op
[0].disps
->X_op
!= O_symbol
)
3331 /* Handle complex expressions. */
3332 sym
= make_expr_symbol (i
.op
[0].disps
);
3336 /* 1 possible extra opcode + 4 byte displacement go in var part.
3337 Pass reloc in fr_var. */
3338 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
3348 if (i
.tm
.opcode_modifier
& JumpByte
)
3350 /* This is a loop or jecxz type instruction. */
3352 if (i
.prefix
[ADDR_PREFIX
] != 0)
3354 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3357 /* Pentium4 branch hints. */
3358 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3359 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3361 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3370 if (flag_code
== CODE_16BIT
)
3373 if (i
.prefix
[DATA_PREFIX
] != 0)
3375 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3385 if (i
.prefix
[REX_PREFIX
] != 0)
3387 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3391 if (i
.prefixes
!= 0 && !intel_syntax
)
3392 as_warn (_("skipping prefixes on this instruction"));
3394 p
= frag_more (1 + size
);
3395 *p
++ = i
.tm
.base_opcode
;
3397 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3398 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3400 /* All jumps handled here are signed, but don't use a signed limit
3401 check for 32 and 16 bit jumps as we want to allow wrap around at
3402 4G and 64k respectively. */
3404 fixP
->fx_signed
= 1;
3408 output_interseg_jump ()
3416 if (flag_code
== CODE_16BIT
)
3420 if (i
.prefix
[DATA_PREFIX
] != 0)
3426 if (i
.prefix
[REX_PREFIX
] != 0)
3436 if (i
.prefixes
!= 0 && !intel_syntax
)
3437 as_warn (_("skipping prefixes on this instruction"));
3439 /* 1 opcode; 2 segment; offset */
3440 p
= frag_more (prefix
+ 1 + 2 + size
);
3442 if (i
.prefix
[DATA_PREFIX
] != 0)
3443 *p
++ = DATA_PREFIX_OPCODE
;
3445 if (i
.prefix
[REX_PREFIX
] != 0)
3446 *p
++ = i
.prefix
[REX_PREFIX
];
3448 *p
++ = i
.tm
.base_opcode
;
3449 if (i
.op
[1].imms
->X_op
== O_constant
)
3451 offsetT n
= i
.op
[1].imms
->X_add_number
;
3454 && !fits_in_unsigned_word (n
)
3455 && !fits_in_signed_word (n
))
3457 as_bad (_("16-bit jump out of range"));
3460 md_number_to_chars (p
, n
, size
);
3463 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3464 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3465 if (i
.op
[0].imms
->X_op
!= O_constant
)
3466 as_bad (_("can't handle non absolute segment in `%s'"),
3468 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3474 fragS
*insn_start_frag
;
3475 offsetT insn_start_off
;
3477 /* Tie dwarf2 debug info to the address at the start of the insn.
3478 We can't do this after the insn has been output as the current
3479 frag may have been closed off. eg. by frag_var. */
3480 dwarf2_emit_insn (0);
3482 insn_start_frag
= frag_now
;
3483 insn_start_off
= frag_now_fix ();
3486 if (i
.tm
.opcode_modifier
& Jump
)
3488 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3490 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3491 output_interseg_jump ();
3494 /* Output normal instructions here. */
3497 unsigned int prefix
;
3499 /* All opcodes on i386 have either 1 or 2 bytes. Merom New
3500 Instructions have 3 bytes. We may use one more higher byte
3501 to specify a prefix the instruction requires. */
3502 if ((i
.tm
.cpu_flags
& CpuMNI
) != 0)
3504 if (i
.tm
.base_opcode
& 0xff000000)
3506 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
3510 else if ((i
.tm
.base_opcode
& 0xff0000) != 0)
3512 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
3513 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0)
3516 if (prefix
!= REPE_PREFIX_OPCODE
3517 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
3518 add_prefix (prefix
);
3521 add_prefix (prefix
);
3524 /* The prefix bytes. */
3526 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3532 md_number_to_chars (p
, (valueT
) *q
, 1);
3536 /* Now the opcode; be careful about word order here! */
3537 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3539 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3543 if ((i
.tm
.cpu_flags
& CpuMNI
) != 0)
3546 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
3551 /* Put out high byte first: can't use md_number_to_chars! */
3552 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3553 *p
= i
.tm
.base_opcode
& 0xff;
3556 /* Now the modrm byte and sib byte (if present). */
3557 if (i
.tm
.opcode_modifier
& Modrm
)
3560 md_number_to_chars (p
,
3561 (valueT
) (i
.rm
.regmem
<< 0
3565 /* If i.rm.regmem == ESP (4)
3566 && i.rm.mode != (Register mode)
3568 ==> need second modrm byte. */
3569 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3571 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3574 md_number_to_chars (p
,
3575 (valueT
) (i
.sib
.base
<< 0
3577 | i
.sib
.scale
<< 6),
3582 if (i
.disp_operands
)
3583 output_disp (insn_start_frag
, insn_start_off
);
3586 output_imm (insn_start_frag
, insn_start_off
);
3592 pi ("" /*line*/, &i
);
3594 #endif /* DEBUG386 */
3598 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
3603 for (n
= 0; n
< i
.operands
; n
++)
3605 if (i
.types
[n
] & Disp
)
3607 if (i
.op
[n
].disps
->X_op
== O_constant
)
3613 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
3616 if (i
.types
[n
] & Disp8
)
3618 if (i
.types
[n
] & Disp64
)
3621 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3623 p
= frag_more (size
);
3624 md_number_to_chars (p
, val
, size
);
3628 enum bfd_reloc_code_real reloc_type
;
3631 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3633 /* The PC relative address is computed relative
3634 to the instruction boundary, so in case immediate
3635 fields follows, we need to adjust the value. */
3636 if (pcrel
&& i
.imm_operands
)
3641 for (n1
= 0; n1
< i
.operands
; n1
++)
3642 if (i
.types
[n1
] & Imm
)
3644 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3647 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3649 if (i
.types
[n1
] & Imm64
)
3654 /* We should find the immediate. */
3655 if (n1
== i
.operands
)
3657 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3660 if (i
.types
[n
] & Disp32S
)
3663 if (i
.types
[n
] & (Disp16
| Disp64
))
3666 if (i
.types
[n
] & Disp64
)
3670 p
= frag_more (size
);
3671 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
3673 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
3674 && (((reloc_type
== BFD_RELOC_32
3675 || reloc_type
== BFD_RELOC_X86_64_32S
3676 || (reloc_type
== BFD_RELOC_64
3678 && (i
.op
[n
].disps
->X_op
== O_symbol
3679 || (i
.op
[n
].disps
->X_op
== O_add
3680 && ((symbol_get_value_expression
3681 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
3683 || reloc_type
== BFD_RELOC_32_PCREL
))
3687 if (insn_start_frag
== frag_now
)
3688 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3693 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3694 for (fr
= insn_start_frag
->fr_next
;
3695 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3697 add
+= p
- frag_now
->fr_literal
;
3702 reloc_type
= BFD_RELOC_386_GOTPC
;
3703 i
.op
[n
].imms
->X_add_number
+= add
;
3705 else if (reloc_type
== BFD_RELOC_64
)
3706 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
3708 /* Don't do the adjustment for x86-64, as there
3709 the pcrel addressing is relative to the _next_
3710 insn, and that is taken care of in other code. */
3711 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
3713 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3714 i
.op
[n
].disps
, pcrel
, reloc_type
);
3721 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
3726 for (n
= 0; n
< i
.operands
; n
++)
3728 if (i
.types
[n
] & Imm
)
3730 if (i
.op
[n
].imms
->X_op
== O_constant
)
3736 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3739 if (i
.types
[n
] & (Imm8
| Imm8S
))
3741 else if (i
.types
[n
] & Imm64
)
3744 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3746 p
= frag_more (size
);
3747 md_number_to_chars (p
, val
, size
);
3751 /* Not absolute_section.
3752 Need a 32-bit fixup (don't support 8bit
3753 non-absolute imms). Try to support other
3755 enum bfd_reloc_code_real reloc_type
;
3759 if ((i
.types
[n
] & (Imm32S
))
3760 && (i
.suffix
== QWORD_MNEM_SUFFIX
3761 || (!i
.suffix
&& (i
.tm
.opcode_modifier
& No_lSuf
))))
3763 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3766 if (i
.types
[n
] & (Imm8
| Imm8S
))
3768 if (i
.types
[n
] & Imm64
)
3772 p
= frag_more (size
);
3773 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3775 /* This is tough to explain. We end up with this one if we
3776 * have operands that look like
3777 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3778 * obtain the absolute address of the GOT, and it is strongly
3779 * preferable from a performance point of view to avoid using
3780 * a runtime relocation for this. The actual sequence of
3781 * instructions often look something like:
3786 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3788 * The call and pop essentially return the absolute address
3789 * of the label .L66 and store it in %ebx. The linker itself
3790 * will ultimately change the first operand of the addl so
3791 * that %ebx points to the GOT, but to keep things simple, the
3792 * .o file must have this operand set so that it generates not
3793 * the absolute address of .L66, but the absolute address of
3794 * itself. This allows the linker itself simply treat a GOTPC
3795 * relocation as asking for a pcrel offset to the GOT to be
3796 * added in, and the addend of the relocation is stored in the
3797 * operand field for the instruction itself.
3799 * Our job here is to fix the operand so that it would add
3800 * the correct offset so that %ebx would point to itself. The
3801 * thing that is tricky is that .-.L66 will point to the
3802 * beginning of the instruction, so we need to further modify
3803 * the operand so that it will point to itself. There are
3804 * other cases where you have something like:
3806 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3808 * and here no correction would be required. Internally in
3809 * the assembler we treat operands of this form as not being
3810 * pcrel since the '.' is explicitly mentioned, and I wonder
3811 * whether it would simplify matters to do it this way. Who
3812 * knows. In earlier versions of the PIC patches, the
3813 * pcrel_adjust field was used to store the correction, but
3814 * since the expression is not pcrel, I felt it would be
3815 * confusing to do it this way. */
3817 if ((reloc_type
== BFD_RELOC_32
3818 || reloc_type
== BFD_RELOC_X86_64_32S
3819 || reloc_type
== BFD_RELOC_64
)
3821 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3822 && (i
.op
[n
].imms
->X_op
== O_symbol
3823 || (i
.op
[n
].imms
->X_op
== O_add
3824 && ((symbol_get_value_expression
3825 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3830 if (insn_start_frag
== frag_now
)
3831 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3836 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3837 for (fr
= insn_start_frag
->fr_next
;
3838 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3840 add
+= p
- frag_now
->fr_literal
;
3844 reloc_type
= BFD_RELOC_386_GOTPC
;
3846 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
3848 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
3849 i
.op
[n
].imms
->X_add_number
+= add
;
3851 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3852 i
.op
[n
].imms
, 0, reloc_type
);
3858 /* x86_cons_fix_new is called via the expression parsing code when a
3859 reloc is needed. We use this hook to get the correct .got reloc. */
3860 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
3861 static int cons_sign
= -1;
3864 x86_cons_fix_new (fragS
*frag
,
3869 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
3871 got_reloc
= NO_RELOC
;
3874 if (exp
->X_op
== O_secrel
)
3876 exp
->X_op
= O_symbol
;
3877 r
= BFD_RELOC_32_SECREL
;
3881 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3884 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
3885 # define lex_got(reloc, adjust, types) NULL
3887 /* Parse operands of the form
3888 <symbol>@GOTOFF+<nnn>
3889 and similar .plt or .got references.
3891 If we find one, set up the correct relocation in RELOC and copy the
3892 input string, minus the `@GOTOFF' into a malloc'd buffer for
3893 parsing by the calling routine. Return this buffer, and if ADJUST
3894 is non-null set it to the length of the string we removed from the
3895 input line. Otherwise return NULL. */
3897 lex_got (enum bfd_reloc_code_real
*reloc
,
3899 unsigned int *types
)
3901 /* Some of the relocations depend on the size of what field is to
3902 be relocated. But in our callers i386_immediate and i386_displacement
3903 we don't yet know the operand size (this will be set by insn
3904 matching). Hence we record the word32 relocation here,
3905 and adjust the reloc according to the real size in reloc(). */
3906 static const struct {
3908 const enum bfd_reloc_code_real rel
[2];
3909 const unsigned int types64
;
3911 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64
}, Imm64
},
3912 { "PLT", { BFD_RELOC_386_PLT32
, BFD_RELOC_X86_64_PLT32
}, Imm32
|Imm32S
|Disp32
},
3913 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64
}, Imm64
|Disp64
},
3914 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, BFD_RELOC_X86_64_GOTOFF64
}, Imm64
|Disp64
},
3915 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL
}, Imm32
|Imm32S
|Disp32
},
3916 { "TLSGD", { BFD_RELOC_386_TLS_GD
, BFD_RELOC_X86_64_TLSGD
}, Imm32
|Imm32S
|Disp32
},
3917 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
, 0 }, 0 },
3918 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD
}, Imm32
|Imm32S
|Disp32
},
3919 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
, BFD_RELOC_X86_64_GOTTPOFF
}, Imm32
|Imm32S
|Disp32
},
3920 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
, BFD_RELOC_X86_64_TPOFF32
}, Imm32
|Imm32S
|Imm64
|Disp32
|Disp64
},
3921 { "NTPOFF", { BFD_RELOC_386_TLS_LE
, 0 }, 0 },
3922 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
, BFD_RELOC_X86_64_DTPOFF32
}, Imm32
|Imm32S
|Imm64
|Disp32
|Disp64
},
3923 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
, 0 }, 0 },
3924 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
, 0 }, 0 },
3925 { "GOT", { BFD_RELOC_386_GOT32
, BFD_RELOC_X86_64_GOT32
}, Imm32
|Imm32S
|Disp32
|Imm64
},
3926 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
, BFD_RELOC_X86_64_GOTPC32_TLSDESC
}, Imm32
|Imm32S
|Disp32
},
3927 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
, BFD_RELOC_X86_64_TLSDESC_CALL
}, Imm32
|Imm32S
|Disp32
}
3935 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3936 if (is_end_of_line
[(unsigned char) *cp
])
3939 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3943 len
= strlen (gotrel
[j
].str
);
3944 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3946 if (gotrel
[j
].rel
[object_64bit
] != 0)
3949 char *tmpbuf
, *past_reloc
;
3951 *reloc
= gotrel
[j
].rel
[object_64bit
];
3957 if (flag_code
!= CODE_64BIT
)
3958 *types
= Imm32
|Disp32
;
3960 *types
= gotrel
[j
].types64
;
3963 if (GOT_symbol
== NULL
)
3964 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3966 /* Replace the relocation token with ' ', so that
3967 errors like foo@GOTOFF1 will be detected. */
3969 /* The length of the first part of our input line. */
3970 first
= cp
- input_line_pointer
;
3972 /* The second part goes from after the reloc token until
3973 (and including) an end_of_line char. Don't use strlen
3974 here as the end_of_line char may not be a NUL. */
3975 past_reloc
= cp
+ 1 + len
;
3976 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3978 second
= cp
- past_reloc
;
3980 /* Allocate and copy string. The trailing NUL shouldn't
3981 be necessary, but be safe. */
3982 tmpbuf
= xmalloc (first
+ second
+ 2);
3983 memcpy (tmpbuf
, input_line_pointer
, first
);
3984 tmpbuf
[first
] = ' ';
3985 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3986 tmpbuf
[first
+ second
+ 1] = '\0';
3990 as_bad (_("@%s reloc is not supported with %d-bit output format"),
3991 gotrel
[j
].str
, 1 << (5 + object_64bit
));
3996 /* Might be a symbol version string. Don't as_bad here. */
4001 x86_cons (exp
, size
)
4005 if (size
== 4 || (object_64bit
&& size
== 8))
4007 /* Handle @GOTOFF and the like in an expression. */
4009 char *gotfree_input_line
;
4012 save
= input_line_pointer
;
4013 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
4014 if (gotfree_input_line
)
4015 input_line_pointer
= gotfree_input_line
;
4019 if (gotfree_input_line
)
4021 /* expression () has merrily parsed up to the end of line,
4022 or a comma - in the wrong buffer. Transfer how far
4023 input_line_pointer has moved to the right buffer. */
4024 input_line_pointer
= (save
4025 + (input_line_pointer
- gotfree_input_line
)
4027 free (gotfree_input_line
);
4035 static void signed_cons (int size
)
4037 if (flag_code
== CODE_64BIT
)
4045 pe_directive_secrel (dummy
)
4046 int dummy ATTRIBUTE_UNUSED
;
4053 if (exp
.X_op
== O_symbol
)
4054 exp
.X_op
= O_secrel
;
4056 emit_expr (&exp
, 4);
4058 while (*input_line_pointer
++ == ',');
4060 input_line_pointer
--;
4061 demand_empty_rest_of_line ();
4065 static int i386_immediate
PARAMS ((char *));
4068 i386_immediate (imm_start
)
4071 char *save_input_line_pointer
;
4072 char *gotfree_input_line
;
4075 unsigned int types
= ~0U;
4077 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
4079 as_bad (_("only 1 or 2 immediate operands are allowed"));
4083 exp
= &im_expressions
[i
.imm_operands
++];
4084 i
.op
[this_operand
].imms
= exp
;
4086 if (is_space_char (*imm_start
))
4089 save_input_line_pointer
= input_line_pointer
;
4090 input_line_pointer
= imm_start
;
4092 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4093 if (gotfree_input_line
)
4094 input_line_pointer
= gotfree_input_line
;
4096 exp_seg
= expression (exp
);
4099 if (*input_line_pointer
)
4100 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4102 input_line_pointer
= save_input_line_pointer
;
4103 if (gotfree_input_line
)
4104 free (gotfree_input_line
);
4106 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4108 /* Missing or bad expr becomes absolute 0. */
4109 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
4111 exp
->X_op
= O_constant
;
4112 exp
->X_add_number
= 0;
4113 exp
->X_add_symbol
= (symbolS
*) 0;
4114 exp
->X_op_symbol
= (symbolS
*) 0;
4116 else if (exp
->X_op
== O_constant
)
4118 /* Size it properly later. */
4119 i
.types
[this_operand
] |= Imm64
;
4120 /* If BFD64, sign extend val. */
4121 if (!use_rela_relocations
)
4122 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
4123 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
4125 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4126 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
4127 && exp_seg
!= absolute_section
4128 && exp_seg
!= text_section
4129 && exp_seg
!= data_section
4130 && exp_seg
!= bss_section
4131 && exp_seg
!= undefined_section
4132 && !bfd_is_com_section (exp_seg
))
4134 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4138 else if (!intel_syntax
&& exp
->X_op
== O_register
)
4140 as_bad (_("illegal immediate register operand %s"), imm_start
);
4145 /* This is an address. The size of the address will be
4146 determined later, depending on destination register,
4147 suffix, or the default for the section. */
4148 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
4149 i
.types
[this_operand
] &= types
;
4155 static char *i386_scale
PARAMS ((char *));
4162 char *save
= input_line_pointer
;
4164 input_line_pointer
= scale
;
4165 val
= get_absolute_expression ();
4170 i
.log2_scale_factor
= 0;
4173 i
.log2_scale_factor
= 1;
4176 i
.log2_scale_factor
= 2;
4179 i
.log2_scale_factor
= 3;
4183 char sep
= *input_line_pointer
;
4185 *input_line_pointer
= '\0';
4186 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4188 *input_line_pointer
= sep
;
4189 input_line_pointer
= save
;
4193 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
4195 as_warn (_("scale factor of %d without an index register"),
4196 1 << i
.log2_scale_factor
);
4197 #if SCALE1_WHEN_NO_INDEX
4198 i
.log2_scale_factor
= 0;
4201 scale
= input_line_pointer
;
4202 input_line_pointer
= save
;
4206 static int i386_displacement
PARAMS ((char *, char *));
4209 i386_displacement (disp_start
, disp_end
)
4215 char *save_input_line_pointer
;
4216 char *gotfree_input_line
;
4217 int bigdisp
, override
;
4218 unsigned int types
= Disp
;
4220 if ((i
.types
[this_operand
] & JumpAbsolute
)
4221 || !(current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
)))
4224 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
4228 /* For PC-relative branches, the width of the displacement
4229 is dependent upon data size, not address size. */
4231 override
= (i
.prefix
[DATA_PREFIX
] != 0);
4233 if (flag_code
== CODE_64BIT
)
4236 bigdisp
= ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
4238 : Disp32S
| Disp32
);
4240 bigdisp
= Disp64
| Disp32S
| Disp32
;
4247 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
4249 : LONG_MNEM_SUFFIX
));
4252 if ((flag_code
== CODE_16BIT
) ^ override
)
4255 i
.types
[this_operand
] |= bigdisp
;
4257 exp
= &disp_expressions
[i
.disp_operands
];
4258 i
.op
[this_operand
].disps
= exp
;
4260 save_input_line_pointer
= input_line_pointer
;
4261 input_line_pointer
= disp_start
;
4262 END_STRING_AND_SAVE (disp_end
);
4264 #ifndef GCC_ASM_O_HACK
4265 #define GCC_ASM_O_HACK 0
4268 END_STRING_AND_SAVE (disp_end
+ 1);
4269 if ((i
.types
[this_operand
] & BaseIndex
) != 0
4270 && displacement_string_end
[-1] == '+')
4272 /* This hack is to avoid a warning when using the "o"
4273 constraint within gcc asm statements.
4276 #define _set_tssldt_desc(n,addr,limit,type) \
4277 __asm__ __volatile__ ( \
4279 "movw %w1,2+%0\n\t" \
4281 "movb %b1,4+%0\n\t" \
4282 "movb %4,5+%0\n\t" \
4283 "movb $0,6+%0\n\t" \
4284 "movb %h1,7+%0\n\t" \
4286 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4288 This works great except that the output assembler ends
4289 up looking a bit weird if it turns out that there is
4290 no offset. You end up producing code that looks like:
4303 So here we provide the missing zero. */
4305 *displacement_string_end
= '0';
4308 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4309 if (gotfree_input_line
)
4310 input_line_pointer
= gotfree_input_line
;
4312 exp_seg
= expression (exp
);
4315 if (*input_line_pointer
)
4316 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4318 RESTORE_END_STRING (disp_end
+ 1);
4320 RESTORE_END_STRING (disp_end
);
4321 input_line_pointer
= save_input_line_pointer
;
4322 if (gotfree_input_line
)
4323 free (gotfree_input_line
);
4325 /* We do this to make sure that the section symbol is in
4326 the symbol table. We will ultimately change the relocation
4327 to be relative to the beginning of the section. */
4328 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
4329 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4330 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4332 if (exp
->X_op
!= O_symbol
)
4334 as_bad (_("bad expression used with @%s"),
4335 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4341 if (S_IS_LOCAL (exp
->X_add_symbol
)
4342 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
4343 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
4344 exp
->X_op
= O_subtract
;
4345 exp
->X_op_symbol
= GOT_symbol
;
4346 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
4347 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
4348 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4349 i
.reloc
[this_operand
] = BFD_RELOC_64
;
4351 i
.reloc
[this_operand
] = BFD_RELOC_32
;
4354 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4356 /* Missing or bad expr becomes absolute 0. */
4357 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4359 exp
->X_op
= O_constant
;
4360 exp
->X_add_number
= 0;
4361 exp
->X_add_symbol
= (symbolS
*) 0;
4362 exp
->X_op_symbol
= (symbolS
*) 0;
4365 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4366 if (exp
->X_op
!= O_constant
4367 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
4368 && exp_seg
!= absolute_section
4369 && exp_seg
!= text_section
4370 && exp_seg
!= data_section
4371 && exp_seg
!= bss_section
4372 && exp_seg
!= undefined_section
4373 && !bfd_is_com_section (exp_seg
))
4375 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4380 if (!(i
.types
[this_operand
] & ~Disp
))
4381 i
.types
[this_operand
] &= types
;
4386 static int i386_index_check
PARAMS ((const char *));
4388 /* Make sure the memory operand we've been dealt is valid.
4389 Return 1 on success, 0 on a failure. */
4392 i386_index_check (operand_string
)
4393 const char *operand_string
;
4396 #if INFER_ADDR_PREFIX
4402 if ((current_templates
->start
->cpu_flags
& CpuSVME
)
4403 && current_templates
->end
[-1].operand_types
[0] == AnyMem
)
4405 /* Memory operands of SVME insns are special in that they only allow
4406 rAX as their memory address and ignore any segment override. */
4409 /* SKINIT is even more restrictive: it always requires EAX. */
4410 if (strcmp (current_templates
->start
->name
, "skinit") == 0)
4412 else if (flag_code
== CODE_64BIT
)
4413 RegXX
= i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
;
4415 RegXX
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0)
4419 || !(i
.base_reg
->reg_type
& Acc
)
4420 || !(i
.base_reg
->reg_type
& RegXX
)
4422 || (i
.types
[0] & Disp
))
4425 else if (flag_code
== CODE_64BIT
)
4427 unsigned RegXX
= (i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
);
4430 && ((i
.base_reg
->reg_type
& RegXX
) == 0)
4431 && (i
.base_reg
->reg_type
!= BaseIndex
4434 && ((i
.index_reg
->reg_type
& (RegXX
| BaseIndex
))
4435 != (RegXX
| BaseIndex
))))
4440 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4444 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
4445 != (Reg16
| BaseIndex
)))
4447 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
4448 != (Reg16
| BaseIndex
))
4450 && i
.base_reg
->reg_num
< 6
4451 && i
.index_reg
->reg_num
>= 6
4452 && i
.log2_scale_factor
== 0))))
4459 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
4461 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
4462 != (Reg32
| BaseIndex
))))
4468 #if INFER_ADDR_PREFIX
4469 if (i
.prefix
[ADDR_PREFIX
] == 0)
4471 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
4473 /* Change the size of any displacement too. At most one of
4474 Disp16 or Disp32 is set.
4475 FIXME. There doesn't seem to be any real need for separate
4476 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4477 Removing them would probably clean up the code quite a lot. */
4478 if (flag_code
!= CODE_64BIT
&& (i
.types
[this_operand
] & (Disp16
| Disp32
)))
4479 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
4484 as_bad (_("`%s' is not a valid base/index expression"),
4488 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4490 flag_code_names
[flag_code
]);
4495 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4499 i386_operand (operand_string
)
4500 char *operand_string
;
4504 char *op_string
= operand_string
;
4506 if (is_space_char (*op_string
))
4509 /* We check for an absolute prefix (differentiating,
4510 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4511 if (*op_string
== ABSOLUTE_PREFIX
)
4514 if (is_space_char (*op_string
))
4516 i
.types
[this_operand
] |= JumpAbsolute
;
4519 /* Check if operand is a register. */
4520 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
4522 /* Check for a segment override by searching for ':' after a
4523 segment register. */
4525 if (is_space_char (*op_string
))
4527 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
4532 i
.seg
[i
.mem_operands
] = &es
;
4535 i
.seg
[i
.mem_operands
] = &cs
;
4538 i
.seg
[i
.mem_operands
] = &ss
;
4541 i
.seg
[i
.mem_operands
] = &ds
;
4544 i
.seg
[i
.mem_operands
] = &fs
;
4547 i
.seg
[i
.mem_operands
] = &gs
;
4551 /* Skip the ':' and whitespace. */
4553 if (is_space_char (*op_string
))
4556 if (!is_digit_char (*op_string
)
4557 && !is_identifier_char (*op_string
)
4558 && *op_string
!= '('
4559 && *op_string
!= ABSOLUTE_PREFIX
)
4561 as_bad (_("bad memory operand `%s'"), op_string
);
4564 /* Handle case of %es:*foo. */
4565 if (*op_string
== ABSOLUTE_PREFIX
)
4568 if (is_space_char (*op_string
))
4570 i
.types
[this_operand
] |= JumpAbsolute
;
4572 goto do_memory_reference
;
4576 as_bad (_("junk `%s' after register"), op_string
);
4579 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
4580 i
.op
[this_operand
].regs
= r
;
4583 else if (*op_string
== REGISTER_PREFIX
)
4585 as_bad (_("bad register name `%s'"), op_string
);
4588 else if (*op_string
== IMMEDIATE_PREFIX
)
4591 if (i
.types
[this_operand
] & JumpAbsolute
)
4593 as_bad (_("immediate operand illegal with absolute jump"));
4596 if (!i386_immediate (op_string
))
4599 else if (is_digit_char (*op_string
)
4600 || is_identifier_char (*op_string
)
4601 || *op_string
== '(')
4603 /* This is a memory reference of some sort. */
4606 /* Start and end of displacement string expression (if found). */
4607 char *displacement_string_start
;
4608 char *displacement_string_end
;
4610 do_memory_reference
:
4611 if ((i
.mem_operands
== 1
4612 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4613 || i
.mem_operands
== 2)
4615 as_bad (_("too many memory references for `%s'"),
4616 current_templates
->start
->name
);
4620 /* Check for base index form. We detect the base index form by
4621 looking for an ')' at the end of the operand, searching
4622 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4624 base_string
= op_string
+ strlen (op_string
);
4627 if (is_space_char (*base_string
))
4630 /* If we only have a displacement, set-up for it to be parsed later. */
4631 displacement_string_start
= op_string
;
4632 displacement_string_end
= base_string
+ 1;
4634 if (*base_string
== ')')
4637 unsigned int parens_balanced
= 1;
4638 /* We've already checked that the number of left & right ()'s are
4639 equal, so this loop will not be infinite. */
4643 if (*base_string
== ')')
4645 if (*base_string
== '(')
4648 while (parens_balanced
);
4650 temp_string
= base_string
;
4652 /* Skip past '(' and whitespace. */
4654 if (is_space_char (*base_string
))
4657 if (*base_string
== ','
4658 || ((i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
4660 displacement_string_end
= temp_string
;
4662 i
.types
[this_operand
] |= BaseIndex
;
4666 base_string
= end_op
;
4667 if (is_space_char (*base_string
))
4671 /* There may be an index reg or scale factor here. */
4672 if (*base_string
== ',')
4675 if (is_space_char (*base_string
))
4678 if ((i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
4680 base_string
= end_op
;
4681 if (is_space_char (*base_string
))
4683 if (*base_string
== ',')
4686 if (is_space_char (*base_string
))
4689 else if (*base_string
!= ')')
4691 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4696 else if (*base_string
== REGISTER_PREFIX
)
4698 as_bad (_("bad register name `%s'"), base_string
);
4702 /* Check for scale factor. */
4703 if (*base_string
!= ')')
4705 char *end_scale
= i386_scale (base_string
);
4710 base_string
= end_scale
;
4711 if (is_space_char (*base_string
))
4713 if (*base_string
!= ')')
4715 as_bad (_("expecting `)' after scale factor in `%s'"),
4720 else if (!i
.index_reg
)
4722 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4727 else if (*base_string
!= ')')
4729 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4734 else if (*base_string
== REGISTER_PREFIX
)
4736 as_bad (_("bad register name `%s'"), base_string
);
4741 /* If there's an expression beginning the operand, parse it,
4742 assuming displacement_string_start and
4743 displacement_string_end are meaningful. */
4744 if (displacement_string_start
!= displacement_string_end
)
4746 if (!i386_displacement (displacement_string_start
,
4747 displacement_string_end
))
4751 /* Special case for (%dx) while doing input/output op. */
4753 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
4755 && i
.log2_scale_factor
== 0
4756 && i
.seg
[i
.mem_operands
] == 0
4757 && (i
.types
[this_operand
] & Disp
) == 0)
4759 i
.types
[this_operand
] = InOutPortReg
;
4763 if (i386_index_check (operand_string
) == 0)
4769 /* It's not a memory operand; argh! */
4770 as_bad (_("invalid char %s beginning operand %d `%s'"),
4771 output_invalid (*op_string
),
4776 return 1; /* Normal return. */
4779 /* md_estimate_size_before_relax()
4781 Called just before relax() for rs_machine_dependent frags. The x86
4782 assembler uses these frags to handle variable size jump
4785 Any symbol that is now undefined will not become defined.
4786 Return the correct fr_subtype in the frag.
4787 Return the initial "guess for variable size of frag" to caller.
4788 The guess is actually the growth beyond the fixed part. Whatever
4789 we do to grow the fixed or variable part contributes to our
4793 md_estimate_size_before_relax (fragP
, segment
)
4797 /* We've already got fragP->fr_subtype right; all we have to do is
4798 check for un-relaxable symbols. On an ELF system, we can't relax
4799 an externally visible symbol, because it may be overridden by a
4801 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4802 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4804 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
4805 || S_IS_WEAK (fragP
->fr_symbol
)))
4809 /* Symbol is undefined in this segment, or we need to keep a
4810 reloc so that weak symbols can be overridden. */
4811 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
4812 enum bfd_reloc_code_real reloc_type
;
4813 unsigned char *opcode
;
4816 if (fragP
->fr_var
!= NO_RELOC
)
4817 reloc_type
= fragP
->fr_var
;
4819 reloc_type
= BFD_RELOC_16_PCREL
;
4821 reloc_type
= BFD_RELOC_32_PCREL
;
4823 old_fr_fix
= fragP
->fr_fix
;
4824 opcode
= (unsigned char *) fragP
->fr_opcode
;
4826 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4829 /* Make jmp (0xeb) a (d)word displacement jump. */
4831 fragP
->fr_fix
+= size
;
4832 fix_new (fragP
, old_fr_fix
, size
,
4834 fragP
->fr_offset
, 1,
4840 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
4842 /* Negate the condition, and branch past an
4843 unconditional jump. */
4846 /* Insert an unconditional jump. */
4848 /* We added two extra opcode bytes, and have a two byte
4850 fragP
->fr_fix
+= 2 + 2;
4851 fix_new (fragP
, old_fr_fix
+ 2, 2,
4853 fragP
->fr_offset
, 1,
4860 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
4865 fixP
= fix_new (fragP
, old_fr_fix
, 1,
4867 fragP
->fr_offset
, 1,
4869 fixP
->fx_signed
= 1;
4873 /* This changes the byte-displacement jump 0x7N
4874 to the (d)word-displacement jump 0x0f,0x8N. */
4875 opcode
[1] = opcode
[0] + 0x10;
4876 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4877 /* We've added an opcode byte. */
4878 fragP
->fr_fix
+= 1 + size
;
4879 fix_new (fragP
, old_fr_fix
+ 1, size
,
4881 fragP
->fr_offset
, 1,
4886 BAD_CASE (fragP
->fr_subtype
);
4890 return fragP
->fr_fix
- old_fr_fix
;
4893 /* Guess size depending on current relax state. Initially the relax
4894 state will correspond to a short jump and we return 1, because
4895 the variable part of the frag (the branch offset) is one byte
4896 long. However, we can relax a section more than once and in that
4897 case we must either set fr_subtype back to the unrelaxed state,
4898 or return the value for the appropriate branch. */
4899 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4902 /* Called after relax() is finished.
4904 In: Address of frag.
4905 fr_type == rs_machine_dependent.
4906 fr_subtype is what the address relaxed to.
4908 Out: Any fixSs and constants are set up.
4909 Caller will turn frag into a ".space 0". */
4912 md_convert_frag (abfd
, sec
, fragP
)
4913 bfd
*abfd ATTRIBUTE_UNUSED
;
4914 segT sec ATTRIBUTE_UNUSED
;
4917 unsigned char *opcode
;
4918 unsigned char *where_to_put_displacement
= NULL
;
4919 offsetT target_address
;
4920 offsetT opcode_address
;
4921 unsigned int extension
= 0;
4922 offsetT displacement_from_opcode_start
;
4924 opcode
= (unsigned char *) fragP
->fr_opcode
;
4926 /* Address we want to reach in file space. */
4927 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4929 /* Address opcode resides at in file space. */
4930 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4932 /* Displacement from opcode start to fill into instruction. */
4933 displacement_from_opcode_start
= target_address
- opcode_address
;
4935 if ((fragP
->fr_subtype
& BIG
) == 0)
4937 /* Don't have to change opcode. */
4938 extension
= 1; /* 1 opcode + 1 displacement */
4939 where_to_put_displacement
= &opcode
[1];
4943 if (no_cond_jump_promotion
4944 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4945 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4947 switch (fragP
->fr_subtype
)
4949 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4950 extension
= 4; /* 1 opcode + 4 displacement */
4952 where_to_put_displacement
= &opcode
[1];
4955 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4956 extension
= 2; /* 1 opcode + 2 displacement */
4958 where_to_put_displacement
= &opcode
[1];
4961 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4962 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4963 extension
= 5; /* 2 opcode + 4 displacement */
4964 opcode
[1] = opcode
[0] + 0x10;
4965 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4966 where_to_put_displacement
= &opcode
[2];
4969 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4970 extension
= 3; /* 2 opcode + 2 displacement */
4971 opcode
[1] = opcode
[0] + 0x10;
4972 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4973 where_to_put_displacement
= &opcode
[2];
4976 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4981 where_to_put_displacement
= &opcode
[3];
4985 BAD_CASE (fragP
->fr_subtype
);
4990 /* If size if less then four we are sure that the operand fits,
4991 but if it's 4, then it could be that the displacement is larger
4993 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
4995 && ((addressT
) (displacement_from_opcode_start
- extension
4996 + ((addressT
) 1 << 31))
4997 > (((addressT
) 2 << 31) - 1)))
4999 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5000 _("jump target out of range"));
5001 /* Make us emit 0. */
5002 displacement_from_opcode_start
= extension
;
5004 /* Now put displacement after opcode. */
5005 md_number_to_chars ((char *) where_to_put_displacement
,
5006 (valueT
) (displacement_from_opcode_start
- extension
),
5007 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
5008 fragP
->fr_fix
+= extension
;
5011 /* Size of byte displacement jmp. */
5012 int md_short_jump_size
= 2;
5014 /* Size of dword displacement jmp. */
5015 int md_long_jump_size
= 5;
5018 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5020 addressT from_addr
, to_addr
;
5021 fragS
*frag ATTRIBUTE_UNUSED
;
5022 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
5026 offset
= to_addr
- (from_addr
+ 2);
5027 /* Opcode for byte-disp jump. */
5028 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
5029 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
5033 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5035 addressT from_addr
, to_addr
;
5036 fragS
*frag ATTRIBUTE_UNUSED
;
5037 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
5041 offset
= to_addr
- (from_addr
+ 5);
5042 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
5043 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
5046 /* Apply a fixup (fixS) to segment data, once it has been determined
5047 by our caller that we have all the info we need to fix it up.
5049 On the 386, immediates, displacements, and data pointers are all in
5050 the same (little-endian) format, so we don't need to care about which
5054 md_apply_fix (fixP
, valP
, seg
)
5055 /* The fix we're to put in. */
5057 /* Pointer to the value of the bits. */
5059 /* Segment fix is from. */
5060 segT seg ATTRIBUTE_UNUSED
;
5062 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
5063 valueT value
= *valP
;
5065 #if !defined (TE_Mach)
5068 switch (fixP
->fx_r_type
)
5074 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
5077 case BFD_RELOC_X86_64_32S
:
5078 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
5081 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
5084 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
5089 if (fixP
->fx_addsy
!= NULL
5090 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
5091 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
5092 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
5093 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
5094 && !use_rela_relocations
)
5096 /* This is a hack. There should be a better way to handle this.
5097 This covers for the fact that bfd_install_relocation will
5098 subtract the current location (for partial_inplace, PC relative
5099 relocations); see more below. */
5103 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
5106 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5108 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5111 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
5114 || (symbol_section_p (fixP
->fx_addsy
)
5115 && sym_seg
!= absolute_section
))
5116 && !generic_force_reloc (fixP
))
5118 /* Yes, we add the values in twice. This is because
5119 bfd_install_relocation subtracts them out again. I think
5120 bfd_install_relocation is broken, but I don't dare change
5122 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5126 #if defined (OBJ_COFF) && defined (TE_PE)
5127 /* For some reason, the PE format does not store a
5128 section address offset for a PC relative symbol. */
5129 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
5130 || S_IS_WEAK (fixP
->fx_addsy
))
5131 value
+= md_pcrel_from (fixP
);
5135 /* Fix a few things - the dynamic linker expects certain values here,
5136 and we must not disappoint it. */
5137 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5138 if (IS_ELF
&& fixP
->fx_addsy
)
5139 switch (fixP
->fx_r_type
)
5141 case BFD_RELOC_386_PLT32
:
5142 case BFD_RELOC_X86_64_PLT32
:
5143 /* Make the jump instruction point to the address of the operand. At
5144 runtime we merely add the offset to the actual PLT entry. */
5148 case BFD_RELOC_386_TLS_GD
:
5149 case BFD_RELOC_386_TLS_LDM
:
5150 case BFD_RELOC_386_TLS_IE_32
:
5151 case BFD_RELOC_386_TLS_IE
:
5152 case BFD_RELOC_386_TLS_GOTIE
:
5153 case BFD_RELOC_386_TLS_GOTDESC
:
5154 case BFD_RELOC_X86_64_TLSGD
:
5155 case BFD_RELOC_X86_64_TLSLD
:
5156 case BFD_RELOC_X86_64_GOTTPOFF
:
5157 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
5158 value
= 0; /* Fully resolved at runtime. No addend. */
5160 case BFD_RELOC_386_TLS_LE
:
5161 case BFD_RELOC_386_TLS_LDO_32
:
5162 case BFD_RELOC_386_TLS_LE_32
:
5163 case BFD_RELOC_X86_64_DTPOFF32
:
5164 case BFD_RELOC_X86_64_DTPOFF64
:
5165 case BFD_RELOC_X86_64_TPOFF32
:
5166 case BFD_RELOC_X86_64_TPOFF64
:
5167 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5170 case BFD_RELOC_386_TLS_DESC_CALL
:
5171 case BFD_RELOC_X86_64_TLSDESC_CALL
:
5172 value
= 0; /* Fully resolved at runtime. No addend. */
5173 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5177 case BFD_RELOC_386_GOT32
:
5178 case BFD_RELOC_X86_64_GOT32
:
5179 value
= 0; /* Fully resolved at runtime. No addend. */
5182 case BFD_RELOC_VTABLE_INHERIT
:
5183 case BFD_RELOC_VTABLE_ENTRY
:
5190 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5192 #endif /* !defined (TE_Mach) */
5194 /* Are we finished with this relocation now? */
5195 if (fixP
->fx_addsy
== NULL
)
5197 else if (use_rela_relocations
)
5199 fixP
->fx_no_overflow
= 1;
5200 /* Remember value for tc_gen_reloc. */
5201 fixP
->fx_addnumber
= value
;
5205 md_number_to_chars (p
, value
, fixP
->fx_size
);
5208 #define MAX_LITTLENUMS 6
5210 /* Turn the string pointed to by litP into a floating point constant
5211 of type TYPE, and emit the appropriate bytes. The number of
5212 LITTLENUMS emitted is stored in *SIZEP. An error message is
5213 returned, or NULL on OK. */
5216 md_atof (type
, litP
, sizeP
)
5222 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5223 LITTLENUM_TYPE
*wordP
;
5245 return _("Bad call to md_atof ()");
5247 t
= atof_ieee (input_line_pointer
, type
, words
);
5249 input_line_pointer
= t
;
5251 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
5252 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5253 the bigendian 386. */
5254 for (wordP
= words
+ prec
- 1; prec
--;)
5256 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
5257 litP
+= sizeof (LITTLENUM_TYPE
);
5262 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
5269 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
5272 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
5273 "(0x%x)", (unsigned char) c
);
5274 return output_invalid_buf
;
5277 /* REG_STRING starts *before* REGISTER_PREFIX. */
5279 static const reg_entry
*
5280 parse_real_register (char *reg_string
, char **end_op
)
5282 char *s
= reg_string
;
5284 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
5287 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5288 if (*s
== REGISTER_PREFIX
)
5291 if (is_space_char (*s
))
5295 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
5297 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
5298 return (const reg_entry
*) NULL
;
5302 /* For naked regs, make sure that we are not dealing with an identifier.
5303 This prevents confusing an identifier like `eax_var' with register
5305 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
5306 return (const reg_entry
*) NULL
;
5310 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
5312 /* Handle floating point regs, allowing spaces in the (i) part. */
5313 if (r
== i386_regtab
/* %st is first entry of table */)
5315 if (is_space_char (*s
))
5320 if (is_space_char (*s
))
5322 if (*s
>= '0' && *s
<= '7')
5324 r
= &i386_float_regtab
[*s
- '0'];
5326 if (is_space_char (*s
))
5334 /* We have "%st(" then garbage. */
5335 return (const reg_entry
*) NULL
;
5340 && ((r
->reg_flags
& (RegRex64
| RegRex
)) | (r
->reg_type
& Reg64
)) != 0
5341 && (r
->reg_type
!= Control
|| !(cpu_arch_flags
& CpuSledgehammer
))
5342 && flag_code
!= CODE_64BIT
)
5343 return (const reg_entry
*) NULL
;
5348 /* REG_STRING starts *before* REGISTER_PREFIX. */
5350 static const reg_entry
*
5351 parse_register (char *reg_string
, char **end_op
)
5355 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5356 r
= parse_real_register (reg_string
, end_op
);
5361 char *save
= input_line_pointer
;
5365 input_line_pointer
= reg_string
;
5366 c
= get_symbol_end ();
5367 symbolP
= symbol_find (reg_string
);
5368 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
5370 const expressionS
*e
= symbol_get_value_expression (symbolP
);
5372 know (e
->X_op
== O_register
);
5373 know (e
->X_add_number
>= 0 && (valueT
) e
->X_add_number
< ARRAY_SIZE (i386_regtab
));
5374 r
= i386_regtab
+ e
->X_add_number
;
5375 *end_op
= input_line_pointer
;
5377 *input_line_pointer
= c
;
5378 input_line_pointer
= save
;
5384 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
5387 char *end
= input_line_pointer
;
5390 r
= parse_register (name
, &input_line_pointer
);
5391 if (r
&& end
<= input_line_pointer
)
5393 *nextcharP
= *input_line_pointer
;
5394 *input_line_pointer
= 0;
5395 e
->X_op
= O_register
;
5396 e
->X_add_number
= r
- i386_regtab
;
5399 input_line_pointer
= end
;
5405 md_operand (expressionS
*e
)
5407 if (*input_line_pointer
== REGISTER_PREFIX
)
5410 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
5414 e
->X_op
= O_register
;
5415 e
->X_add_number
= r
- i386_regtab
;
5416 input_line_pointer
= end
;
5422 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5423 const char *md_shortopts
= "kVQ:sqn";
5425 const char *md_shortopts
= "qn";
5428 #define OPTION_32 (OPTION_MD_BASE + 0)
5429 #define OPTION_64 (OPTION_MD_BASE + 1)
5430 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5432 struct option md_longopts
[] = {
5433 {"32", no_argument
, NULL
, OPTION_32
},
5434 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5435 {"64", no_argument
, NULL
, OPTION_64
},
5437 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
5438 {NULL
, no_argument
, NULL
, 0}
5440 size_t md_longopts_size
= sizeof (md_longopts
);
5443 md_parse_option (c
, arg
)
5445 char *arg ATTRIBUTE_UNUSED
;
5450 optimize_align_code
= 0;
5457 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5458 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5459 should be emitted or not. FIXME: Not implemented. */
5463 /* -V: SVR4 argument to print version ID. */
5465 print_version_id ();
5468 /* -k: Ignore for FreeBSD compatibility. */
5473 /* -s: On i386 Solaris, this tells the native assembler to use
5474 .stab instead of .stab.excl. We always use .stab anyhow. */
5479 const char **list
, **l
;
5481 list
= bfd_target_list ();
5482 for (l
= list
; *l
!= NULL
; l
++)
5483 if (strcmp (*l
, "elf64-x86-64") == 0)
5485 default_arch
= "x86_64";
5489 as_fatal (_("No compiled in support for x86_64"));
5496 default_arch
= "i386";
5500 #ifdef SVR4_COMMENT_CHARS
5505 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
5507 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
5511 i386_comment_chars
= n
;
5523 md_show_usage (stream
)
5526 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5527 fprintf (stream
, _("\
5529 -V print assembler version number\n\
5532 fprintf (stream
, _("\
5533 -n Do not optimize code alignment\n\
5534 -q quieten some warnings\n"));
5535 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5536 fprintf (stream
, _("\
5539 #ifdef SVR4_COMMENT_CHARS
5540 fprintf (stream
, _("\
5541 --divide do not treat `/' as a comment character\n"));
5543 fprintf (stream
, _("\
5544 --divide ignored\n"));
5548 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5549 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5551 /* Pick the target format to use. */
5554 i386_target_format ()
5556 if (!strcmp (default_arch
, "x86_64"))
5557 set_code_flag (CODE_64BIT
);
5558 else if (!strcmp (default_arch
, "i386"))
5559 set_code_flag (CODE_32BIT
);
5561 as_fatal (_("Unknown architecture"));
5562 switch (OUTPUT_FLAVOR
)
5564 #ifdef OBJ_MAYBE_AOUT
5565 case bfd_target_aout_flavour
:
5566 return AOUT_TARGET_FORMAT
;
5568 #ifdef OBJ_MAYBE_COFF
5569 case bfd_target_coff_flavour
:
5572 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5573 case bfd_target_elf_flavour
:
5575 if (flag_code
== CODE_64BIT
)
5578 use_rela_relocations
= 1;
5580 return flag_code
== CODE_64BIT
? "elf64-x86-64" : ELF_TARGET_FORMAT
;
5589 #endif /* OBJ_MAYBE_ more than one */
5591 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5592 void i386_elf_emit_arch_note ()
5594 if (IS_ELF
&& cpu_arch_name
!= NULL
)
5597 asection
*seg
= now_seg
;
5598 subsegT subseg
= now_subseg
;
5599 Elf_Internal_Note i_note
;
5600 Elf_External_Note e_note
;
5601 asection
*note_secp
;
5604 /* Create the .note section. */
5605 note_secp
= subseg_new (".note", 0);
5606 bfd_set_section_flags (stdoutput
,
5608 SEC_HAS_CONTENTS
| SEC_READONLY
);
5610 /* Process the arch string. */
5611 len
= strlen (cpu_arch_name
);
5613 i_note
.namesz
= len
+ 1;
5615 i_note
.type
= NT_ARCH
;
5616 p
= frag_more (sizeof (e_note
.namesz
));
5617 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
5618 p
= frag_more (sizeof (e_note
.descsz
));
5619 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
5620 p
= frag_more (sizeof (e_note
.type
));
5621 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
5622 p
= frag_more (len
+ 1);
5623 strcpy (p
, cpu_arch_name
);
5625 frag_align (2, 0, 0);
5627 subseg_set (seg
, subseg
);
5633 md_undefined_symbol (name
)
5636 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
5637 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
5638 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
5639 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
5643 if (symbol_find (name
))
5644 as_bad (_("GOT already in symbol table"));
5645 GOT_symbol
= symbol_new (name
, undefined_section
,
5646 (valueT
) 0, &zero_address_frag
);
5653 /* Round up a section size to the appropriate boundary. */
5656 md_section_align (segment
, size
)
5657 segT segment ATTRIBUTE_UNUSED
;
5660 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5661 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
5663 /* For a.out, force the section size to be aligned. If we don't do
5664 this, BFD will align it for us, but it will not write out the
5665 final bytes of the section. This may be a bug in BFD, but it is
5666 easier to fix it here since that is how the other a.out targets
5670 align
= bfd_get_section_alignment (stdoutput
, segment
);
5671 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
5678 /* On the i386, PC-relative offsets are relative to the start of the
5679 next instruction. That is, the address of the offset, plus its
5680 size, since the offset is always the last part of the insn. */
5683 md_pcrel_from (fixP
)
5686 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5693 int ignore ATTRIBUTE_UNUSED
;
5697 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5699 obj_elf_section_change_hook ();
5701 temp
= get_absolute_expression ();
5702 subseg_set (bss_section
, (subsegT
) temp
);
5703 demand_empty_rest_of_line ();
5709 i386_validate_fix (fixp
)
5712 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
5714 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
5718 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
5723 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
5725 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
5732 tc_gen_reloc (section
, fixp
)
5733 asection
*section ATTRIBUTE_UNUSED
;
5737 bfd_reloc_code_real_type code
;
5739 switch (fixp
->fx_r_type
)
5741 case BFD_RELOC_X86_64_PLT32
:
5742 case BFD_RELOC_X86_64_GOT32
:
5743 case BFD_RELOC_X86_64_GOTPCREL
:
5744 case BFD_RELOC_386_PLT32
:
5745 case BFD_RELOC_386_GOT32
:
5746 case BFD_RELOC_386_GOTOFF
:
5747 case BFD_RELOC_386_GOTPC
:
5748 case BFD_RELOC_386_TLS_GD
:
5749 case BFD_RELOC_386_TLS_LDM
:
5750 case BFD_RELOC_386_TLS_LDO_32
:
5751 case BFD_RELOC_386_TLS_IE_32
:
5752 case BFD_RELOC_386_TLS_IE
:
5753 case BFD_RELOC_386_TLS_GOTIE
:
5754 case BFD_RELOC_386_TLS_LE_32
:
5755 case BFD_RELOC_386_TLS_LE
:
5756 case BFD_RELOC_386_TLS_GOTDESC
:
5757 case BFD_RELOC_386_TLS_DESC_CALL
:
5758 case BFD_RELOC_X86_64_TLSGD
:
5759 case BFD_RELOC_X86_64_TLSLD
:
5760 case BFD_RELOC_X86_64_DTPOFF32
:
5761 case BFD_RELOC_X86_64_DTPOFF64
:
5762 case BFD_RELOC_X86_64_GOTTPOFF
:
5763 case BFD_RELOC_X86_64_TPOFF32
:
5764 case BFD_RELOC_X86_64_TPOFF64
:
5765 case BFD_RELOC_X86_64_GOTOFF64
:
5766 case BFD_RELOC_X86_64_GOTPC32
:
5767 case BFD_RELOC_X86_64_GOT64
:
5768 case BFD_RELOC_X86_64_GOTPCREL64
:
5769 case BFD_RELOC_X86_64_GOTPC64
:
5770 case BFD_RELOC_X86_64_GOTPLT64
:
5771 case BFD_RELOC_X86_64_PLTOFF64
:
5772 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
5773 case BFD_RELOC_X86_64_TLSDESC_CALL
:
5775 case BFD_RELOC_VTABLE_ENTRY
:
5776 case BFD_RELOC_VTABLE_INHERIT
:
5778 case BFD_RELOC_32_SECREL
:
5780 code
= fixp
->fx_r_type
;
5782 case BFD_RELOC_X86_64_32S
:
5783 if (!fixp
->fx_pcrel
)
5785 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5786 code
= fixp
->fx_r_type
;
5792 switch (fixp
->fx_size
)
5795 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5796 _("can not do %d byte pc-relative relocation"),
5798 code
= BFD_RELOC_32_PCREL
;
5800 case 1: code
= BFD_RELOC_8_PCREL
; break;
5801 case 2: code
= BFD_RELOC_16_PCREL
; break;
5802 case 4: code
= BFD_RELOC_32_PCREL
; break;
5804 case 8: code
= BFD_RELOC_64_PCREL
; break;
5810 switch (fixp
->fx_size
)
5813 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5814 _("can not do %d byte relocation"),
5816 code
= BFD_RELOC_32
;
5818 case 1: code
= BFD_RELOC_8
; break;
5819 case 2: code
= BFD_RELOC_16
; break;
5820 case 4: code
= BFD_RELOC_32
; break;
5822 case 8: code
= BFD_RELOC_64
; break;
5829 if ((code
== BFD_RELOC_32
5830 || code
== BFD_RELOC_32_PCREL
5831 || code
== BFD_RELOC_X86_64_32S
)
5833 && fixp
->fx_addsy
== GOT_symbol
)
5836 code
= BFD_RELOC_386_GOTPC
;
5838 code
= BFD_RELOC_X86_64_GOTPC32
;
5840 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
5842 && fixp
->fx_addsy
== GOT_symbol
)
5844 code
= BFD_RELOC_X86_64_GOTPC64
;
5847 rel
= (arelent
*) xmalloc (sizeof (arelent
));
5848 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5849 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5851 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5853 if (!use_rela_relocations
)
5855 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5856 vtable entry to be used in the relocation's section offset. */
5857 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5858 rel
->address
= fixp
->fx_offset
;
5862 /* Use the rela in 64bit mode. */
5865 if (!fixp
->fx_pcrel
)
5866 rel
->addend
= fixp
->fx_offset
;
5870 case BFD_RELOC_X86_64_PLT32
:
5871 case BFD_RELOC_X86_64_GOT32
:
5872 case BFD_RELOC_X86_64_GOTPCREL
:
5873 case BFD_RELOC_X86_64_TLSGD
:
5874 case BFD_RELOC_X86_64_TLSLD
:
5875 case BFD_RELOC_X86_64_GOTTPOFF
:
5876 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
5877 case BFD_RELOC_X86_64_TLSDESC_CALL
:
5878 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
5881 rel
->addend
= (section
->vma
5883 + fixp
->fx_addnumber
5884 + md_pcrel_from (fixp
));
5889 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
5890 if (rel
->howto
== NULL
)
5892 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5893 _("cannot represent relocation type %s"),
5894 bfd_get_reloc_code_name (code
));
5895 /* Set howto to a garbage value so that we can keep going. */
5896 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
5897 assert (rel
->howto
!= NULL
);
5904 /* Parse operands using Intel syntax. This implements a recursive descent
5905 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5908 FIXME: We do not recognize the full operand grammar defined in the MASM
5909 documentation. In particular, all the structure/union and
5910 high-level macro operands are missing.
5912 Uppercase words are terminals, lower case words are non-terminals.
5913 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5914 bars '|' denote choices. Most grammar productions are implemented in
5915 functions called 'intel_<production>'.
5917 Initial production is 'expr'.
5923 binOp & | AND | \| | OR | ^ | XOR
5925 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5927 constant digits [[ radixOverride ]]
5929 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
5967 => expr expr cmpOp e04
5970 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5971 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5973 hexdigit a | b | c | d | e | f
5974 | A | B | C | D | E | F
5980 mulOp * | / | % | MOD | << | SHL | >> | SHR
5984 register specialRegister
5988 segmentRegister CS | DS | ES | FS | GS | SS
5990 specialRegister CR0 | CR2 | CR3 | CR4
5991 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5992 | TR3 | TR4 | TR5 | TR6 | TR7
5994 We simplify the grammar in obvious places (e.g., register parsing is
5995 done by calling parse_register) and eliminate immediate left recursion
5996 to implement a recursive-descent parser.
6000 expr' cmpOp e04 expr'
6051 /* Parsing structure for the intel syntax parser. Used to implement the
6052 semantic actions for the operand grammar. */
6053 struct intel_parser_s
6055 char *op_string
; /* The string being parsed. */
6056 int got_a_float
; /* Whether the operand is a float. */
6057 int op_modifier
; /* Operand modifier. */
6058 int is_mem
; /* 1 if operand is memory reference. */
6059 int in_offset
; /* >=1 if parsing operand of offset. */
6060 int in_bracket
; /* >=1 if parsing operand in brackets. */
6061 const reg_entry
*reg
; /* Last register reference found. */
6062 char *disp
; /* Displacement string being built. */
6063 char *next_operand
; /* Resume point when splitting operands. */
6066 static struct intel_parser_s intel_parser
;
6068 /* Token structure for parsing intel syntax. */
6071 int code
; /* Token code. */
6072 const reg_entry
*reg
; /* Register entry for register tokens. */
6073 char *str
; /* String representation. */
6076 static struct intel_token cur_token
, prev_token
;
6078 /* Token codes for the intel parser. Since T_SHORT is already used
6079 by COFF, undefine it first to prevent a warning. */
6098 /* Prototypes for intel parser functions. */
6099 static int intel_match_token
PARAMS ((int code
));
6100 static void intel_get_token
PARAMS ((void));
6101 static void intel_putback_token
PARAMS ((void));
6102 static int intel_expr
PARAMS ((void));
6103 static int intel_e04
PARAMS ((void));
6104 static int intel_e05
PARAMS ((void));
6105 static int intel_e06
PARAMS ((void));
6106 static int intel_e09
PARAMS ((void));
6107 static int intel_bracket_expr
PARAMS ((void));
6108 static int intel_e10
PARAMS ((void));
6109 static int intel_e11
PARAMS ((void));
6112 i386_intel_operand (operand_string
, got_a_float
)
6113 char *operand_string
;
6119 p
= intel_parser
.op_string
= xstrdup (operand_string
);
6120 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
6124 /* Initialize token holders. */
6125 cur_token
.code
= prev_token
.code
= T_NIL
;
6126 cur_token
.reg
= prev_token
.reg
= NULL
;
6127 cur_token
.str
= prev_token
.str
= NULL
;
6129 /* Initialize parser structure. */
6130 intel_parser
.got_a_float
= got_a_float
;
6131 intel_parser
.op_modifier
= 0;
6132 intel_parser
.is_mem
= 0;
6133 intel_parser
.in_offset
= 0;
6134 intel_parser
.in_bracket
= 0;
6135 intel_parser
.reg
= NULL
;
6136 intel_parser
.disp
[0] = '\0';
6137 intel_parser
.next_operand
= NULL
;
6139 /* Read the first token and start the parser. */
6141 ret
= intel_expr ();
6146 if (cur_token
.code
!= T_NIL
)
6148 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6149 current_templates
->start
->name
, cur_token
.str
);
6152 /* If we found a memory reference, hand it over to i386_displacement
6153 to fill in the rest of the operand fields. */
6154 else if (intel_parser
.is_mem
)
6156 if ((i
.mem_operands
== 1
6157 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
6158 || i
.mem_operands
== 2)
6160 as_bad (_("too many memory references for '%s'"),
6161 current_templates
->start
->name
);
6166 char *s
= intel_parser
.disp
;
6169 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
6170 /* See the comments in intel_bracket_expr. */
6171 as_warn (_("Treating `%s' as memory reference"), operand_string
);
6173 /* Add the displacement expression. */
6175 ret
= i386_displacement (s
, s
+ strlen (s
));
6178 /* Swap base and index in 16-bit memory operands like
6179 [si+bx]. Since i386_index_check is also used in AT&T
6180 mode we have to do that here. */
6183 && (i
.base_reg
->reg_type
& Reg16
)
6184 && (i
.index_reg
->reg_type
& Reg16
)
6185 && i
.base_reg
->reg_num
>= 6
6186 && i
.index_reg
->reg_num
< 6)
6188 const reg_entry
*base
= i
.index_reg
;
6190 i
.index_reg
= i
.base_reg
;
6193 ret
= i386_index_check (operand_string
);
6198 /* Constant and OFFSET expressions are handled by i386_immediate. */
6199 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
6200 || intel_parser
.reg
== NULL
)
6201 ret
= i386_immediate (intel_parser
.disp
);
6203 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
6205 if (!ret
|| !intel_parser
.next_operand
)
6207 intel_parser
.op_string
= intel_parser
.next_operand
;
6208 this_operand
= i
.operands
++;
6212 free (intel_parser
.disp
);
6217 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6221 expr' cmpOp e04 expr'
6226 /* XXX Implement the comparison operators. */
6227 return intel_e04 ();
6244 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6245 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
6247 if (cur_token
.code
== '+')
6249 else if (cur_token
.code
== '-')
6250 nregs
= NUM_ADDRESS_REGS
;
6254 strcat (intel_parser
.disp
, cur_token
.str
);
6255 intel_match_token (cur_token
.code
);
6266 int nregs
= ~NUM_ADDRESS_REGS
;
6273 if (cur_token
.code
== '&' || cur_token
.code
== '|' || cur_token
.code
== '^')
6277 str
[0] = cur_token
.code
;
6279 strcat (intel_parser
.disp
, str
);
6284 intel_match_token (cur_token
.code
);
6289 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6290 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
6301 int nregs
= ~NUM_ADDRESS_REGS
;
6308 if (cur_token
.code
== '*' || cur_token
.code
== '/' || cur_token
.code
== '%')
6312 str
[0] = cur_token
.code
;
6314 strcat (intel_parser
.disp
, str
);
6316 else if (cur_token
.code
== T_SHL
)
6317 strcat (intel_parser
.disp
, "<<");
6318 else if (cur_token
.code
== T_SHR
)
6319 strcat (intel_parser
.disp
, ">>");
6323 intel_match_token (cur_token
.code
);
6328 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6329 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
6347 int nregs
= ~NUM_ADDRESS_REGS
;
6352 /* Don't consume constants here. */
6353 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6355 /* Need to look one token ahead - if the next token
6356 is a constant, the current token is its sign. */
6359 intel_match_token (cur_token
.code
);
6360 next_code
= cur_token
.code
;
6361 intel_putback_token ();
6362 if (next_code
== T_CONST
)
6366 /* e09 OFFSET e09 */
6367 if (cur_token
.code
== T_OFFSET
)
6370 ++intel_parser
.in_offset
;
6374 else if (cur_token
.code
== T_SHORT
)
6375 intel_parser
.op_modifier
|= 1 << T_SHORT
;
6378 else if (cur_token
.code
== '+')
6379 strcat (intel_parser
.disp
, "+");
6384 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
6390 str
[0] = cur_token
.code
;
6392 strcat (intel_parser
.disp
, str
);
6399 intel_match_token (cur_token
.code
);
6407 /* e09' PTR e10 e09' */
6408 if (cur_token
.code
== T_PTR
)
6412 if (prev_token
.code
== T_BYTE
)
6413 suffix
= BYTE_MNEM_SUFFIX
;
6415 else if (prev_token
.code
== T_WORD
)
6417 if (current_templates
->start
->name
[0] == 'l'
6418 && current_templates
->start
->name
[2] == 's'
6419 && current_templates
->start
->name
[3] == 0)
6420 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6421 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
6422 suffix
= SHORT_MNEM_SUFFIX
;
6424 suffix
= WORD_MNEM_SUFFIX
;
6427 else if (prev_token
.code
== T_DWORD
)
6429 if (current_templates
->start
->name
[0] == 'l'
6430 && current_templates
->start
->name
[2] == 's'
6431 && current_templates
->start
->name
[3] == 0)
6432 suffix
= WORD_MNEM_SUFFIX
;
6433 else if (flag_code
== CODE_16BIT
6434 && (current_templates
->start
->opcode_modifier
6435 & (Jump
| JumpDword
)))
6436 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6437 else if (intel_parser
.got_a_float
== 1) /* "f..." */
6438 suffix
= SHORT_MNEM_SUFFIX
;
6440 suffix
= LONG_MNEM_SUFFIX
;
6443 else if (prev_token
.code
== T_FWORD
)
6445 if (current_templates
->start
->name
[0] == 'l'
6446 && current_templates
->start
->name
[2] == 's'
6447 && current_templates
->start
->name
[3] == 0)
6448 suffix
= LONG_MNEM_SUFFIX
;
6449 else if (!intel_parser
.got_a_float
)
6451 if (flag_code
== CODE_16BIT
)
6452 add_prefix (DATA_PREFIX_OPCODE
);
6453 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6456 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6459 else if (prev_token
.code
== T_QWORD
)
6461 if (intel_parser
.got_a_float
== 1) /* "f..." */
6462 suffix
= LONG_MNEM_SUFFIX
;
6464 suffix
= QWORD_MNEM_SUFFIX
;
6467 else if (prev_token
.code
== T_TBYTE
)
6469 if (intel_parser
.got_a_float
== 1)
6470 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6472 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6475 else if (prev_token
.code
== T_XMMWORD
)
6477 /* XXX ignored for now, but accepted since gcc uses it */
6483 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
6487 /* Operands for jump/call using 'ptr' notation denote absolute
6489 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
))
6490 i
.types
[this_operand
] |= JumpAbsolute
;
6492 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
6496 else if (i
.suffix
!= suffix
)
6498 as_bad (_("Conflicting operand modifiers"));
6504 /* e09' : e10 e09' */
6505 else if (cur_token
.code
== ':')
6507 if (prev_token
.code
!= T_REG
)
6509 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6510 segment/group identifier (which we don't have), using comma
6511 as the operand separator there is even less consistent, since
6512 there all branches only have a single operand. */
6513 if (this_operand
!= 0
6514 || intel_parser
.in_offset
6515 || intel_parser
.in_bracket
6516 || (!(current_templates
->start
->opcode_modifier
6517 & (Jump
|JumpDword
|JumpInterSegment
))
6518 && !(current_templates
->start
->operand_types
[0]
6520 return intel_match_token (T_NIL
);
6521 /* Remember the start of the 2nd operand and terminate 1st
6523 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6524 another expression), but it gets at least the simplest case
6525 (a plain number or symbol on the left side) right. */
6526 intel_parser
.next_operand
= intel_parser
.op_string
;
6527 *--intel_parser
.op_string
= '\0';
6528 return intel_match_token (':');
6536 intel_match_token (cur_token
.code
);
6542 --intel_parser
.in_offset
;
6545 if (NUM_ADDRESS_REGS
> nregs
)
6547 as_bad (_("Invalid operand to `OFFSET'"));
6550 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
6553 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6554 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
6559 intel_bracket_expr ()
6561 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
6562 const char *start
= intel_parser
.op_string
;
6565 if (i
.op
[this_operand
].regs
)
6566 return intel_match_token (T_NIL
);
6568 intel_match_token ('[');
6570 /* Mark as a memory operand only if it's not already known to be an
6571 offset expression. If it's an offset expression, we need to keep
6573 if (!intel_parser
.in_offset
)
6575 ++intel_parser
.in_bracket
;
6577 /* Operands for jump/call inside brackets denote absolute addresses. */
6578 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
))
6579 i
.types
[this_operand
] |= JumpAbsolute
;
6581 /* Unfortunately gas always diverged from MASM in a respect that can't
6582 be easily fixed without risking to break code sequences likely to be
6583 encountered (the testsuite even check for this): MASM doesn't consider
6584 an expression inside brackets unconditionally as a memory reference.
6585 When that is e.g. a constant, an offset expression, or the sum of the
6586 two, this is still taken as a constant load. gas, however, always
6587 treated these as memory references. As a compromise, we'll try to make
6588 offset expressions inside brackets work the MASM way (since that's
6589 less likely to be found in real world code), but make constants alone
6590 continue to work the traditional gas way. In either case, issue a
6592 intel_parser
.op_modifier
&= ~was_offset
;
6595 strcat (intel_parser
.disp
, "[");
6597 /* Add a '+' to the displacement string if necessary. */
6598 if (*intel_parser
.disp
!= '\0'
6599 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
6600 strcat (intel_parser
.disp
, "+");
6603 && (len
= intel_parser
.op_string
- start
- 1,
6604 intel_match_token (']')))
6606 /* Preserve brackets when the operand is an offset expression. */
6607 if (intel_parser
.in_offset
)
6608 strcat (intel_parser
.disp
, "]");
6611 --intel_parser
.in_bracket
;
6612 if (i
.base_reg
|| i
.index_reg
)
6613 intel_parser
.is_mem
= 1;
6614 if (!intel_parser
.is_mem
)
6616 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
6617 /* Defer the warning until all of the operand was parsed. */
6618 intel_parser
.is_mem
= -1;
6619 else if (!quiet_warnings
)
6620 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len
, start
, len
, start
);
6623 intel_parser
.op_modifier
|= was_offset
;
6640 while (cur_token
.code
== '[')
6642 if (!intel_bracket_expr ())
6667 switch (cur_token
.code
)
6671 intel_match_token ('(');
6672 strcat (intel_parser
.disp
, "(");
6674 if (intel_expr () && intel_match_token (')'))
6676 strcat (intel_parser
.disp
, ")");
6683 return intel_bracket_expr ();
6688 strcat (intel_parser
.disp
, cur_token
.str
);
6689 intel_match_token (cur_token
.code
);
6691 /* Mark as a memory operand only if it's not already known to be an
6692 offset expression. */
6693 if (!intel_parser
.in_offset
)
6694 intel_parser
.is_mem
= 1;
6701 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
6703 intel_match_token (T_REG
);
6705 /* Check for segment change. */
6706 if (cur_token
.code
== ':')
6708 if (!(reg
->reg_type
& (SReg2
| SReg3
)))
6710 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
6713 else if (i
.seg
[i
.mem_operands
])
6714 as_warn (_("Extra segment override ignored"));
6717 if (!intel_parser
.in_offset
)
6718 intel_parser
.is_mem
= 1;
6719 switch (reg
->reg_num
)
6722 i
.seg
[i
.mem_operands
] = &es
;
6725 i
.seg
[i
.mem_operands
] = &cs
;
6728 i
.seg
[i
.mem_operands
] = &ss
;
6731 i
.seg
[i
.mem_operands
] = &ds
;
6734 i
.seg
[i
.mem_operands
] = &fs
;
6737 i
.seg
[i
.mem_operands
] = &gs
;
6743 /* Not a segment register. Check for register scaling. */
6744 else if (cur_token
.code
== '*')
6746 if (!intel_parser
.in_bracket
)
6748 as_bad (_("Register scaling only allowed in memory operands"));
6752 if (reg
->reg_type
& Reg16
) /* Disallow things like [si*1]. */
6753 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
6754 else if (i
.index_reg
)
6755 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
6757 /* What follows must be a valid scale. */
6758 intel_match_token ('*');
6760 i
.types
[this_operand
] |= BaseIndex
;
6762 /* Set the scale after setting the register (otherwise,
6763 i386_scale will complain) */
6764 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6766 char *str
, sign
= cur_token
.code
;
6767 intel_match_token (cur_token
.code
);
6768 if (cur_token
.code
!= T_CONST
)
6770 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6774 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
6775 strcpy (str
+ 1, cur_token
.str
);
6777 if (!i386_scale (str
))
6781 else if (!i386_scale (cur_token
.str
))
6783 intel_match_token (cur_token
.code
);
6786 /* No scaling. If this is a memory operand, the register is either a
6787 base register (first occurrence) or an index register (second
6789 else if (intel_parser
.in_bracket
)
6794 else if (!i
.index_reg
)
6798 as_bad (_("Too many register references in memory operand"));
6802 i
.types
[this_operand
] |= BaseIndex
;
6805 /* It's neither base nor index. */
6806 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
6808 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
6809 i
.op
[this_operand
].regs
= reg
;
6814 as_bad (_("Invalid use of register"));
6818 /* Since registers are not part of the displacement string (except
6819 when we're parsing offset operands), we may need to remove any
6820 preceding '+' from the displacement string. */
6821 if (*intel_parser
.disp
!= '\0'
6822 && !intel_parser
.in_offset
)
6824 char *s
= intel_parser
.disp
;
6825 s
+= strlen (s
) - 1;
6848 intel_match_token (cur_token
.code
);
6850 if (cur_token
.code
== T_PTR
)
6853 /* It must have been an identifier. */
6854 intel_putback_token ();
6855 cur_token
.code
= T_ID
;
6861 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
6865 /* The identifier represents a memory reference only if it's not
6866 preceded by an offset modifier and if it's not an equate. */
6867 symbolP
= symbol_find(cur_token
.str
);
6868 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
6869 intel_parser
.is_mem
= 1;
6877 char *save_str
, sign
= 0;
6879 /* Allow constants that start with `+' or `-'. */
6880 if (cur_token
.code
== '-' || cur_token
.code
== '+')
6882 sign
= cur_token
.code
;
6883 intel_match_token (cur_token
.code
);
6884 if (cur_token
.code
!= T_CONST
)
6886 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6892 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
6893 strcpy (save_str
+ !!sign
, cur_token
.str
);
6897 /* Get the next token to check for register scaling. */
6898 intel_match_token (cur_token
.code
);
6900 /* Check if this constant is a scaling factor for an index register. */
6901 if (cur_token
.code
== '*')
6903 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
6905 const reg_entry
*reg
= cur_token
.reg
;
6907 if (!intel_parser
.in_bracket
)
6909 as_bad (_("Register scaling only allowed in memory operands"));
6913 if (reg
->reg_type
& Reg16
) /* Disallow things like [1*si]. */
6914 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
6915 else if (i
.index_reg
)
6916 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
6918 /* The constant is followed by `* reg', so it must be
6921 i
.types
[this_operand
] |= BaseIndex
;
6923 /* Set the scale after setting the register (otherwise,
6924 i386_scale will complain) */
6925 if (!i386_scale (save_str
))
6927 intel_match_token (T_REG
);
6929 /* Since registers are not part of the displacement
6930 string, we may need to remove any preceding '+' from
6931 the displacement string. */
6932 if (*intel_parser
.disp
!= '\0')
6934 char *s
= intel_parser
.disp
;
6935 s
+= strlen (s
) - 1;
6945 /* The constant was not used for register scaling. Since we have
6946 already consumed the token following `*' we now need to put it
6947 back in the stream. */
6948 intel_putback_token ();
6951 /* Add the constant to the displacement string. */
6952 strcat (intel_parser
.disp
, save_str
);
6959 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
6963 /* Match the given token against cur_token. If they match, read the next
6964 token from the operand string. */
6966 intel_match_token (code
)
6969 if (cur_token
.code
== code
)
6976 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
6981 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6986 const reg_entry
*reg
;
6987 struct intel_token new_token
;
6989 new_token
.code
= T_NIL
;
6990 new_token
.reg
= NULL
;
6991 new_token
.str
= NULL
;
6993 /* Free the memory allocated to the previous token and move
6994 cur_token to prev_token. */
6996 free (prev_token
.str
);
6998 prev_token
= cur_token
;
7000 /* Skip whitespace. */
7001 while (is_space_char (*intel_parser
.op_string
))
7002 intel_parser
.op_string
++;
7004 /* Return an empty token if we find nothing else on the line. */
7005 if (*intel_parser
.op_string
== '\0')
7007 cur_token
= new_token
;
7011 /* The new token cannot be larger than the remainder of the operand
7013 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
7014 new_token
.str
[0] = '\0';
7016 if (strchr ("0123456789", *intel_parser
.op_string
))
7018 char *p
= new_token
.str
;
7019 char *q
= intel_parser
.op_string
;
7020 new_token
.code
= T_CONST
;
7022 /* Allow any kind of identifier char to encompass floating point and
7023 hexadecimal numbers. */
7024 while (is_identifier_char (*q
))
7028 /* Recognize special symbol names [0-9][bf]. */
7029 if (strlen (intel_parser
.op_string
) == 2
7030 && (intel_parser
.op_string
[1] == 'b'
7031 || intel_parser
.op_string
[1] == 'f'))
7032 new_token
.code
= T_ID
;
7035 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
7037 size_t len
= end_op
- intel_parser
.op_string
;
7039 new_token
.code
= T_REG
;
7040 new_token
.reg
= reg
;
7042 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
7043 new_token
.str
[len
] = '\0';
7046 else if (is_identifier_char (*intel_parser
.op_string
))
7048 char *p
= new_token
.str
;
7049 char *q
= intel_parser
.op_string
;
7051 /* A '.' or '$' followed by an identifier char is an identifier.
7052 Otherwise, it's operator '.' followed by an expression. */
7053 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
7055 new_token
.code
= '.';
7056 new_token
.str
[0] = '.';
7057 new_token
.str
[1] = '\0';
7061 while (is_identifier_char (*q
) || *q
== '@')
7065 if (strcasecmp (new_token
.str
, "NOT") == 0)
7066 new_token
.code
= '~';
7068 else if (strcasecmp (new_token
.str
, "MOD") == 0)
7069 new_token
.code
= '%';
7071 else if (strcasecmp (new_token
.str
, "AND") == 0)
7072 new_token
.code
= '&';
7074 else if (strcasecmp (new_token
.str
, "OR") == 0)
7075 new_token
.code
= '|';
7077 else if (strcasecmp (new_token
.str
, "XOR") == 0)
7078 new_token
.code
= '^';
7080 else if (strcasecmp (new_token
.str
, "SHL") == 0)
7081 new_token
.code
= T_SHL
;
7083 else if (strcasecmp (new_token
.str
, "SHR") == 0)
7084 new_token
.code
= T_SHR
;
7086 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
7087 new_token
.code
= T_BYTE
;
7089 else if (strcasecmp (new_token
.str
, "WORD") == 0)
7090 new_token
.code
= T_WORD
;
7092 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
7093 new_token
.code
= T_DWORD
;
7095 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
7096 new_token
.code
= T_FWORD
;
7098 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
7099 new_token
.code
= T_QWORD
;
7101 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
7102 /* XXX remove (gcc still uses it) */
7103 || strcasecmp (new_token
.str
, "XWORD") == 0)
7104 new_token
.code
= T_TBYTE
;
7106 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
7107 || strcasecmp (new_token
.str
, "OWORD") == 0)
7108 new_token
.code
= T_XMMWORD
;
7110 else if (strcasecmp (new_token
.str
, "PTR") == 0)
7111 new_token
.code
= T_PTR
;
7113 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
7114 new_token
.code
= T_SHORT
;
7116 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
7118 new_token
.code
= T_OFFSET
;
7120 /* ??? This is not mentioned in the MASM grammar but gcc
7121 makes use of it with -mintel-syntax. OFFSET may be
7122 followed by FLAT: */
7123 if (strncasecmp (q
, " FLAT:", 6) == 0)
7124 strcat (new_token
.str
, " FLAT:");
7127 /* ??? This is not mentioned in the MASM grammar. */
7128 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
7130 new_token
.code
= T_OFFSET
;
7132 strcat (new_token
.str
, ":");
7134 as_bad (_("`:' expected"));
7138 new_token
.code
= T_ID
;
7142 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
7144 new_token
.code
= *intel_parser
.op_string
;
7145 new_token
.str
[0] = *intel_parser
.op_string
;
7146 new_token
.str
[1] = '\0';
7149 else if (strchr ("<>", *intel_parser
.op_string
)
7150 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
7152 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
7153 new_token
.str
[0] = *intel_parser
.op_string
;
7154 new_token
.str
[1] = *intel_parser
.op_string
;
7155 new_token
.str
[2] = '\0';
7159 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
7161 intel_parser
.op_string
+= strlen (new_token
.str
);
7162 cur_token
= new_token
;
7165 /* Put cur_token back into the token stream and make cur_token point to
7168 intel_putback_token ()
7170 if (cur_token
.code
!= T_NIL
)
7172 intel_parser
.op_string
-= strlen (cur_token
.str
);
7173 free (cur_token
.str
);
7175 cur_token
= prev_token
;
7177 /* Forget prev_token. */
7178 prev_token
.code
= T_NIL
;
7179 prev_token
.reg
= NULL
;
7180 prev_token
.str
= NULL
;
7184 tc_x86_regname_to_dw2regnum (char *regname
)
7186 unsigned int regnum
;
7187 unsigned int regnames_count
;
7188 static const char *const regnames_32
[] =
7190 "eax", "ecx", "edx", "ebx",
7191 "esp", "ebp", "esi", "edi",
7192 "eip", "eflags", NULL
,
7193 "st0", "st1", "st2", "st3",
7194 "st4", "st5", "st6", "st7",
7196 "xmm0", "xmm1", "xmm2", "xmm3",
7197 "xmm4", "xmm5", "xmm6", "xmm7",
7198 "mm0", "mm1", "mm2", "mm3",
7199 "mm4", "mm5", "mm6", "mm7",
7200 "fcw", "fsw", "mxcsr",
7201 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
7204 static const char *const regnames_64
[] =
7206 "rax", "rdx", "rcx", "rbx",
7207 "rsi", "rdi", "rbp", "rsp",
7208 "r8", "r9", "r10", "r11",
7209 "r12", "r13", "r14", "r15",
7211 "xmm0", "xmm1", "xmm2", "xmm3",
7212 "xmm4", "xmm5", "xmm6", "xmm7",
7213 "xmm8", "xmm9", "xmm10", "xmm11",
7214 "xmm12", "xmm13", "xmm14", "xmm15",
7215 "st0", "st1", "st2", "st3",
7216 "st4", "st5", "st6", "st7",
7217 "mm0", "mm1", "mm2", "mm3",
7218 "mm4", "mm5", "mm6", "mm7",
7220 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
7221 "fs.base", "gs.base", NULL
, NULL
,
7223 "mxcsr", "fcw", "fsw"
7225 const char *const *regnames
;
7227 if (flag_code
== CODE_64BIT
)
7229 regnames
= regnames_64
;
7230 regnames_count
= ARRAY_SIZE (regnames_64
);
7234 regnames
= regnames_32
;
7235 regnames_count
= ARRAY_SIZE (regnames_32
);
7238 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
7239 if (regnames
[regnum
] != NULL
7240 && strcmp (regname
, regnames
[regnum
]) == 0)
7247 tc_x86_frame_initial_instructions (void)
7249 static unsigned int sp_regno
;
7252 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
7255 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
7256 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
7260 i386_elf_section_type (const char *str
, size_t len
)
7262 if (flag_code
== CODE_64BIT
7263 && len
== sizeof ("unwind") - 1
7264 && strncmp (str
, "unwind", 6) == 0)
7265 return SHT_X86_64_UNWIND
;
7272 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
7276 expr
.X_op
= O_secrel
;
7277 expr
.X_add_symbol
= symbol
;
7278 expr
.X_add_number
= 0;
7279 emit_expr (&expr
, size
);
7283 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7284 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7287 x86_64_section_letter (int letter
, char **ptr_msg
)
7289 if (flag_code
== CODE_64BIT
)
7292 return SHF_X86_64_LARGE
;
7294 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7297 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
7302 x86_64_section_word (char *str
, size_t len
)
7304 if (len
== 5 && flag_code
== CODE_64BIT
&& strncmp (str
, "large", 5) == 0)
7305 return SHF_X86_64_LARGE
;
7311 handle_large_common (int small ATTRIBUTE_UNUSED
)
7313 if (flag_code
!= CODE_64BIT
)
7315 s_comm_internal (0, elf_common_parse
);
7316 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7320 static segT lbss_section
;
7321 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
7322 asection
*saved_bss_section
= bss_section
;
7324 if (lbss_section
== NULL
)
7326 flagword applicable
;
7328 subsegT subseg
= now_subseg
;
7330 /* The .lbss section is for local .largecomm symbols. */
7331 lbss_section
= subseg_new (".lbss", 0);
7332 applicable
= bfd_applicable_section_flags (stdoutput
);
7333 bfd_set_section_flags (stdoutput
, lbss_section
,
7334 applicable
& SEC_ALLOC
);
7335 seg_info (lbss_section
)->bss
= 1;
7337 subseg_set (seg
, subseg
);
7340 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
7341 bss_section
= lbss_section
;
7343 s_comm_internal (0, elf_common_parse
);
7345 elf_com_section_ptr
= saved_com_section_ptr
;
7346 bss_section
= saved_bss_section
;
7349 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */