1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template
*start
;
100 const insn_template
*end
;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem
; /* codes register or memory operand */
108 unsigned int reg
; /* codes register operand (or extended opcode) */
109 unsigned int mode
; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte
;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name
; /* arch name */
129 unsigned int len
; /* arch string length */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
132 unsigned int skip
; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 i386_cpu_flags flags
; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c
);
158 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
160 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS
*);
165 static int i386_intel_parse_name (const char *, expressionS
*);
166 static const reg_entry
*parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template
*match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry
*build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS
*, offsetT
);
185 static void output_disp (fragS
*, offsetT
);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
192 /* GNU_PROPERTY_X86_ISA_1_USED. */
193 static unsigned int x86_isa_1_used
;
194 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
195 static unsigned int x86_feature_2_used
;
196 /* Generate x86 used ISA and feature properties. */
197 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
200 static const char *default_arch
= DEFAULT_ARCH
;
202 /* This struct describes rounding control and SAE in the instruction. */
216 static struct RC_Operation rc_op
;
218 /* The struct describes masking, applied to OPERAND in the instruction.
219 MASK is a pointer to the corresponding mask register. ZEROING tells
220 whether merging or zeroing mask is used. */
221 struct Mask_Operation
223 const reg_entry
*mask
;
224 unsigned int zeroing
;
225 /* The operand where this operation is associated. */
229 static struct Mask_Operation mask_op
;
231 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
233 struct Broadcast_Operation
235 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
238 /* Index of broadcasted operand. */
241 /* Number of bytes to broadcast. */
245 static struct Broadcast_Operation broadcast_op
;
250 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
251 unsigned char bytes
[4];
253 /* Destination or source register specifier. */
254 const reg_entry
*register_specifier
;
257 /* 'md_assemble ()' gathers together information and puts it into a
264 const reg_entry
*regs
;
269 operand_size_mismatch
,
270 operand_type_mismatch
,
271 register_type_mismatch
,
272 number_of_operands_mismatch
,
273 invalid_instruction_suffix
,
275 unsupported_with_intel_mnemonic
,
278 invalid_vsib_address
,
279 invalid_vector_register_set
,
280 unsupported_vector_index_register
,
281 unsupported_broadcast
,
284 mask_not_on_destination
,
287 rc_sae_operand_not_last_imm
,
288 invalid_register_operand
,
293 /* TM holds the template for the insn were currently assembling. */
296 /* SUFFIX holds the instruction size suffix for byte, word, dword
297 or qword, if given. */
300 /* OPERANDS gives the number of given operands. */
301 unsigned int operands
;
303 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
304 of given register, displacement, memory operands and immediate
306 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
308 /* TYPES [i] is the type (see above #defines) which tells us how to
309 use OP[i] for the corresponding operand. */
310 i386_operand_type types
[MAX_OPERANDS
];
312 /* Displacement expression, immediate expression, or register for each
314 union i386_op op
[MAX_OPERANDS
];
316 /* Flags for operands. */
317 unsigned int flags
[MAX_OPERANDS
];
318 #define Operand_PCrel 1
319 #define Operand_Mem 2
321 /* Relocation type for operand */
322 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
324 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
325 the base index byte below. */
326 const reg_entry
*base_reg
;
327 const reg_entry
*index_reg
;
328 unsigned int log2_scale_factor
;
330 /* SEG gives the seg_entries of this insn. They are zero unless
331 explicit segment overrides are given. */
332 const seg_entry
*seg
[2];
334 /* Copied first memory operand string, for re-checking. */
337 /* PREFIX holds all the given prefix opcodes (usually null).
338 PREFIXES is the number of prefix opcodes. */
339 unsigned int prefixes
;
340 unsigned char prefix
[MAX_PREFIXES
];
342 /* Has MMX register operands. */
343 bfd_boolean has_regmmx
;
345 /* Has XMM register operands. */
346 bfd_boolean has_regxmm
;
348 /* Has YMM register operands. */
349 bfd_boolean has_regymm
;
351 /* Has ZMM register operands. */
352 bfd_boolean has_regzmm
;
354 /* RM and SIB are the modrm byte and the sib byte where the
355 addressing modes of this insn are encoded. */
362 /* Masking attributes. */
363 struct Mask_Operation
*mask
;
365 /* Rounding control and SAE attributes. */
366 struct RC_Operation
*rounding
;
368 /* Broadcasting attributes. */
369 struct Broadcast_Operation
*broadcast
;
371 /* Compressed disp8*N attribute. */
372 unsigned int memshift
;
374 /* Prefer load or store in encoding. */
377 dir_encoding_default
= 0,
383 /* Prefer 8bit or 32bit displacement in encoding. */
386 disp_encoding_default
= 0,
391 /* Prefer the REX byte in encoding. */
392 bfd_boolean rex_encoding
;
394 /* Disable instruction size optimization. */
395 bfd_boolean no_optimize
;
397 /* How to encode vector instructions. */
400 vex_encoding_default
= 0,
407 const char *rep_prefix
;
410 const char *hle_prefix
;
412 /* Have BND prefix. */
413 const char *bnd_prefix
;
415 /* Have NOTRACK prefix. */
416 const char *notrack_prefix
;
419 enum i386_error error
;
422 typedef struct _i386_insn i386_insn
;
424 /* Link RC type with corresponding string, that'll be looked for in
433 static const struct RC_name RC_NamesTable
[] =
435 { rne
, STRING_COMMA_LEN ("rn-sae") },
436 { rd
, STRING_COMMA_LEN ("rd-sae") },
437 { ru
, STRING_COMMA_LEN ("ru-sae") },
438 { rz
, STRING_COMMA_LEN ("rz-sae") },
439 { saeonly
, STRING_COMMA_LEN ("sae") },
442 /* List of chars besides those in app.c:symbol_chars that can start an
443 operand. Used to prevent the scrubber eating vital white-space. */
444 const char extra_symbol_chars
[] = "*%-([{}"
453 #if (defined (TE_I386AIX) \
454 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
455 && !defined (TE_GNU) \
456 && !defined (TE_LINUX) \
457 && !defined (TE_NACL) \
458 && !defined (TE_FreeBSD) \
459 && !defined (TE_DragonFly) \
460 && !defined (TE_NetBSD)))
461 /* This array holds the chars that always start a comment. If the
462 pre-processor is disabled, these aren't very useful. The option
463 --divide will remove '/' from this list. */
464 const char *i386_comment_chars
= "#/";
465 #define SVR4_COMMENT_CHARS 1
466 #define PREFIX_SEPARATOR '\\'
469 const char *i386_comment_chars
= "#";
470 #define PREFIX_SEPARATOR '/'
473 /* This array holds the chars that only start a comment at the beginning of
474 a line. If the line seems to have the form '# 123 filename'
475 .line and .file directives will appear in the pre-processed output.
476 Note that input_file.c hand checks for '#' at the beginning of the
477 first line of the input file. This is because the compiler outputs
478 #NO_APP at the beginning of its output.
479 Also note that comments started like this one will always work if
480 '/' isn't otherwise defined. */
481 const char line_comment_chars
[] = "#/";
483 const char line_separator_chars
[] = ";";
485 /* Chars that can be used to separate mant from exp in floating point
487 const char EXP_CHARS
[] = "eE";
489 /* Chars that mean this number is a floating point constant
492 const char FLT_CHARS
[] = "fFdDxX";
494 /* Tables for lexical analysis. */
495 static char mnemonic_chars
[256];
496 static char register_chars
[256];
497 static char operand_chars
[256];
498 static char identifier_chars
[256];
499 static char digit_chars
[256];
501 /* Lexical macros. */
502 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
503 #define is_operand_char(x) (operand_chars[(unsigned char) x])
504 #define is_register_char(x) (register_chars[(unsigned char) x])
505 #define is_space_char(x) ((x) == ' ')
506 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
507 #define is_digit_char(x) (digit_chars[(unsigned char) x])
509 /* All non-digit non-letter characters that may occur in an operand. */
510 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
512 /* md_assemble() always leaves the strings it's passed unaltered. To
513 effect this we maintain a stack of saved characters that we've smashed
514 with '\0's (indicating end of strings for various sub-fields of the
515 assembler instruction). */
516 static char save_stack
[32];
517 static char *save_stack_p
;
518 #define END_STRING_AND_SAVE(s) \
519 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
520 #define RESTORE_END_STRING(s) \
521 do { *(s) = *--save_stack_p; } while (0)
523 /* The instruction we're assembling. */
526 /* Possible templates for current insn. */
527 static const templates
*current_templates
;
529 /* Per instruction expressionS buffers: max displacements & immediates. */
530 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
531 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
533 /* Current operand we are working on. */
534 static int this_operand
= -1;
536 /* We support four different modes. FLAG_CODE variable is used to distinguish
544 static enum flag_code flag_code
;
545 static unsigned int object_64bit
;
546 static unsigned int disallow_64bit_reloc
;
547 static int use_rela_relocations
= 0;
549 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
550 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
551 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
553 /* The ELF ABI to use. */
561 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
564 #if defined (TE_PE) || defined (TE_PEP)
565 /* Use big object file format. */
566 static int use_big_obj
= 0;
569 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570 /* 1 if generating code for a shared library. */
571 static int shared
= 0;
574 /* 1 for intel syntax,
576 static int intel_syntax
= 0;
578 /* 1 for Intel64 ISA,
582 /* 1 for intel mnemonic,
583 0 if att mnemonic. */
584 static int intel_mnemonic
= !SYSV386_COMPAT
;
586 /* 1 if pseudo registers are permitted. */
587 static int allow_pseudo_reg
= 0;
589 /* 1 if register prefix % not required. */
590 static int allow_naked_reg
= 0;
592 /* 1 if the assembler should add BND prefix for all control-transferring
593 instructions supporting it, even if this prefix wasn't specified
595 static int add_bnd_prefix
= 0;
597 /* 1 if pseudo index register, eiz/riz, is allowed . */
598 static int allow_index_reg
= 0;
600 /* 1 if the assembler should ignore LOCK prefix, even if it was
601 specified explicitly. */
602 static int omit_lock_prefix
= 0;
604 /* 1 if the assembler should encode lfence, mfence, and sfence as
605 "lock addl $0, (%{re}sp)". */
606 static int avoid_fence
= 0;
608 /* 1 if the assembler should generate relax relocations. */
610 static int generate_relax_relocations
611 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
613 static enum check_kind
619 sse_check
, operand_check
= check_warning
;
622 1. Clear the REX_W bit with register operand if possible.
623 2. Above plus use 128bit vector instruction to clear the full vector
626 static int optimize
= 0;
629 1. Clear the REX_W bit with register operand if possible.
630 2. Above plus use 128bit vector instruction to clear the full vector
632 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
635 static int optimize_for_space
= 0;
637 /* Register prefix used for error message. */
638 static const char *register_prefix
= "%";
640 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
641 leave, push, and pop instructions so that gcc has the same stack
642 frame as in 32 bit mode. */
643 static char stackop_size
= '\0';
645 /* Non-zero to optimize code alignment. */
646 int optimize_align_code
= 1;
648 /* Non-zero to quieten some warnings. */
649 static int quiet_warnings
= 0;
652 static const char *cpu_arch_name
= NULL
;
653 static char *cpu_sub_arch_name
= NULL
;
655 /* CPU feature flags. */
656 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
658 /* If we have selected a cpu we are generating instructions for. */
659 static int cpu_arch_tune_set
= 0;
661 /* Cpu we are generating instructions for. */
662 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
664 /* CPU feature flags of cpu we are generating instructions for. */
665 static i386_cpu_flags cpu_arch_tune_flags
;
667 /* CPU instruction set architecture used. */
668 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
670 /* CPU feature flags of instruction set architecture used. */
671 i386_cpu_flags cpu_arch_isa_flags
;
673 /* If set, conditional jumps are not automatically promoted to handle
674 larger than a byte offset. */
675 static unsigned int no_cond_jump_promotion
= 0;
677 /* Encode SSE instructions with VEX prefix. */
678 static unsigned int sse2avx
;
680 /* Encode scalar AVX instructions with specific vector length. */
687 /* Encode VEX WIG instructions with specific vex.w. */
694 /* Encode scalar EVEX LIG instructions with specific vector length. */
702 /* Encode EVEX WIG instructions with specific evex.w. */
709 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
710 static enum rc_type evexrcig
= rne
;
712 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
713 static symbolS
*GOT_symbol
;
715 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
716 unsigned int x86_dwarf2_return_column
;
718 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
719 int x86_cie_data_alignment
;
721 /* Interface to relax_segment.
722 There are 3 major relax states for 386 jump insns because the
723 different types of jumps add different sizes to frags when we're
724 figuring out what sort of jump to choose to reach a given label. */
727 #define UNCOND_JUMP 0
729 #define COND_JUMP86 2
734 #define SMALL16 (SMALL | CODE16)
736 #define BIG16 (BIG | CODE16)
740 #define INLINE __inline__
746 #define ENCODE_RELAX_STATE(type, size) \
747 ((relax_substateT) (((type) << 2) | (size)))
748 #define TYPE_FROM_RELAX_STATE(s) \
750 #define DISP_SIZE_FROM_RELAX_STATE(s) \
751 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
753 /* This table is used by relax_frag to promote short jumps to long
754 ones where necessary. SMALL (short) jumps may be promoted to BIG
755 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
756 don't allow a short jump in a 32 bit code segment to be promoted to
757 a 16 bit offset jump because it's slower (requires data size
758 prefix), and doesn't work, unless the destination is in the bottom
759 64k of the code segment (The top 16 bits of eip are zeroed). */
761 const relax_typeS md_relax_table
[] =
764 1) most positive reach of this state,
765 2) most negative reach of this state,
766 3) how many bytes this mode will have in the variable part of the frag
767 4) which index into the table to try if we can't fit into this one. */
769 /* UNCOND_JUMP states. */
770 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
771 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
772 /* dword jmp adds 4 bytes to frag:
773 0 extra opcode bytes, 4 displacement bytes. */
775 /* word jmp adds 2 byte2 to frag:
776 0 extra opcode bytes, 2 displacement bytes. */
779 /* COND_JUMP states. */
780 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
781 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
782 /* dword conditionals adds 5 bytes to frag:
783 1 extra opcode byte, 4 displacement bytes. */
785 /* word conditionals add 3 bytes to frag:
786 1 extra opcode byte, 2 displacement bytes. */
789 /* COND_JUMP86 states. */
790 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
791 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
792 /* dword conditionals adds 5 bytes to frag:
793 1 extra opcode byte, 4 displacement bytes. */
795 /* word conditionals add 4 bytes to frag:
796 1 displacement byte and a 3 byte long branch insn. */
800 static const arch_entry cpu_arch
[] =
802 /* Do not replace the first two entries - i386_target_format()
803 relies on them being there in this order. */
804 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
805 CPU_GENERIC32_FLAGS
, 0 },
806 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
807 CPU_GENERIC64_FLAGS
, 0 },
808 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
810 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
812 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
814 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
816 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
818 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
820 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
822 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
824 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
825 CPU_PENTIUMPRO_FLAGS
, 0 },
826 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
828 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
830 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
832 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
834 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
835 CPU_NOCONA_FLAGS
, 0 },
836 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
838 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
840 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
841 CPU_CORE2_FLAGS
, 1 },
842 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
843 CPU_CORE2_FLAGS
, 0 },
844 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
845 CPU_COREI7_FLAGS
, 0 },
846 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
848 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
850 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
851 CPU_IAMCU_FLAGS
, 0 },
852 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
854 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
856 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
857 CPU_ATHLON_FLAGS
, 0 },
858 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
860 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
862 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
864 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
865 CPU_AMDFAM10_FLAGS
, 0 },
866 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
867 CPU_BDVER1_FLAGS
, 0 },
868 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
869 CPU_BDVER2_FLAGS
, 0 },
870 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
871 CPU_BDVER3_FLAGS
, 0 },
872 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
873 CPU_BDVER4_FLAGS
, 0 },
874 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
875 CPU_ZNVER1_FLAGS
, 0 },
876 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
877 CPU_ZNVER2_FLAGS
, 0 },
878 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
879 CPU_BTVER1_FLAGS
, 0 },
880 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
881 CPU_BTVER2_FLAGS
, 0 },
882 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
884 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
886 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
888 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
890 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
892 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
894 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
896 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
898 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
900 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
902 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
903 CPU_SSSE3_FLAGS
, 0 },
904 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
905 CPU_SSE4_1_FLAGS
, 0 },
906 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
907 CPU_SSE4_2_FLAGS
, 0 },
908 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
909 CPU_SSE4_2_FLAGS
, 0 },
910 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
912 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
914 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
915 CPU_AVX512F_FLAGS
, 0 },
916 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
917 CPU_AVX512CD_FLAGS
, 0 },
918 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
919 CPU_AVX512ER_FLAGS
, 0 },
920 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
921 CPU_AVX512PF_FLAGS
, 0 },
922 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
923 CPU_AVX512DQ_FLAGS
, 0 },
924 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
925 CPU_AVX512BW_FLAGS
, 0 },
926 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
927 CPU_AVX512VL_FLAGS
, 0 },
928 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
930 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
931 CPU_VMFUNC_FLAGS
, 0 },
932 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
934 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
935 CPU_XSAVE_FLAGS
, 0 },
936 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
937 CPU_XSAVEOPT_FLAGS
, 0 },
938 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
939 CPU_XSAVEC_FLAGS
, 0 },
940 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
941 CPU_XSAVES_FLAGS
, 0 },
942 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
944 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
945 CPU_PCLMUL_FLAGS
, 0 },
946 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
947 CPU_PCLMUL_FLAGS
, 1 },
948 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
949 CPU_FSGSBASE_FLAGS
, 0 },
950 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
951 CPU_RDRND_FLAGS
, 0 },
952 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
954 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
956 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
958 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
960 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
962 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
964 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
965 CPU_MOVBE_FLAGS
, 0 },
966 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
968 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
970 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
971 CPU_LZCNT_FLAGS
, 0 },
972 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
974 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
976 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
977 CPU_INVPCID_FLAGS
, 0 },
978 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
979 CPU_CLFLUSH_FLAGS
, 0 },
980 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
982 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
983 CPU_SYSCALL_FLAGS
, 0 },
984 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
985 CPU_RDTSCP_FLAGS
, 0 },
986 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
987 CPU_3DNOW_FLAGS
, 0 },
988 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
989 CPU_3DNOWA_FLAGS
, 0 },
990 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
991 CPU_PADLOCK_FLAGS
, 0 },
992 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
994 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
996 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
997 CPU_SSE4A_FLAGS
, 0 },
998 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1000 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1002 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1004 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1006 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1007 CPU_RDSEED_FLAGS
, 0 },
1008 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1009 CPU_PRFCHW_FLAGS
, 0 },
1010 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1011 CPU_SMAP_FLAGS
, 0 },
1012 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1014 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1016 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1017 CPU_CLFLUSHOPT_FLAGS
, 0 },
1018 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1019 CPU_PREFETCHWT1_FLAGS
, 0 },
1020 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1022 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1023 CPU_CLWB_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1025 CPU_AVX512IFMA_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1027 CPU_AVX512VBMI_FLAGS
, 0 },
1028 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1029 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1030 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1031 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1032 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1033 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1035 CPU_AVX512_VBMI2_FLAGS
, 0 },
1036 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1037 CPU_AVX512_VNNI_FLAGS
, 0 },
1038 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1039 CPU_AVX512_BITALG_FLAGS
, 0 },
1040 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1041 CPU_CLZERO_FLAGS
, 0 },
1042 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1043 CPU_MWAITX_FLAGS
, 0 },
1044 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1045 CPU_OSPKE_FLAGS
, 0 },
1046 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1047 CPU_RDPID_FLAGS
, 0 },
1048 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1049 CPU_PTWRITE_FLAGS
, 0 },
1050 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1052 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1053 CPU_SHSTK_FLAGS
, 0 },
1054 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1055 CPU_GFNI_FLAGS
, 0 },
1056 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1057 CPU_VAES_FLAGS
, 0 },
1058 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1059 CPU_VPCLMULQDQ_FLAGS
, 0 },
1060 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1061 CPU_WBNOINVD_FLAGS
, 0 },
1062 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1063 CPU_PCONFIG_FLAGS
, 0 },
1064 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1065 CPU_WAITPKG_FLAGS
, 0 },
1066 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1067 CPU_CLDEMOTE_FLAGS
, 0 },
1068 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1069 CPU_MOVDIRI_FLAGS
, 0 },
1070 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1071 CPU_MOVDIR64B_FLAGS
, 0 },
1074 static const noarch_entry cpu_noarch
[] =
1076 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1077 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1078 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1079 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1080 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1081 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1082 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1083 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1084 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1085 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1086 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1087 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1088 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1089 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1090 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1091 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1092 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1093 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1094 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1095 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1096 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1097 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1098 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1099 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1100 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1101 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1102 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1103 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1104 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1105 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1106 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1107 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1108 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1109 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1110 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1114 /* Like s_lcomm_internal in gas/read.c but the alignment string
1115 is allowed to be optional. */
1118 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1125 && *input_line_pointer
== ',')
1127 align
= parse_align (needs_align
- 1);
1129 if (align
== (addressT
) -1)
1144 bss_alloc (symbolP
, size
, align
);
1149 pe_lcomm (int needs_align
)
1151 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1155 const pseudo_typeS md_pseudo_table
[] =
1157 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1158 {"align", s_align_bytes
, 0},
1160 {"align", s_align_ptwo
, 0},
1162 {"arch", set_cpu_arch
, 0},
1166 {"lcomm", pe_lcomm
, 1},
1168 {"ffloat", float_cons
, 'f'},
1169 {"dfloat", float_cons
, 'd'},
1170 {"tfloat", float_cons
, 'x'},
1172 {"slong", signed_cons
, 4},
1173 {"noopt", s_ignore
, 0},
1174 {"optim", s_ignore
, 0},
1175 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1176 {"code16", set_code_flag
, CODE_16BIT
},
1177 {"code32", set_code_flag
, CODE_32BIT
},
1179 {"code64", set_code_flag
, CODE_64BIT
},
1181 {"intel_syntax", set_intel_syntax
, 1},
1182 {"att_syntax", set_intel_syntax
, 0},
1183 {"intel_mnemonic", set_intel_mnemonic
, 1},
1184 {"att_mnemonic", set_intel_mnemonic
, 0},
1185 {"allow_index_reg", set_allow_index_reg
, 1},
1186 {"disallow_index_reg", set_allow_index_reg
, 0},
1187 {"sse_check", set_check
, 0},
1188 {"operand_check", set_check
, 1},
1189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1190 {"largecomm", handle_large_common
, 0},
1192 {"file", dwarf2_directive_file
, 0},
1193 {"loc", dwarf2_directive_loc
, 0},
1194 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1197 {"secrel32", pe_directive_secrel
, 0},
1202 /* For interface with expression (). */
1203 extern char *input_line_pointer
;
1205 /* Hash table for instruction mnemonic lookup. */
1206 static struct hash_control
*op_hash
;
1208 /* Hash table for register lookup. */
1209 static struct hash_control
*reg_hash
;
1211 /* Various efficient no-op patterns for aligning code labels.
1212 Note: Don't try to assemble the instructions in the comments.
1213 0L and 0w are not legal. */
1214 static const unsigned char f32_1
[] =
1216 static const unsigned char f32_2
[] =
1217 {0x66,0x90}; /* xchg %ax,%ax */
1218 static const unsigned char f32_3
[] =
1219 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1220 static const unsigned char f32_4
[] =
1221 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1222 static const unsigned char f32_6
[] =
1223 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1224 static const unsigned char f32_7
[] =
1225 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1226 static const unsigned char f16_3
[] =
1227 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1228 static const unsigned char f16_4
[] =
1229 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1230 static const unsigned char jump_disp8
[] =
1231 {0xeb}; /* jmp disp8 */
1232 static const unsigned char jump32_disp32
[] =
1233 {0xe9}; /* jmp disp32 */
1234 static const unsigned char jump16_disp32
[] =
1235 {0x66,0xe9}; /* jmp disp32 */
1236 /* 32-bit NOPs patterns. */
1237 static const unsigned char *const f32_patt
[] = {
1238 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1240 /* 16-bit NOPs patterns. */
1241 static const unsigned char *const f16_patt
[] = {
1242 f32_1
, f32_2
, f16_3
, f16_4
1244 /* nopl (%[re]ax) */
1245 static const unsigned char alt_3
[] =
1247 /* nopl 0(%[re]ax) */
1248 static const unsigned char alt_4
[] =
1249 {0x0f,0x1f,0x40,0x00};
1250 /* nopl 0(%[re]ax,%[re]ax,1) */
1251 static const unsigned char alt_5
[] =
1252 {0x0f,0x1f,0x44,0x00,0x00};
1253 /* nopw 0(%[re]ax,%[re]ax,1) */
1254 static const unsigned char alt_6
[] =
1255 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1256 /* nopl 0L(%[re]ax) */
1257 static const unsigned char alt_7
[] =
1258 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1259 /* nopl 0L(%[re]ax,%[re]ax,1) */
1260 static const unsigned char alt_8
[] =
1261 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1262 /* nopw 0L(%[re]ax,%[re]ax,1) */
1263 static const unsigned char alt_9
[] =
1264 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1265 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1266 static const unsigned char alt_10
[] =
1267 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1268 /* data16 nopw %cs:0L(%eax,%eax,1) */
1269 static const unsigned char alt_11
[] =
1270 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1271 /* 32-bit and 64-bit NOPs patterns. */
1272 static const unsigned char *const alt_patt
[] = {
1273 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1274 alt_9
, alt_10
, alt_11
1277 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1278 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1281 i386_output_nops (char *where
, const unsigned char *const *patt
,
1282 int count
, int max_single_nop_size
)
1285 /* Place the longer NOP first. */
1288 const unsigned char *nops
= patt
[max_single_nop_size
- 1];
1290 /* Use the smaller one if the requsted one isn't available. */
1293 max_single_nop_size
--;
1294 nops
= patt
[max_single_nop_size
- 1];
1297 last
= count
% max_single_nop_size
;
1300 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1301 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1305 nops
= patt
[last
- 1];
1308 /* Use the smaller one plus one-byte NOP if the needed one
1311 nops
= patt
[last
- 1];
1312 memcpy (where
+ offset
, nops
, last
);
1313 where
[offset
+ last
] = *patt
[0];
1316 memcpy (where
+ offset
, nops
, last
);
1321 fits_in_imm7 (offsetT num
)
1323 return (num
& 0x7f) == num
;
1327 fits_in_imm31 (offsetT num
)
1329 return (num
& 0x7fffffff) == num
;
1332 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1333 single NOP instruction LIMIT. */
1336 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1338 const unsigned char *const *patt
= NULL
;
1339 int max_single_nop_size
;
1340 /* Maximum number of NOPs before switching to jump over NOPs. */
1341 int max_number_of_nops
;
1343 switch (fragP
->fr_type
)
1352 /* We need to decide which NOP sequence to use for 32bit and
1353 64bit. When -mtune= is used:
1355 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1356 PROCESSOR_GENERIC32, f32_patt will be used.
1357 2. For the rest, alt_patt will be used.
1359 When -mtune= isn't used, alt_patt will be used if
1360 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1363 When -march= or .arch is used, we can't use anything beyond
1364 cpu_arch_isa_flags. */
1366 if (flag_code
== CODE_16BIT
)
1369 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1370 /* Limit number of NOPs to 2 in 16-bit mode. */
1371 max_number_of_nops
= 2;
1375 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1377 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1378 switch (cpu_arch_tune
)
1380 case PROCESSOR_UNKNOWN
:
1381 /* We use cpu_arch_isa_flags to check if we SHOULD
1382 optimize with nops. */
1383 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1388 case PROCESSOR_PENTIUM4
:
1389 case PROCESSOR_NOCONA
:
1390 case PROCESSOR_CORE
:
1391 case PROCESSOR_CORE2
:
1392 case PROCESSOR_COREI7
:
1393 case PROCESSOR_L1OM
:
1394 case PROCESSOR_K1OM
:
1395 case PROCESSOR_GENERIC64
:
1397 case PROCESSOR_ATHLON
:
1399 case PROCESSOR_AMDFAM10
:
1401 case PROCESSOR_ZNVER
:
1405 case PROCESSOR_I386
:
1406 case PROCESSOR_I486
:
1407 case PROCESSOR_PENTIUM
:
1408 case PROCESSOR_PENTIUMPRO
:
1409 case PROCESSOR_IAMCU
:
1410 case PROCESSOR_GENERIC32
:
1417 switch (fragP
->tc_frag_data
.tune
)
1419 case PROCESSOR_UNKNOWN
:
1420 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1421 PROCESSOR_UNKNOWN. */
1425 case PROCESSOR_I386
:
1426 case PROCESSOR_I486
:
1427 case PROCESSOR_PENTIUM
:
1428 case PROCESSOR_IAMCU
:
1430 case PROCESSOR_ATHLON
:
1432 case PROCESSOR_AMDFAM10
:
1434 case PROCESSOR_ZNVER
:
1436 case PROCESSOR_GENERIC32
:
1437 /* We use cpu_arch_isa_flags to check if we CAN optimize
1439 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1444 case PROCESSOR_PENTIUMPRO
:
1445 case PROCESSOR_PENTIUM4
:
1446 case PROCESSOR_NOCONA
:
1447 case PROCESSOR_CORE
:
1448 case PROCESSOR_CORE2
:
1449 case PROCESSOR_COREI7
:
1450 case PROCESSOR_L1OM
:
1451 case PROCESSOR_K1OM
:
1452 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1457 case PROCESSOR_GENERIC64
:
1463 if (patt
== f32_patt
)
1465 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1466 /* Limit number of NOPs to 2 for older processors. */
1467 max_number_of_nops
= 2;
1471 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1472 /* Limit number of NOPs to 7 for newer processors. */
1473 max_number_of_nops
= 7;
1478 limit
= max_single_nop_size
;
1480 if (fragP
->fr_type
== rs_fill_nop
)
1482 /* Output NOPs for .nop directive. */
1483 if (limit
> max_single_nop_size
)
1485 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1486 _("invalid single nop size: %d "
1487 "(expect within [0, %d])"),
1488 limit
, max_single_nop_size
);
1493 fragP
->fr_var
= count
;
1495 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1497 /* Generate jump over NOPs. */
1498 offsetT disp
= count
- 2;
1499 if (fits_in_imm7 (disp
))
1501 /* Use "jmp disp8" if possible. */
1503 where
[0] = jump_disp8
[0];
1509 unsigned int size_of_jump
;
1511 if (flag_code
== CODE_16BIT
)
1513 where
[0] = jump16_disp32
[0];
1514 where
[1] = jump16_disp32
[1];
1519 where
[0] = jump32_disp32
[0];
1523 count
-= size_of_jump
+ 4;
1524 if (!fits_in_imm31 (count
))
1526 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1527 _("jump over nop padding out of range"));
1531 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1532 where
+= size_of_jump
+ 4;
1536 /* Generate multiple NOPs. */
1537 i386_output_nops (where
, patt
, count
, limit
);
1541 operand_type_all_zero (const union i386_operand_type
*x
)
1543 switch (ARRAY_SIZE(x
->array
))
1554 return !x
->array
[0];
1561 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1563 switch (ARRAY_SIZE(x
->array
))
1581 operand_type_equal (const union i386_operand_type
*x
,
1582 const union i386_operand_type
*y
)
1584 switch (ARRAY_SIZE(x
->array
))
1587 if (x
->array
[2] != y
->array
[2])
1591 if (x
->array
[1] != y
->array
[1])
1595 return x
->array
[0] == y
->array
[0];
1603 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1605 switch (ARRAY_SIZE(x
->array
))
1620 return !x
->array
[0];
1627 cpu_flags_equal (const union i386_cpu_flags
*x
,
1628 const union i386_cpu_flags
*y
)
1630 switch (ARRAY_SIZE(x
->array
))
1633 if (x
->array
[3] != y
->array
[3])
1637 if (x
->array
[2] != y
->array
[2])
1641 if (x
->array
[1] != y
->array
[1])
1645 return x
->array
[0] == y
->array
[0];
1653 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1655 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1656 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1659 static INLINE i386_cpu_flags
1660 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1662 switch (ARRAY_SIZE (x
.array
))
1665 x
.array
[3] &= y
.array
[3];
1668 x
.array
[2] &= y
.array
[2];
1671 x
.array
[1] &= y
.array
[1];
1674 x
.array
[0] &= y
.array
[0];
1682 static INLINE i386_cpu_flags
1683 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1685 switch (ARRAY_SIZE (x
.array
))
1688 x
.array
[3] |= y
.array
[3];
1691 x
.array
[2] |= y
.array
[2];
1694 x
.array
[1] |= y
.array
[1];
1697 x
.array
[0] |= y
.array
[0];
1705 static INLINE i386_cpu_flags
1706 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1708 switch (ARRAY_SIZE (x
.array
))
1711 x
.array
[3] &= ~y
.array
[3];
1714 x
.array
[2] &= ~y
.array
[2];
1717 x
.array
[1] &= ~y
.array
[1];
1720 x
.array
[0] &= ~y
.array
[0];
1728 #define CPU_FLAGS_ARCH_MATCH 0x1
1729 #define CPU_FLAGS_64BIT_MATCH 0x2
1731 #define CPU_FLAGS_PERFECT_MATCH \
1732 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1734 /* Return CPU flags match bits. */
1737 cpu_flags_match (const insn_template
*t
)
1739 i386_cpu_flags x
= t
->cpu_flags
;
1740 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1742 x
.bitfield
.cpu64
= 0;
1743 x
.bitfield
.cpuno64
= 0;
1745 if (cpu_flags_all_zero (&x
))
1747 /* This instruction is available on all archs. */
1748 match
|= CPU_FLAGS_ARCH_MATCH
;
1752 /* This instruction is available only on some archs. */
1753 i386_cpu_flags cpu
= cpu_arch_flags
;
1755 /* AVX512VL is no standalone feature - match it and then strip it. */
1756 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1758 x
.bitfield
.cpuavx512vl
= 0;
1760 cpu
= cpu_flags_and (x
, cpu
);
1761 if (!cpu_flags_all_zero (&cpu
))
1763 if (x
.bitfield
.cpuavx
)
1765 /* We need to check a few extra flags with AVX. */
1766 if (cpu
.bitfield
.cpuavx
1767 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1768 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1769 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1770 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1771 match
|= CPU_FLAGS_ARCH_MATCH
;
1773 else if (x
.bitfield
.cpuavx512f
)
1775 /* We need to check a few extra flags with AVX512F. */
1776 if (cpu
.bitfield
.cpuavx512f
1777 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1778 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1779 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1780 match
|= CPU_FLAGS_ARCH_MATCH
;
1783 match
|= CPU_FLAGS_ARCH_MATCH
;
1789 static INLINE i386_operand_type
1790 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1792 switch (ARRAY_SIZE (x
.array
))
1795 x
.array
[2] &= y
.array
[2];
1798 x
.array
[1] &= y
.array
[1];
1801 x
.array
[0] &= y
.array
[0];
1809 static INLINE i386_operand_type
1810 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1812 switch (ARRAY_SIZE (x
.array
))
1815 x
.array
[2] &= ~y
.array
[2];
1818 x
.array
[1] &= ~y
.array
[1];
1821 x
.array
[0] &= ~y
.array
[0];
1829 static INLINE i386_operand_type
1830 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1832 switch (ARRAY_SIZE (x
.array
))
1835 x
.array
[2] |= y
.array
[2];
1838 x
.array
[1] |= y
.array
[1];
1841 x
.array
[0] |= y
.array
[0];
1849 static INLINE i386_operand_type
1850 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1852 switch (ARRAY_SIZE (x
.array
))
1855 x
.array
[2] ^= y
.array
[2];
1858 x
.array
[1] ^= y
.array
[1];
1861 x
.array
[0] ^= y
.array
[0];
1869 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1870 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1871 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1872 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1873 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1874 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1875 static const i386_operand_type anydisp
1876 = OPERAND_TYPE_ANYDISP
;
1877 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1878 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1879 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1880 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1881 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1882 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1883 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1884 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1885 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1886 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1887 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1888 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1899 operand_type_check (i386_operand_type t
, enum operand_type c
)
1904 return t
.bitfield
.reg
;
1907 return (t
.bitfield
.imm8
1911 || t
.bitfield
.imm32s
1912 || t
.bitfield
.imm64
);
1915 return (t
.bitfield
.disp8
1916 || t
.bitfield
.disp16
1917 || t
.bitfield
.disp32
1918 || t
.bitfield
.disp32s
1919 || t
.bitfield
.disp64
);
1922 return (t
.bitfield
.disp8
1923 || t
.bitfield
.disp16
1924 || t
.bitfield
.disp32
1925 || t
.bitfield
.disp32s
1926 || t
.bitfield
.disp64
1927 || t
.bitfield
.baseindex
);
1936 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1937 between operand GIVEN and opeand WANTED for instruction template T. */
1940 match_operand_size (const insn_template
*t
, unsigned int wanted
,
1943 return !((i
.types
[given
].bitfield
.byte
1944 && !t
->operand_types
[wanted
].bitfield
.byte
)
1945 || (i
.types
[given
].bitfield
.word
1946 && !t
->operand_types
[wanted
].bitfield
.word
)
1947 || (i
.types
[given
].bitfield
.dword
1948 && !t
->operand_types
[wanted
].bitfield
.dword
)
1949 || (i
.types
[given
].bitfield
.qword
1950 && !t
->operand_types
[wanted
].bitfield
.qword
)
1951 || (i
.types
[given
].bitfield
.tbyte
1952 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
1955 /* Return 1 if there is no conflict in SIMD register between operand
1956 GIVEN and opeand WANTED for instruction template T. */
1959 match_simd_size (const insn_template
*t
, unsigned int wanted
,
1962 return !((i
.types
[given
].bitfield
.xmmword
1963 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
1964 || (i
.types
[given
].bitfield
.ymmword
1965 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
1966 || (i
.types
[given
].bitfield
.zmmword
1967 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
1970 /* Return 1 if there is no conflict in any size between operand GIVEN
1971 and opeand WANTED for instruction template T. */
1974 match_mem_size (const insn_template
*t
, unsigned int wanted
,
1977 return (match_operand_size (t
, wanted
, given
)
1978 && !((i
.types
[given
].bitfield
.unspecified
1980 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
1981 || (i
.types
[given
].bitfield
.fword
1982 && !t
->operand_types
[wanted
].bitfield
.fword
)
1983 /* For scalar opcode templates to allow register and memory
1984 operands at the same time, some special casing is needed
1985 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1986 down-conversion vpmov*. */
1987 || ((t
->operand_types
[wanted
].bitfield
.regsimd
1988 && !t
->opcode_modifier
.broadcast
1989 && (t
->operand_types
[wanted
].bitfield
.byte
1990 || t
->operand_types
[wanted
].bitfield
.word
1991 || t
->operand_types
[wanted
].bitfield
.dword
1992 || t
->operand_types
[wanted
].bitfield
.qword
))
1993 ? (i
.types
[given
].bitfield
.xmmword
1994 || i
.types
[given
].bitfield
.ymmword
1995 || i
.types
[given
].bitfield
.zmmword
)
1996 : !match_simd_size(t
, wanted
, given
))));
1999 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2000 operands for instruction template T, and it has MATCH_REVERSE set if there
2001 is no size conflict on any operands for the template with operands reversed
2002 (and the template allows for reversing in the first place). */
2004 #define MATCH_STRAIGHT 1
2005 #define MATCH_REVERSE 2
2007 static INLINE
unsigned int
2008 operand_size_match (const insn_template
*t
)
2010 unsigned int j
, match
= MATCH_STRAIGHT
;
2012 /* Don't check jump instructions. */
2013 if (t
->opcode_modifier
.jump
2014 || t
->opcode_modifier
.jumpbyte
2015 || t
->opcode_modifier
.jumpdword
2016 || t
->opcode_modifier
.jumpintersegment
)
2019 /* Check memory and accumulator operand size. */
2020 for (j
= 0; j
< i
.operands
; j
++)
2022 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
2023 && t
->operand_types
[j
].bitfield
.anysize
)
2026 if (t
->operand_types
[j
].bitfield
.reg
2027 && !match_operand_size (t
, j
, j
))
2033 if (t
->operand_types
[j
].bitfield
.regsimd
2034 && !match_simd_size (t
, j
, j
))
2040 if (t
->operand_types
[j
].bitfield
.acc
2041 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2047 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2054 if (!t
->opcode_modifier
.d
)
2058 i
.error
= operand_size_mismatch
;
2062 /* Check reverse. */
2063 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2065 for (j
= 0; j
< i
.operands
; j
++)
2067 unsigned int given
= i
.operands
- j
- 1;
2069 if (t
->operand_types
[j
].bitfield
.reg
2070 && !match_operand_size (t
, j
, given
))
2073 if (t
->operand_types
[j
].bitfield
.regsimd
2074 && !match_simd_size (t
, j
, given
))
2077 if (t
->operand_types
[j
].bitfield
.acc
2078 && (!match_operand_size (t
, j
, given
)
2079 || !match_simd_size (t
, j
, given
)))
2082 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2086 return match
| MATCH_REVERSE
;
2090 operand_type_match (i386_operand_type overlap
,
2091 i386_operand_type given
)
2093 i386_operand_type temp
= overlap
;
2095 temp
.bitfield
.jumpabsolute
= 0;
2096 temp
.bitfield
.unspecified
= 0;
2097 temp
.bitfield
.byte
= 0;
2098 temp
.bitfield
.word
= 0;
2099 temp
.bitfield
.dword
= 0;
2100 temp
.bitfield
.fword
= 0;
2101 temp
.bitfield
.qword
= 0;
2102 temp
.bitfield
.tbyte
= 0;
2103 temp
.bitfield
.xmmword
= 0;
2104 temp
.bitfield
.ymmword
= 0;
2105 temp
.bitfield
.zmmword
= 0;
2106 if (operand_type_all_zero (&temp
))
2109 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2110 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2114 i
.error
= operand_type_mismatch
;
2118 /* If given types g0 and g1 are registers they must be of the same type
2119 unless the expected operand type register overlap is null.
2120 Memory operand size of certain SIMD instructions is also being checked
2124 operand_type_register_match (i386_operand_type g0
,
2125 i386_operand_type t0
,
2126 i386_operand_type g1
,
2127 i386_operand_type t1
)
2129 if (!g0
.bitfield
.reg
2130 && !g0
.bitfield
.regsimd
2131 && (!operand_type_check (g0
, anymem
)
2132 || g0
.bitfield
.unspecified
2133 || !t0
.bitfield
.regsimd
))
2136 if (!g1
.bitfield
.reg
2137 && !g1
.bitfield
.regsimd
2138 && (!operand_type_check (g1
, anymem
)
2139 || g1
.bitfield
.unspecified
2140 || !t1
.bitfield
.regsimd
))
2143 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2144 && g0
.bitfield
.word
== g1
.bitfield
.word
2145 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2146 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2147 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2148 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2149 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2152 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2153 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2154 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2155 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2156 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2157 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2158 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2161 i
.error
= register_type_mismatch
;
2166 static INLINE
unsigned int
2167 register_number (const reg_entry
*r
)
2169 unsigned int nr
= r
->reg_num
;
2171 if (r
->reg_flags
& RegRex
)
2174 if (r
->reg_flags
& RegVRex
)
2180 static INLINE
unsigned int
2181 mode_from_disp_size (i386_operand_type t
)
2183 if (t
.bitfield
.disp8
)
2185 else if (t
.bitfield
.disp16
2186 || t
.bitfield
.disp32
2187 || t
.bitfield
.disp32s
)
2194 fits_in_signed_byte (addressT num
)
2196 return num
+ 0x80 <= 0xff;
2200 fits_in_unsigned_byte (addressT num
)
2206 fits_in_unsigned_word (addressT num
)
2208 return num
<= 0xffff;
2212 fits_in_signed_word (addressT num
)
2214 return num
+ 0x8000 <= 0xffff;
2218 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2223 return num
+ 0x80000000 <= 0xffffffff;
2225 } /* fits_in_signed_long() */
2228 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2233 return num
<= 0xffffffff;
2235 } /* fits_in_unsigned_long() */
2238 fits_in_disp8 (offsetT num
)
2240 int shift
= i
.memshift
;
2246 mask
= (1 << shift
) - 1;
2248 /* Return 0 if NUM isn't properly aligned. */
2252 /* Check if NUM will fit in 8bit after shift. */
2253 return fits_in_signed_byte (num
>> shift
);
2257 fits_in_imm4 (offsetT num
)
2259 return (num
& 0xf) == num
;
2262 static i386_operand_type
2263 smallest_imm_type (offsetT num
)
2265 i386_operand_type t
;
2267 operand_type_set (&t
, 0);
2268 t
.bitfield
.imm64
= 1;
2270 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2272 /* This code is disabled on the 486 because all the Imm1 forms
2273 in the opcode table are slower on the i486. They're the
2274 versions with the implicitly specified single-position
2275 displacement, which has another syntax if you really want to
2277 t
.bitfield
.imm1
= 1;
2278 t
.bitfield
.imm8
= 1;
2279 t
.bitfield
.imm8s
= 1;
2280 t
.bitfield
.imm16
= 1;
2281 t
.bitfield
.imm32
= 1;
2282 t
.bitfield
.imm32s
= 1;
2284 else if (fits_in_signed_byte (num
))
2286 t
.bitfield
.imm8
= 1;
2287 t
.bitfield
.imm8s
= 1;
2288 t
.bitfield
.imm16
= 1;
2289 t
.bitfield
.imm32
= 1;
2290 t
.bitfield
.imm32s
= 1;
2292 else if (fits_in_unsigned_byte (num
))
2294 t
.bitfield
.imm8
= 1;
2295 t
.bitfield
.imm16
= 1;
2296 t
.bitfield
.imm32
= 1;
2297 t
.bitfield
.imm32s
= 1;
2299 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2301 t
.bitfield
.imm16
= 1;
2302 t
.bitfield
.imm32
= 1;
2303 t
.bitfield
.imm32s
= 1;
2305 else if (fits_in_signed_long (num
))
2307 t
.bitfield
.imm32
= 1;
2308 t
.bitfield
.imm32s
= 1;
2310 else if (fits_in_unsigned_long (num
))
2311 t
.bitfield
.imm32
= 1;
2317 offset_in_range (offsetT val
, int size
)
2323 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2324 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2325 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2327 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2333 /* If BFD64, sign extend val for 32bit address mode. */
2334 if (flag_code
!= CODE_64BIT
2335 || i
.prefix
[ADDR_PREFIX
])
2336 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2337 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2340 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2342 char buf1
[40], buf2
[40];
2344 sprint_value (buf1
, val
);
2345 sprint_value (buf2
, val
& mask
);
2346 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2361 a. PREFIX_EXIST if attempting to add a prefix where one from the
2362 same class already exists.
2363 b. PREFIX_LOCK if lock prefix is added.
2364 c. PREFIX_REP if rep/repne prefix is added.
2365 d. PREFIX_DS if ds prefix is added.
2366 e. PREFIX_OTHER if other prefix is added.
2369 static enum PREFIX_GROUP
2370 add_prefix (unsigned int prefix
)
2372 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2375 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2376 && flag_code
== CODE_64BIT
)
2378 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2379 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2380 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2381 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2392 case DS_PREFIX_OPCODE
:
2395 case CS_PREFIX_OPCODE
:
2396 case ES_PREFIX_OPCODE
:
2397 case FS_PREFIX_OPCODE
:
2398 case GS_PREFIX_OPCODE
:
2399 case SS_PREFIX_OPCODE
:
2403 case REPNE_PREFIX_OPCODE
:
2404 case REPE_PREFIX_OPCODE
:
2409 case LOCK_PREFIX_OPCODE
:
2418 case ADDR_PREFIX_OPCODE
:
2422 case DATA_PREFIX_OPCODE
:
2426 if (i
.prefix
[q
] != 0)
2434 i
.prefix
[q
] |= prefix
;
2437 as_bad (_("same type of prefix used twice"));
2443 update_code_flag (int value
, int check
)
2445 PRINTF_LIKE ((*as_error
));
2447 flag_code
= (enum flag_code
) value
;
2448 if (flag_code
== CODE_64BIT
)
2450 cpu_arch_flags
.bitfield
.cpu64
= 1;
2451 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2455 cpu_arch_flags
.bitfield
.cpu64
= 0;
2456 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2458 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2461 as_error
= as_fatal
;
2464 (*as_error
) (_("64bit mode not supported on `%s'."),
2465 cpu_arch_name
? cpu_arch_name
: default_arch
);
2467 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2470 as_error
= as_fatal
;
2473 (*as_error
) (_("32bit mode not supported on `%s'."),
2474 cpu_arch_name
? cpu_arch_name
: default_arch
);
2476 stackop_size
= '\0';
2480 set_code_flag (int value
)
2482 update_code_flag (value
, 0);
2486 set_16bit_gcc_code_flag (int new_code_flag
)
2488 flag_code
= (enum flag_code
) new_code_flag
;
2489 if (flag_code
!= CODE_16BIT
)
2491 cpu_arch_flags
.bitfield
.cpu64
= 0;
2492 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2493 stackop_size
= LONG_MNEM_SUFFIX
;
2497 set_intel_syntax (int syntax_flag
)
2499 /* Find out if register prefixing is specified. */
2500 int ask_naked_reg
= 0;
2503 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2506 int e
= get_symbol_name (&string
);
2508 if (strcmp (string
, "prefix") == 0)
2510 else if (strcmp (string
, "noprefix") == 0)
2513 as_bad (_("bad argument to syntax directive."));
2514 (void) restore_line_pointer (e
);
2516 demand_empty_rest_of_line ();
2518 intel_syntax
= syntax_flag
;
2520 if (ask_naked_reg
== 0)
2521 allow_naked_reg
= (intel_syntax
2522 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2524 allow_naked_reg
= (ask_naked_reg
< 0);
2526 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2528 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2529 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2530 register_prefix
= allow_naked_reg
? "" : "%";
2534 set_intel_mnemonic (int mnemonic_flag
)
2536 intel_mnemonic
= mnemonic_flag
;
2540 set_allow_index_reg (int flag
)
2542 allow_index_reg
= flag
;
2546 set_check (int what
)
2548 enum check_kind
*kind
;
2553 kind
= &operand_check
;
2564 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2567 int e
= get_symbol_name (&string
);
2569 if (strcmp (string
, "none") == 0)
2571 else if (strcmp (string
, "warning") == 0)
2572 *kind
= check_warning
;
2573 else if (strcmp (string
, "error") == 0)
2574 *kind
= check_error
;
2576 as_bad (_("bad argument to %s_check directive."), str
);
2577 (void) restore_line_pointer (e
);
2580 as_bad (_("missing argument for %s_check directive"), str
);
2582 demand_empty_rest_of_line ();
2586 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2587 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2589 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2590 static const char *arch
;
2592 /* Intel LIOM is only supported on ELF. */
2598 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2599 use default_arch. */
2600 arch
= cpu_arch_name
;
2602 arch
= default_arch
;
2605 /* If we are targeting Intel MCU, we must enable it. */
2606 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2607 || new_flag
.bitfield
.cpuiamcu
)
2610 /* If we are targeting Intel L1OM, we must enable it. */
2611 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2612 || new_flag
.bitfield
.cpul1om
)
2615 /* If we are targeting Intel K1OM, we must enable it. */
2616 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2617 || new_flag
.bitfield
.cpuk1om
)
2620 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2625 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2629 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2632 int e
= get_symbol_name (&string
);
2634 i386_cpu_flags flags
;
2636 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2638 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2640 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2644 cpu_arch_name
= cpu_arch
[j
].name
;
2645 cpu_sub_arch_name
= NULL
;
2646 cpu_arch_flags
= cpu_arch
[j
].flags
;
2647 if (flag_code
== CODE_64BIT
)
2649 cpu_arch_flags
.bitfield
.cpu64
= 1;
2650 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2654 cpu_arch_flags
.bitfield
.cpu64
= 0;
2655 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2657 cpu_arch_isa
= cpu_arch
[j
].type
;
2658 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2659 if (!cpu_arch_tune_set
)
2661 cpu_arch_tune
= cpu_arch_isa
;
2662 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2667 flags
= cpu_flags_or (cpu_arch_flags
,
2670 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2672 if (cpu_sub_arch_name
)
2674 char *name
= cpu_sub_arch_name
;
2675 cpu_sub_arch_name
= concat (name
,
2677 (const char *) NULL
);
2681 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2682 cpu_arch_flags
= flags
;
2683 cpu_arch_isa_flags
= flags
;
2687 = cpu_flags_or (cpu_arch_isa_flags
,
2689 (void) restore_line_pointer (e
);
2690 demand_empty_rest_of_line ();
2695 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2697 /* Disable an ISA extension. */
2698 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2699 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2701 flags
= cpu_flags_and_not (cpu_arch_flags
,
2702 cpu_noarch
[j
].flags
);
2703 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2705 if (cpu_sub_arch_name
)
2707 char *name
= cpu_sub_arch_name
;
2708 cpu_sub_arch_name
= concat (name
, string
,
2709 (const char *) NULL
);
2713 cpu_sub_arch_name
= xstrdup (string
);
2714 cpu_arch_flags
= flags
;
2715 cpu_arch_isa_flags
= flags
;
2717 (void) restore_line_pointer (e
);
2718 demand_empty_rest_of_line ();
2722 j
= ARRAY_SIZE (cpu_arch
);
2725 if (j
>= ARRAY_SIZE (cpu_arch
))
2726 as_bad (_("no such architecture: `%s'"), string
);
2728 *input_line_pointer
= e
;
2731 as_bad (_("missing cpu architecture"));
2733 no_cond_jump_promotion
= 0;
2734 if (*input_line_pointer
== ','
2735 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2740 ++input_line_pointer
;
2741 e
= get_symbol_name (&string
);
2743 if (strcmp (string
, "nojumps") == 0)
2744 no_cond_jump_promotion
= 1;
2745 else if (strcmp (string
, "jumps") == 0)
2748 as_bad (_("no such architecture modifier: `%s'"), string
);
2750 (void) restore_line_pointer (e
);
2753 demand_empty_rest_of_line ();
2756 enum bfd_architecture
2759 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2761 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2762 || flag_code
!= CODE_64BIT
)
2763 as_fatal (_("Intel L1OM is 64bit ELF only"));
2764 return bfd_arch_l1om
;
2766 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2768 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2769 || flag_code
!= CODE_64BIT
)
2770 as_fatal (_("Intel K1OM is 64bit ELF only"));
2771 return bfd_arch_k1om
;
2773 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2775 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2776 || flag_code
== CODE_64BIT
)
2777 as_fatal (_("Intel MCU is 32bit ELF only"));
2778 return bfd_arch_iamcu
;
2781 return bfd_arch_i386
;
2787 if (!strncmp (default_arch
, "x86_64", 6))
2789 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2791 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2792 || default_arch
[6] != '\0')
2793 as_fatal (_("Intel L1OM is 64bit ELF only"));
2794 return bfd_mach_l1om
;
2796 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2798 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2799 || default_arch
[6] != '\0')
2800 as_fatal (_("Intel K1OM is 64bit ELF only"));
2801 return bfd_mach_k1om
;
2803 else if (default_arch
[6] == '\0')
2804 return bfd_mach_x86_64
;
2806 return bfd_mach_x64_32
;
2808 else if (!strcmp (default_arch
, "i386")
2809 || !strcmp (default_arch
, "iamcu"))
2811 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2813 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2814 as_fatal (_("Intel MCU is 32bit ELF only"));
2815 return bfd_mach_i386_iamcu
;
2818 return bfd_mach_i386_i386
;
2821 as_fatal (_("unknown architecture"));
2827 const char *hash_err
;
2829 /* Support pseudo prefixes like {disp32}. */
2830 lex_type
['{'] = LEX_BEGIN_NAME
;
2832 /* Initialize op_hash hash table. */
2833 op_hash
= hash_new ();
2836 const insn_template
*optab
;
2837 templates
*core_optab
;
2839 /* Setup for loop. */
2841 core_optab
= XNEW (templates
);
2842 core_optab
->start
= optab
;
2847 if (optab
->name
== NULL
2848 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2850 /* different name --> ship out current template list;
2851 add to hash table; & begin anew. */
2852 core_optab
->end
= optab
;
2853 hash_err
= hash_insert (op_hash
,
2855 (void *) core_optab
);
2858 as_fatal (_("can't hash %s: %s"),
2862 if (optab
->name
== NULL
)
2864 core_optab
= XNEW (templates
);
2865 core_optab
->start
= optab
;
2870 /* Initialize reg_hash hash table. */
2871 reg_hash
= hash_new ();
2873 const reg_entry
*regtab
;
2874 unsigned int regtab_size
= i386_regtab_size
;
2876 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2878 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2880 as_fatal (_("can't hash %s: %s"),
2886 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2891 for (c
= 0; c
< 256; c
++)
2896 mnemonic_chars
[c
] = c
;
2897 register_chars
[c
] = c
;
2898 operand_chars
[c
] = c
;
2900 else if (ISLOWER (c
))
2902 mnemonic_chars
[c
] = c
;
2903 register_chars
[c
] = c
;
2904 operand_chars
[c
] = c
;
2906 else if (ISUPPER (c
))
2908 mnemonic_chars
[c
] = TOLOWER (c
);
2909 register_chars
[c
] = mnemonic_chars
[c
];
2910 operand_chars
[c
] = c
;
2912 else if (c
== '{' || c
== '}')
2914 mnemonic_chars
[c
] = c
;
2915 operand_chars
[c
] = c
;
2918 if (ISALPHA (c
) || ISDIGIT (c
))
2919 identifier_chars
[c
] = c
;
2922 identifier_chars
[c
] = c
;
2923 operand_chars
[c
] = c
;
2928 identifier_chars
['@'] = '@';
2931 identifier_chars
['?'] = '?';
2932 operand_chars
['?'] = '?';
2934 digit_chars
['-'] = '-';
2935 mnemonic_chars
['_'] = '_';
2936 mnemonic_chars
['-'] = '-';
2937 mnemonic_chars
['.'] = '.';
2938 identifier_chars
['_'] = '_';
2939 identifier_chars
['.'] = '.';
2941 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2942 operand_chars
[(unsigned char) *p
] = *p
;
2945 if (flag_code
== CODE_64BIT
)
2947 #if defined (OBJ_COFF) && defined (TE_PE)
2948 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2951 x86_dwarf2_return_column
= 16;
2953 x86_cie_data_alignment
= -8;
2957 x86_dwarf2_return_column
= 8;
2958 x86_cie_data_alignment
= -4;
2963 i386_print_statistics (FILE *file
)
2965 hash_print_statistics (file
, "i386 opcode", op_hash
);
2966 hash_print_statistics (file
, "i386 register", reg_hash
);
2971 /* Debugging routines for md_assemble. */
2972 static void pte (insn_template
*);
2973 static void pt (i386_operand_type
);
2974 static void pe (expressionS
*);
2975 static void ps (symbolS
*);
2978 pi (char *line
, i386_insn
*x
)
2982 fprintf (stdout
, "%s: template ", line
);
2984 fprintf (stdout
, " address: base %s index %s scale %x\n",
2985 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2986 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2987 x
->log2_scale_factor
);
2988 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2989 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2990 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2991 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2992 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2993 (x
->rex
& REX_W
) != 0,
2994 (x
->rex
& REX_R
) != 0,
2995 (x
->rex
& REX_X
) != 0,
2996 (x
->rex
& REX_B
) != 0);
2997 for (j
= 0; j
< x
->operands
; j
++)
2999 fprintf (stdout
, " #%d: ", j
+ 1);
3001 fprintf (stdout
, "\n");
3002 if (x
->types
[j
].bitfield
.reg
3003 || x
->types
[j
].bitfield
.regmmx
3004 || x
->types
[j
].bitfield
.regsimd
3005 || x
->types
[j
].bitfield
.sreg2
3006 || x
->types
[j
].bitfield
.sreg3
3007 || x
->types
[j
].bitfield
.control
3008 || x
->types
[j
].bitfield
.debug
3009 || x
->types
[j
].bitfield
.test
)
3010 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3011 if (operand_type_check (x
->types
[j
], imm
))
3013 if (operand_type_check (x
->types
[j
], disp
))
3014 pe (x
->op
[j
].disps
);
3019 pte (insn_template
*t
)
3022 fprintf (stdout
, " %d operands ", t
->operands
);
3023 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3024 if (t
->extension_opcode
!= None
)
3025 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3026 if (t
->opcode_modifier
.d
)
3027 fprintf (stdout
, "D");
3028 if (t
->opcode_modifier
.w
)
3029 fprintf (stdout
, "W");
3030 fprintf (stdout
, "\n");
3031 for (j
= 0; j
< t
->operands
; j
++)
3033 fprintf (stdout
, " #%d type ", j
+ 1);
3034 pt (t
->operand_types
[j
]);
3035 fprintf (stdout
, "\n");
3042 fprintf (stdout
, " operation %d\n", e
->X_op
);
3043 fprintf (stdout
, " add_number %ld (%lx)\n",
3044 (long) e
->X_add_number
, (long) e
->X_add_number
);
3045 if (e
->X_add_symbol
)
3047 fprintf (stdout
, " add_symbol ");
3048 ps (e
->X_add_symbol
);
3049 fprintf (stdout
, "\n");
3053 fprintf (stdout
, " op_symbol ");
3054 ps (e
->X_op_symbol
);
3055 fprintf (stdout
, "\n");
3062 fprintf (stdout
, "%s type %s%s",
3064 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3065 segment_name (S_GET_SEGMENT (s
)));
3068 static struct type_name
3070 i386_operand_type mask
;
3073 const type_names
[] =
3075 { OPERAND_TYPE_REG8
, "r8" },
3076 { OPERAND_TYPE_REG16
, "r16" },
3077 { OPERAND_TYPE_REG32
, "r32" },
3078 { OPERAND_TYPE_REG64
, "r64" },
3079 { OPERAND_TYPE_IMM8
, "i8" },
3080 { OPERAND_TYPE_IMM8
, "i8s" },
3081 { OPERAND_TYPE_IMM16
, "i16" },
3082 { OPERAND_TYPE_IMM32
, "i32" },
3083 { OPERAND_TYPE_IMM32S
, "i32s" },
3084 { OPERAND_TYPE_IMM64
, "i64" },
3085 { OPERAND_TYPE_IMM1
, "i1" },
3086 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3087 { OPERAND_TYPE_DISP8
, "d8" },
3088 { OPERAND_TYPE_DISP16
, "d16" },
3089 { OPERAND_TYPE_DISP32
, "d32" },
3090 { OPERAND_TYPE_DISP32S
, "d32s" },
3091 { OPERAND_TYPE_DISP64
, "d64" },
3092 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3093 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3094 { OPERAND_TYPE_CONTROL
, "control reg" },
3095 { OPERAND_TYPE_TEST
, "test reg" },
3096 { OPERAND_TYPE_DEBUG
, "debug reg" },
3097 { OPERAND_TYPE_FLOATREG
, "FReg" },
3098 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3099 { OPERAND_TYPE_SREG2
, "SReg2" },
3100 { OPERAND_TYPE_SREG3
, "SReg3" },
3101 { OPERAND_TYPE_ACC
, "Acc" },
3102 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3103 { OPERAND_TYPE_REGMMX
, "rMMX" },
3104 { OPERAND_TYPE_REGXMM
, "rXMM" },
3105 { OPERAND_TYPE_REGYMM
, "rYMM" },
3106 { OPERAND_TYPE_REGZMM
, "rZMM" },
3107 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3108 { OPERAND_TYPE_ESSEG
, "es" },
3112 pt (i386_operand_type t
)
3115 i386_operand_type a
;
3117 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3119 a
= operand_type_and (t
, type_names
[j
].mask
);
3120 if (!operand_type_all_zero (&a
))
3121 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3126 #endif /* DEBUG386 */
3128 static bfd_reloc_code_real_type
3129 reloc (unsigned int size
,
3132 bfd_reloc_code_real_type other
)
3134 if (other
!= NO_RELOC
)
3136 reloc_howto_type
*rel
;
3141 case BFD_RELOC_X86_64_GOT32
:
3142 return BFD_RELOC_X86_64_GOT64
;
3144 case BFD_RELOC_X86_64_GOTPLT64
:
3145 return BFD_RELOC_X86_64_GOTPLT64
;
3147 case BFD_RELOC_X86_64_PLTOFF64
:
3148 return BFD_RELOC_X86_64_PLTOFF64
;
3150 case BFD_RELOC_X86_64_GOTPC32
:
3151 other
= BFD_RELOC_X86_64_GOTPC64
;
3153 case BFD_RELOC_X86_64_GOTPCREL
:
3154 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3156 case BFD_RELOC_X86_64_TPOFF32
:
3157 other
= BFD_RELOC_X86_64_TPOFF64
;
3159 case BFD_RELOC_X86_64_DTPOFF32
:
3160 other
= BFD_RELOC_X86_64_DTPOFF64
;
3166 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3167 if (other
== BFD_RELOC_SIZE32
)
3170 other
= BFD_RELOC_SIZE64
;
3173 as_bad (_("there are no pc-relative size relocations"));
3179 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3180 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3183 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3185 as_bad (_("unknown relocation (%u)"), other
);
3186 else if (size
!= bfd_get_reloc_size (rel
))
3187 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3188 bfd_get_reloc_size (rel
),
3190 else if (pcrel
&& !rel
->pc_relative
)
3191 as_bad (_("non-pc-relative relocation for pc-relative field"));
3192 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3194 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3196 as_bad (_("relocated field and relocation type differ in signedness"));
3205 as_bad (_("there are no unsigned pc-relative relocations"));
3208 case 1: return BFD_RELOC_8_PCREL
;
3209 case 2: return BFD_RELOC_16_PCREL
;
3210 case 4: return BFD_RELOC_32_PCREL
;
3211 case 8: return BFD_RELOC_64_PCREL
;
3213 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3220 case 4: return BFD_RELOC_X86_64_32S
;
3225 case 1: return BFD_RELOC_8
;
3226 case 2: return BFD_RELOC_16
;
3227 case 4: return BFD_RELOC_32
;
3228 case 8: return BFD_RELOC_64
;
3230 as_bad (_("cannot do %s %u byte relocation"),
3231 sign
> 0 ? "signed" : "unsigned", size
);
3237 /* Here we decide which fixups can be adjusted to make them relative to
3238 the beginning of the section instead of the symbol. Basically we need
3239 to make sure that the dynamic relocations are done correctly, so in
3240 some cases we force the original symbol to be used. */
3243 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3245 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3249 /* Don't adjust pc-relative references to merge sections in 64-bit
3251 if (use_rela_relocations
3252 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3256 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3257 and changed later by validate_fix. */
3258 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3259 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3262 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3263 for size relocations. */
3264 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3265 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3266 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3267 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3268 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3269 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3270 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3271 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3272 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3273 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3274 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3275 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3276 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3277 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3278 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3279 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3280 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3281 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3282 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3283 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3284 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3285 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3286 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3287 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3288 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3289 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3290 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3291 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3292 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3293 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3294 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3295 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3296 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3303 intel_float_operand (const char *mnemonic
)
3305 /* Note that the value returned is meaningful only for opcodes with (memory)
3306 operands, hence the code here is free to improperly handle opcodes that
3307 have no operands (for better performance and smaller code). */
3309 if (mnemonic
[0] != 'f')
3310 return 0; /* non-math */
3312 switch (mnemonic
[1])
3314 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3315 the fs segment override prefix not currently handled because no
3316 call path can make opcodes without operands get here */
3318 return 2 /* integer op */;
3320 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3321 return 3; /* fldcw/fldenv */
3324 if (mnemonic
[2] != 'o' /* fnop */)
3325 return 3; /* non-waiting control op */
3328 if (mnemonic
[2] == 's')
3329 return 3; /* frstor/frstpm */
3332 if (mnemonic
[2] == 'a')
3333 return 3; /* fsave */
3334 if (mnemonic
[2] == 't')
3336 switch (mnemonic
[3])
3338 case 'c': /* fstcw */
3339 case 'd': /* fstdw */
3340 case 'e': /* fstenv */
3341 case 's': /* fsts[gw] */
3347 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3348 return 0; /* fxsave/fxrstor are not really math ops */
3355 /* Build the VEX prefix. */
3358 build_vex_prefix (const insn_template
*t
)
3360 unsigned int register_specifier
;
3361 unsigned int implied_prefix
;
3362 unsigned int vector_length
;
3365 /* Check register specifier. */
3366 if (i
.vex
.register_specifier
)
3368 register_specifier
=
3369 ~register_number (i
.vex
.register_specifier
) & 0xf;
3370 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3373 register_specifier
= 0xf;
3375 /* Use 2-byte VEX prefix by swapping destination and source operand
3376 if there are more than 1 register operand. */
3377 if (i
.reg_operands
> 1
3378 && i
.vec_encoding
!= vex_encoding_vex3
3379 && i
.dir_encoding
== dir_encoding_default
3380 && i
.operands
== i
.reg_operands
3381 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3382 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3383 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3386 unsigned int xchg
= i
.operands
- 1;
3387 union i386_op temp_op
;
3388 i386_operand_type temp_type
;
3390 temp_type
= i
.types
[xchg
];
3391 i
.types
[xchg
] = i
.types
[0];
3392 i
.types
[0] = temp_type
;
3393 temp_op
= i
.op
[xchg
];
3394 i
.op
[xchg
] = i
.op
[0];
3397 gas_assert (i
.rm
.mode
== 3);
3401 i
.rm
.regmem
= i
.rm
.reg
;
3404 if (i
.tm
.opcode_modifier
.d
)
3405 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3406 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3407 else /* Use the next insn. */
3411 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3412 vector_length
= avxscalar
;
3413 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3419 /* Determine vector length from the last multi-length vector
3422 for (op
= t
->operands
; op
--;)
3423 if (t
->operand_types
[op
].bitfield
.xmmword
3424 && t
->operand_types
[op
].bitfield
.ymmword
3425 && i
.types
[op
].bitfield
.ymmword
)
3432 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3437 case DATA_PREFIX_OPCODE
:
3440 case REPE_PREFIX_OPCODE
:
3443 case REPNE_PREFIX_OPCODE
:
3450 /* Check the REX.W bit and VEXW. */
3451 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3452 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3453 else if (i
.tm
.opcode_modifier
.vexw
)
3454 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3456 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3458 /* Use 2-byte VEX prefix if possible. */
3460 && i
.vec_encoding
!= vex_encoding_vex3
3461 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3462 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3464 /* 2-byte VEX prefix. */
3468 i
.vex
.bytes
[0] = 0xc5;
3470 /* Check the REX.R bit. */
3471 r
= (i
.rex
& REX_R
) ? 0 : 1;
3472 i
.vex
.bytes
[1] = (r
<< 7
3473 | register_specifier
<< 3
3474 | vector_length
<< 2
3479 /* 3-byte VEX prefix. */
3484 switch (i
.tm
.opcode_modifier
.vexopcode
)
3488 i
.vex
.bytes
[0] = 0xc4;
3492 i
.vex
.bytes
[0] = 0xc4;
3496 i
.vex
.bytes
[0] = 0xc4;
3500 i
.vex
.bytes
[0] = 0x8f;
3504 i
.vex
.bytes
[0] = 0x8f;
3508 i
.vex
.bytes
[0] = 0x8f;
3514 /* The high 3 bits of the second VEX byte are 1's compliment
3515 of RXB bits from REX. */
3516 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3518 i
.vex
.bytes
[2] = (w
<< 7
3519 | register_specifier
<< 3
3520 | vector_length
<< 2
3525 static INLINE bfd_boolean
3526 is_evex_encoding (const insn_template
*t
)
3528 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3529 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3530 || t
->opcode_modifier
.staticrounding
|| t
->opcode_modifier
.sae
;
3533 static INLINE bfd_boolean
3534 is_any_vex_encoding (const insn_template
*t
)
3536 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3537 || is_evex_encoding (t
);
3540 /* Build the EVEX prefix. */
3543 build_evex_prefix (void)
3545 unsigned int register_specifier
;
3546 unsigned int implied_prefix
;
3548 rex_byte vrex_used
= 0;
3550 /* Check register specifier. */
3551 if (i
.vex
.register_specifier
)
3553 gas_assert ((i
.vrex
& REX_X
) == 0);
3555 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3556 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3557 register_specifier
+= 8;
3558 /* The upper 16 registers are encoded in the fourth byte of the
3560 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3561 i
.vex
.bytes
[3] = 0x8;
3562 register_specifier
= ~register_specifier
& 0xf;
3566 register_specifier
= 0xf;
3568 /* Encode upper 16 vector index register in the fourth byte of
3570 if (!(i
.vrex
& REX_X
))
3571 i
.vex
.bytes
[3] = 0x8;
3576 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3581 case DATA_PREFIX_OPCODE
:
3584 case REPE_PREFIX_OPCODE
:
3587 case REPNE_PREFIX_OPCODE
:
3594 /* 4 byte EVEX prefix. */
3596 i
.vex
.bytes
[0] = 0x62;
3599 switch (i
.tm
.opcode_modifier
.vexopcode
)
3615 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3617 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3619 /* The fifth bit of the second EVEX byte is 1's compliment of the
3620 REX_R bit in VREX. */
3621 if (!(i
.vrex
& REX_R
))
3622 i
.vex
.bytes
[1] |= 0x10;
3626 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3628 /* When all operands are registers, the REX_X bit in REX is not
3629 used. We reuse it to encode the upper 16 registers, which is
3630 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3631 as 1's compliment. */
3632 if ((i
.vrex
& REX_B
))
3635 i
.vex
.bytes
[1] &= ~0x40;
3639 /* EVEX instructions shouldn't need the REX prefix. */
3640 i
.vrex
&= ~vrex_used
;
3641 gas_assert (i
.vrex
== 0);
3643 /* Check the REX.W bit and VEXW. */
3644 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3645 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3646 else if (i
.tm
.opcode_modifier
.vexw
)
3647 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3649 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3651 /* Encode the U bit. */
3652 implied_prefix
|= 0x4;
3654 /* The third byte of the EVEX prefix. */
3655 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3657 /* The fourth byte of the EVEX prefix. */
3658 /* The zeroing-masking bit. */
3659 if (i
.mask
&& i
.mask
->zeroing
)
3660 i
.vex
.bytes
[3] |= 0x80;
3662 /* Don't always set the broadcast bit if there is no RC. */
3665 /* Encode the vector length. */
3666 unsigned int vec_length
;
3668 if (!i
.tm
.opcode_modifier
.evex
3669 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3673 /* Determine vector length from the last multi-length vector
3676 for (op
= i
.operands
; op
--;)
3677 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3678 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3679 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3681 if (i
.types
[op
].bitfield
.zmmword
)
3683 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3686 else if (i
.types
[op
].bitfield
.ymmword
)
3688 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3691 else if (i
.types
[op
].bitfield
.xmmword
)
3693 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3696 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3698 switch (i
.broadcast
->bytes
)
3701 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3704 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3707 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3716 if (op
>= MAX_OPERANDS
)
3720 switch (i
.tm
.opcode_modifier
.evex
)
3722 case EVEXLIG
: /* LL' is ignored */
3723 vec_length
= evexlig
<< 5;
3726 vec_length
= 0 << 5;
3729 vec_length
= 1 << 5;
3732 vec_length
= 2 << 5;
3738 i
.vex
.bytes
[3] |= vec_length
;
3739 /* Encode the broadcast bit. */
3741 i
.vex
.bytes
[3] |= 0x10;
3745 if (i
.rounding
->type
!= saeonly
)
3746 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3748 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3751 if (i
.mask
&& i
.mask
->mask
)
3752 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3756 process_immext (void)
3760 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3763 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3764 with an opcode suffix which is coded in the same place as an
3765 8-bit immediate field would be.
3766 Here we check those operands and remove them afterwards. */
3769 for (x
= 0; x
< i
.operands
; x
++)
3770 if (register_number (i
.op
[x
].regs
) != x
)
3771 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3772 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3778 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3780 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3781 suffix which is coded in the same place as an 8-bit immediate
3783 Here we check those operands and remove them afterwards. */
3786 if (i
.operands
!= 3)
3789 for (x
= 0; x
< 2; x
++)
3790 if (register_number (i
.op
[x
].regs
) != x
)
3791 goto bad_register_operand
;
3793 /* Check for third operand for mwaitx/monitorx insn. */
3794 if (register_number (i
.op
[x
].regs
)
3795 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3797 bad_register_operand
:
3798 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3799 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3806 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3807 which is coded in the same place as an 8-bit immediate field
3808 would be. Here we fake an 8-bit immediate operand from the
3809 opcode suffix stored in tm.extension_opcode.
3811 AVX instructions also use this encoding, for some of
3812 3 argument instructions. */
3814 gas_assert (i
.imm_operands
<= 1
3816 || (is_any_vex_encoding (&i
.tm
)
3817 && i
.operands
<= 4)));
3819 exp
= &im_expressions
[i
.imm_operands
++];
3820 i
.op
[i
.operands
].imms
= exp
;
3821 i
.types
[i
.operands
] = imm8
;
3823 exp
->X_op
= O_constant
;
3824 exp
->X_add_number
= i
.tm
.extension_opcode
;
3825 i
.tm
.extension_opcode
= None
;
3832 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3837 as_bad (_("invalid instruction `%s' after `%s'"),
3838 i
.tm
.name
, i
.hle_prefix
);
3841 if (i
.prefix
[LOCK_PREFIX
])
3843 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3847 case HLEPrefixRelease
:
3848 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3850 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3854 if (i
.mem_operands
== 0
3855 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3857 as_bad (_("memory destination needed for instruction `%s'"
3858 " after `xrelease'"), i
.tm
.name
);
3865 /* Try the shortest encoding by shortening operand size. */
3868 optimize_encoding (void)
3872 if (optimize_for_space
3873 && i
.reg_operands
== 1
3874 && i
.imm_operands
== 1
3875 && !i
.types
[1].bitfield
.byte
3876 && i
.op
[0].imms
->X_op
== O_constant
3877 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3878 && ((i
.tm
.base_opcode
== 0xa8
3879 && i
.tm
.extension_opcode
== None
)
3880 || (i
.tm
.base_opcode
== 0xf6
3881 && i
.tm
.extension_opcode
== 0x0)))
3884 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3886 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3887 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3889 i
.types
[1].bitfield
.byte
= 1;
3890 /* Ignore the suffix. */
3892 if (base_regnum
>= 4
3893 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3895 /* Handle SP, BP, SI and DI registers. */
3896 if (i
.types
[1].bitfield
.word
)
3898 else if (i
.types
[1].bitfield
.dword
)
3906 else if (flag_code
== CODE_64BIT
3907 && ((i
.types
[1].bitfield
.qword
3908 && i
.reg_operands
== 1
3909 && i
.imm_operands
== 1
3910 && i
.op
[0].imms
->X_op
== O_constant
3911 && ((i
.tm
.base_opcode
== 0xb0
3912 && i
.tm
.extension_opcode
== None
3913 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3914 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3915 && (((i
.tm
.base_opcode
== 0x24
3916 || i
.tm
.base_opcode
== 0xa8)
3917 && i
.tm
.extension_opcode
== None
)
3918 || (i
.tm
.base_opcode
== 0x80
3919 && i
.tm
.extension_opcode
== 0x4)
3920 || ((i
.tm
.base_opcode
== 0xf6
3921 || i
.tm
.base_opcode
== 0xc6)
3922 && i
.tm
.extension_opcode
== 0x0)))))
3923 || (i
.types
[0].bitfield
.qword
3924 && ((i
.reg_operands
== 2
3925 && i
.op
[0].regs
== i
.op
[1].regs
3926 && ((i
.tm
.base_opcode
== 0x30
3927 || i
.tm
.base_opcode
== 0x28)
3928 && i
.tm
.extension_opcode
== None
))
3929 || (i
.reg_operands
== 1
3931 && i
.tm
.base_opcode
== 0x30
3932 && i
.tm
.extension_opcode
== None
)))))
3935 andq $imm31, %r64 -> andl $imm31, %r32
3936 testq $imm31, %r64 -> testl $imm31, %r32
3937 xorq %r64, %r64 -> xorl %r32, %r32
3938 subq %r64, %r64 -> subl %r32, %r32
3939 movq $imm31, %r64 -> movl $imm31, %r32
3940 movq $imm32, %r64 -> movl $imm32, %r32
3942 i
.tm
.opcode_modifier
.norex64
= 1;
3943 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
3946 movq $imm31, %r64 -> movl $imm31, %r32
3947 movq $imm32, %r64 -> movl $imm32, %r32
3949 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3950 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3951 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3952 i
.types
[0].bitfield
.imm32
= 1;
3953 i
.types
[0].bitfield
.imm32s
= 0;
3954 i
.types
[0].bitfield
.imm64
= 0;
3955 i
.types
[1].bitfield
.dword
= 1;
3956 i
.types
[1].bitfield
.qword
= 0;
3957 if (i
.tm
.base_opcode
== 0xc6)
3960 movq $imm31, %r64 -> movl $imm31, %r32
3962 i
.tm
.base_opcode
= 0xb0;
3963 i
.tm
.extension_opcode
= None
;
3964 i
.tm
.opcode_modifier
.shortform
= 1;
3965 i
.tm
.opcode_modifier
.modrm
= 0;
3969 else if (optimize
> 1
3970 && i
.reg_operands
== 3
3971 && i
.op
[0].regs
== i
.op
[1].regs
3972 && !i
.types
[2].bitfield
.xmmword
3973 && (i
.tm
.opcode_modifier
.vex
3974 || ((!i
.mask
|| i
.mask
->zeroing
)
3976 && is_evex_encoding (&i
.tm
)
3977 && (i
.vec_encoding
!= vex_encoding_evex
3978 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
3979 || (i
.tm
.operand_types
[2].bitfield
.zmmword
3980 && i
.types
[2].bitfield
.ymmword
)
3981 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
)))
3982 && ((i
.tm
.base_opcode
== 0x55
3983 || i
.tm
.base_opcode
== 0x6655
3984 || i
.tm
.base_opcode
== 0x66df
3985 || i
.tm
.base_opcode
== 0x57
3986 || i
.tm
.base_opcode
== 0x6657
3987 || i
.tm
.base_opcode
== 0x66ef
3988 || i
.tm
.base_opcode
== 0x66f8
3989 || i
.tm
.base_opcode
== 0x66f9
3990 || i
.tm
.base_opcode
== 0x66fa
3991 || i
.tm
.base_opcode
== 0x66fb
3992 || i
.tm
.base_opcode
== 0x42
3993 || i
.tm
.base_opcode
== 0x6642
3994 || i
.tm
.base_opcode
== 0x47
3995 || i
.tm
.base_opcode
== 0x6647)
3996 && i
.tm
.extension_opcode
== None
))
3999 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4001 EVEX VOP %zmmM, %zmmM, %zmmN
4002 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4003 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4004 EVEX VOP %ymmM, %ymmM, %ymmN
4005 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4006 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4007 VEX VOP %ymmM, %ymmM, %ymmN
4008 -> VEX VOP %xmmM, %xmmM, %xmmN
4009 VOP, one of vpandn and vpxor:
4010 VEX VOP %ymmM, %ymmM, %ymmN
4011 -> VEX VOP %xmmM, %xmmM, %xmmN
4012 VOP, one of vpandnd and vpandnq:
4013 EVEX VOP %zmmM, %zmmM, %zmmN
4014 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4015 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4016 EVEX VOP %ymmM, %ymmM, %ymmN
4017 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4018 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4019 VOP, one of vpxord and vpxorq:
4020 EVEX VOP %zmmM, %zmmM, %zmmN
4021 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4022 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4023 EVEX VOP %ymmM, %ymmM, %ymmN
4024 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4025 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4026 VOP, one of kxord and kxorq:
4027 VEX VOP %kM, %kM, %kN
4028 -> VEX kxorw %kM, %kM, %kN
4029 VOP, one of kandnd and kandnq:
4030 VEX VOP %kM, %kM, %kN
4031 -> VEX kandnw %kM, %kM, %kN
4033 if (is_evex_encoding (&i
.tm
))
4035 if (i
.vec_encoding
== vex_encoding_evex
)
4036 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4039 i
.tm
.opcode_modifier
.vex
= VEX128
;
4040 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4041 i
.tm
.opcode_modifier
.evex
= 0;
4044 else if (i
.tm
.operand_types
[0].bitfield
.regmask
)
4046 i
.tm
.base_opcode
&= 0xff;
4047 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4050 i
.tm
.opcode_modifier
.vex
= VEX128
;
4052 if (i
.tm
.opcode_modifier
.vex
)
4053 for (j
= 0; j
< 3; j
++)
4055 i
.types
[j
].bitfield
.xmmword
= 1;
4056 i
.types
[j
].bitfield
.ymmword
= 0;
4061 /* This is the guts of the machine-dependent assembler. LINE points to a
4062 machine dependent instruction. This function is supposed to emit
4063 the frags/bytes it assembles to. */
4066 md_assemble (char *line
)
4069 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4070 const insn_template
*t
;
4072 /* Initialize globals. */
4073 memset (&i
, '\0', sizeof (i
));
4074 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4075 i
.reloc
[j
] = NO_RELOC
;
4076 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4077 memset (im_expressions
, '\0', sizeof (im_expressions
));
4078 save_stack_p
= save_stack
;
4080 /* First parse an instruction mnemonic & call i386_operand for the operands.
4081 We assume that the scrubber has arranged it so that line[0] is the valid
4082 start of a (possibly prefixed) mnemonic. */
4084 line
= parse_insn (line
, mnemonic
);
4087 mnem_suffix
= i
.suffix
;
4089 line
= parse_operands (line
, mnemonic
);
4091 xfree (i
.memop1_string
);
4092 i
.memop1_string
= NULL
;
4096 /* Now we've parsed the mnemonic into a set of templates, and have the
4097 operands at hand. */
4099 /* All intel opcodes have reversed operands except for "bound" and
4100 "enter". We also don't reverse intersegment "jmp" and "call"
4101 instructions with 2 immediate operands so that the immediate segment
4102 precedes the offset, as it does when in AT&T mode. */
4105 && (strcmp (mnemonic
, "bound") != 0)
4106 && (strcmp (mnemonic
, "invlpga") != 0)
4107 && !(operand_type_check (i
.types
[0], imm
)
4108 && operand_type_check (i
.types
[1], imm
)))
4111 /* The order of the immediates should be reversed
4112 for 2 immediates extrq and insertq instructions */
4113 if (i
.imm_operands
== 2
4114 && (strcmp (mnemonic
, "extrq") == 0
4115 || strcmp (mnemonic
, "insertq") == 0))
4116 swap_2_operands (0, 1);
4121 /* Don't optimize displacement for movabs since it only takes 64bit
4124 && i
.disp_encoding
!= disp_encoding_32bit
4125 && (flag_code
!= CODE_64BIT
4126 || strcmp (mnemonic
, "movabs") != 0))
4129 /* Next, we find a template that matches the given insn,
4130 making sure the overlap of the given operands types is consistent
4131 with the template operand types. */
4133 if (!(t
= match_template (mnem_suffix
)))
4136 if (sse_check
!= check_none
4137 && !i
.tm
.opcode_modifier
.noavx
4138 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4139 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4140 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4141 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4142 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4143 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4144 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4145 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4146 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4147 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4149 (sse_check
== check_warning
4151 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4154 /* Zap movzx and movsx suffix. The suffix has been set from
4155 "word ptr" or "byte ptr" on the source operand in Intel syntax
4156 or extracted from mnemonic in AT&T syntax. But we'll use
4157 the destination register to choose the suffix for encoding. */
4158 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4160 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4161 there is no suffix, the default will be byte extension. */
4162 if (i
.reg_operands
!= 2
4165 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4170 if (i
.tm
.opcode_modifier
.fwait
)
4171 if (!add_prefix (FWAIT_OPCODE
))
4174 /* Check if REP prefix is OK. */
4175 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4177 as_bad (_("invalid instruction `%s' after `%s'"),
4178 i
.tm
.name
, i
.rep_prefix
);
4182 /* Check for lock without a lockable instruction. Destination operand
4183 must be memory unless it is xchg (0x86). */
4184 if (i
.prefix
[LOCK_PREFIX
]
4185 && (!i
.tm
.opcode_modifier
.islockable
4186 || i
.mem_operands
== 0
4187 || (i
.tm
.base_opcode
!= 0x86
4188 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4190 as_bad (_("expecting lockable instruction after `lock'"));
4194 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4195 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4197 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4201 /* Check if HLE prefix is OK. */
4202 if (i
.hle_prefix
&& !check_hle ())
4205 /* Check BND prefix. */
4206 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4207 as_bad (_("expecting valid branch instruction after `bnd'"));
4209 /* Check NOTRACK prefix. */
4210 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4211 as_bad (_("expecting indirect branch instruction after `notrack'"));
4213 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4215 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4216 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4217 else if (flag_code
!= CODE_16BIT
4218 ? i
.prefix
[ADDR_PREFIX
]
4219 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4220 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4223 /* Insert BND prefix. */
4224 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4226 if (!i
.prefix
[BND_PREFIX
])
4227 add_prefix (BND_PREFIX_OPCODE
);
4228 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4230 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4231 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4235 /* Check string instruction segment overrides. */
4236 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4238 if (!check_string ())
4240 i
.disp_operands
= 0;
4243 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4244 optimize_encoding ();
4246 if (!process_suffix ())
4249 /* Update operand types. */
4250 for (j
= 0; j
< i
.operands
; j
++)
4251 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4253 /* Make still unresolved immediate matches conform to size of immediate
4254 given in i.suffix. */
4255 if (!finalize_imm ())
4258 if (i
.types
[0].bitfield
.imm1
)
4259 i
.imm_operands
= 0; /* kludge for shift insns. */
4261 /* We only need to check those implicit registers for instructions
4262 with 3 operands or less. */
4263 if (i
.operands
<= 3)
4264 for (j
= 0; j
< i
.operands
; j
++)
4265 if (i
.types
[j
].bitfield
.inoutportreg
4266 || i
.types
[j
].bitfield
.shiftcount
4267 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4270 /* ImmExt should be processed after SSE2AVX. */
4271 if (!i
.tm
.opcode_modifier
.sse2avx
4272 && i
.tm
.opcode_modifier
.immext
)
4275 /* For insns with operands there are more diddles to do to the opcode. */
4278 if (!process_operands ())
4281 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4283 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4284 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4287 if (is_any_vex_encoding (&i
.tm
))
4289 if (flag_code
== CODE_16BIT
)
4291 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4296 if (i
.tm
.opcode_modifier
.vex
)
4297 build_vex_prefix (t
);
4299 build_evex_prefix ();
4302 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4303 instructions may define INT_OPCODE as well, so avoid this corner
4304 case for those instructions that use MODRM. */
4305 if (i
.tm
.base_opcode
== INT_OPCODE
4306 && !i
.tm
.opcode_modifier
.modrm
4307 && i
.op
[0].imms
->X_add_number
== 3)
4309 i
.tm
.base_opcode
= INT3_OPCODE
;
4313 if ((i
.tm
.opcode_modifier
.jump
4314 || i
.tm
.opcode_modifier
.jumpbyte
4315 || i
.tm
.opcode_modifier
.jumpdword
)
4316 && i
.op
[0].disps
->X_op
== O_constant
)
4318 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4319 the absolute address given by the constant. Since ix86 jumps and
4320 calls are pc relative, we need to generate a reloc. */
4321 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4322 i
.op
[0].disps
->X_op
= O_symbol
;
4325 if (i
.tm
.opcode_modifier
.rex64
)
4328 /* For 8 bit registers we need an empty rex prefix. Also if the
4329 instruction already has a prefix, we need to convert old
4330 registers to new ones. */
4332 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4333 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4334 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4335 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4336 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4337 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4342 i
.rex
|= REX_OPCODE
;
4343 for (x
= 0; x
< 2; x
++)
4345 /* Look for 8 bit operand that uses old registers. */
4346 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4347 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4349 /* In case it is "hi" register, give up. */
4350 if (i
.op
[x
].regs
->reg_num
> 3)
4351 as_bad (_("can't encode register '%s%s' in an "
4352 "instruction requiring REX prefix."),
4353 register_prefix
, i
.op
[x
].regs
->reg_name
);
4355 /* Otherwise it is equivalent to the extended register.
4356 Since the encoding doesn't change this is merely
4357 cosmetic cleanup for debug output. */
4359 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4364 if (i
.rex
== 0 && i
.rex_encoding
)
4366 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4367 that uses legacy register. If it is "hi" register, don't add
4368 the REX_OPCODE byte. */
4370 for (x
= 0; x
< 2; x
++)
4371 if (i
.types
[x
].bitfield
.reg
4372 && i
.types
[x
].bitfield
.byte
4373 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4374 && i
.op
[x
].regs
->reg_num
> 3)
4376 i
.rex_encoding
= FALSE
;
4385 add_prefix (REX_OPCODE
| i
.rex
);
4387 /* We are ready to output the insn. */
4392 parse_insn (char *line
, char *mnemonic
)
4395 char *token_start
= l
;
4398 const insn_template
*t
;
4404 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4409 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4411 as_bad (_("no such instruction: `%s'"), token_start
);
4416 if (!is_space_char (*l
)
4417 && *l
!= END_OF_INSN
4419 || (*l
!= PREFIX_SEPARATOR
4422 as_bad (_("invalid character %s in mnemonic"),
4423 output_invalid (*l
));
4426 if (token_start
== l
)
4428 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4429 as_bad (_("expecting prefix; got nothing"));
4431 as_bad (_("expecting mnemonic; got nothing"));
4435 /* Look up instruction (or prefix) via hash table. */
4436 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4438 if (*l
!= END_OF_INSN
4439 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4440 && current_templates
4441 && current_templates
->start
->opcode_modifier
.isprefix
)
4443 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4445 as_bad ((flag_code
!= CODE_64BIT
4446 ? _("`%s' is only supported in 64-bit mode")
4447 : _("`%s' is not supported in 64-bit mode")),
4448 current_templates
->start
->name
);
4451 /* If we are in 16-bit mode, do not allow addr16 or data16.
4452 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4453 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4454 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4455 && flag_code
!= CODE_64BIT
4456 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4457 ^ (flag_code
== CODE_16BIT
)))
4459 as_bad (_("redundant %s prefix"),
4460 current_templates
->start
->name
);
4463 if (current_templates
->start
->opcode_length
== 0)
4465 /* Handle pseudo prefixes. */
4466 switch (current_templates
->start
->base_opcode
)
4470 i
.disp_encoding
= disp_encoding_8bit
;
4474 i
.disp_encoding
= disp_encoding_32bit
;
4478 i
.dir_encoding
= dir_encoding_load
;
4482 i
.dir_encoding
= dir_encoding_store
;
4486 i
.vec_encoding
= vex_encoding_vex2
;
4490 i
.vec_encoding
= vex_encoding_vex3
;
4494 i
.vec_encoding
= vex_encoding_evex
;
4498 i
.rex_encoding
= TRUE
;
4502 i
.no_optimize
= TRUE
;
4510 /* Add prefix, checking for repeated prefixes. */
4511 switch (add_prefix (current_templates
->start
->base_opcode
))
4516 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4517 i
.notrack_prefix
= current_templates
->start
->name
;
4520 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4521 i
.hle_prefix
= current_templates
->start
->name
;
4522 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4523 i
.bnd_prefix
= current_templates
->start
->name
;
4525 i
.rep_prefix
= current_templates
->start
->name
;
4531 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4538 if (!current_templates
)
4540 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4541 Check if we should swap operand or force 32bit displacement in
4543 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4544 i
.dir_encoding
= dir_encoding_swap
;
4545 else if (mnem_p
- 3 == dot_p
4548 i
.disp_encoding
= disp_encoding_8bit
;
4549 else if (mnem_p
- 4 == dot_p
4553 i
.disp_encoding
= disp_encoding_32bit
;
4558 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4561 if (!current_templates
)
4564 /* See if we can get a match by trimming off a suffix. */
4567 case WORD_MNEM_SUFFIX
:
4568 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4569 i
.suffix
= SHORT_MNEM_SUFFIX
;
4572 case BYTE_MNEM_SUFFIX
:
4573 case QWORD_MNEM_SUFFIX
:
4574 i
.suffix
= mnem_p
[-1];
4576 current_templates
= (const templates
*) hash_find (op_hash
,
4579 case SHORT_MNEM_SUFFIX
:
4580 case LONG_MNEM_SUFFIX
:
4583 i
.suffix
= mnem_p
[-1];
4585 current_templates
= (const templates
*) hash_find (op_hash
,
4594 if (intel_float_operand (mnemonic
) == 1)
4595 i
.suffix
= SHORT_MNEM_SUFFIX
;
4597 i
.suffix
= LONG_MNEM_SUFFIX
;
4599 current_templates
= (const templates
*) hash_find (op_hash
,
4604 if (!current_templates
)
4606 as_bad (_("no such instruction: `%s'"), token_start
);
4611 if (current_templates
->start
->opcode_modifier
.jump
4612 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4614 /* Check for a branch hint. We allow ",pt" and ",pn" for
4615 predict taken and predict not taken respectively.
4616 I'm not sure that branch hints actually do anything on loop
4617 and jcxz insns (JumpByte) for current Pentium4 chips. They
4618 may work in the future and it doesn't hurt to accept them
4620 if (l
[0] == ',' && l
[1] == 'p')
4624 if (!add_prefix (DS_PREFIX_OPCODE
))
4628 else if (l
[2] == 'n')
4630 if (!add_prefix (CS_PREFIX_OPCODE
))
4636 /* Any other comma loses. */
4639 as_bad (_("invalid character %s in mnemonic"),
4640 output_invalid (*l
));
4644 /* Check if instruction is supported on specified architecture. */
4646 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4648 supported
|= cpu_flags_match (t
);
4649 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4651 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4652 as_warn (_("use .code16 to ensure correct addressing mode"));
4658 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4659 as_bad (flag_code
== CODE_64BIT
4660 ? _("`%s' is not supported in 64-bit mode")
4661 : _("`%s' is only supported in 64-bit mode"),
4662 current_templates
->start
->name
);
4664 as_bad (_("`%s' is not supported on `%s%s'"),
4665 current_templates
->start
->name
,
4666 cpu_arch_name
? cpu_arch_name
: default_arch
,
4667 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4673 parse_operands (char *l
, const char *mnemonic
)
4677 /* 1 if operand is pending after ','. */
4678 unsigned int expecting_operand
= 0;
4680 /* Non-zero if operand parens not balanced. */
4681 unsigned int paren_not_balanced
;
4683 while (*l
!= END_OF_INSN
)
4685 /* Skip optional white space before operand. */
4686 if (is_space_char (*l
))
4688 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4690 as_bad (_("invalid character %s before operand %d"),
4691 output_invalid (*l
),
4695 token_start
= l
; /* After white space. */
4696 paren_not_balanced
= 0;
4697 while (paren_not_balanced
|| *l
!= ',')
4699 if (*l
== END_OF_INSN
)
4701 if (paren_not_balanced
)
4704 as_bad (_("unbalanced parenthesis in operand %d."),
4707 as_bad (_("unbalanced brackets in operand %d."),
4712 break; /* we are done */
4714 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4716 as_bad (_("invalid character %s in operand %d"),
4717 output_invalid (*l
),
4724 ++paren_not_balanced
;
4726 --paren_not_balanced
;
4731 ++paren_not_balanced
;
4733 --paren_not_balanced
;
4737 if (l
!= token_start
)
4738 { /* Yes, we've read in another operand. */
4739 unsigned int operand_ok
;
4740 this_operand
= i
.operands
++;
4741 if (i
.operands
> MAX_OPERANDS
)
4743 as_bad (_("spurious operands; (%d operands/instruction max)"),
4747 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4748 /* Now parse operand adding info to 'i' as we go along. */
4749 END_STRING_AND_SAVE (l
);
4751 if (i
.mem_operands
> 1)
4753 as_bad (_("too many memory references for `%s'"),
4760 i386_intel_operand (token_start
,
4761 intel_float_operand (mnemonic
));
4763 operand_ok
= i386_att_operand (token_start
);
4765 RESTORE_END_STRING (l
);
4771 if (expecting_operand
)
4773 expecting_operand_after_comma
:
4774 as_bad (_("expecting operand after ','; got nothing"));
4779 as_bad (_("expecting operand before ','; got nothing"));
4784 /* Now *l must be either ',' or END_OF_INSN. */
4787 if (*++l
== END_OF_INSN
)
4789 /* Just skip it, if it's \n complain. */
4790 goto expecting_operand_after_comma
;
4792 expecting_operand
= 1;
4799 swap_2_operands (int xchg1
, int xchg2
)
4801 union i386_op temp_op
;
4802 i386_operand_type temp_type
;
4803 unsigned int temp_flags
;
4804 enum bfd_reloc_code_real temp_reloc
;
4806 temp_type
= i
.types
[xchg2
];
4807 i
.types
[xchg2
] = i
.types
[xchg1
];
4808 i
.types
[xchg1
] = temp_type
;
4810 temp_flags
= i
.flags
[xchg2
];
4811 i
.flags
[xchg2
] = i
.flags
[xchg1
];
4812 i
.flags
[xchg1
] = temp_flags
;
4814 temp_op
= i
.op
[xchg2
];
4815 i
.op
[xchg2
] = i
.op
[xchg1
];
4816 i
.op
[xchg1
] = temp_op
;
4818 temp_reloc
= i
.reloc
[xchg2
];
4819 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4820 i
.reloc
[xchg1
] = temp_reloc
;
4824 if (i
.mask
->operand
== xchg1
)
4825 i
.mask
->operand
= xchg2
;
4826 else if (i
.mask
->operand
== xchg2
)
4827 i
.mask
->operand
= xchg1
;
4831 if (i
.broadcast
->operand
== xchg1
)
4832 i
.broadcast
->operand
= xchg2
;
4833 else if (i
.broadcast
->operand
== xchg2
)
4834 i
.broadcast
->operand
= xchg1
;
4838 if (i
.rounding
->operand
== xchg1
)
4839 i
.rounding
->operand
= xchg2
;
4840 else if (i
.rounding
->operand
== xchg2
)
4841 i
.rounding
->operand
= xchg1
;
4846 swap_operands (void)
4852 swap_2_operands (1, i
.operands
- 2);
4856 swap_2_operands (0, i
.operands
- 1);
4862 if (i
.mem_operands
== 2)
4864 const seg_entry
*temp_seg
;
4865 temp_seg
= i
.seg
[0];
4866 i
.seg
[0] = i
.seg
[1];
4867 i
.seg
[1] = temp_seg
;
4871 /* Try to ensure constant immediates are represented in the smallest
4876 char guess_suffix
= 0;
4880 guess_suffix
= i
.suffix
;
4881 else if (i
.reg_operands
)
4883 /* Figure out a suffix from the last register operand specified.
4884 We can't do this properly yet, ie. excluding InOutPortReg,
4885 but the following works for instructions with immediates.
4886 In any case, we can't set i.suffix yet. */
4887 for (op
= i
.operands
; --op
>= 0;)
4888 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
4890 guess_suffix
= BYTE_MNEM_SUFFIX
;
4893 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
4895 guess_suffix
= WORD_MNEM_SUFFIX
;
4898 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
4900 guess_suffix
= LONG_MNEM_SUFFIX
;
4903 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
4905 guess_suffix
= QWORD_MNEM_SUFFIX
;
4909 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4910 guess_suffix
= WORD_MNEM_SUFFIX
;
4912 for (op
= i
.operands
; --op
>= 0;)
4913 if (operand_type_check (i
.types
[op
], imm
))
4915 switch (i
.op
[op
].imms
->X_op
)
4918 /* If a suffix is given, this operand may be shortened. */
4919 switch (guess_suffix
)
4921 case LONG_MNEM_SUFFIX
:
4922 i
.types
[op
].bitfield
.imm32
= 1;
4923 i
.types
[op
].bitfield
.imm64
= 1;
4925 case WORD_MNEM_SUFFIX
:
4926 i
.types
[op
].bitfield
.imm16
= 1;
4927 i
.types
[op
].bitfield
.imm32
= 1;
4928 i
.types
[op
].bitfield
.imm32s
= 1;
4929 i
.types
[op
].bitfield
.imm64
= 1;
4931 case BYTE_MNEM_SUFFIX
:
4932 i
.types
[op
].bitfield
.imm8
= 1;
4933 i
.types
[op
].bitfield
.imm8s
= 1;
4934 i
.types
[op
].bitfield
.imm16
= 1;
4935 i
.types
[op
].bitfield
.imm32
= 1;
4936 i
.types
[op
].bitfield
.imm32s
= 1;
4937 i
.types
[op
].bitfield
.imm64
= 1;
4941 /* If this operand is at most 16 bits, convert it
4942 to a signed 16 bit number before trying to see
4943 whether it will fit in an even smaller size.
4944 This allows a 16-bit operand such as $0xffe0 to
4945 be recognised as within Imm8S range. */
4946 if ((i
.types
[op
].bitfield
.imm16
)
4947 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4949 i
.op
[op
].imms
->X_add_number
=
4950 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4953 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4954 if ((i
.types
[op
].bitfield
.imm32
)
4955 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4958 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4959 ^ ((offsetT
) 1 << 31))
4960 - ((offsetT
) 1 << 31));
4964 = operand_type_or (i
.types
[op
],
4965 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4967 /* We must avoid matching of Imm32 templates when 64bit
4968 only immediate is available. */
4969 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4970 i
.types
[op
].bitfield
.imm32
= 0;
4977 /* Symbols and expressions. */
4979 /* Convert symbolic operand to proper sizes for matching, but don't
4980 prevent matching a set of insns that only supports sizes other
4981 than those matching the insn suffix. */
4983 i386_operand_type mask
, allowed
;
4984 const insn_template
*t
;
4986 operand_type_set (&mask
, 0);
4987 operand_type_set (&allowed
, 0);
4989 for (t
= current_templates
->start
;
4990 t
< current_templates
->end
;
4992 allowed
= operand_type_or (allowed
,
4993 t
->operand_types
[op
]);
4994 switch (guess_suffix
)
4996 case QWORD_MNEM_SUFFIX
:
4997 mask
.bitfield
.imm64
= 1;
4998 mask
.bitfield
.imm32s
= 1;
5000 case LONG_MNEM_SUFFIX
:
5001 mask
.bitfield
.imm32
= 1;
5003 case WORD_MNEM_SUFFIX
:
5004 mask
.bitfield
.imm16
= 1;
5006 case BYTE_MNEM_SUFFIX
:
5007 mask
.bitfield
.imm8
= 1;
5012 allowed
= operand_type_and (mask
, allowed
);
5013 if (!operand_type_all_zero (&allowed
))
5014 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5021 /* Try to use the smallest displacement type too. */
5023 optimize_disp (void)
5027 for (op
= i
.operands
; --op
>= 0;)
5028 if (operand_type_check (i
.types
[op
], disp
))
5030 if (i
.op
[op
].disps
->X_op
== O_constant
)
5032 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5034 if (i
.types
[op
].bitfield
.disp16
5035 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5037 /* If this operand is at most 16 bits, convert
5038 to a signed 16 bit number and don't use 64bit
5040 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5041 i
.types
[op
].bitfield
.disp64
= 0;
5044 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5045 if (i
.types
[op
].bitfield
.disp32
5046 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5048 /* If this operand is at most 32 bits, convert
5049 to a signed 32 bit number and don't use 64bit
5051 op_disp
&= (((offsetT
) 2 << 31) - 1);
5052 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5053 i
.types
[op
].bitfield
.disp64
= 0;
5056 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5058 i
.types
[op
].bitfield
.disp8
= 0;
5059 i
.types
[op
].bitfield
.disp16
= 0;
5060 i
.types
[op
].bitfield
.disp32
= 0;
5061 i
.types
[op
].bitfield
.disp32s
= 0;
5062 i
.types
[op
].bitfield
.disp64
= 0;
5066 else if (flag_code
== CODE_64BIT
)
5068 if (fits_in_signed_long (op_disp
))
5070 i
.types
[op
].bitfield
.disp64
= 0;
5071 i
.types
[op
].bitfield
.disp32s
= 1;
5073 if (i
.prefix
[ADDR_PREFIX
]
5074 && fits_in_unsigned_long (op_disp
))
5075 i
.types
[op
].bitfield
.disp32
= 1;
5077 if ((i
.types
[op
].bitfield
.disp32
5078 || i
.types
[op
].bitfield
.disp32s
5079 || i
.types
[op
].bitfield
.disp16
)
5080 && fits_in_disp8 (op_disp
))
5081 i
.types
[op
].bitfield
.disp8
= 1;
5083 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5084 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5086 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5087 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5088 i
.types
[op
].bitfield
.disp8
= 0;
5089 i
.types
[op
].bitfield
.disp16
= 0;
5090 i
.types
[op
].bitfield
.disp32
= 0;
5091 i
.types
[op
].bitfield
.disp32s
= 0;
5092 i
.types
[op
].bitfield
.disp64
= 0;
5095 /* We only support 64bit displacement on constants. */
5096 i
.types
[op
].bitfield
.disp64
= 0;
5100 /* Return 1 if there is a match in broadcast bytes between operand
5101 GIVEN and instruction template T. */
5104 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5106 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5107 && i
.types
[given
].bitfield
.byte
)
5108 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5109 && i
.types
[given
].bitfield
.word
)
5110 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5111 && i
.types
[given
].bitfield
.dword
)
5112 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5113 && i
.types
[given
].bitfield
.qword
));
5116 /* Check if operands are valid for the instruction. */
5119 check_VecOperands (const insn_template
*t
)
5123 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5125 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5126 any one operand are implicity requiring AVX512VL support if the actual
5127 operand size is YMMword or XMMword. Since this function runs after
5128 template matching, there's no need to check for YMMword/XMMword in
5130 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5131 if (!cpu_flags_all_zero (&cpu
)
5132 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5133 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5135 for (op
= 0; op
< t
->operands
; ++op
)
5137 if (t
->operand_types
[op
].bitfield
.zmmword
5138 && (i
.types
[op
].bitfield
.ymmword
5139 || i
.types
[op
].bitfield
.xmmword
))
5141 i
.error
= unsupported
;
5147 /* Without VSIB byte, we can't have a vector register for index. */
5148 if (!t
->opcode_modifier
.vecsib
5150 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5151 || i
.index_reg
->reg_type
.bitfield
.ymmword
5152 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5154 i
.error
= unsupported_vector_index_register
;
5158 /* Check if default mask is allowed. */
5159 if (t
->opcode_modifier
.nodefmask
5160 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5162 i
.error
= no_default_mask
;
5166 /* For VSIB byte, we need a vector register for index, and all vector
5167 registers must be distinct. */
5168 if (t
->opcode_modifier
.vecsib
)
5171 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5172 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5173 || (t
->opcode_modifier
.vecsib
== VecSIB256
5174 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5175 || (t
->opcode_modifier
.vecsib
== VecSIB512
5176 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5178 i
.error
= invalid_vsib_address
;
5182 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5183 if (i
.reg_operands
== 2 && !i
.mask
)
5185 gas_assert (i
.types
[0].bitfield
.regsimd
);
5186 gas_assert (i
.types
[0].bitfield
.xmmword
5187 || i
.types
[0].bitfield
.ymmword
);
5188 gas_assert (i
.types
[2].bitfield
.regsimd
);
5189 gas_assert (i
.types
[2].bitfield
.xmmword
5190 || i
.types
[2].bitfield
.ymmword
);
5191 if (operand_check
== check_none
)
5193 if (register_number (i
.op
[0].regs
)
5194 != register_number (i
.index_reg
)
5195 && register_number (i
.op
[2].regs
)
5196 != register_number (i
.index_reg
)
5197 && register_number (i
.op
[0].regs
)
5198 != register_number (i
.op
[2].regs
))
5200 if (operand_check
== check_error
)
5202 i
.error
= invalid_vector_register_set
;
5205 as_warn (_("mask, index, and destination registers should be distinct"));
5207 else if (i
.reg_operands
== 1 && i
.mask
)
5209 if (i
.types
[1].bitfield
.regsimd
5210 && (i
.types
[1].bitfield
.xmmword
5211 || i
.types
[1].bitfield
.ymmword
5212 || i
.types
[1].bitfield
.zmmword
)
5213 && (register_number (i
.op
[1].regs
)
5214 == register_number (i
.index_reg
)))
5216 if (operand_check
== check_error
)
5218 i
.error
= invalid_vector_register_set
;
5221 if (operand_check
!= check_none
)
5222 as_warn (_("index and destination registers should be distinct"));
5227 /* Check if broadcast is supported by the instruction and is applied
5228 to the memory operand. */
5231 i386_operand_type type
, overlap
;
5233 /* Check if specified broadcast is supported in this instruction,
5234 and its broadcast bytes match the memory operand. */
5235 op
= i
.broadcast
->operand
;
5236 if (!t
->opcode_modifier
.broadcast
5237 || !(i
.flags
[op
] & Operand_Mem
)
5238 || (!i
.types
[op
].bitfield
.unspecified
5239 && !match_broadcast_size (t
, op
)))
5242 i
.error
= unsupported_broadcast
;
5246 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5247 * i
.broadcast
->type
);
5248 operand_type_set (&type
, 0);
5249 switch (i
.broadcast
->bytes
)
5252 type
.bitfield
.word
= 1;
5255 type
.bitfield
.dword
= 1;
5258 type
.bitfield
.qword
= 1;
5261 type
.bitfield
.xmmword
= 1;
5264 type
.bitfield
.ymmword
= 1;
5267 type
.bitfield
.zmmword
= 1;
5273 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5274 if (operand_type_all_zero (&overlap
))
5277 if (t
->opcode_modifier
.checkregsize
)
5281 type
.bitfield
.baseindex
= 1;
5282 for (j
= 0; j
< i
.operands
; ++j
)
5285 && !operand_type_register_match(i
.types
[j
],
5286 t
->operand_types
[j
],
5288 t
->operand_types
[op
]))
5293 /* If broadcast is supported in this instruction, we need to check if
5294 operand of one-element size isn't specified without broadcast. */
5295 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5297 /* Find memory operand. */
5298 for (op
= 0; op
< i
.operands
; op
++)
5299 if (operand_type_check (i
.types
[op
], anymem
))
5301 gas_assert (op
< i
.operands
);
5302 /* Check size of the memory operand. */
5303 if (match_broadcast_size (t
, op
))
5305 i
.error
= broadcast_needed
;
5310 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5312 /* Check if requested masking is supported. */
5315 switch (t
->opcode_modifier
.masking
)
5319 case MERGING_MASKING
:
5320 if (i
.mask
->zeroing
)
5323 i
.error
= unsupported_masking
;
5327 case DYNAMIC_MASKING
:
5328 /* Memory destinations allow only merging masking. */
5329 if (i
.mask
->zeroing
&& i
.mem_operands
)
5331 /* Find memory operand. */
5332 for (op
= 0; op
< i
.operands
; op
++)
5333 if (i
.flags
[op
] & Operand_Mem
)
5335 gas_assert (op
< i
.operands
);
5336 if (op
== i
.operands
- 1)
5338 i
.error
= unsupported_masking
;
5348 /* Check if masking is applied to dest operand. */
5349 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5351 i
.error
= mask_not_on_destination
;
5358 if ((i
.rounding
->type
!= saeonly
5359 && !t
->opcode_modifier
.staticrounding
)
5360 || (i
.rounding
->type
== saeonly
5361 && (t
->opcode_modifier
.staticrounding
5362 || !t
->opcode_modifier
.sae
)))
5364 i
.error
= unsupported_rc_sae
;
5367 /* If the instruction has several immediate operands and one of
5368 them is rounding, the rounding operand should be the last
5369 immediate operand. */
5370 if (i
.imm_operands
> 1
5371 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5373 i
.error
= rc_sae_operand_not_last_imm
;
5378 /* Check vector Disp8 operand. */
5379 if (t
->opcode_modifier
.disp8memshift
5380 && i
.disp_encoding
!= disp_encoding_32bit
)
5383 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5384 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5385 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5388 const i386_operand_type
*type
= NULL
;
5391 for (op
= 0; op
< i
.operands
; op
++)
5392 if (operand_type_check (i
.types
[op
], anymem
))
5394 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5395 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5396 else if (t
->operand_types
[op
].bitfield
.xmmword
5397 + t
->operand_types
[op
].bitfield
.ymmword
5398 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5399 type
= &t
->operand_types
[op
];
5400 else if (!i
.types
[op
].bitfield
.unspecified
)
5401 type
= &i
.types
[op
];
5403 else if (i
.types
[op
].bitfield
.regsimd
5404 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5406 if (i
.types
[op
].bitfield
.zmmword
)
5408 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5410 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5416 if (type
->bitfield
.zmmword
)
5418 else if (type
->bitfield
.ymmword
)
5420 else if (type
->bitfield
.xmmword
)
5424 /* For the check in fits_in_disp8(). */
5425 if (i
.memshift
== 0)
5429 for (op
= 0; op
< i
.operands
; op
++)
5430 if (operand_type_check (i
.types
[op
], disp
)
5431 && i
.op
[op
].disps
->X_op
== O_constant
)
5433 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5435 i
.types
[op
].bitfield
.disp8
= 1;
5438 i
.types
[op
].bitfield
.disp8
= 0;
5447 /* Check if operands are valid for the instruction. Update VEX
5451 VEX_check_operands (const insn_template
*t
)
5453 if (i
.vec_encoding
== vex_encoding_evex
)
5455 /* This instruction must be encoded with EVEX prefix. */
5456 if (!is_evex_encoding (t
))
5458 i
.error
= unsupported
;
5464 if (!t
->opcode_modifier
.vex
)
5466 /* This instruction template doesn't have VEX prefix. */
5467 if (i
.vec_encoding
!= vex_encoding_default
)
5469 i
.error
= unsupported
;
5475 /* Only check VEX_Imm4, which must be the first operand. */
5476 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5478 if (i
.op
[0].imms
->X_op
!= O_constant
5479 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5485 /* Turn off Imm8 so that update_imm won't complain. */
5486 i
.types
[0] = vec_imm4
;
5492 static const insn_template
*
5493 match_template (char mnem_suffix
)
5495 /* Points to template once we've found it. */
5496 const insn_template
*t
;
5497 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5498 i386_operand_type overlap4
;
5499 unsigned int found_reverse_match
;
5500 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5501 i386_operand_type operand_types
[MAX_OPERANDS
];
5502 int addr_prefix_disp
;
5504 unsigned int found_cpu_match
, size_match
;
5505 unsigned int check_register
;
5506 enum i386_error specific_error
= 0;
5508 #if MAX_OPERANDS != 5
5509 # error "MAX_OPERANDS must be 5."
5512 found_reverse_match
= 0;
5513 addr_prefix_disp
= -1;
5515 memset (&suffix_check
, 0, sizeof (suffix_check
));
5516 if (intel_syntax
&& i
.broadcast
)
5518 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5519 suffix_check
.no_bsuf
= 1;
5520 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5521 suffix_check
.no_wsuf
= 1;
5522 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5523 suffix_check
.no_ssuf
= 1;
5524 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5525 suffix_check
.no_lsuf
= 1;
5526 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5527 suffix_check
.no_qsuf
= 1;
5528 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5529 suffix_check
.no_ldsuf
= 1;
5531 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5534 switch (mnem_suffix
)
5536 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5537 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5538 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5539 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5540 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5544 /* Must have right number of operands. */
5545 i
.error
= number_of_operands_mismatch
;
5547 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5549 addr_prefix_disp
= -1;
5550 found_reverse_match
= 0;
5552 if (i
.operands
!= t
->operands
)
5555 /* Check processor support. */
5556 i
.error
= unsupported
;
5557 found_cpu_match
= (cpu_flags_match (t
)
5558 == CPU_FLAGS_PERFECT_MATCH
);
5559 if (!found_cpu_match
)
5562 /* Check AT&T mnemonic. */
5563 i
.error
= unsupported_with_intel_mnemonic
;
5564 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5567 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5568 i
.error
= unsupported_syntax
;
5569 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5570 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5571 || (intel64
&& t
->opcode_modifier
.amd64
)
5572 || (!intel64
&& t
->opcode_modifier
.intel64
))
5575 /* Check the suffix, except for some instructions in intel mode. */
5576 i
.error
= invalid_instruction_suffix
;
5577 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5578 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5579 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5580 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5581 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5582 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5583 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5585 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5586 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5587 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5588 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5589 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5590 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5591 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5594 size_match
= operand_size_match (t
);
5598 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5599 operand_types
[j
] = t
->operand_types
[j
];
5601 /* In general, don't allow 64-bit operands in 32-bit mode. */
5602 if (i
.suffix
== QWORD_MNEM_SUFFIX
5603 && flag_code
!= CODE_64BIT
5605 ? (!t
->opcode_modifier
.ignoresize
5606 && !t
->opcode_modifier
.broadcast
5607 && !intel_float_operand (t
->name
))
5608 : intel_float_operand (t
->name
) != 2)
5609 && ((!operand_types
[0].bitfield
.regmmx
5610 && !operand_types
[0].bitfield
.regsimd
)
5611 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5612 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5613 && (t
->base_opcode
!= 0x0fc7
5614 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5617 /* In general, don't allow 32-bit operands on pre-386. */
5618 else if (i
.suffix
== LONG_MNEM_SUFFIX
5619 && !cpu_arch_flags
.bitfield
.cpui386
5621 ? (!t
->opcode_modifier
.ignoresize
5622 && !intel_float_operand (t
->name
))
5623 : intel_float_operand (t
->name
) != 2)
5624 && ((!operand_types
[0].bitfield
.regmmx
5625 && !operand_types
[0].bitfield
.regsimd
)
5626 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5627 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5630 /* Do not verify operands when there are none. */
5634 /* We've found a match; break out of loop. */
5638 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5639 into Disp32/Disp16/Disp32 operand. */
5640 if (i
.prefix
[ADDR_PREFIX
] != 0)
5642 /* There should be only one Disp operand. */
5646 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5648 if (operand_types
[j
].bitfield
.disp16
)
5650 addr_prefix_disp
= j
;
5651 operand_types
[j
].bitfield
.disp32
= 1;
5652 operand_types
[j
].bitfield
.disp16
= 0;
5658 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5660 if (operand_types
[j
].bitfield
.disp32
)
5662 addr_prefix_disp
= j
;
5663 operand_types
[j
].bitfield
.disp32
= 0;
5664 operand_types
[j
].bitfield
.disp16
= 1;
5670 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5672 if (operand_types
[j
].bitfield
.disp64
)
5674 addr_prefix_disp
= j
;
5675 operand_types
[j
].bitfield
.disp64
= 0;
5676 operand_types
[j
].bitfield
.disp32
= 1;
5684 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5685 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5688 /* We check register size if needed. */
5689 if (t
->opcode_modifier
.checkregsize
)
5691 check_register
= (1 << t
->operands
) - 1;
5693 check_register
&= ~(1 << i
.broadcast
->operand
);
5698 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5699 switch (t
->operands
)
5702 if (!operand_type_match (overlap0
, i
.types
[0]))
5706 /* xchg %eax, %eax is a special case. It is an alias for nop
5707 only in 32bit mode and we can use opcode 0x90. In 64bit
5708 mode, we can't use 0x90 for xchg %eax, %eax since it should
5709 zero-extend %eax to %rax. */
5710 if (flag_code
== CODE_64BIT
5711 && t
->base_opcode
== 0x90
5712 && operand_type_equal (&i
.types
[0], &acc32
)
5713 && operand_type_equal (&i
.types
[1], &acc32
))
5715 /* xrelease mov %eax, <disp> is another special case. It must not
5716 match the accumulator-only encoding of mov. */
5717 if (flag_code
!= CODE_64BIT
5719 && t
->base_opcode
== 0xa0
5720 && i
.types
[0].bitfield
.acc
5721 && operand_type_check (i
.types
[1], anymem
))
5726 if (!(size_match
& MATCH_STRAIGHT
))
5728 /* Reverse direction of operands if swapping is possible in the first
5729 place (operands need to be symmetric) and
5730 - the load form is requested, and the template is a store form,
5731 - the store form is requested, and the template is a load form,
5732 - the non-default (swapped) form is requested. */
5733 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5734 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5735 && !operand_type_all_zero (&overlap1
))
5736 switch (i
.dir_encoding
)
5738 case dir_encoding_load
:
5739 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5740 || operand_types
[i
.operands
- 1].bitfield
.regmem
)
5744 case dir_encoding_store
:
5745 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5746 && !operand_types
[i
.operands
- 1].bitfield
.regmem
)
5750 case dir_encoding_swap
:
5753 case dir_encoding_default
:
5756 /* If we want store form, we skip the current load. */
5757 if ((i
.dir_encoding
== dir_encoding_store
5758 || i
.dir_encoding
== dir_encoding_swap
)
5759 && i
.mem_operands
== 0
5760 && t
->opcode_modifier
.load
)
5765 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5766 if (!operand_type_match (overlap0
, i
.types
[0])
5767 || !operand_type_match (overlap1
, i
.types
[1])
5768 || ((check_register
& 3) == 3
5769 && !operand_type_register_match (i
.types
[0],
5774 /* Check if other direction is valid ... */
5775 if (!t
->opcode_modifier
.d
)
5779 if (!(size_match
& MATCH_REVERSE
))
5781 /* Try reversing direction of operands. */
5782 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
5783 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
5784 if (!operand_type_match (overlap0
, i
.types
[0])
5785 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
5787 && !operand_type_register_match (i
.types
[0],
5788 operand_types
[i
.operands
- 1],
5789 i
.types
[i
.operands
- 1],
5792 /* Does not match either direction. */
5795 /* found_reverse_match holds which of D or FloatR
5797 if (!t
->opcode_modifier
.d
)
5798 found_reverse_match
= 0;
5799 else if (operand_types
[0].bitfield
.tbyte
)
5800 found_reverse_match
= Opcode_FloatD
;
5801 else if (operand_types
[0].bitfield
.xmmword
5802 || operand_types
[i
.operands
- 1].bitfield
.xmmword
5803 || operand_types
[0].bitfield
.regmmx
5804 || operand_types
[i
.operands
- 1].bitfield
.regmmx
5805 || is_any_vex_encoding(t
))
5806 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
5807 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
5809 found_reverse_match
= Opcode_D
;
5810 if (t
->opcode_modifier
.floatr
)
5811 found_reverse_match
|= Opcode_FloatR
;
5815 /* Found a forward 2 operand match here. */
5816 switch (t
->operands
)
5819 overlap4
= operand_type_and (i
.types
[4],
5823 overlap3
= operand_type_and (i
.types
[3],
5827 overlap2
= operand_type_and (i
.types
[2],
5832 switch (t
->operands
)
5835 if (!operand_type_match (overlap4
, i
.types
[4])
5836 || !operand_type_register_match (i
.types
[3],
5843 if (!operand_type_match (overlap3
, i
.types
[3])
5844 || ((check_register
& 0xa) == 0xa
5845 && !operand_type_register_match (i
.types
[1],
5849 || ((check_register
& 0xc) == 0xc
5850 && !operand_type_register_match (i
.types
[2],
5857 /* Here we make use of the fact that there are no
5858 reverse match 3 operand instructions. */
5859 if (!operand_type_match (overlap2
, i
.types
[2])
5860 || ((check_register
& 5) == 5
5861 && !operand_type_register_match (i
.types
[0],
5865 || ((check_register
& 6) == 6
5866 && !operand_type_register_match (i
.types
[1],
5874 /* Found either forward/reverse 2, 3 or 4 operand match here:
5875 slip through to break. */
5877 if (!found_cpu_match
)
5880 /* Check if vector and VEX operands are valid. */
5881 if (check_VecOperands (t
) || VEX_check_operands (t
))
5883 specific_error
= i
.error
;
5887 /* We've found a match; break out of loop. */
5891 if (t
== current_templates
->end
)
5893 /* We found no match. */
5894 const char *err_msg
;
5895 switch (specific_error
? specific_error
: i
.error
)
5899 case operand_size_mismatch
:
5900 err_msg
= _("operand size mismatch");
5902 case operand_type_mismatch
:
5903 err_msg
= _("operand type mismatch");
5905 case register_type_mismatch
:
5906 err_msg
= _("register type mismatch");
5908 case number_of_operands_mismatch
:
5909 err_msg
= _("number of operands mismatch");
5911 case invalid_instruction_suffix
:
5912 err_msg
= _("invalid instruction suffix");
5915 err_msg
= _("constant doesn't fit in 4 bits");
5917 case unsupported_with_intel_mnemonic
:
5918 err_msg
= _("unsupported with Intel mnemonic");
5920 case unsupported_syntax
:
5921 err_msg
= _("unsupported syntax");
5924 as_bad (_("unsupported instruction `%s'"),
5925 current_templates
->start
->name
);
5927 case invalid_vsib_address
:
5928 err_msg
= _("invalid VSIB address");
5930 case invalid_vector_register_set
:
5931 err_msg
= _("mask, index, and destination registers must be distinct");
5933 case unsupported_vector_index_register
:
5934 err_msg
= _("unsupported vector index register");
5936 case unsupported_broadcast
:
5937 err_msg
= _("unsupported broadcast");
5939 case broadcast_needed
:
5940 err_msg
= _("broadcast is needed for operand of such type");
5942 case unsupported_masking
:
5943 err_msg
= _("unsupported masking");
5945 case mask_not_on_destination
:
5946 err_msg
= _("mask not on destination operand");
5948 case no_default_mask
:
5949 err_msg
= _("default mask isn't allowed");
5951 case unsupported_rc_sae
:
5952 err_msg
= _("unsupported static rounding/sae");
5954 case rc_sae_operand_not_last_imm
:
5956 err_msg
= _("RC/SAE operand must precede immediate operands");
5958 err_msg
= _("RC/SAE operand must follow immediate operands");
5960 case invalid_register_operand
:
5961 err_msg
= _("invalid register operand");
5964 as_bad (_("%s for `%s'"), err_msg
,
5965 current_templates
->start
->name
);
5969 if (!quiet_warnings
)
5972 && (i
.types
[0].bitfield
.jumpabsolute
5973 != operand_types
[0].bitfield
.jumpabsolute
))
5975 as_warn (_("indirect %s without `*'"), t
->name
);
5978 if (t
->opcode_modifier
.isprefix
5979 && t
->opcode_modifier
.ignoresize
)
5981 /* Warn them that a data or address size prefix doesn't
5982 affect assembly of the next line of code. */
5983 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5987 /* Copy the template we found. */
5990 if (addr_prefix_disp
!= -1)
5991 i
.tm
.operand_types
[addr_prefix_disp
]
5992 = operand_types
[addr_prefix_disp
];
5994 if (found_reverse_match
)
5996 /* If we found a reverse match we must alter the opcode
5997 direction bit. found_reverse_match holds bits to change
5998 (different for int & float insns). */
6000 i
.tm
.base_opcode
^= found_reverse_match
;
6002 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6003 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6012 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
6013 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
6015 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
6017 as_bad (_("`%s' operand %d must use `%ses' segment"),
6023 /* There's only ever one segment override allowed per instruction.
6024 This instruction possibly has a legal segment override on the
6025 second operand, so copy the segment to where non-string
6026 instructions store it, allowing common code. */
6027 i
.seg
[0] = i
.seg
[1];
6029 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
6031 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
6033 as_bad (_("`%s' operand %d must use `%ses' segment"),
6044 process_suffix (void)
6046 /* If matched instruction specifies an explicit instruction mnemonic
6048 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6049 i
.suffix
= WORD_MNEM_SUFFIX
;
6050 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6051 i
.suffix
= LONG_MNEM_SUFFIX
;
6052 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6053 i
.suffix
= QWORD_MNEM_SUFFIX
;
6054 else if (i
.reg_operands
)
6056 /* If there's no instruction mnemonic suffix we try to invent one
6057 based on register operands. */
6060 /* We take i.suffix from the last register operand specified,
6061 Destination register type is more significant than source
6062 register type. crc32 in SSE4.2 prefers source register
6064 if (i
.tm
.base_opcode
== 0xf20f38f0 && i
.types
[0].bitfield
.reg
)
6066 if (i
.types
[0].bitfield
.byte
)
6067 i
.suffix
= BYTE_MNEM_SUFFIX
;
6068 else if (i
.types
[0].bitfield
.word
)
6069 i
.suffix
= WORD_MNEM_SUFFIX
;
6070 else if (i
.types
[0].bitfield
.dword
)
6071 i
.suffix
= LONG_MNEM_SUFFIX
;
6072 else if (i
.types
[0].bitfield
.qword
)
6073 i
.suffix
= QWORD_MNEM_SUFFIX
;
6080 if (i
.tm
.base_opcode
== 0xf20f38f0)
6082 /* We have to know the operand size for crc32. */
6083 as_bad (_("ambiguous memory operand size for `%s`"),
6088 for (op
= i
.operands
; --op
>= 0;)
6089 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
6090 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
6092 if (!i
.types
[op
].bitfield
.reg
)
6094 if (i
.types
[op
].bitfield
.byte
)
6095 i
.suffix
= BYTE_MNEM_SUFFIX
;
6096 else if (i
.types
[op
].bitfield
.word
)
6097 i
.suffix
= WORD_MNEM_SUFFIX
;
6098 else if (i
.types
[op
].bitfield
.dword
)
6099 i
.suffix
= LONG_MNEM_SUFFIX
;
6100 else if (i
.types
[op
].bitfield
.qword
)
6101 i
.suffix
= QWORD_MNEM_SUFFIX
;
6108 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6111 && i
.tm
.opcode_modifier
.ignoresize
6112 && i
.tm
.opcode_modifier
.no_bsuf
)
6114 else if (!check_byte_reg ())
6117 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6120 && i
.tm
.opcode_modifier
.ignoresize
6121 && i
.tm
.opcode_modifier
.no_lsuf
6122 && !i
.tm
.opcode_modifier
.todword
6123 && !i
.tm
.opcode_modifier
.toqword
)
6125 else if (!check_long_reg ())
6128 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6131 && i
.tm
.opcode_modifier
.ignoresize
6132 && i
.tm
.opcode_modifier
.no_qsuf
6133 && !i
.tm
.opcode_modifier
.todword
6134 && !i
.tm
.opcode_modifier
.toqword
)
6136 else if (!check_qword_reg ())
6139 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6142 && i
.tm
.opcode_modifier
.ignoresize
6143 && i
.tm
.opcode_modifier
.no_wsuf
)
6145 else if (!check_word_reg ())
6148 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6149 /* Do nothing if the instruction is going to ignore the prefix. */
6154 else if (i
.tm
.opcode_modifier
.defaultsize
6156 /* exclude fldenv/frstor/fsave/fstenv */
6157 && i
.tm
.opcode_modifier
.no_ssuf
)
6159 i
.suffix
= stackop_size
;
6161 else if (intel_syntax
6163 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
6164 || i
.tm
.opcode_modifier
.jumpbyte
6165 || i
.tm
.opcode_modifier
.jumpintersegment
6166 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6167 && i
.tm
.extension_opcode
<= 3)))
6172 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6174 i
.suffix
= QWORD_MNEM_SUFFIX
;
6179 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6180 i
.suffix
= LONG_MNEM_SUFFIX
;
6183 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6184 i
.suffix
= WORD_MNEM_SUFFIX
;
6193 if (i
.tm
.opcode_modifier
.w
)
6195 as_bad (_("no instruction mnemonic suffix given and "
6196 "no register operands; can't size instruction"));
6202 unsigned int suffixes
;
6204 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6205 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6207 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6209 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6211 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6213 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6216 /* There are more than suffix matches. */
6217 if (i
.tm
.opcode_modifier
.w
6218 || ((suffixes
& (suffixes
- 1))
6219 && !i
.tm
.opcode_modifier
.defaultsize
6220 && !i
.tm
.opcode_modifier
.ignoresize
))
6222 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6228 /* Change the opcode based on the operand size given by i.suffix. */
6231 /* Size floating point instruction. */
6232 case LONG_MNEM_SUFFIX
:
6233 if (i
.tm
.opcode_modifier
.floatmf
)
6235 i
.tm
.base_opcode
^= 4;
6239 case WORD_MNEM_SUFFIX
:
6240 case QWORD_MNEM_SUFFIX
:
6241 /* It's not a byte, select word/dword operation. */
6242 if (i
.tm
.opcode_modifier
.w
)
6244 if (i
.tm
.opcode_modifier
.shortform
)
6245 i
.tm
.base_opcode
|= 8;
6247 i
.tm
.base_opcode
|= 1;
6250 case SHORT_MNEM_SUFFIX
:
6251 /* Now select between word & dword operations via the operand
6252 size prefix, except for instructions that will ignore this
6254 if (i
.reg_operands
> 0
6255 && i
.types
[0].bitfield
.reg
6256 && i
.tm
.opcode_modifier
.addrprefixopreg
6257 && (i
.tm
.opcode_modifier
.immext
6258 || i
.operands
== 1))
6260 /* The address size override prefix changes the size of the
6262 if ((flag_code
== CODE_32BIT
6263 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6264 || (flag_code
!= CODE_32BIT
6265 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6266 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6269 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6270 && !i
.tm
.opcode_modifier
.ignoresize
6271 && !i
.tm
.opcode_modifier
.floatmf
6272 && !i
.tm
.opcode_modifier
.vex
6273 && !i
.tm
.opcode_modifier
.vexopcode
6274 && !is_evex_encoding (&i
.tm
)
6275 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6276 || (flag_code
== CODE_64BIT
6277 && i
.tm
.opcode_modifier
.jumpbyte
)))
6279 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6281 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6282 prefix
= ADDR_PREFIX_OPCODE
;
6284 if (!add_prefix (prefix
))
6288 /* Set mode64 for an operand. */
6289 if (i
.suffix
== QWORD_MNEM_SUFFIX
6290 && flag_code
== CODE_64BIT
6291 && !i
.tm
.opcode_modifier
.norex64
6292 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6294 && ! (i
.operands
== 2
6295 && i
.tm
.base_opcode
== 0x90
6296 && i
.tm
.extension_opcode
== None
6297 && operand_type_equal (&i
.types
[0], &acc64
)
6298 && operand_type_equal (&i
.types
[1], &acc64
)))
6304 if (i
.reg_operands
!= 0
6306 && i
.tm
.opcode_modifier
.addrprefixopreg
6307 && !i
.tm
.opcode_modifier
.immext
)
6309 /* Check invalid register operand when the address size override
6310 prefix changes the size of register operands. */
6312 enum { need_word
, need_dword
, need_qword
} need
;
6314 if (flag_code
== CODE_32BIT
)
6315 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6318 if (i
.prefix
[ADDR_PREFIX
])
6321 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6324 for (op
= 0; op
< i
.operands
; op
++)
6325 if (i
.types
[op
].bitfield
.reg
6326 && ((need
== need_word
6327 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6328 || (need
== need_dword
6329 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6330 || (need
== need_qword
6331 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6333 as_bad (_("invalid register operand size for `%s'"),
6343 check_byte_reg (void)
6347 for (op
= i
.operands
; --op
>= 0;)
6349 /* Skip non-register operands. */
6350 if (!i
.types
[op
].bitfield
.reg
)
6353 /* If this is an eight bit register, it's OK. If it's the 16 or
6354 32 bit version of an eight bit register, we will just use the
6355 low portion, and that's OK too. */
6356 if (i
.types
[op
].bitfield
.byte
)
6359 /* I/O port address operands are OK too. */
6360 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6363 /* crc32 doesn't generate this warning. */
6364 if (i
.tm
.base_opcode
== 0xf20f38f0)
6367 if ((i
.types
[op
].bitfield
.word
6368 || i
.types
[op
].bitfield
.dword
6369 || i
.types
[op
].bitfield
.qword
)
6370 && i
.op
[op
].regs
->reg_num
< 4
6371 /* Prohibit these changes in 64bit mode, since the lowering
6372 would be more complicated. */
6373 && flag_code
!= CODE_64BIT
)
6375 #if REGISTER_WARNINGS
6376 if (!quiet_warnings
)
6377 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6379 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6380 ? REGNAM_AL
- REGNAM_AX
6381 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6383 i
.op
[op
].regs
->reg_name
,
6388 /* Any other register is bad. */
6389 if (i
.types
[op
].bitfield
.reg
6390 || i
.types
[op
].bitfield
.regmmx
6391 || i
.types
[op
].bitfield
.regsimd
6392 || i
.types
[op
].bitfield
.sreg2
6393 || i
.types
[op
].bitfield
.sreg3
6394 || i
.types
[op
].bitfield
.control
6395 || i
.types
[op
].bitfield
.debug
6396 || i
.types
[op
].bitfield
.test
)
6398 as_bad (_("`%s%s' not allowed with `%s%c'"),
6400 i
.op
[op
].regs
->reg_name
,
6410 check_long_reg (void)
6414 for (op
= i
.operands
; --op
>= 0;)
6415 /* Skip non-register operands. */
6416 if (!i
.types
[op
].bitfield
.reg
)
6418 /* Reject eight bit registers, except where the template requires
6419 them. (eg. movzb) */
6420 else if (i
.types
[op
].bitfield
.byte
6421 && (i
.tm
.operand_types
[op
].bitfield
.reg
6422 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6423 && (i
.tm
.operand_types
[op
].bitfield
.word
6424 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6426 as_bad (_("`%s%s' not allowed with `%s%c'"),
6428 i
.op
[op
].regs
->reg_name
,
6433 /* Warn if the e prefix on a general reg is missing. */
6434 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6435 && i
.types
[op
].bitfield
.word
6436 && (i
.tm
.operand_types
[op
].bitfield
.reg
6437 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6438 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6440 /* Prohibit these changes in the 64bit mode, since the
6441 lowering is more complicated. */
6442 if (flag_code
== CODE_64BIT
)
6444 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6445 register_prefix
, i
.op
[op
].regs
->reg_name
,
6449 #if REGISTER_WARNINGS
6450 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6452 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6453 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6456 /* Warn if the r prefix on a general reg is present. */
6457 else if (i
.types
[op
].bitfield
.qword
6458 && (i
.tm
.operand_types
[op
].bitfield
.reg
6459 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6460 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6463 && i
.tm
.opcode_modifier
.toqword
6464 && !i
.types
[0].bitfield
.regsimd
)
6466 /* Convert to QWORD. We want REX byte. */
6467 i
.suffix
= QWORD_MNEM_SUFFIX
;
6471 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6472 register_prefix
, i
.op
[op
].regs
->reg_name
,
6481 check_qword_reg (void)
6485 for (op
= i
.operands
; --op
>= 0; )
6486 /* Skip non-register operands. */
6487 if (!i
.types
[op
].bitfield
.reg
)
6489 /* Reject eight bit registers, except where the template requires
6490 them. (eg. movzb) */
6491 else if (i
.types
[op
].bitfield
.byte
6492 && (i
.tm
.operand_types
[op
].bitfield
.reg
6493 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6494 && (i
.tm
.operand_types
[op
].bitfield
.word
6495 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6497 as_bad (_("`%s%s' not allowed with `%s%c'"),
6499 i
.op
[op
].regs
->reg_name
,
6504 /* Warn if the r prefix on a general reg is missing. */
6505 else if ((i
.types
[op
].bitfield
.word
6506 || i
.types
[op
].bitfield
.dword
)
6507 && (i
.tm
.operand_types
[op
].bitfield
.reg
6508 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6509 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6511 /* Prohibit these changes in the 64bit mode, since the
6512 lowering is more complicated. */
6514 && i
.tm
.opcode_modifier
.todword
6515 && !i
.types
[0].bitfield
.regsimd
)
6517 /* Convert to DWORD. We don't want REX byte. */
6518 i
.suffix
= LONG_MNEM_SUFFIX
;
6522 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6523 register_prefix
, i
.op
[op
].regs
->reg_name
,
6532 check_word_reg (void)
6535 for (op
= i
.operands
; --op
>= 0;)
6536 /* Skip non-register operands. */
6537 if (!i
.types
[op
].bitfield
.reg
)
6539 /* Reject eight bit registers, except where the template requires
6540 them. (eg. movzb) */
6541 else if (i
.types
[op
].bitfield
.byte
6542 && (i
.tm
.operand_types
[op
].bitfield
.reg
6543 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6544 && (i
.tm
.operand_types
[op
].bitfield
.word
6545 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6547 as_bad (_("`%s%s' not allowed with `%s%c'"),
6549 i
.op
[op
].regs
->reg_name
,
6554 /* Warn if the e or r prefix on a general reg is present. */
6555 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6556 && (i
.types
[op
].bitfield
.dword
6557 || i
.types
[op
].bitfield
.qword
)
6558 && (i
.tm
.operand_types
[op
].bitfield
.reg
6559 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6560 && i
.tm
.operand_types
[op
].bitfield
.word
)
6562 /* Prohibit these changes in the 64bit mode, since the
6563 lowering is more complicated. */
6564 if (flag_code
== CODE_64BIT
)
6566 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6567 register_prefix
, i
.op
[op
].regs
->reg_name
,
6571 #if REGISTER_WARNINGS
6572 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6574 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6575 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6582 update_imm (unsigned int j
)
6584 i386_operand_type overlap
= i
.types
[j
];
6585 if ((overlap
.bitfield
.imm8
6586 || overlap
.bitfield
.imm8s
6587 || overlap
.bitfield
.imm16
6588 || overlap
.bitfield
.imm32
6589 || overlap
.bitfield
.imm32s
6590 || overlap
.bitfield
.imm64
)
6591 && !operand_type_equal (&overlap
, &imm8
)
6592 && !operand_type_equal (&overlap
, &imm8s
)
6593 && !operand_type_equal (&overlap
, &imm16
)
6594 && !operand_type_equal (&overlap
, &imm32
)
6595 && !operand_type_equal (&overlap
, &imm32s
)
6596 && !operand_type_equal (&overlap
, &imm64
))
6600 i386_operand_type temp
;
6602 operand_type_set (&temp
, 0);
6603 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6605 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6606 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6608 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6609 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6610 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6612 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6613 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6616 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6619 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6620 || operand_type_equal (&overlap
, &imm16_32
)
6621 || operand_type_equal (&overlap
, &imm16_32s
))
6623 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6628 if (!operand_type_equal (&overlap
, &imm8
)
6629 && !operand_type_equal (&overlap
, &imm8s
)
6630 && !operand_type_equal (&overlap
, &imm16
)
6631 && !operand_type_equal (&overlap
, &imm32
)
6632 && !operand_type_equal (&overlap
, &imm32s
)
6633 && !operand_type_equal (&overlap
, &imm64
))
6635 as_bad (_("no instruction mnemonic suffix given; "
6636 "can't determine immediate size"));
6640 i
.types
[j
] = overlap
;
6650 /* Update the first 2 immediate operands. */
6651 n
= i
.operands
> 2 ? 2 : i
.operands
;
6654 for (j
= 0; j
< n
; j
++)
6655 if (update_imm (j
) == 0)
6658 /* The 3rd operand can't be immediate operand. */
6659 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6666 process_operands (void)
6668 /* Default segment register this instruction will use for memory
6669 accesses. 0 means unknown. This is only for optimizing out
6670 unnecessary segment overrides. */
6671 const seg_entry
*default_seg
= 0;
6673 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6675 unsigned int dupl
= i
.operands
;
6676 unsigned int dest
= dupl
- 1;
6679 /* The destination must be an xmm register. */
6680 gas_assert (i
.reg_operands
6681 && MAX_OPERANDS
> dupl
6682 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6684 if (i
.tm
.operand_types
[0].bitfield
.acc
6685 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6687 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6689 /* Keep xmm0 for instructions with VEX prefix and 3
6691 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6692 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6697 /* We remove the first xmm0 and keep the number of
6698 operands unchanged, which in fact duplicates the
6700 for (j
= 1; j
< i
.operands
; j
++)
6702 i
.op
[j
- 1] = i
.op
[j
];
6703 i
.types
[j
- 1] = i
.types
[j
];
6704 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6708 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6710 gas_assert ((MAX_OPERANDS
- 1) > dupl
6711 && (i
.tm
.opcode_modifier
.vexsources
6714 /* Add the implicit xmm0 for instructions with VEX prefix
6716 for (j
= i
.operands
; j
> 0; j
--)
6718 i
.op
[j
] = i
.op
[j
- 1];
6719 i
.types
[j
] = i
.types
[j
- 1];
6720 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6723 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6724 i
.types
[0] = regxmm
;
6725 i
.tm
.operand_types
[0] = regxmm
;
6728 i
.reg_operands
+= 2;
6733 i
.op
[dupl
] = i
.op
[dest
];
6734 i
.types
[dupl
] = i
.types
[dest
];
6735 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6744 i
.op
[dupl
] = i
.op
[dest
];
6745 i
.types
[dupl
] = i
.types
[dest
];
6746 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6749 if (i
.tm
.opcode_modifier
.immext
)
6752 else if (i
.tm
.operand_types
[0].bitfield
.acc
6753 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6757 for (j
= 1; j
< i
.operands
; j
++)
6759 i
.op
[j
- 1] = i
.op
[j
];
6760 i
.types
[j
- 1] = i
.types
[j
];
6762 /* We need to adjust fields in i.tm since they are used by
6763 build_modrm_byte. */
6764 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6771 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6773 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6775 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6776 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6777 regnum
= register_number (i
.op
[1].regs
);
6778 first_reg_in_group
= regnum
& ~3;
6779 last_reg_in_group
= first_reg_in_group
+ 3;
6780 if (regnum
!= first_reg_in_group
)
6781 as_warn (_("source register `%s%s' implicitly denotes"
6782 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6783 register_prefix
, i
.op
[1].regs
->reg_name
,
6784 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6785 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6788 else if (i
.tm
.opcode_modifier
.regkludge
)
6790 /* The imul $imm, %reg instruction is converted into
6791 imul $imm, %reg, %reg, and the clr %reg instruction
6792 is converted into xor %reg, %reg. */
6794 unsigned int first_reg_op
;
6796 if (operand_type_check (i
.types
[0], reg
))
6800 /* Pretend we saw the extra register operand. */
6801 gas_assert (i
.reg_operands
== 1
6802 && i
.op
[first_reg_op
+ 1].regs
== 0);
6803 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6804 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6809 if (i
.tm
.opcode_modifier
.shortform
)
6811 if (i
.types
[0].bitfield
.sreg2
6812 || i
.types
[0].bitfield
.sreg3
)
6814 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6815 && i
.op
[0].regs
->reg_num
== 1)
6817 as_bad (_("you can't `pop %scs'"), register_prefix
);
6820 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6821 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6826 /* The register or float register operand is in operand
6830 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
6831 || operand_type_check (i
.types
[0], reg
))
6835 /* Register goes in low 3 bits of opcode. */
6836 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6837 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6839 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6841 /* Warn about some common errors, but press on regardless.
6842 The first case can be generated by gcc (<= 2.8.1). */
6843 if (i
.operands
== 2)
6845 /* Reversed arguments on faddp, fsubp, etc. */
6846 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6847 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6848 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6852 /* Extraneous `l' suffix on fp insn. */
6853 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6854 register_prefix
, i
.op
[0].regs
->reg_name
);
6859 else if (i
.tm
.opcode_modifier
.modrm
)
6861 /* The opcode is completed (modulo i.tm.extension_opcode which
6862 must be put into the modrm byte). Now, we make the modrm and
6863 index base bytes based on all the info we've collected. */
6865 default_seg
= build_modrm_byte ();
6867 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6871 else if (i
.tm
.opcode_modifier
.isstring
)
6873 /* For the string instructions that allow a segment override
6874 on one of their operands, the default segment is ds. */
6878 if (i
.tm
.base_opcode
== 0x8d /* lea */
6881 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6883 /* If a segment was explicitly specified, and the specified segment
6884 is not the default, use an opcode prefix to select it. If we
6885 never figured out what the default segment is, then default_seg
6886 will be zero at this point, and the specified segment prefix will
6888 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6890 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6896 static const seg_entry
*
6897 build_modrm_byte (void)
6899 const seg_entry
*default_seg
= 0;
6900 unsigned int source
, dest
;
6903 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6906 unsigned int nds
, reg_slot
;
6909 dest
= i
.operands
- 1;
6912 /* There are 2 kinds of instructions:
6913 1. 5 operands: 4 register operands or 3 register operands
6914 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6915 VexW0 or VexW1. The destination must be either XMM, YMM or
6917 2. 4 operands: 4 register operands or 3 register operands
6918 plus 1 memory operand, with VexXDS. */
6919 gas_assert ((i
.reg_operands
== 4
6920 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6921 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6922 && i
.tm
.opcode_modifier
.vexw
6923 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
6925 /* If VexW1 is set, the first non-immediate operand is the source and
6926 the second non-immediate one is encoded in the immediate operand. */
6927 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6929 source
= i
.imm_operands
;
6930 reg_slot
= i
.imm_operands
+ 1;
6934 source
= i
.imm_operands
+ 1;
6935 reg_slot
= i
.imm_operands
;
6938 if (i
.imm_operands
== 0)
6940 /* When there is no immediate operand, generate an 8bit
6941 immediate operand to encode the first operand. */
6942 exp
= &im_expressions
[i
.imm_operands
++];
6943 i
.op
[i
.operands
].imms
= exp
;
6944 i
.types
[i
.operands
] = imm8
;
6947 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6948 exp
->X_op
= O_constant
;
6949 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6950 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6954 unsigned int imm_slot
;
6956 gas_assert (i
.imm_operands
== 1 && i
.types
[0].bitfield
.vec_imm4
);
6958 if (i
.tm
.opcode_modifier
.immext
)
6960 /* When ImmExt is set, the immediate byte is the last
6962 imm_slot
= i
.operands
- 1;
6970 /* Turn on Imm8 so that output_imm will generate it. */
6971 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6974 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6975 i
.op
[imm_slot
].imms
->X_add_number
6976 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6977 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6980 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
6981 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6986 /* i.reg_operands MUST be the number of real register operands;
6987 implicit registers do not count. If there are 3 register
6988 operands, it must be a instruction with VexNDS. For a
6989 instruction with VexNDD, the destination register is encoded
6990 in VEX prefix. If there are 4 register operands, it must be
6991 a instruction with VEX prefix and 3 sources. */
6992 if (i
.mem_operands
== 0
6993 && ((i
.reg_operands
== 2
6994 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6995 || (i
.reg_operands
== 3
6996 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6997 || (i
.reg_operands
== 4 && vex_3_sources
)))
7005 /* When there are 3 operands, one of them may be immediate,
7006 which may be the first or the last operand. Otherwise,
7007 the first operand must be shift count register (cl) or it
7008 is an instruction with VexNDS. */
7009 gas_assert (i
.imm_operands
== 1
7010 || (i
.imm_operands
== 0
7011 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7012 || i
.types
[0].bitfield
.shiftcount
)));
7013 if (operand_type_check (i
.types
[0], imm
)
7014 || i
.types
[0].bitfield
.shiftcount
)
7020 /* When there are 4 operands, the first two must be 8bit
7021 immediate operands. The source operand will be the 3rd
7024 For instructions with VexNDS, if the first operand
7025 an imm8, the source operand is the 2nd one. If the last
7026 operand is imm8, the source operand is the first one. */
7027 gas_assert ((i
.imm_operands
== 2
7028 && i
.types
[0].bitfield
.imm8
7029 && i
.types
[1].bitfield
.imm8
)
7030 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7031 && i
.imm_operands
== 1
7032 && (i
.types
[0].bitfield
.imm8
7033 || i
.types
[i
.operands
- 1].bitfield
.imm8
7035 if (i
.imm_operands
== 2)
7039 if (i
.types
[0].bitfield
.imm8
)
7046 if (is_evex_encoding (&i
.tm
))
7048 /* For EVEX instructions, when there are 5 operands, the
7049 first one must be immediate operand. If the second one
7050 is immediate operand, the source operand is the 3th
7051 one. If the last one is immediate operand, the source
7052 operand is the 2nd one. */
7053 gas_assert (i
.imm_operands
== 2
7054 && i
.tm
.opcode_modifier
.sae
7055 && operand_type_check (i
.types
[0], imm
));
7056 if (operand_type_check (i
.types
[1], imm
))
7058 else if (operand_type_check (i
.types
[4], imm
))
7072 /* RC/SAE operand could be between DEST and SRC. That happens
7073 when one operand is GPR and the other one is XMM/YMM/ZMM
7075 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7078 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7080 /* For instructions with VexNDS, the register-only source
7081 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7082 register. It is encoded in VEX prefix. We need to
7083 clear RegMem bit before calling operand_type_equal. */
7085 i386_operand_type op
;
7088 /* Check register-only source operand when two source
7089 operands are swapped. */
7090 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7091 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7099 op
= i
.tm
.operand_types
[vvvv
];
7100 op
.bitfield
.regmem
= 0;
7101 if ((dest
+ 1) >= i
.operands
7102 || ((!op
.bitfield
.reg
7103 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7104 && !op
.bitfield
.regsimd
7105 && !operand_type_equal (&op
, ®mask
)))
7107 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7113 /* One of the register operands will be encoded in the i.tm.reg
7114 field, the other in the combined i.tm.mode and i.tm.regmem
7115 fields. If no form of this instruction supports a memory
7116 destination operand, then we assume the source operand may
7117 sometimes be a memory operand and so we need to store the
7118 destination in the i.rm.reg field. */
7119 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
7120 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7122 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7123 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7124 if (i
.op
[dest
].regs
->reg_type
.bitfield
.regmmx
7125 || i
.op
[source
].regs
->reg_type
.bitfield
.regmmx
)
7126 i
.has_regmmx
= TRUE
;
7127 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.regsimd
7128 || i
.op
[source
].regs
->reg_type
.bitfield
.regsimd
)
7130 if (i
.types
[dest
].bitfield
.zmmword
7131 || i
.types
[source
].bitfield
.zmmword
)
7132 i
.has_regzmm
= TRUE
;
7133 else if (i
.types
[dest
].bitfield
.ymmword
7134 || i
.types
[source
].bitfield
.ymmword
)
7135 i
.has_regymm
= TRUE
;
7137 i
.has_regxmm
= TRUE
;
7139 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7141 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7143 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7145 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7150 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7151 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7152 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7154 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7156 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7158 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7161 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7163 if (!i
.types
[i
.tm
.operand_types
[0].bitfield
.regmem
].bitfield
.control
)
7166 add_prefix (LOCK_PREFIX_OPCODE
);
7170 { /* If it's not 2 reg operands... */
7175 unsigned int fake_zero_displacement
= 0;
7178 for (op
= 0; op
< i
.operands
; op
++)
7179 if (operand_type_check (i
.types
[op
], anymem
))
7181 gas_assert (op
< i
.operands
);
7183 if (i
.tm
.opcode_modifier
.vecsib
)
7185 if (i
.index_reg
->reg_num
== RegIZ
)
7188 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7191 i
.sib
.base
= NO_BASE_REGISTER
;
7192 i
.sib
.scale
= i
.log2_scale_factor
;
7193 i
.types
[op
].bitfield
.disp8
= 0;
7194 i
.types
[op
].bitfield
.disp16
= 0;
7195 i
.types
[op
].bitfield
.disp64
= 0;
7196 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7198 /* Must be 32 bit */
7199 i
.types
[op
].bitfield
.disp32
= 1;
7200 i
.types
[op
].bitfield
.disp32s
= 0;
7204 i
.types
[op
].bitfield
.disp32
= 0;
7205 i
.types
[op
].bitfield
.disp32s
= 1;
7208 i
.sib
.index
= i
.index_reg
->reg_num
;
7209 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7211 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7217 if (i
.base_reg
== 0)
7220 if (!i
.disp_operands
)
7221 fake_zero_displacement
= 1;
7222 if (i
.index_reg
== 0)
7224 i386_operand_type newdisp
;
7226 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7227 /* Operand is just <disp> */
7228 if (flag_code
== CODE_64BIT
)
7230 /* 64bit mode overwrites the 32bit absolute
7231 addressing by RIP relative addressing and
7232 absolute addressing is encoded by one of the
7233 redundant SIB forms. */
7234 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7235 i
.sib
.base
= NO_BASE_REGISTER
;
7236 i
.sib
.index
= NO_INDEX_REGISTER
;
7237 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7239 else if ((flag_code
== CODE_16BIT
)
7240 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7242 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7247 i
.rm
.regmem
= NO_BASE_REGISTER
;
7250 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7251 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7253 else if (!i
.tm
.opcode_modifier
.vecsib
)
7255 /* !i.base_reg && i.index_reg */
7256 if (i
.index_reg
->reg_num
== RegIZ
)
7257 i
.sib
.index
= NO_INDEX_REGISTER
;
7259 i
.sib
.index
= i
.index_reg
->reg_num
;
7260 i
.sib
.base
= NO_BASE_REGISTER
;
7261 i
.sib
.scale
= i
.log2_scale_factor
;
7262 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7263 i
.types
[op
].bitfield
.disp8
= 0;
7264 i
.types
[op
].bitfield
.disp16
= 0;
7265 i
.types
[op
].bitfield
.disp64
= 0;
7266 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7268 /* Must be 32 bit */
7269 i
.types
[op
].bitfield
.disp32
= 1;
7270 i
.types
[op
].bitfield
.disp32s
= 0;
7274 i
.types
[op
].bitfield
.disp32
= 0;
7275 i
.types
[op
].bitfield
.disp32s
= 1;
7277 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7281 /* RIP addressing for 64bit mode. */
7282 else if (i
.base_reg
->reg_num
== RegIP
)
7284 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7285 i
.rm
.regmem
= NO_BASE_REGISTER
;
7286 i
.types
[op
].bitfield
.disp8
= 0;
7287 i
.types
[op
].bitfield
.disp16
= 0;
7288 i
.types
[op
].bitfield
.disp32
= 0;
7289 i
.types
[op
].bitfield
.disp32s
= 1;
7290 i
.types
[op
].bitfield
.disp64
= 0;
7291 i
.flags
[op
] |= Operand_PCrel
;
7292 if (! i
.disp_operands
)
7293 fake_zero_displacement
= 1;
7295 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7297 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7298 switch (i
.base_reg
->reg_num
)
7301 if (i
.index_reg
== 0)
7303 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7304 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7308 if (i
.index_reg
== 0)
7311 if (operand_type_check (i
.types
[op
], disp
) == 0)
7313 /* fake (%bp) into 0(%bp) */
7314 i
.types
[op
].bitfield
.disp8
= 1;
7315 fake_zero_displacement
= 1;
7318 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7319 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7321 default: /* (%si) -> 4 or (%di) -> 5 */
7322 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7324 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7326 else /* i.base_reg and 32/64 bit mode */
7328 if (flag_code
== CODE_64BIT
7329 && operand_type_check (i
.types
[op
], disp
))
7331 i
.types
[op
].bitfield
.disp16
= 0;
7332 i
.types
[op
].bitfield
.disp64
= 0;
7333 if (i
.prefix
[ADDR_PREFIX
] == 0)
7335 i
.types
[op
].bitfield
.disp32
= 0;
7336 i
.types
[op
].bitfield
.disp32s
= 1;
7340 i
.types
[op
].bitfield
.disp32
= 1;
7341 i
.types
[op
].bitfield
.disp32s
= 0;
7345 if (!i
.tm
.opcode_modifier
.vecsib
)
7346 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7347 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7349 i
.sib
.base
= i
.base_reg
->reg_num
;
7350 /* x86-64 ignores REX prefix bit here to avoid decoder
7352 if (!(i
.base_reg
->reg_flags
& RegRex
)
7353 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7354 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7356 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7358 fake_zero_displacement
= 1;
7359 i
.types
[op
].bitfield
.disp8
= 1;
7361 i
.sib
.scale
= i
.log2_scale_factor
;
7362 if (i
.index_reg
== 0)
7364 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7365 /* <disp>(%esp) becomes two byte modrm with no index
7366 register. We've already stored the code for esp
7367 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7368 Any base register besides %esp will not use the
7369 extra modrm byte. */
7370 i
.sib
.index
= NO_INDEX_REGISTER
;
7372 else if (!i
.tm
.opcode_modifier
.vecsib
)
7374 if (i
.index_reg
->reg_num
== RegIZ
)
7375 i
.sib
.index
= NO_INDEX_REGISTER
;
7377 i
.sib
.index
= i
.index_reg
->reg_num
;
7378 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7379 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7384 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7385 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7389 if (!fake_zero_displacement
7393 fake_zero_displacement
= 1;
7394 if (i
.disp_encoding
== disp_encoding_8bit
)
7395 i
.types
[op
].bitfield
.disp8
= 1;
7397 i
.types
[op
].bitfield
.disp32
= 1;
7399 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7403 if (fake_zero_displacement
)
7405 /* Fakes a zero displacement assuming that i.types[op]
7406 holds the correct displacement size. */
7409 gas_assert (i
.op
[op
].disps
== 0);
7410 exp
= &disp_expressions
[i
.disp_operands
++];
7411 i
.op
[op
].disps
= exp
;
7412 exp
->X_op
= O_constant
;
7413 exp
->X_add_number
= 0;
7414 exp
->X_add_symbol
= (symbolS
*) 0;
7415 exp
->X_op_symbol
= (symbolS
*) 0;
7423 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7425 if (operand_type_check (i
.types
[0], imm
))
7426 i
.vex
.register_specifier
= NULL
;
7429 /* VEX.vvvv encodes one of the sources when the first
7430 operand is not an immediate. */
7431 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7432 i
.vex
.register_specifier
= i
.op
[0].regs
;
7434 i
.vex
.register_specifier
= i
.op
[1].regs
;
7437 /* Destination is a XMM register encoded in the ModRM.reg
7439 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7440 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7443 /* ModRM.rm and VEX.B encodes the other source. */
7444 if (!i
.mem_operands
)
7448 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7449 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7451 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7453 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7457 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7459 i
.vex
.register_specifier
= i
.op
[2].regs
;
7460 if (!i
.mem_operands
)
7463 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7464 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7468 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7469 (if any) based on i.tm.extension_opcode. Again, we must be
7470 careful to make sure that segment/control/debug/test/MMX
7471 registers are coded into the i.rm.reg field. */
7472 else if (i
.reg_operands
)
7475 unsigned int vex_reg
= ~0;
7477 for (op
= 0; op
< i
.operands
; op
++)
7479 if (i
.types
[op
].bitfield
.reg
7480 || i
.types
[op
].bitfield
.regbnd
7481 || i
.types
[op
].bitfield
.regmask
7482 || i
.types
[op
].bitfield
.sreg2
7483 || i
.types
[op
].bitfield
.sreg3
7484 || i
.types
[op
].bitfield
.control
7485 || i
.types
[op
].bitfield
.debug
7486 || i
.types
[op
].bitfield
.test
)
7488 if (i
.types
[op
].bitfield
.regsimd
)
7490 if (i
.types
[op
].bitfield
.zmmword
)
7491 i
.has_regzmm
= TRUE
;
7492 else if (i
.types
[op
].bitfield
.ymmword
)
7493 i
.has_regymm
= TRUE
;
7495 i
.has_regxmm
= TRUE
;
7498 if (i
.types
[op
].bitfield
.regmmx
)
7500 i
.has_regmmx
= TRUE
;
7507 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7509 /* For instructions with VexNDS, the register-only
7510 source operand is encoded in VEX prefix. */
7511 gas_assert (mem
!= (unsigned int) ~0);
7516 gas_assert (op
< i
.operands
);
7520 /* Check register-only source operand when two source
7521 operands are swapped. */
7522 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7523 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7527 gas_assert (mem
== (vex_reg
+ 1)
7528 && op
< i
.operands
);
7533 gas_assert (vex_reg
< i
.operands
);
7537 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7539 /* For instructions with VexNDD, the register destination
7540 is encoded in VEX prefix. */
7541 if (i
.mem_operands
== 0)
7543 /* There is no memory operand. */
7544 gas_assert ((op
+ 2) == i
.operands
);
7549 /* There are only 2 non-immediate operands. */
7550 gas_assert (op
< i
.imm_operands
+ 2
7551 && i
.operands
== i
.imm_operands
+ 2);
7552 vex_reg
= i
.imm_operands
+ 1;
7556 gas_assert (op
< i
.operands
);
7558 if (vex_reg
!= (unsigned int) ~0)
7560 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7562 if ((!type
->bitfield
.reg
7563 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7564 && !type
->bitfield
.regsimd
7565 && !operand_type_equal (type
, ®mask
))
7568 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7571 /* Don't set OP operand twice. */
7574 /* If there is an extension opcode to put here, the
7575 register number must be put into the regmem field. */
7576 if (i
.tm
.extension_opcode
!= None
)
7578 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7579 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7581 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7586 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7587 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7589 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7594 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7595 must set it to 3 to indicate this is a register operand
7596 in the regmem field. */
7597 if (!i
.mem_operands
)
7601 /* Fill in i.rm.reg field with extension opcode (if any). */
7602 if (i
.tm
.extension_opcode
!= None
)
7603 i
.rm
.reg
= i
.tm
.extension_opcode
;
7609 output_branch (void)
7615 relax_substateT subtype
;
7619 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7620 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7623 if (i
.prefix
[DATA_PREFIX
] != 0)
7629 /* Pentium4 branch hints. */
7630 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7631 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7636 if (i
.prefix
[REX_PREFIX
] != 0)
7642 /* BND prefixed jump. */
7643 if (i
.prefix
[BND_PREFIX
] != 0)
7645 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7649 if (i
.prefixes
!= 0 && !intel_syntax
)
7650 as_warn (_("skipping prefixes on this instruction"));
7652 /* It's always a symbol; End frag & setup for relax.
7653 Make sure there is enough room in this frag for the largest
7654 instruction we may generate in md_convert_frag. This is 2
7655 bytes for the opcode and room for the prefix and largest
7657 frag_grow (prefix
+ 2 + 4);
7658 /* Prefix and 1 opcode byte go in fr_fix. */
7659 p
= frag_more (prefix
+ 1);
7660 if (i
.prefix
[DATA_PREFIX
] != 0)
7661 *p
++ = DATA_PREFIX_OPCODE
;
7662 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7663 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7664 *p
++ = i
.prefix
[SEG_PREFIX
];
7665 if (i
.prefix
[REX_PREFIX
] != 0)
7666 *p
++ = i
.prefix
[REX_PREFIX
];
7667 *p
= i
.tm
.base_opcode
;
7669 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7670 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7671 else if (cpu_arch_flags
.bitfield
.cpui386
)
7672 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7674 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7677 sym
= i
.op
[0].disps
->X_add_symbol
;
7678 off
= i
.op
[0].disps
->X_add_number
;
7680 if (i
.op
[0].disps
->X_op
!= O_constant
7681 && i
.op
[0].disps
->X_op
!= O_symbol
)
7683 /* Handle complex expressions. */
7684 sym
= make_expr_symbol (i
.op
[0].disps
);
7688 /* 1 possible extra opcode + 4 byte displacement go in var part.
7689 Pass reloc in fr_var. */
7690 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7693 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7694 /* Return TRUE iff PLT32 relocation should be used for branching to
7698 need_plt32_p (symbolS
*s
)
7700 /* PLT32 relocation is ELF only. */
7704 /* Since there is no need to prepare for PLT branch on x86-64, we
7705 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7706 be used as a marker for 32-bit PC-relative branches. */
7710 /* Weak or undefined symbol need PLT32 relocation. */
7711 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7714 /* Non-global symbol doesn't need PLT32 relocation. */
7715 if (! S_IS_EXTERNAL (s
))
7718 /* Other global symbols need PLT32 relocation. NB: Symbol with
7719 non-default visibilities are treated as normal global symbol
7720 so that PLT32 relocation can be used as a marker for 32-bit
7721 PC-relative branches. It is useful for linker relaxation. */
7732 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7734 if (i
.tm
.opcode_modifier
.jumpbyte
)
7736 /* This is a loop or jecxz type instruction. */
7738 if (i
.prefix
[ADDR_PREFIX
] != 0)
7740 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7743 /* Pentium4 branch hints. */
7744 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7745 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7747 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7756 if (flag_code
== CODE_16BIT
)
7759 if (i
.prefix
[DATA_PREFIX
] != 0)
7761 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7771 if (i
.prefix
[REX_PREFIX
] != 0)
7773 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7777 /* BND prefixed jump. */
7778 if (i
.prefix
[BND_PREFIX
] != 0)
7780 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7784 if (i
.prefixes
!= 0 && !intel_syntax
)
7785 as_warn (_("skipping prefixes on this instruction"));
7787 p
= frag_more (i
.tm
.opcode_length
+ size
);
7788 switch (i
.tm
.opcode_length
)
7791 *p
++ = i
.tm
.base_opcode
>> 8;
7794 *p
++ = i
.tm
.base_opcode
;
7800 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7802 && jump_reloc
== NO_RELOC
7803 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7804 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7807 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7809 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7810 i
.op
[0].disps
, 1, jump_reloc
);
7812 /* All jumps handled here are signed, but don't use a signed limit
7813 check for 32 and 16 bit jumps as we want to allow wrap around at
7814 4G and 64k respectively. */
7816 fixP
->fx_signed
= 1;
7820 output_interseg_jump (void)
7828 if (flag_code
== CODE_16BIT
)
7832 if (i
.prefix
[DATA_PREFIX
] != 0)
7838 if (i
.prefix
[REX_PREFIX
] != 0)
7848 if (i
.prefixes
!= 0 && !intel_syntax
)
7849 as_warn (_("skipping prefixes on this instruction"));
7851 /* 1 opcode; 2 segment; offset */
7852 p
= frag_more (prefix
+ 1 + 2 + size
);
7854 if (i
.prefix
[DATA_PREFIX
] != 0)
7855 *p
++ = DATA_PREFIX_OPCODE
;
7857 if (i
.prefix
[REX_PREFIX
] != 0)
7858 *p
++ = i
.prefix
[REX_PREFIX
];
7860 *p
++ = i
.tm
.base_opcode
;
7861 if (i
.op
[1].imms
->X_op
== O_constant
)
7863 offsetT n
= i
.op
[1].imms
->X_add_number
;
7866 && !fits_in_unsigned_word (n
)
7867 && !fits_in_signed_word (n
))
7869 as_bad (_("16-bit jump out of range"));
7872 md_number_to_chars (p
, n
, size
);
7875 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7876 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7877 if (i
.op
[0].imms
->X_op
!= O_constant
)
7878 as_bad (_("can't handle non absolute segment in `%s'"),
7880 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7883 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7888 asection
*seg
= now_seg
;
7889 subsegT subseg
= now_subseg
;
7891 unsigned int alignment
, align_size_1
;
7892 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
7893 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
7894 unsigned int padding
;
7896 if (!IS_ELF
|| !x86_used_note
)
7899 x86_isa_1_used
|= GNU_PROPERTY_X86_UINT32_VALID
;
7900 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
7902 /* The .note.gnu.property section layout:
7904 Field Length Contents
7907 n_descsz 4 The note descriptor size
7908 n_type 4 NT_GNU_PROPERTY_TYPE_0
7910 n_desc n_descsz The program property array
7914 /* Create the .note.gnu.property section. */
7915 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
7916 bfd_set_section_flags (stdoutput
, sec
,
7923 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
7934 bfd_set_section_alignment (stdoutput
, sec
, alignment
);
7935 elf_section_type (sec
) = SHT_NOTE
;
7937 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
7939 isa_1_descsz_raw
= 4 + 4 + 4;
7940 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
7941 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
7943 feature_2_descsz_raw
= isa_1_descsz
;
7944 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
7946 feature_2_descsz_raw
+= 4 + 4 + 4;
7947 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
7948 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
7951 descsz
= feature_2_descsz
;
7952 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
7953 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
7955 /* Write n_namsz. */
7956 md_number_to_chars (p
, (valueT
) 4, 4);
7958 /* Write n_descsz. */
7959 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
7962 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
7965 memcpy (p
+ 4 * 3, "GNU", 4);
7967 /* Write 4-byte type. */
7968 md_number_to_chars (p
+ 4 * 4,
7969 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
7971 /* Write 4-byte data size. */
7972 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
7974 /* Write 4-byte data. */
7975 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
7977 /* Zero out paddings. */
7978 padding
= isa_1_descsz
- isa_1_descsz_raw
;
7980 memset (p
+ 4 * 7, 0, padding
);
7982 /* Write 4-byte type. */
7983 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
7984 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
7986 /* Write 4-byte data size. */
7987 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
7989 /* Write 4-byte data. */
7990 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
7991 (valueT
) x86_feature_2_used
, 4);
7993 /* Zero out paddings. */
7994 padding
= feature_2_descsz
- feature_2_descsz_raw
;
7996 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
7998 /* We probably can't restore the current segment, for there likely
8001 subseg_set (seg
, subseg
);
8008 fragS
*insn_start_frag
;
8009 offsetT insn_start_off
;
8011 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8012 if (IS_ELF
&& x86_used_note
)
8014 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8015 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8016 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8017 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8018 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8019 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8020 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8021 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8022 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8023 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8024 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8025 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8026 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8027 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8028 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8029 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8030 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8031 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8032 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8033 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8034 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8035 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8036 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8037 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8038 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8039 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8040 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8041 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8042 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8043 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8044 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8045 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8046 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8047 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8048 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8049 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8050 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8051 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8052 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8053 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8054 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8055 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8056 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8057 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8058 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8059 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8060 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8061 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8063 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8064 || i
.tm
.cpu_flags
.bitfield
.cpu287
8065 || i
.tm
.cpu_flags
.bitfield
.cpu387
8066 || i
.tm
.cpu_flags
.bitfield
.cpu687
8067 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8068 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8069 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8070 Xfence instructions. */
8071 if (i
.tm
.base_opcode
!= 0xf18
8072 && i
.tm
.base_opcode
!= 0xf0d
8073 && i
.tm
.base_opcode
!= 0xfae
8075 || i
.tm
.cpu_flags
.bitfield
.cpummx
8076 || i
.tm
.cpu_flags
.bitfield
.cpua3dnow
8077 || i
.tm
.cpu_flags
.bitfield
.cpua3dnowa
))
8078 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8080 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8082 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8084 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8085 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8086 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8087 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8088 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8089 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8090 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8091 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8092 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8096 /* Tie dwarf2 debug info to the address at the start of the insn.
8097 We can't do this after the insn has been output as the current
8098 frag may have been closed off. eg. by frag_var. */
8099 dwarf2_emit_insn (0);
8101 insn_start_frag
= frag_now
;
8102 insn_start_off
= frag_now_fix ();
8105 if (i
.tm
.opcode_modifier
.jump
)
8107 else if (i
.tm
.opcode_modifier
.jumpbyte
8108 || i
.tm
.opcode_modifier
.jumpdword
)
8110 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
8111 output_interseg_jump ();
8114 /* Output normal instructions here. */
8118 unsigned int prefix
;
8121 && i
.tm
.base_opcode
== 0xfae
8123 && i
.imm_operands
== 1
8124 && (i
.op
[0].imms
->X_add_number
== 0xe8
8125 || i
.op
[0].imms
->X_add_number
== 0xf0
8126 || i
.op
[0].imms
->X_add_number
== 0xf8))
8128 /* Encode lfence, mfence, and sfence as
8129 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8130 offsetT val
= 0x240483f0ULL
;
8132 md_number_to_chars (p
, val
, 5);
8136 /* Some processors fail on LOCK prefix. This options makes
8137 assembler ignore LOCK prefix and serves as a workaround. */
8138 if (omit_lock_prefix
)
8140 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8142 i
.prefix
[LOCK_PREFIX
] = 0;
8145 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8146 don't need the explicit prefix. */
8147 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8149 switch (i
.tm
.opcode_length
)
8152 if (i
.tm
.base_opcode
& 0xff000000)
8154 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8155 add_prefix (prefix
);
8159 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8161 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8162 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8163 || prefix
!= REPE_PREFIX_OPCODE
8164 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8165 add_prefix (prefix
);
8171 /* Check for pseudo prefixes. */
8172 as_bad_where (insn_start_frag
->fr_file
,
8173 insn_start_frag
->fr_line
,
8174 _("pseudo prefix without instruction"));
8180 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8181 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8182 R_X86_64_GOTTPOFF relocation so that linker can safely
8183 perform IE->LE optimization. */
8184 if (x86_elf_abi
== X86_64_X32_ABI
8186 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8187 && i
.prefix
[REX_PREFIX
] == 0)
8188 add_prefix (REX_OPCODE
);
8191 /* The prefix bytes. */
8192 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8194 FRAG_APPEND_1_CHAR (*q
);
8198 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8203 /* REX byte is encoded in VEX prefix. */
8207 FRAG_APPEND_1_CHAR (*q
);
8210 /* There should be no other prefixes for instructions
8215 /* For EVEX instructions i.vrex should become 0 after
8216 build_evex_prefix. For VEX instructions upper 16 registers
8217 aren't available, so VREX should be 0. */
8220 /* Now the VEX prefix. */
8221 p
= frag_more (i
.vex
.length
);
8222 for (j
= 0; j
< i
.vex
.length
; j
++)
8223 p
[j
] = i
.vex
.bytes
[j
];
8226 /* Now the opcode; be careful about word order here! */
8227 if (i
.tm
.opcode_length
== 1)
8229 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8233 switch (i
.tm
.opcode_length
)
8237 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8238 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8242 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8252 /* Put out high byte first: can't use md_number_to_chars! */
8253 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8254 *p
= i
.tm
.base_opcode
& 0xff;
8257 /* Now the modrm byte and sib byte (if present). */
8258 if (i
.tm
.opcode_modifier
.modrm
)
8260 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8263 /* If i.rm.regmem == ESP (4)
8264 && i.rm.mode != (Register mode)
8266 ==> need second modrm byte. */
8267 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8269 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8270 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8272 | i
.sib
.scale
<< 6));
8275 if (i
.disp_operands
)
8276 output_disp (insn_start_frag
, insn_start_off
);
8279 output_imm (insn_start_frag
, insn_start_off
);
8285 pi ("" /*line*/, &i
);
8287 #endif /* DEBUG386 */
8290 /* Return the size of the displacement operand N. */
8293 disp_size (unsigned int n
)
8297 if (i
.types
[n
].bitfield
.disp64
)
8299 else if (i
.types
[n
].bitfield
.disp8
)
8301 else if (i
.types
[n
].bitfield
.disp16
)
8306 /* Return the size of the immediate operand N. */
8309 imm_size (unsigned int n
)
8312 if (i
.types
[n
].bitfield
.imm64
)
8314 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8316 else if (i
.types
[n
].bitfield
.imm16
)
8322 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8327 for (n
= 0; n
< i
.operands
; n
++)
8329 if (operand_type_check (i
.types
[n
], disp
))
8331 if (i
.op
[n
].disps
->X_op
== O_constant
)
8333 int size
= disp_size (n
);
8334 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8336 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8338 p
= frag_more (size
);
8339 md_number_to_chars (p
, val
, size
);
8343 enum bfd_reloc_code_real reloc_type
;
8344 int size
= disp_size (n
);
8345 int sign
= i
.types
[n
].bitfield
.disp32s
;
8346 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8349 /* We can't have 8 bit displacement here. */
8350 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8352 /* The PC relative address is computed relative
8353 to the instruction boundary, so in case immediate
8354 fields follows, we need to adjust the value. */
8355 if (pcrel
&& i
.imm_operands
)
8360 for (n1
= 0; n1
< i
.operands
; n1
++)
8361 if (operand_type_check (i
.types
[n1
], imm
))
8363 /* Only one immediate is allowed for PC
8364 relative address. */
8365 gas_assert (sz
== 0);
8367 i
.op
[n
].disps
->X_add_number
-= sz
;
8369 /* We should find the immediate. */
8370 gas_assert (sz
!= 0);
8373 p
= frag_more (size
);
8374 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8376 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8377 && (((reloc_type
== BFD_RELOC_32
8378 || reloc_type
== BFD_RELOC_X86_64_32S
8379 || (reloc_type
== BFD_RELOC_64
8381 && (i
.op
[n
].disps
->X_op
== O_symbol
8382 || (i
.op
[n
].disps
->X_op
== O_add
8383 && ((symbol_get_value_expression
8384 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8386 || reloc_type
== BFD_RELOC_32_PCREL
))
8390 if (insn_start_frag
== frag_now
)
8391 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8396 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8397 for (fr
= insn_start_frag
->fr_next
;
8398 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8400 add
+= p
- frag_now
->fr_literal
;
8405 reloc_type
= BFD_RELOC_386_GOTPC
;
8406 i
.op
[n
].imms
->X_add_number
+= add
;
8408 else if (reloc_type
== BFD_RELOC_64
)
8409 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8411 /* Don't do the adjustment for x86-64, as there
8412 the pcrel addressing is relative to the _next_
8413 insn, and that is taken care of in other code. */
8414 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8416 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8417 size
, i
.op
[n
].disps
, pcrel
,
8419 /* Check for "call/jmp *mem", "mov mem, %reg",
8420 "test %reg, mem" and "binop mem, %reg" where binop
8421 is one of adc, add, and, cmp, or, sbb, sub, xor
8422 instructions without data prefix. Always generate
8423 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
8424 if (i
.prefix
[DATA_PREFIX
] == 0
8425 && (generate_relax_relocations
8428 && i
.rm
.regmem
== 5))
8430 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8431 && ((i
.operands
== 1
8432 && i
.tm
.base_opcode
== 0xff
8433 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8435 && (i
.tm
.base_opcode
== 0x8b
8436 || i
.tm
.base_opcode
== 0x85
8437 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8441 fixP
->fx_tcbit
= i
.rex
!= 0;
8443 && (i
.base_reg
->reg_num
== RegIP
))
8444 fixP
->fx_tcbit2
= 1;
8447 fixP
->fx_tcbit2
= 1;
8455 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8460 for (n
= 0; n
< i
.operands
; n
++)
8462 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8463 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8466 if (operand_type_check (i
.types
[n
], imm
))
8468 if (i
.op
[n
].imms
->X_op
== O_constant
)
8470 int size
= imm_size (n
);
8473 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8475 p
= frag_more (size
);
8476 md_number_to_chars (p
, val
, size
);
8480 /* Not absolute_section.
8481 Need a 32-bit fixup (don't support 8bit
8482 non-absolute imms). Try to support other
8484 enum bfd_reloc_code_real reloc_type
;
8485 int size
= imm_size (n
);
8488 if (i
.types
[n
].bitfield
.imm32s
8489 && (i
.suffix
== QWORD_MNEM_SUFFIX
8490 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8495 p
= frag_more (size
);
8496 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8498 /* This is tough to explain. We end up with this one if we
8499 * have operands that look like
8500 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8501 * obtain the absolute address of the GOT, and it is strongly
8502 * preferable from a performance point of view to avoid using
8503 * a runtime relocation for this. The actual sequence of
8504 * instructions often look something like:
8509 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8511 * The call and pop essentially return the absolute address
8512 * of the label .L66 and store it in %ebx. The linker itself
8513 * will ultimately change the first operand of the addl so
8514 * that %ebx points to the GOT, but to keep things simple, the
8515 * .o file must have this operand set so that it generates not
8516 * the absolute address of .L66, but the absolute address of
8517 * itself. This allows the linker itself simply treat a GOTPC
8518 * relocation as asking for a pcrel offset to the GOT to be
8519 * added in, and the addend of the relocation is stored in the
8520 * operand field for the instruction itself.
8522 * Our job here is to fix the operand so that it would add
8523 * the correct offset so that %ebx would point to itself. The
8524 * thing that is tricky is that .-.L66 will point to the
8525 * beginning of the instruction, so we need to further modify
8526 * the operand so that it will point to itself. There are
8527 * other cases where you have something like:
8529 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8531 * and here no correction would be required. Internally in
8532 * the assembler we treat operands of this form as not being
8533 * pcrel since the '.' is explicitly mentioned, and I wonder
8534 * whether it would simplify matters to do it this way. Who
8535 * knows. In earlier versions of the PIC patches, the
8536 * pcrel_adjust field was used to store the correction, but
8537 * since the expression is not pcrel, I felt it would be
8538 * confusing to do it this way. */
8540 if ((reloc_type
== BFD_RELOC_32
8541 || reloc_type
== BFD_RELOC_X86_64_32S
8542 || reloc_type
== BFD_RELOC_64
)
8544 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8545 && (i
.op
[n
].imms
->X_op
== O_symbol
8546 || (i
.op
[n
].imms
->X_op
== O_add
8547 && ((symbol_get_value_expression
8548 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8553 if (insn_start_frag
== frag_now
)
8554 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8559 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8560 for (fr
= insn_start_frag
->fr_next
;
8561 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8563 add
+= p
- frag_now
->fr_literal
;
8567 reloc_type
= BFD_RELOC_386_GOTPC
;
8569 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8571 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8572 i
.op
[n
].imms
->X_add_number
+= add
;
8574 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8575 i
.op
[n
].imms
, 0, reloc_type
);
8581 /* x86_cons_fix_new is called via the expression parsing code when a
8582 reloc is needed. We use this hook to get the correct .got reloc. */
8583 static int cons_sign
= -1;
8586 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8587 expressionS
*exp
, bfd_reloc_code_real_type r
)
8589 r
= reloc (len
, 0, cons_sign
, r
);
8592 if (exp
->X_op
== O_secrel
)
8594 exp
->X_op
= O_symbol
;
8595 r
= BFD_RELOC_32_SECREL
;
8599 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8602 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8603 purpose of the `.dc.a' internal pseudo-op. */
8606 x86_address_bytes (void)
8608 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8610 return stdoutput
->arch_info
->bits_per_address
/ 8;
8613 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8615 # define lex_got(reloc, adjust, types) NULL
8617 /* Parse operands of the form
8618 <symbol>@GOTOFF+<nnn>
8619 and similar .plt or .got references.
8621 If we find one, set up the correct relocation in RELOC and copy the
8622 input string, minus the `@GOTOFF' into a malloc'd buffer for
8623 parsing by the calling routine. Return this buffer, and if ADJUST
8624 is non-null set it to the length of the string we removed from the
8625 input line. Otherwise return NULL. */
8627 lex_got (enum bfd_reloc_code_real
*rel
,
8629 i386_operand_type
*types
)
8631 /* Some of the relocations depend on the size of what field is to
8632 be relocated. But in our callers i386_immediate and i386_displacement
8633 we don't yet know the operand size (this will be set by insn
8634 matching). Hence we record the word32 relocation here,
8635 and adjust the reloc according to the real size in reloc(). */
8636 static const struct {
8639 const enum bfd_reloc_code_real rel
[2];
8640 const i386_operand_type types64
;
8642 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8643 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8645 OPERAND_TYPE_IMM32_64
},
8647 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8648 BFD_RELOC_X86_64_PLTOFF64
},
8649 OPERAND_TYPE_IMM64
},
8650 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8651 BFD_RELOC_X86_64_PLT32
},
8652 OPERAND_TYPE_IMM32_32S_DISP32
},
8653 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8654 BFD_RELOC_X86_64_GOTPLT64
},
8655 OPERAND_TYPE_IMM64_DISP64
},
8656 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8657 BFD_RELOC_X86_64_GOTOFF64
},
8658 OPERAND_TYPE_IMM64_DISP64
},
8659 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8660 BFD_RELOC_X86_64_GOTPCREL
},
8661 OPERAND_TYPE_IMM32_32S_DISP32
},
8662 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8663 BFD_RELOC_X86_64_TLSGD
},
8664 OPERAND_TYPE_IMM32_32S_DISP32
},
8665 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8666 _dummy_first_bfd_reloc_code_real
},
8667 OPERAND_TYPE_NONE
},
8668 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8669 BFD_RELOC_X86_64_TLSLD
},
8670 OPERAND_TYPE_IMM32_32S_DISP32
},
8671 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8672 BFD_RELOC_X86_64_GOTTPOFF
},
8673 OPERAND_TYPE_IMM32_32S_DISP32
},
8674 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8675 BFD_RELOC_X86_64_TPOFF32
},
8676 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8677 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8678 _dummy_first_bfd_reloc_code_real
},
8679 OPERAND_TYPE_NONE
},
8680 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8681 BFD_RELOC_X86_64_DTPOFF32
},
8682 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8683 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8684 _dummy_first_bfd_reloc_code_real
},
8685 OPERAND_TYPE_NONE
},
8686 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8687 _dummy_first_bfd_reloc_code_real
},
8688 OPERAND_TYPE_NONE
},
8689 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8690 BFD_RELOC_X86_64_GOT32
},
8691 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8692 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8693 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8694 OPERAND_TYPE_IMM32_32S_DISP32
},
8695 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8696 BFD_RELOC_X86_64_TLSDESC_CALL
},
8697 OPERAND_TYPE_IMM32_32S_DISP32
},
8702 #if defined (OBJ_MAYBE_ELF)
8707 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8708 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8711 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8713 int len
= gotrel
[j
].len
;
8714 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8716 if (gotrel
[j
].rel
[object_64bit
] != 0)
8719 char *tmpbuf
, *past_reloc
;
8721 *rel
= gotrel
[j
].rel
[object_64bit
];
8725 if (flag_code
!= CODE_64BIT
)
8727 types
->bitfield
.imm32
= 1;
8728 types
->bitfield
.disp32
= 1;
8731 *types
= gotrel
[j
].types64
;
8734 if (j
!= 0 && GOT_symbol
== NULL
)
8735 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8737 /* The length of the first part of our input line. */
8738 first
= cp
- input_line_pointer
;
8740 /* The second part goes from after the reloc token until
8741 (and including) an end_of_line char or comma. */
8742 past_reloc
= cp
+ 1 + len
;
8744 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8746 second
= cp
+ 1 - past_reloc
;
8748 /* Allocate and copy string. The trailing NUL shouldn't
8749 be necessary, but be safe. */
8750 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8751 memcpy (tmpbuf
, input_line_pointer
, first
);
8752 if (second
!= 0 && *past_reloc
!= ' ')
8753 /* Replace the relocation token with ' ', so that
8754 errors like foo@GOTOFF1 will be detected. */
8755 tmpbuf
[first
++] = ' ';
8757 /* Increment length by 1 if the relocation token is
8762 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8763 tmpbuf
[first
+ second
] = '\0';
8767 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8768 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8773 /* Might be a symbol version string. Don't as_bad here. */
8782 /* Parse operands of the form
8783 <symbol>@SECREL32+<nnn>
8785 If we find one, set up the correct relocation in RELOC and copy the
8786 input string, minus the `@SECREL32' into a malloc'd buffer for
8787 parsing by the calling routine. Return this buffer, and if ADJUST
8788 is non-null set it to the length of the string we removed from the
8789 input line. Otherwise return NULL.
8791 This function is copied from the ELF version above adjusted for PE targets. */
8794 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8795 int *adjust ATTRIBUTE_UNUSED
,
8796 i386_operand_type
*types
)
8802 const enum bfd_reloc_code_real rel
[2];
8803 const i386_operand_type types64
;
8807 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8808 BFD_RELOC_32_SECREL
},
8809 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8815 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8816 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8819 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8821 int len
= gotrel
[j
].len
;
8823 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8825 if (gotrel
[j
].rel
[object_64bit
] != 0)
8828 char *tmpbuf
, *past_reloc
;
8830 *rel
= gotrel
[j
].rel
[object_64bit
];
8836 if (flag_code
!= CODE_64BIT
)
8838 types
->bitfield
.imm32
= 1;
8839 types
->bitfield
.disp32
= 1;
8842 *types
= gotrel
[j
].types64
;
8845 /* The length of the first part of our input line. */
8846 first
= cp
- input_line_pointer
;
8848 /* The second part goes from after the reloc token until
8849 (and including) an end_of_line char or comma. */
8850 past_reloc
= cp
+ 1 + len
;
8852 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8854 second
= cp
+ 1 - past_reloc
;
8856 /* Allocate and copy string. The trailing NUL shouldn't
8857 be necessary, but be safe. */
8858 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8859 memcpy (tmpbuf
, input_line_pointer
, first
);
8860 if (second
!= 0 && *past_reloc
!= ' ')
8861 /* Replace the relocation token with ' ', so that
8862 errors like foo@SECLREL321 will be detected. */
8863 tmpbuf
[first
++] = ' ';
8864 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8865 tmpbuf
[first
+ second
] = '\0';
8869 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8870 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8875 /* Might be a symbol version string. Don't as_bad here. */
8881 bfd_reloc_code_real_type
8882 x86_cons (expressionS
*exp
, int size
)
8884 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
8886 intel_syntax
= -intel_syntax
;
8889 if (size
== 4 || (object_64bit
&& size
== 8))
8891 /* Handle @GOTOFF and the like in an expression. */
8893 char *gotfree_input_line
;
8896 save
= input_line_pointer
;
8897 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
8898 if (gotfree_input_line
)
8899 input_line_pointer
= gotfree_input_line
;
8903 if (gotfree_input_line
)
8905 /* expression () has merrily parsed up to the end of line,
8906 or a comma - in the wrong buffer. Transfer how far
8907 input_line_pointer has moved to the right buffer. */
8908 input_line_pointer
= (save
8909 + (input_line_pointer
- gotfree_input_line
)
8911 free (gotfree_input_line
);
8912 if (exp
->X_op
== O_constant
8913 || exp
->X_op
== O_absent
8914 || exp
->X_op
== O_illegal
8915 || exp
->X_op
== O_register
8916 || exp
->X_op
== O_big
)
8918 char c
= *input_line_pointer
;
8919 *input_line_pointer
= 0;
8920 as_bad (_("missing or invalid expression `%s'"), save
);
8921 *input_line_pointer
= c
;
8928 intel_syntax
= -intel_syntax
;
8931 i386_intel_simplify (exp
);
8937 signed_cons (int size
)
8939 if (flag_code
== CODE_64BIT
)
8947 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
8954 if (exp
.X_op
== O_symbol
)
8955 exp
.X_op
= O_secrel
;
8957 emit_expr (&exp
, 4);
8959 while (*input_line_pointer
++ == ',');
8961 input_line_pointer
--;
8962 demand_empty_rest_of_line ();
8966 /* Handle Vector operations. */
8969 check_VecOperations (char *op_string
, char *op_end
)
8971 const reg_entry
*mask
;
8976 && (op_end
== NULL
|| op_string
< op_end
))
8979 if (*op_string
== '{')
8983 /* Check broadcasts. */
8984 if (strncmp (op_string
, "1to", 3) == 0)
8989 goto duplicated_vec_op
;
8992 if (*op_string
== '8')
8994 else if (*op_string
== '4')
8996 else if (*op_string
== '2')
8998 else if (*op_string
== '1'
8999 && *(op_string
+1) == '6')
9006 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9011 broadcast_op
.type
= bcst_type
;
9012 broadcast_op
.operand
= this_operand
;
9013 broadcast_op
.bytes
= 0;
9014 i
.broadcast
= &broadcast_op
;
9016 /* Check masking operation. */
9017 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9019 /* k0 can't be used for write mask. */
9020 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
9022 as_bad (_("`%s%s' can't be used for write mask"),
9023 register_prefix
, mask
->reg_name
);
9029 mask_op
.mask
= mask
;
9030 mask_op
.zeroing
= 0;
9031 mask_op
.operand
= this_operand
;
9037 goto duplicated_vec_op
;
9039 i
.mask
->mask
= mask
;
9041 /* Only "{z}" is allowed here. No need to check
9042 zeroing mask explicitly. */
9043 if (i
.mask
->operand
!= this_operand
)
9045 as_bad (_("invalid write mask `%s'"), saved
);
9052 /* Check zeroing-flag for masking operation. */
9053 else if (*op_string
== 'z')
9057 mask_op
.mask
= NULL
;
9058 mask_op
.zeroing
= 1;
9059 mask_op
.operand
= this_operand
;
9064 if (i
.mask
->zeroing
)
9067 as_bad (_("duplicated `%s'"), saved
);
9071 i
.mask
->zeroing
= 1;
9073 /* Only "{%k}" is allowed here. No need to check mask
9074 register explicitly. */
9075 if (i
.mask
->operand
!= this_operand
)
9077 as_bad (_("invalid zeroing-masking `%s'"),
9086 goto unknown_vec_op
;
9088 if (*op_string
!= '}')
9090 as_bad (_("missing `}' in `%s'"), saved
);
9095 /* Strip whitespace since the addition of pseudo prefixes
9096 changed how the scrubber treats '{'. */
9097 if (is_space_char (*op_string
))
9103 /* We don't know this one. */
9104 as_bad (_("unknown vector operation: `%s'"), saved
);
9108 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9110 as_bad (_("zeroing-masking only allowed with write mask"));
9118 i386_immediate (char *imm_start
)
9120 char *save_input_line_pointer
;
9121 char *gotfree_input_line
;
9124 i386_operand_type types
;
9126 operand_type_set (&types
, ~0);
9128 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9130 as_bad (_("at most %d immediate operands are allowed"),
9131 MAX_IMMEDIATE_OPERANDS
);
9135 exp
= &im_expressions
[i
.imm_operands
++];
9136 i
.op
[this_operand
].imms
= exp
;
9138 if (is_space_char (*imm_start
))
9141 save_input_line_pointer
= input_line_pointer
;
9142 input_line_pointer
= imm_start
;
9144 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9145 if (gotfree_input_line
)
9146 input_line_pointer
= gotfree_input_line
;
9148 exp_seg
= expression (exp
);
9152 /* Handle vector operations. */
9153 if (*input_line_pointer
== '{')
9155 input_line_pointer
= check_VecOperations (input_line_pointer
,
9157 if (input_line_pointer
== NULL
)
9161 if (*input_line_pointer
)
9162 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9164 input_line_pointer
= save_input_line_pointer
;
9165 if (gotfree_input_line
)
9167 free (gotfree_input_line
);
9169 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9170 exp
->X_op
= O_illegal
;
9173 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9177 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9178 i386_operand_type types
, const char *imm_start
)
9180 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9183 as_bad (_("missing or invalid immediate expression `%s'"),
9187 else if (exp
->X_op
== O_constant
)
9189 /* Size it properly later. */
9190 i
.types
[this_operand
].bitfield
.imm64
= 1;
9191 /* If not 64bit, sign extend val. */
9192 if (flag_code
!= CODE_64BIT
9193 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9195 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9197 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9198 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9199 && exp_seg
!= absolute_section
9200 && exp_seg
!= text_section
9201 && exp_seg
!= data_section
9202 && exp_seg
!= bss_section
9203 && exp_seg
!= undefined_section
9204 && !bfd_is_com_section (exp_seg
))
9206 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9210 else if (!intel_syntax
&& exp_seg
== reg_section
)
9213 as_bad (_("illegal immediate register operand %s"), imm_start
);
9218 /* This is an address. The size of the address will be
9219 determined later, depending on destination register,
9220 suffix, or the default for the section. */
9221 i
.types
[this_operand
].bitfield
.imm8
= 1;
9222 i
.types
[this_operand
].bitfield
.imm16
= 1;
9223 i
.types
[this_operand
].bitfield
.imm32
= 1;
9224 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9225 i
.types
[this_operand
].bitfield
.imm64
= 1;
9226 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9234 i386_scale (char *scale
)
9237 char *save
= input_line_pointer
;
9239 input_line_pointer
= scale
;
9240 val
= get_absolute_expression ();
9245 i
.log2_scale_factor
= 0;
9248 i
.log2_scale_factor
= 1;
9251 i
.log2_scale_factor
= 2;
9254 i
.log2_scale_factor
= 3;
9258 char sep
= *input_line_pointer
;
9260 *input_line_pointer
= '\0';
9261 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9263 *input_line_pointer
= sep
;
9264 input_line_pointer
= save
;
9268 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9270 as_warn (_("scale factor of %d without an index register"),
9271 1 << i
.log2_scale_factor
);
9272 i
.log2_scale_factor
= 0;
9274 scale
= input_line_pointer
;
9275 input_line_pointer
= save
;
9280 i386_displacement (char *disp_start
, char *disp_end
)
9284 char *save_input_line_pointer
;
9285 char *gotfree_input_line
;
9287 i386_operand_type bigdisp
, types
= anydisp
;
9290 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9292 as_bad (_("at most %d displacement operands are allowed"),
9293 MAX_MEMORY_OPERANDS
);
9297 operand_type_set (&bigdisp
, 0);
9298 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
9299 || (!current_templates
->start
->opcode_modifier
.jump
9300 && !current_templates
->start
->opcode_modifier
.jumpdword
))
9302 bigdisp
.bitfield
.disp32
= 1;
9303 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9304 if (flag_code
== CODE_64BIT
)
9308 bigdisp
.bitfield
.disp32s
= 1;
9309 bigdisp
.bitfield
.disp64
= 1;
9312 else if ((flag_code
== CODE_16BIT
) ^ override
)
9314 bigdisp
.bitfield
.disp32
= 0;
9315 bigdisp
.bitfield
.disp16
= 1;
9320 /* For PC-relative branches, the width of the displacement
9321 is dependent upon data size, not address size. */
9322 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9323 if (flag_code
== CODE_64BIT
)
9325 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9326 bigdisp
.bitfield
.disp16
= 1;
9329 bigdisp
.bitfield
.disp32
= 1;
9330 bigdisp
.bitfield
.disp32s
= 1;
9336 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9338 : LONG_MNEM_SUFFIX
));
9339 bigdisp
.bitfield
.disp32
= 1;
9340 if ((flag_code
== CODE_16BIT
) ^ override
)
9342 bigdisp
.bitfield
.disp32
= 0;
9343 bigdisp
.bitfield
.disp16
= 1;
9347 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9350 exp
= &disp_expressions
[i
.disp_operands
];
9351 i
.op
[this_operand
].disps
= exp
;
9353 save_input_line_pointer
= input_line_pointer
;
9354 input_line_pointer
= disp_start
;
9355 END_STRING_AND_SAVE (disp_end
);
9357 #ifndef GCC_ASM_O_HACK
9358 #define GCC_ASM_O_HACK 0
9361 END_STRING_AND_SAVE (disp_end
+ 1);
9362 if (i
.types
[this_operand
].bitfield
.baseIndex
9363 && displacement_string_end
[-1] == '+')
9365 /* This hack is to avoid a warning when using the "o"
9366 constraint within gcc asm statements.
9369 #define _set_tssldt_desc(n,addr,limit,type) \
9370 __asm__ __volatile__ ( \
9372 "movw %w1,2+%0\n\t" \
9374 "movb %b1,4+%0\n\t" \
9375 "movb %4,5+%0\n\t" \
9376 "movb $0,6+%0\n\t" \
9377 "movb %h1,7+%0\n\t" \
9379 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9381 This works great except that the output assembler ends
9382 up looking a bit weird if it turns out that there is
9383 no offset. You end up producing code that looks like:
9396 So here we provide the missing zero. */
9398 *displacement_string_end
= '0';
9401 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9402 if (gotfree_input_line
)
9403 input_line_pointer
= gotfree_input_line
;
9405 exp_seg
= expression (exp
);
9408 if (*input_line_pointer
)
9409 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9411 RESTORE_END_STRING (disp_end
+ 1);
9413 input_line_pointer
= save_input_line_pointer
;
9414 if (gotfree_input_line
)
9416 free (gotfree_input_line
);
9418 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9419 exp
->X_op
= O_illegal
;
9422 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9424 RESTORE_END_STRING (disp_end
);
9430 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9431 i386_operand_type types
, const char *disp_start
)
9433 i386_operand_type bigdisp
;
9436 /* We do this to make sure that the section symbol is in
9437 the symbol table. We will ultimately change the relocation
9438 to be relative to the beginning of the section. */
9439 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9440 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9441 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9443 if (exp
->X_op
!= O_symbol
)
9446 if (S_IS_LOCAL (exp
->X_add_symbol
)
9447 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9448 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9449 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9450 exp
->X_op
= O_subtract
;
9451 exp
->X_op_symbol
= GOT_symbol
;
9452 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9453 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9454 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9455 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9457 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9460 else if (exp
->X_op
== O_absent
9461 || exp
->X_op
== O_illegal
9462 || exp
->X_op
== O_big
)
9465 as_bad (_("missing or invalid displacement expression `%s'"),
9470 else if (flag_code
== CODE_64BIT
9471 && !i
.prefix
[ADDR_PREFIX
]
9472 && exp
->X_op
== O_constant
)
9474 /* Since displacement is signed extended to 64bit, don't allow
9475 disp32 and turn off disp32s if they are out of range. */
9476 i
.types
[this_operand
].bitfield
.disp32
= 0;
9477 if (!fits_in_signed_long (exp
->X_add_number
))
9479 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9480 if (i
.types
[this_operand
].bitfield
.baseindex
)
9482 as_bad (_("0x%lx out range of signed 32bit displacement"),
9483 (long) exp
->X_add_number
);
9489 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9490 else if (exp
->X_op
!= O_constant
9491 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9492 && exp_seg
!= absolute_section
9493 && exp_seg
!= text_section
9494 && exp_seg
!= data_section
9495 && exp_seg
!= bss_section
9496 && exp_seg
!= undefined_section
9497 && !bfd_is_com_section (exp_seg
))
9499 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9504 /* Check if this is a displacement only operand. */
9505 bigdisp
= i
.types
[this_operand
];
9506 bigdisp
.bitfield
.disp8
= 0;
9507 bigdisp
.bitfield
.disp16
= 0;
9508 bigdisp
.bitfield
.disp32
= 0;
9509 bigdisp
.bitfield
.disp32s
= 0;
9510 bigdisp
.bitfield
.disp64
= 0;
9511 if (operand_type_all_zero (&bigdisp
))
9512 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9518 /* Return the active addressing mode, taking address override and
9519 registers forming the address into consideration. Update the
9520 address override prefix if necessary. */
9522 static enum flag_code
9523 i386_addressing_mode (void)
9525 enum flag_code addr_mode
;
9527 if (i
.prefix
[ADDR_PREFIX
])
9528 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9531 addr_mode
= flag_code
;
9533 #if INFER_ADDR_PREFIX
9534 if (i
.mem_operands
== 0)
9536 /* Infer address prefix from the first memory operand. */
9537 const reg_entry
*addr_reg
= i
.base_reg
;
9539 if (addr_reg
== NULL
)
9540 addr_reg
= i
.index_reg
;
9544 if (addr_reg
->reg_type
.bitfield
.dword
)
9545 addr_mode
= CODE_32BIT
;
9546 else if (flag_code
!= CODE_64BIT
9547 && addr_reg
->reg_type
.bitfield
.word
)
9548 addr_mode
= CODE_16BIT
;
9550 if (addr_mode
!= flag_code
)
9552 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9554 /* Change the size of any displacement too. At most one
9555 of Disp16 or Disp32 is set.
9556 FIXME. There doesn't seem to be any real need for
9557 separate Disp16 and Disp32 flags. The same goes for
9558 Imm16 and Imm32. Removing them would probably clean
9559 up the code quite a lot. */
9560 if (flag_code
!= CODE_64BIT
9561 && (i
.types
[this_operand
].bitfield
.disp16
9562 || i
.types
[this_operand
].bitfield
.disp32
))
9563 i
.types
[this_operand
]
9564 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9574 /* Make sure the memory operand we've been dealt is valid.
9575 Return 1 on success, 0 on a failure. */
9578 i386_index_check (const char *operand_string
)
9580 const char *kind
= "base/index";
9581 enum flag_code addr_mode
= i386_addressing_mode ();
9583 if (current_templates
->start
->opcode_modifier
.isstring
9584 && !current_templates
->start
->opcode_modifier
.immext
9585 && (current_templates
->end
[-1].opcode_modifier
.isstring
9588 /* Memory operands of string insns are special in that they only allow
9589 a single register (rDI, rSI, or rBX) as their memory address. */
9590 const reg_entry
*expected_reg
;
9591 static const char *di_si
[][2] =
9597 static const char *bx
[] = { "ebx", "bx", "rbx" };
9599 kind
= "string address";
9601 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9603 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9605 if (!type
.bitfield
.baseindex
9606 || ((!i
.mem_operands
!= !intel_syntax
)
9607 && current_templates
->end
[-1].operand_types
[1]
9608 .bitfield
.baseindex
))
9609 type
= current_templates
->end
[-1].operand_types
[1];
9610 expected_reg
= hash_find (reg_hash
,
9611 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9615 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9617 if (i
.base_reg
!= expected_reg
9619 || operand_type_check (i
.types
[this_operand
], disp
))
9621 /* The second memory operand must have the same size as
9625 && !((addr_mode
== CODE_64BIT
9626 && i
.base_reg
->reg_type
.bitfield
.qword
)
9627 || (addr_mode
== CODE_32BIT
9628 ? i
.base_reg
->reg_type
.bitfield
.dword
9629 : i
.base_reg
->reg_type
.bitfield
.word
)))
9632 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9634 intel_syntax
? '[' : '(',
9636 expected_reg
->reg_name
,
9637 intel_syntax
? ']' : ')');
9644 as_bad (_("`%s' is not a valid %s expression"),
9645 operand_string
, kind
);
9650 if (addr_mode
!= CODE_16BIT
)
9652 /* 32-bit/64-bit checks. */
9654 && ((addr_mode
== CODE_64BIT
9655 ? !i
.base_reg
->reg_type
.bitfield
.qword
9656 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9657 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
9658 || i
.base_reg
->reg_num
== RegIZ
))
9660 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9661 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9662 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9663 && ((addr_mode
== CODE_64BIT
9664 ? !i
.index_reg
->reg_type
.bitfield
.qword
9665 : !i
.index_reg
->reg_type
.bitfield
.dword
)
9666 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9669 /* bndmk, bndldx, and bndstx have special restrictions. */
9670 if (current_templates
->start
->base_opcode
== 0xf30f1b
9671 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9673 /* They cannot use RIP-relative addressing. */
9674 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9676 as_bad (_("`%s' cannot be used here"), operand_string
);
9680 /* bndldx and bndstx ignore their scale factor. */
9681 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9682 && i
.log2_scale_factor
)
9683 as_warn (_("register scaling is being ignored here"));
9688 /* 16-bit checks. */
9690 && (!i
.base_reg
->reg_type
.bitfield
.word
9691 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9693 && (!i
.index_reg
->reg_type
.bitfield
.word
9694 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9696 && i
.base_reg
->reg_num
< 6
9697 && i
.index_reg
->reg_num
>= 6
9698 && i
.log2_scale_factor
== 0))))
9705 /* Handle vector immediates. */
9708 RC_SAE_immediate (const char *imm_start
)
9710 unsigned int match_found
, j
;
9711 const char *pstr
= imm_start
;
9719 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9721 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9725 rc_op
.type
= RC_NamesTable
[j
].type
;
9726 rc_op
.operand
= this_operand
;
9727 i
.rounding
= &rc_op
;
9731 as_bad (_("duplicated `%s'"), imm_start
);
9734 pstr
+= RC_NamesTable
[j
].len
;
9744 as_bad (_("Missing '}': '%s'"), imm_start
);
9747 /* RC/SAE immediate string should contain nothing more. */;
9750 as_bad (_("Junk after '}': '%s'"), imm_start
);
9754 exp
= &im_expressions
[i
.imm_operands
++];
9755 i
.op
[this_operand
].imms
= exp
;
9757 exp
->X_op
= O_constant
;
9758 exp
->X_add_number
= 0;
9759 exp
->X_add_symbol
= (symbolS
*) 0;
9760 exp
->X_op_symbol
= (symbolS
*) 0;
9762 i
.types
[this_operand
].bitfield
.imm8
= 1;
9766 /* Only string instructions can have a second memory operand, so
9767 reduce current_templates to just those if it contains any. */
9769 maybe_adjust_templates (void)
9771 const insn_template
*t
;
9773 gas_assert (i
.mem_operands
== 1);
9775 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9776 if (t
->opcode_modifier
.isstring
)
9779 if (t
< current_templates
->end
)
9781 static templates aux_templates
;
9782 bfd_boolean recheck
;
9784 aux_templates
.start
= t
;
9785 for (; t
< current_templates
->end
; ++t
)
9786 if (!t
->opcode_modifier
.isstring
)
9788 aux_templates
.end
= t
;
9790 /* Determine whether to re-check the first memory operand. */
9791 recheck
= (aux_templates
.start
!= current_templates
->start
9792 || t
!= current_templates
->end
);
9794 current_templates
= &aux_templates
;
9799 if (i
.memop1_string
!= NULL
9800 && i386_index_check (i
.memop1_string
) == 0)
9809 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9813 i386_att_operand (char *operand_string
)
9817 char *op_string
= operand_string
;
9819 if (is_space_char (*op_string
))
9822 /* We check for an absolute prefix (differentiating,
9823 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9824 if (*op_string
== ABSOLUTE_PREFIX
)
9827 if (is_space_char (*op_string
))
9829 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9832 /* Check if operand is a register. */
9833 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
9835 i386_operand_type temp
;
9837 /* Check for a segment override by searching for ':' after a
9838 segment register. */
9840 if (is_space_char (*op_string
))
9842 if (*op_string
== ':'
9843 && (r
->reg_type
.bitfield
.sreg2
9844 || r
->reg_type
.bitfield
.sreg3
))
9849 i
.seg
[i
.mem_operands
] = &es
;
9852 i
.seg
[i
.mem_operands
] = &cs
;
9855 i
.seg
[i
.mem_operands
] = &ss
;
9858 i
.seg
[i
.mem_operands
] = &ds
;
9861 i
.seg
[i
.mem_operands
] = &fs
;
9864 i
.seg
[i
.mem_operands
] = &gs
;
9868 /* Skip the ':' and whitespace. */
9870 if (is_space_char (*op_string
))
9873 if (!is_digit_char (*op_string
)
9874 && !is_identifier_char (*op_string
)
9875 && *op_string
!= '('
9876 && *op_string
!= ABSOLUTE_PREFIX
)
9878 as_bad (_("bad memory operand `%s'"), op_string
);
9881 /* Handle case of %es:*foo. */
9882 if (*op_string
== ABSOLUTE_PREFIX
)
9885 if (is_space_char (*op_string
))
9887 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9889 goto do_memory_reference
;
9892 /* Handle vector operations. */
9893 if (*op_string
== '{')
9895 op_string
= check_VecOperations (op_string
, NULL
);
9896 if (op_string
== NULL
)
9902 as_bad (_("junk `%s' after register"), op_string
);
9906 temp
.bitfield
.baseindex
= 0;
9907 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9909 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9910 i
.op
[this_operand
].regs
= r
;
9913 else if (*op_string
== REGISTER_PREFIX
)
9915 as_bad (_("bad register name `%s'"), op_string
);
9918 else if (*op_string
== IMMEDIATE_PREFIX
)
9921 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
9923 as_bad (_("immediate operand illegal with absolute jump"));
9926 if (!i386_immediate (op_string
))
9929 else if (RC_SAE_immediate (operand_string
))
9931 /* If it is a RC or SAE immediate, do nothing. */
9934 else if (is_digit_char (*op_string
)
9935 || is_identifier_char (*op_string
)
9936 || *op_string
== '"'
9937 || *op_string
== '(')
9939 /* This is a memory reference of some sort. */
9942 /* Start and end of displacement string expression (if found). */
9943 char *displacement_string_start
;
9944 char *displacement_string_end
;
9947 do_memory_reference
:
9948 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
9950 if ((i
.mem_operands
== 1
9951 && !current_templates
->start
->opcode_modifier
.isstring
)
9952 || i
.mem_operands
== 2)
9954 as_bad (_("too many memory references for `%s'"),
9955 current_templates
->start
->name
);
9959 /* Check for base index form. We detect the base index form by
9960 looking for an ')' at the end of the operand, searching
9961 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9963 base_string
= op_string
+ strlen (op_string
);
9965 /* Handle vector operations. */
9966 vop_start
= strchr (op_string
, '{');
9967 if (vop_start
&& vop_start
< base_string
)
9969 if (check_VecOperations (vop_start
, base_string
) == NULL
)
9971 base_string
= vop_start
;
9975 if (is_space_char (*base_string
))
9978 /* If we only have a displacement, set-up for it to be parsed later. */
9979 displacement_string_start
= op_string
;
9980 displacement_string_end
= base_string
+ 1;
9982 if (*base_string
== ')')
9985 unsigned int parens_balanced
= 1;
9986 /* We've already checked that the number of left & right ()'s are
9987 equal, so this loop will not be infinite. */
9991 if (*base_string
== ')')
9993 if (*base_string
== '(')
9996 while (parens_balanced
);
9998 temp_string
= base_string
;
10000 /* Skip past '(' and whitespace. */
10002 if (is_space_char (*base_string
))
10005 if (*base_string
== ','
10006 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10009 displacement_string_end
= temp_string
;
10011 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10015 base_string
= end_op
;
10016 if (is_space_char (*base_string
))
10020 /* There may be an index reg or scale factor here. */
10021 if (*base_string
== ',')
10024 if (is_space_char (*base_string
))
10027 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10030 base_string
= end_op
;
10031 if (is_space_char (*base_string
))
10033 if (*base_string
== ',')
10036 if (is_space_char (*base_string
))
10039 else if (*base_string
!= ')')
10041 as_bad (_("expecting `,' or `)' "
10042 "after index register in `%s'"),
10047 else if (*base_string
== REGISTER_PREFIX
)
10049 end_op
= strchr (base_string
, ',');
10052 as_bad (_("bad register name `%s'"), base_string
);
10056 /* Check for scale factor. */
10057 if (*base_string
!= ')')
10059 char *end_scale
= i386_scale (base_string
);
10064 base_string
= end_scale
;
10065 if (is_space_char (*base_string
))
10067 if (*base_string
!= ')')
10069 as_bad (_("expecting `)' "
10070 "after scale factor in `%s'"),
10075 else if (!i
.index_reg
)
10077 as_bad (_("expecting index register or scale factor "
10078 "after `,'; got '%c'"),
10083 else if (*base_string
!= ')')
10085 as_bad (_("expecting `,' or `)' "
10086 "after base register in `%s'"),
10091 else if (*base_string
== REGISTER_PREFIX
)
10093 end_op
= strchr (base_string
, ',');
10096 as_bad (_("bad register name `%s'"), base_string
);
10101 /* If there's an expression beginning the operand, parse it,
10102 assuming displacement_string_start and
10103 displacement_string_end are meaningful. */
10104 if (displacement_string_start
!= displacement_string_end
)
10106 if (!i386_displacement (displacement_string_start
,
10107 displacement_string_end
))
10111 /* Special case for (%dx) while doing input/output op. */
10113 && i
.base_reg
->reg_type
.bitfield
.inoutportreg
10114 && i
.index_reg
== 0
10115 && i
.log2_scale_factor
== 0
10116 && i
.seg
[i
.mem_operands
] == 0
10117 && !operand_type_check (i
.types
[this_operand
], disp
))
10119 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10123 if (i386_index_check (operand_string
) == 0)
10125 i
.flags
[this_operand
] |= Operand_Mem
;
10126 if (i
.mem_operands
== 0)
10127 i
.memop1_string
= xstrdup (operand_string
);
10132 /* It's not a memory operand; argh! */
10133 as_bad (_("invalid char %s beginning operand %d `%s'"),
10134 output_invalid (*op_string
),
10139 return 1; /* Normal return. */
10142 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10143 that an rs_machine_dependent frag may reach. */
10146 i386_frag_max_var (fragS
*frag
)
10148 /* The only relaxable frags are for jumps.
10149 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10150 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10151 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10154 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10156 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10158 /* STT_GNU_IFUNC symbol must go through PLT. */
10159 if ((symbol_get_bfdsym (fr_symbol
)->flags
10160 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10163 if (!S_IS_EXTERNAL (fr_symbol
))
10164 /* Symbol may be weak or local. */
10165 return !S_IS_WEAK (fr_symbol
);
10167 /* Global symbols with non-default visibility can't be preempted. */
10168 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10171 if (fr_var
!= NO_RELOC
)
10172 switch ((enum bfd_reloc_code_real
) fr_var
)
10174 case BFD_RELOC_386_PLT32
:
10175 case BFD_RELOC_X86_64_PLT32
:
10176 /* Symbol with PLT relocation may be preempted. */
10182 /* Global symbols with default visibility in a shared library may be
10183 preempted by another definition. */
10188 /* md_estimate_size_before_relax()
10190 Called just before relax() for rs_machine_dependent frags. The x86
10191 assembler uses these frags to handle variable size jump
10194 Any symbol that is now undefined will not become defined.
10195 Return the correct fr_subtype in the frag.
10196 Return the initial "guess for variable size of frag" to caller.
10197 The guess is actually the growth beyond the fixed part. Whatever
10198 we do to grow the fixed or variable part contributes to our
10202 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
10204 /* We've already got fragP->fr_subtype right; all we have to do is
10205 check for un-relaxable symbols. On an ELF system, we can't relax
10206 an externally visible symbol, because it may be overridden by a
10208 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
10209 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10211 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
10214 #if defined (OBJ_COFF) && defined (TE_PE)
10215 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
10216 && S_IS_WEAK (fragP
->fr_symbol
))
10220 /* Symbol is undefined in this segment, or we need to keep a
10221 reloc so that weak symbols can be overridden. */
10222 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
10223 enum bfd_reloc_code_real reloc_type
;
10224 unsigned char *opcode
;
10227 if (fragP
->fr_var
!= NO_RELOC
)
10228 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
10229 else if (size
== 2)
10230 reloc_type
= BFD_RELOC_16_PCREL
;
10231 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10232 else if (need_plt32_p (fragP
->fr_symbol
))
10233 reloc_type
= BFD_RELOC_X86_64_PLT32
;
10236 reloc_type
= BFD_RELOC_32_PCREL
;
10238 old_fr_fix
= fragP
->fr_fix
;
10239 opcode
= (unsigned char *) fragP
->fr_opcode
;
10241 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
10244 /* Make jmp (0xeb) a (d)word displacement jump. */
10246 fragP
->fr_fix
+= size
;
10247 fix_new (fragP
, old_fr_fix
, size
,
10249 fragP
->fr_offset
, 1,
10255 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
10257 /* Negate the condition, and branch past an
10258 unconditional jump. */
10261 /* Insert an unconditional jump. */
10263 /* We added two extra opcode bytes, and have a two byte
10265 fragP
->fr_fix
+= 2 + 2;
10266 fix_new (fragP
, old_fr_fix
+ 2, 2,
10268 fragP
->fr_offset
, 1,
10272 /* Fall through. */
10275 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
10279 fragP
->fr_fix
+= 1;
10280 fixP
= fix_new (fragP
, old_fr_fix
, 1,
10282 fragP
->fr_offset
, 1,
10283 BFD_RELOC_8_PCREL
);
10284 fixP
->fx_signed
= 1;
10288 /* This changes the byte-displacement jump 0x7N
10289 to the (d)word-displacement jump 0x0f,0x8N. */
10290 opcode
[1] = opcode
[0] + 0x10;
10291 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10292 /* We've added an opcode byte. */
10293 fragP
->fr_fix
+= 1 + size
;
10294 fix_new (fragP
, old_fr_fix
+ 1, size
,
10296 fragP
->fr_offset
, 1,
10301 BAD_CASE (fragP
->fr_subtype
);
10305 return fragP
->fr_fix
- old_fr_fix
;
10308 /* Guess size depending on current relax state. Initially the relax
10309 state will correspond to a short jump and we return 1, because
10310 the variable part of the frag (the branch offset) is one byte
10311 long. However, we can relax a section more than once and in that
10312 case we must either set fr_subtype back to the unrelaxed state,
10313 or return the value for the appropriate branch. */
10314 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
10317 /* Called after relax() is finished.
10319 In: Address of frag.
10320 fr_type == rs_machine_dependent.
10321 fr_subtype is what the address relaxed to.
10323 Out: Any fixSs and constants are set up.
10324 Caller will turn frag into a ".space 0". */
10327 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
10330 unsigned char *opcode
;
10331 unsigned char *where_to_put_displacement
= NULL
;
10332 offsetT target_address
;
10333 offsetT opcode_address
;
10334 unsigned int extension
= 0;
10335 offsetT displacement_from_opcode_start
;
10337 opcode
= (unsigned char *) fragP
->fr_opcode
;
10339 /* Address we want to reach in file space. */
10340 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
10342 /* Address opcode resides at in file space. */
10343 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
10345 /* Displacement from opcode start to fill into instruction. */
10346 displacement_from_opcode_start
= target_address
- opcode_address
;
10348 if ((fragP
->fr_subtype
& BIG
) == 0)
10350 /* Don't have to change opcode. */
10351 extension
= 1; /* 1 opcode + 1 displacement */
10352 where_to_put_displacement
= &opcode
[1];
10356 if (no_cond_jump_promotion
10357 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
10358 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
10359 _("long jump required"));
10361 switch (fragP
->fr_subtype
)
10363 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10364 extension
= 4; /* 1 opcode + 4 displacement */
10366 where_to_put_displacement
= &opcode
[1];
10369 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10370 extension
= 2; /* 1 opcode + 2 displacement */
10372 where_to_put_displacement
= &opcode
[1];
10375 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10376 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10377 extension
= 5; /* 2 opcode + 4 displacement */
10378 opcode
[1] = opcode
[0] + 0x10;
10379 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10380 where_to_put_displacement
= &opcode
[2];
10383 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10384 extension
= 3; /* 2 opcode + 2 displacement */
10385 opcode
[1] = opcode
[0] + 0x10;
10386 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10387 where_to_put_displacement
= &opcode
[2];
10390 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10395 where_to_put_displacement
= &opcode
[3];
10399 BAD_CASE (fragP
->fr_subtype
);
10404 /* If size if less then four we are sure that the operand fits,
10405 but if it's 4, then it could be that the displacement is larger
10407 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10409 && ((addressT
) (displacement_from_opcode_start
- extension
10410 + ((addressT
) 1 << 31))
10411 > (((addressT
) 2 << 31) - 1)))
10413 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10414 _("jump target out of range"));
10415 /* Make us emit 0. */
10416 displacement_from_opcode_start
= extension
;
10418 /* Now put displacement after opcode. */
10419 md_number_to_chars ((char *) where_to_put_displacement
,
10420 (valueT
) (displacement_from_opcode_start
- extension
),
10421 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10422 fragP
->fr_fix
+= extension
;
10425 /* Apply a fixup (fixP) to segment data, once it has been determined
10426 by our caller that we have all the info we need to fix it up.
10428 Parameter valP is the pointer to the value of the bits.
10430 On the 386, immediates, displacements, and data pointers are all in
10431 the same (little-endian) format, so we don't need to care about which
10432 we are handling. */
10435 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10437 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10438 valueT value
= *valP
;
10440 #if !defined (TE_Mach)
10441 if (fixP
->fx_pcrel
)
10443 switch (fixP
->fx_r_type
)
10449 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10452 case BFD_RELOC_X86_64_32S
:
10453 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10456 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10459 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10464 if (fixP
->fx_addsy
!= NULL
10465 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10466 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10467 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10468 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10469 && !use_rela_relocations
)
10471 /* This is a hack. There should be a better way to handle this.
10472 This covers for the fact that bfd_install_relocation will
10473 subtract the current location (for partial_inplace, PC relative
10474 relocations); see more below. */
10478 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10481 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10483 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10486 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10488 if ((sym_seg
== seg
10489 || (symbol_section_p (fixP
->fx_addsy
)
10490 && sym_seg
!= absolute_section
))
10491 && !generic_force_reloc (fixP
))
10493 /* Yes, we add the values in twice. This is because
10494 bfd_install_relocation subtracts them out again. I think
10495 bfd_install_relocation is broken, but I don't dare change
10497 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10501 #if defined (OBJ_COFF) && defined (TE_PE)
10502 /* For some reason, the PE format does not store a
10503 section address offset for a PC relative symbol. */
10504 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10505 || S_IS_WEAK (fixP
->fx_addsy
))
10506 value
+= md_pcrel_from (fixP
);
10509 #if defined (OBJ_COFF) && defined (TE_PE)
10510 if (fixP
->fx_addsy
!= NULL
10511 && S_IS_WEAK (fixP
->fx_addsy
)
10512 /* PR 16858: Do not modify weak function references. */
10513 && ! fixP
->fx_pcrel
)
10515 #if !defined (TE_PEP)
10516 /* For x86 PE weak function symbols are neither PC-relative
10517 nor do they set S_IS_FUNCTION. So the only reliable way
10518 to detect them is to check the flags of their containing
10520 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10521 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10525 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10529 /* Fix a few things - the dynamic linker expects certain values here,
10530 and we must not disappoint it. */
10531 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10532 if (IS_ELF
&& fixP
->fx_addsy
)
10533 switch (fixP
->fx_r_type
)
10535 case BFD_RELOC_386_PLT32
:
10536 case BFD_RELOC_X86_64_PLT32
:
10537 /* Make the jump instruction point to the address of the operand. At
10538 runtime we merely add the offset to the actual PLT entry. */
10542 case BFD_RELOC_386_TLS_GD
:
10543 case BFD_RELOC_386_TLS_LDM
:
10544 case BFD_RELOC_386_TLS_IE_32
:
10545 case BFD_RELOC_386_TLS_IE
:
10546 case BFD_RELOC_386_TLS_GOTIE
:
10547 case BFD_RELOC_386_TLS_GOTDESC
:
10548 case BFD_RELOC_X86_64_TLSGD
:
10549 case BFD_RELOC_X86_64_TLSLD
:
10550 case BFD_RELOC_X86_64_GOTTPOFF
:
10551 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10552 value
= 0; /* Fully resolved at runtime. No addend. */
10554 case BFD_RELOC_386_TLS_LE
:
10555 case BFD_RELOC_386_TLS_LDO_32
:
10556 case BFD_RELOC_386_TLS_LE_32
:
10557 case BFD_RELOC_X86_64_DTPOFF32
:
10558 case BFD_RELOC_X86_64_DTPOFF64
:
10559 case BFD_RELOC_X86_64_TPOFF32
:
10560 case BFD_RELOC_X86_64_TPOFF64
:
10561 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10564 case BFD_RELOC_386_TLS_DESC_CALL
:
10565 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10566 value
= 0; /* Fully resolved at runtime. No addend. */
10567 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10571 case BFD_RELOC_VTABLE_INHERIT
:
10572 case BFD_RELOC_VTABLE_ENTRY
:
10579 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10581 #endif /* !defined (TE_Mach) */
10583 /* Are we finished with this relocation now? */
10584 if (fixP
->fx_addsy
== NULL
)
10586 #if defined (OBJ_COFF) && defined (TE_PE)
10587 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10590 /* Remember value for tc_gen_reloc. */
10591 fixP
->fx_addnumber
= value
;
10592 /* Clear out the frag for now. */
10596 else if (use_rela_relocations
)
10598 fixP
->fx_no_overflow
= 1;
10599 /* Remember value for tc_gen_reloc. */
10600 fixP
->fx_addnumber
= value
;
10604 md_number_to_chars (p
, value
, fixP
->fx_size
);
10608 md_atof (int type
, char *litP
, int *sizeP
)
10610 /* This outputs the LITTLENUMs in REVERSE order;
10611 in accord with the bigendian 386. */
10612 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10615 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10618 output_invalid (int c
)
10621 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10624 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10625 "(0x%x)", (unsigned char) c
);
10626 return output_invalid_buf
;
10629 /* REG_STRING starts *before* REGISTER_PREFIX. */
10631 static const reg_entry
*
10632 parse_real_register (char *reg_string
, char **end_op
)
10634 char *s
= reg_string
;
10636 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10637 const reg_entry
*r
;
10639 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10640 if (*s
== REGISTER_PREFIX
)
10643 if (is_space_char (*s
))
10646 p
= reg_name_given
;
10647 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10649 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10650 return (const reg_entry
*) NULL
;
10654 /* For naked regs, make sure that we are not dealing with an identifier.
10655 This prevents confusing an identifier like `eax_var' with register
10657 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10658 return (const reg_entry
*) NULL
;
10662 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10664 /* Handle floating point regs, allowing spaces in the (i) part. */
10665 if (r
== i386_regtab
/* %st is first entry of table */)
10667 if (!cpu_arch_flags
.bitfield
.cpu8087
10668 && !cpu_arch_flags
.bitfield
.cpu287
10669 && !cpu_arch_flags
.bitfield
.cpu387
)
10670 return (const reg_entry
*) NULL
;
10672 if (is_space_char (*s
))
10677 if (is_space_char (*s
))
10679 if (*s
>= '0' && *s
<= '7')
10681 int fpr
= *s
- '0';
10683 if (is_space_char (*s
))
10688 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10693 /* We have "%st(" then garbage. */
10694 return (const reg_entry
*) NULL
;
10698 if (r
== NULL
|| allow_pseudo_reg
)
10701 if (operand_type_all_zero (&r
->reg_type
))
10702 return (const reg_entry
*) NULL
;
10704 if ((r
->reg_type
.bitfield
.dword
10705 || r
->reg_type
.bitfield
.sreg3
10706 || r
->reg_type
.bitfield
.control
10707 || r
->reg_type
.bitfield
.debug
10708 || r
->reg_type
.bitfield
.test
)
10709 && !cpu_arch_flags
.bitfield
.cpui386
)
10710 return (const reg_entry
*) NULL
;
10712 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10713 return (const reg_entry
*) NULL
;
10715 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10717 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10718 return (const reg_entry
*) NULL
;
10720 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10722 if (r
->reg_type
.bitfield
.ymmword
)
10723 return (const reg_entry
*) NULL
;
10725 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10726 return (const reg_entry
*) NULL
;
10730 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10731 return (const reg_entry
*) NULL
;
10733 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10734 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
10735 return (const reg_entry
*) NULL
;
10737 /* Upper 16 vector registers are only available with VREX in 64bit
10738 mode, and require EVEX encoding. */
10739 if (r
->reg_flags
& RegVRex
)
10741 if (!cpu_arch_flags
.bitfield
.cpuavx512f
10742 || flag_code
!= CODE_64BIT
)
10743 return (const reg_entry
*) NULL
;
10745 i
.vec_encoding
= vex_encoding_evex
;
10748 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10749 && (!cpu_arch_flags
.bitfield
.cpulm
|| !r
->reg_type
.bitfield
.control
)
10750 && flag_code
!= CODE_64BIT
)
10751 return (const reg_entry
*) NULL
;
10753 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10754 return (const reg_entry
*) NULL
;
10759 /* REG_STRING starts *before* REGISTER_PREFIX. */
10761 static const reg_entry
*
10762 parse_register (char *reg_string
, char **end_op
)
10764 const reg_entry
*r
;
10766 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10767 r
= parse_real_register (reg_string
, end_op
);
10772 char *save
= input_line_pointer
;
10776 input_line_pointer
= reg_string
;
10777 c
= get_symbol_name (®_string
);
10778 symbolP
= symbol_find (reg_string
);
10779 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10781 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10783 know (e
->X_op
== O_register
);
10784 know (e
->X_add_number
>= 0
10785 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10786 r
= i386_regtab
+ e
->X_add_number
;
10787 if ((r
->reg_flags
& RegVRex
))
10788 i
.vec_encoding
= vex_encoding_evex
;
10789 *end_op
= input_line_pointer
;
10791 *input_line_pointer
= c
;
10792 input_line_pointer
= save
;
10798 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10800 const reg_entry
*r
;
10801 char *end
= input_line_pointer
;
10804 r
= parse_register (name
, &input_line_pointer
);
10805 if (r
&& end
<= input_line_pointer
)
10807 *nextcharP
= *input_line_pointer
;
10808 *input_line_pointer
= 0;
10809 e
->X_op
= O_register
;
10810 e
->X_add_number
= r
- i386_regtab
;
10813 input_line_pointer
= end
;
10815 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
10819 md_operand (expressionS
*e
)
10822 const reg_entry
*r
;
10824 switch (*input_line_pointer
)
10826 case REGISTER_PREFIX
:
10827 r
= parse_real_register (input_line_pointer
, &end
);
10830 e
->X_op
= O_register
;
10831 e
->X_add_number
= r
- i386_regtab
;
10832 input_line_pointer
= end
;
10837 gas_assert (intel_syntax
);
10838 end
= input_line_pointer
++;
10840 if (*input_line_pointer
== ']')
10842 ++input_line_pointer
;
10843 e
->X_op_symbol
= make_expr_symbol (e
);
10844 e
->X_add_symbol
= NULL
;
10845 e
->X_add_number
= 0;
10850 e
->X_op
= O_absent
;
10851 input_line_pointer
= end
;
10858 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10859 const char *md_shortopts
= "kVQ:sqnO::";
10861 const char *md_shortopts
= "qnO::";
10864 #define OPTION_32 (OPTION_MD_BASE + 0)
10865 #define OPTION_64 (OPTION_MD_BASE + 1)
10866 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10867 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10868 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10869 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10870 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10871 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10872 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10873 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10874 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10875 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10876 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10877 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10878 #define OPTION_X32 (OPTION_MD_BASE + 14)
10879 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10880 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10881 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10882 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10883 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10884 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10885 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10886 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10887 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10888 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10889 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
10890 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
10892 struct option md_longopts
[] =
10894 {"32", no_argument
, NULL
, OPTION_32
},
10895 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10896 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10897 {"64", no_argument
, NULL
, OPTION_64
},
10899 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10900 {"x32", no_argument
, NULL
, OPTION_X32
},
10901 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10902 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
10904 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
10905 {"march", required_argument
, NULL
, OPTION_MARCH
},
10906 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10907 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
10908 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
10909 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
10910 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
10911 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
10912 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
10913 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
10914 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
10915 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
10916 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
10917 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
10918 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
10919 # if defined (TE_PE) || defined (TE_PEP)
10920 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
10922 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
10923 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
10924 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
10925 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
10926 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
10927 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
10928 {NULL
, no_argument
, NULL
, 0}
10930 size_t md_longopts_size
= sizeof (md_longopts
);
10933 md_parse_option (int c
, const char *arg
)
10936 char *arch
, *next
, *saved
;
10941 optimize_align_code
= 0;
10945 quiet_warnings
= 1;
10948 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10949 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10950 should be emitted or not. FIXME: Not implemented. */
10954 /* -V: SVR4 argument to print version ID. */
10956 print_version_id ();
10959 /* -k: Ignore for FreeBSD compatibility. */
10964 /* -s: On i386 Solaris, this tells the native assembler to use
10965 .stab instead of .stab.excl. We always use .stab anyhow. */
10968 case OPTION_MSHARED
:
10972 case OPTION_X86_USED_NOTE
:
10973 if (strcasecmp (arg
, "yes") == 0)
10975 else if (strcasecmp (arg
, "no") == 0)
10978 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
10983 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10984 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10987 const char **list
, **l
;
10989 list
= bfd_target_list ();
10990 for (l
= list
; *l
!= NULL
; l
++)
10991 if (CONST_STRNEQ (*l
, "elf64-x86-64")
10992 || strcmp (*l
, "coff-x86-64") == 0
10993 || strcmp (*l
, "pe-x86-64") == 0
10994 || strcmp (*l
, "pei-x86-64") == 0
10995 || strcmp (*l
, "mach-o-x86-64") == 0)
10997 default_arch
= "x86_64";
11001 as_fatal (_("no compiled in support for x86_64"));
11007 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11011 const char **list
, **l
;
11013 list
= bfd_target_list ();
11014 for (l
= list
; *l
!= NULL
; l
++)
11015 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
11017 default_arch
= "x86_64:32";
11021 as_fatal (_("no compiled in support for 32bit x86_64"));
11025 as_fatal (_("32bit x86_64 is only supported for ELF"));
11030 default_arch
= "i386";
11033 case OPTION_DIVIDE
:
11034 #ifdef SVR4_COMMENT_CHARS
11039 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
11041 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
11045 i386_comment_chars
= n
;
11051 saved
= xstrdup (arg
);
11053 /* Allow -march=+nosse. */
11059 as_fatal (_("invalid -march= option: `%s'"), arg
);
11060 next
= strchr (arch
, '+');
11063 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11065 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
11068 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11071 cpu_arch_name
= cpu_arch
[j
].name
;
11072 cpu_sub_arch_name
= NULL
;
11073 cpu_arch_flags
= cpu_arch
[j
].flags
;
11074 cpu_arch_isa
= cpu_arch
[j
].type
;
11075 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
11076 if (!cpu_arch_tune_set
)
11078 cpu_arch_tune
= cpu_arch_isa
;
11079 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11083 else if (*cpu_arch
[j
].name
== '.'
11084 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
11086 /* ISA extension. */
11087 i386_cpu_flags flags
;
11089 flags
= cpu_flags_or (cpu_arch_flags
,
11090 cpu_arch
[j
].flags
);
11092 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11094 if (cpu_sub_arch_name
)
11096 char *name
= cpu_sub_arch_name
;
11097 cpu_sub_arch_name
= concat (name
,
11099 (const char *) NULL
);
11103 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
11104 cpu_arch_flags
= flags
;
11105 cpu_arch_isa_flags
= flags
;
11109 = cpu_flags_or (cpu_arch_isa_flags
,
11110 cpu_arch
[j
].flags
);
11115 if (j
>= ARRAY_SIZE (cpu_arch
))
11117 /* Disable an ISA extension. */
11118 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11119 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
11121 i386_cpu_flags flags
;
11123 flags
= cpu_flags_and_not (cpu_arch_flags
,
11124 cpu_noarch
[j
].flags
);
11125 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11127 if (cpu_sub_arch_name
)
11129 char *name
= cpu_sub_arch_name
;
11130 cpu_sub_arch_name
= concat (arch
,
11131 (const char *) NULL
);
11135 cpu_sub_arch_name
= xstrdup (arch
);
11136 cpu_arch_flags
= flags
;
11137 cpu_arch_isa_flags
= flags
;
11142 if (j
>= ARRAY_SIZE (cpu_noarch
))
11143 j
= ARRAY_SIZE (cpu_arch
);
11146 if (j
>= ARRAY_SIZE (cpu_arch
))
11147 as_fatal (_("invalid -march= option: `%s'"), arg
);
11151 while (next
!= NULL
);
11157 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11158 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11160 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
11162 cpu_arch_tune_set
= 1;
11163 cpu_arch_tune
= cpu_arch
[j
].type
;
11164 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
11168 if (j
>= ARRAY_SIZE (cpu_arch
))
11169 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11172 case OPTION_MMNEMONIC
:
11173 if (strcasecmp (arg
, "att") == 0)
11174 intel_mnemonic
= 0;
11175 else if (strcasecmp (arg
, "intel") == 0)
11176 intel_mnemonic
= 1;
11178 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
11181 case OPTION_MSYNTAX
:
11182 if (strcasecmp (arg
, "att") == 0)
11184 else if (strcasecmp (arg
, "intel") == 0)
11187 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
11190 case OPTION_MINDEX_REG
:
11191 allow_index_reg
= 1;
11194 case OPTION_MNAKED_REG
:
11195 allow_naked_reg
= 1;
11198 case OPTION_MSSE2AVX
:
11202 case OPTION_MSSE_CHECK
:
11203 if (strcasecmp (arg
, "error") == 0)
11204 sse_check
= check_error
;
11205 else if (strcasecmp (arg
, "warning") == 0)
11206 sse_check
= check_warning
;
11207 else if (strcasecmp (arg
, "none") == 0)
11208 sse_check
= check_none
;
11210 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
11213 case OPTION_MOPERAND_CHECK
:
11214 if (strcasecmp (arg
, "error") == 0)
11215 operand_check
= check_error
;
11216 else if (strcasecmp (arg
, "warning") == 0)
11217 operand_check
= check_warning
;
11218 else if (strcasecmp (arg
, "none") == 0)
11219 operand_check
= check_none
;
11221 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
11224 case OPTION_MAVXSCALAR
:
11225 if (strcasecmp (arg
, "128") == 0)
11226 avxscalar
= vex128
;
11227 else if (strcasecmp (arg
, "256") == 0)
11228 avxscalar
= vex256
;
11230 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
11233 case OPTION_MVEXWIG
:
11234 if (strcmp (arg
, "0") == 0)
11236 else if (strcmp (arg
, "1") == 0)
11239 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
11242 case OPTION_MADD_BND_PREFIX
:
11243 add_bnd_prefix
= 1;
11246 case OPTION_MEVEXLIG
:
11247 if (strcmp (arg
, "128") == 0)
11248 evexlig
= evexl128
;
11249 else if (strcmp (arg
, "256") == 0)
11250 evexlig
= evexl256
;
11251 else if (strcmp (arg
, "512") == 0)
11252 evexlig
= evexl512
;
11254 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
11257 case OPTION_MEVEXRCIG
:
11258 if (strcmp (arg
, "rne") == 0)
11260 else if (strcmp (arg
, "rd") == 0)
11262 else if (strcmp (arg
, "ru") == 0)
11264 else if (strcmp (arg
, "rz") == 0)
11267 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
11270 case OPTION_MEVEXWIG
:
11271 if (strcmp (arg
, "0") == 0)
11273 else if (strcmp (arg
, "1") == 0)
11276 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
11279 # if defined (TE_PE) || defined (TE_PEP)
11280 case OPTION_MBIG_OBJ
:
11285 case OPTION_MOMIT_LOCK_PREFIX
:
11286 if (strcasecmp (arg
, "yes") == 0)
11287 omit_lock_prefix
= 1;
11288 else if (strcasecmp (arg
, "no") == 0)
11289 omit_lock_prefix
= 0;
11291 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
11294 case OPTION_MFENCE_AS_LOCK_ADD
:
11295 if (strcasecmp (arg
, "yes") == 0)
11297 else if (strcasecmp (arg
, "no") == 0)
11300 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
11303 case OPTION_MRELAX_RELOCATIONS
:
11304 if (strcasecmp (arg
, "yes") == 0)
11305 generate_relax_relocations
= 1;
11306 else if (strcasecmp (arg
, "no") == 0)
11307 generate_relax_relocations
= 0;
11309 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
11312 case OPTION_MAMD64
:
11316 case OPTION_MINTEL64
:
11324 /* Turn off -Os. */
11325 optimize_for_space
= 0;
11327 else if (*arg
== 's')
11329 optimize_for_space
= 1;
11330 /* Turn on all encoding optimizations. */
11335 optimize
= atoi (arg
);
11336 /* Turn off -Os. */
11337 optimize_for_space
= 0;
11347 #define MESSAGE_TEMPLATE \
11351 output_message (FILE *stream
, char *p
, char *message
, char *start
,
11352 int *left_p
, const char *name
, int len
)
11354 int size
= sizeof (MESSAGE_TEMPLATE
);
11355 int left
= *left_p
;
11357 /* Reserve 2 spaces for ", " or ",\0" */
11360 /* Check if there is any room. */
11368 p
= mempcpy (p
, name
, len
);
11372 /* Output the current message now and start a new one. */
11375 fprintf (stream
, "%s\n", message
);
11377 left
= size
- (start
- message
) - len
- 2;
11379 gas_assert (left
>= 0);
11381 p
= mempcpy (p
, name
, len
);
11389 show_arch (FILE *stream
, int ext
, int check
)
11391 static char message
[] = MESSAGE_TEMPLATE
;
11392 char *start
= message
+ 27;
11394 int size
= sizeof (MESSAGE_TEMPLATE
);
11401 left
= size
- (start
- message
);
11402 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11404 /* Should it be skipped? */
11405 if (cpu_arch
[j
].skip
)
11408 name
= cpu_arch
[j
].name
;
11409 len
= cpu_arch
[j
].len
;
11412 /* It is an extension. Skip if we aren't asked to show it. */
11423 /* It is an processor. Skip if we show only extension. */
11426 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11428 /* It is an impossible processor - skip. */
11432 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11435 /* Display disabled extensions. */
11437 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11439 name
= cpu_noarch
[j
].name
;
11440 len
= cpu_noarch
[j
].len
;
11441 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11446 fprintf (stream
, "%s\n", message
);
11450 md_show_usage (FILE *stream
)
11452 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11453 fprintf (stream
, _("\
11455 -V print assembler version number\n\
11458 fprintf (stream
, _("\
11459 -n Do not optimize code alignment\n\
11460 -q quieten some warnings\n"));
11461 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11462 fprintf (stream
, _("\
11465 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11466 || defined (TE_PE) || defined (TE_PEP))
11467 fprintf (stream
, _("\
11468 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11470 #ifdef SVR4_COMMENT_CHARS
11471 fprintf (stream
, _("\
11472 --divide do not treat `/' as a comment character\n"));
11474 fprintf (stream
, _("\
11475 --divide ignored\n"));
11477 fprintf (stream
, _("\
11478 -march=CPU[,+EXTENSION...]\n\
11479 generate code for CPU and EXTENSION, CPU is one of:\n"));
11480 show_arch (stream
, 0, 1);
11481 fprintf (stream
, _("\
11482 EXTENSION is combination of:\n"));
11483 show_arch (stream
, 1, 0);
11484 fprintf (stream
, _("\
11485 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11486 show_arch (stream
, 0, 0);
11487 fprintf (stream
, _("\
11488 -msse2avx encode SSE instructions with VEX prefix\n"));
11489 fprintf (stream
, _("\
11490 -msse-check=[none|error|warning] (default: warning)\n\
11491 check SSE instructions\n"));
11492 fprintf (stream
, _("\
11493 -moperand-check=[none|error|warning] (default: warning)\n\
11494 check operand combinations for validity\n"));
11495 fprintf (stream
, _("\
11496 -mavxscalar=[128|256] (default: 128)\n\
11497 encode scalar AVX instructions with specific vector\n\
11499 fprintf (stream
, _("\
11500 -mvexwig=[0|1] (default: 0)\n\
11501 encode VEX instructions with specific VEX.W value\n\
11502 for VEX.W bit ignored instructions\n"));
11503 fprintf (stream
, _("\
11504 -mevexlig=[128|256|512] (default: 128)\n\
11505 encode scalar EVEX instructions with specific vector\n\
11507 fprintf (stream
, _("\
11508 -mevexwig=[0|1] (default: 0)\n\
11509 encode EVEX instructions with specific EVEX.W value\n\
11510 for EVEX.W bit ignored instructions\n"));
11511 fprintf (stream
, _("\
11512 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11513 encode EVEX instructions with specific EVEX.RC value\n\
11514 for SAE-only ignored instructions\n"));
11515 fprintf (stream
, _("\
11516 -mmnemonic=[att|intel] "));
11517 if (SYSV386_COMPAT
)
11518 fprintf (stream
, _("(default: att)\n"));
11520 fprintf (stream
, _("(default: intel)\n"));
11521 fprintf (stream
, _("\
11522 use AT&T/Intel mnemonic\n"));
11523 fprintf (stream
, _("\
11524 -msyntax=[att|intel] (default: att)\n\
11525 use AT&T/Intel syntax\n"));
11526 fprintf (stream
, _("\
11527 -mindex-reg support pseudo index registers\n"));
11528 fprintf (stream
, _("\
11529 -mnaked-reg don't require `%%' prefix for registers\n"));
11530 fprintf (stream
, _("\
11531 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11532 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11533 fprintf (stream
, _("\
11534 -mshared disable branch optimization for shared code\n"));
11535 fprintf (stream
, _("\
11536 -mx86-used-note=[no|yes] "));
11537 if (DEFAULT_X86_USED_NOTE
)
11538 fprintf (stream
, _("(default: yes)\n"));
11540 fprintf (stream
, _("(default: no)\n"));
11541 fprintf (stream
, _("\
11542 generate x86 used ISA and feature properties\n"));
11544 #if defined (TE_PE) || defined (TE_PEP)
11545 fprintf (stream
, _("\
11546 -mbig-obj generate big object files\n"));
11548 fprintf (stream
, _("\
11549 -momit-lock-prefix=[no|yes] (default: no)\n\
11550 strip all lock prefixes\n"));
11551 fprintf (stream
, _("\
11552 -mfence-as-lock-add=[no|yes] (default: no)\n\
11553 encode lfence, mfence and sfence as\n\
11554 lock addl $0x0, (%%{re}sp)\n"));
11555 fprintf (stream
, _("\
11556 -mrelax-relocations=[no|yes] "));
11557 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
11558 fprintf (stream
, _("(default: yes)\n"));
11560 fprintf (stream
, _("(default: no)\n"));
11561 fprintf (stream
, _("\
11562 generate relax relocations\n"));
11563 fprintf (stream
, _("\
11564 -mamd64 accept only AMD64 ISA [default]\n"));
11565 fprintf (stream
, _("\
11566 -mintel64 accept only Intel64 ISA\n"));
11569 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11570 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11571 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11573 /* Pick the target format to use. */
11576 i386_target_format (void)
11578 if (!strncmp (default_arch
, "x86_64", 6))
11580 update_code_flag (CODE_64BIT
, 1);
11581 if (default_arch
[6] == '\0')
11582 x86_elf_abi
= X86_64_ABI
;
11584 x86_elf_abi
= X86_64_X32_ABI
;
11586 else if (!strcmp (default_arch
, "i386"))
11587 update_code_flag (CODE_32BIT
, 1);
11588 else if (!strcmp (default_arch
, "iamcu"))
11590 update_code_flag (CODE_32BIT
, 1);
11591 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11593 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11594 cpu_arch_name
= "iamcu";
11595 cpu_sub_arch_name
= NULL
;
11596 cpu_arch_flags
= iamcu_flags
;
11597 cpu_arch_isa
= PROCESSOR_IAMCU
;
11598 cpu_arch_isa_flags
= iamcu_flags
;
11599 if (!cpu_arch_tune_set
)
11601 cpu_arch_tune
= cpu_arch_isa
;
11602 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11605 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11606 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11610 as_fatal (_("unknown architecture"));
11612 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11613 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11614 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11615 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11617 switch (OUTPUT_FLAVOR
)
11619 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11620 case bfd_target_aout_flavour
:
11621 return AOUT_TARGET_FORMAT
;
11623 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11624 # if defined (TE_PE) || defined (TE_PEP)
11625 case bfd_target_coff_flavour
:
11626 if (flag_code
== CODE_64BIT
)
11627 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11630 # elif defined (TE_GO32)
11631 case bfd_target_coff_flavour
:
11632 return "coff-go32";
11634 case bfd_target_coff_flavour
:
11635 return "coff-i386";
11638 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11639 case bfd_target_elf_flavour
:
11641 const char *format
;
11643 switch (x86_elf_abi
)
11646 format
= ELF_TARGET_FORMAT
;
11649 use_rela_relocations
= 1;
11651 format
= ELF_TARGET_FORMAT64
;
11653 case X86_64_X32_ABI
:
11654 use_rela_relocations
= 1;
11656 disallow_64bit_reloc
= 1;
11657 format
= ELF_TARGET_FORMAT32
;
11660 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11662 if (x86_elf_abi
!= X86_64_ABI
)
11663 as_fatal (_("Intel L1OM is 64bit only"));
11664 return ELF_TARGET_L1OM_FORMAT
;
11666 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11668 if (x86_elf_abi
!= X86_64_ABI
)
11669 as_fatal (_("Intel K1OM is 64bit only"));
11670 return ELF_TARGET_K1OM_FORMAT
;
11672 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11674 if (x86_elf_abi
!= I386_ABI
)
11675 as_fatal (_("Intel MCU is 32bit only"));
11676 return ELF_TARGET_IAMCU_FORMAT
;
11682 #if defined (OBJ_MACH_O)
11683 case bfd_target_mach_o_flavour
:
11684 if (flag_code
== CODE_64BIT
)
11686 use_rela_relocations
= 1;
11688 return "mach-o-x86-64";
11691 return "mach-o-i386";
11699 #endif /* OBJ_MAYBE_ more than one */
11702 md_undefined_symbol (char *name
)
11704 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11705 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11706 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11707 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11711 if (symbol_find (name
))
11712 as_bad (_("GOT already in symbol table"));
11713 GOT_symbol
= symbol_new (name
, undefined_section
,
11714 (valueT
) 0, &zero_address_frag
);
11721 /* Round up a section size to the appropriate boundary. */
11724 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11726 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11727 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11729 /* For a.out, force the section size to be aligned. If we don't do
11730 this, BFD will align it for us, but it will not write out the
11731 final bytes of the section. This may be a bug in BFD, but it is
11732 easier to fix it here since that is how the other a.out targets
11736 align
= bfd_get_section_alignment (stdoutput
, segment
);
11737 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11744 /* On the i386, PC-relative offsets are relative to the start of the
11745 next instruction. That is, the address of the offset, plus its
11746 size, since the offset is always the last part of the insn. */
11749 md_pcrel_from (fixS
*fixP
)
11751 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11757 s_bss (int ignore ATTRIBUTE_UNUSED
)
11761 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11763 obj_elf_section_change_hook ();
11765 temp
= get_absolute_expression ();
11766 subseg_set (bss_section
, (subsegT
) temp
);
11767 demand_empty_rest_of_line ();
11773 i386_validate_fix (fixS
*fixp
)
11775 if (fixp
->fx_subsy
)
11777 if (fixp
->fx_subsy
== GOT_symbol
)
11779 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11783 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11784 if (fixp
->fx_tcbit2
)
11785 fixp
->fx_r_type
= (fixp
->fx_tcbit
11786 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11787 : BFD_RELOC_X86_64_GOTPCRELX
);
11790 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11795 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11797 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11799 fixp
->fx_subsy
= 0;
11802 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11803 else if (!object_64bit
)
11805 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11806 && fixp
->fx_tcbit2
)
11807 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11813 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11816 bfd_reloc_code_real_type code
;
11818 switch (fixp
->fx_r_type
)
11820 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11821 case BFD_RELOC_SIZE32
:
11822 case BFD_RELOC_SIZE64
:
11823 if (S_IS_DEFINED (fixp
->fx_addsy
)
11824 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
11826 /* Resolve size relocation against local symbol to size of
11827 the symbol plus addend. */
11828 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
11829 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
11830 && !fits_in_unsigned_long (value
))
11831 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11832 _("symbol size computation overflow"));
11833 fixp
->fx_addsy
= NULL
;
11834 fixp
->fx_subsy
= NULL
;
11835 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
11839 /* Fall through. */
11841 case BFD_RELOC_X86_64_PLT32
:
11842 case BFD_RELOC_X86_64_GOT32
:
11843 case BFD_RELOC_X86_64_GOTPCREL
:
11844 case BFD_RELOC_X86_64_GOTPCRELX
:
11845 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11846 case BFD_RELOC_386_PLT32
:
11847 case BFD_RELOC_386_GOT32
:
11848 case BFD_RELOC_386_GOT32X
:
11849 case BFD_RELOC_386_GOTOFF
:
11850 case BFD_RELOC_386_GOTPC
:
11851 case BFD_RELOC_386_TLS_GD
:
11852 case BFD_RELOC_386_TLS_LDM
:
11853 case BFD_RELOC_386_TLS_LDO_32
:
11854 case BFD_RELOC_386_TLS_IE_32
:
11855 case BFD_RELOC_386_TLS_IE
:
11856 case BFD_RELOC_386_TLS_GOTIE
:
11857 case BFD_RELOC_386_TLS_LE_32
:
11858 case BFD_RELOC_386_TLS_LE
:
11859 case BFD_RELOC_386_TLS_GOTDESC
:
11860 case BFD_RELOC_386_TLS_DESC_CALL
:
11861 case BFD_RELOC_X86_64_TLSGD
:
11862 case BFD_RELOC_X86_64_TLSLD
:
11863 case BFD_RELOC_X86_64_DTPOFF32
:
11864 case BFD_RELOC_X86_64_DTPOFF64
:
11865 case BFD_RELOC_X86_64_GOTTPOFF
:
11866 case BFD_RELOC_X86_64_TPOFF32
:
11867 case BFD_RELOC_X86_64_TPOFF64
:
11868 case BFD_RELOC_X86_64_GOTOFF64
:
11869 case BFD_RELOC_X86_64_GOTPC32
:
11870 case BFD_RELOC_X86_64_GOT64
:
11871 case BFD_RELOC_X86_64_GOTPCREL64
:
11872 case BFD_RELOC_X86_64_GOTPC64
:
11873 case BFD_RELOC_X86_64_GOTPLT64
:
11874 case BFD_RELOC_X86_64_PLTOFF64
:
11875 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11876 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11877 case BFD_RELOC_RVA
:
11878 case BFD_RELOC_VTABLE_ENTRY
:
11879 case BFD_RELOC_VTABLE_INHERIT
:
11881 case BFD_RELOC_32_SECREL
:
11883 code
= fixp
->fx_r_type
;
11885 case BFD_RELOC_X86_64_32S
:
11886 if (!fixp
->fx_pcrel
)
11888 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11889 code
= fixp
->fx_r_type
;
11892 /* Fall through. */
11894 if (fixp
->fx_pcrel
)
11896 switch (fixp
->fx_size
)
11899 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11900 _("can not do %d byte pc-relative relocation"),
11902 code
= BFD_RELOC_32_PCREL
;
11904 case 1: code
= BFD_RELOC_8_PCREL
; break;
11905 case 2: code
= BFD_RELOC_16_PCREL
; break;
11906 case 4: code
= BFD_RELOC_32_PCREL
; break;
11908 case 8: code
= BFD_RELOC_64_PCREL
; break;
11914 switch (fixp
->fx_size
)
11917 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11918 _("can not do %d byte relocation"),
11920 code
= BFD_RELOC_32
;
11922 case 1: code
= BFD_RELOC_8
; break;
11923 case 2: code
= BFD_RELOC_16
; break;
11924 case 4: code
= BFD_RELOC_32
; break;
11926 case 8: code
= BFD_RELOC_64
; break;
11933 if ((code
== BFD_RELOC_32
11934 || code
== BFD_RELOC_32_PCREL
11935 || code
== BFD_RELOC_X86_64_32S
)
11937 && fixp
->fx_addsy
== GOT_symbol
)
11940 code
= BFD_RELOC_386_GOTPC
;
11942 code
= BFD_RELOC_X86_64_GOTPC32
;
11944 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
11946 && fixp
->fx_addsy
== GOT_symbol
)
11948 code
= BFD_RELOC_X86_64_GOTPC64
;
11951 rel
= XNEW (arelent
);
11952 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
11953 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11955 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11957 if (!use_rela_relocations
)
11959 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11960 vtable entry to be used in the relocation's section offset. */
11961 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11962 rel
->address
= fixp
->fx_offset
;
11963 #if defined (OBJ_COFF) && defined (TE_PE)
11964 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
11965 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
11970 /* Use the rela in 64bit mode. */
11973 if (disallow_64bit_reloc
)
11976 case BFD_RELOC_X86_64_DTPOFF64
:
11977 case BFD_RELOC_X86_64_TPOFF64
:
11978 case BFD_RELOC_64_PCREL
:
11979 case BFD_RELOC_X86_64_GOTOFF64
:
11980 case BFD_RELOC_X86_64_GOT64
:
11981 case BFD_RELOC_X86_64_GOTPCREL64
:
11982 case BFD_RELOC_X86_64_GOTPC64
:
11983 case BFD_RELOC_X86_64_GOTPLT64
:
11984 case BFD_RELOC_X86_64_PLTOFF64
:
11985 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11986 _("cannot represent relocation type %s in x32 mode"),
11987 bfd_get_reloc_code_name (code
));
11993 if (!fixp
->fx_pcrel
)
11994 rel
->addend
= fixp
->fx_offset
;
11998 case BFD_RELOC_X86_64_PLT32
:
11999 case BFD_RELOC_X86_64_GOT32
:
12000 case BFD_RELOC_X86_64_GOTPCREL
:
12001 case BFD_RELOC_X86_64_GOTPCRELX
:
12002 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12003 case BFD_RELOC_X86_64_TLSGD
:
12004 case BFD_RELOC_X86_64_TLSLD
:
12005 case BFD_RELOC_X86_64_GOTTPOFF
:
12006 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12007 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12008 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
12011 rel
->addend
= (section
->vma
12013 + fixp
->fx_addnumber
12014 + md_pcrel_from (fixp
));
12019 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12020 if (rel
->howto
== NULL
)
12022 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12023 _("cannot represent relocation type %s"),
12024 bfd_get_reloc_code_name (code
));
12025 /* Set howto to a garbage value so that we can keep going. */
12026 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
12027 gas_assert (rel
->howto
!= NULL
);
12033 #include "tc-i386-intel.c"
12036 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
12038 int saved_naked_reg
;
12039 char saved_register_dot
;
12041 saved_naked_reg
= allow_naked_reg
;
12042 allow_naked_reg
= 1;
12043 saved_register_dot
= register_chars
['.'];
12044 register_chars
['.'] = '.';
12045 allow_pseudo_reg
= 1;
12046 expression_and_evaluate (exp
);
12047 allow_pseudo_reg
= 0;
12048 register_chars
['.'] = saved_register_dot
;
12049 allow_naked_reg
= saved_naked_reg
;
12051 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
12053 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
12055 exp
->X_op
= O_constant
;
12056 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
12057 .dw2_regnum
[flag_code
>> 1];
12060 exp
->X_op
= O_illegal
;
12065 tc_x86_frame_initial_instructions (void)
12067 static unsigned int sp_regno
[2];
12069 if (!sp_regno
[flag_code
>> 1])
12071 char *saved_input
= input_line_pointer
;
12072 char sp
[][4] = {"esp", "rsp"};
12075 input_line_pointer
= sp
[flag_code
>> 1];
12076 tc_x86_parse_to_dw2regnum (&exp
);
12077 gas_assert (exp
.X_op
== O_constant
);
12078 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
12079 input_line_pointer
= saved_input
;
12082 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
12083 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
12087 x86_dwarf2_addr_size (void)
12089 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12090 if (x86_elf_abi
== X86_64_X32_ABI
)
12093 return bfd_arch_bits_per_address (stdoutput
) / 8;
12097 i386_elf_section_type (const char *str
, size_t len
)
12099 if (flag_code
== CODE_64BIT
12100 && len
== sizeof ("unwind") - 1
12101 && strncmp (str
, "unwind", 6) == 0)
12102 return SHT_X86_64_UNWIND
;
12109 i386_solaris_fix_up_eh_frame (segT sec
)
12111 if (flag_code
== CODE_64BIT
)
12112 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
12118 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
12122 exp
.X_op
= O_secrel
;
12123 exp
.X_add_symbol
= symbol
;
12124 exp
.X_add_number
= 0;
12125 emit_expr (&exp
, size
);
12129 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12130 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12133 x86_64_section_letter (int letter
, const char **ptr_msg
)
12135 if (flag_code
== CODE_64BIT
)
12138 return SHF_X86_64_LARGE
;
12140 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12143 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
12148 x86_64_section_word (char *str
, size_t len
)
12150 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
12151 return SHF_X86_64_LARGE
;
12157 handle_large_common (int small ATTRIBUTE_UNUSED
)
12159 if (flag_code
!= CODE_64BIT
)
12161 s_comm_internal (0, elf_common_parse
);
12162 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12166 static segT lbss_section
;
12167 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
12168 asection
*saved_bss_section
= bss_section
;
12170 if (lbss_section
== NULL
)
12172 flagword applicable
;
12173 segT seg
= now_seg
;
12174 subsegT subseg
= now_subseg
;
12176 /* The .lbss section is for local .largecomm symbols. */
12177 lbss_section
= subseg_new (".lbss", 0);
12178 applicable
= bfd_applicable_section_flags (stdoutput
);
12179 bfd_set_section_flags (stdoutput
, lbss_section
,
12180 applicable
& SEC_ALLOC
);
12181 seg_info (lbss_section
)->bss
= 1;
12183 subseg_set (seg
, subseg
);
12186 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
12187 bss_section
= lbss_section
;
12189 s_comm_internal (0, elf_common_parse
);
12191 elf_com_section_ptr
= saved_com_section_ptr
;
12192 bss_section
= saved_bss_section
;
12195 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */