1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
136 unsigned int negated
; /* turn off indicated flags. */
140 static void update_code_flag (int, int);
141 static void set_code_flag (int);
142 static void set_16bit_gcc_code_flag (int);
143 static void set_intel_syntax (int);
144 static void set_intel_mnemonic (int);
145 static void set_allow_index_reg (int);
146 static void set_check (int);
147 static void set_cpu_arch (int);
149 static void pe_directive_secrel (int);
151 static void signed_cons (int);
152 static char *output_invalid (int c
);
153 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
155 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
157 static int i386_att_operand (char *);
158 static int i386_intel_operand (char *, int);
159 static int i386_intel_simplify (expressionS
*);
160 static int i386_intel_parse_name (const char *, expressionS
*);
161 static const reg_entry
*parse_register (char *, char **);
162 static char *parse_insn (char *, char *);
163 static char *parse_operands (char *, const char *);
164 static void swap_operands (void);
165 static void swap_2_operands (int, int);
166 static void optimize_imm (void);
167 static void optimize_disp (void);
168 static const insn_template
*match_template (void);
169 static int check_string (void);
170 static int process_suffix (void);
171 static int check_byte_reg (void);
172 static int check_long_reg (void);
173 static int check_qword_reg (void);
174 static int check_word_reg (void);
175 static int finalize_imm (void);
176 static int process_operands (void);
177 static const seg_entry
*build_modrm_byte (void);
178 static void output_insn (void);
179 static void output_imm (fragS
*, offsetT
);
180 static void output_disp (fragS
*, offsetT
);
182 static void s_bss (int);
184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
188 static const char *default_arch
= DEFAULT_ARCH
;
190 /* This struct describes rounding control and SAE in the instruction. */
204 static struct RC_Operation rc_op
;
206 /* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209 struct Mask_Operation
211 const reg_entry
*mask
;
212 unsigned int zeroing
;
213 /* The operand where this operation is associated. */
217 static struct Mask_Operation mask_op
;
219 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
221 struct Broadcast_Operation
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
226 /* Index of broadcasted operand. */
230 static struct Broadcast_Operation broadcast_op
;
235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes
[4];
238 /* Destination or source register specifier. */
239 const reg_entry
*register_specifier
;
242 /* 'md_assemble ()' gathers together information and puts it into a
249 const reg_entry
*regs
;
254 operand_size_mismatch
,
255 operand_type_mismatch
,
256 register_type_mismatch
,
257 number_of_operands_mismatch
,
258 invalid_instruction_suffix
,
261 unsupported_with_intel_mnemonic
,
264 invalid_vsib_address
,
265 invalid_vector_register_set
,
266 unsupported_vector_index_register
,
267 unsupported_broadcast
,
268 broadcast_not_on_src_operand
,
271 mask_not_on_destination
,
274 rc_sae_operand_not_last_imm
,
275 invalid_register_operand
,
281 /* TM holds the template for the insn were currently assembling. */
284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
288 /* OPERANDS gives the number of given operands. */
289 unsigned int operands
;
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
294 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
296 /* TYPES [i] is the type (see above #defines) which tells us how to
297 use OP[i] for the corresponding operand. */
298 i386_operand_type types
[MAX_OPERANDS
];
300 /* Displacement expression, immediate expression, or register for each
302 union i386_op op
[MAX_OPERANDS
];
304 /* Flags for operands. */
305 unsigned int flags
[MAX_OPERANDS
];
306 #define Operand_PCrel 1
308 /* Relocation type for operand */
309 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry
*base_reg
;
314 const reg_entry
*index_reg
;
315 unsigned int log2_scale_factor
;
317 /* SEG gives the seg_entries of this insn. They are zero unless
318 explicit segment overrides are given. */
319 const seg_entry
*seg
[2];
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes
;
324 unsigned char prefix
[MAX_PREFIXES
];
326 /* RM and SIB are the modrm byte and the sib byte where the
327 addressing modes of this insn are encoded. */
334 /* Masking attributes. */
335 struct Mask_Operation
*mask
;
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation
*rounding
;
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation
*broadcast
;
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift
;
346 /* Swap operand in encoding. */
347 unsigned int swap_operand
;
349 /* Prefer 8bit or 32bit displacement in encoding. */
352 disp_encoding_default
= 0,
358 const char *rep_prefix
;
361 const char *hle_prefix
;
363 /* Have BND prefix. */
364 const char *bnd_prefix
;
366 /* Need VREX to support upper 16 registers. */
370 enum i386_error error
;
373 typedef struct _i386_insn i386_insn
;
375 /* Link RC type with corresponding string, that'll be looked for in
384 static const struct RC_name RC_NamesTable
[] =
386 { rne
, STRING_COMMA_LEN ("rn-sae") },
387 { rd
, STRING_COMMA_LEN ("rd-sae") },
388 { ru
, STRING_COMMA_LEN ("ru-sae") },
389 { rz
, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly
, STRING_COMMA_LEN ("sae") },
393 /* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
395 const char extra_symbol_chars
[] = "*%-([{"
404 #if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
406 && !defined (TE_GNU) \
407 && !defined (TE_LINUX) \
408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
410 && !defined (TE_FreeBSD) \
411 && !defined (TE_DragonFly) \
412 && !defined (TE_NetBSD)))
413 /* This array holds the chars that always start a comment. If the
414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416 const char *i386_comment_chars
= "#/";
417 #define SVR4_COMMENT_CHARS 1
418 #define PREFIX_SEPARATOR '\\'
421 const char *i386_comment_chars
= "#";
422 #define PREFIX_SEPARATOR '/'
425 /* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
429 first line of the input file. This is because the compiler outputs
430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
432 '/' isn't otherwise defined. */
433 const char line_comment_chars
[] = "#/";
435 const char line_separator_chars
[] = ";";
437 /* Chars that can be used to separate mant from exp in floating point
439 const char EXP_CHARS
[] = "eE";
441 /* Chars that mean this number is a floating point constant
444 const char FLT_CHARS
[] = "fFdDxX";
446 /* Tables for lexical analysis. */
447 static char mnemonic_chars
[256];
448 static char register_chars
[256];
449 static char operand_chars
[256];
450 static char identifier_chars
[256];
451 static char digit_chars
[256];
453 /* Lexical macros. */
454 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455 #define is_operand_char(x) (operand_chars[(unsigned char) x])
456 #define is_register_char(x) (register_chars[(unsigned char) x])
457 #define is_space_char(x) ((x) == ' ')
458 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459 #define is_digit_char(x) (digit_chars[(unsigned char) x])
461 /* All non-digit non-letter characters that may occur in an operand. */
462 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
464 /* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
467 assembler instruction). */
468 static char save_stack
[32];
469 static char *save_stack_p
;
470 #define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472 #define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
475 /* The instruction we're assembling. */
478 /* Possible templates for current insn. */
479 static const templates
*current_templates
;
481 /* Per instruction expressionS buffers: max displacements & immediates. */
482 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
483 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
485 /* Current operand we are working on. */
486 static int this_operand
= -1;
488 /* We support four different modes. FLAG_CODE variable is used to distinguish
496 static enum flag_code flag_code
;
497 static unsigned int object_64bit
;
498 static unsigned int disallow_64bit_reloc
;
499 static int use_rela_relocations
= 0;
501 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
505 /* The ELF ABI to use. */
513 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
516 #if defined (TE_PE) || defined (TE_PEP)
517 /* Use big object file format. */
518 static int use_big_obj
= 0;
521 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
522 /* 1 if generating code for a shared library. */
523 static int shared
= 0;
526 /* 1 for intel syntax,
528 static int intel_syntax
= 0;
530 /* 1 for intel mnemonic,
531 0 if att mnemonic. */
532 static int intel_mnemonic
= !SYSV386_COMPAT
;
534 /* 1 if support old (<= 2.8.1) versions of gcc. */
535 static int old_gcc
= OLDGCC_COMPAT
;
537 /* 1 if pseudo registers are permitted. */
538 static int allow_pseudo_reg
= 0;
540 /* 1 if register prefix % not required. */
541 static int allow_naked_reg
= 0;
543 /* 1 if the assembler should add BND prefix for all control-tranferring
544 instructions supporting it, even if this prefix wasn't specified
546 static int add_bnd_prefix
= 0;
548 /* 1 if pseudo index register, eiz/riz, is allowed . */
549 static int allow_index_reg
= 0;
551 /* 1 if the assembler should ignore LOCK prefix, even if it was
552 specified explicitly. */
553 static int omit_lock_prefix
= 0;
555 /* 1 if the assembler should encode lfence, mfence, and sfence as
556 "lock addl $0, (%{re}sp)". */
557 static int avoid_fence
= 0;
559 /* 1 if the assembler should generate relax relocations. */
561 static int generate_relax_relocations
562 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
564 static enum check_kind
570 sse_check
, operand_check
= check_warning
;
572 /* Register prefix used for error message. */
573 static const char *register_prefix
= "%";
575 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
576 leave, push, and pop instructions so that gcc has the same stack
577 frame as in 32 bit mode. */
578 static char stackop_size
= '\0';
580 /* Non-zero to optimize code alignment. */
581 int optimize_align_code
= 1;
583 /* Non-zero to quieten some warnings. */
584 static int quiet_warnings
= 0;
587 static const char *cpu_arch_name
= NULL
;
588 static char *cpu_sub_arch_name
= NULL
;
590 /* CPU feature flags. */
591 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
593 /* If we have selected a cpu we are generating instructions for. */
594 static int cpu_arch_tune_set
= 0;
596 /* Cpu we are generating instructions for. */
597 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
599 /* CPU feature flags of cpu we are generating instructions for. */
600 static i386_cpu_flags cpu_arch_tune_flags
;
602 /* CPU instruction set architecture used. */
603 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
605 /* CPU feature flags of instruction set architecture used. */
606 i386_cpu_flags cpu_arch_isa_flags
;
608 /* If set, conditional jumps are not automatically promoted to handle
609 larger than a byte offset. */
610 static unsigned int no_cond_jump_promotion
= 0;
612 /* Encode SSE instructions with VEX prefix. */
613 static unsigned int sse2avx
;
615 /* Encode scalar AVX instructions with specific vector length. */
622 /* Encode scalar EVEX LIG instructions with specific vector length. */
630 /* Encode EVEX WIG instructions with specific evex.w. */
637 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
638 static enum rc_type evexrcig
= rne
;
640 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
641 static symbolS
*GOT_symbol
;
643 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
644 unsigned int x86_dwarf2_return_column
;
646 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
647 int x86_cie_data_alignment
;
649 /* Interface to relax_segment.
650 There are 3 major relax states for 386 jump insns because the
651 different types of jumps add different sizes to frags when we're
652 figuring out what sort of jump to choose to reach a given label. */
655 #define UNCOND_JUMP 0
657 #define COND_JUMP86 2
662 #define SMALL16 (SMALL | CODE16)
664 #define BIG16 (BIG | CODE16)
668 #define INLINE __inline__
674 #define ENCODE_RELAX_STATE(type, size) \
675 ((relax_substateT) (((type) << 2) | (size)))
676 #define TYPE_FROM_RELAX_STATE(s) \
678 #define DISP_SIZE_FROM_RELAX_STATE(s) \
679 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
681 /* This table is used by relax_frag to promote short jumps to long
682 ones where necessary. SMALL (short) jumps may be promoted to BIG
683 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
684 don't allow a short jump in a 32 bit code segment to be promoted to
685 a 16 bit offset jump because it's slower (requires data size
686 prefix), and doesn't work, unless the destination is in the bottom
687 64k of the code segment (The top 16 bits of eip are zeroed). */
689 const relax_typeS md_relax_table
[] =
692 1) most positive reach of this state,
693 2) most negative reach of this state,
694 3) how many bytes this mode will have in the variable part of the frag
695 4) which index into the table to try if we can't fit into this one. */
697 /* UNCOND_JUMP states. */
698 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
699 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
700 /* dword jmp adds 4 bytes to frag:
701 0 extra opcode bytes, 4 displacement bytes. */
703 /* word jmp adds 2 byte2 to frag:
704 0 extra opcode bytes, 2 displacement bytes. */
707 /* COND_JUMP states. */
708 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
709 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
710 /* dword conditionals adds 5 bytes to frag:
711 1 extra opcode byte, 4 displacement bytes. */
713 /* word conditionals add 3 bytes to frag:
714 1 extra opcode byte, 2 displacement bytes. */
717 /* COND_JUMP86 states. */
718 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
719 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
720 /* dword conditionals adds 5 bytes to frag:
721 1 extra opcode byte, 4 displacement bytes. */
723 /* word conditionals add 4 bytes to frag:
724 1 displacement byte and a 3 byte long branch insn. */
728 static const arch_entry cpu_arch
[] =
730 /* Do not replace the first two entries - i386_target_format()
731 relies on them being there in this order. */
732 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
733 CPU_GENERIC32_FLAGS
, 0, 0 },
734 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
735 CPU_GENERIC64_FLAGS
, 0, 0 },
736 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
737 CPU_NONE_FLAGS
, 0, 0 },
738 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
739 CPU_I186_FLAGS
, 0, 0 },
740 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
741 CPU_I286_FLAGS
, 0, 0 },
742 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
743 CPU_I386_FLAGS
, 0, 0 },
744 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
745 CPU_I486_FLAGS
, 0, 0 },
746 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
747 CPU_I586_FLAGS
, 0, 0 },
748 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
749 CPU_I686_FLAGS
, 0, 0 },
750 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
751 CPU_I586_FLAGS
, 0, 0 },
752 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
753 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
754 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
755 CPU_P2_FLAGS
, 0, 0 },
756 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
757 CPU_P3_FLAGS
, 0, 0 },
758 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
759 CPU_P4_FLAGS
, 0, 0 },
760 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
761 CPU_CORE_FLAGS
, 0, 0 },
762 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
763 CPU_NOCONA_FLAGS
, 0, 0 },
764 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
765 CPU_CORE_FLAGS
, 1, 0 },
766 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
767 CPU_CORE_FLAGS
, 0, 0 },
768 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
769 CPU_CORE2_FLAGS
, 1, 0 },
770 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
771 CPU_CORE2_FLAGS
, 0, 0 },
772 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
773 CPU_COREI7_FLAGS
, 0, 0 },
774 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
775 CPU_L1OM_FLAGS
, 0, 0 },
776 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
777 CPU_K1OM_FLAGS
, 0, 0 },
778 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
779 CPU_IAMCU_FLAGS
, 0, 0 },
780 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
781 CPU_K6_FLAGS
, 0, 0 },
782 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
783 CPU_K6_2_FLAGS
, 0, 0 },
784 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
785 CPU_ATHLON_FLAGS
, 0, 0 },
786 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
787 CPU_K8_FLAGS
, 1, 0 },
788 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
789 CPU_K8_FLAGS
, 0, 0 },
790 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
791 CPU_K8_FLAGS
, 0, 0 },
792 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
793 CPU_AMDFAM10_FLAGS
, 0, 0 },
794 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
795 CPU_BDVER1_FLAGS
, 0, 0 },
796 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
797 CPU_BDVER2_FLAGS
, 0, 0 },
798 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
799 CPU_BDVER3_FLAGS
, 0, 0 },
800 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
801 CPU_BDVER4_FLAGS
, 0, 0 },
802 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
803 CPU_ZNVER1_FLAGS
, 0, 0 },
804 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
805 CPU_BTVER1_FLAGS
, 0, 0 },
806 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
807 CPU_BTVER2_FLAGS
, 0, 0 },
808 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
809 CPU_8087_FLAGS
, 0, 0 },
810 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
811 CPU_287_FLAGS
, 0, 0 },
812 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
813 CPU_387_FLAGS
, 0, 0 },
814 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
815 CPU_ANY87_FLAGS
, 0, 1 },
816 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
817 CPU_MMX_FLAGS
, 0, 0 },
818 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
819 CPU_3DNOWA_FLAGS
, 0, 1 },
820 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
821 CPU_SSE_FLAGS
, 0, 0 },
822 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
823 CPU_SSE2_FLAGS
, 0, 0 },
824 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
825 CPU_SSE3_FLAGS
, 0, 0 },
826 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
827 CPU_SSSE3_FLAGS
, 0, 0 },
828 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
829 CPU_SSE4_1_FLAGS
, 0, 0 },
830 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
831 CPU_SSE4_2_FLAGS
, 0, 0 },
832 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
833 CPU_SSE4_2_FLAGS
, 0, 0 },
834 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
835 CPU_ANY_SSE_FLAGS
, 0, 1 },
836 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
837 CPU_AVX_FLAGS
, 0, 0 },
838 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
839 CPU_AVX2_FLAGS
, 0, 0 },
840 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
841 CPU_AVX512F_FLAGS
, 0, 0 },
842 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
843 CPU_AVX512CD_FLAGS
, 0, 0 },
844 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
845 CPU_AVX512ER_FLAGS
, 0, 0 },
846 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
847 CPU_AVX512PF_FLAGS
, 0, 0 },
848 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
849 CPU_AVX512DQ_FLAGS
, 0, 0 },
850 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
851 CPU_AVX512BW_FLAGS
, 0, 0 },
852 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
853 CPU_AVX512VL_FLAGS
, 0, 0 },
854 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
855 CPU_ANY_AVX_FLAGS
, 0, 1 },
856 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
857 CPU_VMX_FLAGS
, 0, 0 },
858 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
859 CPU_VMFUNC_FLAGS
, 0, 0 },
860 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
861 CPU_SMX_FLAGS
, 0, 0 },
862 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
863 CPU_XSAVE_FLAGS
, 0, 0 },
864 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
865 CPU_XSAVEOPT_FLAGS
, 0, 0 },
866 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
867 CPU_XSAVEC_FLAGS
, 0, 0 },
868 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
869 CPU_XSAVES_FLAGS
, 0, 0 },
870 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
871 CPU_AES_FLAGS
, 0, 0 },
872 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
873 CPU_PCLMUL_FLAGS
, 0, 0 },
874 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
875 CPU_PCLMUL_FLAGS
, 1, 0 },
876 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
877 CPU_FSGSBASE_FLAGS
, 0, 0 },
878 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
879 CPU_RDRND_FLAGS
, 0, 0 },
880 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
881 CPU_F16C_FLAGS
, 0, 0 },
882 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
883 CPU_BMI2_FLAGS
, 0, 0 },
884 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
885 CPU_FMA_FLAGS
, 0, 0 },
886 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
887 CPU_FMA4_FLAGS
, 0, 0 },
888 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
889 CPU_XOP_FLAGS
, 0, 0 },
890 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
891 CPU_LWP_FLAGS
, 0, 0 },
892 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
893 CPU_MOVBE_FLAGS
, 0, 0 },
894 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
895 CPU_CX16_FLAGS
, 0, 0 },
896 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
897 CPU_EPT_FLAGS
, 0, 0 },
898 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
899 CPU_LZCNT_FLAGS
, 0, 0 },
900 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
901 CPU_HLE_FLAGS
, 0, 0 },
902 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
903 CPU_RTM_FLAGS
, 0, 0 },
904 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
905 CPU_INVPCID_FLAGS
, 0, 0 },
906 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
907 CPU_CLFLUSH_FLAGS
, 0, 0 },
908 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
909 CPU_NOP_FLAGS
, 0, 0 },
910 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
911 CPU_SYSCALL_FLAGS
, 0, 0 },
912 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
913 CPU_RDTSCP_FLAGS
, 0, 0 },
914 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
915 CPU_3DNOW_FLAGS
, 0, 0 },
916 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
917 CPU_3DNOWA_FLAGS
, 0, 0 },
918 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
919 CPU_PADLOCK_FLAGS
, 0, 0 },
920 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
921 CPU_SVME_FLAGS
, 1, 0 },
922 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
923 CPU_SVME_FLAGS
, 0, 0 },
924 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
925 CPU_SSE4A_FLAGS
, 0, 0 },
926 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
927 CPU_ABM_FLAGS
, 0, 0 },
928 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
929 CPU_BMI_FLAGS
, 0, 0 },
930 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
931 CPU_TBM_FLAGS
, 0, 0 },
932 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
933 CPU_ADX_FLAGS
, 0, 0 },
934 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
935 CPU_RDSEED_FLAGS
, 0, 0 },
936 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
937 CPU_PRFCHW_FLAGS
, 0, 0 },
938 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
939 CPU_SMAP_FLAGS
, 0, 0 },
940 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
941 CPU_MPX_FLAGS
, 0, 0 },
942 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
943 CPU_SHA_FLAGS
, 0, 0 },
944 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
945 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
946 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
947 CPU_PREFETCHWT1_FLAGS
, 0, 0 },
948 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
949 CPU_SE1_FLAGS
, 0, 0 },
950 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
951 CPU_CLWB_FLAGS
, 0, 0 },
952 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
953 CPU_PCOMMIT_FLAGS
, 0, 0 },
954 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
955 CPU_AVX512IFMA_FLAGS
, 0, 0 },
956 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
957 CPU_AVX512VBMI_FLAGS
, 0, 0 },
958 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
959 CPU_CLZERO_FLAGS
, 0, 0 },
960 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
961 CPU_MWAITX_FLAGS
, 0, 0 },
962 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
963 CPU_OSPKE_FLAGS
, 0, 0 },
967 /* Like s_lcomm_internal in gas/read.c but the alignment string
968 is allowed to be optional. */
971 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
978 && *input_line_pointer
== ',')
980 align
= parse_align (needs_align
- 1);
982 if (align
== (addressT
) -1)
997 bss_alloc (symbolP
, size
, align
);
1002 pe_lcomm (int needs_align
)
1004 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1008 const pseudo_typeS md_pseudo_table
[] =
1010 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1011 {"align", s_align_bytes
, 0},
1013 {"align", s_align_ptwo
, 0},
1015 {"arch", set_cpu_arch
, 0},
1019 {"lcomm", pe_lcomm
, 1},
1021 {"ffloat", float_cons
, 'f'},
1022 {"dfloat", float_cons
, 'd'},
1023 {"tfloat", float_cons
, 'x'},
1025 {"slong", signed_cons
, 4},
1026 {"noopt", s_ignore
, 0},
1027 {"optim", s_ignore
, 0},
1028 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1029 {"code16", set_code_flag
, CODE_16BIT
},
1030 {"code32", set_code_flag
, CODE_32BIT
},
1031 {"code64", set_code_flag
, CODE_64BIT
},
1032 {"intel_syntax", set_intel_syntax
, 1},
1033 {"att_syntax", set_intel_syntax
, 0},
1034 {"intel_mnemonic", set_intel_mnemonic
, 1},
1035 {"att_mnemonic", set_intel_mnemonic
, 0},
1036 {"allow_index_reg", set_allow_index_reg
, 1},
1037 {"disallow_index_reg", set_allow_index_reg
, 0},
1038 {"sse_check", set_check
, 0},
1039 {"operand_check", set_check
, 1},
1040 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1041 {"largecomm", handle_large_common
, 0},
1043 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1044 {"loc", dwarf2_directive_loc
, 0},
1045 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1048 {"secrel32", pe_directive_secrel
, 0},
1053 /* For interface with expression (). */
1054 extern char *input_line_pointer
;
1056 /* Hash table for instruction mnemonic lookup. */
1057 static struct hash_control
*op_hash
;
1059 /* Hash table for register lookup. */
1060 static struct hash_control
*reg_hash
;
1063 i386_align_code (fragS
*fragP
, int count
)
1065 /* Various efficient no-op patterns for aligning code labels.
1066 Note: Don't try to assemble the instructions in the comments.
1067 0L and 0w are not legal. */
1068 static const unsigned char f32_1
[] =
1070 static const unsigned char f32_2
[] =
1071 {0x66,0x90}; /* xchg %ax,%ax */
1072 static const unsigned char f32_3
[] =
1073 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1074 static const unsigned char f32_4
[] =
1075 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1076 static const unsigned char f32_5
[] =
1078 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1079 static const unsigned char f32_6
[] =
1080 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1081 static const unsigned char f32_7
[] =
1082 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1083 static const unsigned char f32_8
[] =
1085 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1086 static const unsigned char f32_9
[] =
1087 {0x89,0xf6, /* movl %esi,%esi */
1088 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1089 static const unsigned char f32_10
[] =
1090 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1091 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1092 static const unsigned char f32_11
[] =
1093 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1094 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1095 static const unsigned char f32_12
[] =
1096 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1097 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1098 static const unsigned char f32_13
[] =
1099 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1100 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1101 static const unsigned char f32_14
[] =
1102 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1103 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1104 static const unsigned char f16_3
[] =
1105 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1106 static const unsigned char f16_4
[] =
1107 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1108 static const unsigned char f16_5
[] =
1110 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1111 static const unsigned char f16_6
[] =
1112 {0x89,0xf6, /* mov %si,%si */
1113 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1114 static const unsigned char f16_7
[] =
1115 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1116 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1117 static const unsigned char f16_8
[] =
1118 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1119 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1120 static const unsigned char jump_31
[] =
1121 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1122 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1123 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1124 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1125 static const unsigned char *const f32_patt
[] = {
1126 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1127 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1129 static const unsigned char *const f16_patt
[] = {
1130 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1132 /* nopl (%[re]ax) */
1133 static const unsigned char alt_3
[] =
1135 /* nopl 0(%[re]ax) */
1136 static const unsigned char alt_4
[] =
1137 {0x0f,0x1f,0x40,0x00};
1138 /* nopl 0(%[re]ax,%[re]ax,1) */
1139 static const unsigned char alt_5
[] =
1140 {0x0f,0x1f,0x44,0x00,0x00};
1141 /* nopw 0(%[re]ax,%[re]ax,1) */
1142 static const unsigned char alt_6
[] =
1143 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1144 /* nopl 0L(%[re]ax) */
1145 static const unsigned char alt_7
[] =
1146 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1147 /* nopl 0L(%[re]ax,%[re]ax,1) */
1148 static const unsigned char alt_8
[] =
1149 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1150 /* nopw 0L(%[re]ax,%[re]ax,1) */
1151 static const unsigned char alt_9
[] =
1152 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1153 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1154 static const unsigned char alt_10
[] =
1155 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1156 static const unsigned char *const alt_patt
[] = {
1157 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1161 /* Only align for at least a positive non-zero boundary. */
1162 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1165 /* We need to decide which NOP sequence to use for 32bit and
1166 64bit. When -mtune= is used:
1168 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1169 PROCESSOR_GENERIC32, f32_patt will be used.
1170 2. For the rest, alt_patt will be used.
1172 When -mtune= isn't used, alt_patt will be used if
1173 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1176 When -march= or .arch is used, we can't use anything beyond
1177 cpu_arch_isa_flags. */
1179 if (flag_code
== CODE_16BIT
)
1183 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1185 /* Adjust jump offset. */
1186 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1189 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1190 f16_patt
[count
- 1], count
);
1194 const unsigned char *const *patt
= NULL
;
1196 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1198 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1199 switch (cpu_arch_tune
)
1201 case PROCESSOR_UNKNOWN
:
1202 /* We use cpu_arch_isa_flags to check if we SHOULD
1203 optimize with nops. */
1204 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1209 case PROCESSOR_PENTIUM4
:
1210 case PROCESSOR_NOCONA
:
1211 case PROCESSOR_CORE
:
1212 case PROCESSOR_CORE2
:
1213 case PROCESSOR_COREI7
:
1214 case PROCESSOR_L1OM
:
1215 case PROCESSOR_K1OM
:
1216 case PROCESSOR_GENERIC64
:
1218 case PROCESSOR_ATHLON
:
1220 case PROCESSOR_AMDFAM10
:
1222 case PROCESSOR_ZNVER
:
1226 case PROCESSOR_I386
:
1227 case PROCESSOR_I486
:
1228 case PROCESSOR_PENTIUM
:
1229 case PROCESSOR_PENTIUMPRO
:
1230 case PROCESSOR_IAMCU
:
1231 case PROCESSOR_GENERIC32
:
1238 switch (fragP
->tc_frag_data
.tune
)
1240 case PROCESSOR_UNKNOWN
:
1241 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1242 PROCESSOR_UNKNOWN. */
1246 case PROCESSOR_I386
:
1247 case PROCESSOR_I486
:
1248 case PROCESSOR_PENTIUM
:
1249 case PROCESSOR_IAMCU
:
1251 case PROCESSOR_ATHLON
:
1253 case PROCESSOR_AMDFAM10
:
1255 case PROCESSOR_ZNVER
:
1257 case PROCESSOR_GENERIC32
:
1258 /* We use cpu_arch_isa_flags to check if we CAN optimize
1260 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1265 case PROCESSOR_PENTIUMPRO
:
1266 case PROCESSOR_PENTIUM4
:
1267 case PROCESSOR_NOCONA
:
1268 case PROCESSOR_CORE
:
1269 case PROCESSOR_CORE2
:
1270 case PROCESSOR_COREI7
:
1271 case PROCESSOR_L1OM
:
1272 case PROCESSOR_K1OM
:
1273 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1278 case PROCESSOR_GENERIC64
:
1284 if (patt
== f32_patt
)
1286 /* If the padding is less than 15 bytes, we use the normal
1287 ones. Otherwise, we use a jump instruction and adjust
1291 /* For 64bit, the limit is 3 bytes. */
1292 if (flag_code
== CODE_64BIT
1293 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1298 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1299 patt
[count
- 1], count
);
1302 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1304 /* Adjust jump offset. */
1305 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1310 /* Maximum length of an instruction is 10 byte. If the
1311 padding is greater than 10 bytes and we don't use jump,
1312 we have to break it into smaller pieces. */
1313 int padding
= count
;
1314 while (padding
> 10)
1317 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1322 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1323 patt
[padding
- 1], padding
);
1326 fragP
->fr_var
= count
;
1330 operand_type_all_zero (const union i386_operand_type
*x
)
1332 switch (ARRAY_SIZE(x
->array
))
1341 return !x
->array
[0];
1348 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1350 switch (ARRAY_SIZE(x
->array
))
1365 operand_type_equal (const union i386_operand_type
*x
,
1366 const union i386_operand_type
*y
)
1368 switch (ARRAY_SIZE(x
->array
))
1371 if (x
->array
[2] != y
->array
[2])
1374 if (x
->array
[1] != y
->array
[1])
1377 return x
->array
[0] == y
->array
[0];
1385 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1387 switch (ARRAY_SIZE(x
->array
))
1396 return !x
->array
[0];
1403 cpu_flags_equal (const union i386_cpu_flags
*x
,
1404 const union i386_cpu_flags
*y
)
1406 switch (ARRAY_SIZE(x
->array
))
1409 if (x
->array
[2] != y
->array
[2])
1412 if (x
->array
[1] != y
->array
[1])
1415 return x
->array
[0] == y
->array
[0];
1423 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1425 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1426 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1429 static INLINE i386_cpu_flags
1430 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1432 switch (ARRAY_SIZE (x
.array
))
1435 x
.array
[2] &= y
.array
[2];
1437 x
.array
[1] &= y
.array
[1];
1439 x
.array
[0] &= y
.array
[0];
1447 static INLINE i386_cpu_flags
1448 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1450 switch (ARRAY_SIZE (x
.array
))
1453 x
.array
[2] |= y
.array
[2];
1455 x
.array
[1] |= y
.array
[1];
1457 x
.array
[0] |= y
.array
[0];
1465 static INLINE i386_cpu_flags
1466 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1468 switch (ARRAY_SIZE (x
.array
))
1471 x
.array
[2] &= ~y
.array
[2];
1473 x
.array
[1] &= ~y
.array
[1];
1475 x
.array
[0] &= ~y
.array
[0];
1484 valid_iamcu_cpu_flags (const i386_cpu_flags
*flags
)
1486 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
1488 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_COMPAT_FLAGS
;
1489 i386_cpu_flags compat_flags
;
1490 compat_flags
= cpu_flags_and_not (*flags
, iamcu_flags
);
1491 return cpu_flags_all_zero (&compat_flags
);
1497 #define CPU_FLAGS_ARCH_MATCH 0x1
1498 #define CPU_FLAGS_64BIT_MATCH 0x2
1499 #define CPU_FLAGS_AES_MATCH 0x4
1500 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1501 #define CPU_FLAGS_AVX_MATCH 0x10
1503 #define CPU_FLAGS_32BIT_MATCH \
1504 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1505 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1506 #define CPU_FLAGS_PERFECT_MATCH \
1507 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1509 /* Return CPU flags match bits. */
1512 cpu_flags_match (const insn_template
*t
)
1514 i386_cpu_flags x
= t
->cpu_flags
;
1515 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1517 x
.bitfield
.cpu64
= 0;
1518 x
.bitfield
.cpuno64
= 0;
1520 if (cpu_flags_all_zero (&x
))
1522 /* This instruction is available on all archs. */
1523 match
|= CPU_FLAGS_32BIT_MATCH
;
1527 /* This instruction is available only on some archs. */
1528 i386_cpu_flags cpu
= cpu_arch_flags
;
1530 cpu
.bitfield
.cpu64
= 0;
1531 cpu
.bitfield
.cpuno64
= 0;
1532 cpu
= cpu_flags_and (x
, cpu
);
1533 if (!cpu_flags_all_zero (&cpu
))
1535 if (x
.bitfield
.cpuavx
)
1537 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1538 if (cpu
.bitfield
.cpuavx
)
1540 /* Check SSE2AVX. */
1541 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1543 match
|= (CPU_FLAGS_ARCH_MATCH
1544 | CPU_FLAGS_AVX_MATCH
);
1546 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1547 match
|= CPU_FLAGS_AES_MATCH
;
1549 if (!x
.bitfield
.cpupclmul
1550 || cpu
.bitfield
.cpupclmul
)
1551 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1555 match
|= CPU_FLAGS_ARCH_MATCH
;
1558 match
|= CPU_FLAGS_32BIT_MATCH
;
1564 static INLINE i386_operand_type
1565 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1567 switch (ARRAY_SIZE (x
.array
))
1570 x
.array
[2] &= y
.array
[2];
1572 x
.array
[1] &= y
.array
[1];
1574 x
.array
[0] &= y
.array
[0];
1582 static INLINE i386_operand_type
1583 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1585 switch (ARRAY_SIZE (x
.array
))
1588 x
.array
[2] |= y
.array
[2];
1590 x
.array
[1] |= y
.array
[1];
1592 x
.array
[0] |= y
.array
[0];
1600 static INLINE i386_operand_type
1601 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1603 switch (ARRAY_SIZE (x
.array
))
1606 x
.array
[2] ^= y
.array
[2];
1608 x
.array
[1] ^= y
.array
[1];
1610 x
.array
[0] ^= y
.array
[0];
1618 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1619 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1620 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1621 static const i386_operand_type inoutportreg
1622 = OPERAND_TYPE_INOUTPORTREG
;
1623 static const i386_operand_type reg16_inoutportreg
1624 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1625 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1626 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1627 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1628 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1629 static const i386_operand_type anydisp
1630 = OPERAND_TYPE_ANYDISP
;
1631 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1632 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1633 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1634 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1635 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1636 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1637 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1638 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1639 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1640 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1641 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1642 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1643 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1644 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1655 operand_type_check (i386_operand_type t
, enum operand_type c
)
1660 return (t
.bitfield
.reg8
1663 || t
.bitfield
.reg64
);
1666 return (t
.bitfield
.imm8
1670 || t
.bitfield
.imm32s
1671 || t
.bitfield
.imm64
);
1674 return (t
.bitfield
.disp8
1675 || t
.bitfield
.disp16
1676 || t
.bitfield
.disp32
1677 || t
.bitfield
.disp32s
1678 || t
.bitfield
.disp64
);
1681 return (t
.bitfield
.disp8
1682 || t
.bitfield
.disp16
1683 || t
.bitfield
.disp32
1684 || t
.bitfield
.disp32s
1685 || t
.bitfield
.disp64
1686 || t
.bitfield
.baseindex
);
1695 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1696 operand J for instruction template T. */
1699 match_reg_size (const insn_template
*t
, unsigned int j
)
1701 return !((i
.types
[j
].bitfield
.byte
1702 && !t
->operand_types
[j
].bitfield
.byte
)
1703 || (i
.types
[j
].bitfield
.word
1704 && !t
->operand_types
[j
].bitfield
.word
)
1705 || (i
.types
[j
].bitfield
.dword
1706 && !t
->operand_types
[j
].bitfield
.dword
)
1707 || (i
.types
[j
].bitfield
.qword
1708 && !t
->operand_types
[j
].bitfield
.qword
));
1711 /* Return 1 if there is no conflict in any size on operand J for
1712 instruction template T. */
1715 match_mem_size (const insn_template
*t
, unsigned int j
)
1717 return (match_reg_size (t
, j
)
1718 && !((i
.types
[j
].bitfield
.unspecified
1720 && !t
->operand_types
[j
].bitfield
.unspecified
)
1721 || (i
.types
[j
].bitfield
.fword
1722 && !t
->operand_types
[j
].bitfield
.fword
)
1723 || (i
.types
[j
].bitfield
.tbyte
1724 && !t
->operand_types
[j
].bitfield
.tbyte
)
1725 || (i
.types
[j
].bitfield
.xmmword
1726 && !t
->operand_types
[j
].bitfield
.xmmword
)
1727 || (i
.types
[j
].bitfield
.ymmword
1728 && !t
->operand_types
[j
].bitfield
.ymmword
)
1729 || (i
.types
[j
].bitfield
.zmmword
1730 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1733 /* Return 1 if there is no size conflict on any operands for
1734 instruction template T. */
1737 operand_size_match (const insn_template
*t
)
1742 /* Don't check jump instructions. */
1743 if (t
->opcode_modifier
.jump
1744 || t
->opcode_modifier
.jumpbyte
1745 || t
->opcode_modifier
.jumpdword
1746 || t
->opcode_modifier
.jumpintersegment
)
1749 /* Check memory and accumulator operand size. */
1750 for (j
= 0; j
< i
.operands
; j
++)
1752 if (t
->operand_types
[j
].bitfield
.anysize
)
1755 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1761 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1770 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1773 i
.error
= operand_size_mismatch
;
1777 /* Check reverse. */
1778 gas_assert (i
.operands
== 2);
1781 for (j
= 0; j
< 2; j
++)
1783 if (t
->operand_types
[j
].bitfield
.acc
1784 && !match_reg_size (t
, j
? 0 : 1))
1787 if (i
.types
[j
].bitfield
.mem
1788 && !match_mem_size (t
, j
? 0 : 1))
1796 operand_type_match (i386_operand_type overlap
,
1797 i386_operand_type given
)
1799 i386_operand_type temp
= overlap
;
1801 temp
.bitfield
.jumpabsolute
= 0;
1802 temp
.bitfield
.unspecified
= 0;
1803 temp
.bitfield
.byte
= 0;
1804 temp
.bitfield
.word
= 0;
1805 temp
.bitfield
.dword
= 0;
1806 temp
.bitfield
.fword
= 0;
1807 temp
.bitfield
.qword
= 0;
1808 temp
.bitfield
.tbyte
= 0;
1809 temp
.bitfield
.xmmword
= 0;
1810 temp
.bitfield
.ymmword
= 0;
1811 temp
.bitfield
.zmmword
= 0;
1812 if (operand_type_all_zero (&temp
))
1815 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1816 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1820 i
.error
= operand_type_mismatch
;
1824 /* If given types g0 and g1 are registers they must be of the same type
1825 unless the expected operand type register overlap is null.
1826 Note that Acc in a template matches every size of reg. */
1829 operand_type_register_match (i386_operand_type m0
,
1830 i386_operand_type g0
,
1831 i386_operand_type t0
,
1832 i386_operand_type m1
,
1833 i386_operand_type g1
,
1834 i386_operand_type t1
)
1836 if (!operand_type_check (g0
, reg
))
1839 if (!operand_type_check (g1
, reg
))
1842 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1843 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1844 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1845 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1848 if (m0
.bitfield
.acc
)
1850 t0
.bitfield
.reg8
= 1;
1851 t0
.bitfield
.reg16
= 1;
1852 t0
.bitfield
.reg32
= 1;
1853 t0
.bitfield
.reg64
= 1;
1856 if (m1
.bitfield
.acc
)
1858 t1
.bitfield
.reg8
= 1;
1859 t1
.bitfield
.reg16
= 1;
1860 t1
.bitfield
.reg32
= 1;
1861 t1
.bitfield
.reg64
= 1;
1864 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1865 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1866 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1867 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1870 i
.error
= register_type_mismatch
;
1875 static INLINE
unsigned int
1876 register_number (const reg_entry
*r
)
1878 unsigned int nr
= r
->reg_num
;
1880 if (r
->reg_flags
& RegRex
)
1883 if (r
->reg_flags
& RegVRex
)
1889 static INLINE
unsigned int
1890 mode_from_disp_size (i386_operand_type t
)
1892 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1894 else if (t
.bitfield
.disp16
1895 || t
.bitfield
.disp32
1896 || t
.bitfield
.disp32s
)
1903 fits_in_signed_byte (addressT num
)
1905 return num
+ 0x80 <= 0xff;
1909 fits_in_unsigned_byte (addressT num
)
1915 fits_in_unsigned_word (addressT num
)
1917 return num
<= 0xffff;
1921 fits_in_signed_word (addressT num
)
1923 return num
+ 0x8000 <= 0xffff;
1927 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1932 return num
+ 0x80000000 <= 0xffffffff;
1934 } /* fits_in_signed_long() */
1937 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
1942 return num
<= 0xffffffff;
1944 } /* fits_in_unsigned_long() */
1947 fits_in_vec_disp8 (offsetT num
)
1949 int shift
= i
.memshift
;
1955 mask
= (1 << shift
) - 1;
1957 /* Return 0 if NUM isn't properly aligned. */
1961 /* Check if NUM will fit in 8bit after shift. */
1962 return fits_in_signed_byte (num
>> shift
);
1966 fits_in_imm4 (offsetT num
)
1968 return (num
& 0xf) == num
;
1971 static i386_operand_type
1972 smallest_imm_type (offsetT num
)
1974 i386_operand_type t
;
1976 operand_type_set (&t
, 0);
1977 t
.bitfield
.imm64
= 1;
1979 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1981 /* This code is disabled on the 486 because all the Imm1 forms
1982 in the opcode table are slower on the i486. They're the
1983 versions with the implicitly specified single-position
1984 displacement, which has another syntax if you really want to
1986 t
.bitfield
.imm1
= 1;
1987 t
.bitfield
.imm8
= 1;
1988 t
.bitfield
.imm8s
= 1;
1989 t
.bitfield
.imm16
= 1;
1990 t
.bitfield
.imm32
= 1;
1991 t
.bitfield
.imm32s
= 1;
1993 else if (fits_in_signed_byte (num
))
1995 t
.bitfield
.imm8
= 1;
1996 t
.bitfield
.imm8s
= 1;
1997 t
.bitfield
.imm16
= 1;
1998 t
.bitfield
.imm32
= 1;
1999 t
.bitfield
.imm32s
= 1;
2001 else if (fits_in_unsigned_byte (num
))
2003 t
.bitfield
.imm8
= 1;
2004 t
.bitfield
.imm16
= 1;
2005 t
.bitfield
.imm32
= 1;
2006 t
.bitfield
.imm32s
= 1;
2008 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2010 t
.bitfield
.imm16
= 1;
2011 t
.bitfield
.imm32
= 1;
2012 t
.bitfield
.imm32s
= 1;
2014 else if (fits_in_signed_long (num
))
2016 t
.bitfield
.imm32
= 1;
2017 t
.bitfield
.imm32s
= 1;
2019 else if (fits_in_unsigned_long (num
))
2020 t
.bitfield
.imm32
= 1;
2026 offset_in_range (offsetT val
, int size
)
2032 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2033 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2034 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2036 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2042 /* If BFD64, sign extend val for 32bit address mode. */
2043 if (flag_code
!= CODE_64BIT
2044 || i
.prefix
[ADDR_PREFIX
])
2045 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2046 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2049 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2051 char buf1
[40], buf2
[40];
2053 sprint_value (buf1
, val
);
2054 sprint_value (buf2
, val
& mask
);
2055 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2069 a. PREFIX_EXIST if attempting to add a prefix where one from the
2070 same class already exists.
2071 b. PREFIX_LOCK if lock prefix is added.
2072 c. PREFIX_REP if rep/repne prefix is added.
2073 d. PREFIX_OTHER if other prefix is added.
2076 static enum PREFIX_GROUP
2077 add_prefix (unsigned int prefix
)
2079 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2082 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2083 && flag_code
== CODE_64BIT
)
2085 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2086 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2087 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2098 case CS_PREFIX_OPCODE
:
2099 case DS_PREFIX_OPCODE
:
2100 case ES_PREFIX_OPCODE
:
2101 case FS_PREFIX_OPCODE
:
2102 case GS_PREFIX_OPCODE
:
2103 case SS_PREFIX_OPCODE
:
2107 case REPNE_PREFIX_OPCODE
:
2108 case REPE_PREFIX_OPCODE
:
2113 case LOCK_PREFIX_OPCODE
:
2122 case ADDR_PREFIX_OPCODE
:
2126 case DATA_PREFIX_OPCODE
:
2130 if (i
.prefix
[q
] != 0)
2138 i
.prefix
[q
] |= prefix
;
2141 as_bad (_("same type of prefix used twice"));
2147 update_code_flag (int value
, int check
)
2149 PRINTF_LIKE ((*as_error
));
2151 flag_code
= (enum flag_code
) value
;
2152 if (flag_code
== CODE_64BIT
)
2154 cpu_arch_flags
.bitfield
.cpu64
= 1;
2155 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2159 cpu_arch_flags
.bitfield
.cpu64
= 0;
2160 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2162 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2165 as_error
= as_fatal
;
2168 (*as_error
) (_("64bit mode not supported on `%s'."),
2169 cpu_arch_name
? cpu_arch_name
: default_arch
);
2171 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2174 as_error
= as_fatal
;
2177 (*as_error
) (_("32bit mode not supported on `%s'."),
2178 cpu_arch_name
? cpu_arch_name
: default_arch
);
2180 stackop_size
= '\0';
2184 set_code_flag (int value
)
2186 update_code_flag (value
, 0);
2190 set_16bit_gcc_code_flag (int new_code_flag
)
2192 flag_code
= (enum flag_code
) new_code_flag
;
2193 if (flag_code
!= CODE_16BIT
)
2195 cpu_arch_flags
.bitfield
.cpu64
= 0;
2196 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2197 stackop_size
= LONG_MNEM_SUFFIX
;
2201 set_intel_syntax (int syntax_flag
)
2203 /* Find out if register prefixing is specified. */
2204 int ask_naked_reg
= 0;
2207 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2210 int e
= get_symbol_name (&string
);
2212 if (strcmp (string
, "prefix") == 0)
2214 else if (strcmp (string
, "noprefix") == 0)
2217 as_bad (_("bad argument to syntax directive."));
2218 (void) restore_line_pointer (e
);
2220 demand_empty_rest_of_line ();
2222 intel_syntax
= syntax_flag
;
2224 if (ask_naked_reg
== 0)
2225 allow_naked_reg
= (intel_syntax
2226 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2228 allow_naked_reg
= (ask_naked_reg
< 0);
2230 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2232 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2233 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2234 register_prefix
= allow_naked_reg
? "" : "%";
2238 set_intel_mnemonic (int mnemonic_flag
)
2240 intel_mnemonic
= mnemonic_flag
;
2244 set_allow_index_reg (int flag
)
2246 allow_index_reg
= flag
;
2250 set_check (int what
)
2252 enum check_kind
*kind
;
2257 kind
= &operand_check
;
2268 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2271 int e
= get_symbol_name (&string
);
2273 if (strcmp (string
, "none") == 0)
2275 else if (strcmp (string
, "warning") == 0)
2276 *kind
= check_warning
;
2277 else if (strcmp (string
, "error") == 0)
2278 *kind
= check_error
;
2280 as_bad (_("bad argument to %s_check directive."), str
);
2281 (void) restore_line_pointer (e
);
2284 as_bad (_("missing argument for %s_check directive"), str
);
2286 demand_empty_rest_of_line ();
2290 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2291 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2293 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2294 static const char *arch
;
2296 /* Intel LIOM is only supported on ELF. */
2302 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2303 use default_arch. */
2304 arch
= cpu_arch_name
;
2306 arch
= default_arch
;
2309 /* If we are targeting Intel MCU, we must enable it. */
2310 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2311 || new_flag
.bitfield
.cpuiamcu
)
2314 /* If we are targeting Intel L1OM, we must enable it. */
2315 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2316 || new_flag
.bitfield
.cpul1om
)
2319 /* If we are targeting Intel K1OM, we must enable it. */
2320 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2321 || new_flag
.bitfield
.cpuk1om
)
2324 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2329 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2333 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2336 int e
= get_symbol_name (&string
);
2338 i386_cpu_flags flags
;
2340 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2342 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2344 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2348 cpu_arch_name
= cpu_arch
[j
].name
;
2349 cpu_sub_arch_name
= NULL
;
2350 cpu_arch_flags
= cpu_arch
[j
].flags
;
2351 if (flag_code
== CODE_64BIT
)
2353 cpu_arch_flags
.bitfield
.cpu64
= 1;
2354 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2358 cpu_arch_flags
.bitfield
.cpu64
= 0;
2359 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2361 cpu_arch_isa
= cpu_arch
[j
].type
;
2362 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2363 if (!cpu_arch_tune_set
)
2365 cpu_arch_tune
= cpu_arch_isa
;
2366 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2371 if (!cpu_arch
[j
].negated
)
2372 flags
= cpu_flags_or (cpu_arch_flags
,
2375 flags
= cpu_flags_and_not (cpu_arch_flags
,
2378 if (!valid_iamcu_cpu_flags (&flags
))
2379 as_fatal (_("`%s' isn't valid for Intel MCU"),
2381 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2383 if (cpu_sub_arch_name
)
2385 char *name
= cpu_sub_arch_name
;
2386 cpu_sub_arch_name
= concat (name
,
2388 (const char *) NULL
);
2392 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2393 cpu_arch_flags
= flags
;
2394 cpu_arch_isa_flags
= flags
;
2396 (void) restore_line_pointer (e
);
2397 demand_empty_rest_of_line ();
2401 if (j
>= ARRAY_SIZE (cpu_arch
))
2402 as_bad (_("no such architecture: `%s'"), string
);
2404 *input_line_pointer
= e
;
2407 as_bad (_("missing cpu architecture"));
2409 no_cond_jump_promotion
= 0;
2410 if (*input_line_pointer
== ','
2411 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2416 ++input_line_pointer
;
2417 e
= get_symbol_name (&string
);
2419 if (strcmp (string
, "nojumps") == 0)
2420 no_cond_jump_promotion
= 1;
2421 else if (strcmp (string
, "jumps") == 0)
2424 as_bad (_("no such architecture modifier: `%s'"), string
);
2426 (void) restore_line_pointer (e
);
2429 demand_empty_rest_of_line ();
2432 enum bfd_architecture
2435 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2437 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2438 || flag_code
!= CODE_64BIT
)
2439 as_fatal (_("Intel L1OM is 64bit ELF only"));
2440 return bfd_arch_l1om
;
2442 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2444 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2445 || flag_code
!= CODE_64BIT
)
2446 as_fatal (_("Intel K1OM is 64bit ELF only"));
2447 return bfd_arch_k1om
;
2449 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2451 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2452 || flag_code
== CODE_64BIT
)
2453 as_fatal (_("Intel MCU is 32bit ELF only"));
2454 return bfd_arch_iamcu
;
2457 return bfd_arch_i386
;
2463 if (!strncmp (default_arch
, "x86_64", 6))
2465 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2467 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2468 || default_arch
[6] != '\0')
2469 as_fatal (_("Intel L1OM is 64bit ELF only"));
2470 return bfd_mach_l1om
;
2472 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2474 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2475 || default_arch
[6] != '\0')
2476 as_fatal (_("Intel K1OM is 64bit ELF only"));
2477 return bfd_mach_k1om
;
2479 else if (default_arch
[6] == '\0')
2480 return bfd_mach_x86_64
;
2482 return bfd_mach_x64_32
;
2484 else if (!strcmp (default_arch
, "i386")
2485 || !strcmp (default_arch
, "iamcu"))
2487 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2489 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2490 as_fatal (_("Intel MCU is 32bit ELF only"));
2491 return bfd_mach_i386_iamcu
;
2494 return bfd_mach_i386_i386
;
2497 as_fatal (_("unknown architecture"));
2503 const char *hash_err
;
2505 /* Initialize op_hash hash table. */
2506 op_hash
= hash_new ();
2509 const insn_template
*optab
;
2510 templates
*core_optab
;
2512 /* Setup for loop. */
2514 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2515 core_optab
->start
= optab
;
2520 if (optab
->name
== NULL
2521 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2523 /* different name --> ship out current template list;
2524 add to hash table; & begin anew. */
2525 core_optab
->end
= optab
;
2526 hash_err
= hash_insert (op_hash
,
2528 (void *) core_optab
);
2531 as_fatal (_("can't hash %s: %s"),
2535 if (optab
->name
== NULL
)
2537 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2538 core_optab
->start
= optab
;
2543 /* Initialize reg_hash hash table. */
2544 reg_hash
= hash_new ();
2546 const reg_entry
*regtab
;
2547 unsigned int regtab_size
= i386_regtab_size
;
2549 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2551 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2553 as_fatal (_("can't hash %s: %s"),
2559 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2564 for (c
= 0; c
< 256; c
++)
2569 mnemonic_chars
[c
] = c
;
2570 register_chars
[c
] = c
;
2571 operand_chars
[c
] = c
;
2573 else if (ISLOWER (c
))
2575 mnemonic_chars
[c
] = c
;
2576 register_chars
[c
] = c
;
2577 operand_chars
[c
] = c
;
2579 else if (ISUPPER (c
))
2581 mnemonic_chars
[c
] = TOLOWER (c
);
2582 register_chars
[c
] = mnemonic_chars
[c
];
2583 operand_chars
[c
] = c
;
2585 else if (c
== '{' || c
== '}')
2586 operand_chars
[c
] = c
;
2588 if (ISALPHA (c
) || ISDIGIT (c
))
2589 identifier_chars
[c
] = c
;
2592 identifier_chars
[c
] = c
;
2593 operand_chars
[c
] = c
;
2598 identifier_chars
['@'] = '@';
2601 identifier_chars
['?'] = '?';
2602 operand_chars
['?'] = '?';
2604 digit_chars
['-'] = '-';
2605 mnemonic_chars
['_'] = '_';
2606 mnemonic_chars
['-'] = '-';
2607 mnemonic_chars
['.'] = '.';
2608 identifier_chars
['_'] = '_';
2609 identifier_chars
['.'] = '.';
2611 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2612 operand_chars
[(unsigned char) *p
] = *p
;
2615 if (flag_code
== CODE_64BIT
)
2617 #if defined (OBJ_COFF) && defined (TE_PE)
2618 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2621 x86_dwarf2_return_column
= 16;
2623 x86_cie_data_alignment
= -8;
2627 x86_dwarf2_return_column
= 8;
2628 x86_cie_data_alignment
= -4;
2633 i386_print_statistics (FILE *file
)
2635 hash_print_statistics (file
, "i386 opcode", op_hash
);
2636 hash_print_statistics (file
, "i386 register", reg_hash
);
2641 /* Debugging routines for md_assemble. */
2642 static void pte (insn_template
*);
2643 static void pt (i386_operand_type
);
2644 static void pe (expressionS
*);
2645 static void ps (symbolS
*);
2648 pi (char *line
, i386_insn
*x
)
2652 fprintf (stdout
, "%s: template ", line
);
2654 fprintf (stdout
, " address: base %s index %s scale %x\n",
2655 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2656 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2657 x
->log2_scale_factor
);
2658 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2659 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2660 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2661 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2662 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2663 (x
->rex
& REX_W
) != 0,
2664 (x
->rex
& REX_R
) != 0,
2665 (x
->rex
& REX_X
) != 0,
2666 (x
->rex
& REX_B
) != 0);
2667 for (j
= 0; j
< x
->operands
; j
++)
2669 fprintf (stdout
, " #%d: ", j
+ 1);
2671 fprintf (stdout
, "\n");
2672 if (x
->types
[j
].bitfield
.reg8
2673 || x
->types
[j
].bitfield
.reg16
2674 || x
->types
[j
].bitfield
.reg32
2675 || x
->types
[j
].bitfield
.reg64
2676 || x
->types
[j
].bitfield
.regmmx
2677 || x
->types
[j
].bitfield
.regxmm
2678 || x
->types
[j
].bitfield
.regymm
2679 || x
->types
[j
].bitfield
.regzmm
2680 || x
->types
[j
].bitfield
.sreg2
2681 || x
->types
[j
].bitfield
.sreg3
2682 || x
->types
[j
].bitfield
.control
2683 || x
->types
[j
].bitfield
.debug
2684 || x
->types
[j
].bitfield
.test
)
2685 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2686 if (operand_type_check (x
->types
[j
], imm
))
2688 if (operand_type_check (x
->types
[j
], disp
))
2689 pe (x
->op
[j
].disps
);
2694 pte (insn_template
*t
)
2697 fprintf (stdout
, " %d operands ", t
->operands
);
2698 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2699 if (t
->extension_opcode
!= None
)
2700 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2701 if (t
->opcode_modifier
.d
)
2702 fprintf (stdout
, "D");
2703 if (t
->opcode_modifier
.w
)
2704 fprintf (stdout
, "W");
2705 fprintf (stdout
, "\n");
2706 for (j
= 0; j
< t
->operands
; j
++)
2708 fprintf (stdout
, " #%d type ", j
+ 1);
2709 pt (t
->operand_types
[j
]);
2710 fprintf (stdout
, "\n");
2717 fprintf (stdout
, " operation %d\n", e
->X_op
);
2718 fprintf (stdout
, " add_number %ld (%lx)\n",
2719 (long) e
->X_add_number
, (long) e
->X_add_number
);
2720 if (e
->X_add_symbol
)
2722 fprintf (stdout
, " add_symbol ");
2723 ps (e
->X_add_symbol
);
2724 fprintf (stdout
, "\n");
2728 fprintf (stdout
, " op_symbol ");
2729 ps (e
->X_op_symbol
);
2730 fprintf (stdout
, "\n");
2737 fprintf (stdout
, "%s type %s%s",
2739 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2740 segment_name (S_GET_SEGMENT (s
)));
2743 static struct type_name
2745 i386_operand_type mask
;
2748 const type_names
[] =
2750 { OPERAND_TYPE_REG8
, "r8" },
2751 { OPERAND_TYPE_REG16
, "r16" },
2752 { OPERAND_TYPE_REG32
, "r32" },
2753 { OPERAND_TYPE_REG64
, "r64" },
2754 { OPERAND_TYPE_IMM8
, "i8" },
2755 { OPERAND_TYPE_IMM8
, "i8s" },
2756 { OPERAND_TYPE_IMM16
, "i16" },
2757 { OPERAND_TYPE_IMM32
, "i32" },
2758 { OPERAND_TYPE_IMM32S
, "i32s" },
2759 { OPERAND_TYPE_IMM64
, "i64" },
2760 { OPERAND_TYPE_IMM1
, "i1" },
2761 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2762 { OPERAND_TYPE_DISP8
, "d8" },
2763 { OPERAND_TYPE_DISP16
, "d16" },
2764 { OPERAND_TYPE_DISP32
, "d32" },
2765 { OPERAND_TYPE_DISP32S
, "d32s" },
2766 { OPERAND_TYPE_DISP64
, "d64" },
2767 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2768 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2769 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2770 { OPERAND_TYPE_CONTROL
, "control reg" },
2771 { OPERAND_TYPE_TEST
, "test reg" },
2772 { OPERAND_TYPE_DEBUG
, "debug reg" },
2773 { OPERAND_TYPE_FLOATREG
, "FReg" },
2774 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2775 { OPERAND_TYPE_SREG2
, "SReg2" },
2776 { OPERAND_TYPE_SREG3
, "SReg3" },
2777 { OPERAND_TYPE_ACC
, "Acc" },
2778 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2779 { OPERAND_TYPE_REGMMX
, "rMMX" },
2780 { OPERAND_TYPE_REGXMM
, "rXMM" },
2781 { OPERAND_TYPE_REGYMM
, "rYMM" },
2782 { OPERAND_TYPE_REGZMM
, "rZMM" },
2783 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2784 { OPERAND_TYPE_ESSEG
, "es" },
2788 pt (i386_operand_type t
)
2791 i386_operand_type a
;
2793 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2795 a
= operand_type_and (t
, type_names
[j
].mask
);
2796 if (!operand_type_all_zero (&a
))
2797 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2802 #endif /* DEBUG386 */
2804 static bfd_reloc_code_real_type
2805 reloc (unsigned int size
,
2808 bfd_reloc_code_real_type other
)
2810 if (other
!= NO_RELOC
)
2812 reloc_howto_type
*rel
;
2817 case BFD_RELOC_X86_64_GOT32
:
2818 return BFD_RELOC_X86_64_GOT64
;
2820 case BFD_RELOC_X86_64_GOTPLT64
:
2821 return BFD_RELOC_X86_64_GOTPLT64
;
2823 case BFD_RELOC_X86_64_PLTOFF64
:
2824 return BFD_RELOC_X86_64_PLTOFF64
;
2826 case BFD_RELOC_X86_64_GOTPC32
:
2827 other
= BFD_RELOC_X86_64_GOTPC64
;
2829 case BFD_RELOC_X86_64_GOTPCREL
:
2830 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2832 case BFD_RELOC_X86_64_TPOFF32
:
2833 other
= BFD_RELOC_X86_64_TPOFF64
;
2835 case BFD_RELOC_X86_64_DTPOFF32
:
2836 other
= BFD_RELOC_X86_64_DTPOFF64
;
2842 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2843 if (other
== BFD_RELOC_SIZE32
)
2846 other
= BFD_RELOC_SIZE64
;
2849 as_bad (_("there are no pc-relative size relocations"));
2855 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2856 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2859 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2861 as_bad (_("unknown relocation (%u)"), other
);
2862 else if (size
!= bfd_get_reloc_size (rel
))
2863 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2864 bfd_get_reloc_size (rel
),
2866 else if (pcrel
&& !rel
->pc_relative
)
2867 as_bad (_("non-pc-relative relocation for pc-relative field"));
2868 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2870 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2872 as_bad (_("relocated field and relocation type differ in signedness"));
2881 as_bad (_("there are no unsigned pc-relative relocations"));
2884 case 1: return BFD_RELOC_8_PCREL
;
2885 case 2: return BFD_RELOC_16_PCREL
;
2886 case 4: return BFD_RELOC_32_PCREL
;
2887 case 8: return BFD_RELOC_64_PCREL
;
2889 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2896 case 4: return BFD_RELOC_X86_64_32S
;
2901 case 1: return BFD_RELOC_8
;
2902 case 2: return BFD_RELOC_16
;
2903 case 4: return BFD_RELOC_32
;
2904 case 8: return BFD_RELOC_64
;
2906 as_bad (_("cannot do %s %u byte relocation"),
2907 sign
> 0 ? "signed" : "unsigned", size
);
2913 /* Here we decide which fixups can be adjusted to make them relative to
2914 the beginning of the section instead of the symbol. Basically we need
2915 to make sure that the dynamic relocations are done correctly, so in
2916 some cases we force the original symbol to be used. */
2919 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2921 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2925 /* Don't adjust pc-relative references to merge sections in 64-bit
2927 if (use_rela_relocations
2928 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2932 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2933 and changed later by validate_fix. */
2934 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2935 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2938 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2939 for size relocations. */
2940 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2941 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2942 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2943 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2944 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2945 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
2946 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2947 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2948 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2949 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2950 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2951 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2952 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2953 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2954 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2955 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2956 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2957 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2958 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2959 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
2960 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
2961 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2962 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2963 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2964 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2965 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2966 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2967 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2968 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2969 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2970 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2971 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2972 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2979 intel_float_operand (const char *mnemonic
)
2981 /* Note that the value returned is meaningful only for opcodes with (memory)
2982 operands, hence the code here is free to improperly handle opcodes that
2983 have no operands (for better performance and smaller code). */
2985 if (mnemonic
[0] != 'f')
2986 return 0; /* non-math */
2988 switch (mnemonic
[1])
2990 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2991 the fs segment override prefix not currently handled because no
2992 call path can make opcodes without operands get here */
2994 return 2 /* integer op */;
2996 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2997 return 3; /* fldcw/fldenv */
3000 if (mnemonic
[2] != 'o' /* fnop */)
3001 return 3; /* non-waiting control op */
3004 if (mnemonic
[2] == 's')
3005 return 3; /* frstor/frstpm */
3008 if (mnemonic
[2] == 'a')
3009 return 3; /* fsave */
3010 if (mnemonic
[2] == 't')
3012 switch (mnemonic
[3])
3014 case 'c': /* fstcw */
3015 case 'd': /* fstdw */
3016 case 'e': /* fstenv */
3017 case 's': /* fsts[gw] */
3023 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3024 return 0; /* fxsave/fxrstor are not really math ops */
3031 /* Build the VEX prefix. */
3034 build_vex_prefix (const insn_template
*t
)
3036 unsigned int register_specifier
;
3037 unsigned int implied_prefix
;
3038 unsigned int vector_length
;
3040 /* Check register specifier. */
3041 if (i
.vex
.register_specifier
)
3043 register_specifier
=
3044 ~register_number (i
.vex
.register_specifier
) & 0xf;
3045 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3048 register_specifier
= 0xf;
3050 /* Use 2-byte VEX prefix by swappping destination and source
3053 && i
.operands
== i
.reg_operands
3054 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3055 && i
.tm
.opcode_modifier
.s
3058 unsigned int xchg
= i
.operands
- 1;
3059 union i386_op temp_op
;
3060 i386_operand_type temp_type
;
3062 temp_type
= i
.types
[xchg
];
3063 i
.types
[xchg
] = i
.types
[0];
3064 i
.types
[0] = temp_type
;
3065 temp_op
= i
.op
[xchg
];
3066 i
.op
[xchg
] = i
.op
[0];
3069 gas_assert (i
.rm
.mode
== 3);
3073 i
.rm
.regmem
= i
.rm
.reg
;
3076 /* Use the next insn. */
3080 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3081 vector_length
= avxscalar
;
3083 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3085 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3090 case DATA_PREFIX_OPCODE
:
3093 case REPE_PREFIX_OPCODE
:
3096 case REPNE_PREFIX_OPCODE
:
3103 /* Use 2-byte VEX prefix if possible. */
3104 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3105 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3106 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3108 /* 2-byte VEX prefix. */
3112 i
.vex
.bytes
[0] = 0xc5;
3114 /* Check the REX.R bit. */
3115 r
= (i
.rex
& REX_R
) ? 0 : 1;
3116 i
.vex
.bytes
[1] = (r
<< 7
3117 | register_specifier
<< 3
3118 | vector_length
<< 2
3123 /* 3-byte VEX prefix. */
3128 switch (i
.tm
.opcode_modifier
.vexopcode
)
3132 i
.vex
.bytes
[0] = 0xc4;
3136 i
.vex
.bytes
[0] = 0xc4;
3140 i
.vex
.bytes
[0] = 0xc4;
3144 i
.vex
.bytes
[0] = 0x8f;
3148 i
.vex
.bytes
[0] = 0x8f;
3152 i
.vex
.bytes
[0] = 0x8f;
3158 /* The high 3 bits of the second VEX byte are 1's compliment
3159 of RXB bits from REX. */
3160 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3162 /* Check the REX.W bit. */
3163 w
= (i
.rex
& REX_W
) ? 1 : 0;
3164 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3167 i
.vex
.bytes
[2] = (w
<< 7
3168 | register_specifier
<< 3
3169 | vector_length
<< 2
3174 /* Build the EVEX prefix. */
3177 build_evex_prefix (void)
3179 unsigned int register_specifier
;
3180 unsigned int implied_prefix
;
3182 rex_byte vrex_used
= 0;
3184 /* Check register specifier. */
3185 if (i
.vex
.register_specifier
)
3187 gas_assert ((i
.vrex
& REX_X
) == 0);
3189 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3190 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3191 register_specifier
+= 8;
3192 /* The upper 16 registers are encoded in the fourth byte of the
3194 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3195 i
.vex
.bytes
[3] = 0x8;
3196 register_specifier
= ~register_specifier
& 0xf;
3200 register_specifier
= 0xf;
3202 /* Encode upper 16 vector index register in the fourth byte of
3204 if (!(i
.vrex
& REX_X
))
3205 i
.vex
.bytes
[3] = 0x8;
3210 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3215 case DATA_PREFIX_OPCODE
:
3218 case REPE_PREFIX_OPCODE
:
3221 case REPNE_PREFIX_OPCODE
:
3228 /* 4 byte EVEX prefix. */
3230 i
.vex
.bytes
[0] = 0x62;
3233 switch (i
.tm
.opcode_modifier
.vexopcode
)
3249 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3251 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3253 /* The fifth bit of the second EVEX byte is 1's compliment of the
3254 REX_R bit in VREX. */
3255 if (!(i
.vrex
& REX_R
))
3256 i
.vex
.bytes
[1] |= 0x10;
3260 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3262 /* When all operands are registers, the REX_X bit in REX is not
3263 used. We reuse it to encode the upper 16 registers, which is
3264 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3265 as 1's compliment. */
3266 if ((i
.vrex
& REX_B
))
3269 i
.vex
.bytes
[1] &= ~0x40;
3273 /* EVEX instructions shouldn't need the REX prefix. */
3274 i
.vrex
&= ~vrex_used
;
3275 gas_assert (i
.vrex
== 0);
3277 /* Check the REX.W bit. */
3278 w
= (i
.rex
& REX_W
) ? 1 : 0;
3279 if (i
.tm
.opcode_modifier
.vexw
)
3281 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3284 /* If w is not set it means we are dealing with WIG instruction. */
3287 if (evexwig
== evexw1
)
3291 /* Encode the U bit. */
3292 implied_prefix
|= 0x4;
3294 /* The third byte of the EVEX prefix. */
3295 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3297 /* The fourth byte of the EVEX prefix. */
3298 /* The zeroing-masking bit. */
3299 if (i
.mask
&& i
.mask
->zeroing
)
3300 i
.vex
.bytes
[3] |= 0x80;
3302 /* Don't always set the broadcast bit if there is no RC. */
3305 /* Encode the vector length. */
3306 unsigned int vec_length
;
3308 switch (i
.tm
.opcode_modifier
.evex
)
3310 case EVEXLIG
: /* LL' is ignored */
3311 vec_length
= evexlig
<< 5;
3314 vec_length
= 0 << 5;
3317 vec_length
= 1 << 5;
3320 vec_length
= 2 << 5;
3326 i
.vex
.bytes
[3] |= vec_length
;
3327 /* Encode the broadcast bit. */
3329 i
.vex
.bytes
[3] |= 0x10;
3333 if (i
.rounding
->type
!= saeonly
)
3334 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3336 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3339 if (i
.mask
&& i
.mask
->mask
)
3340 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3344 process_immext (void)
3348 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3351 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3352 with an opcode suffix which is coded in the same place as an
3353 8-bit immediate field would be.
3354 Here we check those operands and remove them afterwards. */
3357 for (x
= 0; x
< i
.operands
; x
++)
3358 if (register_number (i
.op
[x
].regs
) != x
)
3359 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3360 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3366 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3368 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3369 suffix which is coded in the same place as an 8-bit immediate
3371 Here we check those operands and remove them afterwards. */
3374 if (i
.operands
!= 3)
3377 for (x
= 0; x
< 2; x
++)
3378 if (register_number (i
.op
[x
].regs
) != x
)
3379 goto bad_register_operand
;
3381 /* Check for third operand for mwaitx/monitorx insn. */
3382 if (register_number (i
.op
[x
].regs
)
3383 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3385 bad_register_operand
:
3386 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3387 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3394 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3395 which is coded in the same place as an 8-bit immediate field
3396 would be. Here we fake an 8-bit immediate operand from the
3397 opcode suffix stored in tm.extension_opcode.
3399 AVX instructions also use this encoding, for some of
3400 3 argument instructions. */
3402 gas_assert (i
.imm_operands
<= 1
3404 || ((i
.tm
.opcode_modifier
.vex
3405 || i
.tm
.opcode_modifier
.evex
)
3406 && i
.operands
<= 4)));
3408 exp
= &im_expressions
[i
.imm_operands
++];
3409 i
.op
[i
.operands
].imms
= exp
;
3410 i
.types
[i
.operands
] = imm8
;
3412 exp
->X_op
= O_constant
;
3413 exp
->X_add_number
= i
.tm
.extension_opcode
;
3414 i
.tm
.extension_opcode
= None
;
3421 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3426 as_bad (_("invalid instruction `%s' after `%s'"),
3427 i
.tm
.name
, i
.hle_prefix
);
3430 if (i
.prefix
[LOCK_PREFIX
])
3432 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3436 case HLEPrefixRelease
:
3437 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3439 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3443 if (i
.mem_operands
== 0
3444 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3446 as_bad (_("memory destination needed for instruction `%s'"
3447 " after `xrelease'"), i
.tm
.name
);
3454 /* This is the guts of the machine-dependent assembler. LINE points to a
3455 machine dependent instruction. This function is supposed to emit
3456 the frags/bytes it assembles to. */
3459 md_assemble (char *line
)
3462 char mnemonic
[MAX_MNEM_SIZE
];
3463 const insn_template
*t
;
3465 /* Initialize globals. */
3466 memset (&i
, '\0', sizeof (i
));
3467 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3468 i
.reloc
[j
] = NO_RELOC
;
3469 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3470 memset (im_expressions
, '\0', sizeof (im_expressions
));
3471 save_stack_p
= save_stack
;
3473 /* First parse an instruction mnemonic & call i386_operand for the operands.
3474 We assume that the scrubber has arranged it so that line[0] is the valid
3475 start of a (possibly prefixed) mnemonic. */
3477 line
= parse_insn (line
, mnemonic
);
3481 line
= parse_operands (line
, mnemonic
);
3486 /* Now we've parsed the mnemonic into a set of templates, and have the
3487 operands at hand. */
3489 /* All intel opcodes have reversed operands except for "bound" and
3490 "enter". We also don't reverse intersegment "jmp" and "call"
3491 instructions with 2 immediate operands so that the immediate segment
3492 precedes the offset, as it does when in AT&T mode. */
3495 && (strcmp (mnemonic
, "bound") != 0)
3496 && (strcmp (mnemonic
, "invlpga") != 0)
3497 && !(operand_type_check (i
.types
[0], imm
)
3498 && operand_type_check (i
.types
[1], imm
)))
3501 /* The order of the immediates should be reversed
3502 for 2 immediates extrq and insertq instructions */
3503 if (i
.imm_operands
== 2
3504 && (strcmp (mnemonic
, "extrq") == 0
3505 || strcmp (mnemonic
, "insertq") == 0))
3506 swap_2_operands (0, 1);
3511 /* Don't optimize displacement for movabs since it only takes 64bit
3514 && i
.disp_encoding
!= disp_encoding_32bit
3515 && (flag_code
!= CODE_64BIT
3516 || strcmp (mnemonic
, "movabs") != 0))
3519 /* Next, we find a template that matches the given insn,
3520 making sure the overlap of the given operands types is consistent
3521 with the template operand types. */
3523 if (!(t
= match_template ()))
3526 if (sse_check
!= check_none
3527 && !i
.tm
.opcode_modifier
.noavx
3528 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3529 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3530 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3531 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3532 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3533 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3535 (sse_check
== check_warning
3537 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3540 /* Zap movzx and movsx suffix. The suffix has been set from
3541 "word ptr" or "byte ptr" on the source operand in Intel syntax
3542 or extracted from mnemonic in AT&T syntax. But we'll use
3543 the destination register to choose the suffix for encoding. */
3544 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3546 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3547 there is no suffix, the default will be byte extension. */
3548 if (i
.reg_operands
!= 2
3551 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3556 if (i
.tm
.opcode_modifier
.fwait
)
3557 if (!add_prefix (FWAIT_OPCODE
))
3560 /* Check if REP prefix is OK. */
3561 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3563 as_bad (_("invalid instruction `%s' after `%s'"),
3564 i
.tm
.name
, i
.rep_prefix
);
3568 /* Check for lock without a lockable instruction. Destination operand
3569 must be memory unless it is xchg (0x86). */
3570 if (i
.prefix
[LOCK_PREFIX
]
3571 && (!i
.tm
.opcode_modifier
.islockable
3572 || i
.mem_operands
== 0
3573 || (i
.tm
.base_opcode
!= 0x86
3574 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3576 as_bad (_("expecting lockable instruction after `lock'"));
3580 /* Check if HLE prefix is OK. */
3581 if (i
.hle_prefix
&& !check_hle ())
3584 /* Check BND prefix. */
3585 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3586 as_bad (_("expecting valid branch instruction after `bnd'"));
3588 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3589 && flag_code
== CODE_64BIT
3590 && i
.prefix
[ADDR_PREFIX
])
3591 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3593 /* Insert BND prefix. */
3595 && i
.tm
.opcode_modifier
.bndprefixok
3596 && !i
.prefix
[BND_PREFIX
])
3597 add_prefix (BND_PREFIX_OPCODE
);
3599 /* Check string instruction segment overrides. */
3600 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3602 if (!check_string ())
3604 i
.disp_operands
= 0;
3607 if (!process_suffix ())
3610 /* Update operand types. */
3611 for (j
= 0; j
< i
.operands
; j
++)
3612 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3614 /* Make still unresolved immediate matches conform to size of immediate
3615 given in i.suffix. */
3616 if (!finalize_imm ())
3619 if (i
.types
[0].bitfield
.imm1
)
3620 i
.imm_operands
= 0; /* kludge for shift insns. */
3622 /* We only need to check those implicit registers for instructions
3623 with 3 operands or less. */
3624 if (i
.operands
<= 3)
3625 for (j
= 0; j
< i
.operands
; j
++)
3626 if (i
.types
[j
].bitfield
.inoutportreg
3627 || i
.types
[j
].bitfield
.shiftcount
3628 || i
.types
[j
].bitfield
.acc
3629 || i
.types
[j
].bitfield
.floatacc
)
3632 /* ImmExt should be processed after SSE2AVX. */
3633 if (!i
.tm
.opcode_modifier
.sse2avx
3634 && i
.tm
.opcode_modifier
.immext
)
3637 /* For insns with operands there are more diddles to do to the opcode. */
3640 if (!process_operands ())
3643 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3645 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3646 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3649 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3651 if (flag_code
== CODE_16BIT
)
3653 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3658 if (i
.tm
.opcode_modifier
.vex
)
3659 build_vex_prefix (t
);
3661 build_evex_prefix ();
3664 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3665 instructions may define INT_OPCODE as well, so avoid this corner
3666 case for those instructions that use MODRM. */
3667 if (i
.tm
.base_opcode
== INT_OPCODE
3668 && !i
.tm
.opcode_modifier
.modrm
3669 && i
.op
[0].imms
->X_add_number
== 3)
3671 i
.tm
.base_opcode
= INT3_OPCODE
;
3675 if ((i
.tm
.opcode_modifier
.jump
3676 || i
.tm
.opcode_modifier
.jumpbyte
3677 || i
.tm
.opcode_modifier
.jumpdword
)
3678 && i
.op
[0].disps
->X_op
== O_constant
)
3680 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3681 the absolute address given by the constant. Since ix86 jumps and
3682 calls are pc relative, we need to generate a reloc. */
3683 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3684 i
.op
[0].disps
->X_op
= O_symbol
;
3687 if (i
.tm
.opcode_modifier
.rex64
)
3690 /* For 8 bit registers we need an empty rex prefix. Also if the
3691 instruction already has a prefix, we need to convert old
3692 registers to new ones. */
3694 if ((i
.types
[0].bitfield
.reg8
3695 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3696 || (i
.types
[1].bitfield
.reg8
3697 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3698 || ((i
.types
[0].bitfield
.reg8
3699 || i
.types
[1].bitfield
.reg8
)
3704 i
.rex
|= REX_OPCODE
;
3705 for (x
= 0; x
< 2; x
++)
3707 /* Look for 8 bit operand that uses old registers. */
3708 if (i
.types
[x
].bitfield
.reg8
3709 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3711 /* In case it is "hi" register, give up. */
3712 if (i
.op
[x
].regs
->reg_num
> 3)
3713 as_bad (_("can't encode register '%s%s' in an "
3714 "instruction requiring REX prefix."),
3715 register_prefix
, i
.op
[x
].regs
->reg_name
);
3717 /* Otherwise it is equivalent to the extended register.
3718 Since the encoding doesn't change this is merely
3719 cosmetic cleanup for debug output. */
3721 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3727 add_prefix (REX_OPCODE
| i
.rex
);
3729 /* We are ready to output the insn. */
3734 parse_insn (char *line
, char *mnemonic
)
3737 char *token_start
= l
;
3740 const insn_template
*t
;
3746 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3751 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3753 as_bad (_("no such instruction: `%s'"), token_start
);
3758 if (!is_space_char (*l
)
3759 && *l
!= END_OF_INSN
3761 || (*l
!= PREFIX_SEPARATOR
3764 as_bad (_("invalid character %s in mnemonic"),
3765 output_invalid (*l
));
3768 if (token_start
== l
)
3770 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3771 as_bad (_("expecting prefix; got nothing"));
3773 as_bad (_("expecting mnemonic; got nothing"));
3777 /* Look up instruction (or prefix) via hash table. */
3778 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3780 if (*l
!= END_OF_INSN
3781 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3782 && current_templates
3783 && current_templates
->start
->opcode_modifier
.isprefix
)
3785 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3787 as_bad ((flag_code
!= CODE_64BIT
3788 ? _("`%s' is only supported in 64-bit mode")
3789 : _("`%s' is not supported in 64-bit mode")),
3790 current_templates
->start
->name
);
3793 /* If we are in 16-bit mode, do not allow addr16 or data16.
3794 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3795 if ((current_templates
->start
->opcode_modifier
.size16
3796 || current_templates
->start
->opcode_modifier
.size32
)
3797 && flag_code
!= CODE_64BIT
3798 && (current_templates
->start
->opcode_modifier
.size32
3799 ^ (flag_code
== CODE_16BIT
)))
3801 as_bad (_("redundant %s prefix"),
3802 current_templates
->start
->name
);
3805 /* Add prefix, checking for repeated prefixes. */
3806 switch (add_prefix (current_templates
->start
->base_opcode
))
3811 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3812 i
.hle_prefix
= current_templates
->start
->name
;
3813 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3814 i
.bnd_prefix
= current_templates
->start
->name
;
3816 i
.rep_prefix
= current_templates
->start
->name
;
3821 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3828 if (!current_templates
)
3830 /* Check if we should swap operand or force 32bit displacement in
3832 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3834 else if (mnem_p
- 3 == dot_p
3837 i
.disp_encoding
= disp_encoding_8bit
;
3838 else if (mnem_p
- 4 == dot_p
3842 i
.disp_encoding
= disp_encoding_32bit
;
3847 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3850 if (!current_templates
)
3853 /* See if we can get a match by trimming off a suffix. */
3856 case WORD_MNEM_SUFFIX
:
3857 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3858 i
.suffix
= SHORT_MNEM_SUFFIX
;
3860 case BYTE_MNEM_SUFFIX
:
3861 case QWORD_MNEM_SUFFIX
:
3862 i
.suffix
= mnem_p
[-1];
3864 current_templates
= (const templates
*) hash_find (op_hash
,
3867 case SHORT_MNEM_SUFFIX
:
3868 case LONG_MNEM_SUFFIX
:
3871 i
.suffix
= mnem_p
[-1];
3873 current_templates
= (const templates
*) hash_find (op_hash
,
3882 if (intel_float_operand (mnemonic
) == 1)
3883 i
.suffix
= SHORT_MNEM_SUFFIX
;
3885 i
.suffix
= LONG_MNEM_SUFFIX
;
3887 current_templates
= (const templates
*) hash_find (op_hash
,
3892 if (!current_templates
)
3894 as_bad (_("no such instruction: `%s'"), token_start
);
3899 if (current_templates
->start
->opcode_modifier
.jump
3900 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3902 /* Check for a branch hint. We allow ",pt" and ",pn" for
3903 predict taken and predict not taken respectively.
3904 I'm not sure that branch hints actually do anything on loop
3905 and jcxz insns (JumpByte) for current Pentium4 chips. They
3906 may work in the future and it doesn't hurt to accept them
3908 if (l
[0] == ',' && l
[1] == 'p')
3912 if (!add_prefix (DS_PREFIX_OPCODE
))
3916 else if (l
[2] == 'n')
3918 if (!add_prefix (CS_PREFIX_OPCODE
))
3924 /* Any other comma loses. */
3927 as_bad (_("invalid character %s in mnemonic"),
3928 output_invalid (*l
));
3932 /* Check if instruction is supported on specified architecture. */
3934 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3936 supported
|= cpu_flags_match (t
);
3937 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3941 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3943 as_bad (flag_code
== CODE_64BIT
3944 ? _("`%s' is not supported in 64-bit mode")
3945 : _("`%s' is only supported in 64-bit mode"),
3946 current_templates
->start
->name
);
3949 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3951 as_bad (_("`%s' is not supported on `%s%s'"),
3952 current_templates
->start
->name
,
3953 cpu_arch_name
? cpu_arch_name
: default_arch
,
3954 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3959 if (!cpu_arch_flags
.bitfield
.cpui386
3960 && (flag_code
!= CODE_16BIT
))
3962 as_warn (_("use .code16 to ensure correct addressing mode"));
3969 parse_operands (char *l
, const char *mnemonic
)
3973 /* 1 if operand is pending after ','. */
3974 unsigned int expecting_operand
= 0;
3976 /* Non-zero if operand parens not balanced. */
3977 unsigned int paren_not_balanced
;
3979 while (*l
!= END_OF_INSN
)
3981 /* Skip optional white space before operand. */
3982 if (is_space_char (*l
))
3984 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
3986 as_bad (_("invalid character %s before operand %d"),
3987 output_invalid (*l
),
3991 token_start
= l
; /* After white space. */
3992 paren_not_balanced
= 0;
3993 while (paren_not_balanced
|| *l
!= ',')
3995 if (*l
== END_OF_INSN
)
3997 if (paren_not_balanced
)
4000 as_bad (_("unbalanced parenthesis in operand %d."),
4003 as_bad (_("unbalanced brackets in operand %d."),
4008 break; /* we are done */
4010 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4012 as_bad (_("invalid character %s in operand %d"),
4013 output_invalid (*l
),
4020 ++paren_not_balanced
;
4022 --paren_not_balanced
;
4027 ++paren_not_balanced
;
4029 --paren_not_balanced
;
4033 if (l
!= token_start
)
4034 { /* Yes, we've read in another operand. */
4035 unsigned int operand_ok
;
4036 this_operand
= i
.operands
++;
4037 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4038 if (i
.operands
> MAX_OPERANDS
)
4040 as_bad (_("spurious operands; (%d operands/instruction max)"),
4044 /* Now parse operand adding info to 'i' as we go along. */
4045 END_STRING_AND_SAVE (l
);
4049 i386_intel_operand (token_start
,
4050 intel_float_operand (mnemonic
));
4052 operand_ok
= i386_att_operand (token_start
);
4054 RESTORE_END_STRING (l
);
4060 if (expecting_operand
)
4062 expecting_operand_after_comma
:
4063 as_bad (_("expecting operand after ','; got nothing"));
4068 as_bad (_("expecting operand before ','; got nothing"));
4073 /* Now *l must be either ',' or END_OF_INSN. */
4076 if (*++l
== END_OF_INSN
)
4078 /* Just skip it, if it's \n complain. */
4079 goto expecting_operand_after_comma
;
4081 expecting_operand
= 1;
4088 swap_2_operands (int xchg1
, int xchg2
)
4090 union i386_op temp_op
;
4091 i386_operand_type temp_type
;
4092 enum bfd_reloc_code_real temp_reloc
;
4094 temp_type
= i
.types
[xchg2
];
4095 i
.types
[xchg2
] = i
.types
[xchg1
];
4096 i
.types
[xchg1
] = temp_type
;
4097 temp_op
= i
.op
[xchg2
];
4098 i
.op
[xchg2
] = i
.op
[xchg1
];
4099 i
.op
[xchg1
] = temp_op
;
4100 temp_reloc
= i
.reloc
[xchg2
];
4101 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4102 i
.reloc
[xchg1
] = temp_reloc
;
4106 if (i
.mask
->operand
== xchg1
)
4107 i
.mask
->operand
= xchg2
;
4108 else if (i
.mask
->operand
== xchg2
)
4109 i
.mask
->operand
= xchg1
;
4113 if (i
.broadcast
->operand
== xchg1
)
4114 i
.broadcast
->operand
= xchg2
;
4115 else if (i
.broadcast
->operand
== xchg2
)
4116 i
.broadcast
->operand
= xchg1
;
4120 if (i
.rounding
->operand
== xchg1
)
4121 i
.rounding
->operand
= xchg2
;
4122 else if (i
.rounding
->operand
== xchg2
)
4123 i
.rounding
->operand
= xchg1
;
4128 swap_operands (void)
4134 swap_2_operands (1, i
.operands
- 2);
4137 swap_2_operands (0, i
.operands
- 1);
4143 if (i
.mem_operands
== 2)
4145 const seg_entry
*temp_seg
;
4146 temp_seg
= i
.seg
[0];
4147 i
.seg
[0] = i
.seg
[1];
4148 i
.seg
[1] = temp_seg
;
4152 /* Try to ensure constant immediates are represented in the smallest
4157 char guess_suffix
= 0;
4161 guess_suffix
= i
.suffix
;
4162 else if (i
.reg_operands
)
4164 /* Figure out a suffix from the last register operand specified.
4165 We can't do this properly yet, ie. excluding InOutPortReg,
4166 but the following works for instructions with immediates.
4167 In any case, we can't set i.suffix yet. */
4168 for (op
= i
.operands
; --op
>= 0;)
4169 if (i
.types
[op
].bitfield
.reg8
)
4171 guess_suffix
= BYTE_MNEM_SUFFIX
;
4174 else if (i
.types
[op
].bitfield
.reg16
)
4176 guess_suffix
= WORD_MNEM_SUFFIX
;
4179 else if (i
.types
[op
].bitfield
.reg32
)
4181 guess_suffix
= LONG_MNEM_SUFFIX
;
4184 else if (i
.types
[op
].bitfield
.reg64
)
4186 guess_suffix
= QWORD_MNEM_SUFFIX
;
4190 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4191 guess_suffix
= WORD_MNEM_SUFFIX
;
4193 for (op
= i
.operands
; --op
>= 0;)
4194 if (operand_type_check (i
.types
[op
], imm
))
4196 switch (i
.op
[op
].imms
->X_op
)
4199 /* If a suffix is given, this operand may be shortened. */
4200 switch (guess_suffix
)
4202 case LONG_MNEM_SUFFIX
:
4203 i
.types
[op
].bitfield
.imm32
= 1;
4204 i
.types
[op
].bitfield
.imm64
= 1;
4206 case WORD_MNEM_SUFFIX
:
4207 i
.types
[op
].bitfield
.imm16
= 1;
4208 i
.types
[op
].bitfield
.imm32
= 1;
4209 i
.types
[op
].bitfield
.imm32s
= 1;
4210 i
.types
[op
].bitfield
.imm64
= 1;
4212 case BYTE_MNEM_SUFFIX
:
4213 i
.types
[op
].bitfield
.imm8
= 1;
4214 i
.types
[op
].bitfield
.imm8s
= 1;
4215 i
.types
[op
].bitfield
.imm16
= 1;
4216 i
.types
[op
].bitfield
.imm32
= 1;
4217 i
.types
[op
].bitfield
.imm32s
= 1;
4218 i
.types
[op
].bitfield
.imm64
= 1;
4222 /* If this operand is at most 16 bits, convert it
4223 to a signed 16 bit number before trying to see
4224 whether it will fit in an even smaller size.
4225 This allows a 16-bit operand such as $0xffe0 to
4226 be recognised as within Imm8S range. */
4227 if ((i
.types
[op
].bitfield
.imm16
)
4228 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4230 i
.op
[op
].imms
->X_add_number
=
4231 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4234 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4235 if ((i
.types
[op
].bitfield
.imm32
)
4236 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4239 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4240 ^ ((offsetT
) 1 << 31))
4241 - ((offsetT
) 1 << 31));
4245 = operand_type_or (i
.types
[op
],
4246 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4248 /* We must avoid matching of Imm32 templates when 64bit
4249 only immediate is available. */
4250 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4251 i
.types
[op
].bitfield
.imm32
= 0;
4258 /* Symbols and expressions. */
4260 /* Convert symbolic operand to proper sizes for matching, but don't
4261 prevent matching a set of insns that only supports sizes other
4262 than those matching the insn suffix. */
4264 i386_operand_type mask
, allowed
;
4265 const insn_template
*t
;
4267 operand_type_set (&mask
, 0);
4268 operand_type_set (&allowed
, 0);
4270 for (t
= current_templates
->start
;
4271 t
< current_templates
->end
;
4273 allowed
= operand_type_or (allowed
,
4274 t
->operand_types
[op
]);
4275 switch (guess_suffix
)
4277 case QWORD_MNEM_SUFFIX
:
4278 mask
.bitfield
.imm64
= 1;
4279 mask
.bitfield
.imm32s
= 1;
4281 case LONG_MNEM_SUFFIX
:
4282 mask
.bitfield
.imm32
= 1;
4284 case WORD_MNEM_SUFFIX
:
4285 mask
.bitfield
.imm16
= 1;
4287 case BYTE_MNEM_SUFFIX
:
4288 mask
.bitfield
.imm8
= 1;
4293 allowed
= operand_type_and (mask
, allowed
);
4294 if (!operand_type_all_zero (&allowed
))
4295 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4302 /* Try to use the smallest displacement type too. */
4304 optimize_disp (void)
4308 for (op
= i
.operands
; --op
>= 0;)
4309 if (operand_type_check (i
.types
[op
], disp
))
4311 if (i
.op
[op
].disps
->X_op
== O_constant
)
4313 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4315 if (i
.types
[op
].bitfield
.disp16
4316 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4318 /* If this operand is at most 16 bits, convert
4319 to a signed 16 bit number and don't use 64bit
4321 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4322 i
.types
[op
].bitfield
.disp64
= 0;
4325 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4326 if (i
.types
[op
].bitfield
.disp32
4327 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4329 /* If this operand is at most 32 bits, convert
4330 to a signed 32 bit number and don't use 64bit
4332 op_disp
&= (((offsetT
) 2 << 31) - 1);
4333 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4334 i
.types
[op
].bitfield
.disp64
= 0;
4337 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4339 i
.types
[op
].bitfield
.disp8
= 0;
4340 i
.types
[op
].bitfield
.disp16
= 0;
4341 i
.types
[op
].bitfield
.disp32
= 0;
4342 i
.types
[op
].bitfield
.disp32s
= 0;
4343 i
.types
[op
].bitfield
.disp64
= 0;
4347 else if (flag_code
== CODE_64BIT
)
4349 if (fits_in_signed_long (op_disp
))
4351 i
.types
[op
].bitfield
.disp64
= 0;
4352 i
.types
[op
].bitfield
.disp32s
= 1;
4354 if (i
.prefix
[ADDR_PREFIX
]
4355 && fits_in_unsigned_long (op_disp
))
4356 i
.types
[op
].bitfield
.disp32
= 1;
4358 if ((i
.types
[op
].bitfield
.disp32
4359 || i
.types
[op
].bitfield
.disp32s
4360 || i
.types
[op
].bitfield
.disp16
)
4361 && fits_in_signed_byte (op_disp
))
4362 i
.types
[op
].bitfield
.disp8
= 1;
4364 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4365 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4367 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4368 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4369 i
.types
[op
].bitfield
.disp8
= 0;
4370 i
.types
[op
].bitfield
.disp16
= 0;
4371 i
.types
[op
].bitfield
.disp32
= 0;
4372 i
.types
[op
].bitfield
.disp32s
= 0;
4373 i
.types
[op
].bitfield
.disp64
= 0;
4376 /* We only support 64bit displacement on constants. */
4377 i
.types
[op
].bitfield
.disp64
= 0;
4381 /* Check if operands are valid for the instruction. */
4384 check_VecOperands (const insn_template
*t
)
4388 /* Without VSIB byte, we can't have a vector register for index. */
4389 if (!t
->opcode_modifier
.vecsib
4391 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4392 || i
.index_reg
->reg_type
.bitfield
.regymm
4393 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4395 i
.error
= unsupported_vector_index_register
;
4399 /* Check if default mask is allowed. */
4400 if (t
->opcode_modifier
.nodefmask
4401 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4403 i
.error
= no_default_mask
;
4407 /* For VSIB byte, we need a vector register for index, and all vector
4408 registers must be distinct. */
4409 if (t
->opcode_modifier
.vecsib
)
4412 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4413 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4414 || (t
->opcode_modifier
.vecsib
== VecSIB256
4415 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4416 || (t
->opcode_modifier
.vecsib
== VecSIB512
4417 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4419 i
.error
= invalid_vsib_address
;
4423 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4424 if (i
.reg_operands
== 2 && !i
.mask
)
4426 gas_assert (i
.types
[0].bitfield
.regxmm
4427 || i
.types
[0].bitfield
.regymm
);
4428 gas_assert (i
.types
[2].bitfield
.regxmm
4429 || i
.types
[2].bitfield
.regymm
);
4430 if (operand_check
== check_none
)
4432 if (register_number (i
.op
[0].regs
)
4433 != register_number (i
.index_reg
)
4434 && register_number (i
.op
[2].regs
)
4435 != register_number (i
.index_reg
)
4436 && register_number (i
.op
[0].regs
)
4437 != register_number (i
.op
[2].regs
))
4439 if (operand_check
== check_error
)
4441 i
.error
= invalid_vector_register_set
;
4444 as_warn (_("mask, index, and destination registers should be distinct"));
4446 else if (i
.reg_operands
== 1 && i
.mask
)
4448 if ((i
.types
[1].bitfield
.regymm
4449 || i
.types
[1].bitfield
.regzmm
)
4450 && (register_number (i
.op
[1].regs
)
4451 == register_number (i
.index_reg
)))
4453 if (operand_check
== check_error
)
4455 i
.error
= invalid_vector_register_set
;
4458 if (operand_check
!= check_none
)
4459 as_warn (_("index and destination registers should be distinct"));
4464 /* Check if broadcast is supported by the instruction and is applied
4465 to the memory operand. */
4468 int broadcasted_opnd_size
;
4470 /* Check if specified broadcast is supported in this instruction,
4471 and it's applied to memory operand of DWORD or QWORD type,
4472 depending on VecESize. */
4473 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4474 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4475 || (t
->opcode_modifier
.vecesize
== 0
4476 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4477 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4478 || (t
->opcode_modifier
.vecesize
== 1
4479 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4480 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4483 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4484 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4485 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4486 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4487 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4488 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4489 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4490 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4491 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4495 if ((broadcasted_opnd_size
== 256
4496 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4497 || (broadcasted_opnd_size
== 512
4498 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4501 i
.error
= unsupported_broadcast
;
4505 /* If broadcast is supported in this instruction, we need to check if
4506 operand of one-element size isn't specified without broadcast. */
4507 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4509 /* Find memory operand. */
4510 for (op
= 0; op
< i
.operands
; op
++)
4511 if (operand_type_check (i
.types
[op
], anymem
))
4513 gas_assert (op
< i
.operands
);
4514 /* Check size of the memory operand. */
4515 if ((t
->opcode_modifier
.vecesize
== 0
4516 && i
.types
[op
].bitfield
.dword
)
4517 || (t
->opcode_modifier
.vecesize
== 1
4518 && i
.types
[op
].bitfield
.qword
))
4520 i
.error
= broadcast_needed
;
4525 /* Check if requested masking is supported. */
4527 && (!t
->opcode_modifier
.masking
4529 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4531 i
.error
= unsupported_masking
;
4535 /* Check if masking is applied to dest operand. */
4536 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4538 i
.error
= mask_not_on_destination
;
4545 if ((i
.rounding
->type
!= saeonly
4546 && !t
->opcode_modifier
.staticrounding
)
4547 || (i
.rounding
->type
== saeonly
4548 && (t
->opcode_modifier
.staticrounding
4549 || !t
->opcode_modifier
.sae
)))
4551 i
.error
= unsupported_rc_sae
;
4554 /* If the instruction has several immediate operands and one of
4555 them is rounding, the rounding operand should be the last
4556 immediate operand. */
4557 if (i
.imm_operands
> 1
4558 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4560 i
.error
= rc_sae_operand_not_last_imm
;
4565 /* Check vector Disp8 operand. */
4566 if (t
->opcode_modifier
.disp8memshift
)
4569 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4571 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4573 for (op
= 0; op
< i
.operands
; op
++)
4574 if (operand_type_check (i
.types
[op
], disp
)
4575 && i
.op
[op
].disps
->X_op
== O_constant
)
4577 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4578 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4579 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4582 i
.types
[op
].bitfield
.vec_disp8
= 1;
4585 /* Vector insn can only have Vec_Disp8/Disp32 in
4586 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4588 i
.types
[op
].bitfield
.disp8
= 0;
4589 if (flag_code
!= CODE_16BIT
)
4590 i
.types
[op
].bitfield
.disp16
= 0;
4593 else if (flag_code
!= CODE_16BIT
)
4595 /* One form of this instruction supports vector Disp8.
4596 Try vector Disp8 if we need to use Disp32. */
4597 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4599 i
.error
= try_vector_disp8
;
4611 /* Check if operands are valid for the instruction. Update VEX
4615 VEX_check_operands (const insn_template
*t
)
4617 /* VREX is only valid with EVEX prefix. */
4618 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4620 i
.error
= invalid_register_operand
;
4624 if (!t
->opcode_modifier
.vex
)
4627 /* Only check VEX_Imm4, which must be the first operand. */
4628 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4630 if (i
.op
[0].imms
->X_op
!= O_constant
4631 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4637 /* Turn off Imm8 so that update_imm won't complain. */
4638 i
.types
[0] = vec_imm4
;
4644 static const insn_template
*
4645 match_template (void)
4647 /* Points to template once we've found it. */
4648 const insn_template
*t
;
4649 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4650 i386_operand_type overlap4
;
4651 unsigned int found_reverse_match
;
4652 i386_opcode_modifier suffix_check
;
4653 i386_operand_type operand_types
[MAX_OPERANDS
];
4654 int addr_prefix_disp
;
4656 unsigned int found_cpu_match
;
4657 unsigned int check_register
;
4658 enum i386_error specific_error
= 0;
4660 #if MAX_OPERANDS != 5
4661 # error "MAX_OPERANDS must be 5."
4664 found_reverse_match
= 0;
4665 addr_prefix_disp
= -1;
4667 memset (&suffix_check
, 0, sizeof (suffix_check
));
4668 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4669 suffix_check
.no_bsuf
= 1;
4670 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4671 suffix_check
.no_wsuf
= 1;
4672 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4673 suffix_check
.no_ssuf
= 1;
4674 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4675 suffix_check
.no_lsuf
= 1;
4676 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4677 suffix_check
.no_qsuf
= 1;
4678 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4679 suffix_check
.no_ldsuf
= 1;
4681 /* Must have right number of operands. */
4682 i
.error
= number_of_operands_mismatch
;
4684 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4686 addr_prefix_disp
= -1;
4688 if (i
.operands
!= t
->operands
)
4691 /* Check processor support. */
4692 i
.error
= unsupported
;
4693 found_cpu_match
= (cpu_flags_match (t
)
4694 == CPU_FLAGS_PERFECT_MATCH
);
4695 if (!found_cpu_match
)
4698 /* Check old gcc support. */
4699 i
.error
= old_gcc_only
;
4700 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4703 /* Check AT&T mnemonic. */
4704 i
.error
= unsupported_with_intel_mnemonic
;
4705 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4708 /* Check AT&T/Intel syntax. */
4709 i
.error
= unsupported_syntax
;
4710 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4711 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4714 /* Check the suffix, except for some instructions in intel mode. */
4715 i
.error
= invalid_instruction_suffix
;
4716 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4717 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4718 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4719 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4720 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4721 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4722 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4725 if (!operand_size_match (t
))
4728 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4729 operand_types
[j
] = t
->operand_types
[j
];
4731 /* In general, don't allow 64-bit operands in 32-bit mode. */
4732 if (i
.suffix
== QWORD_MNEM_SUFFIX
4733 && flag_code
!= CODE_64BIT
4735 ? (!t
->opcode_modifier
.ignoresize
4736 && !intel_float_operand (t
->name
))
4737 : intel_float_operand (t
->name
) != 2)
4738 && ((!operand_types
[0].bitfield
.regmmx
4739 && !operand_types
[0].bitfield
.regxmm
4740 && !operand_types
[0].bitfield
.regymm
4741 && !operand_types
[0].bitfield
.regzmm
)
4742 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4743 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4744 && operand_types
[t
->operands
> 1].bitfield
.regymm
4745 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4746 && (t
->base_opcode
!= 0x0fc7
4747 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4750 /* In general, don't allow 32-bit operands on pre-386. */
4751 else if (i
.suffix
== LONG_MNEM_SUFFIX
4752 && !cpu_arch_flags
.bitfield
.cpui386
4754 ? (!t
->opcode_modifier
.ignoresize
4755 && !intel_float_operand (t
->name
))
4756 : intel_float_operand (t
->name
) != 2)
4757 && ((!operand_types
[0].bitfield
.regmmx
4758 && !operand_types
[0].bitfield
.regxmm
)
4759 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4760 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4763 /* Do not verify operands when there are none. */
4767 /* We've found a match; break out of loop. */
4771 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4772 into Disp32/Disp16/Disp32 operand. */
4773 if (i
.prefix
[ADDR_PREFIX
] != 0)
4775 /* There should be only one Disp operand. */
4779 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4781 if (operand_types
[j
].bitfield
.disp16
)
4783 addr_prefix_disp
= j
;
4784 operand_types
[j
].bitfield
.disp32
= 1;
4785 operand_types
[j
].bitfield
.disp16
= 0;
4791 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4793 if (operand_types
[j
].bitfield
.disp32
)
4795 addr_prefix_disp
= j
;
4796 operand_types
[j
].bitfield
.disp32
= 0;
4797 operand_types
[j
].bitfield
.disp16
= 1;
4803 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4805 if (operand_types
[j
].bitfield
.disp64
)
4807 addr_prefix_disp
= j
;
4808 operand_types
[j
].bitfield
.disp64
= 0;
4809 operand_types
[j
].bitfield
.disp32
= 1;
4817 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4818 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
4821 /* We check register size if needed. */
4822 check_register
= t
->opcode_modifier
.checkregsize
;
4823 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4824 switch (t
->operands
)
4827 if (!operand_type_match (overlap0
, i
.types
[0]))
4831 /* xchg %eax, %eax is a special case. It is an aliase for nop
4832 only in 32bit mode and we can use opcode 0x90. In 64bit
4833 mode, we can't use 0x90 for xchg %eax, %eax since it should
4834 zero-extend %eax to %rax. */
4835 if (flag_code
== CODE_64BIT
4836 && t
->base_opcode
== 0x90
4837 && operand_type_equal (&i
.types
[0], &acc32
)
4838 && operand_type_equal (&i
.types
[1], &acc32
))
4842 /* If we swap operand in encoding, we either match
4843 the next one or reverse direction of operands. */
4844 if (t
->opcode_modifier
.s
)
4846 else if (t
->opcode_modifier
.d
)
4851 /* If we swap operand in encoding, we match the next one. */
4852 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4856 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4857 if (!operand_type_match (overlap0
, i
.types
[0])
4858 || !operand_type_match (overlap1
, i
.types
[1])
4860 && !operand_type_register_match (overlap0
, i
.types
[0],
4862 overlap1
, i
.types
[1],
4865 /* Check if other direction is valid ... */
4866 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4870 /* Try reversing direction of operands. */
4871 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4872 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4873 if (!operand_type_match (overlap0
, i
.types
[0])
4874 || !operand_type_match (overlap1
, i
.types
[1])
4876 && !operand_type_register_match (overlap0
,
4883 /* Does not match either direction. */
4886 /* found_reverse_match holds which of D or FloatDR
4888 if (t
->opcode_modifier
.d
)
4889 found_reverse_match
= Opcode_D
;
4890 else if (t
->opcode_modifier
.floatd
)
4891 found_reverse_match
= Opcode_FloatD
;
4893 found_reverse_match
= 0;
4894 if (t
->opcode_modifier
.floatr
)
4895 found_reverse_match
|= Opcode_FloatR
;
4899 /* Found a forward 2 operand match here. */
4900 switch (t
->operands
)
4903 overlap4
= operand_type_and (i
.types
[4],
4906 overlap3
= operand_type_and (i
.types
[3],
4909 overlap2
= operand_type_and (i
.types
[2],
4914 switch (t
->operands
)
4917 if (!operand_type_match (overlap4
, i
.types
[4])
4918 || !operand_type_register_match (overlap3
,
4926 if (!operand_type_match (overlap3
, i
.types
[3])
4928 && !operand_type_register_match (overlap2
,
4936 /* Here we make use of the fact that there are no
4937 reverse match 3 operand instructions, and all 3
4938 operand instructions only need to be checked for
4939 register consistency between operands 2 and 3. */
4940 if (!operand_type_match (overlap2
, i
.types
[2])
4942 && !operand_type_register_match (overlap1
,
4952 /* Found either forward/reverse 2, 3 or 4 operand match here:
4953 slip through to break. */
4955 if (!found_cpu_match
)
4957 found_reverse_match
= 0;
4961 /* Check if vector and VEX operands are valid. */
4962 if (check_VecOperands (t
) || VEX_check_operands (t
))
4964 specific_error
= i
.error
;
4968 /* We've found a match; break out of loop. */
4972 if (t
== current_templates
->end
)
4974 /* We found no match. */
4975 const char *err_msg
;
4976 switch (specific_error
? specific_error
: i
.error
)
4980 case operand_size_mismatch
:
4981 err_msg
= _("operand size mismatch");
4983 case operand_type_mismatch
:
4984 err_msg
= _("operand type mismatch");
4986 case register_type_mismatch
:
4987 err_msg
= _("register type mismatch");
4989 case number_of_operands_mismatch
:
4990 err_msg
= _("number of operands mismatch");
4992 case invalid_instruction_suffix
:
4993 err_msg
= _("invalid instruction suffix");
4996 err_msg
= _("constant doesn't fit in 4 bits");
4999 err_msg
= _("only supported with old gcc");
5001 case unsupported_with_intel_mnemonic
:
5002 err_msg
= _("unsupported with Intel mnemonic");
5004 case unsupported_syntax
:
5005 err_msg
= _("unsupported syntax");
5008 as_bad (_("unsupported instruction `%s'"),
5009 current_templates
->start
->name
);
5011 case invalid_vsib_address
:
5012 err_msg
= _("invalid VSIB address");
5014 case invalid_vector_register_set
:
5015 err_msg
= _("mask, index, and destination registers must be distinct");
5017 case unsupported_vector_index_register
:
5018 err_msg
= _("unsupported vector index register");
5020 case unsupported_broadcast
:
5021 err_msg
= _("unsupported broadcast");
5023 case broadcast_not_on_src_operand
:
5024 err_msg
= _("broadcast not on source memory operand");
5026 case broadcast_needed
:
5027 err_msg
= _("broadcast is needed for operand of such type");
5029 case unsupported_masking
:
5030 err_msg
= _("unsupported masking");
5032 case mask_not_on_destination
:
5033 err_msg
= _("mask not on destination operand");
5035 case no_default_mask
:
5036 err_msg
= _("default mask isn't allowed");
5038 case unsupported_rc_sae
:
5039 err_msg
= _("unsupported static rounding/sae");
5041 case rc_sae_operand_not_last_imm
:
5043 err_msg
= _("RC/SAE operand must precede immediate operands");
5045 err_msg
= _("RC/SAE operand must follow immediate operands");
5047 case invalid_register_operand
:
5048 err_msg
= _("invalid register operand");
5051 as_bad (_("%s for `%s'"), err_msg
,
5052 current_templates
->start
->name
);
5056 if (!quiet_warnings
)
5059 && (i
.types
[0].bitfield
.jumpabsolute
5060 != operand_types
[0].bitfield
.jumpabsolute
))
5062 as_warn (_("indirect %s without `*'"), t
->name
);
5065 if (t
->opcode_modifier
.isprefix
5066 && t
->opcode_modifier
.ignoresize
)
5068 /* Warn them that a data or address size prefix doesn't
5069 affect assembly of the next line of code. */
5070 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5074 /* Copy the template we found. */
5077 if (addr_prefix_disp
!= -1)
5078 i
.tm
.operand_types
[addr_prefix_disp
]
5079 = operand_types
[addr_prefix_disp
];
5081 if (found_reverse_match
)
5083 /* If we found a reverse match we must alter the opcode
5084 direction bit. found_reverse_match holds bits to change
5085 (different for int & float insns). */
5087 i
.tm
.base_opcode
^= found_reverse_match
;
5089 i
.tm
.operand_types
[0] = operand_types
[1];
5090 i
.tm
.operand_types
[1] = operand_types
[0];
5099 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5100 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5102 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5104 as_bad (_("`%s' operand %d must use `%ses' segment"),
5110 /* There's only ever one segment override allowed per instruction.
5111 This instruction possibly has a legal segment override on the
5112 second operand, so copy the segment to where non-string
5113 instructions store it, allowing common code. */
5114 i
.seg
[0] = i
.seg
[1];
5116 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5118 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5120 as_bad (_("`%s' operand %d must use `%ses' segment"),
5131 process_suffix (void)
5133 /* If matched instruction specifies an explicit instruction mnemonic
5135 if (i
.tm
.opcode_modifier
.size16
)
5136 i
.suffix
= WORD_MNEM_SUFFIX
;
5137 else if (i
.tm
.opcode_modifier
.size32
)
5138 i
.suffix
= LONG_MNEM_SUFFIX
;
5139 else if (i
.tm
.opcode_modifier
.size64
)
5140 i
.suffix
= QWORD_MNEM_SUFFIX
;
5141 else if (i
.reg_operands
)
5143 /* If there's no instruction mnemonic suffix we try to invent one
5144 based on register operands. */
5147 /* We take i.suffix from the last register operand specified,
5148 Destination register type is more significant than source
5149 register type. crc32 in SSE4.2 prefers source register
5151 if (i
.tm
.base_opcode
== 0xf20f38f1)
5153 if (i
.types
[0].bitfield
.reg16
)
5154 i
.suffix
= WORD_MNEM_SUFFIX
;
5155 else if (i
.types
[0].bitfield
.reg32
)
5156 i
.suffix
= LONG_MNEM_SUFFIX
;
5157 else if (i
.types
[0].bitfield
.reg64
)
5158 i
.suffix
= QWORD_MNEM_SUFFIX
;
5160 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5162 if (i
.types
[0].bitfield
.reg8
)
5163 i
.suffix
= BYTE_MNEM_SUFFIX
;
5170 if (i
.tm
.base_opcode
== 0xf20f38f1
5171 || i
.tm
.base_opcode
== 0xf20f38f0)
5173 /* We have to know the operand size for crc32. */
5174 as_bad (_("ambiguous memory operand size for `%s`"),
5179 for (op
= i
.operands
; --op
>= 0;)
5180 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5182 if (i
.types
[op
].bitfield
.reg8
)
5184 i
.suffix
= BYTE_MNEM_SUFFIX
;
5187 else if (i
.types
[op
].bitfield
.reg16
)
5189 i
.suffix
= WORD_MNEM_SUFFIX
;
5192 else if (i
.types
[op
].bitfield
.reg32
)
5194 i
.suffix
= LONG_MNEM_SUFFIX
;
5197 else if (i
.types
[op
].bitfield
.reg64
)
5199 i
.suffix
= QWORD_MNEM_SUFFIX
;
5205 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5208 && i
.tm
.opcode_modifier
.ignoresize
5209 && i
.tm
.opcode_modifier
.no_bsuf
)
5211 else if (!check_byte_reg ())
5214 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5217 && i
.tm
.opcode_modifier
.ignoresize
5218 && i
.tm
.opcode_modifier
.no_lsuf
)
5220 else if (!check_long_reg ())
5223 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5226 && i
.tm
.opcode_modifier
.ignoresize
5227 && i
.tm
.opcode_modifier
.no_qsuf
)
5229 else if (!check_qword_reg ())
5232 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5235 && i
.tm
.opcode_modifier
.ignoresize
5236 && i
.tm
.opcode_modifier
.no_wsuf
)
5238 else if (!check_word_reg ())
5241 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5242 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5243 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5245 /* Skip if the instruction has x/y/z suffix. match_template
5246 should check if it is a valid suffix. */
5248 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5249 /* Do nothing if the instruction is going to ignore the prefix. */
5254 else if (i
.tm
.opcode_modifier
.defaultsize
5256 /* exclude fldenv/frstor/fsave/fstenv */
5257 && i
.tm
.opcode_modifier
.no_ssuf
)
5259 i
.suffix
= stackop_size
;
5261 else if (intel_syntax
5263 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5264 || i
.tm
.opcode_modifier
.jumpbyte
5265 || i
.tm
.opcode_modifier
.jumpintersegment
5266 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5267 && i
.tm
.extension_opcode
<= 3)))
5272 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5274 i
.suffix
= QWORD_MNEM_SUFFIX
;
5278 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5279 i
.suffix
= LONG_MNEM_SUFFIX
;
5282 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5283 i
.suffix
= WORD_MNEM_SUFFIX
;
5292 if (i
.tm
.opcode_modifier
.w
)
5294 as_bad (_("no instruction mnemonic suffix given and "
5295 "no register operands; can't size instruction"));
5301 unsigned int suffixes
;
5303 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5304 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5306 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5308 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5310 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5312 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5315 /* There are more than suffix matches. */
5316 if (i
.tm
.opcode_modifier
.w
5317 || ((suffixes
& (suffixes
- 1))
5318 && !i
.tm
.opcode_modifier
.defaultsize
5319 && !i
.tm
.opcode_modifier
.ignoresize
))
5321 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5327 /* Change the opcode based on the operand size given by i.suffix;
5328 We don't need to change things for byte insns. */
5331 && i
.suffix
!= BYTE_MNEM_SUFFIX
5332 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5333 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5334 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5336 /* It's not a byte, select word/dword operation. */
5337 if (i
.tm
.opcode_modifier
.w
)
5339 if (i
.tm
.opcode_modifier
.shortform
)
5340 i
.tm
.base_opcode
|= 8;
5342 i
.tm
.base_opcode
|= 1;
5345 /* Now select between word & dword operations via the operand
5346 size prefix, except for instructions that will ignore this
5348 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5350 /* The address size override prefix changes the size of the
5352 if ((flag_code
== CODE_32BIT
5353 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5354 || (flag_code
!= CODE_32BIT
5355 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5356 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5359 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5360 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5361 && !i
.tm
.opcode_modifier
.ignoresize
5362 && !i
.tm
.opcode_modifier
.floatmf
5363 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5364 || (flag_code
== CODE_64BIT
5365 && i
.tm
.opcode_modifier
.jumpbyte
)))
5367 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5369 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5370 prefix
= ADDR_PREFIX_OPCODE
;
5372 if (!add_prefix (prefix
))
5376 /* Set mode64 for an operand. */
5377 if (i
.suffix
== QWORD_MNEM_SUFFIX
5378 && flag_code
== CODE_64BIT
5379 && !i
.tm
.opcode_modifier
.norex64
)
5381 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5382 need rex64. cmpxchg8b is also a special case. */
5383 if (! (i
.operands
== 2
5384 && i
.tm
.base_opcode
== 0x90
5385 && i
.tm
.extension_opcode
== None
5386 && operand_type_equal (&i
.types
[0], &acc64
)
5387 && operand_type_equal (&i
.types
[1], &acc64
))
5388 && ! (i
.operands
== 1
5389 && i
.tm
.base_opcode
== 0xfc7
5390 && i
.tm
.extension_opcode
== 1
5391 && !operand_type_check (i
.types
[0], reg
)
5392 && operand_type_check (i
.types
[0], anymem
)))
5396 /* Size floating point instruction. */
5397 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5398 if (i
.tm
.opcode_modifier
.floatmf
)
5399 i
.tm
.base_opcode
^= 4;
5406 check_byte_reg (void)
5410 for (op
= i
.operands
; --op
>= 0;)
5412 /* If this is an eight bit register, it's OK. If it's the 16 or
5413 32 bit version of an eight bit register, we will just use the
5414 low portion, and that's OK too. */
5415 if (i
.types
[op
].bitfield
.reg8
)
5418 /* I/O port address operands are OK too. */
5419 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5422 /* crc32 doesn't generate this warning. */
5423 if (i
.tm
.base_opcode
== 0xf20f38f0)
5426 if ((i
.types
[op
].bitfield
.reg16
5427 || i
.types
[op
].bitfield
.reg32
5428 || i
.types
[op
].bitfield
.reg64
)
5429 && i
.op
[op
].regs
->reg_num
< 4
5430 /* Prohibit these changes in 64bit mode, since the lowering
5431 would be more complicated. */
5432 && flag_code
!= CODE_64BIT
)
5434 #if REGISTER_WARNINGS
5435 if (!quiet_warnings
)
5436 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5438 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5439 ? REGNAM_AL
- REGNAM_AX
5440 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5442 i
.op
[op
].regs
->reg_name
,
5447 /* Any other register is bad. */
5448 if (i
.types
[op
].bitfield
.reg16
5449 || i
.types
[op
].bitfield
.reg32
5450 || i
.types
[op
].bitfield
.reg64
5451 || i
.types
[op
].bitfield
.regmmx
5452 || i
.types
[op
].bitfield
.regxmm
5453 || i
.types
[op
].bitfield
.regymm
5454 || i
.types
[op
].bitfield
.regzmm
5455 || i
.types
[op
].bitfield
.sreg2
5456 || i
.types
[op
].bitfield
.sreg3
5457 || i
.types
[op
].bitfield
.control
5458 || i
.types
[op
].bitfield
.debug
5459 || i
.types
[op
].bitfield
.test
5460 || i
.types
[op
].bitfield
.floatreg
5461 || i
.types
[op
].bitfield
.floatacc
)
5463 as_bad (_("`%s%s' not allowed with `%s%c'"),
5465 i
.op
[op
].regs
->reg_name
,
5475 check_long_reg (void)
5479 for (op
= i
.operands
; --op
>= 0;)
5480 /* Reject eight bit registers, except where the template requires
5481 them. (eg. movzb) */
5482 if (i
.types
[op
].bitfield
.reg8
5483 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5484 || i
.tm
.operand_types
[op
].bitfield
.reg32
5485 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5487 as_bad (_("`%s%s' not allowed with `%s%c'"),
5489 i
.op
[op
].regs
->reg_name
,
5494 /* Warn if the e prefix on a general reg is missing. */
5495 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5496 && i
.types
[op
].bitfield
.reg16
5497 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5498 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5500 /* Prohibit these changes in the 64bit mode, since the
5501 lowering is more complicated. */
5502 if (flag_code
== CODE_64BIT
)
5504 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5505 register_prefix
, i
.op
[op
].regs
->reg_name
,
5509 #if REGISTER_WARNINGS
5510 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5512 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5513 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5516 /* Warn if the r prefix on a general reg is present. */
5517 else if (i
.types
[op
].bitfield
.reg64
5518 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5519 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5522 && i
.tm
.opcode_modifier
.toqword
5523 && !i
.types
[0].bitfield
.regxmm
)
5525 /* Convert to QWORD. We want REX byte. */
5526 i
.suffix
= QWORD_MNEM_SUFFIX
;
5530 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5531 register_prefix
, i
.op
[op
].regs
->reg_name
,
5540 check_qword_reg (void)
5544 for (op
= i
.operands
; --op
>= 0; )
5545 /* Reject eight bit registers, except where the template requires
5546 them. (eg. movzb) */
5547 if (i
.types
[op
].bitfield
.reg8
5548 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5549 || i
.tm
.operand_types
[op
].bitfield
.reg32
5550 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5552 as_bad (_("`%s%s' not allowed with `%s%c'"),
5554 i
.op
[op
].regs
->reg_name
,
5559 /* Warn if the r prefix on a general reg is missing. */
5560 else if ((i
.types
[op
].bitfield
.reg16
5561 || i
.types
[op
].bitfield
.reg32
)
5562 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5563 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5565 /* Prohibit these changes in the 64bit mode, since the
5566 lowering is more complicated. */
5568 && i
.tm
.opcode_modifier
.todword
5569 && !i
.types
[0].bitfield
.regxmm
)
5571 /* Convert to DWORD. We don't want REX byte. */
5572 i
.suffix
= LONG_MNEM_SUFFIX
;
5576 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5577 register_prefix
, i
.op
[op
].regs
->reg_name
,
5586 check_word_reg (void)
5589 for (op
= i
.operands
; --op
>= 0;)
5590 /* Reject eight bit registers, except where the template requires
5591 them. (eg. movzb) */
5592 if (i
.types
[op
].bitfield
.reg8
5593 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5594 || i
.tm
.operand_types
[op
].bitfield
.reg32
5595 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5597 as_bad (_("`%s%s' not allowed with `%s%c'"),
5599 i
.op
[op
].regs
->reg_name
,
5604 /* Warn if the e or r prefix on a general reg is present. */
5605 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5606 && (i
.types
[op
].bitfield
.reg32
5607 || i
.types
[op
].bitfield
.reg64
)
5608 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5609 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5611 /* Prohibit these changes in the 64bit mode, since the
5612 lowering is more complicated. */
5613 if (flag_code
== CODE_64BIT
)
5615 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5616 register_prefix
, i
.op
[op
].regs
->reg_name
,
5620 #if REGISTER_WARNINGS
5621 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5623 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5624 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5631 update_imm (unsigned int j
)
5633 i386_operand_type overlap
= i
.types
[j
];
5634 if ((overlap
.bitfield
.imm8
5635 || overlap
.bitfield
.imm8s
5636 || overlap
.bitfield
.imm16
5637 || overlap
.bitfield
.imm32
5638 || overlap
.bitfield
.imm32s
5639 || overlap
.bitfield
.imm64
)
5640 && !operand_type_equal (&overlap
, &imm8
)
5641 && !operand_type_equal (&overlap
, &imm8s
)
5642 && !operand_type_equal (&overlap
, &imm16
)
5643 && !operand_type_equal (&overlap
, &imm32
)
5644 && !operand_type_equal (&overlap
, &imm32s
)
5645 && !operand_type_equal (&overlap
, &imm64
))
5649 i386_operand_type temp
;
5651 operand_type_set (&temp
, 0);
5652 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5654 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5655 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5657 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5658 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5659 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5661 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5662 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5665 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5668 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5669 || operand_type_equal (&overlap
, &imm16_32
)
5670 || operand_type_equal (&overlap
, &imm16_32s
))
5672 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5677 if (!operand_type_equal (&overlap
, &imm8
)
5678 && !operand_type_equal (&overlap
, &imm8s
)
5679 && !operand_type_equal (&overlap
, &imm16
)
5680 && !operand_type_equal (&overlap
, &imm32
)
5681 && !operand_type_equal (&overlap
, &imm32s
)
5682 && !operand_type_equal (&overlap
, &imm64
))
5684 as_bad (_("no instruction mnemonic suffix given; "
5685 "can't determine immediate size"));
5689 i
.types
[j
] = overlap
;
5699 /* Update the first 2 immediate operands. */
5700 n
= i
.operands
> 2 ? 2 : i
.operands
;
5703 for (j
= 0; j
< n
; j
++)
5704 if (update_imm (j
) == 0)
5707 /* The 3rd operand can't be immediate operand. */
5708 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5715 bad_implicit_operand (int xmm
)
5717 const char *ireg
= xmm
? "xmm0" : "ymm0";
5720 as_bad (_("the last operand of `%s' must be `%s%s'"),
5721 i
.tm
.name
, register_prefix
, ireg
);
5723 as_bad (_("the first operand of `%s' must be `%s%s'"),
5724 i
.tm
.name
, register_prefix
, ireg
);
5729 process_operands (void)
5731 /* Default segment register this instruction will use for memory
5732 accesses. 0 means unknown. This is only for optimizing out
5733 unnecessary segment overrides. */
5734 const seg_entry
*default_seg
= 0;
5736 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5738 unsigned int dupl
= i
.operands
;
5739 unsigned int dest
= dupl
- 1;
5742 /* The destination must be an xmm register. */
5743 gas_assert (i
.reg_operands
5744 && MAX_OPERANDS
> dupl
5745 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5747 if (i
.tm
.opcode_modifier
.firstxmm0
)
5749 /* The first operand is implicit and must be xmm0. */
5750 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5751 if (register_number (i
.op
[0].regs
) != 0)
5752 return bad_implicit_operand (1);
5754 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5756 /* Keep xmm0 for instructions with VEX prefix and 3
5762 /* We remove the first xmm0 and keep the number of
5763 operands unchanged, which in fact duplicates the
5765 for (j
= 1; j
< i
.operands
; j
++)
5767 i
.op
[j
- 1] = i
.op
[j
];
5768 i
.types
[j
- 1] = i
.types
[j
];
5769 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5773 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5775 gas_assert ((MAX_OPERANDS
- 1) > dupl
5776 && (i
.tm
.opcode_modifier
.vexsources
5779 /* Add the implicit xmm0 for instructions with VEX prefix
5781 for (j
= i
.operands
; j
> 0; j
--)
5783 i
.op
[j
] = i
.op
[j
- 1];
5784 i
.types
[j
] = i
.types
[j
- 1];
5785 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5788 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5789 i
.types
[0] = regxmm
;
5790 i
.tm
.operand_types
[0] = regxmm
;
5793 i
.reg_operands
+= 2;
5798 i
.op
[dupl
] = i
.op
[dest
];
5799 i
.types
[dupl
] = i
.types
[dest
];
5800 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5809 i
.op
[dupl
] = i
.op
[dest
];
5810 i
.types
[dupl
] = i
.types
[dest
];
5811 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5814 if (i
.tm
.opcode_modifier
.immext
)
5817 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5821 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5822 gas_assert (i
.reg_operands
5823 && (operand_type_equal (&i
.types
[0], ®xmm
)
5824 || operand_type_equal (&i
.types
[0], ®ymm
)
5825 || operand_type_equal (&i
.types
[0], ®zmm
)));
5826 if (register_number (i
.op
[0].regs
) != 0)
5827 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5829 for (j
= 1; j
< i
.operands
; j
++)
5831 i
.op
[j
- 1] = i
.op
[j
];
5832 i
.types
[j
- 1] = i
.types
[j
];
5834 /* We need to adjust fields in i.tm since they are used by
5835 build_modrm_byte. */
5836 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5843 else if (i
.tm
.opcode_modifier
.regkludge
)
5845 /* The imul $imm, %reg instruction is converted into
5846 imul $imm, %reg, %reg, and the clr %reg instruction
5847 is converted into xor %reg, %reg. */
5849 unsigned int first_reg_op
;
5851 if (operand_type_check (i
.types
[0], reg
))
5855 /* Pretend we saw the extra register operand. */
5856 gas_assert (i
.reg_operands
== 1
5857 && i
.op
[first_reg_op
+ 1].regs
== 0);
5858 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5859 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5864 if (i
.tm
.opcode_modifier
.shortform
)
5866 if (i
.types
[0].bitfield
.sreg2
5867 || i
.types
[0].bitfield
.sreg3
)
5869 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5870 && i
.op
[0].regs
->reg_num
== 1)
5872 as_bad (_("you can't `pop %scs'"), register_prefix
);
5875 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5876 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5881 /* The register or float register operand is in operand
5885 if (i
.types
[0].bitfield
.floatreg
5886 || operand_type_check (i
.types
[0], reg
))
5890 /* Register goes in low 3 bits of opcode. */
5891 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5892 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5894 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5896 /* Warn about some common errors, but press on regardless.
5897 The first case can be generated by gcc (<= 2.8.1). */
5898 if (i
.operands
== 2)
5900 /* Reversed arguments on faddp, fsubp, etc. */
5901 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5902 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5903 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5907 /* Extraneous `l' suffix on fp insn. */
5908 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5909 register_prefix
, i
.op
[0].regs
->reg_name
);
5914 else if (i
.tm
.opcode_modifier
.modrm
)
5916 /* The opcode is completed (modulo i.tm.extension_opcode which
5917 must be put into the modrm byte). Now, we make the modrm and
5918 index base bytes based on all the info we've collected. */
5920 default_seg
= build_modrm_byte ();
5922 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5926 else if (i
.tm
.opcode_modifier
.isstring
)
5928 /* For the string instructions that allow a segment override
5929 on one of their operands, the default segment is ds. */
5933 if (i
.tm
.base_opcode
== 0x8d /* lea */
5936 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5938 /* If a segment was explicitly specified, and the specified segment
5939 is not the default, use an opcode prefix to select it. If we
5940 never figured out what the default segment is, then default_seg
5941 will be zero at this point, and the specified segment prefix will
5943 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5945 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5951 static const seg_entry
*
5952 build_modrm_byte (void)
5954 const seg_entry
*default_seg
= 0;
5955 unsigned int source
, dest
;
5958 /* The first operand of instructions with VEX prefix and 3 sources
5959 must be VEX_Imm4. */
5960 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5963 unsigned int nds
, reg_slot
;
5966 if (i
.tm
.opcode_modifier
.veximmext
5967 && i
.tm
.opcode_modifier
.immext
)
5969 dest
= i
.operands
- 2;
5970 gas_assert (dest
== 3);
5973 dest
= i
.operands
- 1;
5976 /* There are 2 kinds of instructions:
5977 1. 5 operands: 4 register operands or 3 register operands
5978 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5979 VexW0 or VexW1. The destination must be either XMM, YMM or
5981 2. 4 operands: 4 register operands or 3 register operands
5982 plus 1 memory operand, VexXDS, and VexImmExt */
5983 gas_assert ((i
.reg_operands
== 4
5984 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5985 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5986 && (i
.tm
.opcode_modifier
.veximmext
5987 || (i
.imm_operands
== 1
5988 && i
.types
[0].bitfield
.vec_imm4
5989 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5990 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5991 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5992 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5993 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5995 if (i
.imm_operands
== 0)
5997 /* When there is no immediate operand, generate an 8bit
5998 immediate operand to encode the first operand. */
5999 exp
= &im_expressions
[i
.imm_operands
++];
6000 i
.op
[i
.operands
].imms
= exp
;
6001 i
.types
[i
.operands
] = imm8
;
6003 /* If VexW1 is set, the first operand is the source and
6004 the second operand is encoded in the immediate operand. */
6005 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6016 /* FMA swaps REG and NDS. */
6017 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6025 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6027 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6029 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6031 exp
->X_op
= O_constant
;
6032 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6033 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6037 unsigned int imm_slot
;
6039 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6041 /* If VexW0 is set, the third operand is the source and
6042 the second operand is encoded in the immediate
6049 /* VexW1 is set, the second operand is the source and
6050 the third operand is encoded in the immediate
6056 if (i
.tm
.opcode_modifier
.immext
)
6058 /* When ImmExt is set, the immdiate byte is the last
6060 imm_slot
= i
.operands
- 1;
6068 /* Turn on Imm8 so that output_imm will generate it. */
6069 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6072 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6074 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6076 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6078 i
.op
[imm_slot
].imms
->X_add_number
6079 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6080 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6083 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6084 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6086 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6088 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6093 /* i.reg_operands MUST be the number of real register operands;
6094 implicit registers do not count. If there are 3 register
6095 operands, it must be a instruction with VexNDS. For a
6096 instruction with VexNDD, the destination register is encoded
6097 in VEX prefix. If there are 4 register operands, it must be
6098 a instruction with VEX prefix and 3 sources. */
6099 if (i
.mem_operands
== 0
6100 && ((i
.reg_operands
== 2
6101 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6102 || (i
.reg_operands
== 3
6103 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6104 || (i
.reg_operands
== 4 && vex_3_sources
)))
6112 /* When there are 3 operands, one of them may be immediate,
6113 which may be the first or the last operand. Otherwise,
6114 the first operand must be shift count register (cl) or it
6115 is an instruction with VexNDS. */
6116 gas_assert (i
.imm_operands
== 1
6117 || (i
.imm_operands
== 0
6118 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6119 || i
.types
[0].bitfield
.shiftcount
)));
6120 if (operand_type_check (i
.types
[0], imm
)
6121 || i
.types
[0].bitfield
.shiftcount
)
6127 /* When there are 4 operands, the first two must be 8bit
6128 immediate operands. The source operand will be the 3rd
6131 For instructions with VexNDS, if the first operand
6132 an imm8, the source operand is the 2nd one. If the last
6133 operand is imm8, the source operand is the first one. */
6134 gas_assert ((i
.imm_operands
== 2
6135 && i
.types
[0].bitfield
.imm8
6136 && i
.types
[1].bitfield
.imm8
)
6137 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6138 && i
.imm_operands
== 1
6139 && (i
.types
[0].bitfield
.imm8
6140 || i
.types
[i
.operands
- 1].bitfield
.imm8
6142 if (i
.imm_operands
== 2)
6146 if (i
.types
[0].bitfield
.imm8
)
6153 if (i
.tm
.opcode_modifier
.evex
)
6155 /* For EVEX instructions, when there are 5 operands, the
6156 first one must be immediate operand. If the second one
6157 is immediate operand, the source operand is the 3th
6158 one. If the last one is immediate operand, the source
6159 operand is the 2nd one. */
6160 gas_assert (i
.imm_operands
== 2
6161 && i
.tm
.opcode_modifier
.sae
6162 && operand_type_check (i
.types
[0], imm
));
6163 if (operand_type_check (i
.types
[1], imm
))
6165 else if (operand_type_check (i
.types
[4], imm
))
6179 /* RC/SAE operand could be between DEST and SRC. That happens
6180 when one operand is GPR and the other one is XMM/YMM/ZMM
6182 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6185 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6187 /* For instructions with VexNDS, the register-only source
6188 operand must be 32/64bit integer, XMM, YMM or ZMM
6189 register. It is encoded in VEX prefix. We need to
6190 clear RegMem bit before calling operand_type_equal. */
6192 i386_operand_type op
;
6195 /* Check register-only source operand when two source
6196 operands are swapped. */
6197 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6198 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6206 op
= i
.tm
.operand_types
[vvvv
];
6207 op
.bitfield
.regmem
= 0;
6208 if ((dest
+ 1) >= i
.operands
6209 || (!op
.bitfield
.reg32
6210 && op
.bitfield
.reg64
6211 && !operand_type_equal (&op
, ®xmm
)
6212 && !operand_type_equal (&op
, ®ymm
)
6213 && !operand_type_equal (&op
, ®zmm
)
6214 && !operand_type_equal (&op
, ®mask
)))
6216 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6222 /* One of the register operands will be encoded in the i.tm.reg
6223 field, the other in the combined i.tm.mode and i.tm.regmem
6224 fields. If no form of this instruction supports a memory
6225 destination operand, then we assume the source operand may
6226 sometimes be a memory operand and so we need to store the
6227 destination in the i.rm.reg field. */
6228 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6229 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6231 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6232 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6233 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6235 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6237 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6239 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6244 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6245 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6246 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6248 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6250 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6252 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6255 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6257 if (!i
.types
[0].bitfield
.control
6258 && !i
.types
[1].bitfield
.control
)
6260 i
.rex
&= ~(REX_R
| REX_B
);
6261 add_prefix (LOCK_PREFIX_OPCODE
);
6265 { /* If it's not 2 reg operands... */
6270 unsigned int fake_zero_displacement
= 0;
6273 for (op
= 0; op
< i
.operands
; op
++)
6274 if (operand_type_check (i
.types
[op
], anymem
))
6276 gas_assert (op
< i
.operands
);
6278 if (i
.tm
.opcode_modifier
.vecsib
)
6280 if (i
.index_reg
->reg_num
== RegEiz
6281 || i
.index_reg
->reg_num
== RegRiz
)
6284 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6287 i
.sib
.base
= NO_BASE_REGISTER
;
6288 i
.sib
.scale
= i
.log2_scale_factor
;
6289 /* No Vec_Disp8 if there is no base. */
6290 i
.types
[op
].bitfield
.vec_disp8
= 0;
6291 i
.types
[op
].bitfield
.disp8
= 0;
6292 i
.types
[op
].bitfield
.disp16
= 0;
6293 i
.types
[op
].bitfield
.disp64
= 0;
6294 if (flag_code
!= CODE_64BIT
)
6296 /* Must be 32 bit */
6297 i
.types
[op
].bitfield
.disp32
= 1;
6298 i
.types
[op
].bitfield
.disp32s
= 0;
6302 i
.types
[op
].bitfield
.disp32
= 0;
6303 i
.types
[op
].bitfield
.disp32s
= 1;
6306 i
.sib
.index
= i
.index_reg
->reg_num
;
6307 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6309 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6315 if (i
.base_reg
== 0)
6318 if (!i
.disp_operands
)
6320 fake_zero_displacement
= 1;
6321 /* Instructions with VSIB byte need 32bit displacement
6322 if there is no base register. */
6323 if (i
.tm
.opcode_modifier
.vecsib
)
6324 i
.types
[op
].bitfield
.disp32
= 1;
6326 if (i
.index_reg
== 0)
6328 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6329 /* Operand is just <disp> */
6330 if (flag_code
== CODE_64BIT
)
6332 /* 64bit mode overwrites the 32bit absolute
6333 addressing by RIP relative addressing and
6334 absolute addressing is encoded by one of the
6335 redundant SIB forms. */
6336 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6337 i
.sib
.base
= NO_BASE_REGISTER
;
6338 i
.sib
.index
= NO_INDEX_REGISTER
;
6339 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6340 ? disp32s
: disp32
);
6342 else if ((flag_code
== CODE_16BIT
)
6343 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6345 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6346 i
.types
[op
] = disp16
;
6350 i
.rm
.regmem
= NO_BASE_REGISTER
;
6351 i
.types
[op
] = disp32
;
6354 else if (!i
.tm
.opcode_modifier
.vecsib
)
6356 /* !i.base_reg && i.index_reg */
6357 if (i
.index_reg
->reg_num
== RegEiz
6358 || i
.index_reg
->reg_num
== RegRiz
)
6359 i
.sib
.index
= NO_INDEX_REGISTER
;
6361 i
.sib
.index
= i
.index_reg
->reg_num
;
6362 i
.sib
.base
= NO_BASE_REGISTER
;
6363 i
.sib
.scale
= i
.log2_scale_factor
;
6364 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6365 /* No Vec_Disp8 if there is no base. */
6366 i
.types
[op
].bitfield
.vec_disp8
= 0;
6367 i
.types
[op
].bitfield
.disp8
= 0;
6368 i
.types
[op
].bitfield
.disp16
= 0;
6369 i
.types
[op
].bitfield
.disp64
= 0;
6370 if (flag_code
!= CODE_64BIT
)
6372 /* Must be 32 bit */
6373 i
.types
[op
].bitfield
.disp32
= 1;
6374 i
.types
[op
].bitfield
.disp32s
= 0;
6378 i
.types
[op
].bitfield
.disp32
= 0;
6379 i
.types
[op
].bitfield
.disp32s
= 1;
6381 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6385 /* RIP addressing for 64bit mode. */
6386 else if (i
.base_reg
->reg_num
== RegRip
||
6387 i
.base_reg
->reg_num
== RegEip
)
6389 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6390 i
.rm
.regmem
= NO_BASE_REGISTER
;
6391 i
.types
[op
].bitfield
.disp8
= 0;
6392 i
.types
[op
].bitfield
.disp16
= 0;
6393 i
.types
[op
].bitfield
.disp32
= 0;
6394 i
.types
[op
].bitfield
.disp32s
= 1;
6395 i
.types
[op
].bitfield
.disp64
= 0;
6396 i
.types
[op
].bitfield
.vec_disp8
= 0;
6397 i
.flags
[op
] |= Operand_PCrel
;
6398 if (! i
.disp_operands
)
6399 fake_zero_displacement
= 1;
6401 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6403 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6404 switch (i
.base_reg
->reg_num
)
6407 if (i
.index_reg
== 0)
6409 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6410 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6414 if (i
.index_reg
== 0)
6417 if (operand_type_check (i
.types
[op
], disp
) == 0)
6419 /* fake (%bp) into 0(%bp) */
6420 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6421 i
.types
[op
].bitfield
.vec_disp8
= 1;
6423 i
.types
[op
].bitfield
.disp8
= 1;
6424 fake_zero_displacement
= 1;
6427 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6428 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6430 default: /* (%si) -> 4 or (%di) -> 5 */
6431 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6433 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6435 else /* i.base_reg and 32/64 bit mode */
6437 if (flag_code
== CODE_64BIT
6438 && operand_type_check (i
.types
[op
], disp
))
6440 i386_operand_type temp
;
6441 operand_type_set (&temp
, 0);
6442 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6443 temp
.bitfield
.vec_disp8
6444 = i
.types
[op
].bitfield
.vec_disp8
;
6446 if (i
.prefix
[ADDR_PREFIX
] == 0)
6447 i
.types
[op
].bitfield
.disp32s
= 1;
6449 i
.types
[op
].bitfield
.disp32
= 1;
6452 if (!i
.tm
.opcode_modifier
.vecsib
)
6453 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6454 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6456 i
.sib
.base
= i
.base_reg
->reg_num
;
6457 /* x86-64 ignores REX prefix bit here to avoid decoder
6459 if (!(i
.base_reg
->reg_flags
& RegRex
)
6460 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6461 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6463 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6465 fake_zero_displacement
= 1;
6466 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6467 i
.types
[op
].bitfield
.vec_disp8
= 1;
6469 i
.types
[op
].bitfield
.disp8
= 1;
6471 i
.sib
.scale
= i
.log2_scale_factor
;
6472 if (i
.index_reg
== 0)
6474 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6475 /* <disp>(%esp) becomes two byte modrm with no index
6476 register. We've already stored the code for esp
6477 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6478 Any base register besides %esp will not use the
6479 extra modrm byte. */
6480 i
.sib
.index
= NO_INDEX_REGISTER
;
6482 else if (!i
.tm
.opcode_modifier
.vecsib
)
6484 if (i
.index_reg
->reg_num
== RegEiz
6485 || i
.index_reg
->reg_num
== RegRiz
)
6486 i
.sib
.index
= NO_INDEX_REGISTER
;
6488 i
.sib
.index
= i
.index_reg
->reg_num
;
6489 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6490 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6495 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6496 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6500 if (!fake_zero_displacement
6504 fake_zero_displacement
= 1;
6505 if (i
.disp_encoding
== disp_encoding_8bit
)
6506 i
.types
[op
].bitfield
.disp8
= 1;
6508 i
.types
[op
].bitfield
.disp32
= 1;
6510 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6514 if (fake_zero_displacement
)
6516 /* Fakes a zero displacement assuming that i.types[op]
6517 holds the correct displacement size. */
6520 gas_assert (i
.op
[op
].disps
== 0);
6521 exp
= &disp_expressions
[i
.disp_operands
++];
6522 i
.op
[op
].disps
= exp
;
6523 exp
->X_op
= O_constant
;
6524 exp
->X_add_number
= 0;
6525 exp
->X_add_symbol
= (symbolS
*) 0;
6526 exp
->X_op_symbol
= (symbolS
*) 0;
6534 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6536 if (operand_type_check (i
.types
[0], imm
))
6537 i
.vex
.register_specifier
= NULL
;
6540 /* VEX.vvvv encodes one of the sources when the first
6541 operand is not an immediate. */
6542 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6543 i
.vex
.register_specifier
= i
.op
[0].regs
;
6545 i
.vex
.register_specifier
= i
.op
[1].regs
;
6548 /* Destination is a XMM register encoded in the ModRM.reg
6550 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6551 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6554 /* ModRM.rm and VEX.B encodes the other source. */
6555 if (!i
.mem_operands
)
6559 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6560 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6562 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6564 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6568 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6570 i
.vex
.register_specifier
= i
.op
[2].regs
;
6571 if (!i
.mem_operands
)
6574 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6575 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6579 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6580 (if any) based on i.tm.extension_opcode. Again, we must be
6581 careful to make sure that segment/control/debug/test/MMX
6582 registers are coded into the i.rm.reg field. */
6583 else if (i
.reg_operands
)
6586 unsigned int vex_reg
= ~0;
6588 for (op
= 0; op
< i
.operands
; op
++)
6589 if (i
.types
[op
].bitfield
.reg8
6590 || i
.types
[op
].bitfield
.reg16
6591 || i
.types
[op
].bitfield
.reg32
6592 || i
.types
[op
].bitfield
.reg64
6593 || i
.types
[op
].bitfield
.regmmx
6594 || i
.types
[op
].bitfield
.regxmm
6595 || i
.types
[op
].bitfield
.regymm
6596 || i
.types
[op
].bitfield
.regbnd
6597 || i
.types
[op
].bitfield
.regzmm
6598 || i
.types
[op
].bitfield
.regmask
6599 || i
.types
[op
].bitfield
.sreg2
6600 || i
.types
[op
].bitfield
.sreg3
6601 || i
.types
[op
].bitfield
.control
6602 || i
.types
[op
].bitfield
.debug
6603 || i
.types
[op
].bitfield
.test
)
6608 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6610 /* For instructions with VexNDS, the register-only
6611 source operand is encoded in VEX prefix. */
6612 gas_assert (mem
!= (unsigned int) ~0);
6617 gas_assert (op
< i
.operands
);
6621 /* Check register-only source operand when two source
6622 operands are swapped. */
6623 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6624 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6628 gas_assert (mem
== (vex_reg
+ 1)
6629 && op
< i
.operands
);
6634 gas_assert (vex_reg
< i
.operands
);
6638 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6640 /* For instructions with VexNDD, the register destination
6641 is encoded in VEX prefix. */
6642 if (i
.mem_operands
== 0)
6644 /* There is no memory operand. */
6645 gas_assert ((op
+ 2) == i
.operands
);
6650 /* There are only 2 operands. */
6651 gas_assert (op
< 2 && i
.operands
== 2);
6656 gas_assert (op
< i
.operands
);
6658 if (vex_reg
!= (unsigned int) ~0)
6660 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6662 if (type
->bitfield
.reg32
!= 1
6663 && type
->bitfield
.reg64
!= 1
6664 && !operand_type_equal (type
, ®xmm
)
6665 && !operand_type_equal (type
, ®ymm
)
6666 && !operand_type_equal (type
, ®zmm
)
6667 && !operand_type_equal (type
, ®mask
))
6670 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6673 /* Don't set OP operand twice. */
6676 /* If there is an extension opcode to put here, the
6677 register number must be put into the regmem field. */
6678 if (i
.tm
.extension_opcode
!= None
)
6680 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6681 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6683 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6688 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6689 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6691 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6696 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6697 must set it to 3 to indicate this is a register operand
6698 in the regmem field. */
6699 if (!i
.mem_operands
)
6703 /* Fill in i.rm.reg field with extension opcode (if any). */
6704 if (i
.tm
.extension_opcode
!= None
)
6705 i
.rm
.reg
= i
.tm
.extension_opcode
;
6711 output_branch (void)
6717 relax_substateT subtype
;
6721 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6722 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6725 if (i
.prefix
[DATA_PREFIX
] != 0)
6731 /* Pentium4 branch hints. */
6732 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6733 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6738 if (i
.prefix
[REX_PREFIX
] != 0)
6744 /* BND prefixed jump. */
6745 if (i
.prefix
[BND_PREFIX
] != 0)
6747 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6751 if (i
.prefixes
!= 0 && !intel_syntax
)
6752 as_warn (_("skipping prefixes on this instruction"));
6754 /* It's always a symbol; End frag & setup for relax.
6755 Make sure there is enough room in this frag for the largest
6756 instruction we may generate in md_convert_frag. This is 2
6757 bytes for the opcode and room for the prefix and largest
6759 frag_grow (prefix
+ 2 + 4);
6760 /* Prefix and 1 opcode byte go in fr_fix. */
6761 p
= frag_more (prefix
+ 1);
6762 if (i
.prefix
[DATA_PREFIX
] != 0)
6763 *p
++ = DATA_PREFIX_OPCODE
;
6764 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6765 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6766 *p
++ = i
.prefix
[SEG_PREFIX
];
6767 if (i
.prefix
[REX_PREFIX
] != 0)
6768 *p
++ = i
.prefix
[REX_PREFIX
];
6769 *p
= i
.tm
.base_opcode
;
6771 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6772 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6773 else if (cpu_arch_flags
.bitfield
.cpui386
)
6774 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6776 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6779 sym
= i
.op
[0].disps
->X_add_symbol
;
6780 off
= i
.op
[0].disps
->X_add_number
;
6782 if (i
.op
[0].disps
->X_op
!= O_constant
6783 && i
.op
[0].disps
->X_op
!= O_symbol
)
6785 /* Handle complex expressions. */
6786 sym
= make_expr_symbol (i
.op
[0].disps
);
6790 /* 1 possible extra opcode + 4 byte displacement go in var part.
6791 Pass reloc in fr_var. */
6792 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6802 if (i
.tm
.opcode_modifier
.jumpbyte
)
6804 /* This is a loop or jecxz type instruction. */
6806 if (i
.prefix
[ADDR_PREFIX
] != 0)
6808 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6811 /* Pentium4 branch hints. */
6812 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6813 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6815 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6824 if (flag_code
== CODE_16BIT
)
6827 if (i
.prefix
[DATA_PREFIX
] != 0)
6829 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6839 if (i
.prefix
[REX_PREFIX
] != 0)
6841 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6845 /* BND prefixed jump. */
6846 if (i
.prefix
[BND_PREFIX
] != 0)
6848 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6852 if (i
.prefixes
!= 0 && !intel_syntax
)
6853 as_warn (_("skipping prefixes on this instruction"));
6855 p
= frag_more (i
.tm
.opcode_length
+ size
);
6856 switch (i
.tm
.opcode_length
)
6859 *p
++ = i
.tm
.base_opcode
>> 8;
6861 *p
++ = i
.tm
.base_opcode
;
6867 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6868 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6870 /* All jumps handled here are signed, but don't use a signed limit
6871 check for 32 and 16 bit jumps as we want to allow wrap around at
6872 4G and 64k respectively. */
6874 fixP
->fx_signed
= 1;
6878 output_interseg_jump (void)
6886 if (flag_code
== CODE_16BIT
)
6890 if (i
.prefix
[DATA_PREFIX
] != 0)
6896 if (i
.prefix
[REX_PREFIX
] != 0)
6906 if (i
.prefixes
!= 0 && !intel_syntax
)
6907 as_warn (_("skipping prefixes on this instruction"));
6909 /* 1 opcode; 2 segment; offset */
6910 p
= frag_more (prefix
+ 1 + 2 + size
);
6912 if (i
.prefix
[DATA_PREFIX
] != 0)
6913 *p
++ = DATA_PREFIX_OPCODE
;
6915 if (i
.prefix
[REX_PREFIX
] != 0)
6916 *p
++ = i
.prefix
[REX_PREFIX
];
6918 *p
++ = i
.tm
.base_opcode
;
6919 if (i
.op
[1].imms
->X_op
== O_constant
)
6921 offsetT n
= i
.op
[1].imms
->X_add_number
;
6924 && !fits_in_unsigned_word (n
)
6925 && !fits_in_signed_word (n
))
6927 as_bad (_("16-bit jump out of range"));
6930 md_number_to_chars (p
, n
, size
);
6933 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6934 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6935 if (i
.op
[0].imms
->X_op
!= O_constant
)
6936 as_bad (_("can't handle non absolute segment in `%s'"),
6938 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6944 fragS
*insn_start_frag
;
6945 offsetT insn_start_off
;
6947 /* Tie dwarf2 debug info to the address at the start of the insn.
6948 We can't do this after the insn has been output as the current
6949 frag may have been closed off. eg. by frag_var. */
6950 dwarf2_emit_insn (0);
6952 insn_start_frag
= frag_now
;
6953 insn_start_off
= frag_now_fix ();
6956 if (i
.tm
.opcode_modifier
.jump
)
6958 else if (i
.tm
.opcode_modifier
.jumpbyte
6959 || i
.tm
.opcode_modifier
.jumpdword
)
6961 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6962 output_interseg_jump ();
6965 /* Output normal instructions here. */
6969 unsigned int prefix
;
6972 && i
.tm
.base_opcode
== 0xfae
6974 && i
.imm_operands
== 1
6975 && (i
.op
[0].imms
->X_add_number
== 0xe8
6976 || i
.op
[0].imms
->X_add_number
== 0xf0
6977 || i
.op
[0].imms
->X_add_number
== 0xf8))
6979 /* Encode lfence, mfence, and sfence as
6980 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
6981 offsetT val
= 0x240483f0ULL
;
6983 md_number_to_chars (p
, val
, 5);
6987 /* Some processors fail on LOCK prefix. This options makes
6988 assembler ignore LOCK prefix and serves as a workaround. */
6989 if (omit_lock_prefix
)
6991 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
6993 i
.prefix
[LOCK_PREFIX
] = 0;
6996 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6997 don't need the explicit prefix. */
6998 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7000 switch (i
.tm
.opcode_length
)
7003 if (i
.tm
.base_opcode
& 0xff000000)
7005 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7010 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7012 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7013 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7016 if (prefix
!= REPE_PREFIX_OPCODE
7017 || (i
.prefix
[REP_PREFIX
]
7018 != REPE_PREFIX_OPCODE
))
7019 add_prefix (prefix
);
7022 add_prefix (prefix
);
7031 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7032 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7033 R_X86_64_GOTTPOFF relocation so that linker can safely
7034 perform IE->LE optimization. */
7035 if (x86_elf_abi
== X86_64_X32_ABI
7037 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7038 && i
.prefix
[REX_PREFIX
] == 0)
7039 add_prefix (REX_OPCODE
);
7042 /* The prefix bytes. */
7043 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7045 FRAG_APPEND_1_CHAR (*q
);
7049 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7054 /* REX byte is encoded in VEX prefix. */
7058 FRAG_APPEND_1_CHAR (*q
);
7061 /* There should be no other prefixes for instructions
7066 /* For EVEX instructions i.vrex should become 0 after
7067 build_evex_prefix. For VEX instructions upper 16 registers
7068 aren't available, so VREX should be 0. */
7071 /* Now the VEX prefix. */
7072 p
= frag_more (i
.vex
.length
);
7073 for (j
= 0; j
< i
.vex
.length
; j
++)
7074 p
[j
] = i
.vex
.bytes
[j
];
7077 /* Now the opcode; be careful about word order here! */
7078 if (i
.tm
.opcode_length
== 1)
7080 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7084 switch (i
.tm
.opcode_length
)
7088 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7089 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7093 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7103 /* Put out high byte first: can't use md_number_to_chars! */
7104 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7105 *p
= i
.tm
.base_opcode
& 0xff;
7108 /* Now the modrm byte and sib byte (if present). */
7109 if (i
.tm
.opcode_modifier
.modrm
)
7111 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7114 /* If i.rm.regmem == ESP (4)
7115 && i.rm.mode != (Register mode)
7117 ==> need second modrm byte. */
7118 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7120 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7121 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7123 | i
.sib
.scale
<< 6));
7126 if (i
.disp_operands
)
7127 output_disp (insn_start_frag
, insn_start_off
);
7130 output_imm (insn_start_frag
, insn_start_off
);
7136 pi ("" /*line*/, &i
);
7138 #endif /* DEBUG386 */
7141 /* Return the size of the displacement operand N. */
7144 disp_size (unsigned int n
)
7148 /* Vec_Disp8 has to be 8bit. */
7149 if (i
.types
[n
].bitfield
.vec_disp8
)
7151 else if (i
.types
[n
].bitfield
.disp64
)
7153 else if (i
.types
[n
].bitfield
.disp8
)
7155 else if (i
.types
[n
].bitfield
.disp16
)
7160 /* Return the size of the immediate operand N. */
7163 imm_size (unsigned int n
)
7166 if (i
.types
[n
].bitfield
.imm64
)
7168 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7170 else if (i
.types
[n
].bitfield
.imm16
)
7176 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7181 for (n
= 0; n
< i
.operands
; n
++)
7183 if (i
.types
[n
].bitfield
.vec_disp8
7184 || operand_type_check (i
.types
[n
], disp
))
7186 if (i
.op
[n
].disps
->X_op
== O_constant
)
7188 int size
= disp_size (n
);
7189 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7191 if (i
.types
[n
].bitfield
.vec_disp8
)
7193 val
= offset_in_range (val
, size
);
7194 p
= frag_more (size
);
7195 md_number_to_chars (p
, val
, size
);
7199 enum bfd_reloc_code_real reloc_type
;
7200 int size
= disp_size (n
);
7201 int sign
= i
.types
[n
].bitfield
.disp32s
;
7202 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7205 /* We can't have 8 bit displacement here. */
7206 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7208 /* The PC relative address is computed relative
7209 to the instruction boundary, so in case immediate
7210 fields follows, we need to adjust the value. */
7211 if (pcrel
&& i
.imm_operands
)
7216 for (n1
= 0; n1
< i
.operands
; n1
++)
7217 if (operand_type_check (i
.types
[n1
], imm
))
7219 /* Only one immediate is allowed for PC
7220 relative address. */
7221 gas_assert (sz
== 0);
7223 i
.op
[n
].disps
->X_add_number
-= sz
;
7225 /* We should find the immediate. */
7226 gas_assert (sz
!= 0);
7229 p
= frag_more (size
);
7230 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7232 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7233 && (((reloc_type
== BFD_RELOC_32
7234 || reloc_type
== BFD_RELOC_X86_64_32S
7235 || (reloc_type
== BFD_RELOC_64
7237 && (i
.op
[n
].disps
->X_op
== O_symbol
7238 || (i
.op
[n
].disps
->X_op
== O_add
7239 && ((symbol_get_value_expression
7240 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7242 || reloc_type
== BFD_RELOC_32_PCREL
))
7246 if (insn_start_frag
== frag_now
)
7247 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7252 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7253 for (fr
= insn_start_frag
->fr_next
;
7254 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7256 add
+= p
- frag_now
->fr_literal
;
7261 reloc_type
= BFD_RELOC_386_GOTPC
;
7262 i
.op
[n
].imms
->X_add_number
+= add
;
7264 else if (reloc_type
== BFD_RELOC_64
)
7265 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7267 /* Don't do the adjustment for x86-64, as there
7268 the pcrel addressing is relative to the _next_
7269 insn, and that is taken care of in other code. */
7270 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7272 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7273 size
, i
.op
[n
].disps
, pcrel
,
7275 /* Check for "call/jmp *mem", "mov mem, %reg",
7276 "test %reg, mem" and "binop mem, %reg" where binop
7277 is one of adc, add, and, cmp, or, sbb, sub, xor
7278 instructions. Always generate R_386_GOT32X for
7279 "sym*GOT" operand in 32-bit mode. */
7280 if ((generate_relax_relocations
7283 && i
.rm
.regmem
== 5))
7285 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7286 && ((i
.operands
== 1
7287 && i
.tm
.base_opcode
== 0xff
7288 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7290 && (i
.tm
.base_opcode
== 0x8b
7291 || i
.tm
.base_opcode
== 0x85
7292 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7296 fixP
->fx_tcbit
= i
.rex
!= 0;
7298 && (i
.base_reg
->reg_num
== RegRip
7299 || i
.base_reg
->reg_num
== RegEip
))
7300 fixP
->fx_tcbit2
= 1;
7303 fixP
->fx_tcbit2
= 1;
7311 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7316 for (n
= 0; n
< i
.operands
; n
++)
7318 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7319 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7322 if (operand_type_check (i
.types
[n
], imm
))
7324 if (i
.op
[n
].imms
->X_op
== O_constant
)
7326 int size
= imm_size (n
);
7329 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7331 p
= frag_more (size
);
7332 md_number_to_chars (p
, val
, size
);
7336 /* Not absolute_section.
7337 Need a 32-bit fixup (don't support 8bit
7338 non-absolute imms). Try to support other
7340 enum bfd_reloc_code_real reloc_type
;
7341 int size
= imm_size (n
);
7344 if (i
.types
[n
].bitfield
.imm32s
7345 && (i
.suffix
== QWORD_MNEM_SUFFIX
7346 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7351 p
= frag_more (size
);
7352 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7354 /* This is tough to explain. We end up with this one if we
7355 * have operands that look like
7356 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7357 * obtain the absolute address of the GOT, and it is strongly
7358 * preferable from a performance point of view to avoid using
7359 * a runtime relocation for this. The actual sequence of
7360 * instructions often look something like:
7365 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7367 * The call and pop essentially return the absolute address
7368 * of the label .L66 and store it in %ebx. The linker itself
7369 * will ultimately change the first operand of the addl so
7370 * that %ebx points to the GOT, but to keep things simple, the
7371 * .o file must have this operand set so that it generates not
7372 * the absolute address of .L66, but the absolute address of
7373 * itself. This allows the linker itself simply treat a GOTPC
7374 * relocation as asking for a pcrel offset to the GOT to be
7375 * added in, and the addend of the relocation is stored in the
7376 * operand field for the instruction itself.
7378 * Our job here is to fix the operand so that it would add
7379 * the correct offset so that %ebx would point to itself. The
7380 * thing that is tricky is that .-.L66 will point to the
7381 * beginning of the instruction, so we need to further modify
7382 * the operand so that it will point to itself. There are
7383 * other cases where you have something like:
7385 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7387 * and here no correction would be required. Internally in
7388 * the assembler we treat operands of this form as not being
7389 * pcrel since the '.' is explicitly mentioned, and I wonder
7390 * whether it would simplify matters to do it this way. Who
7391 * knows. In earlier versions of the PIC patches, the
7392 * pcrel_adjust field was used to store the correction, but
7393 * since the expression is not pcrel, I felt it would be
7394 * confusing to do it this way. */
7396 if ((reloc_type
== BFD_RELOC_32
7397 || reloc_type
== BFD_RELOC_X86_64_32S
7398 || reloc_type
== BFD_RELOC_64
)
7400 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7401 && (i
.op
[n
].imms
->X_op
== O_symbol
7402 || (i
.op
[n
].imms
->X_op
== O_add
7403 && ((symbol_get_value_expression
7404 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7409 if (insn_start_frag
== frag_now
)
7410 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7415 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7416 for (fr
= insn_start_frag
->fr_next
;
7417 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7419 add
+= p
- frag_now
->fr_literal
;
7423 reloc_type
= BFD_RELOC_386_GOTPC
;
7425 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7427 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7428 i
.op
[n
].imms
->X_add_number
+= add
;
7430 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7431 i
.op
[n
].imms
, 0, reloc_type
);
7437 /* x86_cons_fix_new is called via the expression parsing code when a
7438 reloc is needed. We use this hook to get the correct .got reloc. */
7439 static int cons_sign
= -1;
7442 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7443 expressionS
*exp
, bfd_reloc_code_real_type r
)
7445 r
= reloc (len
, 0, cons_sign
, r
);
7448 if (exp
->X_op
== O_secrel
)
7450 exp
->X_op
= O_symbol
;
7451 r
= BFD_RELOC_32_SECREL
;
7455 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7458 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7459 purpose of the `.dc.a' internal pseudo-op. */
7462 x86_address_bytes (void)
7464 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7466 return stdoutput
->arch_info
->bits_per_address
/ 8;
7469 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7471 # define lex_got(reloc, adjust, types) NULL
7473 /* Parse operands of the form
7474 <symbol>@GOTOFF+<nnn>
7475 and similar .plt or .got references.
7477 If we find one, set up the correct relocation in RELOC and copy the
7478 input string, minus the `@GOTOFF' into a malloc'd buffer for
7479 parsing by the calling routine. Return this buffer, and if ADJUST
7480 is non-null set it to the length of the string we removed from the
7481 input line. Otherwise return NULL. */
7483 lex_got (enum bfd_reloc_code_real
*rel
,
7485 i386_operand_type
*types
)
7487 /* Some of the relocations depend on the size of what field is to
7488 be relocated. But in our callers i386_immediate and i386_displacement
7489 we don't yet know the operand size (this will be set by insn
7490 matching). Hence we record the word32 relocation here,
7491 and adjust the reloc according to the real size in reloc(). */
7492 static const struct {
7495 const enum bfd_reloc_code_real rel
[2];
7496 const i386_operand_type types64
;
7498 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7499 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7501 OPERAND_TYPE_IMM32_64
},
7503 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7504 BFD_RELOC_X86_64_PLTOFF64
},
7505 OPERAND_TYPE_IMM64
},
7506 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7507 BFD_RELOC_X86_64_PLT32
},
7508 OPERAND_TYPE_IMM32_32S_DISP32
},
7509 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7510 BFD_RELOC_X86_64_GOTPLT64
},
7511 OPERAND_TYPE_IMM64_DISP64
},
7512 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7513 BFD_RELOC_X86_64_GOTOFF64
},
7514 OPERAND_TYPE_IMM64_DISP64
},
7515 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7516 BFD_RELOC_X86_64_GOTPCREL
},
7517 OPERAND_TYPE_IMM32_32S_DISP32
},
7518 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7519 BFD_RELOC_X86_64_TLSGD
},
7520 OPERAND_TYPE_IMM32_32S_DISP32
},
7521 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7522 _dummy_first_bfd_reloc_code_real
},
7523 OPERAND_TYPE_NONE
},
7524 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7525 BFD_RELOC_X86_64_TLSLD
},
7526 OPERAND_TYPE_IMM32_32S_DISP32
},
7527 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7528 BFD_RELOC_X86_64_GOTTPOFF
},
7529 OPERAND_TYPE_IMM32_32S_DISP32
},
7530 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7531 BFD_RELOC_X86_64_TPOFF32
},
7532 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7533 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7534 _dummy_first_bfd_reloc_code_real
},
7535 OPERAND_TYPE_NONE
},
7536 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7537 BFD_RELOC_X86_64_DTPOFF32
},
7538 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7539 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7540 _dummy_first_bfd_reloc_code_real
},
7541 OPERAND_TYPE_NONE
},
7542 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7543 _dummy_first_bfd_reloc_code_real
},
7544 OPERAND_TYPE_NONE
},
7545 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7546 BFD_RELOC_X86_64_GOT32
},
7547 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7548 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7549 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7550 OPERAND_TYPE_IMM32_32S_DISP32
},
7551 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7552 BFD_RELOC_X86_64_TLSDESC_CALL
},
7553 OPERAND_TYPE_IMM32_32S_DISP32
},
7558 #if defined (OBJ_MAYBE_ELF)
7563 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7564 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7567 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7569 int len
= gotrel
[j
].len
;
7570 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7572 if (gotrel
[j
].rel
[object_64bit
] != 0)
7575 char *tmpbuf
, *past_reloc
;
7577 *rel
= gotrel
[j
].rel
[object_64bit
];
7581 if (flag_code
!= CODE_64BIT
)
7583 types
->bitfield
.imm32
= 1;
7584 types
->bitfield
.disp32
= 1;
7587 *types
= gotrel
[j
].types64
;
7590 if (j
!= 0 && GOT_symbol
== NULL
)
7591 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7593 /* The length of the first part of our input line. */
7594 first
= cp
- input_line_pointer
;
7596 /* The second part goes from after the reloc token until
7597 (and including) an end_of_line char or comma. */
7598 past_reloc
= cp
+ 1 + len
;
7600 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7602 second
= cp
+ 1 - past_reloc
;
7604 /* Allocate and copy string. The trailing NUL shouldn't
7605 be necessary, but be safe. */
7606 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7607 memcpy (tmpbuf
, input_line_pointer
, first
);
7608 if (second
!= 0 && *past_reloc
!= ' ')
7609 /* Replace the relocation token with ' ', so that
7610 errors like foo@GOTOFF1 will be detected. */
7611 tmpbuf
[first
++] = ' ';
7613 /* Increment length by 1 if the relocation token is
7618 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7619 tmpbuf
[first
+ second
] = '\0';
7623 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7624 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7629 /* Might be a symbol version string. Don't as_bad here. */
7638 /* Parse operands of the form
7639 <symbol>@SECREL32+<nnn>
7641 If we find one, set up the correct relocation in RELOC and copy the
7642 input string, minus the `@SECREL32' into a malloc'd buffer for
7643 parsing by the calling routine. Return this buffer, and if ADJUST
7644 is non-null set it to the length of the string we removed from the
7645 input line. Otherwise return NULL.
7647 This function is copied from the ELF version above adjusted for PE targets. */
7650 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7651 int *adjust ATTRIBUTE_UNUSED
,
7652 i386_operand_type
*types
)
7658 const enum bfd_reloc_code_real rel
[2];
7659 const i386_operand_type types64
;
7663 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7664 BFD_RELOC_32_SECREL
},
7665 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7671 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7672 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7675 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7677 int len
= gotrel
[j
].len
;
7679 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7681 if (gotrel
[j
].rel
[object_64bit
] != 0)
7684 char *tmpbuf
, *past_reloc
;
7686 *rel
= gotrel
[j
].rel
[object_64bit
];
7692 if (flag_code
!= CODE_64BIT
)
7694 types
->bitfield
.imm32
= 1;
7695 types
->bitfield
.disp32
= 1;
7698 *types
= gotrel
[j
].types64
;
7701 /* The length of the first part of our input line. */
7702 first
= cp
- input_line_pointer
;
7704 /* The second part goes from after the reloc token until
7705 (and including) an end_of_line char or comma. */
7706 past_reloc
= cp
+ 1 + len
;
7708 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7710 second
= cp
+ 1 - past_reloc
;
7712 /* Allocate and copy string. The trailing NUL shouldn't
7713 be necessary, but be safe. */
7714 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7715 memcpy (tmpbuf
, input_line_pointer
, first
);
7716 if (second
!= 0 && *past_reloc
!= ' ')
7717 /* Replace the relocation token with ' ', so that
7718 errors like foo@SECLREL321 will be detected. */
7719 tmpbuf
[first
++] = ' ';
7720 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7721 tmpbuf
[first
+ second
] = '\0';
7725 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7726 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7731 /* Might be a symbol version string. Don't as_bad here. */
7737 bfd_reloc_code_real_type
7738 x86_cons (expressionS
*exp
, int size
)
7740 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7742 intel_syntax
= -intel_syntax
;
7745 if (size
== 4 || (object_64bit
&& size
== 8))
7747 /* Handle @GOTOFF and the like in an expression. */
7749 char *gotfree_input_line
;
7752 save
= input_line_pointer
;
7753 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7754 if (gotfree_input_line
)
7755 input_line_pointer
= gotfree_input_line
;
7759 if (gotfree_input_line
)
7761 /* expression () has merrily parsed up to the end of line,
7762 or a comma - in the wrong buffer. Transfer how far
7763 input_line_pointer has moved to the right buffer. */
7764 input_line_pointer
= (save
7765 + (input_line_pointer
- gotfree_input_line
)
7767 free (gotfree_input_line
);
7768 if (exp
->X_op
== O_constant
7769 || exp
->X_op
== O_absent
7770 || exp
->X_op
== O_illegal
7771 || exp
->X_op
== O_register
7772 || exp
->X_op
== O_big
)
7774 char c
= *input_line_pointer
;
7775 *input_line_pointer
= 0;
7776 as_bad (_("missing or invalid expression `%s'"), save
);
7777 *input_line_pointer
= c
;
7784 intel_syntax
= -intel_syntax
;
7787 i386_intel_simplify (exp
);
7793 signed_cons (int size
)
7795 if (flag_code
== CODE_64BIT
)
7803 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7810 if (exp
.X_op
== O_symbol
)
7811 exp
.X_op
= O_secrel
;
7813 emit_expr (&exp
, 4);
7815 while (*input_line_pointer
++ == ',');
7817 input_line_pointer
--;
7818 demand_empty_rest_of_line ();
7822 /* Handle Vector operations. */
7825 check_VecOperations (char *op_string
, char *op_end
)
7827 const reg_entry
*mask
;
7832 && (op_end
== NULL
|| op_string
< op_end
))
7835 if (*op_string
== '{')
7839 /* Check broadcasts. */
7840 if (strncmp (op_string
, "1to", 3) == 0)
7845 goto duplicated_vec_op
;
7848 if (*op_string
== '8')
7849 bcst_type
= BROADCAST_1TO8
;
7850 else if (*op_string
== '4')
7851 bcst_type
= BROADCAST_1TO4
;
7852 else if (*op_string
== '2')
7853 bcst_type
= BROADCAST_1TO2
;
7854 else if (*op_string
== '1'
7855 && *(op_string
+1) == '6')
7857 bcst_type
= BROADCAST_1TO16
;
7862 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7867 broadcast_op
.type
= bcst_type
;
7868 broadcast_op
.operand
= this_operand
;
7869 i
.broadcast
= &broadcast_op
;
7871 /* Check masking operation. */
7872 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7874 /* k0 can't be used for write mask. */
7875 if (mask
->reg_num
== 0)
7877 as_bad (_("`%s' can't be used for write mask"),
7884 mask_op
.mask
= mask
;
7885 mask_op
.zeroing
= 0;
7886 mask_op
.operand
= this_operand
;
7892 goto duplicated_vec_op
;
7894 i
.mask
->mask
= mask
;
7896 /* Only "{z}" is allowed here. No need to check
7897 zeroing mask explicitly. */
7898 if (i
.mask
->operand
!= this_operand
)
7900 as_bad (_("invalid write mask `%s'"), saved
);
7907 /* Check zeroing-flag for masking operation. */
7908 else if (*op_string
== 'z')
7912 mask_op
.mask
= NULL
;
7913 mask_op
.zeroing
= 1;
7914 mask_op
.operand
= this_operand
;
7919 if (i
.mask
->zeroing
)
7922 as_bad (_("duplicated `%s'"), saved
);
7926 i
.mask
->zeroing
= 1;
7928 /* Only "{%k}" is allowed here. No need to check mask
7929 register explicitly. */
7930 if (i
.mask
->operand
!= this_operand
)
7932 as_bad (_("invalid zeroing-masking `%s'"),
7941 goto unknown_vec_op
;
7943 if (*op_string
!= '}')
7945 as_bad (_("missing `}' in `%s'"), saved
);
7952 /* We don't know this one. */
7953 as_bad (_("unknown vector operation: `%s'"), saved
);
7961 i386_immediate (char *imm_start
)
7963 char *save_input_line_pointer
;
7964 char *gotfree_input_line
;
7967 i386_operand_type types
;
7969 operand_type_set (&types
, ~0);
7971 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7973 as_bad (_("at most %d immediate operands are allowed"),
7974 MAX_IMMEDIATE_OPERANDS
);
7978 exp
= &im_expressions
[i
.imm_operands
++];
7979 i
.op
[this_operand
].imms
= exp
;
7981 if (is_space_char (*imm_start
))
7984 save_input_line_pointer
= input_line_pointer
;
7985 input_line_pointer
= imm_start
;
7987 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7988 if (gotfree_input_line
)
7989 input_line_pointer
= gotfree_input_line
;
7991 exp_seg
= expression (exp
);
7995 /* Handle vector operations. */
7996 if (*input_line_pointer
== '{')
7998 input_line_pointer
= check_VecOperations (input_line_pointer
,
8000 if (input_line_pointer
== NULL
)
8004 if (*input_line_pointer
)
8005 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8007 input_line_pointer
= save_input_line_pointer
;
8008 if (gotfree_input_line
)
8010 free (gotfree_input_line
);
8012 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8013 exp
->X_op
= O_illegal
;
8016 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8020 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8021 i386_operand_type types
, const char *imm_start
)
8023 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8026 as_bad (_("missing or invalid immediate expression `%s'"),
8030 else if (exp
->X_op
== O_constant
)
8032 /* Size it properly later. */
8033 i
.types
[this_operand
].bitfield
.imm64
= 1;
8034 /* If not 64bit, sign extend val. */
8035 if (flag_code
!= CODE_64BIT
8036 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8038 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8040 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8041 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8042 && exp_seg
!= absolute_section
8043 && exp_seg
!= text_section
8044 && exp_seg
!= data_section
8045 && exp_seg
!= bss_section
8046 && exp_seg
!= undefined_section
8047 && !bfd_is_com_section (exp_seg
))
8049 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8053 else if (!intel_syntax
&& exp_seg
== reg_section
)
8056 as_bad (_("illegal immediate register operand %s"), imm_start
);
8061 /* This is an address. The size of the address will be
8062 determined later, depending on destination register,
8063 suffix, or the default for the section. */
8064 i
.types
[this_operand
].bitfield
.imm8
= 1;
8065 i
.types
[this_operand
].bitfield
.imm16
= 1;
8066 i
.types
[this_operand
].bitfield
.imm32
= 1;
8067 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8068 i
.types
[this_operand
].bitfield
.imm64
= 1;
8069 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8077 i386_scale (char *scale
)
8080 char *save
= input_line_pointer
;
8082 input_line_pointer
= scale
;
8083 val
= get_absolute_expression ();
8088 i
.log2_scale_factor
= 0;
8091 i
.log2_scale_factor
= 1;
8094 i
.log2_scale_factor
= 2;
8097 i
.log2_scale_factor
= 3;
8101 char sep
= *input_line_pointer
;
8103 *input_line_pointer
= '\0';
8104 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8106 *input_line_pointer
= sep
;
8107 input_line_pointer
= save
;
8111 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8113 as_warn (_("scale factor of %d without an index register"),
8114 1 << i
.log2_scale_factor
);
8115 i
.log2_scale_factor
= 0;
8117 scale
= input_line_pointer
;
8118 input_line_pointer
= save
;
8123 i386_displacement (char *disp_start
, char *disp_end
)
8127 char *save_input_line_pointer
;
8128 char *gotfree_input_line
;
8130 i386_operand_type bigdisp
, types
= anydisp
;
8133 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8135 as_bad (_("at most %d displacement operands are allowed"),
8136 MAX_MEMORY_OPERANDS
);
8140 operand_type_set (&bigdisp
, 0);
8141 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8142 || (!current_templates
->start
->opcode_modifier
.jump
8143 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8145 bigdisp
.bitfield
.disp32
= 1;
8146 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8147 if (flag_code
== CODE_64BIT
)
8151 bigdisp
.bitfield
.disp32s
= 1;
8152 bigdisp
.bitfield
.disp64
= 1;
8155 else if ((flag_code
== CODE_16BIT
) ^ override
)
8157 bigdisp
.bitfield
.disp32
= 0;
8158 bigdisp
.bitfield
.disp16
= 1;
8163 /* For PC-relative branches, the width of the displacement
8164 is dependent upon data size, not address size. */
8165 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8166 if (flag_code
== CODE_64BIT
)
8168 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8169 bigdisp
.bitfield
.disp16
= 1;
8172 bigdisp
.bitfield
.disp32
= 1;
8173 bigdisp
.bitfield
.disp32s
= 1;
8179 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8181 : LONG_MNEM_SUFFIX
));
8182 bigdisp
.bitfield
.disp32
= 1;
8183 if ((flag_code
== CODE_16BIT
) ^ override
)
8185 bigdisp
.bitfield
.disp32
= 0;
8186 bigdisp
.bitfield
.disp16
= 1;
8190 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8193 exp
= &disp_expressions
[i
.disp_operands
];
8194 i
.op
[this_operand
].disps
= exp
;
8196 save_input_line_pointer
= input_line_pointer
;
8197 input_line_pointer
= disp_start
;
8198 END_STRING_AND_SAVE (disp_end
);
8200 #ifndef GCC_ASM_O_HACK
8201 #define GCC_ASM_O_HACK 0
8204 END_STRING_AND_SAVE (disp_end
+ 1);
8205 if (i
.types
[this_operand
].bitfield
.baseIndex
8206 && displacement_string_end
[-1] == '+')
8208 /* This hack is to avoid a warning when using the "o"
8209 constraint within gcc asm statements.
8212 #define _set_tssldt_desc(n,addr,limit,type) \
8213 __asm__ __volatile__ ( \
8215 "movw %w1,2+%0\n\t" \
8217 "movb %b1,4+%0\n\t" \
8218 "movb %4,5+%0\n\t" \
8219 "movb $0,6+%0\n\t" \
8220 "movb %h1,7+%0\n\t" \
8222 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8224 This works great except that the output assembler ends
8225 up looking a bit weird if it turns out that there is
8226 no offset. You end up producing code that looks like:
8239 So here we provide the missing zero. */
8241 *displacement_string_end
= '0';
8244 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8245 if (gotfree_input_line
)
8246 input_line_pointer
= gotfree_input_line
;
8248 exp_seg
= expression (exp
);
8251 if (*input_line_pointer
)
8252 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8254 RESTORE_END_STRING (disp_end
+ 1);
8256 input_line_pointer
= save_input_line_pointer
;
8257 if (gotfree_input_line
)
8259 free (gotfree_input_line
);
8261 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8262 exp
->X_op
= O_illegal
;
8265 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8267 RESTORE_END_STRING (disp_end
);
8273 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8274 i386_operand_type types
, const char *disp_start
)
8276 i386_operand_type bigdisp
;
8279 /* We do this to make sure that the section symbol is in
8280 the symbol table. We will ultimately change the relocation
8281 to be relative to the beginning of the section. */
8282 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8283 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8284 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8286 if (exp
->X_op
!= O_symbol
)
8289 if (S_IS_LOCAL (exp
->X_add_symbol
)
8290 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8291 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8292 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8293 exp
->X_op
= O_subtract
;
8294 exp
->X_op_symbol
= GOT_symbol
;
8295 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8296 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8297 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8298 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8300 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8303 else if (exp
->X_op
== O_absent
8304 || exp
->X_op
== O_illegal
8305 || exp
->X_op
== O_big
)
8308 as_bad (_("missing or invalid displacement expression `%s'"),
8313 else if (flag_code
== CODE_64BIT
8314 && !i
.prefix
[ADDR_PREFIX
]
8315 && exp
->X_op
== O_constant
)
8317 /* Since displacement is signed extended to 64bit, don't allow
8318 disp32 and turn off disp32s if they are out of range. */
8319 i
.types
[this_operand
].bitfield
.disp32
= 0;
8320 if (!fits_in_signed_long (exp
->X_add_number
))
8322 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8323 if (i
.types
[this_operand
].bitfield
.baseindex
)
8325 as_bad (_("0x%lx out range of signed 32bit displacement"),
8326 (long) exp
->X_add_number
);
8332 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8333 else if (exp
->X_op
!= O_constant
8334 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8335 && exp_seg
!= absolute_section
8336 && exp_seg
!= text_section
8337 && exp_seg
!= data_section
8338 && exp_seg
!= bss_section
8339 && exp_seg
!= undefined_section
8340 && !bfd_is_com_section (exp_seg
))
8342 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8347 /* Check if this is a displacement only operand. */
8348 bigdisp
= i
.types
[this_operand
];
8349 bigdisp
.bitfield
.disp8
= 0;
8350 bigdisp
.bitfield
.disp16
= 0;
8351 bigdisp
.bitfield
.disp32
= 0;
8352 bigdisp
.bitfield
.disp32s
= 0;
8353 bigdisp
.bitfield
.disp64
= 0;
8354 if (operand_type_all_zero (&bigdisp
))
8355 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8361 /* Make sure the memory operand we've been dealt is valid.
8362 Return 1 on success, 0 on a failure. */
8365 i386_index_check (const char *operand_string
)
8367 const char *kind
= "base/index";
8368 enum flag_code addr_mode
;
8370 if (i
.prefix
[ADDR_PREFIX
])
8371 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8374 addr_mode
= flag_code
;
8376 #if INFER_ADDR_PREFIX
8377 if (i
.mem_operands
== 0)
8379 /* Infer address prefix from the first memory operand. */
8380 const reg_entry
*addr_reg
= i
.base_reg
;
8382 if (addr_reg
== NULL
)
8383 addr_reg
= i
.index_reg
;
8387 if (addr_reg
->reg_num
== RegEip
8388 || addr_reg
->reg_num
== RegEiz
8389 || addr_reg
->reg_type
.bitfield
.reg32
)
8390 addr_mode
= CODE_32BIT
;
8391 else if (flag_code
!= CODE_64BIT
8392 && addr_reg
->reg_type
.bitfield
.reg16
)
8393 addr_mode
= CODE_16BIT
;
8395 if (addr_mode
!= flag_code
)
8397 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8399 /* Change the size of any displacement too. At most one
8400 of Disp16 or Disp32 is set.
8401 FIXME. There doesn't seem to be any real need for
8402 separate Disp16 and Disp32 flags. The same goes for
8403 Imm16 and Imm32. Removing them would probably clean
8404 up the code quite a lot. */
8405 if (flag_code
!= CODE_64BIT
8406 && (i
.types
[this_operand
].bitfield
.disp16
8407 || i
.types
[this_operand
].bitfield
.disp32
))
8408 i
.types
[this_operand
]
8409 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8416 if (current_templates
->start
->opcode_modifier
.isstring
8417 && !current_templates
->start
->opcode_modifier
.immext
8418 && (current_templates
->end
[-1].opcode_modifier
.isstring
8421 /* Memory operands of string insns are special in that they only allow
8422 a single register (rDI, rSI, or rBX) as their memory address. */
8423 const reg_entry
*expected_reg
;
8424 static const char *di_si
[][2] =
8430 static const char *bx
[] = { "ebx", "bx", "rbx" };
8432 kind
= "string address";
8434 if (current_templates
->start
->opcode_modifier
.w
)
8436 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8438 if (!type
.bitfield
.baseindex
8439 || ((!i
.mem_operands
!= !intel_syntax
)
8440 && current_templates
->end
[-1].operand_types
[1]
8441 .bitfield
.baseindex
))
8442 type
= current_templates
->end
[-1].operand_types
[1];
8443 expected_reg
= hash_find (reg_hash
,
8444 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8448 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8450 if (i
.base_reg
!= expected_reg
8452 || operand_type_check (i
.types
[this_operand
], disp
))
8454 /* The second memory operand must have the same size as
8458 && !((addr_mode
== CODE_64BIT
8459 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8460 || (addr_mode
== CODE_32BIT
8461 ? i
.base_reg
->reg_type
.bitfield
.reg32
8462 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8465 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8467 intel_syntax
? '[' : '(',
8469 expected_reg
->reg_name
,
8470 intel_syntax
? ']' : ')');
8477 as_bad (_("`%s' is not a valid %s expression"),
8478 operand_string
, kind
);
8483 if (addr_mode
!= CODE_16BIT
)
8485 /* 32-bit/64-bit checks. */
8487 && (addr_mode
== CODE_64BIT
8488 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8489 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8491 || (i
.base_reg
->reg_num
8492 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8494 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8495 && !i
.index_reg
->reg_type
.bitfield
.regymm
8496 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8497 && ((addr_mode
== CODE_64BIT
8498 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8499 || i
.index_reg
->reg_num
== RegRiz
)
8500 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8501 || i
.index_reg
->reg_num
== RegEiz
))
8502 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8507 /* 16-bit checks. */
8509 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8510 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8512 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8513 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8515 && i
.base_reg
->reg_num
< 6
8516 && i
.index_reg
->reg_num
>= 6
8517 && i
.log2_scale_factor
== 0))))
8524 /* Handle vector immediates. */
8527 RC_SAE_immediate (const char *imm_start
)
8529 unsigned int match_found
, j
;
8530 const char *pstr
= imm_start
;
8538 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8540 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8544 rc_op
.type
= RC_NamesTable
[j
].type
;
8545 rc_op
.operand
= this_operand
;
8546 i
.rounding
= &rc_op
;
8550 as_bad (_("duplicated `%s'"), imm_start
);
8553 pstr
+= RC_NamesTable
[j
].len
;
8563 as_bad (_("Missing '}': '%s'"), imm_start
);
8566 /* RC/SAE immediate string should contain nothing more. */;
8569 as_bad (_("Junk after '}': '%s'"), imm_start
);
8573 exp
= &im_expressions
[i
.imm_operands
++];
8574 i
.op
[this_operand
].imms
= exp
;
8576 exp
->X_op
= O_constant
;
8577 exp
->X_add_number
= 0;
8578 exp
->X_add_symbol
= (symbolS
*) 0;
8579 exp
->X_op_symbol
= (symbolS
*) 0;
8581 i
.types
[this_operand
].bitfield
.imm8
= 1;
8585 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8589 i386_att_operand (char *operand_string
)
8593 char *op_string
= operand_string
;
8595 if (is_space_char (*op_string
))
8598 /* We check for an absolute prefix (differentiating,
8599 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8600 if (*op_string
== ABSOLUTE_PREFIX
)
8603 if (is_space_char (*op_string
))
8605 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8608 /* Check if operand is a register. */
8609 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8611 i386_operand_type temp
;
8613 /* Check for a segment override by searching for ':' after a
8614 segment register. */
8616 if (is_space_char (*op_string
))
8618 if (*op_string
== ':'
8619 && (r
->reg_type
.bitfield
.sreg2
8620 || r
->reg_type
.bitfield
.sreg3
))
8625 i
.seg
[i
.mem_operands
] = &es
;
8628 i
.seg
[i
.mem_operands
] = &cs
;
8631 i
.seg
[i
.mem_operands
] = &ss
;
8634 i
.seg
[i
.mem_operands
] = &ds
;
8637 i
.seg
[i
.mem_operands
] = &fs
;
8640 i
.seg
[i
.mem_operands
] = &gs
;
8644 /* Skip the ':' and whitespace. */
8646 if (is_space_char (*op_string
))
8649 if (!is_digit_char (*op_string
)
8650 && !is_identifier_char (*op_string
)
8651 && *op_string
!= '('
8652 && *op_string
!= ABSOLUTE_PREFIX
)
8654 as_bad (_("bad memory operand `%s'"), op_string
);
8657 /* Handle case of %es:*foo. */
8658 if (*op_string
== ABSOLUTE_PREFIX
)
8661 if (is_space_char (*op_string
))
8663 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8665 goto do_memory_reference
;
8668 /* Handle vector operations. */
8669 if (*op_string
== '{')
8671 op_string
= check_VecOperations (op_string
, NULL
);
8672 if (op_string
== NULL
)
8678 as_bad (_("junk `%s' after register"), op_string
);
8682 temp
.bitfield
.baseindex
= 0;
8683 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8685 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8686 i
.op
[this_operand
].regs
= r
;
8689 else if (*op_string
== REGISTER_PREFIX
)
8691 as_bad (_("bad register name `%s'"), op_string
);
8694 else if (*op_string
== IMMEDIATE_PREFIX
)
8697 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8699 as_bad (_("immediate operand illegal with absolute jump"));
8702 if (!i386_immediate (op_string
))
8705 else if (RC_SAE_immediate (operand_string
))
8707 /* If it is a RC or SAE immediate, do nothing. */
8710 else if (is_digit_char (*op_string
)
8711 || is_identifier_char (*op_string
)
8712 || *op_string
== '"'
8713 || *op_string
== '(')
8715 /* This is a memory reference of some sort. */
8718 /* Start and end of displacement string expression (if found). */
8719 char *displacement_string_start
;
8720 char *displacement_string_end
;
8723 do_memory_reference
:
8724 if ((i
.mem_operands
== 1
8725 && !current_templates
->start
->opcode_modifier
.isstring
)
8726 || i
.mem_operands
== 2)
8728 as_bad (_("too many memory references for `%s'"),
8729 current_templates
->start
->name
);
8733 /* Check for base index form. We detect the base index form by
8734 looking for an ')' at the end of the operand, searching
8735 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8737 base_string
= op_string
+ strlen (op_string
);
8739 /* Handle vector operations. */
8740 vop_start
= strchr (op_string
, '{');
8741 if (vop_start
&& vop_start
< base_string
)
8743 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8745 base_string
= vop_start
;
8749 if (is_space_char (*base_string
))
8752 /* If we only have a displacement, set-up for it to be parsed later. */
8753 displacement_string_start
= op_string
;
8754 displacement_string_end
= base_string
+ 1;
8756 if (*base_string
== ')')
8759 unsigned int parens_balanced
= 1;
8760 /* We've already checked that the number of left & right ()'s are
8761 equal, so this loop will not be infinite. */
8765 if (*base_string
== ')')
8767 if (*base_string
== '(')
8770 while (parens_balanced
);
8772 temp_string
= base_string
;
8774 /* Skip past '(' and whitespace. */
8776 if (is_space_char (*base_string
))
8779 if (*base_string
== ','
8780 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8783 displacement_string_end
= temp_string
;
8785 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8789 base_string
= end_op
;
8790 if (is_space_char (*base_string
))
8794 /* There may be an index reg or scale factor here. */
8795 if (*base_string
== ',')
8798 if (is_space_char (*base_string
))
8801 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8804 base_string
= end_op
;
8805 if (is_space_char (*base_string
))
8807 if (*base_string
== ',')
8810 if (is_space_char (*base_string
))
8813 else if (*base_string
!= ')')
8815 as_bad (_("expecting `,' or `)' "
8816 "after index register in `%s'"),
8821 else if (*base_string
== REGISTER_PREFIX
)
8823 end_op
= strchr (base_string
, ',');
8826 as_bad (_("bad register name `%s'"), base_string
);
8830 /* Check for scale factor. */
8831 if (*base_string
!= ')')
8833 char *end_scale
= i386_scale (base_string
);
8838 base_string
= end_scale
;
8839 if (is_space_char (*base_string
))
8841 if (*base_string
!= ')')
8843 as_bad (_("expecting `)' "
8844 "after scale factor in `%s'"),
8849 else if (!i
.index_reg
)
8851 as_bad (_("expecting index register or scale factor "
8852 "after `,'; got '%c'"),
8857 else if (*base_string
!= ')')
8859 as_bad (_("expecting `,' or `)' "
8860 "after base register in `%s'"),
8865 else if (*base_string
== REGISTER_PREFIX
)
8867 end_op
= strchr (base_string
, ',');
8870 as_bad (_("bad register name `%s'"), base_string
);
8875 /* If there's an expression beginning the operand, parse it,
8876 assuming displacement_string_start and
8877 displacement_string_end are meaningful. */
8878 if (displacement_string_start
!= displacement_string_end
)
8880 if (!i386_displacement (displacement_string_start
,
8881 displacement_string_end
))
8885 /* Special case for (%dx) while doing input/output op. */
8887 && operand_type_equal (&i
.base_reg
->reg_type
,
8888 ®16_inoutportreg
)
8890 && i
.log2_scale_factor
== 0
8891 && i
.seg
[i
.mem_operands
] == 0
8892 && !operand_type_check (i
.types
[this_operand
], disp
))
8894 i
.types
[this_operand
] = inoutportreg
;
8898 if (i386_index_check (operand_string
) == 0)
8900 i
.types
[this_operand
].bitfield
.mem
= 1;
8905 /* It's not a memory operand; argh! */
8906 as_bad (_("invalid char %s beginning operand %d `%s'"),
8907 output_invalid (*op_string
),
8912 return 1; /* Normal return. */
8915 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8916 that an rs_machine_dependent frag may reach. */
8919 i386_frag_max_var (fragS
*frag
)
8921 /* The only relaxable frags are for jumps.
8922 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8923 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8924 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8927 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8929 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
8931 /* STT_GNU_IFUNC symbol must go through PLT. */
8932 if ((symbol_get_bfdsym (fr_symbol
)->flags
8933 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
8936 if (!S_IS_EXTERNAL (fr_symbol
))
8937 /* Symbol may be weak or local. */
8938 return !S_IS_WEAK (fr_symbol
);
8940 /* Global symbols with non-default visibility can't be preempted. */
8941 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
8944 if (fr_var
!= NO_RELOC
)
8945 switch ((enum bfd_reloc_code_real
) fr_var
)
8947 case BFD_RELOC_386_PLT32
:
8948 case BFD_RELOC_X86_64_PLT32
:
8949 /* Symbol with PLT relocatin may be preempted. */
8955 /* Global symbols with default visibility in a shared library may be
8956 preempted by another definition. */
8961 /* md_estimate_size_before_relax()
8963 Called just before relax() for rs_machine_dependent frags. The x86
8964 assembler uses these frags to handle variable size jump
8967 Any symbol that is now undefined will not become defined.
8968 Return the correct fr_subtype in the frag.
8969 Return the initial "guess for variable size of frag" to caller.
8970 The guess is actually the growth beyond the fixed part. Whatever
8971 we do to grow the fixed or variable part contributes to our
8975 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8977 /* We've already got fragP->fr_subtype right; all we have to do is
8978 check for un-relaxable symbols. On an ELF system, we can't relax
8979 an externally visible symbol, because it may be overridden by a
8981 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8982 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8984 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
8987 #if defined (OBJ_COFF) && defined (TE_PE)
8988 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8989 && S_IS_WEAK (fragP
->fr_symbol
))
8993 /* Symbol is undefined in this segment, or we need to keep a
8994 reloc so that weak symbols can be overridden. */
8995 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8996 enum bfd_reloc_code_real reloc_type
;
8997 unsigned char *opcode
;
9000 if (fragP
->fr_var
!= NO_RELOC
)
9001 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9003 reloc_type
= BFD_RELOC_16_PCREL
;
9005 reloc_type
= BFD_RELOC_32_PCREL
;
9007 old_fr_fix
= fragP
->fr_fix
;
9008 opcode
= (unsigned char *) fragP
->fr_opcode
;
9010 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9013 /* Make jmp (0xeb) a (d)word displacement jump. */
9015 fragP
->fr_fix
+= size
;
9016 fix_new (fragP
, old_fr_fix
, size
,
9018 fragP
->fr_offset
, 1,
9024 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9026 /* Negate the condition, and branch past an
9027 unconditional jump. */
9030 /* Insert an unconditional jump. */
9032 /* We added two extra opcode bytes, and have a two byte
9034 fragP
->fr_fix
+= 2 + 2;
9035 fix_new (fragP
, old_fr_fix
+ 2, 2,
9037 fragP
->fr_offset
, 1,
9044 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9049 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9051 fragP
->fr_offset
, 1,
9053 fixP
->fx_signed
= 1;
9057 /* This changes the byte-displacement jump 0x7N
9058 to the (d)word-displacement jump 0x0f,0x8N. */
9059 opcode
[1] = opcode
[0] + 0x10;
9060 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9061 /* We've added an opcode byte. */
9062 fragP
->fr_fix
+= 1 + size
;
9063 fix_new (fragP
, old_fr_fix
+ 1, size
,
9065 fragP
->fr_offset
, 1,
9070 BAD_CASE (fragP
->fr_subtype
);
9074 return fragP
->fr_fix
- old_fr_fix
;
9077 /* Guess size depending on current relax state. Initially the relax
9078 state will correspond to a short jump and we return 1, because
9079 the variable part of the frag (the branch offset) is one byte
9080 long. However, we can relax a section more than once and in that
9081 case we must either set fr_subtype back to the unrelaxed state,
9082 or return the value for the appropriate branch. */
9083 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9086 /* Called after relax() is finished.
9088 In: Address of frag.
9089 fr_type == rs_machine_dependent.
9090 fr_subtype is what the address relaxed to.
9092 Out: Any fixSs and constants are set up.
9093 Caller will turn frag into a ".space 0". */
9096 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9099 unsigned char *opcode
;
9100 unsigned char *where_to_put_displacement
= NULL
;
9101 offsetT target_address
;
9102 offsetT opcode_address
;
9103 unsigned int extension
= 0;
9104 offsetT displacement_from_opcode_start
;
9106 opcode
= (unsigned char *) fragP
->fr_opcode
;
9108 /* Address we want to reach in file space. */
9109 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9111 /* Address opcode resides at in file space. */
9112 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9114 /* Displacement from opcode start to fill into instruction. */
9115 displacement_from_opcode_start
= target_address
- opcode_address
;
9117 if ((fragP
->fr_subtype
& BIG
) == 0)
9119 /* Don't have to change opcode. */
9120 extension
= 1; /* 1 opcode + 1 displacement */
9121 where_to_put_displacement
= &opcode
[1];
9125 if (no_cond_jump_promotion
9126 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9127 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9128 _("long jump required"));
9130 switch (fragP
->fr_subtype
)
9132 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9133 extension
= 4; /* 1 opcode + 4 displacement */
9135 where_to_put_displacement
= &opcode
[1];
9138 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9139 extension
= 2; /* 1 opcode + 2 displacement */
9141 where_to_put_displacement
= &opcode
[1];
9144 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9145 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9146 extension
= 5; /* 2 opcode + 4 displacement */
9147 opcode
[1] = opcode
[0] + 0x10;
9148 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9149 where_to_put_displacement
= &opcode
[2];
9152 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9153 extension
= 3; /* 2 opcode + 2 displacement */
9154 opcode
[1] = opcode
[0] + 0x10;
9155 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9156 where_to_put_displacement
= &opcode
[2];
9159 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9164 where_to_put_displacement
= &opcode
[3];
9168 BAD_CASE (fragP
->fr_subtype
);
9173 /* If size if less then four we are sure that the operand fits,
9174 but if it's 4, then it could be that the displacement is larger
9176 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9178 && ((addressT
) (displacement_from_opcode_start
- extension
9179 + ((addressT
) 1 << 31))
9180 > (((addressT
) 2 << 31) - 1)))
9182 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9183 _("jump target out of range"));
9184 /* Make us emit 0. */
9185 displacement_from_opcode_start
= extension
;
9187 /* Now put displacement after opcode. */
9188 md_number_to_chars ((char *) where_to_put_displacement
,
9189 (valueT
) (displacement_from_opcode_start
- extension
),
9190 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9191 fragP
->fr_fix
+= extension
;
9194 /* Apply a fixup (fixP) to segment data, once it has been determined
9195 by our caller that we have all the info we need to fix it up.
9197 Parameter valP is the pointer to the value of the bits.
9199 On the 386, immediates, displacements, and data pointers are all in
9200 the same (little-endian) format, so we don't need to care about which
9204 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9206 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9207 valueT value
= *valP
;
9209 #if !defined (TE_Mach)
9212 switch (fixP
->fx_r_type
)
9218 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9221 case BFD_RELOC_X86_64_32S
:
9222 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9225 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9228 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9233 if (fixP
->fx_addsy
!= NULL
9234 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9235 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9236 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9237 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9238 && !use_rela_relocations
)
9240 /* This is a hack. There should be a better way to handle this.
9241 This covers for the fact that bfd_install_relocation will
9242 subtract the current location (for partial_inplace, PC relative
9243 relocations); see more below. */
9247 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9250 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9252 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9255 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9258 || (symbol_section_p (fixP
->fx_addsy
)
9259 && sym_seg
!= absolute_section
))
9260 && !generic_force_reloc (fixP
))
9262 /* Yes, we add the values in twice. This is because
9263 bfd_install_relocation subtracts them out again. I think
9264 bfd_install_relocation is broken, but I don't dare change
9266 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9270 #if defined (OBJ_COFF) && defined (TE_PE)
9271 /* For some reason, the PE format does not store a
9272 section address offset for a PC relative symbol. */
9273 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9274 || S_IS_WEAK (fixP
->fx_addsy
))
9275 value
+= md_pcrel_from (fixP
);
9278 #if defined (OBJ_COFF) && defined (TE_PE)
9279 if (fixP
->fx_addsy
!= NULL
9280 && S_IS_WEAK (fixP
->fx_addsy
)
9281 /* PR 16858: Do not modify weak function references. */
9282 && ! fixP
->fx_pcrel
)
9284 #if !defined (TE_PEP)
9285 /* For x86 PE weak function symbols are neither PC-relative
9286 nor do they set S_IS_FUNCTION. So the only reliable way
9287 to detect them is to check the flags of their containing
9289 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9290 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9294 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9298 /* Fix a few things - the dynamic linker expects certain values here,
9299 and we must not disappoint it. */
9300 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9301 if (IS_ELF
&& fixP
->fx_addsy
)
9302 switch (fixP
->fx_r_type
)
9304 case BFD_RELOC_386_PLT32
:
9305 case BFD_RELOC_X86_64_PLT32
:
9306 /* Make the jump instruction point to the address of the operand. At
9307 runtime we merely add the offset to the actual PLT entry. */
9311 case BFD_RELOC_386_TLS_GD
:
9312 case BFD_RELOC_386_TLS_LDM
:
9313 case BFD_RELOC_386_TLS_IE_32
:
9314 case BFD_RELOC_386_TLS_IE
:
9315 case BFD_RELOC_386_TLS_GOTIE
:
9316 case BFD_RELOC_386_TLS_GOTDESC
:
9317 case BFD_RELOC_X86_64_TLSGD
:
9318 case BFD_RELOC_X86_64_TLSLD
:
9319 case BFD_RELOC_X86_64_GOTTPOFF
:
9320 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9321 value
= 0; /* Fully resolved at runtime. No addend. */
9323 case BFD_RELOC_386_TLS_LE
:
9324 case BFD_RELOC_386_TLS_LDO_32
:
9325 case BFD_RELOC_386_TLS_LE_32
:
9326 case BFD_RELOC_X86_64_DTPOFF32
:
9327 case BFD_RELOC_X86_64_DTPOFF64
:
9328 case BFD_RELOC_X86_64_TPOFF32
:
9329 case BFD_RELOC_X86_64_TPOFF64
:
9330 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9333 case BFD_RELOC_386_TLS_DESC_CALL
:
9334 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9335 value
= 0; /* Fully resolved at runtime. No addend. */
9336 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9340 case BFD_RELOC_386_GOT32
:
9341 case BFD_RELOC_X86_64_GOT32
:
9342 value
= 0; /* Fully resolved at runtime. No addend. */
9345 case BFD_RELOC_VTABLE_INHERIT
:
9346 case BFD_RELOC_VTABLE_ENTRY
:
9353 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9355 #endif /* !defined (TE_Mach) */
9357 /* Are we finished with this relocation now? */
9358 if (fixP
->fx_addsy
== NULL
)
9360 #if defined (OBJ_COFF) && defined (TE_PE)
9361 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9364 /* Remember value for tc_gen_reloc. */
9365 fixP
->fx_addnumber
= value
;
9366 /* Clear out the frag for now. */
9370 else if (use_rela_relocations
)
9372 fixP
->fx_no_overflow
= 1;
9373 /* Remember value for tc_gen_reloc. */
9374 fixP
->fx_addnumber
= value
;
9378 md_number_to_chars (p
, value
, fixP
->fx_size
);
9382 md_atof (int type
, char *litP
, int *sizeP
)
9384 /* This outputs the LITTLENUMs in REVERSE order;
9385 in accord with the bigendian 386. */
9386 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9389 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9392 output_invalid (int c
)
9395 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9398 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9399 "(0x%x)", (unsigned char) c
);
9400 return output_invalid_buf
;
9403 /* REG_STRING starts *before* REGISTER_PREFIX. */
9405 static const reg_entry
*
9406 parse_real_register (char *reg_string
, char **end_op
)
9408 char *s
= reg_string
;
9410 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9413 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9414 if (*s
== REGISTER_PREFIX
)
9417 if (is_space_char (*s
))
9421 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9423 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9424 return (const reg_entry
*) NULL
;
9428 /* For naked regs, make sure that we are not dealing with an identifier.
9429 This prevents confusing an identifier like `eax_var' with register
9431 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9432 return (const reg_entry
*) NULL
;
9436 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9438 /* Handle floating point regs, allowing spaces in the (i) part. */
9439 if (r
== i386_regtab
/* %st is first entry of table */)
9441 if (is_space_char (*s
))
9446 if (is_space_char (*s
))
9448 if (*s
>= '0' && *s
<= '7')
9452 if (is_space_char (*s
))
9457 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9462 /* We have "%st(" then garbage. */
9463 return (const reg_entry
*) NULL
;
9467 if (r
== NULL
|| allow_pseudo_reg
)
9470 if (operand_type_all_zero (&r
->reg_type
))
9471 return (const reg_entry
*) NULL
;
9473 if ((r
->reg_type
.bitfield
.reg32
9474 || r
->reg_type
.bitfield
.sreg3
9475 || r
->reg_type
.bitfield
.control
9476 || r
->reg_type
.bitfield
.debug
9477 || r
->reg_type
.bitfield
.test
)
9478 && !cpu_arch_flags
.bitfield
.cpui386
)
9479 return (const reg_entry
*) NULL
;
9481 if (r
->reg_type
.bitfield
.floatreg
9482 && !cpu_arch_flags
.bitfield
.cpu8087
9483 && !cpu_arch_flags
.bitfield
.cpu287
9484 && !cpu_arch_flags
.bitfield
.cpu387
)
9485 return (const reg_entry
*) NULL
;
9487 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9488 return (const reg_entry
*) NULL
;
9490 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9491 return (const reg_entry
*) NULL
;
9493 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9494 return (const reg_entry
*) NULL
;
9496 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9497 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9498 return (const reg_entry
*) NULL
;
9500 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9501 if (!allow_index_reg
9502 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9503 return (const reg_entry
*) NULL
;
9505 /* Upper 16 vector register is only available with VREX in 64bit
9507 if ((r
->reg_flags
& RegVRex
))
9509 if (!cpu_arch_flags
.bitfield
.cpuvrex
9510 || flag_code
!= CODE_64BIT
)
9511 return (const reg_entry
*) NULL
;
9516 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9517 || r
->reg_type
.bitfield
.reg64
)
9518 && (!cpu_arch_flags
.bitfield
.cpulm
9519 || !operand_type_equal (&r
->reg_type
, &control
))
9520 && flag_code
!= CODE_64BIT
)
9521 return (const reg_entry
*) NULL
;
9523 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9524 return (const reg_entry
*) NULL
;
9529 /* REG_STRING starts *before* REGISTER_PREFIX. */
9531 static const reg_entry
*
9532 parse_register (char *reg_string
, char **end_op
)
9536 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9537 r
= parse_real_register (reg_string
, end_op
);
9542 char *save
= input_line_pointer
;
9546 input_line_pointer
= reg_string
;
9547 c
= get_symbol_name (®_string
);
9548 symbolP
= symbol_find (reg_string
);
9549 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9551 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9553 know (e
->X_op
== O_register
);
9554 know (e
->X_add_number
>= 0
9555 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9556 r
= i386_regtab
+ e
->X_add_number
;
9557 if ((r
->reg_flags
& RegVRex
))
9559 *end_op
= input_line_pointer
;
9561 *input_line_pointer
= c
;
9562 input_line_pointer
= save
;
9568 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9571 char *end
= input_line_pointer
;
9574 r
= parse_register (name
, &input_line_pointer
);
9575 if (r
&& end
<= input_line_pointer
)
9577 *nextcharP
= *input_line_pointer
;
9578 *input_line_pointer
= 0;
9579 e
->X_op
= O_register
;
9580 e
->X_add_number
= r
- i386_regtab
;
9583 input_line_pointer
= end
;
9585 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9589 md_operand (expressionS
*e
)
9594 switch (*input_line_pointer
)
9596 case REGISTER_PREFIX
:
9597 r
= parse_real_register (input_line_pointer
, &end
);
9600 e
->X_op
= O_register
;
9601 e
->X_add_number
= r
- i386_regtab
;
9602 input_line_pointer
= end
;
9607 gas_assert (intel_syntax
);
9608 end
= input_line_pointer
++;
9610 if (*input_line_pointer
== ']')
9612 ++input_line_pointer
;
9613 e
->X_op_symbol
= make_expr_symbol (e
);
9614 e
->X_add_symbol
= NULL
;
9615 e
->X_add_number
= 0;
9621 input_line_pointer
= end
;
9628 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9629 const char *md_shortopts
= "kVQ:sqn";
9631 const char *md_shortopts
= "qn";
9634 #define OPTION_32 (OPTION_MD_BASE + 0)
9635 #define OPTION_64 (OPTION_MD_BASE + 1)
9636 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9637 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9638 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9639 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9640 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9641 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9642 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9643 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9644 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9645 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9646 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9647 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9648 #define OPTION_X32 (OPTION_MD_BASE + 14)
9649 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9650 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9651 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9652 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9653 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9654 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9655 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9656 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9657 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9658 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9659 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
9661 struct option md_longopts
[] =
9663 {"32", no_argument
, NULL
, OPTION_32
},
9664 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9665 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9666 {"64", no_argument
, NULL
, OPTION_64
},
9668 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9669 {"x32", no_argument
, NULL
, OPTION_X32
},
9670 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
9672 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9673 {"march", required_argument
, NULL
, OPTION_MARCH
},
9674 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9675 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9676 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9677 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9678 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9679 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9680 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9681 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9682 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9683 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9684 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9685 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9686 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9687 # if defined (TE_PE) || defined (TE_PEP)
9688 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9690 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
9691 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
9692 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
9693 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9694 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
9695 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
9696 {NULL
, no_argument
, NULL
, 0}
9698 size_t md_longopts_size
= sizeof (md_longopts
);
9701 md_parse_option (int c
, const char *arg
)
9709 optimize_align_code
= 0;
9716 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9717 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9718 should be emitted or not. FIXME: Not implemented. */
9722 /* -V: SVR4 argument to print version ID. */
9724 print_version_id ();
9727 /* -k: Ignore for FreeBSD compatibility. */
9732 /* -s: On i386 Solaris, this tells the native assembler to use
9733 .stab instead of .stab.excl. We always use .stab anyhow. */
9736 case OPTION_MSHARED
:
9740 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9741 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9744 const char **list
, **l
;
9746 list
= bfd_target_list ();
9747 for (l
= list
; *l
!= NULL
; l
++)
9748 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9749 || strcmp (*l
, "coff-x86-64") == 0
9750 || strcmp (*l
, "pe-x86-64") == 0
9751 || strcmp (*l
, "pei-x86-64") == 0
9752 || strcmp (*l
, "mach-o-x86-64") == 0)
9754 default_arch
= "x86_64";
9758 as_fatal (_("no compiled in support for x86_64"));
9764 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9768 const char **list
, **l
;
9770 list
= bfd_target_list ();
9771 for (l
= list
; *l
!= NULL
; l
++)
9772 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9774 default_arch
= "x86_64:32";
9778 as_fatal (_("no compiled in support for 32bit x86_64"));
9782 as_fatal (_("32bit x86_64 is only supported for ELF"));
9787 default_arch
= "i386";
9791 #ifdef SVR4_COMMENT_CHARS
9796 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9798 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9802 i386_comment_chars
= n
;
9808 arch
= xstrdup (arg
);
9812 as_fatal (_("invalid -march= option: `%s'"), arg
);
9813 next
= strchr (arch
, '+');
9816 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9818 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9821 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9824 cpu_arch_name
= cpu_arch
[j
].name
;
9825 cpu_sub_arch_name
= NULL
;
9826 cpu_arch_flags
= cpu_arch
[j
].flags
;
9827 cpu_arch_isa
= cpu_arch
[j
].type
;
9828 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9829 if (!cpu_arch_tune_set
)
9831 cpu_arch_tune
= cpu_arch_isa
;
9832 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9836 else if (*cpu_arch
[j
].name
== '.'
9837 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9839 /* ISA entension. */
9840 i386_cpu_flags flags
;
9842 if (!cpu_arch
[j
].negated
)
9843 flags
= cpu_flags_or (cpu_arch_flags
,
9846 flags
= cpu_flags_and_not (cpu_arch_flags
,
9849 if (!valid_iamcu_cpu_flags (&flags
))
9850 as_fatal (_("`%s' isn't valid for Intel MCU"), arch
);
9851 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9853 if (cpu_sub_arch_name
)
9855 char *name
= cpu_sub_arch_name
;
9856 cpu_sub_arch_name
= concat (name
,
9858 (const char *) NULL
);
9862 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9863 cpu_arch_flags
= flags
;
9864 cpu_arch_isa_flags
= flags
;
9870 if (j
>= ARRAY_SIZE (cpu_arch
))
9871 as_fatal (_("invalid -march= option: `%s'"), arg
);
9875 while (next
!= NULL
);
9880 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9881 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9883 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9885 cpu_arch_tune_set
= 1;
9886 cpu_arch_tune
= cpu_arch
[j
].type
;
9887 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9891 if (j
>= ARRAY_SIZE (cpu_arch
))
9892 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9895 case OPTION_MMNEMONIC
:
9896 if (strcasecmp (arg
, "att") == 0)
9898 else if (strcasecmp (arg
, "intel") == 0)
9901 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9904 case OPTION_MSYNTAX
:
9905 if (strcasecmp (arg
, "att") == 0)
9907 else if (strcasecmp (arg
, "intel") == 0)
9910 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9913 case OPTION_MINDEX_REG
:
9914 allow_index_reg
= 1;
9917 case OPTION_MNAKED_REG
:
9918 allow_naked_reg
= 1;
9921 case OPTION_MOLD_GCC
:
9925 case OPTION_MSSE2AVX
:
9929 case OPTION_MSSE_CHECK
:
9930 if (strcasecmp (arg
, "error") == 0)
9931 sse_check
= check_error
;
9932 else if (strcasecmp (arg
, "warning") == 0)
9933 sse_check
= check_warning
;
9934 else if (strcasecmp (arg
, "none") == 0)
9935 sse_check
= check_none
;
9937 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9940 case OPTION_MOPERAND_CHECK
:
9941 if (strcasecmp (arg
, "error") == 0)
9942 operand_check
= check_error
;
9943 else if (strcasecmp (arg
, "warning") == 0)
9944 operand_check
= check_warning
;
9945 else if (strcasecmp (arg
, "none") == 0)
9946 operand_check
= check_none
;
9948 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9951 case OPTION_MAVXSCALAR
:
9952 if (strcasecmp (arg
, "128") == 0)
9954 else if (strcasecmp (arg
, "256") == 0)
9957 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9960 case OPTION_MADD_BND_PREFIX
:
9964 case OPTION_MEVEXLIG
:
9965 if (strcmp (arg
, "128") == 0)
9967 else if (strcmp (arg
, "256") == 0)
9969 else if (strcmp (arg
, "512") == 0)
9972 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9975 case OPTION_MEVEXRCIG
:
9976 if (strcmp (arg
, "rne") == 0)
9978 else if (strcmp (arg
, "rd") == 0)
9980 else if (strcmp (arg
, "ru") == 0)
9982 else if (strcmp (arg
, "rz") == 0)
9985 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
9988 case OPTION_MEVEXWIG
:
9989 if (strcmp (arg
, "0") == 0)
9991 else if (strcmp (arg
, "1") == 0)
9994 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9997 # if defined (TE_PE) || defined (TE_PEP)
9998 case OPTION_MBIG_OBJ
:
10003 case OPTION_MOMIT_LOCK_PREFIX
:
10004 if (strcasecmp (arg
, "yes") == 0)
10005 omit_lock_prefix
= 1;
10006 else if (strcasecmp (arg
, "no") == 0)
10007 omit_lock_prefix
= 0;
10009 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10012 case OPTION_MFENCE_AS_LOCK_ADD
:
10013 if (strcasecmp (arg
, "yes") == 0)
10015 else if (strcasecmp (arg
, "no") == 0)
10018 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10021 case OPTION_MRELAX_RELOCATIONS
:
10022 if (strcasecmp (arg
, "yes") == 0)
10023 generate_relax_relocations
= 1;
10024 else if (strcasecmp (arg
, "no") == 0)
10025 generate_relax_relocations
= 0;
10027 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10030 case OPTION_MAMD64
:
10031 cpu_arch_flags
.bitfield
.cpuamd64
= 1;
10032 cpu_arch_flags
.bitfield
.cpuintel64
= 0;
10033 cpu_arch_isa_flags
.bitfield
.cpuamd64
= 1;
10034 cpu_arch_isa_flags
.bitfield
.cpuintel64
= 0;
10037 case OPTION_MINTEL64
:
10038 cpu_arch_flags
.bitfield
.cpuamd64
= 0;
10039 cpu_arch_flags
.bitfield
.cpuintel64
= 1;
10040 cpu_arch_isa_flags
.bitfield
.cpuamd64
= 0;
10041 cpu_arch_isa_flags
.bitfield
.cpuintel64
= 1;
10050 #define MESSAGE_TEMPLATE \
10054 show_arch (FILE *stream
, int ext
, int check
)
10056 static char message
[] = MESSAGE_TEMPLATE
;
10057 char *start
= message
+ 27;
10059 int size
= sizeof (MESSAGE_TEMPLATE
);
10066 left
= size
- (start
- message
);
10067 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10069 /* Should it be skipped? */
10070 if (cpu_arch
[j
].skip
)
10073 name
= cpu_arch
[j
].name
;
10074 len
= cpu_arch
[j
].len
;
10077 /* It is an extension. Skip if we aren't asked to show it. */
10088 /* It is an processor. Skip if we show only extension. */
10091 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10093 /* It is an impossible processor - skip. */
10097 /* Reserve 2 spaces for ", " or ",\0" */
10100 /* Check if there is any room. */
10108 p
= mempcpy (p
, name
, len
);
10112 /* Output the current message now and start a new one. */
10115 fprintf (stream
, "%s\n", message
);
10117 left
= size
- (start
- message
) - len
- 2;
10119 gas_assert (left
>= 0);
10121 p
= mempcpy (p
, name
, len
);
10126 fprintf (stream
, "%s\n", message
);
10130 md_show_usage (FILE *stream
)
10132 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10133 fprintf (stream
, _("\
10135 -V print assembler version number\n\
10138 fprintf (stream
, _("\
10139 -n Do not optimize code alignment\n\
10140 -q quieten some warnings\n"));
10141 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10142 fprintf (stream
, _("\
10145 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10146 || defined (TE_PE) || defined (TE_PEP))
10147 fprintf (stream
, _("\
10148 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10150 #ifdef SVR4_COMMENT_CHARS
10151 fprintf (stream
, _("\
10152 --divide do not treat `/' as a comment character\n"));
10154 fprintf (stream
, _("\
10155 --divide ignored\n"));
10157 fprintf (stream
, _("\
10158 -march=CPU[,+EXTENSION...]\n\
10159 generate code for CPU and EXTENSION, CPU is one of:\n"));
10160 show_arch (stream
, 0, 1);
10161 fprintf (stream
, _("\
10162 EXTENSION is combination of:\n"));
10163 show_arch (stream
, 1, 0);
10164 fprintf (stream
, _("\
10165 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10166 show_arch (stream
, 0, 0);
10167 fprintf (stream
, _("\
10168 -msse2avx encode SSE instructions with VEX prefix\n"));
10169 fprintf (stream
, _("\
10170 -msse-check=[none|error|warning]\n\
10171 check SSE instructions\n"));
10172 fprintf (stream
, _("\
10173 -moperand-check=[none|error|warning]\n\
10174 check operand combinations for validity\n"));
10175 fprintf (stream
, _("\
10176 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10178 fprintf (stream
, _("\
10179 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10181 fprintf (stream
, _("\
10182 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10183 for EVEX.W bit ignored instructions\n"));
10184 fprintf (stream
, _("\
10185 -mevexrcig=[rne|rd|ru|rz]\n\
10186 encode EVEX instructions with specific EVEX.RC value\n\
10187 for SAE-only ignored instructions\n"));
10188 fprintf (stream
, _("\
10189 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10190 fprintf (stream
, _("\
10191 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10192 fprintf (stream
, _("\
10193 -mindex-reg support pseudo index registers\n"));
10194 fprintf (stream
, _("\
10195 -mnaked-reg don't require `%%' prefix for registers\n"));
10196 fprintf (stream
, _("\
10197 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10198 fprintf (stream
, _("\
10199 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10200 fprintf (stream
, _("\
10201 -mshared disable branch optimization for shared code\n"));
10202 # if defined (TE_PE) || defined (TE_PEP)
10203 fprintf (stream
, _("\
10204 -mbig-obj generate big object files\n"));
10206 fprintf (stream
, _("\
10207 -momit-lock-prefix=[no|yes]\n\
10208 strip all lock prefixes\n"));
10209 fprintf (stream
, _("\
10210 -mfence-as-lock-add=[no|yes]\n\
10211 encode lfence, mfence and sfence as\n\
10212 lock addl $0x0, (%%{re}sp)\n"));
10213 fprintf (stream
, _("\
10214 -mrelax-relocations=[no|yes]\n\
10215 generate relax relocations\n"));
10216 fprintf (stream
, _("\
10217 -mamd64 accept only AMD64 ISA\n"));
10218 fprintf (stream
, _("\
10219 -mintel64 accept only Intel64 ISA\n"));
10222 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10223 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10224 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10226 /* Pick the target format to use. */
10229 i386_target_format (void)
10231 if (!strncmp (default_arch
, "x86_64", 6))
10233 update_code_flag (CODE_64BIT
, 1);
10234 if (default_arch
[6] == '\0')
10235 x86_elf_abi
= X86_64_ABI
;
10237 x86_elf_abi
= X86_64_X32_ABI
;
10239 else if (!strcmp (default_arch
, "i386"))
10240 update_code_flag (CODE_32BIT
, 1);
10241 else if (!strcmp (default_arch
, "iamcu"))
10243 update_code_flag (CODE_32BIT
, 1);
10244 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10246 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10247 cpu_arch_name
= "iamcu";
10248 cpu_sub_arch_name
= NULL
;
10249 cpu_arch_flags
= iamcu_flags
;
10250 cpu_arch_isa
= PROCESSOR_IAMCU
;
10251 cpu_arch_isa_flags
= iamcu_flags
;
10252 if (!cpu_arch_tune_set
)
10254 cpu_arch_tune
= cpu_arch_isa
;
10255 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10259 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10263 as_fatal (_("unknown architecture"));
10265 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10266 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10267 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10268 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10270 switch (OUTPUT_FLAVOR
)
10272 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10273 case bfd_target_aout_flavour
:
10274 return AOUT_TARGET_FORMAT
;
10276 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10277 # if defined (TE_PE) || defined (TE_PEP)
10278 case bfd_target_coff_flavour
:
10279 if (flag_code
== CODE_64BIT
)
10280 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10283 # elif defined (TE_GO32)
10284 case bfd_target_coff_flavour
:
10285 return "coff-go32";
10287 case bfd_target_coff_flavour
:
10288 return "coff-i386";
10291 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10292 case bfd_target_elf_flavour
:
10294 const char *format
;
10296 switch (x86_elf_abi
)
10299 format
= ELF_TARGET_FORMAT
;
10302 use_rela_relocations
= 1;
10304 format
= ELF_TARGET_FORMAT64
;
10306 case X86_64_X32_ABI
:
10307 use_rela_relocations
= 1;
10309 disallow_64bit_reloc
= 1;
10310 format
= ELF_TARGET_FORMAT32
;
10313 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10315 if (x86_elf_abi
!= X86_64_ABI
)
10316 as_fatal (_("Intel L1OM is 64bit only"));
10317 return ELF_TARGET_L1OM_FORMAT
;
10319 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10321 if (x86_elf_abi
!= X86_64_ABI
)
10322 as_fatal (_("Intel K1OM is 64bit only"));
10323 return ELF_TARGET_K1OM_FORMAT
;
10325 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10327 if (x86_elf_abi
!= I386_ABI
)
10328 as_fatal (_("Intel MCU is 32bit only"));
10329 return ELF_TARGET_IAMCU_FORMAT
;
10335 #if defined (OBJ_MACH_O)
10336 case bfd_target_mach_o_flavour
:
10337 if (flag_code
== CODE_64BIT
)
10339 use_rela_relocations
= 1;
10341 return "mach-o-x86-64";
10344 return "mach-o-i386";
10352 #endif /* OBJ_MAYBE_ more than one */
10355 md_undefined_symbol (char *name
)
10357 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10358 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10359 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10360 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10364 if (symbol_find (name
))
10365 as_bad (_("GOT already in symbol table"));
10366 GOT_symbol
= symbol_new (name
, undefined_section
,
10367 (valueT
) 0, &zero_address_frag
);
10374 /* Round up a section size to the appropriate boundary. */
10377 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10379 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10380 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10382 /* For a.out, force the section size to be aligned. If we don't do
10383 this, BFD will align it for us, but it will not write out the
10384 final bytes of the section. This may be a bug in BFD, but it is
10385 easier to fix it here since that is how the other a.out targets
10389 align
= bfd_get_section_alignment (stdoutput
, segment
);
10390 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
10397 /* On the i386, PC-relative offsets are relative to the start of the
10398 next instruction. That is, the address of the offset, plus its
10399 size, since the offset is always the last part of the insn. */
10402 md_pcrel_from (fixS
*fixP
)
10404 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10410 s_bss (int ignore ATTRIBUTE_UNUSED
)
10414 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10416 obj_elf_section_change_hook ();
10418 temp
= get_absolute_expression ();
10419 subseg_set (bss_section
, (subsegT
) temp
);
10420 demand_empty_rest_of_line ();
10426 i386_validate_fix (fixS
*fixp
)
10428 if (fixp
->fx_subsy
)
10430 if (fixp
->fx_subsy
== GOT_symbol
)
10432 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10436 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10437 if (fixp
->fx_tcbit2
)
10438 fixp
->fx_r_type
= (fixp
->fx_tcbit
10439 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10440 : BFD_RELOC_X86_64_GOTPCRELX
);
10443 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10448 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10450 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10452 fixp
->fx_subsy
= 0;
10455 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10456 else if (!object_64bit
)
10458 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
10459 && fixp
->fx_tcbit2
)
10460 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
10466 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10469 bfd_reloc_code_real_type code
;
10471 switch (fixp
->fx_r_type
)
10473 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10474 case BFD_RELOC_SIZE32
:
10475 case BFD_RELOC_SIZE64
:
10476 if (S_IS_DEFINED (fixp
->fx_addsy
)
10477 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10479 /* Resolve size relocation against local symbol to size of
10480 the symbol plus addend. */
10481 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10482 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10483 && !fits_in_unsigned_long (value
))
10484 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10485 _("symbol size computation overflow"));
10486 fixp
->fx_addsy
= NULL
;
10487 fixp
->fx_subsy
= NULL
;
10488 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10493 case BFD_RELOC_X86_64_PLT32
:
10494 case BFD_RELOC_X86_64_GOT32
:
10495 case BFD_RELOC_X86_64_GOTPCREL
:
10496 case BFD_RELOC_X86_64_GOTPCRELX
:
10497 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10498 case BFD_RELOC_386_PLT32
:
10499 case BFD_RELOC_386_GOT32
:
10500 case BFD_RELOC_386_GOT32X
:
10501 case BFD_RELOC_386_GOTOFF
:
10502 case BFD_RELOC_386_GOTPC
:
10503 case BFD_RELOC_386_TLS_GD
:
10504 case BFD_RELOC_386_TLS_LDM
:
10505 case BFD_RELOC_386_TLS_LDO_32
:
10506 case BFD_RELOC_386_TLS_IE_32
:
10507 case BFD_RELOC_386_TLS_IE
:
10508 case BFD_RELOC_386_TLS_GOTIE
:
10509 case BFD_RELOC_386_TLS_LE_32
:
10510 case BFD_RELOC_386_TLS_LE
:
10511 case BFD_RELOC_386_TLS_GOTDESC
:
10512 case BFD_RELOC_386_TLS_DESC_CALL
:
10513 case BFD_RELOC_X86_64_TLSGD
:
10514 case BFD_RELOC_X86_64_TLSLD
:
10515 case BFD_RELOC_X86_64_DTPOFF32
:
10516 case BFD_RELOC_X86_64_DTPOFF64
:
10517 case BFD_RELOC_X86_64_GOTTPOFF
:
10518 case BFD_RELOC_X86_64_TPOFF32
:
10519 case BFD_RELOC_X86_64_TPOFF64
:
10520 case BFD_RELOC_X86_64_GOTOFF64
:
10521 case BFD_RELOC_X86_64_GOTPC32
:
10522 case BFD_RELOC_X86_64_GOT64
:
10523 case BFD_RELOC_X86_64_GOTPCREL64
:
10524 case BFD_RELOC_X86_64_GOTPC64
:
10525 case BFD_RELOC_X86_64_GOTPLT64
:
10526 case BFD_RELOC_X86_64_PLTOFF64
:
10527 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10528 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10529 case BFD_RELOC_RVA
:
10530 case BFD_RELOC_VTABLE_ENTRY
:
10531 case BFD_RELOC_VTABLE_INHERIT
:
10533 case BFD_RELOC_32_SECREL
:
10535 code
= fixp
->fx_r_type
;
10537 case BFD_RELOC_X86_64_32S
:
10538 if (!fixp
->fx_pcrel
)
10540 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10541 code
= fixp
->fx_r_type
;
10545 if (fixp
->fx_pcrel
)
10547 switch (fixp
->fx_size
)
10550 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10551 _("can not do %d byte pc-relative relocation"),
10553 code
= BFD_RELOC_32_PCREL
;
10555 case 1: code
= BFD_RELOC_8_PCREL
; break;
10556 case 2: code
= BFD_RELOC_16_PCREL
; break;
10557 case 4: code
= BFD_RELOC_32_PCREL
; break;
10559 case 8: code
= BFD_RELOC_64_PCREL
; break;
10565 switch (fixp
->fx_size
)
10568 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10569 _("can not do %d byte relocation"),
10571 code
= BFD_RELOC_32
;
10573 case 1: code
= BFD_RELOC_8
; break;
10574 case 2: code
= BFD_RELOC_16
; break;
10575 case 4: code
= BFD_RELOC_32
; break;
10577 case 8: code
= BFD_RELOC_64
; break;
10584 if ((code
== BFD_RELOC_32
10585 || code
== BFD_RELOC_32_PCREL
10586 || code
== BFD_RELOC_X86_64_32S
)
10588 && fixp
->fx_addsy
== GOT_symbol
)
10591 code
= BFD_RELOC_386_GOTPC
;
10593 code
= BFD_RELOC_X86_64_GOTPC32
;
10595 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10597 && fixp
->fx_addsy
== GOT_symbol
)
10599 code
= BFD_RELOC_X86_64_GOTPC64
;
10602 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10603 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10604 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10606 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10608 if (!use_rela_relocations
)
10610 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10611 vtable entry to be used in the relocation's section offset. */
10612 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10613 rel
->address
= fixp
->fx_offset
;
10614 #if defined (OBJ_COFF) && defined (TE_PE)
10615 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10616 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10621 /* Use the rela in 64bit mode. */
10624 if (disallow_64bit_reloc
)
10627 case BFD_RELOC_X86_64_DTPOFF64
:
10628 case BFD_RELOC_X86_64_TPOFF64
:
10629 case BFD_RELOC_64_PCREL
:
10630 case BFD_RELOC_X86_64_GOTOFF64
:
10631 case BFD_RELOC_X86_64_GOT64
:
10632 case BFD_RELOC_X86_64_GOTPCREL64
:
10633 case BFD_RELOC_X86_64_GOTPC64
:
10634 case BFD_RELOC_X86_64_GOTPLT64
:
10635 case BFD_RELOC_X86_64_PLTOFF64
:
10636 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10637 _("cannot represent relocation type %s in x32 mode"),
10638 bfd_get_reloc_code_name (code
));
10644 if (!fixp
->fx_pcrel
)
10645 rel
->addend
= fixp
->fx_offset
;
10649 case BFD_RELOC_X86_64_PLT32
:
10650 case BFD_RELOC_X86_64_GOT32
:
10651 case BFD_RELOC_X86_64_GOTPCREL
:
10652 case BFD_RELOC_X86_64_GOTPCRELX
:
10653 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10654 case BFD_RELOC_X86_64_TLSGD
:
10655 case BFD_RELOC_X86_64_TLSLD
:
10656 case BFD_RELOC_X86_64_GOTTPOFF
:
10657 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10658 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10659 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10662 rel
->addend
= (section
->vma
10664 + fixp
->fx_addnumber
10665 + md_pcrel_from (fixp
));
10670 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10671 if (rel
->howto
== NULL
)
10673 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10674 _("cannot represent relocation type %s"),
10675 bfd_get_reloc_code_name (code
));
10676 /* Set howto to a garbage value so that we can keep going. */
10677 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10678 gas_assert (rel
->howto
!= NULL
);
10684 #include "tc-i386-intel.c"
10687 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10689 int saved_naked_reg
;
10690 char saved_register_dot
;
10692 saved_naked_reg
= allow_naked_reg
;
10693 allow_naked_reg
= 1;
10694 saved_register_dot
= register_chars
['.'];
10695 register_chars
['.'] = '.';
10696 allow_pseudo_reg
= 1;
10697 expression_and_evaluate (exp
);
10698 allow_pseudo_reg
= 0;
10699 register_chars
['.'] = saved_register_dot
;
10700 allow_naked_reg
= saved_naked_reg
;
10702 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10704 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10706 exp
->X_op
= O_constant
;
10707 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10708 .dw2_regnum
[flag_code
>> 1];
10711 exp
->X_op
= O_illegal
;
10716 tc_x86_frame_initial_instructions (void)
10718 static unsigned int sp_regno
[2];
10720 if (!sp_regno
[flag_code
>> 1])
10722 char *saved_input
= input_line_pointer
;
10723 char sp
[][4] = {"esp", "rsp"};
10726 input_line_pointer
= sp
[flag_code
>> 1];
10727 tc_x86_parse_to_dw2regnum (&exp
);
10728 gas_assert (exp
.X_op
== O_constant
);
10729 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10730 input_line_pointer
= saved_input
;
10733 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10734 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10738 x86_dwarf2_addr_size (void)
10740 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10741 if (x86_elf_abi
== X86_64_X32_ABI
)
10744 return bfd_arch_bits_per_address (stdoutput
) / 8;
10748 i386_elf_section_type (const char *str
, size_t len
)
10750 if (flag_code
== CODE_64BIT
10751 && len
== sizeof ("unwind") - 1
10752 && strncmp (str
, "unwind", 6) == 0)
10753 return SHT_X86_64_UNWIND
;
10760 i386_solaris_fix_up_eh_frame (segT sec
)
10762 if (flag_code
== CODE_64BIT
)
10763 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10769 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10773 exp
.X_op
= O_secrel
;
10774 exp
.X_add_symbol
= symbol
;
10775 exp
.X_add_number
= 0;
10776 emit_expr (&exp
, size
);
10780 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10781 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10784 x86_64_section_letter (int letter
, char **ptr_msg
)
10786 if (flag_code
== CODE_64BIT
)
10789 return SHF_X86_64_LARGE
;
10791 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10794 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10799 x86_64_section_word (char *str
, size_t len
)
10801 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10802 return SHF_X86_64_LARGE
;
10808 handle_large_common (int small ATTRIBUTE_UNUSED
)
10810 if (flag_code
!= CODE_64BIT
)
10812 s_comm_internal (0, elf_common_parse
);
10813 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10817 static segT lbss_section
;
10818 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10819 asection
*saved_bss_section
= bss_section
;
10821 if (lbss_section
== NULL
)
10823 flagword applicable
;
10824 segT seg
= now_seg
;
10825 subsegT subseg
= now_subseg
;
10827 /* The .lbss section is for local .largecomm symbols. */
10828 lbss_section
= subseg_new (".lbss", 0);
10829 applicable
= bfd_applicable_section_flags (stdoutput
);
10830 bfd_set_section_flags (stdoutput
, lbss_section
,
10831 applicable
& SEC_ALLOC
);
10832 seg_info (lbss_section
)->bss
= 1;
10834 subseg_set (seg
, subseg
);
10837 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10838 bss_section
= lbss_section
;
10840 s_comm_internal (0, elf_common_parse
);
10842 elf_com_section_ptr
= saved_com_section_ptr
;
10843 bss_section
= saved_bss_section
;
10846 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */