1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
33 #include "dwarf2dbg.h"
34 #include "opcode/i386.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
44 #ifndef SCALE1_WHEN_NO_INDEX
45 /* Specifying a scale factor besides 1 when there is no index is
46 futile. eg. `mov (%ebx,2),%al' does exactly the same as
47 `mov (%ebx),%al'. To slavishly follow what the programmer
48 specified, set SCALE1_WHEN_NO_INDEX to 0. */
49 #define SCALE1_WHEN_NO_INDEX 1
55 static unsigned int mode_from_disp_size
PARAMS ((unsigned int));
56 static int fits_in_signed_byte
PARAMS ((offsetT
));
57 static int fits_in_unsigned_byte
PARAMS ((offsetT
));
58 static int fits_in_unsigned_word
PARAMS ((offsetT
));
59 static int fits_in_signed_word
PARAMS ((offsetT
));
60 static int fits_in_unsigned_long
PARAMS ((offsetT
));
61 static int fits_in_signed_long
PARAMS ((offsetT
));
62 static int smallest_imm_type
PARAMS ((offsetT
));
63 static offsetT offset_in_range
PARAMS ((offsetT
, int));
64 static int add_prefix
PARAMS ((unsigned int));
65 static void set_code_flag
PARAMS ((int));
66 static void set_16bit_gcc_code_flag
PARAMS ((int));
67 static void set_intel_syntax
PARAMS ((int));
68 static void set_cpu_arch
PARAMS ((int));
71 static bfd_reloc_code_real_type reloc
72 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
73 #define RELOC_ENUM enum bfd_reloc_code_real
75 #define RELOC_ENUM int
79 #define DEFAULT_ARCH "i386"
81 static char *default_arch
= DEFAULT_ARCH
;
83 /* 'md_assemble ()' gathers together information and puts it into a
90 const reg_entry
*regs
;
95 /* TM holds the template for the insn were currently assembling. */
98 /* SUFFIX holds the instruction mnemonic suffix if given.
99 (e.g. 'l' for 'movl') */
102 /* OPERANDS gives the number of given operands. */
103 unsigned int operands
;
105 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
106 of given register, displacement, memory operands and immediate
108 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
110 /* TYPES [i] is the type (see above #defines) which tells us how to
111 use OP[i] for the corresponding operand. */
112 unsigned int types
[MAX_OPERANDS
];
114 /* Displacement expression, immediate expression, or register for each
116 union i386_op op
[MAX_OPERANDS
];
118 /* Flags for operands. */
119 unsigned int flags
[MAX_OPERANDS
];
120 #define Operand_PCrel 1
122 /* Relocation type for operand */
123 RELOC_ENUM reloc
[MAX_OPERANDS
];
125 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
126 the base index byte below. */
127 const reg_entry
*base_reg
;
128 const reg_entry
*index_reg
;
129 unsigned int log2_scale_factor
;
131 /* SEG gives the seg_entries of this insn. They are zero unless
132 explicit segment overrides are given. */
133 const seg_entry
*seg
[2];
135 /* PREFIX holds all the given prefix opcodes (usually null).
136 PREFIXES is the number of prefix opcodes. */
137 unsigned int prefixes
;
138 unsigned char prefix
[MAX_PREFIXES
];
140 /* RM and SIB are the modrm byte and the sib byte where the
141 addressing modes of this insn are encoded. */
148 typedef struct _i386_insn i386_insn
;
150 /* List of chars besides those in app.c:symbol_chars that can start an
151 operand. Used to prevent the scrubber eating vital white-space. */
153 const char extra_symbol_chars
[] = "*%-(@";
155 const char extra_symbol_chars
[] = "*%-(";
158 /* This array holds the chars that always start a comment. If the
159 pre-processor is disabled, these aren't very useful. */
160 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
161 /* Putting '/' here makes it impossible to use the divide operator.
162 However, we need it for compatibility with SVR4 systems. */
163 const char comment_chars
[] = "#/";
164 #define PREFIX_SEPARATOR '\\'
166 const char comment_chars
[] = "#";
167 #define PREFIX_SEPARATOR '/'
170 /* This array holds the chars that only start a comment at the beginning of
171 a line. If the line seems to have the form '# 123 filename'
172 .line and .file directives will appear in the pre-processed output.
173 Note that input_file.c hand checks for '#' at the beginning of the
174 first line of the input file. This is because the compiler outputs
175 #NO_APP at the beginning of its output.
176 Also note that comments started like this one will always work if
177 '/' isn't otherwise defined. */
178 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
179 const char line_comment_chars
[] = "";
181 const char line_comment_chars
[] = "/";
184 const char line_separator_chars
[] = ";";
186 /* Chars that can be used to separate mant from exp in floating point
188 const char EXP_CHARS
[] = "eE";
190 /* Chars that mean this number is a floating point constant
193 const char FLT_CHARS
[] = "fFdDxX";
195 /* Tables for lexical analysis. */
196 static char mnemonic_chars
[256];
197 static char register_chars
[256];
198 static char operand_chars
[256];
199 static char identifier_chars
[256];
200 static char digit_chars
[256];
202 /* Lexical macros. */
203 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
204 #define is_operand_char(x) (operand_chars[(unsigned char) x])
205 #define is_register_char(x) (register_chars[(unsigned char) x])
206 #define is_space_char(x) ((x) == ' ')
207 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
208 #define is_digit_char(x) (digit_chars[(unsigned char) x])
210 /* All non-digit non-letter charcters that may occur in an operand. */
211 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
213 /* md_assemble() always leaves the strings it's passed unaltered. To
214 effect this we maintain a stack of saved characters that we've smashed
215 with '\0's (indicating end of strings for various sub-fields of the
216 assembler instruction). */
217 static char save_stack
[32];
218 static char *save_stack_p
;
219 #define END_STRING_AND_SAVE(s) \
220 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
221 #define RESTORE_END_STRING(s) \
222 do { *(s) = *--save_stack_p; } while (0)
224 /* The instruction we're assembling. */
227 /* Possible templates for current insn. */
228 static const templates
*current_templates
;
230 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
231 static expressionS disp_expressions
[2], im_expressions
[2];
233 /* Current operand we are working on. */
234 static int this_operand
;
236 /* We support four different modes. FLAG_CODE variable is used to distinguish
243 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
245 static enum flag_code flag_code
;
246 static int use_rela_relocations
= 0;
248 /* The names used to print error messages. */
249 static const char *flag_code_names
[] =
256 /* 1 for intel syntax,
258 static int intel_syntax
= 0;
260 /* 1 if register prefix % not required. */
261 static int allow_naked_reg
= 0;
263 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
264 leave, push, and pop instructions so that gcc has the same stack
265 frame as in 32 bit mode. */
266 static char stackop_size
= '\0';
268 /* Non-zero to quieten some warnings. */
269 static int quiet_warnings
= 0;
272 static const char *cpu_arch_name
= NULL
;
274 /* CPU feature flags. */
275 static unsigned int cpu_arch_flags
= CpuUnknownFlags
|CpuNo64
;
277 /* If set, conditional jumps are not automatically promoted to handle
278 larger than a byte offset. */
279 static unsigned int no_cond_jump_promotion
= 0;
281 /* Interface to relax_segment.
282 There are 3 major relax states for 386 jump insns because the
283 different types of jumps add different sizes to frags when we're
284 figuring out what sort of jump to choose to reach a given label. */
287 #define UNCOND_JUMP 0
289 #define COND_JUMP86 2
294 #define SMALL16 (SMALL|CODE16)
296 #define BIG16 (BIG|CODE16)
300 #define INLINE __inline__
306 #define ENCODE_RELAX_STATE(type, size) \
307 ((relax_substateT) (((type) << 2) | (size)))
308 #define TYPE_FROM_RELAX_STATE(s) \
310 #define DISP_SIZE_FROM_RELAX_STATE(s) \
311 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
313 /* This table is used by relax_frag to promote short jumps to long
314 ones where necessary. SMALL (short) jumps may be promoted to BIG
315 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
316 don't allow a short jump in a 32 bit code segment to be promoted to
317 a 16 bit offset jump because it's slower (requires data size
318 prefix), and doesn't work, unless the destination is in the bottom
319 64k of the code segment (The top 16 bits of eip are zeroed). */
321 const relax_typeS md_relax_table
[] =
324 1) most positive reach of this state,
325 2) most negative reach of this state,
326 3) how many bytes this mode will have in the variable part of the frag
327 4) which index into the table to try if we can't fit into this one. */
329 /* UNCOND_JUMP states. */
330 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
331 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
332 /* dword jmp adds 4 bytes to frag:
333 0 extra opcode bytes, 4 displacement bytes. */
335 /* word jmp adds 2 byte2 to frag:
336 0 extra opcode bytes, 2 displacement bytes. */
339 /* COND_JUMP states. */
340 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
341 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
342 /* dword conditionals adds 5 bytes to frag:
343 1 extra opcode byte, 4 displacement bytes. */
345 /* word conditionals add 3 bytes to frag:
346 1 extra opcode byte, 2 displacement bytes. */
349 /* COND_JUMP86 states. */
350 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
351 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
352 /* dword conditionals adds 5 bytes to frag:
353 1 extra opcode byte, 4 displacement bytes. */
355 /* word conditionals add 4 bytes to frag:
356 1 displacement byte and a 3 byte long branch insn. */
360 static const arch_entry cpu_arch
[] = {
362 {"i186", Cpu086
|Cpu186
},
363 {"i286", Cpu086
|Cpu186
|Cpu286
},
364 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
365 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
366 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
367 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
368 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
369 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
370 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
371 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
372 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
373 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
378 i386_align_code (fragP
, count
)
382 /* Various efficient no-op patterns for aligning code labels.
383 Note: Don't try to assemble the instructions in the comments.
384 0L and 0w are not legal. */
385 static const char f32_1
[] =
387 static const char f32_2
[] =
388 {0x89,0xf6}; /* movl %esi,%esi */
389 static const char f32_3
[] =
390 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
391 static const char f32_4
[] =
392 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
393 static const char f32_5
[] =
395 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
396 static const char f32_6
[] =
397 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
398 static const char f32_7
[] =
399 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
400 static const char f32_8
[] =
402 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
403 static const char f32_9
[] =
404 {0x89,0xf6, /* movl %esi,%esi */
405 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
406 static const char f32_10
[] =
407 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
408 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
409 static const char f32_11
[] =
410 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
411 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
412 static const char f32_12
[] =
413 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
414 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
415 static const char f32_13
[] =
416 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
417 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
418 static const char f32_14
[] =
419 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
420 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
421 static const char f32_15
[] =
422 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
423 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
424 static const char f16_3
[] =
425 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
426 static const char f16_4
[] =
427 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
428 static const char f16_5
[] =
430 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
431 static const char f16_6
[] =
432 {0x89,0xf6, /* mov %si,%si */
433 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
434 static const char f16_7
[] =
435 {0x8d,0x74,0x00, /* lea 0(%si),%si */
436 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
437 static const char f16_8
[] =
438 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
439 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
440 static const char *const f32_patt
[] = {
441 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
442 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
444 static const char *const f16_patt
[] = {
445 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
446 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
449 /* ??? We can't use these fillers for x86_64, since they often kills the
450 upper halves. Solve later. */
451 if (flag_code
== CODE_64BIT
)
454 if (count
> 0 && count
<= 15)
456 if (flag_code
== CODE_16BIT
)
458 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
459 f16_patt
[count
- 1], count
);
461 /* Adjust jump offset. */
462 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
465 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
466 f32_patt
[count
- 1], count
);
467 fragP
->fr_var
= count
;
471 static char *output_invalid
PARAMS ((int c
));
472 static int i386_operand
PARAMS ((char *operand_string
));
473 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
474 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
478 static void s_bss
PARAMS ((int));
481 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
483 static INLINE
unsigned int
484 mode_from_disp_size (t
)
487 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
491 fits_in_signed_byte (num
)
494 return (num
>= -128) && (num
<= 127);
498 fits_in_unsigned_byte (num
)
501 return (num
& 0xff) == num
;
505 fits_in_unsigned_word (num
)
508 return (num
& 0xffff) == num
;
512 fits_in_signed_word (num
)
515 return (-32768 <= num
) && (num
<= 32767);
518 fits_in_signed_long (num
)
519 offsetT num ATTRIBUTE_UNUSED
;
524 return (!(((offsetT
) -1 << 31) & num
)
525 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
527 } /* fits_in_signed_long() */
529 fits_in_unsigned_long (num
)
530 offsetT num ATTRIBUTE_UNUSED
;
535 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
537 } /* fits_in_unsigned_long() */
540 smallest_imm_type (num
)
543 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
)
544 && !(cpu_arch_flags
& (CpuUnknown
)))
546 /* This code is disabled on the 486 because all the Imm1 forms
547 in the opcode table are slower on the i486. They're the
548 versions with the implicitly specified single-position
549 displacement, which has another syntax if you really want to
552 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
554 return (fits_in_signed_byte (num
)
555 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
556 : fits_in_unsigned_byte (num
)
557 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
558 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
559 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
560 : fits_in_signed_long (num
)
561 ? (Imm32
| Imm32S
| Imm64
)
562 : fits_in_unsigned_long (num
)
568 offset_in_range (val
, size
)
576 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
577 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
578 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
580 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
585 /* If BFD64, sign extend val. */
586 if (!use_rela_relocations
)
587 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
588 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
590 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
592 char buf1
[40], buf2
[40];
594 sprint_value (buf1
, val
);
595 sprint_value (buf2
, val
& mask
);
596 as_warn (_("%s shortened to %s"), buf1
, buf2
);
601 /* Returns 0 if attempting to add a prefix where one from the same
602 class already exists, 1 if non rep/repne added, 2 if rep/repne
611 if (prefix
>= 0x40 && prefix
< 0x50 && flag_code
== CODE_64BIT
)
619 case CS_PREFIX_OPCODE
:
620 case DS_PREFIX_OPCODE
:
621 case ES_PREFIX_OPCODE
:
622 case FS_PREFIX_OPCODE
:
623 case GS_PREFIX_OPCODE
:
624 case SS_PREFIX_OPCODE
:
628 case REPNE_PREFIX_OPCODE
:
629 case REPE_PREFIX_OPCODE
:
632 case LOCK_PREFIX_OPCODE
:
640 case ADDR_PREFIX_OPCODE
:
644 case DATA_PREFIX_OPCODE
:
651 as_bad (_("same type of prefix used twice"));
656 i
.prefix
[q
] = prefix
;
661 set_code_flag (value
)
665 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
666 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
667 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
669 as_bad (_("64bit mode not supported on this CPU."));
671 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
673 as_bad (_("32bit mode not supported on this CPU."));
679 set_16bit_gcc_code_flag (new_code_flag
)
682 flag_code
= new_code_flag
;
683 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
684 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
689 set_intel_syntax (syntax_flag
)
692 /* Find out if register prefixing is specified. */
693 int ask_naked_reg
= 0;
696 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
698 char *string
= input_line_pointer
;
699 int e
= get_symbol_end ();
701 if (strcmp (string
, "prefix") == 0)
703 else if (strcmp (string
, "noprefix") == 0)
706 as_bad (_("bad argument to syntax directive."));
707 *input_line_pointer
= e
;
709 demand_empty_rest_of_line ();
711 intel_syntax
= syntax_flag
;
713 if (ask_naked_reg
== 0)
716 allow_naked_reg
= (intel_syntax
717 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
719 /* Conservative default. */
724 allow_naked_reg
= (ask_naked_reg
< 0);
729 int dummy ATTRIBUTE_UNUSED
;
733 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
735 char *string
= input_line_pointer
;
736 int e
= get_symbol_end ();
739 for (i
= 0; cpu_arch
[i
].name
; i
++)
741 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
743 cpu_arch_name
= cpu_arch
[i
].name
;
744 cpu_arch_flags
= (cpu_arch
[i
].flags
745 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
749 if (!cpu_arch
[i
].name
)
750 as_bad (_("no such architecture: `%s'"), string
);
752 *input_line_pointer
= e
;
755 as_bad (_("missing cpu architecture"));
757 no_cond_jump_promotion
= 0;
758 if (*input_line_pointer
== ','
759 && ! is_end_of_line
[(unsigned char) input_line_pointer
[1]])
761 char *string
= ++input_line_pointer
;
762 int e
= get_symbol_end ();
764 if (strcmp (string
, "nojumps") == 0)
765 no_cond_jump_promotion
= 1;
766 else if (strcmp (string
, "jumps") == 0)
769 as_bad (_("no such architecture modifier: `%s'"), string
);
771 *input_line_pointer
= e
;
774 demand_empty_rest_of_line ();
777 const pseudo_typeS md_pseudo_table
[] =
779 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
780 {"align", s_align_bytes
, 0},
782 {"align", s_align_ptwo
, 0},
784 {"arch", set_cpu_arch
, 0},
788 {"ffloat", float_cons
, 'f'},
789 {"dfloat", float_cons
, 'd'},
790 {"tfloat", float_cons
, 'x'},
792 {"noopt", s_ignore
, 0},
793 {"optim", s_ignore
, 0},
794 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
795 {"code16", set_code_flag
, CODE_16BIT
},
796 {"code32", set_code_flag
, CODE_32BIT
},
797 {"code64", set_code_flag
, CODE_64BIT
},
798 {"intel_syntax", set_intel_syntax
, 1},
799 {"att_syntax", set_intel_syntax
, 0},
800 {"file", dwarf2_directive_file
, 0},
801 {"loc", dwarf2_directive_loc
, 0},
805 /* For interface with expression (). */
806 extern char *input_line_pointer
;
808 /* Hash table for instruction mnemonic lookup. */
809 static struct hash_control
*op_hash
;
811 /* Hash table for register lookup. */
812 static struct hash_control
*reg_hash
;
818 if (!strcmp (default_arch
, "x86_64"))
819 return bfd_mach_x86_64
;
820 else if (!strcmp (default_arch
, "i386"))
821 return bfd_mach_i386_i386
;
823 as_fatal (_("Unknown architecture"));
830 const char *hash_err
;
832 /* Initialize op_hash hash table. */
833 op_hash
= hash_new ();
836 register const template *optab
;
837 register templates
*core_optab
;
839 /* Setup for loop. */
841 core_optab
= (templates
*) xmalloc (sizeof (templates
));
842 core_optab
->start
= optab
;
847 if (optab
->name
== NULL
848 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
850 /* different name --> ship out current template list;
851 add to hash table; & begin anew. */
852 core_optab
->end
= optab
;
853 hash_err
= hash_insert (op_hash
,
858 as_fatal (_("Internal Error: Can't hash %s: %s"),
862 if (optab
->name
== NULL
)
864 core_optab
= (templates
*) xmalloc (sizeof (templates
));
865 core_optab
->start
= optab
;
870 /* Initialize reg_hash hash table. */
871 reg_hash
= hash_new ();
873 register const reg_entry
*regtab
;
875 for (regtab
= i386_regtab
;
876 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
879 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
881 as_fatal (_("Internal Error: Can't hash %s: %s"),
887 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
892 for (c
= 0; c
< 256; c
++)
897 mnemonic_chars
[c
] = c
;
898 register_chars
[c
] = c
;
899 operand_chars
[c
] = c
;
901 else if (islower (c
))
903 mnemonic_chars
[c
] = c
;
904 register_chars
[c
] = c
;
905 operand_chars
[c
] = c
;
907 else if (isupper (c
))
909 mnemonic_chars
[c
] = tolower (c
);
910 register_chars
[c
] = mnemonic_chars
[c
];
911 operand_chars
[c
] = c
;
914 if (isalpha (c
) || isdigit (c
))
915 identifier_chars
[c
] = c
;
918 identifier_chars
[c
] = c
;
919 operand_chars
[c
] = c
;
924 identifier_chars
['@'] = '@';
926 digit_chars
['-'] = '-';
927 identifier_chars
['_'] = '_';
928 identifier_chars
['.'] = '.';
930 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
931 operand_chars
[(unsigned char) *p
] = *p
;
934 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
935 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
937 record_alignment (text_section
, 2);
938 record_alignment (data_section
, 2);
939 record_alignment (bss_section
, 2);
945 i386_print_statistics (file
)
948 hash_print_statistics (file
, "i386 opcode", op_hash
);
949 hash_print_statistics (file
, "i386 register", reg_hash
);
954 /* Debugging routines for md_assemble. */
955 static void pi
PARAMS ((char *, i386_insn
*));
956 static void pte
PARAMS ((template *));
957 static void pt
PARAMS ((unsigned int));
958 static void pe
PARAMS ((expressionS
*));
959 static void ps
PARAMS ((symbolS
*));
968 fprintf (stdout
, "%s: template ", line
);
970 fprintf (stdout
, " address: base %s index %s scale %x\n",
971 x
->base_reg
? x
->base_reg
->reg_name
: "none",
972 x
->index_reg
? x
->index_reg
->reg_name
: "none",
973 x
->log2_scale_factor
);
974 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
975 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
976 fprintf (stdout
, " sib: base %x index %x scale %x\n",
977 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
978 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
979 x
->rex
.mode64
, x
->rex
.extX
, x
->rex
.extY
, x
->rex
.extZ
);
980 for (i
= 0; i
< x
->operands
; i
++)
982 fprintf (stdout
, " #%d: ", i
+ 1);
984 fprintf (stdout
, "\n");
986 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
987 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
988 if (x
->types
[i
] & Imm
)
990 if (x
->types
[i
] & Disp
)
1000 fprintf (stdout
, " %d operands ", t
->operands
);
1001 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1002 if (t
->extension_opcode
!= None
)
1003 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1004 if (t
->opcode_modifier
& D
)
1005 fprintf (stdout
, "D");
1006 if (t
->opcode_modifier
& W
)
1007 fprintf (stdout
, "W");
1008 fprintf (stdout
, "\n");
1009 for (i
= 0; i
< t
->operands
; i
++)
1011 fprintf (stdout
, " #%d type ", i
+ 1);
1012 pt (t
->operand_types
[i
]);
1013 fprintf (stdout
, "\n");
1021 fprintf (stdout
, " operation %d\n", e
->X_op
);
1022 fprintf (stdout
, " add_number %ld (%lx)\n",
1023 (long) e
->X_add_number
, (long) e
->X_add_number
);
1024 if (e
->X_add_symbol
)
1026 fprintf (stdout
, " add_symbol ");
1027 ps (e
->X_add_symbol
);
1028 fprintf (stdout
, "\n");
1032 fprintf (stdout
, " op_symbol ");
1033 ps (e
->X_op_symbol
);
1034 fprintf (stdout
, "\n");
1042 fprintf (stdout
, "%s type %s%s",
1044 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1045 segment_name (S_GET_SEGMENT (s
)));
1067 { BaseIndex
, "BaseIndex" },
1071 { Disp32S
, "d32s" },
1073 { InOutPortReg
, "InOutPortReg" },
1074 { ShiftCount
, "ShiftCount" },
1075 { Control
, "control reg" },
1076 { Test
, "test reg" },
1077 { Debug
, "debug reg" },
1078 { FloatReg
, "FReg" },
1079 { FloatAcc
, "FAcc" },
1083 { JumpAbsolute
, "Jump Absolute" },
1094 register struct type_name
*ty
;
1096 for (ty
= type_names
; ty
->mask
; ty
++)
1098 fprintf (stdout
, "%s, ", ty
->tname
);
1102 #endif /* DEBUG386 */
1105 tc_i386_force_relocation (fixp
)
1108 #ifdef BFD_ASSEMBLER
1109 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1110 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1115 return fixp
->fx_r_type
== 7;
1119 #ifdef BFD_ASSEMBLER
1121 static bfd_reloc_code_real_type
1122 reloc (size
, pcrel
, sign
, other
)
1126 bfd_reloc_code_real_type other
;
1128 if (other
!= NO_RELOC
)
1134 as_bad (_("There are no unsigned pc-relative relocations"));
1137 case 1: return BFD_RELOC_8_PCREL
;
1138 case 2: return BFD_RELOC_16_PCREL
;
1139 case 4: return BFD_RELOC_32_PCREL
;
1141 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1148 case 4: return BFD_RELOC_X86_64_32S
;
1153 case 1: return BFD_RELOC_8
;
1154 case 2: return BFD_RELOC_16
;
1155 case 4: return BFD_RELOC_32
;
1156 case 8: return BFD_RELOC_64
;
1158 as_bad (_("can not do %s %d byte relocation"),
1159 sign
? "signed" : "unsigned", size
);
1163 return BFD_RELOC_NONE
;
1166 /* Here we decide which fixups can be adjusted to make them relative to
1167 the beginning of the section instead of the symbol. Basically we need
1168 to make sure that the dynamic relocations are done correctly, so in
1169 some cases we force the original symbol to be used. */
1172 tc_i386_fix_adjustable (fixP
)
1175 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1176 /* Prevent all adjustments to global symbols, or else dynamic
1177 linking will not work correctly. */
1178 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1179 || S_IS_WEAK (fixP
->fx_addsy
))
1182 /* adjust_reloc_syms doesn't know about the GOT. */
1183 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1184 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1185 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1186 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1187 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1188 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1189 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1190 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1195 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1196 #define BFD_RELOC_16 0
1197 #define BFD_RELOC_32 0
1198 #define BFD_RELOC_16_PCREL 0
1199 #define BFD_RELOC_32_PCREL 0
1200 #define BFD_RELOC_386_PLT32 0
1201 #define BFD_RELOC_386_GOT32 0
1202 #define BFD_RELOC_386_GOTOFF 0
1203 #define BFD_RELOC_X86_64_PLT32 0
1204 #define BFD_RELOC_X86_64_GOT32 0
1205 #define BFD_RELOC_X86_64_GOTPCREL 0
1208 static int intel_float_operand
PARAMS ((char *mnemonic
));
1211 intel_float_operand (mnemonic
)
1214 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1217 if (mnemonic
[0] == 'f')
1223 /* This is the guts of the machine-dependent assembler. LINE points to a
1224 machine dependent instruction. This function is supposed to emit
1225 the frags/bytes it assembles to. */
1231 /* Points to template once we've found it. */
1234 /* Count the size of the instruction generated. Does not include
1235 variable part of jump insns before relax. */
1240 char mnemonic
[MAX_MNEM_SIZE
];
1242 /* Initialize globals. */
1243 memset (&i
, '\0', sizeof (i
));
1244 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1245 i
.reloc
[j
] = NO_RELOC
;
1246 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1247 memset (im_expressions
, '\0', sizeof (im_expressions
));
1248 save_stack_p
= save_stack
;
1250 /* First parse an instruction mnemonic & call i386_operand for the operands.
1251 We assume that the scrubber has arranged it so that line[0] is the valid
1252 start of a (possibly prefixed) mnemonic. */
1255 char *token_start
= l
;
1258 /* Non-zero if we found a prefix only acceptable with string insns. */
1259 const char *expecting_string_instruction
= NULL
;
1264 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1267 if (mnem_p
>= mnemonic
+ sizeof (mnemonic
))
1269 as_bad (_("no such instruction: `%s'"), token_start
);
1274 if (!is_space_char (*l
)
1275 && *l
!= END_OF_INSN
1276 && *l
!= PREFIX_SEPARATOR
)
1278 as_bad (_("invalid character %s in mnemonic"),
1279 output_invalid (*l
));
1282 if (token_start
== l
)
1284 if (*l
== PREFIX_SEPARATOR
)
1285 as_bad (_("expecting prefix; got nothing"));
1287 as_bad (_("expecting mnemonic; got nothing"));
1291 /* Look up instruction (or prefix) via hash table. */
1292 current_templates
= hash_find (op_hash
, mnemonic
);
1294 if (*l
!= END_OF_INSN
1295 && (! is_space_char (*l
) || l
[1] != END_OF_INSN
)
1296 && current_templates
1297 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1299 /* If we are in 16-bit mode, do not allow addr16 or data16.
1300 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1301 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1302 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1303 ^ (flag_code
== CODE_16BIT
)))
1305 as_bad (_("redundant %s prefix"),
1306 current_templates
->start
->name
);
1309 /* Add prefix, checking for repeated prefixes. */
1310 switch (add_prefix (current_templates
->start
->base_opcode
))
1315 expecting_string_instruction
= current_templates
->start
->name
;
1318 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1325 if (!current_templates
)
1327 /* See if we can get a match by trimming off a suffix. */
1330 case WORD_MNEM_SUFFIX
:
1331 case BYTE_MNEM_SUFFIX
:
1332 case QWORD_MNEM_SUFFIX
:
1333 i
.suffix
= mnem_p
[-1];
1335 current_templates
= hash_find (op_hash
, mnemonic
);
1337 case SHORT_MNEM_SUFFIX
:
1338 case LONG_MNEM_SUFFIX
:
1341 i
.suffix
= mnem_p
[-1];
1343 current_templates
= hash_find (op_hash
, mnemonic
);
1351 if (intel_float_operand (mnemonic
))
1352 i
.suffix
= SHORT_MNEM_SUFFIX
;
1354 i
.suffix
= LONG_MNEM_SUFFIX
;
1356 current_templates
= hash_find (op_hash
, mnemonic
);
1360 if (!current_templates
)
1362 as_bad (_("no such instruction: `%s'"), token_start
);
1367 /* Check if instruction is supported on specified architecture. */
1368 if (cpu_arch_flags
!= 0)
1370 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1371 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1373 as_warn (_("`%s' is not supported on `%s'"),
1374 current_templates
->start
->name
, cpu_arch_name
);
1376 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1378 as_warn (_("use .code16 to ensure correct addressing mode"));
1382 /* Check for rep/repne without a string instruction. */
1383 if (expecting_string_instruction
1384 && !(current_templates
->start
->opcode_modifier
& IsString
))
1386 as_bad (_("expecting string instruction after `%s'"),
1387 expecting_string_instruction
);
1391 /* There may be operands to parse. */
1392 if (*l
!= END_OF_INSN
)
1394 /* 1 if operand is pending after ','. */
1395 unsigned int expecting_operand
= 0;
1397 /* Non-zero if operand parens not balanced. */
1398 unsigned int paren_not_balanced
;
1402 /* Skip optional white space before operand. */
1403 if (is_space_char (*l
))
1405 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1407 as_bad (_("invalid character %s before operand %d"),
1408 output_invalid (*l
),
1412 token_start
= l
; /* after white space */
1413 paren_not_balanced
= 0;
1414 while (paren_not_balanced
|| *l
!= ',')
1416 if (*l
== END_OF_INSN
)
1418 if (paren_not_balanced
)
1421 as_bad (_("unbalanced parenthesis in operand %d."),
1424 as_bad (_("unbalanced brackets in operand %d."),
1429 break; /* we are done */
1431 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1433 as_bad (_("invalid character %s in operand %d"),
1434 output_invalid (*l
),
1441 ++paren_not_balanced
;
1443 --paren_not_balanced
;
1448 ++paren_not_balanced
;
1450 --paren_not_balanced
;
1454 if (l
!= token_start
)
1455 { /* Yes, we've read in another operand. */
1456 unsigned int operand_ok
;
1457 this_operand
= i
.operands
++;
1458 if (i
.operands
> MAX_OPERANDS
)
1460 as_bad (_("spurious operands; (%d operands/instruction max)"),
1464 /* Now parse operand adding info to 'i' as we go along. */
1465 END_STRING_AND_SAVE (l
);
1469 i386_intel_operand (token_start
,
1470 intel_float_operand (mnemonic
));
1472 operand_ok
= i386_operand (token_start
);
1474 RESTORE_END_STRING (l
);
1480 if (expecting_operand
)
1482 expecting_operand_after_comma
:
1483 as_bad (_("expecting operand after ','; got nothing"));
1488 as_bad (_("expecting operand before ','; got nothing"));
1493 /* Now *l must be either ',' or END_OF_INSN. */
1496 if (*++l
== END_OF_INSN
)
1498 /* Just skip it, if it's \n complain. */
1499 goto expecting_operand_after_comma
;
1501 expecting_operand
= 1;
1504 while (*l
!= END_OF_INSN
);
1508 /* Now we've parsed the mnemonic into a set of templates, and have the
1511 Next, we find a template that matches the given insn,
1512 making sure the overlap of the given operands types is consistent
1513 with the template operand types. */
1515 #define MATCH(overlap, given, template) \
1516 ((overlap & ~JumpAbsolute) \
1517 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1519 /* If given types r0 and r1 are registers they must be of the same type
1520 unless the expected operand type register overlap is null.
1521 Note that Acc in a template matches every size of reg. */
1522 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1523 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1524 ((g0) & Reg) == ((g1) & Reg) || \
1525 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1528 register unsigned int overlap0
, overlap1
;
1529 unsigned int overlap2
;
1530 unsigned int found_reverse_match
;
1533 /* All intel opcodes have reversed operands except for "bound" and
1534 "enter". We also don't reverse intersegment "jmp" and "call"
1535 instructions with 2 immediate operands so that the immediate segment
1536 precedes the offset, as it does when in AT&T mode. "enter" and the
1537 intersegment "jmp" and "call" instructions are the only ones that
1538 have two immediate operands. */
1539 if (intel_syntax
&& i
.operands
> 1
1540 && (strcmp (mnemonic
, "bound") != 0)
1541 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1543 union i386_op temp_op
;
1544 unsigned int temp_type
;
1545 RELOC_ENUM temp_reloc
;
1549 if (i
.operands
== 2)
1554 else if (i
.operands
== 3)
1559 temp_type
= i
.types
[xchg2
];
1560 i
.types
[xchg2
] = i
.types
[xchg1
];
1561 i
.types
[xchg1
] = temp_type
;
1562 temp_op
= i
.op
[xchg2
];
1563 i
.op
[xchg2
] = i
.op
[xchg1
];
1564 i
.op
[xchg1
] = temp_op
;
1565 temp_reloc
= i
.reloc
[xchg2
];
1566 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1567 i
.reloc
[xchg1
] = temp_reloc
;
1569 if (i
.mem_operands
== 2)
1571 const seg_entry
*temp_seg
;
1572 temp_seg
= i
.seg
[0];
1573 i
.seg
[0] = i
.seg
[1];
1574 i
.seg
[1] = temp_seg
;
1580 /* Try to ensure constant immediates are represented in the smallest
1582 char guess_suffix
= 0;
1586 guess_suffix
= i
.suffix
;
1587 else if (i
.reg_operands
)
1589 /* Figure out a suffix from the last register operand specified.
1590 We can't do this properly yet, ie. excluding InOutPortReg,
1591 but the following works for instructions with immediates.
1592 In any case, we can't set i.suffix yet. */
1593 for (op
= i
.operands
; --op
>= 0;)
1594 if (i
.types
[op
] & Reg
)
1596 if (i
.types
[op
] & Reg8
)
1597 guess_suffix
= BYTE_MNEM_SUFFIX
;
1598 else if (i
.types
[op
] & Reg16
)
1599 guess_suffix
= WORD_MNEM_SUFFIX
;
1600 else if (i
.types
[op
] & Reg32
)
1601 guess_suffix
= LONG_MNEM_SUFFIX
;
1602 else if (i
.types
[op
] & Reg64
)
1603 guess_suffix
= QWORD_MNEM_SUFFIX
;
1607 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1608 guess_suffix
= WORD_MNEM_SUFFIX
;
1610 for (op
= i
.operands
; --op
>= 0;)
1611 if (i
.types
[op
] & Imm
)
1613 switch (i
.op
[op
].imms
->X_op
)
1616 /* If a suffix is given, this operand may be shortened. */
1617 switch (guess_suffix
)
1619 case LONG_MNEM_SUFFIX
:
1620 i
.types
[op
] |= Imm32
| Imm64
;
1622 case WORD_MNEM_SUFFIX
:
1623 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1625 case BYTE_MNEM_SUFFIX
:
1626 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1630 /* If this operand is at most 16 bits, convert it
1631 to a signed 16 bit number before trying to see
1632 whether it will fit in an even smaller size.
1633 This allows a 16-bit operand such as $0xffe0 to
1634 be recognised as within Imm8S range. */
1635 if ((i
.types
[op
] & Imm16
)
1636 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
1638 i
.op
[op
].imms
->X_add_number
=
1639 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1641 if ((i
.types
[op
] & Imm32
)
1642 && (i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1)) == 0)
1644 i
.op
[op
].imms
->X_add_number
=
1645 (i
.op
[op
].imms
->X_add_number
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1647 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1648 /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */
1649 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1650 i
.types
[op
] &= ~Imm32
;
1655 /* Symbols and expressions. */
1657 /* Convert symbolic operand to proper sizes for matching. */
1658 switch (guess_suffix
)
1660 case QWORD_MNEM_SUFFIX
:
1661 i
.types
[op
] = Imm64
| Imm32S
;
1663 case LONG_MNEM_SUFFIX
:
1664 i
.types
[op
] = Imm32
| Imm64
;
1666 case WORD_MNEM_SUFFIX
:
1667 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1670 case BYTE_MNEM_SUFFIX
:
1671 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1680 if (i
.disp_operands
)
1682 /* Try to use the smallest displacement type too. */
1685 for (op
= i
.operands
; --op
>= 0;)
1686 if ((i
.types
[op
] & Disp
)
1687 && i
.op
[op
].disps
->X_op
== O_constant
)
1689 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1691 if (i
.types
[op
] & Disp16
)
1693 /* We know this operand is at most 16 bits, so
1694 convert to a signed 16 bit number before trying
1695 to see whether it will fit in an even smaller
1698 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1700 else if (i
.types
[op
] & Disp32
)
1702 /* We know this operand is at most 32 bits, so convert to a
1703 signed 32 bit number before trying to see whether it will
1704 fit in an even smaller size. */
1705 disp
&= (((offsetT
) 2 << 31) - 1);
1706 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1708 if (flag_code
== CODE_64BIT
)
1710 if (fits_in_signed_long (disp
))
1711 i
.types
[op
] |= Disp32S
;
1712 if (fits_in_unsigned_long (disp
))
1713 i
.types
[op
] |= Disp32
;
1715 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1716 && fits_in_signed_byte (disp
))
1717 i
.types
[op
] |= Disp8
;
1724 found_reverse_match
= 0;
1725 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1727 : (i
.suffix
== WORD_MNEM_SUFFIX
1729 : (i
.suffix
== SHORT_MNEM_SUFFIX
1731 : (i
.suffix
== LONG_MNEM_SUFFIX
1733 : (i
.suffix
== QWORD_MNEM_SUFFIX
1735 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
? No_xSuf
: 0))))));
1737 for (t
= current_templates
->start
;
1738 t
< current_templates
->end
;
1741 /* Must have right number of operands. */
1742 if (i
.operands
!= t
->operands
)
1745 /* Check the suffix, except for some instructions in intel mode. */
1746 if ((t
->opcode_modifier
& suffix_check
)
1748 && (t
->opcode_modifier
& IgnoreSize
))
1750 && t
->base_opcode
== 0xd9
1751 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1752 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1755 /* Do not verify operands when there are none. */
1756 else if (!t
->operands
)
1758 if (t
->cpu_flags
& ~cpu_arch_flags
)
1760 /* We've found a match; break out of loop. */
1764 overlap0
= i
.types
[0] & t
->operand_types
[0];
1765 switch (t
->operands
)
1768 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1773 overlap1
= i
.types
[1] & t
->operand_types
[1];
1774 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1775 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1776 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1777 t
->operand_types
[0],
1778 overlap1
, i
.types
[1],
1779 t
->operand_types
[1]))
1781 /* Check if other direction is valid ... */
1782 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1785 /* Try reversing direction of operands. */
1786 overlap0
= i
.types
[0] & t
->operand_types
[1];
1787 overlap1
= i
.types
[1] & t
->operand_types
[0];
1788 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1789 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1790 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1791 t
->operand_types
[1],
1792 overlap1
, i
.types
[1],
1793 t
->operand_types
[0]))
1795 /* Does not match either direction. */
1798 /* found_reverse_match holds which of D or FloatDR
1800 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1802 /* Found a forward 2 operand match here. */
1803 else if (t
->operands
== 3)
1805 /* Here we make use of the fact that there are no
1806 reverse match 3 operand instructions, and all 3
1807 operand instructions only need to be checked for
1808 register consistency between operands 2 and 3. */
1809 overlap2
= i
.types
[2] & t
->operand_types
[2];
1810 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1811 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1812 t
->operand_types
[1],
1813 overlap2
, i
.types
[2],
1814 t
->operand_types
[2]))
1818 /* Found either forward/reverse 2 or 3 operand match here:
1819 slip through to break. */
1821 if (t
->cpu_flags
& ~cpu_arch_flags
)
1823 found_reverse_match
= 0;
1826 /* We've found a match; break out of loop. */
1829 if (t
== current_templates
->end
)
1831 /* We found no match. */
1832 as_bad (_("suffix or operands invalid for `%s'"),
1833 current_templates
->start
->name
);
1837 if (!quiet_warnings
)
1840 && ((i
.types
[0] & JumpAbsolute
)
1841 != (t
->operand_types
[0] & JumpAbsolute
)))
1843 as_warn (_("indirect %s without `*'"), t
->name
);
1846 if ((t
->opcode_modifier
& (IsPrefix
|IgnoreSize
))
1847 == (IsPrefix
|IgnoreSize
))
1849 /* Warn them that a data or address size prefix doesn't
1850 affect assembly of the next line of code. */
1851 as_warn (_("stand-alone `%s' prefix"), t
->name
);
1855 /* Copy the template we found. */
1857 if (found_reverse_match
)
1859 /* If we found a reverse match we must alter the opcode
1860 direction bit. found_reverse_match holds bits to change
1861 (different for int & float insns). */
1863 i
.tm
.base_opcode
^= found_reverse_match
;
1865 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1866 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1869 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1872 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1873 i
.tm
.base_opcode
^= FloatR
;
1875 if (i
.tm
.opcode_modifier
& FWait
)
1876 if (! add_prefix (FWAIT_OPCODE
))
1879 /* Check string instruction segment overrides. */
1880 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1882 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1883 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1885 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1887 as_bad (_("`%s' operand %d must use `%%es' segment"),
1892 /* There's only ever one segment override allowed per instruction.
1893 This instruction possibly has a legal segment override on the
1894 second operand, so copy the segment to where non-string
1895 instructions store it, allowing common code. */
1896 i
.seg
[0] = i
.seg
[1];
1898 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1900 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1902 as_bad (_("`%s' operand %d must use `%%es' segment"),
1910 if (i
.reg_operands
&& flag_code
< CODE_64BIT
)
1913 for (op
= i
.operands
; --op
>= 0;)
1914 if ((i
.types
[op
] & Reg
)
1915 && (i
.op
[op
].regs
->reg_flags
& (RegRex64
|RegRex
)))
1917 as_bad (_("Extended register `%%%s' available only in 64bit mode."),
1918 i
.op
[op
].regs
->reg_name
);
1923 /* If matched instruction specifies an explicit instruction mnemonic
1925 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
1927 if (i
.tm
.opcode_modifier
& Size16
)
1928 i
.suffix
= WORD_MNEM_SUFFIX
;
1929 else if (i
.tm
.opcode_modifier
& Size64
)
1930 i
.suffix
= QWORD_MNEM_SUFFIX
;
1932 i
.suffix
= LONG_MNEM_SUFFIX
;
1934 else if (i
.reg_operands
)
1936 /* If there's no instruction mnemonic suffix we try to invent one
1937 based on register operands. */
1940 /* We take i.suffix from the last register operand specified,
1941 Destination register type is more significant than source
1944 for (op
= i
.operands
; --op
>= 0;)
1945 if ((i
.types
[op
] & Reg
)
1946 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
1948 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
1949 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
1950 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
1955 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
1958 for (op
= i
.operands
; --op
>= 0;)
1960 /* If this is an eight bit register, it's OK. If it's
1961 the 16 or 32 bit version of an eight bit register,
1962 we will just use the low portion, and that's OK too. */
1963 if (i
.types
[op
] & Reg8
)
1966 /* movzx and movsx should not generate this warning. */
1968 && (i
.tm
.base_opcode
== 0xfb7
1969 || i
.tm
.base_opcode
== 0xfb6
1970 || i
.tm
.base_opcode
== 0x63
1971 || i
.tm
.base_opcode
== 0xfbe
1972 || i
.tm
.base_opcode
== 0xfbf))
1975 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
1977 /* Check that the template allows eight bit regs
1978 This kills insns such as `orb $1,%edx', which
1979 maybe should be allowed. */
1980 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
1984 /* Prohibit these changes in the 64bit mode, since
1985 the lowering is more complicated. */
1986 if (flag_code
== CODE_64BIT
1987 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1988 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1989 i
.op
[op
].regs
->reg_name
,
1991 #if REGISTER_WARNINGS
1993 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1994 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1996 + (i
.types
[op
] & Reg16
1997 ? REGNAM_AL
- REGNAM_AX
1998 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
1999 i
.op
[op
].regs
->reg_name
,
2004 /* Any other register is bad. */
2005 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2007 | Control
| Debug
| Test
2008 | FloatReg
| FloatAcc
))
2010 as_bad (_("`%%%s' not allowed with `%s%c'"),
2011 i
.op
[op
].regs
->reg_name
,
2018 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2022 for (op
= i
.operands
; --op
>= 0;)
2023 /* Reject eight bit registers, except where the template
2024 requires them. (eg. movzb) */
2025 if ((i
.types
[op
] & Reg8
) != 0
2026 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2028 as_bad (_("`%%%s' not allowed with `%s%c'"),
2029 i
.op
[op
].regs
->reg_name
,
2034 /* Warn if the e prefix on a general reg is missing. */
2035 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2036 && (i
.types
[op
] & Reg16
) != 0
2037 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2039 /* Prohibit these changes in the 64bit mode, since
2040 the lowering is more complicated. */
2041 if (flag_code
== CODE_64BIT
)
2042 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2043 i
.op
[op
].regs
->reg_name
,
2045 #if REGISTER_WARNINGS
2047 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2048 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2049 i
.op
[op
].regs
->reg_name
,
2053 /* Warn if the r prefix on a general reg is missing. */
2054 else if ((i
.types
[op
] & Reg64
) != 0
2055 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2057 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2058 i
.op
[op
].regs
->reg_name
,
2062 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2066 for (op
= i
.operands
; --op
>= 0; )
2067 /* Reject eight bit registers, except where the template
2068 requires them. (eg. movzb) */
2069 if ((i
.types
[op
] & Reg8
) != 0
2070 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2072 as_bad (_("`%%%s' not allowed with `%s%c'"),
2073 i
.op
[op
].regs
->reg_name
,
2078 /* Warn if the e prefix on a general reg is missing. */
2079 else if (((i
.types
[op
] & Reg16
) != 0
2080 || (i
.types
[op
] & Reg32
) != 0)
2081 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2083 /* Prohibit these changes in the 64bit mode, since
2084 the lowering is more complicated. */
2085 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2086 i
.op
[op
].regs
->reg_name
,
2090 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2093 for (op
= i
.operands
; --op
>= 0;)
2094 /* Reject eight bit registers, except where the template
2095 requires them. (eg. movzb) */
2096 if ((i
.types
[op
] & Reg8
) != 0
2097 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2099 as_bad (_("`%%%s' not allowed with `%s%c'"),
2100 i
.op
[op
].regs
->reg_name
,
2105 /* Warn if the e prefix on a general reg is present. */
2106 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2107 && (i
.types
[op
] & Reg32
) != 0
2108 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
2110 /* Prohibit these changes in the 64bit mode, since
2111 the lowering is more complicated. */
2112 if (flag_code
== CODE_64BIT
)
2113 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2114 i
.op
[op
].regs
->reg_name
,
2117 #if REGISTER_WARNINGS
2118 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2119 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2120 i
.op
[op
].regs
->reg_name
,
2125 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2126 /* Do nothing if the instruction is going to ignore the prefix. */
2131 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2133 i
.suffix
= stackop_size
;
2135 /* Make still unresolved immediate matches conform to size of immediate
2136 given in i.suffix. Note: overlap2 cannot be an immediate! */
2137 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2138 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2139 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2140 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2144 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2145 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2146 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2148 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2149 || overlap0
== (Imm16
| Imm32
)
2150 || overlap0
== (Imm16
| Imm32S
))
2153 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2155 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2156 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2157 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2159 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2163 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2164 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2165 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2166 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2170 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2171 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2172 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2174 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2175 || overlap1
== (Imm16
| Imm32
)
2176 || overlap1
== (Imm16
| Imm32S
))
2179 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2181 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2182 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2183 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2185 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2189 assert ((overlap2
& Imm
) == 0);
2191 i
.types
[0] = overlap0
;
2192 if (overlap0
& ImplicitRegister
)
2194 if (overlap0
& Imm1
)
2195 i
.imm_operands
= 0; /* kludge for shift insns. */
2197 i
.types
[1] = overlap1
;
2198 if (overlap1
& ImplicitRegister
)
2201 i
.types
[2] = overlap2
;
2202 if (overlap2
& ImplicitRegister
)
2205 /* Finalize opcode. First, we change the opcode based on the operand
2206 size given by i.suffix: We need not change things for byte insns. */
2208 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2210 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2214 /* For movzx and movsx, need to check the register type. */
2216 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
2217 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
2219 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2221 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
2222 if (!add_prefix (prefix
))
2226 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2228 /* It's not a byte, select word/dword operation. */
2229 if (i
.tm
.opcode_modifier
& W
)
2231 if (i
.tm
.opcode_modifier
& ShortForm
)
2232 i
.tm
.base_opcode
|= 8;
2234 i
.tm
.base_opcode
|= 1;
2236 /* Now select between word & dword operations via the operand
2237 size prefix, except for instructions that will ignore this
2239 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2240 && (i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2241 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
2243 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2244 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2245 prefix
= ADDR_PREFIX_OPCODE
;
2247 if (! add_prefix (prefix
))
2251 /* Set mode64 for an operand. */
2252 if (i
.suffix
== QWORD_MNEM_SUFFIX
2253 && !(i
.tm
.opcode_modifier
& NoRex64
))
2256 if (flag_code
< CODE_64BIT
)
2258 as_bad (_("64bit operations available only in 64bit modes."));
2263 /* Size floating point instruction. */
2264 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2266 if (i
.tm
.opcode_modifier
& FloatMF
)
2267 i
.tm
.base_opcode
^= 4;
2271 if (i
.tm
.opcode_modifier
& ImmExt
)
2273 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2274 opcode suffix which is coded in the same place as an 8-bit
2275 immediate field would be. Here we fake an 8-bit immediate
2276 operand from the opcode suffix stored in tm.extension_opcode. */
2280 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
2282 exp
= &im_expressions
[i
.imm_operands
++];
2283 i
.op
[i
.operands
].imms
= exp
;
2284 i
.types
[i
.operands
++] = Imm8
;
2285 exp
->X_op
= O_constant
;
2286 exp
->X_add_number
= i
.tm
.extension_opcode
;
2287 i
.tm
.extension_opcode
= None
;
2290 /* For insns with operands there are more diddles to do to the opcode. */
2293 /* Default segment register this instruction will use
2294 for memory accesses. 0 means unknown.
2295 This is only for optimizing out unnecessary segment overrides. */
2296 const seg_entry
*default_seg
= 0;
2298 /* The imul $imm, %reg instruction is converted into
2299 imul $imm, %reg, %reg, and the clr %reg instruction
2300 is converted into xor %reg, %reg. */
2301 if (i
.tm
.opcode_modifier
& regKludge
)
2303 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2304 /* Pretend we saw the extra register operand. */
2305 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2306 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2307 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2311 if (i
.tm
.opcode_modifier
& ShortForm
)
2313 /* The register or float register operand is in operand 0 or 1. */
2314 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2315 /* Register goes in low 3 bits of opcode. */
2316 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2317 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2319 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2321 /* Warn about some common errors, but press on regardless.
2322 The first case can be generated by gcc (<= 2.8.1). */
2323 if (i
.operands
== 2)
2325 /* Reversed arguments on faddp, fsubp, etc. */
2326 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2327 i
.op
[1].regs
->reg_name
,
2328 i
.op
[0].regs
->reg_name
);
2332 /* Extraneous `l' suffix on fp insn. */
2333 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2334 i
.op
[0].regs
->reg_name
);
2338 else if (i
.tm
.opcode_modifier
& Modrm
)
2340 /* The opcode is completed (modulo i.tm.extension_opcode which
2341 must be put into the modrm byte).
2342 Now, we make the modrm & index base bytes based on all the
2343 info we've collected. */
2345 /* i.reg_operands MUST be the number of real register operands;
2346 implicit registers do not count. */
2347 if (i
.reg_operands
== 2)
2349 unsigned int source
, dest
;
2350 source
= ((i
.types
[0]
2351 & (Reg
| RegMMX
| RegXMM
2353 | Control
| Debug
| Test
))
2358 /* One of the register operands will be encoded in the
2359 i.tm.reg field, the other in the combined i.tm.mode
2360 and i.tm.regmem fields. If no form of this
2361 instruction supports a memory destination operand,
2362 then we assume the source operand may sometimes be
2363 a memory operand and so we need to store the
2364 destination in the i.rm.reg field. */
2365 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2367 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2368 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2369 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2371 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2376 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2377 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2378 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2380 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2385 { /* If it's not 2 reg operands... */
2388 unsigned int fake_zero_displacement
= 0;
2389 unsigned int op
= ((i
.types
[0] & AnyMem
)
2391 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2398 if (! i
.disp_operands
)
2399 fake_zero_displacement
= 1;
2402 /* Operand is just <disp> */
2403 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2405 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2406 i
.types
[op
] &= ~Disp
;
2407 i
.types
[op
] |= Disp16
;
2409 else if (flag_code
!= CODE_64BIT
)
2411 i
.rm
.regmem
= NO_BASE_REGISTER
;
2412 i
.types
[op
] &= ~Disp
;
2413 i
.types
[op
] |= Disp32
;
2417 /* 64bit mode overwrites the 32bit
2418 absolute addressing by RIP relative
2419 addressing and absolute addressing
2420 is encoded by one of the redundant
2423 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2424 i
.sib
.base
= NO_BASE_REGISTER
;
2425 i
.sib
.index
= NO_INDEX_REGISTER
;
2426 i
.types
[op
] &= ~Disp
;
2427 i
.types
[op
] |= Disp32S
;
2430 else /* ! i.base_reg && i.index_reg */
2432 i
.sib
.index
= i
.index_reg
->reg_num
;
2433 i
.sib
.base
= NO_BASE_REGISTER
;
2434 i
.sib
.scale
= i
.log2_scale_factor
;
2435 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2436 i
.types
[op
] &= ~Disp
;
2437 if (flag_code
!= CODE_64BIT
)
2438 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2440 i
.types
[op
] |= Disp32S
;
2441 if (i
.index_reg
->reg_flags
& RegRex
)
2445 /* RIP addressing for 64bit mode. */
2446 else if (i
.base_reg
->reg_type
== BaseIndex
)
2448 i
.rm
.regmem
= NO_BASE_REGISTER
;
2449 i
.types
[op
] &= ~Disp
;
2450 i
.types
[op
] |= Disp32S
;
2451 i
.flags
[op
] = Operand_PCrel
;
2453 else if (i
.base_reg
->reg_type
& Reg16
)
2455 switch (i
.base_reg
->reg_num
)
2460 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2461 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2468 if ((i
.types
[op
] & Disp
) == 0)
2470 /* fake (%bp) into 0(%bp) */
2471 i
.types
[op
] |= Disp8
;
2472 fake_zero_displacement
= 1;
2475 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2476 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2478 default: /* (%si) -> 4 or (%di) -> 5 */
2479 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2481 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2483 else /* i.base_reg and 32/64 bit mode */
2485 if (flag_code
== CODE_64BIT
2486 && (i
.types
[op
] & Disp
))
2488 if (i
.types
[op
] & Disp8
)
2489 i
.types
[op
] = Disp8
| Disp32S
;
2491 i
.types
[op
] = Disp32S
;
2493 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2494 if (i
.base_reg
->reg_flags
& RegRex
)
2496 i
.sib
.base
= i
.base_reg
->reg_num
;
2497 /* x86-64 ignores REX prefix bit here to avoid
2498 decoder complications. */
2499 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2502 if (i
.disp_operands
== 0)
2504 fake_zero_displacement
= 1;
2505 i
.types
[op
] |= Disp8
;
2508 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2512 i
.sib
.scale
= i
.log2_scale_factor
;
2515 /* <disp>(%esp) becomes two byte modrm
2516 with no index register. We've already
2517 stored the code for esp in i.rm.regmem
2518 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2519 base register besides %esp will not use
2520 the extra modrm byte. */
2521 i
.sib
.index
= NO_INDEX_REGISTER
;
2522 #if ! SCALE1_WHEN_NO_INDEX
2523 /* Another case where we force the second
2525 if (i
.log2_scale_factor
)
2526 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2531 i
.sib
.index
= i
.index_reg
->reg_num
;
2532 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2533 if (i
.index_reg
->reg_flags
& RegRex
)
2536 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2539 if (fake_zero_displacement
)
2541 /* Fakes a zero displacement assuming that i.types[op]
2542 holds the correct displacement size. */
2545 assert (i
.op
[op
].disps
== 0);
2546 exp
= &disp_expressions
[i
.disp_operands
++];
2547 i
.op
[op
].disps
= exp
;
2548 exp
->X_op
= O_constant
;
2549 exp
->X_add_number
= 0;
2550 exp
->X_add_symbol
= (symbolS
*) 0;
2551 exp
->X_op_symbol
= (symbolS
*) 0;
2555 /* Fill in i.rm.reg or i.rm.regmem field with register
2556 operand (if any) based on i.tm.extension_opcode.
2557 Again, we must be careful to make sure that
2558 segment/control/debug/test/MMX registers are coded
2559 into the i.rm.reg field. */
2564 & (Reg
| RegMMX
| RegXMM
2566 | Control
| Debug
| Test
))
2569 & (Reg
| RegMMX
| RegXMM
2571 | Control
| Debug
| Test
))
2574 /* If there is an extension opcode to put here, the
2575 register number must be put into the regmem field. */
2576 if (i
.tm
.extension_opcode
!= None
)
2578 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2579 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2584 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2585 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2589 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2590 we must set it to 3 to indicate this is a register
2591 operand in the regmem field. */
2592 if (!i
.mem_operands
)
2596 /* Fill in i.rm.reg field with extension opcode (if any). */
2597 if (i
.tm
.extension_opcode
!= None
)
2598 i
.rm
.reg
= i
.tm
.extension_opcode
;
2601 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2603 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2604 && i
.op
[0].regs
->reg_num
== 1)
2606 as_bad (_("you can't `pop %%cs'"));
2609 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2610 if (i
.op
[0].regs
->reg_flags
& RegRex
)
2613 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
2617 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2619 /* For the string instructions that allow a segment override
2620 on one of their operands, the default segment is ds. */
2624 /* If a segment was explicitly specified,
2625 and the specified segment is not the default,
2626 use an opcode prefix to select it.
2627 If we never figured out what the default segment is,
2628 then default_seg will be zero at this point,
2629 and the specified segment prefix will always be used. */
2630 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2632 if (! add_prefix (i
.seg
[0]->seg_prefix
))
2636 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2638 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2639 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2643 /* Handle conversion of 'int $3' --> special int3 insn. */
2644 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2646 i
.tm
.base_opcode
= INT3_OPCODE
;
2650 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
2651 && i
.op
[0].disps
->X_op
== O_constant
)
2653 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2654 the absolute address given by the constant. Since ix86 jumps and
2655 calls are pc relative, we need to generate a reloc. */
2656 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2657 i
.op
[0].disps
->X_op
= O_symbol
;
2660 if (i
.tm
.opcode_modifier
& Rex64
)
2663 /* For 8bit registers we would need an empty rex prefix.
2664 Also in the case instruction is already having prefix,
2665 we need to convert old registers to new ones. */
2667 if (((i
.types
[0] & Reg8
) && (i
.op
[0].regs
->reg_flags
& RegRex64
))
2668 || ((i
.types
[1] & Reg8
) && (i
.op
[1].regs
->reg_flags
& RegRex64
))
2669 || ((i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2670 && ((i
.types
[0] & Reg8
) || (i
.types
[1] & Reg8
))))
2674 for (x
= 0; x
< 2; x
++)
2676 /* Look for 8bit operand that does use old registers. */
2677 if (i
.types
[x
] & Reg8
2678 && !(i
.op
[x
].regs
->reg_flags
& RegRex64
))
2680 /* In case it is "hi" register, give up. */
2681 if (i
.op
[x
].regs
->reg_num
> 3)
2682 as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"),
2683 i
.op
[x
].regs
->reg_name
);
2685 /* Otherwise it is equivalent to the extended register.
2686 Since the encoding don't change this is merely cosmetical
2687 cleanup for debug output. */
2689 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2694 if (i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2696 | (i
.rex
.mode64
? 8 : 0)
2697 | (i
.rex
.extX
? 4 : 0)
2698 | (i
.rex
.extY
? 2 : 0)
2699 | (i
.rex
.extZ
? 1 : 0));
2701 /* We are ready to output the insn. */
2706 if (i
.tm
.opcode_modifier
& Jump
)
2712 if (flag_code
== CODE_16BIT
)
2716 if (i
.prefix
[DATA_PREFIX
])
2722 if (i
.prefix
[REX_PREFIX
])
2728 if (i
.prefixes
!= 0 && !intel_syntax
)
2729 as_warn (_("skipping prefixes on this instruction"));
2731 /* It's always a symbol; End frag & setup for relax.
2732 Make sure there is enough room in this frag for the largest
2733 instruction we may generate in md_convert_frag. This is 2
2734 bytes for the opcode and room for the prefix and largest
2736 frag_grow (prefix
+ 2 + 4);
2737 insn_size
+= prefix
+ 1;
2738 /* Prefix and 1 opcode byte go in fr_fix. */
2739 p
= frag_more (prefix
+ 1);
2740 if (i
.prefix
[DATA_PREFIX
])
2741 *p
++ = DATA_PREFIX_OPCODE
;
2742 if (i
.prefix
[REX_PREFIX
])
2743 *p
++ = i
.prefix
[REX_PREFIX
];
2744 *p
= i
.tm
.base_opcode
;
2745 /* 1 possible extra opcode + displacement go in var part.
2746 Pass reloc in fr_var. */
2747 frag_var (rs_machine_dependent
,
2750 ((unsigned char) *p
== JUMP_PC_RELATIVE
2751 ? ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
) | code16
2752 : ((cpu_arch_flags
& Cpu386
) != 0
2753 ? ENCODE_RELAX_STATE (COND_JUMP
, SMALL
) | code16
2754 : ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
) | code16
)),
2755 i
.op
[0].disps
->X_add_symbol
,
2756 i
.op
[0].disps
->X_add_number
,
2759 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
2763 if (i
.tm
.opcode_modifier
& JumpByte
)
2765 /* This is a loop or jecxz type instruction. */
2767 if (i
.prefix
[ADDR_PREFIX
])
2770 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2779 if (flag_code
== CODE_16BIT
)
2782 if (i
.prefix
[DATA_PREFIX
])
2785 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
2795 if (i
.prefix
[REX_PREFIX
])
2797 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
2802 if (i
.prefixes
!= 0 && !intel_syntax
)
2803 as_warn (_("skipping prefixes on this instruction"));
2805 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2807 insn_size
+= 1 + size
;
2808 p
= frag_more (1 + size
);
2812 /* Opcode can be at most two bytes. */
2813 insn_size
+= 2 + size
;
2814 p
= frag_more (2 + size
);
2815 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2817 *p
++ = i
.tm
.base_opcode
& 0xff;
2819 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2820 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
2822 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
2829 if (flag_code
== CODE_16BIT
)
2833 if (i
.prefix
[DATA_PREFIX
])
2839 if (i
.prefix
[REX_PREFIX
])
2849 if (i
.prefixes
!= 0 && !intel_syntax
)
2850 as_warn (_("skipping prefixes on this instruction"));
2852 /* 1 opcode; 2 segment; offset */
2853 insn_size
+= prefix
+ 1 + 2 + size
;
2854 p
= frag_more (prefix
+ 1 + 2 + size
);
2856 if (i
.prefix
[DATA_PREFIX
])
2857 *p
++ = DATA_PREFIX_OPCODE
;
2859 if (i
.prefix
[REX_PREFIX
])
2860 *p
++ = i
.prefix
[REX_PREFIX
];
2862 *p
++ = i
.tm
.base_opcode
;
2863 if (i
.op
[1].imms
->X_op
== O_constant
)
2865 offsetT n
= i
.op
[1].imms
->X_add_number
;
2868 && !fits_in_unsigned_word (n
)
2869 && !fits_in_signed_word (n
))
2871 as_bad (_("16-bit jump out of range"));
2874 md_number_to_chars (p
, n
, size
);
2877 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2878 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
2879 if (i
.op
[0].imms
->X_op
!= O_constant
)
2880 as_bad (_("can't handle non absolute segment in `%s'"),
2882 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
2886 /* Output normal instructions here. */
2889 /* All opcodes on i386 have eighter 1 or 2 bytes. We may use third
2890 byte for the SSE instructions to specify prefix they require. */
2891 if (i
.tm
.base_opcode
& 0xff0000)
2892 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
2894 /* The prefix bytes. */
2896 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2903 md_number_to_chars (p
, (valueT
) *q
, 1);
2907 /* Now the opcode; be careful about word order here! */
2908 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2911 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2917 /* Put out high byte first: can't use md_number_to_chars! */
2918 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2919 *p
= i
.tm
.base_opcode
& 0xff;
2922 /* Now the modrm byte and sib byte (if present). */
2923 if (i
.tm
.opcode_modifier
& Modrm
)
2927 md_number_to_chars (p
,
2928 (valueT
) (i
.rm
.regmem
<< 0
2932 /* If i.rm.regmem == ESP (4)
2933 && i.rm.mode != (Register mode)
2935 ==> need second modrm byte. */
2936 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2938 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2942 md_number_to_chars (p
,
2943 (valueT
) (i
.sib
.base
<< 0
2945 | i
.sib
.scale
<< 6),
2950 if (i
.disp_operands
)
2952 register unsigned int n
;
2954 for (n
= 0; n
< i
.operands
; n
++)
2956 if (i
.types
[n
] & Disp
)
2958 if (i
.op
[n
].disps
->X_op
== O_constant
)
2964 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
2967 if (i
.types
[n
] & Disp8
)
2969 if (i
.types
[n
] & Disp64
)
2972 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
2975 p
= frag_more (size
);
2976 md_number_to_chars (p
, val
, size
);
2982 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
2984 /* The PC relative address is computed relative
2985 to the instruction boundary, so in case immediate
2986 fields follows, we need to adjust the value. */
2987 if (pcrel
&& i
.imm_operands
)
2990 register unsigned int n1
;
2992 for (n1
= 0; n1
< i
.operands
; n1
++)
2993 if (i
.types
[n1
] & Imm
)
2995 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
2998 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3000 if (i
.types
[n1
] & Imm64
)
3005 /* We should find the immediate. */
3006 if (n1
== i
.operands
)
3008 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3011 if (i
.types
[n
] & Disp32S
)
3014 if (i
.types
[n
] & (Disp16
| Disp64
))
3017 if (i
.types
[n
] & Disp64
)
3022 p
= frag_more (size
);
3023 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3024 i
.op
[n
].disps
, pcrel
,
3025 reloc (size
, pcrel
, sign
, i
.reloc
[n
]));
3031 /* Output immediate. */
3034 register unsigned int n
;
3036 for (n
= 0; n
< i
.operands
; n
++)
3038 if (i
.types
[n
] & Imm
)
3040 if (i
.op
[n
].imms
->X_op
== O_constant
)
3046 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3049 if (i
.types
[n
] & (Imm8
| Imm8S
))
3051 else if (i
.types
[n
] & Imm64
)
3054 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3057 p
= frag_more (size
);
3058 md_number_to_chars (p
, val
, size
);
3062 /* Not absolute_section.
3063 Need a 32-bit fixup (don't support 8bit
3064 non-absolute imms). Try to support other
3066 RELOC_ENUM reloc_type
;
3070 if ((i
.types
[n
] & (Imm32S
))
3071 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3073 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3076 if (i
.types
[n
] & (Imm8
| Imm8S
))
3078 if (i
.types
[n
] & Imm64
)
3083 p
= frag_more (size
);
3084 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3085 #ifdef BFD_ASSEMBLER
3086 if (reloc_type
== BFD_RELOC_32
3088 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3089 && (i
.op
[n
].imms
->X_op
== O_symbol
3090 || (i
.op
[n
].imms
->X_op
== O_add
3091 && ((symbol_get_value_expression
3092 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3095 /* We don't support dynamic linking on x86-64 yet. */
3096 if (flag_code
== CODE_64BIT
)
3098 reloc_type
= BFD_RELOC_386_GOTPC
;
3099 i
.op
[n
].imms
->X_add_number
+= 3;
3102 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3103 i
.op
[n
].imms
, 0, reloc_type
);
3110 dwarf2_emit_insn (insn_size
);
3117 #endif /* DEBUG386 */
3122 static char *lex_got
PARAMS ((RELOC_ENUM
*, int *));
3124 /* Parse operands of the form
3125 <symbol>@GOTOFF+<nnn>
3126 and similar .plt or .got references.
3128 If we find one, set up the correct relocation in RELOC and copy the
3129 input string, minus the `@GOTOFF' into a malloc'd buffer for
3130 parsing by the calling routine. Return this buffer, and if ADJUST
3131 is non-null set it to the length of the string we removed from the
3132 input line. Otherwise return NULL. */
3134 lex_got (reloc
, adjust
)
3138 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3139 static const struct {
3141 const RELOC_ENUM rel
[NUM_FLAG_CODE
];
3143 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
} },
3144 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, 0 } },
3145 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
} },
3146 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
} }
3151 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3152 if (is_end_of_line
[(unsigned char) *cp
])
3155 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3159 len
= strlen (gotrel
[j
].str
);
3160 if (strncmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3162 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3167 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3169 if (GOT_symbol
== NULL
)
3170 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3172 /* Replace the relocation token with ' ', so that
3173 errors like foo@GOTOFF1 will be detected. */
3174 first
= cp
- input_line_pointer
;
3175 tmpbuf
= xmalloc (strlen (input_line_pointer
));
3176 memcpy (tmpbuf
, input_line_pointer
, first
);
3177 tmpbuf
[first
] = ' ';
3178 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
3184 as_bad (_("@%s reloc is not supported in %s bit mode"),
3185 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3190 /* Might be a symbol version string. Don't as_bad here. */
3194 /* x86_cons_fix_new is called via the expression parsing code when a
3195 reloc is needed. We use this hook to get the correct .got reloc. */
3196 static RELOC_ENUM got_reloc
= NO_RELOC
;
3199 x86_cons_fix_new (frag
, off
, len
, exp
)
3205 RELOC_ENUM r
= reloc (len
, 0, 0, got_reloc
);
3206 got_reloc
= NO_RELOC
;
3207 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3211 x86_cons (exp
, size
)
3217 /* Handle @GOTOFF and the like in an expression. */
3219 char *gotfree_input_line
;
3222 save
= input_line_pointer
;
3223 gotfree_input_line
= lex_got (&got_reloc
, &adjust
);
3224 if (gotfree_input_line
)
3225 input_line_pointer
= gotfree_input_line
;
3229 if (gotfree_input_line
)
3231 /* expression () has merrily parsed up to the end of line,
3232 or a comma - in the wrong buffer. Transfer how far
3233 input_line_pointer has moved to the right buffer. */
3234 input_line_pointer
= (save
3235 + (input_line_pointer
- gotfree_input_line
)
3237 free (gotfree_input_line
);
3245 static int i386_immediate
PARAMS ((char *));
3248 i386_immediate (imm_start
)
3251 char *save_input_line_pointer
;
3253 char *gotfree_input_line
;
3258 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3260 as_bad (_("only 1 or 2 immediate operands are allowed"));
3264 exp
= &im_expressions
[i
.imm_operands
++];
3265 i
.op
[this_operand
].imms
= exp
;
3267 if (is_space_char (*imm_start
))
3270 save_input_line_pointer
= input_line_pointer
;
3271 input_line_pointer
= imm_start
;
3274 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3275 if (gotfree_input_line
)
3276 input_line_pointer
= gotfree_input_line
;
3279 exp_seg
= expression (exp
);
3282 if (*input_line_pointer
)
3283 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3285 input_line_pointer
= save_input_line_pointer
;
3287 if (gotfree_input_line
)
3288 free (gotfree_input_line
);
3291 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3293 /* Missing or bad expr becomes absolute 0. */
3294 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3296 exp
->X_op
= O_constant
;
3297 exp
->X_add_number
= 0;
3298 exp
->X_add_symbol
= (symbolS
*) 0;
3299 exp
->X_op_symbol
= (symbolS
*) 0;
3301 else if (exp
->X_op
== O_constant
)
3303 /* Size it properly later. */
3304 i
.types
[this_operand
] |= Imm64
;
3305 /* If BFD64, sign extend val. */
3306 if (!use_rela_relocations
)
3307 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3308 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3310 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3312 #ifdef BFD_ASSEMBLER
3313 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3315 && exp_seg
!= text_section
3316 && exp_seg
!= data_section
3317 && exp_seg
!= bss_section
3318 && exp_seg
!= undefined_section
3319 #ifdef BFD_ASSEMBLER
3320 && !bfd_is_com_section (exp_seg
)
3324 #ifdef BFD_ASSEMBLER
3325 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3327 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3334 /* This is an address. The size of the address will be
3335 determined later, depending on destination register,
3336 suffix, or the default for the section. */
3337 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3343 static char *i386_scale
PARAMS ((char *));
3350 char *save
= input_line_pointer
;
3352 input_line_pointer
= scale
;
3353 val
= get_absolute_expression ();
3359 i
.log2_scale_factor
= 0;
3362 i
.log2_scale_factor
= 1;
3365 i
.log2_scale_factor
= 2;
3368 i
.log2_scale_factor
= 3;
3371 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3373 input_line_pointer
= save
;
3376 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
3378 as_warn (_("scale factor of %d without an index register"),
3379 1 << i
.log2_scale_factor
);
3380 #if SCALE1_WHEN_NO_INDEX
3381 i
.log2_scale_factor
= 0;
3384 scale
= input_line_pointer
;
3385 input_line_pointer
= save
;
3389 static int i386_displacement
PARAMS ((char *, char *));
3392 i386_displacement (disp_start
, disp_end
)
3396 register expressionS
*exp
;
3398 char *save_input_line_pointer
;
3400 char *gotfree_input_line
;
3402 int bigdisp
= Disp32
;
3404 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3406 if (flag_code
== CODE_64BIT
)
3408 i
.types
[this_operand
] |= bigdisp
;
3410 exp
= &disp_expressions
[i
.disp_operands
];
3411 i
.op
[this_operand
].disps
= exp
;
3413 save_input_line_pointer
= input_line_pointer
;
3414 input_line_pointer
= disp_start
;
3415 END_STRING_AND_SAVE (disp_end
);
3417 #ifndef GCC_ASM_O_HACK
3418 #define GCC_ASM_O_HACK 0
3421 END_STRING_AND_SAVE (disp_end
+ 1);
3422 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3423 && displacement_string_end
[-1] == '+')
3425 /* This hack is to avoid a warning when using the "o"
3426 constraint within gcc asm statements.
3429 #define _set_tssldt_desc(n,addr,limit,type) \
3430 __asm__ __volatile__ ( \
3432 "movw %w1,2+%0\n\t" \
3434 "movb %b1,4+%0\n\t" \
3435 "movb %4,5+%0\n\t" \
3436 "movb $0,6+%0\n\t" \
3437 "movb %h1,7+%0\n\t" \
3439 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3441 This works great except that the output assembler ends
3442 up looking a bit weird if it turns out that there is
3443 no offset. You end up producing code that looks like:
3456 So here we provide the missing zero. */
3458 *displacement_string_end
= '0';
3462 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3463 if (gotfree_input_line
)
3464 input_line_pointer
= gotfree_input_line
;
3467 exp_seg
= expression (exp
);
3470 if (*input_line_pointer
)
3471 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3473 RESTORE_END_STRING (disp_end
+ 1);
3475 RESTORE_END_STRING (disp_end
);
3476 input_line_pointer
= save_input_line_pointer
;
3478 if (gotfree_input_line
)
3479 free (gotfree_input_line
);
3482 #ifdef BFD_ASSEMBLER
3483 /* We do this to make sure that the section symbol is in
3484 the symbol table. We will ultimately change the relocation
3485 to be relative to the beginning of the section. */
3486 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3487 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3489 if (exp
->X_op
!= O_symbol
)
3491 as_bad (_("bad expression used with @%s"),
3492 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
3498 if (S_IS_LOCAL (exp
->X_add_symbol
)
3499 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3500 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3501 exp
->X_op
= O_subtract
;
3502 exp
->X_op_symbol
= GOT_symbol
;
3503 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3504 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
3506 i
.reloc
[this_operand
] = BFD_RELOC_32
;
3510 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3512 /* Missing or bad expr becomes absolute 0. */
3513 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3515 exp
->X_op
= O_constant
;
3516 exp
->X_add_number
= 0;
3517 exp
->X_add_symbol
= (symbolS
*) 0;
3518 exp
->X_op_symbol
= (symbolS
*) 0;
3521 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3522 if (exp
->X_op
!= O_constant
3523 #ifdef BFD_ASSEMBLER
3524 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3526 && exp_seg
!= text_section
3527 && exp_seg
!= data_section
3528 && exp_seg
!= bss_section
3529 && exp_seg
!= undefined_section
)
3531 #ifdef BFD_ASSEMBLER
3532 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3534 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3539 else if (flag_code
== CODE_64BIT
)
3540 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3544 static int i386_index_check
PARAMS ((const char *));
3546 /* Make sure the memory operand we've been dealt is valid.
3547 Return 1 on success, 0 on a failure. */
3550 i386_index_check (operand_string
)
3551 const char *operand_string
;
3554 #if INFER_ADDR_PREFIX
3560 if (flag_code
== CODE_64BIT
)
3564 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3565 && (i
.base_reg
->reg_type
!= BaseIndex
3568 && ((i
.index_reg
->reg_type
& (Reg64
|BaseIndex
))
3569 != (Reg64
|BaseIndex
))))
3574 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3578 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
|RegRex
))
3579 != (Reg16
|BaseIndex
)))
3581 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
3582 != (Reg16
|BaseIndex
))
3584 && i
.base_reg
->reg_num
< 6
3585 && i
.index_reg
->reg_num
>= 6
3586 && i
.log2_scale_factor
== 0))))
3593 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3595 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
|RegRex
))
3596 != (Reg32
|BaseIndex
))))
3602 #if INFER_ADDR_PREFIX
3603 if (flag_code
!= CODE_64BIT
3604 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3606 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3608 /* Change the size of any displacement too. At most one of
3609 Disp16 or Disp32 is set.
3610 FIXME. There doesn't seem to be any real need for separate
3611 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3612 Removing them would probably clean up the code quite a lot. */
3613 if (i
.types
[this_operand
] & (Disp16
|Disp32
))
3614 i
.types
[this_operand
] ^= (Disp16
|Disp32
);
3619 as_bad (_("`%s' is not a valid base/index expression"),
3623 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3625 flag_code_names
[flag_code
]);
3631 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3635 i386_operand (operand_string
)
3636 char *operand_string
;
3640 char *op_string
= operand_string
;
3642 if (is_space_char (*op_string
))
3645 /* We check for an absolute prefix (differentiating,
3646 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3647 if (*op_string
== ABSOLUTE_PREFIX
)
3650 if (is_space_char (*op_string
))
3652 i
.types
[this_operand
] |= JumpAbsolute
;
3655 /* Check if operand is a register. */
3656 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3657 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3659 /* Check for a segment override by searching for ':' after a
3660 segment register. */
3662 if (is_space_char (*op_string
))
3664 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3669 i
.seg
[i
.mem_operands
] = &es
;
3672 i
.seg
[i
.mem_operands
] = &cs
;
3675 i
.seg
[i
.mem_operands
] = &ss
;
3678 i
.seg
[i
.mem_operands
] = &ds
;
3681 i
.seg
[i
.mem_operands
] = &fs
;
3684 i
.seg
[i
.mem_operands
] = &gs
;
3688 /* Skip the ':' and whitespace. */
3690 if (is_space_char (*op_string
))
3693 if (!is_digit_char (*op_string
)
3694 && !is_identifier_char (*op_string
)
3695 && *op_string
!= '('
3696 && *op_string
!= ABSOLUTE_PREFIX
)
3698 as_bad (_("bad memory operand `%s'"), op_string
);
3701 /* Handle case of %es:*foo. */
3702 if (*op_string
== ABSOLUTE_PREFIX
)
3705 if (is_space_char (*op_string
))
3707 i
.types
[this_operand
] |= JumpAbsolute
;
3709 goto do_memory_reference
;
3713 as_bad (_("junk `%s' after register"), op_string
);
3716 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3717 i
.op
[this_operand
].regs
= r
;
3720 else if (*op_string
== REGISTER_PREFIX
)
3722 as_bad (_("bad register name `%s'"), op_string
);
3725 else if (*op_string
== IMMEDIATE_PREFIX
)
3728 if (i
.types
[this_operand
] & JumpAbsolute
)
3730 as_bad (_("immediate operand illegal with absolute jump"));
3733 if (!i386_immediate (op_string
))
3736 else if (is_digit_char (*op_string
)
3737 || is_identifier_char (*op_string
)
3738 || *op_string
== '(')
3740 /* This is a memory reference of some sort. */
3743 /* Start and end of displacement string expression (if found). */
3744 char *displacement_string_start
;
3745 char *displacement_string_end
;
3747 do_memory_reference
:
3748 if ((i
.mem_operands
== 1
3749 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3750 || i
.mem_operands
== 2)
3752 as_bad (_("too many memory references for `%s'"),
3753 current_templates
->start
->name
);
3757 /* Check for base index form. We detect the base index form by
3758 looking for an ')' at the end of the operand, searching
3759 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3761 base_string
= op_string
+ strlen (op_string
);
3764 if (is_space_char (*base_string
))
3767 /* If we only have a displacement, set-up for it to be parsed later. */
3768 displacement_string_start
= op_string
;
3769 displacement_string_end
= base_string
+ 1;
3771 if (*base_string
== ')')
3774 unsigned int parens_balanced
= 1;
3775 /* We've already checked that the number of left & right ()'s are
3776 equal, so this loop will not be infinite. */
3780 if (*base_string
== ')')
3782 if (*base_string
== '(')
3785 while (parens_balanced
);
3787 temp_string
= base_string
;
3789 /* Skip past '(' and whitespace. */
3791 if (is_space_char (*base_string
))
3794 if (*base_string
== ','
3795 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3796 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
3798 displacement_string_end
= temp_string
;
3800 i
.types
[this_operand
] |= BaseIndex
;
3804 base_string
= end_op
;
3805 if (is_space_char (*base_string
))
3809 /* There may be an index reg or scale factor here. */
3810 if (*base_string
== ',')
3813 if (is_space_char (*base_string
))
3816 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3817 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
3819 base_string
= end_op
;
3820 if (is_space_char (*base_string
))
3822 if (*base_string
== ',')
3825 if (is_space_char (*base_string
))
3828 else if (*base_string
!= ')')
3830 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3835 else if (*base_string
== REGISTER_PREFIX
)
3837 as_bad (_("bad register name `%s'"), base_string
);
3841 /* Check for scale factor. */
3842 if (*base_string
!= ')')
3844 char *end_scale
= i386_scale (base_string
);
3849 base_string
= end_scale
;
3850 if (is_space_char (*base_string
))
3852 if (*base_string
!= ')')
3854 as_bad (_("expecting `)' after scale factor in `%s'"),
3859 else if (!i
.index_reg
)
3861 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3866 else if (*base_string
!= ')')
3868 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3873 else if (*base_string
== REGISTER_PREFIX
)
3875 as_bad (_("bad register name `%s'"), base_string
);
3880 /* If there's an expression beginning the operand, parse it,
3881 assuming displacement_string_start and
3882 displacement_string_end are meaningful. */
3883 if (displacement_string_start
!= displacement_string_end
)
3885 if (!i386_displacement (displacement_string_start
,
3886 displacement_string_end
))
3890 /* Special case for (%dx) while doing input/output op. */
3892 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
3894 && i
.log2_scale_factor
== 0
3895 && i
.seg
[i
.mem_operands
] == 0
3896 && (i
.types
[this_operand
] & Disp
) == 0)
3898 i
.types
[this_operand
] = InOutPortReg
;
3902 if (i386_index_check (operand_string
) == 0)
3908 /* It's not a memory operand; argh! */
3909 as_bad (_("invalid char %s beginning operand %d `%s'"),
3910 output_invalid (*op_string
),
3915 return 1; /* Normal return. */
3918 /* md_estimate_size_before_relax()
3920 Called just before relax() for rs_machine_dependent frags. The x86
3921 assembler uses these frags to handle variable size jump
3924 Any symbol that is now undefined will not become defined.
3925 Return the correct fr_subtype in the frag.
3926 Return the initial "guess for variable size of frag" to caller.
3927 The guess is actually the growth beyond the fixed part. Whatever
3928 we do to grow the fixed or variable part contributes to our
3932 md_estimate_size_before_relax (fragP
, segment
)
3933 register fragS
*fragP
;
3934 register segT segment
;
3936 /* We've already got fragP->fr_subtype right; all we have to do is
3937 check for un-relaxable symbols. On an ELF system, we can't relax
3938 an externally visible symbol, because it may be overridden by a
3940 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3941 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3942 || S_IS_EXTERNAL (fragP
->fr_symbol
)
3943 || S_IS_WEAK (fragP
->fr_symbol
)
3947 /* Symbol is undefined in this segment, or we need to keep a
3948 reloc so that weak symbols can be overridden. */
3949 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
3950 RELOC_ENUM reloc_type
;
3951 unsigned char *opcode
;
3954 if (fragP
->fr_var
!= NO_RELOC
)
3955 reloc_type
= fragP
->fr_var
;
3957 reloc_type
= BFD_RELOC_16_PCREL
;
3959 reloc_type
= BFD_RELOC_32_PCREL
;
3961 old_fr_fix
= fragP
->fr_fix
;
3962 opcode
= (unsigned char *) fragP
->fr_opcode
;
3964 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
3967 /* Make jmp (0xeb) a (d)word displacement jump. */
3969 fragP
->fr_fix
+= size
;
3970 fix_new (fragP
, old_fr_fix
, size
,
3972 fragP
->fr_offset
, 1,
3977 if (no_cond_jump_promotion
)
3982 /* Negate the condition, and branch past an
3983 unconditional jump. */
3986 /* Insert an unconditional jump. */
3988 /* We added two extra opcode bytes, and have a two byte
3990 fragP
->fr_fix
+= 2 + 2;
3991 fix_new (fragP
, old_fr_fix
+ 2, 2,
3993 fragP
->fr_offset
, 1,
4000 if (no_cond_jump_promotion
)
4003 /* This changes the byte-displacement jump 0x7N
4004 to the (d)word-displacement jump 0x0f,0x8N. */
4005 opcode
[1] = opcode
[0] + 0x10;
4006 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4007 /* We've added an opcode byte. */
4008 fragP
->fr_fix
+= 1 + size
;
4009 fix_new (fragP
, old_fr_fix
+ 1, size
,
4011 fragP
->fr_offset
, 1,
4016 BAD_CASE (fragP
->fr_subtype
);
4020 return fragP
->fr_fix
- old_fr_fix
;
4024 /* Guess size depending on current relax state. Initially the relax
4025 state will correspond to a short jump and we return 1, because
4026 the variable part of the frag (the branch offset) is one byte
4027 long. However, we can relax a section more than once and in that
4028 case we must either set fr_subtype back to the unrelaxed state,
4029 or return the value for the appropriate branch. */
4030 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4033 /* Called after relax() is finished.
4035 In: Address of frag.
4036 fr_type == rs_machine_dependent.
4037 fr_subtype is what the address relaxed to.
4039 Out: Any fixSs and constants are set up.
4040 Caller will turn frag into a ".space 0". */
4042 #ifndef BFD_ASSEMBLER
4044 md_convert_frag (headers
, sec
, fragP
)
4045 object_headers
*headers ATTRIBUTE_UNUSED
;
4046 segT sec ATTRIBUTE_UNUSED
;
4047 register fragS
*fragP
;
4050 md_convert_frag (abfd
, sec
, fragP
)
4051 bfd
*abfd ATTRIBUTE_UNUSED
;
4052 segT sec ATTRIBUTE_UNUSED
;
4053 register fragS
*fragP
;
4056 register unsigned char *opcode
;
4057 unsigned char *where_to_put_displacement
= NULL
;
4058 offsetT target_address
;
4059 offsetT opcode_address
;
4060 unsigned int extension
= 0;
4061 offsetT displacement_from_opcode_start
;
4063 opcode
= (unsigned char *) fragP
->fr_opcode
;
4065 /* Address we want to reach in file space. */
4066 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4067 #ifdef BFD_ASSEMBLER
4068 /* Not needed otherwise? */
4069 target_address
+= symbol_get_frag (fragP
->fr_symbol
)->fr_address
;
4072 /* Address opcode resides at in file space. */
4073 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4075 /* Displacement from opcode start to fill into instruction. */
4076 displacement_from_opcode_start
= target_address
- opcode_address
;
4078 if ((fragP
->fr_subtype
& BIG
) == 0)
4080 /* Don't have to change opcode. */
4081 extension
= 1; /* 1 opcode + 1 displacement */
4082 where_to_put_displacement
= &opcode
[1];
4086 if (no_cond_jump_promotion
4087 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4088 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4090 switch (fragP
->fr_subtype
)
4092 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4093 extension
= 4; /* 1 opcode + 4 displacement */
4095 where_to_put_displacement
= &opcode
[1];
4098 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4099 extension
= 2; /* 1 opcode + 2 displacement */
4101 where_to_put_displacement
= &opcode
[1];
4104 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4105 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4106 extension
= 5; /* 2 opcode + 4 displacement */
4107 opcode
[1] = opcode
[0] + 0x10;
4108 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4109 where_to_put_displacement
= &opcode
[2];
4112 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4113 extension
= 3; /* 2 opcode + 2 displacement */
4114 opcode
[1] = opcode
[0] + 0x10;
4115 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4116 where_to_put_displacement
= &opcode
[2];
4119 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4124 where_to_put_displacement
= &opcode
[3];
4128 BAD_CASE (fragP
->fr_subtype
);
4133 /* Now put displacement after opcode. */
4134 md_number_to_chars ((char *) where_to_put_displacement
,
4135 (valueT
) (displacement_from_opcode_start
- extension
),
4136 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4137 fragP
->fr_fix
+= extension
;
4140 /* Size of byte displacement jmp. */
4141 int md_short_jump_size
= 2;
4143 /* Size of dword displacement jmp. */
4144 int md_long_jump_size
= 5;
4146 /* Size of relocation record. */
4147 const int md_reloc_size
= 8;
4150 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4152 addressT from_addr
, to_addr
;
4153 fragS
*frag ATTRIBUTE_UNUSED
;
4154 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4158 offset
= to_addr
- (from_addr
+ 2);
4159 /* Opcode for byte-disp jump. */
4160 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4161 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4165 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4167 addressT from_addr
, to_addr
;
4168 fragS
*frag ATTRIBUTE_UNUSED
;
4169 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4173 offset
= to_addr
- (from_addr
+ 5);
4174 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4175 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4178 /* Apply a fixup (fixS) to segment data, once it has been determined
4179 by our caller that we have all the info we need to fix it up.
4181 On the 386, immediates, displacements, and data pointers are all in
4182 the same (little-endian) format, so we don't need to care about which
4186 md_apply_fix3 (fixP
, valp
, seg
)
4187 /* The fix we're to put in. */
4190 /* Pointer to the value of the bits. */
4193 /* Segment fix is from. */
4194 segT seg ATTRIBUTE_UNUSED
;
4196 register char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4197 valueT value
= *valp
;
4199 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4202 switch (fixP
->fx_r_type
)
4208 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4211 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4214 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4219 /* This is a hack. There should be a better way to handle this.
4220 This covers for the fact that bfd_install_relocation will
4221 subtract the current location (for partial_inplace, PC relative
4222 relocations); see more below. */
4223 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4224 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4225 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4226 && fixP
->fx_addsy
&& !use_rela_relocations
)
4229 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4231 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4234 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4236 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4237 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4239 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4242 || (symbol_section_p (fixP
->fx_addsy
)
4243 && fseg
!= absolute_section
))
4244 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
4245 && ! S_IS_WEAK (fixP
->fx_addsy
)
4246 && S_IS_DEFINED (fixP
->fx_addsy
)
4247 && ! S_IS_COMMON (fixP
->fx_addsy
))
4249 /* Yes, we add the values in twice. This is because
4250 bfd_perform_relocation subtracts them out again. I think
4251 bfd_perform_relocation is broken, but I don't dare change
4253 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4257 #if defined (OBJ_COFF) && defined (TE_PE)
4258 /* For some reason, the PE format does not store a section
4259 address offset for a PC relative symbol. */
4260 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4261 value
+= md_pcrel_from (fixP
);
4265 /* Fix a few things - the dynamic linker expects certain values here,
4266 and we must not dissappoint it. */
4267 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4268 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4270 switch (fixP
->fx_r_type
)
4272 case BFD_RELOC_386_PLT32
:
4273 case BFD_RELOC_X86_64_PLT32
:
4274 /* Make the jump instruction point to the address of the operand. At
4275 runtime we merely add the offset to the actual PLT entry. */
4278 case BFD_RELOC_386_GOTPC
:
4280 /* This is tough to explain. We end up with this one if we have
4281 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4282 * here is to obtain the absolute address of the GOT, and it is strongly
4283 * preferable from a performance point of view to avoid using a runtime
4284 * relocation for this. The actual sequence of instructions often look
4290 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4292 * The call and pop essentially return the absolute address of
4293 * the label .L66 and store it in %ebx. The linker itself will
4294 * ultimately change the first operand of the addl so that %ebx points to
4295 * the GOT, but to keep things simple, the .o file must have this operand
4296 * set so that it generates not the absolute address of .L66, but the
4297 * absolute address of itself. This allows the linker itself simply
4298 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4299 * added in, and the addend of the relocation is stored in the operand
4300 * field for the instruction itself.
4302 * Our job here is to fix the operand so that it would add the correct
4303 * offset so that %ebx would point to itself. The thing that is tricky is
4304 * that .-.L66 will point to the beginning of the instruction, so we need
4305 * to further modify the operand so that it will point to itself.
4306 * There are other cases where you have something like:
4308 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4310 * and here no correction would be required. Internally in the assembler
4311 * we treat operands of this form as not being pcrel since the '.' is
4312 * explicitly mentioned, and I wonder whether it would simplify matters
4313 * to do it this way. Who knows. In earlier versions of the PIC patches,
4314 * the pcrel_adjust field was used to store the correction, but since the
4315 * expression is not pcrel, I felt it would be confusing to do it this
4320 case BFD_RELOC_386_GOT32
:
4321 case BFD_RELOC_X86_64_GOT32
:
4322 value
= 0; /* Fully resolved at runtime. No addend. */
4324 case BFD_RELOC_386_GOTOFF
:
4325 case BFD_RELOC_X86_64_GOTPCREL
:
4328 case BFD_RELOC_VTABLE_INHERIT
:
4329 case BFD_RELOC_VTABLE_ENTRY
:
4336 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4338 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4340 #ifndef BFD_ASSEMBLER
4341 md_number_to_chars (p
, value
, fixP
->fx_size
);
4343 /* Are we finished with this relocation now? */
4344 if (fixP
->fx_addsy
== 0 && fixP
->fx_pcrel
== 0)
4346 else if (use_rela_relocations
)
4348 fixP
->fx_no_overflow
= 1;
4351 md_number_to_chars (p
, value
, fixP
->fx_size
);
4357 #define MAX_LITTLENUMS 6
4359 /* Turn the string pointed to by litP into a floating point constant
4360 of type TYPE, and emit the appropriate bytes. The number of
4361 LITTLENUMS emitted is stored in *SIZEP. An error message is
4362 returned, or NULL on OK. */
4365 md_atof (type
, litP
, sizeP
)
4371 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4372 LITTLENUM_TYPE
*wordP
;
4394 return _("Bad call to md_atof ()");
4396 t
= atof_ieee (input_line_pointer
, type
, words
);
4398 input_line_pointer
= t
;
4400 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4401 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4402 the bigendian 386. */
4403 for (wordP
= words
+ prec
- 1; prec
--;)
4405 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4406 litP
+= sizeof (LITTLENUM_TYPE
);
4411 char output_invalid_buf
[8];
4418 sprintf (output_invalid_buf
, "'%c'", c
);
4420 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4421 return output_invalid_buf
;
4424 /* REG_STRING starts *before* REGISTER_PREFIX. */
4426 static const reg_entry
*
4427 parse_register (reg_string
, end_op
)
4431 char *s
= reg_string
;
4433 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4436 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4437 if (*s
== REGISTER_PREFIX
)
4440 if (is_space_char (*s
))
4444 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4446 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4447 return (const reg_entry
*) NULL
;
4451 /* For naked regs, make sure that we are not dealing with an identifier.
4452 This prevents confusing an identifier like `eax_var' with register
4454 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4455 return (const reg_entry
*) NULL
;
4459 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4461 /* Handle floating point regs, allowing spaces in the (i) part. */
4462 if (r
== i386_regtab
/* %st is first entry of table */)
4464 if (is_space_char (*s
))
4469 if (is_space_char (*s
))
4471 if (*s
>= '0' && *s
<= '7')
4473 r
= &i386_float_regtab
[*s
- '0'];
4475 if (is_space_char (*s
))
4483 /* We have "%st(" then garbage. */
4484 return (const reg_entry
*) NULL
;
4491 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4492 const char *md_shortopts
= "kVQ:sq";
4494 const char *md_shortopts
= "q";
4497 struct option md_longopts
[] = {
4498 #define OPTION_32 (OPTION_MD_BASE + 0)
4499 {"32", no_argument
, NULL
, OPTION_32
},
4500 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4501 #define OPTION_64 (OPTION_MD_BASE + 1)
4502 {"64", no_argument
, NULL
, OPTION_64
},
4504 {NULL
, no_argument
, NULL
, 0}
4506 size_t md_longopts_size
= sizeof (md_longopts
);
4509 md_parse_option (c
, arg
)
4511 char *arg ATTRIBUTE_UNUSED
;
4519 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4520 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4521 should be emitted or not. FIXME: Not implemented. */
4525 /* -V: SVR4 argument to print version ID. */
4527 print_version_id ();
4530 /* -k: Ignore for FreeBSD compatibility. */
4535 /* -s: On i386 Solaris, this tells the native assembler to use
4536 .stab instead of .stab.excl. We always use .stab anyhow. */
4541 const char **list
, **l
;
4543 list
= bfd_target_list ();
4544 for (l
= list
; *l
!= NULL
; l
++)
4545 if (strcmp (*l
, "elf64-x86-64") == 0)
4547 default_arch
= "x86_64";
4551 as_fatal (_("No compiled in support for x86_64"));
4558 default_arch
= "i386";
4568 md_show_usage (stream
)
4571 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4572 fprintf (stream
, _("\
4574 -V print assembler version number\n\
4576 -q quieten some warnings\n\
4579 fprintf (stream
, _("\
4580 -q quieten some warnings\n"));
4584 #ifdef BFD_ASSEMBLER
4585 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4586 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4588 /* Pick the target format to use. */
4591 i386_target_format ()
4593 if (!strcmp (default_arch
, "x86_64"))
4594 set_code_flag (CODE_64BIT
);
4595 else if (!strcmp (default_arch
, "i386"))
4596 set_code_flag (CODE_32BIT
);
4598 as_fatal (_("Unknown architecture"));
4599 switch (OUTPUT_FLAVOR
)
4601 #ifdef OBJ_MAYBE_AOUT
4602 case bfd_target_aout_flavour
:
4603 return AOUT_TARGET_FORMAT
;
4605 #ifdef OBJ_MAYBE_COFF
4606 case bfd_target_coff_flavour
:
4609 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4610 case bfd_target_elf_flavour
:
4612 if (flag_code
== CODE_64BIT
)
4613 use_rela_relocations
= 1;
4614 return flag_code
== CODE_64BIT
? "elf64-x86-64" : "elf32-i386";
4623 #endif /* OBJ_MAYBE_ more than one */
4624 #endif /* BFD_ASSEMBLER */
4627 md_undefined_symbol (name
)
4630 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4631 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4632 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4633 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4637 if (symbol_find (name
))
4638 as_bad (_("GOT already in symbol table"));
4639 GOT_symbol
= symbol_new (name
, undefined_section
,
4640 (valueT
) 0, &zero_address_frag
);
4647 /* Round up a section size to the appropriate boundary. */
4650 md_section_align (segment
, size
)
4651 segT segment ATTRIBUTE_UNUSED
;
4654 #ifdef BFD_ASSEMBLER
4655 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4656 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4658 /* For a.out, force the section size to be aligned. If we don't do
4659 this, BFD will align it for us, but it will not write out the
4660 final bytes of the section. This may be a bug in BFD, but it is
4661 easier to fix it here since that is how the other a.out targets
4665 align
= bfd_get_section_alignment (stdoutput
, segment
);
4666 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4674 /* On the i386, PC-relative offsets are relative to the start of the
4675 next instruction. That is, the address of the offset, plus its
4676 size, since the offset is always the last part of the insn. */
4679 md_pcrel_from (fixP
)
4682 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4689 int ignore ATTRIBUTE_UNUSED
;
4693 temp
= get_absolute_expression ();
4694 subseg_set (bss_section
, (subsegT
) temp
);
4695 demand_empty_rest_of_line ();
4700 #ifdef BFD_ASSEMBLER
4703 i386_validate_fix (fixp
)
4706 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
4708 /* GOTOFF relocation are nonsense in 64bit mode. */
4709 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
4711 if (flag_code
!= CODE_64BIT
)
4713 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
4717 if (flag_code
== CODE_64BIT
)
4719 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
4726 tc_gen_reloc (section
, fixp
)
4727 asection
*section ATTRIBUTE_UNUSED
;
4731 bfd_reloc_code_real_type code
;
4733 switch (fixp
->fx_r_type
)
4735 case BFD_RELOC_X86_64_PLT32
:
4736 case BFD_RELOC_X86_64_GOT32
:
4737 case BFD_RELOC_X86_64_GOTPCREL
:
4738 case BFD_RELOC_386_PLT32
:
4739 case BFD_RELOC_386_GOT32
:
4740 case BFD_RELOC_386_GOTOFF
:
4741 case BFD_RELOC_386_GOTPC
:
4742 case BFD_RELOC_X86_64_32S
:
4744 case BFD_RELOC_VTABLE_ENTRY
:
4745 case BFD_RELOC_VTABLE_INHERIT
:
4746 code
= fixp
->fx_r_type
;
4751 switch (fixp
->fx_size
)
4754 as_bad (_("can not do %d byte pc-relative relocation"),
4756 code
= BFD_RELOC_32_PCREL
;
4758 case 1: code
= BFD_RELOC_8_PCREL
; break;
4759 case 2: code
= BFD_RELOC_16_PCREL
; break;
4760 case 4: code
= BFD_RELOC_32_PCREL
; break;
4765 switch (fixp
->fx_size
)
4768 as_bad (_("can not do %d byte relocation"), fixp
->fx_size
);
4769 code
= BFD_RELOC_32
;
4771 case 1: code
= BFD_RELOC_8
; break;
4772 case 2: code
= BFD_RELOC_16
; break;
4773 case 4: code
= BFD_RELOC_32
; break;
4774 case 8: code
= BFD_RELOC_64
; break;
4780 if (code
== BFD_RELOC_32
4782 && fixp
->fx_addsy
== GOT_symbol
)
4784 /* We don't support GOTPC on 64bit targets. */
4785 if (flag_code
== CODE_64BIT
)
4787 code
= BFD_RELOC_386_GOTPC
;
4790 rel
= (arelent
*) xmalloc (sizeof (arelent
));
4791 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4792 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4794 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4795 if (!use_rela_relocations
)
4797 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4798 vtable entry to be used in the relocation's section offset. */
4799 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4800 rel
->address
= fixp
->fx_offset
;
4803 rel
->addend
= fixp
->fx_addnumber
;
4807 /* Use the rela in 64bit mode. */
4810 rel
->addend
= fixp
->fx_offset
;
4812 rel
->addend
-= fixp
->fx_size
;
4815 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4816 if (rel
->howto
== NULL
)
4818 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4819 _("cannot represent relocation type %s"),
4820 bfd_get_reloc_code_name (code
));
4821 /* Set howto to a garbage value so that we can keep going. */
4822 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
4823 assert (rel
->howto
!= NULL
);
4829 #else /* ! BFD_ASSEMBLER */
4831 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4833 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4836 relax_addressT segment_address_in_file
;
4838 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4839 Out: GNU LD relocation length code: 0, 1, or 2. */
4841 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
4844 know (fixP
->fx_addsy
!= NULL
);
4846 md_number_to_chars (where
,
4847 (valueT
) (fixP
->fx_frag
->fr_address
4848 + fixP
->fx_where
- segment_address_in_file
),
4851 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4852 ? S_GET_TYPE (fixP
->fx_addsy
)
4853 : fixP
->fx_addsy
->sy_number
);
4855 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
4856 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4857 where
[4] = r_symbolnum
& 0x0ff;
4858 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
4859 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
4860 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
4863 #endif /* OBJ_AOUT or OBJ_BOUT. */
4865 #if defined (I386COFF)
4868 tc_coff_fix2rtype (fixP
)
4871 if (fixP
->fx_r_type
== R_IMAGEBASE
)
4874 return (fixP
->fx_pcrel
?
4875 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
4876 fixP
->fx_size
== 2 ? R_PCRWORD
:
4878 (fixP
->fx_size
== 1 ? R_RELBYTE
:
4879 fixP
->fx_size
== 2 ? R_RELWORD
:
4884 tc_coff_sizemachdep (frag
)
4888 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
4893 #endif /* I386COFF */
4895 #endif /* ! BFD_ASSEMBLER */
4897 /* Parse operands using Intel syntax. This implements a recursive descent
4898 parser based on the BNF grammar published in Appendix B of the MASM 6.1
4901 FIXME: We do not recognize the full operand grammar defined in the MASM
4902 documentation. In particular, all the structure/union and
4903 high-level macro operands are missing.
4905 Uppercase words are terminals, lower case words are non-terminals.
4906 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
4907 bars '|' denote choices. Most grammar productions are implemented in
4908 functions called 'intel_<production>'.
4910 Initial production is 'expr'.
4916 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
4918 constant digits [[ radixOverride ]]
4920 dataType BYTE | WORD | DWORD | QWORD | XWORD
4953 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
4954 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
4956 hexdigit a | b | c | d | e | f
4957 | A | B | C | D | E | F
4967 register specialRegister
4971 segmentRegister CS | DS | ES | FS | GS | SS
4973 specialRegister CR0 | CR2 | CR3
4974 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
4975 | TR3 | TR4 | TR5 | TR6 | TR7
4977 We simplify the grammar in obvious places (e.g., register parsing is
4978 done by calling parse_register) and eliminate immediate left recursion
4979 to implement a recursive-descent parser.
5019 /* Parsing structure for the intel syntax parser. Used to implement the
5020 semantic actions for the operand grammar. */
5021 struct intel_parser_s
5023 char *op_string
; /* The string being parsed. */
5024 int got_a_float
; /* Whether the operand is a float. */
5025 int op_modifier
; /* Operand modifier. */
5026 int is_mem
; /* 1 if operand is memory reference. */
5027 const reg_entry
*reg
; /* Last register reference found. */
5028 char *disp
; /* Displacement string being built. */
5031 static struct intel_parser_s intel_parser
;
5033 /* Token structure for parsing intel syntax. */
5036 int code
; /* Token code. */
5037 const reg_entry
*reg
; /* Register entry for register tokens. */
5038 char *str
; /* String representation. */
5041 static struct intel_token cur_token
, prev_token
;
5043 /* Token codes for the intel parser. Since T_SHORT is already used
5044 by COFF, undefine it first to prevent a warning. */
5059 /* Prototypes for intel parser functions. */
5060 static int intel_match_token
PARAMS ((int code
));
5061 static void intel_get_token
PARAMS ((void));
5062 static void intel_putback_token
PARAMS ((void));
5063 static int intel_expr
PARAMS ((void));
5064 static int intel_e05
PARAMS ((void));
5065 static int intel_e05_1
PARAMS ((void));
5066 static int intel_e06
PARAMS ((void));
5067 static int intel_e06_1
PARAMS ((void));
5068 static int intel_e09
PARAMS ((void));
5069 static int intel_e09_1
PARAMS ((void));
5070 static int intel_e10
PARAMS ((void));
5071 static int intel_e10_1
PARAMS ((void));
5072 static int intel_e11
PARAMS ((void));
5075 i386_intel_operand (operand_string
, got_a_float
)
5076 char *operand_string
;
5082 /* Initialize token holders. */
5083 cur_token
.code
= prev_token
.code
= T_NIL
;
5084 cur_token
.reg
= prev_token
.reg
= NULL
;
5085 cur_token
.str
= prev_token
.str
= NULL
;
5087 /* Initialize parser structure. */
5088 p
= intel_parser
.op_string
= (char *) malloc (strlen (operand_string
) + 1);
5091 strcpy (intel_parser
.op_string
, operand_string
);
5092 intel_parser
.got_a_float
= got_a_float
;
5093 intel_parser
.op_modifier
= -1;
5094 intel_parser
.is_mem
= 0;
5095 intel_parser
.reg
= NULL
;
5096 intel_parser
.disp
= (char *) malloc (strlen (operand_string
) + 1);
5097 if (intel_parser
.disp
== NULL
)
5099 intel_parser
.disp
[0] = '\0';
5101 /* Read the first token and start the parser. */
5103 ret
= intel_expr ();
5107 /* If we found a memory reference, hand it over to i386_displacement
5108 to fill in the rest of the operand fields. */
5109 if (intel_parser
.is_mem
)
5111 if ((i
.mem_operands
== 1
5112 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5113 || i
.mem_operands
== 2)
5115 as_bad (_("too many memory references for '%s'"),
5116 current_templates
->start
->name
);
5121 char *s
= intel_parser
.disp
;
5124 /* Add the displacement expression. */
5126 ret
= i386_displacement (s
, s
+ strlen (s
))
5127 && i386_index_check (s
);
5131 /* Constant and OFFSET expressions are handled by i386_immediate. */
5132 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5133 || intel_parser
.reg
== NULL
)
5134 ret
= i386_immediate (intel_parser
.disp
);
5138 free (intel_parser
.disp
);
5148 /* expr SHORT e05 */
5149 if (cur_token
.code
== T_SHORT
)
5151 intel_parser
.op_modifier
= SHORT
;
5152 intel_match_token (T_SHORT
);
5154 return (intel_e05 ());
5159 return intel_e05 ();
5169 return (intel_e06 () && intel_e05_1 ());
5175 /* e05' addOp e06 e05' */
5176 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5178 strcat (intel_parser
.disp
, cur_token
.str
);
5179 intel_match_token (cur_token
.code
);
5181 return (intel_e06 () && intel_e05_1 ());
5196 return (intel_e09 () && intel_e06_1 ());
5202 /* e06' mulOp e09 e06' */
5203 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5205 strcat (intel_parser
.disp
, cur_token
.str
);
5206 intel_match_token (cur_token
.code
);
5208 return (intel_e09 () && intel_e06_1 ());
5216 /* e09 OFFSET e10 e09'
5225 /* e09 OFFSET e10 e09' */
5226 if (cur_token
.code
== T_OFFSET
)
5228 intel_parser
.is_mem
= 0;
5229 intel_parser
.op_modifier
= OFFSET_FLAT
;
5230 intel_match_token (T_OFFSET
);
5232 return (intel_e10 () && intel_e09_1 ());
5237 return (intel_e10 () && intel_e09_1 ());
5243 /* e09' PTR e10 e09' */
5244 if (cur_token
.code
== T_PTR
)
5246 if (prev_token
.code
== T_BYTE
)
5247 i
.suffix
= BYTE_MNEM_SUFFIX
;
5249 else if (prev_token
.code
== T_WORD
)
5251 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5252 i
.suffix
= SHORT_MNEM_SUFFIX
;
5254 i
.suffix
= WORD_MNEM_SUFFIX
;
5257 else if (prev_token
.code
== T_DWORD
)
5259 if (intel_parser
.got_a_float
== 1) /* "f..." */
5260 i
.suffix
= SHORT_MNEM_SUFFIX
;
5262 i
.suffix
= LONG_MNEM_SUFFIX
;
5265 else if (prev_token
.code
== T_QWORD
)
5267 if (intel_parser
.got_a_float
== 1) /* "f..." */
5268 i
.suffix
= LONG_MNEM_SUFFIX
;
5270 i
.suffix
= QWORD_MNEM_SUFFIX
;
5273 else if (prev_token
.code
== T_XWORD
)
5274 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5278 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5282 intel_match_token (T_PTR
);
5284 return (intel_e10 () && intel_e09_1 ());
5287 /* e09 : e10 e09' */
5288 else if (cur_token
.code
== ':')
5290 /* Mark as a memory operand only if it's not already known to be an
5291 offset expression. */
5292 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5293 intel_parser
.is_mem
= 1;
5295 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5310 return (intel_e11 () && intel_e10_1 ());
5316 /* e10' [ expr ] e10' */
5317 if (cur_token
.code
== '[')
5319 intel_match_token ('[');
5321 /* Mark as a memory operand only if it's not already known to be an
5322 offset expression. If it's an offset expression, we need to keep
5324 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5325 intel_parser
.is_mem
= 1;
5327 strcat (intel_parser
.disp
, "[");
5329 /* Add a '+' to the displacement string if necessary. */
5330 if (*intel_parser
.disp
!= '\0'
5331 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5332 strcat (intel_parser
.disp
, "+");
5334 if (intel_expr () && intel_match_token (']'))
5336 /* Preserve brackets when the operand is an offset expression. */
5337 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5338 strcat (intel_parser
.disp
, "]");
5340 return intel_e10_1 ();
5367 if (cur_token
.code
== '(')
5369 intel_match_token ('(');
5370 strcat (intel_parser
.disp
, "(");
5372 if (intel_expr () && intel_match_token (')'))
5374 strcat (intel_parser
.disp
, ")");
5382 else if (cur_token
.code
== '[')
5384 intel_match_token ('[');
5386 /* Mark as a memory operand only if it's not already known to be an
5387 offset expression. If it's an offset expression, we need to keep
5389 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5390 intel_parser
.is_mem
= 1;
5392 strcat (intel_parser
.disp
, "[");
5394 /* Operands for jump/call inside brackets denote absolute addresses. */
5395 if (current_templates
->start
->opcode_modifier
& Jump
5396 || current_templates
->start
->opcode_modifier
& JumpDword
5397 || current_templates
->start
->opcode_modifier
& JumpByte
5398 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5399 i
.types
[this_operand
] |= JumpAbsolute
;
5401 /* Add a '+' to the displacement string if necessary. */
5402 if (*intel_parser
.disp
!= '\0'
5403 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5404 strcat (intel_parser
.disp
, "+");
5406 if (intel_expr () && intel_match_token (']'))
5408 /* Preserve brackets when the operand is an offset expression. */
5409 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5410 strcat (intel_parser
.disp
, "]");
5423 else if (cur_token
.code
== T_BYTE
5424 || cur_token
.code
== T_WORD
5425 || cur_token
.code
== T_DWORD
5426 || cur_token
.code
== T_QWORD
5427 || cur_token
.code
== T_XWORD
)
5429 intel_match_token (cur_token
.code
);
5436 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5438 strcat (intel_parser
.disp
, cur_token
.str
);
5439 intel_match_token (cur_token
.code
);
5441 /* Mark as a memory operand only if it's not already known to be an
5442 offset expression. */
5443 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5444 intel_parser
.is_mem
= 1;
5450 else if (cur_token
.code
== T_REG
)
5452 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5454 intel_match_token (T_REG
);
5456 /* Check for segment change. */
5457 if (cur_token
.code
== ':')
5459 if (reg
->reg_type
& (SReg2
| SReg3
))
5461 switch (reg
->reg_num
)
5464 i
.seg
[i
.mem_operands
] = &es
;
5467 i
.seg
[i
.mem_operands
] = &cs
;
5470 i
.seg
[i
.mem_operands
] = &ss
;
5473 i
.seg
[i
.mem_operands
] = &ds
;
5476 i
.seg
[i
.mem_operands
] = &fs
;
5479 i
.seg
[i
.mem_operands
] = &gs
;
5485 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5490 /* Not a segment register. Check for register scaling. */
5491 else if (cur_token
.code
== '*')
5493 if (!intel_parser
.is_mem
)
5495 as_bad (_("Register scaling only allowed in memory operands."));
5499 /* What follows must be a valid scale. */
5500 if (intel_match_token ('*')
5501 && strchr ("01248", *cur_token
.str
))
5504 i
.types
[this_operand
] |= BaseIndex
;
5506 /* Set the scale after setting the register (otherwise,
5507 i386_scale will complain) */
5508 i386_scale (cur_token
.str
);
5509 intel_match_token (T_CONST
);
5513 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5519 /* No scaling. If this is a memory operand, the register is either a
5520 base register (first occurrence) or an index register (second
5522 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5524 if (i
.base_reg
&& i
.index_reg
)
5526 as_bad (_("Too many register references in memory operand.\n"));
5530 if (i
.base_reg
== NULL
)
5535 i
.types
[this_operand
] |= BaseIndex
;
5538 /* Offset modifier. Add the register to the displacement string to be
5539 parsed as an immediate expression after we're done. */
5540 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5541 strcat (intel_parser
.disp
, reg
->reg_name
);
5543 /* It's neither base nor index nor offset. */
5546 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5547 i
.op
[this_operand
].regs
= reg
;
5551 /* Since registers are not part of the displacement string (except
5552 when we're parsing offset operands), we may need to remove any
5553 preceding '+' from the displacement string. */
5554 if (*intel_parser
.disp
!= '\0'
5555 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
5557 char *s
= intel_parser
.disp
;
5558 s
+= strlen (s
) - 1;
5567 else if (cur_token
.code
== T_ID
)
5569 /* Add the identifier to the displacement string. */
5570 strcat (intel_parser
.disp
, cur_token
.str
);
5571 intel_match_token (T_ID
);
5573 /* The identifier represents a memory reference only if it's not
5574 preceded by an offset modifier. */
5575 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5576 intel_parser
.is_mem
= 1;
5582 else if (cur_token
.code
== T_CONST
5583 || cur_token
.code
== '-'
5584 || cur_token
.code
== '+')
5588 /* Allow constants that start with `+' or `-'. */
5589 if (cur_token
.code
== '-' || cur_token
.code
== '+')
5591 strcat (intel_parser
.disp
, cur_token
.str
);
5592 intel_match_token (cur_token
.code
);
5593 if (cur_token
.code
!= T_CONST
)
5595 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5601 save_str
= (char *) malloc (strlen (cur_token
.str
) + 1);
5602 if (save_str
== NULL
)
5604 strcpy (save_str
, cur_token
.str
);
5606 /* Get the next token to check for register scaling. */
5607 intel_match_token (cur_token
.code
);
5609 /* Check if this constant is a scaling factor for an index register. */
5610 if (cur_token
.code
== '*')
5612 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
5614 if (!intel_parser
.is_mem
)
5616 as_bad (_("Register scaling only allowed in memory operands."));
5620 /* The constant is followed by `* reg', so it must be
5622 if (strchr ("01248", *save_str
))
5624 i
.index_reg
= cur_token
.reg
;
5625 i
.types
[this_operand
] |= BaseIndex
;
5627 /* Set the scale after setting the register (otherwise,
5628 i386_scale will complain) */
5629 i386_scale (save_str
);
5630 intel_match_token (T_REG
);
5632 /* Since registers are not part of the displacement
5633 string, we may need to remove any preceding '+' from
5634 the displacement string. */
5635 if (*intel_parser
.disp
!= '\0')
5637 char *s
= intel_parser
.disp
;
5638 s
+= strlen (s
) - 1;
5651 /* The constant was not used for register scaling. Since we have
5652 already consumed the token following `*' we now need to put it
5653 back in the stream. */
5655 intel_putback_token ();
5658 /* Add the constant to the displacement string. */
5659 strcat (intel_parser
.disp
, save_str
);
5665 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
5669 /* Match the given token against cur_token. If they match, read the next
5670 token from the operand string. */
5672 intel_match_token (code
)
5675 if (cur_token
.code
== code
)
5682 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
5687 /* Read a new token from intel_parser.op_string and store it in cur_token. */
5692 const reg_entry
*reg
;
5693 struct intel_token new_token
;
5695 new_token
.code
= T_NIL
;
5696 new_token
.reg
= NULL
;
5697 new_token
.str
= NULL
;
5699 /* Free the memory allocated to the previous token and move
5700 cur_token to prev_token. */
5702 free (prev_token
.str
);
5704 prev_token
= cur_token
;
5706 /* Skip whitespace. */
5707 while (is_space_char (*intel_parser
.op_string
))
5708 intel_parser
.op_string
++;
5710 /* Return an empty token if we find nothing else on the line. */
5711 if (*intel_parser
.op_string
== '\0')
5713 cur_token
= new_token
;
5717 /* The new token cannot be larger than the remainder of the operand
5719 new_token
.str
= (char *) malloc (strlen (intel_parser
.op_string
) + 1);
5720 if (new_token
.str
== NULL
)
5722 new_token
.str
[0] = '\0';
5724 if (strchr ("0123456789", *intel_parser
.op_string
))
5726 char *p
= new_token
.str
;
5727 char *q
= intel_parser
.op_string
;
5728 new_token
.code
= T_CONST
;
5730 /* Allow any kind of identifier char to encompass floating point and
5731 hexadecimal numbers. */
5732 while (is_identifier_char (*q
))
5736 /* Recognize special symbol names [0-9][bf]. */
5737 if (strlen (intel_parser
.op_string
) == 2
5738 && (intel_parser
.op_string
[1] == 'b'
5739 || intel_parser
.op_string
[1] == 'f'))
5740 new_token
.code
= T_ID
;
5743 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
5745 new_token
.code
= *intel_parser
.op_string
;
5746 new_token
.str
[0] = *intel_parser
.op_string
;
5747 new_token
.str
[1] = '\0';
5750 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5751 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
5753 new_token
.code
= T_REG
;
5754 new_token
.reg
= reg
;
5756 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
5758 new_token
.str
[0] = REGISTER_PREFIX
;
5759 new_token
.str
[1] = '\0';
5762 strcat (new_token
.str
, reg
->reg_name
);
5765 else if (is_identifier_char (*intel_parser
.op_string
))
5767 char *p
= new_token
.str
;
5768 char *q
= intel_parser
.op_string
;
5770 /* A '.' or '$' followed by an identifier char is an identifier.
5771 Otherwise, it's operator '.' followed by an expression. */
5772 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
5774 new_token
.code
= *q
;
5775 new_token
.str
[0] = *q
;
5776 new_token
.str
[1] = '\0';
5780 while (is_identifier_char (*q
) || *q
== '@')
5784 if (strcasecmp (new_token
.str
, "BYTE") == 0)
5785 new_token
.code
= T_BYTE
;
5787 else if (strcasecmp (new_token
.str
, "WORD") == 0)
5788 new_token
.code
= T_WORD
;
5790 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
5791 new_token
.code
= T_DWORD
;
5793 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
5794 new_token
.code
= T_QWORD
;
5796 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
5797 new_token
.code
= T_XWORD
;
5799 else if (strcasecmp (new_token
.str
, "PTR") == 0)
5800 new_token
.code
= T_PTR
;
5802 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
5803 new_token
.code
= T_SHORT
;
5805 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
5807 new_token
.code
= T_OFFSET
;
5809 /* ??? This is not mentioned in the MASM grammar but gcc
5810 makes use of it with -mintel-syntax. OFFSET may be
5811 followed by FLAT: */
5812 if (strncasecmp (q
, " FLAT:", 6) == 0)
5813 strcat (new_token
.str
, " FLAT:");
5816 /* ??? This is not mentioned in the MASM grammar. */
5817 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
5818 new_token
.code
= T_OFFSET
;
5821 new_token
.code
= T_ID
;
5826 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
5828 intel_parser
.op_string
+= strlen (new_token
.str
);
5829 cur_token
= new_token
;
5832 /* Put cur_token back into the token stream and make cur_token point to
5835 intel_putback_token ()
5837 intel_parser
.op_string
-= strlen (cur_token
.str
);
5838 free (cur_token
.str
);
5839 cur_token
= prev_token
;
5841 /* Forget prev_token. */
5842 prev_token
.code
= T_NIL
;
5843 prev_token
.reg
= NULL
;
5844 prev_token
.str
= NULL
;