1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
37 /* Default to compress debug sections for Linux. */
38 enum compressed_debug_section_type flag_compress_debug
39 = COMPRESS_DEBUG_GNU_ZLIB
;
42 #ifndef REGISTER_WARNINGS
43 #define REGISTER_WARNINGS 1
46 #ifndef INFER_ADDR_PREFIX
47 #define INFER_ADDR_PREFIX 1
51 #define DEFAULT_ARCH "i386"
56 #define INLINE __inline__
62 /* Prefixes will be emitted in the order defined below.
63 WAIT_PREFIX must be the first prefix since FWAIT is really is an
64 instruction, and so must come before any prefixes.
65 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
66 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
72 #define HLE_PREFIX REP_PREFIX
73 #define BND_PREFIX REP_PREFIX
75 #define REX_PREFIX 6 /* must come last. */
76 #define MAX_PREFIXES 7 /* max prefixes per opcode */
78 /* we define the syntax here (modulo base,index,scale syntax) */
79 #define REGISTER_PREFIX '%'
80 #define IMMEDIATE_PREFIX '$'
81 #define ABSOLUTE_PREFIX '*'
83 /* these are the instruction mnemonic suffixes in AT&T syntax or
84 memory operand size in Intel syntax. */
85 #define WORD_MNEM_SUFFIX 'w'
86 #define BYTE_MNEM_SUFFIX 'b'
87 #define SHORT_MNEM_SUFFIX 's'
88 #define LONG_MNEM_SUFFIX 'l'
89 #define QWORD_MNEM_SUFFIX 'q'
90 #define XMMWORD_MNEM_SUFFIX 'x'
91 #define YMMWORD_MNEM_SUFFIX 'y'
92 #define ZMMWORD_MNEM_SUFFIX 'z'
93 /* Intel Syntax. Use a non-ascii letter since since it never appears
95 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
97 #define END_OF_INSN '\0'
100 'templates' is for grouping together 'template' structures for opcodes
101 of the same name. This is only used for storing the insns in the grand
102 ole hash table of insns.
103 The templates themselves start at START and range up to (but not including)
108 const insn_template
*start
;
109 const insn_template
*end
;
113 /* 386 operand encoding bytes: see 386 book for details of this. */
116 unsigned int regmem
; /* codes register or memory operand */
117 unsigned int reg
; /* codes register operand (or extended opcode) */
118 unsigned int mode
; /* how to interpret regmem & reg */
122 /* x86-64 extension prefix. */
123 typedef int rex_byte
;
125 /* 386 opcode byte to code indirect addressing. */
134 /* x86 arch names, types and features */
137 const char *name
; /* arch name */
138 unsigned int len
; /* arch string length */
139 enum processor_type type
; /* arch type */
140 i386_cpu_flags flags
; /* cpu feature flags */
141 unsigned int skip
; /* show_arch should skip this. */
142 unsigned int negated
; /* turn off indicated flags. */
146 static void update_code_flag (int, int);
147 static void set_code_flag (int);
148 static void set_16bit_gcc_code_flag (int);
149 static void set_intel_syntax (int);
150 static void set_intel_mnemonic (int);
151 static void set_allow_index_reg (int);
152 static void set_check (int);
153 static void set_cpu_arch (int);
155 static void pe_directive_secrel (int);
157 static void signed_cons (int);
158 static char *output_invalid (int c
);
159 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
161 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
163 static int i386_att_operand (char *);
164 static int i386_intel_operand (char *, int);
165 static int i386_intel_simplify (expressionS
*);
166 static int i386_intel_parse_name (const char *, expressionS
*);
167 static const reg_entry
*parse_register (char *, char **);
168 static char *parse_insn (char *, char *);
169 static char *parse_operands (char *, const char *);
170 static void swap_operands (void);
171 static void swap_2_operands (int, int);
172 static void optimize_imm (void);
173 static void optimize_disp (void);
174 static const insn_template
*match_template (void);
175 static int check_string (void);
176 static int process_suffix (void);
177 static int check_byte_reg (void);
178 static int check_long_reg (void);
179 static int check_qword_reg (void);
180 static int check_word_reg (void);
181 static int finalize_imm (void);
182 static int process_operands (void);
183 static const seg_entry
*build_modrm_byte (void);
184 static void output_insn (void);
185 static void output_imm (fragS
*, offsetT
);
186 static void output_disp (fragS
*, offsetT
);
188 static void s_bss (int);
190 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
191 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
194 static const char *default_arch
= DEFAULT_ARCH
;
196 /* This struct describes rounding control and SAE in the instruction. */
210 static struct RC_Operation rc_op
;
212 /* The struct describes masking, applied to OPERAND in the instruction.
213 MASK is a pointer to the corresponding mask register. ZEROING tells
214 whether merging or zeroing mask is used. */
215 struct Mask_Operation
217 const reg_entry
*mask
;
218 unsigned int zeroing
;
219 /* The operand where this operation is associated. */
223 static struct Mask_Operation mask_op
;
225 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
227 struct Broadcast_Operation
229 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 /* Index of broadcasted operand. */
236 static struct Broadcast_Operation broadcast_op
;
241 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
242 unsigned char bytes
[4];
244 /* Destination or source register specifier. */
245 const reg_entry
*register_specifier
;
248 /* 'md_assemble ()' gathers together information and puts it into a
255 const reg_entry
*regs
;
260 operand_size_mismatch
,
261 operand_type_mismatch
,
262 register_type_mismatch
,
263 number_of_operands_mismatch
,
264 invalid_instruction_suffix
,
267 unsupported_with_intel_mnemonic
,
270 invalid_vsib_address
,
271 invalid_vector_register_set
,
272 unsupported_vector_index_register
,
273 unsupported_broadcast
,
274 broadcast_not_on_src_operand
,
277 mask_not_on_destination
,
280 rc_sae_operand_not_last_imm
,
281 invalid_register_operand
,
287 /* TM holds the template for the insn were currently assembling. */
290 /* SUFFIX holds the instruction size suffix for byte, word, dword
291 or qword, if given. */
294 /* OPERANDS gives the number of given operands. */
295 unsigned int operands
;
297 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
298 of given register, displacement, memory operands and immediate
300 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
302 /* TYPES [i] is the type (see above #defines) which tells us how to
303 use OP[i] for the corresponding operand. */
304 i386_operand_type types
[MAX_OPERANDS
];
306 /* Displacement expression, immediate expression, or register for each
308 union i386_op op
[MAX_OPERANDS
];
310 /* Flags for operands. */
311 unsigned int flags
[MAX_OPERANDS
];
312 #define Operand_PCrel 1
314 /* Relocation type for operand */
315 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
317 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
318 the base index byte below. */
319 const reg_entry
*base_reg
;
320 const reg_entry
*index_reg
;
321 unsigned int log2_scale_factor
;
323 /* SEG gives the seg_entries of this insn. They are zero unless
324 explicit segment overrides are given. */
325 const seg_entry
*seg
[2];
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes
;
330 unsigned char prefix
[MAX_PREFIXES
];
332 /* RM and SIB are the modrm byte and the sib byte where the
333 addressing modes of this insn are encoded. */
340 /* Masking attributes. */
341 struct Mask_Operation
*mask
;
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation
*rounding
;
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation
*broadcast
;
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift
;
352 /* Swap operand in encoding. */
353 unsigned int swap_operand
;
355 /* Prefer 8bit or 32bit displacement in encoding. */
358 disp_encoding_default
= 0,
364 const char *rep_prefix
;
367 const char *hle_prefix
;
369 /* Have BND prefix. */
370 const char *bnd_prefix
;
372 /* Need VREX to support upper 16 registers. */
376 enum i386_error error
;
379 typedef struct _i386_insn i386_insn
;
381 /* Link RC type with corresponding string, that'll be looked for in
390 static const struct RC_name RC_NamesTable
[] =
392 { rne
, STRING_COMMA_LEN ("rn-sae") },
393 { rd
, STRING_COMMA_LEN ("rd-sae") },
394 { ru
, STRING_COMMA_LEN ("ru-sae") },
395 { rz
, STRING_COMMA_LEN ("rz-sae") },
396 { saeonly
, STRING_COMMA_LEN ("sae") },
399 /* List of chars besides those in app.c:symbol_chars that can start an
400 operand. Used to prevent the scrubber eating vital white-space. */
401 const char extra_symbol_chars
[] = "*%-([{"
410 #if (defined (TE_I386AIX) \
411 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
412 && !defined (TE_GNU) \
413 && !defined (TE_LINUX) \
414 && !defined (TE_NACL) \
415 && !defined (TE_NETWARE) \
416 && !defined (TE_FreeBSD) \
417 && !defined (TE_DragonFly) \
418 && !defined (TE_NetBSD)))
419 /* This array holds the chars that always start a comment. If the
420 pre-processor is disabled, these aren't very useful. The option
421 --divide will remove '/' from this list. */
422 const char *i386_comment_chars
= "#/";
423 #define SVR4_COMMENT_CHARS 1
424 #define PREFIX_SEPARATOR '\\'
427 const char *i386_comment_chars
= "#";
428 #define PREFIX_SEPARATOR '/'
431 /* This array holds the chars that only start a comment at the beginning of
432 a line. If the line seems to have the form '# 123 filename'
433 .line and .file directives will appear in the pre-processed output.
434 Note that input_file.c hand checks for '#' at the beginning of the
435 first line of the input file. This is because the compiler outputs
436 #NO_APP at the beginning of its output.
437 Also note that comments started like this one will always work if
438 '/' isn't otherwise defined. */
439 const char line_comment_chars
[] = "#/";
441 const char line_separator_chars
[] = ";";
443 /* Chars that can be used to separate mant from exp in floating point
445 const char EXP_CHARS
[] = "eE";
447 /* Chars that mean this number is a floating point constant
450 const char FLT_CHARS
[] = "fFdDxX";
452 /* Tables for lexical analysis. */
453 static char mnemonic_chars
[256];
454 static char register_chars
[256];
455 static char operand_chars
[256];
456 static char identifier_chars
[256];
457 static char digit_chars
[256];
459 /* Lexical macros. */
460 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
461 #define is_operand_char(x) (operand_chars[(unsigned char) x])
462 #define is_register_char(x) (register_chars[(unsigned char) x])
463 #define is_space_char(x) ((x) == ' ')
464 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
465 #define is_digit_char(x) (digit_chars[(unsigned char) x])
467 /* All non-digit non-letter characters that may occur in an operand. */
468 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
470 /* md_assemble() always leaves the strings it's passed unaltered. To
471 effect this we maintain a stack of saved characters that we've smashed
472 with '\0's (indicating end of strings for various sub-fields of the
473 assembler instruction). */
474 static char save_stack
[32];
475 static char *save_stack_p
;
476 #define END_STRING_AND_SAVE(s) \
477 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
478 #define RESTORE_END_STRING(s) \
479 do { *(s) = *--save_stack_p; } while (0)
481 /* The instruction we're assembling. */
484 /* Possible templates for current insn. */
485 static const templates
*current_templates
;
487 /* Per instruction expressionS buffers: max displacements & immediates. */
488 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
489 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
491 /* Current operand we are working on. */
492 static int this_operand
= -1;
494 /* We support four different modes. FLAG_CODE variable is used to distinguish
502 static enum flag_code flag_code
;
503 static unsigned int object_64bit
;
504 static unsigned int disallow_64bit_reloc
;
505 static int use_rela_relocations
= 0;
507 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
508 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
509 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
511 /* The ELF ABI to use. */
519 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
522 #if defined (TE_PE) || defined (TE_PEP)
523 /* Use big object file format. */
524 static int use_big_obj
= 0;
527 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
528 /* 1 if generating code for a shared library. */
529 static int shared
= 0;
532 /* 1 for intel syntax,
534 static int intel_syntax
= 0;
536 /* 1 for intel mnemonic,
537 0 if att mnemonic. */
538 static int intel_mnemonic
= !SYSV386_COMPAT
;
540 /* 1 if support old (<= 2.8.1) versions of gcc. */
541 static int old_gcc
= OLDGCC_COMPAT
;
543 /* 1 if pseudo registers are permitted. */
544 static int allow_pseudo_reg
= 0;
546 /* 1 if register prefix % not required. */
547 static int allow_naked_reg
= 0;
549 /* 1 if the assembler should add BND prefix for all control-tranferring
550 instructions supporting it, even if this prefix wasn't specified
552 static int add_bnd_prefix
= 0;
554 /* 1 if pseudo index register, eiz/riz, is allowed . */
555 static int allow_index_reg
= 0;
557 /* 1 if the assembler should ignore LOCK prefix, even if it was
558 specified explicitly. */
559 static int omit_lock_prefix
= 0;
561 static enum check_kind
567 sse_check
, operand_check
= check_warning
;
569 /* Register prefix used for error message. */
570 static const char *register_prefix
= "%";
572 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
573 leave, push, and pop instructions so that gcc has the same stack
574 frame as in 32 bit mode. */
575 static char stackop_size
= '\0';
577 /* Non-zero to optimize code alignment. */
578 int optimize_align_code
= 1;
580 /* Non-zero to quieten some warnings. */
581 static int quiet_warnings
= 0;
584 static const char *cpu_arch_name
= NULL
;
585 static char *cpu_sub_arch_name
= NULL
;
587 /* CPU feature flags. */
588 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
590 /* If we have selected a cpu we are generating instructions for. */
591 static int cpu_arch_tune_set
= 0;
593 /* Cpu we are generating instructions for. */
594 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
596 /* CPU feature flags of cpu we are generating instructions for. */
597 static i386_cpu_flags cpu_arch_tune_flags
;
599 /* CPU instruction set architecture used. */
600 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
602 /* CPU feature flags of instruction set architecture used. */
603 i386_cpu_flags cpu_arch_isa_flags
;
605 /* If set, conditional jumps are not automatically promoted to handle
606 larger than a byte offset. */
607 static unsigned int no_cond_jump_promotion
= 0;
609 /* Encode SSE instructions with VEX prefix. */
610 static unsigned int sse2avx
;
612 /* Encode scalar AVX instructions with specific vector length. */
619 /* Encode scalar EVEX LIG instructions with specific vector length. */
627 /* Encode EVEX WIG instructions with specific evex.w. */
634 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
635 static enum rc_type evexrcig
= rne
;
637 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
638 static symbolS
*GOT_symbol
;
640 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
641 unsigned int x86_dwarf2_return_column
;
643 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
644 int x86_cie_data_alignment
;
646 /* Interface to relax_segment.
647 There are 3 major relax states for 386 jump insns because the
648 different types of jumps add different sizes to frags when we're
649 figuring out what sort of jump to choose to reach a given label. */
652 #define UNCOND_JUMP 0
654 #define COND_JUMP86 2
659 #define SMALL16 (SMALL | CODE16)
661 #define BIG16 (BIG | CODE16)
665 #define INLINE __inline__
671 #define ENCODE_RELAX_STATE(type, size) \
672 ((relax_substateT) (((type) << 2) | (size)))
673 #define TYPE_FROM_RELAX_STATE(s) \
675 #define DISP_SIZE_FROM_RELAX_STATE(s) \
676 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
678 /* This table is used by relax_frag to promote short jumps to long
679 ones where necessary. SMALL (short) jumps may be promoted to BIG
680 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
681 don't allow a short jump in a 32 bit code segment to be promoted to
682 a 16 bit offset jump because it's slower (requires data size
683 prefix), and doesn't work, unless the destination is in the bottom
684 64k of the code segment (The top 16 bits of eip are zeroed). */
686 const relax_typeS md_relax_table
[] =
689 1) most positive reach of this state,
690 2) most negative reach of this state,
691 3) how many bytes this mode will have in the variable part of the frag
692 4) which index into the table to try if we can't fit into this one. */
694 /* UNCOND_JUMP states. */
695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
696 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
697 /* dword jmp adds 4 bytes to frag:
698 0 extra opcode bytes, 4 displacement bytes. */
700 /* word jmp adds 2 byte2 to frag:
701 0 extra opcode bytes, 2 displacement bytes. */
704 /* COND_JUMP states. */
705 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
706 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
707 /* dword conditionals adds 5 bytes to frag:
708 1 extra opcode byte, 4 displacement bytes. */
710 /* word conditionals add 3 bytes to frag:
711 1 extra opcode byte, 2 displacement bytes. */
714 /* COND_JUMP86 states. */
715 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
716 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
717 /* dword conditionals adds 5 bytes to frag:
718 1 extra opcode byte, 4 displacement bytes. */
720 /* word conditionals add 4 bytes to frag:
721 1 displacement byte and a 3 byte long branch insn. */
725 static const arch_entry cpu_arch
[] =
727 /* Do not replace the first two entries - i386_target_format()
728 relies on them being there in this order. */
729 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
730 CPU_GENERIC32_FLAGS
, 0, 0 },
731 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
732 CPU_GENERIC64_FLAGS
, 0, 0 },
733 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
734 CPU_NONE_FLAGS
, 0, 0 },
735 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
736 CPU_I186_FLAGS
, 0, 0 },
737 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
738 CPU_I286_FLAGS
, 0, 0 },
739 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
740 CPU_I386_FLAGS
, 0, 0 },
741 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
742 CPU_I486_FLAGS
, 0, 0 },
743 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
744 CPU_I586_FLAGS
, 0, 0 },
745 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
746 CPU_I686_FLAGS
, 0, 0 },
747 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
748 CPU_I586_FLAGS
, 0, 0 },
749 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
750 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
751 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
752 CPU_P2_FLAGS
, 0, 0 },
753 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
754 CPU_P3_FLAGS
, 0, 0 },
755 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
756 CPU_P4_FLAGS
, 0, 0 },
757 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
758 CPU_CORE_FLAGS
, 0, 0 },
759 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
760 CPU_NOCONA_FLAGS
, 0, 0 },
761 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
762 CPU_CORE_FLAGS
, 1, 0 },
763 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
764 CPU_CORE_FLAGS
, 0, 0 },
765 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
766 CPU_CORE2_FLAGS
, 1, 0 },
767 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
768 CPU_CORE2_FLAGS
, 0, 0 },
769 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
770 CPU_COREI7_FLAGS
, 0, 0 },
771 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
772 CPU_L1OM_FLAGS
, 0, 0 },
773 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
774 CPU_K1OM_FLAGS
, 0, 0 },
775 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
776 CPU_IAMCU_FLAGS
, 0, 0 },
777 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
778 CPU_K6_FLAGS
, 0, 0 },
779 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
780 CPU_K6_2_FLAGS
, 0, 0 },
781 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
782 CPU_ATHLON_FLAGS
, 0, 0 },
783 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
784 CPU_K8_FLAGS
, 1, 0 },
785 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
786 CPU_K8_FLAGS
, 0, 0 },
787 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
788 CPU_K8_FLAGS
, 0, 0 },
789 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
790 CPU_AMDFAM10_FLAGS
, 0, 0 },
791 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
792 CPU_BDVER1_FLAGS
, 0, 0 },
793 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
794 CPU_BDVER2_FLAGS
, 0, 0 },
795 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
796 CPU_BDVER3_FLAGS
, 0, 0 },
797 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
798 CPU_BDVER4_FLAGS
, 0, 0 },
799 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
800 CPU_ZNVER1_FLAGS
, 0, 0 },
801 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
802 CPU_BTVER1_FLAGS
, 0, 0 },
803 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
804 CPU_BTVER2_FLAGS
, 0, 0 },
805 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
806 CPU_8087_FLAGS
, 0, 0 },
807 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
808 CPU_287_FLAGS
, 0, 0 },
809 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
810 CPU_387_FLAGS
, 0, 0 },
811 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
812 CPU_ANY87_FLAGS
, 0, 1 },
813 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
814 CPU_MMX_FLAGS
, 0, 0 },
815 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
816 CPU_3DNOWA_FLAGS
, 0, 1 },
817 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
818 CPU_SSE_FLAGS
, 0, 0 },
819 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
820 CPU_SSE2_FLAGS
, 0, 0 },
821 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
822 CPU_SSE3_FLAGS
, 0, 0 },
823 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
824 CPU_SSSE3_FLAGS
, 0, 0 },
825 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
826 CPU_SSE4_1_FLAGS
, 0, 0 },
827 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
828 CPU_SSE4_2_FLAGS
, 0, 0 },
829 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
830 CPU_SSE4_2_FLAGS
, 0, 0 },
831 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
832 CPU_ANY_SSE_FLAGS
, 0, 1 },
833 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
834 CPU_AVX_FLAGS
, 0, 0 },
835 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
836 CPU_AVX2_FLAGS
, 0, 0 },
837 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
838 CPU_AVX512F_FLAGS
, 0, 0 },
839 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
840 CPU_AVX512CD_FLAGS
, 0, 0 },
841 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
842 CPU_AVX512ER_FLAGS
, 0, 0 },
843 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
844 CPU_AVX512PF_FLAGS
, 0, 0 },
845 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
846 CPU_AVX512DQ_FLAGS
, 0, 0 },
847 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
848 CPU_AVX512BW_FLAGS
, 0, 0 },
849 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
850 CPU_AVX512VL_FLAGS
, 0, 0 },
851 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
852 CPU_ANY_AVX_FLAGS
, 0, 1 },
853 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
854 CPU_VMX_FLAGS
, 0, 0 },
855 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
856 CPU_VMFUNC_FLAGS
, 0, 0 },
857 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
858 CPU_SMX_FLAGS
, 0, 0 },
859 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
860 CPU_XSAVE_FLAGS
, 0, 0 },
861 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
862 CPU_XSAVEOPT_FLAGS
, 0, 0 },
863 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
864 CPU_XSAVEC_FLAGS
, 0, 0 },
865 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
866 CPU_XSAVES_FLAGS
, 0, 0 },
867 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
868 CPU_AES_FLAGS
, 0, 0 },
869 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
870 CPU_PCLMUL_FLAGS
, 0, 0 },
871 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
872 CPU_PCLMUL_FLAGS
, 1, 0 },
873 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
874 CPU_FSGSBASE_FLAGS
, 0, 0 },
875 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
876 CPU_RDRND_FLAGS
, 0, 0 },
877 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
878 CPU_F16C_FLAGS
, 0, 0 },
879 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
880 CPU_BMI2_FLAGS
, 0, 0 },
881 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
882 CPU_FMA_FLAGS
, 0, 0 },
883 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
884 CPU_FMA4_FLAGS
, 0, 0 },
885 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
886 CPU_XOP_FLAGS
, 0, 0 },
887 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
888 CPU_LWP_FLAGS
, 0, 0 },
889 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
890 CPU_MOVBE_FLAGS
, 0, 0 },
891 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
892 CPU_CX16_FLAGS
, 0, 0 },
893 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
894 CPU_EPT_FLAGS
, 0, 0 },
895 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
896 CPU_LZCNT_FLAGS
, 0, 0 },
897 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
898 CPU_HLE_FLAGS
, 0, 0 },
899 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
900 CPU_RTM_FLAGS
, 0, 0 },
901 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
902 CPU_INVPCID_FLAGS
, 0, 0 },
903 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
904 CPU_CLFLUSH_FLAGS
, 0, 0 },
905 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
906 CPU_NOP_FLAGS
, 0, 0 },
907 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
908 CPU_SYSCALL_FLAGS
, 0, 0 },
909 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
910 CPU_RDTSCP_FLAGS
, 0, 0 },
911 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
912 CPU_3DNOW_FLAGS
, 0, 0 },
913 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
914 CPU_3DNOWA_FLAGS
, 0, 0 },
915 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
916 CPU_PADLOCK_FLAGS
, 0, 0 },
917 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
918 CPU_SVME_FLAGS
, 1, 0 },
919 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
920 CPU_SVME_FLAGS
, 0, 0 },
921 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
922 CPU_SSE4A_FLAGS
, 0, 0 },
923 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
924 CPU_ABM_FLAGS
, 0, 0 },
925 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
926 CPU_BMI_FLAGS
, 0, 0 },
927 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
928 CPU_TBM_FLAGS
, 0, 0 },
929 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
930 CPU_ADX_FLAGS
, 0, 0 },
931 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
932 CPU_RDSEED_FLAGS
, 0, 0 },
933 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
934 CPU_PRFCHW_FLAGS
, 0, 0 },
935 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
936 CPU_SMAP_FLAGS
, 0, 0 },
937 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
938 CPU_MPX_FLAGS
, 0, 0 },
939 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
940 CPU_SHA_FLAGS
, 0, 0 },
941 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
942 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
943 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
944 CPU_PREFETCHWT1_FLAGS
, 0, 0 },
945 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
946 CPU_SE1_FLAGS
, 0, 0 },
947 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
948 CPU_CLWB_FLAGS
, 0, 0 },
949 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
950 CPU_PCOMMIT_FLAGS
, 0, 0 },
951 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
952 CPU_AVX512IFMA_FLAGS
, 0, 0 },
953 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
954 CPU_AVX512VBMI_FLAGS
, 0, 0 },
955 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
956 CPU_CLZERO_FLAGS
, 0, 0 },
957 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
958 CPU_MWAITX_FLAGS
, 0, 0 },
962 /* Like s_lcomm_internal in gas/read.c but the alignment string
963 is allowed to be optional. */
966 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
973 && *input_line_pointer
== ',')
975 align
= parse_align (needs_align
- 1);
977 if (align
== (addressT
) -1)
992 bss_alloc (symbolP
, size
, align
);
997 pe_lcomm (int needs_align
)
999 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1003 const pseudo_typeS md_pseudo_table
[] =
1005 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1006 {"align", s_align_bytes
, 0},
1008 {"align", s_align_ptwo
, 0},
1010 {"arch", set_cpu_arch
, 0},
1014 {"lcomm", pe_lcomm
, 1},
1016 {"ffloat", float_cons
, 'f'},
1017 {"dfloat", float_cons
, 'd'},
1018 {"tfloat", float_cons
, 'x'},
1020 {"slong", signed_cons
, 4},
1021 {"noopt", s_ignore
, 0},
1022 {"optim", s_ignore
, 0},
1023 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1024 {"code16", set_code_flag
, CODE_16BIT
},
1025 {"code32", set_code_flag
, CODE_32BIT
},
1026 {"code64", set_code_flag
, CODE_64BIT
},
1027 {"intel_syntax", set_intel_syntax
, 1},
1028 {"att_syntax", set_intel_syntax
, 0},
1029 {"intel_mnemonic", set_intel_mnemonic
, 1},
1030 {"att_mnemonic", set_intel_mnemonic
, 0},
1031 {"allow_index_reg", set_allow_index_reg
, 1},
1032 {"disallow_index_reg", set_allow_index_reg
, 0},
1033 {"sse_check", set_check
, 0},
1034 {"operand_check", set_check
, 1},
1035 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1036 {"largecomm", handle_large_common
, 0},
1038 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1039 {"loc", dwarf2_directive_loc
, 0},
1040 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1043 {"secrel32", pe_directive_secrel
, 0},
1048 /* For interface with expression (). */
1049 extern char *input_line_pointer
;
1051 /* Hash table for instruction mnemonic lookup. */
1052 static struct hash_control
*op_hash
;
1054 /* Hash table for register lookup. */
1055 static struct hash_control
*reg_hash
;
1058 i386_align_code (fragS
*fragP
, int count
)
1060 /* Various efficient no-op patterns for aligning code labels.
1061 Note: Don't try to assemble the instructions in the comments.
1062 0L and 0w are not legal. */
1063 static const char f32_1
[] =
1065 static const char f32_2
[] =
1066 {0x66,0x90}; /* xchg %ax,%ax */
1067 static const char f32_3
[] =
1068 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1069 static const char f32_4
[] =
1070 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1071 static const char f32_5
[] =
1073 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1074 static const char f32_6
[] =
1075 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1076 static const char f32_7
[] =
1077 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1078 static const char f32_8
[] =
1080 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1081 static const char f32_9
[] =
1082 {0x89,0xf6, /* movl %esi,%esi */
1083 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1084 static const char f32_10
[] =
1085 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1086 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1087 static const char f32_11
[] =
1088 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1089 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1090 static const char f32_12
[] =
1091 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1092 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1093 static const char f32_13
[] =
1094 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1095 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1096 static const char f32_14
[] =
1097 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1098 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1099 static const char f16_3
[] =
1100 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1101 static const char f16_4
[] =
1102 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1103 static const char f16_5
[] =
1105 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1106 static const char f16_6
[] =
1107 {0x89,0xf6, /* mov %si,%si */
1108 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1109 static const char f16_7
[] =
1110 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1111 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1112 static const char f16_8
[] =
1113 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1114 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1115 static const char jump_31
[] =
1116 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1117 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1118 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1119 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1120 static const char *const f32_patt
[] = {
1121 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1122 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1124 static const char *const f16_patt
[] = {
1125 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1127 /* nopl (%[re]ax) */
1128 static const char alt_3
[] =
1130 /* nopl 0(%[re]ax) */
1131 static const char alt_4
[] =
1132 {0x0f,0x1f,0x40,0x00};
1133 /* nopl 0(%[re]ax,%[re]ax,1) */
1134 static const char alt_5
[] =
1135 {0x0f,0x1f,0x44,0x00,0x00};
1136 /* nopw 0(%[re]ax,%[re]ax,1) */
1137 static const char alt_6
[] =
1138 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1139 /* nopl 0L(%[re]ax) */
1140 static const char alt_7
[] =
1141 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1142 /* nopl 0L(%[re]ax,%[re]ax,1) */
1143 static const char alt_8
[] =
1144 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1145 /* nopw 0L(%[re]ax,%[re]ax,1) */
1146 static const char alt_9
[] =
1147 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1148 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1149 static const char alt_10
[] =
1150 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1151 static const char *const alt_patt
[] = {
1152 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1156 /* Only align for at least a positive non-zero boundary. */
1157 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1160 /* We need to decide which NOP sequence to use for 32bit and
1161 64bit. When -mtune= is used:
1163 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1164 PROCESSOR_GENERIC32, f32_patt will be used.
1165 2. For the rest, alt_patt will be used.
1167 When -mtune= isn't used, alt_patt will be used if
1168 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1171 When -march= or .arch is used, we can't use anything beyond
1172 cpu_arch_isa_flags. */
1174 if (flag_code
== CODE_16BIT
)
1178 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1180 /* Adjust jump offset. */
1181 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1184 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1185 f16_patt
[count
- 1], count
);
1189 const char *const *patt
= NULL
;
1191 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1193 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1194 switch (cpu_arch_tune
)
1196 case PROCESSOR_UNKNOWN
:
1197 /* We use cpu_arch_isa_flags to check if we SHOULD
1198 optimize with nops. */
1199 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1204 case PROCESSOR_PENTIUM4
:
1205 case PROCESSOR_NOCONA
:
1206 case PROCESSOR_CORE
:
1207 case PROCESSOR_CORE2
:
1208 case PROCESSOR_COREI7
:
1209 case PROCESSOR_L1OM
:
1210 case PROCESSOR_K1OM
:
1211 case PROCESSOR_GENERIC64
:
1213 case PROCESSOR_ATHLON
:
1215 case PROCESSOR_AMDFAM10
:
1217 case PROCESSOR_ZNVER
:
1221 case PROCESSOR_I386
:
1222 case PROCESSOR_I486
:
1223 case PROCESSOR_PENTIUM
:
1224 case PROCESSOR_PENTIUMPRO
:
1225 case PROCESSOR_IAMCU
:
1226 case PROCESSOR_GENERIC32
:
1233 switch (fragP
->tc_frag_data
.tune
)
1235 case PROCESSOR_UNKNOWN
:
1236 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1237 PROCESSOR_UNKNOWN. */
1241 case PROCESSOR_I386
:
1242 case PROCESSOR_I486
:
1243 case PROCESSOR_PENTIUM
:
1244 case PROCESSOR_IAMCU
:
1246 case PROCESSOR_ATHLON
:
1248 case PROCESSOR_AMDFAM10
:
1250 case PROCESSOR_ZNVER
:
1252 case PROCESSOR_GENERIC32
:
1253 /* We use cpu_arch_isa_flags to check if we CAN optimize
1255 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1260 case PROCESSOR_PENTIUMPRO
:
1261 case PROCESSOR_PENTIUM4
:
1262 case PROCESSOR_NOCONA
:
1263 case PROCESSOR_CORE
:
1264 case PROCESSOR_CORE2
:
1265 case PROCESSOR_COREI7
:
1266 case PROCESSOR_L1OM
:
1267 case PROCESSOR_K1OM
:
1268 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1273 case PROCESSOR_GENERIC64
:
1279 if (patt
== f32_patt
)
1281 /* If the padding is less than 15 bytes, we use the normal
1282 ones. Otherwise, we use a jump instruction and adjust
1286 /* For 64bit, the limit is 3 bytes. */
1287 if (flag_code
== CODE_64BIT
1288 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1293 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1294 patt
[count
- 1], count
);
1297 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1299 /* Adjust jump offset. */
1300 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1305 /* Maximum length of an instruction is 10 byte. If the
1306 padding is greater than 10 bytes and we don't use jump,
1307 we have to break it into smaller pieces. */
1308 int padding
= count
;
1309 while (padding
> 10)
1312 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1317 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1318 patt
[padding
- 1], padding
);
1321 fragP
->fr_var
= count
;
1325 operand_type_all_zero (const union i386_operand_type
*x
)
1327 switch (ARRAY_SIZE(x
->array
))
1336 return !x
->array
[0];
1343 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1345 switch (ARRAY_SIZE(x
->array
))
1360 operand_type_equal (const union i386_operand_type
*x
,
1361 const union i386_operand_type
*y
)
1363 switch (ARRAY_SIZE(x
->array
))
1366 if (x
->array
[2] != y
->array
[2])
1369 if (x
->array
[1] != y
->array
[1])
1372 return x
->array
[0] == y
->array
[0];
1380 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1382 switch (ARRAY_SIZE(x
->array
))
1391 return !x
->array
[0];
1398 cpu_flags_equal (const union i386_cpu_flags
*x
,
1399 const union i386_cpu_flags
*y
)
1401 switch (ARRAY_SIZE(x
->array
))
1404 if (x
->array
[2] != y
->array
[2])
1407 if (x
->array
[1] != y
->array
[1])
1410 return x
->array
[0] == y
->array
[0];
1418 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1420 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1421 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1424 static INLINE i386_cpu_flags
1425 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1427 switch (ARRAY_SIZE (x
.array
))
1430 x
.array
[2] &= y
.array
[2];
1432 x
.array
[1] &= y
.array
[1];
1434 x
.array
[0] &= y
.array
[0];
1442 static INLINE i386_cpu_flags
1443 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1445 switch (ARRAY_SIZE (x
.array
))
1448 x
.array
[2] |= y
.array
[2];
1450 x
.array
[1] |= y
.array
[1];
1452 x
.array
[0] |= y
.array
[0];
1460 static INLINE i386_cpu_flags
1461 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1463 switch (ARRAY_SIZE (x
.array
))
1466 x
.array
[2] &= ~y
.array
[2];
1468 x
.array
[1] &= ~y
.array
[1];
1470 x
.array
[0] &= ~y
.array
[0];
1479 valid_iamcu_cpu_flags (const i386_cpu_flags
*flags
)
1481 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
1483 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_COMPAT_FLAGS
;
1484 i386_cpu_flags compat_flags
;
1485 compat_flags
= cpu_flags_and_not (*flags
, iamcu_flags
);
1486 return cpu_flags_all_zero (&compat_flags
);
1492 #define CPU_FLAGS_ARCH_MATCH 0x1
1493 #define CPU_FLAGS_64BIT_MATCH 0x2
1494 #define CPU_FLAGS_AES_MATCH 0x4
1495 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1496 #define CPU_FLAGS_AVX_MATCH 0x10
1498 #define CPU_FLAGS_32BIT_MATCH \
1499 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1500 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1501 #define CPU_FLAGS_PERFECT_MATCH \
1502 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1504 /* Return CPU flags match bits. */
1507 cpu_flags_match (const insn_template
*t
)
1509 i386_cpu_flags x
= t
->cpu_flags
;
1510 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1512 x
.bitfield
.cpu64
= 0;
1513 x
.bitfield
.cpuno64
= 0;
1515 if (cpu_flags_all_zero (&x
))
1517 /* This instruction is available on all archs. */
1518 match
|= CPU_FLAGS_32BIT_MATCH
;
1522 /* This instruction is available only on some archs. */
1523 i386_cpu_flags cpu
= cpu_arch_flags
;
1525 cpu
.bitfield
.cpu64
= 0;
1526 cpu
.bitfield
.cpuno64
= 0;
1527 cpu
= cpu_flags_and (x
, cpu
);
1528 if (!cpu_flags_all_zero (&cpu
))
1530 if (x
.bitfield
.cpuavx
)
1532 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1533 if (cpu
.bitfield
.cpuavx
)
1535 /* Check SSE2AVX. */
1536 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1538 match
|= (CPU_FLAGS_ARCH_MATCH
1539 | CPU_FLAGS_AVX_MATCH
);
1541 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1542 match
|= CPU_FLAGS_AES_MATCH
;
1544 if (!x
.bitfield
.cpupclmul
1545 || cpu
.bitfield
.cpupclmul
)
1546 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1550 match
|= CPU_FLAGS_ARCH_MATCH
;
1553 match
|= CPU_FLAGS_32BIT_MATCH
;
1559 static INLINE i386_operand_type
1560 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1562 switch (ARRAY_SIZE (x
.array
))
1565 x
.array
[2] &= y
.array
[2];
1567 x
.array
[1] &= y
.array
[1];
1569 x
.array
[0] &= y
.array
[0];
1577 static INLINE i386_operand_type
1578 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1580 switch (ARRAY_SIZE (x
.array
))
1583 x
.array
[2] |= y
.array
[2];
1585 x
.array
[1] |= y
.array
[1];
1587 x
.array
[0] |= y
.array
[0];
1595 static INLINE i386_operand_type
1596 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1598 switch (ARRAY_SIZE (x
.array
))
1601 x
.array
[2] ^= y
.array
[2];
1603 x
.array
[1] ^= y
.array
[1];
1605 x
.array
[0] ^= y
.array
[0];
1613 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1614 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1615 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1616 static const i386_operand_type inoutportreg
1617 = OPERAND_TYPE_INOUTPORTREG
;
1618 static const i386_operand_type reg16_inoutportreg
1619 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1620 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1621 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1622 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1623 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1624 static const i386_operand_type anydisp
1625 = OPERAND_TYPE_ANYDISP
;
1626 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1627 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1628 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1629 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1630 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1631 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1632 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1633 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1634 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1635 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1636 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1637 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1638 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1639 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1650 operand_type_check (i386_operand_type t
, enum operand_type c
)
1655 return (t
.bitfield
.reg8
1658 || t
.bitfield
.reg64
);
1661 return (t
.bitfield
.imm8
1665 || t
.bitfield
.imm32s
1666 || t
.bitfield
.imm64
);
1669 return (t
.bitfield
.disp8
1670 || t
.bitfield
.disp16
1671 || t
.bitfield
.disp32
1672 || t
.bitfield
.disp32s
1673 || t
.bitfield
.disp64
);
1676 return (t
.bitfield
.disp8
1677 || t
.bitfield
.disp16
1678 || t
.bitfield
.disp32
1679 || t
.bitfield
.disp32s
1680 || t
.bitfield
.disp64
1681 || t
.bitfield
.baseindex
);
1690 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1691 operand J for instruction template T. */
1694 match_reg_size (const insn_template
*t
, unsigned int j
)
1696 return !((i
.types
[j
].bitfield
.byte
1697 && !t
->operand_types
[j
].bitfield
.byte
)
1698 || (i
.types
[j
].bitfield
.word
1699 && !t
->operand_types
[j
].bitfield
.word
)
1700 || (i
.types
[j
].bitfield
.dword
1701 && !t
->operand_types
[j
].bitfield
.dword
)
1702 || (i
.types
[j
].bitfield
.qword
1703 && !t
->operand_types
[j
].bitfield
.qword
));
1706 /* Return 1 if there is no conflict in any size on operand J for
1707 instruction template T. */
1710 match_mem_size (const insn_template
*t
, unsigned int j
)
1712 return (match_reg_size (t
, j
)
1713 && !((i
.types
[j
].bitfield
.unspecified
1715 && !t
->operand_types
[j
].bitfield
.unspecified
)
1716 || (i
.types
[j
].bitfield
.fword
1717 && !t
->operand_types
[j
].bitfield
.fword
)
1718 || (i
.types
[j
].bitfield
.tbyte
1719 && !t
->operand_types
[j
].bitfield
.tbyte
)
1720 || (i
.types
[j
].bitfield
.xmmword
1721 && !t
->operand_types
[j
].bitfield
.xmmword
)
1722 || (i
.types
[j
].bitfield
.ymmword
1723 && !t
->operand_types
[j
].bitfield
.ymmword
)
1724 || (i
.types
[j
].bitfield
.zmmword
1725 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1728 /* Return 1 if there is no size conflict on any operands for
1729 instruction template T. */
1732 operand_size_match (const insn_template
*t
)
1737 /* Don't check jump instructions. */
1738 if (t
->opcode_modifier
.jump
1739 || t
->opcode_modifier
.jumpbyte
1740 || t
->opcode_modifier
.jumpdword
1741 || t
->opcode_modifier
.jumpintersegment
)
1744 /* Check memory and accumulator operand size. */
1745 for (j
= 0; j
< i
.operands
; j
++)
1747 if (t
->operand_types
[j
].bitfield
.anysize
)
1750 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1756 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1765 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1768 i
.error
= operand_size_mismatch
;
1772 /* Check reverse. */
1773 gas_assert (i
.operands
== 2);
1776 for (j
= 0; j
< 2; j
++)
1778 if (t
->operand_types
[j
].bitfield
.acc
1779 && !match_reg_size (t
, j
? 0 : 1))
1782 if (i
.types
[j
].bitfield
.mem
1783 && !match_mem_size (t
, j
? 0 : 1))
1791 operand_type_match (i386_operand_type overlap
,
1792 i386_operand_type given
)
1794 i386_operand_type temp
= overlap
;
1796 temp
.bitfield
.jumpabsolute
= 0;
1797 temp
.bitfield
.unspecified
= 0;
1798 temp
.bitfield
.byte
= 0;
1799 temp
.bitfield
.word
= 0;
1800 temp
.bitfield
.dword
= 0;
1801 temp
.bitfield
.fword
= 0;
1802 temp
.bitfield
.qword
= 0;
1803 temp
.bitfield
.tbyte
= 0;
1804 temp
.bitfield
.xmmword
= 0;
1805 temp
.bitfield
.ymmword
= 0;
1806 temp
.bitfield
.zmmword
= 0;
1807 if (operand_type_all_zero (&temp
))
1810 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1811 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1815 i
.error
= operand_type_mismatch
;
1819 /* If given types g0 and g1 are registers they must be of the same type
1820 unless the expected operand type register overlap is null.
1821 Note that Acc in a template matches every size of reg. */
1824 operand_type_register_match (i386_operand_type m0
,
1825 i386_operand_type g0
,
1826 i386_operand_type t0
,
1827 i386_operand_type m1
,
1828 i386_operand_type g1
,
1829 i386_operand_type t1
)
1831 if (!operand_type_check (g0
, reg
))
1834 if (!operand_type_check (g1
, reg
))
1837 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1838 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1839 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1840 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1843 if (m0
.bitfield
.acc
)
1845 t0
.bitfield
.reg8
= 1;
1846 t0
.bitfield
.reg16
= 1;
1847 t0
.bitfield
.reg32
= 1;
1848 t0
.bitfield
.reg64
= 1;
1851 if (m1
.bitfield
.acc
)
1853 t1
.bitfield
.reg8
= 1;
1854 t1
.bitfield
.reg16
= 1;
1855 t1
.bitfield
.reg32
= 1;
1856 t1
.bitfield
.reg64
= 1;
1859 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1860 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1861 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1862 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1865 i
.error
= register_type_mismatch
;
1870 static INLINE
unsigned int
1871 register_number (const reg_entry
*r
)
1873 unsigned int nr
= r
->reg_num
;
1875 if (r
->reg_flags
& RegRex
)
1881 static INLINE
unsigned int
1882 mode_from_disp_size (i386_operand_type t
)
1884 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1886 else if (t
.bitfield
.disp16
1887 || t
.bitfield
.disp32
1888 || t
.bitfield
.disp32s
)
1895 fits_in_signed_byte (addressT num
)
1897 return num
+ 0x80 <= 0xff;
1901 fits_in_unsigned_byte (addressT num
)
1907 fits_in_unsigned_word (addressT num
)
1909 return num
<= 0xffff;
1913 fits_in_signed_word (addressT num
)
1915 return num
+ 0x8000 <= 0xffff;
1919 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1924 return num
+ 0x80000000 <= 0xffffffff;
1926 } /* fits_in_signed_long() */
1929 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
1934 return num
<= 0xffffffff;
1936 } /* fits_in_unsigned_long() */
1939 fits_in_vec_disp8 (offsetT num
)
1941 int shift
= i
.memshift
;
1947 mask
= (1 << shift
) - 1;
1949 /* Return 0 if NUM isn't properly aligned. */
1953 /* Check if NUM will fit in 8bit after shift. */
1954 return fits_in_signed_byte (num
>> shift
);
1958 fits_in_imm4 (offsetT num
)
1960 return (num
& 0xf) == num
;
1963 static i386_operand_type
1964 smallest_imm_type (offsetT num
)
1966 i386_operand_type t
;
1968 operand_type_set (&t
, 0);
1969 t
.bitfield
.imm64
= 1;
1971 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1973 /* This code is disabled on the 486 because all the Imm1 forms
1974 in the opcode table are slower on the i486. They're the
1975 versions with the implicitly specified single-position
1976 displacement, which has another syntax if you really want to
1978 t
.bitfield
.imm1
= 1;
1979 t
.bitfield
.imm8
= 1;
1980 t
.bitfield
.imm8s
= 1;
1981 t
.bitfield
.imm16
= 1;
1982 t
.bitfield
.imm32
= 1;
1983 t
.bitfield
.imm32s
= 1;
1985 else if (fits_in_signed_byte (num
))
1987 t
.bitfield
.imm8
= 1;
1988 t
.bitfield
.imm8s
= 1;
1989 t
.bitfield
.imm16
= 1;
1990 t
.bitfield
.imm32
= 1;
1991 t
.bitfield
.imm32s
= 1;
1993 else if (fits_in_unsigned_byte (num
))
1995 t
.bitfield
.imm8
= 1;
1996 t
.bitfield
.imm16
= 1;
1997 t
.bitfield
.imm32
= 1;
1998 t
.bitfield
.imm32s
= 1;
2000 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2002 t
.bitfield
.imm16
= 1;
2003 t
.bitfield
.imm32
= 1;
2004 t
.bitfield
.imm32s
= 1;
2006 else if (fits_in_signed_long (num
))
2008 t
.bitfield
.imm32
= 1;
2009 t
.bitfield
.imm32s
= 1;
2011 else if (fits_in_unsigned_long (num
))
2012 t
.bitfield
.imm32
= 1;
2018 offset_in_range (offsetT val
, int size
)
2024 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2025 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2026 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2028 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2034 /* If BFD64, sign extend val for 32bit address mode. */
2035 if (flag_code
!= CODE_64BIT
2036 || i
.prefix
[ADDR_PREFIX
])
2037 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2038 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2041 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2043 char buf1
[40], buf2
[40];
2045 sprint_value (buf1
, val
);
2046 sprint_value (buf2
, val
& mask
);
2047 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2061 a. PREFIX_EXIST if attempting to add a prefix where one from the
2062 same class already exists.
2063 b. PREFIX_LOCK if lock prefix is added.
2064 c. PREFIX_REP if rep/repne prefix is added.
2065 d. PREFIX_OTHER if other prefix is added.
2068 static enum PREFIX_GROUP
2069 add_prefix (unsigned int prefix
)
2071 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2074 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2075 && flag_code
== CODE_64BIT
)
2077 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2078 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2079 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2090 case CS_PREFIX_OPCODE
:
2091 case DS_PREFIX_OPCODE
:
2092 case ES_PREFIX_OPCODE
:
2093 case FS_PREFIX_OPCODE
:
2094 case GS_PREFIX_OPCODE
:
2095 case SS_PREFIX_OPCODE
:
2099 case REPNE_PREFIX_OPCODE
:
2100 case REPE_PREFIX_OPCODE
:
2105 case LOCK_PREFIX_OPCODE
:
2114 case ADDR_PREFIX_OPCODE
:
2118 case DATA_PREFIX_OPCODE
:
2122 if (i
.prefix
[q
] != 0)
2130 i
.prefix
[q
] |= prefix
;
2133 as_bad (_("same type of prefix used twice"));
2139 update_code_flag (int value
, int check
)
2141 PRINTF_LIKE ((*as_error
));
2143 flag_code
= (enum flag_code
) value
;
2144 if (flag_code
== CODE_64BIT
)
2146 cpu_arch_flags
.bitfield
.cpu64
= 1;
2147 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2151 cpu_arch_flags
.bitfield
.cpu64
= 0;
2152 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2154 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2157 as_error
= as_fatal
;
2160 (*as_error
) (_("64bit mode not supported on `%s'."),
2161 cpu_arch_name
? cpu_arch_name
: default_arch
);
2163 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2166 as_error
= as_fatal
;
2169 (*as_error
) (_("32bit mode not supported on `%s'."),
2170 cpu_arch_name
? cpu_arch_name
: default_arch
);
2172 stackop_size
= '\0';
2176 set_code_flag (int value
)
2178 update_code_flag (value
, 0);
2182 set_16bit_gcc_code_flag (int new_code_flag
)
2184 flag_code
= (enum flag_code
) new_code_flag
;
2185 if (flag_code
!= CODE_16BIT
)
2187 cpu_arch_flags
.bitfield
.cpu64
= 0;
2188 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2189 stackop_size
= LONG_MNEM_SUFFIX
;
2193 set_intel_syntax (int syntax_flag
)
2195 /* Find out if register prefixing is specified. */
2196 int ask_naked_reg
= 0;
2199 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2201 char *string
= input_line_pointer
;
2202 int e
= get_symbol_end ();
2204 if (strcmp (string
, "prefix") == 0)
2206 else if (strcmp (string
, "noprefix") == 0)
2209 as_bad (_("bad argument to syntax directive."));
2210 *input_line_pointer
= e
;
2212 demand_empty_rest_of_line ();
2214 intel_syntax
= syntax_flag
;
2216 if (ask_naked_reg
== 0)
2217 allow_naked_reg
= (intel_syntax
2218 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2220 allow_naked_reg
= (ask_naked_reg
< 0);
2222 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2224 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2225 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2226 register_prefix
= allow_naked_reg
? "" : "%";
2230 set_intel_mnemonic (int mnemonic_flag
)
2232 intel_mnemonic
= mnemonic_flag
;
2236 set_allow_index_reg (int flag
)
2238 allow_index_reg
= flag
;
2242 set_check (int what
)
2244 enum check_kind
*kind
;
2249 kind
= &operand_check
;
2260 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2262 char *string
= input_line_pointer
;
2263 int e
= get_symbol_end ();
2265 if (strcmp (string
, "none") == 0)
2267 else if (strcmp (string
, "warning") == 0)
2268 *kind
= check_warning
;
2269 else if (strcmp (string
, "error") == 0)
2270 *kind
= check_error
;
2272 as_bad (_("bad argument to %s_check directive."), str
);
2273 *input_line_pointer
= e
;
2276 as_bad (_("missing argument for %s_check directive"), str
);
2278 demand_empty_rest_of_line ();
2282 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2283 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2285 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2286 static const char *arch
;
2288 /* Intel LIOM is only supported on ELF. */
2294 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2295 use default_arch. */
2296 arch
= cpu_arch_name
;
2298 arch
= default_arch
;
2301 /* If we are targeting Intel MCU, we must enable it. */
2302 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2303 || new_flag
.bitfield
.cpuiamcu
)
2306 /* If we are targeting Intel L1OM, we must enable it. */
2307 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2308 || new_flag
.bitfield
.cpul1om
)
2311 /* If we are targeting Intel K1OM, we must enable it. */
2312 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2313 || new_flag
.bitfield
.cpuk1om
)
2316 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2321 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2325 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2327 char *string
= input_line_pointer
;
2328 int e
= get_symbol_end ();
2330 i386_cpu_flags flags
;
2332 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2334 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2336 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2340 cpu_arch_name
= cpu_arch
[j
].name
;
2341 cpu_sub_arch_name
= NULL
;
2342 cpu_arch_flags
= cpu_arch
[j
].flags
;
2343 if (flag_code
== CODE_64BIT
)
2345 cpu_arch_flags
.bitfield
.cpu64
= 1;
2346 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2350 cpu_arch_flags
.bitfield
.cpu64
= 0;
2351 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2353 cpu_arch_isa
= cpu_arch
[j
].type
;
2354 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2355 if (!cpu_arch_tune_set
)
2357 cpu_arch_tune
= cpu_arch_isa
;
2358 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2363 if (!cpu_arch
[j
].negated
)
2364 flags
= cpu_flags_or (cpu_arch_flags
,
2367 flags
= cpu_flags_and_not (cpu_arch_flags
,
2370 if (!valid_iamcu_cpu_flags (&flags
))
2371 as_fatal (_("`%s' isn't valid for Intel MCU"),
2373 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2375 if (cpu_sub_arch_name
)
2377 char *name
= cpu_sub_arch_name
;
2378 cpu_sub_arch_name
= concat (name
,
2380 (const char *) NULL
);
2384 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2385 cpu_arch_flags
= flags
;
2386 cpu_arch_isa_flags
= flags
;
2388 *input_line_pointer
= e
;
2389 demand_empty_rest_of_line ();
2393 if (j
>= ARRAY_SIZE (cpu_arch
))
2394 as_bad (_("no such architecture: `%s'"), string
);
2396 *input_line_pointer
= e
;
2399 as_bad (_("missing cpu architecture"));
2401 no_cond_jump_promotion
= 0;
2402 if (*input_line_pointer
== ','
2403 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2405 char *string
= ++input_line_pointer
;
2406 int e
= get_symbol_end ();
2408 if (strcmp (string
, "nojumps") == 0)
2409 no_cond_jump_promotion
= 1;
2410 else if (strcmp (string
, "jumps") == 0)
2413 as_bad (_("no such architecture modifier: `%s'"), string
);
2415 *input_line_pointer
= e
;
2418 demand_empty_rest_of_line ();
2421 enum bfd_architecture
2424 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2426 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2427 || flag_code
!= CODE_64BIT
)
2428 as_fatal (_("Intel L1OM is 64bit ELF only"));
2429 return bfd_arch_l1om
;
2431 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2433 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2434 || flag_code
!= CODE_64BIT
)
2435 as_fatal (_("Intel K1OM is 64bit ELF only"));
2436 return bfd_arch_k1om
;
2438 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2440 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2441 || flag_code
== CODE_64BIT
)
2442 as_fatal (_("Intel MCU is 32bit ELF only"));
2443 return bfd_arch_iamcu
;
2446 return bfd_arch_i386
;
2452 if (!strncmp (default_arch
, "x86_64", 6))
2454 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2456 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2457 || default_arch
[6] != '\0')
2458 as_fatal (_("Intel L1OM is 64bit ELF only"));
2459 return bfd_mach_l1om
;
2461 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2463 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2464 || default_arch
[6] != '\0')
2465 as_fatal (_("Intel K1OM is 64bit ELF only"));
2466 return bfd_mach_k1om
;
2468 else if (default_arch
[6] == '\0')
2469 return bfd_mach_x86_64
;
2471 return bfd_mach_x64_32
;
2473 else if (!strcmp (default_arch
, "i386")
2474 || !strcmp (default_arch
, "iamcu"))
2476 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2478 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2479 as_fatal (_("Intel MCU is 32bit ELF only"));
2480 return bfd_mach_i386_iamcu
;
2483 return bfd_mach_i386_i386
;
2486 as_fatal (_("unknown architecture"));
2492 const char *hash_err
;
2494 /* Initialize op_hash hash table. */
2495 op_hash
= hash_new ();
2498 const insn_template
*optab
;
2499 templates
*core_optab
;
2501 /* Setup for loop. */
2503 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2504 core_optab
->start
= optab
;
2509 if (optab
->name
== NULL
2510 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2512 /* different name --> ship out current template list;
2513 add to hash table; & begin anew. */
2514 core_optab
->end
= optab
;
2515 hash_err
= hash_insert (op_hash
,
2517 (void *) core_optab
);
2520 as_fatal (_("can't hash %s: %s"),
2524 if (optab
->name
== NULL
)
2526 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2527 core_optab
->start
= optab
;
2532 /* Initialize reg_hash hash table. */
2533 reg_hash
= hash_new ();
2535 const reg_entry
*regtab
;
2536 unsigned int regtab_size
= i386_regtab_size
;
2538 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2540 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2542 as_fatal (_("can't hash %s: %s"),
2548 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2553 for (c
= 0; c
< 256; c
++)
2558 mnemonic_chars
[c
] = c
;
2559 register_chars
[c
] = c
;
2560 operand_chars
[c
] = c
;
2562 else if (ISLOWER (c
))
2564 mnemonic_chars
[c
] = c
;
2565 register_chars
[c
] = c
;
2566 operand_chars
[c
] = c
;
2568 else if (ISUPPER (c
))
2570 mnemonic_chars
[c
] = TOLOWER (c
);
2571 register_chars
[c
] = mnemonic_chars
[c
];
2572 operand_chars
[c
] = c
;
2574 else if (c
== '{' || c
== '}')
2575 operand_chars
[c
] = c
;
2577 if (ISALPHA (c
) || ISDIGIT (c
))
2578 identifier_chars
[c
] = c
;
2581 identifier_chars
[c
] = c
;
2582 operand_chars
[c
] = c
;
2587 identifier_chars
['@'] = '@';
2590 identifier_chars
['?'] = '?';
2591 operand_chars
['?'] = '?';
2593 digit_chars
['-'] = '-';
2594 mnemonic_chars
['_'] = '_';
2595 mnemonic_chars
['-'] = '-';
2596 mnemonic_chars
['.'] = '.';
2597 identifier_chars
['_'] = '_';
2598 identifier_chars
['.'] = '.';
2600 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2601 operand_chars
[(unsigned char) *p
] = *p
;
2604 if (flag_code
== CODE_64BIT
)
2606 #if defined (OBJ_COFF) && defined (TE_PE)
2607 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2610 x86_dwarf2_return_column
= 16;
2612 x86_cie_data_alignment
= -8;
2616 x86_dwarf2_return_column
= 8;
2617 x86_cie_data_alignment
= -4;
2622 i386_print_statistics (FILE *file
)
2624 hash_print_statistics (file
, "i386 opcode", op_hash
);
2625 hash_print_statistics (file
, "i386 register", reg_hash
);
2630 /* Debugging routines for md_assemble. */
2631 static void pte (insn_template
*);
2632 static void pt (i386_operand_type
);
2633 static void pe (expressionS
*);
2634 static void ps (symbolS
*);
2637 pi (char *line
, i386_insn
*x
)
2641 fprintf (stdout
, "%s: template ", line
);
2643 fprintf (stdout
, " address: base %s index %s scale %x\n",
2644 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2645 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2646 x
->log2_scale_factor
);
2647 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2648 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2649 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2650 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2651 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2652 (x
->rex
& REX_W
) != 0,
2653 (x
->rex
& REX_R
) != 0,
2654 (x
->rex
& REX_X
) != 0,
2655 (x
->rex
& REX_B
) != 0);
2656 for (j
= 0; j
< x
->operands
; j
++)
2658 fprintf (stdout
, " #%d: ", j
+ 1);
2660 fprintf (stdout
, "\n");
2661 if (x
->types
[j
].bitfield
.reg8
2662 || x
->types
[j
].bitfield
.reg16
2663 || x
->types
[j
].bitfield
.reg32
2664 || x
->types
[j
].bitfield
.reg64
2665 || x
->types
[j
].bitfield
.regmmx
2666 || x
->types
[j
].bitfield
.regxmm
2667 || x
->types
[j
].bitfield
.regymm
2668 || x
->types
[j
].bitfield
.regzmm
2669 || x
->types
[j
].bitfield
.sreg2
2670 || x
->types
[j
].bitfield
.sreg3
2671 || x
->types
[j
].bitfield
.control
2672 || x
->types
[j
].bitfield
.debug
2673 || x
->types
[j
].bitfield
.test
)
2674 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2675 if (operand_type_check (x
->types
[j
], imm
))
2677 if (operand_type_check (x
->types
[j
], disp
))
2678 pe (x
->op
[j
].disps
);
2683 pte (insn_template
*t
)
2686 fprintf (stdout
, " %d operands ", t
->operands
);
2687 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2688 if (t
->extension_opcode
!= None
)
2689 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2690 if (t
->opcode_modifier
.d
)
2691 fprintf (stdout
, "D");
2692 if (t
->opcode_modifier
.w
)
2693 fprintf (stdout
, "W");
2694 fprintf (stdout
, "\n");
2695 for (j
= 0; j
< t
->operands
; j
++)
2697 fprintf (stdout
, " #%d type ", j
+ 1);
2698 pt (t
->operand_types
[j
]);
2699 fprintf (stdout
, "\n");
2706 fprintf (stdout
, " operation %d\n", e
->X_op
);
2707 fprintf (stdout
, " add_number %ld (%lx)\n",
2708 (long) e
->X_add_number
, (long) e
->X_add_number
);
2709 if (e
->X_add_symbol
)
2711 fprintf (stdout
, " add_symbol ");
2712 ps (e
->X_add_symbol
);
2713 fprintf (stdout
, "\n");
2717 fprintf (stdout
, " op_symbol ");
2718 ps (e
->X_op_symbol
);
2719 fprintf (stdout
, "\n");
2726 fprintf (stdout
, "%s type %s%s",
2728 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2729 segment_name (S_GET_SEGMENT (s
)));
2732 static struct type_name
2734 i386_operand_type mask
;
2737 const type_names
[] =
2739 { OPERAND_TYPE_REG8
, "r8" },
2740 { OPERAND_TYPE_REG16
, "r16" },
2741 { OPERAND_TYPE_REG32
, "r32" },
2742 { OPERAND_TYPE_REG64
, "r64" },
2743 { OPERAND_TYPE_IMM8
, "i8" },
2744 { OPERAND_TYPE_IMM8
, "i8s" },
2745 { OPERAND_TYPE_IMM16
, "i16" },
2746 { OPERAND_TYPE_IMM32
, "i32" },
2747 { OPERAND_TYPE_IMM32S
, "i32s" },
2748 { OPERAND_TYPE_IMM64
, "i64" },
2749 { OPERAND_TYPE_IMM1
, "i1" },
2750 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2751 { OPERAND_TYPE_DISP8
, "d8" },
2752 { OPERAND_TYPE_DISP16
, "d16" },
2753 { OPERAND_TYPE_DISP32
, "d32" },
2754 { OPERAND_TYPE_DISP32S
, "d32s" },
2755 { OPERAND_TYPE_DISP64
, "d64" },
2756 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2757 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2758 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2759 { OPERAND_TYPE_CONTROL
, "control reg" },
2760 { OPERAND_TYPE_TEST
, "test reg" },
2761 { OPERAND_TYPE_DEBUG
, "debug reg" },
2762 { OPERAND_TYPE_FLOATREG
, "FReg" },
2763 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2764 { OPERAND_TYPE_SREG2
, "SReg2" },
2765 { OPERAND_TYPE_SREG3
, "SReg3" },
2766 { OPERAND_TYPE_ACC
, "Acc" },
2767 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2768 { OPERAND_TYPE_REGMMX
, "rMMX" },
2769 { OPERAND_TYPE_REGXMM
, "rXMM" },
2770 { OPERAND_TYPE_REGYMM
, "rYMM" },
2771 { OPERAND_TYPE_REGZMM
, "rZMM" },
2772 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2773 { OPERAND_TYPE_ESSEG
, "es" },
2777 pt (i386_operand_type t
)
2780 i386_operand_type a
;
2782 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2784 a
= operand_type_and (t
, type_names
[j
].mask
);
2785 if (!operand_type_all_zero (&a
))
2786 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2791 #endif /* DEBUG386 */
2793 static bfd_reloc_code_real_type
2794 reloc (unsigned int size
,
2797 bfd_reloc_code_real_type other
)
2799 if (other
!= NO_RELOC
)
2801 reloc_howto_type
*rel
;
2806 case BFD_RELOC_X86_64_GOT32
:
2807 return BFD_RELOC_X86_64_GOT64
;
2809 case BFD_RELOC_X86_64_GOTPLT64
:
2810 return BFD_RELOC_X86_64_GOTPLT64
;
2812 case BFD_RELOC_X86_64_PLTOFF64
:
2813 return BFD_RELOC_X86_64_PLTOFF64
;
2815 case BFD_RELOC_X86_64_GOTPC32
:
2816 other
= BFD_RELOC_X86_64_GOTPC64
;
2818 case BFD_RELOC_X86_64_GOTPCREL
:
2819 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2821 case BFD_RELOC_X86_64_TPOFF32
:
2822 other
= BFD_RELOC_X86_64_TPOFF64
;
2824 case BFD_RELOC_X86_64_DTPOFF32
:
2825 other
= BFD_RELOC_X86_64_DTPOFF64
;
2831 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2832 if (other
== BFD_RELOC_SIZE32
)
2835 other
= BFD_RELOC_SIZE64
;
2838 as_bad (_("there are no pc-relative size relocations"));
2844 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2845 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2848 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2850 as_bad (_("unknown relocation (%u)"), other
);
2851 else if (size
!= bfd_get_reloc_size (rel
))
2852 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2853 bfd_get_reloc_size (rel
),
2855 else if (pcrel
&& !rel
->pc_relative
)
2856 as_bad (_("non-pc-relative relocation for pc-relative field"));
2857 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2859 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2861 as_bad (_("relocated field and relocation type differ in signedness"));
2870 as_bad (_("there are no unsigned pc-relative relocations"));
2873 case 1: return BFD_RELOC_8_PCREL
;
2874 case 2: return BFD_RELOC_16_PCREL
;
2875 case 4: return BFD_RELOC_32_PCREL
;
2876 case 8: return BFD_RELOC_64_PCREL
;
2878 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2885 case 4: return BFD_RELOC_X86_64_32S
;
2890 case 1: return BFD_RELOC_8
;
2891 case 2: return BFD_RELOC_16
;
2892 case 4: return BFD_RELOC_32
;
2893 case 8: return BFD_RELOC_64
;
2895 as_bad (_("cannot do %s %u byte relocation"),
2896 sign
> 0 ? "signed" : "unsigned", size
);
2902 /* Here we decide which fixups can be adjusted to make them relative to
2903 the beginning of the section instead of the symbol. Basically we need
2904 to make sure that the dynamic relocations are done correctly, so in
2905 some cases we force the original symbol to be used. */
2908 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2910 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2914 /* Don't adjust pc-relative references to merge sections in 64-bit
2916 if (use_rela_relocations
2917 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2921 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2922 and changed later by validate_fix. */
2923 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2924 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2927 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2928 for size relocations. */
2929 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2930 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2931 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2932 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2933 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2934 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2935 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2936 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2937 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2938 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2939 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2940 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2941 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2942 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2943 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2944 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2945 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2946 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2947 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2948 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2949 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2950 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2951 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2952 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2953 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2954 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2955 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2956 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2957 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2958 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2965 intel_float_operand (const char *mnemonic
)
2967 /* Note that the value returned is meaningful only for opcodes with (memory)
2968 operands, hence the code here is free to improperly handle opcodes that
2969 have no operands (for better performance and smaller code). */
2971 if (mnemonic
[0] != 'f')
2972 return 0; /* non-math */
2974 switch (mnemonic
[1])
2976 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2977 the fs segment override prefix not currently handled because no
2978 call path can make opcodes without operands get here */
2980 return 2 /* integer op */;
2982 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2983 return 3; /* fldcw/fldenv */
2986 if (mnemonic
[2] != 'o' /* fnop */)
2987 return 3; /* non-waiting control op */
2990 if (mnemonic
[2] == 's')
2991 return 3; /* frstor/frstpm */
2994 if (mnemonic
[2] == 'a')
2995 return 3; /* fsave */
2996 if (mnemonic
[2] == 't')
2998 switch (mnemonic
[3])
3000 case 'c': /* fstcw */
3001 case 'd': /* fstdw */
3002 case 'e': /* fstenv */
3003 case 's': /* fsts[gw] */
3009 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3010 return 0; /* fxsave/fxrstor are not really math ops */
3017 /* Build the VEX prefix. */
3020 build_vex_prefix (const insn_template
*t
)
3022 unsigned int register_specifier
;
3023 unsigned int implied_prefix
;
3024 unsigned int vector_length
;
3026 /* Check register specifier. */
3027 if (i
.vex
.register_specifier
)
3029 register_specifier
=
3030 ~register_number (i
.vex
.register_specifier
) & 0xf;
3031 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3034 register_specifier
= 0xf;
3036 /* Use 2-byte VEX prefix by swappping destination and source
3039 && i
.operands
== i
.reg_operands
3040 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3041 && i
.tm
.opcode_modifier
.s
3044 unsigned int xchg
= i
.operands
- 1;
3045 union i386_op temp_op
;
3046 i386_operand_type temp_type
;
3048 temp_type
= i
.types
[xchg
];
3049 i
.types
[xchg
] = i
.types
[0];
3050 i
.types
[0] = temp_type
;
3051 temp_op
= i
.op
[xchg
];
3052 i
.op
[xchg
] = i
.op
[0];
3055 gas_assert (i
.rm
.mode
== 3);
3059 i
.rm
.regmem
= i
.rm
.reg
;
3062 /* Use the next insn. */
3066 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3067 vector_length
= avxscalar
;
3069 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3071 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3076 case DATA_PREFIX_OPCODE
:
3079 case REPE_PREFIX_OPCODE
:
3082 case REPNE_PREFIX_OPCODE
:
3089 /* Use 2-byte VEX prefix if possible. */
3090 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3091 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3092 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3094 /* 2-byte VEX prefix. */
3098 i
.vex
.bytes
[0] = 0xc5;
3100 /* Check the REX.R bit. */
3101 r
= (i
.rex
& REX_R
) ? 0 : 1;
3102 i
.vex
.bytes
[1] = (r
<< 7
3103 | register_specifier
<< 3
3104 | vector_length
<< 2
3109 /* 3-byte VEX prefix. */
3114 switch (i
.tm
.opcode_modifier
.vexopcode
)
3118 i
.vex
.bytes
[0] = 0xc4;
3122 i
.vex
.bytes
[0] = 0xc4;
3126 i
.vex
.bytes
[0] = 0xc4;
3130 i
.vex
.bytes
[0] = 0x8f;
3134 i
.vex
.bytes
[0] = 0x8f;
3138 i
.vex
.bytes
[0] = 0x8f;
3144 /* The high 3 bits of the second VEX byte are 1's compliment
3145 of RXB bits from REX. */
3146 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3148 /* Check the REX.W bit. */
3149 w
= (i
.rex
& REX_W
) ? 1 : 0;
3150 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3153 i
.vex
.bytes
[2] = (w
<< 7
3154 | register_specifier
<< 3
3155 | vector_length
<< 2
3160 /* Build the EVEX prefix. */
3163 build_evex_prefix (void)
3165 unsigned int register_specifier
;
3166 unsigned int implied_prefix
;
3168 rex_byte vrex_used
= 0;
3170 /* Check register specifier. */
3171 if (i
.vex
.register_specifier
)
3173 gas_assert ((i
.vrex
& REX_X
) == 0);
3175 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3176 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3177 register_specifier
+= 8;
3178 /* The upper 16 registers are encoded in the fourth byte of the
3180 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3181 i
.vex
.bytes
[3] = 0x8;
3182 register_specifier
= ~register_specifier
& 0xf;
3186 register_specifier
= 0xf;
3188 /* Encode upper 16 vector index register in the fourth byte of
3190 if (!(i
.vrex
& REX_X
))
3191 i
.vex
.bytes
[3] = 0x8;
3196 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3201 case DATA_PREFIX_OPCODE
:
3204 case REPE_PREFIX_OPCODE
:
3207 case REPNE_PREFIX_OPCODE
:
3214 /* 4 byte EVEX prefix. */
3216 i
.vex
.bytes
[0] = 0x62;
3219 switch (i
.tm
.opcode_modifier
.vexopcode
)
3235 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3237 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3239 /* The fifth bit of the second EVEX byte is 1's compliment of the
3240 REX_R bit in VREX. */
3241 if (!(i
.vrex
& REX_R
))
3242 i
.vex
.bytes
[1] |= 0x10;
3246 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3248 /* When all operands are registers, the REX_X bit in REX is not
3249 used. We reuse it to encode the upper 16 registers, which is
3250 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3251 as 1's compliment. */
3252 if ((i
.vrex
& REX_B
))
3255 i
.vex
.bytes
[1] &= ~0x40;
3259 /* EVEX instructions shouldn't need the REX prefix. */
3260 i
.vrex
&= ~vrex_used
;
3261 gas_assert (i
.vrex
== 0);
3263 /* Check the REX.W bit. */
3264 w
= (i
.rex
& REX_W
) ? 1 : 0;
3265 if (i
.tm
.opcode_modifier
.vexw
)
3267 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3270 /* If w is not set it means we are dealing with WIG instruction. */
3273 if (evexwig
== evexw1
)
3277 /* Encode the U bit. */
3278 implied_prefix
|= 0x4;
3280 /* The third byte of the EVEX prefix. */
3281 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3283 /* The fourth byte of the EVEX prefix. */
3284 /* The zeroing-masking bit. */
3285 if (i
.mask
&& i
.mask
->zeroing
)
3286 i
.vex
.bytes
[3] |= 0x80;
3288 /* Don't always set the broadcast bit if there is no RC. */
3291 /* Encode the vector length. */
3292 unsigned int vec_length
;
3294 switch (i
.tm
.opcode_modifier
.evex
)
3296 case EVEXLIG
: /* LL' is ignored */
3297 vec_length
= evexlig
<< 5;
3300 vec_length
= 0 << 5;
3303 vec_length
= 1 << 5;
3306 vec_length
= 2 << 5;
3312 i
.vex
.bytes
[3] |= vec_length
;
3313 /* Encode the broadcast bit. */
3315 i
.vex
.bytes
[3] |= 0x10;
3319 if (i
.rounding
->type
!= saeonly
)
3320 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3322 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3325 if (i
.mask
&& i
.mask
->mask
)
3326 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3330 process_immext (void)
3334 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3337 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3338 with an opcode suffix which is coded in the same place as an
3339 8-bit immediate field would be.
3340 Here we check those operands and remove them afterwards. */
3343 for (x
= 0; x
< i
.operands
; x
++)
3344 if (register_number (i
.op
[x
].regs
) != x
)
3345 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3346 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3352 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3354 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3355 suffix which is coded in the same place as an 8-bit immediate
3357 Here we check those operands and remove them afterwards. */
3360 if (i
.operands
!= 3)
3363 for (x
= 0; x
< 2; x
++)
3364 if (register_number (i
.op
[x
].regs
) != x
)
3365 goto bad_register_operand
;
3367 /* Check for third operand for mwaitx/monitorx insn. */
3368 if (register_number (i
.op
[x
].regs
)
3369 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3371 bad_register_operand
:
3372 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3373 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3380 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3381 which is coded in the same place as an 8-bit immediate field
3382 would be. Here we fake an 8-bit immediate operand from the
3383 opcode suffix stored in tm.extension_opcode.
3385 AVX instructions also use this encoding, for some of
3386 3 argument instructions. */
3388 gas_assert (i
.imm_operands
<= 1
3390 || ((i
.tm
.opcode_modifier
.vex
3391 || i
.tm
.opcode_modifier
.evex
)
3392 && i
.operands
<= 4)));
3394 exp
= &im_expressions
[i
.imm_operands
++];
3395 i
.op
[i
.operands
].imms
= exp
;
3396 i
.types
[i
.operands
] = imm8
;
3398 exp
->X_op
= O_constant
;
3399 exp
->X_add_number
= i
.tm
.extension_opcode
;
3400 i
.tm
.extension_opcode
= None
;
3407 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3412 as_bad (_("invalid instruction `%s' after `%s'"),
3413 i
.tm
.name
, i
.hle_prefix
);
3416 if (i
.prefix
[LOCK_PREFIX
])
3418 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3422 case HLEPrefixRelease
:
3423 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3425 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3429 if (i
.mem_operands
== 0
3430 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3432 as_bad (_("memory destination needed for instruction `%s'"
3433 " after `xrelease'"), i
.tm
.name
);
3440 /* This is the guts of the machine-dependent assembler. LINE points to a
3441 machine dependent instruction. This function is supposed to emit
3442 the frags/bytes it assembles to. */
3445 md_assemble (char *line
)
3448 char mnemonic
[MAX_MNEM_SIZE
];
3449 const insn_template
*t
;
3451 /* Initialize globals. */
3452 memset (&i
, '\0', sizeof (i
));
3453 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3454 i
.reloc
[j
] = NO_RELOC
;
3455 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3456 memset (im_expressions
, '\0', sizeof (im_expressions
));
3457 save_stack_p
= save_stack
;
3459 /* First parse an instruction mnemonic & call i386_operand for the operands.
3460 We assume that the scrubber has arranged it so that line[0] is the valid
3461 start of a (possibly prefixed) mnemonic. */
3463 line
= parse_insn (line
, mnemonic
);
3467 line
= parse_operands (line
, mnemonic
);
3472 /* Now we've parsed the mnemonic into a set of templates, and have the
3473 operands at hand. */
3475 /* All intel opcodes have reversed operands except for "bound" and
3476 "enter". We also don't reverse intersegment "jmp" and "call"
3477 instructions with 2 immediate operands so that the immediate segment
3478 precedes the offset, as it does when in AT&T mode. */
3481 && (strcmp (mnemonic
, "bound") != 0)
3482 && (strcmp (mnemonic
, "invlpga") != 0)
3483 && !(operand_type_check (i
.types
[0], imm
)
3484 && operand_type_check (i
.types
[1], imm
)))
3487 /* The order of the immediates should be reversed
3488 for 2 immediates extrq and insertq instructions */
3489 if (i
.imm_operands
== 2
3490 && (strcmp (mnemonic
, "extrq") == 0
3491 || strcmp (mnemonic
, "insertq") == 0))
3492 swap_2_operands (0, 1);
3497 /* Don't optimize displacement for movabs since it only takes 64bit
3500 && i
.disp_encoding
!= disp_encoding_32bit
3501 && (flag_code
!= CODE_64BIT
3502 || strcmp (mnemonic
, "movabs") != 0))
3505 /* Next, we find a template that matches the given insn,
3506 making sure the overlap of the given operands types is consistent
3507 with the template operand types. */
3509 if (!(t
= match_template ()))
3512 if (sse_check
!= check_none
3513 && !i
.tm
.opcode_modifier
.noavx
3514 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3515 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3516 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3517 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3518 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3519 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3521 (sse_check
== check_warning
3523 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3526 /* Zap movzx and movsx suffix. The suffix has been set from
3527 "word ptr" or "byte ptr" on the source operand in Intel syntax
3528 or extracted from mnemonic in AT&T syntax. But we'll use
3529 the destination register to choose the suffix for encoding. */
3530 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3532 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3533 there is no suffix, the default will be byte extension. */
3534 if (i
.reg_operands
!= 2
3537 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3542 if (i
.tm
.opcode_modifier
.fwait
)
3543 if (!add_prefix (FWAIT_OPCODE
))
3546 /* Check if REP prefix is OK. */
3547 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3549 as_bad (_("invalid instruction `%s' after `%s'"),
3550 i
.tm
.name
, i
.rep_prefix
);
3554 /* Check for lock without a lockable instruction. Destination operand
3555 must be memory unless it is xchg (0x86). */
3556 if (i
.prefix
[LOCK_PREFIX
]
3557 && (!i
.tm
.opcode_modifier
.islockable
3558 || i
.mem_operands
== 0
3559 || (i
.tm
.base_opcode
!= 0x86
3560 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3562 as_bad (_("expecting lockable instruction after `lock'"));
3566 /* Check if HLE prefix is OK. */
3567 if (i
.hle_prefix
&& !check_hle ())
3570 /* Check BND prefix. */
3571 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3572 as_bad (_("expecting valid branch instruction after `bnd'"));
3574 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3575 && flag_code
== CODE_64BIT
3576 && i
.prefix
[ADDR_PREFIX
])
3577 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3579 /* Insert BND prefix. */
3581 && i
.tm
.opcode_modifier
.bndprefixok
3582 && !i
.prefix
[BND_PREFIX
])
3583 add_prefix (BND_PREFIX_OPCODE
);
3585 /* Check string instruction segment overrides. */
3586 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3588 if (!check_string ())
3590 i
.disp_operands
= 0;
3593 if (!process_suffix ())
3596 /* Update operand types. */
3597 for (j
= 0; j
< i
.operands
; j
++)
3598 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3600 /* Make still unresolved immediate matches conform to size of immediate
3601 given in i.suffix. */
3602 if (!finalize_imm ())
3605 if (i
.types
[0].bitfield
.imm1
)
3606 i
.imm_operands
= 0; /* kludge for shift insns. */
3608 /* We only need to check those implicit registers for instructions
3609 with 3 operands or less. */
3610 if (i
.operands
<= 3)
3611 for (j
= 0; j
< i
.operands
; j
++)
3612 if (i
.types
[j
].bitfield
.inoutportreg
3613 || i
.types
[j
].bitfield
.shiftcount
3614 || i
.types
[j
].bitfield
.acc
3615 || i
.types
[j
].bitfield
.floatacc
)
3618 /* ImmExt should be processed after SSE2AVX. */
3619 if (!i
.tm
.opcode_modifier
.sse2avx
3620 && i
.tm
.opcode_modifier
.immext
)
3623 /* For insns with operands there are more diddles to do to the opcode. */
3626 if (!process_operands ())
3629 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3631 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3632 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3635 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3637 if (flag_code
== CODE_16BIT
)
3639 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3644 if (i
.tm
.opcode_modifier
.vex
)
3645 build_vex_prefix (t
);
3647 build_evex_prefix ();
3650 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3651 instructions may define INT_OPCODE as well, so avoid this corner
3652 case for those instructions that use MODRM. */
3653 if (i
.tm
.base_opcode
== INT_OPCODE
3654 && !i
.tm
.opcode_modifier
.modrm
3655 && i
.op
[0].imms
->X_add_number
== 3)
3657 i
.tm
.base_opcode
= INT3_OPCODE
;
3661 if ((i
.tm
.opcode_modifier
.jump
3662 || i
.tm
.opcode_modifier
.jumpbyte
3663 || i
.tm
.opcode_modifier
.jumpdword
)
3664 && i
.op
[0].disps
->X_op
== O_constant
)
3666 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3667 the absolute address given by the constant. Since ix86 jumps and
3668 calls are pc relative, we need to generate a reloc. */
3669 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3670 i
.op
[0].disps
->X_op
= O_symbol
;
3673 if (i
.tm
.opcode_modifier
.rex64
)
3676 /* For 8 bit registers we need an empty rex prefix. Also if the
3677 instruction already has a prefix, we need to convert old
3678 registers to new ones. */
3680 if ((i
.types
[0].bitfield
.reg8
3681 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3682 || (i
.types
[1].bitfield
.reg8
3683 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3684 || ((i
.types
[0].bitfield
.reg8
3685 || i
.types
[1].bitfield
.reg8
)
3690 i
.rex
|= REX_OPCODE
;
3691 for (x
= 0; x
< 2; x
++)
3693 /* Look for 8 bit operand that uses old registers. */
3694 if (i
.types
[x
].bitfield
.reg8
3695 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3697 /* In case it is "hi" register, give up. */
3698 if (i
.op
[x
].regs
->reg_num
> 3)
3699 as_bad (_("can't encode register '%s%s' in an "
3700 "instruction requiring REX prefix."),
3701 register_prefix
, i
.op
[x
].regs
->reg_name
);
3703 /* Otherwise it is equivalent to the extended register.
3704 Since the encoding doesn't change this is merely
3705 cosmetic cleanup for debug output. */
3707 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3713 add_prefix (REX_OPCODE
| i
.rex
);
3715 /* We are ready to output the insn. */
3720 parse_insn (char *line
, char *mnemonic
)
3723 char *token_start
= l
;
3726 const insn_template
*t
;
3732 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3737 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3739 as_bad (_("no such instruction: `%s'"), token_start
);
3744 if (!is_space_char (*l
)
3745 && *l
!= END_OF_INSN
3747 || (*l
!= PREFIX_SEPARATOR
3750 as_bad (_("invalid character %s in mnemonic"),
3751 output_invalid (*l
));
3754 if (token_start
== l
)
3756 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3757 as_bad (_("expecting prefix; got nothing"));
3759 as_bad (_("expecting mnemonic; got nothing"));
3763 /* Look up instruction (or prefix) via hash table. */
3764 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3766 if (*l
!= END_OF_INSN
3767 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3768 && current_templates
3769 && current_templates
->start
->opcode_modifier
.isprefix
)
3771 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3773 as_bad ((flag_code
!= CODE_64BIT
3774 ? _("`%s' is only supported in 64-bit mode")
3775 : _("`%s' is not supported in 64-bit mode")),
3776 current_templates
->start
->name
);
3779 /* If we are in 16-bit mode, do not allow addr16 or data16.
3780 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3781 if ((current_templates
->start
->opcode_modifier
.size16
3782 || current_templates
->start
->opcode_modifier
.size32
)
3783 && flag_code
!= CODE_64BIT
3784 && (current_templates
->start
->opcode_modifier
.size32
3785 ^ (flag_code
== CODE_16BIT
)))
3787 as_bad (_("redundant %s prefix"),
3788 current_templates
->start
->name
);
3791 /* Add prefix, checking for repeated prefixes. */
3792 switch (add_prefix (current_templates
->start
->base_opcode
))
3797 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3798 i
.hle_prefix
= current_templates
->start
->name
;
3799 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3800 i
.bnd_prefix
= current_templates
->start
->name
;
3802 i
.rep_prefix
= current_templates
->start
->name
;
3807 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3814 if (!current_templates
)
3816 /* Check if we should swap operand or force 32bit displacement in
3818 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3820 else if (mnem_p
- 3 == dot_p
3823 i
.disp_encoding
= disp_encoding_8bit
;
3824 else if (mnem_p
- 4 == dot_p
3828 i
.disp_encoding
= disp_encoding_32bit
;
3833 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3836 if (!current_templates
)
3839 /* See if we can get a match by trimming off a suffix. */
3842 case WORD_MNEM_SUFFIX
:
3843 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3844 i
.suffix
= SHORT_MNEM_SUFFIX
;
3846 case BYTE_MNEM_SUFFIX
:
3847 case QWORD_MNEM_SUFFIX
:
3848 i
.suffix
= mnem_p
[-1];
3850 current_templates
= (const templates
*) hash_find (op_hash
,
3853 case SHORT_MNEM_SUFFIX
:
3854 case LONG_MNEM_SUFFIX
:
3857 i
.suffix
= mnem_p
[-1];
3859 current_templates
= (const templates
*) hash_find (op_hash
,
3868 if (intel_float_operand (mnemonic
) == 1)
3869 i
.suffix
= SHORT_MNEM_SUFFIX
;
3871 i
.suffix
= LONG_MNEM_SUFFIX
;
3873 current_templates
= (const templates
*) hash_find (op_hash
,
3878 if (!current_templates
)
3880 as_bad (_("no such instruction: `%s'"), token_start
);
3885 if (current_templates
->start
->opcode_modifier
.jump
3886 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3888 /* Check for a branch hint. We allow ",pt" and ",pn" for
3889 predict taken and predict not taken respectively.
3890 I'm not sure that branch hints actually do anything on loop
3891 and jcxz insns (JumpByte) for current Pentium4 chips. They
3892 may work in the future and it doesn't hurt to accept them
3894 if (l
[0] == ',' && l
[1] == 'p')
3898 if (!add_prefix (DS_PREFIX_OPCODE
))
3902 else if (l
[2] == 'n')
3904 if (!add_prefix (CS_PREFIX_OPCODE
))
3910 /* Any other comma loses. */
3913 as_bad (_("invalid character %s in mnemonic"),
3914 output_invalid (*l
));
3918 /* Check if instruction is supported on specified architecture. */
3920 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3922 supported
|= cpu_flags_match (t
);
3923 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3927 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3929 as_bad (flag_code
== CODE_64BIT
3930 ? _("`%s' is not supported in 64-bit mode")
3931 : _("`%s' is only supported in 64-bit mode"),
3932 current_templates
->start
->name
);
3935 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3937 as_bad (_("`%s' is not supported on `%s%s'"),
3938 current_templates
->start
->name
,
3939 cpu_arch_name
? cpu_arch_name
: default_arch
,
3940 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3945 if (!cpu_arch_flags
.bitfield
.cpui386
3946 && (flag_code
!= CODE_16BIT
))
3948 as_warn (_("use .code16 to ensure correct addressing mode"));
3955 parse_operands (char *l
, const char *mnemonic
)
3959 /* 1 if operand is pending after ','. */
3960 unsigned int expecting_operand
= 0;
3962 /* Non-zero if operand parens not balanced. */
3963 unsigned int paren_not_balanced
;
3965 while (*l
!= END_OF_INSN
)
3967 /* Skip optional white space before operand. */
3968 if (is_space_char (*l
))
3970 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3972 as_bad (_("invalid character %s before operand %d"),
3973 output_invalid (*l
),
3977 token_start
= l
; /* after white space */
3978 paren_not_balanced
= 0;
3979 while (paren_not_balanced
|| *l
!= ',')
3981 if (*l
== END_OF_INSN
)
3983 if (paren_not_balanced
)
3986 as_bad (_("unbalanced parenthesis in operand %d."),
3989 as_bad (_("unbalanced brackets in operand %d."),
3994 break; /* we are done */
3996 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3998 as_bad (_("invalid character %s in operand %d"),
3999 output_invalid (*l
),
4006 ++paren_not_balanced
;
4008 --paren_not_balanced
;
4013 ++paren_not_balanced
;
4015 --paren_not_balanced
;
4019 if (l
!= token_start
)
4020 { /* Yes, we've read in another operand. */
4021 unsigned int operand_ok
;
4022 this_operand
= i
.operands
++;
4023 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4024 if (i
.operands
> MAX_OPERANDS
)
4026 as_bad (_("spurious operands; (%d operands/instruction max)"),
4030 /* Now parse operand adding info to 'i' as we go along. */
4031 END_STRING_AND_SAVE (l
);
4035 i386_intel_operand (token_start
,
4036 intel_float_operand (mnemonic
));
4038 operand_ok
= i386_att_operand (token_start
);
4040 RESTORE_END_STRING (l
);
4046 if (expecting_operand
)
4048 expecting_operand_after_comma
:
4049 as_bad (_("expecting operand after ','; got nothing"));
4054 as_bad (_("expecting operand before ','; got nothing"));
4059 /* Now *l must be either ',' or END_OF_INSN. */
4062 if (*++l
== END_OF_INSN
)
4064 /* Just skip it, if it's \n complain. */
4065 goto expecting_operand_after_comma
;
4067 expecting_operand
= 1;
4074 swap_2_operands (int xchg1
, int xchg2
)
4076 union i386_op temp_op
;
4077 i386_operand_type temp_type
;
4078 enum bfd_reloc_code_real temp_reloc
;
4080 temp_type
= i
.types
[xchg2
];
4081 i
.types
[xchg2
] = i
.types
[xchg1
];
4082 i
.types
[xchg1
] = temp_type
;
4083 temp_op
= i
.op
[xchg2
];
4084 i
.op
[xchg2
] = i
.op
[xchg1
];
4085 i
.op
[xchg1
] = temp_op
;
4086 temp_reloc
= i
.reloc
[xchg2
];
4087 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4088 i
.reloc
[xchg1
] = temp_reloc
;
4092 if (i
.mask
->operand
== xchg1
)
4093 i
.mask
->operand
= xchg2
;
4094 else if (i
.mask
->operand
== xchg2
)
4095 i
.mask
->operand
= xchg1
;
4099 if (i
.broadcast
->operand
== xchg1
)
4100 i
.broadcast
->operand
= xchg2
;
4101 else if (i
.broadcast
->operand
== xchg2
)
4102 i
.broadcast
->operand
= xchg1
;
4106 if (i
.rounding
->operand
== xchg1
)
4107 i
.rounding
->operand
= xchg2
;
4108 else if (i
.rounding
->operand
== xchg2
)
4109 i
.rounding
->operand
= xchg1
;
4114 swap_operands (void)
4120 swap_2_operands (1, i
.operands
- 2);
4123 swap_2_operands (0, i
.operands
- 1);
4129 if (i
.mem_operands
== 2)
4131 const seg_entry
*temp_seg
;
4132 temp_seg
= i
.seg
[0];
4133 i
.seg
[0] = i
.seg
[1];
4134 i
.seg
[1] = temp_seg
;
4138 /* Try to ensure constant immediates are represented in the smallest
4143 char guess_suffix
= 0;
4147 guess_suffix
= i
.suffix
;
4148 else if (i
.reg_operands
)
4150 /* Figure out a suffix from the last register operand specified.
4151 We can't do this properly yet, ie. excluding InOutPortReg,
4152 but the following works for instructions with immediates.
4153 In any case, we can't set i.suffix yet. */
4154 for (op
= i
.operands
; --op
>= 0;)
4155 if (i
.types
[op
].bitfield
.reg8
)
4157 guess_suffix
= BYTE_MNEM_SUFFIX
;
4160 else if (i
.types
[op
].bitfield
.reg16
)
4162 guess_suffix
= WORD_MNEM_SUFFIX
;
4165 else if (i
.types
[op
].bitfield
.reg32
)
4167 guess_suffix
= LONG_MNEM_SUFFIX
;
4170 else if (i
.types
[op
].bitfield
.reg64
)
4172 guess_suffix
= QWORD_MNEM_SUFFIX
;
4176 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4177 guess_suffix
= WORD_MNEM_SUFFIX
;
4179 for (op
= i
.operands
; --op
>= 0;)
4180 if (operand_type_check (i
.types
[op
], imm
))
4182 switch (i
.op
[op
].imms
->X_op
)
4185 /* If a suffix is given, this operand may be shortened. */
4186 switch (guess_suffix
)
4188 case LONG_MNEM_SUFFIX
:
4189 i
.types
[op
].bitfield
.imm32
= 1;
4190 i
.types
[op
].bitfield
.imm64
= 1;
4192 case WORD_MNEM_SUFFIX
:
4193 i
.types
[op
].bitfield
.imm16
= 1;
4194 i
.types
[op
].bitfield
.imm32
= 1;
4195 i
.types
[op
].bitfield
.imm32s
= 1;
4196 i
.types
[op
].bitfield
.imm64
= 1;
4198 case BYTE_MNEM_SUFFIX
:
4199 i
.types
[op
].bitfield
.imm8
= 1;
4200 i
.types
[op
].bitfield
.imm8s
= 1;
4201 i
.types
[op
].bitfield
.imm16
= 1;
4202 i
.types
[op
].bitfield
.imm32
= 1;
4203 i
.types
[op
].bitfield
.imm32s
= 1;
4204 i
.types
[op
].bitfield
.imm64
= 1;
4208 /* If this operand is at most 16 bits, convert it
4209 to a signed 16 bit number before trying to see
4210 whether it will fit in an even smaller size.
4211 This allows a 16-bit operand such as $0xffe0 to
4212 be recognised as within Imm8S range. */
4213 if ((i
.types
[op
].bitfield
.imm16
)
4214 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4216 i
.op
[op
].imms
->X_add_number
=
4217 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4219 if ((i
.types
[op
].bitfield
.imm32
)
4220 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4223 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4224 ^ ((offsetT
) 1 << 31))
4225 - ((offsetT
) 1 << 31));
4228 = operand_type_or (i
.types
[op
],
4229 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4231 /* We must avoid matching of Imm32 templates when 64bit
4232 only immediate is available. */
4233 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4234 i
.types
[op
].bitfield
.imm32
= 0;
4241 /* Symbols and expressions. */
4243 /* Convert symbolic operand to proper sizes for matching, but don't
4244 prevent matching a set of insns that only supports sizes other
4245 than those matching the insn suffix. */
4247 i386_operand_type mask
, allowed
;
4248 const insn_template
*t
;
4250 operand_type_set (&mask
, 0);
4251 operand_type_set (&allowed
, 0);
4253 for (t
= current_templates
->start
;
4254 t
< current_templates
->end
;
4256 allowed
= operand_type_or (allowed
,
4257 t
->operand_types
[op
]);
4258 switch (guess_suffix
)
4260 case QWORD_MNEM_SUFFIX
:
4261 mask
.bitfield
.imm64
= 1;
4262 mask
.bitfield
.imm32s
= 1;
4264 case LONG_MNEM_SUFFIX
:
4265 mask
.bitfield
.imm32
= 1;
4267 case WORD_MNEM_SUFFIX
:
4268 mask
.bitfield
.imm16
= 1;
4270 case BYTE_MNEM_SUFFIX
:
4271 mask
.bitfield
.imm8
= 1;
4276 allowed
= operand_type_and (mask
, allowed
);
4277 if (!operand_type_all_zero (&allowed
))
4278 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4285 /* Try to use the smallest displacement type too. */
4287 optimize_disp (void)
4291 for (op
= i
.operands
; --op
>= 0;)
4292 if (operand_type_check (i
.types
[op
], disp
))
4294 if (i
.op
[op
].disps
->X_op
== O_constant
)
4296 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4298 if (i
.types
[op
].bitfield
.disp16
4299 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4301 /* If this operand is at most 16 bits, convert
4302 to a signed 16 bit number and don't use 64bit
4304 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4305 i
.types
[op
].bitfield
.disp64
= 0;
4307 if (i
.types
[op
].bitfield
.disp32
4308 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4310 /* If this operand is at most 32 bits, convert
4311 to a signed 32 bit number and don't use 64bit
4313 op_disp
&= (((offsetT
) 2 << 31) - 1);
4314 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4315 i
.types
[op
].bitfield
.disp64
= 0;
4317 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4319 i
.types
[op
].bitfield
.disp8
= 0;
4320 i
.types
[op
].bitfield
.disp16
= 0;
4321 i
.types
[op
].bitfield
.disp32
= 0;
4322 i
.types
[op
].bitfield
.disp32s
= 0;
4323 i
.types
[op
].bitfield
.disp64
= 0;
4327 else if (flag_code
== CODE_64BIT
)
4329 if (fits_in_signed_long (op_disp
))
4331 i
.types
[op
].bitfield
.disp64
= 0;
4332 i
.types
[op
].bitfield
.disp32s
= 1;
4334 if (i
.prefix
[ADDR_PREFIX
]
4335 && fits_in_unsigned_long (op_disp
))
4336 i
.types
[op
].bitfield
.disp32
= 1;
4338 if ((i
.types
[op
].bitfield
.disp32
4339 || i
.types
[op
].bitfield
.disp32s
4340 || i
.types
[op
].bitfield
.disp16
)
4341 && fits_in_signed_byte (op_disp
))
4342 i
.types
[op
].bitfield
.disp8
= 1;
4344 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4345 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4347 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4348 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4349 i
.types
[op
].bitfield
.disp8
= 0;
4350 i
.types
[op
].bitfield
.disp16
= 0;
4351 i
.types
[op
].bitfield
.disp32
= 0;
4352 i
.types
[op
].bitfield
.disp32s
= 0;
4353 i
.types
[op
].bitfield
.disp64
= 0;
4356 /* We only support 64bit displacement on constants. */
4357 i
.types
[op
].bitfield
.disp64
= 0;
4361 /* Check if operands are valid for the instruction. */
4364 check_VecOperands (const insn_template
*t
)
4368 /* Without VSIB byte, we can't have a vector register for index. */
4369 if (!t
->opcode_modifier
.vecsib
4371 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4372 || i
.index_reg
->reg_type
.bitfield
.regymm
4373 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4375 i
.error
= unsupported_vector_index_register
;
4379 /* Check if default mask is allowed. */
4380 if (t
->opcode_modifier
.nodefmask
4381 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4383 i
.error
= no_default_mask
;
4387 /* For VSIB byte, we need a vector register for index, and all vector
4388 registers must be distinct. */
4389 if (t
->opcode_modifier
.vecsib
)
4392 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4393 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4394 || (t
->opcode_modifier
.vecsib
== VecSIB256
4395 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4396 || (t
->opcode_modifier
.vecsib
== VecSIB512
4397 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4399 i
.error
= invalid_vsib_address
;
4403 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4404 if (i
.reg_operands
== 2 && !i
.mask
)
4406 gas_assert (i
.types
[0].bitfield
.regxmm
4407 || i
.types
[0].bitfield
.regymm
);
4408 gas_assert (i
.types
[2].bitfield
.regxmm
4409 || i
.types
[2].bitfield
.regymm
);
4410 if (operand_check
== check_none
)
4412 if (register_number (i
.op
[0].regs
)
4413 != register_number (i
.index_reg
)
4414 && register_number (i
.op
[2].regs
)
4415 != register_number (i
.index_reg
)
4416 && register_number (i
.op
[0].regs
)
4417 != register_number (i
.op
[2].regs
))
4419 if (operand_check
== check_error
)
4421 i
.error
= invalid_vector_register_set
;
4424 as_warn (_("mask, index, and destination registers should be distinct"));
4426 else if (i
.reg_operands
== 1 && i
.mask
)
4428 if ((i
.types
[1].bitfield
.regymm
4429 || i
.types
[1].bitfield
.regzmm
)
4430 && (register_number (i
.op
[1].regs
)
4431 == register_number (i
.index_reg
)))
4433 if (operand_check
== check_error
)
4435 i
.error
= invalid_vector_register_set
;
4438 if (operand_check
!= check_none
)
4439 as_warn (_("index and destination registers should be distinct"));
4444 /* Check if broadcast is supported by the instruction and is applied
4445 to the memory operand. */
4448 int broadcasted_opnd_size
;
4450 /* Check if specified broadcast is supported in this instruction,
4451 and it's applied to memory operand of DWORD or QWORD type,
4452 depending on VecESize. */
4453 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4454 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4455 || (t
->opcode_modifier
.vecesize
== 0
4456 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4457 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4458 || (t
->opcode_modifier
.vecesize
== 1
4459 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4460 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4463 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4464 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4465 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4466 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4467 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4468 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4469 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4470 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4471 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4475 if ((broadcasted_opnd_size
== 256
4476 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4477 || (broadcasted_opnd_size
== 512
4478 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4481 i
.error
= unsupported_broadcast
;
4485 /* If broadcast is supported in this instruction, we need to check if
4486 operand of one-element size isn't specified without broadcast. */
4487 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4489 /* Find memory operand. */
4490 for (op
= 0; op
< i
.operands
; op
++)
4491 if (operand_type_check (i
.types
[op
], anymem
))
4493 gas_assert (op
< i
.operands
);
4494 /* Check size of the memory operand. */
4495 if ((t
->opcode_modifier
.vecesize
== 0
4496 && i
.types
[op
].bitfield
.dword
)
4497 || (t
->opcode_modifier
.vecesize
== 1
4498 && i
.types
[op
].bitfield
.qword
))
4500 i
.error
= broadcast_needed
;
4505 /* Check if requested masking is supported. */
4507 && (!t
->opcode_modifier
.masking
4509 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4511 i
.error
= unsupported_masking
;
4515 /* Check if masking is applied to dest operand. */
4516 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4518 i
.error
= mask_not_on_destination
;
4525 if ((i
.rounding
->type
!= saeonly
4526 && !t
->opcode_modifier
.staticrounding
)
4527 || (i
.rounding
->type
== saeonly
4528 && (t
->opcode_modifier
.staticrounding
4529 || !t
->opcode_modifier
.sae
)))
4531 i
.error
= unsupported_rc_sae
;
4534 /* If the instruction has several immediate operands and one of
4535 them is rounding, the rounding operand should be the last
4536 immediate operand. */
4537 if (i
.imm_operands
> 1
4538 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4540 i
.error
= rc_sae_operand_not_last_imm
;
4545 /* Check vector Disp8 operand. */
4546 if (t
->opcode_modifier
.disp8memshift
)
4549 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4551 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4553 for (op
= 0; op
< i
.operands
; op
++)
4554 if (operand_type_check (i
.types
[op
], disp
)
4555 && i
.op
[op
].disps
->X_op
== O_constant
)
4557 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4558 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4559 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4562 i
.types
[op
].bitfield
.vec_disp8
= 1;
4565 /* Vector insn can only have Vec_Disp8/Disp32 in
4566 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4568 i
.types
[op
].bitfield
.disp8
= 0;
4569 if (flag_code
!= CODE_16BIT
)
4570 i
.types
[op
].bitfield
.disp16
= 0;
4573 else if (flag_code
!= CODE_16BIT
)
4575 /* One form of this instruction supports vector Disp8.
4576 Try vector Disp8 if we need to use Disp32. */
4577 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4579 i
.error
= try_vector_disp8
;
4591 /* Check if operands are valid for the instruction. Update VEX
4595 VEX_check_operands (const insn_template
*t
)
4597 /* VREX is only valid with EVEX prefix. */
4598 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4600 i
.error
= invalid_register_operand
;
4604 if (!t
->opcode_modifier
.vex
)
4607 /* Only check VEX_Imm4, which must be the first operand. */
4608 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4610 if (i
.op
[0].imms
->X_op
!= O_constant
4611 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4617 /* Turn off Imm8 so that update_imm won't complain. */
4618 i
.types
[0] = vec_imm4
;
4624 static const insn_template
*
4625 match_template (void)
4627 /* Points to template once we've found it. */
4628 const insn_template
*t
;
4629 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4630 i386_operand_type overlap4
;
4631 unsigned int found_reverse_match
;
4632 i386_opcode_modifier suffix_check
;
4633 i386_operand_type operand_types
[MAX_OPERANDS
];
4634 int addr_prefix_disp
;
4636 unsigned int found_cpu_match
;
4637 unsigned int check_register
;
4638 enum i386_error specific_error
= 0;
4640 #if MAX_OPERANDS != 5
4641 # error "MAX_OPERANDS must be 5."
4644 found_reverse_match
= 0;
4645 addr_prefix_disp
= -1;
4647 memset (&suffix_check
, 0, sizeof (suffix_check
));
4648 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4649 suffix_check
.no_bsuf
= 1;
4650 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4651 suffix_check
.no_wsuf
= 1;
4652 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4653 suffix_check
.no_ssuf
= 1;
4654 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4655 suffix_check
.no_lsuf
= 1;
4656 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4657 suffix_check
.no_qsuf
= 1;
4658 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4659 suffix_check
.no_ldsuf
= 1;
4661 /* Must have right number of operands. */
4662 i
.error
= number_of_operands_mismatch
;
4664 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4666 addr_prefix_disp
= -1;
4668 if (i
.operands
!= t
->operands
)
4671 /* Check processor support. */
4672 i
.error
= unsupported
;
4673 found_cpu_match
= (cpu_flags_match (t
)
4674 == CPU_FLAGS_PERFECT_MATCH
);
4675 if (!found_cpu_match
)
4678 /* Check old gcc support. */
4679 i
.error
= old_gcc_only
;
4680 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4683 /* Check AT&T mnemonic. */
4684 i
.error
= unsupported_with_intel_mnemonic
;
4685 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4688 /* Check AT&T/Intel syntax. */
4689 i
.error
= unsupported_syntax
;
4690 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4691 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4694 /* Check the suffix, except for some instructions in intel mode. */
4695 i
.error
= invalid_instruction_suffix
;
4696 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4697 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4698 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4699 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4700 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4701 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4702 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4705 if (!operand_size_match (t
))
4708 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4709 operand_types
[j
] = t
->operand_types
[j
];
4711 /* In general, don't allow 64-bit operands in 32-bit mode. */
4712 if (i
.suffix
== QWORD_MNEM_SUFFIX
4713 && flag_code
!= CODE_64BIT
4715 ? (!t
->opcode_modifier
.ignoresize
4716 && !intel_float_operand (t
->name
))
4717 : intel_float_operand (t
->name
) != 2)
4718 && ((!operand_types
[0].bitfield
.regmmx
4719 && !operand_types
[0].bitfield
.regxmm
4720 && !operand_types
[0].bitfield
.regymm
4721 && !operand_types
[0].bitfield
.regzmm
)
4722 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4723 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4724 && operand_types
[t
->operands
> 1].bitfield
.regymm
4725 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4726 && (t
->base_opcode
!= 0x0fc7
4727 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4730 /* In general, don't allow 32-bit operands on pre-386. */
4731 else if (i
.suffix
== LONG_MNEM_SUFFIX
4732 && !cpu_arch_flags
.bitfield
.cpui386
4734 ? (!t
->opcode_modifier
.ignoresize
4735 && !intel_float_operand (t
->name
))
4736 : intel_float_operand (t
->name
) != 2)
4737 && ((!operand_types
[0].bitfield
.regmmx
4738 && !operand_types
[0].bitfield
.regxmm
)
4739 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4740 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4743 /* Do not verify operands when there are none. */
4747 /* We've found a match; break out of loop. */
4751 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4752 into Disp32/Disp16/Disp32 operand. */
4753 if (i
.prefix
[ADDR_PREFIX
] != 0)
4755 /* There should be only one Disp operand. */
4759 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4761 if (operand_types
[j
].bitfield
.disp16
)
4763 addr_prefix_disp
= j
;
4764 operand_types
[j
].bitfield
.disp32
= 1;
4765 operand_types
[j
].bitfield
.disp16
= 0;
4771 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4773 if (operand_types
[j
].bitfield
.disp32
)
4775 addr_prefix_disp
= j
;
4776 operand_types
[j
].bitfield
.disp32
= 0;
4777 operand_types
[j
].bitfield
.disp16
= 1;
4783 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4785 if (operand_types
[j
].bitfield
.disp64
)
4787 addr_prefix_disp
= j
;
4788 operand_types
[j
].bitfield
.disp64
= 0;
4789 operand_types
[j
].bitfield
.disp32
= 1;
4797 /* We check register size if needed. */
4798 check_register
= t
->opcode_modifier
.checkregsize
;
4799 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4800 switch (t
->operands
)
4803 if (!operand_type_match (overlap0
, i
.types
[0]))
4807 /* xchg %eax, %eax is a special case. It is an aliase for nop
4808 only in 32bit mode and we can use opcode 0x90. In 64bit
4809 mode, we can't use 0x90 for xchg %eax, %eax since it should
4810 zero-extend %eax to %rax. */
4811 if (flag_code
== CODE_64BIT
4812 && t
->base_opcode
== 0x90
4813 && operand_type_equal (&i
.types
[0], &acc32
)
4814 && operand_type_equal (&i
.types
[1], &acc32
))
4818 /* If we swap operand in encoding, we either match
4819 the next one or reverse direction of operands. */
4820 if (t
->opcode_modifier
.s
)
4822 else if (t
->opcode_modifier
.d
)
4827 /* If we swap operand in encoding, we match the next one. */
4828 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4832 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4833 if (!operand_type_match (overlap0
, i
.types
[0])
4834 || !operand_type_match (overlap1
, i
.types
[1])
4836 && !operand_type_register_match (overlap0
, i
.types
[0],
4838 overlap1
, i
.types
[1],
4841 /* Check if other direction is valid ... */
4842 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4846 /* Try reversing direction of operands. */
4847 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4848 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4849 if (!operand_type_match (overlap0
, i
.types
[0])
4850 || !operand_type_match (overlap1
, i
.types
[1])
4852 && !operand_type_register_match (overlap0
,
4859 /* Does not match either direction. */
4862 /* found_reverse_match holds which of D or FloatDR
4864 if (t
->opcode_modifier
.d
)
4865 found_reverse_match
= Opcode_D
;
4866 else if (t
->opcode_modifier
.floatd
)
4867 found_reverse_match
= Opcode_FloatD
;
4869 found_reverse_match
= 0;
4870 if (t
->opcode_modifier
.floatr
)
4871 found_reverse_match
|= Opcode_FloatR
;
4875 /* Found a forward 2 operand match here. */
4876 switch (t
->operands
)
4879 overlap4
= operand_type_and (i
.types
[4],
4882 overlap3
= operand_type_and (i
.types
[3],
4885 overlap2
= operand_type_and (i
.types
[2],
4890 switch (t
->operands
)
4893 if (!operand_type_match (overlap4
, i
.types
[4])
4894 || !operand_type_register_match (overlap3
,
4902 if (!operand_type_match (overlap3
, i
.types
[3])
4904 && !operand_type_register_match (overlap2
,
4912 /* Here we make use of the fact that there are no
4913 reverse match 3 operand instructions, and all 3
4914 operand instructions only need to be checked for
4915 register consistency between operands 2 and 3. */
4916 if (!operand_type_match (overlap2
, i
.types
[2])
4918 && !operand_type_register_match (overlap1
,
4928 /* Found either forward/reverse 2, 3 or 4 operand match here:
4929 slip through to break. */
4931 if (!found_cpu_match
)
4933 found_reverse_match
= 0;
4937 /* Check if vector and VEX operands are valid. */
4938 if (check_VecOperands (t
) || VEX_check_operands (t
))
4940 specific_error
= i
.error
;
4944 /* We've found a match; break out of loop. */
4948 if (t
== current_templates
->end
)
4950 /* We found no match. */
4951 const char *err_msg
;
4952 switch (specific_error
? specific_error
: i
.error
)
4956 case operand_size_mismatch
:
4957 err_msg
= _("operand size mismatch");
4959 case operand_type_mismatch
:
4960 err_msg
= _("operand type mismatch");
4962 case register_type_mismatch
:
4963 err_msg
= _("register type mismatch");
4965 case number_of_operands_mismatch
:
4966 err_msg
= _("number of operands mismatch");
4968 case invalid_instruction_suffix
:
4969 err_msg
= _("invalid instruction suffix");
4972 err_msg
= _("constant doesn't fit in 4 bits");
4975 err_msg
= _("only supported with old gcc");
4977 case unsupported_with_intel_mnemonic
:
4978 err_msg
= _("unsupported with Intel mnemonic");
4980 case unsupported_syntax
:
4981 err_msg
= _("unsupported syntax");
4984 as_bad (_("unsupported instruction `%s'"),
4985 current_templates
->start
->name
);
4987 case invalid_vsib_address
:
4988 err_msg
= _("invalid VSIB address");
4990 case invalid_vector_register_set
:
4991 err_msg
= _("mask, index, and destination registers must be distinct");
4993 case unsupported_vector_index_register
:
4994 err_msg
= _("unsupported vector index register");
4996 case unsupported_broadcast
:
4997 err_msg
= _("unsupported broadcast");
4999 case broadcast_not_on_src_operand
:
5000 err_msg
= _("broadcast not on source memory operand");
5002 case broadcast_needed
:
5003 err_msg
= _("broadcast is needed for operand of such type");
5005 case unsupported_masking
:
5006 err_msg
= _("unsupported masking");
5008 case mask_not_on_destination
:
5009 err_msg
= _("mask not on destination operand");
5011 case no_default_mask
:
5012 err_msg
= _("default mask isn't allowed");
5014 case unsupported_rc_sae
:
5015 err_msg
= _("unsupported static rounding/sae");
5017 case rc_sae_operand_not_last_imm
:
5019 err_msg
= _("RC/SAE operand must precede immediate operands");
5021 err_msg
= _("RC/SAE operand must follow immediate operands");
5023 case invalid_register_operand
:
5024 err_msg
= _("invalid register operand");
5027 as_bad (_("%s for `%s'"), err_msg
,
5028 current_templates
->start
->name
);
5032 if (!quiet_warnings
)
5035 && (i
.types
[0].bitfield
.jumpabsolute
5036 != operand_types
[0].bitfield
.jumpabsolute
))
5038 as_warn (_("indirect %s without `*'"), t
->name
);
5041 if (t
->opcode_modifier
.isprefix
5042 && t
->opcode_modifier
.ignoresize
)
5044 /* Warn them that a data or address size prefix doesn't
5045 affect assembly of the next line of code. */
5046 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5050 /* Copy the template we found. */
5053 if (addr_prefix_disp
!= -1)
5054 i
.tm
.operand_types
[addr_prefix_disp
]
5055 = operand_types
[addr_prefix_disp
];
5057 if (found_reverse_match
)
5059 /* If we found a reverse match we must alter the opcode
5060 direction bit. found_reverse_match holds bits to change
5061 (different for int & float insns). */
5063 i
.tm
.base_opcode
^= found_reverse_match
;
5065 i
.tm
.operand_types
[0] = operand_types
[1];
5066 i
.tm
.operand_types
[1] = operand_types
[0];
5075 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5076 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5078 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5080 as_bad (_("`%s' operand %d must use `%ses' segment"),
5086 /* There's only ever one segment override allowed per instruction.
5087 This instruction possibly has a legal segment override on the
5088 second operand, so copy the segment to where non-string
5089 instructions store it, allowing common code. */
5090 i
.seg
[0] = i
.seg
[1];
5092 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5094 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5096 as_bad (_("`%s' operand %d must use `%ses' segment"),
5107 process_suffix (void)
5109 /* If matched instruction specifies an explicit instruction mnemonic
5111 if (i
.tm
.opcode_modifier
.size16
)
5112 i
.suffix
= WORD_MNEM_SUFFIX
;
5113 else if (i
.tm
.opcode_modifier
.size32
)
5114 i
.suffix
= LONG_MNEM_SUFFIX
;
5115 else if (i
.tm
.opcode_modifier
.size64
)
5116 i
.suffix
= QWORD_MNEM_SUFFIX
;
5117 else if (i
.reg_operands
)
5119 /* If there's no instruction mnemonic suffix we try to invent one
5120 based on register operands. */
5123 /* We take i.suffix from the last register operand specified,
5124 Destination register type is more significant than source
5125 register type. crc32 in SSE4.2 prefers source register
5127 if (i
.tm
.base_opcode
== 0xf20f38f1)
5129 if (i
.types
[0].bitfield
.reg16
)
5130 i
.suffix
= WORD_MNEM_SUFFIX
;
5131 else if (i
.types
[0].bitfield
.reg32
)
5132 i
.suffix
= LONG_MNEM_SUFFIX
;
5133 else if (i
.types
[0].bitfield
.reg64
)
5134 i
.suffix
= QWORD_MNEM_SUFFIX
;
5136 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5138 if (i
.types
[0].bitfield
.reg8
)
5139 i
.suffix
= BYTE_MNEM_SUFFIX
;
5146 if (i
.tm
.base_opcode
== 0xf20f38f1
5147 || i
.tm
.base_opcode
== 0xf20f38f0)
5149 /* We have to know the operand size for crc32. */
5150 as_bad (_("ambiguous memory operand size for `%s`"),
5155 for (op
= i
.operands
; --op
>= 0;)
5156 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5158 if (i
.types
[op
].bitfield
.reg8
)
5160 i
.suffix
= BYTE_MNEM_SUFFIX
;
5163 else if (i
.types
[op
].bitfield
.reg16
)
5165 i
.suffix
= WORD_MNEM_SUFFIX
;
5168 else if (i
.types
[op
].bitfield
.reg32
)
5170 i
.suffix
= LONG_MNEM_SUFFIX
;
5173 else if (i
.types
[op
].bitfield
.reg64
)
5175 i
.suffix
= QWORD_MNEM_SUFFIX
;
5181 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5184 && i
.tm
.opcode_modifier
.ignoresize
5185 && i
.tm
.opcode_modifier
.no_bsuf
)
5187 else if (!check_byte_reg ())
5190 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5193 && i
.tm
.opcode_modifier
.ignoresize
5194 && i
.tm
.opcode_modifier
.no_lsuf
)
5196 else if (!check_long_reg ())
5199 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5202 && i
.tm
.opcode_modifier
.ignoresize
5203 && i
.tm
.opcode_modifier
.no_qsuf
)
5205 else if (!check_qword_reg ())
5208 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5211 && i
.tm
.opcode_modifier
.ignoresize
5212 && i
.tm
.opcode_modifier
.no_wsuf
)
5214 else if (!check_word_reg ())
5217 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5218 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5219 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5221 /* Skip if the instruction has x/y/z suffix. match_template
5222 should check if it is a valid suffix. */
5224 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5225 /* Do nothing if the instruction is going to ignore the prefix. */
5230 else if (i
.tm
.opcode_modifier
.defaultsize
5232 /* exclude fldenv/frstor/fsave/fstenv */
5233 && i
.tm
.opcode_modifier
.no_ssuf
)
5235 i
.suffix
= stackop_size
;
5237 else if (intel_syntax
5239 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5240 || i
.tm
.opcode_modifier
.jumpbyte
5241 || i
.tm
.opcode_modifier
.jumpintersegment
5242 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5243 && i
.tm
.extension_opcode
<= 3)))
5248 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5250 i
.suffix
= QWORD_MNEM_SUFFIX
;
5254 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5255 i
.suffix
= LONG_MNEM_SUFFIX
;
5258 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5259 i
.suffix
= WORD_MNEM_SUFFIX
;
5268 if (i
.tm
.opcode_modifier
.w
)
5270 as_bad (_("no instruction mnemonic suffix given and "
5271 "no register operands; can't size instruction"));
5277 unsigned int suffixes
;
5279 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5280 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5282 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5284 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5286 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5288 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5291 /* There are more than suffix matches. */
5292 if (i
.tm
.opcode_modifier
.w
5293 || ((suffixes
& (suffixes
- 1))
5294 && !i
.tm
.opcode_modifier
.defaultsize
5295 && !i
.tm
.opcode_modifier
.ignoresize
))
5297 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5303 /* Change the opcode based on the operand size given by i.suffix;
5304 We don't need to change things for byte insns. */
5307 && i
.suffix
!= BYTE_MNEM_SUFFIX
5308 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5309 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5310 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5312 /* It's not a byte, select word/dword operation. */
5313 if (i
.tm
.opcode_modifier
.w
)
5315 if (i
.tm
.opcode_modifier
.shortform
)
5316 i
.tm
.base_opcode
|= 8;
5318 i
.tm
.base_opcode
|= 1;
5321 /* Now select between word & dword operations via the operand
5322 size prefix, except for instructions that will ignore this
5324 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5326 /* The address size override prefix changes the size of the
5328 if ((flag_code
== CODE_32BIT
5329 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5330 || (flag_code
!= CODE_32BIT
5331 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5332 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5335 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5336 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5337 && !i
.tm
.opcode_modifier
.ignoresize
5338 && !i
.tm
.opcode_modifier
.floatmf
5339 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5340 || (flag_code
== CODE_64BIT
5341 && i
.tm
.opcode_modifier
.jumpbyte
)))
5343 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5345 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5346 prefix
= ADDR_PREFIX_OPCODE
;
5348 if (!add_prefix (prefix
))
5352 /* Set mode64 for an operand. */
5353 if (i
.suffix
== QWORD_MNEM_SUFFIX
5354 && flag_code
== CODE_64BIT
5355 && !i
.tm
.opcode_modifier
.norex64
)
5357 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5358 need rex64. cmpxchg8b is also a special case. */
5359 if (! (i
.operands
== 2
5360 && i
.tm
.base_opcode
== 0x90
5361 && i
.tm
.extension_opcode
== None
5362 && operand_type_equal (&i
.types
[0], &acc64
)
5363 && operand_type_equal (&i
.types
[1], &acc64
))
5364 && ! (i
.operands
== 1
5365 && i
.tm
.base_opcode
== 0xfc7
5366 && i
.tm
.extension_opcode
== 1
5367 && !operand_type_check (i
.types
[0], reg
)
5368 && operand_type_check (i
.types
[0], anymem
)))
5372 /* Size floating point instruction. */
5373 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5374 if (i
.tm
.opcode_modifier
.floatmf
)
5375 i
.tm
.base_opcode
^= 4;
5382 check_byte_reg (void)
5386 for (op
= i
.operands
; --op
>= 0;)
5388 /* If this is an eight bit register, it's OK. If it's the 16 or
5389 32 bit version of an eight bit register, we will just use the
5390 low portion, and that's OK too. */
5391 if (i
.types
[op
].bitfield
.reg8
)
5394 /* I/O port address operands are OK too. */
5395 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5398 /* crc32 doesn't generate this warning. */
5399 if (i
.tm
.base_opcode
== 0xf20f38f0)
5402 if ((i
.types
[op
].bitfield
.reg16
5403 || i
.types
[op
].bitfield
.reg32
5404 || i
.types
[op
].bitfield
.reg64
)
5405 && i
.op
[op
].regs
->reg_num
< 4
5406 /* Prohibit these changes in 64bit mode, since the lowering
5407 would be more complicated. */
5408 && flag_code
!= CODE_64BIT
)
5410 #if REGISTER_WARNINGS
5411 if (!quiet_warnings
)
5412 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5414 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5415 ? REGNAM_AL
- REGNAM_AX
5416 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5418 i
.op
[op
].regs
->reg_name
,
5423 /* Any other register is bad. */
5424 if (i
.types
[op
].bitfield
.reg16
5425 || i
.types
[op
].bitfield
.reg32
5426 || i
.types
[op
].bitfield
.reg64
5427 || i
.types
[op
].bitfield
.regmmx
5428 || i
.types
[op
].bitfield
.regxmm
5429 || i
.types
[op
].bitfield
.regymm
5430 || i
.types
[op
].bitfield
.regzmm
5431 || i
.types
[op
].bitfield
.sreg2
5432 || i
.types
[op
].bitfield
.sreg3
5433 || i
.types
[op
].bitfield
.control
5434 || i
.types
[op
].bitfield
.debug
5435 || i
.types
[op
].bitfield
.test
5436 || i
.types
[op
].bitfield
.floatreg
5437 || i
.types
[op
].bitfield
.floatacc
)
5439 as_bad (_("`%s%s' not allowed with `%s%c'"),
5441 i
.op
[op
].regs
->reg_name
,
5451 check_long_reg (void)
5455 for (op
= i
.operands
; --op
>= 0;)
5456 /* Reject eight bit registers, except where the template requires
5457 them. (eg. movzb) */
5458 if (i
.types
[op
].bitfield
.reg8
5459 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5460 || i
.tm
.operand_types
[op
].bitfield
.reg32
5461 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5463 as_bad (_("`%s%s' not allowed with `%s%c'"),
5465 i
.op
[op
].regs
->reg_name
,
5470 /* Warn if the e prefix on a general reg is missing. */
5471 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5472 && i
.types
[op
].bitfield
.reg16
5473 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5474 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5476 /* Prohibit these changes in the 64bit mode, since the
5477 lowering is more complicated. */
5478 if (flag_code
== CODE_64BIT
)
5480 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5481 register_prefix
, i
.op
[op
].regs
->reg_name
,
5485 #if REGISTER_WARNINGS
5486 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5488 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5489 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5492 /* Warn if the r prefix on a general reg is present. */
5493 else if (i
.types
[op
].bitfield
.reg64
5494 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5495 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5498 && i
.tm
.opcode_modifier
.toqword
5499 && !i
.types
[0].bitfield
.regxmm
)
5501 /* Convert to QWORD. We want REX byte. */
5502 i
.suffix
= QWORD_MNEM_SUFFIX
;
5506 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5507 register_prefix
, i
.op
[op
].regs
->reg_name
,
5516 check_qword_reg (void)
5520 for (op
= i
.operands
; --op
>= 0; )
5521 /* Reject eight bit registers, except where the template requires
5522 them. (eg. movzb) */
5523 if (i
.types
[op
].bitfield
.reg8
5524 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5525 || i
.tm
.operand_types
[op
].bitfield
.reg32
5526 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5528 as_bad (_("`%s%s' not allowed with `%s%c'"),
5530 i
.op
[op
].regs
->reg_name
,
5535 /* Warn if the r prefix on a general reg is missing. */
5536 else if ((i
.types
[op
].bitfield
.reg16
5537 || i
.types
[op
].bitfield
.reg32
)
5538 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5539 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5541 /* Prohibit these changes in the 64bit mode, since the
5542 lowering is more complicated. */
5544 && i
.tm
.opcode_modifier
.todword
5545 && !i
.types
[0].bitfield
.regxmm
)
5547 /* Convert to DWORD. We don't want REX byte. */
5548 i
.suffix
= LONG_MNEM_SUFFIX
;
5552 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5553 register_prefix
, i
.op
[op
].regs
->reg_name
,
5562 check_word_reg (void)
5565 for (op
= i
.operands
; --op
>= 0;)
5566 /* Reject eight bit registers, except where the template requires
5567 them. (eg. movzb) */
5568 if (i
.types
[op
].bitfield
.reg8
5569 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5570 || i
.tm
.operand_types
[op
].bitfield
.reg32
5571 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5573 as_bad (_("`%s%s' not allowed with `%s%c'"),
5575 i
.op
[op
].regs
->reg_name
,
5580 /* Warn if the e or r prefix on a general reg is present. */
5581 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5582 && (i
.types
[op
].bitfield
.reg32
5583 || i
.types
[op
].bitfield
.reg64
)
5584 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5585 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5587 /* Prohibit these changes in the 64bit mode, since the
5588 lowering is more complicated. */
5589 if (flag_code
== CODE_64BIT
)
5591 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5592 register_prefix
, i
.op
[op
].regs
->reg_name
,
5596 #if REGISTER_WARNINGS
5597 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5599 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5600 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5607 update_imm (unsigned int j
)
5609 i386_operand_type overlap
= i
.types
[j
];
5610 if ((overlap
.bitfield
.imm8
5611 || overlap
.bitfield
.imm8s
5612 || overlap
.bitfield
.imm16
5613 || overlap
.bitfield
.imm32
5614 || overlap
.bitfield
.imm32s
5615 || overlap
.bitfield
.imm64
)
5616 && !operand_type_equal (&overlap
, &imm8
)
5617 && !operand_type_equal (&overlap
, &imm8s
)
5618 && !operand_type_equal (&overlap
, &imm16
)
5619 && !operand_type_equal (&overlap
, &imm32
)
5620 && !operand_type_equal (&overlap
, &imm32s
)
5621 && !operand_type_equal (&overlap
, &imm64
))
5625 i386_operand_type temp
;
5627 operand_type_set (&temp
, 0);
5628 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5630 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5631 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5633 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5634 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5635 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5637 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5638 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5641 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5644 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5645 || operand_type_equal (&overlap
, &imm16_32
)
5646 || operand_type_equal (&overlap
, &imm16_32s
))
5648 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5653 if (!operand_type_equal (&overlap
, &imm8
)
5654 && !operand_type_equal (&overlap
, &imm8s
)
5655 && !operand_type_equal (&overlap
, &imm16
)
5656 && !operand_type_equal (&overlap
, &imm32
)
5657 && !operand_type_equal (&overlap
, &imm32s
)
5658 && !operand_type_equal (&overlap
, &imm64
))
5660 as_bad (_("no instruction mnemonic suffix given; "
5661 "can't determine immediate size"));
5665 i
.types
[j
] = overlap
;
5675 /* Update the first 2 immediate operands. */
5676 n
= i
.operands
> 2 ? 2 : i
.operands
;
5679 for (j
= 0; j
< n
; j
++)
5680 if (update_imm (j
) == 0)
5683 /* The 3rd operand can't be immediate operand. */
5684 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5691 bad_implicit_operand (int xmm
)
5693 const char *ireg
= xmm
? "xmm0" : "ymm0";
5696 as_bad (_("the last operand of `%s' must be `%s%s'"),
5697 i
.tm
.name
, register_prefix
, ireg
);
5699 as_bad (_("the first operand of `%s' must be `%s%s'"),
5700 i
.tm
.name
, register_prefix
, ireg
);
5705 process_operands (void)
5707 /* Default segment register this instruction will use for memory
5708 accesses. 0 means unknown. This is only for optimizing out
5709 unnecessary segment overrides. */
5710 const seg_entry
*default_seg
= 0;
5712 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5714 unsigned int dupl
= i
.operands
;
5715 unsigned int dest
= dupl
- 1;
5718 /* The destination must be an xmm register. */
5719 gas_assert (i
.reg_operands
5720 && MAX_OPERANDS
> dupl
5721 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5723 if (i
.tm
.opcode_modifier
.firstxmm0
)
5725 /* The first operand is implicit and must be xmm0. */
5726 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5727 if (register_number (i
.op
[0].regs
) != 0)
5728 return bad_implicit_operand (1);
5730 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5732 /* Keep xmm0 for instructions with VEX prefix and 3
5738 /* We remove the first xmm0 and keep the number of
5739 operands unchanged, which in fact duplicates the
5741 for (j
= 1; j
< i
.operands
; j
++)
5743 i
.op
[j
- 1] = i
.op
[j
];
5744 i
.types
[j
- 1] = i
.types
[j
];
5745 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5749 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5751 gas_assert ((MAX_OPERANDS
- 1) > dupl
5752 && (i
.tm
.opcode_modifier
.vexsources
5755 /* Add the implicit xmm0 for instructions with VEX prefix
5757 for (j
= i
.operands
; j
> 0; j
--)
5759 i
.op
[j
] = i
.op
[j
- 1];
5760 i
.types
[j
] = i
.types
[j
- 1];
5761 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5764 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5765 i
.types
[0] = regxmm
;
5766 i
.tm
.operand_types
[0] = regxmm
;
5769 i
.reg_operands
+= 2;
5774 i
.op
[dupl
] = i
.op
[dest
];
5775 i
.types
[dupl
] = i
.types
[dest
];
5776 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5785 i
.op
[dupl
] = i
.op
[dest
];
5786 i
.types
[dupl
] = i
.types
[dest
];
5787 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5790 if (i
.tm
.opcode_modifier
.immext
)
5793 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5797 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5798 gas_assert (i
.reg_operands
5799 && (operand_type_equal (&i
.types
[0], ®xmm
)
5800 || operand_type_equal (&i
.types
[0], ®ymm
)
5801 || operand_type_equal (&i
.types
[0], ®zmm
)));
5802 if (register_number (i
.op
[0].regs
) != 0)
5803 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5805 for (j
= 1; j
< i
.operands
; j
++)
5807 i
.op
[j
- 1] = i
.op
[j
];
5808 i
.types
[j
- 1] = i
.types
[j
];
5810 /* We need to adjust fields in i.tm since they are used by
5811 build_modrm_byte. */
5812 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5819 else if (i
.tm
.opcode_modifier
.regkludge
)
5821 /* The imul $imm, %reg instruction is converted into
5822 imul $imm, %reg, %reg, and the clr %reg instruction
5823 is converted into xor %reg, %reg. */
5825 unsigned int first_reg_op
;
5827 if (operand_type_check (i
.types
[0], reg
))
5831 /* Pretend we saw the extra register operand. */
5832 gas_assert (i
.reg_operands
== 1
5833 && i
.op
[first_reg_op
+ 1].regs
== 0);
5834 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5835 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5840 if (i
.tm
.opcode_modifier
.shortform
)
5842 if (i
.types
[0].bitfield
.sreg2
5843 || i
.types
[0].bitfield
.sreg3
)
5845 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5846 && i
.op
[0].regs
->reg_num
== 1)
5848 as_bad (_("you can't `pop %scs'"), register_prefix
);
5851 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5852 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5857 /* The register or float register operand is in operand
5861 if (i
.types
[0].bitfield
.floatreg
5862 || operand_type_check (i
.types
[0], reg
))
5866 /* Register goes in low 3 bits of opcode. */
5867 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5868 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5870 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5872 /* Warn about some common errors, but press on regardless.
5873 The first case can be generated by gcc (<= 2.8.1). */
5874 if (i
.operands
== 2)
5876 /* Reversed arguments on faddp, fsubp, etc. */
5877 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5878 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5879 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5883 /* Extraneous `l' suffix on fp insn. */
5884 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5885 register_prefix
, i
.op
[0].regs
->reg_name
);
5890 else if (i
.tm
.opcode_modifier
.modrm
)
5892 /* The opcode is completed (modulo i.tm.extension_opcode which
5893 must be put into the modrm byte). Now, we make the modrm and
5894 index base bytes based on all the info we've collected. */
5896 default_seg
= build_modrm_byte ();
5898 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5902 else if (i
.tm
.opcode_modifier
.isstring
)
5904 /* For the string instructions that allow a segment override
5905 on one of their operands, the default segment is ds. */
5909 if (i
.tm
.base_opcode
== 0x8d /* lea */
5912 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5914 /* If a segment was explicitly specified, and the specified segment
5915 is not the default, use an opcode prefix to select it. If we
5916 never figured out what the default segment is, then default_seg
5917 will be zero at this point, and the specified segment prefix will
5919 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5921 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5927 static const seg_entry
*
5928 build_modrm_byte (void)
5930 const seg_entry
*default_seg
= 0;
5931 unsigned int source
, dest
;
5934 /* The first operand of instructions with VEX prefix and 3 sources
5935 must be VEX_Imm4. */
5936 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5939 unsigned int nds
, reg_slot
;
5942 if (i
.tm
.opcode_modifier
.veximmext
5943 && i
.tm
.opcode_modifier
.immext
)
5945 dest
= i
.operands
- 2;
5946 gas_assert (dest
== 3);
5949 dest
= i
.operands
- 1;
5952 /* There are 2 kinds of instructions:
5953 1. 5 operands: 4 register operands or 3 register operands
5954 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5955 VexW0 or VexW1. The destination must be either XMM, YMM or
5957 2. 4 operands: 4 register operands or 3 register operands
5958 plus 1 memory operand, VexXDS, and VexImmExt */
5959 gas_assert ((i
.reg_operands
== 4
5960 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5961 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5962 && (i
.tm
.opcode_modifier
.veximmext
5963 || (i
.imm_operands
== 1
5964 && i
.types
[0].bitfield
.vec_imm4
5965 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5966 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5967 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5968 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5969 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5971 if (i
.imm_operands
== 0)
5973 /* When there is no immediate operand, generate an 8bit
5974 immediate operand to encode the first operand. */
5975 exp
= &im_expressions
[i
.imm_operands
++];
5976 i
.op
[i
.operands
].imms
= exp
;
5977 i
.types
[i
.operands
] = imm8
;
5979 /* If VexW1 is set, the first operand is the source and
5980 the second operand is encoded in the immediate operand. */
5981 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5992 /* FMA swaps REG and NDS. */
5993 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6001 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6003 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6005 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6007 exp
->X_op
= O_constant
;
6008 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6009 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6013 unsigned int imm_slot
;
6015 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6017 /* If VexW0 is set, the third operand is the source and
6018 the second operand is encoded in the immediate
6025 /* VexW1 is set, the second operand is the source and
6026 the third operand is encoded in the immediate
6032 if (i
.tm
.opcode_modifier
.immext
)
6034 /* When ImmExt is set, the immdiate byte is the last
6036 imm_slot
= i
.operands
- 1;
6044 /* Turn on Imm8 so that output_imm will generate it. */
6045 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6048 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6050 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6052 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6054 i
.op
[imm_slot
].imms
->X_add_number
6055 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6056 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6059 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6060 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6062 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6064 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6069 /* i.reg_operands MUST be the number of real register operands;
6070 implicit registers do not count. If there are 3 register
6071 operands, it must be a instruction with VexNDS. For a
6072 instruction with VexNDD, the destination register is encoded
6073 in VEX prefix. If there are 4 register operands, it must be
6074 a instruction with VEX prefix and 3 sources. */
6075 if (i
.mem_operands
== 0
6076 && ((i
.reg_operands
== 2
6077 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6078 || (i
.reg_operands
== 3
6079 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6080 || (i
.reg_operands
== 4 && vex_3_sources
)))
6088 /* When there are 3 operands, one of them may be immediate,
6089 which may be the first or the last operand. Otherwise,
6090 the first operand must be shift count register (cl) or it
6091 is an instruction with VexNDS. */
6092 gas_assert (i
.imm_operands
== 1
6093 || (i
.imm_operands
== 0
6094 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6095 || i
.types
[0].bitfield
.shiftcount
)));
6096 if (operand_type_check (i
.types
[0], imm
)
6097 || i
.types
[0].bitfield
.shiftcount
)
6103 /* When there are 4 operands, the first two must be 8bit
6104 immediate operands. The source operand will be the 3rd
6107 For instructions with VexNDS, if the first operand
6108 an imm8, the source operand is the 2nd one. If the last
6109 operand is imm8, the source operand is the first one. */
6110 gas_assert ((i
.imm_operands
== 2
6111 && i
.types
[0].bitfield
.imm8
6112 && i
.types
[1].bitfield
.imm8
)
6113 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6114 && i
.imm_operands
== 1
6115 && (i
.types
[0].bitfield
.imm8
6116 || i
.types
[i
.operands
- 1].bitfield
.imm8
6118 if (i
.imm_operands
== 2)
6122 if (i
.types
[0].bitfield
.imm8
)
6129 if (i
.tm
.opcode_modifier
.evex
)
6131 /* For EVEX instructions, when there are 5 operands, the
6132 first one must be immediate operand. If the second one
6133 is immediate operand, the source operand is the 3th
6134 one. If the last one is immediate operand, the source
6135 operand is the 2nd one. */
6136 gas_assert (i
.imm_operands
== 2
6137 && i
.tm
.opcode_modifier
.sae
6138 && operand_type_check (i
.types
[0], imm
));
6139 if (operand_type_check (i
.types
[1], imm
))
6141 else if (operand_type_check (i
.types
[4], imm
))
6155 /* RC/SAE operand could be between DEST and SRC. That happens
6156 when one operand is GPR and the other one is XMM/YMM/ZMM
6158 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6161 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6163 /* For instructions with VexNDS, the register-only source
6164 operand must be 32/64bit integer, XMM, YMM or ZMM
6165 register. It is encoded in VEX prefix. We need to
6166 clear RegMem bit before calling operand_type_equal. */
6168 i386_operand_type op
;
6171 /* Check register-only source operand when two source
6172 operands are swapped. */
6173 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6174 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6182 op
= i
.tm
.operand_types
[vvvv
];
6183 op
.bitfield
.regmem
= 0;
6184 if ((dest
+ 1) >= i
.operands
6185 || (!op
.bitfield
.reg32
6186 && op
.bitfield
.reg64
6187 && !operand_type_equal (&op
, ®xmm
)
6188 && !operand_type_equal (&op
, ®ymm
)
6189 && !operand_type_equal (&op
, ®zmm
)
6190 && !operand_type_equal (&op
, ®mask
)))
6192 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6198 /* One of the register operands will be encoded in the i.tm.reg
6199 field, the other in the combined i.tm.mode and i.tm.regmem
6200 fields. If no form of this instruction supports a memory
6201 destination operand, then we assume the source operand may
6202 sometimes be a memory operand and so we need to store the
6203 destination in the i.rm.reg field. */
6204 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6205 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6207 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6208 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6209 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6211 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6213 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6215 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6220 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6221 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6222 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6224 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6226 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6228 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6231 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6233 if (!i
.types
[0].bitfield
.control
6234 && !i
.types
[1].bitfield
.control
)
6236 i
.rex
&= ~(REX_R
| REX_B
);
6237 add_prefix (LOCK_PREFIX_OPCODE
);
6241 { /* If it's not 2 reg operands... */
6246 unsigned int fake_zero_displacement
= 0;
6249 for (op
= 0; op
< i
.operands
; op
++)
6250 if (operand_type_check (i
.types
[op
], anymem
))
6252 gas_assert (op
< i
.operands
);
6254 if (i
.tm
.opcode_modifier
.vecsib
)
6256 if (i
.index_reg
->reg_num
== RegEiz
6257 || i
.index_reg
->reg_num
== RegRiz
)
6260 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6263 i
.sib
.base
= NO_BASE_REGISTER
;
6264 i
.sib
.scale
= i
.log2_scale_factor
;
6265 /* No Vec_Disp8 if there is no base. */
6266 i
.types
[op
].bitfield
.vec_disp8
= 0;
6267 i
.types
[op
].bitfield
.disp8
= 0;
6268 i
.types
[op
].bitfield
.disp16
= 0;
6269 i
.types
[op
].bitfield
.disp64
= 0;
6270 if (flag_code
!= CODE_64BIT
)
6272 /* Must be 32 bit */
6273 i
.types
[op
].bitfield
.disp32
= 1;
6274 i
.types
[op
].bitfield
.disp32s
= 0;
6278 i
.types
[op
].bitfield
.disp32
= 0;
6279 i
.types
[op
].bitfield
.disp32s
= 1;
6282 i
.sib
.index
= i
.index_reg
->reg_num
;
6283 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6285 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6291 if (i
.base_reg
== 0)
6294 if (!i
.disp_operands
)
6296 fake_zero_displacement
= 1;
6297 /* Instructions with VSIB byte need 32bit displacement
6298 if there is no base register. */
6299 if (i
.tm
.opcode_modifier
.vecsib
)
6300 i
.types
[op
].bitfield
.disp32
= 1;
6302 if (i
.index_reg
== 0)
6304 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6305 /* Operand is just <disp> */
6306 if (flag_code
== CODE_64BIT
)
6308 /* 64bit mode overwrites the 32bit absolute
6309 addressing by RIP relative addressing and
6310 absolute addressing is encoded by one of the
6311 redundant SIB forms. */
6312 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6313 i
.sib
.base
= NO_BASE_REGISTER
;
6314 i
.sib
.index
= NO_INDEX_REGISTER
;
6315 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6316 ? disp32s
: disp32
);
6318 else if ((flag_code
== CODE_16BIT
)
6319 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6321 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6322 i
.types
[op
] = disp16
;
6326 i
.rm
.regmem
= NO_BASE_REGISTER
;
6327 i
.types
[op
] = disp32
;
6330 else if (!i
.tm
.opcode_modifier
.vecsib
)
6332 /* !i.base_reg && i.index_reg */
6333 if (i
.index_reg
->reg_num
== RegEiz
6334 || i
.index_reg
->reg_num
== RegRiz
)
6335 i
.sib
.index
= NO_INDEX_REGISTER
;
6337 i
.sib
.index
= i
.index_reg
->reg_num
;
6338 i
.sib
.base
= NO_BASE_REGISTER
;
6339 i
.sib
.scale
= i
.log2_scale_factor
;
6340 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6341 /* No Vec_Disp8 if there is no base. */
6342 i
.types
[op
].bitfield
.vec_disp8
= 0;
6343 i
.types
[op
].bitfield
.disp8
= 0;
6344 i
.types
[op
].bitfield
.disp16
= 0;
6345 i
.types
[op
].bitfield
.disp64
= 0;
6346 if (flag_code
!= CODE_64BIT
)
6348 /* Must be 32 bit */
6349 i
.types
[op
].bitfield
.disp32
= 1;
6350 i
.types
[op
].bitfield
.disp32s
= 0;
6354 i
.types
[op
].bitfield
.disp32
= 0;
6355 i
.types
[op
].bitfield
.disp32s
= 1;
6357 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6361 /* RIP addressing for 64bit mode. */
6362 else if (i
.base_reg
->reg_num
== RegRip
||
6363 i
.base_reg
->reg_num
== RegEip
)
6365 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6366 i
.rm
.regmem
= NO_BASE_REGISTER
;
6367 i
.types
[op
].bitfield
.disp8
= 0;
6368 i
.types
[op
].bitfield
.disp16
= 0;
6369 i
.types
[op
].bitfield
.disp32
= 0;
6370 i
.types
[op
].bitfield
.disp32s
= 1;
6371 i
.types
[op
].bitfield
.disp64
= 0;
6372 i
.types
[op
].bitfield
.vec_disp8
= 0;
6373 i
.flags
[op
] |= Operand_PCrel
;
6374 if (! i
.disp_operands
)
6375 fake_zero_displacement
= 1;
6377 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6379 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6380 switch (i
.base_reg
->reg_num
)
6383 if (i
.index_reg
== 0)
6385 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6386 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6390 if (i
.index_reg
== 0)
6393 if (operand_type_check (i
.types
[op
], disp
) == 0)
6395 /* fake (%bp) into 0(%bp) */
6396 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6397 i
.types
[op
].bitfield
.vec_disp8
= 1;
6399 i
.types
[op
].bitfield
.disp8
= 1;
6400 fake_zero_displacement
= 1;
6403 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6404 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6406 default: /* (%si) -> 4 or (%di) -> 5 */
6407 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6409 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6411 else /* i.base_reg and 32/64 bit mode */
6413 if (flag_code
== CODE_64BIT
6414 && operand_type_check (i
.types
[op
], disp
))
6416 i386_operand_type temp
;
6417 operand_type_set (&temp
, 0);
6418 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6419 temp
.bitfield
.vec_disp8
6420 = i
.types
[op
].bitfield
.vec_disp8
;
6422 if (i
.prefix
[ADDR_PREFIX
] == 0)
6423 i
.types
[op
].bitfield
.disp32s
= 1;
6425 i
.types
[op
].bitfield
.disp32
= 1;
6428 if (!i
.tm
.opcode_modifier
.vecsib
)
6429 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6430 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6432 i
.sib
.base
= i
.base_reg
->reg_num
;
6433 /* x86-64 ignores REX prefix bit here to avoid decoder
6435 if (!(i
.base_reg
->reg_flags
& RegRex
)
6436 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6437 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6439 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6441 fake_zero_displacement
= 1;
6442 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6443 i
.types
[op
].bitfield
.vec_disp8
= 1;
6445 i
.types
[op
].bitfield
.disp8
= 1;
6447 i
.sib
.scale
= i
.log2_scale_factor
;
6448 if (i
.index_reg
== 0)
6450 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6451 /* <disp>(%esp) becomes two byte modrm with no index
6452 register. We've already stored the code for esp
6453 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6454 Any base register besides %esp will not use the
6455 extra modrm byte. */
6456 i
.sib
.index
= NO_INDEX_REGISTER
;
6458 else if (!i
.tm
.opcode_modifier
.vecsib
)
6460 if (i
.index_reg
->reg_num
== RegEiz
6461 || i
.index_reg
->reg_num
== RegRiz
)
6462 i
.sib
.index
= NO_INDEX_REGISTER
;
6464 i
.sib
.index
= i
.index_reg
->reg_num
;
6465 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6466 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6471 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6472 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6476 if (!fake_zero_displacement
6480 fake_zero_displacement
= 1;
6481 if (i
.disp_encoding
== disp_encoding_8bit
)
6482 i
.types
[op
].bitfield
.disp8
= 1;
6484 i
.types
[op
].bitfield
.disp32
= 1;
6486 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6490 if (fake_zero_displacement
)
6492 /* Fakes a zero displacement assuming that i.types[op]
6493 holds the correct displacement size. */
6496 gas_assert (i
.op
[op
].disps
== 0);
6497 exp
= &disp_expressions
[i
.disp_operands
++];
6498 i
.op
[op
].disps
= exp
;
6499 exp
->X_op
= O_constant
;
6500 exp
->X_add_number
= 0;
6501 exp
->X_add_symbol
= (symbolS
*) 0;
6502 exp
->X_op_symbol
= (symbolS
*) 0;
6510 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6512 if (operand_type_check (i
.types
[0], imm
))
6513 i
.vex
.register_specifier
= NULL
;
6516 /* VEX.vvvv encodes one of the sources when the first
6517 operand is not an immediate. */
6518 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6519 i
.vex
.register_specifier
= i
.op
[0].regs
;
6521 i
.vex
.register_specifier
= i
.op
[1].regs
;
6524 /* Destination is a XMM register encoded in the ModRM.reg
6526 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6527 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6530 /* ModRM.rm and VEX.B encodes the other source. */
6531 if (!i
.mem_operands
)
6535 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6536 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6538 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6540 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6544 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6546 i
.vex
.register_specifier
= i
.op
[2].regs
;
6547 if (!i
.mem_operands
)
6550 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6551 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6555 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6556 (if any) based on i.tm.extension_opcode. Again, we must be
6557 careful to make sure that segment/control/debug/test/MMX
6558 registers are coded into the i.rm.reg field. */
6559 else if (i
.reg_operands
)
6562 unsigned int vex_reg
= ~0;
6564 for (op
= 0; op
< i
.operands
; op
++)
6565 if (i
.types
[op
].bitfield
.reg8
6566 || i
.types
[op
].bitfield
.reg16
6567 || i
.types
[op
].bitfield
.reg32
6568 || i
.types
[op
].bitfield
.reg64
6569 || i
.types
[op
].bitfield
.regmmx
6570 || i
.types
[op
].bitfield
.regxmm
6571 || i
.types
[op
].bitfield
.regymm
6572 || i
.types
[op
].bitfield
.regbnd
6573 || i
.types
[op
].bitfield
.regzmm
6574 || i
.types
[op
].bitfield
.regmask
6575 || i
.types
[op
].bitfield
.sreg2
6576 || i
.types
[op
].bitfield
.sreg3
6577 || i
.types
[op
].bitfield
.control
6578 || i
.types
[op
].bitfield
.debug
6579 || i
.types
[op
].bitfield
.test
)
6584 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6586 /* For instructions with VexNDS, the register-only
6587 source operand is encoded in VEX prefix. */
6588 gas_assert (mem
!= (unsigned int) ~0);
6593 gas_assert (op
< i
.operands
);
6597 /* Check register-only source operand when two source
6598 operands are swapped. */
6599 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6600 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6604 gas_assert (mem
== (vex_reg
+ 1)
6605 && op
< i
.operands
);
6610 gas_assert (vex_reg
< i
.operands
);
6614 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6616 /* For instructions with VexNDD, the register destination
6617 is encoded in VEX prefix. */
6618 if (i
.mem_operands
== 0)
6620 /* There is no memory operand. */
6621 gas_assert ((op
+ 2) == i
.operands
);
6626 /* There are only 2 operands. */
6627 gas_assert (op
< 2 && i
.operands
== 2);
6632 gas_assert (op
< i
.operands
);
6634 if (vex_reg
!= (unsigned int) ~0)
6636 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6638 if (type
->bitfield
.reg32
!= 1
6639 && type
->bitfield
.reg64
!= 1
6640 && !operand_type_equal (type
, ®xmm
)
6641 && !operand_type_equal (type
, ®ymm
)
6642 && !operand_type_equal (type
, ®zmm
)
6643 && !operand_type_equal (type
, ®mask
))
6646 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6649 /* Don't set OP operand twice. */
6652 /* If there is an extension opcode to put here, the
6653 register number must be put into the regmem field. */
6654 if (i
.tm
.extension_opcode
!= None
)
6656 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6657 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6659 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6664 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6665 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6667 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6672 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6673 must set it to 3 to indicate this is a register operand
6674 in the regmem field. */
6675 if (!i
.mem_operands
)
6679 /* Fill in i.rm.reg field with extension opcode (if any). */
6680 if (i
.tm
.extension_opcode
!= None
)
6681 i
.rm
.reg
= i
.tm
.extension_opcode
;
6687 output_branch (void)
6693 relax_substateT subtype
;
6697 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6698 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6701 if (i
.prefix
[DATA_PREFIX
] != 0)
6707 /* Pentium4 branch hints. */
6708 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6709 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6714 if (i
.prefix
[REX_PREFIX
] != 0)
6720 /* BND prefixed jump. */
6721 if (i
.prefix
[BND_PREFIX
] != 0)
6723 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6727 if (i
.prefixes
!= 0 && !intel_syntax
)
6728 as_warn (_("skipping prefixes on this instruction"));
6730 /* It's always a symbol; End frag & setup for relax.
6731 Make sure there is enough room in this frag for the largest
6732 instruction we may generate in md_convert_frag. This is 2
6733 bytes for the opcode and room for the prefix and largest
6735 frag_grow (prefix
+ 2 + 4);
6736 /* Prefix and 1 opcode byte go in fr_fix. */
6737 p
= frag_more (prefix
+ 1);
6738 if (i
.prefix
[DATA_PREFIX
] != 0)
6739 *p
++ = DATA_PREFIX_OPCODE
;
6740 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6741 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6742 *p
++ = i
.prefix
[SEG_PREFIX
];
6743 if (i
.prefix
[REX_PREFIX
] != 0)
6744 *p
++ = i
.prefix
[REX_PREFIX
];
6745 *p
= i
.tm
.base_opcode
;
6747 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6748 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6749 else if (cpu_arch_flags
.bitfield
.cpui386
)
6750 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6752 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6755 sym
= i
.op
[0].disps
->X_add_symbol
;
6756 off
= i
.op
[0].disps
->X_add_number
;
6758 if (i
.op
[0].disps
->X_op
!= O_constant
6759 && i
.op
[0].disps
->X_op
!= O_symbol
)
6761 /* Handle complex expressions. */
6762 sym
= make_expr_symbol (i
.op
[0].disps
);
6766 /* 1 possible extra opcode + 4 byte displacement go in var part.
6767 Pass reloc in fr_var. */
6768 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6778 if (i
.tm
.opcode_modifier
.jumpbyte
)
6780 /* This is a loop or jecxz type instruction. */
6782 if (i
.prefix
[ADDR_PREFIX
] != 0)
6784 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6787 /* Pentium4 branch hints. */
6788 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6789 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6791 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6800 if (flag_code
== CODE_16BIT
)
6803 if (i
.prefix
[DATA_PREFIX
] != 0)
6805 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6815 if (i
.prefix
[REX_PREFIX
] != 0)
6817 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6821 /* BND prefixed jump. */
6822 if (i
.prefix
[BND_PREFIX
] != 0)
6824 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6828 if (i
.prefixes
!= 0 && !intel_syntax
)
6829 as_warn (_("skipping prefixes on this instruction"));
6831 p
= frag_more (i
.tm
.opcode_length
+ size
);
6832 switch (i
.tm
.opcode_length
)
6835 *p
++ = i
.tm
.base_opcode
>> 8;
6837 *p
++ = i
.tm
.base_opcode
;
6843 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6844 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6846 /* All jumps handled here are signed, but don't use a signed limit
6847 check for 32 and 16 bit jumps as we want to allow wrap around at
6848 4G and 64k respectively. */
6850 fixP
->fx_signed
= 1;
6854 output_interseg_jump (void)
6862 if (flag_code
== CODE_16BIT
)
6866 if (i
.prefix
[DATA_PREFIX
] != 0)
6872 if (i
.prefix
[REX_PREFIX
] != 0)
6882 if (i
.prefixes
!= 0 && !intel_syntax
)
6883 as_warn (_("skipping prefixes on this instruction"));
6885 /* 1 opcode; 2 segment; offset */
6886 p
= frag_more (prefix
+ 1 + 2 + size
);
6888 if (i
.prefix
[DATA_PREFIX
] != 0)
6889 *p
++ = DATA_PREFIX_OPCODE
;
6891 if (i
.prefix
[REX_PREFIX
] != 0)
6892 *p
++ = i
.prefix
[REX_PREFIX
];
6894 *p
++ = i
.tm
.base_opcode
;
6895 if (i
.op
[1].imms
->X_op
== O_constant
)
6897 offsetT n
= i
.op
[1].imms
->X_add_number
;
6900 && !fits_in_unsigned_word (n
)
6901 && !fits_in_signed_word (n
))
6903 as_bad (_("16-bit jump out of range"));
6906 md_number_to_chars (p
, n
, size
);
6909 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6910 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6911 if (i
.op
[0].imms
->X_op
!= O_constant
)
6912 as_bad (_("can't handle non absolute segment in `%s'"),
6914 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6920 fragS
*insn_start_frag
;
6921 offsetT insn_start_off
;
6923 /* Tie dwarf2 debug info to the address at the start of the insn.
6924 We can't do this after the insn has been output as the current
6925 frag may have been closed off. eg. by frag_var. */
6926 dwarf2_emit_insn (0);
6928 insn_start_frag
= frag_now
;
6929 insn_start_off
= frag_now_fix ();
6932 if (i
.tm
.opcode_modifier
.jump
)
6934 else if (i
.tm
.opcode_modifier
.jumpbyte
6935 || i
.tm
.opcode_modifier
.jumpdword
)
6937 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6938 output_interseg_jump ();
6941 /* Output normal instructions here. */
6945 unsigned int prefix
;
6947 /* Some processors fail on LOCK prefix. This options makes
6948 assembler ignore LOCK prefix and serves as a workaround. */
6949 if (omit_lock_prefix
)
6951 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
6953 i
.prefix
[LOCK_PREFIX
] = 0;
6956 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6957 don't need the explicit prefix. */
6958 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6960 switch (i
.tm
.opcode_length
)
6963 if (i
.tm
.base_opcode
& 0xff000000)
6965 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6970 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6972 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6973 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6976 if (prefix
!= REPE_PREFIX_OPCODE
6977 || (i
.prefix
[REP_PREFIX
]
6978 != REPE_PREFIX_OPCODE
))
6979 add_prefix (prefix
);
6982 add_prefix (prefix
);
6991 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6992 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
6993 R_X86_64_GOTTPOFF relocation so that linker can safely
6994 perform IE->LE optimization. */
6995 if (x86_elf_abi
== X86_64_X32_ABI
6997 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
6998 && i
.prefix
[REX_PREFIX
] == 0)
6999 add_prefix (REX_OPCODE
);
7002 /* The prefix bytes. */
7003 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7005 FRAG_APPEND_1_CHAR (*q
);
7009 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7014 /* REX byte is encoded in VEX prefix. */
7018 FRAG_APPEND_1_CHAR (*q
);
7021 /* There should be no other prefixes for instructions
7026 /* For EVEX instructions i.vrex should become 0 after
7027 build_evex_prefix. For VEX instructions upper 16 registers
7028 aren't available, so VREX should be 0. */
7031 /* Now the VEX prefix. */
7032 p
= frag_more (i
.vex
.length
);
7033 for (j
= 0; j
< i
.vex
.length
; j
++)
7034 p
[j
] = i
.vex
.bytes
[j
];
7037 /* Now the opcode; be careful about word order here! */
7038 if (i
.tm
.opcode_length
== 1)
7040 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7044 switch (i
.tm
.opcode_length
)
7048 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7049 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7053 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7063 /* Put out high byte first: can't use md_number_to_chars! */
7064 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7065 *p
= i
.tm
.base_opcode
& 0xff;
7068 /* Now the modrm byte and sib byte (if present). */
7069 if (i
.tm
.opcode_modifier
.modrm
)
7071 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7074 /* If i.rm.regmem == ESP (4)
7075 && i.rm.mode != (Register mode)
7077 ==> need second modrm byte. */
7078 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7080 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7081 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7083 | i
.sib
.scale
<< 6));
7086 if (i
.disp_operands
)
7087 output_disp (insn_start_frag
, insn_start_off
);
7090 output_imm (insn_start_frag
, insn_start_off
);
7096 pi ("" /*line*/, &i
);
7098 #endif /* DEBUG386 */
7101 /* Return the size of the displacement operand N. */
7104 disp_size (unsigned int n
)
7108 /* Vec_Disp8 has to be 8bit. */
7109 if (i
.types
[n
].bitfield
.vec_disp8
)
7111 else if (i
.types
[n
].bitfield
.disp64
)
7113 else if (i
.types
[n
].bitfield
.disp8
)
7115 else if (i
.types
[n
].bitfield
.disp16
)
7120 /* Return the size of the immediate operand N. */
7123 imm_size (unsigned int n
)
7126 if (i
.types
[n
].bitfield
.imm64
)
7128 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7130 else if (i
.types
[n
].bitfield
.imm16
)
7136 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7141 for (n
= 0; n
< i
.operands
; n
++)
7143 if (i
.types
[n
].bitfield
.vec_disp8
7144 || operand_type_check (i
.types
[n
], disp
))
7146 if (i
.op
[n
].disps
->X_op
== O_constant
)
7148 int size
= disp_size (n
);
7149 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7151 if (i
.types
[n
].bitfield
.vec_disp8
)
7153 val
= offset_in_range (val
, size
);
7154 p
= frag_more (size
);
7155 md_number_to_chars (p
, val
, size
);
7159 enum bfd_reloc_code_real reloc_type
;
7160 int size
= disp_size (n
);
7161 int sign
= i
.types
[n
].bitfield
.disp32s
;
7162 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7164 /* We can't have 8 bit displacement here. */
7165 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7167 /* The PC relative address is computed relative
7168 to the instruction boundary, so in case immediate
7169 fields follows, we need to adjust the value. */
7170 if (pcrel
&& i
.imm_operands
)
7175 for (n1
= 0; n1
< i
.operands
; n1
++)
7176 if (operand_type_check (i
.types
[n1
], imm
))
7178 /* Only one immediate is allowed for PC
7179 relative address. */
7180 gas_assert (sz
== 0);
7182 i
.op
[n
].disps
->X_add_number
-= sz
;
7184 /* We should find the immediate. */
7185 gas_assert (sz
!= 0);
7188 p
= frag_more (size
);
7189 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7191 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7192 && (((reloc_type
== BFD_RELOC_32
7193 || reloc_type
== BFD_RELOC_X86_64_32S
7194 || (reloc_type
== BFD_RELOC_64
7196 && (i
.op
[n
].disps
->X_op
== O_symbol
7197 || (i
.op
[n
].disps
->X_op
== O_add
7198 && ((symbol_get_value_expression
7199 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7201 || reloc_type
== BFD_RELOC_32_PCREL
))
7205 if (insn_start_frag
== frag_now
)
7206 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7211 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7212 for (fr
= insn_start_frag
->fr_next
;
7213 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7215 add
+= p
- frag_now
->fr_literal
;
7220 reloc_type
= BFD_RELOC_386_GOTPC
;
7221 i
.op
[n
].imms
->X_add_number
+= add
;
7223 else if (reloc_type
== BFD_RELOC_64
)
7224 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7226 /* Don't do the adjustment for x86-64, as there
7227 the pcrel addressing is relative to the _next_
7228 insn, and that is taken care of in other code. */
7229 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7231 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7232 i
.op
[n
].disps
, pcrel
, reloc_type
);
7239 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7244 for (n
= 0; n
< i
.operands
; n
++)
7246 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7247 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7250 if (operand_type_check (i
.types
[n
], imm
))
7252 if (i
.op
[n
].imms
->X_op
== O_constant
)
7254 int size
= imm_size (n
);
7257 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7259 p
= frag_more (size
);
7260 md_number_to_chars (p
, val
, size
);
7264 /* Not absolute_section.
7265 Need a 32-bit fixup (don't support 8bit
7266 non-absolute imms). Try to support other
7268 enum bfd_reloc_code_real reloc_type
;
7269 int size
= imm_size (n
);
7272 if (i
.types
[n
].bitfield
.imm32s
7273 && (i
.suffix
== QWORD_MNEM_SUFFIX
7274 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7279 p
= frag_more (size
);
7280 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7282 /* This is tough to explain. We end up with this one if we
7283 * have operands that look like
7284 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7285 * obtain the absolute address of the GOT, and it is strongly
7286 * preferable from a performance point of view to avoid using
7287 * a runtime relocation for this. The actual sequence of
7288 * instructions often look something like:
7293 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7295 * The call and pop essentially return the absolute address
7296 * of the label .L66 and store it in %ebx. The linker itself
7297 * will ultimately change the first operand of the addl so
7298 * that %ebx points to the GOT, but to keep things simple, the
7299 * .o file must have this operand set so that it generates not
7300 * the absolute address of .L66, but the absolute address of
7301 * itself. This allows the linker itself simply treat a GOTPC
7302 * relocation as asking for a pcrel offset to the GOT to be
7303 * added in, and the addend of the relocation is stored in the
7304 * operand field for the instruction itself.
7306 * Our job here is to fix the operand so that it would add
7307 * the correct offset so that %ebx would point to itself. The
7308 * thing that is tricky is that .-.L66 will point to the
7309 * beginning of the instruction, so we need to further modify
7310 * the operand so that it will point to itself. There are
7311 * other cases where you have something like:
7313 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7315 * and here no correction would be required. Internally in
7316 * the assembler we treat operands of this form as not being
7317 * pcrel since the '.' is explicitly mentioned, and I wonder
7318 * whether it would simplify matters to do it this way. Who
7319 * knows. In earlier versions of the PIC patches, the
7320 * pcrel_adjust field was used to store the correction, but
7321 * since the expression is not pcrel, I felt it would be
7322 * confusing to do it this way. */
7324 if ((reloc_type
== BFD_RELOC_32
7325 || reloc_type
== BFD_RELOC_X86_64_32S
7326 || reloc_type
== BFD_RELOC_64
)
7328 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7329 && (i
.op
[n
].imms
->X_op
== O_symbol
7330 || (i
.op
[n
].imms
->X_op
== O_add
7331 && ((symbol_get_value_expression
7332 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7337 if (insn_start_frag
== frag_now
)
7338 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7343 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7344 for (fr
= insn_start_frag
->fr_next
;
7345 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7347 add
+= p
- frag_now
->fr_literal
;
7351 reloc_type
= BFD_RELOC_386_GOTPC
;
7353 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7355 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7356 i
.op
[n
].imms
->X_add_number
+= add
;
7358 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7359 i
.op
[n
].imms
, 0, reloc_type
);
7365 /* x86_cons_fix_new is called via the expression parsing code when a
7366 reloc is needed. We use this hook to get the correct .got reloc. */
7367 static int cons_sign
= -1;
7370 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7371 expressionS
*exp
, bfd_reloc_code_real_type r
)
7373 r
= reloc (len
, 0, cons_sign
, r
);
7376 if (exp
->X_op
== O_secrel
)
7378 exp
->X_op
= O_symbol
;
7379 r
= BFD_RELOC_32_SECREL
;
7383 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7386 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7387 purpose of the `.dc.a' internal pseudo-op. */
7390 x86_address_bytes (void)
7392 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7394 return stdoutput
->arch_info
->bits_per_address
/ 8;
7397 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7399 # define lex_got(reloc, adjust, types) NULL
7401 /* Parse operands of the form
7402 <symbol>@GOTOFF+<nnn>
7403 and similar .plt or .got references.
7405 If we find one, set up the correct relocation in RELOC and copy the
7406 input string, minus the `@GOTOFF' into a malloc'd buffer for
7407 parsing by the calling routine. Return this buffer, and if ADJUST
7408 is non-null set it to the length of the string we removed from the
7409 input line. Otherwise return NULL. */
7411 lex_got (enum bfd_reloc_code_real
*rel
,
7413 i386_operand_type
*types
)
7415 /* Some of the relocations depend on the size of what field is to
7416 be relocated. But in our callers i386_immediate and i386_displacement
7417 we don't yet know the operand size (this will be set by insn
7418 matching). Hence we record the word32 relocation here,
7419 and adjust the reloc according to the real size in reloc(). */
7420 static const struct {
7423 const enum bfd_reloc_code_real rel
[2];
7424 const i386_operand_type types64
;
7426 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7427 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7429 OPERAND_TYPE_IMM32_64
},
7431 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7432 BFD_RELOC_X86_64_PLTOFF64
},
7433 OPERAND_TYPE_IMM64
},
7434 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7435 BFD_RELOC_X86_64_PLT32
},
7436 OPERAND_TYPE_IMM32_32S_DISP32
},
7437 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7438 BFD_RELOC_X86_64_GOTPLT64
},
7439 OPERAND_TYPE_IMM64_DISP64
},
7440 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7441 BFD_RELOC_X86_64_GOTOFF64
},
7442 OPERAND_TYPE_IMM64_DISP64
},
7443 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7444 BFD_RELOC_X86_64_GOTPCREL
},
7445 OPERAND_TYPE_IMM32_32S_DISP32
},
7446 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7447 BFD_RELOC_X86_64_TLSGD
},
7448 OPERAND_TYPE_IMM32_32S_DISP32
},
7449 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7450 _dummy_first_bfd_reloc_code_real
},
7451 OPERAND_TYPE_NONE
},
7452 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7453 BFD_RELOC_X86_64_TLSLD
},
7454 OPERAND_TYPE_IMM32_32S_DISP32
},
7455 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7456 BFD_RELOC_X86_64_GOTTPOFF
},
7457 OPERAND_TYPE_IMM32_32S_DISP32
},
7458 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7459 BFD_RELOC_X86_64_TPOFF32
},
7460 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7461 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7462 _dummy_first_bfd_reloc_code_real
},
7463 OPERAND_TYPE_NONE
},
7464 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7465 BFD_RELOC_X86_64_DTPOFF32
},
7466 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7467 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7468 _dummy_first_bfd_reloc_code_real
},
7469 OPERAND_TYPE_NONE
},
7470 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7471 _dummy_first_bfd_reloc_code_real
},
7472 OPERAND_TYPE_NONE
},
7473 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7474 BFD_RELOC_X86_64_GOT32
},
7475 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7476 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7477 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7478 OPERAND_TYPE_IMM32_32S_DISP32
},
7479 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7480 BFD_RELOC_X86_64_TLSDESC_CALL
},
7481 OPERAND_TYPE_IMM32_32S_DISP32
},
7486 #if defined (OBJ_MAYBE_ELF)
7491 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7492 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7495 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7497 int len
= gotrel
[j
].len
;
7498 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7500 if (gotrel
[j
].rel
[object_64bit
] != 0)
7503 char *tmpbuf
, *past_reloc
;
7505 *rel
= gotrel
[j
].rel
[object_64bit
];
7509 if (flag_code
!= CODE_64BIT
)
7511 types
->bitfield
.imm32
= 1;
7512 types
->bitfield
.disp32
= 1;
7515 *types
= gotrel
[j
].types64
;
7518 if (j
!= 0 && GOT_symbol
== NULL
)
7519 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7521 /* The length of the first part of our input line. */
7522 first
= cp
- input_line_pointer
;
7524 /* The second part goes from after the reloc token until
7525 (and including) an end_of_line char or comma. */
7526 past_reloc
= cp
+ 1 + len
;
7528 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7530 second
= cp
+ 1 - past_reloc
;
7532 /* Allocate and copy string. The trailing NUL shouldn't
7533 be necessary, but be safe. */
7534 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7535 memcpy (tmpbuf
, input_line_pointer
, first
);
7536 if (second
!= 0 && *past_reloc
!= ' ')
7537 /* Replace the relocation token with ' ', so that
7538 errors like foo@GOTOFF1 will be detected. */
7539 tmpbuf
[first
++] = ' ';
7541 /* Increment length by 1 if the relocation token is
7546 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7547 tmpbuf
[first
+ second
] = '\0';
7551 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7552 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7557 /* Might be a symbol version string. Don't as_bad here. */
7566 /* Parse operands of the form
7567 <symbol>@SECREL32+<nnn>
7569 If we find one, set up the correct relocation in RELOC and copy the
7570 input string, minus the `@SECREL32' into a malloc'd buffer for
7571 parsing by the calling routine. Return this buffer, and if ADJUST
7572 is non-null set it to the length of the string we removed from the
7573 input line. Otherwise return NULL.
7575 This function is copied from the ELF version above adjusted for PE targets. */
7578 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7579 int *adjust ATTRIBUTE_UNUSED
,
7580 i386_operand_type
*types
)
7586 const enum bfd_reloc_code_real rel
[2];
7587 const i386_operand_type types64
;
7591 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7592 BFD_RELOC_32_SECREL
},
7593 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7599 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7600 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7603 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7605 int len
= gotrel
[j
].len
;
7607 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7609 if (gotrel
[j
].rel
[object_64bit
] != 0)
7612 char *tmpbuf
, *past_reloc
;
7614 *rel
= gotrel
[j
].rel
[object_64bit
];
7620 if (flag_code
!= CODE_64BIT
)
7622 types
->bitfield
.imm32
= 1;
7623 types
->bitfield
.disp32
= 1;
7626 *types
= gotrel
[j
].types64
;
7629 /* The length of the first part of our input line. */
7630 first
= cp
- input_line_pointer
;
7632 /* The second part goes from after the reloc token until
7633 (and including) an end_of_line char or comma. */
7634 past_reloc
= cp
+ 1 + len
;
7636 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7638 second
= cp
+ 1 - past_reloc
;
7640 /* Allocate and copy string. The trailing NUL shouldn't
7641 be necessary, but be safe. */
7642 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7643 memcpy (tmpbuf
, input_line_pointer
, first
);
7644 if (second
!= 0 && *past_reloc
!= ' ')
7645 /* Replace the relocation token with ' ', so that
7646 errors like foo@SECLREL321 will be detected. */
7647 tmpbuf
[first
++] = ' ';
7648 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7649 tmpbuf
[first
+ second
] = '\0';
7653 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7654 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7659 /* Might be a symbol version string. Don't as_bad here. */
7665 bfd_reloc_code_real_type
7666 x86_cons (expressionS
*exp
, int size
)
7668 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7670 intel_syntax
= -intel_syntax
;
7673 if (size
== 4 || (object_64bit
&& size
== 8))
7675 /* Handle @GOTOFF and the like in an expression. */
7677 char *gotfree_input_line
;
7680 save
= input_line_pointer
;
7681 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7682 if (gotfree_input_line
)
7683 input_line_pointer
= gotfree_input_line
;
7687 if (gotfree_input_line
)
7689 /* expression () has merrily parsed up to the end of line,
7690 or a comma - in the wrong buffer. Transfer how far
7691 input_line_pointer has moved to the right buffer. */
7692 input_line_pointer
= (save
7693 + (input_line_pointer
- gotfree_input_line
)
7695 free (gotfree_input_line
);
7696 if (exp
->X_op
== O_constant
7697 || exp
->X_op
== O_absent
7698 || exp
->X_op
== O_illegal
7699 || exp
->X_op
== O_register
7700 || exp
->X_op
== O_big
)
7702 char c
= *input_line_pointer
;
7703 *input_line_pointer
= 0;
7704 as_bad (_("missing or invalid expression `%s'"), save
);
7705 *input_line_pointer
= c
;
7712 intel_syntax
= -intel_syntax
;
7715 i386_intel_simplify (exp
);
7721 signed_cons (int size
)
7723 if (flag_code
== CODE_64BIT
)
7731 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7738 if (exp
.X_op
== O_symbol
)
7739 exp
.X_op
= O_secrel
;
7741 emit_expr (&exp
, 4);
7743 while (*input_line_pointer
++ == ',');
7745 input_line_pointer
--;
7746 demand_empty_rest_of_line ();
7750 /* Handle Vector operations. */
7753 check_VecOperations (char *op_string
, char *op_end
)
7755 const reg_entry
*mask
;
7760 && (op_end
== NULL
|| op_string
< op_end
))
7763 if (*op_string
== '{')
7767 /* Check broadcasts. */
7768 if (strncmp (op_string
, "1to", 3) == 0)
7773 goto duplicated_vec_op
;
7776 if (*op_string
== '8')
7777 bcst_type
= BROADCAST_1TO8
;
7778 else if (*op_string
== '4')
7779 bcst_type
= BROADCAST_1TO4
;
7780 else if (*op_string
== '2')
7781 bcst_type
= BROADCAST_1TO2
;
7782 else if (*op_string
== '1'
7783 && *(op_string
+1) == '6')
7785 bcst_type
= BROADCAST_1TO16
;
7790 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7795 broadcast_op
.type
= bcst_type
;
7796 broadcast_op
.operand
= this_operand
;
7797 i
.broadcast
= &broadcast_op
;
7799 /* Check masking operation. */
7800 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7802 /* k0 can't be used for write mask. */
7803 if (mask
->reg_num
== 0)
7805 as_bad (_("`%s' can't be used for write mask"),
7812 mask_op
.mask
= mask
;
7813 mask_op
.zeroing
= 0;
7814 mask_op
.operand
= this_operand
;
7820 goto duplicated_vec_op
;
7822 i
.mask
->mask
= mask
;
7824 /* Only "{z}" is allowed here. No need to check
7825 zeroing mask explicitly. */
7826 if (i
.mask
->operand
!= this_operand
)
7828 as_bad (_("invalid write mask `%s'"), saved
);
7835 /* Check zeroing-flag for masking operation. */
7836 else if (*op_string
== 'z')
7840 mask_op
.mask
= NULL
;
7841 mask_op
.zeroing
= 1;
7842 mask_op
.operand
= this_operand
;
7847 if (i
.mask
->zeroing
)
7850 as_bad (_("duplicated `%s'"), saved
);
7854 i
.mask
->zeroing
= 1;
7856 /* Only "{%k}" is allowed here. No need to check mask
7857 register explicitly. */
7858 if (i
.mask
->operand
!= this_operand
)
7860 as_bad (_("invalid zeroing-masking `%s'"),
7869 goto unknown_vec_op
;
7871 if (*op_string
!= '}')
7873 as_bad (_("missing `}' in `%s'"), saved
);
7880 /* We don't know this one. */
7881 as_bad (_("unknown vector operation: `%s'"), saved
);
7889 i386_immediate (char *imm_start
)
7891 char *save_input_line_pointer
;
7892 char *gotfree_input_line
;
7895 i386_operand_type types
;
7897 operand_type_set (&types
, ~0);
7899 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7901 as_bad (_("at most %d immediate operands are allowed"),
7902 MAX_IMMEDIATE_OPERANDS
);
7906 exp
= &im_expressions
[i
.imm_operands
++];
7907 i
.op
[this_operand
].imms
= exp
;
7909 if (is_space_char (*imm_start
))
7912 save_input_line_pointer
= input_line_pointer
;
7913 input_line_pointer
= imm_start
;
7915 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7916 if (gotfree_input_line
)
7917 input_line_pointer
= gotfree_input_line
;
7919 exp_seg
= expression (exp
);
7923 /* Handle vector operations. */
7924 if (*input_line_pointer
== '{')
7926 input_line_pointer
= check_VecOperations (input_line_pointer
,
7928 if (input_line_pointer
== NULL
)
7932 if (*input_line_pointer
)
7933 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7935 input_line_pointer
= save_input_line_pointer
;
7936 if (gotfree_input_line
)
7938 free (gotfree_input_line
);
7940 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7941 exp
->X_op
= O_illegal
;
7944 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7948 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7949 i386_operand_type types
, const char *imm_start
)
7951 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7954 as_bad (_("missing or invalid immediate expression `%s'"),
7958 else if (exp
->X_op
== O_constant
)
7960 /* Size it properly later. */
7961 i
.types
[this_operand
].bitfield
.imm64
= 1;
7962 /* If not 64bit, sign extend val. */
7963 if (flag_code
!= CODE_64BIT
7964 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7966 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7968 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7969 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7970 && exp_seg
!= absolute_section
7971 && exp_seg
!= text_section
7972 && exp_seg
!= data_section
7973 && exp_seg
!= bss_section
7974 && exp_seg
!= undefined_section
7975 && !bfd_is_com_section (exp_seg
))
7977 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7981 else if (!intel_syntax
&& exp_seg
== reg_section
)
7984 as_bad (_("illegal immediate register operand %s"), imm_start
);
7989 /* This is an address. The size of the address will be
7990 determined later, depending on destination register,
7991 suffix, or the default for the section. */
7992 i
.types
[this_operand
].bitfield
.imm8
= 1;
7993 i
.types
[this_operand
].bitfield
.imm16
= 1;
7994 i
.types
[this_operand
].bitfield
.imm32
= 1;
7995 i
.types
[this_operand
].bitfield
.imm32s
= 1;
7996 i
.types
[this_operand
].bitfield
.imm64
= 1;
7997 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8005 i386_scale (char *scale
)
8008 char *save
= input_line_pointer
;
8010 input_line_pointer
= scale
;
8011 val
= get_absolute_expression ();
8016 i
.log2_scale_factor
= 0;
8019 i
.log2_scale_factor
= 1;
8022 i
.log2_scale_factor
= 2;
8025 i
.log2_scale_factor
= 3;
8029 char sep
= *input_line_pointer
;
8031 *input_line_pointer
= '\0';
8032 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8034 *input_line_pointer
= sep
;
8035 input_line_pointer
= save
;
8039 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8041 as_warn (_("scale factor of %d without an index register"),
8042 1 << i
.log2_scale_factor
);
8043 i
.log2_scale_factor
= 0;
8045 scale
= input_line_pointer
;
8046 input_line_pointer
= save
;
8051 i386_displacement (char *disp_start
, char *disp_end
)
8055 char *save_input_line_pointer
;
8056 char *gotfree_input_line
;
8058 i386_operand_type bigdisp
, types
= anydisp
;
8061 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8063 as_bad (_("at most %d displacement operands are allowed"),
8064 MAX_MEMORY_OPERANDS
);
8068 operand_type_set (&bigdisp
, 0);
8069 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8070 || (!current_templates
->start
->opcode_modifier
.jump
8071 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8073 bigdisp
.bitfield
.disp32
= 1;
8074 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8075 if (flag_code
== CODE_64BIT
)
8079 bigdisp
.bitfield
.disp32s
= 1;
8080 bigdisp
.bitfield
.disp64
= 1;
8083 else if ((flag_code
== CODE_16BIT
) ^ override
)
8085 bigdisp
.bitfield
.disp32
= 0;
8086 bigdisp
.bitfield
.disp16
= 1;
8091 /* For PC-relative branches, the width of the displacement
8092 is dependent upon data size, not address size. */
8093 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8094 if (flag_code
== CODE_64BIT
)
8096 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8097 bigdisp
.bitfield
.disp16
= 1;
8100 bigdisp
.bitfield
.disp32
= 1;
8101 bigdisp
.bitfield
.disp32s
= 1;
8107 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8109 : LONG_MNEM_SUFFIX
));
8110 bigdisp
.bitfield
.disp32
= 1;
8111 if ((flag_code
== CODE_16BIT
) ^ override
)
8113 bigdisp
.bitfield
.disp32
= 0;
8114 bigdisp
.bitfield
.disp16
= 1;
8118 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8121 exp
= &disp_expressions
[i
.disp_operands
];
8122 i
.op
[this_operand
].disps
= exp
;
8124 save_input_line_pointer
= input_line_pointer
;
8125 input_line_pointer
= disp_start
;
8126 END_STRING_AND_SAVE (disp_end
);
8128 #ifndef GCC_ASM_O_HACK
8129 #define GCC_ASM_O_HACK 0
8132 END_STRING_AND_SAVE (disp_end
+ 1);
8133 if (i
.types
[this_operand
].bitfield
.baseIndex
8134 && displacement_string_end
[-1] == '+')
8136 /* This hack is to avoid a warning when using the "o"
8137 constraint within gcc asm statements.
8140 #define _set_tssldt_desc(n,addr,limit,type) \
8141 __asm__ __volatile__ ( \
8143 "movw %w1,2+%0\n\t" \
8145 "movb %b1,4+%0\n\t" \
8146 "movb %4,5+%0\n\t" \
8147 "movb $0,6+%0\n\t" \
8148 "movb %h1,7+%0\n\t" \
8150 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8152 This works great except that the output assembler ends
8153 up looking a bit weird if it turns out that there is
8154 no offset. You end up producing code that looks like:
8167 So here we provide the missing zero. */
8169 *displacement_string_end
= '0';
8172 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8173 if (gotfree_input_line
)
8174 input_line_pointer
= gotfree_input_line
;
8176 exp_seg
= expression (exp
);
8179 if (*input_line_pointer
)
8180 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8182 RESTORE_END_STRING (disp_end
+ 1);
8184 input_line_pointer
= save_input_line_pointer
;
8185 if (gotfree_input_line
)
8187 free (gotfree_input_line
);
8189 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8190 exp
->X_op
= O_illegal
;
8193 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8195 RESTORE_END_STRING (disp_end
);
8201 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8202 i386_operand_type types
, const char *disp_start
)
8204 i386_operand_type bigdisp
;
8207 /* We do this to make sure that the section symbol is in
8208 the symbol table. We will ultimately change the relocation
8209 to be relative to the beginning of the section. */
8210 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8211 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8212 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8214 if (exp
->X_op
!= O_symbol
)
8217 if (S_IS_LOCAL (exp
->X_add_symbol
)
8218 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8219 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8220 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8221 exp
->X_op
= O_subtract
;
8222 exp
->X_op_symbol
= GOT_symbol
;
8223 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8224 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8225 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8226 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8228 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8231 else if (exp
->X_op
== O_absent
8232 || exp
->X_op
== O_illegal
8233 || exp
->X_op
== O_big
)
8236 as_bad (_("missing or invalid displacement expression `%s'"),
8241 else if (flag_code
== CODE_64BIT
8242 && !i
.prefix
[ADDR_PREFIX
]
8243 && exp
->X_op
== O_constant
)
8245 /* Since displacement is signed extended to 64bit, don't allow
8246 disp32 and turn off disp32s if they are out of range. */
8247 i
.types
[this_operand
].bitfield
.disp32
= 0;
8248 if (!fits_in_signed_long (exp
->X_add_number
))
8250 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8251 if (i
.types
[this_operand
].bitfield
.baseindex
)
8253 as_bad (_("0x%lx out range of signed 32bit displacement"),
8254 (long) exp
->X_add_number
);
8260 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8261 else if (exp
->X_op
!= O_constant
8262 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8263 && exp_seg
!= absolute_section
8264 && exp_seg
!= text_section
8265 && exp_seg
!= data_section
8266 && exp_seg
!= bss_section
8267 && exp_seg
!= undefined_section
8268 && !bfd_is_com_section (exp_seg
))
8270 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8275 /* Check if this is a displacement only operand. */
8276 bigdisp
= i
.types
[this_operand
];
8277 bigdisp
.bitfield
.disp8
= 0;
8278 bigdisp
.bitfield
.disp16
= 0;
8279 bigdisp
.bitfield
.disp32
= 0;
8280 bigdisp
.bitfield
.disp32s
= 0;
8281 bigdisp
.bitfield
.disp64
= 0;
8282 if (operand_type_all_zero (&bigdisp
))
8283 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8289 /* Make sure the memory operand we've been dealt is valid.
8290 Return 1 on success, 0 on a failure. */
8293 i386_index_check (const char *operand_string
)
8295 const char *kind
= "base/index";
8296 enum flag_code addr_mode
;
8298 if (i
.prefix
[ADDR_PREFIX
])
8299 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8302 addr_mode
= flag_code
;
8304 #if INFER_ADDR_PREFIX
8305 if (i
.mem_operands
== 0)
8307 /* Infer address prefix from the first memory operand. */
8308 const reg_entry
*addr_reg
= i
.base_reg
;
8310 if (addr_reg
== NULL
)
8311 addr_reg
= i
.index_reg
;
8315 if (addr_reg
->reg_num
== RegEip
8316 || addr_reg
->reg_num
== RegEiz
8317 || addr_reg
->reg_type
.bitfield
.reg32
)
8318 addr_mode
= CODE_32BIT
;
8319 else if (flag_code
!= CODE_64BIT
8320 && addr_reg
->reg_type
.bitfield
.reg16
)
8321 addr_mode
= CODE_16BIT
;
8323 if (addr_mode
!= flag_code
)
8325 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8327 /* Change the size of any displacement too. At most one
8328 of Disp16 or Disp32 is set.
8329 FIXME. There doesn't seem to be any real need for
8330 separate Disp16 and Disp32 flags. The same goes for
8331 Imm16 and Imm32. Removing them would probably clean
8332 up the code quite a lot. */
8333 if (flag_code
!= CODE_64BIT
8334 && (i
.types
[this_operand
].bitfield
.disp16
8335 || i
.types
[this_operand
].bitfield
.disp32
))
8336 i
.types
[this_operand
]
8337 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8344 if (current_templates
->start
->opcode_modifier
.isstring
8345 && !current_templates
->start
->opcode_modifier
.immext
8346 && (current_templates
->end
[-1].opcode_modifier
.isstring
8349 /* Memory operands of string insns are special in that they only allow
8350 a single register (rDI, rSI, or rBX) as their memory address. */
8351 const reg_entry
*expected_reg
;
8352 static const char *di_si
[][2] =
8358 static const char *bx
[] = { "ebx", "bx", "rbx" };
8360 kind
= "string address";
8362 if (current_templates
->start
->opcode_modifier
.w
)
8364 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8366 if (!type
.bitfield
.baseindex
8367 || ((!i
.mem_operands
!= !intel_syntax
)
8368 && current_templates
->end
[-1].operand_types
[1]
8369 .bitfield
.baseindex
))
8370 type
= current_templates
->end
[-1].operand_types
[1];
8371 expected_reg
= hash_find (reg_hash
,
8372 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8376 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8378 if (i
.base_reg
!= expected_reg
8380 || operand_type_check (i
.types
[this_operand
], disp
))
8382 /* The second memory operand must have the same size as
8386 && !((addr_mode
== CODE_64BIT
8387 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8388 || (addr_mode
== CODE_32BIT
8389 ? i
.base_reg
->reg_type
.bitfield
.reg32
8390 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8393 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8395 intel_syntax
? '[' : '(',
8397 expected_reg
->reg_name
,
8398 intel_syntax
? ']' : ')');
8405 as_bad (_("`%s' is not a valid %s expression"),
8406 operand_string
, kind
);
8411 if (addr_mode
!= CODE_16BIT
)
8413 /* 32-bit/64-bit checks. */
8415 && (addr_mode
== CODE_64BIT
8416 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8417 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8419 || (i
.base_reg
->reg_num
8420 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8422 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8423 && !i
.index_reg
->reg_type
.bitfield
.regymm
8424 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8425 && ((addr_mode
== CODE_64BIT
8426 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8427 || i
.index_reg
->reg_num
== RegRiz
)
8428 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8429 || i
.index_reg
->reg_num
== RegEiz
))
8430 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8435 /* 16-bit checks. */
8437 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8438 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8440 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8441 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8443 && i
.base_reg
->reg_num
< 6
8444 && i
.index_reg
->reg_num
>= 6
8445 && i
.log2_scale_factor
== 0))))
8452 /* Handle vector immediates. */
8455 RC_SAE_immediate (const char *imm_start
)
8457 unsigned int match_found
, j
;
8458 const char *pstr
= imm_start
;
8466 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8468 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8472 rc_op
.type
= RC_NamesTable
[j
].type
;
8473 rc_op
.operand
= this_operand
;
8474 i
.rounding
= &rc_op
;
8478 as_bad (_("duplicated `%s'"), imm_start
);
8481 pstr
+= RC_NamesTable
[j
].len
;
8491 as_bad (_("Missing '}': '%s'"), imm_start
);
8494 /* RC/SAE immediate string should contain nothing more. */;
8497 as_bad (_("Junk after '}': '%s'"), imm_start
);
8501 exp
= &im_expressions
[i
.imm_operands
++];
8502 i
.op
[this_operand
].imms
= exp
;
8504 exp
->X_op
= O_constant
;
8505 exp
->X_add_number
= 0;
8506 exp
->X_add_symbol
= (symbolS
*) 0;
8507 exp
->X_op_symbol
= (symbolS
*) 0;
8509 i
.types
[this_operand
].bitfield
.imm8
= 1;
8513 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8517 i386_att_operand (char *operand_string
)
8521 char *op_string
= operand_string
;
8523 if (is_space_char (*op_string
))
8526 /* We check for an absolute prefix (differentiating,
8527 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8528 if (*op_string
== ABSOLUTE_PREFIX
)
8531 if (is_space_char (*op_string
))
8533 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8536 /* Check if operand is a register. */
8537 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8539 i386_operand_type temp
;
8541 /* Check for a segment override by searching for ':' after a
8542 segment register. */
8544 if (is_space_char (*op_string
))
8546 if (*op_string
== ':'
8547 && (r
->reg_type
.bitfield
.sreg2
8548 || r
->reg_type
.bitfield
.sreg3
))
8553 i
.seg
[i
.mem_operands
] = &es
;
8556 i
.seg
[i
.mem_operands
] = &cs
;
8559 i
.seg
[i
.mem_operands
] = &ss
;
8562 i
.seg
[i
.mem_operands
] = &ds
;
8565 i
.seg
[i
.mem_operands
] = &fs
;
8568 i
.seg
[i
.mem_operands
] = &gs
;
8572 /* Skip the ':' and whitespace. */
8574 if (is_space_char (*op_string
))
8577 if (!is_digit_char (*op_string
)
8578 && !is_identifier_char (*op_string
)
8579 && *op_string
!= '('
8580 && *op_string
!= ABSOLUTE_PREFIX
)
8582 as_bad (_("bad memory operand `%s'"), op_string
);
8585 /* Handle case of %es:*foo. */
8586 if (*op_string
== ABSOLUTE_PREFIX
)
8589 if (is_space_char (*op_string
))
8591 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8593 goto do_memory_reference
;
8596 /* Handle vector operations. */
8597 if (*op_string
== '{')
8599 op_string
= check_VecOperations (op_string
, NULL
);
8600 if (op_string
== NULL
)
8606 as_bad (_("junk `%s' after register"), op_string
);
8610 temp
.bitfield
.baseindex
= 0;
8611 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8613 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8614 i
.op
[this_operand
].regs
= r
;
8617 else if (*op_string
== REGISTER_PREFIX
)
8619 as_bad (_("bad register name `%s'"), op_string
);
8622 else if (*op_string
== IMMEDIATE_PREFIX
)
8625 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8627 as_bad (_("immediate operand illegal with absolute jump"));
8630 if (!i386_immediate (op_string
))
8633 else if (RC_SAE_immediate (operand_string
))
8635 /* If it is a RC or SAE immediate, do nothing. */
8638 else if (is_digit_char (*op_string
)
8639 || is_identifier_char (*op_string
)
8640 || *op_string
== '(')
8642 /* This is a memory reference of some sort. */
8645 /* Start and end of displacement string expression (if found). */
8646 char *displacement_string_start
;
8647 char *displacement_string_end
;
8650 do_memory_reference
:
8651 if ((i
.mem_operands
== 1
8652 && !current_templates
->start
->opcode_modifier
.isstring
)
8653 || i
.mem_operands
== 2)
8655 as_bad (_("too many memory references for `%s'"),
8656 current_templates
->start
->name
);
8660 /* Check for base index form. We detect the base index form by
8661 looking for an ')' at the end of the operand, searching
8662 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8664 base_string
= op_string
+ strlen (op_string
);
8666 /* Handle vector operations. */
8667 vop_start
= strchr (op_string
, '{');
8668 if (vop_start
&& vop_start
< base_string
)
8670 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8672 base_string
= vop_start
;
8676 if (is_space_char (*base_string
))
8679 /* If we only have a displacement, set-up for it to be parsed later. */
8680 displacement_string_start
= op_string
;
8681 displacement_string_end
= base_string
+ 1;
8683 if (*base_string
== ')')
8686 unsigned int parens_balanced
= 1;
8687 /* We've already checked that the number of left & right ()'s are
8688 equal, so this loop will not be infinite. */
8692 if (*base_string
== ')')
8694 if (*base_string
== '(')
8697 while (parens_balanced
);
8699 temp_string
= base_string
;
8701 /* Skip past '(' and whitespace. */
8703 if (is_space_char (*base_string
))
8706 if (*base_string
== ','
8707 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8710 displacement_string_end
= temp_string
;
8712 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8716 base_string
= end_op
;
8717 if (is_space_char (*base_string
))
8721 /* There may be an index reg or scale factor here. */
8722 if (*base_string
== ',')
8725 if (is_space_char (*base_string
))
8728 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8731 base_string
= end_op
;
8732 if (is_space_char (*base_string
))
8734 if (*base_string
== ',')
8737 if (is_space_char (*base_string
))
8740 else if (*base_string
!= ')')
8742 as_bad (_("expecting `,' or `)' "
8743 "after index register in `%s'"),
8748 else if (*base_string
== REGISTER_PREFIX
)
8750 end_op
= strchr (base_string
, ',');
8753 as_bad (_("bad register name `%s'"), base_string
);
8757 /* Check for scale factor. */
8758 if (*base_string
!= ')')
8760 char *end_scale
= i386_scale (base_string
);
8765 base_string
= end_scale
;
8766 if (is_space_char (*base_string
))
8768 if (*base_string
!= ')')
8770 as_bad (_("expecting `)' "
8771 "after scale factor in `%s'"),
8776 else if (!i
.index_reg
)
8778 as_bad (_("expecting index register or scale factor "
8779 "after `,'; got '%c'"),
8784 else if (*base_string
!= ')')
8786 as_bad (_("expecting `,' or `)' "
8787 "after base register in `%s'"),
8792 else if (*base_string
== REGISTER_PREFIX
)
8794 end_op
= strchr (base_string
, ',');
8797 as_bad (_("bad register name `%s'"), base_string
);
8802 /* If there's an expression beginning the operand, parse it,
8803 assuming displacement_string_start and
8804 displacement_string_end are meaningful. */
8805 if (displacement_string_start
!= displacement_string_end
)
8807 if (!i386_displacement (displacement_string_start
,
8808 displacement_string_end
))
8812 /* Special case for (%dx) while doing input/output op. */
8814 && operand_type_equal (&i
.base_reg
->reg_type
,
8815 ®16_inoutportreg
)
8817 && i
.log2_scale_factor
== 0
8818 && i
.seg
[i
.mem_operands
] == 0
8819 && !operand_type_check (i
.types
[this_operand
], disp
))
8821 i
.types
[this_operand
] = inoutportreg
;
8825 if (i386_index_check (operand_string
) == 0)
8827 i
.types
[this_operand
].bitfield
.mem
= 1;
8832 /* It's not a memory operand; argh! */
8833 as_bad (_("invalid char %s beginning operand %d `%s'"),
8834 output_invalid (*op_string
),
8839 return 1; /* Normal return. */
8842 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8843 that an rs_machine_dependent frag may reach. */
8846 i386_frag_max_var (fragS
*frag
)
8848 /* The only relaxable frags are for jumps.
8849 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8850 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8851 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8854 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8856 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
8858 /* STT_GNU_IFUNC symbol must go through PLT. */
8859 if ((symbol_get_bfdsym (fr_symbol
)->flags
8860 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
8863 if (!S_IS_EXTERNAL (fr_symbol
))
8864 /* Symbol may be weak or local. */
8865 return !S_IS_WEAK (fr_symbol
);
8867 /* Global symbols with non-default visibility can't be preempted. */
8868 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
8871 if (fr_var
!= NO_RELOC
)
8872 switch ((enum bfd_reloc_code_real
) fr_var
)
8874 case BFD_RELOC_386_PLT32
:
8875 case BFD_RELOC_X86_64_PLT32
:
8876 /* Symbol with PLT relocatin may be preempted. */
8882 /* Global symbols with default visibility in a shared library may be
8883 preempted by another definition. */
8888 /* md_estimate_size_before_relax()
8890 Called just before relax() for rs_machine_dependent frags. The x86
8891 assembler uses these frags to handle variable size jump
8894 Any symbol that is now undefined will not become defined.
8895 Return the correct fr_subtype in the frag.
8896 Return the initial "guess for variable size of frag" to caller.
8897 The guess is actually the growth beyond the fixed part. Whatever
8898 we do to grow the fixed or variable part contributes to our
8902 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8904 /* We've already got fragP->fr_subtype right; all we have to do is
8905 check for un-relaxable symbols. On an ELF system, we can't relax
8906 an externally visible symbol, because it may be overridden by a
8908 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8909 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8911 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
8914 #if defined (OBJ_COFF) && defined (TE_PE)
8915 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8916 && S_IS_WEAK (fragP
->fr_symbol
))
8920 /* Symbol is undefined in this segment, or we need to keep a
8921 reloc so that weak symbols can be overridden. */
8922 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8923 enum bfd_reloc_code_real reloc_type
;
8924 unsigned char *opcode
;
8927 if (fragP
->fr_var
!= NO_RELOC
)
8928 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8930 reloc_type
= BFD_RELOC_16_PCREL
;
8932 reloc_type
= BFD_RELOC_32_PCREL
;
8934 old_fr_fix
= fragP
->fr_fix
;
8935 opcode
= (unsigned char *) fragP
->fr_opcode
;
8937 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
8940 /* Make jmp (0xeb) a (d)word displacement jump. */
8942 fragP
->fr_fix
+= size
;
8943 fix_new (fragP
, old_fr_fix
, size
,
8945 fragP
->fr_offset
, 1,
8951 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
8953 /* Negate the condition, and branch past an
8954 unconditional jump. */
8957 /* Insert an unconditional jump. */
8959 /* We added two extra opcode bytes, and have a two byte
8961 fragP
->fr_fix
+= 2 + 2;
8962 fix_new (fragP
, old_fr_fix
+ 2, 2,
8964 fragP
->fr_offset
, 1,
8971 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8976 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8978 fragP
->fr_offset
, 1,
8980 fixP
->fx_signed
= 1;
8984 /* This changes the byte-displacement jump 0x7N
8985 to the (d)word-displacement jump 0x0f,0x8N. */
8986 opcode
[1] = opcode
[0] + 0x10;
8987 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8988 /* We've added an opcode byte. */
8989 fragP
->fr_fix
+= 1 + size
;
8990 fix_new (fragP
, old_fr_fix
+ 1, size
,
8992 fragP
->fr_offset
, 1,
8997 BAD_CASE (fragP
->fr_subtype
);
9001 return fragP
->fr_fix
- old_fr_fix
;
9004 /* Guess size depending on current relax state. Initially the relax
9005 state will correspond to a short jump and we return 1, because
9006 the variable part of the frag (the branch offset) is one byte
9007 long. However, we can relax a section more than once and in that
9008 case we must either set fr_subtype back to the unrelaxed state,
9009 or return the value for the appropriate branch. */
9010 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9013 /* Called after relax() is finished.
9015 In: Address of frag.
9016 fr_type == rs_machine_dependent.
9017 fr_subtype is what the address relaxed to.
9019 Out: Any fixSs and constants are set up.
9020 Caller will turn frag into a ".space 0". */
9023 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9026 unsigned char *opcode
;
9027 unsigned char *where_to_put_displacement
= NULL
;
9028 offsetT target_address
;
9029 offsetT opcode_address
;
9030 unsigned int extension
= 0;
9031 offsetT displacement_from_opcode_start
;
9033 opcode
= (unsigned char *) fragP
->fr_opcode
;
9035 /* Address we want to reach in file space. */
9036 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9038 /* Address opcode resides at in file space. */
9039 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9041 /* Displacement from opcode start to fill into instruction. */
9042 displacement_from_opcode_start
= target_address
- opcode_address
;
9044 if ((fragP
->fr_subtype
& BIG
) == 0)
9046 /* Don't have to change opcode. */
9047 extension
= 1; /* 1 opcode + 1 displacement */
9048 where_to_put_displacement
= &opcode
[1];
9052 if (no_cond_jump_promotion
9053 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9054 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9055 _("long jump required"));
9057 switch (fragP
->fr_subtype
)
9059 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9060 extension
= 4; /* 1 opcode + 4 displacement */
9062 where_to_put_displacement
= &opcode
[1];
9065 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9066 extension
= 2; /* 1 opcode + 2 displacement */
9068 where_to_put_displacement
= &opcode
[1];
9071 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9072 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9073 extension
= 5; /* 2 opcode + 4 displacement */
9074 opcode
[1] = opcode
[0] + 0x10;
9075 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9076 where_to_put_displacement
= &opcode
[2];
9079 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9080 extension
= 3; /* 2 opcode + 2 displacement */
9081 opcode
[1] = opcode
[0] + 0x10;
9082 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9083 where_to_put_displacement
= &opcode
[2];
9086 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9091 where_to_put_displacement
= &opcode
[3];
9095 BAD_CASE (fragP
->fr_subtype
);
9100 /* If size if less then four we are sure that the operand fits,
9101 but if it's 4, then it could be that the displacement is larger
9103 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9105 && ((addressT
) (displacement_from_opcode_start
- extension
9106 + ((addressT
) 1 << 31))
9107 > (((addressT
) 2 << 31) - 1)))
9109 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9110 _("jump target out of range"));
9111 /* Make us emit 0. */
9112 displacement_from_opcode_start
= extension
;
9114 /* Now put displacement after opcode. */
9115 md_number_to_chars ((char *) where_to_put_displacement
,
9116 (valueT
) (displacement_from_opcode_start
- extension
),
9117 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9118 fragP
->fr_fix
+= extension
;
9121 /* Apply a fixup (fixP) to segment data, once it has been determined
9122 by our caller that we have all the info we need to fix it up.
9124 Parameter valP is the pointer to the value of the bits.
9126 On the 386, immediates, displacements, and data pointers are all in
9127 the same (little-endian) format, so we don't need to care about which
9131 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9133 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9134 valueT value
= *valP
;
9136 #if !defined (TE_Mach)
9139 switch (fixP
->fx_r_type
)
9145 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9148 case BFD_RELOC_X86_64_32S
:
9149 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9152 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9155 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9160 if (fixP
->fx_addsy
!= NULL
9161 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9162 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9163 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9164 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9165 && !use_rela_relocations
)
9167 /* This is a hack. There should be a better way to handle this.
9168 This covers for the fact that bfd_install_relocation will
9169 subtract the current location (for partial_inplace, PC relative
9170 relocations); see more below. */
9174 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9177 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9179 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9182 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9185 || (symbol_section_p (fixP
->fx_addsy
)
9186 && sym_seg
!= absolute_section
))
9187 && !generic_force_reloc (fixP
))
9189 /* Yes, we add the values in twice. This is because
9190 bfd_install_relocation subtracts them out again. I think
9191 bfd_install_relocation is broken, but I don't dare change
9193 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9197 #if defined (OBJ_COFF) && defined (TE_PE)
9198 /* For some reason, the PE format does not store a
9199 section address offset for a PC relative symbol. */
9200 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9201 || S_IS_WEAK (fixP
->fx_addsy
))
9202 value
+= md_pcrel_from (fixP
);
9205 #if defined (OBJ_COFF) && defined (TE_PE)
9206 if (fixP
->fx_addsy
!= NULL
9207 && S_IS_WEAK (fixP
->fx_addsy
)
9208 /* PR 16858: Do not modify weak function references. */
9209 && ! fixP
->fx_pcrel
)
9211 #if !defined (TE_PEP)
9212 /* For x86 PE weak function symbols are neither PC-relative
9213 nor do they set S_IS_FUNCTION. So the only reliable way
9214 to detect them is to check the flags of their containing
9216 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9217 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9221 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9225 /* Fix a few things - the dynamic linker expects certain values here,
9226 and we must not disappoint it. */
9227 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9228 if (IS_ELF
&& fixP
->fx_addsy
)
9229 switch (fixP
->fx_r_type
)
9231 case BFD_RELOC_386_PLT32
:
9232 case BFD_RELOC_X86_64_PLT32
:
9233 /* Make the jump instruction point to the address of the operand. At
9234 runtime we merely add the offset to the actual PLT entry. */
9238 case BFD_RELOC_386_TLS_GD
:
9239 case BFD_RELOC_386_TLS_LDM
:
9240 case BFD_RELOC_386_TLS_IE_32
:
9241 case BFD_RELOC_386_TLS_IE
:
9242 case BFD_RELOC_386_TLS_GOTIE
:
9243 case BFD_RELOC_386_TLS_GOTDESC
:
9244 case BFD_RELOC_X86_64_TLSGD
:
9245 case BFD_RELOC_X86_64_TLSLD
:
9246 case BFD_RELOC_X86_64_GOTTPOFF
:
9247 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9248 value
= 0; /* Fully resolved at runtime. No addend. */
9250 case BFD_RELOC_386_TLS_LE
:
9251 case BFD_RELOC_386_TLS_LDO_32
:
9252 case BFD_RELOC_386_TLS_LE_32
:
9253 case BFD_RELOC_X86_64_DTPOFF32
:
9254 case BFD_RELOC_X86_64_DTPOFF64
:
9255 case BFD_RELOC_X86_64_TPOFF32
:
9256 case BFD_RELOC_X86_64_TPOFF64
:
9257 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9260 case BFD_RELOC_386_TLS_DESC_CALL
:
9261 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9262 value
= 0; /* Fully resolved at runtime. No addend. */
9263 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9267 case BFD_RELOC_386_GOT32
:
9268 case BFD_RELOC_X86_64_GOT32
:
9269 value
= 0; /* Fully resolved at runtime. No addend. */
9272 case BFD_RELOC_VTABLE_INHERIT
:
9273 case BFD_RELOC_VTABLE_ENTRY
:
9280 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9282 #endif /* !defined (TE_Mach) */
9284 /* Are we finished with this relocation now? */
9285 if (fixP
->fx_addsy
== NULL
)
9287 #if defined (OBJ_COFF) && defined (TE_PE)
9288 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9291 /* Remember value for tc_gen_reloc. */
9292 fixP
->fx_addnumber
= value
;
9293 /* Clear out the frag for now. */
9297 else if (use_rela_relocations
)
9299 fixP
->fx_no_overflow
= 1;
9300 /* Remember value for tc_gen_reloc. */
9301 fixP
->fx_addnumber
= value
;
9305 md_number_to_chars (p
, value
, fixP
->fx_size
);
9309 md_atof (int type
, char *litP
, int *sizeP
)
9311 /* This outputs the LITTLENUMs in REVERSE order;
9312 in accord with the bigendian 386. */
9313 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9316 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9319 output_invalid (int c
)
9322 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9325 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9326 "(0x%x)", (unsigned char) c
);
9327 return output_invalid_buf
;
9330 /* REG_STRING starts *before* REGISTER_PREFIX. */
9332 static const reg_entry
*
9333 parse_real_register (char *reg_string
, char **end_op
)
9335 char *s
= reg_string
;
9337 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9340 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9341 if (*s
== REGISTER_PREFIX
)
9344 if (is_space_char (*s
))
9348 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9350 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9351 return (const reg_entry
*) NULL
;
9355 /* For naked regs, make sure that we are not dealing with an identifier.
9356 This prevents confusing an identifier like `eax_var' with register
9358 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9359 return (const reg_entry
*) NULL
;
9363 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9365 /* Handle floating point regs, allowing spaces in the (i) part. */
9366 if (r
== i386_regtab
/* %st is first entry of table */)
9368 if (is_space_char (*s
))
9373 if (is_space_char (*s
))
9375 if (*s
>= '0' && *s
<= '7')
9379 if (is_space_char (*s
))
9384 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9389 /* We have "%st(" then garbage. */
9390 return (const reg_entry
*) NULL
;
9394 if (r
== NULL
|| allow_pseudo_reg
)
9397 if (operand_type_all_zero (&r
->reg_type
))
9398 return (const reg_entry
*) NULL
;
9400 if ((r
->reg_type
.bitfield
.reg32
9401 || r
->reg_type
.bitfield
.sreg3
9402 || r
->reg_type
.bitfield
.control
9403 || r
->reg_type
.bitfield
.debug
9404 || r
->reg_type
.bitfield
.test
)
9405 && !cpu_arch_flags
.bitfield
.cpui386
)
9406 return (const reg_entry
*) NULL
;
9408 if (r
->reg_type
.bitfield
.floatreg
9409 && !cpu_arch_flags
.bitfield
.cpu8087
9410 && !cpu_arch_flags
.bitfield
.cpu287
9411 && !cpu_arch_flags
.bitfield
.cpu387
)
9412 return (const reg_entry
*) NULL
;
9414 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9415 return (const reg_entry
*) NULL
;
9417 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9418 return (const reg_entry
*) NULL
;
9420 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9421 return (const reg_entry
*) NULL
;
9423 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9424 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9425 return (const reg_entry
*) NULL
;
9427 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9428 if (!allow_index_reg
9429 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9430 return (const reg_entry
*) NULL
;
9432 /* Upper 16 vector register is only available with VREX in 64bit
9434 if ((r
->reg_flags
& RegVRex
))
9436 if (!cpu_arch_flags
.bitfield
.cpuvrex
9437 || flag_code
!= CODE_64BIT
)
9438 return (const reg_entry
*) NULL
;
9443 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9444 || r
->reg_type
.bitfield
.reg64
)
9445 && (!cpu_arch_flags
.bitfield
.cpulm
9446 || !operand_type_equal (&r
->reg_type
, &control
))
9447 && flag_code
!= CODE_64BIT
)
9448 return (const reg_entry
*) NULL
;
9450 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9451 return (const reg_entry
*) NULL
;
9456 /* REG_STRING starts *before* REGISTER_PREFIX. */
9458 static const reg_entry
*
9459 parse_register (char *reg_string
, char **end_op
)
9463 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9464 r
= parse_real_register (reg_string
, end_op
);
9469 char *save
= input_line_pointer
;
9473 input_line_pointer
= reg_string
;
9474 c
= get_symbol_end ();
9475 symbolP
= symbol_find (reg_string
);
9476 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9478 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9480 know (e
->X_op
== O_register
);
9481 know (e
->X_add_number
>= 0
9482 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9483 r
= i386_regtab
+ e
->X_add_number
;
9484 if ((r
->reg_flags
& RegVRex
))
9486 *end_op
= input_line_pointer
;
9488 *input_line_pointer
= c
;
9489 input_line_pointer
= save
;
9495 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9498 char *end
= input_line_pointer
;
9501 r
= parse_register (name
, &input_line_pointer
);
9502 if (r
&& end
<= input_line_pointer
)
9504 *nextcharP
= *input_line_pointer
;
9505 *input_line_pointer
= 0;
9506 e
->X_op
= O_register
;
9507 e
->X_add_number
= r
- i386_regtab
;
9510 input_line_pointer
= end
;
9512 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9516 md_operand (expressionS
*e
)
9521 switch (*input_line_pointer
)
9523 case REGISTER_PREFIX
:
9524 r
= parse_real_register (input_line_pointer
, &end
);
9527 e
->X_op
= O_register
;
9528 e
->X_add_number
= r
- i386_regtab
;
9529 input_line_pointer
= end
;
9534 gas_assert (intel_syntax
);
9535 end
= input_line_pointer
++;
9537 if (*input_line_pointer
== ']')
9539 ++input_line_pointer
;
9540 e
->X_op_symbol
= make_expr_symbol (e
);
9541 e
->X_add_symbol
= NULL
;
9542 e
->X_add_number
= 0;
9548 input_line_pointer
= end
;
9555 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9556 const char *md_shortopts
= "kVQ:sqn";
9558 const char *md_shortopts
= "qn";
9561 #define OPTION_32 (OPTION_MD_BASE + 0)
9562 #define OPTION_64 (OPTION_MD_BASE + 1)
9563 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9564 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9565 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9566 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9567 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9568 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9569 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9570 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9571 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9572 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9573 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9574 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9575 #define OPTION_X32 (OPTION_MD_BASE + 14)
9576 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9577 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9578 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9579 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9580 #define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9581 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9582 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9583 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9584 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9586 struct option md_longopts
[] =
9588 {"32", no_argument
, NULL
, OPTION_32
},
9589 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9590 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9591 {"64", no_argument
, NULL
, OPTION_64
},
9593 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9594 {"x32", no_argument
, NULL
, OPTION_X32
},
9595 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
9597 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9598 {"march", required_argument
, NULL
, OPTION_MARCH
},
9599 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9600 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9601 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9602 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9603 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9604 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9605 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9606 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9607 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9608 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9609 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9610 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9611 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9612 # if defined (TE_PE) || defined (TE_PEP)
9613 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9615 {"momit-lock-prefix", required_argument
, NULL
, OPTION_OMIT_LOCK_PREFIX
},
9616 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9617 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
9618 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
9619 {NULL
, no_argument
, NULL
, 0}
9621 size_t md_longopts_size
= sizeof (md_longopts
);
9624 md_parse_option (int c
, char *arg
)
9632 optimize_align_code
= 0;
9639 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9640 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9641 should be emitted or not. FIXME: Not implemented. */
9645 /* -V: SVR4 argument to print version ID. */
9647 print_version_id ();
9650 /* -k: Ignore for FreeBSD compatibility. */
9655 /* -s: On i386 Solaris, this tells the native assembler to use
9656 .stab instead of .stab.excl. We always use .stab anyhow. */
9659 case OPTION_MSHARED
:
9663 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9664 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9667 const char **list
, **l
;
9669 list
= bfd_target_list ();
9670 for (l
= list
; *l
!= NULL
; l
++)
9671 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9672 || strcmp (*l
, "coff-x86-64") == 0
9673 || strcmp (*l
, "pe-x86-64") == 0
9674 || strcmp (*l
, "pei-x86-64") == 0
9675 || strcmp (*l
, "mach-o-x86-64") == 0)
9677 default_arch
= "x86_64";
9681 as_fatal (_("no compiled in support for x86_64"));
9687 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9691 const char **list
, **l
;
9693 list
= bfd_target_list ();
9694 for (l
= list
; *l
!= NULL
; l
++)
9695 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9697 default_arch
= "x86_64:32";
9701 as_fatal (_("no compiled in support for 32bit x86_64"));
9705 as_fatal (_("32bit x86_64 is only supported for ELF"));
9710 default_arch
= "i386";
9714 #ifdef SVR4_COMMENT_CHARS
9719 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9721 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9725 i386_comment_chars
= n
;
9731 arch
= xstrdup (arg
);
9735 as_fatal (_("invalid -march= option: `%s'"), arg
);
9736 next
= strchr (arch
, '+');
9739 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9741 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9744 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9747 cpu_arch_name
= cpu_arch
[j
].name
;
9748 cpu_sub_arch_name
= NULL
;
9749 cpu_arch_flags
= cpu_arch
[j
].flags
;
9750 cpu_arch_isa
= cpu_arch
[j
].type
;
9751 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9752 if (!cpu_arch_tune_set
)
9754 cpu_arch_tune
= cpu_arch_isa
;
9755 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9759 else if (*cpu_arch
[j
].name
== '.'
9760 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9762 /* ISA entension. */
9763 i386_cpu_flags flags
;
9765 if (!cpu_arch
[j
].negated
)
9766 flags
= cpu_flags_or (cpu_arch_flags
,
9769 flags
= cpu_flags_and_not (cpu_arch_flags
,
9772 if (!valid_iamcu_cpu_flags (&flags
))
9773 as_fatal (_("`%s' isn't valid for Intel MCU"), arch
);
9774 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9776 if (cpu_sub_arch_name
)
9778 char *name
= cpu_sub_arch_name
;
9779 cpu_sub_arch_name
= concat (name
,
9781 (const char *) NULL
);
9785 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9786 cpu_arch_flags
= flags
;
9787 cpu_arch_isa_flags
= flags
;
9793 if (j
>= ARRAY_SIZE (cpu_arch
))
9794 as_fatal (_("invalid -march= option: `%s'"), arg
);
9798 while (next
!= NULL
);
9803 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9804 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9806 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9808 cpu_arch_tune_set
= 1;
9809 cpu_arch_tune
= cpu_arch
[j
].type
;
9810 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9814 if (j
>= ARRAY_SIZE (cpu_arch
))
9815 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9818 case OPTION_MMNEMONIC
:
9819 if (strcasecmp (arg
, "att") == 0)
9821 else if (strcasecmp (arg
, "intel") == 0)
9824 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9827 case OPTION_MSYNTAX
:
9828 if (strcasecmp (arg
, "att") == 0)
9830 else if (strcasecmp (arg
, "intel") == 0)
9833 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9836 case OPTION_MINDEX_REG
:
9837 allow_index_reg
= 1;
9840 case OPTION_MNAKED_REG
:
9841 allow_naked_reg
= 1;
9844 case OPTION_MOLD_GCC
:
9848 case OPTION_MSSE2AVX
:
9852 case OPTION_MSSE_CHECK
:
9853 if (strcasecmp (arg
, "error") == 0)
9854 sse_check
= check_error
;
9855 else if (strcasecmp (arg
, "warning") == 0)
9856 sse_check
= check_warning
;
9857 else if (strcasecmp (arg
, "none") == 0)
9858 sse_check
= check_none
;
9860 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9863 case OPTION_MOPERAND_CHECK
:
9864 if (strcasecmp (arg
, "error") == 0)
9865 operand_check
= check_error
;
9866 else if (strcasecmp (arg
, "warning") == 0)
9867 operand_check
= check_warning
;
9868 else if (strcasecmp (arg
, "none") == 0)
9869 operand_check
= check_none
;
9871 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9874 case OPTION_MAVXSCALAR
:
9875 if (strcasecmp (arg
, "128") == 0)
9877 else if (strcasecmp (arg
, "256") == 0)
9880 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9883 case OPTION_MADD_BND_PREFIX
:
9887 case OPTION_MEVEXLIG
:
9888 if (strcmp (arg
, "128") == 0)
9890 else if (strcmp (arg
, "256") == 0)
9892 else if (strcmp (arg
, "512") == 0)
9895 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9898 case OPTION_MEVEXRCIG
:
9899 if (strcmp (arg
, "rne") == 0)
9901 else if (strcmp (arg
, "rd") == 0)
9903 else if (strcmp (arg
, "ru") == 0)
9905 else if (strcmp (arg
, "rz") == 0)
9908 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
9911 case OPTION_MEVEXWIG
:
9912 if (strcmp (arg
, "0") == 0)
9914 else if (strcmp (arg
, "1") == 0)
9917 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9920 # if defined (TE_PE) || defined (TE_PEP)
9921 case OPTION_MBIG_OBJ
:
9926 case OPTION_OMIT_LOCK_PREFIX
:
9927 if (strcasecmp (arg
, "yes") == 0)
9928 omit_lock_prefix
= 1;
9929 else if (strcasecmp (arg
, "no") == 0)
9930 omit_lock_prefix
= 0;
9932 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
9936 cpu_arch_flags
.bitfield
.cpuamd64
= 1;
9937 cpu_arch_flags
.bitfield
.cpuintel64
= 0;
9938 cpu_arch_isa_flags
.bitfield
.cpuamd64
= 1;
9939 cpu_arch_isa_flags
.bitfield
.cpuintel64
= 0;
9942 case OPTION_MINTEL64
:
9943 cpu_arch_flags
.bitfield
.cpuamd64
= 0;
9944 cpu_arch_flags
.bitfield
.cpuintel64
= 1;
9945 cpu_arch_isa_flags
.bitfield
.cpuamd64
= 0;
9946 cpu_arch_isa_flags
.bitfield
.cpuintel64
= 1;
9955 #define MESSAGE_TEMPLATE \
9959 show_arch (FILE *stream
, int ext
, int check
)
9961 static char message
[] = MESSAGE_TEMPLATE
;
9962 char *start
= message
+ 27;
9964 int size
= sizeof (MESSAGE_TEMPLATE
);
9971 left
= size
- (start
- message
);
9972 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9974 /* Should it be skipped? */
9975 if (cpu_arch
[j
].skip
)
9978 name
= cpu_arch
[j
].name
;
9979 len
= cpu_arch
[j
].len
;
9982 /* It is an extension. Skip if we aren't asked to show it. */
9993 /* It is an processor. Skip if we show only extension. */
9996 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9998 /* It is an impossible processor - skip. */
10002 /* Reserve 2 spaces for ", " or ",\0" */
10005 /* Check if there is any room. */
10013 p
= mempcpy (p
, name
, len
);
10017 /* Output the current message now and start a new one. */
10020 fprintf (stream
, "%s\n", message
);
10022 left
= size
- (start
- message
) - len
- 2;
10024 gas_assert (left
>= 0);
10026 p
= mempcpy (p
, name
, len
);
10031 fprintf (stream
, "%s\n", message
);
10035 md_show_usage (FILE *stream
)
10037 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10038 fprintf (stream
, _("\
10040 -V print assembler version number\n\
10043 fprintf (stream
, _("\
10044 -n Do not optimize code alignment\n\
10045 -q quieten some warnings\n"));
10046 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10047 fprintf (stream
, _("\
10050 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10051 || defined (TE_PE) || defined (TE_PEP))
10052 fprintf (stream
, _("\
10053 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10055 #ifdef SVR4_COMMENT_CHARS
10056 fprintf (stream
, _("\
10057 --divide do not treat `/' as a comment character\n"));
10059 fprintf (stream
, _("\
10060 --divide ignored\n"));
10062 fprintf (stream
, _("\
10063 -march=CPU[,+EXTENSION...]\n\
10064 generate code for CPU and EXTENSION, CPU is one of:\n"));
10065 show_arch (stream
, 0, 1);
10066 fprintf (stream
, _("\
10067 EXTENSION is combination of:\n"));
10068 show_arch (stream
, 1, 0);
10069 fprintf (stream
, _("\
10070 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10071 show_arch (stream
, 0, 0);
10072 fprintf (stream
, _("\
10073 -msse2avx encode SSE instructions with VEX prefix\n"));
10074 fprintf (stream
, _("\
10075 -msse-check=[none|error|warning]\n\
10076 check SSE instructions\n"));
10077 fprintf (stream
, _("\
10078 -moperand-check=[none|error|warning]\n\
10079 check operand combinations for validity\n"));
10080 fprintf (stream
, _("\
10081 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10083 fprintf (stream
, _("\
10084 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10086 fprintf (stream
, _("\
10087 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10088 for EVEX.W bit ignored instructions\n"));
10089 fprintf (stream
, _("\
10090 -mevexrcig=[rne|rd|ru|rz]\n\
10091 encode EVEX instructions with specific EVEX.RC value\n\
10092 for SAE-only ignored instructions\n"));
10093 fprintf (stream
, _("\
10094 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10095 fprintf (stream
, _("\
10096 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10097 fprintf (stream
, _("\
10098 -mindex-reg support pseudo index registers\n"));
10099 fprintf (stream
, _("\
10100 -mnaked-reg don't require `%%' prefix for registers\n"));
10101 fprintf (stream
, _("\
10102 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10103 fprintf (stream
, _("\
10104 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10105 fprintf (stream
, _("\
10106 -mshared disable branch optimization for shared code\n"));
10107 # if defined (TE_PE) || defined (TE_PEP)
10108 fprintf (stream
, _("\
10109 -mbig-obj generate big object files\n"));
10111 fprintf (stream
, _("\
10112 -momit-lock-prefix=[no|yes]\n\
10113 strip all lock prefixes\n"));
10114 fprintf (stream
, _("\
10115 -mamd64 accept only AMD64 ISA\n"));
10116 fprintf (stream
, _("\
10117 -mintel64 accept only Intel64 ISA\n"));
10120 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10121 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10122 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10124 /* Pick the target format to use. */
10127 i386_target_format (void)
10129 if (!strncmp (default_arch
, "x86_64", 6))
10131 update_code_flag (CODE_64BIT
, 1);
10132 if (default_arch
[6] == '\0')
10133 x86_elf_abi
= X86_64_ABI
;
10135 x86_elf_abi
= X86_64_X32_ABI
;
10137 else if (!strcmp (default_arch
, "i386"))
10138 update_code_flag (CODE_32BIT
, 1);
10139 else if (!strcmp (default_arch
, "iamcu"))
10141 update_code_flag (CODE_32BIT
, 1);
10142 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10144 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10145 cpu_arch_name
= "iamcu";
10146 cpu_sub_arch_name
= NULL
;
10147 cpu_arch_flags
= iamcu_flags
;
10148 cpu_arch_isa
= PROCESSOR_IAMCU
;
10149 cpu_arch_isa_flags
= iamcu_flags
;
10150 if (!cpu_arch_tune_set
)
10152 cpu_arch_tune
= cpu_arch_isa
;
10153 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10157 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10161 as_fatal (_("unknown architecture"));
10163 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10164 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10165 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10166 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10168 switch (OUTPUT_FLAVOR
)
10170 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10171 case bfd_target_aout_flavour
:
10172 return AOUT_TARGET_FORMAT
;
10174 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10175 # if defined (TE_PE) || defined (TE_PEP)
10176 case bfd_target_coff_flavour
:
10177 if (flag_code
== CODE_64BIT
)
10178 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10181 # elif defined (TE_GO32)
10182 case bfd_target_coff_flavour
:
10183 return "coff-go32";
10185 case bfd_target_coff_flavour
:
10186 return "coff-i386";
10189 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10190 case bfd_target_elf_flavour
:
10192 const char *format
;
10194 switch (x86_elf_abi
)
10197 format
= ELF_TARGET_FORMAT
;
10200 use_rela_relocations
= 1;
10202 format
= ELF_TARGET_FORMAT64
;
10204 case X86_64_X32_ABI
:
10205 use_rela_relocations
= 1;
10207 disallow_64bit_reloc
= 1;
10208 format
= ELF_TARGET_FORMAT32
;
10211 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10213 if (x86_elf_abi
!= X86_64_ABI
)
10214 as_fatal (_("Intel L1OM is 64bit only"));
10215 return ELF_TARGET_L1OM_FORMAT
;
10217 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10219 if (x86_elf_abi
!= X86_64_ABI
)
10220 as_fatal (_("Intel K1OM is 64bit only"));
10221 return ELF_TARGET_K1OM_FORMAT
;
10223 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10225 if (x86_elf_abi
!= I386_ABI
)
10226 as_fatal (_("Intel MCU is 32bit only"));
10227 return ELF_TARGET_IAMCU_FORMAT
;
10233 #if defined (OBJ_MACH_O)
10234 case bfd_target_mach_o_flavour
:
10235 if (flag_code
== CODE_64BIT
)
10237 use_rela_relocations
= 1;
10239 return "mach-o-x86-64";
10242 return "mach-o-i386";
10250 #endif /* OBJ_MAYBE_ more than one */
10253 md_undefined_symbol (char *name
)
10255 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10256 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10257 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10258 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10262 if (symbol_find (name
))
10263 as_bad (_("GOT already in symbol table"));
10264 GOT_symbol
= symbol_new (name
, undefined_section
,
10265 (valueT
) 0, &zero_address_frag
);
10272 /* Round up a section size to the appropriate boundary. */
10275 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10277 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10278 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10280 /* For a.out, force the section size to be aligned. If we don't do
10281 this, BFD will align it for us, but it will not write out the
10282 final bytes of the section. This may be a bug in BFD, but it is
10283 easier to fix it here since that is how the other a.out targets
10287 align
= bfd_get_section_alignment (stdoutput
, segment
);
10288 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
10295 /* On the i386, PC-relative offsets are relative to the start of the
10296 next instruction. That is, the address of the offset, plus its
10297 size, since the offset is always the last part of the insn. */
10300 md_pcrel_from (fixS
*fixP
)
10302 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10308 s_bss (int ignore ATTRIBUTE_UNUSED
)
10312 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10314 obj_elf_section_change_hook ();
10316 temp
= get_absolute_expression ();
10317 subseg_set (bss_section
, (subsegT
) temp
);
10318 demand_empty_rest_of_line ();
10324 i386_validate_fix (fixS
*fixp
)
10326 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
10328 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10332 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10337 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10339 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10341 fixp
->fx_subsy
= 0;
10346 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10349 bfd_reloc_code_real_type code
;
10351 switch (fixp
->fx_r_type
)
10353 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10354 case BFD_RELOC_SIZE32
:
10355 case BFD_RELOC_SIZE64
:
10356 if (S_IS_DEFINED (fixp
->fx_addsy
)
10357 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10359 /* Resolve size relocation against local symbol to size of
10360 the symbol plus addend. */
10361 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10362 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10363 && !fits_in_unsigned_long (value
))
10364 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10365 _("symbol size computation overflow"));
10366 fixp
->fx_addsy
= NULL
;
10367 fixp
->fx_subsy
= NULL
;
10368 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10373 case BFD_RELOC_X86_64_PLT32
:
10374 case BFD_RELOC_X86_64_GOT32
:
10375 case BFD_RELOC_X86_64_GOTPCREL
:
10376 case BFD_RELOC_386_PLT32
:
10377 case BFD_RELOC_386_GOT32
:
10378 case BFD_RELOC_386_GOTOFF
:
10379 case BFD_RELOC_386_GOTPC
:
10380 case BFD_RELOC_386_TLS_GD
:
10381 case BFD_RELOC_386_TLS_LDM
:
10382 case BFD_RELOC_386_TLS_LDO_32
:
10383 case BFD_RELOC_386_TLS_IE_32
:
10384 case BFD_RELOC_386_TLS_IE
:
10385 case BFD_RELOC_386_TLS_GOTIE
:
10386 case BFD_RELOC_386_TLS_LE_32
:
10387 case BFD_RELOC_386_TLS_LE
:
10388 case BFD_RELOC_386_TLS_GOTDESC
:
10389 case BFD_RELOC_386_TLS_DESC_CALL
:
10390 case BFD_RELOC_X86_64_TLSGD
:
10391 case BFD_RELOC_X86_64_TLSLD
:
10392 case BFD_RELOC_X86_64_DTPOFF32
:
10393 case BFD_RELOC_X86_64_DTPOFF64
:
10394 case BFD_RELOC_X86_64_GOTTPOFF
:
10395 case BFD_RELOC_X86_64_TPOFF32
:
10396 case BFD_RELOC_X86_64_TPOFF64
:
10397 case BFD_RELOC_X86_64_GOTOFF64
:
10398 case BFD_RELOC_X86_64_GOTPC32
:
10399 case BFD_RELOC_X86_64_GOT64
:
10400 case BFD_RELOC_X86_64_GOTPCREL64
:
10401 case BFD_RELOC_X86_64_GOTPC64
:
10402 case BFD_RELOC_X86_64_GOTPLT64
:
10403 case BFD_RELOC_X86_64_PLTOFF64
:
10404 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10405 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10406 case BFD_RELOC_RVA
:
10407 case BFD_RELOC_VTABLE_ENTRY
:
10408 case BFD_RELOC_VTABLE_INHERIT
:
10410 case BFD_RELOC_32_SECREL
:
10412 code
= fixp
->fx_r_type
;
10414 case BFD_RELOC_X86_64_32S
:
10415 if (!fixp
->fx_pcrel
)
10417 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10418 code
= fixp
->fx_r_type
;
10422 if (fixp
->fx_pcrel
)
10424 switch (fixp
->fx_size
)
10427 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10428 _("can not do %d byte pc-relative relocation"),
10430 code
= BFD_RELOC_32_PCREL
;
10432 case 1: code
= BFD_RELOC_8_PCREL
; break;
10433 case 2: code
= BFD_RELOC_16_PCREL
; break;
10434 case 4: code
= BFD_RELOC_32_PCREL
; break;
10436 case 8: code
= BFD_RELOC_64_PCREL
; break;
10442 switch (fixp
->fx_size
)
10445 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10446 _("can not do %d byte relocation"),
10448 code
= BFD_RELOC_32
;
10450 case 1: code
= BFD_RELOC_8
; break;
10451 case 2: code
= BFD_RELOC_16
; break;
10452 case 4: code
= BFD_RELOC_32
; break;
10454 case 8: code
= BFD_RELOC_64
; break;
10461 if ((code
== BFD_RELOC_32
10462 || code
== BFD_RELOC_32_PCREL
10463 || code
== BFD_RELOC_X86_64_32S
)
10465 && fixp
->fx_addsy
== GOT_symbol
)
10468 code
= BFD_RELOC_386_GOTPC
;
10470 code
= BFD_RELOC_X86_64_GOTPC32
;
10472 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10474 && fixp
->fx_addsy
== GOT_symbol
)
10476 code
= BFD_RELOC_X86_64_GOTPC64
;
10479 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10480 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10481 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10483 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10485 if (!use_rela_relocations
)
10487 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10488 vtable entry to be used in the relocation's section offset. */
10489 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10490 rel
->address
= fixp
->fx_offset
;
10491 #if defined (OBJ_COFF) && defined (TE_PE)
10492 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10493 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10498 /* Use the rela in 64bit mode. */
10501 if (disallow_64bit_reloc
)
10504 case BFD_RELOC_X86_64_DTPOFF64
:
10505 case BFD_RELOC_X86_64_TPOFF64
:
10506 case BFD_RELOC_64_PCREL
:
10507 case BFD_RELOC_X86_64_GOTOFF64
:
10508 case BFD_RELOC_X86_64_GOT64
:
10509 case BFD_RELOC_X86_64_GOTPCREL64
:
10510 case BFD_RELOC_X86_64_GOTPC64
:
10511 case BFD_RELOC_X86_64_GOTPLT64
:
10512 case BFD_RELOC_X86_64_PLTOFF64
:
10513 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10514 _("cannot represent relocation type %s in x32 mode"),
10515 bfd_get_reloc_code_name (code
));
10521 if (!fixp
->fx_pcrel
)
10522 rel
->addend
= fixp
->fx_offset
;
10526 case BFD_RELOC_X86_64_PLT32
:
10527 case BFD_RELOC_X86_64_GOT32
:
10528 case BFD_RELOC_X86_64_GOTPCREL
:
10529 case BFD_RELOC_X86_64_TLSGD
:
10530 case BFD_RELOC_X86_64_TLSLD
:
10531 case BFD_RELOC_X86_64_GOTTPOFF
:
10532 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10533 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10534 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10537 rel
->addend
= (section
->vma
10539 + fixp
->fx_addnumber
10540 + md_pcrel_from (fixp
));
10545 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10546 if (rel
->howto
== NULL
)
10548 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10549 _("cannot represent relocation type %s"),
10550 bfd_get_reloc_code_name (code
));
10551 /* Set howto to a garbage value so that we can keep going. */
10552 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10553 gas_assert (rel
->howto
!= NULL
);
10559 #include "tc-i386-intel.c"
10562 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10564 int saved_naked_reg
;
10565 char saved_register_dot
;
10567 saved_naked_reg
= allow_naked_reg
;
10568 allow_naked_reg
= 1;
10569 saved_register_dot
= register_chars
['.'];
10570 register_chars
['.'] = '.';
10571 allow_pseudo_reg
= 1;
10572 expression_and_evaluate (exp
);
10573 allow_pseudo_reg
= 0;
10574 register_chars
['.'] = saved_register_dot
;
10575 allow_naked_reg
= saved_naked_reg
;
10577 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10579 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10581 exp
->X_op
= O_constant
;
10582 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10583 .dw2_regnum
[flag_code
>> 1];
10586 exp
->X_op
= O_illegal
;
10591 tc_x86_frame_initial_instructions (void)
10593 static unsigned int sp_regno
[2];
10595 if (!sp_regno
[flag_code
>> 1])
10597 char *saved_input
= input_line_pointer
;
10598 char sp
[][4] = {"esp", "rsp"};
10601 input_line_pointer
= sp
[flag_code
>> 1];
10602 tc_x86_parse_to_dw2regnum (&exp
);
10603 gas_assert (exp
.X_op
== O_constant
);
10604 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10605 input_line_pointer
= saved_input
;
10608 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10609 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10613 x86_dwarf2_addr_size (void)
10615 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10616 if (x86_elf_abi
== X86_64_X32_ABI
)
10619 return bfd_arch_bits_per_address (stdoutput
) / 8;
10623 i386_elf_section_type (const char *str
, size_t len
)
10625 if (flag_code
== CODE_64BIT
10626 && len
== sizeof ("unwind") - 1
10627 && strncmp (str
, "unwind", 6) == 0)
10628 return SHT_X86_64_UNWIND
;
10635 i386_solaris_fix_up_eh_frame (segT sec
)
10637 if (flag_code
== CODE_64BIT
)
10638 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10644 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10648 exp
.X_op
= O_secrel
;
10649 exp
.X_add_symbol
= symbol
;
10650 exp
.X_add_number
= 0;
10651 emit_expr (&exp
, size
);
10655 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10656 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10659 x86_64_section_letter (int letter
, char **ptr_msg
)
10661 if (flag_code
== CODE_64BIT
)
10664 return SHF_X86_64_LARGE
;
10666 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10669 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10674 x86_64_section_word (char *str
, size_t len
)
10676 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10677 return SHF_X86_64_LARGE
;
10683 handle_large_common (int small ATTRIBUTE_UNUSED
)
10685 if (flag_code
!= CODE_64BIT
)
10687 s_comm_internal (0, elf_common_parse
);
10688 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10692 static segT lbss_section
;
10693 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10694 asection
*saved_bss_section
= bss_section
;
10696 if (lbss_section
== NULL
)
10698 flagword applicable
;
10699 segT seg
= now_seg
;
10700 subsegT subseg
= now_subseg
;
10702 /* The .lbss section is for local .largecomm symbols. */
10703 lbss_section
= subseg_new (".lbss", 0);
10704 applicable
= bfd_applicable_section_flags (stdoutput
);
10705 bfd_set_section_flags (stdoutput
, lbss_section
,
10706 applicable
& SEC_ALLOC
);
10707 seg_info (lbss_section
)->bss
= 1;
10709 subseg_set (seg
, subseg
);
10712 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10713 bss_section
= lbss_section
;
10715 s_comm_internal (0, elf_common_parse
);
10717 elf_com_section_ptr
= saved_com_section_ptr
;
10718 bss_section
= saved_bss_section
;
10721 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */