1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Intel 80386 machine specific gas.
23 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
24 Bugs & suggestions are completely welcome. This is free software.
25 Please help us make it better. */
31 #include "dwarf2dbg.h"
32 #include "opcode/i386.h"
34 #ifndef REGISTER_WARNINGS
35 #define REGISTER_WARNINGS 1
38 #ifndef INFER_ADDR_PREFIX
39 #define INFER_ADDR_PREFIX 1
42 #ifndef SCALE1_WHEN_NO_INDEX
43 /* Specifying a scale factor besides 1 when there is no index is
44 futile. eg. `mov (%ebx,2),%al' does exactly the same as
45 `mov (%ebx),%al'. To slavishly follow what the programmer
46 specified, set SCALE1_WHEN_NO_INDEX to 0. */
47 #define SCALE1_WHEN_NO_INDEX 1
53 static unsigned int mode_from_disp_size
PARAMS ((unsigned int));
54 static int fits_in_signed_byte
PARAMS ((offsetT
));
55 static int fits_in_unsigned_byte
PARAMS ((offsetT
));
56 static int fits_in_unsigned_word
PARAMS ((offsetT
));
57 static int fits_in_signed_word
PARAMS ((offsetT
));
58 static int smallest_imm_type
PARAMS ((offsetT
));
59 static offsetT offset_in_range
PARAMS ((offsetT
, int));
60 static int add_prefix
PARAMS ((unsigned int));
61 static void set_16bit_code_flag
PARAMS ((int));
62 static void set_16bit_gcc_code_flag
PARAMS ((int));
63 static void set_intel_syntax
PARAMS ((int));
64 static void set_cpu_arch
PARAMS ((int));
67 static bfd_reloc_code_real_type reloc
68 PARAMS ((int, int, bfd_reloc_code_real_type
));
71 /* 'md_assemble ()' gathers together information and puts it into a
78 const reg_entry
*regs
;
83 /* TM holds the template for the insn were currently assembling. */
86 /* SUFFIX holds the instruction mnemonic suffix if given.
87 (e.g. 'l' for 'movl') */
90 /* OPERANDS gives the number of given operands. */
91 unsigned int operands
;
93 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
94 of given register, displacement, memory operands and immediate
96 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
98 /* TYPES [i] is the type (see above #defines) which tells us how to
99 use OP[i] for the corresponding operand. */
100 unsigned int types
[MAX_OPERANDS
];
102 /* Displacement expression, immediate expression, or register for each
104 union i386_op op
[MAX_OPERANDS
];
106 /* Relocation type for operand */
108 enum bfd_reloc_code_real disp_reloc
[MAX_OPERANDS
];
110 int disp_reloc
[MAX_OPERANDS
];
113 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
114 the base index byte below. */
115 const reg_entry
*base_reg
;
116 const reg_entry
*index_reg
;
117 unsigned int log2_scale_factor
;
119 /* SEG gives the seg_entries of this insn. They are zero unless
120 explicit segment overrides are given. */
121 const seg_entry
*seg
[2];
123 /* PREFIX holds all the given prefix opcodes (usually null).
124 PREFIXES is the number of prefix opcodes. */
125 unsigned int prefixes
;
126 unsigned char prefix
[MAX_PREFIXES
];
128 /* RM and SIB are the modrm byte and the sib byte where the
129 addressing modes of this insn are encoded. */
135 typedef struct _i386_insn i386_insn
;
137 /* List of chars besides those in app.c:symbol_chars that can start an
138 operand. Used to prevent the scrubber eating vital white-space. */
140 const char extra_symbol_chars
[] = "*%-(@";
142 const char extra_symbol_chars
[] = "*%-(";
145 /* This array holds the chars that always start a comment. If the
146 pre-processor is disabled, these aren't very useful. */
147 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
148 /* Putting '/' here makes it impossible to use the divide operator.
149 However, we need it for compatibility with SVR4 systems. */
150 const char comment_chars
[] = "#/";
151 #define PREFIX_SEPARATOR '\\'
153 const char comment_chars
[] = "#";
154 #define PREFIX_SEPARATOR '/'
157 /* This array holds the chars that only start a comment at the beginning of
158 a line. If the line seems to have the form '# 123 filename'
159 .line and .file directives will appear in the pre-processed output.
160 Note that input_file.c hand checks for '#' at the beginning of the
161 first line of the input file. This is because the compiler outputs
162 #NO_APP at the beginning of its output.
163 Also note that comments started like this one will always work if
164 '/' isn't otherwise defined. */
165 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
166 const char line_comment_chars
[] = "";
168 const char line_comment_chars
[] = "/";
171 const char line_separator_chars
[] = ";";
173 /* Chars that can be used to separate mant from exp in floating point
175 const char EXP_CHARS
[] = "eE";
177 /* Chars that mean this number is a floating point constant
180 const char FLT_CHARS
[] = "fFdDxX";
182 /* Tables for lexical analysis. */
183 static char mnemonic_chars
[256];
184 static char register_chars
[256];
185 static char operand_chars
[256];
186 static char identifier_chars
[256];
187 static char digit_chars
[256];
189 /* Lexical macros. */
190 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
191 #define is_operand_char(x) (operand_chars[(unsigned char) x])
192 #define is_register_char(x) (register_chars[(unsigned char) x])
193 #define is_space_char(x) ((x) == ' ')
194 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
195 #define is_digit_char(x) (digit_chars[(unsigned char) x])
197 /* All non-digit non-letter charcters that may occur in an operand. */
198 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
200 /* md_assemble() always leaves the strings it's passed unaltered. To
201 effect this we maintain a stack of saved characters that we've smashed
202 with '\0's (indicating end of strings for various sub-fields of the
203 assembler instruction). */
204 static char save_stack
[32];
205 static char *save_stack_p
;
206 #define END_STRING_AND_SAVE(s) \
207 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
208 #define RESTORE_END_STRING(s) \
209 do { *(s) = *--save_stack_p; } while (0)
211 /* The instruction we're assembling. */
214 /* Possible templates for current insn. */
215 static const templates
*current_templates
;
217 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
218 static expressionS disp_expressions
[2], im_expressions
[2];
220 /* Current operand we are working on. */
221 static int this_operand
;
223 /* 1 if we're writing 16-bit code,
225 static int flag_16bit_code
;
227 /* 1 for intel syntax,
229 static int intel_syntax
= 0;
231 /* 1 if register prefix % not required. */
232 static int allow_naked_reg
= 0;
234 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
235 leave, push, and pop instructions so that gcc has the same stack
236 frame as in 32 bit mode. */
237 static char stackop_size
= '\0';
239 /* Non-zero to quieten some warnings. */
240 static int quiet_warnings
= 0;
243 static const char *cpu_arch_name
= NULL
;
245 /* CPU feature flags. */
246 static unsigned int cpu_arch_flags
= 0;
248 /* Interface to relax_segment.
249 There are 2 relax states for 386 jump insns: one for conditional &
250 one for unconditional jumps. This is because these two types of
251 jumps add different sizes to frags when we're figuring out what
252 sort of jump to choose to reach a given label. */
256 #define UNCOND_JUMP 2
260 #define SMALL16 (SMALL|CODE16)
262 #define BIG16 (BIG|CODE16)
266 #define INLINE __inline__
272 #define ENCODE_RELAX_STATE(type,size) \
273 ((relax_substateT) ((type<<2) | (size)))
274 #define SIZE_FROM_RELAX_STATE(s) \
275 ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) )
277 /* This table is used by relax_frag to promote short jumps to long
278 ones where necessary. SMALL (short) jumps may be promoted to BIG
279 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
280 don't allow a short jump in a 32 bit code segment to be promoted to
281 a 16 bit offset jump because it's slower (requires data size
282 prefix), and doesn't work, unless the destination is in the bottom
283 64k of the code segment (The top 16 bits of eip are zeroed). */
285 const relax_typeS md_relax_table
[] =
288 1) most positive reach of this state,
289 2) most negative reach of this state,
290 3) how many bytes this mode will add to the size of the current frag
291 4) which index into the table to try if we can't fit into this one. */
297 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
298 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
299 /* dword conditionals adds 4 bytes to frag:
300 1 extra opcode byte, 3 extra displacement bytes. */
302 /* word conditionals add 2 bytes to frag:
303 1 extra opcode byte, 1 extra displacement byte. */
306 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
307 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
308 /* dword jmp adds 3 bytes to frag:
309 0 extra opcode bytes, 3 extra displacement bytes. */
311 /* word jmp adds 1 byte to frag:
312 0 extra opcode bytes, 1 extra displacement byte. */
317 static const arch_entry cpu_arch
[] = {
319 {"i186", Cpu086
|Cpu186
},
320 {"i286", Cpu086
|Cpu186
|Cpu286
},
321 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
322 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
323 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
324 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
325 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
326 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
327 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
|Cpu3dnow
},
328 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|Cpu3dnow
},
333 i386_align_code (fragP
, count
)
337 /* Various efficient no-op patterns for aligning code labels.
338 Note: Don't try to assemble the instructions in the comments.
339 0L and 0w are not legal. */
340 static const char f32_1
[] =
342 static const char f32_2
[] =
343 {0x89,0xf6}; /* movl %esi,%esi */
344 static const char f32_3
[] =
345 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
346 static const char f32_4
[] =
347 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
348 static const char f32_5
[] =
350 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
351 static const char f32_6
[] =
352 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
353 static const char f32_7
[] =
354 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
355 static const char f32_8
[] =
357 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
358 static const char f32_9
[] =
359 {0x89,0xf6, /* movl %esi,%esi */
360 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
361 static const char f32_10
[] =
362 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
363 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
364 static const char f32_11
[] =
365 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
366 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
367 static const char f32_12
[] =
368 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
369 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
370 static const char f32_13
[] =
371 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
372 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
373 static const char f32_14
[] =
374 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
375 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
376 static const char f32_15
[] =
377 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
378 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
379 static const char f16_3
[] =
380 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
381 static const char f16_4
[] =
382 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
383 static const char f16_5
[] =
385 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
386 static const char f16_6
[] =
387 {0x89,0xf6, /* mov %si,%si */
388 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
389 static const char f16_7
[] =
390 {0x8d,0x74,0x00, /* lea 0(%si),%si */
391 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
392 static const char f16_8
[] =
393 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
394 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
395 static const char *const f32_patt
[] = {
396 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
397 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
399 static const char *const f16_patt
[] = {
400 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
401 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
404 if (count
> 0 && count
<= 15)
408 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
409 f16_patt
[count
- 1], count
);
411 /* Adjust jump offset. */
412 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
415 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
416 f32_patt
[count
- 1], count
);
417 fragP
->fr_var
= count
;
421 static char *output_invalid
PARAMS ((int c
));
422 static int i386_operand
PARAMS ((char *operand_string
));
423 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
424 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
428 static void s_bss
PARAMS ((int));
431 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
433 static INLINE
unsigned int
434 mode_from_disp_size (t
)
437 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
)) ? 2 : 0;
441 fits_in_signed_byte (num
)
444 return (num
>= -128) && (num
<= 127);
448 fits_in_unsigned_byte (num
)
451 return (num
& 0xff) == num
;
455 fits_in_unsigned_word (num
)
458 return (num
& 0xffff) == num
;
462 fits_in_signed_word (num
)
465 return (-32768 <= num
) && (num
<= 32767);
469 smallest_imm_type (num
)
472 if (cpu_arch_flags
!= 0
473 && cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
))
475 /* This code is disabled on the 486 because all the Imm1 forms
476 in the opcode table are slower on the i486. They're the
477 versions with the implicitly specified single-position
478 displacement, which has another syntax if you really want to
481 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
;
483 return (fits_in_signed_byte (num
)
484 ? (Imm8S
| Imm8
| Imm16
| Imm32
)
485 : fits_in_unsigned_byte (num
)
486 ? (Imm8
| Imm16
| Imm32
)
487 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
493 offset_in_range (val
, size
)
501 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
502 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
503 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
507 /* If BFD64, sign extend val. */
508 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
509 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
511 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
513 char buf1
[40], buf2
[40];
515 sprint_value (buf1
, val
);
516 sprint_value (buf2
, val
& mask
);
517 as_warn (_("%s shortened to %s"), buf1
, buf2
);
522 /* Returns 0 if attempting to add a prefix where one from the same
523 class already exists, 1 if non rep/repne added, 2 if rep/repne
537 case CS_PREFIX_OPCODE
:
538 case DS_PREFIX_OPCODE
:
539 case ES_PREFIX_OPCODE
:
540 case FS_PREFIX_OPCODE
:
541 case GS_PREFIX_OPCODE
:
542 case SS_PREFIX_OPCODE
:
546 case REPNE_PREFIX_OPCODE
:
547 case REPE_PREFIX_OPCODE
:
550 case LOCK_PREFIX_OPCODE
:
558 case ADDR_PREFIX_OPCODE
:
562 case DATA_PREFIX_OPCODE
:
569 as_bad (_("same type of prefix used twice"));
574 i
.prefix
[q
] = prefix
;
579 set_16bit_code_flag (new_16bit_code_flag
)
580 int new_16bit_code_flag
;
582 flag_16bit_code
= new_16bit_code_flag
;
587 set_16bit_gcc_code_flag (new_16bit_code_flag
)
588 int new_16bit_code_flag
;
590 flag_16bit_code
= new_16bit_code_flag
;
591 stackop_size
= new_16bit_code_flag
? 'l' : '\0';
595 set_intel_syntax (syntax_flag
)
598 /* Find out if register prefixing is specified. */
599 int ask_naked_reg
= 0;
602 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
604 char *string
= input_line_pointer
;
605 int e
= get_symbol_end ();
607 if (strcmp (string
, "prefix") == 0)
609 else if (strcmp (string
, "noprefix") == 0)
612 as_bad (_("bad argument to syntax directive."));
613 *input_line_pointer
= e
;
615 demand_empty_rest_of_line ();
617 intel_syntax
= syntax_flag
;
619 if (ask_naked_reg
== 0)
622 allow_naked_reg
= (intel_syntax
623 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
625 /* Conservative default. */
630 allow_naked_reg
= (ask_naked_reg
< 0);
635 int dummy ATTRIBUTE_UNUSED
;
639 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
641 char *string
= input_line_pointer
;
642 int e
= get_symbol_end ();
645 for (i
= 0; cpu_arch
[i
].name
; i
++)
647 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
649 cpu_arch_name
= cpu_arch
[i
].name
;
650 cpu_arch_flags
= cpu_arch
[i
].flags
;
654 if (!cpu_arch
[i
].name
)
655 as_bad (_("no such architecture: `%s'"), string
);
657 *input_line_pointer
= e
;
660 as_bad (_("missing cpu architecture"));
662 demand_empty_rest_of_line ();
665 const pseudo_typeS md_pseudo_table
[] =
667 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
668 {"align", s_align_bytes
, 0},
670 {"align", s_align_ptwo
, 0},
672 {"arch", set_cpu_arch
, 0},
676 {"ffloat", float_cons
, 'f'},
677 {"dfloat", float_cons
, 'd'},
678 {"tfloat", float_cons
, 'x'},
680 {"noopt", s_ignore
, 0},
681 {"optim", s_ignore
, 0},
682 {"code16gcc", set_16bit_gcc_code_flag
, 1},
683 {"code16", set_16bit_code_flag
, 1},
684 {"code32", set_16bit_code_flag
, 0},
685 {"intel_syntax", set_intel_syntax
, 1},
686 {"att_syntax", set_intel_syntax
, 0},
687 {"file", dwarf2_directive_file
, 0},
688 {"loc", dwarf2_directive_loc
, 0},
692 /* For interface with expression (). */
693 extern char *input_line_pointer
;
695 /* Hash table for instruction mnemonic lookup. */
696 static struct hash_control
*op_hash
;
698 /* Hash table for register lookup. */
699 static struct hash_control
*reg_hash
;
704 const char *hash_err
;
706 /* Initialize op_hash hash table. */
707 op_hash
= hash_new ();
710 register const template *optab
;
711 register templates
*core_optab
;
713 /* Setup for loop. */
715 core_optab
= (templates
*) xmalloc (sizeof (templates
));
716 core_optab
->start
= optab
;
721 if (optab
->name
== NULL
722 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
724 /* different name --> ship out current template list;
725 add to hash table; & begin anew. */
726 core_optab
->end
= optab
;
727 hash_err
= hash_insert (op_hash
,
733 as_fatal (_("Internal Error: Can't hash %s: %s"),
737 if (optab
->name
== NULL
)
739 core_optab
= (templates
*) xmalloc (sizeof (templates
));
740 core_optab
->start
= optab
;
745 /* Initialize reg_hash hash table. */
746 reg_hash
= hash_new ();
748 register const reg_entry
*regtab
;
750 for (regtab
= i386_regtab
;
751 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
754 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
760 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
765 for (c
= 0; c
< 256; c
++)
770 mnemonic_chars
[c
] = c
;
771 register_chars
[c
] = c
;
772 operand_chars
[c
] = c
;
774 else if (islower (c
))
776 mnemonic_chars
[c
] = c
;
777 register_chars
[c
] = c
;
778 operand_chars
[c
] = c
;
780 else if (isupper (c
))
782 mnemonic_chars
[c
] = tolower (c
);
783 register_chars
[c
] = mnemonic_chars
[c
];
784 operand_chars
[c
] = c
;
787 if (isalpha (c
) || isdigit (c
))
788 identifier_chars
[c
] = c
;
791 identifier_chars
[c
] = c
;
792 operand_chars
[c
] = c
;
797 identifier_chars
['@'] = '@';
799 digit_chars
['-'] = '-';
800 identifier_chars
['_'] = '_';
801 identifier_chars
['.'] = '.';
803 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
804 operand_chars
[(unsigned char) *p
] = *p
;
807 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
808 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
810 record_alignment (text_section
, 2);
811 record_alignment (data_section
, 2);
812 record_alignment (bss_section
, 2);
818 i386_print_statistics (file
)
821 hash_print_statistics (file
, "i386 opcode", op_hash
);
822 hash_print_statistics (file
, "i386 register", reg_hash
);
827 /* Debugging routines for md_assemble. */
828 static void pi
PARAMS ((char *, i386_insn
*));
829 static void pte
PARAMS ((template *));
830 static void pt
PARAMS ((unsigned int));
831 static void pe
PARAMS ((expressionS
*));
832 static void ps
PARAMS ((symbolS
*));
839 register template *p
;
842 fprintf (stdout
, "%s: template ", line
);
844 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x",
845 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
846 fprintf (stdout
, " base %x index %x scale %x\n",
847 x
->bi
.base
, x
->bi
.index
, x
->bi
.scale
);
848 for (i
= 0; i
< x
->operands
; i
++)
850 fprintf (stdout
, " #%d: ", i
+ 1);
852 fprintf (stdout
, "\n");
854 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
855 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
856 if (x
->types
[i
] & Imm
)
858 if (x
->types
[i
] & Disp
)
868 fprintf (stdout
, " %d operands ", t
->operands
);
869 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
870 if (t
->extension_opcode
!= None
)
871 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
872 if (t
->opcode_modifier
& D
)
873 fprintf (stdout
, "D");
874 if (t
->opcode_modifier
& W
)
875 fprintf (stdout
, "W");
876 fprintf (stdout
, "\n");
877 for (i
= 0; i
< t
->operands
; i
++)
879 fprintf (stdout
, " #%d type ", i
+ 1);
880 pt (t
->operand_types
[i
]);
881 fprintf (stdout
, "\n");
889 fprintf (stdout
, " operation %d\n", e
->X_op
);
890 fprintf (stdout
, " add_number %ld (%lx)\n",
891 (long) e
->X_add_number
, (long) e
->X_add_number
);
894 fprintf (stdout
, " add_symbol ");
895 ps (e
->X_add_symbol
);
896 fprintf (stdout
, "\n");
900 fprintf (stdout
, " op_symbol ");
902 fprintf (stdout
, "\n");
910 fprintf (stdout
, "%s type %s%s",
912 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
913 segment_name (S_GET_SEGMENT (s
)));
932 { BaseIndex
, "BaseIndex" },
936 { InOutPortReg
, "InOutPortReg" },
937 { ShiftCount
, "ShiftCount" },
938 { Control
, "control reg" },
939 { Test
, "test reg" },
940 { Debug
, "debug reg" },
941 { FloatReg
, "FReg" },
942 { FloatAcc
, "FAcc" },
946 { JumpAbsolute
, "Jump Absolute" },
957 register struct type_name
*ty
;
961 fprintf (stdout
, _("Unknown"));
965 for (ty
= type_names
; ty
->mask
; ty
++)
967 fprintf (stdout
, "%s, ", ty
->tname
);
972 #endif /* DEBUG386 */
975 tc_i386_force_relocation (fixp
)
979 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
980 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
985 return fixp
->fx_r_type
== 7;
990 static bfd_reloc_code_real_type reloc
991 PARAMS ((int, int, bfd_reloc_code_real_type
));
993 static bfd_reloc_code_real_type
994 reloc (size
, pcrel
, other
)
997 bfd_reloc_code_real_type other
;
999 if (other
!= NO_RELOC
)
1006 case 1: return BFD_RELOC_8_PCREL
;
1007 case 2: return BFD_RELOC_16_PCREL
;
1008 case 4: return BFD_RELOC_32_PCREL
;
1010 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1016 case 1: return BFD_RELOC_8
;
1017 case 2: return BFD_RELOC_16
;
1018 case 4: return BFD_RELOC_32
;
1020 as_bad (_("can not do %d byte relocation"), size
);
1023 return BFD_RELOC_NONE
;
1026 /* Here we decide which fixups can be adjusted to make them relative to
1027 the beginning of the section instead of the symbol. Basically we need
1028 to make sure that the dynamic relocations are done correctly, so in
1029 some cases we force the original symbol to be used. */
1032 tc_i386_fix_adjustable (fixP
)
1035 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1036 /* Prevent all adjustments to global symbols, or else dynamic
1037 linking will not work correctly. */
1038 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1039 || S_IS_WEAK (fixP
->fx_addsy
))
1042 /* adjust_reloc_syms doesn't know about the GOT. */
1043 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1044 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1045 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1046 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1047 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1052 #define reloc(SIZE,PCREL,OTHER) 0
1053 #define BFD_RELOC_16 0
1054 #define BFD_RELOC_32 0
1055 #define BFD_RELOC_16_PCREL 0
1056 #define BFD_RELOC_32_PCREL 0
1057 #define BFD_RELOC_386_PLT32 0
1058 #define BFD_RELOC_386_GOT32 0
1059 #define BFD_RELOC_386_GOTOFF 0
1062 static int intel_float_operand
PARAMS ((char *mnemonic
));
1065 intel_float_operand (mnemonic
)
1068 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1071 if (mnemonic
[0] == 'f')
1077 /* This is the guts of the machine-dependent assembler. LINE points to a
1078 machine dependent instruction. This function is supposed to emit
1079 the frags/bytes it assembles to. */
1085 /* Points to template once we've found it. */
1088 /* Count the size of the instruction generated. */
1093 char mnemonic
[MAX_MNEM_SIZE
];
1095 /* Initialize globals. */
1096 memset (&i
, '\0', sizeof (i
));
1097 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1098 i
.disp_reloc
[j
] = NO_RELOC
;
1099 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1100 memset (im_expressions
, '\0', sizeof (im_expressions
));
1101 save_stack_p
= save_stack
;
1103 /* First parse an instruction mnemonic & call i386_operand for the operands.
1104 We assume that the scrubber has arranged it so that line[0] is the valid
1105 start of a (possibly prefixed) mnemonic. */
1108 char *token_start
= l
;
1111 /* Non-zero if we found a prefix only acceptable with string insns. */
1112 const char *expecting_string_instruction
= NULL
;
1117 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1120 if (mnem_p
>= mnemonic
+ sizeof (mnemonic
))
1122 as_bad (_("no such instruction: `%s'"), token_start
);
1127 if (!is_space_char (*l
)
1128 && *l
!= END_OF_INSN
1129 && *l
!= PREFIX_SEPARATOR
)
1131 as_bad (_("invalid character %s in mnemonic"),
1132 output_invalid (*l
));
1135 if (token_start
== l
)
1137 if (*l
== PREFIX_SEPARATOR
)
1138 as_bad (_("expecting prefix; got nothing"));
1140 as_bad (_("expecting mnemonic; got nothing"));
1144 /* Look up instruction (or prefix) via hash table. */
1145 current_templates
= hash_find (op_hash
, mnemonic
);
1147 if (*l
!= END_OF_INSN
1148 && (! is_space_char (*l
) || l
[1] != END_OF_INSN
)
1149 && current_templates
1150 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1152 /* If we are in 16-bit mode, do not allow addr16 or data16.
1153 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1154 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1155 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1158 as_bad (_("redundant %s prefix"),
1159 current_templates
->start
->name
);
1162 /* Add prefix, checking for repeated prefixes. */
1163 switch (add_prefix (current_templates
->start
->base_opcode
))
1168 expecting_string_instruction
= current_templates
->start
->name
;
1171 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1178 if (!current_templates
)
1180 /* See if we can get a match by trimming off a suffix. */
1183 case WORD_MNEM_SUFFIX
:
1184 case BYTE_MNEM_SUFFIX
:
1185 case SHORT_MNEM_SUFFIX
:
1186 case LONG_MNEM_SUFFIX
:
1187 i
.suffix
= mnem_p
[-1];
1189 current_templates
= hash_find (op_hash
, mnemonic
);
1193 case DWORD_MNEM_SUFFIX
:
1196 i
.suffix
= mnem_p
[-1];
1198 current_templates
= hash_find (op_hash
, mnemonic
);
1202 if (!current_templates
)
1204 as_bad (_("no such instruction: `%s'"), token_start
);
1209 /* Check if instruction is supported on specified architecture. */
1210 if (cpu_arch_flags
!= 0)
1212 if (current_templates
->start
->cpu_flags
& ~cpu_arch_flags
)
1214 as_warn (_("`%s' is not supported on `%s'"),
1215 current_templates
->start
->name
, cpu_arch_name
);
1217 else if ((Cpu386
& ~cpu_arch_flags
) && !flag_16bit_code
)
1219 as_warn (_("use .code16 to ensure correct addressing mode"));
1223 /* Check for rep/repne without a string instruction. */
1224 if (expecting_string_instruction
1225 && !(current_templates
->start
->opcode_modifier
& IsString
))
1227 as_bad (_("expecting string instruction after `%s'"),
1228 expecting_string_instruction
);
1232 /* There may be operands to parse. */
1233 if (*l
!= END_OF_INSN
)
1235 /* 1 if operand is pending after ','. */
1236 unsigned int expecting_operand
= 0;
1238 /* Non-zero if operand parens not balanced. */
1239 unsigned int paren_not_balanced
;
1243 /* Skip optional white space before operand. */
1244 if (is_space_char (*l
))
1246 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1248 as_bad (_("invalid character %s before operand %d"),
1249 output_invalid (*l
),
1253 token_start
= l
; /* after white space */
1254 paren_not_balanced
= 0;
1255 while (paren_not_balanced
|| *l
!= ',')
1257 if (*l
== END_OF_INSN
)
1259 if (paren_not_balanced
)
1262 as_bad (_("unbalanced parenthesis in operand %d."),
1265 as_bad (_("unbalanced brackets in operand %d."),
1270 break; /* we are done */
1272 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1274 as_bad (_("invalid character %s in operand %d"),
1275 output_invalid (*l
),
1282 ++paren_not_balanced
;
1284 --paren_not_balanced
;
1289 ++paren_not_balanced
;
1291 --paren_not_balanced
;
1295 if (l
!= token_start
)
1296 { /* Yes, we've read in another operand. */
1297 unsigned int operand_ok
;
1298 this_operand
= i
.operands
++;
1299 if (i
.operands
> MAX_OPERANDS
)
1301 as_bad (_("spurious operands; (%d operands/instruction max)"),
1305 /* Now parse operand adding info to 'i' as we go along. */
1306 END_STRING_AND_SAVE (l
);
1310 i386_intel_operand (token_start
,
1311 intel_float_operand (mnemonic
));
1313 operand_ok
= i386_operand (token_start
);
1315 RESTORE_END_STRING (l
);
1321 if (expecting_operand
)
1323 expecting_operand_after_comma
:
1324 as_bad (_("expecting operand after ','; got nothing"));
1329 as_bad (_("expecting operand before ','; got nothing"));
1334 /* Now *l must be either ',' or END_OF_INSN. */
1337 if (*++l
== END_OF_INSN
)
1339 /* Just skip it, if it's \n complain. */
1340 goto expecting_operand_after_comma
;
1342 expecting_operand
= 1;
1345 while (*l
!= END_OF_INSN
);
1349 /* Now we've parsed the mnemonic into a set of templates, and have the
1352 Next, we find a template that matches the given insn,
1353 making sure the overlap of the given operands types is consistent
1354 with the template operand types. */
1356 #define MATCH(overlap, given, template) \
1357 ((overlap & ~JumpAbsolute) \
1358 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1360 /* If given types r0 and r1 are registers they must be of the same type
1361 unless the expected operand type register overlap is null.
1362 Note that Acc in a template matches every size of reg. */
1363 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1364 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1365 ((g0) & Reg) == ((g1) & Reg) || \
1366 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1369 register unsigned int overlap0
, overlap1
;
1370 unsigned int overlap2
;
1371 unsigned int found_reverse_match
;
1374 /* All intel opcodes have reversed operands except for "bound" and
1375 "enter". We also don't reverse intersegment "jmp" and "call"
1376 instructions with 2 immediate operands so that the immediate segment
1377 precedes the offset, as it does when in AT&T mode. "enter" and the
1378 intersegment "jmp" and "call" instructions are the only ones that
1379 have two immediate operands. */
1380 if (intel_syntax
&& i
.operands
> 1
1381 && (strcmp (mnemonic
, "bound") != 0)
1382 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1384 union i386_op temp_op
;
1385 unsigned int temp_type
;
1386 #ifdef BFD_ASSEMBLER
1387 enum bfd_reloc_code_real temp_disp_reloc
;
1389 int temp_disp_reloc
;
1394 if (i
.operands
== 2)
1399 else if (i
.operands
== 3)
1404 temp_type
= i
.types
[xchg2
];
1405 i
.types
[xchg2
] = i
.types
[xchg1
];
1406 i
.types
[xchg1
] = temp_type
;
1407 temp_op
= i
.op
[xchg2
];
1408 i
.op
[xchg2
] = i
.op
[xchg1
];
1409 i
.op
[xchg1
] = temp_op
;
1410 temp_disp_reloc
= i
.disp_reloc
[xchg2
];
1411 i
.disp_reloc
[xchg2
] = i
.disp_reloc
[xchg1
];
1412 i
.disp_reloc
[xchg1
] = temp_disp_reloc
;
1414 if (i
.mem_operands
== 2)
1416 const seg_entry
*temp_seg
;
1417 temp_seg
= i
.seg
[0];
1418 i
.seg
[0] = i
.seg
[1];
1419 i
.seg
[1] = temp_seg
;
1425 /* Try to ensure constant immediates are represented in the smallest
1427 char guess_suffix
= 0;
1431 guess_suffix
= i
.suffix
;
1432 else if (i
.reg_operands
)
1434 /* Figure out a suffix from the last register operand specified.
1435 We can't do this properly yet, ie. excluding InOutPortReg,
1436 but the following works for instructions with immediates.
1437 In any case, we can't set i.suffix yet. */
1438 for (op
= i
.operands
; --op
>= 0;)
1439 if (i
.types
[op
] & Reg
)
1441 if (i
.types
[op
] & Reg8
)
1442 guess_suffix
= BYTE_MNEM_SUFFIX
;
1443 else if (i
.types
[op
] & Reg16
)
1444 guess_suffix
= WORD_MNEM_SUFFIX
;
1448 else if (flag_16bit_code
^ (i
.prefix
[DATA_PREFIX
] != 0))
1449 guess_suffix
= WORD_MNEM_SUFFIX
;
1451 for (op
= i
.operands
; --op
>= 0;)
1452 if ((i
.types
[op
] & Imm
)
1453 && i
.op
[op
].imms
->X_op
== O_constant
)
1455 /* If a suffix is given, this operand may be shortened. */
1456 switch (guess_suffix
)
1458 case WORD_MNEM_SUFFIX
:
1459 i
.types
[op
] |= Imm16
;
1461 case BYTE_MNEM_SUFFIX
:
1462 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
;
1466 /* If this operand is at most 16 bits, convert it to a
1467 signed 16 bit number before trying to see whether it will
1468 fit in an even smaller size. This allows a 16-bit operand
1469 such as $0xffe0 to be recognised as within Imm8S range. */
1470 if ((i
.types
[op
] & Imm16
)
1471 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
)0xffff) == 0)
1473 i
.op
[op
].imms
->X_add_number
=
1474 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1476 i
.types
[op
] |= smallest_imm_type ((long) i
.op
[op
].imms
->X_add_number
);
1480 if (i
.disp_operands
)
1482 /* Try to use the smallest displacement type too. */
1485 for (op
= i
.operands
; --op
>= 0;)
1486 if ((i
.types
[op
] & Disp
)
1487 && i
.op
[op
].imms
->X_op
== O_constant
)
1489 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1491 if (i
.types
[op
] & Disp16
)
1493 /* We know this operand is at most 16 bits, so
1494 convert to a signed 16 bit number before trying
1495 to see whether it will fit in an even smaller
1498 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1500 if (fits_in_signed_byte (disp
))
1501 i
.types
[op
] |= Disp8
;
1508 found_reverse_match
= 0;
1509 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1511 : (i
.suffix
== WORD_MNEM_SUFFIX
1513 : (i
.suffix
== SHORT_MNEM_SUFFIX
1515 : (i
.suffix
== LONG_MNEM_SUFFIX
1517 : (i
.suffix
== DWORD_MNEM_SUFFIX
1519 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
? No_xSuf
: 0))))));
1521 for (t
= current_templates
->start
;
1522 t
< current_templates
->end
;
1525 /* Must have right number of operands. */
1526 if (i
.operands
!= t
->operands
)
1529 /* Check the suffix, except for some instructions in intel mode. */
1530 if ((t
->opcode_modifier
& suffix_check
)
1532 && (t
->opcode_modifier
& IgnoreSize
))
1534 && t
->base_opcode
== 0xd9
1535 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1536 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1539 else if (!t
->operands
)
1540 /* 0 operands always matches. */
1543 overlap0
= i
.types
[0] & t
->operand_types
[0];
1544 switch (t
->operands
)
1547 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1552 overlap1
= i
.types
[1] & t
->operand_types
[1];
1553 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1554 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1555 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1556 t
->operand_types
[0],
1557 overlap1
, i
.types
[1],
1558 t
->operand_types
[1]))
1560 /* Check if other direction is valid ... */
1561 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1564 /* Try reversing direction of operands. */
1565 overlap0
= i
.types
[0] & t
->operand_types
[1];
1566 overlap1
= i
.types
[1] & t
->operand_types
[0];
1567 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1568 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1569 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1570 t
->operand_types
[1],
1571 overlap1
, i
.types
[1],
1572 t
->operand_types
[0]))
1574 /* Does not match either direction. */
1577 /* found_reverse_match holds which of D or FloatDR
1579 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1582 /* Found a forward 2 operand match here. */
1583 if (t
->operands
== 3)
1585 /* Here we make use of the fact that there are no
1586 reverse match 3 operand instructions, and all 3
1587 operand instructions only need to be checked for
1588 register consistency between operands 2 and 3. */
1589 overlap2
= i
.types
[2] & t
->operand_types
[2];
1590 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1591 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1592 t
->operand_types
[1],
1593 overlap2
, i
.types
[2],
1594 t
->operand_types
[2]))
1598 /* Found either forward/reverse 2 or 3 operand match here:
1599 slip through to break. */
1601 /* We've found a match; break out of loop. */
1604 if (t
== current_templates
->end
)
1606 /* We found no match. */
1607 as_bad (_("suffix or operands invalid for `%s'"),
1608 current_templates
->start
->name
);
1612 if (!quiet_warnings
)
1615 && ((i
.types
[0] & JumpAbsolute
)
1616 != (t
->operand_types
[0] & JumpAbsolute
)))
1618 as_warn (_("indirect %s without `*'"), t
->name
);
1621 if ((t
->opcode_modifier
& (IsPrefix
|IgnoreSize
))
1622 == (IsPrefix
|IgnoreSize
))
1624 /* Warn them that a data or address size prefix doesn't
1625 affect assembly of the next line of code. */
1626 as_warn (_("stand-alone `%s' prefix"), t
->name
);
1630 /* Copy the template we found. */
1632 if (found_reverse_match
)
1634 /* If we found a reverse match we must alter the opcode
1635 direction bit. found_reverse_match holds bits to change
1636 (different for int & float insns). */
1638 i
.tm
.base_opcode
^= found_reverse_match
;
1640 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1641 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1644 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1647 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1648 i
.tm
.base_opcode
^= FloatR
;
1650 if (i
.tm
.opcode_modifier
& FWait
)
1651 if (! add_prefix (FWAIT_OPCODE
))
1654 /* Check string instruction segment overrides. */
1655 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1657 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1658 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1660 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1662 as_bad (_("`%s' operand %d must use `%%es' segment"),
1667 /* There's only ever one segment override allowed per instruction.
1668 This instruction possibly has a legal segment override on the
1669 second operand, so copy the segment to where non-string
1670 instructions store it, allowing common code. */
1671 i
.seg
[0] = i
.seg
[1];
1673 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1675 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1677 as_bad (_("`%s' operand %d must use `%%es' segment"),
1685 /* If matched instruction specifies an explicit instruction mnemonic
1687 if (i
.tm
.opcode_modifier
& (Size16
| Size32
))
1689 if (i
.tm
.opcode_modifier
& Size16
)
1690 i
.suffix
= WORD_MNEM_SUFFIX
;
1692 i
.suffix
= LONG_MNEM_SUFFIX
;
1694 else if (i
.reg_operands
)
1696 /* If there's no instruction mnemonic suffix we try to invent one
1697 based on register operands. */
1700 /* We take i.suffix from the last register operand specified,
1701 Destination register type is more significant than source
1704 for (op
= i
.operands
; --op
>= 0;)
1705 if ((i
.types
[op
] & Reg
)
1706 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
1708 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
1709 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
1714 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
1717 for (op
= i
.operands
; --op
>= 0;)
1719 /* If this is an eight bit register, it's OK. If it's
1720 the 16 or 32 bit version of an eight bit register,
1721 we will just use the low portion, and that's OK too. */
1722 if (i
.types
[op
] & Reg8
)
1725 /* movzx and movsx should not generate this warning. */
1727 && (i
.tm
.base_opcode
== 0xfb7
1728 || i
.tm
.base_opcode
== 0xfb6
1729 || i
.tm
.base_opcode
== 0xfbe
1730 || i
.tm
.base_opcode
== 0xfbf))
1733 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
1735 /* Check that the template allows eight bit regs
1736 This kills insns such as `orb $1,%edx', which
1737 maybe should be allowed. */
1738 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
1742 #if REGISTER_WARNINGS
1744 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1745 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1746 (i
.op
[op
].regs
- (i
.types
[op
] & Reg16
? 8 : 16))->reg_name
,
1747 i
.op
[op
].regs
->reg_name
,
1752 /* Any other register is bad. */
1753 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
1755 | Control
| Debug
| Test
1756 | FloatReg
| FloatAcc
))
1758 as_bad (_("`%%%s' not allowed with `%s%c'"),
1759 i
.op
[op
].regs
->reg_name
,
1766 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
1770 for (op
= i
.operands
; --op
>= 0;)
1771 /* Reject eight bit registers, except where the template
1772 requires them. (eg. movzb) */
1773 if ((i
.types
[op
] & Reg8
) != 0
1774 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
1776 as_bad (_("`%%%s' not allowed with `%s%c'"),
1777 i
.op
[op
].regs
->reg_name
,
1782 #if REGISTER_WARNINGS
1783 /* Warn if the e prefix on a general reg is missing. */
1784 else if (!quiet_warnings
1785 && (i
.types
[op
] & Reg16
) != 0
1786 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
1788 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1789 (i
.op
[op
].regs
+ 8)->reg_name
,
1790 i
.op
[op
].regs
->reg_name
,
1795 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
1798 for (op
= i
.operands
; --op
>= 0;)
1799 /* Reject eight bit registers, except where the template
1800 requires them. (eg. movzb) */
1801 if ((i
.types
[op
] & Reg8
) != 0
1802 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
1804 as_bad (_("`%%%s' not allowed with `%s%c'"),
1805 i
.op
[op
].regs
->reg_name
,
1810 #if REGISTER_WARNINGS
1811 /* Warn if the e prefix on a general reg is present. */
1812 else if (!quiet_warnings
1813 && (i
.types
[op
] & Reg32
) != 0
1814 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
1816 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1817 (i
.op
[op
].regs
- 8)->reg_name
,
1818 i
.op
[op
].regs
->reg_name
,
1823 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
1824 /* Do nothing if the instruction is going to ignore the prefix. */
1829 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
1831 i
.suffix
= stackop_size
;
1834 /* Make still unresolved immediate matches conform to size of immediate
1835 given in i.suffix. Note: overlap2 cannot be an immediate! */
1836 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
))
1837 && overlap0
!= Imm8
&& overlap0
!= Imm8S
1838 && overlap0
!= Imm16
&& overlap0
!= Imm32
)
1842 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
1843 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
: Imm32
));
1845 else if (overlap0
== (Imm16
| Imm32
))
1848 (flag_16bit_code
^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32
;
1852 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
1856 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32
))
1857 && overlap1
!= Imm8
&& overlap1
!= Imm8S
1858 && overlap1
!= Imm16
&& overlap1
!= Imm32
)
1862 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
1863 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
: Imm32
));
1865 else if (overlap1
== (Imm16
| Imm32
))
1868 (flag_16bit_code
^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32
;
1872 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
1876 assert ((overlap2
& Imm
) == 0);
1878 i
.types
[0] = overlap0
;
1879 if (overlap0
& ImplicitRegister
)
1881 if (overlap0
& Imm1
)
1882 i
.imm_operands
= 0; /* kludge for shift insns. */
1884 i
.types
[1] = overlap1
;
1885 if (overlap1
& ImplicitRegister
)
1888 i
.types
[2] = overlap2
;
1889 if (overlap2
& ImplicitRegister
)
1892 /* Finalize opcode. First, we change the opcode based on the operand
1893 size given by i.suffix: We need not change things for byte insns. */
1895 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
1897 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
1901 /* For movzx and movsx, need to check the register type. */
1903 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
1904 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
1906 unsigned int prefix
= DATA_PREFIX_OPCODE
;
1908 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
1909 if (!add_prefix (prefix
))
1913 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
1915 /* It's not a byte, select word/dword operation. */
1916 if (i
.tm
.opcode_modifier
& W
)
1918 if (i
.tm
.opcode_modifier
& ShortForm
)
1919 i
.tm
.base_opcode
|= 8;
1921 i
.tm
.base_opcode
|= 1;
1923 /* Now select between word & dword operations via the operand
1924 size prefix, except for instructions that will ignore this
1926 if (((intel_syntax
&& (i
.suffix
== DWORD_MNEM_SUFFIX
))
1927 || i
.suffix
== LONG_MNEM_SUFFIX
) == flag_16bit_code
1928 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
1930 unsigned int prefix
= DATA_PREFIX_OPCODE
;
1931 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
1932 prefix
= ADDR_PREFIX_OPCODE
;
1934 if (! add_prefix (prefix
))
1937 /* Size floating point instruction. */
1938 if (i
.suffix
== LONG_MNEM_SUFFIX
1939 || (intel_syntax
&& i
.suffix
== DWORD_MNEM_SUFFIX
))
1941 if (i
.tm
.opcode_modifier
& FloatMF
)
1942 i
.tm
.base_opcode
^= 4;
1946 if (i
.tm
.opcode_modifier
& ImmExt
)
1948 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1949 opcode suffix which is coded in the same place as an 8-bit
1950 immediate field would be. Here we fake an 8-bit immediate
1951 operand from the opcode suffix stored in tm.extension_opcode. */
1955 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1957 exp
= &im_expressions
[i
.imm_operands
++];
1958 i
.op
[i
.operands
].imms
= exp
;
1959 i
.types
[i
.operands
++] = Imm8
;
1960 exp
->X_op
= O_constant
;
1961 exp
->X_add_number
= i
.tm
.extension_opcode
;
1962 i
.tm
.extension_opcode
= None
;
1965 /* For insns with operands there are more diddles to do to the opcode. */
1968 /* Default segment register this instruction will use
1969 for memory accesses. 0 means unknown.
1970 This is only for optimizing out unnecessary segment overrides. */
1971 const seg_entry
*default_seg
= 0;
1973 /* The imul $imm, %reg instruction is converted into
1974 imul $imm, %reg, %reg, and the clr %reg instruction
1975 is converted into xor %reg, %reg. */
1976 if (i
.tm
.opcode_modifier
& regKludge
)
1978 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
1979 /* Pretend we saw the extra register operand. */
1980 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
1981 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
1982 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
1986 if (i
.tm
.opcode_modifier
& ShortForm
)
1988 /* The register or float register operand is in operand 0 or 1. */
1989 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
1990 /* Register goes in low 3 bits of opcode. */
1991 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
1992 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1994 /* Warn about some common errors, but press on regardless.
1995 The first case can be generated by gcc (<= 2.8.1). */
1996 if (i
.operands
== 2)
1998 /* Reversed arguments on faddp, fsubp, etc. */
1999 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2000 i
.op
[1].regs
->reg_name
,
2001 i
.op
[0].regs
->reg_name
);
2005 /* Extraneous `l' suffix on fp insn. */
2006 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2007 i
.op
[0].regs
->reg_name
);
2011 else if (i
.tm
.opcode_modifier
& Modrm
)
2013 /* The opcode is completed (modulo i.tm.extension_opcode which
2014 must be put into the modrm byte).
2015 Now, we make the modrm & index base bytes based on all the
2016 info we've collected. */
2018 /* i.reg_operands MUST be the number of real register operands;
2019 implicit registers do not count. */
2020 if (i
.reg_operands
== 2)
2022 unsigned int source
, dest
;
2023 source
= ((i
.types
[0]
2024 & (Reg
| RegMMX
| RegXMM
2026 | Control
| Debug
| Test
))
2031 /* One of the register operands will be encoded in the
2032 i.tm.reg field, the other in the combined i.tm.mode
2033 and i.tm.regmem fields. If no form of this
2034 instruction supports a memory destination operand,
2035 then we assume the source operand may sometimes be
2036 a memory operand and so we need to store the
2037 destination in the i.rm.reg field. */
2038 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2040 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2041 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2045 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2046 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2050 { /* If it's not 2 reg operands... */
2053 unsigned int fake_zero_displacement
= 0;
2054 unsigned int op
= ((i
.types
[0] & AnyMem
)
2056 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2063 if (! i
.disp_operands
)
2064 fake_zero_displacement
= 1;
2067 /* Operand is just <disp> */
2068 if (flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0))
2070 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2071 i
.types
[op
] &= ~Disp
;
2072 i
.types
[op
] |= Disp16
;
2076 i
.rm
.regmem
= NO_BASE_REGISTER
;
2077 i
.types
[op
] &= ~Disp
;
2078 i
.types
[op
] |= Disp32
;
2081 else /* ! i.base_reg && i.index_reg */
2083 i
.sib
.index
= i
.index_reg
->reg_num
;
2084 i
.sib
.base
= NO_BASE_REGISTER
;
2085 i
.sib
.scale
= i
.log2_scale_factor
;
2086 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2087 i
.types
[op
] &= ~Disp
;
2088 i
.types
[op
] |= Disp32
; /* Must be 32 bit. */
2091 else if (i
.base_reg
->reg_type
& Reg16
)
2093 switch (i
.base_reg
->reg_num
)
2098 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2099 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2106 if ((i
.types
[op
] & Disp
) == 0)
2108 /* fake (%bp) into 0(%bp) */
2109 i
.types
[op
] |= Disp8
;
2110 fake_zero_displacement
= 1;
2113 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2114 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2116 default: /* (%si) -> 4 or (%di) -> 5 */
2117 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2119 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2121 else /* i.base_reg and 32 bit mode */
2123 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2124 i
.sib
.base
= i
.base_reg
->reg_num
;
2125 if (i
.base_reg
->reg_num
== EBP_REG_NUM
)
2128 if (i
.disp_operands
== 0)
2130 fake_zero_displacement
= 1;
2131 i
.types
[op
] |= Disp8
;
2134 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2138 i
.sib
.scale
= i
.log2_scale_factor
;
2141 /* <disp>(%esp) becomes two byte modrm
2142 with no index register. We've already
2143 stored the code for esp in i.rm.regmem
2144 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2145 base register besides %esp will not use
2146 the extra modrm byte. */
2147 i
.sib
.index
= NO_INDEX_REGISTER
;
2148 #if ! SCALE1_WHEN_NO_INDEX
2149 /* Another case where we force the second
2151 if (i
.log2_scale_factor
)
2152 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2157 i
.sib
.index
= i
.index_reg
->reg_num
;
2158 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2160 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2163 if (fake_zero_displacement
)
2165 /* Fakes a zero displacement assuming that i.types[op]
2166 holds the correct displacement size. */
2169 assert (i
.op
[op
].disps
== 0);
2170 exp
= &disp_expressions
[i
.disp_operands
++];
2171 i
.op
[op
].disps
= exp
;
2172 exp
->X_op
= O_constant
;
2173 exp
->X_add_number
= 0;
2174 exp
->X_add_symbol
= (symbolS
*) 0;
2175 exp
->X_op_symbol
= (symbolS
*) 0;
2179 /* Fill in i.rm.reg or i.rm.regmem field with register
2180 operand (if any) based on i.tm.extension_opcode.
2181 Again, we must be careful to make sure that
2182 segment/control/debug/test/MMX registers are coded
2183 into the i.rm.reg field. */
2188 & (Reg
| RegMMX
| RegXMM
2190 | Control
| Debug
| Test
))
2193 & (Reg
| RegMMX
| RegXMM
2195 | Control
| Debug
| Test
))
2198 /* If there is an extension opcode to put here, the
2199 register number must be put into the regmem field. */
2200 if (i
.tm
.extension_opcode
!= None
)
2201 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2203 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2205 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2206 we must set it to 3 to indicate this is a register
2207 operand in the regmem field. */
2208 if (!i
.mem_operands
)
2212 /* Fill in i.rm.reg field with extension opcode (if any). */
2213 if (i
.tm
.extension_opcode
!= None
)
2214 i
.rm
.reg
= i
.tm
.extension_opcode
;
2217 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2219 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2220 && i
.op
[0].regs
->reg_num
== 1)
2222 as_bad (_("you can't `pop %%cs'"));
2225 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2227 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
2231 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2233 /* For the string instructions that allow a segment override
2234 on one of their operands, the default segment is ds. */
2238 /* If a segment was explicitly specified,
2239 and the specified segment is not the default,
2240 use an opcode prefix to select it.
2241 If we never figured out what the default segment is,
2242 then default_seg will be zero at this point,
2243 and the specified segment prefix will always be used. */
2244 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2246 if (! add_prefix (i
.seg
[0]->seg_prefix
))
2250 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2252 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2253 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2257 /* Handle conversion of 'int $3' --> special int3 insn. */
2258 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2260 i
.tm
.base_opcode
= INT3_OPCODE
;
2264 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
2265 && i
.op
[0].disps
->X_op
== O_constant
)
2267 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2268 the absolute address given by the constant. Since ix86 jumps and
2269 calls are pc relative, we need to generate a reloc. */
2270 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2271 i
.op
[0].disps
->X_op
= O_symbol
;
2274 /* We are ready to output the insn. */
2279 if (i
.tm
.opcode_modifier
& Jump
)
2286 if (flag_16bit_code
)
2290 if (i
.prefix
[DATA_PREFIX
])
2301 if (i
.prefixes
!= 0 && !intel_syntax
)
2302 as_warn (_("skipping prefixes on this instruction"));
2304 /* It's always a symbol; End frag & setup for relax.
2305 Make sure there is enough room in this frag for the largest
2306 instruction we may generate in md_convert_frag. This is 2
2307 bytes for the opcode and room for the prefix and largest
2309 frag_grow (prefix
+ 2 + size
);
2310 insn_size
+= prefix
+ 1;
2311 /* Prefix and 1 opcode byte go in fr_fix. */
2312 p
= frag_more (prefix
+ 1);
2314 *p
++ = DATA_PREFIX_OPCODE
;
2315 *p
= i
.tm
.base_opcode
;
2316 /* 1 possible extra opcode + displacement go in var part.
2317 Pass reloc in fr_var. */
2318 frag_var (rs_machine_dependent
,
2321 ((unsigned char) *p
== JUMP_PC_RELATIVE
2322 ? ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
) | code16
2323 : ENCODE_RELAX_STATE (COND_JUMP
, SMALL
) | code16
),
2324 i
.op
[0].disps
->X_add_symbol
,
2325 i
.op
[0].disps
->X_add_number
,
2328 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
2332 if (i
.tm
.opcode_modifier
& JumpByte
)
2334 /* This is a loop or jecxz type instruction. */
2336 if (i
.prefix
[ADDR_PREFIX
])
2339 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2348 if (flag_16bit_code
)
2351 if (i
.prefix
[DATA_PREFIX
])
2354 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
2364 if (i
.prefixes
!= 0 && !intel_syntax
)
2365 as_warn (_("skipping prefixes on this instruction"));
2367 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2369 insn_size
+= 1 + size
;
2370 p
= frag_more (1 + size
);
2374 /* Opcode can be at most two bytes. */
2375 insn_size
+= 2 + size
;
2376 p
= frag_more (2 + size
);
2377 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2379 *p
++ = i
.tm
.base_opcode
& 0xff;
2381 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2382 i
.op
[0].disps
, 1, reloc (size
, 1, i
.disp_reloc
[0]));
2384 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
2391 if (flag_16bit_code
)
2395 if (i
.prefix
[DATA_PREFIX
])
2406 if (i
.prefixes
!= 0 && !intel_syntax
)
2407 as_warn (_("skipping prefixes on this instruction"));
2409 /* 1 opcode; 2 segment; offset */
2410 insn_size
+= prefix
+ 1 + 2 + size
;
2411 p
= frag_more (prefix
+ 1 + 2 + size
);
2413 *p
++ = DATA_PREFIX_OPCODE
;
2414 *p
++ = i
.tm
.base_opcode
;
2415 if (i
.op
[1].imms
->X_op
== O_constant
)
2417 offsetT n
= i
.op
[1].imms
->X_add_number
;
2420 && !fits_in_unsigned_word (n
)
2421 && !fits_in_signed_word (n
))
2423 as_bad (_("16-bit jump out of range"));
2426 md_number_to_chars (p
, n
, size
);
2429 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2430 i
.op
[1].imms
, 0, reloc (size
, 0, i
.disp_reloc
[0]));
2431 if (i
.op
[0].imms
->X_op
!= O_constant
)
2432 as_bad (_("can't handle non absolute segment in `%s'"),
2434 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
2438 /* Output normal instructions here. */
2441 /* The prefix bytes. */
2443 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2450 md_number_to_chars (p
, (valueT
) *q
, 1);
2454 /* Now the opcode; be careful about word order here! */
2455 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2458 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2460 else if (fits_in_unsigned_word (i
.tm
.base_opcode
))
2464 /* Put out high byte first: can't use md_number_to_chars! */
2465 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2466 *p
= i
.tm
.base_opcode
& 0xff;
2469 { /* Opcode is either 3 or 4 bytes. */
2470 if (i
.tm
.base_opcode
& 0xff000000)
2474 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
2481 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
2482 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2483 *p
= (i
.tm
.base_opcode
) & 0xff;
2486 /* Now the modrm byte and sib byte (if present). */
2487 if (i
.tm
.opcode_modifier
& Modrm
)
2491 md_number_to_chars (p
,
2492 (valueT
) (i
.rm
.regmem
<< 0
2496 /* If i.rm.regmem == ESP (4)
2497 && i.rm.mode != (Register mode)
2499 ==> need second modrm byte. */
2500 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2502 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2506 md_number_to_chars (p
,
2507 (valueT
) (i
.sib
.base
<< 0
2509 | i
.sib
.scale
<< 6),
2514 if (i
.disp_operands
)
2516 register unsigned int n
;
2518 for (n
= 0; n
< i
.operands
; n
++)
2520 if (i
.types
[n
] & Disp
)
2522 if (i
.op
[n
].disps
->X_op
== O_constant
)
2528 if (i
.types
[n
] & (Disp8
| Disp16
))
2531 if (i
.types
[n
] & Disp8
)
2534 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
2537 p
= frag_more (size
);
2538 md_number_to_chars (p
, val
, size
);
2544 if (i
.types
[n
] & Disp16
)
2548 p
= frag_more (size
);
2549 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2551 reloc (size
, 0, i
.disp_reloc
[n
]));
2557 /* Output immediate. */
2560 register unsigned int n
;
2562 for (n
= 0; n
< i
.operands
; n
++)
2564 if (i
.types
[n
] & Imm
)
2566 if (i
.op
[n
].imms
->X_op
== O_constant
)
2572 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
))
2575 if (i
.types
[n
] & (Imm8
| Imm8S
))
2578 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
2581 p
= frag_more (size
);
2582 md_number_to_chars (p
, val
, size
);
2586 /* Not absolute_section.
2587 Need a 32-bit fixup (don't support 8bit
2588 non-absolute imms). Try to support other
2590 #ifdef BFD_ASSEMBLER
2591 enum bfd_reloc_code_real reloc_type
;
2597 if (i
.types
[n
] & Imm16
)
2599 else if (i
.types
[n
] & (Imm8
| Imm8S
))
2603 p
= frag_more (size
);
2604 reloc_type
= reloc (size
, 0, i
.disp_reloc
[0]);
2605 #ifdef BFD_ASSEMBLER
2606 if (reloc_type
== BFD_RELOC_32
2608 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
2609 && (i
.op
[n
].imms
->X_op
== O_symbol
2610 || (i
.op
[n
].imms
->X_op
== O_add
2611 && ((symbol_get_value_expression
2612 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
2615 reloc_type
= BFD_RELOC_386_GOTPC
;
2616 i
.op
[n
].imms
->X_add_number
+= 3;
2619 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2620 i
.op
[n
].imms
, 0, reloc_type
);
2627 dwarf2_emit_insn (insn_size
);
2634 #endif /* DEBUG386 */
2638 static int i386_immediate
PARAMS ((char *));
2641 i386_immediate (imm_start
)
2644 char *save_input_line_pointer
;
2648 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
2650 as_bad (_("only 1 or 2 immediate operands are allowed"));
2654 exp
= &im_expressions
[i
.imm_operands
++];
2655 i
.op
[this_operand
].imms
= exp
;
2657 if (is_space_char (*imm_start
))
2660 save_input_line_pointer
= input_line_pointer
;
2661 input_line_pointer
= imm_start
;
2665 /* We can have operands of the form
2666 <symbol>@GOTOFF+<nnn>
2667 Take the easy way out here and copy everything
2668 into a temporary buffer... */
2671 cp
= strchr (input_line_pointer
, '@');
2678 /* GOT relocations are not supported in 16 bit mode. */
2679 if (flag_16bit_code
)
2680 as_bad (_("GOT relocations not supported in 16 bit mode"));
2682 if (GOT_symbol
== NULL
)
2683 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
2685 if (strncmp (cp
+ 1, "PLT", 3) == 0)
2687 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
2690 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
2692 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
2695 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
2697 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
2701 as_bad (_("bad reloc specifier in expression"));
2703 /* Replace the relocation token with ' ', so that errors like
2704 foo@GOTOFF1 will be detected. */
2705 first
= cp
- input_line_pointer
;
2706 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
2707 memcpy (tmpbuf
, input_line_pointer
, first
);
2708 tmpbuf
[first
] = ' ';
2709 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
2710 input_line_pointer
= tmpbuf
;
2715 exp_seg
= expression (exp
);
2718 if (*input_line_pointer
)
2719 as_bad (_("ignoring junk `%s' after expression"), input_line_pointer
);
2721 input_line_pointer
= save_input_line_pointer
;
2723 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
2725 /* Missing or bad expr becomes absolute 0. */
2726 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
2728 exp
->X_op
= O_constant
;
2729 exp
->X_add_number
= 0;
2730 exp
->X_add_symbol
= (symbolS
*) 0;
2731 exp
->X_op_symbol
= (symbolS
*) 0;
2734 if (exp
->X_op
== O_constant
)
2736 /* Size it properly later. */
2737 i
.types
[this_operand
] |= Imm32
;
2739 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
2741 #ifdef BFD_ASSEMBLER
2742 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
2744 && exp_seg
!= text_section
2745 && exp_seg
!= data_section
2746 && exp_seg
!= bss_section
2747 && exp_seg
!= undefined_section
2748 #ifdef BFD_ASSEMBLER
2749 && !bfd_is_com_section (exp_seg
)
2753 #ifdef BFD_ASSEMBLER
2754 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
2756 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
2763 /* This is an address. The size of the address will be
2764 determined later, depending on destination register,
2765 suffix, or the default for the section. We exclude
2766 Imm8S here so that `push $foo' and other instructions
2767 with an Imm8S form will use Imm16 or Imm32. */
2768 i
.types
[this_operand
] |= (Imm8
| Imm16
| Imm32
);
2774 static int i386_scale
PARAMS ((char *));
2780 if (!isdigit (*scale
))
2787 i
.log2_scale_factor
= 0;
2790 i
.log2_scale_factor
= 1;
2793 i
.log2_scale_factor
= 2;
2796 i
.log2_scale_factor
= 3;
2800 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
2804 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
2806 as_warn (_("scale factor of %d without an index register"),
2807 1 << i
.log2_scale_factor
);
2808 #if SCALE1_WHEN_NO_INDEX
2809 i
.log2_scale_factor
= 0;
2815 static int i386_displacement
PARAMS ((char *, char *));
2818 i386_displacement (disp_start
, disp_end
)
2822 register expressionS
*exp
;
2824 char *save_input_line_pointer
;
2825 int bigdisp
= Disp32
;
2827 if (flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0))
2829 i
.types
[this_operand
] |= bigdisp
;
2831 exp
= &disp_expressions
[i
.disp_operands
];
2832 i
.op
[this_operand
].disps
= exp
;
2834 save_input_line_pointer
= input_line_pointer
;
2835 input_line_pointer
= disp_start
;
2836 END_STRING_AND_SAVE (disp_end
);
2838 #ifndef GCC_ASM_O_HACK
2839 #define GCC_ASM_O_HACK 0
2842 END_STRING_AND_SAVE (disp_end
+ 1);
2843 if ((i
.types
[this_operand
] & BaseIndex
) != 0
2844 && displacement_string_end
[-1] == '+')
2846 /* This hack is to avoid a warning when using the "o"
2847 constraint within gcc asm statements.
2850 #define _set_tssldt_desc(n,addr,limit,type) \
2851 __asm__ __volatile__ ( \
2853 "movw %w1,2+%0\n\t" \
2855 "movb %b1,4+%0\n\t" \
2856 "movb %4,5+%0\n\t" \
2857 "movb $0,6+%0\n\t" \
2858 "movb %h1,7+%0\n\t" \
2860 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
2862 This works great except that the output assembler ends
2863 up looking a bit weird if it turns out that there is
2864 no offset. You end up producing code that looks like:
2877 So here we provide the missing zero. */
2879 *displacement_string_end
= '0';
2884 /* We can have operands of the form
2885 <symbol>@GOTOFF+<nnn>
2886 Take the easy way out here and copy everything
2887 into a temporary buffer... */
2890 cp
= strchr (input_line_pointer
, '@');
2897 /* GOT relocations are not supported in 16 bit mode. */
2898 if (flag_16bit_code
)
2899 as_bad (_("GOT relocations not supported in 16 bit mode"));
2901 if (GOT_symbol
== NULL
)
2902 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
2904 if (strncmp (cp
+ 1, "PLT", 3) == 0)
2906 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
2909 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
2911 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
2914 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
2916 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
2920 as_bad (_("bad reloc specifier in expression"));
2922 /* Replace the relocation token with ' ', so that errors like
2923 foo@GOTOFF1 will be detected. */
2924 first
= cp
- input_line_pointer
;
2925 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
2926 memcpy (tmpbuf
, input_line_pointer
, first
);
2927 tmpbuf
[first
] = ' ';
2928 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
2929 input_line_pointer
= tmpbuf
;
2934 exp_seg
= expression (exp
);
2936 #ifdef BFD_ASSEMBLER
2937 /* We do this to make sure that the section symbol is in
2938 the symbol table. We will ultimately change the relocation
2939 to be relative to the beginning of the section. */
2940 if (i
.disp_reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
)
2942 if (S_IS_LOCAL(exp
->X_add_symbol
)
2943 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
2944 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
2945 assert (exp
->X_op
== O_symbol
);
2946 exp
->X_op
= O_subtract
;
2947 exp
->X_op_symbol
= GOT_symbol
;
2948 i
.disp_reloc
[this_operand
] = BFD_RELOC_32
;
2953 if (*input_line_pointer
)
2954 as_bad (_("ignoring junk `%s' after expression"),
2955 input_line_pointer
);
2957 RESTORE_END_STRING (disp_end
+ 1);
2959 RESTORE_END_STRING (disp_end
);
2960 input_line_pointer
= save_input_line_pointer
;
2962 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
2964 /* Missing or bad expr becomes absolute 0. */
2965 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2967 exp
->X_op
= O_constant
;
2968 exp
->X_add_number
= 0;
2969 exp
->X_add_symbol
= (symbolS
*) 0;
2970 exp
->X_op_symbol
= (symbolS
*) 0;
2973 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
2974 if (exp
->X_op
!= O_constant
2975 #ifdef BFD_ASSEMBLER
2976 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
2978 && exp_seg
!= text_section
2979 && exp_seg
!= data_section
2980 && exp_seg
!= bss_section
2981 && exp_seg
!= undefined_section
)
2983 #ifdef BFD_ASSEMBLER
2984 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
2986 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
2994 static int i386_index_check
PARAMS((const char *));
2996 /* Make sure the memory operand we've been dealt is valid.
2997 Return 1 on success, 0 on a failure. */
3000 i386_index_check (operand_string
)
3001 const char *operand_string
;
3003 #if INFER_ADDR_PREFIX
3008 if (flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0)
3009 /* 16 bit mode checks. */
3011 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
))
3012 != (Reg16
|BaseIndex
)))
3014 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
3015 != (Reg16
|BaseIndex
))
3017 && i
.base_reg
->reg_num
< 6
3018 && i
.index_reg
->reg_num
>= 6
3019 && i
.log2_scale_factor
== 0))))
3020 /* 32 bit mode checks. */
3022 && (i
.base_reg
->reg_type
& Reg32
) == 0)
3024 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
))
3025 != (Reg32
|BaseIndex
)))))
3027 #if INFER_ADDR_PREFIX
3028 if (i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3030 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3032 /* Change the size of any displacement too. At most one of
3033 Disp16 or Disp32 is set.
3034 FIXME. There doesn't seem to be any real need for separate
3035 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3036 Removing them would probably clean up the code quite a lot. */
3037 if (i
.types
[this_operand
] & (Disp16
|Disp32
))
3038 i
.types
[this_operand
] ^= (Disp16
|Disp32
);
3043 as_bad (_("`%s' is not a valid base/index expression"),
3047 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3049 flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0) ? "16" : "32");
3055 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3059 i386_operand (operand_string
)
3060 char *operand_string
;
3064 char *op_string
= operand_string
;
3066 if (is_space_char (*op_string
))
3069 /* We check for an absolute prefix (differentiating,
3070 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3071 if (*op_string
== ABSOLUTE_PREFIX
)
3074 if (is_space_char (*op_string
))
3076 i
.types
[this_operand
] |= JumpAbsolute
;
3079 /* Check if operand is a register. */
3080 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3081 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3083 /* Check for a segment override by searching for ':' after a
3084 segment register. */
3086 if (is_space_char (*op_string
))
3088 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3093 i
.seg
[i
.mem_operands
] = &es
;
3096 i
.seg
[i
.mem_operands
] = &cs
;
3099 i
.seg
[i
.mem_operands
] = &ss
;
3102 i
.seg
[i
.mem_operands
] = &ds
;
3105 i
.seg
[i
.mem_operands
] = &fs
;
3108 i
.seg
[i
.mem_operands
] = &gs
;
3112 /* Skip the ':' and whitespace. */
3114 if (is_space_char (*op_string
))
3117 if (!is_digit_char (*op_string
)
3118 && !is_identifier_char (*op_string
)
3119 && *op_string
!= '('
3120 && *op_string
!= ABSOLUTE_PREFIX
)
3122 as_bad (_("bad memory operand `%s'"), op_string
);
3125 /* Handle case of %es:*foo. */
3126 if (*op_string
== ABSOLUTE_PREFIX
)
3129 if (is_space_char (*op_string
))
3131 i
.types
[this_operand
] |= JumpAbsolute
;
3133 goto do_memory_reference
;
3137 as_bad (_("junk `%s' after register"), op_string
);
3140 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3141 i
.op
[this_operand
].regs
= r
;
3144 else if (*op_string
== REGISTER_PREFIX
)
3146 as_bad (_("bad register name `%s'"), op_string
);
3149 else if (*op_string
== IMMEDIATE_PREFIX
)
3152 if (i
.types
[this_operand
] & JumpAbsolute
)
3154 as_bad (_("immediate operand illegal with absolute jump"));
3157 if (!i386_immediate (op_string
))
3160 else if (is_digit_char (*op_string
)
3161 || is_identifier_char (*op_string
)
3162 || *op_string
== '(' )
3164 /* This is a memory reference of some sort. */
3167 /* Start and end of displacement string expression (if found). */
3168 char *displacement_string_start
;
3169 char *displacement_string_end
;
3171 do_memory_reference
:
3172 if ((i
.mem_operands
== 1
3173 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3174 || i
.mem_operands
== 2)
3176 as_bad (_("too many memory references for `%s'"),
3177 current_templates
->start
->name
);
3181 /* Check for base index form. We detect the base index form by
3182 looking for an ')' at the end of the operand, searching
3183 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3185 base_string
= op_string
+ strlen (op_string
);
3188 if (is_space_char (*base_string
))
3191 /* If we only have a displacement, set-up for it to be parsed later. */
3192 displacement_string_start
= op_string
;
3193 displacement_string_end
= base_string
+ 1;
3195 if (*base_string
== ')')
3198 unsigned int parens_balanced
= 1;
3199 /* We've already checked that the number of left & right ()'s are
3200 equal, so this loop will not be infinite. */
3204 if (*base_string
== ')')
3206 if (*base_string
== '(')
3209 while (parens_balanced
);
3211 temp_string
= base_string
;
3213 /* Skip past '(' and whitespace. */
3215 if (is_space_char (*base_string
))
3218 if (*base_string
== ','
3219 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3220 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
3222 displacement_string_end
= temp_string
;
3224 i
.types
[this_operand
] |= BaseIndex
;
3228 base_string
= end_op
;
3229 if (is_space_char (*base_string
))
3233 /* There may be an index reg or scale factor here. */
3234 if (*base_string
== ',')
3237 if (is_space_char (*base_string
))
3240 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3241 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
3243 base_string
= end_op
;
3244 if (is_space_char (*base_string
))
3246 if (*base_string
== ',')
3249 if (is_space_char (*base_string
))
3252 else if (*base_string
!= ')' )
3254 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3259 else if (*base_string
== REGISTER_PREFIX
)
3261 as_bad (_("bad register name `%s'"), base_string
);
3265 /* Check for scale factor. */
3266 if (isdigit ((unsigned char) *base_string
))
3268 if (!i386_scale (base_string
))
3272 if (is_space_char (*base_string
))
3274 if (*base_string
!= ')')
3276 as_bad (_("expecting `)' after scale factor in `%s'"),
3281 else if (!i
.index_reg
)
3283 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3288 else if (*base_string
!= ')')
3290 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3295 else if (*base_string
== REGISTER_PREFIX
)
3297 as_bad (_("bad register name `%s'"), base_string
);
3302 /* If there's an expression beginning the operand, parse it,
3303 assuming displacement_string_start and
3304 displacement_string_end are meaningful. */
3305 if (displacement_string_start
!= displacement_string_end
)
3307 if (!i386_displacement (displacement_string_start
,
3308 displacement_string_end
))
3312 /* Special case for (%dx) while doing input/output op. */
3314 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
3316 && i
.log2_scale_factor
== 0
3317 && i
.seg
[i
.mem_operands
] == 0
3318 && (i
.types
[this_operand
] & Disp
) == 0)
3320 i
.types
[this_operand
] = InOutPortReg
;
3324 if (i386_index_check (operand_string
) == 0)
3330 /* It's not a memory operand; argh! */
3331 as_bad (_("invalid char %s beginning operand %d `%s'"),
3332 output_invalid (*op_string
),
3337 return 1; /* Normal return. */
3340 /* md_estimate_size_before_relax()
3342 Called just before relax() for rs_machine_dependent frags. The x86
3343 assembler uses these frags to handle variable size jump
3346 Any symbol that is now undefined will not become defined.
3347 Return the correct fr_subtype in the frag.
3348 Return the initial "guess for variable size of frag" to caller.
3349 The guess is actually the growth beyond the fixed part. Whatever
3350 we do to grow the fixed or variable part contributes to our
3354 md_estimate_size_before_relax (fragP
, segment
)
3355 register fragS
*fragP
;
3356 register segT segment
;
3358 /* We've already got fragP->fr_subtype right; all we have to do is
3359 check for un-relaxable symbols. On an ELF system, we can't relax
3360 an externally visible symbol, because it may be overridden by a
3362 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3363 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3364 || S_IS_EXTERNAL (fragP
->fr_symbol
)
3365 || S_IS_WEAK (fragP
->fr_symbol
)
3369 /* Symbol is undefined in this segment, or we need to keep a
3370 reloc so that weak symbols can be overridden. */
3371 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
3372 #ifdef BFD_ASSEMBLER
3373 enum bfd_reloc_code_real reloc_type
;
3377 unsigned char *opcode
;
3380 if (fragP
->fr_var
!= NO_RELOC
)
3381 reloc_type
= fragP
->fr_var
;
3383 reloc_type
= BFD_RELOC_16_PCREL
;
3385 reloc_type
= BFD_RELOC_32_PCREL
;
3387 old_fr_fix
= fragP
->fr_fix
;
3388 opcode
= (unsigned char *) fragP
->fr_opcode
;
3392 case JUMP_PC_RELATIVE
:
3393 /* Make jmp (0xeb) a dword displacement jump. */
3395 fragP
->fr_fix
+= size
;
3396 fix_new (fragP
, old_fr_fix
, size
,
3398 fragP
->fr_offset
, 1,
3403 /* This changes the byte-displacement jump 0x7N
3404 to the dword-displacement jump 0x0f,0x8N. */
3405 opcode
[1] = opcode
[0] + 0x10;
3406 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3407 /* We've added an opcode byte. */
3408 fragP
->fr_fix
+= 1 + size
;
3409 fix_new (fragP
, old_fr_fix
+ 1, size
,
3411 fragP
->fr_offset
, 1,
3416 return fragP
->fr_fix
- old_fr_fix
;
3418 /* Guess a short jump. */
3422 /* Called after relax() is finished.
3424 In: Address of frag.
3425 fr_type == rs_machine_dependent.
3426 fr_subtype is what the address relaxed to.
3428 Out: Any fixSs and constants are set up.
3429 Caller will turn frag into a ".space 0". */
3431 #ifndef BFD_ASSEMBLER
3433 md_convert_frag (headers
, sec
, fragP
)
3434 object_headers
*headers ATTRIBUTE_UNUSED
;
3435 segT sec ATTRIBUTE_UNUSED
;
3436 register fragS
*fragP
;
3439 md_convert_frag (abfd
, sec
, fragP
)
3440 bfd
*abfd ATTRIBUTE_UNUSED
;
3441 segT sec ATTRIBUTE_UNUSED
;
3442 register fragS
*fragP
;
3445 register unsigned char *opcode
;
3446 unsigned char *where_to_put_displacement
= NULL
;
3447 offsetT target_address
;
3448 offsetT opcode_address
;
3449 unsigned int extension
= 0;
3450 offsetT displacement_from_opcode_start
;
3452 opcode
= (unsigned char *) fragP
->fr_opcode
;
3454 /* Address we want to reach in file space. */
3455 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
3456 #ifdef BFD_ASSEMBLER
3457 /* Not needed otherwise? */
3458 target_address
+= symbol_get_frag (fragP
->fr_symbol
)->fr_address
;
3461 /* Address opcode resides at in file space. */
3462 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
3464 /* Displacement from opcode start to fill into instruction. */
3465 displacement_from_opcode_start
= target_address
- opcode_address
;
3467 switch (fragP
->fr_subtype
)
3469 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL
):
3470 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL16
):
3471 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
):
3472 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL16
):
3473 /* Don't have to change opcode. */
3474 extension
= 1; /* 1 opcode + 1 displacement */
3475 where_to_put_displacement
= &opcode
[1];
3478 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
3479 extension
= 5; /* 2 opcode + 4 displacement */
3480 opcode
[1] = opcode
[0] + 0x10;
3481 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3482 where_to_put_displacement
= &opcode
[2];
3485 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
3486 extension
= 4; /* 1 opcode + 4 displacement */
3488 where_to_put_displacement
= &opcode
[1];
3491 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
3492 extension
= 3; /* 2 opcode + 2 displacement */
3493 opcode
[1] = opcode
[0] + 0x10;
3494 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3495 where_to_put_displacement
= &opcode
[2];
3498 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
3499 extension
= 2; /* 1 opcode + 2 displacement */
3501 where_to_put_displacement
= &opcode
[1];
3505 BAD_CASE (fragP
->fr_subtype
);
3508 /* Now put displacement after opcode. */
3509 md_number_to_chars ((char *) where_to_put_displacement
,
3510 (valueT
) (displacement_from_opcode_start
- extension
),
3511 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
3512 fragP
->fr_fix
+= extension
;
3515 /* Size of byte displacement jmp. */
3516 int md_short_jump_size
= 2;
3518 /* Size of dword displacement jmp. */
3519 int md_long_jump_size
= 5;
3521 /* Size of relocation record. */
3522 const int md_reloc_size
= 8;
3525 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
3527 addressT from_addr
, to_addr
;
3528 fragS
*frag ATTRIBUTE_UNUSED
;
3529 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
3533 offset
= to_addr
- (from_addr
+ 2);
3534 /* Opcode for byte-disp jump. */
3535 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
3536 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
3540 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
3542 addressT from_addr
, to_addr
;
3543 fragS
*frag ATTRIBUTE_UNUSED
;
3544 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
3548 offset
= to_addr
- (from_addr
+ 5);
3549 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
3550 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
3553 /* Apply a fixup (fixS) to segment data, once it has been determined
3554 by our caller that we have all the info we need to fix it up.
3556 On the 386, immediates, displacements, and data pointers are all in
3557 the same (little-endian) format, so we don't need to care about which
3561 md_apply_fix3 (fixP
, valp
, seg
)
3562 /* The fix we're to put in. */
3565 /* Pointer to the value of the bits. */
3568 /* Segment fix is from. */
3569 segT seg ATTRIBUTE_UNUSED
;
3571 register char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3572 valueT value
= *valp
;
3574 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
3577 switch (fixP
->fx_r_type
)
3583 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
3586 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
3589 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
3594 /* This is a hack. There should be a better way to handle this.
3595 This covers for the fact that bfd_install_relocation will
3596 subtract the current location (for partial_inplace, PC relative
3597 relocations); see more below. */
3598 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
3599 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
3600 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
3604 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
3606 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
3609 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3611 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3612 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
3614 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
3617 || (symbol_section_p (fixP
->fx_addsy
)
3618 && fseg
!= absolute_section
))
3619 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
3620 && ! S_IS_WEAK (fixP
->fx_addsy
)
3621 && S_IS_DEFINED (fixP
->fx_addsy
)
3622 && ! S_IS_COMMON (fixP
->fx_addsy
))
3624 /* Yes, we add the values in twice. This is because
3625 bfd_perform_relocation subtracts them out again. I think
3626 bfd_perform_relocation is broken, but I don't dare change
3628 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3632 #if defined (OBJ_COFF) && defined (TE_PE)
3633 /* For some reason, the PE format does not store a section
3634 address offset for a PC relative symbol. */
3635 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
3636 value
+= md_pcrel_from (fixP
);
3640 /* Fix a few things - the dynamic linker expects certain values here,
3641 and we must not dissappoint it. */
3642 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3643 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
3645 switch (fixP
->fx_r_type
)
3647 case BFD_RELOC_386_PLT32
:
3648 /* Make the jump instruction point to the address of the operand. At
3649 runtime we merely add the offset to the actual PLT entry. */
3652 case BFD_RELOC_386_GOTPC
:
3654 /* This is tough to explain. We end up with this one if we have
3655 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
3656 * here is to obtain the absolute address of the GOT, and it is strongly
3657 * preferable from a performance point of view to avoid using a runtime
3658 * relocation for this. The actual sequence of instructions often look
3664 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3666 * The call and pop essentially return the absolute address of
3667 * the label .L66 and store it in %ebx. The linker itself will
3668 * ultimately change the first operand of the addl so that %ebx points to
3669 * the GOT, but to keep things simple, the .o file must have this operand
3670 * set so that it generates not the absolute address of .L66, but the
3671 * absolute address of itself. This allows the linker itself simply
3672 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
3673 * added in, and the addend of the relocation is stored in the operand
3674 * field for the instruction itself.
3676 * Our job here is to fix the operand so that it would add the correct
3677 * offset so that %ebx would point to itself. The thing that is tricky is
3678 * that .-.L66 will point to the beginning of the instruction, so we need
3679 * to further modify the operand so that it will point to itself.
3680 * There are other cases where you have something like:
3682 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3684 * and here no correction would be required. Internally in the assembler
3685 * we treat operands of this form as not being pcrel since the '.' is
3686 * explicitly mentioned, and I wonder whether it would simplify matters
3687 * to do it this way. Who knows. In earlier versions of the PIC patches,
3688 * the pcrel_adjust field was used to store the correction, but since the
3689 * expression is not pcrel, I felt it would be confusing to do it this
3694 case BFD_RELOC_386_GOT32
:
3695 value
= 0; /* Fully resolved at runtime. No addend. */
3697 case BFD_RELOC_386_GOTOFF
:
3700 case BFD_RELOC_VTABLE_INHERIT
:
3701 case BFD_RELOC_VTABLE_ENTRY
:
3708 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
3710 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
3711 md_number_to_chars (p
, value
, fixP
->fx_size
);
3716 #define MAX_LITTLENUMS 6
3718 /* Turn the string pointed to by litP into a floating point constant
3719 of type TYPE, and emit the appropriate bytes. The number of
3720 LITTLENUMS emitted is stored in *SIZEP. An error message is
3721 returned, or NULL on OK. */
3724 md_atof (type
, litP
, sizeP
)
3730 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
3731 LITTLENUM_TYPE
*wordP
;
3753 return _("Bad call to md_atof ()");
3755 t
= atof_ieee (input_line_pointer
, type
, words
);
3757 input_line_pointer
= t
;
3759 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
3760 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
3761 the bigendian 386. */
3762 for (wordP
= words
+ prec
- 1; prec
--;)
3764 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
3765 litP
+= sizeof (LITTLENUM_TYPE
);
3770 char output_invalid_buf
[8];
3777 sprintf (output_invalid_buf
, "'%c'", c
);
3779 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
3780 return output_invalid_buf
;
3783 /* REG_STRING starts *before* REGISTER_PREFIX. */
3785 static const reg_entry
*
3786 parse_register (reg_string
, end_op
)
3790 char *s
= reg_string
;
3792 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
3795 /* Skip possible REGISTER_PREFIX and possible whitespace. */
3796 if (*s
== REGISTER_PREFIX
)
3799 if (is_space_char (*s
))
3803 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
3805 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
3806 return (const reg_entry
*) NULL
;
3810 /* For naked regs, make sure that we are not dealing with an identifier.
3811 This prevents confusing an identifier like `eax_var' with register
3813 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
3814 return (const reg_entry
*) NULL
;
3818 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
3820 /* Handle floating point regs, allowing spaces in the (i) part. */
3821 if (r
== i386_regtab
/* %st is first entry of table */)
3823 if (is_space_char (*s
))
3828 if (is_space_char (*s
))
3830 if (*s
>= '0' && *s
<= '7')
3832 r
= &i386_float_regtab
[*s
- '0'];
3834 if (is_space_char (*s
))
3842 /* We have "%st(" then garbage. */
3843 return (const reg_entry
*) NULL
;
3850 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3851 const char *md_shortopts
= "kVQ:sq";
3853 const char *md_shortopts
= "q";
3855 struct option md_longopts
[] = {
3856 {NULL
, no_argument
, NULL
, 0}
3858 size_t md_longopts_size
= sizeof (md_longopts
);
3861 md_parse_option (c
, arg
)
3863 char *arg ATTRIBUTE_UNUSED
;
3871 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3872 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
3873 should be emitted or not. FIXME: Not implemented. */
3877 /* -V: SVR4 argument to print version ID. */
3879 print_version_id ();
3882 /* -k: Ignore for FreeBSD compatibility. */
3887 /* -s: On i386 Solaris, this tells the native assembler to use
3888 .stab instead of .stab.excl. We always use .stab anyhow. */
3899 md_show_usage (stream
)
3902 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3903 fprintf (stream
, _("\
3905 -V print assembler version number\n\
3907 -q quieten some warnings\n\
3910 fprintf (stream
, _("\
3911 -q quieten some warnings\n"));
3915 #ifdef BFD_ASSEMBLER
3916 #if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \
3917 || (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \
3918 || (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)))
3920 /* Pick the target format to use. */
3923 i386_target_format ()
3925 switch (OUTPUT_FLAVOR
)
3927 #ifdef OBJ_MAYBE_AOUT
3928 case bfd_target_aout_flavour
:
3929 return AOUT_TARGET_FORMAT
;
3931 #ifdef OBJ_MAYBE_COFF
3932 case bfd_target_coff_flavour
:
3935 #ifdef OBJ_MAYBE_ELF
3936 case bfd_target_elf_flavour
:
3937 return "elf32-i386";
3945 #endif /* OBJ_MAYBE_ more than one */
3946 #endif /* BFD_ASSEMBLER */
3949 md_undefined_symbol (name
)
3952 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
3953 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
3954 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
3955 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
3959 if (symbol_find (name
))
3960 as_bad (_("GOT already in symbol table"));
3961 GOT_symbol
= symbol_new (name
, undefined_section
,
3962 (valueT
) 0, &zero_address_frag
);
3969 /* Round up a section size to the appropriate boundary. */
3972 md_section_align (segment
, size
)
3973 segT segment ATTRIBUTE_UNUSED
;
3976 #ifdef BFD_ASSEMBLER
3977 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3978 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
3980 /* For a.out, force the section size to be aligned. If we don't do
3981 this, BFD will align it for us, but it will not write out the
3982 final bytes of the section. This may be a bug in BFD, but it is
3983 easier to fix it here since that is how the other a.out targets
3987 align
= bfd_get_section_alignment (stdoutput
, segment
);
3988 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
3996 /* On the i386, PC-relative offsets are relative to the start of the
3997 next instruction. That is, the address of the offset, plus its
3998 size, since the offset is always the last part of the insn. */
4001 md_pcrel_from (fixP
)
4004 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4011 int ignore ATTRIBUTE_UNUSED
;
4015 temp
= get_absolute_expression ();
4016 subseg_set (bss_section
, (subsegT
) temp
);
4017 demand_empty_rest_of_line ();
4022 #ifdef BFD_ASSEMBLER
4025 i386_validate_fix (fixp
)
4028 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
4030 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
4036 tc_gen_reloc (section
, fixp
)
4037 asection
*section ATTRIBUTE_UNUSED
;
4041 bfd_reloc_code_real_type code
;
4043 switch (fixp
->fx_r_type
)
4045 case BFD_RELOC_386_PLT32
:
4046 case BFD_RELOC_386_GOT32
:
4047 case BFD_RELOC_386_GOTOFF
:
4048 case BFD_RELOC_386_GOTPC
:
4050 case BFD_RELOC_VTABLE_ENTRY
:
4051 case BFD_RELOC_VTABLE_INHERIT
:
4052 code
= fixp
->fx_r_type
;
4057 switch (fixp
->fx_size
)
4060 as_bad (_("can not do %d byte pc-relative relocation"),
4062 code
= BFD_RELOC_32_PCREL
;
4064 case 1: code
= BFD_RELOC_8_PCREL
; break;
4065 case 2: code
= BFD_RELOC_16_PCREL
; break;
4066 case 4: code
= BFD_RELOC_32_PCREL
; break;
4071 switch (fixp
->fx_size
)
4074 as_bad (_("can not do %d byte relocation"), fixp
->fx_size
);
4075 code
= BFD_RELOC_32
;
4077 case 1: code
= BFD_RELOC_8
; break;
4078 case 2: code
= BFD_RELOC_16
; break;
4079 case 4: code
= BFD_RELOC_32
; break;
4085 if (code
== BFD_RELOC_32
4087 && fixp
->fx_addsy
== GOT_symbol
)
4088 code
= BFD_RELOC_386_GOTPC
;
4090 rel
= (arelent
*) xmalloc (sizeof (arelent
));
4091 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4092 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4094 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4095 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4096 vtable entry to be used in the relocation's section offset. */
4097 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4098 rel
->address
= fixp
->fx_offset
;
4101 rel
->addend
= fixp
->fx_addnumber
;
4105 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4106 if (rel
->howto
== NULL
)
4108 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4109 _("cannot represent relocation type %s"),
4110 bfd_get_reloc_code_name (code
));
4111 /* Set howto to a garbage value so that we can keep going. */
4112 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
4113 assert (rel
->howto
!= NULL
);
4119 #else /* ! BFD_ASSEMBLER */
4121 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4123 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4126 relax_addressT segment_address_in_file
;
4128 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4129 Out: GNU LD relocation length code: 0, 1, or 2. */
4131 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
4134 know (fixP
->fx_addsy
!= NULL
);
4136 md_number_to_chars (where
,
4137 (valueT
) (fixP
->fx_frag
->fr_address
4138 + fixP
->fx_where
- segment_address_in_file
),
4141 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4142 ? S_GET_TYPE (fixP
->fx_addsy
)
4143 : fixP
->fx_addsy
->sy_number
);
4145 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
4146 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4147 where
[4] = r_symbolnum
& 0x0ff;
4148 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
4149 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
4150 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
4153 #endif /* OBJ_AOUT or OBJ_BOUT. */
4155 #if defined (I386COFF)
4158 tc_coff_fix2rtype (fixP
)
4161 if (fixP
->fx_r_type
== R_IMAGEBASE
)
4164 return (fixP
->fx_pcrel
?
4165 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
4166 fixP
->fx_size
== 2 ? R_PCRWORD
:
4168 (fixP
->fx_size
== 1 ? R_RELBYTE
:
4169 fixP
->fx_size
== 2 ? R_RELWORD
:
4174 tc_coff_sizemachdep (frag
)
4178 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
4183 #endif /* I386COFF */
4185 #endif /* ! BFD_ASSEMBLER */
4187 /* Parse operands using Intel syntax. This implements a recursive descent
4188 parser based on the BNF grammar published in Appendix B of the MASM 6.1
4191 FIXME: We do not recognize the full operand grammar defined in the MASM
4192 documentation. In particular, all the structure/union and
4193 high-level macro operands are missing.
4195 Uppercase words are terminals, lower case words are non-terminals.
4196 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
4197 bars '|' denote choices. Most grammar productions are implemented in
4198 functions called 'intel_<production>'.
4200 Initial production is 'expr'.
4206 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
4208 constant digits [[ radixOverride ]]
4210 dataType BYTE | WORD | DWORD | QWORD | XWORD
4243 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
4244 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
4246 hexdigit a | b | c | d | e | f
4247 | A | B | C | D | E | F
4257 register specialRegister
4261 segmentRegister CS | DS | ES | FS | GS | SS
4263 specialRegister CR0 | CR2 | CR3
4264 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
4265 | TR3 | TR4 | TR5 | TR6 | TR7
4267 We simplify the grammar in obvious places (e.g., register parsing is
4268 done by calling parse_register) and eliminate immediate left recursion
4269 to implement a recursive-descent parser.
4309 /* Parsing structure for the intel syntax parser. Used to implement the
4310 semantic actions for the operand grammar. */
4311 struct intel_parser_s
4313 char *op_string
; /* The string being parsed. */
4314 int got_a_float
; /* Whether the operand is a float. */
4315 int op_modifier
; /* Operand modifier. */
4316 int is_mem
; /* 1 if operand is memory reference. */
4317 const reg_entry
*reg
; /* Last register reference found. */
4318 char *disp
; /* Displacement string being built. */
4321 static struct intel_parser_s intel_parser
;
4323 /* Token structure for parsing intel syntax. */
4326 int code
; /* Token code. */
4327 const reg_entry
*reg
; /* Register entry for register tokens. */
4328 char *str
; /* String representation. */
4331 static struct intel_token cur_token
, prev_token
;
4333 /* Token codes for the intel parser. */
4347 /* Prototypes for intel parser functions. */
4348 static int intel_match_token
PARAMS ((int code
));
4349 static void intel_get_token
PARAMS ((void));
4350 static void intel_putback_token
PARAMS ((void));
4351 static int intel_expr
PARAMS ((void));
4352 static int intel_e05
PARAMS ((void));
4353 static int intel_e05_1
PARAMS ((void));
4354 static int intel_e06
PARAMS ((void));
4355 static int intel_e06_1
PARAMS ((void));
4356 static int intel_e09
PARAMS ((void));
4357 static int intel_e09_1
PARAMS ((void));
4358 static int intel_e10
PARAMS ((void));
4359 static int intel_e10_1
PARAMS ((void));
4360 static int intel_e11
PARAMS ((void));
4363 i386_intel_operand (operand_string
, got_a_float
)
4364 char *operand_string
;
4370 /* Initialize token holders. */
4371 cur_token
.code
= prev_token
.code
= T_NIL
;
4372 cur_token
.reg
= prev_token
.reg
= NULL
;
4373 cur_token
.str
= prev_token
.str
= NULL
;
4375 /* Initialize parser structure. */
4376 p
= intel_parser
.op_string
= (char *)malloc (strlen (operand_string
) + 1);
4379 strcpy (intel_parser
.op_string
, operand_string
);
4380 intel_parser
.got_a_float
= got_a_float
;
4381 intel_parser
.op_modifier
= -1;
4382 intel_parser
.is_mem
= 0;
4383 intel_parser
.reg
= NULL
;
4384 intel_parser
.disp
= (char *)malloc (strlen (operand_string
) + 1);
4385 if (intel_parser
.disp
== NULL
)
4387 intel_parser
.disp
[0] = '\0';
4389 /* Read the first token and start the parser. */
4391 ret
= intel_expr ();
4395 /* If we found a memory reference, hand it over to i386_displacement
4396 to fill in the rest of the operand fields. */
4397 if (intel_parser
.is_mem
)
4399 if ((i
.mem_operands
== 1
4400 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4401 || i
.mem_operands
== 2)
4403 as_bad (_("too many memory references for '%s'"),
4404 current_templates
->start
->name
);
4409 char *s
= intel_parser
.disp
;
4412 /* Add the displacement expression. */
4414 ret
= i386_displacement (s
, s
+ strlen (s
))
4415 && i386_index_check (s
);
4419 /* Constant and OFFSET expressions are handled by i386_immediate. */
4420 else if (intel_parser
.op_modifier
== OFFSET_FLAT
4421 || intel_parser
.reg
== NULL
)
4422 ret
= i386_immediate (intel_parser
.disp
);
4426 free (intel_parser
.disp
);
4436 /* expr SHORT e05 */
4437 if (cur_token
.code
== T_SHORT
)
4439 intel_parser
.op_modifier
= SHORT
;
4440 intel_match_token (T_SHORT
);
4442 return (intel_e05 ());
4447 return intel_e05 ();
4457 return (intel_e06 () && intel_e05_1 ());
4463 /* e05' addOp e06 e05' */
4464 if (cur_token
.code
== '+' || cur_token
.code
== '-')
4466 strcat (intel_parser
.disp
, cur_token
.str
);
4467 intel_match_token (cur_token
.code
);
4469 return (intel_e06 () && intel_e05_1 ());
4484 return (intel_e09 () && intel_e06_1 ());
4490 /* e06' mulOp e09 e06' */
4491 if (cur_token
.code
== '*' || cur_token
.code
== '/')
4493 strcat (intel_parser
.disp
, cur_token
.str
);
4494 intel_match_token (cur_token
.code
);
4496 return (intel_e09 () && intel_e06_1 ());
4504 /* e09 OFFSET e10 e09'
4513 /* e09 OFFSET e10 e09' */
4514 if (cur_token
.code
== T_OFFSET
)
4516 intel_parser
.is_mem
= 0;
4517 intel_parser
.op_modifier
= OFFSET_FLAT
;
4518 intel_match_token (T_OFFSET
);
4520 return (intel_e10 () && intel_e09_1 ());
4525 return (intel_e10 () && intel_e09_1 ());
4531 /* e09' PTR e10 e09' */
4532 if (cur_token
.code
== T_PTR
)
4534 if (prev_token
.code
== T_BYTE
)
4535 i
.suffix
= BYTE_MNEM_SUFFIX
;
4537 else if (prev_token
.code
== T_WORD
)
4539 if (intel_parser
.got_a_float
== 2) /* "fi..." */
4540 i
.suffix
= SHORT_MNEM_SUFFIX
;
4542 i
.suffix
= WORD_MNEM_SUFFIX
;
4545 else if (prev_token
.code
== T_DWORD
)
4547 if (intel_parser
.got_a_float
== 1) /* "f..." */
4548 i
.suffix
= SHORT_MNEM_SUFFIX
;
4550 i
.suffix
= LONG_MNEM_SUFFIX
;
4553 else if (prev_token
.code
== T_QWORD
)
4554 i
.suffix
= DWORD_MNEM_SUFFIX
;
4556 else if (prev_token
.code
== T_XWORD
)
4557 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
4561 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
4565 intel_match_token (T_PTR
);
4567 return (intel_e10 () && intel_e09_1 ());
4570 /* e09 : e10 e09' */
4571 else if (cur_token
.code
== ':')
4573 intel_parser
.is_mem
= 1;
4575 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
4590 return (intel_e11 () && intel_e10_1 ());
4596 /* e10' [ expr ] e10' */
4597 if (cur_token
.code
== '[')
4599 intel_match_token ('[');
4600 intel_parser
.is_mem
= 1;
4602 /* Add a '+' to the displacement string if necessary. */
4603 if (*intel_parser
.disp
!= '\0')
4604 strcat (intel_parser
.disp
, "+");
4606 return (intel_expr () && intel_match_token (']') && intel_e10_1 ());
4630 if (cur_token
.code
== '(')
4632 intel_match_token ('(');
4633 strcat (intel_parser
.disp
, "(");
4635 if (intel_expr () && intel_match_token (')'))
4637 strcat (intel_parser
.disp
, ")");
4645 else if (cur_token
.code
== '[')
4647 intel_match_token ('[');
4648 intel_parser
.is_mem
= 1;
4650 /* Operands for jump/call inside brackets denote absolute addresses. */
4651 if (current_templates
->start
->opcode_modifier
& Jump
4652 || current_templates
->start
->opcode_modifier
& JumpDword
4653 || current_templates
->start
->opcode_modifier
& JumpByte
4654 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
4655 i
.types
[this_operand
] |= JumpAbsolute
;
4657 /* Add a '+' to the displacement string if necessary. */
4658 if (*intel_parser
.disp
!= '\0')
4659 strcat (intel_parser
.disp
, "+");
4661 return (intel_expr () && intel_match_token (']'));
4669 else if (cur_token
.code
== T_BYTE
4670 || cur_token
.code
== T_WORD
4671 || cur_token
.code
== T_DWORD
4672 || cur_token
.code
== T_QWORD
4673 || cur_token
.code
== T_XWORD
)
4675 intel_match_token (cur_token
.code
);
4682 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
4684 strcat (intel_parser
.disp
, cur_token
.str
);
4685 intel_match_token (cur_token
.code
);
4686 intel_parser
.is_mem
= 1;
4692 else if (cur_token
.code
== T_REG
)
4694 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
4696 intel_match_token (T_REG
);
4698 /* Check for segment change. */
4699 if (cur_token
.code
== ':')
4701 if (reg
->reg_type
& (SReg2
| SReg3
))
4703 switch (reg
->reg_num
)
4706 i
.seg
[i
.mem_operands
] = &es
;
4709 i
.seg
[i
.mem_operands
] = &cs
;
4712 i
.seg
[i
.mem_operands
] = &ss
;
4715 i
.seg
[i
.mem_operands
] = &ds
;
4718 i
.seg
[i
.mem_operands
] = &fs
;
4721 i
.seg
[i
.mem_operands
] = &gs
;
4727 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
4732 /* Not a segment register. Check for register scaling. */
4733 else if (cur_token
.code
== '*')
4735 if (!intel_parser
.is_mem
)
4737 as_bad (_("Register scaling only allowed in memory operands."));
4741 /* What follows must be a valid scale. */
4742 if (intel_match_token ('*')
4743 && strchr ("01248", *cur_token
.str
))
4746 i
.types
[this_operand
] |= BaseIndex
;
4748 /* Set the scale after setting the register (otherwise,
4749 i386_scale will complain) */
4750 i386_scale (cur_token
.str
);
4751 intel_match_token (T_CONST
);
4755 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4761 /* No scaling. If this is a memory operand, the register is either a
4762 base register (first occurrence) or an index register (second
4764 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
4766 if (i
.base_reg
&& i
.index_reg
)
4768 as_bad (_("Too many register references in memory operand.\n"));
4772 if (i
.base_reg
== NULL
)
4777 i
.types
[this_operand
] |= BaseIndex
;
4780 /* Offset modifier. Add the register to the displacement string to be
4781 parsed as an immediate expression after we're done. */
4782 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
4783 strcat (intel_parser
.disp
, reg
->reg_name
);
4785 /* It's neither base nor index nor offset. */
4788 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
4789 i
.op
[this_operand
].regs
= reg
;
4793 /* Since registers are not part of the displacement string (except
4794 when we're parsing offset operands), we may need to remove any
4795 preceding '+' from the displacement string. */
4796 if (*intel_parser
.disp
!= '\0'
4797 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
4799 char *s
= intel_parser
.disp
;
4800 s
+= strlen (s
) - 1;
4809 else if (cur_token
.code
== T_ID
)
4811 /* Add the identifier to the displacement string. */
4812 strcat (intel_parser
.disp
, cur_token
.str
);
4813 intel_match_token (T_ID
);
4815 /* The identifier represents a memory reference only if it's not
4816 preceded by an offset modifier. */
4817 if (intel_parser
.op_modifier
!= OFFSET_FLAT
4818 && intel_parser
.op_modifier
!= FLAT
)
4819 intel_parser
.is_mem
= 1;
4825 else if (cur_token
.code
== T_CONST
4826 || cur_token
.code
== '-'
4827 || cur_token
.code
== '+')
4831 /* Allow constants that start with `+' or `-'. */
4832 if (cur_token
.code
== '-' || cur_token
.code
== '+')
4834 strcat (intel_parser
.disp
, cur_token
.str
);
4835 intel_match_token (cur_token
.code
);
4836 if (cur_token
.code
!= T_CONST
)
4838 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
4844 save_str
= (char *)malloc (strlen (cur_token
.str
) + 1);
4845 if (save_str
== NULL
)
4847 strcpy (save_str
, cur_token
.str
);
4849 /* Get the next token to check for register scaling. */
4850 intel_match_token (cur_token
.code
);
4852 /* Check if this constant is a scaling factor for an index register. */
4853 if (cur_token
.code
== '*')
4855 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
4857 if (!intel_parser
.is_mem
)
4859 as_bad (_("Register scaling only allowed in memory operands."));
4863 /* The constant is followed by `* reg', so it must be
4865 if (strchr ("01248", *save_str
))
4867 i
.index_reg
= cur_token
.reg
;
4868 i
.types
[this_operand
] |= BaseIndex
;
4870 /* Set the scale after setting the register (otherwise,
4871 i386_scale will complain) */
4872 i386_scale (save_str
);
4873 intel_match_token (T_REG
);
4875 /* Since registers are not part of the displacement
4876 string, we may need to remove any preceding '+' from
4877 the displacement string. */
4878 if (*intel_parser
.disp
!= '\0')
4880 char *s
= intel_parser
.disp
;
4881 s
+= strlen (s
) - 1;
4894 /* The constant was not used for register scaling. Since we have
4895 already consumed the token following `*' we now need to put it
4896 back in the stream. */
4898 intel_putback_token ();
4901 /* Add the constant to the displacement string. */
4902 strcat (intel_parser
.disp
, save_str
);
4908 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
4912 /* Match the given token against cur_token. If they match, read the next
4913 token from the operand string. */
4915 intel_match_token (code
)
4918 if (cur_token
.code
== code
)
4925 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
4930 /* Read a new token from intel_parser.op_string and store it in cur_token. */
4935 const reg_entry
*reg
;
4936 struct intel_token new_token
;
4938 new_token
.code
= T_NIL
;
4939 new_token
.reg
= NULL
;
4940 new_token
.str
= NULL
;
4942 /* Free the memory allocated to the previous token and move
4943 cur_token to prev_token. */
4945 free (prev_token
.str
);
4947 prev_token
= cur_token
;
4949 /* Skip whitespace. */
4950 while (is_space_char (*intel_parser
.op_string
))
4951 intel_parser
.op_string
++;
4953 /* Return an empty token if we find nothing else on the line. */
4954 if (*intel_parser
.op_string
== '\0')
4956 cur_token
= new_token
;
4960 /* The new token cannot be larger than the remainder of the operand
4962 new_token
.str
= (char *)malloc (strlen (intel_parser
.op_string
) + 1);
4963 if (new_token
.str
== NULL
)
4965 new_token
.str
[0] = '\0';
4967 if (strchr ("0123456789", *intel_parser
.op_string
))
4969 char *p
= new_token
.str
;
4970 char *q
= intel_parser
.op_string
;
4971 new_token
.code
= T_CONST
;
4973 /* Allow any kind of identifier char to encompass floating point and
4974 hexadecimal numbers. */
4975 while (is_identifier_char (*q
))
4979 /* Recognize special symbol names [0-9][bf]. */
4980 if (strlen (intel_parser
.op_string
) == 2
4981 && (intel_parser
.op_string
[1] == 'b'
4982 || intel_parser
.op_string
[1] == 'f'))
4983 new_token
.code
= T_ID
;
4986 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
4988 new_token
.code
= *intel_parser
.op_string
;
4989 new_token
.str
[0] = *intel_parser
.op_string
;
4990 new_token
.str
[1] = '\0';
4993 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4994 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
4996 new_token
.code
= T_REG
;
4997 new_token
.reg
= reg
;
4999 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
5001 new_token
.str
[0] = REGISTER_PREFIX
;
5002 new_token
.str
[1] = '\0';
5005 strcat (new_token
.str
, reg
->reg_name
);
5008 else if (is_identifier_char (*intel_parser
.op_string
))
5010 char *p
= new_token
.str
;
5011 char *q
= intel_parser
.op_string
;
5013 /* A '.' or '$' followed by an identifier char is an identifier.
5014 Otherwise, it's operator '.' followed by an expression. */
5015 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
5017 new_token
.code
= *q
;
5018 new_token
.str
[0] = *q
;
5019 new_token
.str
[1] = '\0';
5023 while (is_identifier_char (*q
) || *q
== '@')
5027 if (strcasecmp (new_token
.str
, "BYTE") == 0)
5028 new_token
.code
= T_BYTE
;
5030 else if (strcasecmp (new_token
.str
, "WORD") == 0)
5031 new_token
.code
= T_WORD
;
5033 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
5034 new_token
.code
= T_DWORD
;
5036 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
5037 new_token
.code
= T_QWORD
;
5039 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
5040 new_token
.code
= T_XWORD
;
5042 else if (strcasecmp (new_token
.str
, "PTR") == 0)
5043 new_token
.code
= T_PTR
;
5045 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
5046 new_token
.code
= T_SHORT
;
5048 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
5050 new_token
.code
= T_OFFSET
;
5052 /* ??? This is not mentioned in the MASM grammar but gcc
5053 makes use of it with -mintel-syntax. OFFSET may be
5054 followed by FLAT: */
5055 if (strncasecmp (q
, " FLAT:", 6) == 0)
5056 strcat (new_token
.str
, " FLAT:");
5059 /* ??? This is not mentioned in the MASM grammar. */
5060 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
5061 new_token
.code
= T_OFFSET
;
5064 new_token
.code
= T_ID
;
5069 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
5071 intel_parser
.op_string
+= strlen (new_token
.str
);
5072 cur_token
= new_token
;
5075 /* Put cur_token back into the token stream and make cur_token point to
5078 intel_putback_token ()
5080 intel_parser
.op_string
-= strlen (cur_token
.str
);
5081 free (cur_token
.str
);
5082 cur_token
= prev_token
;
5084 /* Forget prev_token. */
5085 prev_token
.code
= T_NIL
;
5086 prev_token
.reg
= NULL
;
5087 prev_token
.str
= NULL
;