1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2017 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
139 /* Used to turn off indicated flags. */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 i386_cpu_flags flags
; /* cpu feature flags */
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
157 static void pe_directive_secrel (int);
159 static void signed_cons (int);
160 static char *output_invalid (int c
);
161 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
163 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS
*);
168 static int i386_intel_parse_name (const char *, expressionS
*);
169 static const reg_entry
*parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template
*match_template (char);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry
*build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS
*, offsetT
);
188 static void output_disp (fragS
*, offsetT
);
190 static void s_bss (int);
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
196 static const char *default_arch
= DEFAULT_ARCH
;
198 /* This struct describes rounding control and SAE in the instruction. */
212 static struct RC_Operation rc_op
;
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
219 const reg_entry
*mask
;
220 unsigned int zeroing
;
221 /* The operand where this operation is associated. */
225 static struct Mask_Operation mask_op
;
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
229 struct Broadcast_Operation
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
234 /* Index of broadcasted operand. */
238 static struct Broadcast_Operation broadcast_op
;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes
[4];
246 /* Destination or source register specifier. */
247 const reg_entry
*register_specifier
;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry
*regs
;
262 operand_size_mismatch
,
263 operand_type_mismatch
,
264 register_type_mismatch
,
265 number_of_operands_mismatch
,
266 invalid_instruction_suffix
,
269 unsupported_with_intel_mnemonic
,
272 invalid_vsib_address
,
273 invalid_vector_register_set
,
274 unsupported_vector_index_register
,
275 unsupported_broadcast
,
276 broadcast_not_on_src_operand
,
279 mask_not_on_destination
,
282 rc_sae_operand_not_last_imm
,
283 invalid_register_operand
,
289 /* TM holds the template for the insn were currently assembling. */
292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
296 /* OPERANDS gives the number of given operands. */
297 unsigned int operands
;
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
302 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
304 /* TYPES [i] is the type (see above #defines) which tells us how to
305 use OP[i] for the corresponding operand. */
306 i386_operand_type types
[MAX_OPERANDS
];
308 /* Displacement expression, immediate expression, or register for each
310 union i386_op op
[MAX_OPERANDS
];
312 /* Flags for operands. */
313 unsigned int flags
[MAX_OPERANDS
];
314 #define Operand_PCrel 1
316 /* Relocation type for operand */
317 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry
*base_reg
;
322 const reg_entry
*index_reg
;
323 unsigned int log2_scale_factor
;
325 /* SEG gives the seg_entries of this insn. They are zero unless
326 explicit segment overrides are given. */
327 const seg_entry
*seg
[2];
329 /* Copied first memory operand string, for re-checking. */
332 /* PREFIX holds all the given prefix opcodes (usually null).
333 PREFIXES is the number of prefix opcodes. */
334 unsigned int prefixes
;
335 unsigned char prefix
[MAX_PREFIXES
];
337 /* RM and SIB are the modrm byte and the sib byte where the
338 addressing modes of this insn are encoded. */
345 /* Masking attributes. */
346 struct Mask_Operation
*mask
;
348 /* Rounding control and SAE attributes. */
349 struct RC_Operation
*rounding
;
351 /* Broadcasting attributes. */
352 struct Broadcast_Operation
*broadcast
;
354 /* Compressed disp8*N attribute. */
355 unsigned int memshift
;
357 /* Prefer load or store in encoding. */
360 dir_encoding_default
= 0,
365 /* Prefer 8bit or 32bit displacement in encoding. */
368 disp_encoding_default
= 0,
373 /* How to encode vector instructions. */
376 vex_encoding_default
= 0,
383 const char *rep_prefix
;
386 const char *hle_prefix
;
388 /* Have BND prefix. */
389 const char *bnd_prefix
;
392 enum i386_error error
;
395 typedef struct _i386_insn i386_insn
;
397 /* Link RC type with corresponding string, that'll be looked for in
406 static const struct RC_name RC_NamesTable
[] =
408 { rne
, STRING_COMMA_LEN ("rn-sae") },
409 { rd
, STRING_COMMA_LEN ("rd-sae") },
410 { ru
, STRING_COMMA_LEN ("ru-sae") },
411 { rz
, STRING_COMMA_LEN ("rz-sae") },
412 { saeonly
, STRING_COMMA_LEN ("sae") },
415 /* List of chars besides those in app.c:symbol_chars that can start an
416 operand. Used to prevent the scrubber eating vital white-space. */
417 const char extra_symbol_chars
[] = "*%-([{}"
426 #if (defined (TE_I386AIX) \
427 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
428 && !defined (TE_GNU) \
429 && !defined (TE_LINUX) \
430 && !defined (TE_NACL) \
431 && !defined (TE_NETWARE) \
432 && !defined (TE_FreeBSD) \
433 && !defined (TE_DragonFly) \
434 && !defined (TE_NetBSD)))
435 /* This array holds the chars that always start a comment. If the
436 pre-processor is disabled, these aren't very useful. The option
437 --divide will remove '/' from this list. */
438 const char *i386_comment_chars
= "#/";
439 #define SVR4_COMMENT_CHARS 1
440 #define PREFIX_SEPARATOR '\\'
443 const char *i386_comment_chars
= "#";
444 #define PREFIX_SEPARATOR '/'
447 /* This array holds the chars that only start a comment at the beginning of
448 a line. If the line seems to have the form '# 123 filename'
449 .line and .file directives will appear in the pre-processed output.
450 Note that input_file.c hand checks for '#' at the beginning of the
451 first line of the input file. This is because the compiler outputs
452 #NO_APP at the beginning of its output.
453 Also note that comments started like this one will always work if
454 '/' isn't otherwise defined. */
455 const char line_comment_chars
[] = "#/";
457 const char line_separator_chars
[] = ";";
459 /* Chars that can be used to separate mant from exp in floating point
461 const char EXP_CHARS
[] = "eE";
463 /* Chars that mean this number is a floating point constant
466 const char FLT_CHARS
[] = "fFdDxX";
468 /* Tables for lexical analysis. */
469 static char mnemonic_chars
[256];
470 static char register_chars
[256];
471 static char operand_chars
[256];
472 static char identifier_chars
[256];
473 static char digit_chars
[256];
475 /* Lexical macros. */
476 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
477 #define is_operand_char(x) (operand_chars[(unsigned char) x])
478 #define is_register_char(x) (register_chars[(unsigned char) x])
479 #define is_space_char(x) ((x) == ' ')
480 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
481 #define is_digit_char(x) (digit_chars[(unsigned char) x])
483 /* All non-digit non-letter characters that may occur in an operand. */
484 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
486 /* md_assemble() always leaves the strings it's passed unaltered. To
487 effect this we maintain a stack of saved characters that we've smashed
488 with '\0's (indicating end of strings for various sub-fields of the
489 assembler instruction). */
490 static char save_stack
[32];
491 static char *save_stack_p
;
492 #define END_STRING_AND_SAVE(s) \
493 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
494 #define RESTORE_END_STRING(s) \
495 do { *(s) = *--save_stack_p; } while (0)
497 /* The instruction we're assembling. */
500 /* Possible templates for current insn. */
501 static const templates
*current_templates
;
503 /* Per instruction expressionS buffers: max displacements & immediates. */
504 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
505 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
507 /* Current operand we are working on. */
508 static int this_operand
= -1;
510 /* We support four different modes. FLAG_CODE variable is used to distinguish
518 static enum flag_code flag_code
;
519 static unsigned int object_64bit
;
520 static unsigned int disallow_64bit_reloc
;
521 static int use_rela_relocations
= 0;
523 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
524 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
525 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
527 /* The ELF ABI to use. */
535 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
538 #if defined (TE_PE) || defined (TE_PEP)
539 /* Use big object file format. */
540 static int use_big_obj
= 0;
543 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
544 /* 1 if generating code for a shared library. */
545 static int shared
= 0;
548 /* 1 for intel syntax,
550 static int intel_syntax
= 0;
552 /* 1 for Intel64 ISA,
556 /* 1 for intel mnemonic,
557 0 if att mnemonic. */
558 static int intel_mnemonic
= !SYSV386_COMPAT
;
560 /* 1 if support old (<= 2.8.1) versions of gcc. */
561 static int old_gcc
= OLDGCC_COMPAT
;
563 /* 1 if pseudo registers are permitted. */
564 static int allow_pseudo_reg
= 0;
566 /* 1 if register prefix % not required. */
567 static int allow_naked_reg
= 0;
569 /* 1 if the assembler should add BND prefix for all control-transferring
570 instructions supporting it, even if this prefix wasn't specified
572 static int add_bnd_prefix
= 0;
574 /* 1 if pseudo index register, eiz/riz, is allowed . */
575 static int allow_index_reg
= 0;
577 /* 1 if the assembler should ignore LOCK prefix, even if it was
578 specified explicitly. */
579 static int omit_lock_prefix
= 0;
581 /* 1 if the assembler should encode lfence, mfence, and sfence as
582 "lock addl $0, (%{re}sp)". */
583 static int avoid_fence
= 0;
585 /* 1 if the assembler should generate relax relocations. */
587 static int generate_relax_relocations
588 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
590 static enum check_kind
596 sse_check
, operand_check
= check_warning
;
598 /* Register prefix used for error message. */
599 static const char *register_prefix
= "%";
601 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
602 leave, push, and pop instructions so that gcc has the same stack
603 frame as in 32 bit mode. */
604 static char stackop_size
= '\0';
606 /* Non-zero to optimize code alignment. */
607 int optimize_align_code
= 1;
609 /* Non-zero to quieten some warnings. */
610 static int quiet_warnings
= 0;
613 static const char *cpu_arch_name
= NULL
;
614 static char *cpu_sub_arch_name
= NULL
;
616 /* CPU feature flags. */
617 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
619 /* If we have selected a cpu we are generating instructions for. */
620 static int cpu_arch_tune_set
= 0;
622 /* Cpu we are generating instructions for. */
623 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
625 /* CPU feature flags of cpu we are generating instructions for. */
626 static i386_cpu_flags cpu_arch_tune_flags
;
628 /* CPU instruction set architecture used. */
629 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
631 /* CPU feature flags of instruction set architecture used. */
632 i386_cpu_flags cpu_arch_isa_flags
;
634 /* If set, conditional jumps are not automatically promoted to handle
635 larger than a byte offset. */
636 static unsigned int no_cond_jump_promotion
= 0;
638 /* Encode SSE instructions with VEX prefix. */
639 static unsigned int sse2avx
;
641 /* Encode scalar AVX instructions with specific vector length. */
648 /* Encode scalar EVEX LIG instructions with specific vector length. */
656 /* Encode EVEX WIG instructions with specific evex.w. */
663 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
664 static enum rc_type evexrcig
= rne
;
666 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
667 static symbolS
*GOT_symbol
;
669 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
670 unsigned int x86_dwarf2_return_column
;
672 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
673 int x86_cie_data_alignment
;
675 /* Interface to relax_segment.
676 There are 3 major relax states for 386 jump insns because the
677 different types of jumps add different sizes to frags when we're
678 figuring out what sort of jump to choose to reach a given label. */
681 #define UNCOND_JUMP 0
683 #define COND_JUMP86 2
688 #define SMALL16 (SMALL | CODE16)
690 #define BIG16 (BIG | CODE16)
694 #define INLINE __inline__
700 #define ENCODE_RELAX_STATE(type, size) \
701 ((relax_substateT) (((type) << 2) | (size)))
702 #define TYPE_FROM_RELAX_STATE(s) \
704 #define DISP_SIZE_FROM_RELAX_STATE(s) \
705 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
707 /* This table is used by relax_frag to promote short jumps to long
708 ones where necessary. SMALL (short) jumps may be promoted to BIG
709 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
710 don't allow a short jump in a 32 bit code segment to be promoted to
711 a 16 bit offset jump because it's slower (requires data size
712 prefix), and doesn't work, unless the destination is in the bottom
713 64k of the code segment (The top 16 bits of eip are zeroed). */
715 const relax_typeS md_relax_table
[] =
718 1) most positive reach of this state,
719 2) most negative reach of this state,
720 3) how many bytes this mode will have in the variable part of the frag
721 4) which index into the table to try if we can't fit into this one. */
723 /* UNCOND_JUMP states. */
724 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
725 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
726 /* dword jmp adds 4 bytes to frag:
727 0 extra opcode bytes, 4 displacement bytes. */
729 /* word jmp adds 2 byte2 to frag:
730 0 extra opcode bytes, 2 displacement bytes. */
733 /* COND_JUMP states. */
734 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
735 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
736 /* dword conditionals adds 5 bytes to frag:
737 1 extra opcode byte, 4 displacement bytes. */
739 /* word conditionals add 3 bytes to frag:
740 1 extra opcode byte, 2 displacement bytes. */
743 /* COND_JUMP86 states. */
744 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
745 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
746 /* dword conditionals adds 5 bytes to frag:
747 1 extra opcode byte, 4 displacement bytes. */
749 /* word conditionals add 4 bytes to frag:
750 1 displacement byte and a 3 byte long branch insn. */
754 static const arch_entry cpu_arch
[] =
756 /* Do not replace the first two entries - i386_target_format()
757 relies on them being there in this order. */
758 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
759 CPU_GENERIC32_FLAGS
, 0 },
760 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
761 CPU_GENERIC64_FLAGS
, 0 },
762 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
764 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
766 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
768 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
770 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
772 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
774 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
776 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
778 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
779 CPU_PENTIUMPRO_FLAGS
, 0 },
780 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
782 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
784 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
786 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
788 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
789 CPU_NOCONA_FLAGS
, 0 },
790 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
792 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
794 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
795 CPU_CORE2_FLAGS
, 1 },
796 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
797 CPU_CORE2_FLAGS
, 0 },
798 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
799 CPU_COREI7_FLAGS
, 0 },
800 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
802 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
804 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
805 CPU_IAMCU_FLAGS
, 0 },
806 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
808 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
810 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
811 CPU_ATHLON_FLAGS
, 0 },
812 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
814 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
816 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
818 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
819 CPU_AMDFAM10_FLAGS
, 0 },
820 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
821 CPU_BDVER1_FLAGS
, 0 },
822 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
823 CPU_BDVER2_FLAGS
, 0 },
824 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
825 CPU_BDVER3_FLAGS
, 0 },
826 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
827 CPU_BDVER4_FLAGS
, 0 },
828 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
829 CPU_ZNVER1_FLAGS
, 0 },
830 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
831 CPU_BTVER1_FLAGS
, 0 },
832 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
833 CPU_BTVER2_FLAGS
, 0 },
834 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
836 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
838 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
840 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
842 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
844 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
846 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
848 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
850 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
851 CPU_SSSE3_FLAGS
, 0 },
852 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
853 CPU_SSE4_1_FLAGS
, 0 },
854 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
855 CPU_SSE4_2_FLAGS
, 0 },
856 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
857 CPU_SSE4_2_FLAGS
, 0 },
858 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
860 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
862 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
863 CPU_AVX512F_FLAGS
, 0 },
864 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
865 CPU_AVX512CD_FLAGS
, 0 },
866 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
867 CPU_AVX512ER_FLAGS
, 0 },
868 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
869 CPU_AVX512PF_FLAGS
, 0 },
870 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
871 CPU_AVX512DQ_FLAGS
, 0 },
872 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
873 CPU_AVX512BW_FLAGS
, 0 },
874 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
875 CPU_AVX512VL_FLAGS
, 0 },
876 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
878 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
879 CPU_VMFUNC_FLAGS
, 0 },
880 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
882 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
883 CPU_XSAVE_FLAGS
, 0 },
884 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
885 CPU_XSAVEOPT_FLAGS
, 0 },
886 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
887 CPU_XSAVEC_FLAGS
, 0 },
888 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
889 CPU_XSAVES_FLAGS
, 0 },
890 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
892 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
893 CPU_PCLMUL_FLAGS
, 0 },
894 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
895 CPU_PCLMUL_FLAGS
, 1 },
896 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
897 CPU_FSGSBASE_FLAGS
, 0 },
898 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
899 CPU_RDRND_FLAGS
, 0 },
900 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
902 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
904 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
906 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
908 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
910 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
912 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
913 CPU_MOVBE_FLAGS
, 0 },
914 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
916 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
918 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
919 CPU_LZCNT_FLAGS
, 0 },
920 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
922 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
924 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
925 CPU_INVPCID_FLAGS
, 0 },
926 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
927 CPU_CLFLUSH_FLAGS
, 0 },
928 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
930 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
931 CPU_SYSCALL_FLAGS
, 0 },
932 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
933 CPU_RDTSCP_FLAGS
, 0 },
934 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
935 CPU_3DNOW_FLAGS
, 0 },
936 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
937 CPU_3DNOWA_FLAGS
, 0 },
938 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
939 CPU_PADLOCK_FLAGS
, 0 },
940 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
942 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
944 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
945 CPU_SSE4A_FLAGS
, 0 },
946 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
948 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
950 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
952 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
954 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
955 CPU_RDSEED_FLAGS
, 0 },
956 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
957 CPU_PRFCHW_FLAGS
, 0 },
958 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
960 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
962 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
964 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
965 CPU_CLFLUSHOPT_FLAGS
, 0 },
966 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
967 CPU_PREFETCHWT1_FLAGS
, 0 },
968 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
970 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
972 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
973 CPU_AVX512IFMA_FLAGS
, 0 },
974 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
975 CPU_AVX512VBMI_FLAGS
, 0 },
976 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
977 CPU_AVX512_4FMAPS_FLAGS
, 0 },
978 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
979 CPU_AVX512_4VNNIW_FLAGS
, 0 },
980 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
981 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
982 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
983 CPU_CLZERO_FLAGS
, 0 },
984 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
985 CPU_MWAITX_FLAGS
, 0 },
986 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
987 CPU_OSPKE_FLAGS
, 0 },
988 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
989 CPU_RDPID_FLAGS
, 0 },
990 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
991 CPU_PTWRITE_FLAGS
, 0 },
992 { STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN
,
996 static const noarch_entry cpu_noarch
[] =
998 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
999 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1000 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1001 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1002 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1003 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1004 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1005 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1006 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1007 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1008 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1009 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1010 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1011 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1012 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1013 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1014 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1015 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1016 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1017 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1018 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1019 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1020 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1021 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1022 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1023 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1027 /* Like s_lcomm_internal in gas/read.c but the alignment string
1028 is allowed to be optional. */
1031 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1038 && *input_line_pointer
== ',')
1040 align
= parse_align (needs_align
- 1);
1042 if (align
== (addressT
) -1)
1057 bss_alloc (symbolP
, size
, align
);
1062 pe_lcomm (int needs_align
)
1064 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1068 const pseudo_typeS md_pseudo_table
[] =
1070 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1071 {"align", s_align_bytes
, 0},
1073 {"align", s_align_ptwo
, 0},
1075 {"arch", set_cpu_arch
, 0},
1079 {"lcomm", pe_lcomm
, 1},
1081 {"ffloat", float_cons
, 'f'},
1082 {"dfloat", float_cons
, 'd'},
1083 {"tfloat", float_cons
, 'x'},
1085 {"slong", signed_cons
, 4},
1086 {"noopt", s_ignore
, 0},
1087 {"optim", s_ignore
, 0},
1088 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1089 {"code16", set_code_flag
, CODE_16BIT
},
1090 {"code32", set_code_flag
, CODE_32BIT
},
1091 {"code64", set_code_flag
, CODE_64BIT
},
1092 {"intel_syntax", set_intel_syntax
, 1},
1093 {"att_syntax", set_intel_syntax
, 0},
1094 {"intel_mnemonic", set_intel_mnemonic
, 1},
1095 {"att_mnemonic", set_intel_mnemonic
, 0},
1096 {"allow_index_reg", set_allow_index_reg
, 1},
1097 {"disallow_index_reg", set_allow_index_reg
, 0},
1098 {"sse_check", set_check
, 0},
1099 {"operand_check", set_check
, 1},
1100 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1101 {"largecomm", handle_large_common
, 0},
1103 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1104 {"loc", dwarf2_directive_loc
, 0},
1105 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1108 {"secrel32", pe_directive_secrel
, 0},
1113 /* For interface with expression (). */
1114 extern char *input_line_pointer
;
1116 /* Hash table for instruction mnemonic lookup. */
1117 static struct hash_control
*op_hash
;
1119 /* Hash table for register lookup. */
1120 static struct hash_control
*reg_hash
;
1123 i386_align_code (fragS
*fragP
, int count
)
1125 /* Various efficient no-op patterns for aligning code labels.
1126 Note: Don't try to assemble the instructions in the comments.
1127 0L and 0w are not legal. */
1128 static const unsigned char f32_1
[] =
1130 static const unsigned char f32_2
[] =
1131 {0x66,0x90}; /* xchg %ax,%ax */
1132 static const unsigned char f32_3
[] =
1133 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1134 static const unsigned char f32_4
[] =
1135 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1136 static const unsigned char f32_5
[] =
1138 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1139 static const unsigned char f32_6
[] =
1140 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1141 static const unsigned char f32_7
[] =
1142 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1143 static const unsigned char f32_8
[] =
1145 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1146 static const unsigned char f32_9
[] =
1147 {0x89,0xf6, /* movl %esi,%esi */
1148 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1149 static const unsigned char f32_10
[] =
1150 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1151 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1152 static const unsigned char f32_11
[] =
1153 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1154 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1155 static const unsigned char f32_12
[] =
1156 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1157 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1158 static const unsigned char f32_13
[] =
1159 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1160 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1161 static const unsigned char f32_14
[] =
1162 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1163 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1164 static const unsigned char f16_3
[] =
1165 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1166 static const unsigned char f16_4
[] =
1167 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1168 static const unsigned char f16_5
[] =
1170 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1171 static const unsigned char f16_6
[] =
1172 {0x89,0xf6, /* mov %si,%si */
1173 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1174 static const unsigned char f16_7
[] =
1175 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1176 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1177 static const unsigned char f16_8
[] =
1178 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1179 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1180 static const unsigned char jump_31
[] =
1181 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1182 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1183 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1184 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1185 static const unsigned char *const f32_patt
[] = {
1186 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1187 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1189 static const unsigned char *const f16_patt
[] = {
1190 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1192 /* nopl (%[re]ax) */
1193 static const unsigned char alt_3
[] =
1195 /* nopl 0(%[re]ax) */
1196 static const unsigned char alt_4
[] =
1197 {0x0f,0x1f,0x40,0x00};
1198 /* nopl 0(%[re]ax,%[re]ax,1) */
1199 static const unsigned char alt_5
[] =
1200 {0x0f,0x1f,0x44,0x00,0x00};
1201 /* nopw 0(%[re]ax,%[re]ax,1) */
1202 static const unsigned char alt_6
[] =
1203 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1204 /* nopl 0L(%[re]ax) */
1205 static const unsigned char alt_7
[] =
1206 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1207 /* nopl 0L(%[re]ax,%[re]ax,1) */
1208 static const unsigned char alt_8
[] =
1209 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1210 /* nopw 0L(%[re]ax,%[re]ax,1) */
1211 static const unsigned char alt_9
[] =
1212 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1213 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1214 static const unsigned char alt_10
[] =
1215 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1216 static const unsigned char *const alt_patt
[] = {
1217 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1221 /* Only align for at least a positive non-zero boundary. */
1222 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1225 /* We need to decide which NOP sequence to use for 32bit and
1226 64bit. When -mtune= is used:
1228 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1229 PROCESSOR_GENERIC32, f32_patt will be used.
1230 2. For the rest, alt_patt will be used.
1232 When -mtune= isn't used, alt_patt will be used if
1233 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1236 When -march= or .arch is used, we can't use anything beyond
1237 cpu_arch_isa_flags. */
1239 if (flag_code
== CODE_16BIT
)
1243 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1245 /* Adjust jump offset. */
1246 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1249 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1250 f16_patt
[count
- 1], count
);
1254 const unsigned char *const *patt
= NULL
;
1256 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1258 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1259 switch (cpu_arch_tune
)
1261 case PROCESSOR_UNKNOWN
:
1262 /* We use cpu_arch_isa_flags to check if we SHOULD
1263 optimize with nops. */
1264 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1269 case PROCESSOR_PENTIUM4
:
1270 case PROCESSOR_NOCONA
:
1271 case PROCESSOR_CORE
:
1272 case PROCESSOR_CORE2
:
1273 case PROCESSOR_COREI7
:
1274 case PROCESSOR_L1OM
:
1275 case PROCESSOR_K1OM
:
1276 case PROCESSOR_GENERIC64
:
1278 case PROCESSOR_ATHLON
:
1280 case PROCESSOR_AMDFAM10
:
1282 case PROCESSOR_ZNVER
:
1286 case PROCESSOR_I386
:
1287 case PROCESSOR_I486
:
1288 case PROCESSOR_PENTIUM
:
1289 case PROCESSOR_PENTIUMPRO
:
1290 case PROCESSOR_IAMCU
:
1291 case PROCESSOR_GENERIC32
:
1298 switch (fragP
->tc_frag_data
.tune
)
1300 case PROCESSOR_UNKNOWN
:
1301 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1302 PROCESSOR_UNKNOWN. */
1306 case PROCESSOR_I386
:
1307 case PROCESSOR_I486
:
1308 case PROCESSOR_PENTIUM
:
1309 case PROCESSOR_IAMCU
:
1311 case PROCESSOR_ATHLON
:
1313 case PROCESSOR_AMDFAM10
:
1315 case PROCESSOR_ZNVER
:
1317 case PROCESSOR_GENERIC32
:
1318 /* We use cpu_arch_isa_flags to check if we CAN optimize
1320 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1325 case PROCESSOR_PENTIUMPRO
:
1326 case PROCESSOR_PENTIUM4
:
1327 case PROCESSOR_NOCONA
:
1328 case PROCESSOR_CORE
:
1329 case PROCESSOR_CORE2
:
1330 case PROCESSOR_COREI7
:
1331 case PROCESSOR_L1OM
:
1332 case PROCESSOR_K1OM
:
1333 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1338 case PROCESSOR_GENERIC64
:
1344 if (patt
== f32_patt
)
1346 /* If the padding is less than 15 bytes, we use the normal
1347 ones. Otherwise, we use a jump instruction and adjust
1351 /* For 64bit, the limit is 3 bytes. */
1352 if (flag_code
== CODE_64BIT
1353 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1358 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1359 patt
[count
- 1], count
);
1362 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1364 /* Adjust jump offset. */
1365 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1370 /* Maximum length of an instruction is 10 byte. If the
1371 padding is greater than 10 bytes and we don't use jump,
1372 we have to break it into smaller pieces. */
1373 int padding
= count
;
1374 while (padding
> 10)
1377 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1382 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1383 patt
[padding
- 1], padding
);
1386 fragP
->fr_var
= count
;
1390 operand_type_all_zero (const union i386_operand_type
*x
)
1392 switch (ARRAY_SIZE(x
->array
))
1403 return !x
->array
[0];
1410 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1412 switch (ARRAY_SIZE(x
->array
))
1430 operand_type_equal (const union i386_operand_type
*x
,
1431 const union i386_operand_type
*y
)
1433 switch (ARRAY_SIZE(x
->array
))
1436 if (x
->array
[2] != y
->array
[2])
1440 if (x
->array
[1] != y
->array
[1])
1444 return x
->array
[0] == y
->array
[0];
1452 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1454 switch (ARRAY_SIZE(x
->array
))
1465 return !x
->array
[0];
1472 cpu_flags_equal (const union i386_cpu_flags
*x
,
1473 const union i386_cpu_flags
*y
)
1475 switch (ARRAY_SIZE(x
->array
))
1478 if (x
->array
[2] != y
->array
[2])
1482 if (x
->array
[1] != y
->array
[1])
1486 return x
->array
[0] == y
->array
[0];
1494 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1496 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1497 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1500 static INLINE i386_cpu_flags
1501 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1503 switch (ARRAY_SIZE (x
.array
))
1506 x
.array
[2] &= y
.array
[2];
1509 x
.array
[1] &= y
.array
[1];
1512 x
.array
[0] &= y
.array
[0];
1520 static INLINE i386_cpu_flags
1521 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1523 switch (ARRAY_SIZE (x
.array
))
1526 x
.array
[2] |= y
.array
[2];
1529 x
.array
[1] |= y
.array
[1];
1532 x
.array
[0] |= y
.array
[0];
1540 static INLINE i386_cpu_flags
1541 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1543 switch (ARRAY_SIZE (x
.array
))
1546 x
.array
[2] &= ~y
.array
[2];
1549 x
.array
[1] &= ~y
.array
[1];
1552 x
.array
[0] &= ~y
.array
[0];
1560 #define CPU_FLAGS_ARCH_MATCH 0x1
1561 #define CPU_FLAGS_64BIT_MATCH 0x2
1562 #define CPU_FLAGS_AES_MATCH 0x4
1563 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1564 #define CPU_FLAGS_AVX_MATCH 0x10
1566 #define CPU_FLAGS_32BIT_MATCH \
1567 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1568 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1569 #define CPU_FLAGS_PERFECT_MATCH \
1570 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1572 /* Return CPU flags match bits. */
1575 cpu_flags_match (const insn_template
*t
)
1577 i386_cpu_flags x
= t
->cpu_flags
;
1578 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1580 x
.bitfield
.cpu64
= 0;
1581 x
.bitfield
.cpuno64
= 0;
1583 if (cpu_flags_all_zero (&x
))
1585 /* This instruction is available on all archs. */
1586 match
|= CPU_FLAGS_32BIT_MATCH
;
1590 /* This instruction is available only on some archs. */
1591 i386_cpu_flags cpu
= cpu_arch_flags
;
1593 cpu
= cpu_flags_and (x
, cpu
);
1594 if (!cpu_flags_all_zero (&cpu
))
1596 if (x
.bitfield
.cpuavx
)
1598 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1599 if (cpu
.bitfield
.cpuavx
)
1601 /* Check SSE2AVX. */
1602 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1604 match
|= (CPU_FLAGS_ARCH_MATCH
1605 | CPU_FLAGS_AVX_MATCH
);
1607 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1608 match
|= CPU_FLAGS_AES_MATCH
;
1610 if (!x
.bitfield
.cpupclmul
1611 || cpu
.bitfield
.cpupclmul
)
1612 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1616 match
|= CPU_FLAGS_ARCH_MATCH
;
1618 else if (x
.bitfield
.cpuavx512vl
)
1620 /* Match AVX512VL. */
1621 if (cpu
.bitfield
.cpuavx512vl
)
1623 /* Need another match. */
1624 cpu
.bitfield
.cpuavx512vl
= 0;
1625 if (!cpu_flags_all_zero (&cpu
))
1626 match
|= CPU_FLAGS_32BIT_MATCH
;
1628 match
|= CPU_FLAGS_ARCH_MATCH
;
1631 match
|= CPU_FLAGS_ARCH_MATCH
;
1634 match
|= CPU_FLAGS_32BIT_MATCH
;
1640 static INLINE i386_operand_type
1641 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1643 switch (ARRAY_SIZE (x
.array
))
1646 x
.array
[2] &= y
.array
[2];
1649 x
.array
[1] &= y
.array
[1];
1652 x
.array
[0] &= y
.array
[0];
1660 static INLINE i386_operand_type
1661 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1663 switch (ARRAY_SIZE (x
.array
))
1666 x
.array
[2] |= y
.array
[2];
1669 x
.array
[1] |= y
.array
[1];
1672 x
.array
[0] |= y
.array
[0];
1680 static INLINE i386_operand_type
1681 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1683 switch (ARRAY_SIZE (x
.array
))
1686 x
.array
[2] ^= y
.array
[2];
1689 x
.array
[1] ^= y
.array
[1];
1692 x
.array
[0] ^= y
.array
[0];
1700 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1701 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1702 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1703 static const i386_operand_type inoutportreg
1704 = OPERAND_TYPE_INOUTPORTREG
;
1705 static const i386_operand_type reg16_inoutportreg
1706 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1707 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1708 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1709 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1710 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1711 static const i386_operand_type anydisp
1712 = OPERAND_TYPE_ANYDISP
;
1713 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1714 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1715 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1716 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1717 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1718 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1719 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1720 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1721 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1722 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1723 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1724 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1725 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1726 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1737 operand_type_check (i386_operand_type t
, enum operand_type c
)
1742 return (t
.bitfield
.reg8
1745 || t
.bitfield
.reg64
);
1748 return (t
.bitfield
.imm8
1752 || t
.bitfield
.imm32s
1753 || t
.bitfield
.imm64
);
1756 return (t
.bitfield
.disp8
1757 || t
.bitfield
.disp16
1758 || t
.bitfield
.disp32
1759 || t
.bitfield
.disp32s
1760 || t
.bitfield
.disp64
);
1763 return (t
.bitfield
.disp8
1764 || t
.bitfield
.disp16
1765 || t
.bitfield
.disp32
1766 || t
.bitfield
.disp32s
1767 || t
.bitfield
.disp64
1768 || t
.bitfield
.baseindex
);
1777 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1778 operand J for instruction template T. */
1781 match_reg_size (const insn_template
*t
, unsigned int j
)
1783 return !((i
.types
[j
].bitfield
.byte
1784 && !t
->operand_types
[j
].bitfield
.byte
)
1785 || (i
.types
[j
].bitfield
.word
1786 && !t
->operand_types
[j
].bitfield
.word
)
1787 || (i
.types
[j
].bitfield
.dword
1788 && !t
->operand_types
[j
].bitfield
.dword
)
1789 || (i
.types
[j
].bitfield
.qword
1790 && !t
->operand_types
[j
].bitfield
.qword
));
1793 /* Return 1 if there is no conflict in any size on operand J for
1794 instruction template T. */
1797 match_mem_size (const insn_template
*t
, unsigned int j
)
1799 return (match_reg_size (t
, j
)
1800 && !((i
.types
[j
].bitfield
.unspecified
1802 && !t
->operand_types
[j
].bitfield
.unspecified
)
1803 || (i
.types
[j
].bitfield
.fword
1804 && !t
->operand_types
[j
].bitfield
.fword
)
1805 || (i
.types
[j
].bitfield
.tbyte
1806 && !t
->operand_types
[j
].bitfield
.tbyte
)
1807 || (i
.types
[j
].bitfield
.xmmword
1808 && !t
->operand_types
[j
].bitfield
.xmmword
)
1809 || (i
.types
[j
].bitfield
.ymmword
1810 && !t
->operand_types
[j
].bitfield
.ymmword
)
1811 || (i
.types
[j
].bitfield
.zmmword
1812 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1815 /* Return 1 if there is no size conflict on any operands for
1816 instruction template T. */
1819 operand_size_match (const insn_template
*t
)
1824 /* Don't check jump instructions. */
1825 if (t
->opcode_modifier
.jump
1826 || t
->opcode_modifier
.jumpbyte
1827 || t
->opcode_modifier
.jumpdword
1828 || t
->opcode_modifier
.jumpintersegment
)
1831 /* Check memory and accumulator operand size. */
1832 for (j
= 0; j
< i
.operands
; j
++)
1834 if (t
->operand_types
[j
].bitfield
.anysize
)
1837 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1843 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1852 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1855 i
.error
= operand_size_mismatch
;
1859 /* Check reverse. */
1860 gas_assert (i
.operands
== 2);
1863 for (j
= 0; j
< 2; j
++)
1865 if (t
->operand_types
[j
].bitfield
.acc
1866 && !match_reg_size (t
, j
? 0 : 1))
1869 if (i
.types
[j
].bitfield
.mem
1870 && !match_mem_size (t
, j
? 0 : 1))
1878 operand_type_match (i386_operand_type overlap
,
1879 i386_operand_type given
)
1881 i386_operand_type temp
= overlap
;
1883 temp
.bitfield
.jumpabsolute
= 0;
1884 temp
.bitfield
.unspecified
= 0;
1885 temp
.bitfield
.byte
= 0;
1886 temp
.bitfield
.word
= 0;
1887 temp
.bitfield
.dword
= 0;
1888 temp
.bitfield
.fword
= 0;
1889 temp
.bitfield
.qword
= 0;
1890 temp
.bitfield
.tbyte
= 0;
1891 temp
.bitfield
.xmmword
= 0;
1892 temp
.bitfield
.ymmword
= 0;
1893 temp
.bitfield
.zmmword
= 0;
1894 if (operand_type_all_zero (&temp
))
1897 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1898 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1902 i
.error
= operand_type_mismatch
;
1906 /* If given types g0 and g1 are registers they must be of the same type
1907 unless the expected operand type register overlap is null.
1908 Note that Acc in a template matches every size of reg. */
1911 operand_type_register_match (i386_operand_type m0
,
1912 i386_operand_type g0
,
1913 i386_operand_type t0
,
1914 i386_operand_type m1
,
1915 i386_operand_type g1
,
1916 i386_operand_type t1
)
1918 if (!operand_type_check (g0
, reg
))
1921 if (!operand_type_check (g1
, reg
))
1924 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1925 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1926 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1927 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1930 if (m0
.bitfield
.acc
)
1932 t0
.bitfield
.reg8
= 1;
1933 t0
.bitfield
.reg16
= 1;
1934 t0
.bitfield
.reg32
= 1;
1935 t0
.bitfield
.reg64
= 1;
1938 if (m1
.bitfield
.acc
)
1940 t1
.bitfield
.reg8
= 1;
1941 t1
.bitfield
.reg16
= 1;
1942 t1
.bitfield
.reg32
= 1;
1943 t1
.bitfield
.reg64
= 1;
1946 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1947 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1948 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1949 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1952 i
.error
= register_type_mismatch
;
1957 static INLINE
unsigned int
1958 register_number (const reg_entry
*r
)
1960 unsigned int nr
= r
->reg_num
;
1962 if (r
->reg_flags
& RegRex
)
1965 if (r
->reg_flags
& RegVRex
)
1971 static INLINE
unsigned int
1972 mode_from_disp_size (i386_operand_type t
)
1974 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1976 else if (t
.bitfield
.disp16
1977 || t
.bitfield
.disp32
1978 || t
.bitfield
.disp32s
)
1985 fits_in_signed_byte (addressT num
)
1987 return num
+ 0x80 <= 0xff;
1991 fits_in_unsigned_byte (addressT num
)
1997 fits_in_unsigned_word (addressT num
)
1999 return num
<= 0xffff;
2003 fits_in_signed_word (addressT num
)
2005 return num
+ 0x8000 <= 0xffff;
2009 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2014 return num
+ 0x80000000 <= 0xffffffff;
2016 } /* fits_in_signed_long() */
2019 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2024 return num
<= 0xffffffff;
2026 } /* fits_in_unsigned_long() */
2029 fits_in_vec_disp8 (offsetT num
)
2031 int shift
= i
.memshift
;
2037 mask
= (1 << shift
) - 1;
2039 /* Return 0 if NUM isn't properly aligned. */
2043 /* Check if NUM will fit in 8bit after shift. */
2044 return fits_in_signed_byte (num
>> shift
);
2048 fits_in_imm4 (offsetT num
)
2050 return (num
& 0xf) == num
;
2053 static i386_operand_type
2054 smallest_imm_type (offsetT num
)
2056 i386_operand_type t
;
2058 operand_type_set (&t
, 0);
2059 t
.bitfield
.imm64
= 1;
2061 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2063 /* This code is disabled on the 486 because all the Imm1 forms
2064 in the opcode table are slower on the i486. They're the
2065 versions with the implicitly specified single-position
2066 displacement, which has another syntax if you really want to
2068 t
.bitfield
.imm1
= 1;
2069 t
.bitfield
.imm8
= 1;
2070 t
.bitfield
.imm8s
= 1;
2071 t
.bitfield
.imm16
= 1;
2072 t
.bitfield
.imm32
= 1;
2073 t
.bitfield
.imm32s
= 1;
2075 else if (fits_in_signed_byte (num
))
2077 t
.bitfield
.imm8
= 1;
2078 t
.bitfield
.imm8s
= 1;
2079 t
.bitfield
.imm16
= 1;
2080 t
.bitfield
.imm32
= 1;
2081 t
.bitfield
.imm32s
= 1;
2083 else if (fits_in_unsigned_byte (num
))
2085 t
.bitfield
.imm8
= 1;
2086 t
.bitfield
.imm16
= 1;
2087 t
.bitfield
.imm32
= 1;
2088 t
.bitfield
.imm32s
= 1;
2090 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2092 t
.bitfield
.imm16
= 1;
2093 t
.bitfield
.imm32
= 1;
2094 t
.bitfield
.imm32s
= 1;
2096 else if (fits_in_signed_long (num
))
2098 t
.bitfield
.imm32
= 1;
2099 t
.bitfield
.imm32s
= 1;
2101 else if (fits_in_unsigned_long (num
))
2102 t
.bitfield
.imm32
= 1;
2108 offset_in_range (offsetT val
, int size
)
2114 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2115 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2116 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2118 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2124 /* If BFD64, sign extend val for 32bit address mode. */
2125 if (flag_code
!= CODE_64BIT
2126 || i
.prefix
[ADDR_PREFIX
])
2127 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2128 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2131 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2133 char buf1
[40], buf2
[40];
2135 sprint_value (buf1
, val
);
2136 sprint_value (buf2
, val
& mask
);
2137 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2151 a. PREFIX_EXIST if attempting to add a prefix where one from the
2152 same class already exists.
2153 b. PREFIX_LOCK if lock prefix is added.
2154 c. PREFIX_REP if rep/repne prefix is added.
2155 d. PREFIX_OTHER if other prefix is added.
2158 static enum PREFIX_GROUP
2159 add_prefix (unsigned int prefix
)
2161 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2164 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2165 && flag_code
== CODE_64BIT
)
2167 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2168 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2169 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2180 case CS_PREFIX_OPCODE
:
2181 case DS_PREFIX_OPCODE
:
2182 case ES_PREFIX_OPCODE
:
2183 case FS_PREFIX_OPCODE
:
2184 case GS_PREFIX_OPCODE
:
2185 case SS_PREFIX_OPCODE
:
2189 case REPNE_PREFIX_OPCODE
:
2190 case REPE_PREFIX_OPCODE
:
2195 case LOCK_PREFIX_OPCODE
:
2204 case ADDR_PREFIX_OPCODE
:
2208 case DATA_PREFIX_OPCODE
:
2212 if (i
.prefix
[q
] != 0)
2220 i
.prefix
[q
] |= prefix
;
2223 as_bad (_("same type of prefix used twice"));
2229 update_code_flag (int value
, int check
)
2231 PRINTF_LIKE ((*as_error
));
2233 flag_code
= (enum flag_code
) value
;
2234 if (flag_code
== CODE_64BIT
)
2236 cpu_arch_flags
.bitfield
.cpu64
= 1;
2237 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2241 cpu_arch_flags
.bitfield
.cpu64
= 0;
2242 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2244 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2247 as_error
= as_fatal
;
2250 (*as_error
) (_("64bit mode not supported on `%s'."),
2251 cpu_arch_name
? cpu_arch_name
: default_arch
);
2253 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2256 as_error
= as_fatal
;
2259 (*as_error
) (_("32bit mode not supported on `%s'."),
2260 cpu_arch_name
? cpu_arch_name
: default_arch
);
2262 stackop_size
= '\0';
2266 set_code_flag (int value
)
2268 update_code_flag (value
, 0);
2272 set_16bit_gcc_code_flag (int new_code_flag
)
2274 flag_code
= (enum flag_code
) new_code_flag
;
2275 if (flag_code
!= CODE_16BIT
)
2277 cpu_arch_flags
.bitfield
.cpu64
= 0;
2278 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2279 stackop_size
= LONG_MNEM_SUFFIX
;
2283 set_intel_syntax (int syntax_flag
)
2285 /* Find out if register prefixing is specified. */
2286 int ask_naked_reg
= 0;
2289 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2292 int e
= get_symbol_name (&string
);
2294 if (strcmp (string
, "prefix") == 0)
2296 else if (strcmp (string
, "noprefix") == 0)
2299 as_bad (_("bad argument to syntax directive."));
2300 (void) restore_line_pointer (e
);
2302 demand_empty_rest_of_line ();
2304 intel_syntax
= syntax_flag
;
2306 if (ask_naked_reg
== 0)
2307 allow_naked_reg
= (intel_syntax
2308 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2310 allow_naked_reg
= (ask_naked_reg
< 0);
2312 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2314 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2315 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2316 register_prefix
= allow_naked_reg
? "" : "%";
2320 set_intel_mnemonic (int mnemonic_flag
)
2322 intel_mnemonic
= mnemonic_flag
;
2326 set_allow_index_reg (int flag
)
2328 allow_index_reg
= flag
;
2332 set_check (int what
)
2334 enum check_kind
*kind
;
2339 kind
= &operand_check
;
2350 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2353 int e
= get_symbol_name (&string
);
2355 if (strcmp (string
, "none") == 0)
2357 else if (strcmp (string
, "warning") == 0)
2358 *kind
= check_warning
;
2359 else if (strcmp (string
, "error") == 0)
2360 *kind
= check_error
;
2362 as_bad (_("bad argument to %s_check directive."), str
);
2363 (void) restore_line_pointer (e
);
2366 as_bad (_("missing argument for %s_check directive"), str
);
2368 demand_empty_rest_of_line ();
2372 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2373 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2375 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2376 static const char *arch
;
2378 /* Intel LIOM is only supported on ELF. */
2384 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2385 use default_arch. */
2386 arch
= cpu_arch_name
;
2388 arch
= default_arch
;
2391 /* If we are targeting Intel MCU, we must enable it. */
2392 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2393 || new_flag
.bitfield
.cpuiamcu
)
2396 /* If we are targeting Intel L1OM, we must enable it. */
2397 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2398 || new_flag
.bitfield
.cpul1om
)
2401 /* If we are targeting Intel K1OM, we must enable it. */
2402 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2403 || new_flag
.bitfield
.cpuk1om
)
2406 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2411 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2415 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2418 int e
= get_symbol_name (&string
);
2420 i386_cpu_flags flags
;
2422 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2424 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2426 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2430 cpu_arch_name
= cpu_arch
[j
].name
;
2431 cpu_sub_arch_name
= NULL
;
2432 cpu_arch_flags
= cpu_arch
[j
].flags
;
2433 if (flag_code
== CODE_64BIT
)
2435 cpu_arch_flags
.bitfield
.cpu64
= 1;
2436 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2440 cpu_arch_flags
.bitfield
.cpu64
= 0;
2441 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2443 cpu_arch_isa
= cpu_arch
[j
].type
;
2444 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2445 if (!cpu_arch_tune_set
)
2447 cpu_arch_tune
= cpu_arch_isa
;
2448 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2453 flags
= cpu_flags_or (cpu_arch_flags
,
2456 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2458 if (cpu_sub_arch_name
)
2460 char *name
= cpu_sub_arch_name
;
2461 cpu_sub_arch_name
= concat (name
,
2463 (const char *) NULL
);
2467 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2468 cpu_arch_flags
= flags
;
2469 cpu_arch_isa_flags
= flags
;
2471 (void) restore_line_pointer (e
);
2472 demand_empty_rest_of_line ();
2477 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2479 /* Disable an ISA extension. */
2480 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2481 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2483 flags
= cpu_flags_and_not (cpu_arch_flags
,
2484 cpu_noarch
[j
].flags
);
2485 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2487 if (cpu_sub_arch_name
)
2489 char *name
= cpu_sub_arch_name
;
2490 cpu_sub_arch_name
= concat (name
, string
,
2491 (const char *) NULL
);
2495 cpu_sub_arch_name
= xstrdup (string
);
2496 cpu_arch_flags
= flags
;
2497 cpu_arch_isa_flags
= flags
;
2499 (void) restore_line_pointer (e
);
2500 demand_empty_rest_of_line ();
2504 j
= ARRAY_SIZE (cpu_arch
);
2507 if (j
>= ARRAY_SIZE (cpu_arch
))
2508 as_bad (_("no such architecture: `%s'"), string
);
2510 *input_line_pointer
= e
;
2513 as_bad (_("missing cpu architecture"));
2515 no_cond_jump_promotion
= 0;
2516 if (*input_line_pointer
== ','
2517 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2522 ++input_line_pointer
;
2523 e
= get_symbol_name (&string
);
2525 if (strcmp (string
, "nojumps") == 0)
2526 no_cond_jump_promotion
= 1;
2527 else if (strcmp (string
, "jumps") == 0)
2530 as_bad (_("no such architecture modifier: `%s'"), string
);
2532 (void) restore_line_pointer (e
);
2535 demand_empty_rest_of_line ();
2538 enum bfd_architecture
2541 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2543 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2544 || flag_code
!= CODE_64BIT
)
2545 as_fatal (_("Intel L1OM is 64bit ELF only"));
2546 return bfd_arch_l1om
;
2548 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2550 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2551 || flag_code
!= CODE_64BIT
)
2552 as_fatal (_("Intel K1OM is 64bit ELF only"));
2553 return bfd_arch_k1om
;
2555 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2557 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2558 || flag_code
== CODE_64BIT
)
2559 as_fatal (_("Intel MCU is 32bit ELF only"));
2560 return bfd_arch_iamcu
;
2563 return bfd_arch_i386
;
2569 if (!strncmp (default_arch
, "x86_64", 6))
2571 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2573 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2574 || default_arch
[6] != '\0')
2575 as_fatal (_("Intel L1OM is 64bit ELF only"));
2576 return bfd_mach_l1om
;
2578 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2580 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2581 || default_arch
[6] != '\0')
2582 as_fatal (_("Intel K1OM is 64bit ELF only"));
2583 return bfd_mach_k1om
;
2585 else if (default_arch
[6] == '\0')
2586 return bfd_mach_x86_64
;
2588 return bfd_mach_x64_32
;
2590 else if (!strcmp (default_arch
, "i386")
2591 || !strcmp (default_arch
, "iamcu"))
2593 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2595 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2596 as_fatal (_("Intel MCU is 32bit ELF only"));
2597 return bfd_mach_i386_iamcu
;
2600 return bfd_mach_i386_i386
;
2603 as_fatal (_("unknown architecture"));
2609 const char *hash_err
;
2611 /* Support pseudo prefixes like {disp32}. */
2612 lex_type
['{'] = LEX_BEGIN_NAME
;
2614 /* Initialize op_hash hash table. */
2615 op_hash
= hash_new ();
2618 const insn_template
*optab
;
2619 templates
*core_optab
;
2621 /* Setup for loop. */
2623 core_optab
= XNEW (templates
);
2624 core_optab
->start
= optab
;
2629 if (optab
->name
== NULL
2630 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2632 /* different name --> ship out current template list;
2633 add to hash table; & begin anew. */
2634 core_optab
->end
= optab
;
2635 hash_err
= hash_insert (op_hash
,
2637 (void *) core_optab
);
2640 as_fatal (_("can't hash %s: %s"),
2644 if (optab
->name
== NULL
)
2646 core_optab
= XNEW (templates
);
2647 core_optab
->start
= optab
;
2652 /* Initialize reg_hash hash table. */
2653 reg_hash
= hash_new ();
2655 const reg_entry
*regtab
;
2656 unsigned int regtab_size
= i386_regtab_size
;
2658 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2660 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2662 as_fatal (_("can't hash %s: %s"),
2668 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2673 for (c
= 0; c
< 256; c
++)
2678 mnemonic_chars
[c
] = c
;
2679 register_chars
[c
] = c
;
2680 operand_chars
[c
] = c
;
2682 else if (ISLOWER (c
))
2684 mnemonic_chars
[c
] = c
;
2685 register_chars
[c
] = c
;
2686 operand_chars
[c
] = c
;
2688 else if (ISUPPER (c
))
2690 mnemonic_chars
[c
] = TOLOWER (c
);
2691 register_chars
[c
] = mnemonic_chars
[c
];
2692 operand_chars
[c
] = c
;
2694 else if (c
== '{' || c
== '}')
2696 mnemonic_chars
[c
] = c
;
2697 operand_chars
[c
] = c
;
2700 if (ISALPHA (c
) || ISDIGIT (c
))
2701 identifier_chars
[c
] = c
;
2704 identifier_chars
[c
] = c
;
2705 operand_chars
[c
] = c
;
2710 identifier_chars
['@'] = '@';
2713 identifier_chars
['?'] = '?';
2714 operand_chars
['?'] = '?';
2716 digit_chars
['-'] = '-';
2717 mnemonic_chars
['_'] = '_';
2718 mnemonic_chars
['-'] = '-';
2719 mnemonic_chars
['.'] = '.';
2720 identifier_chars
['_'] = '_';
2721 identifier_chars
['.'] = '.';
2723 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2724 operand_chars
[(unsigned char) *p
] = *p
;
2727 if (flag_code
== CODE_64BIT
)
2729 #if defined (OBJ_COFF) && defined (TE_PE)
2730 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2733 x86_dwarf2_return_column
= 16;
2735 x86_cie_data_alignment
= -8;
2739 x86_dwarf2_return_column
= 8;
2740 x86_cie_data_alignment
= -4;
2745 i386_print_statistics (FILE *file
)
2747 hash_print_statistics (file
, "i386 opcode", op_hash
);
2748 hash_print_statistics (file
, "i386 register", reg_hash
);
2753 /* Debugging routines for md_assemble. */
2754 static void pte (insn_template
*);
2755 static void pt (i386_operand_type
);
2756 static void pe (expressionS
*);
2757 static void ps (symbolS
*);
2760 pi (char *line
, i386_insn
*x
)
2764 fprintf (stdout
, "%s: template ", line
);
2766 fprintf (stdout
, " address: base %s index %s scale %x\n",
2767 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2768 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2769 x
->log2_scale_factor
);
2770 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2771 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2772 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2773 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2774 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2775 (x
->rex
& REX_W
) != 0,
2776 (x
->rex
& REX_R
) != 0,
2777 (x
->rex
& REX_X
) != 0,
2778 (x
->rex
& REX_B
) != 0);
2779 for (j
= 0; j
< x
->operands
; j
++)
2781 fprintf (stdout
, " #%d: ", j
+ 1);
2783 fprintf (stdout
, "\n");
2784 if (x
->types
[j
].bitfield
.reg8
2785 || x
->types
[j
].bitfield
.reg16
2786 || x
->types
[j
].bitfield
.reg32
2787 || x
->types
[j
].bitfield
.reg64
2788 || x
->types
[j
].bitfield
.regmmx
2789 || x
->types
[j
].bitfield
.regxmm
2790 || x
->types
[j
].bitfield
.regymm
2791 || x
->types
[j
].bitfield
.regzmm
2792 || x
->types
[j
].bitfield
.sreg2
2793 || x
->types
[j
].bitfield
.sreg3
2794 || x
->types
[j
].bitfield
.control
2795 || x
->types
[j
].bitfield
.debug
2796 || x
->types
[j
].bitfield
.test
)
2797 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2798 if (operand_type_check (x
->types
[j
], imm
))
2800 if (operand_type_check (x
->types
[j
], disp
))
2801 pe (x
->op
[j
].disps
);
2806 pte (insn_template
*t
)
2809 fprintf (stdout
, " %d operands ", t
->operands
);
2810 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2811 if (t
->extension_opcode
!= None
)
2812 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2813 if (t
->opcode_modifier
.d
)
2814 fprintf (stdout
, "D");
2815 if (t
->opcode_modifier
.w
)
2816 fprintf (stdout
, "W");
2817 fprintf (stdout
, "\n");
2818 for (j
= 0; j
< t
->operands
; j
++)
2820 fprintf (stdout
, " #%d type ", j
+ 1);
2821 pt (t
->operand_types
[j
]);
2822 fprintf (stdout
, "\n");
2829 fprintf (stdout
, " operation %d\n", e
->X_op
);
2830 fprintf (stdout
, " add_number %ld (%lx)\n",
2831 (long) e
->X_add_number
, (long) e
->X_add_number
);
2832 if (e
->X_add_symbol
)
2834 fprintf (stdout
, " add_symbol ");
2835 ps (e
->X_add_symbol
);
2836 fprintf (stdout
, "\n");
2840 fprintf (stdout
, " op_symbol ");
2841 ps (e
->X_op_symbol
);
2842 fprintf (stdout
, "\n");
2849 fprintf (stdout
, "%s type %s%s",
2851 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2852 segment_name (S_GET_SEGMENT (s
)));
2855 static struct type_name
2857 i386_operand_type mask
;
2860 const type_names
[] =
2862 { OPERAND_TYPE_REG8
, "r8" },
2863 { OPERAND_TYPE_REG16
, "r16" },
2864 { OPERAND_TYPE_REG32
, "r32" },
2865 { OPERAND_TYPE_REG64
, "r64" },
2866 { OPERAND_TYPE_IMM8
, "i8" },
2867 { OPERAND_TYPE_IMM8
, "i8s" },
2868 { OPERAND_TYPE_IMM16
, "i16" },
2869 { OPERAND_TYPE_IMM32
, "i32" },
2870 { OPERAND_TYPE_IMM32S
, "i32s" },
2871 { OPERAND_TYPE_IMM64
, "i64" },
2872 { OPERAND_TYPE_IMM1
, "i1" },
2873 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2874 { OPERAND_TYPE_DISP8
, "d8" },
2875 { OPERAND_TYPE_DISP16
, "d16" },
2876 { OPERAND_TYPE_DISP32
, "d32" },
2877 { OPERAND_TYPE_DISP32S
, "d32s" },
2878 { OPERAND_TYPE_DISP64
, "d64" },
2879 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2880 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2881 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2882 { OPERAND_TYPE_CONTROL
, "control reg" },
2883 { OPERAND_TYPE_TEST
, "test reg" },
2884 { OPERAND_TYPE_DEBUG
, "debug reg" },
2885 { OPERAND_TYPE_FLOATREG
, "FReg" },
2886 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2887 { OPERAND_TYPE_SREG2
, "SReg2" },
2888 { OPERAND_TYPE_SREG3
, "SReg3" },
2889 { OPERAND_TYPE_ACC
, "Acc" },
2890 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2891 { OPERAND_TYPE_REGMMX
, "rMMX" },
2892 { OPERAND_TYPE_REGXMM
, "rXMM" },
2893 { OPERAND_TYPE_REGYMM
, "rYMM" },
2894 { OPERAND_TYPE_REGZMM
, "rZMM" },
2895 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2896 { OPERAND_TYPE_ESSEG
, "es" },
2900 pt (i386_operand_type t
)
2903 i386_operand_type a
;
2905 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2907 a
= operand_type_and (t
, type_names
[j
].mask
);
2908 if (!operand_type_all_zero (&a
))
2909 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2914 #endif /* DEBUG386 */
2916 static bfd_reloc_code_real_type
2917 reloc (unsigned int size
,
2920 bfd_reloc_code_real_type other
)
2922 if (other
!= NO_RELOC
)
2924 reloc_howto_type
*rel
;
2929 case BFD_RELOC_X86_64_GOT32
:
2930 return BFD_RELOC_X86_64_GOT64
;
2932 case BFD_RELOC_X86_64_GOTPLT64
:
2933 return BFD_RELOC_X86_64_GOTPLT64
;
2935 case BFD_RELOC_X86_64_PLTOFF64
:
2936 return BFD_RELOC_X86_64_PLTOFF64
;
2938 case BFD_RELOC_X86_64_GOTPC32
:
2939 other
= BFD_RELOC_X86_64_GOTPC64
;
2941 case BFD_RELOC_X86_64_GOTPCREL
:
2942 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2944 case BFD_RELOC_X86_64_TPOFF32
:
2945 other
= BFD_RELOC_X86_64_TPOFF64
;
2947 case BFD_RELOC_X86_64_DTPOFF32
:
2948 other
= BFD_RELOC_X86_64_DTPOFF64
;
2954 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2955 if (other
== BFD_RELOC_SIZE32
)
2958 other
= BFD_RELOC_SIZE64
;
2961 as_bad (_("there are no pc-relative size relocations"));
2967 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2968 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2971 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2973 as_bad (_("unknown relocation (%u)"), other
);
2974 else if (size
!= bfd_get_reloc_size (rel
))
2975 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2976 bfd_get_reloc_size (rel
),
2978 else if (pcrel
&& !rel
->pc_relative
)
2979 as_bad (_("non-pc-relative relocation for pc-relative field"));
2980 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2982 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2984 as_bad (_("relocated field and relocation type differ in signedness"));
2993 as_bad (_("there are no unsigned pc-relative relocations"));
2996 case 1: return BFD_RELOC_8_PCREL
;
2997 case 2: return BFD_RELOC_16_PCREL
;
2998 case 4: return BFD_RELOC_32_PCREL
;
2999 case 8: return BFD_RELOC_64_PCREL
;
3001 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3008 case 4: return BFD_RELOC_X86_64_32S
;
3013 case 1: return BFD_RELOC_8
;
3014 case 2: return BFD_RELOC_16
;
3015 case 4: return BFD_RELOC_32
;
3016 case 8: return BFD_RELOC_64
;
3018 as_bad (_("cannot do %s %u byte relocation"),
3019 sign
> 0 ? "signed" : "unsigned", size
);
3025 /* Here we decide which fixups can be adjusted to make them relative to
3026 the beginning of the section instead of the symbol. Basically we need
3027 to make sure that the dynamic relocations are done correctly, so in
3028 some cases we force the original symbol to be used. */
3031 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3033 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3037 /* Don't adjust pc-relative references to merge sections in 64-bit
3039 if (use_rela_relocations
3040 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3044 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3045 and changed later by validate_fix. */
3046 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3047 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3050 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3051 for size relocations. */
3052 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3053 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3054 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3055 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3056 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3057 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3058 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3059 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3060 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3061 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3062 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3063 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3064 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3065 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3066 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3067 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3068 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3069 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3070 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3071 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3072 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3073 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3074 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3075 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3076 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3077 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3078 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3079 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3080 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3081 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3082 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3083 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3084 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3091 intel_float_operand (const char *mnemonic
)
3093 /* Note that the value returned is meaningful only for opcodes with (memory)
3094 operands, hence the code here is free to improperly handle opcodes that
3095 have no operands (for better performance and smaller code). */
3097 if (mnemonic
[0] != 'f')
3098 return 0; /* non-math */
3100 switch (mnemonic
[1])
3102 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3103 the fs segment override prefix not currently handled because no
3104 call path can make opcodes without operands get here */
3106 return 2 /* integer op */;
3108 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3109 return 3; /* fldcw/fldenv */
3112 if (mnemonic
[2] != 'o' /* fnop */)
3113 return 3; /* non-waiting control op */
3116 if (mnemonic
[2] == 's')
3117 return 3; /* frstor/frstpm */
3120 if (mnemonic
[2] == 'a')
3121 return 3; /* fsave */
3122 if (mnemonic
[2] == 't')
3124 switch (mnemonic
[3])
3126 case 'c': /* fstcw */
3127 case 'd': /* fstdw */
3128 case 'e': /* fstenv */
3129 case 's': /* fsts[gw] */
3135 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3136 return 0; /* fxsave/fxrstor are not really math ops */
3143 /* Build the VEX prefix. */
3146 build_vex_prefix (const insn_template
*t
)
3148 unsigned int register_specifier
;
3149 unsigned int implied_prefix
;
3150 unsigned int vector_length
;
3152 /* Check register specifier. */
3153 if (i
.vex
.register_specifier
)
3155 register_specifier
=
3156 ~register_number (i
.vex
.register_specifier
) & 0xf;
3157 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3160 register_specifier
= 0xf;
3162 /* Use 2-byte VEX prefix by swapping destination and source
3164 if (i
.vec_encoding
!= vex_encoding_vex3
3165 && i
.dir_encoding
== dir_encoding_default
3166 && i
.operands
== i
.reg_operands
3167 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3168 && i
.tm
.opcode_modifier
.load
3171 unsigned int xchg
= i
.operands
- 1;
3172 union i386_op temp_op
;
3173 i386_operand_type temp_type
;
3175 temp_type
= i
.types
[xchg
];
3176 i
.types
[xchg
] = i
.types
[0];
3177 i
.types
[0] = temp_type
;
3178 temp_op
= i
.op
[xchg
];
3179 i
.op
[xchg
] = i
.op
[0];
3182 gas_assert (i
.rm
.mode
== 3);
3186 i
.rm
.regmem
= i
.rm
.reg
;
3189 /* Use the next insn. */
3193 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3194 vector_length
= avxscalar
;
3196 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3198 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3203 case DATA_PREFIX_OPCODE
:
3206 case REPE_PREFIX_OPCODE
:
3209 case REPNE_PREFIX_OPCODE
:
3216 /* Use 2-byte VEX prefix if possible. */
3217 if (i
.vec_encoding
!= vex_encoding_vex3
3218 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3219 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3220 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3222 /* 2-byte VEX prefix. */
3226 i
.vex
.bytes
[0] = 0xc5;
3228 /* Check the REX.R bit. */
3229 r
= (i
.rex
& REX_R
) ? 0 : 1;
3230 i
.vex
.bytes
[1] = (r
<< 7
3231 | register_specifier
<< 3
3232 | vector_length
<< 2
3237 /* 3-byte VEX prefix. */
3242 switch (i
.tm
.opcode_modifier
.vexopcode
)
3246 i
.vex
.bytes
[0] = 0xc4;
3250 i
.vex
.bytes
[0] = 0xc4;
3254 i
.vex
.bytes
[0] = 0xc4;
3258 i
.vex
.bytes
[0] = 0x8f;
3262 i
.vex
.bytes
[0] = 0x8f;
3266 i
.vex
.bytes
[0] = 0x8f;
3272 /* The high 3 bits of the second VEX byte are 1's compliment
3273 of RXB bits from REX. */
3274 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3276 /* Check the REX.W bit. */
3277 w
= (i
.rex
& REX_W
) ? 1 : 0;
3278 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3281 i
.vex
.bytes
[2] = (w
<< 7
3282 | register_specifier
<< 3
3283 | vector_length
<< 2
3288 /* Build the EVEX prefix. */
3291 build_evex_prefix (void)
3293 unsigned int register_specifier
;
3294 unsigned int implied_prefix
;
3296 rex_byte vrex_used
= 0;
3298 /* Check register specifier. */
3299 if (i
.vex
.register_specifier
)
3301 gas_assert ((i
.vrex
& REX_X
) == 0);
3303 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3304 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3305 register_specifier
+= 8;
3306 /* The upper 16 registers are encoded in the fourth byte of the
3308 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3309 i
.vex
.bytes
[3] = 0x8;
3310 register_specifier
= ~register_specifier
& 0xf;
3314 register_specifier
= 0xf;
3316 /* Encode upper 16 vector index register in the fourth byte of
3318 if (!(i
.vrex
& REX_X
))
3319 i
.vex
.bytes
[3] = 0x8;
3324 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3329 case DATA_PREFIX_OPCODE
:
3332 case REPE_PREFIX_OPCODE
:
3335 case REPNE_PREFIX_OPCODE
:
3342 /* 4 byte EVEX prefix. */
3344 i
.vex
.bytes
[0] = 0x62;
3347 switch (i
.tm
.opcode_modifier
.vexopcode
)
3363 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3365 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3367 /* The fifth bit of the second EVEX byte is 1's compliment of the
3368 REX_R bit in VREX. */
3369 if (!(i
.vrex
& REX_R
))
3370 i
.vex
.bytes
[1] |= 0x10;
3374 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3376 /* When all operands are registers, the REX_X bit in REX is not
3377 used. We reuse it to encode the upper 16 registers, which is
3378 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3379 as 1's compliment. */
3380 if ((i
.vrex
& REX_B
))
3383 i
.vex
.bytes
[1] &= ~0x40;
3387 /* EVEX instructions shouldn't need the REX prefix. */
3388 i
.vrex
&= ~vrex_used
;
3389 gas_assert (i
.vrex
== 0);
3391 /* Check the REX.W bit. */
3392 w
= (i
.rex
& REX_W
) ? 1 : 0;
3393 if (i
.tm
.opcode_modifier
.vexw
)
3395 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3398 /* If w is not set it means we are dealing with WIG instruction. */
3401 if (evexwig
== evexw1
)
3405 /* Encode the U bit. */
3406 implied_prefix
|= 0x4;
3408 /* The third byte of the EVEX prefix. */
3409 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3411 /* The fourth byte of the EVEX prefix. */
3412 /* The zeroing-masking bit. */
3413 if (i
.mask
&& i
.mask
->zeroing
)
3414 i
.vex
.bytes
[3] |= 0x80;
3416 /* Don't always set the broadcast bit if there is no RC. */
3419 /* Encode the vector length. */
3420 unsigned int vec_length
;
3422 switch (i
.tm
.opcode_modifier
.evex
)
3424 case EVEXLIG
: /* LL' is ignored */
3425 vec_length
= evexlig
<< 5;
3428 vec_length
= 0 << 5;
3431 vec_length
= 1 << 5;
3434 vec_length
= 2 << 5;
3440 i
.vex
.bytes
[3] |= vec_length
;
3441 /* Encode the broadcast bit. */
3443 i
.vex
.bytes
[3] |= 0x10;
3447 if (i
.rounding
->type
!= saeonly
)
3448 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3450 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3453 if (i
.mask
&& i
.mask
->mask
)
3454 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3458 process_immext (void)
3462 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3465 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3466 with an opcode suffix which is coded in the same place as an
3467 8-bit immediate field would be.
3468 Here we check those operands and remove them afterwards. */
3471 for (x
= 0; x
< i
.operands
; x
++)
3472 if (register_number (i
.op
[x
].regs
) != x
)
3473 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3474 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3480 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3482 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3483 suffix which is coded in the same place as an 8-bit immediate
3485 Here we check those operands and remove them afterwards. */
3488 if (i
.operands
!= 3)
3491 for (x
= 0; x
< 2; x
++)
3492 if (register_number (i
.op
[x
].regs
) != x
)
3493 goto bad_register_operand
;
3495 /* Check for third operand for mwaitx/monitorx insn. */
3496 if (register_number (i
.op
[x
].regs
)
3497 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3499 bad_register_operand
:
3500 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3501 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3508 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3509 which is coded in the same place as an 8-bit immediate field
3510 would be. Here we fake an 8-bit immediate operand from the
3511 opcode suffix stored in tm.extension_opcode.
3513 AVX instructions also use this encoding, for some of
3514 3 argument instructions. */
3516 gas_assert (i
.imm_operands
<= 1
3518 || ((i
.tm
.opcode_modifier
.vex
3519 || i
.tm
.opcode_modifier
.evex
)
3520 && i
.operands
<= 4)));
3522 exp
= &im_expressions
[i
.imm_operands
++];
3523 i
.op
[i
.operands
].imms
= exp
;
3524 i
.types
[i
.operands
] = imm8
;
3526 exp
->X_op
= O_constant
;
3527 exp
->X_add_number
= i
.tm
.extension_opcode
;
3528 i
.tm
.extension_opcode
= None
;
3535 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3540 as_bad (_("invalid instruction `%s' after `%s'"),
3541 i
.tm
.name
, i
.hle_prefix
);
3544 if (i
.prefix
[LOCK_PREFIX
])
3546 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3550 case HLEPrefixRelease
:
3551 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3553 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3557 if (i
.mem_operands
== 0
3558 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3560 as_bad (_("memory destination needed for instruction `%s'"
3561 " after `xrelease'"), i
.tm
.name
);
3568 /* This is the guts of the machine-dependent assembler. LINE points to a
3569 machine dependent instruction. This function is supposed to emit
3570 the frags/bytes it assembles to. */
3573 md_assemble (char *line
)
3576 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
3577 const insn_template
*t
;
3579 /* Initialize globals. */
3580 memset (&i
, '\0', sizeof (i
));
3581 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3582 i
.reloc
[j
] = NO_RELOC
;
3583 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3584 memset (im_expressions
, '\0', sizeof (im_expressions
));
3585 save_stack_p
= save_stack
;
3587 /* First parse an instruction mnemonic & call i386_operand for the operands.
3588 We assume that the scrubber has arranged it so that line[0] is the valid
3589 start of a (possibly prefixed) mnemonic. */
3591 line
= parse_insn (line
, mnemonic
);
3594 mnem_suffix
= i
.suffix
;
3596 line
= parse_operands (line
, mnemonic
);
3598 xfree (i
.memop1_string
);
3599 i
.memop1_string
= NULL
;
3603 /* Now we've parsed the mnemonic into a set of templates, and have the
3604 operands at hand. */
3606 /* All intel opcodes have reversed operands except for "bound" and
3607 "enter". We also don't reverse intersegment "jmp" and "call"
3608 instructions with 2 immediate operands so that the immediate segment
3609 precedes the offset, as it does when in AT&T mode. */
3612 && (strcmp (mnemonic
, "bound") != 0)
3613 && (strcmp (mnemonic
, "invlpga") != 0)
3614 && !(operand_type_check (i
.types
[0], imm
)
3615 && operand_type_check (i
.types
[1], imm
)))
3618 /* The order of the immediates should be reversed
3619 for 2 immediates extrq and insertq instructions */
3620 if (i
.imm_operands
== 2
3621 && (strcmp (mnemonic
, "extrq") == 0
3622 || strcmp (mnemonic
, "insertq") == 0))
3623 swap_2_operands (0, 1);
3628 /* Don't optimize displacement for movabs since it only takes 64bit
3631 && i
.disp_encoding
!= disp_encoding_32bit
3632 && (flag_code
!= CODE_64BIT
3633 || strcmp (mnemonic
, "movabs") != 0))
3636 /* Next, we find a template that matches the given insn,
3637 making sure the overlap of the given operands types is consistent
3638 with the template operand types. */
3640 if (!(t
= match_template (mnem_suffix
)))
3643 if (sse_check
!= check_none
3644 && !i
.tm
.opcode_modifier
.noavx
3645 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3646 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3647 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3648 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3649 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3650 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3652 (sse_check
== check_warning
3654 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3657 /* Zap movzx and movsx suffix. The suffix has been set from
3658 "word ptr" or "byte ptr" on the source operand in Intel syntax
3659 or extracted from mnemonic in AT&T syntax. But we'll use
3660 the destination register to choose the suffix for encoding. */
3661 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3663 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3664 there is no suffix, the default will be byte extension. */
3665 if (i
.reg_operands
!= 2
3668 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3673 if (i
.tm
.opcode_modifier
.fwait
)
3674 if (!add_prefix (FWAIT_OPCODE
))
3677 /* Check if REP prefix is OK. */
3678 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3680 as_bad (_("invalid instruction `%s' after `%s'"),
3681 i
.tm
.name
, i
.rep_prefix
);
3685 /* Check for lock without a lockable instruction. Destination operand
3686 must be memory unless it is xchg (0x86). */
3687 if (i
.prefix
[LOCK_PREFIX
]
3688 && (!i
.tm
.opcode_modifier
.islockable
3689 || i
.mem_operands
== 0
3690 || (i
.tm
.base_opcode
!= 0x86
3691 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3693 as_bad (_("expecting lockable instruction after `lock'"));
3697 /* Check if HLE prefix is OK. */
3698 if (i
.hle_prefix
&& !check_hle ())
3701 /* Check BND prefix. */
3702 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3703 as_bad (_("expecting valid branch instruction after `bnd'"));
3705 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
3707 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
3708 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3709 else if (flag_code
!= CODE_16BIT
3710 ? i
.prefix
[ADDR_PREFIX
]
3711 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
3712 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3715 /* Insert BND prefix. */
3717 && i
.tm
.opcode_modifier
.bndprefixok
3718 && !i
.prefix
[BND_PREFIX
])
3719 add_prefix (BND_PREFIX_OPCODE
);
3721 /* Check string instruction segment overrides. */
3722 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3724 if (!check_string ())
3726 i
.disp_operands
= 0;
3729 if (!process_suffix ())
3732 /* Update operand types. */
3733 for (j
= 0; j
< i
.operands
; j
++)
3734 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3736 /* Make still unresolved immediate matches conform to size of immediate
3737 given in i.suffix. */
3738 if (!finalize_imm ())
3741 if (i
.types
[0].bitfield
.imm1
)
3742 i
.imm_operands
= 0; /* kludge for shift insns. */
3744 /* We only need to check those implicit registers for instructions
3745 with 3 operands or less. */
3746 if (i
.operands
<= 3)
3747 for (j
= 0; j
< i
.operands
; j
++)
3748 if (i
.types
[j
].bitfield
.inoutportreg
3749 || i
.types
[j
].bitfield
.shiftcount
3750 || i
.types
[j
].bitfield
.acc
3751 || i
.types
[j
].bitfield
.floatacc
)
3754 /* ImmExt should be processed after SSE2AVX. */
3755 if (!i
.tm
.opcode_modifier
.sse2avx
3756 && i
.tm
.opcode_modifier
.immext
)
3759 /* For insns with operands there are more diddles to do to the opcode. */
3762 if (!process_operands ())
3765 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3767 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3768 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3771 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3773 if (flag_code
== CODE_16BIT
)
3775 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3780 if (i
.tm
.opcode_modifier
.vex
)
3781 build_vex_prefix (t
);
3783 build_evex_prefix ();
3786 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3787 instructions may define INT_OPCODE as well, so avoid this corner
3788 case for those instructions that use MODRM. */
3789 if (i
.tm
.base_opcode
== INT_OPCODE
3790 && !i
.tm
.opcode_modifier
.modrm
3791 && i
.op
[0].imms
->X_add_number
== 3)
3793 i
.tm
.base_opcode
= INT3_OPCODE
;
3797 if ((i
.tm
.opcode_modifier
.jump
3798 || i
.tm
.opcode_modifier
.jumpbyte
3799 || i
.tm
.opcode_modifier
.jumpdword
)
3800 && i
.op
[0].disps
->X_op
== O_constant
)
3802 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3803 the absolute address given by the constant. Since ix86 jumps and
3804 calls are pc relative, we need to generate a reloc. */
3805 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3806 i
.op
[0].disps
->X_op
= O_symbol
;
3809 if (i
.tm
.opcode_modifier
.rex64
)
3812 /* For 8 bit registers we need an empty rex prefix. Also if the
3813 instruction already has a prefix, we need to convert old
3814 registers to new ones. */
3816 if ((i
.types
[0].bitfield
.reg8
3817 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3818 || (i
.types
[1].bitfield
.reg8
3819 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3820 || ((i
.types
[0].bitfield
.reg8
3821 || i
.types
[1].bitfield
.reg8
)
3826 i
.rex
|= REX_OPCODE
;
3827 for (x
= 0; x
< 2; x
++)
3829 /* Look for 8 bit operand that uses old registers. */
3830 if (i
.types
[x
].bitfield
.reg8
3831 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3833 /* In case it is "hi" register, give up. */
3834 if (i
.op
[x
].regs
->reg_num
> 3)
3835 as_bad (_("can't encode register '%s%s' in an "
3836 "instruction requiring REX prefix."),
3837 register_prefix
, i
.op
[x
].regs
->reg_name
);
3839 /* Otherwise it is equivalent to the extended register.
3840 Since the encoding doesn't change this is merely
3841 cosmetic cleanup for debug output. */
3843 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3849 add_prefix (REX_OPCODE
| i
.rex
);
3851 /* We are ready to output the insn. */
3856 parse_insn (char *line
, char *mnemonic
)
3859 char *token_start
= l
;
3862 const insn_template
*t
;
3868 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3873 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3875 as_bad (_("no such instruction: `%s'"), token_start
);
3880 if (!is_space_char (*l
)
3881 && *l
!= END_OF_INSN
3883 || (*l
!= PREFIX_SEPARATOR
3886 as_bad (_("invalid character %s in mnemonic"),
3887 output_invalid (*l
));
3890 if (token_start
== l
)
3892 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3893 as_bad (_("expecting prefix; got nothing"));
3895 as_bad (_("expecting mnemonic; got nothing"));
3899 /* Look up instruction (or prefix) via hash table. */
3900 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3902 if (*l
!= END_OF_INSN
3903 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3904 && current_templates
3905 && current_templates
->start
->opcode_modifier
.isprefix
)
3907 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3909 as_bad ((flag_code
!= CODE_64BIT
3910 ? _("`%s' is only supported in 64-bit mode")
3911 : _("`%s' is not supported in 64-bit mode")),
3912 current_templates
->start
->name
);
3915 /* If we are in 16-bit mode, do not allow addr16 or data16.
3916 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3917 if ((current_templates
->start
->opcode_modifier
.size16
3918 || current_templates
->start
->opcode_modifier
.size32
)
3919 && flag_code
!= CODE_64BIT
3920 && (current_templates
->start
->opcode_modifier
.size32
3921 ^ (flag_code
== CODE_16BIT
)))
3923 as_bad (_("redundant %s prefix"),
3924 current_templates
->start
->name
);
3927 if (current_templates
->start
->opcode_length
== 0)
3929 /* Handle pseudo prefixes. */
3930 switch (current_templates
->start
->base_opcode
)
3934 i
.disp_encoding
= disp_encoding_8bit
;
3938 i
.disp_encoding
= disp_encoding_32bit
;
3942 i
.dir_encoding
= dir_encoding_load
;
3946 i
.dir_encoding
= dir_encoding_store
;
3950 i
.vec_encoding
= vex_encoding_vex2
;
3954 i
.vec_encoding
= vex_encoding_vex3
;
3958 i
.vec_encoding
= vex_encoding_evex
;
3966 /* Add prefix, checking for repeated prefixes. */
3967 switch (add_prefix (current_templates
->start
->base_opcode
))
3972 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3973 i
.hle_prefix
= current_templates
->start
->name
;
3974 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3975 i
.bnd_prefix
= current_templates
->start
->name
;
3977 i
.rep_prefix
= current_templates
->start
->name
;
3983 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3990 if (!current_templates
)
3992 /* Check if we should swap operand or force 32bit displacement in
3994 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3995 i
.dir_encoding
= dir_encoding_store
;
3996 else if (mnem_p
- 3 == dot_p
3999 i
.disp_encoding
= disp_encoding_8bit
;
4000 else if (mnem_p
- 4 == dot_p
4004 i
.disp_encoding
= disp_encoding_32bit
;
4009 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4012 if (!current_templates
)
4015 /* See if we can get a match by trimming off a suffix. */
4018 case WORD_MNEM_SUFFIX
:
4019 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4020 i
.suffix
= SHORT_MNEM_SUFFIX
;
4023 case BYTE_MNEM_SUFFIX
:
4024 case QWORD_MNEM_SUFFIX
:
4025 i
.suffix
= mnem_p
[-1];
4027 current_templates
= (const templates
*) hash_find (op_hash
,
4030 case SHORT_MNEM_SUFFIX
:
4031 case LONG_MNEM_SUFFIX
:
4034 i
.suffix
= mnem_p
[-1];
4036 current_templates
= (const templates
*) hash_find (op_hash
,
4045 if (intel_float_operand (mnemonic
) == 1)
4046 i
.suffix
= SHORT_MNEM_SUFFIX
;
4048 i
.suffix
= LONG_MNEM_SUFFIX
;
4050 current_templates
= (const templates
*) hash_find (op_hash
,
4055 if (!current_templates
)
4057 as_bad (_("no such instruction: `%s'"), token_start
);
4062 if (current_templates
->start
->opcode_modifier
.jump
4063 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4065 /* Check for a branch hint. We allow ",pt" and ",pn" for
4066 predict taken and predict not taken respectively.
4067 I'm not sure that branch hints actually do anything on loop
4068 and jcxz insns (JumpByte) for current Pentium4 chips. They
4069 may work in the future and it doesn't hurt to accept them
4071 if (l
[0] == ',' && l
[1] == 'p')
4075 if (!add_prefix (DS_PREFIX_OPCODE
))
4079 else if (l
[2] == 'n')
4081 if (!add_prefix (CS_PREFIX_OPCODE
))
4087 /* Any other comma loses. */
4090 as_bad (_("invalid character %s in mnemonic"),
4091 output_invalid (*l
));
4095 /* Check if instruction is supported on specified architecture. */
4097 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4099 supported
|= cpu_flags_match (t
);
4100 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4104 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4106 as_bad (flag_code
== CODE_64BIT
4107 ? _("`%s' is not supported in 64-bit mode")
4108 : _("`%s' is only supported in 64-bit mode"),
4109 current_templates
->start
->name
);
4112 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
4114 as_bad (_("`%s' is not supported on `%s%s'"),
4115 current_templates
->start
->name
,
4116 cpu_arch_name
? cpu_arch_name
: default_arch
,
4117 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4122 if (!cpu_arch_flags
.bitfield
.cpui386
4123 && (flag_code
!= CODE_16BIT
))
4125 as_warn (_("use .code16 to ensure correct addressing mode"));
4132 parse_operands (char *l
, const char *mnemonic
)
4136 /* 1 if operand is pending after ','. */
4137 unsigned int expecting_operand
= 0;
4139 /* Non-zero if operand parens not balanced. */
4140 unsigned int paren_not_balanced
;
4142 while (*l
!= END_OF_INSN
)
4144 /* Skip optional white space before operand. */
4145 if (is_space_char (*l
))
4147 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4149 as_bad (_("invalid character %s before operand %d"),
4150 output_invalid (*l
),
4154 token_start
= l
; /* After white space. */
4155 paren_not_balanced
= 0;
4156 while (paren_not_balanced
|| *l
!= ',')
4158 if (*l
== END_OF_INSN
)
4160 if (paren_not_balanced
)
4163 as_bad (_("unbalanced parenthesis in operand %d."),
4166 as_bad (_("unbalanced brackets in operand %d."),
4171 break; /* we are done */
4173 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4175 as_bad (_("invalid character %s in operand %d"),
4176 output_invalid (*l
),
4183 ++paren_not_balanced
;
4185 --paren_not_balanced
;
4190 ++paren_not_balanced
;
4192 --paren_not_balanced
;
4196 if (l
!= token_start
)
4197 { /* Yes, we've read in another operand. */
4198 unsigned int operand_ok
;
4199 this_operand
= i
.operands
++;
4200 if (i
.operands
> MAX_OPERANDS
)
4202 as_bad (_("spurious operands; (%d operands/instruction max)"),
4206 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4207 /* Now parse operand adding info to 'i' as we go along. */
4208 END_STRING_AND_SAVE (l
);
4212 i386_intel_operand (token_start
,
4213 intel_float_operand (mnemonic
));
4215 operand_ok
= i386_att_operand (token_start
);
4217 RESTORE_END_STRING (l
);
4223 if (expecting_operand
)
4225 expecting_operand_after_comma
:
4226 as_bad (_("expecting operand after ','; got nothing"));
4231 as_bad (_("expecting operand before ','; got nothing"));
4236 /* Now *l must be either ',' or END_OF_INSN. */
4239 if (*++l
== END_OF_INSN
)
4241 /* Just skip it, if it's \n complain. */
4242 goto expecting_operand_after_comma
;
4244 expecting_operand
= 1;
4251 swap_2_operands (int xchg1
, int xchg2
)
4253 union i386_op temp_op
;
4254 i386_operand_type temp_type
;
4255 enum bfd_reloc_code_real temp_reloc
;
4257 temp_type
= i
.types
[xchg2
];
4258 i
.types
[xchg2
] = i
.types
[xchg1
];
4259 i
.types
[xchg1
] = temp_type
;
4260 temp_op
= i
.op
[xchg2
];
4261 i
.op
[xchg2
] = i
.op
[xchg1
];
4262 i
.op
[xchg1
] = temp_op
;
4263 temp_reloc
= i
.reloc
[xchg2
];
4264 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4265 i
.reloc
[xchg1
] = temp_reloc
;
4269 if (i
.mask
->operand
== xchg1
)
4270 i
.mask
->operand
= xchg2
;
4271 else if (i
.mask
->operand
== xchg2
)
4272 i
.mask
->operand
= xchg1
;
4276 if (i
.broadcast
->operand
== xchg1
)
4277 i
.broadcast
->operand
= xchg2
;
4278 else if (i
.broadcast
->operand
== xchg2
)
4279 i
.broadcast
->operand
= xchg1
;
4283 if (i
.rounding
->operand
== xchg1
)
4284 i
.rounding
->operand
= xchg2
;
4285 else if (i
.rounding
->operand
== xchg2
)
4286 i
.rounding
->operand
= xchg1
;
4291 swap_operands (void)
4297 swap_2_operands (1, i
.operands
- 2);
4301 swap_2_operands (0, i
.operands
- 1);
4307 if (i
.mem_operands
== 2)
4309 const seg_entry
*temp_seg
;
4310 temp_seg
= i
.seg
[0];
4311 i
.seg
[0] = i
.seg
[1];
4312 i
.seg
[1] = temp_seg
;
4316 /* Try to ensure constant immediates are represented in the smallest
4321 char guess_suffix
= 0;
4325 guess_suffix
= i
.suffix
;
4326 else if (i
.reg_operands
)
4328 /* Figure out a suffix from the last register operand specified.
4329 We can't do this properly yet, ie. excluding InOutPortReg,
4330 but the following works for instructions with immediates.
4331 In any case, we can't set i.suffix yet. */
4332 for (op
= i
.operands
; --op
>= 0;)
4333 if (i
.types
[op
].bitfield
.reg8
)
4335 guess_suffix
= BYTE_MNEM_SUFFIX
;
4338 else if (i
.types
[op
].bitfield
.reg16
)
4340 guess_suffix
= WORD_MNEM_SUFFIX
;
4343 else if (i
.types
[op
].bitfield
.reg32
)
4345 guess_suffix
= LONG_MNEM_SUFFIX
;
4348 else if (i
.types
[op
].bitfield
.reg64
)
4350 guess_suffix
= QWORD_MNEM_SUFFIX
;
4354 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4355 guess_suffix
= WORD_MNEM_SUFFIX
;
4357 for (op
= i
.operands
; --op
>= 0;)
4358 if (operand_type_check (i
.types
[op
], imm
))
4360 switch (i
.op
[op
].imms
->X_op
)
4363 /* If a suffix is given, this operand may be shortened. */
4364 switch (guess_suffix
)
4366 case LONG_MNEM_SUFFIX
:
4367 i
.types
[op
].bitfield
.imm32
= 1;
4368 i
.types
[op
].bitfield
.imm64
= 1;
4370 case WORD_MNEM_SUFFIX
:
4371 i
.types
[op
].bitfield
.imm16
= 1;
4372 i
.types
[op
].bitfield
.imm32
= 1;
4373 i
.types
[op
].bitfield
.imm32s
= 1;
4374 i
.types
[op
].bitfield
.imm64
= 1;
4376 case BYTE_MNEM_SUFFIX
:
4377 i
.types
[op
].bitfield
.imm8
= 1;
4378 i
.types
[op
].bitfield
.imm8s
= 1;
4379 i
.types
[op
].bitfield
.imm16
= 1;
4380 i
.types
[op
].bitfield
.imm32
= 1;
4381 i
.types
[op
].bitfield
.imm32s
= 1;
4382 i
.types
[op
].bitfield
.imm64
= 1;
4386 /* If this operand is at most 16 bits, convert it
4387 to a signed 16 bit number before trying to see
4388 whether it will fit in an even smaller size.
4389 This allows a 16-bit operand such as $0xffe0 to
4390 be recognised as within Imm8S range. */
4391 if ((i
.types
[op
].bitfield
.imm16
)
4392 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4394 i
.op
[op
].imms
->X_add_number
=
4395 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4398 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4399 if ((i
.types
[op
].bitfield
.imm32
)
4400 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4403 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4404 ^ ((offsetT
) 1 << 31))
4405 - ((offsetT
) 1 << 31));
4409 = operand_type_or (i
.types
[op
],
4410 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4412 /* We must avoid matching of Imm32 templates when 64bit
4413 only immediate is available. */
4414 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4415 i
.types
[op
].bitfield
.imm32
= 0;
4422 /* Symbols and expressions. */
4424 /* Convert symbolic operand to proper sizes for matching, but don't
4425 prevent matching a set of insns that only supports sizes other
4426 than those matching the insn suffix. */
4428 i386_operand_type mask
, allowed
;
4429 const insn_template
*t
;
4431 operand_type_set (&mask
, 0);
4432 operand_type_set (&allowed
, 0);
4434 for (t
= current_templates
->start
;
4435 t
< current_templates
->end
;
4437 allowed
= operand_type_or (allowed
,
4438 t
->operand_types
[op
]);
4439 switch (guess_suffix
)
4441 case QWORD_MNEM_SUFFIX
:
4442 mask
.bitfield
.imm64
= 1;
4443 mask
.bitfield
.imm32s
= 1;
4445 case LONG_MNEM_SUFFIX
:
4446 mask
.bitfield
.imm32
= 1;
4448 case WORD_MNEM_SUFFIX
:
4449 mask
.bitfield
.imm16
= 1;
4451 case BYTE_MNEM_SUFFIX
:
4452 mask
.bitfield
.imm8
= 1;
4457 allowed
= operand_type_and (mask
, allowed
);
4458 if (!operand_type_all_zero (&allowed
))
4459 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4466 /* Try to use the smallest displacement type too. */
4468 optimize_disp (void)
4472 for (op
= i
.operands
; --op
>= 0;)
4473 if (operand_type_check (i
.types
[op
], disp
))
4475 if (i
.op
[op
].disps
->X_op
== O_constant
)
4477 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4479 if (i
.types
[op
].bitfield
.disp16
4480 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4482 /* If this operand is at most 16 bits, convert
4483 to a signed 16 bit number and don't use 64bit
4485 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4486 i
.types
[op
].bitfield
.disp64
= 0;
4489 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4490 if (i
.types
[op
].bitfield
.disp32
4491 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4493 /* If this operand is at most 32 bits, convert
4494 to a signed 32 bit number and don't use 64bit
4496 op_disp
&= (((offsetT
) 2 << 31) - 1);
4497 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4498 i
.types
[op
].bitfield
.disp64
= 0;
4501 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4503 i
.types
[op
].bitfield
.disp8
= 0;
4504 i
.types
[op
].bitfield
.disp16
= 0;
4505 i
.types
[op
].bitfield
.disp32
= 0;
4506 i
.types
[op
].bitfield
.disp32s
= 0;
4507 i
.types
[op
].bitfield
.disp64
= 0;
4511 else if (flag_code
== CODE_64BIT
)
4513 if (fits_in_signed_long (op_disp
))
4515 i
.types
[op
].bitfield
.disp64
= 0;
4516 i
.types
[op
].bitfield
.disp32s
= 1;
4518 if (i
.prefix
[ADDR_PREFIX
]
4519 && fits_in_unsigned_long (op_disp
))
4520 i
.types
[op
].bitfield
.disp32
= 1;
4522 if ((i
.types
[op
].bitfield
.disp32
4523 || i
.types
[op
].bitfield
.disp32s
4524 || i
.types
[op
].bitfield
.disp16
)
4525 && fits_in_signed_byte (op_disp
))
4526 i
.types
[op
].bitfield
.disp8
= 1;
4528 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4529 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4531 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4532 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4533 i
.types
[op
].bitfield
.disp8
= 0;
4534 i
.types
[op
].bitfield
.disp16
= 0;
4535 i
.types
[op
].bitfield
.disp32
= 0;
4536 i
.types
[op
].bitfield
.disp32s
= 0;
4537 i
.types
[op
].bitfield
.disp64
= 0;
4540 /* We only support 64bit displacement on constants. */
4541 i
.types
[op
].bitfield
.disp64
= 0;
4545 /* Check if operands are valid for the instruction. */
4548 check_VecOperands (const insn_template
*t
)
4552 /* Without VSIB byte, we can't have a vector register for index. */
4553 if (!t
->opcode_modifier
.vecsib
4555 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4556 || i
.index_reg
->reg_type
.bitfield
.regymm
4557 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4559 i
.error
= unsupported_vector_index_register
;
4563 /* Check if default mask is allowed. */
4564 if (t
->opcode_modifier
.nodefmask
4565 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4567 i
.error
= no_default_mask
;
4571 /* For VSIB byte, we need a vector register for index, and all vector
4572 registers must be distinct. */
4573 if (t
->opcode_modifier
.vecsib
)
4576 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4577 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4578 || (t
->opcode_modifier
.vecsib
== VecSIB256
4579 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4580 || (t
->opcode_modifier
.vecsib
== VecSIB512
4581 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4583 i
.error
= invalid_vsib_address
;
4587 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4588 if (i
.reg_operands
== 2 && !i
.mask
)
4590 gas_assert (i
.types
[0].bitfield
.regxmm
4591 || i
.types
[0].bitfield
.regymm
);
4592 gas_assert (i
.types
[2].bitfield
.regxmm
4593 || i
.types
[2].bitfield
.regymm
);
4594 if (operand_check
== check_none
)
4596 if (register_number (i
.op
[0].regs
)
4597 != register_number (i
.index_reg
)
4598 && register_number (i
.op
[2].regs
)
4599 != register_number (i
.index_reg
)
4600 && register_number (i
.op
[0].regs
)
4601 != register_number (i
.op
[2].regs
))
4603 if (operand_check
== check_error
)
4605 i
.error
= invalid_vector_register_set
;
4608 as_warn (_("mask, index, and destination registers should be distinct"));
4610 else if (i
.reg_operands
== 1 && i
.mask
)
4612 if ((i
.types
[1].bitfield
.regymm
4613 || i
.types
[1].bitfield
.regzmm
)
4614 && (register_number (i
.op
[1].regs
)
4615 == register_number (i
.index_reg
)))
4617 if (operand_check
== check_error
)
4619 i
.error
= invalid_vector_register_set
;
4622 if (operand_check
!= check_none
)
4623 as_warn (_("index and destination registers should be distinct"));
4628 /* Check if broadcast is supported by the instruction and is applied
4629 to the memory operand. */
4632 int broadcasted_opnd_size
;
4634 /* Check if specified broadcast is supported in this instruction,
4635 and it's applied to memory operand of DWORD or QWORD type,
4636 depending on VecESize. */
4637 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4638 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4639 || (t
->opcode_modifier
.vecesize
== 0
4640 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4641 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4642 || (t
->opcode_modifier
.vecesize
== 1
4643 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4644 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4647 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4648 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4649 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4650 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4651 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4652 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4653 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4654 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4655 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4659 if ((broadcasted_opnd_size
== 256
4660 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4661 || (broadcasted_opnd_size
== 512
4662 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4665 i
.error
= unsupported_broadcast
;
4669 /* If broadcast is supported in this instruction, we need to check if
4670 operand of one-element size isn't specified without broadcast. */
4671 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4673 /* Find memory operand. */
4674 for (op
= 0; op
< i
.operands
; op
++)
4675 if (operand_type_check (i
.types
[op
], anymem
))
4677 gas_assert (op
< i
.operands
);
4678 /* Check size of the memory operand. */
4679 if ((t
->opcode_modifier
.vecesize
== 0
4680 && i
.types
[op
].bitfield
.dword
)
4681 || (t
->opcode_modifier
.vecesize
== 1
4682 && i
.types
[op
].bitfield
.qword
))
4684 i
.error
= broadcast_needed
;
4689 /* Check if requested masking is supported. */
4691 && (!t
->opcode_modifier
.masking
4693 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4695 i
.error
= unsupported_masking
;
4699 /* Check if masking is applied to dest operand. */
4700 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4702 i
.error
= mask_not_on_destination
;
4709 if ((i
.rounding
->type
!= saeonly
4710 && !t
->opcode_modifier
.staticrounding
)
4711 || (i
.rounding
->type
== saeonly
4712 && (t
->opcode_modifier
.staticrounding
4713 || !t
->opcode_modifier
.sae
)))
4715 i
.error
= unsupported_rc_sae
;
4718 /* If the instruction has several immediate operands and one of
4719 them is rounding, the rounding operand should be the last
4720 immediate operand. */
4721 if (i
.imm_operands
> 1
4722 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4724 i
.error
= rc_sae_operand_not_last_imm
;
4729 /* Check vector Disp8 operand. */
4730 if (t
->opcode_modifier
.disp8memshift
)
4733 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4735 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4737 for (op
= 0; op
< i
.operands
; op
++)
4738 if (operand_type_check (i
.types
[op
], disp
)
4739 && i
.op
[op
].disps
->X_op
== O_constant
)
4741 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4743 = (i
.disp_encoding
!= disp_encoding_32bit
4744 && fits_in_vec_disp8 (value
));
4745 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4748 i
.types
[op
].bitfield
.vec_disp8
= 1;
4751 /* Vector insn can only have Vec_Disp8/Disp32 in
4752 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4754 i
.types
[op
].bitfield
.disp8
= 0;
4755 if (flag_code
!= CODE_16BIT
)
4756 i
.types
[op
].bitfield
.disp16
= 0;
4759 else if (flag_code
!= CODE_16BIT
)
4761 /* One form of this instruction supports vector Disp8.
4762 Try vector Disp8 if we need to use Disp32. */
4763 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4765 i
.error
= try_vector_disp8
;
4777 /* Check if operands are valid for the instruction. Update VEX
4781 VEX_check_operands (const insn_template
*t
)
4783 if (i
.vec_encoding
== vex_encoding_evex
)
4785 /* This instruction must be encoded with EVEX prefix. */
4786 if (!t
->opcode_modifier
.evex
)
4788 i
.error
= unsupported
;
4794 if (!t
->opcode_modifier
.vex
)
4796 /* This instruction template doesn't have VEX prefix. */
4797 if (i
.vec_encoding
!= vex_encoding_default
)
4799 i
.error
= unsupported
;
4805 /* Only check VEX_Imm4, which must be the first operand. */
4806 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4808 if (i
.op
[0].imms
->X_op
!= O_constant
4809 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4815 /* Turn off Imm8 so that update_imm won't complain. */
4816 i
.types
[0] = vec_imm4
;
4822 static const insn_template
*
4823 match_template (char mnem_suffix
)
4825 /* Points to template once we've found it. */
4826 const insn_template
*t
;
4827 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4828 i386_operand_type overlap4
;
4829 unsigned int found_reverse_match
;
4830 i386_opcode_modifier suffix_check
, mnemsuf_check
;
4831 i386_operand_type operand_types
[MAX_OPERANDS
];
4832 int addr_prefix_disp
;
4834 unsigned int found_cpu_match
;
4835 unsigned int check_register
;
4836 enum i386_error specific_error
= 0;
4838 #if MAX_OPERANDS != 5
4839 # error "MAX_OPERANDS must be 5."
4842 found_reverse_match
= 0;
4843 addr_prefix_disp
= -1;
4845 memset (&suffix_check
, 0, sizeof (suffix_check
));
4846 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4847 suffix_check
.no_bsuf
= 1;
4848 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4849 suffix_check
.no_wsuf
= 1;
4850 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4851 suffix_check
.no_ssuf
= 1;
4852 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4853 suffix_check
.no_lsuf
= 1;
4854 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4855 suffix_check
.no_qsuf
= 1;
4856 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4857 suffix_check
.no_ldsuf
= 1;
4859 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
4862 switch (mnem_suffix
)
4864 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
4865 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
4866 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
4867 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
4868 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
4872 /* Must have right number of operands. */
4873 i
.error
= number_of_operands_mismatch
;
4875 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4877 addr_prefix_disp
= -1;
4879 if (i
.operands
!= t
->operands
)
4882 /* Check processor support. */
4883 i
.error
= unsupported
;
4884 found_cpu_match
= (cpu_flags_match (t
)
4885 == CPU_FLAGS_PERFECT_MATCH
);
4886 if (!found_cpu_match
)
4889 /* Check old gcc support. */
4890 i
.error
= old_gcc_only
;
4891 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4894 /* Check AT&T mnemonic. */
4895 i
.error
= unsupported_with_intel_mnemonic
;
4896 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4899 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
4900 i
.error
= unsupported_syntax
;
4901 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4902 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
4903 || (intel64
&& t
->opcode_modifier
.amd64
)
4904 || (!intel64
&& t
->opcode_modifier
.intel64
))
4907 /* Check the suffix, except for some instructions in intel mode. */
4908 i
.error
= invalid_instruction_suffix
;
4909 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4910 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4911 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4912 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4913 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4914 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4915 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4917 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4918 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
4919 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
4920 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
4921 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
4922 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
4923 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
4926 if (!operand_size_match (t
))
4929 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4930 operand_types
[j
] = t
->operand_types
[j
];
4932 /* In general, don't allow 64-bit operands in 32-bit mode. */
4933 if (i
.suffix
== QWORD_MNEM_SUFFIX
4934 && flag_code
!= CODE_64BIT
4936 ? (!t
->opcode_modifier
.ignoresize
4937 && !intel_float_operand (t
->name
))
4938 : intel_float_operand (t
->name
) != 2)
4939 && ((!operand_types
[0].bitfield
.regmmx
4940 && !operand_types
[0].bitfield
.regxmm
4941 && !operand_types
[0].bitfield
.regymm
4942 && !operand_types
[0].bitfield
.regzmm
)
4943 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4944 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4945 && operand_types
[t
->operands
> 1].bitfield
.regymm
4946 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4947 && (t
->base_opcode
!= 0x0fc7
4948 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4951 /* In general, don't allow 32-bit operands on pre-386. */
4952 else if (i
.suffix
== LONG_MNEM_SUFFIX
4953 && !cpu_arch_flags
.bitfield
.cpui386
4955 ? (!t
->opcode_modifier
.ignoresize
4956 && !intel_float_operand (t
->name
))
4957 : intel_float_operand (t
->name
) != 2)
4958 && ((!operand_types
[0].bitfield
.regmmx
4959 && !operand_types
[0].bitfield
.regxmm
)
4960 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4961 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4964 /* Do not verify operands when there are none. */
4968 /* We've found a match; break out of loop. */
4972 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4973 into Disp32/Disp16/Disp32 operand. */
4974 if (i
.prefix
[ADDR_PREFIX
] != 0)
4976 /* There should be only one Disp operand. */
4980 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4982 if (operand_types
[j
].bitfield
.disp16
)
4984 addr_prefix_disp
= j
;
4985 operand_types
[j
].bitfield
.disp32
= 1;
4986 operand_types
[j
].bitfield
.disp16
= 0;
4992 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4994 if (operand_types
[j
].bitfield
.disp32
)
4996 addr_prefix_disp
= j
;
4997 operand_types
[j
].bitfield
.disp32
= 0;
4998 operand_types
[j
].bitfield
.disp16
= 1;
5004 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5006 if (operand_types
[j
].bitfield
.disp64
)
5008 addr_prefix_disp
= j
;
5009 operand_types
[j
].bitfield
.disp64
= 0;
5010 operand_types
[j
].bitfield
.disp32
= 1;
5018 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5019 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5022 /* We check register size if needed. */
5023 check_register
= t
->opcode_modifier
.checkregsize
;
5024 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5025 switch (t
->operands
)
5028 if (!operand_type_match (overlap0
, i
.types
[0]))
5032 /* xchg %eax, %eax is a special case. It is an alias for nop
5033 only in 32bit mode and we can use opcode 0x90. In 64bit
5034 mode, we can't use 0x90 for xchg %eax, %eax since it should
5035 zero-extend %eax to %rax. */
5036 if (flag_code
== CODE_64BIT
5037 && t
->base_opcode
== 0x90
5038 && operand_type_equal (&i
.types
[0], &acc32
)
5039 && operand_type_equal (&i
.types
[1], &acc32
))
5041 /* If we want store form, we reverse direction of operands. */
5042 if (i
.dir_encoding
== dir_encoding_store
5043 && t
->opcode_modifier
.d
)
5048 /* If we want store form, we skip the current load. */
5049 if (i
.dir_encoding
== dir_encoding_store
5050 && i
.mem_operands
== 0
5051 && t
->opcode_modifier
.load
)
5056 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5057 if (!operand_type_match (overlap0
, i
.types
[0])
5058 || !operand_type_match (overlap1
, i
.types
[1])
5060 && !operand_type_register_match (overlap0
, i
.types
[0],
5062 overlap1
, i
.types
[1],
5065 /* Check if other direction is valid ... */
5066 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
5070 /* Try reversing direction of operands. */
5071 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
5072 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
5073 if (!operand_type_match (overlap0
, i
.types
[0])
5074 || !operand_type_match (overlap1
, i
.types
[1])
5076 && !operand_type_register_match (overlap0
,
5083 /* Does not match either direction. */
5086 /* found_reverse_match holds which of D or FloatDR
5088 if (t
->opcode_modifier
.d
)
5089 found_reverse_match
= Opcode_D
;
5090 else if (t
->opcode_modifier
.floatd
)
5091 found_reverse_match
= Opcode_FloatD
;
5093 found_reverse_match
= 0;
5094 if (t
->opcode_modifier
.floatr
)
5095 found_reverse_match
|= Opcode_FloatR
;
5099 /* Found a forward 2 operand match here. */
5100 switch (t
->operands
)
5103 overlap4
= operand_type_and (i
.types
[4],
5107 overlap3
= operand_type_and (i
.types
[3],
5111 overlap2
= operand_type_and (i
.types
[2],
5116 switch (t
->operands
)
5119 if (!operand_type_match (overlap4
, i
.types
[4])
5120 || !operand_type_register_match (overlap3
,
5129 if (!operand_type_match (overlap3
, i
.types
[3])
5131 && !operand_type_register_match (overlap2
,
5140 /* Here we make use of the fact that there are no
5141 reverse match 3 operand instructions, and all 3
5142 operand instructions only need to be checked for
5143 register consistency between operands 2 and 3. */
5144 if (!operand_type_match (overlap2
, i
.types
[2])
5146 && !operand_type_register_match (overlap1
,
5156 /* Found either forward/reverse 2, 3 or 4 operand match here:
5157 slip through to break. */
5159 if (!found_cpu_match
)
5161 found_reverse_match
= 0;
5165 /* Check if vector and VEX operands are valid. */
5166 if (check_VecOperands (t
) || VEX_check_operands (t
))
5168 specific_error
= i
.error
;
5172 /* We've found a match; break out of loop. */
5176 if (t
== current_templates
->end
)
5178 /* We found no match. */
5179 const char *err_msg
;
5180 switch (specific_error
? specific_error
: i
.error
)
5184 case operand_size_mismatch
:
5185 err_msg
= _("operand size mismatch");
5187 case operand_type_mismatch
:
5188 err_msg
= _("operand type mismatch");
5190 case register_type_mismatch
:
5191 err_msg
= _("register type mismatch");
5193 case number_of_operands_mismatch
:
5194 err_msg
= _("number of operands mismatch");
5196 case invalid_instruction_suffix
:
5197 err_msg
= _("invalid instruction suffix");
5200 err_msg
= _("constant doesn't fit in 4 bits");
5203 err_msg
= _("only supported with old gcc");
5205 case unsupported_with_intel_mnemonic
:
5206 err_msg
= _("unsupported with Intel mnemonic");
5208 case unsupported_syntax
:
5209 err_msg
= _("unsupported syntax");
5212 as_bad (_("unsupported instruction `%s'"),
5213 current_templates
->start
->name
);
5215 case invalid_vsib_address
:
5216 err_msg
= _("invalid VSIB address");
5218 case invalid_vector_register_set
:
5219 err_msg
= _("mask, index, and destination registers must be distinct");
5221 case unsupported_vector_index_register
:
5222 err_msg
= _("unsupported vector index register");
5224 case unsupported_broadcast
:
5225 err_msg
= _("unsupported broadcast");
5227 case broadcast_not_on_src_operand
:
5228 err_msg
= _("broadcast not on source memory operand");
5230 case broadcast_needed
:
5231 err_msg
= _("broadcast is needed for operand of such type");
5233 case unsupported_masking
:
5234 err_msg
= _("unsupported masking");
5236 case mask_not_on_destination
:
5237 err_msg
= _("mask not on destination operand");
5239 case no_default_mask
:
5240 err_msg
= _("default mask isn't allowed");
5242 case unsupported_rc_sae
:
5243 err_msg
= _("unsupported static rounding/sae");
5245 case rc_sae_operand_not_last_imm
:
5247 err_msg
= _("RC/SAE operand must precede immediate operands");
5249 err_msg
= _("RC/SAE operand must follow immediate operands");
5251 case invalid_register_operand
:
5252 err_msg
= _("invalid register operand");
5255 as_bad (_("%s for `%s'"), err_msg
,
5256 current_templates
->start
->name
);
5260 if (!quiet_warnings
)
5263 && (i
.types
[0].bitfield
.jumpabsolute
5264 != operand_types
[0].bitfield
.jumpabsolute
))
5266 as_warn (_("indirect %s without `*'"), t
->name
);
5269 if (t
->opcode_modifier
.isprefix
5270 && t
->opcode_modifier
.ignoresize
)
5272 /* Warn them that a data or address size prefix doesn't
5273 affect assembly of the next line of code. */
5274 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5278 /* Copy the template we found. */
5281 if (addr_prefix_disp
!= -1)
5282 i
.tm
.operand_types
[addr_prefix_disp
]
5283 = operand_types
[addr_prefix_disp
];
5285 if (found_reverse_match
)
5287 /* If we found a reverse match we must alter the opcode
5288 direction bit. found_reverse_match holds bits to change
5289 (different for int & float insns). */
5291 i
.tm
.base_opcode
^= found_reverse_match
;
5293 i
.tm
.operand_types
[0] = operand_types
[1];
5294 i
.tm
.operand_types
[1] = operand_types
[0];
5303 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5304 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5306 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5308 as_bad (_("`%s' operand %d must use `%ses' segment"),
5314 /* There's only ever one segment override allowed per instruction.
5315 This instruction possibly has a legal segment override on the
5316 second operand, so copy the segment to where non-string
5317 instructions store it, allowing common code. */
5318 i
.seg
[0] = i
.seg
[1];
5320 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5322 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5324 as_bad (_("`%s' operand %d must use `%ses' segment"),
5335 process_suffix (void)
5337 /* If matched instruction specifies an explicit instruction mnemonic
5339 if (i
.tm
.opcode_modifier
.size16
)
5340 i
.suffix
= WORD_MNEM_SUFFIX
;
5341 else if (i
.tm
.opcode_modifier
.size32
)
5342 i
.suffix
= LONG_MNEM_SUFFIX
;
5343 else if (i
.tm
.opcode_modifier
.size64
)
5344 i
.suffix
= QWORD_MNEM_SUFFIX
;
5345 else if (i
.reg_operands
)
5347 /* If there's no instruction mnemonic suffix we try to invent one
5348 based on register operands. */
5351 /* We take i.suffix from the last register operand specified,
5352 Destination register type is more significant than source
5353 register type. crc32 in SSE4.2 prefers source register
5355 if (i
.tm
.base_opcode
== 0xf20f38f1)
5357 if (i
.types
[0].bitfield
.reg16
)
5358 i
.suffix
= WORD_MNEM_SUFFIX
;
5359 else if (i
.types
[0].bitfield
.reg32
)
5360 i
.suffix
= LONG_MNEM_SUFFIX
;
5361 else if (i
.types
[0].bitfield
.reg64
)
5362 i
.suffix
= QWORD_MNEM_SUFFIX
;
5364 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5366 if (i
.types
[0].bitfield
.reg8
)
5367 i
.suffix
= BYTE_MNEM_SUFFIX
;
5374 if (i
.tm
.base_opcode
== 0xf20f38f1
5375 || i
.tm
.base_opcode
== 0xf20f38f0)
5377 /* We have to know the operand size for crc32. */
5378 as_bad (_("ambiguous memory operand size for `%s`"),
5383 for (op
= i
.operands
; --op
>= 0;)
5384 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5386 if (i
.types
[op
].bitfield
.reg8
)
5388 i
.suffix
= BYTE_MNEM_SUFFIX
;
5391 else if (i
.types
[op
].bitfield
.reg16
)
5393 i
.suffix
= WORD_MNEM_SUFFIX
;
5396 else if (i
.types
[op
].bitfield
.reg32
)
5398 i
.suffix
= LONG_MNEM_SUFFIX
;
5401 else if (i
.types
[op
].bitfield
.reg64
)
5403 i
.suffix
= QWORD_MNEM_SUFFIX
;
5409 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5412 && i
.tm
.opcode_modifier
.ignoresize
5413 && i
.tm
.opcode_modifier
.no_bsuf
)
5415 else if (!check_byte_reg ())
5418 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5421 && i
.tm
.opcode_modifier
.ignoresize
5422 && i
.tm
.opcode_modifier
.no_lsuf
)
5424 else if (!check_long_reg ())
5427 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5430 && i
.tm
.opcode_modifier
.ignoresize
5431 && i
.tm
.opcode_modifier
.no_qsuf
)
5433 else if (!check_qword_reg ())
5436 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5439 && i
.tm
.opcode_modifier
.ignoresize
5440 && i
.tm
.opcode_modifier
.no_wsuf
)
5442 else if (!check_word_reg ())
5445 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5446 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5447 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5449 /* Skip if the instruction has x/y/z suffix. match_template
5450 should check if it is a valid suffix. */
5452 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5453 /* Do nothing if the instruction is going to ignore the prefix. */
5458 else if (i
.tm
.opcode_modifier
.defaultsize
5460 /* exclude fldenv/frstor/fsave/fstenv */
5461 && i
.tm
.opcode_modifier
.no_ssuf
)
5463 i
.suffix
= stackop_size
;
5465 else if (intel_syntax
5467 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5468 || i
.tm
.opcode_modifier
.jumpbyte
5469 || i
.tm
.opcode_modifier
.jumpintersegment
5470 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5471 && i
.tm
.extension_opcode
<= 3)))
5476 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5478 i
.suffix
= QWORD_MNEM_SUFFIX
;
5483 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5484 i
.suffix
= LONG_MNEM_SUFFIX
;
5487 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5488 i
.suffix
= WORD_MNEM_SUFFIX
;
5497 if (i
.tm
.opcode_modifier
.w
)
5499 as_bad (_("no instruction mnemonic suffix given and "
5500 "no register operands; can't size instruction"));
5506 unsigned int suffixes
;
5508 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5509 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5511 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5513 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5515 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5517 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5520 /* There are more than suffix matches. */
5521 if (i
.tm
.opcode_modifier
.w
5522 || ((suffixes
& (suffixes
- 1))
5523 && !i
.tm
.opcode_modifier
.defaultsize
5524 && !i
.tm
.opcode_modifier
.ignoresize
))
5526 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5532 /* Change the opcode based on the operand size given by i.suffix;
5533 We don't need to change things for byte insns. */
5536 && i
.suffix
!= BYTE_MNEM_SUFFIX
5537 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5538 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5539 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5541 /* It's not a byte, select word/dword operation. */
5542 if (i
.tm
.opcode_modifier
.w
)
5544 if (i
.tm
.opcode_modifier
.shortform
)
5545 i
.tm
.base_opcode
|= 8;
5547 i
.tm
.base_opcode
|= 1;
5550 /* Now select between word & dword operations via the operand
5551 size prefix, except for instructions that will ignore this
5553 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5555 /* The address size override prefix changes the size of the
5557 if ((flag_code
== CODE_32BIT
5558 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5559 || (flag_code
!= CODE_32BIT
5560 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5561 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5564 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5565 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5566 && !i
.tm
.opcode_modifier
.ignoresize
5567 && !i
.tm
.opcode_modifier
.floatmf
5568 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5569 || (flag_code
== CODE_64BIT
5570 && i
.tm
.opcode_modifier
.jumpbyte
)))
5572 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5574 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5575 prefix
= ADDR_PREFIX_OPCODE
;
5577 if (!add_prefix (prefix
))
5581 /* Set mode64 for an operand. */
5582 if (i
.suffix
== QWORD_MNEM_SUFFIX
5583 && flag_code
== CODE_64BIT
5584 && !i
.tm
.opcode_modifier
.norex64
)
5586 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5587 need rex64. cmpxchg8b is also a special case. */
5588 if (! (i
.operands
== 2
5589 && i
.tm
.base_opcode
== 0x90
5590 && i
.tm
.extension_opcode
== None
5591 && operand_type_equal (&i
.types
[0], &acc64
)
5592 && operand_type_equal (&i
.types
[1], &acc64
))
5593 && ! (i
.operands
== 1
5594 && i
.tm
.base_opcode
== 0xfc7
5595 && i
.tm
.extension_opcode
== 1
5596 && !operand_type_check (i
.types
[0], reg
)
5597 && operand_type_check (i
.types
[0], anymem
)))
5601 /* Size floating point instruction. */
5602 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5603 if (i
.tm
.opcode_modifier
.floatmf
)
5604 i
.tm
.base_opcode
^= 4;
5611 check_byte_reg (void)
5615 for (op
= i
.operands
; --op
>= 0;)
5617 /* If this is an eight bit register, it's OK. If it's the 16 or
5618 32 bit version of an eight bit register, we will just use the
5619 low portion, and that's OK too. */
5620 if (i
.types
[op
].bitfield
.reg8
)
5623 /* I/O port address operands are OK too. */
5624 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5627 /* crc32 doesn't generate this warning. */
5628 if (i
.tm
.base_opcode
== 0xf20f38f0)
5631 if ((i
.types
[op
].bitfield
.reg16
5632 || i
.types
[op
].bitfield
.reg32
5633 || i
.types
[op
].bitfield
.reg64
)
5634 && i
.op
[op
].regs
->reg_num
< 4
5635 /* Prohibit these changes in 64bit mode, since the lowering
5636 would be more complicated. */
5637 && flag_code
!= CODE_64BIT
)
5639 #if REGISTER_WARNINGS
5640 if (!quiet_warnings
)
5641 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5643 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5644 ? REGNAM_AL
- REGNAM_AX
5645 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5647 i
.op
[op
].regs
->reg_name
,
5652 /* Any other register is bad. */
5653 if (i
.types
[op
].bitfield
.reg16
5654 || i
.types
[op
].bitfield
.reg32
5655 || i
.types
[op
].bitfield
.reg64
5656 || i
.types
[op
].bitfield
.regmmx
5657 || i
.types
[op
].bitfield
.regxmm
5658 || i
.types
[op
].bitfield
.regymm
5659 || i
.types
[op
].bitfield
.regzmm
5660 || i
.types
[op
].bitfield
.sreg2
5661 || i
.types
[op
].bitfield
.sreg3
5662 || i
.types
[op
].bitfield
.control
5663 || i
.types
[op
].bitfield
.debug
5664 || i
.types
[op
].bitfield
.test
5665 || i
.types
[op
].bitfield
.floatreg
5666 || i
.types
[op
].bitfield
.floatacc
)
5668 as_bad (_("`%s%s' not allowed with `%s%c'"),
5670 i
.op
[op
].regs
->reg_name
,
5680 check_long_reg (void)
5684 for (op
= i
.operands
; --op
>= 0;)
5685 /* Reject eight bit registers, except where the template requires
5686 them. (eg. movzb) */
5687 if (i
.types
[op
].bitfield
.reg8
5688 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5689 || i
.tm
.operand_types
[op
].bitfield
.reg32
5690 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5692 as_bad (_("`%s%s' not allowed with `%s%c'"),
5694 i
.op
[op
].regs
->reg_name
,
5699 /* Warn if the e prefix on a general reg is missing. */
5700 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5701 && i
.types
[op
].bitfield
.reg16
5702 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5703 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5705 /* Prohibit these changes in the 64bit mode, since the
5706 lowering is more complicated. */
5707 if (flag_code
== CODE_64BIT
)
5709 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5710 register_prefix
, i
.op
[op
].regs
->reg_name
,
5714 #if REGISTER_WARNINGS
5715 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5717 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5718 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5721 /* Warn if the r prefix on a general reg is present. */
5722 else if (i
.types
[op
].bitfield
.reg64
5723 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5724 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5727 && i
.tm
.opcode_modifier
.toqword
5728 && !i
.types
[0].bitfield
.regxmm
)
5730 /* Convert to QWORD. We want REX byte. */
5731 i
.suffix
= QWORD_MNEM_SUFFIX
;
5735 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5736 register_prefix
, i
.op
[op
].regs
->reg_name
,
5745 check_qword_reg (void)
5749 for (op
= i
.operands
; --op
>= 0; )
5750 /* Reject eight bit registers, except where the template requires
5751 them. (eg. movzb) */
5752 if (i
.types
[op
].bitfield
.reg8
5753 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5754 || i
.tm
.operand_types
[op
].bitfield
.reg32
5755 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5757 as_bad (_("`%s%s' not allowed with `%s%c'"),
5759 i
.op
[op
].regs
->reg_name
,
5764 /* Warn if the r prefix on a general reg is missing. */
5765 else if ((i
.types
[op
].bitfield
.reg16
5766 || i
.types
[op
].bitfield
.reg32
)
5767 && (i
.tm
.operand_types
[op
].bitfield
.reg64
5768 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5770 /* Prohibit these changes in the 64bit mode, since the
5771 lowering is more complicated. */
5773 && i
.tm
.opcode_modifier
.todword
5774 && !i
.types
[0].bitfield
.regxmm
)
5776 /* Convert to DWORD. We don't want REX byte. */
5777 i
.suffix
= LONG_MNEM_SUFFIX
;
5781 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5782 register_prefix
, i
.op
[op
].regs
->reg_name
,
5791 check_word_reg (void)
5794 for (op
= i
.operands
; --op
>= 0;)
5795 /* Reject eight bit registers, except where the template requires
5796 them. (eg. movzb) */
5797 if (i
.types
[op
].bitfield
.reg8
5798 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5799 || i
.tm
.operand_types
[op
].bitfield
.reg32
5800 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5802 as_bad (_("`%s%s' not allowed with `%s%c'"),
5804 i
.op
[op
].regs
->reg_name
,
5809 /* Warn if the e or r prefix on a general reg is present. */
5810 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5811 && (i
.types
[op
].bitfield
.reg32
5812 || i
.types
[op
].bitfield
.reg64
)
5813 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5814 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5816 /* Prohibit these changes in the 64bit mode, since the
5817 lowering is more complicated. */
5818 if (flag_code
== CODE_64BIT
)
5820 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5821 register_prefix
, i
.op
[op
].regs
->reg_name
,
5825 #if REGISTER_WARNINGS
5826 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5828 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5829 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5836 update_imm (unsigned int j
)
5838 i386_operand_type overlap
= i
.types
[j
];
5839 if ((overlap
.bitfield
.imm8
5840 || overlap
.bitfield
.imm8s
5841 || overlap
.bitfield
.imm16
5842 || overlap
.bitfield
.imm32
5843 || overlap
.bitfield
.imm32s
5844 || overlap
.bitfield
.imm64
)
5845 && !operand_type_equal (&overlap
, &imm8
)
5846 && !operand_type_equal (&overlap
, &imm8s
)
5847 && !operand_type_equal (&overlap
, &imm16
)
5848 && !operand_type_equal (&overlap
, &imm32
)
5849 && !operand_type_equal (&overlap
, &imm32s
)
5850 && !operand_type_equal (&overlap
, &imm64
))
5854 i386_operand_type temp
;
5856 operand_type_set (&temp
, 0);
5857 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5859 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5860 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5862 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5863 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5864 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5866 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5867 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5870 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5873 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5874 || operand_type_equal (&overlap
, &imm16_32
)
5875 || operand_type_equal (&overlap
, &imm16_32s
))
5877 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5882 if (!operand_type_equal (&overlap
, &imm8
)
5883 && !operand_type_equal (&overlap
, &imm8s
)
5884 && !operand_type_equal (&overlap
, &imm16
)
5885 && !operand_type_equal (&overlap
, &imm32
)
5886 && !operand_type_equal (&overlap
, &imm32s
)
5887 && !operand_type_equal (&overlap
, &imm64
))
5889 as_bad (_("no instruction mnemonic suffix given; "
5890 "can't determine immediate size"));
5894 i
.types
[j
] = overlap
;
5904 /* Update the first 2 immediate operands. */
5905 n
= i
.operands
> 2 ? 2 : i
.operands
;
5908 for (j
= 0; j
< n
; j
++)
5909 if (update_imm (j
) == 0)
5912 /* The 3rd operand can't be immediate operand. */
5913 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5920 bad_implicit_operand (int xmm
)
5922 const char *ireg
= xmm
? "xmm0" : "ymm0";
5925 as_bad (_("the last operand of `%s' must be `%s%s'"),
5926 i
.tm
.name
, register_prefix
, ireg
);
5928 as_bad (_("the first operand of `%s' must be `%s%s'"),
5929 i
.tm
.name
, register_prefix
, ireg
);
5934 process_operands (void)
5936 /* Default segment register this instruction will use for memory
5937 accesses. 0 means unknown. This is only for optimizing out
5938 unnecessary segment overrides. */
5939 const seg_entry
*default_seg
= 0;
5941 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5943 unsigned int dupl
= i
.operands
;
5944 unsigned int dest
= dupl
- 1;
5947 /* The destination must be an xmm register. */
5948 gas_assert (i
.reg_operands
5949 && MAX_OPERANDS
> dupl
5950 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5952 if (i
.tm
.opcode_modifier
.firstxmm0
)
5954 /* The first operand is implicit and must be xmm0. */
5955 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5956 if (register_number (i
.op
[0].regs
) != 0)
5957 return bad_implicit_operand (1);
5959 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5961 /* Keep xmm0 for instructions with VEX prefix and 3
5967 /* We remove the first xmm0 and keep the number of
5968 operands unchanged, which in fact duplicates the
5970 for (j
= 1; j
< i
.operands
; j
++)
5972 i
.op
[j
- 1] = i
.op
[j
];
5973 i
.types
[j
- 1] = i
.types
[j
];
5974 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5978 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5980 gas_assert ((MAX_OPERANDS
- 1) > dupl
5981 && (i
.tm
.opcode_modifier
.vexsources
5984 /* Add the implicit xmm0 for instructions with VEX prefix
5986 for (j
= i
.operands
; j
> 0; j
--)
5988 i
.op
[j
] = i
.op
[j
- 1];
5989 i
.types
[j
] = i
.types
[j
- 1];
5990 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5993 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5994 i
.types
[0] = regxmm
;
5995 i
.tm
.operand_types
[0] = regxmm
;
5998 i
.reg_operands
+= 2;
6003 i
.op
[dupl
] = i
.op
[dest
];
6004 i
.types
[dupl
] = i
.types
[dest
];
6005 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6014 i
.op
[dupl
] = i
.op
[dest
];
6015 i
.types
[dupl
] = i
.types
[dest
];
6016 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6019 if (i
.tm
.opcode_modifier
.immext
)
6022 else if (i
.tm
.opcode_modifier
.firstxmm0
)
6026 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
6027 gas_assert (i
.reg_operands
6028 && (operand_type_equal (&i
.types
[0], ®xmm
)
6029 || operand_type_equal (&i
.types
[0], ®ymm
)
6030 || operand_type_equal (&i
.types
[0], ®zmm
)));
6031 if (register_number (i
.op
[0].regs
) != 0)
6032 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
6034 for (j
= 1; j
< i
.operands
; j
++)
6036 i
.op
[j
- 1] = i
.op
[j
];
6037 i
.types
[j
- 1] = i
.types
[j
];
6039 /* We need to adjust fields in i.tm since they are used by
6040 build_modrm_byte. */
6041 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6048 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6050 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6051 gas_assert (i
.operands
>= 2
6052 && (operand_type_equal (&i
.types
[1], ®xmm
)
6053 || operand_type_equal (&i
.types
[1], ®ymm
)
6054 || operand_type_equal (&i
.types
[1], ®zmm
)));
6055 unsigned int regnum
= register_number (i
.op
[1].regs
);
6056 unsigned int first_reg_in_group
= regnum
& ~3;
6057 unsigned int last_reg_in_group
= first_reg_in_group
+ 3;
6058 if (regnum
!= first_reg_in_group
) {
6059 as_warn (_("the second source register `%s%s' implicitly denotes"
6060 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
6061 register_prefix
, i
.op
[1].regs
->reg_name
,
6062 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6063 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6067 else if (i
.tm
.opcode_modifier
.regkludge
)
6069 /* The imul $imm, %reg instruction is converted into
6070 imul $imm, %reg, %reg, and the clr %reg instruction
6071 is converted into xor %reg, %reg. */
6073 unsigned int first_reg_op
;
6075 if (operand_type_check (i
.types
[0], reg
))
6079 /* Pretend we saw the extra register operand. */
6080 gas_assert (i
.reg_operands
== 1
6081 && i
.op
[first_reg_op
+ 1].regs
== 0);
6082 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6083 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6088 if (i
.tm
.opcode_modifier
.shortform
)
6090 if (i
.types
[0].bitfield
.sreg2
6091 || i
.types
[0].bitfield
.sreg3
)
6093 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6094 && i
.op
[0].regs
->reg_num
== 1)
6096 as_bad (_("you can't `pop %scs'"), register_prefix
);
6099 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6100 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6105 /* The register or float register operand is in operand
6109 if (i
.types
[0].bitfield
.floatreg
6110 || operand_type_check (i
.types
[0], reg
))
6114 /* Register goes in low 3 bits of opcode. */
6115 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6116 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6118 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6120 /* Warn about some common errors, but press on regardless.
6121 The first case can be generated by gcc (<= 2.8.1). */
6122 if (i
.operands
== 2)
6124 /* Reversed arguments on faddp, fsubp, etc. */
6125 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6126 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6127 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6131 /* Extraneous `l' suffix on fp insn. */
6132 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6133 register_prefix
, i
.op
[0].regs
->reg_name
);
6138 else if (i
.tm
.opcode_modifier
.modrm
)
6140 /* The opcode is completed (modulo i.tm.extension_opcode which
6141 must be put into the modrm byte). Now, we make the modrm and
6142 index base bytes based on all the info we've collected. */
6144 default_seg
= build_modrm_byte ();
6146 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6150 else if (i
.tm
.opcode_modifier
.isstring
)
6152 /* For the string instructions that allow a segment override
6153 on one of their operands, the default segment is ds. */
6157 if (i
.tm
.base_opcode
== 0x8d /* lea */
6160 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6162 /* If a segment was explicitly specified, and the specified segment
6163 is not the default, use an opcode prefix to select it. If we
6164 never figured out what the default segment is, then default_seg
6165 will be zero at this point, and the specified segment prefix will
6167 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6169 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6175 static const seg_entry
*
6176 build_modrm_byte (void)
6178 const seg_entry
*default_seg
= 0;
6179 unsigned int source
, dest
;
6182 /* The first operand of instructions with VEX prefix and 3 sources
6183 must be VEX_Imm4. */
6184 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6187 unsigned int nds
, reg_slot
;
6190 if (i
.tm
.opcode_modifier
.veximmext
6191 && i
.tm
.opcode_modifier
.immext
)
6193 dest
= i
.operands
- 2;
6194 gas_assert (dest
== 3);
6197 dest
= i
.operands
- 1;
6200 /* There are 2 kinds of instructions:
6201 1. 5 operands: 4 register operands or 3 register operands
6202 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6203 VexW0 or VexW1. The destination must be either XMM, YMM or
6205 2. 4 operands: 4 register operands or 3 register operands
6206 plus 1 memory operand, VexXDS, and VexImmExt */
6207 gas_assert ((i
.reg_operands
== 4
6208 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6209 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6210 && (i
.tm
.opcode_modifier
.veximmext
6211 || (i
.imm_operands
== 1
6212 && i
.types
[0].bitfield
.vec_imm4
6213 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
6214 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6215 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
6216 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
6217 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
6219 if (i
.imm_operands
== 0)
6221 /* When there is no immediate operand, generate an 8bit
6222 immediate operand to encode the first operand. */
6223 exp
= &im_expressions
[i
.imm_operands
++];
6224 i
.op
[i
.operands
].imms
= exp
;
6225 i
.types
[i
.operands
] = imm8
;
6227 /* If VexW1 is set, the first operand is the source and
6228 the second operand is encoded in the immediate operand. */
6229 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6240 /* FMA swaps REG and NDS. */
6241 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6249 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6251 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6253 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6255 exp
->X_op
= O_constant
;
6256 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6257 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6261 unsigned int imm_slot
;
6263 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6265 /* If VexW0 is set, the third operand is the source and
6266 the second operand is encoded in the immediate
6273 /* VexW1 is set, the second operand is the source and
6274 the third operand is encoded in the immediate
6280 if (i
.tm
.opcode_modifier
.immext
)
6282 /* When ImmExt is set, the immediate byte is the last
6284 imm_slot
= i
.operands
- 1;
6292 /* Turn on Imm8 so that output_imm will generate it. */
6293 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6296 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6298 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6300 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6302 i
.op
[imm_slot
].imms
->X_add_number
6303 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6304 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6307 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6308 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6310 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6312 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6317 /* i.reg_operands MUST be the number of real register operands;
6318 implicit registers do not count. If there are 3 register
6319 operands, it must be a instruction with VexNDS. For a
6320 instruction with VexNDD, the destination register is encoded
6321 in VEX prefix. If there are 4 register operands, it must be
6322 a instruction with VEX prefix and 3 sources. */
6323 if (i
.mem_operands
== 0
6324 && ((i
.reg_operands
== 2
6325 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6326 || (i
.reg_operands
== 3
6327 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6328 || (i
.reg_operands
== 4 && vex_3_sources
)))
6336 /* When there are 3 operands, one of them may be immediate,
6337 which may be the first or the last operand. Otherwise,
6338 the first operand must be shift count register (cl) or it
6339 is an instruction with VexNDS. */
6340 gas_assert (i
.imm_operands
== 1
6341 || (i
.imm_operands
== 0
6342 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6343 || i
.types
[0].bitfield
.shiftcount
)));
6344 if (operand_type_check (i
.types
[0], imm
)
6345 || i
.types
[0].bitfield
.shiftcount
)
6351 /* When there are 4 operands, the first two must be 8bit
6352 immediate operands. The source operand will be the 3rd
6355 For instructions with VexNDS, if the first operand
6356 an imm8, the source operand is the 2nd one. If the last
6357 operand is imm8, the source operand is the first one. */
6358 gas_assert ((i
.imm_operands
== 2
6359 && i
.types
[0].bitfield
.imm8
6360 && i
.types
[1].bitfield
.imm8
)
6361 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6362 && i
.imm_operands
== 1
6363 && (i
.types
[0].bitfield
.imm8
6364 || i
.types
[i
.operands
- 1].bitfield
.imm8
6366 if (i
.imm_operands
== 2)
6370 if (i
.types
[0].bitfield
.imm8
)
6377 if (i
.tm
.opcode_modifier
.evex
)
6379 /* For EVEX instructions, when there are 5 operands, the
6380 first one must be immediate operand. If the second one
6381 is immediate operand, the source operand is the 3th
6382 one. If the last one is immediate operand, the source
6383 operand is the 2nd one. */
6384 gas_assert (i
.imm_operands
== 2
6385 && i
.tm
.opcode_modifier
.sae
6386 && operand_type_check (i
.types
[0], imm
));
6387 if (operand_type_check (i
.types
[1], imm
))
6389 else if (operand_type_check (i
.types
[4], imm
))
6403 /* RC/SAE operand could be between DEST and SRC. That happens
6404 when one operand is GPR and the other one is XMM/YMM/ZMM
6406 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6409 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6411 /* For instructions with VexNDS, the register-only source
6412 operand must be 32/64bit integer, XMM, YMM or ZMM
6413 register. It is encoded in VEX prefix. We need to
6414 clear RegMem bit before calling operand_type_equal. */
6416 i386_operand_type op
;
6419 /* Check register-only source operand when two source
6420 operands are swapped. */
6421 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6422 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6430 op
= i
.tm
.operand_types
[vvvv
];
6431 op
.bitfield
.regmem
= 0;
6432 if ((dest
+ 1) >= i
.operands
6433 || (!op
.bitfield
.reg32
6434 && op
.bitfield
.reg64
6435 && !operand_type_equal (&op
, ®xmm
)
6436 && !operand_type_equal (&op
, ®ymm
)
6437 && !operand_type_equal (&op
, ®zmm
)
6438 && !operand_type_equal (&op
, ®mask
)))
6440 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6446 /* One of the register operands will be encoded in the i.tm.reg
6447 field, the other in the combined i.tm.mode and i.tm.regmem
6448 fields. If no form of this instruction supports a memory
6449 destination operand, then we assume the source operand may
6450 sometimes be a memory operand and so we need to store the
6451 destination in the i.rm.reg field. */
6452 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6453 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6455 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6456 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6457 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6459 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6461 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6463 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6468 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6469 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6470 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6472 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6474 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6476 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6479 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6481 if (!i
.types
[0].bitfield
.control
6482 && !i
.types
[1].bitfield
.control
)
6484 i
.rex
&= ~(REX_R
| REX_B
);
6485 add_prefix (LOCK_PREFIX_OPCODE
);
6489 { /* If it's not 2 reg operands... */
6494 unsigned int fake_zero_displacement
= 0;
6497 for (op
= 0; op
< i
.operands
; op
++)
6498 if (operand_type_check (i
.types
[op
], anymem
))
6500 gas_assert (op
< i
.operands
);
6502 if (i
.tm
.opcode_modifier
.vecsib
)
6504 if (i
.index_reg
->reg_num
== RegEiz
6505 || i
.index_reg
->reg_num
== RegRiz
)
6508 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6511 i
.sib
.base
= NO_BASE_REGISTER
;
6512 i
.sib
.scale
= i
.log2_scale_factor
;
6513 /* No Vec_Disp8 if there is no base. */
6514 i
.types
[op
].bitfield
.vec_disp8
= 0;
6515 i
.types
[op
].bitfield
.disp8
= 0;
6516 i
.types
[op
].bitfield
.disp16
= 0;
6517 i
.types
[op
].bitfield
.disp64
= 0;
6518 if (flag_code
!= CODE_64BIT
)
6520 /* Must be 32 bit */
6521 i
.types
[op
].bitfield
.disp32
= 1;
6522 i
.types
[op
].bitfield
.disp32s
= 0;
6526 i
.types
[op
].bitfield
.disp32
= 0;
6527 i
.types
[op
].bitfield
.disp32s
= 1;
6530 i
.sib
.index
= i
.index_reg
->reg_num
;
6531 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6533 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6539 if (i
.base_reg
== 0)
6542 if (!i
.disp_operands
)
6544 fake_zero_displacement
= 1;
6545 /* Instructions with VSIB byte need 32bit displacement
6546 if there is no base register. */
6547 if (i
.tm
.opcode_modifier
.vecsib
)
6548 i
.types
[op
].bitfield
.disp32
= 1;
6550 if (i
.index_reg
== 0)
6552 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6553 /* Operand is just <disp> */
6554 if (flag_code
== CODE_64BIT
)
6556 /* 64bit mode overwrites the 32bit absolute
6557 addressing by RIP relative addressing and
6558 absolute addressing is encoded by one of the
6559 redundant SIB forms. */
6560 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6561 i
.sib
.base
= NO_BASE_REGISTER
;
6562 i
.sib
.index
= NO_INDEX_REGISTER
;
6563 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6564 ? disp32s
: disp32
);
6566 else if ((flag_code
== CODE_16BIT
)
6567 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6569 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6570 i
.types
[op
] = disp16
;
6574 i
.rm
.regmem
= NO_BASE_REGISTER
;
6575 i
.types
[op
] = disp32
;
6578 else if (!i
.tm
.opcode_modifier
.vecsib
)
6580 /* !i.base_reg && i.index_reg */
6581 if (i
.index_reg
->reg_num
== RegEiz
6582 || i
.index_reg
->reg_num
== RegRiz
)
6583 i
.sib
.index
= NO_INDEX_REGISTER
;
6585 i
.sib
.index
= i
.index_reg
->reg_num
;
6586 i
.sib
.base
= NO_BASE_REGISTER
;
6587 i
.sib
.scale
= i
.log2_scale_factor
;
6588 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6589 /* No Vec_Disp8 if there is no base. */
6590 i
.types
[op
].bitfield
.vec_disp8
= 0;
6591 i
.types
[op
].bitfield
.disp8
= 0;
6592 i
.types
[op
].bitfield
.disp16
= 0;
6593 i
.types
[op
].bitfield
.disp64
= 0;
6594 if (flag_code
!= CODE_64BIT
)
6596 /* Must be 32 bit */
6597 i
.types
[op
].bitfield
.disp32
= 1;
6598 i
.types
[op
].bitfield
.disp32s
= 0;
6602 i
.types
[op
].bitfield
.disp32
= 0;
6603 i
.types
[op
].bitfield
.disp32s
= 1;
6605 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6609 /* RIP addressing for 64bit mode. */
6610 else if (i
.base_reg
->reg_num
== RegRip
||
6611 i
.base_reg
->reg_num
== RegEip
)
6613 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6614 i
.rm
.regmem
= NO_BASE_REGISTER
;
6615 i
.types
[op
].bitfield
.disp8
= 0;
6616 i
.types
[op
].bitfield
.disp16
= 0;
6617 i
.types
[op
].bitfield
.disp32
= 0;
6618 i
.types
[op
].bitfield
.disp32s
= 1;
6619 i
.types
[op
].bitfield
.disp64
= 0;
6620 i
.types
[op
].bitfield
.vec_disp8
= 0;
6621 i
.flags
[op
] |= Operand_PCrel
;
6622 if (! i
.disp_operands
)
6623 fake_zero_displacement
= 1;
6625 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6627 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6628 switch (i
.base_reg
->reg_num
)
6631 if (i
.index_reg
== 0)
6633 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6634 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6638 if (i
.index_reg
== 0)
6641 if (operand_type_check (i
.types
[op
], disp
) == 0)
6643 /* fake (%bp) into 0(%bp) */
6644 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6645 i
.types
[op
].bitfield
.vec_disp8
= 1;
6647 i
.types
[op
].bitfield
.disp8
= 1;
6648 fake_zero_displacement
= 1;
6651 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6652 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6654 default: /* (%si) -> 4 or (%di) -> 5 */
6655 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6657 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6659 else /* i.base_reg and 32/64 bit mode */
6661 if (flag_code
== CODE_64BIT
6662 && operand_type_check (i
.types
[op
], disp
))
6664 i386_operand_type temp
;
6665 operand_type_set (&temp
, 0);
6666 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6667 temp
.bitfield
.vec_disp8
6668 = i
.types
[op
].bitfield
.vec_disp8
;
6670 if (i
.prefix
[ADDR_PREFIX
] == 0)
6671 i
.types
[op
].bitfield
.disp32s
= 1;
6673 i
.types
[op
].bitfield
.disp32
= 1;
6676 if (!i
.tm
.opcode_modifier
.vecsib
)
6677 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6678 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6680 i
.sib
.base
= i
.base_reg
->reg_num
;
6681 /* x86-64 ignores REX prefix bit here to avoid decoder
6683 if (!(i
.base_reg
->reg_flags
& RegRex
)
6684 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6685 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6687 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6689 fake_zero_displacement
= 1;
6690 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6691 i
.types
[op
].bitfield
.vec_disp8
= 1;
6693 i
.types
[op
].bitfield
.disp8
= 1;
6695 i
.sib
.scale
= i
.log2_scale_factor
;
6696 if (i
.index_reg
== 0)
6698 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6699 /* <disp>(%esp) becomes two byte modrm with no index
6700 register. We've already stored the code for esp
6701 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6702 Any base register besides %esp will not use the
6703 extra modrm byte. */
6704 i
.sib
.index
= NO_INDEX_REGISTER
;
6706 else if (!i
.tm
.opcode_modifier
.vecsib
)
6708 if (i
.index_reg
->reg_num
== RegEiz
6709 || i
.index_reg
->reg_num
== RegRiz
)
6710 i
.sib
.index
= NO_INDEX_REGISTER
;
6712 i
.sib
.index
= i
.index_reg
->reg_num
;
6713 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6714 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6719 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6720 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6724 if (!fake_zero_displacement
6728 fake_zero_displacement
= 1;
6729 if (i
.disp_encoding
== disp_encoding_8bit
)
6730 i
.types
[op
].bitfield
.disp8
= 1;
6732 i
.types
[op
].bitfield
.disp32
= 1;
6734 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6738 if (fake_zero_displacement
)
6740 /* Fakes a zero displacement assuming that i.types[op]
6741 holds the correct displacement size. */
6744 gas_assert (i
.op
[op
].disps
== 0);
6745 exp
= &disp_expressions
[i
.disp_operands
++];
6746 i
.op
[op
].disps
= exp
;
6747 exp
->X_op
= O_constant
;
6748 exp
->X_add_number
= 0;
6749 exp
->X_add_symbol
= (symbolS
*) 0;
6750 exp
->X_op_symbol
= (symbolS
*) 0;
6758 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6760 if (operand_type_check (i
.types
[0], imm
))
6761 i
.vex
.register_specifier
= NULL
;
6764 /* VEX.vvvv encodes one of the sources when the first
6765 operand is not an immediate. */
6766 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6767 i
.vex
.register_specifier
= i
.op
[0].regs
;
6769 i
.vex
.register_specifier
= i
.op
[1].regs
;
6772 /* Destination is a XMM register encoded in the ModRM.reg
6774 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6775 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6778 /* ModRM.rm and VEX.B encodes the other source. */
6779 if (!i
.mem_operands
)
6783 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6784 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6786 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6788 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6792 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6794 i
.vex
.register_specifier
= i
.op
[2].regs
;
6795 if (!i
.mem_operands
)
6798 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6799 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6803 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6804 (if any) based on i.tm.extension_opcode. Again, we must be
6805 careful to make sure that segment/control/debug/test/MMX
6806 registers are coded into the i.rm.reg field. */
6807 else if (i
.reg_operands
)
6810 unsigned int vex_reg
= ~0;
6812 for (op
= 0; op
< i
.operands
; op
++)
6813 if (i
.types
[op
].bitfield
.reg8
6814 || i
.types
[op
].bitfield
.reg16
6815 || i
.types
[op
].bitfield
.reg32
6816 || i
.types
[op
].bitfield
.reg64
6817 || i
.types
[op
].bitfield
.regmmx
6818 || i
.types
[op
].bitfield
.regxmm
6819 || i
.types
[op
].bitfield
.regymm
6820 || i
.types
[op
].bitfield
.regbnd
6821 || i
.types
[op
].bitfield
.regzmm
6822 || i
.types
[op
].bitfield
.regmask
6823 || i
.types
[op
].bitfield
.sreg2
6824 || i
.types
[op
].bitfield
.sreg3
6825 || i
.types
[op
].bitfield
.control
6826 || i
.types
[op
].bitfield
.debug
6827 || i
.types
[op
].bitfield
.test
)
6832 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6834 /* For instructions with VexNDS, the register-only
6835 source operand is encoded in VEX prefix. */
6836 gas_assert (mem
!= (unsigned int) ~0);
6841 gas_assert (op
< i
.operands
);
6845 /* Check register-only source operand when two source
6846 operands are swapped. */
6847 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6848 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6852 gas_assert (mem
== (vex_reg
+ 1)
6853 && op
< i
.operands
);
6858 gas_assert (vex_reg
< i
.operands
);
6862 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6864 /* For instructions with VexNDD, the register destination
6865 is encoded in VEX prefix. */
6866 if (i
.mem_operands
== 0)
6868 /* There is no memory operand. */
6869 gas_assert ((op
+ 2) == i
.operands
);
6874 /* There are only 2 operands. */
6875 gas_assert (op
< 2 && i
.operands
== 2);
6880 gas_assert (op
< i
.operands
);
6882 if (vex_reg
!= (unsigned int) ~0)
6884 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6886 if (type
->bitfield
.reg32
!= 1
6887 && type
->bitfield
.reg64
!= 1
6888 && !operand_type_equal (type
, ®xmm
)
6889 && !operand_type_equal (type
, ®ymm
)
6890 && !operand_type_equal (type
, ®zmm
)
6891 && !operand_type_equal (type
, ®mask
))
6894 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6897 /* Don't set OP operand twice. */
6900 /* If there is an extension opcode to put here, the
6901 register number must be put into the regmem field. */
6902 if (i
.tm
.extension_opcode
!= None
)
6904 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6905 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6907 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6912 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6913 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6915 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6920 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6921 must set it to 3 to indicate this is a register operand
6922 in the regmem field. */
6923 if (!i
.mem_operands
)
6927 /* Fill in i.rm.reg field with extension opcode (if any). */
6928 if (i
.tm
.extension_opcode
!= None
)
6929 i
.rm
.reg
= i
.tm
.extension_opcode
;
6935 output_branch (void)
6941 relax_substateT subtype
;
6945 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6946 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6949 if (i
.prefix
[DATA_PREFIX
] != 0)
6955 /* Pentium4 branch hints. */
6956 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6957 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6962 if (i
.prefix
[REX_PREFIX
] != 0)
6968 /* BND prefixed jump. */
6969 if (i
.prefix
[BND_PREFIX
] != 0)
6971 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6975 if (i
.prefixes
!= 0 && !intel_syntax
)
6976 as_warn (_("skipping prefixes on this instruction"));
6978 /* It's always a symbol; End frag & setup for relax.
6979 Make sure there is enough room in this frag for the largest
6980 instruction we may generate in md_convert_frag. This is 2
6981 bytes for the opcode and room for the prefix and largest
6983 frag_grow (prefix
+ 2 + 4);
6984 /* Prefix and 1 opcode byte go in fr_fix. */
6985 p
= frag_more (prefix
+ 1);
6986 if (i
.prefix
[DATA_PREFIX
] != 0)
6987 *p
++ = DATA_PREFIX_OPCODE
;
6988 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6989 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6990 *p
++ = i
.prefix
[SEG_PREFIX
];
6991 if (i
.prefix
[REX_PREFIX
] != 0)
6992 *p
++ = i
.prefix
[REX_PREFIX
];
6993 *p
= i
.tm
.base_opcode
;
6995 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6996 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6997 else if (cpu_arch_flags
.bitfield
.cpui386
)
6998 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7000 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7003 sym
= i
.op
[0].disps
->X_add_symbol
;
7004 off
= i
.op
[0].disps
->X_add_number
;
7006 if (i
.op
[0].disps
->X_op
!= O_constant
7007 && i
.op
[0].disps
->X_op
!= O_symbol
)
7009 /* Handle complex expressions. */
7010 sym
= make_expr_symbol (i
.op
[0].disps
);
7014 /* 1 possible extra opcode + 4 byte displacement go in var part.
7015 Pass reloc in fr_var. */
7016 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7026 if (i
.tm
.opcode_modifier
.jumpbyte
)
7028 /* This is a loop or jecxz type instruction. */
7030 if (i
.prefix
[ADDR_PREFIX
] != 0)
7032 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7035 /* Pentium4 branch hints. */
7036 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7037 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7039 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7048 if (flag_code
== CODE_16BIT
)
7051 if (i
.prefix
[DATA_PREFIX
] != 0)
7053 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7063 if (i
.prefix
[REX_PREFIX
] != 0)
7065 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7069 /* BND prefixed jump. */
7070 if (i
.prefix
[BND_PREFIX
] != 0)
7072 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7076 if (i
.prefixes
!= 0 && !intel_syntax
)
7077 as_warn (_("skipping prefixes on this instruction"));
7079 p
= frag_more (i
.tm
.opcode_length
+ size
);
7080 switch (i
.tm
.opcode_length
)
7083 *p
++ = i
.tm
.base_opcode
>> 8;
7086 *p
++ = i
.tm
.base_opcode
;
7092 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7093 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
7095 /* All jumps handled here are signed, but don't use a signed limit
7096 check for 32 and 16 bit jumps as we want to allow wrap around at
7097 4G and 64k respectively. */
7099 fixP
->fx_signed
= 1;
7103 output_interseg_jump (void)
7111 if (flag_code
== CODE_16BIT
)
7115 if (i
.prefix
[DATA_PREFIX
] != 0)
7121 if (i
.prefix
[REX_PREFIX
] != 0)
7131 if (i
.prefixes
!= 0 && !intel_syntax
)
7132 as_warn (_("skipping prefixes on this instruction"));
7134 /* 1 opcode; 2 segment; offset */
7135 p
= frag_more (prefix
+ 1 + 2 + size
);
7137 if (i
.prefix
[DATA_PREFIX
] != 0)
7138 *p
++ = DATA_PREFIX_OPCODE
;
7140 if (i
.prefix
[REX_PREFIX
] != 0)
7141 *p
++ = i
.prefix
[REX_PREFIX
];
7143 *p
++ = i
.tm
.base_opcode
;
7144 if (i
.op
[1].imms
->X_op
== O_constant
)
7146 offsetT n
= i
.op
[1].imms
->X_add_number
;
7149 && !fits_in_unsigned_word (n
)
7150 && !fits_in_signed_word (n
))
7152 as_bad (_("16-bit jump out of range"));
7155 md_number_to_chars (p
, n
, size
);
7158 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7159 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7160 if (i
.op
[0].imms
->X_op
!= O_constant
)
7161 as_bad (_("can't handle non absolute segment in `%s'"),
7163 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7169 fragS
*insn_start_frag
;
7170 offsetT insn_start_off
;
7172 /* Tie dwarf2 debug info to the address at the start of the insn.
7173 We can't do this after the insn has been output as the current
7174 frag may have been closed off. eg. by frag_var. */
7175 dwarf2_emit_insn (0);
7177 insn_start_frag
= frag_now
;
7178 insn_start_off
= frag_now_fix ();
7181 if (i
.tm
.opcode_modifier
.jump
)
7183 else if (i
.tm
.opcode_modifier
.jumpbyte
7184 || i
.tm
.opcode_modifier
.jumpdword
)
7186 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7187 output_interseg_jump ();
7190 /* Output normal instructions here. */
7194 unsigned int prefix
;
7197 && i
.tm
.base_opcode
== 0xfae
7199 && i
.imm_operands
== 1
7200 && (i
.op
[0].imms
->X_add_number
== 0xe8
7201 || i
.op
[0].imms
->X_add_number
== 0xf0
7202 || i
.op
[0].imms
->X_add_number
== 0xf8))
7204 /* Encode lfence, mfence, and sfence as
7205 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7206 offsetT val
= 0x240483f0ULL
;
7208 md_number_to_chars (p
, val
, 5);
7212 /* Some processors fail on LOCK prefix. This options makes
7213 assembler ignore LOCK prefix and serves as a workaround. */
7214 if (omit_lock_prefix
)
7216 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7218 i
.prefix
[LOCK_PREFIX
] = 0;
7221 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7222 don't need the explicit prefix. */
7223 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7225 switch (i
.tm
.opcode_length
)
7228 if (i
.tm
.base_opcode
& 0xff000000)
7230 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7235 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7237 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7238 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7241 if (prefix
!= REPE_PREFIX_OPCODE
7242 || (i
.prefix
[REP_PREFIX
]
7243 != REPE_PREFIX_OPCODE
))
7244 add_prefix (prefix
);
7247 add_prefix (prefix
);
7256 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7257 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7258 R_X86_64_GOTTPOFF relocation so that linker can safely
7259 perform IE->LE optimization. */
7260 if (x86_elf_abi
== X86_64_X32_ABI
7262 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7263 && i
.prefix
[REX_PREFIX
] == 0)
7264 add_prefix (REX_OPCODE
);
7267 /* The prefix bytes. */
7268 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7270 FRAG_APPEND_1_CHAR (*q
);
7274 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7279 /* REX byte is encoded in VEX prefix. */
7283 FRAG_APPEND_1_CHAR (*q
);
7286 /* There should be no other prefixes for instructions
7291 /* For EVEX instructions i.vrex should become 0 after
7292 build_evex_prefix. For VEX instructions upper 16 registers
7293 aren't available, so VREX should be 0. */
7296 /* Now the VEX prefix. */
7297 p
= frag_more (i
.vex
.length
);
7298 for (j
= 0; j
< i
.vex
.length
; j
++)
7299 p
[j
] = i
.vex
.bytes
[j
];
7302 /* Now the opcode; be careful about word order here! */
7303 if (i
.tm
.opcode_length
== 1)
7305 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7309 switch (i
.tm
.opcode_length
)
7313 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7314 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7318 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7328 /* Put out high byte first: can't use md_number_to_chars! */
7329 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7330 *p
= i
.tm
.base_opcode
& 0xff;
7333 /* Now the modrm byte and sib byte (if present). */
7334 if (i
.tm
.opcode_modifier
.modrm
)
7336 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7339 /* If i.rm.regmem == ESP (4)
7340 && i.rm.mode != (Register mode)
7342 ==> need second modrm byte. */
7343 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7345 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7346 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7348 | i
.sib
.scale
<< 6));
7351 if (i
.disp_operands
)
7352 output_disp (insn_start_frag
, insn_start_off
);
7355 output_imm (insn_start_frag
, insn_start_off
);
7361 pi ("" /*line*/, &i
);
7363 #endif /* DEBUG386 */
7366 /* Return the size of the displacement operand N. */
7369 disp_size (unsigned int n
)
7373 /* Vec_Disp8 has to be 8bit. */
7374 if (i
.types
[n
].bitfield
.vec_disp8
)
7376 else if (i
.types
[n
].bitfield
.disp64
)
7378 else if (i
.types
[n
].bitfield
.disp8
)
7380 else if (i
.types
[n
].bitfield
.disp16
)
7385 /* Return the size of the immediate operand N. */
7388 imm_size (unsigned int n
)
7391 if (i
.types
[n
].bitfield
.imm64
)
7393 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7395 else if (i
.types
[n
].bitfield
.imm16
)
7401 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7406 for (n
= 0; n
< i
.operands
; n
++)
7408 if (i
.types
[n
].bitfield
.vec_disp8
7409 || operand_type_check (i
.types
[n
], disp
))
7411 if (i
.op
[n
].disps
->X_op
== O_constant
)
7413 int size
= disp_size (n
);
7414 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7416 if (i
.types
[n
].bitfield
.vec_disp8
)
7418 val
= offset_in_range (val
, size
);
7419 p
= frag_more (size
);
7420 md_number_to_chars (p
, val
, size
);
7424 enum bfd_reloc_code_real reloc_type
;
7425 int size
= disp_size (n
);
7426 int sign
= i
.types
[n
].bitfield
.disp32s
;
7427 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7430 /* We can't have 8 bit displacement here. */
7431 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7433 /* The PC relative address is computed relative
7434 to the instruction boundary, so in case immediate
7435 fields follows, we need to adjust the value. */
7436 if (pcrel
&& i
.imm_operands
)
7441 for (n1
= 0; n1
< i
.operands
; n1
++)
7442 if (operand_type_check (i
.types
[n1
], imm
))
7444 /* Only one immediate is allowed for PC
7445 relative address. */
7446 gas_assert (sz
== 0);
7448 i
.op
[n
].disps
->X_add_number
-= sz
;
7450 /* We should find the immediate. */
7451 gas_assert (sz
!= 0);
7454 p
= frag_more (size
);
7455 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7457 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7458 && (((reloc_type
== BFD_RELOC_32
7459 || reloc_type
== BFD_RELOC_X86_64_32S
7460 || (reloc_type
== BFD_RELOC_64
7462 && (i
.op
[n
].disps
->X_op
== O_symbol
7463 || (i
.op
[n
].disps
->X_op
== O_add
7464 && ((symbol_get_value_expression
7465 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7467 || reloc_type
== BFD_RELOC_32_PCREL
))
7471 if (insn_start_frag
== frag_now
)
7472 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7477 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7478 for (fr
= insn_start_frag
->fr_next
;
7479 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7481 add
+= p
- frag_now
->fr_literal
;
7486 reloc_type
= BFD_RELOC_386_GOTPC
;
7487 i
.op
[n
].imms
->X_add_number
+= add
;
7489 else if (reloc_type
== BFD_RELOC_64
)
7490 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7492 /* Don't do the adjustment for x86-64, as there
7493 the pcrel addressing is relative to the _next_
7494 insn, and that is taken care of in other code. */
7495 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7497 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7498 size
, i
.op
[n
].disps
, pcrel
,
7500 /* Check for "call/jmp *mem", "mov mem, %reg",
7501 "test %reg, mem" and "binop mem, %reg" where binop
7502 is one of adc, add, and, cmp, or, sbb, sub, xor
7503 instructions. Always generate R_386_GOT32X for
7504 "sym*GOT" operand in 32-bit mode. */
7505 if ((generate_relax_relocations
7508 && i
.rm
.regmem
== 5))
7510 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7511 && ((i
.operands
== 1
7512 && i
.tm
.base_opcode
== 0xff
7513 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7515 && (i
.tm
.base_opcode
== 0x8b
7516 || i
.tm
.base_opcode
== 0x85
7517 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7521 fixP
->fx_tcbit
= i
.rex
!= 0;
7523 && (i
.base_reg
->reg_num
== RegRip
7524 || i
.base_reg
->reg_num
== RegEip
))
7525 fixP
->fx_tcbit2
= 1;
7528 fixP
->fx_tcbit2
= 1;
7536 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7541 for (n
= 0; n
< i
.operands
; n
++)
7543 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7544 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7547 if (operand_type_check (i
.types
[n
], imm
))
7549 if (i
.op
[n
].imms
->X_op
== O_constant
)
7551 int size
= imm_size (n
);
7554 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7556 p
= frag_more (size
);
7557 md_number_to_chars (p
, val
, size
);
7561 /* Not absolute_section.
7562 Need a 32-bit fixup (don't support 8bit
7563 non-absolute imms). Try to support other
7565 enum bfd_reloc_code_real reloc_type
;
7566 int size
= imm_size (n
);
7569 if (i
.types
[n
].bitfield
.imm32s
7570 && (i
.suffix
== QWORD_MNEM_SUFFIX
7571 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7576 p
= frag_more (size
);
7577 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7579 /* This is tough to explain. We end up with this one if we
7580 * have operands that look like
7581 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7582 * obtain the absolute address of the GOT, and it is strongly
7583 * preferable from a performance point of view to avoid using
7584 * a runtime relocation for this. The actual sequence of
7585 * instructions often look something like:
7590 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7592 * The call and pop essentially return the absolute address
7593 * of the label .L66 and store it in %ebx. The linker itself
7594 * will ultimately change the first operand of the addl so
7595 * that %ebx points to the GOT, but to keep things simple, the
7596 * .o file must have this operand set so that it generates not
7597 * the absolute address of .L66, but the absolute address of
7598 * itself. This allows the linker itself simply treat a GOTPC
7599 * relocation as asking for a pcrel offset to the GOT to be
7600 * added in, and the addend of the relocation is stored in the
7601 * operand field for the instruction itself.
7603 * Our job here is to fix the operand so that it would add
7604 * the correct offset so that %ebx would point to itself. The
7605 * thing that is tricky is that .-.L66 will point to the
7606 * beginning of the instruction, so we need to further modify
7607 * the operand so that it will point to itself. There are
7608 * other cases where you have something like:
7610 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7612 * and here no correction would be required. Internally in
7613 * the assembler we treat operands of this form as not being
7614 * pcrel since the '.' is explicitly mentioned, and I wonder
7615 * whether it would simplify matters to do it this way. Who
7616 * knows. In earlier versions of the PIC patches, the
7617 * pcrel_adjust field was used to store the correction, but
7618 * since the expression is not pcrel, I felt it would be
7619 * confusing to do it this way. */
7621 if ((reloc_type
== BFD_RELOC_32
7622 || reloc_type
== BFD_RELOC_X86_64_32S
7623 || reloc_type
== BFD_RELOC_64
)
7625 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7626 && (i
.op
[n
].imms
->X_op
== O_symbol
7627 || (i
.op
[n
].imms
->X_op
== O_add
7628 && ((symbol_get_value_expression
7629 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7634 if (insn_start_frag
== frag_now
)
7635 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7640 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7641 for (fr
= insn_start_frag
->fr_next
;
7642 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7644 add
+= p
- frag_now
->fr_literal
;
7648 reloc_type
= BFD_RELOC_386_GOTPC
;
7650 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7652 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7653 i
.op
[n
].imms
->X_add_number
+= add
;
7655 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7656 i
.op
[n
].imms
, 0, reloc_type
);
7662 /* x86_cons_fix_new is called via the expression parsing code when a
7663 reloc is needed. We use this hook to get the correct .got reloc. */
7664 static int cons_sign
= -1;
7667 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7668 expressionS
*exp
, bfd_reloc_code_real_type r
)
7670 r
= reloc (len
, 0, cons_sign
, r
);
7673 if (exp
->X_op
== O_secrel
)
7675 exp
->X_op
= O_symbol
;
7676 r
= BFD_RELOC_32_SECREL
;
7680 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7683 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7684 purpose of the `.dc.a' internal pseudo-op. */
7687 x86_address_bytes (void)
7689 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7691 return stdoutput
->arch_info
->bits_per_address
/ 8;
7694 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7696 # define lex_got(reloc, adjust, types) NULL
7698 /* Parse operands of the form
7699 <symbol>@GOTOFF+<nnn>
7700 and similar .plt or .got references.
7702 If we find one, set up the correct relocation in RELOC and copy the
7703 input string, minus the `@GOTOFF' into a malloc'd buffer for
7704 parsing by the calling routine. Return this buffer, and if ADJUST
7705 is non-null set it to the length of the string we removed from the
7706 input line. Otherwise return NULL. */
7708 lex_got (enum bfd_reloc_code_real
*rel
,
7710 i386_operand_type
*types
)
7712 /* Some of the relocations depend on the size of what field is to
7713 be relocated. But in our callers i386_immediate and i386_displacement
7714 we don't yet know the operand size (this will be set by insn
7715 matching). Hence we record the word32 relocation here,
7716 and adjust the reloc according to the real size in reloc(). */
7717 static const struct {
7720 const enum bfd_reloc_code_real rel
[2];
7721 const i386_operand_type types64
;
7723 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7724 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7726 OPERAND_TYPE_IMM32_64
},
7728 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7729 BFD_RELOC_X86_64_PLTOFF64
},
7730 OPERAND_TYPE_IMM64
},
7731 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7732 BFD_RELOC_X86_64_PLT32
},
7733 OPERAND_TYPE_IMM32_32S_DISP32
},
7734 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7735 BFD_RELOC_X86_64_GOTPLT64
},
7736 OPERAND_TYPE_IMM64_DISP64
},
7737 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7738 BFD_RELOC_X86_64_GOTOFF64
},
7739 OPERAND_TYPE_IMM64_DISP64
},
7740 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7741 BFD_RELOC_X86_64_GOTPCREL
},
7742 OPERAND_TYPE_IMM32_32S_DISP32
},
7743 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7744 BFD_RELOC_X86_64_TLSGD
},
7745 OPERAND_TYPE_IMM32_32S_DISP32
},
7746 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7747 _dummy_first_bfd_reloc_code_real
},
7748 OPERAND_TYPE_NONE
},
7749 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7750 BFD_RELOC_X86_64_TLSLD
},
7751 OPERAND_TYPE_IMM32_32S_DISP32
},
7752 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7753 BFD_RELOC_X86_64_GOTTPOFF
},
7754 OPERAND_TYPE_IMM32_32S_DISP32
},
7755 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7756 BFD_RELOC_X86_64_TPOFF32
},
7757 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7758 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7759 _dummy_first_bfd_reloc_code_real
},
7760 OPERAND_TYPE_NONE
},
7761 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7762 BFD_RELOC_X86_64_DTPOFF32
},
7763 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7764 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7765 _dummy_first_bfd_reloc_code_real
},
7766 OPERAND_TYPE_NONE
},
7767 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7768 _dummy_first_bfd_reloc_code_real
},
7769 OPERAND_TYPE_NONE
},
7770 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7771 BFD_RELOC_X86_64_GOT32
},
7772 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7773 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7774 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7775 OPERAND_TYPE_IMM32_32S_DISP32
},
7776 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7777 BFD_RELOC_X86_64_TLSDESC_CALL
},
7778 OPERAND_TYPE_IMM32_32S_DISP32
},
7783 #if defined (OBJ_MAYBE_ELF)
7788 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7789 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7792 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7794 int len
= gotrel
[j
].len
;
7795 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7797 if (gotrel
[j
].rel
[object_64bit
] != 0)
7800 char *tmpbuf
, *past_reloc
;
7802 *rel
= gotrel
[j
].rel
[object_64bit
];
7806 if (flag_code
!= CODE_64BIT
)
7808 types
->bitfield
.imm32
= 1;
7809 types
->bitfield
.disp32
= 1;
7812 *types
= gotrel
[j
].types64
;
7815 if (j
!= 0 && GOT_symbol
== NULL
)
7816 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7818 /* The length of the first part of our input line. */
7819 first
= cp
- input_line_pointer
;
7821 /* The second part goes from after the reloc token until
7822 (and including) an end_of_line char or comma. */
7823 past_reloc
= cp
+ 1 + len
;
7825 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7827 second
= cp
+ 1 - past_reloc
;
7829 /* Allocate and copy string. The trailing NUL shouldn't
7830 be necessary, but be safe. */
7831 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7832 memcpy (tmpbuf
, input_line_pointer
, first
);
7833 if (second
!= 0 && *past_reloc
!= ' ')
7834 /* Replace the relocation token with ' ', so that
7835 errors like foo@GOTOFF1 will be detected. */
7836 tmpbuf
[first
++] = ' ';
7838 /* Increment length by 1 if the relocation token is
7843 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7844 tmpbuf
[first
+ second
] = '\0';
7848 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7849 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7854 /* Might be a symbol version string. Don't as_bad here. */
7863 /* Parse operands of the form
7864 <symbol>@SECREL32+<nnn>
7866 If we find one, set up the correct relocation in RELOC and copy the
7867 input string, minus the `@SECREL32' into a malloc'd buffer for
7868 parsing by the calling routine. Return this buffer, and if ADJUST
7869 is non-null set it to the length of the string we removed from the
7870 input line. Otherwise return NULL.
7872 This function is copied from the ELF version above adjusted for PE targets. */
7875 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7876 int *adjust ATTRIBUTE_UNUSED
,
7877 i386_operand_type
*types
)
7883 const enum bfd_reloc_code_real rel
[2];
7884 const i386_operand_type types64
;
7888 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7889 BFD_RELOC_32_SECREL
},
7890 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7896 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7897 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7900 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7902 int len
= gotrel
[j
].len
;
7904 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7906 if (gotrel
[j
].rel
[object_64bit
] != 0)
7909 char *tmpbuf
, *past_reloc
;
7911 *rel
= gotrel
[j
].rel
[object_64bit
];
7917 if (flag_code
!= CODE_64BIT
)
7919 types
->bitfield
.imm32
= 1;
7920 types
->bitfield
.disp32
= 1;
7923 *types
= gotrel
[j
].types64
;
7926 /* The length of the first part of our input line. */
7927 first
= cp
- input_line_pointer
;
7929 /* The second part goes from after the reloc token until
7930 (and including) an end_of_line char or comma. */
7931 past_reloc
= cp
+ 1 + len
;
7933 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7935 second
= cp
+ 1 - past_reloc
;
7937 /* Allocate and copy string. The trailing NUL shouldn't
7938 be necessary, but be safe. */
7939 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7940 memcpy (tmpbuf
, input_line_pointer
, first
);
7941 if (second
!= 0 && *past_reloc
!= ' ')
7942 /* Replace the relocation token with ' ', so that
7943 errors like foo@SECLREL321 will be detected. */
7944 tmpbuf
[first
++] = ' ';
7945 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7946 tmpbuf
[first
+ second
] = '\0';
7950 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7951 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7956 /* Might be a symbol version string. Don't as_bad here. */
7962 bfd_reloc_code_real_type
7963 x86_cons (expressionS
*exp
, int size
)
7965 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7967 intel_syntax
= -intel_syntax
;
7970 if (size
== 4 || (object_64bit
&& size
== 8))
7972 /* Handle @GOTOFF and the like in an expression. */
7974 char *gotfree_input_line
;
7977 save
= input_line_pointer
;
7978 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7979 if (gotfree_input_line
)
7980 input_line_pointer
= gotfree_input_line
;
7984 if (gotfree_input_line
)
7986 /* expression () has merrily parsed up to the end of line,
7987 or a comma - in the wrong buffer. Transfer how far
7988 input_line_pointer has moved to the right buffer. */
7989 input_line_pointer
= (save
7990 + (input_line_pointer
- gotfree_input_line
)
7992 free (gotfree_input_line
);
7993 if (exp
->X_op
== O_constant
7994 || exp
->X_op
== O_absent
7995 || exp
->X_op
== O_illegal
7996 || exp
->X_op
== O_register
7997 || exp
->X_op
== O_big
)
7999 char c
= *input_line_pointer
;
8000 *input_line_pointer
= 0;
8001 as_bad (_("missing or invalid expression `%s'"), save
);
8002 *input_line_pointer
= c
;
8009 intel_syntax
= -intel_syntax
;
8012 i386_intel_simplify (exp
);
8018 signed_cons (int size
)
8020 if (flag_code
== CODE_64BIT
)
8028 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
8035 if (exp
.X_op
== O_symbol
)
8036 exp
.X_op
= O_secrel
;
8038 emit_expr (&exp
, 4);
8040 while (*input_line_pointer
++ == ',');
8042 input_line_pointer
--;
8043 demand_empty_rest_of_line ();
8047 /* Handle Vector operations. */
8050 check_VecOperations (char *op_string
, char *op_end
)
8052 const reg_entry
*mask
;
8057 && (op_end
== NULL
|| op_string
< op_end
))
8060 if (*op_string
== '{')
8064 /* Check broadcasts. */
8065 if (strncmp (op_string
, "1to", 3) == 0)
8070 goto duplicated_vec_op
;
8073 if (*op_string
== '8')
8074 bcst_type
= BROADCAST_1TO8
;
8075 else if (*op_string
== '4')
8076 bcst_type
= BROADCAST_1TO4
;
8077 else if (*op_string
== '2')
8078 bcst_type
= BROADCAST_1TO2
;
8079 else if (*op_string
== '1'
8080 && *(op_string
+1) == '6')
8082 bcst_type
= BROADCAST_1TO16
;
8087 as_bad (_("Unsupported broadcast: `%s'"), saved
);
8092 broadcast_op
.type
= bcst_type
;
8093 broadcast_op
.operand
= this_operand
;
8094 i
.broadcast
= &broadcast_op
;
8096 /* Check masking operation. */
8097 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
8099 /* k0 can't be used for write mask. */
8100 if (mask
->reg_num
== 0)
8102 as_bad (_("`%s' can't be used for write mask"),
8109 mask_op
.mask
= mask
;
8110 mask_op
.zeroing
= 0;
8111 mask_op
.operand
= this_operand
;
8117 goto duplicated_vec_op
;
8119 i
.mask
->mask
= mask
;
8121 /* Only "{z}" is allowed here. No need to check
8122 zeroing mask explicitly. */
8123 if (i
.mask
->operand
!= this_operand
)
8125 as_bad (_("invalid write mask `%s'"), saved
);
8132 /* Check zeroing-flag for masking operation. */
8133 else if (*op_string
== 'z')
8137 mask_op
.mask
= NULL
;
8138 mask_op
.zeroing
= 1;
8139 mask_op
.operand
= this_operand
;
8144 if (i
.mask
->zeroing
)
8147 as_bad (_("duplicated `%s'"), saved
);
8151 i
.mask
->zeroing
= 1;
8153 /* Only "{%k}" is allowed here. No need to check mask
8154 register explicitly. */
8155 if (i
.mask
->operand
!= this_operand
)
8157 as_bad (_("invalid zeroing-masking `%s'"),
8166 goto unknown_vec_op
;
8168 if (*op_string
!= '}')
8170 as_bad (_("missing `}' in `%s'"), saved
);
8177 /* We don't know this one. */
8178 as_bad (_("unknown vector operation: `%s'"), saved
);
8186 i386_immediate (char *imm_start
)
8188 char *save_input_line_pointer
;
8189 char *gotfree_input_line
;
8192 i386_operand_type types
;
8194 operand_type_set (&types
, ~0);
8196 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8198 as_bad (_("at most %d immediate operands are allowed"),
8199 MAX_IMMEDIATE_OPERANDS
);
8203 exp
= &im_expressions
[i
.imm_operands
++];
8204 i
.op
[this_operand
].imms
= exp
;
8206 if (is_space_char (*imm_start
))
8209 save_input_line_pointer
= input_line_pointer
;
8210 input_line_pointer
= imm_start
;
8212 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8213 if (gotfree_input_line
)
8214 input_line_pointer
= gotfree_input_line
;
8216 exp_seg
= expression (exp
);
8220 /* Handle vector operations. */
8221 if (*input_line_pointer
== '{')
8223 input_line_pointer
= check_VecOperations (input_line_pointer
,
8225 if (input_line_pointer
== NULL
)
8229 if (*input_line_pointer
)
8230 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8232 input_line_pointer
= save_input_line_pointer
;
8233 if (gotfree_input_line
)
8235 free (gotfree_input_line
);
8237 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8238 exp
->X_op
= O_illegal
;
8241 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8245 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8246 i386_operand_type types
, const char *imm_start
)
8248 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8251 as_bad (_("missing or invalid immediate expression `%s'"),
8255 else if (exp
->X_op
== O_constant
)
8257 /* Size it properly later. */
8258 i
.types
[this_operand
].bitfield
.imm64
= 1;
8259 /* If not 64bit, sign extend val. */
8260 if (flag_code
!= CODE_64BIT
8261 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8263 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8265 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8266 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8267 && exp_seg
!= absolute_section
8268 && exp_seg
!= text_section
8269 && exp_seg
!= data_section
8270 && exp_seg
!= bss_section
8271 && exp_seg
!= undefined_section
8272 && !bfd_is_com_section (exp_seg
))
8274 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8278 else if (!intel_syntax
&& exp_seg
== reg_section
)
8281 as_bad (_("illegal immediate register operand %s"), imm_start
);
8286 /* This is an address. The size of the address will be
8287 determined later, depending on destination register,
8288 suffix, or the default for the section. */
8289 i
.types
[this_operand
].bitfield
.imm8
= 1;
8290 i
.types
[this_operand
].bitfield
.imm16
= 1;
8291 i
.types
[this_operand
].bitfield
.imm32
= 1;
8292 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8293 i
.types
[this_operand
].bitfield
.imm64
= 1;
8294 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8302 i386_scale (char *scale
)
8305 char *save
= input_line_pointer
;
8307 input_line_pointer
= scale
;
8308 val
= get_absolute_expression ();
8313 i
.log2_scale_factor
= 0;
8316 i
.log2_scale_factor
= 1;
8319 i
.log2_scale_factor
= 2;
8322 i
.log2_scale_factor
= 3;
8326 char sep
= *input_line_pointer
;
8328 *input_line_pointer
= '\0';
8329 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8331 *input_line_pointer
= sep
;
8332 input_line_pointer
= save
;
8336 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8338 as_warn (_("scale factor of %d without an index register"),
8339 1 << i
.log2_scale_factor
);
8340 i
.log2_scale_factor
= 0;
8342 scale
= input_line_pointer
;
8343 input_line_pointer
= save
;
8348 i386_displacement (char *disp_start
, char *disp_end
)
8352 char *save_input_line_pointer
;
8353 char *gotfree_input_line
;
8355 i386_operand_type bigdisp
, types
= anydisp
;
8358 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8360 as_bad (_("at most %d displacement operands are allowed"),
8361 MAX_MEMORY_OPERANDS
);
8365 operand_type_set (&bigdisp
, 0);
8366 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8367 || (!current_templates
->start
->opcode_modifier
.jump
8368 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8370 bigdisp
.bitfield
.disp32
= 1;
8371 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8372 if (flag_code
== CODE_64BIT
)
8376 bigdisp
.bitfield
.disp32s
= 1;
8377 bigdisp
.bitfield
.disp64
= 1;
8380 else if ((flag_code
== CODE_16BIT
) ^ override
)
8382 bigdisp
.bitfield
.disp32
= 0;
8383 bigdisp
.bitfield
.disp16
= 1;
8388 /* For PC-relative branches, the width of the displacement
8389 is dependent upon data size, not address size. */
8390 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8391 if (flag_code
== CODE_64BIT
)
8393 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8394 bigdisp
.bitfield
.disp16
= 1;
8397 bigdisp
.bitfield
.disp32
= 1;
8398 bigdisp
.bitfield
.disp32s
= 1;
8404 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8406 : LONG_MNEM_SUFFIX
));
8407 bigdisp
.bitfield
.disp32
= 1;
8408 if ((flag_code
== CODE_16BIT
) ^ override
)
8410 bigdisp
.bitfield
.disp32
= 0;
8411 bigdisp
.bitfield
.disp16
= 1;
8415 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8418 exp
= &disp_expressions
[i
.disp_operands
];
8419 i
.op
[this_operand
].disps
= exp
;
8421 save_input_line_pointer
= input_line_pointer
;
8422 input_line_pointer
= disp_start
;
8423 END_STRING_AND_SAVE (disp_end
);
8425 #ifndef GCC_ASM_O_HACK
8426 #define GCC_ASM_O_HACK 0
8429 END_STRING_AND_SAVE (disp_end
+ 1);
8430 if (i
.types
[this_operand
].bitfield
.baseIndex
8431 && displacement_string_end
[-1] == '+')
8433 /* This hack is to avoid a warning when using the "o"
8434 constraint within gcc asm statements.
8437 #define _set_tssldt_desc(n,addr,limit,type) \
8438 __asm__ __volatile__ ( \
8440 "movw %w1,2+%0\n\t" \
8442 "movb %b1,4+%0\n\t" \
8443 "movb %4,5+%0\n\t" \
8444 "movb $0,6+%0\n\t" \
8445 "movb %h1,7+%0\n\t" \
8447 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8449 This works great except that the output assembler ends
8450 up looking a bit weird if it turns out that there is
8451 no offset. You end up producing code that looks like:
8464 So here we provide the missing zero. */
8466 *displacement_string_end
= '0';
8469 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8470 if (gotfree_input_line
)
8471 input_line_pointer
= gotfree_input_line
;
8473 exp_seg
= expression (exp
);
8476 if (*input_line_pointer
)
8477 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8479 RESTORE_END_STRING (disp_end
+ 1);
8481 input_line_pointer
= save_input_line_pointer
;
8482 if (gotfree_input_line
)
8484 free (gotfree_input_line
);
8486 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8487 exp
->X_op
= O_illegal
;
8490 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8492 RESTORE_END_STRING (disp_end
);
8498 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8499 i386_operand_type types
, const char *disp_start
)
8501 i386_operand_type bigdisp
;
8504 /* We do this to make sure that the section symbol is in
8505 the symbol table. We will ultimately change the relocation
8506 to be relative to the beginning of the section. */
8507 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8508 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8509 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8511 if (exp
->X_op
!= O_symbol
)
8514 if (S_IS_LOCAL (exp
->X_add_symbol
)
8515 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8516 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8517 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8518 exp
->X_op
= O_subtract
;
8519 exp
->X_op_symbol
= GOT_symbol
;
8520 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8521 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8522 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8523 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8525 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8528 else if (exp
->X_op
== O_absent
8529 || exp
->X_op
== O_illegal
8530 || exp
->X_op
== O_big
)
8533 as_bad (_("missing or invalid displacement expression `%s'"),
8538 else if (flag_code
== CODE_64BIT
8539 && !i
.prefix
[ADDR_PREFIX
]
8540 && exp
->X_op
== O_constant
)
8542 /* Since displacement is signed extended to 64bit, don't allow
8543 disp32 and turn off disp32s if they are out of range. */
8544 i
.types
[this_operand
].bitfield
.disp32
= 0;
8545 if (!fits_in_signed_long (exp
->X_add_number
))
8547 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8548 if (i
.types
[this_operand
].bitfield
.baseindex
)
8550 as_bad (_("0x%lx out range of signed 32bit displacement"),
8551 (long) exp
->X_add_number
);
8557 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8558 else if (exp
->X_op
!= O_constant
8559 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8560 && exp_seg
!= absolute_section
8561 && exp_seg
!= text_section
8562 && exp_seg
!= data_section
8563 && exp_seg
!= bss_section
8564 && exp_seg
!= undefined_section
8565 && !bfd_is_com_section (exp_seg
))
8567 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8572 /* Check if this is a displacement only operand. */
8573 bigdisp
= i
.types
[this_operand
];
8574 bigdisp
.bitfield
.disp8
= 0;
8575 bigdisp
.bitfield
.disp16
= 0;
8576 bigdisp
.bitfield
.disp32
= 0;
8577 bigdisp
.bitfield
.disp32s
= 0;
8578 bigdisp
.bitfield
.disp64
= 0;
8579 if (operand_type_all_zero (&bigdisp
))
8580 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8586 /* Make sure the memory operand we've been dealt is valid.
8587 Return 1 on success, 0 on a failure. */
8590 i386_index_check (const char *operand_string
)
8592 const char *kind
= "base/index";
8593 enum flag_code addr_mode
;
8595 if (i
.prefix
[ADDR_PREFIX
])
8596 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8599 addr_mode
= flag_code
;
8601 #if INFER_ADDR_PREFIX
8602 if (i
.mem_operands
== 0)
8604 /* Infer address prefix from the first memory operand. */
8605 const reg_entry
*addr_reg
= i
.base_reg
;
8607 if (addr_reg
== NULL
)
8608 addr_reg
= i
.index_reg
;
8612 if (addr_reg
->reg_num
== RegEip
8613 || addr_reg
->reg_num
== RegEiz
8614 || addr_reg
->reg_type
.bitfield
.reg32
)
8615 addr_mode
= CODE_32BIT
;
8616 else if (flag_code
!= CODE_64BIT
8617 && addr_reg
->reg_type
.bitfield
.reg16
)
8618 addr_mode
= CODE_16BIT
;
8620 if (addr_mode
!= flag_code
)
8622 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8624 /* Change the size of any displacement too. At most one
8625 of Disp16 or Disp32 is set.
8626 FIXME. There doesn't seem to be any real need for
8627 separate Disp16 and Disp32 flags. The same goes for
8628 Imm16 and Imm32. Removing them would probably clean
8629 up the code quite a lot. */
8630 if (flag_code
!= CODE_64BIT
8631 && (i
.types
[this_operand
].bitfield
.disp16
8632 || i
.types
[this_operand
].bitfield
.disp32
))
8633 i
.types
[this_operand
]
8634 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8641 if (current_templates
->start
->opcode_modifier
.isstring
8642 && !current_templates
->start
->opcode_modifier
.immext
8643 && (current_templates
->end
[-1].opcode_modifier
.isstring
8646 /* Memory operands of string insns are special in that they only allow
8647 a single register (rDI, rSI, or rBX) as their memory address. */
8648 const reg_entry
*expected_reg
;
8649 static const char *di_si
[][2] =
8655 static const char *bx
[] = { "ebx", "bx", "rbx" };
8657 kind
= "string address";
8659 if (current_templates
->start
->opcode_modifier
.repprefixok
)
8661 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8663 if (!type
.bitfield
.baseindex
8664 || ((!i
.mem_operands
!= !intel_syntax
)
8665 && current_templates
->end
[-1].operand_types
[1]
8666 .bitfield
.baseindex
))
8667 type
= current_templates
->end
[-1].operand_types
[1];
8668 expected_reg
= hash_find (reg_hash
,
8669 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8673 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8675 if (i
.base_reg
!= expected_reg
8677 || operand_type_check (i
.types
[this_operand
], disp
))
8679 /* The second memory operand must have the same size as
8683 && !((addr_mode
== CODE_64BIT
8684 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8685 || (addr_mode
== CODE_32BIT
8686 ? i
.base_reg
->reg_type
.bitfield
.reg32
8687 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8690 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8692 intel_syntax
? '[' : '(',
8694 expected_reg
->reg_name
,
8695 intel_syntax
? ']' : ')');
8702 as_bad (_("`%s' is not a valid %s expression"),
8703 operand_string
, kind
);
8708 if (addr_mode
!= CODE_16BIT
)
8710 /* 32-bit/64-bit checks. */
8712 && (addr_mode
== CODE_64BIT
8713 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8714 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8716 || (i
.base_reg
->reg_num
8717 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8719 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8720 && !i
.index_reg
->reg_type
.bitfield
.regymm
8721 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8722 && ((addr_mode
== CODE_64BIT
8723 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8724 || i
.index_reg
->reg_num
== RegRiz
)
8725 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8726 || i
.index_reg
->reg_num
== RegEiz
))
8727 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8730 /* bndmk, bndldx, and bndstx have special restrictions. */
8731 if (current_templates
->start
->base_opcode
== 0xf30f1b
8732 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
8734 /* They cannot use RIP-relative addressing. */
8735 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegRip
)
8737 as_bad (_("`%s' cannot be used here"), operand_string
);
8741 /* bndldx and bndstx ignore their scale factor. */
8742 if (current_templates
->start
->base_opcode
!= 0xf30f1b
8743 && i
.log2_scale_factor
)
8744 as_warn (_("register scaling is being ignored here"));
8749 /* 16-bit checks. */
8751 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8752 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8754 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8755 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8757 && i
.base_reg
->reg_num
< 6
8758 && i
.index_reg
->reg_num
>= 6
8759 && i
.log2_scale_factor
== 0))))
8766 /* Handle vector immediates. */
8769 RC_SAE_immediate (const char *imm_start
)
8771 unsigned int match_found
, j
;
8772 const char *pstr
= imm_start
;
8780 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8782 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8786 rc_op
.type
= RC_NamesTable
[j
].type
;
8787 rc_op
.operand
= this_operand
;
8788 i
.rounding
= &rc_op
;
8792 as_bad (_("duplicated `%s'"), imm_start
);
8795 pstr
+= RC_NamesTable
[j
].len
;
8805 as_bad (_("Missing '}': '%s'"), imm_start
);
8808 /* RC/SAE immediate string should contain nothing more. */;
8811 as_bad (_("Junk after '}': '%s'"), imm_start
);
8815 exp
= &im_expressions
[i
.imm_operands
++];
8816 i
.op
[this_operand
].imms
= exp
;
8818 exp
->X_op
= O_constant
;
8819 exp
->X_add_number
= 0;
8820 exp
->X_add_symbol
= (symbolS
*) 0;
8821 exp
->X_op_symbol
= (symbolS
*) 0;
8823 i
.types
[this_operand
].bitfield
.imm8
= 1;
8827 /* Only string instructions can have a second memory operand, so
8828 reduce current_templates to just those if it contains any. */
8830 maybe_adjust_templates (void)
8832 const insn_template
*t
;
8834 gas_assert (i
.mem_operands
== 1);
8836 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
8837 if (t
->opcode_modifier
.isstring
)
8840 if (t
< current_templates
->end
)
8842 static templates aux_templates
;
8843 bfd_boolean recheck
;
8845 aux_templates
.start
= t
;
8846 for (; t
< current_templates
->end
; ++t
)
8847 if (!t
->opcode_modifier
.isstring
)
8849 aux_templates
.end
= t
;
8851 /* Determine whether to re-check the first memory operand. */
8852 recheck
= (aux_templates
.start
!= current_templates
->start
8853 || t
!= current_templates
->end
);
8855 current_templates
= &aux_templates
;
8860 if (i
.memop1_string
!= NULL
8861 && i386_index_check (i
.memop1_string
) == 0)
8870 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8874 i386_att_operand (char *operand_string
)
8878 char *op_string
= operand_string
;
8880 if (is_space_char (*op_string
))
8883 /* We check for an absolute prefix (differentiating,
8884 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8885 if (*op_string
== ABSOLUTE_PREFIX
)
8888 if (is_space_char (*op_string
))
8890 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8893 /* Check if operand is a register. */
8894 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8896 i386_operand_type temp
;
8898 /* Check for a segment override by searching for ':' after a
8899 segment register. */
8901 if (is_space_char (*op_string
))
8903 if (*op_string
== ':'
8904 && (r
->reg_type
.bitfield
.sreg2
8905 || r
->reg_type
.bitfield
.sreg3
))
8910 i
.seg
[i
.mem_operands
] = &es
;
8913 i
.seg
[i
.mem_operands
] = &cs
;
8916 i
.seg
[i
.mem_operands
] = &ss
;
8919 i
.seg
[i
.mem_operands
] = &ds
;
8922 i
.seg
[i
.mem_operands
] = &fs
;
8925 i
.seg
[i
.mem_operands
] = &gs
;
8929 /* Skip the ':' and whitespace. */
8931 if (is_space_char (*op_string
))
8934 if (!is_digit_char (*op_string
)
8935 && !is_identifier_char (*op_string
)
8936 && *op_string
!= '('
8937 && *op_string
!= ABSOLUTE_PREFIX
)
8939 as_bad (_("bad memory operand `%s'"), op_string
);
8942 /* Handle case of %es:*foo. */
8943 if (*op_string
== ABSOLUTE_PREFIX
)
8946 if (is_space_char (*op_string
))
8948 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8950 goto do_memory_reference
;
8953 /* Handle vector operations. */
8954 if (*op_string
== '{')
8956 op_string
= check_VecOperations (op_string
, NULL
);
8957 if (op_string
== NULL
)
8963 as_bad (_("junk `%s' after register"), op_string
);
8967 temp
.bitfield
.baseindex
= 0;
8968 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8970 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8971 i
.op
[this_operand
].regs
= r
;
8974 else if (*op_string
== REGISTER_PREFIX
)
8976 as_bad (_("bad register name `%s'"), op_string
);
8979 else if (*op_string
== IMMEDIATE_PREFIX
)
8982 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8984 as_bad (_("immediate operand illegal with absolute jump"));
8987 if (!i386_immediate (op_string
))
8990 else if (RC_SAE_immediate (operand_string
))
8992 /* If it is a RC or SAE immediate, do nothing. */
8995 else if (is_digit_char (*op_string
)
8996 || is_identifier_char (*op_string
)
8997 || *op_string
== '"'
8998 || *op_string
== '(')
9000 /* This is a memory reference of some sort. */
9003 /* Start and end of displacement string expression (if found). */
9004 char *displacement_string_start
;
9005 char *displacement_string_end
;
9008 do_memory_reference
:
9009 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
9011 if ((i
.mem_operands
== 1
9012 && !current_templates
->start
->opcode_modifier
.isstring
)
9013 || i
.mem_operands
== 2)
9015 as_bad (_("too many memory references for `%s'"),
9016 current_templates
->start
->name
);
9020 /* Check for base index form. We detect the base index form by
9021 looking for an ')' at the end of the operand, searching
9022 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9024 base_string
= op_string
+ strlen (op_string
);
9026 /* Handle vector operations. */
9027 vop_start
= strchr (op_string
, '{');
9028 if (vop_start
&& vop_start
< base_string
)
9030 if (check_VecOperations (vop_start
, base_string
) == NULL
)
9032 base_string
= vop_start
;
9036 if (is_space_char (*base_string
))
9039 /* If we only have a displacement, set-up for it to be parsed later. */
9040 displacement_string_start
= op_string
;
9041 displacement_string_end
= base_string
+ 1;
9043 if (*base_string
== ')')
9046 unsigned int parens_balanced
= 1;
9047 /* We've already checked that the number of left & right ()'s are
9048 equal, so this loop will not be infinite. */
9052 if (*base_string
== ')')
9054 if (*base_string
== '(')
9057 while (parens_balanced
);
9059 temp_string
= base_string
;
9061 /* Skip past '(' and whitespace. */
9063 if (is_space_char (*base_string
))
9066 if (*base_string
== ','
9067 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
9070 displacement_string_end
= temp_string
;
9072 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9076 base_string
= end_op
;
9077 if (is_space_char (*base_string
))
9081 /* There may be an index reg or scale factor here. */
9082 if (*base_string
== ',')
9085 if (is_space_char (*base_string
))
9088 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
9091 base_string
= end_op
;
9092 if (is_space_char (*base_string
))
9094 if (*base_string
== ',')
9097 if (is_space_char (*base_string
))
9100 else if (*base_string
!= ')')
9102 as_bad (_("expecting `,' or `)' "
9103 "after index register in `%s'"),
9108 else if (*base_string
== REGISTER_PREFIX
)
9110 end_op
= strchr (base_string
, ',');
9113 as_bad (_("bad register name `%s'"), base_string
);
9117 /* Check for scale factor. */
9118 if (*base_string
!= ')')
9120 char *end_scale
= i386_scale (base_string
);
9125 base_string
= end_scale
;
9126 if (is_space_char (*base_string
))
9128 if (*base_string
!= ')')
9130 as_bad (_("expecting `)' "
9131 "after scale factor in `%s'"),
9136 else if (!i
.index_reg
)
9138 as_bad (_("expecting index register or scale factor "
9139 "after `,'; got '%c'"),
9144 else if (*base_string
!= ')')
9146 as_bad (_("expecting `,' or `)' "
9147 "after base register in `%s'"),
9152 else if (*base_string
== REGISTER_PREFIX
)
9154 end_op
= strchr (base_string
, ',');
9157 as_bad (_("bad register name `%s'"), base_string
);
9162 /* If there's an expression beginning the operand, parse it,
9163 assuming displacement_string_start and
9164 displacement_string_end are meaningful. */
9165 if (displacement_string_start
!= displacement_string_end
)
9167 if (!i386_displacement (displacement_string_start
,
9168 displacement_string_end
))
9172 /* Special case for (%dx) while doing input/output op. */
9174 && operand_type_equal (&i
.base_reg
->reg_type
,
9175 ®16_inoutportreg
)
9177 && i
.log2_scale_factor
== 0
9178 && i
.seg
[i
.mem_operands
] == 0
9179 && !operand_type_check (i
.types
[this_operand
], disp
))
9181 i
.types
[this_operand
] = inoutportreg
;
9185 if (i386_index_check (operand_string
) == 0)
9187 i
.types
[this_operand
].bitfield
.mem
= 1;
9188 if (i
.mem_operands
== 0)
9189 i
.memop1_string
= xstrdup (operand_string
);
9194 /* It's not a memory operand; argh! */
9195 as_bad (_("invalid char %s beginning operand %d `%s'"),
9196 output_invalid (*op_string
),
9201 return 1; /* Normal return. */
9204 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9205 that an rs_machine_dependent frag may reach. */
9208 i386_frag_max_var (fragS
*frag
)
9210 /* The only relaxable frags are for jumps.
9211 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9212 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9213 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9216 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9218 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9220 /* STT_GNU_IFUNC symbol must go through PLT. */
9221 if ((symbol_get_bfdsym (fr_symbol
)->flags
9222 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9225 if (!S_IS_EXTERNAL (fr_symbol
))
9226 /* Symbol may be weak or local. */
9227 return !S_IS_WEAK (fr_symbol
);
9229 /* Global symbols with non-default visibility can't be preempted. */
9230 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9233 if (fr_var
!= NO_RELOC
)
9234 switch ((enum bfd_reloc_code_real
) fr_var
)
9236 case BFD_RELOC_386_PLT32
:
9237 case BFD_RELOC_X86_64_PLT32
:
9238 /* Symbol with PLT relocation may be preempted. */
9244 /* Global symbols with default visibility in a shared library may be
9245 preempted by another definition. */
9250 /* md_estimate_size_before_relax()
9252 Called just before relax() for rs_machine_dependent frags. The x86
9253 assembler uses these frags to handle variable size jump
9256 Any symbol that is now undefined will not become defined.
9257 Return the correct fr_subtype in the frag.
9258 Return the initial "guess for variable size of frag" to caller.
9259 The guess is actually the growth beyond the fixed part. Whatever
9260 we do to grow the fixed or variable part contributes to our
9264 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9266 /* We've already got fragP->fr_subtype right; all we have to do is
9267 check for un-relaxable symbols. On an ELF system, we can't relax
9268 an externally visible symbol, because it may be overridden by a
9270 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9271 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9273 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9276 #if defined (OBJ_COFF) && defined (TE_PE)
9277 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9278 && S_IS_WEAK (fragP
->fr_symbol
))
9282 /* Symbol is undefined in this segment, or we need to keep a
9283 reloc so that weak symbols can be overridden. */
9284 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9285 enum bfd_reloc_code_real reloc_type
;
9286 unsigned char *opcode
;
9289 if (fragP
->fr_var
!= NO_RELOC
)
9290 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9292 reloc_type
= BFD_RELOC_16_PCREL
;
9294 reloc_type
= BFD_RELOC_32_PCREL
;
9296 old_fr_fix
= fragP
->fr_fix
;
9297 opcode
= (unsigned char *) fragP
->fr_opcode
;
9299 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9302 /* Make jmp (0xeb) a (d)word displacement jump. */
9304 fragP
->fr_fix
+= size
;
9305 fix_new (fragP
, old_fr_fix
, size
,
9307 fragP
->fr_offset
, 1,
9313 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9315 /* Negate the condition, and branch past an
9316 unconditional jump. */
9319 /* Insert an unconditional jump. */
9321 /* We added two extra opcode bytes, and have a two byte
9323 fragP
->fr_fix
+= 2 + 2;
9324 fix_new (fragP
, old_fr_fix
+ 2, 2,
9326 fragP
->fr_offset
, 1,
9333 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9338 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9340 fragP
->fr_offset
, 1,
9342 fixP
->fx_signed
= 1;
9346 /* This changes the byte-displacement jump 0x7N
9347 to the (d)word-displacement jump 0x0f,0x8N. */
9348 opcode
[1] = opcode
[0] + 0x10;
9349 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9350 /* We've added an opcode byte. */
9351 fragP
->fr_fix
+= 1 + size
;
9352 fix_new (fragP
, old_fr_fix
+ 1, size
,
9354 fragP
->fr_offset
, 1,
9359 BAD_CASE (fragP
->fr_subtype
);
9363 return fragP
->fr_fix
- old_fr_fix
;
9366 /* Guess size depending on current relax state. Initially the relax
9367 state will correspond to a short jump and we return 1, because
9368 the variable part of the frag (the branch offset) is one byte
9369 long. However, we can relax a section more than once and in that
9370 case we must either set fr_subtype back to the unrelaxed state,
9371 or return the value for the appropriate branch. */
9372 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9375 /* Called after relax() is finished.
9377 In: Address of frag.
9378 fr_type == rs_machine_dependent.
9379 fr_subtype is what the address relaxed to.
9381 Out: Any fixSs and constants are set up.
9382 Caller will turn frag into a ".space 0". */
9385 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9388 unsigned char *opcode
;
9389 unsigned char *where_to_put_displacement
= NULL
;
9390 offsetT target_address
;
9391 offsetT opcode_address
;
9392 unsigned int extension
= 0;
9393 offsetT displacement_from_opcode_start
;
9395 opcode
= (unsigned char *) fragP
->fr_opcode
;
9397 /* Address we want to reach in file space. */
9398 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9400 /* Address opcode resides at in file space. */
9401 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9403 /* Displacement from opcode start to fill into instruction. */
9404 displacement_from_opcode_start
= target_address
- opcode_address
;
9406 if ((fragP
->fr_subtype
& BIG
) == 0)
9408 /* Don't have to change opcode. */
9409 extension
= 1; /* 1 opcode + 1 displacement */
9410 where_to_put_displacement
= &opcode
[1];
9414 if (no_cond_jump_promotion
9415 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9416 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9417 _("long jump required"));
9419 switch (fragP
->fr_subtype
)
9421 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9422 extension
= 4; /* 1 opcode + 4 displacement */
9424 where_to_put_displacement
= &opcode
[1];
9427 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9428 extension
= 2; /* 1 opcode + 2 displacement */
9430 where_to_put_displacement
= &opcode
[1];
9433 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9434 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9435 extension
= 5; /* 2 opcode + 4 displacement */
9436 opcode
[1] = opcode
[0] + 0x10;
9437 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9438 where_to_put_displacement
= &opcode
[2];
9441 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9442 extension
= 3; /* 2 opcode + 2 displacement */
9443 opcode
[1] = opcode
[0] + 0x10;
9444 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9445 where_to_put_displacement
= &opcode
[2];
9448 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9453 where_to_put_displacement
= &opcode
[3];
9457 BAD_CASE (fragP
->fr_subtype
);
9462 /* If size if less then four we are sure that the operand fits,
9463 but if it's 4, then it could be that the displacement is larger
9465 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9467 && ((addressT
) (displacement_from_opcode_start
- extension
9468 + ((addressT
) 1 << 31))
9469 > (((addressT
) 2 << 31) - 1)))
9471 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9472 _("jump target out of range"));
9473 /* Make us emit 0. */
9474 displacement_from_opcode_start
= extension
;
9476 /* Now put displacement after opcode. */
9477 md_number_to_chars ((char *) where_to_put_displacement
,
9478 (valueT
) (displacement_from_opcode_start
- extension
),
9479 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9480 fragP
->fr_fix
+= extension
;
9483 /* Apply a fixup (fixP) to segment data, once it has been determined
9484 by our caller that we have all the info we need to fix it up.
9486 Parameter valP is the pointer to the value of the bits.
9488 On the 386, immediates, displacements, and data pointers are all in
9489 the same (little-endian) format, so we don't need to care about which
9493 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9495 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9496 valueT value
= *valP
;
9498 #if !defined (TE_Mach)
9501 switch (fixP
->fx_r_type
)
9507 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9510 case BFD_RELOC_X86_64_32S
:
9511 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9514 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9517 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9522 if (fixP
->fx_addsy
!= NULL
9523 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9524 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9525 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9526 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9527 && !use_rela_relocations
)
9529 /* This is a hack. There should be a better way to handle this.
9530 This covers for the fact that bfd_install_relocation will
9531 subtract the current location (for partial_inplace, PC relative
9532 relocations); see more below. */
9536 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9539 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9541 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9544 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9547 || (symbol_section_p (fixP
->fx_addsy
)
9548 && sym_seg
!= absolute_section
))
9549 && !generic_force_reloc (fixP
))
9551 /* Yes, we add the values in twice. This is because
9552 bfd_install_relocation subtracts them out again. I think
9553 bfd_install_relocation is broken, but I don't dare change
9555 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9559 #if defined (OBJ_COFF) && defined (TE_PE)
9560 /* For some reason, the PE format does not store a
9561 section address offset for a PC relative symbol. */
9562 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9563 || S_IS_WEAK (fixP
->fx_addsy
))
9564 value
+= md_pcrel_from (fixP
);
9567 #if defined (OBJ_COFF) && defined (TE_PE)
9568 if (fixP
->fx_addsy
!= NULL
9569 && S_IS_WEAK (fixP
->fx_addsy
)
9570 /* PR 16858: Do not modify weak function references. */
9571 && ! fixP
->fx_pcrel
)
9573 #if !defined (TE_PEP)
9574 /* For x86 PE weak function symbols are neither PC-relative
9575 nor do they set S_IS_FUNCTION. So the only reliable way
9576 to detect them is to check the flags of their containing
9578 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9579 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9583 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9587 /* Fix a few things - the dynamic linker expects certain values here,
9588 and we must not disappoint it. */
9589 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9590 if (IS_ELF
&& fixP
->fx_addsy
)
9591 switch (fixP
->fx_r_type
)
9593 case BFD_RELOC_386_PLT32
:
9594 case BFD_RELOC_X86_64_PLT32
:
9595 /* Make the jump instruction point to the address of the operand. At
9596 runtime we merely add the offset to the actual PLT entry. */
9600 case BFD_RELOC_386_TLS_GD
:
9601 case BFD_RELOC_386_TLS_LDM
:
9602 case BFD_RELOC_386_TLS_IE_32
:
9603 case BFD_RELOC_386_TLS_IE
:
9604 case BFD_RELOC_386_TLS_GOTIE
:
9605 case BFD_RELOC_386_TLS_GOTDESC
:
9606 case BFD_RELOC_X86_64_TLSGD
:
9607 case BFD_RELOC_X86_64_TLSLD
:
9608 case BFD_RELOC_X86_64_GOTTPOFF
:
9609 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9610 value
= 0; /* Fully resolved at runtime. No addend. */
9612 case BFD_RELOC_386_TLS_LE
:
9613 case BFD_RELOC_386_TLS_LDO_32
:
9614 case BFD_RELOC_386_TLS_LE_32
:
9615 case BFD_RELOC_X86_64_DTPOFF32
:
9616 case BFD_RELOC_X86_64_DTPOFF64
:
9617 case BFD_RELOC_X86_64_TPOFF32
:
9618 case BFD_RELOC_X86_64_TPOFF64
:
9619 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9622 case BFD_RELOC_386_TLS_DESC_CALL
:
9623 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9624 value
= 0; /* Fully resolved at runtime. No addend. */
9625 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9629 case BFD_RELOC_VTABLE_INHERIT
:
9630 case BFD_RELOC_VTABLE_ENTRY
:
9637 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9639 #endif /* !defined (TE_Mach) */
9641 /* Are we finished with this relocation now? */
9642 if (fixP
->fx_addsy
== NULL
)
9644 #if defined (OBJ_COFF) && defined (TE_PE)
9645 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9648 /* Remember value for tc_gen_reloc. */
9649 fixP
->fx_addnumber
= value
;
9650 /* Clear out the frag for now. */
9654 else if (use_rela_relocations
)
9656 fixP
->fx_no_overflow
= 1;
9657 /* Remember value for tc_gen_reloc. */
9658 fixP
->fx_addnumber
= value
;
9662 md_number_to_chars (p
, value
, fixP
->fx_size
);
9666 md_atof (int type
, char *litP
, int *sizeP
)
9668 /* This outputs the LITTLENUMs in REVERSE order;
9669 in accord with the bigendian 386. */
9670 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9673 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9676 output_invalid (int c
)
9679 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9682 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9683 "(0x%x)", (unsigned char) c
);
9684 return output_invalid_buf
;
9687 /* REG_STRING starts *before* REGISTER_PREFIX. */
9689 static const reg_entry
*
9690 parse_real_register (char *reg_string
, char **end_op
)
9692 char *s
= reg_string
;
9694 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9697 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9698 if (*s
== REGISTER_PREFIX
)
9701 if (is_space_char (*s
))
9705 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9707 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9708 return (const reg_entry
*) NULL
;
9712 /* For naked regs, make sure that we are not dealing with an identifier.
9713 This prevents confusing an identifier like `eax_var' with register
9715 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9716 return (const reg_entry
*) NULL
;
9720 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9722 /* Handle floating point regs, allowing spaces in the (i) part. */
9723 if (r
== i386_regtab
/* %st is first entry of table */)
9725 if (is_space_char (*s
))
9730 if (is_space_char (*s
))
9732 if (*s
>= '0' && *s
<= '7')
9736 if (is_space_char (*s
))
9741 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9746 /* We have "%st(" then garbage. */
9747 return (const reg_entry
*) NULL
;
9751 if (r
== NULL
|| allow_pseudo_reg
)
9754 if (operand_type_all_zero (&r
->reg_type
))
9755 return (const reg_entry
*) NULL
;
9757 if ((r
->reg_type
.bitfield
.reg32
9758 || r
->reg_type
.bitfield
.sreg3
9759 || r
->reg_type
.bitfield
.control
9760 || r
->reg_type
.bitfield
.debug
9761 || r
->reg_type
.bitfield
.test
)
9762 && !cpu_arch_flags
.bitfield
.cpui386
)
9763 return (const reg_entry
*) NULL
;
9765 if (r
->reg_type
.bitfield
.floatreg
9766 && !cpu_arch_flags
.bitfield
.cpu8087
9767 && !cpu_arch_flags
.bitfield
.cpu287
9768 && !cpu_arch_flags
.bitfield
.cpu387
)
9769 return (const reg_entry
*) NULL
;
9771 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpuregmmx
)
9772 return (const reg_entry
*) NULL
;
9774 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpuregxmm
)
9775 return (const reg_entry
*) NULL
;
9777 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuregymm
)
9778 return (const reg_entry
*) NULL
;
9780 if (r
->reg_type
.bitfield
.regzmm
&& !cpu_arch_flags
.bitfield
.cpuregzmm
)
9781 return (const reg_entry
*) NULL
;
9783 if (r
->reg_type
.bitfield
.regmask
9784 && !cpu_arch_flags
.bitfield
.cpuregmask
)
9785 return (const reg_entry
*) NULL
;
9787 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9788 if (!allow_index_reg
9789 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9790 return (const reg_entry
*) NULL
;
9792 /* Upper 16 vector register is only available with VREX in 64bit
9794 if ((r
->reg_flags
& RegVRex
))
9796 if (i
.vec_encoding
== vex_encoding_default
)
9797 i
.vec_encoding
= vex_encoding_evex
;
9799 if (!cpu_arch_flags
.bitfield
.cpuvrex
9800 || i
.vec_encoding
!= vex_encoding_evex
9801 || flag_code
!= CODE_64BIT
)
9802 return (const reg_entry
*) NULL
;
9805 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9806 || r
->reg_type
.bitfield
.reg64
)
9807 && (!cpu_arch_flags
.bitfield
.cpulm
9808 || !operand_type_equal (&r
->reg_type
, &control
))
9809 && flag_code
!= CODE_64BIT
)
9810 return (const reg_entry
*) NULL
;
9812 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9813 return (const reg_entry
*) NULL
;
9818 /* REG_STRING starts *before* REGISTER_PREFIX. */
9820 static const reg_entry
*
9821 parse_register (char *reg_string
, char **end_op
)
9825 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9826 r
= parse_real_register (reg_string
, end_op
);
9831 char *save
= input_line_pointer
;
9835 input_line_pointer
= reg_string
;
9836 c
= get_symbol_name (®_string
);
9837 symbolP
= symbol_find (reg_string
);
9838 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9840 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9842 know (e
->X_op
== O_register
);
9843 know (e
->X_add_number
>= 0
9844 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9845 r
= i386_regtab
+ e
->X_add_number
;
9846 if ((r
->reg_flags
& RegVRex
))
9847 i
.vec_encoding
= vex_encoding_evex
;
9848 *end_op
= input_line_pointer
;
9850 *input_line_pointer
= c
;
9851 input_line_pointer
= save
;
9857 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9860 char *end
= input_line_pointer
;
9863 r
= parse_register (name
, &input_line_pointer
);
9864 if (r
&& end
<= input_line_pointer
)
9866 *nextcharP
= *input_line_pointer
;
9867 *input_line_pointer
= 0;
9868 e
->X_op
= O_register
;
9869 e
->X_add_number
= r
- i386_regtab
;
9872 input_line_pointer
= end
;
9874 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9878 md_operand (expressionS
*e
)
9883 switch (*input_line_pointer
)
9885 case REGISTER_PREFIX
:
9886 r
= parse_real_register (input_line_pointer
, &end
);
9889 e
->X_op
= O_register
;
9890 e
->X_add_number
= r
- i386_regtab
;
9891 input_line_pointer
= end
;
9896 gas_assert (intel_syntax
);
9897 end
= input_line_pointer
++;
9899 if (*input_line_pointer
== ']')
9901 ++input_line_pointer
;
9902 e
->X_op_symbol
= make_expr_symbol (e
);
9903 e
->X_add_symbol
= NULL
;
9904 e
->X_add_number
= 0;
9910 input_line_pointer
= end
;
9917 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9918 const char *md_shortopts
= "kVQ:sqn";
9920 const char *md_shortopts
= "qn";
9923 #define OPTION_32 (OPTION_MD_BASE + 0)
9924 #define OPTION_64 (OPTION_MD_BASE + 1)
9925 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9926 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9927 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9928 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9929 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9930 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9931 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9932 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9933 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9934 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9935 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9936 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9937 #define OPTION_X32 (OPTION_MD_BASE + 14)
9938 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9939 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9940 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9941 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9942 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9943 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9944 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9945 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9946 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9947 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9948 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
9950 struct option md_longopts
[] =
9952 {"32", no_argument
, NULL
, OPTION_32
},
9953 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9954 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9955 {"64", no_argument
, NULL
, OPTION_64
},
9957 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9958 {"x32", no_argument
, NULL
, OPTION_X32
},
9959 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
9961 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9962 {"march", required_argument
, NULL
, OPTION_MARCH
},
9963 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9964 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9965 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9966 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9967 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9968 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9969 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9970 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9971 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9972 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9973 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9974 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9975 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9976 # if defined (TE_PE) || defined (TE_PEP)
9977 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9979 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
9980 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
9981 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
9982 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9983 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
9984 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
9985 {NULL
, no_argument
, NULL
, 0}
9987 size_t md_longopts_size
= sizeof (md_longopts
);
9990 md_parse_option (int c
, const char *arg
)
9993 char *arch
, *next
, *saved
;
9998 optimize_align_code
= 0;
10002 quiet_warnings
= 1;
10005 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10006 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10007 should be emitted or not. FIXME: Not implemented. */
10011 /* -V: SVR4 argument to print version ID. */
10013 print_version_id ();
10016 /* -k: Ignore for FreeBSD compatibility. */
10021 /* -s: On i386 Solaris, this tells the native assembler to use
10022 .stab instead of .stab.excl. We always use .stab anyhow. */
10025 case OPTION_MSHARED
:
10029 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10030 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10033 const char **list
, **l
;
10035 list
= bfd_target_list ();
10036 for (l
= list
; *l
!= NULL
; l
++)
10037 if (CONST_STRNEQ (*l
, "elf64-x86-64")
10038 || strcmp (*l
, "coff-x86-64") == 0
10039 || strcmp (*l
, "pe-x86-64") == 0
10040 || strcmp (*l
, "pei-x86-64") == 0
10041 || strcmp (*l
, "mach-o-x86-64") == 0)
10043 default_arch
= "x86_64";
10047 as_fatal (_("no compiled in support for x86_64"));
10053 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10057 const char **list
, **l
;
10059 list
= bfd_target_list ();
10060 for (l
= list
; *l
!= NULL
; l
++)
10061 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
10063 default_arch
= "x86_64:32";
10067 as_fatal (_("no compiled in support for 32bit x86_64"));
10071 as_fatal (_("32bit x86_64 is only supported for ELF"));
10076 default_arch
= "i386";
10079 case OPTION_DIVIDE
:
10080 #ifdef SVR4_COMMENT_CHARS
10085 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
10087 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
10091 i386_comment_chars
= n
;
10097 saved
= xstrdup (arg
);
10099 /* Allow -march=+nosse. */
10105 as_fatal (_("invalid -march= option: `%s'"), arg
);
10106 next
= strchr (arch
, '+');
10109 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10111 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
10114 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10117 cpu_arch_name
= cpu_arch
[j
].name
;
10118 cpu_sub_arch_name
= NULL
;
10119 cpu_arch_flags
= cpu_arch
[j
].flags
;
10120 cpu_arch_isa
= cpu_arch
[j
].type
;
10121 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
10122 if (!cpu_arch_tune_set
)
10124 cpu_arch_tune
= cpu_arch_isa
;
10125 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10129 else if (*cpu_arch
[j
].name
== '.'
10130 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
10132 /* ISA extension. */
10133 i386_cpu_flags flags
;
10135 flags
= cpu_flags_or (cpu_arch_flags
,
10136 cpu_arch
[j
].flags
);
10138 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10140 if (cpu_sub_arch_name
)
10142 char *name
= cpu_sub_arch_name
;
10143 cpu_sub_arch_name
= concat (name
,
10145 (const char *) NULL
);
10149 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
10150 cpu_arch_flags
= flags
;
10151 cpu_arch_isa_flags
= flags
;
10157 if (j
>= ARRAY_SIZE (cpu_arch
))
10159 /* Disable an ISA extension. */
10160 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10161 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
10163 i386_cpu_flags flags
;
10165 flags
= cpu_flags_and_not (cpu_arch_flags
,
10166 cpu_noarch
[j
].flags
);
10167 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10169 if (cpu_sub_arch_name
)
10171 char *name
= cpu_sub_arch_name
;
10172 cpu_sub_arch_name
= concat (arch
,
10173 (const char *) NULL
);
10177 cpu_sub_arch_name
= xstrdup (arch
);
10178 cpu_arch_flags
= flags
;
10179 cpu_arch_isa_flags
= flags
;
10184 if (j
>= ARRAY_SIZE (cpu_noarch
))
10185 j
= ARRAY_SIZE (cpu_arch
);
10188 if (j
>= ARRAY_SIZE (cpu_arch
))
10189 as_fatal (_("invalid -march= option: `%s'"), arg
);
10193 while (next
!= NULL
);
10199 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10200 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10202 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
10204 cpu_arch_tune_set
= 1;
10205 cpu_arch_tune
= cpu_arch
[j
].type
;
10206 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10210 if (j
>= ARRAY_SIZE (cpu_arch
))
10211 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10214 case OPTION_MMNEMONIC
:
10215 if (strcasecmp (arg
, "att") == 0)
10216 intel_mnemonic
= 0;
10217 else if (strcasecmp (arg
, "intel") == 0)
10218 intel_mnemonic
= 1;
10220 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10223 case OPTION_MSYNTAX
:
10224 if (strcasecmp (arg
, "att") == 0)
10226 else if (strcasecmp (arg
, "intel") == 0)
10229 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10232 case OPTION_MINDEX_REG
:
10233 allow_index_reg
= 1;
10236 case OPTION_MNAKED_REG
:
10237 allow_naked_reg
= 1;
10240 case OPTION_MOLD_GCC
:
10244 case OPTION_MSSE2AVX
:
10248 case OPTION_MSSE_CHECK
:
10249 if (strcasecmp (arg
, "error") == 0)
10250 sse_check
= check_error
;
10251 else if (strcasecmp (arg
, "warning") == 0)
10252 sse_check
= check_warning
;
10253 else if (strcasecmp (arg
, "none") == 0)
10254 sse_check
= check_none
;
10256 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10259 case OPTION_MOPERAND_CHECK
:
10260 if (strcasecmp (arg
, "error") == 0)
10261 operand_check
= check_error
;
10262 else if (strcasecmp (arg
, "warning") == 0)
10263 operand_check
= check_warning
;
10264 else if (strcasecmp (arg
, "none") == 0)
10265 operand_check
= check_none
;
10267 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10270 case OPTION_MAVXSCALAR
:
10271 if (strcasecmp (arg
, "128") == 0)
10272 avxscalar
= vex128
;
10273 else if (strcasecmp (arg
, "256") == 0)
10274 avxscalar
= vex256
;
10276 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10279 case OPTION_MADD_BND_PREFIX
:
10280 add_bnd_prefix
= 1;
10283 case OPTION_MEVEXLIG
:
10284 if (strcmp (arg
, "128") == 0)
10285 evexlig
= evexl128
;
10286 else if (strcmp (arg
, "256") == 0)
10287 evexlig
= evexl256
;
10288 else if (strcmp (arg
, "512") == 0)
10289 evexlig
= evexl512
;
10291 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10294 case OPTION_MEVEXRCIG
:
10295 if (strcmp (arg
, "rne") == 0)
10297 else if (strcmp (arg
, "rd") == 0)
10299 else if (strcmp (arg
, "ru") == 0)
10301 else if (strcmp (arg
, "rz") == 0)
10304 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10307 case OPTION_MEVEXWIG
:
10308 if (strcmp (arg
, "0") == 0)
10310 else if (strcmp (arg
, "1") == 0)
10313 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10316 # if defined (TE_PE) || defined (TE_PEP)
10317 case OPTION_MBIG_OBJ
:
10322 case OPTION_MOMIT_LOCK_PREFIX
:
10323 if (strcasecmp (arg
, "yes") == 0)
10324 omit_lock_prefix
= 1;
10325 else if (strcasecmp (arg
, "no") == 0)
10326 omit_lock_prefix
= 0;
10328 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10331 case OPTION_MFENCE_AS_LOCK_ADD
:
10332 if (strcasecmp (arg
, "yes") == 0)
10334 else if (strcasecmp (arg
, "no") == 0)
10337 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10340 case OPTION_MRELAX_RELOCATIONS
:
10341 if (strcasecmp (arg
, "yes") == 0)
10342 generate_relax_relocations
= 1;
10343 else if (strcasecmp (arg
, "no") == 0)
10344 generate_relax_relocations
= 0;
10346 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10349 case OPTION_MAMD64
:
10353 case OPTION_MINTEL64
:
10363 #define MESSAGE_TEMPLATE \
10367 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10368 int *left_p
, const char *name
, int len
)
10370 int size
= sizeof (MESSAGE_TEMPLATE
);
10371 int left
= *left_p
;
10373 /* Reserve 2 spaces for ", " or ",\0" */
10376 /* Check if there is any room. */
10384 p
= mempcpy (p
, name
, len
);
10388 /* Output the current message now and start a new one. */
10391 fprintf (stream
, "%s\n", message
);
10393 left
= size
- (start
- message
) - len
- 2;
10395 gas_assert (left
>= 0);
10397 p
= mempcpy (p
, name
, len
);
10405 show_arch (FILE *stream
, int ext
, int check
)
10407 static char message
[] = MESSAGE_TEMPLATE
;
10408 char *start
= message
+ 27;
10410 int size
= sizeof (MESSAGE_TEMPLATE
);
10417 left
= size
- (start
- message
);
10418 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10420 /* Should it be skipped? */
10421 if (cpu_arch
[j
].skip
)
10424 name
= cpu_arch
[j
].name
;
10425 len
= cpu_arch
[j
].len
;
10428 /* It is an extension. Skip if we aren't asked to show it. */
10439 /* It is an processor. Skip if we show only extension. */
10442 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10444 /* It is an impossible processor - skip. */
10448 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10451 /* Display disabled extensions. */
10453 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10455 name
= cpu_noarch
[j
].name
;
10456 len
= cpu_noarch
[j
].len
;
10457 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10462 fprintf (stream
, "%s\n", message
);
10466 md_show_usage (FILE *stream
)
10468 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10469 fprintf (stream
, _("\
10471 -V print assembler version number\n\
10474 fprintf (stream
, _("\
10475 -n Do not optimize code alignment\n\
10476 -q quieten some warnings\n"));
10477 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10478 fprintf (stream
, _("\
10481 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10482 || defined (TE_PE) || defined (TE_PEP))
10483 fprintf (stream
, _("\
10484 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10486 #ifdef SVR4_COMMENT_CHARS
10487 fprintf (stream
, _("\
10488 --divide do not treat `/' as a comment character\n"));
10490 fprintf (stream
, _("\
10491 --divide ignored\n"));
10493 fprintf (stream
, _("\
10494 -march=CPU[,+EXTENSION...]\n\
10495 generate code for CPU and EXTENSION, CPU is one of:\n"));
10496 show_arch (stream
, 0, 1);
10497 fprintf (stream
, _("\
10498 EXTENSION is combination of:\n"));
10499 show_arch (stream
, 1, 0);
10500 fprintf (stream
, _("\
10501 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10502 show_arch (stream
, 0, 0);
10503 fprintf (stream
, _("\
10504 -msse2avx encode SSE instructions with VEX prefix\n"));
10505 fprintf (stream
, _("\
10506 -msse-check=[none|error|warning]\n\
10507 check SSE instructions\n"));
10508 fprintf (stream
, _("\
10509 -moperand-check=[none|error|warning]\n\
10510 check operand combinations for validity\n"));
10511 fprintf (stream
, _("\
10512 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10514 fprintf (stream
, _("\
10515 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10517 fprintf (stream
, _("\
10518 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10519 for EVEX.W bit ignored instructions\n"));
10520 fprintf (stream
, _("\
10521 -mevexrcig=[rne|rd|ru|rz]\n\
10522 encode EVEX instructions with specific EVEX.RC value\n\
10523 for SAE-only ignored instructions\n"));
10524 fprintf (stream
, _("\
10525 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10526 fprintf (stream
, _("\
10527 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10528 fprintf (stream
, _("\
10529 -mindex-reg support pseudo index registers\n"));
10530 fprintf (stream
, _("\
10531 -mnaked-reg don't require `%%' prefix for registers\n"));
10532 fprintf (stream
, _("\
10533 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10534 fprintf (stream
, _("\
10535 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10536 fprintf (stream
, _("\
10537 -mshared disable branch optimization for shared code\n"));
10538 # if defined (TE_PE) || defined (TE_PEP)
10539 fprintf (stream
, _("\
10540 -mbig-obj generate big object files\n"));
10542 fprintf (stream
, _("\
10543 -momit-lock-prefix=[no|yes]\n\
10544 strip all lock prefixes\n"));
10545 fprintf (stream
, _("\
10546 -mfence-as-lock-add=[no|yes]\n\
10547 encode lfence, mfence and sfence as\n\
10548 lock addl $0x0, (%%{re}sp)\n"));
10549 fprintf (stream
, _("\
10550 -mrelax-relocations=[no|yes]\n\
10551 generate relax relocations\n"));
10552 fprintf (stream
, _("\
10553 -mamd64 accept only AMD64 ISA\n"));
10554 fprintf (stream
, _("\
10555 -mintel64 accept only Intel64 ISA\n"));
10558 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10559 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10560 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10562 /* Pick the target format to use. */
10565 i386_target_format (void)
10567 if (!strncmp (default_arch
, "x86_64", 6))
10569 update_code_flag (CODE_64BIT
, 1);
10570 if (default_arch
[6] == '\0')
10571 x86_elf_abi
= X86_64_ABI
;
10573 x86_elf_abi
= X86_64_X32_ABI
;
10575 else if (!strcmp (default_arch
, "i386"))
10576 update_code_flag (CODE_32BIT
, 1);
10577 else if (!strcmp (default_arch
, "iamcu"))
10579 update_code_flag (CODE_32BIT
, 1);
10580 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10582 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10583 cpu_arch_name
= "iamcu";
10584 cpu_sub_arch_name
= NULL
;
10585 cpu_arch_flags
= iamcu_flags
;
10586 cpu_arch_isa
= PROCESSOR_IAMCU
;
10587 cpu_arch_isa_flags
= iamcu_flags
;
10588 if (!cpu_arch_tune_set
)
10590 cpu_arch_tune
= cpu_arch_isa
;
10591 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10594 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
10595 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10599 as_fatal (_("unknown architecture"));
10601 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10602 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10603 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10604 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10606 switch (OUTPUT_FLAVOR
)
10608 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10609 case bfd_target_aout_flavour
:
10610 return AOUT_TARGET_FORMAT
;
10612 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10613 # if defined (TE_PE) || defined (TE_PEP)
10614 case bfd_target_coff_flavour
:
10615 if (flag_code
== CODE_64BIT
)
10616 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10619 # elif defined (TE_GO32)
10620 case bfd_target_coff_flavour
:
10621 return "coff-go32";
10623 case bfd_target_coff_flavour
:
10624 return "coff-i386";
10627 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10628 case bfd_target_elf_flavour
:
10630 const char *format
;
10632 switch (x86_elf_abi
)
10635 format
= ELF_TARGET_FORMAT
;
10638 use_rela_relocations
= 1;
10640 format
= ELF_TARGET_FORMAT64
;
10642 case X86_64_X32_ABI
:
10643 use_rela_relocations
= 1;
10645 disallow_64bit_reloc
= 1;
10646 format
= ELF_TARGET_FORMAT32
;
10649 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10651 if (x86_elf_abi
!= X86_64_ABI
)
10652 as_fatal (_("Intel L1OM is 64bit only"));
10653 return ELF_TARGET_L1OM_FORMAT
;
10655 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10657 if (x86_elf_abi
!= X86_64_ABI
)
10658 as_fatal (_("Intel K1OM is 64bit only"));
10659 return ELF_TARGET_K1OM_FORMAT
;
10661 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10663 if (x86_elf_abi
!= I386_ABI
)
10664 as_fatal (_("Intel MCU is 32bit only"));
10665 return ELF_TARGET_IAMCU_FORMAT
;
10671 #if defined (OBJ_MACH_O)
10672 case bfd_target_mach_o_flavour
:
10673 if (flag_code
== CODE_64BIT
)
10675 use_rela_relocations
= 1;
10677 return "mach-o-x86-64";
10680 return "mach-o-i386";
10688 #endif /* OBJ_MAYBE_ more than one */
10691 md_undefined_symbol (char *name
)
10693 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10694 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10695 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10696 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10700 if (symbol_find (name
))
10701 as_bad (_("GOT already in symbol table"));
10702 GOT_symbol
= symbol_new (name
, undefined_section
,
10703 (valueT
) 0, &zero_address_frag
);
10710 /* Round up a section size to the appropriate boundary. */
10713 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10715 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10716 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10718 /* For a.out, force the section size to be aligned. If we don't do
10719 this, BFD will align it for us, but it will not write out the
10720 final bytes of the section. This may be a bug in BFD, but it is
10721 easier to fix it here since that is how the other a.out targets
10725 align
= bfd_get_section_alignment (stdoutput
, segment
);
10726 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
10733 /* On the i386, PC-relative offsets are relative to the start of the
10734 next instruction. That is, the address of the offset, plus its
10735 size, since the offset is always the last part of the insn. */
10738 md_pcrel_from (fixS
*fixP
)
10740 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10746 s_bss (int ignore ATTRIBUTE_UNUSED
)
10750 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10752 obj_elf_section_change_hook ();
10754 temp
= get_absolute_expression ();
10755 subseg_set (bss_section
, (subsegT
) temp
);
10756 demand_empty_rest_of_line ();
10762 i386_validate_fix (fixS
*fixp
)
10764 if (fixp
->fx_subsy
)
10766 if (fixp
->fx_subsy
== GOT_symbol
)
10768 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10772 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10773 if (fixp
->fx_tcbit2
)
10774 fixp
->fx_r_type
= (fixp
->fx_tcbit
10775 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10776 : BFD_RELOC_X86_64_GOTPCRELX
);
10779 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10784 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10786 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10788 fixp
->fx_subsy
= 0;
10791 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10792 else if (!object_64bit
)
10794 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
10795 && fixp
->fx_tcbit2
)
10796 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
10802 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10805 bfd_reloc_code_real_type code
;
10807 switch (fixp
->fx_r_type
)
10809 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10810 case BFD_RELOC_SIZE32
:
10811 case BFD_RELOC_SIZE64
:
10812 if (S_IS_DEFINED (fixp
->fx_addsy
)
10813 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10815 /* Resolve size relocation against local symbol to size of
10816 the symbol plus addend. */
10817 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10818 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10819 && !fits_in_unsigned_long (value
))
10820 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10821 _("symbol size computation overflow"));
10822 fixp
->fx_addsy
= NULL
;
10823 fixp
->fx_subsy
= NULL
;
10824 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10828 /* Fall through. */
10830 case BFD_RELOC_X86_64_PLT32
:
10831 case BFD_RELOC_X86_64_GOT32
:
10832 case BFD_RELOC_X86_64_GOTPCREL
:
10833 case BFD_RELOC_X86_64_GOTPCRELX
:
10834 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10835 case BFD_RELOC_386_PLT32
:
10836 case BFD_RELOC_386_GOT32
:
10837 case BFD_RELOC_386_GOT32X
:
10838 case BFD_RELOC_386_GOTOFF
:
10839 case BFD_RELOC_386_GOTPC
:
10840 case BFD_RELOC_386_TLS_GD
:
10841 case BFD_RELOC_386_TLS_LDM
:
10842 case BFD_RELOC_386_TLS_LDO_32
:
10843 case BFD_RELOC_386_TLS_IE_32
:
10844 case BFD_RELOC_386_TLS_IE
:
10845 case BFD_RELOC_386_TLS_GOTIE
:
10846 case BFD_RELOC_386_TLS_LE_32
:
10847 case BFD_RELOC_386_TLS_LE
:
10848 case BFD_RELOC_386_TLS_GOTDESC
:
10849 case BFD_RELOC_386_TLS_DESC_CALL
:
10850 case BFD_RELOC_X86_64_TLSGD
:
10851 case BFD_RELOC_X86_64_TLSLD
:
10852 case BFD_RELOC_X86_64_DTPOFF32
:
10853 case BFD_RELOC_X86_64_DTPOFF64
:
10854 case BFD_RELOC_X86_64_GOTTPOFF
:
10855 case BFD_RELOC_X86_64_TPOFF32
:
10856 case BFD_RELOC_X86_64_TPOFF64
:
10857 case BFD_RELOC_X86_64_GOTOFF64
:
10858 case BFD_RELOC_X86_64_GOTPC32
:
10859 case BFD_RELOC_X86_64_GOT64
:
10860 case BFD_RELOC_X86_64_GOTPCREL64
:
10861 case BFD_RELOC_X86_64_GOTPC64
:
10862 case BFD_RELOC_X86_64_GOTPLT64
:
10863 case BFD_RELOC_X86_64_PLTOFF64
:
10864 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10865 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10866 case BFD_RELOC_RVA
:
10867 case BFD_RELOC_VTABLE_ENTRY
:
10868 case BFD_RELOC_VTABLE_INHERIT
:
10870 case BFD_RELOC_32_SECREL
:
10872 code
= fixp
->fx_r_type
;
10874 case BFD_RELOC_X86_64_32S
:
10875 if (!fixp
->fx_pcrel
)
10877 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10878 code
= fixp
->fx_r_type
;
10881 /* Fall through. */
10883 if (fixp
->fx_pcrel
)
10885 switch (fixp
->fx_size
)
10888 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10889 _("can not do %d byte pc-relative relocation"),
10891 code
= BFD_RELOC_32_PCREL
;
10893 case 1: code
= BFD_RELOC_8_PCREL
; break;
10894 case 2: code
= BFD_RELOC_16_PCREL
; break;
10895 case 4: code
= BFD_RELOC_32_PCREL
; break;
10897 case 8: code
= BFD_RELOC_64_PCREL
; break;
10903 switch (fixp
->fx_size
)
10906 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10907 _("can not do %d byte relocation"),
10909 code
= BFD_RELOC_32
;
10911 case 1: code
= BFD_RELOC_8
; break;
10912 case 2: code
= BFD_RELOC_16
; break;
10913 case 4: code
= BFD_RELOC_32
; break;
10915 case 8: code
= BFD_RELOC_64
; break;
10922 if ((code
== BFD_RELOC_32
10923 || code
== BFD_RELOC_32_PCREL
10924 || code
== BFD_RELOC_X86_64_32S
)
10926 && fixp
->fx_addsy
== GOT_symbol
)
10929 code
= BFD_RELOC_386_GOTPC
;
10931 code
= BFD_RELOC_X86_64_GOTPC32
;
10933 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10935 && fixp
->fx_addsy
== GOT_symbol
)
10937 code
= BFD_RELOC_X86_64_GOTPC64
;
10940 rel
= XNEW (arelent
);
10941 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
10942 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10944 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10946 if (!use_rela_relocations
)
10948 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10949 vtable entry to be used in the relocation's section offset. */
10950 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10951 rel
->address
= fixp
->fx_offset
;
10952 #if defined (OBJ_COFF) && defined (TE_PE)
10953 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10954 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10959 /* Use the rela in 64bit mode. */
10962 if (disallow_64bit_reloc
)
10965 case BFD_RELOC_X86_64_DTPOFF64
:
10966 case BFD_RELOC_X86_64_TPOFF64
:
10967 case BFD_RELOC_64_PCREL
:
10968 case BFD_RELOC_X86_64_GOTOFF64
:
10969 case BFD_RELOC_X86_64_GOT64
:
10970 case BFD_RELOC_X86_64_GOTPCREL64
:
10971 case BFD_RELOC_X86_64_GOTPC64
:
10972 case BFD_RELOC_X86_64_GOTPLT64
:
10973 case BFD_RELOC_X86_64_PLTOFF64
:
10974 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10975 _("cannot represent relocation type %s in x32 mode"),
10976 bfd_get_reloc_code_name (code
));
10982 if (!fixp
->fx_pcrel
)
10983 rel
->addend
= fixp
->fx_offset
;
10987 case BFD_RELOC_X86_64_PLT32
:
10988 case BFD_RELOC_X86_64_GOT32
:
10989 case BFD_RELOC_X86_64_GOTPCREL
:
10990 case BFD_RELOC_X86_64_GOTPCRELX
:
10991 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10992 case BFD_RELOC_X86_64_TLSGD
:
10993 case BFD_RELOC_X86_64_TLSLD
:
10994 case BFD_RELOC_X86_64_GOTTPOFF
:
10995 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10996 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10997 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
11000 rel
->addend
= (section
->vma
11002 + fixp
->fx_addnumber
11003 + md_pcrel_from (fixp
));
11008 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11009 if (rel
->howto
== NULL
)
11011 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11012 _("cannot represent relocation type %s"),
11013 bfd_get_reloc_code_name (code
));
11014 /* Set howto to a garbage value so that we can keep going. */
11015 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
11016 gas_assert (rel
->howto
!= NULL
);
11022 #include "tc-i386-intel.c"
11025 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
11027 int saved_naked_reg
;
11028 char saved_register_dot
;
11030 saved_naked_reg
= allow_naked_reg
;
11031 allow_naked_reg
= 1;
11032 saved_register_dot
= register_chars
['.'];
11033 register_chars
['.'] = '.';
11034 allow_pseudo_reg
= 1;
11035 expression_and_evaluate (exp
);
11036 allow_pseudo_reg
= 0;
11037 register_chars
['.'] = saved_register_dot
;
11038 allow_naked_reg
= saved_naked_reg
;
11040 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
11042 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
11044 exp
->X_op
= O_constant
;
11045 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
11046 .dw2_regnum
[flag_code
>> 1];
11049 exp
->X_op
= O_illegal
;
11054 tc_x86_frame_initial_instructions (void)
11056 static unsigned int sp_regno
[2];
11058 if (!sp_regno
[flag_code
>> 1])
11060 char *saved_input
= input_line_pointer
;
11061 char sp
[][4] = {"esp", "rsp"};
11064 input_line_pointer
= sp
[flag_code
>> 1];
11065 tc_x86_parse_to_dw2regnum (&exp
);
11066 gas_assert (exp
.X_op
== O_constant
);
11067 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
11068 input_line_pointer
= saved_input
;
11071 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
11072 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
11076 x86_dwarf2_addr_size (void)
11078 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11079 if (x86_elf_abi
== X86_64_X32_ABI
)
11082 return bfd_arch_bits_per_address (stdoutput
) / 8;
11086 i386_elf_section_type (const char *str
, size_t len
)
11088 if (flag_code
== CODE_64BIT
11089 && len
== sizeof ("unwind") - 1
11090 && strncmp (str
, "unwind", 6) == 0)
11091 return SHT_X86_64_UNWIND
;
11098 i386_solaris_fix_up_eh_frame (segT sec
)
11100 if (flag_code
== CODE_64BIT
)
11101 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
11107 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
11111 exp
.X_op
= O_secrel
;
11112 exp
.X_add_symbol
= symbol
;
11113 exp
.X_add_number
= 0;
11114 emit_expr (&exp
, size
);
11118 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11119 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11122 x86_64_section_letter (int letter
, const char **ptr_msg
)
11124 if (flag_code
== CODE_64BIT
)
11127 return SHF_X86_64_LARGE
;
11129 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11132 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
11137 x86_64_section_word (char *str
, size_t len
)
11139 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
11140 return SHF_X86_64_LARGE
;
11146 handle_large_common (int small ATTRIBUTE_UNUSED
)
11148 if (flag_code
!= CODE_64BIT
)
11150 s_comm_internal (0, elf_common_parse
);
11151 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11155 static segT lbss_section
;
11156 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
11157 asection
*saved_bss_section
= bss_section
;
11159 if (lbss_section
== NULL
)
11161 flagword applicable
;
11162 segT seg
= now_seg
;
11163 subsegT subseg
= now_subseg
;
11165 /* The .lbss section is for local .largecomm symbols. */
11166 lbss_section
= subseg_new (".lbss", 0);
11167 applicable
= bfd_applicable_section_flags (stdoutput
);
11168 bfd_set_section_flags (stdoutput
, lbss_section
,
11169 applicable
& SEC_ALLOC
);
11170 seg_info (lbss_section
)->bss
= 1;
11172 subseg_set (seg
, subseg
);
11175 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
11176 bss_section
= lbss_section
;
11178 s_comm_internal (0, elf_common_parse
);
11180 elf_com_section_ptr
= saved_com_section_ptr
;
11181 bss_section
= saved_bss_section
;
11184 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */