1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
139 /* Used to turn off indicated flags. */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 i386_cpu_flags flags
; /* cpu feature flags */
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
157 static void pe_directive_secrel (int);
159 static void signed_cons (int);
160 static char *output_invalid (int c
);
161 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
163 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS
*);
168 static int i386_intel_parse_name (const char *, expressionS
*);
169 static const reg_entry
*parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template
*match_template (char);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry
*build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS
*, offsetT
);
188 static void output_disp (fragS
*, offsetT
);
190 static void s_bss (int);
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
196 static const char *default_arch
= DEFAULT_ARCH
;
198 /* This struct describes rounding control and SAE in the instruction. */
212 static struct RC_Operation rc_op
;
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
219 const reg_entry
*mask
;
220 unsigned int zeroing
;
221 /* The operand where this operation is associated. */
225 static struct Mask_Operation mask_op
;
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
229 struct Broadcast_Operation
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
234 /* Index of broadcasted operand. */
238 static struct Broadcast_Operation broadcast_op
;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes
[4];
246 /* Destination or source register specifier. */
247 const reg_entry
*register_specifier
;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry
*regs
;
262 operand_size_mismatch
,
263 operand_type_mismatch
,
264 register_type_mismatch
,
265 number_of_operands_mismatch
,
266 invalid_instruction_suffix
,
269 unsupported_with_intel_mnemonic
,
272 invalid_vsib_address
,
273 invalid_vector_register_set
,
274 unsupported_vector_index_register
,
275 unsupported_broadcast
,
276 broadcast_not_on_src_operand
,
279 mask_not_on_destination
,
282 rc_sae_operand_not_last_imm
,
283 invalid_register_operand
,
289 /* TM holds the template for the insn were currently assembling. */
292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
296 /* OPERANDS gives the number of given operands. */
297 unsigned int operands
;
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
302 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
304 /* TYPES [i] is the type (see above #defines) which tells us how to
305 use OP[i] for the corresponding operand. */
306 i386_operand_type types
[MAX_OPERANDS
];
308 /* Displacement expression, immediate expression, or register for each
310 union i386_op op
[MAX_OPERANDS
];
312 /* Flags for operands. */
313 unsigned int flags
[MAX_OPERANDS
];
314 #define Operand_PCrel 1
316 /* Relocation type for operand */
317 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry
*base_reg
;
322 const reg_entry
*index_reg
;
323 unsigned int log2_scale_factor
;
325 /* SEG gives the seg_entries of this insn. They are zero unless
326 explicit segment overrides are given. */
327 const seg_entry
*seg
[2];
329 /* Copied first memory operand string, for re-checking. */
332 /* PREFIX holds all the given prefix opcodes (usually null).
333 PREFIXES is the number of prefix opcodes. */
334 unsigned int prefixes
;
335 unsigned char prefix
[MAX_PREFIXES
];
337 /* RM and SIB are the modrm byte and the sib byte where the
338 addressing modes of this insn are encoded. */
345 /* Masking attributes. */
346 struct Mask_Operation
*mask
;
348 /* Rounding control and SAE attributes. */
349 struct RC_Operation
*rounding
;
351 /* Broadcasting attributes. */
352 struct Broadcast_Operation
*broadcast
;
354 /* Compressed disp8*N attribute. */
355 unsigned int memshift
;
357 /* Swap operand in encoding. */
358 unsigned int swap_operand
;
360 /* Prefer 8bit or 32bit displacement in encoding. */
363 disp_encoding_default
= 0,
369 const char *rep_prefix
;
372 const char *hle_prefix
;
374 /* Have BND prefix. */
375 const char *bnd_prefix
;
377 /* Need VREX to support upper 16 registers. */
381 enum i386_error error
;
384 typedef struct _i386_insn i386_insn
;
386 /* Link RC type with corresponding string, that'll be looked for in
395 static const struct RC_name RC_NamesTable
[] =
397 { rne
, STRING_COMMA_LEN ("rn-sae") },
398 { rd
, STRING_COMMA_LEN ("rd-sae") },
399 { ru
, STRING_COMMA_LEN ("ru-sae") },
400 { rz
, STRING_COMMA_LEN ("rz-sae") },
401 { saeonly
, STRING_COMMA_LEN ("sae") },
404 /* List of chars besides those in app.c:symbol_chars that can start an
405 operand. Used to prevent the scrubber eating vital white-space. */
406 const char extra_symbol_chars
[] = "*%-([{"
415 #if (defined (TE_I386AIX) \
416 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
417 && !defined (TE_GNU) \
418 && !defined (TE_LINUX) \
419 && !defined (TE_NACL) \
420 && !defined (TE_NETWARE) \
421 && !defined (TE_FreeBSD) \
422 && !defined (TE_DragonFly) \
423 && !defined (TE_NetBSD)))
424 /* This array holds the chars that always start a comment. If the
425 pre-processor is disabled, these aren't very useful. The option
426 --divide will remove '/' from this list. */
427 const char *i386_comment_chars
= "#/";
428 #define SVR4_COMMENT_CHARS 1
429 #define PREFIX_SEPARATOR '\\'
432 const char *i386_comment_chars
= "#";
433 #define PREFIX_SEPARATOR '/'
436 /* This array holds the chars that only start a comment at the beginning of
437 a line. If the line seems to have the form '# 123 filename'
438 .line and .file directives will appear in the pre-processed output.
439 Note that input_file.c hand checks for '#' at the beginning of the
440 first line of the input file. This is because the compiler outputs
441 #NO_APP at the beginning of its output.
442 Also note that comments started like this one will always work if
443 '/' isn't otherwise defined. */
444 const char line_comment_chars
[] = "#/";
446 const char line_separator_chars
[] = ";";
448 /* Chars that can be used to separate mant from exp in floating point
450 const char EXP_CHARS
[] = "eE";
452 /* Chars that mean this number is a floating point constant
455 const char FLT_CHARS
[] = "fFdDxX";
457 /* Tables for lexical analysis. */
458 static char mnemonic_chars
[256];
459 static char register_chars
[256];
460 static char operand_chars
[256];
461 static char identifier_chars
[256];
462 static char digit_chars
[256];
464 /* Lexical macros. */
465 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
466 #define is_operand_char(x) (operand_chars[(unsigned char) x])
467 #define is_register_char(x) (register_chars[(unsigned char) x])
468 #define is_space_char(x) ((x) == ' ')
469 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
470 #define is_digit_char(x) (digit_chars[(unsigned char) x])
472 /* All non-digit non-letter characters that may occur in an operand. */
473 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
475 /* md_assemble() always leaves the strings it's passed unaltered. To
476 effect this we maintain a stack of saved characters that we've smashed
477 with '\0's (indicating end of strings for various sub-fields of the
478 assembler instruction). */
479 static char save_stack
[32];
480 static char *save_stack_p
;
481 #define END_STRING_AND_SAVE(s) \
482 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
483 #define RESTORE_END_STRING(s) \
484 do { *(s) = *--save_stack_p; } while (0)
486 /* The instruction we're assembling. */
489 /* Possible templates for current insn. */
490 static const templates
*current_templates
;
492 /* Per instruction expressionS buffers: max displacements & immediates. */
493 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
494 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
496 /* Current operand we are working on. */
497 static int this_operand
= -1;
499 /* We support four different modes. FLAG_CODE variable is used to distinguish
507 static enum flag_code flag_code
;
508 static unsigned int object_64bit
;
509 static unsigned int disallow_64bit_reloc
;
510 static int use_rela_relocations
= 0;
512 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
513 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
514 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
516 /* The ELF ABI to use. */
524 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
527 #if defined (TE_PE) || defined (TE_PEP)
528 /* Use big object file format. */
529 static int use_big_obj
= 0;
532 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
533 /* 1 if generating code for a shared library. */
534 static int shared
= 0;
537 /* 1 for intel syntax,
539 static int intel_syntax
= 0;
541 /* 1 for Intel64 ISA,
545 /* 1 for intel mnemonic,
546 0 if att mnemonic. */
547 static int intel_mnemonic
= !SYSV386_COMPAT
;
549 /* 1 if support old (<= 2.8.1) versions of gcc. */
550 static int old_gcc
= OLDGCC_COMPAT
;
552 /* 1 if pseudo registers are permitted. */
553 static int allow_pseudo_reg
= 0;
555 /* 1 if register prefix % not required. */
556 static int allow_naked_reg
= 0;
558 /* 1 if the assembler should add BND prefix for all control-tranferring
559 instructions supporting it, even if this prefix wasn't specified
561 static int add_bnd_prefix
= 0;
563 /* 1 if pseudo index register, eiz/riz, is allowed . */
564 static int allow_index_reg
= 0;
566 /* 1 if the assembler should ignore LOCK prefix, even if it was
567 specified explicitly. */
568 static int omit_lock_prefix
= 0;
570 /* 1 if the assembler should encode lfence, mfence, and sfence as
571 "lock addl $0, (%{re}sp)". */
572 static int avoid_fence
= 0;
574 /* 1 if the assembler should generate relax relocations. */
576 static int generate_relax_relocations
577 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
579 static enum check_kind
585 sse_check
, operand_check
= check_warning
;
587 /* Register prefix used for error message. */
588 static const char *register_prefix
= "%";
590 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
591 leave, push, and pop instructions so that gcc has the same stack
592 frame as in 32 bit mode. */
593 static char stackop_size
= '\0';
595 /* Non-zero to optimize code alignment. */
596 int optimize_align_code
= 1;
598 /* Non-zero to quieten some warnings. */
599 static int quiet_warnings
= 0;
602 static const char *cpu_arch_name
= NULL
;
603 static char *cpu_sub_arch_name
= NULL
;
605 /* CPU feature flags. */
606 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
608 /* If we have selected a cpu we are generating instructions for. */
609 static int cpu_arch_tune_set
= 0;
611 /* Cpu we are generating instructions for. */
612 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
614 /* CPU feature flags of cpu we are generating instructions for. */
615 static i386_cpu_flags cpu_arch_tune_flags
;
617 /* CPU instruction set architecture used. */
618 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
620 /* CPU feature flags of instruction set architecture used. */
621 i386_cpu_flags cpu_arch_isa_flags
;
623 /* If set, conditional jumps are not automatically promoted to handle
624 larger than a byte offset. */
625 static unsigned int no_cond_jump_promotion
= 0;
627 /* Encode SSE instructions with VEX prefix. */
628 static unsigned int sse2avx
;
630 /* Encode scalar AVX instructions with specific vector length. */
637 /* Encode scalar EVEX LIG instructions with specific vector length. */
645 /* Encode EVEX WIG instructions with specific evex.w. */
652 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
653 static enum rc_type evexrcig
= rne
;
655 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
656 static symbolS
*GOT_symbol
;
658 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
659 unsigned int x86_dwarf2_return_column
;
661 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
662 int x86_cie_data_alignment
;
664 /* Interface to relax_segment.
665 There are 3 major relax states for 386 jump insns because the
666 different types of jumps add different sizes to frags when we're
667 figuring out what sort of jump to choose to reach a given label. */
670 #define UNCOND_JUMP 0
672 #define COND_JUMP86 2
677 #define SMALL16 (SMALL | CODE16)
679 #define BIG16 (BIG | CODE16)
683 #define INLINE __inline__
689 #define ENCODE_RELAX_STATE(type, size) \
690 ((relax_substateT) (((type) << 2) | (size)))
691 #define TYPE_FROM_RELAX_STATE(s) \
693 #define DISP_SIZE_FROM_RELAX_STATE(s) \
694 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
696 /* This table is used by relax_frag to promote short jumps to long
697 ones where necessary. SMALL (short) jumps may be promoted to BIG
698 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
699 don't allow a short jump in a 32 bit code segment to be promoted to
700 a 16 bit offset jump because it's slower (requires data size
701 prefix), and doesn't work, unless the destination is in the bottom
702 64k of the code segment (The top 16 bits of eip are zeroed). */
704 const relax_typeS md_relax_table
[] =
707 1) most positive reach of this state,
708 2) most negative reach of this state,
709 3) how many bytes this mode will have in the variable part of the frag
710 4) which index into the table to try if we can't fit into this one. */
712 /* UNCOND_JUMP states. */
713 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
714 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
715 /* dword jmp adds 4 bytes to frag:
716 0 extra opcode bytes, 4 displacement bytes. */
718 /* word jmp adds 2 byte2 to frag:
719 0 extra opcode bytes, 2 displacement bytes. */
722 /* COND_JUMP states. */
723 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
724 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
725 /* dword conditionals adds 5 bytes to frag:
726 1 extra opcode byte, 4 displacement bytes. */
728 /* word conditionals add 3 bytes to frag:
729 1 extra opcode byte, 2 displacement bytes. */
732 /* COND_JUMP86 states. */
733 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
734 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
735 /* dword conditionals adds 5 bytes to frag:
736 1 extra opcode byte, 4 displacement bytes. */
738 /* word conditionals add 4 bytes to frag:
739 1 displacement byte and a 3 byte long branch insn. */
743 static const arch_entry cpu_arch
[] =
745 /* Do not replace the first two entries - i386_target_format()
746 relies on them being there in this order. */
747 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
748 CPU_GENERIC32_FLAGS
, 0 },
749 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
750 CPU_GENERIC64_FLAGS
, 0 },
751 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
753 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
755 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
757 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
759 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
761 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
763 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
765 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
767 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
768 CPU_PENTIUMPRO_FLAGS
, 0 },
769 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
771 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
773 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
775 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
777 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
778 CPU_NOCONA_FLAGS
, 0 },
779 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
781 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
783 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
784 CPU_CORE2_FLAGS
, 1 },
785 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
786 CPU_CORE2_FLAGS
, 0 },
787 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
788 CPU_COREI7_FLAGS
, 0 },
789 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
791 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
793 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
794 CPU_IAMCU_FLAGS
, 0 },
795 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
797 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
799 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
800 CPU_ATHLON_FLAGS
, 0 },
801 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
803 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
805 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
807 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
808 CPU_AMDFAM10_FLAGS
, 0 },
809 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
810 CPU_BDVER1_FLAGS
, 0 },
811 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
812 CPU_BDVER2_FLAGS
, 0 },
813 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
814 CPU_BDVER3_FLAGS
, 0 },
815 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
816 CPU_BDVER4_FLAGS
, 0 },
817 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
818 CPU_ZNVER1_FLAGS
, 0 },
819 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
820 CPU_BTVER1_FLAGS
, 0 },
821 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
822 CPU_BTVER2_FLAGS
, 0 },
823 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
825 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
827 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
829 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
831 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
833 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
835 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
837 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
839 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
840 CPU_SSSE3_FLAGS
, 0 },
841 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
842 CPU_SSE4_1_FLAGS
, 0 },
843 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
844 CPU_SSE4_2_FLAGS
, 0 },
845 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
846 CPU_SSE4_2_FLAGS
, 0 },
847 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
849 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
851 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
852 CPU_AVX512F_FLAGS
, 0 },
853 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
854 CPU_AVX512CD_FLAGS
, 0 },
855 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
856 CPU_AVX512ER_FLAGS
, 0 },
857 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
858 CPU_AVX512PF_FLAGS
, 0 },
859 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
860 CPU_AVX512DQ_FLAGS
, 0 },
861 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
862 CPU_AVX512BW_FLAGS
, 0 },
863 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
864 CPU_AVX512VL_FLAGS
, 0 },
865 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
867 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
868 CPU_VMFUNC_FLAGS
, 0 },
869 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
871 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
872 CPU_XSAVE_FLAGS
, 0 },
873 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
874 CPU_XSAVEOPT_FLAGS
, 0 },
875 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
876 CPU_XSAVEC_FLAGS
, 0 },
877 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
878 CPU_XSAVES_FLAGS
, 0 },
879 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
881 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
882 CPU_PCLMUL_FLAGS
, 0 },
883 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
884 CPU_PCLMUL_FLAGS
, 1 },
885 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
886 CPU_FSGSBASE_FLAGS
, 0 },
887 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
888 CPU_RDRND_FLAGS
, 0 },
889 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
891 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
893 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
895 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
897 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
899 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
901 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
902 CPU_MOVBE_FLAGS
, 0 },
903 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
905 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
907 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
908 CPU_LZCNT_FLAGS
, 0 },
909 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
911 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
913 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
914 CPU_INVPCID_FLAGS
, 0 },
915 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
916 CPU_CLFLUSH_FLAGS
, 0 },
917 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
919 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
920 CPU_SYSCALL_FLAGS
, 0 },
921 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
922 CPU_RDTSCP_FLAGS
, 0 },
923 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
924 CPU_3DNOW_FLAGS
, 0 },
925 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
926 CPU_3DNOWA_FLAGS
, 0 },
927 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
928 CPU_PADLOCK_FLAGS
, 0 },
929 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
931 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
933 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
934 CPU_SSE4A_FLAGS
, 0 },
935 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
937 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
939 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
941 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
943 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
944 CPU_RDSEED_FLAGS
, 0 },
945 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
946 CPU_PRFCHW_FLAGS
, 0 },
947 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
949 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
951 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
953 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
954 CPU_CLFLUSHOPT_FLAGS
, 0 },
955 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
956 CPU_PREFETCHWT1_FLAGS
, 0 },
957 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
959 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
961 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
962 CPU_PCOMMIT_FLAGS
, 0 },
963 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
964 CPU_AVX512IFMA_FLAGS
, 0 },
965 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
966 CPU_AVX512VBMI_FLAGS
, 0 },
967 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
968 CPU_CLZERO_FLAGS
, 0 },
969 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
970 CPU_MWAITX_FLAGS
, 0 },
971 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
972 CPU_OSPKE_FLAGS
, 0 },
973 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
974 CPU_RDPID_FLAGS
, 0 },
975 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
976 CPU_PTWRITE_FLAGS
, 0 },
979 static const noarch_entry cpu_noarch
[] =
981 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
982 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
983 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
984 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
985 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
986 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
987 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
988 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
989 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
990 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
991 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
992 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
993 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
994 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
995 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
996 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
997 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
998 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
999 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1000 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1001 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1002 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1003 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1007 /* Like s_lcomm_internal in gas/read.c but the alignment string
1008 is allowed to be optional. */
1011 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1018 && *input_line_pointer
== ',')
1020 align
= parse_align (needs_align
- 1);
1022 if (align
== (addressT
) -1)
1037 bss_alloc (symbolP
, size
, align
);
1042 pe_lcomm (int needs_align
)
1044 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1048 const pseudo_typeS md_pseudo_table
[] =
1050 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1051 {"align", s_align_bytes
, 0},
1053 {"align", s_align_ptwo
, 0},
1055 {"arch", set_cpu_arch
, 0},
1059 {"lcomm", pe_lcomm
, 1},
1061 {"ffloat", float_cons
, 'f'},
1062 {"dfloat", float_cons
, 'd'},
1063 {"tfloat", float_cons
, 'x'},
1065 {"slong", signed_cons
, 4},
1066 {"noopt", s_ignore
, 0},
1067 {"optim", s_ignore
, 0},
1068 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1069 {"code16", set_code_flag
, CODE_16BIT
},
1070 {"code32", set_code_flag
, CODE_32BIT
},
1071 {"code64", set_code_flag
, CODE_64BIT
},
1072 {"intel_syntax", set_intel_syntax
, 1},
1073 {"att_syntax", set_intel_syntax
, 0},
1074 {"intel_mnemonic", set_intel_mnemonic
, 1},
1075 {"att_mnemonic", set_intel_mnemonic
, 0},
1076 {"allow_index_reg", set_allow_index_reg
, 1},
1077 {"disallow_index_reg", set_allow_index_reg
, 0},
1078 {"sse_check", set_check
, 0},
1079 {"operand_check", set_check
, 1},
1080 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1081 {"largecomm", handle_large_common
, 0},
1083 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1084 {"loc", dwarf2_directive_loc
, 0},
1085 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1088 {"secrel32", pe_directive_secrel
, 0},
1093 /* For interface with expression (). */
1094 extern char *input_line_pointer
;
1096 /* Hash table for instruction mnemonic lookup. */
1097 static struct hash_control
*op_hash
;
1099 /* Hash table for register lookup. */
1100 static struct hash_control
*reg_hash
;
1103 i386_align_code (fragS
*fragP
, int count
)
1105 /* Various efficient no-op patterns for aligning code labels.
1106 Note: Don't try to assemble the instructions in the comments.
1107 0L and 0w are not legal. */
1108 static const unsigned char f32_1
[] =
1110 static const unsigned char f32_2
[] =
1111 {0x66,0x90}; /* xchg %ax,%ax */
1112 static const unsigned char f32_3
[] =
1113 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1114 static const unsigned char f32_4
[] =
1115 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1116 static const unsigned char f32_5
[] =
1118 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1119 static const unsigned char f32_6
[] =
1120 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1121 static const unsigned char f32_7
[] =
1122 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1123 static const unsigned char f32_8
[] =
1125 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1126 static const unsigned char f32_9
[] =
1127 {0x89,0xf6, /* movl %esi,%esi */
1128 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1129 static const unsigned char f32_10
[] =
1130 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1131 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1132 static const unsigned char f32_11
[] =
1133 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1134 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1135 static const unsigned char f32_12
[] =
1136 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1137 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1138 static const unsigned char f32_13
[] =
1139 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1140 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1141 static const unsigned char f32_14
[] =
1142 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1143 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1144 static const unsigned char f16_3
[] =
1145 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1146 static const unsigned char f16_4
[] =
1147 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1148 static const unsigned char f16_5
[] =
1150 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1151 static const unsigned char f16_6
[] =
1152 {0x89,0xf6, /* mov %si,%si */
1153 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1154 static const unsigned char f16_7
[] =
1155 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1156 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1157 static const unsigned char f16_8
[] =
1158 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1159 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1160 static const unsigned char jump_31
[] =
1161 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1162 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1163 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1164 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1165 static const unsigned char *const f32_patt
[] = {
1166 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1167 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1169 static const unsigned char *const f16_patt
[] = {
1170 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1172 /* nopl (%[re]ax) */
1173 static const unsigned char alt_3
[] =
1175 /* nopl 0(%[re]ax) */
1176 static const unsigned char alt_4
[] =
1177 {0x0f,0x1f,0x40,0x00};
1178 /* nopl 0(%[re]ax,%[re]ax,1) */
1179 static const unsigned char alt_5
[] =
1180 {0x0f,0x1f,0x44,0x00,0x00};
1181 /* nopw 0(%[re]ax,%[re]ax,1) */
1182 static const unsigned char alt_6
[] =
1183 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1184 /* nopl 0L(%[re]ax) */
1185 static const unsigned char alt_7
[] =
1186 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1187 /* nopl 0L(%[re]ax,%[re]ax,1) */
1188 static const unsigned char alt_8
[] =
1189 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1190 /* nopw 0L(%[re]ax,%[re]ax,1) */
1191 static const unsigned char alt_9
[] =
1192 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1193 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1194 static const unsigned char alt_10
[] =
1195 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1196 static const unsigned char *const alt_patt
[] = {
1197 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1201 /* Only align for at least a positive non-zero boundary. */
1202 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1205 /* We need to decide which NOP sequence to use for 32bit and
1206 64bit. When -mtune= is used:
1208 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1209 PROCESSOR_GENERIC32, f32_patt will be used.
1210 2. For the rest, alt_patt will be used.
1212 When -mtune= isn't used, alt_patt will be used if
1213 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1216 When -march= or .arch is used, we can't use anything beyond
1217 cpu_arch_isa_flags. */
1219 if (flag_code
== CODE_16BIT
)
1223 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1225 /* Adjust jump offset. */
1226 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1229 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1230 f16_patt
[count
- 1], count
);
1234 const unsigned char *const *patt
= NULL
;
1236 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1238 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1239 switch (cpu_arch_tune
)
1241 case PROCESSOR_UNKNOWN
:
1242 /* We use cpu_arch_isa_flags to check if we SHOULD
1243 optimize with nops. */
1244 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1249 case PROCESSOR_PENTIUM4
:
1250 case PROCESSOR_NOCONA
:
1251 case PROCESSOR_CORE
:
1252 case PROCESSOR_CORE2
:
1253 case PROCESSOR_COREI7
:
1254 case PROCESSOR_L1OM
:
1255 case PROCESSOR_K1OM
:
1256 case PROCESSOR_GENERIC64
:
1258 case PROCESSOR_ATHLON
:
1260 case PROCESSOR_AMDFAM10
:
1262 case PROCESSOR_ZNVER
:
1266 case PROCESSOR_I386
:
1267 case PROCESSOR_I486
:
1268 case PROCESSOR_PENTIUM
:
1269 case PROCESSOR_PENTIUMPRO
:
1270 case PROCESSOR_IAMCU
:
1271 case PROCESSOR_GENERIC32
:
1278 switch (fragP
->tc_frag_data
.tune
)
1280 case PROCESSOR_UNKNOWN
:
1281 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1282 PROCESSOR_UNKNOWN. */
1286 case PROCESSOR_I386
:
1287 case PROCESSOR_I486
:
1288 case PROCESSOR_PENTIUM
:
1289 case PROCESSOR_IAMCU
:
1291 case PROCESSOR_ATHLON
:
1293 case PROCESSOR_AMDFAM10
:
1295 case PROCESSOR_ZNVER
:
1297 case PROCESSOR_GENERIC32
:
1298 /* We use cpu_arch_isa_flags to check if we CAN optimize
1300 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1305 case PROCESSOR_PENTIUMPRO
:
1306 case PROCESSOR_PENTIUM4
:
1307 case PROCESSOR_NOCONA
:
1308 case PROCESSOR_CORE
:
1309 case PROCESSOR_CORE2
:
1310 case PROCESSOR_COREI7
:
1311 case PROCESSOR_L1OM
:
1312 case PROCESSOR_K1OM
:
1313 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1318 case PROCESSOR_GENERIC64
:
1324 if (patt
== f32_patt
)
1326 /* If the padding is less than 15 bytes, we use the normal
1327 ones. Otherwise, we use a jump instruction and adjust
1331 /* For 64bit, the limit is 3 bytes. */
1332 if (flag_code
== CODE_64BIT
1333 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1338 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1339 patt
[count
- 1], count
);
1342 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1344 /* Adjust jump offset. */
1345 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1350 /* Maximum length of an instruction is 10 byte. If the
1351 padding is greater than 10 bytes and we don't use jump,
1352 we have to break it into smaller pieces. */
1353 int padding
= count
;
1354 while (padding
> 10)
1357 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1362 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1363 patt
[padding
- 1], padding
);
1366 fragP
->fr_var
= count
;
1370 operand_type_all_zero (const union i386_operand_type
*x
)
1372 switch (ARRAY_SIZE(x
->array
))
1381 return !x
->array
[0];
1388 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1390 switch (ARRAY_SIZE(x
->array
))
1405 operand_type_equal (const union i386_operand_type
*x
,
1406 const union i386_operand_type
*y
)
1408 switch (ARRAY_SIZE(x
->array
))
1411 if (x
->array
[2] != y
->array
[2])
1414 if (x
->array
[1] != y
->array
[1])
1417 return x
->array
[0] == y
->array
[0];
1425 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1427 switch (ARRAY_SIZE(x
->array
))
1436 return !x
->array
[0];
1443 cpu_flags_equal (const union i386_cpu_flags
*x
,
1444 const union i386_cpu_flags
*y
)
1446 switch (ARRAY_SIZE(x
->array
))
1449 if (x
->array
[2] != y
->array
[2])
1452 if (x
->array
[1] != y
->array
[1])
1455 return x
->array
[0] == y
->array
[0];
1463 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1465 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1466 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1469 static INLINE i386_cpu_flags
1470 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1472 switch (ARRAY_SIZE (x
.array
))
1475 x
.array
[2] &= y
.array
[2];
1477 x
.array
[1] &= y
.array
[1];
1479 x
.array
[0] &= y
.array
[0];
1487 static INLINE i386_cpu_flags
1488 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1490 switch (ARRAY_SIZE (x
.array
))
1493 x
.array
[2] |= y
.array
[2];
1495 x
.array
[1] |= y
.array
[1];
1497 x
.array
[0] |= y
.array
[0];
1505 static INLINE i386_cpu_flags
1506 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1508 switch (ARRAY_SIZE (x
.array
))
1511 x
.array
[2] &= ~y
.array
[2];
1513 x
.array
[1] &= ~y
.array
[1];
1515 x
.array
[0] &= ~y
.array
[0];
1523 #define CPU_FLAGS_ARCH_MATCH 0x1
1524 #define CPU_FLAGS_64BIT_MATCH 0x2
1525 #define CPU_FLAGS_AES_MATCH 0x4
1526 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1527 #define CPU_FLAGS_AVX_MATCH 0x10
1529 #define CPU_FLAGS_32BIT_MATCH \
1530 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1531 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1532 #define CPU_FLAGS_PERFECT_MATCH \
1533 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1535 /* Return CPU flags match bits. */
1538 cpu_flags_match (const insn_template
*t
)
1540 i386_cpu_flags x
= t
->cpu_flags
;
1541 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1543 x
.bitfield
.cpu64
= 0;
1544 x
.bitfield
.cpuno64
= 0;
1546 if (cpu_flags_all_zero (&x
))
1548 /* This instruction is available on all archs. */
1549 match
|= CPU_FLAGS_32BIT_MATCH
;
1553 /* This instruction is available only on some archs. */
1554 i386_cpu_flags cpu
= cpu_arch_flags
;
1556 cpu
= cpu_flags_and (x
, cpu
);
1557 if (!cpu_flags_all_zero (&cpu
))
1559 if (x
.bitfield
.cpuavx
)
1561 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1562 if (cpu
.bitfield
.cpuavx
)
1564 /* Check SSE2AVX. */
1565 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1567 match
|= (CPU_FLAGS_ARCH_MATCH
1568 | CPU_FLAGS_AVX_MATCH
);
1570 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1571 match
|= CPU_FLAGS_AES_MATCH
;
1573 if (!x
.bitfield
.cpupclmul
1574 || cpu
.bitfield
.cpupclmul
)
1575 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1579 match
|= CPU_FLAGS_ARCH_MATCH
;
1581 else if (x
.bitfield
.cpuavx512vl
)
1583 /* Match AVX512VL. */
1584 if (cpu
.bitfield
.cpuavx512vl
)
1586 /* Need another match. */
1587 cpu
.bitfield
.cpuavx512vl
= 0;
1588 if (!cpu_flags_all_zero (&cpu
))
1589 match
|= CPU_FLAGS_32BIT_MATCH
;
1591 match
|= CPU_FLAGS_ARCH_MATCH
;
1594 match
|= CPU_FLAGS_ARCH_MATCH
;
1597 match
|= CPU_FLAGS_32BIT_MATCH
;
1603 static INLINE i386_operand_type
1604 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1606 switch (ARRAY_SIZE (x
.array
))
1609 x
.array
[2] &= y
.array
[2];
1611 x
.array
[1] &= y
.array
[1];
1613 x
.array
[0] &= y
.array
[0];
1621 static INLINE i386_operand_type
1622 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1624 switch (ARRAY_SIZE (x
.array
))
1627 x
.array
[2] |= y
.array
[2];
1629 x
.array
[1] |= y
.array
[1];
1631 x
.array
[0] |= y
.array
[0];
1639 static INLINE i386_operand_type
1640 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1642 switch (ARRAY_SIZE (x
.array
))
1645 x
.array
[2] ^= y
.array
[2];
1647 x
.array
[1] ^= y
.array
[1];
1649 x
.array
[0] ^= y
.array
[0];
1657 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1658 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1659 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1660 static const i386_operand_type inoutportreg
1661 = OPERAND_TYPE_INOUTPORTREG
;
1662 static const i386_operand_type reg16_inoutportreg
1663 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1664 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1665 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1666 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1667 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1668 static const i386_operand_type anydisp
1669 = OPERAND_TYPE_ANYDISP
;
1670 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1671 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1672 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1673 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1674 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1675 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1676 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1677 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1678 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1679 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1680 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1681 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1682 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1683 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1694 operand_type_check (i386_operand_type t
, enum operand_type c
)
1699 return (t
.bitfield
.reg8
1702 || t
.bitfield
.reg64
);
1705 return (t
.bitfield
.imm8
1709 || t
.bitfield
.imm32s
1710 || t
.bitfield
.imm64
);
1713 return (t
.bitfield
.disp8
1714 || t
.bitfield
.disp16
1715 || t
.bitfield
.disp32
1716 || t
.bitfield
.disp32s
1717 || t
.bitfield
.disp64
);
1720 return (t
.bitfield
.disp8
1721 || t
.bitfield
.disp16
1722 || t
.bitfield
.disp32
1723 || t
.bitfield
.disp32s
1724 || t
.bitfield
.disp64
1725 || t
.bitfield
.baseindex
);
1734 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1735 operand J for instruction template T. */
1738 match_reg_size (const insn_template
*t
, unsigned int j
)
1740 return !((i
.types
[j
].bitfield
.byte
1741 && !t
->operand_types
[j
].bitfield
.byte
)
1742 || (i
.types
[j
].bitfield
.word
1743 && !t
->operand_types
[j
].bitfield
.word
)
1744 || (i
.types
[j
].bitfield
.dword
1745 && !t
->operand_types
[j
].bitfield
.dword
)
1746 || (i
.types
[j
].bitfield
.qword
1747 && !t
->operand_types
[j
].bitfield
.qword
));
1750 /* Return 1 if there is no conflict in any size on operand J for
1751 instruction template T. */
1754 match_mem_size (const insn_template
*t
, unsigned int j
)
1756 return (match_reg_size (t
, j
)
1757 && !((i
.types
[j
].bitfield
.unspecified
1759 && !t
->operand_types
[j
].bitfield
.unspecified
)
1760 || (i
.types
[j
].bitfield
.fword
1761 && !t
->operand_types
[j
].bitfield
.fword
)
1762 || (i
.types
[j
].bitfield
.tbyte
1763 && !t
->operand_types
[j
].bitfield
.tbyte
)
1764 || (i
.types
[j
].bitfield
.xmmword
1765 && !t
->operand_types
[j
].bitfield
.xmmword
)
1766 || (i
.types
[j
].bitfield
.ymmword
1767 && !t
->operand_types
[j
].bitfield
.ymmword
)
1768 || (i
.types
[j
].bitfield
.zmmword
1769 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1772 /* Return 1 if there is no size conflict on any operands for
1773 instruction template T. */
1776 operand_size_match (const insn_template
*t
)
1781 /* Don't check jump instructions. */
1782 if (t
->opcode_modifier
.jump
1783 || t
->opcode_modifier
.jumpbyte
1784 || t
->opcode_modifier
.jumpdword
1785 || t
->opcode_modifier
.jumpintersegment
)
1788 /* Check memory and accumulator operand size. */
1789 for (j
= 0; j
< i
.operands
; j
++)
1791 if (t
->operand_types
[j
].bitfield
.anysize
)
1794 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1800 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1809 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1812 i
.error
= operand_size_mismatch
;
1816 /* Check reverse. */
1817 gas_assert (i
.operands
== 2);
1820 for (j
= 0; j
< 2; j
++)
1822 if (t
->operand_types
[j
].bitfield
.acc
1823 && !match_reg_size (t
, j
? 0 : 1))
1826 if (i
.types
[j
].bitfield
.mem
1827 && !match_mem_size (t
, j
? 0 : 1))
1835 operand_type_match (i386_operand_type overlap
,
1836 i386_operand_type given
)
1838 i386_operand_type temp
= overlap
;
1840 temp
.bitfield
.jumpabsolute
= 0;
1841 temp
.bitfield
.unspecified
= 0;
1842 temp
.bitfield
.byte
= 0;
1843 temp
.bitfield
.word
= 0;
1844 temp
.bitfield
.dword
= 0;
1845 temp
.bitfield
.fword
= 0;
1846 temp
.bitfield
.qword
= 0;
1847 temp
.bitfield
.tbyte
= 0;
1848 temp
.bitfield
.xmmword
= 0;
1849 temp
.bitfield
.ymmword
= 0;
1850 temp
.bitfield
.zmmword
= 0;
1851 if (operand_type_all_zero (&temp
))
1854 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1855 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1859 i
.error
= operand_type_mismatch
;
1863 /* If given types g0 and g1 are registers they must be of the same type
1864 unless the expected operand type register overlap is null.
1865 Note that Acc in a template matches every size of reg. */
1868 operand_type_register_match (i386_operand_type m0
,
1869 i386_operand_type g0
,
1870 i386_operand_type t0
,
1871 i386_operand_type m1
,
1872 i386_operand_type g1
,
1873 i386_operand_type t1
)
1875 if (!operand_type_check (g0
, reg
))
1878 if (!operand_type_check (g1
, reg
))
1881 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1882 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1883 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1884 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1887 if (m0
.bitfield
.acc
)
1889 t0
.bitfield
.reg8
= 1;
1890 t0
.bitfield
.reg16
= 1;
1891 t0
.bitfield
.reg32
= 1;
1892 t0
.bitfield
.reg64
= 1;
1895 if (m1
.bitfield
.acc
)
1897 t1
.bitfield
.reg8
= 1;
1898 t1
.bitfield
.reg16
= 1;
1899 t1
.bitfield
.reg32
= 1;
1900 t1
.bitfield
.reg64
= 1;
1903 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1904 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1905 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1906 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1909 i
.error
= register_type_mismatch
;
1914 static INLINE
unsigned int
1915 register_number (const reg_entry
*r
)
1917 unsigned int nr
= r
->reg_num
;
1919 if (r
->reg_flags
& RegRex
)
1922 if (r
->reg_flags
& RegVRex
)
1928 static INLINE
unsigned int
1929 mode_from_disp_size (i386_operand_type t
)
1931 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1933 else if (t
.bitfield
.disp16
1934 || t
.bitfield
.disp32
1935 || t
.bitfield
.disp32s
)
1942 fits_in_signed_byte (addressT num
)
1944 return num
+ 0x80 <= 0xff;
1948 fits_in_unsigned_byte (addressT num
)
1954 fits_in_unsigned_word (addressT num
)
1956 return num
<= 0xffff;
1960 fits_in_signed_word (addressT num
)
1962 return num
+ 0x8000 <= 0xffff;
1966 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1971 return num
+ 0x80000000 <= 0xffffffff;
1973 } /* fits_in_signed_long() */
1976 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
1981 return num
<= 0xffffffff;
1983 } /* fits_in_unsigned_long() */
1986 fits_in_vec_disp8 (offsetT num
)
1988 int shift
= i
.memshift
;
1994 mask
= (1 << shift
) - 1;
1996 /* Return 0 if NUM isn't properly aligned. */
2000 /* Check if NUM will fit in 8bit after shift. */
2001 return fits_in_signed_byte (num
>> shift
);
2005 fits_in_imm4 (offsetT num
)
2007 return (num
& 0xf) == num
;
2010 static i386_operand_type
2011 smallest_imm_type (offsetT num
)
2013 i386_operand_type t
;
2015 operand_type_set (&t
, 0);
2016 t
.bitfield
.imm64
= 1;
2018 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2020 /* This code is disabled on the 486 because all the Imm1 forms
2021 in the opcode table are slower on the i486. They're the
2022 versions with the implicitly specified single-position
2023 displacement, which has another syntax if you really want to
2025 t
.bitfield
.imm1
= 1;
2026 t
.bitfield
.imm8
= 1;
2027 t
.bitfield
.imm8s
= 1;
2028 t
.bitfield
.imm16
= 1;
2029 t
.bitfield
.imm32
= 1;
2030 t
.bitfield
.imm32s
= 1;
2032 else if (fits_in_signed_byte (num
))
2034 t
.bitfield
.imm8
= 1;
2035 t
.bitfield
.imm8s
= 1;
2036 t
.bitfield
.imm16
= 1;
2037 t
.bitfield
.imm32
= 1;
2038 t
.bitfield
.imm32s
= 1;
2040 else if (fits_in_unsigned_byte (num
))
2042 t
.bitfield
.imm8
= 1;
2043 t
.bitfield
.imm16
= 1;
2044 t
.bitfield
.imm32
= 1;
2045 t
.bitfield
.imm32s
= 1;
2047 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2049 t
.bitfield
.imm16
= 1;
2050 t
.bitfield
.imm32
= 1;
2051 t
.bitfield
.imm32s
= 1;
2053 else if (fits_in_signed_long (num
))
2055 t
.bitfield
.imm32
= 1;
2056 t
.bitfield
.imm32s
= 1;
2058 else if (fits_in_unsigned_long (num
))
2059 t
.bitfield
.imm32
= 1;
2065 offset_in_range (offsetT val
, int size
)
2071 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2072 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2073 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2075 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2081 /* If BFD64, sign extend val for 32bit address mode. */
2082 if (flag_code
!= CODE_64BIT
2083 || i
.prefix
[ADDR_PREFIX
])
2084 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2085 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2088 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2090 char buf1
[40], buf2
[40];
2092 sprint_value (buf1
, val
);
2093 sprint_value (buf2
, val
& mask
);
2094 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2108 a. PREFIX_EXIST if attempting to add a prefix where one from the
2109 same class already exists.
2110 b. PREFIX_LOCK if lock prefix is added.
2111 c. PREFIX_REP if rep/repne prefix is added.
2112 d. PREFIX_OTHER if other prefix is added.
2115 static enum PREFIX_GROUP
2116 add_prefix (unsigned int prefix
)
2118 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2121 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2122 && flag_code
== CODE_64BIT
)
2124 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2125 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2126 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2137 case CS_PREFIX_OPCODE
:
2138 case DS_PREFIX_OPCODE
:
2139 case ES_PREFIX_OPCODE
:
2140 case FS_PREFIX_OPCODE
:
2141 case GS_PREFIX_OPCODE
:
2142 case SS_PREFIX_OPCODE
:
2146 case REPNE_PREFIX_OPCODE
:
2147 case REPE_PREFIX_OPCODE
:
2152 case LOCK_PREFIX_OPCODE
:
2161 case ADDR_PREFIX_OPCODE
:
2165 case DATA_PREFIX_OPCODE
:
2169 if (i
.prefix
[q
] != 0)
2177 i
.prefix
[q
] |= prefix
;
2180 as_bad (_("same type of prefix used twice"));
2186 update_code_flag (int value
, int check
)
2188 PRINTF_LIKE ((*as_error
));
2190 flag_code
= (enum flag_code
) value
;
2191 if (flag_code
== CODE_64BIT
)
2193 cpu_arch_flags
.bitfield
.cpu64
= 1;
2194 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2198 cpu_arch_flags
.bitfield
.cpu64
= 0;
2199 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2201 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2204 as_error
= as_fatal
;
2207 (*as_error
) (_("64bit mode not supported on `%s'."),
2208 cpu_arch_name
? cpu_arch_name
: default_arch
);
2210 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2213 as_error
= as_fatal
;
2216 (*as_error
) (_("32bit mode not supported on `%s'."),
2217 cpu_arch_name
? cpu_arch_name
: default_arch
);
2219 stackop_size
= '\0';
2223 set_code_flag (int value
)
2225 update_code_flag (value
, 0);
2229 set_16bit_gcc_code_flag (int new_code_flag
)
2231 flag_code
= (enum flag_code
) new_code_flag
;
2232 if (flag_code
!= CODE_16BIT
)
2234 cpu_arch_flags
.bitfield
.cpu64
= 0;
2235 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2236 stackop_size
= LONG_MNEM_SUFFIX
;
2240 set_intel_syntax (int syntax_flag
)
2242 /* Find out if register prefixing is specified. */
2243 int ask_naked_reg
= 0;
2246 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2249 int e
= get_symbol_name (&string
);
2251 if (strcmp (string
, "prefix") == 0)
2253 else if (strcmp (string
, "noprefix") == 0)
2256 as_bad (_("bad argument to syntax directive."));
2257 (void) restore_line_pointer (e
);
2259 demand_empty_rest_of_line ();
2261 intel_syntax
= syntax_flag
;
2263 if (ask_naked_reg
== 0)
2264 allow_naked_reg
= (intel_syntax
2265 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2267 allow_naked_reg
= (ask_naked_reg
< 0);
2269 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2271 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2272 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2273 register_prefix
= allow_naked_reg
? "" : "%";
2277 set_intel_mnemonic (int mnemonic_flag
)
2279 intel_mnemonic
= mnemonic_flag
;
2283 set_allow_index_reg (int flag
)
2285 allow_index_reg
= flag
;
2289 set_check (int what
)
2291 enum check_kind
*kind
;
2296 kind
= &operand_check
;
2307 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2310 int e
= get_symbol_name (&string
);
2312 if (strcmp (string
, "none") == 0)
2314 else if (strcmp (string
, "warning") == 0)
2315 *kind
= check_warning
;
2316 else if (strcmp (string
, "error") == 0)
2317 *kind
= check_error
;
2319 as_bad (_("bad argument to %s_check directive."), str
);
2320 (void) restore_line_pointer (e
);
2323 as_bad (_("missing argument for %s_check directive"), str
);
2325 demand_empty_rest_of_line ();
2329 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2330 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2332 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2333 static const char *arch
;
2335 /* Intel LIOM is only supported on ELF. */
2341 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2342 use default_arch. */
2343 arch
= cpu_arch_name
;
2345 arch
= default_arch
;
2348 /* If we are targeting Intel MCU, we must enable it. */
2349 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2350 || new_flag
.bitfield
.cpuiamcu
)
2353 /* If we are targeting Intel L1OM, we must enable it. */
2354 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2355 || new_flag
.bitfield
.cpul1om
)
2358 /* If we are targeting Intel K1OM, we must enable it. */
2359 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2360 || new_flag
.bitfield
.cpuk1om
)
2363 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2368 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2372 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2375 int e
= get_symbol_name (&string
);
2377 i386_cpu_flags flags
;
2379 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2381 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2383 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2387 cpu_arch_name
= cpu_arch
[j
].name
;
2388 cpu_sub_arch_name
= NULL
;
2389 cpu_arch_flags
= cpu_arch
[j
].flags
;
2390 if (flag_code
== CODE_64BIT
)
2392 cpu_arch_flags
.bitfield
.cpu64
= 1;
2393 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2397 cpu_arch_flags
.bitfield
.cpu64
= 0;
2398 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2400 cpu_arch_isa
= cpu_arch
[j
].type
;
2401 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2402 if (!cpu_arch_tune_set
)
2404 cpu_arch_tune
= cpu_arch_isa
;
2405 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2410 flags
= cpu_flags_or (cpu_arch_flags
,
2413 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2415 if (cpu_sub_arch_name
)
2417 char *name
= cpu_sub_arch_name
;
2418 cpu_sub_arch_name
= concat (name
,
2420 (const char *) NULL
);
2424 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2425 cpu_arch_flags
= flags
;
2426 cpu_arch_isa_flags
= flags
;
2428 (void) restore_line_pointer (e
);
2429 demand_empty_rest_of_line ();
2434 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2436 /* Disable an ISA entension. */
2437 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2438 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2440 flags
= cpu_flags_and_not (cpu_arch_flags
,
2441 cpu_noarch
[j
].flags
);
2442 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2444 if (cpu_sub_arch_name
)
2446 char *name
= cpu_sub_arch_name
;
2447 cpu_sub_arch_name
= concat (name
, string
,
2448 (const char *) NULL
);
2452 cpu_sub_arch_name
= xstrdup (string
);
2453 cpu_arch_flags
= flags
;
2454 cpu_arch_isa_flags
= flags
;
2456 (void) restore_line_pointer (e
);
2457 demand_empty_rest_of_line ();
2461 j
= ARRAY_SIZE (cpu_arch
);
2464 if (j
>= ARRAY_SIZE (cpu_arch
))
2465 as_bad (_("no such architecture: `%s'"), string
);
2467 *input_line_pointer
= e
;
2470 as_bad (_("missing cpu architecture"));
2472 no_cond_jump_promotion
= 0;
2473 if (*input_line_pointer
== ','
2474 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2479 ++input_line_pointer
;
2480 e
= get_symbol_name (&string
);
2482 if (strcmp (string
, "nojumps") == 0)
2483 no_cond_jump_promotion
= 1;
2484 else if (strcmp (string
, "jumps") == 0)
2487 as_bad (_("no such architecture modifier: `%s'"), string
);
2489 (void) restore_line_pointer (e
);
2492 demand_empty_rest_of_line ();
2495 enum bfd_architecture
2498 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2500 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2501 || flag_code
!= CODE_64BIT
)
2502 as_fatal (_("Intel L1OM is 64bit ELF only"));
2503 return bfd_arch_l1om
;
2505 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2507 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2508 || flag_code
!= CODE_64BIT
)
2509 as_fatal (_("Intel K1OM is 64bit ELF only"));
2510 return bfd_arch_k1om
;
2512 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2514 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2515 || flag_code
== CODE_64BIT
)
2516 as_fatal (_("Intel MCU is 32bit ELF only"));
2517 return bfd_arch_iamcu
;
2520 return bfd_arch_i386
;
2526 if (!strncmp (default_arch
, "x86_64", 6))
2528 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2530 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2531 || default_arch
[6] != '\0')
2532 as_fatal (_("Intel L1OM is 64bit ELF only"));
2533 return bfd_mach_l1om
;
2535 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2537 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2538 || default_arch
[6] != '\0')
2539 as_fatal (_("Intel K1OM is 64bit ELF only"));
2540 return bfd_mach_k1om
;
2542 else if (default_arch
[6] == '\0')
2543 return bfd_mach_x86_64
;
2545 return bfd_mach_x64_32
;
2547 else if (!strcmp (default_arch
, "i386")
2548 || !strcmp (default_arch
, "iamcu"))
2550 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2552 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2553 as_fatal (_("Intel MCU is 32bit ELF only"));
2554 return bfd_mach_i386_iamcu
;
2557 return bfd_mach_i386_i386
;
2560 as_fatal (_("unknown architecture"));
2566 const char *hash_err
;
2568 /* Initialize op_hash hash table. */
2569 op_hash
= hash_new ();
2572 const insn_template
*optab
;
2573 templates
*core_optab
;
2575 /* Setup for loop. */
2577 core_optab
= XNEW (templates
);
2578 core_optab
->start
= optab
;
2583 if (optab
->name
== NULL
2584 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2586 /* different name --> ship out current template list;
2587 add to hash table; & begin anew. */
2588 core_optab
->end
= optab
;
2589 hash_err
= hash_insert (op_hash
,
2591 (void *) core_optab
);
2594 as_fatal (_("can't hash %s: %s"),
2598 if (optab
->name
== NULL
)
2600 core_optab
= XNEW (templates
);
2601 core_optab
->start
= optab
;
2606 /* Initialize reg_hash hash table. */
2607 reg_hash
= hash_new ();
2609 const reg_entry
*regtab
;
2610 unsigned int regtab_size
= i386_regtab_size
;
2612 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2614 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2616 as_fatal (_("can't hash %s: %s"),
2622 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2627 for (c
= 0; c
< 256; c
++)
2632 mnemonic_chars
[c
] = c
;
2633 register_chars
[c
] = c
;
2634 operand_chars
[c
] = c
;
2636 else if (ISLOWER (c
))
2638 mnemonic_chars
[c
] = c
;
2639 register_chars
[c
] = c
;
2640 operand_chars
[c
] = c
;
2642 else if (ISUPPER (c
))
2644 mnemonic_chars
[c
] = TOLOWER (c
);
2645 register_chars
[c
] = mnemonic_chars
[c
];
2646 operand_chars
[c
] = c
;
2648 else if (c
== '{' || c
== '}')
2649 operand_chars
[c
] = c
;
2651 if (ISALPHA (c
) || ISDIGIT (c
))
2652 identifier_chars
[c
] = c
;
2655 identifier_chars
[c
] = c
;
2656 operand_chars
[c
] = c
;
2661 identifier_chars
['@'] = '@';
2664 identifier_chars
['?'] = '?';
2665 operand_chars
['?'] = '?';
2667 digit_chars
['-'] = '-';
2668 mnemonic_chars
['_'] = '_';
2669 mnemonic_chars
['-'] = '-';
2670 mnemonic_chars
['.'] = '.';
2671 identifier_chars
['_'] = '_';
2672 identifier_chars
['.'] = '.';
2674 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2675 operand_chars
[(unsigned char) *p
] = *p
;
2678 if (flag_code
== CODE_64BIT
)
2680 #if defined (OBJ_COFF) && defined (TE_PE)
2681 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2684 x86_dwarf2_return_column
= 16;
2686 x86_cie_data_alignment
= -8;
2690 x86_dwarf2_return_column
= 8;
2691 x86_cie_data_alignment
= -4;
2696 i386_print_statistics (FILE *file
)
2698 hash_print_statistics (file
, "i386 opcode", op_hash
);
2699 hash_print_statistics (file
, "i386 register", reg_hash
);
2704 /* Debugging routines for md_assemble. */
2705 static void pte (insn_template
*);
2706 static void pt (i386_operand_type
);
2707 static void pe (expressionS
*);
2708 static void ps (symbolS
*);
2711 pi (char *line
, i386_insn
*x
)
2715 fprintf (stdout
, "%s: template ", line
);
2717 fprintf (stdout
, " address: base %s index %s scale %x\n",
2718 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2719 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2720 x
->log2_scale_factor
);
2721 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2722 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2723 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2724 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2725 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2726 (x
->rex
& REX_W
) != 0,
2727 (x
->rex
& REX_R
) != 0,
2728 (x
->rex
& REX_X
) != 0,
2729 (x
->rex
& REX_B
) != 0);
2730 for (j
= 0; j
< x
->operands
; j
++)
2732 fprintf (stdout
, " #%d: ", j
+ 1);
2734 fprintf (stdout
, "\n");
2735 if (x
->types
[j
].bitfield
.reg8
2736 || x
->types
[j
].bitfield
.reg16
2737 || x
->types
[j
].bitfield
.reg32
2738 || x
->types
[j
].bitfield
.reg64
2739 || x
->types
[j
].bitfield
.regmmx
2740 || x
->types
[j
].bitfield
.regxmm
2741 || x
->types
[j
].bitfield
.regymm
2742 || x
->types
[j
].bitfield
.regzmm
2743 || x
->types
[j
].bitfield
.sreg2
2744 || x
->types
[j
].bitfield
.sreg3
2745 || x
->types
[j
].bitfield
.control
2746 || x
->types
[j
].bitfield
.debug
2747 || x
->types
[j
].bitfield
.test
)
2748 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2749 if (operand_type_check (x
->types
[j
], imm
))
2751 if (operand_type_check (x
->types
[j
], disp
))
2752 pe (x
->op
[j
].disps
);
2757 pte (insn_template
*t
)
2760 fprintf (stdout
, " %d operands ", t
->operands
);
2761 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2762 if (t
->extension_opcode
!= None
)
2763 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2764 if (t
->opcode_modifier
.d
)
2765 fprintf (stdout
, "D");
2766 if (t
->opcode_modifier
.w
)
2767 fprintf (stdout
, "W");
2768 fprintf (stdout
, "\n");
2769 for (j
= 0; j
< t
->operands
; j
++)
2771 fprintf (stdout
, " #%d type ", j
+ 1);
2772 pt (t
->operand_types
[j
]);
2773 fprintf (stdout
, "\n");
2780 fprintf (stdout
, " operation %d\n", e
->X_op
);
2781 fprintf (stdout
, " add_number %ld (%lx)\n",
2782 (long) e
->X_add_number
, (long) e
->X_add_number
);
2783 if (e
->X_add_symbol
)
2785 fprintf (stdout
, " add_symbol ");
2786 ps (e
->X_add_symbol
);
2787 fprintf (stdout
, "\n");
2791 fprintf (stdout
, " op_symbol ");
2792 ps (e
->X_op_symbol
);
2793 fprintf (stdout
, "\n");
2800 fprintf (stdout
, "%s type %s%s",
2802 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2803 segment_name (S_GET_SEGMENT (s
)));
2806 static struct type_name
2808 i386_operand_type mask
;
2811 const type_names
[] =
2813 { OPERAND_TYPE_REG8
, "r8" },
2814 { OPERAND_TYPE_REG16
, "r16" },
2815 { OPERAND_TYPE_REG32
, "r32" },
2816 { OPERAND_TYPE_REG64
, "r64" },
2817 { OPERAND_TYPE_IMM8
, "i8" },
2818 { OPERAND_TYPE_IMM8
, "i8s" },
2819 { OPERAND_TYPE_IMM16
, "i16" },
2820 { OPERAND_TYPE_IMM32
, "i32" },
2821 { OPERAND_TYPE_IMM32S
, "i32s" },
2822 { OPERAND_TYPE_IMM64
, "i64" },
2823 { OPERAND_TYPE_IMM1
, "i1" },
2824 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2825 { OPERAND_TYPE_DISP8
, "d8" },
2826 { OPERAND_TYPE_DISP16
, "d16" },
2827 { OPERAND_TYPE_DISP32
, "d32" },
2828 { OPERAND_TYPE_DISP32S
, "d32s" },
2829 { OPERAND_TYPE_DISP64
, "d64" },
2830 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2831 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2832 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2833 { OPERAND_TYPE_CONTROL
, "control reg" },
2834 { OPERAND_TYPE_TEST
, "test reg" },
2835 { OPERAND_TYPE_DEBUG
, "debug reg" },
2836 { OPERAND_TYPE_FLOATREG
, "FReg" },
2837 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2838 { OPERAND_TYPE_SREG2
, "SReg2" },
2839 { OPERAND_TYPE_SREG3
, "SReg3" },
2840 { OPERAND_TYPE_ACC
, "Acc" },
2841 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2842 { OPERAND_TYPE_REGMMX
, "rMMX" },
2843 { OPERAND_TYPE_REGXMM
, "rXMM" },
2844 { OPERAND_TYPE_REGYMM
, "rYMM" },
2845 { OPERAND_TYPE_REGZMM
, "rZMM" },
2846 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2847 { OPERAND_TYPE_ESSEG
, "es" },
2851 pt (i386_operand_type t
)
2854 i386_operand_type a
;
2856 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2858 a
= operand_type_and (t
, type_names
[j
].mask
);
2859 if (!operand_type_all_zero (&a
))
2860 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2865 #endif /* DEBUG386 */
2867 static bfd_reloc_code_real_type
2868 reloc (unsigned int size
,
2871 bfd_reloc_code_real_type other
)
2873 if (other
!= NO_RELOC
)
2875 reloc_howto_type
*rel
;
2880 case BFD_RELOC_X86_64_GOT32
:
2881 return BFD_RELOC_X86_64_GOT64
;
2883 case BFD_RELOC_X86_64_GOTPLT64
:
2884 return BFD_RELOC_X86_64_GOTPLT64
;
2886 case BFD_RELOC_X86_64_PLTOFF64
:
2887 return BFD_RELOC_X86_64_PLTOFF64
;
2889 case BFD_RELOC_X86_64_GOTPC32
:
2890 other
= BFD_RELOC_X86_64_GOTPC64
;
2892 case BFD_RELOC_X86_64_GOTPCREL
:
2893 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2895 case BFD_RELOC_X86_64_TPOFF32
:
2896 other
= BFD_RELOC_X86_64_TPOFF64
;
2898 case BFD_RELOC_X86_64_DTPOFF32
:
2899 other
= BFD_RELOC_X86_64_DTPOFF64
;
2905 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2906 if (other
== BFD_RELOC_SIZE32
)
2909 other
= BFD_RELOC_SIZE64
;
2912 as_bad (_("there are no pc-relative size relocations"));
2918 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2919 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2922 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2924 as_bad (_("unknown relocation (%u)"), other
);
2925 else if (size
!= bfd_get_reloc_size (rel
))
2926 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2927 bfd_get_reloc_size (rel
),
2929 else if (pcrel
&& !rel
->pc_relative
)
2930 as_bad (_("non-pc-relative relocation for pc-relative field"));
2931 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2933 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2935 as_bad (_("relocated field and relocation type differ in signedness"));
2944 as_bad (_("there are no unsigned pc-relative relocations"));
2947 case 1: return BFD_RELOC_8_PCREL
;
2948 case 2: return BFD_RELOC_16_PCREL
;
2949 case 4: return BFD_RELOC_32_PCREL
;
2950 case 8: return BFD_RELOC_64_PCREL
;
2952 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2959 case 4: return BFD_RELOC_X86_64_32S
;
2964 case 1: return BFD_RELOC_8
;
2965 case 2: return BFD_RELOC_16
;
2966 case 4: return BFD_RELOC_32
;
2967 case 8: return BFD_RELOC_64
;
2969 as_bad (_("cannot do %s %u byte relocation"),
2970 sign
> 0 ? "signed" : "unsigned", size
);
2976 /* Here we decide which fixups can be adjusted to make them relative to
2977 the beginning of the section instead of the symbol. Basically we need
2978 to make sure that the dynamic relocations are done correctly, so in
2979 some cases we force the original symbol to be used. */
2982 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2984 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2988 /* Don't adjust pc-relative references to merge sections in 64-bit
2990 if (use_rela_relocations
2991 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2995 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2996 and changed later by validate_fix. */
2997 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2998 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3001 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3002 for size relocations. */
3003 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3004 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3005 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3006 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3007 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3008 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3009 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3010 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3011 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3012 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3013 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3014 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3015 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3016 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3017 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3018 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3019 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3020 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3021 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3022 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3023 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3024 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3025 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3026 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3027 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3028 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3029 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3030 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3031 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3032 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3033 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3034 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3035 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3042 intel_float_operand (const char *mnemonic
)
3044 /* Note that the value returned is meaningful only for opcodes with (memory)
3045 operands, hence the code here is free to improperly handle opcodes that
3046 have no operands (for better performance and smaller code). */
3048 if (mnemonic
[0] != 'f')
3049 return 0; /* non-math */
3051 switch (mnemonic
[1])
3053 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3054 the fs segment override prefix not currently handled because no
3055 call path can make opcodes without operands get here */
3057 return 2 /* integer op */;
3059 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3060 return 3; /* fldcw/fldenv */
3063 if (mnemonic
[2] != 'o' /* fnop */)
3064 return 3; /* non-waiting control op */
3067 if (mnemonic
[2] == 's')
3068 return 3; /* frstor/frstpm */
3071 if (mnemonic
[2] == 'a')
3072 return 3; /* fsave */
3073 if (mnemonic
[2] == 't')
3075 switch (mnemonic
[3])
3077 case 'c': /* fstcw */
3078 case 'd': /* fstdw */
3079 case 'e': /* fstenv */
3080 case 's': /* fsts[gw] */
3086 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3087 return 0; /* fxsave/fxrstor are not really math ops */
3094 /* Build the VEX prefix. */
3097 build_vex_prefix (const insn_template
*t
)
3099 unsigned int register_specifier
;
3100 unsigned int implied_prefix
;
3101 unsigned int vector_length
;
3103 /* Check register specifier. */
3104 if (i
.vex
.register_specifier
)
3106 register_specifier
=
3107 ~register_number (i
.vex
.register_specifier
) & 0xf;
3108 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3111 register_specifier
= 0xf;
3113 /* Use 2-byte VEX prefix by swappping destination and source
3116 && i
.operands
== i
.reg_operands
3117 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3118 && i
.tm
.opcode_modifier
.s
3121 unsigned int xchg
= i
.operands
- 1;
3122 union i386_op temp_op
;
3123 i386_operand_type temp_type
;
3125 temp_type
= i
.types
[xchg
];
3126 i
.types
[xchg
] = i
.types
[0];
3127 i
.types
[0] = temp_type
;
3128 temp_op
= i
.op
[xchg
];
3129 i
.op
[xchg
] = i
.op
[0];
3132 gas_assert (i
.rm
.mode
== 3);
3136 i
.rm
.regmem
= i
.rm
.reg
;
3139 /* Use the next insn. */
3143 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3144 vector_length
= avxscalar
;
3146 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3148 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3153 case DATA_PREFIX_OPCODE
:
3156 case REPE_PREFIX_OPCODE
:
3159 case REPNE_PREFIX_OPCODE
:
3166 /* Use 2-byte VEX prefix if possible. */
3167 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3168 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3169 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3171 /* 2-byte VEX prefix. */
3175 i
.vex
.bytes
[0] = 0xc5;
3177 /* Check the REX.R bit. */
3178 r
= (i
.rex
& REX_R
) ? 0 : 1;
3179 i
.vex
.bytes
[1] = (r
<< 7
3180 | register_specifier
<< 3
3181 | vector_length
<< 2
3186 /* 3-byte VEX prefix. */
3191 switch (i
.tm
.opcode_modifier
.vexopcode
)
3195 i
.vex
.bytes
[0] = 0xc4;
3199 i
.vex
.bytes
[0] = 0xc4;
3203 i
.vex
.bytes
[0] = 0xc4;
3207 i
.vex
.bytes
[0] = 0x8f;
3211 i
.vex
.bytes
[0] = 0x8f;
3215 i
.vex
.bytes
[0] = 0x8f;
3221 /* The high 3 bits of the second VEX byte are 1's compliment
3222 of RXB bits from REX. */
3223 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3225 /* Check the REX.W bit. */
3226 w
= (i
.rex
& REX_W
) ? 1 : 0;
3227 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3230 i
.vex
.bytes
[2] = (w
<< 7
3231 | register_specifier
<< 3
3232 | vector_length
<< 2
3237 /* Build the EVEX prefix. */
3240 build_evex_prefix (void)
3242 unsigned int register_specifier
;
3243 unsigned int implied_prefix
;
3245 rex_byte vrex_used
= 0;
3247 /* Check register specifier. */
3248 if (i
.vex
.register_specifier
)
3250 gas_assert ((i
.vrex
& REX_X
) == 0);
3252 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3253 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3254 register_specifier
+= 8;
3255 /* The upper 16 registers are encoded in the fourth byte of the
3257 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3258 i
.vex
.bytes
[3] = 0x8;
3259 register_specifier
= ~register_specifier
& 0xf;
3263 register_specifier
= 0xf;
3265 /* Encode upper 16 vector index register in the fourth byte of
3267 if (!(i
.vrex
& REX_X
))
3268 i
.vex
.bytes
[3] = 0x8;
3273 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3278 case DATA_PREFIX_OPCODE
:
3281 case REPE_PREFIX_OPCODE
:
3284 case REPNE_PREFIX_OPCODE
:
3291 /* 4 byte EVEX prefix. */
3293 i
.vex
.bytes
[0] = 0x62;
3296 switch (i
.tm
.opcode_modifier
.vexopcode
)
3312 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3314 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3316 /* The fifth bit of the second EVEX byte is 1's compliment of the
3317 REX_R bit in VREX. */
3318 if (!(i
.vrex
& REX_R
))
3319 i
.vex
.bytes
[1] |= 0x10;
3323 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3325 /* When all operands are registers, the REX_X bit in REX is not
3326 used. We reuse it to encode the upper 16 registers, which is
3327 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3328 as 1's compliment. */
3329 if ((i
.vrex
& REX_B
))
3332 i
.vex
.bytes
[1] &= ~0x40;
3336 /* EVEX instructions shouldn't need the REX prefix. */
3337 i
.vrex
&= ~vrex_used
;
3338 gas_assert (i
.vrex
== 0);
3340 /* Check the REX.W bit. */
3341 w
= (i
.rex
& REX_W
) ? 1 : 0;
3342 if (i
.tm
.opcode_modifier
.vexw
)
3344 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3347 /* If w is not set it means we are dealing with WIG instruction. */
3350 if (evexwig
== evexw1
)
3354 /* Encode the U bit. */
3355 implied_prefix
|= 0x4;
3357 /* The third byte of the EVEX prefix. */
3358 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3360 /* The fourth byte of the EVEX prefix. */
3361 /* The zeroing-masking bit. */
3362 if (i
.mask
&& i
.mask
->zeroing
)
3363 i
.vex
.bytes
[3] |= 0x80;
3365 /* Don't always set the broadcast bit if there is no RC. */
3368 /* Encode the vector length. */
3369 unsigned int vec_length
;
3371 switch (i
.tm
.opcode_modifier
.evex
)
3373 case EVEXLIG
: /* LL' is ignored */
3374 vec_length
= evexlig
<< 5;
3377 vec_length
= 0 << 5;
3380 vec_length
= 1 << 5;
3383 vec_length
= 2 << 5;
3389 i
.vex
.bytes
[3] |= vec_length
;
3390 /* Encode the broadcast bit. */
3392 i
.vex
.bytes
[3] |= 0x10;
3396 if (i
.rounding
->type
!= saeonly
)
3397 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3399 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3402 if (i
.mask
&& i
.mask
->mask
)
3403 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3407 process_immext (void)
3411 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3414 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3415 with an opcode suffix which is coded in the same place as an
3416 8-bit immediate field would be.
3417 Here we check those operands and remove them afterwards. */
3420 for (x
= 0; x
< i
.operands
; x
++)
3421 if (register_number (i
.op
[x
].regs
) != x
)
3422 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3423 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3429 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3431 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3432 suffix which is coded in the same place as an 8-bit immediate
3434 Here we check those operands and remove them afterwards. */
3437 if (i
.operands
!= 3)
3440 for (x
= 0; x
< 2; x
++)
3441 if (register_number (i
.op
[x
].regs
) != x
)
3442 goto bad_register_operand
;
3444 /* Check for third operand for mwaitx/monitorx insn. */
3445 if (register_number (i
.op
[x
].regs
)
3446 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3448 bad_register_operand
:
3449 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3450 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3457 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3458 which is coded in the same place as an 8-bit immediate field
3459 would be. Here we fake an 8-bit immediate operand from the
3460 opcode suffix stored in tm.extension_opcode.
3462 AVX instructions also use this encoding, for some of
3463 3 argument instructions. */
3465 gas_assert (i
.imm_operands
<= 1
3467 || ((i
.tm
.opcode_modifier
.vex
3468 || i
.tm
.opcode_modifier
.evex
)
3469 && i
.operands
<= 4)));
3471 exp
= &im_expressions
[i
.imm_operands
++];
3472 i
.op
[i
.operands
].imms
= exp
;
3473 i
.types
[i
.operands
] = imm8
;
3475 exp
->X_op
= O_constant
;
3476 exp
->X_add_number
= i
.tm
.extension_opcode
;
3477 i
.tm
.extension_opcode
= None
;
3484 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3489 as_bad (_("invalid instruction `%s' after `%s'"),
3490 i
.tm
.name
, i
.hle_prefix
);
3493 if (i
.prefix
[LOCK_PREFIX
])
3495 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3499 case HLEPrefixRelease
:
3500 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3502 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3506 if (i
.mem_operands
== 0
3507 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3509 as_bad (_("memory destination needed for instruction `%s'"
3510 " after `xrelease'"), i
.tm
.name
);
3517 /* This is the guts of the machine-dependent assembler. LINE points to a
3518 machine dependent instruction. This function is supposed to emit
3519 the frags/bytes it assembles to. */
3522 md_assemble (char *line
)
3525 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
3526 const insn_template
*t
;
3528 /* Initialize globals. */
3529 memset (&i
, '\0', sizeof (i
));
3530 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3531 i
.reloc
[j
] = NO_RELOC
;
3532 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3533 memset (im_expressions
, '\0', sizeof (im_expressions
));
3534 save_stack_p
= save_stack
;
3536 /* First parse an instruction mnemonic & call i386_operand for the operands.
3537 We assume that the scrubber has arranged it so that line[0] is the valid
3538 start of a (possibly prefixed) mnemonic. */
3540 line
= parse_insn (line
, mnemonic
);
3543 mnem_suffix
= i
.suffix
;
3545 line
= parse_operands (line
, mnemonic
);
3547 xfree (i
.memop1_string
);
3548 i
.memop1_string
= NULL
;
3552 /* Now we've parsed the mnemonic into a set of templates, and have the
3553 operands at hand. */
3555 /* All intel opcodes have reversed operands except for "bound" and
3556 "enter". We also don't reverse intersegment "jmp" and "call"
3557 instructions with 2 immediate operands so that the immediate segment
3558 precedes the offset, as it does when in AT&T mode. */
3561 && (strcmp (mnemonic
, "bound") != 0)
3562 && (strcmp (mnemonic
, "invlpga") != 0)
3563 && !(operand_type_check (i
.types
[0], imm
)
3564 && operand_type_check (i
.types
[1], imm
)))
3567 /* The order of the immediates should be reversed
3568 for 2 immediates extrq and insertq instructions */
3569 if (i
.imm_operands
== 2
3570 && (strcmp (mnemonic
, "extrq") == 0
3571 || strcmp (mnemonic
, "insertq") == 0))
3572 swap_2_operands (0, 1);
3577 /* Don't optimize displacement for movabs since it only takes 64bit
3580 && i
.disp_encoding
!= disp_encoding_32bit
3581 && (flag_code
!= CODE_64BIT
3582 || strcmp (mnemonic
, "movabs") != 0))
3585 /* Next, we find a template that matches the given insn,
3586 making sure the overlap of the given operands types is consistent
3587 with the template operand types. */
3589 if (!(t
= match_template (mnem_suffix
)))
3592 if (sse_check
!= check_none
3593 && !i
.tm
.opcode_modifier
.noavx
3594 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3595 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3596 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3597 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3598 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3599 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3601 (sse_check
== check_warning
3603 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3606 /* Zap movzx and movsx suffix. The suffix has been set from
3607 "word ptr" or "byte ptr" on the source operand in Intel syntax
3608 or extracted from mnemonic in AT&T syntax. But we'll use
3609 the destination register to choose the suffix for encoding. */
3610 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3612 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3613 there is no suffix, the default will be byte extension. */
3614 if (i
.reg_operands
!= 2
3617 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3622 if (i
.tm
.opcode_modifier
.fwait
)
3623 if (!add_prefix (FWAIT_OPCODE
))
3626 /* Check if REP prefix is OK. */
3627 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3629 as_bad (_("invalid instruction `%s' after `%s'"),
3630 i
.tm
.name
, i
.rep_prefix
);
3634 /* Check for lock without a lockable instruction. Destination operand
3635 must be memory unless it is xchg (0x86). */
3636 if (i
.prefix
[LOCK_PREFIX
]
3637 && (!i
.tm
.opcode_modifier
.islockable
3638 || i
.mem_operands
== 0
3639 || (i
.tm
.base_opcode
!= 0x86
3640 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3642 as_bad (_("expecting lockable instruction after `lock'"));
3646 /* Check if HLE prefix is OK. */
3647 if (i
.hle_prefix
&& !check_hle ())
3650 /* Check BND prefix. */
3651 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3652 as_bad (_("expecting valid branch instruction after `bnd'"));
3654 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
3656 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
3657 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3658 else if (flag_code
!= CODE_16BIT
3659 ? i
.prefix
[ADDR_PREFIX
]
3660 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
3661 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3664 /* Insert BND prefix. */
3666 && i
.tm
.opcode_modifier
.bndprefixok
3667 && !i
.prefix
[BND_PREFIX
])
3668 add_prefix (BND_PREFIX_OPCODE
);
3670 /* Check string instruction segment overrides. */
3671 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3673 if (!check_string ())
3675 i
.disp_operands
= 0;
3678 if (!process_suffix ())
3681 /* Update operand types. */
3682 for (j
= 0; j
< i
.operands
; j
++)
3683 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3685 /* Make still unresolved immediate matches conform to size of immediate
3686 given in i.suffix. */
3687 if (!finalize_imm ())
3690 if (i
.types
[0].bitfield
.imm1
)
3691 i
.imm_operands
= 0; /* kludge for shift insns. */
3693 /* We only need to check those implicit registers for instructions
3694 with 3 operands or less. */
3695 if (i
.operands
<= 3)
3696 for (j
= 0; j
< i
.operands
; j
++)
3697 if (i
.types
[j
].bitfield
.inoutportreg
3698 || i
.types
[j
].bitfield
.shiftcount
3699 || i
.types
[j
].bitfield
.acc
3700 || i
.types
[j
].bitfield
.floatacc
)
3703 /* ImmExt should be processed after SSE2AVX. */
3704 if (!i
.tm
.opcode_modifier
.sse2avx
3705 && i
.tm
.opcode_modifier
.immext
)
3708 /* For insns with operands there are more diddles to do to the opcode. */
3711 if (!process_operands ())
3714 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3716 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3717 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3720 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3722 if (flag_code
== CODE_16BIT
)
3724 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3729 if (i
.tm
.opcode_modifier
.vex
)
3730 build_vex_prefix (t
);
3732 build_evex_prefix ();
3735 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3736 instructions may define INT_OPCODE as well, so avoid this corner
3737 case for those instructions that use MODRM. */
3738 if (i
.tm
.base_opcode
== INT_OPCODE
3739 && !i
.tm
.opcode_modifier
.modrm
3740 && i
.op
[0].imms
->X_add_number
== 3)
3742 i
.tm
.base_opcode
= INT3_OPCODE
;
3746 if ((i
.tm
.opcode_modifier
.jump
3747 || i
.tm
.opcode_modifier
.jumpbyte
3748 || i
.tm
.opcode_modifier
.jumpdword
)
3749 && i
.op
[0].disps
->X_op
== O_constant
)
3751 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3752 the absolute address given by the constant. Since ix86 jumps and
3753 calls are pc relative, we need to generate a reloc. */
3754 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3755 i
.op
[0].disps
->X_op
= O_symbol
;
3758 if (i
.tm
.opcode_modifier
.rex64
)
3761 /* For 8 bit registers we need an empty rex prefix. Also if the
3762 instruction already has a prefix, we need to convert old
3763 registers to new ones. */
3765 if ((i
.types
[0].bitfield
.reg8
3766 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3767 || (i
.types
[1].bitfield
.reg8
3768 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3769 || ((i
.types
[0].bitfield
.reg8
3770 || i
.types
[1].bitfield
.reg8
)
3775 i
.rex
|= REX_OPCODE
;
3776 for (x
= 0; x
< 2; x
++)
3778 /* Look for 8 bit operand that uses old registers. */
3779 if (i
.types
[x
].bitfield
.reg8
3780 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3782 /* In case it is "hi" register, give up. */
3783 if (i
.op
[x
].regs
->reg_num
> 3)
3784 as_bad (_("can't encode register '%s%s' in an "
3785 "instruction requiring REX prefix."),
3786 register_prefix
, i
.op
[x
].regs
->reg_name
);
3788 /* Otherwise it is equivalent to the extended register.
3789 Since the encoding doesn't change this is merely
3790 cosmetic cleanup for debug output. */
3792 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3798 add_prefix (REX_OPCODE
| i
.rex
);
3800 /* We are ready to output the insn. */
3805 parse_insn (char *line
, char *mnemonic
)
3808 char *token_start
= l
;
3811 const insn_template
*t
;
3817 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3822 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3824 as_bad (_("no such instruction: `%s'"), token_start
);
3829 if (!is_space_char (*l
)
3830 && *l
!= END_OF_INSN
3832 || (*l
!= PREFIX_SEPARATOR
3835 as_bad (_("invalid character %s in mnemonic"),
3836 output_invalid (*l
));
3839 if (token_start
== l
)
3841 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3842 as_bad (_("expecting prefix; got nothing"));
3844 as_bad (_("expecting mnemonic; got nothing"));
3848 /* Look up instruction (or prefix) via hash table. */
3849 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3851 if (*l
!= END_OF_INSN
3852 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3853 && current_templates
3854 && current_templates
->start
->opcode_modifier
.isprefix
)
3856 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3858 as_bad ((flag_code
!= CODE_64BIT
3859 ? _("`%s' is only supported in 64-bit mode")
3860 : _("`%s' is not supported in 64-bit mode")),
3861 current_templates
->start
->name
);
3864 /* If we are in 16-bit mode, do not allow addr16 or data16.
3865 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3866 if ((current_templates
->start
->opcode_modifier
.size16
3867 || current_templates
->start
->opcode_modifier
.size32
)
3868 && flag_code
!= CODE_64BIT
3869 && (current_templates
->start
->opcode_modifier
.size32
3870 ^ (flag_code
== CODE_16BIT
)))
3872 as_bad (_("redundant %s prefix"),
3873 current_templates
->start
->name
);
3876 /* Add prefix, checking for repeated prefixes. */
3877 switch (add_prefix (current_templates
->start
->base_opcode
))
3882 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3883 i
.hle_prefix
= current_templates
->start
->name
;
3884 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3885 i
.bnd_prefix
= current_templates
->start
->name
;
3887 i
.rep_prefix
= current_templates
->start
->name
;
3892 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3899 if (!current_templates
)
3901 /* Check if we should swap operand or force 32bit displacement in
3903 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3905 else if (mnem_p
- 3 == dot_p
3908 i
.disp_encoding
= disp_encoding_8bit
;
3909 else if (mnem_p
- 4 == dot_p
3913 i
.disp_encoding
= disp_encoding_32bit
;
3918 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3921 if (!current_templates
)
3924 /* See if we can get a match by trimming off a suffix. */
3927 case WORD_MNEM_SUFFIX
:
3928 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3929 i
.suffix
= SHORT_MNEM_SUFFIX
;
3931 case BYTE_MNEM_SUFFIX
:
3932 case QWORD_MNEM_SUFFIX
:
3933 i
.suffix
= mnem_p
[-1];
3935 current_templates
= (const templates
*) hash_find (op_hash
,
3938 case SHORT_MNEM_SUFFIX
:
3939 case LONG_MNEM_SUFFIX
:
3942 i
.suffix
= mnem_p
[-1];
3944 current_templates
= (const templates
*) hash_find (op_hash
,
3953 if (intel_float_operand (mnemonic
) == 1)
3954 i
.suffix
= SHORT_MNEM_SUFFIX
;
3956 i
.suffix
= LONG_MNEM_SUFFIX
;
3958 current_templates
= (const templates
*) hash_find (op_hash
,
3963 if (!current_templates
)
3965 as_bad (_("no such instruction: `%s'"), token_start
);
3970 if (current_templates
->start
->opcode_modifier
.jump
3971 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3973 /* Check for a branch hint. We allow ",pt" and ",pn" for
3974 predict taken and predict not taken respectively.
3975 I'm not sure that branch hints actually do anything on loop
3976 and jcxz insns (JumpByte) for current Pentium4 chips. They
3977 may work in the future and it doesn't hurt to accept them
3979 if (l
[0] == ',' && l
[1] == 'p')
3983 if (!add_prefix (DS_PREFIX_OPCODE
))
3987 else if (l
[2] == 'n')
3989 if (!add_prefix (CS_PREFIX_OPCODE
))
3995 /* Any other comma loses. */
3998 as_bad (_("invalid character %s in mnemonic"),
3999 output_invalid (*l
));
4003 /* Check if instruction is supported on specified architecture. */
4005 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4007 supported
|= cpu_flags_match (t
);
4008 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4012 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4014 as_bad (flag_code
== CODE_64BIT
4015 ? _("`%s' is not supported in 64-bit mode")
4016 : _("`%s' is only supported in 64-bit mode"),
4017 current_templates
->start
->name
);
4020 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
4022 as_bad (_("`%s' is not supported on `%s%s'"),
4023 current_templates
->start
->name
,
4024 cpu_arch_name
? cpu_arch_name
: default_arch
,
4025 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4030 if (!cpu_arch_flags
.bitfield
.cpui386
4031 && (flag_code
!= CODE_16BIT
))
4033 as_warn (_("use .code16 to ensure correct addressing mode"));
4040 parse_operands (char *l
, const char *mnemonic
)
4044 /* 1 if operand is pending after ','. */
4045 unsigned int expecting_operand
= 0;
4047 /* Non-zero if operand parens not balanced. */
4048 unsigned int paren_not_balanced
;
4050 while (*l
!= END_OF_INSN
)
4052 /* Skip optional white space before operand. */
4053 if (is_space_char (*l
))
4055 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4057 as_bad (_("invalid character %s before operand %d"),
4058 output_invalid (*l
),
4062 token_start
= l
; /* After white space. */
4063 paren_not_balanced
= 0;
4064 while (paren_not_balanced
|| *l
!= ',')
4066 if (*l
== END_OF_INSN
)
4068 if (paren_not_balanced
)
4071 as_bad (_("unbalanced parenthesis in operand %d."),
4074 as_bad (_("unbalanced brackets in operand %d."),
4079 break; /* we are done */
4081 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4083 as_bad (_("invalid character %s in operand %d"),
4084 output_invalid (*l
),
4091 ++paren_not_balanced
;
4093 --paren_not_balanced
;
4098 ++paren_not_balanced
;
4100 --paren_not_balanced
;
4104 if (l
!= token_start
)
4105 { /* Yes, we've read in another operand. */
4106 unsigned int operand_ok
;
4107 this_operand
= i
.operands
++;
4108 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4109 if (i
.operands
> MAX_OPERANDS
)
4111 as_bad (_("spurious operands; (%d operands/instruction max)"),
4115 /* Now parse operand adding info to 'i' as we go along. */
4116 END_STRING_AND_SAVE (l
);
4120 i386_intel_operand (token_start
,
4121 intel_float_operand (mnemonic
));
4123 operand_ok
= i386_att_operand (token_start
);
4125 RESTORE_END_STRING (l
);
4131 if (expecting_operand
)
4133 expecting_operand_after_comma
:
4134 as_bad (_("expecting operand after ','; got nothing"));
4139 as_bad (_("expecting operand before ','; got nothing"));
4144 /* Now *l must be either ',' or END_OF_INSN. */
4147 if (*++l
== END_OF_INSN
)
4149 /* Just skip it, if it's \n complain. */
4150 goto expecting_operand_after_comma
;
4152 expecting_operand
= 1;
4159 swap_2_operands (int xchg1
, int xchg2
)
4161 union i386_op temp_op
;
4162 i386_operand_type temp_type
;
4163 enum bfd_reloc_code_real temp_reloc
;
4165 temp_type
= i
.types
[xchg2
];
4166 i
.types
[xchg2
] = i
.types
[xchg1
];
4167 i
.types
[xchg1
] = temp_type
;
4168 temp_op
= i
.op
[xchg2
];
4169 i
.op
[xchg2
] = i
.op
[xchg1
];
4170 i
.op
[xchg1
] = temp_op
;
4171 temp_reloc
= i
.reloc
[xchg2
];
4172 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4173 i
.reloc
[xchg1
] = temp_reloc
;
4177 if (i
.mask
->operand
== xchg1
)
4178 i
.mask
->operand
= xchg2
;
4179 else if (i
.mask
->operand
== xchg2
)
4180 i
.mask
->operand
= xchg1
;
4184 if (i
.broadcast
->operand
== xchg1
)
4185 i
.broadcast
->operand
= xchg2
;
4186 else if (i
.broadcast
->operand
== xchg2
)
4187 i
.broadcast
->operand
= xchg1
;
4191 if (i
.rounding
->operand
== xchg1
)
4192 i
.rounding
->operand
= xchg2
;
4193 else if (i
.rounding
->operand
== xchg2
)
4194 i
.rounding
->operand
= xchg1
;
4199 swap_operands (void)
4205 swap_2_operands (1, i
.operands
- 2);
4208 swap_2_operands (0, i
.operands
- 1);
4214 if (i
.mem_operands
== 2)
4216 const seg_entry
*temp_seg
;
4217 temp_seg
= i
.seg
[0];
4218 i
.seg
[0] = i
.seg
[1];
4219 i
.seg
[1] = temp_seg
;
4223 /* Try to ensure constant immediates are represented in the smallest
4228 char guess_suffix
= 0;
4232 guess_suffix
= i
.suffix
;
4233 else if (i
.reg_operands
)
4235 /* Figure out a suffix from the last register operand specified.
4236 We can't do this properly yet, ie. excluding InOutPortReg,
4237 but the following works for instructions with immediates.
4238 In any case, we can't set i.suffix yet. */
4239 for (op
= i
.operands
; --op
>= 0;)
4240 if (i
.types
[op
].bitfield
.reg8
)
4242 guess_suffix
= BYTE_MNEM_SUFFIX
;
4245 else if (i
.types
[op
].bitfield
.reg16
)
4247 guess_suffix
= WORD_MNEM_SUFFIX
;
4250 else if (i
.types
[op
].bitfield
.reg32
)
4252 guess_suffix
= LONG_MNEM_SUFFIX
;
4255 else if (i
.types
[op
].bitfield
.reg64
)
4257 guess_suffix
= QWORD_MNEM_SUFFIX
;
4261 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4262 guess_suffix
= WORD_MNEM_SUFFIX
;
4264 for (op
= i
.operands
; --op
>= 0;)
4265 if (operand_type_check (i
.types
[op
], imm
))
4267 switch (i
.op
[op
].imms
->X_op
)
4270 /* If a suffix is given, this operand may be shortened. */
4271 switch (guess_suffix
)
4273 case LONG_MNEM_SUFFIX
:
4274 i
.types
[op
].bitfield
.imm32
= 1;
4275 i
.types
[op
].bitfield
.imm64
= 1;
4277 case WORD_MNEM_SUFFIX
:
4278 i
.types
[op
].bitfield
.imm16
= 1;
4279 i
.types
[op
].bitfield
.imm32
= 1;
4280 i
.types
[op
].bitfield
.imm32s
= 1;
4281 i
.types
[op
].bitfield
.imm64
= 1;
4283 case BYTE_MNEM_SUFFIX
:
4284 i
.types
[op
].bitfield
.imm8
= 1;
4285 i
.types
[op
].bitfield
.imm8s
= 1;
4286 i
.types
[op
].bitfield
.imm16
= 1;
4287 i
.types
[op
].bitfield
.imm32
= 1;
4288 i
.types
[op
].bitfield
.imm32s
= 1;
4289 i
.types
[op
].bitfield
.imm64
= 1;
4293 /* If this operand is at most 16 bits, convert it
4294 to a signed 16 bit number before trying to see
4295 whether it will fit in an even smaller size.
4296 This allows a 16-bit operand such as $0xffe0 to
4297 be recognised as within Imm8S range. */
4298 if ((i
.types
[op
].bitfield
.imm16
)
4299 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4301 i
.op
[op
].imms
->X_add_number
=
4302 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4305 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4306 if ((i
.types
[op
].bitfield
.imm32
)
4307 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4310 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4311 ^ ((offsetT
) 1 << 31))
4312 - ((offsetT
) 1 << 31));
4316 = operand_type_or (i
.types
[op
],
4317 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4319 /* We must avoid matching of Imm32 templates when 64bit
4320 only immediate is available. */
4321 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4322 i
.types
[op
].bitfield
.imm32
= 0;
4329 /* Symbols and expressions. */
4331 /* Convert symbolic operand to proper sizes for matching, but don't
4332 prevent matching a set of insns that only supports sizes other
4333 than those matching the insn suffix. */
4335 i386_operand_type mask
, allowed
;
4336 const insn_template
*t
;
4338 operand_type_set (&mask
, 0);
4339 operand_type_set (&allowed
, 0);
4341 for (t
= current_templates
->start
;
4342 t
< current_templates
->end
;
4344 allowed
= operand_type_or (allowed
,
4345 t
->operand_types
[op
]);
4346 switch (guess_suffix
)
4348 case QWORD_MNEM_SUFFIX
:
4349 mask
.bitfield
.imm64
= 1;
4350 mask
.bitfield
.imm32s
= 1;
4352 case LONG_MNEM_SUFFIX
:
4353 mask
.bitfield
.imm32
= 1;
4355 case WORD_MNEM_SUFFIX
:
4356 mask
.bitfield
.imm16
= 1;
4358 case BYTE_MNEM_SUFFIX
:
4359 mask
.bitfield
.imm8
= 1;
4364 allowed
= operand_type_and (mask
, allowed
);
4365 if (!operand_type_all_zero (&allowed
))
4366 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4373 /* Try to use the smallest displacement type too. */
4375 optimize_disp (void)
4379 for (op
= i
.operands
; --op
>= 0;)
4380 if (operand_type_check (i
.types
[op
], disp
))
4382 if (i
.op
[op
].disps
->X_op
== O_constant
)
4384 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4386 if (i
.types
[op
].bitfield
.disp16
4387 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4389 /* If this operand is at most 16 bits, convert
4390 to a signed 16 bit number and don't use 64bit
4392 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4393 i
.types
[op
].bitfield
.disp64
= 0;
4396 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4397 if (i
.types
[op
].bitfield
.disp32
4398 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4400 /* If this operand is at most 32 bits, convert
4401 to a signed 32 bit number and don't use 64bit
4403 op_disp
&= (((offsetT
) 2 << 31) - 1);
4404 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4405 i
.types
[op
].bitfield
.disp64
= 0;
4408 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4410 i
.types
[op
].bitfield
.disp8
= 0;
4411 i
.types
[op
].bitfield
.disp16
= 0;
4412 i
.types
[op
].bitfield
.disp32
= 0;
4413 i
.types
[op
].bitfield
.disp32s
= 0;
4414 i
.types
[op
].bitfield
.disp64
= 0;
4418 else if (flag_code
== CODE_64BIT
)
4420 if (fits_in_signed_long (op_disp
))
4422 i
.types
[op
].bitfield
.disp64
= 0;
4423 i
.types
[op
].bitfield
.disp32s
= 1;
4425 if (i
.prefix
[ADDR_PREFIX
]
4426 && fits_in_unsigned_long (op_disp
))
4427 i
.types
[op
].bitfield
.disp32
= 1;
4429 if ((i
.types
[op
].bitfield
.disp32
4430 || i
.types
[op
].bitfield
.disp32s
4431 || i
.types
[op
].bitfield
.disp16
)
4432 && fits_in_signed_byte (op_disp
))
4433 i
.types
[op
].bitfield
.disp8
= 1;
4435 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4436 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4438 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4439 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4440 i
.types
[op
].bitfield
.disp8
= 0;
4441 i
.types
[op
].bitfield
.disp16
= 0;
4442 i
.types
[op
].bitfield
.disp32
= 0;
4443 i
.types
[op
].bitfield
.disp32s
= 0;
4444 i
.types
[op
].bitfield
.disp64
= 0;
4447 /* We only support 64bit displacement on constants. */
4448 i
.types
[op
].bitfield
.disp64
= 0;
4452 /* Check if operands are valid for the instruction. */
4455 check_VecOperands (const insn_template
*t
)
4459 /* Without VSIB byte, we can't have a vector register for index. */
4460 if (!t
->opcode_modifier
.vecsib
4462 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4463 || i
.index_reg
->reg_type
.bitfield
.regymm
4464 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4466 i
.error
= unsupported_vector_index_register
;
4470 /* Check if default mask is allowed. */
4471 if (t
->opcode_modifier
.nodefmask
4472 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4474 i
.error
= no_default_mask
;
4478 /* For VSIB byte, we need a vector register for index, and all vector
4479 registers must be distinct. */
4480 if (t
->opcode_modifier
.vecsib
)
4483 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4484 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4485 || (t
->opcode_modifier
.vecsib
== VecSIB256
4486 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4487 || (t
->opcode_modifier
.vecsib
== VecSIB512
4488 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4490 i
.error
= invalid_vsib_address
;
4494 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4495 if (i
.reg_operands
== 2 && !i
.mask
)
4497 gas_assert (i
.types
[0].bitfield
.regxmm
4498 || i
.types
[0].bitfield
.regymm
);
4499 gas_assert (i
.types
[2].bitfield
.regxmm
4500 || i
.types
[2].bitfield
.regymm
);
4501 if (operand_check
== check_none
)
4503 if (register_number (i
.op
[0].regs
)
4504 != register_number (i
.index_reg
)
4505 && register_number (i
.op
[2].regs
)
4506 != register_number (i
.index_reg
)
4507 && register_number (i
.op
[0].regs
)
4508 != register_number (i
.op
[2].regs
))
4510 if (operand_check
== check_error
)
4512 i
.error
= invalid_vector_register_set
;
4515 as_warn (_("mask, index, and destination registers should be distinct"));
4517 else if (i
.reg_operands
== 1 && i
.mask
)
4519 if ((i
.types
[1].bitfield
.regymm
4520 || i
.types
[1].bitfield
.regzmm
)
4521 && (register_number (i
.op
[1].regs
)
4522 == register_number (i
.index_reg
)))
4524 if (operand_check
== check_error
)
4526 i
.error
= invalid_vector_register_set
;
4529 if (operand_check
!= check_none
)
4530 as_warn (_("index and destination registers should be distinct"));
4535 /* Check if broadcast is supported by the instruction and is applied
4536 to the memory operand. */
4539 int broadcasted_opnd_size
;
4541 /* Check if specified broadcast is supported in this instruction,
4542 and it's applied to memory operand of DWORD or QWORD type,
4543 depending on VecESize. */
4544 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4545 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4546 || (t
->opcode_modifier
.vecesize
== 0
4547 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4548 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4549 || (t
->opcode_modifier
.vecesize
== 1
4550 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4551 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4554 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4555 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4556 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4557 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4558 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4559 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4560 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4561 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4562 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4566 if ((broadcasted_opnd_size
== 256
4567 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4568 || (broadcasted_opnd_size
== 512
4569 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4572 i
.error
= unsupported_broadcast
;
4576 /* If broadcast is supported in this instruction, we need to check if
4577 operand of one-element size isn't specified without broadcast. */
4578 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4580 /* Find memory operand. */
4581 for (op
= 0; op
< i
.operands
; op
++)
4582 if (operand_type_check (i
.types
[op
], anymem
))
4584 gas_assert (op
< i
.operands
);
4585 /* Check size of the memory operand. */
4586 if ((t
->opcode_modifier
.vecesize
== 0
4587 && i
.types
[op
].bitfield
.dword
)
4588 || (t
->opcode_modifier
.vecesize
== 1
4589 && i
.types
[op
].bitfield
.qword
))
4591 i
.error
= broadcast_needed
;
4596 /* Check if requested masking is supported. */
4598 && (!t
->opcode_modifier
.masking
4600 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4602 i
.error
= unsupported_masking
;
4606 /* Check if masking is applied to dest operand. */
4607 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4609 i
.error
= mask_not_on_destination
;
4616 if ((i
.rounding
->type
!= saeonly
4617 && !t
->opcode_modifier
.staticrounding
)
4618 || (i
.rounding
->type
== saeonly
4619 && (t
->opcode_modifier
.staticrounding
4620 || !t
->opcode_modifier
.sae
)))
4622 i
.error
= unsupported_rc_sae
;
4625 /* If the instruction has several immediate operands and one of
4626 them is rounding, the rounding operand should be the last
4627 immediate operand. */
4628 if (i
.imm_operands
> 1
4629 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4631 i
.error
= rc_sae_operand_not_last_imm
;
4636 /* Check vector Disp8 operand. */
4637 if (t
->opcode_modifier
.disp8memshift
)
4640 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4642 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4644 for (op
= 0; op
< i
.operands
; op
++)
4645 if (operand_type_check (i
.types
[op
], disp
)
4646 && i
.op
[op
].disps
->X_op
== O_constant
)
4648 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4650 = (i
.disp_encoding
!= disp_encoding_32bit
4651 && fits_in_vec_disp8 (value
));
4652 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4655 i
.types
[op
].bitfield
.vec_disp8
= 1;
4658 /* Vector insn can only have Vec_Disp8/Disp32 in
4659 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4661 i
.types
[op
].bitfield
.disp8
= 0;
4662 if (flag_code
!= CODE_16BIT
)
4663 i
.types
[op
].bitfield
.disp16
= 0;
4666 else if (flag_code
!= CODE_16BIT
)
4668 /* One form of this instruction supports vector Disp8.
4669 Try vector Disp8 if we need to use Disp32. */
4670 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4672 i
.error
= try_vector_disp8
;
4684 /* Check if operands are valid for the instruction. Update VEX
4688 VEX_check_operands (const insn_template
*t
)
4690 /* VREX is only valid with EVEX prefix. */
4691 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4693 i
.error
= invalid_register_operand
;
4697 if (!t
->opcode_modifier
.vex
)
4700 /* Only check VEX_Imm4, which must be the first operand. */
4701 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4703 if (i
.op
[0].imms
->X_op
!= O_constant
4704 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4710 /* Turn off Imm8 so that update_imm won't complain. */
4711 i
.types
[0] = vec_imm4
;
4717 static const insn_template
*
4718 match_template (char mnem_suffix
)
4720 /* Points to template once we've found it. */
4721 const insn_template
*t
;
4722 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4723 i386_operand_type overlap4
;
4724 unsigned int found_reverse_match
;
4725 i386_opcode_modifier suffix_check
, mnemsuf_check
;
4726 i386_operand_type operand_types
[MAX_OPERANDS
];
4727 int addr_prefix_disp
;
4729 unsigned int found_cpu_match
;
4730 unsigned int check_register
;
4731 enum i386_error specific_error
= 0;
4733 #if MAX_OPERANDS != 5
4734 # error "MAX_OPERANDS must be 5."
4737 found_reverse_match
= 0;
4738 addr_prefix_disp
= -1;
4740 memset (&suffix_check
, 0, sizeof (suffix_check
));
4741 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4742 suffix_check
.no_bsuf
= 1;
4743 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4744 suffix_check
.no_wsuf
= 1;
4745 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4746 suffix_check
.no_ssuf
= 1;
4747 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4748 suffix_check
.no_lsuf
= 1;
4749 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4750 suffix_check
.no_qsuf
= 1;
4751 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4752 suffix_check
.no_ldsuf
= 1;
4754 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
4757 switch (mnem_suffix
)
4759 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
4760 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
4761 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
4762 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
4763 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
4767 /* Must have right number of operands. */
4768 i
.error
= number_of_operands_mismatch
;
4770 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4772 addr_prefix_disp
= -1;
4774 if (i
.operands
!= t
->operands
)
4777 /* Check processor support. */
4778 i
.error
= unsupported
;
4779 found_cpu_match
= (cpu_flags_match (t
)
4780 == CPU_FLAGS_PERFECT_MATCH
);
4781 if (!found_cpu_match
)
4784 /* Check old gcc support. */
4785 i
.error
= old_gcc_only
;
4786 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4789 /* Check AT&T mnemonic. */
4790 i
.error
= unsupported_with_intel_mnemonic
;
4791 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4794 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
4795 i
.error
= unsupported_syntax
;
4796 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4797 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
4798 || (intel64
&& t
->opcode_modifier
.amd64
)
4799 || (!intel64
&& t
->opcode_modifier
.intel64
))
4802 /* Check the suffix, except for some instructions in intel mode. */
4803 i
.error
= invalid_instruction_suffix
;
4804 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4805 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4806 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4807 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4808 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4809 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4810 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4812 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4813 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
4814 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
4815 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
4816 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
4817 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
4818 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
4821 if (!operand_size_match (t
))
4824 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4825 operand_types
[j
] = t
->operand_types
[j
];
4827 /* In general, don't allow 64-bit operands in 32-bit mode. */
4828 if (i
.suffix
== QWORD_MNEM_SUFFIX
4829 && flag_code
!= CODE_64BIT
4831 ? (!t
->opcode_modifier
.ignoresize
4832 && !intel_float_operand (t
->name
))
4833 : intel_float_operand (t
->name
) != 2)
4834 && ((!operand_types
[0].bitfield
.regmmx
4835 && !operand_types
[0].bitfield
.regxmm
4836 && !operand_types
[0].bitfield
.regymm
4837 && !operand_types
[0].bitfield
.regzmm
)
4838 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4839 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4840 && operand_types
[t
->operands
> 1].bitfield
.regymm
4841 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4842 && (t
->base_opcode
!= 0x0fc7
4843 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4846 /* In general, don't allow 32-bit operands on pre-386. */
4847 else if (i
.suffix
== LONG_MNEM_SUFFIX
4848 && !cpu_arch_flags
.bitfield
.cpui386
4850 ? (!t
->opcode_modifier
.ignoresize
4851 && !intel_float_operand (t
->name
))
4852 : intel_float_operand (t
->name
) != 2)
4853 && ((!operand_types
[0].bitfield
.regmmx
4854 && !operand_types
[0].bitfield
.regxmm
)
4855 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4856 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4859 /* Do not verify operands when there are none. */
4863 /* We've found a match; break out of loop. */
4867 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4868 into Disp32/Disp16/Disp32 operand. */
4869 if (i
.prefix
[ADDR_PREFIX
] != 0)
4871 /* There should be only one Disp operand. */
4875 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4877 if (operand_types
[j
].bitfield
.disp16
)
4879 addr_prefix_disp
= j
;
4880 operand_types
[j
].bitfield
.disp32
= 1;
4881 operand_types
[j
].bitfield
.disp16
= 0;
4887 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4889 if (operand_types
[j
].bitfield
.disp32
)
4891 addr_prefix_disp
= j
;
4892 operand_types
[j
].bitfield
.disp32
= 0;
4893 operand_types
[j
].bitfield
.disp16
= 1;
4899 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4901 if (operand_types
[j
].bitfield
.disp64
)
4903 addr_prefix_disp
= j
;
4904 operand_types
[j
].bitfield
.disp64
= 0;
4905 operand_types
[j
].bitfield
.disp32
= 1;
4913 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4914 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
4917 /* We check register size if needed. */
4918 check_register
= t
->opcode_modifier
.checkregsize
;
4919 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4920 switch (t
->operands
)
4923 if (!operand_type_match (overlap0
, i
.types
[0]))
4927 /* xchg %eax, %eax is a special case. It is an aliase for nop
4928 only in 32bit mode and we can use opcode 0x90. In 64bit
4929 mode, we can't use 0x90 for xchg %eax, %eax since it should
4930 zero-extend %eax to %rax. */
4931 if (flag_code
== CODE_64BIT
4932 && t
->base_opcode
== 0x90
4933 && operand_type_equal (&i
.types
[0], &acc32
)
4934 && operand_type_equal (&i
.types
[1], &acc32
))
4938 /* If we swap operand in encoding, we either match
4939 the next one or reverse direction of operands. */
4940 if (t
->opcode_modifier
.s
)
4942 else if (t
->opcode_modifier
.d
)
4947 /* If we swap operand in encoding, we match the next one. */
4948 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4952 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4953 if (!operand_type_match (overlap0
, i
.types
[0])
4954 || !operand_type_match (overlap1
, i
.types
[1])
4956 && !operand_type_register_match (overlap0
, i
.types
[0],
4958 overlap1
, i
.types
[1],
4961 /* Check if other direction is valid ... */
4962 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4966 /* Try reversing direction of operands. */
4967 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4968 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4969 if (!operand_type_match (overlap0
, i
.types
[0])
4970 || !operand_type_match (overlap1
, i
.types
[1])
4972 && !operand_type_register_match (overlap0
,
4979 /* Does not match either direction. */
4982 /* found_reverse_match holds which of D or FloatDR
4984 if (t
->opcode_modifier
.d
)
4985 found_reverse_match
= Opcode_D
;
4986 else if (t
->opcode_modifier
.floatd
)
4987 found_reverse_match
= Opcode_FloatD
;
4989 found_reverse_match
= 0;
4990 if (t
->opcode_modifier
.floatr
)
4991 found_reverse_match
|= Opcode_FloatR
;
4995 /* Found a forward 2 operand match here. */
4996 switch (t
->operands
)
4999 overlap4
= operand_type_and (i
.types
[4],
5002 overlap3
= operand_type_and (i
.types
[3],
5005 overlap2
= operand_type_and (i
.types
[2],
5010 switch (t
->operands
)
5013 if (!operand_type_match (overlap4
, i
.types
[4])
5014 || !operand_type_register_match (overlap3
,
5022 if (!operand_type_match (overlap3
, i
.types
[3])
5024 && !operand_type_register_match (overlap2
,
5032 /* Here we make use of the fact that there are no
5033 reverse match 3 operand instructions, and all 3
5034 operand instructions only need to be checked for
5035 register consistency between operands 2 and 3. */
5036 if (!operand_type_match (overlap2
, i
.types
[2])
5038 && !operand_type_register_match (overlap1
,
5048 /* Found either forward/reverse 2, 3 or 4 operand match here:
5049 slip through to break. */
5051 if (!found_cpu_match
)
5053 found_reverse_match
= 0;
5057 /* Check if vector and VEX operands are valid. */
5058 if (check_VecOperands (t
) || VEX_check_operands (t
))
5060 specific_error
= i
.error
;
5064 /* We've found a match; break out of loop. */
5068 if (t
== current_templates
->end
)
5070 /* We found no match. */
5071 const char *err_msg
;
5072 switch (specific_error
? specific_error
: i
.error
)
5076 case operand_size_mismatch
:
5077 err_msg
= _("operand size mismatch");
5079 case operand_type_mismatch
:
5080 err_msg
= _("operand type mismatch");
5082 case register_type_mismatch
:
5083 err_msg
= _("register type mismatch");
5085 case number_of_operands_mismatch
:
5086 err_msg
= _("number of operands mismatch");
5088 case invalid_instruction_suffix
:
5089 err_msg
= _("invalid instruction suffix");
5092 err_msg
= _("constant doesn't fit in 4 bits");
5095 err_msg
= _("only supported with old gcc");
5097 case unsupported_with_intel_mnemonic
:
5098 err_msg
= _("unsupported with Intel mnemonic");
5100 case unsupported_syntax
:
5101 err_msg
= _("unsupported syntax");
5104 as_bad (_("unsupported instruction `%s'"),
5105 current_templates
->start
->name
);
5107 case invalid_vsib_address
:
5108 err_msg
= _("invalid VSIB address");
5110 case invalid_vector_register_set
:
5111 err_msg
= _("mask, index, and destination registers must be distinct");
5113 case unsupported_vector_index_register
:
5114 err_msg
= _("unsupported vector index register");
5116 case unsupported_broadcast
:
5117 err_msg
= _("unsupported broadcast");
5119 case broadcast_not_on_src_operand
:
5120 err_msg
= _("broadcast not on source memory operand");
5122 case broadcast_needed
:
5123 err_msg
= _("broadcast is needed for operand of such type");
5125 case unsupported_masking
:
5126 err_msg
= _("unsupported masking");
5128 case mask_not_on_destination
:
5129 err_msg
= _("mask not on destination operand");
5131 case no_default_mask
:
5132 err_msg
= _("default mask isn't allowed");
5134 case unsupported_rc_sae
:
5135 err_msg
= _("unsupported static rounding/sae");
5137 case rc_sae_operand_not_last_imm
:
5139 err_msg
= _("RC/SAE operand must precede immediate operands");
5141 err_msg
= _("RC/SAE operand must follow immediate operands");
5143 case invalid_register_operand
:
5144 err_msg
= _("invalid register operand");
5147 as_bad (_("%s for `%s'"), err_msg
,
5148 current_templates
->start
->name
);
5152 if (!quiet_warnings
)
5155 && (i
.types
[0].bitfield
.jumpabsolute
5156 != operand_types
[0].bitfield
.jumpabsolute
))
5158 as_warn (_("indirect %s without `*'"), t
->name
);
5161 if (t
->opcode_modifier
.isprefix
5162 && t
->opcode_modifier
.ignoresize
)
5164 /* Warn them that a data or address size prefix doesn't
5165 affect assembly of the next line of code. */
5166 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5170 /* Copy the template we found. */
5173 if (addr_prefix_disp
!= -1)
5174 i
.tm
.operand_types
[addr_prefix_disp
]
5175 = operand_types
[addr_prefix_disp
];
5177 if (found_reverse_match
)
5179 /* If we found a reverse match we must alter the opcode
5180 direction bit. found_reverse_match holds bits to change
5181 (different for int & float insns). */
5183 i
.tm
.base_opcode
^= found_reverse_match
;
5185 i
.tm
.operand_types
[0] = operand_types
[1];
5186 i
.tm
.operand_types
[1] = operand_types
[0];
5195 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5196 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5198 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5200 as_bad (_("`%s' operand %d must use `%ses' segment"),
5206 /* There's only ever one segment override allowed per instruction.
5207 This instruction possibly has a legal segment override on the
5208 second operand, so copy the segment to where non-string
5209 instructions store it, allowing common code. */
5210 i
.seg
[0] = i
.seg
[1];
5212 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5214 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5216 as_bad (_("`%s' operand %d must use `%ses' segment"),
5227 process_suffix (void)
5229 /* If matched instruction specifies an explicit instruction mnemonic
5231 if (i
.tm
.opcode_modifier
.size16
)
5232 i
.suffix
= WORD_MNEM_SUFFIX
;
5233 else if (i
.tm
.opcode_modifier
.size32
)
5234 i
.suffix
= LONG_MNEM_SUFFIX
;
5235 else if (i
.tm
.opcode_modifier
.size64
)
5236 i
.suffix
= QWORD_MNEM_SUFFIX
;
5237 else if (i
.reg_operands
)
5239 /* If there's no instruction mnemonic suffix we try to invent one
5240 based on register operands. */
5243 /* We take i.suffix from the last register operand specified,
5244 Destination register type is more significant than source
5245 register type. crc32 in SSE4.2 prefers source register
5247 if (i
.tm
.base_opcode
== 0xf20f38f1)
5249 if (i
.types
[0].bitfield
.reg16
)
5250 i
.suffix
= WORD_MNEM_SUFFIX
;
5251 else if (i
.types
[0].bitfield
.reg32
)
5252 i
.suffix
= LONG_MNEM_SUFFIX
;
5253 else if (i
.types
[0].bitfield
.reg64
)
5254 i
.suffix
= QWORD_MNEM_SUFFIX
;
5256 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5258 if (i
.types
[0].bitfield
.reg8
)
5259 i
.suffix
= BYTE_MNEM_SUFFIX
;
5266 if (i
.tm
.base_opcode
== 0xf20f38f1
5267 || i
.tm
.base_opcode
== 0xf20f38f0)
5269 /* We have to know the operand size for crc32. */
5270 as_bad (_("ambiguous memory operand size for `%s`"),
5275 for (op
= i
.operands
; --op
>= 0;)
5276 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5278 if (i
.types
[op
].bitfield
.reg8
)
5280 i
.suffix
= BYTE_MNEM_SUFFIX
;
5283 else if (i
.types
[op
].bitfield
.reg16
)
5285 i
.suffix
= WORD_MNEM_SUFFIX
;
5288 else if (i
.types
[op
].bitfield
.reg32
)
5290 i
.suffix
= LONG_MNEM_SUFFIX
;
5293 else if (i
.types
[op
].bitfield
.reg64
)
5295 i
.suffix
= QWORD_MNEM_SUFFIX
;
5301 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5304 && i
.tm
.opcode_modifier
.ignoresize
5305 && i
.tm
.opcode_modifier
.no_bsuf
)
5307 else if (!check_byte_reg ())
5310 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5313 && i
.tm
.opcode_modifier
.ignoresize
5314 && i
.tm
.opcode_modifier
.no_lsuf
)
5316 else if (!check_long_reg ())
5319 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5322 && i
.tm
.opcode_modifier
.ignoresize
5323 && i
.tm
.opcode_modifier
.no_qsuf
)
5325 else if (!check_qword_reg ())
5328 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5331 && i
.tm
.opcode_modifier
.ignoresize
5332 && i
.tm
.opcode_modifier
.no_wsuf
)
5334 else if (!check_word_reg ())
5337 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5338 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5339 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5341 /* Skip if the instruction has x/y/z suffix. match_template
5342 should check if it is a valid suffix. */
5344 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5345 /* Do nothing if the instruction is going to ignore the prefix. */
5350 else if (i
.tm
.opcode_modifier
.defaultsize
5352 /* exclude fldenv/frstor/fsave/fstenv */
5353 && i
.tm
.opcode_modifier
.no_ssuf
)
5355 i
.suffix
= stackop_size
;
5357 else if (intel_syntax
5359 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5360 || i
.tm
.opcode_modifier
.jumpbyte
5361 || i
.tm
.opcode_modifier
.jumpintersegment
5362 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5363 && i
.tm
.extension_opcode
<= 3)))
5368 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5370 i
.suffix
= QWORD_MNEM_SUFFIX
;
5374 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5375 i
.suffix
= LONG_MNEM_SUFFIX
;
5378 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5379 i
.suffix
= WORD_MNEM_SUFFIX
;
5388 if (i
.tm
.opcode_modifier
.w
)
5390 as_bad (_("no instruction mnemonic suffix given and "
5391 "no register operands; can't size instruction"));
5397 unsigned int suffixes
;
5399 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5400 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5402 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5404 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5406 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5408 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5411 /* There are more than suffix matches. */
5412 if (i
.tm
.opcode_modifier
.w
5413 || ((suffixes
& (suffixes
- 1))
5414 && !i
.tm
.opcode_modifier
.defaultsize
5415 && !i
.tm
.opcode_modifier
.ignoresize
))
5417 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5423 /* Change the opcode based on the operand size given by i.suffix;
5424 We don't need to change things for byte insns. */
5427 && i
.suffix
!= BYTE_MNEM_SUFFIX
5428 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5429 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5430 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5432 /* It's not a byte, select word/dword operation. */
5433 if (i
.tm
.opcode_modifier
.w
)
5435 if (i
.tm
.opcode_modifier
.shortform
)
5436 i
.tm
.base_opcode
|= 8;
5438 i
.tm
.base_opcode
|= 1;
5441 /* Now select between word & dword operations via the operand
5442 size prefix, except for instructions that will ignore this
5444 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5446 /* The address size override prefix changes the size of the
5448 if ((flag_code
== CODE_32BIT
5449 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5450 || (flag_code
!= CODE_32BIT
5451 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5452 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5455 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5456 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5457 && !i
.tm
.opcode_modifier
.ignoresize
5458 && !i
.tm
.opcode_modifier
.floatmf
5459 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5460 || (flag_code
== CODE_64BIT
5461 && i
.tm
.opcode_modifier
.jumpbyte
)))
5463 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5465 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5466 prefix
= ADDR_PREFIX_OPCODE
;
5468 if (!add_prefix (prefix
))
5472 /* Set mode64 for an operand. */
5473 if (i
.suffix
== QWORD_MNEM_SUFFIX
5474 && flag_code
== CODE_64BIT
5475 && !i
.tm
.opcode_modifier
.norex64
)
5477 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5478 need rex64. cmpxchg8b is also a special case. */
5479 if (! (i
.operands
== 2
5480 && i
.tm
.base_opcode
== 0x90
5481 && i
.tm
.extension_opcode
== None
5482 && operand_type_equal (&i
.types
[0], &acc64
)
5483 && operand_type_equal (&i
.types
[1], &acc64
))
5484 && ! (i
.operands
== 1
5485 && i
.tm
.base_opcode
== 0xfc7
5486 && i
.tm
.extension_opcode
== 1
5487 && !operand_type_check (i
.types
[0], reg
)
5488 && operand_type_check (i
.types
[0], anymem
)))
5492 /* Size floating point instruction. */
5493 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5494 if (i
.tm
.opcode_modifier
.floatmf
)
5495 i
.tm
.base_opcode
^= 4;
5502 check_byte_reg (void)
5506 for (op
= i
.operands
; --op
>= 0;)
5508 /* If this is an eight bit register, it's OK. If it's the 16 or
5509 32 bit version of an eight bit register, we will just use the
5510 low portion, and that's OK too. */
5511 if (i
.types
[op
].bitfield
.reg8
)
5514 /* I/O port address operands are OK too. */
5515 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5518 /* crc32 doesn't generate this warning. */
5519 if (i
.tm
.base_opcode
== 0xf20f38f0)
5522 if ((i
.types
[op
].bitfield
.reg16
5523 || i
.types
[op
].bitfield
.reg32
5524 || i
.types
[op
].bitfield
.reg64
)
5525 && i
.op
[op
].regs
->reg_num
< 4
5526 /* Prohibit these changes in 64bit mode, since the lowering
5527 would be more complicated. */
5528 && flag_code
!= CODE_64BIT
)
5530 #if REGISTER_WARNINGS
5531 if (!quiet_warnings
)
5532 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5534 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5535 ? REGNAM_AL
- REGNAM_AX
5536 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5538 i
.op
[op
].regs
->reg_name
,
5543 /* Any other register is bad. */
5544 if (i
.types
[op
].bitfield
.reg16
5545 || i
.types
[op
].bitfield
.reg32
5546 || i
.types
[op
].bitfield
.reg64
5547 || i
.types
[op
].bitfield
.regmmx
5548 || i
.types
[op
].bitfield
.regxmm
5549 || i
.types
[op
].bitfield
.regymm
5550 || i
.types
[op
].bitfield
.regzmm
5551 || i
.types
[op
].bitfield
.sreg2
5552 || i
.types
[op
].bitfield
.sreg3
5553 || i
.types
[op
].bitfield
.control
5554 || i
.types
[op
].bitfield
.debug
5555 || i
.types
[op
].bitfield
.test
5556 || i
.types
[op
].bitfield
.floatreg
5557 || i
.types
[op
].bitfield
.floatacc
)
5559 as_bad (_("`%s%s' not allowed with `%s%c'"),
5561 i
.op
[op
].regs
->reg_name
,
5571 check_long_reg (void)
5575 for (op
= i
.operands
; --op
>= 0;)
5576 /* Reject eight bit registers, except where the template requires
5577 them. (eg. movzb) */
5578 if (i
.types
[op
].bitfield
.reg8
5579 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5580 || i
.tm
.operand_types
[op
].bitfield
.reg32
5581 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5583 as_bad (_("`%s%s' not allowed with `%s%c'"),
5585 i
.op
[op
].regs
->reg_name
,
5590 /* Warn if the e prefix on a general reg is missing. */
5591 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5592 && i
.types
[op
].bitfield
.reg16
5593 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5594 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5596 /* Prohibit these changes in the 64bit mode, since the
5597 lowering is more complicated. */
5598 if (flag_code
== CODE_64BIT
)
5600 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5601 register_prefix
, i
.op
[op
].regs
->reg_name
,
5605 #if REGISTER_WARNINGS
5606 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5608 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5609 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5612 /* Warn if the r prefix on a general reg is present. */
5613 else if (i
.types
[op
].bitfield
.reg64
5614 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5615 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5618 && i
.tm
.opcode_modifier
.toqword
5619 && !i
.types
[0].bitfield
.regxmm
)
5621 /* Convert to QWORD. We want REX byte. */
5622 i
.suffix
= QWORD_MNEM_SUFFIX
;
5626 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5627 register_prefix
, i
.op
[op
].regs
->reg_name
,
5636 check_qword_reg (void)
5640 for (op
= i
.operands
; --op
>= 0; )
5641 /* Reject eight bit registers, except where the template requires
5642 them. (eg. movzb) */
5643 if (i
.types
[op
].bitfield
.reg8
5644 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5645 || i
.tm
.operand_types
[op
].bitfield
.reg32
5646 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5648 as_bad (_("`%s%s' not allowed with `%s%c'"),
5650 i
.op
[op
].regs
->reg_name
,
5655 /* Warn if the r prefix on a general reg is missing. */
5656 else if ((i
.types
[op
].bitfield
.reg16
5657 || i
.types
[op
].bitfield
.reg32
)
5658 && (i
.tm
.operand_types
[op
].bitfield
.reg64
5659 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5661 /* Prohibit these changes in the 64bit mode, since the
5662 lowering is more complicated. */
5664 && i
.tm
.opcode_modifier
.todword
5665 && !i
.types
[0].bitfield
.regxmm
)
5667 /* Convert to DWORD. We don't want REX byte. */
5668 i
.suffix
= LONG_MNEM_SUFFIX
;
5672 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5673 register_prefix
, i
.op
[op
].regs
->reg_name
,
5682 check_word_reg (void)
5685 for (op
= i
.operands
; --op
>= 0;)
5686 /* Reject eight bit registers, except where the template requires
5687 them. (eg. movzb) */
5688 if (i
.types
[op
].bitfield
.reg8
5689 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5690 || i
.tm
.operand_types
[op
].bitfield
.reg32
5691 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5693 as_bad (_("`%s%s' not allowed with `%s%c'"),
5695 i
.op
[op
].regs
->reg_name
,
5700 /* Warn if the e or r prefix on a general reg is present. */
5701 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5702 && (i
.types
[op
].bitfield
.reg32
5703 || i
.types
[op
].bitfield
.reg64
)
5704 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5705 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5707 /* Prohibit these changes in the 64bit mode, since the
5708 lowering is more complicated. */
5709 if (flag_code
== CODE_64BIT
)
5711 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5712 register_prefix
, i
.op
[op
].regs
->reg_name
,
5716 #if REGISTER_WARNINGS
5717 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5719 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5720 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5727 update_imm (unsigned int j
)
5729 i386_operand_type overlap
= i
.types
[j
];
5730 if ((overlap
.bitfield
.imm8
5731 || overlap
.bitfield
.imm8s
5732 || overlap
.bitfield
.imm16
5733 || overlap
.bitfield
.imm32
5734 || overlap
.bitfield
.imm32s
5735 || overlap
.bitfield
.imm64
)
5736 && !operand_type_equal (&overlap
, &imm8
)
5737 && !operand_type_equal (&overlap
, &imm8s
)
5738 && !operand_type_equal (&overlap
, &imm16
)
5739 && !operand_type_equal (&overlap
, &imm32
)
5740 && !operand_type_equal (&overlap
, &imm32s
)
5741 && !operand_type_equal (&overlap
, &imm64
))
5745 i386_operand_type temp
;
5747 operand_type_set (&temp
, 0);
5748 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5750 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5751 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5753 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5754 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5755 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5757 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5758 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5761 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5764 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5765 || operand_type_equal (&overlap
, &imm16_32
)
5766 || operand_type_equal (&overlap
, &imm16_32s
))
5768 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5773 if (!operand_type_equal (&overlap
, &imm8
)
5774 && !operand_type_equal (&overlap
, &imm8s
)
5775 && !operand_type_equal (&overlap
, &imm16
)
5776 && !operand_type_equal (&overlap
, &imm32
)
5777 && !operand_type_equal (&overlap
, &imm32s
)
5778 && !operand_type_equal (&overlap
, &imm64
))
5780 as_bad (_("no instruction mnemonic suffix given; "
5781 "can't determine immediate size"));
5785 i
.types
[j
] = overlap
;
5795 /* Update the first 2 immediate operands. */
5796 n
= i
.operands
> 2 ? 2 : i
.operands
;
5799 for (j
= 0; j
< n
; j
++)
5800 if (update_imm (j
) == 0)
5803 /* The 3rd operand can't be immediate operand. */
5804 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5811 bad_implicit_operand (int xmm
)
5813 const char *ireg
= xmm
? "xmm0" : "ymm0";
5816 as_bad (_("the last operand of `%s' must be `%s%s'"),
5817 i
.tm
.name
, register_prefix
, ireg
);
5819 as_bad (_("the first operand of `%s' must be `%s%s'"),
5820 i
.tm
.name
, register_prefix
, ireg
);
5825 process_operands (void)
5827 /* Default segment register this instruction will use for memory
5828 accesses. 0 means unknown. This is only for optimizing out
5829 unnecessary segment overrides. */
5830 const seg_entry
*default_seg
= 0;
5832 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5834 unsigned int dupl
= i
.operands
;
5835 unsigned int dest
= dupl
- 1;
5838 /* The destination must be an xmm register. */
5839 gas_assert (i
.reg_operands
5840 && MAX_OPERANDS
> dupl
5841 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5843 if (i
.tm
.opcode_modifier
.firstxmm0
)
5845 /* The first operand is implicit and must be xmm0. */
5846 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5847 if (register_number (i
.op
[0].regs
) != 0)
5848 return bad_implicit_operand (1);
5850 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5852 /* Keep xmm0 for instructions with VEX prefix and 3
5858 /* We remove the first xmm0 and keep the number of
5859 operands unchanged, which in fact duplicates the
5861 for (j
= 1; j
< i
.operands
; j
++)
5863 i
.op
[j
- 1] = i
.op
[j
];
5864 i
.types
[j
- 1] = i
.types
[j
];
5865 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5869 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5871 gas_assert ((MAX_OPERANDS
- 1) > dupl
5872 && (i
.tm
.opcode_modifier
.vexsources
5875 /* Add the implicit xmm0 for instructions with VEX prefix
5877 for (j
= i
.operands
; j
> 0; j
--)
5879 i
.op
[j
] = i
.op
[j
- 1];
5880 i
.types
[j
] = i
.types
[j
- 1];
5881 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5884 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5885 i
.types
[0] = regxmm
;
5886 i
.tm
.operand_types
[0] = regxmm
;
5889 i
.reg_operands
+= 2;
5894 i
.op
[dupl
] = i
.op
[dest
];
5895 i
.types
[dupl
] = i
.types
[dest
];
5896 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5905 i
.op
[dupl
] = i
.op
[dest
];
5906 i
.types
[dupl
] = i
.types
[dest
];
5907 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5910 if (i
.tm
.opcode_modifier
.immext
)
5913 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5917 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5918 gas_assert (i
.reg_operands
5919 && (operand_type_equal (&i
.types
[0], ®xmm
)
5920 || operand_type_equal (&i
.types
[0], ®ymm
)
5921 || operand_type_equal (&i
.types
[0], ®zmm
)));
5922 if (register_number (i
.op
[0].regs
) != 0)
5923 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5925 for (j
= 1; j
< i
.operands
; j
++)
5927 i
.op
[j
- 1] = i
.op
[j
];
5928 i
.types
[j
- 1] = i
.types
[j
];
5930 /* We need to adjust fields in i.tm since they are used by
5931 build_modrm_byte. */
5932 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5939 else if (i
.tm
.opcode_modifier
.regkludge
)
5941 /* The imul $imm, %reg instruction is converted into
5942 imul $imm, %reg, %reg, and the clr %reg instruction
5943 is converted into xor %reg, %reg. */
5945 unsigned int first_reg_op
;
5947 if (operand_type_check (i
.types
[0], reg
))
5951 /* Pretend we saw the extra register operand. */
5952 gas_assert (i
.reg_operands
== 1
5953 && i
.op
[first_reg_op
+ 1].regs
== 0);
5954 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5955 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5960 if (i
.tm
.opcode_modifier
.shortform
)
5962 if (i
.types
[0].bitfield
.sreg2
5963 || i
.types
[0].bitfield
.sreg3
)
5965 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5966 && i
.op
[0].regs
->reg_num
== 1)
5968 as_bad (_("you can't `pop %scs'"), register_prefix
);
5971 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5972 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5977 /* The register or float register operand is in operand
5981 if (i
.types
[0].bitfield
.floatreg
5982 || operand_type_check (i
.types
[0], reg
))
5986 /* Register goes in low 3 bits of opcode. */
5987 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5988 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5990 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5992 /* Warn about some common errors, but press on regardless.
5993 The first case can be generated by gcc (<= 2.8.1). */
5994 if (i
.operands
== 2)
5996 /* Reversed arguments on faddp, fsubp, etc. */
5997 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5998 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5999 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6003 /* Extraneous `l' suffix on fp insn. */
6004 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6005 register_prefix
, i
.op
[0].regs
->reg_name
);
6010 else if (i
.tm
.opcode_modifier
.modrm
)
6012 /* The opcode is completed (modulo i.tm.extension_opcode which
6013 must be put into the modrm byte). Now, we make the modrm and
6014 index base bytes based on all the info we've collected. */
6016 default_seg
= build_modrm_byte ();
6018 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6022 else if (i
.tm
.opcode_modifier
.isstring
)
6024 /* For the string instructions that allow a segment override
6025 on one of their operands, the default segment is ds. */
6029 if (i
.tm
.base_opcode
== 0x8d /* lea */
6032 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6034 /* If a segment was explicitly specified, and the specified segment
6035 is not the default, use an opcode prefix to select it. If we
6036 never figured out what the default segment is, then default_seg
6037 will be zero at this point, and the specified segment prefix will
6039 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6041 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6047 static const seg_entry
*
6048 build_modrm_byte (void)
6050 const seg_entry
*default_seg
= 0;
6051 unsigned int source
, dest
;
6054 /* The first operand of instructions with VEX prefix and 3 sources
6055 must be VEX_Imm4. */
6056 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6059 unsigned int nds
, reg_slot
;
6062 if (i
.tm
.opcode_modifier
.veximmext
6063 && i
.tm
.opcode_modifier
.immext
)
6065 dest
= i
.operands
- 2;
6066 gas_assert (dest
== 3);
6069 dest
= i
.operands
- 1;
6072 /* There are 2 kinds of instructions:
6073 1. 5 operands: 4 register operands or 3 register operands
6074 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6075 VexW0 or VexW1. The destination must be either XMM, YMM or
6077 2. 4 operands: 4 register operands or 3 register operands
6078 plus 1 memory operand, VexXDS, and VexImmExt */
6079 gas_assert ((i
.reg_operands
== 4
6080 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6081 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6082 && (i
.tm
.opcode_modifier
.veximmext
6083 || (i
.imm_operands
== 1
6084 && i
.types
[0].bitfield
.vec_imm4
6085 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
6086 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6087 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
6088 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
6089 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
6091 if (i
.imm_operands
== 0)
6093 /* When there is no immediate operand, generate an 8bit
6094 immediate operand to encode the first operand. */
6095 exp
= &im_expressions
[i
.imm_operands
++];
6096 i
.op
[i
.operands
].imms
= exp
;
6097 i
.types
[i
.operands
] = imm8
;
6099 /* If VexW1 is set, the first operand is the source and
6100 the second operand is encoded in the immediate operand. */
6101 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6112 /* FMA swaps REG and NDS. */
6113 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6121 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6123 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6125 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6127 exp
->X_op
= O_constant
;
6128 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6129 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6133 unsigned int imm_slot
;
6135 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6137 /* If VexW0 is set, the third operand is the source and
6138 the second operand is encoded in the immediate
6145 /* VexW1 is set, the second operand is the source and
6146 the third operand is encoded in the immediate
6152 if (i
.tm
.opcode_modifier
.immext
)
6154 /* When ImmExt is set, the immdiate byte is the last
6156 imm_slot
= i
.operands
- 1;
6164 /* Turn on Imm8 so that output_imm will generate it. */
6165 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6168 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6170 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6172 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6174 i
.op
[imm_slot
].imms
->X_add_number
6175 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6176 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6179 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6180 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6182 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6184 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6189 /* i.reg_operands MUST be the number of real register operands;
6190 implicit registers do not count. If there are 3 register
6191 operands, it must be a instruction with VexNDS. For a
6192 instruction with VexNDD, the destination register is encoded
6193 in VEX prefix. If there are 4 register operands, it must be
6194 a instruction with VEX prefix and 3 sources. */
6195 if (i
.mem_operands
== 0
6196 && ((i
.reg_operands
== 2
6197 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6198 || (i
.reg_operands
== 3
6199 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6200 || (i
.reg_operands
== 4 && vex_3_sources
)))
6208 /* When there are 3 operands, one of them may be immediate,
6209 which may be the first or the last operand. Otherwise,
6210 the first operand must be shift count register (cl) or it
6211 is an instruction with VexNDS. */
6212 gas_assert (i
.imm_operands
== 1
6213 || (i
.imm_operands
== 0
6214 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6215 || i
.types
[0].bitfield
.shiftcount
)));
6216 if (operand_type_check (i
.types
[0], imm
)
6217 || i
.types
[0].bitfield
.shiftcount
)
6223 /* When there are 4 operands, the first two must be 8bit
6224 immediate operands. The source operand will be the 3rd
6227 For instructions with VexNDS, if the first operand
6228 an imm8, the source operand is the 2nd one. If the last
6229 operand is imm8, the source operand is the first one. */
6230 gas_assert ((i
.imm_operands
== 2
6231 && i
.types
[0].bitfield
.imm8
6232 && i
.types
[1].bitfield
.imm8
)
6233 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6234 && i
.imm_operands
== 1
6235 && (i
.types
[0].bitfield
.imm8
6236 || i
.types
[i
.operands
- 1].bitfield
.imm8
6238 if (i
.imm_operands
== 2)
6242 if (i
.types
[0].bitfield
.imm8
)
6249 if (i
.tm
.opcode_modifier
.evex
)
6251 /* For EVEX instructions, when there are 5 operands, the
6252 first one must be immediate operand. If the second one
6253 is immediate operand, the source operand is the 3th
6254 one. If the last one is immediate operand, the source
6255 operand is the 2nd one. */
6256 gas_assert (i
.imm_operands
== 2
6257 && i
.tm
.opcode_modifier
.sae
6258 && operand_type_check (i
.types
[0], imm
));
6259 if (operand_type_check (i
.types
[1], imm
))
6261 else if (operand_type_check (i
.types
[4], imm
))
6275 /* RC/SAE operand could be between DEST and SRC. That happens
6276 when one operand is GPR and the other one is XMM/YMM/ZMM
6278 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6281 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6283 /* For instructions with VexNDS, the register-only source
6284 operand must be 32/64bit integer, XMM, YMM or ZMM
6285 register. It is encoded in VEX prefix. We need to
6286 clear RegMem bit before calling operand_type_equal. */
6288 i386_operand_type op
;
6291 /* Check register-only source operand when two source
6292 operands are swapped. */
6293 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6294 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6302 op
= i
.tm
.operand_types
[vvvv
];
6303 op
.bitfield
.regmem
= 0;
6304 if ((dest
+ 1) >= i
.operands
6305 || (!op
.bitfield
.reg32
6306 && op
.bitfield
.reg64
6307 && !operand_type_equal (&op
, ®xmm
)
6308 && !operand_type_equal (&op
, ®ymm
)
6309 && !operand_type_equal (&op
, ®zmm
)
6310 && !operand_type_equal (&op
, ®mask
)))
6312 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6318 /* One of the register operands will be encoded in the i.tm.reg
6319 field, the other in the combined i.tm.mode and i.tm.regmem
6320 fields. If no form of this instruction supports a memory
6321 destination operand, then we assume the source operand may
6322 sometimes be a memory operand and so we need to store the
6323 destination in the i.rm.reg field. */
6324 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6325 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6327 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6328 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6329 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6331 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6333 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6335 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6340 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6341 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6342 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6344 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6346 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6348 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6351 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6353 if (!i
.types
[0].bitfield
.control
6354 && !i
.types
[1].bitfield
.control
)
6356 i
.rex
&= ~(REX_R
| REX_B
);
6357 add_prefix (LOCK_PREFIX_OPCODE
);
6361 { /* If it's not 2 reg operands... */
6366 unsigned int fake_zero_displacement
= 0;
6369 for (op
= 0; op
< i
.operands
; op
++)
6370 if (operand_type_check (i
.types
[op
], anymem
))
6372 gas_assert (op
< i
.operands
);
6374 if (i
.tm
.opcode_modifier
.vecsib
)
6376 if (i
.index_reg
->reg_num
== RegEiz
6377 || i
.index_reg
->reg_num
== RegRiz
)
6380 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6383 i
.sib
.base
= NO_BASE_REGISTER
;
6384 i
.sib
.scale
= i
.log2_scale_factor
;
6385 /* No Vec_Disp8 if there is no base. */
6386 i
.types
[op
].bitfield
.vec_disp8
= 0;
6387 i
.types
[op
].bitfield
.disp8
= 0;
6388 i
.types
[op
].bitfield
.disp16
= 0;
6389 i
.types
[op
].bitfield
.disp64
= 0;
6390 if (flag_code
!= CODE_64BIT
)
6392 /* Must be 32 bit */
6393 i
.types
[op
].bitfield
.disp32
= 1;
6394 i
.types
[op
].bitfield
.disp32s
= 0;
6398 i
.types
[op
].bitfield
.disp32
= 0;
6399 i
.types
[op
].bitfield
.disp32s
= 1;
6402 i
.sib
.index
= i
.index_reg
->reg_num
;
6403 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6405 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6411 if (i
.base_reg
== 0)
6414 if (!i
.disp_operands
)
6416 fake_zero_displacement
= 1;
6417 /* Instructions with VSIB byte need 32bit displacement
6418 if there is no base register. */
6419 if (i
.tm
.opcode_modifier
.vecsib
)
6420 i
.types
[op
].bitfield
.disp32
= 1;
6422 if (i
.index_reg
== 0)
6424 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6425 /* Operand is just <disp> */
6426 if (flag_code
== CODE_64BIT
)
6428 /* 64bit mode overwrites the 32bit absolute
6429 addressing by RIP relative addressing and
6430 absolute addressing is encoded by one of the
6431 redundant SIB forms. */
6432 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6433 i
.sib
.base
= NO_BASE_REGISTER
;
6434 i
.sib
.index
= NO_INDEX_REGISTER
;
6435 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6436 ? disp32s
: disp32
);
6438 else if ((flag_code
== CODE_16BIT
)
6439 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6441 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6442 i
.types
[op
] = disp16
;
6446 i
.rm
.regmem
= NO_BASE_REGISTER
;
6447 i
.types
[op
] = disp32
;
6450 else if (!i
.tm
.opcode_modifier
.vecsib
)
6452 /* !i.base_reg && i.index_reg */
6453 if (i
.index_reg
->reg_num
== RegEiz
6454 || i
.index_reg
->reg_num
== RegRiz
)
6455 i
.sib
.index
= NO_INDEX_REGISTER
;
6457 i
.sib
.index
= i
.index_reg
->reg_num
;
6458 i
.sib
.base
= NO_BASE_REGISTER
;
6459 i
.sib
.scale
= i
.log2_scale_factor
;
6460 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6461 /* No Vec_Disp8 if there is no base. */
6462 i
.types
[op
].bitfield
.vec_disp8
= 0;
6463 i
.types
[op
].bitfield
.disp8
= 0;
6464 i
.types
[op
].bitfield
.disp16
= 0;
6465 i
.types
[op
].bitfield
.disp64
= 0;
6466 if (flag_code
!= CODE_64BIT
)
6468 /* Must be 32 bit */
6469 i
.types
[op
].bitfield
.disp32
= 1;
6470 i
.types
[op
].bitfield
.disp32s
= 0;
6474 i
.types
[op
].bitfield
.disp32
= 0;
6475 i
.types
[op
].bitfield
.disp32s
= 1;
6477 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6481 /* RIP addressing for 64bit mode. */
6482 else if (i
.base_reg
->reg_num
== RegRip
||
6483 i
.base_reg
->reg_num
== RegEip
)
6485 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6486 i
.rm
.regmem
= NO_BASE_REGISTER
;
6487 i
.types
[op
].bitfield
.disp8
= 0;
6488 i
.types
[op
].bitfield
.disp16
= 0;
6489 i
.types
[op
].bitfield
.disp32
= 0;
6490 i
.types
[op
].bitfield
.disp32s
= 1;
6491 i
.types
[op
].bitfield
.disp64
= 0;
6492 i
.types
[op
].bitfield
.vec_disp8
= 0;
6493 i
.flags
[op
] |= Operand_PCrel
;
6494 if (! i
.disp_operands
)
6495 fake_zero_displacement
= 1;
6497 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6499 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6500 switch (i
.base_reg
->reg_num
)
6503 if (i
.index_reg
== 0)
6505 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6506 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6510 if (i
.index_reg
== 0)
6513 if (operand_type_check (i
.types
[op
], disp
) == 0)
6515 /* fake (%bp) into 0(%bp) */
6516 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6517 i
.types
[op
].bitfield
.vec_disp8
= 1;
6519 i
.types
[op
].bitfield
.disp8
= 1;
6520 fake_zero_displacement
= 1;
6523 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6524 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6526 default: /* (%si) -> 4 or (%di) -> 5 */
6527 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6529 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6531 else /* i.base_reg and 32/64 bit mode */
6533 if (flag_code
== CODE_64BIT
6534 && operand_type_check (i
.types
[op
], disp
))
6536 i386_operand_type temp
;
6537 operand_type_set (&temp
, 0);
6538 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6539 temp
.bitfield
.vec_disp8
6540 = i
.types
[op
].bitfield
.vec_disp8
;
6542 if (i
.prefix
[ADDR_PREFIX
] == 0)
6543 i
.types
[op
].bitfield
.disp32s
= 1;
6545 i
.types
[op
].bitfield
.disp32
= 1;
6548 if (!i
.tm
.opcode_modifier
.vecsib
)
6549 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6550 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6552 i
.sib
.base
= i
.base_reg
->reg_num
;
6553 /* x86-64 ignores REX prefix bit here to avoid decoder
6555 if (!(i
.base_reg
->reg_flags
& RegRex
)
6556 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6557 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6559 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6561 fake_zero_displacement
= 1;
6562 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6563 i
.types
[op
].bitfield
.vec_disp8
= 1;
6565 i
.types
[op
].bitfield
.disp8
= 1;
6567 i
.sib
.scale
= i
.log2_scale_factor
;
6568 if (i
.index_reg
== 0)
6570 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6571 /* <disp>(%esp) becomes two byte modrm with no index
6572 register. We've already stored the code for esp
6573 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6574 Any base register besides %esp will not use the
6575 extra modrm byte. */
6576 i
.sib
.index
= NO_INDEX_REGISTER
;
6578 else if (!i
.tm
.opcode_modifier
.vecsib
)
6580 if (i
.index_reg
->reg_num
== RegEiz
6581 || i
.index_reg
->reg_num
== RegRiz
)
6582 i
.sib
.index
= NO_INDEX_REGISTER
;
6584 i
.sib
.index
= i
.index_reg
->reg_num
;
6585 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6586 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6591 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6592 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6596 if (!fake_zero_displacement
6600 fake_zero_displacement
= 1;
6601 if (i
.disp_encoding
== disp_encoding_8bit
)
6602 i
.types
[op
].bitfield
.disp8
= 1;
6604 i
.types
[op
].bitfield
.disp32
= 1;
6606 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6610 if (fake_zero_displacement
)
6612 /* Fakes a zero displacement assuming that i.types[op]
6613 holds the correct displacement size. */
6616 gas_assert (i
.op
[op
].disps
== 0);
6617 exp
= &disp_expressions
[i
.disp_operands
++];
6618 i
.op
[op
].disps
= exp
;
6619 exp
->X_op
= O_constant
;
6620 exp
->X_add_number
= 0;
6621 exp
->X_add_symbol
= (symbolS
*) 0;
6622 exp
->X_op_symbol
= (symbolS
*) 0;
6630 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6632 if (operand_type_check (i
.types
[0], imm
))
6633 i
.vex
.register_specifier
= NULL
;
6636 /* VEX.vvvv encodes one of the sources when the first
6637 operand is not an immediate. */
6638 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6639 i
.vex
.register_specifier
= i
.op
[0].regs
;
6641 i
.vex
.register_specifier
= i
.op
[1].regs
;
6644 /* Destination is a XMM register encoded in the ModRM.reg
6646 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6647 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6650 /* ModRM.rm and VEX.B encodes the other source. */
6651 if (!i
.mem_operands
)
6655 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6656 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6658 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6660 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6664 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6666 i
.vex
.register_specifier
= i
.op
[2].regs
;
6667 if (!i
.mem_operands
)
6670 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6671 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6675 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6676 (if any) based on i.tm.extension_opcode. Again, we must be
6677 careful to make sure that segment/control/debug/test/MMX
6678 registers are coded into the i.rm.reg field. */
6679 else if (i
.reg_operands
)
6682 unsigned int vex_reg
= ~0;
6684 for (op
= 0; op
< i
.operands
; op
++)
6685 if (i
.types
[op
].bitfield
.reg8
6686 || i
.types
[op
].bitfield
.reg16
6687 || i
.types
[op
].bitfield
.reg32
6688 || i
.types
[op
].bitfield
.reg64
6689 || i
.types
[op
].bitfield
.regmmx
6690 || i
.types
[op
].bitfield
.regxmm
6691 || i
.types
[op
].bitfield
.regymm
6692 || i
.types
[op
].bitfield
.regbnd
6693 || i
.types
[op
].bitfield
.regzmm
6694 || i
.types
[op
].bitfield
.regmask
6695 || i
.types
[op
].bitfield
.sreg2
6696 || i
.types
[op
].bitfield
.sreg3
6697 || i
.types
[op
].bitfield
.control
6698 || i
.types
[op
].bitfield
.debug
6699 || i
.types
[op
].bitfield
.test
)
6704 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6706 /* For instructions with VexNDS, the register-only
6707 source operand is encoded in VEX prefix. */
6708 gas_assert (mem
!= (unsigned int) ~0);
6713 gas_assert (op
< i
.operands
);
6717 /* Check register-only source operand when two source
6718 operands are swapped. */
6719 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6720 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6724 gas_assert (mem
== (vex_reg
+ 1)
6725 && op
< i
.operands
);
6730 gas_assert (vex_reg
< i
.operands
);
6734 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6736 /* For instructions with VexNDD, the register destination
6737 is encoded in VEX prefix. */
6738 if (i
.mem_operands
== 0)
6740 /* There is no memory operand. */
6741 gas_assert ((op
+ 2) == i
.operands
);
6746 /* There are only 2 operands. */
6747 gas_assert (op
< 2 && i
.operands
== 2);
6752 gas_assert (op
< i
.operands
);
6754 if (vex_reg
!= (unsigned int) ~0)
6756 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6758 if (type
->bitfield
.reg32
!= 1
6759 && type
->bitfield
.reg64
!= 1
6760 && !operand_type_equal (type
, ®xmm
)
6761 && !operand_type_equal (type
, ®ymm
)
6762 && !operand_type_equal (type
, ®zmm
)
6763 && !operand_type_equal (type
, ®mask
))
6766 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6769 /* Don't set OP operand twice. */
6772 /* If there is an extension opcode to put here, the
6773 register number must be put into the regmem field. */
6774 if (i
.tm
.extension_opcode
!= None
)
6776 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6777 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6779 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6784 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6785 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6787 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6792 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6793 must set it to 3 to indicate this is a register operand
6794 in the regmem field. */
6795 if (!i
.mem_operands
)
6799 /* Fill in i.rm.reg field with extension opcode (if any). */
6800 if (i
.tm
.extension_opcode
!= None
)
6801 i
.rm
.reg
= i
.tm
.extension_opcode
;
6807 output_branch (void)
6813 relax_substateT subtype
;
6817 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6818 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6821 if (i
.prefix
[DATA_PREFIX
] != 0)
6827 /* Pentium4 branch hints. */
6828 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6829 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6834 if (i
.prefix
[REX_PREFIX
] != 0)
6840 /* BND prefixed jump. */
6841 if (i
.prefix
[BND_PREFIX
] != 0)
6843 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6847 if (i
.prefixes
!= 0 && !intel_syntax
)
6848 as_warn (_("skipping prefixes on this instruction"));
6850 /* It's always a symbol; End frag & setup for relax.
6851 Make sure there is enough room in this frag for the largest
6852 instruction we may generate in md_convert_frag. This is 2
6853 bytes for the opcode and room for the prefix and largest
6855 frag_grow (prefix
+ 2 + 4);
6856 /* Prefix and 1 opcode byte go in fr_fix. */
6857 p
= frag_more (prefix
+ 1);
6858 if (i
.prefix
[DATA_PREFIX
] != 0)
6859 *p
++ = DATA_PREFIX_OPCODE
;
6860 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6861 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6862 *p
++ = i
.prefix
[SEG_PREFIX
];
6863 if (i
.prefix
[REX_PREFIX
] != 0)
6864 *p
++ = i
.prefix
[REX_PREFIX
];
6865 *p
= i
.tm
.base_opcode
;
6867 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6868 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6869 else if (cpu_arch_flags
.bitfield
.cpui386
)
6870 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6872 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6875 sym
= i
.op
[0].disps
->X_add_symbol
;
6876 off
= i
.op
[0].disps
->X_add_number
;
6878 if (i
.op
[0].disps
->X_op
!= O_constant
6879 && i
.op
[0].disps
->X_op
!= O_symbol
)
6881 /* Handle complex expressions. */
6882 sym
= make_expr_symbol (i
.op
[0].disps
);
6886 /* 1 possible extra opcode + 4 byte displacement go in var part.
6887 Pass reloc in fr_var. */
6888 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6898 if (i
.tm
.opcode_modifier
.jumpbyte
)
6900 /* This is a loop or jecxz type instruction. */
6902 if (i
.prefix
[ADDR_PREFIX
] != 0)
6904 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6907 /* Pentium4 branch hints. */
6908 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6909 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6911 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6920 if (flag_code
== CODE_16BIT
)
6923 if (i
.prefix
[DATA_PREFIX
] != 0)
6925 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6935 if (i
.prefix
[REX_PREFIX
] != 0)
6937 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6941 /* BND prefixed jump. */
6942 if (i
.prefix
[BND_PREFIX
] != 0)
6944 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6948 if (i
.prefixes
!= 0 && !intel_syntax
)
6949 as_warn (_("skipping prefixes on this instruction"));
6951 p
= frag_more (i
.tm
.opcode_length
+ size
);
6952 switch (i
.tm
.opcode_length
)
6955 *p
++ = i
.tm
.base_opcode
>> 8;
6957 *p
++ = i
.tm
.base_opcode
;
6963 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6964 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6966 /* All jumps handled here are signed, but don't use a signed limit
6967 check for 32 and 16 bit jumps as we want to allow wrap around at
6968 4G and 64k respectively. */
6970 fixP
->fx_signed
= 1;
6974 output_interseg_jump (void)
6982 if (flag_code
== CODE_16BIT
)
6986 if (i
.prefix
[DATA_PREFIX
] != 0)
6992 if (i
.prefix
[REX_PREFIX
] != 0)
7002 if (i
.prefixes
!= 0 && !intel_syntax
)
7003 as_warn (_("skipping prefixes on this instruction"));
7005 /* 1 opcode; 2 segment; offset */
7006 p
= frag_more (prefix
+ 1 + 2 + size
);
7008 if (i
.prefix
[DATA_PREFIX
] != 0)
7009 *p
++ = DATA_PREFIX_OPCODE
;
7011 if (i
.prefix
[REX_PREFIX
] != 0)
7012 *p
++ = i
.prefix
[REX_PREFIX
];
7014 *p
++ = i
.tm
.base_opcode
;
7015 if (i
.op
[1].imms
->X_op
== O_constant
)
7017 offsetT n
= i
.op
[1].imms
->X_add_number
;
7020 && !fits_in_unsigned_word (n
)
7021 && !fits_in_signed_word (n
))
7023 as_bad (_("16-bit jump out of range"));
7026 md_number_to_chars (p
, n
, size
);
7029 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7030 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7031 if (i
.op
[0].imms
->X_op
!= O_constant
)
7032 as_bad (_("can't handle non absolute segment in `%s'"),
7034 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7040 fragS
*insn_start_frag
;
7041 offsetT insn_start_off
;
7043 /* Tie dwarf2 debug info to the address at the start of the insn.
7044 We can't do this after the insn has been output as the current
7045 frag may have been closed off. eg. by frag_var. */
7046 dwarf2_emit_insn (0);
7048 insn_start_frag
= frag_now
;
7049 insn_start_off
= frag_now_fix ();
7052 if (i
.tm
.opcode_modifier
.jump
)
7054 else if (i
.tm
.opcode_modifier
.jumpbyte
7055 || i
.tm
.opcode_modifier
.jumpdword
)
7057 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7058 output_interseg_jump ();
7061 /* Output normal instructions here. */
7065 unsigned int prefix
;
7068 && i
.tm
.base_opcode
== 0xfae
7070 && i
.imm_operands
== 1
7071 && (i
.op
[0].imms
->X_add_number
== 0xe8
7072 || i
.op
[0].imms
->X_add_number
== 0xf0
7073 || i
.op
[0].imms
->X_add_number
== 0xf8))
7075 /* Encode lfence, mfence, and sfence as
7076 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7077 offsetT val
= 0x240483f0ULL
;
7079 md_number_to_chars (p
, val
, 5);
7083 /* Some processors fail on LOCK prefix. This options makes
7084 assembler ignore LOCK prefix and serves as a workaround. */
7085 if (omit_lock_prefix
)
7087 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7089 i
.prefix
[LOCK_PREFIX
] = 0;
7092 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7093 don't need the explicit prefix. */
7094 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7096 switch (i
.tm
.opcode_length
)
7099 if (i
.tm
.base_opcode
& 0xff000000)
7101 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7106 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7108 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7109 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7112 if (prefix
!= REPE_PREFIX_OPCODE
7113 || (i
.prefix
[REP_PREFIX
]
7114 != REPE_PREFIX_OPCODE
))
7115 add_prefix (prefix
);
7118 add_prefix (prefix
);
7127 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7128 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7129 R_X86_64_GOTTPOFF relocation so that linker can safely
7130 perform IE->LE optimization. */
7131 if (x86_elf_abi
== X86_64_X32_ABI
7133 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7134 && i
.prefix
[REX_PREFIX
] == 0)
7135 add_prefix (REX_OPCODE
);
7138 /* The prefix bytes. */
7139 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7141 FRAG_APPEND_1_CHAR (*q
);
7145 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7150 /* REX byte is encoded in VEX prefix. */
7154 FRAG_APPEND_1_CHAR (*q
);
7157 /* There should be no other prefixes for instructions
7162 /* For EVEX instructions i.vrex should become 0 after
7163 build_evex_prefix. For VEX instructions upper 16 registers
7164 aren't available, so VREX should be 0. */
7167 /* Now the VEX prefix. */
7168 p
= frag_more (i
.vex
.length
);
7169 for (j
= 0; j
< i
.vex
.length
; j
++)
7170 p
[j
] = i
.vex
.bytes
[j
];
7173 /* Now the opcode; be careful about word order here! */
7174 if (i
.tm
.opcode_length
== 1)
7176 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7180 switch (i
.tm
.opcode_length
)
7184 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7185 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7189 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7199 /* Put out high byte first: can't use md_number_to_chars! */
7200 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7201 *p
= i
.tm
.base_opcode
& 0xff;
7204 /* Now the modrm byte and sib byte (if present). */
7205 if (i
.tm
.opcode_modifier
.modrm
)
7207 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7210 /* If i.rm.regmem == ESP (4)
7211 && i.rm.mode != (Register mode)
7213 ==> need second modrm byte. */
7214 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7216 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7217 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7219 | i
.sib
.scale
<< 6));
7222 if (i
.disp_operands
)
7223 output_disp (insn_start_frag
, insn_start_off
);
7226 output_imm (insn_start_frag
, insn_start_off
);
7232 pi ("" /*line*/, &i
);
7234 #endif /* DEBUG386 */
7237 /* Return the size of the displacement operand N. */
7240 disp_size (unsigned int n
)
7244 /* Vec_Disp8 has to be 8bit. */
7245 if (i
.types
[n
].bitfield
.vec_disp8
)
7247 else if (i
.types
[n
].bitfield
.disp64
)
7249 else if (i
.types
[n
].bitfield
.disp8
)
7251 else if (i
.types
[n
].bitfield
.disp16
)
7256 /* Return the size of the immediate operand N. */
7259 imm_size (unsigned int n
)
7262 if (i
.types
[n
].bitfield
.imm64
)
7264 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7266 else if (i
.types
[n
].bitfield
.imm16
)
7272 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7277 for (n
= 0; n
< i
.operands
; n
++)
7279 if (i
.types
[n
].bitfield
.vec_disp8
7280 || operand_type_check (i
.types
[n
], disp
))
7282 if (i
.op
[n
].disps
->X_op
== O_constant
)
7284 int size
= disp_size (n
);
7285 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7287 if (i
.types
[n
].bitfield
.vec_disp8
)
7289 val
= offset_in_range (val
, size
);
7290 p
= frag_more (size
);
7291 md_number_to_chars (p
, val
, size
);
7295 enum bfd_reloc_code_real reloc_type
;
7296 int size
= disp_size (n
);
7297 int sign
= i
.types
[n
].bitfield
.disp32s
;
7298 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7301 /* We can't have 8 bit displacement here. */
7302 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7304 /* The PC relative address is computed relative
7305 to the instruction boundary, so in case immediate
7306 fields follows, we need to adjust the value. */
7307 if (pcrel
&& i
.imm_operands
)
7312 for (n1
= 0; n1
< i
.operands
; n1
++)
7313 if (operand_type_check (i
.types
[n1
], imm
))
7315 /* Only one immediate is allowed for PC
7316 relative address. */
7317 gas_assert (sz
== 0);
7319 i
.op
[n
].disps
->X_add_number
-= sz
;
7321 /* We should find the immediate. */
7322 gas_assert (sz
!= 0);
7325 p
= frag_more (size
);
7326 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7328 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7329 && (((reloc_type
== BFD_RELOC_32
7330 || reloc_type
== BFD_RELOC_X86_64_32S
7331 || (reloc_type
== BFD_RELOC_64
7333 && (i
.op
[n
].disps
->X_op
== O_symbol
7334 || (i
.op
[n
].disps
->X_op
== O_add
7335 && ((symbol_get_value_expression
7336 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7338 || reloc_type
== BFD_RELOC_32_PCREL
))
7342 if (insn_start_frag
== frag_now
)
7343 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7348 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7349 for (fr
= insn_start_frag
->fr_next
;
7350 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7352 add
+= p
- frag_now
->fr_literal
;
7357 reloc_type
= BFD_RELOC_386_GOTPC
;
7358 i
.op
[n
].imms
->X_add_number
+= add
;
7360 else if (reloc_type
== BFD_RELOC_64
)
7361 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7363 /* Don't do the adjustment for x86-64, as there
7364 the pcrel addressing is relative to the _next_
7365 insn, and that is taken care of in other code. */
7366 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7368 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7369 size
, i
.op
[n
].disps
, pcrel
,
7371 /* Check for "call/jmp *mem", "mov mem, %reg",
7372 "test %reg, mem" and "binop mem, %reg" where binop
7373 is one of adc, add, and, cmp, or, sbb, sub, xor
7374 instructions. Always generate R_386_GOT32X for
7375 "sym*GOT" operand in 32-bit mode. */
7376 if ((generate_relax_relocations
7379 && i
.rm
.regmem
== 5))
7381 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7382 && ((i
.operands
== 1
7383 && i
.tm
.base_opcode
== 0xff
7384 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7386 && (i
.tm
.base_opcode
== 0x8b
7387 || i
.tm
.base_opcode
== 0x85
7388 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7392 fixP
->fx_tcbit
= i
.rex
!= 0;
7394 && (i
.base_reg
->reg_num
== RegRip
7395 || i
.base_reg
->reg_num
== RegEip
))
7396 fixP
->fx_tcbit2
= 1;
7399 fixP
->fx_tcbit2
= 1;
7407 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7412 for (n
= 0; n
< i
.operands
; n
++)
7414 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7415 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7418 if (operand_type_check (i
.types
[n
], imm
))
7420 if (i
.op
[n
].imms
->X_op
== O_constant
)
7422 int size
= imm_size (n
);
7425 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7427 p
= frag_more (size
);
7428 md_number_to_chars (p
, val
, size
);
7432 /* Not absolute_section.
7433 Need a 32-bit fixup (don't support 8bit
7434 non-absolute imms). Try to support other
7436 enum bfd_reloc_code_real reloc_type
;
7437 int size
= imm_size (n
);
7440 if (i
.types
[n
].bitfield
.imm32s
7441 && (i
.suffix
== QWORD_MNEM_SUFFIX
7442 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7447 p
= frag_more (size
);
7448 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7450 /* This is tough to explain. We end up with this one if we
7451 * have operands that look like
7452 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7453 * obtain the absolute address of the GOT, and it is strongly
7454 * preferable from a performance point of view to avoid using
7455 * a runtime relocation for this. The actual sequence of
7456 * instructions often look something like:
7461 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7463 * The call and pop essentially return the absolute address
7464 * of the label .L66 and store it in %ebx. The linker itself
7465 * will ultimately change the first operand of the addl so
7466 * that %ebx points to the GOT, but to keep things simple, the
7467 * .o file must have this operand set so that it generates not
7468 * the absolute address of .L66, but the absolute address of
7469 * itself. This allows the linker itself simply treat a GOTPC
7470 * relocation as asking for a pcrel offset to the GOT to be
7471 * added in, and the addend of the relocation is stored in the
7472 * operand field for the instruction itself.
7474 * Our job here is to fix the operand so that it would add
7475 * the correct offset so that %ebx would point to itself. The
7476 * thing that is tricky is that .-.L66 will point to the
7477 * beginning of the instruction, so we need to further modify
7478 * the operand so that it will point to itself. There are
7479 * other cases where you have something like:
7481 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7483 * and here no correction would be required. Internally in
7484 * the assembler we treat operands of this form as not being
7485 * pcrel since the '.' is explicitly mentioned, and I wonder
7486 * whether it would simplify matters to do it this way. Who
7487 * knows. In earlier versions of the PIC patches, the
7488 * pcrel_adjust field was used to store the correction, but
7489 * since the expression is not pcrel, I felt it would be
7490 * confusing to do it this way. */
7492 if ((reloc_type
== BFD_RELOC_32
7493 || reloc_type
== BFD_RELOC_X86_64_32S
7494 || reloc_type
== BFD_RELOC_64
)
7496 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7497 && (i
.op
[n
].imms
->X_op
== O_symbol
7498 || (i
.op
[n
].imms
->X_op
== O_add
7499 && ((symbol_get_value_expression
7500 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7505 if (insn_start_frag
== frag_now
)
7506 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7511 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7512 for (fr
= insn_start_frag
->fr_next
;
7513 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7515 add
+= p
- frag_now
->fr_literal
;
7519 reloc_type
= BFD_RELOC_386_GOTPC
;
7521 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7523 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7524 i
.op
[n
].imms
->X_add_number
+= add
;
7526 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7527 i
.op
[n
].imms
, 0, reloc_type
);
7533 /* x86_cons_fix_new is called via the expression parsing code when a
7534 reloc is needed. We use this hook to get the correct .got reloc. */
7535 static int cons_sign
= -1;
7538 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7539 expressionS
*exp
, bfd_reloc_code_real_type r
)
7541 r
= reloc (len
, 0, cons_sign
, r
);
7544 if (exp
->X_op
== O_secrel
)
7546 exp
->X_op
= O_symbol
;
7547 r
= BFD_RELOC_32_SECREL
;
7551 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7554 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7555 purpose of the `.dc.a' internal pseudo-op. */
7558 x86_address_bytes (void)
7560 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7562 return stdoutput
->arch_info
->bits_per_address
/ 8;
7565 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7567 # define lex_got(reloc, adjust, types) NULL
7569 /* Parse operands of the form
7570 <symbol>@GOTOFF+<nnn>
7571 and similar .plt or .got references.
7573 If we find one, set up the correct relocation in RELOC and copy the
7574 input string, minus the `@GOTOFF' into a malloc'd buffer for
7575 parsing by the calling routine. Return this buffer, and if ADJUST
7576 is non-null set it to the length of the string we removed from the
7577 input line. Otherwise return NULL. */
7579 lex_got (enum bfd_reloc_code_real
*rel
,
7581 i386_operand_type
*types
)
7583 /* Some of the relocations depend on the size of what field is to
7584 be relocated. But in our callers i386_immediate and i386_displacement
7585 we don't yet know the operand size (this will be set by insn
7586 matching). Hence we record the word32 relocation here,
7587 and adjust the reloc according to the real size in reloc(). */
7588 static const struct {
7591 const enum bfd_reloc_code_real rel
[2];
7592 const i386_operand_type types64
;
7594 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7595 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7597 OPERAND_TYPE_IMM32_64
},
7599 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7600 BFD_RELOC_X86_64_PLTOFF64
},
7601 OPERAND_TYPE_IMM64
},
7602 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7603 BFD_RELOC_X86_64_PLT32
},
7604 OPERAND_TYPE_IMM32_32S_DISP32
},
7605 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7606 BFD_RELOC_X86_64_GOTPLT64
},
7607 OPERAND_TYPE_IMM64_DISP64
},
7608 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7609 BFD_RELOC_X86_64_GOTOFF64
},
7610 OPERAND_TYPE_IMM64_DISP64
},
7611 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7612 BFD_RELOC_X86_64_GOTPCREL
},
7613 OPERAND_TYPE_IMM32_32S_DISP32
},
7614 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7615 BFD_RELOC_X86_64_TLSGD
},
7616 OPERAND_TYPE_IMM32_32S_DISP32
},
7617 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7618 _dummy_first_bfd_reloc_code_real
},
7619 OPERAND_TYPE_NONE
},
7620 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7621 BFD_RELOC_X86_64_TLSLD
},
7622 OPERAND_TYPE_IMM32_32S_DISP32
},
7623 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7624 BFD_RELOC_X86_64_GOTTPOFF
},
7625 OPERAND_TYPE_IMM32_32S_DISP32
},
7626 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7627 BFD_RELOC_X86_64_TPOFF32
},
7628 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7629 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7630 _dummy_first_bfd_reloc_code_real
},
7631 OPERAND_TYPE_NONE
},
7632 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7633 BFD_RELOC_X86_64_DTPOFF32
},
7634 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7635 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7636 _dummy_first_bfd_reloc_code_real
},
7637 OPERAND_TYPE_NONE
},
7638 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7639 _dummy_first_bfd_reloc_code_real
},
7640 OPERAND_TYPE_NONE
},
7641 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7642 BFD_RELOC_X86_64_GOT32
},
7643 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7644 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7645 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7646 OPERAND_TYPE_IMM32_32S_DISP32
},
7647 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7648 BFD_RELOC_X86_64_TLSDESC_CALL
},
7649 OPERAND_TYPE_IMM32_32S_DISP32
},
7654 #if defined (OBJ_MAYBE_ELF)
7659 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7660 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7663 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7665 int len
= gotrel
[j
].len
;
7666 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7668 if (gotrel
[j
].rel
[object_64bit
] != 0)
7671 char *tmpbuf
, *past_reloc
;
7673 *rel
= gotrel
[j
].rel
[object_64bit
];
7677 if (flag_code
!= CODE_64BIT
)
7679 types
->bitfield
.imm32
= 1;
7680 types
->bitfield
.disp32
= 1;
7683 *types
= gotrel
[j
].types64
;
7686 if (j
!= 0 && GOT_symbol
== NULL
)
7687 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7689 /* The length of the first part of our input line. */
7690 first
= cp
- input_line_pointer
;
7692 /* The second part goes from after the reloc token until
7693 (and including) an end_of_line char or comma. */
7694 past_reloc
= cp
+ 1 + len
;
7696 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7698 second
= cp
+ 1 - past_reloc
;
7700 /* Allocate and copy string. The trailing NUL shouldn't
7701 be necessary, but be safe. */
7702 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7703 memcpy (tmpbuf
, input_line_pointer
, first
);
7704 if (second
!= 0 && *past_reloc
!= ' ')
7705 /* Replace the relocation token with ' ', so that
7706 errors like foo@GOTOFF1 will be detected. */
7707 tmpbuf
[first
++] = ' ';
7709 /* Increment length by 1 if the relocation token is
7714 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7715 tmpbuf
[first
+ second
] = '\0';
7719 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7720 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7725 /* Might be a symbol version string. Don't as_bad here. */
7734 /* Parse operands of the form
7735 <symbol>@SECREL32+<nnn>
7737 If we find one, set up the correct relocation in RELOC and copy the
7738 input string, minus the `@SECREL32' into a malloc'd buffer for
7739 parsing by the calling routine. Return this buffer, and if ADJUST
7740 is non-null set it to the length of the string we removed from the
7741 input line. Otherwise return NULL.
7743 This function is copied from the ELF version above adjusted for PE targets. */
7746 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7747 int *adjust ATTRIBUTE_UNUSED
,
7748 i386_operand_type
*types
)
7754 const enum bfd_reloc_code_real rel
[2];
7755 const i386_operand_type types64
;
7759 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7760 BFD_RELOC_32_SECREL
},
7761 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7767 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7768 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7771 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7773 int len
= gotrel
[j
].len
;
7775 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7777 if (gotrel
[j
].rel
[object_64bit
] != 0)
7780 char *tmpbuf
, *past_reloc
;
7782 *rel
= gotrel
[j
].rel
[object_64bit
];
7788 if (flag_code
!= CODE_64BIT
)
7790 types
->bitfield
.imm32
= 1;
7791 types
->bitfield
.disp32
= 1;
7794 *types
= gotrel
[j
].types64
;
7797 /* The length of the first part of our input line. */
7798 first
= cp
- input_line_pointer
;
7800 /* The second part goes from after the reloc token until
7801 (and including) an end_of_line char or comma. */
7802 past_reloc
= cp
+ 1 + len
;
7804 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7806 second
= cp
+ 1 - past_reloc
;
7808 /* Allocate and copy string. The trailing NUL shouldn't
7809 be necessary, but be safe. */
7810 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7811 memcpy (tmpbuf
, input_line_pointer
, first
);
7812 if (second
!= 0 && *past_reloc
!= ' ')
7813 /* Replace the relocation token with ' ', so that
7814 errors like foo@SECLREL321 will be detected. */
7815 tmpbuf
[first
++] = ' ';
7816 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7817 tmpbuf
[first
+ second
] = '\0';
7821 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7822 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7827 /* Might be a symbol version string. Don't as_bad here. */
7833 bfd_reloc_code_real_type
7834 x86_cons (expressionS
*exp
, int size
)
7836 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7838 intel_syntax
= -intel_syntax
;
7841 if (size
== 4 || (object_64bit
&& size
== 8))
7843 /* Handle @GOTOFF and the like in an expression. */
7845 char *gotfree_input_line
;
7848 save
= input_line_pointer
;
7849 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7850 if (gotfree_input_line
)
7851 input_line_pointer
= gotfree_input_line
;
7855 if (gotfree_input_line
)
7857 /* expression () has merrily parsed up to the end of line,
7858 or a comma - in the wrong buffer. Transfer how far
7859 input_line_pointer has moved to the right buffer. */
7860 input_line_pointer
= (save
7861 + (input_line_pointer
- gotfree_input_line
)
7863 free (gotfree_input_line
);
7864 if (exp
->X_op
== O_constant
7865 || exp
->X_op
== O_absent
7866 || exp
->X_op
== O_illegal
7867 || exp
->X_op
== O_register
7868 || exp
->X_op
== O_big
)
7870 char c
= *input_line_pointer
;
7871 *input_line_pointer
= 0;
7872 as_bad (_("missing or invalid expression `%s'"), save
);
7873 *input_line_pointer
= c
;
7880 intel_syntax
= -intel_syntax
;
7883 i386_intel_simplify (exp
);
7889 signed_cons (int size
)
7891 if (flag_code
== CODE_64BIT
)
7899 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7906 if (exp
.X_op
== O_symbol
)
7907 exp
.X_op
= O_secrel
;
7909 emit_expr (&exp
, 4);
7911 while (*input_line_pointer
++ == ',');
7913 input_line_pointer
--;
7914 demand_empty_rest_of_line ();
7918 /* Handle Vector operations. */
7921 check_VecOperations (char *op_string
, char *op_end
)
7923 const reg_entry
*mask
;
7928 && (op_end
== NULL
|| op_string
< op_end
))
7931 if (*op_string
== '{')
7935 /* Check broadcasts. */
7936 if (strncmp (op_string
, "1to", 3) == 0)
7941 goto duplicated_vec_op
;
7944 if (*op_string
== '8')
7945 bcst_type
= BROADCAST_1TO8
;
7946 else if (*op_string
== '4')
7947 bcst_type
= BROADCAST_1TO4
;
7948 else if (*op_string
== '2')
7949 bcst_type
= BROADCAST_1TO2
;
7950 else if (*op_string
== '1'
7951 && *(op_string
+1) == '6')
7953 bcst_type
= BROADCAST_1TO16
;
7958 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7963 broadcast_op
.type
= bcst_type
;
7964 broadcast_op
.operand
= this_operand
;
7965 i
.broadcast
= &broadcast_op
;
7967 /* Check masking operation. */
7968 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7970 /* k0 can't be used for write mask. */
7971 if (mask
->reg_num
== 0)
7973 as_bad (_("`%s' can't be used for write mask"),
7980 mask_op
.mask
= mask
;
7981 mask_op
.zeroing
= 0;
7982 mask_op
.operand
= this_operand
;
7988 goto duplicated_vec_op
;
7990 i
.mask
->mask
= mask
;
7992 /* Only "{z}" is allowed here. No need to check
7993 zeroing mask explicitly. */
7994 if (i
.mask
->operand
!= this_operand
)
7996 as_bad (_("invalid write mask `%s'"), saved
);
8003 /* Check zeroing-flag for masking operation. */
8004 else if (*op_string
== 'z')
8008 mask_op
.mask
= NULL
;
8009 mask_op
.zeroing
= 1;
8010 mask_op
.operand
= this_operand
;
8015 if (i
.mask
->zeroing
)
8018 as_bad (_("duplicated `%s'"), saved
);
8022 i
.mask
->zeroing
= 1;
8024 /* Only "{%k}" is allowed here. No need to check mask
8025 register explicitly. */
8026 if (i
.mask
->operand
!= this_operand
)
8028 as_bad (_("invalid zeroing-masking `%s'"),
8037 goto unknown_vec_op
;
8039 if (*op_string
!= '}')
8041 as_bad (_("missing `}' in `%s'"), saved
);
8048 /* We don't know this one. */
8049 as_bad (_("unknown vector operation: `%s'"), saved
);
8057 i386_immediate (char *imm_start
)
8059 char *save_input_line_pointer
;
8060 char *gotfree_input_line
;
8063 i386_operand_type types
;
8065 operand_type_set (&types
, ~0);
8067 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8069 as_bad (_("at most %d immediate operands are allowed"),
8070 MAX_IMMEDIATE_OPERANDS
);
8074 exp
= &im_expressions
[i
.imm_operands
++];
8075 i
.op
[this_operand
].imms
= exp
;
8077 if (is_space_char (*imm_start
))
8080 save_input_line_pointer
= input_line_pointer
;
8081 input_line_pointer
= imm_start
;
8083 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8084 if (gotfree_input_line
)
8085 input_line_pointer
= gotfree_input_line
;
8087 exp_seg
= expression (exp
);
8091 /* Handle vector operations. */
8092 if (*input_line_pointer
== '{')
8094 input_line_pointer
= check_VecOperations (input_line_pointer
,
8096 if (input_line_pointer
== NULL
)
8100 if (*input_line_pointer
)
8101 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8103 input_line_pointer
= save_input_line_pointer
;
8104 if (gotfree_input_line
)
8106 free (gotfree_input_line
);
8108 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8109 exp
->X_op
= O_illegal
;
8112 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8116 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8117 i386_operand_type types
, const char *imm_start
)
8119 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8122 as_bad (_("missing or invalid immediate expression `%s'"),
8126 else if (exp
->X_op
== O_constant
)
8128 /* Size it properly later. */
8129 i
.types
[this_operand
].bitfield
.imm64
= 1;
8130 /* If not 64bit, sign extend val. */
8131 if (flag_code
!= CODE_64BIT
8132 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8134 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8136 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8137 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8138 && exp_seg
!= absolute_section
8139 && exp_seg
!= text_section
8140 && exp_seg
!= data_section
8141 && exp_seg
!= bss_section
8142 && exp_seg
!= undefined_section
8143 && !bfd_is_com_section (exp_seg
))
8145 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8149 else if (!intel_syntax
&& exp_seg
== reg_section
)
8152 as_bad (_("illegal immediate register operand %s"), imm_start
);
8157 /* This is an address. The size of the address will be
8158 determined later, depending on destination register,
8159 suffix, or the default for the section. */
8160 i
.types
[this_operand
].bitfield
.imm8
= 1;
8161 i
.types
[this_operand
].bitfield
.imm16
= 1;
8162 i
.types
[this_operand
].bitfield
.imm32
= 1;
8163 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8164 i
.types
[this_operand
].bitfield
.imm64
= 1;
8165 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8173 i386_scale (char *scale
)
8176 char *save
= input_line_pointer
;
8178 input_line_pointer
= scale
;
8179 val
= get_absolute_expression ();
8184 i
.log2_scale_factor
= 0;
8187 i
.log2_scale_factor
= 1;
8190 i
.log2_scale_factor
= 2;
8193 i
.log2_scale_factor
= 3;
8197 char sep
= *input_line_pointer
;
8199 *input_line_pointer
= '\0';
8200 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8202 *input_line_pointer
= sep
;
8203 input_line_pointer
= save
;
8207 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8209 as_warn (_("scale factor of %d without an index register"),
8210 1 << i
.log2_scale_factor
);
8211 i
.log2_scale_factor
= 0;
8213 scale
= input_line_pointer
;
8214 input_line_pointer
= save
;
8219 i386_displacement (char *disp_start
, char *disp_end
)
8223 char *save_input_line_pointer
;
8224 char *gotfree_input_line
;
8226 i386_operand_type bigdisp
, types
= anydisp
;
8229 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8231 as_bad (_("at most %d displacement operands are allowed"),
8232 MAX_MEMORY_OPERANDS
);
8236 operand_type_set (&bigdisp
, 0);
8237 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8238 || (!current_templates
->start
->opcode_modifier
.jump
8239 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8241 bigdisp
.bitfield
.disp32
= 1;
8242 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8243 if (flag_code
== CODE_64BIT
)
8247 bigdisp
.bitfield
.disp32s
= 1;
8248 bigdisp
.bitfield
.disp64
= 1;
8251 else if ((flag_code
== CODE_16BIT
) ^ override
)
8253 bigdisp
.bitfield
.disp32
= 0;
8254 bigdisp
.bitfield
.disp16
= 1;
8259 /* For PC-relative branches, the width of the displacement
8260 is dependent upon data size, not address size. */
8261 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8262 if (flag_code
== CODE_64BIT
)
8264 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8265 bigdisp
.bitfield
.disp16
= 1;
8268 bigdisp
.bitfield
.disp32
= 1;
8269 bigdisp
.bitfield
.disp32s
= 1;
8275 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8277 : LONG_MNEM_SUFFIX
));
8278 bigdisp
.bitfield
.disp32
= 1;
8279 if ((flag_code
== CODE_16BIT
) ^ override
)
8281 bigdisp
.bitfield
.disp32
= 0;
8282 bigdisp
.bitfield
.disp16
= 1;
8286 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8289 exp
= &disp_expressions
[i
.disp_operands
];
8290 i
.op
[this_operand
].disps
= exp
;
8292 save_input_line_pointer
= input_line_pointer
;
8293 input_line_pointer
= disp_start
;
8294 END_STRING_AND_SAVE (disp_end
);
8296 #ifndef GCC_ASM_O_HACK
8297 #define GCC_ASM_O_HACK 0
8300 END_STRING_AND_SAVE (disp_end
+ 1);
8301 if (i
.types
[this_operand
].bitfield
.baseIndex
8302 && displacement_string_end
[-1] == '+')
8304 /* This hack is to avoid a warning when using the "o"
8305 constraint within gcc asm statements.
8308 #define _set_tssldt_desc(n,addr,limit,type) \
8309 __asm__ __volatile__ ( \
8311 "movw %w1,2+%0\n\t" \
8313 "movb %b1,4+%0\n\t" \
8314 "movb %4,5+%0\n\t" \
8315 "movb $0,6+%0\n\t" \
8316 "movb %h1,7+%0\n\t" \
8318 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8320 This works great except that the output assembler ends
8321 up looking a bit weird if it turns out that there is
8322 no offset. You end up producing code that looks like:
8335 So here we provide the missing zero. */
8337 *displacement_string_end
= '0';
8340 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8341 if (gotfree_input_line
)
8342 input_line_pointer
= gotfree_input_line
;
8344 exp_seg
= expression (exp
);
8347 if (*input_line_pointer
)
8348 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8350 RESTORE_END_STRING (disp_end
+ 1);
8352 input_line_pointer
= save_input_line_pointer
;
8353 if (gotfree_input_line
)
8355 free (gotfree_input_line
);
8357 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8358 exp
->X_op
= O_illegal
;
8361 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8363 RESTORE_END_STRING (disp_end
);
8369 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8370 i386_operand_type types
, const char *disp_start
)
8372 i386_operand_type bigdisp
;
8375 /* We do this to make sure that the section symbol is in
8376 the symbol table. We will ultimately change the relocation
8377 to be relative to the beginning of the section. */
8378 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8379 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8380 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8382 if (exp
->X_op
!= O_symbol
)
8385 if (S_IS_LOCAL (exp
->X_add_symbol
)
8386 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8387 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8388 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8389 exp
->X_op
= O_subtract
;
8390 exp
->X_op_symbol
= GOT_symbol
;
8391 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8392 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8393 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8394 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8396 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8399 else if (exp
->X_op
== O_absent
8400 || exp
->X_op
== O_illegal
8401 || exp
->X_op
== O_big
)
8404 as_bad (_("missing or invalid displacement expression `%s'"),
8409 else if (flag_code
== CODE_64BIT
8410 && !i
.prefix
[ADDR_PREFIX
]
8411 && exp
->X_op
== O_constant
)
8413 /* Since displacement is signed extended to 64bit, don't allow
8414 disp32 and turn off disp32s if they are out of range. */
8415 i
.types
[this_operand
].bitfield
.disp32
= 0;
8416 if (!fits_in_signed_long (exp
->X_add_number
))
8418 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8419 if (i
.types
[this_operand
].bitfield
.baseindex
)
8421 as_bad (_("0x%lx out range of signed 32bit displacement"),
8422 (long) exp
->X_add_number
);
8428 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8429 else if (exp
->X_op
!= O_constant
8430 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8431 && exp_seg
!= absolute_section
8432 && exp_seg
!= text_section
8433 && exp_seg
!= data_section
8434 && exp_seg
!= bss_section
8435 && exp_seg
!= undefined_section
8436 && !bfd_is_com_section (exp_seg
))
8438 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8443 /* Check if this is a displacement only operand. */
8444 bigdisp
= i
.types
[this_operand
];
8445 bigdisp
.bitfield
.disp8
= 0;
8446 bigdisp
.bitfield
.disp16
= 0;
8447 bigdisp
.bitfield
.disp32
= 0;
8448 bigdisp
.bitfield
.disp32s
= 0;
8449 bigdisp
.bitfield
.disp64
= 0;
8450 if (operand_type_all_zero (&bigdisp
))
8451 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8457 /* Make sure the memory operand we've been dealt is valid.
8458 Return 1 on success, 0 on a failure. */
8461 i386_index_check (const char *operand_string
)
8463 const char *kind
= "base/index";
8464 enum flag_code addr_mode
;
8466 if (i
.prefix
[ADDR_PREFIX
])
8467 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8470 addr_mode
= flag_code
;
8472 #if INFER_ADDR_PREFIX
8473 if (i
.mem_operands
== 0)
8475 /* Infer address prefix from the first memory operand. */
8476 const reg_entry
*addr_reg
= i
.base_reg
;
8478 if (addr_reg
== NULL
)
8479 addr_reg
= i
.index_reg
;
8483 if (addr_reg
->reg_num
== RegEip
8484 || addr_reg
->reg_num
== RegEiz
8485 || addr_reg
->reg_type
.bitfield
.reg32
)
8486 addr_mode
= CODE_32BIT
;
8487 else if (flag_code
!= CODE_64BIT
8488 && addr_reg
->reg_type
.bitfield
.reg16
)
8489 addr_mode
= CODE_16BIT
;
8491 if (addr_mode
!= flag_code
)
8493 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8495 /* Change the size of any displacement too. At most one
8496 of Disp16 or Disp32 is set.
8497 FIXME. There doesn't seem to be any real need for
8498 separate Disp16 and Disp32 flags. The same goes for
8499 Imm16 and Imm32. Removing them would probably clean
8500 up the code quite a lot. */
8501 if (flag_code
!= CODE_64BIT
8502 && (i
.types
[this_operand
].bitfield
.disp16
8503 || i
.types
[this_operand
].bitfield
.disp32
))
8504 i
.types
[this_operand
]
8505 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8512 if (current_templates
->start
->opcode_modifier
.isstring
8513 && !current_templates
->start
->opcode_modifier
.immext
8514 && (current_templates
->end
[-1].opcode_modifier
.isstring
8517 /* Memory operands of string insns are special in that they only allow
8518 a single register (rDI, rSI, or rBX) as their memory address. */
8519 const reg_entry
*expected_reg
;
8520 static const char *di_si
[][2] =
8526 static const char *bx
[] = { "ebx", "bx", "rbx" };
8528 kind
= "string address";
8530 if (current_templates
->start
->opcode_modifier
.repprefixok
)
8532 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8534 if (!type
.bitfield
.baseindex
8535 || ((!i
.mem_operands
!= !intel_syntax
)
8536 && current_templates
->end
[-1].operand_types
[1]
8537 .bitfield
.baseindex
))
8538 type
= current_templates
->end
[-1].operand_types
[1];
8539 expected_reg
= hash_find (reg_hash
,
8540 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8544 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8546 if (i
.base_reg
!= expected_reg
8548 || operand_type_check (i
.types
[this_operand
], disp
))
8550 /* The second memory operand must have the same size as
8554 && !((addr_mode
== CODE_64BIT
8555 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8556 || (addr_mode
== CODE_32BIT
8557 ? i
.base_reg
->reg_type
.bitfield
.reg32
8558 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8561 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8563 intel_syntax
? '[' : '(',
8565 expected_reg
->reg_name
,
8566 intel_syntax
? ']' : ')');
8573 as_bad (_("`%s' is not a valid %s expression"),
8574 operand_string
, kind
);
8579 if (addr_mode
!= CODE_16BIT
)
8581 /* 32-bit/64-bit checks. */
8583 && (addr_mode
== CODE_64BIT
8584 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8585 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8587 || (i
.base_reg
->reg_num
8588 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8590 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8591 && !i
.index_reg
->reg_type
.bitfield
.regymm
8592 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8593 && ((addr_mode
== CODE_64BIT
8594 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8595 || i
.index_reg
->reg_num
== RegRiz
)
8596 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8597 || i
.index_reg
->reg_num
== RegEiz
))
8598 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8601 /* bndmk, bndldx, and bndstx have special restrictions. */
8602 if (current_templates
->start
->base_opcode
== 0xf30f1b
8603 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
8605 /* They cannot use RIP-relative addressing. */
8606 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegRip
)
8608 as_bad (_("`%s' cannot be used here"), operand_string
);
8612 /* bndldx and bndstx ignore their scale factor. */
8613 if (current_templates
->start
->base_opcode
!= 0xf30f1b
8614 && i
.log2_scale_factor
)
8615 as_warn (_("register scaling is being ignored here"));
8620 /* 16-bit checks. */
8622 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8623 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8625 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8626 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8628 && i
.base_reg
->reg_num
< 6
8629 && i
.index_reg
->reg_num
>= 6
8630 && i
.log2_scale_factor
== 0))))
8637 /* Handle vector immediates. */
8640 RC_SAE_immediate (const char *imm_start
)
8642 unsigned int match_found
, j
;
8643 const char *pstr
= imm_start
;
8651 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8653 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8657 rc_op
.type
= RC_NamesTable
[j
].type
;
8658 rc_op
.operand
= this_operand
;
8659 i
.rounding
= &rc_op
;
8663 as_bad (_("duplicated `%s'"), imm_start
);
8666 pstr
+= RC_NamesTable
[j
].len
;
8676 as_bad (_("Missing '}': '%s'"), imm_start
);
8679 /* RC/SAE immediate string should contain nothing more. */;
8682 as_bad (_("Junk after '}': '%s'"), imm_start
);
8686 exp
= &im_expressions
[i
.imm_operands
++];
8687 i
.op
[this_operand
].imms
= exp
;
8689 exp
->X_op
= O_constant
;
8690 exp
->X_add_number
= 0;
8691 exp
->X_add_symbol
= (symbolS
*) 0;
8692 exp
->X_op_symbol
= (symbolS
*) 0;
8694 i
.types
[this_operand
].bitfield
.imm8
= 1;
8698 /* Only string instructions can have a second memory operand, so
8699 reduce current_templates to just those if it contains any. */
8701 maybe_adjust_templates (void)
8703 const insn_template
*t
;
8705 gas_assert (i
.mem_operands
== 1);
8707 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
8708 if (t
->opcode_modifier
.isstring
)
8711 if (t
< current_templates
->end
)
8713 static templates aux_templates
;
8714 bfd_boolean recheck
;
8716 aux_templates
.start
= t
;
8717 for (; t
< current_templates
->end
; ++t
)
8718 if (!t
->opcode_modifier
.isstring
)
8720 aux_templates
.end
= t
;
8722 /* Determine whether to re-check the first memory operand. */
8723 recheck
= (aux_templates
.start
!= current_templates
->start
8724 || t
!= current_templates
->end
);
8726 current_templates
= &aux_templates
;
8731 if (i
.memop1_string
!= NULL
8732 && i386_index_check (i
.memop1_string
) == 0)
8741 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8745 i386_att_operand (char *operand_string
)
8749 char *op_string
= operand_string
;
8751 if (is_space_char (*op_string
))
8754 /* We check for an absolute prefix (differentiating,
8755 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8756 if (*op_string
== ABSOLUTE_PREFIX
)
8759 if (is_space_char (*op_string
))
8761 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8764 /* Check if operand is a register. */
8765 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8767 i386_operand_type temp
;
8769 /* Check for a segment override by searching for ':' after a
8770 segment register. */
8772 if (is_space_char (*op_string
))
8774 if (*op_string
== ':'
8775 && (r
->reg_type
.bitfield
.sreg2
8776 || r
->reg_type
.bitfield
.sreg3
))
8781 i
.seg
[i
.mem_operands
] = &es
;
8784 i
.seg
[i
.mem_operands
] = &cs
;
8787 i
.seg
[i
.mem_operands
] = &ss
;
8790 i
.seg
[i
.mem_operands
] = &ds
;
8793 i
.seg
[i
.mem_operands
] = &fs
;
8796 i
.seg
[i
.mem_operands
] = &gs
;
8800 /* Skip the ':' and whitespace. */
8802 if (is_space_char (*op_string
))
8805 if (!is_digit_char (*op_string
)
8806 && !is_identifier_char (*op_string
)
8807 && *op_string
!= '('
8808 && *op_string
!= ABSOLUTE_PREFIX
)
8810 as_bad (_("bad memory operand `%s'"), op_string
);
8813 /* Handle case of %es:*foo. */
8814 if (*op_string
== ABSOLUTE_PREFIX
)
8817 if (is_space_char (*op_string
))
8819 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8821 goto do_memory_reference
;
8824 /* Handle vector operations. */
8825 if (*op_string
== '{')
8827 op_string
= check_VecOperations (op_string
, NULL
);
8828 if (op_string
== NULL
)
8834 as_bad (_("junk `%s' after register"), op_string
);
8838 temp
.bitfield
.baseindex
= 0;
8839 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8841 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8842 i
.op
[this_operand
].regs
= r
;
8845 else if (*op_string
== REGISTER_PREFIX
)
8847 as_bad (_("bad register name `%s'"), op_string
);
8850 else if (*op_string
== IMMEDIATE_PREFIX
)
8853 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8855 as_bad (_("immediate operand illegal with absolute jump"));
8858 if (!i386_immediate (op_string
))
8861 else if (RC_SAE_immediate (operand_string
))
8863 /* If it is a RC or SAE immediate, do nothing. */
8866 else if (is_digit_char (*op_string
)
8867 || is_identifier_char (*op_string
)
8868 || *op_string
== '"'
8869 || *op_string
== '(')
8871 /* This is a memory reference of some sort. */
8874 /* Start and end of displacement string expression (if found). */
8875 char *displacement_string_start
;
8876 char *displacement_string_end
;
8879 do_memory_reference
:
8880 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
8882 if ((i
.mem_operands
== 1
8883 && !current_templates
->start
->opcode_modifier
.isstring
)
8884 || i
.mem_operands
== 2)
8886 as_bad (_("too many memory references for `%s'"),
8887 current_templates
->start
->name
);
8891 /* Check for base index form. We detect the base index form by
8892 looking for an ')' at the end of the operand, searching
8893 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8895 base_string
= op_string
+ strlen (op_string
);
8897 /* Handle vector operations. */
8898 vop_start
= strchr (op_string
, '{');
8899 if (vop_start
&& vop_start
< base_string
)
8901 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8903 base_string
= vop_start
;
8907 if (is_space_char (*base_string
))
8910 /* If we only have a displacement, set-up for it to be parsed later. */
8911 displacement_string_start
= op_string
;
8912 displacement_string_end
= base_string
+ 1;
8914 if (*base_string
== ')')
8917 unsigned int parens_balanced
= 1;
8918 /* We've already checked that the number of left & right ()'s are
8919 equal, so this loop will not be infinite. */
8923 if (*base_string
== ')')
8925 if (*base_string
== '(')
8928 while (parens_balanced
);
8930 temp_string
= base_string
;
8932 /* Skip past '(' and whitespace. */
8934 if (is_space_char (*base_string
))
8937 if (*base_string
== ','
8938 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8941 displacement_string_end
= temp_string
;
8943 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8947 base_string
= end_op
;
8948 if (is_space_char (*base_string
))
8952 /* There may be an index reg or scale factor here. */
8953 if (*base_string
== ',')
8956 if (is_space_char (*base_string
))
8959 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8962 base_string
= end_op
;
8963 if (is_space_char (*base_string
))
8965 if (*base_string
== ',')
8968 if (is_space_char (*base_string
))
8971 else if (*base_string
!= ')')
8973 as_bad (_("expecting `,' or `)' "
8974 "after index register in `%s'"),
8979 else if (*base_string
== REGISTER_PREFIX
)
8981 end_op
= strchr (base_string
, ',');
8984 as_bad (_("bad register name `%s'"), base_string
);
8988 /* Check for scale factor. */
8989 if (*base_string
!= ')')
8991 char *end_scale
= i386_scale (base_string
);
8996 base_string
= end_scale
;
8997 if (is_space_char (*base_string
))
8999 if (*base_string
!= ')')
9001 as_bad (_("expecting `)' "
9002 "after scale factor in `%s'"),
9007 else if (!i
.index_reg
)
9009 as_bad (_("expecting index register or scale factor "
9010 "after `,'; got '%c'"),
9015 else if (*base_string
!= ')')
9017 as_bad (_("expecting `,' or `)' "
9018 "after base register in `%s'"),
9023 else if (*base_string
== REGISTER_PREFIX
)
9025 end_op
= strchr (base_string
, ',');
9028 as_bad (_("bad register name `%s'"), base_string
);
9033 /* If there's an expression beginning the operand, parse it,
9034 assuming displacement_string_start and
9035 displacement_string_end are meaningful. */
9036 if (displacement_string_start
!= displacement_string_end
)
9038 if (!i386_displacement (displacement_string_start
,
9039 displacement_string_end
))
9043 /* Special case for (%dx) while doing input/output op. */
9045 && operand_type_equal (&i
.base_reg
->reg_type
,
9046 ®16_inoutportreg
)
9048 && i
.log2_scale_factor
== 0
9049 && i
.seg
[i
.mem_operands
] == 0
9050 && !operand_type_check (i
.types
[this_operand
], disp
))
9052 i
.types
[this_operand
] = inoutportreg
;
9056 if (i386_index_check (operand_string
) == 0)
9058 i
.types
[this_operand
].bitfield
.mem
= 1;
9059 if (i
.mem_operands
== 0)
9060 i
.memop1_string
= xstrdup (operand_string
);
9065 /* It's not a memory operand; argh! */
9066 as_bad (_("invalid char %s beginning operand %d `%s'"),
9067 output_invalid (*op_string
),
9072 return 1; /* Normal return. */
9075 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9076 that an rs_machine_dependent frag may reach. */
9079 i386_frag_max_var (fragS
*frag
)
9081 /* The only relaxable frags are for jumps.
9082 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9083 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9084 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9087 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9089 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9091 /* STT_GNU_IFUNC symbol must go through PLT. */
9092 if ((symbol_get_bfdsym (fr_symbol
)->flags
9093 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9096 if (!S_IS_EXTERNAL (fr_symbol
))
9097 /* Symbol may be weak or local. */
9098 return !S_IS_WEAK (fr_symbol
);
9100 /* Global symbols with non-default visibility can't be preempted. */
9101 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9104 if (fr_var
!= NO_RELOC
)
9105 switch ((enum bfd_reloc_code_real
) fr_var
)
9107 case BFD_RELOC_386_PLT32
:
9108 case BFD_RELOC_X86_64_PLT32
:
9109 /* Symbol with PLT relocatin may be preempted. */
9115 /* Global symbols with default visibility in a shared library may be
9116 preempted by another definition. */
9121 /* md_estimate_size_before_relax()
9123 Called just before relax() for rs_machine_dependent frags. The x86
9124 assembler uses these frags to handle variable size jump
9127 Any symbol that is now undefined will not become defined.
9128 Return the correct fr_subtype in the frag.
9129 Return the initial "guess for variable size of frag" to caller.
9130 The guess is actually the growth beyond the fixed part. Whatever
9131 we do to grow the fixed or variable part contributes to our
9135 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9137 /* We've already got fragP->fr_subtype right; all we have to do is
9138 check for un-relaxable symbols. On an ELF system, we can't relax
9139 an externally visible symbol, because it may be overridden by a
9141 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9142 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9144 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9147 #if defined (OBJ_COFF) && defined (TE_PE)
9148 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9149 && S_IS_WEAK (fragP
->fr_symbol
))
9153 /* Symbol is undefined in this segment, or we need to keep a
9154 reloc so that weak symbols can be overridden. */
9155 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9156 enum bfd_reloc_code_real reloc_type
;
9157 unsigned char *opcode
;
9160 if (fragP
->fr_var
!= NO_RELOC
)
9161 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9163 reloc_type
= BFD_RELOC_16_PCREL
;
9165 reloc_type
= BFD_RELOC_32_PCREL
;
9167 old_fr_fix
= fragP
->fr_fix
;
9168 opcode
= (unsigned char *) fragP
->fr_opcode
;
9170 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9173 /* Make jmp (0xeb) a (d)word displacement jump. */
9175 fragP
->fr_fix
+= size
;
9176 fix_new (fragP
, old_fr_fix
, size
,
9178 fragP
->fr_offset
, 1,
9184 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9186 /* Negate the condition, and branch past an
9187 unconditional jump. */
9190 /* Insert an unconditional jump. */
9192 /* We added two extra opcode bytes, and have a two byte
9194 fragP
->fr_fix
+= 2 + 2;
9195 fix_new (fragP
, old_fr_fix
+ 2, 2,
9197 fragP
->fr_offset
, 1,
9204 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9209 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9211 fragP
->fr_offset
, 1,
9213 fixP
->fx_signed
= 1;
9217 /* This changes the byte-displacement jump 0x7N
9218 to the (d)word-displacement jump 0x0f,0x8N. */
9219 opcode
[1] = opcode
[0] + 0x10;
9220 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9221 /* We've added an opcode byte. */
9222 fragP
->fr_fix
+= 1 + size
;
9223 fix_new (fragP
, old_fr_fix
+ 1, size
,
9225 fragP
->fr_offset
, 1,
9230 BAD_CASE (fragP
->fr_subtype
);
9234 return fragP
->fr_fix
- old_fr_fix
;
9237 /* Guess size depending on current relax state. Initially the relax
9238 state will correspond to a short jump and we return 1, because
9239 the variable part of the frag (the branch offset) is one byte
9240 long. However, we can relax a section more than once and in that
9241 case we must either set fr_subtype back to the unrelaxed state,
9242 or return the value for the appropriate branch. */
9243 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9246 /* Called after relax() is finished.
9248 In: Address of frag.
9249 fr_type == rs_machine_dependent.
9250 fr_subtype is what the address relaxed to.
9252 Out: Any fixSs and constants are set up.
9253 Caller will turn frag into a ".space 0". */
9256 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9259 unsigned char *opcode
;
9260 unsigned char *where_to_put_displacement
= NULL
;
9261 offsetT target_address
;
9262 offsetT opcode_address
;
9263 unsigned int extension
= 0;
9264 offsetT displacement_from_opcode_start
;
9266 opcode
= (unsigned char *) fragP
->fr_opcode
;
9268 /* Address we want to reach in file space. */
9269 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9271 /* Address opcode resides at in file space. */
9272 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9274 /* Displacement from opcode start to fill into instruction. */
9275 displacement_from_opcode_start
= target_address
- opcode_address
;
9277 if ((fragP
->fr_subtype
& BIG
) == 0)
9279 /* Don't have to change opcode. */
9280 extension
= 1; /* 1 opcode + 1 displacement */
9281 where_to_put_displacement
= &opcode
[1];
9285 if (no_cond_jump_promotion
9286 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9287 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9288 _("long jump required"));
9290 switch (fragP
->fr_subtype
)
9292 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9293 extension
= 4; /* 1 opcode + 4 displacement */
9295 where_to_put_displacement
= &opcode
[1];
9298 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9299 extension
= 2; /* 1 opcode + 2 displacement */
9301 where_to_put_displacement
= &opcode
[1];
9304 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9305 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9306 extension
= 5; /* 2 opcode + 4 displacement */
9307 opcode
[1] = opcode
[0] + 0x10;
9308 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9309 where_to_put_displacement
= &opcode
[2];
9312 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9313 extension
= 3; /* 2 opcode + 2 displacement */
9314 opcode
[1] = opcode
[0] + 0x10;
9315 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9316 where_to_put_displacement
= &opcode
[2];
9319 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9324 where_to_put_displacement
= &opcode
[3];
9328 BAD_CASE (fragP
->fr_subtype
);
9333 /* If size if less then four we are sure that the operand fits,
9334 but if it's 4, then it could be that the displacement is larger
9336 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9338 && ((addressT
) (displacement_from_opcode_start
- extension
9339 + ((addressT
) 1 << 31))
9340 > (((addressT
) 2 << 31) - 1)))
9342 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9343 _("jump target out of range"));
9344 /* Make us emit 0. */
9345 displacement_from_opcode_start
= extension
;
9347 /* Now put displacement after opcode. */
9348 md_number_to_chars ((char *) where_to_put_displacement
,
9349 (valueT
) (displacement_from_opcode_start
- extension
),
9350 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9351 fragP
->fr_fix
+= extension
;
9354 /* Apply a fixup (fixP) to segment data, once it has been determined
9355 by our caller that we have all the info we need to fix it up.
9357 Parameter valP is the pointer to the value of the bits.
9359 On the 386, immediates, displacements, and data pointers are all in
9360 the same (little-endian) format, so we don't need to care about which
9364 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9366 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9367 valueT value
= *valP
;
9369 #if !defined (TE_Mach)
9372 switch (fixP
->fx_r_type
)
9378 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9381 case BFD_RELOC_X86_64_32S
:
9382 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9385 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9388 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9393 if (fixP
->fx_addsy
!= NULL
9394 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9395 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9396 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9397 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9398 && !use_rela_relocations
)
9400 /* This is a hack. There should be a better way to handle this.
9401 This covers for the fact that bfd_install_relocation will
9402 subtract the current location (for partial_inplace, PC relative
9403 relocations); see more below. */
9407 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9410 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9412 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9415 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9418 || (symbol_section_p (fixP
->fx_addsy
)
9419 && sym_seg
!= absolute_section
))
9420 && !generic_force_reloc (fixP
))
9422 /* Yes, we add the values in twice. This is because
9423 bfd_install_relocation subtracts them out again. I think
9424 bfd_install_relocation is broken, but I don't dare change
9426 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9430 #if defined (OBJ_COFF) && defined (TE_PE)
9431 /* For some reason, the PE format does not store a
9432 section address offset for a PC relative symbol. */
9433 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9434 || S_IS_WEAK (fixP
->fx_addsy
))
9435 value
+= md_pcrel_from (fixP
);
9438 #if defined (OBJ_COFF) && defined (TE_PE)
9439 if (fixP
->fx_addsy
!= NULL
9440 && S_IS_WEAK (fixP
->fx_addsy
)
9441 /* PR 16858: Do not modify weak function references. */
9442 && ! fixP
->fx_pcrel
)
9444 #if !defined (TE_PEP)
9445 /* For x86 PE weak function symbols are neither PC-relative
9446 nor do they set S_IS_FUNCTION. So the only reliable way
9447 to detect them is to check the flags of their containing
9449 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9450 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9454 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9458 /* Fix a few things - the dynamic linker expects certain values here,
9459 and we must not disappoint it. */
9460 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9461 if (IS_ELF
&& fixP
->fx_addsy
)
9462 switch (fixP
->fx_r_type
)
9464 case BFD_RELOC_386_PLT32
:
9465 case BFD_RELOC_X86_64_PLT32
:
9466 /* Make the jump instruction point to the address of the operand. At
9467 runtime we merely add the offset to the actual PLT entry. */
9471 case BFD_RELOC_386_TLS_GD
:
9472 case BFD_RELOC_386_TLS_LDM
:
9473 case BFD_RELOC_386_TLS_IE_32
:
9474 case BFD_RELOC_386_TLS_IE
:
9475 case BFD_RELOC_386_TLS_GOTIE
:
9476 case BFD_RELOC_386_TLS_GOTDESC
:
9477 case BFD_RELOC_X86_64_TLSGD
:
9478 case BFD_RELOC_X86_64_TLSLD
:
9479 case BFD_RELOC_X86_64_GOTTPOFF
:
9480 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9481 value
= 0; /* Fully resolved at runtime. No addend. */
9483 case BFD_RELOC_386_TLS_LE
:
9484 case BFD_RELOC_386_TLS_LDO_32
:
9485 case BFD_RELOC_386_TLS_LE_32
:
9486 case BFD_RELOC_X86_64_DTPOFF32
:
9487 case BFD_RELOC_X86_64_DTPOFF64
:
9488 case BFD_RELOC_X86_64_TPOFF32
:
9489 case BFD_RELOC_X86_64_TPOFF64
:
9490 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9493 case BFD_RELOC_386_TLS_DESC_CALL
:
9494 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9495 value
= 0; /* Fully resolved at runtime. No addend. */
9496 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9500 case BFD_RELOC_VTABLE_INHERIT
:
9501 case BFD_RELOC_VTABLE_ENTRY
:
9508 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9510 #endif /* !defined (TE_Mach) */
9512 /* Are we finished with this relocation now? */
9513 if (fixP
->fx_addsy
== NULL
)
9515 #if defined (OBJ_COFF) && defined (TE_PE)
9516 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9519 /* Remember value for tc_gen_reloc. */
9520 fixP
->fx_addnumber
= value
;
9521 /* Clear out the frag for now. */
9525 else if (use_rela_relocations
)
9527 fixP
->fx_no_overflow
= 1;
9528 /* Remember value for tc_gen_reloc. */
9529 fixP
->fx_addnumber
= value
;
9533 md_number_to_chars (p
, value
, fixP
->fx_size
);
9537 md_atof (int type
, char *litP
, int *sizeP
)
9539 /* This outputs the LITTLENUMs in REVERSE order;
9540 in accord with the bigendian 386. */
9541 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9544 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9547 output_invalid (int c
)
9550 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9553 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9554 "(0x%x)", (unsigned char) c
);
9555 return output_invalid_buf
;
9558 /* REG_STRING starts *before* REGISTER_PREFIX. */
9560 static const reg_entry
*
9561 parse_real_register (char *reg_string
, char **end_op
)
9563 char *s
= reg_string
;
9565 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9568 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9569 if (*s
== REGISTER_PREFIX
)
9572 if (is_space_char (*s
))
9576 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9578 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9579 return (const reg_entry
*) NULL
;
9583 /* For naked regs, make sure that we are not dealing with an identifier.
9584 This prevents confusing an identifier like `eax_var' with register
9586 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9587 return (const reg_entry
*) NULL
;
9591 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9593 /* Handle floating point regs, allowing spaces in the (i) part. */
9594 if (r
== i386_regtab
/* %st is first entry of table */)
9596 if (is_space_char (*s
))
9601 if (is_space_char (*s
))
9603 if (*s
>= '0' && *s
<= '7')
9607 if (is_space_char (*s
))
9612 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9617 /* We have "%st(" then garbage. */
9618 return (const reg_entry
*) NULL
;
9622 if (r
== NULL
|| allow_pseudo_reg
)
9625 if (operand_type_all_zero (&r
->reg_type
))
9626 return (const reg_entry
*) NULL
;
9628 if ((r
->reg_type
.bitfield
.reg32
9629 || r
->reg_type
.bitfield
.sreg3
9630 || r
->reg_type
.bitfield
.control
9631 || r
->reg_type
.bitfield
.debug
9632 || r
->reg_type
.bitfield
.test
)
9633 && !cpu_arch_flags
.bitfield
.cpui386
)
9634 return (const reg_entry
*) NULL
;
9636 if (r
->reg_type
.bitfield
.floatreg
9637 && !cpu_arch_flags
.bitfield
.cpu8087
9638 && !cpu_arch_flags
.bitfield
.cpu287
9639 && !cpu_arch_flags
.bitfield
.cpu387
)
9640 return (const reg_entry
*) NULL
;
9642 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpuregmmx
)
9643 return (const reg_entry
*) NULL
;
9645 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpuregxmm
)
9646 return (const reg_entry
*) NULL
;
9648 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuregymm
)
9649 return (const reg_entry
*) NULL
;
9651 if (r
->reg_type
.bitfield
.regzmm
&& !cpu_arch_flags
.bitfield
.cpuregzmm
)
9652 return (const reg_entry
*) NULL
;
9654 if (r
->reg_type
.bitfield
.regmask
9655 && !cpu_arch_flags
.bitfield
.cpuregmask
)
9656 return (const reg_entry
*) NULL
;
9658 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9659 if (!allow_index_reg
9660 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9661 return (const reg_entry
*) NULL
;
9663 /* Upper 16 vector register is only available with VREX in 64bit
9665 if ((r
->reg_flags
& RegVRex
))
9667 if (!cpu_arch_flags
.bitfield
.cpuvrex
9668 || flag_code
!= CODE_64BIT
)
9669 return (const reg_entry
*) NULL
;
9674 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9675 || r
->reg_type
.bitfield
.reg64
)
9676 && (!cpu_arch_flags
.bitfield
.cpulm
9677 || !operand_type_equal (&r
->reg_type
, &control
))
9678 && flag_code
!= CODE_64BIT
)
9679 return (const reg_entry
*) NULL
;
9681 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9682 return (const reg_entry
*) NULL
;
9687 /* REG_STRING starts *before* REGISTER_PREFIX. */
9689 static const reg_entry
*
9690 parse_register (char *reg_string
, char **end_op
)
9694 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9695 r
= parse_real_register (reg_string
, end_op
);
9700 char *save
= input_line_pointer
;
9704 input_line_pointer
= reg_string
;
9705 c
= get_symbol_name (®_string
);
9706 symbolP
= symbol_find (reg_string
);
9707 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9709 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9711 know (e
->X_op
== O_register
);
9712 know (e
->X_add_number
>= 0
9713 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9714 r
= i386_regtab
+ e
->X_add_number
;
9715 if ((r
->reg_flags
& RegVRex
))
9717 *end_op
= input_line_pointer
;
9719 *input_line_pointer
= c
;
9720 input_line_pointer
= save
;
9726 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9729 char *end
= input_line_pointer
;
9732 r
= parse_register (name
, &input_line_pointer
);
9733 if (r
&& end
<= input_line_pointer
)
9735 *nextcharP
= *input_line_pointer
;
9736 *input_line_pointer
= 0;
9737 e
->X_op
= O_register
;
9738 e
->X_add_number
= r
- i386_regtab
;
9741 input_line_pointer
= end
;
9743 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9747 md_operand (expressionS
*e
)
9752 switch (*input_line_pointer
)
9754 case REGISTER_PREFIX
:
9755 r
= parse_real_register (input_line_pointer
, &end
);
9758 e
->X_op
= O_register
;
9759 e
->X_add_number
= r
- i386_regtab
;
9760 input_line_pointer
= end
;
9765 gas_assert (intel_syntax
);
9766 end
= input_line_pointer
++;
9768 if (*input_line_pointer
== ']')
9770 ++input_line_pointer
;
9771 e
->X_op_symbol
= make_expr_symbol (e
);
9772 e
->X_add_symbol
= NULL
;
9773 e
->X_add_number
= 0;
9779 input_line_pointer
= end
;
9786 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9787 const char *md_shortopts
= "kVQ:sqn";
9789 const char *md_shortopts
= "qn";
9792 #define OPTION_32 (OPTION_MD_BASE + 0)
9793 #define OPTION_64 (OPTION_MD_BASE + 1)
9794 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9795 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9796 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9797 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9798 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9799 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9800 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9801 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9802 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9803 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9804 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9805 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9806 #define OPTION_X32 (OPTION_MD_BASE + 14)
9807 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9808 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9809 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9810 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9811 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9812 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9813 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9814 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9815 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9816 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9817 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
9819 struct option md_longopts
[] =
9821 {"32", no_argument
, NULL
, OPTION_32
},
9822 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9823 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9824 {"64", no_argument
, NULL
, OPTION_64
},
9826 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9827 {"x32", no_argument
, NULL
, OPTION_X32
},
9828 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
9830 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9831 {"march", required_argument
, NULL
, OPTION_MARCH
},
9832 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9833 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9834 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9835 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9836 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9837 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9838 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9839 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9840 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9841 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9842 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9843 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9844 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9845 # if defined (TE_PE) || defined (TE_PEP)
9846 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9848 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
9849 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
9850 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
9851 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9852 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
9853 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
9854 {NULL
, no_argument
, NULL
, 0}
9856 size_t md_longopts_size
= sizeof (md_longopts
);
9859 md_parse_option (int c
, const char *arg
)
9862 char *arch
, *next
, *saved
;
9867 optimize_align_code
= 0;
9874 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9875 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9876 should be emitted or not. FIXME: Not implemented. */
9880 /* -V: SVR4 argument to print version ID. */
9882 print_version_id ();
9885 /* -k: Ignore for FreeBSD compatibility. */
9890 /* -s: On i386 Solaris, this tells the native assembler to use
9891 .stab instead of .stab.excl. We always use .stab anyhow. */
9894 case OPTION_MSHARED
:
9898 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9899 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9902 const char **list
, **l
;
9904 list
= bfd_target_list ();
9905 for (l
= list
; *l
!= NULL
; l
++)
9906 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9907 || strcmp (*l
, "coff-x86-64") == 0
9908 || strcmp (*l
, "pe-x86-64") == 0
9909 || strcmp (*l
, "pei-x86-64") == 0
9910 || strcmp (*l
, "mach-o-x86-64") == 0)
9912 default_arch
= "x86_64";
9916 as_fatal (_("no compiled in support for x86_64"));
9922 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9926 const char **list
, **l
;
9928 list
= bfd_target_list ();
9929 for (l
= list
; *l
!= NULL
; l
++)
9930 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9932 default_arch
= "x86_64:32";
9936 as_fatal (_("no compiled in support for 32bit x86_64"));
9940 as_fatal (_("32bit x86_64 is only supported for ELF"));
9945 default_arch
= "i386";
9949 #ifdef SVR4_COMMENT_CHARS
9954 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
9956 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9960 i386_comment_chars
= n
;
9966 saved
= xstrdup (arg
);
9968 /* Allow -march=+nosse. */
9974 as_fatal (_("invalid -march= option: `%s'"), arg
);
9975 next
= strchr (arch
, '+');
9978 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9980 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9983 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9986 cpu_arch_name
= cpu_arch
[j
].name
;
9987 cpu_sub_arch_name
= NULL
;
9988 cpu_arch_flags
= cpu_arch
[j
].flags
;
9989 cpu_arch_isa
= cpu_arch
[j
].type
;
9990 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9991 if (!cpu_arch_tune_set
)
9993 cpu_arch_tune
= cpu_arch_isa
;
9994 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9998 else if (*cpu_arch
[j
].name
== '.'
9999 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
10001 /* ISA entension. */
10002 i386_cpu_flags flags
;
10004 flags
= cpu_flags_or (cpu_arch_flags
,
10005 cpu_arch
[j
].flags
);
10007 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10009 if (cpu_sub_arch_name
)
10011 char *name
= cpu_sub_arch_name
;
10012 cpu_sub_arch_name
= concat (name
,
10014 (const char *) NULL
);
10018 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
10019 cpu_arch_flags
= flags
;
10020 cpu_arch_isa_flags
= flags
;
10026 if (j
>= ARRAY_SIZE (cpu_arch
))
10028 /* Disable an ISA entension. */
10029 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10030 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
10032 i386_cpu_flags flags
;
10034 flags
= cpu_flags_and_not (cpu_arch_flags
,
10035 cpu_noarch
[j
].flags
);
10036 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10038 if (cpu_sub_arch_name
)
10040 char *name
= cpu_sub_arch_name
;
10041 cpu_sub_arch_name
= concat (arch
,
10042 (const char *) NULL
);
10046 cpu_sub_arch_name
= xstrdup (arch
);
10047 cpu_arch_flags
= flags
;
10048 cpu_arch_isa_flags
= flags
;
10053 if (j
>= ARRAY_SIZE (cpu_noarch
))
10054 j
= ARRAY_SIZE (cpu_arch
);
10057 if (j
>= ARRAY_SIZE (cpu_arch
))
10058 as_fatal (_("invalid -march= option: `%s'"), arg
);
10062 while (next
!= NULL
);
10068 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10069 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10071 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
10073 cpu_arch_tune_set
= 1;
10074 cpu_arch_tune
= cpu_arch
[j
].type
;
10075 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10079 if (j
>= ARRAY_SIZE (cpu_arch
))
10080 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10083 case OPTION_MMNEMONIC
:
10084 if (strcasecmp (arg
, "att") == 0)
10085 intel_mnemonic
= 0;
10086 else if (strcasecmp (arg
, "intel") == 0)
10087 intel_mnemonic
= 1;
10089 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10092 case OPTION_MSYNTAX
:
10093 if (strcasecmp (arg
, "att") == 0)
10095 else if (strcasecmp (arg
, "intel") == 0)
10098 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10101 case OPTION_MINDEX_REG
:
10102 allow_index_reg
= 1;
10105 case OPTION_MNAKED_REG
:
10106 allow_naked_reg
= 1;
10109 case OPTION_MOLD_GCC
:
10113 case OPTION_MSSE2AVX
:
10117 case OPTION_MSSE_CHECK
:
10118 if (strcasecmp (arg
, "error") == 0)
10119 sse_check
= check_error
;
10120 else if (strcasecmp (arg
, "warning") == 0)
10121 sse_check
= check_warning
;
10122 else if (strcasecmp (arg
, "none") == 0)
10123 sse_check
= check_none
;
10125 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10128 case OPTION_MOPERAND_CHECK
:
10129 if (strcasecmp (arg
, "error") == 0)
10130 operand_check
= check_error
;
10131 else if (strcasecmp (arg
, "warning") == 0)
10132 operand_check
= check_warning
;
10133 else if (strcasecmp (arg
, "none") == 0)
10134 operand_check
= check_none
;
10136 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10139 case OPTION_MAVXSCALAR
:
10140 if (strcasecmp (arg
, "128") == 0)
10141 avxscalar
= vex128
;
10142 else if (strcasecmp (arg
, "256") == 0)
10143 avxscalar
= vex256
;
10145 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10148 case OPTION_MADD_BND_PREFIX
:
10149 add_bnd_prefix
= 1;
10152 case OPTION_MEVEXLIG
:
10153 if (strcmp (arg
, "128") == 0)
10154 evexlig
= evexl128
;
10155 else if (strcmp (arg
, "256") == 0)
10156 evexlig
= evexl256
;
10157 else if (strcmp (arg
, "512") == 0)
10158 evexlig
= evexl512
;
10160 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10163 case OPTION_MEVEXRCIG
:
10164 if (strcmp (arg
, "rne") == 0)
10166 else if (strcmp (arg
, "rd") == 0)
10168 else if (strcmp (arg
, "ru") == 0)
10170 else if (strcmp (arg
, "rz") == 0)
10173 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10176 case OPTION_MEVEXWIG
:
10177 if (strcmp (arg
, "0") == 0)
10179 else if (strcmp (arg
, "1") == 0)
10182 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10185 # if defined (TE_PE) || defined (TE_PEP)
10186 case OPTION_MBIG_OBJ
:
10191 case OPTION_MOMIT_LOCK_PREFIX
:
10192 if (strcasecmp (arg
, "yes") == 0)
10193 omit_lock_prefix
= 1;
10194 else if (strcasecmp (arg
, "no") == 0)
10195 omit_lock_prefix
= 0;
10197 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10200 case OPTION_MFENCE_AS_LOCK_ADD
:
10201 if (strcasecmp (arg
, "yes") == 0)
10203 else if (strcasecmp (arg
, "no") == 0)
10206 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10209 case OPTION_MRELAX_RELOCATIONS
:
10210 if (strcasecmp (arg
, "yes") == 0)
10211 generate_relax_relocations
= 1;
10212 else if (strcasecmp (arg
, "no") == 0)
10213 generate_relax_relocations
= 0;
10215 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10218 case OPTION_MAMD64
:
10222 case OPTION_MINTEL64
:
10232 #define MESSAGE_TEMPLATE \
10236 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10237 int *left_p
, const char *name
, int len
)
10239 int size
= sizeof (MESSAGE_TEMPLATE
);
10240 int left
= *left_p
;
10242 /* Reserve 2 spaces for ", " or ",\0" */
10245 /* Check if there is any room. */
10253 p
= mempcpy (p
, name
, len
);
10257 /* Output the current message now and start a new one. */
10260 fprintf (stream
, "%s\n", message
);
10262 left
= size
- (start
- message
) - len
- 2;
10264 gas_assert (left
>= 0);
10266 p
= mempcpy (p
, name
, len
);
10274 show_arch (FILE *stream
, int ext
, int check
)
10276 static char message
[] = MESSAGE_TEMPLATE
;
10277 char *start
= message
+ 27;
10279 int size
= sizeof (MESSAGE_TEMPLATE
);
10286 left
= size
- (start
- message
);
10287 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10289 /* Should it be skipped? */
10290 if (cpu_arch
[j
].skip
)
10293 name
= cpu_arch
[j
].name
;
10294 len
= cpu_arch
[j
].len
;
10297 /* It is an extension. Skip if we aren't asked to show it. */
10308 /* It is an processor. Skip if we show only extension. */
10311 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10313 /* It is an impossible processor - skip. */
10317 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10320 /* Display disabled extensions. */
10322 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10324 name
= cpu_noarch
[j
].name
;
10325 len
= cpu_noarch
[j
].len
;
10326 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10331 fprintf (stream
, "%s\n", message
);
10335 md_show_usage (FILE *stream
)
10337 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10338 fprintf (stream
, _("\
10340 -V print assembler version number\n\
10343 fprintf (stream
, _("\
10344 -n Do not optimize code alignment\n\
10345 -q quieten some warnings\n"));
10346 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10347 fprintf (stream
, _("\
10350 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10351 || defined (TE_PE) || defined (TE_PEP))
10352 fprintf (stream
, _("\
10353 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10355 #ifdef SVR4_COMMENT_CHARS
10356 fprintf (stream
, _("\
10357 --divide do not treat `/' as a comment character\n"));
10359 fprintf (stream
, _("\
10360 --divide ignored\n"));
10362 fprintf (stream
, _("\
10363 -march=CPU[,+EXTENSION...]\n\
10364 generate code for CPU and EXTENSION, CPU is one of:\n"));
10365 show_arch (stream
, 0, 1);
10366 fprintf (stream
, _("\
10367 EXTENSION is combination of:\n"));
10368 show_arch (stream
, 1, 0);
10369 fprintf (stream
, _("\
10370 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10371 show_arch (stream
, 0, 0);
10372 fprintf (stream
, _("\
10373 -msse2avx encode SSE instructions with VEX prefix\n"));
10374 fprintf (stream
, _("\
10375 -msse-check=[none|error|warning]\n\
10376 check SSE instructions\n"));
10377 fprintf (stream
, _("\
10378 -moperand-check=[none|error|warning]\n\
10379 check operand combinations for validity\n"));
10380 fprintf (stream
, _("\
10381 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10383 fprintf (stream
, _("\
10384 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10386 fprintf (stream
, _("\
10387 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10388 for EVEX.W bit ignored instructions\n"));
10389 fprintf (stream
, _("\
10390 -mevexrcig=[rne|rd|ru|rz]\n\
10391 encode EVEX instructions with specific EVEX.RC value\n\
10392 for SAE-only ignored instructions\n"));
10393 fprintf (stream
, _("\
10394 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10395 fprintf (stream
, _("\
10396 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10397 fprintf (stream
, _("\
10398 -mindex-reg support pseudo index registers\n"));
10399 fprintf (stream
, _("\
10400 -mnaked-reg don't require `%%' prefix for registers\n"));
10401 fprintf (stream
, _("\
10402 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10403 fprintf (stream
, _("\
10404 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10405 fprintf (stream
, _("\
10406 -mshared disable branch optimization for shared code\n"));
10407 # if defined (TE_PE) || defined (TE_PEP)
10408 fprintf (stream
, _("\
10409 -mbig-obj generate big object files\n"));
10411 fprintf (stream
, _("\
10412 -momit-lock-prefix=[no|yes]\n\
10413 strip all lock prefixes\n"));
10414 fprintf (stream
, _("\
10415 -mfence-as-lock-add=[no|yes]\n\
10416 encode lfence, mfence and sfence as\n\
10417 lock addl $0x0, (%%{re}sp)\n"));
10418 fprintf (stream
, _("\
10419 -mrelax-relocations=[no|yes]\n\
10420 generate relax relocations\n"));
10421 fprintf (stream
, _("\
10422 -mamd64 accept only AMD64 ISA\n"));
10423 fprintf (stream
, _("\
10424 -mintel64 accept only Intel64 ISA\n"));
10427 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10428 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10429 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10431 /* Pick the target format to use. */
10434 i386_target_format (void)
10436 if (!strncmp (default_arch
, "x86_64", 6))
10438 update_code_flag (CODE_64BIT
, 1);
10439 if (default_arch
[6] == '\0')
10440 x86_elf_abi
= X86_64_ABI
;
10442 x86_elf_abi
= X86_64_X32_ABI
;
10444 else if (!strcmp (default_arch
, "i386"))
10445 update_code_flag (CODE_32BIT
, 1);
10446 else if (!strcmp (default_arch
, "iamcu"))
10448 update_code_flag (CODE_32BIT
, 1);
10449 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10451 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10452 cpu_arch_name
= "iamcu";
10453 cpu_sub_arch_name
= NULL
;
10454 cpu_arch_flags
= iamcu_flags
;
10455 cpu_arch_isa
= PROCESSOR_IAMCU
;
10456 cpu_arch_isa_flags
= iamcu_flags
;
10457 if (!cpu_arch_tune_set
)
10459 cpu_arch_tune
= cpu_arch_isa
;
10460 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10463 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
10464 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10468 as_fatal (_("unknown architecture"));
10470 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10471 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10472 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10473 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10475 switch (OUTPUT_FLAVOR
)
10477 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10478 case bfd_target_aout_flavour
:
10479 return AOUT_TARGET_FORMAT
;
10481 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10482 # if defined (TE_PE) || defined (TE_PEP)
10483 case bfd_target_coff_flavour
:
10484 if (flag_code
== CODE_64BIT
)
10485 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10488 # elif defined (TE_GO32)
10489 case bfd_target_coff_flavour
:
10490 return "coff-go32";
10492 case bfd_target_coff_flavour
:
10493 return "coff-i386";
10496 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10497 case bfd_target_elf_flavour
:
10499 const char *format
;
10501 switch (x86_elf_abi
)
10504 format
= ELF_TARGET_FORMAT
;
10507 use_rela_relocations
= 1;
10509 format
= ELF_TARGET_FORMAT64
;
10511 case X86_64_X32_ABI
:
10512 use_rela_relocations
= 1;
10514 disallow_64bit_reloc
= 1;
10515 format
= ELF_TARGET_FORMAT32
;
10518 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10520 if (x86_elf_abi
!= X86_64_ABI
)
10521 as_fatal (_("Intel L1OM is 64bit only"));
10522 return ELF_TARGET_L1OM_FORMAT
;
10524 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10526 if (x86_elf_abi
!= X86_64_ABI
)
10527 as_fatal (_("Intel K1OM is 64bit only"));
10528 return ELF_TARGET_K1OM_FORMAT
;
10530 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10532 if (x86_elf_abi
!= I386_ABI
)
10533 as_fatal (_("Intel MCU is 32bit only"));
10534 return ELF_TARGET_IAMCU_FORMAT
;
10540 #if defined (OBJ_MACH_O)
10541 case bfd_target_mach_o_flavour
:
10542 if (flag_code
== CODE_64BIT
)
10544 use_rela_relocations
= 1;
10546 return "mach-o-x86-64";
10549 return "mach-o-i386";
10557 #endif /* OBJ_MAYBE_ more than one */
10560 md_undefined_symbol (char *name
)
10562 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10563 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10564 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10565 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10569 if (symbol_find (name
))
10570 as_bad (_("GOT already in symbol table"));
10571 GOT_symbol
= symbol_new (name
, undefined_section
,
10572 (valueT
) 0, &zero_address_frag
);
10579 /* Round up a section size to the appropriate boundary. */
10582 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10584 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10585 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10587 /* For a.out, force the section size to be aligned. If we don't do
10588 this, BFD will align it for us, but it will not write out the
10589 final bytes of the section. This may be a bug in BFD, but it is
10590 easier to fix it here since that is how the other a.out targets
10594 align
= bfd_get_section_alignment (stdoutput
, segment
);
10595 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
10602 /* On the i386, PC-relative offsets are relative to the start of the
10603 next instruction. That is, the address of the offset, plus its
10604 size, since the offset is always the last part of the insn. */
10607 md_pcrel_from (fixS
*fixP
)
10609 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10615 s_bss (int ignore ATTRIBUTE_UNUSED
)
10619 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10621 obj_elf_section_change_hook ();
10623 temp
= get_absolute_expression ();
10624 subseg_set (bss_section
, (subsegT
) temp
);
10625 demand_empty_rest_of_line ();
10631 i386_validate_fix (fixS
*fixp
)
10633 if (fixp
->fx_subsy
)
10635 if (fixp
->fx_subsy
== GOT_symbol
)
10637 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10641 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10642 if (fixp
->fx_tcbit2
)
10643 fixp
->fx_r_type
= (fixp
->fx_tcbit
10644 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10645 : BFD_RELOC_X86_64_GOTPCRELX
);
10648 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10653 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10655 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10657 fixp
->fx_subsy
= 0;
10660 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10661 else if (!object_64bit
)
10663 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
10664 && fixp
->fx_tcbit2
)
10665 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
10671 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10674 bfd_reloc_code_real_type code
;
10676 switch (fixp
->fx_r_type
)
10678 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10679 case BFD_RELOC_SIZE32
:
10680 case BFD_RELOC_SIZE64
:
10681 if (S_IS_DEFINED (fixp
->fx_addsy
)
10682 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10684 /* Resolve size relocation against local symbol to size of
10685 the symbol plus addend. */
10686 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10687 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10688 && !fits_in_unsigned_long (value
))
10689 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10690 _("symbol size computation overflow"));
10691 fixp
->fx_addsy
= NULL
;
10692 fixp
->fx_subsy
= NULL
;
10693 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10698 case BFD_RELOC_X86_64_PLT32
:
10699 case BFD_RELOC_X86_64_GOT32
:
10700 case BFD_RELOC_X86_64_GOTPCREL
:
10701 case BFD_RELOC_X86_64_GOTPCRELX
:
10702 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10703 case BFD_RELOC_386_PLT32
:
10704 case BFD_RELOC_386_GOT32
:
10705 case BFD_RELOC_386_GOT32X
:
10706 case BFD_RELOC_386_GOTOFF
:
10707 case BFD_RELOC_386_GOTPC
:
10708 case BFD_RELOC_386_TLS_GD
:
10709 case BFD_RELOC_386_TLS_LDM
:
10710 case BFD_RELOC_386_TLS_LDO_32
:
10711 case BFD_RELOC_386_TLS_IE_32
:
10712 case BFD_RELOC_386_TLS_IE
:
10713 case BFD_RELOC_386_TLS_GOTIE
:
10714 case BFD_RELOC_386_TLS_LE_32
:
10715 case BFD_RELOC_386_TLS_LE
:
10716 case BFD_RELOC_386_TLS_GOTDESC
:
10717 case BFD_RELOC_386_TLS_DESC_CALL
:
10718 case BFD_RELOC_X86_64_TLSGD
:
10719 case BFD_RELOC_X86_64_TLSLD
:
10720 case BFD_RELOC_X86_64_DTPOFF32
:
10721 case BFD_RELOC_X86_64_DTPOFF64
:
10722 case BFD_RELOC_X86_64_GOTTPOFF
:
10723 case BFD_RELOC_X86_64_TPOFF32
:
10724 case BFD_RELOC_X86_64_TPOFF64
:
10725 case BFD_RELOC_X86_64_GOTOFF64
:
10726 case BFD_RELOC_X86_64_GOTPC32
:
10727 case BFD_RELOC_X86_64_GOT64
:
10728 case BFD_RELOC_X86_64_GOTPCREL64
:
10729 case BFD_RELOC_X86_64_GOTPC64
:
10730 case BFD_RELOC_X86_64_GOTPLT64
:
10731 case BFD_RELOC_X86_64_PLTOFF64
:
10732 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10733 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10734 case BFD_RELOC_RVA
:
10735 case BFD_RELOC_VTABLE_ENTRY
:
10736 case BFD_RELOC_VTABLE_INHERIT
:
10738 case BFD_RELOC_32_SECREL
:
10740 code
= fixp
->fx_r_type
;
10742 case BFD_RELOC_X86_64_32S
:
10743 if (!fixp
->fx_pcrel
)
10745 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10746 code
= fixp
->fx_r_type
;
10750 if (fixp
->fx_pcrel
)
10752 switch (fixp
->fx_size
)
10755 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10756 _("can not do %d byte pc-relative relocation"),
10758 code
= BFD_RELOC_32_PCREL
;
10760 case 1: code
= BFD_RELOC_8_PCREL
; break;
10761 case 2: code
= BFD_RELOC_16_PCREL
; break;
10762 case 4: code
= BFD_RELOC_32_PCREL
; break;
10764 case 8: code
= BFD_RELOC_64_PCREL
; break;
10770 switch (fixp
->fx_size
)
10773 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10774 _("can not do %d byte relocation"),
10776 code
= BFD_RELOC_32
;
10778 case 1: code
= BFD_RELOC_8
; break;
10779 case 2: code
= BFD_RELOC_16
; break;
10780 case 4: code
= BFD_RELOC_32
; break;
10782 case 8: code
= BFD_RELOC_64
; break;
10789 if ((code
== BFD_RELOC_32
10790 || code
== BFD_RELOC_32_PCREL
10791 || code
== BFD_RELOC_X86_64_32S
)
10793 && fixp
->fx_addsy
== GOT_symbol
)
10796 code
= BFD_RELOC_386_GOTPC
;
10798 code
= BFD_RELOC_X86_64_GOTPC32
;
10800 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10802 && fixp
->fx_addsy
== GOT_symbol
)
10804 code
= BFD_RELOC_X86_64_GOTPC64
;
10807 rel
= XNEW (arelent
);
10808 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
10809 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10811 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10813 if (!use_rela_relocations
)
10815 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10816 vtable entry to be used in the relocation's section offset. */
10817 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10818 rel
->address
= fixp
->fx_offset
;
10819 #if defined (OBJ_COFF) && defined (TE_PE)
10820 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10821 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10826 /* Use the rela in 64bit mode. */
10829 if (disallow_64bit_reloc
)
10832 case BFD_RELOC_X86_64_DTPOFF64
:
10833 case BFD_RELOC_X86_64_TPOFF64
:
10834 case BFD_RELOC_64_PCREL
:
10835 case BFD_RELOC_X86_64_GOTOFF64
:
10836 case BFD_RELOC_X86_64_GOT64
:
10837 case BFD_RELOC_X86_64_GOTPCREL64
:
10838 case BFD_RELOC_X86_64_GOTPC64
:
10839 case BFD_RELOC_X86_64_GOTPLT64
:
10840 case BFD_RELOC_X86_64_PLTOFF64
:
10841 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10842 _("cannot represent relocation type %s in x32 mode"),
10843 bfd_get_reloc_code_name (code
));
10849 if (!fixp
->fx_pcrel
)
10850 rel
->addend
= fixp
->fx_offset
;
10854 case BFD_RELOC_X86_64_PLT32
:
10855 case BFD_RELOC_X86_64_GOT32
:
10856 case BFD_RELOC_X86_64_GOTPCREL
:
10857 case BFD_RELOC_X86_64_GOTPCRELX
:
10858 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10859 case BFD_RELOC_X86_64_TLSGD
:
10860 case BFD_RELOC_X86_64_TLSLD
:
10861 case BFD_RELOC_X86_64_GOTTPOFF
:
10862 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10863 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10864 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10867 rel
->addend
= (section
->vma
10869 + fixp
->fx_addnumber
10870 + md_pcrel_from (fixp
));
10875 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10876 if (rel
->howto
== NULL
)
10878 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10879 _("cannot represent relocation type %s"),
10880 bfd_get_reloc_code_name (code
));
10881 /* Set howto to a garbage value so that we can keep going. */
10882 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10883 gas_assert (rel
->howto
!= NULL
);
10889 #include "tc-i386-intel.c"
10892 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10894 int saved_naked_reg
;
10895 char saved_register_dot
;
10897 saved_naked_reg
= allow_naked_reg
;
10898 allow_naked_reg
= 1;
10899 saved_register_dot
= register_chars
['.'];
10900 register_chars
['.'] = '.';
10901 allow_pseudo_reg
= 1;
10902 expression_and_evaluate (exp
);
10903 allow_pseudo_reg
= 0;
10904 register_chars
['.'] = saved_register_dot
;
10905 allow_naked_reg
= saved_naked_reg
;
10907 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10909 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10911 exp
->X_op
= O_constant
;
10912 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10913 .dw2_regnum
[flag_code
>> 1];
10916 exp
->X_op
= O_illegal
;
10921 tc_x86_frame_initial_instructions (void)
10923 static unsigned int sp_regno
[2];
10925 if (!sp_regno
[flag_code
>> 1])
10927 char *saved_input
= input_line_pointer
;
10928 char sp
[][4] = {"esp", "rsp"};
10931 input_line_pointer
= sp
[flag_code
>> 1];
10932 tc_x86_parse_to_dw2regnum (&exp
);
10933 gas_assert (exp
.X_op
== O_constant
);
10934 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10935 input_line_pointer
= saved_input
;
10938 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10939 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10943 x86_dwarf2_addr_size (void)
10945 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10946 if (x86_elf_abi
== X86_64_X32_ABI
)
10949 return bfd_arch_bits_per_address (stdoutput
) / 8;
10953 i386_elf_section_type (const char *str
, size_t len
)
10955 if (flag_code
== CODE_64BIT
10956 && len
== sizeof ("unwind") - 1
10957 && strncmp (str
, "unwind", 6) == 0)
10958 return SHT_X86_64_UNWIND
;
10965 i386_solaris_fix_up_eh_frame (segT sec
)
10967 if (flag_code
== CODE_64BIT
)
10968 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10974 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10978 exp
.X_op
= O_secrel
;
10979 exp
.X_add_symbol
= symbol
;
10980 exp
.X_add_number
= 0;
10981 emit_expr (&exp
, size
);
10985 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10986 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10989 x86_64_section_letter (int letter
, const char **ptr_msg
)
10991 if (flag_code
== CODE_64BIT
)
10994 return SHF_X86_64_LARGE
;
10996 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10999 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
11004 x86_64_section_word (char *str
, size_t len
)
11006 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
11007 return SHF_X86_64_LARGE
;
11013 handle_large_common (int small ATTRIBUTE_UNUSED
)
11015 if (flag_code
!= CODE_64BIT
)
11017 s_comm_internal (0, elf_common_parse
);
11018 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11022 static segT lbss_section
;
11023 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
11024 asection
*saved_bss_section
= bss_section
;
11026 if (lbss_section
== NULL
)
11028 flagword applicable
;
11029 segT seg
= now_seg
;
11030 subsegT subseg
= now_subseg
;
11032 /* The .lbss section is for local .largecomm symbols. */
11033 lbss_section
= subseg_new (".lbss", 0);
11034 applicable
= bfd_applicable_section_flags (stdoutput
);
11035 bfd_set_section_flags (stdoutput
, lbss_section
,
11036 applicable
& SEC_ALLOC
);
11037 seg_info (lbss_section
)->bss
= 1;
11039 subseg_set (seg
, subseg
);
11042 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
11043 bss_section
= lbss_section
;
11045 s_comm_internal (0, elf_common_parse
);
11047 elf_com_section_ptr
= saved_com_section_ptr
;
11048 bss_section
= saved_bss_section
;
11051 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */