1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
139 /* Used to turn off indicated flags. */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 i386_cpu_flags flags
; /* cpu feature flags */
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
157 static void pe_directive_secrel (int);
159 static void signed_cons (int);
160 static char *output_invalid (int c
);
161 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
163 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS
*);
168 static int i386_intel_parse_name (const char *, expressionS
*);
169 static const reg_entry
*parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template
*match_template (char);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry
*build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS
*, offsetT
);
188 static void output_disp (fragS
*, offsetT
);
190 static void s_bss (int);
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
196 static const char *default_arch
= DEFAULT_ARCH
;
198 /* This struct describes rounding control and SAE in the instruction. */
212 static struct RC_Operation rc_op
;
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
219 const reg_entry
*mask
;
220 unsigned int zeroing
;
221 /* The operand where this operation is associated. */
225 static struct Mask_Operation mask_op
;
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
229 struct Broadcast_Operation
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
234 /* Index of broadcasted operand. */
238 static struct Broadcast_Operation broadcast_op
;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes
[4];
246 /* Destination or source register specifier. */
247 const reg_entry
*register_specifier
;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry
*regs
;
262 operand_size_mismatch
,
263 operand_type_mismatch
,
264 register_type_mismatch
,
265 number_of_operands_mismatch
,
266 invalid_instruction_suffix
,
269 unsupported_with_intel_mnemonic
,
272 invalid_vsib_address
,
273 invalid_vector_register_set
,
274 unsupported_vector_index_register
,
275 unsupported_broadcast
,
276 broadcast_not_on_src_operand
,
279 mask_not_on_destination
,
282 rc_sae_operand_not_last_imm
,
283 invalid_register_operand
,
289 /* TM holds the template for the insn were currently assembling. */
292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
296 /* OPERANDS gives the number of given operands. */
297 unsigned int operands
;
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
302 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
304 /* TYPES [i] is the type (see above #defines) which tells us how to
305 use OP[i] for the corresponding operand. */
306 i386_operand_type types
[MAX_OPERANDS
];
308 /* Displacement expression, immediate expression, or register for each
310 union i386_op op
[MAX_OPERANDS
];
312 /* Flags for operands. */
313 unsigned int flags
[MAX_OPERANDS
];
314 #define Operand_PCrel 1
316 /* Relocation type for operand */
317 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry
*base_reg
;
322 const reg_entry
*index_reg
;
323 unsigned int log2_scale_factor
;
325 /* SEG gives the seg_entries of this insn. They are zero unless
326 explicit segment overrides are given. */
327 const seg_entry
*seg
[2];
329 /* Copied first memory operand string, for re-checking. */
332 /* PREFIX holds all the given prefix opcodes (usually null).
333 PREFIXES is the number of prefix opcodes. */
334 unsigned int prefixes
;
335 unsigned char prefix
[MAX_PREFIXES
];
337 /* RM and SIB are the modrm byte and the sib byte where the
338 addressing modes of this insn are encoded. */
345 /* Masking attributes. */
346 struct Mask_Operation
*mask
;
348 /* Rounding control and SAE attributes. */
349 struct RC_Operation
*rounding
;
351 /* Broadcasting attributes. */
352 struct Broadcast_Operation
*broadcast
;
354 /* Compressed disp8*N attribute. */
355 unsigned int memshift
;
357 /* Swap operand in encoding. */
358 unsigned int swap_operand
;
360 /* Prefer 8bit or 32bit displacement in encoding. */
363 disp_encoding_default
= 0,
369 const char *rep_prefix
;
372 const char *hle_prefix
;
374 /* Have BND prefix. */
375 const char *bnd_prefix
;
377 /* Need VREX to support upper 16 registers. */
381 enum i386_error error
;
384 typedef struct _i386_insn i386_insn
;
386 /* Link RC type with corresponding string, that'll be looked for in
395 static const struct RC_name RC_NamesTable
[] =
397 { rne
, STRING_COMMA_LEN ("rn-sae") },
398 { rd
, STRING_COMMA_LEN ("rd-sae") },
399 { ru
, STRING_COMMA_LEN ("ru-sae") },
400 { rz
, STRING_COMMA_LEN ("rz-sae") },
401 { saeonly
, STRING_COMMA_LEN ("sae") },
404 /* List of chars besides those in app.c:symbol_chars that can start an
405 operand. Used to prevent the scrubber eating vital white-space. */
406 const char extra_symbol_chars
[] = "*%-([{"
415 #if (defined (TE_I386AIX) \
416 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
417 && !defined (TE_GNU) \
418 && !defined (TE_LINUX) \
419 && !defined (TE_NACL) \
420 && !defined (TE_NETWARE) \
421 && !defined (TE_FreeBSD) \
422 && !defined (TE_DragonFly) \
423 && !defined (TE_NetBSD)))
424 /* This array holds the chars that always start a comment. If the
425 pre-processor is disabled, these aren't very useful. The option
426 --divide will remove '/' from this list. */
427 const char *i386_comment_chars
= "#/";
428 #define SVR4_COMMENT_CHARS 1
429 #define PREFIX_SEPARATOR '\\'
432 const char *i386_comment_chars
= "#";
433 #define PREFIX_SEPARATOR '/'
436 /* This array holds the chars that only start a comment at the beginning of
437 a line. If the line seems to have the form '# 123 filename'
438 .line and .file directives will appear in the pre-processed output.
439 Note that input_file.c hand checks for '#' at the beginning of the
440 first line of the input file. This is because the compiler outputs
441 #NO_APP at the beginning of its output.
442 Also note that comments started like this one will always work if
443 '/' isn't otherwise defined. */
444 const char line_comment_chars
[] = "#/";
446 const char line_separator_chars
[] = ";";
448 /* Chars that can be used to separate mant from exp in floating point
450 const char EXP_CHARS
[] = "eE";
452 /* Chars that mean this number is a floating point constant
455 const char FLT_CHARS
[] = "fFdDxX";
457 /* Tables for lexical analysis. */
458 static char mnemonic_chars
[256];
459 static char register_chars
[256];
460 static char operand_chars
[256];
461 static char identifier_chars
[256];
462 static char digit_chars
[256];
464 /* Lexical macros. */
465 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
466 #define is_operand_char(x) (operand_chars[(unsigned char) x])
467 #define is_register_char(x) (register_chars[(unsigned char) x])
468 #define is_space_char(x) ((x) == ' ')
469 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
470 #define is_digit_char(x) (digit_chars[(unsigned char) x])
472 /* All non-digit non-letter characters that may occur in an operand. */
473 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
475 /* md_assemble() always leaves the strings it's passed unaltered. To
476 effect this we maintain a stack of saved characters that we've smashed
477 with '\0's (indicating end of strings for various sub-fields of the
478 assembler instruction). */
479 static char save_stack
[32];
480 static char *save_stack_p
;
481 #define END_STRING_AND_SAVE(s) \
482 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
483 #define RESTORE_END_STRING(s) \
484 do { *(s) = *--save_stack_p; } while (0)
486 /* The instruction we're assembling. */
489 /* Possible templates for current insn. */
490 static const templates
*current_templates
;
492 /* Per instruction expressionS buffers: max displacements & immediates. */
493 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
494 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
496 /* Current operand we are working on. */
497 static int this_operand
= -1;
499 /* We support four different modes. FLAG_CODE variable is used to distinguish
507 static enum flag_code flag_code
;
508 static unsigned int object_64bit
;
509 static unsigned int disallow_64bit_reloc
;
510 static int use_rela_relocations
= 0;
512 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
513 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
514 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
516 /* The ELF ABI to use. */
524 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
527 #if defined (TE_PE) || defined (TE_PEP)
528 /* Use big object file format. */
529 static int use_big_obj
= 0;
532 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
533 /* 1 if generating code for a shared library. */
534 static int shared
= 0;
537 /* 1 for intel syntax,
539 static int intel_syntax
= 0;
541 /* 1 for Intel64 ISA,
545 /* 1 for intel mnemonic,
546 0 if att mnemonic. */
547 static int intel_mnemonic
= !SYSV386_COMPAT
;
549 /* 1 if support old (<= 2.8.1) versions of gcc. */
550 static int old_gcc
= OLDGCC_COMPAT
;
552 /* 1 if pseudo registers are permitted. */
553 static int allow_pseudo_reg
= 0;
555 /* 1 if register prefix % not required. */
556 static int allow_naked_reg
= 0;
558 /* 1 if the assembler should add BND prefix for all control-tranferring
559 instructions supporting it, even if this prefix wasn't specified
561 static int add_bnd_prefix
= 0;
563 /* 1 if pseudo index register, eiz/riz, is allowed . */
564 static int allow_index_reg
= 0;
566 /* 1 if the assembler should ignore LOCK prefix, even if it was
567 specified explicitly. */
568 static int omit_lock_prefix
= 0;
570 /* 1 if the assembler should encode lfence, mfence, and sfence as
571 "lock addl $0, (%{re}sp)". */
572 static int avoid_fence
= 0;
574 /* 1 if the assembler should generate relax relocations. */
576 static int generate_relax_relocations
577 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
579 static enum check_kind
585 sse_check
, operand_check
= check_warning
;
587 /* Register prefix used for error message. */
588 static const char *register_prefix
= "%";
590 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
591 leave, push, and pop instructions so that gcc has the same stack
592 frame as in 32 bit mode. */
593 static char stackop_size
= '\0';
595 /* Non-zero to optimize code alignment. */
596 int optimize_align_code
= 1;
598 /* Non-zero to quieten some warnings. */
599 static int quiet_warnings
= 0;
602 static const char *cpu_arch_name
= NULL
;
603 static char *cpu_sub_arch_name
= NULL
;
605 /* CPU feature flags. */
606 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
608 /* If we have selected a cpu we are generating instructions for. */
609 static int cpu_arch_tune_set
= 0;
611 /* Cpu we are generating instructions for. */
612 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
614 /* CPU feature flags of cpu we are generating instructions for. */
615 static i386_cpu_flags cpu_arch_tune_flags
;
617 /* CPU instruction set architecture used. */
618 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
620 /* CPU feature flags of instruction set architecture used. */
621 i386_cpu_flags cpu_arch_isa_flags
;
623 /* If set, conditional jumps are not automatically promoted to handle
624 larger than a byte offset. */
625 static unsigned int no_cond_jump_promotion
= 0;
627 /* Encode SSE instructions with VEX prefix. */
628 static unsigned int sse2avx
;
630 /* Encode scalar AVX instructions with specific vector length. */
637 /* Encode scalar EVEX LIG instructions with specific vector length. */
645 /* Encode EVEX WIG instructions with specific evex.w. */
652 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
653 static enum rc_type evexrcig
= rne
;
655 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
656 static symbolS
*GOT_symbol
;
658 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
659 unsigned int x86_dwarf2_return_column
;
661 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
662 int x86_cie_data_alignment
;
664 /* Interface to relax_segment.
665 There are 3 major relax states for 386 jump insns because the
666 different types of jumps add different sizes to frags when we're
667 figuring out what sort of jump to choose to reach a given label. */
670 #define UNCOND_JUMP 0
672 #define COND_JUMP86 2
677 #define SMALL16 (SMALL | CODE16)
679 #define BIG16 (BIG | CODE16)
683 #define INLINE __inline__
689 #define ENCODE_RELAX_STATE(type, size) \
690 ((relax_substateT) (((type) << 2) | (size)))
691 #define TYPE_FROM_RELAX_STATE(s) \
693 #define DISP_SIZE_FROM_RELAX_STATE(s) \
694 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
696 /* This table is used by relax_frag to promote short jumps to long
697 ones where necessary. SMALL (short) jumps may be promoted to BIG
698 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
699 don't allow a short jump in a 32 bit code segment to be promoted to
700 a 16 bit offset jump because it's slower (requires data size
701 prefix), and doesn't work, unless the destination is in the bottom
702 64k of the code segment (The top 16 bits of eip are zeroed). */
704 const relax_typeS md_relax_table
[] =
707 1) most positive reach of this state,
708 2) most negative reach of this state,
709 3) how many bytes this mode will have in the variable part of the frag
710 4) which index into the table to try if we can't fit into this one. */
712 /* UNCOND_JUMP states. */
713 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
714 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
715 /* dword jmp adds 4 bytes to frag:
716 0 extra opcode bytes, 4 displacement bytes. */
718 /* word jmp adds 2 byte2 to frag:
719 0 extra opcode bytes, 2 displacement bytes. */
722 /* COND_JUMP states. */
723 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
724 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
725 /* dword conditionals adds 5 bytes to frag:
726 1 extra opcode byte, 4 displacement bytes. */
728 /* word conditionals add 3 bytes to frag:
729 1 extra opcode byte, 2 displacement bytes. */
732 /* COND_JUMP86 states. */
733 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
734 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
735 /* dword conditionals adds 5 bytes to frag:
736 1 extra opcode byte, 4 displacement bytes. */
738 /* word conditionals add 4 bytes to frag:
739 1 displacement byte and a 3 byte long branch insn. */
743 static const arch_entry cpu_arch
[] =
745 /* Do not replace the first two entries - i386_target_format()
746 relies on them being there in this order. */
747 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
748 CPU_GENERIC32_FLAGS
, 0 },
749 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
750 CPU_GENERIC64_FLAGS
, 0 },
751 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
753 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
755 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
757 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
759 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
761 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
763 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
765 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
767 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
768 CPU_PENTIUMPRO_FLAGS
, 0 },
769 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
771 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
773 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
775 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
777 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
778 CPU_NOCONA_FLAGS
, 0 },
779 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
781 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
783 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
784 CPU_CORE2_FLAGS
, 1 },
785 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
786 CPU_CORE2_FLAGS
, 0 },
787 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
788 CPU_COREI7_FLAGS
, 0 },
789 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
791 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
793 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
794 CPU_IAMCU_FLAGS
, 0 },
795 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
797 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
799 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
800 CPU_ATHLON_FLAGS
, 0 },
801 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
803 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
805 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
807 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
808 CPU_AMDFAM10_FLAGS
, 0 },
809 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
810 CPU_BDVER1_FLAGS
, 0 },
811 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
812 CPU_BDVER2_FLAGS
, 0 },
813 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
814 CPU_BDVER3_FLAGS
, 0 },
815 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
816 CPU_BDVER4_FLAGS
, 0 },
817 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
818 CPU_ZNVER1_FLAGS
, 0 },
819 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
820 CPU_BTVER1_FLAGS
, 0 },
821 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
822 CPU_BTVER2_FLAGS
, 0 },
823 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
825 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
827 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
829 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
831 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
833 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
835 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
837 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
839 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
840 CPU_SSSE3_FLAGS
, 0 },
841 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
842 CPU_SSE4_1_FLAGS
, 0 },
843 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
844 CPU_SSE4_2_FLAGS
, 0 },
845 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
846 CPU_SSE4_2_FLAGS
, 0 },
847 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
849 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
851 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
852 CPU_AVX512F_FLAGS
, 0 },
853 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
854 CPU_AVX512CD_FLAGS
, 0 },
855 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
856 CPU_AVX512ER_FLAGS
, 0 },
857 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
858 CPU_AVX512PF_FLAGS
, 0 },
859 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
860 CPU_AVX512DQ_FLAGS
, 0 },
861 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
862 CPU_AVX512BW_FLAGS
, 0 },
863 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
864 CPU_AVX512VL_FLAGS
, 0 },
865 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
867 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
868 CPU_VMFUNC_FLAGS
, 0 },
869 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
871 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
872 CPU_XSAVE_FLAGS
, 0 },
873 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
874 CPU_XSAVEOPT_FLAGS
, 0 },
875 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
876 CPU_XSAVEC_FLAGS
, 0 },
877 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
878 CPU_XSAVES_FLAGS
, 0 },
879 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
881 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
882 CPU_PCLMUL_FLAGS
, 0 },
883 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
884 CPU_PCLMUL_FLAGS
, 1 },
885 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
886 CPU_FSGSBASE_FLAGS
, 0 },
887 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
888 CPU_RDRND_FLAGS
, 0 },
889 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
891 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
893 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
895 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
897 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
899 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
901 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
902 CPU_MOVBE_FLAGS
, 0 },
903 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
905 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
907 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
908 CPU_LZCNT_FLAGS
, 0 },
909 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
911 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
913 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
914 CPU_INVPCID_FLAGS
, 0 },
915 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
916 CPU_CLFLUSH_FLAGS
, 0 },
917 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
919 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
920 CPU_SYSCALL_FLAGS
, 0 },
921 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
922 CPU_RDTSCP_FLAGS
, 0 },
923 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
924 CPU_3DNOW_FLAGS
, 0 },
925 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
926 CPU_3DNOWA_FLAGS
, 0 },
927 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
928 CPU_PADLOCK_FLAGS
, 0 },
929 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
931 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
933 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
934 CPU_SSE4A_FLAGS
, 0 },
935 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
937 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
939 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
941 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
943 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
944 CPU_RDSEED_FLAGS
, 0 },
945 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
946 CPU_PRFCHW_FLAGS
, 0 },
947 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
949 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
951 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
953 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
954 CPU_CLFLUSHOPT_FLAGS
, 0 },
955 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
956 CPU_PREFETCHWT1_FLAGS
, 0 },
957 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
959 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
961 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
962 CPU_AVX512IFMA_FLAGS
, 0 },
963 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
964 CPU_AVX512VBMI_FLAGS
, 0 },
965 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
966 CPU_CLZERO_FLAGS
, 0 },
967 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
968 CPU_MWAITX_FLAGS
, 0 },
969 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
970 CPU_OSPKE_FLAGS
, 0 },
971 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
972 CPU_RDPID_FLAGS
, 0 },
973 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
974 CPU_PTWRITE_FLAGS
, 0 },
977 static const noarch_entry cpu_noarch
[] =
979 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
980 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
981 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
982 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
983 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
984 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
985 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
986 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
987 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
988 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
989 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
990 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
991 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
992 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
993 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
994 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
995 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
996 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
997 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
998 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
999 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1000 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1001 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1005 /* Like s_lcomm_internal in gas/read.c but the alignment string
1006 is allowed to be optional. */
1009 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1016 && *input_line_pointer
== ',')
1018 align
= parse_align (needs_align
- 1);
1020 if (align
== (addressT
) -1)
1035 bss_alloc (symbolP
, size
, align
);
1040 pe_lcomm (int needs_align
)
1042 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1046 const pseudo_typeS md_pseudo_table
[] =
1048 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1049 {"align", s_align_bytes
, 0},
1051 {"align", s_align_ptwo
, 0},
1053 {"arch", set_cpu_arch
, 0},
1057 {"lcomm", pe_lcomm
, 1},
1059 {"ffloat", float_cons
, 'f'},
1060 {"dfloat", float_cons
, 'd'},
1061 {"tfloat", float_cons
, 'x'},
1063 {"slong", signed_cons
, 4},
1064 {"noopt", s_ignore
, 0},
1065 {"optim", s_ignore
, 0},
1066 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1067 {"code16", set_code_flag
, CODE_16BIT
},
1068 {"code32", set_code_flag
, CODE_32BIT
},
1069 {"code64", set_code_flag
, CODE_64BIT
},
1070 {"intel_syntax", set_intel_syntax
, 1},
1071 {"att_syntax", set_intel_syntax
, 0},
1072 {"intel_mnemonic", set_intel_mnemonic
, 1},
1073 {"att_mnemonic", set_intel_mnemonic
, 0},
1074 {"allow_index_reg", set_allow_index_reg
, 1},
1075 {"disallow_index_reg", set_allow_index_reg
, 0},
1076 {"sse_check", set_check
, 0},
1077 {"operand_check", set_check
, 1},
1078 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1079 {"largecomm", handle_large_common
, 0},
1081 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1082 {"loc", dwarf2_directive_loc
, 0},
1083 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1086 {"secrel32", pe_directive_secrel
, 0},
1091 /* For interface with expression (). */
1092 extern char *input_line_pointer
;
1094 /* Hash table for instruction mnemonic lookup. */
1095 static struct hash_control
*op_hash
;
1097 /* Hash table for register lookup. */
1098 static struct hash_control
*reg_hash
;
1101 i386_align_code (fragS
*fragP
, int count
)
1103 /* Various efficient no-op patterns for aligning code labels.
1104 Note: Don't try to assemble the instructions in the comments.
1105 0L and 0w are not legal. */
1106 static const unsigned char f32_1
[] =
1108 static const unsigned char f32_2
[] =
1109 {0x66,0x90}; /* xchg %ax,%ax */
1110 static const unsigned char f32_3
[] =
1111 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1112 static const unsigned char f32_4
[] =
1113 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1114 static const unsigned char f32_5
[] =
1116 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1117 static const unsigned char f32_6
[] =
1118 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1119 static const unsigned char f32_7
[] =
1120 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1121 static const unsigned char f32_8
[] =
1123 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1124 static const unsigned char f32_9
[] =
1125 {0x89,0xf6, /* movl %esi,%esi */
1126 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1127 static const unsigned char f32_10
[] =
1128 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1129 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1130 static const unsigned char f32_11
[] =
1131 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1132 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1133 static const unsigned char f32_12
[] =
1134 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1135 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1136 static const unsigned char f32_13
[] =
1137 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1138 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1139 static const unsigned char f32_14
[] =
1140 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1141 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1142 static const unsigned char f16_3
[] =
1143 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1144 static const unsigned char f16_4
[] =
1145 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1146 static const unsigned char f16_5
[] =
1148 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1149 static const unsigned char f16_6
[] =
1150 {0x89,0xf6, /* mov %si,%si */
1151 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1152 static const unsigned char f16_7
[] =
1153 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1154 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1155 static const unsigned char f16_8
[] =
1156 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1157 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1158 static const unsigned char jump_31
[] =
1159 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1160 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1161 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1162 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1163 static const unsigned char *const f32_patt
[] = {
1164 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1165 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1167 static const unsigned char *const f16_patt
[] = {
1168 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1170 /* nopl (%[re]ax) */
1171 static const unsigned char alt_3
[] =
1173 /* nopl 0(%[re]ax) */
1174 static const unsigned char alt_4
[] =
1175 {0x0f,0x1f,0x40,0x00};
1176 /* nopl 0(%[re]ax,%[re]ax,1) */
1177 static const unsigned char alt_5
[] =
1178 {0x0f,0x1f,0x44,0x00,0x00};
1179 /* nopw 0(%[re]ax,%[re]ax,1) */
1180 static const unsigned char alt_6
[] =
1181 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1182 /* nopl 0L(%[re]ax) */
1183 static const unsigned char alt_7
[] =
1184 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1185 /* nopl 0L(%[re]ax,%[re]ax,1) */
1186 static const unsigned char alt_8
[] =
1187 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1188 /* nopw 0L(%[re]ax,%[re]ax,1) */
1189 static const unsigned char alt_9
[] =
1190 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1191 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1192 static const unsigned char alt_10
[] =
1193 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1194 static const unsigned char *const alt_patt
[] = {
1195 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1199 /* Only align for at least a positive non-zero boundary. */
1200 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1203 /* We need to decide which NOP sequence to use for 32bit and
1204 64bit. When -mtune= is used:
1206 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1207 PROCESSOR_GENERIC32, f32_patt will be used.
1208 2. For the rest, alt_patt will be used.
1210 When -mtune= isn't used, alt_patt will be used if
1211 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1214 When -march= or .arch is used, we can't use anything beyond
1215 cpu_arch_isa_flags. */
1217 if (flag_code
== CODE_16BIT
)
1221 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1223 /* Adjust jump offset. */
1224 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1227 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1228 f16_patt
[count
- 1], count
);
1232 const unsigned char *const *patt
= NULL
;
1234 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1236 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1237 switch (cpu_arch_tune
)
1239 case PROCESSOR_UNKNOWN
:
1240 /* We use cpu_arch_isa_flags to check if we SHOULD
1241 optimize with nops. */
1242 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1247 case PROCESSOR_PENTIUM4
:
1248 case PROCESSOR_NOCONA
:
1249 case PROCESSOR_CORE
:
1250 case PROCESSOR_CORE2
:
1251 case PROCESSOR_COREI7
:
1252 case PROCESSOR_L1OM
:
1253 case PROCESSOR_K1OM
:
1254 case PROCESSOR_GENERIC64
:
1256 case PROCESSOR_ATHLON
:
1258 case PROCESSOR_AMDFAM10
:
1260 case PROCESSOR_ZNVER
:
1264 case PROCESSOR_I386
:
1265 case PROCESSOR_I486
:
1266 case PROCESSOR_PENTIUM
:
1267 case PROCESSOR_PENTIUMPRO
:
1268 case PROCESSOR_IAMCU
:
1269 case PROCESSOR_GENERIC32
:
1276 switch (fragP
->tc_frag_data
.tune
)
1278 case PROCESSOR_UNKNOWN
:
1279 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1280 PROCESSOR_UNKNOWN. */
1284 case PROCESSOR_I386
:
1285 case PROCESSOR_I486
:
1286 case PROCESSOR_PENTIUM
:
1287 case PROCESSOR_IAMCU
:
1289 case PROCESSOR_ATHLON
:
1291 case PROCESSOR_AMDFAM10
:
1293 case PROCESSOR_ZNVER
:
1295 case PROCESSOR_GENERIC32
:
1296 /* We use cpu_arch_isa_flags to check if we CAN optimize
1298 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1303 case PROCESSOR_PENTIUMPRO
:
1304 case PROCESSOR_PENTIUM4
:
1305 case PROCESSOR_NOCONA
:
1306 case PROCESSOR_CORE
:
1307 case PROCESSOR_CORE2
:
1308 case PROCESSOR_COREI7
:
1309 case PROCESSOR_L1OM
:
1310 case PROCESSOR_K1OM
:
1311 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1316 case PROCESSOR_GENERIC64
:
1322 if (patt
== f32_patt
)
1324 /* If the padding is less than 15 bytes, we use the normal
1325 ones. Otherwise, we use a jump instruction and adjust
1329 /* For 64bit, the limit is 3 bytes. */
1330 if (flag_code
== CODE_64BIT
1331 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1336 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1337 patt
[count
- 1], count
);
1340 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1342 /* Adjust jump offset. */
1343 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1348 /* Maximum length of an instruction is 10 byte. If the
1349 padding is greater than 10 bytes and we don't use jump,
1350 we have to break it into smaller pieces. */
1351 int padding
= count
;
1352 while (padding
> 10)
1355 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1360 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1361 patt
[padding
- 1], padding
);
1364 fragP
->fr_var
= count
;
1368 operand_type_all_zero (const union i386_operand_type
*x
)
1370 switch (ARRAY_SIZE(x
->array
))
1381 return !x
->array
[0];
1388 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1390 switch (ARRAY_SIZE(x
->array
))
1408 operand_type_equal (const union i386_operand_type
*x
,
1409 const union i386_operand_type
*y
)
1411 switch (ARRAY_SIZE(x
->array
))
1414 if (x
->array
[2] != y
->array
[2])
1418 if (x
->array
[1] != y
->array
[1])
1422 return x
->array
[0] == y
->array
[0];
1430 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1432 switch (ARRAY_SIZE(x
->array
))
1443 return !x
->array
[0];
1450 cpu_flags_equal (const union i386_cpu_flags
*x
,
1451 const union i386_cpu_flags
*y
)
1453 switch (ARRAY_SIZE(x
->array
))
1456 if (x
->array
[2] != y
->array
[2])
1460 if (x
->array
[1] != y
->array
[1])
1464 return x
->array
[0] == y
->array
[0];
1472 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1474 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1475 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1478 static INLINE i386_cpu_flags
1479 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1481 switch (ARRAY_SIZE (x
.array
))
1484 x
.array
[2] &= y
.array
[2];
1487 x
.array
[1] &= y
.array
[1];
1490 x
.array
[0] &= y
.array
[0];
1498 static INLINE i386_cpu_flags
1499 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1501 switch (ARRAY_SIZE (x
.array
))
1504 x
.array
[2] |= y
.array
[2];
1507 x
.array
[1] |= y
.array
[1];
1510 x
.array
[0] |= y
.array
[0];
1518 static INLINE i386_cpu_flags
1519 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1521 switch (ARRAY_SIZE (x
.array
))
1524 x
.array
[2] &= ~y
.array
[2];
1527 x
.array
[1] &= ~y
.array
[1];
1530 x
.array
[0] &= ~y
.array
[0];
1538 #define CPU_FLAGS_ARCH_MATCH 0x1
1539 #define CPU_FLAGS_64BIT_MATCH 0x2
1540 #define CPU_FLAGS_AES_MATCH 0x4
1541 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1542 #define CPU_FLAGS_AVX_MATCH 0x10
1544 #define CPU_FLAGS_32BIT_MATCH \
1545 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1546 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1547 #define CPU_FLAGS_PERFECT_MATCH \
1548 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1550 /* Return CPU flags match bits. */
1553 cpu_flags_match (const insn_template
*t
)
1555 i386_cpu_flags x
= t
->cpu_flags
;
1556 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1558 x
.bitfield
.cpu64
= 0;
1559 x
.bitfield
.cpuno64
= 0;
1561 if (cpu_flags_all_zero (&x
))
1563 /* This instruction is available on all archs. */
1564 match
|= CPU_FLAGS_32BIT_MATCH
;
1568 /* This instruction is available only on some archs. */
1569 i386_cpu_flags cpu
= cpu_arch_flags
;
1571 cpu
= cpu_flags_and (x
, cpu
);
1572 if (!cpu_flags_all_zero (&cpu
))
1574 if (x
.bitfield
.cpuavx
)
1576 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1577 if (cpu
.bitfield
.cpuavx
)
1579 /* Check SSE2AVX. */
1580 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1582 match
|= (CPU_FLAGS_ARCH_MATCH
1583 | CPU_FLAGS_AVX_MATCH
);
1585 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1586 match
|= CPU_FLAGS_AES_MATCH
;
1588 if (!x
.bitfield
.cpupclmul
1589 || cpu
.bitfield
.cpupclmul
)
1590 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1594 match
|= CPU_FLAGS_ARCH_MATCH
;
1596 else if (x
.bitfield
.cpuavx512vl
)
1598 /* Match AVX512VL. */
1599 if (cpu
.bitfield
.cpuavx512vl
)
1601 /* Need another match. */
1602 cpu
.bitfield
.cpuavx512vl
= 0;
1603 if (!cpu_flags_all_zero (&cpu
))
1604 match
|= CPU_FLAGS_32BIT_MATCH
;
1606 match
|= CPU_FLAGS_ARCH_MATCH
;
1609 match
|= CPU_FLAGS_ARCH_MATCH
;
1612 match
|= CPU_FLAGS_32BIT_MATCH
;
1618 static INLINE i386_operand_type
1619 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1621 switch (ARRAY_SIZE (x
.array
))
1624 x
.array
[2] &= y
.array
[2];
1627 x
.array
[1] &= y
.array
[1];
1630 x
.array
[0] &= y
.array
[0];
1638 static INLINE i386_operand_type
1639 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1641 switch (ARRAY_SIZE (x
.array
))
1644 x
.array
[2] |= y
.array
[2];
1647 x
.array
[1] |= y
.array
[1];
1650 x
.array
[0] |= y
.array
[0];
1658 static INLINE i386_operand_type
1659 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1661 switch (ARRAY_SIZE (x
.array
))
1664 x
.array
[2] ^= y
.array
[2];
1667 x
.array
[1] ^= y
.array
[1];
1670 x
.array
[0] ^= y
.array
[0];
1678 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1679 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1680 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1681 static const i386_operand_type inoutportreg
1682 = OPERAND_TYPE_INOUTPORTREG
;
1683 static const i386_operand_type reg16_inoutportreg
1684 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1685 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1686 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1687 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1688 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1689 static const i386_operand_type anydisp
1690 = OPERAND_TYPE_ANYDISP
;
1691 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1692 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1693 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1694 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1695 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1696 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1697 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1698 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1699 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1700 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1701 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1702 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1703 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1704 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1715 operand_type_check (i386_operand_type t
, enum operand_type c
)
1720 return (t
.bitfield
.reg8
1723 || t
.bitfield
.reg64
);
1726 return (t
.bitfield
.imm8
1730 || t
.bitfield
.imm32s
1731 || t
.bitfield
.imm64
);
1734 return (t
.bitfield
.disp8
1735 || t
.bitfield
.disp16
1736 || t
.bitfield
.disp32
1737 || t
.bitfield
.disp32s
1738 || t
.bitfield
.disp64
);
1741 return (t
.bitfield
.disp8
1742 || t
.bitfield
.disp16
1743 || t
.bitfield
.disp32
1744 || t
.bitfield
.disp32s
1745 || t
.bitfield
.disp64
1746 || t
.bitfield
.baseindex
);
1755 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1756 operand J for instruction template T. */
1759 match_reg_size (const insn_template
*t
, unsigned int j
)
1761 return !((i
.types
[j
].bitfield
.byte
1762 && !t
->operand_types
[j
].bitfield
.byte
)
1763 || (i
.types
[j
].bitfield
.word
1764 && !t
->operand_types
[j
].bitfield
.word
)
1765 || (i
.types
[j
].bitfield
.dword
1766 && !t
->operand_types
[j
].bitfield
.dword
)
1767 || (i
.types
[j
].bitfield
.qword
1768 && !t
->operand_types
[j
].bitfield
.qword
));
1771 /* Return 1 if there is no conflict in any size on operand J for
1772 instruction template T. */
1775 match_mem_size (const insn_template
*t
, unsigned int j
)
1777 return (match_reg_size (t
, j
)
1778 && !((i
.types
[j
].bitfield
.unspecified
1780 && !t
->operand_types
[j
].bitfield
.unspecified
)
1781 || (i
.types
[j
].bitfield
.fword
1782 && !t
->operand_types
[j
].bitfield
.fword
)
1783 || (i
.types
[j
].bitfield
.tbyte
1784 && !t
->operand_types
[j
].bitfield
.tbyte
)
1785 || (i
.types
[j
].bitfield
.xmmword
1786 && !t
->operand_types
[j
].bitfield
.xmmword
)
1787 || (i
.types
[j
].bitfield
.ymmword
1788 && !t
->operand_types
[j
].bitfield
.ymmword
)
1789 || (i
.types
[j
].bitfield
.zmmword
1790 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1793 /* Return 1 if there is no size conflict on any operands for
1794 instruction template T. */
1797 operand_size_match (const insn_template
*t
)
1802 /* Don't check jump instructions. */
1803 if (t
->opcode_modifier
.jump
1804 || t
->opcode_modifier
.jumpbyte
1805 || t
->opcode_modifier
.jumpdword
1806 || t
->opcode_modifier
.jumpintersegment
)
1809 /* Check memory and accumulator operand size. */
1810 for (j
= 0; j
< i
.operands
; j
++)
1812 if (t
->operand_types
[j
].bitfield
.anysize
)
1815 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1821 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1830 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1833 i
.error
= operand_size_mismatch
;
1837 /* Check reverse. */
1838 gas_assert (i
.operands
== 2);
1841 for (j
= 0; j
< 2; j
++)
1843 if (t
->operand_types
[j
].bitfield
.acc
1844 && !match_reg_size (t
, j
? 0 : 1))
1847 if (i
.types
[j
].bitfield
.mem
1848 && !match_mem_size (t
, j
? 0 : 1))
1856 operand_type_match (i386_operand_type overlap
,
1857 i386_operand_type given
)
1859 i386_operand_type temp
= overlap
;
1861 temp
.bitfield
.jumpabsolute
= 0;
1862 temp
.bitfield
.unspecified
= 0;
1863 temp
.bitfield
.byte
= 0;
1864 temp
.bitfield
.word
= 0;
1865 temp
.bitfield
.dword
= 0;
1866 temp
.bitfield
.fword
= 0;
1867 temp
.bitfield
.qword
= 0;
1868 temp
.bitfield
.tbyte
= 0;
1869 temp
.bitfield
.xmmword
= 0;
1870 temp
.bitfield
.ymmword
= 0;
1871 temp
.bitfield
.zmmword
= 0;
1872 if (operand_type_all_zero (&temp
))
1875 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1876 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1880 i
.error
= operand_type_mismatch
;
1884 /* If given types g0 and g1 are registers they must be of the same type
1885 unless the expected operand type register overlap is null.
1886 Note that Acc in a template matches every size of reg. */
1889 operand_type_register_match (i386_operand_type m0
,
1890 i386_operand_type g0
,
1891 i386_operand_type t0
,
1892 i386_operand_type m1
,
1893 i386_operand_type g1
,
1894 i386_operand_type t1
)
1896 if (!operand_type_check (g0
, reg
))
1899 if (!operand_type_check (g1
, reg
))
1902 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1903 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1904 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1905 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1908 if (m0
.bitfield
.acc
)
1910 t0
.bitfield
.reg8
= 1;
1911 t0
.bitfield
.reg16
= 1;
1912 t0
.bitfield
.reg32
= 1;
1913 t0
.bitfield
.reg64
= 1;
1916 if (m1
.bitfield
.acc
)
1918 t1
.bitfield
.reg8
= 1;
1919 t1
.bitfield
.reg16
= 1;
1920 t1
.bitfield
.reg32
= 1;
1921 t1
.bitfield
.reg64
= 1;
1924 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1925 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1926 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1927 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1930 i
.error
= register_type_mismatch
;
1935 static INLINE
unsigned int
1936 register_number (const reg_entry
*r
)
1938 unsigned int nr
= r
->reg_num
;
1940 if (r
->reg_flags
& RegRex
)
1943 if (r
->reg_flags
& RegVRex
)
1949 static INLINE
unsigned int
1950 mode_from_disp_size (i386_operand_type t
)
1952 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1954 else if (t
.bitfield
.disp16
1955 || t
.bitfield
.disp32
1956 || t
.bitfield
.disp32s
)
1963 fits_in_signed_byte (addressT num
)
1965 return num
+ 0x80 <= 0xff;
1969 fits_in_unsigned_byte (addressT num
)
1975 fits_in_unsigned_word (addressT num
)
1977 return num
<= 0xffff;
1981 fits_in_signed_word (addressT num
)
1983 return num
+ 0x8000 <= 0xffff;
1987 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1992 return num
+ 0x80000000 <= 0xffffffff;
1994 } /* fits_in_signed_long() */
1997 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2002 return num
<= 0xffffffff;
2004 } /* fits_in_unsigned_long() */
2007 fits_in_vec_disp8 (offsetT num
)
2009 int shift
= i
.memshift
;
2015 mask
= (1 << shift
) - 1;
2017 /* Return 0 if NUM isn't properly aligned. */
2021 /* Check if NUM will fit in 8bit after shift. */
2022 return fits_in_signed_byte (num
>> shift
);
2026 fits_in_imm4 (offsetT num
)
2028 return (num
& 0xf) == num
;
2031 static i386_operand_type
2032 smallest_imm_type (offsetT num
)
2034 i386_operand_type t
;
2036 operand_type_set (&t
, 0);
2037 t
.bitfield
.imm64
= 1;
2039 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2041 /* This code is disabled on the 486 because all the Imm1 forms
2042 in the opcode table are slower on the i486. They're the
2043 versions with the implicitly specified single-position
2044 displacement, which has another syntax if you really want to
2046 t
.bitfield
.imm1
= 1;
2047 t
.bitfield
.imm8
= 1;
2048 t
.bitfield
.imm8s
= 1;
2049 t
.bitfield
.imm16
= 1;
2050 t
.bitfield
.imm32
= 1;
2051 t
.bitfield
.imm32s
= 1;
2053 else if (fits_in_signed_byte (num
))
2055 t
.bitfield
.imm8
= 1;
2056 t
.bitfield
.imm8s
= 1;
2057 t
.bitfield
.imm16
= 1;
2058 t
.bitfield
.imm32
= 1;
2059 t
.bitfield
.imm32s
= 1;
2061 else if (fits_in_unsigned_byte (num
))
2063 t
.bitfield
.imm8
= 1;
2064 t
.bitfield
.imm16
= 1;
2065 t
.bitfield
.imm32
= 1;
2066 t
.bitfield
.imm32s
= 1;
2068 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2070 t
.bitfield
.imm16
= 1;
2071 t
.bitfield
.imm32
= 1;
2072 t
.bitfield
.imm32s
= 1;
2074 else if (fits_in_signed_long (num
))
2076 t
.bitfield
.imm32
= 1;
2077 t
.bitfield
.imm32s
= 1;
2079 else if (fits_in_unsigned_long (num
))
2080 t
.bitfield
.imm32
= 1;
2086 offset_in_range (offsetT val
, int size
)
2092 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2093 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2094 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2096 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2102 /* If BFD64, sign extend val for 32bit address mode. */
2103 if (flag_code
!= CODE_64BIT
2104 || i
.prefix
[ADDR_PREFIX
])
2105 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2106 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2109 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2111 char buf1
[40], buf2
[40];
2113 sprint_value (buf1
, val
);
2114 sprint_value (buf2
, val
& mask
);
2115 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2129 a. PREFIX_EXIST if attempting to add a prefix where one from the
2130 same class already exists.
2131 b. PREFIX_LOCK if lock prefix is added.
2132 c. PREFIX_REP if rep/repne prefix is added.
2133 d. PREFIX_OTHER if other prefix is added.
2136 static enum PREFIX_GROUP
2137 add_prefix (unsigned int prefix
)
2139 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2142 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2143 && flag_code
== CODE_64BIT
)
2145 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2146 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2147 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2158 case CS_PREFIX_OPCODE
:
2159 case DS_PREFIX_OPCODE
:
2160 case ES_PREFIX_OPCODE
:
2161 case FS_PREFIX_OPCODE
:
2162 case GS_PREFIX_OPCODE
:
2163 case SS_PREFIX_OPCODE
:
2167 case REPNE_PREFIX_OPCODE
:
2168 case REPE_PREFIX_OPCODE
:
2173 case LOCK_PREFIX_OPCODE
:
2182 case ADDR_PREFIX_OPCODE
:
2186 case DATA_PREFIX_OPCODE
:
2190 if (i
.prefix
[q
] != 0)
2198 i
.prefix
[q
] |= prefix
;
2201 as_bad (_("same type of prefix used twice"));
2207 update_code_flag (int value
, int check
)
2209 PRINTF_LIKE ((*as_error
));
2211 flag_code
= (enum flag_code
) value
;
2212 if (flag_code
== CODE_64BIT
)
2214 cpu_arch_flags
.bitfield
.cpu64
= 1;
2215 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2219 cpu_arch_flags
.bitfield
.cpu64
= 0;
2220 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2222 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2225 as_error
= as_fatal
;
2228 (*as_error
) (_("64bit mode not supported on `%s'."),
2229 cpu_arch_name
? cpu_arch_name
: default_arch
);
2231 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2234 as_error
= as_fatal
;
2237 (*as_error
) (_("32bit mode not supported on `%s'."),
2238 cpu_arch_name
? cpu_arch_name
: default_arch
);
2240 stackop_size
= '\0';
2244 set_code_flag (int value
)
2246 update_code_flag (value
, 0);
2250 set_16bit_gcc_code_flag (int new_code_flag
)
2252 flag_code
= (enum flag_code
) new_code_flag
;
2253 if (flag_code
!= CODE_16BIT
)
2255 cpu_arch_flags
.bitfield
.cpu64
= 0;
2256 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2257 stackop_size
= LONG_MNEM_SUFFIX
;
2261 set_intel_syntax (int syntax_flag
)
2263 /* Find out if register prefixing is specified. */
2264 int ask_naked_reg
= 0;
2267 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2270 int e
= get_symbol_name (&string
);
2272 if (strcmp (string
, "prefix") == 0)
2274 else if (strcmp (string
, "noprefix") == 0)
2277 as_bad (_("bad argument to syntax directive."));
2278 (void) restore_line_pointer (e
);
2280 demand_empty_rest_of_line ();
2282 intel_syntax
= syntax_flag
;
2284 if (ask_naked_reg
== 0)
2285 allow_naked_reg
= (intel_syntax
2286 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2288 allow_naked_reg
= (ask_naked_reg
< 0);
2290 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2292 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2293 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2294 register_prefix
= allow_naked_reg
? "" : "%";
2298 set_intel_mnemonic (int mnemonic_flag
)
2300 intel_mnemonic
= mnemonic_flag
;
2304 set_allow_index_reg (int flag
)
2306 allow_index_reg
= flag
;
2310 set_check (int what
)
2312 enum check_kind
*kind
;
2317 kind
= &operand_check
;
2328 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2331 int e
= get_symbol_name (&string
);
2333 if (strcmp (string
, "none") == 0)
2335 else if (strcmp (string
, "warning") == 0)
2336 *kind
= check_warning
;
2337 else if (strcmp (string
, "error") == 0)
2338 *kind
= check_error
;
2340 as_bad (_("bad argument to %s_check directive."), str
);
2341 (void) restore_line_pointer (e
);
2344 as_bad (_("missing argument for %s_check directive"), str
);
2346 demand_empty_rest_of_line ();
2350 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2351 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2353 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2354 static const char *arch
;
2356 /* Intel LIOM is only supported on ELF. */
2362 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2363 use default_arch. */
2364 arch
= cpu_arch_name
;
2366 arch
= default_arch
;
2369 /* If we are targeting Intel MCU, we must enable it. */
2370 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2371 || new_flag
.bitfield
.cpuiamcu
)
2374 /* If we are targeting Intel L1OM, we must enable it. */
2375 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2376 || new_flag
.bitfield
.cpul1om
)
2379 /* If we are targeting Intel K1OM, we must enable it. */
2380 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2381 || new_flag
.bitfield
.cpuk1om
)
2384 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2389 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2393 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2396 int e
= get_symbol_name (&string
);
2398 i386_cpu_flags flags
;
2400 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2402 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2404 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2408 cpu_arch_name
= cpu_arch
[j
].name
;
2409 cpu_sub_arch_name
= NULL
;
2410 cpu_arch_flags
= cpu_arch
[j
].flags
;
2411 if (flag_code
== CODE_64BIT
)
2413 cpu_arch_flags
.bitfield
.cpu64
= 1;
2414 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2418 cpu_arch_flags
.bitfield
.cpu64
= 0;
2419 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2421 cpu_arch_isa
= cpu_arch
[j
].type
;
2422 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2423 if (!cpu_arch_tune_set
)
2425 cpu_arch_tune
= cpu_arch_isa
;
2426 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2431 flags
= cpu_flags_or (cpu_arch_flags
,
2434 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2436 if (cpu_sub_arch_name
)
2438 char *name
= cpu_sub_arch_name
;
2439 cpu_sub_arch_name
= concat (name
,
2441 (const char *) NULL
);
2445 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2446 cpu_arch_flags
= flags
;
2447 cpu_arch_isa_flags
= flags
;
2449 (void) restore_line_pointer (e
);
2450 demand_empty_rest_of_line ();
2455 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2457 /* Disable an ISA entension. */
2458 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2459 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2461 flags
= cpu_flags_and_not (cpu_arch_flags
,
2462 cpu_noarch
[j
].flags
);
2463 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2465 if (cpu_sub_arch_name
)
2467 char *name
= cpu_sub_arch_name
;
2468 cpu_sub_arch_name
= concat (name
, string
,
2469 (const char *) NULL
);
2473 cpu_sub_arch_name
= xstrdup (string
);
2474 cpu_arch_flags
= flags
;
2475 cpu_arch_isa_flags
= flags
;
2477 (void) restore_line_pointer (e
);
2478 demand_empty_rest_of_line ();
2482 j
= ARRAY_SIZE (cpu_arch
);
2485 if (j
>= ARRAY_SIZE (cpu_arch
))
2486 as_bad (_("no such architecture: `%s'"), string
);
2488 *input_line_pointer
= e
;
2491 as_bad (_("missing cpu architecture"));
2493 no_cond_jump_promotion
= 0;
2494 if (*input_line_pointer
== ','
2495 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2500 ++input_line_pointer
;
2501 e
= get_symbol_name (&string
);
2503 if (strcmp (string
, "nojumps") == 0)
2504 no_cond_jump_promotion
= 1;
2505 else if (strcmp (string
, "jumps") == 0)
2508 as_bad (_("no such architecture modifier: `%s'"), string
);
2510 (void) restore_line_pointer (e
);
2513 demand_empty_rest_of_line ();
2516 enum bfd_architecture
2519 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2521 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2522 || flag_code
!= CODE_64BIT
)
2523 as_fatal (_("Intel L1OM is 64bit ELF only"));
2524 return bfd_arch_l1om
;
2526 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2528 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2529 || flag_code
!= CODE_64BIT
)
2530 as_fatal (_("Intel K1OM is 64bit ELF only"));
2531 return bfd_arch_k1om
;
2533 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2535 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2536 || flag_code
== CODE_64BIT
)
2537 as_fatal (_("Intel MCU is 32bit ELF only"));
2538 return bfd_arch_iamcu
;
2541 return bfd_arch_i386
;
2547 if (!strncmp (default_arch
, "x86_64", 6))
2549 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2551 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2552 || default_arch
[6] != '\0')
2553 as_fatal (_("Intel L1OM is 64bit ELF only"));
2554 return bfd_mach_l1om
;
2556 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2558 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2559 || default_arch
[6] != '\0')
2560 as_fatal (_("Intel K1OM is 64bit ELF only"));
2561 return bfd_mach_k1om
;
2563 else if (default_arch
[6] == '\0')
2564 return bfd_mach_x86_64
;
2566 return bfd_mach_x64_32
;
2568 else if (!strcmp (default_arch
, "i386")
2569 || !strcmp (default_arch
, "iamcu"))
2571 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2573 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2574 as_fatal (_("Intel MCU is 32bit ELF only"));
2575 return bfd_mach_i386_iamcu
;
2578 return bfd_mach_i386_i386
;
2581 as_fatal (_("unknown architecture"));
2587 const char *hash_err
;
2589 /* Initialize op_hash hash table. */
2590 op_hash
= hash_new ();
2593 const insn_template
*optab
;
2594 templates
*core_optab
;
2596 /* Setup for loop. */
2598 core_optab
= XNEW (templates
);
2599 core_optab
->start
= optab
;
2604 if (optab
->name
== NULL
2605 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2607 /* different name --> ship out current template list;
2608 add to hash table; & begin anew. */
2609 core_optab
->end
= optab
;
2610 hash_err
= hash_insert (op_hash
,
2612 (void *) core_optab
);
2615 as_fatal (_("can't hash %s: %s"),
2619 if (optab
->name
== NULL
)
2621 core_optab
= XNEW (templates
);
2622 core_optab
->start
= optab
;
2627 /* Initialize reg_hash hash table. */
2628 reg_hash
= hash_new ();
2630 const reg_entry
*regtab
;
2631 unsigned int regtab_size
= i386_regtab_size
;
2633 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2635 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2637 as_fatal (_("can't hash %s: %s"),
2643 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2648 for (c
= 0; c
< 256; c
++)
2653 mnemonic_chars
[c
] = c
;
2654 register_chars
[c
] = c
;
2655 operand_chars
[c
] = c
;
2657 else if (ISLOWER (c
))
2659 mnemonic_chars
[c
] = c
;
2660 register_chars
[c
] = c
;
2661 operand_chars
[c
] = c
;
2663 else if (ISUPPER (c
))
2665 mnemonic_chars
[c
] = TOLOWER (c
);
2666 register_chars
[c
] = mnemonic_chars
[c
];
2667 operand_chars
[c
] = c
;
2669 else if (c
== '{' || c
== '}')
2670 operand_chars
[c
] = c
;
2672 if (ISALPHA (c
) || ISDIGIT (c
))
2673 identifier_chars
[c
] = c
;
2676 identifier_chars
[c
] = c
;
2677 operand_chars
[c
] = c
;
2682 identifier_chars
['@'] = '@';
2685 identifier_chars
['?'] = '?';
2686 operand_chars
['?'] = '?';
2688 digit_chars
['-'] = '-';
2689 mnemonic_chars
['_'] = '_';
2690 mnemonic_chars
['-'] = '-';
2691 mnemonic_chars
['.'] = '.';
2692 identifier_chars
['_'] = '_';
2693 identifier_chars
['.'] = '.';
2695 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2696 operand_chars
[(unsigned char) *p
] = *p
;
2699 if (flag_code
== CODE_64BIT
)
2701 #if defined (OBJ_COFF) && defined (TE_PE)
2702 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2705 x86_dwarf2_return_column
= 16;
2707 x86_cie_data_alignment
= -8;
2711 x86_dwarf2_return_column
= 8;
2712 x86_cie_data_alignment
= -4;
2717 i386_print_statistics (FILE *file
)
2719 hash_print_statistics (file
, "i386 opcode", op_hash
);
2720 hash_print_statistics (file
, "i386 register", reg_hash
);
2725 /* Debugging routines for md_assemble. */
2726 static void pte (insn_template
*);
2727 static void pt (i386_operand_type
);
2728 static void pe (expressionS
*);
2729 static void ps (symbolS
*);
2732 pi (char *line
, i386_insn
*x
)
2736 fprintf (stdout
, "%s: template ", line
);
2738 fprintf (stdout
, " address: base %s index %s scale %x\n",
2739 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2740 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2741 x
->log2_scale_factor
);
2742 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2743 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2744 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2745 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2746 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2747 (x
->rex
& REX_W
) != 0,
2748 (x
->rex
& REX_R
) != 0,
2749 (x
->rex
& REX_X
) != 0,
2750 (x
->rex
& REX_B
) != 0);
2751 for (j
= 0; j
< x
->operands
; j
++)
2753 fprintf (stdout
, " #%d: ", j
+ 1);
2755 fprintf (stdout
, "\n");
2756 if (x
->types
[j
].bitfield
.reg8
2757 || x
->types
[j
].bitfield
.reg16
2758 || x
->types
[j
].bitfield
.reg32
2759 || x
->types
[j
].bitfield
.reg64
2760 || x
->types
[j
].bitfield
.regmmx
2761 || x
->types
[j
].bitfield
.regxmm
2762 || x
->types
[j
].bitfield
.regymm
2763 || x
->types
[j
].bitfield
.regzmm
2764 || x
->types
[j
].bitfield
.sreg2
2765 || x
->types
[j
].bitfield
.sreg3
2766 || x
->types
[j
].bitfield
.control
2767 || x
->types
[j
].bitfield
.debug
2768 || x
->types
[j
].bitfield
.test
)
2769 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2770 if (operand_type_check (x
->types
[j
], imm
))
2772 if (operand_type_check (x
->types
[j
], disp
))
2773 pe (x
->op
[j
].disps
);
2778 pte (insn_template
*t
)
2781 fprintf (stdout
, " %d operands ", t
->operands
);
2782 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2783 if (t
->extension_opcode
!= None
)
2784 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2785 if (t
->opcode_modifier
.d
)
2786 fprintf (stdout
, "D");
2787 if (t
->opcode_modifier
.w
)
2788 fprintf (stdout
, "W");
2789 fprintf (stdout
, "\n");
2790 for (j
= 0; j
< t
->operands
; j
++)
2792 fprintf (stdout
, " #%d type ", j
+ 1);
2793 pt (t
->operand_types
[j
]);
2794 fprintf (stdout
, "\n");
2801 fprintf (stdout
, " operation %d\n", e
->X_op
);
2802 fprintf (stdout
, " add_number %ld (%lx)\n",
2803 (long) e
->X_add_number
, (long) e
->X_add_number
);
2804 if (e
->X_add_symbol
)
2806 fprintf (stdout
, " add_symbol ");
2807 ps (e
->X_add_symbol
);
2808 fprintf (stdout
, "\n");
2812 fprintf (stdout
, " op_symbol ");
2813 ps (e
->X_op_symbol
);
2814 fprintf (stdout
, "\n");
2821 fprintf (stdout
, "%s type %s%s",
2823 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2824 segment_name (S_GET_SEGMENT (s
)));
2827 static struct type_name
2829 i386_operand_type mask
;
2832 const type_names
[] =
2834 { OPERAND_TYPE_REG8
, "r8" },
2835 { OPERAND_TYPE_REG16
, "r16" },
2836 { OPERAND_TYPE_REG32
, "r32" },
2837 { OPERAND_TYPE_REG64
, "r64" },
2838 { OPERAND_TYPE_IMM8
, "i8" },
2839 { OPERAND_TYPE_IMM8
, "i8s" },
2840 { OPERAND_TYPE_IMM16
, "i16" },
2841 { OPERAND_TYPE_IMM32
, "i32" },
2842 { OPERAND_TYPE_IMM32S
, "i32s" },
2843 { OPERAND_TYPE_IMM64
, "i64" },
2844 { OPERAND_TYPE_IMM1
, "i1" },
2845 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2846 { OPERAND_TYPE_DISP8
, "d8" },
2847 { OPERAND_TYPE_DISP16
, "d16" },
2848 { OPERAND_TYPE_DISP32
, "d32" },
2849 { OPERAND_TYPE_DISP32S
, "d32s" },
2850 { OPERAND_TYPE_DISP64
, "d64" },
2851 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2852 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2853 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2854 { OPERAND_TYPE_CONTROL
, "control reg" },
2855 { OPERAND_TYPE_TEST
, "test reg" },
2856 { OPERAND_TYPE_DEBUG
, "debug reg" },
2857 { OPERAND_TYPE_FLOATREG
, "FReg" },
2858 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2859 { OPERAND_TYPE_SREG2
, "SReg2" },
2860 { OPERAND_TYPE_SREG3
, "SReg3" },
2861 { OPERAND_TYPE_ACC
, "Acc" },
2862 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2863 { OPERAND_TYPE_REGMMX
, "rMMX" },
2864 { OPERAND_TYPE_REGXMM
, "rXMM" },
2865 { OPERAND_TYPE_REGYMM
, "rYMM" },
2866 { OPERAND_TYPE_REGZMM
, "rZMM" },
2867 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2868 { OPERAND_TYPE_ESSEG
, "es" },
2872 pt (i386_operand_type t
)
2875 i386_operand_type a
;
2877 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2879 a
= operand_type_and (t
, type_names
[j
].mask
);
2880 if (!operand_type_all_zero (&a
))
2881 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2886 #endif /* DEBUG386 */
2888 static bfd_reloc_code_real_type
2889 reloc (unsigned int size
,
2892 bfd_reloc_code_real_type other
)
2894 if (other
!= NO_RELOC
)
2896 reloc_howto_type
*rel
;
2901 case BFD_RELOC_X86_64_GOT32
:
2902 return BFD_RELOC_X86_64_GOT64
;
2904 case BFD_RELOC_X86_64_GOTPLT64
:
2905 return BFD_RELOC_X86_64_GOTPLT64
;
2907 case BFD_RELOC_X86_64_PLTOFF64
:
2908 return BFD_RELOC_X86_64_PLTOFF64
;
2910 case BFD_RELOC_X86_64_GOTPC32
:
2911 other
= BFD_RELOC_X86_64_GOTPC64
;
2913 case BFD_RELOC_X86_64_GOTPCREL
:
2914 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2916 case BFD_RELOC_X86_64_TPOFF32
:
2917 other
= BFD_RELOC_X86_64_TPOFF64
;
2919 case BFD_RELOC_X86_64_DTPOFF32
:
2920 other
= BFD_RELOC_X86_64_DTPOFF64
;
2926 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2927 if (other
== BFD_RELOC_SIZE32
)
2930 other
= BFD_RELOC_SIZE64
;
2933 as_bad (_("there are no pc-relative size relocations"));
2939 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2940 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2943 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2945 as_bad (_("unknown relocation (%u)"), other
);
2946 else if (size
!= bfd_get_reloc_size (rel
))
2947 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2948 bfd_get_reloc_size (rel
),
2950 else if (pcrel
&& !rel
->pc_relative
)
2951 as_bad (_("non-pc-relative relocation for pc-relative field"));
2952 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2954 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2956 as_bad (_("relocated field and relocation type differ in signedness"));
2965 as_bad (_("there are no unsigned pc-relative relocations"));
2968 case 1: return BFD_RELOC_8_PCREL
;
2969 case 2: return BFD_RELOC_16_PCREL
;
2970 case 4: return BFD_RELOC_32_PCREL
;
2971 case 8: return BFD_RELOC_64_PCREL
;
2973 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2980 case 4: return BFD_RELOC_X86_64_32S
;
2985 case 1: return BFD_RELOC_8
;
2986 case 2: return BFD_RELOC_16
;
2987 case 4: return BFD_RELOC_32
;
2988 case 8: return BFD_RELOC_64
;
2990 as_bad (_("cannot do %s %u byte relocation"),
2991 sign
> 0 ? "signed" : "unsigned", size
);
2997 /* Here we decide which fixups can be adjusted to make them relative to
2998 the beginning of the section instead of the symbol. Basically we need
2999 to make sure that the dynamic relocations are done correctly, so in
3000 some cases we force the original symbol to be used. */
3003 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3005 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3009 /* Don't adjust pc-relative references to merge sections in 64-bit
3011 if (use_rela_relocations
3012 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3016 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3017 and changed later by validate_fix. */
3018 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3019 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3022 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3023 for size relocations. */
3024 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3025 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3026 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3027 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3028 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3029 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3030 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3031 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3032 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3033 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3034 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3035 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3036 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3037 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3038 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3039 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3040 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3041 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3042 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3043 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3044 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3045 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3046 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3047 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3048 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3049 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3050 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3051 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3052 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3053 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3054 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3055 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3056 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3063 intel_float_operand (const char *mnemonic
)
3065 /* Note that the value returned is meaningful only for opcodes with (memory)
3066 operands, hence the code here is free to improperly handle opcodes that
3067 have no operands (for better performance and smaller code). */
3069 if (mnemonic
[0] != 'f')
3070 return 0; /* non-math */
3072 switch (mnemonic
[1])
3074 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3075 the fs segment override prefix not currently handled because no
3076 call path can make opcodes without operands get here */
3078 return 2 /* integer op */;
3080 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3081 return 3; /* fldcw/fldenv */
3084 if (mnemonic
[2] != 'o' /* fnop */)
3085 return 3; /* non-waiting control op */
3088 if (mnemonic
[2] == 's')
3089 return 3; /* frstor/frstpm */
3092 if (mnemonic
[2] == 'a')
3093 return 3; /* fsave */
3094 if (mnemonic
[2] == 't')
3096 switch (mnemonic
[3])
3098 case 'c': /* fstcw */
3099 case 'd': /* fstdw */
3100 case 'e': /* fstenv */
3101 case 's': /* fsts[gw] */
3107 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3108 return 0; /* fxsave/fxrstor are not really math ops */
3115 /* Build the VEX prefix. */
3118 build_vex_prefix (const insn_template
*t
)
3120 unsigned int register_specifier
;
3121 unsigned int implied_prefix
;
3122 unsigned int vector_length
;
3124 /* Check register specifier. */
3125 if (i
.vex
.register_specifier
)
3127 register_specifier
=
3128 ~register_number (i
.vex
.register_specifier
) & 0xf;
3129 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3132 register_specifier
= 0xf;
3134 /* Use 2-byte VEX prefix by swappping destination and source
3137 && i
.operands
== i
.reg_operands
3138 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3139 && i
.tm
.opcode_modifier
.s
3142 unsigned int xchg
= i
.operands
- 1;
3143 union i386_op temp_op
;
3144 i386_operand_type temp_type
;
3146 temp_type
= i
.types
[xchg
];
3147 i
.types
[xchg
] = i
.types
[0];
3148 i
.types
[0] = temp_type
;
3149 temp_op
= i
.op
[xchg
];
3150 i
.op
[xchg
] = i
.op
[0];
3153 gas_assert (i
.rm
.mode
== 3);
3157 i
.rm
.regmem
= i
.rm
.reg
;
3160 /* Use the next insn. */
3164 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3165 vector_length
= avxscalar
;
3167 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3169 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3174 case DATA_PREFIX_OPCODE
:
3177 case REPE_PREFIX_OPCODE
:
3180 case REPNE_PREFIX_OPCODE
:
3187 /* Use 2-byte VEX prefix if possible. */
3188 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3189 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3190 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3192 /* 2-byte VEX prefix. */
3196 i
.vex
.bytes
[0] = 0xc5;
3198 /* Check the REX.R bit. */
3199 r
= (i
.rex
& REX_R
) ? 0 : 1;
3200 i
.vex
.bytes
[1] = (r
<< 7
3201 | register_specifier
<< 3
3202 | vector_length
<< 2
3207 /* 3-byte VEX prefix. */
3212 switch (i
.tm
.opcode_modifier
.vexopcode
)
3216 i
.vex
.bytes
[0] = 0xc4;
3220 i
.vex
.bytes
[0] = 0xc4;
3224 i
.vex
.bytes
[0] = 0xc4;
3228 i
.vex
.bytes
[0] = 0x8f;
3232 i
.vex
.bytes
[0] = 0x8f;
3236 i
.vex
.bytes
[0] = 0x8f;
3242 /* The high 3 bits of the second VEX byte are 1's compliment
3243 of RXB bits from REX. */
3244 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3246 /* Check the REX.W bit. */
3247 w
= (i
.rex
& REX_W
) ? 1 : 0;
3248 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3251 i
.vex
.bytes
[2] = (w
<< 7
3252 | register_specifier
<< 3
3253 | vector_length
<< 2
3258 /* Build the EVEX prefix. */
3261 build_evex_prefix (void)
3263 unsigned int register_specifier
;
3264 unsigned int implied_prefix
;
3266 rex_byte vrex_used
= 0;
3268 /* Check register specifier. */
3269 if (i
.vex
.register_specifier
)
3271 gas_assert ((i
.vrex
& REX_X
) == 0);
3273 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3274 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3275 register_specifier
+= 8;
3276 /* The upper 16 registers are encoded in the fourth byte of the
3278 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3279 i
.vex
.bytes
[3] = 0x8;
3280 register_specifier
= ~register_specifier
& 0xf;
3284 register_specifier
= 0xf;
3286 /* Encode upper 16 vector index register in the fourth byte of
3288 if (!(i
.vrex
& REX_X
))
3289 i
.vex
.bytes
[3] = 0x8;
3294 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3299 case DATA_PREFIX_OPCODE
:
3302 case REPE_PREFIX_OPCODE
:
3305 case REPNE_PREFIX_OPCODE
:
3312 /* 4 byte EVEX prefix. */
3314 i
.vex
.bytes
[0] = 0x62;
3317 switch (i
.tm
.opcode_modifier
.vexopcode
)
3333 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3335 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3337 /* The fifth bit of the second EVEX byte is 1's compliment of the
3338 REX_R bit in VREX. */
3339 if (!(i
.vrex
& REX_R
))
3340 i
.vex
.bytes
[1] |= 0x10;
3344 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3346 /* When all operands are registers, the REX_X bit in REX is not
3347 used. We reuse it to encode the upper 16 registers, which is
3348 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3349 as 1's compliment. */
3350 if ((i
.vrex
& REX_B
))
3353 i
.vex
.bytes
[1] &= ~0x40;
3357 /* EVEX instructions shouldn't need the REX prefix. */
3358 i
.vrex
&= ~vrex_used
;
3359 gas_assert (i
.vrex
== 0);
3361 /* Check the REX.W bit. */
3362 w
= (i
.rex
& REX_W
) ? 1 : 0;
3363 if (i
.tm
.opcode_modifier
.vexw
)
3365 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3368 /* If w is not set it means we are dealing with WIG instruction. */
3371 if (evexwig
== evexw1
)
3375 /* Encode the U bit. */
3376 implied_prefix
|= 0x4;
3378 /* The third byte of the EVEX prefix. */
3379 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3381 /* The fourth byte of the EVEX prefix. */
3382 /* The zeroing-masking bit. */
3383 if (i
.mask
&& i
.mask
->zeroing
)
3384 i
.vex
.bytes
[3] |= 0x80;
3386 /* Don't always set the broadcast bit if there is no RC. */
3389 /* Encode the vector length. */
3390 unsigned int vec_length
;
3392 switch (i
.tm
.opcode_modifier
.evex
)
3394 case EVEXLIG
: /* LL' is ignored */
3395 vec_length
= evexlig
<< 5;
3398 vec_length
= 0 << 5;
3401 vec_length
= 1 << 5;
3404 vec_length
= 2 << 5;
3410 i
.vex
.bytes
[3] |= vec_length
;
3411 /* Encode the broadcast bit. */
3413 i
.vex
.bytes
[3] |= 0x10;
3417 if (i
.rounding
->type
!= saeonly
)
3418 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3420 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3423 if (i
.mask
&& i
.mask
->mask
)
3424 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3428 process_immext (void)
3432 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3435 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3436 with an opcode suffix which is coded in the same place as an
3437 8-bit immediate field would be.
3438 Here we check those operands and remove them afterwards. */
3441 for (x
= 0; x
< i
.operands
; x
++)
3442 if (register_number (i
.op
[x
].regs
) != x
)
3443 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3444 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3450 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3452 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3453 suffix which is coded in the same place as an 8-bit immediate
3455 Here we check those operands and remove them afterwards. */
3458 if (i
.operands
!= 3)
3461 for (x
= 0; x
< 2; x
++)
3462 if (register_number (i
.op
[x
].regs
) != x
)
3463 goto bad_register_operand
;
3465 /* Check for third operand for mwaitx/monitorx insn. */
3466 if (register_number (i
.op
[x
].regs
)
3467 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3469 bad_register_operand
:
3470 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3471 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3478 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3479 which is coded in the same place as an 8-bit immediate field
3480 would be. Here we fake an 8-bit immediate operand from the
3481 opcode suffix stored in tm.extension_opcode.
3483 AVX instructions also use this encoding, for some of
3484 3 argument instructions. */
3486 gas_assert (i
.imm_operands
<= 1
3488 || ((i
.tm
.opcode_modifier
.vex
3489 || i
.tm
.opcode_modifier
.evex
)
3490 && i
.operands
<= 4)));
3492 exp
= &im_expressions
[i
.imm_operands
++];
3493 i
.op
[i
.operands
].imms
= exp
;
3494 i
.types
[i
.operands
] = imm8
;
3496 exp
->X_op
= O_constant
;
3497 exp
->X_add_number
= i
.tm
.extension_opcode
;
3498 i
.tm
.extension_opcode
= None
;
3505 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3510 as_bad (_("invalid instruction `%s' after `%s'"),
3511 i
.tm
.name
, i
.hle_prefix
);
3514 if (i
.prefix
[LOCK_PREFIX
])
3516 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3520 case HLEPrefixRelease
:
3521 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3523 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3527 if (i
.mem_operands
== 0
3528 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3530 as_bad (_("memory destination needed for instruction `%s'"
3531 " after `xrelease'"), i
.tm
.name
);
3538 /* This is the guts of the machine-dependent assembler. LINE points to a
3539 machine dependent instruction. This function is supposed to emit
3540 the frags/bytes it assembles to. */
3543 md_assemble (char *line
)
3546 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
3547 const insn_template
*t
;
3549 /* Initialize globals. */
3550 memset (&i
, '\0', sizeof (i
));
3551 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3552 i
.reloc
[j
] = NO_RELOC
;
3553 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3554 memset (im_expressions
, '\0', sizeof (im_expressions
));
3555 save_stack_p
= save_stack
;
3557 /* First parse an instruction mnemonic & call i386_operand for the operands.
3558 We assume that the scrubber has arranged it so that line[0] is the valid
3559 start of a (possibly prefixed) mnemonic. */
3561 line
= parse_insn (line
, mnemonic
);
3564 mnem_suffix
= i
.suffix
;
3566 line
= parse_operands (line
, mnemonic
);
3568 xfree (i
.memop1_string
);
3569 i
.memop1_string
= NULL
;
3573 /* Now we've parsed the mnemonic into a set of templates, and have the
3574 operands at hand. */
3576 /* All intel opcodes have reversed operands except for "bound" and
3577 "enter". We also don't reverse intersegment "jmp" and "call"
3578 instructions with 2 immediate operands so that the immediate segment
3579 precedes the offset, as it does when in AT&T mode. */
3582 && (strcmp (mnemonic
, "bound") != 0)
3583 && (strcmp (mnemonic
, "invlpga") != 0)
3584 && !(operand_type_check (i
.types
[0], imm
)
3585 && operand_type_check (i
.types
[1], imm
)))
3588 /* The order of the immediates should be reversed
3589 for 2 immediates extrq and insertq instructions */
3590 if (i
.imm_operands
== 2
3591 && (strcmp (mnemonic
, "extrq") == 0
3592 || strcmp (mnemonic
, "insertq") == 0))
3593 swap_2_operands (0, 1);
3598 /* Don't optimize displacement for movabs since it only takes 64bit
3601 && i
.disp_encoding
!= disp_encoding_32bit
3602 && (flag_code
!= CODE_64BIT
3603 || strcmp (mnemonic
, "movabs") != 0))
3606 /* Next, we find a template that matches the given insn,
3607 making sure the overlap of the given operands types is consistent
3608 with the template operand types. */
3610 if (!(t
= match_template (mnem_suffix
)))
3613 if (sse_check
!= check_none
3614 && !i
.tm
.opcode_modifier
.noavx
3615 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3616 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3617 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3618 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3619 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3620 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3622 (sse_check
== check_warning
3624 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3627 /* Zap movzx and movsx suffix. The suffix has been set from
3628 "word ptr" or "byte ptr" on the source operand in Intel syntax
3629 or extracted from mnemonic in AT&T syntax. But we'll use
3630 the destination register to choose the suffix for encoding. */
3631 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3633 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3634 there is no suffix, the default will be byte extension. */
3635 if (i
.reg_operands
!= 2
3638 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3643 if (i
.tm
.opcode_modifier
.fwait
)
3644 if (!add_prefix (FWAIT_OPCODE
))
3647 /* Check if REP prefix is OK. */
3648 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3650 as_bad (_("invalid instruction `%s' after `%s'"),
3651 i
.tm
.name
, i
.rep_prefix
);
3655 /* Check for lock without a lockable instruction. Destination operand
3656 must be memory unless it is xchg (0x86). */
3657 if (i
.prefix
[LOCK_PREFIX
]
3658 && (!i
.tm
.opcode_modifier
.islockable
3659 || i
.mem_operands
== 0
3660 || (i
.tm
.base_opcode
!= 0x86
3661 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3663 as_bad (_("expecting lockable instruction after `lock'"));
3667 /* Check if HLE prefix is OK. */
3668 if (i
.hle_prefix
&& !check_hle ())
3671 /* Check BND prefix. */
3672 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3673 as_bad (_("expecting valid branch instruction after `bnd'"));
3675 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
3677 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
3678 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3679 else if (flag_code
!= CODE_16BIT
3680 ? i
.prefix
[ADDR_PREFIX
]
3681 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
3682 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3685 /* Insert BND prefix. */
3687 && i
.tm
.opcode_modifier
.bndprefixok
3688 && !i
.prefix
[BND_PREFIX
])
3689 add_prefix (BND_PREFIX_OPCODE
);
3691 /* Check string instruction segment overrides. */
3692 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3694 if (!check_string ())
3696 i
.disp_operands
= 0;
3699 if (!process_suffix ())
3702 /* Update operand types. */
3703 for (j
= 0; j
< i
.operands
; j
++)
3704 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3706 /* Make still unresolved immediate matches conform to size of immediate
3707 given in i.suffix. */
3708 if (!finalize_imm ())
3711 if (i
.types
[0].bitfield
.imm1
)
3712 i
.imm_operands
= 0; /* kludge for shift insns. */
3714 /* We only need to check those implicit registers for instructions
3715 with 3 operands or less. */
3716 if (i
.operands
<= 3)
3717 for (j
= 0; j
< i
.operands
; j
++)
3718 if (i
.types
[j
].bitfield
.inoutportreg
3719 || i
.types
[j
].bitfield
.shiftcount
3720 || i
.types
[j
].bitfield
.acc
3721 || i
.types
[j
].bitfield
.floatacc
)
3724 /* ImmExt should be processed after SSE2AVX. */
3725 if (!i
.tm
.opcode_modifier
.sse2avx
3726 && i
.tm
.opcode_modifier
.immext
)
3729 /* For insns with operands there are more diddles to do to the opcode. */
3732 if (!process_operands ())
3735 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3737 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3738 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3741 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3743 if (flag_code
== CODE_16BIT
)
3745 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3750 if (i
.tm
.opcode_modifier
.vex
)
3751 build_vex_prefix (t
);
3753 build_evex_prefix ();
3756 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3757 instructions may define INT_OPCODE as well, so avoid this corner
3758 case for those instructions that use MODRM. */
3759 if (i
.tm
.base_opcode
== INT_OPCODE
3760 && !i
.tm
.opcode_modifier
.modrm
3761 && i
.op
[0].imms
->X_add_number
== 3)
3763 i
.tm
.base_opcode
= INT3_OPCODE
;
3767 if ((i
.tm
.opcode_modifier
.jump
3768 || i
.tm
.opcode_modifier
.jumpbyte
3769 || i
.tm
.opcode_modifier
.jumpdword
)
3770 && i
.op
[0].disps
->X_op
== O_constant
)
3772 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3773 the absolute address given by the constant. Since ix86 jumps and
3774 calls are pc relative, we need to generate a reloc. */
3775 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3776 i
.op
[0].disps
->X_op
= O_symbol
;
3779 if (i
.tm
.opcode_modifier
.rex64
)
3782 /* For 8 bit registers we need an empty rex prefix. Also if the
3783 instruction already has a prefix, we need to convert old
3784 registers to new ones. */
3786 if ((i
.types
[0].bitfield
.reg8
3787 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3788 || (i
.types
[1].bitfield
.reg8
3789 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3790 || ((i
.types
[0].bitfield
.reg8
3791 || i
.types
[1].bitfield
.reg8
)
3796 i
.rex
|= REX_OPCODE
;
3797 for (x
= 0; x
< 2; x
++)
3799 /* Look for 8 bit operand that uses old registers. */
3800 if (i
.types
[x
].bitfield
.reg8
3801 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3803 /* In case it is "hi" register, give up. */
3804 if (i
.op
[x
].regs
->reg_num
> 3)
3805 as_bad (_("can't encode register '%s%s' in an "
3806 "instruction requiring REX prefix."),
3807 register_prefix
, i
.op
[x
].regs
->reg_name
);
3809 /* Otherwise it is equivalent to the extended register.
3810 Since the encoding doesn't change this is merely
3811 cosmetic cleanup for debug output. */
3813 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3819 add_prefix (REX_OPCODE
| i
.rex
);
3821 /* We are ready to output the insn. */
3826 parse_insn (char *line
, char *mnemonic
)
3829 char *token_start
= l
;
3832 const insn_template
*t
;
3838 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3843 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3845 as_bad (_("no such instruction: `%s'"), token_start
);
3850 if (!is_space_char (*l
)
3851 && *l
!= END_OF_INSN
3853 || (*l
!= PREFIX_SEPARATOR
3856 as_bad (_("invalid character %s in mnemonic"),
3857 output_invalid (*l
));
3860 if (token_start
== l
)
3862 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3863 as_bad (_("expecting prefix; got nothing"));
3865 as_bad (_("expecting mnemonic; got nothing"));
3869 /* Look up instruction (or prefix) via hash table. */
3870 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3872 if (*l
!= END_OF_INSN
3873 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3874 && current_templates
3875 && current_templates
->start
->opcode_modifier
.isprefix
)
3877 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3879 as_bad ((flag_code
!= CODE_64BIT
3880 ? _("`%s' is only supported in 64-bit mode")
3881 : _("`%s' is not supported in 64-bit mode")),
3882 current_templates
->start
->name
);
3885 /* If we are in 16-bit mode, do not allow addr16 or data16.
3886 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3887 if ((current_templates
->start
->opcode_modifier
.size16
3888 || current_templates
->start
->opcode_modifier
.size32
)
3889 && flag_code
!= CODE_64BIT
3890 && (current_templates
->start
->opcode_modifier
.size32
3891 ^ (flag_code
== CODE_16BIT
)))
3893 as_bad (_("redundant %s prefix"),
3894 current_templates
->start
->name
);
3897 /* Add prefix, checking for repeated prefixes. */
3898 switch (add_prefix (current_templates
->start
->base_opcode
))
3903 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3904 i
.hle_prefix
= current_templates
->start
->name
;
3905 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3906 i
.bnd_prefix
= current_templates
->start
->name
;
3908 i
.rep_prefix
= current_templates
->start
->name
;
3913 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3920 if (!current_templates
)
3922 /* Check if we should swap operand or force 32bit displacement in
3924 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3926 else if (mnem_p
- 3 == dot_p
3929 i
.disp_encoding
= disp_encoding_8bit
;
3930 else if (mnem_p
- 4 == dot_p
3934 i
.disp_encoding
= disp_encoding_32bit
;
3939 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3942 if (!current_templates
)
3945 /* See if we can get a match by trimming off a suffix. */
3948 case WORD_MNEM_SUFFIX
:
3949 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3950 i
.suffix
= SHORT_MNEM_SUFFIX
;
3953 case BYTE_MNEM_SUFFIX
:
3954 case QWORD_MNEM_SUFFIX
:
3955 i
.suffix
= mnem_p
[-1];
3957 current_templates
= (const templates
*) hash_find (op_hash
,
3960 case SHORT_MNEM_SUFFIX
:
3961 case LONG_MNEM_SUFFIX
:
3964 i
.suffix
= mnem_p
[-1];
3966 current_templates
= (const templates
*) hash_find (op_hash
,
3975 if (intel_float_operand (mnemonic
) == 1)
3976 i
.suffix
= SHORT_MNEM_SUFFIX
;
3978 i
.suffix
= LONG_MNEM_SUFFIX
;
3980 current_templates
= (const templates
*) hash_find (op_hash
,
3985 if (!current_templates
)
3987 as_bad (_("no such instruction: `%s'"), token_start
);
3992 if (current_templates
->start
->opcode_modifier
.jump
3993 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3995 /* Check for a branch hint. We allow ",pt" and ",pn" for
3996 predict taken and predict not taken respectively.
3997 I'm not sure that branch hints actually do anything on loop
3998 and jcxz insns (JumpByte) for current Pentium4 chips. They
3999 may work in the future and it doesn't hurt to accept them
4001 if (l
[0] == ',' && l
[1] == 'p')
4005 if (!add_prefix (DS_PREFIX_OPCODE
))
4009 else if (l
[2] == 'n')
4011 if (!add_prefix (CS_PREFIX_OPCODE
))
4017 /* Any other comma loses. */
4020 as_bad (_("invalid character %s in mnemonic"),
4021 output_invalid (*l
));
4025 /* Check if instruction is supported on specified architecture. */
4027 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4029 supported
|= cpu_flags_match (t
);
4030 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4034 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4036 as_bad (flag_code
== CODE_64BIT
4037 ? _("`%s' is not supported in 64-bit mode")
4038 : _("`%s' is only supported in 64-bit mode"),
4039 current_templates
->start
->name
);
4042 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
4044 as_bad (_("`%s' is not supported on `%s%s'"),
4045 current_templates
->start
->name
,
4046 cpu_arch_name
? cpu_arch_name
: default_arch
,
4047 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4052 if (!cpu_arch_flags
.bitfield
.cpui386
4053 && (flag_code
!= CODE_16BIT
))
4055 as_warn (_("use .code16 to ensure correct addressing mode"));
4062 parse_operands (char *l
, const char *mnemonic
)
4066 /* 1 if operand is pending after ','. */
4067 unsigned int expecting_operand
= 0;
4069 /* Non-zero if operand parens not balanced. */
4070 unsigned int paren_not_balanced
;
4072 while (*l
!= END_OF_INSN
)
4074 /* Skip optional white space before operand. */
4075 if (is_space_char (*l
))
4077 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4079 as_bad (_("invalid character %s before operand %d"),
4080 output_invalid (*l
),
4084 token_start
= l
; /* After white space. */
4085 paren_not_balanced
= 0;
4086 while (paren_not_balanced
|| *l
!= ',')
4088 if (*l
== END_OF_INSN
)
4090 if (paren_not_balanced
)
4093 as_bad (_("unbalanced parenthesis in operand %d."),
4096 as_bad (_("unbalanced brackets in operand %d."),
4101 break; /* we are done */
4103 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4105 as_bad (_("invalid character %s in operand %d"),
4106 output_invalid (*l
),
4113 ++paren_not_balanced
;
4115 --paren_not_balanced
;
4120 ++paren_not_balanced
;
4122 --paren_not_balanced
;
4126 if (l
!= token_start
)
4127 { /* Yes, we've read in another operand. */
4128 unsigned int operand_ok
;
4129 this_operand
= i
.operands
++;
4130 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4131 if (i
.operands
> MAX_OPERANDS
)
4133 as_bad (_("spurious operands; (%d operands/instruction max)"),
4137 /* Now parse operand adding info to 'i' as we go along. */
4138 END_STRING_AND_SAVE (l
);
4142 i386_intel_operand (token_start
,
4143 intel_float_operand (mnemonic
));
4145 operand_ok
= i386_att_operand (token_start
);
4147 RESTORE_END_STRING (l
);
4153 if (expecting_operand
)
4155 expecting_operand_after_comma
:
4156 as_bad (_("expecting operand after ','; got nothing"));
4161 as_bad (_("expecting operand before ','; got nothing"));
4166 /* Now *l must be either ',' or END_OF_INSN. */
4169 if (*++l
== END_OF_INSN
)
4171 /* Just skip it, if it's \n complain. */
4172 goto expecting_operand_after_comma
;
4174 expecting_operand
= 1;
4181 swap_2_operands (int xchg1
, int xchg2
)
4183 union i386_op temp_op
;
4184 i386_operand_type temp_type
;
4185 enum bfd_reloc_code_real temp_reloc
;
4187 temp_type
= i
.types
[xchg2
];
4188 i
.types
[xchg2
] = i
.types
[xchg1
];
4189 i
.types
[xchg1
] = temp_type
;
4190 temp_op
= i
.op
[xchg2
];
4191 i
.op
[xchg2
] = i
.op
[xchg1
];
4192 i
.op
[xchg1
] = temp_op
;
4193 temp_reloc
= i
.reloc
[xchg2
];
4194 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4195 i
.reloc
[xchg1
] = temp_reloc
;
4199 if (i
.mask
->operand
== xchg1
)
4200 i
.mask
->operand
= xchg2
;
4201 else if (i
.mask
->operand
== xchg2
)
4202 i
.mask
->operand
= xchg1
;
4206 if (i
.broadcast
->operand
== xchg1
)
4207 i
.broadcast
->operand
= xchg2
;
4208 else if (i
.broadcast
->operand
== xchg2
)
4209 i
.broadcast
->operand
= xchg1
;
4213 if (i
.rounding
->operand
== xchg1
)
4214 i
.rounding
->operand
= xchg2
;
4215 else if (i
.rounding
->operand
== xchg2
)
4216 i
.rounding
->operand
= xchg1
;
4221 swap_operands (void)
4227 swap_2_operands (1, i
.operands
- 2);
4231 swap_2_operands (0, i
.operands
- 1);
4237 if (i
.mem_operands
== 2)
4239 const seg_entry
*temp_seg
;
4240 temp_seg
= i
.seg
[0];
4241 i
.seg
[0] = i
.seg
[1];
4242 i
.seg
[1] = temp_seg
;
4246 /* Try to ensure constant immediates are represented in the smallest
4251 char guess_suffix
= 0;
4255 guess_suffix
= i
.suffix
;
4256 else if (i
.reg_operands
)
4258 /* Figure out a suffix from the last register operand specified.
4259 We can't do this properly yet, ie. excluding InOutPortReg,
4260 but the following works for instructions with immediates.
4261 In any case, we can't set i.suffix yet. */
4262 for (op
= i
.operands
; --op
>= 0;)
4263 if (i
.types
[op
].bitfield
.reg8
)
4265 guess_suffix
= BYTE_MNEM_SUFFIX
;
4268 else if (i
.types
[op
].bitfield
.reg16
)
4270 guess_suffix
= WORD_MNEM_SUFFIX
;
4273 else if (i
.types
[op
].bitfield
.reg32
)
4275 guess_suffix
= LONG_MNEM_SUFFIX
;
4278 else if (i
.types
[op
].bitfield
.reg64
)
4280 guess_suffix
= QWORD_MNEM_SUFFIX
;
4284 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4285 guess_suffix
= WORD_MNEM_SUFFIX
;
4287 for (op
= i
.operands
; --op
>= 0;)
4288 if (operand_type_check (i
.types
[op
], imm
))
4290 switch (i
.op
[op
].imms
->X_op
)
4293 /* If a suffix is given, this operand may be shortened. */
4294 switch (guess_suffix
)
4296 case LONG_MNEM_SUFFIX
:
4297 i
.types
[op
].bitfield
.imm32
= 1;
4298 i
.types
[op
].bitfield
.imm64
= 1;
4300 case WORD_MNEM_SUFFIX
:
4301 i
.types
[op
].bitfield
.imm16
= 1;
4302 i
.types
[op
].bitfield
.imm32
= 1;
4303 i
.types
[op
].bitfield
.imm32s
= 1;
4304 i
.types
[op
].bitfield
.imm64
= 1;
4306 case BYTE_MNEM_SUFFIX
:
4307 i
.types
[op
].bitfield
.imm8
= 1;
4308 i
.types
[op
].bitfield
.imm8s
= 1;
4309 i
.types
[op
].bitfield
.imm16
= 1;
4310 i
.types
[op
].bitfield
.imm32
= 1;
4311 i
.types
[op
].bitfield
.imm32s
= 1;
4312 i
.types
[op
].bitfield
.imm64
= 1;
4316 /* If this operand is at most 16 bits, convert it
4317 to a signed 16 bit number before trying to see
4318 whether it will fit in an even smaller size.
4319 This allows a 16-bit operand such as $0xffe0 to
4320 be recognised as within Imm8S range. */
4321 if ((i
.types
[op
].bitfield
.imm16
)
4322 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4324 i
.op
[op
].imms
->X_add_number
=
4325 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4328 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4329 if ((i
.types
[op
].bitfield
.imm32
)
4330 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4333 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4334 ^ ((offsetT
) 1 << 31))
4335 - ((offsetT
) 1 << 31));
4339 = operand_type_or (i
.types
[op
],
4340 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4342 /* We must avoid matching of Imm32 templates when 64bit
4343 only immediate is available. */
4344 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4345 i
.types
[op
].bitfield
.imm32
= 0;
4352 /* Symbols and expressions. */
4354 /* Convert symbolic operand to proper sizes for matching, but don't
4355 prevent matching a set of insns that only supports sizes other
4356 than those matching the insn suffix. */
4358 i386_operand_type mask
, allowed
;
4359 const insn_template
*t
;
4361 operand_type_set (&mask
, 0);
4362 operand_type_set (&allowed
, 0);
4364 for (t
= current_templates
->start
;
4365 t
< current_templates
->end
;
4367 allowed
= operand_type_or (allowed
,
4368 t
->operand_types
[op
]);
4369 switch (guess_suffix
)
4371 case QWORD_MNEM_SUFFIX
:
4372 mask
.bitfield
.imm64
= 1;
4373 mask
.bitfield
.imm32s
= 1;
4375 case LONG_MNEM_SUFFIX
:
4376 mask
.bitfield
.imm32
= 1;
4378 case WORD_MNEM_SUFFIX
:
4379 mask
.bitfield
.imm16
= 1;
4381 case BYTE_MNEM_SUFFIX
:
4382 mask
.bitfield
.imm8
= 1;
4387 allowed
= operand_type_and (mask
, allowed
);
4388 if (!operand_type_all_zero (&allowed
))
4389 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4396 /* Try to use the smallest displacement type too. */
4398 optimize_disp (void)
4402 for (op
= i
.operands
; --op
>= 0;)
4403 if (operand_type_check (i
.types
[op
], disp
))
4405 if (i
.op
[op
].disps
->X_op
== O_constant
)
4407 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4409 if (i
.types
[op
].bitfield
.disp16
4410 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4412 /* If this operand is at most 16 bits, convert
4413 to a signed 16 bit number and don't use 64bit
4415 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4416 i
.types
[op
].bitfield
.disp64
= 0;
4419 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4420 if (i
.types
[op
].bitfield
.disp32
4421 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4423 /* If this operand is at most 32 bits, convert
4424 to a signed 32 bit number and don't use 64bit
4426 op_disp
&= (((offsetT
) 2 << 31) - 1);
4427 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4428 i
.types
[op
].bitfield
.disp64
= 0;
4431 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4433 i
.types
[op
].bitfield
.disp8
= 0;
4434 i
.types
[op
].bitfield
.disp16
= 0;
4435 i
.types
[op
].bitfield
.disp32
= 0;
4436 i
.types
[op
].bitfield
.disp32s
= 0;
4437 i
.types
[op
].bitfield
.disp64
= 0;
4441 else if (flag_code
== CODE_64BIT
)
4443 if (fits_in_signed_long (op_disp
))
4445 i
.types
[op
].bitfield
.disp64
= 0;
4446 i
.types
[op
].bitfield
.disp32s
= 1;
4448 if (i
.prefix
[ADDR_PREFIX
]
4449 && fits_in_unsigned_long (op_disp
))
4450 i
.types
[op
].bitfield
.disp32
= 1;
4452 if ((i
.types
[op
].bitfield
.disp32
4453 || i
.types
[op
].bitfield
.disp32s
4454 || i
.types
[op
].bitfield
.disp16
)
4455 && fits_in_signed_byte (op_disp
))
4456 i
.types
[op
].bitfield
.disp8
= 1;
4458 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4459 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4461 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4462 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4463 i
.types
[op
].bitfield
.disp8
= 0;
4464 i
.types
[op
].bitfield
.disp16
= 0;
4465 i
.types
[op
].bitfield
.disp32
= 0;
4466 i
.types
[op
].bitfield
.disp32s
= 0;
4467 i
.types
[op
].bitfield
.disp64
= 0;
4470 /* We only support 64bit displacement on constants. */
4471 i
.types
[op
].bitfield
.disp64
= 0;
4475 /* Check if operands are valid for the instruction. */
4478 check_VecOperands (const insn_template
*t
)
4482 /* Without VSIB byte, we can't have a vector register for index. */
4483 if (!t
->opcode_modifier
.vecsib
4485 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4486 || i
.index_reg
->reg_type
.bitfield
.regymm
4487 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4489 i
.error
= unsupported_vector_index_register
;
4493 /* Check if default mask is allowed. */
4494 if (t
->opcode_modifier
.nodefmask
4495 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4497 i
.error
= no_default_mask
;
4501 /* For VSIB byte, we need a vector register for index, and all vector
4502 registers must be distinct. */
4503 if (t
->opcode_modifier
.vecsib
)
4506 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4507 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4508 || (t
->opcode_modifier
.vecsib
== VecSIB256
4509 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4510 || (t
->opcode_modifier
.vecsib
== VecSIB512
4511 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4513 i
.error
= invalid_vsib_address
;
4517 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4518 if (i
.reg_operands
== 2 && !i
.mask
)
4520 gas_assert (i
.types
[0].bitfield
.regxmm
4521 || i
.types
[0].bitfield
.regymm
);
4522 gas_assert (i
.types
[2].bitfield
.regxmm
4523 || i
.types
[2].bitfield
.regymm
);
4524 if (operand_check
== check_none
)
4526 if (register_number (i
.op
[0].regs
)
4527 != register_number (i
.index_reg
)
4528 && register_number (i
.op
[2].regs
)
4529 != register_number (i
.index_reg
)
4530 && register_number (i
.op
[0].regs
)
4531 != register_number (i
.op
[2].regs
))
4533 if (operand_check
== check_error
)
4535 i
.error
= invalid_vector_register_set
;
4538 as_warn (_("mask, index, and destination registers should be distinct"));
4540 else if (i
.reg_operands
== 1 && i
.mask
)
4542 if ((i
.types
[1].bitfield
.regymm
4543 || i
.types
[1].bitfield
.regzmm
)
4544 && (register_number (i
.op
[1].regs
)
4545 == register_number (i
.index_reg
)))
4547 if (operand_check
== check_error
)
4549 i
.error
= invalid_vector_register_set
;
4552 if (operand_check
!= check_none
)
4553 as_warn (_("index and destination registers should be distinct"));
4558 /* Check if broadcast is supported by the instruction and is applied
4559 to the memory operand. */
4562 int broadcasted_opnd_size
;
4564 /* Check if specified broadcast is supported in this instruction,
4565 and it's applied to memory operand of DWORD or QWORD type,
4566 depending on VecESize. */
4567 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4568 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4569 || (t
->opcode_modifier
.vecesize
== 0
4570 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4571 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4572 || (t
->opcode_modifier
.vecesize
== 1
4573 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4574 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4577 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4578 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4579 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4580 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4581 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4582 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4583 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4584 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4585 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4589 if ((broadcasted_opnd_size
== 256
4590 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4591 || (broadcasted_opnd_size
== 512
4592 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4595 i
.error
= unsupported_broadcast
;
4599 /* If broadcast is supported in this instruction, we need to check if
4600 operand of one-element size isn't specified without broadcast. */
4601 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4603 /* Find memory operand. */
4604 for (op
= 0; op
< i
.operands
; op
++)
4605 if (operand_type_check (i
.types
[op
], anymem
))
4607 gas_assert (op
< i
.operands
);
4608 /* Check size of the memory operand. */
4609 if ((t
->opcode_modifier
.vecesize
== 0
4610 && i
.types
[op
].bitfield
.dword
)
4611 || (t
->opcode_modifier
.vecesize
== 1
4612 && i
.types
[op
].bitfield
.qword
))
4614 i
.error
= broadcast_needed
;
4619 /* Check if requested masking is supported. */
4621 && (!t
->opcode_modifier
.masking
4623 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4625 i
.error
= unsupported_masking
;
4629 /* Check if masking is applied to dest operand. */
4630 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4632 i
.error
= mask_not_on_destination
;
4639 if ((i
.rounding
->type
!= saeonly
4640 && !t
->opcode_modifier
.staticrounding
)
4641 || (i
.rounding
->type
== saeonly
4642 && (t
->opcode_modifier
.staticrounding
4643 || !t
->opcode_modifier
.sae
)))
4645 i
.error
= unsupported_rc_sae
;
4648 /* If the instruction has several immediate operands and one of
4649 them is rounding, the rounding operand should be the last
4650 immediate operand. */
4651 if (i
.imm_operands
> 1
4652 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4654 i
.error
= rc_sae_operand_not_last_imm
;
4659 /* Check vector Disp8 operand. */
4660 if (t
->opcode_modifier
.disp8memshift
)
4663 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4665 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4667 for (op
= 0; op
< i
.operands
; op
++)
4668 if (operand_type_check (i
.types
[op
], disp
)
4669 && i
.op
[op
].disps
->X_op
== O_constant
)
4671 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4673 = (i
.disp_encoding
!= disp_encoding_32bit
4674 && fits_in_vec_disp8 (value
));
4675 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4678 i
.types
[op
].bitfield
.vec_disp8
= 1;
4681 /* Vector insn can only have Vec_Disp8/Disp32 in
4682 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4684 i
.types
[op
].bitfield
.disp8
= 0;
4685 if (flag_code
!= CODE_16BIT
)
4686 i
.types
[op
].bitfield
.disp16
= 0;
4689 else if (flag_code
!= CODE_16BIT
)
4691 /* One form of this instruction supports vector Disp8.
4692 Try vector Disp8 if we need to use Disp32. */
4693 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4695 i
.error
= try_vector_disp8
;
4707 /* Check if operands are valid for the instruction. Update VEX
4711 VEX_check_operands (const insn_template
*t
)
4713 /* VREX is only valid with EVEX prefix. */
4714 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4716 i
.error
= invalid_register_operand
;
4720 if (!t
->opcode_modifier
.vex
)
4723 /* Only check VEX_Imm4, which must be the first operand. */
4724 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4726 if (i
.op
[0].imms
->X_op
!= O_constant
4727 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4733 /* Turn off Imm8 so that update_imm won't complain. */
4734 i
.types
[0] = vec_imm4
;
4740 static const insn_template
*
4741 match_template (char mnem_suffix
)
4743 /* Points to template once we've found it. */
4744 const insn_template
*t
;
4745 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4746 i386_operand_type overlap4
;
4747 unsigned int found_reverse_match
;
4748 i386_opcode_modifier suffix_check
, mnemsuf_check
;
4749 i386_operand_type operand_types
[MAX_OPERANDS
];
4750 int addr_prefix_disp
;
4752 unsigned int found_cpu_match
;
4753 unsigned int check_register
;
4754 enum i386_error specific_error
= 0;
4756 #if MAX_OPERANDS != 5
4757 # error "MAX_OPERANDS must be 5."
4760 found_reverse_match
= 0;
4761 addr_prefix_disp
= -1;
4763 memset (&suffix_check
, 0, sizeof (suffix_check
));
4764 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4765 suffix_check
.no_bsuf
= 1;
4766 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4767 suffix_check
.no_wsuf
= 1;
4768 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4769 suffix_check
.no_ssuf
= 1;
4770 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4771 suffix_check
.no_lsuf
= 1;
4772 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4773 suffix_check
.no_qsuf
= 1;
4774 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4775 suffix_check
.no_ldsuf
= 1;
4777 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
4780 switch (mnem_suffix
)
4782 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
4783 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
4784 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
4785 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
4786 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
4790 /* Must have right number of operands. */
4791 i
.error
= number_of_operands_mismatch
;
4793 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4795 addr_prefix_disp
= -1;
4797 if (i
.operands
!= t
->operands
)
4800 /* Check processor support. */
4801 i
.error
= unsupported
;
4802 found_cpu_match
= (cpu_flags_match (t
)
4803 == CPU_FLAGS_PERFECT_MATCH
);
4804 if (!found_cpu_match
)
4807 /* Check old gcc support. */
4808 i
.error
= old_gcc_only
;
4809 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4812 /* Check AT&T mnemonic. */
4813 i
.error
= unsupported_with_intel_mnemonic
;
4814 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4817 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
4818 i
.error
= unsupported_syntax
;
4819 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4820 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
4821 || (intel64
&& t
->opcode_modifier
.amd64
)
4822 || (!intel64
&& t
->opcode_modifier
.intel64
))
4825 /* Check the suffix, except for some instructions in intel mode. */
4826 i
.error
= invalid_instruction_suffix
;
4827 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4828 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4829 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4830 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4831 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4832 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4833 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4835 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4836 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
4837 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
4838 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
4839 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
4840 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
4841 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
4844 if (!operand_size_match (t
))
4847 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4848 operand_types
[j
] = t
->operand_types
[j
];
4850 /* In general, don't allow 64-bit operands in 32-bit mode. */
4851 if (i
.suffix
== QWORD_MNEM_SUFFIX
4852 && flag_code
!= CODE_64BIT
4854 ? (!t
->opcode_modifier
.ignoresize
4855 && !intel_float_operand (t
->name
))
4856 : intel_float_operand (t
->name
) != 2)
4857 && ((!operand_types
[0].bitfield
.regmmx
4858 && !operand_types
[0].bitfield
.regxmm
4859 && !operand_types
[0].bitfield
.regymm
4860 && !operand_types
[0].bitfield
.regzmm
)
4861 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4862 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4863 && operand_types
[t
->operands
> 1].bitfield
.regymm
4864 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4865 && (t
->base_opcode
!= 0x0fc7
4866 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4869 /* In general, don't allow 32-bit operands on pre-386. */
4870 else if (i
.suffix
== LONG_MNEM_SUFFIX
4871 && !cpu_arch_flags
.bitfield
.cpui386
4873 ? (!t
->opcode_modifier
.ignoresize
4874 && !intel_float_operand (t
->name
))
4875 : intel_float_operand (t
->name
) != 2)
4876 && ((!operand_types
[0].bitfield
.regmmx
4877 && !operand_types
[0].bitfield
.regxmm
)
4878 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4879 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4882 /* Do not verify operands when there are none. */
4886 /* We've found a match; break out of loop. */
4890 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4891 into Disp32/Disp16/Disp32 operand. */
4892 if (i
.prefix
[ADDR_PREFIX
] != 0)
4894 /* There should be only one Disp operand. */
4898 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4900 if (operand_types
[j
].bitfield
.disp16
)
4902 addr_prefix_disp
= j
;
4903 operand_types
[j
].bitfield
.disp32
= 1;
4904 operand_types
[j
].bitfield
.disp16
= 0;
4910 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4912 if (operand_types
[j
].bitfield
.disp32
)
4914 addr_prefix_disp
= j
;
4915 operand_types
[j
].bitfield
.disp32
= 0;
4916 operand_types
[j
].bitfield
.disp16
= 1;
4922 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4924 if (operand_types
[j
].bitfield
.disp64
)
4926 addr_prefix_disp
= j
;
4927 operand_types
[j
].bitfield
.disp64
= 0;
4928 operand_types
[j
].bitfield
.disp32
= 1;
4936 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4937 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
4940 /* We check register size if needed. */
4941 check_register
= t
->opcode_modifier
.checkregsize
;
4942 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4943 switch (t
->operands
)
4946 if (!operand_type_match (overlap0
, i
.types
[0]))
4950 /* xchg %eax, %eax is a special case. It is an aliase for nop
4951 only in 32bit mode and we can use opcode 0x90. In 64bit
4952 mode, we can't use 0x90 for xchg %eax, %eax since it should
4953 zero-extend %eax to %rax. */
4954 if (flag_code
== CODE_64BIT
4955 && t
->base_opcode
== 0x90
4956 && operand_type_equal (&i
.types
[0], &acc32
)
4957 && operand_type_equal (&i
.types
[1], &acc32
))
4961 /* If we swap operand in encoding, we either match
4962 the next one or reverse direction of operands. */
4963 if (t
->opcode_modifier
.s
)
4965 else if (t
->opcode_modifier
.d
)
4971 /* If we swap operand in encoding, we match the next one. */
4972 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4977 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4978 if (!operand_type_match (overlap0
, i
.types
[0])
4979 || !operand_type_match (overlap1
, i
.types
[1])
4981 && !operand_type_register_match (overlap0
, i
.types
[0],
4983 overlap1
, i
.types
[1],
4986 /* Check if other direction is valid ... */
4987 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4991 /* Try reversing direction of operands. */
4992 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4993 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4994 if (!operand_type_match (overlap0
, i
.types
[0])
4995 || !operand_type_match (overlap1
, i
.types
[1])
4997 && !operand_type_register_match (overlap0
,
5004 /* Does not match either direction. */
5007 /* found_reverse_match holds which of D or FloatDR
5009 if (t
->opcode_modifier
.d
)
5010 found_reverse_match
= Opcode_D
;
5011 else if (t
->opcode_modifier
.floatd
)
5012 found_reverse_match
= Opcode_FloatD
;
5014 found_reverse_match
= 0;
5015 if (t
->opcode_modifier
.floatr
)
5016 found_reverse_match
|= Opcode_FloatR
;
5020 /* Found a forward 2 operand match here. */
5021 switch (t
->operands
)
5024 overlap4
= operand_type_and (i
.types
[4],
5028 overlap3
= operand_type_and (i
.types
[3],
5032 overlap2
= operand_type_and (i
.types
[2],
5037 switch (t
->operands
)
5040 if (!operand_type_match (overlap4
, i
.types
[4])
5041 || !operand_type_register_match (overlap3
,
5050 if (!operand_type_match (overlap3
, i
.types
[3])
5052 && !operand_type_register_match (overlap2
,
5061 /* Here we make use of the fact that there are no
5062 reverse match 3 operand instructions, and all 3
5063 operand instructions only need to be checked for
5064 register consistency between operands 2 and 3. */
5065 if (!operand_type_match (overlap2
, i
.types
[2])
5067 && !operand_type_register_match (overlap1
,
5077 /* Found either forward/reverse 2, 3 or 4 operand match here:
5078 slip through to break. */
5080 if (!found_cpu_match
)
5082 found_reverse_match
= 0;
5086 /* Check if vector and VEX operands are valid. */
5087 if (check_VecOperands (t
) || VEX_check_operands (t
))
5089 specific_error
= i
.error
;
5093 /* We've found a match; break out of loop. */
5097 if (t
== current_templates
->end
)
5099 /* We found no match. */
5100 const char *err_msg
;
5101 switch (specific_error
? specific_error
: i
.error
)
5105 case operand_size_mismatch
:
5106 err_msg
= _("operand size mismatch");
5108 case operand_type_mismatch
:
5109 err_msg
= _("operand type mismatch");
5111 case register_type_mismatch
:
5112 err_msg
= _("register type mismatch");
5114 case number_of_operands_mismatch
:
5115 err_msg
= _("number of operands mismatch");
5117 case invalid_instruction_suffix
:
5118 err_msg
= _("invalid instruction suffix");
5121 err_msg
= _("constant doesn't fit in 4 bits");
5124 err_msg
= _("only supported with old gcc");
5126 case unsupported_with_intel_mnemonic
:
5127 err_msg
= _("unsupported with Intel mnemonic");
5129 case unsupported_syntax
:
5130 err_msg
= _("unsupported syntax");
5133 as_bad (_("unsupported instruction `%s'"),
5134 current_templates
->start
->name
);
5136 case invalid_vsib_address
:
5137 err_msg
= _("invalid VSIB address");
5139 case invalid_vector_register_set
:
5140 err_msg
= _("mask, index, and destination registers must be distinct");
5142 case unsupported_vector_index_register
:
5143 err_msg
= _("unsupported vector index register");
5145 case unsupported_broadcast
:
5146 err_msg
= _("unsupported broadcast");
5148 case broadcast_not_on_src_operand
:
5149 err_msg
= _("broadcast not on source memory operand");
5151 case broadcast_needed
:
5152 err_msg
= _("broadcast is needed for operand of such type");
5154 case unsupported_masking
:
5155 err_msg
= _("unsupported masking");
5157 case mask_not_on_destination
:
5158 err_msg
= _("mask not on destination operand");
5160 case no_default_mask
:
5161 err_msg
= _("default mask isn't allowed");
5163 case unsupported_rc_sae
:
5164 err_msg
= _("unsupported static rounding/sae");
5166 case rc_sae_operand_not_last_imm
:
5168 err_msg
= _("RC/SAE operand must precede immediate operands");
5170 err_msg
= _("RC/SAE operand must follow immediate operands");
5172 case invalid_register_operand
:
5173 err_msg
= _("invalid register operand");
5176 as_bad (_("%s for `%s'"), err_msg
,
5177 current_templates
->start
->name
);
5181 if (!quiet_warnings
)
5184 && (i
.types
[0].bitfield
.jumpabsolute
5185 != operand_types
[0].bitfield
.jumpabsolute
))
5187 as_warn (_("indirect %s without `*'"), t
->name
);
5190 if (t
->opcode_modifier
.isprefix
5191 && t
->opcode_modifier
.ignoresize
)
5193 /* Warn them that a data or address size prefix doesn't
5194 affect assembly of the next line of code. */
5195 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5199 /* Copy the template we found. */
5202 if (addr_prefix_disp
!= -1)
5203 i
.tm
.operand_types
[addr_prefix_disp
]
5204 = operand_types
[addr_prefix_disp
];
5206 if (found_reverse_match
)
5208 /* If we found a reverse match we must alter the opcode
5209 direction bit. found_reverse_match holds bits to change
5210 (different for int & float insns). */
5212 i
.tm
.base_opcode
^= found_reverse_match
;
5214 i
.tm
.operand_types
[0] = operand_types
[1];
5215 i
.tm
.operand_types
[1] = operand_types
[0];
5224 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5225 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5227 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5229 as_bad (_("`%s' operand %d must use `%ses' segment"),
5235 /* There's only ever one segment override allowed per instruction.
5236 This instruction possibly has a legal segment override on the
5237 second operand, so copy the segment to where non-string
5238 instructions store it, allowing common code. */
5239 i
.seg
[0] = i
.seg
[1];
5241 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5243 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5245 as_bad (_("`%s' operand %d must use `%ses' segment"),
5256 process_suffix (void)
5258 /* If matched instruction specifies an explicit instruction mnemonic
5260 if (i
.tm
.opcode_modifier
.size16
)
5261 i
.suffix
= WORD_MNEM_SUFFIX
;
5262 else if (i
.tm
.opcode_modifier
.size32
)
5263 i
.suffix
= LONG_MNEM_SUFFIX
;
5264 else if (i
.tm
.opcode_modifier
.size64
)
5265 i
.suffix
= QWORD_MNEM_SUFFIX
;
5266 else if (i
.reg_operands
)
5268 /* If there's no instruction mnemonic suffix we try to invent one
5269 based on register operands. */
5272 /* We take i.suffix from the last register operand specified,
5273 Destination register type is more significant than source
5274 register type. crc32 in SSE4.2 prefers source register
5276 if (i
.tm
.base_opcode
== 0xf20f38f1)
5278 if (i
.types
[0].bitfield
.reg16
)
5279 i
.suffix
= WORD_MNEM_SUFFIX
;
5280 else if (i
.types
[0].bitfield
.reg32
)
5281 i
.suffix
= LONG_MNEM_SUFFIX
;
5282 else if (i
.types
[0].bitfield
.reg64
)
5283 i
.suffix
= QWORD_MNEM_SUFFIX
;
5285 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5287 if (i
.types
[0].bitfield
.reg8
)
5288 i
.suffix
= BYTE_MNEM_SUFFIX
;
5295 if (i
.tm
.base_opcode
== 0xf20f38f1
5296 || i
.tm
.base_opcode
== 0xf20f38f0)
5298 /* We have to know the operand size for crc32. */
5299 as_bad (_("ambiguous memory operand size for `%s`"),
5304 for (op
= i
.operands
; --op
>= 0;)
5305 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5307 if (i
.types
[op
].bitfield
.reg8
)
5309 i
.suffix
= BYTE_MNEM_SUFFIX
;
5312 else if (i
.types
[op
].bitfield
.reg16
)
5314 i
.suffix
= WORD_MNEM_SUFFIX
;
5317 else if (i
.types
[op
].bitfield
.reg32
)
5319 i
.suffix
= LONG_MNEM_SUFFIX
;
5322 else if (i
.types
[op
].bitfield
.reg64
)
5324 i
.suffix
= QWORD_MNEM_SUFFIX
;
5330 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5333 && i
.tm
.opcode_modifier
.ignoresize
5334 && i
.tm
.opcode_modifier
.no_bsuf
)
5336 else if (!check_byte_reg ())
5339 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5342 && i
.tm
.opcode_modifier
.ignoresize
5343 && i
.tm
.opcode_modifier
.no_lsuf
)
5345 else if (!check_long_reg ())
5348 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5351 && i
.tm
.opcode_modifier
.ignoresize
5352 && i
.tm
.opcode_modifier
.no_qsuf
)
5354 else if (!check_qword_reg ())
5357 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5360 && i
.tm
.opcode_modifier
.ignoresize
5361 && i
.tm
.opcode_modifier
.no_wsuf
)
5363 else if (!check_word_reg ())
5366 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5367 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5368 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5370 /* Skip if the instruction has x/y/z suffix. match_template
5371 should check if it is a valid suffix. */
5373 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5374 /* Do nothing if the instruction is going to ignore the prefix. */
5379 else if (i
.tm
.opcode_modifier
.defaultsize
5381 /* exclude fldenv/frstor/fsave/fstenv */
5382 && i
.tm
.opcode_modifier
.no_ssuf
)
5384 i
.suffix
= stackop_size
;
5386 else if (intel_syntax
5388 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5389 || i
.tm
.opcode_modifier
.jumpbyte
5390 || i
.tm
.opcode_modifier
.jumpintersegment
5391 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5392 && i
.tm
.extension_opcode
<= 3)))
5397 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5399 i
.suffix
= QWORD_MNEM_SUFFIX
;
5404 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5405 i
.suffix
= LONG_MNEM_SUFFIX
;
5408 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5409 i
.suffix
= WORD_MNEM_SUFFIX
;
5418 if (i
.tm
.opcode_modifier
.w
)
5420 as_bad (_("no instruction mnemonic suffix given and "
5421 "no register operands; can't size instruction"));
5427 unsigned int suffixes
;
5429 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5430 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5432 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5434 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5436 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5438 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5441 /* There are more than suffix matches. */
5442 if (i
.tm
.opcode_modifier
.w
5443 || ((suffixes
& (suffixes
- 1))
5444 && !i
.tm
.opcode_modifier
.defaultsize
5445 && !i
.tm
.opcode_modifier
.ignoresize
))
5447 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5453 /* Change the opcode based on the operand size given by i.suffix;
5454 We don't need to change things for byte insns. */
5457 && i
.suffix
!= BYTE_MNEM_SUFFIX
5458 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5459 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5460 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5462 /* It's not a byte, select word/dword operation. */
5463 if (i
.tm
.opcode_modifier
.w
)
5465 if (i
.tm
.opcode_modifier
.shortform
)
5466 i
.tm
.base_opcode
|= 8;
5468 i
.tm
.base_opcode
|= 1;
5471 /* Now select between word & dword operations via the operand
5472 size prefix, except for instructions that will ignore this
5474 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5476 /* The address size override prefix changes the size of the
5478 if ((flag_code
== CODE_32BIT
5479 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5480 || (flag_code
!= CODE_32BIT
5481 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5482 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5485 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5486 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5487 && !i
.tm
.opcode_modifier
.ignoresize
5488 && !i
.tm
.opcode_modifier
.floatmf
5489 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5490 || (flag_code
== CODE_64BIT
5491 && i
.tm
.opcode_modifier
.jumpbyte
)))
5493 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5495 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5496 prefix
= ADDR_PREFIX_OPCODE
;
5498 if (!add_prefix (prefix
))
5502 /* Set mode64 for an operand. */
5503 if (i
.suffix
== QWORD_MNEM_SUFFIX
5504 && flag_code
== CODE_64BIT
5505 && !i
.tm
.opcode_modifier
.norex64
)
5507 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5508 need rex64. cmpxchg8b is also a special case. */
5509 if (! (i
.operands
== 2
5510 && i
.tm
.base_opcode
== 0x90
5511 && i
.tm
.extension_opcode
== None
5512 && operand_type_equal (&i
.types
[0], &acc64
)
5513 && operand_type_equal (&i
.types
[1], &acc64
))
5514 && ! (i
.operands
== 1
5515 && i
.tm
.base_opcode
== 0xfc7
5516 && i
.tm
.extension_opcode
== 1
5517 && !operand_type_check (i
.types
[0], reg
)
5518 && operand_type_check (i
.types
[0], anymem
)))
5522 /* Size floating point instruction. */
5523 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5524 if (i
.tm
.opcode_modifier
.floatmf
)
5525 i
.tm
.base_opcode
^= 4;
5532 check_byte_reg (void)
5536 for (op
= i
.operands
; --op
>= 0;)
5538 /* If this is an eight bit register, it's OK. If it's the 16 or
5539 32 bit version of an eight bit register, we will just use the
5540 low portion, and that's OK too. */
5541 if (i
.types
[op
].bitfield
.reg8
)
5544 /* I/O port address operands are OK too. */
5545 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5548 /* crc32 doesn't generate this warning. */
5549 if (i
.tm
.base_opcode
== 0xf20f38f0)
5552 if ((i
.types
[op
].bitfield
.reg16
5553 || i
.types
[op
].bitfield
.reg32
5554 || i
.types
[op
].bitfield
.reg64
)
5555 && i
.op
[op
].regs
->reg_num
< 4
5556 /* Prohibit these changes in 64bit mode, since the lowering
5557 would be more complicated. */
5558 && flag_code
!= CODE_64BIT
)
5560 #if REGISTER_WARNINGS
5561 if (!quiet_warnings
)
5562 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5564 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5565 ? REGNAM_AL
- REGNAM_AX
5566 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5568 i
.op
[op
].regs
->reg_name
,
5573 /* Any other register is bad. */
5574 if (i
.types
[op
].bitfield
.reg16
5575 || i
.types
[op
].bitfield
.reg32
5576 || i
.types
[op
].bitfield
.reg64
5577 || i
.types
[op
].bitfield
.regmmx
5578 || i
.types
[op
].bitfield
.regxmm
5579 || i
.types
[op
].bitfield
.regymm
5580 || i
.types
[op
].bitfield
.regzmm
5581 || i
.types
[op
].bitfield
.sreg2
5582 || i
.types
[op
].bitfield
.sreg3
5583 || i
.types
[op
].bitfield
.control
5584 || i
.types
[op
].bitfield
.debug
5585 || i
.types
[op
].bitfield
.test
5586 || i
.types
[op
].bitfield
.floatreg
5587 || i
.types
[op
].bitfield
.floatacc
)
5589 as_bad (_("`%s%s' not allowed with `%s%c'"),
5591 i
.op
[op
].regs
->reg_name
,
5601 check_long_reg (void)
5605 for (op
= i
.operands
; --op
>= 0;)
5606 /* Reject eight bit registers, except where the template requires
5607 them. (eg. movzb) */
5608 if (i
.types
[op
].bitfield
.reg8
5609 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5610 || i
.tm
.operand_types
[op
].bitfield
.reg32
5611 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5613 as_bad (_("`%s%s' not allowed with `%s%c'"),
5615 i
.op
[op
].regs
->reg_name
,
5620 /* Warn if the e prefix on a general reg is missing. */
5621 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5622 && i
.types
[op
].bitfield
.reg16
5623 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5624 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5626 /* Prohibit these changes in the 64bit mode, since the
5627 lowering is more complicated. */
5628 if (flag_code
== CODE_64BIT
)
5630 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5631 register_prefix
, i
.op
[op
].regs
->reg_name
,
5635 #if REGISTER_WARNINGS
5636 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5638 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5639 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5642 /* Warn if the r prefix on a general reg is present. */
5643 else if (i
.types
[op
].bitfield
.reg64
5644 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5645 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5648 && i
.tm
.opcode_modifier
.toqword
5649 && !i
.types
[0].bitfield
.regxmm
)
5651 /* Convert to QWORD. We want REX byte. */
5652 i
.suffix
= QWORD_MNEM_SUFFIX
;
5656 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5657 register_prefix
, i
.op
[op
].regs
->reg_name
,
5666 check_qword_reg (void)
5670 for (op
= i
.operands
; --op
>= 0; )
5671 /* Reject eight bit registers, except where the template requires
5672 them. (eg. movzb) */
5673 if (i
.types
[op
].bitfield
.reg8
5674 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5675 || i
.tm
.operand_types
[op
].bitfield
.reg32
5676 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5678 as_bad (_("`%s%s' not allowed with `%s%c'"),
5680 i
.op
[op
].regs
->reg_name
,
5685 /* Warn if the r prefix on a general reg is missing. */
5686 else if ((i
.types
[op
].bitfield
.reg16
5687 || i
.types
[op
].bitfield
.reg32
)
5688 && (i
.tm
.operand_types
[op
].bitfield
.reg64
5689 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5691 /* Prohibit these changes in the 64bit mode, since the
5692 lowering is more complicated. */
5694 && i
.tm
.opcode_modifier
.todword
5695 && !i
.types
[0].bitfield
.regxmm
)
5697 /* Convert to DWORD. We don't want REX byte. */
5698 i
.suffix
= LONG_MNEM_SUFFIX
;
5702 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5703 register_prefix
, i
.op
[op
].regs
->reg_name
,
5712 check_word_reg (void)
5715 for (op
= i
.operands
; --op
>= 0;)
5716 /* Reject eight bit registers, except where the template requires
5717 them. (eg. movzb) */
5718 if (i
.types
[op
].bitfield
.reg8
5719 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5720 || i
.tm
.operand_types
[op
].bitfield
.reg32
5721 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5723 as_bad (_("`%s%s' not allowed with `%s%c'"),
5725 i
.op
[op
].regs
->reg_name
,
5730 /* Warn if the e or r prefix on a general reg is present. */
5731 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5732 && (i
.types
[op
].bitfield
.reg32
5733 || i
.types
[op
].bitfield
.reg64
)
5734 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5735 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5737 /* Prohibit these changes in the 64bit mode, since the
5738 lowering is more complicated. */
5739 if (flag_code
== CODE_64BIT
)
5741 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5742 register_prefix
, i
.op
[op
].regs
->reg_name
,
5746 #if REGISTER_WARNINGS
5747 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5749 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5750 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5757 update_imm (unsigned int j
)
5759 i386_operand_type overlap
= i
.types
[j
];
5760 if ((overlap
.bitfield
.imm8
5761 || overlap
.bitfield
.imm8s
5762 || overlap
.bitfield
.imm16
5763 || overlap
.bitfield
.imm32
5764 || overlap
.bitfield
.imm32s
5765 || overlap
.bitfield
.imm64
)
5766 && !operand_type_equal (&overlap
, &imm8
)
5767 && !operand_type_equal (&overlap
, &imm8s
)
5768 && !operand_type_equal (&overlap
, &imm16
)
5769 && !operand_type_equal (&overlap
, &imm32
)
5770 && !operand_type_equal (&overlap
, &imm32s
)
5771 && !operand_type_equal (&overlap
, &imm64
))
5775 i386_operand_type temp
;
5777 operand_type_set (&temp
, 0);
5778 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5780 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5781 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5783 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5784 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5785 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5787 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5788 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5791 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5794 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5795 || operand_type_equal (&overlap
, &imm16_32
)
5796 || operand_type_equal (&overlap
, &imm16_32s
))
5798 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5803 if (!operand_type_equal (&overlap
, &imm8
)
5804 && !operand_type_equal (&overlap
, &imm8s
)
5805 && !operand_type_equal (&overlap
, &imm16
)
5806 && !operand_type_equal (&overlap
, &imm32
)
5807 && !operand_type_equal (&overlap
, &imm32s
)
5808 && !operand_type_equal (&overlap
, &imm64
))
5810 as_bad (_("no instruction mnemonic suffix given; "
5811 "can't determine immediate size"));
5815 i
.types
[j
] = overlap
;
5825 /* Update the first 2 immediate operands. */
5826 n
= i
.operands
> 2 ? 2 : i
.operands
;
5829 for (j
= 0; j
< n
; j
++)
5830 if (update_imm (j
) == 0)
5833 /* The 3rd operand can't be immediate operand. */
5834 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5841 bad_implicit_operand (int xmm
)
5843 const char *ireg
= xmm
? "xmm0" : "ymm0";
5846 as_bad (_("the last operand of `%s' must be `%s%s'"),
5847 i
.tm
.name
, register_prefix
, ireg
);
5849 as_bad (_("the first operand of `%s' must be `%s%s'"),
5850 i
.tm
.name
, register_prefix
, ireg
);
5855 process_operands (void)
5857 /* Default segment register this instruction will use for memory
5858 accesses. 0 means unknown. This is only for optimizing out
5859 unnecessary segment overrides. */
5860 const seg_entry
*default_seg
= 0;
5862 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5864 unsigned int dupl
= i
.operands
;
5865 unsigned int dest
= dupl
- 1;
5868 /* The destination must be an xmm register. */
5869 gas_assert (i
.reg_operands
5870 && MAX_OPERANDS
> dupl
5871 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5873 if (i
.tm
.opcode_modifier
.firstxmm0
)
5875 /* The first operand is implicit and must be xmm0. */
5876 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5877 if (register_number (i
.op
[0].regs
) != 0)
5878 return bad_implicit_operand (1);
5880 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5882 /* Keep xmm0 for instructions with VEX prefix and 3
5888 /* We remove the first xmm0 and keep the number of
5889 operands unchanged, which in fact duplicates the
5891 for (j
= 1; j
< i
.operands
; j
++)
5893 i
.op
[j
- 1] = i
.op
[j
];
5894 i
.types
[j
- 1] = i
.types
[j
];
5895 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5899 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5901 gas_assert ((MAX_OPERANDS
- 1) > dupl
5902 && (i
.tm
.opcode_modifier
.vexsources
5905 /* Add the implicit xmm0 for instructions with VEX prefix
5907 for (j
= i
.operands
; j
> 0; j
--)
5909 i
.op
[j
] = i
.op
[j
- 1];
5910 i
.types
[j
] = i
.types
[j
- 1];
5911 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5914 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5915 i
.types
[0] = regxmm
;
5916 i
.tm
.operand_types
[0] = regxmm
;
5919 i
.reg_operands
+= 2;
5924 i
.op
[dupl
] = i
.op
[dest
];
5925 i
.types
[dupl
] = i
.types
[dest
];
5926 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5935 i
.op
[dupl
] = i
.op
[dest
];
5936 i
.types
[dupl
] = i
.types
[dest
];
5937 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5940 if (i
.tm
.opcode_modifier
.immext
)
5943 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5947 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5948 gas_assert (i
.reg_operands
5949 && (operand_type_equal (&i
.types
[0], ®xmm
)
5950 || operand_type_equal (&i
.types
[0], ®ymm
)
5951 || operand_type_equal (&i
.types
[0], ®zmm
)));
5952 if (register_number (i
.op
[0].regs
) != 0)
5953 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5955 for (j
= 1; j
< i
.operands
; j
++)
5957 i
.op
[j
- 1] = i
.op
[j
];
5958 i
.types
[j
- 1] = i
.types
[j
];
5960 /* We need to adjust fields in i.tm since they are used by
5961 build_modrm_byte. */
5962 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5969 else if (i
.tm
.opcode_modifier
.regkludge
)
5971 /* The imul $imm, %reg instruction is converted into
5972 imul $imm, %reg, %reg, and the clr %reg instruction
5973 is converted into xor %reg, %reg. */
5975 unsigned int first_reg_op
;
5977 if (operand_type_check (i
.types
[0], reg
))
5981 /* Pretend we saw the extra register operand. */
5982 gas_assert (i
.reg_operands
== 1
5983 && i
.op
[first_reg_op
+ 1].regs
== 0);
5984 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5985 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5990 if (i
.tm
.opcode_modifier
.shortform
)
5992 if (i
.types
[0].bitfield
.sreg2
5993 || i
.types
[0].bitfield
.sreg3
)
5995 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5996 && i
.op
[0].regs
->reg_num
== 1)
5998 as_bad (_("you can't `pop %scs'"), register_prefix
);
6001 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6002 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6007 /* The register or float register operand is in operand
6011 if (i
.types
[0].bitfield
.floatreg
6012 || operand_type_check (i
.types
[0], reg
))
6016 /* Register goes in low 3 bits of opcode. */
6017 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6018 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6020 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6022 /* Warn about some common errors, but press on regardless.
6023 The first case can be generated by gcc (<= 2.8.1). */
6024 if (i
.operands
== 2)
6026 /* Reversed arguments on faddp, fsubp, etc. */
6027 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6028 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6029 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6033 /* Extraneous `l' suffix on fp insn. */
6034 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6035 register_prefix
, i
.op
[0].regs
->reg_name
);
6040 else if (i
.tm
.opcode_modifier
.modrm
)
6042 /* The opcode is completed (modulo i.tm.extension_opcode which
6043 must be put into the modrm byte). Now, we make the modrm and
6044 index base bytes based on all the info we've collected. */
6046 default_seg
= build_modrm_byte ();
6048 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6052 else if (i
.tm
.opcode_modifier
.isstring
)
6054 /* For the string instructions that allow a segment override
6055 on one of their operands, the default segment is ds. */
6059 if (i
.tm
.base_opcode
== 0x8d /* lea */
6062 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6064 /* If a segment was explicitly specified, and the specified segment
6065 is not the default, use an opcode prefix to select it. If we
6066 never figured out what the default segment is, then default_seg
6067 will be zero at this point, and the specified segment prefix will
6069 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6071 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6077 static const seg_entry
*
6078 build_modrm_byte (void)
6080 const seg_entry
*default_seg
= 0;
6081 unsigned int source
, dest
;
6084 /* The first operand of instructions with VEX prefix and 3 sources
6085 must be VEX_Imm4. */
6086 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6089 unsigned int nds
, reg_slot
;
6092 if (i
.tm
.opcode_modifier
.veximmext
6093 && i
.tm
.opcode_modifier
.immext
)
6095 dest
= i
.operands
- 2;
6096 gas_assert (dest
== 3);
6099 dest
= i
.operands
- 1;
6102 /* There are 2 kinds of instructions:
6103 1. 5 operands: 4 register operands or 3 register operands
6104 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6105 VexW0 or VexW1. The destination must be either XMM, YMM or
6107 2. 4 operands: 4 register operands or 3 register operands
6108 plus 1 memory operand, VexXDS, and VexImmExt */
6109 gas_assert ((i
.reg_operands
== 4
6110 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6111 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6112 && (i
.tm
.opcode_modifier
.veximmext
6113 || (i
.imm_operands
== 1
6114 && i
.types
[0].bitfield
.vec_imm4
6115 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
6116 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6117 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
6118 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
6119 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
6121 if (i
.imm_operands
== 0)
6123 /* When there is no immediate operand, generate an 8bit
6124 immediate operand to encode the first operand. */
6125 exp
= &im_expressions
[i
.imm_operands
++];
6126 i
.op
[i
.operands
].imms
= exp
;
6127 i
.types
[i
.operands
] = imm8
;
6129 /* If VexW1 is set, the first operand is the source and
6130 the second operand is encoded in the immediate operand. */
6131 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6142 /* FMA swaps REG and NDS. */
6143 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6151 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6153 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6155 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6157 exp
->X_op
= O_constant
;
6158 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6159 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6163 unsigned int imm_slot
;
6165 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6167 /* If VexW0 is set, the third operand is the source and
6168 the second operand is encoded in the immediate
6175 /* VexW1 is set, the second operand is the source and
6176 the third operand is encoded in the immediate
6182 if (i
.tm
.opcode_modifier
.immext
)
6184 /* When ImmExt is set, the immdiate byte is the last
6186 imm_slot
= i
.operands
- 1;
6194 /* Turn on Imm8 so that output_imm will generate it. */
6195 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6198 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6200 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6202 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6204 i
.op
[imm_slot
].imms
->X_add_number
6205 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6206 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6209 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6210 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6212 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6214 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6219 /* i.reg_operands MUST be the number of real register operands;
6220 implicit registers do not count. If there are 3 register
6221 operands, it must be a instruction with VexNDS. For a
6222 instruction with VexNDD, the destination register is encoded
6223 in VEX prefix. If there are 4 register operands, it must be
6224 a instruction with VEX prefix and 3 sources. */
6225 if (i
.mem_operands
== 0
6226 && ((i
.reg_operands
== 2
6227 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6228 || (i
.reg_operands
== 3
6229 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6230 || (i
.reg_operands
== 4 && vex_3_sources
)))
6238 /* When there are 3 operands, one of them may be immediate,
6239 which may be the first or the last operand. Otherwise,
6240 the first operand must be shift count register (cl) or it
6241 is an instruction with VexNDS. */
6242 gas_assert (i
.imm_operands
== 1
6243 || (i
.imm_operands
== 0
6244 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6245 || i
.types
[0].bitfield
.shiftcount
)));
6246 if (operand_type_check (i
.types
[0], imm
)
6247 || i
.types
[0].bitfield
.shiftcount
)
6253 /* When there are 4 operands, the first two must be 8bit
6254 immediate operands. The source operand will be the 3rd
6257 For instructions with VexNDS, if the first operand
6258 an imm8, the source operand is the 2nd one. If the last
6259 operand is imm8, the source operand is the first one. */
6260 gas_assert ((i
.imm_operands
== 2
6261 && i
.types
[0].bitfield
.imm8
6262 && i
.types
[1].bitfield
.imm8
)
6263 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6264 && i
.imm_operands
== 1
6265 && (i
.types
[0].bitfield
.imm8
6266 || i
.types
[i
.operands
- 1].bitfield
.imm8
6268 if (i
.imm_operands
== 2)
6272 if (i
.types
[0].bitfield
.imm8
)
6279 if (i
.tm
.opcode_modifier
.evex
)
6281 /* For EVEX instructions, when there are 5 operands, the
6282 first one must be immediate operand. If the second one
6283 is immediate operand, the source operand is the 3th
6284 one. If the last one is immediate operand, the source
6285 operand is the 2nd one. */
6286 gas_assert (i
.imm_operands
== 2
6287 && i
.tm
.opcode_modifier
.sae
6288 && operand_type_check (i
.types
[0], imm
));
6289 if (operand_type_check (i
.types
[1], imm
))
6291 else if (operand_type_check (i
.types
[4], imm
))
6305 /* RC/SAE operand could be between DEST and SRC. That happens
6306 when one operand is GPR and the other one is XMM/YMM/ZMM
6308 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6311 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6313 /* For instructions with VexNDS, the register-only source
6314 operand must be 32/64bit integer, XMM, YMM or ZMM
6315 register. It is encoded in VEX prefix. We need to
6316 clear RegMem bit before calling operand_type_equal. */
6318 i386_operand_type op
;
6321 /* Check register-only source operand when two source
6322 operands are swapped. */
6323 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6324 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6332 op
= i
.tm
.operand_types
[vvvv
];
6333 op
.bitfield
.regmem
= 0;
6334 if ((dest
+ 1) >= i
.operands
6335 || (!op
.bitfield
.reg32
6336 && op
.bitfield
.reg64
6337 && !operand_type_equal (&op
, ®xmm
)
6338 && !operand_type_equal (&op
, ®ymm
)
6339 && !operand_type_equal (&op
, ®zmm
)
6340 && !operand_type_equal (&op
, ®mask
)))
6342 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6348 /* One of the register operands will be encoded in the i.tm.reg
6349 field, the other in the combined i.tm.mode and i.tm.regmem
6350 fields. If no form of this instruction supports a memory
6351 destination operand, then we assume the source operand may
6352 sometimes be a memory operand and so we need to store the
6353 destination in the i.rm.reg field. */
6354 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6355 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6357 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6358 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6359 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6361 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6363 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6365 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6370 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6371 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6372 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6374 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6376 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6378 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6381 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6383 if (!i
.types
[0].bitfield
.control
6384 && !i
.types
[1].bitfield
.control
)
6386 i
.rex
&= ~(REX_R
| REX_B
);
6387 add_prefix (LOCK_PREFIX_OPCODE
);
6391 { /* If it's not 2 reg operands... */
6396 unsigned int fake_zero_displacement
= 0;
6399 for (op
= 0; op
< i
.operands
; op
++)
6400 if (operand_type_check (i
.types
[op
], anymem
))
6402 gas_assert (op
< i
.operands
);
6404 if (i
.tm
.opcode_modifier
.vecsib
)
6406 if (i
.index_reg
->reg_num
== RegEiz
6407 || i
.index_reg
->reg_num
== RegRiz
)
6410 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6413 i
.sib
.base
= NO_BASE_REGISTER
;
6414 i
.sib
.scale
= i
.log2_scale_factor
;
6415 /* No Vec_Disp8 if there is no base. */
6416 i
.types
[op
].bitfield
.vec_disp8
= 0;
6417 i
.types
[op
].bitfield
.disp8
= 0;
6418 i
.types
[op
].bitfield
.disp16
= 0;
6419 i
.types
[op
].bitfield
.disp64
= 0;
6420 if (flag_code
!= CODE_64BIT
)
6422 /* Must be 32 bit */
6423 i
.types
[op
].bitfield
.disp32
= 1;
6424 i
.types
[op
].bitfield
.disp32s
= 0;
6428 i
.types
[op
].bitfield
.disp32
= 0;
6429 i
.types
[op
].bitfield
.disp32s
= 1;
6432 i
.sib
.index
= i
.index_reg
->reg_num
;
6433 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6435 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6441 if (i
.base_reg
== 0)
6444 if (!i
.disp_operands
)
6446 fake_zero_displacement
= 1;
6447 /* Instructions with VSIB byte need 32bit displacement
6448 if there is no base register. */
6449 if (i
.tm
.opcode_modifier
.vecsib
)
6450 i
.types
[op
].bitfield
.disp32
= 1;
6452 if (i
.index_reg
== 0)
6454 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6455 /* Operand is just <disp> */
6456 if (flag_code
== CODE_64BIT
)
6458 /* 64bit mode overwrites the 32bit absolute
6459 addressing by RIP relative addressing and
6460 absolute addressing is encoded by one of the
6461 redundant SIB forms. */
6462 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6463 i
.sib
.base
= NO_BASE_REGISTER
;
6464 i
.sib
.index
= NO_INDEX_REGISTER
;
6465 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6466 ? disp32s
: disp32
);
6468 else if ((flag_code
== CODE_16BIT
)
6469 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6471 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6472 i
.types
[op
] = disp16
;
6476 i
.rm
.regmem
= NO_BASE_REGISTER
;
6477 i
.types
[op
] = disp32
;
6480 else if (!i
.tm
.opcode_modifier
.vecsib
)
6482 /* !i.base_reg && i.index_reg */
6483 if (i
.index_reg
->reg_num
== RegEiz
6484 || i
.index_reg
->reg_num
== RegRiz
)
6485 i
.sib
.index
= NO_INDEX_REGISTER
;
6487 i
.sib
.index
= i
.index_reg
->reg_num
;
6488 i
.sib
.base
= NO_BASE_REGISTER
;
6489 i
.sib
.scale
= i
.log2_scale_factor
;
6490 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6491 /* No Vec_Disp8 if there is no base. */
6492 i
.types
[op
].bitfield
.vec_disp8
= 0;
6493 i
.types
[op
].bitfield
.disp8
= 0;
6494 i
.types
[op
].bitfield
.disp16
= 0;
6495 i
.types
[op
].bitfield
.disp64
= 0;
6496 if (flag_code
!= CODE_64BIT
)
6498 /* Must be 32 bit */
6499 i
.types
[op
].bitfield
.disp32
= 1;
6500 i
.types
[op
].bitfield
.disp32s
= 0;
6504 i
.types
[op
].bitfield
.disp32
= 0;
6505 i
.types
[op
].bitfield
.disp32s
= 1;
6507 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6511 /* RIP addressing for 64bit mode. */
6512 else if (i
.base_reg
->reg_num
== RegRip
||
6513 i
.base_reg
->reg_num
== RegEip
)
6515 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6516 i
.rm
.regmem
= NO_BASE_REGISTER
;
6517 i
.types
[op
].bitfield
.disp8
= 0;
6518 i
.types
[op
].bitfield
.disp16
= 0;
6519 i
.types
[op
].bitfield
.disp32
= 0;
6520 i
.types
[op
].bitfield
.disp32s
= 1;
6521 i
.types
[op
].bitfield
.disp64
= 0;
6522 i
.types
[op
].bitfield
.vec_disp8
= 0;
6523 i
.flags
[op
] |= Operand_PCrel
;
6524 if (! i
.disp_operands
)
6525 fake_zero_displacement
= 1;
6527 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6529 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6530 switch (i
.base_reg
->reg_num
)
6533 if (i
.index_reg
== 0)
6535 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6536 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6540 if (i
.index_reg
== 0)
6543 if (operand_type_check (i
.types
[op
], disp
) == 0)
6545 /* fake (%bp) into 0(%bp) */
6546 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6547 i
.types
[op
].bitfield
.vec_disp8
= 1;
6549 i
.types
[op
].bitfield
.disp8
= 1;
6550 fake_zero_displacement
= 1;
6553 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6554 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6556 default: /* (%si) -> 4 or (%di) -> 5 */
6557 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6559 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6561 else /* i.base_reg and 32/64 bit mode */
6563 if (flag_code
== CODE_64BIT
6564 && operand_type_check (i
.types
[op
], disp
))
6566 i386_operand_type temp
;
6567 operand_type_set (&temp
, 0);
6568 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6569 temp
.bitfield
.vec_disp8
6570 = i
.types
[op
].bitfield
.vec_disp8
;
6572 if (i
.prefix
[ADDR_PREFIX
] == 0)
6573 i
.types
[op
].bitfield
.disp32s
= 1;
6575 i
.types
[op
].bitfield
.disp32
= 1;
6578 if (!i
.tm
.opcode_modifier
.vecsib
)
6579 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6580 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6582 i
.sib
.base
= i
.base_reg
->reg_num
;
6583 /* x86-64 ignores REX prefix bit here to avoid decoder
6585 if (!(i
.base_reg
->reg_flags
& RegRex
)
6586 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6587 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6589 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6591 fake_zero_displacement
= 1;
6592 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6593 i
.types
[op
].bitfield
.vec_disp8
= 1;
6595 i
.types
[op
].bitfield
.disp8
= 1;
6597 i
.sib
.scale
= i
.log2_scale_factor
;
6598 if (i
.index_reg
== 0)
6600 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6601 /* <disp>(%esp) becomes two byte modrm with no index
6602 register. We've already stored the code for esp
6603 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6604 Any base register besides %esp will not use the
6605 extra modrm byte. */
6606 i
.sib
.index
= NO_INDEX_REGISTER
;
6608 else if (!i
.tm
.opcode_modifier
.vecsib
)
6610 if (i
.index_reg
->reg_num
== RegEiz
6611 || i
.index_reg
->reg_num
== RegRiz
)
6612 i
.sib
.index
= NO_INDEX_REGISTER
;
6614 i
.sib
.index
= i
.index_reg
->reg_num
;
6615 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6616 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6621 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6622 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6626 if (!fake_zero_displacement
6630 fake_zero_displacement
= 1;
6631 if (i
.disp_encoding
== disp_encoding_8bit
)
6632 i
.types
[op
].bitfield
.disp8
= 1;
6634 i
.types
[op
].bitfield
.disp32
= 1;
6636 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6640 if (fake_zero_displacement
)
6642 /* Fakes a zero displacement assuming that i.types[op]
6643 holds the correct displacement size. */
6646 gas_assert (i
.op
[op
].disps
== 0);
6647 exp
= &disp_expressions
[i
.disp_operands
++];
6648 i
.op
[op
].disps
= exp
;
6649 exp
->X_op
= O_constant
;
6650 exp
->X_add_number
= 0;
6651 exp
->X_add_symbol
= (symbolS
*) 0;
6652 exp
->X_op_symbol
= (symbolS
*) 0;
6660 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6662 if (operand_type_check (i
.types
[0], imm
))
6663 i
.vex
.register_specifier
= NULL
;
6666 /* VEX.vvvv encodes one of the sources when the first
6667 operand is not an immediate. */
6668 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6669 i
.vex
.register_specifier
= i
.op
[0].regs
;
6671 i
.vex
.register_specifier
= i
.op
[1].regs
;
6674 /* Destination is a XMM register encoded in the ModRM.reg
6676 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6677 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6680 /* ModRM.rm and VEX.B encodes the other source. */
6681 if (!i
.mem_operands
)
6685 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6686 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6688 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6690 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6694 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6696 i
.vex
.register_specifier
= i
.op
[2].regs
;
6697 if (!i
.mem_operands
)
6700 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6701 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6705 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6706 (if any) based on i.tm.extension_opcode. Again, we must be
6707 careful to make sure that segment/control/debug/test/MMX
6708 registers are coded into the i.rm.reg field. */
6709 else if (i
.reg_operands
)
6712 unsigned int vex_reg
= ~0;
6714 for (op
= 0; op
< i
.operands
; op
++)
6715 if (i
.types
[op
].bitfield
.reg8
6716 || i
.types
[op
].bitfield
.reg16
6717 || i
.types
[op
].bitfield
.reg32
6718 || i
.types
[op
].bitfield
.reg64
6719 || i
.types
[op
].bitfield
.regmmx
6720 || i
.types
[op
].bitfield
.regxmm
6721 || i
.types
[op
].bitfield
.regymm
6722 || i
.types
[op
].bitfield
.regbnd
6723 || i
.types
[op
].bitfield
.regzmm
6724 || i
.types
[op
].bitfield
.regmask
6725 || i
.types
[op
].bitfield
.sreg2
6726 || i
.types
[op
].bitfield
.sreg3
6727 || i
.types
[op
].bitfield
.control
6728 || i
.types
[op
].bitfield
.debug
6729 || i
.types
[op
].bitfield
.test
)
6734 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6736 /* For instructions with VexNDS, the register-only
6737 source operand is encoded in VEX prefix. */
6738 gas_assert (mem
!= (unsigned int) ~0);
6743 gas_assert (op
< i
.operands
);
6747 /* Check register-only source operand when two source
6748 operands are swapped. */
6749 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6750 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6754 gas_assert (mem
== (vex_reg
+ 1)
6755 && op
< i
.operands
);
6760 gas_assert (vex_reg
< i
.operands
);
6764 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6766 /* For instructions with VexNDD, the register destination
6767 is encoded in VEX prefix. */
6768 if (i
.mem_operands
== 0)
6770 /* There is no memory operand. */
6771 gas_assert ((op
+ 2) == i
.operands
);
6776 /* There are only 2 operands. */
6777 gas_assert (op
< 2 && i
.operands
== 2);
6782 gas_assert (op
< i
.operands
);
6784 if (vex_reg
!= (unsigned int) ~0)
6786 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6788 if (type
->bitfield
.reg32
!= 1
6789 && type
->bitfield
.reg64
!= 1
6790 && !operand_type_equal (type
, ®xmm
)
6791 && !operand_type_equal (type
, ®ymm
)
6792 && !operand_type_equal (type
, ®zmm
)
6793 && !operand_type_equal (type
, ®mask
))
6796 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6799 /* Don't set OP operand twice. */
6802 /* If there is an extension opcode to put here, the
6803 register number must be put into the regmem field. */
6804 if (i
.tm
.extension_opcode
!= None
)
6806 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6807 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6809 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6814 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6815 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6817 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6822 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6823 must set it to 3 to indicate this is a register operand
6824 in the regmem field. */
6825 if (!i
.mem_operands
)
6829 /* Fill in i.rm.reg field with extension opcode (if any). */
6830 if (i
.tm
.extension_opcode
!= None
)
6831 i
.rm
.reg
= i
.tm
.extension_opcode
;
6837 output_branch (void)
6843 relax_substateT subtype
;
6847 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6848 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6851 if (i
.prefix
[DATA_PREFIX
] != 0)
6857 /* Pentium4 branch hints. */
6858 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6859 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6864 if (i
.prefix
[REX_PREFIX
] != 0)
6870 /* BND prefixed jump. */
6871 if (i
.prefix
[BND_PREFIX
] != 0)
6873 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6877 if (i
.prefixes
!= 0 && !intel_syntax
)
6878 as_warn (_("skipping prefixes on this instruction"));
6880 /* It's always a symbol; End frag & setup for relax.
6881 Make sure there is enough room in this frag for the largest
6882 instruction we may generate in md_convert_frag. This is 2
6883 bytes for the opcode and room for the prefix and largest
6885 frag_grow (prefix
+ 2 + 4);
6886 /* Prefix and 1 opcode byte go in fr_fix. */
6887 p
= frag_more (prefix
+ 1);
6888 if (i
.prefix
[DATA_PREFIX
] != 0)
6889 *p
++ = DATA_PREFIX_OPCODE
;
6890 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6891 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6892 *p
++ = i
.prefix
[SEG_PREFIX
];
6893 if (i
.prefix
[REX_PREFIX
] != 0)
6894 *p
++ = i
.prefix
[REX_PREFIX
];
6895 *p
= i
.tm
.base_opcode
;
6897 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6898 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6899 else if (cpu_arch_flags
.bitfield
.cpui386
)
6900 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6902 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6905 sym
= i
.op
[0].disps
->X_add_symbol
;
6906 off
= i
.op
[0].disps
->X_add_number
;
6908 if (i
.op
[0].disps
->X_op
!= O_constant
6909 && i
.op
[0].disps
->X_op
!= O_symbol
)
6911 /* Handle complex expressions. */
6912 sym
= make_expr_symbol (i
.op
[0].disps
);
6916 /* 1 possible extra opcode + 4 byte displacement go in var part.
6917 Pass reloc in fr_var. */
6918 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6928 if (i
.tm
.opcode_modifier
.jumpbyte
)
6930 /* This is a loop or jecxz type instruction. */
6932 if (i
.prefix
[ADDR_PREFIX
] != 0)
6934 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6937 /* Pentium4 branch hints. */
6938 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6939 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6941 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6950 if (flag_code
== CODE_16BIT
)
6953 if (i
.prefix
[DATA_PREFIX
] != 0)
6955 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6965 if (i
.prefix
[REX_PREFIX
] != 0)
6967 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6971 /* BND prefixed jump. */
6972 if (i
.prefix
[BND_PREFIX
] != 0)
6974 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6978 if (i
.prefixes
!= 0 && !intel_syntax
)
6979 as_warn (_("skipping prefixes on this instruction"));
6981 p
= frag_more (i
.tm
.opcode_length
+ size
);
6982 switch (i
.tm
.opcode_length
)
6985 *p
++ = i
.tm
.base_opcode
>> 8;
6988 *p
++ = i
.tm
.base_opcode
;
6994 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6995 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6997 /* All jumps handled here are signed, but don't use a signed limit
6998 check for 32 and 16 bit jumps as we want to allow wrap around at
6999 4G and 64k respectively. */
7001 fixP
->fx_signed
= 1;
7005 output_interseg_jump (void)
7013 if (flag_code
== CODE_16BIT
)
7017 if (i
.prefix
[DATA_PREFIX
] != 0)
7023 if (i
.prefix
[REX_PREFIX
] != 0)
7033 if (i
.prefixes
!= 0 && !intel_syntax
)
7034 as_warn (_("skipping prefixes on this instruction"));
7036 /* 1 opcode; 2 segment; offset */
7037 p
= frag_more (prefix
+ 1 + 2 + size
);
7039 if (i
.prefix
[DATA_PREFIX
] != 0)
7040 *p
++ = DATA_PREFIX_OPCODE
;
7042 if (i
.prefix
[REX_PREFIX
] != 0)
7043 *p
++ = i
.prefix
[REX_PREFIX
];
7045 *p
++ = i
.tm
.base_opcode
;
7046 if (i
.op
[1].imms
->X_op
== O_constant
)
7048 offsetT n
= i
.op
[1].imms
->X_add_number
;
7051 && !fits_in_unsigned_word (n
)
7052 && !fits_in_signed_word (n
))
7054 as_bad (_("16-bit jump out of range"));
7057 md_number_to_chars (p
, n
, size
);
7060 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7061 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7062 if (i
.op
[0].imms
->X_op
!= O_constant
)
7063 as_bad (_("can't handle non absolute segment in `%s'"),
7065 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7071 fragS
*insn_start_frag
;
7072 offsetT insn_start_off
;
7074 /* Tie dwarf2 debug info to the address at the start of the insn.
7075 We can't do this after the insn has been output as the current
7076 frag may have been closed off. eg. by frag_var. */
7077 dwarf2_emit_insn (0);
7079 insn_start_frag
= frag_now
;
7080 insn_start_off
= frag_now_fix ();
7083 if (i
.tm
.opcode_modifier
.jump
)
7085 else if (i
.tm
.opcode_modifier
.jumpbyte
7086 || i
.tm
.opcode_modifier
.jumpdword
)
7088 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7089 output_interseg_jump ();
7092 /* Output normal instructions here. */
7096 unsigned int prefix
;
7099 && i
.tm
.base_opcode
== 0xfae
7101 && i
.imm_operands
== 1
7102 && (i
.op
[0].imms
->X_add_number
== 0xe8
7103 || i
.op
[0].imms
->X_add_number
== 0xf0
7104 || i
.op
[0].imms
->X_add_number
== 0xf8))
7106 /* Encode lfence, mfence, and sfence as
7107 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7108 offsetT val
= 0x240483f0ULL
;
7110 md_number_to_chars (p
, val
, 5);
7114 /* Some processors fail on LOCK prefix. This options makes
7115 assembler ignore LOCK prefix and serves as a workaround. */
7116 if (omit_lock_prefix
)
7118 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7120 i
.prefix
[LOCK_PREFIX
] = 0;
7123 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7124 don't need the explicit prefix. */
7125 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7127 switch (i
.tm
.opcode_length
)
7130 if (i
.tm
.base_opcode
& 0xff000000)
7132 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7137 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7139 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7140 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7143 if (prefix
!= REPE_PREFIX_OPCODE
7144 || (i
.prefix
[REP_PREFIX
]
7145 != REPE_PREFIX_OPCODE
))
7146 add_prefix (prefix
);
7149 add_prefix (prefix
);
7158 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7159 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7160 R_X86_64_GOTTPOFF relocation so that linker can safely
7161 perform IE->LE optimization. */
7162 if (x86_elf_abi
== X86_64_X32_ABI
7164 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7165 && i
.prefix
[REX_PREFIX
] == 0)
7166 add_prefix (REX_OPCODE
);
7169 /* The prefix bytes. */
7170 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7172 FRAG_APPEND_1_CHAR (*q
);
7176 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7181 /* REX byte is encoded in VEX prefix. */
7185 FRAG_APPEND_1_CHAR (*q
);
7188 /* There should be no other prefixes for instructions
7193 /* For EVEX instructions i.vrex should become 0 after
7194 build_evex_prefix. For VEX instructions upper 16 registers
7195 aren't available, so VREX should be 0. */
7198 /* Now the VEX prefix. */
7199 p
= frag_more (i
.vex
.length
);
7200 for (j
= 0; j
< i
.vex
.length
; j
++)
7201 p
[j
] = i
.vex
.bytes
[j
];
7204 /* Now the opcode; be careful about word order here! */
7205 if (i
.tm
.opcode_length
== 1)
7207 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7211 switch (i
.tm
.opcode_length
)
7215 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7216 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7220 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7230 /* Put out high byte first: can't use md_number_to_chars! */
7231 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7232 *p
= i
.tm
.base_opcode
& 0xff;
7235 /* Now the modrm byte and sib byte (if present). */
7236 if (i
.tm
.opcode_modifier
.modrm
)
7238 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7241 /* If i.rm.regmem == ESP (4)
7242 && i.rm.mode != (Register mode)
7244 ==> need second modrm byte. */
7245 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7247 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7248 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7250 | i
.sib
.scale
<< 6));
7253 if (i
.disp_operands
)
7254 output_disp (insn_start_frag
, insn_start_off
);
7257 output_imm (insn_start_frag
, insn_start_off
);
7263 pi ("" /*line*/, &i
);
7265 #endif /* DEBUG386 */
7268 /* Return the size of the displacement operand N. */
7271 disp_size (unsigned int n
)
7275 /* Vec_Disp8 has to be 8bit. */
7276 if (i
.types
[n
].bitfield
.vec_disp8
)
7278 else if (i
.types
[n
].bitfield
.disp64
)
7280 else if (i
.types
[n
].bitfield
.disp8
)
7282 else if (i
.types
[n
].bitfield
.disp16
)
7287 /* Return the size of the immediate operand N. */
7290 imm_size (unsigned int n
)
7293 if (i
.types
[n
].bitfield
.imm64
)
7295 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7297 else if (i
.types
[n
].bitfield
.imm16
)
7303 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7308 for (n
= 0; n
< i
.operands
; n
++)
7310 if (i
.types
[n
].bitfield
.vec_disp8
7311 || operand_type_check (i
.types
[n
], disp
))
7313 if (i
.op
[n
].disps
->X_op
== O_constant
)
7315 int size
= disp_size (n
);
7316 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7318 if (i
.types
[n
].bitfield
.vec_disp8
)
7320 val
= offset_in_range (val
, size
);
7321 p
= frag_more (size
);
7322 md_number_to_chars (p
, val
, size
);
7326 enum bfd_reloc_code_real reloc_type
;
7327 int size
= disp_size (n
);
7328 int sign
= i
.types
[n
].bitfield
.disp32s
;
7329 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7332 /* We can't have 8 bit displacement here. */
7333 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7335 /* The PC relative address is computed relative
7336 to the instruction boundary, so in case immediate
7337 fields follows, we need to adjust the value. */
7338 if (pcrel
&& i
.imm_operands
)
7343 for (n1
= 0; n1
< i
.operands
; n1
++)
7344 if (operand_type_check (i
.types
[n1
], imm
))
7346 /* Only one immediate is allowed for PC
7347 relative address. */
7348 gas_assert (sz
== 0);
7350 i
.op
[n
].disps
->X_add_number
-= sz
;
7352 /* We should find the immediate. */
7353 gas_assert (sz
!= 0);
7356 p
= frag_more (size
);
7357 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7359 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7360 && (((reloc_type
== BFD_RELOC_32
7361 || reloc_type
== BFD_RELOC_X86_64_32S
7362 || (reloc_type
== BFD_RELOC_64
7364 && (i
.op
[n
].disps
->X_op
== O_symbol
7365 || (i
.op
[n
].disps
->X_op
== O_add
7366 && ((symbol_get_value_expression
7367 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7369 || reloc_type
== BFD_RELOC_32_PCREL
))
7373 if (insn_start_frag
== frag_now
)
7374 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7379 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7380 for (fr
= insn_start_frag
->fr_next
;
7381 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7383 add
+= p
- frag_now
->fr_literal
;
7388 reloc_type
= BFD_RELOC_386_GOTPC
;
7389 i
.op
[n
].imms
->X_add_number
+= add
;
7391 else if (reloc_type
== BFD_RELOC_64
)
7392 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7394 /* Don't do the adjustment for x86-64, as there
7395 the pcrel addressing is relative to the _next_
7396 insn, and that is taken care of in other code. */
7397 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7399 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7400 size
, i
.op
[n
].disps
, pcrel
,
7402 /* Check for "call/jmp *mem", "mov mem, %reg",
7403 "test %reg, mem" and "binop mem, %reg" where binop
7404 is one of adc, add, and, cmp, or, sbb, sub, xor
7405 instructions. Always generate R_386_GOT32X for
7406 "sym*GOT" operand in 32-bit mode. */
7407 if ((generate_relax_relocations
7410 && i
.rm
.regmem
== 5))
7412 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7413 && ((i
.operands
== 1
7414 && i
.tm
.base_opcode
== 0xff
7415 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7417 && (i
.tm
.base_opcode
== 0x8b
7418 || i
.tm
.base_opcode
== 0x85
7419 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7423 fixP
->fx_tcbit
= i
.rex
!= 0;
7425 && (i
.base_reg
->reg_num
== RegRip
7426 || i
.base_reg
->reg_num
== RegEip
))
7427 fixP
->fx_tcbit2
= 1;
7430 fixP
->fx_tcbit2
= 1;
7438 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7443 for (n
= 0; n
< i
.operands
; n
++)
7445 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7446 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7449 if (operand_type_check (i
.types
[n
], imm
))
7451 if (i
.op
[n
].imms
->X_op
== O_constant
)
7453 int size
= imm_size (n
);
7456 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7458 p
= frag_more (size
);
7459 md_number_to_chars (p
, val
, size
);
7463 /* Not absolute_section.
7464 Need a 32-bit fixup (don't support 8bit
7465 non-absolute imms). Try to support other
7467 enum bfd_reloc_code_real reloc_type
;
7468 int size
= imm_size (n
);
7471 if (i
.types
[n
].bitfield
.imm32s
7472 && (i
.suffix
== QWORD_MNEM_SUFFIX
7473 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7478 p
= frag_more (size
);
7479 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7481 /* This is tough to explain. We end up with this one if we
7482 * have operands that look like
7483 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7484 * obtain the absolute address of the GOT, and it is strongly
7485 * preferable from a performance point of view to avoid using
7486 * a runtime relocation for this. The actual sequence of
7487 * instructions often look something like:
7492 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7494 * The call and pop essentially return the absolute address
7495 * of the label .L66 and store it in %ebx. The linker itself
7496 * will ultimately change the first operand of the addl so
7497 * that %ebx points to the GOT, but to keep things simple, the
7498 * .o file must have this operand set so that it generates not
7499 * the absolute address of .L66, but the absolute address of
7500 * itself. This allows the linker itself simply treat a GOTPC
7501 * relocation as asking for a pcrel offset to the GOT to be
7502 * added in, and the addend of the relocation is stored in the
7503 * operand field for the instruction itself.
7505 * Our job here is to fix the operand so that it would add
7506 * the correct offset so that %ebx would point to itself. The
7507 * thing that is tricky is that .-.L66 will point to the
7508 * beginning of the instruction, so we need to further modify
7509 * the operand so that it will point to itself. There are
7510 * other cases where you have something like:
7512 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7514 * and here no correction would be required. Internally in
7515 * the assembler we treat operands of this form as not being
7516 * pcrel since the '.' is explicitly mentioned, and I wonder
7517 * whether it would simplify matters to do it this way. Who
7518 * knows. In earlier versions of the PIC patches, the
7519 * pcrel_adjust field was used to store the correction, but
7520 * since the expression is not pcrel, I felt it would be
7521 * confusing to do it this way. */
7523 if ((reloc_type
== BFD_RELOC_32
7524 || reloc_type
== BFD_RELOC_X86_64_32S
7525 || reloc_type
== BFD_RELOC_64
)
7527 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7528 && (i
.op
[n
].imms
->X_op
== O_symbol
7529 || (i
.op
[n
].imms
->X_op
== O_add
7530 && ((symbol_get_value_expression
7531 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7536 if (insn_start_frag
== frag_now
)
7537 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7542 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7543 for (fr
= insn_start_frag
->fr_next
;
7544 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7546 add
+= p
- frag_now
->fr_literal
;
7550 reloc_type
= BFD_RELOC_386_GOTPC
;
7552 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7554 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7555 i
.op
[n
].imms
->X_add_number
+= add
;
7557 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7558 i
.op
[n
].imms
, 0, reloc_type
);
7564 /* x86_cons_fix_new is called via the expression parsing code when a
7565 reloc is needed. We use this hook to get the correct .got reloc. */
7566 static int cons_sign
= -1;
7569 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7570 expressionS
*exp
, bfd_reloc_code_real_type r
)
7572 r
= reloc (len
, 0, cons_sign
, r
);
7575 if (exp
->X_op
== O_secrel
)
7577 exp
->X_op
= O_symbol
;
7578 r
= BFD_RELOC_32_SECREL
;
7582 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7585 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7586 purpose of the `.dc.a' internal pseudo-op. */
7589 x86_address_bytes (void)
7591 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7593 return stdoutput
->arch_info
->bits_per_address
/ 8;
7596 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7598 # define lex_got(reloc, adjust, types) NULL
7600 /* Parse operands of the form
7601 <symbol>@GOTOFF+<nnn>
7602 and similar .plt or .got references.
7604 If we find one, set up the correct relocation in RELOC and copy the
7605 input string, minus the `@GOTOFF' into a malloc'd buffer for
7606 parsing by the calling routine. Return this buffer, and if ADJUST
7607 is non-null set it to the length of the string we removed from the
7608 input line. Otherwise return NULL. */
7610 lex_got (enum bfd_reloc_code_real
*rel
,
7612 i386_operand_type
*types
)
7614 /* Some of the relocations depend on the size of what field is to
7615 be relocated. But in our callers i386_immediate and i386_displacement
7616 we don't yet know the operand size (this will be set by insn
7617 matching). Hence we record the word32 relocation here,
7618 and adjust the reloc according to the real size in reloc(). */
7619 static const struct {
7622 const enum bfd_reloc_code_real rel
[2];
7623 const i386_operand_type types64
;
7625 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7626 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7628 OPERAND_TYPE_IMM32_64
},
7630 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7631 BFD_RELOC_X86_64_PLTOFF64
},
7632 OPERAND_TYPE_IMM64
},
7633 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7634 BFD_RELOC_X86_64_PLT32
},
7635 OPERAND_TYPE_IMM32_32S_DISP32
},
7636 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7637 BFD_RELOC_X86_64_GOTPLT64
},
7638 OPERAND_TYPE_IMM64_DISP64
},
7639 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7640 BFD_RELOC_X86_64_GOTOFF64
},
7641 OPERAND_TYPE_IMM64_DISP64
},
7642 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7643 BFD_RELOC_X86_64_GOTPCREL
},
7644 OPERAND_TYPE_IMM32_32S_DISP32
},
7645 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7646 BFD_RELOC_X86_64_TLSGD
},
7647 OPERAND_TYPE_IMM32_32S_DISP32
},
7648 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7649 _dummy_first_bfd_reloc_code_real
},
7650 OPERAND_TYPE_NONE
},
7651 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7652 BFD_RELOC_X86_64_TLSLD
},
7653 OPERAND_TYPE_IMM32_32S_DISP32
},
7654 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7655 BFD_RELOC_X86_64_GOTTPOFF
},
7656 OPERAND_TYPE_IMM32_32S_DISP32
},
7657 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7658 BFD_RELOC_X86_64_TPOFF32
},
7659 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7660 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7661 _dummy_first_bfd_reloc_code_real
},
7662 OPERAND_TYPE_NONE
},
7663 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7664 BFD_RELOC_X86_64_DTPOFF32
},
7665 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7666 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7667 _dummy_first_bfd_reloc_code_real
},
7668 OPERAND_TYPE_NONE
},
7669 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7670 _dummy_first_bfd_reloc_code_real
},
7671 OPERAND_TYPE_NONE
},
7672 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7673 BFD_RELOC_X86_64_GOT32
},
7674 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7675 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7676 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7677 OPERAND_TYPE_IMM32_32S_DISP32
},
7678 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7679 BFD_RELOC_X86_64_TLSDESC_CALL
},
7680 OPERAND_TYPE_IMM32_32S_DISP32
},
7685 #if defined (OBJ_MAYBE_ELF)
7690 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7691 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7694 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7696 int len
= gotrel
[j
].len
;
7697 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7699 if (gotrel
[j
].rel
[object_64bit
] != 0)
7702 char *tmpbuf
, *past_reloc
;
7704 *rel
= gotrel
[j
].rel
[object_64bit
];
7708 if (flag_code
!= CODE_64BIT
)
7710 types
->bitfield
.imm32
= 1;
7711 types
->bitfield
.disp32
= 1;
7714 *types
= gotrel
[j
].types64
;
7717 if (j
!= 0 && GOT_symbol
== NULL
)
7718 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7720 /* The length of the first part of our input line. */
7721 first
= cp
- input_line_pointer
;
7723 /* The second part goes from after the reloc token until
7724 (and including) an end_of_line char or comma. */
7725 past_reloc
= cp
+ 1 + len
;
7727 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7729 second
= cp
+ 1 - past_reloc
;
7731 /* Allocate and copy string. The trailing NUL shouldn't
7732 be necessary, but be safe. */
7733 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7734 memcpy (tmpbuf
, input_line_pointer
, first
);
7735 if (second
!= 0 && *past_reloc
!= ' ')
7736 /* Replace the relocation token with ' ', so that
7737 errors like foo@GOTOFF1 will be detected. */
7738 tmpbuf
[first
++] = ' ';
7740 /* Increment length by 1 if the relocation token is
7745 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7746 tmpbuf
[first
+ second
] = '\0';
7750 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7751 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7756 /* Might be a symbol version string. Don't as_bad here. */
7765 /* Parse operands of the form
7766 <symbol>@SECREL32+<nnn>
7768 If we find one, set up the correct relocation in RELOC and copy the
7769 input string, minus the `@SECREL32' into a malloc'd buffer for
7770 parsing by the calling routine. Return this buffer, and if ADJUST
7771 is non-null set it to the length of the string we removed from the
7772 input line. Otherwise return NULL.
7774 This function is copied from the ELF version above adjusted for PE targets. */
7777 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7778 int *adjust ATTRIBUTE_UNUSED
,
7779 i386_operand_type
*types
)
7785 const enum bfd_reloc_code_real rel
[2];
7786 const i386_operand_type types64
;
7790 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7791 BFD_RELOC_32_SECREL
},
7792 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7798 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7799 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7802 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7804 int len
= gotrel
[j
].len
;
7806 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7808 if (gotrel
[j
].rel
[object_64bit
] != 0)
7811 char *tmpbuf
, *past_reloc
;
7813 *rel
= gotrel
[j
].rel
[object_64bit
];
7819 if (flag_code
!= CODE_64BIT
)
7821 types
->bitfield
.imm32
= 1;
7822 types
->bitfield
.disp32
= 1;
7825 *types
= gotrel
[j
].types64
;
7828 /* The length of the first part of our input line. */
7829 first
= cp
- input_line_pointer
;
7831 /* The second part goes from after the reloc token until
7832 (and including) an end_of_line char or comma. */
7833 past_reloc
= cp
+ 1 + len
;
7835 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7837 second
= cp
+ 1 - past_reloc
;
7839 /* Allocate and copy string. The trailing NUL shouldn't
7840 be necessary, but be safe. */
7841 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7842 memcpy (tmpbuf
, input_line_pointer
, first
);
7843 if (second
!= 0 && *past_reloc
!= ' ')
7844 /* Replace the relocation token with ' ', so that
7845 errors like foo@SECLREL321 will be detected. */
7846 tmpbuf
[first
++] = ' ';
7847 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7848 tmpbuf
[first
+ second
] = '\0';
7852 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7853 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7858 /* Might be a symbol version string. Don't as_bad here. */
7864 bfd_reloc_code_real_type
7865 x86_cons (expressionS
*exp
, int size
)
7867 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7869 intel_syntax
= -intel_syntax
;
7872 if (size
== 4 || (object_64bit
&& size
== 8))
7874 /* Handle @GOTOFF and the like in an expression. */
7876 char *gotfree_input_line
;
7879 save
= input_line_pointer
;
7880 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7881 if (gotfree_input_line
)
7882 input_line_pointer
= gotfree_input_line
;
7886 if (gotfree_input_line
)
7888 /* expression () has merrily parsed up to the end of line,
7889 or a comma - in the wrong buffer. Transfer how far
7890 input_line_pointer has moved to the right buffer. */
7891 input_line_pointer
= (save
7892 + (input_line_pointer
- gotfree_input_line
)
7894 free (gotfree_input_line
);
7895 if (exp
->X_op
== O_constant
7896 || exp
->X_op
== O_absent
7897 || exp
->X_op
== O_illegal
7898 || exp
->X_op
== O_register
7899 || exp
->X_op
== O_big
)
7901 char c
= *input_line_pointer
;
7902 *input_line_pointer
= 0;
7903 as_bad (_("missing or invalid expression `%s'"), save
);
7904 *input_line_pointer
= c
;
7911 intel_syntax
= -intel_syntax
;
7914 i386_intel_simplify (exp
);
7920 signed_cons (int size
)
7922 if (flag_code
== CODE_64BIT
)
7930 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7937 if (exp
.X_op
== O_symbol
)
7938 exp
.X_op
= O_secrel
;
7940 emit_expr (&exp
, 4);
7942 while (*input_line_pointer
++ == ',');
7944 input_line_pointer
--;
7945 demand_empty_rest_of_line ();
7949 /* Handle Vector operations. */
7952 check_VecOperations (char *op_string
, char *op_end
)
7954 const reg_entry
*mask
;
7959 && (op_end
== NULL
|| op_string
< op_end
))
7962 if (*op_string
== '{')
7966 /* Check broadcasts. */
7967 if (strncmp (op_string
, "1to", 3) == 0)
7972 goto duplicated_vec_op
;
7975 if (*op_string
== '8')
7976 bcst_type
= BROADCAST_1TO8
;
7977 else if (*op_string
== '4')
7978 bcst_type
= BROADCAST_1TO4
;
7979 else if (*op_string
== '2')
7980 bcst_type
= BROADCAST_1TO2
;
7981 else if (*op_string
== '1'
7982 && *(op_string
+1) == '6')
7984 bcst_type
= BROADCAST_1TO16
;
7989 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7994 broadcast_op
.type
= bcst_type
;
7995 broadcast_op
.operand
= this_operand
;
7996 i
.broadcast
= &broadcast_op
;
7998 /* Check masking operation. */
7999 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
8001 /* k0 can't be used for write mask. */
8002 if (mask
->reg_num
== 0)
8004 as_bad (_("`%s' can't be used for write mask"),
8011 mask_op
.mask
= mask
;
8012 mask_op
.zeroing
= 0;
8013 mask_op
.operand
= this_operand
;
8019 goto duplicated_vec_op
;
8021 i
.mask
->mask
= mask
;
8023 /* Only "{z}" is allowed here. No need to check
8024 zeroing mask explicitly. */
8025 if (i
.mask
->operand
!= this_operand
)
8027 as_bad (_("invalid write mask `%s'"), saved
);
8034 /* Check zeroing-flag for masking operation. */
8035 else if (*op_string
== 'z')
8039 mask_op
.mask
= NULL
;
8040 mask_op
.zeroing
= 1;
8041 mask_op
.operand
= this_operand
;
8046 if (i
.mask
->zeroing
)
8049 as_bad (_("duplicated `%s'"), saved
);
8053 i
.mask
->zeroing
= 1;
8055 /* Only "{%k}" is allowed here. No need to check mask
8056 register explicitly. */
8057 if (i
.mask
->operand
!= this_operand
)
8059 as_bad (_("invalid zeroing-masking `%s'"),
8068 goto unknown_vec_op
;
8070 if (*op_string
!= '}')
8072 as_bad (_("missing `}' in `%s'"), saved
);
8079 /* We don't know this one. */
8080 as_bad (_("unknown vector operation: `%s'"), saved
);
8088 i386_immediate (char *imm_start
)
8090 char *save_input_line_pointer
;
8091 char *gotfree_input_line
;
8094 i386_operand_type types
;
8096 operand_type_set (&types
, ~0);
8098 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8100 as_bad (_("at most %d immediate operands are allowed"),
8101 MAX_IMMEDIATE_OPERANDS
);
8105 exp
= &im_expressions
[i
.imm_operands
++];
8106 i
.op
[this_operand
].imms
= exp
;
8108 if (is_space_char (*imm_start
))
8111 save_input_line_pointer
= input_line_pointer
;
8112 input_line_pointer
= imm_start
;
8114 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8115 if (gotfree_input_line
)
8116 input_line_pointer
= gotfree_input_line
;
8118 exp_seg
= expression (exp
);
8122 /* Handle vector operations. */
8123 if (*input_line_pointer
== '{')
8125 input_line_pointer
= check_VecOperations (input_line_pointer
,
8127 if (input_line_pointer
== NULL
)
8131 if (*input_line_pointer
)
8132 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8134 input_line_pointer
= save_input_line_pointer
;
8135 if (gotfree_input_line
)
8137 free (gotfree_input_line
);
8139 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8140 exp
->X_op
= O_illegal
;
8143 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8147 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8148 i386_operand_type types
, const char *imm_start
)
8150 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8153 as_bad (_("missing or invalid immediate expression `%s'"),
8157 else if (exp
->X_op
== O_constant
)
8159 /* Size it properly later. */
8160 i
.types
[this_operand
].bitfield
.imm64
= 1;
8161 /* If not 64bit, sign extend val. */
8162 if (flag_code
!= CODE_64BIT
8163 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8165 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8167 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8168 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8169 && exp_seg
!= absolute_section
8170 && exp_seg
!= text_section
8171 && exp_seg
!= data_section
8172 && exp_seg
!= bss_section
8173 && exp_seg
!= undefined_section
8174 && !bfd_is_com_section (exp_seg
))
8176 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8180 else if (!intel_syntax
&& exp_seg
== reg_section
)
8183 as_bad (_("illegal immediate register operand %s"), imm_start
);
8188 /* This is an address. The size of the address will be
8189 determined later, depending on destination register,
8190 suffix, or the default for the section. */
8191 i
.types
[this_operand
].bitfield
.imm8
= 1;
8192 i
.types
[this_operand
].bitfield
.imm16
= 1;
8193 i
.types
[this_operand
].bitfield
.imm32
= 1;
8194 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8195 i
.types
[this_operand
].bitfield
.imm64
= 1;
8196 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8204 i386_scale (char *scale
)
8207 char *save
= input_line_pointer
;
8209 input_line_pointer
= scale
;
8210 val
= get_absolute_expression ();
8215 i
.log2_scale_factor
= 0;
8218 i
.log2_scale_factor
= 1;
8221 i
.log2_scale_factor
= 2;
8224 i
.log2_scale_factor
= 3;
8228 char sep
= *input_line_pointer
;
8230 *input_line_pointer
= '\0';
8231 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8233 *input_line_pointer
= sep
;
8234 input_line_pointer
= save
;
8238 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8240 as_warn (_("scale factor of %d without an index register"),
8241 1 << i
.log2_scale_factor
);
8242 i
.log2_scale_factor
= 0;
8244 scale
= input_line_pointer
;
8245 input_line_pointer
= save
;
8250 i386_displacement (char *disp_start
, char *disp_end
)
8254 char *save_input_line_pointer
;
8255 char *gotfree_input_line
;
8257 i386_operand_type bigdisp
, types
= anydisp
;
8260 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8262 as_bad (_("at most %d displacement operands are allowed"),
8263 MAX_MEMORY_OPERANDS
);
8267 operand_type_set (&bigdisp
, 0);
8268 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8269 || (!current_templates
->start
->opcode_modifier
.jump
8270 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8272 bigdisp
.bitfield
.disp32
= 1;
8273 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8274 if (flag_code
== CODE_64BIT
)
8278 bigdisp
.bitfield
.disp32s
= 1;
8279 bigdisp
.bitfield
.disp64
= 1;
8282 else if ((flag_code
== CODE_16BIT
) ^ override
)
8284 bigdisp
.bitfield
.disp32
= 0;
8285 bigdisp
.bitfield
.disp16
= 1;
8290 /* For PC-relative branches, the width of the displacement
8291 is dependent upon data size, not address size. */
8292 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8293 if (flag_code
== CODE_64BIT
)
8295 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8296 bigdisp
.bitfield
.disp16
= 1;
8299 bigdisp
.bitfield
.disp32
= 1;
8300 bigdisp
.bitfield
.disp32s
= 1;
8306 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8308 : LONG_MNEM_SUFFIX
));
8309 bigdisp
.bitfield
.disp32
= 1;
8310 if ((flag_code
== CODE_16BIT
) ^ override
)
8312 bigdisp
.bitfield
.disp32
= 0;
8313 bigdisp
.bitfield
.disp16
= 1;
8317 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8320 exp
= &disp_expressions
[i
.disp_operands
];
8321 i
.op
[this_operand
].disps
= exp
;
8323 save_input_line_pointer
= input_line_pointer
;
8324 input_line_pointer
= disp_start
;
8325 END_STRING_AND_SAVE (disp_end
);
8327 #ifndef GCC_ASM_O_HACK
8328 #define GCC_ASM_O_HACK 0
8331 END_STRING_AND_SAVE (disp_end
+ 1);
8332 if (i
.types
[this_operand
].bitfield
.baseIndex
8333 && displacement_string_end
[-1] == '+')
8335 /* This hack is to avoid a warning when using the "o"
8336 constraint within gcc asm statements.
8339 #define _set_tssldt_desc(n,addr,limit,type) \
8340 __asm__ __volatile__ ( \
8342 "movw %w1,2+%0\n\t" \
8344 "movb %b1,4+%0\n\t" \
8345 "movb %4,5+%0\n\t" \
8346 "movb $0,6+%0\n\t" \
8347 "movb %h1,7+%0\n\t" \
8349 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8351 This works great except that the output assembler ends
8352 up looking a bit weird if it turns out that there is
8353 no offset. You end up producing code that looks like:
8366 So here we provide the missing zero. */
8368 *displacement_string_end
= '0';
8371 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8372 if (gotfree_input_line
)
8373 input_line_pointer
= gotfree_input_line
;
8375 exp_seg
= expression (exp
);
8378 if (*input_line_pointer
)
8379 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8381 RESTORE_END_STRING (disp_end
+ 1);
8383 input_line_pointer
= save_input_line_pointer
;
8384 if (gotfree_input_line
)
8386 free (gotfree_input_line
);
8388 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8389 exp
->X_op
= O_illegal
;
8392 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8394 RESTORE_END_STRING (disp_end
);
8400 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8401 i386_operand_type types
, const char *disp_start
)
8403 i386_operand_type bigdisp
;
8406 /* We do this to make sure that the section symbol is in
8407 the symbol table. We will ultimately change the relocation
8408 to be relative to the beginning of the section. */
8409 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8410 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8411 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8413 if (exp
->X_op
!= O_symbol
)
8416 if (S_IS_LOCAL (exp
->X_add_symbol
)
8417 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8418 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8419 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8420 exp
->X_op
= O_subtract
;
8421 exp
->X_op_symbol
= GOT_symbol
;
8422 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8423 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8424 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8425 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8427 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8430 else if (exp
->X_op
== O_absent
8431 || exp
->X_op
== O_illegal
8432 || exp
->X_op
== O_big
)
8435 as_bad (_("missing or invalid displacement expression `%s'"),
8440 else if (flag_code
== CODE_64BIT
8441 && !i
.prefix
[ADDR_PREFIX
]
8442 && exp
->X_op
== O_constant
)
8444 /* Since displacement is signed extended to 64bit, don't allow
8445 disp32 and turn off disp32s if they are out of range. */
8446 i
.types
[this_operand
].bitfield
.disp32
= 0;
8447 if (!fits_in_signed_long (exp
->X_add_number
))
8449 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8450 if (i
.types
[this_operand
].bitfield
.baseindex
)
8452 as_bad (_("0x%lx out range of signed 32bit displacement"),
8453 (long) exp
->X_add_number
);
8459 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8460 else if (exp
->X_op
!= O_constant
8461 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8462 && exp_seg
!= absolute_section
8463 && exp_seg
!= text_section
8464 && exp_seg
!= data_section
8465 && exp_seg
!= bss_section
8466 && exp_seg
!= undefined_section
8467 && !bfd_is_com_section (exp_seg
))
8469 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8474 /* Check if this is a displacement only operand. */
8475 bigdisp
= i
.types
[this_operand
];
8476 bigdisp
.bitfield
.disp8
= 0;
8477 bigdisp
.bitfield
.disp16
= 0;
8478 bigdisp
.bitfield
.disp32
= 0;
8479 bigdisp
.bitfield
.disp32s
= 0;
8480 bigdisp
.bitfield
.disp64
= 0;
8481 if (operand_type_all_zero (&bigdisp
))
8482 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8488 /* Make sure the memory operand we've been dealt is valid.
8489 Return 1 on success, 0 on a failure. */
8492 i386_index_check (const char *operand_string
)
8494 const char *kind
= "base/index";
8495 enum flag_code addr_mode
;
8497 if (i
.prefix
[ADDR_PREFIX
])
8498 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8501 addr_mode
= flag_code
;
8503 #if INFER_ADDR_PREFIX
8504 if (i
.mem_operands
== 0)
8506 /* Infer address prefix from the first memory operand. */
8507 const reg_entry
*addr_reg
= i
.base_reg
;
8509 if (addr_reg
== NULL
)
8510 addr_reg
= i
.index_reg
;
8514 if (addr_reg
->reg_num
== RegEip
8515 || addr_reg
->reg_num
== RegEiz
8516 || addr_reg
->reg_type
.bitfield
.reg32
)
8517 addr_mode
= CODE_32BIT
;
8518 else if (flag_code
!= CODE_64BIT
8519 && addr_reg
->reg_type
.bitfield
.reg16
)
8520 addr_mode
= CODE_16BIT
;
8522 if (addr_mode
!= flag_code
)
8524 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8526 /* Change the size of any displacement too. At most one
8527 of Disp16 or Disp32 is set.
8528 FIXME. There doesn't seem to be any real need for
8529 separate Disp16 and Disp32 flags. The same goes for
8530 Imm16 and Imm32. Removing them would probably clean
8531 up the code quite a lot. */
8532 if (flag_code
!= CODE_64BIT
8533 && (i
.types
[this_operand
].bitfield
.disp16
8534 || i
.types
[this_operand
].bitfield
.disp32
))
8535 i
.types
[this_operand
]
8536 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8543 if (current_templates
->start
->opcode_modifier
.isstring
8544 && !current_templates
->start
->opcode_modifier
.immext
8545 && (current_templates
->end
[-1].opcode_modifier
.isstring
8548 /* Memory operands of string insns are special in that they only allow
8549 a single register (rDI, rSI, or rBX) as their memory address. */
8550 const reg_entry
*expected_reg
;
8551 static const char *di_si
[][2] =
8557 static const char *bx
[] = { "ebx", "bx", "rbx" };
8559 kind
= "string address";
8561 if (current_templates
->start
->opcode_modifier
.repprefixok
)
8563 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8565 if (!type
.bitfield
.baseindex
8566 || ((!i
.mem_operands
!= !intel_syntax
)
8567 && current_templates
->end
[-1].operand_types
[1]
8568 .bitfield
.baseindex
))
8569 type
= current_templates
->end
[-1].operand_types
[1];
8570 expected_reg
= hash_find (reg_hash
,
8571 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8575 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8577 if (i
.base_reg
!= expected_reg
8579 || operand_type_check (i
.types
[this_operand
], disp
))
8581 /* The second memory operand must have the same size as
8585 && !((addr_mode
== CODE_64BIT
8586 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8587 || (addr_mode
== CODE_32BIT
8588 ? i
.base_reg
->reg_type
.bitfield
.reg32
8589 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8592 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8594 intel_syntax
? '[' : '(',
8596 expected_reg
->reg_name
,
8597 intel_syntax
? ']' : ')');
8604 as_bad (_("`%s' is not a valid %s expression"),
8605 operand_string
, kind
);
8610 if (addr_mode
!= CODE_16BIT
)
8612 /* 32-bit/64-bit checks. */
8614 && (addr_mode
== CODE_64BIT
8615 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8616 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8618 || (i
.base_reg
->reg_num
8619 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8621 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8622 && !i
.index_reg
->reg_type
.bitfield
.regymm
8623 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8624 && ((addr_mode
== CODE_64BIT
8625 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8626 || i
.index_reg
->reg_num
== RegRiz
)
8627 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8628 || i
.index_reg
->reg_num
== RegEiz
))
8629 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8632 /* bndmk, bndldx, and bndstx have special restrictions. */
8633 if (current_templates
->start
->base_opcode
== 0xf30f1b
8634 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
8636 /* They cannot use RIP-relative addressing. */
8637 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegRip
)
8639 as_bad (_("`%s' cannot be used here"), operand_string
);
8643 /* bndldx and bndstx ignore their scale factor. */
8644 if (current_templates
->start
->base_opcode
!= 0xf30f1b
8645 && i
.log2_scale_factor
)
8646 as_warn (_("register scaling is being ignored here"));
8651 /* 16-bit checks. */
8653 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8654 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8656 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8657 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8659 && i
.base_reg
->reg_num
< 6
8660 && i
.index_reg
->reg_num
>= 6
8661 && i
.log2_scale_factor
== 0))))
8668 /* Handle vector immediates. */
8671 RC_SAE_immediate (const char *imm_start
)
8673 unsigned int match_found
, j
;
8674 const char *pstr
= imm_start
;
8682 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8684 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8688 rc_op
.type
= RC_NamesTable
[j
].type
;
8689 rc_op
.operand
= this_operand
;
8690 i
.rounding
= &rc_op
;
8694 as_bad (_("duplicated `%s'"), imm_start
);
8697 pstr
+= RC_NamesTable
[j
].len
;
8707 as_bad (_("Missing '}': '%s'"), imm_start
);
8710 /* RC/SAE immediate string should contain nothing more. */;
8713 as_bad (_("Junk after '}': '%s'"), imm_start
);
8717 exp
= &im_expressions
[i
.imm_operands
++];
8718 i
.op
[this_operand
].imms
= exp
;
8720 exp
->X_op
= O_constant
;
8721 exp
->X_add_number
= 0;
8722 exp
->X_add_symbol
= (symbolS
*) 0;
8723 exp
->X_op_symbol
= (symbolS
*) 0;
8725 i
.types
[this_operand
].bitfield
.imm8
= 1;
8729 /* Only string instructions can have a second memory operand, so
8730 reduce current_templates to just those if it contains any. */
8732 maybe_adjust_templates (void)
8734 const insn_template
*t
;
8736 gas_assert (i
.mem_operands
== 1);
8738 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
8739 if (t
->opcode_modifier
.isstring
)
8742 if (t
< current_templates
->end
)
8744 static templates aux_templates
;
8745 bfd_boolean recheck
;
8747 aux_templates
.start
= t
;
8748 for (; t
< current_templates
->end
; ++t
)
8749 if (!t
->opcode_modifier
.isstring
)
8751 aux_templates
.end
= t
;
8753 /* Determine whether to re-check the first memory operand. */
8754 recheck
= (aux_templates
.start
!= current_templates
->start
8755 || t
!= current_templates
->end
);
8757 current_templates
= &aux_templates
;
8762 if (i
.memop1_string
!= NULL
8763 && i386_index_check (i
.memop1_string
) == 0)
8772 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8776 i386_att_operand (char *operand_string
)
8780 char *op_string
= operand_string
;
8782 if (is_space_char (*op_string
))
8785 /* We check for an absolute prefix (differentiating,
8786 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8787 if (*op_string
== ABSOLUTE_PREFIX
)
8790 if (is_space_char (*op_string
))
8792 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8795 /* Check if operand is a register. */
8796 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8798 i386_operand_type temp
;
8800 /* Check for a segment override by searching for ':' after a
8801 segment register. */
8803 if (is_space_char (*op_string
))
8805 if (*op_string
== ':'
8806 && (r
->reg_type
.bitfield
.sreg2
8807 || r
->reg_type
.bitfield
.sreg3
))
8812 i
.seg
[i
.mem_operands
] = &es
;
8815 i
.seg
[i
.mem_operands
] = &cs
;
8818 i
.seg
[i
.mem_operands
] = &ss
;
8821 i
.seg
[i
.mem_operands
] = &ds
;
8824 i
.seg
[i
.mem_operands
] = &fs
;
8827 i
.seg
[i
.mem_operands
] = &gs
;
8831 /* Skip the ':' and whitespace. */
8833 if (is_space_char (*op_string
))
8836 if (!is_digit_char (*op_string
)
8837 && !is_identifier_char (*op_string
)
8838 && *op_string
!= '('
8839 && *op_string
!= ABSOLUTE_PREFIX
)
8841 as_bad (_("bad memory operand `%s'"), op_string
);
8844 /* Handle case of %es:*foo. */
8845 if (*op_string
== ABSOLUTE_PREFIX
)
8848 if (is_space_char (*op_string
))
8850 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8852 goto do_memory_reference
;
8855 /* Handle vector operations. */
8856 if (*op_string
== '{')
8858 op_string
= check_VecOperations (op_string
, NULL
);
8859 if (op_string
== NULL
)
8865 as_bad (_("junk `%s' after register"), op_string
);
8869 temp
.bitfield
.baseindex
= 0;
8870 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8872 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8873 i
.op
[this_operand
].regs
= r
;
8876 else if (*op_string
== REGISTER_PREFIX
)
8878 as_bad (_("bad register name `%s'"), op_string
);
8881 else if (*op_string
== IMMEDIATE_PREFIX
)
8884 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8886 as_bad (_("immediate operand illegal with absolute jump"));
8889 if (!i386_immediate (op_string
))
8892 else if (RC_SAE_immediate (operand_string
))
8894 /* If it is a RC or SAE immediate, do nothing. */
8897 else if (is_digit_char (*op_string
)
8898 || is_identifier_char (*op_string
)
8899 || *op_string
== '"'
8900 || *op_string
== '(')
8902 /* This is a memory reference of some sort. */
8905 /* Start and end of displacement string expression (if found). */
8906 char *displacement_string_start
;
8907 char *displacement_string_end
;
8910 do_memory_reference
:
8911 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
8913 if ((i
.mem_operands
== 1
8914 && !current_templates
->start
->opcode_modifier
.isstring
)
8915 || i
.mem_operands
== 2)
8917 as_bad (_("too many memory references for `%s'"),
8918 current_templates
->start
->name
);
8922 /* Check for base index form. We detect the base index form by
8923 looking for an ')' at the end of the operand, searching
8924 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8926 base_string
= op_string
+ strlen (op_string
);
8928 /* Handle vector operations. */
8929 vop_start
= strchr (op_string
, '{');
8930 if (vop_start
&& vop_start
< base_string
)
8932 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8934 base_string
= vop_start
;
8938 if (is_space_char (*base_string
))
8941 /* If we only have a displacement, set-up for it to be parsed later. */
8942 displacement_string_start
= op_string
;
8943 displacement_string_end
= base_string
+ 1;
8945 if (*base_string
== ')')
8948 unsigned int parens_balanced
= 1;
8949 /* We've already checked that the number of left & right ()'s are
8950 equal, so this loop will not be infinite. */
8954 if (*base_string
== ')')
8956 if (*base_string
== '(')
8959 while (parens_balanced
);
8961 temp_string
= base_string
;
8963 /* Skip past '(' and whitespace. */
8965 if (is_space_char (*base_string
))
8968 if (*base_string
== ','
8969 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8972 displacement_string_end
= temp_string
;
8974 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8978 base_string
= end_op
;
8979 if (is_space_char (*base_string
))
8983 /* There may be an index reg or scale factor here. */
8984 if (*base_string
== ',')
8987 if (is_space_char (*base_string
))
8990 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8993 base_string
= end_op
;
8994 if (is_space_char (*base_string
))
8996 if (*base_string
== ',')
8999 if (is_space_char (*base_string
))
9002 else if (*base_string
!= ')')
9004 as_bad (_("expecting `,' or `)' "
9005 "after index register in `%s'"),
9010 else if (*base_string
== REGISTER_PREFIX
)
9012 end_op
= strchr (base_string
, ',');
9015 as_bad (_("bad register name `%s'"), base_string
);
9019 /* Check for scale factor. */
9020 if (*base_string
!= ')')
9022 char *end_scale
= i386_scale (base_string
);
9027 base_string
= end_scale
;
9028 if (is_space_char (*base_string
))
9030 if (*base_string
!= ')')
9032 as_bad (_("expecting `)' "
9033 "after scale factor in `%s'"),
9038 else if (!i
.index_reg
)
9040 as_bad (_("expecting index register or scale factor "
9041 "after `,'; got '%c'"),
9046 else if (*base_string
!= ')')
9048 as_bad (_("expecting `,' or `)' "
9049 "after base register in `%s'"),
9054 else if (*base_string
== REGISTER_PREFIX
)
9056 end_op
= strchr (base_string
, ',');
9059 as_bad (_("bad register name `%s'"), base_string
);
9064 /* If there's an expression beginning the operand, parse it,
9065 assuming displacement_string_start and
9066 displacement_string_end are meaningful. */
9067 if (displacement_string_start
!= displacement_string_end
)
9069 if (!i386_displacement (displacement_string_start
,
9070 displacement_string_end
))
9074 /* Special case for (%dx) while doing input/output op. */
9076 && operand_type_equal (&i
.base_reg
->reg_type
,
9077 ®16_inoutportreg
)
9079 && i
.log2_scale_factor
== 0
9080 && i
.seg
[i
.mem_operands
] == 0
9081 && !operand_type_check (i
.types
[this_operand
], disp
))
9083 i
.types
[this_operand
] = inoutportreg
;
9087 if (i386_index_check (operand_string
) == 0)
9089 i
.types
[this_operand
].bitfield
.mem
= 1;
9090 if (i
.mem_operands
== 0)
9091 i
.memop1_string
= xstrdup (operand_string
);
9096 /* It's not a memory operand; argh! */
9097 as_bad (_("invalid char %s beginning operand %d `%s'"),
9098 output_invalid (*op_string
),
9103 return 1; /* Normal return. */
9106 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9107 that an rs_machine_dependent frag may reach. */
9110 i386_frag_max_var (fragS
*frag
)
9112 /* The only relaxable frags are for jumps.
9113 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9114 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9115 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9118 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9120 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9122 /* STT_GNU_IFUNC symbol must go through PLT. */
9123 if ((symbol_get_bfdsym (fr_symbol
)->flags
9124 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9127 if (!S_IS_EXTERNAL (fr_symbol
))
9128 /* Symbol may be weak or local. */
9129 return !S_IS_WEAK (fr_symbol
);
9131 /* Global symbols with non-default visibility can't be preempted. */
9132 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9135 if (fr_var
!= NO_RELOC
)
9136 switch ((enum bfd_reloc_code_real
) fr_var
)
9138 case BFD_RELOC_386_PLT32
:
9139 case BFD_RELOC_X86_64_PLT32
:
9140 /* Symbol with PLT relocatin may be preempted. */
9146 /* Global symbols with default visibility in a shared library may be
9147 preempted by another definition. */
9152 /* md_estimate_size_before_relax()
9154 Called just before relax() for rs_machine_dependent frags. The x86
9155 assembler uses these frags to handle variable size jump
9158 Any symbol that is now undefined will not become defined.
9159 Return the correct fr_subtype in the frag.
9160 Return the initial "guess for variable size of frag" to caller.
9161 The guess is actually the growth beyond the fixed part. Whatever
9162 we do to grow the fixed or variable part contributes to our
9166 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9168 /* We've already got fragP->fr_subtype right; all we have to do is
9169 check for un-relaxable symbols. On an ELF system, we can't relax
9170 an externally visible symbol, because it may be overridden by a
9172 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9173 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9175 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9178 #if defined (OBJ_COFF) && defined (TE_PE)
9179 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9180 && S_IS_WEAK (fragP
->fr_symbol
))
9184 /* Symbol is undefined in this segment, or we need to keep a
9185 reloc so that weak symbols can be overridden. */
9186 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9187 enum bfd_reloc_code_real reloc_type
;
9188 unsigned char *opcode
;
9191 if (fragP
->fr_var
!= NO_RELOC
)
9192 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9194 reloc_type
= BFD_RELOC_16_PCREL
;
9196 reloc_type
= BFD_RELOC_32_PCREL
;
9198 old_fr_fix
= fragP
->fr_fix
;
9199 opcode
= (unsigned char *) fragP
->fr_opcode
;
9201 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9204 /* Make jmp (0xeb) a (d)word displacement jump. */
9206 fragP
->fr_fix
+= size
;
9207 fix_new (fragP
, old_fr_fix
, size
,
9209 fragP
->fr_offset
, 1,
9215 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9217 /* Negate the condition, and branch past an
9218 unconditional jump. */
9221 /* Insert an unconditional jump. */
9223 /* We added two extra opcode bytes, and have a two byte
9225 fragP
->fr_fix
+= 2 + 2;
9226 fix_new (fragP
, old_fr_fix
+ 2, 2,
9228 fragP
->fr_offset
, 1,
9235 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9240 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9242 fragP
->fr_offset
, 1,
9244 fixP
->fx_signed
= 1;
9248 /* This changes the byte-displacement jump 0x7N
9249 to the (d)word-displacement jump 0x0f,0x8N. */
9250 opcode
[1] = opcode
[0] + 0x10;
9251 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9252 /* We've added an opcode byte. */
9253 fragP
->fr_fix
+= 1 + size
;
9254 fix_new (fragP
, old_fr_fix
+ 1, size
,
9256 fragP
->fr_offset
, 1,
9261 BAD_CASE (fragP
->fr_subtype
);
9265 return fragP
->fr_fix
- old_fr_fix
;
9268 /* Guess size depending on current relax state. Initially the relax
9269 state will correspond to a short jump and we return 1, because
9270 the variable part of the frag (the branch offset) is one byte
9271 long. However, we can relax a section more than once and in that
9272 case we must either set fr_subtype back to the unrelaxed state,
9273 or return the value for the appropriate branch. */
9274 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9277 /* Called after relax() is finished.
9279 In: Address of frag.
9280 fr_type == rs_machine_dependent.
9281 fr_subtype is what the address relaxed to.
9283 Out: Any fixSs and constants are set up.
9284 Caller will turn frag into a ".space 0". */
9287 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9290 unsigned char *opcode
;
9291 unsigned char *where_to_put_displacement
= NULL
;
9292 offsetT target_address
;
9293 offsetT opcode_address
;
9294 unsigned int extension
= 0;
9295 offsetT displacement_from_opcode_start
;
9297 opcode
= (unsigned char *) fragP
->fr_opcode
;
9299 /* Address we want to reach in file space. */
9300 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9302 /* Address opcode resides at in file space. */
9303 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9305 /* Displacement from opcode start to fill into instruction. */
9306 displacement_from_opcode_start
= target_address
- opcode_address
;
9308 if ((fragP
->fr_subtype
& BIG
) == 0)
9310 /* Don't have to change opcode. */
9311 extension
= 1; /* 1 opcode + 1 displacement */
9312 where_to_put_displacement
= &opcode
[1];
9316 if (no_cond_jump_promotion
9317 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9318 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9319 _("long jump required"));
9321 switch (fragP
->fr_subtype
)
9323 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9324 extension
= 4; /* 1 opcode + 4 displacement */
9326 where_to_put_displacement
= &opcode
[1];
9329 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9330 extension
= 2; /* 1 opcode + 2 displacement */
9332 where_to_put_displacement
= &opcode
[1];
9335 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9336 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9337 extension
= 5; /* 2 opcode + 4 displacement */
9338 opcode
[1] = opcode
[0] + 0x10;
9339 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9340 where_to_put_displacement
= &opcode
[2];
9343 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9344 extension
= 3; /* 2 opcode + 2 displacement */
9345 opcode
[1] = opcode
[0] + 0x10;
9346 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9347 where_to_put_displacement
= &opcode
[2];
9350 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9355 where_to_put_displacement
= &opcode
[3];
9359 BAD_CASE (fragP
->fr_subtype
);
9364 /* If size if less then four we are sure that the operand fits,
9365 but if it's 4, then it could be that the displacement is larger
9367 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9369 && ((addressT
) (displacement_from_opcode_start
- extension
9370 + ((addressT
) 1 << 31))
9371 > (((addressT
) 2 << 31) - 1)))
9373 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9374 _("jump target out of range"));
9375 /* Make us emit 0. */
9376 displacement_from_opcode_start
= extension
;
9378 /* Now put displacement after opcode. */
9379 md_number_to_chars ((char *) where_to_put_displacement
,
9380 (valueT
) (displacement_from_opcode_start
- extension
),
9381 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9382 fragP
->fr_fix
+= extension
;
9385 /* Apply a fixup (fixP) to segment data, once it has been determined
9386 by our caller that we have all the info we need to fix it up.
9388 Parameter valP is the pointer to the value of the bits.
9390 On the 386, immediates, displacements, and data pointers are all in
9391 the same (little-endian) format, so we don't need to care about which
9395 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9397 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9398 valueT value
= *valP
;
9400 #if !defined (TE_Mach)
9403 switch (fixP
->fx_r_type
)
9409 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9412 case BFD_RELOC_X86_64_32S
:
9413 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9416 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9419 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9424 if (fixP
->fx_addsy
!= NULL
9425 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9426 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9427 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9428 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9429 && !use_rela_relocations
)
9431 /* This is a hack. There should be a better way to handle this.
9432 This covers for the fact that bfd_install_relocation will
9433 subtract the current location (for partial_inplace, PC relative
9434 relocations); see more below. */
9438 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9441 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9443 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9446 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9449 || (symbol_section_p (fixP
->fx_addsy
)
9450 && sym_seg
!= absolute_section
))
9451 && !generic_force_reloc (fixP
))
9453 /* Yes, we add the values in twice. This is because
9454 bfd_install_relocation subtracts them out again. I think
9455 bfd_install_relocation is broken, but I don't dare change
9457 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9461 #if defined (OBJ_COFF) && defined (TE_PE)
9462 /* For some reason, the PE format does not store a
9463 section address offset for a PC relative symbol. */
9464 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9465 || S_IS_WEAK (fixP
->fx_addsy
))
9466 value
+= md_pcrel_from (fixP
);
9469 #if defined (OBJ_COFF) && defined (TE_PE)
9470 if (fixP
->fx_addsy
!= NULL
9471 && S_IS_WEAK (fixP
->fx_addsy
)
9472 /* PR 16858: Do not modify weak function references. */
9473 && ! fixP
->fx_pcrel
)
9475 #if !defined (TE_PEP)
9476 /* For x86 PE weak function symbols are neither PC-relative
9477 nor do they set S_IS_FUNCTION. So the only reliable way
9478 to detect them is to check the flags of their containing
9480 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9481 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9485 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9489 /* Fix a few things - the dynamic linker expects certain values here,
9490 and we must not disappoint it. */
9491 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9492 if (IS_ELF
&& fixP
->fx_addsy
)
9493 switch (fixP
->fx_r_type
)
9495 case BFD_RELOC_386_PLT32
:
9496 case BFD_RELOC_X86_64_PLT32
:
9497 /* Make the jump instruction point to the address of the operand. At
9498 runtime we merely add the offset to the actual PLT entry. */
9502 case BFD_RELOC_386_TLS_GD
:
9503 case BFD_RELOC_386_TLS_LDM
:
9504 case BFD_RELOC_386_TLS_IE_32
:
9505 case BFD_RELOC_386_TLS_IE
:
9506 case BFD_RELOC_386_TLS_GOTIE
:
9507 case BFD_RELOC_386_TLS_GOTDESC
:
9508 case BFD_RELOC_X86_64_TLSGD
:
9509 case BFD_RELOC_X86_64_TLSLD
:
9510 case BFD_RELOC_X86_64_GOTTPOFF
:
9511 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9512 value
= 0; /* Fully resolved at runtime. No addend. */
9514 case BFD_RELOC_386_TLS_LE
:
9515 case BFD_RELOC_386_TLS_LDO_32
:
9516 case BFD_RELOC_386_TLS_LE_32
:
9517 case BFD_RELOC_X86_64_DTPOFF32
:
9518 case BFD_RELOC_X86_64_DTPOFF64
:
9519 case BFD_RELOC_X86_64_TPOFF32
:
9520 case BFD_RELOC_X86_64_TPOFF64
:
9521 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9524 case BFD_RELOC_386_TLS_DESC_CALL
:
9525 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9526 value
= 0; /* Fully resolved at runtime. No addend. */
9527 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9531 case BFD_RELOC_VTABLE_INHERIT
:
9532 case BFD_RELOC_VTABLE_ENTRY
:
9539 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9541 #endif /* !defined (TE_Mach) */
9543 /* Are we finished with this relocation now? */
9544 if (fixP
->fx_addsy
== NULL
)
9546 #if defined (OBJ_COFF) && defined (TE_PE)
9547 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9550 /* Remember value for tc_gen_reloc. */
9551 fixP
->fx_addnumber
= value
;
9552 /* Clear out the frag for now. */
9556 else if (use_rela_relocations
)
9558 fixP
->fx_no_overflow
= 1;
9559 /* Remember value for tc_gen_reloc. */
9560 fixP
->fx_addnumber
= value
;
9564 md_number_to_chars (p
, value
, fixP
->fx_size
);
9568 md_atof (int type
, char *litP
, int *sizeP
)
9570 /* This outputs the LITTLENUMs in REVERSE order;
9571 in accord with the bigendian 386. */
9572 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9575 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9578 output_invalid (int c
)
9581 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9584 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9585 "(0x%x)", (unsigned char) c
);
9586 return output_invalid_buf
;
9589 /* REG_STRING starts *before* REGISTER_PREFIX. */
9591 static const reg_entry
*
9592 parse_real_register (char *reg_string
, char **end_op
)
9594 char *s
= reg_string
;
9596 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9599 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9600 if (*s
== REGISTER_PREFIX
)
9603 if (is_space_char (*s
))
9607 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9609 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9610 return (const reg_entry
*) NULL
;
9614 /* For naked regs, make sure that we are not dealing with an identifier.
9615 This prevents confusing an identifier like `eax_var' with register
9617 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9618 return (const reg_entry
*) NULL
;
9622 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9624 /* Handle floating point regs, allowing spaces in the (i) part. */
9625 if (r
== i386_regtab
/* %st is first entry of table */)
9627 if (is_space_char (*s
))
9632 if (is_space_char (*s
))
9634 if (*s
>= '0' && *s
<= '7')
9638 if (is_space_char (*s
))
9643 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9648 /* We have "%st(" then garbage. */
9649 return (const reg_entry
*) NULL
;
9653 if (r
== NULL
|| allow_pseudo_reg
)
9656 if (operand_type_all_zero (&r
->reg_type
))
9657 return (const reg_entry
*) NULL
;
9659 if ((r
->reg_type
.bitfield
.reg32
9660 || r
->reg_type
.bitfield
.sreg3
9661 || r
->reg_type
.bitfield
.control
9662 || r
->reg_type
.bitfield
.debug
9663 || r
->reg_type
.bitfield
.test
)
9664 && !cpu_arch_flags
.bitfield
.cpui386
)
9665 return (const reg_entry
*) NULL
;
9667 if (r
->reg_type
.bitfield
.floatreg
9668 && !cpu_arch_flags
.bitfield
.cpu8087
9669 && !cpu_arch_flags
.bitfield
.cpu287
9670 && !cpu_arch_flags
.bitfield
.cpu387
)
9671 return (const reg_entry
*) NULL
;
9673 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpuregmmx
)
9674 return (const reg_entry
*) NULL
;
9676 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpuregxmm
)
9677 return (const reg_entry
*) NULL
;
9679 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuregymm
)
9680 return (const reg_entry
*) NULL
;
9682 if (r
->reg_type
.bitfield
.regzmm
&& !cpu_arch_flags
.bitfield
.cpuregzmm
)
9683 return (const reg_entry
*) NULL
;
9685 if (r
->reg_type
.bitfield
.regmask
9686 && !cpu_arch_flags
.bitfield
.cpuregmask
)
9687 return (const reg_entry
*) NULL
;
9689 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9690 if (!allow_index_reg
9691 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9692 return (const reg_entry
*) NULL
;
9694 /* Upper 16 vector register is only available with VREX in 64bit
9696 if ((r
->reg_flags
& RegVRex
))
9698 if (!cpu_arch_flags
.bitfield
.cpuvrex
9699 || flag_code
!= CODE_64BIT
)
9700 return (const reg_entry
*) NULL
;
9705 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9706 || r
->reg_type
.bitfield
.reg64
)
9707 && (!cpu_arch_flags
.bitfield
.cpulm
9708 || !operand_type_equal (&r
->reg_type
, &control
))
9709 && flag_code
!= CODE_64BIT
)
9710 return (const reg_entry
*) NULL
;
9712 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9713 return (const reg_entry
*) NULL
;
9718 /* REG_STRING starts *before* REGISTER_PREFIX. */
9720 static const reg_entry
*
9721 parse_register (char *reg_string
, char **end_op
)
9725 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9726 r
= parse_real_register (reg_string
, end_op
);
9731 char *save
= input_line_pointer
;
9735 input_line_pointer
= reg_string
;
9736 c
= get_symbol_name (®_string
);
9737 symbolP
= symbol_find (reg_string
);
9738 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9740 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9742 know (e
->X_op
== O_register
);
9743 know (e
->X_add_number
>= 0
9744 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9745 r
= i386_regtab
+ e
->X_add_number
;
9746 if ((r
->reg_flags
& RegVRex
))
9748 *end_op
= input_line_pointer
;
9750 *input_line_pointer
= c
;
9751 input_line_pointer
= save
;
9757 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9760 char *end
= input_line_pointer
;
9763 r
= parse_register (name
, &input_line_pointer
);
9764 if (r
&& end
<= input_line_pointer
)
9766 *nextcharP
= *input_line_pointer
;
9767 *input_line_pointer
= 0;
9768 e
->X_op
= O_register
;
9769 e
->X_add_number
= r
- i386_regtab
;
9772 input_line_pointer
= end
;
9774 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9778 md_operand (expressionS
*e
)
9783 switch (*input_line_pointer
)
9785 case REGISTER_PREFIX
:
9786 r
= parse_real_register (input_line_pointer
, &end
);
9789 e
->X_op
= O_register
;
9790 e
->X_add_number
= r
- i386_regtab
;
9791 input_line_pointer
= end
;
9796 gas_assert (intel_syntax
);
9797 end
= input_line_pointer
++;
9799 if (*input_line_pointer
== ']')
9801 ++input_line_pointer
;
9802 e
->X_op_symbol
= make_expr_symbol (e
);
9803 e
->X_add_symbol
= NULL
;
9804 e
->X_add_number
= 0;
9810 input_line_pointer
= end
;
9817 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9818 const char *md_shortopts
= "kVQ:sqn";
9820 const char *md_shortopts
= "qn";
9823 #define OPTION_32 (OPTION_MD_BASE + 0)
9824 #define OPTION_64 (OPTION_MD_BASE + 1)
9825 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9826 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9827 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9828 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9829 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9830 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9831 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9832 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9833 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9834 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9835 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9836 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9837 #define OPTION_X32 (OPTION_MD_BASE + 14)
9838 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9839 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9840 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9841 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9842 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9843 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9844 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9845 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9846 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9847 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9848 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
9850 struct option md_longopts
[] =
9852 {"32", no_argument
, NULL
, OPTION_32
},
9853 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9854 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9855 {"64", no_argument
, NULL
, OPTION_64
},
9857 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9858 {"x32", no_argument
, NULL
, OPTION_X32
},
9859 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
9861 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9862 {"march", required_argument
, NULL
, OPTION_MARCH
},
9863 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9864 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9865 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9866 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9867 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9868 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9869 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9870 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9871 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9872 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9873 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9874 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9875 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9876 # if defined (TE_PE) || defined (TE_PEP)
9877 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9879 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
9880 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
9881 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
9882 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9883 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
9884 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
9885 {NULL
, no_argument
, NULL
, 0}
9887 size_t md_longopts_size
= sizeof (md_longopts
);
9890 md_parse_option (int c
, const char *arg
)
9893 char *arch
, *next
, *saved
;
9898 optimize_align_code
= 0;
9905 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9906 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9907 should be emitted or not. FIXME: Not implemented. */
9911 /* -V: SVR4 argument to print version ID. */
9913 print_version_id ();
9916 /* -k: Ignore for FreeBSD compatibility. */
9921 /* -s: On i386 Solaris, this tells the native assembler to use
9922 .stab instead of .stab.excl. We always use .stab anyhow. */
9925 case OPTION_MSHARED
:
9929 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9930 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9933 const char **list
, **l
;
9935 list
= bfd_target_list ();
9936 for (l
= list
; *l
!= NULL
; l
++)
9937 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9938 || strcmp (*l
, "coff-x86-64") == 0
9939 || strcmp (*l
, "pe-x86-64") == 0
9940 || strcmp (*l
, "pei-x86-64") == 0
9941 || strcmp (*l
, "mach-o-x86-64") == 0)
9943 default_arch
= "x86_64";
9947 as_fatal (_("no compiled in support for x86_64"));
9953 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9957 const char **list
, **l
;
9959 list
= bfd_target_list ();
9960 for (l
= list
; *l
!= NULL
; l
++)
9961 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9963 default_arch
= "x86_64:32";
9967 as_fatal (_("no compiled in support for 32bit x86_64"));
9971 as_fatal (_("32bit x86_64 is only supported for ELF"));
9976 default_arch
= "i386";
9980 #ifdef SVR4_COMMENT_CHARS
9985 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
9987 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9991 i386_comment_chars
= n
;
9997 saved
= xstrdup (arg
);
9999 /* Allow -march=+nosse. */
10005 as_fatal (_("invalid -march= option: `%s'"), arg
);
10006 next
= strchr (arch
, '+');
10009 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10011 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
10014 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10017 cpu_arch_name
= cpu_arch
[j
].name
;
10018 cpu_sub_arch_name
= NULL
;
10019 cpu_arch_flags
= cpu_arch
[j
].flags
;
10020 cpu_arch_isa
= cpu_arch
[j
].type
;
10021 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
10022 if (!cpu_arch_tune_set
)
10024 cpu_arch_tune
= cpu_arch_isa
;
10025 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10029 else if (*cpu_arch
[j
].name
== '.'
10030 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
10032 /* ISA entension. */
10033 i386_cpu_flags flags
;
10035 flags
= cpu_flags_or (cpu_arch_flags
,
10036 cpu_arch
[j
].flags
);
10038 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10040 if (cpu_sub_arch_name
)
10042 char *name
= cpu_sub_arch_name
;
10043 cpu_sub_arch_name
= concat (name
,
10045 (const char *) NULL
);
10049 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
10050 cpu_arch_flags
= flags
;
10051 cpu_arch_isa_flags
= flags
;
10057 if (j
>= ARRAY_SIZE (cpu_arch
))
10059 /* Disable an ISA entension. */
10060 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10061 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
10063 i386_cpu_flags flags
;
10065 flags
= cpu_flags_and_not (cpu_arch_flags
,
10066 cpu_noarch
[j
].flags
);
10067 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10069 if (cpu_sub_arch_name
)
10071 char *name
= cpu_sub_arch_name
;
10072 cpu_sub_arch_name
= concat (arch
,
10073 (const char *) NULL
);
10077 cpu_sub_arch_name
= xstrdup (arch
);
10078 cpu_arch_flags
= flags
;
10079 cpu_arch_isa_flags
= flags
;
10084 if (j
>= ARRAY_SIZE (cpu_noarch
))
10085 j
= ARRAY_SIZE (cpu_arch
);
10088 if (j
>= ARRAY_SIZE (cpu_arch
))
10089 as_fatal (_("invalid -march= option: `%s'"), arg
);
10093 while (next
!= NULL
);
10099 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10100 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10102 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
10104 cpu_arch_tune_set
= 1;
10105 cpu_arch_tune
= cpu_arch
[j
].type
;
10106 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10110 if (j
>= ARRAY_SIZE (cpu_arch
))
10111 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10114 case OPTION_MMNEMONIC
:
10115 if (strcasecmp (arg
, "att") == 0)
10116 intel_mnemonic
= 0;
10117 else if (strcasecmp (arg
, "intel") == 0)
10118 intel_mnemonic
= 1;
10120 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10123 case OPTION_MSYNTAX
:
10124 if (strcasecmp (arg
, "att") == 0)
10126 else if (strcasecmp (arg
, "intel") == 0)
10129 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10132 case OPTION_MINDEX_REG
:
10133 allow_index_reg
= 1;
10136 case OPTION_MNAKED_REG
:
10137 allow_naked_reg
= 1;
10140 case OPTION_MOLD_GCC
:
10144 case OPTION_MSSE2AVX
:
10148 case OPTION_MSSE_CHECK
:
10149 if (strcasecmp (arg
, "error") == 0)
10150 sse_check
= check_error
;
10151 else if (strcasecmp (arg
, "warning") == 0)
10152 sse_check
= check_warning
;
10153 else if (strcasecmp (arg
, "none") == 0)
10154 sse_check
= check_none
;
10156 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10159 case OPTION_MOPERAND_CHECK
:
10160 if (strcasecmp (arg
, "error") == 0)
10161 operand_check
= check_error
;
10162 else if (strcasecmp (arg
, "warning") == 0)
10163 operand_check
= check_warning
;
10164 else if (strcasecmp (arg
, "none") == 0)
10165 operand_check
= check_none
;
10167 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10170 case OPTION_MAVXSCALAR
:
10171 if (strcasecmp (arg
, "128") == 0)
10172 avxscalar
= vex128
;
10173 else if (strcasecmp (arg
, "256") == 0)
10174 avxscalar
= vex256
;
10176 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10179 case OPTION_MADD_BND_PREFIX
:
10180 add_bnd_prefix
= 1;
10183 case OPTION_MEVEXLIG
:
10184 if (strcmp (arg
, "128") == 0)
10185 evexlig
= evexl128
;
10186 else if (strcmp (arg
, "256") == 0)
10187 evexlig
= evexl256
;
10188 else if (strcmp (arg
, "512") == 0)
10189 evexlig
= evexl512
;
10191 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10194 case OPTION_MEVEXRCIG
:
10195 if (strcmp (arg
, "rne") == 0)
10197 else if (strcmp (arg
, "rd") == 0)
10199 else if (strcmp (arg
, "ru") == 0)
10201 else if (strcmp (arg
, "rz") == 0)
10204 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10207 case OPTION_MEVEXWIG
:
10208 if (strcmp (arg
, "0") == 0)
10210 else if (strcmp (arg
, "1") == 0)
10213 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10216 # if defined (TE_PE) || defined (TE_PEP)
10217 case OPTION_MBIG_OBJ
:
10222 case OPTION_MOMIT_LOCK_PREFIX
:
10223 if (strcasecmp (arg
, "yes") == 0)
10224 omit_lock_prefix
= 1;
10225 else if (strcasecmp (arg
, "no") == 0)
10226 omit_lock_prefix
= 0;
10228 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10231 case OPTION_MFENCE_AS_LOCK_ADD
:
10232 if (strcasecmp (arg
, "yes") == 0)
10234 else if (strcasecmp (arg
, "no") == 0)
10237 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10240 case OPTION_MRELAX_RELOCATIONS
:
10241 if (strcasecmp (arg
, "yes") == 0)
10242 generate_relax_relocations
= 1;
10243 else if (strcasecmp (arg
, "no") == 0)
10244 generate_relax_relocations
= 0;
10246 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10249 case OPTION_MAMD64
:
10253 case OPTION_MINTEL64
:
10263 #define MESSAGE_TEMPLATE \
10267 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10268 int *left_p
, const char *name
, int len
)
10270 int size
= sizeof (MESSAGE_TEMPLATE
);
10271 int left
= *left_p
;
10273 /* Reserve 2 spaces for ", " or ",\0" */
10276 /* Check if there is any room. */
10284 p
= mempcpy (p
, name
, len
);
10288 /* Output the current message now and start a new one. */
10291 fprintf (stream
, "%s\n", message
);
10293 left
= size
- (start
- message
) - len
- 2;
10295 gas_assert (left
>= 0);
10297 p
= mempcpy (p
, name
, len
);
10305 show_arch (FILE *stream
, int ext
, int check
)
10307 static char message
[] = MESSAGE_TEMPLATE
;
10308 char *start
= message
+ 27;
10310 int size
= sizeof (MESSAGE_TEMPLATE
);
10317 left
= size
- (start
- message
);
10318 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10320 /* Should it be skipped? */
10321 if (cpu_arch
[j
].skip
)
10324 name
= cpu_arch
[j
].name
;
10325 len
= cpu_arch
[j
].len
;
10328 /* It is an extension. Skip if we aren't asked to show it. */
10339 /* It is an processor. Skip if we show only extension. */
10342 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10344 /* It is an impossible processor - skip. */
10348 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10351 /* Display disabled extensions. */
10353 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10355 name
= cpu_noarch
[j
].name
;
10356 len
= cpu_noarch
[j
].len
;
10357 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10362 fprintf (stream
, "%s\n", message
);
10366 md_show_usage (FILE *stream
)
10368 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10369 fprintf (stream
, _("\
10371 -V print assembler version number\n\
10374 fprintf (stream
, _("\
10375 -n Do not optimize code alignment\n\
10376 -q quieten some warnings\n"));
10377 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10378 fprintf (stream
, _("\
10381 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10382 || defined (TE_PE) || defined (TE_PEP))
10383 fprintf (stream
, _("\
10384 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10386 #ifdef SVR4_COMMENT_CHARS
10387 fprintf (stream
, _("\
10388 --divide do not treat `/' as a comment character\n"));
10390 fprintf (stream
, _("\
10391 --divide ignored\n"));
10393 fprintf (stream
, _("\
10394 -march=CPU[,+EXTENSION...]\n\
10395 generate code for CPU and EXTENSION, CPU is one of:\n"));
10396 show_arch (stream
, 0, 1);
10397 fprintf (stream
, _("\
10398 EXTENSION is combination of:\n"));
10399 show_arch (stream
, 1, 0);
10400 fprintf (stream
, _("\
10401 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10402 show_arch (stream
, 0, 0);
10403 fprintf (stream
, _("\
10404 -msse2avx encode SSE instructions with VEX prefix\n"));
10405 fprintf (stream
, _("\
10406 -msse-check=[none|error|warning]\n\
10407 check SSE instructions\n"));
10408 fprintf (stream
, _("\
10409 -moperand-check=[none|error|warning]\n\
10410 check operand combinations for validity\n"));
10411 fprintf (stream
, _("\
10412 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10414 fprintf (stream
, _("\
10415 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10417 fprintf (stream
, _("\
10418 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10419 for EVEX.W bit ignored instructions\n"));
10420 fprintf (stream
, _("\
10421 -mevexrcig=[rne|rd|ru|rz]\n\
10422 encode EVEX instructions with specific EVEX.RC value\n\
10423 for SAE-only ignored instructions\n"));
10424 fprintf (stream
, _("\
10425 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10426 fprintf (stream
, _("\
10427 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10428 fprintf (stream
, _("\
10429 -mindex-reg support pseudo index registers\n"));
10430 fprintf (stream
, _("\
10431 -mnaked-reg don't require `%%' prefix for registers\n"));
10432 fprintf (stream
, _("\
10433 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10434 fprintf (stream
, _("\
10435 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10436 fprintf (stream
, _("\
10437 -mshared disable branch optimization for shared code\n"));
10438 # if defined (TE_PE) || defined (TE_PEP)
10439 fprintf (stream
, _("\
10440 -mbig-obj generate big object files\n"));
10442 fprintf (stream
, _("\
10443 -momit-lock-prefix=[no|yes]\n\
10444 strip all lock prefixes\n"));
10445 fprintf (stream
, _("\
10446 -mfence-as-lock-add=[no|yes]\n\
10447 encode lfence, mfence and sfence as\n\
10448 lock addl $0x0, (%%{re}sp)\n"));
10449 fprintf (stream
, _("\
10450 -mrelax-relocations=[no|yes]\n\
10451 generate relax relocations\n"));
10452 fprintf (stream
, _("\
10453 -mamd64 accept only AMD64 ISA\n"));
10454 fprintf (stream
, _("\
10455 -mintel64 accept only Intel64 ISA\n"));
10458 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10459 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10460 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10462 /* Pick the target format to use. */
10465 i386_target_format (void)
10467 if (!strncmp (default_arch
, "x86_64", 6))
10469 update_code_flag (CODE_64BIT
, 1);
10470 if (default_arch
[6] == '\0')
10471 x86_elf_abi
= X86_64_ABI
;
10473 x86_elf_abi
= X86_64_X32_ABI
;
10475 else if (!strcmp (default_arch
, "i386"))
10476 update_code_flag (CODE_32BIT
, 1);
10477 else if (!strcmp (default_arch
, "iamcu"))
10479 update_code_flag (CODE_32BIT
, 1);
10480 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10482 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10483 cpu_arch_name
= "iamcu";
10484 cpu_sub_arch_name
= NULL
;
10485 cpu_arch_flags
= iamcu_flags
;
10486 cpu_arch_isa
= PROCESSOR_IAMCU
;
10487 cpu_arch_isa_flags
= iamcu_flags
;
10488 if (!cpu_arch_tune_set
)
10490 cpu_arch_tune
= cpu_arch_isa
;
10491 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10494 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
10495 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10499 as_fatal (_("unknown architecture"));
10501 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10502 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10503 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10504 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10506 switch (OUTPUT_FLAVOR
)
10508 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10509 case bfd_target_aout_flavour
:
10510 return AOUT_TARGET_FORMAT
;
10512 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10513 # if defined (TE_PE) || defined (TE_PEP)
10514 case bfd_target_coff_flavour
:
10515 if (flag_code
== CODE_64BIT
)
10516 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10519 # elif defined (TE_GO32)
10520 case bfd_target_coff_flavour
:
10521 return "coff-go32";
10523 case bfd_target_coff_flavour
:
10524 return "coff-i386";
10527 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10528 case bfd_target_elf_flavour
:
10530 const char *format
;
10532 switch (x86_elf_abi
)
10535 format
= ELF_TARGET_FORMAT
;
10538 use_rela_relocations
= 1;
10540 format
= ELF_TARGET_FORMAT64
;
10542 case X86_64_X32_ABI
:
10543 use_rela_relocations
= 1;
10545 disallow_64bit_reloc
= 1;
10546 format
= ELF_TARGET_FORMAT32
;
10549 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10551 if (x86_elf_abi
!= X86_64_ABI
)
10552 as_fatal (_("Intel L1OM is 64bit only"));
10553 return ELF_TARGET_L1OM_FORMAT
;
10555 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10557 if (x86_elf_abi
!= X86_64_ABI
)
10558 as_fatal (_("Intel K1OM is 64bit only"));
10559 return ELF_TARGET_K1OM_FORMAT
;
10561 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10563 if (x86_elf_abi
!= I386_ABI
)
10564 as_fatal (_("Intel MCU is 32bit only"));
10565 return ELF_TARGET_IAMCU_FORMAT
;
10571 #if defined (OBJ_MACH_O)
10572 case bfd_target_mach_o_flavour
:
10573 if (flag_code
== CODE_64BIT
)
10575 use_rela_relocations
= 1;
10577 return "mach-o-x86-64";
10580 return "mach-o-i386";
10588 #endif /* OBJ_MAYBE_ more than one */
10591 md_undefined_symbol (char *name
)
10593 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10594 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10595 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10596 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10600 if (symbol_find (name
))
10601 as_bad (_("GOT already in symbol table"));
10602 GOT_symbol
= symbol_new (name
, undefined_section
,
10603 (valueT
) 0, &zero_address_frag
);
10610 /* Round up a section size to the appropriate boundary. */
10613 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10615 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10616 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10618 /* For a.out, force the section size to be aligned. If we don't do
10619 this, BFD will align it for us, but it will not write out the
10620 final bytes of the section. This may be a bug in BFD, but it is
10621 easier to fix it here since that is how the other a.out targets
10625 align
= bfd_get_section_alignment (stdoutput
, segment
);
10626 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
10633 /* On the i386, PC-relative offsets are relative to the start of the
10634 next instruction. That is, the address of the offset, plus its
10635 size, since the offset is always the last part of the insn. */
10638 md_pcrel_from (fixS
*fixP
)
10640 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10646 s_bss (int ignore ATTRIBUTE_UNUSED
)
10650 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10652 obj_elf_section_change_hook ();
10654 temp
= get_absolute_expression ();
10655 subseg_set (bss_section
, (subsegT
) temp
);
10656 demand_empty_rest_of_line ();
10662 i386_validate_fix (fixS
*fixp
)
10664 if (fixp
->fx_subsy
)
10666 if (fixp
->fx_subsy
== GOT_symbol
)
10668 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10672 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10673 if (fixp
->fx_tcbit2
)
10674 fixp
->fx_r_type
= (fixp
->fx_tcbit
10675 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10676 : BFD_RELOC_X86_64_GOTPCRELX
);
10679 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10684 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10686 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10688 fixp
->fx_subsy
= 0;
10691 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10692 else if (!object_64bit
)
10694 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
10695 && fixp
->fx_tcbit2
)
10696 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
10702 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10705 bfd_reloc_code_real_type code
;
10707 switch (fixp
->fx_r_type
)
10709 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10710 case BFD_RELOC_SIZE32
:
10711 case BFD_RELOC_SIZE64
:
10712 if (S_IS_DEFINED (fixp
->fx_addsy
)
10713 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10715 /* Resolve size relocation against local symbol to size of
10716 the symbol plus addend. */
10717 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10718 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10719 && !fits_in_unsigned_long (value
))
10720 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10721 _("symbol size computation overflow"));
10722 fixp
->fx_addsy
= NULL
;
10723 fixp
->fx_subsy
= NULL
;
10724 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10728 /* Fall through. */
10730 case BFD_RELOC_X86_64_PLT32
:
10731 case BFD_RELOC_X86_64_GOT32
:
10732 case BFD_RELOC_X86_64_GOTPCREL
:
10733 case BFD_RELOC_X86_64_GOTPCRELX
:
10734 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10735 case BFD_RELOC_386_PLT32
:
10736 case BFD_RELOC_386_GOT32
:
10737 case BFD_RELOC_386_GOT32X
:
10738 case BFD_RELOC_386_GOTOFF
:
10739 case BFD_RELOC_386_GOTPC
:
10740 case BFD_RELOC_386_TLS_GD
:
10741 case BFD_RELOC_386_TLS_LDM
:
10742 case BFD_RELOC_386_TLS_LDO_32
:
10743 case BFD_RELOC_386_TLS_IE_32
:
10744 case BFD_RELOC_386_TLS_IE
:
10745 case BFD_RELOC_386_TLS_GOTIE
:
10746 case BFD_RELOC_386_TLS_LE_32
:
10747 case BFD_RELOC_386_TLS_LE
:
10748 case BFD_RELOC_386_TLS_GOTDESC
:
10749 case BFD_RELOC_386_TLS_DESC_CALL
:
10750 case BFD_RELOC_X86_64_TLSGD
:
10751 case BFD_RELOC_X86_64_TLSLD
:
10752 case BFD_RELOC_X86_64_DTPOFF32
:
10753 case BFD_RELOC_X86_64_DTPOFF64
:
10754 case BFD_RELOC_X86_64_GOTTPOFF
:
10755 case BFD_RELOC_X86_64_TPOFF32
:
10756 case BFD_RELOC_X86_64_TPOFF64
:
10757 case BFD_RELOC_X86_64_GOTOFF64
:
10758 case BFD_RELOC_X86_64_GOTPC32
:
10759 case BFD_RELOC_X86_64_GOT64
:
10760 case BFD_RELOC_X86_64_GOTPCREL64
:
10761 case BFD_RELOC_X86_64_GOTPC64
:
10762 case BFD_RELOC_X86_64_GOTPLT64
:
10763 case BFD_RELOC_X86_64_PLTOFF64
:
10764 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10765 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10766 case BFD_RELOC_RVA
:
10767 case BFD_RELOC_VTABLE_ENTRY
:
10768 case BFD_RELOC_VTABLE_INHERIT
:
10770 case BFD_RELOC_32_SECREL
:
10772 code
= fixp
->fx_r_type
;
10774 case BFD_RELOC_X86_64_32S
:
10775 if (!fixp
->fx_pcrel
)
10777 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10778 code
= fixp
->fx_r_type
;
10781 /* Fall through. */
10783 if (fixp
->fx_pcrel
)
10785 switch (fixp
->fx_size
)
10788 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10789 _("can not do %d byte pc-relative relocation"),
10791 code
= BFD_RELOC_32_PCREL
;
10793 case 1: code
= BFD_RELOC_8_PCREL
; break;
10794 case 2: code
= BFD_RELOC_16_PCREL
; break;
10795 case 4: code
= BFD_RELOC_32_PCREL
; break;
10797 case 8: code
= BFD_RELOC_64_PCREL
; break;
10803 switch (fixp
->fx_size
)
10806 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10807 _("can not do %d byte relocation"),
10809 code
= BFD_RELOC_32
;
10811 case 1: code
= BFD_RELOC_8
; break;
10812 case 2: code
= BFD_RELOC_16
; break;
10813 case 4: code
= BFD_RELOC_32
; break;
10815 case 8: code
= BFD_RELOC_64
; break;
10822 if ((code
== BFD_RELOC_32
10823 || code
== BFD_RELOC_32_PCREL
10824 || code
== BFD_RELOC_X86_64_32S
)
10826 && fixp
->fx_addsy
== GOT_symbol
)
10829 code
= BFD_RELOC_386_GOTPC
;
10831 code
= BFD_RELOC_X86_64_GOTPC32
;
10833 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10835 && fixp
->fx_addsy
== GOT_symbol
)
10837 code
= BFD_RELOC_X86_64_GOTPC64
;
10840 rel
= XNEW (arelent
);
10841 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
10842 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10844 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10846 if (!use_rela_relocations
)
10848 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10849 vtable entry to be used in the relocation's section offset. */
10850 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10851 rel
->address
= fixp
->fx_offset
;
10852 #if defined (OBJ_COFF) && defined (TE_PE)
10853 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10854 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10859 /* Use the rela in 64bit mode. */
10862 if (disallow_64bit_reloc
)
10865 case BFD_RELOC_X86_64_DTPOFF64
:
10866 case BFD_RELOC_X86_64_TPOFF64
:
10867 case BFD_RELOC_64_PCREL
:
10868 case BFD_RELOC_X86_64_GOTOFF64
:
10869 case BFD_RELOC_X86_64_GOT64
:
10870 case BFD_RELOC_X86_64_GOTPCREL64
:
10871 case BFD_RELOC_X86_64_GOTPC64
:
10872 case BFD_RELOC_X86_64_GOTPLT64
:
10873 case BFD_RELOC_X86_64_PLTOFF64
:
10874 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10875 _("cannot represent relocation type %s in x32 mode"),
10876 bfd_get_reloc_code_name (code
));
10882 if (!fixp
->fx_pcrel
)
10883 rel
->addend
= fixp
->fx_offset
;
10887 case BFD_RELOC_X86_64_PLT32
:
10888 case BFD_RELOC_X86_64_GOT32
:
10889 case BFD_RELOC_X86_64_GOTPCREL
:
10890 case BFD_RELOC_X86_64_GOTPCRELX
:
10891 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10892 case BFD_RELOC_X86_64_TLSGD
:
10893 case BFD_RELOC_X86_64_TLSLD
:
10894 case BFD_RELOC_X86_64_GOTTPOFF
:
10895 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10896 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10897 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10900 rel
->addend
= (section
->vma
10902 + fixp
->fx_addnumber
10903 + md_pcrel_from (fixp
));
10908 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10909 if (rel
->howto
== NULL
)
10911 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10912 _("cannot represent relocation type %s"),
10913 bfd_get_reloc_code_name (code
));
10914 /* Set howto to a garbage value so that we can keep going. */
10915 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10916 gas_assert (rel
->howto
!= NULL
);
10922 #include "tc-i386-intel.c"
10925 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10927 int saved_naked_reg
;
10928 char saved_register_dot
;
10930 saved_naked_reg
= allow_naked_reg
;
10931 allow_naked_reg
= 1;
10932 saved_register_dot
= register_chars
['.'];
10933 register_chars
['.'] = '.';
10934 allow_pseudo_reg
= 1;
10935 expression_and_evaluate (exp
);
10936 allow_pseudo_reg
= 0;
10937 register_chars
['.'] = saved_register_dot
;
10938 allow_naked_reg
= saved_naked_reg
;
10940 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10942 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10944 exp
->X_op
= O_constant
;
10945 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10946 .dw2_regnum
[flag_code
>> 1];
10949 exp
->X_op
= O_illegal
;
10954 tc_x86_frame_initial_instructions (void)
10956 static unsigned int sp_regno
[2];
10958 if (!sp_regno
[flag_code
>> 1])
10960 char *saved_input
= input_line_pointer
;
10961 char sp
[][4] = {"esp", "rsp"};
10964 input_line_pointer
= sp
[flag_code
>> 1];
10965 tc_x86_parse_to_dw2regnum (&exp
);
10966 gas_assert (exp
.X_op
== O_constant
);
10967 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10968 input_line_pointer
= saved_input
;
10971 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10972 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10976 x86_dwarf2_addr_size (void)
10978 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10979 if (x86_elf_abi
== X86_64_X32_ABI
)
10982 return bfd_arch_bits_per_address (stdoutput
) / 8;
10986 i386_elf_section_type (const char *str
, size_t len
)
10988 if (flag_code
== CODE_64BIT
10989 && len
== sizeof ("unwind") - 1
10990 && strncmp (str
, "unwind", 6) == 0)
10991 return SHT_X86_64_UNWIND
;
10998 i386_solaris_fix_up_eh_frame (segT sec
)
11000 if (flag_code
== CODE_64BIT
)
11001 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
11007 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
11011 exp
.X_op
= O_secrel
;
11012 exp
.X_add_symbol
= symbol
;
11013 exp
.X_add_number
= 0;
11014 emit_expr (&exp
, size
);
11018 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11019 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11022 x86_64_section_letter (int letter
, const char **ptr_msg
)
11024 if (flag_code
== CODE_64BIT
)
11027 return SHF_X86_64_LARGE
;
11029 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11032 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
11037 x86_64_section_word (char *str
, size_t len
)
11039 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
11040 return SHF_X86_64_LARGE
;
11046 handle_large_common (int small ATTRIBUTE_UNUSED
)
11048 if (flag_code
!= CODE_64BIT
)
11050 s_comm_internal (0, elf_common_parse
);
11051 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11055 static segT lbss_section
;
11056 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
11057 asection
*saved_bss_section
= bss_section
;
11059 if (lbss_section
== NULL
)
11061 flagword applicable
;
11062 segT seg
= now_seg
;
11063 subsegT subseg
= now_subseg
;
11065 /* The .lbss section is for local .largecomm symbols. */
11066 lbss_section
= subseg_new (".lbss", 0);
11067 applicable
= bfd_applicable_section_flags (stdoutput
);
11068 bfd_set_section_flags (stdoutput
, lbss_section
,
11069 applicable
& SEC_ALLOC
);
11070 seg_info (lbss_section
)->bss
= 1;
11072 subseg_set (seg
, subseg
);
11075 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
11076 bss_section
= lbss_section
;
11078 s_comm_internal (0, elf_common_parse
);
11080 elf_com_section_ptr
= saved_com_section_ptr
;
11081 bss_section
= saved_bss_section
;
11084 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */