1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static INLINE
unsigned int mode_from_disp_size
PARAMS ((unsigned int));
67 static INLINE
int fits_in_signed_byte
PARAMS ((offsetT
));
68 static INLINE
int fits_in_unsigned_byte
PARAMS ((offsetT
));
69 static INLINE
int fits_in_unsigned_word
PARAMS ((offsetT
));
70 static INLINE
int fits_in_signed_word
PARAMS ((offsetT
));
71 static INLINE
int fits_in_unsigned_long
PARAMS ((offsetT
));
72 static INLINE
int fits_in_signed_long
PARAMS ((offsetT
));
73 static int smallest_imm_type
PARAMS ((offsetT
));
74 static offsetT offset_in_range
PARAMS ((offsetT
, int));
75 static int add_prefix
PARAMS ((unsigned int));
76 static void set_code_flag
PARAMS ((int));
77 static void set_16bit_gcc_code_flag
PARAMS ((int));
78 static void set_intel_syntax
PARAMS ((int));
79 static void set_cpu_arch
PARAMS ((int));
81 static void pe_directive_secrel
PARAMS ((int));
83 static char *output_invalid
PARAMS ((int c
));
84 static int i386_operand
PARAMS ((char *operand_string
));
85 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
86 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
88 static char *parse_insn
PARAMS ((char *, char *));
89 static char *parse_operands
PARAMS ((char *, const char *));
90 static void swap_operands
PARAMS ((void));
91 static void optimize_imm
PARAMS ((void));
92 static void optimize_disp
PARAMS ((void));
93 static int match_template
PARAMS ((void));
94 static int check_string
PARAMS ((void));
95 static int process_suffix
PARAMS ((void));
96 static int check_byte_reg
PARAMS ((void));
97 static int check_long_reg
PARAMS ((void));
98 static int check_qword_reg
PARAMS ((void));
99 static int check_word_reg
PARAMS ((void));
100 static int finalize_imm
PARAMS ((void));
101 static int process_operands
PARAMS ((void));
102 static const seg_entry
*build_modrm_byte
PARAMS ((void));
103 static void output_insn
PARAMS ((void));
104 static void output_branch
PARAMS ((void));
105 static void output_jump
PARAMS ((void));
106 static void output_interseg_jump
PARAMS ((void));
107 static void output_imm
PARAMS ((fragS
*insn_start_frag
,
108 offsetT insn_start_off
));
109 static void output_disp
PARAMS ((fragS
*insn_start_frag
,
110 offsetT insn_start_off
));
112 static void s_bss
PARAMS ((int));
115 static const char *default_arch
= DEFAULT_ARCH
;
117 /* 'md_assemble ()' gathers together information and puts it into a
124 const reg_entry
*regs
;
129 /* TM holds the template for the insn were currently assembling. */
132 /* SUFFIX holds the instruction mnemonic suffix if given.
133 (e.g. 'l' for 'movl') */
136 /* OPERANDS gives the number of given operands. */
137 unsigned int operands
;
139 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
140 of given register, displacement, memory operands and immediate
142 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
144 /* TYPES [i] is the type (see above #defines) which tells us how to
145 use OP[i] for the corresponding operand. */
146 unsigned int types
[MAX_OPERANDS
];
148 /* Displacement expression, immediate expression, or register for each
150 union i386_op op
[MAX_OPERANDS
];
152 /* Flags for operands. */
153 unsigned int flags
[MAX_OPERANDS
];
154 #define Operand_PCrel 1
156 /* Relocation type for operand */
157 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
159 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
160 the base index byte below. */
161 const reg_entry
*base_reg
;
162 const reg_entry
*index_reg
;
163 unsigned int log2_scale_factor
;
165 /* SEG gives the seg_entries of this insn. They are zero unless
166 explicit segment overrides are given. */
167 const seg_entry
*seg
[2];
169 /* PREFIX holds all the given prefix opcodes (usually null).
170 PREFIXES is the number of prefix opcodes. */
171 unsigned int prefixes
;
172 unsigned char prefix
[MAX_PREFIXES
];
174 /* RM and SIB are the modrm byte and the sib byte where the
175 addressing modes of this insn are encoded. */
182 typedef struct _i386_insn i386_insn
;
184 /* List of chars besides those in app.c:symbol_chars that can start an
185 operand. Used to prevent the scrubber eating vital white-space. */
186 const char extra_symbol_chars
[] = "*%-(["
195 #if (defined (TE_I386AIX) \
196 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
197 && !defined (TE_LINUX) \
198 && !defined (TE_NETWARE) \
199 && !defined (TE_FreeBSD) \
200 && !defined (TE_NetBSD)))
201 /* This array holds the chars that always start a comment. If the
202 pre-processor is disabled, these aren't very useful. */
203 const char comment_chars
[] = "#/";
204 #define PREFIX_SEPARATOR '\\'
206 /* This array holds the chars that only start a comment at the beginning of
207 a line. If the line seems to have the form '# 123 filename'
208 .line and .file directives will appear in the pre-processed output.
209 Note that input_file.c hand checks for '#' at the beginning of the
210 first line of the input file. This is because the compiler outputs
211 #NO_APP at the beginning of its output.
212 Also note that comments started like this one will always work if
213 '/' isn't otherwise defined. */
214 const char line_comment_chars
[] = "#";
217 /* Putting '/' here makes it impossible to use the divide operator.
218 However, we need it for compatibility with SVR4 systems. */
219 const char comment_chars
[] = "#";
220 #define PREFIX_SEPARATOR '/'
222 const char line_comment_chars
[] = "/#";
225 const char line_separator_chars
[] = ";";
227 /* Chars that can be used to separate mant from exp in floating point
229 const char EXP_CHARS
[] = "eE";
231 /* Chars that mean this number is a floating point constant
234 const char FLT_CHARS
[] = "fFdDxX";
236 /* Tables for lexical analysis. */
237 static char mnemonic_chars
[256];
238 static char register_chars
[256];
239 static char operand_chars
[256];
240 static char identifier_chars
[256];
241 static char digit_chars
[256];
243 /* Lexical macros. */
244 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
245 #define is_operand_char(x) (operand_chars[(unsigned char) x])
246 #define is_register_char(x) (register_chars[(unsigned char) x])
247 #define is_space_char(x) ((x) == ' ')
248 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
249 #define is_digit_char(x) (digit_chars[(unsigned char) x])
251 /* All non-digit non-letter characters that may occur in an operand. */
252 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
254 /* md_assemble() always leaves the strings it's passed unaltered. To
255 effect this we maintain a stack of saved characters that we've smashed
256 with '\0's (indicating end of strings for various sub-fields of the
257 assembler instruction). */
258 static char save_stack
[32];
259 static char *save_stack_p
;
260 #define END_STRING_AND_SAVE(s) \
261 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
262 #define RESTORE_END_STRING(s) \
263 do { *(s) = *--save_stack_p; } while (0)
265 /* The instruction we're assembling. */
268 /* Possible templates for current insn. */
269 static const templates
*current_templates
;
271 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
272 static expressionS disp_expressions
[2], im_expressions
[2];
274 /* Current operand we are working on. */
275 static int this_operand
;
277 /* We support four different modes. FLAG_CODE variable is used to distinguish
284 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
286 static enum flag_code flag_code
;
287 static int use_rela_relocations
= 0;
289 /* The names used to print error messages. */
290 static const char *flag_code_names
[] =
297 /* 1 for intel syntax,
299 static int intel_syntax
= 0;
301 /* 1 if register prefix % not required. */
302 static int allow_naked_reg
= 0;
304 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
305 leave, push, and pop instructions so that gcc has the same stack
306 frame as in 32 bit mode. */
307 static char stackop_size
= '\0';
309 /* Non-zero to optimize code alignment. */
310 int optimize_align_code
= 1;
312 /* Non-zero to quieten some warnings. */
313 static int quiet_warnings
= 0;
316 static const char *cpu_arch_name
= NULL
;
317 static const char *cpu_sub_arch_name
= NULL
;
319 /* CPU feature flags. */
320 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
322 /* If set, conditional jumps are not automatically promoted to handle
323 larger than a byte offset. */
324 static unsigned int no_cond_jump_promotion
= 0;
326 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
327 static symbolS
*GOT_symbol
;
329 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
330 unsigned int x86_dwarf2_return_column
;
332 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
333 int x86_cie_data_alignment
;
335 /* Interface to relax_segment.
336 There are 3 major relax states for 386 jump insns because the
337 different types of jumps add different sizes to frags when we're
338 figuring out what sort of jump to choose to reach a given label. */
341 #define UNCOND_JUMP 0
343 #define COND_JUMP86 2
348 #define SMALL16 (SMALL | CODE16)
350 #define BIG16 (BIG | CODE16)
354 #define INLINE __inline__
360 #define ENCODE_RELAX_STATE(type, size) \
361 ((relax_substateT) (((type) << 2) | (size)))
362 #define TYPE_FROM_RELAX_STATE(s) \
364 #define DISP_SIZE_FROM_RELAX_STATE(s) \
365 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
367 /* This table is used by relax_frag to promote short jumps to long
368 ones where necessary. SMALL (short) jumps may be promoted to BIG
369 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
370 don't allow a short jump in a 32 bit code segment to be promoted to
371 a 16 bit offset jump because it's slower (requires data size
372 prefix), and doesn't work, unless the destination is in the bottom
373 64k of the code segment (The top 16 bits of eip are zeroed). */
375 const relax_typeS md_relax_table
[] =
378 1) most positive reach of this state,
379 2) most negative reach of this state,
380 3) how many bytes this mode will have in the variable part of the frag
381 4) which index into the table to try if we can't fit into this one. */
383 /* UNCOND_JUMP states. */
384 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
385 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
386 /* dword jmp adds 4 bytes to frag:
387 0 extra opcode bytes, 4 displacement bytes. */
389 /* word jmp adds 2 byte2 to frag:
390 0 extra opcode bytes, 2 displacement bytes. */
393 /* COND_JUMP states. */
394 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
395 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
396 /* dword conditionals adds 5 bytes to frag:
397 1 extra opcode byte, 4 displacement bytes. */
399 /* word conditionals add 3 bytes to frag:
400 1 extra opcode byte, 2 displacement bytes. */
403 /* COND_JUMP86 states. */
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
406 /* dword conditionals adds 5 bytes to frag:
407 1 extra opcode byte, 4 displacement bytes. */
409 /* word conditionals add 4 bytes to frag:
410 1 displacement byte and a 3 byte long branch insn. */
414 static const arch_entry cpu_arch
[] = {
416 {"i186", Cpu086
|Cpu186
},
417 {"i286", Cpu086
|Cpu186
|Cpu286
},
418 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
419 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
420 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
421 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
422 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
423 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
424 {"pentiumii", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
},
425 {"pentiumiii",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuMMX2
|CpuSSE
},
426 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
427 {"prescott", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuPNI
},
428 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
},
429 {"k6_2", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
430 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
431 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
433 {".sse", CpuMMX
|CpuMMX2
|CpuSSE
},
434 {".sse2", CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
435 {".3dnow", CpuMMX
|Cpu3dnow
},
436 {".3dnowa", CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
437 {".padlock", CpuPadLock
},
441 const pseudo_typeS md_pseudo_table
[] =
443 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
444 {"align", s_align_bytes
, 0},
446 {"align", s_align_ptwo
, 0},
448 {"arch", set_cpu_arch
, 0},
452 {"ffloat", float_cons
, 'f'},
453 {"dfloat", float_cons
, 'd'},
454 {"tfloat", float_cons
, 'x'},
456 {"noopt", s_ignore
, 0},
457 {"optim", s_ignore
, 0},
458 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
459 {"code16", set_code_flag
, CODE_16BIT
},
460 {"code32", set_code_flag
, CODE_32BIT
},
461 {"code64", set_code_flag
, CODE_64BIT
},
462 {"intel_syntax", set_intel_syntax
, 1},
463 {"att_syntax", set_intel_syntax
, 0},
464 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0},
465 {"loc", dwarf2_directive_loc
, 0},
467 {"secrel32", pe_directive_secrel
, 0},
472 /* For interface with expression (). */
473 extern char *input_line_pointer
;
475 /* Hash table for instruction mnemonic lookup. */
476 static struct hash_control
*op_hash
;
478 /* Hash table for register lookup. */
479 static struct hash_control
*reg_hash
;
482 i386_align_code (fragP
, count
)
486 /* Various efficient no-op patterns for aligning code labels.
487 Note: Don't try to assemble the instructions in the comments.
488 0L and 0w are not legal. */
489 static const char f32_1
[] =
491 static const char f32_2
[] =
492 {0x89,0xf6}; /* movl %esi,%esi */
493 static const char f32_3
[] =
494 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
495 static const char f32_4
[] =
496 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
497 static const char f32_5
[] =
499 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
500 static const char f32_6
[] =
501 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
502 static const char f32_7
[] =
503 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
504 static const char f32_8
[] =
506 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
507 static const char f32_9
[] =
508 {0x89,0xf6, /* movl %esi,%esi */
509 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
510 static const char f32_10
[] =
511 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
512 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
513 static const char f32_11
[] =
514 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
515 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
516 static const char f32_12
[] =
517 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
518 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
519 static const char f32_13
[] =
520 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
521 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
522 static const char f32_14
[] =
523 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
524 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
525 static const char f32_15
[] =
526 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
527 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
528 static const char f16_3
[] =
529 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
530 static const char f16_4
[] =
531 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
532 static const char f16_5
[] =
534 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
535 static const char f16_6
[] =
536 {0x89,0xf6, /* mov %si,%si */
537 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
538 static const char f16_7
[] =
539 {0x8d,0x74,0x00, /* lea 0(%si),%si */
540 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
541 static const char f16_8
[] =
542 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
543 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
544 static const char *const f32_patt
[] = {
545 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
546 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
548 static const char *const f16_patt
[] = {
549 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
550 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
553 if (count
<= 0 || count
> 15)
556 /* The recommended way to pad 64bit code is to use NOPs preceded by
557 maximally four 0x66 prefixes. Balance the size of nops. */
558 if (flag_code
== CODE_64BIT
)
561 int nnops
= (count
+ 3) / 4;
562 int len
= count
/ nnops
;
563 int remains
= count
- nnops
* len
;
566 for (i
= 0; i
< remains
; i
++)
568 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
569 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
572 for (; i
< nnops
; i
++)
574 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
575 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
580 if (flag_code
== CODE_16BIT
)
582 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
583 f16_patt
[count
- 1], count
);
585 /* Adjust jump offset. */
586 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
589 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
590 f32_patt
[count
- 1], count
);
591 fragP
->fr_var
= count
;
594 static INLINE
unsigned int
595 mode_from_disp_size (t
)
598 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
602 fits_in_signed_byte (num
)
605 return (num
>= -128) && (num
<= 127);
609 fits_in_unsigned_byte (num
)
612 return (num
& 0xff) == num
;
616 fits_in_unsigned_word (num
)
619 return (num
& 0xffff) == num
;
623 fits_in_signed_word (num
)
626 return (-32768 <= num
) && (num
<= 32767);
629 fits_in_signed_long (num
)
630 offsetT num ATTRIBUTE_UNUSED
;
635 return (!(((offsetT
) -1 << 31) & num
)
636 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
638 } /* fits_in_signed_long() */
640 fits_in_unsigned_long (num
)
641 offsetT num ATTRIBUTE_UNUSED
;
646 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
648 } /* fits_in_unsigned_long() */
651 smallest_imm_type (num
)
654 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
656 /* This code is disabled on the 486 because all the Imm1 forms
657 in the opcode table are slower on the i486. They're the
658 versions with the implicitly specified single-position
659 displacement, which has another syntax if you really want to
662 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
664 return (fits_in_signed_byte (num
)
665 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
666 : fits_in_unsigned_byte (num
)
667 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
668 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
669 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
670 : fits_in_signed_long (num
)
671 ? (Imm32
| Imm32S
| Imm64
)
672 : fits_in_unsigned_long (num
)
678 offset_in_range (val
, size
)
686 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
687 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
688 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
690 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
695 /* If BFD64, sign extend val. */
696 if (!use_rela_relocations
)
697 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
698 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
700 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
702 char buf1
[40], buf2
[40];
704 sprint_value (buf1
, val
);
705 sprint_value (buf2
, val
& mask
);
706 as_warn (_("%s shortened to %s"), buf1
, buf2
);
711 /* Returns 0 if attempting to add a prefix where one from the same
712 class already exists, 1 if non rep/repne added, 2 if rep/repne
721 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
722 && flag_code
== CODE_64BIT
)
730 case CS_PREFIX_OPCODE
:
731 case DS_PREFIX_OPCODE
:
732 case ES_PREFIX_OPCODE
:
733 case FS_PREFIX_OPCODE
:
734 case GS_PREFIX_OPCODE
:
735 case SS_PREFIX_OPCODE
:
739 case REPNE_PREFIX_OPCODE
:
740 case REPE_PREFIX_OPCODE
:
743 case LOCK_PREFIX_OPCODE
:
751 case ADDR_PREFIX_OPCODE
:
755 case DATA_PREFIX_OPCODE
:
760 if (i
.prefix
[q
] != 0)
762 as_bad (_("same type of prefix used twice"));
767 i
.prefix
[q
] = prefix
;
772 set_code_flag (value
)
776 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
777 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
778 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
780 as_bad (_("64bit mode not supported on this CPU."));
782 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
784 as_bad (_("32bit mode not supported on this CPU."));
790 set_16bit_gcc_code_flag (new_code_flag
)
793 flag_code
= new_code_flag
;
794 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
795 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
796 stackop_size
= LONG_MNEM_SUFFIX
;
800 set_intel_syntax (syntax_flag
)
803 /* Find out if register prefixing is specified. */
804 int ask_naked_reg
= 0;
807 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
809 char *string
= input_line_pointer
;
810 int e
= get_symbol_end ();
812 if (strcmp (string
, "prefix") == 0)
814 else if (strcmp (string
, "noprefix") == 0)
817 as_bad (_("bad argument to syntax directive."));
818 *input_line_pointer
= e
;
820 demand_empty_rest_of_line ();
822 intel_syntax
= syntax_flag
;
824 if (ask_naked_reg
== 0)
825 allow_naked_reg
= (intel_syntax
826 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
828 allow_naked_reg
= (ask_naked_reg
< 0);
830 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
831 identifier_chars
['$'] = intel_syntax
? '$' : 0;
836 int dummy ATTRIBUTE_UNUSED
;
840 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
842 char *string
= input_line_pointer
;
843 int e
= get_symbol_end ();
846 for (i
= 0; cpu_arch
[i
].name
; i
++)
848 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
852 cpu_arch_name
= cpu_arch
[i
].name
;
853 cpu_sub_arch_name
= NULL
;
854 cpu_arch_flags
= (cpu_arch
[i
].flags
855 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
858 if ((cpu_arch_flags
| cpu_arch
[i
].flags
) != cpu_arch_flags
)
860 cpu_sub_arch_name
= cpu_arch
[i
].name
;
861 cpu_arch_flags
|= cpu_arch
[i
].flags
;
863 *input_line_pointer
= e
;
864 demand_empty_rest_of_line ();
868 if (!cpu_arch
[i
].name
)
869 as_bad (_("no such architecture: `%s'"), string
);
871 *input_line_pointer
= e
;
874 as_bad (_("missing cpu architecture"));
876 no_cond_jump_promotion
= 0;
877 if (*input_line_pointer
== ','
878 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
880 char *string
= ++input_line_pointer
;
881 int e
= get_symbol_end ();
883 if (strcmp (string
, "nojumps") == 0)
884 no_cond_jump_promotion
= 1;
885 else if (strcmp (string
, "jumps") == 0)
888 as_bad (_("no such architecture modifier: `%s'"), string
);
890 *input_line_pointer
= e
;
893 demand_empty_rest_of_line ();
899 if (!strcmp (default_arch
, "x86_64"))
900 return bfd_mach_x86_64
;
901 else if (!strcmp (default_arch
, "i386"))
902 return bfd_mach_i386_i386
;
904 as_fatal (_("Unknown architecture"));
910 const char *hash_err
;
912 /* Initialize op_hash hash table. */
913 op_hash
= hash_new ();
916 const template *optab
;
917 templates
*core_optab
;
919 /* Setup for loop. */
921 core_optab
= (templates
*) xmalloc (sizeof (templates
));
922 core_optab
->start
= optab
;
927 if (optab
->name
== NULL
928 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
930 /* different name --> ship out current template list;
931 add to hash table; & begin anew. */
932 core_optab
->end
= optab
;
933 hash_err
= hash_insert (op_hash
,
938 as_fatal (_("Internal Error: Can't hash %s: %s"),
942 if (optab
->name
== NULL
)
944 core_optab
= (templates
*) xmalloc (sizeof (templates
));
945 core_optab
->start
= optab
;
950 /* Initialize reg_hash hash table. */
951 reg_hash
= hash_new ();
953 const reg_entry
*regtab
;
955 for (regtab
= i386_regtab
;
956 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
959 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
961 as_fatal (_("Internal Error: Can't hash %s: %s"),
967 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
972 for (c
= 0; c
< 256; c
++)
977 mnemonic_chars
[c
] = c
;
978 register_chars
[c
] = c
;
979 operand_chars
[c
] = c
;
981 else if (ISLOWER (c
))
983 mnemonic_chars
[c
] = c
;
984 register_chars
[c
] = c
;
985 operand_chars
[c
] = c
;
987 else if (ISUPPER (c
))
989 mnemonic_chars
[c
] = TOLOWER (c
);
990 register_chars
[c
] = mnemonic_chars
[c
];
991 operand_chars
[c
] = c
;
994 if (ISALPHA (c
) || ISDIGIT (c
))
995 identifier_chars
[c
] = c
;
998 identifier_chars
[c
] = c
;
999 operand_chars
[c
] = c
;
1004 identifier_chars
['@'] = '@';
1007 identifier_chars
['?'] = '?';
1008 operand_chars
['?'] = '?';
1010 digit_chars
['-'] = '-';
1011 mnemonic_chars
['-'] = '-';
1012 identifier_chars
['_'] = '_';
1013 identifier_chars
['.'] = '.';
1015 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1016 operand_chars
[(unsigned char) *p
] = *p
;
1019 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1020 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1022 record_alignment (text_section
, 2);
1023 record_alignment (data_section
, 2);
1024 record_alignment (bss_section
, 2);
1028 if (flag_code
== CODE_64BIT
)
1030 x86_dwarf2_return_column
= 16;
1031 x86_cie_data_alignment
= -8;
1035 x86_dwarf2_return_column
= 8;
1036 x86_cie_data_alignment
= -4;
1041 i386_print_statistics (file
)
1044 hash_print_statistics (file
, "i386 opcode", op_hash
);
1045 hash_print_statistics (file
, "i386 register", reg_hash
);
1050 /* Debugging routines for md_assemble. */
1051 static void pi
PARAMS ((char *, i386_insn
*));
1052 static void pte
PARAMS ((template *));
1053 static void pt
PARAMS ((unsigned int));
1054 static void pe
PARAMS ((expressionS
*));
1055 static void ps
PARAMS ((symbolS
*));
1064 fprintf (stdout
, "%s: template ", line
);
1066 fprintf (stdout
, " address: base %s index %s scale %x\n",
1067 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1068 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1069 x
->log2_scale_factor
);
1070 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1071 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1072 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1073 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1074 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1075 (x
->rex
& REX_MODE64
) != 0,
1076 (x
->rex
& REX_EXTX
) != 0,
1077 (x
->rex
& REX_EXTY
) != 0,
1078 (x
->rex
& REX_EXTZ
) != 0);
1079 for (i
= 0; i
< x
->operands
; i
++)
1081 fprintf (stdout
, " #%d: ", i
+ 1);
1083 fprintf (stdout
, "\n");
1085 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1086 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1087 if (x
->types
[i
] & Imm
)
1089 if (x
->types
[i
] & Disp
)
1090 pe (x
->op
[i
].disps
);
1099 fprintf (stdout
, " %d operands ", t
->operands
);
1100 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1101 if (t
->extension_opcode
!= None
)
1102 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1103 if (t
->opcode_modifier
& D
)
1104 fprintf (stdout
, "D");
1105 if (t
->opcode_modifier
& W
)
1106 fprintf (stdout
, "W");
1107 fprintf (stdout
, "\n");
1108 for (i
= 0; i
< t
->operands
; i
++)
1110 fprintf (stdout
, " #%d type ", i
+ 1);
1111 pt (t
->operand_types
[i
]);
1112 fprintf (stdout
, "\n");
1120 fprintf (stdout
, " operation %d\n", e
->X_op
);
1121 fprintf (stdout
, " add_number %ld (%lx)\n",
1122 (long) e
->X_add_number
, (long) e
->X_add_number
);
1123 if (e
->X_add_symbol
)
1125 fprintf (stdout
, " add_symbol ");
1126 ps (e
->X_add_symbol
);
1127 fprintf (stdout
, "\n");
1131 fprintf (stdout
, " op_symbol ");
1132 ps (e
->X_op_symbol
);
1133 fprintf (stdout
, "\n");
1141 fprintf (stdout
, "%s type %s%s",
1143 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1144 segment_name (S_GET_SEGMENT (s
)));
1153 static const type_names
[] =
1166 { BaseIndex
, "BaseIndex" },
1170 { Disp32S
, "d32s" },
1172 { InOutPortReg
, "InOutPortReg" },
1173 { ShiftCount
, "ShiftCount" },
1174 { Control
, "control reg" },
1175 { Test
, "test reg" },
1176 { Debug
, "debug reg" },
1177 { FloatReg
, "FReg" },
1178 { FloatAcc
, "FAcc" },
1182 { JumpAbsolute
, "Jump Absolute" },
1193 const struct type_name
*ty
;
1195 for (ty
= type_names
; ty
->mask
; ty
++)
1197 fprintf (stdout
, "%s, ", ty
->tname
);
1201 #endif /* DEBUG386 */
1203 static bfd_reloc_code_real_type reloc
1204 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
1206 static bfd_reloc_code_real_type
1207 reloc (size
, pcrel
, sign
, other
)
1211 bfd_reloc_code_real_type other
;
1213 if (other
!= NO_RELOC
)
1219 as_bad (_("There are no unsigned pc-relative relocations"));
1222 case 1: return BFD_RELOC_8_PCREL
;
1223 case 2: return BFD_RELOC_16_PCREL
;
1224 case 4: return BFD_RELOC_32_PCREL
;
1225 case 8: return BFD_RELOC_64_PCREL
;
1227 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1234 case 4: return BFD_RELOC_X86_64_32S
;
1239 case 1: return BFD_RELOC_8
;
1240 case 2: return BFD_RELOC_16
;
1241 case 4: return BFD_RELOC_32
;
1242 case 8: return BFD_RELOC_64
;
1244 as_bad (_("can not do %s %d byte relocation"),
1245 sign
? "signed" : "unsigned", size
);
1249 return BFD_RELOC_NONE
;
1252 /* Here we decide which fixups can be adjusted to make them relative to
1253 the beginning of the section instead of the symbol. Basically we need
1254 to make sure that the dynamic relocations are done correctly, so in
1255 some cases we force the original symbol to be used. */
1258 tc_i386_fix_adjustable (fixP
)
1259 fixS
*fixP ATTRIBUTE_UNUSED
;
1261 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1262 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
1265 /* Don't adjust pc-relative references to merge sections in 64-bit
1267 if (use_rela_relocations
1268 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1272 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1273 and changed later by validate_fix. */
1274 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
1275 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
1278 /* adjust_reloc_syms doesn't know about the GOT. */
1279 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1280 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1281 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1282 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1283 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1284 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1285 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1286 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1287 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1288 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1289 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1290 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1291 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1292 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1293 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1294 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1295 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1296 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
1297 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1298 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1299 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
1300 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
1301 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1302 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1308 static int intel_float_operand
PARAMS ((const char *mnemonic
));
1311 intel_float_operand (mnemonic
)
1312 const char *mnemonic
;
1314 /* Note that the value returned is meaningful only for opcodes with (memory)
1315 operands, hence the code here is free to improperly handle opcodes that
1316 have no operands (for better performance and smaller code). */
1318 if (mnemonic
[0] != 'f')
1319 return 0; /* non-math */
1321 switch (mnemonic
[1])
1323 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1324 the fs segment override prefix not currently handled because no
1325 call path can make opcodes without operands get here */
1327 return 2 /* integer op */;
1329 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
1330 return 3; /* fldcw/fldenv */
1333 if (mnemonic
[2] != 'o' /* fnop */)
1334 return 3; /* non-waiting control op */
1337 if (mnemonic
[2] == 's')
1338 return 3; /* frstor/frstpm */
1341 if (mnemonic
[2] == 'a')
1342 return 3; /* fsave */
1343 if (mnemonic
[2] == 't')
1345 switch (mnemonic
[3])
1347 case 'c': /* fstcw */
1348 case 'd': /* fstdw */
1349 case 'e': /* fstenv */
1350 case 's': /* fsts[gw] */
1356 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
1357 return 0; /* fxsave/fxrstor are not really math ops */
1364 /* This is the guts of the machine-dependent assembler. LINE points to a
1365 machine dependent instruction. This function is supposed to emit
1366 the frags/bytes it assembles to. */
1373 char mnemonic
[MAX_MNEM_SIZE
];
1375 /* Initialize globals. */
1376 memset (&i
, '\0', sizeof (i
));
1377 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1378 i
.reloc
[j
] = NO_RELOC
;
1379 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1380 memset (im_expressions
, '\0', sizeof (im_expressions
));
1381 save_stack_p
= save_stack
;
1383 /* First parse an instruction mnemonic & call i386_operand for the operands.
1384 We assume that the scrubber has arranged it so that line[0] is the valid
1385 start of a (possibly prefixed) mnemonic. */
1387 line
= parse_insn (line
, mnemonic
);
1391 line
= parse_operands (line
, mnemonic
);
1395 /* Now we've parsed the mnemonic into a set of templates, and have the
1396 operands at hand. */
1398 /* All intel opcodes have reversed operands except for "bound" and
1399 "enter". We also don't reverse intersegment "jmp" and "call"
1400 instructions with 2 immediate operands so that the immediate segment
1401 precedes the offset, as it does when in AT&T mode. "enter" and the
1402 intersegment "jmp" and "call" instructions are the only ones that
1403 have two immediate operands. */
1404 if (intel_syntax
&& i
.operands
> 1
1405 && (strcmp (mnemonic
, "bound") != 0)
1406 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1412 /* Don't optimize displacement for movabs since it only takes 64bit
1415 && (flag_code
!= CODE_64BIT
1416 || strcmp (mnemonic
, "movabs") != 0))
1419 /* Next, we find a template that matches the given insn,
1420 making sure the overlap of the given operands types is consistent
1421 with the template operand types. */
1423 if (!match_template ())
1428 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1430 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1431 i
.tm
.base_opcode
^= FloatR
;
1433 /* Zap movzx and movsx suffix. The suffix may have been set from
1434 "word ptr" or "byte ptr" on the source operand, but we'll use
1435 the suffix later to choose the destination register. */
1436 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1438 if (i
.reg_operands
< 2
1440 && (~i
.tm
.opcode_modifier
1447 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
1453 if (i
.tm
.opcode_modifier
& FWait
)
1454 if (!add_prefix (FWAIT_OPCODE
))
1457 /* Check string instruction segment overrides. */
1458 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1460 if (!check_string ())
1464 if (!process_suffix ())
1467 /* Make still unresolved immediate matches conform to size of immediate
1468 given in i.suffix. */
1469 if (!finalize_imm ())
1472 if (i
.types
[0] & Imm1
)
1473 i
.imm_operands
= 0; /* kludge for shift insns. */
1474 if (i
.types
[0] & ImplicitRegister
)
1476 if (i
.types
[1] & ImplicitRegister
)
1478 if (i
.types
[2] & ImplicitRegister
)
1481 if (i
.tm
.opcode_modifier
& ImmExt
)
1485 if ((i
.tm
.cpu_flags
& CpuPNI
) && i
.operands
> 0)
1487 /* These Intel Prescott New Instructions have the fixed
1488 operands with an opcode suffix which is coded in the same
1489 place as an 8-bit immediate field would be. Here we check
1490 those operands and remove them afterwards. */
1493 for (x
= 0; x
< i
.operands
; x
++)
1494 if (i
.op
[x
].regs
->reg_num
!= x
)
1495 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1496 i
.op
[x
].regs
->reg_name
, x
+ 1, i
.tm
.name
);
1500 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1501 opcode suffix which is coded in the same place as an 8-bit
1502 immediate field would be. Here we fake an 8-bit immediate
1503 operand from the opcode suffix stored in tm.extension_opcode. */
1505 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1507 exp
= &im_expressions
[i
.imm_operands
++];
1508 i
.op
[i
.operands
].imms
= exp
;
1509 i
.types
[i
.operands
++] = Imm8
;
1510 exp
->X_op
= O_constant
;
1511 exp
->X_add_number
= i
.tm
.extension_opcode
;
1512 i
.tm
.extension_opcode
= None
;
1515 /* For insns with operands there are more diddles to do to the opcode. */
1518 if (!process_operands ())
1521 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1523 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1524 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1527 /* Handle conversion of 'int $3' --> special int3 insn. */
1528 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1530 i
.tm
.base_opcode
= INT3_OPCODE
;
1534 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1535 && i
.op
[0].disps
->X_op
== O_constant
)
1537 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1538 the absolute address given by the constant. Since ix86 jumps and
1539 calls are pc relative, we need to generate a reloc. */
1540 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1541 i
.op
[0].disps
->X_op
= O_symbol
;
1544 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1545 i
.rex
|= REX_MODE64
;
1547 /* For 8 bit registers we need an empty rex prefix. Also if the
1548 instruction already has a prefix, we need to convert old
1549 registers to new ones. */
1551 if (((i
.types
[0] & Reg8
) != 0
1552 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1553 || ((i
.types
[1] & Reg8
) != 0
1554 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1555 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1560 i
.rex
|= REX_OPCODE
;
1561 for (x
= 0; x
< 2; x
++)
1563 /* Look for 8 bit operand that uses old registers. */
1564 if ((i
.types
[x
] & Reg8
) != 0
1565 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1567 /* In case it is "hi" register, give up. */
1568 if (i
.op
[x
].regs
->reg_num
> 3)
1569 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1570 i
.op
[x
].regs
->reg_name
);
1572 /* Otherwise it is equivalent to the extended register.
1573 Since the encoding doesn't change this is merely
1574 cosmetic cleanup for debug output. */
1576 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1582 add_prefix (REX_OPCODE
| i
.rex
);
1584 /* We are ready to output the insn. */
1589 parse_insn (line
, mnemonic
)
1594 char *token_start
= l
;
1599 /* Non-zero if we found a prefix only acceptable with string insns. */
1600 const char *expecting_string_instruction
= NULL
;
1605 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1608 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1610 as_bad (_("no such instruction: `%s'"), token_start
);
1615 if (!is_space_char (*l
)
1616 && *l
!= END_OF_INSN
1618 || (*l
!= PREFIX_SEPARATOR
1621 as_bad (_("invalid character %s in mnemonic"),
1622 output_invalid (*l
));
1625 if (token_start
== l
)
1627 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
1628 as_bad (_("expecting prefix; got nothing"));
1630 as_bad (_("expecting mnemonic; got nothing"));
1634 /* Look up instruction (or prefix) via hash table. */
1635 current_templates
= hash_find (op_hash
, mnemonic
);
1637 if (*l
!= END_OF_INSN
1638 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1639 && current_templates
1640 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1642 /* If we are in 16-bit mode, do not allow addr16 or data16.
1643 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1644 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1645 && flag_code
!= CODE_64BIT
1646 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1647 ^ (flag_code
== CODE_16BIT
)))
1649 as_bad (_("redundant %s prefix"),
1650 current_templates
->start
->name
);
1653 /* Add prefix, checking for repeated prefixes. */
1654 switch (add_prefix (current_templates
->start
->base_opcode
))
1659 expecting_string_instruction
= current_templates
->start
->name
;
1662 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1669 if (!current_templates
)
1671 /* See if we can get a match by trimming off a suffix. */
1674 case WORD_MNEM_SUFFIX
:
1675 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
1676 i
.suffix
= SHORT_MNEM_SUFFIX
;
1678 case BYTE_MNEM_SUFFIX
:
1679 case QWORD_MNEM_SUFFIX
:
1680 i
.suffix
= mnem_p
[-1];
1682 current_templates
= hash_find (op_hash
, mnemonic
);
1684 case SHORT_MNEM_SUFFIX
:
1685 case LONG_MNEM_SUFFIX
:
1688 i
.suffix
= mnem_p
[-1];
1690 current_templates
= hash_find (op_hash
, mnemonic
);
1698 if (intel_float_operand (mnemonic
) == 1)
1699 i
.suffix
= SHORT_MNEM_SUFFIX
;
1701 i
.suffix
= LONG_MNEM_SUFFIX
;
1703 current_templates
= hash_find (op_hash
, mnemonic
);
1707 if (!current_templates
)
1709 as_bad (_("no such instruction: `%s'"), token_start
);
1714 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1716 /* Check for a branch hint. We allow ",pt" and ",pn" for
1717 predict taken and predict not taken respectively.
1718 I'm not sure that branch hints actually do anything on loop
1719 and jcxz insns (JumpByte) for current Pentium4 chips. They
1720 may work in the future and it doesn't hurt to accept them
1722 if (l
[0] == ',' && l
[1] == 'p')
1726 if (!add_prefix (DS_PREFIX_OPCODE
))
1730 else if (l
[2] == 'n')
1732 if (!add_prefix (CS_PREFIX_OPCODE
))
1738 /* Any other comma loses. */
1741 as_bad (_("invalid character %s in mnemonic"),
1742 output_invalid (*l
));
1746 /* Check if instruction is supported on specified architecture. */
1748 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
1750 if (!((t
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1751 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
))))
1753 if (!(t
->cpu_flags
& (flag_code
== CODE_64BIT
? CpuNo64
: Cpu64
)))
1756 if (!(supported
& 2))
1758 as_bad (flag_code
== CODE_64BIT
1759 ? _("`%s' is not supported in 64-bit mode")
1760 : _("`%s' is only supported in 64-bit mode"),
1761 current_templates
->start
->name
);
1764 if (!(supported
& 1))
1766 as_warn (_("`%s' is not supported on `%s%s'"),
1767 current_templates
->start
->name
,
1769 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
1771 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1773 as_warn (_("use .code16 to ensure correct addressing mode"));
1776 /* Check for rep/repne without a string instruction. */
1777 if (expecting_string_instruction
)
1779 static templates override
;
1781 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
1782 if (t
->opcode_modifier
& IsString
)
1784 if (t
>= current_templates
->end
)
1786 as_bad (_("expecting string instruction after `%s'"),
1787 expecting_string_instruction
);
1790 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
1791 if (!(t
->opcode_modifier
& IsString
))
1794 current_templates
= &override
;
1801 parse_operands (l
, mnemonic
)
1803 const char *mnemonic
;
1807 /* 1 if operand is pending after ','. */
1808 unsigned int expecting_operand
= 0;
1810 /* Non-zero if operand parens not balanced. */
1811 unsigned int paren_not_balanced
;
1813 while (*l
!= END_OF_INSN
)
1815 /* Skip optional white space before operand. */
1816 if (is_space_char (*l
))
1818 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1820 as_bad (_("invalid character %s before operand %d"),
1821 output_invalid (*l
),
1825 token_start
= l
; /* after white space */
1826 paren_not_balanced
= 0;
1827 while (paren_not_balanced
|| *l
!= ',')
1829 if (*l
== END_OF_INSN
)
1831 if (paren_not_balanced
)
1834 as_bad (_("unbalanced parenthesis in operand %d."),
1837 as_bad (_("unbalanced brackets in operand %d."),
1842 break; /* we are done */
1844 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1846 as_bad (_("invalid character %s in operand %d"),
1847 output_invalid (*l
),
1854 ++paren_not_balanced
;
1856 --paren_not_balanced
;
1861 ++paren_not_balanced
;
1863 --paren_not_balanced
;
1867 if (l
!= token_start
)
1868 { /* Yes, we've read in another operand. */
1869 unsigned int operand_ok
;
1870 this_operand
= i
.operands
++;
1871 if (i
.operands
> MAX_OPERANDS
)
1873 as_bad (_("spurious operands; (%d operands/instruction max)"),
1877 /* Now parse operand adding info to 'i' as we go along. */
1878 END_STRING_AND_SAVE (l
);
1882 i386_intel_operand (token_start
,
1883 intel_float_operand (mnemonic
));
1885 operand_ok
= i386_operand (token_start
);
1887 RESTORE_END_STRING (l
);
1893 if (expecting_operand
)
1895 expecting_operand_after_comma
:
1896 as_bad (_("expecting operand after ','; got nothing"));
1901 as_bad (_("expecting operand before ','; got nothing"));
1906 /* Now *l must be either ',' or END_OF_INSN. */
1909 if (*++l
== END_OF_INSN
)
1911 /* Just skip it, if it's \n complain. */
1912 goto expecting_operand_after_comma
;
1914 expecting_operand
= 1;
1923 union i386_op temp_op
;
1924 unsigned int temp_type
;
1925 enum bfd_reloc_code_real temp_reloc
;
1929 if (i
.operands
== 2)
1934 else if (i
.operands
== 3)
1939 temp_type
= i
.types
[xchg2
];
1940 i
.types
[xchg2
] = i
.types
[xchg1
];
1941 i
.types
[xchg1
] = temp_type
;
1942 temp_op
= i
.op
[xchg2
];
1943 i
.op
[xchg2
] = i
.op
[xchg1
];
1944 i
.op
[xchg1
] = temp_op
;
1945 temp_reloc
= i
.reloc
[xchg2
];
1946 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1947 i
.reloc
[xchg1
] = temp_reloc
;
1949 if (i
.mem_operands
== 2)
1951 const seg_entry
*temp_seg
;
1952 temp_seg
= i
.seg
[0];
1953 i
.seg
[0] = i
.seg
[1];
1954 i
.seg
[1] = temp_seg
;
1958 /* Try to ensure constant immediates are represented in the smallest
1963 char guess_suffix
= 0;
1967 guess_suffix
= i
.suffix
;
1968 else if (i
.reg_operands
)
1970 /* Figure out a suffix from the last register operand specified.
1971 We can't do this properly yet, ie. excluding InOutPortReg,
1972 but the following works for instructions with immediates.
1973 In any case, we can't set i.suffix yet. */
1974 for (op
= i
.operands
; --op
>= 0;)
1975 if (i
.types
[op
] & Reg
)
1977 if (i
.types
[op
] & Reg8
)
1978 guess_suffix
= BYTE_MNEM_SUFFIX
;
1979 else if (i
.types
[op
] & Reg16
)
1980 guess_suffix
= WORD_MNEM_SUFFIX
;
1981 else if (i
.types
[op
] & Reg32
)
1982 guess_suffix
= LONG_MNEM_SUFFIX
;
1983 else if (i
.types
[op
] & Reg64
)
1984 guess_suffix
= QWORD_MNEM_SUFFIX
;
1988 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1989 guess_suffix
= WORD_MNEM_SUFFIX
;
1991 for (op
= i
.operands
; --op
>= 0;)
1992 if (i
.types
[op
] & Imm
)
1994 switch (i
.op
[op
].imms
->X_op
)
1997 /* If a suffix is given, this operand may be shortened. */
1998 switch (guess_suffix
)
2000 case LONG_MNEM_SUFFIX
:
2001 i
.types
[op
] |= Imm32
| Imm64
;
2003 case WORD_MNEM_SUFFIX
:
2004 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
2006 case BYTE_MNEM_SUFFIX
:
2007 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
2011 /* If this operand is at most 16 bits, convert it
2012 to a signed 16 bit number before trying to see
2013 whether it will fit in an even smaller size.
2014 This allows a 16-bit operand such as $0xffe0 to
2015 be recognised as within Imm8S range. */
2016 if ((i
.types
[op
] & Imm16
)
2017 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
2019 i
.op
[op
].imms
->X_add_number
=
2020 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2022 if ((i
.types
[op
] & Imm32
)
2023 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2026 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2027 ^ ((offsetT
) 1 << 31))
2028 - ((offsetT
) 1 << 31));
2030 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
2032 /* We must avoid matching of Imm32 templates when 64bit
2033 only immediate is available. */
2034 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2035 i
.types
[op
] &= ~Imm32
;
2042 /* Symbols and expressions. */
2044 /* Convert symbolic operand to proper sizes for matching. */
2045 switch (guess_suffix
)
2047 case QWORD_MNEM_SUFFIX
:
2048 i
.types
[op
] = Imm64
| Imm32S
;
2050 case LONG_MNEM_SUFFIX
:
2051 i
.types
[op
] = Imm32
;
2053 case WORD_MNEM_SUFFIX
:
2054 i
.types
[op
] = Imm16
;
2056 case BYTE_MNEM_SUFFIX
:
2057 i
.types
[op
] = Imm8
| Imm8S
;
2065 /* Try to use the smallest displacement type too. */
2071 for (op
= i
.operands
; --op
>= 0;)
2072 if (i
.types
[op
] & Disp
)
2074 if (i
.op
[op
].disps
->X_op
== O_constant
)
2076 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
2078 if ((i
.types
[op
] & Disp16
)
2079 && (disp
& ~(offsetT
) 0xffff) == 0)
2081 /* If this operand is at most 16 bits, convert
2082 to a signed 16 bit number and don't use 64bit
2084 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
2085 i
.types
[op
] &= ~Disp64
;
2087 if ((i
.types
[op
] & Disp32
)
2088 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
2090 /* If this operand is at most 32 bits, convert
2091 to a signed 32 bit number and don't use 64bit
2093 disp
&= (((offsetT
) 2 << 31) - 1);
2094 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
2095 i
.types
[op
] &= ~Disp64
;
2097 if (!disp
&& (i
.types
[op
] & BaseIndex
))
2099 i
.types
[op
] &= ~Disp
;
2103 else if (flag_code
== CODE_64BIT
)
2105 if (fits_in_signed_long (disp
))
2106 i
.types
[op
] |= Disp32S
;
2107 if (fits_in_unsigned_long (disp
))
2108 i
.types
[op
] |= Disp32
;
2110 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
2111 && fits_in_signed_byte (disp
))
2112 i
.types
[op
] |= Disp8
;
2115 /* We only support 64bit displacement on constants. */
2116 i
.types
[op
] &= ~Disp64
;
2123 /* Points to template once we've found it. */
2125 unsigned int overlap0
, overlap1
, overlap2
;
2126 unsigned int found_reverse_match
;
2129 #define MATCH(overlap, given, template) \
2130 ((overlap & ~JumpAbsolute) \
2131 && (((given) & (BaseIndex | JumpAbsolute)) \
2132 == ((overlap) & (BaseIndex | JumpAbsolute))))
2134 /* If given types r0 and r1 are registers they must be of the same type
2135 unless the expected operand type register overlap is null.
2136 Note that Acc in a template matches every size of reg. */
2137 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2138 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2139 || ((g0) & Reg) == ((g1) & Reg) \
2140 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2145 found_reverse_match
= 0;
2146 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
2148 : (i
.suffix
== WORD_MNEM_SUFFIX
2150 : (i
.suffix
== SHORT_MNEM_SUFFIX
2152 : (i
.suffix
== LONG_MNEM_SUFFIX
2154 : (i
.suffix
== QWORD_MNEM_SUFFIX
2156 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
2157 ? No_xSuf
: 0))))));
2159 t
= current_templates
->start
;
2160 if (i
.suffix
== QWORD_MNEM_SUFFIX
2161 && flag_code
!= CODE_64BIT
2163 ? !(t
->opcode_modifier
& IgnoreSize
)
2164 && !intel_float_operand (t
->name
)
2165 : intel_float_operand (t
->name
) != 2)
2166 && (!(t
->operand_types
[0] & (RegMMX
| RegXMM
))
2167 || !(t
->operand_types
[t
->operands
> 1] & (RegMMX
| RegXMM
)))
2168 && (t
->base_opcode
!= 0x0fc7
2169 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
2170 t
= current_templates
->end
;
2171 for (; t
< current_templates
->end
; t
++)
2173 /* Must have right number of operands. */
2174 if (i
.operands
!= t
->operands
)
2177 /* Check the suffix, except for some instructions in intel mode. */
2178 if ((t
->opcode_modifier
& suffix_check
)
2180 && (t
->opcode_modifier
& IgnoreSize
)))
2183 /* Do not verify operands when there are none. */
2184 else if (!t
->operands
)
2186 if (t
->cpu_flags
& ~cpu_arch_flags
)
2188 /* We've found a match; break out of loop. */
2192 overlap0
= i
.types
[0] & t
->operand_types
[0];
2193 switch (t
->operands
)
2196 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
2201 overlap1
= i
.types
[1] & t
->operand_types
[1];
2202 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
2203 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
2204 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2205 t
->operand_types
[0],
2206 overlap1
, i
.types
[1],
2207 t
->operand_types
[1]))
2209 /* Check if other direction is valid ... */
2210 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2213 /* Try reversing direction of operands. */
2214 overlap0
= i
.types
[0] & t
->operand_types
[1];
2215 overlap1
= i
.types
[1] & t
->operand_types
[0];
2216 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
2217 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
2218 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2219 t
->operand_types
[1],
2220 overlap1
, i
.types
[1],
2221 t
->operand_types
[0]))
2223 /* Does not match either direction. */
2226 /* found_reverse_match holds which of D or FloatDR
2228 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2230 /* Found a forward 2 operand match here. */
2231 else if (t
->operands
== 3)
2233 /* Here we make use of the fact that there are no
2234 reverse match 3 operand instructions, and all 3
2235 operand instructions only need to be checked for
2236 register consistency between operands 2 and 3. */
2237 overlap2
= i
.types
[2] & t
->operand_types
[2];
2238 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
2239 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
2240 t
->operand_types
[1],
2241 overlap2
, i
.types
[2],
2242 t
->operand_types
[2]))
2246 /* Found either forward/reverse 2 or 3 operand match here:
2247 slip through to break. */
2249 if (t
->cpu_flags
& ~cpu_arch_flags
)
2251 found_reverse_match
= 0;
2254 /* We've found a match; break out of loop. */
2258 if (t
== current_templates
->end
)
2260 /* We found no match. */
2261 as_bad (_("suffix or operands invalid for `%s'"),
2262 current_templates
->start
->name
);
2266 if (!quiet_warnings
)
2269 && ((i
.types
[0] & JumpAbsolute
)
2270 != (t
->operand_types
[0] & JumpAbsolute
)))
2272 as_warn (_("indirect %s without `*'"), t
->name
);
2275 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2276 == (IsPrefix
| IgnoreSize
))
2278 /* Warn them that a data or address size prefix doesn't
2279 affect assembly of the next line of code. */
2280 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2284 /* Copy the template we found. */
2286 if (found_reverse_match
)
2288 /* If we found a reverse match we must alter the opcode
2289 direction bit. found_reverse_match holds bits to change
2290 (different for int & float insns). */
2292 i
.tm
.base_opcode
^= found_reverse_match
;
2294 i
.tm
.operand_types
[0] = t
->operand_types
[1];
2295 i
.tm
.operand_types
[1] = t
->operand_types
[0];
2304 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2305 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2307 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2309 as_bad (_("`%s' operand %d must use `%%es' segment"),
2314 /* There's only ever one segment override allowed per instruction.
2315 This instruction possibly has a legal segment override on the
2316 second operand, so copy the segment to where non-string
2317 instructions store it, allowing common code. */
2318 i
.seg
[0] = i
.seg
[1];
2320 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2322 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2324 as_bad (_("`%s' operand %d must use `%%es' segment"),
2334 process_suffix (void)
2336 /* If matched instruction specifies an explicit instruction mnemonic
2338 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2340 if (i
.tm
.opcode_modifier
& Size16
)
2341 i
.suffix
= WORD_MNEM_SUFFIX
;
2342 else if (i
.tm
.opcode_modifier
& Size64
)
2343 i
.suffix
= QWORD_MNEM_SUFFIX
;
2345 i
.suffix
= LONG_MNEM_SUFFIX
;
2347 else if (i
.reg_operands
)
2349 /* If there's no instruction mnemonic suffix we try to invent one
2350 based on register operands. */
2353 /* We take i.suffix from the last register operand specified,
2354 Destination register type is more significant than source
2358 for (op
= i
.operands
; --op
>= 0;)
2359 if ((i
.types
[op
] & Reg
)
2360 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2362 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2363 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2364 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2369 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2371 if (!check_byte_reg ())
2374 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2376 if (!check_long_reg ())
2379 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2381 if (!check_qword_reg ())
2384 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2386 if (!check_word_reg ())
2389 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2390 /* Do nothing if the instruction is going to ignore the prefix. */
2395 else if ((i
.tm
.opcode_modifier
& DefaultSize
)
2397 /* exclude fldenv/frstor/fsave/fstenv */
2398 && (i
.tm
.opcode_modifier
& No_sSuf
))
2400 i
.suffix
= stackop_size
;
2402 else if (intel_syntax
2404 && ((i
.tm
.operand_types
[0] & JumpAbsolute
)
2405 || (i
.tm
.opcode_modifier
& (JumpByte
|JumpInterSegment
))
2406 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
2407 && i
.tm
.extension_opcode
<= 3)))
2412 if (!(i
.tm
.opcode_modifier
& No_qSuf
))
2414 i
.suffix
= QWORD_MNEM_SUFFIX
;
2418 if (!(i
.tm
.opcode_modifier
& No_lSuf
))
2419 i
.suffix
= LONG_MNEM_SUFFIX
;
2422 if (!(i
.tm
.opcode_modifier
& No_wSuf
))
2423 i
.suffix
= WORD_MNEM_SUFFIX
;
2432 if (i
.tm
.opcode_modifier
& W
)
2434 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2440 unsigned int suffixes
= ~i
.tm
.opcode_modifier
2448 if ((i
.tm
.opcode_modifier
& W
)
2449 || ((suffixes
& (suffixes
- 1))
2450 && !(i
.tm
.opcode_modifier
& (DefaultSize
| IgnoreSize
))))
2452 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2458 /* Change the opcode based on the operand size given by i.suffix;
2459 We don't need to change things for byte insns. */
2461 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2463 /* It's not a byte, select word/dword operation. */
2464 if (i
.tm
.opcode_modifier
& W
)
2466 if (i
.tm
.opcode_modifier
& ShortForm
)
2467 i
.tm
.base_opcode
|= 8;
2469 i
.tm
.base_opcode
|= 1;
2472 /* Now select between word & dword operations via the operand
2473 size prefix, except for instructions that will ignore this
2475 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2476 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
2477 && !(i
.tm
.opcode_modifier
& (IgnoreSize
| FloatMF
))
2478 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2479 || (flag_code
== CODE_64BIT
2480 && (i
.tm
.opcode_modifier
& JumpByte
))))
2482 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2484 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2485 prefix
= ADDR_PREFIX_OPCODE
;
2487 if (!add_prefix (prefix
))
2491 /* Set mode64 for an operand. */
2492 if (i
.suffix
== QWORD_MNEM_SUFFIX
2493 && flag_code
== CODE_64BIT
2494 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2495 i
.rex
|= REX_MODE64
;
2497 /* Size floating point instruction. */
2498 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2499 if (i
.tm
.opcode_modifier
& FloatMF
)
2500 i
.tm
.base_opcode
^= 4;
2507 check_byte_reg (void)
2511 for (op
= i
.operands
; --op
>= 0;)
2513 /* If this is an eight bit register, it's OK. If it's the 16 or
2514 32 bit version of an eight bit register, we will just use the
2515 low portion, and that's OK too. */
2516 if (i
.types
[op
] & Reg8
)
2519 /* movzx and movsx should not generate this warning. */
2521 && (i
.tm
.base_opcode
== 0xfb7
2522 || i
.tm
.base_opcode
== 0xfb6
2523 || i
.tm
.base_opcode
== 0x63
2524 || i
.tm
.base_opcode
== 0xfbe
2525 || i
.tm
.base_opcode
== 0xfbf))
2528 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4)
2530 /* Prohibit these changes in the 64bit mode, since the
2531 lowering is more complicated. */
2532 if (flag_code
== CODE_64BIT
2533 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2535 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2536 i
.op
[op
].regs
->reg_name
,
2540 #if REGISTER_WARNINGS
2542 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2543 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2544 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
2545 ? REGNAM_AL
- REGNAM_AX
2546 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2547 i
.op
[op
].regs
->reg_name
,
2552 /* Any other register is bad. */
2553 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2555 | Control
| Debug
| Test
2556 | FloatReg
| FloatAcc
))
2558 as_bad (_("`%%%s' not allowed with `%s%c'"),
2559 i
.op
[op
].regs
->reg_name
,
2573 for (op
= i
.operands
; --op
>= 0;)
2574 /* Reject eight bit registers, except where the template requires
2575 them. (eg. movzb) */
2576 if ((i
.types
[op
] & Reg8
) != 0
2577 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2579 as_bad (_("`%%%s' not allowed with `%s%c'"),
2580 i
.op
[op
].regs
->reg_name
,
2585 /* Warn if the e prefix on a general reg is missing. */
2586 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2587 && (i
.types
[op
] & Reg16
) != 0
2588 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2590 /* Prohibit these changes in the 64bit mode, since the
2591 lowering is more complicated. */
2592 if (flag_code
== CODE_64BIT
)
2594 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2595 i
.op
[op
].regs
->reg_name
,
2599 #if REGISTER_WARNINGS
2601 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2602 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2603 i
.op
[op
].regs
->reg_name
,
2607 /* Warn if the r prefix on a general reg is missing. */
2608 else if ((i
.types
[op
] & Reg64
) != 0
2609 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2611 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2612 i
.op
[op
].regs
->reg_name
,
2624 for (op
= i
.operands
; --op
>= 0; )
2625 /* Reject eight bit registers, except where the template requires
2626 them. (eg. movzb) */
2627 if ((i
.types
[op
] & Reg8
) != 0
2628 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2630 as_bad (_("`%%%s' not allowed with `%s%c'"),
2631 i
.op
[op
].regs
->reg_name
,
2636 /* Warn if the e prefix on a general reg is missing. */
2637 else if (((i
.types
[op
] & Reg16
) != 0
2638 || (i
.types
[op
] & Reg32
) != 0)
2639 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2641 /* Prohibit these changes in the 64bit mode, since the
2642 lowering is more complicated. */
2643 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2644 i
.op
[op
].regs
->reg_name
,
2655 for (op
= i
.operands
; --op
>= 0;)
2656 /* Reject eight bit registers, except where the template requires
2657 them. (eg. movzb) */
2658 if ((i
.types
[op
] & Reg8
) != 0
2659 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2661 as_bad (_("`%%%s' not allowed with `%s%c'"),
2662 i
.op
[op
].regs
->reg_name
,
2667 /* Warn if the e prefix on a general reg is present. */
2668 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2669 && (i
.types
[op
] & Reg32
) != 0
2670 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
2672 /* Prohibit these changes in the 64bit mode, since the
2673 lowering is more complicated. */
2674 if (flag_code
== CODE_64BIT
)
2676 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2677 i
.op
[op
].regs
->reg_name
,
2682 #if REGISTER_WARNINGS
2683 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2684 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2685 i
.op
[op
].regs
->reg_name
,
2695 unsigned int overlap0
, overlap1
, overlap2
;
2697 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
2698 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
))
2699 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2700 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2701 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2705 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2707 : (i
.suffix
== WORD_MNEM_SUFFIX
2709 : (i
.suffix
== QWORD_MNEM_SUFFIX
2713 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2714 || overlap0
== (Imm16
| Imm32
)
2715 || overlap0
== (Imm16
| Imm32S
))
2717 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2720 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2721 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2722 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2724 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2728 i
.types
[0] = overlap0
;
2730 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
2731 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
| Imm64
))
2732 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2733 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2734 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2738 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2740 : (i
.suffix
== WORD_MNEM_SUFFIX
2742 : (i
.suffix
== QWORD_MNEM_SUFFIX
2746 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2747 || overlap1
== (Imm16
| Imm32
)
2748 || overlap1
== (Imm16
| Imm32S
))
2750 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2753 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2754 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2755 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2757 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2761 i
.types
[1] = overlap1
;
2763 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
2764 assert ((overlap2
& Imm
) == 0);
2765 i
.types
[2] = overlap2
;
2773 /* Default segment register this instruction will use for memory
2774 accesses. 0 means unknown. This is only for optimizing out
2775 unnecessary segment overrides. */
2776 const seg_entry
*default_seg
= 0;
2778 /* The imul $imm, %reg instruction is converted into
2779 imul $imm, %reg, %reg, and the clr %reg instruction
2780 is converted into xor %reg, %reg. */
2781 if (i
.tm
.opcode_modifier
& regKludge
)
2783 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2784 /* Pretend we saw the extra register operand. */
2785 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2786 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2787 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2791 if (i
.tm
.opcode_modifier
& ShortForm
)
2793 /* The register or float register operand is in operand 0 or 1. */
2794 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2795 /* Register goes in low 3 bits of opcode. */
2796 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2797 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2799 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2801 /* Warn about some common errors, but press on regardless.
2802 The first case can be generated by gcc (<= 2.8.1). */
2803 if (i
.operands
== 2)
2805 /* Reversed arguments on faddp, fsubp, etc. */
2806 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2807 i
.op
[1].regs
->reg_name
,
2808 i
.op
[0].regs
->reg_name
);
2812 /* Extraneous `l' suffix on fp insn. */
2813 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2814 i
.op
[0].regs
->reg_name
);
2818 else if (i
.tm
.opcode_modifier
& Modrm
)
2820 /* The opcode is completed (modulo i.tm.extension_opcode which
2821 must be put into the modrm byte). Now, we make the modrm and
2822 index base bytes based on all the info we've collected. */
2824 default_seg
= build_modrm_byte ();
2826 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2828 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2829 && i
.op
[0].regs
->reg_num
== 1)
2831 as_bad (_("you can't `pop %%cs'"));
2834 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2835 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
2838 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
2842 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2844 /* For the string instructions that allow a segment override
2845 on one of their operands, the default segment is ds. */
2849 if (i
.tm
.base_opcode
== 0x8d /* lea */ && i
.seg
[0] && !quiet_warnings
)
2850 as_warn (_("segment override on `lea' is ineffectual"));
2852 /* If a segment was explicitly specified, and the specified segment
2853 is not the default, use an opcode prefix to select it. If we
2854 never figured out what the default segment is, then default_seg
2855 will be zero at this point, and the specified segment prefix will
2857 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2859 if (!add_prefix (i
.seg
[0]->seg_prefix
))
2865 static const seg_entry
*
2868 const seg_entry
*default_seg
= 0;
2870 /* i.reg_operands MUST be the number of real register operands;
2871 implicit registers do not count. */
2872 if (i
.reg_operands
== 2)
2874 unsigned int source
, dest
;
2875 source
= ((i
.types
[0]
2876 & (Reg
| RegMMX
| RegXMM
2878 | Control
| Debug
| Test
))
2883 /* One of the register operands will be encoded in the i.tm.reg
2884 field, the other in the combined i.tm.mode and i.tm.regmem
2885 fields. If no form of this instruction supports a memory
2886 destination operand, then we assume the source operand may
2887 sometimes be a memory operand and so we need to store the
2888 destination in the i.rm.reg field. */
2889 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2891 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2892 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2893 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2895 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2900 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2901 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2902 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2904 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2907 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_EXTX
| REX_EXTZ
)))
2909 if (!((i
.types
[0] | i
.types
[1]) & Control
))
2911 i
.rex
&= ~(REX_EXTX
| REX_EXTZ
);
2912 add_prefix (LOCK_PREFIX_OPCODE
);
2916 { /* If it's not 2 reg operands... */
2919 unsigned int fake_zero_displacement
= 0;
2920 unsigned int op
= ((i
.types
[0] & AnyMem
)
2922 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2926 if (i
.base_reg
== 0)
2929 if (!i
.disp_operands
)
2930 fake_zero_displacement
= 1;
2931 if (i
.index_reg
== 0)
2933 /* Operand is just <disp> */
2934 if (flag_code
== CODE_64BIT
)
2936 /* 64bit mode overwrites the 32bit absolute
2937 addressing by RIP relative addressing and
2938 absolute addressing is encoded by one of the
2939 redundant SIB forms. */
2940 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2941 i
.sib
.base
= NO_BASE_REGISTER
;
2942 i
.sib
.index
= NO_INDEX_REGISTER
;
2943 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0) ? Disp32S
: Disp32
);
2945 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2947 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2948 i
.types
[op
] = Disp16
;
2952 i
.rm
.regmem
= NO_BASE_REGISTER
;
2953 i
.types
[op
] = Disp32
;
2956 else /* !i.base_reg && i.index_reg */
2958 i
.sib
.index
= i
.index_reg
->reg_num
;
2959 i
.sib
.base
= NO_BASE_REGISTER
;
2960 i
.sib
.scale
= i
.log2_scale_factor
;
2961 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2962 i
.types
[op
] &= ~Disp
;
2963 if (flag_code
!= CODE_64BIT
)
2964 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2966 i
.types
[op
] |= Disp32S
;
2967 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2971 /* RIP addressing for 64bit mode. */
2972 else if (i
.base_reg
->reg_type
== BaseIndex
)
2974 i
.rm
.regmem
= NO_BASE_REGISTER
;
2975 i
.types
[op
] &= ~ Disp
;
2976 i
.types
[op
] |= Disp32S
;
2977 i
.flags
[op
] = Operand_PCrel
;
2978 if (! i
.disp_operands
)
2979 fake_zero_displacement
= 1;
2981 else if (i
.base_reg
->reg_type
& Reg16
)
2983 switch (i
.base_reg
->reg_num
)
2986 if (i
.index_reg
== 0)
2988 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2989 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2993 if (i
.index_reg
== 0)
2996 if ((i
.types
[op
] & Disp
) == 0)
2998 /* fake (%bp) into 0(%bp) */
2999 i
.types
[op
] |= Disp8
;
3000 fake_zero_displacement
= 1;
3003 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3004 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
3006 default: /* (%si) -> 4 or (%di) -> 5 */
3007 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
3009 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3011 else /* i.base_reg and 32/64 bit mode */
3013 if (flag_code
== CODE_64BIT
3014 && (i
.types
[op
] & Disp
))
3015 i
.types
[op
] = (i
.types
[op
] & Disp8
) | (i
.prefix
[ADDR_PREFIX
] == 0 ? Disp32S
: Disp32
);
3017 i
.rm
.regmem
= i
.base_reg
->reg_num
;
3018 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
3020 i
.sib
.base
= i
.base_reg
->reg_num
;
3021 /* x86-64 ignores REX prefix bit here to avoid decoder
3023 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
3026 if (i
.disp_operands
== 0)
3028 fake_zero_displacement
= 1;
3029 i
.types
[op
] |= Disp8
;
3032 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
3036 i
.sib
.scale
= i
.log2_scale_factor
;
3037 if (i
.index_reg
== 0)
3039 /* <disp>(%esp) becomes two byte modrm with no index
3040 register. We've already stored the code for esp
3041 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3042 Any base register besides %esp will not use the
3043 extra modrm byte. */
3044 i
.sib
.index
= NO_INDEX_REGISTER
;
3045 #if !SCALE1_WHEN_NO_INDEX
3046 /* Another case where we force the second modrm byte. */
3047 if (i
.log2_scale_factor
)
3048 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3053 i
.sib
.index
= i
.index_reg
->reg_num
;
3054 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3055 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3058 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3061 if (fake_zero_displacement
)
3063 /* Fakes a zero displacement assuming that i.types[op]
3064 holds the correct displacement size. */
3067 assert (i
.op
[op
].disps
== 0);
3068 exp
= &disp_expressions
[i
.disp_operands
++];
3069 i
.op
[op
].disps
= exp
;
3070 exp
->X_op
= O_constant
;
3071 exp
->X_add_number
= 0;
3072 exp
->X_add_symbol
= (symbolS
*) 0;
3073 exp
->X_op_symbol
= (symbolS
*) 0;
3077 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3078 (if any) based on i.tm.extension_opcode. Again, we must be
3079 careful to make sure that segment/control/debug/test/MMX
3080 registers are coded into the i.rm.reg field. */
3085 & (Reg
| RegMMX
| RegXMM
3087 | Control
| Debug
| Test
))
3090 & (Reg
| RegMMX
| RegXMM
3092 | Control
| Debug
| Test
))
3095 /* If there is an extension opcode to put here, the register
3096 number must be put into the regmem field. */
3097 if (i
.tm
.extension_opcode
!= None
)
3099 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
3100 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3105 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
3106 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3110 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3111 must set it to 3 to indicate this is a register operand
3112 in the regmem field. */
3113 if (!i
.mem_operands
)
3117 /* Fill in i.rm.reg field with extension opcode (if any). */
3118 if (i
.tm
.extension_opcode
!= None
)
3119 i
.rm
.reg
= i
.tm
.extension_opcode
;
3130 relax_substateT subtype
;
3135 if (flag_code
== CODE_16BIT
)
3139 if (i
.prefix
[DATA_PREFIX
] != 0)
3145 /* Pentium4 branch hints. */
3146 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3147 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3152 if (i
.prefix
[REX_PREFIX
] != 0)
3158 if (i
.prefixes
!= 0 && !intel_syntax
)
3159 as_warn (_("skipping prefixes on this instruction"));
3161 /* It's always a symbol; End frag & setup for relax.
3162 Make sure there is enough room in this frag for the largest
3163 instruction we may generate in md_convert_frag. This is 2
3164 bytes for the opcode and room for the prefix and largest
3166 frag_grow (prefix
+ 2 + 4);
3167 /* Prefix and 1 opcode byte go in fr_fix. */
3168 p
= frag_more (prefix
+ 1);
3169 if (i
.prefix
[DATA_PREFIX
] != 0)
3170 *p
++ = DATA_PREFIX_OPCODE
;
3171 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
3172 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
3173 *p
++ = i
.prefix
[SEG_PREFIX
];
3174 if (i
.prefix
[REX_PREFIX
] != 0)
3175 *p
++ = i
.prefix
[REX_PREFIX
];
3176 *p
= i
.tm
.base_opcode
;
3178 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
3179 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
3180 else if ((cpu_arch_flags
& Cpu386
) != 0)
3181 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
3183 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
3186 sym
= i
.op
[0].disps
->X_add_symbol
;
3187 off
= i
.op
[0].disps
->X_add_number
;
3189 if (i
.op
[0].disps
->X_op
!= O_constant
3190 && i
.op
[0].disps
->X_op
!= O_symbol
)
3192 /* Handle complex expressions. */
3193 sym
= make_expr_symbol (i
.op
[0].disps
);
3197 /* 1 possible extra opcode + 4 byte displacement go in var part.
3198 Pass reloc in fr_var. */
3199 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
3209 if (i
.tm
.opcode_modifier
& JumpByte
)
3211 /* This is a loop or jecxz type instruction. */
3213 if (i
.prefix
[ADDR_PREFIX
] != 0)
3215 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3218 /* Pentium4 branch hints. */
3219 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3220 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3222 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3231 if (flag_code
== CODE_16BIT
)
3234 if (i
.prefix
[DATA_PREFIX
] != 0)
3236 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3246 if (i
.prefix
[REX_PREFIX
] != 0)
3248 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3252 if (i
.prefixes
!= 0 && !intel_syntax
)
3253 as_warn (_("skipping prefixes on this instruction"));
3255 p
= frag_more (1 + size
);
3256 *p
++ = i
.tm
.base_opcode
;
3258 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3259 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3261 /* All jumps handled here are signed, but don't use a signed limit
3262 check for 32 and 16 bit jumps as we want to allow wrap around at
3263 4G and 64k respectively. */
3265 fixP
->fx_signed
= 1;
3269 output_interseg_jump ()
3277 if (flag_code
== CODE_16BIT
)
3281 if (i
.prefix
[DATA_PREFIX
] != 0)
3287 if (i
.prefix
[REX_PREFIX
] != 0)
3297 if (i
.prefixes
!= 0 && !intel_syntax
)
3298 as_warn (_("skipping prefixes on this instruction"));
3300 /* 1 opcode; 2 segment; offset */
3301 p
= frag_more (prefix
+ 1 + 2 + size
);
3303 if (i
.prefix
[DATA_PREFIX
] != 0)
3304 *p
++ = DATA_PREFIX_OPCODE
;
3306 if (i
.prefix
[REX_PREFIX
] != 0)
3307 *p
++ = i
.prefix
[REX_PREFIX
];
3309 *p
++ = i
.tm
.base_opcode
;
3310 if (i
.op
[1].imms
->X_op
== O_constant
)
3312 offsetT n
= i
.op
[1].imms
->X_add_number
;
3315 && !fits_in_unsigned_word (n
)
3316 && !fits_in_signed_word (n
))
3318 as_bad (_("16-bit jump out of range"));
3321 md_number_to_chars (p
, n
, size
);
3324 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3325 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3326 if (i
.op
[0].imms
->X_op
!= O_constant
)
3327 as_bad (_("can't handle non absolute segment in `%s'"),
3329 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3335 fragS
*insn_start_frag
;
3336 offsetT insn_start_off
;
3338 /* Tie dwarf2 debug info to the address at the start of the insn.
3339 We can't do this after the insn has been output as the current
3340 frag may have been closed off. eg. by frag_var. */
3341 dwarf2_emit_insn (0);
3343 insn_start_frag
= frag_now
;
3344 insn_start_off
= frag_now_fix ();
3347 if (i
.tm
.opcode_modifier
& Jump
)
3349 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3351 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3352 output_interseg_jump ();
3355 /* Output normal instructions here. */
3359 /* All opcodes on i386 have either 1 or 2 bytes. We may use one
3360 more higher byte to specify a prefix the instruction
3362 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
3364 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0)
3366 unsigned int prefix
;
3367 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
3369 if (prefix
!= REPE_PREFIX_OPCODE
3370 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
3371 add_prefix (prefix
);
3374 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
3377 /* The prefix bytes. */
3379 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3385 md_number_to_chars (p
, (valueT
) *q
, 1);
3389 /* Now the opcode; be careful about word order here! */
3390 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3392 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3398 /* Put out high byte first: can't use md_number_to_chars! */
3399 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3400 *p
= i
.tm
.base_opcode
& 0xff;
3403 /* Now the modrm byte and sib byte (if present). */
3404 if (i
.tm
.opcode_modifier
& Modrm
)
3407 md_number_to_chars (p
,
3408 (valueT
) (i
.rm
.regmem
<< 0
3412 /* If i.rm.regmem == ESP (4)
3413 && i.rm.mode != (Register mode)
3415 ==> need second modrm byte. */
3416 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3418 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3421 md_number_to_chars (p
,
3422 (valueT
) (i
.sib
.base
<< 0
3424 | i
.sib
.scale
<< 6),
3429 if (i
.disp_operands
)
3430 output_disp (insn_start_frag
, insn_start_off
);
3433 output_imm (insn_start_frag
, insn_start_off
);
3441 #endif /* DEBUG386 */
3445 output_disp (insn_start_frag
, insn_start_off
)
3446 fragS
*insn_start_frag
;
3447 offsetT insn_start_off
;
3452 for (n
= 0; n
< i
.operands
; n
++)
3454 if (i
.types
[n
] & Disp
)
3456 if (i
.op
[n
].disps
->X_op
== O_constant
)
3462 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
3465 if (i
.types
[n
] & Disp8
)
3467 if (i
.types
[n
] & Disp64
)
3470 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3472 p
= frag_more (size
);
3473 md_number_to_chars (p
, val
, size
);
3477 enum bfd_reloc_code_real reloc_type
;
3480 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3482 /* The PC relative address is computed relative
3483 to the instruction boundary, so in case immediate
3484 fields follows, we need to adjust the value. */
3485 if (pcrel
&& i
.imm_operands
)
3490 for (n1
= 0; n1
< i
.operands
; n1
++)
3491 if (i
.types
[n1
] & Imm
)
3493 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3496 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3498 if (i
.types
[n1
] & Imm64
)
3503 /* We should find the immediate. */
3504 if (n1
== i
.operands
)
3506 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3509 if (i
.types
[n
] & Disp32S
)
3512 if (i
.types
[n
] & (Disp16
| Disp64
))
3515 if (i
.types
[n
] & Disp64
)
3519 p
= frag_more (size
);
3520 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
3522 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
3523 && (((reloc_type
== BFD_RELOC_32
3524 || reloc_type
== BFD_RELOC_X86_64_32S
)
3525 && (i
.op
[n
].disps
->X_op
== O_symbol
3526 || (i
.op
[n
].disps
->X_op
== O_add
3527 && ((symbol_get_value_expression
3528 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
3530 || reloc_type
== BFD_RELOC_32_PCREL
))
3534 if (insn_start_frag
== frag_now
)
3535 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3540 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3541 for (fr
= insn_start_frag
->fr_next
;
3542 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3544 add
+= p
- frag_now
->fr_literal
;
3547 if (flag_code
!= CODE_64BIT
)
3548 reloc_type
= BFD_RELOC_386_GOTPC
;
3550 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
3551 i
.op
[n
].disps
->X_add_number
+= add
;
3553 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3554 i
.op
[n
].disps
, pcrel
, reloc_type
);
3561 output_imm (insn_start_frag
, insn_start_off
)
3562 fragS
*insn_start_frag
;
3563 offsetT insn_start_off
;
3568 for (n
= 0; n
< i
.operands
; n
++)
3570 if (i
.types
[n
] & Imm
)
3572 if (i
.op
[n
].imms
->X_op
== O_constant
)
3578 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3581 if (i
.types
[n
] & (Imm8
| Imm8S
))
3583 else if (i
.types
[n
] & Imm64
)
3586 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3588 p
= frag_more (size
);
3589 md_number_to_chars (p
, val
, size
);
3593 /* Not absolute_section.
3594 Need a 32-bit fixup (don't support 8bit
3595 non-absolute imms). Try to support other
3597 enum bfd_reloc_code_real reloc_type
;
3601 if ((i
.types
[n
] & (Imm32S
))
3602 && (i
.suffix
== QWORD_MNEM_SUFFIX
3603 || (!i
.suffix
&& (i
.tm
.opcode_modifier
& No_lSuf
))))
3605 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3608 if (i
.types
[n
] & (Imm8
| Imm8S
))
3610 if (i
.types
[n
] & Imm64
)
3614 p
= frag_more (size
);
3615 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3617 /* This is tough to explain. We end up with this one if we
3618 * have operands that look like
3619 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3620 * obtain the absolute address of the GOT, and it is strongly
3621 * preferable from a performance point of view to avoid using
3622 * a runtime relocation for this. The actual sequence of
3623 * instructions often look something like:
3628 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3630 * The call and pop essentially return the absolute address
3631 * of the label .L66 and store it in %ebx. The linker itself
3632 * will ultimately change the first operand of the addl so
3633 * that %ebx points to the GOT, but to keep things simple, the
3634 * .o file must have this operand set so that it generates not
3635 * the absolute address of .L66, but the absolute address of
3636 * itself. This allows the linker itself simply treat a GOTPC
3637 * relocation as asking for a pcrel offset to the GOT to be
3638 * added in, and the addend of the relocation is stored in the
3639 * operand field for the instruction itself.
3641 * Our job here is to fix the operand so that it would add
3642 * the correct offset so that %ebx would point to itself. The
3643 * thing that is tricky is that .-.L66 will point to the
3644 * beginning of the instruction, so we need to further modify
3645 * the operand so that it will point to itself. There are
3646 * other cases where you have something like:
3648 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3650 * and here no correction would be required. Internally in
3651 * the assembler we treat operands of this form as not being
3652 * pcrel since the '.' is explicitly mentioned, and I wonder
3653 * whether it would simplify matters to do it this way. Who
3654 * knows. In earlier versions of the PIC patches, the
3655 * pcrel_adjust field was used to store the correction, but
3656 * since the expression is not pcrel, I felt it would be
3657 * confusing to do it this way. */
3659 if ((reloc_type
== BFD_RELOC_32
3660 || reloc_type
== BFD_RELOC_X86_64_32S
)
3662 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3663 && (i
.op
[n
].imms
->X_op
== O_symbol
3664 || (i
.op
[n
].imms
->X_op
== O_add
3665 && ((symbol_get_value_expression
3666 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3671 if (insn_start_frag
== frag_now
)
3672 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3677 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3678 for (fr
= insn_start_frag
->fr_next
;
3679 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3681 add
+= p
- frag_now
->fr_literal
;
3684 if (flag_code
!= CODE_64BIT
)
3685 reloc_type
= BFD_RELOC_386_GOTPC
;
3687 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
3688 i
.op
[n
].imms
->X_add_number
+= add
;
3690 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3691 i
.op
[n
].imms
, 0, reloc_type
);
3698 static char *lex_got
PARAMS ((enum bfd_reloc_code_real
*, int *));
3700 /* Parse operands of the form
3701 <symbol>@GOTOFF+<nnn>
3702 and similar .plt or .got references.
3704 If we find one, set up the correct relocation in RELOC and copy the
3705 input string, minus the `@GOTOFF' into a malloc'd buffer for
3706 parsing by the calling routine. Return this buffer, and if ADJUST
3707 is non-null set it to the length of the string we removed from the
3708 input line. Otherwise return NULL. */
3710 lex_got (reloc
, adjust
)
3711 enum bfd_reloc_code_real
*reloc
;
3714 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3715 static const struct {
3717 const enum bfd_reloc_code_real rel
[NUM_FLAG_CODE
];
3719 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
} },
3720 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, BFD_RELOC_X86_64_GOTOFF64
} },
3721 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
} },
3722 { "TLSGD", { BFD_RELOC_386_TLS_GD
, 0, BFD_RELOC_X86_64_TLSGD
} },
3723 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
, 0, 0 } },
3724 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD
} },
3725 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
, 0, BFD_RELOC_X86_64_GOTTPOFF
} },
3726 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
, 0, BFD_RELOC_X86_64_TPOFF32
} },
3727 { "NTPOFF", { BFD_RELOC_386_TLS_LE
, 0, 0 } },
3728 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
, 0, BFD_RELOC_X86_64_DTPOFF32
} },
3729 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
, 0, 0 } },
3730 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
, 0, 0 } },
3731 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
} }
3736 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3737 if (is_end_of_line
[(unsigned char) *cp
])
3740 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3744 len
= strlen (gotrel
[j
].str
);
3745 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3747 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3750 char *tmpbuf
, *past_reloc
;
3752 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3756 if (GOT_symbol
== NULL
)
3757 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3759 /* Replace the relocation token with ' ', so that
3760 errors like foo@GOTOFF1 will be detected. */
3762 /* The length of the first part of our input line. */
3763 first
= cp
- input_line_pointer
;
3765 /* The second part goes from after the reloc token until
3766 (and including) an end_of_line char. Don't use strlen
3767 here as the end_of_line char may not be a NUL. */
3768 past_reloc
= cp
+ 1 + len
;
3769 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3771 second
= cp
- past_reloc
;
3773 /* Allocate and copy string. The trailing NUL shouldn't
3774 be necessary, but be safe. */
3775 tmpbuf
= xmalloc (first
+ second
+ 2);
3776 memcpy (tmpbuf
, input_line_pointer
, first
);
3777 tmpbuf
[first
] = ' ';
3778 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3779 tmpbuf
[first
+ second
+ 1] = '\0';
3783 as_bad (_("@%s reloc is not supported in %s bit mode"),
3784 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3789 /* Might be a symbol version string. Don't as_bad here. */
3793 /* x86_cons_fix_new is called via the expression parsing code when a
3794 reloc is needed. We use this hook to get the correct .got reloc. */
3795 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
3798 x86_cons_fix_new (frag
, off
, len
, exp
)
3804 enum bfd_reloc_code_real r
= reloc (len
, 0, 0, got_reloc
);
3805 got_reloc
= NO_RELOC
;
3806 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3810 x86_cons (exp
, size
)
3814 if (size
== 4 || (flag_code
== CODE_64BIT
&& size
== 8))
3816 /* Handle @GOTOFF and the like in an expression. */
3818 char *gotfree_input_line
;
3821 save
= input_line_pointer
;
3822 gotfree_input_line
= lex_got (&got_reloc
, &adjust
);
3823 if (gotfree_input_line
)
3824 input_line_pointer
= gotfree_input_line
;
3828 if (gotfree_input_line
)
3830 /* expression () has merrily parsed up to the end of line,
3831 or a comma - in the wrong buffer. Transfer how far
3832 input_line_pointer has moved to the right buffer. */
3833 input_line_pointer
= (save
3834 + (input_line_pointer
- gotfree_input_line
)
3836 free (gotfree_input_line
);
3847 x86_pe_cons_fix_new (frag
, off
, len
, exp
)
3853 enum bfd_reloc_code_real r
= reloc (len
, 0, 0, NO_RELOC
);
3855 if (exp
->X_op
== O_secrel
)
3857 exp
->X_op
= O_symbol
;
3858 r
= BFD_RELOC_32_SECREL
;
3861 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3865 pe_directive_secrel (dummy
)
3866 int dummy ATTRIBUTE_UNUSED
;
3873 if (exp
.X_op
== O_symbol
)
3874 exp
.X_op
= O_secrel
;
3876 emit_expr (&exp
, 4);
3878 while (*input_line_pointer
++ == ',');
3880 input_line_pointer
--;
3881 demand_empty_rest_of_line ();
3886 static int i386_immediate
PARAMS ((char *));
3889 i386_immediate (imm_start
)
3892 char *save_input_line_pointer
;
3894 char *gotfree_input_line
;
3899 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3901 as_bad (_("only 1 or 2 immediate operands are allowed"));
3905 exp
= &im_expressions
[i
.imm_operands
++];
3906 i
.op
[this_operand
].imms
= exp
;
3908 if (is_space_char (*imm_start
))
3911 save_input_line_pointer
= input_line_pointer
;
3912 input_line_pointer
= imm_start
;
3915 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3916 if (gotfree_input_line
)
3917 input_line_pointer
= gotfree_input_line
;
3920 exp_seg
= expression (exp
);
3923 if (*input_line_pointer
)
3924 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3926 input_line_pointer
= save_input_line_pointer
;
3928 if (gotfree_input_line
)
3929 free (gotfree_input_line
);
3932 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3934 /* Missing or bad expr becomes absolute 0. */
3935 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3937 exp
->X_op
= O_constant
;
3938 exp
->X_add_number
= 0;
3939 exp
->X_add_symbol
= (symbolS
*) 0;
3940 exp
->X_op_symbol
= (symbolS
*) 0;
3942 else if (exp
->X_op
== O_constant
)
3944 /* Size it properly later. */
3945 i
.types
[this_operand
] |= Imm64
;
3946 /* If BFD64, sign extend val. */
3947 if (!use_rela_relocations
)
3948 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3949 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3951 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3952 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
3953 && exp_seg
!= absolute_section
3954 && exp_seg
!= text_section
3955 && exp_seg
!= data_section
3956 && exp_seg
!= bss_section
3957 && exp_seg
!= undefined_section
3958 && !bfd_is_com_section (exp_seg
))
3960 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3966 /* This is an address. The size of the address will be
3967 determined later, depending on destination register,
3968 suffix, or the default for the section. */
3969 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3975 static char *i386_scale
PARAMS ((char *));
3982 char *save
= input_line_pointer
;
3984 input_line_pointer
= scale
;
3985 val
= get_absolute_expression ();
3990 i
.log2_scale_factor
= 0;
3993 i
.log2_scale_factor
= 1;
3996 i
.log2_scale_factor
= 2;
3999 i
.log2_scale_factor
= 3;
4003 char sep
= *input_line_pointer
;
4005 *input_line_pointer
= '\0';
4006 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4008 *input_line_pointer
= sep
;
4009 input_line_pointer
= save
;
4013 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
4015 as_warn (_("scale factor of %d without an index register"),
4016 1 << i
.log2_scale_factor
);
4017 #if SCALE1_WHEN_NO_INDEX
4018 i
.log2_scale_factor
= 0;
4021 scale
= input_line_pointer
;
4022 input_line_pointer
= save
;
4026 static int i386_displacement
PARAMS ((char *, char *));
4029 i386_displacement (disp_start
, disp_end
)
4035 char *save_input_line_pointer
;
4037 char *gotfree_input_line
;
4039 int bigdisp
= Disp32
;
4041 if (flag_code
== CODE_64BIT
)
4043 if (i
.prefix
[ADDR_PREFIX
] == 0)
4046 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4048 i
.types
[this_operand
] |= bigdisp
;
4050 exp
= &disp_expressions
[i
.disp_operands
];
4051 i
.op
[this_operand
].disps
= exp
;
4053 save_input_line_pointer
= input_line_pointer
;
4054 input_line_pointer
= disp_start
;
4055 END_STRING_AND_SAVE (disp_end
);
4057 #ifndef GCC_ASM_O_HACK
4058 #define GCC_ASM_O_HACK 0
4061 END_STRING_AND_SAVE (disp_end
+ 1);
4062 if ((i
.types
[this_operand
] & BaseIndex
) != 0
4063 && displacement_string_end
[-1] == '+')
4065 /* This hack is to avoid a warning when using the "o"
4066 constraint within gcc asm statements.
4069 #define _set_tssldt_desc(n,addr,limit,type) \
4070 __asm__ __volatile__ ( \
4072 "movw %w1,2+%0\n\t" \
4074 "movb %b1,4+%0\n\t" \
4075 "movb %4,5+%0\n\t" \
4076 "movb $0,6+%0\n\t" \
4077 "movb %h1,7+%0\n\t" \
4079 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4081 This works great except that the output assembler ends
4082 up looking a bit weird if it turns out that there is
4083 no offset. You end up producing code that looks like:
4096 So here we provide the missing zero. */
4098 *displacement_string_end
= '0';
4102 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
4103 if (gotfree_input_line
)
4104 input_line_pointer
= gotfree_input_line
;
4107 exp_seg
= expression (exp
);
4110 if (*input_line_pointer
)
4111 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4113 RESTORE_END_STRING (disp_end
+ 1);
4115 RESTORE_END_STRING (disp_end
);
4116 input_line_pointer
= save_input_line_pointer
;
4118 if (gotfree_input_line
)
4119 free (gotfree_input_line
);
4122 /* We do this to make sure that the section symbol is in
4123 the symbol table. We will ultimately change the relocation
4124 to be relative to the beginning of the section. */
4125 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
4126 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4127 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4129 if (exp
->X_op
!= O_symbol
)
4131 as_bad (_("bad expression used with @%s"),
4132 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4138 if (S_IS_LOCAL (exp
->X_add_symbol
)
4139 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
4140 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
4141 exp
->X_op
= O_subtract
;
4142 exp
->X_op_symbol
= GOT_symbol
;
4143 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
4144 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
4145 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4146 i
.reloc
[this_operand
] = BFD_RELOC_64
;
4148 i
.reloc
[this_operand
] = BFD_RELOC_32
;
4151 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4153 /* Missing or bad expr becomes absolute 0. */
4154 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4156 exp
->X_op
= O_constant
;
4157 exp
->X_add_number
= 0;
4158 exp
->X_add_symbol
= (symbolS
*) 0;
4159 exp
->X_op_symbol
= (symbolS
*) 0;
4162 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4163 if (exp
->X_op
!= O_constant
4164 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
4165 && exp_seg
!= absolute_section
4166 && exp_seg
!= text_section
4167 && exp_seg
!= data_section
4168 && exp_seg
!= bss_section
4169 && exp_seg
!= undefined_section
4170 && !bfd_is_com_section (exp_seg
))
4172 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4176 else if (flag_code
== CODE_64BIT
)
4177 i
.types
[this_operand
] |= Disp32S
| Disp32
;
4181 static int i386_index_check
PARAMS ((const char *));
4183 /* Make sure the memory operand we've been dealt is valid.
4184 Return 1 on success, 0 on a failure. */
4187 i386_index_check (operand_string
)
4188 const char *operand_string
;
4191 #if INFER_ADDR_PREFIX
4197 if (flag_code
== CODE_64BIT
)
4199 unsigned RegXX
= (i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
);
4202 && ((i
.base_reg
->reg_type
& RegXX
) == 0)
4203 && (i
.base_reg
->reg_type
!= BaseIndex
4206 && ((i
.index_reg
->reg_type
& (RegXX
| BaseIndex
))
4207 != (RegXX
| BaseIndex
))))
4212 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4216 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
4217 != (Reg16
| BaseIndex
)))
4219 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
4220 != (Reg16
| BaseIndex
))
4222 && i
.base_reg
->reg_num
< 6
4223 && i
.index_reg
->reg_num
>= 6
4224 && i
.log2_scale_factor
== 0))))
4231 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
4233 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
4234 != (Reg32
| BaseIndex
))))
4240 #if INFER_ADDR_PREFIX
4241 if (i
.prefix
[ADDR_PREFIX
] == 0)
4243 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
4245 /* Change the size of any displacement too. At most one of
4246 Disp16 or Disp32 is set.
4247 FIXME. There doesn't seem to be any real need for separate
4248 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4249 Removing them would probably clean up the code quite a lot. */
4250 if (flag_code
!= CODE_64BIT
&& (i
.types
[this_operand
] & (Disp16
| Disp32
)))
4251 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
4256 as_bad (_("`%s' is not a valid base/index expression"),
4260 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4262 flag_code_names
[flag_code
]);
4267 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4271 i386_operand (operand_string
)
4272 char *operand_string
;
4276 char *op_string
= operand_string
;
4278 if (is_space_char (*op_string
))
4281 /* We check for an absolute prefix (differentiating,
4282 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4283 if (*op_string
== ABSOLUTE_PREFIX
)
4286 if (is_space_char (*op_string
))
4288 i
.types
[this_operand
] |= JumpAbsolute
;
4291 /* Check if operand is a register. */
4292 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4293 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
4295 /* Check for a segment override by searching for ':' after a
4296 segment register. */
4298 if (is_space_char (*op_string
))
4300 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
4305 i
.seg
[i
.mem_operands
] = &es
;
4308 i
.seg
[i
.mem_operands
] = &cs
;
4311 i
.seg
[i
.mem_operands
] = &ss
;
4314 i
.seg
[i
.mem_operands
] = &ds
;
4317 i
.seg
[i
.mem_operands
] = &fs
;
4320 i
.seg
[i
.mem_operands
] = &gs
;
4324 /* Skip the ':' and whitespace. */
4326 if (is_space_char (*op_string
))
4329 if (!is_digit_char (*op_string
)
4330 && !is_identifier_char (*op_string
)
4331 && *op_string
!= '('
4332 && *op_string
!= ABSOLUTE_PREFIX
)
4334 as_bad (_("bad memory operand `%s'"), op_string
);
4337 /* Handle case of %es:*foo. */
4338 if (*op_string
== ABSOLUTE_PREFIX
)
4341 if (is_space_char (*op_string
))
4343 i
.types
[this_operand
] |= JumpAbsolute
;
4345 goto do_memory_reference
;
4349 as_bad (_("junk `%s' after register"), op_string
);
4352 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
4353 i
.op
[this_operand
].regs
= r
;
4356 else if (*op_string
== REGISTER_PREFIX
)
4358 as_bad (_("bad register name `%s'"), op_string
);
4361 else if (*op_string
== IMMEDIATE_PREFIX
)
4364 if (i
.types
[this_operand
] & JumpAbsolute
)
4366 as_bad (_("immediate operand illegal with absolute jump"));
4369 if (!i386_immediate (op_string
))
4372 else if (is_digit_char (*op_string
)
4373 || is_identifier_char (*op_string
)
4374 || *op_string
== '(')
4376 /* This is a memory reference of some sort. */
4379 /* Start and end of displacement string expression (if found). */
4380 char *displacement_string_start
;
4381 char *displacement_string_end
;
4383 do_memory_reference
:
4384 if ((i
.mem_operands
== 1
4385 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4386 || i
.mem_operands
== 2)
4388 as_bad (_("too many memory references for `%s'"),
4389 current_templates
->start
->name
);
4393 /* Check for base index form. We detect the base index form by
4394 looking for an ')' at the end of the operand, searching
4395 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4397 base_string
= op_string
+ strlen (op_string
);
4400 if (is_space_char (*base_string
))
4403 /* If we only have a displacement, set-up for it to be parsed later. */
4404 displacement_string_start
= op_string
;
4405 displacement_string_end
= base_string
+ 1;
4407 if (*base_string
== ')')
4410 unsigned int parens_balanced
= 1;
4411 /* We've already checked that the number of left & right ()'s are
4412 equal, so this loop will not be infinite. */
4416 if (*base_string
== ')')
4418 if (*base_string
== '(')
4421 while (parens_balanced
);
4423 temp_string
= base_string
;
4425 /* Skip past '(' and whitespace. */
4427 if (is_space_char (*base_string
))
4430 if (*base_string
== ','
4431 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4432 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
4434 displacement_string_end
= temp_string
;
4436 i
.types
[this_operand
] |= BaseIndex
;
4440 base_string
= end_op
;
4441 if (is_space_char (*base_string
))
4445 /* There may be an index reg or scale factor here. */
4446 if (*base_string
== ',')
4449 if (is_space_char (*base_string
))
4452 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4453 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
4455 base_string
= end_op
;
4456 if (is_space_char (*base_string
))
4458 if (*base_string
== ',')
4461 if (is_space_char (*base_string
))
4464 else if (*base_string
!= ')')
4466 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4471 else if (*base_string
== REGISTER_PREFIX
)
4473 as_bad (_("bad register name `%s'"), base_string
);
4477 /* Check for scale factor. */
4478 if (*base_string
!= ')')
4480 char *end_scale
= i386_scale (base_string
);
4485 base_string
= end_scale
;
4486 if (is_space_char (*base_string
))
4488 if (*base_string
!= ')')
4490 as_bad (_("expecting `)' after scale factor in `%s'"),
4495 else if (!i
.index_reg
)
4497 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4502 else if (*base_string
!= ')')
4504 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4509 else if (*base_string
== REGISTER_PREFIX
)
4511 as_bad (_("bad register name `%s'"), base_string
);
4516 /* If there's an expression beginning the operand, parse it,
4517 assuming displacement_string_start and
4518 displacement_string_end are meaningful. */
4519 if (displacement_string_start
!= displacement_string_end
)
4521 if (!i386_displacement (displacement_string_start
,
4522 displacement_string_end
))
4526 /* Special case for (%dx) while doing input/output op. */
4528 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
4530 && i
.log2_scale_factor
== 0
4531 && i
.seg
[i
.mem_operands
] == 0
4532 && (i
.types
[this_operand
] & Disp
) == 0)
4534 i
.types
[this_operand
] = InOutPortReg
;
4538 if (i386_index_check (operand_string
) == 0)
4544 /* It's not a memory operand; argh! */
4545 as_bad (_("invalid char %s beginning operand %d `%s'"),
4546 output_invalid (*op_string
),
4551 return 1; /* Normal return. */
4554 /* md_estimate_size_before_relax()
4556 Called just before relax() for rs_machine_dependent frags. The x86
4557 assembler uses these frags to handle variable size jump
4560 Any symbol that is now undefined will not become defined.
4561 Return the correct fr_subtype in the frag.
4562 Return the initial "guess for variable size of frag" to caller.
4563 The guess is actually the growth beyond the fixed part. Whatever
4564 we do to grow the fixed or variable part contributes to our
4568 md_estimate_size_before_relax (fragP
, segment
)
4572 /* We've already got fragP->fr_subtype right; all we have to do is
4573 check for un-relaxable symbols. On an ELF system, we can't relax
4574 an externally visible symbol, because it may be overridden by a
4576 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4577 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4578 || (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4579 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
4580 || S_IS_WEAK (fragP
->fr_symbol
)))
4584 /* Symbol is undefined in this segment, or we need to keep a
4585 reloc so that weak symbols can be overridden. */
4586 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
4587 enum bfd_reloc_code_real reloc_type
;
4588 unsigned char *opcode
;
4591 if (fragP
->fr_var
!= NO_RELOC
)
4592 reloc_type
= fragP
->fr_var
;
4594 reloc_type
= BFD_RELOC_16_PCREL
;
4596 reloc_type
= BFD_RELOC_32_PCREL
;
4598 old_fr_fix
= fragP
->fr_fix
;
4599 opcode
= (unsigned char *) fragP
->fr_opcode
;
4601 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4604 /* Make jmp (0xeb) a (d)word displacement jump. */
4606 fragP
->fr_fix
+= size
;
4607 fix_new (fragP
, old_fr_fix
, size
,
4609 fragP
->fr_offset
, 1,
4615 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
4617 /* Negate the condition, and branch past an
4618 unconditional jump. */
4621 /* Insert an unconditional jump. */
4623 /* We added two extra opcode bytes, and have a two byte
4625 fragP
->fr_fix
+= 2 + 2;
4626 fix_new (fragP
, old_fr_fix
+ 2, 2,
4628 fragP
->fr_offset
, 1,
4635 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
4640 fixP
= fix_new (fragP
, old_fr_fix
, 1,
4642 fragP
->fr_offset
, 1,
4644 fixP
->fx_signed
= 1;
4648 /* This changes the byte-displacement jump 0x7N
4649 to the (d)word-displacement jump 0x0f,0x8N. */
4650 opcode
[1] = opcode
[0] + 0x10;
4651 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4652 /* We've added an opcode byte. */
4653 fragP
->fr_fix
+= 1 + size
;
4654 fix_new (fragP
, old_fr_fix
+ 1, size
,
4656 fragP
->fr_offset
, 1,
4661 BAD_CASE (fragP
->fr_subtype
);
4665 return fragP
->fr_fix
- old_fr_fix
;
4668 /* Guess size depending on current relax state. Initially the relax
4669 state will correspond to a short jump and we return 1, because
4670 the variable part of the frag (the branch offset) is one byte
4671 long. However, we can relax a section more than once and in that
4672 case we must either set fr_subtype back to the unrelaxed state,
4673 or return the value for the appropriate branch. */
4674 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4677 /* Called after relax() is finished.
4679 In: Address of frag.
4680 fr_type == rs_machine_dependent.
4681 fr_subtype is what the address relaxed to.
4683 Out: Any fixSs and constants are set up.
4684 Caller will turn frag into a ".space 0". */
4687 md_convert_frag (abfd
, sec
, fragP
)
4688 bfd
*abfd ATTRIBUTE_UNUSED
;
4689 segT sec ATTRIBUTE_UNUSED
;
4692 unsigned char *opcode
;
4693 unsigned char *where_to_put_displacement
= NULL
;
4694 offsetT target_address
;
4695 offsetT opcode_address
;
4696 unsigned int extension
= 0;
4697 offsetT displacement_from_opcode_start
;
4699 opcode
= (unsigned char *) fragP
->fr_opcode
;
4701 /* Address we want to reach in file space. */
4702 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4704 /* Address opcode resides at in file space. */
4705 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4707 /* Displacement from opcode start to fill into instruction. */
4708 displacement_from_opcode_start
= target_address
- opcode_address
;
4710 if ((fragP
->fr_subtype
& BIG
) == 0)
4712 /* Don't have to change opcode. */
4713 extension
= 1; /* 1 opcode + 1 displacement */
4714 where_to_put_displacement
= &opcode
[1];
4718 if (no_cond_jump_promotion
4719 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4720 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4722 switch (fragP
->fr_subtype
)
4724 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4725 extension
= 4; /* 1 opcode + 4 displacement */
4727 where_to_put_displacement
= &opcode
[1];
4730 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4731 extension
= 2; /* 1 opcode + 2 displacement */
4733 where_to_put_displacement
= &opcode
[1];
4736 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4737 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4738 extension
= 5; /* 2 opcode + 4 displacement */
4739 opcode
[1] = opcode
[0] + 0x10;
4740 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4741 where_to_put_displacement
= &opcode
[2];
4744 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4745 extension
= 3; /* 2 opcode + 2 displacement */
4746 opcode
[1] = opcode
[0] + 0x10;
4747 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4748 where_to_put_displacement
= &opcode
[2];
4751 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4756 where_to_put_displacement
= &opcode
[3];
4760 BAD_CASE (fragP
->fr_subtype
);
4765 /* Now put displacement after opcode. */
4766 md_number_to_chars ((char *) where_to_put_displacement
,
4767 (valueT
) (displacement_from_opcode_start
- extension
),
4768 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4769 fragP
->fr_fix
+= extension
;
4772 /* Size of byte displacement jmp. */
4773 int md_short_jump_size
= 2;
4775 /* Size of dword displacement jmp. */
4776 int md_long_jump_size
= 5;
4778 /* Size of relocation record. */
4779 const int md_reloc_size
= 8;
4782 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4784 addressT from_addr
, to_addr
;
4785 fragS
*frag ATTRIBUTE_UNUSED
;
4786 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4790 offset
= to_addr
- (from_addr
+ 2);
4791 /* Opcode for byte-disp jump. */
4792 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4793 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4797 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4799 addressT from_addr
, to_addr
;
4800 fragS
*frag ATTRIBUTE_UNUSED
;
4801 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4805 offset
= to_addr
- (from_addr
+ 5);
4806 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4807 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4810 /* Apply a fixup (fixS) to segment data, once it has been determined
4811 by our caller that we have all the info we need to fix it up.
4813 On the 386, immediates, displacements, and data pointers are all in
4814 the same (little-endian) format, so we don't need to care about which
4818 md_apply_fix (fixP
, valP
, seg
)
4819 /* The fix we're to put in. */
4821 /* Pointer to the value of the bits. */
4823 /* Segment fix is from. */
4824 segT seg ATTRIBUTE_UNUSED
;
4826 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4827 valueT value
= *valP
;
4829 #if !defined (TE_Mach)
4832 switch (fixP
->fx_r_type
)
4838 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
4841 case BFD_RELOC_X86_64_32S
:
4842 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4845 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4848 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4853 if (fixP
->fx_addsy
!= NULL
4854 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4855 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
4856 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4857 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4858 && !use_rela_relocations
)
4860 /* This is a hack. There should be a better way to handle this.
4861 This covers for the fact that bfd_install_relocation will
4862 subtract the current location (for partial_inplace, PC relative
4863 relocations); see more below. */
4865 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4867 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4870 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4872 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4873 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4875 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4878 || (symbol_section_p (fixP
->fx_addsy
)
4879 && sym_seg
!= absolute_section
))
4880 && !generic_force_reloc (fixP
))
4882 /* Yes, we add the values in twice. This is because
4883 bfd_install_relocation subtracts them out again. I think
4884 bfd_install_relocation is broken, but I don't dare change
4886 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4890 #if defined (OBJ_COFF) && defined (TE_PE)
4891 /* For some reason, the PE format does not store a
4892 section address offset for a PC relative symbol. */
4893 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
4894 #if defined(BFD_ASSEMBLER) || defined(S_IS_WEAK)
4895 || S_IS_WEAK (fixP
->fx_addsy
)
4898 value
+= md_pcrel_from (fixP
);
4902 /* Fix a few things - the dynamic linker expects certain values here,
4903 and we must not disappoint it. */
4904 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4905 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4907 switch (fixP
->fx_r_type
)
4909 case BFD_RELOC_386_PLT32
:
4910 case BFD_RELOC_X86_64_PLT32
:
4911 /* Make the jump instruction point to the address of the operand. At
4912 runtime we merely add the offset to the actual PLT entry. */
4916 case BFD_RELOC_386_TLS_GD
:
4917 case BFD_RELOC_386_TLS_LDM
:
4918 case BFD_RELOC_386_TLS_IE_32
:
4919 case BFD_RELOC_386_TLS_IE
:
4920 case BFD_RELOC_386_TLS_GOTIE
:
4921 case BFD_RELOC_X86_64_TLSGD
:
4922 case BFD_RELOC_X86_64_TLSLD
:
4923 case BFD_RELOC_X86_64_GOTTPOFF
:
4924 value
= 0; /* Fully resolved at runtime. No addend. */
4926 case BFD_RELOC_386_TLS_LE
:
4927 case BFD_RELOC_386_TLS_LDO_32
:
4928 case BFD_RELOC_386_TLS_LE_32
:
4929 case BFD_RELOC_X86_64_DTPOFF32
:
4930 case BFD_RELOC_X86_64_DTPOFF64
:
4931 case BFD_RELOC_X86_64_TPOFF32
:
4932 case BFD_RELOC_X86_64_TPOFF64
:
4933 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
4936 case BFD_RELOC_386_GOT32
:
4937 case BFD_RELOC_X86_64_GOT32
:
4938 value
= 0; /* Fully resolved at runtime. No addend. */
4941 case BFD_RELOC_VTABLE_INHERIT
:
4942 case BFD_RELOC_VTABLE_ENTRY
:
4949 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4951 #endif /* !defined (TE_Mach) */
4953 /* Are we finished with this relocation now? */
4954 if (fixP
->fx_addsy
== NULL
)
4956 else if (use_rela_relocations
)
4958 fixP
->fx_no_overflow
= 1;
4959 /* Remember value for tc_gen_reloc. */
4960 fixP
->fx_addnumber
= value
;
4964 md_number_to_chars (p
, value
, fixP
->fx_size
);
4967 #define MAX_LITTLENUMS 6
4969 /* Turn the string pointed to by litP into a floating point constant
4970 of type TYPE, and emit the appropriate bytes. The number of
4971 LITTLENUMS emitted is stored in *SIZEP. An error message is
4972 returned, or NULL on OK. */
4975 md_atof (type
, litP
, sizeP
)
4981 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4982 LITTLENUM_TYPE
*wordP
;
5004 return _("Bad call to md_atof ()");
5006 t
= atof_ieee (input_line_pointer
, type
, words
);
5008 input_line_pointer
= t
;
5010 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
5011 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5012 the bigendian 386. */
5013 for (wordP
= words
+ prec
- 1; prec
--;)
5015 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
5016 litP
+= sizeof (LITTLENUM_TYPE
);
5021 static char output_invalid_buf
[8];
5028 sprintf (output_invalid_buf
, "'%c'", c
);
5030 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
5031 return output_invalid_buf
;
5034 /* REG_STRING starts *before* REGISTER_PREFIX. */
5036 static const reg_entry
*
5037 parse_register (reg_string
, end_op
)
5041 char *s
= reg_string
;
5043 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
5046 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5047 if (*s
== REGISTER_PREFIX
)
5050 if (is_space_char (*s
))
5054 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
5056 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
5057 return (const reg_entry
*) NULL
;
5061 /* For naked regs, make sure that we are not dealing with an identifier.
5062 This prevents confusing an identifier like `eax_var' with register
5064 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
5065 return (const reg_entry
*) NULL
;
5069 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
5071 /* Handle floating point regs, allowing spaces in the (i) part. */
5072 if (r
== i386_regtab
/* %st is first entry of table */)
5074 if (is_space_char (*s
))
5079 if (is_space_char (*s
))
5081 if (*s
>= '0' && *s
<= '7')
5083 r
= &i386_float_regtab
[*s
- '0'];
5085 if (is_space_char (*s
))
5093 /* We have "%st(" then garbage. */
5094 return (const reg_entry
*) NULL
;
5099 && ((r
->reg_flags
& (RegRex64
| RegRex
)) | (r
->reg_type
& Reg64
)) != 0
5100 && (r
->reg_type
!= Control
|| !(cpu_arch_flags
& CpuSledgehammer
))
5101 && flag_code
!= CODE_64BIT
)
5102 return (const reg_entry
*) NULL
;
5107 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5108 const char *md_shortopts
= "kVQ:sqn";
5110 const char *md_shortopts
= "qn";
5113 struct option md_longopts
[] = {
5114 #define OPTION_32 (OPTION_MD_BASE + 0)
5115 {"32", no_argument
, NULL
, OPTION_32
},
5116 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5117 #define OPTION_64 (OPTION_MD_BASE + 1)
5118 {"64", no_argument
, NULL
, OPTION_64
},
5120 {NULL
, no_argument
, NULL
, 0}
5122 size_t md_longopts_size
= sizeof (md_longopts
);
5125 md_parse_option (c
, arg
)
5127 char *arg ATTRIBUTE_UNUSED
;
5132 optimize_align_code
= 0;
5139 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5140 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5141 should be emitted or not. FIXME: Not implemented. */
5145 /* -V: SVR4 argument to print version ID. */
5147 print_version_id ();
5150 /* -k: Ignore for FreeBSD compatibility. */
5155 /* -s: On i386 Solaris, this tells the native assembler to use
5156 .stab instead of .stab.excl. We always use .stab anyhow. */
5161 const char **list
, **l
;
5163 list
= bfd_target_list ();
5164 for (l
= list
; *l
!= NULL
; l
++)
5165 if (strcmp (*l
, "elf64-x86-64") == 0)
5167 default_arch
= "x86_64";
5171 as_fatal (_("No compiled in support for x86_64"));
5178 default_arch
= "i386";
5188 md_show_usage (stream
)
5191 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5192 fprintf (stream
, _("\
5194 -V print assembler version number\n\
5196 -n Do not optimize code alignment\n\
5197 -q quieten some warnings\n\
5200 fprintf (stream
, _("\
5201 -n Do not optimize code alignment\n\
5202 -q quieten some warnings\n"));
5206 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5207 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5209 /* Pick the target format to use. */
5212 i386_target_format ()
5214 if (!strcmp (default_arch
, "x86_64"))
5215 set_code_flag (CODE_64BIT
);
5216 else if (!strcmp (default_arch
, "i386"))
5217 set_code_flag (CODE_32BIT
);
5219 as_fatal (_("Unknown architecture"));
5220 switch (OUTPUT_FLAVOR
)
5222 #ifdef OBJ_MAYBE_AOUT
5223 case bfd_target_aout_flavour
:
5224 return AOUT_TARGET_FORMAT
;
5226 #ifdef OBJ_MAYBE_COFF
5227 case bfd_target_coff_flavour
:
5230 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5231 case bfd_target_elf_flavour
:
5233 if (flag_code
== CODE_64BIT
)
5234 use_rela_relocations
= 1;
5235 return flag_code
== CODE_64BIT
? "elf64-x86-64" : ELF_TARGET_FORMAT
;
5244 #endif /* OBJ_MAYBE_ more than one */
5246 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5247 void i386_elf_emit_arch_note ()
5249 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
5250 && cpu_arch_name
!= NULL
)
5253 asection
*seg
= now_seg
;
5254 subsegT subseg
= now_subseg
;
5255 Elf_Internal_Note i_note
;
5256 Elf_External_Note e_note
;
5257 asection
*note_secp
;
5260 /* Create the .note section. */
5261 note_secp
= subseg_new (".note", 0);
5262 bfd_set_section_flags (stdoutput
,
5264 SEC_HAS_CONTENTS
| SEC_READONLY
);
5266 /* Process the arch string. */
5267 len
= strlen (cpu_arch_name
);
5269 i_note
.namesz
= len
+ 1;
5271 i_note
.type
= NT_ARCH
;
5272 p
= frag_more (sizeof (e_note
.namesz
));
5273 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
5274 p
= frag_more (sizeof (e_note
.descsz
));
5275 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
5276 p
= frag_more (sizeof (e_note
.type
));
5277 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
5278 p
= frag_more (len
+ 1);
5279 strcpy (p
, cpu_arch_name
);
5281 frag_align (2, 0, 0);
5283 subseg_set (seg
, subseg
);
5289 md_undefined_symbol (name
)
5292 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
5293 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
5294 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
5295 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
5299 if (symbol_find (name
))
5300 as_bad (_("GOT already in symbol table"));
5301 GOT_symbol
= symbol_new (name
, undefined_section
,
5302 (valueT
) 0, &zero_address_frag
);
5309 /* Round up a section size to the appropriate boundary. */
5312 md_section_align (segment
, size
)
5313 segT segment ATTRIBUTE_UNUSED
;
5316 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5317 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
5319 /* For a.out, force the section size to be aligned. If we don't do
5320 this, BFD will align it for us, but it will not write out the
5321 final bytes of the section. This may be a bug in BFD, but it is
5322 easier to fix it here since that is how the other a.out targets
5326 align
= bfd_get_section_alignment (stdoutput
, segment
);
5327 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
5334 /* On the i386, PC-relative offsets are relative to the start of the
5335 next instruction. That is, the address of the offset, plus its
5336 size, since the offset is always the last part of the insn. */
5339 md_pcrel_from (fixP
)
5342 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5349 int ignore ATTRIBUTE_UNUSED
;
5353 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5355 obj_elf_section_change_hook ();
5357 temp
= get_absolute_expression ();
5358 subseg_set (bss_section
, (subsegT
) temp
);
5359 demand_empty_rest_of_line ();
5365 i386_validate_fix (fixp
)
5368 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
5370 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
5372 if (flag_code
!= CODE_64BIT
)
5374 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
5378 if (flag_code
!= CODE_64BIT
)
5379 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
5381 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
5388 tc_gen_reloc (section
, fixp
)
5389 asection
*section ATTRIBUTE_UNUSED
;
5393 bfd_reloc_code_real_type code
;
5395 switch (fixp
->fx_r_type
)
5397 case BFD_RELOC_X86_64_PLT32
:
5398 case BFD_RELOC_X86_64_GOT32
:
5399 case BFD_RELOC_X86_64_GOTPCREL
:
5400 case BFD_RELOC_386_PLT32
:
5401 case BFD_RELOC_386_GOT32
:
5402 case BFD_RELOC_386_GOTOFF
:
5403 case BFD_RELOC_386_GOTPC
:
5404 case BFD_RELOC_386_TLS_GD
:
5405 case BFD_RELOC_386_TLS_LDM
:
5406 case BFD_RELOC_386_TLS_LDO_32
:
5407 case BFD_RELOC_386_TLS_IE_32
:
5408 case BFD_RELOC_386_TLS_IE
:
5409 case BFD_RELOC_386_TLS_GOTIE
:
5410 case BFD_RELOC_386_TLS_LE_32
:
5411 case BFD_RELOC_386_TLS_LE
:
5412 case BFD_RELOC_X86_64_TLSGD
:
5413 case BFD_RELOC_X86_64_TLSLD
:
5414 case BFD_RELOC_X86_64_DTPOFF32
:
5415 case BFD_RELOC_X86_64_DTPOFF64
:
5416 case BFD_RELOC_X86_64_GOTTPOFF
:
5417 case BFD_RELOC_X86_64_TPOFF32
:
5418 case BFD_RELOC_X86_64_TPOFF64
:
5419 case BFD_RELOC_X86_64_GOTOFF64
:
5420 case BFD_RELOC_X86_64_GOTPC32
:
5422 case BFD_RELOC_VTABLE_ENTRY
:
5423 case BFD_RELOC_VTABLE_INHERIT
:
5425 case BFD_RELOC_32_SECREL
:
5427 code
= fixp
->fx_r_type
;
5429 case BFD_RELOC_X86_64_32S
:
5430 if (!fixp
->fx_pcrel
)
5432 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5433 code
= fixp
->fx_r_type
;
5439 switch (fixp
->fx_size
)
5442 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5443 _("can not do %d byte pc-relative relocation"),
5445 code
= BFD_RELOC_32_PCREL
;
5447 case 1: code
= BFD_RELOC_8_PCREL
; break;
5448 case 2: code
= BFD_RELOC_16_PCREL
; break;
5449 case 4: code
= BFD_RELOC_32_PCREL
; break;
5451 case 8: code
= BFD_RELOC_64_PCREL
; break;
5457 switch (fixp
->fx_size
)
5460 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5461 _("can not do %d byte relocation"),
5463 code
= BFD_RELOC_32
;
5465 case 1: code
= BFD_RELOC_8
; break;
5466 case 2: code
= BFD_RELOC_16
; break;
5467 case 4: code
= BFD_RELOC_32
; break;
5469 case 8: code
= BFD_RELOC_64
; break;
5476 if ((code
== BFD_RELOC_32
|| code
== BFD_RELOC_32_PCREL
)
5478 && fixp
->fx_addsy
== GOT_symbol
)
5480 if (flag_code
!= CODE_64BIT
)
5481 code
= BFD_RELOC_386_GOTPC
;
5483 code
= BFD_RELOC_X86_64_GOTPC32
;
5486 rel
= (arelent
*) xmalloc (sizeof (arelent
));
5487 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5488 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5490 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5492 if (!use_rela_relocations
)
5494 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5495 vtable entry to be used in the relocation's section offset. */
5496 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5497 rel
->address
= fixp
->fx_offset
;
5501 /* Use the rela in 64bit mode. */
5504 if (!fixp
->fx_pcrel
)
5505 rel
->addend
= fixp
->fx_offset
;
5509 case BFD_RELOC_X86_64_PLT32
:
5510 case BFD_RELOC_X86_64_GOT32
:
5511 case BFD_RELOC_X86_64_GOTPCREL
:
5512 case BFD_RELOC_X86_64_TLSGD
:
5513 case BFD_RELOC_X86_64_TLSLD
:
5514 case BFD_RELOC_X86_64_GOTTPOFF
:
5515 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
5518 rel
->addend
= (section
->vma
5520 + fixp
->fx_addnumber
5521 + md_pcrel_from (fixp
));
5526 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
5527 if (rel
->howto
== NULL
)
5529 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5530 _("cannot represent relocation type %s"),
5531 bfd_get_reloc_code_name (code
));
5532 /* Set howto to a garbage value so that we can keep going. */
5533 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
5534 assert (rel
->howto
!= NULL
);
5541 /* Parse operands using Intel syntax. This implements a recursive descent
5542 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5545 FIXME: We do not recognize the full operand grammar defined in the MASM
5546 documentation. In particular, all the structure/union and
5547 high-level macro operands are missing.
5549 Uppercase words are terminals, lower case words are non-terminals.
5550 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5551 bars '|' denote choices. Most grammar productions are implemented in
5552 functions called 'intel_<production>'.
5554 Initial production is 'expr'.
5560 binOp & | AND | \| | OR | ^ | XOR
5562 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5564 constant digits [[ radixOverride ]]
5566 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
5604 => expr expr cmpOp e04
5607 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5608 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5610 hexdigit a | b | c | d | e | f
5611 | A | B | C | D | E | F
5617 mulOp * | / | % | MOD | << | SHL | >> | SHR
5621 register specialRegister
5625 segmentRegister CS | DS | ES | FS | GS | SS
5627 specialRegister CR0 | CR2 | CR3 | CR4
5628 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5629 | TR3 | TR4 | TR5 | TR6 | TR7
5631 We simplify the grammar in obvious places (e.g., register parsing is
5632 done by calling parse_register) and eliminate immediate left recursion
5633 to implement a recursive-descent parser.
5637 expr' cmpOp e04 expr'
5688 /* Parsing structure for the intel syntax parser. Used to implement the
5689 semantic actions for the operand grammar. */
5690 struct intel_parser_s
5692 char *op_string
; /* The string being parsed. */
5693 int got_a_float
; /* Whether the operand is a float. */
5694 int op_modifier
; /* Operand modifier. */
5695 int is_mem
; /* 1 if operand is memory reference. */
5696 int in_offset
; /* >=1 if parsing operand of offset. */
5697 int in_bracket
; /* >=1 if parsing operand in brackets. */
5698 const reg_entry
*reg
; /* Last register reference found. */
5699 char *disp
; /* Displacement string being built. */
5700 char *next_operand
; /* Resume point when splitting operands. */
5703 static struct intel_parser_s intel_parser
;
5705 /* Token structure for parsing intel syntax. */
5708 int code
; /* Token code. */
5709 const reg_entry
*reg
; /* Register entry for register tokens. */
5710 char *str
; /* String representation. */
5713 static struct intel_token cur_token
, prev_token
;
5715 /* Token codes for the intel parser. Since T_SHORT is already used
5716 by COFF, undefine it first to prevent a warning. */
5735 /* Prototypes for intel parser functions. */
5736 static int intel_match_token
PARAMS ((int code
));
5737 static void intel_get_token
PARAMS ((void));
5738 static void intel_putback_token
PARAMS ((void));
5739 static int intel_expr
PARAMS ((void));
5740 static int intel_e04
PARAMS ((void));
5741 static int intel_e05
PARAMS ((void));
5742 static int intel_e06
PARAMS ((void));
5743 static int intel_e09
PARAMS ((void));
5744 static int intel_bracket_expr
PARAMS ((void));
5745 static int intel_e10
PARAMS ((void));
5746 static int intel_e11
PARAMS ((void));
5749 i386_intel_operand (operand_string
, got_a_float
)
5750 char *operand_string
;
5756 p
= intel_parser
.op_string
= xstrdup (operand_string
);
5757 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
5761 /* Initialize token holders. */
5762 cur_token
.code
= prev_token
.code
= T_NIL
;
5763 cur_token
.reg
= prev_token
.reg
= NULL
;
5764 cur_token
.str
= prev_token
.str
= NULL
;
5766 /* Initialize parser structure. */
5767 intel_parser
.got_a_float
= got_a_float
;
5768 intel_parser
.op_modifier
= 0;
5769 intel_parser
.is_mem
= 0;
5770 intel_parser
.in_offset
= 0;
5771 intel_parser
.in_bracket
= 0;
5772 intel_parser
.reg
= NULL
;
5773 intel_parser
.disp
[0] = '\0';
5774 intel_parser
.next_operand
= NULL
;
5776 /* Read the first token and start the parser. */
5778 ret
= intel_expr ();
5783 if (cur_token
.code
!= T_NIL
)
5785 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
5786 current_templates
->start
->name
, cur_token
.str
);
5789 /* If we found a memory reference, hand it over to i386_displacement
5790 to fill in the rest of the operand fields. */
5791 else if (intel_parser
.is_mem
)
5793 if ((i
.mem_operands
== 1
5794 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5795 || i
.mem_operands
== 2)
5797 as_bad (_("too many memory references for '%s'"),
5798 current_templates
->start
->name
);
5803 char *s
= intel_parser
.disp
;
5806 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
5807 /* See the comments in intel_bracket_expr. */
5808 as_warn (_("Treating `%s' as memory reference"), operand_string
);
5810 /* Add the displacement expression. */
5812 ret
= i386_displacement (s
, s
+ strlen (s
));
5815 /* Swap base and index in 16-bit memory operands like
5816 [si+bx]. Since i386_index_check is also used in AT&T
5817 mode we have to do that here. */
5820 && (i
.base_reg
->reg_type
& Reg16
)
5821 && (i
.index_reg
->reg_type
& Reg16
)
5822 && i
.base_reg
->reg_num
>= 6
5823 && i
.index_reg
->reg_num
< 6)
5825 const reg_entry
*base
= i
.index_reg
;
5827 i
.index_reg
= i
.base_reg
;
5830 ret
= i386_index_check (operand_string
);
5835 /* Constant and OFFSET expressions are handled by i386_immediate. */
5836 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
5837 || intel_parser
.reg
== NULL
)
5838 ret
= i386_immediate (intel_parser
.disp
);
5840 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
5842 if (!ret
|| !intel_parser
.next_operand
)
5844 intel_parser
.op_string
= intel_parser
.next_operand
;
5845 this_operand
= i
.operands
++;
5849 free (intel_parser
.disp
);
5854 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
5858 expr' cmpOp e04 expr'
5863 /* XXX Implement the comparison operators. */
5864 return intel_e04 ();
5881 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
5882 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
5884 if (cur_token
.code
== '+')
5886 else if (cur_token
.code
== '-')
5887 nregs
= NUM_ADDRESS_REGS
;
5891 strcat (intel_parser
.disp
, cur_token
.str
);
5892 intel_match_token (cur_token
.code
);
5903 int nregs
= ~NUM_ADDRESS_REGS
;
5910 if (cur_token
.code
== '&' || cur_token
.code
== '|' || cur_token
.code
== '^')
5914 str
[0] = cur_token
.code
;
5916 strcat (intel_parser
.disp
, str
);
5921 intel_match_token (cur_token
.code
);
5926 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
5927 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
5938 int nregs
= ~NUM_ADDRESS_REGS
;
5945 if (cur_token
.code
== '*' || cur_token
.code
== '/' || cur_token
.code
== '%')
5949 str
[0] = cur_token
.code
;
5951 strcat (intel_parser
.disp
, str
);
5953 else if (cur_token
.code
== T_SHL
)
5954 strcat (intel_parser
.disp
, "<<");
5955 else if (cur_token
.code
== T_SHR
)
5956 strcat (intel_parser
.disp
, ">>");
5960 intel_match_token (cur_token
.code
);
5965 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
5966 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
5984 int nregs
= ~NUM_ADDRESS_REGS
;
5989 /* Don't consume constants here. */
5990 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5992 /* Need to look one token ahead - if the next token
5993 is a constant, the current token is its sign. */
5996 intel_match_token (cur_token
.code
);
5997 next_code
= cur_token
.code
;
5998 intel_putback_token ();
5999 if (next_code
== T_CONST
)
6003 /* e09 OFFSET e09 */
6004 if (cur_token
.code
== T_OFFSET
)
6007 ++intel_parser
.in_offset
;
6011 else if (cur_token
.code
== T_SHORT
)
6012 intel_parser
.op_modifier
|= 1 << T_SHORT
;
6015 else if (cur_token
.code
== '+')
6016 strcat (intel_parser
.disp
, "+");
6021 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
6027 str
[0] = cur_token
.code
;
6029 strcat (intel_parser
.disp
, str
);
6036 intel_match_token (cur_token
.code
);
6044 /* e09' PTR e10 e09' */
6045 if (cur_token
.code
== T_PTR
)
6049 if (prev_token
.code
== T_BYTE
)
6050 suffix
= BYTE_MNEM_SUFFIX
;
6052 else if (prev_token
.code
== T_WORD
)
6054 if (current_templates
->start
->name
[0] == 'l'
6055 && current_templates
->start
->name
[2] == 's'
6056 && current_templates
->start
->name
[3] == 0)
6057 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6058 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
6059 suffix
= SHORT_MNEM_SUFFIX
;
6061 suffix
= WORD_MNEM_SUFFIX
;
6064 else if (prev_token
.code
== T_DWORD
)
6066 if (current_templates
->start
->name
[0] == 'l'
6067 && current_templates
->start
->name
[2] == 's'
6068 && current_templates
->start
->name
[3] == 0)
6069 suffix
= WORD_MNEM_SUFFIX
;
6070 else if (flag_code
== CODE_16BIT
6071 && (current_templates
->start
->opcode_modifier
6072 & (Jump
|JumpDword
|JumpInterSegment
)))
6073 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6074 else if (intel_parser
.got_a_float
== 1) /* "f..." */
6075 suffix
= SHORT_MNEM_SUFFIX
;
6077 suffix
= LONG_MNEM_SUFFIX
;
6080 else if (prev_token
.code
== T_FWORD
)
6082 if (current_templates
->start
->name
[0] == 'l'
6083 && current_templates
->start
->name
[2] == 's'
6084 && current_templates
->start
->name
[3] == 0)
6085 suffix
= LONG_MNEM_SUFFIX
;
6086 else if (!intel_parser
.got_a_float
)
6088 if (flag_code
== CODE_16BIT
)
6089 add_prefix (DATA_PREFIX_OPCODE
);
6090 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6093 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6096 else if (prev_token
.code
== T_QWORD
)
6098 if (intel_parser
.got_a_float
== 1) /* "f..." */
6099 suffix
= LONG_MNEM_SUFFIX
;
6101 suffix
= QWORD_MNEM_SUFFIX
;
6104 else if (prev_token
.code
== T_TBYTE
)
6106 if (intel_parser
.got_a_float
== 1)
6107 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6109 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6112 else if (prev_token
.code
== T_XMMWORD
)
6114 /* XXX ignored for now, but accepted since gcc uses it */
6120 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
6124 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
6128 else if (i
.suffix
!= suffix
)
6130 as_bad (_("Conflicting operand modifiers"));
6136 /* e09' : e10 e09' */
6137 else if (cur_token
.code
== ':')
6139 if (prev_token
.code
!= T_REG
)
6141 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6142 segment/group identifier (which we don't have), using comma
6143 as the operand separator there is even less consistent, since
6144 there all branches only have a single operand. */
6145 if (this_operand
!= 0
6146 || intel_parser
.in_offset
6147 || intel_parser
.in_bracket
6148 || (!(current_templates
->start
->opcode_modifier
6149 & (Jump
|JumpDword
|JumpInterSegment
))
6150 && !(current_templates
->start
->operand_types
[0]
6152 return intel_match_token (T_NIL
);
6153 /* Remember the start of the 2nd operand and terminate 1st
6155 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6156 another expression), but it gets at least the simplest case
6157 (a plain number or symbol on the left side) right. */
6158 intel_parser
.next_operand
= intel_parser
.op_string
;
6159 *--intel_parser
.op_string
= '\0';
6160 return intel_match_token (':');
6168 intel_match_token (cur_token
.code
);
6174 --intel_parser
.in_offset
;
6177 if (NUM_ADDRESS_REGS
> nregs
)
6179 as_bad (_("Invalid operand to `OFFSET'"));
6182 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
6185 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6186 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
6191 intel_bracket_expr ()
6193 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
6194 const char *start
= intel_parser
.op_string
;
6197 if (i
.op
[this_operand
].regs
)
6198 return intel_match_token (T_NIL
);
6200 intel_match_token ('[');
6202 /* Mark as a memory operand only if it's not already known to be an
6203 offset expression. If it's an offset expression, we need to keep
6205 if (!intel_parser
.in_offset
)
6207 ++intel_parser
.in_bracket
;
6208 /* Unfortunately gas always diverged from MASM in a respect that can't
6209 be easily fixed without risking to break code sequences likely to be
6210 encountered (the testsuite even check for this): MASM doesn't consider
6211 an expression inside brackets unconditionally as a memory reference.
6212 When that is e.g. a constant, an offset expression, or the sum of the
6213 two, this is still taken as a constant load. gas, however, always
6214 treated these as memory references. As a compromise, we'll try to make
6215 offset expressions inside brackets work the MASM way (since that's
6216 less likely to be found in real world code), but make constants alone
6217 continue to work the traditional gas way. In either case, issue a
6219 intel_parser
.op_modifier
&= ~was_offset
;
6222 strcat (intel_parser
.disp
, "[");
6224 /* Add a '+' to the displacement string if necessary. */
6225 if (*intel_parser
.disp
!= '\0'
6226 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
6227 strcat (intel_parser
.disp
, "+");
6230 && (len
= intel_parser
.op_string
- start
- 1,
6231 intel_match_token (']')))
6233 /* Preserve brackets when the operand is an offset expression. */
6234 if (intel_parser
.in_offset
)
6235 strcat (intel_parser
.disp
, "]");
6238 --intel_parser
.in_bracket
;
6239 if (i
.base_reg
|| i
.index_reg
)
6240 intel_parser
.is_mem
= 1;
6241 if (!intel_parser
.is_mem
)
6243 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
6244 /* Defer the warning until all of the operand was parsed. */
6245 intel_parser
.is_mem
= -1;
6246 else if (!quiet_warnings
)
6247 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len
, start
, len
, start
);
6250 intel_parser
.op_modifier
|= was_offset
;
6267 while (cur_token
.code
== '[')
6269 if (!intel_bracket_expr ())
6294 switch (cur_token
.code
)
6298 intel_match_token ('(');
6299 strcat (intel_parser
.disp
, "(");
6301 if (intel_expr () && intel_match_token (')'))
6303 strcat (intel_parser
.disp
, ")");
6310 /* Operands for jump/call inside brackets denote absolute addresses.
6311 XXX This shouldn't be needed anymore (or if it should rather live
6312 in intel_bracket_expr). */
6313 if (current_templates
->start
->opcode_modifier
6314 & (Jump
|JumpDword
|JumpByte
|JumpInterSegment
))
6315 i
.types
[this_operand
] |= JumpAbsolute
;
6317 return intel_bracket_expr ();
6322 strcat (intel_parser
.disp
, cur_token
.str
);
6323 intel_match_token (cur_token
.code
);
6325 /* Mark as a memory operand only if it's not already known to be an
6326 offset expression. */
6327 if (!intel_parser
.in_offset
)
6328 intel_parser
.is_mem
= 1;
6335 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
6337 intel_match_token (T_REG
);
6339 /* Check for segment change. */
6340 if (cur_token
.code
== ':')
6342 if (!(reg
->reg_type
& (SReg2
| SReg3
)))
6344 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
6347 else if (i
.seg
[i
.mem_operands
])
6348 as_warn (_("Extra segment override ignored"));
6351 if (!intel_parser
.in_offset
)
6352 intel_parser
.is_mem
= 1;
6353 switch (reg
->reg_num
)
6356 i
.seg
[i
.mem_operands
] = &es
;
6359 i
.seg
[i
.mem_operands
] = &cs
;
6362 i
.seg
[i
.mem_operands
] = &ss
;
6365 i
.seg
[i
.mem_operands
] = &ds
;
6368 i
.seg
[i
.mem_operands
] = &fs
;
6371 i
.seg
[i
.mem_operands
] = &gs
;
6377 /* Not a segment register. Check for register scaling. */
6378 else if (cur_token
.code
== '*')
6380 if (!intel_parser
.in_bracket
)
6382 as_bad (_("Register scaling only allowed in memory operands"));
6386 if (reg
->reg_type
& Reg16
) /* Disallow things like [si*1]. */
6387 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
6388 else if (i
.index_reg
)
6389 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
6391 /* What follows must be a valid scale. */
6392 intel_match_token ('*');
6394 i
.types
[this_operand
] |= BaseIndex
;
6396 /* Set the scale after setting the register (otherwise,
6397 i386_scale will complain) */
6398 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6400 char *str
, sign
= cur_token
.code
;
6401 intel_match_token (cur_token
.code
);
6402 if (cur_token
.code
!= T_CONST
)
6404 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6408 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
6409 strcpy (str
+ 1, cur_token
.str
);
6411 if (!i386_scale (str
))
6415 else if (!i386_scale (cur_token
.str
))
6417 intel_match_token (cur_token
.code
);
6420 /* No scaling. If this is a memory operand, the register is either a
6421 base register (first occurrence) or an index register (second
6423 else if (intel_parser
.in_bracket
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
6428 else if (!i
.index_reg
)
6432 as_bad (_("Too many register references in memory operand"));
6436 i
.types
[this_operand
] |= BaseIndex
;
6439 /* Offset modifier. Add the register to the displacement string to be
6440 parsed as an immediate expression after we're done. */
6441 else if (intel_parser
.in_offset
)
6443 as_warn (_("Using register names in OFFSET expressions is deprecated"));
6444 strcat (intel_parser
.disp
, reg
->reg_name
);
6447 /* It's neither base nor index nor offset. */
6448 else if (!intel_parser
.is_mem
)
6450 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
6451 i
.op
[this_operand
].regs
= reg
;
6456 as_bad (_("Invalid use of register"));
6460 /* Since registers are not part of the displacement string (except
6461 when we're parsing offset operands), we may need to remove any
6462 preceding '+' from the displacement string. */
6463 if (*intel_parser
.disp
!= '\0'
6464 && !intel_parser
.in_offset
)
6466 char *s
= intel_parser
.disp
;
6467 s
+= strlen (s
) - 1;
6490 intel_match_token (cur_token
.code
);
6492 if (cur_token
.code
== T_PTR
)
6495 /* It must have been an identifier. */
6496 intel_putback_token ();
6497 cur_token
.code
= T_ID
;
6503 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
6507 /* The identifier represents a memory reference only if it's not
6508 preceded by an offset modifier and if it's not an equate. */
6509 symbolP
= symbol_find(cur_token
.str
);
6510 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
6511 intel_parser
.is_mem
= 1;
6519 char *save_str
, sign
= 0;
6521 /* Allow constants that start with `+' or `-'. */
6522 if (cur_token
.code
== '-' || cur_token
.code
== '+')
6524 sign
= cur_token
.code
;
6525 intel_match_token (cur_token
.code
);
6526 if (cur_token
.code
!= T_CONST
)
6528 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6534 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
6535 strcpy (save_str
+ !!sign
, cur_token
.str
);
6539 /* Get the next token to check for register scaling. */
6540 intel_match_token (cur_token
.code
);
6542 /* Check if this constant is a scaling factor for an index register. */
6543 if (cur_token
.code
== '*')
6545 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
6547 const reg_entry
*reg
= cur_token
.reg
;
6549 if (!intel_parser
.in_bracket
)
6551 as_bad (_("Register scaling only allowed in memory operands"));
6555 if (reg
->reg_type
& Reg16
) /* Disallow things like [1*si]. */
6556 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
6557 else if (i
.index_reg
)
6558 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
6560 /* The constant is followed by `* reg', so it must be
6563 i
.types
[this_operand
] |= BaseIndex
;
6565 /* Set the scale after setting the register (otherwise,
6566 i386_scale will complain) */
6567 if (!i386_scale (save_str
))
6569 intel_match_token (T_REG
);
6571 /* Since registers are not part of the displacement
6572 string, we may need to remove any preceding '+' from
6573 the displacement string. */
6574 if (*intel_parser
.disp
!= '\0')
6576 char *s
= intel_parser
.disp
;
6577 s
+= strlen (s
) - 1;
6587 /* The constant was not used for register scaling. Since we have
6588 already consumed the token following `*' we now need to put it
6589 back in the stream. */
6590 intel_putback_token ();
6593 /* Add the constant to the displacement string. */
6594 strcat (intel_parser
.disp
, save_str
);
6601 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
6605 /* Match the given token against cur_token. If they match, read the next
6606 token from the operand string. */
6608 intel_match_token (code
)
6611 if (cur_token
.code
== code
)
6618 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
6623 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6628 const reg_entry
*reg
;
6629 struct intel_token new_token
;
6631 new_token
.code
= T_NIL
;
6632 new_token
.reg
= NULL
;
6633 new_token
.str
= NULL
;
6635 /* Free the memory allocated to the previous token and move
6636 cur_token to prev_token. */
6638 free (prev_token
.str
);
6640 prev_token
= cur_token
;
6642 /* Skip whitespace. */
6643 while (is_space_char (*intel_parser
.op_string
))
6644 intel_parser
.op_string
++;
6646 /* Return an empty token if we find nothing else on the line. */
6647 if (*intel_parser
.op_string
== '\0')
6649 cur_token
= new_token
;
6653 /* The new token cannot be larger than the remainder of the operand
6655 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
6656 new_token
.str
[0] = '\0';
6658 if (strchr ("0123456789", *intel_parser
.op_string
))
6660 char *p
= new_token
.str
;
6661 char *q
= intel_parser
.op_string
;
6662 new_token
.code
= T_CONST
;
6664 /* Allow any kind of identifier char to encompass floating point and
6665 hexadecimal numbers. */
6666 while (is_identifier_char (*q
))
6670 /* Recognize special symbol names [0-9][bf]. */
6671 if (strlen (intel_parser
.op_string
) == 2
6672 && (intel_parser
.op_string
[1] == 'b'
6673 || intel_parser
.op_string
[1] == 'f'))
6674 new_token
.code
= T_ID
;
6677 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6678 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
6680 new_token
.code
= T_REG
;
6681 new_token
.reg
= reg
;
6683 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
6685 new_token
.str
[0] = REGISTER_PREFIX
;
6686 new_token
.str
[1] = '\0';
6689 strcat (new_token
.str
, reg
->reg_name
);
6692 else if (is_identifier_char (*intel_parser
.op_string
))
6694 char *p
= new_token
.str
;
6695 char *q
= intel_parser
.op_string
;
6697 /* A '.' or '$' followed by an identifier char is an identifier.
6698 Otherwise, it's operator '.' followed by an expression. */
6699 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
6701 new_token
.code
= '.';
6702 new_token
.str
[0] = '.';
6703 new_token
.str
[1] = '\0';
6707 while (is_identifier_char (*q
) || *q
== '@')
6711 if (strcasecmp (new_token
.str
, "NOT") == 0)
6712 new_token
.code
= '~';
6714 else if (strcasecmp (new_token
.str
, "MOD") == 0)
6715 new_token
.code
= '%';
6717 else if (strcasecmp (new_token
.str
, "AND") == 0)
6718 new_token
.code
= '&';
6720 else if (strcasecmp (new_token
.str
, "OR") == 0)
6721 new_token
.code
= '|';
6723 else if (strcasecmp (new_token
.str
, "XOR") == 0)
6724 new_token
.code
= '^';
6726 else if (strcasecmp (new_token
.str
, "SHL") == 0)
6727 new_token
.code
= T_SHL
;
6729 else if (strcasecmp (new_token
.str
, "SHR") == 0)
6730 new_token
.code
= T_SHR
;
6732 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
6733 new_token
.code
= T_BYTE
;
6735 else if (strcasecmp (new_token
.str
, "WORD") == 0)
6736 new_token
.code
= T_WORD
;
6738 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
6739 new_token
.code
= T_DWORD
;
6741 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
6742 new_token
.code
= T_FWORD
;
6744 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
6745 new_token
.code
= T_QWORD
;
6747 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
6748 /* XXX remove (gcc still uses it) */
6749 || strcasecmp (new_token
.str
, "XWORD") == 0)
6750 new_token
.code
= T_TBYTE
;
6752 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
6753 || strcasecmp (new_token
.str
, "OWORD") == 0)
6754 new_token
.code
= T_XMMWORD
;
6756 else if (strcasecmp (new_token
.str
, "PTR") == 0)
6757 new_token
.code
= T_PTR
;
6759 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
6760 new_token
.code
= T_SHORT
;
6762 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
6764 new_token
.code
= T_OFFSET
;
6766 /* ??? This is not mentioned in the MASM grammar but gcc
6767 makes use of it with -mintel-syntax. OFFSET may be
6768 followed by FLAT: */
6769 if (strncasecmp (q
, " FLAT:", 6) == 0)
6770 strcat (new_token
.str
, " FLAT:");
6773 /* ??? This is not mentioned in the MASM grammar. */
6774 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
6776 new_token
.code
= T_OFFSET
;
6778 strcat (new_token
.str
, ":");
6780 as_bad (_("`:' expected"));
6784 new_token
.code
= T_ID
;
6788 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
6790 new_token
.code
= *intel_parser
.op_string
;
6791 new_token
.str
[0] = *intel_parser
.op_string
;
6792 new_token
.str
[1] = '\0';
6795 else if (strchr ("<>", *intel_parser
.op_string
)
6796 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
6798 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
6799 new_token
.str
[0] = *intel_parser
.op_string
;
6800 new_token
.str
[1] = *intel_parser
.op_string
;
6801 new_token
.str
[2] = '\0';
6805 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
6807 intel_parser
.op_string
+= strlen (new_token
.str
);
6808 cur_token
= new_token
;
6811 /* Put cur_token back into the token stream and make cur_token point to
6814 intel_putback_token ()
6816 if (cur_token
.code
!= T_NIL
)
6818 intel_parser
.op_string
-= strlen (cur_token
.str
);
6819 free (cur_token
.str
);
6821 cur_token
= prev_token
;
6823 /* Forget prev_token. */
6824 prev_token
.code
= T_NIL
;
6825 prev_token
.reg
= NULL
;
6826 prev_token
.str
= NULL
;
6830 tc_x86_regname_to_dw2regnum (const char *regname
)
6832 unsigned int regnum
;
6833 unsigned int regnames_count
;
6834 static const char *const regnames_32
[] =
6836 "eax", "ecx", "edx", "ebx",
6837 "esp", "ebp", "esi", "edi",
6838 "eip", "eflags", NULL
,
6839 "st0", "st1", "st2", "st3",
6840 "st4", "st5", "st6", "st7",
6842 "xmm0", "xmm1", "xmm2", "xmm3",
6843 "xmm4", "xmm5", "xmm6", "xmm7",
6844 "mm0", "mm1", "mm2", "mm3",
6845 "mm4", "mm5", "mm6", "mm7"
6847 static const char *const regnames_64
[] =
6849 "rax", "rdx", "rcx", "rbx",
6850 "rsi", "rdi", "rbp", "rsp",
6851 "r8", "r9", "r10", "r11",
6852 "r12", "r13", "r14", "r15",
6854 "xmm0", "xmm1", "xmm2", "xmm3",
6855 "xmm4", "xmm5", "xmm6", "xmm7",
6856 "xmm8", "xmm9", "xmm10", "xmm11",
6857 "xmm12", "xmm13", "xmm14", "xmm15",
6858 "st0", "st1", "st2", "st3",
6859 "st4", "st5", "st6", "st7",
6860 "mm0", "mm1", "mm2", "mm3",
6861 "mm4", "mm5", "mm6", "mm7"
6863 const char *const *regnames
;
6865 if (flag_code
== CODE_64BIT
)
6867 regnames
= regnames_64
;
6868 regnames_count
= ARRAY_SIZE (regnames_64
);
6872 regnames
= regnames_32
;
6873 regnames_count
= ARRAY_SIZE (regnames_32
);
6876 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
6877 if (regnames
[regnum
] != NULL
6878 && strcmp (regname
, regnames
[regnum
]) == 0)
6885 tc_x86_frame_initial_instructions (void)
6887 static unsigned int sp_regno
;
6890 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
6893 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
6894 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
6898 i386_elf_section_type (const char *str
, size_t len
)
6900 if (flag_code
== CODE_64BIT
6901 && len
== sizeof ("unwind") - 1
6902 && strncmp (str
, "unwind", 6) == 0)
6903 return SHT_X86_64_UNWIND
;
6910 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
6914 expr
.X_op
= O_secrel
;
6915 expr
.X_add_symbol
= symbol
;
6916 expr
.X_add_number
= 0;
6917 emit_expr (&expr
, size
);