1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* parse_register() returns this when a register alias cannot be used. */
214 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
215 { Dw2Inval
, Dw2Inval
} };
217 /* This struct describes rounding control and SAE in the instruction. */
231 static struct RC_Operation rc_op
;
233 /* The struct describes masking, applied to OPERAND in the instruction.
234 MASK is a pointer to the corresponding mask register. ZEROING tells
235 whether merging or zeroing mask is used. */
236 struct Mask_Operation
238 const reg_entry
*mask
;
239 unsigned int zeroing
;
240 /* The operand where this operation is associated. */
244 static struct Mask_Operation mask_op
;
246 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
248 struct Broadcast_Operation
250 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
253 /* Index of broadcasted operand. */
256 /* Number of bytes to broadcast. */
260 static struct Broadcast_Operation broadcast_op
;
265 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
266 unsigned char bytes
[4];
268 /* Destination or source register specifier. */
269 const reg_entry
*register_specifier
;
272 /* 'md_assemble ()' gathers together information and puts it into a
279 const reg_entry
*regs
;
284 operand_size_mismatch
,
285 operand_type_mismatch
,
286 register_type_mismatch
,
287 number_of_operands_mismatch
,
288 invalid_instruction_suffix
,
290 unsupported_with_intel_mnemonic
,
294 invalid_vsib_address
,
295 invalid_vector_register_set
,
296 invalid_tmm_register_set
,
297 unsupported_vector_index_register
,
298 unsupported_broadcast
,
301 mask_not_on_destination
,
304 rc_sae_operand_not_last_imm
,
305 invalid_register_operand
,
310 /* TM holds the template for the insn were currently assembling. */
313 /* SUFFIX holds the instruction size suffix for byte, word, dword
314 or qword, if given. */
317 /* OPERANDS gives the number of given operands. */
318 unsigned int operands
;
320 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
321 of given register, displacement, memory operands and immediate
323 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
325 /* TYPES [i] is the type (see above #defines) which tells us how to
326 use OP[i] for the corresponding operand. */
327 i386_operand_type types
[MAX_OPERANDS
];
329 /* Displacement expression, immediate expression, or register for each
331 union i386_op op
[MAX_OPERANDS
];
333 /* Flags for operands. */
334 unsigned int flags
[MAX_OPERANDS
];
335 #define Operand_PCrel 1
336 #define Operand_Mem 2
338 /* Relocation type for operand */
339 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
341 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
342 the base index byte below. */
343 const reg_entry
*base_reg
;
344 const reg_entry
*index_reg
;
345 unsigned int log2_scale_factor
;
347 /* SEG gives the seg_entries of this insn. They are zero unless
348 explicit segment overrides are given. */
349 const seg_entry
*seg
[2];
351 /* Copied first memory operand string, for re-checking. */
354 /* PREFIX holds all the given prefix opcodes (usually null).
355 PREFIXES is the number of prefix opcodes. */
356 unsigned int prefixes
;
357 unsigned char prefix
[MAX_PREFIXES
];
359 /* Register is in low 3 bits of opcode. */
360 bfd_boolean short_form
;
362 /* The operand to a branch insn indicates an absolute branch. */
363 bfd_boolean jumpabsolute
;
365 /* Extended states. */
373 xstate_ymm
= 1 << 2 | xstate_xmm
,
375 xstate_zmm
= 1 << 3 | xstate_ymm
,
380 /* Has GOTPC or TLS relocation. */
381 bfd_boolean has_gotpc_tls_reloc
;
383 /* RM and SIB are the modrm byte and the sib byte where the
384 addressing modes of this insn are encoded. */
391 /* Masking attributes. */
392 struct Mask_Operation
*mask
;
394 /* Rounding control and SAE attributes. */
395 struct RC_Operation
*rounding
;
397 /* Broadcasting attributes. */
398 struct Broadcast_Operation
*broadcast
;
400 /* Compressed disp8*N attribute. */
401 unsigned int memshift
;
403 /* Prefer load or store in encoding. */
406 dir_encoding_default
= 0,
412 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
415 disp_encoding_default
= 0,
421 /* Prefer the REX byte in encoding. */
422 bfd_boolean rex_encoding
;
424 /* Disable instruction size optimization. */
425 bfd_boolean no_optimize
;
427 /* How to encode vector instructions. */
430 vex_encoding_default
= 0,
438 const char *rep_prefix
;
441 const char *hle_prefix
;
443 /* Have BND prefix. */
444 const char *bnd_prefix
;
446 /* Have NOTRACK prefix. */
447 const char *notrack_prefix
;
450 enum i386_error error
;
453 typedef struct _i386_insn i386_insn
;
455 /* Link RC type with corresponding string, that'll be looked for in
464 static const struct RC_name RC_NamesTable
[] =
466 { rne
, STRING_COMMA_LEN ("rn-sae") },
467 { rd
, STRING_COMMA_LEN ("rd-sae") },
468 { ru
, STRING_COMMA_LEN ("ru-sae") },
469 { rz
, STRING_COMMA_LEN ("rz-sae") },
470 { saeonly
, STRING_COMMA_LEN ("sae") },
473 /* List of chars besides those in app.c:symbol_chars that can start an
474 operand. Used to prevent the scrubber eating vital white-space. */
475 const char extra_symbol_chars
[] = "*%-([{}"
484 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
485 && !defined (TE_GNU) \
486 && !defined (TE_LINUX) \
487 && !defined (TE_FreeBSD) \
488 && !defined (TE_DragonFly) \
489 && !defined (TE_NetBSD))
490 /* This array holds the chars that always start a comment. If the
491 pre-processor is disabled, these aren't very useful. The option
492 --divide will remove '/' from this list. */
493 const char *i386_comment_chars
= "#/";
494 #define SVR4_COMMENT_CHARS 1
495 #define PREFIX_SEPARATOR '\\'
498 const char *i386_comment_chars
= "#";
499 #define PREFIX_SEPARATOR '/'
502 /* This array holds the chars that only start a comment at the beginning of
503 a line. If the line seems to have the form '# 123 filename'
504 .line and .file directives will appear in the pre-processed output.
505 Note that input_file.c hand checks for '#' at the beginning of the
506 first line of the input file. This is because the compiler outputs
507 #NO_APP at the beginning of its output.
508 Also note that comments started like this one will always work if
509 '/' isn't otherwise defined. */
510 const char line_comment_chars
[] = "#/";
512 const char line_separator_chars
[] = ";";
514 /* Chars that can be used to separate mant from exp in floating point
516 const char EXP_CHARS
[] = "eE";
518 /* Chars that mean this number is a floating point constant
521 const char FLT_CHARS
[] = "fFdDxX";
523 /* Tables for lexical analysis. */
524 static char mnemonic_chars
[256];
525 static char register_chars
[256];
526 static char operand_chars
[256];
527 static char identifier_chars
[256];
528 static char digit_chars
[256];
530 /* Lexical macros. */
531 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
532 #define is_operand_char(x) (operand_chars[(unsigned char) x])
533 #define is_register_char(x) (register_chars[(unsigned char) x])
534 #define is_space_char(x) ((x) == ' ')
535 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
536 #define is_digit_char(x) (digit_chars[(unsigned char) x])
538 /* All non-digit non-letter characters that may occur in an operand. */
539 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
541 /* md_assemble() always leaves the strings it's passed unaltered. To
542 effect this we maintain a stack of saved characters that we've smashed
543 with '\0's (indicating end of strings for various sub-fields of the
544 assembler instruction). */
545 static char save_stack
[32];
546 static char *save_stack_p
;
547 #define END_STRING_AND_SAVE(s) \
548 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
549 #define RESTORE_END_STRING(s) \
550 do { *(s) = *--save_stack_p; } while (0)
552 /* The instruction we're assembling. */
555 /* Possible templates for current insn. */
556 static const templates
*current_templates
;
558 /* Per instruction expressionS buffers: max displacements & immediates. */
559 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
560 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
562 /* Current operand we are working on. */
563 static int this_operand
= -1;
565 /* We support four different modes. FLAG_CODE variable is used to distinguish
573 static enum flag_code flag_code
;
574 static unsigned int object_64bit
;
575 static unsigned int disallow_64bit_reloc
;
576 static int use_rela_relocations
= 0;
577 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
578 static const char *tls_get_addr
;
580 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
581 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
582 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
584 /* The ELF ABI to use. */
592 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
595 #if defined (TE_PE) || defined (TE_PEP)
596 /* Use big object file format. */
597 static int use_big_obj
= 0;
600 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
601 /* 1 if generating code for a shared library. */
602 static int shared
= 0;
605 /* 1 for intel syntax,
607 static int intel_syntax
= 0;
609 static enum x86_64_isa
611 amd64
= 1, /* AMD64 ISA. */
612 intel64
/* Intel64 ISA. */
615 /* 1 for intel mnemonic,
616 0 if att mnemonic. */
617 static int intel_mnemonic
= !SYSV386_COMPAT
;
619 /* 1 if pseudo registers are permitted. */
620 static int allow_pseudo_reg
= 0;
622 /* 1 if register prefix % not required. */
623 static int allow_naked_reg
= 0;
625 /* 1 if the assembler should add BND prefix for all control-transferring
626 instructions supporting it, even if this prefix wasn't specified
628 static int add_bnd_prefix
= 0;
630 /* 1 if pseudo index register, eiz/riz, is allowed . */
631 static int allow_index_reg
= 0;
633 /* 1 if the assembler should ignore LOCK prefix, even if it was
634 specified explicitly. */
635 static int omit_lock_prefix
= 0;
637 /* 1 if the assembler should encode lfence, mfence, and sfence as
638 "lock addl $0, (%{re}sp)". */
639 static int avoid_fence
= 0;
641 /* 1 if lfence should be inserted after every load. */
642 static int lfence_after_load
= 0;
644 /* Non-zero if lfence should be inserted before indirect branch. */
645 static enum lfence_before_indirect_branch_kind
647 lfence_branch_none
= 0,
648 lfence_branch_register
,
649 lfence_branch_memory
,
652 lfence_before_indirect_branch
;
654 /* Non-zero if lfence should be inserted before ret. */
655 static enum lfence_before_ret_kind
657 lfence_before_ret_none
= 0,
658 lfence_before_ret_not
,
659 lfence_before_ret_or
,
660 lfence_before_ret_shl
664 /* Types of previous instruction is .byte or prefix. */
679 /* 1 if the assembler should generate relax relocations. */
681 static int generate_relax_relocations
682 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
684 static enum check_kind
690 sse_check
, operand_check
= check_warning
;
692 /* Non-zero if branches should be aligned within power of 2 boundary. */
693 static int align_branch_power
= 0;
695 /* Types of branches to align. */
696 enum align_branch_kind
698 align_branch_none
= 0,
699 align_branch_jcc
= 1,
700 align_branch_fused
= 2,
701 align_branch_jmp
= 3,
702 align_branch_call
= 4,
703 align_branch_indirect
= 5,
707 /* Type bits of branches to align. */
708 enum align_branch_bit
710 align_branch_jcc_bit
= 1 << align_branch_jcc
,
711 align_branch_fused_bit
= 1 << align_branch_fused
,
712 align_branch_jmp_bit
= 1 << align_branch_jmp
,
713 align_branch_call_bit
= 1 << align_branch_call
,
714 align_branch_indirect_bit
= 1 << align_branch_indirect
,
715 align_branch_ret_bit
= 1 << align_branch_ret
718 static unsigned int align_branch
= (align_branch_jcc_bit
719 | align_branch_fused_bit
720 | align_branch_jmp_bit
);
722 /* Types of condition jump used by macro-fusion. */
725 mf_jcc_jo
= 0, /* base opcode 0x70 */
726 mf_jcc_jc
, /* base opcode 0x72 */
727 mf_jcc_je
, /* base opcode 0x74 */
728 mf_jcc_jna
, /* base opcode 0x76 */
729 mf_jcc_js
, /* base opcode 0x78 */
730 mf_jcc_jp
, /* base opcode 0x7a */
731 mf_jcc_jl
, /* base opcode 0x7c */
732 mf_jcc_jle
, /* base opcode 0x7e */
735 /* Types of compare flag-modifying insntructions used by macro-fusion. */
738 mf_cmp_test_and
, /* test/cmp */
739 mf_cmp_alu_cmp
, /* add/sub/cmp */
740 mf_cmp_incdec
/* inc/dec */
743 /* The maximum padding size for fused jcc. CMP like instruction can
744 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
746 #define MAX_FUSED_JCC_PADDING_SIZE 20
748 /* The maximum number of prefixes added for an instruction. */
749 static unsigned int align_branch_prefix_size
= 5;
752 1. Clear the REX_W bit with register operand if possible.
753 2. Above plus use 128bit vector instruction to clear the full vector
756 static int optimize
= 0;
759 1. Clear the REX_W bit with register operand if possible.
760 2. Above plus use 128bit vector instruction to clear the full vector
762 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
765 static int optimize_for_space
= 0;
767 /* Register prefix used for error message. */
768 static const char *register_prefix
= "%";
770 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
771 leave, push, and pop instructions so that gcc has the same stack
772 frame as in 32 bit mode. */
773 static char stackop_size
= '\0';
775 /* Non-zero to optimize code alignment. */
776 int optimize_align_code
= 1;
778 /* Non-zero to quieten some warnings. */
779 static int quiet_warnings
= 0;
782 static const char *cpu_arch_name
= NULL
;
783 static char *cpu_sub_arch_name
= NULL
;
785 /* CPU feature flags. */
786 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
788 /* If we have selected a cpu we are generating instructions for. */
789 static int cpu_arch_tune_set
= 0;
791 /* Cpu we are generating instructions for. */
792 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
794 /* CPU feature flags of cpu we are generating instructions for. */
795 static i386_cpu_flags cpu_arch_tune_flags
;
797 /* CPU instruction set architecture used. */
798 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
800 /* CPU feature flags of instruction set architecture used. */
801 i386_cpu_flags cpu_arch_isa_flags
;
803 /* If set, conditional jumps are not automatically promoted to handle
804 larger than a byte offset. */
805 static unsigned int no_cond_jump_promotion
= 0;
807 /* Encode SSE instructions with VEX prefix. */
808 static unsigned int sse2avx
;
810 /* Encode scalar AVX instructions with specific vector length. */
817 /* Encode VEX WIG instructions with specific vex.w. */
824 /* Encode scalar EVEX LIG instructions with specific vector length. */
832 /* Encode EVEX WIG instructions with specific evex.w. */
839 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
840 static enum rc_type evexrcig
= rne
;
842 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
843 static symbolS
*GOT_symbol
;
845 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
846 unsigned int x86_dwarf2_return_column
;
848 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
849 int x86_cie_data_alignment
;
851 /* Interface to relax_segment.
852 There are 3 major relax states for 386 jump insns because the
853 different types of jumps add different sizes to frags when we're
854 figuring out what sort of jump to choose to reach a given label.
856 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
857 branches which are handled by md_estimate_size_before_relax() and
858 i386_generic_table_relax_frag(). */
861 #define UNCOND_JUMP 0
863 #define COND_JUMP86 2
864 #define BRANCH_PADDING 3
865 #define BRANCH_PREFIX 4
866 #define FUSED_JCC_PADDING 5
871 #define SMALL16 (SMALL | CODE16)
873 #define BIG16 (BIG | CODE16)
877 #define INLINE __inline__
883 #define ENCODE_RELAX_STATE(type, size) \
884 ((relax_substateT) (((type) << 2) | (size)))
885 #define TYPE_FROM_RELAX_STATE(s) \
887 #define DISP_SIZE_FROM_RELAX_STATE(s) \
888 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
890 /* This table is used by relax_frag to promote short jumps to long
891 ones where necessary. SMALL (short) jumps may be promoted to BIG
892 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
893 don't allow a short jump in a 32 bit code segment to be promoted to
894 a 16 bit offset jump because it's slower (requires data size
895 prefix), and doesn't work, unless the destination is in the bottom
896 64k of the code segment (The top 16 bits of eip are zeroed). */
898 const relax_typeS md_relax_table
[] =
901 1) most positive reach of this state,
902 2) most negative reach of this state,
903 3) how many bytes this mode will have in the variable part of the frag
904 4) which index into the table to try if we can't fit into this one. */
906 /* UNCOND_JUMP states. */
907 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
908 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
909 /* dword jmp adds 4 bytes to frag:
910 0 extra opcode bytes, 4 displacement bytes. */
912 /* word jmp adds 2 byte2 to frag:
913 0 extra opcode bytes, 2 displacement bytes. */
916 /* COND_JUMP states. */
917 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
918 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
919 /* dword conditionals adds 5 bytes to frag:
920 1 extra opcode byte, 4 displacement bytes. */
922 /* word conditionals add 3 bytes to frag:
923 1 extra opcode byte, 2 displacement bytes. */
926 /* COND_JUMP86 states. */
927 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
928 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
929 /* dword conditionals adds 5 bytes to frag:
930 1 extra opcode byte, 4 displacement bytes. */
932 /* word conditionals add 4 bytes to frag:
933 1 displacement byte and a 3 byte long branch insn. */
937 static const arch_entry cpu_arch
[] =
939 /* Do not replace the first two entries - i386_target_format()
940 relies on them being there in this order. */
941 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
942 CPU_GENERIC32_FLAGS
, 0 },
943 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
944 CPU_GENERIC64_FLAGS
, 0 },
945 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
947 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
949 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
951 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
953 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
955 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
957 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
959 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
961 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
962 CPU_PENTIUMPRO_FLAGS
, 0 },
963 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
965 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
967 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
969 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
971 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
972 CPU_NOCONA_FLAGS
, 0 },
973 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
975 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
977 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
978 CPU_CORE2_FLAGS
, 1 },
979 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
980 CPU_CORE2_FLAGS
, 0 },
981 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
982 CPU_COREI7_FLAGS
, 0 },
983 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
985 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
987 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
988 CPU_IAMCU_FLAGS
, 0 },
989 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
991 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
993 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
994 CPU_ATHLON_FLAGS
, 0 },
995 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
997 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
999 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
1001 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
1002 CPU_AMDFAM10_FLAGS
, 0 },
1003 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
1004 CPU_BDVER1_FLAGS
, 0 },
1005 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
1006 CPU_BDVER2_FLAGS
, 0 },
1007 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
1008 CPU_BDVER3_FLAGS
, 0 },
1009 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
1010 CPU_BDVER4_FLAGS
, 0 },
1011 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
1012 CPU_ZNVER1_FLAGS
, 0 },
1013 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
1014 CPU_ZNVER2_FLAGS
, 0 },
1015 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
1016 CPU_BTVER1_FLAGS
, 0 },
1017 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
1018 CPU_BTVER2_FLAGS
, 0 },
1019 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
1020 CPU_8087_FLAGS
, 0 },
1021 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
1023 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
1025 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
1027 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
1028 CPU_CMOV_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
1030 CPU_FXSR_FLAGS
, 0 },
1031 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1033 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1035 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1036 CPU_SSE2_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1038 CPU_SSE3_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1040 CPU_SSE4A_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1042 CPU_SSSE3_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1044 CPU_SSE4_1_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1046 CPU_SSE4_2_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1048 CPU_SSE4_2_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1051 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1052 CPU_AVX2_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1054 CPU_AVX512F_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1056 CPU_AVX512CD_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1058 CPU_AVX512ER_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1060 CPU_AVX512PF_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1062 CPU_AVX512DQ_FLAGS
, 0 },
1063 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1064 CPU_AVX512BW_FLAGS
, 0 },
1065 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1066 CPU_AVX512VL_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1069 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1070 CPU_VMFUNC_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1073 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1074 CPU_XSAVE_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1076 CPU_XSAVEOPT_FLAGS
, 0 },
1077 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1078 CPU_XSAVEC_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1080 CPU_XSAVES_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1083 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1084 CPU_PCLMUL_FLAGS
, 0 },
1085 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1086 CPU_PCLMUL_FLAGS
, 1 },
1087 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1088 CPU_FSGSBASE_FLAGS
, 0 },
1089 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1090 CPU_RDRND_FLAGS
, 0 },
1091 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1092 CPU_F16C_FLAGS
, 0 },
1093 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1094 CPU_BMI2_FLAGS
, 0 },
1095 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1097 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1098 CPU_FMA4_FLAGS
, 0 },
1099 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1101 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1103 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1104 CPU_MOVBE_FLAGS
, 0 },
1105 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1106 CPU_CX16_FLAGS
, 0 },
1107 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1109 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1110 CPU_LZCNT_FLAGS
, 0 },
1111 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1112 CPU_POPCNT_FLAGS
, 0 },
1113 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1115 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1117 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1118 CPU_INVPCID_FLAGS
, 0 },
1119 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1120 CPU_CLFLUSH_FLAGS
, 0 },
1121 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1123 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1124 CPU_SYSCALL_FLAGS
, 0 },
1125 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1126 CPU_RDTSCP_FLAGS
, 0 },
1127 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1128 CPU_3DNOW_FLAGS
, 0 },
1129 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1130 CPU_3DNOWA_FLAGS
, 0 },
1131 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1132 CPU_PADLOCK_FLAGS
, 0 },
1133 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1134 CPU_SVME_FLAGS
, 1 },
1135 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1136 CPU_SVME_FLAGS
, 0 },
1137 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1138 CPU_SSE4A_FLAGS
, 0 },
1139 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1141 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1143 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1145 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1147 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1148 CPU_RDSEED_FLAGS
, 0 },
1149 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1150 CPU_PRFCHW_FLAGS
, 0 },
1151 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1152 CPU_SMAP_FLAGS
, 0 },
1153 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1155 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1157 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1158 CPU_CLFLUSHOPT_FLAGS
, 0 },
1159 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1160 CPU_PREFETCHWT1_FLAGS
, 0 },
1161 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1163 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1164 CPU_CLWB_FLAGS
, 0 },
1165 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1166 CPU_AVX512IFMA_FLAGS
, 0 },
1167 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1168 CPU_AVX512VBMI_FLAGS
, 0 },
1169 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1170 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1171 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1172 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1173 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1174 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1175 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1176 CPU_AVX512_VBMI2_FLAGS
, 0 },
1177 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1178 CPU_AVX512_VNNI_FLAGS
, 0 },
1179 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1180 CPU_AVX512_BITALG_FLAGS
, 0 },
1181 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1182 CPU_CLZERO_FLAGS
, 0 },
1183 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1184 CPU_MWAITX_FLAGS
, 0 },
1185 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1186 CPU_OSPKE_FLAGS
, 0 },
1187 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1188 CPU_RDPID_FLAGS
, 0 },
1189 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1190 CPU_PTWRITE_FLAGS
, 0 },
1191 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1193 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1194 CPU_SHSTK_FLAGS
, 0 },
1195 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1196 CPU_GFNI_FLAGS
, 0 },
1197 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1198 CPU_VAES_FLAGS
, 0 },
1199 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1200 CPU_VPCLMULQDQ_FLAGS
, 0 },
1201 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1202 CPU_WBNOINVD_FLAGS
, 0 },
1203 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1204 CPU_PCONFIG_FLAGS
, 0 },
1205 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1206 CPU_WAITPKG_FLAGS
, 0 },
1207 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1208 CPU_CLDEMOTE_FLAGS
, 0 },
1209 { STRING_COMMA_LEN (".amx_int8"), PROCESSOR_UNKNOWN
,
1210 CPU_AMX_INT8_FLAGS
, 0 },
1211 { STRING_COMMA_LEN (".amx_bf16"), PROCESSOR_UNKNOWN
,
1212 CPU_AMX_BF16_FLAGS
, 0 },
1213 { STRING_COMMA_LEN (".amx_tile"), PROCESSOR_UNKNOWN
,
1214 CPU_AMX_TILE_FLAGS
, 0 },
1215 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1216 CPU_MOVDIRI_FLAGS
, 0 },
1217 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1218 CPU_MOVDIR64B_FLAGS
, 0 },
1219 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1220 CPU_AVX512_BF16_FLAGS
, 0 },
1221 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1222 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1223 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1224 CPU_ENQCMD_FLAGS
, 0 },
1225 { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN
,
1226 CPU_SERIALIZE_FLAGS
, 0 },
1227 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1228 CPU_RDPRU_FLAGS
, 0 },
1229 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1230 CPU_MCOMMIT_FLAGS
, 0 },
1231 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN
,
1232 CPU_SEV_ES_FLAGS
, 0 },
1233 { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN
,
1234 CPU_TSXLDTRK_FLAGS
, 0 },
1237 static const noarch_entry cpu_noarch
[] =
1239 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1240 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1241 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1242 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1243 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1244 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1245 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1246 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1247 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1248 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1249 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1250 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1251 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1252 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1253 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1254 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1255 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1256 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1257 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1258 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1259 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1260 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1261 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1262 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1263 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1264 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1265 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1266 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1267 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1268 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1269 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1270 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1271 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1272 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1273 { STRING_COMMA_LEN ("noamx_int8"), CPU_ANY_AMX_INT8_FLAGS
},
1274 { STRING_COMMA_LEN ("noamx_bf16"), CPU_ANY_AMX_BF16_FLAGS
},
1275 { STRING_COMMA_LEN ("noamx_tile"), CPU_ANY_AMX_TILE_FLAGS
},
1276 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1277 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1278 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1279 { STRING_COMMA_LEN ("noavx512_vp2intersect"),
1280 CPU_ANY_AVX512_VP2INTERSECT_FLAGS
},
1281 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1282 { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS
},
1283 { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS
},
1287 /* Like s_lcomm_internal in gas/read.c but the alignment string
1288 is allowed to be optional. */
1291 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1298 && *input_line_pointer
== ',')
1300 align
= parse_align (needs_align
- 1);
1302 if (align
== (addressT
) -1)
1317 bss_alloc (symbolP
, size
, align
);
1322 pe_lcomm (int needs_align
)
1324 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1328 const pseudo_typeS md_pseudo_table
[] =
1330 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1331 {"align", s_align_bytes
, 0},
1333 {"align", s_align_ptwo
, 0},
1335 {"arch", set_cpu_arch
, 0},
1339 {"lcomm", pe_lcomm
, 1},
1341 {"ffloat", float_cons
, 'f'},
1342 {"dfloat", float_cons
, 'd'},
1343 {"tfloat", float_cons
, 'x'},
1345 {"slong", signed_cons
, 4},
1346 {"noopt", s_ignore
, 0},
1347 {"optim", s_ignore
, 0},
1348 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1349 {"code16", set_code_flag
, CODE_16BIT
},
1350 {"code32", set_code_flag
, CODE_32BIT
},
1352 {"code64", set_code_flag
, CODE_64BIT
},
1354 {"intel_syntax", set_intel_syntax
, 1},
1355 {"att_syntax", set_intel_syntax
, 0},
1356 {"intel_mnemonic", set_intel_mnemonic
, 1},
1357 {"att_mnemonic", set_intel_mnemonic
, 0},
1358 {"allow_index_reg", set_allow_index_reg
, 1},
1359 {"disallow_index_reg", set_allow_index_reg
, 0},
1360 {"sse_check", set_check
, 0},
1361 {"operand_check", set_check
, 1},
1362 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1363 {"largecomm", handle_large_common
, 0},
1365 {"file", dwarf2_directive_file
, 0},
1366 {"loc", dwarf2_directive_loc
, 0},
1367 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1370 {"secrel32", pe_directive_secrel
, 0},
1375 /* For interface with expression (). */
1376 extern char *input_line_pointer
;
1378 /* Hash table for instruction mnemonic lookup. */
1379 static struct hash_control
*op_hash
;
1381 /* Hash table for register lookup. */
1382 static struct hash_control
*reg_hash
;
1384 /* Various efficient no-op patterns for aligning code labels.
1385 Note: Don't try to assemble the instructions in the comments.
1386 0L and 0w are not legal. */
1387 static const unsigned char f32_1
[] =
1389 static const unsigned char f32_2
[] =
1390 {0x66,0x90}; /* xchg %ax,%ax */
1391 static const unsigned char f32_3
[] =
1392 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1393 static const unsigned char f32_4
[] =
1394 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1395 static const unsigned char f32_6
[] =
1396 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1397 static const unsigned char f32_7
[] =
1398 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1399 static const unsigned char f16_3
[] =
1400 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1401 static const unsigned char f16_4
[] =
1402 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1403 static const unsigned char jump_disp8
[] =
1404 {0xeb}; /* jmp disp8 */
1405 static const unsigned char jump32_disp32
[] =
1406 {0xe9}; /* jmp disp32 */
1407 static const unsigned char jump16_disp32
[] =
1408 {0x66,0xe9}; /* jmp disp32 */
1409 /* 32-bit NOPs patterns. */
1410 static const unsigned char *const f32_patt
[] = {
1411 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1413 /* 16-bit NOPs patterns. */
1414 static const unsigned char *const f16_patt
[] = {
1415 f32_1
, f32_2
, f16_3
, f16_4
1417 /* nopl (%[re]ax) */
1418 static const unsigned char alt_3
[] =
1420 /* nopl 0(%[re]ax) */
1421 static const unsigned char alt_4
[] =
1422 {0x0f,0x1f,0x40,0x00};
1423 /* nopl 0(%[re]ax,%[re]ax,1) */
1424 static const unsigned char alt_5
[] =
1425 {0x0f,0x1f,0x44,0x00,0x00};
1426 /* nopw 0(%[re]ax,%[re]ax,1) */
1427 static const unsigned char alt_6
[] =
1428 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1429 /* nopl 0L(%[re]ax) */
1430 static const unsigned char alt_7
[] =
1431 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1432 /* nopl 0L(%[re]ax,%[re]ax,1) */
1433 static const unsigned char alt_8
[] =
1434 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1435 /* nopw 0L(%[re]ax,%[re]ax,1) */
1436 static const unsigned char alt_9
[] =
1437 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1438 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1439 static const unsigned char alt_10
[] =
1440 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1441 /* data16 nopw %cs:0L(%eax,%eax,1) */
1442 static const unsigned char alt_11
[] =
1443 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1444 /* 32-bit and 64-bit NOPs patterns. */
1445 static const unsigned char *const alt_patt
[] = {
1446 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1447 alt_9
, alt_10
, alt_11
1450 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1451 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1454 i386_output_nops (char *where
, const unsigned char *const *patt
,
1455 int count
, int max_single_nop_size
)
1458 /* Place the longer NOP first. */
1461 const unsigned char *nops
;
1463 if (max_single_nop_size
< 1)
1465 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1466 max_single_nop_size
);
1470 nops
= patt
[max_single_nop_size
- 1];
1472 /* Use the smaller one if the requsted one isn't available. */
1475 max_single_nop_size
--;
1476 nops
= patt
[max_single_nop_size
- 1];
1479 last
= count
% max_single_nop_size
;
1482 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1483 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1487 nops
= patt
[last
- 1];
1490 /* Use the smaller one plus one-byte NOP if the needed one
1493 nops
= patt
[last
- 1];
1494 memcpy (where
+ offset
, nops
, last
);
1495 where
[offset
+ last
] = *patt
[0];
1498 memcpy (where
+ offset
, nops
, last
);
1503 fits_in_imm7 (offsetT num
)
1505 return (num
& 0x7f) == num
;
1509 fits_in_imm31 (offsetT num
)
1511 return (num
& 0x7fffffff) == num
;
1514 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1515 single NOP instruction LIMIT. */
1518 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1520 const unsigned char *const *patt
= NULL
;
1521 int max_single_nop_size
;
1522 /* Maximum number of NOPs before switching to jump over NOPs. */
1523 int max_number_of_nops
;
1525 switch (fragP
->fr_type
)
1530 case rs_machine_dependent
:
1531 /* Allow NOP padding for jumps and calls. */
1532 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1533 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1540 /* We need to decide which NOP sequence to use for 32bit and
1541 64bit. When -mtune= is used:
1543 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1544 PROCESSOR_GENERIC32, f32_patt will be used.
1545 2. For the rest, alt_patt will be used.
1547 When -mtune= isn't used, alt_patt will be used if
1548 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1551 When -march= or .arch is used, we can't use anything beyond
1552 cpu_arch_isa_flags. */
1554 if (flag_code
== CODE_16BIT
)
1557 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1558 /* Limit number of NOPs to 2 in 16-bit mode. */
1559 max_number_of_nops
= 2;
1563 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1565 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1566 switch (cpu_arch_tune
)
1568 case PROCESSOR_UNKNOWN
:
1569 /* We use cpu_arch_isa_flags to check if we SHOULD
1570 optimize with nops. */
1571 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1576 case PROCESSOR_PENTIUM4
:
1577 case PROCESSOR_NOCONA
:
1578 case PROCESSOR_CORE
:
1579 case PROCESSOR_CORE2
:
1580 case PROCESSOR_COREI7
:
1581 case PROCESSOR_L1OM
:
1582 case PROCESSOR_K1OM
:
1583 case PROCESSOR_GENERIC64
:
1585 case PROCESSOR_ATHLON
:
1587 case PROCESSOR_AMDFAM10
:
1589 case PROCESSOR_ZNVER
:
1593 case PROCESSOR_I386
:
1594 case PROCESSOR_I486
:
1595 case PROCESSOR_PENTIUM
:
1596 case PROCESSOR_PENTIUMPRO
:
1597 case PROCESSOR_IAMCU
:
1598 case PROCESSOR_GENERIC32
:
1605 switch (fragP
->tc_frag_data
.tune
)
1607 case PROCESSOR_UNKNOWN
:
1608 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1609 PROCESSOR_UNKNOWN. */
1613 case PROCESSOR_I386
:
1614 case PROCESSOR_I486
:
1615 case PROCESSOR_PENTIUM
:
1616 case PROCESSOR_IAMCU
:
1618 case PROCESSOR_ATHLON
:
1620 case PROCESSOR_AMDFAM10
:
1622 case PROCESSOR_ZNVER
:
1624 case PROCESSOR_GENERIC32
:
1625 /* We use cpu_arch_isa_flags to check if we CAN optimize
1627 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1632 case PROCESSOR_PENTIUMPRO
:
1633 case PROCESSOR_PENTIUM4
:
1634 case PROCESSOR_NOCONA
:
1635 case PROCESSOR_CORE
:
1636 case PROCESSOR_CORE2
:
1637 case PROCESSOR_COREI7
:
1638 case PROCESSOR_L1OM
:
1639 case PROCESSOR_K1OM
:
1640 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1645 case PROCESSOR_GENERIC64
:
1651 if (patt
== f32_patt
)
1653 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1654 /* Limit number of NOPs to 2 for older processors. */
1655 max_number_of_nops
= 2;
1659 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1660 /* Limit number of NOPs to 7 for newer processors. */
1661 max_number_of_nops
= 7;
1666 limit
= max_single_nop_size
;
1668 if (fragP
->fr_type
== rs_fill_nop
)
1670 /* Output NOPs for .nop directive. */
1671 if (limit
> max_single_nop_size
)
1673 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1674 _("invalid single nop size: %d "
1675 "(expect within [0, %d])"),
1676 limit
, max_single_nop_size
);
1680 else if (fragP
->fr_type
!= rs_machine_dependent
)
1681 fragP
->fr_var
= count
;
1683 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1685 /* Generate jump over NOPs. */
1686 offsetT disp
= count
- 2;
1687 if (fits_in_imm7 (disp
))
1689 /* Use "jmp disp8" if possible. */
1691 where
[0] = jump_disp8
[0];
1697 unsigned int size_of_jump
;
1699 if (flag_code
== CODE_16BIT
)
1701 where
[0] = jump16_disp32
[0];
1702 where
[1] = jump16_disp32
[1];
1707 where
[0] = jump32_disp32
[0];
1711 count
-= size_of_jump
+ 4;
1712 if (!fits_in_imm31 (count
))
1714 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1715 _("jump over nop padding out of range"));
1719 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1720 where
+= size_of_jump
+ 4;
1724 /* Generate multiple NOPs. */
1725 i386_output_nops (where
, patt
, count
, limit
);
1729 operand_type_all_zero (const union i386_operand_type
*x
)
1731 switch (ARRAY_SIZE(x
->array
))
1742 return !x
->array
[0];
1749 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1751 switch (ARRAY_SIZE(x
->array
))
1767 x
->bitfield
.class = ClassNone
;
1768 x
->bitfield
.instance
= InstanceNone
;
1772 operand_type_equal (const union i386_operand_type
*x
,
1773 const union i386_operand_type
*y
)
1775 switch (ARRAY_SIZE(x
->array
))
1778 if (x
->array
[2] != y
->array
[2])
1782 if (x
->array
[1] != y
->array
[1])
1786 return x
->array
[0] == y
->array
[0];
1794 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1796 switch (ARRAY_SIZE(x
->array
))
1811 return !x
->array
[0];
1818 cpu_flags_equal (const union i386_cpu_flags
*x
,
1819 const union i386_cpu_flags
*y
)
1821 switch (ARRAY_SIZE(x
->array
))
1824 if (x
->array
[3] != y
->array
[3])
1828 if (x
->array
[2] != y
->array
[2])
1832 if (x
->array
[1] != y
->array
[1])
1836 return x
->array
[0] == y
->array
[0];
1844 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1846 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1847 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1850 static INLINE i386_cpu_flags
1851 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1853 switch (ARRAY_SIZE (x
.array
))
1856 x
.array
[3] &= y
.array
[3];
1859 x
.array
[2] &= y
.array
[2];
1862 x
.array
[1] &= y
.array
[1];
1865 x
.array
[0] &= y
.array
[0];
1873 static INLINE i386_cpu_flags
1874 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1876 switch (ARRAY_SIZE (x
.array
))
1879 x
.array
[3] |= y
.array
[3];
1882 x
.array
[2] |= y
.array
[2];
1885 x
.array
[1] |= y
.array
[1];
1888 x
.array
[0] |= y
.array
[0];
1896 static INLINE i386_cpu_flags
1897 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1899 switch (ARRAY_SIZE (x
.array
))
1902 x
.array
[3] &= ~y
.array
[3];
1905 x
.array
[2] &= ~y
.array
[2];
1908 x
.array
[1] &= ~y
.array
[1];
1911 x
.array
[0] &= ~y
.array
[0];
1919 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1921 #define CPU_FLAGS_ARCH_MATCH 0x1
1922 #define CPU_FLAGS_64BIT_MATCH 0x2
1924 #define CPU_FLAGS_PERFECT_MATCH \
1925 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1927 /* Return CPU flags match bits. */
1930 cpu_flags_match (const insn_template
*t
)
1932 i386_cpu_flags x
= t
->cpu_flags
;
1933 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1935 x
.bitfield
.cpu64
= 0;
1936 x
.bitfield
.cpuno64
= 0;
1938 if (cpu_flags_all_zero (&x
))
1940 /* This instruction is available on all archs. */
1941 match
|= CPU_FLAGS_ARCH_MATCH
;
1945 /* This instruction is available only on some archs. */
1946 i386_cpu_flags cpu
= cpu_arch_flags
;
1948 /* AVX512VL is no standalone feature - match it and then strip it. */
1949 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1951 x
.bitfield
.cpuavx512vl
= 0;
1953 cpu
= cpu_flags_and (x
, cpu
);
1954 if (!cpu_flags_all_zero (&cpu
))
1956 if (x
.bitfield
.cpuavx
)
1958 /* We need to check a few extra flags with AVX. */
1959 if (cpu
.bitfield
.cpuavx
1960 && (!t
->opcode_modifier
.sse2avx
1961 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1962 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1963 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1964 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1965 match
|= CPU_FLAGS_ARCH_MATCH
;
1967 else if (x
.bitfield
.cpuavx512f
)
1969 /* We need to check a few extra flags with AVX512F. */
1970 if (cpu
.bitfield
.cpuavx512f
1971 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1972 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1973 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1974 match
|= CPU_FLAGS_ARCH_MATCH
;
1977 match
|= CPU_FLAGS_ARCH_MATCH
;
1983 static INLINE i386_operand_type
1984 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1986 if (x
.bitfield
.class != y
.bitfield
.class)
1987 x
.bitfield
.class = ClassNone
;
1988 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1989 x
.bitfield
.instance
= InstanceNone
;
1991 switch (ARRAY_SIZE (x
.array
))
1994 x
.array
[2] &= y
.array
[2];
1997 x
.array
[1] &= y
.array
[1];
2000 x
.array
[0] &= y
.array
[0];
2008 static INLINE i386_operand_type
2009 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
2011 gas_assert (y
.bitfield
.class == ClassNone
);
2012 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2014 switch (ARRAY_SIZE (x
.array
))
2017 x
.array
[2] &= ~y
.array
[2];
2020 x
.array
[1] &= ~y
.array
[1];
2023 x
.array
[0] &= ~y
.array
[0];
2031 static INLINE i386_operand_type
2032 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2034 gas_assert (x
.bitfield
.class == ClassNone
||
2035 y
.bitfield
.class == ClassNone
||
2036 x
.bitfield
.class == y
.bitfield
.class);
2037 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2038 y
.bitfield
.instance
== InstanceNone
||
2039 x
.bitfield
.instance
== y
.bitfield
.instance
);
2041 switch (ARRAY_SIZE (x
.array
))
2044 x
.array
[2] |= y
.array
[2];
2047 x
.array
[1] |= y
.array
[1];
2050 x
.array
[0] |= y
.array
[0];
2058 static INLINE i386_operand_type
2059 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2061 gas_assert (y
.bitfield
.class == ClassNone
);
2062 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2064 switch (ARRAY_SIZE (x
.array
))
2067 x
.array
[2] ^= y
.array
[2];
2070 x
.array
[1] ^= y
.array
[1];
2073 x
.array
[0] ^= y
.array
[0];
2081 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2082 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2083 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2084 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2085 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2086 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2087 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2088 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2089 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2090 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2091 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2092 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2093 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2094 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2095 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2096 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2097 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2108 operand_type_check (i386_operand_type t
, enum operand_type c
)
2113 return t
.bitfield
.class == Reg
;
2116 return (t
.bitfield
.imm8
2120 || t
.bitfield
.imm32s
2121 || t
.bitfield
.imm64
);
2124 return (t
.bitfield
.disp8
2125 || t
.bitfield
.disp16
2126 || t
.bitfield
.disp32
2127 || t
.bitfield
.disp32s
2128 || t
.bitfield
.disp64
);
2131 return (t
.bitfield
.disp8
2132 || t
.bitfield
.disp16
2133 || t
.bitfield
.disp32
2134 || t
.bitfield
.disp32s
2135 || t
.bitfield
.disp64
2136 || t
.bitfield
.baseindex
);
2145 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2146 between operand GIVEN and opeand WANTED for instruction template T. */
2149 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2152 return !((i
.types
[given
].bitfield
.byte
2153 && !t
->operand_types
[wanted
].bitfield
.byte
)
2154 || (i
.types
[given
].bitfield
.word
2155 && !t
->operand_types
[wanted
].bitfield
.word
)
2156 || (i
.types
[given
].bitfield
.dword
2157 && !t
->operand_types
[wanted
].bitfield
.dword
)
2158 || (i
.types
[given
].bitfield
.qword
2159 && !t
->operand_types
[wanted
].bitfield
.qword
)
2160 || (i
.types
[given
].bitfield
.tbyte
2161 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2164 /* Return 1 if there is no conflict in SIMD register between operand
2165 GIVEN and opeand WANTED for instruction template T. */
2168 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2171 return !((i
.types
[given
].bitfield
.xmmword
2172 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2173 || (i
.types
[given
].bitfield
.ymmword
2174 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2175 || (i
.types
[given
].bitfield
.zmmword
2176 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2177 || (i
.types
[given
].bitfield
.tmmword
2178 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2181 /* Return 1 if there is no conflict in any size between operand GIVEN
2182 and opeand WANTED for instruction template T. */
2185 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2188 return (match_operand_size (t
, wanted
, given
)
2189 && !((i
.types
[given
].bitfield
.unspecified
2191 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2192 || (i
.types
[given
].bitfield
.fword
2193 && !t
->operand_types
[wanted
].bitfield
.fword
)
2194 /* For scalar opcode templates to allow register and memory
2195 operands at the same time, some special casing is needed
2196 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2197 down-conversion vpmov*. */
2198 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2199 && t
->operand_types
[wanted
].bitfield
.byte
2200 + t
->operand_types
[wanted
].bitfield
.word
2201 + t
->operand_types
[wanted
].bitfield
.dword
2202 + t
->operand_types
[wanted
].bitfield
.qword
2203 > !!t
->opcode_modifier
.broadcast
)
2204 ? (i
.types
[given
].bitfield
.xmmword
2205 || i
.types
[given
].bitfield
.ymmword
2206 || i
.types
[given
].bitfield
.zmmword
)
2207 : !match_simd_size(t
, wanted
, given
))));
2210 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2211 operands for instruction template T, and it has MATCH_REVERSE set if there
2212 is no size conflict on any operands for the template with operands reversed
2213 (and the template allows for reversing in the first place). */
2215 #define MATCH_STRAIGHT 1
2216 #define MATCH_REVERSE 2
2218 static INLINE
unsigned int
2219 operand_size_match (const insn_template
*t
)
2221 unsigned int j
, match
= MATCH_STRAIGHT
;
2223 /* Don't check non-absolute jump instructions. */
2224 if (t
->opcode_modifier
.jump
2225 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2228 /* Check memory and accumulator operand size. */
2229 for (j
= 0; j
< i
.operands
; j
++)
2231 if (i
.types
[j
].bitfield
.class != Reg
2232 && i
.types
[j
].bitfield
.class != RegSIMD
2233 && t
->opcode_modifier
.anysize
)
2236 if (t
->operand_types
[j
].bitfield
.class == Reg
2237 && !match_operand_size (t
, j
, j
))
2243 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2244 && !match_simd_size (t
, j
, j
))
2250 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2251 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2257 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2264 if (!t
->opcode_modifier
.d
)
2268 i
.error
= operand_size_mismatch
;
2272 /* Check reverse. */
2273 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2275 for (j
= 0; j
< i
.operands
; j
++)
2277 unsigned int given
= i
.operands
- j
- 1;
2279 if (t
->operand_types
[j
].bitfield
.class == Reg
2280 && !match_operand_size (t
, j
, given
))
2283 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2284 && !match_simd_size (t
, j
, given
))
2287 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2288 && (!match_operand_size (t
, j
, given
)
2289 || !match_simd_size (t
, j
, given
)))
2292 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2296 return match
| MATCH_REVERSE
;
2300 operand_type_match (i386_operand_type overlap
,
2301 i386_operand_type given
)
2303 i386_operand_type temp
= overlap
;
2305 temp
.bitfield
.unspecified
= 0;
2306 temp
.bitfield
.byte
= 0;
2307 temp
.bitfield
.word
= 0;
2308 temp
.bitfield
.dword
= 0;
2309 temp
.bitfield
.fword
= 0;
2310 temp
.bitfield
.qword
= 0;
2311 temp
.bitfield
.tbyte
= 0;
2312 temp
.bitfield
.xmmword
= 0;
2313 temp
.bitfield
.ymmword
= 0;
2314 temp
.bitfield
.zmmword
= 0;
2315 temp
.bitfield
.tmmword
= 0;
2316 if (operand_type_all_zero (&temp
))
2319 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2323 i
.error
= operand_type_mismatch
;
2327 /* If given types g0 and g1 are registers they must be of the same type
2328 unless the expected operand type register overlap is null.
2329 Some Intel syntax memory operand size checking also happens here. */
2332 operand_type_register_match (i386_operand_type g0
,
2333 i386_operand_type t0
,
2334 i386_operand_type g1
,
2335 i386_operand_type t1
)
2337 if (g0
.bitfield
.class != Reg
2338 && g0
.bitfield
.class != RegSIMD
2339 && (!operand_type_check (g0
, anymem
)
2340 || g0
.bitfield
.unspecified
2341 || (t0
.bitfield
.class != Reg
2342 && t0
.bitfield
.class != RegSIMD
)))
2345 if (g1
.bitfield
.class != Reg
2346 && g1
.bitfield
.class != RegSIMD
2347 && (!operand_type_check (g1
, anymem
)
2348 || g1
.bitfield
.unspecified
2349 || (t1
.bitfield
.class != Reg
2350 && t1
.bitfield
.class != RegSIMD
)))
2353 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2354 && g0
.bitfield
.word
== g1
.bitfield
.word
2355 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2356 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2357 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2358 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2359 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2362 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2363 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2364 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2365 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2366 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2367 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2368 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2371 i
.error
= register_type_mismatch
;
2376 static INLINE
unsigned int
2377 register_number (const reg_entry
*r
)
2379 unsigned int nr
= r
->reg_num
;
2381 if (r
->reg_flags
& RegRex
)
2384 if (r
->reg_flags
& RegVRex
)
2390 static INLINE
unsigned int
2391 mode_from_disp_size (i386_operand_type t
)
2393 if (t
.bitfield
.disp8
)
2395 else if (t
.bitfield
.disp16
2396 || t
.bitfield
.disp32
2397 || t
.bitfield
.disp32s
)
2404 fits_in_signed_byte (addressT num
)
2406 return num
+ 0x80 <= 0xff;
2410 fits_in_unsigned_byte (addressT num
)
2416 fits_in_unsigned_word (addressT num
)
2418 return num
<= 0xffff;
2422 fits_in_signed_word (addressT num
)
2424 return num
+ 0x8000 <= 0xffff;
2428 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2433 return num
+ 0x80000000 <= 0xffffffff;
2435 } /* fits_in_signed_long() */
2438 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2443 return num
<= 0xffffffff;
2445 } /* fits_in_unsigned_long() */
2448 fits_in_disp8 (offsetT num
)
2450 int shift
= i
.memshift
;
2456 mask
= (1 << shift
) - 1;
2458 /* Return 0 if NUM isn't properly aligned. */
2462 /* Check if NUM will fit in 8bit after shift. */
2463 return fits_in_signed_byte (num
>> shift
);
2467 fits_in_imm4 (offsetT num
)
2469 return (num
& 0xf) == num
;
2472 static i386_operand_type
2473 smallest_imm_type (offsetT num
)
2475 i386_operand_type t
;
2477 operand_type_set (&t
, 0);
2478 t
.bitfield
.imm64
= 1;
2480 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2482 /* This code is disabled on the 486 because all the Imm1 forms
2483 in the opcode table are slower on the i486. They're the
2484 versions with the implicitly specified single-position
2485 displacement, which has another syntax if you really want to
2487 t
.bitfield
.imm1
= 1;
2488 t
.bitfield
.imm8
= 1;
2489 t
.bitfield
.imm8s
= 1;
2490 t
.bitfield
.imm16
= 1;
2491 t
.bitfield
.imm32
= 1;
2492 t
.bitfield
.imm32s
= 1;
2494 else if (fits_in_signed_byte (num
))
2496 t
.bitfield
.imm8
= 1;
2497 t
.bitfield
.imm8s
= 1;
2498 t
.bitfield
.imm16
= 1;
2499 t
.bitfield
.imm32
= 1;
2500 t
.bitfield
.imm32s
= 1;
2502 else if (fits_in_unsigned_byte (num
))
2504 t
.bitfield
.imm8
= 1;
2505 t
.bitfield
.imm16
= 1;
2506 t
.bitfield
.imm32
= 1;
2507 t
.bitfield
.imm32s
= 1;
2509 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2511 t
.bitfield
.imm16
= 1;
2512 t
.bitfield
.imm32
= 1;
2513 t
.bitfield
.imm32s
= 1;
2515 else if (fits_in_signed_long (num
))
2517 t
.bitfield
.imm32
= 1;
2518 t
.bitfield
.imm32s
= 1;
2520 else if (fits_in_unsigned_long (num
))
2521 t
.bitfield
.imm32
= 1;
2527 offset_in_range (offsetT val
, int size
)
2533 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2534 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2535 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2537 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2542 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2544 char buf1
[40], buf2
[40];
2546 sprint_value (buf1
, val
);
2547 sprint_value (buf2
, val
& mask
);
2548 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2563 a. PREFIX_EXIST if attempting to add a prefix where one from the
2564 same class already exists.
2565 b. PREFIX_LOCK if lock prefix is added.
2566 c. PREFIX_REP if rep/repne prefix is added.
2567 d. PREFIX_DS if ds prefix is added.
2568 e. PREFIX_OTHER if other prefix is added.
2571 static enum PREFIX_GROUP
2572 add_prefix (unsigned int prefix
)
2574 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2577 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2578 && flag_code
== CODE_64BIT
)
2580 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2581 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2582 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2583 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2594 case DS_PREFIX_OPCODE
:
2597 case CS_PREFIX_OPCODE
:
2598 case ES_PREFIX_OPCODE
:
2599 case FS_PREFIX_OPCODE
:
2600 case GS_PREFIX_OPCODE
:
2601 case SS_PREFIX_OPCODE
:
2605 case REPNE_PREFIX_OPCODE
:
2606 case REPE_PREFIX_OPCODE
:
2611 case LOCK_PREFIX_OPCODE
:
2620 case ADDR_PREFIX_OPCODE
:
2624 case DATA_PREFIX_OPCODE
:
2628 if (i
.prefix
[q
] != 0)
2636 i
.prefix
[q
] |= prefix
;
2639 as_bad (_("same type of prefix used twice"));
2645 update_code_flag (int value
, int check
)
2647 PRINTF_LIKE ((*as_error
));
2649 flag_code
= (enum flag_code
) value
;
2650 if (flag_code
== CODE_64BIT
)
2652 cpu_arch_flags
.bitfield
.cpu64
= 1;
2653 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2657 cpu_arch_flags
.bitfield
.cpu64
= 0;
2658 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2660 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2663 as_error
= as_fatal
;
2666 (*as_error
) (_("64bit mode not supported on `%s'."),
2667 cpu_arch_name
? cpu_arch_name
: default_arch
);
2669 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2672 as_error
= as_fatal
;
2675 (*as_error
) (_("32bit mode not supported on `%s'."),
2676 cpu_arch_name
? cpu_arch_name
: default_arch
);
2678 stackop_size
= '\0';
2682 set_code_flag (int value
)
2684 update_code_flag (value
, 0);
2688 set_16bit_gcc_code_flag (int new_code_flag
)
2690 flag_code
= (enum flag_code
) new_code_flag
;
2691 if (flag_code
!= CODE_16BIT
)
2693 cpu_arch_flags
.bitfield
.cpu64
= 0;
2694 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2695 stackop_size
= LONG_MNEM_SUFFIX
;
2699 set_intel_syntax (int syntax_flag
)
2701 /* Find out if register prefixing is specified. */
2702 int ask_naked_reg
= 0;
2705 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2708 int e
= get_symbol_name (&string
);
2710 if (strcmp (string
, "prefix") == 0)
2712 else if (strcmp (string
, "noprefix") == 0)
2715 as_bad (_("bad argument to syntax directive."));
2716 (void) restore_line_pointer (e
);
2718 demand_empty_rest_of_line ();
2720 intel_syntax
= syntax_flag
;
2722 if (ask_naked_reg
== 0)
2723 allow_naked_reg
= (intel_syntax
2724 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2726 allow_naked_reg
= (ask_naked_reg
< 0);
2728 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2730 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2731 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2732 register_prefix
= allow_naked_reg
? "" : "%";
2736 set_intel_mnemonic (int mnemonic_flag
)
2738 intel_mnemonic
= mnemonic_flag
;
2742 set_allow_index_reg (int flag
)
2744 allow_index_reg
= flag
;
2748 set_check (int what
)
2750 enum check_kind
*kind
;
2755 kind
= &operand_check
;
2766 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2769 int e
= get_symbol_name (&string
);
2771 if (strcmp (string
, "none") == 0)
2773 else if (strcmp (string
, "warning") == 0)
2774 *kind
= check_warning
;
2775 else if (strcmp (string
, "error") == 0)
2776 *kind
= check_error
;
2778 as_bad (_("bad argument to %s_check directive."), str
);
2779 (void) restore_line_pointer (e
);
2782 as_bad (_("missing argument for %s_check directive"), str
);
2784 demand_empty_rest_of_line ();
2788 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2789 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2791 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2792 static const char *arch
;
2794 /* Intel LIOM is only supported on ELF. */
2800 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2801 use default_arch. */
2802 arch
= cpu_arch_name
;
2804 arch
= default_arch
;
2807 /* If we are targeting Intel MCU, we must enable it. */
2808 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2809 || new_flag
.bitfield
.cpuiamcu
)
2812 /* If we are targeting Intel L1OM, we must enable it. */
2813 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2814 || new_flag
.bitfield
.cpul1om
)
2817 /* If we are targeting Intel K1OM, we must enable it. */
2818 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2819 || new_flag
.bitfield
.cpuk1om
)
2822 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2827 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2831 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2834 int e
= get_symbol_name (&string
);
2836 i386_cpu_flags flags
;
2838 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2840 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2842 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2846 cpu_arch_name
= cpu_arch
[j
].name
;
2847 cpu_sub_arch_name
= NULL
;
2848 cpu_arch_flags
= cpu_arch
[j
].flags
;
2849 if (flag_code
== CODE_64BIT
)
2851 cpu_arch_flags
.bitfield
.cpu64
= 1;
2852 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2856 cpu_arch_flags
.bitfield
.cpu64
= 0;
2857 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2859 cpu_arch_isa
= cpu_arch
[j
].type
;
2860 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2861 if (!cpu_arch_tune_set
)
2863 cpu_arch_tune
= cpu_arch_isa
;
2864 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2869 flags
= cpu_flags_or (cpu_arch_flags
,
2872 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2874 if (cpu_sub_arch_name
)
2876 char *name
= cpu_sub_arch_name
;
2877 cpu_sub_arch_name
= concat (name
,
2879 (const char *) NULL
);
2883 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2884 cpu_arch_flags
= flags
;
2885 cpu_arch_isa_flags
= flags
;
2889 = cpu_flags_or (cpu_arch_isa_flags
,
2891 (void) restore_line_pointer (e
);
2892 demand_empty_rest_of_line ();
2897 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2899 /* Disable an ISA extension. */
2900 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2901 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2903 flags
= cpu_flags_and_not (cpu_arch_flags
,
2904 cpu_noarch
[j
].flags
);
2905 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2907 if (cpu_sub_arch_name
)
2909 char *name
= cpu_sub_arch_name
;
2910 cpu_sub_arch_name
= concat (name
, string
,
2911 (const char *) NULL
);
2915 cpu_sub_arch_name
= xstrdup (string
);
2916 cpu_arch_flags
= flags
;
2917 cpu_arch_isa_flags
= flags
;
2919 (void) restore_line_pointer (e
);
2920 demand_empty_rest_of_line ();
2924 j
= ARRAY_SIZE (cpu_arch
);
2927 if (j
>= ARRAY_SIZE (cpu_arch
))
2928 as_bad (_("no such architecture: `%s'"), string
);
2930 *input_line_pointer
= e
;
2933 as_bad (_("missing cpu architecture"));
2935 no_cond_jump_promotion
= 0;
2936 if (*input_line_pointer
== ','
2937 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2942 ++input_line_pointer
;
2943 e
= get_symbol_name (&string
);
2945 if (strcmp (string
, "nojumps") == 0)
2946 no_cond_jump_promotion
= 1;
2947 else if (strcmp (string
, "jumps") == 0)
2950 as_bad (_("no such architecture modifier: `%s'"), string
);
2952 (void) restore_line_pointer (e
);
2955 demand_empty_rest_of_line ();
2958 enum bfd_architecture
2961 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2963 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2964 || flag_code
!= CODE_64BIT
)
2965 as_fatal (_("Intel L1OM is 64bit ELF only"));
2966 return bfd_arch_l1om
;
2968 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2970 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2971 || flag_code
!= CODE_64BIT
)
2972 as_fatal (_("Intel K1OM is 64bit ELF only"));
2973 return bfd_arch_k1om
;
2975 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2977 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2978 || flag_code
== CODE_64BIT
)
2979 as_fatal (_("Intel MCU is 32bit ELF only"));
2980 return bfd_arch_iamcu
;
2983 return bfd_arch_i386
;
2989 if (!strncmp (default_arch
, "x86_64", 6))
2991 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2993 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2994 || default_arch
[6] != '\0')
2995 as_fatal (_("Intel L1OM is 64bit ELF only"));
2996 return bfd_mach_l1om
;
2998 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
3000 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3001 || default_arch
[6] != '\0')
3002 as_fatal (_("Intel K1OM is 64bit ELF only"));
3003 return bfd_mach_k1om
;
3005 else if (default_arch
[6] == '\0')
3006 return bfd_mach_x86_64
;
3008 return bfd_mach_x64_32
;
3010 else if (!strcmp (default_arch
, "i386")
3011 || !strcmp (default_arch
, "iamcu"))
3013 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3015 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3016 as_fatal (_("Intel MCU is 32bit ELF only"));
3017 return bfd_mach_i386_iamcu
;
3020 return bfd_mach_i386_i386
;
3023 as_fatal (_("unknown architecture"));
3029 const char *hash_err
;
3031 /* Support pseudo prefixes like {disp32}. */
3032 lex_type
['{'] = LEX_BEGIN_NAME
;
3034 /* Initialize op_hash hash table. */
3035 op_hash
= hash_new ();
3038 const insn_template
*optab
;
3039 templates
*core_optab
;
3041 /* Setup for loop. */
3043 core_optab
= XNEW (templates
);
3044 core_optab
->start
= optab
;
3049 if (optab
->name
== NULL
3050 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3052 /* different name --> ship out current template list;
3053 add to hash table; & begin anew. */
3054 core_optab
->end
= optab
;
3055 hash_err
= hash_insert (op_hash
,
3057 (void *) core_optab
);
3060 as_fatal (_("can't hash %s: %s"),
3064 if (optab
->name
== NULL
)
3066 core_optab
= XNEW (templates
);
3067 core_optab
->start
= optab
;
3072 /* Initialize reg_hash hash table. */
3073 reg_hash
= hash_new ();
3075 const reg_entry
*regtab
;
3076 unsigned int regtab_size
= i386_regtab_size
;
3078 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3080 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
3082 as_fatal (_("can't hash %s: %s"),
3088 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3093 for (c
= 0; c
< 256; c
++)
3098 mnemonic_chars
[c
] = c
;
3099 register_chars
[c
] = c
;
3100 operand_chars
[c
] = c
;
3102 else if (ISLOWER (c
))
3104 mnemonic_chars
[c
] = c
;
3105 register_chars
[c
] = c
;
3106 operand_chars
[c
] = c
;
3108 else if (ISUPPER (c
))
3110 mnemonic_chars
[c
] = TOLOWER (c
);
3111 register_chars
[c
] = mnemonic_chars
[c
];
3112 operand_chars
[c
] = c
;
3114 else if (c
== '{' || c
== '}')
3116 mnemonic_chars
[c
] = c
;
3117 operand_chars
[c
] = c
;
3119 #ifdef SVR4_COMMENT_CHARS
3120 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3121 operand_chars
[c
] = c
;
3124 if (ISALPHA (c
) || ISDIGIT (c
))
3125 identifier_chars
[c
] = c
;
3128 identifier_chars
[c
] = c
;
3129 operand_chars
[c
] = c
;
3134 identifier_chars
['@'] = '@';
3137 identifier_chars
['?'] = '?';
3138 operand_chars
['?'] = '?';
3140 digit_chars
['-'] = '-';
3141 mnemonic_chars
['_'] = '_';
3142 mnemonic_chars
['-'] = '-';
3143 mnemonic_chars
['.'] = '.';
3144 identifier_chars
['_'] = '_';
3145 identifier_chars
['.'] = '.';
3147 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3148 operand_chars
[(unsigned char) *p
] = *p
;
3151 if (flag_code
== CODE_64BIT
)
3153 #if defined (OBJ_COFF) && defined (TE_PE)
3154 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3157 x86_dwarf2_return_column
= 16;
3159 x86_cie_data_alignment
= -8;
3163 x86_dwarf2_return_column
= 8;
3164 x86_cie_data_alignment
= -4;
3167 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3168 can be turned into BRANCH_PREFIX frag. */
3169 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3174 i386_print_statistics (FILE *file
)
3176 hash_print_statistics (file
, "i386 opcode", op_hash
);
3177 hash_print_statistics (file
, "i386 register", reg_hash
);
3182 /* Debugging routines for md_assemble. */
3183 static void pte (insn_template
*);
3184 static void pt (i386_operand_type
);
3185 static void pe (expressionS
*);
3186 static void ps (symbolS
*);
3189 pi (const char *line
, i386_insn
*x
)
3193 fprintf (stdout
, "%s: template ", line
);
3195 fprintf (stdout
, " address: base %s index %s scale %x\n",
3196 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3197 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3198 x
->log2_scale_factor
);
3199 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3200 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3201 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3202 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3203 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3204 (x
->rex
& REX_W
) != 0,
3205 (x
->rex
& REX_R
) != 0,
3206 (x
->rex
& REX_X
) != 0,
3207 (x
->rex
& REX_B
) != 0);
3208 for (j
= 0; j
< x
->operands
; j
++)
3210 fprintf (stdout
, " #%d: ", j
+ 1);
3212 fprintf (stdout
, "\n");
3213 if (x
->types
[j
].bitfield
.class == Reg
3214 || x
->types
[j
].bitfield
.class == RegMMX
3215 || x
->types
[j
].bitfield
.class == RegSIMD
3216 || x
->types
[j
].bitfield
.class == RegMask
3217 || x
->types
[j
].bitfield
.class == SReg
3218 || x
->types
[j
].bitfield
.class == RegCR
3219 || x
->types
[j
].bitfield
.class == RegDR
3220 || x
->types
[j
].bitfield
.class == RegTR
3221 || x
->types
[j
].bitfield
.class == RegBND
)
3222 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3223 if (operand_type_check (x
->types
[j
], imm
))
3225 if (operand_type_check (x
->types
[j
], disp
))
3226 pe (x
->op
[j
].disps
);
3231 pte (insn_template
*t
)
3234 fprintf (stdout
, " %d operands ", t
->operands
);
3235 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3236 if (t
->extension_opcode
!= None
)
3237 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3238 if (t
->opcode_modifier
.d
)
3239 fprintf (stdout
, "D");
3240 if (t
->opcode_modifier
.w
)
3241 fprintf (stdout
, "W");
3242 fprintf (stdout
, "\n");
3243 for (j
= 0; j
< t
->operands
; j
++)
3245 fprintf (stdout
, " #%d type ", j
+ 1);
3246 pt (t
->operand_types
[j
]);
3247 fprintf (stdout
, "\n");
3254 fprintf (stdout
, " operation %d\n", e
->X_op
);
3255 fprintf (stdout
, " add_number %ld (%lx)\n",
3256 (long) e
->X_add_number
, (long) e
->X_add_number
);
3257 if (e
->X_add_symbol
)
3259 fprintf (stdout
, " add_symbol ");
3260 ps (e
->X_add_symbol
);
3261 fprintf (stdout
, "\n");
3265 fprintf (stdout
, " op_symbol ");
3266 ps (e
->X_op_symbol
);
3267 fprintf (stdout
, "\n");
3274 fprintf (stdout
, "%s type %s%s",
3276 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3277 segment_name (S_GET_SEGMENT (s
)));
3280 static struct type_name
3282 i386_operand_type mask
;
3285 const type_names
[] =
3287 { OPERAND_TYPE_REG8
, "r8" },
3288 { OPERAND_TYPE_REG16
, "r16" },
3289 { OPERAND_TYPE_REG32
, "r32" },
3290 { OPERAND_TYPE_REG64
, "r64" },
3291 { OPERAND_TYPE_ACC8
, "acc8" },
3292 { OPERAND_TYPE_ACC16
, "acc16" },
3293 { OPERAND_TYPE_ACC32
, "acc32" },
3294 { OPERAND_TYPE_ACC64
, "acc64" },
3295 { OPERAND_TYPE_IMM8
, "i8" },
3296 { OPERAND_TYPE_IMM8
, "i8s" },
3297 { OPERAND_TYPE_IMM16
, "i16" },
3298 { OPERAND_TYPE_IMM32
, "i32" },
3299 { OPERAND_TYPE_IMM32S
, "i32s" },
3300 { OPERAND_TYPE_IMM64
, "i64" },
3301 { OPERAND_TYPE_IMM1
, "i1" },
3302 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3303 { OPERAND_TYPE_DISP8
, "d8" },
3304 { OPERAND_TYPE_DISP16
, "d16" },
3305 { OPERAND_TYPE_DISP32
, "d32" },
3306 { OPERAND_TYPE_DISP32S
, "d32s" },
3307 { OPERAND_TYPE_DISP64
, "d64" },
3308 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3309 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3310 { OPERAND_TYPE_CONTROL
, "control reg" },
3311 { OPERAND_TYPE_TEST
, "test reg" },
3312 { OPERAND_TYPE_DEBUG
, "debug reg" },
3313 { OPERAND_TYPE_FLOATREG
, "FReg" },
3314 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3315 { OPERAND_TYPE_SREG
, "SReg" },
3316 { OPERAND_TYPE_REGMMX
, "rMMX" },
3317 { OPERAND_TYPE_REGXMM
, "rXMM" },
3318 { OPERAND_TYPE_REGYMM
, "rYMM" },
3319 { OPERAND_TYPE_REGZMM
, "rZMM" },
3320 { OPERAND_TYPE_REGTMM
, "rTMM" },
3321 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3325 pt (i386_operand_type t
)
3328 i386_operand_type a
;
3330 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3332 a
= operand_type_and (t
, type_names
[j
].mask
);
3333 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3334 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3339 #endif /* DEBUG386 */
3341 static bfd_reloc_code_real_type
3342 reloc (unsigned int size
,
3345 bfd_reloc_code_real_type other
)
3347 if (other
!= NO_RELOC
)
3349 reloc_howto_type
*rel
;
3354 case BFD_RELOC_X86_64_GOT32
:
3355 return BFD_RELOC_X86_64_GOT64
;
3357 case BFD_RELOC_X86_64_GOTPLT64
:
3358 return BFD_RELOC_X86_64_GOTPLT64
;
3360 case BFD_RELOC_X86_64_PLTOFF64
:
3361 return BFD_RELOC_X86_64_PLTOFF64
;
3363 case BFD_RELOC_X86_64_GOTPC32
:
3364 other
= BFD_RELOC_X86_64_GOTPC64
;
3366 case BFD_RELOC_X86_64_GOTPCREL
:
3367 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3369 case BFD_RELOC_X86_64_TPOFF32
:
3370 other
= BFD_RELOC_X86_64_TPOFF64
;
3372 case BFD_RELOC_X86_64_DTPOFF32
:
3373 other
= BFD_RELOC_X86_64_DTPOFF64
;
3379 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3380 if (other
== BFD_RELOC_SIZE32
)
3383 other
= BFD_RELOC_SIZE64
;
3386 as_bad (_("there are no pc-relative size relocations"));
3392 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3393 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3396 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3398 as_bad (_("unknown relocation (%u)"), other
);
3399 else if (size
!= bfd_get_reloc_size (rel
))
3400 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3401 bfd_get_reloc_size (rel
),
3403 else if (pcrel
&& !rel
->pc_relative
)
3404 as_bad (_("non-pc-relative relocation for pc-relative field"));
3405 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3407 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3409 as_bad (_("relocated field and relocation type differ in signedness"));
3418 as_bad (_("there are no unsigned pc-relative relocations"));
3421 case 1: return BFD_RELOC_8_PCREL
;
3422 case 2: return BFD_RELOC_16_PCREL
;
3423 case 4: return BFD_RELOC_32_PCREL
;
3424 case 8: return BFD_RELOC_64_PCREL
;
3426 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3433 case 4: return BFD_RELOC_X86_64_32S
;
3438 case 1: return BFD_RELOC_8
;
3439 case 2: return BFD_RELOC_16
;
3440 case 4: return BFD_RELOC_32
;
3441 case 8: return BFD_RELOC_64
;
3443 as_bad (_("cannot do %s %u byte relocation"),
3444 sign
> 0 ? "signed" : "unsigned", size
);
3450 /* Here we decide which fixups can be adjusted to make them relative to
3451 the beginning of the section instead of the symbol. Basically we need
3452 to make sure that the dynamic relocations are done correctly, so in
3453 some cases we force the original symbol to be used. */
3456 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3458 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3462 /* Don't adjust pc-relative references to merge sections in 64-bit
3464 if (use_rela_relocations
3465 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3469 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3470 and changed later by validate_fix. */
3471 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3472 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3475 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3476 for size relocations. */
3477 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3478 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3479 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3480 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3481 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3482 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3483 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3484 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3485 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3486 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3487 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3488 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3489 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3490 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3491 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3492 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3493 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3494 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3495 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3496 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3497 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3498 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3499 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3500 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3501 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3502 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3503 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3504 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3505 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3506 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3507 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3514 intel_float_operand (const char *mnemonic
)
3516 /* Note that the value returned is meaningful only for opcodes with (memory)
3517 operands, hence the code here is free to improperly handle opcodes that
3518 have no operands (for better performance and smaller code). */
3520 if (mnemonic
[0] != 'f')
3521 return 0; /* non-math */
3523 switch (mnemonic
[1])
3525 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3526 the fs segment override prefix not currently handled because no
3527 call path can make opcodes without operands get here */
3529 return 2 /* integer op */;
3531 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3532 return 3; /* fldcw/fldenv */
3535 if (mnemonic
[2] != 'o' /* fnop */)
3536 return 3; /* non-waiting control op */
3539 if (mnemonic
[2] == 's')
3540 return 3; /* frstor/frstpm */
3543 if (mnemonic
[2] == 'a')
3544 return 3; /* fsave */
3545 if (mnemonic
[2] == 't')
3547 switch (mnemonic
[3])
3549 case 'c': /* fstcw */
3550 case 'd': /* fstdw */
3551 case 'e': /* fstenv */
3552 case 's': /* fsts[gw] */
3558 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3559 return 0; /* fxsave/fxrstor are not really math ops */
3566 /* Build the VEX prefix. */
3569 build_vex_prefix (const insn_template
*t
)
3571 unsigned int register_specifier
;
3572 unsigned int implied_prefix
;
3573 unsigned int vector_length
;
3576 /* Check register specifier. */
3577 if (i
.vex
.register_specifier
)
3579 register_specifier
=
3580 ~register_number (i
.vex
.register_specifier
) & 0xf;
3581 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3584 register_specifier
= 0xf;
3586 /* Use 2-byte VEX prefix by swapping destination and source operand
3587 if there are more than 1 register operand. */
3588 if (i
.reg_operands
> 1
3589 && i
.vec_encoding
!= vex_encoding_vex3
3590 && i
.dir_encoding
== dir_encoding_default
3591 && i
.operands
== i
.reg_operands
3592 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3593 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3594 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3597 unsigned int xchg
= i
.operands
- 1;
3598 union i386_op temp_op
;
3599 i386_operand_type temp_type
;
3601 temp_type
= i
.types
[xchg
];
3602 i
.types
[xchg
] = i
.types
[0];
3603 i
.types
[0] = temp_type
;
3604 temp_op
= i
.op
[xchg
];
3605 i
.op
[xchg
] = i
.op
[0];
3608 gas_assert (i
.rm
.mode
== 3);
3612 i
.rm
.regmem
= i
.rm
.reg
;
3615 if (i
.tm
.opcode_modifier
.d
)
3616 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3617 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3618 else /* Use the next insn. */
3622 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3623 are no memory operands and at least 3 register ones. */
3624 if (i
.reg_operands
>= 3
3625 && i
.vec_encoding
!= vex_encoding_vex3
3626 && i
.reg_operands
== i
.operands
- i
.imm_operands
3627 && i
.tm
.opcode_modifier
.vex
3628 && i
.tm
.opcode_modifier
.commutative
3629 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3631 && i
.vex
.register_specifier
3632 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3634 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3635 union i386_op temp_op
;
3636 i386_operand_type temp_type
;
3638 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3639 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3640 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3641 &i
.types
[i
.operands
- 3]));
3642 gas_assert (i
.rm
.mode
== 3);
3644 temp_type
= i
.types
[xchg
];
3645 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3646 i
.types
[xchg
+ 1] = temp_type
;
3647 temp_op
= i
.op
[xchg
];
3648 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3649 i
.op
[xchg
+ 1] = temp_op
;
3652 xchg
= i
.rm
.regmem
| 8;
3653 i
.rm
.regmem
= ~register_specifier
& 0xf;
3654 gas_assert (!(i
.rm
.regmem
& 8));
3655 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3656 register_specifier
= ~xchg
& 0xf;
3659 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3660 vector_length
= avxscalar
;
3661 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3667 /* Determine vector length from the last multi-length vector
3670 for (op
= t
->operands
; op
--;)
3671 if (t
->operand_types
[op
].bitfield
.xmmword
3672 && t
->operand_types
[op
].bitfield
.ymmword
3673 && i
.types
[op
].bitfield
.ymmword
)
3680 switch ((i
.tm
.base_opcode
>> (i
.tm
.opcode_length
<< 3)) & 0xff)
3685 case DATA_PREFIX_OPCODE
:
3688 case REPE_PREFIX_OPCODE
:
3691 case REPNE_PREFIX_OPCODE
:
3698 /* Check the REX.W bit and VEXW. */
3699 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3700 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3701 else if (i
.tm
.opcode_modifier
.vexw
)
3702 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3704 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3706 /* Use 2-byte VEX prefix if possible. */
3708 && i
.vec_encoding
!= vex_encoding_vex3
3709 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3710 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3712 /* 2-byte VEX prefix. */
3716 i
.vex
.bytes
[0] = 0xc5;
3718 /* Check the REX.R bit. */
3719 r
= (i
.rex
& REX_R
) ? 0 : 1;
3720 i
.vex
.bytes
[1] = (r
<< 7
3721 | register_specifier
<< 3
3722 | vector_length
<< 2
3727 /* 3-byte VEX prefix. */
3732 switch (i
.tm
.opcode_modifier
.vexopcode
)
3736 i
.vex
.bytes
[0] = 0xc4;
3740 i
.vex
.bytes
[0] = 0xc4;
3744 i
.vex
.bytes
[0] = 0xc4;
3748 i
.vex
.bytes
[0] = 0x8f;
3752 i
.vex
.bytes
[0] = 0x8f;
3756 i
.vex
.bytes
[0] = 0x8f;
3762 /* The high 3 bits of the second VEX byte are 1's compliment
3763 of RXB bits from REX. */
3764 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3766 i
.vex
.bytes
[2] = (w
<< 7
3767 | register_specifier
<< 3
3768 | vector_length
<< 2
3773 static INLINE bfd_boolean
3774 is_evex_encoding (const insn_template
*t
)
3776 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3777 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3778 || t
->opcode_modifier
.sae
;
3781 static INLINE bfd_boolean
3782 is_any_vex_encoding (const insn_template
*t
)
3784 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3785 || is_evex_encoding (t
);
3788 /* Build the EVEX prefix. */
3791 build_evex_prefix (void)
3793 unsigned int register_specifier
;
3794 unsigned int implied_prefix
;
3796 rex_byte vrex_used
= 0;
3798 /* Check register specifier. */
3799 if (i
.vex
.register_specifier
)
3801 gas_assert ((i
.vrex
& REX_X
) == 0);
3803 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3804 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3805 register_specifier
+= 8;
3806 /* The upper 16 registers are encoded in the fourth byte of the
3808 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3809 i
.vex
.bytes
[3] = 0x8;
3810 register_specifier
= ~register_specifier
& 0xf;
3814 register_specifier
= 0xf;
3816 /* Encode upper 16 vector index register in the fourth byte of
3818 if (!(i
.vrex
& REX_X
))
3819 i
.vex
.bytes
[3] = 0x8;
3824 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3829 case DATA_PREFIX_OPCODE
:
3832 case REPE_PREFIX_OPCODE
:
3835 case REPNE_PREFIX_OPCODE
:
3842 /* 4 byte EVEX prefix. */
3844 i
.vex
.bytes
[0] = 0x62;
3847 switch (i
.tm
.opcode_modifier
.vexopcode
)
3863 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3865 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3867 /* The fifth bit of the second EVEX byte is 1's compliment of the
3868 REX_R bit in VREX. */
3869 if (!(i
.vrex
& REX_R
))
3870 i
.vex
.bytes
[1] |= 0x10;
3874 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3876 /* When all operands are registers, the REX_X bit in REX is not
3877 used. We reuse it to encode the upper 16 registers, which is
3878 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3879 as 1's compliment. */
3880 if ((i
.vrex
& REX_B
))
3883 i
.vex
.bytes
[1] &= ~0x40;
3887 /* EVEX instructions shouldn't need the REX prefix. */
3888 i
.vrex
&= ~vrex_used
;
3889 gas_assert (i
.vrex
== 0);
3891 /* Check the REX.W bit and VEXW. */
3892 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3893 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3894 else if (i
.tm
.opcode_modifier
.vexw
)
3895 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3897 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3899 /* Encode the U bit. */
3900 implied_prefix
|= 0x4;
3902 /* The third byte of the EVEX prefix. */
3903 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3905 /* The fourth byte of the EVEX prefix. */
3906 /* The zeroing-masking bit. */
3907 if (i
.mask
&& i
.mask
->zeroing
)
3908 i
.vex
.bytes
[3] |= 0x80;
3910 /* Don't always set the broadcast bit if there is no RC. */
3913 /* Encode the vector length. */
3914 unsigned int vec_length
;
3916 if (!i
.tm
.opcode_modifier
.evex
3917 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3921 /* Determine vector length from the last multi-length vector
3923 for (op
= i
.operands
; op
--;)
3924 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3925 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3926 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3928 if (i
.types
[op
].bitfield
.zmmword
)
3930 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3933 else if (i
.types
[op
].bitfield
.ymmword
)
3935 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3938 else if (i
.types
[op
].bitfield
.xmmword
)
3940 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3943 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3945 switch (i
.broadcast
->bytes
)
3948 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3951 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3954 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3963 if (op
>= MAX_OPERANDS
)
3967 switch (i
.tm
.opcode_modifier
.evex
)
3969 case EVEXLIG
: /* LL' is ignored */
3970 vec_length
= evexlig
<< 5;
3973 vec_length
= 0 << 5;
3976 vec_length
= 1 << 5;
3979 vec_length
= 2 << 5;
3985 i
.vex
.bytes
[3] |= vec_length
;
3986 /* Encode the broadcast bit. */
3988 i
.vex
.bytes
[3] |= 0x10;
3992 if (i
.rounding
->type
!= saeonly
)
3993 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3995 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3998 if (i
.mask
&& i
.mask
->mask
)
3999 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
4003 process_immext (void)
4007 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4008 which is coded in the same place as an 8-bit immediate field
4009 would be. Here we fake an 8-bit immediate operand from the
4010 opcode suffix stored in tm.extension_opcode.
4012 AVX instructions also use this encoding, for some of
4013 3 argument instructions. */
4015 gas_assert (i
.imm_operands
<= 1
4017 || (is_any_vex_encoding (&i
.tm
)
4018 && i
.operands
<= 4)));
4020 exp
= &im_expressions
[i
.imm_operands
++];
4021 i
.op
[i
.operands
].imms
= exp
;
4022 i
.types
[i
.operands
] = imm8
;
4024 exp
->X_op
= O_constant
;
4025 exp
->X_add_number
= i
.tm
.extension_opcode
;
4026 i
.tm
.extension_opcode
= None
;
4033 switch (i
.tm
.opcode_modifier
.hleprefixok
)
4038 as_bad (_("invalid instruction `%s' after `%s'"),
4039 i
.tm
.name
, i
.hle_prefix
);
4042 if (i
.prefix
[LOCK_PREFIX
])
4044 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4048 case HLEPrefixRelease
:
4049 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4051 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4055 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4057 as_bad (_("memory destination needed for instruction `%s'"
4058 " after `xrelease'"), i
.tm
.name
);
4065 /* Try the shortest encoding by shortening operand size. */
4068 optimize_encoding (void)
4072 if (optimize_for_space
4073 && !is_any_vex_encoding (&i
.tm
)
4074 && i
.reg_operands
== 1
4075 && i
.imm_operands
== 1
4076 && !i
.types
[1].bitfield
.byte
4077 && i
.op
[0].imms
->X_op
== O_constant
4078 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4079 && (i
.tm
.base_opcode
== 0xa8
4080 || (i
.tm
.base_opcode
== 0xf6
4081 && i
.tm
.extension_opcode
== 0x0)))
4084 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4086 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4087 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4089 i
.types
[1].bitfield
.byte
= 1;
4090 /* Ignore the suffix. */
4092 /* Convert to byte registers. */
4093 if (i
.types
[1].bitfield
.word
)
4095 else if (i
.types
[1].bitfield
.dword
)
4099 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4104 else if (flag_code
== CODE_64BIT
4105 && !is_any_vex_encoding (&i
.tm
)
4106 && ((i
.types
[1].bitfield
.qword
4107 && i
.reg_operands
== 1
4108 && i
.imm_operands
== 1
4109 && i
.op
[0].imms
->X_op
== O_constant
4110 && ((i
.tm
.base_opcode
== 0xb8
4111 && i
.tm
.extension_opcode
== None
4112 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4113 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4114 && ((i
.tm
.base_opcode
== 0x24
4115 || i
.tm
.base_opcode
== 0xa8)
4116 || (i
.tm
.base_opcode
== 0x80
4117 && i
.tm
.extension_opcode
== 0x4)
4118 || ((i
.tm
.base_opcode
== 0xf6
4119 || (i
.tm
.base_opcode
| 1) == 0xc7)
4120 && i
.tm
.extension_opcode
== 0x0)))
4121 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4122 && i
.tm
.base_opcode
== 0x83
4123 && i
.tm
.extension_opcode
== 0x4)))
4124 || (i
.types
[0].bitfield
.qword
4125 && ((i
.reg_operands
== 2
4126 && i
.op
[0].regs
== i
.op
[1].regs
4127 && (i
.tm
.base_opcode
== 0x30
4128 || i
.tm
.base_opcode
== 0x28))
4129 || (i
.reg_operands
== 1
4131 && i
.tm
.base_opcode
== 0x30)))))
4134 andq $imm31, %r64 -> andl $imm31, %r32
4135 andq $imm7, %r64 -> andl $imm7, %r32
4136 testq $imm31, %r64 -> testl $imm31, %r32
4137 xorq %r64, %r64 -> xorl %r32, %r32
4138 subq %r64, %r64 -> subl %r32, %r32
4139 movq $imm31, %r64 -> movl $imm31, %r32
4140 movq $imm32, %r64 -> movl $imm32, %r32
4142 i
.tm
.opcode_modifier
.norex64
= 1;
4143 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4146 movq $imm31, %r64 -> movl $imm31, %r32
4147 movq $imm32, %r64 -> movl $imm32, %r32
4149 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4150 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4151 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4152 i
.types
[0].bitfield
.imm32
= 1;
4153 i
.types
[0].bitfield
.imm32s
= 0;
4154 i
.types
[0].bitfield
.imm64
= 0;
4155 i
.types
[1].bitfield
.dword
= 1;
4156 i
.types
[1].bitfield
.qword
= 0;
4157 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4160 movq $imm31, %r64 -> movl $imm31, %r32
4162 i
.tm
.base_opcode
= 0xb8;
4163 i
.tm
.extension_opcode
= None
;
4164 i
.tm
.opcode_modifier
.w
= 0;
4165 i
.tm
.opcode_modifier
.modrm
= 0;
4169 else if (optimize
> 1
4170 && !optimize_for_space
4171 && !is_any_vex_encoding (&i
.tm
)
4172 && i
.reg_operands
== 2
4173 && i
.op
[0].regs
== i
.op
[1].regs
4174 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4175 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4176 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4179 andb %rN, %rN -> testb %rN, %rN
4180 andw %rN, %rN -> testw %rN, %rN
4181 andq %rN, %rN -> testq %rN, %rN
4182 orb %rN, %rN -> testb %rN, %rN
4183 orw %rN, %rN -> testw %rN, %rN
4184 orq %rN, %rN -> testq %rN, %rN
4186 and outside of 64-bit mode
4188 andl %rN, %rN -> testl %rN, %rN
4189 orl %rN, %rN -> testl %rN, %rN
4191 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4193 else if (i
.reg_operands
== 3
4194 && i
.op
[0].regs
== i
.op
[1].regs
4195 && !i
.types
[2].bitfield
.xmmword
4196 && (i
.tm
.opcode_modifier
.vex
4197 || ((!i
.mask
|| i
.mask
->zeroing
)
4199 && is_evex_encoding (&i
.tm
)
4200 && (i
.vec_encoding
!= vex_encoding_evex
4201 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4202 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4203 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4204 && i
.types
[2].bitfield
.ymmword
))))
4205 && ((i
.tm
.base_opcode
== 0x55
4206 || i
.tm
.base_opcode
== 0x6655
4207 || i
.tm
.base_opcode
== 0x66df
4208 || i
.tm
.base_opcode
== 0x57
4209 || i
.tm
.base_opcode
== 0x6657
4210 || i
.tm
.base_opcode
== 0x66ef
4211 || i
.tm
.base_opcode
== 0x66f8
4212 || i
.tm
.base_opcode
== 0x66f9
4213 || i
.tm
.base_opcode
== 0x66fa
4214 || i
.tm
.base_opcode
== 0x66fb
4215 || i
.tm
.base_opcode
== 0x42
4216 || i
.tm
.base_opcode
== 0x6642
4217 || i
.tm
.base_opcode
== 0x47
4218 || i
.tm
.base_opcode
== 0x6647)
4219 && i
.tm
.extension_opcode
== None
))
4222 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4224 EVEX VOP %zmmM, %zmmM, %zmmN
4225 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4226 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4227 EVEX VOP %ymmM, %ymmM, %ymmN
4228 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4229 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4230 VEX VOP %ymmM, %ymmM, %ymmN
4231 -> VEX VOP %xmmM, %xmmM, %xmmN
4232 VOP, one of vpandn and vpxor:
4233 VEX VOP %ymmM, %ymmM, %ymmN
4234 -> VEX VOP %xmmM, %xmmM, %xmmN
4235 VOP, one of vpandnd and vpandnq:
4236 EVEX VOP %zmmM, %zmmM, %zmmN
4237 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4238 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4239 EVEX VOP %ymmM, %ymmM, %ymmN
4240 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4241 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4242 VOP, one of vpxord and vpxorq:
4243 EVEX VOP %zmmM, %zmmM, %zmmN
4244 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4245 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4246 EVEX VOP %ymmM, %ymmM, %ymmN
4247 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4248 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4249 VOP, one of kxord and kxorq:
4250 VEX VOP %kM, %kM, %kN
4251 -> VEX kxorw %kM, %kM, %kN
4252 VOP, one of kandnd and kandnq:
4253 VEX VOP %kM, %kM, %kN
4254 -> VEX kandnw %kM, %kM, %kN
4256 if (is_evex_encoding (&i
.tm
))
4258 if (i
.vec_encoding
!= vex_encoding_evex
)
4260 i
.tm
.opcode_modifier
.vex
= VEX128
;
4261 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4262 i
.tm
.opcode_modifier
.evex
= 0;
4264 else if (optimize
> 1)
4265 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4269 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4271 i
.tm
.base_opcode
&= 0xff;
4272 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4275 i
.tm
.opcode_modifier
.vex
= VEX128
;
4277 if (i
.tm
.opcode_modifier
.vex
)
4278 for (j
= 0; j
< 3; j
++)
4280 i
.types
[j
].bitfield
.xmmword
= 1;
4281 i
.types
[j
].bitfield
.ymmword
= 0;
4284 else if (i
.vec_encoding
!= vex_encoding_evex
4285 && !i
.types
[0].bitfield
.zmmword
4286 && !i
.types
[1].bitfield
.zmmword
4289 && is_evex_encoding (&i
.tm
)
4290 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4291 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4292 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4293 || (i
.tm
.base_opcode
& ~4) == 0x66db
4294 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4295 && i
.tm
.extension_opcode
== None
)
4298 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4299 vmovdqu32 and vmovdqu64:
4300 EVEX VOP %xmmM, %xmmN
4301 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4302 EVEX VOP %ymmM, %ymmN
4303 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4305 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4307 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4309 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4311 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4312 VOP, one of vpand, vpandn, vpor, vpxor:
4313 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4314 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4315 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4316 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4317 EVEX VOP{d,q} mem, %xmmM, %xmmN
4318 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4319 EVEX VOP{d,q} mem, %ymmM, %ymmN
4320 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4322 for (j
= 0; j
< i
.operands
; j
++)
4323 if (operand_type_check (i
.types
[j
], disp
)
4324 && i
.op
[j
].disps
->X_op
== O_constant
)
4326 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4327 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4328 bytes, we choose EVEX Disp8 over VEX Disp32. */
4329 int evex_disp8
, vex_disp8
;
4330 unsigned int memshift
= i
.memshift
;
4331 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4333 evex_disp8
= fits_in_disp8 (n
);
4335 vex_disp8
= fits_in_disp8 (n
);
4336 if (evex_disp8
!= vex_disp8
)
4338 i
.memshift
= memshift
;
4342 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4345 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4346 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4347 i
.tm
.opcode_modifier
.vex
4348 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4349 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4350 /* VPAND, VPOR, and VPXOR are commutative. */
4351 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4352 i
.tm
.opcode_modifier
.commutative
= 1;
4353 i
.tm
.opcode_modifier
.evex
= 0;
4354 i
.tm
.opcode_modifier
.masking
= 0;
4355 i
.tm
.opcode_modifier
.broadcast
= 0;
4356 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4359 i
.types
[j
].bitfield
.disp8
4360 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4364 /* Return non-zero for load instruction. */
4370 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4371 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4375 /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
4376 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
4377 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
4378 if (i
.tm
.opcode_modifier
.anysize
)
4381 /* pop, popf, popa. */
4382 if (strcmp (i
.tm
.name
, "pop") == 0
4383 || i
.tm
.base_opcode
== 0x9d
4384 || i
.tm
.base_opcode
== 0x61)
4387 /* movs, cmps, lods, scas. */
4388 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4392 if (base_opcode
== 0x6f
4393 || i
.tm
.base_opcode
== 0xd7)
4395 /* NB: For AMD-specific insns with implicit memory operands,
4396 they're intentionally not covered. */
4399 /* No memory operand. */
4400 if (!i
.mem_operands
)
4406 if (i
.tm
.base_opcode
== 0xae
4407 && i
.tm
.opcode_modifier
.vex
4408 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
4409 && i
.tm
.extension_opcode
== 2)
4414 /* test, not, neg, mul, imul, div, idiv. */
4415 if ((i
.tm
.base_opcode
== 0xf6 || i
.tm
.base_opcode
== 0xf7)
4416 && i
.tm
.extension_opcode
!= 1)
4420 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4423 /* add, or, adc, sbb, and, sub, xor, cmp. */
4424 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4427 /* bt, bts, btr, btc. */
4428 if (i
.tm
.base_opcode
== 0xfba
4429 && (i
.tm
.extension_opcode
>= 4 && i
.tm
.extension_opcode
<= 7))
4432 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4433 if ((base_opcode
== 0xc1
4434 || (i
.tm
.base_opcode
>= 0xd0 && i
.tm
.base_opcode
<= 0xd3))
4435 && i
.tm
.extension_opcode
!= 6)
4438 /* cmpxchg8b, cmpxchg16b, xrstors. */
4439 if (i
.tm
.base_opcode
== 0xfc7
4440 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3))
4443 /* fxrstor, ldmxcsr, xrstor. */
4444 if (i
.tm
.base_opcode
== 0xfae
4445 && (i
.tm
.extension_opcode
== 1
4446 || i
.tm
.extension_opcode
== 2
4447 || i
.tm
.extension_opcode
== 5))
4450 /* lgdt, lidt, lmsw. */
4451 if (i
.tm
.base_opcode
== 0xf01
4452 && (i
.tm
.extension_opcode
== 2
4453 || i
.tm
.extension_opcode
== 3
4454 || i
.tm
.extension_opcode
== 6))
4458 if (i
.tm
.base_opcode
== 0xfc7
4459 && i
.tm
.extension_opcode
== 6)
4462 /* Check for x87 instructions. */
4463 if (i
.tm
.base_opcode
>= 0xd8 && i
.tm
.base_opcode
<= 0xdf)
4465 /* Skip fst, fstp, fstenv, fstcw. */
4466 if (i
.tm
.base_opcode
== 0xd9
4467 && (i
.tm
.extension_opcode
== 2
4468 || i
.tm
.extension_opcode
== 3
4469 || i
.tm
.extension_opcode
== 6
4470 || i
.tm
.extension_opcode
== 7))
4473 /* Skip fisttp, fist, fistp, fstp. */
4474 if (i
.tm
.base_opcode
== 0xdb
4475 && (i
.tm
.extension_opcode
== 1
4476 || i
.tm
.extension_opcode
== 2
4477 || i
.tm
.extension_opcode
== 3
4478 || i
.tm
.extension_opcode
== 7))
4481 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4482 if (i
.tm
.base_opcode
== 0xdd
4483 && (i
.tm
.extension_opcode
== 1
4484 || i
.tm
.extension_opcode
== 2
4485 || i
.tm
.extension_opcode
== 3
4486 || i
.tm
.extension_opcode
== 6
4487 || i
.tm
.extension_opcode
== 7))
4490 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4491 if (i
.tm
.base_opcode
== 0xdf
4492 && (i
.tm
.extension_opcode
== 1
4493 || i
.tm
.extension_opcode
== 2
4494 || i
.tm
.extension_opcode
== 3
4495 || i
.tm
.extension_opcode
== 6
4496 || i
.tm
.extension_opcode
== 7))
4503 dest
= i
.operands
- 1;
4505 /* Check fake imm8 operand and 3 source operands. */
4506 if ((i
.tm
.opcode_modifier
.immext
4507 || i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4508 && i
.types
[dest
].bitfield
.imm8
)
4511 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */
4513 && (base_opcode
== 0x1
4514 || base_opcode
== 0x9
4515 || base_opcode
== 0x11
4516 || base_opcode
== 0x19
4517 || base_opcode
== 0x21
4518 || base_opcode
== 0x29
4519 || base_opcode
== 0x31
4520 || base_opcode
== 0x39
4521 || (i
.tm
.base_opcode
>= 0x84 && i
.tm
.base_opcode
<= 0x87)
4522 || base_opcode
== 0xfc1))
4525 /* Check for load instruction. */
4526 return (i
.types
[dest
].bitfield
.class != ClassNone
4527 || i
.types
[dest
].bitfield
.instance
== Accum
);
4530 /* Output lfence, 0xfaee8, after instruction. */
4533 insert_lfence_after (void)
4535 if (lfence_after_load
&& load_insn_p ())
4537 /* There are also two REP string instructions that require
4538 special treatment. Specifically, the compare string (CMPS)
4539 and scan string (SCAS) instructions set EFLAGS in a manner
4540 that depends on the data being compared/scanned. When used
4541 with a REP prefix, the number of iterations may therefore
4542 vary depending on this data. If the data is a program secret
4543 chosen by the adversary using an LVI method,
4544 then this data-dependent behavior may leak some aspect
4546 if (((i
.tm
.base_opcode
| 0x1) == 0xa7
4547 || (i
.tm
.base_opcode
| 0x1) == 0xaf)
4548 && i
.prefix
[REP_PREFIX
])
4550 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4553 char *p
= frag_more (3);
4560 /* Output lfence, 0xfaee8, before instruction. */
4563 insert_lfence_before (void)
4567 if (is_any_vex_encoding (&i
.tm
))
4570 if (i
.tm
.base_opcode
== 0xff
4571 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4573 /* Insert lfence before indirect branch if needed. */
4575 if (lfence_before_indirect_branch
== lfence_branch_none
)
4578 if (i
.operands
!= 1)
4581 if (i
.reg_operands
== 1)
4583 /* Indirect branch via register. Don't insert lfence with
4584 -mlfence-after-load=yes. */
4585 if (lfence_after_load
4586 || lfence_before_indirect_branch
== lfence_branch_memory
)
4589 else if (i
.mem_operands
== 1
4590 && lfence_before_indirect_branch
!= lfence_branch_register
)
4592 as_warn (_("indirect `%s` with memory operand should be avoided"),
4599 if (last_insn
.kind
!= last_insn_other
4600 && last_insn
.seg
== now_seg
)
4602 as_warn_where (last_insn
.file
, last_insn
.line
,
4603 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4604 last_insn
.name
, i
.tm
.name
);
4615 /* Output or/not/shl and lfence before near ret. */
4616 if (lfence_before_ret
!= lfence_before_ret_none
4617 && (i
.tm
.base_opcode
== 0xc2
4618 || i
.tm
.base_opcode
== 0xc3))
4620 if (last_insn
.kind
!= last_insn_other
4621 && last_insn
.seg
== now_seg
)
4623 as_warn_where (last_insn
.file
, last_insn
.line
,
4624 _("`%s` skips -mlfence-before-ret on `%s`"),
4625 last_insn
.name
, i
.tm
.name
);
4629 /* Near ret ingore operand size override under CPU64. */
4630 char prefix
= flag_code
== CODE_64BIT
4632 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4634 if (lfence_before_ret
== lfence_before_ret_not
)
4636 /* not: 0xf71424, may add prefix
4637 for operand size override or 64-bit code. */
4638 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4652 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4655 if (lfence_before_ret
== lfence_before_ret_or
)
4657 /* or: 0x830c2400, may add prefix
4658 for operand size override or 64-bit code. */
4664 /* shl: 0xc1242400, may add prefix
4665 for operand size override or 64-bit code. */
4680 /* This is the guts of the machine-dependent assembler. LINE points to a
4681 machine dependent instruction. This function is supposed to emit
4682 the frags/bytes it assembles to. */
4685 md_assemble (char *line
)
4688 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4689 const insn_template
*t
;
4691 /* Initialize globals. */
4692 memset (&i
, '\0', sizeof (i
));
4693 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4694 i
.reloc
[j
] = NO_RELOC
;
4695 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4696 memset (im_expressions
, '\0', sizeof (im_expressions
));
4697 save_stack_p
= save_stack
;
4699 /* First parse an instruction mnemonic & call i386_operand for the operands.
4700 We assume that the scrubber has arranged it so that line[0] is the valid
4701 start of a (possibly prefixed) mnemonic. */
4703 line
= parse_insn (line
, mnemonic
);
4706 mnem_suffix
= i
.suffix
;
4708 line
= parse_operands (line
, mnemonic
);
4710 xfree (i
.memop1_string
);
4711 i
.memop1_string
= NULL
;
4715 /* Now we've parsed the mnemonic into a set of templates, and have the
4716 operands at hand. */
4718 /* All Intel opcodes have reversed operands except for "bound", "enter",
4719 "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
4720 intersegment "jmp" and "call" instructions with 2 immediate operands so
4721 that the immediate segment precedes the offset, as it does when in AT&T
4725 && (strcmp (mnemonic
, "bound") != 0)
4726 && (strcmp (mnemonic
, "invlpga") != 0)
4727 && (strncmp (mnemonic
, "monitor", 7) != 0)
4728 && (strncmp (mnemonic
, "mwait", 5) != 0)
4729 && (strcmp (mnemonic
, "tpause") != 0)
4730 && (strcmp (mnemonic
, "umwait") != 0)
4731 && !(operand_type_check (i
.types
[0], imm
)
4732 && operand_type_check (i
.types
[1], imm
)))
4735 /* The order of the immediates should be reversed
4736 for 2 immediates extrq and insertq instructions */
4737 if (i
.imm_operands
== 2
4738 && (strcmp (mnemonic
, "extrq") == 0
4739 || strcmp (mnemonic
, "insertq") == 0))
4740 swap_2_operands (0, 1);
4745 /* Don't optimize displacement for movabs since it only takes 64bit
4748 && i
.disp_encoding
!= disp_encoding_32bit
4749 && (flag_code
!= CODE_64BIT
4750 || strcmp (mnemonic
, "movabs") != 0))
4753 /* Next, we find a template that matches the given insn,
4754 making sure the overlap of the given operands types is consistent
4755 with the template operand types. */
4757 if (!(t
= match_template (mnem_suffix
)))
4760 if (sse_check
!= check_none
4761 && !i
.tm
.opcode_modifier
.noavx
4762 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4763 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4764 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4765 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4766 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4767 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4768 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4769 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4770 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4771 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4772 || i
.tm
.cpu_flags
.bitfield
.cpusha
4773 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4775 (sse_check
== check_warning
4777 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4780 if (i
.tm
.opcode_modifier
.fwait
)
4781 if (!add_prefix (FWAIT_OPCODE
))
4784 /* Check if REP prefix is OK. */
4785 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4787 as_bad (_("invalid instruction `%s' after `%s'"),
4788 i
.tm
.name
, i
.rep_prefix
);
4792 /* Check for lock without a lockable instruction. Destination operand
4793 must be memory unless it is xchg (0x86). */
4794 if (i
.prefix
[LOCK_PREFIX
]
4795 && (!i
.tm
.opcode_modifier
.islockable
4796 || i
.mem_operands
== 0
4797 || (i
.tm
.base_opcode
!= 0x86
4798 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4800 as_bad (_("expecting lockable instruction after `lock'"));
4804 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
4805 if (i
.prefix
[DATA_PREFIX
]
4806 && (is_any_vex_encoding (&i
.tm
)
4807 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
4808 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
))
4810 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4814 /* Check if HLE prefix is OK. */
4815 if (i
.hle_prefix
&& !check_hle ())
4818 /* Check BND prefix. */
4819 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4820 as_bad (_("expecting valid branch instruction after `bnd'"));
4822 /* Check NOTRACK prefix. */
4823 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4824 as_bad (_("expecting indirect branch instruction after `notrack'"));
4826 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4828 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4829 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4830 else if (flag_code
!= CODE_16BIT
4831 ? i
.prefix
[ADDR_PREFIX
]
4832 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4833 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4836 /* Insert BND prefix. */
4837 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4839 if (!i
.prefix
[BND_PREFIX
])
4840 add_prefix (BND_PREFIX_OPCODE
);
4841 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4843 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4844 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4848 /* Check string instruction segment overrides. */
4849 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4851 gas_assert (i
.mem_operands
);
4852 if (!check_string ())
4854 i
.disp_operands
= 0;
4857 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4858 optimize_encoding ();
4860 if (!process_suffix ())
4863 /* Update operand types and check extended states. */
4864 for (j
= 0; j
< i
.operands
; j
++)
4866 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4867 switch (i
.tm
.operand_types
[j
].bitfield
.class)
4872 i
.xstate
|= xstate_mmx
;
4875 i
.xstate
|= xstate_zmm
;
4878 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
4879 i
.xstate
|= xstate_tmm
;
4880 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
)
4881 i
.xstate
|= xstate_zmm
;
4882 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
)
4883 i
.xstate
|= xstate_ymm
;
4884 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
4885 i
.xstate
|= xstate_xmm
;
4890 /* Make still unresolved immediate matches conform to size of immediate
4891 given in i.suffix. */
4892 if (!finalize_imm ())
4895 if (i
.types
[0].bitfield
.imm1
)
4896 i
.imm_operands
= 0; /* kludge for shift insns. */
4898 /* We only need to check those implicit registers for instructions
4899 with 3 operands or less. */
4900 if (i
.operands
<= 3)
4901 for (j
= 0; j
< i
.operands
; j
++)
4902 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4903 && !i
.types
[j
].bitfield
.xmmword
)
4906 /* For insns with operands there are more diddles to do to the opcode. */
4909 if (!process_operands ())
4912 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4914 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4915 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4918 if (is_any_vex_encoding (&i
.tm
))
4920 if (!cpu_arch_flags
.bitfield
.cpui286
)
4922 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4927 /* Check for explicit REX prefix. */
4928 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
4930 as_bad (_("REX prefix invalid with `%s'"), i
.tm
.name
);
4934 if (i
.tm
.opcode_modifier
.vex
)
4935 build_vex_prefix (t
);
4937 build_evex_prefix ();
4939 /* The individual REX.RXBW bits got consumed. */
4940 i
.rex
&= REX_OPCODE
;
4943 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4944 instructions may define INT_OPCODE as well, so avoid this corner
4945 case for those instructions that use MODRM. */
4946 if (i
.tm
.base_opcode
== INT_OPCODE
4947 && !i
.tm
.opcode_modifier
.modrm
4948 && i
.op
[0].imms
->X_add_number
== 3)
4950 i
.tm
.base_opcode
= INT3_OPCODE
;
4954 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4955 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4956 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4957 && i
.op
[0].disps
->X_op
== O_constant
)
4959 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4960 the absolute address given by the constant. Since ix86 jumps and
4961 calls are pc relative, we need to generate a reloc. */
4962 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4963 i
.op
[0].disps
->X_op
= O_symbol
;
4966 /* For 8 bit registers we need an empty rex prefix. Also if the
4967 instruction already has a prefix, we need to convert old
4968 registers to new ones. */
4970 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4971 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4972 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4973 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4974 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4975 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4980 i
.rex
|= REX_OPCODE
;
4981 for (x
= 0; x
< 2; x
++)
4983 /* Look for 8 bit operand that uses old registers. */
4984 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4985 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4987 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4988 /* In case it is "hi" register, give up. */
4989 if (i
.op
[x
].regs
->reg_num
> 3)
4990 as_bad (_("can't encode register '%s%s' in an "
4991 "instruction requiring REX prefix."),
4992 register_prefix
, i
.op
[x
].regs
->reg_name
);
4994 /* Otherwise it is equivalent to the extended register.
4995 Since the encoding doesn't change this is merely
4996 cosmetic cleanup for debug output. */
4998 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
5003 if (i
.rex
== 0 && i
.rex_encoding
)
5005 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5006 that uses legacy register. If it is "hi" register, don't add
5007 the REX_OPCODE byte. */
5009 for (x
= 0; x
< 2; x
++)
5010 if (i
.types
[x
].bitfield
.class == Reg
5011 && i
.types
[x
].bitfield
.byte
5012 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5013 && i
.op
[x
].regs
->reg_num
> 3)
5015 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5016 i
.rex_encoding
= FALSE
;
5025 add_prefix (REX_OPCODE
| i
.rex
);
5027 insert_lfence_before ();
5029 /* We are ready to output the insn. */
5032 insert_lfence_after ();
5034 last_insn
.seg
= now_seg
;
5036 if (i
.tm
.opcode_modifier
.isprefix
)
5038 last_insn
.kind
= last_insn_prefix
;
5039 last_insn
.name
= i
.tm
.name
;
5040 last_insn
.file
= as_where (&last_insn
.line
);
5043 last_insn
.kind
= last_insn_other
;
5047 parse_insn (char *line
, char *mnemonic
)
5050 char *token_start
= l
;
5053 const insn_template
*t
;
5059 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5064 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5066 as_bad (_("no such instruction: `%s'"), token_start
);
5071 if (!is_space_char (*l
)
5072 && *l
!= END_OF_INSN
5074 || (*l
!= PREFIX_SEPARATOR
5077 as_bad (_("invalid character %s in mnemonic"),
5078 output_invalid (*l
));
5081 if (token_start
== l
)
5083 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5084 as_bad (_("expecting prefix; got nothing"));
5086 as_bad (_("expecting mnemonic; got nothing"));
5090 /* Look up instruction (or prefix) via hash table. */
5091 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
5093 if (*l
!= END_OF_INSN
5094 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5095 && current_templates
5096 && current_templates
->start
->opcode_modifier
.isprefix
)
5098 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5100 as_bad ((flag_code
!= CODE_64BIT
5101 ? _("`%s' is only supported in 64-bit mode")
5102 : _("`%s' is not supported in 64-bit mode")),
5103 current_templates
->start
->name
);
5106 /* If we are in 16-bit mode, do not allow addr16 or data16.
5107 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5108 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5109 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5110 && flag_code
!= CODE_64BIT
5111 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5112 ^ (flag_code
== CODE_16BIT
)))
5114 as_bad (_("redundant %s prefix"),
5115 current_templates
->start
->name
);
5118 if (current_templates
->start
->opcode_length
== 0)
5120 /* Handle pseudo prefixes. */
5121 switch (current_templates
->start
->base_opcode
)
5125 i
.disp_encoding
= disp_encoding_8bit
;
5129 i
.disp_encoding
= disp_encoding_16bit
;
5133 i
.disp_encoding
= disp_encoding_32bit
;
5137 i
.dir_encoding
= dir_encoding_load
;
5141 i
.dir_encoding
= dir_encoding_store
;
5145 i
.vec_encoding
= vex_encoding_vex
;
5149 i
.vec_encoding
= vex_encoding_vex3
;
5153 i
.vec_encoding
= vex_encoding_evex
;
5157 i
.rex_encoding
= TRUE
;
5159 case Prefix_NoOptimize
:
5161 i
.no_optimize
= TRUE
;
5169 /* Add prefix, checking for repeated prefixes. */
5170 switch (add_prefix (current_templates
->start
->base_opcode
))
5175 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5176 i
.notrack_prefix
= current_templates
->start
->name
;
5179 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5180 i
.hle_prefix
= current_templates
->start
->name
;
5181 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5182 i
.bnd_prefix
= current_templates
->start
->name
;
5184 i
.rep_prefix
= current_templates
->start
->name
;
5190 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5197 if (!current_templates
)
5199 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5200 Check if we should swap operand or force 32bit displacement in
5202 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5203 i
.dir_encoding
= dir_encoding_swap
;
5204 else if (mnem_p
- 3 == dot_p
5207 i
.disp_encoding
= disp_encoding_8bit
;
5208 else if (mnem_p
- 4 == dot_p
5212 i
.disp_encoding
= disp_encoding_32bit
;
5217 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
5220 if (!current_templates
)
5223 if (mnem_p
> mnemonic
)
5225 /* See if we can get a match by trimming off a suffix. */
5228 case WORD_MNEM_SUFFIX
:
5229 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5230 i
.suffix
= SHORT_MNEM_SUFFIX
;
5233 case BYTE_MNEM_SUFFIX
:
5234 case QWORD_MNEM_SUFFIX
:
5235 i
.suffix
= mnem_p
[-1];
5237 current_templates
= (const templates
*) hash_find (op_hash
,
5240 case SHORT_MNEM_SUFFIX
:
5241 case LONG_MNEM_SUFFIX
:
5244 i
.suffix
= mnem_p
[-1];
5246 current_templates
= (const templates
*) hash_find (op_hash
,
5255 if (intel_float_operand (mnemonic
) == 1)
5256 i
.suffix
= SHORT_MNEM_SUFFIX
;
5258 i
.suffix
= LONG_MNEM_SUFFIX
;
5260 current_templates
= (const templates
*) hash_find (op_hash
,
5267 if (!current_templates
)
5269 as_bad (_("no such instruction: `%s'"), token_start
);
5274 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5275 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5277 /* Check for a branch hint. We allow ",pt" and ",pn" for
5278 predict taken and predict not taken respectively.
5279 I'm not sure that branch hints actually do anything on loop
5280 and jcxz insns (JumpByte) for current Pentium4 chips. They
5281 may work in the future and it doesn't hurt to accept them
5283 if (l
[0] == ',' && l
[1] == 'p')
5287 if (!add_prefix (DS_PREFIX_OPCODE
))
5291 else if (l
[2] == 'n')
5293 if (!add_prefix (CS_PREFIX_OPCODE
))
5299 /* Any other comma loses. */
5302 as_bad (_("invalid character %s in mnemonic"),
5303 output_invalid (*l
));
5307 /* Check if instruction is supported on specified architecture. */
5309 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5311 supported
|= cpu_flags_match (t
);
5312 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5314 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
5315 as_warn (_("use .code16 to ensure correct addressing mode"));
5321 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
5322 as_bad (flag_code
== CODE_64BIT
5323 ? _("`%s' is not supported in 64-bit mode")
5324 : _("`%s' is only supported in 64-bit mode"),
5325 current_templates
->start
->name
);
5327 as_bad (_("`%s' is not supported on `%s%s'"),
5328 current_templates
->start
->name
,
5329 cpu_arch_name
? cpu_arch_name
: default_arch
,
5330 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5336 parse_operands (char *l
, const char *mnemonic
)
5340 /* 1 if operand is pending after ','. */
5341 unsigned int expecting_operand
= 0;
5343 /* Non-zero if operand parens not balanced. */
5344 unsigned int paren_not_balanced
;
5346 while (*l
!= END_OF_INSN
)
5348 /* Skip optional white space before operand. */
5349 if (is_space_char (*l
))
5351 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5353 as_bad (_("invalid character %s before operand %d"),
5354 output_invalid (*l
),
5358 token_start
= l
; /* After white space. */
5359 paren_not_balanced
= 0;
5360 while (paren_not_balanced
|| *l
!= ',')
5362 if (*l
== END_OF_INSN
)
5364 if (paren_not_balanced
)
5367 as_bad (_("unbalanced parenthesis in operand %d."),
5370 as_bad (_("unbalanced brackets in operand %d."),
5375 break; /* we are done */
5377 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
5379 as_bad (_("invalid character %s in operand %d"),
5380 output_invalid (*l
),
5387 ++paren_not_balanced
;
5389 --paren_not_balanced
;
5394 ++paren_not_balanced
;
5396 --paren_not_balanced
;
5400 if (l
!= token_start
)
5401 { /* Yes, we've read in another operand. */
5402 unsigned int operand_ok
;
5403 this_operand
= i
.operands
++;
5404 if (i
.operands
> MAX_OPERANDS
)
5406 as_bad (_("spurious operands; (%d operands/instruction max)"),
5410 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5411 /* Now parse operand adding info to 'i' as we go along. */
5412 END_STRING_AND_SAVE (l
);
5414 if (i
.mem_operands
> 1)
5416 as_bad (_("too many memory references for `%s'"),
5423 i386_intel_operand (token_start
,
5424 intel_float_operand (mnemonic
));
5426 operand_ok
= i386_att_operand (token_start
);
5428 RESTORE_END_STRING (l
);
5434 if (expecting_operand
)
5436 expecting_operand_after_comma
:
5437 as_bad (_("expecting operand after ','; got nothing"));
5442 as_bad (_("expecting operand before ','; got nothing"));
5447 /* Now *l must be either ',' or END_OF_INSN. */
5450 if (*++l
== END_OF_INSN
)
5452 /* Just skip it, if it's \n complain. */
5453 goto expecting_operand_after_comma
;
5455 expecting_operand
= 1;
5462 swap_2_operands (int xchg1
, int xchg2
)
5464 union i386_op temp_op
;
5465 i386_operand_type temp_type
;
5466 unsigned int temp_flags
;
5467 enum bfd_reloc_code_real temp_reloc
;
5469 temp_type
= i
.types
[xchg2
];
5470 i
.types
[xchg2
] = i
.types
[xchg1
];
5471 i
.types
[xchg1
] = temp_type
;
5473 temp_flags
= i
.flags
[xchg2
];
5474 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5475 i
.flags
[xchg1
] = temp_flags
;
5477 temp_op
= i
.op
[xchg2
];
5478 i
.op
[xchg2
] = i
.op
[xchg1
];
5479 i
.op
[xchg1
] = temp_op
;
5481 temp_reloc
= i
.reloc
[xchg2
];
5482 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5483 i
.reloc
[xchg1
] = temp_reloc
;
5487 if (i
.mask
->operand
== xchg1
)
5488 i
.mask
->operand
= xchg2
;
5489 else if (i
.mask
->operand
== xchg2
)
5490 i
.mask
->operand
= xchg1
;
5494 if (i
.broadcast
->operand
== xchg1
)
5495 i
.broadcast
->operand
= xchg2
;
5496 else if (i
.broadcast
->operand
== xchg2
)
5497 i
.broadcast
->operand
= xchg1
;
5501 if (i
.rounding
->operand
== xchg1
)
5502 i
.rounding
->operand
= xchg2
;
5503 else if (i
.rounding
->operand
== xchg2
)
5504 i
.rounding
->operand
= xchg1
;
5509 swap_operands (void)
5515 swap_2_operands (1, i
.operands
- 2);
5519 swap_2_operands (0, i
.operands
- 1);
5525 if (i
.mem_operands
== 2)
5527 const seg_entry
*temp_seg
;
5528 temp_seg
= i
.seg
[0];
5529 i
.seg
[0] = i
.seg
[1];
5530 i
.seg
[1] = temp_seg
;
5534 /* Try to ensure constant immediates are represented in the smallest
5539 char guess_suffix
= 0;
5543 guess_suffix
= i
.suffix
;
5544 else if (i
.reg_operands
)
5546 /* Figure out a suffix from the last register operand specified.
5547 We can't do this properly yet, i.e. excluding special register
5548 instances, but the following works for instructions with
5549 immediates. In any case, we can't set i.suffix yet. */
5550 for (op
= i
.operands
; --op
>= 0;)
5551 if (i
.types
[op
].bitfield
.class != Reg
)
5553 else if (i
.types
[op
].bitfield
.byte
)
5555 guess_suffix
= BYTE_MNEM_SUFFIX
;
5558 else if (i
.types
[op
].bitfield
.word
)
5560 guess_suffix
= WORD_MNEM_SUFFIX
;
5563 else if (i
.types
[op
].bitfield
.dword
)
5565 guess_suffix
= LONG_MNEM_SUFFIX
;
5568 else if (i
.types
[op
].bitfield
.qword
)
5570 guess_suffix
= QWORD_MNEM_SUFFIX
;
5574 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5575 guess_suffix
= WORD_MNEM_SUFFIX
;
5577 for (op
= i
.operands
; --op
>= 0;)
5578 if (operand_type_check (i
.types
[op
], imm
))
5580 switch (i
.op
[op
].imms
->X_op
)
5583 /* If a suffix is given, this operand may be shortened. */
5584 switch (guess_suffix
)
5586 case LONG_MNEM_SUFFIX
:
5587 i
.types
[op
].bitfield
.imm32
= 1;
5588 i
.types
[op
].bitfield
.imm64
= 1;
5590 case WORD_MNEM_SUFFIX
:
5591 i
.types
[op
].bitfield
.imm16
= 1;
5592 i
.types
[op
].bitfield
.imm32
= 1;
5593 i
.types
[op
].bitfield
.imm32s
= 1;
5594 i
.types
[op
].bitfield
.imm64
= 1;
5596 case BYTE_MNEM_SUFFIX
:
5597 i
.types
[op
].bitfield
.imm8
= 1;
5598 i
.types
[op
].bitfield
.imm8s
= 1;
5599 i
.types
[op
].bitfield
.imm16
= 1;
5600 i
.types
[op
].bitfield
.imm32
= 1;
5601 i
.types
[op
].bitfield
.imm32s
= 1;
5602 i
.types
[op
].bitfield
.imm64
= 1;
5606 /* If this operand is at most 16 bits, convert it
5607 to a signed 16 bit number before trying to see
5608 whether it will fit in an even smaller size.
5609 This allows a 16-bit operand such as $0xffe0 to
5610 be recognised as within Imm8S range. */
5611 if ((i
.types
[op
].bitfield
.imm16
)
5612 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5614 i
.op
[op
].imms
->X_add_number
=
5615 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5618 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5619 if ((i
.types
[op
].bitfield
.imm32
)
5620 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5623 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5624 ^ ((offsetT
) 1 << 31))
5625 - ((offsetT
) 1 << 31));
5629 = operand_type_or (i
.types
[op
],
5630 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5632 /* We must avoid matching of Imm32 templates when 64bit
5633 only immediate is available. */
5634 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5635 i
.types
[op
].bitfield
.imm32
= 0;
5642 /* Symbols and expressions. */
5644 /* Convert symbolic operand to proper sizes for matching, but don't
5645 prevent matching a set of insns that only supports sizes other
5646 than those matching the insn suffix. */
5648 i386_operand_type mask
, allowed
;
5649 const insn_template
*t
;
5651 operand_type_set (&mask
, 0);
5652 operand_type_set (&allowed
, 0);
5654 for (t
= current_templates
->start
;
5655 t
< current_templates
->end
;
5658 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5659 allowed
= operand_type_and (allowed
, anyimm
);
5661 switch (guess_suffix
)
5663 case QWORD_MNEM_SUFFIX
:
5664 mask
.bitfield
.imm64
= 1;
5665 mask
.bitfield
.imm32s
= 1;
5667 case LONG_MNEM_SUFFIX
:
5668 mask
.bitfield
.imm32
= 1;
5670 case WORD_MNEM_SUFFIX
:
5671 mask
.bitfield
.imm16
= 1;
5673 case BYTE_MNEM_SUFFIX
:
5674 mask
.bitfield
.imm8
= 1;
5679 allowed
= operand_type_and (mask
, allowed
);
5680 if (!operand_type_all_zero (&allowed
))
5681 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5688 /* Try to use the smallest displacement type too. */
5690 optimize_disp (void)
5694 for (op
= i
.operands
; --op
>= 0;)
5695 if (operand_type_check (i
.types
[op
], disp
))
5697 if (i
.op
[op
].disps
->X_op
== O_constant
)
5699 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5701 if (i
.types
[op
].bitfield
.disp16
5702 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5704 /* If this operand is at most 16 bits, convert
5705 to a signed 16 bit number and don't use 64bit
5707 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5708 i
.types
[op
].bitfield
.disp64
= 0;
5711 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5712 if (i
.types
[op
].bitfield
.disp32
5713 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5715 /* If this operand is at most 32 bits, convert
5716 to a signed 32 bit number and don't use 64bit
5718 op_disp
&= (((offsetT
) 2 << 31) - 1);
5719 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5720 i
.types
[op
].bitfield
.disp64
= 0;
5723 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5725 i
.types
[op
].bitfield
.disp8
= 0;
5726 i
.types
[op
].bitfield
.disp16
= 0;
5727 i
.types
[op
].bitfield
.disp32
= 0;
5728 i
.types
[op
].bitfield
.disp32s
= 0;
5729 i
.types
[op
].bitfield
.disp64
= 0;
5733 else if (flag_code
== CODE_64BIT
)
5735 if (fits_in_signed_long (op_disp
))
5737 i
.types
[op
].bitfield
.disp64
= 0;
5738 i
.types
[op
].bitfield
.disp32s
= 1;
5740 if (i
.prefix
[ADDR_PREFIX
]
5741 && fits_in_unsigned_long (op_disp
))
5742 i
.types
[op
].bitfield
.disp32
= 1;
5744 if ((i
.types
[op
].bitfield
.disp32
5745 || i
.types
[op
].bitfield
.disp32s
5746 || i
.types
[op
].bitfield
.disp16
)
5747 && fits_in_disp8 (op_disp
))
5748 i
.types
[op
].bitfield
.disp8
= 1;
5750 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5751 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5753 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5754 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5755 i
.types
[op
].bitfield
.disp8
= 0;
5756 i
.types
[op
].bitfield
.disp16
= 0;
5757 i
.types
[op
].bitfield
.disp32
= 0;
5758 i
.types
[op
].bitfield
.disp32s
= 0;
5759 i
.types
[op
].bitfield
.disp64
= 0;
5762 /* We only support 64bit displacement on constants. */
5763 i
.types
[op
].bitfield
.disp64
= 0;
5767 /* Return 1 if there is a match in broadcast bytes between operand
5768 GIVEN and instruction template T. */
5771 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5773 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5774 && i
.types
[given
].bitfield
.byte
)
5775 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5776 && i
.types
[given
].bitfield
.word
)
5777 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5778 && i
.types
[given
].bitfield
.dword
)
5779 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5780 && i
.types
[given
].bitfield
.qword
));
5783 /* Check if operands are valid for the instruction. */
5786 check_VecOperands (const insn_template
*t
)
5791 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5792 any one operand are implicity requiring AVX512VL support if the actual
5793 operand size is YMMword or XMMword. Since this function runs after
5794 template matching, there's no need to check for YMMword/XMMword in
5796 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5797 if (!cpu_flags_all_zero (&cpu
)
5798 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5799 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5801 for (op
= 0; op
< t
->operands
; ++op
)
5803 if (t
->operand_types
[op
].bitfield
.zmmword
5804 && (i
.types
[op
].bitfield
.ymmword
5805 || i
.types
[op
].bitfield
.xmmword
))
5807 i
.error
= unsupported
;
5813 /* Without VSIB byte, we can't have a vector register for index. */
5814 if (!t
->opcode_modifier
.sib
5816 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5817 || i
.index_reg
->reg_type
.bitfield
.ymmword
5818 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5820 i
.error
= unsupported_vector_index_register
;
5824 /* Check if default mask is allowed. */
5825 if (t
->opcode_modifier
.nodefmask
5826 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5828 i
.error
= no_default_mask
;
5832 /* For VSIB byte, we need a vector register for index, and all vector
5833 registers must be distinct. */
5834 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
5837 || !((t
->opcode_modifier
.sib
== VECSIB128
5838 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5839 || (t
->opcode_modifier
.sib
== VECSIB256
5840 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5841 || (t
->opcode_modifier
.sib
== VECSIB512
5842 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5844 i
.error
= invalid_vsib_address
;
5848 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5849 if (i
.reg_operands
== 2 && !i
.mask
)
5851 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5852 gas_assert (i
.types
[0].bitfield
.xmmword
5853 || i
.types
[0].bitfield
.ymmword
);
5854 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5855 gas_assert (i
.types
[2].bitfield
.xmmword
5856 || i
.types
[2].bitfield
.ymmword
);
5857 if (operand_check
== check_none
)
5859 if (register_number (i
.op
[0].regs
)
5860 != register_number (i
.index_reg
)
5861 && register_number (i
.op
[2].regs
)
5862 != register_number (i
.index_reg
)
5863 && register_number (i
.op
[0].regs
)
5864 != register_number (i
.op
[2].regs
))
5866 if (operand_check
== check_error
)
5868 i
.error
= invalid_vector_register_set
;
5871 as_warn (_("mask, index, and destination registers should be distinct"));
5873 else if (i
.reg_operands
== 1 && i
.mask
)
5875 if (i
.types
[1].bitfield
.class == RegSIMD
5876 && (i
.types
[1].bitfield
.xmmword
5877 || i
.types
[1].bitfield
.ymmword
5878 || i
.types
[1].bitfield
.zmmword
)
5879 && (register_number (i
.op
[1].regs
)
5880 == register_number (i
.index_reg
)))
5882 if (operand_check
== check_error
)
5884 i
.error
= invalid_vector_register_set
;
5887 if (operand_check
!= check_none
)
5888 as_warn (_("index and destination registers should be distinct"));
5893 /* For AMX instructions with three tmmword operands, all tmmword operand must be
5895 if (t
->operand_types
[0].bitfield
.tmmword
5896 && i
.reg_operands
== 3)
5898 if (register_number (i
.op
[0].regs
)
5899 == register_number (i
.op
[1].regs
)
5900 || register_number (i
.op
[0].regs
)
5901 == register_number (i
.op
[2].regs
)
5902 || register_number (i
.op
[1].regs
)
5903 == register_number (i
.op
[2].regs
))
5905 i
.error
= invalid_tmm_register_set
;
5910 /* Check if broadcast is supported by the instruction and is applied
5911 to the memory operand. */
5914 i386_operand_type type
, overlap
;
5916 /* Check if specified broadcast is supported in this instruction,
5917 and its broadcast bytes match the memory operand. */
5918 op
= i
.broadcast
->operand
;
5919 if (!t
->opcode_modifier
.broadcast
5920 || !(i
.flags
[op
] & Operand_Mem
)
5921 || (!i
.types
[op
].bitfield
.unspecified
5922 && !match_broadcast_size (t
, op
)))
5925 i
.error
= unsupported_broadcast
;
5929 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5930 * i
.broadcast
->type
);
5931 operand_type_set (&type
, 0);
5932 switch (i
.broadcast
->bytes
)
5935 type
.bitfield
.word
= 1;
5938 type
.bitfield
.dword
= 1;
5941 type
.bitfield
.qword
= 1;
5944 type
.bitfield
.xmmword
= 1;
5947 type
.bitfield
.ymmword
= 1;
5950 type
.bitfield
.zmmword
= 1;
5956 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5957 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
5958 && t
->operand_types
[op
].bitfield
.byte
5959 + t
->operand_types
[op
].bitfield
.word
5960 + t
->operand_types
[op
].bitfield
.dword
5961 + t
->operand_types
[op
].bitfield
.qword
> 1)
5963 overlap
.bitfield
.xmmword
= 0;
5964 overlap
.bitfield
.ymmword
= 0;
5965 overlap
.bitfield
.zmmword
= 0;
5967 if (operand_type_all_zero (&overlap
))
5970 if (t
->opcode_modifier
.checkregsize
)
5974 type
.bitfield
.baseindex
= 1;
5975 for (j
= 0; j
< i
.operands
; ++j
)
5978 && !operand_type_register_match(i
.types
[j
],
5979 t
->operand_types
[j
],
5981 t
->operand_types
[op
]))
5986 /* If broadcast is supported in this instruction, we need to check if
5987 operand of one-element size isn't specified without broadcast. */
5988 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5990 /* Find memory operand. */
5991 for (op
= 0; op
< i
.operands
; op
++)
5992 if (i
.flags
[op
] & Operand_Mem
)
5994 gas_assert (op
< i
.operands
);
5995 /* Check size of the memory operand. */
5996 if (match_broadcast_size (t
, op
))
5998 i
.error
= broadcast_needed
;
6003 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6005 /* Check if requested masking is supported. */
6008 switch (t
->opcode_modifier
.masking
)
6012 case MERGING_MASKING
:
6013 if (i
.mask
->zeroing
)
6016 i
.error
= unsupported_masking
;
6020 case DYNAMIC_MASKING
:
6021 /* Memory destinations allow only merging masking. */
6022 if (i
.mask
->zeroing
&& i
.mem_operands
)
6024 /* Find memory operand. */
6025 for (op
= 0; op
< i
.operands
; op
++)
6026 if (i
.flags
[op
] & Operand_Mem
)
6028 gas_assert (op
< i
.operands
);
6029 if (op
== i
.operands
- 1)
6031 i
.error
= unsupported_masking
;
6041 /* Check if masking is applied to dest operand. */
6042 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
6044 i
.error
= mask_not_on_destination
;
6051 if (!t
->opcode_modifier
.sae
6052 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
6054 i
.error
= unsupported_rc_sae
;
6057 /* If the instruction has several immediate operands and one of
6058 them is rounding, the rounding operand should be the last
6059 immediate operand. */
6060 if (i
.imm_operands
> 1
6061 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
6063 i
.error
= rc_sae_operand_not_last_imm
;
6068 /* Check the special Imm4 cases; must be the first operand. */
6069 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6071 if (i
.op
[0].imms
->X_op
!= O_constant
6072 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6078 /* Turn off Imm<N> so that update_imm won't complain. */
6079 operand_type_set (&i
.types
[0], 0);
6082 /* Check vector Disp8 operand. */
6083 if (t
->opcode_modifier
.disp8memshift
6084 && i
.disp_encoding
!= disp_encoding_32bit
)
6087 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6088 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6089 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6092 const i386_operand_type
*type
= NULL
;
6095 for (op
= 0; op
< i
.operands
; op
++)
6096 if (i
.flags
[op
] & Operand_Mem
)
6098 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6099 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6100 else if (t
->operand_types
[op
].bitfield
.xmmword
6101 + t
->operand_types
[op
].bitfield
.ymmword
6102 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6103 type
= &t
->operand_types
[op
];
6104 else if (!i
.types
[op
].bitfield
.unspecified
)
6105 type
= &i
.types
[op
];
6107 else if (i
.types
[op
].bitfield
.class == RegSIMD
6108 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6110 if (i
.types
[op
].bitfield
.zmmword
)
6112 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6114 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6120 if (type
->bitfield
.zmmword
)
6122 else if (type
->bitfield
.ymmword
)
6124 else if (type
->bitfield
.xmmword
)
6128 /* For the check in fits_in_disp8(). */
6129 if (i
.memshift
== 0)
6133 for (op
= 0; op
< i
.operands
; op
++)
6134 if (operand_type_check (i
.types
[op
], disp
)
6135 && i
.op
[op
].disps
->X_op
== O_constant
)
6137 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6139 i
.types
[op
].bitfield
.disp8
= 1;
6142 i
.types
[op
].bitfield
.disp8
= 0;
6151 /* Check if encoding requirements are met by the instruction. */
6154 VEX_check_encoding (const insn_template
*t
)
6156 if (i
.vec_encoding
== vex_encoding_error
)
6158 i
.error
= unsupported
;
6162 if (i
.vec_encoding
== vex_encoding_evex
)
6164 /* This instruction must be encoded with EVEX prefix. */
6165 if (!is_evex_encoding (t
))
6167 i
.error
= unsupported
;
6173 if (!t
->opcode_modifier
.vex
)
6175 /* This instruction template doesn't have VEX prefix. */
6176 if (i
.vec_encoding
!= vex_encoding_default
)
6178 i
.error
= unsupported
;
6187 static const insn_template
*
6188 match_template (char mnem_suffix
)
6190 /* Points to template once we've found it. */
6191 const insn_template
*t
;
6192 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6193 i386_operand_type overlap4
;
6194 unsigned int found_reverse_match
;
6195 i386_opcode_modifier suffix_check
;
6196 i386_operand_type operand_types
[MAX_OPERANDS
];
6197 int addr_prefix_disp
;
6198 unsigned int j
, size_match
, check_register
;
6199 enum i386_error specific_error
= 0;
6201 #if MAX_OPERANDS != 5
6202 # error "MAX_OPERANDS must be 5."
6205 found_reverse_match
= 0;
6206 addr_prefix_disp
= -1;
6208 /* Prepare for mnemonic suffix check. */
6209 memset (&suffix_check
, 0, sizeof (suffix_check
));
6210 switch (mnem_suffix
)
6212 case BYTE_MNEM_SUFFIX
:
6213 suffix_check
.no_bsuf
= 1;
6215 case WORD_MNEM_SUFFIX
:
6216 suffix_check
.no_wsuf
= 1;
6218 case SHORT_MNEM_SUFFIX
:
6219 suffix_check
.no_ssuf
= 1;
6221 case LONG_MNEM_SUFFIX
:
6222 suffix_check
.no_lsuf
= 1;
6224 case QWORD_MNEM_SUFFIX
:
6225 suffix_check
.no_qsuf
= 1;
6228 /* NB: In Intel syntax, normally we can check for memory operand
6229 size when there is no mnemonic suffix. But jmp and call have
6230 2 different encodings with Dword memory operand size, one with
6231 No_ldSuf and the other without. i.suffix is set to
6232 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
6233 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
6234 suffix_check
.no_ldsuf
= 1;
6237 /* Must have right number of operands. */
6238 i
.error
= number_of_operands_mismatch
;
6240 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6242 addr_prefix_disp
= -1;
6243 found_reverse_match
= 0;
6245 if (i
.operands
!= t
->operands
)
6248 /* Check processor support. */
6249 i
.error
= unsupported
;
6250 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6253 /* Check AT&T mnemonic. */
6254 i
.error
= unsupported_with_intel_mnemonic
;
6255 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6258 /* Check AT&T/Intel syntax. */
6259 i
.error
= unsupported_syntax
;
6260 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6261 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6264 /* Check Intel64/AMD64 ISA. */
6268 /* Default: Don't accept Intel64. */
6269 if (t
->opcode_modifier
.isa64
== INTEL64
)
6273 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6274 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6278 /* -mintel64: Don't accept AMD64. */
6279 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6284 /* Check the suffix. */
6285 i
.error
= invalid_instruction_suffix
;
6286 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
6287 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
6288 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
6289 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
6290 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
6291 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
6294 size_match
= operand_size_match (t
);
6298 /* This is intentionally not
6300 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6302 as the case of a missing * on the operand is accepted (perhaps with
6303 a warning, issued further down). */
6304 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6306 i
.error
= operand_type_mismatch
;
6310 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6311 operand_types
[j
] = t
->operand_types
[j
];
6313 /* In general, don't allow
6314 - 64-bit operands outside of 64-bit mode,
6315 - 32-bit operands on pre-386. */
6316 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6317 if (((i
.suffix
== QWORD_MNEM_SUFFIX
6318 && flag_code
!= CODE_64BIT
6319 && (t
->base_opcode
!= 0x0fc7
6320 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
6321 || (i
.suffix
== LONG_MNEM_SUFFIX
6322 && !cpu_arch_flags
.bitfield
.cpui386
))
6324 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6325 && !intel_float_operand (t
->name
))
6326 : intel_float_operand (t
->name
) != 2)
6327 && (t
->operands
== i
.imm_operands
6328 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6329 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6330 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6331 || (operand_types
[j
].bitfield
.class != RegMMX
6332 && operand_types
[j
].bitfield
.class != RegSIMD
6333 && operand_types
[j
].bitfield
.class != RegMask
))
6334 && !t
->opcode_modifier
.sib
)
6337 /* Do not verify operands when there are none. */
6340 if (VEX_check_encoding (t
))
6342 specific_error
= i
.error
;
6346 /* We've found a match; break out of loop. */
6350 if (!t
->opcode_modifier
.jump
6351 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6353 /* There should be only one Disp operand. */
6354 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6355 if (operand_type_check (operand_types
[j
], disp
))
6357 if (j
< MAX_OPERANDS
)
6359 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6361 addr_prefix_disp
= j
;
6363 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
6364 operand into Disp32/Disp32/Disp16/Disp32 operand. */
6368 override
= !override
;
6371 if (operand_types
[j
].bitfield
.disp32
6372 && operand_types
[j
].bitfield
.disp16
)
6374 operand_types
[j
].bitfield
.disp16
= override
;
6375 operand_types
[j
].bitfield
.disp32
= !override
;
6377 operand_types
[j
].bitfield
.disp32s
= 0;
6378 operand_types
[j
].bitfield
.disp64
= 0;
6382 if (operand_types
[j
].bitfield
.disp32s
6383 || operand_types
[j
].bitfield
.disp64
)
6385 operand_types
[j
].bitfield
.disp64
&= !override
;
6386 operand_types
[j
].bitfield
.disp32s
&= !override
;
6387 operand_types
[j
].bitfield
.disp32
= override
;
6389 operand_types
[j
].bitfield
.disp16
= 0;
6395 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6396 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
6399 /* We check register size if needed. */
6400 if (t
->opcode_modifier
.checkregsize
)
6402 check_register
= (1 << t
->operands
) - 1;
6404 check_register
&= ~(1 << i
.broadcast
->operand
);
6409 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6410 switch (t
->operands
)
6413 if (!operand_type_match (overlap0
, i
.types
[0]))
6417 /* xchg %eax, %eax is a special case. It is an alias for nop
6418 only in 32bit mode and we can use opcode 0x90. In 64bit
6419 mode, we can't use 0x90 for xchg %eax, %eax since it should
6420 zero-extend %eax to %rax. */
6421 if (flag_code
== CODE_64BIT
6422 && t
->base_opcode
== 0x90
6423 && i
.types
[0].bitfield
.instance
== Accum
6424 && i
.types
[0].bitfield
.dword
6425 && i
.types
[1].bitfield
.instance
== Accum
6426 && i
.types
[1].bitfield
.dword
)
6428 /* xrelease mov %eax, <disp> is another special case. It must not
6429 match the accumulator-only encoding of mov. */
6430 if (flag_code
!= CODE_64BIT
6432 && t
->base_opcode
== 0xa0
6433 && i
.types
[0].bitfield
.instance
== Accum
6434 && (i
.flags
[1] & Operand_Mem
))
6439 if (!(size_match
& MATCH_STRAIGHT
))
6441 /* Reverse direction of operands if swapping is possible in the first
6442 place (operands need to be symmetric) and
6443 - the load form is requested, and the template is a store form,
6444 - the store form is requested, and the template is a load form,
6445 - the non-default (swapped) form is requested. */
6446 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6447 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6448 && !operand_type_all_zero (&overlap1
))
6449 switch (i
.dir_encoding
)
6451 case dir_encoding_load
:
6452 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6453 || t
->opcode_modifier
.regmem
)
6457 case dir_encoding_store
:
6458 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6459 && !t
->opcode_modifier
.regmem
)
6463 case dir_encoding_swap
:
6466 case dir_encoding_default
:
6469 /* If we want store form, we skip the current load. */
6470 if ((i
.dir_encoding
== dir_encoding_store
6471 || i
.dir_encoding
== dir_encoding_swap
)
6472 && i
.mem_operands
== 0
6473 && t
->opcode_modifier
.load
)
6478 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6479 if (!operand_type_match (overlap0
, i
.types
[0])
6480 || !operand_type_match (overlap1
, i
.types
[1])
6481 || ((check_register
& 3) == 3
6482 && !operand_type_register_match (i
.types
[0],
6487 /* Check if other direction is valid ... */
6488 if (!t
->opcode_modifier
.d
)
6492 if (!(size_match
& MATCH_REVERSE
))
6494 /* Try reversing direction of operands. */
6495 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6496 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6497 if (!operand_type_match (overlap0
, i
.types
[0])
6498 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6500 && !operand_type_register_match (i
.types
[0],
6501 operand_types
[i
.operands
- 1],
6502 i
.types
[i
.operands
- 1],
6505 /* Does not match either direction. */
6508 /* found_reverse_match holds which of D or FloatR
6510 if (!t
->opcode_modifier
.d
)
6511 found_reverse_match
= 0;
6512 else if (operand_types
[0].bitfield
.tbyte
)
6513 found_reverse_match
= Opcode_FloatD
;
6514 else if (operand_types
[0].bitfield
.xmmword
6515 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6516 || operand_types
[0].bitfield
.class == RegMMX
6517 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6518 || is_any_vex_encoding(t
))
6519 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6520 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6522 found_reverse_match
= Opcode_D
;
6523 if (t
->opcode_modifier
.floatr
)
6524 found_reverse_match
|= Opcode_FloatR
;
6528 /* Found a forward 2 operand match here. */
6529 switch (t
->operands
)
6532 overlap4
= operand_type_and (i
.types
[4],
6536 overlap3
= operand_type_and (i
.types
[3],
6540 overlap2
= operand_type_and (i
.types
[2],
6545 switch (t
->operands
)
6548 if (!operand_type_match (overlap4
, i
.types
[4])
6549 || !operand_type_register_match (i
.types
[3],
6556 if (!operand_type_match (overlap3
, i
.types
[3])
6557 || ((check_register
& 0xa) == 0xa
6558 && !operand_type_register_match (i
.types
[1],
6562 || ((check_register
& 0xc) == 0xc
6563 && !operand_type_register_match (i
.types
[2],
6570 /* Here we make use of the fact that there are no
6571 reverse match 3 operand instructions. */
6572 if (!operand_type_match (overlap2
, i
.types
[2])
6573 || ((check_register
& 5) == 5
6574 && !operand_type_register_match (i
.types
[0],
6578 || ((check_register
& 6) == 6
6579 && !operand_type_register_match (i
.types
[1],
6587 /* Found either forward/reverse 2, 3 or 4 operand match here:
6588 slip through to break. */
6591 /* Check if vector operands are valid. */
6592 if (check_VecOperands (t
))
6594 specific_error
= i
.error
;
6598 /* Check if VEX/EVEX encoding requirements can be satisfied. */
6599 if (VEX_check_encoding (t
))
6601 specific_error
= i
.error
;
6605 /* We've found a match; break out of loop. */
6609 if (t
== current_templates
->end
)
6611 /* We found no match. */
6612 const char *err_msg
;
6613 switch (specific_error
? specific_error
: i
.error
)
6617 case operand_size_mismatch
:
6618 err_msg
= _("operand size mismatch");
6620 case operand_type_mismatch
:
6621 err_msg
= _("operand type mismatch");
6623 case register_type_mismatch
:
6624 err_msg
= _("register type mismatch");
6626 case number_of_operands_mismatch
:
6627 err_msg
= _("number of operands mismatch");
6629 case invalid_instruction_suffix
:
6630 err_msg
= _("invalid instruction suffix");
6633 err_msg
= _("constant doesn't fit in 4 bits");
6635 case unsupported_with_intel_mnemonic
:
6636 err_msg
= _("unsupported with Intel mnemonic");
6638 case unsupported_syntax
:
6639 err_msg
= _("unsupported syntax");
6642 as_bad (_("unsupported instruction `%s'"),
6643 current_templates
->start
->name
);
6645 case invalid_sib_address
:
6646 err_msg
= _("invalid SIB address");
6648 case invalid_vsib_address
:
6649 err_msg
= _("invalid VSIB address");
6651 case invalid_vector_register_set
:
6652 err_msg
= _("mask, index, and destination registers must be distinct");
6654 case invalid_tmm_register_set
:
6655 err_msg
= _("all tmm registers must be distinct");
6657 case unsupported_vector_index_register
:
6658 err_msg
= _("unsupported vector index register");
6660 case unsupported_broadcast
:
6661 err_msg
= _("unsupported broadcast");
6663 case broadcast_needed
:
6664 err_msg
= _("broadcast is needed for operand of such type");
6666 case unsupported_masking
:
6667 err_msg
= _("unsupported masking");
6669 case mask_not_on_destination
:
6670 err_msg
= _("mask not on destination operand");
6672 case no_default_mask
:
6673 err_msg
= _("default mask isn't allowed");
6675 case unsupported_rc_sae
:
6676 err_msg
= _("unsupported static rounding/sae");
6678 case rc_sae_operand_not_last_imm
:
6680 err_msg
= _("RC/SAE operand must precede immediate operands");
6682 err_msg
= _("RC/SAE operand must follow immediate operands");
6684 case invalid_register_operand
:
6685 err_msg
= _("invalid register operand");
6688 as_bad (_("%s for `%s'"), err_msg
,
6689 current_templates
->start
->name
);
6693 if (!quiet_warnings
)
6696 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6697 as_warn (_("indirect %s without `*'"), t
->name
);
6699 if (t
->opcode_modifier
.isprefix
6700 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6702 /* Warn them that a data or address size prefix doesn't
6703 affect assembly of the next line of code. */
6704 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6708 /* Copy the template we found. */
6711 if (addr_prefix_disp
!= -1)
6712 i
.tm
.operand_types
[addr_prefix_disp
]
6713 = operand_types
[addr_prefix_disp
];
6715 if (found_reverse_match
)
6717 /* If we found a reverse match we must alter the opcode direction
6718 bit and clear/flip the regmem modifier one. found_reverse_match
6719 holds bits to change (different for int & float insns). */
6721 i
.tm
.base_opcode
^= found_reverse_match
;
6723 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6724 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6726 /* Certain SIMD insns have their load forms specified in the opcode
6727 table, and hence we need to _set_ RegMem instead of clearing it.
6728 We need to avoid setting the bit though on insns like KMOVW. */
6729 i
.tm
.opcode_modifier
.regmem
6730 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6731 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6732 && !i
.tm
.opcode_modifier
.regmem
;
6741 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6742 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6744 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6746 as_bad (_("`%s' operand %u must use `%ses' segment"),
6748 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6753 /* There's only ever one segment override allowed per instruction.
6754 This instruction possibly has a legal segment override on the
6755 second operand, so copy the segment to where non-string
6756 instructions store it, allowing common code. */
6757 i
.seg
[op
] = i
.seg
[1];
6763 process_suffix (void)
6765 /* If matched instruction specifies an explicit instruction mnemonic
6767 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6768 i
.suffix
= WORD_MNEM_SUFFIX
;
6769 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6770 i
.suffix
= LONG_MNEM_SUFFIX
;
6771 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6772 i
.suffix
= QWORD_MNEM_SUFFIX
;
6773 else if (i
.reg_operands
6774 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6775 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6777 unsigned int numop
= i
.operands
;
6779 /* movsx/movzx want only their source operand considered here, for the
6780 ambiguity checking below. The suffix will be replaced afterwards
6781 to represent the destination (register). */
6782 if (((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
)
6783 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6786 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6787 if (i
.tm
.base_opcode
== 0xf20f38f0
6788 && i
.tm
.operand_types
[1].bitfield
.qword
)
6791 /* If there's no instruction mnemonic suffix we try to invent one
6792 based on GPR operands. */
6795 /* We take i.suffix from the last register operand specified,
6796 Destination register type is more significant than source
6797 register type. crc32 in SSE4.2 prefers source register
6799 unsigned int op
= i
.tm
.base_opcode
!= 0xf20f38f0 ? i
.operands
: 1;
6802 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6803 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6805 if (i
.types
[op
].bitfield
.class != Reg
)
6807 if (i
.types
[op
].bitfield
.byte
)
6808 i
.suffix
= BYTE_MNEM_SUFFIX
;
6809 else if (i
.types
[op
].bitfield
.word
)
6810 i
.suffix
= WORD_MNEM_SUFFIX
;
6811 else if (i
.types
[op
].bitfield
.dword
)
6812 i
.suffix
= LONG_MNEM_SUFFIX
;
6813 else if (i
.types
[op
].bitfield
.qword
)
6814 i
.suffix
= QWORD_MNEM_SUFFIX
;
6820 /* As an exception, movsx/movzx silently default to a byte source
6822 if ((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
6823 && !i
.suffix
&& !intel_syntax
)
6824 i
.suffix
= BYTE_MNEM_SUFFIX
;
6826 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6829 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6830 && i
.tm
.opcode_modifier
.no_bsuf
)
6832 else if (!check_byte_reg ())
6835 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6838 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6839 && i
.tm
.opcode_modifier
.no_lsuf
6840 && !i
.tm
.opcode_modifier
.todword
6841 && !i
.tm
.opcode_modifier
.toqword
)
6843 else if (!check_long_reg ())
6846 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6849 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6850 && i
.tm
.opcode_modifier
.no_qsuf
6851 && !i
.tm
.opcode_modifier
.todword
6852 && !i
.tm
.opcode_modifier
.toqword
)
6854 else if (!check_qword_reg ())
6857 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6860 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6861 && i
.tm
.opcode_modifier
.no_wsuf
)
6863 else if (!check_word_reg ())
6866 else if (intel_syntax
6867 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6868 /* Do nothing if the instruction is going to ignore the prefix. */
6873 /* Undo the movsx/movzx change done above. */
6876 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
6879 i
.suffix
= stackop_size
;
6880 if (stackop_size
== LONG_MNEM_SUFFIX
)
6882 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6883 .code16gcc directive to support 16-bit mode with
6884 32-bit address. For IRET without a suffix, generate
6885 16-bit IRET (opcode 0xcf) to return from an interrupt
6887 if (i
.tm
.base_opcode
== 0xcf)
6889 i
.suffix
= WORD_MNEM_SUFFIX
;
6890 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6892 /* Warn about changed behavior for segment register push/pop. */
6893 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6894 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6899 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6900 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6901 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6902 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6903 && i
.tm
.extension_opcode
<= 3)))
6908 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6910 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6911 || i
.tm
.opcode_modifier
.no_lsuf
)
6912 i
.suffix
= QWORD_MNEM_SUFFIX
;
6917 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6918 i
.suffix
= LONG_MNEM_SUFFIX
;
6921 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6922 i
.suffix
= WORD_MNEM_SUFFIX
;
6928 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6929 /* Also cover lret/retf/iret in 64-bit mode. */
6930 || (flag_code
== CODE_64BIT
6931 && !i
.tm
.opcode_modifier
.no_lsuf
6932 && !i
.tm
.opcode_modifier
.no_qsuf
))
6933 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6934 /* Explicit sizing prefixes are assumed to disambiguate insns. */
6935 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
6936 /* Accept FLDENV et al without suffix. */
6937 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6939 unsigned int suffixes
, evex
= 0;
6941 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6942 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6944 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6946 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6948 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6950 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6953 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6954 also suitable for AT&T syntax mode, it was requested that this be
6955 restricted to just Intel syntax. */
6956 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
)
6960 for (op
= 0; op
< i
.tm
.operands
; ++op
)
6962 if (is_evex_encoding (&i
.tm
)
6963 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6965 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6966 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
6967 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6968 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
6969 if (!i
.tm
.opcode_modifier
.evex
6970 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
6971 i
.tm
.opcode_modifier
.evex
= EVEX512
;
6974 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
6975 + i
.tm
.operand_types
[op
].bitfield
.ymmword
6976 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
6979 /* Any properly sized operand disambiguates the insn. */
6980 if (i
.types
[op
].bitfield
.xmmword
6981 || i
.types
[op
].bitfield
.ymmword
6982 || i
.types
[op
].bitfield
.zmmword
)
6984 suffixes
&= ~(7 << 6);
6989 if ((i
.flags
[op
] & Operand_Mem
)
6990 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
6992 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
6994 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6996 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6998 if (is_evex_encoding (&i
.tm
))
7004 /* Are multiple suffixes / operand sizes allowed? */
7005 if (suffixes
& (suffixes
- 1))
7008 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7009 || operand_check
== check_error
))
7011 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
7014 if (operand_check
== check_error
)
7016 as_bad (_("no instruction mnemonic suffix given and "
7017 "no register operands; can't size `%s'"), i
.tm
.name
);
7020 if (operand_check
== check_warning
)
7021 as_warn (_("%s; using default for `%s'"),
7023 ? _("ambiguous operand size")
7024 : _("no instruction mnemonic suffix given and "
7025 "no register operands"),
7028 if (i
.tm
.opcode_modifier
.floatmf
)
7029 i
.suffix
= SHORT_MNEM_SUFFIX
;
7030 else if ((i
.tm
.base_opcode
| 8) == 0xfbe
7031 || (i
.tm
.base_opcode
== 0x63
7032 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
7033 /* handled below */;
7035 i
.tm
.opcode_modifier
.evex
= evex
;
7036 else if (flag_code
== CODE_16BIT
)
7037 i
.suffix
= WORD_MNEM_SUFFIX
;
7038 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7039 i
.suffix
= LONG_MNEM_SUFFIX
;
7041 i
.suffix
= QWORD_MNEM_SUFFIX
;
7045 if ((i
.tm
.base_opcode
| 8) == 0xfbe
7046 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
7048 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7049 In AT&T syntax, if there is no suffix (warned about above), the default
7050 will be byte extension. */
7051 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7052 i
.tm
.base_opcode
|= 1;
7054 /* For further processing, the suffix should represent the destination
7055 (register). This is already the case when one was used with
7056 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7057 no suffix to begin with. */
7058 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7060 if (i
.types
[1].bitfield
.word
)
7061 i
.suffix
= WORD_MNEM_SUFFIX
;
7062 else if (i
.types
[1].bitfield
.qword
)
7063 i
.suffix
= QWORD_MNEM_SUFFIX
;
7065 i
.suffix
= LONG_MNEM_SUFFIX
;
7067 i
.tm
.opcode_modifier
.w
= 0;
7071 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7072 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7073 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7075 /* Change the opcode based on the operand size given by i.suffix. */
7078 /* Size floating point instruction. */
7079 case LONG_MNEM_SUFFIX
:
7080 if (i
.tm
.opcode_modifier
.floatmf
)
7082 i
.tm
.base_opcode
^= 4;
7086 case WORD_MNEM_SUFFIX
:
7087 case QWORD_MNEM_SUFFIX
:
7088 /* It's not a byte, select word/dword operation. */
7089 if (i
.tm
.opcode_modifier
.w
)
7092 i
.tm
.base_opcode
|= 8;
7094 i
.tm
.base_opcode
|= 1;
7097 case SHORT_MNEM_SUFFIX
:
7098 /* Now select between word & dword operations via the operand
7099 size prefix, except for instructions that will ignore this
7101 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7102 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7103 && !i
.tm
.opcode_modifier
.floatmf
7104 && !is_any_vex_encoding (&i
.tm
)
7105 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7106 || (flag_code
== CODE_64BIT
7107 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7109 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7111 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7112 prefix
= ADDR_PREFIX_OPCODE
;
7114 if (!add_prefix (prefix
))
7118 /* Set mode64 for an operand. */
7119 if (i
.suffix
== QWORD_MNEM_SUFFIX
7120 && flag_code
== CODE_64BIT
7121 && !i
.tm
.opcode_modifier
.norex64
7122 && !i
.tm
.opcode_modifier
.vexw
7123 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7125 && ! (i
.operands
== 2
7126 && i
.tm
.base_opcode
== 0x90
7127 && i
.tm
.extension_opcode
== None
7128 && i
.types
[0].bitfield
.instance
== Accum
7129 && i
.types
[0].bitfield
.qword
7130 && i
.types
[1].bitfield
.instance
== Accum
7131 && i
.types
[1].bitfield
.qword
))
7137 /* Select word/dword/qword operation with explict data sizing prefix
7138 when there are no suitable register operands. */
7139 if (i
.tm
.opcode_modifier
.w
7140 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7142 || (i
.reg_operands
== 1
7144 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7146 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7147 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7149 || i
.tm
.base_opcode
== 0xf20f38f0))))
7150 i
.tm
.base_opcode
|= 1;
7154 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
7156 gas_assert (!i
.suffix
);
7157 gas_assert (i
.reg_operands
);
7159 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7162 /* The address size override prefix changes the size of the
7164 if (flag_code
== CODE_64BIT
7165 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7167 as_bad (_("16-bit addressing unavailable for `%s'"),
7172 if ((flag_code
== CODE_32BIT
7173 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7174 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7175 && !add_prefix (ADDR_PREFIX_OPCODE
))
7180 /* Check invalid register operand when the address size override
7181 prefix changes the size of register operands. */
7183 enum { need_word
, need_dword
, need_qword
} need
;
7185 if (flag_code
== CODE_32BIT
)
7186 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7187 else if (i
.prefix
[ADDR_PREFIX
])
7190 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7192 for (op
= 0; op
< i
.operands
; op
++)
7194 if (i
.types
[op
].bitfield
.class != Reg
)
7200 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7204 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7208 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7213 as_bad (_("invalid register operand size for `%s'"),
7224 check_byte_reg (void)
7228 for (op
= i
.operands
; --op
>= 0;)
7230 /* Skip non-register operands. */
7231 if (i
.types
[op
].bitfield
.class != Reg
)
7234 /* If this is an eight bit register, it's OK. If it's the 16 or
7235 32 bit version of an eight bit register, we will just use the
7236 low portion, and that's OK too. */
7237 if (i
.types
[op
].bitfield
.byte
)
7240 /* I/O port address operands are OK too. */
7241 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7242 && i
.tm
.operand_types
[op
].bitfield
.word
)
7245 /* crc32 only wants its source operand checked here. */
7246 if (i
.tm
.base_opcode
== 0xf20f38f0 && op
)
7249 /* Any other register is bad. */
7250 as_bad (_("`%s%s' not allowed with `%s%c'"),
7251 register_prefix
, i
.op
[op
].regs
->reg_name
,
7252 i
.tm
.name
, i
.suffix
);
7259 check_long_reg (void)
7263 for (op
= i
.operands
; --op
>= 0;)
7264 /* Skip non-register operands. */
7265 if (i
.types
[op
].bitfield
.class != Reg
)
7267 /* Reject eight bit registers, except where the template requires
7268 them. (eg. movzb) */
7269 else if (i
.types
[op
].bitfield
.byte
7270 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7271 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7272 && (i
.tm
.operand_types
[op
].bitfield
.word
7273 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7275 as_bad (_("`%s%s' not allowed with `%s%c'"),
7277 i
.op
[op
].regs
->reg_name
,
7282 /* Error if the e prefix on a general reg is missing. */
7283 else if (i
.types
[op
].bitfield
.word
7284 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7285 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7286 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7288 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7289 register_prefix
, i
.op
[op
].regs
->reg_name
,
7293 /* Warn if the r prefix on a general reg is present. */
7294 else if (i
.types
[op
].bitfield
.qword
7295 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7296 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7297 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7300 && i
.tm
.opcode_modifier
.toqword
7301 && i
.types
[0].bitfield
.class != RegSIMD
)
7303 /* Convert to QWORD. We want REX byte. */
7304 i
.suffix
= QWORD_MNEM_SUFFIX
;
7308 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7309 register_prefix
, i
.op
[op
].regs
->reg_name
,
7318 check_qword_reg (void)
7322 for (op
= i
.operands
; --op
>= 0; )
7323 /* Skip non-register operands. */
7324 if (i
.types
[op
].bitfield
.class != Reg
)
7326 /* Reject eight bit registers, except where the template requires
7327 them. (eg. movzb) */
7328 else if (i
.types
[op
].bitfield
.byte
7329 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7330 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7331 && (i
.tm
.operand_types
[op
].bitfield
.word
7332 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7334 as_bad (_("`%s%s' not allowed with `%s%c'"),
7336 i
.op
[op
].regs
->reg_name
,
7341 /* Warn if the r prefix on a general reg is missing. */
7342 else if ((i
.types
[op
].bitfield
.word
7343 || i
.types
[op
].bitfield
.dword
)
7344 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7345 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7346 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7348 /* Prohibit these changes in the 64bit mode, since the
7349 lowering is more complicated. */
7351 && i
.tm
.opcode_modifier
.todword
7352 && i
.types
[0].bitfield
.class != RegSIMD
)
7354 /* Convert to DWORD. We don't want REX byte. */
7355 i
.suffix
= LONG_MNEM_SUFFIX
;
7359 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7360 register_prefix
, i
.op
[op
].regs
->reg_name
,
7369 check_word_reg (void)
7372 for (op
= i
.operands
; --op
>= 0;)
7373 /* Skip non-register operands. */
7374 if (i
.types
[op
].bitfield
.class != Reg
)
7376 /* Reject eight bit registers, except where the template requires
7377 them. (eg. movzb) */
7378 else if (i
.types
[op
].bitfield
.byte
7379 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7380 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7381 && (i
.tm
.operand_types
[op
].bitfield
.word
7382 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7384 as_bad (_("`%s%s' not allowed with `%s%c'"),
7386 i
.op
[op
].regs
->reg_name
,
7391 /* Error if the e or r prefix on a general reg is present. */
7392 else if ((i
.types
[op
].bitfield
.dword
7393 || i
.types
[op
].bitfield
.qword
)
7394 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7395 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7396 && i
.tm
.operand_types
[op
].bitfield
.word
)
7398 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7399 register_prefix
, i
.op
[op
].regs
->reg_name
,
7407 update_imm (unsigned int j
)
7409 i386_operand_type overlap
= i
.types
[j
];
7410 if ((overlap
.bitfield
.imm8
7411 || overlap
.bitfield
.imm8s
7412 || overlap
.bitfield
.imm16
7413 || overlap
.bitfield
.imm32
7414 || overlap
.bitfield
.imm32s
7415 || overlap
.bitfield
.imm64
)
7416 && !operand_type_equal (&overlap
, &imm8
)
7417 && !operand_type_equal (&overlap
, &imm8s
)
7418 && !operand_type_equal (&overlap
, &imm16
)
7419 && !operand_type_equal (&overlap
, &imm32
)
7420 && !operand_type_equal (&overlap
, &imm32s
)
7421 && !operand_type_equal (&overlap
, &imm64
))
7425 i386_operand_type temp
;
7427 operand_type_set (&temp
, 0);
7428 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7430 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7431 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7433 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7434 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7435 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7437 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7438 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7441 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7444 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7445 || operand_type_equal (&overlap
, &imm16_32
)
7446 || operand_type_equal (&overlap
, &imm16_32s
))
7448 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7453 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
7454 overlap
= operand_type_and (overlap
, imm32s
);
7455 else if (i
.prefix
[DATA_PREFIX
])
7456 overlap
= operand_type_and (overlap
,
7457 flag_code
!= CODE_16BIT
? imm16
: imm32
);
7458 if (!operand_type_equal (&overlap
, &imm8
)
7459 && !operand_type_equal (&overlap
, &imm8s
)
7460 && !operand_type_equal (&overlap
, &imm16
)
7461 && !operand_type_equal (&overlap
, &imm32
)
7462 && !operand_type_equal (&overlap
, &imm32s
)
7463 && !operand_type_equal (&overlap
, &imm64
))
7465 as_bad (_("no instruction mnemonic suffix given; "
7466 "can't determine immediate size"));
7470 i
.types
[j
] = overlap
;
7480 /* Update the first 2 immediate operands. */
7481 n
= i
.operands
> 2 ? 2 : i
.operands
;
7484 for (j
= 0; j
< n
; j
++)
7485 if (update_imm (j
) == 0)
7488 /* The 3rd operand can't be immediate operand. */
7489 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7496 process_operands (void)
7498 /* Default segment register this instruction will use for memory
7499 accesses. 0 means unknown. This is only for optimizing out
7500 unnecessary segment overrides. */
7501 const seg_entry
*default_seg
= 0;
7503 if (i
.tm
.opcode_modifier
.sse2avx
)
7505 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
7507 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
7508 i
.prefix
[REX_PREFIX
] = 0;
7511 /* ImmExt should be processed after SSE2AVX. */
7512 else if (i
.tm
.opcode_modifier
.immext
)
7515 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7517 unsigned int dupl
= i
.operands
;
7518 unsigned int dest
= dupl
- 1;
7521 /* The destination must be an xmm register. */
7522 gas_assert (i
.reg_operands
7523 && MAX_OPERANDS
> dupl
7524 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7526 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7527 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7529 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7531 /* Keep xmm0 for instructions with VEX prefix and 3
7533 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7534 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7539 /* We remove the first xmm0 and keep the number of
7540 operands unchanged, which in fact duplicates the
7542 for (j
= 1; j
< i
.operands
; j
++)
7544 i
.op
[j
- 1] = i
.op
[j
];
7545 i
.types
[j
- 1] = i
.types
[j
];
7546 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7547 i
.flags
[j
- 1] = i
.flags
[j
];
7551 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7553 gas_assert ((MAX_OPERANDS
- 1) > dupl
7554 && (i
.tm
.opcode_modifier
.vexsources
7557 /* Add the implicit xmm0 for instructions with VEX prefix
7559 for (j
= i
.operands
; j
> 0; j
--)
7561 i
.op
[j
] = i
.op
[j
- 1];
7562 i
.types
[j
] = i
.types
[j
- 1];
7563 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7564 i
.flags
[j
] = i
.flags
[j
- 1];
7567 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
7568 i
.types
[0] = regxmm
;
7569 i
.tm
.operand_types
[0] = regxmm
;
7572 i
.reg_operands
+= 2;
7577 i
.op
[dupl
] = i
.op
[dest
];
7578 i
.types
[dupl
] = i
.types
[dest
];
7579 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7580 i
.flags
[dupl
] = i
.flags
[dest
];
7589 i
.op
[dupl
] = i
.op
[dest
];
7590 i
.types
[dupl
] = i
.types
[dest
];
7591 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7592 i
.flags
[dupl
] = i
.flags
[dest
];
7595 if (i
.tm
.opcode_modifier
.immext
)
7598 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7599 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7603 for (j
= 1; j
< i
.operands
; j
++)
7605 i
.op
[j
- 1] = i
.op
[j
];
7606 i
.types
[j
- 1] = i
.types
[j
];
7608 /* We need to adjust fields in i.tm since they are used by
7609 build_modrm_byte. */
7610 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7612 i
.flags
[j
- 1] = i
.flags
[j
];
7619 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7621 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7623 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7624 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7625 regnum
= register_number (i
.op
[1].regs
);
7626 first_reg_in_group
= regnum
& ~3;
7627 last_reg_in_group
= first_reg_in_group
+ 3;
7628 if (regnum
!= first_reg_in_group
)
7629 as_warn (_("source register `%s%s' implicitly denotes"
7630 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7631 register_prefix
, i
.op
[1].regs
->reg_name
,
7632 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7633 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7636 else if (i
.tm
.opcode_modifier
.regkludge
)
7638 /* The imul $imm, %reg instruction is converted into
7639 imul $imm, %reg, %reg, and the clr %reg instruction
7640 is converted into xor %reg, %reg. */
7642 unsigned int first_reg_op
;
7644 if (operand_type_check (i
.types
[0], reg
))
7648 /* Pretend we saw the extra register operand. */
7649 gas_assert (i
.reg_operands
== 1
7650 && i
.op
[first_reg_op
+ 1].regs
== 0);
7651 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7652 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7657 if (i
.tm
.opcode_modifier
.modrm
)
7659 /* The opcode is completed (modulo i.tm.extension_opcode which
7660 must be put into the modrm byte). Now, we make the modrm and
7661 index base bytes based on all the info we've collected. */
7663 default_seg
= build_modrm_byte ();
7665 else if (i
.types
[0].bitfield
.class == SReg
)
7667 if (flag_code
!= CODE_64BIT
7668 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7669 && i
.op
[0].regs
->reg_num
== 1
7670 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7671 && i
.op
[0].regs
->reg_num
< 4)
7673 as_bad (_("you can't `%s %s%s'"),
7674 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7677 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7679 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7680 i
.tm
.opcode_length
= 2;
7682 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7684 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7688 else if (i
.tm
.opcode_modifier
.isstring
)
7690 /* For the string instructions that allow a segment override
7691 on one of their operands, the default segment is ds. */
7694 else if (i
.short_form
)
7696 /* The register or float register operand is in operand
7698 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7700 /* Register goes in low 3 bits of opcode. */
7701 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7702 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7704 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7706 /* Warn about some common errors, but press on regardless.
7707 The first case can be generated by gcc (<= 2.8.1). */
7708 if (i
.operands
== 2)
7710 /* Reversed arguments on faddp, fsubp, etc. */
7711 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7712 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7713 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7717 /* Extraneous `l' suffix on fp insn. */
7718 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7719 register_prefix
, i
.op
[0].regs
->reg_name
);
7724 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7725 && i
.tm
.base_opcode
== 0x8d /* lea */
7726 && !is_any_vex_encoding(&i
.tm
))
7728 if (!quiet_warnings
)
7729 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7733 i
.prefix
[SEG_PREFIX
] = 0;
7737 /* If a segment was explicitly specified, and the specified segment
7738 is neither the default nor the one already recorded from a prefix,
7739 use an opcode prefix to select it. If we never figured out what
7740 the default segment is, then default_seg will be zero at this
7741 point, and the specified segment prefix will always be used. */
7743 && i
.seg
[0] != default_seg
7744 && i
.seg
[0]->seg_prefix
!= i
.prefix
[SEG_PREFIX
])
7746 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7752 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
7753 bfd_boolean do_sse2avx
)
7755 if (r
->reg_flags
& RegRex
)
7757 if (i
.rex
& rex_bit
)
7758 as_bad (_("same type of prefix used twice"));
7761 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
7763 gas_assert (i
.vex
.register_specifier
== r
);
7764 i
.vex
.register_specifier
+= 8;
7767 if (r
->reg_flags
& RegVRex
)
7771 static const seg_entry
*
7772 build_modrm_byte (void)
7774 const seg_entry
*default_seg
= 0;
7775 unsigned int source
, dest
;
7778 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7781 unsigned int nds
, reg_slot
;
7784 dest
= i
.operands
- 1;
7787 /* There are 2 kinds of instructions:
7788 1. 5 operands: 4 register operands or 3 register operands
7789 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7790 VexW0 or VexW1. The destination must be either XMM, YMM or
7792 2. 4 operands: 4 register operands or 3 register operands
7793 plus 1 memory operand, with VexXDS. */
7794 gas_assert ((i
.reg_operands
== 4
7795 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7796 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7797 && i
.tm
.opcode_modifier
.vexw
7798 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7800 /* If VexW1 is set, the first non-immediate operand is the source and
7801 the second non-immediate one is encoded in the immediate operand. */
7802 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7804 source
= i
.imm_operands
;
7805 reg_slot
= i
.imm_operands
+ 1;
7809 source
= i
.imm_operands
+ 1;
7810 reg_slot
= i
.imm_operands
;
7813 if (i
.imm_operands
== 0)
7815 /* When there is no immediate operand, generate an 8bit
7816 immediate operand to encode the first operand. */
7817 exp
= &im_expressions
[i
.imm_operands
++];
7818 i
.op
[i
.operands
].imms
= exp
;
7819 i
.types
[i
.operands
] = imm8
;
7822 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7823 exp
->X_op
= O_constant
;
7824 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7825 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7829 gas_assert (i
.imm_operands
== 1);
7830 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7831 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7833 /* Turn on Imm8 again so that output_imm will generate it. */
7834 i
.types
[0].bitfield
.imm8
= 1;
7836 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7837 i
.op
[0].imms
->X_add_number
7838 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7839 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7842 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7843 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7848 /* i.reg_operands MUST be the number of real register operands;
7849 implicit registers do not count. If there are 3 register
7850 operands, it must be a instruction with VexNDS. For a
7851 instruction with VexNDD, the destination register is encoded
7852 in VEX prefix. If there are 4 register operands, it must be
7853 a instruction with VEX prefix and 3 sources. */
7854 if (i
.mem_operands
== 0
7855 && ((i
.reg_operands
== 2
7856 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7857 || (i
.reg_operands
== 3
7858 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7859 || (i
.reg_operands
== 4 && vex_3_sources
)))
7867 /* When there are 3 operands, one of them may be immediate,
7868 which may be the first or the last operand. Otherwise,
7869 the first operand must be shift count register (cl) or it
7870 is an instruction with VexNDS. */
7871 gas_assert (i
.imm_operands
== 1
7872 || (i
.imm_operands
== 0
7873 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7874 || (i
.types
[0].bitfield
.instance
== RegC
7875 && i
.types
[0].bitfield
.byte
))));
7876 if (operand_type_check (i
.types
[0], imm
)
7877 || (i
.types
[0].bitfield
.instance
== RegC
7878 && i
.types
[0].bitfield
.byte
))
7884 /* When there are 4 operands, the first two must be 8bit
7885 immediate operands. The source operand will be the 3rd
7888 For instructions with VexNDS, if the first operand
7889 an imm8, the source operand is the 2nd one. If the last
7890 operand is imm8, the source operand is the first one. */
7891 gas_assert ((i
.imm_operands
== 2
7892 && i
.types
[0].bitfield
.imm8
7893 && i
.types
[1].bitfield
.imm8
)
7894 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7895 && i
.imm_operands
== 1
7896 && (i
.types
[0].bitfield
.imm8
7897 || i
.types
[i
.operands
- 1].bitfield
.imm8
7899 if (i
.imm_operands
== 2)
7903 if (i
.types
[0].bitfield
.imm8
)
7910 if (is_evex_encoding (&i
.tm
))
7912 /* For EVEX instructions, when there are 5 operands, the
7913 first one must be immediate operand. If the second one
7914 is immediate operand, the source operand is the 3th
7915 one. If the last one is immediate operand, the source
7916 operand is the 2nd one. */
7917 gas_assert (i
.imm_operands
== 2
7918 && i
.tm
.opcode_modifier
.sae
7919 && operand_type_check (i
.types
[0], imm
));
7920 if (operand_type_check (i
.types
[1], imm
))
7922 else if (operand_type_check (i
.types
[4], imm
))
7936 /* RC/SAE operand could be between DEST and SRC. That happens
7937 when one operand is GPR and the other one is XMM/YMM/ZMM
7939 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7942 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7944 /* For instructions with VexNDS, the register-only source
7945 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7946 register. It is encoded in VEX prefix. */
7948 i386_operand_type op
;
7951 /* Swap two source operands if needed. */
7952 if (i
.tm
.opcode_modifier
.swapsources
)
7960 op
= i
.tm
.operand_types
[vvvv
];
7961 if ((dest
+ 1) >= i
.operands
7962 || ((op
.bitfield
.class != Reg
7963 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7964 && op
.bitfield
.class != RegSIMD
7965 && !operand_type_equal (&op
, ®mask
)))
7967 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7973 /* One of the register operands will be encoded in the i.rm.reg
7974 field, the other in the combined i.rm.mode and i.rm.regmem
7975 fields. If no form of this instruction supports a memory
7976 destination operand, then we assume the source operand may
7977 sometimes be a memory operand and so we need to store the
7978 destination in the i.rm.reg field. */
7979 if (!i
.tm
.opcode_modifier
.regmem
7980 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7982 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7983 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7984 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
7985 set_rex_vrex (i
.op
[source
].regs
, REX_B
, FALSE
);
7989 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7990 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7991 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
7992 set_rex_vrex (i
.op
[source
].regs
, REX_R
, FALSE
);
7994 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7996 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7999 add_prefix (LOCK_PREFIX_OPCODE
);
8003 { /* If it's not 2 reg operands... */
8008 unsigned int fake_zero_displacement
= 0;
8011 for (op
= 0; op
< i
.operands
; op
++)
8012 if (i
.flags
[op
] & Operand_Mem
)
8014 gas_assert (op
< i
.operands
);
8016 if (i
.tm
.opcode_modifier
.sib
)
8018 /* The index register of VSIB shouldn't be RegIZ. */
8019 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8020 && i
.index_reg
->reg_num
== RegIZ
)
8023 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8026 i
.sib
.base
= NO_BASE_REGISTER
;
8027 i
.sib
.scale
= i
.log2_scale_factor
;
8028 i
.types
[op
].bitfield
.disp8
= 0;
8029 i
.types
[op
].bitfield
.disp16
= 0;
8030 i
.types
[op
].bitfield
.disp64
= 0;
8031 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8033 /* Must be 32 bit */
8034 i
.types
[op
].bitfield
.disp32
= 1;
8035 i
.types
[op
].bitfield
.disp32s
= 0;
8039 i
.types
[op
].bitfield
.disp32
= 0;
8040 i
.types
[op
].bitfield
.disp32s
= 1;
8044 /* Since the mandatory SIB always has index register, so
8045 the code logic remains unchanged. The non-mandatory SIB
8046 without index register is allowed and will be handled
8050 if (i
.index_reg
->reg_num
== RegIZ
)
8051 i
.sib
.index
= NO_INDEX_REGISTER
;
8053 i
.sib
.index
= i
.index_reg
->reg_num
;
8054 set_rex_vrex (i
.index_reg
, REX_X
, FALSE
);
8060 if (i
.base_reg
== 0)
8063 if (!i
.disp_operands
)
8064 fake_zero_displacement
= 1;
8065 if (i
.index_reg
== 0)
8067 i386_operand_type newdisp
;
8069 /* Both check for VSIB and mandatory non-vector SIB. */
8070 gas_assert (!i
.tm
.opcode_modifier
.sib
8071 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8072 /* Operand is just <disp> */
8073 if (flag_code
== CODE_64BIT
)
8075 /* 64bit mode overwrites the 32bit absolute
8076 addressing by RIP relative addressing and
8077 absolute addressing is encoded by one of the
8078 redundant SIB forms. */
8079 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8080 i
.sib
.base
= NO_BASE_REGISTER
;
8081 i
.sib
.index
= NO_INDEX_REGISTER
;
8082 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
8084 else if ((flag_code
== CODE_16BIT
)
8085 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8087 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8092 i
.rm
.regmem
= NO_BASE_REGISTER
;
8095 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8096 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
8098 else if (!i
.tm
.opcode_modifier
.sib
)
8100 /* !i.base_reg && i.index_reg */
8101 if (i
.index_reg
->reg_num
== RegIZ
)
8102 i
.sib
.index
= NO_INDEX_REGISTER
;
8104 i
.sib
.index
= i
.index_reg
->reg_num
;
8105 i
.sib
.base
= NO_BASE_REGISTER
;
8106 i
.sib
.scale
= i
.log2_scale_factor
;
8107 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8108 i
.types
[op
].bitfield
.disp8
= 0;
8109 i
.types
[op
].bitfield
.disp16
= 0;
8110 i
.types
[op
].bitfield
.disp64
= 0;
8111 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
8113 /* Must be 32 bit */
8114 i
.types
[op
].bitfield
.disp32
= 1;
8115 i
.types
[op
].bitfield
.disp32s
= 0;
8119 i
.types
[op
].bitfield
.disp32
= 0;
8120 i
.types
[op
].bitfield
.disp32s
= 1;
8122 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8126 /* RIP addressing for 64bit mode. */
8127 else if (i
.base_reg
->reg_num
== RegIP
)
8129 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8130 i
.rm
.regmem
= NO_BASE_REGISTER
;
8131 i
.types
[op
].bitfield
.disp8
= 0;
8132 i
.types
[op
].bitfield
.disp16
= 0;
8133 i
.types
[op
].bitfield
.disp32
= 0;
8134 i
.types
[op
].bitfield
.disp32s
= 1;
8135 i
.types
[op
].bitfield
.disp64
= 0;
8136 i
.flags
[op
] |= Operand_PCrel
;
8137 if (! i
.disp_operands
)
8138 fake_zero_displacement
= 1;
8140 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8142 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8143 switch (i
.base_reg
->reg_num
)
8146 if (i
.index_reg
== 0)
8148 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8149 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8153 if (i
.index_reg
== 0)
8156 if (operand_type_check (i
.types
[op
], disp
) == 0)
8158 /* fake (%bp) into 0(%bp) */
8159 if (i
.disp_encoding
== disp_encoding_16bit
)
8160 i
.types
[op
].bitfield
.disp16
= 1;
8162 i
.types
[op
].bitfield
.disp8
= 1;
8163 fake_zero_displacement
= 1;
8166 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8167 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8169 default: /* (%si) -> 4 or (%di) -> 5 */
8170 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8172 if (!fake_zero_displacement
8176 fake_zero_displacement
= 1;
8177 if (i
.disp_encoding
== disp_encoding_8bit
)
8178 i
.types
[op
].bitfield
.disp8
= 1;
8180 i
.types
[op
].bitfield
.disp16
= 1;
8182 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8184 else /* i.base_reg and 32/64 bit mode */
8186 if (flag_code
== CODE_64BIT
8187 && operand_type_check (i
.types
[op
], disp
))
8189 i
.types
[op
].bitfield
.disp16
= 0;
8190 i
.types
[op
].bitfield
.disp64
= 0;
8191 if (i
.prefix
[ADDR_PREFIX
] == 0)
8193 i
.types
[op
].bitfield
.disp32
= 0;
8194 i
.types
[op
].bitfield
.disp32s
= 1;
8198 i
.types
[op
].bitfield
.disp32
= 1;
8199 i
.types
[op
].bitfield
.disp32s
= 0;
8203 if (!i
.tm
.opcode_modifier
.sib
)
8204 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8205 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8207 i
.sib
.base
= i
.base_reg
->reg_num
;
8208 /* x86-64 ignores REX prefix bit here to avoid decoder
8210 if (!(i
.base_reg
->reg_flags
& RegRex
)
8211 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8212 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8214 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8216 fake_zero_displacement
= 1;
8217 if (i
.disp_encoding
== disp_encoding_32bit
)
8218 i
.types
[op
].bitfield
.disp32
= 1;
8220 i
.types
[op
].bitfield
.disp8
= 1;
8222 i
.sib
.scale
= i
.log2_scale_factor
;
8223 if (i
.index_reg
== 0)
8225 /* Only check for VSIB. */
8226 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8227 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8228 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8230 /* <disp>(%esp) becomes two byte modrm with no index
8231 register. We've already stored the code for esp
8232 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8233 Any base register besides %esp will not use the
8234 extra modrm byte. */
8235 i
.sib
.index
= NO_INDEX_REGISTER
;
8237 else if (!i
.tm
.opcode_modifier
.sib
)
8239 if (i
.index_reg
->reg_num
== RegIZ
)
8240 i
.sib
.index
= NO_INDEX_REGISTER
;
8242 i
.sib
.index
= i
.index_reg
->reg_num
;
8243 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8244 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8249 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8250 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8254 if (!fake_zero_displacement
8258 fake_zero_displacement
= 1;
8259 if (i
.disp_encoding
== disp_encoding_8bit
)
8260 i
.types
[op
].bitfield
.disp8
= 1;
8262 i
.types
[op
].bitfield
.disp32
= 1;
8264 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8268 if (fake_zero_displacement
)
8270 /* Fakes a zero displacement assuming that i.types[op]
8271 holds the correct displacement size. */
8274 gas_assert (i
.op
[op
].disps
== 0);
8275 exp
= &disp_expressions
[i
.disp_operands
++];
8276 i
.op
[op
].disps
= exp
;
8277 exp
->X_op
= O_constant
;
8278 exp
->X_add_number
= 0;
8279 exp
->X_add_symbol
= (symbolS
*) 0;
8280 exp
->X_op_symbol
= (symbolS
*) 0;
8288 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
8290 if (operand_type_check (i
.types
[0], imm
))
8291 i
.vex
.register_specifier
= NULL
;
8294 /* VEX.vvvv encodes one of the sources when the first
8295 operand is not an immediate. */
8296 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8297 i
.vex
.register_specifier
= i
.op
[0].regs
;
8299 i
.vex
.register_specifier
= i
.op
[1].regs
;
8302 /* Destination is a XMM register encoded in the ModRM.reg
8304 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
8305 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
8308 /* ModRM.rm and VEX.B encodes the other source. */
8309 if (!i
.mem_operands
)
8313 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8314 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8316 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
8318 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8322 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
8324 i
.vex
.register_specifier
= i
.op
[2].regs
;
8325 if (!i
.mem_operands
)
8328 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8329 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8333 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8334 (if any) based on i.tm.extension_opcode. Again, we must be
8335 careful to make sure that segment/control/debug/test/MMX
8336 registers are coded into the i.rm.reg field. */
8337 else if (i
.reg_operands
)
8340 unsigned int vex_reg
= ~0;
8342 for (op
= 0; op
< i
.operands
; op
++)
8343 if (i
.types
[op
].bitfield
.class == Reg
8344 || i
.types
[op
].bitfield
.class == RegBND
8345 || i
.types
[op
].bitfield
.class == RegMask
8346 || i
.types
[op
].bitfield
.class == SReg
8347 || i
.types
[op
].bitfield
.class == RegCR
8348 || i
.types
[op
].bitfield
.class == RegDR
8349 || i
.types
[op
].bitfield
.class == RegTR
8350 || i
.types
[op
].bitfield
.class == RegSIMD
8351 || i
.types
[op
].bitfield
.class == RegMMX
)
8356 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8358 /* For instructions with VexNDS, the register-only
8359 source operand is encoded in VEX prefix. */
8360 gas_assert (mem
!= (unsigned int) ~0);
8365 gas_assert (op
< i
.operands
);
8369 /* Check register-only source operand when two source
8370 operands are swapped. */
8371 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
8372 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
8376 gas_assert (mem
== (vex_reg
+ 1)
8377 && op
< i
.operands
);
8382 gas_assert (vex_reg
< i
.operands
);
8386 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
8388 /* For instructions with VexNDD, the register destination
8389 is encoded in VEX prefix. */
8390 if (i
.mem_operands
== 0)
8392 /* There is no memory operand. */
8393 gas_assert ((op
+ 2) == i
.operands
);
8398 /* There are only 2 non-immediate operands. */
8399 gas_assert (op
< i
.imm_operands
+ 2
8400 && i
.operands
== i
.imm_operands
+ 2);
8401 vex_reg
= i
.imm_operands
+ 1;
8405 gas_assert (op
< i
.operands
);
8407 if (vex_reg
!= (unsigned int) ~0)
8409 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
8411 if ((type
->bitfield
.class != Reg
8412 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
8413 && type
->bitfield
.class != RegSIMD
8414 && !operand_type_equal (type
, ®mask
))
8417 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
8420 /* Don't set OP operand twice. */
8423 /* If there is an extension opcode to put here, the
8424 register number must be put into the regmem field. */
8425 if (i
.tm
.extension_opcode
!= None
)
8427 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8428 set_rex_vrex (i
.op
[op
].regs
, REX_B
,
8429 i
.tm
.opcode_modifier
.sse2avx
);
8433 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
8434 set_rex_vrex (i
.op
[op
].regs
, REX_R
,
8435 i
.tm
.opcode_modifier
.sse2avx
);
8439 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8440 must set it to 3 to indicate this is a register operand
8441 in the regmem field. */
8442 if (!i
.mem_operands
)
8446 /* Fill in i.rm.reg field with extension opcode (if any). */
8447 if (i
.tm
.extension_opcode
!= None
)
8448 i
.rm
.reg
= i
.tm
.extension_opcode
;
8454 frag_opcode_byte (unsigned char byte
)
8456 if (now_seg
!= absolute_section
)
8457 FRAG_APPEND_1_CHAR (byte
);
8459 ++abs_section_offset
;
8463 flip_code16 (unsigned int code16
)
8465 gas_assert (i
.tm
.operands
== 1);
8467 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8468 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8469 || i
.tm
.operand_types
[0].bitfield
.disp32s
8470 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8475 output_branch (void)
8481 relax_substateT subtype
;
8485 if (now_seg
== absolute_section
)
8487 as_bad (_("relaxable branches not supported in absolute section"));
8491 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8492 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
8495 if (i
.prefix
[DATA_PREFIX
] != 0)
8499 code16
^= flip_code16(code16
);
8501 /* Pentium4 branch hints. */
8502 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8503 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8508 if (i
.prefix
[REX_PREFIX
] != 0)
8514 /* BND prefixed jump. */
8515 if (i
.prefix
[BND_PREFIX
] != 0)
8521 if (i
.prefixes
!= 0)
8522 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8524 /* It's always a symbol; End frag & setup for relax.
8525 Make sure there is enough room in this frag for the largest
8526 instruction we may generate in md_convert_frag. This is 2
8527 bytes for the opcode and room for the prefix and largest
8529 frag_grow (prefix
+ 2 + 4);
8530 /* Prefix and 1 opcode byte go in fr_fix. */
8531 p
= frag_more (prefix
+ 1);
8532 if (i
.prefix
[DATA_PREFIX
] != 0)
8533 *p
++ = DATA_PREFIX_OPCODE
;
8534 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8535 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8536 *p
++ = i
.prefix
[SEG_PREFIX
];
8537 if (i
.prefix
[BND_PREFIX
] != 0)
8538 *p
++ = BND_PREFIX_OPCODE
;
8539 if (i
.prefix
[REX_PREFIX
] != 0)
8540 *p
++ = i
.prefix
[REX_PREFIX
];
8541 *p
= i
.tm
.base_opcode
;
8543 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8544 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8545 else if (cpu_arch_flags
.bitfield
.cpui386
)
8546 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8548 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8551 sym
= i
.op
[0].disps
->X_add_symbol
;
8552 off
= i
.op
[0].disps
->X_add_number
;
8554 if (i
.op
[0].disps
->X_op
!= O_constant
8555 && i
.op
[0].disps
->X_op
!= O_symbol
)
8557 /* Handle complex expressions. */
8558 sym
= make_expr_symbol (i
.op
[0].disps
);
8562 /* 1 possible extra opcode + 4 byte displacement go in var part.
8563 Pass reloc in fr_var. */
8564 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8567 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8568 /* Return TRUE iff PLT32 relocation should be used for branching to
8572 need_plt32_p (symbolS
*s
)
8574 /* PLT32 relocation is ELF only. */
8579 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8580 krtld support it. */
8584 /* Since there is no need to prepare for PLT branch on x86-64, we
8585 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8586 be used as a marker for 32-bit PC-relative branches. */
8590 /* Weak or undefined symbol need PLT32 relocation. */
8591 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8594 /* Non-global symbol doesn't need PLT32 relocation. */
8595 if (! S_IS_EXTERNAL (s
))
8598 /* Other global symbols need PLT32 relocation. NB: Symbol with
8599 non-default visibilities are treated as normal global symbol
8600 so that PLT32 relocation can be used as a marker for 32-bit
8601 PC-relative branches. It is useful for linker relaxation. */
8612 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8614 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8616 /* This is a loop or jecxz type instruction. */
8618 if (i
.prefix
[ADDR_PREFIX
] != 0)
8620 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
8623 /* Pentium4 branch hints. */
8624 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8625 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8627 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
8636 if (flag_code
== CODE_16BIT
)
8639 if (i
.prefix
[DATA_PREFIX
] != 0)
8641 frag_opcode_byte (DATA_PREFIX_OPCODE
);
8643 code16
^= flip_code16(code16
);
8651 /* BND prefixed jump. */
8652 if (i
.prefix
[BND_PREFIX
] != 0)
8654 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
8658 if (i
.prefix
[REX_PREFIX
] != 0)
8660 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
8664 if (i
.prefixes
!= 0)
8665 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8667 if (now_seg
== absolute_section
)
8669 abs_section_offset
+= i
.tm
.opcode_length
+ size
;
8673 p
= frag_more (i
.tm
.opcode_length
+ size
);
8674 switch (i
.tm
.opcode_length
)
8677 *p
++ = i
.tm
.base_opcode
>> 8;
8680 *p
++ = i
.tm
.base_opcode
;
8686 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8688 && jump_reloc
== NO_RELOC
8689 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8690 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8693 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8695 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8696 i
.op
[0].disps
, 1, jump_reloc
);
8698 /* All jumps handled here are signed, but don't use a signed limit
8699 check for 32 and 16 bit jumps as we want to allow wrap around at
8700 4G and 64k respectively. */
8702 fixP
->fx_signed
= 1;
8706 output_interseg_jump (void)
8714 if (flag_code
== CODE_16BIT
)
8718 if (i
.prefix
[DATA_PREFIX
] != 0)
8725 gas_assert (!i
.prefix
[REX_PREFIX
]);
8731 if (i
.prefixes
!= 0)
8732 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8734 if (now_seg
== absolute_section
)
8736 abs_section_offset
+= prefix
+ 1 + 2 + size
;
8740 /* 1 opcode; 2 segment; offset */
8741 p
= frag_more (prefix
+ 1 + 2 + size
);
8743 if (i
.prefix
[DATA_PREFIX
] != 0)
8744 *p
++ = DATA_PREFIX_OPCODE
;
8746 if (i
.prefix
[REX_PREFIX
] != 0)
8747 *p
++ = i
.prefix
[REX_PREFIX
];
8749 *p
++ = i
.tm
.base_opcode
;
8750 if (i
.op
[1].imms
->X_op
== O_constant
)
8752 offsetT n
= i
.op
[1].imms
->X_add_number
;
8755 && !fits_in_unsigned_word (n
)
8756 && !fits_in_signed_word (n
))
8758 as_bad (_("16-bit jump out of range"));
8761 md_number_to_chars (p
, n
, size
);
8764 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8765 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8766 if (i
.op
[0].imms
->X_op
!= O_constant
)
8767 as_bad (_("can't handle non absolute segment in `%s'"),
8769 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8772 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8777 asection
*seg
= now_seg
;
8778 subsegT subseg
= now_subseg
;
8780 unsigned int alignment
, align_size_1
;
8781 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8782 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8783 unsigned int padding
;
8785 if (!IS_ELF
|| !x86_used_note
)
8788 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8790 /* The .note.gnu.property section layout:
8792 Field Length Contents
8795 n_descsz 4 The note descriptor size
8796 n_type 4 NT_GNU_PROPERTY_TYPE_0
8798 n_desc n_descsz The program property array
8802 /* Create the .note.gnu.property section. */
8803 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8804 bfd_set_section_flags (sec
,
8811 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8822 bfd_set_section_alignment (sec
, alignment
);
8823 elf_section_type (sec
) = SHT_NOTE
;
8825 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8827 isa_1_descsz_raw
= 4 + 4 + 4;
8828 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8829 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8831 feature_2_descsz_raw
= isa_1_descsz
;
8832 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8834 feature_2_descsz_raw
+= 4 + 4 + 4;
8835 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8836 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8839 descsz
= feature_2_descsz
;
8840 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8841 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8843 /* Write n_namsz. */
8844 md_number_to_chars (p
, (valueT
) 4, 4);
8846 /* Write n_descsz. */
8847 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8850 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8853 memcpy (p
+ 4 * 3, "GNU", 4);
8855 /* Write 4-byte type. */
8856 md_number_to_chars (p
+ 4 * 4,
8857 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8859 /* Write 4-byte data size. */
8860 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8862 /* Write 4-byte data. */
8863 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8865 /* Zero out paddings. */
8866 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8868 memset (p
+ 4 * 7, 0, padding
);
8870 /* Write 4-byte type. */
8871 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8872 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8874 /* Write 4-byte data size. */
8875 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8877 /* Write 4-byte data. */
8878 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8879 (valueT
) x86_feature_2_used
, 4);
8881 /* Zero out paddings. */
8882 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8884 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8886 /* We probably can't restore the current segment, for there likely
8889 subseg_set (seg
, subseg
);
8894 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8895 const char *frag_now_ptr
)
8897 unsigned int len
= 0;
8899 if (start_frag
!= frag_now
)
8901 const fragS
*fr
= start_frag
;
8906 } while (fr
&& fr
!= frag_now
);
8909 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8912 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8913 be macro-fused with conditional jumps.
8914 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
8915 or is one of the following format:
8928 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
8930 /* No RIP address. */
8931 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8934 /* No VEX/EVEX encoding. */
8935 if (is_any_vex_encoding (&i
.tm
))
8938 /* add, sub without add/sub m, imm. */
8939 if (i
.tm
.base_opcode
<= 5
8940 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8941 || ((i
.tm
.base_opcode
| 3) == 0x83
8942 && (i
.tm
.extension_opcode
== 0x5
8943 || i
.tm
.extension_opcode
== 0x0)))
8945 *mf_cmp_p
= mf_cmp_alu_cmp
;
8946 return !(i
.mem_operands
&& i
.imm_operands
);
8949 /* and without and m, imm. */
8950 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8951 || ((i
.tm
.base_opcode
| 3) == 0x83
8952 && i
.tm
.extension_opcode
== 0x4))
8954 *mf_cmp_p
= mf_cmp_test_and
;
8955 return !(i
.mem_operands
&& i
.imm_operands
);
8958 /* test without test m imm. */
8959 if ((i
.tm
.base_opcode
| 1) == 0x85
8960 || (i
.tm
.base_opcode
| 1) == 0xa9
8961 || ((i
.tm
.base_opcode
| 1) == 0xf7
8962 && i
.tm
.extension_opcode
== 0))
8964 *mf_cmp_p
= mf_cmp_test_and
;
8965 return !(i
.mem_operands
&& i
.imm_operands
);
8968 /* cmp without cmp m, imm. */
8969 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8970 || ((i
.tm
.base_opcode
| 3) == 0x83
8971 && (i
.tm
.extension_opcode
== 0x7)))
8973 *mf_cmp_p
= mf_cmp_alu_cmp
;
8974 return !(i
.mem_operands
&& i
.imm_operands
);
8977 /* inc, dec without inc/dec m. */
8978 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8979 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8980 || ((i
.tm
.base_opcode
| 1) == 0xff
8981 && i
.tm
.extension_opcode
<= 0x1))
8983 *mf_cmp_p
= mf_cmp_incdec
;
8984 return !i
.mem_operands
;
8990 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
8993 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
8995 /* NB: Don't work with COND_JUMP86 without i386. */
8996 if (!align_branch_power
8997 || now_seg
== absolute_section
8998 || !cpu_arch_flags
.bitfield
.cpui386
8999 || !(align_branch
& align_branch_fused_bit
))
9002 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9004 if (last_insn
.kind
== last_insn_other
9005 || last_insn
.seg
!= now_seg
)
9008 as_warn_where (last_insn
.file
, last_insn
.line
,
9009 _("`%s` skips -malign-branch-boundary on `%s`"),
9010 last_insn
.name
, i
.tm
.name
);
9016 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9019 add_branch_prefix_frag_p (void)
9021 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9022 to PadLock instructions since they include prefixes in opcode. */
9023 if (!align_branch_power
9024 || !align_branch_prefix_size
9025 || now_seg
== absolute_section
9026 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
9027 || !cpu_arch_flags
.bitfield
.cpui386
)
9030 /* Don't add prefix if it is a prefix or there is no operand in case
9031 that segment prefix is special. */
9032 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9035 if (last_insn
.kind
== last_insn_other
9036 || last_insn
.seg
!= now_seg
)
9040 as_warn_where (last_insn
.file
, last_insn
.line
,
9041 _("`%s` skips -malign-branch-boundary on `%s`"),
9042 last_insn
.name
, i
.tm
.name
);
9047 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9050 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9051 enum mf_jcc_kind
*mf_jcc_p
)
9055 /* NB: Don't work with COND_JUMP86 without i386. */
9056 if (!align_branch_power
9057 || now_seg
== absolute_section
9058 || !cpu_arch_flags
.bitfield
.cpui386
)
9063 /* Check for jcc and direct jmp. */
9064 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9066 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9068 *branch_p
= align_branch_jmp
;
9069 add_padding
= align_branch
& align_branch_jmp_bit
;
9073 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9074 igore the lowest bit. */
9075 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9076 *branch_p
= align_branch_jcc
;
9077 if ((align_branch
& align_branch_jcc_bit
))
9081 else if (is_any_vex_encoding (&i
.tm
))
9083 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9086 *branch_p
= align_branch_ret
;
9087 if ((align_branch
& align_branch_ret_bit
))
9092 /* Check for indirect jmp, direct and indirect calls. */
9093 if (i
.tm
.base_opcode
== 0xe8)
9096 *branch_p
= align_branch_call
;
9097 if ((align_branch
& align_branch_call_bit
))
9100 else if (i
.tm
.base_opcode
== 0xff
9101 && (i
.tm
.extension_opcode
== 2
9102 || i
.tm
.extension_opcode
== 4))
9104 /* Indirect call and jmp. */
9105 *branch_p
= align_branch_indirect
;
9106 if ((align_branch
& align_branch_indirect_bit
))
9113 && (i
.op
[0].disps
->X_op
== O_symbol
9114 || (i
.op
[0].disps
->X_op
== O_subtract
9115 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9117 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9118 /* No padding to call to global or undefined tls_get_addr. */
9119 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9120 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9126 && last_insn
.kind
!= last_insn_other
9127 && last_insn
.seg
== now_seg
)
9130 as_warn_where (last_insn
.file
, last_insn
.line
,
9131 _("`%s` skips -malign-branch-boundary on `%s`"),
9132 last_insn
.name
, i
.tm
.name
);
9142 fragS
*insn_start_frag
;
9143 offsetT insn_start_off
;
9144 fragS
*fragP
= NULL
;
9145 enum align_branch_kind branch
= align_branch_none
;
9146 /* The initializer is arbitrary just to avoid uninitialized error.
9147 it's actually either assigned in add_branch_padding_frag_p
9148 or never be used. */
9149 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9151 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9152 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9154 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
9155 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
9156 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
9157 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
9158 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
9159 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
9160 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
9161 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
9162 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
9163 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
9164 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
9165 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
9166 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
9167 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
9168 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9169 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
9170 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
9171 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
9172 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
9173 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
9174 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
9175 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
9176 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
9177 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
9178 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
9179 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
9180 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
9181 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
9182 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
9183 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
9184 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
9185 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
9186 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
9187 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
9188 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
9189 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
9190 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
9191 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
9192 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
9193 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
9194 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
9195 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
9196 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
9197 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
9198 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
9199 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
9200 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
9201 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
9202 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
9203 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
9205 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9206 || i
.tm
.cpu_flags
.bitfield
.cpu287
9207 || i
.tm
.cpu_flags
.bitfield
.cpu387
9208 || i
.tm
.cpu_flags
.bitfield
.cpu687
9209 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9210 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9211 if ((i
.xstate
& xstate_mmx
)
9212 || i
.tm
.base_opcode
== 0xf77 /* emms */
9213 || i
.tm
.base_opcode
== 0xf0e /* femms */)
9214 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9215 if ((i
.xstate
& xstate_xmm
))
9216 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9217 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9218 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9219 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9220 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9221 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9222 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9223 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9224 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9225 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9226 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9227 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9228 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9230 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9231 || i
.tm
.cpu_flags
.bitfield
.cpuamx_tile
)
9232 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9236 /* Tie dwarf2 debug info to the address at the start of the insn.
9237 We can't do this after the insn has been output as the current
9238 frag may have been closed off. eg. by frag_var. */
9239 dwarf2_emit_insn (0);
9241 insn_start_frag
= frag_now
;
9242 insn_start_off
= frag_now_fix ();
9244 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9247 /* Branch can be 8 bytes. Leave some room for prefixes. */
9248 unsigned int max_branch_padding_size
= 14;
9250 /* Align section to boundary. */
9251 record_alignment (now_seg
, align_branch_power
);
9253 /* Make room for padding. */
9254 frag_grow (max_branch_padding_size
);
9256 /* Start of the padding. */
9261 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9262 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9265 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9266 fragP
->tc_frag_data
.branch_type
= branch
;
9267 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9271 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9273 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9274 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9276 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9277 output_interseg_jump ();
9280 /* Output normal instructions here. */
9284 unsigned int prefix
;
9285 enum mf_cmp_kind mf_cmp
;
9288 && (i
.tm
.base_opcode
== 0xfaee8
9289 || i
.tm
.base_opcode
== 0xfaef0
9290 || i
.tm
.base_opcode
== 0xfaef8))
9292 /* Encode lfence, mfence, and sfence as
9293 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9294 if (now_seg
!= absolute_section
)
9296 offsetT val
= 0x240483f0ULL
;
9299 md_number_to_chars (p
, val
, 5);
9302 abs_section_offset
+= 5;
9306 /* Some processors fail on LOCK prefix. This options makes
9307 assembler ignore LOCK prefix and serves as a workaround. */
9308 if (omit_lock_prefix
)
9310 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
9312 i
.prefix
[LOCK_PREFIX
] = 0;
9316 /* Skip if this is a branch. */
9318 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9320 /* Make room for padding. */
9321 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9326 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9327 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9330 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9331 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9332 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9334 else if (add_branch_prefix_frag_p ())
9336 unsigned int max_prefix_size
= align_branch_prefix_size
;
9338 /* Make room for padding. */
9339 frag_grow (max_prefix_size
);
9344 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9345 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9348 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9351 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9352 don't need the explicit prefix. */
9353 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
9355 switch (i
.tm
.opcode_length
)
9358 if (i
.tm
.base_opcode
& 0xff000000)
9360 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
9361 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9362 || prefix
!= REPE_PREFIX_OPCODE
9363 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
9364 add_prefix (prefix
);
9368 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
9370 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
9371 add_prefix (prefix
);
9377 /* Check for pseudo prefixes. */
9378 as_bad_where (insn_start_frag
->fr_file
,
9379 insn_start_frag
->fr_line
,
9380 _("pseudo prefix without instruction"));
9386 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9387 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9388 R_X86_64_GOTTPOFF relocation so that linker can safely
9389 perform IE->LE optimization. A dummy REX_OPCODE prefix
9390 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9391 relocation for GDesc -> IE/LE optimization. */
9392 if (x86_elf_abi
== X86_64_X32_ABI
9394 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9395 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9396 && i
.prefix
[REX_PREFIX
] == 0)
9397 add_prefix (REX_OPCODE
);
9400 /* The prefix bytes. */
9401 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9403 frag_opcode_byte (*q
);
9407 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9413 frag_opcode_byte (*q
);
9416 /* There should be no other prefixes for instructions
9421 /* For EVEX instructions i.vrex should become 0 after
9422 build_evex_prefix. For VEX instructions upper 16 registers
9423 aren't available, so VREX should be 0. */
9426 /* Now the VEX prefix. */
9427 if (now_seg
!= absolute_section
)
9429 p
= frag_more (i
.vex
.length
);
9430 for (j
= 0; j
< i
.vex
.length
; j
++)
9431 p
[j
] = i
.vex
.bytes
[j
];
9434 abs_section_offset
+= i
.vex
.length
;
9437 /* Now the opcode; be careful about word order here! */
9438 if (now_seg
== absolute_section
)
9439 abs_section_offset
+= i
.tm
.opcode_length
;
9440 else if (i
.tm
.opcode_length
== 1)
9442 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9446 switch (i
.tm
.opcode_length
)
9450 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
9451 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9455 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9465 /* Put out high byte first: can't use md_number_to_chars! */
9466 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9467 *p
= i
.tm
.base_opcode
& 0xff;
9470 /* Now the modrm byte and sib byte (if present). */
9471 if (i
.tm
.opcode_modifier
.modrm
)
9473 frag_opcode_byte ((i
.rm
.regmem
<< 0)
9475 | (i
.rm
.mode
<< 6));
9476 /* If i.rm.regmem == ESP (4)
9477 && i.rm.mode != (Register mode)
9479 ==> need second modrm byte. */
9480 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9482 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9483 frag_opcode_byte ((i
.sib
.base
<< 0)
9484 | (i
.sib
.index
<< 3)
9485 | (i
.sib
.scale
<< 6));
9488 if (i
.disp_operands
)
9489 output_disp (insn_start_frag
, insn_start_off
);
9492 output_imm (insn_start_frag
, insn_start_off
);
9495 * frag_now_fix () returning plain abs_section_offset when we're in the
9496 * absolute section, and abs_section_offset not getting updated as data
9497 * gets added to the frag breaks the logic below.
9499 if (now_seg
!= absolute_section
)
9501 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9503 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9507 /* NB: Don't add prefix with GOTPC relocation since
9508 output_disp() above depends on the fixed encoding
9509 length. Can't add prefix with TLS relocation since
9510 it breaks TLS linker optimization. */
9511 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9512 /* Prefix count on the current instruction. */
9513 unsigned int count
= i
.vex
.length
;
9515 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9516 /* REX byte is encoded in VEX/EVEX prefix. */
9517 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9520 /* Count prefixes for extended opcode maps. */
9522 switch (i
.tm
.opcode_length
)
9525 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
9528 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
9540 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
9549 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9552 /* Set the maximum prefix size in BRANCH_PREFIX
9554 if (fragP
->tc_frag_data
.max_bytes
> max
)
9555 fragP
->tc_frag_data
.max_bytes
= max
;
9556 if (fragP
->tc_frag_data
.max_bytes
> count
)
9557 fragP
->tc_frag_data
.max_bytes
-= count
;
9559 fragP
->tc_frag_data
.max_bytes
= 0;
9563 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9565 unsigned int max_prefix_size
;
9566 if (align_branch_prefix_size
> max
)
9567 max_prefix_size
= max
;
9569 max_prefix_size
= align_branch_prefix_size
;
9570 if (max_prefix_size
> count
)
9571 fragP
->tc_frag_data
.max_prefix_length
9572 = max_prefix_size
- count
;
9575 /* Use existing segment prefix if possible. Use CS
9576 segment prefix in 64-bit mode. In 32-bit mode, use SS
9577 segment prefix with ESP/EBP base register and use DS
9578 segment prefix without ESP/EBP base register. */
9579 if (i
.prefix
[SEG_PREFIX
])
9580 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9581 else if (flag_code
== CODE_64BIT
)
9582 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9584 && (i
.base_reg
->reg_num
== 4
9585 || i
.base_reg
->reg_num
== 5))
9586 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9588 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9593 /* NB: Don't work with COND_JUMP86 without i386. */
9594 if (align_branch_power
9595 && now_seg
!= absolute_section
9596 && cpu_arch_flags
.bitfield
.cpui386
)
9598 /* Terminate each frag so that we can add prefix and check for
9600 frag_wane (frag_now
);
9607 pi ("" /*line*/, &i
);
9609 #endif /* DEBUG386 */
9612 /* Return the size of the displacement operand N. */
9615 disp_size (unsigned int n
)
9619 if (i
.types
[n
].bitfield
.disp64
)
9621 else if (i
.types
[n
].bitfield
.disp8
)
9623 else if (i
.types
[n
].bitfield
.disp16
)
9628 /* Return the size of the immediate operand N. */
9631 imm_size (unsigned int n
)
9634 if (i
.types
[n
].bitfield
.imm64
)
9636 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9638 else if (i
.types
[n
].bitfield
.imm16
)
9644 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9649 for (n
= 0; n
< i
.operands
; n
++)
9651 if (operand_type_check (i
.types
[n
], disp
))
9653 int size
= disp_size (n
);
9655 if (now_seg
== absolute_section
)
9656 abs_section_offset
+= size
;
9657 else if (i
.op
[n
].disps
->X_op
== O_constant
)
9659 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9661 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9663 p
= frag_more (size
);
9664 md_number_to_chars (p
, val
, size
);
9668 enum bfd_reloc_code_real reloc_type
;
9669 int sign
= i
.types
[n
].bitfield
.disp32s
;
9670 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9673 /* We can't have 8 bit displacement here. */
9674 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9676 /* The PC relative address is computed relative
9677 to the instruction boundary, so in case immediate
9678 fields follows, we need to adjust the value. */
9679 if (pcrel
&& i
.imm_operands
)
9684 for (n1
= 0; n1
< i
.operands
; n1
++)
9685 if (operand_type_check (i
.types
[n1
], imm
))
9687 /* Only one immediate is allowed for PC
9688 relative address. */
9689 gas_assert (sz
== 0);
9691 i
.op
[n
].disps
->X_add_number
-= sz
;
9693 /* We should find the immediate. */
9694 gas_assert (sz
!= 0);
9697 p
= frag_more (size
);
9698 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9700 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9701 && (((reloc_type
== BFD_RELOC_32
9702 || reloc_type
== BFD_RELOC_X86_64_32S
9703 || (reloc_type
== BFD_RELOC_64
9705 && (i
.op
[n
].disps
->X_op
== O_symbol
9706 || (i
.op
[n
].disps
->X_op
== O_add
9707 && ((symbol_get_value_expression
9708 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9710 || reloc_type
== BFD_RELOC_32_PCREL
))
9714 reloc_type
= BFD_RELOC_386_GOTPC
;
9715 i
.has_gotpc_tls_reloc
= TRUE
;
9716 i
.op
[n
].imms
->X_add_number
+=
9717 encoding_length (insn_start_frag
, insn_start_off
, p
);
9719 else if (reloc_type
== BFD_RELOC_64
)
9720 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9722 /* Don't do the adjustment for x86-64, as there
9723 the pcrel addressing is relative to the _next_
9724 insn, and that is taken care of in other code. */
9725 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9727 else if (align_branch_power
)
9731 case BFD_RELOC_386_TLS_GD
:
9732 case BFD_RELOC_386_TLS_LDM
:
9733 case BFD_RELOC_386_TLS_IE
:
9734 case BFD_RELOC_386_TLS_IE_32
:
9735 case BFD_RELOC_386_TLS_GOTIE
:
9736 case BFD_RELOC_386_TLS_GOTDESC
:
9737 case BFD_RELOC_386_TLS_DESC_CALL
:
9738 case BFD_RELOC_X86_64_TLSGD
:
9739 case BFD_RELOC_X86_64_TLSLD
:
9740 case BFD_RELOC_X86_64_GOTTPOFF
:
9741 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9742 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9743 i
.has_gotpc_tls_reloc
= TRUE
;
9748 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9749 size
, i
.op
[n
].disps
, pcrel
,
9751 /* Check for "call/jmp *mem", "mov mem, %reg",
9752 "test %reg, mem" and "binop mem, %reg" where binop
9753 is one of adc, add, and, cmp, or, sbb, sub, xor
9754 instructions without data prefix. Always generate
9755 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9756 if (i
.prefix
[DATA_PREFIX
] == 0
9757 && (generate_relax_relocations
9760 && i
.rm
.regmem
== 5))
9762 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9763 && !is_any_vex_encoding(&i
.tm
)
9764 && ((i
.operands
== 1
9765 && i
.tm
.base_opcode
== 0xff
9766 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9768 && (i
.tm
.base_opcode
== 0x8b
9769 || i
.tm
.base_opcode
== 0x85
9770 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9774 fixP
->fx_tcbit
= i
.rex
!= 0;
9776 && (i
.base_reg
->reg_num
== RegIP
))
9777 fixP
->fx_tcbit2
= 1;
9780 fixP
->fx_tcbit2
= 1;
9788 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9793 for (n
= 0; n
< i
.operands
; n
++)
9795 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9796 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9799 if (operand_type_check (i
.types
[n
], imm
))
9801 int size
= imm_size (n
);
9803 if (now_seg
== absolute_section
)
9804 abs_section_offset
+= size
;
9805 else if (i
.op
[n
].imms
->X_op
== O_constant
)
9809 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9811 p
= frag_more (size
);
9812 md_number_to_chars (p
, val
, size
);
9816 /* Not absolute_section.
9817 Need a 32-bit fixup (don't support 8bit
9818 non-absolute imms). Try to support other
9820 enum bfd_reloc_code_real reloc_type
;
9823 if (i
.types
[n
].bitfield
.imm32s
9824 && (i
.suffix
== QWORD_MNEM_SUFFIX
9825 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9830 p
= frag_more (size
);
9831 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9833 /* This is tough to explain. We end up with this one if we
9834 * have operands that look like
9835 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9836 * obtain the absolute address of the GOT, and it is strongly
9837 * preferable from a performance point of view to avoid using
9838 * a runtime relocation for this. The actual sequence of
9839 * instructions often look something like:
9844 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9846 * The call and pop essentially return the absolute address
9847 * of the label .L66 and store it in %ebx. The linker itself
9848 * will ultimately change the first operand of the addl so
9849 * that %ebx points to the GOT, but to keep things simple, the
9850 * .o file must have this operand set so that it generates not
9851 * the absolute address of .L66, but the absolute address of
9852 * itself. This allows the linker itself simply treat a GOTPC
9853 * relocation as asking for a pcrel offset to the GOT to be
9854 * added in, and the addend of the relocation is stored in the
9855 * operand field for the instruction itself.
9857 * Our job here is to fix the operand so that it would add
9858 * the correct offset so that %ebx would point to itself. The
9859 * thing that is tricky is that .-.L66 will point to the
9860 * beginning of the instruction, so we need to further modify
9861 * the operand so that it will point to itself. There are
9862 * other cases where you have something like:
9864 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9866 * and here no correction would be required. Internally in
9867 * the assembler we treat operands of this form as not being
9868 * pcrel since the '.' is explicitly mentioned, and I wonder
9869 * whether it would simplify matters to do it this way. Who
9870 * knows. In earlier versions of the PIC patches, the
9871 * pcrel_adjust field was used to store the correction, but
9872 * since the expression is not pcrel, I felt it would be
9873 * confusing to do it this way. */
9875 if ((reloc_type
== BFD_RELOC_32
9876 || reloc_type
== BFD_RELOC_X86_64_32S
9877 || reloc_type
== BFD_RELOC_64
)
9879 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9880 && (i
.op
[n
].imms
->X_op
== O_symbol
9881 || (i
.op
[n
].imms
->X_op
== O_add
9882 && ((symbol_get_value_expression
9883 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9887 reloc_type
= BFD_RELOC_386_GOTPC
;
9889 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9891 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9892 i
.has_gotpc_tls_reloc
= TRUE
;
9893 i
.op
[n
].imms
->X_add_number
+=
9894 encoding_length (insn_start_frag
, insn_start_off
, p
);
9896 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9897 i
.op
[n
].imms
, 0, reloc_type
);
9903 /* x86_cons_fix_new is called via the expression parsing code when a
9904 reloc is needed. We use this hook to get the correct .got reloc. */
9905 static int cons_sign
= -1;
9908 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9909 expressionS
*exp
, bfd_reloc_code_real_type r
)
9911 r
= reloc (len
, 0, cons_sign
, r
);
9914 if (exp
->X_op
== O_secrel
)
9916 exp
->X_op
= O_symbol
;
9917 r
= BFD_RELOC_32_SECREL
;
9921 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9924 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9925 purpose of the `.dc.a' internal pseudo-op. */
9928 x86_address_bytes (void)
9930 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9932 return stdoutput
->arch_info
->bits_per_address
/ 8;
9935 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9937 # define lex_got(reloc, adjust, types) NULL
9939 /* Parse operands of the form
9940 <symbol>@GOTOFF+<nnn>
9941 and similar .plt or .got references.
9943 If we find one, set up the correct relocation in RELOC and copy the
9944 input string, minus the `@GOTOFF' into a malloc'd buffer for
9945 parsing by the calling routine. Return this buffer, and if ADJUST
9946 is non-null set it to the length of the string we removed from the
9947 input line. Otherwise return NULL. */
9949 lex_got (enum bfd_reloc_code_real
*rel
,
9951 i386_operand_type
*types
)
9953 /* Some of the relocations depend on the size of what field is to
9954 be relocated. But in our callers i386_immediate and i386_displacement
9955 we don't yet know the operand size (this will be set by insn
9956 matching). Hence we record the word32 relocation here,
9957 and adjust the reloc according to the real size in reloc(). */
9958 static const struct {
9961 const enum bfd_reloc_code_real rel
[2];
9962 const i386_operand_type types64
;
9964 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9965 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
9967 OPERAND_TYPE_IMM32_64
},
9969 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
9970 BFD_RELOC_X86_64_PLTOFF64
},
9971 OPERAND_TYPE_IMM64
},
9972 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
9973 BFD_RELOC_X86_64_PLT32
},
9974 OPERAND_TYPE_IMM32_32S_DISP32
},
9975 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
9976 BFD_RELOC_X86_64_GOTPLT64
},
9977 OPERAND_TYPE_IMM64_DISP64
},
9978 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
9979 BFD_RELOC_X86_64_GOTOFF64
},
9980 OPERAND_TYPE_IMM64_DISP64
},
9981 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
9982 BFD_RELOC_X86_64_GOTPCREL
},
9983 OPERAND_TYPE_IMM32_32S_DISP32
},
9984 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
9985 BFD_RELOC_X86_64_TLSGD
},
9986 OPERAND_TYPE_IMM32_32S_DISP32
},
9987 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
9988 _dummy_first_bfd_reloc_code_real
},
9989 OPERAND_TYPE_NONE
},
9990 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
9991 BFD_RELOC_X86_64_TLSLD
},
9992 OPERAND_TYPE_IMM32_32S_DISP32
},
9993 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
9994 BFD_RELOC_X86_64_GOTTPOFF
},
9995 OPERAND_TYPE_IMM32_32S_DISP32
},
9996 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
9997 BFD_RELOC_X86_64_TPOFF32
},
9998 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9999 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10000 _dummy_first_bfd_reloc_code_real
},
10001 OPERAND_TYPE_NONE
},
10002 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10003 BFD_RELOC_X86_64_DTPOFF32
},
10004 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
10005 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10006 _dummy_first_bfd_reloc_code_real
},
10007 OPERAND_TYPE_NONE
},
10008 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10009 _dummy_first_bfd_reloc_code_real
},
10010 OPERAND_TYPE_NONE
},
10011 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10012 BFD_RELOC_X86_64_GOT32
},
10013 OPERAND_TYPE_IMM32_32S_64_DISP32
},
10014 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10015 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10016 OPERAND_TYPE_IMM32_32S_DISP32
},
10017 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10018 BFD_RELOC_X86_64_TLSDESC_CALL
},
10019 OPERAND_TYPE_IMM32_32S_DISP32
},
10024 #if defined (OBJ_MAYBE_ELF)
10029 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10030 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10033 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10035 int len
= gotrel
[j
].len
;
10036 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10038 if (gotrel
[j
].rel
[object_64bit
] != 0)
10041 char *tmpbuf
, *past_reloc
;
10043 *rel
= gotrel
[j
].rel
[object_64bit
];
10047 if (flag_code
!= CODE_64BIT
)
10049 types
->bitfield
.imm32
= 1;
10050 types
->bitfield
.disp32
= 1;
10053 *types
= gotrel
[j
].types64
;
10056 if (j
!= 0 && GOT_symbol
== NULL
)
10057 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10059 /* The length of the first part of our input line. */
10060 first
= cp
- input_line_pointer
;
10062 /* The second part goes from after the reloc token until
10063 (and including) an end_of_line char or comma. */
10064 past_reloc
= cp
+ 1 + len
;
10066 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10068 second
= cp
+ 1 - past_reloc
;
10070 /* Allocate and copy string. The trailing NUL shouldn't
10071 be necessary, but be safe. */
10072 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10073 memcpy (tmpbuf
, input_line_pointer
, first
);
10074 if (second
!= 0 && *past_reloc
!= ' ')
10075 /* Replace the relocation token with ' ', so that
10076 errors like foo@GOTOFF1 will be detected. */
10077 tmpbuf
[first
++] = ' ';
10079 /* Increment length by 1 if the relocation token is
10084 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10085 tmpbuf
[first
+ second
] = '\0';
10089 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10090 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10095 /* Might be a symbol version string. Don't as_bad here. */
10104 /* Parse operands of the form
10105 <symbol>@SECREL32+<nnn>
10107 If we find one, set up the correct relocation in RELOC and copy the
10108 input string, minus the `@SECREL32' into a malloc'd buffer for
10109 parsing by the calling routine. Return this buffer, and if ADJUST
10110 is non-null set it to the length of the string we removed from the
10111 input line. Otherwise return NULL.
10113 This function is copied from the ELF version above adjusted for PE targets. */
10116 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
10117 int *adjust ATTRIBUTE_UNUSED
,
10118 i386_operand_type
*types
)
10120 static const struct
10124 const enum bfd_reloc_code_real rel
[2];
10125 const i386_operand_type types64
;
10129 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10130 BFD_RELOC_32_SECREL
},
10131 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
10137 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10138 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10141 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10143 int len
= gotrel
[j
].len
;
10145 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10147 if (gotrel
[j
].rel
[object_64bit
] != 0)
10150 char *tmpbuf
, *past_reloc
;
10152 *rel
= gotrel
[j
].rel
[object_64bit
];
10158 if (flag_code
!= CODE_64BIT
)
10160 types
->bitfield
.imm32
= 1;
10161 types
->bitfield
.disp32
= 1;
10164 *types
= gotrel
[j
].types64
;
10167 /* The length of the first part of our input line. */
10168 first
= cp
- input_line_pointer
;
10170 /* The second part goes from after the reloc token until
10171 (and including) an end_of_line char or comma. */
10172 past_reloc
= cp
+ 1 + len
;
10174 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10176 second
= cp
+ 1 - past_reloc
;
10178 /* Allocate and copy string. The trailing NUL shouldn't
10179 be necessary, but be safe. */
10180 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10181 memcpy (tmpbuf
, input_line_pointer
, first
);
10182 if (second
!= 0 && *past_reloc
!= ' ')
10183 /* Replace the relocation token with ' ', so that
10184 errors like foo@SECLREL321 will be detected. */
10185 tmpbuf
[first
++] = ' ';
10186 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10187 tmpbuf
[first
+ second
] = '\0';
10191 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10192 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10197 /* Might be a symbol version string. Don't as_bad here. */
10203 bfd_reloc_code_real_type
10204 x86_cons (expressionS
*exp
, int size
)
10206 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10208 intel_syntax
= -intel_syntax
;
10211 if (size
== 4 || (object_64bit
&& size
== 8))
10213 /* Handle @GOTOFF and the like in an expression. */
10215 char *gotfree_input_line
;
10218 save
= input_line_pointer
;
10219 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10220 if (gotfree_input_line
)
10221 input_line_pointer
= gotfree_input_line
;
10225 if (gotfree_input_line
)
10227 /* expression () has merrily parsed up to the end of line,
10228 or a comma - in the wrong buffer. Transfer how far
10229 input_line_pointer has moved to the right buffer. */
10230 input_line_pointer
= (save
10231 + (input_line_pointer
- gotfree_input_line
)
10233 free (gotfree_input_line
);
10234 if (exp
->X_op
== O_constant
10235 || exp
->X_op
== O_absent
10236 || exp
->X_op
== O_illegal
10237 || exp
->X_op
== O_register
10238 || exp
->X_op
== O_big
)
10240 char c
= *input_line_pointer
;
10241 *input_line_pointer
= 0;
10242 as_bad (_("missing or invalid expression `%s'"), save
);
10243 *input_line_pointer
= c
;
10245 else if ((got_reloc
== BFD_RELOC_386_PLT32
10246 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10247 && exp
->X_op
!= O_symbol
)
10249 char c
= *input_line_pointer
;
10250 *input_line_pointer
= 0;
10251 as_bad (_("invalid PLT expression `%s'"), save
);
10252 *input_line_pointer
= c
;
10259 intel_syntax
= -intel_syntax
;
10262 i386_intel_simplify (exp
);
10268 signed_cons (int size
)
10270 if (flag_code
== CODE_64BIT
)
10278 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
10285 if (exp
.X_op
== O_symbol
)
10286 exp
.X_op
= O_secrel
;
10288 emit_expr (&exp
, 4);
10290 while (*input_line_pointer
++ == ',');
10292 input_line_pointer
--;
10293 demand_empty_rest_of_line ();
10297 /* Handle Vector operations. */
10300 check_VecOperations (char *op_string
, char *op_end
)
10302 const reg_entry
*mask
;
10307 && (op_end
== NULL
|| op_string
< op_end
))
10310 if (*op_string
== '{')
10314 /* Check broadcasts. */
10315 if (strncmp (op_string
, "1to", 3) == 0)
10320 goto duplicated_vec_op
;
10323 if (*op_string
== '8')
10325 else if (*op_string
== '4')
10327 else if (*op_string
== '2')
10329 else if (*op_string
== '1'
10330 && *(op_string
+1) == '6')
10337 as_bad (_("Unsupported broadcast: `%s'"), saved
);
10342 broadcast_op
.type
= bcst_type
;
10343 broadcast_op
.operand
= this_operand
;
10344 broadcast_op
.bytes
= 0;
10345 i
.broadcast
= &broadcast_op
;
10347 /* Check masking operation. */
10348 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
10350 if (mask
== &bad_reg
)
10353 /* k0 can't be used for write mask. */
10354 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
10356 as_bad (_("`%s%s' can't be used for write mask"),
10357 register_prefix
, mask
->reg_name
);
10363 mask_op
.mask
= mask
;
10364 mask_op
.zeroing
= 0;
10365 mask_op
.operand
= this_operand
;
10371 goto duplicated_vec_op
;
10373 i
.mask
->mask
= mask
;
10375 /* Only "{z}" is allowed here. No need to check
10376 zeroing mask explicitly. */
10377 if (i
.mask
->operand
!= this_operand
)
10379 as_bad (_("invalid write mask `%s'"), saved
);
10384 op_string
= end_op
;
10386 /* Check zeroing-flag for masking operation. */
10387 else if (*op_string
== 'z')
10391 mask_op
.mask
= NULL
;
10392 mask_op
.zeroing
= 1;
10393 mask_op
.operand
= this_operand
;
10398 if (i
.mask
->zeroing
)
10401 as_bad (_("duplicated `%s'"), saved
);
10405 i
.mask
->zeroing
= 1;
10407 /* Only "{%k}" is allowed here. No need to check mask
10408 register explicitly. */
10409 if (i
.mask
->operand
!= this_operand
)
10411 as_bad (_("invalid zeroing-masking `%s'"),
10420 goto unknown_vec_op
;
10422 if (*op_string
!= '}')
10424 as_bad (_("missing `}' in `%s'"), saved
);
10429 /* Strip whitespace since the addition of pseudo prefixes
10430 changed how the scrubber treats '{'. */
10431 if (is_space_char (*op_string
))
10437 /* We don't know this one. */
10438 as_bad (_("unknown vector operation: `%s'"), saved
);
10442 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
10444 as_bad (_("zeroing-masking only allowed with write mask"));
10452 i386_immediate (char *imm_start
)
10454 char *save_input_line_pointer
;
10455 char *gotfree_input_line
;
10458 i386_operand_type types
;
10460 operand_type_set (&types
, ~0);
10462 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
10464 as_bad (_("at most %d immediate operands are allowed"),
10465 MAX_IMMEDIATE_OPERANDS
);
10469 exp
= &im_expressions
[i
.imm_operands
++];
10470 i
.op
[this_operand
].imms
= exp
;
10472 if (is_space_char (*imm_start
))
10475 save_input_line_pointer
= input_line_pointer
;
10476 input_line_pointer
= imm_start
;
10478 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10479 if (gotfree_input_line
)
10480 input_line_pointer
= gotfree_input_line
;
10482 exp_seg
= expression (exp
);
10484 SKIP_WHITESPACE ();
10486 /* Handle vector operations. */
10487 if (*input_line_pointer
== '{')
10489 input_line_pointer
= check_VecOperations (input_line_pointer
,
10491 if (input_line_pointer
== NULL
)
10495 if (*input_line_pointer
)
10496 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10498 input_line_pointer
= save_input_line_pointer
;
10499 if (gotfree_input_line
)
10501 free (gotfree_input_line
);
10503 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10504 exp
->X_op
= O_illegal
;
10507 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
10511 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10512 i386_operand_type types
, const char *imm_start
)
10514 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
10517 as_bad (_("missing or invalid immediate expression `%s'"),
10521 else if (exp
->X_op
== O_constant
)
10523 /* Size it properly later. */
10524 i
.types
[this_operand
].bitfield
.imm64
= 1;
10525 /* If not 64bit, sign extend val. */
10526 if (flag_code
!= CODE_64BIT
10527 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
10529 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
10531 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10532 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10533 && exp_seg
!= absolute_section
10534 && exp_seg
!= text_section
10535 && exp_seg
!= data_section
10536 && exp_seg
!= bss_section
10537 && exp_seg
!= undefined_section
10538 && !bfd_is_com_section (exp_seg
))
10540 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10544 else if (!intel_syntax
&& exp_seg
== reg_section
)
10547 as_bad (_("illegal immediate register operand %s"), imm_start
);
10552 /* This is an address. The size of the address will be
10553 determined later, depending on destination register,
10554 suffix, or the default for the section. */
10555 i
.types
[this_operand
].bitfield
.imm8
= 1;
10556 i
.types
[this_operand
].bitfield
.imm16
= 1;
10557 i
.types
[this_operand
].bitfield
.imm32
= 1;
10558 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10559 i
.types
[this_operand
].bitfield
.imm64
= 1;
10560 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10568 i386_scale (char *scale
)
10571 char *save
= input_line_pointer
;
10573 input_line_pointer
= scale
;
10574 val
= get_absolute_expression ();
10579 i
.log2_scale_factor
= 0;
10582 i
.log2_scale_factor
= 1;
10585 i
.log2_scale_factor
= 2;
10588 i
.log2_scale_factor
= 3;
10592 char sep
= *input_line_pointer
;
10594 *input_line_pointer
= '\0';
10595 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10597 *input_line_pointer
= sep
;
10598 input_line_pointer
= save
;
10602 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10604 as_warn (_("scale factor of %d without an index register"),
10605 1 << i
.log2_scale_factor
);
10606 i
.log2_scale_factor
= 0;
10608 scale
= input_line_pointer
;
10609 input_line_pointer
= save
;
10614 i386_displacement (char *disp_start
, char *disp_end
)
10618 char *save_input_line_pointer
;
10619 char *gotfree_input_line
;
10621 i386_operand_type bigdisp
, types
= anydisp
;
10624 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10626 as_bad (_("at most %d displacement operands are allowed"),
10627 MAX_MEMORY_OPERANDS
);
10631 operand_type_set (&bigdisp
, 0);
10633 || i
.types
[this_operand
].bitfield
.baseindex
10634 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10635 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10637 i386_addressing_mode ();
10638 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10639 if (flag_code
== CODE_64BIT
)
10643 bigdisp
.bitfield
.disp32s
= 1;
10644 bigdisp
.bitfield
.disp64
= 1;
10647 bigdisp
.bitfield
.disp32
= 1;
10649 else if ((flag_code
== CODE_16BIT
) ^ override
)
10650 bigdisp
.bitfield
.disp16
= 1;
10652 bigdisp
.bitfield
.disp32
= 1;
10656 /* For PC-relative branches, the width of the displacement may be
10657 dependent upon data size, but is never dependent upon address size.
10658 Also make sure to not unintentionally match against a non-PC-relative
10659 branch template. */
10660 static templates aux_templates
;
10661 const insn_template
*t
= current_templates
->start
;
10662 bfd_boolean has_intel64
= FALSE
;
10664 aux_templates
.start
= t
;
10665 while (++t
< current_templates
->end
)
10667 if (t
->opcode_modifier
.jump
10668 != current_templates
->start
->opcode_modifier
.jump
)
10670 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10671 has_intel64
= TRUE
;
10673 if (t
< current_templates
->end
)
10675 aux_templates
.end
= t
;
10676 current_templates
= &aux_templates
;
10679 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10680 if (flag_code
== CODE_64BIT
)
10682 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10683 && (!intel64
|| !has_intel64
))
10684 bigdisp
.bitfield
.disp16
= 1;
10686 bigdisp
.bitfield
.disp32s
= 1;
10691 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10693 : LONG_MNEM_SUFFIX
));
10694 bigdisp
.bitfield
.disp32
= 1;
10695 if ((flag_code
== CODE_16BIT
) ^ override
)
10697 bigdisp
.bitfield
.disp32
= 0;
10698 bigdisp
.bitfield
.disp16
= 1;
10702 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10705 exp
= &disp_expressions
[i
.disp_operands
];
10706 i
.op
[this_operand
].disps
= exp
;
10708 save_input_line_pointer
= input_line_pointer
;
10709 input_line_pointer
= disp_start
;
10710 END_STRING_AND_SAVE (disp_end
);
10712 #ifndef GCC_ASM_O_HACK
10713 #define GCC_ASM_O_HACK 0
10716 END_STRING_AND_SAVE (disp_end
+ 1);
10717 if (i
.types
[this_operand
].bitfield
.baseIndex
10718 && displacement_string_end
[-1] == '+')
10720 /* This hack is to avoid a warning when using the "o"
10721 constraint within gcc asm statements.
10724 #define _set_tssldt_desc(n,addr,limit,type) \
10725 __asm__ __volatile__ ( \
10726 "movw %w2,%0\n\t" \
10727 "movw %w1,2+%0\n\t" \
10728 "rorl $16,%1\n\t" \
10729 "movb %b1,4+%0\n\t" \
10730 "movb %4,5+%0\n\t" \
10731 "movb $0,6+%0\n\t" \
10732 "movb %h1,7+%0\n\t" \
10734 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10736 This works great except that the output assembler ends
10737 up looking a bit weird if it turns out that there is
10738 no offset. You end up producing code that looks like:
10751 So here we provide the missing zero. */
10753 *displacement_string_end
= '0';
10756 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10757 if (gotfree_input_line
)
10758 input_line_pointer
= gotfree_input_line
;
10760 exp_seg
= expression (exp
);
10762 SKIP_WHITESPACE ();
10763 if (*input_line_pointer
)
10764 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10766 RESTORE_END_STRING (disp_end
+ 1);
10768 input_line_pointer
= save_input_line_pointer
;
10769 if (gotfree_input_line
)
10771 free (gotfree_input_line
);
10773 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10774 exp
->X_op
= O_illegal
;
10777 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10779 RESTORE_END_STRING (disp_end
);
10785 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10786 i386_operand_type types
, const char *disp_start
)
10788 i386_operand_type bigdisp
;
10791 /* We do this to make sure that the section symbol is in
10792 the symbol table. We will ultimately change the relocation
10793 to be relative to the beginning of the section. */
10794 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10795 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10796 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10798 if (exp
->X_op
!= O_symbol
)
10801 if (S_IS_LOCAL (exp
->X_add_symbol
)
10802 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10803 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10804 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10805 exp
->X_op
= O_subtract
;
10806 exp
->X_op_symbol
= GOT_symbol
;
10807 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10808 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10809 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10810 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10812 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10815 else if (exp
->X_op
== O_absent
10816 || exp
->X_op
== O_illegal
10817 || exp
->X_op
== O_big
)
10820 as_bad (_("missing or invalid displacement expression `%s'"),
10825 else if (flag_code
== CODE_64BIT
10826 && !i
.prefix
[ADDR_PREFIX
]
10827 && exp
->X_op
== O_constant
)
10829 /* Since displacement is signed extended to 64bit, don't allow
10830 disp32 and turn off disp32s if they are out of range. */
10831 i
.types
[this_operand
].bitfield
.disp32
= 0;
10832 if (!fits_in_signed_long (exp
->X_add_number
))
10834 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10835 if (i
.types
[this_operand
].bitfield
.baseindex
)
10837 as_bad (_("0x%lx out range of signed 32bit displacement"),
10838 (long) exp
->X_add_number
);
10844 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10845 else if (exp
->X_op
!= O_constant
10846 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10847 && exp_seg
!= absolute_section
10848 && exp_seg
!= text_section
10849 && exp_seg
!= data_section
10850 && exp_seg
!= bss_section
10851 && exp_seg
!= undefined_section
10852 && !bfd_is_com_section (exp_seg
))
10854 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10859 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10860 /* Constants get taken care of by optimize_disp(). */
10861 && exp
->X_op
!= O_constant
)
10862 i
.types
[this_operand
].bitfield
.disp8
= 1;
10864 /* Check if this is a displacement only operand. */
10865 bigdisp
= i
.types
[this_operand
];
10866 bigdisp
.bitfield
.disp8
= 0;
10867 bigdisp
.bitfield
.disp16
= 0;
10868 bigdisp
.bitfield
.disp32
= 0;
10869 bigdisp
.bitfield
.disp32s
= 0;
10870 bigdisp
.bitfield
.disp64
= 0;
10871 if (operand_type_all_zero (&bigdisp
))
10872 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10878 /* Return the active addressing mode, taking address override and
10879 registers forming the address into consideration. Update the
10880 address override prefix if necessary. */
10882 static enum flag_code
10883 i386_addressing_mode (void)
10885 enum flag_code addr_mode
;
10887 if (i
.prefix
[ADDR_PREFIX
])
10888 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10889 else if (flag_code
== CODE_16BIT
10890 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
10891 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
10892 from md_assemble() by "is not a valid base/index expression"
10893 when there is a base and/or index. */
10894 && !i
.types
[this_operand
].bitfield
.baseindex
)
10896 /* MPX insn memory operands with neither base nor index must be forced
10897 to use 32-bit addressing in 16-bit mode. */
10898 addr_mode
= CODE_32BIT
;
10899 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10901 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
10902 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
10906 addr_mode
= flag_code
;
10908 #if INFER_ADDR_PREFIX
10909 if (i
.mem_operands
== 0)
10911 /* Infer address prefix from the first memory operand. */
10912 const reg_entry
*addr_reg
= i
.base_reg
;
10914 if (addr_reg
== NULL
)
10915 addr_reg
= i
.index_reg
;
10919 if (addr_reg
->reg_type
.bitfield
.dword
)
10920 addr_mode
= CODE_32BIT
;
10921 else if (flag_code
!= CODE_64BIT
10922 && addr_reg
->reg_type
.bitfield
.word
)
10923 addr_mode
= CODE_16BIT
;
10925 if (addr_mode
!= flag_code
)
10927 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10929 /* Change the size of any displacement too. At most one
10930 of Disp16 or Disp32 is set.
10931 FIXME. There doesn't seem to be any real need for
10932 separate Disp16 and Disp32 flags. The same goes for
10933 Imm16 and Imm32. Removing them would probably clean
10934 up the code quite a lot. */
10935 if (flag_code
!= CODE_64BIT
10936 && (i
.types
[this_operand
].bitfield
.disp16
10937 || i
.types
[this_operand
].bitfield
.disp32
))
10938 i
.types
[this_operand
]
10939 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10949 /* Make sure the memory operand we've been dealt is valid.
10950 Return 1 on success, 0 on a failure. */
10953 i386_index_check (const char *operand_string
)
10955 const char *kind
= "base/index";
10956 enum flag_code addr_mode
= i386_addressing_mode ();
10958 if (current_templates
->start
->opcode_modifier
.isstring
10959 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
10960 && (current_templates
->end
[-1].opcode_modifier
.isstring
10961 || i
.mem_operands
))
10963 /* Memory operands of string insns are special in that they only allow
10964 a single register (rDI, rSI, or rBX) as their memory address. */
10965 const reg_entry
*expected_reg
;
10966 static const char *di_si
[][2] =
10972 static const char *bx
[] = { "ebx", "bx", "rbx" };
10974 kind
= "string address";
10976 if (current_templates
->start
->opcode_modifier
.repprefixok
)
10978 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
10979 - IS_STRING_ES_OP0
;
10982 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
10983 || ((!i
.mem_operands
!= !intel_syntax
)
10984 && current_templates
->end
[-1].operand_types
[1]
10985 .bitfield
.baseindex
))
10987 expected_reg
= hash_find (reg_hash
, di_si
[addr_mode
][op
== es_op
]);
10990 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
10992 if (i
.base_reg
!= expected_reg
10994 || operand_type_check (i
.types
[this_operand
], disp
))
10996 /* The second memory operand must have the same size as
11000 && !((addr_mode
== CODE_64BIT
11001 && i
.base_reg
->reg_type
.bitfield
.qword
)
11002 || (addr_mode
== CODE_32BIT
11003 ? i
.base_reg
->reg_type
.bitfield
.dword
11004 : i
.base_reg
->reg_type
.bitfield
.word
)))
11007 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
11009 intel_syntax
? '[' : '(',
11011 expected_reg
->reg_name
,
11012 intel_syntax
? ']' : ')');
11019 as_bad (_("`%s' is not a valid %s expression"),
11020 operand_string
, kind
);
11025 if (addr_mode
!= CODE_16BIT
)
11027 /* 32-bit/64-bit checks. */
11028 if (i
.disp_encoding
== disp_encoding_16bit
)
11031 as_bad (_("invalid `%s' prefix"),
11032 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
11037 && ((addr_mode
== CODE_64BIT
11038 ? !i
.base_reg
->reg_type
.bitfield
.qword
11039 : !i
.base_reg
->reg_type
.bitfield
.dword
)
11040 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
11041 || i
.base_reg
->reg_num
== RegIZ
))
11043 && !i
.index_reg
->reg_type
.bitfield
.xmmword
11044 && !i
.index_reg
->reg_type
.bitfield
.ymmword
11045 && !i
.index_reg
->reg_type
.bitfield
.zmmword
11046 && ((addr_mode
== CODE_64BIT
11047 ? !i
.index_reg
->reg_type
.bitfield
.qword
11048 : !i
.index_reg
->reg_type
.bitfield
.dword
)
11049 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
11052 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
11053 if (current_templates
->start
->base_opcode
== 0xf30f1b
11054 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a
11055 || current_templates
->start
->opcode_modifier
.sib
== SIBMEM
)
11057 /* They cannot use RIP-relative addressing. */
11058 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
11060 as_bad (_("`%s' cannot be used here"), operand_string
);
11064 /* bndldx and bndstx ignore their scale factor. */
11065 if ((current_templates
->start
->base_opcode
& ~1) == 0x0f1a
11066 && i
.log2_scale_factor
)
11067 as_warn (_("register scaling is being ignored here"));
11072 /* 16-bit checks. */
11073 if (i
.disp_encoding
== disp_encoding_32bit
)
11077 && (!i
.base_reg
->reg_type
.bitfield
.word
11078 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
11080 && (!i
.index_reg
->reg_type
.bitfield
.word
11081 || !i
.index_reg
->reg_type
.bitfield
.baseindex
11083 && i
.base_reg
->reg_num
< 6
11084 && i
.index_reg
->reg_num
>= 6
11085 && i
.log2_scale_factor
== 0))))
11092 /* Handle vector immediates. */
11095 RC_SAE_immediate (const char *imm_start
)
11097 unsigned int match_found
, j
;
11098 const char *pstr
= imm_start
;
11106 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11108 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11112 rc_op
.type
= RC_NamesTable
[j
].type
;
11113 rc_op
.operand
= this_operand
;
11114 i
.rounding
= &rc_op
;
11118 as_bad (_("duplicated `%s'"), imm_start
);
11121 pstr
+= RC_NamesTable
[j
].len
;
11129 if (*pstr
++ != '}')
11131 as_bad (_("Missing '}': '%s'"), imm_start
);
11134 /* RC/SAE immediate string should contain nothing more. */;
11137 as_bad (_("Junk after '}': '%s'"), imm_start
);
11141 exp
= &im_expressions
[i
.imm_operands
++];
11142 i
.op
[this_operand
].imms
= exp
;
11144 exp
->X_op
= O_constant
;
11145 exp
->X_add_number
= 0;
11146 exp
->X_add_symbol
= (symbolS
*) 0;
11147 exp
->X_op_symbol
= (symbolS
*) 0;
11149 i
.types
[this_operand
].bitfield
.imm8
= 1;
11153 /* Only string instructions can have a second memory operand, so
11154 reduce current_templates to just those if it contains any. */
11156 maybe_adjust_templates (void)
11158 const insn_template
*t
;
11160 gas_assert (i
.mem_operands
== 1);
11162 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
11163 if (t
->opcode_modifier
.isstring
)
11166 if (t
< current_templates
->end
)
11168 static templates aux_templates
;
11169 bfd_boolean recheck
;
11171 aux_templates
.start
= t
;
11172 for (; t
< current_templates
->end
; ++t
)
11173 if (!t
->opcode_modifier
.isstring
)
11175 aux_templates
.end
= t
;
11177 /* Determine whether to re-check the first memory operand. */
11178 recheck
= (aux_templates
.start
!= current_templates
->start
11179 || t
!= current_templates
->end
);
11181 current_templates
= &aux_templates
;
11185 i
.mem_operands
= 0;
11186 if (i
.memop1_string
!= NULL
11187 && i386_index_check (i
.memop1_string
) == 0)
11189 i
.mem_operands
= 1;
11196 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11200 i386_att_operand (char *operand_string
)
11202 const reg_entry
*r
;
11204 char *op_string
= operand_string
;
11206 if (is_space_char (*op_string
))
11209 /* We check for an absolute prefix (differentiating,
11210 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11211 if (*op_string
== ABSOLUTE_PREFIX
)
11214 if (is_space_char (*op_string
))
11216 i
.jumpabsolute
= TRUE
;
11219 /* Check if operand is a register. */
11220 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
11222 i386_operand_type temp
;
11227 /* Check for a segment override by searching for ':' after a
11228 segment register. */
11229 op_string
= end_op
;
11230 if (is_space_char (*op_string
))
11232 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
11234 switch (r
->reg_num
)
11237 i
.seg
[i
.mem_operands
] = &es
;
11240 i
.seg
[i
.mem_operands
] = &cs
;
11243 i
.seg
[i
.mem_operands
] = &ss
;
11246 i
.seg
[i
.mem_operands
] = &ds
;
11249 i
.seg
[i
.mem_operands
] = &fs
;
11252 i
.seg
[i
.mem_operands
] = &gs
;
11256 /* Skip the ':' and whitespace. */
11258 if (is_space_char (*op_string
))
11261 if (!is_digit_char (*op_string
)
11262 && !is_identifier_char (*op_string
)
11263 && *op_string
!= '('
11264 && *op_string
!= ABSOLUTE_PREFIX
)
11266 as_bad (_("bad memory operand `%s'"), op_string
);
11269 /* Handle case of %es:*foo. */
11270 if (*op_string
== ABSOLUTE_PREFIX
)
11273 if (is_space_char (*op_string
))
11275 i
.jumpabsolute
= TRUE
;
11277 goto do_memory_reference
;
11280 /* Handle vector operations. */
11281 if (*op_string
== '{')
11283 op_string
= check_VecOperations (op_string
, NULL
);
11284 if (op_string
== NULL
)
11290 as_bad (_("junk `%s' after register"), op_string
);
11293 temp
= r
->reg_type
;
11294 temp
.bitfield
.baseindex
= 0;
11295 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11297 i
.types
[this_operand
].bitfield
.unspecified
= 0;
11298 i
.op
[this_operand
].regs
= r
;
11301 else if (*op_string
== REGISTER_PREFIX
)
11303 as_bad (_("bad register name `%s'"), op_string
);
11306 else if (*op_string
== IMMEDIATE_PREFIX
)
11309 if (i
.jumpabsolute
)
11311 as_bad (_("immediate operand illegal with absolute jump"));
11314 if (!i386_immediate (op_string
))
11317 else if (RC_SAE_immediate (operand_string
))
11319 /* If it is a RC or SAE immediate, do nothing. */
11322 else if (is_digit_char (*op_string
)
11323 || is_identifier_char (*op_string
)
11324 || *op_string
== '"'
11325 || *op_string
== '(')
11327 /* This is a memory reference of some sort. */
11330 /* Start and end of displacement string expression (if found). */
11331 char *displacement_string_start
;
11332 char *displacement_string_end
;
11335 do_memory_reference
:
11336 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
11338 if ((i
.mem_operands
== 1
11339 && !current_templates
->start
->opcode_modifier
.isstring
)
11340 || i
.mem_operands
== 2)
11342 as_bad (_("too many memory references for `%s'"),
11343 current_templates
->start
->name
);
11347 /* Check for base index form. We detect the base index form by
11348 looking for an ')' at the end of the operand, searching
11349 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11351 base_string
= op_string
+ strlen (op_string
);
11353 /* Handle vector operations. */
11354 vop_start
= strchr (op_string
, '{');
11355 if (vop_start
&& vop_start
< base_string
)
11357 if (check_VecOperations (vop_start
, base_string
) == NULL
)
11359 base_string
= vop_start
;
11363 if (is_space_char (*base_string
))
11366 /* If we only have a displacement, set-up for it to be parsed later. */
11367 displacement_string_start
= op_string
;
11368 displacement_string_end
= base_string
+ 1;
11370 if (*base_string
== ')')
11373 unsigned int parens_balanced
= 1;
11374 /* We've already checked that the number of left & right ()'s are
11375 equal, so this loop will not be infinite. */
11379 if (*base_string
== ')')
11381 if (*base_string
== '(')
11384 while (parens_balanced
);
11386 temp_string
= base_string
;
11388 /* Skip past '(' and whitespace. */
11390 if (is_space_char (*base_string
))
11393 if (*base_string
== ','
11394 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
11397 displacement_string_end
= temp_string
;
11399 i
.types
[this_operand
].bitfield
.baseindex
= 1;
11403 if (i
.base_reg
== &bad_reg
)
11405 base_string
= end_op
;
11406 if (is_space_char (*base_string
))
11410 /* There may be an index reg or scale factor here. */
11411 if (*base_string
== ',')
11414 if (is_space_char (*base_string
))
11417 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
11420 if (i
.index_reg
== &bad_reg
)
11422 base_string
= end_op
;
11423 if (is_space_char (*base_string
))
11425 if (*base_string
== ',')
11428 if (is_space_char (*base_string
))
11431 else if (*base_string
!= ')')
11433 as_bad (_("expecting `,' or `)' "
11434 "after index register in `%s'"),
11439 else if (*base_string
== REGISTER_PREFIX
)
11441 end_op
= strchr (base_string
, ',');
11444 as_bad (_("bad register name `%s'"), base_string
);
11448 /* Check for scale factor. */
11449 if (*base_string
!= ')')
11451 char *end_scale
= i386_scale (base_string
);
11456 base_string
= end_scale
;
11457 if (is_space_char (*base_string
))
11459 if (*base_string
!= ')')
11461 as_bad (_("expecting `)' "
11462 "after scale factor in `%s'"),
11467 else if (!i
.index_reg
)
11469 as_bad (_("expecting index register or scale factor "
11470 "after `,'; got '%c'"),
11475 else if (*base_string
!= ')')
11477 as_bad (_("expecting `,' or `)' "
11478 "after base register in `%s'"),
11483 else if (*base_string
== REGISTER_PREFIX
)
11485 end_op
= strchr (base_string
, ',');
11488 as_bad (_("bad register name `%s'"), base_string
);
11493 /* If there's an expression beginning the operand, parse it,
11494 assuming displacement_string_start and
11495 displacement_string_end are meaningful. */
11496 if (displacement_string_start
!= displacement_string_end
)
11498 if (!i386_displacement (displacement_string_start
,
11499 displacement_string_end
))
11503 /* Special case for (%dx) while doing input/output op. */
11505 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
11506 && i
.base_reg
->reg_type
.bitfield
.word
11507 && i
.index_reg
== 0
11508 && i
.log2_scale_factor
== 0
11509 && i
.seg
[i
.mem_operands
] == 0
11510 && !operand_type_check (i
.types
[this_operand
], disp
))
11512 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
11516 if (i386_index_check (operand_string
) == 0)
11518 i
.flags
[this_operand
] |= Operand_Mem
;
11519 if (i
.mem_operands
== 0)
11520 i
.memop1_string
= xstrdup (operand_string
);
11525 /* It's not a memory operand; argh! */
11526 as_bad (_("invalid char %s beginning operand %d `%s'"),
11527 output_invalid (*op_string
),
11532 return 1; /* Normal return. */
11535 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11536 that an rs_machine_dependent frag may reach. */
11539 i386_frag_max_var (fragS
*frag
)
11541 /* The only relaxable frags are for jumps.
11542 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11543 gas_assert (frag
->fr_type
== rs_machine_dependent
);
11544 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11547 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11549 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11551 /* STT_GNU_IFUNC symbol must go through PLT. */
11552 if ((symbol_get_bfdsym (fr_symbol
)->flags
11553 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11556 if (!S_IS_EXTERNAL (fr_symbol
))
11557 /* Symbol may be weak or local. */
11558 return !S_IS_WEAK (fr_symbol
);
11560 /* Global symbols with non-default visibility can't be preempted. */
11561 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11564 if (fr_var
!= NO_RELOC
)
11565 switch ((enum bfd_reloc_code_real
) fr_var
)
11567 case BFD_RELOC_386_PLT32
:
11568 case BFD_RELOC_X86_64_PLT32
:
11569 /* Symbol with PLT relocation may be preempted. */
11575 /* Global symbols with default visibility in a shared library may be
11576 preempted by another definition. */
11581 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11582 Note also work for Skylake and Cascadelake.
11583 ---------------------------------------------------------------------
11584 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11585 | ------ | ----------- | ------- | -------- |
11587 | Jno | N | N | Y |
11588 | Jc/Jb | Y | N | Y |
11589 | Jae/Jnb | Y | N | Y |
11590 | Je/Jz | Y | Y | Y |
11591 | Jne/Jnz | Y | Y | Y |
11592 | Jna/Jbe | Y | N | Y |
11593 | Ja/Jnbe | Y | N | Y |
11595 | Jns | N | N | Y |
11596 | Jp/Jpe | N | N | Y |
11597 | Jnp/Jpo | N | N | Y |
11598 | Jl/Jnge | Y | Y | Y |
11599 | Jge/Jnl | Y | Y | Y |
11600 | Jle/Jng | Y | Y | Y |
11601 | Jg/Jnle | Y | Y | Y |
11602 --------------------------------------------------------------------- */
11604 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11606 if (mf_cmp
== mf_cmp_alu_cmp
)
11607 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11608 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11609 if (mf_cmp
== mf_cmp_incdec
)
11610 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11611 || mf_jcc
== mf_jcc_jle
);
11612 if (mf_cmp
== mf_cmp_test_and
)
11617 /* Return the next non-empty frag. */
11620 i386_next_non_empty_frag (fragS
*fragP
)
11622 /* There may be a frag with a ".fill 0" when there is no room in
11623 the current frag for frag_grow in output_insn. */
11624 for (fragP
= fragP
->fr_next
;
11626 && fragP
->fr_type
== rs_fill
11627 && fragP
->fr_fix
== 0);
11628 fragP
= fragP
->fr_next
)
11633 /* Return the next jcc frag after BRANCH_PADDING. */
11636 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11638 fragS
*branch_fragP
;
11642 if (pad_fragP
->fr_type
== rs_machine_dependent
11643 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11644 == BRANCH_PADDING
))
11646 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11647 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11649 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11650 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11651 pad_fragP
->tc_frag_data
.mf_type
))
11652 return branch_fragP
;
11658 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11661 i386_classify_machine_dependent_frag (fragS
*fragP
)
11665 fragS
*branch_fragP
;
11667 unsigned int max_prefix_length
;
11669 if (fragP
->tc_frag_data
.classified
)
11672 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11673 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11674 for (next_fragP
= fragP
;
11675 next_fragP
!= NULL
;
11676 next_fragP
= next_fragP
->fr_next
)
11678 next_fragP
->tc_frag_data
.classified
= 1;
11679 if (next_fragP
->fr_type
== rs_machine_dependent
)
11680 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11682 case BRANCH_PADDING
:
11683 /* The BRANCH_PADDING frag must be followed by a branch
11685 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11686 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11688 case FUSED_JCC_PADDING
:
11689 /* Check if this is a fused jcc:
11691 CMP like instruction
11695 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11696 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11697 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11700 /* The BRANCH_PADDING frag is merged with the
11701 FUSED_JCC_PADDING frag. */
11702 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11703 /* CMP like instruction size. */
11704 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11705 frag_wane (pad_fragP
);
11706 /* Skip to branch_fragP. */
11707 next_fragP
= branch_fragP
;
11709 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11711 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11713 next_fragP
->fr_subtype
11714 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11715 next_fragP
->tc_frag_data
.max_bytes
11716 = next_fragP
->tc_frag_data
.max_prefix_length
;
11717 /* This will be updated in the BRANCH_PREFIX scan. */
11718 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11721 frag_wane (next_fragP
);
11726 /* Stop if there is no BRANCH_PREFIX. */
11727 if (!align_branch_prefix_size
)
11730 /* Scan for BRANCH_PREFIX. */
11731 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11733 if (fragP
->fr_type
!= rs_machine_dependent
11734 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11738 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11739 COND_JUMP_PREFIX. */
11740 max_prefix_length
= 0;
11741 for (next_fragP
= fragP
;
11742 next_fragP
!= NULL
;
11743 next_fragP
= next_fragP
->fr_next
)
11745 if (next_fragP
->fr_type
== rs_fill
)
11746 /* Skip rs_fill frags. */
11748 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11749 /* Stop for all other frags. */
11752 /* rs_machine_dependent frags. */
11753 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11756 /* Count BRANCH_PREFIX frags. */
11757 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11759 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11760 frag_wane (next_fragP
);
11764 += next_fragP
->tc_frag_data
.max_bytes
;
11766 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11768 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11769 == FUSED_JCC_PADDING
))
11771 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11772 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11776 /* Stop for other rs_machine_dependent frags. */
11780 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11782 /* Skip to the next frag. */
11783 fragP
= next_fragP
;
11787 /* Compute padding size for
11790 CMP like instruction
11792 COND_JUMP/UNCOND_JUMP
11797 COND_JUMP/UNCOND_JUMP
11801 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11803 unsigned int offset
, size
, padding_size
;
11804 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11806 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11808 address
= fragP
->fr_address
;
11809 address
+= fragP
->fr_fix
;
11811 /* CMP like instrunction size. */
11812 size
= fragP
->tc_frag_data
.cmp_size
;
11814 /* The base size of the branch frag. */
11815 size
+= branch_fragP
->fr_fix
;
11817 /* Add opcode and displacement bytes for the rs_machine_dependent
11819 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11820 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11822 /* Check if branch is within boundary and doesn't end at the last
11824 offset
= address
& ((1U << align_branch_power
) - 1);
11825 if ((offset
+ size
) >= (1U << align_branch_power
))
11826 /* Padding needed to avoid crossing boundary. */
11827 padding_size
= (1U << align_branch_power
) - offset
;
11829 /* No padding needed. */
11832 /* The return value may be saved in tc_frag_data.length which is
11834 if (!fits_in_unsigned_byte (padding_size
))
11837 return padding_size
;
11840 /* i386_generic_table_relax_frag()
11842 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11843 grow/shrink padding to align branch frags. Hand others to
11847 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11849 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11850 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11852 long padding_size
= i386_branch_padding_size (fragP
, 0);
11853 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11855 /* When the BRANCH_PREFIX frag is used, the computed address
11856 must match the actual address and there should be no padding. */
11857 if (fragP
->tc_frag_data
.padding_address
11858 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11862 /* Update the padding size. */
11864 fragP
->tc_frag_data
.length
= padding_size
;
11868 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11870 fragS
*padding_fragP
, *next_fragP
;
11871 long padding_size
, left_size
, last_size
;
11873 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11874 if (!padding_fragP
)
11875 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11876 return (fragP
->tc_frag_data
.length
11877 - fragP
->tc_frag_data
.last_length
);
11879 /* Compute the relative address of the padding frag in the very
11880 first time where the BRANCH_PREFIX frag sizes are zero. */
11881 if (!fragP
->tc_frag_data
.padding_address
)
11882 fragP
->tc_frag_data
.padding_address
11883 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11885 /* First update the last length from the previous interation. */
11886 left_size
= fragP
->tc_frag_data
.prefix_length
;
11887 for (next_fragP
= fragP
;
11888 next_fragP
!= padding_fragP
;
11889 next_fragP
= next_fragP
->fr_next
)
11890 if (next_fragP
->fr_type
== rs_machine_dependent
11891 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11896 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11900 if (max
> left_size
)
11905 next_fragP
->tc_frag_data
.last_length
= size
;
11909 next_fragP
->tc_frag_data
.last_length
= 0;
11912 /* Check the padding size for the padding frag. */
11913 padding_size
= i386_branch_padding_size
11914 (padding_fragP
, (fragP
->fr_address
11915 + fragP
->tc_frag_data
.padding_address
));
11917 last_size
= fragP
->tc_frag_data
.prefix_length
;
11918 /* Check if there is change from the last interation. */
11919 if (padding_size
== last_size
)
11921 /* Update the expected address of the padding frag. */
11922 padding_fragP
->tc_frag_data
.padding_address
11923 = (fragP
->fr_address
+ padding_size
11924 + fragP
->tc_frag_data
.padding_address
);
11928 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11930 /* No padding if there is no sufficient room. Clear the
11931 expected address of the padding frag. */
11932 padding_fragP
->tc_frag_data
.padding_address
= 0;
11936 /* Store the expected address of the padding frag. */
11937 padding_fragP
->tc_frag_data
.padding_address
11938 = (fragP
->fr_address
+ padding_size
11939 + fragP
->tc_frag_data
.padding_address
);
11941 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11943 /* Update the length for the current interation. */
11944 left_size
= padding_size
;
11945 for (next_fragP
= fragP
;
11946 next_fragP
!= padding_fragP
;
11947 next_fragP
= next_fragP
->fr_next
)
11948 if (next_fragP
->fr_type
== rs_machine_dependent
11949 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11954 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11958 if (max
> left_size
)
11963 next_fragP
->tc_frag_data
.length
= size
;
11967 next_fragP
->tc_frag_data
.length
= 0;
11970 return (fragP
->tc_frag_data
.length
11971 - fragP
->tc_frag_data
.last_length
);
11973 return relax_frag (segment
, fragP
, stretch
);
11976 /* md_estimate_size_before_relax()
11978 Called just before relax() for rs_machine_dependent frags. The x86
11979 assembler uses these frags to handle variable size jump
11982 Any symbol that is now undefined will not become defined.
11983 Return the correct fr_subtype in the frag.
11984 Return the initial "guess for variable size of frag" to caller.
11985 The guess is actually the growth beyond the fixed part. Whatever
11986 we do to grow the fixed or variable part contributes to our
11990 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
11992 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11993 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
11994 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11996 i386_classify_machine_dependent_frag (fragP
);
11997 return fragP
->tc_frag_data
.length
;
12000 /* We've already got fragP->fr_subtype right; all we have to do is
12001 check for un-relaxable symbols. On an ELF system, we can't relax
12002 an externally visible symbol, because it may be overridden by a
12004 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
12005 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12007 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
12010 #if defined (OBJ_COFF) && defined (TE_PE)
12011 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
12012 && S_IS_WEAK (fragP
->fr_symbol
))
12016 /* Symbol is undefined in this segment, or we need to keep a
12017 reloc so that weak symbols can be overridden. */
12018 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
12019 enum bfd_reloc_code_real reloc_type
;
12020 unsigned char *opcode
;
12023 if (fragP
->fr_var
!= NO_RELOC
)
12024 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
12025 else if (size
== 2)
12026 reloc_type
= BFD_RELOC_16_PCREL
;
12027 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12028 else if (need_plt32_p (fragP
->fr_symbol
))
12029 reloc_type
= BFD_RELOC_X86_64_PLT32
;
12032 reloc_type
= BFD_RELOC_32_PCREL
;
12034 old_fr_fix
= fragP
->fr_fix
;
12035 opcode
= (unsigned char *) fragP
->fr_opcode
;
12037 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
12040 /* Make jmp (0xeb) a (d)word displacement jump. */
12042 fragP
->fr_fix
+= size
;
12043 fix_new (fragP
, old_fr_fix
, size
,
12045 fragP
->fr_offset
, 1,
12051 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
12053 /* Negate the condition, and branch past an
12054 unconditional jump. */
12057 /* Insert an unconditional jump. */
12059 /* We added two extra opcode bytes, and have a two byte
12061 fragP
->fr_fix
+= 2 + 2;
12062 fix_new (fragP
, old_fr_fix
+ 2, 2,
12064 fragP
->fr_offset
, 1,
12068 /* Fall through. */
12071 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
12075 fragP
->fr_fix
+= 1;
12076 fixP
= fix_new (fragP
, old_fr_fix
, 1,
12078 fragP
->fr_offset
, 1,
12079 BFD_RELOC_8_PCREL
);
12080 fixP
->fx_signed
= 1;
12084 /* This changes the byte-displacement jump 0x7N
12085 to the (d)word-displacement jump 0x0f,0x8N. */
12086 opcode
[1] = opcode
[0] + 0x10;
12087 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12088 /* We've added an opcode byte. */
12089 fragP
->fr_fix
+= 1 + size
;
12090 fix_new (fragP
, old_fr_fix
+ 1, size
,
12092 fragP
->fr_offset
, 1,
12097 BAD_CASE (fragP
->fr_subtype
);
12101 return fragP
->fr_fix
- old_fr_fix
;
12104 /* Guess size depending on current relax state. Initially the relax
12105 state will correspond to a short jump and we return 1, because
12106 the variable part of the frag (the branch offset) is one byte
12107 long. However, we can relax a section more than once and in that
12108 case we must either set fr_subtype back to the unrelaxed state,
12109 or return the value for the appropriate branch. */
12110 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
12113 /* Called after relax() is finished.
12115 In: Address of frag.
12116 fr_type == rs_machine_dependent.
12117 fr_subtype is what the address relaxed to.
12119 Out: Any fixSs and constants are set up.
12120 Caller will turn frag into a ".space 0". */
12123 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
12126 unsigned char *opcode
;
12127 unsigned char *where_to_put_displacement
= NULL
;
12128 offsetT target_address
;
12129 offsetT opcode_address
;
12130 unsigned int extension
= 0;
12131 offsetT displacement_from_opcode_start
;
12133 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
12134 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
12135 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12137 /* Generate nop padding. */
12138 unsigned int size
= fragP
->tc_frag_data
.length
;
12141 if (size
> fragP
->tc_frag_data
.max_bytes
)
12147 const char *branch
= "branch";
12148 const char *prefix
= "";
12149 fragS
*padding_fragP
;
12150 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
12153 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
12154 switch (fragP
->tc_frag_data
.default_prefix
)
12159 case CS_PREFIX_OPCODE
:
12162 case DS_PREFIX_OPCODE
:
12165 case ES_PREFIX_OPCODE
:
12168 case FS_PREFIX_OPCODE
:
12171 case GS_PREFIX_OPCODE
:
12174 case SS_PREFIX_OPCODE
:
12179 msg
= _("%s:%u: add %d%s at 0x%llx to align "
12180 "%s within %d-byte boundary\n");
12182 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
12183 "align %s within %d-byte boundary\n");
12187 padding_fragP
= fragP
;
12188 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12189 "%s within %d-byte boundary\n");
12193 switch (padding_fragP
->tc_frag_data
.branch_type
)
12195 case align_branch_jcc
:
12198 case align_branch_fused
:
12199 branch
= "fused jcc";
12201 case align_branch_jmp
:
12204 case align_branch_call
:
12207 case align_branch_indirect
:
12208 branch
= "indiret branch";
12210 case align_branch_ret
:
12217 fprintf (stdout
, msg
,
12218 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
12219 (long long) fragP
->fr_address
, branch
,
12220 1 << align_branch_power
);
12222 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12223 memset (fragP
->fr_opcode
,
12224 fragP
->tc_frag_data
.default_prefix
, size
);
12226 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
12228 fragP
->fr_fix
+= size
;
12233 opcode
= (unsigned char *) fragP
->fr_opcode
;
12235 /* Address we want to reach in file space. */
12236 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
12238 /* Address opcode resides at in file space. */
12239 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
12241 /* Displacement from opcode start to fill into instruction. */
12242 displacement_from_opcode_start
= target_address
- opcode_address
;
12244 if ((fragP
->fr_subtype
& BIG
) == 0)
12246 /* Don't have to change opcode. */
12247 extension
= 1; /* 1 opcode + 1 displacement */
12248 where_to_put_displacement
= &opcode
[1];
12252 if (no_cond_jump_promotion
12253 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
12254 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
12255 _("long jump required"));
12257 switch (fragP
->fr_subtype
)
12259 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
12260 extension
= 4; /* 1 opcode + 4 displacement */
12262 where_to_put_displacement
= &opcode
[1];
12265 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
12266 extension
= 2; /* 1 opcode + 2 displacement */
12268 where_to_put_displacement
= &opcode
[1];
12271 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
12272 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
12273 extension
= 5; /* 2 opcode + 4 displacement */
12274 opcode
[1] = opcode
[0] + 0x10;
12275 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12276 where_to_put_displacement
= &opcode
[2];
12279 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
12280 extension
= 3; /* 2 opcode + 2 displacement */
12281 opcode
[1] = opcode
[0] + 0x10;
12282 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12283 where_to_put_displacement
= &opcode
[2];
12286 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
12291 where_to_put_displacement
= &opcode
[3];
12295 BAD_CASE (fragP
->fr_subtype
);
12300 /* If size if less then four we are sure that the operand fits,
12301 but if it's 4, then it could be that the displacement is larger
12303 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
12305 && ((addressT
) (displacement_from_opcode_start
- extension
12306 + ((addressT
) 1 << 31))
12307 > (((addressT
) 2 << 31) - 1)))
12309 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
12310 _("jump target out of range"));
12311 /* Make us emit 0. */
12312 displacement_from_opcode_start
= extension
;
12314 /* Now put displacement after opcode. */
12315 md_number_to_chars ((char *) where_to_put_displacement
,
12316 (valueT
) (displacement_from_opcode_start
- extension
),
12317 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
12318 fragP
->fr_fix
+= extension
;
12321 /* Apply a fixup (fixP) to segment data, once it has been determined
12322 by our caller that we have all the info we need to fix it up.
12324 Parameter valP is the pointer to the value of the bits.
12326 On the 386, immediates, displacements, and data pointers are all in
12327 the same (little-endian) format, so we don't need to care about which
12328 we are handling. */
12331 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12333 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
12334 valueT value
= *valP
;
12336 #if !defined (TE_Mach)
12337 if (fixP
->fx_pcrel
)
12339 switch (fixP
->fx_r_type
)
12345 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
12348 case BFD_RELOC_X86_64_32S
:
12349 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
12352 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
12355 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
12360 if (fixP
->fx_addsy
!= NULL
12361 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
12362 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
12363 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
12364 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
12365 && !use_rela_relocations
)
12367 /* This is a hack. There should be a better way to handle this.
12368 This covers for the fact that bfd_install_relocation will
12369 subtract the current location (for partial_inplace, PC relative
12370 relocations); see more below. */
12374 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
12377 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12379 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12382 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
12384 if ((sym_seg
== seg
12385 || (symbol_section_p (fixP
->fx_addsy
)
12386 && sym_seg
!= absolute_section
))
12387 && !generic_force_reloc (fixP
))
12389 /* Yes, we add the values in twice. This is because
12390 bfd_install_relocation subtracts them out again. I think
12391 bfd_install_relocation is broken, but I don't dare change
12393 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12397 #if defined (OBJ_COFF) && defined (TE_PE)
12398 /* For some reason, the PE format does not store a
12399 section address offset for a PC relative symbol. */
12400 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
12401 || S_IS_WEAK (fixP
->fx_addsy
))
12402 value
+= md_pcrel_from (fixP
);
12405 #if defined (OBJ_COFF) && defined (TE_PE)
12406 if (fixP
->fx_addsy
!= NULL
12407 && S_IS_WEAK (fixP
->fx_addsy
)
12408 /* PR 16858: Do not modify weak function references. */
12409 && ! fixP
->fx_pcrel
)
12411 #if !defined (TE_PEP)
12412 /* For x86 PE weak function symbols are neither PC-relative
12413 nor do they set S_IS_FUNCTION. So the only reliable way
12414 to detect them is to check the flags of their containing
12416 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
12417 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
12421 value
-= S_GET_VALUE (fixP
->fx_addsy
);
12425 /* Fix a few things - the dynamic linker expects certain values here,
12426 and we must not disappoint it. */
12427 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12428 if (IS_ELF
&& fixP
->fx_addsy
)
12429 switch (fixP
->fx_r_type
)
12431 case BFD_RELOC_386_PLT32
:
12432 case BFD_RELOC_X86_64_PLT32
:
12433 /* Make the jump instruction point to the address of the operand.
12434 At runtime we merely add the offset to the actual PLT entry.
12435 NB: Subtract the offset size only for jump instructions. */
12436 if (fixP
->fx_pcrel
)
12440 case BFD_RELOC_386_TLS_GD
:
12441 case BFD_RELOC_386_TLS_LDM
:
12442 case BFD_RELOC_386_TLS_IE_32
:
12443 case BFD_RELOC_386_TLS_IE
:
12444 case BFD_RELOC_386_TLS_GOTIE
:
12445 case BFD_RELOC_386_TLS_GOTDESC
:
12446 case BFD_RELOC_X86_64_TLSGD
:
12447 case BFD_RELOC_X86_64_TLSLD
:
12448 case BFD_RELOC_X86_64_GOTTPOFF
:
12449 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12450 value
= 0; /* Fully resolved at runtime. No addend. */
12452 case BFD_RELOC_386_TLS_LE
:
12453 case BFD_RELOC_386_TLS_LDO_32
:
12454 case BFD_RELOC_386_TLS_LE_32
:
12455 case BFD_RELOC_X86_64_DTPOFF32
:
12456 case BFD_RELOC_X86_64_DTPOFF64
:
12457 case BFD_RELOC_X86_64_TPOFF32
:
12458 case BFD_RELOC_X86_64_TPOFF64
:
12459 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12462 case BFD_RELOC_386_TLS_DESC_CALL
:
12463 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12464 value
= 0; /* Fully resolved at runtime. No addend. */
12465 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12469 case BFD_RELOC_VTABLE_INHERIT
:
12470 case BFD_RELOC_VTABLE_ENTRY
:
12477 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12479 #endif /* !defined (TE_Mach) */
12481 /* Are we finished with this relocation now? */
12482 if (fixP
->fx_addsy
== NULL
)
12484 #if defined (OBJ_COFF) && defined (TE_PE)
12485 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
12488 /* Remember value for tc_gen_reloc. */
12489 fixP
->fx_addnumber
= value
;
12490 /* Clear out the frag for now. */
12494 else if (use_rela_relocations
)
12496 fixP
->fx_no_overflow
= 1;
12497 /* Remember value for tc_gen_reloc. */
12498 fixP
->fx_addnumber
= value
;
12502 md_number_to_chars (p
, value
, fixP
->fx_size
);
12506 md_atof (int type
, char *litP
, int *sizeP
)
12508 /* This outputs the LITTLENUMs in REVERSE order;
12509 in accord with the bigendian 386. */
12510 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
12513 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
12516 output_invalid (int c
)
12519 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12522 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12523 "(0x%x)", (unsigned char) c
);
12524 return output_invalid_buf
;
12527 /* Verify that @r can be used in the current context. */
12529 static bfd_boolean
check_register (const reg_entry
*r
)
12531 if (allow_pseudo_reg
)
12534 if (operand_type_all_zero (&r
->reg_type
))
12537 if ((r
->reg_type
.bitfield
.dword
12538 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12539 || r
->reg_type
.bitfield
.class == RegCR
12540 || r
->reg_type
.bitfield
.class == RegDR
)
12541 && !cpu_arch_flags
.bitfield
.cpui386
)
12544 if (r
->reg_type
.bitfield
.class == RegTR
12545 && (flag_code
== CODE_64BIT
12546 || !cpu_arch_flags
.bitfield
.cpui386
12547 || cpu_arch_isa_flags
.bitfield
.cpui586
12548 || cpu_arch_isa_flags
.bitfield
.cpui686
))
12551 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12554 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12556 if (r
->reg_type
.bitfield
.zmmword
12557 || r
->reg_type
.bitfield
.class == RegMask
)
12560 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12562 if (r
->reg_type
.bitfield
.ymmword
)
12565 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12570 if (r
->reg_type
.bitfield
.tmmword
12571 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
12572 || flag_code
!= CODE_64BIT
))
12575 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12578 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12579 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12582 /* Upper 16 vector registers are only available with VREX in 64bit
12583 mode, and require EVEX encoding. */
12584 if (r
->reg_flags
& RegVRex
)
12586 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12587 || flag_code
!= CODE_64BIT
)
12590 if (i
.vec_encoding
== vex_encoding_default
)
12591 i
.vec_encoding
= vex_encoding_evex
;
12592 else if (i
.vec_encoding
!= vex_encoding_evex
)
12593 i
.vec_encoding
= vex_encoding_error
;
12596 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12597 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12598 && flag_code
!= CODE_64BIT
)
12601 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12608 /* REG_STRING starts *before* REGISTER_PREFIX. */
12610 static const reg_entry
*
12611 parse_real_register (char *reg_string
, char **end_op
)
12613 char *s
= reg_string
;
12615 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
12616 const reg_entry
*r
;
12618 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12619 if (*s
== REGISTER_PREFIX
)
12622 if (is_space_char (*s
))
12625 p
= reg_name_given
;
12626 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
12628 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
12629 return (const reg_entry
*) NULL
;
12633 /* For naked regs, make sure that we are not dealing with an identifier.
12634 This prevents confusing an identifier like `eax_var' with register
12636 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12637 return (const reg_entry
*) NULL
;
12641 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
12643 /* Handle floating point regs, allowing spaces in the (i) part. */
12644 if (r
== i386_regtab
/* %st is first entry of table */)
12646 if (!cpu_arch_flags
.bitfield
.cpu8087
12647 && !cpu_arch_flags
.bitfield
.cpu287
12648 && !cpu_arch_flags
.bitfield
.cpu387
12649 && !allow_pseudo_reg
)
12650 return (const reg_entry
*) NULL
;
12652 if (is_space_char (*s
))
12657 if (is_space_char (*s
))
12659 if (*s
>= '0' && *s
<= '7')
12661 int fpr
= *s
- '0';
12663 if (is_space_char (*s
))
12668 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
12673 /* We have "%st(" then garbage. */
12674 return (const reg_entry
*) NULL
;
12678 return r
&& check_register (r
) ? r
: NULL
;
12681 /* REG_STRING starts *before* REGISTER_PREFIX. */
12683 static const reg_entry
*
12684 parse_register (char *reg_string
, char **end_op
)
12686 const reg_entry
*r
;
12688 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12689 r
= parse_real_register (reg_string
, end_op
);
12694 char *save
= input_line_pointer
;
12698 input_line_pointer
= reg_string
;
12699 c
= get_symbol_name (®_string
);
12700 symbolP
= symbol_find (reg_string
);
12701 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12703 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12705 know (e
->X_op
== O_register
);
12706 know (e
->X_add_number
>= 0
12707 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12708 r
= i386_regtab
+ e
->X_add_number
;
12709 if (!check_register (r
))
12711 as_bad (_("register '%s%s' cannot be used here"),
12712 register_prefix
, r
->reg_name
);
12715 *end_op
= input_line_pointer
;
12717 *input_line_pointer
= c
;
12718 input_line_pointer
= save
;
12724 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12726 const reg_entry
*r
;
12727 char *end
= input_line_pointer
;
12730 r
= parse_register (name
, &input_line_pointer
);
12731 if (r
&& end
<= input_line_pointer
)
12733 *nextcharP
= *input_line_pointer
;
12734 *input_line_pointer
= 0;
12737 e
->X_op
= O_register
;
12738 e
->X_add_number
= r
- i386_regtab
;
12741 e
->X_op
= O_illegal
;
12744 input_line_pointer
= end
;
12746 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12750 md_operand (expressionS
*e
)
12753 const reg_entry
*r
;
12755 switch (*input_line_pointer
)
12757 case REGISTER_PREFIX
:
12758 r
= parse_real_register (input_line_pointer
, &end
);
12761 e
->X_op
= O_register
;
12762 e
->X_add_number
= r
- i386_regtab
;
12763 input_line_pointer
= end
;
12768 gas_assert (intel_syntax
);
12769 end
= input_line_pointer
++;
12771 if (*input_line_pointer
== ']')
12773 ++input_line_pointer
;
12774 e
->X_op_symbol
= make_expr_symbol (e
);
12775 e
->X_add_symbol
= NULL
;
12776 e
->X_add_number
= 0;
12781 e
->X_op
= O_absent
;
12782 input_line_pointer
= end
;
12789 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12790 const char *md_shortopts
= "kVQ:sqnO::";
12792 const char *md_shortopts
= "qnO::";
12795 #define OPTION_32 (OPTION_MD_BASE + 0)
12796 #define OPTION_64 (OPTION_MD_BASE + 1)
12797 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12798 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12799 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12800 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12801 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12802 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12803 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12804 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12805 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12806 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12807 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12808 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12809 #define OPTION_X32 (OPTION_MD_BASE + 14)
12810 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12811 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12812 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12813 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12814 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12815 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12816 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12817 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12818 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12819 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12820 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12821 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12822 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12823 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12824 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12825 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12826 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
12827 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
12828 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
12830 struct option md_longopts
[] =
12832 {"32", no_argument
, NULL
, OPTION_32
},
12833 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12834 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12835 {"64", no_argument
, NULL
, OPTION_64
},
12837 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12838 {"x32", no_argument
, NULL
, OPTION_X32
},
12839 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12840 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12842 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12843 {"march", required_argument
, NULL
, OPTION_MARCH
},
12844 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12845 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12846 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12847 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12848 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12849 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12850 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12851 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12852 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12853 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12854 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12855 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12856 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12857 # if defined (TE_PE) || defined (TE_PEP)
12858 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12860 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12861 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12862 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12863 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12864 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12865 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12866 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12867 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12868 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
12869 {"mlfence-before-indirect-branch", required_argument
, NULL
,
12870 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
12871 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
12872 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12873 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12874 {NULL
, no_argument
, NULL
, 0}
12876 size_t md_longopts_size
= sizeof (md_longopts
);
12879 md_parse_option (int c
, const char *arg
)
12882 char *arch
, *next
, *saved
, *type
;
12887 optimize_align_code
= 0;
12891 quiet_warnings
= 1;
12894 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12895 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12896 should be emitted or not. FIXME: Not implemented. */
12898 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12902 /* -V: SVR4 argument to print version ID. */
12904 print_version_id ();
12907 /* -k: Ignore for FreeBSD compatibility. */
12912 /* -s: On i386 Solaris, this tells the native assembler to use
12913 .stab instead of .stab.excl. We always use .stab anyhow. */
12916 case OPTION_MSHARED
:
12920 case OPTION_X86_USED_NOTE
:
12921 if (strcasecmp (arg
, "yes") == 0)
12923 else if (strcasecmp (arg
, "no") == 0)
12926 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12931 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12932 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12935 const char **list
, **l
;
12937 list
= bfd_target_list ();
12938 for (l
= list
; *l
!= NULL
; l
++)
12939 if (CONST_STRNEQ (*l
, "elf64-x86-64")
12940 || strcmp (*l
, "coff-x86-64") == 0
12941 || strcmp (*l
, "pe-x86-64") == 0
12942 || strcmp (*l
, "pei-x86-64") == 0
12943 || strcmp (*l
, "mach-o-x86-64") == 0)
12945 default_arch
= "x86_64";
12949 as_fatal (_("no compiled in support for x86_64"));
12955 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12959 const char **list
, **l
;
12961 list
= bfd_target_list ();
12962 for (l
= list
; *l
!= NULL
; l
++)
12963 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
12965 default_arch
= "x86_64:32";
12969 as_fatal (_("no compiled in support for 32bit x86_64"));
12973 as_fatal (_("32bit x86_64 is only supported for ELF"));
12978 default_arch
= "i386";
12981 case OPTION_DIVIDE
:
12982 #ifdef SVR4_COMMENT_CHARS
12987 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
12989 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
12993 i386_comment_chars
= n
;
12999 saved
= xstrdup (arg
);
13001 /* Allow -march=+nosse. */
13007 as_fatal (_("invalid -march= option: `%s'"), arg
);
13008 next
= strchr (arch
, '+');
13011 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13013 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
13016 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13019 cpu_arch_name
= cpu_arch
[j
].name
;
13020 cpu_sub_arch_name
= NULL
;
13021 cpu_arch_flags
= cpu_arch
[j
].flags
;
13022 cpu_arch_isa
= cpu_arch
[j
].type
;
13023 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
13024 if (!cpu_arch_tune_set
)
13026 cpu_arch_tune
= cpu_arch_isa
;
13027 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13031 else if (*cpu_arch
[j
].name
== '.'
13032 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
13034 /* ISA extension. */
13035 i386_cpu_flags flags
;
13037 flags
= cpu_flags_or (cpu_arch_flags
,
13038 cpu_arch
[j
].flags
);
13040 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13042 if (cpu_sub_arch_name
)
13044 char *name
= cpu_sub_arch_name
;
13045 cpu_sub_arch_name
= concat (name
,
13047 (const char *) NULL
);
13051 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
13052 cpu_arch_flags
= flags
;
13053 cpu_arch_isa_flags
= flags
;
13057 = cpu_flags_or (cpu_arch_isa_flags
,
13058 cpu_arch
[j
].flags
);
13063 if (j
>= ARRAY_SIZE (cpu_arch
))
13065 /* Disable an ISA extension. */
13066 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13067 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
13069 i386_cpu_flags flags
;
13071 flags
= cpu_flags_and_not (cpu_arch_flags
,
13072 cpu_noarch
[j
].flags
);
13073 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
13075 if (cpu_sub_arch_name
)
13077 char *name
= cpu_sub_arch_name
;
13078 cpu_sub_arch_name
= concat (arch
,
13079 (const char *) NULL
);
13083 cpu_sub_arch_name
= xstrdup (arch
);
13084 cpu_arch_flags
= flags
;
13085 cpu_arch_isa_flags
= flags
;
13090 if (j
>= ARRAY_SIZE (cpu_noarch
))
13091 j
= ARRAY_SIZE (cpu_arch
);
13094 if (j
>= ARRAY_SIZE (cpu_arch
))
13095 as_fatal (_("invalid -march= option: `%s'"), arg
);
13099 while (next
!= NULL
);
13105 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13106 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13108 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
13110 cpu_arch_tune_set
= 1;
13111 cpu_arch_tune
= cpu_arch
[j
].type
;
13112 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
13116 if (j
>= ARRAY_SIZE (cpu_arch
))
13117 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
13120 case OPTION_MMNEMONIC
:
13121 if (strcasecmp (arg
, "att") == 0)
13122 intel_mnemonic
= 0;
13123 else if (strcasecmp (arg
, "intel") == 0)
13124 intel_mnemonic
= 1;
13126 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
13129 case OPTION_MSYNTAX
:
13130 if (strcasecmp (arg
, "att") == 0)
13132 else if (strcasecmp (arg
, "intel") == 0)
13135 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
13138 case OPTION_MINDEX_REG
:
13139 allow_index_reg
= 1;
13142 case OPTION_MNAKED_REG
:
13143 allow_naked_reg
= 1;
13146 case OPTION_MSSE2AVX
:
13150 case OPTION_MSSE_CHECK
:
13151 if (strcasecmp (arg
, "error") == 0)
13152 sse_check
= check_error
;
13153 else if (strcasecmp (arg
, "warning") == 0)
13154 sse_check
= check_warning
;
13155 else if (strcasecmp (arg
, "none") == 0)
13156 sse_check
= check_none
;
13158 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
13161 case OPTION_MOPERAND_CHECK
:
13162 if (strcasecmp (arg
, "error") == 0)
13163 operand_check
= check_error
;
13164 else if (strcasecmp (arg
, "warning") == 0)
13165 operand_check
= check_warning
;
13166 else if (strcasecmp (arg
, "none") == 0)
13167 operand_check
= check_none
;
13169 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
13172 case OPTION_MAVXSCALAR
:
13173 if (strcasecmp (arg
, "128") == 0)
13174 avxscalar
= vex128
;
13175 else if (strcasecmp (arg
, "256") == 0)
13176 avxscalar
= vex256
;
13178 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
13181 case OPTION_MVEXWIG
:
13182 if (strcmp (arg
, "0") == 0)
13184 else if (strcmp (arg
, "1") == 0)
13187 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
13190 case OPTION_MADD_BND_PREFIX
:
13191 add_bnd_prefix
= 1;
13194 case OPTION_MEVEXLIG
:
13195 if (strcmp (arg
, "128") == 0)
13196 evexlig
= evexl128
;
13197 else if (strcmp (arg
, "256") == 0)
13198 evexlig
= evexl256
;
13199 else if (strcmp (arg
, "512") == 0)
13200 evexlig
= evexl512
;
13202 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
13205 case OPTION_MEVEXRCIG
:
13206 if (strcmp (arg
, "rne") == 0)
13208 else if (strcmp (arg
, "rd") == 0)
13210 else if (strcmp (arg
, "ru") == 0)
13212 else if (strcmp (arg
, "rz") == 0)
13215 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
13218 case OPTION_MEVEXWIG
:
13219 if (strcmp (arg
, "0") == 0)
13221 else if (strcmp (arg
, "1") == 0)
13224 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
13227 # if defined (TE_PE) || defined (TE_PEP)
13228 case OPTION_MBIG_OBJ
:
13233 case OPTION_MOMIT_LOCK_PREFIX
:
13234 if (strcasecmp (arg
, "yes") == 0)
13235 omit_lock_prefix
= 1;
13236 else if (strcasecmp (arg
, "no") == 0)
13237 omit_lock_prefix
= 0;
13239 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
13242 case OPTION_MFENCE_AS_LOCK_ADD
:
13243 if (strcasecmp (arg
, "yes") == 0)
13245 else if (strcasecmp (arg
, "no") == 0)
13248 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
13251 case OPTION_MLFENCE_AFTER_LOAD
:
13252 if (strcasecmp (arg
, "yes") == 0)
13253 lfence_after_load
= 1;
13254 else if (strcasecmp (arg
, "no") == 0)
13255 lfence_after_load
= 0;
13257 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
13260 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
13261 if (strcasecmp (arg
, "all") == 0)
13263 lfence_before_indirect_branch
= lfence_branch_all
;
13264 if (lfence_before_ret
== lfence_before_ret_none
)
13265 lfence_before_ret
= lfence_before_ret_shl
;
13267 else if (strcasecmp (arg
, "memory") == 0)
13268 lfence_before_indirect_branch
= lfence_branch_memory
;
13269 else if (strcasecmp (arg
, "register") == 0)
13270 lfence_before_indirect_branch
= lfence_branch_register
;
13271 else if (strcasecmp (arg
, "none") == 0)
13272 lfence_before_indirect_branch
= lfence_branch_none
;
13274 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13278 case OPTION_MLFENCE_BEFORE_RET
:
13279 if (strcasecmp (arg
, "or") == 0)
13280 lfence_before_ret
= lfence_before_ret_or
;
13281 else if (strcasecmp (arg
, "not") == 0)
13282 lfence_before_ret
= lfence_before_ret_not
;
13283 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
13284 lfence_before_ret
= lfence_before_ret_shl
;
13285 else if (strcasecmp (arg
, "none") == 0)
13286 lfence_before_ret
= lfence_before_ret_none
;
13288 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13292 case OPTION_MRELAX_RELOCATIONS
:
13293 if (strcasecmp (arg
, "yes") == 0)
13294 generate_relax_relocations
= 1;
13295 else if (strcasecmp (arg
, "no") == 0)
13296 generate_relax_relocations
= 0;
13298 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
13301 case OPTION_MALIGN_BRANCH_BOUNDARY
:
13304 long int align
= strtoul (arg
, &end
, 0);
13309 align_branch_power
= 0;
13312 else if (align
>= 16)
13315 for (align_power
= 0;
13317 align
>>= 1, align_power
++)
13319 /* Limit alignment power to 31. */
13320 if (align
== 1 && align_power
< 32)
13322 align_branch_power
= align_power
;
13327 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
13331 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
13334 int align
= strtoul (arg
, &end
, 0);
13335 /* Some processors only support 5 prefixes. */
13336 if (*end
== '\0' && align
>= 0 && align
< 6)
13338 align_branch_prefix_size
= align
;
13341 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13346 case OPTION_MALIGN_BRANCH
:
13348 saved
= xstrdup (arg
);
13352 next
= strchr (type
, '+');
13355 if (strcasecmp (type
, "jcc") == 0)
13356 align_branch
|= align_branch_jcc_bit
;
13357 else if (strcasecmp (type
, "fused") == 0)
13358 align_branch
|= align_branch_fused_bit
;
13359 else if (strcasecmp (type
, "jmp") == 0)
13360 align_branch
|= align_branch_jmp_bit
;
13361 else if (strcasecmp (type
, "call") == 0)
13362 align_branch
|= align_branch_call_bit
;
13363 else if (strcasecmp (type
, "ret") == 0)
13364 align_branch
|= align_branch_ret_bit
;
13365 else if (strcasecmp (type
, "indirect") == 0)
13366 align_branch
|= align_branch_indirect_bit
;
13368 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
13371 while (next
!= NULL
);
13375 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
13376 align_branch_power
= 5;
13377 align_branch_prefix_size
= 5;
13378 align_branch
= (align_branch_jcc_bit
13379 | align_branch_fused_bit
13380 | align_branch_jmp_bit
);
13383 case OPTION_MAMD64
:
13387 case OPTION_MINTEL64
:
13395 /* Turn off -Os. */
13396 optimize_for_space
= 0;
13398 else if (*arg
== 's')
13400 optimize_for_space
= 1;
13401 /* Turn on all encoding optimizations. */
13402 optimize
= INT_MAX
;
13406 optimize
= atoi (arg
);
13407 /* Turn off -Os. */
13408 optimize_for_space
= 0;
13418 #define MESSAGE_TEMPLATE \
13422 output_message (FILE *stream
, char *p
, char *message
, char *start
,
13423 int *left_p
, const char *name
, int len
)
13425 int size
= sizeof (MESSAGE_TEMPLATE
);
13426 int left
= *left_p
;
13428 /* Reserve 2 spaces for ", " or ",\0" */
13431 /* Check if there is any room. */
13439 p
= mempcpy (p
, name
, len
);
13443 /* Output the current message now and start a new one. */
13446 fprintf (stream
, "%s\n", message
);
13448 left
= size
- (start
- message
) - len
- 2;
13450 gas_assert (left
>= 0);
13452 p
= mempcpy (p
, name
, len
);
13460 show_arch (FILE *stream
, int ext
, int check
)
13462 static char message
[] = MESSAGE_TEMPLATE
;
13463 char *start
= message
+ 27;
13465 int size
= sizeof (MESSAGE_TEMPLATE
);
13472 left
= size
- (start
- message
);
13473 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13475 /* Should it be skipped? */
13476 if (cpu_arch
[j
].skip
)
13479 name
= cpu_arch
[j
].name
;
13480 len
= cpu_arch
[j
].len
;
13483 /* It is an extension. Skip if we aren't asked to show it. */
13494 /* It is an processor. Skip if we show only extension. */
13497 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13499 /* It is an impossible processor - skip. */
13503 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
13506 /* Display disabled extensions. */
13508 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13510 name
= cpu_noarch
[j
].name
;
13511 len
= cpu_noarch
[j
].len
;
13512 p
= output_message (stream
, p
, message
, start
, &left
, name
,
13517 fprintf (stream
, "%s\n", message
);
13521 md_show_usage (FILE *stream
)
13523 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13524 fprintf (stream
, _("\
13525 -Qy, -Qn ignored\n\
13526 -V print assembler version number\n\
13529 fprintf (stream
, _("\
13530 -n Do not optimize code alignment\n\
13531 -q quieten some warnings\n"));
13532 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13533 fprintf (stream
, _("\
13536 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13537 || defined (TE_PE) || defined (TE_PEP))
13538 fprintf (stream
, _("\
13539 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
13541 #ifdef SVR4_COMMENT_CHARS
13542 fprintf (stream
, _("\
13543 --divide do not treat `/' as a comment character\n"));
13545 fprintf (stream
, _("\
13546 --divide ignored\n"));
13548 fprintf (stream
, _("\
13549 -march=CPU[,+EXTENSION...]\n\
13550 generate code for CPU and EXTENSION, CPU is one of:\n"));
13551 show_arch (stream
, 0, 1);
13552 fprintf (stream
, _("\
13553 EXTENSION is combination of:\n"));
13554 show_arch (stream
, 1, 0);
13555 fprintf (stream
, _("\
13556 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13557 show_arch (stream
, 0, 0);
13558 fprintf (stream
, _("\
13559 -msse2avx encode SSE instructions with VEX prefix\n"));
13560 fprintf (stream
, _("\
13561 -msse-check=[none|error|warning] (default: warning)\n\
13562 check SSE instructions\n"));
13563 fprintf (stream
, _("\
13564 -moperand-check=[none|error|warning] (default: warning)\n\
13565 check operand combinations for validity\n"));
13566 fprintf (stream
, _("\
13567 -mavxscalar=[128|256] (default: 128)\n\
13568 encode scalar AVX instructions with specific vector\n\
13570 fprintf (stream
, _("\
13571 -mvexwig=[0|1] (default: 0)\n\
13572 encode VEX instructions with specific VEX.W value\n\
13573 for VEX.W bit ignored instructions\n"));
13574 fprintf (stream
, _("\
13575 -mevexlig=[128|256|512] (default: 128)\n\
13576 encode scalar EVEX instructions with specific vector\n\
13578 fprintf (stream
, _("\
13579 -mevexwig=[0|1] (default: 0)\n\
13580 encode EVEX instructions with specific EVEX.W value\n\
13581 for EVEX.W bit ignored instructions\n"));
13582 fprintf (stream
, _("\
13583 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13584 encode EVEX instructions with specific EVEX.RC value\n\
13585 for SAE-only ignored instructions\n"));
13586 fprintf (stream
, _("\
13587 -mmnemonic=[att|intel] "));
13588 if (SYSV386_COMPAT
)
13589 fprintf (stream
, _("(default: att)\n"));
13591 fprintf (stream
, _("(default: intel)\n"));
13592 fprintf (stream
, _("\
13593 use AT&T/Intel mnemonic\n"));
13594 fprintf (stream
, _("\
13595 -msyntax=[att|intel] (default: att)\n\
13596 use AT&T/Intel syntax\n"));
13597 fprintf (stream
, _("\
13598 -mindex-reg support pseudo index registers\n"));
13599 fprintf (stream
, _("\
13600 -mnaked-reg don't require `%%' prefix for registers\n"));
13601 fprintf (stream
, _("\
13602 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13603 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13604 fprintf (stream
, _("\
13605 -mshared disable branch optimization for shared code\n"));
13606 fprintf (stream
, _("\
13607 -mx86-used-note=[no|yes] "));
13608 if (DEFAULT_X86_USED_NOTE
)
13609 fprintf (stream
, _("(default: yes)\n"));
13611 fprintf (stream
, _("(default: no)\n"));
13612 fprintf (stream
, _("\
13613 generate x86 used ISA and feature properties\n"));
13615 #if defined (TE_PE) || defined (TE_PEP)
13616 fprintf (stream
, _("\
13617 -mbig-obj generate big object files\n"));
13619 fprintf (stream
, _("\
13620 -momit-lock-prefix=[no|yes] (default: no)\n\
13621 strip all lock prefixes\n"));
13622 fprintf (stream
, _("\
13623 -mfence-as-lock-add=[no|yes] (default: no)\n\
13624 encode lfence, mfence and sfence as\n\
13625 lock addl $0x0, (%%{re}sp)\n"));
13626 fprintf (stream
, _("\
13627 -mrelax-relocations=[no|yes] "));
13628 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
13629 fprintf (stream
, _("(default: yes)\n"));
13631 fprintf (stream
, _("(default: no)\n"));
13632 fprintf (stream
, _("\
13633 generate relax relocations\n"));
13634 fprintf (stream
, _("\
13635 -malign-branch-boundary=NUM (default: 0)\n\
13636 align branches within NUM byte boundary\n"));
13637 fprintf (stream
, _("\
13638 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13639 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13641 specify types of branches to align\n"));
13642 fprintf (stream
, _("\
13643 -malign-branch-prefix-size=NUM (default: 5)\n\
13644 align branches with NUM prefixes per instruction\n"));
13645 fprintf (stream
, _("\
13646 -mbranches-within-32B-boundaries\n\
13647 align branches within 32 byte boundary\n"));
13648 fprintf (stream
, _("\
13649 -mlfence-after-load=[no|yes] (default: no)\n\
13650 generate lfence after load\n"));
13651 fprintf (stream
, _("\
13652 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
13653 generate lfence before indirect near branch\n"));
13654 fprintf (stream
, _("\
13655 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
13656 generate lfence before ret\n"));
13657 fprintf (stream
, _("\
13658 -mamd64 accept only AMD64 ISA [default]\n"));
13659 fprintf (stream
, _("\
13660 -mintel64 accept only Intel64 ISA\n"));
13663 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13664 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13665 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13667 /* Pick the target format to use. */
13670 i386_target_format (void)
13672 if (!strncmp (default_arch
, "x86_64", 6))
13674 update_code_flag (CODE_64BIT
, 1);
13675 if (default_arch
[6] == '\0')
13676 x86_elf_abi
= X86_64_ABI
;
13678 x86_elf_abi
= X86_64_X32_ABI
;
13680 else if (!strcmp (default_arch
, "i386"))
13681 update_code_flag (CODE_32BIT
, 1);
13682 else if (!strcmp (default_arch
, "iamcu"))
13684 update_code_flag (CODE_32BIT
, 1);
13685 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13687 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13688 cpu_arch_name
= "iamcu";
13689 cpu_sub_arch_name
= NULL
;
13690 cpu_arch_flags
= iamcu_flags
;
13691 cpu_arch_isa
= PROCESSOR_IAMCU
;
13692 cpu_arch_isa_flags
= iamcu_flags
;
13693 if (!cpu_arch_tune_set
)
13695 cpu_arch_tune
= cpu_arch_isa
;
13696 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13699 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13700 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13704 as_fatal (_("unknown architecture"));
13706 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13707 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13708 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13709 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13711 switch (OUTPUT_FLAVOR
)
13713 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13714 case bfd_target_aout_flavour
:
13715 return AOUT_TARGET_FORMAT
;
13717 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13718 # if defined (TE_PE) || defined (TE_PEP)
13719 case bfd_target_coff_flavour
:
13720 if (flag_code
== CODE_64BIT
)
13721 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13723 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
13724 # elif defined (TE_GO32)
13725 case bfd_target_coff_flavour
:
13726 return "coff-go32";
13728 case bfd_target_coff_flavour
:
13729 return "coff-i386";
13732 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13733 case bfd_target_elf_flavour
:
13735 const char *format
;
13737 switch (x86_elf_abi
)
13740 format
= ELF_TARGET_FORMAT
;
13742 tls_get_addr
= "___tls_get_addr";
13746 use_rela_relocations
= 1;
13749 tls_get_addr
= "__tls_get_addr";
13751 format
= ELF_TARGET_FORMAT64
;
13753 case X86_64_X32_ABI
:
13754 use_rela_relocations
= 1;
13757 tls_get_addr
= "__tls_get_addr";
13759 disallow_64bit_reloc
= 1;
13760 format
= ELF_TARGET_FORMAT32
;
13763 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13765 if (x86_elf_abi
!= X86_64_ABI
)
13766 as_fatal (_("Intel L1OM is 64bit only"));
13767 return ELF_TARGET_L1OM_FORMAT
;
13769 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13771 if (x86_elf_abi
!= X86_64_ABI
)
13772 as_fatal (_("Intel K1OM is 64bit only"));
13773 return ELF_TARGET_K1OM_FORMAT
;
13775 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13777 if (x86_elf_abi
!= I386_ABI
)
13778 as_fatal (_("Intel MCU is 32bit only"));
13779 return ELF_TARGET_IAMCU_FORMAT
;
13785 #if defined (OBJ_MACH_O)
13786 case bfd_target_mach_o_flavour
:
13787 if (flag_code
== CODE_64BIT
)
13789 use_rela_relocations
= 1;
13791 return "mach-o-x86-64";
13794 return "mach-o-i386";
13802 #endif /* OBJ_MAYBE_ more than one */
13805 md_undefined_symbol (char *name
)
13807 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13808 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13809 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13810 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
13814 if (symbol_find (name
))
13815 as_bad (_("GOT already in symbol table"));
13816 GOT_symbol
= symbol_new (name
, undefined_section
,
13817 (valueT
) 0, &zero_address_frag
);
13824 /* Round up a section size to the appropriate boundary. */
13827 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
13829 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13830 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
13832 /* For a.out, force the section size to be aligned. If we don't do
13833 this, BFD will align it for us, but it will not write out the
13834 final bytes of the section. This may be a bug in BFD, but it is
13835 easier to fix it here since that is how the other a.out targets
13839 align
= bfd_section_alignment (segment
);
13840 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13847 /* On the i386, PC-relative offsets are relative to the start of the
13848 next instruction. That is, the address of the offset, plus its
13849 size, since the offset is always the last part of the insn. */
13852 md_pcrel_from (fixS
*fixP
)
13854 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13860 s_bss (int ignore ATTRIBUTE_UNUSED
)
13864 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13866 obj_elf_section_change_hook ();
13868 temp
= get_absolute_expression ();
13869 subseg_set (bss_section
, (subsegT
) temp
);
13870 demand_empty_rest_of_line ();
13875 /* Remember constant directive. */
13878 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13880 if (last_insn
.kind
!= last_insn_directive
13881 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13883 last_insn
.seg
= now_seg
;
13884 last_insn
.kind
= last_insn_directive
;
13885 last_insn
.name
= "constant directive";
13886 last_insn
.file
= as_where (&last_insn
.line
);
13887 if (lfence_before_ret
!= lfence_before_ret_none
)
13889 if (lfence_before_indirect_branch
!= lfence_branch_none
)
13890 as_warn (_("constant directive skips -mlfence-before-ret "
13891 "and -mlfence-before-indirect-branch"));
13893 as_warn (_("constant directive skips -mlfence-before-ret"));
13895 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
13896 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
13901 i386_validate_fix (fixS
*fixp
)
13903 if (fixp
->fx_subsy
)
13905 if (fixp
->fx_subsy
== GOT_symbol
)
13907 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13911 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13912 if (fixp
->fx_tcbit2
)
13913 fixp
->fx_r_type
= (fixp
->fx_tcbit
13914 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13915 : BFD_RELOC_X86_64_GOTPCRELX
);
13918 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13923 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13925 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13927 fixp
->fx_subsy
= 0;
13930 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13933 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
13934 to section. Since PLT32 relocation must be against symbols,
13935 turn such PLT32 relocation into PC32 relocation. */
13937 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
13938 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
13939 && symbol_section_p (fixp
->fx_addsy
))
13940 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
13943 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13944 && fixp
->fx_tcbit2
)
13945 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
13952 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13955 bfd_reloc_code_real_type code
;
13957 switch (fixp
->fx_r_type
)
13959 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13960 case BFD_RELOC_SIZE32
:
13961 case BFD_RELOC_SIZE64
:
13962 if (S_IS_DEFINED (fixp
->fx_addsy
)
13963 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
13965 /* Resolve size relocation against local symbol to size of
13966 the symbol plus addend. */
13967 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
13968 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
13969 && !fits_in_unsigned_long (value
))
13970 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13971 _("symbol size computation overflow"));
13972 fixp
->fx_addsy
= NULL
;
13973 fixp
->fx_subsy
= NULL
;
13974 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
13978 /* Fall through. */
13980 case BFD_RELOC_X86_64_PLT32
:
13981 case BFD_RELOC_X86_64_GOT32
:
13982 case BFD_RELOC_X86_64_GOTPCREL
:
13983 case BFD_RELOC_X86_64_GOTPCRELX
:
13984 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13985 case BFD_RELOC_386_PLT32
:
13986 case BFD_RELOC_386_GOT32
:
13987 case BFD_RELOC_386_GOT32X
:
13988 case BFD_RELOC_386_GOTOFF
:
13989 case BFD_RELOC_386_GOTPC
:
13990 case BFD_RELOC_386_TLS_GD
:
13991 case BFD_RELOC_386_TLS_LDM
:
13992 case BFD_RELOC_386_TLS_LDO_32
:
13993 case BFD_RELOC_386_TLS_IE_32
:
13994 case BFD_RELOC_386_TLS_IE
:
13995 case BFD_RELOC_386_TLS_GOTIE
:
13996 case BFD_RELOC_386_TLS_LE_32
:
13997 case BFD_RELOC_386_TLS_LE
:
13998 case BFD_RELOC_386_TLS_GOTDESC
:
13999 case BFD_RELOC_386_TLS_DESC_CALL
:
14000 case BFD_RELOC_X86_64_TLSGD
:
14001 case BFD_RELOC_X86_64_TLSLD
:
14002 case BFD_RELOC_X86_64_DTPOFF32
:
14003 case BFD_RELOC_X86_64_DTPOFF64
:
14004 case BFD_RELOC_X86_64_GOTTPOFF
:
14005 case BFD_RELOC_X86_64_TPOFF32
:
14006 case BFD_RELOC_X86_64_TPOFF64
:
14007 case BFD_RELOC_X86_64_GOTOFF64
:
14008 case BFD_RELOC_X86_64_GOTPC32
:
14009 case BFD_RELOC_X86_64_GOT64
:
14010 case BFD_RELOC_X86_64_GOTPCREL64
:
14011 case BFD_RELOC_X86_64_GOTPC64
:
14012 case BFD_RELOC_X86_64_GOTPLT64
:
14013 case BFD_RELOC_X86_64_PLTOFF64
:
14014 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14015 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14016 case BFD_RELOC_RVA
:
14017 case BFD_RELOC_VTABLE_ENTRY
:
14018 case BFD_RELOC_VTABLE_INHERIT
:
14020 case BFD_RELOC_32_SECREL
:
14022 code
= fixp
->fx_r_type
;
14024 case BFD_RELOC_X86_64_32S
:
14025 if (!fixp
->fx_pcrel
)
14027 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
14028 code
= fixp
->fx_r_type
;
14031 /* Fall through. */
14033 if (fixp
->fx_pcrel
)
14035 switch (fixp
->fx_size
)
14038 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14039 _("can not do %d byte pc-relative relocation"),
14041 code
= BFD_RELOC_32_PCREL
;
14043 case 1: code
= BFD_RELOC_8_PCREL
; break;
14044 case 2: code
= BFD_RELOC_16_PCREL
; break;
14045 case 4: code
= BFD_RELOC_32_PCREL
; break;
14047 case 8: code
= BFD_RELOC_64_PCREL
; break;
14053 switch (fixp
->fx_size
)
14056 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14057 _("can not do %d byte relocation"),
14059 code
= BFD_RELOC_32
;
14061 case 1: code
= BFD_RELOC_8
; break;
14062 case 2: code
= BFD_RELOC_16
; break;
14063 case 4: code
= BFD_RELOC_32
; break;
14065 case 8: code
= BFD_RELOC_64
; break;
14072 if ((code
== BFD_RELOC_32
14073 || code
== BFD_RELOC_32_PCREL
14074 || code
== BFD_RELOC_X86_64_32S
)
14076 && fixp
->fx_addsy
== GOT_symbol
)
14079 code
= BFD_RELOC_386_GOTPC
;
14081 code
= BFD_RELOC_X86_64_GOTPC32
;
14083 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
14085 && fixp
->fx_addsy
== GOT_symbol
)
14087 code
= BFD_RELOC_X86_64_GOTPC64
;
14090 rel
= XNEW (arelent
);
14091 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
14092 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14094 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14096 if (!use_rela_relocations
)
14098 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
14099 vtable entry to be used in the relocation's section offset. */
14100 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14101 rel
->address
= fixp
->fx_offset
;
14102 #if defined (OBJ_COFF) && defined (TE_PE)
14103 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
14104 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
14109 /* Use the rela in 64bit mode. */
14112 if (disallow_64bit_reloc
)
14115 case BFD_RELOC_X86_64_DTPOFF64
:
14116 case BFD_RELOC_X86_64_TPOFF64
:
14117 case BFD_RELOC_64_PCREL
:
14118 case BFD_RELOC_X86_64_GOTOFF64
:
14119 case BFD_RELOC_X86_64_GOT64
:
14120 case BFD_RELOC_X86_64_GOTPCREL64
:
14121 case BFD_RELOC_X86_64_GOTPC64
:
14122 case BFD_RELOC_X86_64_GOTPLT64
:
14123 case BFD_RELOC_X86_64_PLTOFF64
:
14124 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14125 _("cannot represent relocation type %s in x32 mode"),
14126 bfd_get_reloc_code_name (code
));
14132 if (!fixp
->fx_pcrel
)
14133 rel
->addend
= fixp
->fx_offset
;
14137 case BFD_RELOC_X86_64_PLT32
:
14138 case BFD_RELOC_X86_64_GOT32
:
14139 case BFD_RELOC_X86_64_GOTPCREL
:
14140 case BFD_RELOC_X86_64_GOTPCRELX
:
14141 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
14142 case BFD_RELOC_X86_64_TLSGD
:
14143 case BFD_RELOC_X86_64_TLSLD
:
14144 case BFD_RELOC_X86_64_GOTTPOFF
:
14145 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
14146 case BFD_RELOC_X86_64_TLSDESC_CALL
:
14147 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
14150 rel
->addend
= (section
->vma
14152 + fixp
->fx_addnumber
14153 + md_pcrel_from (fixp
));
14158 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14159 if (rel
->howto
== NULL
)
14161 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14162 _("cannot represent relocation type %s"),
14163 bfd_get_reloc_code_name (code
));
14164 /* Set howto to a garbage value so that we can keep going. */
14165 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
14166 gas_assert (rel
->howto
!= NULL
);
14172 #include "tc-i386-intel.c"
14175 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
14177 int saved_naked_reg
;
14178 char saved_register_dot
;
14180 saved_naked_reg
= allow_naked_reg
;
14181 allow_naked_reg
= 1;
14182 saved_register_dot
= register_chars
['.'];
14183 register_chars
['.'] = '.';
14184 allow_pseudo_reg
= 1;
14185 expression_and_evaluate (exp
);
14186 allow_pseudo_reg
= 0;
14187 register_chars
['.'] = saved_register_dot
;
14188 allow_naked_reg
= saved_naked_reg
;
14190 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
14192 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
14194 exp
->X_op
= O_constant
;
14195 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
14196 .dw2_regnum
[flag_code
>> 1];
14199 exp
->X_op
= O_illegal
;
14204 tc_x86_frame_initial_instructions (void)
14206 static unsigned int sp_regno
[2];
14208 if (!sp_regno
[flag_code
>> 1])
14210 char *saved_input
= input_line_pointer
;
14211 char sp
[][4] = {"esp", "rsp"};
14214 input_line_pointer
= sp
[flag_code
>> 1];
14215 tc_x86_parse_to_dw2regnum (&exp
);
14216 gas_assert (exp
.X_op
== O_constant
);
14217 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
14218 input_line_pointer
= saved_input
;
14221 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
14222 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
14226 x86_dwarf2_addr_size (void)
14228 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14229 if (x86_elf_abi
== X86_64_X32_ABI
)
14232 return bfd_arch_bits_per_address (stdoutput
) / 8;
14236 i386_elf_section_type (const char *str
, size_t len
)
14238 if (flag_code
== CODE_64BIT
14239 && len
== sizeof ("unwind") - 1
14240 && strncmp (str
, "unwind", 6) == 0)
14241 return SHT_X86_64_UNWIND
;
14248 i386_solaris_fix_up_eh_frame (segT sec
)
14250 if (flag_code
== CODE_64BIT
)
14251 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
14257 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
14261 exp
.X_op
= O_secrel
;
14262 exp
.X_add_symbol
= symbol
;
14263 exp
.X_add_number
= 0;
14264 emit_expr (&exp
, size
);
14268 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14269 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14272 x86_64_section_letter (int letter
, const char **ptr_msg
)
14274 if (flag_code
== CODE_64BIT
)
14277 return SHF_X86_64_LARGE
;
14279 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14282 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
14287 x86_64_section_word (char *str
, size_t len
)
14289 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
14290 return SHF_X86_64_LARGE
;
14296 handle_large_common (int small ATTRIBUTE_UNUSED
)
14298 if (flag_code
!= CODE_64BIT
)
14300 s_comm_internal (0, elf_common_parse
);
14301 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14305 static segT lbss_section
;
14306 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
14307 asection
*saved_bss_section
= bss_section
;
14309 if (lbss_section
== NULL
)
14311 flagword applicable
;
14312 segT seg
= now_seg
;
14313 subsegT subseg
= now_subseg
;
14315 /* The .lbss section is for local .largecomm symbols. */
14316 lbss_section
= subseg_new (".lbss", 0);
14317 applicable
= bfd_applicable_section_flags (stdoutput
);
14318 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
14319 seg_info (lbss_section
)->bss
= 1;
14321 subseg_set (seg
, subseg
);
14324 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
14325 bss_section
= lbss_section
;
14327 s_comm_internal (0, elf_common_parse
);
14329 elf_com_section_ptr
= saved_com_section_ptr
;
14330 bss_section
= saved_bss_section
;
14333 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */