1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
30 #include "safe-ctype.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
34 #include "opcode/i386.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
44 #ifndef SCALE1_WHEN_NO_INDEX
45 /* Specifying a scale factor besides 1 when there is no index is
46 futile. eg. `mov (%ebx,2),%al' does exactly the same as
47 `mov (%ebx),%al'. To slavishly follow what the programmer
48 specified, set SCALE1_WHEN_NO_INDEX to 0. */
49 #define SCALE1_WHEN_NO_INDEX 1
53 #define DEFAULT_ARCH "i386"
58 #define INLINE __inline__
64 static INLINE
unsigned int mode_from_disp_size
PARAMS ((unsigned int));
65 static INLINE
int fits_in_signed_byte
PARAMS ((offsetT
));
66 static INLINE
int fits_in_unsigned_byte
PARAMS ((offsetT
));
67 static INLINE
int fits_in_unsigned_word
PARAMS ((offsetT
));
68 static INLINE
int fits_in_signed_word
PARAMS ((offsetT
));
69 static INLINE
int fits_in_unsigned_long
PARAMS ((offsetT
));
70 static INLINE
int fits_in_signed_long
PARAMS ((offsetT
));
71 static int smallest_imm_type
PARAMS ((offsetT
));
72 static offsetT offset_in_range
PARAMS ((offsetT
, int));
73 static int add_prefix
PARAMS ((unsigned int));
74 static void set_code_flag
PARAMS ((int));
75 static void set_16bit_gcc_code_flag
PARAMS ((int));
76 static void set_intel_syntax
PARAMS ((int));
77 static void set_cpu_arch
PARAMS ((int));
78 static char *output_invalid
PARAMS ((int c
));
79 static int i386_operand
PARAMS ((char *operand_string
));
80 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
81 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
83 static char *parse_insn
PARAMS ((char *, char *));
84 static char *parse_operands
PARAMS ((char *, const char *));
85 static void swap_operands
PARAMS ((void));
86 static void optimize_imm
PARAMS ((void));
87 static void optimize_disp
PARAMS ((void));
88 static int match_template
PARAMS ((void));
89 static int check_string
PARAMS ((void));
90 static int process_suffix
PARAMS ((void));
91 static int check_byte_reg
PARAMS ((void));
92 static int check_long_reg
PARAMS ((void));
93 static int check_qword_reg
PARAMS ((void));
94 static int check_word_reg
PARAMS ((void));
95 static int finalize_imm
PARAMS ((void));
96 static int process_operands
PARAMS ((void));
97 static const seg_entry
*build_modrm_byte
PARAMS ((void));
98 static void output_insn
PARAMS ((void));
99 static void output_branch
PARAMS ((void));
100 static void output_jump
PARAMS ((void));
101 static void output_interseg_jump
PARAMS ((void));
102 static void output_imm
PARAMS ((fragS
*insn_start_frag
,
103 offsetT insn_start_off
));
104 static void output_disp
PARAMS ((fragS
*insn_start_frag
,
105 offsetT insn_start_off
));
107 static void s_bss
PARAMS ((int));
110 static const char *default_arch
= DEFAULT_ARCH
;
112 /* 'md_assemble ()' gathers together information and puts it into a
119 const reg_entry
*regs
;
124 /* TM holds the template for the insn were currently assembling. */
127 /* SUFFIX holds the instruction mnemonic suffix if given.
128 (e.g. 'l' for 'movl') */
131 /* OPERANDS gives the number of given operands. */
132 unsigned int operands
;
134 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
135 of given register, displacement, memory operands and immediate
137 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
139 /* TYPES [i] is the type (see above #defines) which tells us how to
140 use OP[i] for the corresponding operand. */
141 unsigned int types
[MAX_OPERANDS
];
143 /* Displacement expression, immediate expression, or register for each
145 union i386_op op
[MAX_OPERANDS
];
147 /* Flags for operands. */
148 unsigned int flags
[MAX_OPERANDS
];
149 #define Operand_PCrel 1
151 /* Relocation type for operand */
152 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
154 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
155 the base index byte below. */
156 const reg_entry
*base_reg
;
157 const reg_entry
*index_reg
;
158 unsigned int log2_scale_factor
;
160 /* SEG gives the seg_entries of this insn. They are zero unless
161 explicit segment overrides are given. */
162 const seg_entry
*seg
[2];
164 /* PREFIX holds all the given prefix opcodes (usually null).
165 PREFIXES is the number of prefix opcodes. */
166 unsigned int prefixes
;
167 unsigned char prefix
[MAX_PREFIXES
];
169 /* RM and SIB are the modrm byte and the sib byte where the
170 addressing modes of this insn are encoded. */
177 typedef struct _i386_insn i386_insn
;
179 /* List of chars besides those in app.c:symbol_chars that can start an
180 operand. Used to prevent the scrubber eating vital white-space. */
182 const char extra_symbol_chars
[] = "*%-(@[";
184 const char extra_symbol_chars
[] = "*%-([";
187 #if (defined (TE_I386AIX) \
188 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
189 && !defined (TE_LINUX) \
190 && !defined (TE_FreeBSD) \
191 && !defined (TE_NetBSD)))
192 /* This array holds the chars that always start a comment. If the
193 pre-processor is disabled, these aren't very useful. */
194 const char comment_chars
[] = "#/";
195 #define PREFIX_SEPARATOR '\\'
197 /* This array holds the chars that only start a comment at the beginning of
198 a line. If the line seems to have the form '# 123 filename'
199 .line and .file directives will appear in the pre-processed output.
200 Note that input_file.c hand checks for '#' at the beginning of the
201 first line of the input file. This is because the compiler outputs
202 #NO_APP at the beginning of its output.
203 Also note that comments started like this one will always work if
204 '/' isn't otherwise defined. */
205 const char line_comment_chars
[] = "#";
208 /* Putting '/' here makes it impossible to use the divide operator.
209 However, we need it for compatibility with SVR4 systems. */
210 const char comment_chars
[] = "#";
211 #define PREFIX_SEPARATOR '/'
213 const char line_comment_chars
[] = "/#";
216 const char line_separator_chars
[] = ";";
218 /* Chars that can be used to separate mant from exp in floating point
220 const char EXP_CHARS
[] = "eE";
222 /* Chars that mean this number is a floating point constant
225 const char FLT_CHARS
[] = "fFdDxX";
227 /* Tables for lexical analysis. */
228 static char mnemonic_chars
[256];
229 static char register_chars
[256];
230 static char operand_chars
[256];
231 static char identifier_chars
[256];
232 static char digit_chars
[256];
234 /* Lexical macros. */
235 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
236 #define is_operand_char(x) (operand_chars[(unsigned char) x])
237 #define is_register_char(x) (register_chars[(unsigned char) x])
238 #define is_space_char(x) ((x) == ' ')
239 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
240 #define is_digit_char(x) (digit_chars[(unsigned char) x])
242 /* All non-digit non-letter charcters that may occur in an operand. */
243 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
245 /* md_assemble() always leaves the strings it's passed unaltered. To
246 effect this we maintain a stack of saved characters that we've smashed
247 with '\0's (indicating end of strings for various sub-fields of the
248 assembler instruction). */
249 static char save_stack
[32];
250 static char *save_stack_p
;
251 #define END_STRING_AND_SAVE(s) \
252 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
253 #define RESTORE_END_STRING(s) \
254 do { *(s) = *--save_stack_p; } while (0)
256 /* The instruction we're assembling. */
259 /* Possible templates for current insn. */
260 static const templates
*current_templates
;
262 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
263 static expressionS disp_expressions
[2], im_expressions
[2];
265 /* Current operand we are working on. */
266 static int this_operand
;
268 /* We support four different modes. FLAG_CODE variable is used to distinguish
275 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
277 static enum flag_code flag_code
;
278 static int use_rela_relocations
= 0;
280 /* The names used to print error messages. */
281 static const char *flag_code_names
[] =
288 /* 1 for intel syntax,
290 static int intel_syntax
= 0;
292 /* 1 if register prefix % not required. */
293 static int allow_naked_reg
= 0;
295 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
296 leave, push, and pop instructions so that gcc has the same stack
297 frame as in 32 bit mode. */
298 static char stackop_size
= '\0';
300 /* Non-zero to optimize code alignment. */
301 int optimize_align_code
= 1;
303 /* Non-zero to quieten some warnings. */
304 static int quiet_warnings
= 0;
307 static const char *cpu_arch_name
= NULL
;
309 /* CPU feature flags. */
310 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
312 /* If set, conditional jumps are not automatically promoted to handle
313 larger than a byte offset. */
314 static unsigned int no_cond_jump_promotion
= 0;
316 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
319 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
320 unsigned int x86_dwarf2_return_column
;
322 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
323 int x86_cie_data_alignment
;
325 /* Interface to relax_segment.
326 There are 3 major relax states for 386 jump insns because the
327 different types of jumps add different sizes to frags when we're
328 figuring out what sort of jump to choose to reach a given label. */
331 #define UNCOND_JUMP 0
333 #define COND_JUMP86 2
338 #define SMALL16 (SMALL | CODE16)
340 #define BIG16 (BIG | CODE16)
344 #define INLINE __inline__
350 #define ENCODE_RELAX_STATE(type, size) \
351 ((relax_substateT) (((type) << 2) | (size)))
352 #define TYPE_FROM_RELAX_STATE(s) \
354 #define DISP_SIZE_FROM_RELAX_STATE(s) \
355 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
357 /* This table is used by relax_frag to promote short jumps to long
358 ones where necessary. SMALL (short) jumps may be promoted to BIG
359 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
360 don't allow a short jump in a 32 bit code segment to be promoted to
361 a 16 bit offset jump because it's slower (requires data size
362 prefix), and doesn't work, unless the destination is in the bottom
363 64k of the code segment (The top 16 bits of eip are zeroed). */
365 const relax_typeS md_relax_table
[] =
368 1) most positive reach of this state,
369 2) most negative reach of this state,
370 3) how many bytes this mode will have in the variable part of the frag
371 4) which index into the table to try if we can't fit into this one. */
373 /* UNCOND_JUMP states. */
374 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
375 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
376 /* dword jmp adds 4 bytes to frag:
377 0 extra opcode bytes, 4 displacement bytes. */
379 /* word jmp adds 2 byte2 to frag:
380 0 extra opcode bytes, 2 displacement bytes. */
383 /* COND_JUMP states. */
384 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
385 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
386 /* dword conditionals adds 5 bytes to frag:
387 1 extra opcode byte, 4 displacement bytes. */
389 /* word conditionals add 3 bytes to frag:
390 1 extra opcode byte, 2 displacement bytes. */
393 /* COND_JUMP86 states. */
394 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
395 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
396 /* dword conditionals adds 5 bytes to frag:
397 1 extra opcode byte, 4 displacement bytes. */
399 /* word conditionals add 4 bytes to frag:
400 1 displacement byte and a 3 byte long branch insn. */
404 static const arch_entry cpu_arch
[] = {
406 {"i186", Cpu086
|Cpu186
},
407 {"i286", Cpu086
|Cpu186
|Cpu286
},
408 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
409 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
410 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
411 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
412 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
413 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
414 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
415 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
416 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
417 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
421 const pseudo_typeS md_pseudo_table
[] =
423 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
424 {"align", s_align_bytes
, 0},
426 {"align", s_align_ptwo
, 0},
428 {"arch", set_cpu_arch
, 0},
432 {"ffloat", float_cons
, 'f'},
433 {"dfloat", float_cons
, 'd'},
434 {"tfloat", float_cons
, 'x'},
436 {"noopt", s_ignore
, 0},
437 {"optim", s_ignore
, 0},
438 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
439 {"code16", set_code_flag
, CODE_16BIT
},
440 {"code32", set_code_flag
, CODE_32BIT
},
441 {"code64", set_code_flag
, CODE_64BIT
},
442 {"intel_syntax", set_intel_syntax
, 1},
443 {"att_syntax", set_intel_syntax
, 0},
444 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0},
445 {"loc", dwarf2_directive_loc
, 0},
449 /* For interface with expression (). */
450 extern char *input_line_pointer
;
452 /* Hash table for instruction mnemonic lookup. */
453 static struct hash_control
*op_hash
;
455 /* Hash table for register lookup. */
456 static struct hash_control
*reg_hash
;
459 i386_align_code (fragP
, count
)
463 /* Various efficient no-op patterns for aligning code labels.
464 Note: Don't try to assemble the instructions in the comments.
465 0L and 0w are not legal. */
466 static const char f32_1
[] =
468 static const char f32_2
[] =
469 {0x89,0xf6}; /* movl %esi,%esi */
470 static const char f32_3
[] =
471 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
472 static const char f32_4
[] =
473 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
474 static const char f32_5
[] =
476 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
477 static const char f32_6
[] =
478 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
479 static const char f32_7
[] =
480 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
481 static const char f32_8
[] =
483 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
484 static const char f32_9
[] =
485 {0x89,0xf6, /* movl %esi,%esi */
486 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
487 static const char f32_10
[] =
488 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
489 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
490 static const char f32_11
[] =
491 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
492 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
493 static const char f32_12
[] =
494 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
495 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
496 static const char f32_13
[] =
497 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
498 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
499 static const char f32_14
[] =
500 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
501 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
502 static const char f32_15
[] =
503 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
504 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
505 static const char f16_3
[] =
506 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
507 static const char f16_4
[] =
508 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
509 static const char f16_5
[] =
511 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
512 static const char f16_6
[] =
513 {0x89,0xf6, /* mov %si,%si */
514 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
515 static const char f16_7
[] =
516 {0x8d,0x74,0x00, /* lea 0(%si),%si */
517 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
518 static const char f16_8
[] =
519 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
520 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
521 static const char *const f32_patt
[] = {
522 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
523 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
525 static const char *const f16_patt
[] = {
526 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
527 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
530 if (count
<= 0 || count
> 15)
533 /* The recommended way to pad 64bit code is to use NOPs preceded by
534 maximally four 0x66 prefixes. Balance the size of nops. */
535 if (flag_code
== CODE_64BIT
)
538 int nnops
= (count
+ 3) / 4;
539 int len
= count
/ nnops
;
540 int remains
= count
- nnops
* len
;
543 for (i
= 0; i
< remains
; i
++)
545 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
546 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
549 for (; i
< nnops
; i
++)
551 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
552 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
557 if (flag_code
== CODE_16BIT
)
559 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
560 f16_patt
[count
- 1], count
);
562 /* Adjust jump offset. */
563 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
566 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
567 f32_patt
[count
- 1], count
);
568 fragP
->fr_var
= count
;
571 static INLINE
unsigned int
572 mode_from_disp_size (t
)
575 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
579 fits_in_signed_byte (num
)
582 return (num
>= -128) && (num
<= 127);
586 fits_in_unsigned_byte (num
)
589 return (num
& 0xff) == num
;
593 fits_in_unsigned_word (num
)
596 return (num
& 0xffff) == num
;
600 fits_in_signed_word (num
)
603 return (-32768 <= num
) && (num
<= 32767);
606 fits_in_signed_long (num
)
607 offsetT num ATTRIBUTE_UNUSED
;
612 return (!(((offsetT
) -1 << 31) & num
)
613 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
615 } /* fits_in_signed_long() */
617 fits_in_unsigned_long (num
)
618 offsetT num ATTRIBUTE_UNUSED
;
623 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
625 } /* fits_in_unsigned_long() */
628 smallest_imm_type (num
)
631 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
633 /* This code is disabled on the 486 because all the Imm1 forms
634 in the opcode table are slower on the i486. They're the
635 versions with the implicitly specified single-position
636 displacement, which has another syntax if you really want to
639 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
641 return (fits_in_signed_byte (num
)
642 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
643 : fits_in_unsigned_byte (num
)
644 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
645 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
646 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
647 : fits_in_signed_long (num
)
648 ? (Imm32
| Imm32S
| Imm64
)
649 : fits_in_unsigned_long (num
)
655 offset_in_range (val
, size
)
663 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
664 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
665 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
667 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
672 /* If BFD64, sign extend val. */
673 if (!use_rela_relocations
)
674 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
675 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
677 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
679 char buf1
[40], buf2
[40];
681 sprint_value (buf1
, val
);
682 sprint_value (buf2
, val
& mask
);
683 as_warn (_("%s shortened to %s"), buf1
, buf2
);
688 /* Returns 0 if attempting to add a prefix where one from the same
689 class already exists, 1 if non rep/repne added, 2 if rep/repne
698 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
699 && flag_code
== CODE_64BIT
)
707 case CS_PREFIX_OPCODE
:
708 case DS_PREFIX_OPCODE
:
709 case ES_PREFIX_OPCODE
:
710 case FS_PREFIX_OPCODE
:
711 case GS_PREFIX_OPCODE
:
712 case SS_PREFIX_OPCODE
:
716 case REPNE_PREFIX_OPCODE
:
717 case REPE_PREFIX_OPCODE
:
720 case LOCK_PREFIX_OPCODE
:
728 case ADDR_PREFIX_OPCODE
:
732 case DATA_PREFIX_OPCODE
:
737 if (i
.prefix
[q
] != 0)
739 as_bad (_("same type of prefix used twice"));
744 i
.prefix
[q
] = prefix
;
749 set_code_flag (value
)
753 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
754 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
755 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
757 as_bad (_("64bit mode not supported on this CPU."));
759 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
761 as_bad (_("32bit mode not supported on this CPU."));
767 set_16bit_gcc_code_flag (new_code_flag
)
770 flag_code
= new_code_flag
;
771 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
772 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
777 set_intel_syntax (syntax_flag
)
780 /* Find out if register prefixing is specified. */
781 int ask_naked_reg
= 0;
784 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
786 char *string
= input_line_pointer
;
787 int e
= get_symbol_end ();
789 if (strcmp (string
, "prefix") == 0)
791 else if (strcmp (string
, "noprefix") == 0)
794 as_bad (_("bad argument to syntax directive."));
795 *input_line_pointer
= e
;
797 demand_empty_rest_of_line ();
799 intel_syntax
= syntax_flag
;
801 if (ask_naked_reg
== 0)
802 allow_naked_reg
= (intel_syntax
803 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
805 allow_naked_reg
= (ask_naked_reg
< 0);
810 int dummy ATTRIBUTE_UNUSED
;
814 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
816 char *string
= input_line_pointer
;
817 int e
= get_symbol_end ();
820 for (i
= 0; cpu_arch
[i
].name
; i
++)
822 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
824 cpu_arch_name
= cpu_arch
[i
].name
;
825 cpu_arch_flags
= (cpu_arch
[i
].flags
826 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
830 if (!cpu_arch
[i
].name
)
831 as_bad (_("no such architecture: `%s'"), string
);
833 *input_line_pointer
= e
;
836 as_bad (_("missing cpu architecture"));
838 no_cond_jump_promotion
= 0;
839 if (*input_line_pointer
== ','
840 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
842 char *string
= ++input_line_pointer
;
843 int e
= get_symbol_end ();
845 if (strcmp (string
, "nojumps") == 0)
846 no_cond_jump_promotion
= 1;
847 else if (strcmp (string
, "jumps") == 0)
850 as_bad (_("no such architecture modifier: `%s'"), string
);
852 *input_line_pointer
= e
;
855 demand_empty_rest_of_line ();
861 if (!strcmp (default_arch
, "x86_64"))
862 return bfd_mach_x86_64
;
863 else if (!strcmp (default_arch
, "i386"))
864 return bfd_mach_i386_i386
;
866 as_fatal (_("Unknown architecture"));
872 const char *hash_err
;
874 /* Initialize op_hash hash table. */
875 op_hash
= hash_new ();
878 const template *optab
;
879 templates
*core_optab
;
881 /* Setup for loop. */
883 core_optab
= (templates
*) xmalloc (sizeof (templates
));
884 core_optab
->start
= optab
;
889 if (optab
->name
== NULL
890 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
892 /* different name --> ship out current template list;
893 add to hash table; & begin anew. */
894 core_optab
->end
= optab
;
895 hash_err
= hash_insert (op_hash
,
900 as_fatal (_("Internal Error: Can't hash %s: %s"),
904 if (optab
->name
== NULL
)
906 core_optab
= (templates
*) xmalloc (sizeof (templates
));
907 core_optab
->start
= optab
;
912 /* Initialize reg_hash hash table. */
913 reg_hash
= hash_new ();
915 const reg_entry
*regtab
;
917 for (regtab
= i386_regtab
;
918 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
921 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
923 as_fatal (_("Internal Error: Can't hash %s: %s"),
929 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
934 for (c
= 0; c
< 256; c
++)
939 mnemonic_chars
[c
] = c
;
940 register_chars
[c
] = c
;
941 operand_chars
[c
] = c
;
943 else if (ISLOWER (c
))
945 mnemonic_chars
[c
] = c
;
946 register_chars
[c
] = c
;
947 operand_chars
[c
] = c
;
949 else if (ISUPPER (c
))
951 mnemonic_chars
[c
] = TOLOWER (c
);
952 register_chars
[c
] = mnemonic_chars
[c
];
953 operand_chars
[c
] = c
;
956 if (ISALPHA (c
) || ISDIGIT (c
))
957 identifier_chars
[c
] = c
;
960 identifier_chars
[c
] = c
;
961 operand_chars
[c
] = c
;
966 identifier_chars
['@'] = '@';
968 digit_chars
['-'] = '-';
969 identifier_chars
['_'] = '_';
970 identifier_chars
['.'] = '.';
972 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
973 operand_chars
[(unsigned char) *p
] = *p
;
976 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
977 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
979 record_alignment (text_section
, 2);
980 record_alignment (data_section
, 2);
981 record_alignment (bss_section
, 2);
985 if (flag_code
== CODE_64BIT
)
987 x86_dwarf2_return_column
= 16;
988 x86_cie_data_alignment
= -8;
992 x86_dwarf2_return_column
= 8;
993 x86_cie_data_alignment
= -4;
998 i386_print_statistics (file
)
1001 hash_print_statistics (file
, "i386 opcode", op_hash
);
1002 hash_print_statistics (file
, "i386 register", reg_hash
);
1007 /* Debugging routines for md_assemble. */
1008 static void pi
PARAMS ((char *, i386_insn
*));
1009 static void pte
PARAMS ((template *));
1010 static void pt
PARAMS ((unsigned int));
1011 static void pe
PARAMS ((expressionS
*));
1012 static void ps
PARAMS ((symbolS
*));
1021 fprintf (stdout
, "%s: template ", line
);
1023 fprintf (stdout
, " address: base %s index %s scale %x\n",
1024 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1025 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1026 x
->log2_scale_factor
);
1027 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1028 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1029 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1030 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1031 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1032 (x
->rex
& REX_MODE64
) != 0,
1033 (x
->rex
& REX_EXTX
) != 0,
1034 (x
->rex
& REX_EXTY
) != 0,
1035 (x
->rex
& REX_EXTZ
) != 0);
1036 for (i
= 0; i
< x
->operands
; i
++)
1038 fprintf (stdout
, " #%d: ", i
+ 1);
1040 fprintf (stdout
, "\n");
1042 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1043 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1044 if (x
->types
[i
] & Imm
)
1046 if (x
->types
[i
] & Disp
)
1047 pe (x
->op
[i
].disps
);
1056 fprintf (stdout
, " %d operands ", t
->operands
);
1057 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1058 if (t
->extension_opcode
!= None
)
1059 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1060 if (t
->opcode_modifier
& D
)
1061 fprintf (stdout
, "D");
1062 if (t
->opcode_modifier
& W
)
1063 fprintf (stdout
, "W");
1064 fprintf (stdout
, "\n");
1065 for (i
= 0; i
< t
->operands
; i
++)
1067 fprintf (stdout
, " #%d type ", i
+ 1);
1068 pt (t
->operand_types
[i
]);
1069 fprintf (stdout
, "\n");
1077 fprintf (stdout
, " operation %d\n", e
->X_op
);
1078 fprintf (stdout
, " add_number %ld (%lx)\n",
1079 (long) e
->X_add_number
, (long) e
->X_add_number
);
1080 if (e
->X_add_symbol
)
1082 fprintf (stdout
, " add_symbol ");
1083 ps (e
->X_add_symbol
);
1084 fprintf (stdout
, "\n");
1088 fprintf (stdout
, " op_symbol ");
1089 ps (e
->X_op_symbol
);
1090 fprintf (stdout
, "\n");
1098 fprintf (stdout
, "%s type %s%s",
1100 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1101 segment_name (S_GET_SEGMENT (s
)));
1110 static const type_names
[] =
1123 { BaseIndex
, "BaseIndex" },
1127 { Disp32S
, "d32s" },
1129 { InOutPortReg
, "InOutPortReg" },
1130 { ShiftCount
, "ShiftCount" },
1131 { Control
, "control reg" },
1132 { Test
, "test reg" },
1133 { Debug
, "debug reg" },
1134 { FloatReg
, "FReg" },
1135 { FloatAcc
, "FAcc" },
1139 { JumpAbsolute
, "Jump Absolute" },
1150 const struct type_name
*ty
;
1152 for (ty
= type_names
; ty
->mask
; ty
++)
1154 fprintf (stdout
, "%s, ", ty
->tname
);
1158 #endif /* DEBUG386 */
1160 static bfd_reloc_code_real_type reloc
1161 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
1163 static bfd_reloc_code_real_type
1164 reloc (size
, pcrel
, sign
, other
)
1168 bfd_reloc_code_real_type other
;
1170 if (other
!= NO_RELOC
)
1176 as_bad (_("There are no unsigned pc-relative relocations"));
1179 case 1: return BFD_RELOC_8_PCREL
;
1180 case 2: return BFD_RELOC_16_PCREL
;
1181 case 4: return BFD_RELOC_32_PCREL
;
1183 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1190 case 4: return BFD_RELOC_X86_64_32S
;
1195 case 1: return BFD_RELOC_8
;
1196 case 2: return BFD_RELOC_16
;
1197 case 4: return BFD_RELOC_32
;
1198 case 8: return BFD_RELOC_64
;
1200 as_bad (_("can not do %s %d byte relocation"),
1201 sign
? "signed" : "unsigned", size
);
1205 return BFD_RELOC_NONE
;
1208 /* Here we decide which fixups can be adjusted to make them relative to
1209 the beginning of the section instead of the symbol. Basically we need
1210 to make sure that the dynamic relocations are done correctly, so in
1211 some cases we force the original symbol to be used. */
1214 tc_i386_fix_adjustable (fixP
)
1215 fixS
*fixP ATTRIBUTE_UNUSED
;
1217 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1218 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
1221 /* Don't adjust pc-relative references to merge sections in 64-bit
1223 if (use_rela_relocations
1224 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1228 /* adjust_reloc_syms doesn't know about the GOT. */
1229 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1230 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1231 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1232 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1233 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1234 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1235 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1236 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1237 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1238 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1239 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1240 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1241 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1242 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1243 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1244 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1245 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1246 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1247 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1248 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1249 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1255 static int intel_float_operand
PARAMS ((const char *mnemonic
));
1258 intel_float_operand (mnemonic
)
1259 const char *mnemonic
;
1261 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1264 if (mnemonic
[0] == 'f')
1270 /* This is the guts of the machine-dependent assembler. LINE points to a
1271 machine dependent instruction. This function is supposed to emit
1272 the frags/bytes it assembles to. */
1279 char mnemonic
[MAX_MNEM_SIZE
];
1281 /* Initialize globals. */
1282 memset (&i
, '\0', sizeof (i
));
1283 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1284 i
.reloc
[j
] = NO_RELOC
;
1285 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1286 memset (im_expressions
, '\0', sizeof (im_expressions
));
1287 save_stack_p
= save_stack
;
1289 /* First parse an instruction mnemonic & call i386_operand for the operands.
1290 We assume that the scrubber has arranged it so that line[0] is the valid
1291 start of a (possibly prefixed) mnemonic. */
1293 line
= parse_insn (line
, mnemonic
);
1297 line
= parse_operands (line
, mnemonic
);
1301 /* Now we've parsed the mnemonic into a set of templates, and have the
1302 operands at hand. */
1304 /* All intel opcodes have reversed operands except for "bound" and
1305 "enter". We also don't reverse intersegment "jmp" and "call"
1306 instructions with 2 immediate operands so that the immediate segment
1307 precedes the offset, as it does when in AT&T mode. "enter" and the
1308 intersegment "jmp" and "call" instructions are the only ones that
1309 have two immediate operands. */
1310 if (intel_syntax
&& i
.operands
> 1
1311 && (strcmp (mnemonic
, "bound") != 0)
1312 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1318 if (i
.disp_operands
)
1321 /* Next, we find a template that matches the given insn,
1322 making sure the overlap of the given operands types is consistent
1323 with the template operand types. */
1325 if (!match_template ())
1330 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1332 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1333 i
.tm
.base_opcode
^= FloatR
;
1335 /* Zap movzx and movsx suffix. The suffix may have been set from
1336 "word ptr" or "byte ptr" on the source operand, but we'll use
1337 the suffix later to choose the destination register. */
1338 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1342 if (i
.tm
.opcode_modifier
& FWait
)
1343 if (!add_prefix (FWAIT_OPCODE
))
1346 /* Check string instruction segment overrides. */
1347 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1349 if (!check_string ())
1353 if (!process_suffix ())
1356 /* Make still unresolved immediate matches conform to size of immediate
1357 given in i.suffix. */
1358 if (!finalize_imm ())
1361 if (i
.types
[0] & Imm1
)
1362 i
.imm_operands
= 0; /* kludge for shift insns. */
1363 if (i
.types
[0] & ImplicitRegister
)
1365 if (i
.types
[1] & ImplicitRegister
)
1367 if (i
.types
[2] & ImplicitRegister
)
1370 if (i
.tm
.opcode_modifier
& ImmExt
)
1374 if ((i
.tm
.cpu_flags
& CpuPNI
) && i
.operands
> 0)
1376 /* These Intel Precott New Instructions have the fixed
1377 operands with an opcode suffix which is coded in the same
1378 place as an 8-bit immediate field would be. Here we check
1379 those operands and remove them afterwards. */
1382 for (x
= 0; x
< i
.operands
; x
++)
1383 if (i
.op
[x
].regs
->reg_num
!= x
)
1384 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1385 i
.op
[x
].regs
->reg_name
, x
+ 1, i
.tm
.name
);
1389 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1390 opcode suffix which is coded in the same place as an 8-bit
1391 immediate field would be. Here we fake an 8-bit immediate
1392 operand from the opcode suffix stored in tm.extension_opcode. */
1394 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1396 exp
= &im_expressions
[i
.imm_operands
++];
1397 i
.op
[i
.operands
].imms
= exp
;
1398 i
.types
[i
.operands
++] = Imm8
;
1399 exp
->X_op
= O_constant
;
1400 exp
->X_add_number
= i
.tm
.extension_opcode
;
1401 i
.tm
.extension_opcode
= None
;
1404 /* For insns with operands there are more diddles to do to the opcode. */
1407 if (!process_operands ())
1410 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1412 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1413 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1416 /* Handle conversion of 'int $3' --> special int3 insn. */
1417 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1419 i
.tm
.base_opcode
= INT3_OPCODE
;
1423 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1424 && i
.op
[0].disps
->X_op
== O_constant
)
1426 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1427 the absolute address given by the constant. Since ix86 jumps and
1428 calls are pc relative, we need to generate a reloc. */
1429 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1430 i
.op
[0].disps
->X_op
= O_symbol
;
1433 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1434 i
.rex
|= REX_MODE64
;
1436 /* For 8 bit registers we need an empty rex prefix. Also if the
1437 instruction already has a prefix, we need to convert old
1438 registers to new ones. */
1440 if (((i
.types
[0] & Reg8
) != 0
1441 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1442 || ((i
.types
[1] & Reg8
) != 0
1443 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1444 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1449 i
.rex
|= REX_OPCODE
;
1450 for (x
= 0; x
< 2; x
++)
1452 /* Look for 8 bit operand that uses old registers. */
1453 if ((i
.types
[x
] & Reg8
) != 0
1454 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1456 /* In case it is "hi" register, give up. */
1457 if (i
.op
[x
].regs
->reg_num
> 3)
1458 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"),
1459 i
.op
[x
].regs
->reg_name
);
1461 /* Otherwise it is equivalent to the extended register.
1462 Since the encoding doesn't change this is merely
1463 cosmetic cleanup for debug output. */
1465 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1471 add_prefix (REX_OPCODE
| i
.rex
);
1473 /* We are ready to output the insn. */
1478 parse_insn (line
, mnemonic
)
1483 char *token_start
= l
;
1486 /* Non-zero if we found a prefix only acceptable with string insns. */
1487 const char *expecting_string_instruction
= NULL
;
1492 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1495 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1497 as_bad (_("no such instruction: `%s'"), token_start
);
1502 if (!is_space_char (*l
)
1503 && *l
!= END_OF_INSN
1504 && *l
!= PREFIX_SEPARATOR
1507 as_bad (_("invalid character %s in mnemonic"),
1508 output_invalid (*l
));
1511 if (token_start
== l
)
1513 if (*l
== PREFIX_SEPARATOR
)
1514 as_bad (_("expecting prefix; got nothing"));
1516 as_bad (_("expecting mnemonic; got nothing"));
1520 /* Look up instruction (or prefix) via hash table. */
1521 current_templates
= hash_find (op_hash
, mnemonic
);
1523 if (*l
!= END_OF_INSN
1524 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1525 && current_templates
1526 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1528 /* If we are in 16-bit mode, do not allow addr16 or data16.
1529 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1530 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1531 && flag_code
!= CODE_64BIT
1532 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1533 ^ (flag_code
== CODE_16BIT
)))
1535 as_bad (_("redundant %s prefix"),
1536 current_templates
->start
->name
);
1539 /* Add prefix, checking for repeated prefixes. */
1540 switch (add_prefix (current_templates
->start
->base_opcode
))
1545 expecting_string_instruction
= current_templates
->start
->name
;
1548 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1555 if (!current_templates
)
1557 /* See if we can get a match by trimming off a suffix. */
1560 case WORD_MNEM_SUFFIX
:
1561 case BYTE_MNEM_SUFFIX
:
1562 case QWORD_MNEM_SUFFIX
:
1563 i
.suffix
= mnem_p
[-1];
1565 current_templates
= hash_find (op_hash
, mnemonic
);
1567 case SHORT_MNEM_SUFFIX
:
1568 case LONG_MNEM_SUFFIX
:
1571 i
.suffix
= mnem_p
[-1];
1573 current_templates
= hash_find (op_hash
, mnemonic
);
1581 if (intel_float_operand (mnemonic
))
1582 i
.suffix
= SHORT_MNEM_SUFFIX
;
1584 i
.suffix
= LONG_MNEM_SUFFIX
;
1586 current_templates
= hash_find (op_hash
, mnemonic
);
1590 if (!current_templates
)
1592 as_bad (_("no such instruction: `%s'"), token_start
);
1597 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1599 /* Check for a branch hint. We allow ",pt" and ",pn" for
1600 predict taken and predict not taken respectively.
1601 I'm not sure that branch hints actually do anything on loop
1602 and jcxz insns (JumpByte) for current Pentium4 chips. They
1603 may work in the future and it doesn't hurt to accept them
1605 if (l
[0] == ',' && l
[1] == 'p')
1609 if (!add_prefix (DS_PREFIX_OPCODE
))
1613 else if (l
[2] == 'n')
1615 if (!add_prefix (CS_PREFIX_OPCODE
))
1621 /* Any other comma loses. */
1624 as_bad (_("invalid character %s in mnemonic"),
1625 output_invalid (*l
));
1629 /* Check if instruction is supported on specified architecture. */
1630 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1631 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1633 as_warn (_("`%s' is not supported on `%s'"),
1634 current_templates
->start
->name
, cpu_arch_name
);
1636 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1638 as_warn (_("use .code16 to ensure correct addressing mode"));
1641 /* Check for rep/repne without a string instruction. */
1642 if (expecting_string_instruction
1643 && !(current_templates
->start
->opcode_modifier
& IsString
))
1645 as_bad (_("expecting string instruction after `%s'"),
1646 expecting_string_instruction
);
1654 parse_operands (l
, mnemonic
)
1656 const char *mnemonic
;
1660 /* 1 if operand is pending after ','. */
1661 unsigned int expecting_operand
= 0;
1663 /* Non-zero if operand parens not balanced. */
1664 unsigned int paren_not_balanced
;
1666 while (*l
!= END_OF_INSN
)
1668 /* Skip optional white space before operand. */
1669 if (is_space_char (*l
))
1671 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1673 as_bad (_("invalid character %s before operand %d"),
1674 output_invalid (*l
),
1678 token_start
= l
; /* after white space */
1679 paren_not_balanced
= 0;
1680 while (paren_not_balanced
|| *l
!= ',')
1682 if (*l
== END_OF_INSN
)
1684 if (paren_not_balanced
)
1687 as_bad (_("unbalanced parenthesis in operand %d."),
1690 as_bad (_("unbalanced brackets in operand %d."),
1695 break; /* we are done */
1697 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1699 as_bad (_("invalid character %s in operand %d"),
1700 output_invalid (*l
),
1707 ++paren_not_balanced
;
1709 --paren_not_balanced
;
1714 ++paren_not_balanced
;
1716 --paren_not_balanced
;
1720 if (l
!= token_start
)
1721 { /* Yes, we've read in another operand. */
1722 unsigned int operand_ok
;
1723 this_operand
= i
.operands
++;
1724 if (i
.operands
> MAX_OPERANDS
)
1726 as_bad (_("spurious operands; (%d operands/instruction max)"),
1730 /* Now parse operand adding info to 'i' as we go along. */
1731 END_STRING_AND_SAVE (l
);
1735 i386_intel_operand (token_start
,
1736 intel_float_operand (mnemonic
));
1738 operand_ok
= i386_operand (token_start
);
1740 RESTORE_END_STRING (l
);
1746 if (expecting_operand
)
1748 expecting_operand_after_comma
:
1749 as_bad (_("expecting operand after ','; got nothing"));
1754 as_bad (_("expecting operand before ','; got nothing"));
1759 /* Now *l must be either ',' or END_OF_INSN. */
1762 if (*++l
== END_OF_INSN
)
1764 /* Just skip it, if it's \n complain. */
1765 goto expecting_operand_after_comma
;
1767 expecting_operand
= 1;
1776 union i386_op temp_op
;
1777 unsigned int temp_type
;
1778 enum bfd_reloc_code_real temp_reloc
;
1782 if (i
.operands
== 2)
1787 else if (i
.operands
== 3)
1792 temp_type
= i
.types
[xchg2
];
1793 i
.types
[xchg2
] = i
.types
[xchg1
];
1794 i
.types
[xchg1
] = temp_type
;
1795 temp_op
= i
.op
[xchg2
];
1796 i
.op
[xchg2
] = i
.op
[xchg1
];
1797 i
.op
[xchg1
] = temp_op
;
1798 temp_reloc
= i
.reloc
[xchg2
];
1799 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1800 i
.reloc
[xchg1
] = temp_reloc
;
1802 if (i
.mem_operands
== 2)
1804 const seg_entry
*temp_seg
;
1805 temp_seg
= i
.seg
[0];
1806 i
.seg
[0] = i
.seg
[1];
1807 i
.seg
[1] = temp_seg
;
1811 /* Try to ensure constant immediates are represented in the smallest
1816 char guess_suffix
= 0;
1820 guess_suffix
= i
.suffix
;
1821 else if (i
.reg_operands
)
1823 /* Figure out a suffix from the last register operand specified.
1824 We can't do this properly yet, ie. excluding InOutPortReg,
1825 but the following works for instructions with immediates.
1826 In any case, we can't set i.suffix yet. */
1827 for (op
= i
.operands
; --op
>= 0;)
1828 if (i
.types
[op
] & Reg
)
1830 if (i
.types
[op
] & Reg8
)
1831 guess_suffix
= BYTE_MNEM_SUFFIX
;
1832 else if (i
.types
[op
] & Reg16
)
1833 guess_suffix
= WORD_MNEM_SUFFIX
;
1834 else if (i
.types
[op
] & Reg32
)
1835 guess_suffix
= LONG_MNEM_SUFFIX
;
1836 else if (i
.types
[op
] & Reg64
)
1837 guess_suffix
= QWORD_MNEM_SUFFIX
;
1841 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1842 guess_suffix
= WORD_MNEM_SUFFIX
;
1844 for (op
= i
.operands
; --op
>= 0;)
1845 if (i
.types
[op
] & Imm
)
1847 switch (i
.op
[op
].imms
->X_op
)
1850 /* If a suffix is given, this operand may be shortened. */
1851 switch (guess_suffix
)
1853 case LONG_MNEM_SUFFIX
:
1854 i
.types
[op
] |= Imm32
| Imm64
;
1856 case WORD_MNEM_SUFFIX
:
1857 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1859 case BYTE_MNEM_SUFFIX
:
1860 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1864 /* If this operand is at most 16 bits, convert it
1865 to a signed 16 bit number before trying to see
1866 whether it will fit in an even smaller size.
1867 This allows a 16-bit operand such as $0xffe0 to
1868 be recognised as within Imm8S range. */
1869 if ((i
.types
[op
] & Imm16
)
1870 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
1872 i
.op
[op
].imms
->X_add_number
=
1873 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1875 if ((i
.types
[op
] & Imm32
)
1876 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
1879 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
1880 ^ ((offsetT
) 1 << 31))
1881 - ((offsetT
) 1 << 31));
1883 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1885 /* We must avoid matching of Imm32 templates when 64bit
1886 only immediate is available. */
1887 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1888 i
.types
[op
] &= ~Imm32
;
1895 /* Symbols and expressions. */
1897 /* Convert symbolic operand to proper sizes for matching. */
1898 switch (guess_suffix
)
1900 case QWORD_MNEM_SUFFIX
:
1901 i
.types
[op
] = Imm64
| Imm32S
;
1903 case LONG_MNEM_SUFFIX
:
1904 i
.types
[op
] = Imm32
| Imm64
;
1906 case WORD_MNEM_SUFFIX
:
1907 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1910 case BYTE_MNEM_SUFFIX
:
1911 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1920 /* Try to use the smallest displacement type too. */
1926 for (op
= i
.operands
; --op
>= 0;)
1927 if ((i
.types
[op
] & Disp
) && i
.op
[op
].disps
->X_op
== O_constant
)
1929 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1931 if (i
.types
[op
] & Disp16
)
1933 /* We know this operand is at most 16 bits, so
1934 convert to a signed 16 bit number before trying
1935 to see whether it will fit in an even smaller
1938 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1940 else if (i
.types
[op
] & Disp32
)
1942 /* We know this operand is at most 32 bits, so convert to a
1943 signed 32 bit number before trying to see whether it will
1944 fit in an even smaller size. */
1945 disp
&= (((offsetT
) 2 << 31) - 1);
1946 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1948 if (flag_code
== CODE_64BIT
)
1950 if (fits_in_signed_long (disp
))
1951 i
.types
[op
] |= Disp32S
;
1952 if (fits_in_unsigned_long (disp
))
1953 i
.types
[op
] |= Disp32
;
1955 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1956 && fits_in_signed_byte (disp
))
1957 i
.types
[op
] |= Disp8
;
1964 /* Points to template once we've found it. */
1966 unsigned int overlap0
, overlap1
, overlap2
;
1967 unsigned int found_reverse_match
;
1970 #define MATCH(overlap, given, template) \
1971 ((overlap & ~JumpAbsolute) \
1972 && (((given) & (BaseIndex | JumpAbsolute)) \
1973 == ((overlap) & (BaseIndex | JumpAbsolute))))
1975 /* If given types r0 and r1 are registers they must be of the same type
1976 unless the expected operand type register overlap is null.
1977 Note that Acc in a template matches every size of reg. */
1978 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1979 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
1980 || ((g0) & Reg) == ((g1) & Reg) \
1981 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1986 found_reverse_match
= 0;
1987 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1989 : (i
.suffix
== WORD_MNEM_SUFFIX
1991 : (i
.suffix
== SHORT_MNEM_SUFFIX
1993 : (i
.suffix
== LONG_MNEM_SUFFIX
1995 : (i
.suffix
== QWORD_MNEM_SUFFIX
1997 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
1998 ? No_xSuf
: 0))))));
2000 for (t
= current_templates
->start
;
2001 t
< current_templates
->end
;
2004 /* Must have right number of operands. */
2005 if (i
.operands
!= t
->operands
)
2008 /* Check the suffix, except for some instructions in intel mode. */
2009 if ((t
->opcode_modifier
& suffix_check
)
2011 && (t
->opcode_modifier
& IgnoreSize
))
2013 && t
->base_opcode
== 0xd9
2014 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
2015 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
2018 /* Do not verify operands when there are none. */
2019 else if (!t
->operands
)
2021 if (t
->cpu_flags
& ~cpu_arch_flags
)
2023 /* We've found a match; break out of loop. */
2027 overlap0
= i
.types
[0] & t
->operand_types
[0];
2028 switch (t
->operands
)
2031 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
2036 overlap1
= i
.types
[1] & t
->operand_types
[1];
2037 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
2038 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
2039 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2040 t
->operand_types
[0],
2041 overlap1
, i
.types
[1],
2042 t
->operand_types
[1]))
2044 /* Check if other direction is valid ... */
2045 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2048 /* Try reversing direction of operands. */
2049 overlap0
= i
.types
[0] & t
->operand_types
[1];
2050 overlap1
= i
.types
[1] & t
->operand_types
[0];
2051 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
2052 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
2053 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2054 t
->operand_types
[1],
2055 overlap1
, i
.types
[1],
2056 t
->operand_types
[0]))
2058 /* Does not match either direction. */
2061 /* found_reverse_match holds which of D or FloatDR
2063 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2065 /* Found a forward 2 operand match here. */
2066 else if (t
->operands
== 3)
2068 /* Here we make use of the fact that there are no
2069 reverse match 3 operand instructions, and all 3
2070 operand instructions only need to be checked for
2071 register consistency between operands 2 and 3. */
2072 overlap2
= i
.types
[2] & t
->operand_types
[2];
2073 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
2074 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
2075 t
->operand_types
[1],
2076 overlap2
, i
.types
[2],
2077 t
->operand_types
[2]))
2081 /* Found either forward/reverse 2 or 3 operand match here:
2082 slip through to break. */
2084 if (t
->cpu_flags
& ~cpu_arch_flags
)
2086 found_reverse_match
= 0;
2089 /* We've found a match; break out of loop. */
2093 if (t
== current_templates
->end
)
2095 /* We found no match. */
2096 as_bad (_("suffix or operands invalid for `%s'"),
2097 current_templates
->start
->name
);
2101 if (!quiet_warnings
)
2104 && ((i
.types
[0] & JumpAbsolute
)
2105 != (t
->operand_types
[0] & JumpAbsolute
)))
2107 as_warn (_("indirect %s without `*'"), t
->name
);
2110 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2111 == (IsPrefix
| IgnoreSize
))
2113 /* Warn them that a data or address size prefix doesn't
2114 affect assembly of the next line of code. */
2115 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2119 /* Copy the template we found. */
2121 if (found_reverse_match
)
2123 /* If we found a reverse match we must alter the opcode
2124 direction bit. found_reverse_match holds bits to change
2125 (different for int & float insns). */
2127 i
.tm
.base_opcode
^= found_reverse_match
;
2129 i
.tm
.operand_types
[0] = t
->operand_types
[1];
2130 i
.tm
.operand_types
[1] = t
->operand_types
[0];
2139 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2140 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2142 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2144 as_bad (_("`%s' operand %d must use `%%es' segment"),
2149 /* There's only ever one segment override allowed per instruction.
2150 This instruction possibly has a legal segment override on the
2151 second operand, so copy the segment to where non-string
2152 instructions store it, allowing common code. */
2153 i
.seg
[0] = i
.seg
[1];
2155 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2157 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2159 as_bad (_("`%s' operand %d must use `%%es' segment"),
2171 /* If matched instruction specifies an explicit instruction mnemonic
2173 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2175 if (i
.tm
.opcode_modifier
& Size16
)
2176 i
.suffix
= WORD_MNEM_SUFFIX
;
2177 else if (i
.tm
.opcode_modifier
& Size64
)
2178 i
.suffix
= QWORD_MNEM_SUFFIX
;
2180 i
.suffix
= LONG_MNEM_SUFFIX
;
2182 else if (i
.reg_operands
)
2184 /* If there's no instruction mnemonic suffix we try to invent one
2185 based on register operands. */
2188 /* We take i.suffix from the last register operand specified,
2189 Destination register type is more significant than source
2192 for (op
= i
.operands
; --op
>= 0;)
2193 if ((i
.types
[op
] & Reg
)
2194 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2196 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2197 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2198 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2203 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2205 if (!check_byte_reg ())
2208 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2210 if (!check_long_reg ())
2213 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2215 if (!check_qword_reg ())
2218 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2220 if (!check_word_reg ())
2223 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2224 /* Do nothing if the instruction is going to ignore the prefix. */
2229 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2231 i
.suffix
= stackop_size
;
2234 /* Change the opcode based on the operand size given by i.suffix;
2235 We need not change things for byte insns. */
2237 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2239 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2243 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2245 /* It's not a byte, select word/dword operation. */
2246 if (i
.tm
.opcode_modifier
& W
)
2248 if (i
.tm
.opcode_modifier
& ShortForm
)
2249 i
.tm
.base_opcode
|= 8;
2251 i
.tm
.base_opcode
|= 1;
2254 /* Now select between word & dword operations via the operand
2255 size prefix, except for instructions that will ignore this
2257 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2258 && !(i
.tm
.opcode_modifier
& IgnoreSize
)
2259 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2260 || (flag_code
== CODE_64BIT
2261 && (i
.tm
.opcode_modifier
& JumpByte
))))
2263 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2264 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2265 prefix
= ADDR_PREFIX_OPCODE
;
2267 if (!add_prefix (prefix
))
2271 /* Set mode64 for an operand. */
2272 if (i
.suffix
== QWORD_MNEM_SUFFIX
2273 && flag_code
== CODE_64BIT
2274 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2275 i
.rex
|= REX_MODE64
;
2277 /* Size floating point instruction. */
2278 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2280 if (i
.tm
.opcode_modifier
& FloatMF
)
2281 i
.tm
.base_opcode
^= 4;
2292 for (op
= i
.operands
; --op
>= 0;)
2294 /* If this is an eight bit register, it's OK. If it's the 16 or
2295 32 bit version of an eight bit register, we will just use the
2296 low portion, and that's OK too. */
2297 if (i
.types
[op
] & Reg8
)
2300 /* movzx and movsx should not generate this warning. */
2302 && (i
.tm
.base_opcode
== 0xfb7
2303 || i
.tm
.base_opcode
== 0xfb6
2304 || i
.tm
.base_opcode
== 0x63
2305 || i
.tm
.base_opcode
== 0xfbe
2306 || i
.tm
.base_opcode
== 0xfbf))
2309 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
2311 /* Check that the template allows eight bit regs. This
2312 kills insns such as `orb $1,%edx', which maybe should be
2314 && (i
.tm
.operand_types
[op
] & (Reg8
| InOutPortReg
))
2318 /* Prohibit these changes in the 64bit mode, since the
2319 lowering is more complicated. */
2320 if (flag_code
== CODE_64BIT
2321 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2323 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2324 i
.op
[op
].regs
->reg_name
,
2328 #if REGISTER_WARNINGS
2330 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2331 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2332 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
2333 ? REGNAM_AL
- REGNAM_AX
2334 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2335 i
.op
[op
].regs
->reg_name
,
2340 /* Any other register is bad. */
2341 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2343 | Control
| Debug
| Test
2344 | FloatReg
| FloatAcc
))
2346 as_bad (_("`%%%s' not allowed with `%s%c'"),
2347 i
.op
[op
].regs
->reg_name
,
2361 for (op
= i
.operands
; --op
>= 0;)
2362 /* Reject eight bit registers, except where the template requires
2363 them. (eg. movzb) */
2364 if ((i
.types
[op
] & Reg8
) != 0
2365 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2367 as_bad (_("`%%%s' not allowed with `%s%c'"),
2368 i
.op
[op
].regs
->reg_name
,
2373 /* Warn if the e prefix on a general reg is missing. */
2374 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2375 && (i
.types
[op
] & Reg16
) != 0
2376 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2378 /* Prohibit these changes in the 64bit mode, since the
2379 lowering is more complicated. */
2380 if (flag_code
== CODE_64BIT
)
2382 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2383 i
.op
[op
].regs
->reg_name
,
2387 #if REGISTER_WARNINGS
2389 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2390 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2391 i
.op
[op
].regs
->reg_name
,
2395 /* Warn if the r prefix on a general reg is missing. */
2396 else if ((i
.types
[op
] & Reg64
) != 0
2397 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2399 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2400 i
.op
[op
].regs
->reg_name
,
2412 for (op
= i
.operands
; --op
>= 0; )
2413 /* Reject eight bit registers, except where the template requires
2414 them. (eg. movzb) */
2415 if ((i
.types
[op
] & Reg8
) != 0
2416 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2418 as_bad (_("`%%%s' not allowed with `%s%c'"),
2419 i
.op
[op
].regs
->reg_name
,
2424 /* Warn if the e prefix on a general reg is missing. */
2425 else if (((i
.types
[op
] & Reg16
) != 0
2426 || (i
.types
[op
] & Reg32
) != 0)
2427 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2429 /* Prohibit these changes in the 64bit mode, since the
2430 lowering is more complicated. */
2431 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2432 i
.op
[op
].regs
->reg_name
,
2443 for (op
= i
.operands
; --op
>= 0;)
2444 /* Reject eight bit registers, except where the template requires
2445 them. (eg. movzb) */
2446 if ((i
.types
[op
] & Reg8
) != 0
2447 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2449 as_bad (_("`%%%s' not allowed with `%s%c'"),
2450 i
.op
[op
].regs
->reg_name
,
2455 /* Warn if the e prefix on a general reg is present. */
2456 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2457 && (i
.types
[op
] & Reg32
) != 0
2458 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
2460 /* Prohibit these changes in the 64bit mode, since the
2461 lowering is more complicated. */
2462 if (flag_code
== CODE_64BIT
)
2464 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2465 i
.op
[op
].regs
->reg_name
,
2470 #if REGISTER_WARNINGS
2471 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2472 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2473 i
.op
[op
].regs
->reg_name
,
2483 unsigned int overlap0
, overlap1
, overlap2
;
2485 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
2486 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2487 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2488 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2489 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2493 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2495 : (i
.suffix
== WORD_MNEM_SUFFIX
2497 : (i
.suffix
== QWORD_MNEM_SUFFIX
2501 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2502 || overlap0
== (Imm16
| Imm32
)
2503 || overlap0
== (Imm16
| Imm32S
))
2505 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2508 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2509 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2510 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2512 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2516 i
.types
[0] = overlap0
;
2518 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
2519 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2520 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2521 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2522 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2526 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2528 : (i
.suffix
== WORD_MNEM_SUFFIX
2530 : (i
.suffix
== QWORD_MNEM_SUFFIX
2534 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2535 || overlap1
== (Imm16
| Imm32
)
2536 || overlap1
== (Imm16
| Imm32S
))
2538 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2541 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2542 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2543 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2545 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2549 i
.types
[1] = overlap1
;
2551 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
2552 assert ((overlap2
& Imm
) == 0);
2553 i
.types
[2] = overlap2
;
2561 /* Default segment register this instruction will use for memory
2562 accesses. 0 means unknown. This is only for optimizing out
2563 unnecessary segment overrides. */
2564 const seg_entry
*default_seg
= 0;
2566 /* The imul $imm, %reg instruction is converted into
2567 imul $imm, %reg, %reg, and the clr %reg instruction
2568 is converted into xor %reg, %reg. */
2569 if (i
.tm
.opcode_modifier
& regKludge
)
2571 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2572 /* Pretend we saw the extra register operand. */
2573 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2574 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2575 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2579 if (i
.tm
.opcode_modifier
& ShortForm
)
2581 /* The register or float register operand is in operand 0 or 1. */
2582 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2583 /* Register goes in low 3 bits of opcode. */
2584 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2585 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2587 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2589 /* Warn about some common errors, but press on regardless.
2590 The first case can be generated by gcc (<= 2.8.1). */
2591 if (i
.operands
== 2)
2593 /* Reversed arguments on faddp, fsubp, etc. */
2594 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2595 i
.op
[1].regs
->reg_name
,
2596 i
.op
[0].regs
->reg_name
);
2600 /* Extraneous `l' suffix on fp insn. */
2601 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2602 i
.op
[0].regs
->reg_name
);
2606 else if (i
.tm
.opcode_modifier
& Modrm
)
2608 /* The opcode is completed (modulo i.tm.extension_opcode which
2609 must be put into the modrm byte). Now, we make the modrm and
2610 index base bytes based on all the info we've collected. */
2612 default_seg
= build_modrm_byte ();
2614 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2616 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2617 && i
.op
[0].regs
->reg_num
== 1)
2619 as_bad (_("you can't `pop %%cs'"));
2622 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2623 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
2626 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
2630 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2632 /* For the string instructions that allow a segment override
2633 on one of their operands, the default segment is ds. */
2637 if (i
.tm
.base_opcode
== 0x8d /* lea */ && i
.seg
[0] && !quiet_warnings
)
2638 as_warn (_("segment override on `lea' is ineffectual"));
2640 /* If a segment was explicitly specified, and the specified segment
2641 is not the default, use an opcode prefix to select it. If we
2642 never figured out what the default segment is, then default_seg
2643 will be zero at this point, and the specified segment prefix will
2645 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2647 if (!add_prefix (i
.seg
[0]->seg_prefix
))
2653 static const seg_entry
*
2656 const seg_entry
*default_seg
= 0;
2658 /* i.reg_operands MUST be the number of real register operands;
2659 implicit registers do not count. */
2660 if (i
.reg_operands
== 2)
2662 unsigned int source
, dest
;
2663 source
= ((i
.types
[0]
2664 & (Reg
| RegMMX
| RegXMM
2666 | Control
| Debug
| Test
))
2671 /* One of the register operands will be encoded in the i.tm.reg
2672 field, the other in the combined i.tm.mode and i.tm.regmem
2673 fields. If no form of this instruction supports a memory
2674 destination operand, then we assume the source operand may
2675 sometimes be a memory operand and so we need to store the
2676 destination in the i.rm.reg field. */
2677 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2679 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2680 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2681 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2683 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2688 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2689 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2690 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2692 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2697 { /* If it's not 2 reg operands... */
2700 unsigned int fake_zero_displacement
= 0;
2701 unsigned int op
= ((i
.types
[0] & AnyMem
)
2703 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2707 if (i
.base_reg
== 0)
2710 if (!i
.disp_operands
)
2711 fake_zero_displacement
= 1;
2712 if (i
.index_reg
== 0)
2714 /* Operand is just <disp> */
2715 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0)
2716 && (flag_code
!= CODE_64BIT
))
2718 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2719 i
.types
[op
] &= ~Disp
;
2720 i
.types
[op
] |= Disp16
;
2722 else if (flag_code
!= CODE_64BIT
2723 || (i
.prefix
[ADDR_PREFIX
] != 0))
2725 i
.rm
.regmem
= NO_BASE_REGISTER
;
2726 i
.types
[op
] &= ~Disp
;
2727 i
.types
[op
] |= Disp32
;
2731 /* 64bit mode overwrites the 32bit absolute
2732 addressing by RIP relative addressing and
2733 absolute addressing is encoded by one of the
2734 redundant SIB forms. */
2735 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2736 i
.sib
.base
= NO_BASE_REGISTER
;
2737 i
.sib
.index
= NO_INDEX_REGISTER
;
2738 i
.types
[op
] &= ~Disp
;
2739 i
.types
[op
] |= Disp32S
;
2742 else /* !i.base_reg && i.index_reg */
2744 i
.sib
.index
= i
.index_reg
->reg_num
;
2745 i
.sib
.base
= NO_BASE_REGISTER
;
2746 i
.sib
.scale
= i
.log2_scale_factor
;
2747 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2748 i
.types
[op
] &= ~Disp
;
2749 if (flag_code
!= CODE_64BIT
)
2750 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2752 i
.types
[op
] |= Disp32S
;
2753 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2757 /* RIP addressing for 64bit mode. */
2758 else if (i
.base_reg
->reg_type
== BaseIndex
)
2760 i
.rm
.regmem
= NO_BASE_REGISTER
;
2761 i
.types
[op
] &= ~Disp
;
2762 i
.types
[op
] |= Disp32S
;
2763 i
.flags
[op
] = Operand_PCrel
;
2765 else if (i
.base_reg
->reg_type
& Reg16
)
2767 switch (i
.base_reg
->reg_num
)
2770 if (i
.index_reg
== 0)
2772 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2773 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2777 if (i
.index_reg
== 0)
2780 if ((i
.types
[op
] & Disp
) == 0)
2782 /* fake (%bp) into 0(%bp) */
2783 i
.types
[op
] |= Disp8
;
2784 fake_zero_displacement
= 1;
2787 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2788 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2790 default: /* (%si) -> 4 or (%di) -> 5 */
2791 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2793 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2795 else /* i.base_reg and 32/64 bit mode */
2797 if (flag_code
== CODE_64BIT
2798 && (i
.types
[op
] & Disp
))
2800 if (i
.types
[op
] & Disp8
)
2801 i
.types
[op
] = Disp8
| Disp32S
;
2803 i
.types
[op
] = Disp32S
;
2805 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2806 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
2808 i
.sib
.base
= i
.base_reg
->reg_num
;
2809 /* x86-64 ignores REX prefix bit here to avoid decoder
2811 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2814 if (i
.disp_operands
== 0)
2816 fake_zero_displacement
= 1;
2817 i
.types
[op
] |= Disp8
;
2820 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2824 i
.sib
.scale
= i
.log2_scale_factor
;
2825 if (i
.index_reg
== 0)
2827 /* <disp>(%esp) becomes two byte modrm with no index
2828 register. We've already stored the code for esp
2829 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2830 Any base register besides %esp will not use the
2831 extra modrm byte. */
2832 i
.sib
.index
= NO_INDEX_REGISTER
;
2833 #if !SCALE1_WHEN_NO_INDEX
2834 /* Another case where we force the second modrm byte. */
2835 if (i
.log2_scale_factor
)
2836 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2841 i
.sib
.index
= i
.index_reg
->reg_num
;
2842 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2843 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2846 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2849 if (fake_zero_displacement
)
2851 /* Fakes a zero displacement assuming that i.types[op]
2852 holds the correct displacement size. */
2855 assert (i
.op
[op
].disps
== 0);
2856 exp
= &disp_expressions
[i
.disp_operands
++];
2857 i
.op
[op
].disps
= exp
;
2858 exp
->X_op
= O_constant
;
2859 exp
->X_add_number
= 0;
2860 exp
->X_add_symbol
= (symbolS
*) 0;
2861 exp
->X_op_symbol
= (symbolS
*) 0;
2865 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2866 (if any) based on i.tm.extension_opcode. Again, we must be
2867 careful to make sure that segment/control/debug/test/MMX
2868 registers are coded into the i.rm.reg field. */
2873 & (Reg
| RegMMX
| RegXMM
2875 | Control
| Debug
| Test
))
2878 & (Reg
| RegMMX
| RegXMM
2880 | Control
| Debug
| Test
))
2883 /* If there is an extension opcode to put here, the register
2884 number must be put into the regmem field. */
2885 if (i
.tm
.extension_opcode
!= None
)
2887 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2888 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2893 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2894 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2898 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2899 must set it to 3 to indicate this is a register operand
2900 in the regmem field. */
2901 if (!i
.mem_operands
)
2905 /* Fill in i.rm.reg field with extension opcode (if any). */
2906 if (i
.tm
.extension_opcode
!= None
)
2907 i
.rm
.reg
= i
.tm
.extension_opcode
;
2918 relax_substateT subtype
;
2923 if (flag_code
== CODE_16BIT
)
2927 if (i
.prefix
[DATA_PREFIX
] != 0)
2933 /* Pentium4 branch hints. */
2934 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
2935 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
2940 if (i
.prefix
[REX_PREFIX
] != 0)
2946 if (i
.prefixes
!= 0 && !intel_syntax
)
2947 as_warn (_("skipping prefixes on this instruction"));
2949 /* It's always a symbol; End frag & setup for relax.
2950 Make sure there is enough room in this frag for the largest
2951 instruction we may generate in md_convert_frag. This is 2
2952 bytes for the opcode and room for the prefix and largest
2954 frag_grow (prefix
+ 2 + 4);
2955 /* Prefix and 1 opcode byte go in fr_fix. */
2956 p
= frag_more (prefix
+ 1);
2957 if (i
.prefix
[DATA_PREFIX
] != 0)
2958 *p
++ = DATA_PREFIX_OPCODE
;
2959 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
2960 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
2961 *p
++ = i
.prefix
[SEG_PREFIX
];
2962 if (i
.prefix
[REX_PREFIX
] != 0)
2963 *p
++ = i
.prefix
[REX_PREFIX
];
2964 *p
= i
.tm
.base_opcode
;
2966 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
2967 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
2968 else if ((cpu_arch_flags
& Cpu386
) != 0)
2969 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
2971 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
2974 sym
= i
.op
[0].disps
->X_add_symbol
;
2975 off
= i
.op
[0].disps
->X_add_number
;
2977 if (i
.op
[0].disps
->X_op
!= O_constant
2978 && i
.op
[0].disps
->X_op
!= O_symbol
)
2980 /* Handle complex expressions. */
2981 sym
= make_expr_symbol (i
.op
[0].disps
);
2985 /* 1 possible extra opcode + 4 byte displacement go in var part.
2986 Pass reloc in fr_var. */
2987 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
2997 if (i
.tm
.opcode_modifier
& JumpByte
)
2999 /* This is a loop or jecxz type instruction. */
3001 if (i
.prefix
[ADDR_PREFIX
] != 0)
3003 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3006 /* Pentium4 branch hints. */
3007 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3008 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3010 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3019 if (flag_code
== CODE_16BIT
)
3022 if (i
.prefix
[DATA_PREFIX
] != 0)
3024 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3034 if (i
.prefix
[REX_PREFIX
] != 0)
3036 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3040 if (i
.prefixes
!= 0 && !intel_syntax
)
3041 as_warn (_("skipping prefixes on this instruction"));
3043 p
= frag_more (1 + size
);
3044 *p
++ = i
.tm
.base_opcode
;
3046 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3047 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3049 /* All jumps handled here are signed, but don't use a signed limit
3050 check for 32 and 16 bit jumps as we want to allow wrap around at
3051 4G and 64k respectively. */
3053 fixP
->fx_signed
= 1;
3057 output_interseg_jump ()
3065 if (flag_code
== CODE_16BIT
)
3069 if (i
.prefix
[DATA_PREFIX
] != 0)
3075 if (i
.prefix
[REX_PREFIX
] != 0)
3085 if (i
.prefixes
!= 0 && !intel_syntax
)
3086 as_warn (_("skipping prefixes on this instruction"));
3088 /* 1 opcode; 2 segment; offset */
3089 p
= frag_more (prefix
+ 1 + 2 + size
);
3091 if (i
.prefix
[DATA_PREFIX
] != 0)
3092 *p
++ = DATA_PREFIX_OPCODE
;
3094 if (i
.prefix
[REX_PREFIX
] != 0)
3095 *p
++ = i
.prefix
[REX_PREFIX
];
3097 *p
++ = i
.tm
.base_opcode
;
3098 if (i
.op
[1].imms
->X_op
== O_constant
)
3100 offsetT n
= i
.op
[1].imms
->X_add_number
;
3103 && !fits_in_unsigned_word (n
)
3104 && !fits_in_signed_word (n
))
3106 as_bad (_("16-bit jump out of range"));
3109 md_number_to_chars (p
, n
, size
);
3112 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3113 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3114 if (i
.op
[0].imms
->X_op
!= O_constant
)
3115 as_bad (_("can't handle non absolute segment in `%s'"),
3117 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3124 fragS
*insn_start_frag
;
3125 offsetT insn_start_off
;
3127 /* Tie dwarf2 debug info to the address at the start of the insn.
3128 We can't do this after the insn has been output as the current
3129 frag may have been closed off. eg. by frag_var. */
3130 dwarf2_emit_insn (0);
3132 insn_start_frag
= frag_now
;
3133 insn_start_off
= frag_now_fix ();
3136 if (i
.tm
.opcode_modifier
& Jump
)
3138 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3140 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3141 output_interseg_jump ();
3144 /* Output normal instructions here. */
3148 /* All opcodes on i386 have either 1 or 2 bytes. We may use third
3149 byte for the SSE instructions to specify a prefix they require. */
3150 if (i
.tm
.base_opcode
& 0xff0000)
3151 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
3153 /* The prefix bytes. */
3155 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3161 md_number_to_chars (p
, (valueT
) *q
, 1);
3165 /* Now the opcode; be careful about word order here! */
3166 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3168 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3173 /* Put out high byte first: can't use md_number_to_chars! */
3174 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3175 *p
= i
.tm
.base_opcode
& 0xff;
3178 /* Now the modrm byte and sib byte (if present). */
3179 if (i
.tm
.opcode_modifier
& Modrm
)
3182 md_number_to_chars (p
,
3183 (valueT
) (i
.rm
.regmem
<< 0
3187 /* If i.rm.regmem == ESP (4)
3188 && i.rm.mode != (Register mode)
3190 ==> need second modrm byte. */
3191 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3193 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3196 md_number_to_chars (p
,
3197 (valueT
) (i
.sib
.base
<< 0
3199 | i
.sib
.scale
<< 6),
3204 if (i
.disp_operands
)
3205 output_disp (insn_start_frag
, insn_start_off
);
3208 output_imm (insn_start_frag
, insn_start_off
);
3216 #endif /* DEBUG386 */
3220 output_disp (insn_start_frag
, insn_start_off
)
3221 fragS
*insn_start_frag
;
3222 offsetT insn_start_off
;
3227 for (n
= 0; n
< i
.operands
; n
++)
3229 if (i
.types
[n
] & Disp
)
3231 if (i
.op
[n
].disps
->X_op
== O_constant
)
3237 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
3240 if (i
.types
[n
] & Disp8
)
3242 if (i
.types
[n
] & Disp64
)
3245 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3247 p
= frag_more (size
);
3248 md_number_to_chars (p
, val
, size
);
3252 enum bfd_reloc_code_real reloc_type
;
3255 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3257 /* The PC relative address is computed relative
3258 to the instruction boundary, so in case immediate
3259 fields follows, we need to adjust the value. */
3260 if (pcrel
&& i
.imm_operands
)
3265 for (n1
= 0; n1
< i
.operands
; n1
++)
3266 if (i
.types
[n1
] & Imm
)
3268 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3271 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3273 if (i
.types
[n1
] & Imm64
)
3278 /* We should find the immediate. */
3279 if (n1
== i
.operands
)
3281 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3284 if (i
.types
[n
] & Disp32S
)
3287 if (i
.types
[n
] & (Disp16
| Disp64
))
3290 if (i
.types
[n
] & Disp64
)
3294 p
= frag_more (size
);
3295 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
3296 if (reloc_type
== BFD_RELOC_32
3298 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
3299 && (i
.op
[n
].disps
->X_op
== O_symbol
3300 || (i
.op
[n
].disps
->X_op
== O_add
3301 && ((symbol_get_value_expression
3302 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
3307 if (insn_start_frag
== frag_now
)
3308 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3313 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3314 for (fr
= insn_start_frag
->fr_next
;
3315 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3317 add
+= p
- frag_now
->fr_literal
;
3320 /* We don't support dynamic linking on x86-64 yet. */
3321 if (flag_code
== CODE_64BIT
)
3323 reloc_type
= BFD_RELOC_386_GOTPC
;
3324 i
.op
[n
].disps
->X_add_number
+= add
;
3326 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3327 i
.op
[n
].disps
, pcrel
, reloc_type
);
3334 output_imm (insn_start_frag
, insn_start_off
)
3335 fragS
*insn_start_frag
;
3336 offsetT insn_start_off
;
3341 for (n
= 0; n
< i
.operands
; n
++)
3343 if (i
.types
[n
] & Imm
)
3345 if (i
.op
[n
].imms
->X_op
== O_constant
)
3351 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3354 if (i
.types
[n
] & (Imm8
| Imm8S
))
3356 else if (i
.types
[n
] & Imm64
)
3359 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3361 p
= frag_more (size
);
3362 md_number_to_chars (p
, val
, size
);
3366 /* Not absolute_section.
3367 Need a 32-bit fixup (don't support 8bit
3368 non-absolute imms). Try to support other
3370 enum bfd_reloc_code_real reloc_type
;
3374 if ((i
.types
[n
] & (Imm32S
))
3375 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3377 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3380 if (i
.types
[n
] & (Imm8
| Imm8S
))
3382 if (i
.types
[n
] & Imm64
)
3386 p
= frag_more (size
);
3387 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3389 /* This is tough to explain. We end up with this one if we
3390 * have operands that look like
3391 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3392 * obtain the absolute address of the GOT, and it is strongly
3393 * preferable from a performance point of view to avoid using
3394 * a runtime relocation for this. The actual sequence of
3395 * instructions often look something like:
3400 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3402 * The call and pop essentially return the absolute address
3403 * of the label .L66 and store it in %ebx. The linker itself
3404 * will ultimately change the first operand of the addl so
3405 * that %ebx points to the GOT, but to keep things simple, the
3406 * .o file must have this operand set so that it generates not
3407 * the absolute address of .L66, but the absolute address of
3408 * itself. This allows the linker itself simply treat a GOTPC
3409 * relocation as asking for a pcrel offset to the GOT to be
3410 * added in, and the addend of the relocation is stored in the
3411 * operand field for the instruction itself.
3413 * Our job here is to fix the operand so that it would add
3414 * the correct offset so that %ebx would point to itself. The
3415 * thing that is tricky is that .-.L66 will point to the
3416 * beginning of the instruction, so we need to further modify
3417 * the operand so that it will point to itself. There are
3418 * other cases where you have something like:
3420 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3422 * and here no correction would be required. Internally in
3423 * the assembler we treat operands of this form as not being
3424 * pcrel since the '.' is explicitly mentioned, and I wonder
3425 * whether it would simplify matters to do it this way. Who
3426 * knows. In earlier versions of the PIC patches, the
3427 * pcrel_adjust field was used to store the correction, but
3428 * since the expression is not pcrel, I felt it would be
3429 * confusing to do it this way. */
3431 if (reloc_type
== BFD_RELOC_32
3433 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3434 && (i
.op
[n
].imms
->X_op
== O_symbol
3435 || (i
.op
[n
].imms
->X_op
== O_add
3436 && ((symbol_get_value_expression
3437 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3442 if (insn_start_frag
== frag_now
)
3443 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3448 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3449 for (fr
= insn_start_frag
->fr_next
;
3450 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3452 add
+= p
- frag_now
->fr_literal
;
3455 /* We don't support dynamic linking on x86-64 yet. */
3456 if (flag_code
== CODE_64BIT
)
3458 reloc_type
= BFD_RELOC_386_GOTPC
;
3459 i
.op
[n
].imms
->X_add_number
+= add
;
3461 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3462 i
.op
[n
].imms
, 0, reloc_type
);
3469 static char *lex_got
PARAMS ((enum bfd_reloc_code_real
*, int *));
3471 /* Parse operands of the form
3472 <symbol>@GOTOFF+<nnn>
3473 and similar .plt or .got references.
3475 If we find one, set up the correct relocation in RELOC and copy the
3476 input string, minus the `@GOTOFF' into a malloc'd buffer for
3477 parsing by the calling routine. Return this buffer, and if ADJUST
3478 is non-null set it to the length of the string we removed from the
3479 input line. Otherwise return NULL. */
3481 lex_got (reloc
, adjust
)
3482 enum bfd_reloc_code_real
*reloc
;
3485 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3486 static const struct {
3488 const enum bfd_reloc_code_real rel
[NUM_FLAG_CODE
];
3490 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
} },
3491 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, 0 } },
3492 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
} },
3493 { "TLSGD", { BFD_RELOC_386_TLS_GD
, 0, BFD_RELOC_X86_64_TLSGD
} },
3494 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
, 0, 0 } },
3495 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD
} },
3496 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
, 0, BFD_RELOC_X86_64_GOTTPOFF
} },
3497 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
, 0, BFD_RELOC_X86_64_TPOFF32
} },
3498 { "NTPOFF", { BFD_RELOC_386_TLS_LE
, 0, 0 } },
3499 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
, 0, BFD_RELOC_X86_64_DTPOFF32
} },
3500 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
, 0, 0 } },
3501 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
, 0, 0 } },
3502 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
} }
3507 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3508 if (is_end_of_line
[(unsigned char) *cp
])
3511 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3515 len
= strlen (gotrel
[j
].str
);
3516 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3518 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3521 char *tmpbuf
, *past_reloc
;
3523 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3527 if (GOT_symbol
== NULL
)
3528 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3530 /* Replace the relocation token with ' ', so that
3531 errors like foo@GOTOFF1 will be detected. */
3533 /* The length of the first part of our input line. */
3534 first
= cp
- input_line_pointer
;
3536 /* The second part goes from after the reloc token until
3537 (and including) an end_of_line char. Don't use strlen
3538 here as the end_of_line char may not be a NUL. */
3539 past_reloc
= cp
+ 1 + len
;
3540 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3542 second
= cp
- past_reloc
;
3544 /* Allocate and copy string. The trailing NUL shouldn't
3545 be necessary, but be safe. */
3546 tmpbuf
= xmalloc (first
+ second
+ 2);
3547 memcpy (tmpbuf
, input_line_pointer
, first
);
3548 tmpbuf
[first
] = ' ';
3549 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3550 tmpbuf
[first
+ second
+ 1] = '\0';
3554 as_bad (_("@%s reloc is not supported in %s bit mode"),
3555 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3560 /* Might be a symbol version string. Don't as_bad here. */
3564 /* x86_cons_fix_new is called via the expression parsing code when a
3565 reloc is needed. We use this hook to get the correct .got reloc. */
3566 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
3569 x86_cons_fix_new (frag
, off
, len
, exp
)
3575 enum bfd_reloc_code_real r
= reloc (len
, 0, 0, got_reloc
);
3576 got_reloc
= NO_RELOC
;
3577 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3581 x86_cons (exp
, size
)
3587 /* Handle @GOTOFF and the like in an expression. */
3589 char *gotfree_input_line
;
3592 save
= input_line_pointer
;
3593 gotfree_input_line
= lex_got (&got_reloc
, &adjust
);
3594 if (gotfree_input_line
)
3595 input_line_pointer
= gotfree_input_line
;
3599 if (gotfree_input_line
)
3601 /* expression () has merrily parsed up to the end of line,
3602 or a comma - in the wrong buffer. Transfer how far
3603 input_line_pointer has moved to the right buffer. */
3604 input_line_pointer
= (save
3605 + (input_line_pointer
- gotfree_input_line
)
3607 free (gotfree_input_line
);
3615 static int i386_immediate
PARAMS ((char *));
3618 i386_immediate (imm_start
)
3621 char *save_input_line_pointer
;
3623 char *gotfree_input_line
;
3628 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3630 as_bad (_("only 1 or 2 immediate operands are allowed"));
3634 exp
= &im_expressions
[i
.imm_operands
++];
3635 i
.op
[this_operand
].imms
= exp
;
3637 if (is_space_char (*imm_start
))
3640 save_input_line_pointer
= input_line_pointer
;
3641 input_line_pointer
= imm_start
;
3644 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3645 if (gotfree_input_line
)
3646 input_line_pointer
= gotfree_input_line
;
3649 exp_seg
= expression (exp
);
3652 if (*input_line_pointer
)
3653 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3655 input_line_pointer
= save_input_line_pointer
;
3657 if (gotfree_input_line
)
3658 free (gotfree_input_line
);
3661 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3663 /* Missing or bad expr becomes absolute 0. */
3664 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3666 exp
->X_op
= O_constant
;
3667 exp
->X_add_number
= 0;
3668 exp
->X_add_symbol
= (symbolS
*) 0;
3669 exp
->X_op_symbol
= (symbolS
*) 0;
3671 else if (exp
->X_op
== O_constant
)
3673 /* Size it properly later. */
3674 i
.types
[this_operand
] |= Imm64
;
3675 /* If BFD64, sign extend val. */
3676 if (!use_rela_relocations
)
3677 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3678 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3680 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3681 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
3682 && exp_seg
!= absolute_section
3683 && exp_seg
!= text_section
3684 && exp_seg
!= data_section
3685 && exp_seg
!= bss_section
3686 && exp_seg
!= undefined_section
3687 && !bfd_is_com_section (exp_seg
))
3689 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3695 /* This is an address. The size of the address will be
3696 determined later, depending on destination register,
3697 suffix, or the default for the section. */
3698 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3704 static char *i386_scale
PARAMS ((char *));
3711 char *save
= input_line_pointer
;
3713 input_line_pointer
= scale
;
3714 val
= get_absolute_expression ();
3720 i
.log2_scale_factor
= 0;
3723 i
.log2_scale_factor
= 1;
3726 i
.log2_scale_factor
= 2;
3729 i
.log2_scale_factor
= 3;
3732 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3734 input_line_pointer
= save
;
3737 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
3739 as_warn (_("scale factor of %d without an index register"),
3740 1 << i
.log2_scale_factor
);
3741 #if SCALE1_WHEN_NO_INDEX
3742 i
.log2_scale_factor
= 0;
3745 scale
= input_line_pointer
;
3746 input_line_pointer
= save
;
3750 static int i386_displacement
PARAMS ((char *, char *));
3753 i386_displacement (disp_start
, disp_end
)
3759 char *save_input_line_pointer
;
3761 char *gotfree_input_line
;
3763 int bigdisp
= Disp32
;
3765 if (flag_code
== CODE_64BIT
)
3767 if (i
.prefix
[ADDR_PREFIX
] == 0)
3770 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3772 i
.types
[this_operand
] |= bigdisp
;
3774 exp
= &disp_expressions
[i
.disp_operands
];
3775 i
.op
[this_operand
].disps
= exp
;
3777 save_input_line_pointer
= input_line_pointer
;
3778 input_line_pointer
= disp_start
;
3779 END_STRING_AND_SAVE (disp_end
);
3781 #ifndef GCC_ASM_O_HACK
3782 #define GCC_ASM_O_HACK 0
3785 END_STRING_AND_SAVE (disp_end
+ 1);
3786 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3787 && displacement_string_end
[-1] == '+')
3789 /* This hack is to avoid a warning when using the "o"
3790 constraint within gcc asm statements.
3793 #define _set_tssldt_desc(n,addr,limit,type) \
3794 __asm__ __volatile__ ( \
3796 "movw %w1,2+%0\n\t" \
3798 "movb %b1,4+%0\n\t" \
3799 "movb %4,5+%0\n\t" \
3800 "movb $0,6+%0\n\t" \
3801 "movb %h1,7+%0\n\t" \
3803 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3805 This works great except that the output assembler ends
3806 up looking a bit weird if it turns out that there is
3807 no offset. You end up producing code that looks like:
3820 So here we provide the missing zero. */
3822 *displacement_string_end
= '0';
3826 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3827 if (gotfree_input_line
)
3828 input_line_pointer
= gotfree_input_line
;
3831 exp_seg
= expression (exp
);
3834 if (*input_line_pointer
)
3835 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3837 RESTORE_END_STRING (disp_end
+ 1);
3839 RESTORE_END_STRING (disp_end
);
3840 input_line_pointer
= save_input_line_pointer
;
3842 if (gotfree_input_line
)
3843 free (gotfree_input_line
);
3846 /* We do this to make sure that the section symbol is in
3847 the symbol table. We will ultimately change the relocation
3848 to be relative to the beginning of the section. */
3849 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3850 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3852 if (exp
->X_op
!= O_symbol
)
3854 as_bad (_("bad expression used with @%s"),
3855 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
3861 if (S_IS_LOCAL (exp
->X_add_symbol
)
3862 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3863 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3864 exp
->X_op
= O_subtract
;
3865 exp
->X_op_symbol
= GOT_symbol
;
3866 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3867 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
3869 i
.reloc
[this_operand
] = BFD_RELOC_32
;
3872 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3874 /* Missing or bad expr becomes absolute 0. */
3875 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3877 exp
->X_op
= O_constant
;
3878 exp
->X_add_number
= 0;
3879 exp
->X_add_symbol
= (symbolS
*) 0;
3880 exp
->X_op_symbol
= (symbolS
*) 0;
3883 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3884 if (exp
->X_op
!= O_constant
3885 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3886 && exp_seg
!= absolute_section
3887 && exp_seg
!= text_section
3888 && exp_seg
!= data_section
3889 && exp_seg
!= bss_section
3890 && exp_seg
!= undefined_section
3891 && !bfd_is_com_section (exp_seg
))
3893 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3897 else if (flag_code
== CODE_64BIT
)
3898 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3902 static int i386_index_check
PARAMS ((const char *));
3904 /* Make sure the memory operand we've been dealt is valid.
3905 Return 1 on success, 0 on a failure. */
3908 i386_index_check (operand_string
)
3909 const char *operand_string
;
3912 #if INFER_ADDR_PREFIX
3918 if (flag_code
== CODE_64BIT
)
3920 if (i
.prefix
[ADDR_PREFIX
] == 0)
3924 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3925 && (i
.base_reg
->reg_type
!= BaseIndex
3928 && ((i
.index_reg
->reg_type
& (Reg64
| BaseIndex
))
3929 != (Reg64
| BaseIndex
))))
3936 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3938 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
3939 != (Reg32
| BaseIndex
))))
3945 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3949 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
3950 != (Reg16
| BaseIndex
)))
3952 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
3953 != (Reg16
| BaseIndex
))
3955 && i
.base_reg
->reg_num
< 6
3956 && i
.index_reg
->reg_num
>= 6
3957 && i
.log2_scale_factor
== 0))))
3964 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3966 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
3967 != (Reg32
| BaseIndex
))))
3973 #if INFER_ADDR_PREFIX
3974 if (flag_code
!= CODE_64BIT
3975 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3977 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3979 /* Change the size of any displacement too. At most one of
3980 Disp16 or Disp32 is set.
3981 FIXME. There doesn't seem to be any real need for separate
3982 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3983 Removing them would probably clean up the code quite a lot. */
3984 if (i
.types
[this_operand
] & (Disp16
| Disp32
))
3985 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
3990 as_bad (_("`%s' is not a valid base/index expression"),
3994 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3996 flag_code_names
[flag_code
]);
4002 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4006 i386_operand (operand_string
)
4007 char *operand_string
;
4011 char *op_string
= operand_string
;
4013 if (is_space_char (*op_string
))
4016 /* We check for an absolute prefix (differentiating,
4017 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4018 if (*op_string
== ABSOLUTE_PREFIX
)
4021 if (is_space_char (*op_string
))
4023 i
.types
[this_operand
] |= JumpAbsolute
;
4026 /* Check if operand is a register. */
4027 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4028 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
4030 /* Check for a segment override by searching for ':' after a
4031 segment register. */
4033 if (is_space_char (*op_string
))
4035 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
4040 i
.seg
[i
.mem_operands
] = &es
;
4043 i
.seg
[i
.mem_operands
] = &cs
;
4046 i
.seg
[i
.mem_operands
] = &ss
;
4049 i
.seg
[i
.mem_operands
] = &ds
;
4052 i
.seg
[i
.mem_operands
] = &fs
;
4055 i
.seg
[i
.mem_operands
] = &gs
;
4059 /* Skip the ':' and whitespace. */
4061 if (is_space_char (*op_string
))
4064 if (!is_digit_char (*op_string
)
4065 && !is_identifier_char (*op_string
)
4066 && *op_string
!= '('
4067 && *op_string
!= ABSOLUTE_PREFIX
)
4069 as_bad (_("bad memory operand `%s'"), op_string
);
4072 /* Handle case of %es:*foo. */
4073 if (*op_string
== ABSOLUTE_PREFIX
)
4076 if (is_space_char (*op_string
))
4078 i
.types
[this_operand
] |= JumpAbsolute
;
4080 goto do_memory_reference
;
4084 as_bad (_("junk `%s' after register"), op_string
);
4087 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
4088 i
.op
[this_operand
].regs
= r
;
4091 else if (*op_string
== REGISTER_PREFIX
)
4093 as_bad (_("bad register name `%s'"), op_string
);
4096 else if (*op_string
== IMMEDIATE_PREFIX
)
4099 if (i
.types
[this_operand
] & JumpAbsolute
)
4101 as_bad (_("immediate operand illegal with absolute jump"));
4104 if (!i386_immediate (op_string
))
4107 else if (is_digit_char (*op_string
)
4108 || is_identifier_char (*op_string
)
4109 || *op_string
== '(')
4111 /* This is a memory reference of some sort. */
4114 /* Start and end of displacement string expression (if found). */
4115 char *displacement_string_start
;
4116 char *displacement_string_end
;
4118 do_memory_reference
:
4119 if ((i
.mem_operands
== 1
4120 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4121 || i
.mem_operands
== 2)
4123 as_bad (_("too many memory references for `%s'"),
4124 current_templates
->start
->name
);
4128 /* Check for base index form. We detect the base index form by
4129 looking for an ')' at the end of the operand, searching
4130 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4132 base_string
= op_string
+ strlen (op_string
);
4135 if (is_space_char (*base_string
))
4138 /* If we only have a displacement, set-up for it to be parsed later. */
4139 displacement_string_start
= op_string
;
4140 displacement_string_end
= base_string
+ 1;
4142 if (*base_string
== ')')
4145 unsigned int parens_balanced
= 1;
4146 /* We've already checked that the number of left & right ()'s are
4147 equal, so this loop will not be infinite. */
4151 if (*base_string
== ')')
4153 if (*base_string
== '(')
4156 while (parens_balanced
);
4158 temp_string
= base_string
;
4160 /* Skip past '(' and whitespace. */
4162 if (is_space_char (*base_string
))
4165 if (*base_string
== ','
4166 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4167 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
4169 displacement_string_end
= temp_string
;
4171 i
.types
[this_operand
] |= BaseIndex
;
4175 base_string
= end_op
;
4176 if (is_space_char (*base_string
))
4180 /* There may be an index reg or scale factor here. */
4181 if (*base_string
== ',')
4184 if (is_space_char (*base_string
))
4187 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4188 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
4190 base_string
= end_op
;
4191 if (is_space_char (*base_string
))
4193 if (*base_string
== ',')
4196 if (is_space_char (*base_string
))
4199 else if (*base_string
!= ')')
4201 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4206 else if (*base_string
== REGISTER_PREFIX
)
4208 as_bad (_("bad register name `%s'"), base_string
);
4212 /* Check for scale factor. */
4213 if (*base_string
!= ')')
4215 char *end_scale
= i386_scale (base_string
);
4220 base_string
= end_scale
;
4221 if (is_space_char (*base_string
))
4223 if (*base_string
!= ')')
4225 as_bad (_("expecting `)' after scale factor in `%s'"),
4230 else if (!i
.index_reg
)
4232 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4237 else if (*base_string
!= ')')
4239 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4244 else if (*base_string
== REGISTER_PREFIX
)
4246 as_bad (_("bad register name `%s'"), base_string
);
4251 /* If there's an expression beginning the operand, parse it,
4252 assuming displacement_string_start and
4253 displacement_string_end are meaningful. */
4254 if (displacement_string_start
!= displacement_string_end
)
4256 if (!i386_displacement (displacement_string_start
,
4257 displacement_string_end
))
4261 /* Special case for (%dx) while doing input/output op. */
4263 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
4265 && i
.log2_scale_factor
== 0
4266 && i
.seg
[i
.mem_operands
] == 0
4267 && (i
.types
[this_operand
] & Disp
) == 0)
4269 i
.types
[this_operand
] = InOutPortReg
;
4273 if (i386_index_check (operand_string
) == 0)
4279 /* It's not a memory operand; argh! */
4280 as_bad (_("invalid char %s beginning operand %d `%s'"),
4281 output_invalid (*op_string
),
4286 return 1; /* Normal return. */
4289 /* md_estimate_size_before_relax()
4291 Called just before relax() for rs_machine_dependent frags. The x86
4292 assembler uses these frags to handle variable size jump
4295 Any symbol that is now undefined will not become defined.
4296 Return the correct fr_subtype in the frag.
4297 Return the initial "guess for variable size of frag" to caller.
4298 The guess is actually the growth beyond the fixed part. Whatever
4299 we do to grow the fixed or variable part contributes to our
4303 md_estimate_size_before_relax (fragP
, segment
)
4307 /* We've already got fragP->fr_subtype right; all we have to do is
4308 check for un-relaxable symbols. On an ELF system, we can't relax
4309 an externally visible symbol, because it may be overridden by a
4311 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4312 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4313 || (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4314 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
4315 || S_IS_WEAK (fragP
->fr_symbol
)))
4319 /* Symbol is undefined in this segment, or we need to keep a
4320 reloc so that weak symbols can be overridden. */
4321 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
4322 enum bfd_reloc_code_real reloc_type
;
4323 unsigned char *opcode
;
4326 if (fragP
->fr_var
!= NO_RELOC
)
4327 reloc_type
= fragP
->fr_var
;
4329 reloc_type
= BFD_RELOC_16_PCREL
;
4331 reloc_type
= BFD_RELOC_32_PCREL
;
4333 old_fr_fix
= fragP
->fr_fix
;
4334 opcode
= (unsigned char *) fragP
->fr_opcode
;
4336 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4339 /* Make jmp (0xeb) a (d)word displacement jump. */
4341 fragP
->fr_fix
+= size
;
4342 fix_new (fragP
, old_fr_fix
, size
,
4344 fragP
->fr_offset
, 1,
4350 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
4352 /* Negate the condition, and branch past an
4353 unconditional jump. */
4356 /* Insert an unconditional jump. */
4358 /* We added two extra opcode bytes, and have a two byte
4360 fragP
->fr_fix
+= 2 + 2;
4361 fix_new (fragP
, old_fr_fix
+ 2, 2,
4363 fragP
->fr_offset
, 1,
4370 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
4375 fixP
= fix_new (fragP
, old_fr_fix
, 1,
4377 fragP
->fr_offset
, 1,
4379 fixP
->fx_signed
= 1;
4383 /* This changes the byte-displacement jump 0x7N
4384 to the (d)word-displacement jump 0x0f,0x8N. */
4385 opcode
[1] = opcode
[0] + 0x10;
4386 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4387 /* We've added an opcode byte. */
4388 fragP
->fr_fix
+= 1 + size
;
4389 fix_new (fragP
, old_fr_fix
+ 1, size
,
4391 fragP
->fr_offset
, 1,
4396 BAD_CASE (fragP
->fr_subtype
);
4400 return fragP
->fr_fix
- old_fr_fix
;
4403 /* Guess size depending on current relax state. Initially the relax
4404 state will correspond to a short jump and we return 1, because
4405 the variable part of the frag (the branch offset) is one byte
4406 long. However, we can relax a section more than once and in that
4407 case we must either set fr_subtype back to the unrelaxed state,
4408 or return the value for the appropriate branch. */
4409 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4412 /* Called after relax() is finished.
4414 In: Address of frag.
4415 fr_type == rs_machine_dependent.
4416 fr_subtype is what the address relaxed to.
4418 Out: Any fixSs and constants are set up.
4419 Caller will turn frag into a ".space 0". */
4422 md_convert_frag (abfd
, sec
, fragP
)
4423 bfd
*abfd ATTRIBUTE_UNUSED
;
4424 segT sec ATTRIBUTE_UNUSED
;
4427 unsigned char *opcode
;
4428 unsigned char *where_to_put_displacement
= NULL
;
4429 offsetT target_address
;
4430 offsetT opcode_address
;
4431 unsigned int extension
= 0;
4432 offsetT displacement_from_opcode_start
;
4434 opcode
= (unsigned char *) fragP
->fr_opcode
;
4436 /* Address we want to reach in file space. */
4437 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4439 /* Address opcode resides at in file space. */
4440 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4442 /* Displacement from opcode start to fill into instruction. */
4443 displacement_from_opcode_start
= target_address
- opcode_address
;
4445 if ((fragP
->fr_subtype
& BIG
) == 0)
4447 /* Don't have to change opcode. */
4448 extension
= 1; /* 1 opcode + 1 displacement */
4449 where_to_put_displacement
= &opcode
[1];
4453 if (no_cond_jump_promotion
4454 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4455 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4457 switch (fragP
->fr_subtype
)
4459 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4460 extension
= 4; /* 1 opcode + 4 displacement */
4462 where_to_put_displacement
= &opcode
[1];
4465 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4466 extension
= 2; /* 1 opcode + 2 displacement */
4468 where_to_put_displacement
= &opcode
[1];
4471 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4472 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4473 extension
= 5; /* 2 opcode + 4 displacement */
4474 opcode
[1] = opcode
[0] + 0x10;
4475 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4476 where_to_put_displacement
= &opcode
[2];
4479 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4480 extension
= 3; /* 2 opcode + 2 displacement */
4481 opcode
[1] = opcode
[0] + 0x10;
4482 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4483 where_to_put_displacement
= &opcode
[2];
4486 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4491 where_to_put_displacement
= &opcode
[3];
4495 BAD_CASE (fragP
->fr_subtype
);
4500 /* Now put displacement after opcode. */
4501 md_number_to_chars ((char *) where_to_put_displacement
,
4502 (valueT
) (displacement_from_opcode_start
- extension
),
4503 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4504 fragP
->fr_fix
+= extension
;
4507 /* Size of byte displacement jmp. */
4508 int md_short_jump_size
= 2;
4510 /* Size of dword displacement jmp. */
4511 int md_long_jump_size
= 5;
4513 /* Size of relocation record. */
4514 const int md_reloc_size
= 8;
4517 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4519 addressT from_addr
, to_addr
;
4520 fragS
*frag ATTRIBUTE_UNUSED
;
4521 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4525 offset
= to_addr
- (from_addr
+ 2);
4526 /* Opcode for byte-disp jump. */
4527 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4528 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4532 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4534 addressT from_addr
, to_addr
;
4535 fragS
*frag ATTRIBUTE_UNUSED
;
4536 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4540 offset
= to_addr
- (from_addr
+ 5);
4541 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4542 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4545 /* Apply a fixup (fixS) to segment data, once it has been determined
4546 by our caller that we have all the info we need to fix it up.
4548 On the 386, immediates, displacements, and data pointers are all in
4549 the same (little-endian) format, so we don't need to care about which
4553 md_apply_fix3 (fixP
, valP
, seg
)
4554 /* The fix we're to put in. */
4556 /* Pointer to the value of the bits. */
4558 /* Segment fix is from. */
4559 segT seg ATTRIBUTE_UNUSED
;
4561 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4562 valueT value
= *valP
;
4564 #if !defined (TE_Mach)
4567 switch (fixP
->fx_r_type
)
4573 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4576 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4579 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4584 if (fixP
->fx_addsy
!= NULL
4585 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4586 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4587 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4588 && !use_rela_relocations
)
4590 /* This is a hack. There should be a better way to handle this.
4591 This covers for the fact that bfd_install_relocation will
4592 subtract the current location (for partial_inplace, PC relative
4593 relocations); see more below. */
4595 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4597 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4600 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4602 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4603 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4605 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4608 || (symbol_section_p (fixP
->fx_addsy
)
4609 && sym_seg
!= absolute_section
))
4610 && !generic_force_reloc (fixP
))
4612 /* Yes, we add the values in twice. This is because
4613 bfd_install_relocation subtracts them out again. I think
4614 bfd_install_relocation is broken, but I don't dare change
4616 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4620 #if defined (OBJ_COFF) && defined (TE_PE)
4621 /* For some reason, the PE format does not store a section
4622 address offset for a PC relative symbol. */
4623 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4624 value
+= md_pcrel_from (fixP
);
4628 /* Fix a few things - the dynamic linker expects certain values here,
4629 and we must not dissappoint it. */
4630 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4631 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4633 switch (fixP
->fx_r_type
)
4635 case BFD_RELOC_386_PLT32
:
4636 case BFD_RELOC_X86_64_PLT32
:
4637 /* Make the jump instruction point to the address of the operand. At
4638 runtime we merely add the offset to the actual PLT entry. */
4642 case BFD_RELOC_386_TLS_GD
:
4643 case BFD_RELOC_386_TLS_LDM
:
4644 case BFD_RELOC_386_TLS_IE_32
:
4645 case BFD_RELOC_386_TLS_IE
:
4646 case BFD_RELOC_386_TLS_GOTIE
:
4647 case BFD_RELOC_X86_64_TLSGD
:
4648 case BFD_RELOC_X86_64_TLSLD
:
4649 case BFD_RELOC_X86_64_GOTTPOFF
:
4650 value
= 0; /* Fully resolved at runtime. No addend. */
4652 case BFD_RELOC_386_TLS_LE
:
4653 case BFD_RELOC_386_TLS_LDO_32
:
4654 case BFD_RELOC_386_TLS_LE_32
:
4655 case BFD_RELOC_X86_64_DTPOFF32
:
4656 case BFD_RELOC_X86_64_TPOFF32
:
4657 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
4660 case BFD_RELOC_386_GOT32
:
4661 case BFD_RELOC_X86_64_GOT32
:
4662 value
= 0; /* Fully resolved at runtime. No addend. */
4665 case BFD_RELOC_VTABLE_INHERIT
:
4666 case BFD_RELOC_VTABLE_ENTRY
:
4673 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4675 #endif /* !defined (TE_Mach) */
4677 /* Are we finished with this relocation now? */
4678 if (fixP
->fx_addsy
== NULL
)
4680 else if (use_rela_relocations
)
4682 fixP
->fx_no_overflow
= 1;
4683 /* Remember value for tc_gen_reloc. */
4684 fixP
->fx_addnumber
= value
;
4688 md_number_to_chars (p
, value
, fixP
->fx_size
);
4691 #define MAX_LITTLENUMS 6
4693 /* Turn the string pointed to by litP into a floating point constant
4694 of type TYPE, and emit the appropriate bytes. The number of
4695 LITTLENUMS emitted is stored in *SIZEP. An error message is
4696 returned, or NULL on OK. */
4699 md_atof (type
, litP
, sizeP
)
4705 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4706 LITTLENUM_TYPE
*wordP
;
4728 return _("Bad call to md_atof ()");
4730 t
= atof_ieee (input_line_pointer
, type
, words
);
4732 input_line_pointer
= t
;
4734 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4735 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4736 the bigendian 386. */
4737 for (wordP
= words
+ prec
- 1; prec
--;)
4739 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4740 litP
+= sizeof (LITTLENUM_TYPE
);
4745 char output_invalid_buf
[8];
4752 sprintf (output_invalid_buf
, "'%c'", c
);
4754 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4755 return output_invalid_buf
;
4758 /* REG_STRING starts *before* REGISTER_PREFIX. */
4760 static const reg_entry
*
4761 parse_register (reg_string
, end_op
)
4765 char *s
= reg_string
;
4767 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4770 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4771 if (*s
== REGISTER_PREFIX
)
4774 if (is_space_char (*s
))
4778 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4780 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4781 return (const reg_entry
*) NULL
;
4785 /* For naked regs, make sure that we are not dealing with an identifier.
4786 This prevents confusing an identifier like `eax_var' with register
4788 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4789 return (const reg_entry
*) NULL
;
4793 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4795 /* Handle floating point regs, allowing spaces in the (i) part. */
4796 if (r
== i386_regtab
/* %st is first entry of table */)
4798 if (is_space_char (*s
))
4803 if (is_space_char (*s
))
4805 if (*s
>= '0' && *s
<= '7')
4807 r
= &i386_float_regtab
[*s
- '0'];
4809 if (is_space_char (*s
))
4817 /* We have "%st(" then garbage. */
4818 return (const reg_entry
*) NULL
;
4823 && (r
->reg_flags
& (RegRex64
| RegRex
)) != 0
4824 && flag_code
!= CODE_64BIT
)
4826 return (const reg_entry
*) NULL
;
4832 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4833 const char *md_shortopts
= "kVQ:sqn";
4835 const char *md_shortopts
= "qn";
4838 struct option md_longopts
[] = {
4839 #define OPTION_32 (OPTION_MD_BASE + 0)
4840 {"32", no_argument
, NULL
, OPTION_32
},
4841 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4842 #define OPTION_64 (OPTION_MD_BASE + 1)
4843 {"64", no_argument
, NULL
, OPTION_64
},
4845 {NULL
, no_argument
, NULL
, 0}
4847 size_t md_longopts_size
= sizeof (md_longopts
);
4850 md_parse_option (c
, arg
)
4852 char *arg ATTRIBUTE_UNUSED
;
4857 optimize_align_code
= 0;
4864 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4865 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4866 should be emitted or not. FIXME: Not implemented. */
4870 /* -V: SVR4 argument to print version ID. */
4872 print_version_id ();
4875 /* -k: Ignore for FreeBSD compatibility. */
4880 /* -s: On i386 Solaris, this tells the native assembler to use
4881 .stab instead of .stab.excl. We always use .stab anyhow. */
4886 const char **list
, **l
;
4888 list
= bfd_target_list ();
4889 for (l
= list
; *l
!= NULL
; l
++)
4890 if (strcmp (*l
, "elf64-x86-64") == 0)
4892 default_arch
= "x86_64";
4896 as_fatal (_("No compiled in support for x86_64"));
4903 default_arch
= "i386";
4913 md_show_usage (stream
)
4916 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4917 fprintf (stream
, _("\
4919 -V print assembler version number\n\
4921 -n Do not optimize code alignment\n\
4922 -q quieten some warnings\n\
4925 fprintf (stream
, _("\
4926 -n Do not optimize code alignment\n\
4927 -q quieten some warnings\n"));
4931 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4932 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4934 /* Pick the target format to use. */
4937 i386_target_format ()
4939 if (!strcmp (default_arch
, "x86_64"))
4940 set_code_flag (CODE_64BIT
);
4941 else if (!strcmp (default_arch
, "i386"))
4942 set_code_flag (CODE_32BIT
);
4944 as_fatal (_("Unknown architecture"));
4945 switch (OUTPUT_FLAVOR
)
4947 #ifdef OBJ_MAYBE_AOUT
4948 case bfd_target_aout_flavour
:
4949 return AOUT_TARGET_FORMAT
;
4951 #ifdef OBJ_MAYBE_COFF
4952 case bfd_target_coff_flavour
:
4955 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4956 case bfd_target_elf_flavour
:
4958 if (flag_code
== CODE_64BIT
)
4959 use_rela_relocations
= 1;
4960 return flag_code
== CODE_64BIT
? "elf64-x86-64" : ELF_TARGET_FORMAT
;
4969 #endif /* OBJ_MAYBE_ more than one */
4971 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4972 void i386_elf_emit_arch_note ()
4974 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4975 && cpu_arch_name
!= NULL
)
4978 asection
*seg
= now_seg
;
4979 subsegT subseg
= now_subseg
;
4980 Elf_Internal_Note i_note
;
4981 Elf_External_Note e_note
;
4982 asection
*note_secp
;
4985 /* Create the .note section. */
4986 note_secp
= subseg_new (".note", 0);
4987 bfd_set_section_flags (stdoutput
,
4989 SEC_HAS_CONTENTS
| SEC_READONLY
);
4991 /* Process the arch string. */
4992 len
= strlen (cpu_arch_name
);
4994 i_note
.namesz
= len
+ 1;
4996 i_note
.type
= NT_ARCH
;
4997 p
= frag_more (sizeof (e_note
.namesz
));
4998 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
4999 p
= frag_more (sizeof (e_note
.descsz
));
5000 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
5001 p
= frag_more (sizeof (e_note
.type
));
5002 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
5003 p
= frag_more (len
+ 1);
5004 strcpy (p
, cpu_arch_name
);
5006 frag_align (2, 0, 0);
5008 subseg_set (seg
, subseg
);
5014 md_undefined_symbol (name
)
5017 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
5018 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
5019 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
5020 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
5024 if (symbol_find (name
))
5025 as_bad (_("GOT already in symbol table"));
5026 GOT_symbol
= symbol_new (name
, undefined_section
,
5027 (valueT
) 0, &zero_address_frag
);
5034 /* Round up a section size to the appropriate boundary. */
5037 md_section_align (segment
, size
)
5038 segT segment ATTRIBUTE_UNUSED
;
5041 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5042 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
5044 /* For a.out, force the section size to be aligned. If we don't do
5045 this, BFD will align it for us, but it will not write out the
5046 final bytes of the section. This may be a bug in BFD, but it is
5047 easier to fix it here since that is how the other a.out targets
5051 align
= bfd_get_section_alignment (stdoutput
, segment
);
5052 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
5059 /* On the i386, PC-relative offsets are relative to the start of the
5060 next instruction. That is, the address of the offset, plus its
5061 size, since the offset is always the last part of the insn. */
5064 md_pcrel_from (fixP
)
5067 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5074 int ignore ATTRIBUTE_UNUSED
;
5078 temp
= get_absolute_expression ();
5079 subseg_set (bss_section
, (subsegT
) temp
);
5080 demand_empty_rest_of_line ();
5086 i386_validate_fix (fixp
)
5089 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
5091 /* GOTOFF relocation are nonsense in 64bit mode. */
5092 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
5094 if (flag_code
!= CODE_64BIT
)
5096 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
5100 if (flag_code
== CODE_64BIT
)
5102 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
5109 tc_gen_reloc (section
, fixp
)
5110 asection
*section ATTRIBUTE_UNUSED
;
5114 bfd_reloc_code_real_type code
;
5116 switch (fixp
->fx_r_type
)
5118 case BFD_RELOC_X86_64_PLT32
:
5119 case BFD_RELOC_X86_64_GOT32
:
5120 case BFD_RELOC_X86_64_GOTPCREL
:
5121 case BFD_RELOC_386_PLT32
:
5122 case BFD_RELOC_386_GOT32
:
5123 case BFD_RELOC_386_GOTOFF
:
5124 case BFD_RELOC_386_GOTPC
:
5125 case BFD_RELOC_386_TLS_GD
:
5126 case BFD_RELOC_386_TLS_LDM
:
5127 case BFD_RELOC_386_TLS_LDO_32
:
5128 case BFD_RELOC_386_TLS_IE_32
:
5129 case BFD_RELOC_386_TLS_IE
:
5130 case BFD_RELOC_386_TLS_GOTIE
:
5131 case BFD_RELOC_386_TLS_LE_32
:
5132 case BFD_RELOC_386_TLS_LE
:
5133 case BFD_RELOC_X86_64_32S
:
5134 case BFD_RELOC_X86_64_TLSGD
:
5135 case BFD_RELOC_X86_64_TLSLD
:
5136 case BFD_RELOC_X86_64_DTPOFF32
:
5137 case BFD_RELOC_X86_64_GOTTPOFF
:
5138 case BFD_RELOC_X86_64_TPOFF32
:
5140 case BFD_RELOC_VTABLE_ENTRY
:
5141 case BFD_RELOC_VTABLE_INHERIT
:
5142 code
= fixp
->fx_r_type
;
5147 switch (fixp
->fx_size
)
5150 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5151 _("can not do %d byte pc-relative relocation"),
5153 code
= BFD_RELOC_32_PCREL
;
5155 case 1: code
= BFD_RELOC_8_PCREL
; break;
5156 case 2: code
= BFD_RELOC_16_PCREL
; break;
5157 case 4: code
= BFD_RELOC_32_PCREL
; break;
5162 switch (fixp
->fx_size
)
5165 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5166 _("can not do %d byte relocation"),
5168 code
= BFD_RELOC_32
;
5170 case 1: code
= BFD_RELOC_8
; break;
5171 case 2: code
= BFD_RELOC_16
; break;
5172 case 4: code
= BFD_RELOC_32
; break;
5174 case 8: code
= BFD_RELOC_64
; break;
5181 if (code
== BFD_RELOC_32
5183 && fixp
->fx_addsy
== GOT_symbol
)
5185 /* We don't support GOTPC on 64bit targets. */
5186 if (flag_code
== CODE_64BIT
)
5188 code
= BFD_RELOC_386_GOTPC
;
5191 rel
= (arelent
*) xmalloc (sizeof (arelent
));
5192 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5193 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5195 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5196 if (!use_rela_relocations
)
5198 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5199 vtable entry to be used in the relocation's section offset. */
5200 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5201 rel
->address
= fixp
->fx_offset
;
5205 /* Use the rela in 64bit mode. */
5208 if (!fixp
->fx_pcrel
)
5209 rel
->addend
= fixp
->fx_offset
;
5213 case BFD_RELOC_X86_64_PLT32
:
5214 case BFD_RELOC_X86_64_GOT32
:
5215 case BFD_RELOC_X86_64_GOTPCREL
:
5216 case BFD_RELOC_X86_64_TLSGD
:
5217 case BFD_RELOC_X86_64_TLSLD
:
5218 case BFD_RELOC_X86_64_GOTTPOFF
:
5219 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
5222 rel
->addend
= (section
->vma
5224 + fixp
->fx_addnumber
5225 + md_pcrel_from (fixp
));
5230 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
5231 if (rel
->howto
== NULL
)
5233 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5234 _("cannot represent relocation type %s"),
5235 bfd_get_reloc_code_name (code
));
5236 /* Set howto to a garbage value so that we can keep going. */
5237 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
5238 assert (rel
->howto
!= NULL
);
5245 /* Parse operands using Intel syntax. This implements a recursive descent
5246 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5249 FIXME: We do not recognize the full operand grammar defined in the MASM
5250 documentation. In particular, all the structure/union and
5251 high-level macro operands are missing.
5253 Uppercase words are terminals, lower case words are non-terminals.
5254 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5255 bars '|' denote choices. Most grammar productions are implemented in
5256 functions called 'intel_<production>'.
5258 Initial production is 'expr'.
5264 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5266 constant digits [[ radixOverride ]]
5268 dataType BYTE | WORD | DWORD | QWORD | XWORD
5301 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5302 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5304 hexdigit a | b | c | d | e | f
5305 | A | B | C | D | E | F
5315 register specialRegister
5319 segmentRegister CS | DS | ES | FS | GS | SS
5321 specialRegister CR0 | CR2 | CR3
5322 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5323 | TR3 | TR4 | TR5 | TR6 | TR7
5325 We simplify the grammar in obvious places (e.g., register parsing is
5326 done by calling parse_register) and eliminate immediate left recursion
5327 to implement a recursive-descent parser.
5367 /* Parsing structure for the intel syntax parser. Used to implement the
5368 semantic actions for the operand grammar. */
5369 struct intel_parser_s
5371 char *op_string
; /* The string being parsed. */
5372 int got_a_float
; /* Whether the operand is a float. */
5373 int op_modifier
; /* Operand modifier. */
5374 int is_mem
; /* 1 if operand is memory reference. */
5375 const reg_entry
*reg
; /* Last register reference found. */
5376 char *disp
; /* Displacement string being built. */
5379 static struct intel_parser_s intel_parser
;
5381 /* Token structure for parsing intel syntax. */
5384 int code
; /* Token code. */
5385 const reg_entry
*reg
; /* Register entry for register tokens. */
5386 char *str
; /* String representation. */
5389 static struct intel_token cur_token
, prev_token
;
5391 /* Token codes for the intel parser. Since T_SHORT is already used
5392 by COFF, undefine it first to prevent a warning. */
5407 /* Prototypes for intel parser functions. */
5408 static int intel_match_token
PARAMS ((int code
));
5409 static void intel_get_token
PARAMS ((void));
5410 static void intel_putback_token
PARAMS ((void));
5411 static int intel_expr
PARAMS ((void));
5412 static int intel_e05
PARAMS ((void));
5413 static int intel_e05_1
PARAMS ((void));
5414 static int intel_e06
PARAMS ((void));
5415 static int intel_e06_1
PARAMS ((void));
5416 static int intel_e09
PARAMS ((void));
5417 static int intel_e09_1
PARAMS ((void));
5418 static int intel_e10
PARAMS ((void));
5419 static int intel_e10_1
PARAMS ((void));
5420 static int intel_e11
PARAMS ((void));
5423 i386_intel_operand (operand_string
, got_a_float
)
5424 char *operand_string
;
5430 /* Initialize token holders. */
5431 cur_token
.code
= prev_token
.code
= T_NIL
;
5432 cur_token
.reg
= prev_token
.reg
= NULL
;
5433 cur_token
.str
= prev_token
.str
= NULL
;
5435 /* Initialize parser structure. */
5436 p
= intel_parser
.op_string
= (char *) malloc (strlen (operand_string
) + 1);
5439 strcpy (intel_parser
.op_string
, operand_string
);
5440 intel_parser
.got_a_float
= got_a_float
;
5441 intel_parser
.op_modifier
= -1;
5442 intel_parser
.is_mem
= 0;
5443 intel_parser
.reg
= NULL
;
5444 intel_parser
.disp
= (char *) malloc (strlen (operand_string
) + 1);
5445 if (intel_parser
.disp
== NULL
)
5447 intel_parser
.disp
[0] = '\0';
5449 /* Read the first token and start the parser. */
5451 ret
= intel_expr ();
5455 /* If we found a memory reference, hand it over to i386_displacement
5456 to fill in the rest of the operand fields. */
5457 if (intel_parser
.is_mem
)
5459 if ((i
.mem_operands
== 1
5460 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5461 || i
.mem_operands
== 2)
5463 as_bad (_("too many memory references for '%s'"),
5464 current_templates
->start
->name
);
5469 char *s
= intel_parser
.disp
;
5472 /* Add the displacement expression. */
5474 ret
= i386_displacement (s
, s
+ strlen (s
));
5476 ret
= i386_index_check (operand_string
);
5480 /* Constant and OFFSET expressions are handled by i386_immediate. */
5481 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5482 || intel_parser
.reg
== NULL
)
5483 ret
= i386_immediate (intel_parser
.disp
);
5487 free (intel_parser
.disp
);
5497 /* expr SHORT e05 */
5498 if (cur_token
.code
== T_SHORT
)
5500 intel_parser
.op_modifier
= SHORT
;
5501 intel_match_token (T_SHORT
);
5503 return (intel_e05 ());
5508 return intel_e05 ();
5518 return (intel_e06 () && intel_e05_1 ());
5524 /* e05' addOp e06 e05' */
5525 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5527 strcat (intel_parser
.disp
, cur_token
.str
);
5528 intel_match_token (cur_token
.code
);
5530 return (intel_e06 () && intel_e05_1 ());
5545 return (intel_e09 () && intel_e06_1 ());
5551 /* e06' mulOp e09 e06' */
5552 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5554 strcat (intel_parser
.disp
, cur_token
.str
);
5555 intel_match_token (cur_token
.code
);
5557 return (intel_e09 () && intel_e06_1 ());
5565 /* e09 OFFSET e10 e09'
5574 /* e09 OFFSET e10 e09' */
5575 if (cur_token
.code
== T_OFFSET
)
5577 intel_parser
.is_mem
= 0;
5578 intel_parser
.op_modifier
= OFFSET_FLAT
;
5579 intel_match_token (T_OFFSET
);
5581 return (intel_e10 () && intel_e09_1 ());
5586 return (intel_e10 () && intel_e09_1 ());
5592 /* e09' PTR e10 e09' */
5593 if (cur_token
.code
== T_PTR
)
5595 if (prev_token
.code
== T_BYTE
)
5596 i
.suffix
= BYTE_MNEM_SUFFIX
;
5598 else if (prev_token
.code
== T_WORD
)
5600 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5601 i
.suffix
= SHORT_MNEM_SUFFIX
;
5603 i
.suffix
= WORD_MNEM_SUFFIX
;
5606 else if (prev_token
.code
== T_DWORD
)
5608 if (intel_parser
.got_a_float
== 1) /* "f..." */
5609 i
.suffix
= SHORT_MNEM_SUFFIX
;
5611 i
.suffix
= LONG_MNEM_SUFFIX
;
5614 else if (prev_token
.code
== T_QWORD
)
5616 if (intel_parser
.got_a_float
== 1) /* "f..." */
5617 i
.suffix
= LONG_MNEM_SUFFIX
;
5619 i
.suffix
= QWORD_MNEM_SUFFIX
;
5622 else if (prev_token
.code
== T_XWORD
)
5623 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5627 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5631 intel_match_token (T_PTR
);
5633 return (intel_e10 () && intel_e09_1 ());
5636 /* e09 : e10 e09' */
5637 else if (cur_token
.code
== ':')
5639 /* Mark as a memory operand only if it's not already known to be an
5640 offset expression. */
5641 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5642 intel_parser
.is_mem
= 1;
5644 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5659 return (intel_e11 () && intel_e10_1 ());
5665 /* e10' [ expr ] e10' */
5666 if (cur_token
.code
== '[')
5668 intel_match_token ('[');
5670 /* Mark as a memory operand only if it's not already known to be an
5671 offset expression. If it's an offset expression, we need to keep
5673 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5674 intel_parser
.is_mem
= 1;
5676 strcat (intel_parser
.disp
, "[");
5678 /* Add a '+' to the displacement string if necessary. */
5679 if (*intel_parser
.disp
!= '\0'
5680 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5681 strcat (intel_parser
.disp
, "+");
5683 if (intel_expr () && intel_match_token (']'))
5685 /* Preserve brackets when the operand is an offset expression. */
5686 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5687 strcat (intel_parser
.disp
, "]");
5689 return intel_e10_1 ();
5716 if (cur_token
.code
== '(')
5718 intel_match_token ('(');
5719 strcat (intel_parser
.disp
, "(");
5721 if (intel_expr () && intel_match_token (')'))
5723 strcat (intel_parser
.disp
, ")");
5731 else if (cur_token
.code
== '[')
5733 intel_match_token ('[');
5735 /* Mark as a memory operand only if it's not already known to be an
5736 offset expression. If it's an offset expression, we need to keep
5738 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5739 intel_parser
.is_mem
= 1;
5741 strcat (intel_parser
.disp
, "[");
5743 /* Operands for jump/call inside brackets denote absolute addresses. */
5744 if (current_templates
->start
->opcode_modifier
& Jump
5745 || current_templates
->start
->opcode_modifier
& JumpDword
5746 || current_templates
->start
->opcode_modifier
& JumpByte
5747 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5748 i
.types
[this_operand
] |= JumpAbsolute
;
5750 /* Add a '+' to the displacement string if necessary. */
5751 if (*intel_parser
.disp
!= '\0'
5752 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5753 strcat (intel_parser
.disp
, "+");
5755 if (intel_expr () && intel_match_token (']'))
5757 /* Preserve brackets when the operand is an offset expression. */
5758 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5759 strcat (intel_parser
.disp
, "]");
5772 else if (cur_token
.code
== T_BYTE
5773 || cur_token
.code
== T_WORD
5774 || cur_token
.code
== T_DWORD
5775 || cur_token
.code
== T_QWORD
5776 || cur_token
.code
== T_XWORD
)
5778 intel_match_token (cur_token
.code
);
5785 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5787 strcat (intel_parser
.disp
, cur_token
.str
);
5788 intel_match_token (cur_token
.code
);
5790 /* Mark as a memory operand only if it's not already known to be an
5791 offset expression. */
5792 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5793 intel_parser
.is_mem
= 1;
5799 else if (cur_token
.code
== T_REG
)
5801 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5803 intel_match_token (T_REG
);
5805 /* Check for segment change. */
5806 if (cur_token
.code
== ':')
5808 if (reg
->reg_type
& (SReg2
| SReg3
))
5810 switch (reg
->reg_num
)
5813 i
.seg
[i
.mem_operands
] = &es
;
5816 i
.seg
[i
.mem_operands
] = &cs
;
5819 i
.seg
[i
.mem_operands
] = &ss
;
5822 i
.seg
[i
.mem_operands
] = &ds
;
5825 i
.seg
[i
.mem_operands
] = &fs
;
5828 i
.seg
[i
.mem_operands
] = &gs
;
5834 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5839 /* Not a segment register. Check for register scaling. */
5840 else if (cur_token
.code
== '*')
5842 if (!intel_parser
.is_mem
)
5844 as_bad (_("Register scaling only allowed in memory operands."));
5848 /* What follows must be a valid scale. */
5849 if (intel_match_token ('*')
5850 && strchr ("01248", *cur_token
.str
))
5853 i
.types
[this_operand
] |= BaseIndex
;
5855 /* Set the scale after setting the register (otherwise,
5856 i386_scale will complain) */
5857 i386_scale (cur_token
.str
);
5858 intel_match_token (T_CONST
);
5862 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5868 /* No scaling. If this is a memory operand, the register is either a
5869 base register (first occurrence) or an index register (second
5871 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5873 if (i
.base_reg
&& i
.index_reg
)
5875 as_bad (_("Too many register references in memory operand.\n"));
5879 if (i
.base_reg
== NULL
)
5884 i
.types
[this_operand
] |= BaseIndex
;
5887 /* Offset modifier. Add the register to the displacement string to be
5888 parsed as an immediate expression after we're done. */
5889 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5890 strcat (intel_parser
.disp
, reg
->reg_name
);
5892 /* It's neither base nor index nor offset. */
5895 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5896 i
.op
[this_operand
].regs
= reg
;
5900 /* Since registers are not part of the displacement string (except
5901 when we're parsing offset operands), we may need to remove any
5902 preceding '+' from the displacement string. */
5903 if (*intel_parser
.disp
!= '\0'
5904 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
5906 char *s
= intel_parser
.disp
;
5907 s
+= strlen (s
) - 1;
5916 else if (cur_token
.code
== T_ID
)
5918 /* Add the identifier to the displacement string. */
5919 strcat (intel_parser
.disp
, cur_token
.str
);
5920 intel_match_token (T_ID
);
5922 /* The identifier represents a memory reference only if it's not
5923 preceded by an offset modifier. */
5924 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5925 intel_parser
.is_mem
= 1;
5931 else if (cur_token
.code
== T_CONST
5932 || cur_token
.code
== '-'
5933 || cur_token
.code
== '+')
5937 /* Allow constants that start with `+' or `-'. */
5938 if (cur_token
.code
== '-' || cur_token
.code
== '+')
5940 strcat (intel_parser
.disp
, cur_token
.str
);
5941 intel_match_token (cur_token
.code
);
5942 if (cur_token
.code
!= T_CONST
)
5944 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5950 save_str
= (char *) malloc (strlen (cur_token
.str
) + 1);
5951 if (save_str
== NULL
)
5953 strcpy (save_str
, cur_token
.str
);
5955 /* Get the next token to check for register scaling. */
5956 intel_match_token (cur_token
.code
);
5958 /* Check if this constant is a scaling factor for an index register. */
5959 if (cur_token
.code
== '*')
5961 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
5963 if (!intel_parser
.is_mem
)
5965 as_bad (_("Register scaling only allowed in memory operands."));
5969 /* The constant is followed by `* reg', so it must be
5971 if (strchr ("01248", *save_str
))
5973 i
.index_reg
= cur_token
.reg
;
5974 i
.types
[this_operand
] |= BaseIndex
;
5976 /* Set the scale after setting the register (otherwise,
5977 i386_scale will complain) */
5978 i386_scale (save_str
);
5979 intel_match_token (T_REG
);
5981 /* Since registers are not part of the displacement
5982 string, we may need to remove any preceding '+' from
5983 the displacement string. */
5984 if (*intel_parser
.disp
!= '\0')
5986 char *s
= intel_parser
.disp
;
5987 s
+= strlen (s
) - 1;
6000 /* The constant was not used for register scaling. Since we have
6001 already consumed the token following `*' we now need to put it
6002 back in the stream. */
6004 intel_putback_token ();
6007 /* Add the constant to the displacement string. */
6008 strcat (intel_parser
.disp
, save_str
);
6014 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
6018 /* Match the given token against cur_token. If they match, read the next
6019 token from the operand string. */
6021 intel_match_token (code
)
6024 if (cur_token
.code
== code
)
6031 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
6036 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6041 const reg_entry
*reg
;
6042 struct intel_token new_token
;
6044 new_token
.code
= T_NIL
;
6045 new_token
.reg
= NULL
;
6046 new_token
.str
= NULL
;
6048 /* Free the memory allocated to the previous token and move
6049 cur_token to prev_token. */
6051 free (prev_token
.str
);
6053 prev_token
= cur_token
;
6055 /* Skip whitespace. */
6056 while (is_space_char (*intel_parser
.op_string
))
6057 intel_parser
.op_string
++;
6059 /* Return an empty token if we find nothing else on the line. */
6060 if (*intel_parser
.op_string
== '\0')
6062 cur_token
= new_token
;
6066 /* The new token cannot be larger than the remainder of the operand
6068 new_token
.str
= (char *) malloc (strlen (intel_parser
.op_string
) + 1);
6069 if (new_token
.str
== NULL
)
6071 new_token
.str
[0] = '\0';
6073 if (strchr ("0123456789", *intel_parser
.op_string
))
6075 char *p
= new_token
.str
;
6076 char *q
= intel_parser
.op_string
;
6077 new_token
.code
= T_CONST
;
6079 /* Allow any kind of identifier char to encompass floating point and
6080 hexadecimal numbers. */
6081 while (is_identifier_char (*q
))
6085 /* Recognize special symbol names [0-9][bf]. */
6086 if (strlen (intel_parser
.op_string
) == 2
6087 && (intel_parser
.op_string
[1] == 'b'
6088 || intel_parser
.op_string
[1] == 'f'))
6089 new_token
.code
= T_ID
;
6092 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
6094 new_token
.code
= *intel_parser
.op_string
;
6095 new_token
.str
[0] = *intel_parser
.op_string
;
6096 new_token
.str
[1] = '\0';
6099 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6100 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
6102 new_token
.code
= T_REG
;
6103 new_token
.reg
= reg
;
6105 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
6107 new_token
.str
[0] = REGISTER_PREFIX
;
6108 new_token
.str
[1] = '\0';
6111 strcat (new_token
.str
, reg
->reg_name
);
6114 else if (is_identifier_char (*intel_parser
.op_string
))
6116 char *p
= new_token
.str
;
6117 char *q
= intel_parser
.op_string
;
6119 /* A '.' or '$' followed by an identifier char is an identifier.
6120 Otherwise, it's operator '.' followed by an expression. */
6121 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
6123 new_token
.code
= *q
;
6124 new_token
.str
[0] = *q
;
6125 new_token
.str
[1] = '\0';
6129 while (is_identifier_char (*q
) || *q
== '@')
6133 if (strcasecmp (new_token
.str
, "BYTE") == 0)
6134 new_token
.code
= T_BYTE
;
6136 else if (strcasecmp (new_token
.str
, "WORD") == 0)
6137 new_token
.code
= T_WORD
;
6139 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
6140 new_token
.code
= T_DWORD
;
6142 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
6143 new_token
.code
= T_QWORD
;
6145 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
6146 new_token
.code
= T_XWORD
;
6148 else if (strcasecmp (new_token
.str
, "PTR") == 0)
6149 new_token
.code
= T_PTR
;
6151 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
6152 new_token
.code
= T_SHORT
;
6154 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
6156 new_token
.code
= T_OFFSET
;
6158 /* ??? This is not mentioned in the MASM grammar but gcc
6159 makes use of it with -mintel-syntax. OFFSET may be
6160 followed by FLAT: */
6161 if (strncasecmp (q
, " FLAT:", 6) == 0)
6162 strcat (new_token
.str
, " FLAT:");
6165 /* ??? This is not mentioned in the MASM grammar. */
6166 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
6167 new_token
.code
= T_OFFSET
;
6170 new_token
.code
= T_ID
;
6175 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
6177 intel_parser
.op_string
+= strlen (new_token
.str
);
6178 cur_token
= new_token
;
6181 /* Put cur_token back into the token stream and make cur_token point to
6184 intel_putback_token ()
6186 intel_parser
.op_string
-= strlen (cur_token
.str
);
6187 free (cur_token
.str
);
6188 cur_token
= prev_token
;
6190 /* Forget prev_token. */
6191 prev_token
.code
= T_NIL
;
6192 prev_token
.reg
= NULL
;
6193 prev_token
.str
= NULL
;
6197 tc_x86_regname_to_dw2regnum (const char *regname
)
6199 unsigned int regnum
;
6200 unsigned int regnames_count
;
6201 char *regnames_32
[] =
6203 "eax", "ecx", "edx", "ebx",
6204 "esp", "ebp", "esi", "edi",
6207 char *regnames_64
[] =
6209 "rax", "rbx", "rcx", "rdx",
6210 "rdi", "rsi", "rbp", "rsp",
6211 "r8", "r9", "r10", "r11",
6212 "r12", "r13", "r14", "r15",
6217 if (flag_code
== CODE_64BIT
)
6219 regnames
= regnames_64
;
6220 regnames_count
= ARRAY_SIZE (regnames_64
);
6224 regnames
= regnames_32
;
6225 regnames_count
= ARRAY_SIZE (regnames_32
);
6228 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
6229 if (strcmp (regname
, regnames
[regnum
]) == 0)
6236 tc_x86_frame_initial_instructions (void)
6238 static unsigned int sp_regno
;
6241 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
6244 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
6245 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);