1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 1998
3 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better.
33 #include "opcode/i386.h"
36 #define TC_RELOC(X,Y) (Y)
39 #ifndef REGISTER_WARNINGS
40 #define REGISTER_WARNINGS 1
43 #ifndef SCALE1_WHEN_NO_INDEX
44 /* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48 #define SCALE1_WHEN_NO_INDEX 1
51 static unsigned long mode_from_disp_size
PARAMS ((unsigned long));
52 static int fits_in_signed_byte
PARAMS ((long));
53 static int fits_in_unsigned_byte
PARAMS ((long));
54 static int fits_in_unsigned_word
PARAMS ((long));
55 static int fits_in_signed_word
PARAMS ((long));
56 static int smallest_imm_type
PARAMS ((long));
57 static int add_prefix
PARAMS ((unsigned int));
58 static void set_16bit_code_flag
PARAMS ((int));
60 static bfd_reloc_code_real_type reloc
61 PARAMS ((int, int, bfd_reloc_code_real_type
));
64 /* 'md_assemble ()' gathers together information and puts it into a
69 /* TM holds the template for the insn were currently assembling. */
72 /* SUFFIX holds the opcode suffix (e.g. 'l' for 'movl') if given. */
75 /* Operands are coded with OPERANDS, TYPES, DISPS, IMMS, and REGS. */
77 /* OPERANDS gives the number of given operands. */
78 unsigned int operands
;
80 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
81 of given register, displacement, memory operands and immediate
83 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
85 /* TYPES [i] is the type (see above #defines) which tells us how to
86 search through DISPS [i] & IMMS [i] & REGS [i] for the required
88 unsigned int types
[MAX_OPERANDS
];
90 /* Displacements (if given) for each operand. */
91 expressionS
*disps
[MAX_OPERANDS
];
93 /* Relocation type for operand */
95 enum bfd_reloc_code_real disp_reloc
[MAX_OPERANDS
];
97 int disp_reloc
[MAX_OPERANDS
];
100 /* Immediate operands (if given) for each operand. */
101 expressionS
*imms
[MAX_OPERANDS
];
103 /* Register operands (if given) for each operand. */
104 const reg_entry
*regs
[MAX_OPERANDS
];
106 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
107 the base index byte below. */
108 const reg_entry
*base_reg
;
109 const reg_entry
*index_reg
;
110 unsigned int log2_scale_factor
;
112 /* SEG gives the seg_entries of this insn. They are zero unless
113 explicit segment overrides are given. */
114 const seg_entry
*seg
[2]; /* segments for memory operands (if given) */
116 /* PREFIX holds all the given prefix opcodes (usually null).
117 PREFIXES is the number of prefix opcodes. */
118 unsigned int prefixes
;
119 unsigned char prefix
[MAX_PREFIXES
];
121 /* RM and SIB are the modrm byte and the sib byte where the
122 addressing modes of this insn are encoded. */
128 typedef struct _i386_insn i386_insn
;
130 /* List of chars besides those in app.c:symbol_chars that can start an
131 operand. Used to prevent the scrubber eating vital white-space. */
133 const char extra_symbol_chars
[] = "*%-(@";
135 const char extra_symbol_chars
[] = "*%-(";
138 /* This array holds the chars that always start a comment. If the
139 pre-processor is disabled, these aren't very useful */
140 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX))
141 /* Putting '/' here makes it impossible to use the divide operator.
142 However, we need it for compatibility with SVR4 systems. */
143 const char comment_chars
[] = "#/";
144 #define PREFIX_SEPARATOR '\\'
146 const char comment_chars
[] = "#";
147 #define PREFIX_SEPARATOR '/'
150 /* This array holds the chars that only start a comment at the beginning of
151 a line. If the line seems to have the form '# 123 filename'
152 .line and .file directives will appear in the pre-processed output */
153 /* Note that input_file.c hand checks for '#' at the beginning of the
154 first line of the input file. This is because the compiler outputs
155 #NO_APP at the beginning of its output. */
156 /* Also note that comments started like this one will always work if
157 '/' isn't otherwise defined. */
158 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX))
159 const char line_comment_chars
[] = "";
161 const char line_comment_chars
[] = "/";
164 const char line_separator_chars
[] = "";
166 /* Chars that can be used to separate mant from exp in floating point nums */
167 const char EXP_CHARS
[] = "eE";
169 /* Chars that mean this number is a floating point constant */
172 const char FLT_CHARS
[] = "fFdDxX";
174 /* tables for lexical analysis */
175 static char opcode_chars
[256];
176 static char register_chars
[256];
177 static char operand_chars
[256];
178 static char identifier_chars
[256];
179 static char digit_chars
[256];
182 #define is_opcode_char(x) (opcode_chars[(unsigned char) x])
183 #define is_operand_char(x) (operand_chars[(unsigned char) x])
184 #define is_register_char(x) (register_chars[(unsigned char) x])
185 #define is_space_char(x) ((x) == ' ')
186 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
187 #define is_digit_char(x) (digit_chars[(unsigned char) x])
189 /* put here all non-digit non-letter charcters that may occur in an operand */
190 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
192 /* md_assemble() always leaves the strings it's passed unaltered. To
193 effect this we maintain a stack of saved characters that we've smashed
194 with '\0's (indicating end of strings for various sub-fields of the
195 assembler instruction). */
196 static char save_stack
[32];
197 static char *save_stack_p
; /* stack pointer */
198 #define END_STRING_AND_SAVE(s) \
199 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
200 #define RESTORE_END_STRING(s) \
201 do { *(s) = *--save_stack_p; } while (0)
203 /* The instruction we're assembling. */
206 /* Possible templates for current insn. */
207 static const templates
*current_templates
;
209 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
210 static expressionS disp_expressions
[2], im_expressions
[2];
212 static int this_operand
; /* current operand we are working on */
214 static int flag_do_long_jump
; /* FIXME what does this do? */
216 static int flag_16bit_code
; /* 1 if we're writing 16-bit code, 0 if 32-bit */
218 /* Interface to relax_segment.
219 There are 2 relax states for 386 jump insns: one for conditional &
220 one for unconditional jumps. This is because the these two types
221 of jumps add different sizes to frags when we're figuring out what
222 sort of jump to choose to reach a given label. */
225 #define COND_JUMP 1 /* conditional jump */
226 #define UNCOND_JUMP 2 /* unconditional jump */
230 #define SMALL16 (SMALL|CODE16)
232 #define BIG16 (BIG|CODE16)
236 #define INLINE __inline__
242 #define ENCODE_RELAX_STATE(type,size) \
243 ((relax_substateT)((type<<2) | (size)))
244 #define SIZE_FROM_RELAX_STATE(s) \
245 ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) )
247 /* This table is used by relax_frag to promote short jumps to long
248 ones where necessary. SMALL (short) jumps may be promoted to BIG
249 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
250 don't allow a short jump in a 32 bit code segment to be promoted to
251 a 16 bit offset jump because it's slower (requires data size
252 prefix), and doesn't work, unless the destination is in the bottom
253 64k of the code segment (The top 16 bits of eip are zeroed). */
255 const relax_typeS md_relax_table
[] =
258 1) most positive reach of this state,
259 2) most negative reach of this state,
260 3) how many bytes this mode will add to the size of the current frag
261 4) which index into the table to try if we can't fit into this one.
268 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
269 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
270 /* dword conditionals adds 4 bytes to frag:
271 1 extra opcode byte, 3 extra displacement bytes. */
273 /* word conditionals add 2 bytes to frag:
274 1 extra opcode byte, 1 extra displacement byte. */
277 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
278 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
279 /* dword jmp adds 3 bytes to frag:
280 0 extra opcode bytes, 3 extra displacement bytes. */
282 /* word jmp adds 1 byte to frag:
283 0 extra opcode bytes, 1 extra displacement byte. */
290 i386_align_code (fragP
, count
)
294 /* Various efficient no-op patterns for aligning code labels. */
295 /* Note: Don't try to assemble the instructions in the comments. */
296 /* 0L and 0w are not legal */
297 static const char f32_1
[] =
299 static const char f32_2
[] =
300 {0x89,0xf6}; /* movl %esi,%esi */
301 static const char f32_3
[] =
302 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
303 static const char f32_4
[] =
304 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
305 static const char f32_5
[] =
307 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
308 static const char f32_6
[] =
309 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
310 static const char f32_7
[] =
311 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
312 static const char f32_8
[] =
314 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
315 static const char f32_9
[] =
316 {0x89,0xf6, /* movl %esi,%esi */
317 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
318 static const char f32_10
[] =
319 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
320 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
321 static const char f32_11
[] =
322 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
323 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
324 static const char f32_12
[] =
325 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
326 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
327 static const char f32_13
[] =
328 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
329 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
330 static const char f32_14
[] =
331 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
332 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
333 static const char f32_15
[] =
334 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
335 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
336 static const char f16_4
[] =
337 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
338 static const char f16_5
[] =
340 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
341 static const char f16_6
[] =
342 {0x89,0xf6, /* mov %si,%si */
343 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
344 static const char f16_7
[] =
345 {0x8d,0x74,0x00, /* lea 0(%si),%si */
346 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
347 static const char f16_8
[] =
348 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
349 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
350 static const char *const f32_patt
[] = {
351 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
352 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
354 static const char *const f16_patt
[] = {
355 f32_1
, f32_2
, f32_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
356 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
359 if (count
> 0 && count
<= 15)
363 memcpy(fragP
->fr_literal
+ fragP
->fr_fix
,
364 f16_patt
[count
- 1], count
);
365 if (count
> 8) /* adjust jump offset */
366 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
369 memcpy(fragP
->fr_literal
+ fragP
->fr_fix
,
370 f32_patt
[count
- 1], count
);
371 fragP
->fr_var
= count
;
375 static char *output_invalid
PARAMS ((int c
));
376 static int i386_operand
PARAMS ((char *operand_string
));
377 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
380 static void s_bss
PARAMS ((int));
383 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
385 static INLINE
unsigned long
386 mode_from_disp_size (t
)
389 return (t
& Disp8
) ? 1 : (t
& (Disp16
|Disp32
)) ? 2 : 0;
393 fits_in_signed_byte (num
)
396 return (num
>= -128) && (num
<= 127);
397 } /* fits_in_signed_byte() */
400 fits_in_unsigned_byte (num
)
403 return (num
& 0xff) == num
;
404 } /* fits_in_unsigned_byte() */
407 fits_in_unsigned_word (num
)
410 return (num
& 0xffff) == num
;
411 } /* fits_in_unsigned_word() */
414 fits_in_signed_word (num
)
417 return (-32768 <= num
) && (num
<= 32767);
418 } /* fits_in_signed_word() */
421 smallest_imm_type (num
)
425 /* This code is disabled because all the Imm1 forms in the opcode table
426 are slower on the i486, and they're the versions with the implicitly
427 specified single-position displacement, which has another syntax if
428 you really want to use that form. If you really prefer to have the
429 one-byte-shorter Imm1 form despite these problems, re-enable this
432 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
;
434 return (fits_in_signed_byte (num
)
435 ? (Imm8S
| Imm8
| Imm16
| Imm32
)
436 : fits_in_unsigned_byte (num
)
437 ? (Imm8
| Imm16
| Imm32
)
438 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
441 } /* smallest_imm_type() */
443 /* Returns 0 if attempting to add a prefix where one from the same
444 class already exists, 1 if non rep/repne added, 2 if rep/repne
458 case CS_PREFIX_OPCODE
:
459 case DS_PREFIX_OPCODE
:
460 case ES_PREFIX_OPCODE
:
461 case FS_PREFIX_OPCODE
:
462 case GS_PREFIX_OPCODE
:
463 case SS_PREFIX_OPCODE
:
467 case REPNE_PREFIX_OPCODE
:
468 case REPE_PREFIX_OPCODE
:
471 case LOCK_PREFIX_OPCODE
:
479 case ADDR_PREFIX_OPCODE
:
483 case DATA_PREFIX_OPCODE
:
490 as_bad (_("same type of prefix used twice"));
495 i
.prefix
[q
] = prefix
;
500 set_16bit_code_flag (new_16bit_code_flag
)
501 int new_16bit_code_flag
;
503 flag_16bit_code
= new_16bit_code_flag
;
506 const pseudo_typeS md_pseudo_table
[] =
511 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
512 {"align", s_align_bytes
, 0},
514 {"align", s_align_ptwo
, 0},
516 {"ffloat", float_cons
, 'f'},
517 {"dfloat", float_cons
, 'd'},
518 {"tfloat", float_cons
, 'x'},
520 {"noopt", s_ignore
, 0},
521 {"optim", s_ignore
, 0},
522 {"code16", set_16bit_code_flag
, 1},
523 {"code32", set_16bit_code_flag
, 0},
527 /* for interface with expression () */
528 extern char *input_line_pointer
;
530 /* hash table for opcode lookup */
531 static struct hash_control
*op_hash
;
532 /* hash table for register lookup */
533 static struct hash_control
*reg_hash
;
539 const char *hash_err
;
541 /* initialize op_hash hash table */
542 op_hash
= hash_new ();
545 register const template *optab
;
546 register templates
*core_optab
;
548 optab
= i386_optab
; /* setup for loop */
549 core_optab
= (templates
*) xmalloc (sizeof (templates
));
550 core_optab
->start
= optab
;
555 if (optab
->name
== NULL
556 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
558 /* different name --> ship out current template list;
559 add to hash table; & begin anew */
560 core_optab
->end
= optab
;
561 hash_err
= hash_insert (op_hash
,
567 as_fatal (_("Internal Error: Can't hash %s: %s"),
571 if (optab
->name
== NULL
)
573 core_optab
= (templates
*) xmalloc (sizeof (templates
));
574 core_optab
->start
= optab
;
579 /* initialize reg_hash hash table */
580 reg_hash
= hash_new ();
582 register const reg_entry
*regtab
;
584 for (regtab
= i386_regtab
;
585 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
588 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
594 /* fill in lexical tables: opcode_chars, operand_chars. */
599 for (c
= 0; c
< 256; c
++)
605 register_chars
[c
] = c
;
606 operand_chars
[c
] = c
;
608 else if (islower (c
))
611 register_chars
[c
] = c
;
612 operand_chars
[c
] = c
;
614 else if (isupper (c
))
616 opcode_chars
[c
] = tolower (c
);
617 register_chars
[c
] = opcode_chars
[c
];
618 operand_chars
[c
] = c
;
621 if (isalpha (c
) || isdigit (c
))
622 identifier_chars
[c
] = c
;
626 identifier_chars
['@'] = '@';
628 register_chars
[')'] = ')';
629 register_chars
['('] = '(';
630 digit_chars
['-'] = '-';
631 identifier_chars
['_'] = '_';
632 identifier_chars
['.'] = '.';
634 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
635 operand_chars
[(unsigned char) *p
] = *p
;
638 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
639 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
641 record_alignment (text_section
, 2);
642 record_alignment (data_section
, 2);
643 record_alignment (bss_section
, 2);
649 i386_print_statistics (file
)
652 hash_print_statistics (file
, "i386 opcode", op_hash
);
653 hash_print_statistics (file
, "i386 register", reg_hash
);
659 /* debugging routines for md_assemble */
660 static void pi
PARAMS ((char *, i386_insn
*));
661 static void pte
PARAMS ((template *));
662 static void pt
PARAMS ((unsigned int));
663 static void pe
PARAMS ((expressionS
*));
664 static void ps
PARAMS ((symbolS
*));
671 register template *p
;
674 fprintf (stdout
, "%s: template ", line
);
676 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x",
677 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
678 fprintf (stdout
, " base %x index %x scale %x\n",
679 x
->bi
.base
, x
->bi
.index
, x
->bi
.scale
);
680 for (i
= 0; i
< x
->operands
; i
++)
682 fprintf (stdout
, " #%d: ", i
+ 1);
684 fprintf (stdout
, "\n");
686 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
))
687 fprintf (stdout
, "%s\n", x
->regs
[i
]->reg_name
);
688 if (x
->types
[i
] & Imm
)
690 if (x
->types
[i
] & Disp
)
700 fprintf (stdout
, " %d operands ", t
->operands
);
701 fprintf (stdout
, "opcode %x ",
703 if (t
->extension_opcode
!= None
)
704 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
705 if (t
->opcode_modifier
& D
)
706 fprintf (stdout
, "D");
707 if (t
->opcode_modifier
& W
)
708 fprintf (stdout
, "W");
709 fprintf (stdout
, "\n");
710 for (i
= 0; i
< t
->operands
; i
++)
712 fprintf (stdout
, " #%d type ", i
+ 1);
713 pt (t
->operand_types
[i
]);
714 fprintf (stdout
, "\n");
722 fprintf (stdout
, " operation %d\n", e
->X_op
);
723 fprintf (stdout
, " add_number %d (%x)\n",
724 e
->X_add_number
, e
->X_add_number
);
727 fprintf (stdout
, " add_symbol ");
728 ps (e
->X_add_symbol
);
729 fprintf (stdout
, "\n");
733 fprintf (stdout
, " op_symbol ");
735 fprintf (stdout
, "\n");
743 fprintf (stdout
, "%s type %s%s",
745 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
746 segment_name (S_GET_SEGMENT (s
)));
765 { BaseIndex
, "BaseIndex" },
769 { InOutPortReg
, "InOutPortReg" },
770 { ShiftCount
, "ShiftCount" },
771 { Control
, "control reg" },
772 { Test
, "test reg" },
773 { Debug
, "debug reg" },
774 { FloatReg
, "FReg" },
775 { FloatAcc
, "FAcc" },
779 { JumpAbsolute
, "Jump Absolute" },
789 register struct type_name
*ty
;
793 fprintf (stdout
, _("Unknown"));
797 for (ty
= type_names
; ty
->mask
; ty
++)
799 fprintf (stdout
, "%s, ", ty
->tname
);
804 #endif /* DEBUG386 */
807 static bfd_reloc_code_real_type
808 reloc (size
, pcrel
, other
)
811 bfd_reloc_code_real_type other
;
813 if (other
!= NO_RELOC
) return other
;
819 case 1: return BFD_RELOC_8_PCREL
;
820 case 2: return BFD_RELOC_16_PCREL
;
821 case 4: return BFD_RELOC_32_PCREL
;
823 as_bad (_("Can not do %d byte pc-relative relocation"), size
);
829 case 1: return BFD_RELOC_8
;
830 case 2: return BFD_RELOC_16
;
831 case 4: return BFD_RELOC_32
;
833 as_bad (_("Can not do %d byte relocation"), size
);
836 return BFD_RELOC_NONE
;
840 * Here we decide which fixups can be adjusted to make them relative to
841 * the beginning of the section instead of the symbol. Basically we need
842 * to make sure that the dynamic relocations are done correctly, so in
843 * some cases we force the original symbol to be used.
846 tc_i386_fix_adjustable(fixP
)
850 /* Prevent all adjustments to global symbols. */
851 if (S_IS_EXTERN (fixP
->fx_addsy
))
853 if (S_IS_WEAK (fixP
->fx_addsy
))
855 #endif /* ! defined (OBJ_AOUT) */
856 /* adjust_reloc_syms doesn't know about the GOT */
857 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
858 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
859 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
)
864 #define reloc(SIZE,PCREL,OTHER) 0
865 #define BFD_RELOC_16 0
866 #define BFD_RELOC_32 0
867 #define BFD_RELOC_16_PCREL 0
868 #define BFD_RELOC_32_PCREL 0
869 #define BFD_RELOC_386_PLT32 0
870 #define BFD_RELOC_386_GOT32 0
871 #define BFD_RELOC_386_GOTOFF 0
874 /* This is the guts of the machine-dependent assembler. LINE points to a
875 machine dependent instruction. This function is supposed to emit
876 the frags/bytes it assembles to. */
882 /* Points to template once we've found it. */
885 /* Count the size of the instruction generated. */
890 /* Initialize globals. */
891 memset (&i
, '\0', sizeof (i
));
892 for (j
= 0; j
< MAX_OPERANDS
; j
++)
893 i
.disp_reloc
[j
] = NO_RELOC
;
894 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
895 memset (im_expressions
, '\0', sizeof (im_expressions
));
896 save_stack_p
= save_stack
; /* reset stack pointer */
898 /* First parse an opcode & call i386_operand for the operands.
899 We assume that the scrubber has arranged it so that line[0] is the valid
900 start of a (possibly prefixed) opcode. */
902 char opcode
[MAX_OPCODE_SIZE
];
904 char *token_start
= l
;
907 /* Non-zero if we found a prefix only acceptable with string insns. */
908 const char *expecting_string_instruction
= NULL
;
913 while ((*opp
= opcode_chars
[(unsigned char) *l
]) != 0)
916 if (opp
>= opcode
+ sizeof (opcode
))
918 as_bad (_("no such 386 instruction: `%s'"), token_start
);
923 if (!is_space_char (*l
)
925 && *l
!= PREFIX_SEPARATOR
)
927 as_bad (_("invalid character %s in opcode"),
928 output_invalid (*l
));
931 if (token_start
== l
)
933 if (*l
== PREFIX_SEPARATOR
)
934 as_bad (_("expecting prefix; got nothing"));
936 as_bad (_("expecting opcode; got nothing"));
940 /* Look up instruction (or prefix) via hash table. */
941 current_templates
= hash_find (op_hash
, opcode
);
943 if (*l
!= END_OF_INSN
945 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
947 /* If we are in 16-bit mode, do not allow addr16 or data16.
948 Similarly, in 32-bit mode, do not allow addr32 or data32. */
949 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
950 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
953 as_bad (_("redundant %s prefix"),
954 current_templates
->start
->name
);
957 /* Add prefix, checking for repeated prefixes. */
958 switch (add_prefix (current_templates
->start
->base_opcode
))
963 expecting_string_instruction
=
964 current_templates
->start
->name
;
967 /* Skip past PREFIX_SEPARATOR and reset token_start. */
974 if (!current_templates
)
976 /* See if we can get a match by trimming off a suffix. */
979 case DWORD_OPCODE_SUFFIX
:
980 case WORD_OPCODE_SUFFIX
:
981 case BYTE_OPCODE_SUFFIX
:
982 case SHORT_OPCODE_SUFFIX
:
983 #if LONG_OPCODE_SUFFIX != DWORD_OPCODE_SUFFIX
984 case LONG_OPCODE_SUFFIX
:
988 current_templates
= hash_find (op_hash
, opcode
);
990 if (!current_templates
)
992 as_bad (_("no such 386 instruction: `%s'"), token_start
);
997 /* check for rep/repne without a string instruction */
998 if (expecting_string_instruction
999 && !(current_templates
->start
->opcode_modifier
& IsString
))
1001 as_bad (_("expecting string instruction after `%s'"),
1002 expecting_string_instruction
);
1006 /* There may be operands to parse. */
1007 if (*l
!= END_OF_INSN
)
1009 /* parse operands */
1011 /* 1 if operand is pending after ','. */
1012 unsigned int expecting_operand
= 0;
1014 /* Non-zero if operand parens not balanced. */
1015 unsigned int paren_not_balanced
;
1019 /* skip optional white space before operand */
1020 if (is_space_char (*l
))
1022 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1024 as_bad (_("invalid character %s before operand %d"),
1025 output_invalid (*l
),
1029 token_start
= l
; /* after white space */
1030 paren_not_balanced
= 0;
1031 while (paren_not_balanced
|| *l
!= ',')
1033 if (*l
== END_OF_INSN
)
1035 if (paren_not_balanced
)
1037 as_bad (_("unbalanced parenthesis in operand %d."),
1042 break; /* we are done */
1044 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1046 as_bad (_("invalid character %s in operand %d"),
1047 output_invalid (*l
),
1052 ++paren_not_balanced
;
1054 --paren_not_balanced
;
1057 if (l
!= token_start
)
1058 { /* yes, we've read in another operand */
1059 unsigned int operand_ok
;
1060 this_operand
= i
.operands
++;
1061 if (i
.operands
> MAX_OPERANDS
)
1063 as_bad (_("spurious operands; (%d operands/instruction max)"),
1067 /* now parse operand adding info to 'i' as we go along */
1068 END_STRING_AND_SAVE (l
);
1069 operand_ok
= i386_operand (token_start
);
1070 RESTORE_END_STRING (l
); /* restore old contents */
1076 if (expecting_operand
)
1078 expecting_operand_after_comma
:
1079 as_bad (_("expecting operand after ','; got nothing"));
1084 as_bad (_("expecting operand before ','; got nothing"));
1089 /* now *l must be either ',' or END_OF_INSN */
1092 if (*++l
== END_OF_INSN
)
1093 { /* just skip it, if it's \n complain */
1094 goto expecting_operand_after_comma
;
1096 expecting_operand
= 1;
1099 while (*l
!= END_OF_INSN
); /* until we get end of insn */
1103 /* Now we've parsed the opcode into a set of templates, and have the
1106 Next, we find a template that matches the given insn,
1107 making sure the overlap of the given operands types is consistent
1108 with the template operand types. */
1110 #define MATCH(overlap, given, template) \
1112 && ((given) & BaseIndex) == ((overlap) & BaseIndex) \
1113 && ((given) & JumpAbsolute) == ((template) & JumpAbsolute))
1115 /* If given types r0 and r1 are registers they must be of the same type
1116 unless the expected operand type register overlap is null.
1117 Note that Acc in a template matches every size of reg. */
1118 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1119 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1120 ((g0) & Reg) == ((g1) & Reg) || \
1121 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1124 register unsigned int overlap0
, overlap1
;
1126 unsigned int overlap2
;
1127 unsigned int found_reverse_match
;
1133 found_reverse_match
= 0;
1134 suffix_check
= (i
.suffix
== BYTE_OPCODE_SUFFIX
1136 : (i
.suffix
== WORD_OPCODE_SUFFIX
1138 : (i
.suffix
== SHORT_OPCODE_SUFFIX
1140 : (i
.suffix
== LONG_OPCODE_SUFFIX
? No_lSuf
: 0))));
1142 for (t
= current_templates
->start
;
1143 t
< current_templates
->end
;
1146 /* Must have right number of operands, and must not have
1147 disallowed suffix. */
1148 if (i
.operands
!= t
->operands
|| (t
->opcode_modifier
& suffix_check
))
1150 else if (!t
->operands
)
1151 break; /* 0 operands always matches */
1153 overlap0
= i
.types
[0] & t
->operand_types
[0];
1154 switch (t
->operands
)
1157 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1162 overlap1
= i
.types
[1] & t
->operand_types
[1];
1163 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1164 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1165 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1166 t
->operand_types
[0],
1167 overlap1
, i
.types
[1],
1168 t
->operand_types
[1]))
1171 /* check if other direction is valid ... */
1172 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1175 /* try reversing direction of operands */
1176 overlap0
= i
.types
[0] & t
->operand_types
[1];
1177 overlap1
= i
.types
[1] & t
->operand_types
[0];
1178 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1179 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1180 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1181 t
->operand_types
[1],
1182 overlap1
, i
.types
[1],
1183 t
->operand_types
[0]))
1185 /* does not match either direction */
1188 /* found_reverse_match holds which of D or FloatDR
1190 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1193 /* found a forward 2 operand match here */
1194 if (t
->operands
== 3)
1196 /* Here we make use of the fact that there are no
1197 reverse match 3 operand instructions, and all 3
1198 operand instructions only need to be checked for
1199 register consistency between operands 2 and 3. */
1200 overlap2
= i
.types
[2] & t
->operand_types
[2];
1201 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1202 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1203 t
->operand_types
[1],
1204 overlap2
, i
.types
[2],
1205 t
->operand_types
[2]))
1208 /* found either forward/reverse 2 or 3 operand match here:
1209 slip through to break */
1211 break; /* we've found a match; break out of loop */
1212 } /* for (t = ... */
1213 if (t
== current_templates
->end
)
1214 { /* we found no match */
1215 as_bad (_("suffix or operands invalid for `%s'"),
1216 current_templates
->start
->name
);
1220 /* Copy the template we found. */
1222 if (found_reverse_match
)
1224 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1225 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1228 if (i
.tm
.opcode_modifier
& FWait
)
1229 if (! add_prefix (FWAIT_OPCODE
))
1232 /* Check string instruction segment overrides */
1233 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1235 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1236 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1238 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1240 as_bad (_("`%s' operand %d must use `%%es' segment"),
1245 /* There's only ever one segment override allowed per instruction.
1246 This instruction possibly has a legal segment override on the
1247 second operand, so copy the segment to where non-string
1248 instructions store it, allowing common code. */
1249 i
.seg
[0] = i
.seg
[1];
1251 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1253 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1255 as_bad (_("`%s' operand %d must use `%%es' segment"),
1263 /* If matched instruction specifies an explicit opcode suffix, use
1265 if (i
.tm
.opcode_modifier
& (Size16
| Size32
))
1267 if (i
.tm
.opcode_modifier
& Size16
)
1268 i
.suffix
= WORD_OPCODE_SUFFIX
;
1270 i
.suffix
= DWORD_OPCODE_SUFFIX
;
1272 else if (i
.reg_operands
)
1274 /* If there's no opcode suffix we try to invent one based on
1275 register operands. */
1278 /* We take i.suffix from the last register operand specified,
1279 Destination register type is more significant than source
1282 for (op
= i
.operands
; --op
>= 0; )
1283 if (i
.types
[op
] & Reg
)
1285 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_OPCODE_SUFFIX
:
1286 (i
.types
[op
] & Reg16
) ? WORD_OPCODE_SUFFIX
:
1287 DWORD_OPCODE_SUFFIX
);
1291 else if (i
.suffix
== BYTE_OPCODE_SUFFIX
)
1294 for (op
= i
.operands
; --op
>= 0; )
1296 /* If this is an eight bit register, it's OK. If it's
1297 the 16 or 32 bit version of an eight bit register,
1298 we will just use the low portion, and that's OK too. */
1299 if (i
.types
[op
] & Reg8
)
1301 if ((i
.types
[op
] & WordReg
) && i
.regs
[op
]->reg_num
< 4
1303 /* Check that the template allows eight bit regs
1304 This kills insns such as `orb $1,%edx', which
1305 maybe should be allowed. */
1306 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
1310 #if REGISTER_WARNINGS
1311 if ((i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1312 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1313 (i
.regs
[op
] - (i
.types
[op
] & Reg16
? 8 : 16))->reg_name
,
1314 i
.regs
[op
]->reg_name
,
1319 /* Any other register is bad */
1320 if (i
.types
[op
] & (Reg
| RegMMX
| Control
| Debug
| Test
1321 | FloatReg
| FloatAcc
| SReg2
| SReg3
))
1323 as_bad (_("`%%%s' not allowed with `%s%c'"),
1324 i
.regs
[op
]->reg_name
,
1331 else if (i
.suffix
== DWORD_OPCODE_SUFFIX
)
1334 for (op
= i
.operands
; --op
>= 0; )
1335 /* Reject eight bit registers, except where the template
1336 requires them. (eg. movzb) */
1337 if ((i
.types
[op
] & Reg8
) != 0
1338 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
1340 as_bad (_("`%%%s' not allowed with `%s%c'"),
1341 i
.regs
[op
]->reg_name
,
1346 #if REGISTER_WARNINGS
1347 /* Warn if the e prefix on a general reg is missing. */
1348 else if ((i
.types
[op
] & Reg16
) != 0
1349 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
1351 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1352 (i
.regs
[op
] + 8)->reg_name
,
1353 i
.regs
[op
]->reg_name
,
1358 else if (i
.suffix
== WORD_OPCODE_SUFFIX
)
1361 for (op
= i
.operands
; --op
>= 0; )
1362 /* Reject eight bit registers, except where the template
1363 requires them. (eg. movzb) */
1364 if ((i
.types
[op
] & Reg8
) != 0
1365 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
1367 as_bad (_("`%%%s' not allowed with `%s%c'"),
1368 i
.regs
[op
]->reg_name
,
1373 #if REGISTER_WARNINGS
1374 /* Warn if the e prefix on a general reg is present. */
1375 else if ((i
.types
[op
] & Reg32
) != 0
1376 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
1378 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1379 (i
.regs
[op
] - 8)->reg_name
,
1380 i
.regs
[op
]->reg_name
,
1389 /* Make still unresolved immediate matches conform to size of immediate
1390 given in i.suffix. Note: overlap2 cannot be an immediate! */
1391 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
))
1392 && overlap0
!= Imm8
&& overlap0
!= Imm8S
1393 && overlap0
!= Imm16
&& overlap0
!= Imm32
)
1397 overlap0
&= (i
.suffix
== BYTE_OPCODE_SUFFIX
? (Imm8
| Imm8S
) :
1398 (i
.suffix
== WORD_OPCODE_SUFFIX
? Imm16
: Imm32
));
1400 else if (overlap0
== (Imm16
| Imm32
))
1403 (flag_16bit_code
^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32
;
1407 as_bad (_("no opcode suffix given; can't determine immediate size"));
1411 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32
))
1412 && overlap1
!= Imm8
&& overlap1
!= Imm8S
1413 && overlap1
!= Imm16
&& overlap1
!= Imm32
)
1417 overlap1
&= (i
.suffix
== BYTE_OPCODE_SUFFIX
? (Imm8
| Imm8S
) :
1418 (i
.suffix
== WORD_OPCODE_SUFFIX
? Imm16
: Imm32
));
1420 else if (overlap1
== (Imm16
| Imm32
))
1423 (flag_16bit_code
^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32
;
1427 as_bad (_("no opcode suffix given; can't determine immediate size"));
1431 assert ((overlap2
& Imm
) == 0);
1433 i
.types
[0] = overlap0
;
1434 if (overlap0
& ImplicitRegister
)
1436 if (overlap0
& Imm1
)
1437 i
.imm_operands
= 0; /* kludge for shift insns */
1439 i
.types
[1] = overlap1
;
1440 if (overlap1
& ImplicitRegister
)
1443 i
.types
[2] = overlap2
;
1444 if (overlap2
& ImplicitRegister
)
1447 /* Finalize opcode. First, we change the opcode based on the operand
1448 size given by i.suffix: we never have to change things for byte insns,
1449 or when no opcode suffix is need to size the operands. */
1451 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
1453 as_bad (_("no opcode suffix given and no register operands; can't size instruction"));
1457 if (i
.suffix
&& i
.suffix
!= BYTE_OPCODE_SUFFIX
)
1459 /* Select between byte and word/dword operations. */
1460 if (i
.tm
.opcode_modifier
& W
)
1462 if (i
.tm
.opcode_modifier
& ShortForm
)
1463 i
.tm
.base_opcode
|= 8;
1465 i
.tm
.base_opcode
|= 1;
1467 /* Now select between word & dword operations via the operand
1468 size prefix, except for instructions that will ignore this
1470 if ((i
.suffix
== DWORD_OPCODE_SUFFIX
1471 || i
.suffix
== LONG_OPCODE_SUFFIX
) == flag_16bit_code
1472 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
1474 unsigned int prefix
= DATA_PREFIX_OPCODE
;
1475 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
1476 prefix
= ADDR_PREFIX_OPCODE
;
1478 if (! add_prefix (prefix
))
1481 /* Size floating point instruction. */
1482 if (i
.suffix
== LONG_OPCODE_SUFFIX
)
1484 if (i
.tm
.opcode_modifier
& FloatMF
)
1485 i
.tm
.base_opcode
^= 4;
1489 /* For insns with operands there are more diddles to do to the opcode. */
1492 /* Default segment register this instruction will use
1493 for memory accesses. 0 means unknown.
1494 This is only for optimizing out unnecessary segment overrides. */
1495 const seg_entry
*default_seg
= 0;
1497 /* If we found a reverse match we must alter the opcode
1498 direction bit. found_reverse_match holds bits to change
1499 (different for int & float insns). */
1501 i
.tm
.base_opcode
^= found_reverse_match
;
1503 /* The imul $imm, %reg instruction is converted into
1504 imul $imm, %reg, %reg, and the clr %reg instruction
1505 is converted into xor %reg, %reg. */
1506 if (i
.tm
.opcode_modifier
& regKludge
)
1508 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
1509 /* Pretend we saw the extra register operand. */
1510 i
.regs
[first_reg_op
+1] = i
.regs
[first_reg_op
];
1514 if (i
.tm
.opcode_modifier
& ShortForm
)
1516 /* The register or float register operand is in operand 0 or 1. */
1517 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
1518 /* Register goes in low 3 bits of opcode. */
1519 i
.tm
.base_opcode
|= i
.regs
[op
]->reg_num
;
1520 if ((i
.tm
.opcode_modifier
& Ugh
) != 0)
1522 /* Warn about some common errors, but press on regardless.
1523 The first case can be generated by gcc (<= 2.8.1). */
1524 if (i
.operands
== 2)
1526 /* reversed arguments on faddp, fsubp, etc. */
1527 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
1528 i
.regs
[1]->reg_name
,
1529 i
.regs
[0]->reg_name
);
1533 /* extraneous `l' suffix on fp insn */
1534 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
1535 i
.regs
[0]->reg_name
);
1539 else if (i
.tm
.opcode_modifier
& Modrm
)
1541 /* The opcode is completed (modulo i.tm.extension_opcode which
1542 must be put into the modrm byte).
1543 Now, we make the modrm & index base bytes based on all the
1544 info we've collected. */
1546 /* i.reg_operands MUST be the number of real register operands;
1547 implicit registers do not count. */
1548 if (i
.reg_operands
== 2)
1550 unsigned int source
, dest
;
1551 source
= ((i
.types
[0]
1562 /* Certain instructions expect the destination to be
1563 in the i.rm.reg field. This is by far the
1564 exceptional case. For these instructions, if the
1565 source operand is a register, we must reverse the
1566 i.rm.reg and i.rm.regmem fields. We accomplish
1567 this by pretending that the two register operands
1568 were given in the reverse order. */
1569 if (i
.tm
.opcode_modifier
& ReverseRegRegmem
)
1571 const reg_entry
*tmp
= i
.regs
[source
];
1572 i
.regs
[source
] = i
.regs
[dest
];
1577 /* We must be careful to make sure that all
1578 segment/control/test/debug/MMX registers go into
1579 the i.rm.reg field (despite whether they are
1580 source or destination operands). */
1581 if (i
.regs
[dest
]->reg_type
1582 & (SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
))
1584 i
.rm
.reg
= i
.regs
[dest
]->reg_num
;
1585 i
.rm
.regmem
= i
.regs
[source
]->reg_num
;
1589 i
.rm
.reg
= i
.regs
[source
]->reg_num
;
1590 i
.rm
.regmem
= i
.regs
[dest
]->reg_num
;
1594 { /* if it's not 2 reg operands... */
1597 unsigned int fake_zero_displacement
= 0;
1598 unsigned int op
= ((i
.types
[0] & AnyMem
)
1600 : (i
.types
[1] & AnyMem
) ? 1 : 2);
1607 if (! i
.disp_operands
)
1608 fake_zero_displacement
= 1;
1611 /* Operand is just <disp> */
1612 if (flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0))
1614 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
1615 i
.types
[op
] &= ~Disp
;
1616 i
.types
[op
] |= Disp16
;
1620 i
.rm
.regmem
= NO_BASE_REGISTER
;
1621 i
.types
[op
] &= ~Disp
;
1622 i
.types
[op
] |= Disp32
;
1625 else /* ! i.base_reg && i.index_reg */
1627 i
.sib
.index
= i
.index_reg
->reg_num
;
1628 i
.sib
.base
= NO_BASE_REGISTER
;
1629 i
.sib
.scale
= i
.log2_scale_factor
;
1630 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
1631 i
.types
[op
] &= ~Disp
;
1632 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
1635 else if (i
.base_reg
->reg_type
& Reg16
)
1637 switch (i
.base_reg
->reg_num
)
1642 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
1643 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
1650 if ((i
.types
[op
] & Disp
) == 0)
1652 /* fake (%bp) into 0(%bp) */
1653 i
.types
[op
] |= Disp8
;
1654 fake_zero_displacement
= 1;
1657 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
1658 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
1660 default: /* (%si) -> 4 or (%di) -> 5 */
1661 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
1663 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
1665 else /* i.base_reg and 32 bit mode */
1667 i
.rm
.regmem
= i
.base_reg
->reg_num
;
1668 i
.sib
.base
= i
.base_reg
->reg_num
;
1669 if (i
.base_reg
->reg_num
== EBP_REG_NUM
)
1672 if (i
.disp_operands
== 0)
1674 fake_zero_displacement
= 1;
1675 i
.types
[op
] |= Disp8
;
1678 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
1682 i
.sib
.scale
= i
.log2_scale_factor
;
1685 /* <disp>(%esp) becomes two byte modrm
1686 with no index register. We've already
1687 stored the code for esp in i.rm.regmem
1688 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
1689 base register besides %esp will not use
1690 the extra modrm byte. */
1691 i
.sib
.index
= NO_INDEX_REGISTER
;
1692 #if ! SCALE1_WHEN_NO_INDEX
1693 /* Another case where we force the second
1695 if (i
.log2_scale_factor
)
1696 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
1701 i
.sib
.index
= i
.index_reg
->reg_num
;
1702 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
1704 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
1707 if (fake_zero_displacement
)
1709 /* Fakes a zero displacement assuming that i.types[op]
1710 holds the correct displacement size. */
1711 exp
= &disp_expressions
[i
.disp_operands
++];
1713 exp
->X_op
= O_constant
;
1714 exp
->X_add_number
= 0;
1715 exp
->X_add_symbol
= (symbolS
*) 0;
1716 exp
->X_op_symbol
= (symbolS
*) 0;
1720 /* Fill in i.rm.reg or i.rm.regmem field with register
1721 operand (if any) based on i.tm.extension_opcode.
1722 Again, we must be careful to make sure that
1723 segment/control/debug/test/MMX registers are coded
1724 into the i.rm.reg field. */
1729 & (Reg
| SReg2
| SReg3
| Control
| Debug
1733 & (Reg
| SReg2
| SReg3
| Control
| Debug
1737 /* If there is an extension opcode to put here, the
1738 register number must be put into the regmem field. */
1739 if (i
.tm
.extension_opcode
!= None
)
1740 i
.rm
.regmem
= i
.regs
[op
]->reg_num
;
1742 i
.rm
.reg
= i
.regs
[op
]->reg_num
;
1744 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
1745 we must set it to 3 to indicate this is a register
1746 operand in the regmem field. */
1747 if (!i
.mem_operands
)
1751 /* Fill in i.rm.reg field with extension opcode (if any). */
1752 if (i
.tm
.extension_opcode
!= None
)
1753 i
.rm
.reg
= i
.tm
.extension_opcode
;
1756 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
1758 if (i
.tm
.base_opcode
== POP_SEG_SHORT
&& i
.regs
[0]->reg_num
== 1)
1760 as_bad (_("you can't `pop %%cs'"));
1763 i
.tm
.base_opcode
|= (i
.regs
[0]->reg_num
<< 3);
1765 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
1769 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
1771 /* For the string instructions that allow a segment override
1772 on one of their operands, the default segment is ds. */
1776 /* If a segment was explicitly specified,
1777 and the specified segment is not the default,
1778 use an opcode prefix to select it.
1779 If we never figured out what the default segment is,
1780 then default_seg will be zero at this point,
1781 and the specified segment prefix will always be used. */
1782 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
1784 if (! add_prefix (i
.seg
[0]->seg_prefix
))
1788 else if ((i
.tm
.opcode_modifier
& Ugh
) != 0)
1790 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc */
1791 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1795 /* Handle conversion of 'int $3' --> special int3 insn. */
1796 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.imms
[0]->X_add_number
== 3)
1798 i
.tm
.base_opcode
= INT3_OPCODE
;
1802 /* We are ready to output the insn. */
1807 if (i
.tm
.opcode_modifier
& Jump
)
1809 unsigned long n
= i
.disps
[0]->X_add_number
;
1810 int prefix
= (i
.prefix
[DATA_PREFIX
] != 0);
1818 if (flag_16bit_code
)
1821 if (i
.prefixes
!= 0)
1822 as_warn (_("skipping prefixes on this instruction"));
1824 if (i
.disps
[0]->X_op
== O_constant
)
1826 if (fits_in_signed_byte (n
))
1830 p
[0] = i
.tm
.base_opcode
;
1835 /* Use 16-bit jumps only for 16-bit code,
1836 because text segments are limited to 64K anyway;
1837 Use 32-bit jumps for 32-bit code, because they're faster,
1838 and a 16-bit jump will clear the top 16 bits of %eip. */
1839 int jmp_size
= code16
? 2 : 4;
1840 if (code16
&& !fits_in_signed_word (n
))
1842 as_bad (_("16-bit jump out of range"));
1846 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
1848 /* unconditional jump */
1849 insn_size
+= prefix
+ 1 + jmp_size
;
1850 p
= frag_more (prefix
+ 1 + jmp_size
);
1852 *p
++ = DATA_PREFIX_OPCODE
;
1854 md_number_to_chars (p
, (valueT
) n
, jmp_size
);
1858 /* conditional jump */
1859 insn_size
+= prefix
+ 2 + jmp_size
;
1860 p
= frag_more (prefix
+ 2 + jmp_size
);
1862 *p
++ = DATA_PREFIX_OPCODE
;
1863 *p
++ = TWO_BYTE_OPCODE_ESCAPE
;
1864 *p
++ = i
.tm
.base_opcode
+ 0x10;
1865 md_number_to_chars (p
, (valueT
) n
, jmp_size
);
1871 int size
= code16
? 2 : 4;
1873 /* It's a symbol; end frag & setup for relax.
1874 Make sure there are more than 6 chars left in the current frag;
1875 if not we'll have to start a new one. */
1876 frag_grow (prefix
+ 1 + 2 + size
);
1877 insn_size
+= 1 + prefix
;
1878 p
= frag_more (1 + prefix
);
1880 *p
++ = DATA_PREFIX_OPCODE
;
1881 *p
= i
.tm
.base_opcode
;
1882 frag_var (rs_machine_dependent
,
1883 prefix
+ 2 + size
, /* 2 opcode/prefix + displacement */
1885 ((unsigned char) *p
== JUMP_PC_RELATIVE
1886 ? ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
) | code16
1887 : ENCODE_RELAX_STATE (COND_JUMP
, SMALL
) | code16
),
1888 i
.disps
[0]->X_add_symbol
,
1892 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
1894 int size
= (i
.tm
.opcode_modifier
& JumpByte
) ? 1 : 4;
1895 unsigned long n
= i
.disps
[0]->X_add_number
;
1897 if (size
== 1) /* then this is a loop or jecxz type instruction */
1899 if (i
.prefix
[ADDR_PREFIX
])
1902 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
1910 if (i
.prefix
[DATA_PREFIX
])
1913 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
1917 if (flag_16bit_code
)
1924 if (i
.prefixes
!= 0)
1925 as_warn (_("skipping prefixes on this instruction"));
1927 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
1929 insn_size
+= 1 + size
;
1930 p
= frag_more (1 + size
);
1934 insn_size
+= 2 + size
; /* opcode can be at most two bytes */
1935 p
= frag_more (2 + size
);
1936 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
1938 *p
++ = i
.tm
.base_opcode
& 0xff;
1940 if (i
.disps
[0]->X_op
== O_constant
)
1942 if (size
== 1 && !fits_in_signed_byte (n
))
1944 as_bad (_("`%s' only takes byte displacement; %lu shortened to %d"),
1947 else if (size
== 2 && !fits_in_signed_word (n
))
1949 as_bad (_("16-bit jump out of range"));
1952 md_number_to_chars (p
, (valueT
) n
, size
);
1956 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
1957 i
.disps
[0], 1, reloc (size
, 1, i
.disp_reloc
[0]));
1961 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
1965 int prefix
= i
.prefix
[DATA_PREFIX
] != 0;
1973 if (flag_16bit_code
)
1977 reloc_type
= BFD_RELOC_32
;
1981 reloc_type
= BFD_RELOC_16
;
1984 if (i
.prefixes
!= 0)
1985 as_warn (_("skipping prefixes on this instruction"));
1987 insn_size
+= prefix
+ 1 + 2 + size
; /* 1 opcode; 2 segment; offset */
1988 p
= frag_more (prefix
+ 1 + 2 + size
);
1990 *p
++ = DATA_PREFIX_OPCODE
;
1991 *p
++ = i
.tm
.base_opcode
;
1992 if (i
.imms
[1]->X_op
== O_constant
)
1994 unsigned long n
= i
.imms
[1]->X_add_number
;
1995 if (size
== 2 && !fits_in_unsigned_word (n
))
1997 as_bad (_("16-bit jump out of range"));
2000 md_number_to_chars (p
, (valueT
) n
, size
);
2003 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2004 i
.imms
[1], 0, reloc_type
);
2005 if (i
.imms
[0]->X_op
!= O_constant
)
2006 as_bad (_("can't handle non absolute segment in `%s'"),
2008 md_number_to_chars (p
+ size
, (valueT
) i
.imms
[0]->X_add_number
, 2);
2012 /* Output normal instructions here. */
2015 /* The prefix bytes. */
2017 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2024 md_number_to_chars (p
, (valueT
) *q
, 1);
2028 /* Now the opcode; be careful about word order here! */
2029 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2032 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2034 else if (fits_in_unsigned_word (i
.tm
.base_opcode
))
2038 /* put out high byte first: can't use md_number_to_chars! */
2039 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2040 *p
= i
.tm
.base_opcode
& 0xff;
2043 { /* opcode is either 3 or 4 bytes */
2044 if (i
.tm
.base_opcode
& 0xff000000)
2048 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
2055 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
2056 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2057 *p
= (i
.tm
.base_opcode
) & 0xff;
2060 /* Now the modrm byte and sib byte (if present). */
2061 if (i
.tm
.opcode_modifier
& Modrm
)
2065 md_number_to_chars (p
,
2066 (valueT
) (i
.rm
.regmem
<< 0
2070 /* If i.rm.regmem == ESP (4)
2071 && i.rm.mode != (Register mode)
2073 ==> need second modrm byte. */
2074 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2076 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2080 md_number_to_chars (p
,
2081 (valueT
) (i
.sib
.base
<< 0
2083 | i
.sib
.scale
<< 6),
2088 if (i
.disp_operands
)
2090 register unsigned int n
;
2092 for (n
= 0; n
< i
.operands
; n
++)
2096 if (i
.disps
[n
]->X_op
== O_constant
)
2098 if (i
.types
[n
] & Disp8
)
2102 md_number_to_chars (p
,
2103 (valueT
) i
.disps
[n
]->X_add_number
,
2106 else if (i
.types
[n
] & Disp16
)
2110 md_number_to_chars (p
,
2111 (valueT
) i
.disps
[n
]->X_add_number
,
2118 md_number_to_chars (p
,
2119 (valueT
) i
.disps
[n
]->X_add_number
,
2123 else if (i
.types
[n
] & Disp32
)
2127 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4,
2129 TC_RELOC (i
.disp_reloc
[n
], BFD_RELOC_32
));
2132 { /* must be Disp16 */
2135 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
2137 TC_RELOC (i
.disp_reloc
[n
], BFD_RELOC_16
));
2141 } /* end displacement output */
2143 /* output immediate */
2146 register unsigned int n
;
2148 for (n
= 0; n
< i
.operands
; n
++)
2152 if (i
.imms
[n
]->X_op
== O_constant
)
2154 if (i
.types
[n
] & (Imm8
| Imm8S
))
2158 md_number_to_chars (p
,
2159 (valueT
) i
.imms
[n
]->X_add_number
,
2162 else if (i
.types
[n
] & Imm16
)
2166 md_number_to_chars (p
,
2167 (valueT
) i
.imms
[n
]->X_add_number
,
2174 md_number_to_chars (p
,
2175 (valueT
) i
.imms
[n
]->X_add_number
,
2180 { /* not absolute_section */
2181 /* Need a 32-bit fixup (don't support 8bit
2182 non-absolute ims). Try to support other
2188 if (i
.types
[n
] & (Imm8
| Imm8S
))
2190 else if (i
.types
[n
] & Imm16
)
2195 p
= frag_more (size
);
2196 r_type
= reloc (size
, 0, i
.disp_reloc
[0]);
2197 #ifdef BFD_ASSEMBLER
2198 if (r_type
== BFD_RELOC_32
2200 && GOT_symbol
== i
.imms
[n
]->X_add_symbol
2201 && (i
.imms
[n
]->X_op
== O_symbol
2202 || (i
.imms
[n
]->X_op
== O_add
2203 && (i
.imms
[n
]->X_op_symbol
->sy_value
.X_op
2206 r_type
= BFD_RELOC_386_GOTPC
;
2207 i
.imms
[n
]->X_add_number
+= 3;
2210 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2211 i
.imms
[n
], pcrel
, r_type
);
2215 } /* end immediate output */
2223 #endif /* DEBUG386 */
2227 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
2231 i386_operand (operand_string
)
2232 char *operand_string
;
2234 register char *op_string
= operand_string
;
2236 /* We check for an absolute prefix (differentiating,
2237 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
2238 if (*op_string
== ABSOLUTE_PREFIX
)
2241 if (is_space_char (*op_string
))
2243 i
.types
[this_operand
] |= JumpAbsolute
;
2246 /* Check if operand is a register. */
2247 if (*op_string
== REGISTER_PREFIX
)
2249 register const reg_entry
*r
;
2252 r
= parse_register (op_string
, &end_op
);
2255 /* Check for a segment override by searching for ':' after a
2256 segment register. */
2258 if (is_space_char (*op_string
))
2260 if ((r
->reg_type
& (SReg2
| SReg3
)) && *op_string
== ':')
2265 i
.seg
[i
.mem_operands
] = &es
;
2268 i
.seg
[i
.mem_operands
] = &cs
;
2271 i
.seg
[i
.mem_operands
] = &ss
;
2274 i
.seg
[i
.mem_operands
] = &ds
;
2277 i
.seg
[i
.mem_operands
] = &fs
;
2280 i
.seg
[i
.mem_operands
] = &gs
;
2284 /* Skip the ':' and whitespace. */
2286 if (is_space_char (*op_string
))
2289 operand_string
= op_string
; /* Pretend given string starts here. */
2290 if (!is_digit_char (*op_string
) && !is_identifier_char (*op_string
)
2291 && *op_string
!= '(' && *op_string
!= ABSOLUTE_PREFIX
)
2293 as_bad (_("bad memory operand `%s'"), op_string
);
2296 /* Handle case of %es:*foo. */
2297 if (*op_string
== ABSOLUTE_PREFIX
)
2300 if (is_space_char (*op_string
))
2302 i
.types
[this_operand
] |= JumpAbsolute
;
2304 goto do_memory_reference
;
2306 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
2307 i
.regs
[this_operand
] = r
;
2310 else if (*op_string
== IMMEDIATE_PREFIX
)
2311 { /* ... or an immediate */
2312 char *save_input_line_pointer
;
2316 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
2318 as_bad (_("only 1 or 2 immediate operands are allowed"));
2322 exp
= &im_expressions
[i
.imm_operands
++];
2323 i
.imms
[this_operand
] = exp
;
2326 if (is_space_char (*op_string
))
2329 save_input_line_pointer
= input_line_pointer
;
2330 input_line_pointer
= op_string
;
2331 exp_seg
= expression (exp
);
2332 if (*input_line_pointer
!= '\0')
2334 /* This should be as_bad, but some versions of gcc, up to
2335 about 2.8 and egcs 1.01, generate a bogus @GOTOFF(%ebx)
2336 in certain cases. Oddly, the code in question turns out
2337 to work correctly anyhow, so we make this just a warning
2338 until those versions of gcc are obsolete. */
2339 as_warn (_("unrecognized characters `%s' in expression"),
2340 input_line_pointer
);
2342 input_line_pointer
= save_input_line_pointer
;
2344 if (exp
->X_op
== O_absent
)
2346 /* missing or bad expr becomes absolute 0 */
2347 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
2349 exp
->X_op
= O_constant
;
2350 exp
->X_add_number
= 0;
2351 exp
->X_add_symbol
= (symbolS
*) 0;
2352 exp
->X_op_symbol
= (symbolS
*) 0;
2353 i
.types
[this_operand
] |= Imm
;
2355 else if (exp
->X_op
== O_constant
)
2357 i
.types
[this_operand
] |=
2358 smallest_imm_type ((long) exp
->X_add_number
);
2361 else if (exp_seg
!= text_section
2362 && exp_seg
!= data_section
2363 && exp_seg
!= bss_section
2364 && exp_seg
!= undefined_section
2365 #ifdef BFD_ASSEMBLER
2366 && ! bfd_is_com_section (exp_seg
)
2371 as_bad (_("Unimplemented segment type %d in parse_operand"), exp_seg
);
2377 /* This is an address. The size of the address will be
2378 determined later, depending on destination register,
2379 suffix, or the default for the section. We exclude
2380 Imm8S here so that `push $foo' and other instructions
2381 with an Imm8S form will use Imm16 or Imm32. */
2382 i
.types
[this_operand
] |= (Imm8
| Imm16
| Imm32
);
2385 else if (is_digit_char (*op_string
) || is_identifier_char (*op_string
)
2386 || *op_string
== '(')
2388 /* This is a memory reference of some sort. */
2389 char *end_of_operand_string
;
2390 register char *base_string
;
2391 int found_base_index_form
;
2393 /* Start and end of displacement string expression (if found). */
2394 char *displacement_string_start
;
2395 char *displacement_string_end
;
2397 do_memory_reference
:
2398 if ((i
.mem_operands
== 1
2399 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
2400 || i
.mem_operands
== 2)
2402 as_bad (_("too many memory references for `%s'"),
2403 current_templates
->start
->name
);
2407 /* Check for base index form. We detect the base index form by
2408 looking for an ')' at the end of the operand, searching
2409 for the '(' matching it, and finding a REGISTER_PREFIX or ','
2411 found_base_index_form
= 0;
2412 end_of_operand_string
= op_string
+ strlen (op_string
);
2414 --end_of_operand_string
;
2415 if (is_space_char (*end_of_operand_string
))
2416 --end_of_operand_string
;
2418 base_string
= end_of_operand_string
;
2419 if (*base_string
== ')')
2421 unsigned int parens_balanced
= 1;
2422 /* We've already checked that the number of left & right ()'s are
2423 equal, so this loop will not be infinite. */
2427 if (*base_string
== ')')
2429 if (*base_string
== '(')
2432 while (parens_balanced
);
2434 /* If there is a displacement set-up for it to be parsed later. */
2435 displacement_string_start
= op_string
;
2436 displacement_string_end
= base_string
;
2438 /* Skip past '(' and whitespace. */
2440 if (is_space_char (*base_string
))
2443 if (*base_string
== REGISTER_PREFIX
|| *base_string
== ',')
2444 found_base_index_form
= 1;
2447 /* If we can't parse a base index register expression, we've found
2448 a pure displacement expression. We set up displacement_string_start
2449 and displacement_string_end for the code below. */
2450 if (!found_base_index_form
)
2452 displacement_string_start
= op_string
;
2453 displacement_string_end
= end_of_operand_string
+ 1;
2457 i
.types
[this_operand
] |= BaseIndex
;
2459 /* Find base register (if any). */
2460 if (*base_string
!= ',')
2464 /* Trim off the closing ')' so that parse_register won't
2466 END_STRING_AND_SAVE (end_of_operand_string
);
2467 i
.base_reg
= parse_register (base_string
, &end_op
);
2468 if (i
.base_reg
== NULL
)
2470 RESTORE_END_STRING (end_of_operand_string
);
2473 RESTORE_END_STRING (end_of_operand_string
);
2474 base_string
= end_op
;
2475 if (is_space_char (*base_string
))
2479 /* There may be an index reg or scale factor here. */
2480 if (*base_string
== ',')
2483 if (is_space_char (*base_string
))
2486 if (*base_string
== REGISTER_PREFIX
)
2490 END_STRING_AND_SAVE (end_of_operand_string
);
2491 i
.index_reg
= parse_register (base_string
, &end_op
);
2492 RESTORE_END_STRING (end_of_operand_string
);
2494 if (i
.index_reg
== NULL
)
2497 base_string
= end_op
;
2498 if (is_space_char (*base_string
))
2500 if (*base_string
== ',')
2503 if (is_space_char (*base_string
))
2506 else if (*base_string
!= ')')
2508 as_bad (_("expecting `,' or `)' after index register in `%s'"),
2514 /* Check for scale factor. */
2515 if (isdigit ((unsigned char) *base_string
))
2517 if (isdigit ((unsigned char) base_string
[1]))
2518 goto bad_scale
; /* must be 1 digit scale */
2519 switch (*base_string
)
2522 i
.log2_scale_factor
= 0;
2525 i
.log2_scale_factor
= 1;
2528 i
.log2_scale_factor
= 2;
2531 i
.log2_scale_factor
= 3;
2535 as_bad (_("expecting scale factor of 1, 2, 4 or 8; got `%s'"),
2541 if (is_space_char (*base_string
))
2543 if (*base_string
!= ')')
2545 as_bad (_("expecting `)' after scale factor in `%s'"),
2549 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
2551 as_warn (_("scale factor of %d without an index register"),
2552 1 << i
.log2_scale_factor
);
2553 #if SCALE1_WHEN_NO_INDEX
2554 i
.log2_scale_factor
= 0;
2558 else if (!i
.index_reg
)
2560 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
2565 else if (*base_string
!= ')')
2567 as_bad (_("expecting `,' or `)' after base register in `%s'"),
2573 /* If there's an expression begining the operand, parse it,
2574 assuming displacement_string_start and
2575 displacement_string_end are meaningful. */
2576 if (displacement_string_start
!= displacement_string_end
)
2578 register expressionS
*exp
;
2580 char *save_input_line_pointer
;
2581 int bigdisp
= Disp32
;
2583 if (flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0))
2585 i
.types
[this_operand
] |= bigdisp
;
2587 exp
= &disp_expressions
[i
.disp_operands
];
2588 i
.disps
[this_operand
] = exp
;
2589 i
.disp_reloc
[this_operand
] = NO_RELOC
;
2591 save_input_line_pointer
= input_line_pointer
;
2592 input_line_pointer
= displacement_string_start
;
2593 END_STRING_AND_SAVE (displacement_string_end
);
2594 #ifndef GCC_ASM_O_HACK
2595 #define GCC_ASM_O_HACK 0
2598 END_STRING_AND_SAVE (displacement_string_end
+ 1);
2599 if ((i
.types
[this_operand
] & BaseIndex
) != 0
2600 && displacement_string_end
[-1] == '+')
2602 /* This hack is to avoid a warning when using the "o"
2603 constraint within gcc asm statements.
2606 #define _set_tssldt_desc(n,addr,limit,type) \
2607 __asm__ __volatile__ ( \
2609 "movw %w1,2+%0\n\t" \
2611 "movb %b1,4+%0\n\t" \
2612 "movb %4,5+%0\n\t" \
2613 "movb $0,6+%0\n\t" \
2614 "movb %h1,7+%0\n\t" \
2616 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
2618 This works great except that the output assembler ends
2619 up looking a bit weird if it turns out that there is
2620 no offset. You end up producing code that looks like:
2633 So here we provide the missing zero.
2636 *displacement_string_end
= '0';
2642 * We can have operands of the form
2643 * <symbol>@GOTOFF+<nnn>
2644 * Take the easy way out here and copy everything
2645 * into a temporary buffer...
2649 cp
= strchr (input_line_pointer
, '@');
2654 if (GOT_symbol
== NULL
)
2655 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
2657 tmpbuf
= (char *) alloca ((cp
- input_line_pointer
) + 20);
2659 if (strncmp (cp
+ 1, "PLT", 3) == 0)
2661 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
2663 strcpy (tmpbuf
, input_line_pointer
);
2664 strcat (tmpbuf
, cp
+ 1 + 3);
2667 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
2669 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
2671 strcpy (tmpbuf
, input_line_pointer
);
2672 strcat (tmpbuf
, cp
+ 1 + 6);
2675 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
2677 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
2679 strcpy (tmpbuf
, input_line_pointer
);
2680 strcat (tmpbuf
, cp
+ 1 + 3);
2684 as_bad (_("Bad reloc specifier `%s' in expression"), cp
+ 1);
2686 /* GOT relocations are not supported in 16 bit mode */
2687 if (flag_16bit_code
)
2688 as_bad (_("GOT relocations not supported in 16 bit mode"));
2690 input_line_pointer
= tmpbuf
;
2695 exp_seg
= expression (exp
);
2697 #ifdef BFD_ASSEMBLER
2698 /* We do this to make sure that the section symbol is in
2699 the symbol table. We will ultimately change the relocation
2700 to be relative to the beginning of the section */
2701 if (i
.disp_reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
)
2703 if (S_IS_LOCAL(exp
->X_add_symbol
)
2704 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
2705 section_symbol(exp
->X_add_symbol
->bsym
->section
);
2706 assert (exp
->X_op
== O_symbol
);
2707 exp
->X_op
= O_subtract
;
2708 exp
->X_op_symbol
= GOT_symbol
;
2709 i
.disp_reloc
[this_operand
] = BFD_RELOC_32
;
2713 if (*input_line_pointer
)
2714 as_bad (_("Ignoring junk `%s' after expression"),
2715 input_line_pointer
);
2717 RESTORE_END_STRING (displacement_string_end
+ 1);
2719 RESTORE_END_STRING (displacement_string_end
);
2720 input_line_pointer
= save_input_line_pointer
;
2722 #if 0 /* this is handled in expr. */
2723 if (exp
->X_op
== O_absent
)
2725 /* missing expr becomes absolute 0 */
2726 as_bad (_("missing or invalid displacement `%s' taken as 0"),
2728 exp
->X_op
= O_constant
;
2729 exp
->X_add_number
= 0;
2730 exp
->X_add_symbol
= (symbolS
*) 0;
2731 exp
->X_op_symbol
= (symbolS
*) 0;
2732 i
.types
[this_operand
] |= Disp8
;
2736 if (exp
->X_op
== O_constant
)
2738 if (fits_in_signed_byte (exp
->X_add_number
))
2739 i
.types
[this_operand
] |= Disp8
;
2742 else if (exp_seg
!= text_section
2743 && exp_seg
!= data_section
2744 && exp_seg
!= bss_section
2745 && exp_seg
!= undefined_section
)
2747 goto seg_unimplemented
;
2752 /* Special case for (%dx) while doing input/output op. */
2754 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
2756 && i
.log2_scale_factor
== 0
2757 && i
.seg
[i
.mem_operands
] == 0
2758 && (i
.types
[this_operand
] & Disp
) == 0)
2760 i
.types
[this_operand
] = InOutPortReg
;
2763 /* Make sure the memory operand we've been dealt is valid. */
2764 if (flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0))
2767 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
))
2768 != (Reg16
|BaseIndex
)))
2770 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
2771 != (Reg16
|BaseIndex
))
2773 && i
.base_reg
->reg_num
< 6
2774 && i
.index_reg
->reg_num
>= 6
2775 && i
.log2_scale_factor
== 0))))
2777 as_bad (_("`%s' is not a valid %s bit base/index expression"),
2778 operand_string
, "16");
2785 && (i
.base_reg
->reg_type
& Reg32
) == 0)
2787 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
))
2788 != (Reg32
|BaseIndex
))))
2790 as_bad (_("`%s' is not a valid %s bit base/index expression"),
2791 operand_string
, "32");
2798 { /* it's not a memory operand; argh! */
2799 as_bad (_("invalid char %s begining operand %d `%s'"),
2800 output_invalid (*op_string
),
2805 return 1; /* normal return */
2809 * md_estimate_size_before_relax()
2811 * Called just before relax().
2812 * Any symbol that is now undefined will not become defined.
2813 * Return the correct fr_subtype in the frag.
2814 * Return the initial "guess for fr_var" to caller.
2815 * The guess for fr_var is ACTUALLY the growth beyond fr_fix.
2816 * Whatever we do to grow fr_fix or fr_var contributes to our returned value.
2817 * Although it may not be explicit in the frag, pretend fr_var starts with a
2821 md_estimate_size_before_relax (fragP
, segment
)
2822 register fragS
*fragP
;
2823 register segT segment
;
2825 register unsigned char *opcode
;
2826 register int old_fr_fix
;
2828 old_fr_fix
= fragP
->fr_fix
;
2829 opcode
= (unsigned char *) fragP
->fr_opcode
;
2830 /* We've already got fragP->fr_subtype right; all we have to do is
2831 check for un-relaxable symbols. */
2832 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
)
2834 /* symbol is undefined in this segment */
2835 int code16
= fragP
->fr_subtype
& CODE16
;
2836 int size
= code16
? 2 : 4;
2837 int pcrel_reloc
= code16
? BFD_RELOC_16_PCREL
: BFD_RELOC_32_PCREL
;
2841 case JUMP_PC_RELATIVE
: /* make jmp (0xeb) a dword displacement jump */
2842 opcode
[0] = 0xe9; /* dword disp jmp */
2843 fragP
->fr_fix
+= size
;
2844 fix_new (fragP
, old_fr_fix
, size
,
2846 fragP
->fr_offset
, 1,
2847 (GOT_symbol
&& /* Not quite right - we should switch on
2848 presence of @PLT, but I cannot see how
2849 to get to that from here. We should have
2850 done this in md_assemble to really
2851 get it right all of the time, but I
2852 think it does not matter that much, as
2853 this will be right most of the time. ERY*/
2854 S_GET_SEGMENT(fragP
->fr_symbol
) == undefined_section
)
2855 ? BFD_RELOC_386_PLT32
: pcrel_reloc
);
2859 /* This changes the byte-displacement jump 0x7N -->
2860 the dword-displacement jump 0x0f8N */
2861 opcode
[1] = opcode
[0] + 0x10;
2862 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
; /* two-byte escape */
2863 fragP
->fr_fix
+= 1 + size
; /* we've added an opcode byte */
2864 fix_new (fragP
, old_fr_fix
+ 1, size
,
2866 fragP
->fr_offset
, 1,
2867 (GOT_symbol
&& /* Not quite right - we should switch on
2868 presence of @PLT, but I cannot see how
2869 to get to that from here. ERY */
2870 S_GET_SEGMENT(fragP
->fr_symbol
) == undefined_section
)
2871 ? BFD_RELOC_386_PLT32
: pcrel_reloc
);
2876 return (fragP
->fr_var
+ fragP
->fr_fix
- old_fr_fix
);
2877 } /* md_estimate_size_before_relax() */
2880 * md_convert_frag();
2882 * Called after relax() is finished.
2883 * In: Address of frag.
2884 * fr_type == rs_machine_dependent.
2885 * fr_subtype is what the address relaxed to.
2887 * Out: Any fixSs and constants are set up.
2888 * Caller will turn frag into a ".space 0".
2890 #ifndef BFD_ASSEMBLER
2892 md_convert_frag (headers
, sec
, fragP
)
2893 object_headers
*headers
;
2895 register fragS
*fragP
;
2898 md_convert_frag (abfd
, sec
, fragP
)
2901 register fragS
*fragP
;
2904 register unsigned char *opcode
;
2905 unsigned char *where_to_put_displacement
= NULL
;
2906 unsigned int target_address
;
2907 unsigned int opcode_address
;
2908 unsigned int extension
= 0;
2909 int displacement_from_opcode_start
;
2911 opcode
= (unsigned char *) fragP
->fr_opcode
;
2913 /* Address we want to reach in file space. */
2914 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
2915 #ifdef BFD_ASSEMBLER /* not needed otherwise? */
2916 target_address
+= fragP
->fr_symbol
->sy_frag
->fr_address
;
2919 /* Address opcode resides at in file space. */
2920 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
2922 /* Displacement from opcode start to fill into instruction. */
2923 displacement_from_opcode_start
= target_address
- opcode_address
;
2925 switch (fragP
->fr_subtype
)
2927 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL
):
2928 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL16
):
2929 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
):
2930 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL16
):
2931 /* don't have to change opcode */
2932 extension
= 1; /* 1 opcode + 1 displacement */
2933 where_to_put_displacement
= &opcode
[1];
2936 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
2937 extension
= 5; /* 2 opcode + 4 displacement */
2938 opcode
[1] = opcode
[0] + 0x10;
2939 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
2940 where_to_put_displacement
= &opcode
[2];
2943 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
2944 extension
= 4; /* 1 opcode + 4 displacement */
2946 where_to_put_displacement
= &opcode
[1];
2949 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
2950 extension
= 3; /* 2 opcode + 2 displacement */
2951 opcode
[1] = opcode
[0] + 0x10;
2952 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
2953 where_to_put_displacement
= &opcode
[2];
2956 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
2957 extension
= 2; /* 1 opcode + 2 displacement */
2959 where_to_put_displacement
= &opcode
[1];
2963 BAD_CASE (fragP
->fr_subtype
);
2966 /* now put displacement after opcode */
2967 md_number_to_chars ((char *) where_to_put_displacement
,
2968 (valueT
) (displacement_from_opcode_start
- extension
),
2969 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
2970 fragP
->fr_fix
+= extension
;
2974 int md_short_jump_size
= 2; /* size of byte displacement jmp */
2975 int md_long_jump_size
= 5; /* size of dword displacement jmp */
2976 const int md_reloc_size
= 8; /* Size of relocation record */
2979 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
2981 addressT from_addr
, to_addr
;
2987 offset
= to_addr
- (from_addr
+ 2);
2988 md_number_to_chars (ptr
, (valueT
) 0xeb, 1); /* opcode for byte-disp jump */
2989 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
2993 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
2995 addressT from_addr
, to_addr
;
3001 if (flag_do_long_jump
)
3003 offset
= to_addr
- S_GET_VALUE (to_symbol
);
3004 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);/* opcode for long jmp */
3005 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
3006 fix_new (frag
, (ptr
+ 1) - frag
->fr_literal
, 4,
3007 to_symbol
, (offsetT
) 0, 0, BFD_RELOC_32
);
3011 offset
= to_addr
- (from_addr
+ 5);
3012 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
3013 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
3017 /* Apply a fixup (fixS) to segment data, once it has been determined
3018 by our caller that we have all the info we need to fix it up.
3020 On the 386, immediates, displacements, and data pointers are all in
3021 the same (little-endian) format, so we don't need to care about which
3025 md_apply_fix3 (fixP
, valp
, seg
)
3026 fixS
*fixP
; /* The fix we're to put in. */
3027 valueT
*valp
; /* Pointer to the value of the bits. */
3028 segT seg
; /* Segment fix is from. */
3030 register char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3031 valueT value
= *valp
;
3033 if (fixP
->fx_r_type
== BFD_RELOC_32
&& fixP
->fx_pcrel
)
3034 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
3036 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
3038 * This is a hack. There should be a better way to
3041 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
&& fixP
->fx_addsy
)
3044 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
3045 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
)
3046 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3048 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3049 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
3050 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
3051 || (fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) != 0)
3052 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
3053 && ! S_IS_WEAK (fixP
->fx_addsy
)
3054 && S_IS_DEFINED (fixP
->fx_addsy
)
3055 && ! S_IS_COMMON (fixP
->fx_addsy
))
3057 /* Yes, we add the values in twice. This is because
3058 bfd_perform_relocation subtracts them out again. I think
3059 bfd_perform_relocation is broken, but I don't dare change
3061 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3064 #if defined (OBJ_COFF) && defined (TE_PE)
3065 /* For some reason, the PE format does not store a section
3066 address offset for a PC relative symbol. */
3067 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
3068 value
+= md_pcrel_from (fixP
);
3072 /* Fix a few things - the dynamic linker expects certain values here,
3073 and we must not dissappoint it. */
3074 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3075 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
3077 switch (fixP
->fx_r_type
) {
3078 case BFD_RELOC_386_PLT32
:
3079 /* Make the jump instruction point to the address of the operand. At
3080 runtime we merely add the offset to the actual PLT entry. */
3083 case BFD_RELOC_386_GOTPC
:
3085 * This is tough to explain. We end up with this one if we have
3086 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
3087 * here is to obtain the absolute address of the GOT, and it is strongly
3088 * preferable from a performance point of view to avoid using a runtime
3089 * relocation for this. The actual sequence of instructions often look
3095 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3097 * The call and pop essentially return the absolute address of
3098 * the label .L66 and store it in %ebx. The linker itself will
3099 * ultimately change the first operand of the addl so that %ebx points to
3100 * the GOT, but to keep things simple, the .o file must have this operand
3101 * set so that it generates not the absolute address of .L66, but the
3102 * absolute address of itself. This allows the linker itself simply
3103 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
3104 * added in, and the addend of the relocation is stored in the operand
3105 * field for the instruction itself.
3107 * Our job here is to fix the operand so that it would add the correct
3108 * offset so that %ebx would point to itself. The thing that is tricky is
3109 * that .-.L66 will point to the beginning of the instruction, so we need
3110 * to further modify the operand so that it will point to itself.
3111 * There are other cases where you have something like:
3113 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3115 * and here no correction would be required. Internally in the assembler
3116 * we treat operands of this form as not being pcrel since the '.' is
3117 * explicitly mentioned, and I wonder whether it would simplify matters
3118 * to do it this way. Who knows. In earlier versions of the PIC patches,
3119 * the pcrel_adjust field was used to store the correction, but since the
3120 * expression is not pcrel, I felt it would be confusing to do it this way.
3124 case BFD_RELOC_386_GOT32
:
3125 value
= 0; /* Fully resolved at runtime. No addend. */
3127 case BFD_RELOC_386_GOTOFF
:
3136 md_number_to_chars (p
, value
, fixP
->fx_size
);
3142 /* This is never used. */
3143 long /* Knows about the byte order in a word. */
3144 md_chars_to_number (con
, nbytes
)
3145 unsigned char con
[]; /* Low order byte 1st. */
3146 int nbytes
; /* Number of bytes in the input. */
3149 for (retval
= 0, con
+= nbytes
- 1; nbytes
--; con
--)
3151 retval
<<= BITS_PER_CHAR
;
3159 #define MAX_LITTLENUMS 6
3161 /* Turn the string pointed to by litP into a floating point constant of type
3162 type, and emit the appropriate bytes. The number of LITTLENUMS emitted
3163 is stored in *sizeP . An error message is returned, or NULL on OK. */
3165 md_atof (type
, litP
, sizeP
)
3171 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
3172 LITTLENUM_TYPE
*wordP
;
3194 return _("Bad call to md_atof ()");
3196 t
= atof_ieee (input_line_pointer
, type
, words
);
3198 input_line_pointer
= t
;
3200 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
3201 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
3202 the bigendian 386. */
3203 for (wordP
= words
+ prec
- 1; prec
--;)
3205 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
3206 litP
+= sizeof (LITTLENUM_TYPE
);
3211 char output_invalid_buf
[8];
3218 sprintf (output_invalid_buf
, "'%c'", c
);
3220 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
3221 return output_invalid_buf
;
3224 /* REG_STRING starts *before* REGISTER_PREFIX. */
3226 static const reg_entry
*
3227 parse_register (reg_string
, end_op
)
3231 register char *s
= reg_string
;
3233 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
3236 /* Skip REGISTER_PREFIX and possible whitespace. */
3238 if (is_space_char (*s
))
3242 while ((*p
++ = register_chars
[(unsigned char) *s
++]) != '\0')
3244 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
3247 as_bad (_("bad register name `%s'"), reg_name_given
);
3248 return (const reg_entry
*) NULL
;
3254 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
3258 as_bad (_("bad register name `%s'"), reg_name_given
);
3259 return (const reg_entry
*) NULL
;
3266 CONST
char *md_shortopts
= "kmVQ:";
3268 CONST
char *md_shortopts
= "m";
3270 struct option md_longopts
[] = {
3271 {NULL
, no_argument
, NULL
, 0}
3273 size_t md_longopts_size
= sizeof (md_longopts
);
3276 md_parse_option (c
, arg
)
3283 flag_do_long_jump
= 1;
3286 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3287 /* -k: Ignore for FreeBSD compatibility. */
3291 /* -V: SVR4 argument to print version ID. */
3293 print_version_id ();
3296 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
3297 should be emitted or not. FIXME: Not implemented. */
3309 md_show_usage (stream
)
3312 fprintf (stream
, _("\
3313 -m do long jump\n"));
3316 #ifdef BFD_ASSEMBLER
3317 #ifdef OBJ_MAYBE_ELF
3318 #ifdef OBJ_MAYBE_COFF
3320 /* Pick the target format to use. */
3323 i386_target_format ()
3325 switch (OUTPUT_FLAVOR
)
3327 case bfd_target_coff_flavour
:
3329 case bfd_target_elf_flavour
:
3330 return "elf32-i386";
3337 #endif /* OBJ_MAYBE_COFF */
3338 #endif /* OBJ_MAYBE_ELF */
3339 #endif /* BFD_ASSEMBLER */
3343 md_undefined_symbol (name
)
3346 if (*name
== '_' && *(name
+1) == 'G'
3347 && strcmp(name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
3351 if (symbol_find (name
))
3352 as_bad (_("GOT already in symbol table"));
3353 GOT_symbol
= symbol_new (name
, undefined_section
,
3354 (valueT
) 0, &zero_address_frag
);
3361 /* Round up a section size to the appropriate boundary. */
3363 md_section_align (segment
, size
)
3368 #ifdef BFD_ASSEMBLER
3369 /* For a.out, force the section size to be aligned. If we don't do
3370 this, BFD will align it for us, but it will not write out the
3371 final bytes of the section. This may be a bug in BFD, but it is
3372 easier to fix it here since that is how the other a.out targets
3376 align
= bfd_get_section_alignment (stdoutput
, segment
);
3377 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
3384 /* On the i386, PC-relative offsets are relative to the start of the
3385 next instruction. That is, the address of the offset, plus its
3386 size, since the offset is always the last part of the insn. */
3389 md_pcrel_from (fixP
)
3392 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3403 temp
= get_absolute_expression ();
3404 subseg_set (bss_section
, (subsegT
) temp
);
3405 demand_empty_rest_of_line ();
3411 #ifdef BFD_ASSEMBLER
3414 i386_validate_fix (fixp
)
3417 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
3419 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
3424 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
3425 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
3428 tc_gen_reloc (section
, fixp
)
3433 bfd_reloc_code_real_type code
;
3435 switch (fixp
->fx_r_type
)
3437 case BFD_RELOC_386_PLT32
:
3438 case BFD_RELOC_386_GOT32
:
3439 case BFD_RELOC_386_GOTOFF
:
3440 case BFD_RELOC_386_GOTPC
:
3442 code
= fixp
->fx_r_type
;
3445 switch (F (fixp
->fx_size
, fixp
->fx_pcrel
))
3447 MAP (1, 0, BFD_RELOC_8
);
3448 MAP (2, 0, BFD_RELOC_16
);
3449 MAP (4, 0, BFD_RELOC_32
);
3450 MAP (1, 1, BFD_RELOC_8_PCREL
);
3451 MAP (2, 1, BFD_RELOC_16_PCREL
);
3452 MAP (4, 1, BFD_RELOC_32_PCREL
);
3455 as_bad (_("Can not do %d byte pc-relative relocation"),
3458 as_bad (_("Can not do %d byte relocation"), fixp
->fx_size
);
3459 code
= BFD_RELOC_32
;
3467 if (code
== BFD_RELOC_32
3469 && fixp
->fx_addsy
== GOT_symbol
)
3470 code
= BFD_RELOC_386_GOTPC
;
3472 rel
= (arelent
*) xmalloc (sizeof (arelent
));
3473 rel
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
3474 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3476 rel
->addend
= fixp
->fx_addnumber
;
3480 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3481 if (rel
->howto
== NULL
)
3483 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3484 _("Cannot represent relocation type %s"),
3485 bfd_get_reloc_code_name (code
));
3486 /* Set howto to a garbage value so that we can keep going. */
3487 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
3488 assert (rel
->howto
!= NULL
);
3494 #else /* ! BFD_ASSEMBLER */
3496 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
3498 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
3501 relax_addressT segment_address_in_file
;
3504 * In: length of relocation (or of address) in chars: 1, 2 or 4.
3505 * Out: GNU LD relocation length code: 0, 1, or 2.
3508 static const unsigned char nbytes_r_length
[] = {42, 0, 1, 42, 2};
3511 know (fixP
->fx_addsy
!= NULL
);
3513 md_number_to_chars (where
,
3514 (valueT
) (fixP
->fx_frag
->fr_address
3515 + fixP
->fx_where
- segment_address_in_file
),
3518 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
3519 ? S_GET_TYPE (fixP
->fx_addsy
)
3520 : fixP
->fx_addsy
->sy_number
);
3522 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
3523 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
3524 where
[4] = r_symbolnum
& 0x0ff;
3525 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
3526 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
3527 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
3530 #endif /* OBJ_AOUT or OBJ_BOUT */
3532 #if defined (I386COFF)
3535 tc_coff_fix2rtype (fixP
)
3538 if (fixP
->fx_r_type
== R_IMAGEBASE
)
3541 return (fixP
->fx_pcrel
?
3542 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
3543 fixP
->fx_size
== 2 ? R_PCRWORD
:
3545 (fixP
->fx_size
== 1 ? R_RELBYTE
:
3546 fixP
->fx_size
== 2 ? R_RELWORD
:
3551 tc_coff_sizemachdep (frag
)
3555 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
3560 #endif /* I386COFF */
3562 #endif /* BFD_ASSEMBLER? */
3564 /* end of tc-i386.c */