1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const template *start
;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem
; /* codes register or memory operand */
109 unsigned int reg
; /* codes register operand (or extended opcode) */
110 unsigned int mode
; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte
;
117 /* The SSE5 instructions have a two bit instruction modifier (OC) that
118 is stored in two separate bytes in the instruction. Pick apart OC
119 into the 2 separate bits for instruction. */
120 #define DREX_OC0(x) (((x) & 1) != 0)
121 #define DREX_OC1(x) (((x) & 2) != 0)
123 #define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
124 #define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
127 #define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
128 #define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
129 #define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
130 #define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
132 #define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
133 #define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
135 /* Information needed to create the DREX byte in SSE5 instructions. */
138 unsigned int reg
; /* register */
139 unsigned int rex
; /* REX flags */
140 unsigned int modrm_reg
; /* which arg goes in the modrm.reg field */
141 unsigned int modrm_regmem
; /* which arg goes in the modrm.regmem field */
144 /* 386 opcode byte to code indirect addressing. */
153 /* x86 arch names, types and features */
156 const char *name
; /* arch name */
157 enum processor_type type
; /* arch type */
158 i386_cpu_flags flags
; /* cpu feature flags */
162 static void set_code_flag (int);
163 static void set_16bit_gcc_code_flag (int);
164 static void set_intel_syntax (int);
165 static void set_intel_mnemonic (int);
166 static void set_allow_index_reg (int);
167 static void set_sse_check (int);
168 static void set_cpu_arch (int);
170 static void pe_directive_secrel (int);
172 static void signed_cons (int);
173 static char *output_invalid (int c
);
174 static int i386_att_operand (char *);
175 static int i386_intel_operand (char *, int);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static void optimize_imm (void);
182 static void optimize_disp (void);
183 static const template *match_template (void);
184 static int check_string (void);
185 static int process_suffix (void);
186 static int check_byte_reg (void);
187 static int check_long_reg (void);
188 static int check_qword_reg (void);
189 static int check_word_reg (void);
190 static int finalize_imm (void);
191 static void process_drex (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
204 static const char *default_arch
= DEFAULT_ARCH
;
209 /* VEX prefix is either 2 byte or 3 byte. */
210 unsigned char bytes
[3];
212 /* Destination or source register specifier. */
213 const reg_entry
*register_specifier
;
216 /* 'md_assemble ()' gathers together information and puts it into a
223 const reg_entry
*regs
;
228 /* TM holds the template for the insn were currently assembling. */
231 /* SUFFIX holds the instruction size suffix for byte, word, dword
232 or qword, if given. */
235 /* OPERANDS gives the number of given operands. */
236 unsigned int operands
;
238 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
239 of given register, displacement, memory operands and immediate
241 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
243 /* TYPES [i] is the type (see above #defines) which tells us how to
244 use OP[i] for the corresponding operand. */
245 i386_operand_type types
[MAX_OPERANDS
];
247 /* Displacement expression, immediate expression, or register for each
249 union i386_op op
[MAX_OPERANDS
];
251 /* Flags for operands. */
252 unsigned int flags
[MAX_OPERANDS
];
253 #define Operand_PCrel 1
255 /* Relocation type for operand */
256 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
258 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
259 the base index byte below. */
260 const reg_entry
*base_reg
;
261 const reg_entry
*index_reg
;
262 unsigned int log2_scale_factor
;
264 /* SEG gives the seg_entries of this insn. They are zero unless
265 explicit segment overrides are given. */
266 const seg_entry
*seg
[2];
268 /* PREFIX holds all the given prefix opcodes (usually null).
269 PREFIXES is the number of prefix opcodes. */
270 unsigned int prefixes
;
271 unsigned char prefix
[MAX_PREFIXES
];
273 /* RM and SIB are the modrm byte and the sib byte where the
274 addressing modes of this insn are encoded. DREX is the byte
275 added by the SSE5 instructions. */
283 /* Swap operand in encoding. */
284 unsigned int swap_operand
: 1;
287 typedef struct _i386_insn i386_insn
;
289 /* List of chars besides those in app.c:symbol_chars that can start an
290 operand. Used to prevent the scrubber eating vital white-space. */
291 const char extra_symbol_chars
[] = "*%-(["
300 #if (defined (TE_I386AIX) \
301 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
302 && !defined (TE_GNU) \
303 && !defined (TE_LINUX) \
304 && !defined (TE_NETWARE) \
305 && !defined (TE_FreeBSD) \
306 && !defined (TE_NetBSD)))
307 /* This array holds the chars that always start a comment. If the
308 pre-processor is disabled, these aren't very useful. The option
309 --divide will remove '/' from this list. */
310 const char *i386_comment_chars
= "#/";
311 #define SVR4_COMMENT_CHARS 1
312 #define PREFIX_SEPARATOR '\\'
315 const char *i386_comment_chars
= "#";
316 #define PREFIX_SEPARATOR '/'
319 /* This array holds the chars that only start a comment at the beginning of
320 a line. If the line seems to have the form '# 123 filename'
321 .line and .file directives will appear in the pre-processed output.
322 Note that input_file.c hand checks for '#' at the beginning of the
323 first line of the input file. This is because the compiler outputs
324 #NO_APP at the beginning of its output.
325 Also note that comments started like this one will always work if
326 '/' isn't otherwise defined. */
327 const char line_comment_chars
[] = "#/";
329 const char line_separator_chars
[] = ";";
331 /* Chars that can be used to separate mant from exp in floating point
333 const char EXP_CHARS
[] = "eE";
335 /* Chars that mean this number is a floating point constant
338 const char FLT_CHARS
[] = "fFdDxX";
340 /* Tables for lexical analysis. */
341 static char mnemonic_chars
[256];
342 static char register_chars
[256];
343 static char operand_chars
[256];
344 static char identifier_chars
[256];
345 static char digit_chars
[256];
347 /* Lexical macros. */
348 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
349 #define is_operand_char(x) (operand_chars[(unsigned char) x])
350 #define is_register_char(x) (register_chars[(unsigned char) x])
351 #define is_space_char(x) ((x) == ' ')
352 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
353 #define is_digit_char(x) (digit_chars[(unsigned char) x])
355 /* All non-digit non-letter characters that may occur in an operand. */
356 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
358 /* md_assemble() always leaves the strings it's passed unaltered. To
359 effect this we maintain a stack of saved characters that we've smashed
360 with '\0's (indicating end of strings for various sub-fields of the
361 assembler instruction). */
362 static char save_stack
[32];
363 static char *save_stack_p
;
364 #define END_STRING_AND_SAVE(s) \
365 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
366 #define RESTORE_END_STRING(s) \
367 do { *(s) = *--save_stack_p; } while (0)
369 /* The instruction we're assembling. */
372 /* Possible templates for current insn. */
373 static const templates
*current_templates
;
375 /* Per instruction expressionS buffers: max displacements & immediates. */
376 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
377 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
379 /* Current operand we are working on. */
380 static int this_operand
;
382 /* We support four different modes. FLAG_CODE variable is used to distinguish
390 static enum flag_code flag_code
;
391 static unsigned int object_64bit
;
392 static int use_rela_relocations
= 0;
394 /* The names used to print error messages. */
395 static const char *flag_code_names
[] =
402 /* 1 for intel syntax,
404 static int intel_syntax
= 0;
406 /* 1 for intel mnemonic,
407 0 if att mnemonic. */
408 static int intel_mnemonic
= !SYSV386_COMPAT
;
410 /* 1 if support old (<= 2.8.1) versions of gcc. */
411 static int old_gcc
= OLDGCC_COMPAT
;
413 /* 1 if pseudo registers are permitted. */
414 static int allow_pseudo_reg
= 0;
416 /* 1 if register prefix % not required. */
417 static int allow_naked_reg
= 0;
419 /* 1 if pseudo index register, eiz/riz, is allowed . */
420 static int allow_index_reg
= 0;
430 /* Register prefix used for error message. */
431 static const char *register_prefix
= "%";
433 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
434 leave, push, and pop instructions so that gcc has the same stack
435 frame as in 32 bit mode. */
436 static char stackop_size
= '\0';
438 /* Non-zero to optimize code alignment. */
439 int optimize_align_code
= 1;
441 /* Non-zero to quieten some warnings. */
442 static int quiet_warnings
= 0;
445 static const char *cpu_arch_name
= NULL
;
446 static char *cpu_sub_arch_name
= NULL
;
448 /* CPU feature flags. */
449 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
451 /* If we have selected a cpu we are generating instructions for. */
452 static int cpu_arch_tune_set
= 0;
454 /* Cpu we are generating instructions for. */
455 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
457 /* CPU feature flags of cpu we are generating instructions for. */
458 static i386_cpu_flags cpu_arch_tune_flags
;
460 /* CPU instruction set architecture used. */
461 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
463 /* CPU feature flags of instruction set architecture used. */
464 i386_cpu_flags cpu_arch_isa_flags
;
466 /* If set, conditional jumps are not automatically promoted to handle
467 larger than a byte offset. */
468 static unsigned int no_cond_jump_promotion
= 0;
470 /* Encode SSE instructions with VEX prefix. */
471 static unsigned int sse2avx
;
473 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
474 static symbolS
*GOT_symbol
;
476 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
477 unsigned int x86_dwarf2_return_column
;
479 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
480 int x86_cie_data_alignment
;
482 /* Interface to relax_segment.
483 There are 3 major relax states for 386 jump insns because the
484 different types of jumps add different sizes to frags when we're
485 figuring out what sort of jump to choose to reach a given label. */
488 #define UNCOND_JUMP 0
490 #define COND_JUMP86 2
495 #define SMALL16 (SMALL | CODE16)
497 #define BIG16 (BIG | CODE16)
501 #define INLINE __inline__
507 #define ENCODE_RELAX_STATE(type, size) \
508 ((relax_substateT) (((type) << 2) | (size)))
509 #define TYPE_FROM_RELAX_STATE(s) \
511 #define DISP_SIZE_FROM_RELAX_STATE(s) \
512 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
514 /* This table is used by relax_frag to promote short jumps to long
515 ones where necessary. SMALL (short) jumps may be promoted to BIG
516 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
517 don't allow a short jump in a 32 bit code segment to be promoted to
518 a 16 bit offset jump because it's slower (requires data size
519 prefix), and doesn't work, unless the destination is in the bottom
520 64k of the code segment (The top 16 bits of eip are zeroed). */
522 const relax_typeS md_relax_table
[] =
525 1) most positive reach of this state,
526 2) most negative reach of this state,
527 3) how many bytes this mode will have in the variable part of the frag
528 4) which index into the table to try if we can't fit into this one. */
530 /* UNCOND_JUMP states. */
531 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
532 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
533 /* dword jmp adds 4 bytes to frag:
534 0 extra opcode bytes, 4 displacement bytes. */
536 /* word jmp adds 2 byte2 to frag:
537 0 extra opcode bytes, 2 displacement bytes. */
540 /* COND_JUMP states. */
541 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
542 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
543 /* dword conditionals adds 5 bytes to frag:
544 1 extra opcode byte, 4 displacement bytes. */
546 /* word conditionals add 3 bytes to frag:
547 1 extra opcode byte, 2 displacement bytes. */
550 /* COND_JUMP86 states. */
551 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
552 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
553 /* dword conditionals adds 5 bytes to frag:
554 1 extra opcode byte, 4 displacement bytes. */
556 /* word conditionals add 4 bytes to frag:
557 1 displacement byte and a 3 byte long branch insn. */
561 static const arch_entry cpu_arch
[] =
563 { "generic32", PROCESSOR_GENERIC32
,
564 CPU_GENERIC32_FLAGS
},
565 { "generic64", PROCESSOR_GENERIC64
,
566 CPU_GENERIC64_FLAGS
},
567 { "i8086", PROCESSOR_UNKNOWN
,
569 { "i186", PROCESSOR_UNKNOWN
,
571 { "i286", PROCESSOR_UNKNOWN
,
573 { "i386", PROCESSOR_I386
,
575 { "i486", PROCESSOR_I486
,
577 { "i586", PROCESSOR_PENTIUM
,
579 { "i686", PROCESSOR_PENTIUMPRO
,
581 { "pentium", PROCESSOR_PENTIUM
,
583 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
585 { "pentiumii", PROCESSOR_PENTIUMPRO
,
587 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
589 { "pentium4", PROCESSOR_PENTIUM4
,
591 { "prescott", PROCESSOR_NOCONA
,
593 { "nocona", PROCESSOR_NOCONA
,
595 { "yonah", PROCESSOR_CORE
,
597 { "core", PROCESSOR_CORE
,
599 { "merom", PROCESSOR_CORE2
,
601 { "core2", PROCESSOR_CORE2
,
603 { "corei7", PROCESSOR_COREI7
,
605 { "k6", PROCESSOR_K6
,
607 { "k6_2", PROCESSOR_K6
,
609 { "athlon", PROCESSOR_ATHLON
,
611 { "sledgehammer", PROCESSOR_K8
,
613 { "opteron", PROCESSOR_K8
,
615 { "k8", PROCESSOR_K8
,
617 { "amdfam10", PROCESSOR_AMDFAM10
,
618 CPU_AMDFAM10_FLAGS
},
619 { ".mmx", PROCESSOR_UNKNOWN
,
621 { ".sse", PROCESSOR_UNKNOWN
,
623 { ".sse2", PROCESSOR_UNKNOWN
,
625 { ".sse3", PROCESSOR_UNKNOWN
,
627 { ".ssse3", PROCESSOR_UNKNOWN
,
629 { ".sse4.1", PROCESSOR_UNKNOWN
,
631 { ".sse4.2", PROCESSOR_UNKNOWN
,
633 { ".sse4", PROCESSOR_UNKNOWN
,
635 { ".avx", PROCESSOR_UNKNOWN
,
637 { ".vmx", PROCESSOR_UNKNOWN
,
639 { ".smx", PROCESSOR_UNKNOWN
,
641 { ".xsave", PROCESSOR_UNKNOWN
,
643 { ".aes", PROCESSOR_UNKNOWN
,
645 { ".pclmul", PROCESSOR_UNKNOWN
,
647 { ".clmul", PROCESSOR_UNKNOWN
,
649 { ".fma", PROCESSOR_UNKNOWN
,
651 { ".movbe", PROCESSOR_UNKNOWN
,
653 { ".ept", PROCESSOR_UNKNOWN
,
655 { ".clflush", PROCESSOR_UNKNOWN
,
657 { ".syscall", PROCESSOR_UNKNOWN
,
659 { ".rdtscp", PROCESSOR_UNKNOWN
,
661 { ".3dnow", PROCESSOR_UNKNOWN
,
663 { ".3dnowa", PROCESSOR_UNKNOWN
,
665 { ".padlock", PROCESSOR_UNKNOWN
,
667 { ".pacifica", PROCESSOR_UNKNOWN
,
669 { ".svme", PROCESSOR_UNKNOWN
,
671 { ".sse4a", PROCESSOR_UNKNOWN
,
673 { ".abm", PROCESSOR_UNKNOWN
,
675 { ".sse5", PROCESSOR_UNKNOWN
,
680 /* Like s_lcomm_internal in gas/read.c but the alignment string
681 is allowed to be optional. */
684 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
691 && *input_line_pointer
== ',')
693 align
= parse_align (needs_align
- 1);
695 if (align
== (addressT
) -1)
710 bss_alloc (symbolP
, size
, align
);
715 pe_lcomm (int needs_align
)
717 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
721 const pseudo_typeS md_pseudo_table
[] =
723 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
724 {"align", s_align_bytes
, 0},
726 {"align", s_align_ptwo
, 0},
728 {"arch", set_cpu_arch
, 0},
732 {"lcomm", pe_lcomm
, 1},
734 {"ffloat", float_cons
, 'f'},
735 {"dfloat", float_cons
, 'd'},
736 {"tfloat", float_cons
, 'x'},
738 {"slong", signed_cons
, 4},
739 {"noopt", s_ignore
, 0},
740 {"optim", s_ignore
, 0},
741 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
742 {"code16", set_code_flag
, CODE_16BIT
},
743 {"code32", set_code_flag
, CODE_32BIT
},
744 {"code64", set_code_flag
, CODE_64BIT
},
745 {"intel_syntax", set_intel_syntax
, 1},
746 {"att_syntax", set_intel_syntax
, 0},
747 {"intel_mnemonic", set_intel_mnemonic
, 1},
748 {"att_mnemonic", set_intel_mnemonic
, 0},
749 {"allow_index_reg", set_allow_index_reg
, 1},
750 {"disallow_index_reg", set_allow_index_reg
, 0},
751 {"sse_check", set_sse_check
, 0},
752 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
753 {"largecomm", handle_large_common
, 0},
755 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
756 {"loc", dwarf2_directive_loc
, 0},
757 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
760 {"secrel32", pe_directive_secrel
, 0},
765 /* For interface with expression (). */
766 extern char *input_line_pointer
;
768 /* Hash table for instruction mnemonic lookup. */
769 static struct hash_control
*op_hash
;
771 /* Hash table for register lookup. */
772 static struct hash_control
*reg_hash
;
775 i386_align_code (fragS
*fragP
, int count
)
777 /* Various efficient no-op patterns for aligning code labels.
778 Note: Don't try to assemble the instructions in the comments.
779 0L and 0w are not legal. */
780 static const char f32_1
[] =
782 static const char f32_2
[] =
783 {0x66,0x90}; /* xchg %ax,%ax */
784 static const char f32_3
[] =
785 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
786 static const char f32_4
[] =
787 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
788 static const char f32_5
[] =
790 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
791 static const char f32_6
[] =
792 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
793 static const char f32_7
[] =
794 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
795 static const char f32_8
[] =
797 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
798 static const char f32_9
[] =
799 {0x89,0xf6, /* movl %esi,%esi */
800 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
801 static const char f32_10
[] =
802 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
803 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
804 static const char f32_11
[] =
805 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
806 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
807 static const char f32_12
[] =
808 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
809 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
810 static const char f32_13
[] =
811 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
812 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
813 static const char f32_14
[] =
814 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
815 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
816 static const char f16_3
[] =
817 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
818 static const char f16_4
[] =
819 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
820 static const char f16_5
[] =
822 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
823 static const char f16_6
[] =
824 {0x89,0xf6, /* mov %si,%si */
825 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
826 static const char f16_7
[] =
827 {0x8d,0x74,0x00, /* lea 0(%si),%si */
828 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
829 static const char f16_8
[] =
830 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
831 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
832 static const char jump_31
[] =
833 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
834 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
835 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
836 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
837 static const char *const f32_patt
[] = {
838 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
839 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
841 static const char *const f16_patt
[] = {
842 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
845 static const char alt_3
[] =
847 /* nopl 0(%[re]ax) */
848 static const char alt_4
[] =
849 {0x0f,0x1f,0x40,0x00};
850 /* nopl 0(%[re]ax,%[re]ax,1) */
851 static const char alt_5
[] =
852 {0x0f,0x1f,0x44,0x00,0x00};
853 /* nopw 0(%[re]ax,%[re]ax,1) */
854 static const char alt_6
[] =
855 {0x66,0x0f,0x1f,0x44,0x00,0x00};
856 /* nopl 0L(%[re]ax) */
857 static const char alt_7
[] =
858 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
859 /* nopl 0L(%[re]ax,%[re]ax,1) */
860 static const char alt_8
[] =
861 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
862 /* nopw 0L(%[re]ax,%[re]ax,1) */
863 static const char alt_9
[] =
864 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
865 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
866 static const char alt_10
[] =
867 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
869 nopw %cs:0L(%[re]ax,%[re]ax,1) */
870 static const char alt_long_11
[] =
872 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
875 nopw %cs:0L(%[re]ax,%[re]ax,1) */
876 static const char alt_long_12
[] =
879 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
883 nopw %cs:0L(%[re]ax,%[re]ax,1) */
884 static const char alt_long_13
[] =
888 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
893 nopw %cs:0L(%[re]ax,%[re]ax,1) */
894 static const char alt_long_14
[] =
899 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
905 nopw %cs:0L(%[re]ax,%[re]ax,1) */
906 static const char alt_long_15
[] =
912 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
913 /* nopl 0(%[re]ax,%[re]ax,1)
914 nopw 0(%[re]ax,%[re]ax,1) */
915 static const char alt_short_11
[] =
916 {0x0f,0x1f,0x44,0x00,0x00,
917 0x66,0x0f,0x1f,0x44,0x00,0x00};
918 /* nopw 0(%[re]ax,%[re]ax,1)
919 nopw 0(%[re]ax,%[re]ax,1) */
920 static const char alt_short_12
[] =
921 {0x66,0x0f,0x1f,0x44,0x00,0x00,
922 0x66,0x0f,0x1f,0x44,0x00,0x00};
923 /* nopw 0(%[re]ax,%[re]ax,1)
925 static const char alt_short_13
[] =
926 {0x66,0x0f,0x1f,0x44,0x00,0x00,
927 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
930 static const char alt_short_14
[] =
931 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
932 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
934 nopl 0L(%[re]ax,%[re]ax,1) */
935 static const char alt_short_15
[] =
936 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
937 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
938 static const char *const alt_short_patt
[] = {
939 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
940 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
941 alt_short_14
, alt_short_15
943 static const char *const alt_long_patt
[] = {
944 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
945 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
946 alt_long_14
, alt_long_15
949 /* Only align for at least a positive non-zero boundary. */
950 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
953 /* We need to decide which NOP sequence to use for 32bit and
954 64bit. When -mtune= is used:
956 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
957 PROCESSOR_GENERIC32, f32_patt will be used.
958 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
959 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
960 PROCESSOR_GENERIC64, alt_long_patt will be used.
961 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
962 PROCESSOR_AMDFAM10, alt_short_patt will be used.
964 When -mtune= isn't used, alt_long_patt will be used if
965 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
968 When -march= or .arch is used, we can't use anything beyond
969 cpu_arch_isa_flags. */
971 if (flag_code
== CODE_16BIT
)
975 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
977 /* Adjust jump offset. */
978 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
981 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
982 f16_patt
[count
- 1], count
);
986 const char *const *patt
= NULL
;
988 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
990 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
991 switch (cpu_arch_tune
)
993 case PROCESSOR_UNKNOWN
:
994 /* We use cpu_arch_isa_flags to check if we SHOULD
995 optimize for Cpu686. */
996 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
997 patt
= alt_long_patt
;
1001 case PROCESSOR_PENTIUMPRO
:
1002 case PROCESSOR_PENTIUM4
:
1003 case PROCESSOR_NOCONA
:
1004 case PROCESSOR_CORE
:
1005 case PROCESSOR_CORE2
:
1006 case PROCESSOR_COREI7
:
1007 case PROCESSOR_GENERIC64
:
1008 patt
= alt_long_patt
;
1011 case PROCESSOR_ATHLON
:
1013 case PROCESSOR_AMDFAM10
:
1014 patt
= alt_short_patt
;
1016 case PROCESSOR_I386
:
1017 case PROCESSOR_I486
:
1018 case PROCESSOR_PENTIUM
:
1019 case PROCESSOR_GENERIC32
:
1026 switch (fragP
->tc_frag_data
.tune
)
1028 case PROCESSOR_UNKNOWN
:
1029 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1030 PROCESSOR_UNKNOWN. */
1034 case PROCESSOR_I386
:
1035 case PROCESSOR_I486
:
1036 case PROCESSOR_PENTIUM
:
1038 case PROCESSOR_ATHLON
:
1040 case PROCESSOR_AMDFAM10
:
1041 case PROCESSOR_GENERIC32
:
1042 /* We use cpu_arch_isa_flags to check if we CAN optimize
1044 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1045 patt
= alt_short_patt
;
1049 case PROCESSOR_PENTIUMPRO
:
1050 case PROCESSOR_PENTIUM4
:
1051 case PROCESSOR_NOCONA
:
1052 case PROCESSOR_CORE
:
1053 case PROCESSOR_CORE2
:
1054 case PROCESSOR_COREI7
:
1055 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1056 patt
= alt_long_patt
;
1060 case PROCESSOR_GENERIC64
:
1061 patt
= alt_long_patt
;
1066 if (patt
== f32_patt
)
1068 /* If the padding is less than 15 bytes, we use the normal
1069 ones. Otherwise, we use a jump instruction and adjust
1072 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1073 patt
[count
- 1], count
);
1076 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1078 /* Adjust jump offset. */
1079 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1084 /* Maximum length of an instruction is 15 byte. If the
1085 padding is greater than 15 bytes and we don't use jump,
1086 we have to break it into smaller pieces. */
1087 int padding
= count
;
1088 while (padding
> 15)
1091 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1096 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1097 patt
[padding
- 1], padding
);
1100 fragP
->fr_var
= count
;
1104 operand_type_all_zero (const union i386_operand_type
*x
)
1106 switch (ARRAY_SIZE(x
->array
))
1115 return !x
->array
[0];
1122 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1124 switch (ARRAY_SIZE(x
->array
))
1139 operand_type_equal (const union i386_operand_type
*x
,
1140 const union i386_operand_type
*y
)
1142 switch (ARRAY_SIZE(x
->array
))
1145 if (x
->array
[2] != y
->array
[2])
1148 if (x
->array
[1] != y
->array
[1])
1151 return x
->array
[0] == y
->array
[0];
1159 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1161 switch (ARRAY_SIZE(x
->array
))
1170 return !x
->array
[0];
1177 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1179 switch (ARRAY_SIZE(x
->array
))
1194 cpu_flags_equal (const union i386_cpu_flags
*x
,
1195 const union i386_cpu_flags
*y
)
1197 switch (ARRAY_SIZE(x
->array
))
1200 if (x
->array
[2] != y
->array
[2])
1203 if (x
->array
[1] != y
->array
[1])
1206 return x
->array
[0] == y
->array
[0];
1214 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1216 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1217 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1220 static INLINE i386_cpu_flags
1221 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1223 switch (ARRAY_SIZE (x
.array
))
1226 x
.array
[2] &= y
.array
[2];
1228 x
.array
[1] &= y
.array
[1];
1230 x
.array
[0] &= y
.array
[0];
1238 static INLINE i386_cpu_flags
1239 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1241 switch (ARRAY_SIZE (x
.array
))
1244 x
.array
[2] |= y
.array
[2];
1246 x
.array
[1] |= y
.array
[1];
1248 x
.array
[0] |= y
.array
[0];
1256 #define CPU_FLAGS_ARCH_MATCH 0x1
1257 #define CPU_FLAGS_64BIT_MATCH 0x2
1258 #define CPU_FLAGS_AES_MATCH 0x4
1259 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1260 #define CPU_FLAGS_AVX_MATCH 0x10
1262 #define CPU_FLAGS_32BIT_MATCH \
1263 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1264 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1265 #define CPU_FLAGS_PERFECT_MATCH \
1266 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1268 /* Return CPU flags match bits. */
1271 cpu_flags_match (const template *t
)
1273 i386_cpu_flags x
= t
->cpu_flags
;
1274 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1276 x
.bitfield
.cpu64
= 0;
1277 x
.bitfield
.cpuno64
= 0;
1279 if (cpu_flags_all_zero (&x
))
1281 /* This instruction is available on all archs. */
1282 match
|= CPU_FLAGS_32BIT_MATCH
;
1286 /* This instruction is available only on some archs. */
1287 i386_cpu_flags cpu
= cpu_arch_flags
;
1289 cpu
.bitfield
.cpu64
= 0;
1290 cpu
.bitfield
.cpuno64
= 0;
1291 cpu
= cpu_flags_and (x
, cpu
);
1292 if (!cpu_flags_all_zero (&cpu
))
1294 if (x
.bitfield
.cpuavx
)
1296 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1297 if (cpu
.bitfield
.cpuavx
)
1299 /* Check SSE2AVX. */
1300 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1302 match
|= (CPU_FLAGS_ARCH_MATCH
1303 | CPU_FLAGS_AVX_MATCH
);
1305 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1306 match
|= CPU_FLAGS_AES_MATCH
;
1308 if (!x
.bitfield
.cpupclmul
1309 || cpu
.bitfield
.cpupclmul
)
1310 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1314 match
|= CPU_FLAGS_ARCH_MATCH
;
1317 match
|= CPU_FLAGS_32BIT_MATCH
;
1323 static INLINE i386_operand_type
1324 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1326 switch (ARRAY_SIZE (x
.array
))
1329 x
.array
[2] &= y
.array
[2];
1331 x
.array
[1] &= y
.array
[1];
1333 x
.array
[0] &= y
.array
[0];
1341 static INLINE i386_operand_type
1342 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1344 switch (ARRAY_SIZE (x
.array
))
1347 x
.array
[2] |= y
.array
[2];
1349 x
.array
[1] |= y
.array
[1];
1351 x
.array
[0] |= y
.array
[0];
1359 static INLINE i386_operand_type
1360 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1362 switch (ARRAY_SIZE (x
.array
))
1365 x
.array
[2] ^= y
.array
[2];
1367 x
.array
[1] ^= y
.array
[1];
1369 x
.array
[0] ^= y
.array
[0];
1377 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1378 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1379 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1380 static const i386_operand_type inoutportreg
1381 = OPERAND_TYPE_INOUTPORTREG
;
1382 static const i386_operand_type reg16_inoutportreg
1383 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1384 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1385 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1386 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1387 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1388 static const i386_operand_type anydisp
1389 = OPERAND_TYPE_ANYDISP
;
1390 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1391 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1392 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1393 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1394 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1395 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1396 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1397 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1398 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1399 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1400 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1401 static const i386_operand_type vex_imm4
= OPERAND_TYPE_VEX_IMM4
;
1412 operand_type_check (i386_operand_type t
, enum operand_type c
)
1417 return (t
.bitfield
.reg8
1420 || t
.bitfield
.reg64
);
1423 return (t
.bitfield
.imm8
1427 || t
.bitfield
.imm32s
1428 || t
.bitfield
.imm64
);
1431 return (t
.bitfield
.disp8
1432 || t
.bitfield
.disp16
1433 || t
.bitfield
.disp32
1434 || t
.bitfield
.disp32s
1435 || t
.bitfield
.disp64
);
1438 return (t
.bitfield
.disp8
1439 || t
.bitfield
.disp16
1440 || t
.bitfield
.disp32
1441 || t
.bitfield
.disp32s
1442 || t
.bitfield
.disp64
1443 || t
.bitfield
.baseindex
);
1452 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1453 operand J for instruction template T. */
1456 match_reg_size (const template *t
, unsigned int j
)
1458 return !((i
.types
[j
].bitfield
.byte
1459 && !t
->operand_types
[j
].bitfield
.byte
)
1460 || (i
.types
[j
].bitfield
.word
1461 && !t
->operand_types
[j
].bitfield
.word
)
1462 || (i
.types
[j
].bitfield
.dword
1463 && !t
->operand_types
[j
].bitfield
.dword
)
1464 || (i
.types
[j
].bitfield
.qword
1465 && !t
->operand_types
[j
].bitfield
.qword
));
1468 /* Return 1 if there is no conflict in any size on operand J for
1469 instruction template T. */
1472 match_mem_size (const template *t
, unsigned int j
)
1474 return (match_reg_size (t
, j
)
1475 && !((i
.types
[j
].bitfield
.unspecified
1476 && !t
->operand_types
[j
].bitfield
.unspecified
)
1477 || (i
.types
[j
].bitfield
.fword
1478 && !t
->operand_types
[j
].bitfield
.fword
)
1479 || (i
.types
[j
].bitfield
.tbyte
1480 && !t
->operand_types
[j
].bitfield
.tbyte
)
1481 || (i
.types
[j
].bitfield
.xmmword
1482 && !t
->operand_types
[j
].bitfield
.xmmword
)
1483 || (i
.types
[j
].bitfield
.ymmword
1484 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1487 /* Return 1 if there is no size conflict on any operands for
1488 instruction template T. */
1491 operand_size_match (const template *t
)
1496 /* Don't check jump instructions. */
1497 if (t
->opcode_modifier
.jump
1498 || t
->opcode_modifier
.jumpbyte
1499 || t
->opcode_modifier
.jumpdword
1500 || t
->opcode_modifier
.jumpintersegment
)
1503 /* Check memory and accumulator operand size. */
1504 for (j
= 0; j
< i
.operands
; j
++)
1506 if (t
->operand_types
[j
].bitfield
.anysize
)
1509 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1515 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1523 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1526 /* Check reverse. */
1527 assert (i
.operands
== 2);
1530 for (j
= 0; j
< 2; j
++)
1532 if (t
->operand_types
[j
].bitfield
.acc
1533 && !match_reg_size (t
, j
? 0 : 1))
1539 if (i
.types
[j
].bitfield
.mem
1540 && !match_mem_size (t
, j
? 0 : 1))
1551 operand_type_match (i386_operand_type overlap
,
1552 i386_operand_type given
)
1554 i386_operand_type temp
= overlap
;
1556 temp
.bitfield
.jumpabsolute
= 0;
1557 temp
.bitfield
.unspecified
= 0;
1558 temp
.bitfield
.byte
= 0;
1559 temp
.bitfield
.word
= 0;
1560 temp
.bitfield
.dword
= 0;
1561 temp
.bitfield
.fword
= 0;
1562 temp
.bitfield
.qword
= 0;
1563 temp
.bitfield
.tbyte
= 0;
1564 temp
.bitfield
.xmmword
= 0;
1565 temp
.bitfield
.ymmword
= 0;
1566 if (operand_type_all_zero (&temp
))
1569 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1570 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1573 /* If given types g0 and g1 are registers they must be of the same type
1574 unless the expected operand type register overlap is null.
1575 Note that Acc in a template matches every size of reg. */
1578 operand_type_register_match (i386_operand_type m0
,
1579 i386_operand_type g0
,
1580 i386_operand_type t0
,
1581 i386_operand_type m1
,
1582 i386_operand_type g1
,
1583 i386_operand_type t1
)
1585 if (!operand_type_check (g0
, reg
))
1588 if (!operand_type_check (g1
, reg
))
1591 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1592 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1593 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1594 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1597 if (m0
.bitfield
.acc
)
1599 t0
.bitfield
.reg8
= 1;
1600 t0
.bitfield
.reg16
= 1;
1601 t0
.bitfield
.reg32
= 1;
1602 t0
.bitfield
.reg64
= 1;
1605 if (m1
.bitfield
.acc
)
1607 t1
.bitfield
.reg8
= 1;
1608 t1
.bitfield
.reg16
= 1;
1609 t1
.bitfield
.reg32
= 1;
1610 t1
.bitfield
.reg64
= 1;
1613 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1614 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1615 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1616 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1619 static INLINE
unsigned int
1620 mode_from_disp_size (i386_operand_type t
)
1622 if (t
.bitfield
.disp8
)
1624 else if (t
.bitfield
.disp16
1625 || t
.bitfield
.disp32
1626 || t
.bitfield
.disp32s
)
1633 fits_in_signed_byte (offsetT num
)
1635 return (num
>= -128) && (num
<= 127);
1639 fits_in_unsigned_byte (offsetT num
)
1641 return (num
& 0xff) == num
;
1645 fits_in_unsigned_word (offsetT num
)
1647 return (num
& 0xffff) == num
;
1651 fits_in_signed_word (offsetT num
)
1653 return (-32768 <= num
) && (num
<= 32767);
1657 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1662 return (!(((offsetT
) -1 << 31) & num
)
1663 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1665 } /* fits_in_signed_long() */
1668 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1673 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1675 } /* fits_in_unsigned_long() */
1678 fits_in_imm4 (offsetT num
)
1680 return (num
& 0xf) == num
;
1683 static i386_operand_type
1684 smallest_imm_type (offsetT num
)
1686 i386_operand_type t
;
1688 operand_type_set (&t
, 0);
1689 t
.bitfield
.imm64
= 1;
1691 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1693 /* This code is disabled on the 486 because all the Imm1 forms
1694 in the opcode table are slower on the i486. They're the
1695 versions with the implicitly specified single-position
1696 displacement, which has another syntax if you really want to
1698 t
.bitfield
.imm1
= 1;
1699 t
.bitfield
.imm8
= 1;
1700 t
.bitfield
.imm8s
= 1;
1701 t
.bitfield
.imm16
= 1;
1702 t
.bitfield
.imm32
= 1;
1703 t
.bitfield
.imm32s
= 1;
1705 else if (fits_in_signed_byte (num
))
1707 t
.bitfield
.imm8
= 1;
1708 t
.bitfield
.imm8s
= 1;
1709 t
.bitfield
.imm16
= 1;
1710 t
.bitfield
.imm32
= 1;
1711 t
.bitfield
.imm32s
= 1;
1713 else if (fits_in_unsigned_byte (num
))
1715 t
.bitfield
.imm8
= 1;
1716 t
.bitfield
.imm16
= 1;
1717 t
.bitfield
.imm32
= 1;
1718 t
.bitfield
.imm32s
= 1;
1720 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1722 t
.bitfield
.imm16
= 1;
1723 t
.bitfield
.imm32
= 1;
1724 t
.bitfield
.imm32s
= 1;
1726 else if (fits_in_signed_long (num
))
1728 t
.bitfield
.imm32
= 1;
1729 t
.bitfield
.imm32s
= 1;
1731 else if (fits_in_unsigned_long (num
))
1732 t
.bitfield
.imm32
= 1;
1738 offset_in_range (offsetT val
, int size
)
1744 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1745 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1746 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1748 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1753 /* If BFD64, sign extend val. */
1754 if (!use_rela_relocations
)
1755 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1756 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1758 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1760 char buf1
[40], buf2
[40];
1762 sprint_value (buf1
, val
);
1763 sprint_value (buf2
, val
& mask
);
1764 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1769 /* Returns 0 if attempting to add a prefix where one from the same
1770 class already exists, 1 if non rep/repne added, 2 if rep/repne
1773 add_prefix (unsigned int prefix
)
1778 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1779 && flag_code
== CODE_64BIT
)
1781 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1782 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1783 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1794 case CS_PREFIX_OPCODE
:
1795 case DS_PREFIX_OPCODE
:
1796 case ES_PREFIX_OPCODE
:
1797 case FS_PREFIX_OPCODE
:
1798 case GS_PREFIX_OPCODE
:
1799 case SS_PREFIX_OPCODE
:
1803 case REPNE_PREFIX_OPCODE
:
1804 case REPE_PREFIX_OPCODE
:
1807 case LOCK_PREFIX_OPCODE
:
1815 case ADDR_PREFIX_OPCODE
:
1819 case DATA_PREFIX_OPCODE
:
1823 if (i
.prefix
[q
] != 0)
1831 i
.prefix
[q
] |= prefix
;
1834 as_bad (_("same type of prefix used twice"));
1840 set_code_flag (int value
)
1843 if (flag_code
== CODE_64BIT
)
1845 cpu_arch_flags
.bitfield
.cpu64
= 1;
1846 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1850 cpu_arch_flags
.bitfield
.cpu64
= 0;
1851 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1853 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1855 as_bad (_("64bit mode not supported on this CPU."));
1857 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1859 as_bad (_("32bit mode not supported on this CPU."));
1861 stackop_size
= '\0';
1865 set_16bit_gcc_code_flag (int new_code_flag
)
1867 flag_code
= new_code_flag
;
1868 if (flag_code
!= CODE_16BIT
)
1870 cpu_arch_flags
.bitfield
.cpu64
= 0;
1871 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1872 stackop_size
= LONG_MNEM_SUFFIX
;
1876 set_intel_syntax (int syntax_flag
)
1878 /* Find out if register prefixing is specified. */
1879 int ask_naked_reg
= 0;
1882 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1884 char *string
= input_line_pointer
;
1885 int e
= get_symbol_end ();
1887 if (strcmp (string
, "prefix") == 0)
1889 else if (strcmp (string
, "noprefix") == 0)
1892 as_bad (_("bad argument to syntax directive."));
1893 *input_line_pointer
= e
;
1895 demand_empty_rest_of_line ();
1897 intel_syntax
= syntax_flag
;
1899 if (ask_naked_reg
== 0)
1900 allow_naked_reg
= (intel_syntax
1901 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1903 allow_naked_reg
= (ask_naked_reg
< 0);
1905 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1906 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1907 register_prefix
= allow_naked_reg
? "" : "%";
1911 set_intel_mnemonic (int mnemonic_flag
)
1913 intel_mnemonic
= mnemonic_flag
;
1917 set_allow_index_reg (int flag
)
1919 allow_index_reg
= flag
;
1923 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1927 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1929 char *string
= input_line_pointer
;
1930 int e
= get_symbol_end ();
1932 if (strcmp (string
, "none") == 0)
1933 sse_check
= sse_check_none
;
1934 else if (strcmp (string
, "warning") == 0)
1935 sse_check
= sse_check_warning
;
1936 else if (strcmp (string
, "error") == 0)
1937 sse_check
= sse_check_error
;
1939 as_bad (_("bad argument to sse_check directive."));
1940 *input_line_pointer
= e
;
1943 as_bad (_("missing argument for sse_check directive"));
1945 demand_empty_rest_of_line ();
1949 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1953 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1955 char *string
= input_line_pointer
;
1956 int e
= get_symbol_end ();
1958 i386_cpu_flags flags
;
1960 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1962 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1966 cpu_arch_name
= cpu_arch
[i
].name
;
1967 cpu_sub_arch_name
= NULL
;
1968 cpu_arch_flags
= cpu_arch
[i
].flags
;
1969 if (flag_code
== CODE_64BIT
)
1971 cpu_arch_flags
.bitfield
.cpu64
= 1;
1972 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1976 cpu_arch_flags
.bitfield
.cpu64
= 0;
1977 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1979 cpu_arch_isa
= cpu_arch
[i
].type
;
1980 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1981 if (!cpu_arch_tune_set
)
1983 cpu_arch_tune
= cpu_arch_isa
;
1984 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1989 flags
= cpu_flags_or (cpu_arch_flags
,
1991 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
1993 if (cpu_sub_arch_name
)
1995 char *name
= cpu_sub_arch_name
;
1996 cpu_sub_arch_name
= concat (name
,
1998 (const char *) NULL
);
2002 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
2003 cpu_arch_flags
= flags
;
2005 *input_line_pointer
= e
;
2006 demand_empty_rest_of_line ();
2010 if (i
>= ARRAY_SIZE (cpu_arch
))
2011 as_bad (_("no such architecture: `%s'"), string
);
2013 *input_line_pointer
= e
;
2016 as_bad (_("missing cpu architecture"));
2018 no_cond_jump_promotion
= 0;
2019 if (*input_line_pointer
== ','
2020 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2022 char *string
= ++input_line_pointer
;
2023 int e
= get_symbol_end ();
2025 if (strcmp (string
, "nojumps") == 0)
2026 no_cond_jump_promotion
= 1;
2027 else if (strcmp (string
, "jumps") == 0)
2030 as_bad (_("no such architecture modifier: `%s'"), string
);
2032 *input_line_pointer
= e
;
2035 demand_empty_rest_of_line ();
2041 if (!strcmp (default_arch
, "x86_64"))
2042 return bfd_mach_x86_64
;
2043 else if (!strcmp (default_arch
, "i386"))
2044 return bfd_mach_i386_i386
;
2046 as_fatal (_("Unknown architecture"));
2052 const char *hash_err
;
2054 /* Initialize op_hash hash table. */
2055 op_hash
= hash_new ();
2058 const template *optab
;
2059 templates
*core_optab
;
2061 /* Setup for loop. */
2063 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2064 core_optab
->start
= optab
;
2069 if (optab
->name
== NULL
2070 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2072 /* different name --> ship out current template list;
2073 add to hash table; & begin anew. */
2074 core_optab
->end
= optab
;
2075 hash_err
= hash_insert (op_hash
,
2077 (void *) core_optab
);
2080 as_fatal (_("Internal Error: Can't hash %s: %s"),
2084 if (optab
->name
== NULL
)
2086 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2087 core_optab
->start
= optab
;
2092 /* Initialize reg_hash hash table. */
2093 reg_hash
= hash_new ();
2095 const reg_entry
*regtab
;
2096 unsigned int regtab_size
= i386_regtab_size
;
2098 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2100 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2102 as_fatal (_("Internal Error: Can't hash %s: %s"),
2108 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2113 for (c
= 0; c
< 256; c
++)
2118 mnemonic_chars
[c
] = c
;
2119 register_chars
[c
] = c
;
2120 operand_chars
[c
] = c
;
2122 else if (ISLOWER (c
))
2124 mnemonic_chars
[c
] = c
;
2125 register_chars
[c
] = c
;
2126 operand_chars
[c
] = c
;
2128 else if (ISUPPER (c
))
2130 mnemonic_chars
[c
] = TOLOWER (c
);
2131 register_chars
[c
] = mnemonic_chars
[c
];
2132 operand_chars
[c
] = c
;
2135 if (ISALPHA (c
) || ISDIGIT (c
))
2136 identifier_chars
[c
] = c
;
2139 identifier_chars
[c
] = c
;
2140 operand_chars
[c
] = c
;
2145 identifier_chars
['@'] = '@';
2148 identifier_chars
['?'] = '?';
2149 operand_chars
['?'] = '?';
2151 digit_chars
['-'] = '-';
2152 mnemonic_chars
['_'] = '_';
2153 mnemonic_chars
['-'] = '-';
2154 mnemonic_chars
['.'] = '.';
2155 identifier_chars
['_'] = '_';
2156 identifier_chars
['.'] = '.';
2158 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2159 operand_chars
[(unsigned char) *p
] = *p
;
2162 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2165 record_alignment (text_section
, 2);
2166 record_alignment (data_section
, 2);
2167 record_alignment (bss_section
, 2);
2171 if (flag_code
== CODE_64BIT
)
2173 x86_dwarf2_return_column
= 16;
2174 x86_cie_data_alignment
= -8;
2178 x86_dwarf2_return_column
= 8;
2179 x86_cie_data_alignment
= -4;
2184 i386_print_statistics (FILE *file
)
2186 hash_print_statistics (file
, "i386 opcode", op_hash
);
2187 hash_print_statistics (file
, "i386 register", reg_hash
);
2192 /* Debugging routines for md_assemble. */
2193 static void pte (template *);
2194 static void pt (i386_operand_type
);
2195 static void pe (expressionS
*);
2196 static void ps (symbolS
*);
2199 pi (char *line
, i386_insn
*x
)
2203 fprintf (stdout
, "%s: template ", line
);
2205 fprintf (stdout
, " address: base %s index %s scale %x\n",
2206 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2207 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2208 x
->log2_scale_factor
);
2209 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2210 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2211 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2212 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2213 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2214 (x
->rex
& REX_W
) != 0,
2215 (x
->rex
& REX_R
) != 0,
2216 (x
->rex
& REX_X
) != 0,
2217 (x
->rex
& REX_B
) != 0);
2218 fprintf (stdout
, " drex: reg %d rex 0x%x\n",
2219 x
->drex
.reg
, x
->drex
.rex
);
2220 for (i
= 0; i
< x
->operands
; i
++)
2222 fprintf (stdout
, " #%d: ", i
+ 1);
2224 fprintf (stdout
, "\n");
2225 if (x
->types
[i
].bitfield
.reg8
2226 || x
->types
[i
].bitfield
.reg16
2227 || x
->types
[i
].bitfield
.reg32
2228 || x
->types
[i
].bitfield
.reg64
2229 || x
->types
[i
].bitfield
.regmmx
2230 || x
->types
[i
].bitfield
.regxmm
2231 || x
->types
[i
].bitfield
.regymm
2232 || x
->types
[i
].bitfield
.sreg2
2233 || x
->types
[i
].bitfield
.sreg3
2234 || x
->types
[i
].bitfield
.control
2235 || x
->types
[i
].bitfield
.debug
2236 || x
->types
[i
].bitfield
.test
)
2237 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2238 if (operand_type_check (x
->types
[i
], imm
))
2240 if (operand_type_check (x
->types
[i
], disp
))
2241 pe (x
->op
[i
].disps
);
2249 fprintf (stdout
, " %d operands ", t
->operands
);
2250 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2251 if (t
->extension_opcode
!= None
)
2252 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2253 if (t
->opcode_modifier
.d
)
2254 fprintf (stdout
, "D");
2255 if (t
->opcode_modifier
.w
)
2256 fprintf (stdout
, "W");
2257 fprintf (stdout
, "\n");
2258 for (i
= 0; i
< t
->operands
; i
++)
2260 fprintf (stdout
, " #%d type ", i
+ 1);
2261 pt (t
->operand_types
[i
]);
2262 fprintf (stdout
, "\n");
2269 fprintf (stdout
, " operation %d\n", e
->X_op
);
2270 fprintf (stdout
, " add_number %ld (%lx)\n",
2271 (long) e
->X_add_number
, (long) e
->X_add_number
);
2272 if (e
->X_add_symbol
)
2274 fprintf (stdout
, " add_symbol ");
2275 ps (e
->X_add_symbol
);
2276 fprintf (stdout
, "\n");
2280 fprintf (stdout
, " op_symbol ");
2281 ps (e
->X_op_symbol
);
2282 fprintf (stdout
, "\n");
2289 fprintf (stdout
, "%s type %s%s",
2291 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2292 segment_name (S_GET_SEGMENT (s
)));
2295 static struct type_name
2297 i386_operand_type mask
;
2300 const type_names
[] =
2302 { OPERAND_TYPE_REG8
, "r8" },
2303 { OPERAND_TYPE_REG16
, "r16" },
2304 { OPERAND_TYPE_REG32
, "r32" },
2305 { OPERAND_TYPE_REG64
, "r64" },
2306 { OPERAND_TYPE_IMM8
, "i8" },
2307 { OPERAND_TYPE_IMM8
, "i8s" },
2308 { OPERAND_TYPE_IMM16
, "i16" },
2309 { OPERAND_TYPE_IMM32
, "i32" },
2310 { OPERAND_TYPE_IMM32S
, "i32s" },
2311 { OPERAND_TYPE_IMM64
, "i64" },
2312 { OPERAND_TYPE_IMM1
, "i1" },
2313 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2314 { OPERAND_TYPE_DISP8
, "d8" },
2315 { OPERAND_TYPE_DISP16
, "d16" },
2316 { OPERAND_TYPE_DISP32
, "d32" },
2317 { OPERAND_TYPE_DISP32S
, "d32s" },
2318 { OPERAND_TYPE_DISP64
, "d64" },
2319 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2320 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2321 { OPERAND_TYPE_CONTROL
, "control reg" },
2322 { OPERAND_TYPE_TEST
, "test reg" },
2323 { OPERAND_TYPE_DEBUG
, "debug reg" },
2324 { OPERAND_TYPE_FLOATREG
, "FReg" },
2325 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2326 { OPERAND_TYPE_SREG2
, "SReg2" },
2327 { OPERAND_TYPE_SREG3
, "SReg3" },
2328 { OPERAND_TYPE_ACC
, "Acc" },
2329 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2330 { OPERAND_TYPE_REGMMX
, "rMMX" },
2331 { OPERAND_TYPE_REGXMM
, "rXMM" },
2332 { OPERAND_TYPE_ESSEG
, "es" },
2333 { OPERAND_TYPE_VEX_IMM4
, "VEX i4" },
2337 pt (i386_operand_type t
)
2340 i386_operand_type a
;
2342 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2344 a
= operand_type_and (t
, type_names
[j
].mask
);
2345 if (!UINTS_ALL_ZERO (a
))
2346 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2351 #endif /* DEBUG386 */
2353 static bfd_reloc_code_real_type
2354 reloc (unsigned int size
,
2357 bfd_reloc_code_real_type other
)
2359 if (other
!= NO_RELOC
)
2361 reloc_howto_type
*reloc
;
2366 case BFD_RELOC_X86_64_GOT32
:
2367 return BFD_RELOC_X86_64_GOT64
;
2369 case BFD_RELOC_X86_64_PLTOFF64
:
2370 return BFD_RELOC_X86_64_PLTOFF64
;
2372 case BFD_RELOC_X86_64_GOTPC32
:
2373 other
= BFD_RELOC_X86_64_GOTPC64
;
2375 case BFD_RELOC_X86_64_GOTPCREL
:
2376 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2378 case BFD_RELOC_X86_64_TPOFF32
:
2379 other
= BFD_RELOC_X86_64_TPOFF64
;
2381 case BFD_RELOC_X86_64_DTPOFF32
:
2382 other
= BFD_RELOC_X86_64_DTPOFF64
;
2388 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2389 if (size
== 4 && flag_code
!= CODE_64BIT
)
2392 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2394 as_bad (_("unknown relocation (%u)"), other
);
2395 else if (size
!= bfd_get_reloc_size (reloc
))
2396 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2397 bfd_get_reloc_size (reloc
),
2399 else if (pcrel
&& !reloc
->pc_relative
)
2400 as_bad (_("non-pc-relative relocation for pc-relative field"));
2401 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2403 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2405 as_bad (_("relocated field and relocation type differ in signedness"));
2414 as_bad (_("there are no unsigned pc-relative relocations"));
2417 case 1: return BFD_RELOC_8_PCREL
;
2418 case 2: return BFD_RELOC_16_PCREL
;
2419 case 4: return BFD_RELOC_32_PCREL
;
2420 case 8: return BFD_RELOC_64_PCREL
;
2422 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2429 case 4: return BFD_RELOC_X86_64_32S
;
2434 case 1: return BFD_RELOC_8
;
2435 case 2: return BFD_RELOC_16
;
2436 case 4: return BFD_RELOC_32
;
2437 case 8: return BFD_RELOC_64
;
2439 as_bad (_("cannot do %s %u byte relocation"),
2440 sign
> 0 ? "signed" : "unsigned", size
);
2444 return BFD_RELOC_NONE
;
2447 /* Here we decide which fixups can be adjusted to make them relative to
2448 the beginning of the section instead of the symbol. Basically we need
2449 to make sure that the dynamic relocations are done correctly, so in
2450 some cases we force the original symbol to be used. */
2453 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2455 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2459 /* Don't adjust pc-relative references to merge sections in 64-bit
2461 if (use_rela_relocations
2462 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2466 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2467 and changed later by validate_fix. */
2468 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2469 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2472 /* adjust_reloc_syms doesn't know about the GOT. */
2473 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2474 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2475 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2476 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2477 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2478 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2479 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2480 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2481 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2482 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2483 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2484 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2485 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2486 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2487 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2488 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2489 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2490 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2491 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2492 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2493 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2494 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2495 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2496 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2497 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2498 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2499 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2500 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2507 intel_float_operand (const char *mnemonic
)
2509 /* Note that the value returned is meaningful only for opcodes with (memory)
2510 operands, hence the code here is free to improperly handle opcodes that
2511 have no operands (for better performance and smaller code). */
2513 if (mnemonic
[0] != 'f')
2514 return 0; /* non-math */
2516 switch (mnemonic
[1])
2518 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2519 the fs segment override prefix not currently handled because no
2520 call path can make opcodes without operands get here */
2522 return 2 /* integer op */;
2524 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2525 return 3; /* fldcw/fldenv */
2528 if (mnemonic
[2] != 'o' /* fnop */)
2529 return 3; /* non-waiting control op */
2532 if (mnemonic
[2] == 's')
2533 return 3; /* frstor/frstpm */
2536 if (mnemonic
[2] == 'a')
2537 return 3; /* fsave */
2538 if (mnemonic
[2] == 't')
2540 switch (mnemonic
[3])
2542 case 'c': /* fstcw */
2543 case 'd': /* fstdw */
2544 case 'e': /* fstenv */
2545 case 's': /* fsts[gw] */
2551 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2552 return 0; /* fxsave/fxrstor are not really math ops */
2559 /* Build the VEX prefix. */
2562 build_vex_prefix (const template *t
)
2564 unsigned int register_specifier
;
2565 unsigned int implied_prefix
;
2566 unsigned int vector_length
;
2568 /* Check register specifier. */
2569 if (i
.vex
.register_specifier
)
2571 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2572 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2573 register_specifier
+= 8;
2574 register_specifier
= ~register_specifier
& 0xf;
2577 register_specifier
= 0xf;
2579 /* Use 2-byte VEX prefix by swappping destination and source
2582 && i
.operands
== i
.reg_operands
2583 && i
.tm
.opcode_modifier
.vex0f
2584 && i
.tm
.opcode_modifier
.s
2587 unsigned int xchg
= i
.operands
- 1;
2588 union i386_op temp_op
;
2589 i386_operand_type temp_type
;
2591 temp_type
= i
.types
[xchg
];
2592 i
.types
[xchg
] = i
.types
[0];
2593 i
.types
[0] = temp_type
;
2594 temp_op
= i
.op
[xchg
];
2595 i
.op
[xchg
] = i
.op
[0];
2598 assert (i
.rm
.mode
== 3);
2602 i
.rm
.regmem
= i
.rm
.reg
;
2605 /* Use the next insn. */
2609 vector_length
= i
.tm
.opcode_modifier
.vex256
? 1 : 0;
2611 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2616 case DATA_PREFIX_OPCODE
:
2619 case REPE_PREFIX_OPCODE
:
2622 case REPNE_PREFIX_OPCODE
:
2629 /* Use 2-byte VEX prefix if possible. */
2630 if (i
.tm
.opcode_modifier
.vex0f
2631 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2633 /* 2-byte VEX prefix. */
2637 i
.vex
.bytes
[0] = 0xc5;
2639 /* Check the REX.R bit. */
2640 r
= (i
.rex
& REX_R
) ? 0 : 1;
2641 i
.vex
.bytes
[1] = (r
<< 7
2642 | register_specifier
<< 3
2643 | vector_length
<< 2
2648 /* 3-byte VEX prefix. */
2651 if (i
.tm
.opcode_modifier
.vex0f
)
2653 else if (i
.tm
.opcode_modifier
.vex0f38
)
2655 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2661 i
.vex
.bytes
[0] = 0xc4;
2663 /* The high 3 bits of the second VEX byte are 1's compliment
2664 of RXB bits from REX. */
2665 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2667 /* Check the REX.W bit. */
2668 w
= (i
.rex
& REX_W
) ? 1 : 0;
2669 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2674 if (i
.tm
.opcode_modifier
.vexw1
)
2678 i
.vex
.bytes
[2] = (w
<< 7
2679 | register_specifier
<< 3
2680 | vector_length
<< 2
2686 process_immext (void)
2690 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2692 /* SSE3 Instructions have the fixed operands with an opcode
2693 suffix which is coded in the same place as an 8-bit immediate
2694 field would be. Here we check those operands and remove them
2698 for (x
= 0; x
< i
.operands
; x
++)
2699 if (i
.op
[x
].regs
->reg_num
!= x
)
2700 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2701 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2707 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2708 which is coded in the same place as an 8-bit immediate field
2709 would be. Here we fake an 8-bit immediate operand from the
2710 opcode suffix stored in tm.extension_opcode.
2712 SSE5 and AVX instructions also use this encoding, for some of
2713 3 argument instructions. */
2715 assert (i
.imm_operands
== 0
2717 || (i
.tm
.cpu_flags
.bitfield
.cpusse5
2719 || (i
.tm
.opcode_modifier
.vex
2720 && i
.operands
<= 4)));
2722 exp
= &im_expressions
[i
.imm_operands
++];
2723 i
.op
[i
.operands
].imms
= exp
;
2724 i
.types
[i
.operands
] = imm8
;
2726 exp
->X_op
= O_constant
;
2727 exp
->X_add_number
= i
.tm
.extension_opcode
;
2728 i
.tm
.extension_opcode
= None
;
2731 /* This is the guts of the machine-dependent assembler. LINE points to a
2732 machine dependent instruction. This function is supposed to emit
2733 the frags/bytes it assembles to. */
2736 md_assemble (char *line
)
2739 char mnemonic
[MAX_MNEM_SIZE
];
2742 /* Initialize globals. */
2743 memset (&i
, '\0', sizeof (i
));
2744 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2745 i
.reloc
[j
] = NO_RELOC
;
2746 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2747 memset (im_expressions
, '\0', sizeof (im_expressions
));
2748 save_stack_p
= save_stack
;
2750 /* First parse an instruction mnemonic & call i386_operand for the operands.
2751 We assume that the scrubber has arranged it so that line[0] is the valid
2752 start of a (possibly prefixed) mnemonic. */
2754 line
= parse_insn (line
, mnemonic
);
2758 line
= parse_operands (line
, mnemonic
);
2762 /* Now we've parsed the mnemonic into a set of templates, and have the
2763 operands at hand. */
2765 /* All intel opcodes have reversed operands except for "bound" and
2766 "enter". We also don't reverse intersegment "jmp" and "call"
2767 instructions with 2 immediate operands so that the immediate segment
2768 precedes the offset, as it does when in AT&T mode. */
2771 && (strcmp (mnemonic
, "bound") != 0)
2772 && (strcmp (mnemonic
, "invlpga") != 0)
2773 && !(operand_type_check (i
.types
[0], imm
)
2774 && operand_type_check (i
.types
[1], imm
)))
2777 /* The order of the immediates should be reversed
2778 for 2 immediates extrq and insertq instructions */
2779 if (i
.imm_operands
== 2
2780 && (strcmp (mnemonic
, "extrq") == 0
2781 || strcmp (mnemonic
, "insertq") == 0))
2782 swap_2_operands (0, 1);
2787 /* Don't optimize displacement for movabs since it only takes 64bit
2790 && (flag_code
!= CODE_64BIT
2791 || strcmp (mnemonic
, "movabs") != 0))
2794 /* Next, we find a template that matches the given insn,
2795 making sure the overlap of the given operands types is consistent
2796 with the template operand types. */
2798 if (!(t
= match_template ()))
2801 if (sse_check
!= sse_check_none
2802 && !i
.tm
.opcode_modifier
.noavx
2803 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2804 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2805 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2806 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2807 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2808 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2810 (sse_check
== sse_check_warning
2812 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2815 /* Zap movzx and movsx suffix. The suffix has been set from
2816 "word ptr" or "byte ptr" on the source operand in Intel syntax
2817 or extracted from mnemonic in AT&T syntax. But we'll use
2818 the destination register to choose the suffix for encoding. */
2819 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2821 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2822 there is no suffix, the default will be byte extension. */
2823 if (i
.reg_operands
!= 2
2826 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2831 if (i
.tm
.opcode_modifier
.fwait
)
2832 if (!add_prefix (FWAIT_OPCODE
))
2835 /* Check string instruction segment overrides. */
2836 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2838 if (!check_string ())
2840 i
.disp_operands
= 0;
2843 if (!process_suffix ())
2846 /* Make still unresolved immediate matches conform to size of immediate
2847 given in i.suffix. */
2848 if (!finalize_imm ())
2851 if (i
.types
[0].bitfield
.imm1
)
2852 i
.imm_operands
= 0; /* kludge for shift insns. */
2854 for (j
= 0; j
< 3; j
++)
2855 if (i
.types
[j
].bitfield
.inoutportreg
2856 || i
.types
[j
].bitfield
.shiftcount
2857 || i
.types
[j
].bitfield
.acc
2858 || i
.types
[j
].bitfield
.floatacc
)
2861 /* ImmExt should be processed after SSE2AVX. */
2862 if (!i
.tm
.opcode_modifier
.sse2avx
2863 && i
.tm
.opcode_modifier
.immext
)
2866 /* For insns with operands there are more diddles to do to the opcode. */
2869 if (!process_operands ())
2872 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2874 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2875 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2878 if (i
.tm
.opcode_modifier
.vex
)
2879 build_vex_prefix (t
);
2881 /* Handle conversion of 'int $3' --> special int3 insn. */
2882 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2884 i
.tm
.base_opcode
= INT3_OPCODE
;
2888 if ((i
.tm
.opcode_modifier
.jump
2889 || i
.tm
.opcode_modifier
.jumpbyte
2890 || i
.tm
.opcode_modifier
.jumpdword
)
2891 && i
.op
[0].disps
->X_op
== O_constant
)
2893 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2894 the absolute address given by the constant. Since ix86 jumps and
2895 calls are pc relative, we need to generate a reloc. */
2896 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2897 i
.op
[0].disps
->X_op
= O_symbol
;
2900 if (i
.tm
.opcode_modifier
.rex64
)
2903 /* For 8 bit registers we need an empty rex prefix. Also if the
2904 instruction already has a prefix, we need to convert old
2905 registers to new ones. */
2907 if ((i
.types
[0].bitfield
.reg8
2908 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2909 || (i
.types
[1].bitfield
.reg8
2910 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2911 || ((i
.types
[0].bitfield
.reg8
2912 || i
.types
[1].bitfield
.reg8
)
2917 i
.rex
|= REX_OPCODE
;
2918 for (x
= 0; x
< 2; x
++)
2920 /* Look for 8 bit operand that uses old registers. */
2921 if (i
.types
[x
].bitfield
.reg8
2922 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2924 /* In case it is "hi" register, give up. */
2925 if (i
.op
[x
].regs
->reg_num
> 3)
2926 as_bad (_("can't encode register '%s%s' in an "
2927 "instruction requiring REX prefix."),
2928 register_prefix
, i
.op
[x
].regs
->reg_name
);
2930 /* Otherwise it is equivalent to the extended register.
2931 Since the encoding doesn't change this is merely
2932 cosmetic cleanup for debug output. */
2934 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2939 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2941 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
2946 else if (i
.rex
!= 0)
2947 add_prefix (REX_OPCODE
| i
.rex
);
2949 /* We are ready to output the insn. */
2954 parse_insn (char *line
, char *mnemonic
)
2957 char *token_start
= l
;
2963 /* Non-zero if we found a prefix only acceptable with string insns. */
2964 const char *expecting_string_instruction
= NULL
;
2969 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
2974 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
2976 as_bad (_("no such instruction: `%s'"), token_start
);
2981 if (!is_space_char (*l
)
2982 && *l
!= END_OF_INSN
2984 || (*l
!= PREFIX_SEPARATOR
2987 as_bad (_("invalid character %s in mnemonic"),
2988 output_invalid (*l
));
2991 if (token_start
== l
)
2993 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
2994 as_bad (_("expecting prefix; got nothing"));
2996 as_bad (_("expecting mnemonic; got nothing"));
3000 /* Look up instruction (or prefix) via hash table. */
3001 current_templates
= hash_find (op_hash
, mnemonic
);
3003 if (*l
!= END_OF_INSN
3004 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3005 && current_templates
3006 && current_templates
->start
->opcode_modifier
.isprefix
)
3008 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3010 as_bad ((flag_code
!= CODE_64BIT
3011 ? _("`%s' is only supported in 64-bit mode")
3012 : _("`%s' is not supported in 64-bit mode")),
3013 current_templates
->start
->name
);
3016 /* If we are in 16-bit mode, do not allow addr16 or data16.
3017 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3018 if ((current_templates
->start
->opcode_modifier
.size16
3019 || current_templates
->start
->opcode_modifier
.size32
)
3020 && flag_code
!= CODE_64BIT
3021 && (current_templates
->start
->opcode_modifier
.size32
3022 ^ (flag_code
== CODE_16BIT
)))
3024 as_bad (_("redundant %s prefix"),
3025 current_templates
->start
->name
);
3028 /* Add prefix, checking for repeated prefixes. */
3029 switch (add_prefix (current_templates
->start
->base_opcode
))
3034 expecting_string_instruction
= current_templates
->start
->name
;
3037 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3044 if (!current_templates
)
3046 /* Check if we should swap operand in encoding. */
3047 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3053 current_templates
= hash_find (op_hash
, mnemonic
);
3056 if (!current_templates
)
3059 /* See if we can get a match by trimming off a suffix. */
3062 case WORD_MNEM_SUFFIX
:
3063 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3064 i
.suffix
= SHORT_MNEM_SUFFIX
;
3066 case BYTE_MNEM_SUFFIX
:
3067 case QWORD_MNEM_SUFFIX
:
3068 i
.suffix
= mnem_p
[-1];
3070 current_templates
= hash_find (op_hash
, mnemonic
);
3072 case SHORT_MNEM_SUFFIX
:
3073 case LONG_MNEM_SUFFIX
:
3076 i
.suffix
= mnem_p
[-1];
3078 current_templates
= hash_find (op_hash
, mnemonic
);
3086 if (intel_float_operand (mnemonic
) == 1)
3087 i
.suffix
= SHORT_MNEM_SUFFIX
;
3089 i
.suffix
= LONG_MNEM_SUFFIX
;
3091 current_templates
= hash_find (op_hash
, mnemonic
);
3095 if (!current_templates
)
3097 as_bad (_("no such instruction: `%s'"), token_start
);
3102 if (current_templates
->start
->opcode_modifier
.jump
3103 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3105 /* Check for a branch hint. We allow ",pt" and ",pn" for
3106 predict taken and predict not taken respectively.
3107 I'm not sure that branch hints actually do anything on loop
3108 and jcxz insns (JumpByte) for current Pentium4 chips. They
3109 may work in the future and it doesn't hurt to accept them
3111 if (l
[0] == ',' && l
[1] == 'p')
3115 if (!add_prefix (DS_PREFIX_OPCODE
))
3119 else if (l
[2] == 'n')
3121 if (!add_prefix (CS_PREFIX_OPCODE
))
3127 /* Any other comma loses. */
3130 as_bad (_("invalid character %s in mnemonic"),
3131 output_invalid (*l
));
3135 /* Check if instruction is supported on specified architecture. */
3137 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3139 supported
|= cpu_flags_match (t
);
3140 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3144 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3146 as_bad (flag_code
== CODE_64BIT
3147 ? _("`%s' is not supported in 64-bit mode")
3148 : _("`%s' is only supported in 64-bit mode"),
3149 current_templates
->start
->name
);
3152 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3154 as_bad (_("`%s' is not supported on `%s%s'"),
3155 current_templates
->start
->name
, cpu_arch_name
,
3156 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3161 if (!cpu_arch_flags
.bitfield
.cpui386
3162 && (flag_code
!= CODE_16BIT
))
3164 as_warn (_("use .code16 to ensure correct addressing mode"));
3167 /* Check for rep/repne without a string instruction. */
3168 if (expecting_string_instruction
)
3170 static templates override
;
3172 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3173 if (t
->opcode_modifier
.isstring
)
3175 if (t
>= current_templates
->end
)
3177 as_bad (_("expecting string instruction after `%s'"),
3178 expecting_string_instruction
);
3181 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3182 if (!t
->opcode_modifier
.isstring
)
3185 current_templates
= &override
;
3192 parse_operands (char *l
, const char *mnemonic
)
3196 /* 1 if operand is pending after ','. */
3197 unsigned int expecting_operand
= 0;
3199 /* Non-zero if operand parens not balanced. */
3200 unsigned int paren_not_balanced
;
3202 while (*l
!= END_OF_INSN
)
3204 /* Skip optional white space before operand. */
3205 if (is_space_char (*l
))
3207 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3209 as_bad (_("invalid character %s before operand %d"),
3210 output_invalid (*l
),
3214 token_start
= l
; /* after white space */
3215 paren_not_balanced
= 0;
3216 while (paren_not_balanced
|| *l
!= ',')
3218 if (*l
== END_OF_INSN
)
3220 if (paren_not_balanced
)
3223 as_bad (_("unbalanced parenthesis in operand %d."),
3226 as_bad (_("unbalanced brackets in operand %d."),
3231 break; /* we are done */
3233 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3235 as_bad (_("invalid character %s in operand %d"),
3236 output_invalid (*l
),
3243 ++paren_not_balanced
;
3245 --paren_not_balanced
;
3250 ++paren_not_balanced
;
3252 --paren_not_balanced
;
3256 if (l
!= token_start
)
3257 { /* Yes, we've read in another operand. */
3258 unsigned int operand_ok
;
3259 this_operand
= i
.operands
++;
3260 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3261 if (i
.operands
> MAX_OPERANDS
)
3263 as_bad (_("spurious operands; (%d operands/instruction max)"),
3267 /* Now parse operand adding info to 'i' as we go along. */
3268 END_STRING_AND_SAVE (l
);
3272 i386_intel_operand (token_start
,
3273 intel_float_operand (mnemonic
));
3275 operand_ok
= i386_att_operand (token_start
);
3277 RESTORE_END_STRING (l
);
3283 if (expecting_operand
)
3285 expecting_operand_after_comma
:
3286 as_bad (_("expecting operand after ','; got nothing"));
3291 as_bad (_("expecting operand before ','; got nothing"));
3296 /* Now *l must be either ',' or END_OF_INSN. */
3299 if (*++l
== END_OF_INSN
)
3301 /* Just skip it, if it's \n complain. */
3302 goto expecting_operand_after_comma
;
3304 expecting_operand
= 1;
3311 swap_2_operands (int xchg1
, int xchg2
)
3313 union i386_op temp_op
;
3314 i386_operand_type temp_type
;
3315 enum bfd_reloc_code_real temp_reloc
;
3317 temp_type
= i
.types
[xchg2
];
3318 i
.types
[xchg2
] = i
.types
[xchg1
];
3319 i
.types
[xchg1
] = temp_type
;
3320 temp_op
= i
.op
[xchg2
];
3321 i
.op
[xchg2
] = i
.op
[xchg1
];
3322 i
.op
[xchg1
] = temp_op
;
3323 temp_reloc
= i
.reloc
[xchg2
];
3324 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3325 i
.reloc
[xchg1
] = temp_reloc
;
3329 swap_operands (void)
3335 swap_2_operands (1, i
.operands
- 2);
3338 swap_2_operands (0, i
.operands
- 1);
3344 if (i
.mem_operands
== 2)
3346 const seg_entry
*temp_seg
;
3347 temp_seg
= i
.seg
[0];
3348 i
.seg
[0] = i
.seg
[1];
3349 i
.seg
[1] = temp_seg
;
3353 /* Try to ensure constant immediates are represented in the smallest
3358 char guess_suffix
= 0;
3362 guess_suffix
= i
.suffix
;
3363 else if (i
.reg_operands
)
3365 /* Figure out a suffix from the last register operand specified.
3366 We can't do this properly yet, ie. excluding InOutPortReg,
3367 but the following works for instructions with immediates.
3368 In any case, we can't set i.suffix yet. */
3369 for (op
= i
.operands
; --op
>= 0;)
3370 if (i
.types
[op
].bitfield
.reg8
)
3372 guess_suffix
= BYTE_MNEM_SUFFIX
;
3375 else if (i
.types
[op
].bitfield
.reg16
)
3377 guess_suffix
= WORD_MNEM_SUFFIX
;
3380 else if (i
.types
[op
].bitfield
.reg32
)
3382 guess_suffix
= LONG_MNEM_SUFFIX
;
3385 else if (i
.types
[op
].bitfield
.reg64
)
3387 guess_suffix
= QWORD_MNEM_SUFFIX
;
3391 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3392 guess_suffix
= WORD_MNEM_SUFFIX
;
3394 for (op
= i
.operands
; --op
>= 0;)
3395 if (operand_type_check (i
.types
[op
], imm
))
3397 switch (i
.op
[op
].imms
->X_op
)
3400 /* If a suffix is given, this operand may be shortened. */
3401 switch (guess_suffix
)
3403 case LONG_MNEM_SUFFIX
:
3404 i
.types
[op
].bitfield
.imm32
= 1;
3405 i
.types
[op
].bitfield
.imm64
= 1;
3407 case WORD_MNEM_SUFFIX
:
3408 i
.types
[op
].bitfield
.imm16
= 1;
3409 i
.types
[op
].bitfield
.imm32
= 1;
3410 i
.types
[op
].bitfield
.imm32s
= 1;
3411 i
.types
[op
].bitfield
.imm64
= 1;
3413 case BYTE_MNEM_SUFFIX
:
3414 i
.types
[op
].bitfield
.imm8
= 1;
3415 i
.types
[op
].bitfield
.imm8s
= 1;
3416 i
.types
[op
].bitfield
.imm16
= 1;
3417 i
.types
[op
].bitfield
.imm32
= 1;
3418 i
.types
[op
].bitfield
.imm32s
= 1;
3419 i
.types
[op
].bitfield
.imm64
= 1;
3423 /* If this operand is at most 16 bits, convert it
3424 to a signed 16 bit number before trying to see
3425 whether it will fit in an even smaller size.
3426 This allows a 16-bit operand such as $0xffe0 to
3427 be recognised as within Imm8S range. */
3428 if ((i
.types
[op
].bitfield
.imm16
)
3429 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3431 i
.op
[op
].imms
->X_add_number
=
3432 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3434 if ((i
.types
[op
].bitfield
.imm32
)
3435 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3438 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3439 ^ ((offsetT
) 1 << 31))
3440 - ((offsetT
) 1 << 31));
3443 = operand_type_or (i
.types
[op
],
3444 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3446 /* We must avoid matching of Imm32 templates when 64bit
3447 only immediate is available. */
3448 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3449 i
.types
[op
].bitfield
.imm32
= 0;
3456 /* Symbols and expressions. */
3458 /* Convert symbolic operand to proper sizes for matching, but don't
3459 prevent matching a set of insns that only supports sizes other
3460 than those matching the insn suffix. */
3462 i386_operand_type mask
, allowed
;
3465 operand_type_set (&mask
, 0);
3466 operand_type_set (&allowed
, 0);
3468 for (t
= current_templates
->start
;
3469 t
< current_templates
->end
;
3471 allowed
= operand_type_or (allowed
,
3472 t
->operand_types
[op
]);
3473 switch (guess_suffix
)
3475 case QWORD_MNEM_SUFFIX
:
3476 mask
.bitfield
.imm64
= 1;
3477 mask
.bitfield
.imm32s
= 1;
3479 case LONG_MNEM_SUFFIX
:
3480 mask
.bitfield
.imm32
= 1;
3482 case WORD_MNEM_SUFFIX
:
3483 mask
.bitfield
.imm16
= 1;
3485 case BYTE_MNEM_SUFFIX
:
3486 mask
.bitfield
.imm8
= 1;
3491 allowed
= operand_type_and (mask
, allowed
);
3492 if (!operand_type_all_zero (&allowed
))
3493 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3500 /* Try to use the smallest displacement type too. */
3502 optimize_disp (void)
3506 for (op
= i
.operands
; --op
>= 0;)
3507 if (operand_type_check (i
.types
[op
], disp
))
3509 if (i
.op
[op
].disps
->X_op
== O_constant
)
3511 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3513 if (i
.types
[op
].bitfield
.disp16
3514 && (disp
& ~(offsetT
) 0xffff) == 0)
3516 /* If this operand is at most 16 bits, convert
3517 to a signed 16 bit number and don't use 64bit
3519 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3520 i
.types
[op
].bitfield
.disp64
= 0;
3522 if (i
.types
[op
].bitfield
.disp32
3523 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3525 /* If this operand is at most 32 bits, convert
3526 to a signed 32 bit number and don't use 64bit
3528 disp
&= (((offsetT
) 2 << 31) - 1);
3529 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3530 i
.types
[op
].bitfield
.disp64
= 0;
3532 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3534 i
.types
[op
].bitfield
.disp8
= 0;
3535 i
.types
[op
].bitfield
.disp16
= 0;
3536 i
.types
[op
].bitfield
.disp32
= 0;
3537 i
.types
[op
].bitfield
.disp32s
= 0;
3538 i
.types
[op
].bitfield
.disp64
= 0;
3542 else if (flag_code
== CODE_64BIT
)
3544 if (fits_in_signed_long (disp
))
3546 i
.types
[op
].bitfield
.disp64
= 0;
3547 i
.types
[op
].bitfield
.disp32s
= 1;
3549 if (fits_in_unsigned_long (disp
))
3550 i
.types
[op
].bitfield
.disp32
= 1;
3552 if ((i
.types
[op
].bitfield
.disp32
3553 || i
.types
[op
].bitfield
.disp32s
3554 || i
.types
[op
].bitfield
.disp16
)
3555 && fits_in_signed_byte (disp
))
3556 i
.types
[op
].bitfield
.disp8
= 1;
3558 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3559 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3561 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3562 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3563 i
.types
[op
].bitfield
.disp8
= 0;
3564 i
.types
[op
].bitfield
.disp16
= 0;
3565 i
.types
[op
].bitfield
.disp32
= 0;
3566 i
.types
[op
].bitfield
.disp32s
= 0;
3567 i
.types
[op
].bitfield
.disp64
= 0;
3570 /* We only support 64bit displacement on constants. */
3571 i
.types
[op
].bitfield
.disp64
= 0;
3575 /* Check if operands are valid for the instrucrtion. Update VEX
3579 VEX_check_operands (const template *t
)
3581 if (!t
->opcode_modifier
.vex
)
3584 /* Only check VEX_Imm4, which must be the first operand. */
3585 if (t
->operand_types
[0].bitfield
.vex_imm4
)
3587 if (i
.op
[0].imms
->X_op
!= O_constant
3588 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
3591 /* Turn off Imm8 so that update_imm won't complain. */
3592 i
.types
[0] = vex_imm4
;
3598 static const template *
3599 match_template (void)
3601 /* Points to template once we've found it. */
3603 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3604 i386_operand_type overlap4
;
3605 unsigned int found_reverse_match
;
3606 i386_opcode_modifier suffix_check
;
3607 i386_operand_type operand_types
[MAX_OPERANDS
];
3608 int addr_prefix_disp
;
3610 unsigned int found_cpu_match
;
3611 unsigned int check_register
;
3613 #if MAX_OPERANDS != 5
3614 # error "MAX_OPERANDS must be 5."
3617 found_reverse_match
= 0;
3618 addr_prefix_disp
= -1;
3620 memset (&suffix_check
, 0, sizeof (suffix_check
));
3621 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3622 suffix_check
.no_bsuf
= 1;
3623 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3624 suffix_check
.no_wsuf
= 1;
3625 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3626 suffix_check
.no_ssuf
= 1;
3627 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3628 suffix_check
.no_lsuf
= 1;
3629 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3630 suffix_check
.no_qsuf
= 1;
3631 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3632 suffix_check
.no_ldsuf
= 1;
3634 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3636 addr_prefix_disp
= -1;
3638 /* Must have right number of operands. */
3639 if (i
.operands
!= t
->operands
)
3642 /* Check processor support. */
3643 found_cpu_match
= (cpu_flags_match (t
)
3644 == CPU_FLAGS_PERFECT_MATCH
);
3645 if (!found_cpu_match
)
3648 /* Check old gcc support. */
3649 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3652 /* Check AT&T mnemonic. */
3653 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3656 /* Check AT&T syntax Intel syntax. */
3657 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3658 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3661 /* Check the suffix, except for some instructions in intel mode. */
3662 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3663 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3664 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3665 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3666 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3667 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3668 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3671 if (!operand_size_match (t
))
3674 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3675 operand_types
[j
] = t
->operand_types
[j
];
3677 /* In general, don't allow 64-bit operands in 32-bit mode. */
3678 if (i
.suffix
== QWORD_MNEM_SUFFIX
3679 && flag_code
!= CODE_64BIT
3681 ? (!t
->opcode_modifier
.ignoresize
3682 && !intel_float_operand (t
->name
))
3683 : intel_float_operand (t
->name
) != 2)
3684 && ((!operand_types
[0].bitfield
.regmmx
3685 && !operand_types
[0].bitfield
.regxmm
3686 && !operand_types
[0].bitfield
.regymm
)
3687 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3688 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3689 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3690 && (t
->base_opcode
!= 0x0fc7
3691 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3694 /* In general, don't allow 32-bit operands on pre-386. */
3695 else if (i
.suffix
== LONG_MNEM_SUFFIX
3696 && !cpu_arch_flags
.bitfield
.cpui386
3698 ? (!t
->opcode_modifier
.ignoresize
3699 && !intel_float_operand (t
->name
))
3700 : intel_float_operand (t
->name
) != 2)
3701 && ((!operand_types
[0].bitfield
.regmmx
3702 && !operand_types
[0].bitfield
.regxmm
)
3703 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3704 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3707 /* Do not verify operands when there are none. */
3711 /* We've found a match; break out of loop. */
3715 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3716 into Disp32/Disp16/Disp32 operand. */
3717 if (i
.prefix
[ADDR_PREFIX
] != 0)
3719 /* There should be only one Disp operand. */
3723 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3725 if (operand_types
[j
].bitfield
.disp16
)
3727 addr_prefix_disp
= j
;
3728 operand_types
[j
].bitfield
.disp32
= 1;
3729 operand_types
[j
].bitfield
.disp16
= 0;
3735 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3737 if (operand_types
[j
].bitfield
.disp32
)
3739 addr_prefix_disp
= j
;
3740 operand_types
[j
].bitfield
.disp32
= 0;
3741 operand_types
[j
].bitfield
.disp16
= 1;
3747 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3749 if (operand_types
[j
].bitfield
.disp64
)
3751 addr_prefix_disp
= j
;
3752 operand_types
[j
].bitfield
.disp64
= 0;
3753 operand_types
[j
].bitfield
.disp32
= 1;
3761 /* We check register size only if size of operands can be
3762 encoded the canonical way. */
3763 check_register
= t
->opcode_modifier
.w
;
3764 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3765 switch (t
->operands
)
3768 if (!operand_type_match (overlap0
, i
.types
[0]))
3772 /* xchg %eax, %eax is a special case. It is an aliase for nop
3773 only in 32bit mode and we can use opcode 0x90. In 64bit
3774 mode, we can't use 0x90 for xchg %eax, %eax since it should
3775 zero-extend %eax to %rax. */
3776 if (flag_code
== CODE_64BIT
3777 && t
->base_opcode
== 0x90
3778 && operand_type_equal (&i
.types
[0], &acc32
)
3779 && operand_type_equal (&i
.types
[1], &acc32
))
3783 /* If we swap operand in encoding, we either match
3784 the next one or reverse direction of operands. */
3785 if (t
->opcode_modifier
.s
)
3787 else if (t
->opcode_modifier
.d
)
3792 /* If we swap operand in encoding, we match the next one. */
3793 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
3797 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3798 if (!operand_type_match (overlap0
, i
.types
[0])
3799 || !operand_type_match (overlap1
, i
.types
[1])
3801 && !operand_type_register_match (overlap0
, i
.types
[0],
3803 overlap1
, i
.types
[1],
3806 /* Check if other direction is valid ... */
3807 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3811 /* Try reversing direction of operands. */
3812 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3813 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3814 if (!operand_type_match (overlap0
, i
.types
[0])
3815 || !operand_type_match (overlap1
, i
.types
[1])
3817 && !operand_type_register_match (overlap0
,
3824 /* Does not match either direction. */
3827 /* found_reverse_match holds which of D or FloatDR
3829 if (t
->opcode_modifier
.d
)
3830 found_reverse_match
= Opcode_D
;
3831 else if (t
->opcode_modifier
.floatd
)
3832 found_reverse_match
= Opcode_FloatD
;
3834 found_reverse_match
= 0;
3835 if (t
->opcode_modifier
.floatr
)
3836 found_reverse_match
|= Opcode_FloatR
;
3840 /* Found a forward 2 operand match here. */
3841 switch (t
->operands
)
3844 overlap4
= operand_type_and (i
.types
[4],
3847 overlap3
= operand_type_and (i
.types
[3],
3850 overlap2
= operand_type_and (i
.types
[2],
3855 switch (t
->operands
)
3858 if (!operand_type_match (overlap4
, i
.types
[4])
3859 || !operand_type_register_match (overlap3
,
3867 if (!operand_type_match (overlap3
, i
.types
[3])
3869 && !operand_type_register_match (overlap2
,
3877 /* Here we make use of the fact that there are no
3878 reverse match 3 operand instructions, and all 3
3879 operand instructions only need to be checked for
3880 register consistency between operands 2 and 3. */
3881 if (!operand_type_match (overlap2
, i
.types
[2])
3883 && !operand_type_register_match (overlap1
,
3893 /* Found either forward/reverse 2, 3 or 4 operand match here:
3894 slip through to break. */
3896 if (!found_cpu_match
)
3898 found_reverse_match
= 0;
3902 /* Check if VEX operands are valid. */
3903 if (VEX_check_operands (t
))
3906 /* We've found a match; break out of loop. */
3910 if (t
== current_templates
->end
)
3912 /* We found no match. */
3914 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3915 current_templates
->start
->name
);
3917 as_bad (_("suffix or operands invalid for `%s'"),
3918 current_templates
->start
->name
);
3922 if (!quiet_warnings
)
3925 && (i
.types
[0].bitfield
.jumpabsolute
3926 != operand_types
[0].bitfield
.jumpabsolute
))
3928 as_warn (_("indirect %s without `*'"), t
->name
);
3931 if (t
->opcode_modifier
.isprefix
3932 && t
->opcode_modifier
.ignoresize
)
3934 /* Warn them that a data or address size prefix doesn't
3935 affect assembly of the next line of code. */
3936 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3940 /* Copy the template we found. */
3943 if (addr_prefix_disp
!= -1)
3944 i
.tm
.operand_types
[addr_prefix_disp
]
3945 = operand_types
[addr_prefix_disp
];
3947 if (found_reverse_match
)
3949 /* If we found a reverse match we must alter the opcode
3950 direction bit. found_reverse_match holds bits to change
3951 (different for int & float insns). */
3953 i
.tm
.base_opcode
^= found_reverse_match
;
3955 i
.tm
.operand_types
[0] = operand_types
[1];
3956 i
.tm
.operand_types
[1] = operand_types
[0];
3965 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
3966 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
3968 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
3970 as_bad (_("`%s' operand %d must use `%ses' segment"),
3976 /* There's only ever one segment override allowed per instruction.
3977 This instruction possibly has a legal segment override on the
3978 second operand, so copy the segment to where non-string
3979 instructions store it, allowing common code. */
3980 i
.seg
[0] = i
.seg
[1];
3982 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
3984 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
3986 as_bad (_("`%s' operand %d must use `%ses' segment"),
3997 process_suffix (void)
3999 /* If matched instruction specifies an explicit instruction mnemonic
4001 if (i
.tm
.opcode_modifier
.size16
)
4002 i
.suffix
= WORD_MNEM_SUFFIX
;
4003 else if (i
.tm
.opcode_modifier
.size32
)
4004 i
.suffix
= LONG_MNEM_SUFFIX
;
4005 else if (i
.tm
.opcode_modifier
.size64
)
4006 i
.suffix
= QWORD_MNEM_SUFFIX
;
4007 else if (i
.reg_operands
)
4009 /* If there's no instruction mnemonic suffix we try to invent one
4010 based on register operands. */
4013 /* We take i.suffix from the last register operand specified,
4014 Destination register type is more significant than source
4015 register type. crc32 in SSE4.2 prefers source register
4017 if (i
.tm
.base_opcode
== 0xf20f38f1)
4019 if (i
.types
[0].bitfield
.reg16
)
4020 i
.suffix
= WORD_MNEM_SUFFIX
;
4021 else if (i
.types
[0].bitfield
.reg32
)
4022 i
.suffix
= LONG_MNEM_SUFFIX
;
4023 else if (i
.types
[0].bitfield
.reg64
)
4024 i
.suffix
= QWORD_MNEM_SUFFIX
;
4026 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4028 if (i
.types
[0].bitfield
.reg8
)
4029 i
.suffix
= BYTE_MNEM_SUFFIX
;
4036 if (i
.tm
.base_opcode
== 0xf20f38f1
4037 || i
.tm
.base_opcode
== 0xf20f38f0)
4039 /* We have to know the operand size for crc32. */
4040 as_bad (_("ambiguous memory operand size for `%s`"),
4045 for (op
= i
.operands
; --op
>= 0;)
4046 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4048 if (i
.types
[op
].bitfield
.reg8
)
4050 i
.suffix
= BYTE_MNEM_SUFFIX
;
4053 else if (i
.types
[op
].bitfield
.reg16
)
4055 i
.suffix
= WORD_MNEM_SUFFIX
;
4058 else if (i
.types
[op
].bitfield
.reg32
)
4060 i
.suffix
= LONG_MNEM_SUFFIX
;
4063 else if (i
.types
[op
].bitfield
.reg64
)
4065 i
.suffix
= QWORD_MNEM_SUFFIX
;
4071 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4073 if (!check_byte_reg ())
4076 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4078 if (!check_long_reg ())
4081 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4084 && i
.tm
.opcode_modifier
.ignoresize
4085 && i
.tm
.opcode_modifier
.no_qsuf
)
4087 else if (!check_qword_reg ())
4090 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4092 if (!check_word_reg ())
4095 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4096 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4098 /* Skip if the instruction has x/y suffix. match_template
4099 should check if it is a valid suffix. */
4101 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4102 /* Do nothing if the instruction is going to ignore the prefix. */
4107 else if (i
.tm
.opcode_modifier
.defaultsize
4109 /* exclude fldenv/frstor/fsave/fstenv */
4110 && i
.tm
.opcode_modifier
.no_ssuf
)
4112 i
.suffix
= stackop_size
;
4114 else if (intel_syntax
4116 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4117 || i
.tm
.opcode_modifier
.jumpbyte
4118 || i
.tm
.opcode_modifier
.jumpintersegment
4119 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4120 && i
.tm
.extension_opcode
<= 3)))
4125 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4127 i
.suffix
= QWORD_MNEM_SUFFIX
;
4131 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4132 i
.suffix
= LONG_MNEM_SUFFIX
;
4135 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4136 i
.suffix
= WORD_MNEM_SUFFIX
;
4145 if (i
.tm
.opcode_modifier
.w
)
4147 as_bad (_("no instruction mnemonic suffix given and "
4148 "no register operands; can't size instruction"));
4154 unsigned int suffixes
;
4156 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4157 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4159 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4161 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4163 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4165 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4168 /* There are more than suffix matches. */
4169 if (i
.tm
.opcode_modifier
.w
4170 || ((suffixes
& (suffixes
- 1))
4171 && !i
.tm
.opcode_modifier
.defaultsize
4172 && !i
.tm
.opcode_modifier
.ignoresize
))
4174 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4180 /* Change the opcode based on the operand size given by i.suffix;
4181 We don't need to change things for byte insns. */
4184 && i
.suffix
!= BYTE_MNEM_SUFFIX
4185 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4186 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4188 /* It's not a byte, select word/dword operation. */
4189 if (i
.tm
.opcode_modifier
.w
)
4191 if (i
.tm
.opcode_modifier
.shortform
)
4192 i
.tm
.base_opcode
|= 8;
4194 i
.tm
.base_opcode
|= 1;
4197 /* Now select between word & dword operations via the operand
4198 size prefix, except for instructions that will ignore this
4200 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4202 /* The address size override prefix changes the size of the
4204 if ((flag_code
== CODE_32BIT
4205 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4206 || (flag_code
!= CODE_32BIT
4207 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4208 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4211 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4212 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4213 && !i
.tm
.opcode_modifier
.ignoresize
4214 && !i
.tm
.opcode_modifier
.floatmf
4215 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4216 || (flag_code
== CODE_64BIT
4217 && i
.tm
.opcode_modifier
.jumpbyte
)))
4219 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4221 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4222 prefix
= ADDR_PREFIX_OPCODE
;
4224 if (!add_prefix (prefix
))
4228 /* Set mode64 for an operand. */
4229 if (i
.suffix
== QWORD_MNEM_SUFFIX
4230 && flag_code
== CODE_64BIT
4231 && !i
.tm
.opcode_modifier
.norex64
)
4233 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4234 need rex64. cmpxchg8b is also a special case. */
4235 if (! (i
.operands
== 2
4236 && i
.tm
.base_opcode
== 0x90
4237 && i
.tm
.extension_opcode
== None
4238 && operand_type_equal (&i
.types
[0], &acc64
)
4239 && operand_type_equal (&i
.types
[1], &acc64
))
4240 && ! (i
.operands
== 1
4241 && i
.tm
.base_opcode
== 0xfc7
4242 && i
.tm
.extension_opcode
== 1
4243 && !operand_type_check (i
.types
[0], reg
)
4244 && operand_type_check (i
.types
[0], anymem
)))
4248 /* Size floating point instruction. */
4249 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4250 if (i
.tm
.opcode_modifier
.floatmf
)
4251 i
.tm
.base_opcode
^= 4;
4258 check_byte_reg (void)
4262 for (op
= i
.operands
; --op
>= 0;)
4264 /* If this is an eight bit register, it's OK. If it's the 16 or
4265 32 bit version of an eight bit register, we will just use the
4266 low portion, and that's OK too. */
4267 if (i
.types
[op
].bitfield
.reg8
)
4270 /* Don't generate this warning if not needed. */
4271 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4274 /* crc32 doesn't generate this warning. */
4275 if (i
.tm
.base_opcode
== 0xf20f38f0)
4278 if ((i
.types
[op
].bitfield
.reg16
4279 || i
.types
[op
].bitfield
.reg32
4280 || i
.types
[op
].bitfield
.reg64
)
4281 && i
.op
[op
].regs
->reg_num
< 4)
4283 /* Prohibit these changes in the 64bit mode, since the
4284 lowering is more complicated. */
4285 if (flag_code
== CODE_64BIT
4286 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4288 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4289 register_prefix
, i
.op
[op
].regs
->reg_name
,
4293 #if REGISTER_WARNINGS
4295 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4296 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4298 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4299 ? REGNAM_AL
- REGNAM_AX
4300 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4302 i
.op
[op
].regs
->reg_name
,
4307 /* Any other register is bad. */
4308 if (i
.types
[op
].bitfield
.reg16
4309 || i
.types
[op
].bitfield
.reg32
4310 || i
.types
[op
].bitfield
.reg64
4311 || i
.types
[op
].bitfield
.regmmx
4312 || i
.types
[op
].bitfield
.regxmm
4313 || i
.types
[op
].bitfield
.regymm
4314 || i
.types
[op
].bitfield
.sreg2
4315 || i
.types
[op
].bitfield
.sreg3
4316 || i
.types
[op
].bitfield
.control
4317 || i
.types
[op
].bitfield
.debug
4318 || i
.types
[op
].bitfield
.test
4319 || i
.types
[op
].bitfield
.floatreg
4320 || i
.types
[op
].bitfield
.floatacc
)
4322 as_bad (_("`%s%s' not allowed with `%s%c'"),
4324 i
.op
[op
].regs
->reg_name
,
4334 check_long_reg (void)
4338 for (op
= i
.operands
; --op
>= 0;)
4339 /* Reject eight bit registers, except where the template requires
4340 them. (eg. movzb) */
4341 if (i
.types
[op
].bitfield
.reg8
4342 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4343 || i
.tm
.operand_types
[op
].bitfield
.reg32
4344 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4346 as_bad (_("`%s%s' not allowed with `%s%c'"),
4348 i
.op
[op
].regs
->reg_name
,
4353 /* Warn if the e prefix on a general reg is missing. */
4354 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4355 && i
.types
[op
].bitfield
.reg16
4356 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4357 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4359 /* Prohibit these changes in the 64bit mode, since the
4360 lowering is more complicated. */
4361 if (flag_code
== CODE_64BIT
)
4363 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4364 register_prefix
, i
.op
[op
].regs
->reg_name
,
4368 #if REGISTER_WARNINGS
4370 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4372 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4374 i
.op
[op
].regs
->reg_name
,
4378 /* Warn if the r prefix on a general reg is missing. */
4379 else if (i
.types
[op
].bitfield
.reg64
4380 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4381 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4384 && i
.tm
.opcode_modifier
.toqword
4385 && !i
.types
[0].bitfield
.regxmm
)
4387 /* Convert to QWORD. We want REX byte. */
4388 i
.suffix
= QWORD_MNEM_SUFFIX
;
4392 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4393 register_prefix
, i
.op
[op
].regs
->reg_name
,
4402 check_qword_reg (void)
4406 for (op
= i
.operands
; --op
>= 0; )
4407 /* Reject eight bit registers, except where the template requires
4408 them. (eg. movzb) */
4409 if (i
.types
[op
].bitfield
.reg8
4410 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4411 || i
.tm
.operand_types
[op
].bitfield
.reg32
4412 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4414 as_bad (_("`%s%s' not allowed with `%s%c'"),
4416 i
.op
[op
].regs
->reg_name
,
4421 /* Warn if the e prefix on a general reg is missing. */
4422 else if ((i
.types
[op
].bitfield
.reg16
4423 || i
.types
[op
].bitfield
.reg32
)
4424 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4425 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4427 /* Prohibit these changes in the 64bit mode, since the
4428 lowering is more complicated. */
4430 && i
.tm
.opcode_modifier
.todword
4431 && !i
.types
[0].bitfield
.regxmm
)
4433 /* Convert to DWORD. We don't want REX byte. */
4434 i
.suffix
= LONG_MNEM_SUFFIX
;
4438 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4439 register_prefix
, i
.op
[op
].regs
->reg_name
,
4448 check_word_reg (void)
4451 for (op
= i
.operands
; --op
>= 0;)
4452 /* Reject eight bit registers, except where the template requires
4453 them. (eg. movzb) */
4454 if (i
.types
[op
].bitfield
.reg8
4455 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4456 || i
.tm
.operand_types
[op
].bitfield
.reg32
4457 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4459 as_bad (_("`%s%s' not allowed with `%s%c'"),
4461 i
.op
[op
].regs
->reg_name
,
4466 /* Warn if the e prefix on a general reg is present. */
4467 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4468 && i
.types
[op
].bitfield
.reg32
4469 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4470 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4472 /* Prohibit these changes in the 64bit mode, since the
4473 lowering is more complicated. */
4474 if (flag_code
== CODE_64BIT
)
4476 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4477 register_prefix
, i
.op
[op
].regs
->reg_name
,
4482 #if REGISTER_WARNINGS
4483 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4485 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4487 i
.op
[op
].regs
->reg_name
,
4495 update_imm (unsigned int j
)
4497 i386_operand_type overlap
;
4499 overlap
= operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4500 if ((overlap
.bitfield
.imm8
4501 || overlap
.bitfield
.imm8s
4502 || overlap
.bitfield
.imm16
4503 || overlap
.bitfield
.imm32
4504 || overlap
.bitfield
.imm32s
4505 || overlap
.bitfield
.imm64
)
4506 && !operand_type_equal (&overlap
, &imm8
)
4507 && !operand_type_equal (&overlap
, &imm8s
)
4508 && !operand_type_equal (&overlap
, &imm16
)
4509 && !operand_type_equal (&overlap
, &imm32
)
4510 && !operand_type_equal (&overlap
, &imm32s
)
4511 && !operand_type_equal (&overlap
, &imm64
))
4515 i386_operand_type temp
;
4517 operand_type_set (&temp
, 0);
4518 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4520 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4521 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4523 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4524 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4525 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4527 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4528 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4531 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4534 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4535 || operand_type_equal (&overlap
, &imm16_32
)
4536 || operand_type_equal (&overlap
, &imm16_32s
))
4538 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4543 if (!operand_type_equal (&overlap
, &imm8
)
4544 && !operand_type_equal (&overlap
, &imm8s
)
4545 && !operand_type_equal (&overlap
, &imm16
)
4546 && !operand_type_equal (&overlap
, &imm32
)
4547 && !operand_type_equal (&overlap
, &imm32s
)
4548 && !operand_type_equal (&overlap
, &imm64
))
4550 as_bad (_("no instruction mnemonic suffix given; "
4551 "can't determine immediate size"));
4555 i
.types
[j
] = overlap
;
4565 for (j
= 0; j
< 2; j
++)
4566 if (update_imm (j
) == 0)
4569 i
.types
[2] = operand_type_and (i
.types
[2], i
.tm
.operand_types
[2]);
4570 assert (operand_type_check (i
.types
[2], imm
) == 0);
4578 i
.drex
.modrm_reg
= 0;
4579 i
.drex
.modrm_regmem
= 0;
4581 /* SSE5 4 operand instructions must have the destination the same as
4582 one of the inputs. Figure out the destination register and cache
4583 it away in the drex field, and remember which fields to use for
4585 if (i
.tm
.opcode_modifier
.drex
4586 && i
.tm
.opcode_modifier
.drexv
4589 i
.tm
.extension_opcode
= None
;
4591 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4592 if (i
.types
[0].bitfield
.regxmm
!= 0
4593 && i
.types
[1].bitfield
.regxmm
!= 0
4594 && i
.types
[2].bitfield
.regxmm
!= 0
4595 && i
.types
[3].bitfield
.regxmm
!= 0
4596 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4597 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4599 /* Clear the arguments that are stored in drex. */
4600 operand_type_set (&i
.types
[0], 0);
4601 operand_type_set (&i
.types
[3], 0);
4602 i
.reg_operands
-= 2;
4604 /* There are two different ways to encode a 4 operand
4605 instruction with all registers that uses OC1 set to
4606 0 or 1. Favor setting OC1 to 0 since this mimics the
4607 actions of other SSE5 assemblers. Use modrm encoding 2
4608 for register/register. Include the high order bit that
4609 is normally stored in the REX byte in the register
4611 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4612 i
.drex
.modrm_reg
= 2;
4613 i
.drex
.modrm_regmem
= 1;
4614 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4615 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4618 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4619 else if (i
.types
[0].bitfield
.regxmm
!= 0
4620 && i
.types
[1].bitfield
.regxmm
!= 0
4621 && (i
.types
[2].bitfield
.regxmm
4622 || operand_type_check (i
.types
[2], anymem
))
4623 && i
.types
[3].bitfield
.regxmm
!= 0
4624 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4625 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4627 /* clear the arguments that are stored in drex */
4628 operand_type_set (&i
.types
[0], 0);
4629 operand_type_set (&i
.types
[3], 0);
4630 i
.reg_operands
-= 2;
4632 /* Specify the modrm encoding for memory addressing. Include
4633 the high order bit that is normally stored in the REX byte
4634 in the register field. */
4635 i
.tm
.extension_opcode
= DREX_X1_X2_XMEM_X1
;
4636 i
.drex
.modrm_reg
= 1;
4637 i
.drex
.modrm_regmem
= 2;
4638 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4639 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4642 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4643 else if (i
.types
[0].bitfield
.regxmm
!= 0
4644 && operand_type_check (i
.types
[1], anymem
) != 0
4645 && i
.types
[2].bitfield
.regxmm
!= 0
4646 && i
.types
[3].bitfield
.regxmm
!= 0
4647 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4648 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4650 /* Clear the arguments that are stored in drex. */
4651 operand_type_set (&i
.types
[0], 0);
4652 operand_type_set (&i
.types
[3], 0);
4653 i
.reg_operands
-= 2;
4655 /* Specify the modrm encoding for memory addressing. Include
4656 the high order bit that is normally stored in the REX byte
4657 in the register field. */
4658 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4659 i
.drex
.modrm_reg
= 2;
4660 i
.drex
.modrm_regmem
= 1;
4661 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4662 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4665 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4666 else if (i
.types
[0].bitfield
.regxmm
!= 0
4667 && i
.types
[1].bitfield
.regxmm
!= 0
4668 && i
.types
[2].bitfield
.regxmm
!= 0
4669 && i
.types
[3].bitfield
.regxmm
!= 0
4670 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4671 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4673 /* clear the arguments that are stored in drex */
4674 operand_type_set (&i
.types
[2], 0);
4675 operand_type_set (&i
.types
[3], 0);
4676 i
.reg_operands
-= 2;
4678 /* There are two different ways to encode a 4 operand
4679 instruction with all registers that uses OC1 set to
4680 0 or 1. Favor setting OC1 to 0 since this mimics the
4681 actions of other SSE5 assemblers. Use modrm encoding
4682 2 for register/register. Include the high order bit that
4683 is normally stored in the REX byte in the register
4685 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4686 i
.drex
.modrm_reg
= 1;
4687 i
.drex
.modrm_regmem
= 0;
4689 /* Remember the register, including the upper bits */
4690 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4691 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4694 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4695 else if (i
.types
[0].bitfield
.regxmm
!= 0
4696 && (i
.types
[1].bitfield
.regxmm
4697 || operand_type_check (i
.types
[1], anymem
))
4698 && i
.types
[2].bitfield
.regxmm
!= 0
4699 && i
.types
[3].bitfield
.regxmm
!= 0
4700 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4701 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4703 /* Clear the arguments that are stored in drex. */
4704 operand_type_set (&i
.types
[2], 0);
4705 operand_type_set (&i
.types
[3], 0);
4706 i
.reg_operands
-= 2;
4708 /* Specify the modrm encoding and remember the register
4709 including the bits normally stored in the REX byte. */
4710 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X2
;
4711 i
.drex
.modrm_reg
= 0;
4712 i
.drex
.modrm_regmem
= 1;
4713 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4714 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4717 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4718 else if (operand_type_check (i
.types
[0], anymem
) != 0
4719 && i
.types
[1].bitfield
.regxmm
!= 0
4720 && i
.types
[2].bitfield
.regxmm
!= 0
4721 && i
.types
[3].bitfield
.regxmm
!= 0
4722 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4723 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4725 /* clear the arguments that are stored in drex */
4726 operand_type_set (&i
.types
[2], 0);
4727 operand_type_set (&i
.types
[3], 0);
4728 i
.reg_operands
-= 2;
4730 /* Specify the modrm encoding and remember the register
4731 including the bits normally stored in the REX byte. */
4732 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4733 i
.drex
.modrm_reg
= 1;
4734 i
.drex
.modrm_regmem
= 0;
4735 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4736 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4740 as_bad (_("Incorrect operands for the '%s' instruction"),
4744 /* SSE5 instructions with the DREX byte where the only memory operand
4745 is in the 2nd argument, and the first and last xmm register must
4746 match, and is encoded in the DREX byte. */
4747 else if (i
.tm
.opcode_modifier
.drex
4748 && !i
.tm
.opcode_modifier
.drexv
4751 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4752 if (i
.types
[0].bitfield
.regxmm
!= 0
4753 && (i
.types
[1].bitfield
.regxmm
4754 || operand_type_check(i
.types
[1], anymem
))
4755 && i
.types
[2].bitfield
.regxmm
!= 0
4756 && i
.types
[3].bitfield
.regxmm
!= 0
4757 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4758 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4760 /* clear the arguments that are stored in drex */
4761 operand_type_set (&i
.types
[0], 0);
4762 operand_type_set (&i
.types
[3], 0);
4763 i
.reg_operands
-= 2;
4765 /* Specify the modrm encoding and remember the register
4766 including the high bit normally stored in the REX
4768 i
.drex
.modrm_reg
= 2;
4769 i
.drex
.modrm_regmem
= 1;
4770 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4771 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4775 as_bad (_("Incorrect operands for the '%s' instruction"),
4779 /* SSE5 3 operand instructions that the result is a register, being
4780 either operand can be a memory operand, using OC0 to note which
4781 one is the memory. */
4782 else if (i
.tm
.opcode_modifier
.drex
4783 && i
.tm
.opcode_modifier
.drexv
4786 i
.tm
.extension_opcode
= None
;
4788 /* Case 1: 3 operand insn, src1 = register. */
4789 if (i
.types
[0].bitfield
.regxmm
!= 0
4790 && i
.types
[1].bitfield
.regxmm
!= 0
4791 && i
.types
[2].bitfield
.regxmm
!= 0)
4793 /* Clear the arguments that are stored in drex. */
4794 operand_type_set (&i
.types
[2], 0);
4797 /* Specify the modrm encoding and remember the register
4798 including the high bit normally stored in the REX byte. */
4799 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4800 i
.drex
.modrm_reg
= 1;
4801 i
.drex
.modrm_regmem
= 0;
4802 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4803 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4806 /* Case 2: 3 operand insn, src1 = memory. */
4807 else if (operand_type_check (i
.types
[0], anymem
) != 0
4808 && i
.types
[1].bitfield
.regxmm
!= 0
4809 && i
.types
[2].bitfield
.regxmm
!= 0)
4811 /* Clear the arguments that are stored in drex. */
4812 operand_type_set (&i
.types
[2], 0);
4815 /* Specify the modrm encoding and remember the register
4816 including the high bit normally stored in the REX
4818 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4819 i
.drex
.modrm_reg
= 1;
4820 i
.drex
.modrm_regmem
= 0;
4821 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4822 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4825 /* Case 3: 3 operand insn, src2 = memory. */
4826 else if (i
.types
[0].bitfield
.regxmm
!= 0
4827 && operand_type_check (i
.types
[1], anymem
) != 0
4828 && i
.types
[2].bitfield
.regxmm
!= 0)
4830 /* Clear the arguments that are stored in drex. */
4831 operand_type_set (&i
.types
[2], 0);
4834 /* Specify the modrm encoding and remember the register
4835 including the high bit normally stored in the REX byte. */
4836 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2
;
4837 i
.drex
.modrm_reg
= 0;
4838 i
.drex
.modrm_regmem
= 1;
4839 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4840 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4844 as_bad (_("Incorrect operands for the '%s' instruction"),
4848 /* SSE5 4 operand instructions that are the comparison instructions
4849 where the first operand is the immediate value of the comparison
4851 else if (i
.tm
.opcode_modifier
.drexc
!= 0 && i
.operands
== 4)
4853 /* Case 1: 4 operand insn, src1 = reg/memory. */
4854 if (operand_type_check (i
.types
[0], imm
) != 0
4855 && (i
.types
[1].bitfield
.regxmm
4856 || operand_type_check (i
.types
[1], anymem
))
4857 && i
.types
[2].bitfield
.regxmm
!= 0
4858 && i
.types
[3].bitfield
.regxmm
!= 0)
4860 /* clear the arguments that are stored in drex */
4861 operand_type_set (&i
.types
[3], 0);
4864 /* Specify the modrm encoding and remember the register
4865 including the high bit normally stored in the REX byte. */
4866 i
.drex
.modrm_reg
= 2;
4867 i
.drex
.modrm_regmem
= 1;
4868 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4869 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4872 /* Case 2: 3 operand insn with ImmExt that places the
4873 opcode_extension as an immediate argument. This is used for
4874 all of the varients of comparison that supplies the appropriate
4875 value as part of the instruction. */
4876 else if ((i
.types
[0].bitfield
.regxmm
4877 || operand_type_check (i
.types
[0], anymem
))
4878 && i
.types
[1].bitfield
.regxmm
!= 0
4879 && i
.types
[2].bitfield
.regxmm
!= 0
4880 && operand_type_check (i
.types
[3], imm
) != 0)
4882 /* clear the arguments that are stored in drex */
4883 operand_type_set (&i
.types
[2], 0);
4886 /* Specify the modrm encoding and remember the register
4887 including the high bit normally stored in the REX byte. */
4888 i
.drex
.modrm_reg
= 1;
4889 i
.drex
.modrm_regmem
= 0;
4890 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4891 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4895 as_bad (_("Incorrect operands for the '%s' instruction"),
4899 else if (i
.tm
.opcode_modifier
.drex
4900 || i
.tm
.opcode_modifier
.drexv
4901 || i
.tm
.opcode_modifier
.drexc
)
4902 as_bad (_("Internal error for the '%s' instruction"), i
.tm
.name
);
4906 bad_implicit_operand (int xmm
)
4908 const char *reg
= xmm
? "xmm0" : "ymm0";
4910 as_bad (_("the last operand of `%s' must be `%s%s'"),
4911 i
.tm
.name
, register_prefix
, reg
);
4913 as_bad (_("the first operand of `%s' must be `%s%s'"),
4914 i
.tm
.name
, register_prefix
, reg
);
4919 process_operands (void)
4921 /* Default segment register this instruction will use for memory
4922 accesses. 0 means unknown. This is only for optimizing out
4923 unnecessary segment overrides. */
4924 const seg_entry
*default_seg
= 0;
4926 /* Handle all of the DREX munging that SSE5 needs. */
4927 if (i
.tm
.opcode_modifier
.drex
4928 || i
.tm
.opcode_modifier
.drexv
4929 || i
.tm
.opcode_modifier
.drexc
)
4932 if (i
.tm
.opcode_modifier
.sse2avx
4933 && (i
.tm
.opcode_modifier
.vexnds
4934 || i
.tm
.opcode_modifier
.vexndd
))
4936 unsigned int dup
= i
.operands
;
4937 unsigned int dest
= dup
- 1;
4940 /* The destination must be an xmm register. */
4941 assert (i
.reg_operands
4942 && MAX_OPERANDS
> dup
4943 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4945 if (i
.tm
.opcode_modifier
.firstxmm0
)
4947 /* The first operand is implicit and must be xmm0. */
4948 assert (operand_type_equal (&i
.types
[0], ®xmm
));
4949 if (i
.op
[0].regs
->reg_num
!= 0)
4950 return bad_implicit_operand (1);
4952 if (i
.tm
.opcode_modifier
.vex3sources
)
4954 /* Keep xmm0 for instructions with VEX prefix and 3
4960 /* We remove the first xmm0 and keep the number of
4961 operands unchanged, which in fact duplicates the
4963 for (j
= 1; j
< i
.operands
; j
++)
4965 i
.op
[j
- 1] = i
.op
[j
];
4966 i
.types
[j
- 1] = i
.types
[j
];
4967 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4971 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4973 assert ((MAX_OPERANDS
- 1) > dup
4974 && i
.tm
.opcode_modifier
.vex3sources
);
4976 /* Add the implicit xmm0 for instructions with VEX prefix
4978 for (j
= i
.operands
; j
> 0; j
--)
4980 i
.op
[j
] = i
.op
[j
- 1];
4981 i
.types
[j
] = i
.types
[j
- 1];
4982 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4985 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4986 i
.types
[0] = regxmm
;
4987 i
.tm
.operand_types
[0] = regxmm
;
4990 i
.reg_operands
+= 2;
4995 i
.op
[dup
] = i
.op
[dest
];
4996 i
.types
[dup
] = i
.types
[dest
];
4997 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
5006 i
.op
[dup
] = i
.op
[dest
];
5007 i
.types
[dup
] = i
.types
[dest
];
5008 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
5011 if (i
.tm
.opcode_modifier
.immext
)
5014 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5018 /* The first operand is implicit and must be xmm0/ymm0. */
5019 assert (i
.reg_operands
5020 && (operand_type_equal (&i
.types
[0], ®xmm
)
5021 || operand_type_equal (&i
.types
[0], ®ymm
)));
5022 if (i
.op
[0].regs
->reg_num
!= 0)
5023 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5025 for (j
= 1; j
< i
.operands
; j
++)
5027 i
.op
[j
- 1] = i
.op
[j
];
5028 i
.types
[j
- 1] = i
.types
[j
];
5030 /* We need to adjust fields in i.tm since they are used by
5031 build_modrm_byte. */
5032 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5039 else if (i
.tm
.opcode_modifier
.regkludge
)
5041 /* The imul $imm, %reg instruction is converted into
5042 imul $imm, %reg, %reg, and the clr %reg instruction
5043 is converted into xor %reg, %reg. */
5045 unsigned int first_reg_op
;
5047 if (operand_type_check (i
.types
[0], reg
))
5051 /* Pretend we saw the extra register operand. */
5052 assert (i
.reg_operands
== 1
5053 && i
.op
[first_reg_op
+ 1].regs
== 0);
5054 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5055 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5060 if (i
.tm
.opcode_modifier
.shortform
)
5062 if (i
.types
[0].bitfield
.sreg2
5063 || i
.types
[0].bitfield
.sreg3
)
5065 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5066 && i
.op
[0].regs
->reg_num
== 1)
5068 as_bad (_("you can't `pop %scs'"), register_prefix
);
5071 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5072 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5077 /* The register or float register operand is in operand
5081 if (i
.types
[0].bitfield
.floatreg
5082 || operand_type_check (i
.types
[0], reg
))
5086 /* Register goes in low 3 bits of opcode. */
5087 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5088 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5090 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5092 /* Warn about some common errors, but press on regardless.
5093 The first case can be generated by gcc (<= 2.8.1). */
5094 if (i
.operands
== 2)
5096 /* Reversed arguments on faddp, fsubp, etc. */
5097 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5098 register_prefix
, i
.op
[1].regs
->reg_name
,
5099 register_prefix
, i
.op
[0].regs
->reg_name
);
5103 /* Extraneous `l' suffix on fp insn. */
5104 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5105 register_prefix
, i
.op
[0].regs
->reg_name
);
5110 else if (i
.tm
.opcode_modifier
.modrm
)
5112 /* The opcode is completed (modulo i.tm.extension_opcode which
5113 must be put into the modrm byte). Now, we make the modrm and
5114 index base bytes based on all the info we've collected. */
5116 default_seg
= build_modrm_byte ();
5118 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5122 else if (i
.tm
.opcode_modifier
.isstring
)
5124 /* For the string instructions that allow a segment override
5125 on one of their operands, the default segment is ds. */
5129 if (i
.tm
.base_opcode
== 0x8d /* lea */
5132 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5134 /* If a segment was explicitly specified, and the specified segment
5135 is not the default, use an opcode prefix to select it. If we
5136 never figured out what the default segment is, then default_seg
5137 will be zero at this point, and the specified segment prefix will
5139 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5141 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5147 static const seg_entry
*
5148 build_modrm_byte (void)
5150 const seg_entry
*default_seg
= 0;
5151 unsigned int source
, dest
;
5154 /* The first operand of instructions with VEX prefix and 3 sources
5155 must be VEX_Imm4. */
5156 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
5159 unsigned int nds
, reg
;
5161 dest
= i
.operands
- 1;
5166 /* This instruction must have 4 operands: 4 register operands
5167 or 3 register operands plus 1 memory operand. It must have
5168 VexNDS and VexImmExt. */
5169 assert (i
.operands
== 4
5170 && (i
.reg_operands
== 4
5171 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5172 && i
.tm
.opcode_modifier
.vexnds
5173 && i
.tm
.opcode_modifier
.veximmext
5174 && (operand_type_equal (&i
.tm
.operand_types
[dest
],
5176 || operand_type_equal (&i
.tm
.operand_types
[dest
],
5178 && (operand_type_equal (&i
.tm
.operand_types
[nds
],
5180 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5182 && (operand_type_equal (&i
.tm
.operand_types
[reg
],
5184 || operand_type_equal (&i
.tm
.operand_types
[reg
],
5187 /* Generate an 8bit immediate operand to encode the register
5189 expressionS
*exp
= &im_expressions
[i
.imm_operands
++];
5190 i
.op
[i
.operands
].imms
= exp
;
5191 i
.types
[i
.operands
] = imm8
;
5193 exp
->X_op
= O_constant
;
5195 = ((i
.op
[0].regs
->reg_num
5196 + ((i
.op
[0].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
5198 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5203 /* SSE5 4 operand instructions are encoded in such a way that one of
5204 the inputs must match the destination register. Process_drex hides
5205 the 3rd argument in the drex field, so that by the time we get
5206 here, it looks to GAS as if this is a 2 operand instruction. */
5207 if ((i
.tm
.opcode_modifier
.drex
5208 || i
.tm
.opcode_modifier
.drexv
5209 || i
.tm
.opcode_modifier
.drexc
)
5210 && i
.reg_operands
== 2)
5212 const reg_entry
*reg
= i
.op
[i
.drex
.modrm_reg
].regs
;
5213 const reg_entry
*regmem
= i
.op
[i
.drex
.modrm_regmem
].regs
;
5215 i
.rm
.reg
= reg
->reg_num
;
5216 i
.rm
.regmem
= regmem
->reg_num
;
5218 if ((reg
->reg_flags
& RegRex
) != 0)
5220 if ((regmem
->reg_flags
& RegRex
) != 0)
5224 /* i.reg_operands MUST be the number of real register operands;
5225 implicit registers do not count. If there are 3 register
5226 operands, it must be a instruction with VexNDS. For a
5227 instruction with VexNDD, the destination register is encoded
5228 in VEX prefix. If there are 4 register operands, it must be
5229 a instruction with VEX prefix and 3 sources. */
5230 else if (i
.mem_operands
== 0
5231 && ((i
.reg_operands
== 2
5232 && !i
.tm
.opcode_modifier
.vexndd
)
5233 || (i
.reg_operands
== 3
5234 && i
.tm
.opcode_modifier
.vexnds
)
5235 || (i
.reg_operands
== 4 && vex_3_sources
)))
5243 /* When there are 3 operands, one of them may be immediate,
5244 which may be the first or the last operand. Otherwise,
5245 the first operand must be shift count register (cl) or it
5246 is an instruction with VexNDS. */
5247 assert (i
.imm_operands
== 1
5248 || (i
.imm_operands
== 0
5249 && (i
.tm
.opcode_modifier
.vexnds
5250 || i
.types
[0].bitfield
.shiftcount
)));
5251 if (operand_type_check (i
.types
[0], imm
)
5252 || i
.types
[0].bitfield
.shiftcount
)
5258 /* When there are 4 operands, the first two must be 8bit
5259 immediate operands. The source operand will be the 3rd
5262 For instructions with VexNDS, if the first operand
5263 an imm8, the source operand is the 2nd one. If the last
5264 operand is imm8, the source operand is the first one. */
5265 assert ((i
.imm_operands
== 2
5266 && i
.types
[0].bitfield
.imm8
5267 && i
.types
[1].bitfield
.imm8
)
5268 || (i
.tm
.opcode_modifier
.vexnds
5269 && i
.imm_operands
== 1
5270 && (i
.types
[0].bitfield
.imm8
5271 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5272 if (i
.tm
.opcode_modifier
.vexnds
)
5274 if (i
.types
[0].bitfield
.imm8
)
5292 if (i
.tm
.opcode_modifier
.vexnds
)
5294 /* For instructions with VexNDS, the register-only
5295 source operand must be XMM or YMM register. It is
5296 encoded in VEX prefix. We need to clear RegMem bit
5297 before calling operand_type_equal. */
5298 i386_operand_type op
= i
.tm
.operand_types
[dest
];
5299 op
.bitfield
.regmem
= 0;
5300 if ((dest
+ 1) >= i
.operands
5301 || (!operand_type_equal (&op
, ®xmm
)
5302 && !operand_type_equal (&op
, ®ymm
)))
5304 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5310 /* One of the register operands will be encoded in the i.tm.reg
5311 field, the other in the combined i.tm.mode and i.tm.regmem
5312 fields. If no form of this instruction supports a memory
5313 destination operand, then we assume the source operand may
5314 sometimes be a memory operand and so we need to store the
5315 destination in the i.rm.reg field. */
5316 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5317 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5319 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5320 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5321 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5323 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5328 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5329 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5330 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5332 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5335 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5337 if (!i
.types
[0].bitfield
.control
5338 && !i
.types
[1].bitfield
.control
)
5340 i
.rex
&= ~(REX_R
| REX_B
);
5341 add_prefix (LOCK_PREFIX_OPCODE
);
5345 { /* If it's not 2 reg operands... */
5350 unsigned int fake_zero_displacement
= 0;
5353 /* This has been precalculated for SSE5 instructions
5354 that have a DREX field earlier in process_drex. */
5355 if (i
.tm
.opcode_modifier
.drex
5356 || i
.tm
.opcode_modifier
.drexv
5357 || i
.tm
.opcode_modifier
.drexc
)
5358 op
= i
.drex
.modrm_regmem
;
5361 for (op
= 0; op
< i
.operands
; op
++)
5362 if (operand_type_check (i
.types
[op
], anymem
))
5364 assert (op
< i
.operands
);
5369 if (i
.base_reg
== 0)
5372 if (!i
.disp_operands
)
5373 fake_zero_displacement
= 1;
5374 if (i
.index_reg
== 0)
5376 /* Operand is just <disp> */
5377 if (flag_code
== CODE_64BIT
)
5379 /* 64bit mode overwrites the 32bit absolute
5380 addressing by RIP relative addressing and
5381 absolute addressing is encoded by one of the
5382 redundant SIB forms. */
5383 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5384 i
.sib
.base
= NO_BASE_REGISTER
;
5385 i
.sib
.index
= NO_INDEX_REGISTER
;
5386 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5387 ? disp32s
: disp32
);
5389 else if ((flag_code
== CODE_16BIT
)
5390 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5392 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5393 i
.types
[op
] = disp16
;
5397 i
.rm
.regmem
= NO_BASE_REGISTER
;
5398 i
.types
[op
] = disp32
;
5401 else /* !i.base_reg && i.index_reg */
5403 if (i
.index_reg
->reg_num
== RegEiz
5404 || i
.index_reg
->reg_num
== RegRiz
)
5405 i
.sib
.index
= NO_INDEX_REGISTER
;
5407 i
.sib
.index
= i
.index_reg
->reg_num
;
5408 i
.sib
.base
= NO_BASE_REGISTER
;
5409 i
.sib
.scale
= i
.log2_scale_factor
;
5410 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5411 i
.types
[op
].bitfield
.disp8
= 0;
5412 i
.types
[op
].bitfield
.disp16
= 0;
5413 i
.types
[op
].bitfield
.disp64
= 0;
5414 if (flag_code
!= CODE_64BIT
)
5416 /* Must be 32 bit */
5417 i
.types
[op
].bitfield
.disp32
= 1;
5418 i
.types
[op
].bitfield
.disp32s
= 0;
5422 i
.types
[op
].bitfield
.disp32
= 0;
5423 i
.types
[op
].bitfield
.disp32s
= 1;
5425 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5429 /* RIP addressing for 64bit mode. */
5430 else if (i
.base_reg
->reg_num
== RegRip
||
5431 i
.base_reg
->reg_num
== RegEip
)
5433 i
.rm
.regmem
= NO_BASE_REGISTER
;
5434 i
.types
[op
].bitfield
.disp8
= 0;
5435 i
.types
[op
].bitfield
.disp16
= 0;
5436 i
.types
[op
].bitfield
.disp32
= 0;
5437 i
.types
[op
].bitfield
.disp32s
= 1;
5438 i
.types
[op
].bitfield
.disp64
= 0;
5439 i
.flags
[op
] |= Operand_PCrel
;
5440 if (! i
.disp_operands
)
5441 fake_zero_displacement
= 1;
5443 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5445 switch (i
.base_reg
->reg_num
)
5448 if (i
.index_reg
== 0)
5450 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5451 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5455 if (i
.index_reg
== 0)
5458 if (operand_type_check (i
.types
[op
], disp
) == 0)
5460 /* fake (%bp) into 0(%bp) */
5461 i
.types
[op
].bitfield
.disp8
= 1;
5462 fake_zero_displacement
= 1;
5465 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5466 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5468 default: /* (%si) -> 4 or (%di) -> 5 */
5469 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5471 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5473 else /* i.base_reg and 32/64 bit mode */
5475 if (flag_code
== CODE_64BIT
5476 && operand_type_check (i
.types
[op
], disp
))
5478 i386_operand_type temp
;
5479 operand_type_set (&temp
, 0);
5480 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5482 if (i
.prefix
[ADDR_PREFIX
] == 0)
5483 i
.types
[op
].bitfield
.disp32s
= 1;
5485 i
.types
[op
].bitfield
.disp32
= 1;
5488 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5489 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5491 i
.sib
.base
= i
.base_reg
->reg_num
;
5492 /* x86-64 ignores REX prefix bit here to avoid decoder
5494 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5497 if (i
.disp_operands
== 0)
5499 fake_zero_displacement
= 1;
5500 i
.types
[op
].bitfield
.disp8
= 1;
5503 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5507 i
.sib
.scale
= i
.log2_scale_factor
;
5508 if (i
.index_reg
== 0)
5510 /* <disp>(%esp) becomes two byte modrm with no index
5511 register. We've already stored the code for esp
5512 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5513 Any base register besides %esp will not use the
5514 extra modrm byte. */
5515 i
.sib
.index
= NO_INDEX_REGISTER
;
5519 if (i
.index_reg
->reg_num
== RegEiz
5520 || i
.index_reg
->reg_num
== RegRiz
)
5521 i
.sib
.index
= NO_INDEX_REGISTER
;
5523 i
.sib
.index
= i
.index_reg
->reg_num
;
5524 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5525 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5530 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5531 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5534 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5537 if (fake_zero_displacement
)
5539 /* Fakes a zero displacement assuming that i.types[op]
5540 holds the correct displacement size. */
5543 assert (i
.op
[op
].disps
== 0);
5544 exp
= &disp_expressions
[i
.disp_operands
++];
5545 i
.op
[op
].disps
= exp
;
5546 exp
->X_op
= O_constant
;
5547 exp
->X_add_number
= 0;
5548 exp
->X_add_symbol
= (symbolS
*) 0;
5549 exp
->X_op_symbol
= (symbolS
*) 0;
5557 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5558 (if any) based on i.tm.extension_opcode. Again, we must be
5559 careful to make sure that segment/control/debug/test/MMX
5560 registers are coded into the i.rm.reg field. */
5565 /* This has been precalculated for SSE5 instructions
5566 that have a DREX field earlier in process_drex. */
5567 if (i
.tm
.opcode_modifier
.drex
5568 || i
.tm
.opcode_modifier
.drexv
5569 || i
.tm
.opcode_modifier
.drexc
)
5571 op
= i
.drex
.modrm_reg
;
5572 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5573 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5578 unsigned int vex_reg
= ~0;
5580 for (op
= 0; op
< i
.operands
; op
++)
5581 if (i
.types
[op
].bitfield
.reg8
5582 || i
.types
[op
].bitfield
.reg16
5583 || i
.types
[op
].bitfield
.reg32
5584 || i
.types
[op
].bitfield
.reg64
5585 || i
.types
[op
].bitfield
.regmmx
5586 || i
.types
[op
].bitfield
.regxmm
5587 || i
.types
[op
].bitfield
.regymm
5588 || i
.types
[op
].bitfield
.sreg2
5589 || i
.types
[op
].bitfield
.sreg3
5590 || i
.types
[op
].bitfield
.control
5591 || i
.types
[op
].bitfield
.debug
5592 || i
.types
[op
].bitfield
.test
)
5597 else if (i
.tm
.opcode_modifier
.vexnds
)
5599 /* For instructions with VexNDS, the register-only
5600 source operand is encoded in VEX prefix. */
5601 assert (mem
!= (unsigned int) ~0);
5606 assert (op
< i
.operands
);
5611 assert (vex_reg
< i
.operands
);
5614 else if (i
.tm
.opcode_modifier
.vexndd
)
5616 /* For instructions with VexNDD, there should be
5617 no memory operand and the register destination
5618 is encoded in VEX prefix. */
5619 assert (i
.mem_operands
== 0
5620 && (op
+ 2) == i
.operands
);
5624 assert (op
< i
.operands
);
5626 if (vex_reg
!= (unsigned int) ~0)
5628 assert (i
.reg_operands
== 2);
5630 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5632 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5635 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5638 /* If there is an extension opcode to put here, the
5639 register number must be put into the regmem field. */
5640 if (i
.tm
.extension_opcode
!= None
)
5642 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5643 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5648 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5649 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5654 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5655 must set it to 3 to indicate this is a register operand
5656 in the regmem field. */
5657 if (!i
.mem_operands
)
5661 /* Fill in i.rm.reg field with extension opcode (if any). */
5662 if (i
.tm
.extension_opcode
!= None
5663 && !(i
.tm
.opcode_modifier
.drex
5664 || i
.tm
.opcode_modifier
.drexv
5665 || i
.tm
.opcode_modifier
.drexc
))
5666 i
.rm
.reg
= i
.tm
.extension_opcode
;
5672 output_branch (void)
5677 relax_substateT subtype
;
5682 if (flag_code
== CODE_16BIT
)
5686 if (i
.prefix
[DATA_PREFIX
] != 0)
5692 /* Pentium4 branch hints. */
5693 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5694 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5699 if (i
.prefix
[REX_PREFIX
] != 0)
5705 if (i
.prefixes
!= 0 && !intel_syntax
)
5706 as_warn (_("skipping prefixes on this instruction"));
5708 /* It's always a symbol; End frag & setup for relax.
5709 Make sure there is enough room in this frag for the largest
5710 instruction we may generate in md_convert_frag. This is 2
5711 bytes for the opcode and room for the prefix and largest
5713 frag_grow (prefix
+ 2 + 4);
5714 /* Prefix and 1 opcode byte go in fr_fix. */
5715 p
= frag_more (prefix
+ 1);
5716 if (i
.prefix
[DATA_PREFIX
] != 0)
5717 *p
++ = DATA_PREFIX_OPCODE
;
5718 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5719 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5720 *p
++ = i
.prefix
[SEG_PREFIX
];
5721 if (i
.prefix
[REX_PREFIX
] != 0)
5722 *p
++ = i
.prefix
[REX_PREFIX
];
5723 *p
= i
.tm
.base_opcode
;
5725 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5726 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5727 else if (cpu_arch_flags
.bitfield
.cpui386
)
5728 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5730 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5733 sym
= i
.op
[0].disps
->X_add_symbol
;
5734 off
= i
.op
[0].disps
->X_add_number
;
5736 if (i
.op
[0].disps
->X_op
!= O_constant
5737 && i
.op
[0].disps
->X_op
!= O_symbol
)
5739 /* Handle complex expressions. */
5740 sym
= make_expr_symbol (i
.op
[0].disps
);
5744 /* 1 possible extra opcode + 4 byte displacement go in var part.
5745 Pass reloc in fr_var. */
5746 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5756 if (i
.tm
.opcode_modifier
.jumpbyte
)
5758 /* This is a loop or jecxz type instruction. */
5760 if (i
.prefix
[ADDR_PREFIX
] != 0)
5762 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5765 /* Pentium4 branch hints. */
5766 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5767 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5769 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5778 if (flag_code
== CODE_16BIT
)
5781 if (i
.prefix
[DATA_PREFIX
] != 0)
5783 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5793 if (i
.prefix
[REX_PREFIX
] != 0)
5795 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5799 if (i
.prefixes
!= 0 && !intel_syntax
)
5800 as_warn (_("skipping prefixes on this instruction"));
5802 p
= frag_more (1 + size
);
5803 *p
++ = i
.tm
.base_opcode
;
5805 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5806 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5808 /* All jumps handled here are signed, but don't use a signed limit
5809 check for 32 and 16 bit jumps as we want to allow wrap around at
5810 4G and 64k respectively. */
5812 fixP
->fx_signed
= 1;
5816 output_interseg_jump (void)
5824 if (flag_code
== CODE_16BIT
)
5828 if (i
.prefix
[DATA_PREFIX
] != 0)
5834 if (i
.prefix
[REX_PREFIX
] != 0)
5844 if (i
.prefixes
!= 0 && !intel_syntax
)
5845 as_warn (_("skipping prefixes on this instruction"));
5847 /* 1 opcode; 2 segment; offset */
5848 p
= frag_more (prefix
+ 1 + 2 + size
);
5850 if (i
.prefix
[DATA_PREFIX
] != 0)
5851 *p
++ = DATA_PREFIX_OPCODE
;
5853 if (i
.prefix
[REX_PREFIX
] != 0)
5854 *p
++ = i
.prefix
[REX_PREFIX
];
5856 *p
++ = i
.tm
.base_opcode
;
5857 if (i
.op
[1].imms
->X_op
== O_constant
)
5859 offsetT n
= i
.op
[1].imms
->X_add_number
;
5862 && !fits_in_unsigned_word (n
)
5863 && !fits_in_signed_word (n
))
5865 as_bad (_("16-bit jump out of range"));
5868 md_number_to_chars (p
, n
, size
);
5871 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5872 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5873 if (i
.op
[0].imms
->X_op
!= O_constant
)
5874 as_bad (_("can't handle non absolute segment in `%s'"),
5876 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5882 fragS
*insn_start_frag
;
5883 offsetT insn_start_off
;
5885 /* Tie dwarf2 debug info to the address at the start of the insn.
5886 We can't do this after the insn has been output as the current
5887 frag may have been closed off. eg. by frag_var. */
5888 dwarf2_emit_insn (0);
5890 insn_start_frag
= frag_now
;
5891 insn_start_off
= frag_now_fix ();
5894 if (i
.tm
.opcode_modifier
.jump
)
5896 else if (i
.tm
.opcode_modifier
.jumpbyte
5897 || i
.tm
.opcode_modifier
.jumpdword
)
5899 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5900 output_interseg_jump ();
5903 /* Output normal instructions here. */
5907 unsigned int prefix
;
5909 /* Since the VEX prefix contains the implicit prefix, we don't
5910 need the explicit prefix. */
5911 if (!i
.tm
.opcode_modifier
.vex
)
5913 switch (i
.tm
.opcode_length
)
5916 if (i
.tm
.base_opcode
& 0xff000000)
5918 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5923 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5925 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5926 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5929 if (prefix
!= REPE_PREFIX_OPCODE
5930 || (i
.prefix
[LOCKREP_PREFIX
]
5931 != REPE_PREFIX_OPCODE
))
5932 add_prefix (prefix
);
5935 add_prefix (prefix
);
5944 /* The prefix bytes. */
5945 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5947 FRAG_APPEND_1_CHAR (*q
);
5950 if (i
.tm
.opcode_modifier
.vex
)
5952 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5957 /* REX byte is encoded in VEX prefix. */
5961 FRAG_APPEND_1_CHAR (*q
);
5964 /* There should be no other prefixes for instructions
5969 /* Now the VEX prefix. */
5970 p
= frag_more (i
.vex
.length
);
5971 for (j
= 0; j
< i
.vex
.length
; j
++)
5972 p
[j
] = i
.vex
.bytes
[j
];
5975 /* Now the opcode; be careful about word order here! */
5976 if (i
.tm
.opcode_length
== 1)
5978 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5982 switch (i
.tm
.opcode_length
)
5986 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5996 /* Put out high byte first: can't use md_number_to_chars! */
5997 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5998 *p
= i
.tm
.base_opcode
& 0xff;
6000 /* On SSE5, encode the OC1 bit in the DREX field if this
6001 encoding has multiple formats. */
6002 if (i
.tm
.opcode_modifier
.drex
6003 && i
.tm
.opcode_modifier
.drexv
6004 && DREX_OC1 (i
.tm
.extension_opcode
))
6005 *p
|= DREX_OC1_MASK
;
6008 /* Now the modrm byte and sib byte (if present). */
6009 if (i
.tm
.opcode_modifier
.modrm
)
6011 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
6014 /* If i.rm.regmem == ESP (4)
6015 && i.rm.mode != (Register mode)
6017 ==> need second modrm byte. */
6018 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
6020 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
6021 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
6023 | i
.sib
.scale
<< 6));
6026 /* Write the DREX byte if needed. */
6027 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
6030 *p
= (((i
.drex
.reg
& 0xf) << 4) | (i
.drex
.rex
& 0x7));
6032 /* Encode the OC0 bit if this encoding has multiple
6034 if ((i
.tm
.opcode_modifier
.drex
6035 || i
.tm
.opcode_modifier
.drexv
)
6036 && DREX_OC0 (i
.tm
.extension_opcode
))
6037 *p
|= DREX_OC0_MASK
;
6040 if (i
.disp_operands
)
6041 output_disp (insn_start_frag
, insn_start_off
);
6044 output_imm (insn_start_frag
, insn_start_off
);
6050 pi ("" /*line*/, &i
);
6052 #endif /* DEBUG386 */
6055 /* Return the size of the displacement operand N. */
6058 disp_size (unsigned int n
)
6061 if (i
.types
[n
].bitfield
.disp64
)
6063 else if (i
.types
[n
].bitfield
.disp8
)
6065 else if (i
.types
[n
].bitfield
.disp16
)
6070 /* Return the size of the immediate operand N. */
6073 imm_size (unsigned int n
)
6076 if (i
.types
[n
].bitfield
.imm64
)
6078 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6080 else if (i
.types
[n
].bitfield
.imm16
)
6086 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6091 for (n
= 0; n
< i
.operands
; n
++)
6093 if (operand_type_check (i
.types
[n
], disp
))
6095 if (i
.op
[n
].disps
->X_op
== O_constant
)
6097 int size
= disp_size (n
);
6100 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6102 p
= frag_more (size
);
6103 md_number_to_chars (p
, val
, size
);
6107 enum bfd_reloc_code_real reloc_type
;
6108 int size
= disp_size (n
);
6109 int sign
= i
.types
[n
].bitfield
.disp32s
;
6110 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6112 /* We can't have 8 bit displacement here. */
6113 assert (!i
.types
[n
].bitfield
.disp8
);
6115 /* The PC relative address is computed relative
6116 to the instruction boundary, so in case immediate
6117 fields follows, we need to adjust the value. */
6118 if (pcrel
&& i
.imm_operands
)
6123 for (n1
= 0; n1
< i
.operands
; n1
++)
6124 if (operand_type_check (i
.types
[n1
], imm
))
6126 /* Only one immediate is allowed for PC
6127 relative address. */
6130 i
.op
[n
].disps
->X_add_number
-= sz
;
6132 /* We should find the immediate. */
6136 p
= frag_more (size
);
6137 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6139 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6140 && (((reloc_type
== BFD_RELOC_32
6141 || reloc_type
== BFD_RELOC_X86_64_32S
6142 || (reloc_type
== BFD_RELOC_64
6144 && (i
.op
[n
].disps
->X_op
== O_symbol
6145 || (i
.op
[n
].disps
->X_op
== O_add
6146 && ((symbol_get_value_expression
6147 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6149 || reloc_type
== BFD_RELOC_32_PCREL
))
6153 if (insn_start_frag
== frag_now
)
6154 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6159 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6160 for (fr
= insn_start_frag
->fr_next
;
6161 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6163 add
+= p
- frag_now
->fr_literal
;
6168 reloc_type
= BFD_RELOC_386_GOTPC
;
6169 i
.op
[n
].imms
->X_add_number
+= add
;
6171 else if (reloc_type
== BFD_RELOC_64
)
6172 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6174 /* Don't do the adjustment for x86-64, as there
6175 the pcrel addressing is relative to the _next_
6176 insn, and that is taken care of in other code. */
6177 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6179 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6180 i
.op
[n
].disps
, pcrel
, reloc_type
);
6187 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6192 for (n
= 0; n
< i
.operands
; n
++)
6194 if (operand_type_check (i
.types
[n
], imm
))
6196 if (i
.op
[n
].imms
->X_op
== O_constant
)
6198 int size
= imm_size (n
);
6201 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6203 p
= frag_more (size
);
6204 md_number_to_chars (p
, val
, size
);
6208 /* Not absolute_section.
6209 Need a 32-bit fixup (don't support 8bit
6210 non-absolute imms). Try to support other
6212 enum bfd_reloc_code_real reloc_type
;
6213 int size
= imm_size (n
);
6216 if (i
.types
[n
].bitfield
.imm32s
6217 && (i
.suffix
== QWORD_MNEM_SUFFIX
6218 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6223 p
= frag_more (size
);
6224 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6226 /* This is tough to explain. We end up with this one if we
6227 * have operands that look like
6228 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6229 * obtain the absolute address of the GOT, and it is strongly
6230 * preferable from a performance point of view to avoid using
6231 * a runtime relocation for this. The actual sequence of
6232 * instructions often look something like:
6237 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6239 * The call and pop essentially return the absolute address
6240 * of the label .L66 and store it in %ebx. The linker itself
6241 * will ultimately change the first operand of the addl so
6242 * that %ebx points to the GOT, but to keep things simple, the
6243 * .o file must have this operand set so that it generates not
6244 * the absolute address of .L66, but the absolute address of
6245 * itself. This allows the linker itself simply treat a GOTPC
6246 * relocation as asking for a pcrel offset to the GOT to be
6247 * added in, and the addend of the relocation is stored in the
6248 * operand field for the instruction itself.
6250 * Our job here is to fix the operand so that it would add
6251 * the correct offset so that %ebx would point to itself. The
6252 * thing that is tricky is that .-.L66 will point to the
6253 * beginning of the instruction, so we need to further modify
6254 * the operand so that it will point to itself. There are
6255 * other cases where you have something like:
6257 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6259 * and here no correction would be required. Internally in
6260 * the assembler we treat operands of this form as not being
6261 * pcrel since the '.' is explicitly mentioned, and I wonder
6262 * whether it would simplify matters to do it this way. Who
6263 * knows. In earlier versions of the PIC patches, the
6264 * pcrel_adjust field was used to store the correction, but
6265 * since the expression is not pcrel, I felt it would be
6266 * confusing to do it this way. */
6268 if ((reloc_type
== BFD_RELOC_32
6269 || reloc_type
== BFD_RELOC_X86_64_32S
6270 || reloc_type
== BFD_RELOC_64
)
6272 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6273 && (i
.op
[n
].imms
->X_op
== O_symbol
6274 || (i
.op
[n
].imms
->X_op
== O_add
6275 && ((symbol_get_value_expression
6276 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6281 if (insn_start_frag
== frag_now
)
6282 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6287 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6288 for (fr
= insn_start_frag
->fr_next
;
6289 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6291 add
+= p
- frag_now
->fr_literal
;
6295 reloc_type
= BFD_RELOC_386_GOTPC
;
6297 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6299 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6300 i
.op
[n
].imms
->X_add_number
+= add
;
6302 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6303 i
.op
[n
].imms
, 0, reloc_type
);
6309 /* x86_cons_fix_new is called via the expression parsing code when a
6310 reloc is needed. We use this hook to get the correct .got reloc. */
6311 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6312 static int cons_sign
= -1;
6315 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6318 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6320 got_reloc
= NO_RELOC
;
6323 if (exp
->X_op
== O_secrel
)
6325 exp
->X_op
= O_symbol
;
6326 r
= BFD_RELOC_32_SECREL
;
6330 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6333 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6334 # define lex_got(reloc, adjust, types) NULL
6336 /* Parse operands of the form
6337 <symbol>@GOTOFF+<nnn>
6338 and similar .plt or .got references.
6340 If we find one, set up the correct relocation in RELOC and copy the
6341 input string, minus the `@GOTOFF' into a malloc'd buffer for
6342 parsing by the calling routine. Return this buffer, and if ADJUST
6343 is non-null set it to the length of the string we removed from the
6344 input line. Otherwise return NULL. */
6346 lex_got (enum bfd_reloc_code_real
*reloc
,
6348 i386_operand_type
*types
)
6350 /* Some of the relocations depend on the size of what field is to
6351 be relocated. But in our callers i386_immediate and i386_displacement
6352 we don't yet know the operand size (this will be set by insn
6353 matching). Hence we record the word32 relocation here,
6354 and adjust the reloc according to the real size in reloc(). */
6355 static const struct {
6357 const enum bfd_reloc_code_real rel
[2];
6358 const i386_operand_type types64
;
6361 BFD_RELOC_X86_64_PLTOFF64
},
6362 OPERAND_TYPE_IMM64
},
6363 { "PLT", { BFD_RELOC_386_PLT32
,
6364 BFD_RELOC_X86_64_PLT32
},
6365 OPERAND_TYPE_IMM32_32S_DISP32
},
6367 BFD_RELOC_X86_64_GOTPLT64
},
6368 OPERAND_TYPE_IMM64_DISP64
},
6369 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6370 BFD_RELOC_X86_64_GOTOFF64
},
6371 OPERAND_TYPE_IMM64_DISP64
},
6373 BFD_RELOC_X86_64_GOTPCREL
},
6374 OPERAND_TYPE_IMM32_32S_DISP32
},
6375 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6376 BFD_RELOC_X86_64_TLSGD
},
6377 OPERAND_TYPE_IMM32_32S_DISP32
},
6378 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6380 OPERAND_TYPE_NONE
},
6382 BFD_RELOC_X86_64_TLSLD
},
6383 OPERAND_TYPE_IMM32_32S_DISP32
},
6384 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6385 BFD_RELOC_X86_64_GOTTPOFF
},
6386 OPERAND_TYPE_IMM32_32S_DISP32
},
6387 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6388 BFD_RELOC_X86_64_TPOFF32
},
6389 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6390 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6392 OPERAND_TYPE_NONE
},
6393 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6394 BFD_RELOC_X86_64_DTPOFF32
},
6396 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6397 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6399 OPERAND_TYPE_NONE
},
6400 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6402 OPERAND_TYPE_NONE
},
6403 { "GOT", { BFD_RELOC_386_GOT32
,
6404 BFD_RELOC_X86_64_GOT32
},
6405 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6406 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6407 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6408 OPERAND_TYPE_IMM32_32S_DISP32
},
6409 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6410 BFD_RELOC_X86_64_TLSDESC_CALL
},
6411 OPERAND_TYPE_IMM32_32S_DISP32
},
6419 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6420 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6423 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6427 len
= strlen (gotrel
[j
].str
);
6428 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6430 if (gotrel
[j
].rel
[object_64bit
] != 0)
6433 char *tmpbuf
, *past_reloc
;
6435 *reloc
= gotrel
[j
].rel
[object_64bit
];
6441 if (flag_code
!= CODE_64BIT
)
6443 types
->bitfield
.imm32
= 1;
6444 types
->bitfield
.disp32
= 1;
6447 *types
= gotrel
[j
].types64
;
6450 if (GOT_symbol
== NULL
)
6451 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6453 /* The length of the first part of our input line. */
6454 first
= cp
- input_line_pointer
;
6456 /* The second part goes from after the reloc token until
6457 (and including) an end_of_line char or comma. */
6458 past_reloc
= cp
+ 1 + len
;
6460 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6462 second
= cp
+ 1 - past_reloc
;
6464 /* Allocate and copy string. The trailing NUL shouldn't
6465 be necessary, but be safe. */
6466 tmpbuf
= xmalloc (first
+ second
+ 2);
6467 memcpy (tmpbuf
, input_line_pointer
, first
);
6468 if (second
!= 0 && *past_reloc
!= ' ')
6469 /* Replace the relocation token with ' ', so that
6470 errors like foo@GOTOFF1 will be detected. */
6471 tmpbuf
[first
++] = ' ';
6472 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6473 tmpbuf
[first
+ second
] = '\0';
6477 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6478 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6483 /* Might be a symbol version string. Don't as_bad here. */
6488 x86_cons (expressionS
*exp
, int size
)
6490 if (size
== 4 || (object_64bit
&& size
== 8))
6492 /* Handle @GOTOFF and the like in an expression. */
6494 char *gotfree_input_line
;
6497 save
= input_line_pointer
;
6498 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6499 if (gotfree_input_line
)
6500 input_line_pointer
= gotfree_input_line
;
6504 if (gotfree_input_line
)
6506 /* expression () has merrily parsed up to the end of line,
6507 or a comma - in the wrong buffer. Transfer how far
6508 input_line_pointer has moved to the right buffer. */
6509 input_line_pointer
= (save
6510 + (input_line_pointer
- gotfree_input_line
)
6512 free (gotfree_input_line
);
6513 if (exp
->X_op
== O_constant
6514 || exp
->X_op
== O_absent
6515 || exp
->X_op
== O_illegal
6516 || exp
->X_op
== O_register
6517 || exp
->X_op
== O_big
)
6519 char c
= *input_line_pointer
;
6520 *input_line_pointer
= 0;
6521 as_bad (_("missing or invalid expression `%s'"), save
);
6522 *input_line_pointer
= c
;
6531 static void signed_cons (int size
)
6533 if (flag_code
== CODE_64BIT
)
6541 pe_directive_secrel (dummy
)
6542 int dummy ATTRIBUTE_UNUSED
;
6549 if (exp
.X_op
== O_symbol
)
6550 exp
.X_op
= O_secrel
;
6552 emit_expr (&exp
, 4);
6554 while (*input_line_pointer
++ == ',');
6556 input_line_pointer
--;
6557 demand_empty_rest_of_line ();
6562 i386_immediate (char *imm_start
)
6564 char *save_input_line_pointer
;
6565 char *gotfree_input_line
;
6568 i386_operand_type types
;
6570 operand_type_set (&types
, ~0);
6572 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6574 as_bad (_("at most %d immediate operands are allowed"),
6575 MAX_IMMEDIATE_OPERANDS
);
6579 exp
= &im_expressions
[i
.imm_operands
++];
6580 i
.op
[this_operand
].imms
= exp
;
6582 if (is_space_char (*imm_start
))
6585 save_input_line_pointer
= input_line_pointer
;
6586 input_line_pointer
= imm_start
;
6588 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6589 if (gotfree_input_line
)
6590 input_line_pointer
= gotfree_input_line
;
6592 exp_seg
= expression (exp
);
6595 if (*input_line_pointer
)
6596 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6598 input_line_pointer
= save_input_line_pointer
;
6599 if (gotfree_input_line
)
6600 free (gotfree_input_line
);
6602 if (exp
->X_op
== O_absent
6603 || exp
->X_op
== O_illegal
6604 || exp
->X_op
== O_big
6605 || (gotfree_input_line
6606 && (exp
->X_op
== O_constant
6607 || exp
->X_op
== O_register
)))
6609 as_bad (_("missing or invalid immediate expression `%s'"),
6613 else if (exp
->X_op
== O_constant
)
6615 /* Size it properly later. */
6616 i
.types
[this_operand
].bitfield
.imm64
= 1;
6617 /* If BFD64, sign extend val. */
6618 if (!use_rela_relocations
6619 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6621 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6623 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6624 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6625 && exp_seg
!= absolute_section
6626 && exp_seg
!= text_section
6627 && exp_seg
!= data_section
6628 && exp_seg
!= bss_section
6629 && exp_seg
!= undefined_section
6630 && !bfd_is_com_section (exp_seg
))
6632 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6636 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6638 as_bad (_("illegal immediate register operand %s"), imm_start
);
6643 /* This is an address. The size of the address will be
6644 determined later, depending on destination register,
6645 suffix, or the default for the section. */
6646 i
.types
[this_operand
].bitfield
.imm8
= 1;
6647 i
.types
[this_operand
].bitfield
.imm16
= 1;
6648 i
.types
[this_operand
].bitfield
.imm32
= 1;
6649 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6650 i
.types
[this_operand
].bitfield
.imm64
= 1;
6651 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6659 i386_scale (char *scale
)
6662 char *save
= input_line_pointer
;
6664 input_line_pointer
= scale
;
6665 val
= get_absolute_expression ();
6670 i
.log2_scale_factor
= 0;
6673 i
.log2_scale_factor
= 1;
6676 i
.log2_scale_factor
= 2;
6679 i
.log2_scale_factor
= 3;
6683 char sep
= *input_line_pointer
;
6685 *input_line_pointer
= '\0';
6686 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6688 *input_line_pointer
= sep
;
6689 input_line_pointer
= save
;
6693 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6695 as_warn (_("scale factor of %d without an index register"),
6696 1 << i
.log2_scale_factor
);
6697 i
.log2_scale_factor
= 0;
6699 scale
= input_line_pointer
;
6700 input_line_pointer
= save
;
6705 i386_displacement (char *disp_start
, char *disp_end
)
6709 char *save_input_line_pointer
;
6710 char *gotfree_input_line
;
6712 i386_operand_type bigdisp
, types
= anydisp
;
6715 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6717 as_bad (_("at most %d displacement operands are allowed"),
6718 MAX_MEMORY_OPERANDS
);
6722 operand_type_set (&bigdisp
, 0);
6723 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6724 || (!current_templates
->start
->opcode_modifier
.jump
6725 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6727 bigdisp
.bitfield
.disp32
= 1;
6728 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6729 if (flag_code
== CODE_64BIT
)
6733 bigdisp
.bitfield
.disp32s
= 1;
6734 bigdisp
.bitfield
.disp64
= 1;
6737 else if ((flag_code
== CODE_16BIT
) ^ override
)
6739 bigdisp
.bitfield
.disp32
= 0;
6740 bigdisp
.bitfield
.disp16
= 1;
6745 /* For PC-relative branches, the width of the displacement
6746 is dependent upon data size, not address size. */
6747 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6748 if (flag_code
== CODE_64BIT
)
6750 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6751 bigdisp
.bitfield
.disp16
= 1;
6754 bigdisp
.bitfield
.disp32
= 1;
6755 bigdisp
.bitfield
.disp32s
= 1;
6761 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6763 : LONG_MNEM_SUFFIX
));
6764 bigdisp
.bitfield
.disp32
= 1;
6765 if ((flag_code
== CODE_16BIT
) ^ override
)
6767 bigdisp
.bitfield
.disp32
= 0;
6768 bigdisp
.bitfield
.disp16
= 1;
6772 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6775 exp
= &disp_expressions
[i
.disp_operands
];
6776 i
.op
[this_operand
].disps
= exp
;
6778 save_input_line_pointer
= input_line_pointer
;
6779 input_line_pointer
= disp_start
;
6780 END_STRING_AND_SAVE (disp_end
);
6782 #ifndef GCC_ASM_O_HACK
6783 #define GCC_ASM_O_HACK 0
6786 END_STRING_AND_SAVE (disp_end
+ 1);
6787 if (i
.types
[this_operand
].bitfield
.baseIndex
6788 && displacement_string_end
[-1] == '+')
6790 /* This hack is to avoid a warning when using the "o"
6791 constraint within gcc asm statements.
6794 #define _set_tssldt_desc(n,addr,limit,type) \
6795 __asm__ __volatile__ ( \
6797 "movw %w1,2+%0\n\t" \
6799 "movb %b1,4+%0\n\t" \
6800 "movb %4,5+%0\n\t" \
6801 "movb $0,6+%0\n\t" \
6802 "movb %h1,7+%0\n\t" \
6804 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6806 This works great except that the output assembler ends
6807 up looking a bit weird if it turns out that there is
6808 no offset. You end up producing code that looks like:
6821 So here we provide the missing zero. */
6823 *displacement_string_end
= '0';
6826 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6827 if (gotfree_input_line
)
6828 input_line_pointer
= gotfree_input_line
;
6830 exp_seg
= expression (exp
);
6833 if (*input_line_pointer
)
6834 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6836 RESTORE_END_STRING (disp_end
+ 1);
6838 input_line_pointer
= save_input_line_pointer
;
6839 if (gotfree_input_line
)
6840 free (gotfree_input_line
);
6843 /* We do this to make sure that the section symbol is in
6844 the symbol table. We will ultimately change the relocation
6845 to be relative to the beginning of the section. */
6846 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6847 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6848 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6850 if (exp
->X_op
!= O_symbol
)
6853 if (S_IS_LOCAL (exp
->X_add_symbol
)
6854 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6855 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6856 exp
->X_op
= O_subtract
;
6857 exp
->X_op_symbol
= GOT_symbol
;
6858 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6859 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6860 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6861 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6863 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6866 else if (exp
->X_op
== O_absent
6867 || exp
->X_op
== O_illegal
6868 || exp
->X_op
== O_big
6869 || (gotfree_input_line
6870 && (exp
->X_op
== O_constant
6871 || exp
->X_op
== O_register
)))
6874 as_bad (_("missing or invalid displacement expression `%s'"),
6879 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6880 else if (exp
->X_op
!= O_constant
6881 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6882 && exp_seg
!= absolute_section
6883 && exp_seg
!= text_section
6884 && exp_seg
!= data_section
6885 && exp_seg
!= bss_section
6886 && exp_seg
!= undefined_section
6887 && !bfd_is_com_section (exp_seg
))
6889 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6894 RESTORE_END_STRING (disp_end
);
6896 /* Check if this is a displacement only operand. */
6897 bigdisp
= i
.types
[this_operand
];
6898 bigdisp
.bitfield
.disp8
= 0;
6899 bigdisp
.bitfield
.disp16
= 0;
6900 bigdisp
.bitfield
.disp32
= 0;
6901 bigdisp
.bitfield
.disp32s
= 0;
6902 bigdisp
.bitfield
.disp64
= 0;
6903 if (operand_type_all_zero (&bigdisp
))
6904 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6910 /* Make sure the memory operand we've been dealt is valid.
6911 Return 1 on success, 0 on a failure. */
6914 i386_index_check (const char *operand_string
)
6917 const char *kind
= "base/index";
6918 #if INFER_ADDR_PREFIX
6924 if (current_templates
->start
->opcode_modifier
.isstring
6925 && !current_templates
->start
->opcode_modifier
.immext
6926 && (current_templates
->end
[-1].opcode_modifier
.isstring
6929 /* Memory operands of string insns are special in that they only allow
6930 a single register (rDI, rSI, or rBX) as their memory address. */
6931 unsigned int expected
;
6933 kind
= "string address";
6935 if (current_templates
->start
->opcode_modifier
.w
)
6937 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6939 if (!type
.bitfield
.baseindex
6940 || ((!i
.mem_operands
!= !intel_syntax
)
6941 && current_templates
->end
[-1].operand_types
[1]
6942 .bitfield
.baseindex
))
6943 type
= current_templates
->end
[-1].operand_types
[1];
6944 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6947 expected
= 3 /* rBX */;
6949 if (!i
.base_reg
|| i
.index_reg
6950 || operand_type_check (i
.types
[this_operand
], disp
))
6952 else if (!(flag_code
== CODE_64BIT
6953 ? i
.prefix
[ADDR_PREFIX
]
6954 ? i
.base_reg
->reg_type
.bitfield
.reg32
6955 : i
.base_reg
->reg_type
.bitfield
.reg64
6956 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6957 ? i
.base_reg
->reg_type
.bitfield
.reg32
6958 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6960 else if (i
.base_reg
->reg_num
!= expected
)
6967 for (j
= 0; j
< i386_regtab_size
; ++j
)
6968 if ((flag_code
== CODE_64BIT
6969 ? i
.prefix
[ADDR_PREFIX
]
6970 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6971 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6972 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6973 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6974 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6975 && i386_regtab
[j
].reg_num
== expected
)
6977 assert (j
< i386_regtab_size
);
6978 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6980 intel_syntax
? '[' : '(',
6982 i386_regtab
[j
].reg_name
,
6983 intel_syntax
? ']' : ')');
6987 else if (flag_code
== CODE_64BIT
)
6990 && ((i
.prefix
[ADDR_PREFIX
] == 0
6991 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6992 || (i
.prefix
[ADDR_PREFIX
]
6993 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6995 || i
.base_reg
->reg_num
!=
6996 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6998 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6999 || (i
.prefix
[ADDR_PREFIX
] == 0
7000 && i
.index_reg
->reg_num
!= RegRiz
7001 && !i
.index_reg
->reg_type
.bitfield
.reg64
7003 || (i
.prefix
[ADDR_PREFIX
]
7004 && i
.index_reg
->reg_num
!= RegEiz
7005 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
7010 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7014 && (!i
.base_reg
->reg_type
.bitfield
.reg16
7015 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
7017 && (!i
.index_reg
->reg_type
.bitfield
.reg16
7018 || !i
.index_reg
->reg_type
.bitfield
.baseindex
7020 && i
.base_reg
->reg_num
< 6
7021 && i
.index_reg
->reg_num
>= 6
7022 && i
.log2_scale_factor
== 0))))
7029 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
7031 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
7032 && i
.index_reg
->reg_num
!= RegEiz
)
7033 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7039 #if INFER_ADDR_PREFIX
7040 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
7042 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7044 /* Change the size of any displacement too. At most one of
7045 Disp16 or Disp32 is set.
7046 FIXME. There doesn't seem to be any real need for separate
7047 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
7048 Removing them would probably clean up the code quite a lot. */
7049 if (flag_code
!= CODE_64BIT
7050 && (i
.types
[this_operand
].bitfield
.disp16
7051 || i
.types
[this_operand
].bitfield
.disp32
))
7052 i
.types
[this_operand
]
7053 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7058 as_bad (_("`%s' is not a valid %s expression"),
7063 as_bad (_("`%s' is not a valid %s-bit %s expression"),
7065 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
7066 ? flag_code
== CODE_32BIT
7075 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7079 i386_att_operand (char *operand_string
)
7083 char *op_string
= operand_string
;
7085 if (is_space_char (*op_string
))
7088 /* We check for an absolute prefix (differentiating,
7089 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7090 if (*op_string
== ABSOLUTE_PREFIX
)
7093 if (is_space_char (*op_string
))
7095 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7098 /* Check if operand is a register. */
7099 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7101 i386_operand_type temp
;
7103 /* Check for a segment override by searching for ':' after a
7104 segment register. */
7106 if (is_space_char (*op_string
))
7108 if (*op_string
== ':'
7109 && (r
->reg_type
.bitfield
.sreg2
7110 || r
->reg_type
.bitfield
.sreg3
))
7115 i
.seg
[i
.mem_operands
] = &es
;
7118 i
.seg
[i
.mem_operands
] = &cs
;
7121 i
.seg
[i
.mem_operands
] = &ss
;
7124 i
.seg
[i
.mem_operands
] = &ds
;
7127 i
.seg
[i
.mem_operands
] = &fs
;
7130 i
.seg
[i
.mem_operands
] = &gs
;
7134 /* Skip the ':' and whitespace. */
7136 if (is_space_char (*op_string
))
7139 if (!is_digit_char (*op_string
)
7140 && !is_identifier_char (*op_string
)
7141 && *op_string
!= '('
7142 && *op_string
!= ABSOLUTE_PREFIX
)
7144 as_bad (_("bad memory operand `%s'"), op_string
);
7147 /* Handle case of %es:*foo. */
7148 if (*op_string
== ABSOLUTE_PREFIX
)
7151 if (is_space_char (*op_string
))
7153 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7155 goto do_memory_reference
;
7159 as_bad (_("junk `%s' after register"), op_string
);
7163 temp
.bitfield
.baseindex
= 0;
7164 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7166 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7167 i
.op
[this_operand
].regs
= r
;
7170 else if (*op_string
== REGISTER_PREFIX
)
7172 as_bad (_("bad register name `%s'"), op_string
);
7175 else if (*op_string
== IMMEDIATE_PREFIX
)
7178 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7180 as_bad (_("immediate operand illegal with absolute jump"));
7183 if (!i386_immediate (op_string
))
7186 else if (is_digit_char (*op_string
)
7187 || is_identifier_char (*op_string
)
7188 || *op_string
== '(')
7190 /* This is a memory reference of some sort. */
7193 /* Start and end of displacement string expression (if found). */
7194 char *displacement_string_start
;
7195 char *displacement_string_end
;
7197 do_memory_reference
:
7198 if ((i
.mem_operands
== 1
7199 && !current_templates
->start
->opcode_modifier
.isstring
)
7200 || i
.mem_operands
== 2)
7202 as_bad (_("too many memory references for `%s'"),
7203 current_templates
->start
->name
);
7207 /* Check for base index form. We detect the base index form by
7208 looking for an ')' at the end of the operand, searching
7209 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7211 base_string
= op_string
+ strlen (op_string
);
7214 if (is_space_char (*base_string
))
7217 /* If we only have a displacement, set-up for it to be parsed later. */
7218 displacement_string_start
= op_string
;
7219 displacement_string_end
= base_string
+ 1;
7221 if (*base_string
== ')')
7224 unsigned int parens_balanced
= 1;
7225 /* We've already checked that the number of left & right ()'s are
7226 equal, so this loop will not be infinite. */
7230 if (*base_string
== ')')
7232 if (*base_string
== '(')
7235 while (parens_balanced
);
7237 temp_string
= base_string
;
7239 /* Skip past '(' and whitespace. */
7241 if (is_space_char (*base_string
))
7244 if (*base_string
== ','
7245 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7248 displacement_string_end
= temp_string
;
7250 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7254 base_string
= end_op
;
7255 if (is_space_char (*base_string
))
7259 /* There may be an index reg or scale factor here. */
7260 if (*base_string
== ',')
7263 if (is_space_char (*base_string
))
7266 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7269 base_string
= end_op
;
7270 if (is_space_char (*base_string
))
7272 if (*base_string
== ',')
7275 if (is_space_char (*base_string
))
7278 else if (*base_string
!= ')')
7280 as_bad (_("expecting `,' or `)' "
7281 "after index register in `%s'"),
7286 else if (*base_string
== REGISTER_PREFIX
)
7288 as_bad (_("bad register name `%s'"), base_string
);
7292 /* Check for scale factor. */
7293 if (*base_string
!= ')')
7295 char *end_scale
= i386_scale (base_string
);
7300 base_string
= end_scale
;
7301 if (is_space_char (*base_string
))
7303 if (*base_string
!= ')')
7305 as_bad (_("expecting `)' "
7306 "after scale factor in `%s'"),
7311 else if (!i
.index_reg
)
7313 as_bad (_("expecting index register or scale factor "
7314 "after `,'; got '%c'"),
7319 else if (*base_string
!= ')')
7321 as_bad (_("expecting `,' or `)' "
7322 "after base register in `%s'"),
7327 else if (*base_string
== REGISTER_PREFIX
)
7329 as_bad (_("bad register name `%s'"), base_string
);
7334 /* If there's an expression beginning the operand, parse it,
7335 assuming displacement_string_start and
7336 displacement_string_end are meaningful. */
7337 if (displacement_string_start
!= displacement_string_end
)
7339 if (!i386_displacement (displacement_string_start
,
7340 displacement_string_end
))
7344 /* Special case for (%dx) while doing input/output op. */
7346 && operand_type_equal (&i
.base_reg
->reg_type
,
7347 ®16_inoutportreg
)
7349 && i
.log2_scale_factor
== 0
7350 && i
.seg
[i
.mem_operands
] == 0
7351 && !operand_type_check (i
.types
[this_operand
], disp
))
7353 i
.types
[this_operand
] = inoutportreg
;
7357 if (i386_index_check (operand_string
) == 0)
7359 i
.types
[this_operand
].bitfield
.mem
= 1;
7364 /* It's not a memory operand; argh! */
7365 as_bad (_("invalid char %s beginning operand %d `%s'"),
7366 output_invalid (*op_string
),
7371 return 1; /* Normal return. */
7374 /* md_estimate_size_before_relax()
7376 Called just before relax() for rs_machine_dependent frags. The x86
7377 assembler uses these frags to handle variable size jump
7380 Any symbol that is now undefined will not become defined.
7381 Return the correct fr_subtype in the frag.
7382 Return the initial "guess for variable size of frag" to caller.
7383 The guess is actually the growth beyond the fixed part. Whatever
7384 we do to grow the fixed or variable part contributes to our
7388 md_estimate_size_before_relax (fragP
, segment
)
7392 /* We've already got fragP->fr_subtype right; all we have to do is
7393 check for un-relaxable symbols. On an ELF system, we can't relax
7394 an externally visible symbol, because it may be overridden by a
7396 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7397 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7399 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7400 || S_IS_WEAK (fragP
->fr_symbol
)))
7404 /* Symbol is undefined in this segment, or we need to keep a
7405 reloc so that weak symbols can be overridden. */
7406 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7407 enum bfd_reloc_code_real reloc_type
;
7408 unsigned char *opcode
;
7411 if (fragP
->fr_var
!= NO_RELOC
)
7412 reloc_type
= fragP
->fr_var
;
7414 reloc_type
= BFD_RELOC_16_PCREL
;
7416 reloc_type
= BFD_RELOC_32_PCREL
;
7418 old_fr_fix
= fragP
->fr_fix
;
7419 opcode
= (unsigned char *) fragP
->fr_opcode
;
7421 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7424 /* Make jmp (0xeb) a (d)word displacement jump. */
7426 fragP
->fr_fix
+= size
;
7427 fix_new (fragP
, old_fr_fix
, size
,
7429 fragP
->fr_offset
, 1,
7435 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7437 /* Negate the condition, and branch past an
7438 unconditional jump. */
7441 /* Insert an unconditional jump. */
7443 /* We added two extra opcode bytes, and have a two byte
7445 fragP
->fr_fix
+= 2 + 2;
7446 fix_new (fragP
, old_fr_fix
+ 2, 2,
7448 fragP
->fr_offset
, 1,
7455 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7460 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7462 fragP
->fr_offset
, 1,
7464 fixP
->fx_signed
= 1;
7468 /* This changes the byte-displacement jump 0x7N
7469 to the (d)word-displacement jump 0x0f,0x8N. */
7470 opcode
[1] = opcode
[0] + 0x10;
7471 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7472 /* We've added an opcode byte. */
7473 fragP
->fr_fix
+= 1 + size
;
7474 fix_new (fragP
, old_fr_fix
+ 1, size
,
7476 fragP
->fr_offset
, 1,
7481 BAD_CASE (fragP
->fr_subtype
);
7485 return fragP
->fr_fix
- old_fr_fix
;
7488 /* Guess size depending on current relax state. Initially the relax
7489 state will correspond to a short jump and we return 1, because
7490 the variable part of the frag (the branch offset) is one byte
7491 long. However, we can relax a section more than once and in that
7492 case we must either set fr_subtype back to the unrelaxed state,
7493 or return the value for the appropriate branch. */
7494 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7497 /* Called after relax() is finished.
7499 In: Address of frag.
7500 fr_type == rs_machine_dependent.
7501 fr_subtype is what the address relaxed to.
7503 Out: Any fixSs and constants are set up.
7504 Caller will turn frag into a ".space 0". */
7507 md_convert_frag (abfd
, sec
, fragP
)
7508 bfd
*abfd ATTRIBUTE_UNUSED
;
7509 segT sec ATTRIBUTE_UNUSED
;
7512 unsigned char *opcode
;
7513 unsigned char *where_to_put_displacement
= NULL
;
7514 offsetT target_address
;
7515 offsetT opcode_address
;
7516 unsigned int extension
= 0;
7517 offsetT displacement_from_opcode_start
;
7519 opcode
= (unsigned char *) fragP
->fr_opcode
;
7521 /* Address we want to reach in file space. */
7522 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7524 /* Address opcode resides at in file space. */
7525 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7527 /* Displacement from opcode start to fill into instruction. */
7528 displacement_from_opcode_start
= target_address
- opcode_address
;
7530 if ((fragP
->fr_subtype
& BIG
) == 0)
7532 /* Don't have to change opcode. */
7533 extension
= 1; /* 1 opcode + 1 displacement */
7534 where_to_put_displacement
= &opcode
[1];
7538 if (no_cond_jump_promotion
7539 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7540 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7541 _("long jump required"));
7543 switch (fragP
->fr_subtype
)
7545 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7546 extension
= 4; /* 1 opcode + 4 displacement */
7548 where_to_put_displacement
= &opcode
[1];
7551 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7552 extension
= 2; /* 1 opcode + 2 displacement */
7554 where_to_put_displacement
= &opcode
[1];
7557 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7558 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7559 extension
= 5; /* 2 opcode + 4 displacement */
7560 opcode
[1] = opcode
[0] + 0x10;
7561 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7562 where_to_put_displacement
= &opcode
[2];
7565 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7566 extension
= 3; /* 2 opcode + 2 displacement */
7567 opcode
[1] = opcode
[0] + 0x10;
7568 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7569 where_to_put_displacement
= &opcode
[2];
7572 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7577 where_to_put_displacement
= &opcode
[3];
7581 BAD_CASE (fragP
->fr_subtype
);
7586 /* If size if less then four we are sure that the operand fits,
7587 but if it's 4, then it could be that the displacement is larger
7589 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7591 && ((addressT
) (displacement_from_opcode_start
- extension
7592 + ((addressT
) 1 << 31))
7593 > (((addressT
) 2 << 31) - 1)))
7595 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7596 _("jump target out of range"));
7597 /* Make us emit 0. */
7598 displacement_from_opcode_start
= extension
;
7600 /* Now put displacement after opcode. */
7601 md_number_to_chars ((char *) where_to_put_displacement
,
7602 (valueT
) (displacement_from_opcode_start
- extension
),
7603 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7604 fragP
->fr_fix
+= extension
;
7607 /* Apply a fixup (fixS) to segment data, once it has been determined
7608 by our caller that we have all the info we need to fix it up.
7610 On the 386, immediates, displacements, and data pointers are all in
7611 the same (little-endian) format, so we don't need to care about which
7615 md_apply_fix (fixP
, valP
, seg
)
7616 /* The fix we're to put in. */
7618 /* Pointer to the value of the bits. */
7620 /* Segment fix is from. */
7621 segT seg ATTRIBUTE_UNUSED
;
7623 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7624 valueT value
= *valP
;
7626 #if !defined (TE_Mach)
7629 switch (fixP
->fx_r_type
)
7635 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7638 case BFD_RELOC_X86_64_32S
:
7639 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7642 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7645 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7650 if (fixP
->fx_addsy
!= NULL
7651 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7652 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7653 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7654 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7655 && !use_rela_relocations
)
7657 /* This is a hack. There should be a better way to handle this.
7658 This covers for the fact that bfd_install_relocation will
7659 subtract the current location (for partial_inplace, PC relative
7660 relocations); see more below. */
7664 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7667 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7669 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7672 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7675 || (symbol_section_p (fixP
->fx_addsy
)
7676 && sym_seg
!= absolute_section
))
7677 && !generic_force_reloc (fixP
))
7679 /* Yes, we add the values in twice. This is because
7680 bfd_install_relocation subtracts them out again. I think
7681 bfd_install_relocation is broken, but I don't dare change
7683 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7687 #if defined (OBJ_COFF) && defined (TE_PE)
7688 /* For some reason, the PE format does not store a
7689 section address offset for a PC relative symbol. */
7690 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7691 || S_IS_WEAK (fixP
->fx_addsy
))
7692 value
+= md_pcrel_from (fixP
);
7696 /* Fix a few things - the dynamic linker expects certain values here,
7697 and we must not disappoint it. */
7698 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7699 if (IS_ELF
&& fixP
->fx_addsy
)
7700 switch (fixP
->fx_r_type
)
7702 case BFD_RELOC_386_PLT32
:
7703 case BFD_RELOC_X86_64_PLT32
:
7704 /* Make the jump instruction point to the address of the operand. At
7705 runtime we merely add the offset to the actual PLT entry. */
7709 case BFD_RELOC_386_TLS_GD
:
7710 case BFD_RELOC_386_TLS_LDM
:
7711 case BFD_RELOC_386_TLS_IE_32
:
7712 case BFD_RELOC_386_TLS_IE
:
7713 case BFD_RELOC_386_TLS_GOTIE
:
7714 case BFD_RELOC_386_TLS_GOTDESC
:
7715 case BFD_RELOC_X86_64_TLSGD
:
7716 case BFD_RELOC_X86_64_TLSLD
:
7717 case BFD_RELOC_X86_64_GOTTPOFF
:
7718 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7719 value
= 0; /* Fully resolved at runtime. No addend. */
7721 case BFD_RELOC_386_TLS_LE
:
7722 case BFD_RELOC_386_TLS_LDO_32
:
7723 case BFD_RELOC_386_TLS_LE_32
:
7724 case BFD_RELOC_X86_64_DTPOFF32
:
7725 case BFD_RELOC_X86_64_DTPOFF64
:
7726 case BFD_RELOC_X86_64_TPOFF32
:
7727 case BFD_RELOC_X86_64_TPOFF64
:
7728 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7731 case BFD_RELOC_386_TLS_DESC_CALL
:
7732 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7733 value
= 0; /* Fully resolved at runtime. No addend. */
7734 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7738 case BFD_RELOC_386_GOT32
:
7739 case BFD_RELOC_X86_64_GOT32
:
7740 value
= 0; /* Fully resolved at runtime. No addend. */
7743 case BFD_RELOC_VTABLE_INHERIT
:
7744 case BFD_RELOC_VTABLE_ENTRY
:
7751 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7753 #endif /* !defined (TE_Mach) */
7755 /* Are we finished with this relocation now? */
7756 if (fixP
->fx_addsy
== NULL
)
7758 else if (use_rela_relocations
)
7760 fixP
->fx_no_overflow
= 1;
7761 /* Remember value for tc_gen_reloc. */
7762 fixP
->fx_addnumber
= value
;
7766 md_number_to_chars (p
, value
, fixP
->fx_size
);
7770 md_atof (int type
, char *litP
, int *sizeP
)
7772 /* This outputs the LITTLENUMs in REVERSE order;
7773 in accord with the bigendian 386. */
7774 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7777 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7780 output_invalid (int c
)
7783 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7786 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7787 "(0x%x)", (unsigned char) c
);
7788 return output_invalid_buf
;
7791 /* REG_STRING starts *before* REGISTER_PREFIX. */
7793 static const reg_entry
*
7794 parse_real_register (char *reg_string
, char **end_op
)
7796 char *s
= reg_string
;
7798 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7801 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7802 if (*s
== REGISTER_PREFIX
)
7805 if (is_space_char (*s
))
7809 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7811 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7812 return (const reg_entry
*) NULL
;
7816 /* For naked regs, make sure that we are not dealing with an identifier.
7817 This prevents confusing an identifier like `eax_var' with register
7819 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7820 return (const reg_entry
*) NULL
;
7824 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7826 /* Handle floating point regs, allowing spaces in the (i) part. */
7827 if (r
== i386_regtab
/* %st is first entry of table */)
7829 if (is_space_char (*s
))
7834 if (is_space_char (*s
))
7836 if (*s
>= '0' && *s
<= '7')
7840 if (is_space_char (*s
))
7845 r
= hash_find (reg_hash
, "st(0)");
7850 /* We have "%st(" then garbage. */
7851 return (const reg_entry
*) NULL
;
7855 if (r
== NULL
|| allow_pseudo_reg
)
7858 if (operand_type_all_zero (&r
->reg_type
))
7859 return (const reg_entry
*) NULL
;
7861 if ((r
->reg_type
.bitfield
.reg32
7862 || r
->reg_type
.bitfield
.sreg3
7863 || r
->reg_type
.bitfield
.control
7864 || r
->reg_type
.bitfield
.debug
7865 || r
->reg_type
.bitfield
.test
)
7866 && !cpu_arch_flags
.bitfield
.cpui386
)
7867 return (const reg_entry
*) NULL
;
7869 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7870 return (const reg_entry
*) NULL
;
7872 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7873 return (const reg_entry
*) NULL
;
7875 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7876 return (const reg_entry
*) NULL
;
7878 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7879 if (!allow_index_reg
7880 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7881 return (const reg_entry
*) NULL
;
7883 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7884 || r
->reg_type
.bitfield
.reg64
)
7885 && (!cpu_arch_flags
.bitfield
.cpulm
7886 || !operand_type_equal (&r
->reg_type
, &control
))
7887 && flag_code
!= CODE_64BIT
)
7888 return (const reg_entry
*) NULL
;
7890 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7891 return (const reg_entry
*) NULL
;
7896 /* REG_STRING starts *before* REGISTER_PREFIX. */
7898 static const reg_entry
*
7899 parse_register (char *reg_string
, char **end_op
)
7903 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7904 r
= parse_real_register (reg_string
, end_op
);
7909 char *save
= input_line_pointer
;
7913 input_line_pointer
= reg_string
;
7914 c
= get_symbol_end ();
7915 symbolP
= symbol_find (reg_string
);
7916 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7918 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7920 know (e
->X_op
== O_register
);
7921 know (e
->X_add_number
>= 0
7922 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7923 r
= i386_regtab
+ e
->X_add_number
;
7924 *end_op
= input_line_pointer
;
7926 *input_line_pointer
= c
;
7927 input_line_pointer
= save
;
7933 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7936 char *end
= input_line_pointer
;
7939 r
= parse_register (name
, &input_line_pointer
);
7940 if (r
&& end
<= input_line_pointer
)
7942 *nextcharP
= *input_line_pointer
;
7943 *input_line_pointer
= 0;
7944 e
->X_op
= O_register
;
7945 e
->X_add_number
= r
- i386_regtab
;
7948 input_line_pointer
= end
;
7954 md_operand (expressionS
*e
)
7956 if (*input_line_pointer
== REGISTER_PREFIX
)
7959 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
7963 e
->X_op
= O_register
;
7964 e
->X_add_number
= r
- i386_regtab
;
7965 input_line_pointer
= end
;
7971 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7972 const char *md_shortopts
= "kVQ:sqn";
7974 const char *md_shortopts
= "qn";
7977 #define OPTION_32 (OPTION_MD_BASE + 0)
7978 #define OPTION_64 (OPTION_MD_BASE + 1)
7979 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7980 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7981 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7982 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7983 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7984 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7985 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7986 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7987 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7988 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7990 struct option md_longopts
[] =
7992 {"32", no_argument
, NULL
, OPTION_32
},
7993 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7994 {"64", no_argument
, NULL
, OPTION_64
},
7996 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7997 {"march", required_argument
, NULL
, OPTION_MARCH
},
7998 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7999 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
8000 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
8001 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
8002 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
8003 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
8004 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
8005 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
8006 {NULL
, no_argument
, NULL
, 0}
8008 size_t md_longopts_size
= sizeof (md_longopts
);
8011 md_parse_option (int c
, char *arg
)
8019 optimize_align_code
= 0;
8026 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8027 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8028 should be emitted or not. FIXME: Not implemented. */
8032 /* -V: SVR4 argument to print version ID. */
8034 print_version_id ();
8037 /* -k: Ignore for FreeBSD compatibility. */
8042 /* -s: On i386 Solaris, this tells the native assembler to use
8043 .stab instead of .stab.excl. We always use .stab anyhow. */
8046 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8049 const char **list
, **l
;
8051 list
= bfd_target_list ();
8052 for (l
= list
; *l
!= NULL
; l
++)
8053 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8054 || strcmp (*l
, "coff-x86-64") == 0
8055 || strcmp (*l
, "pe-x86-64") == 0
8056 || strcmp (*l
, "pei-x86-64") == 0)
8058 default_arch
= "x86_64";
8062 as_fatal (_("No compiled in support for x86_64"));
8069 default_arch
= "i386";
8073 #ifdef SVR4_COMMENT_CHARS
8078 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8080 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8084 i386_comment_chars
= n
;
8090 arch
= xstrdup (arg
);
8094 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8095 next
= strchr (arch
, '+');
8098 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
8100 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
8103 cpu_arch_name
= cpu_arch
[i
].name
;
8104 cpu_sub_arch_name
= NULL
;
8105 cpu_arch_flags
= cpu_arch
[i
].flags
;
8106 cpu_arch_isa
= cpu_arch
[i
].type
;
8107 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
8108 if (!cpu_arch_tune_set
)
8110 cpu_arch_tune
= cpu_arch_isa
;
8111 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8115 else if (*cpu_arch
[i
].name
== '.'
8116 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
8118 /* ISA entension. */
8119 i386_cpu_flags flags
;
8120 flags
= cpu_flags_or (cpu_arch_flags
,
8122 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8124 if (cpu_sub_arch_name
)
8126 char *name
= cpu_sub_arch_name
;
8127 cpu_sub_arch_name
= concat (name
,
8129 (const char *) NULL
);
8133 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
8134 cpu_arch_flags
= flags
;
8140 if (i
>= ARRAY_SIZE (cpu_arch
))
8141 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8145 while (next
!= NULL
);
8150 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8151 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
8153 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
8155 cpu_arch_tune_set
= 1;
8156 cpu_arch_tune
= cpu_arch
[i
].type
;
8157 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
8161 if (i
>= ARRAY_SIZE (cpu_arch
))
8162 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8165 case OPTION_MMNEMONIC
:
8166 if (strcasecmp (arg
, "att") == 0)
8168 else if (strcasecmp (arg
, "intel") == 0)
8171 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8174 case OPTION_MSYNTAX
:
8175 if (strcasecmp (arg
, "att") == 0)
8177 else if (strcasecmp (arg
, "intel") == 0)
8180 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8183 case OPTION_MINDEX_REG
:
8184 allow_index_reg
= 1;
8187 case OPTION_MNAKED_REG
:
8188 allow_naked_reg
= 1;
8191 case OPTION_MOLD_GCC
:
8195 case OPTION_MSSE2AVX
:
8199 case OPTION_MSSE_CHECK
:
8200 if (strcasecmp (arg
, "error") == 0)
8201 sse_check
= sse_check_error
;
8202 else if (strcasecmp (arg
, "warning") == 0)
8203 sse_check
= sse_check_warning
;
8204 else if (strcasecmp (arg
, "none") == 0)
8205 sse_check
= sse_check_none
;
8207 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8217 md_show_usage (stream
)
8220 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8221 fprintf (stream
, _("\
8223 -V print assembler version number\n\
8226 fprintf (stream
, _("\
8227 -n Do not optimize code alignment\n\
8228 -q quieten some warnings\n"));
8229 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8230 fprintf (stream
, _("\
8233 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8234 fprintf (stream
, _("\
8235 --32/--64 generate 32bit/64bit code\n"));
8237 #ifdef SVR4_COMMENT_CHARS
8238 fprintf (stream
, _("\
8239 --divide do not treat `/' as a comment character\n"));
8241 fprintf (stream
, _("\
8242 --divide ignored\n"));
8244 fprintf (stream
, _("\
8245 -march=CPU[,+EXTENSION...]\n\
8246 generate code for CPU and EXTENSION, CPU is one of:\n\
8247 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8248 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8249 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
8250 generic32, generic64\n\
8251 EXTENSION is combination of:\n\
8252 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
8253 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8254 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
8255 sse5, svme, abm, padlock\n"));
8256 fprintf (stream
, _("\
8257 -mtune=CPU optimize for CPU, CPU is one of:\n\
8258 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8259 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8260 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
8261 generic32, generic64\n"));
8262 fprintf (stream
, _("\
8263 -msse2avx encode SSE instructions with VEX prefix\n"));
8264 fprintf (stream
, _("\
8265 -msse-check=[none|error|warning]\n\
8266 check SSE instructions\n"));
8267 fprintf (stream
, _("\
8268 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8269 fprintf (stream
, _("\
8270 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8271 fprintf (stream
, _("\
8272 -mindex-reg support pseudo index registers\n"));
8273 fprintf (stream
, _("\
8274 -mnaked-reg don't require `%%' prefix for registers\n"));
8275 fprintf (stream
, _("\
8276 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8279 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8280 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
8282 /* Pick the target format to use. */
8285 i386_target_format (void)
8287 if (!strcmp (default_arch
, "x86_64"))
8289 set_code_flag (CODE_64BIT
);
8290 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8292 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8293 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8294 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8295 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8296 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8297 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8298 cpu_arch_isa_flags
.bitfield
.cpuclflush
= 1;
8299 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8300 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8301 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8303 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8305 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8306 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8307 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8308 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8309 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8310 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8311 cpu_arch_tune_flags
.bitfield
.cpuclflush
= 1;
8312 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8313 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8314 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8317 else if (!strcmp (default_arch
, "i386"))
8319 set_code_flag (CODE_32BIT
);
8320 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8322 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8323 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8324 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8326 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8328 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8329 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8330 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8334 as_fatal (_("Unknown architecture"));
8335 switch (OUTPUT_FLAVOR
)
8338 case bfd_target_coff_flavour
:
8339 return flag_code
== CODE_64BIT
? COFF_TARGET_FORMAT
: "pe-i386";
8342 #ifdef OBJ_MAYBE_AOUT
8343 case bfd_target_aout_flavour
:
8344 return AOUT_TARGET_FORMAT
;
8346 #ifdef OBJ_MAYBE_COFF
8347 case bfd_target_coff_flavour
:
8350 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8351 case bfd_target_elf_flavour
:
8353 if (flag_code
== CODE_64BIT
)
8356 use_rela_relocations
= 1;
8358 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
8367 #endif /* OBJ_MAYBE_ more than one */
8369 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8371 i386_elf_emit_arch_note (void)
8373 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8376 asection
*seg
= now_seg
;
8377 subsegT subseg
= now_subseg
;
8378 Elf_Internal_Note i_note
;
8379 Elf_External_Note e_note
;
8380 asection
*note_secp
;
8383 /* Create the .note section. */
8384 note_secp
= subseg_new (".note", 0);
8385 bfd_set_section_flags (stdoutput
,
8387 SEC_HAS_CONTENTS
| SEC_READONLY
);
8389 /* Process the arch string. */
8390 len
= strlen (cpu_arch_name
);
8392 i_note
.namesz
= len
+ 1;
8394 i_note
.type
= NT_ARCH
;
8395 p
= frag_more (sizeof (e_note
.namesz
));
8396 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8397 p
= frag_more (sizeof (e_note
.descsz
));
8398 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8399 p
= frag_more (sizeof (e_note
.type
));
8400 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8401 p
= frag_more (len
+ 1);
8402 strcpy (p
, cpu_arch_name
);
8404 frag_align (2, 0, 0);
8406 subseg_set (seg
, subseg
);
8412 md_undefined_symbol (name
)
8415 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8416 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8417 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8418 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8422 if (symbol_find (name
))
8423 as_bad (_("GOT already in symbol table"));
8424 GOT_symbol
= symbol_new (name
, undefined_section
,
8425 (valueT
) 0, &zero_address_frag
);
8432 /* Round up a section size to the appropriate boundary. */
8435 md_section_align (segment
, size
)
8436 segT segment ATTRIBUTE_UNUSED
;
8439 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8440 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8442 /* For a.out, force the section size to be aligned. If we don't do
8443 this, BFD will align it for us, but it will not write out the
8444 final bytes of the section. This may be a bug in BFD, but it is
8445 easier to fix it here since that is how the other a.out targets
8449 align
= bfd_get_section_alignment (stdoutput
, segment
);
8450 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8457 /* On the i386, PC-relative offsets are relative to the start of the
8458 next instruction. That is, the address of the offset, plus its
8459 size, since the offset is always the last part of the insn. */
8462 md_pcrel_from (fixS
*fixP
)
8464 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8470 s_bss (int ignore ATTRIBUTE_UNUSED
)
8474 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8476 obj_elf_section_change_hook ();
8478 temp
= get_absolute_expression ();
8479 subseg_set (bss_section
, (subsegT
) temp
);
8480 demand_empty_rest_of_line ();
8486 i386_validate_fix (fixS
*fixp
)
8488 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8490 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8494 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8499 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8501 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8508 tc_gen_reloc (section
, fixp
)
8509 asection
*section ATTRIBUTE_UNUSED
;
8513 bfd_reloc_code_real_type code
;
8515 switch (fixp
->fx_r_type
)
8517 case BFD_RELOC_X86_64_PLT32
:
8518 case BFD_RELOC_X86_64_GOT32
:
8519 case BFD_RELOC_X86_64_GOTPCREL
:
8520 case BFD_RELOC_386_PLT32
:
8521 case BFD_RELOC_386_GOT32
:
8522 case BFD_RELOC_386_GOTOFF
:
8523 case BFD_RELOC_386_GOTPC
:
8524 case BFD_RELOC_386_TLS_GD
:
8525 case BFD_RELOC_386_TLS_LDM
:
8526 case BFD_RELOC_386_TLS_LDO_32
:
8527 case BFD_RELOC_386_TLS_IE_32
:
8528 case BFD_RELOC_386_TLS_IE
:
8529 case BFD_RELOC_386_TLS_GOTIE
:
8530 case BFD_RELOC_386_TLS_LE_32
:
8531 case BFD_RELOC_386_TLS_LE
:
8532 case BFD_RELOC_386_TLS_GOTDESC
:
8533 case BFD_RELOC_386_TLS_DESC_CALL
:
8534 case BFD_RELOC_X86_64_TLSGD
:
8535 case BFD_RELOC_X86_64_TLSLD
:
8536 case BFD_RELOC_X86_64_DTPOFF32
:
8537 case BFD_RELOC_X86_64_DTPOFF64
:
8538 case BFD_RELOC_X86_64_GOTTPOFF
:
8539 case BFD_RELOC_X86_64_TPOFF32
:
8540 case BFD_RELOC_X86_64_TPOFF64
:
8541 case BFD_RELOC_X86_64_GOTOFF64
:
8542 case BFD_RELOC_X86_64_GOTPC32
:
8543 case BFD_RELOC_X86_64_GOT64
:
8544 case BFD_RELOC_X86_64_GOTPCREL64
:
8545 case BFD_RELOC_X86_64_GOTPC64
:
8546 case BFD_RELOC_X86_64_GOTPLT64
:
8547 case BFD_RELOC_X86_64_PLTOFF64
:
8548 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8549 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8551 case BFD_RELOC_VTABLE_ENTRY
:
8552 case BFD_RELOC_VTABLE_INHERIT
:
8554 case BFD_RELOC_32_SECREL
:
8556 code
= fixp
->fx_r_type
;
8558 case BFD_RELOC_X86_64_32S
:
8559 if (!fixp
->fx_pcrel
)
8561 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8562 code
= fixp
->fx_r_type
;
8568 switch (fixp
->fx_size
)
8571 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8572 _("can not do %d byte pc-relative relocation"),
8574 code
= BFD_RELOC_32_PCREL
;
8576 case 1: code
= BFD_RELOC_8_PCREL
; break;
8577 case 2: code
= BFD_RELOC_16_PCREL
; break;
8578 case 4: code
= BFD_RELOC_32_PCREL
; break;
8580 case 8: code
= BFD_RELOC_64_PCREL
; break;
8586 switch (fixp
->fx_size
)
8589 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8590 _("can not do %d byte relocation"),
8592 code
= BFD_RELOC_32
;
8594 case 1: code
= BFD_RELOC_8
; break;
8595 case 2: code
= BFD_RELOC_16
; break;
8596 case 4: code
= BFD_RELOC_32
; break;
8598 case 8: code
= BFD_RELOC_64
; break;
8605 if ((code
== BFD_RELOC_32
8606 || code
== BFD_RELOC_32_PCREL
8607 || code
== BFD_RELOC_X86_64_32S
)
8609 && fixp
->fx_addsy
== GOT_symbol
)
8612 code
= BFD_RELOC_386_GOTPC
;
8614 code
= BFD_RELOC_X86_64_GOTPC32
;
8616 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8618 && fixp
->fx_addsy
== GOT_symbol
)
8620 code
= BFD_RELOC_X86_64_GOTPC64
;
8623 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8624 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8625 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8627 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8629 if (!use_rela_relocations
)
8631 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8632 vtable entry to be used in the relocation's section offset. */
8633 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8634 rel
->address
= fixp
->fx_offset
;
8638 /* Use the rela in 64bit mode. */
8641 if (!fixp
->fx_pcrel
)
8642 rel
->addend
= fixp
->fx_offset
;
8646 case BFD_RELOC_X86_64_PLT32
:
8647 case BFD_RELOC_X86_64_GOT32
:
8648 case BFD_RELOC_X86_64_GOTPCREL
:
8649 case BFD_RELOC_X86_64_TLSGD
:
8650 case BFD_RELOC_X86_64_TLSLD
:
8651 case BFD_RELOC_X86_64_GOTTPOFF
:
8652 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8653 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8654 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8657 rel
->addend
= (section
->vma
8659 + fixp
->fx_addnumber
8660 + md_pcrel_from (fixp
));
8665 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8666 if (rel
->howto
== NULL
)
8668 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8669 _("cannot represent relocation type %s"),
8670 bfd_get_reloc_code_name (code
));
8671 /* Set howto to a garbage value so that we can keep going. */
8672 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8673 assert (rel
->howto
!= NULL
);
8680 /* Parse operands using Intel syntax. This implements a recursive descent
8681 parser based on the BNF grammar published in Appendix B of the MASM 6.1
8684 FIXME: We do not recognize the full operand grammar defined in the MASM
8685 documentation. In particular, all the structure/union and
8686 high-level macro operands are missing.
8688 Uppercase words are terminals, lower case words are non-terminals.
8689 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
8690 bars '|' denote choices. Most grammar productions are implemented in
8691 functions called 'intel_<production>'.
8693 Initial production is 'expr'.
8699 binOp & | AND | \| | OR | ^ | XOR
8701 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
8703 constant digits [[ radixOverride ]]
8705 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD
8743 => expr expr cmpOp e04
8746 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
8747 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
8749 hexdigit a | b | c | d | e | f
8750 | A | B | C | D | E | F
8756 mulOp * | / | % | MOD | << | SHL | >> | SHR
8760 register specialRegister
8764 segmentRegister CS | DS | ES | FS | GS | SS
8766 specialRegister CR0 | CR2 | CR3 | CR4
8767 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
8768 | TR3 | TR4 | TR5 | TR6 | TR7
8770 We simplify the grammar in obvious places (e.g., register parsing is
8771 done by calling parse_register) and eliminate immediate left recursion
8772 to implement a recursive-descent parser.
8776 expr' cmpOp e04 expr'
8828 /* Parsing structure for the intel syntax parser. Used to implement the
8829 semantic actions for the operand grammar. */
8830 struct intel_parser_s
8832 char *op_string
; /* The string being parsed. */
8833 int got_a_float
; /* Whether the operand is a float. */
8834 int op_modifier
; /* Operand modifier. */
8835 int is_mem
; /* 1 if operand is memory reference. */
8836 int in_offset
; /* >=1 if parsing operand of offset. */
8837 int in_bracket
; /* >=1 if parsing operand in brackets. */
8838 const reg_entry
*reg
; /* Last register reference found. */
8839 char *disp
; /* Displacement string being built. */
8840 char *next_operand
; /* Resume point when splitting operands. */
8843 static struct intel_parser_s intel_parser
;
8845 /* Token structure for parsing intel syntax. */
8848 int code
; /* Token code. */
8849 const reg_entry
*reg
; /* Register entry for register tokens. */
8850 char *str
; /* String representation. */
8853 static struct intel_token cur_token
, prev_token
;
8855 /* Token codes for the intel parser. Since T_SHORT is already used
8856 by COFF, undefine it first to prevent a warning. */
8874 #define T_YMMWORD 16
8876 /* Prototypes for intel parser functions. */
8877 static int intel_match_token (int);
8878 static void intel_putback_token (void);
8879 static void intel_get_token (void);
8880 static int intel_expr (void);
8881 static int intel_e04 (void);
8882 static int intel_e05 (void);
8883 static int intel_e06 (void);
8884 static int intel_e09 (void);
8885 static int intel_e10 (void);
8886 static int intel_e11 (void);
8889 i386_intel_operand (char *operand_string
, int got_a_float
)
8893 const reg_entry
*final_base
= i
.base_reg
;
8894 const reg_entry
*final_index
= i
.index_reg
;
8896 p
= intel_parser
.op_string
= xstrdup (operand_string
);
8897 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
8901 /* Initialize token holders. */
8902 cur_token
.code
= prev_token
.code
= T_NIL
;
8903 cur_token
.reg
= prev_token
.reg
= NULL
;
8904 cur_token
.str
= prev_token
.str
= NULL
;
8906 /* Initialize parser structure. */
8907 intel_parser
.got_a_float
= got_a_float
;
8908 intel_parser
.op_modifier
= 0;
8909 intel_parser
.is_mem
= 0;
8910 intel_parser
.in_offset
= 0;
8911 intel_parser
.in_bracket
= 0;
8912 intel_parser
.reg
= NULL
;
8913 intel_parser
.disp
[0] = '\0';
8914 intel_parser
.next_operand
= NULL
;
8919 /* Read the first token and start the parser. */
8921 ret
= intel_expr ();
8926 if (cur_token
.code
!= T_NIL
)
8928 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8929 current_templates
->start
->name
, cur_token
.str
);
8932 /* If we found a memory reference, hand it over to i386_displacement
8933 to fill in the rest of the operand fields. */
8934 else if (intel_parser
.is_mem
)
8936 if ((i
.mem_operands
== 1
8937 && !current_templates
->start
->opcode_modifier
.isstring
)
8938 || i
.mem_operands
== 2)
8940 as_bad (_("too many memory references for '%s'"),
8941 current_templates
->start
->name
);
8946 char *s
= intel_parser
.disp
;
8948 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
8949 /* See the comments in intel_bracket_expr. */
8950 as_warn (_("Treating `%s' as memory reference"), operand_string
);
8952 /* Add the displacement expression. */
8954 ret
= i386_displacement (s
, s
+ strlen (s
));
8957 /* Swap base and index in 16-bit memory operands like
8958 [si+bx]. Since i386_index_check is also used in AT&T
8959 mode we have to do that here. */
8962 && i
.base_reg
->reg_type
.bitfield
.reg16
8963 && i
.index_reg
->reg_type
.bitfield
.reg16
8964 && i
.base_reg
->reg_num
>= 6
8965 && i
.index_reg
->reg_num
< 6)
8967 const reg_entry
*base
= i
.index_reg
;
8969 i
.index_reg
= i
.base_reg
;
8972 ret
= i386_index_check (operand_string
);
8976 i
.types
[this_operand
].bitfield
.mem
= 1;
8982 /* Constant and OFFSET expressions are handled by i386_immediate. */
8983 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
8984 || intel_parser
.reg
== NULL
)
8986 if (i
.mem_operands
< 2 && i
.seg
[i
.mem_operands
])
8988 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
8989 as_warn (_("Segment override ignored"));
8990 i
.seg
[i
.mem_operands
] = NULL
;
8992 ret
= i386_immediate (intel_parser
.disp
);
8995 if (!final_base
&& !final_index
)
8997 final_base
= i
.base_reg
;
8998 final_index
= i
.index_reg
;
9001 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
9003 if (!ret
|| !intel_parser
.next_operand
)
9005 intel_parser
.op_string
= intel_parser
.next_operand
;
9006 this_operand
= i
.operands
++;
9007 i
.types
[this_operand
].bitfield
.unspecified
= 1;
9011 free (intel_parser
.disp
);
9013 if (final_base
|| final_index
)
9015 i
.base_reg
= final_base
;
9016 i
.index_reg
= final_index
;
9022 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
9026 expr' cmpOp e04 expr'
9031 /* XXX Implement the comparison operators. */
9032 return intel_e04 ();
9049 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9050 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
9052 if (cur_token
.code
== '+')
9054 else if (cur_token
.code
== '-')
9055 nregs
= NUM_ADDRESS_REGS
;
9059 strcat (intel_parser
.disp
, cur_token
.str
);
9060 intel_match_token (cur_token
.code
);
9071 int nregs
= ~NUM_ADDRESS_REGS
;
9078 if (cur_token
.code
== '&'
9079 || cur_token
.code
== '|'
9080 || cur_token
.code
== '^')
9084 str
[0] = cur_token
.code
;
9086 strcat (intel_parser
.disp
, str
);
9091 intel_match_token (cur_token
.code
);
9096 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9097 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
9108 int nregs
= ~NUM_ADDRESS_REGS
;
9115 if (cur_token
.code
== '*'
9116 || cur_token
.code
== '/'
9117 || cur_token
.code
== '%')
9121 str
[0] = cur_token
.code
;
9123 strcat (intel_parser
.disp
, str
);
9125 else if (cur_token
.code
== T_SHL
)
9126 strcat (intel_parser
.disp
, "<<");
9127 else if (cur_token
.code
== T_SHR
)
9128 strcat (intel_parser
.disp
, ">>");
9132 intel_match_token (cur_token
.code
);
9137 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9138 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
9156 int nregs
= ~NUM_ADDRESS_REGS
;
9161 /* Don't consume constants here. */
9162 if (cur_token
.code
== '+' || cur_token
.code
== '-')
9164 /* Need to look one token ahead - if the next token
9165 is a constant, the current token is its sign. */
9168 intel_match_token (cur_token
.code
);
9169 next_code
= cur_token
.code
;
9170 intel_putback_token ();
9171 if (next_code
== T_CONST
)
9175 /* e09 OFFSET e09 */
9176 if (cur_token
.code
== T_OFFSET
)
9179 ++intel_parser
.in_offset
;
9183 else if (cur_token
.code
== T_SHORT
)
9184 intel_parser
.op_modifier
|= 1 << T_SHORT
;
9187 else if (cur_token
.code
== '+')
9188 strcat (intel_parser
.disp
, "+");
9193 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
9199 str
[0] = cur_token
.code
;
9201 strcat (intel_parser
.disp
, str
);
9208 intel_match_token (cur_token
.code
);
9216 /* e09' PTR e10 e09' */
9217 if (cur_token
.code
== T_PTR
)
9221 if (prev_token
.code
== T_BYTE
)
9223 suffix
= BYTE_MNEM_SUFFIX
;
9224 i
.types
[this_operand
].bitfield
.byte
= 1;
9227 else if (prev_token
.code
== T_WORD
)
9229 if ((current_templates
->start
->name
[0] == 'l'
9230 && current_templates
->start
->name
[2] == 's'
9231 && current_templates
->start
->name
[3] == 0)
9232 || current_templates
->start
->base_opcode
== 0x62 /* bound */)
9233 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9234 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
9235 suffix
= SHORT_MNEM_SUFFIX
;
9237 suffix
= WORD_MNEM_SUFFIX
;
9238 i
.types
[this_operand
].bitfield
.word
= 1;
9241 else if (prev_token
.code
== T_DWORD
)
9243 if ((current_templates
->start
->name
[0] == 'l'
9244 && current_templates
->start
->name
[2] == 's'
9245 && current_templates
->start
->name
[3] == 0)
9246 || current_templates
->start
->base_opcode
== 0x62 /* bound */)
9247 suffix
= WORD_MNEM_SUFFIX
;
9248 else if (flag_code
== CODE_16BIT
9249 && (current_templates
->start
->opcode_modifier
.jump
9250 || current_templates
->start
->opcode_modifier
.jumpdword
))
9251 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9252 else if (intel_parser
.got_a_float
== 1) /* "f..." */
9253 suffix
= SHORT_MNEM_SUFFIX
;
9255 suffix
= LONG_MNEM_SUFFIX
;
9256 i
.types
[this_operand
].bitfield
.dword
= 1;
9259 else if (prev_token
.code
== T_FWORD
)
9261 if (current_templates
->start
->name
[0] == 'l'
9262 && current_templates
->start
->name
[2] == 's'
9263 && current_templates
->start
->name
[3] == 0)
9264 suffix
= LONG_MNEM_SUFFIX
;
9265 else if (!intel_parser
.got_a_float
)
9267 if (flag_code
== CODE_16BIT
)
9268 add_prefix (DATA_PREFIX_OPCODE
);
9269 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9272 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9273 i
.types
[this_operand
].bitfield
.fword
= 1;
9276 else if (prev_token
.code
== T_QWORD
)
9278 if (current_templates
->start
->base_opcode
== 0x62 /* bound */
9279 || intel_parser
.got_a_float
== 1) /* "f..." */
9280 suffix
= LONG_MNEM_SUFFIX
;
9282 suffix
= QWORD_MNEM_SUFFIX
;
9283 i
.types
[this_operand
].bitfield
.qword
= 1;
9286 else if (prev_token
.code
== T_TBYTE
)
9288 if (intel_parser
.got_a_float
== 1)
9289 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9291 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9294 else if (prev_token
.code
== T_XMMWORD
)
9296 suffix
= XMMWORD_MNEM_SUFFIX
;
9297 i
.types
[this_operand
].bitfield
.xmmword
= 1;
9300 else if (prev_token
.code
== T_YMMWORD
)
9302 suffix
= YMMWORD_MNEM_SUFFIX
;
9303 i
.types
[this_operand
].bitfield
.ymmword
= 1;
9308 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
9312 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9314 /* Operands for jump/call using 'ptr' notation denote absolute
9316 if (current_templates
->start
->opcode_modifier
.jump
9317 || current_templates
->start
->opcode_modifier
.jumpdword
)
9318 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9320 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
9324 else if (i
.suffix
!= suffix
)
9326 as_bad (_("Conflicting operand modifiers"));
9332 /* e09' : e10 e09' */
9333 else if (cur_token
.code
== ':')
9335 if (prev_token
.code
!= T_REG
)
9337 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
9338 segment/group identifier (which we don't have), using comma
9339 as the operand separator there is even less consistent, since
9340 there all branches only have a single operand. */
9341 if (this_operand
!= 0
9342 || intel_parser
.in_offset
9343 || intel_parser
.in_bracket
9344 || (!current_templates
->start
->opcode_modifier
.jump
9345 && !current_templates
->start
->opcode_modifier
.jumpdword
9346 && !current_templates
->start
->opcode_modifier
.jumpintersegment
9347 && !current_templates
->start
->operand_types
[0].bitfield
.jumpabsolute
))
9348 return intel_match_token (T_NIL
);
9349 /* Remember the start of the 2nd operand and terminate 1st
9351 XXX This isn't right, yet (when SSSS:OOOO is right operand of
9352 another expression), but it gets at least the simplest case
9353 (a plain number or symbol on the left side) right. */
9354 intel_parser
.next_operand
= intel_parser
.op_string
;
9355 *--intel_parser
.op_string
= '\0';
9356 return intel_match_token (':');
9364 intel_match_token (cur_token
.code
);
9370 --intel_parser
.in_offset
;
9373 if (NUM_ADDRESS_REGS
> nregs
)
9375 as_bad (_("Invalid operand to `OFFSET'"));
9378 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
9381 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9382 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
9387 intel_bracket_expr (void)
9389 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
9390 const char *start
= intel_parser
.op_string
;
9393 if (i
.op
[this_operand
].regs
)
9394 return intel_match_token (T_NIL
);
9396 intel_match_token ('[');
9398 /* Mark as a memory operand only if it's not already known to be an
9399 offset expression. If it's an offset expression, we need to keep
9401 if (!intel_parser
.in_offset
)
9403 ++intel_parser
.in_bracket
;
9405 /* Operands for jump/call inside brackets denote absolute addresses. */
9406 if (current_templates
->start
->opcode_modifier
.jump
9407 || current_templates
->start
->opcode_modifier
.jumpdword
)
9408 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9410 /* Unfortunately gas always diverged from MASM in a respect that can't
9411 be easily fixed without risking to break code sequences likely to be
9412 encountered (the testsuite even check for this): MASM doesn't consider
9413 an expression inside brackets unconditionally as a memory reference.
9414 When that is e.g. a constant, an offset expression, or the sum of the
9415 two, this is still taken as a constant load. gas, however, always
9416 treated these as memory references. As a compromise, we'll try to make
9417 offset expressions inside brackets work the MASM way (since that's
9418 less likely to be found in real world code), but make constants alone
9419 continue to work the traditional gas way. In either case, issue a
9421 intel_parser
.op_modifier
&= ~was_offset
;
9424 strcat (intel_parser
.disp
, "[");
9426 /* Add a '+' to the displacement string if necessary. */
9427 if (*intel_parser
.disp
!= '\0'
9428 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
9429 strcat (intel_parser
.disp
, "+");
9432 && (len
= intel_parser
.op_string
- start
- 1,
9433 intel_match_token (']')))
9435 /* Preserve brackets when the operand is an offset expression. */
9436 if (intel_parser
.in_offset
)
9437 strcat (intel_parser
.disp
, "]");
9440 --intel_parser
.in_bracket
;
9441 if (i
.base_reg
|| i
.index_reg
)
9442 intel_parser
.is_mem
= 1;
9443 if (!intel_parser
.is_mem
)
9445 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
9446 /* Defer the warning until all of the operand was parsed. */
9447 intel_parser
.is_mem
= -1;
9448 else if (!quiet_warnings
)
9449 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
9450 len
, start
, len
, start
);
9453 intel_parser
.op_modifier
|= was_offset
;
9470 while (cur_token
.code
== '[')
9472 if (!intel_bracket_expr ())
9498 switch (cur_token
.code
)
9502 intel_match_token ('(');
9503 strcat (intel_parser
.disp
, "(");
9505 if (intel_expr () && intel_match_token (')'))
9507 strcat (intel_parser
.disp
, ")");
9514 return intel_bracket_expr ();
9519 strcat (intel_parser
.disp
, cur_token
.str
);
9520 intel_match_token (cur_token
.code
);
9522 /* Mark as a memory operand only if it's not already known to be an
9523 offset expression. */
9524 if (!intel_parser
.in_offset
)
9525 intel_parser
.is_mem
= 1;
9532 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
9534 intel_match_token (T_REG
);
9536 /* Check for segment change. */
9537 if (cur_token
.code
== ':')
9539 if (!reg
->reg_type
.bitfield
.sreg2
9540 && !reg
->reg_type
.bitfield
.sreg3
)
9542 as_bad (_("`%s' is not a valid segment register"),
9546 else if (i
.mem_operands
>= 2)
9547 as_warn (_("Segment override ignored"));
9548 else if (i
.seg
[i
.mem_operands
])
9549 as_warn (_("Extra segment override ignored"));
9552 if (!intel_parser
.in_offset
)
9553 intel_parser
.is_mem
= 1;
9554 switch (reg
->reg_num
)
9557 i
.seg
[i
.mem_operands
] = &es
;
9560 i
.seg
[i
.mem_operands
] = &cs
;
9563 i
.seg
[i
.mem_operands
] = &ss
;
9566 i
.seg
[i
.mem_operands
] = &ds
;
9569 i
.seg
[i
.mem_operands
] = &fs
;
9572 i
.seg
[i
.mem_operands
] = &gs
;
9578 else if (reg
->reg_type
.bitfield
.sreg3
&& reg
->reg_num
== RegFlat
)
9580 as_bad (_("cannot use `FLAT' here"));
9584 /* Not a segment register. Check for register scaling. */
9585 else if (cur_token
.code
== '*')
9587 if (!intel_parser
.in_bracket
)
9589 as_bad (_("Register scaling only allowed in memory operands"));
9593 if (reg
->reg_type
.bitfield
.reg16
) /* Disallow things like [si*1]. */
9594 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
9595 else if (i
.index_reg
)
9596 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
9598 /* What follows must be a valid scale. */
9599 intel_match_token ('*');
9601 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9603 /* Set the scale after setting the register (otherwise,
9604 i386_scale will complain) */
9605 if (cur_token
.code
== '+' || cur_token
.code
== '-')
9607 char *str
, sign
= cur_token
.code
;
9608 intel_match_token (cur_token
.code
);
9609 if (cur_token
.code
!= T_CONST
)
9611 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9615 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
9616 strcpy (str
+ 1, cur_token
.str
);
9618 if (!i386_scale (str
))
9622 else if (!i386_scale (cur_token
.str
))
9624 intel_match_token (cur_token
.code
);
9627 /* No scaling. If this is a memory operand, the register is either a
9628 base register (first occurrence) or an index register (second
9630 else if (intel_parser
.in_bracket
)
9635 else if (!i
.index_reg
)
9639 as_bad (_("Too many register references in memory operand"));
9643 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9646 /* It's neither base nor index. */
9647 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
9649 i386_operand_type temp
= reg
->reg_type
;
9650 temp
.bitfield
.baseindex
= 0;
9651 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9653 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9654 i
.op
[this_operand
].regs
= reg
;
9659 as_bad (_("Invalid use of register"));
9663 /* Since registers are not part of the displacement string (except
9664 when we're parsing offset operands), we may need to remove any
9665 preceding '+' from the displacement string. */
9666 if (*intel_parser
.disp
!= '\0'
9667 && !intel_parser
.in_offset
)
9669 char *s
= intel_parser
.disp
;
9670 s
+= strlen (s
) - 1;
9695 intel_match_token (cur_token
.code
);
9697 if (cur_token
.code
== T_PTR
)
9700 /* It must have been an identifier. */
9701 intel_putback_token ();
9702 cur_token
.code
= T_ID
;
9708 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
9712 /* The identifier represents a memory reference only if it's not
9713 preceded by an offset modifier and if it's not an equate. */
9714 symbolP
= symbol_find(cur_token
.str
);
9715 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
9716 intel_parser
.is_mem
= 1;
9724 char *save_str
, sign
= 0;
9726 /* Allow constants that start with `+' or `-'. */
9727 if (cur_token
.code
== '-' || cur_token
.code
== '+')
9729 sign
= cur_token
.code
;
9730 intel_match_token (cur_token
.code
);
9731 if (cur_token
.code
!= T_CONST
)
9733 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9739 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
9740 strcpy (save_str
+ !!sign
, cur_token
.str
);
9744 /* Get the next token to check for register scaling. */
9745 intel_match_token (cur_token
.code
);
9747 /* Check if this constant is a scaling factor for an
9749 if (cur_token
.code
== '*')
9751 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
9753 const reg_entry
*reg
= cur_token
.reg
;
9755 if (!intel_parser
.in_bracket
)
9757 as_bad (_("Register scaling only allowed "
9758 "in memory operands"));
9762 /* Disallow things like [1*si].
9763 sp and esp are invalid as index. */
9764 if (reg
->reg_type
.bitfield
.reg16
)
9765 reg
= i386_regtab
+ REGNAM_AX
+ 4;
9766 else if (i
.index_reg
)
9767 reg
= i386_regtab
+ REGNAM_EAX
+ 4;
9769 /* The constant is followed by `* reg', so it must be
9772 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9774 /* Set the scale after setting the register (otherwise,
9775 i386_scale will complain) */
9776 if (!i386_scale (save_str
))
9778 intel_match_token (T_REG
);
9780 /* Since registers are not part of the displacement
9781 string, we may need to remove any preceding '+' from
9782 the displacement string. */
9783 if (*intel_parser
.disp
!= '\0')
9785 char *s
= intel_parser
.disp
;
9786 s
+= strlen (s
) - 1;
9796 /* The constant was not used for register scaling. Since we have
9797 already consumed the token following `*' we now need to put it
9798 back in the stream. */
9799 intel_putback_token ();
9802 /* Add the constant to the displacement string. */
9803 strcat (intel_parser
.disp
, save_str
);
9810 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
9814 /* Match the given token against cur_token. If they match, read the next
9815 token from the operand string. */
9817 intel_match_token (int code
)
9819 if (cur_token
.code
== code
)
9826 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
9831 /* Read a new token from intel_parser.op_string and store it in cur_token. */
9833 intel_get_token (void)
9836 const reg_entry
*reg
;
9837 struct intel_token new_token
;
9839 new_token
.code
= T_NIL
;
9840 new_token
.reg
= NULL
;
9841 new_token
.str
= NULL
;
9843 /* Free the memory allocated to the previous token and move
9844 cur_token to prev_token. */
9846 free (prev_token
.str
);
9848 prev_token
= cur_token
;
9850 /* Skip whitespace. */
9851 while (is_space_char (*intel_parser
.op_string
))
9852 intel_parser
.op_string
++;
9854 /* Return an empty token if we find nothing else on the line. */
9855 if (*intel_parser
.op_string
== '\0')
9857 cur_token
= new_token
;
9861 /* The new token cannot be larger than the remainder of the operand
9863 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
9864 new_token
.str
[0] = '\0';
9866 if (strchr ("0123456789", *intel_parser
.op_string
))
9868 char *p
= new_token
.str
;
9869 char *q
= intel_parser
.op_string
;
9870 new_token
.code
= T_CONST
;
9872 /* Allow any kind of identifier char to encompass floating point and
9873 hexadecimal numbers. */
9874 while (is_identifier_char (*q
))
9878 /* Recognize special symbol names [0-9][bf]. */
9879 if (strlen (intel_parser
.op_string
) == 2
9880 && (intel_parser
.op_string
[1] == 'b'
9881 || intel_parser
.op_string
[1] == 'f'))
9882 new_token
.code
= T_ID
;
9885 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
9887 size_t len
= end_op
- intel_parser
.op_string
;
9889 new_token
.code
= T_REG
;
9890 new_token
.reg
= reg
;
9892 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
9893 new_token
.str
[len
] = '\0';
9896 else if (is_identifier_char (*intel_parser
.op_string
))
9898 char *p
= new_token
.str
;
9899 char *q
= intel_parser
.op_string
;
9901 /* A '.' or '$' followed by an identifier char is an identifier.
9902 Otherwise, it's operator '.' followed by an expression. */
9903 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
9905 new_token
.code
= '.';
9906 new_token
.str
[0] = '.';
9907 new_token
.str
[1] = '\0';
9911 while (is_identifier_char (*q
) || *q
== '@')
9915 if (strcasecmp (new_token
.str
, "NOT") == 0)
9916 new_token
.code
= '~';
9918 else if (strcasecmp (new_token
.str
, "MOD") == 0)
9919 new_token
.code
= '%';
9921 else if (strcasecmp (new_token
.str
, "AND") == 0)
9922 new_token
.code
= '&';
9924 else if (strcasecmp (new_token
.str
, "OR") == 0)
9925 new_token
.code
= '|';
9927 else if (strcasecmp (new_token
.str
, "XOR") == 0)
9928 new_token
.code
= '^';
9930 else if (strcasecmp (new_token
.str
, "SHL") == 0)
9931 new_token
.code
= T_SHL
;
9933 else if (strcasecmp (new_token
.str
, "SHR") == 0)
9934 new_token
.code
= T_SHR
;
9936 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
9937 new_token
.code
= T_BYTE
;
9939 else if (strcasecmp (new_token
.str
, "WORD") == 0)
9940 new_token
.code
= T_WORD
;
9942 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
9943 new_token
.code
= T_DWORD
;
9945 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
9946 new_token
.code
= T_FWORD
;
9948 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
9949 new_token
.code
= T_QWORD
;
9951 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
9952 /* XXX remove (gcc still uses it) */
9953 || strcasecmp (new_token
.str
, "XWORD") == 0)
9954 new_token
.code
= T_TBYTE
;
9956 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
9957 || strcasecmp (new_token
.str
, "OWORD") == 0)
9958 new_token
.code
= T_XMMWORD
;
9960 else if (strcasecmp (new_token
.str
, "YMMWORD") == 0)
9961 new_token
.code
= T_YMMWORD
;
9963 else if (strcasecmp (new_token
.str
, "PTR") == 0)
9964 new_token
.code
= T_PTR
;
9966 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
9967 new_token
.code
= T_SHORT
;
9969 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
9971 new_token
.code
= T_OFFSET
;
9973 /* ??? This is not mentioned in the MASM grammar but gcc
9974 makes use of it with -mintel-syntax. OFFSET may be
9975 followed by FLAT: */
9976 if (strncasecmp (q
, " FLAT:", 6) == 0)
9977 strcat (new_token
.str
, " FLAT:");
9981 new_token
.code
= T_ID
;
9985 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
9987 new_token
.code
= *intel_parser
.op_string
;
9988 new_token
.str
[0] = *intel_parser
.op_string
;
9989 new_token
.str
[1] = '\0';
9992 else if (strchr ("<>", *intel_parser
.op_string
)
9993 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
9995 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
9996 new_token
.str
[0] = *intel_parser
.op_string
;
9997 new_token
.str
[1] = *intel_parser
.op_string
;
9998 new_token
.str
[2] = '\0';
10002 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
10004 intel_parser
.op_string
+= strlen (new_token
.str
);
10005 cur_token
= new_token
;
10008 /* Put cur_token back into the token stream and make cur_token point to
10011 intel_putback_token (void)
10013 if (cur_token
.code
!= T_NIL
)
10015 intel_parser
.op_string
-= strlen (cur_token
.str
);
10016 free (cur_token
.str
);
10018 cur_token
= prev_token
;
10020 /* Forget prev_token. */
10021 prev_token
.code
= T_NIL
;
10022 prev_token
.reg
= NULL
;
10023 prev_token
.str
= NULL
;
10027 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10029 int saved_naked_reg
;
10030 char saved_register_dot
;
10032 saved_naked_reg
= allow_naked_reg
;
10033 allow_naked_reg
= 1;
10034 saved_register_dot
= register_chars
['.'];
10035 register_chars
['.'] = '.';
10036 allow_pseudo_reg
= 1;
10037 expression_and_evaluate (exp
);
10038 allow_pseudo_reg
= 0;
10039 register_chars
['.'] = saved_register_dot
;
10040 allow_naked_reg
= saved_naked_reg
;
10042 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10044 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10046 exp
->X_op
= O_constant
;
10047 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10048 .dw2_regnum
[flag_code
>> 1];
10051 exp
->X_op
= O_illegal
;
10056 tc_x86_frame_initial_instructions (void)
10058 static unsigned int sp_regno
[2];
10060 if (!sp_regno
[flag_code
>> 1])
10062 char *saved_input
= input_line_pointer
;
10063 char sp
[][4] = {"esp", "rsp"};
10066 input_line_pointer
= sp
[flag_code
>> 1];
10067 tc_x86_parse_to_dw2regnum (&exp
);
10068 assert (exp
.X_op
== O_constant
);
10069 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10070 input_line_pointer
= saved_input
;
10073 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10074 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10078 i386_elf_section_type (const char *str
, size_t len
)
10080 if (flag_code
== CODE_64BIT
10081 && len
== sizeof ("unwind") - 1
10082 && strncmp (str
, "unwind", 6) == 0)
10083 return SHT_X86_64_UNWIND
;
10090 i386_solaris_fix_up_eh_frame (segT sec
)
10092 if (flag_code
== CODE_64BIT
)
10093 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10099 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10103 expr
.X_op
= O_secrel
;
10104 expr
.X_add_symbol
= symbol
;
10105 expr
.X_add_number
= 0;
10106 emit_expr (&expr
, size
);
10110 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10111 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10114 x86_64_section_letter (int letter
, char **ptr_msg
)
10116 if (flag_code
== CODE_64BIT
)
10119 return SHF_X86_64_LARGE
;
10121 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
10124 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
10129 x86_64_section_word (char *str
, size_t len
)
10131 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10132 return SHF_X86_64_LARGE
;
10138 handle_large_common (int small ATTRIBUTE_UNUSED
)
10140 if (flag_code
!= CODE_64BIT
)
10142 s_comm_internal (0, elf_common_parse
);
10143 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10147 static segT lbss_section
;
10148 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10149 asection
*saved_bss_section
= bss_section
;
10151 if (lbss_section
== NULL
)
10153 flagword applicable
;
10154 segT seg
= now_seg
;
10155 subsegT subseg
= now_subseg
;
10157 /* The .lbss section is for local .largecomm symbols. */
10158 lbss_section
= subseg_new (".lbss", 0);
10159 applicable
= bfd_applicable_section_flags (stdoutput
);
10160 bfd_set_section_flags (stdoutput
, lbss_section
,
10161 applicable
& SEC_ALLOC
);
10162 seg_info (lbss_section
)->bss
= 1;
10164 subseg_set (seg
, subseg
);
10167 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10168 bss_section
= lbss_section
;
10170 s_comm_internal (0, elf_common_parse
);
10172 elf_com_section_ptr
= saved_com_section_ptr
;
10173 bss_section
= saved_bss_section
;
10176 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */