1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
5 Free Software Foundation, Inc.
7 This file is part of GAS, the GNU Assembler.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
21 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 /* Intel 80386 machine specific gas.
25 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
26 x86_64 support by Jan Hubicka (jh@suse.cz)
27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
28 Bugs & suggestions are completely welcome. This is free software.
29 Please help us make it better. */
32 #include "safe-ctype.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
36 #include "elf/x86-64.h"
37 #include "opcodes/i386-init.h"
39 #ifndef REGISTER_WARNINGS
40 #define REGISTER_WARNINGS 1
43 #ifndef INFER_ADDR_PREFIX
44 #define INFER_ADDR_PREFIX 1
48 #define DEFAULT_ARCH "i386"
53 #define INLINE __inline__
59 /* Prefixes will be emitted in the order defined below.
60 WAIT_PREFIX must be the first prefix since FWAIT is really is an
61 instruction, and so must come before any prefixes.
62 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
63 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
69 #define HLE_PREFIX REP_PREFIX
70 #define BND_PREFIX REP_PREFIX
72 #define REX_PREFIX 6 /* must come last. */
73 #define MAX_PREFIXES 7 /* max prefixes per opcode */
75 /* we define the syntax here (modulo base,index,scale syntax) */
76 #define REGISTER_PREFIX '%'
77 #define IMMEDIATE_PREFIX '$'
78 #define ABSOLUTE_PREFIX '*'
80 /* these are the instruction mnemonic suffixes in AT&T syntax or
81 memory operand size in Intel syntax. */
82 #define WORD_MNEM_SUFFIX 'w'
83 #define BYTE_MNEM_SUFFIX 'b'
84 #define SHORT_MNEM_SUFFIX 's'
85 #define LONG_MNEM_SUFFIX 'l'
86 #define QWORD_MNEM_SUFFIX 'q'
87 #define XMMWORD_MNEM_SUFFIX 'x'
88 #define YMMWORD_MNEM_SUFFIX 'y'
89 /* Intel Syntax. Use a non-ascii letter since since it never appears
91 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
93 #define END_OF_INSN '\0'
96 'templates' is for grouping together 'template' structures for opcodes
97 of the same name. This is only used for storing the insns in the grand
98 ole hash table of insns.
99 The templates themselves start at START and range up to (but not including)
104 const insn_template
*start
;
105 const insn_template
*end
;
109 /* 386 operand encoding bytes: see 386 book for details of this. */
112 unsigned int regmem
; /* codes register or memory operand */
113 unsigned int reg
; /* codes register operand (or extended opcode) */
114 unsigned int mode
; /* how to interpret regmem & reg */
118 /* x86-64 extension prefix. */
119 typedef int rex_byte
;
121 /* 386 opcode byte to code indirect addressing. */
130 /* x86 arch names, types and features */
133 const char *name
; /* arch name */
134 unsigned int len
; /* arch string length */
135 enum processor_type type
; /* arch type */
136 i386_cpu_flags flags
; /* cpu feature flags */
137 unsigned int skip
; /* show_arch should skip this. */
138 unsigned int negated
; /* turn off indicated flags. */
142 static void update_code_flag (int, int);
143 static void set_code_flag (int);
144 static void set_16bit_gcc_code_flag (int);
145 static void set_intel_syntax (int);
146 static void set_intel_mnemonic (int);
147 static void set_allow_index_reg (int);
148 static void set_check (int);
149 static void set_cpu_arch (int);
151 static void pe_directive_secrel (int);
153 static void signed_cons (int);
154 static char *output_invalid (int c
);
155 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
157 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
159 static int i386_att_operand (char *);
160 static int i386_intel_operand (char *, int);
161 static int i386_intel_simplify (expressionS
*);
162 static int i386_intel_parse_name (const char *, expressionS
*);
163 static const reg_entry
*parse_register (char *, char **);
164 static char *parse_insn (char *, char *);
165 static char *parse_operands (char *, const char *);
166 static void swap_operands (void);
167 static void swap_2_operands (int, int);
168 static void optimize_imm (void);
169 static void optimize_disp (void);
170 static const insn_template
*match_template (void);
171 static int check_string (void);
172 static int process_suffix (void);
173 static int check_byte_reg (void);
174 static int check_long_reg (void);
175 static int check_qword_reg (void);
176 static int check_word_reg (void);
177 static int finalize_imm (void);
178 static int process_operands (void);
179 static const seg_entry
*build_modrm_byte (void);
180 static void output_insn (void);
181 static void output_imm (fragS
*, offsetT
);
182 static void output_disp (fragS
*, offsetT
);
184 static void s_bss (int);
186 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
187 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
190 static const char *default_arch
= DEFAULT_ARCH
;
195 /* VEX prefix is either 2 byte or 3 byte. */
196 unsigned char bytes
[3];
198 /* Destination or source register specifier. */
199 const reg_entry
*register_specifier
;
202 /* 'md_assemble ()' gathers together information and puts it into a
209 const reg_entry
*regs
;
214 operand_size_mismatch
,
215 operand_type_mismatch
,
216 register_type_mismatch
,
217 number_of_operands_mismatch
,
218 invalid_instruction_suffix
,
221 unsupported_with_intel_mnemonic
,
224 invalid_vsib_address
,
225 invalid_vector_register_set
,
226 unsupported_vector_index_register
231 /* TM holds the template for the insn were currently assembling. */
234 /* SUFFIX holds the instruction size suffix for byte, word, dword
235 or qword, if given. */
238 /* OPERANDS gives the number of given operands. */
239 unsigned int operands
;
241 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
242 of given register, displacement, memory operands and immediate
244 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
246 /* TYPES [i] is the type (see above #defines) which tells us how to
247 use OP[i] for the corresponding operand. */
248 i386_operand_type types
[MAX_OPERANDS
];
250 /* Displacement expression, immediate expression, or register for each
252 union i386_op op
[MAX_OPERANDS
];
254 /* Flags for operands. */
255 unsigned int flags
[MAX_OPERANDS
];
256 #define Operand_PCrel 1
258 /* Relocation type for operand */
259 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
261 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
262 the base index byte below. */
263 const reg_entry
*base_reg
;
264 const reg_entry
*index_reg
;
265 unsigned int log2_scale_factor
;
267 /* SEG gives the seg_entries of this insn. They are zero unless
268 explicit segment overrides are given. */
269 const seg_entry
*seg
[2];
271 /* PREFIX holds all the given prefix opcodes (usually null).
272 PREFIXES is the number of prefix opcodes. */
273 unsigned int prefixes
;
274 unsigned char prefix
[MAX_PREFIXES
];
276 /* RM and SIB are the modrm byte and the sib byte where the
277 addressing modes of this insn are encoded. */
283 /* Swap operand in encoding. */
284 unsigned int swap_operand
;
286 /* Prefer 8bit or 32bit displacement in encoding. */
289 disp_encoding_default
= 0,
295 const char *rep_prefix
;
298 const char *hle_prefix
;
300 /* Have BND prefix. */
301 const char *bnd_prefix
;
304 enum i386_error error
;
307 typedef struct _i386_insn i386_insn
;
309 /* List of chars besides those in app.c:symbol_chars that can start an
310 operand. Used to prevent the scrubber eating vital white-space. */
311 const char extra_symbol_chars
[] = "*%-(["
320 #if (defined (TE_I386AIX) \
321 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
322 && !defined (TE_GNU) \
323 && !defined (TE_LINUX) \
324 && !defined (TE_NACL) \
325 && !defined (TE_NETWARE) \
326 && !defined (TE_FreeBSD) \
327 && !defined (TE_DragonFly) \
328 && !defined (TE_NetBSD)))
329 /* This array holds the chars that always start a comment. If the
330 pre-processor is disabled, these aren't very useful. The option
331 --divide will remove '/' from this list. */
332 const char *i386_comment_chars
= "#/";
333 #define SVR4_COMMENT_CHARS 1
334 #define PREFIX_SEPARATOR '\\'
337 const char *i386_comment_chars
= "#";
338 #define PREFIX_SEPARATOR '/'
341 /* This array holds the chars that only start a comment at the beginning of
342 a line. If the line seems to have the form '# 123 filename'
343 .line and .file directives will appear in the pre-processed output.
344 Note that input_file.c hand checks for '#' at the beginning of the
345 first line of the input file. This is because the compiler outputs
346 #NO_APP at the beginning of its output.
347 Also note that comments started like this one will always work if
348 '/' isn't otherwise defined. */
349 const char line_comment_chars
[] = "#/";
351 const char line_separator_chars
[] = ";";
353 /* Chars that can be used to separate mant from exp in floating point
355 const char EXP_CHARS
[] = "eE";
357 /* Chars that mean this number is a floating point constant
360 const char FLT_CHARS
[] = "fFdDxX";
362 /* Tables for lexical analysis. */
363 static char mnemonic_chars
[256];
364 static char register_chars
[256];
365 static char operand_chars
[256];
366 static char identifier_chars
[256];
367 static char digit_chars
[256];
369 /* Lexical macros. */
370 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
371 #define is_operand_char(x) (operand_chars[(unsigned char) x])
372 #define is_register_char(x) (register_chars[(unsigned char) x])
373 #define is_space_char(x) ((x) == ' ')
374 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
375 #define is_digit_char(x) (digit_chars[(unsigned char) x])
377 /* All non-digit non-letter characters that may occur in an operand. */
378 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
380 /* md_assemble() always leaves the strings it's passed unaltered. To
381 effect this we maintain a stack of saved characters that we've smashed
382 with '\0's (indicating end of strings for various sub-fields of the
383 assembler instruction). */
384 static char save_stack
[32];
385 static char *save_stack_p
;
386 #define END_STRING_AND_SAVE(s) \
387 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
388 #define RESTORE_END_STRING(s) \
389 do { *(s) = *--save_stack_p; } while (0)
391 /* The instruction we're assembling. */
394 /* Possible templates for current insn. */
395 static const templates
*current_templates
;
397 /* Per instruction expressionS buffers: max displacements & immediates. */
398 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
399 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
401 /* Current operand we are working on. */
402 static int this_operand
= -1;
404 /* We support four different modes. FLAG_CODE variable is used to distinguish
412 static enum flag_code flag_code
;
413 static unsigned int object_64bit
;
414 static unsigned int disallow_64bit_reloc
;
415 static int use_rela_relocations
= 0;
417 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
418 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
419 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
421 /* The ELF ABI to use. */
429 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
432 /* 1 for intel syntax,
434 static int intel_syntax
= 0;
436 /* 1 for intel mnemonic,
437 0 if att mnemonic. */
438 static int intel_mnemonic
= !SYSV386_COMPAT
;
440 /* 1 if support old (<= 2.8.1) versions of gcc. */
441 static int old_gcc
= OLDGCC_COMPAT
;
443 /* 1 if pseudo registers are permitted. */
444 static int allow_pseudo_reg
= 0;
446 /* 1 if register prefix % not required. */
447 static int allow_naked_reg
= 0;
449 /* 1 if the assembler should add BND prefix for all control-tranferring
450 instructions supporting it, even if this prefix wasn't specified
452 static int add_bnd_prefix
= 0;
454 /* 1 if pseudo index register, eiz/riz, is allowed . */
455 static int allow_index_reg
= 0;
457 static enum check_kind
463 sse_check
, operand_check
= check_warning
;
465 /* Register prefix used for error message. */
466 static const char *register_prefix
= "%";
468 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
469 leave, push, and pop instructions so that gcc has the same stack
470 frame as in 32 bit mode. */
471 static char stackop_size
= '\0';
473 /* Non-zero to optimize code alignment. */
474 int optimize_align_code
= 1;
476 /* Non-zero to quieten some warnings. */
477 static int quiet_warnings
= 0;
480 static const char *cpu_arch_name
= NULL
;
481 static char *cpu_sub_arch_name
= NULL
;
483 /* CPU feature flags. */
484 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
486 /* If we have selected a cpu we are generating instructions for. */
487 static int cpu_arch_tune_set
= 0;
489 /* Cpu we are generating instructions for. */
490 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
492 /* CPU feature flags of cpu we are generating instructions for. */
493 static i386_cpu_flags cpu_arch_tune_flags
;
495 /* CPU instruction set architecture used. */
496 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
498 /* CPU feature flags of instruction set architecture used. */
499 i386_cpu_flags cpu_arch_isa_flags
;
501 /* If set, conditional jumps are not automatically promoted to handle
502 larger than a byte offset. */
503 static unsigned int no_cond_jump_promotion
= 0;
505 /* Encode SSE instructions with VEX prefix. */
506 static unsigned int sse2avx
;
508 /* Encode scalar AVX instructions with specific vector length. */
515 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
516 static symbolS
*GOT_symbol
;
518 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
519 unsigned int x86_dwarf2_return_column
;
521 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
522 int x86_cie_data_alignment
;
524 /* Interface to relax_segment.
525 There are 3 major relax states for 386 jump insns because the
526 different types of jumps add different sizes to frags when we're
527 figuring out what sort of jump to choose to reach a given label. */
530 #define UNCOND_JUMP 0
532 #define COND_JUMP86 2
537 #define SMALL16 (SMALL | CODE16)
539 #define BIG16 (BIG | CODE16)
543 #define INLINE __inline__
549 #define ENCODE_RELAX_STATE(type, size) \
550 ((relax_substateT) (((type) << 2) | (size)))
551 #define TYPE_FROM_RELAX_STATE(s) \
553 #define DISP_SIZE_FROM_RELAX_STATE(s) \
554 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
556 /* This table is used by relax_frag to promote short jumps to long
557 ones where necessary. SMALL (short) jumps may be promoted to BIG
558 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
559 don't allow a short jump in a 32 bit code segment to be promoted to
560 a 16 bit offset jump because it's slower (requires data size
561 prefix), and doesn't work, unless the destination is in the bottom
562 64k of the code segment (The top 16 bits of eip are zeroed). */
564 const relax_typeS md_relax_table
[] =
567 1) most positive reach of this state,
568 2) most negative reach of this state,
569 3) how many bytes this mode will have in the variable part of the frag
570 4) which index into the table to try if we can't fit into this one. */
572 /* UNCOND_JUMP states. */
573 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
574 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
575 /* dword jmp adds 4 bytes to frag:
576 0 extra opcode bytes, 4 displacement bytes. */
578 /* word jmp adds 2 byte2 to frag:
579 0 extra opcode bytes, 2 displacement bytes. */
582 /* COND_JUMP states. */
583 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
584 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
585 /* dword conditionals adds 5 bytes to frag:
586 1 extra opcode byte, 4 displacement bytes. */
588 /* word conditionals add 3 bytes to frag:
589 1 extra opcode byte, 2 displacement bytes. */
592 /* COND_JUMP86 states. */
593 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
594 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
595 /* dword conditionals adds 5 bytes to frag:
596 1 extra opcode byte, 4 displacement bytes. */
598 /* word conditionals add 4 bytes to frag:
599 1 displacement byte and a 3 byte long branch insn. */
603 static const arch_entry cpu_arch
[] =
605 /* Do not replace the first two entries - i386_target_format()
606 relies on them being there in this order. */
607 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
608 CPU_GENERIC32_FLAGS
, 0, 0 },
609 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
610 CPU_GENERIC64_FLAGS
, 0, 0 },
611 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
612 CPU_NONE_FLAGS
, 0, 0 },
613 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
614 CPU_I186_FLAGS
, 0, 0 },
615 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
616 CPU_I286_FLAGS
, 0, 0 },
617 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
618 CPU_I386_FLAGS
, 0, 0 },
619 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
620 CPU_I486_FLAGS
, 0, 0 },
621 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
622 CPU_I586_FLAGS
, 0, 0 },
623 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
624 CPU_I686_FLAGS
, 0, 0 },
625 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
626 CPU_I586_FLAGS
, 0, 0 },
627 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
628 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
629 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
630 CPU_P2_FLAGS
, 0, 0 },
631 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
632 CPU_P3_FLAGS
, 0, 0 },
633 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
634 CPU_P4_FLAGS
, 0, 0 },
635 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
636 CPU_CORE_FLAGS
, 0, 0 },
637 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
638 CPU_NOCONA_FLAGS
, 0, 0 },
639 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
640 CPU_CORE_FLAGS
, 1, 0 },
641 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
642 CPU_CORE_FLAGS
, 0, 0 },
643 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
644 CPU_CORE2_FLAGS
, 1, 0 },
645 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
646 CPU_CORE2_FLAGS
, 0, 0 },
647 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
648 CPU_COREI7_FLAGS
, 0, 0 },
649 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
650 CPU_L1OM_FLAGS
, 0, 0 },
651 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
652 CPU_K1OM_FLAGS
, 0, 0 },
653 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
654 CPU_K6_FLAGS
, 0, 0 },
655 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
656 CPU_K6_2_FLAGS
, 0, 0 },
657 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
658 CPU_ATHLON_FLAGS
, 0, 0 },
659 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
660 CPU_K8_FLAGS
, 1, 0 },
661 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
662 CPU_K8_FLAGS
, 0, 0 },
663 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
664 CPU_K8_FLAGS
, 0, 0 },
665 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
666 CPU_AMDFAM10_FLAGS
, 0, 0 },
667 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
668 CPU_BDVER1_FLAGS
, 0, 0 },
669 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
670 CPU_BDVER2_FLAGS
, 0, 0 },
671 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
672 CPU_BDVER3_FLAGS
, 0, 0 },
673 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
674 CPU_BTVER1_FLAGS
, 0, 0 },
675 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
676 CPU_BTVER2_FLAGS
, 0, 0 },
677 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
678 CPU_8087_FLAGS
, 0, 0 },
679 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
680 CPU_287_FLAGS
, 0, 0 },
681 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
682 CPU_387_FLAGS
, 0, 0 },
683 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
684 CPU_ANY87_FLAGS
, 0, 1 },
685 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
686 CPU_MMX_FLAGS
, 0, 0 },
687 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
688 CPU_3DNOWA_FLAGS
, 0, 1 },
689 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
690 CPU_SSE_FLAGS
, 0, 0 },
691 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
692 CPU_SSE2_FLAGS
, 0, 0 },
693 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
694 CPU_SSE3_FLAGS
, 0, 0 },
695 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
696 CPU_SSSE3_FLAGS
, 0, 0 },
697 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
698 CPU_SSE4_1_FLAGS
, 0, 0 },
699 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
700 CPU_SSE4_2_FLAGS
, 0, 0 },
701 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
702 CPU_SSE4_2_FLAGS
, 0, 0 },
703 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
704 CPU_ANY_SSE_FLAGS
, 0, 1 },
705 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
706 CPU_AVX_FLAGS
, 0, 0 },
707 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
708 CPU_AVX2_FLAGS
, 0, 0 },
709 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
710 CPU_ANY_AVX_FLAGS
, 0, 1 },
711 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
712 CPU_VMX_FLAGS
, 0, 0 },
713 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
714 CPU_VMFUNC_FLAGS
, 0, 0 },
715 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
716 CPU_SMX_FLAGS
, 0, 0 },
717 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
718 CPU_XSAVE_FLAGS
, 0, 0 },
719 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
720 CPU_XSAVEOPT_FLAGS
, 0, 0 },
721 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
722 CPU_AES_FLAGS
, 0, 0 },
723 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
724 CPU_PCLMUL_FLAGS
, 0, 0 },
725 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
726 CPU_PCLMUL_FLAGS
, 1, 0 },
727 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
728 CPU_FSGSBASE_FLAGS
, 0, 0 },
729 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
730 CPU_RDRND_FLAGS
, 0, 0 },
731 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
732 CPU_F16C_FLAGS
, 0, 0 },
733 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
734 CPU_BMI2_FLAGS
, 0, 0 },
735 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
736 CPU_FMA_FLAGS
, 0, 0 },
737 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
738 CPU_FMA4_FLAGS
, 0, 0 },
739 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
740 CPU_XOP_FLAGS
, 0, 0 },
741 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
742 CPU_LWP_FLAGS
, 0, 0 },
743 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
744 CPU_MOVBE_FLAGS
, 0, 0 },
745 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
746 CPU_CX16_FLAGS
, 0, 0 },
747 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
748 CPU_EPT_FLAGS
, 0, 0 },
749 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
750 CPU_LZCNT_FLAGS
, 0, 0 },
751 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
752 CPU_HLE_FLAGS
, 0, 0 },
753 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
754 CPU_RTM_FLAGS
, 0, 0 },
755 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
756 CPU_INVPCID_FLAGS
, 0, 0 },
757 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
758 CPU_CLFLUSH_FLAGS
, 0, 0 },
759 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
760 CPU_NOP_FLAGS
, 0, 0 },
761 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
762 CPU_SYSCALL_FLAGS
, 0, 0 },
763 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
764 CPU_RDTSCP_FLAGS
, 0, 0 },
765 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
766 CPU_3DNOW_FLAGS
, 0, 0 },
767 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
768 CPU_3DNOWA_FLAGS
, 0, 0 },
769 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
770 CPU_PADLOCK_FLAGS
, 0, 0 },
771 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
772 CPU_SVME_FLAGS
, 1, 0 },
773 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
774 CPU_SVME_FLAGS
, 0, 0 },
775 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
776 CPU_SSE4A_FLAGS
, 0, 0 },
777 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
778 CPU_ABM_FLAGS
, 0, 0 },
779 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
780 CPU_BMI_FLAGS
, 0, 0 },
781 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
782 CPU_TBM_FLAGS
, 0, 0 },
783 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
784 CPU_ADX_FLAGS
, 0, 0 },
785 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
786 CPU_RDSEED_FLAGS
, 0, 0 },
787 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
788 CPU_PRFCHW_FLAGS
, 0, 0 },
789 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
790 CPU_SMAP_FLAGS
, 0, 0 },
791 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
792 CPU_MPX_FLAGS
, 0, 0 },
793 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
794 CPU_SHA_FLAGS
, 0, 0 },
798 /* Like s_lcomm_internal in gas/read.c but the alignment string
799 is allowed to be optional. */
802 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
809 && *input_line_pointer
== ',')
811 align
= parse_align (needs_align
- 1);
813 if (align
== (addressT
) -1)
828 bss_alloc (symbolP
, size
, align
);
833 pe_lcomm (int needs_align
)
835 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
839 const pseudo_typeS md_pseudo_table
[] =
841 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
842 {"align", s_align_bytes
, 0},
844 {"align", s_align_ptwo
, 0},
846 {"arch", set_cpu_arch
, 0},
850 {"lcomm", pe_lcomm
, 1},
852 {"ffloat", float_cons
, 'f'},
853 {"dfloat", float_cons
, 'd'},
854 {"tfloat", float_cons
, 'x'},
856 {"slong", signed_cons
, 4},
857 {"noopt", s_ignore
, 0},
858 {"optim", s_ignore
, 0},
859 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
860 {"code16", set_code_flag
, CODE_16BIT
},
861 {"code32", set_code_flag
, CODE_32BIT
},
862 {"code64", set_code_flag
, CODE_64BIT
},
863 {"intel_syntax", set_intel_syntax
, 1},
864 {"att_syntax", set_intel_syntax
, 0},
865 {"intel_mnemonic", set_intel_mnemonic
, 1},
866 {"att_mnemonic", set_intel_mnemonic
, 0},
867 {"allow_index_reg", set_allow_index_reg
, 1},
868 {"disallow_index_reg", set_allow_index_reg
, 0},
869 {"sse_check", set_check
, 0},
870 {"operand_check", set_check
, 1},
871 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
872 {"largecomm", handle_large_common
, 0},
874 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
875 {"loc", dwarf2_directive_loc
, 0},
876 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
879 {"secrel32", pe_directive_secrel
, 0},
884 /* For interface with expression (). */
885 extern char *input_line_pointer
;
887 /* Hash table for instruction mnemonic lookup. */
888 static struct hash_control
*op_hash
;
890 /* Hash table for register lookup. */
891 static struct hash_control
*reg_hash
;
894 i386_align_code (fragS
*fragP
, int count
)
896 /* Various efficient no-op patterns for aligning code labels.
897 Note: Don't try to assemble the instructions in the comments.
898 0L and 0w are not legal. */
899 static const char f32_1
[] =
901 static const char f32_2
[] =
902 {0x66,0x90}; /* xchg %ax,%ax */
903 static const char f32_3
[] =
904 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
905 static const char f32_4
[] =
906 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
907 static const char f32_5
[] =
909 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
910 static const char f32_6
[] =
911 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
912 static const char f32_7
[] =
913 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
914 static const char f32_8
[] =
916 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
917 static const char f32_9
[] =
918 {0x89,0xf6, /* movl %esi,%esi */
919 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
920 static const char f32_10
[] =
921 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
922 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
923 static const char f32_11
[] =
924 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
925 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
926 static const char f32_12
[] =
927 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
928 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
929 static const char f32_13
[] =
930 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
931 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
932 static const char f32_14
[] =
933 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
934 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
935 static const char f16_3
[] =
936 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
937 static const char f16_4
[] =
938 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
939 static const char f16_5
[] =
941 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
942 static const char f16_6
[] =
943 {0x89,0xf6, /* mov %si,%si */
944 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
945 static const char f16_7
[] =
946 {0x8d,0x74,0x00, /* lea 0(%si),%si */
947 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
948 static const char f16_8
[] =
949 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
950 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
951 static const char jump_31
[] =
952 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
953 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
954 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
955 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
956 static const char *const f32_patt
[] = {
957 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
958 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
960 static const char *const f16_patt
[] = {
961 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
964 static const char alt_3
[] =
966 /* nopl 0(%[re]ax) */
967 static const char alt_4
[] =
968 {0x0f,0x1f,0x40,0x00};
969 /* nopl 0(%[re]ax,%[re]ax,1) */
970 static const char alt_5
[] =
971 {0x0f,0x1f,0x44,0x00,0x00};
972 /* nopw 0(%[re]ax,%[re]ax,1) */
973 static const char alt_6
[] =
974 {0x66,0x0f,0x1f,0x44,0x00,0x00};
975 /* nopl 0L(%[re]ax) */
976 static const char alt_7
[] =
977 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
978 /* nopl 0L(%[re]ax,%[re]ax,1) */
979 static const char alt_8
[] =
980 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
981 /* nopw 0L(%[re]ax,%[re]ax,1) */
982 static const char alt_9
[] =
983 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
984 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
985 static const char alt_10
[] =
986 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
988 nopw %cs:0L(%[re]ax,%[re]ax,1) */
989 static const char alt_long_11
[] =
991 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
994 nopw %cs:0L(%[re]ax,%[re]ax,1) */
995 static const char alt_long_12
[] =
998 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1002 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1003 static const char alt_long_13
[] =
1007 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1012 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1013 static const char alt_long_14
[] =
1018 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1024 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1025 static const char alt_long_15
[] =
1031 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1032 /* nopl 0(%[re]ax,%[re]ax,1)
1033 nopw 0(%[re]ax,%[re]ax,1) */
1034 static const char alt_short_11
[] =
1035 {0x0f,0x1f,0x44,0x00,0x00,
1036 0x66,0x0f,0x1f,0x44,0x00,0x00};
1037 /* nopw 0(%[re]ax,%[re]ax,1)
1038 nopw 0(%[re]ax,%[re]ax,1) */
1039 static const char alt_short_12
[] =
1040 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1041 0x66,0x0f,0x1f,0x44,0x00,0x00};
1042 /* nopw 0(%[re]ax,%[re]ax,1)
1044 static const char alt_short_13
[] =
1045 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1046 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1049 static const char alt_short_14
[] =
1050 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1051 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1053 nopl 0L(%[re]ax,%[re]ax,1) */
1054 static const char alt_short_15
[] =
1055 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1056 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1057 static const char *const alt_short_patt
[] = {
1058 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1059 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1060 alt_short_14
, alt_short_15
1062 static const char *const alt_long_patt
[] = {
1063 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1064 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1065 alt_long_14
, alt_long_15
1068 /* Only align for at least a positive non-zero boundary. */
1069 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1072 /* We need to decide which NOP sequence to use for 32bit and
1073 64bit. When -mtune= is used:
1075 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1076 PROCESSOR_GENERIC32, f32_patt will be used.
1077 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1078 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1079 PROCESSOR_GENERIC64, alt_long_patt will be used.
1080 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1081 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1084 When -mtune= isn't used, alt_long_patt will be used if
1085 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1088 When -march= or .arch is used, we can't use anything beyond
1089 cpu_arch_isa_flags. */
1091 if (flag_code
== CODE_16BIT
)
1095 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1097 /* Adjust jump offset. */
1098 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1101 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1102 f16_patt
[count
- 1], count
);
1106 const char *const *patt
= NULL
;
1108 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1110 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1111 switch (cpu_arch_tune
)
1113 case PROCESSOR_UNKNOWN
:
1114 /* We use cpu_arch_isa_flags to check if we SHOULD
1115 optimize with nops. */
1116 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1117 patt
= alt_long_patt
;
1121 case PROCESSOR_PENTIUM4
:
1122 case PROCESSOR_NOCONA
:
1123 case PROCESSOR_CORE
:
1124 case PROCESSOR_CORE2
:
1125 case PROCESSOR_COREI7
:
1126 case PROCESSOR_L1OM
:
1127 case PROCESSOR_K1OM
:
1128 case PROCESSOR_GENERIC64
:
1129 patt
= alt_long_patt
;
1132 case PROCESSOR_ATHLON
:
1134 case PROCESSOR_AMDFAM10
:
1137 patt
= alt_short_patt
;
1139 case PROCESSOR_I386
:
1140 case PROCESSOR_I486
:
1141 case PROCESSOR_PENTIUM
:
1142 case PROCESSOR_PENTIUMPRO
:
1143 case PROCESSOR_GENERIC32
:
1150 switch (fragP
->tc_frag_data
.tune
)
1152 case PROCESSOR_UNKNOWN
:
1153 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1154 PROCESSOR_UNKNOWN. */
1158 case PROCESSOR_I386
:
1159 case PROCESSOR_I486
:
1160 case PROCESSOR_PENTIUM
:
1162 case PROCESSOR_ATHLON
:
1164 case PROCESSOR_AMDFAM10
:
1167 case PROCESSOR_GENERIC32
:
1168 /* We use cpu_arch_isa_flags to check if we CAN optimize
1170 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1171 patt
= alt_short_patt
;
1175 case PROCESSOR_PENTIUMPRO
:
1176 case PROCESSOR_PENTIUM4
:
1177 case PROCESSOR_NOCONA
:
1178 case PROCESSOR_CORE
:
1179 case PROCESSOR_CORE2
:
1180 case PROCESSOR_COREI7
:
1181 case PROCESSOR_L1OM
:
1182 case PROCESSOR_K1OM
:
1183 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1184 patt
= alt_long_patt
;
1188 case PROCESSOR_GENERIC64
:
1189 patt
= alt_long_patt
;
1194 if (patt
== f32_patt
)
1196 /* If the padding is less than 15 bytes, we use the normal
1197 ones. Otherwise, we use a jump instruction and adjust
1201 /* For 64bit, the limit is 3 bytes. */
1202 if (flag_code
== CODE_64BIT
1203 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1208 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1209 patt
[count
- 1], count
);
1212 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1214 /* Adjust jump offset. */
1215 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1220 /* Maximum length of an instruction is 15 byte. If the
1221 padding is greater than 15 bytes and we don't use jump,
1222 we have to break it into smaller pieces. */
1223 int padding
= count
;
1224 while (padding
> 15)
1227 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1232 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1233 patt
[padding
- 1], padding
);
1236 fragP
->fr_var
= count
;
1240 operand_type_all_zero (const union i386_operand_type
*x
)
1242 switch (ARRAY_SIZE(x
->array
))
1251 return !x
->array
[0];
1258 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1260 switch (ARRAY_SIZE(x
->array
))
1275 operand_type_equal (const union i386_operand_type
*x
,
1276 const union i386_operand_type
*y
)
1278 switch (ARRAY_SIZE(x
->array
))
1281 if (x
->array
[2] != y
->array
[2])
1284 if (x
->array
[1] != y
->array
[1])
1287 return x
->array
[0] == y
->array
[0];
1295 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1297 switch (ARRAY_SIZE(x
->array
))
1306 return !x
->array
[0];
1313 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1315 switch (ARRAY_SIZE(x
->array
))
1330 cpu_flags_equal (const union i386_cpu_flags
*x
,
1331 const union i386_cpu_flags
*y
)
1333 switch (ARRAY_SIZE(x
->array
))
1336 if (x
->array
[2] != y
->array
[2])
1339 if (x
->array
[1] != y
->array
[1])
1342 return x
->array
[0] == y
->array
[0];
1350 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1352 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1353 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1356 static INLINE i386_cpu_flags
1357 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1359 switch (ARRAY_SIZE (x
.array
))
1362 x
.array
[2] &= y
.array
[2];
1364 x
.array
[1] &= y
.array
[1];
1366 x
.array
[0] &= y
.array
[0];
1374 static INLINE i386_cpu_flags
1375 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1377 switch (ARRAY_SIZE (x
.array
))
1380 x
.array
[2] |= y
.array
[2];
1382 x
.array
[1] |= y
.array
[1];
1384 x
.array
[0] |= y
.array
[0];
1392 static INLINE i386_cpu_flags
1393 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1395 switch (ARRAY_SIZE (x
.array
))
1398 x
.array
[2] &= ~y
.array
[2];
1400 x
.array
[1] &= ~y
.array
[1];
1402 x
.array
[0] &= ~y
.array
[0];
1410 #define CPU_FLAGS_ARCH_MATCH 0x1
1411 #define CPU_FLAGS_64BIT_MATCH 0x2
1412 #define CPU_FLAGS_AES_MATCH 0x4
1413 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1414 #define CPU_FLAGS_AVX_MATCH 0x10
1416 #define CPU_FLAGS_32BIT_MATCH \
1417 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1418 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1419 #define CPU_FLAGS_PERFECT_MATCH \
1420 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1422 /* Return CPU flags match bits. */
1425 cpu_flags_match (const insn_template
*t
)
1427 i386_cpu_flags x
= t
->cpu_flags
;
1428 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1430 x
.bitfield
.cpu64
= 0;
1431 x
.bitfield
.cpuno64
= 0;
1433 if (cpu_flags_all_zero (&x
))
1435 /* This instruction is available on all archs. */
1436 match
|= CPU_FLAGS_32BIT_MATCH
;
1440 /* This instruction is available only on some archs. */
1441 i386_cpu_flags cpu
= cpu_arch_flags
;
1443 cpu
.bitfield
.cpu64
= 0;
1444 cpu
.bitfield
.cpuno64
= 0;
1445 cpu
= cpu_flags_and (x
, cpu
);
1446 if (!cpu_flags_all_zero (&cpu
))
1448 if (x
.bitfield
.cpuavx
)
1450 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1451 if (cpu
.bitfield
.cpuavx
)
1453 /* Check SSE2AVX. */
1454 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1456 match
|= (CPU_FLAGS_ARCH_MATCH
1457 | CPU_FLAGS_AVX_MATCH
);
1459 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1460 match
|= CPU_FLAGS_AES_MATCH
;
1462 if (!x
.bitfield
.cpupclmul
1463 || cpu
.bitfield
.cpupclmul
)
1464 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1468 match
|= CPU_FLAGS_ARCH_MATCH
;
1471 match
|= CPU_FLAGS_32BIT_MATCH
;
1477 static INLINE i386_operand_type
1478 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1480 switch (ARRAY_SIZE (x
.array
))
1483 x
.array
[2] &= y
.array
[2];
1485 x
.array
[1] &= y
.array
[1];
1487 x
.array
[0] &= y
.array
[0];
1495 static INLINE i386_operand_type
1496 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1498 switch (ARRAY_SIZE (x
.array
))
1501 x
.array
[2] |= y
.array
[2];
1503 x
.array
[1] |= y
.array
[1];
1505 x
.array
[0] |= y
.array
[0];
1513 static INLINE i386_operand_type
1514 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1516 switch (ARRAY_SIZE (x
.array
))
1519 x
.array
[2] ^= y
.array
[2];
1521 x
.array
[1] ^= y
.array
[1];
1523 x
.array
[0] ^= y
.array
[0];
1531 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1532 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1533 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1534 static const i386_operand_type inoutportreg
1535 = OPERAND_TYPE_INOUTPORTREG
;
1536 static const i386_operand_type reg16_inoutportreg
1537 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1538 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1539 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1540 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1541 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1542 static const i386_operand_type anydisp
1543 = OPERAND_TYPE_ANYDISP
;
1544 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1545 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1546 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1547 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1548 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1549 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1550 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1551 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1552 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1553 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1554 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1555 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1556 static const i386_operand_type regbnd
= OPERAND_TYPE_REGBND
;
1567 operand_type_check (i386_operand_type t
, enum operand_type c
)
1572 return (t
.bitfield
.reg8
1575 || t
.bitfield
.reg64
);
1578 return (t
.bitfield
.imm8
1582 || t
.bitfield
.imm32s
1583 || t
.bitfield
.imm64
);
1586 return (t
.bitfield
.disp8
1587 || t
.bitfield
.disp16
1588 || t
.bitfield
.disp32
1589 || t
.bitfield
.disp32s
1590 || t
.bitfield
.disp64
);
1593 return (t
.bitfield
.disp8
1594 || t
.bitfield
.disp16
1595 || t
.bitfield
.disp32
1596 || t
.bitfield
.disp32s
1597 || t
.bitfield
.disp64
1598 || t
.bitfield
.baseindex
);
1607 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1608 operand J for instruction template T. */
1611 match_reg_size (const insn_template
*t
, unsigned int j
)
1613 return !((i
.types
[j
].bitfield
.byte
1614 && !t
->operand_types
[j
].bitfield
.byte
)
1615 || (i
.types
[j
].bitfield
.word
1616 && !t
->operand_types
[j
].bitfield
.word
)
1617 || (i
.types
[j
].bitfield
.dword
1618 && !t
->operand_types
[j
].bitfield
.dword
)
1619 || (i
.types
[j
].bitfield
.qword
1620 && !t
->operand_types
[j
].bitfield
.qword
));
1623 /* Return 1 if there is no conflict in any size on operand J for
1624 instruction template T. */
1627 match_mem_size (const insn_template
*t
, unsigned int j
)
1629 return (match_reg_size (t
, j
)
1630 && !((i
.types
[j
].bitfield
.unspecified
1631 && !t
->operand_types
[j
].bitfield
.unspecified
)
1632 || (i
.types
[j
].bitfield
.fword
1633 && !t
->operand_types
[j
].bitfield
.fword
)
1634 || (i
.types
[j
].bitfield
.tbyte
1635 && !t
->operand_types
[j
].bitfield
.tbyte
)
1636 || (i
.types
[j
].bitfield
.xmmword
1637 && !t
->operand_types
[j
].bitfield
.xmmword
)
1638 || (i
.types
[j
].bitfield
.ymmword
1639 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1642 /* Return 1 if there is no size conflict on any operands for
1643 instruction template T. */
1646 operand_size_match (const insn_template
*t
)
1651 /* Don't check jump instructions. */
1652 if (t
->opcode_modifier
.jump
1653 || t
->opcode_modifier
.jumpbyte
1654 || t
->opcode_modifier
.jumpdword
1655 || t
->opcode_modifier
.jumpintersegment
)
1658 /* Check memory and accumulator operand size. */
1659 for (j
= 0; j
< i
.operands
; j
++)
1661 if (t
->operand_types
[j
].bitfield
.anysize
)
1664 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1670 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1679 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1682 i
.error
= operand_size_mismatch
;
1686 /* Check reverse. */
1687 gas_assert (i
.operands
== 2);
1690 for (j
= 0; j
< 2; j
++)
1692 if (t
->operand_types
[j
].bitfield
.acc
1693 && !match_reg_size (t
, j
? 0 : 1))
1696 if (i
.types
[j
].bitfield
.mem
1697 && !match_mem_size (t
, j
? 0 : 1))
1705 operand_type_match (i386_operand_type overlap
,
1706 i386_operand_type given
)
1708 i386_operand_type temp
= overlap
;
1710 temp
.bitfield
.jumpabsolute
= 0;
1711 temp
.bitfield
.unspecified
= 0;
1712 temp
.bitfield
.byte
= 0;
1713 temp
.bitfield
.word
= 0;
1714 temp
.bitfield
.dword
= 0;
1715 temp
.bitfield
.fword
= 0;
1716 temp
.bitfield
.qword
= 0;
1717 temp
.bitfield
.tbyte
= 0;
1718 temp
.bitfield
.xmmword
= 0;
1719 temp
.bitfield
.ymmword
= 0;
1720 if (operand_type_all_zero (&temp
))
1723 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1724 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1728 i
.error
= operand_type_mismatch
;
1732 /* If given types g0 and g1 are registers they must be of the same type
1733 unless the expected operand type register overlap is null.
1734 Note that Acc in a template matches every size of reg. */
1737 operand_type_register_match (i386_operand_type m0
,
1738 i386_operand_type g0
,
1739 i386_operand_type t0
,
1740 i386_operand_type m1
,
1741 i386_operand_type g1
,
1742 i386_operand_type t1
)
1744 if (!operand_type_check (g0
, reg
))
1747 if (!operand_type_check (g1
, reg
))
1750 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1751 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1752 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1753 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1756 if (m0
.bitfield
.acc
)
1758 t0
.bitfield
.reg8
= 1;
1759 t0
.bitfield
.reg16
= 1;
1760 t0
.bitfield
.reg32
= 1;
1761 t0
.bitfield
.reg64
= 1;
1764 if (m1
.bitfield
.acc
)
1766 t1
.bitfield
.reg8
= 1;
1767 t1
.bitfield
.reg16
= 1;
1768 t1
.bitfield
.reg32
= 1;
1769 t1
.bitfield
.reg64
= 1;
1772 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1773 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1774 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1775 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1778 i
.error
= register_type_mismatch
;
1783 static INLINE
unsigned int
1784 register_number (const reg_entry
*r
)
1786 unsigned int nr
= r
->reg_num
;
1788 if (r
->reg_flags
& RegRex
)
1794 static INLINE
unsigned int
1795 mode_from_disp_size (i386_operand_type t
)
1797 if (t
.bitfield
.disp8
)
1799 else if (t
.bitfield
.disp16
1800 || t
.bitfield
.disp32
1801 || t
.bitfield
.disp32s
)
1808 fits_in_signed_byte (offsetT num
)
1810 return (num
>= -128) && (num
<= 127);
1814 fits_in_unsigned_byte (offsetT num
)
1816 return (num
& 0xff) == num
;
1820 fits_in_unsigned_word (offsetT num
)
1822 return (num
& 0xffff) == num
;
1826 fits_in_signed_word (offsetT num
)
1828 return (-32768 <= num
) && (num
<= 32767);
1832 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1837 return (!(((offsetT
) -1 << 31) & num
)
1838 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1840 } /* fits_in_signed_long() */
1843 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1848 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1850 } /* fits_in_unsigned_long() */
1853 fits_in_imm4 (offsetT num
)
1855 return (num
& 0xf) == num
;
1858 static i386_operand_type
1859 smallest_imm_type (offsetT num
)
1861 i386_operand_type t
;
1863 operand_type_set (&t
, 0);
1864 t
.bitfield
.imm64
= 1;
1866 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1868 /* This code is disabled on the 486 because all the Imm1 forms
1869 in the opcode table are slower on the i486. They're the
1870 versions with the implicitly specified single-position
1871 displacement, which has another syntax if you really want to
1873 t
.bitfield
.imm1
= 1;
1874 t
.bitfield
.imm8
= 1;
1875 t
.bitfield
.imm8s
= 1;
1876 t
.bitfield
.imm16
= 1;
1877 t
.bitfield
.imm32
= 1;
1878 t
.bitfield
.imm32s
= 1;
1880 else if (fits_in_signed_byte (num
))
1882 t
.bitfield
.imm8
= 1;
1883 t
.bitfield
.imm8s
= 1;
1884 t
.bitfield
.imm16
= 1;
1885 t
.bitfield
.imm32
= 1;
1886 t
.bitfield
.imm32s
= 1;
1888 else if (fits_in_unsigned_byte (num
))
1890 t
.bitfield
.imm8
= 1;
1891 t
.bitfield
.imm16
= 1;
1892 t
.bitfield
.imm32
= 1;
1893 t
.bitfield
.imm32s
= 1;
1895 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1897 t
.bitfield
.imm16
= 1;
1898 t
.bitfield
.imm32
= 1;
1899 t
.bitfield
.imm32s
= 1;
1901 else if (fits_in_signed_long (num
))
1903 t
.bitfield
.imm32
= 1;
1904 t
.bitfield
.imm32s
= 1;
1906 else if (fits_in_unsigned_long (num
))
1907 t
.bitfield
.imm32
= 1;
1913 offset_in_range (offsetT val
, int size
)
1919 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1920 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1921 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1923 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1929 /* If BFD64, sign extend val for 32bit address mode. */
1930 if (flag_code
!= CODE_64BIT
1931 || i
.prefix
[ADDR_PREFIX
])
1932 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1933 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1936 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1938 char buf1
[40], buf2
[40];
1940 sprint_value (buf1
, val
);
1941 sprint_value (buf2
, val
& mask
);
1942 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1956 a. PREFIX_EXIST if attempting to add a prefix where one from the
1957 same class already exists.
1958 b. PREFIX_LOCK if lock prefix is added.
1959 c. PREFIX_REP if rep/repne prefix is added.
1960 d. PREFIX_OTHER if other prefix is added.
1963 static enum PREFIX_GROUP
1964 add_prefix (unsigned int prefix
)
1966 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
1969 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1970 && flag_code
== CODE_64BIT
)
1972 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1973 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1974 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1985 case CS_PREFIX_OPCODE
:
1986 case DS_PREFIX_OPCODE
:
1987 case ES_PREFIX_OPCODE
:
1988 case FS_PREFIX_OPCODE
:
1989 case GS_PREFIX_OPCODE
:
1990 case SS_PREFIX_OPCODE
:
1994 case REPNE_PREFIX_OPCODE
:
1995 case REPE_PREFIX_OPCODE
:
2000 case LOCK_PREFIX_OPCODE
:
2009 case ADDR_PREFIX_OPCODE
:
2013 case DATA_PREFIX_OPCODE
:
2017 if (i
.prefix
[q
] != 0)
2025 i
.prefix
[q
] |= prefix
;
2028 as_bad (_("same type of prefix used twice"));
2034 update_code_flag (int value
, int check
)
2036 PRINTF_LIKE ((*as_error
));
2038 flag_code
= (enum flag_code
) value
;
2039 if (flag_code
== CODE_64BIT
)
2041 cpu_arch_flags
.bitfield
.cpu64
= 1;
2042 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2046 cpu_arch_flags
.bitfield
.cpu64
= 0;
2047 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2049 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2052 as_error
= as_fatal
;
2055 (*as_error
) (_("64bit mode not supported on `%s'."),
2056 cpu_arch_name
? cpu_arch_name
: default_arch
);
2058 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2061 as_error
= as_fatal
;
2064 (*as_error
) (_("32bit mode not supported on `%s'."),
2065 cpu_arch_name
? cpu_arch_name
: default_arch
);
2067 stackop_size
= '\0';
2071 set_code_flag (int value
)
2073 update_code_flag (value
, 0);
2077 set_16bit_gcc_code_flag (int new_code_flag
)
2079 flag_code
= (enum flag_code
) new_code_flag
;
2080 if (flag_code
!= CODE_16BIT
)
2082 cpu_arch_flags
.bitfield
.cpu64
= 0;
2083 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2084 stackop_size
= LONG_MNEM_SUFFIX
;
2088 set_intel_syntax (int syntax_flag
)
2090 /* Find out if register prefixing is specified. */
2091 int ask_naked_reg
= 0;
2094 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2096 char *string
= input_line_pointer
;
2097 int e
= get_symbol_end ();
2099 if (strcmp (string
, "prefix") == 0)
2101 else if (strcmp (string
, "noprefix") == 0)
2104 as_bad (_("bad argument to syntax directive."));
2105 *input_line_pointer
= e
;
2107 demand_empty_rest_of_line ();
2109 intel_syntax
= syntax_flag
;
2111 if (ask_naked_reg
== 0)
2112 allow_naked_reg
= (intel_syntax
2113 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2115 allow_naked_reg
= (ask_naked_reg
< 0);
2117 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2119 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2120 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2121 register_prefix
= allow_naked_reg
? "" : "%";
2125 set_intel_mnemonic (int mnemonic_flag
)
2127 intel_mnemonic
= mnemonic_flag
;
2131 set_allow_index_reg (int flag
)
2133 allow_index_reg
= flag
;
2137 set_check (int what
)
2139 enum check_kind
*kind
;
2144 kind
= &operand_check
;
2155 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2157 char *string
= input_line_pointer
;
2158 int e
= get_symbol_end ();
2160 if (strcmp (string
, "none") == 0)
2162 else if (strcmp (string
, "warning") == 0)
2163 *kind
= check_warning
;
2164 else if (strcmp (string
, "error") == 0)
2165 *kind
= check_error
;
2167 as_bad (_("bad argument to %s_check directive."), str
);
2168 *input_line_pointer
= e
;
2171 as_bad (_("missing argument for %s_check directive"), str
);
2173 demand_empty_rest_of_line ();
2177 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2178 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2180 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2181 static const char *arch
;
2183 /* Intel LIOM is only supported on ELF. */
2189 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2190 use default_arch. */
2191 arch
= cpu_arch_name
;
2193 arch
= default_arch
;
2196 /* If we are targeting Intel L1OM, we must enable it. */
2197 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2198 || new_flag
.bitfield
.cpul1om
)
2201 /* If we are targeting Intel K1OM, we must enable it. */
2202 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2203 || new_flag
.bitfield
.cpuk1om
)
2206 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2211 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2215 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2217 char *string
= input_line_pointer
;
2218 int e
= get_symbol_end ();
2220 i386_cpu_flags flags
;
2222 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2224 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2226 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2230 cpu_arch_name
= cpu_arch
[j
].name
;
2231 cpu_sub_arch_name
= NULL
;
2232 cpu_arch_flags
= cpu_arch
[j
].flags
;
2233 if (flag_code
== CODE_64BIT
)
2235 cpu_arch_flags
.bitfield
.cpu64
= 1;
2236 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2240 cpu_arch_flags
.bitfield
.cpu64
= 0;
2241 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2243 cpu_arch_isa
= cpu_arch
[j
].type
;
2244 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2245 if (!cpu_arch_tune_set
)
2247 cpu_arch_tune
= cpu_arch_isa
;
2248 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2253 if (!cpu_arch
[j
].negated
)
2254 flags
= cpu_flags_or (cpu_arch_flags
,
2257 flags
= cpu_flags_and_not (cpu_arch_flags
,
2259 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2261 if (cpu_sub_arch_name
)
2263 char *name
= cpu_sub_arch_name
;
2264 cpu_sub_arch_name
= concat (name
,
2266 (const char *) NULL
);
2270 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2271 cpu_arch_flags
= flags
;
2272 cpu_arch_isa_flags
= flags
;
2274 *input_line_pointer
= e
;
2275 demand_empty_rest_of_line ();
2279 if (j
>= ARRAY_SIZE (cpu_arch
))
2280 as_bad (_("no such architecture: `%s'"), string
);
2282 *input_line_pointer
= e
;
2285 as_bad (_("missing cpu architecture"));
2287 no_cond_jump_promotion
= 0;
2288 if (*input_line_pointer
== ','
2289 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2291 char *string
= ++input_line_pointer
;
2292 int e
= get_symbol_end ();
2294 if (strcmp (string
, "nojumps") == 0)
2295 no_cond_jump_promotion
= 1;
2296 else if (strcmp (string
, "jumps") == 0)
2299 as_bad (_("no such architecture modifier: `%s'"), string
);
2301 *input_line_pointer
= e
;
2304 demand_empty_rest_of_line ();
2307 enum bfd_architecture
2310 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2312 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2313 || flag_code
!= CODE_64BIT
)
2314 as_fatal (_("Intel L1OM is 64bit ELF only"));
2315 return bfd_arch_l1om
;
2317 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2319 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2320 || flag_code
!= CODE_64BIT
)
2321 as_fatal (_("Intel K1OM is 64bit ELF only"));
2322 return bfd_arch_k1om
;
2325 return bfd_arch_i386
;
2331 if (!strncmp (default_arch
, "x86_64", 6))
2333 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2335 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2336 || default_arch
[6] != '\0')
2337 as_fatal (_("Intel L1OM is 64bit ELF only"));
2338 return bfd_mach_l1om
;
2340 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2342 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2343 || default_arch
[6] != '\0')
2344 as_fatal (_("Intel K1OM is 64bit ELF only"));
2345 return bfd_mach_k1om
;
2347 else if (default_arch
[6] == '\0')
2348 return bfd_mach_x86_64
;
2350 return bfd_mach_x64_32
;
2352 else if (!strcmp (default_arch
, "i386"))
2353 return bfd_mach_i386_i386
;
2355 as_fatal (_("unknown architecture"));
2361 const char *hash_err
;
2363 /* Initialize op_hash hash table. */
2364 op_hash
= hash_new ();
2367 const insn_template
*optab
;
2368 templates
*core_optab
;
2370 /* Setup for loop. */
2372 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2373 core_optab
->start
= optab
;
2378 if (optab
->name
== NULL
2379 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2381 /* different name --> ship out current template list;
2382 add to hash table; & begin anew. */
2383 core_optab
->end
= optab
;
2384 hash_err
= hash_insert (op_hash
,
2386 (void *) core_optab
);
2389 as_fatal (_("can't hash %s: %s"),
2393 if (optab
->name
== NULL
)
2395 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2396 core_optab
->start
= optab
;
2401 /* Initialize reg_hash hash table. */
2402 reg_hash
= hash_new ();
2404 const reg_entry
*regtab
;
2405 unsigned int regtab_size
= i386_regtab_size
;
2407 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2409 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2411 as_fatal (_("can't hash %s: %s"),
2417 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2422 for (c
= 0; c
< 256; c
++)
2427 mnemonic_chars
[c
] = c
;
2428 register_chars
[c
] = c
;
2429 operand_chars
[c
] = c
;
2431 else if (ISLOWER (c
))
2433 mnemonic_chars
[c
] = c
;
2434 register_chars
[c
] = c
;
2435 operand_chars
[c
] = c
;
2437 else if (ISUPPER (c
))
2439 mnemonic_chars
[c
] = TOLOWER (c
);
2440 register_chars
[c
] = mnemonic_chars
[c
];
2441 operand_chars
[c
] = c
;
2444 if (ISALPHA (c
) || ISDIGIT (c
))
2445 identifier_chars
[c
] = c
;
2448 identifier_chars
[c
] = c
;
2449 operand_chars
[c
] = c
;
2454 identifier_chars
['@'] = '@';
2457 identifier_chars
['?'] = '?';
2458 operand_chars
['?'] = '?';
2460 digit_chars
['-'] = '-';
2461 mnemonic_chars
['_'] = '_';
2462 mnemonic_chars
['-'] = '-';
2463 mnemonic_chars
['.'] = '.';
2464 identifier_chars
['_'] = '_';
2465 identifier_chars
['.'] = '.';
2467 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2468 operand_chars
[(unsigned char) *p
] = *p
;
2471 if (flag_code
== CODE_64BIT
)
2473 #if defined (OBJ_COFF) && defined (TE_PE)
2474 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2477 x86_dwarf2_return_column
= 16;
2479 x86_cie_data_alignment
= -8;
2483 x86_dwarf2_return_column
= 8;
2484 x86_cie_data_alignment
= -4;
2489 i386_print_statistics (FILE *file
)
2491 hash_print_statistics (file
, "i386 opcode", op_hash
);
2492 hash_print_statistics (file
, "i386 register", reg_hash
);
2497 /* Debugging routines for md_assemble. */
2498 static void pte (insn_template
*);
2499 static void pt (i386_operand_type
);
2500 static void pe (expressionS
*);
2501 static void ps (symbolS
*);
2504 pi (char *line
, i386_insn
*x
)
2508 fprintf (stdout
, "%s: template ", line
);
2510 fprintf (stdout
, " address: base %s index %s scale %x\n",
2511 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2512 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2513 x
->log2_scale_factor
);
2514 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2515 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2516 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2517 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2518 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2519 (x
->rex
& REX_W
) != 0,
2520 (x
->rex
& REX_R
) != 0,
2521 (x
->rex
& REX_X
) != 0,
2522 (x
->rex
& REX_B
) != 0);
2523 for (j
= 0; j
< x
->operands
; j
++)
2525 fprintf (stdout
, " #%d: ", j
+ 1);
2527 fprintf (stdout
, "\n");
2528 if (x
->types
[j
].bitfield
.reg8
2529 || x
->types
[j
].bitfield
.reg16
2530 || x
->types
[j
].bitfield
.reg32
2531 || x
->types
[j
].bitfield
.reg64
2532 || x
->types
[j
].bitfield
.regmmx
2533 || x
->types
[j
].bitfield
.regxmm
2534 || x
->types
[j
].bitfield
.regymm
2535 || x
->types
[j
].bitfield
.sreg2
2536 || x
->types
[j
].bitfield
.sreg3
2537 || x
->types
[j
].bitfield
.control
2538 || x
->types
[j
].bitfield
.debug
2539 || x
->types
[j
].bitfield
.test
)
2540 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2541 if (operand_type_check (x
->types
[j
], imm
))
2543 if (operand_type_check (x
->types
[j
], disp
))
2544 pe (x
->op
[j
].disps
);
2549 pte (insn_template
*t
)
2552 fprintf (stdout
, " %d operands ", t
->operands
);
2553 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2554 if (t
->extension_opcode
!= None
)
2555 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2556 if (t
->opcode_modifier
.d
)
2557 fprintf (stdout
, "D");
2558 if (t
->opcode_modifier
.w
)
2559 fprintf (stdout
, "W");
2560 fprintf (stdout
, "\n");
2561 for (j
= 0; j
< t
->operands
; j
++)
2563 fprintf (stdout
, " #%d type ", j
+ 1);
2564 pt (t
->operand_types
[j
]);
2565 fprintf (stdout
, "\n");
2572 fprintf (stdout
, " operation %d\n", e
->X_op
);
2573 fprintf (stdout
, " add_number %ld (%lx)\n",
2574 (long) e
->X_add_number
, (long) e
->X_add_number
);
2575 if (e
->X_add_symbol
)
2577 fprintf (stdout
, " add_symbol ");
2578 ps (e
->X_add_symbol
);
2579 fprintf (stdout
, "\n");
2583 fprintf (stdout
, " op_symbol ");
2584 ps (e
->X_op_symbol
);
2585 fprintf (stdout
, "\n");
2592 fprintf (stdout
, "%s type %s%s",
2594 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2595 segment_name (S_GET_SEGMENT (s
)));
2598 static struct type_name
2600 i386_operand_type mask
;
2603 const type_names
[] =
2605 { OPERAND_TYPE_REG8
, "r8" },
2606 { OPERAND_TYPE_REG16
, "r16" },
2607 { OPERAND_TYPE_REG32
, "r32" },
2608 { OPERAND_TYPE_REG64
, "r64" },
2609 { OPERAND_TYPE_IMM8
, "i8" },
2610 { OPERAND_TYPE_IMM8
, "i8s" },
2611 { OPERAND_TYPE_IMM16
, "i16" },
2612 { OPERAND_TYPE_IMM32
, "i32" },
2613 { OPERAND_TYPE_IMM32S
, "i32s" },
2614 { OPERAND_TYPE_IMM64
, "i64" },
2615 { OPERAND_TYPE_IMM1
, "i1" },
2616 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2617 { OPERAND_TYPE_DISP8
, "d8" },
2618 { OPERAND_TYPE_DISP16
, "d16" },
2619 { OPERAND_TYPE_DISP32
, "d32" },
2620 { OPERAND_TYPE_DISP32S
, "d32s" },
2621 { OPERAND_TYPE_DISP64
, "d64" },
2622 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2623 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2624 { OPERAND_TYPE_CONTROL
, "control reg" },
2625 { OPERAND_TYPE_TEST
, "test reg" },
2626 { OPERAND_TYPE_DEBUG
, "debug reg" },
2627 { OPERAND_TYPE_FLOATREG
, "FReg" },
2628 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2629 { OPERAND_TYPE_SREG2
, "SReg2" },
2630 { OPERAND_TYPE_SREG3
, "SReg3" },
2631 { OPERAND_TYPE_ACC
, "Acc" },
2632 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2633 { OPERAND_TYPE_REGMMX
, "rMMX" },
2634 { OPERAND_TYPE_REGXMM
, "rXMM" },
2635 { OPERAND_TYPE_REGYMM
, "rYMM" },
2636 { OPERAND_TYPE_ESSEG
, "es" },
2640 pt (i386_operand_type t
)
2643 i386_operand_type a
;
2645 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2647 a
= operand_type_and (t
, type_names
[j
].mask
);
2648 if (!operand_type_all_zero (&a
))
2649 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2654 #endif /* DEBUG386 */
2656 static bfd_reloc_code_real_type
2657 reloc (unsigned int size
,
2660 bfd_reloc_code_real_type other
)
2662 if (other
!= NO_RELOC
)
2664 reloc_howto_type
*rel
;
2669 case BFD_RELOC_X86_64_GOT32
:
2670 return BFD_RELOC_X86_64_GOT64
;
2672 case BFD_RELOC_X86_64_PLTOFF64
:
2673 return BFD_RELOC_X86_64_PLTOFF64
;
2675 case BFD_RELOC_X86_64_GOTPC32
:
2676 other
= BFD_RELOC_X86_64_GOTPC64
;
2678 case BFD_RELOC_X86_64_GOTPCREL
:
2679 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2681 case BFD_RELOC_X86_64_TPOFF32
:
2682 other
= BFD_RELOC_X86_64_TPOFF64
;
2684 case BFD_RELOC_X86_64_DTPOFF32
:
2685 other
= BFD_RELOC_X86_64_DTPOFF64
;
2691 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2692 if (other
== BFD_RELOC_SIZE32
)
2695 return BFD_RELOC_SIZE64
;
2697 as_bad (_("there are no pc-relative size relocations"));
2701 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2702 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2705 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2707 as_bad (_("unknown relocation (%u)"), other
);
2708 else if (size
!= bfd_get_reloc_size (rel
))
2709 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2710 bfd_get_reloc_size (rel
),
2712 else if (pcrel
&& !rel
->pc_relative
)
2713 as_bad (_("non-pc-relative relocation for pc-relative field"));
2714 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2716 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2718 as_bad (_("relocated field and relocation type differ in signedness"));
2727 as_bad (_("there are no unsigned pc-relative relocations"));
2730 case 1: return BFD_RELOC_8_PCREL
;
2731 case 2: return BFD_RELOC_16_PCREL
;
2732 case 4: return BFD_RELOC_32_PCREL
;
2733 case 8: return BFD_RELOC_64_PCREL
;
2735 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2742 case 4: return BFD_RELOC_X86_64_32S
;
2747 case 1: return BFD_RELOC_8
;
2748 case 2: return BFD_RELOC_16
;
2749 case 4: return BFD_RELOC_32
;
2750 case 8: return BFD_RELOC_64
;
2752 as_bad (_("cannot do %s %u byte relocation"),
2753 sign
> 0 ? "signed" : "unsigned", size
);
2759 /* Here we decide which fixups can be adjusted to make them relative to
2760 the beginning of the section instead of the symbol. Basically we need
2761 to make sure that the dynamic relocations are done correctly, so in
2762 some cases we force the original symbol to be used. */
2765 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2767 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2771 /* Don't adjust pc-relative references to merge sections in 64-bit
2773 if (use_rela_relocations
2774 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2778 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2779 and changed later by validate_fix. */
2780 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2781 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2784 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2785 for size relocations. */
2786 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2787 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2788 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2789 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2790 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2791 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2792 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2793 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2794 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2795 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2796 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2797 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2798 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2799 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2800 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2801 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2802 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2803 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2804 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2805 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2806 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2807 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2808 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2809 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2810 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2811 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2812 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2813 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2814 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2815 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2822 intel_float_operand (const char *mnemonic
)
2824 /* Note that the value returned is meaningful only for opcodes with (memory)
2825 operands, hence the code here is free to improperly handle opcodes that
2826 have no operands (for better performance and smaller code). */
2828 if (mnemonic
[0] != 'f')
2829 return 0; /* non-math */
2831 switch (mnemonic
[1])
2833 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2834 the fs segment override prefix not currently handled because no
2835 call path can make opcodes without operands get here */
2837 return 2 /* integer op */;
2839 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2840 return 3; /* fldcw/fldenv */
2843 if (mnemonic
[2] != 'o' /* fnop */)
2844 return 3; /* non-waiting control op */
2847 if (mnemonic
[2] == 's')
2848 return 3; /* frstor/frstpm */
2851 if (mnemonic
[2] == 'a')
2852 return 3; /* fsave */
2853 if (mnemonic
[2] == 't')
2855 switch (mnemonic
[3])
2857 case 'c': /* fstcw */
2858 case 'd': /* fstdw */
2859 case 'e': /* fstenv */
2860 case 's': /* fsts[gw] */
2866 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2867 return 0; /* fxsave/fxrstor are not really math ops */
2874 /* Build the VEX prefix. */
2877 build_vex_prefix (const insn_template
*t
)
2879 unsigned int register_specifier
;
2880 unsigned int implied_prefix
;
2881 unsigned int vector_length
;
2883 /* Check register specifier. */
2884 if (i
.vex
.register_specifier
)
2885 register_specifier
= ~register_number (i
.vex
.register_specifier
) & 0xf;
2887 register_specifier
= 0xf;
2889 /* Use 2-byte VEX prefix by swappping destination and source
2892 && i
.operands
== i
.reg_operands
2893 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2894 && i
.tm
.opcode_modifier
.s
2897 unsigned int xchg
= i
.operands
- 1;
2898 union i386_op temp_op
;
2899 i386_operand_type temp_type
;
2901 temp_type
= i
.types
[xchg
];
2902 i
.types
[xchg
] = i
.types
[0];
2903 i
.types
[0] = temp_type
;
2904 temp_op
= i
.op
[xchg
];
2905 i
.op
[xchg
] = i
.op
[0];
2908 gas_assert (i
.rm
.mode
== 3);
2912 i
.rm
.regmem
= i
.rm
.reg
;
2915 /* Use the next insn. */
2919 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
2920 vector_length
= avxscalar
;
2922 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
2924 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2929 case DATA_PREFIX_OPCODE
:
2932 case REPE_PREFIX_OPCODE
:
2935 case REPNE_PREFIX_OPCODE
:
2942 /* Use 2-byte VEX prefix if possible. */
2943 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2944 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
2945 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2947 /* 2-byte VEX prefix. */
2951 i
.vex
.bytes
[0] = 0xc5;
2953 /* Check the REX.R bit. */
2954 r
= (i
.rex
& REX_R
) ? 0 : 1;
2955 i
.vex
.bytes
[1] = (r
<< 7
2956 | register_specifier
<< 3
2957 | vector_length
<< 2
2962 /* 3-byte VEX prefix. */
2967 switch (i
.tm
.opcode_modifier
.vexopcode
)
2971 i
.vex
.bytes
[0] = 0xc4;
2975 i
.vex
.bytes
[0] = 0xc4;
2979 i
.vex
.bytes
[0] = 0xc4;
2983 i
.vex
.bytes
[0] = 0x8f;
2987 i
.vex
.bytes
[0] = 0x8f;
2991 i
.vex
.bytes
[0] = 0x8f;
2997 /* The high 3 bits of the second VEX byte are 1's compliment
2998 of RXB bits from REX. */
2999 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3001 /* Check the REX.W bit. */
3002 w
= (i
.rex
& REX_W
) ? 1 : 0;
3003 if (i
.tm
.opcode_modifier
.vexw
)
3008 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3012 i
.vex
.bytes
[2] = (w
<< 7
3013 | register_specifier
<< 3
3014 | vector_length
<< 2
3020 process_immext (void)
3024 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3027 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3028 with an opcode suffix which is coded in the same place as an
3029 8-bit immediate field would be.
3030 Here we check those operands and remove them afterwards. */
3033 for (x
= 0; x
< i
.operands
; x
++)
3034 if (register_number (i
.op
[x
].regs
) != x
)
3035 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3036 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3042 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3043 which is coded in the same place as an 8-bit immediate field
3044 would be. Here we fake an 8-bit immediate operand from the
3045 opcode suffix stored in tm.extension_opcode.
3047 AVX instructions also use this encoding, for some of
3048 3 argument instructions. */
3050 gas_assert (i
.imm_operands
== 0
3052 || (i
.tm
.opcode_modifier
.vex
3053 && i
.operands
<= 4)));
3055 exp
= &im_expressions
[i
.imm_operands
++];
3056 i
.op
[i
.operands
].imms
= exp
;
3057 i
.types
[i
.operands
] = imm8
;
3059 exp
->X_op
= O_constant
;
3060 exp
->X_add_number
= i
.tm
.extension_opcode
;
3061 i
.tm
.extension_opcode
= None
;
3068 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3073 as_bad (_("invalid instruction `%s' after `%s'"),
3074 i
.tm
.name
, i
.hle_prefix
);
3077 if (i
.prefix
[LOCK_PREFIX
])
3079 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3083 case HLEPrefixRelease
:
3084 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3086 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3090 if (i
.mem_operands
== 0
3091 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3093 as_bad (_("memory destination needed for instruction `%s'"
3094 " after `xrelease'"), i
.tm
.name
);
3101 /* This is the guts of the machine-dependent assembler. LINE points to a
3102 machine dependent instruction. This function is supposed to emit
3103 the frags/bytes it assembles to. */
3106 md_assemble (char *line
)
3109 char mnemonic
[MAX_MNEM_SIZE
];
3110 const insn_template
*t
;
3112 /* Initialize globals. */
3113 memset (&i
, '\0', sizeof (i
));
3114 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3115 i
.reloc
[j
] = NO_RELOC
;
3116 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3117 memset (im_expressions
, '\0', sizeof (im_expressions
));
3118 save_stack_p
= save_stack
;
3120 /* First parse an instruction mnemonic & call i386_operand for the operands.
3121 We assume that the scrubber has arranged it so that line[0] is the valid
3122 start of a (possibly prefixed) mnemonic. */
3124 line
= parse_insn (line
, mnemonic
);
3128 line
= parse_operands (line
, mnemonic
);
3133 /* Now we've parsed the mnemonic into a set of templates, and have the
3134 operands at hand. */
3136 /* All intel opcodes have reversed operands except for "bound" and
3137 "enter". We also don't reverse intersegment "jmp" and "call"
3138 instructions with 2 immediate operands so that the immediate segment
3139 precedes the offset, as it does when in AT&T mode. */
3142 && (strcmp (mnemonic
, "bound") != 0)
3143 && (strcmp (mnemonic
, "invlpga") != 0)
3144 && !(operand_type_check (i
.types
[0], imm
)
3145 && operand_type_check (i
.types
[1], imm
)))
3148 /* The order of the immediates should be reversed
3149 for 2 immediates extrq and insertq instructions */
3150 if (i
.imm_operands
== 2
3151 && (strcmp (mnemonic
, "extrq") == 0
3152 || strcmp (mnemonic
, "insertq") == 0))
3153 swap_2_operands (0, 1);
3158 /* Don't optimize displacement for movabs since it only takes 64bit
3161 && i
.disp_encoding
!= disp_encoding_32bit
3162 && (flag_code
!= CODE_64BIT
3163 || strcmp (mnemonic
, "movabs") != 0))
3166 /* Next, we find a template that matches the given insn,
3167 making sure the overlap of the given operands types is consistent
3168 with the template operand types. */
3170 if (!(t
= match_template ()))
3173 if (sse_check
!= check_none
3174 && !i
.tm
.opcode_modifier
.noavx
3175 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3176 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3177 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3178 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3179 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3180 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3182 (sse_check
== check_warning
3184 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3187 /* Zap movzx and movsx suffix. The suffix has been set from
3188 "word ptr" or "byte ptr" on the source operand in Intel syntax
3189 or extracted from mnemonic in AT&T syntax. But we'll use
3190 the destination register to choose the suffix for encoding. */
3191 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3193 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3194 there is no suffix, the default will be byte extension. */
3195 if (i
.reg_operands
!= 2
3198 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3203 if (i
.tm
.opcode_modifier
.fwait
)
3204 if (!add_prefix (FWAIT_OPCODE
))
3207 /* Check if REP prefix is OK. */
3208 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3210 as_bad (_("invalid instruction `%s' after `%s'"),
3211 i
.tm
.name
, i
.rep_prefix
);
3215 /* Check for lock without a lockable instruction. Destination operand
3216 must be memory unless it is xchg (0x86). */
3217 if (i
.prefix
[LOCK_PREFIX
]
3218 && (!i
.tm
.opcode_modifier
.islockable
3219 || i
.mem_operands
== 0
3220 || (i
.tm
.base_opcode
!= 0x86
3221 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3223 as_bad (_("expecting lockable instruction after `lock'"));
3227 /* Check if HLE prefix is OK. */
3228 if (i
.hle_prefix
&& !check_hle ())
3231 /* Check BND prefix. */
3232 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3233 as_bad (_("expecting valid branch instruction after `bnd'"));
3235 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3236 && flag_code
== CODE_64BIT
3237 && i
.prefix
[ADDR_PREFIX
])
3238 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3240 /* Insert BND prefix. */
3242 && i
.tm
.opcode_modifier
.bndprefixok
3243 && !i
.prefix
[BND_PREFIX
])
3244 add_prefix (BND_PREFIX_OPCODE
);
3246 /* Check string instruction segment overrides. */
3247 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3249 if (!check_string ())
3251 i
.disp_operands
= 0;
3254 if (!process_suffix ())
3257 /* Update operand types. */
3258 for (j
= 0; j
< i
.operands
; j
++)
3259 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3261 /* Make still unresolved immediate matches conform to size of immediate
3262 given in i.suffix. */
3263 if (!finalize_imm ())
3266 if (i
.types
[0].bitfield
.imm1
)
3267 i
.imm_operands
= 0; /* kludge for shift insns. */
3269 /* We only need to check those implicit registers for instructions
3270 with 3 operands or less. */
3271 if (i
.operands
<= 3)
3272 for (j
= 0; j
< i
.operands
; j
++)
3273 if (i
.types
[j
].bitfield
.inoutportreg
3274 || i
.types
[j
].bitfield
.shiftcount
3275 || i
.types
[j
].bitfield
.acc
3276 || i
.types
[j
].bitfield
.floatacc
)
3279 /* ImmExt should be processed after SSE2AVX. */
3280 if (!i
.tm
.opcode_modifier
.sse2avx
3281 && i
.tm
.opcode_modifier
.immext
)
3284 /* For insns with operands there are more diddles to do to the opcode. */
3287 if (!process_operands ())
3290 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3292 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3293 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3296 if (i
.tm
.opcode_modifier
.vex
)
3297 build_vex_prefix (t
);
3299 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3300 instructions may define INT_OPCODE as well, so avoid this corner
3301 case for those instructions that use MODRM. */
3302 if (i
.tm
.base_opcode
== INT_OPCODE
3303 && !i
.tm
.opcode_modifier
.modrm
3304 && i
.op
[0].imms
->X_add_number
== 3)
3306 i
.tm
.base_opcode
= INT3_OPCODE
;
3310 if ((i
.tm
.opcode_modifier
.jump
3311 || i
.tm
.opcode_modifier
.jumpbyte
3312 || i
.tm
.opcode_modifier
.jumpdword
)
3313 && i
.op
[0].disps
->X_op
== O_constant
)
3315 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3316 the absolute address given by the constant. Since ix86 jumps and
3317 calls are pc relative, we need to generate a reloc. */
3318 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3319 i
.op
[0].disps
->X_op
= O_symbol
;
3322 if (i
.tm
.opcode_modifier
.rex64
)
3325 /* For 8 bit registers we need an empty rex prefix. Also if the
3326 instruction already has a prefix, we need to convert old
3327 registers to new ones. */
3329 if ((i
.types
[0].bitfield
.reg8
3330 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3331 || (i
.types
[1].bitfield
.reg8
3332 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3333 || ((i
.types
[0].bitfield
.reg8
3334 || i
.types
[1].bitfield
.reg8
)
3339 i
.rex
|= REX_OPCODE
;
3340 for (x
= 0; x
< 2; x
++)
3342 /* Look for 8 bit operand that uses old registers. */
3343 if (i
.types
[x
].bitfield
.reg8
3344 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3346 /* In case it is "hi" register, give up. */
3347 if (i
.op
[x
].regs
->reg_num
> 3)
3348 as_bad (_("can't encode register '%s%s' in an "
3349 "instruction requiring REX prefix."),
3350 register_prefix
, i
.op
[x
].regs
->reg_name
);
3352 /* Otherwise it is equivalent to the extended register.
3353 Since the encoding doesn't change this is merely
3354 cosmetic cleanup for debug output. */
3356 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3362 add_prefix (REX_OPCODE
| i
.rex
);
3364 /* We are ready to output the insn. */
3369 parse_insn (char *line
, char *mnemonic
)
3372 char *token_start
= l
;
3375 const insn_template
*t
;
3381 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3386 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3388 as_bad (_("no such instruction: `%s'"), token_start
);
3393 if (!is_space_char (*l
)
3394 && *l
!= END_OF_INSN
3396 || (*l
!= PREFIX_SEPARATOR
3399 as_bad (_("invalid character %s in mnemonic"),
3400 output_invalid (*l
));
3403 if (token_start
== l
)
3405 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3406 as_bad (_("expecting prefix; got nothing"));
3408 as_bad (_("expecting mnemonic; got nothing"));
3412 /* Look up instruction (or prefix) via hash table. */
3413 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3415 if (*l
!= END_OF_INSN
3416 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3417 && current_templates
3418 && current_templates
->start
->opcode_modifier
.isprefix
)
3420 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3422 as_bad ((flag_code
!= CODE_64BIT
3423 ? _("`%s' is only supported in 64-bit mode")
3424 : _("`%s' is not supported in 64-bit mode")),
3425 current_templates
->start
->name
);
3428 /* If we are in 16-bit mode, do not allow addr16 or data16.
3429 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3430 if ((current_templates
->start
->opcode_modifier
.size16
3431 || current_templates
->start
->opcode_modifier
.size32
)
3432 && flag_code
!= CODE_64BIT
3433 && (current_templates
->start
->opcode_modifier
.size32
3434 ^ (flag_code
== CODE_16BIT
)))
3436 as_bad (_("redundant %s prefix"),
3437 current_templates
->start
->name
);
3440 /* Add prefix, checking for repeated prefixes. */
3441 switch (add_prefix (current_templates
->start
->base_opcode
))
3446 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3447 i
.hle_prefix
= current_templates
->start
->name
;
3448 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3449 i
.bnd_prefix
= current_templates
->start
->name
;
3451 i
.rep_prefix
= current_templates
->start
->name
;
3456 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3463 if (!current_templates
)
3465 /* Check if we should swap operand or force 32bit displacement in
3467 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3469 else if (mnem_p
- 3 == dot_p
3472 i
.disp_encoding
= disp_encoding_8bit
;
3473 else if (mnem_p
- 4 == dot_p
3477 i
.disp_encoding
= disp_encoding_32bit
;
3482 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3485 if (!current_templates
)
3488 /* See if we can get a match by trimming off a suffix. */
3491 case WORD_MNEM_SUFFIX
:
3492 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3493 i
.suffix
= SHORT_MNEM_SUFFIX
;
3495 case BYTE_MNEM_SUFFIX
:
3496 case QWORD_MNEM_SUFFIX
:
3497 i
.suffix
= mnem_p
[-1];
3499 current_templates
= (const templates
*) hash_find (op_hash
,
3502 case SHORT_MNEM_SUFFIX
:
3503 case LONG_MNEM_SUFFIX
:
3506 i
.suffix
= mnem_p
[-1];
3508 current_templates
= (const templates
*) hash_find (op_hash
,
3517 if (intel_float_operand (mnemonic
) == 1)
3518 i
.suffix
= SHORT_MNEM_SUFFIX
;
3520 i
.suffix
= LONG_MNEM_SUFFIX
;
3522 current_templates
= (const templates
*) hash_find (op_hash
,
3527 if (!current_templates
)
3529 as_bad (_("no such instruction: `%s'"), token_start
);
3534 if (current_templates
->start
->opcode_modifier
.jump
3535 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3537 /* Check for a branch hint. We allow ",pt" and ",pn" for
3538 predict taken and predict not taken respectively.
3539 I'm not sure that branch hints actually do anything on loop
3540 and jcxz insns (JumpByte) for current Pentium4 chips. They
3541 may work in the future and it doesn't hurt to accept them
3543 if (l
[0] == ',' && l
[1] == 'p')
3547 if (!add_prefix (DS_PREFIX_OPCODE
))
3551 else if (l
[2] == 'n')
3553 if (!add_prefix (CS_PREFIX_OPCODE
))
3559 /* Any other comma loses. */
3562 as_bad (_("invalid character %s in mnemonic"),
3563 output_invalid (*l
));
3567 /* Check if instruction is supported on specified architecture. */
3569 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3571 supported
|= cpu_flags_match (t
);
3572 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3576 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3578 as_bad (flag_code
== CODE_64BIT
3579 ? _("`%s' is not supported in 64-bit mode")
3580 : _("`%s' is only supported in 64-bit mode"),
3581 current_templates
->start
->name
);
3584 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3586 as_bad (_("`%s' is not supported on `%s%s'"),
3587 current_templates
->start
->name
,
3588 cpu_arch_name
? cpu_arch_name
: default_arch
,
3589 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3594 if (!cpu_arch_flags
.bitfield
.cpui386
3595 && (flag_code
!= CODE_16BIT
))
3597 as_warn (_("use .code16 to ensure correct addressing mode"));
3604 parse_operands (char *l
, const char *mnemonic
)
3608 /* 1 if operand is pending after ','. */
3609 unsigned int expecting_operand
= 0;
3611 /* Non-zero if operand parens not balanced. */
3612 unsigned int paren_not_balanced
;
3614 while (*l
!= END_OF_INSN
)
3616 /* Skip optional white space before operand. */
3617 if (is_space_char (*l
))
3619 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3621 as_bad (_("invalid character %s before operand %d"),
3622 output_invalid (*l
),
3626 token_start
= l
; /* after white space */
3627 paren_not_balanced
= 0;
3628 while (paren_not_balanced
|| *l
!= ',')
3630 if (*l
== END_OF_INSN
)
3632 if (paren_not_balanced
)
3635 as_bad (_("unbalanced parenthesis in operand %d."),
3638 as_bad (_("unbalanced brackets in operand %d."),
3643 break; /* we are done */
3645 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3647 as_bad (_("invalid character %s in operand %d"),
3648 output_invalid (*l
),
3655 ++paren_not_balanced
;
3657 --paren_not_balanced
;
3662 ++paren_not_balanced
;
3664 --paren_not_balanced
;
3668 if (l
!= token_start
)
3669 { /* Yes, we've read in another operand. */
3670 unsigned int operand_ok
;
3671 this_operand
= i
.operands
++;
3672 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3673 if (i
.operands
> MAX_OPERANDS
)
3675 as_bad (_("spurious operands; (%d operands/instruction max)"),
3679 /* Now parse operand adding info to 'i' as we go along. */
3680 END_STRING_AND_SAVE (l
);
3684 i386_intel_operand (token_start
,
3685 intel_float_operand (mnemonic
));
3687 operand_ok
= i386_att_operand (token_start
);
3689 RESTORE_END_STRING (l
);
3695 if (expecting_operand
)
3697 expecting_operand_after_comma
:
3698 as_bad (_("expecting operand after ','; got nothing"));
3703 as_bad (_("expecting operand before ','; got nothing"));
3708 /* Now *l must be either ',' or END_OF_INSN. */
3711 if (*++l
== END_OF_INSN
)
3713 /* Just skip it, if it's \n complain. */
3714 goto expecting_operand_after_comma
;
3716 expecting_operand
= 1;
3723 swap_2_operands (int xchg1
, int xchg2
)
3725 union i386_op temp_op
;
3726 i386_operand_type temp_type
;
3727 enum bfd_reloc_code_real temp_reloc
;
3729 temp_type
= i
.types
[xchg2
];
3730 i
.types
[xchg2
] = i
.types
[xchg1
];
3731 i
.types
[xchg1
] = temp_type
;
3732 temp_op
= i
.op
[xchg2
];
3733 i
.op
[xchg2
] = i
.op
[xchg1
];
3734 i
.op
[xchg1
] = temp_op
;
3735 temp_reloc
= i
.reloc
[xchg2
];
3736 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3737 i
.reloc
[xchg1
] = temp_reloc
;
3741 swap_operands (void)
3747 swap_2_operands (1, i
.operands
- 2);
3750 swap_2_operands (0, i
.operands
- 1);
3756 if (i
.mem_operands
== 2)
3758 const seg_entry
*temp_seg
;
3759 temp_seg
= i
.seg
[0];
3760 i
.seg
[0] = i
.seg
[1];
3761 i
.seg
[1] = temp_seg
;
3765 /* Try to ensure constant immediates are represented in the smallest
3770 char guess_suffix
= 0;
3774 guess_suffix
= i
.suffix
;
3775 else if (i
.reg_operands
)
3777 /* Figure out a suffix from the last register operand specified.
3778 We can't do this properly yet, ie. excluding InOutPortReg,
3779 but the following works for instructions with immediates.
3780 In any case, we can't set i.suffix yet. */
3781 for (op
= i
.operands
; --op
>= 0;)
3782 if (i
.types
[op
].bitfield
.reg8
)
3784 guess_suffix
= BYTE_MNEM_SUFFIX
;
3787 else if (i
.types
[op
].bitfield
.reg16
)
3789 guess_suffix
= WORD_MNEM_SUFFIX
;
3792 else if (i
.types
[op
].bitfield
.reg32
)
3794 guess_suffix
= LONG_MNEM_SUFFIX
;
3797 else if (i
.types
[op
].bitfield
.reg64
)
3799 guess_suffix
= QWORD_MNEM_SUFFIX
;
3803 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3804 guess_suffix
= WORD_MNEM_SUFFIX
;
3806 for (op
= i
.operands
; --op
>= 0;)
3807 if (operand_type_check (i
.types
[op
], imm
))
3809 switch (i
.op
[op
].imms
->X_op
)
3812 /* If a suffix is given, this operand may be shortened. */
3813 switch (guess_suffix
)
3815 case LONG_MNEM_SUFFIX
:
3816 i
.types
[op
].bitfield
.imm32
= 1;
3817 i
.types
[op
].bitfield
.imm64
= 1;
3819 case WORD_MNEM_SUFFIX
:
3820 i
.types
[op
].bitfield
.imm16
= 1;
3821 i
.types
[op
].bitfield
.imm32
= 1;
3822 i
.types
[op
].bitfield
.imm32s
= 1;
3823 i
.types
[op
].bitfield
.imm64
= 1;
3825 case BYTE_MNEM_SUFFIX
:
3826 i
.types
[op
].bitfield
.imm8
= 1;
3827 i
.types
[op
].bitfield
.imm8s
= 1;
3828 i
.types
[op
].bitfield
.imm16
= 1;
3829 i
.types
[op
].bitfield
.imm32
= 1;
3830 i
.types
[op
].bitfield
.imm32s
= 1;
3831 i
.types
[op
].bitfield
.imm64
= 1;
3835 /* If this operand is at most 16 bits, convert it
3836 to a signed 16 bit number before trying to see
3837 whether it will fit in an even smaller size.
3838 This allows a 16-bit operand such as $0xffe0 to
3839 be recognised as within Imm8S range. */
3840 if ((i
.types
[op
].bitfield
.imm16
)
3841 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3843 i
.op
[op
].imms
->X_add_number
=
3844 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3846 if ((i
.types
[op
].bitfield
.imm32
)
3847 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3850 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3851 ^ ((offsetT
) 1 << 31))
3852 - ((offsetT
) 1 << 31));
3855 = operand_type_or (i
.types
[op
],
3856 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3858 /* We must avoid matching of Imm32 templates when 64bit
3859 only immediate is available. */
3860 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3861 i
.types
[op
].bitfield
.imm32
= 0;
3868 /* Symbols and expressions. */
3870 /* Convert symbolic operand to proper sizes for matching, but don't
3871 prevent matching a set of insns that only supports sizes other
3872 than those matching the insn suffix. */
3874 i386_operand_type mask
, allowed
;
3875 const insn_template
*t
;
3877 operand_type_set (&mask
, 0);
3878 operand_type_set (&allowed
, 0);
3880 for (t
= current_templates
->start
;
3881 t
< current_templates
->end
;
3883 allowed
= operand_type_or (allowed
,
3884 t
->operand_types
[op
]);
3885 switch (guess_suffix
)
3887 case QWORD_MNEM_SUFFIX
:
3888 mask
.bitfield
.imm64
= 1;
3889 mask
.bitfield
.imm32s
= 1;
3891 case LONG_MNEM_SUFFIX
:
3892 mask
.bitfield
.imm32
= 1;
3894 case WORD_MNEM_SUFFIX
:
3895 mask
.bitfield
.imm16
= 1;
3897 case BYTE_MNEM_SUFFIX
:
3898 mask
.bitfield
.imm8
= 1;
3903 allowed
= operand_type_and (mask
, allowed
);
3904 if (!operand_type_all_zero (&allowed
))
3905 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3912 /* Try to use the smallest displacement type too. */
3914 optimize_disp (void)
3918 for (op
= i
.operands
; --op
>= 0;)
3919 if (operand_type_check (i
.types
[op
], disp
))
3921 if (i
.op
[op
].disps
->X_op
== O_constant
)
3923 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
3925 if (i
.types
[op
].bitfield
.disp16
3926 && (op_disp
& ~(offsetT
) 0xffff) == 0)
3928 /* If this operand is at most 16 bits, convert
3929 to a signed 16 bit number and don't use 64bit
3931 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
3932 i
.types
[op
].bitfield
.disp64
= 0;
3934 if (i
.types
[op
].bitfield
.disp32
3935 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3937 /* If this operand is at most 32 bits, convert
3938 to a signed 32 bit number and don't use 64bit
3940 op_disp
&= (((offsetT
) 2 << 31) - 1);
3941 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3942 i
.types
[op
].bitfield
.disp64
= 0;
3944 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
3946 i
.types
[op
].bitfield
.disp8
= 0;
3947 i
.types
[op
].bitfield
.disp16
= 0;
3948 i
.types
[op
].bitfield
.disp32
= 0;
3949 i
.types
[op
].bitfield
.disp32s
= 0;
3950 i
.types
[op
].bitfield
.disp64
= 0;
3954 else if (flag_code
== CODE_64BIT
)
3956 if (fits_in_signed_long (op_disp
))
3958 i
.types
[op
].bitfield
.disp64
= 0;
3959 i
.types
[op
].bitfield
.disp32s
= 1;
3961 if (i
.prefix
[ADDR_PREFIX
]
3962 && fits_in_unsigned_long (op_disp
))
3963 i
.types
[op
].bitfield
.disp32
= 1;
3965 if ((i
.types
[op
].bitfield
.disp32
3966 || i
.types
[op
].bitfield
.disp32s
3967 || i
.types
[op
].bitfield
.disp16
)
3968 && fits_in_signed_byte (op_disp
))
3969 i
.types
[op
].bitfield
.disp8
= 1;
3971 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3972 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3974 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3975 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3976 i
.types
[op
].bitfield
.disp8
= 0;
3977 i
.types
[op
].bitfield
.disp16
= 0;
3978 i
.types
[op
].bitfield
.disp32
= 0;
3979 i
.types
[op
].bitfield
.disp32s
= 0;
3980 i
.types
[op
].bitfield
.disp64
= 0;
3983 /* We only support 64bit displacement on constants. */
3984 i
.types
[op
].bitfield
.disp64
= 0;
3988 /* Check if operands are valid for the instruction. */
3991 check_VecOperands (const insn_template
*t
)
3993 /* Without VSIB byte, we can't have a vector register for index. */
3994 if (!t
->opcode_modifier
.vecsib
3996 && (i
.index_reg
->reg_type
.bitfield
.regxmm
3997 || i
.index_reg
->reg_type
.bitfield
.regymm
))
3999 i
.error
= unsupported_vector_index_register
;
4003 /* For VSIB byte, we need a vector register for index, and all vector
4004 registers must be distinct. */
4005 if (t
->opcode_modifier
.vecsib
)
4008 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4009 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4010 || (t
->opcode_modifier
.vecsib
== VecSIB256
4011 && i
.index_reg
->reg_type
.bitfield
.regymm
)))
4013 i
.error
= invalid_vsib_address
;
4017 gas_assert (i
.reg_operands
== 2);
4018 gas_assert (i
.types
[0].bitfield
.regxmm
4019 || i
.types
[0].bitfield
.regymm
);
4020 gas_assert (i
.types
[2].bitfield
.regxmm
4021 || i
.types
[2].bitfield
.regymm
);
4023 if (operand_check
== check_none
)
4025 if (register_number (i
.op
[0].regs
) != register_number (i
.index_reg
)
4026 && register_number (i
.op
[2].regs
) != register_number (i
.index_reg
)
4027 && register_number (i
.op
[0].regs
) != register_number (i
.op
[2].regs
))
4029 if (operand_check
== check_error
)
4031 i
.error
= invalid_vector_register_set
;
4034 as_warn (_("mask, index, and destination registers should be distinct"));
4040 /* Check if operands are valid for the instruction. Update VEX
4044 VEX_check_operands (const insn_template
*t
)
4046 if (!t
->opcode_modifier
.vex
)
4049 /* Only check VEX_Imm4, which must be the first operand. */
4050 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4052 if (i
.op
[0].imms
->X_op
!= O_constant
4053 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4059 /* Turn off Imm8 so that update_imm won't complain. */
4060 i
.types
[0] = vec_imm4
;
4066 static const insn_template
*
4067 match_template (void)
4069 /* Points to template once we've found it. */
4070 const insn_template
*t
;
4071 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4072 i386_operand_type overlap4
;
4073 unsigned int found_reverse_match
;
4074 i386_opcode_modifier suffix_check
;
4075 i386_operand_type operand_types
[MAX_OPERANDS
];
4076 int addr_prefix_disp
;
4078 unsigned int found_cpu_match
;
4079 unsigned int check_register
;
4080 enum i386_error specific_error
= 0;
4082 #if MAX_OPERANDS != 5
4083 # error "MAX_OPERANDS must be 5."
4086 found_reverse_match
= 0;
4087 addr_prefix_disp
= -1;
4089 memset (&suffix_check
, 0, sizeof (suffix_check
));
4090 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4091 suffix_check
.no_bsuf
= 1;
4092 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4093 suffix_check
.no_wsuf
= 1;
4094 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4095 suffix_check
.no_ssuf
= 1;
4096 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4097 suffix_check
.no_lsuf
= 1;
4098 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4099 suffix_check
.no_qsuf
= 1;
4100 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4101 suffix_check
.no_ldsuf
= 1;
4103 /* Must have right number of operands. */
4104 i
.error
= number_of_operands_mismatch
;
4106 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4108 addr_prefix_disp
= -1;
4110 if (i
.operands
!= t
->operands
)
4113 /* Check processor support. */
4114 i
.error
= unsupported
;
4115 found_cpu_match
= (cpu_flags_match (t
)
4116 == CPU_FLAGS_PERFECT_MATCH
);
4117 if (!found_cpu_match
)
4120 /* Check old gcc support. */
4121 i
.error
= old_gcc_only
;
4122 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4125 /* Check AT&T mnemonic. */
4126 i
.error
= unsupported_with_intel_mnemonic
;
4127 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4130 /* Check AT&T/Intel syntax. */
4131 i
.error
= unsupported_syntax
;
4132 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4133 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4136 /* Check the suffix, except for some instructions in intel mode. */
4137 i
.error
= invalid_instruction_suffix
;
4138 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4139 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4140 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4141 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4142 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4143 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4144 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4147 if (!operand_size_match (t
))
4150 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4151 operand_types
[j
] = t
->operand_types
[j
];
4153 /* In general, don't allow 64-bit operands in 32-bit mode. */
4154 if (i
.suffix
== QWORD_MNEM_SUFFIX
4155 && flag_code
!= CODE_64BIT
4157 ? (!t
->opcode_modifier
.ignoresize
4158 && !intel_float_operand (t
->name
))
4159 : intel_float_operand (t
->name
) != 2)
4160 && ((!operand_types
[0].bitfield
.regmmx
4161 && !operand_types
[0].bitfield
.regxmm
4162 && !operand_types
[0].bitfield
.regymm
)
4163 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4164 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
4165 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
4166 && (t
->base_opcode
!= 0x0fc7
4167 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4170 /* In general, don't allow 32-bit operands on pre-386. */
4171 else if (i
.suffix
== LONG_MNEM_SUFFIX
4172 && !cpu_arch_flags
.bitfield
.cpui386
4174 ? (!t
->opcode_modifier
.ignoresize
4175 && !intel_float_operand (t
->name
))
4176 : intel_float_operand (t
->name
) != 2)
4177 && ((!operand_types
[0].bitfield
.regmmx
4178 && !operand_types
[0].bitfield
.regxmm
)
4179 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4180 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4183 /* Do not verify operands when there are none. */
4187 /* We've found a match; break out of loop. */
4191 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4192 into Disp32/Disp16/Disp32 operand. */
4193 if (i
.prefix
[ADDR_PREFIX
] != 0)
4195 /* There should be only one Disp operand. */
4199 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4201 if (operand_types
[j
].bitfield
.disp16
)
4203 addr_prefix_disp
= j
;
4204 operand_types
[j
].bitfield
.disp32
= 1;
4205 operand_types
[j
].bitfield
.disp16
= 0;
4211 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4213 if (operand_types
[j
].bitfield
.disp32
)
4215 addr_prefix_disp
= j
;
4216 operand_types
[j
].bitfield
.disp32
= 0;
4217 operand_types
[j
].bitfield
.disp16
= 1;
4223 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4225 if (operand_types
[j
].bitfield
.disp64
)
4227 addr_prefix_disp
= j
;
4228 operand_types
[j
].bitfield
.disp64
= 0;
4229 operand_types
[j
].bitfield
.disp32
= 1;
4237 /* We check register size if needed. */
4238 check_register
= t
->opcode_modifier
.checkregsize
;
4239 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4240 switch (t
->operands
)
4243 if (!operand_type_match (overlap0
, i
.types
[0]))
4247 /* xchg %eax, %eax is a special case. It is an aliase for nop
4248 only in 32bit mode and we can use opcode 0x90. In 64bit
4249 mode, we can't use 0x90 for xchg %eax, %eax since it should
4250 zero-extend %eax to %rax. */
4251 if (flag_code
== CODE_64BIT
4252 && t
->base_opcode
== 0x90
4253 && operand_type_equal (&i
.types
[0], &acc32
)
4254 && operand_type_equal (&i
.types
[1], &acc32
))
4258 /* If we swap operand in encoding, we either match
4259 the next one or reverse direction of operands. */
4260 if (t
->opcode_modifier
.s
)
4262 else if (t
->opcode_modifier
.d
)
4267 /* If we swap operand in encoding, we match the next one. */
4268 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4272 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4273 if (!operand_type_match (overlap0
, i
.types
[0])
4274 || !operand_type_match (overlap1
, i
.types
[1])
4276 && !operand_type_register_match (overlap0
, i
.types
[0],
4278 overlap1
, i
.types
[1],
4281 /* Check if other direction is valid ... */
4282 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4286 /* Try reversing direction of operands. */
4287 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4288 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4289 if (!operand_type_match (overlap0
, i
.types
[0])
4290 || !operand_type_match (overlap1
, i
.types
[1])
4292 && !operand_type_register_match (overlap0
,
4299 /* Does not match either direction. */
4302 /* found_reverse_match holds which of D or FloatDR
4304 if (t
->opcode_modifier
.d
)
4305 found_reverse_match
= Opcode_D
;
4306 else if (t
->opcode_modifier
.floatd
)
4307 found_reverse_match
= Opcode_FloatD
;
4309 found_reverse_match
= 0;
4310 if (t
->opcode_modifier
.floatr
)
4311 found_reverse_match
|= Opcode_FloatR
;
4315 /* Found a forward 2 operand match here. */
4316 switch (t
->operands
)
4319 overlap4
= operand_type_and (i
.types
[4],
4322 overlap3
= operand_type_and (i
.types
[3],
4325 overlap2
= operand_type_and (i
.types
[2],
4330 switch (t
->operands
)
4333 if (!operand_type_match (overlap4
, i
.types
[4])
4334 || !operand_type_register_match (overlap3
,
4342 if (!operand_type_match (overlap3
, i
.types
[3])
4344 && !operand_type_register_match (overlap2
,
4352 /* Here we make use of the fact that there are no
4353 reverse match 3 operand instructions, and all 3
4354 operand instructions only need to be checked for
4355 register consistency between operands 2 and 3. */
4356 if (!operand_type_match (overlap2
, i
.types
[2])
4358 && !operand_type_register_match (overlap1
,
4368 /* Found either forward/reverse 2, 3 or 4 operand match here:
4369 slip through to break. */
4371 if (!found_cpu_match
)
4373 found_reverse_match
= 0;
4377 /* Check if vector and VEX operands are valid. */
4378 if (check_VecOperands (t
) || VEX_check_operands (t
))
4380 specific_error
= i
.error
;
4384 /* We've found a match; break out of loop. */
4388 if (t
== current_templates
->end
)
4390 /* We found no match. */
4391 const char *err_msg
;
4392 switch (specific_error
? specific_error
: i
.error
)
4396 case operand_size_mismatch
:
4397 err_msg
= _("operand size mismatch");
4399 case operand_type_mismatch
:
4400 err_msg
= _("operand type mismatch");
4402 case register_type_mismatch
:
4403 err_msg
= _("register type mismatch");
4405 case number_of_operands_mismatch
:
4406 err_msg
= _("number of operands mismatch");
4408 case invalid_instruction_suffix
:
4409 err_msg
= _("invalid instruction suffix");
4412 err_msg
= _("constant doesn't fit in 4 bits");
4415 err_msg
= _("only supported with old gcc");
4417 case unsupported_with_intel_mnemonic
:
4418 err_msg
= _("unsupported with Intel mnemonic");
4420 case unsupported_syntax
:
4421 err_msg
= _("unsupported syntax");
4424 as_bad (_("unsupported instruction `%s'"),
4425 current_templates
->start
->name
);
4427 case invalid_vsib_address
:
4428 err_msg
= _("invalid VSIB address");
4430 case invalid_vector_register_set
:
4431 err_msg
= _("mask, index, and destination registers must be distinct");
4433 case unsupported_vector_index_register
:
4434 err_msg
= _("unsupported vector index register");
4437 as_bad (_("%s for `%s'"), err_msg
,
4438 current_templates
->start
->name
);
4442 if (!quiet_warnings
)
4445 && (i
.types
[0].bitfield
.jumpabsolute
4446 != operand_types
[0].bitfield
.jumpabsolute
))
4448 as_warn (_("indirect %s without `*'"), t
->name
);
4451 if (t
->opcode_modifier
.isprefix
4452 && t
->opcode_modifier
.ignoresize
)
4454 /* Warn them that a data or address size prefix doesn't
4455 affect assembly of the next line of code. */
4456 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4460 /* Copy the template we found. */
4463 if (addr_prefix_disp
!= -1)
4464 i
.tm
.operand_types
[addr_prefix_disp
]
4465 = operand_types
[addr_prefix_disp
];
4467 if (found_reverse_match
)
4469 /* If we found a reverse match we must alter the opcode
4470 direction bit. found_reverse_match holds bits to change
4471 (different for int & float insns). */
4473 i
.tm
.base_opcode
^= found_reverse_match
;
4475 i
.tm
.operand_types
[0] = operand_types
[1];
4476 i
.tm
.operand_types
[1] = operand_types
[0];
4485 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4486 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4488 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4490 as_bad (_("`%s' operand %d must use `%ses' segment"),
4496 /* There's only ever one segment override allowed per instruction.
4497 This instruction possibly has a legal segment override on the
4498 second operand, so copy the segment to where non-string
4499 instructions store it, allowing common code. */
4500 i
.seg
[0] = i
.seg
[1];
4502 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4504 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4506 as_bad (_("`%s' operand %d must use `%ses' segment"),
4517 process_suffix (void)
4519 /* If matched instruction specifies an explicit instruction mnemonic
4521 if (i
.tm
.opcode_modifier
.size16
)
4522 i
.suffix
= WORD_MNEM_SUFFIX
;
4523 else if (i
.tm
.opcode_modifier
.size32
)
4524 i
.suffix
= LONG_MNEM_SUFFIX
;
4525 else if (i
.tm
.opcode_modifier
.size64
)
4526 i
.suffix
= QWORD_MNEM_SUFFIX
;
4527 else if (i
.reg_operands
)
4529 /* If there's no instruction mnemonic suffix we try to invent one
4530 based on register operands. */
4533 /* We take i.suffix from the last register operand specified,
4534 Destination register type is more significant than source
4535 register type. crc32 in SSE4.2 prefers source register
4537 if (i
.tm
.base_opcode
== 0xf20f38f1)
4539 if (i
.types
[0].bitfield
.reg16
)
4540 i
.suffix
= WORD_MNEM_SUFFIX
;
4541 else if (i
.types
[0].bitfield
.reg32
)
4542 i
.suffix
= LONG_MNEM_SUFFIX
;
4543 else if (i
.types
[0].bitfield
.reg64
)
4544 i
.suffix
= QWORD_MNEM_SUFFIX
;
4546 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4548 if (i
.types
[0].bitfield
.reg8
)
4549 i
.suffix
= BYTE_MNEM_SUFFIX
;
4556 if (i
.tm
.base_opcode
== 0xf20f38f1
4557 || i
.tm
.base_opcode
== 0xf20f38f0)
4559 /* We have to know the operand size for crc32. */
4560 as_bad (_("ambiguous memory operand size for `%s`"),
4565 for (op
= i
.operands
; --op
>= 0;)
4566 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4568 if (i
.types
[op
].bitfield
.reg8
)
4570 i
.suffix
= BYTE_MNEM_SUFFIX
;
4573 else if (i
.types
[op
].bitfield
.reg16
)
4575 i
.suffix
= WORD_MNEM_SUFFIX
;
4578 else if (i
.types
[op
].bitfield
.reg32
)
4580 i
.suffix
= LONG_MNEM_SUFFIX
;
4583 else if (i
.types
[op
].bitfield
.reg64
)
4585 i
.suffix
= QWORD_MNEM_SUFFIX
;
4591 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4594 && i
.tm
.opcode_modifier
.ignoresize
4595 && i
.tm
.opcode_modifier
.no_bsuf
)
4597 else if (!check_byte_reg ())
4600 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4603 && i
.tm
.opcode_modifier
.ignoresize
4604 && i
.tm
.opcode_modifier
.no_lsuf
)
4606 else if (!check_long_reg ())
4609 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4612 && i
.tm
.opcode_modifier
.ignoresize
4613 && i
.tm
.opcode_modifier
.no_qsuf
)
4615 else if (!check_qword_reg ())
4618 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4621 && i
.tm
.opcode_modifier
.ignoresize
4622 && i
.tm
.opcode_modifier
.no_wsuf
)
4624 else if (!check_word_reg ())
4627 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4628 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4630 /* Skip if the instruction has x/y suffix. match_template
4631 should check if it is a valid suffix. */
4633 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4634 /* Do nothing if the instruction is going to ignore the prefix. */
4639 else if (i
.tm
.opcode_modifier
.defaultsize
4641 /* exclude fldenv/frstor/fsave/fstenv */
4642 && i
.tm
.opcode_modifier
.no_ssuf
)
4644 i
.suffix
= stackop_size
;
4646 else if (intel_syntax
4648 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4649 || i
.tm
.opcode_modifier
.jumpbyte
4650 || i
.tm
.opcode_modifier
.jumpintersegment
4651 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4652 && i
.tm
.extension_opcode
<= 3)))
4657 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4659 i
.suffix
= QWORD_MNEM_SUFFIX
;
4663 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4664 i
.suffix
= LONG_MNEM_SUFFIX
;
4667 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4668 i
.suffix
= WORD_MNEM_SUFFIX
;
4677 if (i
.tm
.opcode_modifier
.w
)
4679 as_bad (_("no instruction mnemonic suffix given and "
4680 "no register operands; can't size instruction"));
4686 unsigned int suffixes
;
4688 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4689 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4691 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4693 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4695 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4697 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4700 /* There are more than suffix matches. */
4701 if (i
.tm
.opcode_modifier
.w
4702 || ((suffixes
& (suffixes
- 1))
4703 && !i
.tm
.opcode_modifier
.defaultsize
4704 && !i
.tm
.opcode_modifier
.ignoresize
))
4706 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4712 /* Change the opcode based on the operand size given by i.suffix;
4713 We don't need to change things for byte insns. */
4716 && i
.suffix
!= BYTE_MNEM_SUFFIX
4717 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4718 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4720 /* It's not a byte, select word/dword operation. */
4721 if (i
.tm
.opcode_modifier
.w
)
4723 if (i
.tm
.opcode_modifier
.shortform
)
4724 i
.tm
.base_opcode
|= 8;
4726 i
.tm
.base_opcode
|= 1;
4729 /* Now select between word & dword operations via the operand
4730 size prefix, except for instructions that will ignore this
4732 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4734 /* The address size override prefix changes the size of the
4736 if ((flag_code
== CODE_32BIT
4737 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4738 || (flag_code
!= CODE_32BIT
4739 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4740 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4743 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4744 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4745 && !i
.tm
.opcode_modifier
.ignoresize
4746 && !i
.tm
.opcode_modifier
.floatmf
4747 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4748 || (flag_code
== CODE_64BIT
4749 && i
.tm
.opcode_modifier
.jumpbyte
)))
4751 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4753 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4754 prefix
= ADDR_PREFIX_OPCODE
;
4756 if (!add_prefix (prefix
))
4760 /* Set mode64 for an operand. */
4761 if (i
.suffix
== QWORD_MNEM_SUFFIX
4762 && flag_code
== CODE_64BIT
4763 && !i
.tm
.opcode_modifier
.norex64
)
4765 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4766 need rex64. cmpxchg8b is also a special case. */
4767 if (! (i
.operands
== 2
4768 && i
.tm
.base_opcode
== 0x90
4769 && i
.tm
.extension_opcode
== None
4770 && operand_type_equal (&i
.types
[0], &acc64
)
4771 && operand_type_equal (&i
.types
[1], &acc64
))
4772 && ! (i
.operands
== 1
4773 && i
.tm
.base_opcode
== 0xfc7
4774 && i
.tm
.extension_opcode
== 1
4775 && !operand_type_check (i
.types
[0], reg
)
4776 && operand_type_check (i
.types
[0], anymem
)))
4780 /* Size floating point instruction. */
4781 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4782 if (i
.tm
.opcode_modifier
.floatmf
)
4783 i
.tm
.base_opcode
^= 4;
4790 check_byte_reg (void)
4794 for (op
= i
.operands
; --op
>= 0;)
4796 /* If this is an eight bit register, it's OK. If it's the 16 or
4797 32 bit version of an eight bit register, we will just use the
4798 low portion, and that's OK too. */
4799 if (i
.types
[op
].bitfield
.reg8
)
4802 /* I/O port address operands are OK too. */
4803 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4806 /* crc32 doesn't generate this warning. */
4807 if (i
.tm
.base_opcode
== 0xf20f38f0)
4810 if ((i
.types
[op
].bitfield
.reg16
4811 || i
.types
[op
].bitfield
.reg32
4812 || i
.types
[op
].bitfield
.reg64
)
4813 && i
.op
[op
].regs
->reg_num
< 4
4814 /* Prohibit these changes in 64bit mode, since the lowering
4815 would be more complicated. */
4816 && flag_code
!= CODE_64BIT
)
4818 #if REGISTER_WARNINGS
4819 if (!quiet_warnings
)
4820 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4822 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4823 ? REGNAM_AL
- REGNAM_AX
4824 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4826 i
.op
[op
].regs
->reg_name
,
4831 /* Any other register is bad. */
4832 if (i
.types
[op
].bitfield
.reg16
4833 || i
.types
[op
].bitfield
.reg32
4834 || i
.types
[op
].bitfield
.reg64
4835 || i
.types
[op
].bitfield
.regmmx
4836 || i
.types
[op
].bitfield
.regxmm
4837 || i
.types
[op
].bitfield
.regymm
4838 || i
.types
[op
].bitfield
.sreg2
4839 || i
.types
[op
].bitfield
.sreg3
4840 || i
.types
[op
].bitfield
.control
4841 || i
.types
[op
].bitfield
.debug
4842 || i
.types
[op
].bitfield
.test
4843 || i
.types
[op
].bitfield
.floatreg
4844 || i
.types
[op
].bitfield
.floatacc
)
4846 as_bad (_("`%s%s' not allowed with `%s%c'"),
4848 i
.op
[op
].regs
->reg_name
,
4858 check_long_reg (void)
4862 for (op
= i
.operands
; --op
>= 0;)
4863 /* Reject eight bit registers, except where the template requires
4864 them. (eg. movzb) */
4865 if (i
.types
[op
].bitfield
.reg8
4866 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4867 || i
.tm
.operand_types
[op
].bitfield
.reg32
4868 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4870 as_bad (_("`%s%s' not allowed with `%s%c'"),
4872 i
.op
[op
].regs
->reg_name
,
4877 /* Warn if the e prefix on a general reg is missing. */
4878 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4879 && i
.types
[op
].bitfield
.reg16
4880 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4881 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4883 /* Prohibit these changes in the 64bit mode, since the
4884 lowering is more complicated. */
4885 if (flag_code
== CODE_64BIT
)
4887 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4888 register_prefix
, i
.op
[op
].regs
->reg_name
,
4892 #if REGISTER_WARNINGS
4894 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4896 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4898 i
.op
[op
].regs
->reg_name
,
4902 /* Warn if the r prefix on a general reg is missing. */
4903 else if (i
.types
[op
].bitfield
.reg64
4904 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4905 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4908 && i
.tm
.opcode_modifier
.toqword
4909 && !i
.types
[0].bitfield
.regxmm
)
4911 /* Convert to QWORD. We want REX byte. */
4912 i
.suffix
= QWORD_MNEM_SUFFIX
;
4916 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4917 register_prefix
, i
.op
[op
].regs
->reg_name
,
4926 check_qword_reg (void)
4930 for (op
= i
.operands
; --op
>= 0; )
4931 /* Reject eight bit registers, except where the template requires
4932 them. (eg. movzb) */
4933 if (i
.types
[op
].bitfield
.reg8
4934 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4935 || i
.tm
.operand_types
[op
].bitfield
.reg32
4936 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4938 as_bad (_("`%s%s' not allowed with `%s%c'"),
4940 i
.op
[op
].regs
->reg_name
,
4945 /* Warn if the e prefix on a general reg is missing. */
4946 else if ((i
.types
[op
].bitfield
.reg16
4947 || i
.types
[op
].bitfield
.reg32
)
4948 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4949 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4951 /* Prohibit these changes in the 64bit mode, since the
4952 lowering is more complicated. */
4954 && i
.tm
.opcode_modifier
.todword
4955 && !i
.types
[0].bitfield
.regxmm
)
4957 /* Convert to DWORD. We don't want REX byte. */
4958 i
.suffix
= LONG_MNEM_SUFFIX
;
4962 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4963 register_prefix
, i
.op
[op
].regs
->reg_name
,
4972 check_word_reg (void)
4975 for (op
= i
.operands
; --op
>= 0;)
4976 /* Reject eight bit registers, except where the template requires
4977 them. (eg. movzb) */
4978 if (i
.types
[op
].bitfield
.reg8
4979 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4980 || i
.tm
.operand_types
[op
].bitfield
.reg32
4981 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4983 as_bad (_("`%s%s' not allowed with `%s%c'"),
4985 i
.op
[op
].regs
->reg_name
,
4990 /* Warn if the e prefix on a general reg is present. */
4991 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4992 && i
.types
[op
].bitfield
.reg32
4993 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4994 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4996 /* Prohibit these changes in the 64bit mode, since the
4997 lowering is more complicated. */
4998 if (flag_code
== CODE_64BIT
)
5000 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5001 register_prefix
, i
.op
[op
].regs
->reg_name
,
5006 #if REGISTER_WARNINGS
5007 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5009 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5011 i
.op
[op
].regs
->reg_name
,
5019 update_imm (unsigned int j
)
5021 i386_operand_type overlap
= i
.types
[j
];
5022 if ((overlap
.bitfield
.imm8
5023 || overlap
.bitfield
.imm8s
5024 || overlap
.bitfield
.imm16
5025 || overlap
.bitfield
.imm32
5026 || overlap
.bitfield
.imm32s
5027 || overlap
.bitfield
.imm64
)
5028 && !operand_type_equal (&overlap
, &imm8
)
5029 && !operand_type_equal (&overlap
, &imm8s
)
5030 && !operand_type_equal (&overlap
, &imm16
)
5031 && !operand_type_equal (&overlap
, &imm32
)
5032 && !operand_type_equal (&overlap
, &imm32s
)
5033 && !operand_type_equal (&overlap
, &imm64
))
5037 i386_operand_type temp
;
5039 operand_type_set (&temp
, 0);
5040 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5042 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5043 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5045 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5046 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5047 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5049 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5050 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5053 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5056 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5057 || operand_type_equal (&overlap
, &imm16_32
)
5058 || operand_type_equal (&overlap
, &imm16_32s
))
5060 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5065 if (!operand_type_equal (&overlap
, &imm8
)
5066 && !operand_type_equal (&overlap
, &imm8s
)
5067 && !operand_type_equal (&overlap
, &imm16
)
5068 && !operand_type_equal (&overlap
, &imm32
)
5069 && !operand_type_equal (&overlap
, &imm32s
)
5070 && !operand_type_equal (&overlap
, &imm64
))
5072 as_bad (_("no instruction mnemonic suffix given; "
5073 "can't determine immediate size"));
5077 i
.types
[j
] = overlap
;
5087 /* Update the first 2 immediate operands. */
5088 n
= i
.operands
> 2 ? 2 : i
.operands
;
5091 for (j
= 0; j
< n
; j
++)
5092 if (update_imm (j
) == 0)
5095 /* The 3rd operand can't be immediate operand. */
5096 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5103 bad_implicit_operand (int xmm
)
5105 const char *ireg
= xmm
? "xmm0" : "ymm0";
5108 as_bad (_("the last operand of `%s' must be `%s%s'"),
5109 i
.tm
.name
, register_prefix
, ireg
);
5111 as_bad (_("the first operand of `%s' must be `%s%s'"),
5112 i
.tm
.name
, register_prefix
, ireg
);
5117 process_operands (void)
5119 /* Default segment register this instruction will use for memory
5120 accesses. 0 means unknown. This is only for optimizing out
5121 unnecessary segment overrides. */
5122 const seg_entry
*default_seg
= 0;
5124 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5126 unsigned int dupl
= i
.operands
;
5127 unsigned int dest
= dupl
- 1;
5130 /* The destination must be an xmm register. */
5131 gas_assert (i
.reg_operands
5132 && MAX_OPERANDS
> dupl
5133 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5135 if (i
.tm
.opcode_modifier
.firstxmm0
)
5137 /* The first operand is implicit and must be xmm0. */
5138 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5139 if (register_number (i
.op
[0].regs
) != 0)
5140 return bad_implicit_operand (1);
5142 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5144 /* Keep xmm0 for instructions with VEX prefix and 3
5150 /* We remove the first xmm0 and keep the number of
5151 operands unchanged, which in fact duplicates the
5153 for (j
= 1; j
< i
.operands
; j
++)
5155 i
.op
[j
- 1] = i
.op
[j
];
5156 i
.types
[j
- 1] = i
.types
[j
];
5157 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5161 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5163 gas_assert ((MAX_OPERANDS
- 1) > dupl
5164 && (i
.tm
.opcode_modifier
.vexsources
5167 /* Add the implicit xmm0 for instructions with VEX prefix
5169 for (j
= i
.operands
; j
> 0; j
--)
5171 i
.op
[j
] = i
.op
[j
- 1];
5172 i
.types
[j
] = i
.types
[j
- 1];
5173 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5176 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5177 i
.types
[0] = regxmm
;
5178 i
.tm
.operand_types
[0] = regxmm
;
5181 i
.reg_operands
+= 2;
5186 i
.op
[dupl
] = i
.op
[dest
];
5187 i
.types
[dupl
] = i
.types
[dest
];
5188 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5197 i
.op
[dupl
] = i
.op
[dest
];
5198 i
.types
[dupl
] = i
.types
[dest
];
5199 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5202 if (i
.tm
.opcode_modifier
.immext
)
5205 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5209 /* The first operand is implicit and must be xmm0/ymm0. */
5210 gas_assert (i
.reg_operands
5211 && (operand_type_equal (&i
.types
[0], ®xmm
)
5212 || operand_type_equal (&i
.types
[0], ®ymm
)));
5213 if (register_number (i
.op
[0].regs
) != 0)
5214 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5216 for (j
= 1; j
< i
.operands
; j
++)
5218 i
.op
[j
- 1] = i
.op
[j
];
5219 i
.types
[j
- 1] = i
.types
[j
];
5221 /* We need to adjust fields in i.tm since they are used by
5222 build_modrm_byte. */
5223 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5230 else if (i
.tm
.opcode_modifier
.regkludge
)
5232 /* The imul $imm, %reg instruction is converted into
5233 imul $imm, %reg, %reg, and the clr %reg instruction
5234 is converted into xor %reg, %reg. */
5236 unsigned int first_reg_op
;
5238 if (operand_type_check (i
.types
[0], reg
))
5242 /* Pretend we saw the extra register operand. */
5243 gas_assert (i
.reg_operands
== 1
5244 && i
.op
[first_reg_op
+ 1].regs
== 0);
5245 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5246 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5251 if (i
.tm
.opcode_modifier
.shortform
)
5253 if (i
.types
[0].bitfield
.sreg2
5254 || i
.types
[0].bitfield
.sreg3
)
5256 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5257 && i
.op
[0].regs
->reg_num
== 1)
5259 as_bad (_("you can't `pop %scs'"), register_prefix
);
5262 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5263 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5268 /* The register or float register operand is in operand
5272 if (i
.types
[0].bitfield
.floatreg
5273 || operand_type_check (i
.types
[0], reg
))
5277 /* Register goes in low 3 bits of opcode. */
5278 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5279 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5281 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5283 /* Warn about some common errors, but press on regardless.
5284 The first case can be generated by gcc (<= 2.8.1). */
5285 if (i
.operands
== 2)
5287 /* Reversed arguments on faddp, fsubp, etc. */
5288 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5289 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5290 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5294 /* Extraneous `l' suffix on fp insn. */
5295 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5296 register_prefix
, i
.op
[0].regs
->reg_name
);
5301 else if (i
.tm
.opcode_modifier
.modrm
)
5303 /* The opcode is completed (modulo i.tm.extension_opcode which
5304 must be put into the modrm byte). Now, we make the modrm and
5305 index base bytes based on all the info we've collected. */
5307 default_seg
= build_modrm_byte ();
5309 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5313 else if (i
.tm
.opcode_modifier
.isstring
)
5315 /* For the string instructions that allow a segment override
5316 on one of their operands, the default segment is ds. */
5320 if (i
.tm
.base_opcode
== 0x8d /* lea */
5323 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5325 /* If a segment was explicitly specified, and the specified segment
5326 is not the default, use an opcode prefix to select it. If we
5327 never figured out what the default segment is, then default_seg
5328 will be zero at this point, and the specified segment prefix will
5330 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5332 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5338 static const seg_entry
*
5339 build_modrm_byte (void)
5341 const seg_entry
*default_seg
= 0;
5342 unsigned int source
, dest
;
5345 /* The first operand of instructions with VEX prefix and 3 sources
5346 must be VEX_Imm4. */
5347 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5350 unsigned int nds
, reg_slot
;
5353 if (i
.tm
.opcode_modifier
.veximmext
5354 && i
.tm
.opcode_modifier
.immext
)
5356 dest
= i
.operands
- 2;
5357 gas_assert (dest
== 3);
5360 dest
= i
.operands
- 1;
5363 /* There are 2 kinds of instructions:
5364 1. 5 operands: 4 register operands or 3 register operands
5365 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5366 VexW0 or VexW1. The destination must be either XMM or YMM
5368 2. 4 operands: 4 register operands or 3 register operands
5369 plus 1 memory operand, VexXDS, and VexImmExt */
5370 gas_assert ((i
.reg_operands
== 4
5371 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5372 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5373 && (i
.tm
.opcode_modifier
.veximmext
5374 || (i
.imm_operands
== 1
5375 && i
.types
[0].bitfield
.vec_imm4
5376 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5377 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5378 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5379 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)))));
5381 if (i
.imm_operands
== 0)
5383 /* When there is no immediate operand, generate an 8bit
5384 immediate operand to encode the first operand. */
5385 exp
= &im_expressions
[i
.imm_operands
++];
5386 i
.op
[i
.operands
].imms
= exp
;
5387 i
.types
[i
.operands
] = imm8
;
5389 /* If VexW1 is set, the first operand is the source and
5390 the second operand is encoded in the immediate operand. */
5391 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5402 /* FMA swaps REG and NDS. */
5403 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5411 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5413 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5415 exp
->X_op
= O_constant
;
5416 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
5420 unsigned int imm_slot
;
5422 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5424 /* If VexW0 is set, the third operand is the source and
5425 the second operand is encoded in the immediate
5432 /* VexW1 is set, the second operand is the source and
5433 the third operand is encoded in the immediate
5439 if (i
.tm
.opcode_modifier
.immext
)
5441 /* When ImmExt is set, the immdiate byte is the last
5443 imm_slot
= i
.operands
- 1;
5451 /* Turn on Imm8 so that output_imm will generate it. */
5452 i
.types
[imm_slot
].bitfield
.imm8
= 1;
5455 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5457 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5459 i
.op
[imm_slot
].imms
->X_add_number
5460 |= register_number (i
.op
[reg_slot
].regs
) << 4;
5463 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
5464 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5466 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5471 /* i.reg_operands MUST be the number of real register operands;
5472 implicit registers do not count. If there are 3 register
5473 operands, it must be a instruction with VexNDS. For a
5474 instruction with VexNDD, the destination register is encoded
5475 in VEX prefix. If there are 4 register operands, it must be
5476 a instruction with VEX prefix and 3 sources. */
5477 if (i
.mem_operands
== 0
5478 && ((i
.reg_operands
== 2
5479 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
5480 || (i
.reg_operands
== 3
5481 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5482 || (i
.reg_operands
== 4 && vex_3_sources
)))
5490 /* When there are 3 operands, one of them may be immediate,
5491 which may be the first or the last operand. Otherwise,
5492 the first operand must be shift count register (cl) or it
5493 is an instruction with VexNDS. */
5494 gas_assert (i
.imm_operands
== 1
5495 || (i
.imm_operands
== 0
5496 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5497 || i
.types
[0].bitfield
.shiftcount
)));
5498 if (operand_type_check (i
.types
[0], imm
)
5499 || i
.types
[0].bitfield
.shiftcount
)
5505 /* When there are 4 operands, the first two must be 8bit
5506 immediate operands. The source operand will be the 3rd
5509 For instructions with VexNDS, if the first operand
5510 an imm8, the source operand is the 2nd one. If the last
5511 operand is imm8, the source operand is the first one. */
5512 gas_assert ((i
.imm_operands
== 2
5513 && i
.types
[0].bitfield
.imm8
5514 && i
.types
[1].bitfield
.imm8
)
5515 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5516 && i
.imm_operands
== 1
5517 && (i
.types
[0].bitfield
.imm8
5518 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5519 if (i
.imm_operands
== 2)
5523 if (i
.types
[0].bitfield
.imm8
)
5539 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5541 /* For instructions with VexNDS, the register-only
5542 source operand must be 32/64bit integer, XMM or
5543 YMM register. It is encoded in VEX prefix. We
5544 need to clear RegMem bit before calling
5545 operand_type_equal. */
5547 i386_operand_type op
;
5550 /* Check register-only source operand when two source
5551 operands are swapped. */
5552 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
5553 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
5561 op
= i
.tm
.operand_types
[vvvv
];
5562 op
.bitfield
.regmem
= 0;
5563 if ((dest
+ 1) >= i
.operands
5564 || (op
.bitfield
.reg32
!= 1
5565 && !op
.bitfield
.reg64
!= 1
5566 && !operand_type_equal (&op
, ®xmm
)
5567 && !operand_type_equal (&op
, ®ymm
)))
5569 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
5575 /* One of the register operands will be encoded in the i.tm.reg
5576 field, the other in the combined i.tm.mode and i.tm.regmem
5577 fields. If no form of this instruction supports a memory
5578 destination operand, then we assume the source operand may
5579 sometimes be a memory operand and so we need to store the
5580 destination in the i.rm.reg field. */
5581 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5582 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5584 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5585 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5586 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5588 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5593 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5594 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5595 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5597 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5600 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5602 if (!i
.types
[0].bitfield
.control
5603 && !i
.types
[1].bitfield
.control
)
5605 i
.rex
&= ~(REX_R
| REX_B
);
5606 add_prefix (LOCK_PREFIX_OPCODE
);
5610 { /* If it's not 2 reg operands... */
5615 unsigned int fake_zero_displacement
= 0;
5618 for (op
= 0; op
< i
.operands
; op
++)
5619 if (operand_type_check (i
.types
[op
], anymem
))
5621 gas_assert (op
< i
.operands
);
5623 if (i
.tm
.opcode_modifier
.vecsib
)
5625 if (i
.index_reg
->reg_num
== RegEiz
5626 || i
.index_reg
->reg_num
== RegRiz
)
5629 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5632 i
.sib
.base
= NO_BASE_REGISTER
;
5633 i
.sib
.scale
= i
.log2_scale_factor
;
5634 i
.types
[op
].bitfield
.disp8
= 0;
5635 i
.types
[op
].bitfield
.disp16
= 0;
5636 i
.types
[op
].bitfield
.disp64
= 0;
5637 if (flag_code
!= CODE_64BIT
)
5639 /* Must be 32 bit */
5640 i
.types
[op
].bitfield
.disp32
= 1;
5641 i
.types
[op
].bitfield
.disp32s
= 0;
5645 i
.types
[op
].bitfield
.disp32
= 0;
5646 i
.types
[op
].bitfield
.disp32s
= 1;
5649 i
.sib
.index
= i
.index_reg
->reg_num
;
5650 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5656 if (i
.base_reg
== 0)
5659 if (!i
.disp_operands
)
5661 fake_zero_displacement
= 1;
5662 /* Instructions with VSIB byte need 32bit displacement
5663 if there is no base register. */
5664 if (i
.tm
.opcode_modifier
.vecsib
)
5665 i
.types
[op
].bitfield
.disp32
= 1;
5667 if (i
.index_reg
== 0)
5669 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5670 /* Operand is just <disp> */
5671 if (flag_code
== CODE_64BIT
)
5673 /* 64bit mode overwrites the 32bit absolute
5674 addressing by RIP relative addressing and
5675 absolute addressing is encoded by one of the
5676 redundant SIB forms. */
5677 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5678 i
.sib
.base
= NO_BASE_REGISTER
;
5679 i
.sib
.index
= NO_INDEX_REGISTER
;
5680 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5681 ? disp32s
: disp32
);
5683 else if ((flag_code
== CODE_16BIT
)
5684 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5686 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5687 i
.types
[op
] = disp16
;
5691 i
.rm
.regmem
= NO_BASE_REGISTER
;
5692 i
.types
[op
] = disp32
;
5695 else if (!i
.tm
.opcode_modifier
.vecsib
)
5697 /* !i.base_reg && i.index_reg */
5698 if (i
.index_reg
->reg_num
== RegEiz
5699 || i
.index_reg
->reg_num
== RegRiz
)
5700 i
.sib
.index
= NO_INDEX_REGISTER
;
5702 i
.sib
.index
= i
.index_reg
->reg_num
;
5703 i
.sib
.base
= NO_BASE_REGISTER
;
5704 i
.sib
.scale
= i
.log2_scale_factor
;
5705 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5706 i
.types
[op
].bitfield
.disp8
= 0;
5707 i
.types
[op
].bitfield
.disp16
= 0;
5708 i
.types
[op
].bitfield
.disp64
= 0;
5709 if (flag_code
!= CODE_64BIT
)
5711 /* Must be 32 bit */
5712 i
.types
[op
].bitfield
.disp32
= 1;
5713 i
.types
[op
].bitfield
.disp32s
= 0;
5717 i
.types
[op
].bitfield
.disp32
= 0;
5718 i
.types
[op
].bitfield
.disp32s
= 1;
5720 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5724 /* RIP addressing for 64bit mode. */
5725 else if (i
.base_reg
->reg_num
== RegRip
||
5726 i
.base_reg
->reg_num
== RegEip
)
5728 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5729 i
.rm
.regmem
= NO_BASE_REGISTER
;
5730 i
.types
[op
].bitfield
.disp8
= 0;
5731 i
.types
[op
].bitfield
.disp16
= 0;
5732 i
.types
[op
].bitfield
.disp32
= 0;
5733 i
.types
[op
].bitfield
.disp32s
= 1;
5734 i
.types
[op
].bitfield
.disp64
= 0;
5735 i
.flags
[op
] |= Operand_PCrel
;
5736 if (! i
.disp_operands
)
5737 fake_zero_displacement
= 1;
5739 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5741 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5742 switch (i
.base_reg
->reg_num
)
5745 if (i
.index_reg
== 0)
5747 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5748 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5752 if (i
.index_reg
== 0)
5755 if (operand_type_check (i
.types
[op
], disp
) == 0)
5757 /* fake (%bp) into 0(%bp) */
5758 i
.types
[op
].bitfield
.disp8
= 1;
5759 fake_zero_displacement
= 1;
5762 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5763 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5765 default: /* (%si) -> 4 or (%di) -> 5 */
5766 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5768 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5770 else /* i.base_reg and 32/64 bit mode */
5772 if (flag_code
== CODE_64BIT
5773 && operand_type_check (i
.types
[op
], disp
))
5775 i386_operand_type temp
;
5776 operand_type_set (&temp
, 0);
5777 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5779 if (i
.prefix
[ADDR_PREFIX
] == 0)
5780 i
.types
[op
].bitfield
.disp32s
= 1;
5782 i
.types
[op
].bitfield
.disp32
= 1;
5785 if (!i
.tm
.opcode_modifier
.vecsib
)
5786 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5787 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5789 i
.sib
.base
= i
.base_reg
->reg_num
;
5790 /* x86-64 ignores REX prefix bit here to avoid decoder
5792 if (!(i
.base_reg
->reg_flags
& RegRex
)
5793 && (i
.base_reg
->reg_num
== EBP_REG_NUM
5794 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
5796 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
5798 fake_zero_displacement
= 1;
5799 i
.types
[op
].bitfield
.disp8
= 1;
5801 i
.sib
.scale
= i
.log2_scale_factor
;
5802 if (i
.index_reg
== 0)
5804 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5805 /* <disp>(%esp) becomes two byte modrm with no index
5806 register. We've already stored the code for esp
5807 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5808 Any base register besides %esp will not use the
5809 extra modrm byte. */
5810 i
.sib
.index
= NO_INDEX_REGISTER
;
5812 else if (!i
.tm
.opcode_modifier
.vecsib
)
5814 if (i
.index_reg
->reg_num
== RegEiz
5815 || i
.index_reg
->reg_num
== RegRiz
)
5816 i
.sib
.index
= NO_INDEX_REGISTER
;
5818 i
.sib
.index
= i
.index_reg
->reg_num
;
5819 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5820 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5825 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5826 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5830 if (!fake_zero_displacement
5834 fake_zero_displacement
= 1;
5835 if (i
.disp_encoding
== disp_encoding_8bit
)
5836 i
.types
[op
].bitfield
.disp8
= 1;
5838 i
.types
[op
].bitfield
.disp32
= 1;
5840 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5844 if (fake_zero_displacement
)
5846 /* Fakes a zero displacement assuming that i.types[op]
5847 holds the correct displacement size. */
5850 gas_assert (i
.op
[op
].disps
== 0);
5851 exp
= &disp_expressions
[i
.disp_operands
++];
5852 i
.op
[op
].disps
= exp
;
5853 exp
->X_op
= O_constant
;
5854 exp
->X_add_number
= 0;
5855 exp
->X_add_symbol
= (symbolS
*) 0;
5856 exp
->X_op_symbol
= (symbolS
*) 0;
5864 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
5866 if (operand_type_check (i
.types
[0], imm
))
5867 i
.vex
.register_specifier
= NULL
;
5870 /* VEX.vvvv encodes one of the sources when the first
5871 operand is not an immediate. */
5872 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5873 i
.vex
.register_specifier
= i
.op
[0].regs
;
5875 i
.vex
.register_specifier
= i
.op
[1].regs
;
5878 /* Destination is a XMM register encoded in the ModRM.reg
5880 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
5881 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
5884 /* ModRM.rm and VEX.B encodes the other source. */
5885 if (!i
.mem_operands
)
5889 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5890 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5892 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
5894 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5898 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
5900 i
.vex
.register_specifier
= i
.op
[2].regs
;
5901 if (!i
.mem_operands
)
5904 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5905 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5909 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5910 (if any) based on i.tm.extension_opcode. Again, we must be
5911 careful to make sure that segment/control/debug/test/MMX
5912 registers are coded into the i.rm.reg field. */
5913 else if (i
.reg_operands
)
5916 unsigned int vex_reg
= ~0;
5918 for (op
= 0; op
< i
.operands
; op
++)
5919 if (i
.types
[op
].bitfield
.reg8
5920 || i
.types
[op
].bitfield
.reg16
5921 || i
.types
[op
].bitfield
.reg32
5922 || i
.types
[op
].bitfield
.reg64
5923 || i
.types
[op
].bitfield
.regmmx
5924 || i
.types
[op
].bitfield
.regxmm
5925 || i
.types
[op
].bitfield
.regymm
5926 || i
.types
[op
].bitfield
.regbnd
5927 || i
.types
[op
].bitfield
.sreg2
5928 || i
.types
[op
].bitfield
.sreg3
5929 || i
.types
[op
].bitfield
.control
5930 || i
.types
[op
].bitfield
.debug
5931 || i
.types
[op
].bitfield
.test
)
5936 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5938 /* For instructions with VexNDS, the register-only
5939 source operand is encoded in VEX prefix. */
5940 gas_assert (mem
!= (unsigned int) ~0);
5945 gas_assert (op
< i
.operands
);
5949 /* Check register-only source operand when two source
5950 operands are swapped. */
5951 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
5952 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
5956 gas_assert (mem
== (vex_reg
+ 1)
5957 && op
< i
.operands
);
5962 gas_assert (vex_reg
< i
.operands
);
5966 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
5968 /* For instructions with VexNDD, the register destination
5969 is encoded in VEX prefix. */
5970 if (i
.mem_operands
== 0)
5972 /* There is no memory operand. */
5973 gas_assert ((op
+ 2) == i
.operands
);
5978 /* There are only 2 operands. */
5979 gas_assert (op
< 2 && i
.operands
== 2);
5984 gas_assert (op
< i
.operands
);
5986 if (vex_reg
!= (unsigned int) ~0)
5988 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
5990 if (type
->bitfield
.reg32
!= 1
5991 && type
->bitfield
.reg64
!= 1
5992 && !operand_type_equal (type
, ®xmm
)
5993 && !operand_type_equal (type
, ®ymm
))
5996 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5999 /* Don't set OP operand twice. */
6002 /* If there is an extension opcode to put here, the
6003 register number must be put into the regmem field. */
6004 if (i
.tm
.extension_opcode
!= None
)
6006 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6007 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6012 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6013 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6018 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6019 must set it to 3 to indicate this is a register operand
6020 in the regmem field. */
6021 if (!i
.mem_operands
)
6025 /* Fill in i.rm.reg field with extension opcode (if any). */
6026 if (i
.tm
.extension_opcode
!= None
)
6027 i
.rm
.reg
= i
.tm
.extension_opcode
;
6033 output_branch (void)
6039 relax_substateT subtype
;
6043 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6044 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6047 if (i
.prefix
[DATA_PREFIX
] != 0)
6053 /* Pentium4 branch hints. */
6054 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6055 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6060 if (i
.prefix
[REX_PREFIX
] != 0)
6066 /* BND prefixed jump. */
6067 if (i
.prefix
[BND_PREFIX
] != 0)
6069 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6073 if (i
.prefixes
!= 0 && !intel_syntax
)
6074 as_warn (_("skipping prefixes on this instruction"));
6076 /* It's always a symbol; End frag & setup for relax.
6077 Make sure there is enough room in this frag for the largest
6078 instruction we may generate in md_convert_frag. This is 2
6079 bytes for the opcode and room for the prefix and largest
6081 frag_grow (prefix
+ 2 + 4);
6082 /* Prefix and 1 opcode byte go in fr_fix. */
6083 p
= frag_more (prefix
+ 1);
6084 if (i
.prefix
[DATA_PREFIX
] != 0)
6085 *p
++ = DATA_PREFIX_OPCODE
;
6086 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6087 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6088 *p
++ = i
.prefix
[SEG_PREFIX
];
6089 if (i
.prefix
[REX_PREFIX
] != 0)
6090 *p
++ = i
.prefix
[REX_PREFIX
];
6091 *p
= i
.tm
.base_opcode
;
6093 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6094 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6095 else if (cpu_arch_flags
.bitfield
.cpui386
)
6096 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6098 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6101 sym
= i
.op
[0].disps
->X_add_symbol
;
6102 off
= i
.op
[0].disps
->X_add_number
;
6104 if (i
.op
[0].disps
->X_op
!= O_constant
6105 && i
.op
[0].disps
->X_op
!= O_symbol
)
6107 /* Handle complex expressions. */
6108 sym
= make_expr_symbol (i
.op
[0].disps
);
6112 /* 1 possible extra opcode + 4 byte displacement go in var part.
6113 Pass reloc in fr_var. */
6114 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6124 if (i
.tm
.opcode_modifier
.jumpbyte
)
6126 /* This is a loop or jecxz type instruction. */
6128 if (i
.prefix
[ADDR_PREFIX
] != 0)
6130 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6133 /* Pentium4 branch hints. */
6134 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6135 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6137 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6146 if (flag_code
== CODE_16BIT
)
6149 if (i
.prefix
[DATA_PREFIX
] != 0)
6151 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6161 if (i
.prefix
[REX_PREFIX
] != 0)
6163 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6167 /* BND prefixed jump. */
6168 if (i
.prefix
[BND_PREFIX
] != 0)
6170 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6174 if (i
.prefixes
!= 0 && !intel_syntax
)
6175 as_warn (_("skipping prefixes on this instruction"));
6177 p
= frag_more (i
.tm
.opcode_length
+ size
);
6178 switch (i
.tm
.opcode_length
)
6181 *p
++ = i
.tm
.base_opcode
>> 8;
6183 *p
++ = i
.tm
.base_opcode
;
6189 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6190 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6192 /* All jumps handled here are signed, but don't use a signed limit
6193 check for 32 and 16 bit jumps as we want to allow wrap around at
6194 4G and 64k respectively. */
6196 fixP
->fx_signed
= 1;
6200 output_interseg_jump (void)
6208 if (flag_code
== CODE_16BIT
)
6212 if (i
.prefix
[DATA_PREFIX
] != 0)
6218 if (i
.prefix
[REX_PREFIX
] != 0)
6228 if (i
.prefixes
!= 0 && !intel_syntax
)
6229 as_warn (_("skipping prefixes on this instruction"));
6231 /* 1 opcode; 2 segment; offset */
6232 p
= frag_more (prefix
+ 1 + 2 + size
);
6234 if (i
.prefix
[DATA_PREFIX
] != 0)
6235 *p
++ = DATA_PREFIX_OPCODE
;
6237 if (i
.prefix
[REX_PREFIX
] != 0)
6238 *p
++ = i
.prefix
[REX_PREFIX
];
6240 *p
++ = i
.tm
.base_opcode
;
6241 if (i
.op
[1].imms
->X_op
== O_constant
)
6243 offsetT n
= i
.op
[1].imms
->X_add_number
;
6246 && !fits_in_unsigned_word (n
)
6247 && !fits_in_signed_word (n
))
6249 as_bad (_("16-bit jump out of range"));
6252 md_number_to_chars (p
, n
, size
);
6255 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6256 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6257 if (i
.op
[0].imms
->X_op
!= O_constant
)
6258 as_bad (_("can't handle non absolute segment in `%s'"),
6260 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6266 fragS
*insn_start_frag
;
6267 offsetT insn_start_off
;
6269 /* Tie dwarf2 debug info to the address at the start of the insn.
6270 We can't do this after the insn has been output as the current
6271 frag may have been closed off. eg. by frag_var. */
6272 dwarf2_emit_insn (0);
6274 insn_start_frag
= frag_now
;
6275 insn_start_off
= frag_now_fix ();
6278 if (i
.tm
.opcode_modifier
.jump
)
6280 else if (i
.tm
.opcode_modifier
.jumpbyte
6281 || i
.tm
.opcode_modifier
.jumpdword
)
6283 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6284 output_interseg_jump ();
6287 /* Output normal instructions here. */
6291 unsigned int prefix
;
6293 /* Since the VEX prefix contains the implicit prefix, we don't
6294 need the explicit prefix. */
6295 if (!i
.tm
.opcode_modifier
.vex
)
6297 switch (i
.tm
.opcode_length
)
6300 if (i
.tm
.base_opcode
& 0xff000000)
6302 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6307 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6309 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6310 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6313 if (prefix
!= REPE_PREFIX_OPCODE
6314 || (i
.prefix
[REP_PREFIX
]
6315 != REPE_PREFIX_OPCODE
))
6316 add_prefix (prefix
);
6319 add_prefix (prefix
);
6328 /* The prefix bytes. */
6329 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6331 FRAG_APPEND_1_CHAR (*q
);
6335 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
6340 /* REX byte is encoded in VEX prefix. */
6344 FRAG_APPEND_1_CHAR (*q
);
6347 /* There should be no other prefixes for instructions
6352 /* Now the VEX prefix. */
6353 p
= frag_more (i
.vex
.length
);
6354 for (j
= 0; j
< i
.vex
.length
; j
++)
6355 p
[j
] = i
.vex
.bytes
[j
];
6358 /* Now the opcode; be careful about word order here! */
6359 if (i
.tm
.opcode_length
== 1)
6361 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
6365 switch (i
.tm
.opcode_length
)
6369 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
6379 /* Put out high byte first: can't use md_number_to_chars! */
6380 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
6381 *p
= i
.tm
.base_opcode
& 0xff;
6384 /* Now the modrm byte and sib byte (if present). */
6385 if (i
.tm
.opcode_modifier
.modrm
)
6387 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
6390 /* If i.rm.regmem == ESP (4)
6391 && i.rm.mode != (Register mode)
6393 ==> need second modrm byte. */
6394 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
6396 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
6397 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
6399 | i
.sib
.scale
<< 6));
6402 if (i
.disp_operands
)
6403 output_disp (insn_start_frag
, insn_start_off
);
6406 output_imm (insn_start_frag
, insn_start_off
);
6412 pi ("" /*line*/, &i
);
6414 #endif /* DEBUG386 */
6417 /* Return the size of the displacement operand N. */
6420 disp_size (unsigned int n
)
6423 if (i
.types
[n
].bitfield
.disp64
)
6425 else if (i
.types
[n
].bitfield
.disp8
)
6427 else if (i
.types
[n
].bitfield
.disp16
)
6432 /* Return the size of the immediate operand N. */
6435 imm_size (unsigned int n
)
6438 if (i
.types
[n
].bitfield
.imm64
)
6440 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6442 else if (i
.types
[n
].bitfield
.imm16
)
6448 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6453 for (n
= 0; n
< i
.operands
; n
++)
6455 if (operand_type_check (i
.types
[n
], disp
))
6457 if (i
.op
[n
].disps
->X_op
== O_constant
)
6459 int size
= disp_size (n
);
6462 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6464 p
= frag_more (size
);
6465 md_number_to_chars (p
, val
, size
);
6469 enum bfd_reloc_code_real reloc_type
;
6470 int size
= disp_size (n
);
6471 int sign
= i
.types
[n
].bitfield
.disp32s
;
6472 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6474 /* We can't have 8 bit displacement here. */
6475 gas_assert (!i
.types
[n
].bitfield
.disp8
);
6477 /* The PC relative address is computed relative
6478 to the instruction boundary, so in case immediate
6479 fields follows, we need to adjust the value. */
6480 if (pcrel
&& i
.imm_operands
)
6485 for (n1
= 0; n1
< i
.operands
; n1
++)
6486 if (operand_type_check (i
.types
[n1
], imm
))
6488 /* Only one immediate is allowed for PC
6489 relative address. */
6490 gas_assert (sz
== 0);
6492 i
.op
[n
].disps
->X_add_number
-= sz
;
6494 /* We should find the immediate. */
6495 gas_assert (sz
!= 0);
6498 p
= frag_more (size
);
6499 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6501 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6502 && (((reloc_type
== BFD_RELOC_32
6503 || reloc_type
== BFD_RELOC_X86_64_32S
6504 || (reloc_type
== BFD_RELOC_64
6506 && (i
.op
[n
].disps
->X_op
== O_symbol
6507 || (i
.op
[n
].disps
->X_op
== O_add
6508 && ((symbol_get_value_expression
6509 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6511 || reloc_type
== BFD_RELOC_32_PCREL
))
6515 if (insn_start_frag
== frag_now
)
6516 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6521 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6522 for (fr
= insn_start_frag
->fr_next
;
6523 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6525 add
+= p
- frag_now
->fr_literal
;
6530 reloc_type
= BFD_RELOC_386_GOTPC
;
6531 i
.op
[n
].imms
->X_add_number
+= add
;
6533 else if (reloc_type
== BFD_RELOC_64
)
6534 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6536 /* Don't do the adjustment for x86-64, as there
6537 the pcrel addressing is relative to the _next_
6538 insn, and that is taken care of in other code. */
6539 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6541 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6542 i
.op
[n
].disps
, pcrel
, reloc_type
);
6549 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6554 for (n
= 0; n
< i
.operands
; n
++)
6556 if (operand_type_check (i
.types
[n
], imm
))
6558 if (i
.op
[n
].imms
->X_op
== O_constant
)
6560 int size
= imm_size (n
);
6563 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6565 p
= frag_more (size
);
6566 md_number_to_chars (p
, val
, size
);
6570 /* Not absolute_section.
6571 Need a 32-bit fixup (don't support 8bit
6572 non-absolute imms). Try to support other
6574 enum bfd_reloc_code_real reloc_type
;
6575 int size
= imm_size (n
);
6578 if (i
.types
[n
].bitfield
.imm32s
6579 && (i
.suffix
== QWORD_MNEM_SUFFIX
6580 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6585 p
= frag_more (size
);
6586 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6588 /* This is tough to explain. We end up with this one if we
6589 * have operands that look like
6590 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6591 * obtain the absolute address of the GOT, and it is strongly
6592 * preferable from a performance point of view to avoid using
6593 * a runtime relocation for this. The actual sequence of
6594 * instructions often look something like:
6599 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6601 * The call and pop essentially return the absolute address
6602 * of the label .L66 and store it in %ebx. The linker itself
6603 * will ultimately change the first operand of the addl so
6604 * that %ebx points to the GOT, but to keep things simple, the
6605 * .o file must have this operand set so that it generates not
6606 * the absolute address of .L66, but the absolute address of
6607 * itself. This allows the linker itself simply treat a GOTPC
6608 * relocation as asking for a pcrel offset to the GOT to be
6609 * added in, and the addend of the relocation is stored in the
6610 * operand field for the instruction itself.
6612 * Our job here is to fix the operand so that it would add
6613 * the correct offset so that %ebx would point to itself. The
6614 * thing that is tricky is that .-.L66 will point to the
6615 * beginning of the instruction, so we need to further modify
6616 * the operand so that it will point to itself. There are
6617 * other cases where you have something like:
6619 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6621 * and here no correction would be required. Internally in
6622 * the assembler we treat operands of this form as not being
6623 * pcrel since the '.' is explicitly mentioned, and I wonder
6624 * whether it would simplify matters to do it this way. Who
6625 * knows. In earlier versions of the PIC patches, the
6626 * pcrel_adjust field was used to store the correction, but
6627 * since the expression is not pcrel, I felt it would be
6628 * confusing to do it this way. */
6630 if ((reloc_type
== BFD_RELOC_32
6631 || reloc_type
== BFD_RELOC_X86_64_32S
6632 || reloc_type
== BFD_RELOC_64
)
6634 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6635 && (i
.op
[n
].imms
->X_op
== O_symbol
6636 || (i
.op
[n
].imms
->X_op
== O_add
6637 && ((symbol_get_value_expression
6638 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6643 if (insn_start_frag
== frag_now
)
6644 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6649 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6650 for (fr
= insn_start_frag
->fr_next
;
6651 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6653 add
+= p
- frag_now
->fr_literal
;
6657 reloc_type
= BFD_RELOC_386_GOTPC
;
6659 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6661 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6662 i
.op
[n
].imms
->X_add_number
+= add
;
6664 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6665 i
.op
[n
].imms
, 0, reloc_type
);
6671 /* x86_cons_fix_new is called via the expression parsing code when a
6672 reloc is needed. We use this hook to get the correct .got reloc. */
6673 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6674 static int cons_sign
= -1;
6677 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6680 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6682 got_reloc
= NO_RELOC
;
6685 if (exp
->X_op
== O_secrel
)
6687 exp
->X_op
= O_symbol
;
6688 r
= BFD_RELOC_32_SECREL
;
6692 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6695 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
6696 purpose of the `.dc.a' internal pseudo-op. */
6699 x86_address_bytes (void)
6701 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
6703 return stdoutput
->arch_info
->bits_per_address
/ 8;
6706 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
6708 # define lex_got(reloc, adjust, types) NULL
6710 /* Parse operands of the form
6711 <symbol>@GOTOFF+<nnn>
6712 and similar .plt or .got references.
6714 If we find one, set up the correct relocation in RELOC and copy the
6715 input string, minus the `@GOTOFF' into a malloc'd buffer for
6716 parsing by the calling routine. Return this buffer, and if ADJUST
6717 is non-null set it to the length of the string we removed from the
6718 input line. Otherwise return NULL. */
6720 lex_got (enum bfd_reloc_code_real
*rel
,
6722 i386_operand_type
*types
)
6724 /* Some of the relocations depend on the size of what field is to
6725 be relocated. But in our callers i386_immediate and i386_displacement
6726 we don't yet know the operand size (this will be set by insn
6727 matching). Hence we record the word32 relocation here,
6728 and adjust the reloc according to the real size in reloc(). */
6729 static const struct {
6732 const enum bfd_reloc_code_real rel
[2];
6733 const i386_operand_type types64
;
6735 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6736 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
6738 OPERAND_TYPE_IMM32_64
},
6740 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
6741 BFD_RELOC_X86_64_PLTOFF64
},
6742 OPERAND_TYPE_IMM64
},
6743 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
6744 BFD_RELOC_X86_64_PLT32
},
6745 OPERAND_TYPE_IMM32_32S_DISP32
},
6746 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
6747 BFD_RELOC_X86_64_GOTPLT64
},
6748 OPERAND_TYPE_IMM64_DISP64
},
6749 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
6750 BFD_RELOC_X86_64_GOTOFF64
},
6751 OPERAND_TYPE_IMM64_DISP64
},
6752 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
6753 BFD_RELOC_X86_64_GOTPCREL
},
6754 OPERAND_TYPE_IMM32_32S_DISP32
},
6755 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
6756 BFD_RELOC_X86_64_TLSGD
},
6757 OPERAND_TYPE_IMM32_32S_DISP32
},
6758 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
6759 _dummy_first_bfd_reloc_code_real
},
6760 OPERAND_TYPE_NONE
},
6761 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
6762 BFD_RELOC_X86_64_TLSLD
},
6763 OPERAND_TYPE_IMM32_32S_DISP32
},
6764 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
6765 BFD_RELOC_X86_64_GOTTPOFF
},
6766 OPERAND_TYPE_IMM32_32S_DISP32
},
6767 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
6768 BFD_RELOC_X86_64_TPOFF32
},
6769 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6770 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
6771 _dummy_first_bfd_reloc_code_real
},
6772 OPERAND_TYPE_NONE
},
6773 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
6774 BFD_RELOC_X86_64_DTPOFF32
},
6775 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6776 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
6777 _dummy_first_bfd_reloc_code_real
},
6778 OPERAND_TYPE_NONE
},
6779 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
6780 _dummy_first_bfd_reloc_code_real
},
6781 OPERAND_TYPE_NONE
},
6782 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
6783 BFD_RELOC_X86_64_GOT32
},
6784 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6785 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
6786 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6787 OPERAND_TYPE_IMM32_32S_DISP32
},
6788 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
6789 BFD_RELOC_X86_64_TLSDESC_CALL
},
6790 OPERAND_TYPE_IMM32_32S_DISP32
},
6795 #if defined (OBJ_MAYBE_ELF)
6800 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6801 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6804 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6806 int len
= gotrel
[j
].len
;
6807 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6809 if (gotrel
[j
].rel
[object_64bit
] != 0)
6812 char *tmpbuf
, *past_reloc
;
6814 *rel
= gotrel
[j
].rel
[object_64bit
];
6818 if (flag_code
!= CODE_64BIT
)
6820 types
->bitfield
.imm32
= 1;
6821 types
->bitfield
.disp32
= 1;
6824 *types
= gotrel
[j
].types64
;
6827 if (j
!= 0 && GOT_symbol
== NULL
)
6828 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6830 /* The length of the first part of our input line. */
6831 first
= cp
- input_line_pointer
;
6833 /* The second part goes from after the reloc token until
6834 (and including) an end_of_line char or comma. */
6835 past_reloc
= cp
+ 1 + len
;
6837 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6839 second
= cp
+ 1 - past_reloc
;
6841 /* Allocate and copy string. The trailing NUL shouldn't
6842 be necessary, but be safe. */
6843 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6844 memcpy (tmpbuf
, input_line_pointer
, first
);
6845 if (second
!= 0 && *past_reloc
!= ' ')
6846 /* Replace the relocation token with ' ', so that
6847 errors like foo@GOTOFF1 will be detected. */
6848 tmpbuf
[first
++] = ' ';
6850 /* Increment length by 1 if the relocation token is
6855 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6856 tmpbuf
[first
+ second
] = '\0';
6860 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6861 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6866 /* Might be a symbol version string. Don't as_bad here. */
6875 /* Parse operands of the form
6876 <symbol>@SECREL32+<nnn>
6878 If we find one, set up the correct relocation in RELOC and copy the
6879 input string, minus the `@SECREL32' into a malloc'd buffer for
6880 parsing by the calling routine. Return this buffer, and if ADJUST
6881 is non-null set it to the length of the string we removed from the
6882 input line. Otherwise return NULL.
6884 This function is copied from the ELF version above adjusted for PE targets. */
6887 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
6888 int *adjust ATTRIBUTE_UNUSED
,
6889 i386_operand_type
*types ATTRIBUTE_UNUSED
)
6895 const enum bfd_reloc_code_real rel
[2];
6896 const i386_operand_type types64
;
6900 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
6901 BFD_RELOC_32_SECREL
},
6902 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6908 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6909 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6912 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6914 int len
= gotrel
[j
].len
;
6916 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6918 if (gotrel
[j
].rel
[object_64bit
] != 0)
6921 char *tmpbuf
, *past_reloc
;
6923 *rel
= gotrel
[j
].rel
[object_64bit
];
6929 if (flag_code
!= CODE_64BIT
)
6931 types
->bitfield
.imm32
= 1;
6932 types
->bitfield
.disp32
= 1;
6935 *types
= gotrel
[j
].types64
;
6938 /* The length of the first part of our input line. */
6939 first
= cp
- input_line_pointer
;
6941 /* The second part goes from after the reloc token until
6942 (and including) an end_of_line char or comma. */
6943 past_reloc
= cp
+ 1 + len
;
6945 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6947 second
= cp
+ 1 - past_reloc
;
6949 /* Allocate and copy string. The trailing NUL shouldn't
6950 be necessary, but be safe. */
6951 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6952 memcpy (tmpbuf
, input_line_pointer
, first
);
6953 if (second
!= 0 && *past_reloc
!= ' ')
6954 /* Replace the relocation token with ' ', so that
6955 errors like foo@SECLREL321 will be detected. */
6956 tmpbuf
[first
++] = ' ';
6957 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6958 tmpbuf
[first
+ second
] = '\0';
6962 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6963 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6968 /* Might be a symbol version string. Don't as_bad here. */
6975 x86_cons (expressionS
*exp
, int size
)
6977 intel_syntax
= -intel_syntax
;
6980 if (size
== 4 || (object_64bit
&& size
== 8))
6982 /* Handle @GOTOFF and the like in an expression. */
6984 char *gotfree_input_line
;
6987 save
= input_line_pointer
;
6988 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6989 if (gotfree_input_line
)
6990 input_line_pointer
= gotfree_input_line
;
6994 if (gotfree_input_line
)
6996 /* expression () has merrily parsed up to the end of line,
6997 or a comma - in the wrong buffer. Transfer how far
6998 input_line_pointer has moved to the right buffer. */
6999 input_line_pointer
= (save
7000 + (input_line_pointer
- gotfree_input_line
)
7002 free (gotfree_input_line
);
7003 if (exp
->X_op
== O_constant
7004 || exp
->X_op
== O_absent
7005 || exp
->X_op
== O_illegal
7006 || exp
->X_op
== O_register
7007 || exp
->X_op
== O_big
)
7009 char c
= *input_line_pointer
;
7010 *input_line_pointer
= 0;
7011 as_bad (_("missing or invalid expression `%s'"), save
);
7012 *input_line_pointer
= c
;
7019 intel_syntax
= -intel_syntax
;
7022 i386_intel_simplify (exp
);
7026 signed_cons (int size
)
7028 if (flag_code
== CODE_64BIT
)
7036 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7043 if (exp
.X_op
== O_symbol
)
7044 exp
.X_op
= O_secrel
;
7046 emit_expr (&exp
, 4);
7048 while (*input_line_pointer
++ == ',');
7050 input_line_pointer
--;
7051 demand_empty_rest_of_line ();
7056 i386_immediate (char *imm_start
)
7058 char *save_input_line_pointer
;
7059 char *gotfree_input_line
;
7062 i386_operand_type types
;
7064 operand_type_set (&types
, ~0);
7066 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7068 as_bad (_("at most %d immediate operands are allowed"),
7069 MAX_IMMEDIATE_OPERANDS
);
7073 exp
= &im_expressions
[i
.imm_operands
++];
7074 i
.op
[this_operand
].imms
= exp
;
7076 if (is_space_char (*imm_start
))
7079 save_input_line_pointer
= input_line_pointer
;
7080 input_line_pointer
= imm_start
;
7082 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7083 if (gotfree_input_line
)
7084 input_line_pointer
= gotfree_input_line
;
7086 exp_seg
= expression (exp
);
7089 if (*input_line_pointer
)
7090 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7092 input_line_pointer
= save_input_line_pointer
;
7093 if (gotfree_input_line
)
7095 free (gotfree_input_line
);
7097 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7098 exp
->X_op
= O_illegal
;
7101 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7105 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7106 i386_operand_type types
, const char *imm_start
)
7108 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7111 as_bad (_("missing or invalid immediate expression `%s'"),
7115 else if (exp
->X_op
== O_constant
)
7117 /* Size it properly later. */
7118 i
.types
[this_operand
].bitfield
.imm64
= 1;
7119 /* If not 64bit, sign extend val. */
7120 if (flag_code
!= CODE_64BIT
7121 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7123 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7125 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7126 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7127 && exp_seg
!= absolute_section
7128 && exp_seg
!= text_section
7129 && exp_seg
!= data_section
7130 && exp_seg
!= bss_section
7131 && exp_seg
!= undefined_section
7132 && !bfd_is_com_section (exp_seg
))
7134 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7138 else if (!intel_syntax
&& exp
->X_op
== O_register
)
7141 as_bad (_("illegal immediate register operand %s"), imm_start
);
7146 /* This is an address. The size of the address will be
7147 determined later, depending on destination register,
7148 suffix, or the default for the section. */
7149 i
.types
[this_operand
].bitfield
.imm8
= 1;
7150 i
.types
[this_operand
].bitfield
.imm16
= 1;
7151 i
.types
[this_operand
].bitfield
.imm32
= 1;
7152 i
.types
[this_operand
].bitfield
.imm32s
= 1;
7153 i
.types
[this_operand
].bitfield
.imm64
= 1;
7154 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7162 i386_scale (char *scale
)
7165 char *save
= input_line_pointer
;
7167 input_line_pointer
= scale
;
7168 val
= get_absolute_expression ();
7173 i
.log2_scale_factor
= 0;
7176 i
.log2_scale_factor
= 1;
7179 i
.log2_scale_factor
= 2;
7182 i
.log2_scale_factor
= 3;
7186 char sep
= *input_line_pointer
;
7188 *input_line_pointer
= '\0';
7189 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7191 *input_line_pointer
= sep
;
7192 input_line_pointer
= save
;
7196 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
7198 as_warn (_("scale factor of %d without an index register"),
7199 1 << i
.log2_scale_factor
);
7200 i
.log2_scale_factor
= 0;
7202 scale
= input_line_pointer
;
7203 input_line_pointer
= save
;
7208 i386_displacement (char *disp_start
, char *disp_end
)
7212 char *save_input_line_pointer
;
7213 char *gotfree_input_line
;
7215 i386_operand_type bigdisp
, types
= anydisp
;
7218 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
7220 as_bad (_("at most %d displacement operands are allowed"),
7221 MAX_MEMORY_OPERANDS
);
7225 operand_type_set (&bigdisp
, 0);
7226 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
7227 || (!current_templates
->start
->opcode_modifier
.jump
7228 && !current_templates
->start
->opcode_modifier
.jumpdword
))
7230 bigdisp
.bitfield
.disp32
= 1;
7231 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
7232 if (flag_code
== CODE_64BIT
)
7236 bigdisp
.bitfield
.disp32s
= 1;
7237 bigdisp
.bitfield
.disp64
= 1;
7240 else if ((flag_code
== CODE_16BIT
) ^ override
)
7242 bigdisp
.bitfield
.disp32
= 0;
7243 bigdisp
.bitfield
.disp16
= 1;
7248 /* For PC-relative branches, the width of the displacement
7249 is dependent upon data size, not address size. */
7250 override
= (i
.prefix
[DATA_PREFIX
] != 0);
7251 if (flag_code
== CODE_64BIT
)
7253 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
7254 bigdisp
.bitfield
.disp16
= 1;
7257 bigdisp
.bitfield
.disp32
= 1;
7258 bigdisp
.bitfield
.disp32s
= 1;
7264 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
7266 : LONG_MNEM_SUFFIX
));
7267 bigdisp
.bitfield
.disp32
= 1;
7268 if ((flag_code
== CODE_16BIT
) ^ override
)
7270 bigdisp
.bitfield
.disp32
= 0;
7271 bigdisp
.bitfield
.disp16
= 1;
7275 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7278 exp
= &disp_expressions
[i
.disp_operands
];
7279 i
.op
[this_operand
].disps
= exp
;
7281 save_input_line_pointer
= input_line_pointer
;
7282 input_line_pointer
= disp_start
;
7283 END_STRING_AND_SAVE (disp_end
);
7285 #ifndef GCC_ASM_O_HACK
7286 #define GCC_ASM_O_HACK 0
7289 END_STRING_AND_SAVE (disp_end
+ 1);
7290 if (i
.types
[this_operand
].bitfield
.baseIndex
7291 && displacement_string_end
[-1] == '+')
7293 /* This hack is to avoid a warning when using the "o"
7294 constraint within gcc asm statements.
7297 #define _set_tssldt_desc(n,addr,limit,type) \
7298 __asm__ __volatile__ ( \
7300 "movw %w1,2+%0\n\t" \
7302 "movb %b1,4+%0\n\t" \
7303 "movb %4,5+%0\n\t" \
7304 "movb $0,6+%0\n\t" \
7305 "movb %h1,7+%0\n\t" \
7307 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
7309 This works great except that the output assembler ends
7310 up looking a bit weird if it turns out that there is
7311 no offset. You end up producing code that looks like:
7324 So here we provide the missing zero. */
7326 *displacement_string_end
= '0';
7329 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7330 if (gotfree_input_line
)
7331 input_line_pointer
= gotfree_input_line
;
7333 exp_seg
= expression (exp
);
7336 if (*input_line_pointer
)
7337 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7339 RESTORE_END_STRING (disp_end
+ 1);
7341 input_line_pointer
= save_input_line_pointer
;
7342 if (gotfree_input_line
)
7344 free (gotfree_input_line
);
7346 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7347 exp
->X_op
= O_illegal
;
7350 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
7352 RESTORE_END_STRING (disp_end
);
7358 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7359 i386_operand_type types
, const char *disp_start
)
7361 i386_operand_type bigdisp
;
7364 /* We do this to make sure that the section symbol is in
7365 the symbol table. We will ultimately change the relocation
7366 to be relative to the beginning of the section. */
7367 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
7368 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
7369 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
7371 if (exp
->X_op
!= O_symbol
)
7374 if (S_IS_LOCAL (exp
->X_add_symbol
)
7375 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
7376 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
7377 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
7378 exp
->X_op
= O_subtract
;
7379 exp
->X_op_symbol
= GOT_symbol
;
7380 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
7381 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
7382 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
7383 i
.reloc
[this_operand
] = BFD_RELOC_64
;
7385 i
.reloc
[this_operand
] = BFD_RELOC_32
;
7388 else if (exp
->X_op
== O_absent
7389 || exp
->X_op
== O_illegal
7390 || exp
->X_op
== O_big
)
7393 as_bad (_("missing or invalid displacement expression `%s'"),
7398 else if (flag_code
== CODE_64BIT
7399 && !i
.prefix
[ADDR_PREFIX
]
7400 && exp
->X_op
== O_constant
)
7402 /* Since displacement is signed extended to 64bit, don't allow
7403 disp32 and turn off disp32s if they are out of range. */
7404 i
.types
[this_operand
].bitfield
.disp32
= 0;
7405 if (!fits_in_signed_long (exp
->X_add_number
))
7407 i
.types
[this_operand
].bitfield
.disp32s
= 0;
7408 if (i
.types
[this_operand
].bitfield
.baseindex
)
7410 as_bad (_("0x%lx out range of signed 32bit displacement"),
7411 (long) exp
->X_add_number
);
7417 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7418 else if (exp
->X_op
!= O_constant
7419 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
7420 && exp_seg
!= absolute_section
7421 && exp_seg
!= text_section
7422 && exp_seg
!= data_section
7423 && exp_seg
!= bss_section
7424 && exp_seg
!= undefined_section
7425 && !bfd_is_com_section (exp_seg
))
7427 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7432 /* Check if this is a displacement only operand. */
7433 bigdisp
= i
.types
[this_operand
];
7434 bigdisp
.bitfield
.disp8
= 0;
7435 bigdisp
.bitfield
.disp16
= 0;
7436 bigdisp
.bitfield
.disp32
= 0;
7437 bigdisp
.bitfield
.disp32s
= 0;
7438 bigdisp
.bitfield
.disp64
= 0;
7439 if (operand_type_all_zero (&bigdisp
))
7440 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7446 /* Make sure the memory operand we've been dealt is valid.
7447 Return 1 on success, 0 on a failure. */
7450 i386_index_check (const char *operand_string
)
7452 const char *kind
= "base/index";
7453 enum flag_code addr_mode
;
7455 if (i
.prefix
[ADDR_PREFIX
])
7456 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
7459 addr_mode
= flag_code
;
7461 #if INFER_ADDR_PREFIX
7462 if (i
.mem_operands
== 0)
7464 /* Infer address prefix from the first memory operand. */
7465 const reg_entry
*addr_reg
= i
.base_reg
;
7467 if (addr_reg
== NULL
)
7468 addr_reg
= i
.index_reg
;
7472 if (addr_reg
->reg_num
== RegEip
7473 || addr_reg
->reg_num
== RegEiz
7474 || addr_reg
->reg_type
.bitfield
.reg32
)
7475 addr_mode
= CODE_32BIT
;
7476 else if (flag_code
!= CODE_64BIT
7477 && addr_reg
->reg_type
.bitfield
.reg16
)
7478 addr_mode
= CODE_16BIT
;
7480 if (addr_mode
!= flag_code
)
7482 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7484 /* Change the size of any displacement too. At most one
7485 of Disp16 or Disp32 is set.
7486 FIXME. There doesn't seem to be any real need for
7487 separate Disp16 and Disp32 flags. The same goes for
7488 Imm16 and Imm32. Removing them would probably clean
7489 up the code quite a lot. */
7490 if (flag_code
!= CODE_64BIT
7491 && (i
.types
[this_operand
].bitfield
.disp16
7492 || i
.types
[this_operand
].bitfield
.disp32
))
7493 i
.types
[this_operand
]
7494 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7501 if (current_templates
->start
->opcode_modifier
.isstring
7502 && !current_templates
->start
->opcode_modifier
.immext
7503 && (current_templates
->end
[-1].opcode_modifier
.isstring
7506 /* Memory operands of string insns are special in that they only allow
7507 a single register (rDI, rSI, or rBX) as their memory address. */
7508 const reg_entry
*expected_reg
;
7509 static const char *di_si
[][2] =
7515 static const char *bx
[] = { "ebx", "bx", "rbx" };
7517 kind
= "string address";
7519 if (current_templates
->start
->opcode_modifier
.w
)
7521 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
7523 if (!type
.bitfield
.baseindex
7524 || ((!i
.mem_operands
!= !intel_syntax
)
7525 && current_templates
->end
[-1].operand_types
[1]
7526 .bitfield
.baseindex
))
7527 type
= current_templates
->end
[-1].operand_types
[1];
7528 expected_reg
= hash_find (reg_hash
,
7529 di_si
[addr_mode
][type
.bitfield
.esseg
]);
7533 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
7535 if (i
.base_reg
!= expected_reg
7537 || operand_type_check (i
.types
[this_operand
], disp
))
7539 /* The second memory operand must have the same size as
7543 && !((addr_mode
== CODE_64BIT
7544 && i
.base_reg
->reg_type
.bitfield
.reg64
)
7545 || (addr_mode
== CODE_32BIT
7546 ? i
.base_reg
->reg_type
.bitfield
.reg32
7547 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
7550 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7552 intel_syntax
? '[' : '(',
7554 expected_reg
->reg_name
,
7555 intel_syntax
? ']' : ')');
7562 as_bad (_("`%s' is not a valid %s expression"),
7563 operand_string
, kind
);
7568 if (addr_mode
!= CODE_16BIT
)
7570 /* 32-bit/64-bit checks. */
7572 && (addr_mode
== CODE_64BIT
7573 ? !i
.base_reg
->reg_type
.bitfield
.reg64
7574 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
7576 || (i
.base_reg
->reg_num
7577 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
7579 && !i
.index_reg
->reg_type
.bitfield
.regxmm
7580 && !i
.index_reg
->reg_type
.bitfield
.regymm
7581 && ((addr_mode
== CODE_64BIT
7582 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
7583 || i
.index_reg
->reg_num
== RegRiz
)
7584 : !(i
.index_reg
->reg_type
.bitfield
.reg32
7585 || i
.index_reg
->reg_num
== RegEiz
))
7586 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7591 /* 16-bit checks. */
7593 && (!i
.base_reg
->reg_type
.bitfield
.reg16
7594 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
7596 && (!i
.index_reg
->reg_type
.bitfield
.reg16
7597 || !i
.index_reg
->reg_type
.bitfield
.baseindex
7599 && i
.base_reg
->reg_num
< 6
7600 && i
.index_reg
->reg_num
>= 6
7601 && i
.log2_scale_factor
== 0))))
7608 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7612 i386_att_operand (char *operand_string
)
7616 char *op_string
= operand_string
;
7618 if (is_space_char (*op_string
))
7621 /* We check for an absolute prefix (differentiating,
7622 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7623 if (*op_string
== ABSOLUTE_PREFIX
)
7626 if (is_space_char (*op_string
))
7628 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7631 /* Check if operand is a register. */
7632 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7634 i386_operand_type temp
;
7636 /* Check for a segment override by searching for ':' after a
7637 segment register. */
7639 if (is_space_char (*op_string
))
7641 if (*op_string
== ':'
7642 && (r
->reg_type
.bitfield
.sreg2
7643 || r
->reg_type
.bitfield
.sreg3
))
7648 i
.seg
[i
.mem_operands
] = &es
;
7651 i
.seg
[i
.mem_operands
] = &cs
;
7654 i
.seg
[i
.mem_operands
] = &ss
;
7657 i
.seg
[i
.mem_operands
] = &ds
;
7660 i
.seg
[i
.mem_operands
] = &fs
;
7663 i
.seg
[i
.mem_operands
] = &gs
;
7667 /* Skip the ':' and whitespace. */
7669 if (is_space_char (*op_string
))
7672 if (!is_digit_char (*op_string
)
7673 && !is_identifier_char (*op_string
)
7674 && *op_string
!= '('
7675 && *op_string
!= ABSOLUTE_PREFIX
)
7677 as_bad (_("bad memory operand `%s'"), op_string
);
7680 /* Handle case of %es:*foo. */
7681 if (*op_string
== ABSOLUTE_PREFIX
)
7684 if (is_space_char (*op_string
))
7686 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7688 goto do_memory_reference
;
7692 as_bad (_("junk `%s' after register"), op_string
);
7696 temp
.bitfield
.baseindex
= 0;
7697 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7699 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7700 i
.op
[this_operand
].regs
= r
;
7703 else if (*op_string
== REGISTER_PREFIX
)
7705 as_bad (_("bad register name `%s'"), op_string
);
7708 else if (*op_string
== IMMEDIATE_PREFIX
)
7711 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7713 as_bad (_("immediate operand illegal with absolute jump"));
7716 if (!i386_immediate (op_string
))
7719 else if (is_digit_char (*op_string
)
7720 || is_identifier_char (*op_string
)
7721 || *op_string
== '(')
7723 /* This is a memory reference of some sort. */
7726 /* Start and end of displacement string expression (if found). */
7727 char *displacement_string_start
;
7728 char *displacement_string_end
;
7730 do_memory_reference
:
7731 if ((i
.mem_operands
== 1
7732 && !current_templates
->start
->opcode_modifier
.isstring
)
7733 || i
.mem_operands
== 2)
7735 as_bad (_("too many memory references for `%s'"),
7736 current_templates
->start
->name
);
7740 /* Check for base index form. We detect the base index form by
7741 looking for an ')' at the end of the operand, searching
7742 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7744 base_string
= op_string
+ strlen (op_string
);
7747 if (is_space_char (*base_string
))
7750 /* If we only have a displacement, set-up for it to be parsed later. */
7751 displacement_string_start
= op_string
;
7752 displacement_string_end
= base_string
+ 1;
7754 if (*base_string
== ')')
7757 unsigned int parens_balanced
= 1;
7758 /* We've already checked that the number of left & right ()'s are
7759 equal, so this loop will not be infinite. */
7763 if (*base_string
== ')')
7765 if (*base_string
== '(')
7768 while (parens_balanced
);
7770 temp_string
= base_string
;
7772 /* Skip past '(' and whitespace. */
7774 if (is_space_char (*base_string
))
7777 if (*base_string
== ','
7778 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7781 displacement_string_end
= temp_string
;
7783 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7787 base_string
= end_op
;
7788 if (is_space_char (*base_string
))
7792 /* There may be an index reg or scale factor here. */
7793 if (*base_string
== ',')
7796 if (is_space_char (*base_string
))
7799 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7802 base_string
= end_op
;
7803 if (is_space_char (*base_string
))
7805 if (*base_string
== ',')
7808 if (is_space_char (*base_string
))
7811 else if (*base_string
!= ')')
7813 as_bad (_("expecting `,' or `)' "
7814 "after index register in `%s'"),
7819 else if (*base_string
== REGISTER_PREFIX
)
7821 end_op
= strchr (base_string
, ',');
7824 as_bad (_("bad register name `%s'"), base_string
);
7828 /* Check for scale factor. */
7829 if (*base_string
!= ')')
7831 char *end_scale
= i386_scale (base_string
);
7836 base_string
= end_scale
;
7837 if (is_space_char (*base_string
))
7839 if (*base_string
!= ')')
7841 as_bad (_("expecting `)' "
7842 "after scale factor in `%s'"),
7847 else if (!i
.index_reg
)
7849 as_bad (_("expecting index register or scale factor "
7850 "after `,'; got '%c'"),
7855 else if (*base_string
!= ')')
7857 as_bad (_("expecting `,' or `)' "
7858 "after base register in `%s'"),
7863 else if (*base_string
== REGISTER_PREFIX
)
7865 end_op
= strchr (base_string
, ',');
7868 as_bad (_("bad register name `%s'"), base_string
);
7873 /* If there's an expression beginning the operand, parse it,
7874 assuming displacement_string_start and
7875 displacement_string_end are meaningful. */
7876 if (displacement_string_start
!= displacement_string_end
)
7878 if (!i386_displacement (displacement_string_start
,
7879 displacement_string_end
))
7883 /* Special case for (%dx) while doing input/output op. */
7885 && operand_type_equal (&i
.base_reg
->reg_type
,
7886 ®16_inoutportreg
)
7888 && i
.log2_scale_factor
== 0
7889 && i
.seg
[i
.mem_operands
] == 0
7890 && !operand_type_check (i
.types
[this_operand
], disp
))
7892 i
.types
[this_operand
] = inoutportreg
;
7896 if (i386_index_check (operand_string
) == 0)
7898 i
.types
[this_operand
].bitfield
.mem
= 1;
7903 /* It's not a memory operand; argh! */
7904 as_bad (_("invalid char %s beginning operand %d `%s'"),
7905 output_invalid (*op_string
),
7910 return 1; /* Normal return. */
7913 /* Calculate the maximum variable size (i.e., excluding fr_fix)
7914 that an rs_machine_dependent frag may reach. */
7917 i386_frag_max_var (fragS
*frag
)
7919 /* The only relaxable frags are for jumps.
7920 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
7921 gas_assert (frag
->fr_type
== rs_machine_dependent
);
7922 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
7925 /* md_estimate_size_before_relax()
7927 Called just before relax() for rs_machine_dependent frags. The x86
7928 assembler uses these frags to handle variable size jump
7931 Any symbol that is now undefined will not become defined.
7932 Return the correct fr_subtype in the frag.
7933 Return the initial "guess for variable size of frag" to caller.
7934 The guess is actually the growth beyond the fixed part. Whatever
7935 we do to grow the fixed or variable part contributes to our
7939 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
7941 /* We've already got fragP->fr_subtype right; all we have to do is
7942 check for un-relaxable symbols. On an ELF system, we can't relax
7943 an externally visible symbol, because it may be overridden by a
7945 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7946 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7948 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7949 || S_IS_WEAK (fragP
->fr_symbol
)
7950 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7951 & BSF_GNU_INDIRECT_FUNCTION
))))
7953 #if defined (OBJ_COFF) && defined (TE_PE)
7954 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7955 && S_IS_WEAK (fragP
->fr_symbol
))
7959 /* Symbol is undefined in this segment, or we need to keep a
7960 reloc so that weak symbols can be overridden. */
7961 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7962 enum bfd_reloc_code_real reloc_type
;
7963 unsigned char *opcode
;
7966 if (fragP
->fr_var
!= NO_RELOC
)
7967 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7969 reloc_type
= BFD_RELOC_16_PCREL
;
7971 reloc_type
= BFD_RELOC_32_PCREL
;
7973 old_fr_fix
= fragP
->fr_fix
;
7974 opcode
= (unsigned char *) fragP
->fr_opcode
;
7976 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7979 /* Make jmp (0xeb) a (d)word displacement jump. */
7981 fragP
->fr_fix
+= size
;
7982 fix_new (fragP
, old_fr_fix
, size
,
7984 fragP
->fr_offset
, 1,
7990 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7992 /* Negate the condition, and branch past an
7993 unconditional jump. */
7996 /* Insert an unconditional jump. */
7998 /* We added two extra opcode bytes, and have a two byte
8000 fragP
->fr_fix
+= 2 + 2;
8001 fix_new (fragP
, old_fr_fix
+ 2, 2,
8003 fragP
->fr_offset
, 1,
8010 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8015 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8017 fragP
->fr_offset
, 1,
8019 fixP
->fx_signed
= 1;
8023 /* This changes the byte-displacement jump 0x7N
8024 to the (d)word-displacement jump 0x0f,0x8N. */
8025 opcode
[1] = opcode
[0] + 0x10;
8026 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8027 /* We've added an opcode byte. */
8028 fragP
->fr_fix
+= 1 + size
;
8029 fix_new (fragP
, old_fr_fix
+ 1, size
,
8031 fragP
->fr_offset
, 1,
8036 BAD_CASE (fragP
->fr_subtype
);
8040 return fragP
->fr_fix
- old_fr_fix
;
8043 /* Guess size depending on current relax state. Initially the relax
8044 state will correspond to a short jump and we return 1, because
8045 the variable part of the frag (the branch offset) is one byte
8046 long. However, we can relax a section more than once and in that
8047 case we must either set fr_subtype back to the unrelaxed state,
8048 or return the value for the appropriate branch. */
8049 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
8052 /* Called after relax() is finished.
8054 In: Address of frag.
8055 fr_type == rs_machine_dependent.
8056 fr_subtype is what the address relaxed to.
8058 Out: Any fixSs and constants are set up.
8059 Caller will turn frag into a ".space 0". */
8062 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
8065 unsigned char *opcode
;
8066 unsigned char *where_to_put_displacement
= NULL
;
8067 offsetT target_address
;
8068 offsetT opcode_address
;
8069 unsigned int extension
= 0;
8070 offsetT displacement_from_opcode_start
;
8072 opcode
= (unsigned char *) fragP
->fr_opcode
;
8074 /* Address we want to reach in file space. */
8075 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
8077 /* Address opcode resides at in file space. */
8078 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
8080 /* Displacement from opcode start to fill into instruction. */
8081 displacement_from_opcode_start
= target_address
- opcode_address
;
8083 if ((fragP
->fr_subtype
& BIG
) == 0)
8085 /* Don't have to change opcode. */
8086 extension
= 1; /* 1 opcode + 1 displacement */
8087 where_to_put_displacement
= &opcode
[1];
8091 if (no_cond_jump_promotion
8092 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
8093 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
8094 _("long jump required"));
8096 switch (fragP
->fr_subtype
)
8098 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
8099 extension
= 4; /* 1 opcode + 4 displacement */
8101 where_to_put_displacement
= &opcode
[1];
8104 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
8105 extension
= 2; /* 1 opcode + 2 displacement */
8107 where_to_put_displacement
= &opcode
[1];
8110 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
8111 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
8112 extension
= 5; /* 2 opcode + 4 displacement */
8113 opcode
[1] = opcode
[0] + 0x10;
8114 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8115 where_to_put_displacement
= &opcode
[2];
8118 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
8119 extension
= 3; /* 2 opcode + 2 displacement */
8120 opcode
[1] = opcode
[0] + 0x10;
8121 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8122 where_to_put_displacement
= &opcode
[2];
8125 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
8130 where_to_put_displacement
= &opcode
[3];
8134 BAD_CASE (fragP
->fr_subtype
);
8139 /* If size if less then four we are sure that the operand fits,
8140 but if it's 4, then it could be that the displacement is larger
8142 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
8144 && ((addressT
) (displacement_from_opcode_start
- extension
8145 + ((addressT
) 1 << 31))
8146 > (((addressT
) 2 << 31) - 1)))
8148 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
8149 _("jump target out of range"));
8150 /* Make us emit 0. */
8151 displacement_from_opcode_start
= extension
;
8153 /* Now put displacement after opcode. */
8154 md_number_to_chars ((char *) where_to_put_displacement
,
8155 (valueT
) (displacement_from_opcode_start
- extension
),
8156 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
8157 fragP
->fr_fix
+= extension
;
8160 /* Apply a fixup (fixP) to segment data, once it has been determined
8161 by our caller that we have all the info we need to fix it up.
8163 Parameter valP is the pointer to the value of the bits.
8165 On the 386, immediates, displacements, and data pointers are all in
8166 the same (little-endian) format, so we don't need to care about which
8170 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
8172 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8173 valueT value
= *valP
;
8175 #if !defined (TE_Mach)
8178 switch (fixP
->fx_r_type
)
8184 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
8187 case BFD_RELOC_X86_64_32S
:
8188 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
8191 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
8194 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
8199 if (fixP
->fx_addsy
!= NULL
8200 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
8201 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
8202 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
8203 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
8204 && !use_rela_relocations
)
8206 /* This is a hack. There should be a better way to handle this.
8207 This covers for the fact that bfd_install_relocation will
8208 subtract the current location (for partial_inplace, PC relative
8209 relocations); see more below. */
8213 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
8216 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8218 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8221 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
8224 || (symbol_section_p (fixP
->fx_addsy
)
8225 && sym_seg
!= absolute_section
))
8226 && !generic_force_reloc (fixP
))
8228 /* Yes, we add the values in twice. This is because
8229 bfd_install_relocation subtracts them out again. I think
8230 bfd_install_relocation is broken, but I don't dare change
8232 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8236 #if defined (OBJ_COFF) && defined (TE_PE)
8237 /* For some reason, the PE format does not store a
8238 section address offset for a PC relative symbol. */
8239 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
8240 || S_IS_WEAK (fixP
->fx_addsy
))
8241 value
+= md_pcrel_from (fixP
);
8244 #if defined (OBJ_COFF) && defined (TE_PE)
8245 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
8247 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8251 /* Fix a few things - the dynamic linker expects certain values here,
8252 and we must not disappoint it. */
8253 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8254 if (IS_ELF
&& fixP
->fx_addsy
)
8255 switch (fixP
->fx_r_type
)
8257 case BFD_RELOC_386_PLT32
:
8258 case BFD_RELOC_X86_64_PLT32
:
8259 /* Make the jump instruction point to the address of the operand. At
8260 runtime we merely add the offset to the actual PLT entry. */
8264 case BFD_RELOC_386_TLS_GD
:
8265 case BFD_RELOC_386_TLS_LDM
:
8266 case BFD_RELOC_386_TLS_IE_32
:
8267 case BFD_RELOC_386_TLS_IE
:
8268 case BFD_RELOC_386_TLS_GOTIE
:
8269 case BFD_RELOC_386_TLS_GOTDESC
:
8270 case BFD_RELOC_X86_64_TLSGD
:
8271 case BFD_RELOC_X86_64_TLSLD
:
8272 case BFD_RELOC_X86_64_GOTTPOFF
:
8273 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8274 value
= 0; /* Fully resolved at runtime. No addend. */
8276 case BFD_RELOC_386_TLS_LE
:
8277 case BFD_RELOC_386_TLS_LDO_32
:
8278 case BFD_RELOC_386_TLS_LE_32
:
8279 case BFD_RELOC_X86_64_DTPOFF32
:
8280 case BFD_RELOC_X86_64_DTPOFF64
:
8281 case BFD_RELOC_X86_64_TPOFF32
:
8282 case BFD_RELOC_X86_64_TPOFF64
:
8283 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8286 case BFD_RELOC_386_TLS_DESC_CALL
:
8287 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8288 value
= 0; /* Fully resolved at runtime. No addend. */
8289 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8293 case BFD_RELOC_386_GOT32
:
8294 case BFD_RELOC_X86_64_GOT32
:
8295 value
= 0; /* Fully resolved at runtime. No addend. */
8298 case BFD_RELOC_VTABLE_INHERIT
:
8299 case BFD_RELOC_VTABLE_ENTRY
:
8306 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
8308 #endif /* !defined (TE_Mach) */
8310 /* Are we finished with this relocation now? */
8311 if (fixP
->fx_addsy
== NULL
)
8313 #if defined (OBJ_COFF) && defined (TE_PE)
8314 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
8317 /* Remember value for tc_gen_reloc. */
8318 fixP
->fx_addnumber
= value
;
8319 /* Clear out the frag for now. */
8323 else if (use_rela_relocations
)
8325 fixP
->fx_no_overflow
= 1;
8326 /* Remember value for tc_gen_reloc. */
8327 fixP
->fx_addnumber
= value
;
8331 md_number_to_chars (p
, value
, fixP
->fx_size
);
8335 md_atof (int type
, char *litP
, int *sizeP
)
8337 /* This outputs the LITTLENUMs in REVERSE order;
8338 in accord with the bigendian 386. */
8339 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
8342 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
8345 output_invalid (int c
)
8348 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
8351 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
8352 "(0x%x)", (unsigned char) c
);
8353 return output_invalid_buf
;
8356 /* REG_STRING starts *before* REGISTER_PREFIX. */
8358 static const reg_entry
*
8359 parse_real_register (char *reg_string
, char **end_op
)
8361 char *s
= reg_string
;
8363 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
8366 /* Skip possible REGISTER_PREFIX and possible whitespace. */
8367 if (*s
== REGISTER_PREFIX
)
8370 if (is_space_char (*s
))
8374 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
8376 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
8377 return (const reg_entry
*) NULL
;
8381 /* For naked regs, make sure that we are not dealing with an identifier.
8382 This prevents confusing an identifier like `eax_var' with register
8384 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
8385 return (const reg_entry
*) NULL
;
8389 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
8391 /* Handle floating point regs, allowing spaces in the (i) part. */
8392 if (r
== i386_regtab
/* %st is first entry of table */)
8394 if (is_space_char (*s
))
8399 if (is_space_char (*s
))
8401 if (*s
>= '0' && *s
<= '7')
8405 if (is_space_char (*s
))
8410 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
8415 /* We have "%st(" then garbage. */
8416 return (const reg_entry
*) NULL
;
8420 if (r
== NULL
|| allow_pseudo_reg
)
8423 if (operand_type_all_zero (&r
->reg_type
))
8424 return (const reg_entry
*) NULL
;
8426 if ((r
->reg_type
.bitfield
.reg32
8427 || r
->reg_type
.bitfield
.sreg3
8428 || r
->reg_type
.bitfield
.control
8429 || r
->reg_type
.bitfield
.debug
8430 || r
->reg_type
.bitfield
.test
)
8431 && !cpu_arch_flags
.bitfield
.cpui386
)
8432 return (const reg_entry
*) NULL
;
8434 if (r
->reg_type
.bitfield
.floatreg
8435 && !cpu_arch_flags
.bitfield
.cpu8087
8436 && !cpu_arch_flags
.bitfield
.cpu287
8437 && !cpu_arch_flags
.bitfield
.cpu387
)
8438 return (const reg_entry
*) NULL
;
8440 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
8441 return (const reg_entry
*) NULL
;
8443 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
8444 return (const reg_entry
*) NULL
;
8446 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
8447 return (const reg_entry
*) NULL
;
8449 /* Don't allow fake index register unless allow_index_reg isn't 0. */
8450 if (!allow_index_reg
8451 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
8452 return (const reg_entry
*) NULL
;
8454 if (((r
->reg_flags
& (RegRex64
| RegRex
))
8455 || r
->reg_type
.bitfield
.reg64
)
8456 && (!cpu_arch_flags
.bitfield
.cpulm
8457 || !operand_type_equal (&r
->reg_type
, &control
))
8458 && flag_code
!= CODE_64BIT
)
8459 return (const reg_entry
*) NULL
;
8461 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
8462 return (const reg_entry
*) NULL
;
8467 /* REG_STRING starts *before* REGISTER_PREFIX. */
8469 static const reg_entry
*
8470 parse_register (char *reg_string
, char **end_op
)
8474 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
8475 r
= parse_real_register (reg_string
, end_op
);
8480 char *save
= input_line_pointer
;
8484 input_line_pointer
= reg_string
;
8485 c
= get_symbol_end ();
8486 symbolP
= symbol_find (reg_string
);
8487 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
8489 const expressionS
*e
= symbol_get_value_expression (symbolP
);
8491 know (e
->X_op
== O_register
);
8492 know (e
->X_add_number
>= 0
8493 && (valueT
) e
->X_add_number
< i386_regtab_size
);
8494 r
= i386_regtab
+ e
->X_add_number
;
8495 *end_op
= input_line_pointer
;
8497 *input_line_pointer
= c
;
8498 input_line_pointer
= save
;
8504 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
8507 char *end
= input_line_pointer
;
8510 r
= parse_register (name
, &input_line_pointer
);
8511 if (r
&& end
<= input_line_pointer
)
8513 *nextcharP
= *input_line_pointer
;
8514 *input_line_pointer
= 0;
8515 e
->X_op
= O_register
;
8516 e
->X_add_number
= r
- i386_regtab
;
8519 input_line_pointer
= end
;
8521 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
8525 md_operand (expressionS
*e
)
8530 switch (*input_line_pointer
)
8532 case REGISTER_PREFIX
:
8533 r
= parse_real_register (input_line_pointer
, &end
);
8536 e
->X_op
= O_register
;
8537 e
->X_add_number
= r
- i386_regtab
;
8538 input_line_pointer
= end
;
8543 gas_assert (intel_syntax
);
8544 end
= input_line_pointer
++;
8546 if (*input_line_pointer
== ']')
8548 ++input_line_pointer
;
8549 e
->X_op_symbol
= make_expr_symbol (e
);
8550 e
->X_add_symbol
= NULL
;
8551 e
->X_add_number
= 0;
8557 input_line_pointer
= end
;
8564 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8565 const char *md_shortopts
= "kVQ:sqn";
8567 const char *md_shortopts
= "qn";
8570 #define OPTION_32 (OPTION_MD_BASE + 0)
8571 #define OPTION_64 (OPTION_MD_BASE + 1)
8572 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
8573 #define OPTION_MARCH (OPTION_MD_BASE + 3)
8574 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
8575 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8576 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8577 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8578 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8579 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
8580 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
8581 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
8582 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
8583 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
8584 #define OPTION_X32 (OPTION_MD_BASE + 14)
8585 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
8587 struct option md_longopts
[] =
8589 {"32", no_argument
, NULL
, OPTION_32
},
8590 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8591 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8592 {"64", no_argument
, NULL
, OPTION_64
},
8594 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8595 {"x32", no_argument
, NULL
, OPTION_X32
},
8597 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
8598 {"march", required_argument
, NULL
, OPTION_MARCH
},
8599 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
8600 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
8601 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
8602 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
8603 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
8604 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
8605 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
8606 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
8607 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
8608 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
8609 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
8610 {NULL
, no_argument
, NULL
, 0}
8612 size_t md_longopts_size
= sizeof (md_longopts
);
8615 md_parse_option (int c
, char *arg
)
8623 optimize_align_code
= 0;
8630 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8631 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8632 should be emitted or not. FIXME: Not implemented. */
8636 /* -V: SVR4 argument to print version ID. */
8638 print_version_id ();
8641 /* -k: Ignore for FreeBSD compatibility. */
8646 /* -s: On i386 Solaris, this tells the native assembler to use
8647 .stab instead of .stab.excl. We always use .stab anyhow. */
8650 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8651 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8654 const char **list
, **l
;
8656 list
= bfd_target_list ();
8657 for (l
= list
; *l
!= NULL
; l
++)
8658 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8659 || strcmp (*l
, "coff-x86-64") == 0
8660 || strcmp (*l
, "pe-x86-64") == 0
8661 || strcmp (*l
, "pei-x86-64") == 0
8662 || strcmp (*l
, "mach-o-x86-64") == 0)
8664 default_arch
= "x86_64";
8668 as_fatal (_("no compiled in support for x86_64"));
8674 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8678 const char **list
, **l
;
8680 list
= bfd_target_list ();
8681 for (l
= list
; *l
!= NULL
; l
++)
8682 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
8684 default_arch
= "x86_64:32";
8688 as_fatal (_("no compiled in support for 32bit x86_64"));
8692 as_fatal (_("32bit x86_64 is only supported for ELF"));
8697 default_arch
= "i386";
8701 #ifdef SVR4_COMMENT_CHARS
8706 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8708 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8712 i386_comment_chars
= n
;
8718 arch
= xstrdup (arg
);
8722 as_fatal (_("invalid -march= option: `%s'"), arg
);
8723 next
= strchr (arch
, '+');
8726 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8728 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
8731 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8734 cpu_arch_name
= cpu_arch
[j
].name
;
8735 cpu_sub_arch_name
= NULL
;
8736 cpu_arch_flags
= cpu_arch
[j
].flags
;
8737 cpu_arch_isa
= cpu_arch
[j
].type
;
8738 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
8739 if (!cpu_arch_tune_set
)
8741 cpu_arch_tune
= cpu_arch_isa
;
8742 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8746 else if (*cpu_arch
[j
].name
== '.'
8747 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
8749 /* ISA entension. */
8750 i386_cpu_flags flags
;
8752 if (!cpu_arch
[j
].negated
)
8753 flags
= cpu_flags_or (cpu_arch_flags
,
8756 flags
= cpu_flags_and_not (cpu_arch_flags
,
8758 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8760 if (cpu_sub_arch_name
)
8762 char *name
= cpu_sub_arch_name
;
8763 cpu_sub_arch_name
= concat (name
,
8765 (const char *) NULL
);
8769 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
8770 cpu_arch_flags
= flags
;
8771 cpu_arch_isa_flags
= flags
;
8777 if (j
>= ARRAY_SIZE (cpu_arch
))
8778 as_fatal (_("invalid -march= option: `%s'"), arg
);
8782 while (next
!= NULL
);
8787 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
8788 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8790 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
8792 cpu_arch_tune_set
= 1;
8793 cpu_arch_tune
= cpu_arch
[j
].type
;
8794 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
8798 if (j
>= ARRAY_SIZE (cpu_arch
))
8799 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
8802 case OPTION_MMNEMONIC
:
8803 if (strcasecmp (arg
, "att") == 0)
8805 else if (strcasecmp (arg
, "intel") == 0)
8808 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
8811 case OPTION_MSYNTAX
:
8812 if (strcasecmp (arg
, "att") == 0)
8814 else if (strcasecmp (arg
, "intel") == 0)
8817 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
8820 case OPTION_MINDEX_REG
:
8821 allow_index_reg
= 1;
8824 case OPTION_MNAKED_REG
:
8825 allow_naked_reg
= 1;
8828 case OPTION_MOLD_GCC
:
8832 case OPTION_MSSE2AVX
:
8836 case OPTION_MSSE_CHECK
:
8837 if (strcasecmp (arg
, "error") == 0)
8838 sse_check
= check_error
;
8839 else if (strcasecmp (arg
, "warning") == 0)
8840 sse_check
= check_warning
;
8841 else if (strcasecmp (arg
, "none") == 0)
8842 sse_check
= check_none
;
8844 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
8847 case OPTION_MOPERAND_CHECK
:
8848 if (strcasecmp (arg
, "error") == 0)
8849 operand_check
= check_error
;
8850 else if (strcasecmp (arg
, "warning") == 0)
8851 operand_check
= check_warning
;
8852 else if (strcasecmp (arg
, "none") == 0)
8853 operand_check
= check_none
;
8855 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
8858 case OPTION_MAVXSCALAR
:
8859 if (strcasecmp (arg
, "128") == 0)
8861 else if (strcasecmp (arg
, "256") == 0)
8864 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
8867 case OPTION_MADD_BND_PREFIX
:
8877 #define MESSAGE_TEMPLATE \
8881 show_arch (FILE *stream
, int ext
, int check
)
8883 static char message
[] = MESSAGE_TEMPLATE
;
8884 char *start
= message
+ 27;
8886 int size
= sizeof (MESSAGE_TEMPLATE
);
8893 left
= size
- (start
- message
);
8894 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8896 /* Should it be skipped? */
8897 if (cpu_arch
[j
].skip
)
8900 name
= cpu_arch
[j
].name
;
8901 len
= cpu_arch
[j
].len
;
8904 /* It is an extension. Skip if we aren't asked to show it. */
8915 /* It is an processor. Skip if we show only extension. */
8918 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8920 /* It is an impossible processor - skip. */
8924 /* Reserve 2 spaces for ", " or ",\0" */
8927 /* Check if there is any room. */
8935 p
= mempcpy (p
, name
, len
);
8939 /* Output the current message now and start a new one. */
8942 fprintf (stream
, "%s\n", message
);
8944 left
= size
- (start
- message
) - len
- 2;
8946 gas_assert (left
>= 0);
8948 p
= mempcpy (p
, name
, len
);
8953 fprintf (stream
, "%s\n", message
);
8957 md_show_usage (FILE *stream
)
8959 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8960 fprintf (stream
, _("\
8962 -V print assembler version number\n\
8965 fprintf (stream
, _("\
8966 -n Do not optimize code alignment\n\
8967 -q quieten some warnings\n"));
8968 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8969 fprintf (stream
, _("\
8972 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8973 || defined (TE_PE) || defined (TE_PEP))
8974 fprintf (stream
, _("\
8975 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
8977 #ifdef SVR4_COMMENT_CHARS
8978 fprintf (stream
, _("\
8979 --divide do not treat `/' as a comment character\n"));
8981 fprintf (stream
, _("\
8982 --divide ignored\n"));
8984 fprintf (stream
, _("\
8985 -march=CPU[,+EXTENSION...]\n\
8986 generate code for CPU and EXTENSION, CPU is one of:\n"));
8987 show_arch (stream
, 0, 1);
8988 fprintf (stream
, _("\
8989 EXTENSION is combination of:\n"));
8990 show_arch (stream
, 1, 0);
8991 fprintf (stream
, _("\
8992 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8993 show_arch (stream
, 0, 0);
8994 fprintf (stream
, _("\
8995 -msse2avx encode SSE instructions with VEX prefix\n"));
8996 fprintf (stream
, _("\
8997 -msse-check=[none|error|warning]\n\
8998 check SSE instructions\n"));
8999 fprintf (stream
, _("\
9000 -moperand-check=[none|error|warning]\n\
9001 check operand combinations for validity\n"));
9002 fprintf (stream
, _("\
9003 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
9005 fprintf (stream
, _("\
9006 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
9007 fprintf (stream
, _("\
9008 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
9009 fprintf (stream
, _("\
9010 -mindex-reg support pseudo index registers\n"));
9011 fprintf (stream
, _("\
9012 -mnaked-reg don't require `%%' prefix for registers\n"));
9013 fprintf (stream
, _("\
9014 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
9015 fprintf (stream
, _("\
9016 -madd-bnd-prefix add BND prefix for all valid branches\n"));
9019 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
9020 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9021 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9023 /* Pick the target format to use. */
9026 i386_target_format (void)
9028 if (!strncmp (default_arch
, "x86_64", 6))
9030 update_code_flag (CODE_64BIT
, 1);
9031 if (default_arch
[6] == '\0')
9032 x86_elf_abi
= X86_64_ABI
;
9034 x86_elf_abi
= X86_64_X32_ABI
;
9036 else if (!strcmp (default_arch
, "i386"))
9037 update_code_flag (CODE_32BIT
, 1);
9039 as_fatal (_("unknown architecture"));
9041 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
9042 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
9043 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
9044 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
9046 switch (OUTPUT_FLAVOR
)
9048 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
9049 case bfd_target_aout_flavour
:
9050 return AOUT_TARGET_FORMAT
;
9052 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
9053 # if defined (TE_PE) || defined (TE_PEP)
9054 case bfd_target_coff_flavour
:
9055 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
9056 # elif defined (TE_GO32)
9057 case bfd_target_coff_flavour
:
9060 case bfd_target_coff_flavour
:
9064 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9065 case bfd_target_elf_flavour
:
9069 switch (x86_elf_abi
)
9072 format
= ELF_TARGET_FORMAT
;
9075 use_rela_relocations
= 1;
9077 format
= ELF_TARGET_FORMAT64
;
9079 case X86_64_X32_ABI
:
9080 use_rela_relocations
= 1;
9082 disallow_64bit_reloc
= 1;
9083 format
= ELF_TARGET_FORMAT32
;
9086 if (cpu_arch_isa
== PROCESSOR_L1OM
)
9088 if (x86_elf_abi
!= X86_64_ABI
)
9089 as_fatal (_("Intel L1OM is 64bit only"));
9090 return ELF_TARGET_L1OM_FORMAT
;
9092 if (cpu_arch_isa
== PROCESSOR_K1OM
)
9094 if (x86_elf_abi
!= X86_64_ABI
)
9095 as_fatal (_("Intel K1OM is 64bit only"));
9096 return ELF_TARGET_K1OM_FORMAT
;
9102 #if defined (OBJ_MACH_O)
9103 case bfd_target_mach_o_flavour
:
9104 if (flag_code
== CODE_64BIT
)
9106 use_rela_relocations
= 1;
9108 return "mach-o-x86-64";
9111 return "mach-o-i386";
9119 #endif /* OBJ_MAYBE_ more than one */
9121 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
9123 i386_elf_emit_arch_note (void)
9125 if (IS_ELF
&& cpu_arch_name
!= NULL
)
9128 asection
*seg
= now_seg
;
9129 subsegT subseg
= now_subseg
;
9130 Elf_Internal_Note i_note
;
9131 Elf_External_Note e_note
;
9132 asection
*note_secp
;
9135 /* Create the .note section. */
9136 note_secp
= subseg_new (".note", 0);
9137 bfd_set_section_flags (stdoutput
,
9139 SEC_HAS_CONTENTS
| SEC_READONLY
);
9141 /* Process the arch string. */
9142 len
= strlen (cpu_arch_name
);
9144 i_note
.namesz
= len
+ 1;
9146 i_note
.type
= NT_ARCH
;
9147 p
= frag_more (sizeof (e_note
.namesz
));
9148 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
9149 p
= frag_more (sizeof (e_note
.descsz
));
9150 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
9151 p
= frag_more (sizeof (e_note
.type
));
9152 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
9153 p
= frag_more (len
+ 1);
9154 strcpy (p
, cpu_arch_name
);
9156 frag_align (2, 0, 0);
9158 subseg_set (seg
, subseg
);
9164 md_undefined_symbol (char *name
)
9166 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
9167 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
9168 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
9169 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
9173 if (symbol_find (name
))
9174 as_bad (_("GOT already in symbol table"));
9175 GOT_symbol
= symbol_new (name
, undefined_section
,
9176 (valueT
) 0, &zero_address_frag
);
9183 /* Round up a section size to the appropriate boundary. */
9186 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
9188 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9189 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
9191 /* For a.out, force the section size to be aligned. If we don't do
9192 this, BFD will align it for us, but it will not write out the
9193 final bytes of the section. This may be a bug in BFD, but it is
9194 easier to fix it here since that is how the other a.out targets
9198 align
= bfd_get_section_alignment (stdoutput
, segment
);
9199 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
9206 /* On the i386, PC-relative offsets are relative to the start of the
9207 next instruction. That is, the address of the offset, plus its
9208 size, since the offset is always the last part of the insn. */
9211 md_pcrel_from (fixS
*fixP
)
9213 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9219 s_bss (int ignore ATTRIBUTE_UNUSED
)
9223 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9225 obj_elf_section_change_hook ();
9227 temp
= get_absolute_expression ();
9228 subseg_set (bss_section
, (subsegT
) temp
);
9229 demand_empty_rest_of_line ();
9235 i386_validate_fix (fixS
*fixp
)
9237 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
9239 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
9243 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
9248 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
9250 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
9257 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
9260 bfd_reloc_code_real_type code
;
9262 switch (fixp
->fx_r_type
)
9264 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9265 case BFD_RELOC_SIZE32
:
9266 case BFD_RELOC_SIZE64
:
9267 if (S_IS_DEFINED (fixp
->fx_addsy
)
9268 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
9270 /* Resolve size relocation against local symbol to size of
9271 the symbol plus addend. */
9272 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
9273 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
9274 && !fits_in_unsigned_long (value
))
9275 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9276 _("symbol size computation overflow"));
9277 fixp
->fx_addsy
= NULL
;
9278 fixp
->fx_subsy
= NULL
;
9279 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
9284 case BFD_RELOC_X86_64_PLT32
:
9285 case BFD_RELOC_X86_64_GOT32
:
9286 case BFD_RELOC_X86_64_GOTPCREL
:
9287 case BFD_RELOC_386_PLT32
:
9288 case BFD_RELOC_386_GOT32
:
9289 case BFD_RELOC_386_GOTOFF
:
9290 case BFD_RELOC_386_GOTPC
:
9291 case BFD_RELOC_386_TLS_GD
:
9292 case BFD_RELOC_386_TLS_LDM
:
9293 case BFD_RELOC_386_TLS_LDO_32
:
9294 case BFD_RELOC_386_TLS_IE_32
:
9295 case BFD_RELOC_386_TLS_IE
:
9296 case BFD_RELOC_386_TLS_GOTIE
:
9297 case BFD_RELOC_386_TLS_LE_32
:
9298 case BFD_RELOC_386_TLS_LE
:
9299 case BFD_RELOC_386_TLS_GOTDESC
:
9300 case BFD_RELOC_386_TLS_DESC_CALL
:
9301 case BFD_RELOC_X86_64_TLSGD
:
9302 case BFD_RELOC_X86_64_TLSLD
:
9303 case BFD_RELOC_X86_64_DTPOFF32
:
9304 case BFD_RELOC_X86_64_DTPOFF64
:
9305 case BFD_RELOC_X86_64_GOTTPOFF
:
9306 case BFD_RELOC_X86_64_TPOFF32
:
9307 case BFD_RELOC_X86_64_TPOFF64
:
9308 case BFD_RELOC_X86_64_GOTOFF64
:
9309 case BFD_RELOC_X86_64_GOTPC32
:
9310 case BFD_RELOC_X86_64_GOT64
:
9311 case BFD_RELOC_X86_64_GOTPCREL64
:
9312 case BFD_RELOC_X86_64_GOTPC64
:
9313 case BFD_RELOC_X86_64_GOTPLT64
:
9314 case BFD_RELOC_X86_64_PLTOFF64
:
9315 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9316 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9318 case BFD_RELOC_VTABLE_ENTRY
:
9319 case BFD_RELOC_VTABLE_INHERIT
:
9321 case BFD_RELOC_32_SECREL
:
9323 code
= fixp
->fx_r_type
;
9325 case BFD_RELOC_X86_64_32S
:
9326 if (!fixp
->fx_pcrel
)
9328 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
9329 code
= fixp
->fx_r_type
;
9335 switch (fixp
->fx_size
)
9338 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9339 _("can not do %d byte pc-relative relocation"),
9341 code
= BFD_RELOC_32_PCREL
;
9343 case 1: code
= BFD_RELOC_8_PCREL
; break;
9344 case 2: code
= BFD_RELOC_16_PCREL
; break;
9345 case 4: code
= BFD_RELOC_32_PCREL
; break;
9347 case 8: code
= BFD_RELOC_64_PCREL
; break;
9353 switch (fixp
->fx_size
)
9356 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9357 _("can not do %d byte relocation"),
9359 code
= BFD_RELOC_32
;
9361 case 1: code
= BFD_RELOC_8
; break;
9362 case 2: code
= BFD_RELOC_16
; break;
9363 case 4: code
= BFD_RELOC_32
; break;
9365 case 8: code
= BFD_RELOC_64
; break;
9372 if ((code
== BFD_RELOC_32
9373 || code
== BFD_RELOC_32_PCREL
9374 || code
== BFD_RELOC_X86_64_32S
)
9376 && fixp
->fx_addsy
== GOT_symbol
)
9379 code
= BFD_RELOC_386_GOTPC
;
9381 code
= BFD_RELOC_X86_64_GOTPC32
;
9383 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
9385 && fixp
->fx_addsy
== GOT_symbol
)
9387 code
= BFD_RELOC_X86_64_GOTPC64
;
9390 rel
= (arelent
*) xmalloc (sizeof (arelent
));
9391 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
9392 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9394 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9396 if (!use_rela_relocations
)
9398 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
9399 vtable entry to be used in the relocation's section offset. */
9400 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
9401 rel
->address
= fixp
->fx_offset
;
9402 #if defined (OBJ_COFF) && defined (TE_PE)
9403 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
9404 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
9409 /* Use the rela in 64bit mode. */
9412 if (disallow_64bit_reloc
)
9415 case BFD_RELOC_X86_64_DTPOFF64
:
9416 case BFD_RELOC_X86_64_TPOFF64
:
9417 case BFD_RELOC_64_PCREL
:
9418 case BFD_RELOC_X86_64_GOTOFF64
:
9419 case BFD_RELOC_X86_64_GOT64
:
9420 case BFD_RELOC_X86_64_GOTPCREL64
:
9421 case BFD_RELOC_X86_64_GOTPC64
:
9422 case BFD_RELOC_X86_64_GOTPLT64
:
9423 case BFD_RELOC_X86_64_PLTOFF64
:
9424 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9425 _("cannot represent relocation type %s in x32 mode"),
9426 bfd_get_reloc_code_name (code
));
9432 if (!fixp
->fx_pcrel
)
9433 rel
->addend
= fixp
->fx_offset
;
9437 case BFD_RELOC_X86_64_PLT32
:
9438 case BFD_RELOC_X86_64_GOT32
:
9439 case BFD_RELOC_X86_64_GOTPCREL
:
9440 case BFD_RELOC_X86_64_TLSGD
:
9441 case BFD_RELOC_X86_64_TLSLD
:
9442 case BFD_RELOC_X86_64_GOTTPOFF
:
9443 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9444 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9445 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
9448 rel
->addend
= (section
->vma
9450 + fixp
->fx_addnumber
9451 + md_pcrel_from (fixp
));
9456 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9457 if (rel
->howto
== NULL
)
9459 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9460 _("cannot represent relocation type %s"),
9461 bfd_get_reloc_code_name (code
));
9462 /* Set howto to a garbage value so that we can keep going. */
9463 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
9464 gas_assert (rel
->howto
!= NULL
);
9470 #include "tc-i386-intel.c"
9473 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
9475 int saved_naked_reg
;
9476 char saved_register_dot
;
9478 saved_naked_reg
= allow_naked_reg
;
9479 allow_naked_reg
= 1;
9480 saved_register_dot
= register_chars
['.'];
9481 register_chars
['.'] = '.';
9482 allow_pseudo_reg
= 1;
9483 expression_and_evaluate (exp
);
9484 allow_pseudo_reg
= 0;
9485 register_chars
['.'] = saved_register_dot
;
9486 allow_naked_reg
= saved_naked_reg
;
9488 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
9490 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
9492 exp
->X_op
= O_constant
;
9493 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
9494 .dw2_regnum
[flag_code
>> 1];
9497 exp
->X_op
= O_illegal
;
9502 tc_x86_frame_initial_instructions (void)
9504 static unsigned int sp_regno
[2];
9506 if (!sp_regno
[flag_code
>> 1])
9508 char *saved_input
= input_line_pointer
;
9509 char sp
[][4] = {"esp", "rsp"};
9512 input_line_pointer
= sp
[flag_code
>> 1];
9513 tc_x86_parse_to_dw2regnum (&exp
);
9514 gas_assert (exp
.X_op
== O_constant
);
9515 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
9516 input_line_pointer
= saved_input
;
9519 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
9520 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
9524 x86_dwarf2_addr_size (void)
9526 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9527 if (x86_elf_abi
== X86_64_X32_ABI
)
9530 return bfd_arch_bits_per_address (stdoutput
) / 8;
9534 i386_elf_section_type (const char *str
, size_t len
)
9536 if (flag_code
== CODE_64BIT
9537 && len
== sizeof ("unwind") - 1
9538 && strncmp (str
, "unwind", 6) == 0)
9539 return SHT_X86_64_UNWIND
;
9546 i386_solaris_fix_up_eh_frame (segT sec
)
9548 if (flag_code
== CODE_64BIT
)
9549 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
9555 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
9559 exp
.X_op
= O_secrel
;
9560 exp
.X_add_symbol
= symbol
;
9561 exp
.X_add_number
= 0;
9562 emit_expr (&exp
, size
);
9566 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9567 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9570 x86_64_section_letter (int letter
, char **ptr_msg
)
9572 if (flag_code
== CODE_64BIT
)
9575 return SHF_X86_64_LARGE
;
9577 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
9580 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
9585 x86_64_section_word (char *str
, size_t len
)
9587 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
9588 return SHF_X86_64_LARGE
;
9594 handle_large_common (int small ATTRIBUTE_UNUSED
)
9596 if (flag_code
!= CODE_64BIT
)
9598 s_comm_internal (0, elf_common_parse
);
9599 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9603 static segT lbss_section
;
9604 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
9605 asection
*saved_bss_section
= bss_section
;
9607 if (lbss_section
== NULL
)
9609 flagword applicable
;
9611 subsegT subseg
= now_subseg
;
9613 /* The .lbss section is for local .largecomm symbols. */
9614 lbss_section
= subseg_new (".lbss", 0);
9615 applicable
= bfd_applicable_section_flags (stdoutput
);
9616 bfd_set_section_flags (stdoutput
, lbss_section
,
9617 applicable
& SEC_ALLOC
);
9618 seg_info (lbss_section
)->bss
= 1;
9620 subseg_set (seg
, subseg
);
9623 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
9624 bss_section
= lbss_section
;
9626 s_comm_internal (0, elf_common_parse
);
9628 elf_com_section_ptr
= saved_com_section_ptr
;
9629 bss_section
= saved_bss_section
;
9632 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */