1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* This struct describes rounding control and SAE in the instruction. */
227 static struct RC_Operation rc_op
;
229 /* The struct describes masking, applied to OPERAND in the instruction.
230 MASK is a pointer to the corresponding mask register. ZEROING tells
231 whether merging or zeroing mask is used. */
232 struct Mask_Operation
234 const reg_entry
*mask
;
235 unsigned int zeroing
;
236 /* The operand where this operation is associated. */
240 static struct Mask_Operation mask_op
;
242 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
244 struct Broadcast_Operation
246 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
249 /* Index of broadcasted operand. */
252 /* Number of bytes to broadcast. */
256 static struct Broadcast_Operation broadcast_op
;
261 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
262 unsigned char bytes
[4];
264 /* Destination or source register specifier. */
265 const reg_entry
*register_specifier
;
268 /* 'md_assemble ()' gathers together information and puts it into a
275 const reg_entry
*regs
;
280 operand_size_mismatch
,
281 operand_type_mismatch
,
282 register_type_mismatch
,
283 number_of_operands_mismatch
,
284 invalid_instruction_suffix
,
286 unsupported_with_intel_mnemonic
,
289 invalid_vsib_address
,
290 invalid_vector_register_set
,
291 unsupported_vector_index_register
,
292 unsupported_broadcast
,
295 mask_not_on_destination
,
298 rc_sae_operand_not_last_imm
,
299 invalid_register_operand
,
304 /* TM holds the template for the insn were currently assembling. */
307 /* SUFFIX holds the instruction size suffix for byte, word, dword
308 or qword, if given. */
311 /* OPERANDS gives the number of given operands. */
312 unsigned int operands
;
314 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
315 of given register, displacement, memory operands and immediate
317 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
319 /* TYPES [i] is the type (see above #defines) which tells us how to
320 use OP[i] for the corresponding operand. */
321 i386_operand_type types
[MAX_OPERANDS
];
323 /* Displacement expression, immediate expression, or register for each
325 union i386_op op
[MAX_OPERANDS
];
327 /* Flags for operands. */
328 unsigned int flags
[MAX_OPERANDS
];
329 #define Operand_PCrel 1
330 #define Operand_Mem 2
332 /* Relocation type for operand */
333 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
335 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
336 the base index byte below. */
337 const reg_entry
*base_reg
;
338 const reg_entry
*index_reg
;
339 unsigned int log2_scale_factor
;
341 /* SEG gives the seg_entries of this insn. They are zero unless
342 explicit segment overrides are given. */
343 const seg_entry
*seg
[2];
345 /* Copied first memory operand string, for re-checking. */
348 /* PREFIX holds all the given prefix opcodes (usually null).
349 PREFIXES is the number of prefix opcodes. */
350 unsigned int prefixes
;
351 unsigned char prefix
[MAX_PREFIXES
];
353 /* Register is in low 3 bits of opcode. */
354 bfd_boolean short_form
;
356 /* The operand to a branch insn indicates an absolute branch. */
357 bfd_boolean jumpabsolute
;
359 /* Has MMX register operands. */
360 bfd_boolean has_regmmx
;
362 /* Has XMM register operands. */
363 bfd_boolean has_regxmm
;
365 /* Has YMM register operands. */
366 bfd_boolean has_regymm
;
368 /* Has ZMM register operands. */
369 bfd_boolean has_regzmm
;
371 /* Has GOTPC or TLS relocation. */
372 bfd_boolean has_gotpc_tls_reloc
;
374 /* RM and SIB are the modrm byte and the sib byte where the
375 addressing modes of this insn are encoded. */
382 /* Masking attributes. */
383 struct Mask_Operation
*mask
;
385 /* Rounding control and SAE attributes. */
386 struct RC_Operation
*rounding
;
388 /* Broadcasting attributes. */
389 struct Broadcast_Operation
*broadcast
;
391 /* Compressed disp8*N attribute. */
392 unsigned int memshift
;
394 /* Prefer load or store in encoding. */
397 dir_encoding_default
= 0,
403 /* Prefer 8bit or 32bit displacement in encoding. */
406 disp_encoding_default
= 0,
411 /* Prefer the REX byte in encoding. */
412 bfd_boolean rex_encoding
;
414 /* Disable instruction size optimization. */
415 bfd_boolean no_optimize
;
417 /* How to encode vector instructions. */
420 vex_encoding_default
= 0,
427 const char *rep_prefix
;
430 const char *hle_prefix
;
432 /* Have BND prefix. */
433 const char *bnd_prefix
;
435 /* Have NOTRACK prefix. */
436 const char *notrack_prefix
;
439 enum i386_error error
;
442 typedef struct _i386_insn i386_insn
;
444 /* Link RC type with corresponding string, that'll be looked for in
453 static const struct RC_name RC_NamesTable
[] =
455 { rne
, STRING_COMMA_LEN ("rn-sae") },
456 { rd
, STRING_COMMA_LEN ("rd-sae") },
457 { ru
, STRING_COMMA_LEN ("ru-sae") },
458 { rz
, STRING_COMMA_LEN ("rz-sae") },
459 { saeonly
, STRING_COMMA_LEN ("sae") },
462 /* List of chars besides those in app.c:symbol_chars that can start an
463 operand. Used to prevent the scrubber eating vital white-space. */
464 const char extra_symbol_chars
[] = "*%-([{}"
473 #if (defined (TE_I386AIX) \
474 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
475 && !defined (TE_GNU) \
476 && !defined (TE_LINUX) \
477 && !defined (TE_NACL) \
478 && !defined (TE_FreeBSD) \
479 && !defined (TE_DragonFly) \
480 && !defined (TE_NetBSD)))
481 /* This array holds the chars that always start a comment. If the
482 pre-processor is disabled, these aren't very useful. The option
483 --divide will remove '/' from this list. */
484 const char *i386_comment_chars
= "#/";
485 #define SVR4_COMMENT_CHARS 1
486 #define PREFIX_SEPARATOR '\\'
489 const char *i386_comment_chars
= "#";
490 #define PREFIX_SEPARATOR '/'
493 /* This array holds the chars that only start a comment at the beginning of
494 a line. If the line seems to have the form '# 123 filename'
495 .line and .file directives will appear in the pre-processed output.
496 Note that input_file.c hand checks for '#' at the beginning of the
497 first line of the input file. This is because the compiler outputs
498 #NO_APP at the beginning of its output.
499 Also note that comments started like this one will always work if
500 '/' isn't otherwise defined. */
501 const char line_comment_chars
[] = "#/";
503 const char line_separator_chars
[] = ";";
505 /* Chars that can be used to separate mant from exp in floating point
507 const char EXP_CHARS
[] = "eE";
509 /* Chars that mean this number is a floating point constant
512 const char FLT_CHARS
[] = "fFdDxX";
514 /* Tables for lexical analysis. */
515 static char mnemonic_chars
[256];
516 static char register_chars
[256];
517 static char operand_chars
[256];
518 static char identifier_chars
[256];
519 static char digit_chars
[256];
521 /* Lexical macros. */
522 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
523 #define is_operand_char(x) (operand_chars[(unsigned char) x])
524 #define is_register_char(x) (register_chars[(unsigned char) x])
525 #define is_space_char(x) ((x) == ' ')
526 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
527 #define is_digit_char(x) (digit_chars[(unsigned char) x])
529 /* All non-digit non-letter characters that may occur in an operand. */
530 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
532 /* md_assemble() always leaves the strings it's passed unaltered. To
533 effect this we maintain a stack of saved characters that we've smashed
534 with '\0's (indicating end of strings for various sub-fields of the
535 assembler instruction). */
536 static char save_stack
[32];
537 static char *save_stack_p
;
538 #define END_STRING_AND_SAVE(s) \
539 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
540 #define RESTORE_END_STRING(s) \
541 do { *(s) = *--save_stack_p; } while (0)
543 /* The instruction we're assembling. */
546 /* Possible templates for current insn. */
547 static const templates
*current_templates
;
549 /* Per instruction expressionS buffers: max displacements & immediates. */
550 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
551 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
553 /* Current operand we are working on. */
554 static int this_operand
= -1;
556 /* We support four different modes. FLAG_CODE variable is used to distinguish
564 static enum flag_code flag_code
;
565 static unsigned int object_64bit
;
566 static unsigned int disallow_64bit_reloc
;
567 static int use_rela_relocations
= 0;
568 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
569 static const char *tls_get_addr
;
571 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
572 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
573 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
575 /* The ELF ABI to use. */
583 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
586 #if defined (TE_PE) || defined (TE_PEP)
587 /* Use big object file format. */
588 static int use_big_obj
= 0;
591 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
592 /* 1 if generating code for a shared library. */
593 static int shared
= 0;
596 /* 1 for intel syntax,
598 static int intel_syntax
= 0;
600 static enum x86_64_isa
602 amd64
= 1, /* AMD64 ISA. */
603 intel64
/* Intel64 ISA. */
606 /* 1 for intel mnemonic,
607 0 if att mnemonic. */
608 static int intel_mnemonic
= !SYSV386_COMPAT
;
610 /* 1 if pseudo registers are permitted. */
611 static int allow_pseudo_reg
= 0;
613 /* 1 if register prefix % not required. */
614 static int allow_naked_reg
= 0;
616 /* 1 if the assembler should add BND prefix for all control-transferring
617 instructions supporting it, even if this prefix wasn't specified
619 static int add_bnd_prefix
= 0;
621 /* 1 if pseudo index register, eiz/riz, is allowed . */
622 static int allow_index_reg
= 0;
624 /* 1 if the assembler should ignore LOCK prefix, even if it was
625 specified explicitly. */
626 static int omit_lock_prefix
= 0;
628 /* 1 if the assembler should encode lfence, mfence, and sfence as
629 "lock addl $0, (%{re}sp)". */
630 static int avoid_fence
= 0;
632 /* Type of the previous instruction. */
647 /* 1 if the assembler should generate relax relocations. */
649 static int generate_relax_relocations
650 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
652 static enum check_kind
658 sse_check
, operand_check
= check_warning
;
660 /* Non-zero if branches should be aligned within power of 2 boundary. */
661 static int align_branch_power
= 0;
663 /* Types of branches to align. */
664 enum align_branch_kind
666 align_branch_none
= 0,
667 align_branch_jcc
= 1,
668 align_branch_fused
= 2,
669 align_branch_jmp
= 3,
670 align_branch_call
= 4,
671 align_branch_indirect
= 5,
675 /* Type bits of branches to align. */
676 enum align_branch_bit
678 align_branch_jcc_bit
= 1 << align_branch_jcc
,
679 align_branch_fused_bit
= 1 << align_branch_fused
,
680 align_branch_jmp_bit
= 1 << align_branch_jmp
,
681 align_branch_call_bit
= 1 << align_branch_call
,
682 align_branch_indirect_bit
= 1 << align_branch_indirect
,
683 align_branch_ret_bit
= 1 << align_branch_ret
686 static unsigned int align_branch
= (align_branch_jcc_bit
687 | align_branch_fused_bit
688 | align_branch_jmp_bit
);
690 /* Types of condition jump used by macro-fusion. */
693 mf_jcc_jo
= 0, /* base opcode 0x70 */
694 mf_jcc_jc
, /* base opcode 0x72 */
695 mf_jcc_je
, /* base opcode 0x74 */
696 mf_jcc_jna
, /* base opcode 0x76 */
697 mf_jcc_js
, /* base opcode 0x78 */
698 mf_jcc_jp
, /* base opcode 0x7a */
699 mf_jcc_jl
, /* base opcode 0x7c */
700 mf_jcc_jle
, /* base opcode 0x7e */
703 /* Types of compare flag-modifying insntructions used by macro-fusion. */
706 mf_cmp_test_and
, /* test/cmp */
707 mf_cmp_alu_cmp
, /* add/sub/cmp */
708 mf_cmp_incdec
/* inc/dec */
711 /* The maximum padding size for fused jcc. CMP like instruction can
712 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
714 #define MAX_FUSED_JCC_PADDING_SIZE 20
716 /* The maximum number of prefixes added for an instruction. */
717 static unsigned int align_branch_prefix_size
= 5;
720 1. Clear the REX_W bit with register operand if possible.
721 2. Above plus use 128bit vector instruction to clear the full vector
724 static int optimize
= 0;
727 1. Clear the REX_W bit with register operand if possible.
728 2. Above plus use 128bit vector instruction to clear the full vector
730 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
733 static int optimize_for_space
= 0;
735 /* Register prefix used for error message. */
736 static const char *register_prefix
= "%";
738 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
739 leave, push, and pop instructions so that gcc has the same stack
740 frame as in 32 bit mode. */
741 static char stackop_size
= '\0';
743 /* Non-zero to optimize code alignment. */
744 int optimize_align_code
= 1;
746 /* Non-zero to quieten some warnings. */
747 static int quiet_warnings
= 0;
750 static const char *cpu_arch_name
= NULL
;
751 static char *cpu_sub_arch_name
= NULL
;
753 /* CPU feature flags. */
754 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
756 /* If we have selected a cpu we are generating instructions for. */
757 static int cpu_arch_tune_set
= 0;
759 /* Cpu we are generating instructions for. */
760 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
762 /* CPU feature flags of cpu we are generating instructions for. */
763 static i386_cpu_flags cpu_arch_tune_flags
;
765 /* CPU instruction set architecture used. */
766 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
768 /* CPU feature flags of instruction set architecture used. */
769 i386_cpu_flags cpu_arch_isa_flags
;
771 /* If set, conditional jumps are not automatically promoted to handle
772 larger than a byte offset. */
773 static unsigned int no_cond_jump_promotion
= 0;
775 /* Encode SSE instructions with VEX prefix. */
776 static unsigned int sse2avx
;
778 /* Encode scalar AVX instructions with specific vector length. */
785 /* Encode VEX WIG instructions with specific vex.w. */
792 /* Encode scalar EVEX LIG instructions with specific vector length. */
800 /* Encode EVEX WIG instructions with specific evex.w. */
807 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
808 static enum rc_type evexrcig
= rne
;
810 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
811 static symbolS
*GOT_symbol
;
813 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
814 unsigned int x86_dwarf2_return_column
;
816 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
817 int x86_cie_data_alignment
;
819 /* Interface to relax_segment.
820 There are 3 major relax states for 386 jump insns because the
821 different types of jumps add different sizes to frags when we're
822 figuring out what sort of jump to choose to reach a given label.
824 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
825 branches which are handled by md_estimate_size_before_relax() and
826 i386_generic_table_relax_frag(). */
829 #define UNCOND_JUMP 0
831 #define COND_JUMP86 2
832 #define BRANCH_PADDING 3
833 #define BRANCH_PREFIX 4
834 #define FUSED_JCC_PADDING 5
839 #define SMALL16 (SMALL | CODE16)
841 #define BIG16 (BIG | CODE16)
845 #define INLINE __inline__
851 #define ENCODE_RELAX_STATE(type, size) \
852 ((relax_substateT) (((type) << 2) | (size)))
853 #define TYPE_FROM_RELAX_STATE(s) \
855 #define DISP_SIZE_FROM_RELAX_STATE(s) \
856 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
858 /* This table is used by relax_frag to promote short jumps to long
859 ones where necessary. SMALL (short) jumps may be promoted to BIG
860 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
861 don't allow a short jump in a 32 bit code segment to be promoted to
862 a 16 bit offset jump because it's slower (requires data size
863 prefix), and doesn't work, unless the destination is in the bottom
864 64k of the code segment (The top 16 bits of eip are zeroed). */
866 const relax_typeS md_relax_table
[] =
869 1) most positive reach of this state,
870 2) most negative reach of this state,
871 3) how many bytes this mode will have in the variable part of the frag
872 4) which index into the table to try if we can't fit into this one. */
874 /* UNCOND_JUMP states. */
875 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
876 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
877 /* dword jmp adds 4 bytes to frag:
878 0 extra opcode bytes, 4 displacement bytes. */
880 /* word jmp adds 2 byte2 to frag:
881 0 extra opcode bytes, 2 displacement bytes. */
884 /* COND_JUMP states. */
885 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
886 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
887 /* dword conditionals adds 5 bytes to frag:
888 1 extra opcode byte, 4 displacement bytes. */
890 /* word conditionals add 3 bytes to frag:
891 1 extra opcode byte, 2 displacement bytes. */
894 /* COND_JUMP86 states. */
895 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
896 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
897 /* dword conditionals adds 5 bytes to frag:
898 1 extra opcode byte, 4 displacement bytes. */
900 /* word conditionals add 4 bytes to frag:
901 1 displacement byte and a 3 byte long branch insn. */
905 static const arch_entry cpu_arch
[] =
907 /* Do not replace the first two entries - i386_target_format()
908 relies on them being there in this order. */
909 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
910 CPU_GENERIC32_FLAGS
, 0 },
911 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
912 CPU_GENERIC64_FLAGS
, 0 },
913 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
915 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
917 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
919 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
921 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
923 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
925 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
927 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
929 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
930 CPU_PENTIUMPRO_FLAGS
, 0 },
931 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
933 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
935 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
937 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
939 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
940 CPU_NOCONA_FLAGS
, 0 },
941 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
943 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
945 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
946 CPU_CORE2_FLAGS
, 1 },
947 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
948 CPU_CORE2_FLAGS
, 0 },
949 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
950 CPU_COREI7_FLAGS
, 0 },
951 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
953 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
955 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
956 CPU_IAMCU_FLAGS
, 0 },
957 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
959 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
961 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
962 CPU_ATHLON_FLAGS
, 0 },
963 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
965 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
967 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
969 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
970 CPU_AMDFAM10_FLAGS
, 0 },
971 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
972 CPU_BDVER1_FLAGS
, 0 },
973 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
974 CPU_BDVER2_FLAGS
, 0 },
975 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
976 CPU_BDVER3_FLAGS
, 0 },
977 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
978 CPU_BDVER4_FLAGS
, 0 },
979 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
980 CPU_ZNVER1_FLAGS
, 0 },
981 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
982 CPU_ZNVER2_FLAGS
, 0 },
983 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
984 CPU_BTVER1_FLAGS
, 0 },
985 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
986 CPU_BTVER2_FLAGS
, 0 },
987 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
989 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
991 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
993 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
995 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
997 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
999 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1001 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1003 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1004 CPU_SSE2_FLAGS
, 0 },
1005 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1006 CPU_SSE3_FLAGS
, 0 },
1007 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1008 CPU_SSE4A_FLAGS
, 0 },
1009 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1010 CPU_SSSE3_FLAGS
, 0 },
1011 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1012 CPU_SSE4_1_FLAGS
, 0 },
1013 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1014 CPU_SSE4_2_FLAGS
, 0 },
1015 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1016 CPU_SSE4_2_FLAGS
, 0 },
1017 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1019 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1020 CPU_AVX2_FLAGS
, 0 },
1021 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1022 CPU_AVX512F_FLAGS
, 0 },
1023 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1024 CPU_AVX512CD_FLAGS
, 0 },
1025 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1026 CPU_AVX512ER_FLAGS
, 0 },
1027 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1028 CPU_AVX512PF_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1030 CPU_AVX512DQ_FLAGS
, 0 },
1031 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1032 CPU_AVX512BW_FLAGS
, 0 },
1033 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1034 CPU_AVX512VL_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1037 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1038 CPU_VMFUNC_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1041 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1042 CPU_XSAVE_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1044 CPU_XSAVEOPT_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1046 CPU_XSAVEC_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1048 CPU_XSAVES_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1051 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1052 CPU_PCLMUL_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1054 CPU_PCLMUL_FLAGS
, 1 },
1055 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1056 CPU_FSGSBASE_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1058 CPU_RDRND_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1060 CPU_F16C_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1062 CPU_BMI2_FLAGS
, 0 },
1063 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1065 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1066 CPU_FMA4_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1069 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1071 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1072 CPU_MOVBE_FLAGS
, 0 },
1073 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1074 CPU_CX16_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1077 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1078 CPU_LZCNT_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1080 CPU_POPCNT_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1083 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1085 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1086 CPU_INVPCID_FLAGS
, 0 },
1087 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1088 CPU_CLFLUSH_FLAGS
, 0 },
1089 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1091 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1092 CPU_SYSCALL_FLAGS
, 0 },
1093 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1094 CPU_RDTSCP_FLAGS
, 0 },
1095 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1096 CPU_3DNOW_FLAGS
, 0 },
1097 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1098 CPU_3DNOWA_FLAGS
, 0 },
1099 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1100 CPU_PADLOCK_FLAGS
, 0 },
1101 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1102 CPU_SVME_FLAGS
, 1 },
1103 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1104 CPU_SVME_FLAGS
, 0 },
1105 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1106 CPU_SSE4A_FLAGS
, 0 },
1107 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1109 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1111 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1113 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1115 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1116 CPU_RDSEED_FLAGS
, 0 },
1117 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1118 CPU_PRFCHW_FLAGS
, 0 },
1119 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1120 CPU_SMAP_FLAGS
, 0 },
1121 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1123 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1125 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1126 CPU_CLFLUSHOPT_FLAGS
, 0 },
1127 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1128 CPU_PREFETCHWT1_FLAGS
, 0 },
1129 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1131 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1132 CPU_CLWB_FLAGS
, 0 },
1133 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1134 CPU_AVX512IFMA_FLAGS
, 0 },
1135 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1136 CPU_AVX512VBMI_FLAGS
, 0 },
1137 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1138 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1139 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1140 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1141 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1142 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1143 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1144 CPU_AVX512_VBMI2_FLAGS
, 0 },
1145 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1146 CPU_AVX512_VNNI_FLAGS
, 0 },
1147 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1148 CPU_AVX512_BITALG_FLAGS
, 0 },
1149 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1150 CPU_CLZERO_FLAGS
, 0 },
1151 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1152 CPU_MWAITX_FLAGS
, 0 },
1153 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1154 CPU_OSPKE_FLAGS
, 0 },
1155 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1156 CPU_RDPID_FLAGS
, 0 },
1157 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1158 CPU_PTWRITE_FLAGS
, 0 },
1159 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1161 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1162 CPU_SHSTK_FLAGS
, 0 },
1163 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1164 CPU_GFNI_FLAGS
, 0 },
1165 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1166 CPU_VAES_FLAGS
, 0 },
1167 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1168 CPU_VPCLMULQDQ_FLAGS
, 0 },
1169 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1170 CPU_WBNOINVD_FLAGS
, 0 },
1171 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1172 CPU_PCONFIG_FLAGS
, 0 },
1173 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1174 CPU_WAITPKG_FLAGS
, 0 },
1175 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1176 CPU_CLDEMOTE_FLAGS
, 0 },
1177 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1178 CPU_MOVDIRI_FLAGS
, 0 },
1179 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1180 CPU_MOVDIR64B_FLAGS
, 0 },
1181 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1182 CPU_AVX512_BF16_FLAGS
, 0 },
1183 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1184 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1185 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1186 CPU_ENQCMD_FLAGS
, 0 },
1187 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1188 CPU_RDPRU_FLAGS
, 0 },
1189 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1190 CPU_MCOMMIT_FLAGS
, 0 },
1193 static const noarch_entry cpu_noarch
[] =
1195 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1196 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1197 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1198 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1199 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1200 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1201 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1202 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1203 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1204 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1205 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1206 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1207 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1208 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1209 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1210 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1211 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1212 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1213 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1214 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1215 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1216 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1217 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1218 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1219 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1220 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1221 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1222 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1223 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1224 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1225 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1226 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1227 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1228 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1229 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1230 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1231 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1232 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1233 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1237 /* Like s_lcomm_internal in gas/read.c but the alignment string
1238 is allowed to be optional. */
1241 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1248 && *input_line_pointer
== ',')
1250 align
= parse_align (needs_align
- 1);
1252 if (align
== (addressT
) -1)
1267 bss_alloc (symbolP
, size
, align
);
1272 pe_lcomm (int needs_align
)
1274 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1278 const pseudo_typeS md_pseudo_table
[] =
1280 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1281 {"align", s_align_bytes
, 0},
1283 {"align", s_align_ptwo
, 0},
1285 {"arch", set_cpu_arch
, 0},
1289 {"lcomm", pe_lcomm
, 1},
1291 {"ffloat", float_cons
, 'f'},
1292 {"dfloat", float_cons
, 'd'},
1293 {"tfloat", float_cons
, 'x'},
1295 {"slong", signed_cons
, 4},
1296 {"noopt", s_ignore
, 0},
1297 {"optim", s_ignore
, 0},
1298 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1299 {"code16", set_code_flag
, CODE_16BIT
},
1300 {"code32", set_code_flag
, CODE_32BIT
},
1302 {"code64", set_code_flag
, CODE_64BIT
},
1304 {"intel_syntax", set_intel_syntax
, 1},
1305 {"att_syntax", set_intel_syntax
, 0},
1306 {"intel_mnemonic", set_intel_mnemonic
, 1},
1307 {"att_mnemonic", set_intel_mnemonic
, 0},
1308 {"allow_index_reg", set_allow_index_reg
, 1},
1309 {"disallow_index_reg", set_allow_index_reg
, 0},
1310 {"sse_check", set_check
, 0},
1311 {"operand_check", set_check
, 1},
1312 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1313 {"largecomm", handle_large_common
, 0},
1315 {"file", dwarf2_directive_file
, 0},
1316 {"loc", dwarf2_directive_loc
, 0},
1317 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1320 {"secrel32", pe_directive_secrel
, 0},
1325 /* For interface with expression (). */
1326 extern char *input_line_pointer
;
1328 /* Hash table for instruction mnemonic lookup. */
1329 static struct hash_control
*op_hash
;
1331 /* Hash table for register lookup. */
1332 static struct hash_control
*reg_hash
;
1334 /* Various efficient no-op patterns for aligning code labels.
1335 Note: Don't try to assemble the instructions in the comments.
1336 0L and 0w are not legal. */
1337 static const unsigned char f32_1
[] =
1339 static const unsigned char f32_2
[] =
1340 {0x66,0x90}; /* xchg %ax,%ax */
1341 static const unsigned char f32_3
[] =
1342 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1343 static const unsigned char f32_4
[] =
1344 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1345 static const unsigned char f32_6
[] =
1346 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1347 static const unsigned char f32_7
[] =
1348 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1349 static const unsigned char f16_3
[] =
1350 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1351 static const unsigned char f16_4
[] =
1352 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1353 static const unsigned char jump_disp8
[] =
1354 {0xeb}; /* jmp disp8 */
1355 static const unsigned char jump32_disp32
[] =
1356 {0xe9}; /* jmp disp32 */
1357 static const unsigned char jump16_disp32
[] =
1358 {0x66,0xe9}; /* jmp disp32 */
1359 /* 32-bit NOPs patterns. */
1360 static const unsigned char *const f32_patt
[] = {
1361 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1363 /* 16-bit NOPs patterns. */
1364 static const unsigned char *const f16_patt
[] = {
1365 f32_1
, f32_2
, f16_3
, f16_4
1367 /* nopl (%[re]ax) */
1368 static const unsigned char alt_3
[] =
1370 /* nopl 0(%[re]ax) */
1371 static const unsigned char alt_4
[] =
1372 {0x0f,0x1f,0x40,0x00};
1373 /* nopl 0(%[re]ax,%[re]ax,1) */
1374 static const unsigned char alt_5
[] =
1375 {0x0f,0x1f,0x44,0x00,0x00};
1376 /* nopw 0(%[re]ax,%[re]ax,1) */
1377 static const unsigned char alt_6
[] =
1378 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1379 /* nopl 0L(%[re]ax) */
1380 static const unsigned char alt_7
[] =
1381 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1382 /* nopl 0L(%[re]ax,%[re]ax,1) */
1383 static const unsigned char alt_8
[] =
1384 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1385 /* nopw 0L(%[re]ax,%[re]ax,1) */
1386 static const unsigned char alt_9
[] =
1387 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1388 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1389 static const unsigned char alt_10
[] =
1390 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1391 /* data16 nopw %cs:0L(%eax,%eax,1) */
1392 static const unsigned char alt_11
[] =
1393 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1394 /* 32-bit and 64-bit NOPs patterns. */
1395 static const unsigned char *const alt_patt
[] = {
1396 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1397 alt_9
, alt_10
, alt_11
1400 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1401 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1404 i386_output_nops (char *where
, const unsigned char *const *patt
,
1405 int count
, int max_single_nop_size
)
1408 /* Place the longer NOP first. */
1411 const unsigned char *nops
;
1413 if (max_single_nop_size
< 1)
1415 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1416 max_single_nop_size
);
1420 nops
= patt
[max_single_nop_size
- 1];
1422 /* Use the smaller one if the requsted one isn't available. */
1425 max_single_nop_size
--;
1426 nops
= patt
[max_single_nop_size
- 1];
1429 last
= count
% max_single_nop_size
;
1432 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1433 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1437 nops
= patt
[last
- 1];
1440 /* Use the smaller one plus one-byte NOP if the needed one
1443 nops
= patt
[last
- 1];
1444 memcpy (where
+ offset
, nops
, last
);
1445 where
[offset
+ last
] = *patt
[0];
1448 memcpy (where
+ offset
, nops
, last
);
1453 fits_in_imm7 (offsetT num
)
1455 return (num
& 0x7f) == num
;
1459 fits_in_imm31 (offsetT num
)
1461 return (num
& 0x7fffffff) == num
;
1464 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1465 single NOP instruction LIMIT. */
1468 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1470 const unsigned char *const *patt
= NULL
;
1471 int max_single_nop_size
;
1472 /* Maximum number of NOPs before switching to jump over NOPs. */
1473 int max_number_of_nops
;
1475 switch (fragP
->fr_type
)
1480 case rs_machine_dependent
:
1481 /* Allow NOP padding for jumps and calls. */
1482 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1483 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1490 /* We need to decide which NOP sequence to use for 32bit and
1491 64bit. When -mtune= is used:
1493 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1494 PROCESSOR_GENERIC32, f32_patt will be used.
1495 2. For the rest, alt_patt will be used.
1497 When -mtune= isn't used, alt_patt will be used if
1498 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1501 When -march= or .arch is used, we can't use anything beyond
1502 cpu_arch_isa_flags. */
1504 if (flag_code
== CODE_16BIT
)
1507 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1508 /* Limit number of NOPs to 2 in 16-bit mode. */
1509 max_number_of_nops
= 2;
1513 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1515 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1516 switch (cpu_arch_tune
)
1518 case PROCESSOR_UNKNOWN
:
1519 /* We use cpu_arch_isa_flags to check if we SHOULD
1520 optimize with nops. */
1521 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1526 case PROCESSOR_PENTIUM4
:
1527 case PROCESSOR_NOCONA
:
1528 case PROCESSOR_CORE
:
1529 case PROCESSOR_CORE2
:
1530 case PROCESSOR_COREI7
:
1531 case PROCESSOR_L1OM
:
1532 case PROCESSOR_K1OM
:
1533 case PROCESSOR_GENERIC64
:
1535 case PROCESSOR_ATHLON
:
1537 case PROCESSOR_AMDFAM10
:
1539 case PROCESSOR_ZNVER
:
1543 case PROCESSOR_I386
:
1544 case PROCESSOR_I486
:
1545 case PROCESSOR_PENTIUM
:
1546 case PROCESSOR_PENTIUMPRO
:
1547 case PROCESSOR_IAMCU
:
1548 case PROCESSOR_GENERIC32
:
1555 switch (fragP
->tc_frag_data
.tune
)
1557 case PROCESSOR_UNKNOWN
:
1558 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1559 PROCESSOR_UNKNOWN. */
1563 case PROCESSOR_I386
:
1564 case PROCESSOR_I486
:
1565 case PROCESSOR_PENTIUM
:
1566 case PROCESSOR_IAMCU
:
1568 case PROCESSOR_ATHLON
:
1570 case PROCESSOR_AMDFAM10
:
1572 case PROCESSOR_ZNVER
:
1574 case PROCESSOR_GENERIC32
:
1575 /* We use cpu_arch_isa_flags to check if we CAN optimize
1577 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1582 case PROCESSOR_PENTIUMPRO
:
1583 case PROCESSOR_PENTIUM4
:
1584 case PROCESSOR_NOCONA
:
1585 case PROCESSOR_CORE
:
1586 case PROCESSOR_CORE2
:
1587 case PROCESSOR_COREI7
:
1588 case PROCESSOR_L1OM
:
1589 case PROCESSOR_K1OM
:
1590 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1595 case PROCESSOR_GENERIC64
:
1601 if (patt
== f32_patt
)
1603 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1604 /* Limit number of NOPs to 2 for older processors. */
1605 max_number_of_nops
= 2;
1609 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1610 /* Limit number of NOPs to 7 for newer processors. */
1611 max_number_of_nops
= 7;
1616 limit
= max_single_nop_size
;
1618 if (fragP
->fr_type
== rs_fill_nop
)
1620 /* Output NOPs for .nop directive. */
1621 if (limit
> max_single_nop_size
)
1623 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1624 _("invalid single nop size: %d "
1625 "(expect within [0, %d])"),
1626 limit
, max_single_nop_size
);
1630 else if (fragP
->fr_type
!= rs_machine_dependent
)
1631 fragP
->fr_var
= count
;
1633 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1635 /* Generate jump over NOPs. */
1636 offsetT disp
= count
- 2;
1637 if (fits_in_imm7 (disp
))
1639 /* Use "jmp disp8" if possible. */
1641 where
[0] = jump_disp8
[0];
1647 unsigned int size_of_jump
;
1649 if (flag_code
== CODE_16BIT
)
1651 where
[0] = jump16_disp32
[0];
1652 where
[1] = jump16_disp32
[1];
1657 where
[0] = jump32_disp32
[0];
1661 count
-= size_of_jump
+ 4;
1662 if (!fits_in_imm31 (count
))
1664 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1665 _("jump over nop padding out of range"));
1669 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1670 where
+= size_of_jump
+ 4;
1674 /* Generate multiple NOPs. */
1675 i386_output_nops (where
, patt
, count
, limit
);
1679 operand_type_all_zero (const union i386_operand_type
*x
)
1681 switch (ARRAY_SIZE(x
->array
))
1692 return !x
->array
[0];
1699 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1701 switch (ARRAY_SIZE(x
->array
))
1717 x
->bitfield
.class = ClassNone
;
1718 x
->bitfield
.instance
= InstanceNone
;
1722 operand_type_equal (const union i386_operand_type
*x
,
1723 const union i386_operand_type
*y
)
1725 switch (ARRAY_SIZE(x
->array
))
1728 if (x
->array
[2] != y
->array
[2])
1732 if (x
->array
[1] != y
->array
[1])
1736 return x
->array
[0] == y
->array
[0];
1744 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1746 switch (ARRAY_SIZE(x
->array
))
1761 return !x
->array
[0];
1768 cpu_flags_equal (const union i386_cpu_flags
*x
,
1769 const union i386_cpu_flags
*y
)
1771 switch (ARRAY_SIZE(x
->array
))
1774 if (x
->array
[3] != y
->array
[3])
1778 if (x
->array
[2] != y
->array
[2])
1782 if (x
->array
[1] != y
->array
[1])
1786 return x
->array
[0] == y
->array
[0];
1794 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1796 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1797 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1800 static INLINE i386_cpu_flags
1801 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1803 switch (ARRAY_SIZE (x
.array
))
1806 x
.array
[3] &= y
.array
[3];
1809 x
.array
[2] &= y
.array
[2];
1812 x
.array
[1] &= y
.array
[1];
1815 x
.array
[0] &= y
.array
[0];
1823 static INLINE i386_cpu_flags
1824 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1826 switch (ARRAY_SIZE (x
.array
))
1829 x
.array
[3] |= y
.array
[3];
1832 x
.array
[2] |= y
.array
[2];
1835 x
.array
[1] |= y
.array
[1];
1838 x
.array
[0] |= y
.array
[0];
1846 static INLINE i386_cpu_flags
1847 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1849 switch (ARRAY_SIZE (x
.array
))
1852 x
.array
[3] &= ~y
.array
[3];
1855 x
.array
[2] &= ~y
.array
[2];
1858 x
.array
[1] &= ~y
.array
[1];
1861 x
.array
[0] &= ~y
.array
[0];
1869 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1871 #define CPU_FLAGS_ARCH_MATCH 0x1
1872 #define CPU_FLAGS_64BIT_MATCH 0x2
1874 #define CPU_FLAGS_PERFECT_MATCH \
1875 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1877 /* Return CPU flags match bits. */
1880 cpu_flags_match (const insn_template
*t
)
1882 i386_cpu_flags x
= t
->cpu_flags
;
1883 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1885 x
.bitfield
.cpu64
= 0;
1886 x
.bitfield
.cpuno64
= 0;
1888 if (cpu_flags_all_zero (&x
))
1890 /* This instruction is available on all archs. */
1891 match
|= CPU_FLAGS_ARCH_MATCH
;
1895 /* This instruction is available only on some archs. */
1896 i386_cpu_flags cpu
= cpu_arch_flags
;
1898 /* AVX512VL is no standalone feature - match it and then strip it. */
1899 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1901 x
.bitfield
.cpuavx512vl
= 0;
1903 cpu
= cpu_flags_and (x
, cpu
);
1904 if (!cpu_flags_all_zero (&cpu
))
1906 if (x
.bitfield
.cpuavx
)
1908 /* We need to check a few extra flags with AVX. */
1909 if (cpu
.bitfield
.cpuavx
1910 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1911 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1912 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1913 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1914 match
|= CPU_FLAGS_ARCH_MATCH
;
1916 else if (x
.bitfield
.cpuavx512f
)
1918 /* We need to check a few extra flags with AVX512F. */
1919 if (cpu
.bitfield
.cpuavx512f
1920 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1921 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1922 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1923 match
|= CPU_FLAGS_ARCH_MATCH
;
1926 match
|= CPU_FLAGS_ARCH_MATCH
;
1932 static INLINE i386_operand_type
1933 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1935 if (x
.bitfield
.class != y
.bitfield
.class)
1936 x
.bitfield
.class = ClassNone
;
1937 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1938 x
.bitfield
.instance
= InstanceNone
;
1940 switch (ARRAY_SIZE (x
.array
))
1943 x
.array
[2] &= y
.array
[2];
1946 x
.array
[1] &= y
.array
[1];
1949 x
.array
[0] &= y
.array
[0];
1957 static INLINE i386_operand_type
1958 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1960 gas_assert (y
.bitfield
.class == ClassNone
);
1961 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1963 switch (ARRAY_SIZE (x
.array
))
1966 x
.array
[2] &= ~y
.array
[2];
1969 x
.array
[1] &= ~y
.array
[1];
1972 x
.array
[0] &= ~y
.array
[0];
1980 static INLINE i386_operand_type
1981 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1983 gas_assert (x
.bitfield
.class == ClassNone
||
1984 y
.bitfield
.class == ClassNone
||
1985 x
.bitfield
.class == y
.bitfield
.class);
1986 gas_assert (x
.bitfield
.instance
== InstanceNone
||
1987 y
.bitfield
.instance
== InstanceNone
||
1988 x
.bitfield
.instance
== y
.bitfield
.instance
);
1990 switch (ARRAY_SIZE (x
.array
))
1993 x
.array
[2] |= y
.array
[2];
1996 x
.array
[1] |= y
.array
[1];
1999 x
.array
[0] |= y
.array
[0];
2007 static INLINE i386_operand_type
2008 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2010 gas_assert (y
.bitfield
.class == ClassNone
);
2011 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2013 switch (ARRAY_SIZE (x
.array
))
2016 x
.array
[2] ^= y
.array
[2];
2019 x
.array
[1] ^= y
.array
[1];
2022 x
.array
[0] ^= y
.array
[0];
2030 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2031 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2032 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2033 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2034 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2035 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2036 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2037 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2038 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2039 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2040 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2041 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2042 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2043 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2044 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2045 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2046 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2057 operand_type_check (i386_operand_type t
, enum operand_type c
)
2062 return t
.bitfield
.class == Reg
;
2065 return (t
.bitfield
.imm8
2069 || t
.bitfield
.imm32s
2070 || t
.bitfield
.imm64
);
2073 return (t
.bitfield
.disp8
2074 || t
.bitfield
.disp16
2075 || t
.bitfield
.disp32
2076 || t
.bitfield
.disp32s
2077 || t
.bitfield
.disp64
);
2080 return (t
.bitfield
.disp8
2081 || t
.bitfield
.disp16
2082 || t
.bitfield
.disp32
2083 || t
.bitfield
.disp32s
2084 || t
.bitfield
.disp64
2085 || t
.bitfield
.baseindex
);
2094 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2095 between operand GIVEN and opeand WANTED for instruction template T. */
2098 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2101 return !((i
.types
[given
].bitfield
.byte
2102 && !t
->operand_types
[wanted
].bitfield
.byte
)
2103 || (i
.types
[given
].bitfield
.word
2104 && !t
->operand_types
[wanted
].bitfield
.word
)
2105 || (i
.types
[given
].bitfield
.dword
2106 && !t
->operand_types
[wanted
].bitfield
.dword
)
2107 || (i
.types
[given
].bitfield
.qword
2108 && !t
->operand_types
[wanted
].bitfield
.qword
)
2109 || (i
.types
[given
].bitfield
.tbyte
2110 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2113 /* Return 1 if there is no conflict in SIMD register between operand
2114 GIVEN and opeand WANTED for instruction template T. */
2117 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2120 return !((i
.types
[given
].bitfield
.xmmword
2121 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2122 || (i
.types
[given
].bitfield
.ymmword
2123 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2124 || (i
.types
[given
].bitfield
.zmmword
2125 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2128 /* Return 1 if there is no conflict in any size between operand GIVEN
2129 and opeand WANTED for instruction template T. */
2132 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2135 return (match_operand_size (t
, wanted
, given
)
2136 && !((i
.types
[given
].bitfield
.unspecified
2138 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2139 || (i
.types
[given
].bitfield
.fword
2140 && !t
->operand_types
[wanted
].bitfield
.fword
)
2141 /* For scalar opcode templates to allow register and memory
2142 operands at the same time, some special casing is needed
2143 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2144 down-conversion vpmov*. */
2145 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2146 && !t
->opcode_modifier
.broadcast
2147 && (t
->operand_types
[wanted
].bitfield
.byte
2148 || t
->operand_types
[wanted
].bitfield
.word
2149 || t
->operand_types
[wanted
].bitfield
.dword
2150 || t
->operand_types
[wanted
].bitfield
.qword
))
2151 ? (i
.types
[given
].bitfield
.xmmword
2152 || i
.types
[given
].bitfield
.ymmword
2153 || i
.types
[given
].bitfield
.zmmword
)
2154 : !match_simd_size(t
, wanted
, given
))));
2157 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2158 operands for instruction template T, and it has MATCH_REVERSE set if there
2159 is no size conflict on any operands for the template with operands reversed
2160 (and the template allows for reversing in the first place). */
2162 #define MATCH_STRAIGHT 1
2163 #define MATCH_REVERSE 2
2165 static INLINE
unsigned int
2166 operand_size_match (const insn_template
*t
)
2168 unsigned int j
, match
= MATCH_STRAIGHT
;
2170 /* Don't check non-absolute jump instructions. */
2171 if (t
->opcode_modifier
.jump
2172 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2175 /* Check memory and accumulator operand size. */
2176 for (j
= 0; j
< i
.operands
; j
++)
2178 if (i
.types
[j
].bitfield
.class != Reg
2179 && i
.types
[j
].bitfield
.class != RegSIMD
2180 && t
->opcode_modifier
.anysize
)
2183 if (t
->operand_types
[j
].bitfield
.class == Reg
2184 && !match_operand_size (t
, j
, j
))
2190 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2191 && !match_simd_size (t
, j
, j
))
2197 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2198 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2204 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2211 if (!t
->opcode_modifier
.d
)
2215 i
.error
= operand_size_mismatch
;
2219 /* Check reverse. */
2220 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2222 for (j
= 0; j
< i
.operands
; j
++)
2224 unsigned int given
= i
.operands
- j
- 1;
2226 if (t
->operand_types
[j
].bitfield
.class == Reg
2227 && !match_operand_size (t
, j
, given
))
2230 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2231 && !match_simd_size (t
, j
, given
))
2234 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2235 && (!match_operand_size (t
, j
, given
)
2236 || !match_simd_size (t
, j
, given
)))
2239 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2243 return match
| MATCH_REVERSE
;
2247 operand_type_match (i386_operand_type overlap
,
2248 i386_operand_type given
)
2250 i386_operand_type temp
= overlap
;
2252 temp
.bitfield
.unspecified
= 0;
2253 temp
.bitfield
.byte
= 0;
2254 temp
.bitfield
.word
= 0;
2255 temp
.bitfield
.dword
= 0;
2256 temp
.bitfield
.fword
= 0;
2257 temp
.bitfield
.qword
= 0;
2258 temp
.bitfield
.tbyte
= 0;
2259 temp
.bitfield
.xmmword
= 0;
2260 temp
.bitfield
.ymmword
= 0;
2261 temp
.bitfield
.zmmword
= 0;
2262 if (operand_type_all_zero (&temp
))
2265 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2269 i
.error
= operand_type_mismatch
;
2273 /* If given types g0 and g1 are registers they must be of the same type
2274 unless the expected operand type register overlap is null.
2275 Some Intel syntax memory operand size checking also happens here. */
2278 operand_type_register_match (i386_operand_type g0
,
2279 i386_operand_type t0
,
2280 i386_operand_type g1
,
2281 i386_operand_type t1
)
2283 if (g0
.bitfield
.class != Reg
2284 && g0
.bitfield
.class != RegSIMD
2285 && (!operand_type_check (g0
, anymem
)
2286 || g0
.bitfield
.unspecified
2287 || (t0
.bitfield
.class != Reg
2288 && t0
.bitfield
.class != RegSIMD
)))
2291 if (g1
.bitfield
.class != Reg
2292 && g1
.bitfield
.class != RegSIMD
2293 && (!operand_type_check (g1
, anymem
)
2294 || g1
.bitfield
.unspecified
2295 || (t1
.bitfield
.class != Reg
2296 && t1
.bitfield
.class != RegSIMD
)))
2299 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2300 && g0
.bitfield
.word
== g1
.bitfield
.word
2301 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2302 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2303 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2304 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2305 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2308 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2309 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2310 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2311 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2312 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2313 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2314 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2317 i
.error
= register_type_mismatch
;
2322 static INLINE
unsigned int
2323 register_number (const reg_entry
*r
)
2325 unsigned int nr
= r
->reg_num
;
2327 if (r
->reg_flags
& RegRex
)
2330 if (r
->reg_flags
& RegVRex
)
2336 static INLINE
unsigned int
2337 mode_from_disp_size (i386_operand_type t
)
2339 if (t
.bitfield
.disp8
)
2341 else if (t
.bitfield
.disp16
2342 || t
.bitfield
.disp32
2343 || t
.bitfield
.disp32s
)
2350 fits_in_signed_byte (addressT num
)
2352 return num
+ 0x80 <= 0xff;
2356 fits_in_unsigned_byte (addressT num
)
2362 fits_in_unsigned_word (addressT num
)
2364 return num
<= 0xffff;
2368 fits_in_signed_word (addressT num
)
2370 return num
+ 0x8000 <= 0xffff;
2374 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2379 return num
+ 0x80000000 <= 0xffffffff;
2381 } /* fits_in_signed_long() */
2384 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2389 return num
<= 0xffffffff;
2391 } /* fits_in_unsigned_long() */
2394 fits_in_disp8 (offsetT num
)
2396 int shift
= i
.memshift
;
2402 mask
= (1 << shift
) - 1;
2404 /* Return 0 if NUM isn't properly aligned. */
2408 /* Check if NUM will fit in 8bit after shift. */
2409 return fits_in_signed_byte (num
>> shift
);
2413 fits_in_imm4 (offsetT num
)
2415 return (num
& 0xf) == num
;
2418 static i386_operand_type
2419 smallest_imm_type (offsetT num
)
2421 i386_operand_type t
;
2423 operand_type_set (&t
, 0);
2424 t
.bitfield
.imm64
= 1;
2426 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2428 /* This code is disabled on the 486 because all the Imm1 forms
2429 in the opcode table are slower on the i486. They're the
2430 versions with the implicitly specified single-position
2431 displacement, which has another syntax if you really want to
2433 t
.bitfield
.imm1
= 1;
2434 t
.bitfield
.imm8
= 1;
2435 t
.bitfield
.imm8s
= 1;
2436 t
.bitfield
.imm16
= 1;
2437 t
.bitfield
.imm32
= 1;
2438 t
.bitfield
.imm32s
= 1;
2440 else if (fits_in_signed_byte (num
))
2442 t
.bitfield
.imm8
= 1;
2443 t
.bitfield
.imm8s
= 1;
2444 t
.bitfield
.imm16
= 1;
2445 t
.bitfield
.imm32
= 1;
2446 t
.bitfield
.imm32s
= 1;
2448 else if (fits_in_unsigned_byte (num
))
2450 t
.bitfield
.imm8
= 1;
2451 t
.bitfield
.imm16
= 1;
2452 t
.bitfield
.imm32
= 1;
2453 t
.bitfield
.imm32s
= 1;
2455 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2457 t
.bitfield
.imm16
= 1;
2458 t
.bitfield
.imm32
= 1;
2459 t
.bitfield
.imm32s
= 1;
2461 else if (fits_in_signed_long (num
))
2463 t
.bitfield
.imm32
= 1;
2464 t
.bitfield
.imm32s
= 1;
2466 else if (fits_in_unsigned_long (num
))
2467 t
.bitfield
.imm32
= 1;
2473 offset_in_range (offsetT val
, int size
)
2479 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2480 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2481 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2483 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2489 /* If BFD64, sign extend val for 32bit address mode. */
2490 if (flag_code
!= CODE_64BIT
2491 || i
.prefix
[ADDR_PREFIX
])
2492 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2493 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2496 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2498 char buf1
[40], buf2
[40];
2500 sprint_value (buf1
, val
);
2501 sprint_value (buf2
, val
& mask
);
2502 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2517 a. PREFIX_EXIST if attempting to add a prefix where one from the
2518 same class already exists.
2519 b. PREFIX_LOCK if lock prefix is added.
2520 c. PREFIX_REP if rep/repne prefix is added.
2521 d. PREFIX_DS if ds prefix is added.
2522 e. PREFIX_OTHER if other prefix is added.
2525 static enum PREFIX_GROUP
2526 add_prefix (unsigned int prefix
)
2528 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2531 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2532 && flag_code
== CODE_64BIT
)
2534 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2535 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2536 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2537 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2548 case DS_PREFIX_OPCODE
:
2551 case CS_PREFIX_OPCODE
:
2552 case ES_PREFIX_OPCODE
:
2553 case FS_PREFIX_OPCODE
:
2554 case GS_PREFIX_OPCODE
:
2555 case SS_PREFIX_OPCODE
:
2559 case REPNE_PREFIX_OPCODE
:
2560 case REPE_PREFIX_OPCODE
:
2565 case LOCK_PREFIX_OPCODE
:
2574 case ADDR_PREFIX_OPCODE
:
2578 case DATA_PREFIX_OPCODE
:
2582 if (i
.prefix
[q
] != 0)
2590 i
.prefix
[q
] |= prefix
;
2593 as_bad (_("same type of prefix used twice"));
2599 update_code_flag (int value
, int check
)
2601 PRINTF_LIKE ((*as_error
));
2603 flag_code
= (enum flag_code
) value
;
2604 if (flag_code
== CODE_64BIT
)
2606 cpu_arch_flags
.bitfield
.cpu64
= 1;
2607 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2611 cpu_arch_flags
.bitfield
.cpu64
= 0;
2612 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2614 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2617 as_error
= as_fatal
;
2620 (*as_error
) (_("64bit mode not supported on `%s'."),
2621 cpu_arch_name
? cpu_arch_name
: default_arch
);
2623 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2626 as_error
= as_fatal
;
2629 (*as_error
) (_("32bit mode not supported on `%s'."),
2630 cpu_arch_name
? cpu_arch_name
: default_arch
);
2632 stackop_size
= '\0';
2636 set_code_flag (int value
)
2638 update_code_flag (value
, 0);
2642 set_16bit_gcc_code_flag (int new_code_flag
)
2644 flag_code
= (enum flag_code
) new_code_flag
;
2645 if (flag_code
!= CODE_16BIT
)
2647 cpu_arch_flags
.bitfield
.cpu64
= 0;
2648 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2649 stackop_size
= LONG_MNEM_SUFFIX
;
2653 set_intel_syntax (int syntax_flag
)
2655 /* Find out if register prefixing is specified. */
2656 int ask_naked_reg
= 0;
2659 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2662 int e
= get_symbol_name (&string
);
2664 if (strcmp (string
, "prefix") == 0)
2666 else if (strcmp (string
, "noprefix") == 0)
2669 as_bad (_("bad argument to syntax directive."));
2670 (void) restore_line_pointer (e
);
2672 demand_empty_rest_of_line ();
2674 intel_syntax
= syntax_flag
;
2676 if (ask_naked_reg
== 0)
2677 allow_naked_reg
= (intel_syntax
2678 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2680 allow_naked_reg
= (ask_naked_reg
< 0);
2682 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2684 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2685 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2686 register_prefix
= allow_naked_reg
? "" : "%";
2690 set_intel_mnemonic (int mnemonic_flag
)
2692 intel_mnemonic
= mnemonic_flag
;
2696 set_allow_index_reg (int flag
)
2698 allow_index_reg
= flag
;
2702 set_check (int what
)
2704 enum check_kind
*kind
;
2709 kind
= &operand_check
;
2720 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2723 int e
= get_symbol_name (&string
);
2725 if (strcmp (string
, "none") == 0)
2727 else if (strcmp (string
, "warning") == 0)
2728 *kind
= check_warning
;
2729 else if (strcmp (string
, "error") == 0)
2730 *kind
= check_error
;
2732 as_bad (_("bad argument to %s_check directive."), str
);
2733 (void) restore_line_pointer (e
);
2736 as_bad (_("missing argument for %s_check directive"), str
);
2738 demand_empty_rest_of_line ();
2742 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2743 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2745 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2746 static const char *arch
;
2748 /* Intel LIOM is only supported on ELF. */
2754 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2755 use default_arch. */
2756 arch
= cpu_arch_name
;
2758 arch
= default_arch
;
2761 /* If we are targeting Intel MCU, we must enable it. */
2762 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2763 || new_flag
.bitfield
.cpuiamcu
)
2766 /* If we are targeting Intel L1OM, we must enable it. */
2767 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2768 || new_flag
.bitfield
.cpul1om
)
2771 /* If we are targeting Intel K1OM, we must enable it. */
2772 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2773 || new_flag
.bitfield
.cpuk1om
)
2776 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2781 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2785 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2788 int e
= get_symbol_name (&string
);
2790 i386_cpu_flags flags
;
2792 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2794 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2796 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2800 cpu_arch_name
= cpu_arch
[j
].name
;
2801 cpu_sub_arch_name
= NULL
;
2802 cpu_arch_flags
= cpu_arch
[j
].flags
;
2803 if (flag_code
== CODE_64BIT
)
2805 cpu_arch_flags
.bitfield
.cpu64
= 1;
2806 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2810 cpu_arch_flags
.bitfield
.cpu64
= 0;
2811 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2813 cpu_arch_isa
= cpu_arch
[j
].type
;
2814 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2815 if (!cpu_arch_tune_set
)
2817 cpu_arch_tune
= cpu_arch_isa
;
2818 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2823 flags
= cpu_flags_or (cpu_arch_flags
,
2826 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2828 if (cpu_sub_arch_name
)
2830 char *name
= cpu_sub_arch_name
;
2831 cpu_sub_arch_name
= concat (name
,
2833 (const char *) NULL
);
2837 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2838 cpu_arch_flags
= flags
;
2839 cpu_arch_isa_flags
= flags
;
2843 = cpu_flags_or (cpu_arch_isa_flags
,
2845 (void) restore_line_pointer (e
);
2846 demand_empty_rest_of_line ();
2851 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2853 /* Disable an ISA extension. */
2854 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2855 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2857 flags
= cpu_flags_and_not (cpu_arch_flags
,
2858 cpu_noarch
[j
].flags
);
2859 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2861 if (cpu_sub_arch_name
)
2863 char *name
= cpu_sub_arch_name
;
2864 cpu_sub_arch_name
= concat (name
, string
,
2865 (const char *) NULL
);
2869 cpu_sub_arch_name
= xstrdup (string
);
2870 cpu_arch_flags
= flags
;
2871 cpu_arch_isa_flags
= flags
;
2873 (void) restore_line_pointer (e
);
2874 demand_empty_rest_of_line ();
2878 j
= ARRAY_SIZE (cpu_arch
);
2881 if (j
>= ARRAY_SIZE (cpu_arch
))
2882 as_bad (_("no such architecture: `%s'"), string
);
2884 *input_line_pointer
= e
;
2887 as_bad (_("missing cpu architecture"));
2889 no_cond_jump_promotion
= 0;
2890 if (*input_line_pointer
== ','
2891 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2896 ++input_line_pointer
;
2897 e
= get_symbol_name (&string
);
2899 if (strcmp (string
, "nojumps") == 0)
2900 no_cond_jump_promotion
= 1;
2901 else if (strcmp (string
, "jumps") == 0)
2904 as_bad (_("no such architecture modifier: `%s'"), string
);
2906 (void) restore_line_pointer (e
);
2909 demand_empty_rest_of_line ();
2912 enum bfd_architecture
2915 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2917 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2918 || flag_code
!= CODE_64BIT
)
2919 as_fatal (_("Intel L1OM is 64bit ELF only"));
2920 return bfd_arch_l1om
;
2922 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2924 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2925 || flag_code
!= CODE_64BIT
)
2926 as_fatal (_("Intel K1OM is 64bit ELF only"));
2927 return bfd_arch_k1om
;
2929 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2931 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2932 || flag_code
== CODE_64BIT
)
2933 as_fatal (_("Intel MCU is 32bit ELF only"));
2934 return bfd_arch_iamcu
;
2937 return bfd_arch_i386
;
2943 if (!strncmp (default_arch
, "x86_64", 6))
2945 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2947 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2948 || default_arch
[6] != '\0')
2949 as_fatal (_("Intel L1OM is 64bit ELF only"));
2950 return bfd_mach_l1om
;
2952 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2954 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2955 || default_arch
[6] != '\0')
2956 as_fatal (_("Intel K1OM is 64bit ELF only"));
2957 return bfd_mach_k1om
;
2959 else if (default_arch
[6] == '\0')
2960 return bfd_mach_x86_64
;
2962 return bfd_mach_x64_32
;
2964 else if (!strcmp (default_arch
, "i386")
2965 || !strcmp (default_arch
, "iamcu"))
2967 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2969 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2970 as_fatal (_("Intel MCU is 32bit ELF only"));
2971 return bfd_mach_i386_iamcu
;
2974 return bfd_mach_i386_i386
;
2977 as_fatal (_("unknown architecture"));
2983 const char *hash_err
;
2985 /* Support pseudo prefixes like {disp32}. */
2986 lex_type
['{'] = LEX_BEGIN_NAME
;
2988 /* Initialize op_hash hash table. */
2989 op_hash
= hash_new ();
2992 const insn_template
*optab
;
2993 templates
*core_optab
;
2995 /* Setup for loop. */
2997 core_optab
= XNEW (templates
);
2998 core_optab
->start
= optab
;
3003 if (optab
->name
== NULL
3004 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3006 /* different name --> ship out current template list;
3007 add to hash table; & begin anew. */
3008 core_optab
->end
= optab
;
3009 hash_err
= hash_insert (op_hash
,
3011 (void *) core_optab
);
3014 as_fatal (_("can't hash %s: %s"),
3018 if (optab
->name
== NULL
)
3020 core_optab
= XNEW (templates
);
3021 core_optab
->start
= optab
;
3026 /* Initialize reg_hash hash table. */
3027 reg_hash
= hash_new ();
3029 const reg_entry
*regtab
;
3030 unsigned int regtab_size
= i386_regtab_size
;
3032 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3034 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
3036 as_fatal (_("can't hash %s: %s"),
3042 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3047 for (c
= 0; c
< 256; c
++)
3052 mnemonic_chars
[c
] = c
;
3053 register_chars
[c
] = c
;
3054 operand_chars
[c
] = c
;
3056 else if (ISLOWER (c
))
3058 mnemonic_chars
[c
] = c
;
3059 register_chars
[c
] = c
;
3060 operand_chars
[c
] = c
;
3062 else if (ISUPPER (c
))
3064 mnemonic_chars
[c
] = TOLOWER (c
);
3065 register_chars
[c
] = mnemonic_chars
[c
];
3066 operand_chars
[c
] = c
;
3068 else if (c
== '{' || c
== '}')
3070 mnemonic_chars
[c
] = c
;
3071 operand_chars
[c
] = c
;
3074 if (ISALPHA (c
) || ISDIGIT (c
))
3075 identifier_chars
[c
] = c
;
3078 identifier_chars
[c
] = c
;
3079 operand_chars
[c
] = c
;
3084 identifier_chars
['@'] = '@';
3087 identifier_chars
['?'] = '?';
3088 operand_chars
['?'] = '?';
3090 digit_chars
['-'] = '-';
3091 mnemonic_chars
['_'] = '_';
3092 mnemonic_chars
['-'] = '-';
3093 mnemonic_chars
['.'] = '.';
3094 identifier_chars
['_'] = '_';
3095 identifier_chars
['.'] = '.';
3097 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3098 operand_chars
[(unsigned char) *p
] = *p
;
3101 if (flag_code
== CODE_64BIT
)
3103 #if defined (OBJ_COFF) && defined (TE_PE)
3104 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3107 x86_dwarf2_return_column
= 16;
3109 x86_cie_data_alignment
= -8;
3113 x86_dwarf2_return_column
= 8;
3114 x86_cie_data_alignment
= -4;
3117 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3118 can be turned into BRANCH_PREFIX frag. */
3119 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3124 i386_print_statistics (FILE *file
)
3126 hash_print_statistics (file
, "i386 opcode", op_hash
);
3127 hash_print_statistics (file
, "i386 register", reg_hash
);
3132 /* Debugging routines for md_assemble. */
3133 static void pte (insn_template
*);
3134 static void pt (i386_operand_type
);
3135 static void pe (expressionS
*);
3136 static void ps (symbolS
*);
3139 pi (const char *line
, i386_insn
*x
)
3143 fprintf (stdout
, "%s: template ", line
);
3145 fprintf (stdout
, " address: base %s index %s scale %x\n",
3146 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3147 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3148 x
->log2_scale_factor
);
3149 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3150 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3151 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3152 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3153 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3154 (x
->rex
& REX_W
) != 0,
3155 (x
->rex
& REX_R
) != 0,
3156 (x
->rex
& REX_X
) != 0,
3157 (x
->rex
& REX_B
) != 0);
3158 for (j
= 0; j
< x
->operands
; j
++)
3160 fprintf (stdout
, " #%d: ", j
+ 1);
3162 fprintf (stdout
, "\n");
3163 if (x
->types
[j
].bitfield
.class == Reg
3164 || x
->types
[j
].bitfield
.class == RegMMX
3165 || x
->types
[j
].bitfield
.class == RegSIMD
3166 || x
->types
[j
].bitfield
.class == SReg
3167 || x
->types
[j
].bitfield
.class == RegCR
3168 || x
->types
[j
].bitfield
.class == RegDR
3169 || x
->types
[j
].bitfield
.class == RegTR
)
3170 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3171 if (operand_type_check (x
->types
[j
], imm
))
3173 if (operand_type_check (x
->types
[j
], disp
))
3174 pe (x
->op
[j
].disps
);
3179 pte (insn_template
*t
)
3182 fprintf (stdout
, " %d operands ", t
->operands
);
3183 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3184 if (t
->extension_opcode
!= None
)
3185 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3186 if (t
->opcode_modifier
.d
)
3187 fprintf (stdout
, "D");
3188 if (t
->opcode_modifier
.w
)
3189 fprintf (stdout
, "W");
3190 fprintf (stdout
, "\n");
3191 for (j
= 0; j
< t
->operands
; j
++)
3193 fprintf (stdout
, " #%d type ", j
+ 1);
3194 pt (t
->operand_types
[j
]);
3195 fprintf (stdout
, "\n");
3202 fprintf (stdout
, " operation %d\n", e
->X_op
);
3203 fprintf (stdout
, " add_number %ld (%lx)\n",
3204 (long) e
->X_add_number
, (long) e
->X_add_number
);
3205 if (e
->X_add_symbol
)
3207 fprintf (stdout
, " add_symbol ");
3208 ps (e
->X_add_symbol
);
3209 fprintf (stdout
, "\n");
3213 fprintf (stdout
, " op_symbol ");
3214 ps (e
->X_op_symbol
);
3215 fprintf (stdout
, "\n");
3222 fprintf (stdout
, "%s type %s%s",
3224 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3225 segment_name (S_GET_SEGMENT (s
)));
3228 static struct type_name
3230 i386_operand_type mask
;
3233 const type_names
[] =
3235 { OPERAND_TYPE_REG8
, "r8" },
3236 { OPERAND_TYPE_REG16
, "r16" },
3237 { OPERAND_TYPE_REG32
, "r32" },
3238 { OPERAND_TYPE_REG64
, "r64" },
3239 { OPERAND_TYPE_ACC8
, "acc8" },
3240 { OPERAND_TYPE_ACC16
, "acc16" },
3241 { OPERAND_TYPE_ACC32
, "acc32" },
3242 { OPERAND_TYPE_ACC64
, "acc64" },
3243 { OPERAND_TYPE_IMM8
, "i8" },
3244 { OPERAND_TYPE_IMM8
, "i8s" },
3245 { OPERAND_TYPE_IMM16
, "i16" },
3246 { OPERAND_TYPE_IMM32
, "i32" },
3247 { OPERAND_TYPE_IMM32S
, "i32s" },
3248 { OPERAND_TYPE_IMM64
, "i64" },
3249 { OPERAND_TYPE_IMM1
, "i1" },
3250 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3251 { OPERAND_TYPE_DISP8
, "d8" },
3252 { OPERAND_TYPE_DISP16
, "d16" },
3253 { OPERAND_TYPE_DISP32
, "d32" },
3254 { OPERAND_TYPE_DISP32S
, "d32s" },
3255 { OPERAND_TYPE_DISP64
, "d64" },
3256 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3257 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3258 { OPERAND_TYPE_CONTROL
, "control reg" },
3259 { OPERAND_TYPE_TEST
, "test reg" },
3260 { OPERAND_TYPE_DEBUG
, "debug reg" },
3261 { OPERAND_TYPE_FLOATREG
, "FReg" },
3262 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3263 { OPERAND_TYPE_SREG
, "SReg" },
3264 { OPERAND_TYPE_REGMMX
, "rMMX" },
3265 { OPERAND_TYPE_REGXMM
, "rXMM" },
3266 { OPERAND_TYPE_REGYMM
, "rYMM" },
3267 { OPERAND_TYPE_REGZMM
, "rZMM" },
3268 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3272 pt (i386_operand_type t
)
3275 i386_operand_type a
;
3277 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3279 a
= operand_type_and (t
, type_names
[j
].mask
);
3280 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3281 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3286 #endif /* DEBUG386 */
3288 static bfd_reloc_code_real_type
3289 reloc (unsigned int size
,
3292 bfd_reloc_code_real_type other
)
3294 if (other
!= NO_RELOC
)
3296 reloc_howto_type
*rel
;
3301 case BFD_RELOC_X86_64_GOT32
:
3302 return BFD_RELOC_X86_64_GOT64
;
3304 case BFD_RELOC_X86_64_GOTPLT64
:
3305 return BFD_RELOC_X86_64_GOTPLT64
;
3307 case BFD_RELOC_X86_64_PLTOFF64
:
3308 return BFD_RELOC_X86_64_PLTOFF64
;
3310 case BFD_RELOC_X86_64_GOTPC32
:
3311 other
= BFD_RELOC_X86_64_GOTPC64
;
3313 case BFD_RELOC_X86_64_GOTPCREL
:
3314 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3316 case BFD_RELOC_X86_64_TPOFF32
:
3317 other
= BFD_RELOC_X86_64_TPOFF64
;
3319 case BFD_RELOC_X86_64_DTPOFF32
:
3320 other
= BFD_RELOC_X86_64_DTPOFF64
;
3326 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3327 if (other
== BFD_RELOC_SIZE32
)
3330 other
= BFD_RELOC_SIZE64
;
3333 as_bad (_("there are no pc-relative size relocations"));
3339 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3340 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3343 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3345 as_bad (_("unknown relocation (%u)"), other
);
3346 else if (size
!= bfd_get_reloc_size (rel
))
3347 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3348 bfd_get_reloc_size (rel
),
3350 else if (pcrel
&& !rel
->pc_relative
)
3351 as_bad (_("non-pc-relative relocation for pc-relative field"));
3352 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3354 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3356 as_bad (_("relocated field and relocation type differ in signedness"));
3365 as_bad (_("there are no unsigned pc-relative relocations"));
3368 case 1: return BFD_RELOC_8_PCREL
;
3369 case 2: return BFD_RELOC_16_PCREL
;
3370 case 4: return BFD_RELOC_32_PCREL
;
3371 case 8: return BFD_RELOC_64_PCREL
;
3373 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3380 case 4: return BFD_RELOC_X86_64_32S
;
3385 case 1: return BFD_RELOC_8
;
3386 case 2: return BFD_RELOC_16
;
3387 case 4: return BFD_RELOC_32
;
3388 case 8: return BFD_RELOC_64
;
3390 as_bad (_("cannot do %s %u byte relocation"),
3391 sign
> 0 ? "signed" : "unsigned", size
);
3397 /* Here we decide which fixups can be adjusted to make them relative to
3398 the beginning of the section instead of the symbol. Basically we need
3399 to make sure that the dynamic relocations are done correctly, so in
3400 some cases we force the original symbol to be used. */
3403 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3405 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3409 /* Don't adjust pc-relative references to merge sections in 64-bit
3411 if (use_rela_relocations
3412 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3416 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3417 and changed later by validate_fix. */
3418 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3419 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3422 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3423 for size relocations. */
3424 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3425 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3426 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3427 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3428 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3429 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3430 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3431 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3432 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3433 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3434 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3435 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3436 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3437 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3438 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3439 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3440 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3441 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3442 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3443 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3444 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3445 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3446 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3447 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3448 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3449 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3450 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3451 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3452 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3453 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3454 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3461 intel_float_operand (const char *mnemonic
)
3463 /* Note that the value returned is meaningful only for opcodes with (memory)
3464 operands, hence the code here is free to improperly handle opcodes that
3465 have no operands (for better performance and smaller code). */
3467 if (mnemonic
[0] != 'f')
3468 return 0; /* non-math */
3470 switch (mnemonic
[1])
3472 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3473 the fs segment override prefix not currently handled because no
3474 call path can make opcodes without operands get here */
3476 return 2 /* integer op */;
3478 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3479 return 3; /* fldcw/fldenv */
3482 if (mnemonic
[2] != 'o' /* fnop */)
3483 return 3; /* non-waiting control op */
3486 if (mnemonic
[2] == 's')
3487 return 3; /* frstor/frstpm */
3490 if (mnemonic
[2] == 'a')
3491 return 3; /* fsave */
3492 if (mnemonic
[2] == 't')
3494 switch (mnemonic
[3])
3496 case 'c': /* fstcw */
3497 case 'd': /* fstdw */
3498 case 'e': /* fstenv */
3499 case 's': /* fsts[gw] */
3505 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3506 return 0; /* fxsave/fxrstor are not really math ops */
3513 /* Build the VEX prefix. */
3516 build_vex_prefix (const insn_template
*t
)
3518 unsigned int register_specifier
;
3519 unsigned int implied_prefix
;
3520 unsigned int vector_length
;
3523 /* Check register specifier. */
3524 if (i
.vex
.register_specifier
)
3526 register_specifier
=
3527 ~register_number (i
.vex
.register_specifier
) & 0xf;
3528 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3531 register_specifier
= 0xf;
3533 /* Use 2-byte VEX prefix by swapping destination and source operand
3534 if there are more than 1 register operand. */
3535 if (i
.reg_operands
> 1
3536 && i
.vec_encoding
!= vex_encoding_vex3
3537 && i
.dir_encoding
== dir_encoding_default
3538 && i
.operands
== i
.reg_operands
3539 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3540 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3541 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3544 unsigned int xchg
= i
.operands
- 1;
3545 union i386_op temp_op
;
3546 i386_operand_type temp_type
;
3548 temp_type
= i
.types
[xchg
];
3549 i
.types
[xchg
] = i
.types
[0];
3550 i
.types
[0] = temp_type
;
3551 temp_op
= i
.op
[xchg
];
3552 i
.op
[xchg
] = i
.op
[0];
3555 gas_assert (i
.rm
.mode
== 3);
3559 i
.rm
.regmem
= i
.rm
.reg
;
3562 if (i
.tm
.opcode_modifier
.d
)
3563 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3564 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3565 else /* Use the next insn. */
3569 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3570 are no memory operands and at least 3 register ones. */
3571 if (i
.reg_operands
>= 3
3572 && i
.vec_encoding
!= vex_encoding_vex3
3573 && i
.reg_operands
== i
.operands
- i
.imm_operands
3574 && i
.tm
.opcode_modifier
.vex
3575 && i
.tm
.opcode_modifier
.commutative
3576 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3578 && i
.vex
.register_specifier
3579 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3581 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3582 union i386_op temp_op
;
3583 i386_operand_type temp_type
;
3585 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3586 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3587 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3588 &i
.types
[i
.operands
- 3]));
3589 gas_assert (i
.rm
.mode
== 3);
3591 temp_type
= i
.types
[xchg
];
3592 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3593 i
.types
[xchg
+ 1] = temp_type
;
3594 temp_op
= i
.op
[xchg
];
3595 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3596 i
.op
[xchg
+ 1] = temp_op
;
3599 xchg
= i
.rm
.regmem
| 8;
3600 i
.rm
.regmem
= ~register_specifier
& 0xf;
3601 gas_assert (!(i
.rm
.regmem
& 8));
3602 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3603 register_specifier
= ~xchg
& 0xf;
3606 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3607 vector_length
= avxscalar
;
3608 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3614 /* Determine vector length from the last multi-length vector
3617 for (op
= t
->operands
; op
--;)
3618 if (t
->operand_types
[op
].bitfield
.xmmword
3619 && t
->operand_types
[op
].bitfield
.ymmword
3620 && i
.types
[op
].bitfield
.ymmword
)
3627 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3632 case DATA_PREFIX_OPCODE
:
3635 case REPE_PREFIX_OPCODE
:
3638 case REPNE_PREFIX_OPCODE
:
3645 /* Check the REX.W bit and VEXW. */
3646 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3647 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3648 else if (i
.tm
.opcode_modifier
.vexw
)
3649 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3651 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3653 /* Use 2-byte VEX prefix if possible. */
3655 && i
.vec_encoding
!= vex_encoding_vex3
3656 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3657 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3659 /* 2-byte VEX prefix. */
3663 i
.vex
.bytes
[0] = 0xc5;
3665 /* Check the REX.R bit. */
3666 r
= (i
.rex
& REX_R
) ? 0 : 1;
3667 i
.vex
.bytes
[1] = (r
<< 7
3668 | register_specifier
<< 3
3669 | vector_length
<< 2
3674 /* 3-byte VEX prefix. */
3679 switch (i
.tm
.opcode_modifier
.vexopcode
)
3683 i
.vex
.bytes
[0] = 0xc4;
3687 i
.vex
.bytes
[0] = 0xc4;
3691 i
.vex
.bytes
[0] = 0xc4;
3695 i
.vex
.bytes
[0] = 0x8f;
3699 i
.vex
.bytes
[0] = 0x8f;
3703 i
.vex
.bytes
[0] = 0x8f;
3709 /* The high 3 bits of the second VEX byte are 1's compliment
3710 of RXB bits from REX. */
3711 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3713 i
.vex
.bytes
[2] = (w
<< 7
3714 | register_specifier
<< 3
3715 | vector_length
<< 2
3720 static INLINE bfd_boolean
3721 is_evex_encoding (const insn_template
*t
)
3723 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3724 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3725 || t
->opcode_modifier
.sae
;
3728 static INLINE bfd_boolean
3729 is_any_vex_encoding (const insn_template
*t
)
3731 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3732 || is_evex_encoding (t
);
3735 /* Build the EVEX prefix. */
3738 build_evex_prefix (void)
3740 unsigned int register_specifier
;
3741 unsigned int implied_prefix
;
3743 rex_byte vrex_used
= 0;
3745 /* Check register specifier. */
3746 if (i
.vex
.register_specifier
)
3748 gas_assert ((i
.vrex
& REX_X
) == 0);
3750 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3751 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3752 register_specifier
+= 8;
3753 /* The upper 16 registers are encoded in the fourth byte of the
3755 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3756 i
.vex
.bytes
[3] = 0x8;
3757 register_specifier
= ~register_specifier
& 0xf;
3761 register_specifier
= 0xf;
3763 /* Encode upper 16 vector index register in the fourth byte of
3765 if (!(i
.vrex
& REX_X
))
3766 i
.vex
.bytes
[3] = 0x8;
3771 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3776 case DATA_PREFIX_OPCODE
:
3779 case REPE_PREFIX_OPCODE
:
3782 case REPNE_PREFIX_OPCODE
:
3789 /* 4 byte EVEX prefix. */
3791 i
.vex
.bytes
[0] = 0x62;
3794 switch (i
.tm
.opcode_modifier
.vexopcode
)
3810 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3812 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3814 /* The fifth bit of the second EVEX byte is 1's compliment of the
3815 REX_R bit in VREX. */
3816 if (!(i
.vrex
& REX_R
))
3817 i
.vex
.bytes
[1] |= 0x10;
3821 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3823 /* When all operands are registers, the REX_X bit in REX is not
3824 used. We reuse it to encode the upper 16 registers, which is
3825 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3826 as 1's compliment. */
3827 if ((i
.vrex
& REX_B
))
3830 i
.vex
.bytes
[1] &= ~0x40;
3834 /* EVEX instructions shouldn't need the REX prefix. */
3835 i
.vrex
&= ~vrex_used
;
3836 gas_assert (i
.vrex
== 0);
3838 /* Check the REX.W bit and VEXW. */
3839 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3840 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3841 else if (i
.tm
.opcode_modifier
.vexw
)
3842 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3844 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3846 /* Encode the U bit. */
3847 implied_prefix
|= 0x4;
3849 /* The third byte of the EVEX prefix. */
3850 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3852 /* The fourth byte of the EVEX prefix. */
3853 /* The zeroing-masking bit. */
3854 if (i
.mask
&& i
.mask
->zeroing
)
3855 i
.vex
.bytes
[3] |= 0x80;
3857 /* Don't always set the broadcast bit if there is no RC. */
3860 /* Encode the vector length. */
3861 unsigned int vec_length
;
3863 if (!i
.tm
.opcode_modifier
.evex
3864 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3868 /* Determine vector length from the last multi-length vector
3871 for (op
= i
.operands
; op
--;)
3872 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3873 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3874 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3876 if (i
.types
[op
].bitfield
.zmmword
)
3878 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3881 else if (i
.types
[op
].bitfield
.ymmword
)
3883 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3886 else if (i
.types
[op
].bitfield
.xmmword
)
3888 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3891 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3893 switch (i
.broadcast
->bytes
)
3896 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3899 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3902 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3911 if (op
>= MAX_OPERANDS
)
3915 switch (i
.tm
.opcode_modifier
.evex
)
3917 case EVEXLIG
: /* LL' is ignored */
3918 vec_length
= evexlig
<< 5;
3921 vec_length
= 0 << 5;
3924 vec_length
= 1 << 5;
3927 vec_length
= 2 << 5;
3933 i
.vex
.bytes
[3] |= vec_length
;
3934 /* Encode the broadcast bit. */
3936 i
.vex
.bytes
[3] |= 0x10;
3940 if (i
.rounding
->type
!= saeonly
)
3941 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3943 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3946 if (i
.mask
&& i
.mask
->mask
)
3947 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3951 process_immext (void)
3955 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3956 which is coded in the same place as an 8-bit immediate field
3957 would be. Here we fake an 8-bit immediate operand from the
3958 opcode suffix stored in tm.extension_opcode.
3960 AVX instructions also use this encoding, for some of
3961 3 argument instructions. */
3963 gas_assert (i
.imm_operands
<= 1
3965 || (is_any_vex_encoding (&i
.tm
)
3966 && i
.operands
<= 4)));
3968 exp
= &im_expressions
[i
.imm_operands
++];
3969 i
.op
[i
.operands
].imms
= exp
;
3970 i
.types
[i
.operands
] = imm8
;
3972 exp
->X_op
= O_constant
;
3973 exp
->X_add_number
= i
.tm
.extension_opcode
;
3974 i
.tm
.extension_opcode
= None
;
3981 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3986 as_bad (_("invalid instruction `%s' after `%s'"),
3987 i
.tm
.name
, i
.hle_prefix
);
3990 if (i
.prefix
[LOCK_PREFIX
])
3992 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3996 case HLEPrefixRelease
:
3997 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3999 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4003 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4005 as_bad (_("memory destination needed for instruction `%s'"
4006 " after `xrelease'"), i
.tm
.name
);
4013 /* Try the shortest encoding by shortening operand size. */
4016 optimize_encoding (void)
4020 if (optimize_for_space
4021 && !is_any_vex_encoding (&i
.tm
)
4022 && i
.reg_operands
== 1
4023 && i
.imm_operands
== 1
4024 && !i
.types
[1].bitfield
.byte
4025 && i
.op
[0].imms
->X_op
== O_constant
4026 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4027 && (i
.tm
.base_opcode
== 0xa8
4028 || (i
.tm
.base_opcode
== 0xf6
4029 && i
.tm
.extension_opcode
== 0x0)))
4032 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4034 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4035 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4037 i
.types
[1].bitfield
.byte
= 1;
4038 /* Ignore the suffix. */
4040 /* Convert to byte registers. */
4041 if (i
.types
[1].bitfield
.word
)
4043 else if (i
.types
[1].bitfield
.dword
)
4047 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4052 else if (flag_code
== CODE_64BIT
4053 && !is_any_vex_encoding (&i
.tm
)
4054 && ((i
.types
[1].bitfield
.qword
4055 && i
.reg_operands
== 1
4056 && i
.imm_operands
== 1
4057 && i
.op
[0].imms
->X_op
== O_constant
4058 && ((i
.tm
.base_opcode
== 0xb8
4059 && i
.tm
.extension_opcode
== None
4060 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4061 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4062 && ((i
.tm
.base_opcode
== 0x24
4063 || i
.tm
.base_opcode
== 0xa8)
4064 || (i
.tm
.base_opcode
== 0x80
4065 && i
.tm
.extension_opcode
== 0x4)
4066 || ((i
.tm
.base_opcode
== 0xf6
4067 || (i
.tm
.base_opcode
| 1) == 0xc7)
4068 && i
.tm
.extension_opcode
== 0x0)))
4069 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4070 && i
.tm
.base_opcode
== 0x83
4071 && i
.tm
.extension_opcode
== 0x4)))
4072 || (i
.types
[0].bitfield
.qword
4073 && ((i
.reg_operands
== 2
4074 && i
.op
[0].regs
== i
.op
[1].regs
4075 && (i
.tm
.base_opcode
== 0x30
4076 || i
.tm
.base_opcode
== 0x28))
4077 || (i
.reg_operands
== 1
4079 && i
.tm
.base_opcode
== 0x30)))))
4082 andq $imm31, %r64 -> andl $imm31, %r32
4083 andq $imm7, %r64 -> andl $imm7, %r32
4084 testq $imm31, %r64 -> testl $imm31, %r32
4085 xorq %r64, %r64 -> xorl %r32, %r32
4086 subq %r64, %r64 -> subl %r32, %r32
4087 movq $imm31, %r64 -> movl $imm31, %r32
4088 movq $imm32, %r64 -> movl $imm32, %r32
4090 i
.tm
.opcode_modifier
.norex64
= 1;
4091 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4094 movq $imm31, %r64 -> movl $imm31, %r32
4095 movq $imm32, %r64 -> movl $imm32, %r32
4097 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4098 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4099 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4100 i
.types
[0].bitfield
.imm32
= 1;
4101 i
.types
[0].bitfield
.imm32s
= 0;
4102 i
.types
[0].bitfield
.imm64
= 0;
4103 i
.types
[1].bitfield
.dword
= 1;
4104 i
.types
[1].bitfield
.qword
= 0;
4105 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4108 movq $imm31, %r64 -> movl $imm31, %r32
4110 i
.tm
.base_opcode
= 0xb8;
4111 i
.tm
.extension_opcode
= None
;
4112 i
.tm
.opcode_modifier
.w
= 0;
4113 i
.tm
.opcode_modifier
.modrm
= 0;
4117 else if (optimize
> 1
4118 && !optimize_for_space
4119 && !is_any_vex_encoding (&i
.tm
)
4120 && i
.reg_operands
== 2
4121 && i
.op
[0].regs
== i
.op
[1].regs
4122 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4123 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4124 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4127 andb %rN, %rN -> testb %rN, %rN
4128 andw %rN, %rN -> testw %rN, %rN
4129 andq %rN, %rN -> testq %rN, %rN
4130 orb %rN, %rN -> testb %rN, %rN
4131 orw %rN, %rN -> testw %rN, %rN
4132 orq %rN, %rN -> testq %rN, %rN
4134 and outside of 64-bit mode
4136 andl %rN, %rN -> testl %rN, %rN
4137 orl %rN, %rN -> testl %rN, %rN
4139 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4141 else if (i
.reg_operands
== 3
4142 && i
.op
[0].regs
== i
.op
[1].regs
4143 && !i
.types
[2].bitfield
.xmmword
4144 && (i
.tm
.opcode_modifier
.vex
4145 || ((!i
.mask
|| i
.mask
->zeroing
)
4147 && is_evex_encoding (&i
.tm
)
4148 && (i
.vec_encoding
!= vex_encoding_evex
4149 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4150 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4151 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4152 && i
.types
[2].bitfield
.ymmword
))))
4153 && ((i
.tm
.base_opcode
== 0x55
4154 || i
.tm
.base_opcode
== 0x6655
4155 || i
.tm
.base_opcode
== 0x66df
4156 || i
.tm
.base_opcode
== 0x57
4157 || i
.tm
.base_opcode
== 0x6657
4158 || i
.tm
.base_opcode
== 0x66ef
4159 || i
.tm
.base_opcode
== 0x66f8
4160 || i
.tm
.base_opcode
== 0x66f9
4161 || i
.tm
.base_opcode
== 0x66fa
4162 || i
.tm
.base_opcode
== 0x66fb
4163 || i
.tm
.base_opcode
== 0x42
4164 || i
.tm
.base_opcode
== 0x6642
4165 || i
.tm
.base_opcode
== 0x47
4166 || i
.tm
.base_opcode
== 0x6647)
4167 && i
.tm
.extension_opcode
== None
))
4170 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4172 EVEX VOP %zmmM, %zmmM, %zmmN
4173 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4174 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4175 EVEX VOP %ymmM, %ymmM, %ymmN
4176 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4177 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4178 VEX VOP %ymmM, %ymmM, %ymmN
4179 -> VEX VOP %xmmM, %xmmM, %xmmN
4180 VOP, one of vpandn and vpxor:
4181 VEX VOP %ymmM, %ymmM, %ymmN
4182 -> VEX VOP %xmmM, %xmmM, %xmmN
4183 VOP, one of vpandnd and vpandnq:
4184 EVEX VOP %zmmM, %zmmM, %zmmN
4185 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4186 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4187 EVEX VOP %ymmM, %ymmM, %ymmN
4188 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4189 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4190 VOP, one of vpxord and vpxorq:
4191 EVEX VOP %zmmM, %zmmM, %zmmN
4192 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4193 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4194 EVEX VOP %ymmM, %ymmM, %ymmN
4195 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4196 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4197 VOP, one of kxord and kxorq:
4198 VEX VOP %kM, %kM, %kN
4199 -> VEX kxorw %kM, %kM, %kN
4200 VOP, one of kandnd and kandnq:
4201 VEX VOP %kM, %kM, %kN
4202 -> VEX kandnw %kM, %kM, %kN
4204 if (is_evex_encoding (&i
.tm
))
4206 if (i
.vec_encoding
!= vex_encoding_evex
)
4208 i
.tm
.opcode_modifier
.vex
= VEX128
;
4209 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4210 i
.tm
.opcode_modifier
.evex
= 0;
4212 else if (optimize
> 1)
4213 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4217 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4219 i
.tm
.base_opcode
&= 0xff;
4220 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4223 i
.tm
.opcode_modifier
.vex
= VEX128
;
4225 if (i
.tm
.opcode_modifier
.vex
)
4226 for (j
= 0; j
< 3; j
++)
4228 i
.types
[j
].bitfield
.xmmword
= 1;
4229 i
.types
[j
].bitfield
.ymmword
= 0;
4232 else if (i
.vec_encoding
!= vex_encoding_evex
4233 && !i
.types
[0].bitfield
.zmmword
4234 && !i
.types
[1].bitfield
.zmmword
4237 && is_evex_encoding (&i
.tm
)
4238 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4239 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4240 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4241 || (i
.tm
.base_opcode
& ~4) == 0x66db
4242 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4243 && i
.tm
.extension_opcode
== None
)
4246 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4247 vmovdqu32 and vmovdqu64:
4248 EVEX VOP %xmmM, %xmmN
4249 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4250 EVEX VOP %ymmM, %ymmN
4251 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4253 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4255 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4257 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4259 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4260 VOP, one of vpand, vpandn, vpor, vpxor:
4261 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4262 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4263 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4264 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4265 EVEX VOP{d,q} mem, %xmmM, %xmmN
4266 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4267 EVEX VOP{d,q} mem, %ymmM, %ymmN
4268 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4270 for (j
= 0; j
< i
.operands
; j
++)
4271 if (operand_type_check (i
.types
[j
], disp
)
4272 && i
.op
[j
].disps
->X_op
== O_constant
)
4274 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4275 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4276 bytes, we choose EVEX Disp8 over VEX Disp32. */
4277 int evex_disp8
, vex_disp8
;
4278 unsigned int memshift
= i
.memshift
;
4279 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4281 evex_disp8
= fits_in_disp8 (n
);
4283 vex_disp8
= fits_in_disp8 (n
);
4284 if (evex_disp8
!= vex_disp8
)
4286 i
.memshift
= memshift
;
4290 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4293 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4294 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4295 i
.tm
.opcode_modifier
.vex
4296 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4297 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4298 /* VPAND, VPOR, and VPXOR are commutative. */
4299 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4300 i
.tm
.opcode_modifier
.commutative
= 1;
4301 i
.tm
.opcode_modifier
.evex
= 0;
4302 i
.tm
.opcode_modifier
.masking
= 0;
4303 i
.tm
.opcode_modifier
.broadcast
= 0;
4304 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4307 i
.types
[j
].bitfield
.disp8
4308 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4312 /* This is the guts of the machine-dependent assembler. LINE points to a
4313 machine dependent instruction. This function is supposed to emit
4314 the frags/bytes it assembles to. */
4317 md_assemble (char *line
)
4320 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4321 const insn_template
*t
;
4323 /* Initialize globals. */
4324 memset (&i
, '\0', sizeof (i
));
4325 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4326 i
.reloc
[j
] = NO_RELOC
;
4327 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4328 memset (im_expressions
, '\0', sizeof (im_expressions
));
4329 save_stack_p
= save_stack
;
4331 /* First parse an instruction mnemonic & call i386_operand for the operands.
4332 We assume that the scrubber has arranged it so that line[0] is the valid
4333 start of a (possibly prefixed) mnemonic. */
4335 line
= parse_insn (line
, mnemonic
);
4338 mnem_suffix
= i
.suffix
;
4340 line
= parse_operands (line
, mnemonic
);
4342 xfree (i
.memop1_string
);
4343 i
.memop1_string
= NULL
;
4347 /* Now we've parsed the mnemonic into a set of templates, and have the
4348 operands at hand. */
4350 /* All Intel opcodes have reversed operands except for "bound", "enter"
4351 "monitor*", and "mwait*". We also don't reverse intersegment "jmp"
4352 and "call" instructions with 2 immediate operands so that the immediate
4353 segment precedes the offset, as it does when in AT&T mode. */
4356 && (strcmp (mnemonic
, "bound") != 0)
4357 && (strcmp (mnemonic
, "invlpga") != 0)
4358 && (strncmp (mnemonic
, "monitor", 7) != 0)
4359 && (strncmp (mnemonic
, "mwait", 5) != 0)
4360 && !(operand_type_check (i
.types
[0], imm
)
4361 && operand_type_check (i
.types
[1], imm
)))
4364 /* The order of the immediates should be reversed
4365 for 2 immediates extrq and insertq instructions */
4366 if (i
.imm_operands
== 2
4367 && (strcmp (mnemonic
, "extrq") == 0
4368 || strcmp (mnemonic
, "insertq") == 0))
4369 swap_2_operands (0, 1);
4374 /* Don't optimize displacement for movabs since it only takes 64bit
4377 && i
.disp_encoding
!= disp_encoding_32bit
4378 && (flag_code
!= CODE_64BIT
4379 || strcmp (mnemonic
, "movabs") != 0))
4382 /* Next, we find a template that matches the given insn,
4383 making sure the overlap of the given operands types is consistent
4384 with the template operand types. */
4386 if (!(t
= match_template (mnem_suffix
)))
4389 if (sse_check
!= check_none
4390 && !i
.tm
.opcode_modifier
.noavx
4391 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4392 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4393 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4394 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4395 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4396 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4397 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4398 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4399 || i
.tm
.cpu_flags
.bitfield
.cpusse4a
4400 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4401 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4402 || i
.tm
.cpu_flags
.bitfield
.cpusha
4403 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4405 (sse_check
== check_warning
4407 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4410 if (i
.tm
.opcode_modifier
.fwait
)
4411 if (!add_prefix (FWAIT_OPCODE
))
4414 /* Check if REP prefix is OK. */
4415 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4417 as_bad (_("invalid instruction `%s' after `%s'"),
4418 i
.tm
.name
, i
.rep_prefix
);
4422 /* Check for lock without a lockable instruction. Destination operand
4423 must be memory unless it is xchg (0x86). */
4424 if (i
.prefix
[LOCK_PREFIX
]
4425 && (!i
.tm
.opcode_modifier
.islockable
4426 || i
.mem_operands
== 0
4427 || (i
.tm
.base_opcode
!= 0x86
4428 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4430 as_bad (_("expecting lockable instruction after `lock'"));
4434 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4435 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4437 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4441 /* Check if HLE prefix is OK. */
4442 if (i
.hle_prefix
&& !check_hle ())
4445 /* Check BND prefix. */
4446 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4447 as_bad (_("expecting valid branch instruction after `bnd'"));
4449 /* Check NOTRACK prefix. */
4450 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4451 as_bad (_("expecting indirect branch instruction after `notrack'"));
4453 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4455 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4456 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4457 else if (flag_code
!= CODE_16BIT
4458 ? i
.prefix
[ADDR_PREFIX
]
4459 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4460 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4463 /* Insert BND prefix. */
4464 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4466 if (!i
.prefix
[BND_PREFIX
])
4467 add_prefix (BND_PREFIX_OPCODE
);
4468 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4470 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4471 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4475 /* Check string instruction segment overrides. */
4476 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4478 gas_assert (i
.mem_operands
);
4479 if (!check_string ())
4481 i
.disp_operands
= 0;
4484 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4485 optimize_encoding ();
4487 if (!process_suffix ())
4490 /* Update operand types. */
4491 for (j
= 0; j
< i
.operands
; j
++)
4492 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4494 /* Make still unresolved immediate matches conform to size of immediate
4495 given in i.suffix. */
4496 if (!finalize_imm ())
4499 if (i
.types
[0].bitfield
.imm1
)
4500 i
.imm_operands
= 0; /* kludge for shift insns. */
4502 /* We only need to check those implicit registers for instructions
4503 with 3 operands or less. */
4504 if (i
.operands
<= 3)
4505 for (j
= 0; j
< i
.operands
; j
++)
4506 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4507 && !i
.types
[j
].bitfield
.xmmword
)
4510 /* ImmExt should be processed after SSE2AVX. */
4511 if (!i
.tm
.opcode_modifier
.sse2avx
4512 && i
.tm
.opcode_modifier
.immext
)
4515 /* For insns with operands there are more diddles to do to the opcode. */
4518 if (!process_operands ())
4521 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4523 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4524 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4527 if (is_any_vex_encoding (&i
.tm
))
4529 if (!cpu_arch_flags
.bitfield
.cpui286
)
4531 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4536 if (i
.tm
.opcode_modifier
.vex
)
4537 build_vex_prefix (t
);
4539 build_evex_prefix ();
4542 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4543 instructions may define INT_OPCODE as well, so avoid this corner
4544 case for those instructions that use MODRM. */
4545 if (i
.tm
.base_opcode
== INT_OPCODE
4546 && !i
.tm
.opcode_modifier
.modrm
4547 && i
.op
[0].imms
->X_add_number
== 3)
4549 i
.tm
.base_opcode
= INT3_OPCODE
;
4553 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4554 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4555 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4556 && i
.op
[0].disps
->X_op
== O_constant
)
4558 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4559 the absolute address given by the constant. Since ix86 jumps and
4560 calls are pc relative, we need to generate a reloc. */
4561 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4562 i
.op
[0].disps
->X_op
= O_symbol
;
4565 if (i
.tm
.opcode_modifier
.rex64
)
4568 /* For 8 bit registers we need an empty rex prefix. Also if the
4569 instruction already has a prefix, we need to convert old
4570 registers to new ones. */
4572 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4573 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4574 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4575 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4576 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4577 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4582 i
.rex
|= REX_OPCODE
;
4583 for (x
= 0; x
< 2; x
++)
4585 /* Look for 8 bit operand that uses old registers. */
4586 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4587 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4589 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4590 /* In case it is "hi" register, give up. */
4591 if (i
.op
[x
].regs
->reg_num
> 3)
4592 as_bad (_("can't encode register '%s%s' in an "
4593 "instruction requiring REX prefix."),
4594 register_prefix
, i
.op
[x
].regs
->reg_name
);
4596 /* Otherwise it is equivalent to the extended register.
4597 Since the encoding doesn't change this is merely
4598 cosmetic cleanup for debug output. */
4600 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4605 if (i
.rex
== 0 && i
.rex_encoding
)
4607 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4608 that uses legacy register. If it is "hi" register, don't add
4609 the REX_OPCODE byte. */
4611 for (x
= 0; x
< 2; x
++)
4612 if (i
.types
[x
].bitfield
.class == Reg
4613 && i
.types
[x
].bitfield
.byte
4614 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4615 && i
.op
[x
].regs
->reg_num
> 3)
4617 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4618 i
.rex_encoding
= FALSE
;
4627 add_prefix (REX_OPCODE
| i
.rex
);
4629 /* We are ready to output the insn. */
4632 last_insn
.seg
= now_seg
;
4634 if (i
.tm
.opcode_modifier
.isprefix
)
4636 last_insn
.kind
= last_insn_prefix
;
4637 last_insn
.name
= i
.tm
.name
;
4638 last_insn
.file
= as_where (&last_insn
.line
);
4641 last_insn
.kind
= last_insn_other
;
4645 parse_insn (char *line
, char *mnemonic
)
4648 char *token_start
= l
;
4651 const insn_template
*t
;
4657 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4662 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4664 as_bad (_("no such instruction: `%s'"), token_start
);
4669 if (!is_space_char (*l
)
4670 && *l
!= END_OF_INSN
4672 || (*l
!= PREFIX_SEPARATOR
4675 as_bad (_("invalid character %s in mnemonic"),
4676 output_invalid (*l
));
4679 if (token_start
== l
)
4681 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4682 as_bad (_("expecting prefix; got nothing"));
4684 as_bad (_("expecting mnemonic; got nothing"));
4688 /* Look up instruction (or prefix) via hash table. */
4689 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4691 if (*l
!= END_OF_INSN
4692 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4693 && current_templates
4694 && current_templates
->start
->opcode_modifier
.isprefix
)
4696 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4698 as_bad ((flag_code
!= CODE_64BIT
4699 ? _("`%s' is only supported in 64-bit mode")
4700 : _("`%s' is not supported in 64-bit mode")),
4701 current_templates
->start
->name
);
4704 /* If we are in 16-bit mode, do not allow addr16 or data16.
4705 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4706 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4707 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4708 && flag_code
!= CODE_64BIT
4709 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4710 ^ (flag_code
== CODE_16BIT
)))
4712 as_bad (_("redundant %s prefix"),
4713 current_templates
->start
->name
);
4716 if (current_templates
->start
->opcode_length
== 0)
4718 /* Handle pseudo prefixes. */
4719 switch (current_templates
->start
->base_opcode
)
4723 i
.disp_encoding
= disp_encoding_8bit
;
4727 i
.disp_encoding
= disp_encoding_32bit
;
4731 i
.dir_encoding
= dir_encoding_load
;
4735 i
.dir_encoding
= dir_encoding_store
;
4739 i
.vec_encoding
= vex_encoding_vex
;
4743 i
.vec_encoding
= vex_encoding_vex3
;
4747 i
.vec_encoding
= vex_encoding_evex
;
4751 i
.rex_encoding
= TRUE
;
4755 i
.no_optimize
= TRUE
;
4763 /* Add prefix, checking for repeated prefixes. */
4764 switch (add_prefix (current_templates
->start
->base_opcode
))
4769 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4770 i
.notrack_prefix
= current_templates
->start
->name
;
4773 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4774 i
.hle_prefix
= current_templates
->start
->name
;
4775 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4776 i
.bnd_prefix
= current_templates
->start
->name
;
4778 i
.rep_prefix
= current_templates
->start
->name
;
4784 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4791 if (!current_templates
)
4793 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4794 Check if we should swap operand or force 32bit displacement in
4796 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4797 i
.dir_encoding
= dir_encoding_swap
;
4798 else if (mnem_p
- 3 == dot_p
4801 i
.disp_encoding
= disp_encoding_8bit
;
4802 else if (mnem_p
- 4 == dot_p
4806 i
.disp_encoding
= disp_encoding_32bit
;
4811 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4814 if (!current_templates
)
4817 if (mnem_p
> mnemonic
)
4819 /* See if we can get a match by trimming off a suffix. */
4822 case WORD_MNEM_SUFFIX
:
4823 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4824 i
.suffix
= SHORT_MNEM_SUFFIX
;
4827 case BYTE_MNEM_SUFFIX
:
4828 case QWORD_MNEM_SUFFIX
:
4829 i
.suffix
= mnem_p
[-1];
4831 current_templates
= (const templates
*) hash_find (op_hash
,
4834 case SHORT_MNEM_SUFFIX
:
4835 case LONG_MNEM_SUFFIX
:
4838 i
.suffix
= mnem_p
[-1];
4840 current_templates
= (const templates
*) hash_find (op_hash
,
4849 if (intel_float_operand (mnemonic
) == 1)
4850 i
.suffix
= SHORT_MNEM_SUFFIX
;
4852 i
.suffix
= LONG_MNEM_SUFFIX
;
4854 current_templates
= (const templates
*) hash_find (op_hash
,
4861 if (!current_templates
)
4863 as_bad (_("no such instruction: `%s'"), token_start
);
4868 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
4869 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
4871 /* Check for a branch hint. We allow ",pt" and ",pn" for
4872 predict taken and predict not taken respectively.
4873 I'm not sure that branch hints actually do anything on loop
4874 and jcxz insns (JumpByte) for current Pentium4 chips. They
4875 may work in the future and it doesn't hurt to accept them
4877 if (l
[0] == ',' && l
[1] == 'p')
4881 if (!add_prefix (DS_PREFIX_OPCODE
))
4885 else if (l
[2] == 'n')
4887 if (!add_prefix (CS_PREFIX_OPCODE
))
4893 /* Any other comma loses. */
4896 as_bad (_("invalid character %s in mnemonic"),
4897 output_invalid (*l
));
4901 /* Check if instruction is supported on specified architecture. */
4903 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4905 supported
|= cpu_flags_match (t
);
4906 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4908 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4909 as_warn (_("use .code16 to ensure correct addressing mode"));
4915 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4916 as_bad (flag_code
== CODE_64BIT
4917 ? _("`%s' is not supported in 64-bit mode")
4918 : _("`%s' is only supported in 64-bit mode"),
4919 current_templates
->start
->name
);
4921 as_bad (_("`%s' is not supported on `%s%s'"),
4922 current_templates
->start
->name
,
4923 cpu_arch_name
? cpu_arch_name
: default_arch
,
4924 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4930 parse_operands (char *l
, const char *mnemonic
)
4934 /* 1 if operand is pending after ','. */
4935 unsigned int expecting_operand
= 0;
4937 /* Non-zero if operand parens not balanced. */
4938 unsigned int paren_not_balanced
;
4940 while (*l
!= END_OF_INSN
)
4942 /* Skip optional white space before operand. */
4943 if (is_space_char (*l
))
4945 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4947 as_bad (_("invalid character %s before operand %d"),
4948 output_invalid (*l
),
4952 token_start
= l
; /* After white space. */
4953 paren_not_balanced
= 0;
4954 while (paren_not_balanced
|| *l
!= ',')
4956 if (*l
== END_OF_INSN
)
4958 if (paren_not_balanced
)
4961 as_bad (_("unbalanced parenthesis in operand %d."),
4964 as_bad (_("unbalanced brackets in operand %d."),
4969 break; /* we are done */
4971 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4973 as_bad (_("invalid character %s in operand %d"),
4974 output_invalid (*l
),
4981 ++paren_not_balanced
;
4983 --paren_not_balanced
;
4988 ++paren_not_balanced
;
4990 --paren_not_balanced
;
4994 if (l
!= token_start
)
4995 { /* Yes, we've read in another operand. */
4996 unsigned int operand_ok
;
4997 this_operand
= i
.operands
++;
4998 if (i
.operands
> MAX_OPERANDS
)
5000 as_bad (_("spurious operands; (%d operands/instruction max)"),
5004 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5005 /* Now parse operand adding info to 'i' as we go along. */
5006 END_STRING_AND_SAVE (l
);
5008 if (i
.mem_operands
> 1)
5010 as_bad (_("too many memory references for `%s'"),
5017 i386_intel_operand (token_start
,
5018 intel_float_operand (mnemonic
));
5020 operand_ok
= i386_att_operand (token_start
);
5022 RESTORE_END_STRING (l
);
5028 if (expecting_operand
)
5030 expecting_operand_after_comma
:
5031 as_bad (_("expecting operand after ','; got nothing"));
5036 as_bad (_("expecting operand before ','; got nothing"));
5041 /* Now *l must be either ',' or END_OF_INSN. */
5044 if (*++l
== END_OF_INSN
)
5046 /* Just skip it, if it's \n complain. */
5047 goto expecting_operand_after_comma
;
5049 expecting_operand
= 1;
5056 swap_2_operands (int xchg1
, int xchg2
)
5058 union i386_op temp_op
;
5059 i386_operand_type temp_type
;
5060 unsigned int temp_flags
;
5061 enum bfd_reloc_code_real temp_reloc
;
5063 temp_type
= i
.types
[xchg2
];
5064 i
.types
[xchg2
] = i
.types
[xchg1
];
5065 i
.types
[xchg1
] = temp_type
;
5067 temp_flags
= i
.flags
[xchg2
];
5068 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5069 i
.flags
[xchg1
] = temp_flags
;
5071 temp_op
= i
.op
[xchg2
];
5072 i
.op
[xchg2
] = i
.op
[xchg1
];
5073 i
.op
[xchg1
] = temp_op
;
5075 temp_reloc
= i
.reloc
[xchg2
];
5076 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5077 i
.reloc
[xchg1
] = temp_reloc
;
5081 if (i
.mask
->operand
== xchg1
)
5082 i
.mask
->operand
= xchg2
;
5083 else if (i
.mask
->operand
== xchg2
)
5084 i
.mask
->operand
= xchg1
;
5088 if (i
.broadcast
->operand
== xchg1
)
5089 i
.broadcast
->operand
= xchg2
;
5090 else if (i
.broadcast
->operand
== xchg2
)
5091 i
.broadcast
->operand
= xchg1
;
5095 if (i
.rounding
->operand
== xchg1
)
5096 i
.rounding
->operand
= xchg2
;
5097 else if (i
.rounding
->operand
== xchg2
)
5098 i
.rounding
->operand
= xchg1
;
5103 swap_operands (void)
5109 swap_2_operands (1, i
.operands
- 2);
5113 swap_2_operands (0, i
.operands
- 1);
5119 if (i
.mem_operands
== 2)
5121 const seg_entry
*temp_seg
;
5122 temp_seg
= i
.seg
[0];
5123 i
.seg
[0] = i
.seg
[1];
5124 i
.seg
[1] = temp_seg
;
5128 /* Try to ensure constant immediates are represented in the smallest
5133 char guess_suffix
= 0;
5137 guess_suffix
= i
.suffix
;
5138 else if (i
.reg_operands
)
5140 /* Figure out a suffix from the last register operand specified.
5141 We can't do this properly yet, i.e. excluding special register
5142 instances, but the following works for instructions with
5143 immediates. In any case, we can't set i.suffix yet. */
5144 for (op
= i
.operands
; --op
>= 0;)
5145 if (i
.types
[op
].bitfield
.class != Reg
)
5147 else if (i
.types
[op
].bitfield
.byte
)
5149 guess_suffix
= BYTE_MNEM_SUFFIX
;
5152 else if (i
.types
[op
].bitfield
.word
)
5154 guess_suffix
= WORD_MNEM_SUFFIX
;
5157 else if (i
.types
[op
].bitfield
.dword
)
5159 guess_suffix
= LONG_MNEM_SUFFIX
;
5162 else if (i
.types
[op
].bitfield
.qword
)
5164 guess_suffix
= QWORD_MNEM_SUFFIX
;
5168 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5169 guess_suffix
= WORD_MNEM_SUFFIX
;
5171 for (op
= i
.operands
; --op
>= 0;)
5172 if (operand_type_check (i
.types
[op
], imm
))
5174 switch (i
.op
[op
].imms
->X_op
)
5177 /* If a suffix is given, this operand may be shortened. */
5178 switch (guess_suffix
)
5180 case LONG_MNEM_SUFFIX
:
5181 i
.types
[op
].bitfield
.imm32
= 1;
5182 i
.types
[op
].bitfield
.imm64
= 1;
5184 case WORD_MNEM_SUFFIX
:
5185 i
.types
[op
].bitfield
.imm16
= 1;
5186 i
.types
[op
].bitfield
.imm32
= 1;
5187 i
.types
[op
].bitfield
.imm32s
= 1;
5188 i
.types
[op
].bitfield
.imm64
= 1;
5190 case BYTE_MNEM_SUFFIX
:
5191 i
.types
[op
].bitfield
.imm8
= 1;
5192 i
.types
[op
].bitfield
.imm8s
= 1;
5193 i
.types
[op
].bitfield
.imm16
= 1;
5194 i
.types
[op
].bitfield
.imm32
= 1;
5195 i
.types
[op
].bitfield
.imm32s
= 1;
5196 i
.types
[op
].bitfield
.imm64
= 1;
5200 /* If this operand is at most 16 bits, convert it
5201 to a signed 16 bit number before trying to see
5202 whether it will fit in an even smaller size.
5203 This allows a 16-bit operand such as $0xffe0 to
5204 be recognised as within Imm8S range. */
5205 if ((i
.types
[op
].bitfield
.imm16
)
5206 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5208 i
.op
[op
].imms
->X_add_number
=
5209 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5212 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5213 if ((i
.types
[op
].bitfield
.imm32
)
5214 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5217 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5218 ^ ((offsetT
) 1 << 31))
5219 - ((offsetT
) 1 << 31));
5223 = operand_type_or (i
.types
[op
],
5224 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5226 /* We must avoid matching of Imm32 templates when 64bit
5227 only immediate is available. */
5228 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5229 i
.types
[op
].bitfield
.imm32
= 0;
5236 /* Symbols and expressions. */
5238 /* Convert symbolic operand to proper sizes for matching, but don't
5239 prevent matching a set of insns that only supports sizes other
5240 than those matching the insn suffix. */
5242 i386_operand_type mask
, allowed
;
5243 const insn_template
*t
;
5245 operand_type_set (&mask
, 0);
5246 operand_type_set (&allowed
, 0);
5248 for (t
= current_templates
->start
;
5249 t
< current_templates
->end
;
5252 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5253 allowed
= operand_type_and (allowed
, anyimm
);
5255 switch (guess_suffix
)
5257 case QWORD_MNEM_SUFFIX
:
5258 mask
.bitfield
.imm64
= 1;
5259 mask
.bitfield
.imm32s
= 1;
5261 case LONG_MNEM_SUFFIX
:
5262 mask
.bitfield
.imm32
= 1;
5264 case WORD_MNEM_SUFFIX
:
5265 mask
.bitfield
.imm16
= 1;
5267 case BYTE_MNEM_SUFFIX
:
5268 mask
.bitfield
.imm8
= 1;
5273 allowed
= operand_type_and (mask
, allowed
);
5274 if (!operand_type_all_zero (&allowed
))
5275 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5282 /* Try to use the smallest displacement type too. */
5284 optimize_disp (void)
5288 for (op
= i
.operands
; --op
>= 0;)
5289 if (operand_type_check (i
.types
[op
], disp
))
5291 if (i
.op
[op
].disps
->X_op
== O_constant
)
5293 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5295 if (i
.types
[op
].bitfield
.disp16
5296 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5298 /* If this operand is at most 16 bits, convert
5299 to a signed 16 bit number and don't use 64bit
5301 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5302 i
.types
[op
].bitfield
.disp64
= 0;
5305 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5306 if (i
.types
[op
].bitfield
.disp32
5307 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5309 /* If this operand is at most 32 bits, convert
5310 to a signed 32 bit number and don't use 64bit
5312 op_disp
&= (((offsetT
) 2 << 31) - 1);
5313 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5314 i
.types
[op
].bitfield
.disp64
= 0;
5317 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5319 i
.types
[op
].bitfield
.disp8
= 0;
5320 i
.types
[op
].bitfield
.disp16
= 0;
5321 i
.types
[op
].bitfield
.disp32
= 0;
5322 i
.types
[op
].bitfield
.disp32s
= 0;
5323 i
.types
[op
].bitfield
.disp64
= 0;
5327 else if (flag_code
== CODE_64BIT
)
5329 if (fits_in_signed_long (op_disp
))
5331 i
.types
[op
].bitfield
.disp64
= 0;
5332 i
.types
[op
].bitfield
.disp32s
= 1;
5334 if (i
.prefix
[ADDR_PREFIX
]
5335 && fits_in_unsigned_long (op_disp
))
5336 i
.types
[op
].bitfield
.disp32
= 1;
5338 if ((i
.types
[op
].bitfield
.disp32
5339 || i
.types
[op
].bitfield
.disp32s
5340 || i
.types
[op
].bitfield
.disp16
)
5341 && fits_in_disp8 (op_disp
))
5342 i
.types
[op
].bitfield
.disp8
= 1;
5344 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5345 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5347 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5348 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5349 i
.types
[op
].bitfield
.disp8
= 0;
5350 i
.types
[op
].bitfield
.disp16
= 0;
5351 i
.types
[op
].bitfield
.disp32
= 0;
5352 i
.types
[op
].bitfield
.disp32s
= 0;
5353 i
.types
[op
].bitfield
.disp64
= 0;
5356 /* We only support 64bit displacement on constants. */
5357 i
.types
[op
].bitfield
.disp64
= 0;
5361 /* Return 1 if there is a match in broadcast bytes between operand
5362 GIVEN and instruction template T. */
5365 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5367 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5368 && i
.types
[given
].bitfield
.byte
)
5369 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5370 && i
.types
[given
].bitfield
.word
)
5371 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5372 && i
.types
[given
].bitfield
.dword
)
5373 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5374 && i
.types
[given
].bitfield
.qword
));
5377 /* Check if operands are valid for the instruction. */
5380 check_VecOperands (const insn_template
*t
)
5385 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5386 any one operand are implicity requiring AVX512VL support if the actual
5387 operand size is YMMword or XMMword. Since this function runs after
5388 template matching, there's no need to check for YMMword/XMMword in
5390 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5391 if (!cpu_flags_all_zero (&cpu
)
5392 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5393 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5395 for (op
= 0; op
< t
->operands
; ++op
)
5397 if (t
->operand_types
[op
].bitfield
.zmmword
5398 && (i
.types
[op
].bitfield
.ymmword
5399 || i
.types
[op
].bitfield
.xmmword
))
5401 i
.error
= unsupported
;
5407 /* Without VSIB byte, we can't have a vector register for index. */
5408 if (!t
->opcode_modifier
.vecsib
5410 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5411 || i
.index_reg
->reg_type
.bitfield
.ymmword
5412 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5414 i
.error
= unsupported_vector_index_register
;
5418 /* Check if default mask is allowed. */
5419 if (t
->opcode_modifier
.nodefmask
5420 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5422 i
.error
= no_default_mask
;
5426 /* For VSIB byte, we need a vector register for index, and all vector
5427 registers must be distinct. */
5428 if (t
->opcode_modifier
.vecsib
)
5431 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5432 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5433 || (t
->opcode_modifier
.vecsib
== VecSIB256
5434 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5435 || (t
->opcode_modifier
.vecsib
== VecSIB512
5436 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5438 i
.error
= invalid_vsib_address
;
5442 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5443 if (i
.reg_operands
== 2 && !i
.mask
)
5445 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5446 gas_assert (i
.types
[0].bitfield
.xmmword
5447 || i
.types
[0].bitfield
.ymmword
);
5448 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5449 gas_assert (i
.types
[2].bitfield
.xmmword
5450 || i
.types
[2].bitfield
.ymmword
);
5451 if (operand_check
== check_none
)
5453 if (register_number (i
.op
[0].regs
)
5454 != register_number (i
.index_reg
)
5455 && register_number (i
.op
[2].regs
)
5456 != register_number (i
.index_reg
)
5457 && register_number (i
.op
[0].regs
)
5458 != register_number (i
.op
[2].regs
))
5460 if (operand_check
== check_error
)
5462 i
.error
= invalid_vector_register_set
;
5465 as_warn (_("mask, index, and destination registers should be distinct"));
5467 else if (i
.reg_operands
== 1 && i
.mask
)
5469 if (i
.types
[1].bitfield
.class == RegSIMD
5470 && (i
.types
[1].bitfield
.xmmword
5471 || i
.types
[1].bitfield
.ymmword
5472 || i
.types
[1].bitfield
.zmmword
)
5473 && (register_number (i
.op
[1].regs
)
5474 == register_number (i
.index_reg
)))
5476 if (operand_check
== check_error
)
5478 i
.error
= invalid_vector_register_set
;
5481 if (operand_check
!= check_none
)
5482 as_warn (_("index and destination registers should be distinct"));
5487 /* Check if broadcast is supported by the instruction and is applied
5488 to the memory operand. */
5491 i386_operand_type type
, overlap
;
5493 /* Check if specified broadcast is supported in this instruction,
5494 and its broadcast bytes match the memory operand. */
5495 op
= i
.broadcast
->operand
;
5496 if (!t
->opcode_modifier
.broadcast
5497 || !(i
.flags
[op
] & Operand_Mem
)
5498 || (!i
.types
[op
].bitfield
.unspecified
5499 && !match_broadcast_size (t
, op
)))
5502 i
.error
= unsupported_broadcast
;
5506 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5507 * i
.broadcast
->type
);
5508 operand_type_set (&type
, 0);
5509 switch (i
.broadcast
->bytes
)
5512 type
.bitfield
.word
= 1;
5515 type
.bitfield
.dword
= 1;
5518 type
.bitfield
.qword
= 1;
5521 type
.bitfield
.xmmword
= 1;
5524 type
.bitfield
.ymmword
= 1;
5527 type
.bitfield
.zmmword
= 1;
5533 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5534 if (operand_type_all_zero (&overlap
))
5537 if (t
->opcode_modifier
.checkregsize
)
5541 type
.bitfield
.baseindex
= 1;
5542 for (j
= 0; j
< i
.operands
; ++j
)
5545 && !operand_type_register_match(i
.types
[j
],
5546 t
->operand_types
[j
],
5548 t
->operand_types
[op
]))
5553 /* If broadcast is supported in this instruction, we need to check if
5554 operand of one-element size isn't specified without broadcast. */
5555 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5557 /* Find memory operand. */
5558 for (op
= 0; op
< i
.operands
; op
++)
5559 if (i
.flags
[op
] & Operand_Mem
)
5561 gas_assert (op
< i
.operands
);
5562 /* Check size of the memory operand. */
5563 if (match_broadcast_size (t
, op
))
5565 i
.error
= broadcast_needed
;
5570 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5572 /* Check if requested masking is supported. */
5575 switch (t
->opcode_modifier
.masking
)
5579 case MERGING_MASKING
:
5580 if (i
.mask
->zeroing
)
5583 i
.error
= unsupported_masking
;
5587 case DYNAMIC_MASKING
:
5588 /* Memory destinations allow only merging masking. */
5589 if (i
.mask
->zeroing
&& i
.mem_operands
)
5591 /* Find memory operand. */
5592 for (op
= 0; op
< i
.operands
; op
++)
5593 if (i
.flags
[op
] & Operand_Mem
)
5595 gas_assert (op
< i
.operands
);
5596 if (op
== i
.operands
- 1)
5598 i
.error
= unsupported_masking
;
5608 /* Check if masking is applied to dest operand. */
5609 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5611 i
.error
= mask_not_on_destination
;
5618 if (!t
->opcode_modifier
.sae
5619 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5621 i
.error
= unsupported_rc_sae
;
5624 /* If the instruction has several immediate operands and one of
5625 them is rounding, the rounding operand should be the last
5626 immediate operand. */
5627 if (i
.imm_operands
> 1
5628 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5630 i
.error
= rc_sae_operand_not_last_imm
;
5635 /* Check vector Disp8 operand. */
5636 if (t
->opcode_modifier
.disp8memshift
5637 && i
.disp_encoding
!= disp_encoding_32bit
)
5640 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5641 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5642 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5645 const i386_operand_type
*type
= NULL
;
5648 for (op
= 0; op
< i
.operands
; op
++)
5649 if (i
.flags
[op
] & Operand_Mem
)
5651 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5652 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5653 else if (t
->operand_types
[op
].bitfield
.xmmword
5654 + t
->operand_types
[op
].bitfield
.ymmword
5655 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5656 type
= &t
->operand_types
[op
];
5657 else if (!i
.types
[op
].bitfield
.unspecified
)
5658 type
= &i
.types
[op
];
5660 else if (i
.types
[op
].bitfield
.class == RegSIMD
5661 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5663 if (i
.types
[op
].bitfield
.zmmword
)
5665 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5667 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5673 if (type
->bitfield
.zmmword
)
5675 else if (type
->bitfield
.ymmword
)
5677 else if (type
->bitfield
.xmmword
)
5681 /* For the check in fits_in_disp8(). */
5682 if (i
.memshift
== 0)
5686 for (op
= 0; op
< i
.operands
; op
++)
5687 if (operand_type_check (i
.types
[op
], disp
)
5688 && i
.op
[op
].disps
->X_op
== O_constant
)
5690 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5692 i
.types
[op
].bitfield
.disp8
= 1;
5695 i
.types
[op
].bitfield
.disp8
= 0;
5704 /* Check if operands are valid for the instruction. Update VEX
5708 VEX_check_operands (const insn_template
*t
)
5710 if (i
.vec_encoding
== vex_encoding_evex
)
5712 /* This instruction must be encoded with EVEX prefix. */
5713 if (!is_evex_encoding (t
))
5715 i
.error
= unsupported
;
5721 if (!t
->opcode_modifier
.vex
)
5723 /* This instruction template doesn't have VEX prefix. */
5724 if (i
.vec_encoding
!= vex_encoding_default
)
5726 i
.error
= unsupported
;
5732 /* Check the special Imm4 cases; must be the first operand. */
5733 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
5735 if (i
.op
[0].imms
->X_op
!= O_constant
5736 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5742 /* Turn off Imm<N> so that update_imm won't complain. */
5743 operand_type_set (&i
.types
[0], 0);
5749 static const insn_template
*
5750 match_template (char mnem_suffix
)
5752 /* Points to template once we've found it. */
5753 const insn_template
*t
;
5754 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5755 i386_operand_type overlap4
;
5756 unsigned int found_reverse_match
;
5757 i386_opcode_modifier suffix_check
;
5758 i386_operand_type operand_types
[MAX_OPERANDS
];
5759 int addr_prefix_disp
;
5760 unsigned int j
, size_match
, check_register
;
5761 enum i386_error specific_error
= 0;
5763 #if MAX_OPERANDS != 5
5764 # error "MAX_OPERANDS must be 5."
5767 found_reverse_match
= 0;
5768 addr_prefix_disp
= -1;
5770 /* Prepare for mnemonic suffix check. */
5771 memset (&suffix_check
, 0, sizeof (suffix_check
));
5772 switch (mnem_suffix
)
5774 case BYTE_MNEM_SUFFIX
:
5775 suffix_check
.no_bsuf
= 1;
5777 case WORD_MNEM_SUFFIX
:
5778 suffix_check
.no_wsuf
= 1;
5780 case SHORT_MNEM_SUFFIX
:
5781 suffix_check
.no_ssuf
= 1;
5783 case LONG_MNEM_SUFFIX
:
5784 suffix_check
.no_lsuf
= 1;
5786 case QWORD_MNEM_SUFFIX
:
5787 suffix_check
.no_qsuf
= 1;
5790 /* NB: In Intel syntax, normally we can check for memory operand
5791 size when there is no mnemonic suffix. But jmp and call have
5792 2 different encodings with Dword memory operand size, one with
5793 No_ldSuf and the other without. i.suffix is set to
5794 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
5795 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5796 suffix_check
.no_ldsuf
= 1;
5799 /* Must have right number of operands. */
5800 i
.error
= number_of_operands_mismatch
;
5802 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5804 addr_prefix_disp
= -1;
5805 found_reverse_match
= 0;
5807 if (i
.operands
!= t
->operands
)
5810 /* Check processor support. */
5811 i
.error
= unsupported
;
5812 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
5815 /* Check AT&T mnemonic. */
5816 i
.error
= unsupported_with_intel_mnemonic
;
5817 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5820 /* Check AT&T/Intel syntax. */
5821 i
.error
= unsupported_syntax
;
5822 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5823 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
5826 /* Check Intel64/AMD64 ISA. */
5830 /* Default: Don't accept Intel64. */
5831 if (t
->opcode_modifier
.isa64
== INTEL64
)
5835 /* -mamd64: Don't accept Intel64 and Intel64 only. */
5836 if (t
->opcode_modifier
.isa64
>= INTEL64
)
5840 /* -mintel64: Don't accept AMD64. */
5841 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
5846 /* Check the suffix. */
5847 i
.error
= invalid_instruction_suffix
;
5848 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5849 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5850 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5851 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5852 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5853 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
5856 size_match
= operand_size_match (t
);
5860 /* This is intentionally not
5862 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
5864 as the case of a missing * on the operand is accepted (perhaps with
5865 a warning, issued further down). */
5866 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
5868 i
.error
= operand_type_mismatch
;
5872 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5873 operand_types
[j
] = t
->operand_types
[j
];
5875 /* In general, don't allow 64-bit operands in 32-bit mode. */
5876 if (i
.suffix
== QWORD_MNEM_SUFFIX
5877 && flag_code
!= CODE_64BIT
5879 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
5880 && !t
->opcode_modifier
.broadcast
5881 && !intel_float_operand (t
->name
))
5882 : intel_float_operand (t
->name
) != 2)
5883 && ((operand_types
[0].bitfield
.class != RegMMX
5884 && operand_types
[0].bitfield
.class != RegSIMD
)
5885 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5886 && operand_types
[t
->operands
> 1].bitfield
.class != RegSIMD
))
5887 && (t
->base_opcode
!= 0x0fc7
5888 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5891 /* In general, don't allow 32-bit operands on pre-386. */
5892 else if (i
.suffix
== LONG_MNEM_SUFFIX
5893 && !cpu_arch_flags
.bitfield
.cpui386
5895 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
5896 && !intel_float_operand (t
->name
))
5897 : intel_float_operand (t
->name
) != 2)
5898 && ((operand_types
[0].bitfield
.class != RegMMX
5899 && operand_types
[0].bitfield
.class != RegSIMD
)
5900 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5901 && operand_types
[t
->operands
> 1].bitfield
.class
5905 /* Do not verify operands when there are none. */
5909 /* We've found a match; break out of loop. */
5913 if (!t
->opcode_modifier
.jump
5914 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
5916 /* There should be only one Disp operand. */
5917 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5918 if (operand_type_check (operand_types
[j
], disp
))
5920 if (j
< MAX_OPERANDS
)
5922 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
5924 addr_prefix_disp
= j
;
5926 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
5927 operand into Disp32/Disp32/Disp16/Disp32 operand. */
5931 override
= !override
;
5934 if (operand_types
[j
].bitfield
.disp32
5935 && operand_types
[j
].bitfield
.disp16
)
5937 operand_types
[j
].bitfield
.disp16
= override
;
5938 operand_types
[j
].bitfield
.disp32
= !override
;
5940 operand_types
[j
].bitfield
.disp32s
= 0;
5941 operand_types
[j
].bitfield
.disp64
= 0;
5945 if (operand_types
[j
].bitfield
.disp32s
5946 || operand_types
[j
].bitfield
.disp64
)
5948 operand_types
[j
].bitfield
.disp64
&= !override
;
5949 operand_types
[j
].bitfield
.disp32s
&= !override
;
5950 operand_types
[j
].bitfield
.disp32
= override
;
5952 operand_types
[j
].bitfield
.disp16
= 0;
5958 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5959 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5962 /* We check register size if needed. */
5963 if (t
->opcode_modifier
.checkregsize
)
5965 check_register
= (1 << t
->operands
) - 1;
5967 check_register
&= ~(1 << i
.broadcast
->operand
);
5972 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5973 switch (t
->operands
)
5976 if (!operand_type_match (overlap0
, i
.types
[0]))
5980 /* xchg %eax, %eax is a special case. It is an alias for nop
5981 only in 32bit mode and we can use opcode 0x90. In 64bit
5982 mode, we can't use 0x90 for xchg %eax, %eax since it should
5983 zero-extend %eax to %rax. */
5984 if (flag_code
== CODE_64BIT
5985 && t
->base_opcode
== 0x90
5986 && i
.types
[0].bitfield
.instance
== Accum
5987 && i
.types
[0].bitfield
.dword
5988 && i
.types
[1].bitfield
.instance
== Accum
5989 && i
.types
[1].bitfield
.dword
)
5991 /* xrelease mov %eax, <disp> is another special case. It must not
5992 match the accumulator-only encoding of mov. */
5993 if (flag_code
!= CODE_64BIT
5995 && t
->base_opcode
== 0xa0
5996 && i
.types
[0].bitfield
.instance
== Accum
5997 && (i
.flags
[1] & Operand_Mem
))
6002 if (!(size_match
& MATCH_STRAIGHT
))
6004 /* Reverse direction of operands if swapping is possible in the first
6005 place (operands need to be symmetric) and
6006 - the load form is requested, and the template is a store form,
6007 - the store form is requested, and the template is a load form,
6008 - the non-default (swapped) form is requested. */
6009 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6010 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6011 && !operand_type_all_zero (&overlap1
))
6012 switch (i
.dir_encoding
)
6014 case dir_encoding_load
:
6015 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6016 || t
->opcode_modifier
.regmem
)
6020 case dir_encoding_store
:
6021 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6022 && !t
->opcode_modifier
.regmem
)
6026 case dir_encoding_swap
:
6029 case dir_encoding_default
:
6032 /* If we want store form, we skip the current load. */
6033 if ((i
.dir_encoding
== dir_encoding_store
6034 || i
.dir_encoding
== dir_encoding_swap
)
6035 && i
.mem_operands
== 0
6036 && t
->opcode_modifier
.load
)
6041 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6042 if (!operand_type_match (overlap0
, i
.types
[0])
6043 || !operand_type_match (overlap1
, i
.types
[1])
6044 || ((check_register
& 3) == 3
6045 && !operand_type_register_match (i
.types
[0],
6050 /* Check if other direction is valid ... */
6051 if (!t
->opcode_modifier
.d
)
6055 if (!(size_match
& MATCH_REVERSE
))
6057 /* Try reversing direction of operands. */
6058 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6059 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6060 if (!operand_type_match (overlap0
, i
.types
[0])
6061 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6063 && !operand_type_register_match (i
.types
[0],
6064 operand_types
[i
.operands
- 1],
6065 i
.types
[i
.operands
- 1],
6068 /* Does not match either direction. */
6071 /* found_reverse_match holds which of D or FloatR
6073 if (!t
->opcode_modifier
.d
)
6074 found_reverse_match
= 0;
6075 else if (operand_types
[0].bitfield
.tbyte
)
6076 found_reverse_match
= Opcode_FloatD
;
6077 else if (operand_types
[0].bitfield
.xmmword
6078 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6079 || operand_types
[0].bitfield
.class == RegMMX
6080 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6081 || is_any_vex_encoding(t
))
6082 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6083 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6085 found_reverse_match
= Opcode_D
;
6086 if (t
->opcode_modifier
.floatr
)
6087 found_reverse_match
|= Opcode_FloatR
;
6091 /* Found a forward 2 operand match here. */
6092 switch (t
->operands
)
6095 overlap4
= operand_type_and (i
.types
[4],
6099 overlap3
= operand_type_and (i
.types
[3],
6103 overlap2
= operand_type_and (i
.types
[2],
6108 switch (t
->operands
)
6111 if (!operand_type_match (overlap4
, i
.types
[4])
6112 || !operand_type_register_match (i
.types
[3],
6119 if (!operand_type_match (overlap3
, i
.types
[3])
6120 || ((check_register
& 0xa) == 0xa
6121 && !operand_type_register_match (i
.types
[1],
6125 || ((check_register
& 0xc) == 0xc
6126 && !operand_type_register_match (i
.types
[2],
6133 /* Here we make use of the fact that there are no
6134 reverse match 3 operand instructions. */
6135 if (!operand_type_match (overlap2
, i
.types
[2])
6136 || ((check_register
& 5) == 5
6137 && !operand_type_register_match (i
.types
[0],
6141 || ((check_register
& 6) == 6
6142 && !operand_type_register_match (i
.types
[1],
6150 /* Found either forward/reverse 2, 3 or 4 operand match here:
6151 slip through to break. */
6154 /* Check if vector and VEX operands are valid. */
6155 if (check_VecOperands (t
) || VEX_check_operands (t
))
6157 specific_error
= i
.error
;
6161 /* We've found a match; break out of loop. */
6165 if (t
== current_templates
->end
)
6167 /* We found no match. */
6168 const char *err_msg
;
6169 switch (specific_error
? specific_error
: i
.error
)
6173 case operand_size_mismatch
:
6174 err_msg
= _("operand size mismatch");
6176 case operand_type_mismatch
:
6177 err_msg
= _("operand type mismatch");
6179 case register_type_mismatch
:
6180 err_msg
= _("register type mismatch");
6182 case number_of_operands_mismatch
:
6183 err_msg
= _("number of operands mismatch");
6185 case invalid_instruction_suffix
:
6186 err_msg
= _("invalid instruction suffix");
6189 err_msg
= _("constant doesn't fit in 4 bits");
6191 case unsupported_with_intel_mnemonic
:
6192 err_msg
= _("unsupported with Intel mnemonic");
6194 case unsupported_syntax
:
6195 err_msg
= _("unsupported syntax");
6198 as_bad (_("unsupported instruction `%s'"),
6199 current_templates
->start
->name
);
6201 case invalid_vsib_address
:
6202 err_msg
= _("invalid VSIB address");
6204 case invalid_vector_register_set
:
6205 err_msg
= _("mask, index, and destination registers must be distinct");
6207 case unsupported_vector_index_register
:
6208 err_msg
= _("unsupported vector index register");
6210 case unsupported_broadcast
:
6211 err_msg
= _("unsupported broadcast");
6213 case broadcast_needed
:
6214 err_msg
= _("broadcast is needed for operand of such type");
6216 case unsupported_masking
:
6217 err_msg
= _("unsupported masking");
6219 case mask_not_on_destination
:
6220 err_msg
= _("mask not on destination operand");
6222 case no_default_mask
:
6223 err_msg
= _("default mask isn't allowed");
6225 case unsupported_rc_sae
:
6226 err_msg
= _("unsupported static rounding/sae");
6228 case rc_sae_operand_not_last_imm
:
6230 err_msg
= _("RC/SAE operand must precede immediate operands");
6232 err_msg
= _("RC/SAE operand must follow immediate operands");
6234 case invalid_register_operand
:
6235 err_msg
= _("invalid register operand");
6238 as_bad (_("%s for `%s'"), err_msg
,
6239 current_templates
->start
->name
);
6243 if (!quiet_warnings
)
6246 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6247 as_warn (_("indirect %s without `*'"), t
->name
);
6249 if (t
->opcode_modifier
.isprefix
6250 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6252 /* Warn them that a data or address size prefix doesn't
6253 affect assembly of the next line of code. */
6254 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6258 /* Copy the template we found. */
6261 if (addr_prefix_disp
!= -1)
6262 i
.tm
.operand_types
[addr_prefix_disp
]
6263 = operand_types
[addr_prefix_disp
];
6265 if (found_reverse_match
)
6267 /* If we found a reverse match we must alter the opcode direction
6268 bit and clear/flip the regmem modifier one. found_reverse_match
6269 holds bits to change (different for int & float insns). */
6271 i
.tm
.base_opcode
^= found_reverse_match
;
6273 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6274 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6276 /* Certain SIMD insns have their load forms specified in the opcode
6277 table, and hence we need to _set_ RegMem instead of clearing it.
6278 We need to avoid setting the bit though on insns like KMOVW. */
6279 i
.tm
.opcode_modifier
.regmem
6280 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6281 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6282 && !i
.tm
.opcode_modifier
.regmem
;
6291 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6292 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6294 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6296 as_bad (_("`%s' operand %u must use `%ses' segment"),
6298 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6303 /* There's only ever one segment override allowed per instruction.
6304 This instruction possibly has a legal segment override on the
6305 second operand, so copy the segment to where non-string
6306 instructions store it, allowing common code. */
6307 i
.seg
[op
] = i
.seg
[1];
6313 process_suffix (void)
6315 /* If matched instruction specifies an explicit instruction mnemonic
6317 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6318 i
.suffix
= WORD_MNEM_SUFFIX
;
6319 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6320 i
.suffix
= LONG_MNEM_SUFFIX
;
6321 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6322 i
.suffix
= QWORD_MNEM_SUFFIX
;
6323 else if (i
.reg_operands
6324 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6325 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6327 unsigned int numop
= i
.operands
;
6329 /* movsx/movzx want only their source operand considered here, for the
6330 ambiguity checking below. The suffix will be replaced afterwards
6331 to represent the destination (register). */
6332 if (((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
)
6333 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6336 /* If there's no instruction mnemonic suffix we try to invent one
6337 based on GPR operands. */
6340 /* We take i.suffix from the last register operand specified,
6341 Destination register type is more significant than source
6342 register type. crc32 in SSE4.2 prefers source register
6344 unsigned int op
= i
.tm
.base_opcode
!= 0xf20f38f0 ? i
.operands
: 1;
6347 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6348 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6350 if (i
.types
[op
].bitfield
.class != Reg
)
6352 if (i
.types
[op
].bitfield
.byte
)
6353 i
.suffix
= BYTE_MNEM_SUFFIX
;
6354 else if (i
.types
[op
].bitfield
.word
)
6355 i
.suffix
= WORD_MNEM_SUFFIX
;
6356 else if (i
.types
[op
].bitfield
.dword
)
6357 i
.suffix
= LONG_MNEM_SUFFIX
;
6358 else if (i
.types
[op
].bitfield
.qword
)
6359 i
.suffix
= QWORD_MNEM_SUFFIX
;
6365 /* As an exception, movsx/movzx silently default to a byte source
6367 if ((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
6368 && !i
.suffix
&& !intel_syntax
)
6369 i
.suffix
= BYTE_MNEM_SUFFIX
;
6371 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6374 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6375 && i
.tm
.opcode_modifier
.no_bsuf
)
6377 else if (!check_byte_reg ())
6380 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6383 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6384 && i
.tm
.opcode_modifier
.no_lsuf
6385 && !i
.tm
.opcode_modifier
.todword
6386 && !i
.tm
.opcode_modifier
.toqword
)
6388 else if (!check_long_reg ())
6391 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6394 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6395 && i
.tm
.opcode_modifier
.no_qsuf
6396 && !i
.tm
.opcode_modifier
.todword
6397 && !i
.tm
.opcode_modifier
.toqword
)
6399 else if (!check_qword_reg ())
6402 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6405 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6406 && i
.tm
.opcode_modifier
.no_wsuf
)
6408 else if (!check_word_reg ())
6411 else if (intel_syntax
6412 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6413 /* Do nothing if the instruction is going to ignore the prefix. */
6418 /* Undo the movsx/movzx change done above. */
6421 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
6424 i
.suffix
= stackop_size
;
6425 if (stackop_size
== LONG_MNEM_SUFFIX
)
6427 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6428 .code16gcc directive to support 16-bit mode with
6429 32-bit address. For IRET without a suffix, generate
6430 16-bit IRET (opcode 0xcf) to return from an interrupt
6432 if (i
.tm
.base_opcode
== 0xcf)
6434 i
.suffix
= WORD_MNEM_SUFFIX
;
6435 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6437 /* Warn about changed behavior for segment register push/pop. */
6438 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6439 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6444 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6445 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6446 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6447 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6448 && i
.tm
.extension_opcode
<= 3)))
6453 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6455 i
.suffix
= QWORD_MNEM_SUFFIX
;
6460 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6461 i
.suffix
= LONG_MNEM_SUFFIX
;
6464 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6465 i
.suffix
= WORD_MNEM_SUFFIX
;
6471 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6472 /* Also cover lret/retf/iret in 64-bit mode. */
6473 || (flag_code
== CODE_64BIT
6474 && !i
.tm
.opcode_modifier
.no_lsuf
6475 && !i
.tm
.opcode_modifier
.no_qsuf
))
6476 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6477 /* Accept FLDENV et al without suffix. */
6478 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6480 unsigned int suffixes
, evex
= 0;
6482 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6483 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6485 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6487 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6489 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6491 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6494 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6495 also suitable for AT&T syntax mode, it was requested that this be
6496 restricted to just Intel syntax. */
6497 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
)
6501 for (op
= 0; op
< i
.tm
.operands
; ++op
)
6503 if (is_evex_encoding (&i
.tm
)
6504 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6506 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6507 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
6508 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6509 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
6510 if (!i
.tm
.opcode_modifier
.evex
6511 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
6512 i
.tm
.opcode_modifier
.evex
= EVEX512
;
6515 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
6516 + i
.tm
.operand_types
[op
].bitfield
.ymmword
6517 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
6520 /* Any properly sized operand disambiguates the insn. */
6521 if (i
.types
[op
].bitfield
.xmmword
6522 || i
.types
[op
].bitfield
.ymmword
6523 || i
.types
[op
].bitfield
.zmmword
)
6525 suffixes
&= ~(7 << 6);
6530 if ((i
.flags
[op
] & Operand_Mem
)
6531 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
6533 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
6535 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6537 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6539 if (is_evex_encoding (&i
.tm
))
6545 /* Are multiple suffixes / operand sizes allowed? */
6546 if (suffixes
& (suffixes
- 1))
6549 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6550 || operand_check
== check_error
))
6552 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6555 if (operand_check
== check_error
)
6557 as_bad (_("no instruction mnemonic suffix given and "
6558 "no register operands; can't size `%s'"), i
.tm
.name
);
6561 if (operand_check
== check_warning
)
6562 as_warn (_("%s; using default for `%s'"),
6564 ? _("ambiguous operand size")
6565 : _("no instruction mnemonic suffix given and "
6566 "no register operands"),
6569 if (i
.tm
.opcode_modifier
.floatmf
)
6570 i
.suffix
= SHORT_MNEM_SUFFIX
;
6571 else if ((i
.tm
.base_opcode
| 8) == 0xfbe
6572 || (i
.tm
.base_opcode
== 0x63
6573 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6574 /* handled below */;
6576 i
.tm
.opcode_modifier
.evex
= evex
;
6577 else if (flag_code
== CODE_16BIT
)
6578 i
.suffix
= WORD_MNEM_SUFFIX
;
6579 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
6580 i
.suffix
= LONG_MNEM_SUFFIX
;
6582 i
.suffix
= QWORD_MNEM_SUFFIX
;
6586 if ((i
.tm
.base_opcode
| 8) == 0xfbe
6587 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6589 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
6590 In AT&T syntax, if there is no suffix (warned about above), the default
6591 will be byte extension. */
6592 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
6593 i
.tm
.base_opcode
|= 1;
6595 /* For further processing, the suffix should represent the destination
6596 (register). This is already the case when one was used with
6597 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
6598 no suffix to begin with. */
6599 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
6601 if (i
.types
[1].bitfield
.word
)
6602 i
.suffix
= WORD_MNEM_SUFFIX
;
6603 else if (i
.types
[1].bitfield
.qword
)
6604 i
.suffix
= QWORD_MNEM_SUFFIX
;
6606 i
.suffix
= LONG_MNEM_SUFFIX
;
6608 i
.tm
.opcode_modifier
.w
= 0;
6612 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
6613 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
6614 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
6616 /* Change the opcode based on the operand size given by i.suffix. */
6619 /* Size floating point instruction. */
6620 case LONG_MNEM_SUFFIX
:
6621 if (i
.tm
.opcode_modifier
.floatmf
)
6623 i
.tm
.base_opcode
^= 4;
6627 case WORD_MNEM_SUFFIX
:
6628 case QWORD_MNEM_SUFFIX
:
6629 /* It's not a byte, select word/dword operation. */
6630 if (i
.tm
.opcode_modifier
.w
)
6633 i
.tm
.base_opcode
|= 8;
6635 i
.tm
.base_opcode
|= 1;
6638 case SHORT_MNEM_SUFFIX
:
6639 /* Now select between word & dword operations via the operand
6640 size prefix, except for instructions that will ignore this
6642 if (i
.suffix
!= QWORD_MNEM_SUFFIX
6643 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6644 && !i
.tm
.opcode_modifier
.floatmf
6645 && !is_any_vex_encoding (&i
.tm
)
6646 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6647 || (flag_code
== CODE_64BIT
6648 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
6650 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6652 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
6653 prefix
= ADDR_PREFIX_OPCODE
;
6655 if (!add_prefix (prefix
))
6659 /* Set mode64 for an operand. */
6660 if (i
.suffix
== QWORD_MNEM_SUFFIX
6661 && flag_code
== CODE_64BIT
6662 && !i
.tm
.opcode_modifier
.norex64
6663 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6665 && ! (i
.operands
== 2
6666 && i
.tm
.base_opcode
== 0x90
6667 && i
.tm
.extension_opcode
== None
6668 && i
.types
[0].bitfield
.instance
== Accum
6669 && i
.types
[0].bitfield
.qword
6670 && i
.types
[1].bitfield
.instance
== Accum
6671 && i
.types
[1].bitfield
.qword
))
6677 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
6679 gas_assert (!i
.suffix
);
6680 gas_assert (i
.reg_operands
);
6682 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6685 /* The address size override prefix changes the size of the
6687 if (flag_code
== CODE_64BIT
6688 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6690 as_bad (_("16-bit addressing unavailable for `%s'"),
6695 if ((flag_code
== CODE_32BIT
6696 ? i
.op
[0].regs
->reg_type
.bitfield
.word
6697 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
6698 && !add_prefix (ADDR_PREFIX_OPCODE
))
6703 /* Check invalid register operand when the address size override
6704 prefix changes the size of register operands. */
6706 enum { need_word
, need_dword
, need_qword
} need
;
6708 if (flag_code
== CODE_32BIT
)
6709 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6710 else if (i
.prefix
[ADDR_PREFIX
])
6713 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6715 for (op
= 0; op
< i
.operands
; op
++)
6717 if (i
.types
[op
].bitfield
.class != Reg
)
6723 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6727 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6731 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
6736 as_bad (_("invalid register operand size for `%s'"),
6747 check_byte_reg (void)
6751 for (op
= i
.operands
; --op
>= 0;)
6753 /* Skip non-register operands. */
6754 if (i
.types
[op
].bitfield
.class != Reg
)
6757 /* If this is an eight bit register, it's OK. If it's the 16 or
6758 32 bit version of an eight bit register, we will just use the
6759 low portion, and that's OK too. */
6760 if (i
.types
[op
].bitfield
.byte
)
6763 /* I/O port address operands are OK too. */
6764 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
6765 && i
.tm
.operand_types
[op
].bitfield
.word
)
6768 /* crc32 only wants its source operand checked here. */
6769 if (i
.tm
.base_opcode
== 0xf20f38f0 && op
)
6772 /* Any other register is bad. */
6773 if (i
.types
[op
].bitfield
.class == Reg
6774 || i
.types
[op
].bitfield
.class == RegMMX
6775 || i
.types
[op
].bitfield
.class == RegSIMD
6776 || i
.types
[op
].bitfield
.class == SReg
6777 || i
.types
[op
].bitfield
.class == RegCR
6778 || i
.types
[op
].bitfield
.class == RegDR
6779 || i
.types
[op
].bitfield
.class == RegTR
)
6781 as_bad (_("`%s%s' not allowed with `%s%c'"),
6783 i
.op
[op
].regs
->reg_name
,
6793 check_long_reg (void)
6797 for (op
= i
.operands
; --op
>= 0;)
6798 /* Skip non-register operands. */
6799 if (i
.types
[op
].bitfield
.class != Reg
)
6801 /* Reject eight bit registers, except where the template requires
6802 them. (eg. movzb) */
6803 else if (i
.types
[op
].bitfield
.byte
6804 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6805 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6806 && (i
.tm
.operand_types
[op
].bitfield
.word
6807 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6809 as_bad (_("`%s%s' not allowed with `%s%c'"),
6811 i
.op
[op
].regs
->reg_name
,
6816 /* Error if the e prefix on a general reg is missing. */
6817 else if (i
.types
[op
].bitfield
.word
6818 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6819 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6820 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6822 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6823 register_prefix
, i
.op
[op
].regs
->reg_name
,
6827 /* Warn if the r prefix on a general reg is present. */
6828 else if (i
.types
[op
].bitfield
.qword
6829 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6830 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6831 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6834 && i
.tm
.opcode_modifier
.toqword
6835 && i
.types
[0].bitfield
.class != RegSIMD
)
6837 /* Convert to QWORD. We want REX byte. */
6838 i
.suffix
= QWORD_MNEM_SUFFIX
;
6842 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6843 register_prefix
, i
.op
[op
].regs
->reg_name
,
6852 check_qword_reg (void)
6856 for (op
= i
.operands
; --op
>= 0; )
6857 /* Skip non-register operands. */
6858 if (i
.types
[op
].bitfield
.class != Reg
)
6860 /* Reject eight bit registers, except where the template requires
6861 them. (eg. movzb) */
6862 else if (i
.types
[op
].bitfield
.byte
6863 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6864 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6865 && (i
.tm
.operand_types
[op
].bitfield
.word
6866 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6868 as_bad (_("`%s%s' not allowed with `%s%c'"),
6870 i
.op
[op
].regs
->reg_name
,
6875 /* Warn if the r prefix on a general reg is missing. */
6876 else if ((i
.types
[op
].bitfield
.word
6877 || i
.types
[op
].bitfield
.dword
)
6878 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6879 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6880 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6882 /* Prohibit these changes in the 64bit mode, since the
6883 lowering is more complicated. */
6885 && i
.tm
.opcode_modifier
.todword
6886 && i
.types
[0].bitfield
.class != RegSIMD
)
6888 /* Convert to DWORD. We don't want REX byte. */
6889 i
.suffix
= LONG_MNEM_SUFFIX
;
6893 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6894 register_prefix
, i
.op
[op
].regs
->reg_name
,
6903 check_word_reg (void)
6906 for (op
= i
.operands
; --op
>= 0;)
6907 /* Skip non-register operands. */
6908 if (i
.types
[op
].bitfield
.class != Reg
)
6910 /* Reject eight bit registers, except where the template requires
6911 them. (eg. movzb) */
6912 else if (i
.types
[op
].bitfield
.byte
6913 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6914 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6915 && (i
.tm
.operand_types
[op
].bitfield
.word
6916 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6918 as_bad (_("`%s%s' not allowed with `%s%c'"),
6920 i
.op
[op
].regs
->reg_name
,
6925 /* Error if the e or r prefix on a general reg is present. */
6926 else if ((i
.types
[op
].bitfield
.dword
6927 || i
.types
[op
].bitfield
.qword
)
6928 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6929 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6930 && i
.tm
.operand_types
[op
].bitfield
.word
)
6932 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6933 register_prefix
, i
.op
[op
].regs
->reg_name
,
6941 update_imm (unsigned int j
)
6943 i386_operand_type overlap
= i
.types
[j
];
6944 if ((overlap
.bitfield
.imm8
6945 || overlap
.bitfield
.imm8s
6946 || overlap
.bitfield
.imm16
6947 || overlap
.bitfield
.imm32
6948 || overlap
.bitfield
.imm32s
6949 || overlap
.bitfield
.imm64
)
6950 && !operand_type_equal (&overlap
, &imm8
)
6951 && !operand_type_equal (&overlap
, &imm8s
)
6952 && !operand_type_equal (&overlap
, &imm16
)
6953 && !operand_type_equal (&overlap
, &imm32
)
6954 && !operand_type_equal (&overlap
, &imm32s
)
6955 && !operand_type_equal (&overlap
, &imm64
))
6959 i386_operand_type temp
;
6961 operand_type_set (&temp
, 0);
6962 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6964 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6965 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6967 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6968 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6969 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6971 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6972 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6975 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6978 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6979 || operand_type_equal (&overlap
, &imm16_32
)
6980 || operand_type_equal (&overlap
, &imm16_32s
))
6982 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6987 if (!operand_type_equal (&overlap
, &imm8
)
6988 && !operand_type_equal (&overlap
, &imm8s
)
6989 && !operand_type_equal (&overlap
, &imm16
)
6990 && !operand_type_equal (&overlap
, &imm32
)
6991 && !operand_type_equal (&overlap
, &imm32s
)
6992 && !operand_type_equal (&overlap
, &imm64
))
6994 as_bad (_("no instruction mnemonic suffix given; "
6995 "can't determine immediate size"));
6999 i
.types
[j
] = overlap
;
7009 /* Update the first 2 immediate operands. */
7010 n
= i
.operands
> 2 ? 2 : i
.operands
;
7013 for (j
= 0; j
< n
; j
++)
7014 if (update_imm (j
) == 0)
7017 /* The 3rd operand can't be immediate operand. */
7018 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7025 process_operands (void)
7027 /* Default segment register this instruction will use for memory
7028 accesses. 0 means unknown. This is only for optimizing out
7029 unnecessary segment overrides. */
7030 const seg_entry
*default_seg
= 0;
7032 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7034 unsigned int dupl
= i
.operands
;
7035 unsigned int dest
= dupl
- 1;
7038 /* The destination must be an xmm register. */
7039 gas_assert (i
.reg_operands
7040 && MAX_OPERANDS
> dupl
7041 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7043 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7044 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7046 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7048 /* Keep xmm0 for instructions with VEX prefix and 3
7050 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7051 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7056 /* We remove the first xmm0 and keep the number of
7057 operands unchanged, which in fact duplicates the
7059 for (j
= 1; j
< i
.operands
; j
++)
7061 i
.op
[j
- 1] = i
.op
[j
];
7062 i
.types
[j
- 1] = i
.types
[j
];
7063 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7064 i
.flags
[j
- 1] = i
.flags
[j
];
7068 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7070 gas_assert ((MAX_OPERANDS
- 1) > dupl
7071 && (i
.tm
.opcode_modifier
.vexsources
7074 /* Add the implicit xmm0 for instructions with VEX prefix
7076 for (j
= i
.operands
; j
> 0; j
--)
7078 i
.op
[j
] = i
.op
[j
- 1];
7079 i
.types
[j
] = i
.types
[j
- 1];
7080 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7081 i
.flags
[j
] = i
.flags
[j
- 1];
7084 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
7085 i
.types
[0] = regxmm
;
7086 i
.tm
.operand_types
[0] = regxmm
;
7089 i
.reg_operands
+= 2;
7094 i
.op
[dupl
] = i
.op
[dest
];
7095 i
.types
[dupl
] = i
.types
[dest
];
7096 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7097 i
.flags
[dupl
] = i
.flags
[dest
];
7106 i
.op
[dupl
] = i
.op
[dest
];
7107 i
.types
[dupl
] = i
.types
[dest
];
7108 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7109 i
.flags
[dupl
] = i
.flags
[dest
];
7112 if (i
.tm
.opcode_modifier
.immext
)
7115 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7116 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7120 for (j
= 1; j
< i
.operands
; j
++)
7122 i
.op
[j
- 1] = i
.op
[j
];
7123 i
.types
[j
- 1] = i
.types
[j
];
7125 /* We need to adjust fields in i.tm since they are used by
7126 build_modrm_byte. */
7127 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7129 i
.flags
[j
- 1] = i
.flags
[j
];
7136 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7138 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7140 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7141 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7142 regnum
= register_number (i
.op
[1].regs
);
7143 first_reg_in_group
= regnum
& ~3;
7144 last_reg_in_group
= first_reg_in_group
+ 3;
7145 if (regnum
!= first_reg_in_group
)
7146 as_warn (_("source register `%s%s' implicitly denotes"
7147 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7148 register_prefix
, i
.op
[1].regs
->reg_name
,
7149 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7150 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7153 else if (i
.tm
.opcode_modifier
.regkludge
)
7155 /* The imul $imm, %reg instruction is converted into
7156 imul $imm, %reg, %reg, and the clr %reg instruction
7157 is converted into xor %reg, %reg. */
7159 unsigned int first_reg_op
;
7161 if (operand_type_check (i
.types
[0], reg
))
7165 /* Pretend we saw the extra register operand. */
7166 gas_assert (i
.reg_operands
== 1
7167 && i
.op
[first_reg_op
+ 1].regs
== 0);
7168 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7169 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7174 if (i
.tm
.opcode_modifier
.modrm
)
7176 /* The opcode is completed (modulo i.tm.extension_opcode which
7177 must be put into the modrm byte). Now, we make the modrm and
7178 index base bytes based on all the info we've collected. */
7180 default_seg
= build_modrm_byte ();
7182 else if (i
.types
[0].bitfield
.class == SReg
)
7184 if (flag_code
!= CODE_64BIT
7185 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7186 && i
.op
[0].regs
->reg_num
== 1
7187 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7188 && i
.op
[0].regs
->reg_num
< 4)
7190 as_bad (_("you can't `%s %s%s'"),
7191 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7194 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7196 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7197 i
.tm
.opcode_length
= 2;
7199 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7201 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7205 else if (i
.tm
.opcode_modifier
.isstring
)
7207 /* For the string instructions that allow a segment override
7208 on one of their operands, the default segment is ds. */
7211 else if (i
.short_form
)
7213 /* The register or float register operand is in operand
7215 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7217 /* Register goes in low 3 bits of opcode. */
7218 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7219 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7221 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7223 /* Warn about some common errors, but press on regardless.
7224 The first case can be generated by gcc (<= 2.8.1). */
7225 if (i
.operands
== 2)
7227 /* Reversed arguments on faddp, fsubp, etc. */
7228 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7229 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7230 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7234 /* Extraneous `l' suffix on fp insn. */
7235 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7236 register_prefix
, i
.op
[0].regs
->reg_name
);
7241 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7242 && i
.tm
.base_opcode
== 0x8d /* lea */
7243 && !is_any_vex_encoding(&i
.tm
))
7245 if (!quiet_warnings
)
7246 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7250 i
.prefix
[SEG_PREFIX
] = 0;
7254 /* If a segment was explicitly specified, and the specified segment
7255 is neither the default nor the one already recorded from a prefix,
7256 use an opcode prefix to select it. If we never figured out what
7257 the default segment is, then default_seg will be zero at this
7258 point, and the specified segment prefix will always be used. */
7260 && i
.seg
[0] != default_seg
7261 && i
.seg
[0]->seg_prefix
!= i
.prefix
[SEG_PREFIX
])
7263 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7269 static const seg_entry
*
7270 build_modrm_byte (void)
7272 const seg_entry
*default_seg
= 0;
7273 unsigned int source
, dest
;
7276 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7279 unsigned int nds
, reg_slot
;
7282 dest
= i
.operands
- 1;
7285 /* There are 2 kinds of instructions:
7286 1. 5 operands: 4 register operands or 3 register operands
7287 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7288 VexW0 or VexW1. The destination must be either XMM, YMM or
7290 2. 4 operands: 4 register operands or 3 register operands
7291 plus 1 memory operand, with VexXDS. */
7292 gas_assert ((i
.reg_operands
== 4
7293 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7294 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7295 && i
.tm
.opcode_modifier
.vexw
7296 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7298 /* If VexW1 is set, the first non-immediate operand is the source and
7299 the second non-immediate one is encoded in the immediate operand. */
7300 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7302 source
= i
.imm_operands
;
7303 reg_slot
= i
.imm_operands
+ 1;
7307 source
= i
.imm_operands
+ 1;
7308 reg_slot
= i
.imm_operands
;
7311 if (i
.imm_operands
== 0)
7313 /* When there is no immediate operand, generate an 8bit
7314 immediate operand to encode the first operand. */
7315 exp
= &im_expressions
[i
.imm_operands
++];
7316 i
.op
[i
.operands
].imms
= exp
;
7317 i
.types
[i
.operands
] = imm8
;
7320 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7321 exp
->X_op
= O_constant
;
7322 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7323 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7327 gas_assert (i
.imm_operands
== 1);
7328 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7329 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7331 /* Turn on Imm8 again so that output_imm will generate it. */
7332 i
.types
[0].bitfield
.imm8
= 1;
7334 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7335 i
.op
[0].imms
->X_add_number
7336 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7337 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7340 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7341 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7346 /* i.reg_operands MUST be the number of real register operands;
7347 implicit registers do not count. If there are 3 register
7348 operands, it must be a instruction with VexNDS. For a
7349 instruction with VexNDD, the destination register is encoded
7350 in VEX prefix. If there are 4 register operands, it must be
7351 a instruction with VEX prefix and 3 sources. */
7352 if (i
.mem_operands
== 0
7353 && ((i
.reg_operands
== 2
7354 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7355 || (i
.reg_operands
== 3
7356 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7357 || (i
.reg_operands
== 4 && vex_3_sources
)))
7365 /* When there are 3 operands, one of them may be immediate,
7366 which may be the first or the last operand. Otherwise,
7367 the first operand must be shift count register (cl) or it
7368 is an instruction with VexNDS. */
7369 gas_assert (i
.imm_operands
== 1
7370 || (i
.imm_operands
== 0
7371 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7372 || (i
.types
[0].bitfield
.instance
== RegC
7373 && i
.types
[0].bitfield
.byte
))));
7374 if (operand_type_check (i
.types
[0], imm
)
7375 || (i
.types
[0].bitfield
.instance
== RegC
7376 && i
.types
[0].bitfield
.byte
))
7382 /* When there are 4 operands, the first two must be 8bit
7383 immediate operands. The source operand will be the 3rd
7386 For instructions with VexNDS, if the first operand
7387 an imm8, the source operand is the 2nd one. If the last
7388 operand is imm8, the source operand is the first one. */
7389 gas_assert ((i
.imm_operands
== 2
7390 && i
.types
[0].bitfield
.imm8
7391 && i
.types
[1].bitfield
.imm8
)
7392 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7393 && i
.imm_operands
== 1
7394 && (i
.types
[0].bitfield
.imm8
7395 || i
.types
[i
.operands
- 1].bitfield
.imm8
7397 if (i
.imm_operands
== 2)
7401 if (i
.types
[0].bitfield
.imm8
)
7408 if (is_evex_encoding (&i
.tm
))
7410 /* For EVEX instructions, when there are 5 operands, the
7411 first one must be immediate operand. If the second one
7412 is immediate operand, the source operand is the 3th
7413 one. If the last one is immediate operand, the source
7414 operand is the 2nd one. */
7415 gas_assert (i
.imm_operands
== 2
7416 && i
.tm
.opcode_modifier
.sae
7417 && operand_type_check (i
.types
[0], imm
));
7418 if (operand_type_check (i
.types
[1], imm
))
7420 else if (operand_type_check (i
.types
[4], imm
))
7434 /* RC/SAE operand could be between DEST and SRC. That happens
7435 when one operand is GPR and the other one is XMM/YMM/ZMM
7437 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7440 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7442 /* For instructions with VexNDS, the register-only source
7443 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7444 register. It is encoded in VEX prefix. */
7446 i386_operand_type op
;
7449 /* Check register-only source operand when two source
7450 operands are swapped. */
7451 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7452 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7460 op
= i
.tm
.operand_types
[vvvv
];
7461 if ((dest
+ 1) >= i
.operands
7462 || ((op
.bitfield
.class != Reg
7463 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7464 && op
.bitfield
.class != RegSIMD
7465 && !operand_type_equal (&op
, ®mask
)))
7467 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7473 /* One of the register operands will be encoded in the i.rm.reg
7474 field, the other in the combined i.rm.mode and i.rm.regmem
7475 fields. If no form of this instruction supports a memory
7476 destination operand, then we assume the source operand may
7477 sometimes be a memory operand and so we need to store the
7478 destination in the i.rm.reg field. */
7479 if (!i
.tm
.opcode_modifier
.regmem
7480 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7482 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7483 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7484 if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegMMX
7485 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegMMX
)
7486 i
.has_regmmx
= TRUE
;
7487 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegSIMD
7488 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegSIMD
)
7490 if (i
.types
[dest
].bitfield
.zmmword
7491 || i
.types
[source
].bitfield
.zmmword
)
7492 i
.has_regzmm
= TRUE
;
7493 else if (i
.types
[dest
].bitfield
.ymmword
7494 || i
.types
[source
].bitfield
.ymmword
)
7495 i
.has_regymm
= TRUE
;
7497 i
.has_regxmm
= TRUE
;
7499 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7501 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7503 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7505 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7510 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7511 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7512 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7514 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7516 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7518 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7521 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7523 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7526 add_prefix (LOCK_PREFIX_OPCODE
);
7530 { /* If it's not 2 reg operands... */
7535 unsigned int fake_zero_displacement
= 0;
7538 for (op
= 0; op
< i
.operands
; op
++)
7539 if (i
.flags
[op
] & Operand_Mem
)
7541 gas_assert (op
< i
.operands
);
7543 if (i
.tm
.opcode_modifier
.vecsib
)
7545 if (i
.index_reg
->reg_num
== RegIZ
)
7548 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7551 i
.sib
.base
= NO_BASE_REGISTER
;
7552 i
.sib
.scale
= i
.log2_scale_factor
;
7553 i
.types
[op
].bitfield
.disp8
= 0;
7554 i
.types
[op
].bitfield
.disp16
= 0;
7555 i
.types
[op
].bitfield
.disp64
= 0;
7556 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7558 /* Must be 32 bit */
7559 i
.types
[op
].bitfield
.disp32
= 1;
7560 i
.types
[op
].bitfield
.disp32s
= 0;
7564 i
.types
[op
].bitfield
.disp32
= 0;
7565 i
.types
[op
].bitfield
.disp32s
= 1;
7568 i
.sib
.index
= i
.index_reg
->reg_num
;
7569 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7571 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7577 if (i
.base_reg
== 0)
7580 if (!i
.disp_operands
)
7581 fake_zero_displacement
= 1;
7582 if (i
.index_reg
== 0)
7584 i386_operand_type newdisp
;
7586 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7587 /* Operand is just <disp> */
7588 if (flag_code
== CODE_64BIT
)
7590 /* 64bit mode overwrites the 32bit absolute
7591 addressing by RIP relative addressing and
7592 absolute addressing is encoded by one of the
7593 redundant SIB forms. */
7594 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7595 i
.sib
.base
= NO_BASE_REGISTER
;
7596 i
.sib
.index
= NO_INDEX_REGISTER
;
7597 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7599 else if ((flag_code
== CODE_16BIT
)
7600 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7602 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7607 i
.rm
.regmem
= NO_BASE_REGISTER
;
7610 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7611 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7613 else if (!i
.tm
.opcode_modifier
.vecsib
)
7615 /* !i.base_reg && i.index_reg */
7616 if (i
.index_reg
->reg_num
== RegIZ
)
7617 i
.sib
.index
= NO_INDEX_REGISTER
;
7619 i
.sib
.index
= i
.index_reg
->reg_num
;
7620 i
.sib
.base
= NO_BASE_REGISTER
;
7621 i
.sib
.scale
= i
.log2_scale_factor
;
7622 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7623 i
.types
[op
].bitfield
.disp8
= 0;
7624 i
.types
[op
].bitfield
.disp16
= 0;
7625 i
.types
[op
].bitfield
.disp64
= 0;
7626 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7628 /* Must be 32 bit */
7629 i
.types
[op
].bitfield
.disp32
= 1;
7630 i
.types
[op
].bitfield
.disp32s
= 0;
7634 i
.types
[op
].bitfield
.disp32
= 0;
7635 i
.types
[op
].bitfield
.disp32s
= 1;
7637 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7641 /* RIP addressing for 64bit mode. */
7642 else if (i
.base_reg
->reg_num
== RegIP
)
7644 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7645 i
.rm
.regmem
= NO_BASE_REGISTER
;
7646 i
.types
[op
].bitfield
.disp8
= 0;
7647 i
.types
[op
].bitfield
.disp16
= 0;
7648 i
.types
[op
].bitfield
.disp32
= 0;
7649 i
.types
[op
].bitfield
.disp32s
= 1;
7650 i
.types
[op
].bitfield
.disp64
= 0;
7651 i
.flags
[op
] |= Operand_PCrel
;
7652 if (! i
.disp_operands
)
7653 fake_zero_displacement
= 1;
7655 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7657 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7658 switch (i
.base_reg
->reg_num
)
7661 if (i
.index_reg
== 0)
7663 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7664 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7668 if (i
.index_reg
== 0)
7671 if (operand_type_check (i
.types
[op
], disp
) == 0)
7673 /* fake (%bp) into 0(%bp) */
7674 i
.types
[op
].bitfield
.disp8
= 1;
7675 fake_zero_displacement
= 1;
7678 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7679 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7681 default: /* (%si) -> 4 or (%di) -> 5 */
7682 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7684 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7686 else /* i.base_reg and 32/64 bit mode */
7688 if (flag_code
== CODE_64BIT
7689 && operand_type_check (i
.types
[op
], disp
))
7691 i
.types
[op
].bitfield
.disp16
= 0;
7692 i
.types
[op
].bitfield
.disp64
= 0;
7693 if (i
.prefix
[ADDR_PREFIX
] == 0)
7695 i
.types
[op
].bitfield
.disp32
= 0;
7696 i
.types
[op
].bitfield
.disp32s
= 1;
7700 i
.types
[op
].bitfield
.disp32
= 1;
7701 i
.types
[op
].bitfield
.disp32s
= 0;
7705 if (!i
.tm
.opcode_modifier
.vecsib
)
7706 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7707 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7709 i
.sib
.base
= i
.base_reg
->reg_num
;
7710 /* x86-64 ignores REX prefix bit here to avoid decoder
7712 if (!(i
.base_reg
->reg_flags
& RegRex
)
7713 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7714 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7716 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7718 fake_zero_displacement
= 1;
7719 i
.types
[op
].bitfield
.disp8
= 1;
7721 i
.sib
.scale
= i
.log2_scale_factor
;
7722 if (i
.index_reg
== 0)
7724 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7725 /* <disp>(%esp) becomes two byte modrm with no index
7726 register. We've already stored the code for esp
7727 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7728 Any base register besides %esp will not use the
7729 extra modrm byte. */
7730 i
.sib
.index
= NO_INDEX_REGISTER
;
7732 else if (!i
.tm
.opcode_modifier
.vecsib
)
7734 if (i
.index_reg
->reg_num
== RegIZ
)
7735 i
.sib
.index
= NO_INDEX_REGISTER
;
7737 i
.sib
.index
= i
.index_reg
->reg_num
;
7738 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7739 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7744 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7745 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7749 if (!fake_zero_displacement
7753 fake_zero_displacement
= 1;
7754 if (i
.disp_encoding
== disp_encoding_8bit
)
7755 i
.types
[op
].bitfield
.disp8
= 1;
7757 i
.types
[op
].bitfield
.disp32
= 1;
7759 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7763 if (fake_zero_displacement
)
7765 /* Fakes a zero displacement assuming that i.types[op]
7766 holds the correct displacement size. */
7769 gas_assert (i
.op
[op
].disps
== 0);
7770 exp
= &disp_expressions
[i
.disp_operands
++];
7771 i
.op
[op
].disps
= exp
;
7772 exp
->X_op
= O_constant
;
7773 exp
->X_add_number
= 0;
7774 exp
->X_add_symbol
= (symbolS
*) 0;
7775 exp
->X_op_symbol
= (symbolS
*) 0;
7783 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7785 if (operand_type_check (i
.types
[0], imm
))
7786 i
.vex
.register_specifier
= NULL
;
7789 /* VEX.vvvv encodes one of the sources when the first
7790 operand is not an immediate. */
7791 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7792 i
.vex
.register_specifier
= i
.op
[0].regs
;
7794 i
.vex
.register_specifier
= i
.op
[1].regs
;
7797 /* Destination is a XMM register encoded in the ModRM.reg
7799 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7800 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7803 /* ModRM.rm and VEX.B encodes the other source. */
7804 if (!i
.mem_operands
)
7808 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7809 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7811 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7813 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7817 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7819 i
.vex
.register_specifier
= i
.op
[2].regs
;
7820 if (!i
.mem_operands
)
7823 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7824 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7828 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7829 (if any) based on i.tm.extension_opcode. Again, we must be
7830 careful to make sure that segment/control/debug/test/MMX
7831 registers are coded into the i.rm.reg field. */
7832 else if (i
.reg_operands
)
7835 unsigned int vex_reg
= ~0;
7837 for (op
= 0; op
< i
.operands
; op
++)
7839 if (i
.types
[op
].bitfield
.class == Reg
7840 || i
.types
[op
].bitfield
.class == RegBND
7841 || i
.types
[op
].bitfield
.class == RegMask
7842 || i
.types
[op
].bitfield
.class == SReg
7843 || i
.types
[op
].bitfield
.class == RegCR
7844 || i
.types
[op
].bitfield
.class == RegDR
7845 || i
.types
[op
].bitfield
.class == RegTR
)
7847 if (i
.types
[op
].bitfield
.class == RegSIMD
)
7849 if (i
.types
[op
].bitfield
.zmmword
)
7850 i
.has_regzmm
= TRUE
;
7851 else if (i
.types
[op
].bitfield
.ymmword
)
7852 i
.has_regymm
= TRUE
;
7854 i
.has_regxmm
= TRUE
;
7857 if (i
.types
[op
].bitfield
.class == RegMMX
)
7859 i
.has_regmmx
= TRUE
;
7866 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7868 /* For instructions with VexNDS, the register-only
7869 source operand is encoded in VEX prefix. */
7870 gas_assert (mem
!= (unsigned int) ~0);
7875 gas_assert (op
< i
.operands
);
7879 /* Check register-only source operand when two source
7880 operands are swapped. */
7881 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7882 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7886 gas_assert (mem
== (vex_reg
+ 1)
7887 && op
< i
.operands
);
7892 gas_assert (vex_reg
< i
.operands
);
7896 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7898 /* For instructions with VexNDD, the register destination
7899 is encoded in VEX prefix. */
7900 if (i
.mem_operands
== 0)
7902 /* There is no memory operand. */
7903 gas_assert ((op
+ 2) == i
.operands
);
7908 /* There are only 2 non-immediate operands. */
7909 gas_assert (op
< i
.imm_operands
+ 2
7910 && i
.operands
== i
.imm_operands
+ 2);
7911 vex_reg
= i
.imm_operands
+ 1;
7915 gas_assert (op
< i
.operands
);
7917 if (vex_reg
!= (unsigned int) ~0)
7919 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7921 if ((type
->bitfield
.class != Reg
7922 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7923 && type
->bitfield
.class != RegSIMD
7924 && !operand_type_equal (type
, ®mask
))
7927 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7930 /* Don't set OP operand twice. */
7933 /* If there is an extension opcode to put here, the
7934 register number must be put into the regmem field. */
7935 if (i
.tm
.extension_opcode
!= None
)
7937 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7938 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7940 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7945 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7946 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7948 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7953 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7954 must set it to 3 to indicate this is a register operand
7955 in the regmem field. */
7956 if (!i
.mem_operands
)
7960 /* Fill in i.rm.reg field with extension opcode (if any). */
7961 if (i
.tm
.extension_opcode
!= None
)
7962 i
.rm
.reg
= i
.tm
.extension_opcode
;
7968 flip_code16 (unsigned int code16
)
7970 gas_assert (i
.tm
.operands
== 1);
7972 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
7973 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
7974 || i
.tm
.operand_types
[0].bitfield
.disp32s
7975 : i
.tm
.operand_types
[0].bitfield
.disp16
)
7980 output_branch (void)
7986 relax_substateT subtype
;
7990 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7991 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7994 if (i
.prefix
[DATA_PREFIX
] != 0)
7998 code16
^= flip_code16(code16
);
8000 /* Pentium4 branch hints. */
8001 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8002 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8007 if (i
.prefix
[REX_PREFIX
] != 0)
8013 /* BND prefixed jump. */
8014 if (i
.prefix
[BND_PREFIX
] != 0)
8020 if (i
.prefixes
!= 0)
8021 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8023 /* It's always a symbol; End frag & setup for relax.
8024 Make sure there is enough room in this frag for the largest
8025 instruction we may generate in md_convert_frag. This is 2
8026 bytes for the opcode and room for the prefix and largest
8028 frag_grow (prefix
+ 2 + 4);
8029 /* Prefix and 1 opcode byte go in fr_fix. */
8030 p
= frag_more (prefix
+ 1);
8031 if (i
.prefix
[DATA_PREFIX
] != 0)
8032 *p
++ = DATA_PREFIX_OPCODE
;
8033 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8034 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8035 *p
++ = i
.prefix
[SEG_PREFIX
];
8036 if (i
.prefix
[BND_PREFIX
] != 0)
8037 *p
++ = BND_PREFIX_OPCODE
;
8038 if (i
.prefix
[REX_PREFIX
] != 0)
8039 *p
++ = i
.prefix
[REX_PREFIX
];
8040 *p
= i
.tm
.base_opcode
;
8042 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8043 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8044 else if (cpu_arch_flags
.bitfield
.cpui386
)
8045 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8047 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8050 sym
= i
.op
[0].disps
->X_add_symbol
;
8051 off
= i
.op
[0].disps
->X_add_number
;
8053 if (i
.op
[0].disps
->X_op
!= O_constant
8054 && i
.op
[0].disps
->X_op
!= O_symbol
)
8056 /* Handle complex expressions. */
8057 sym
= make_expr_symbol (i
.op
[0].disps
);
8061 /* 1 possible extra opcode + 4 byte displacement go in var part.
8062 Pass reloc in fr_var. */
8063 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8066 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8067 /* Return TRUE iff PLT32 relocation should be used for branching to
8071 need_plt32_p (symbolS
*s
)
8073 /* PLT32 relocation is ELF only. */
8078 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8079 krtld support it. */
8083 /* Since there is no need to prepare for PLT branch on x86-64, we
8084 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8085 be used as a marker for 32-bit PC-relative branches. */
8089 /* Weak or undefined symbol need PLT32 relocation. */
8090 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8093 /* Non-global symbol doesn't need PLT32 relocation. */
8094 if (! S_IS_EXTERNAL (s
))
8097 /* Other global symbols need PLT32 relocation. NB: Symbol with
8098 non-default visibilities are treated as normal global symbol
8099 so that PLT32 relocation can be used as a marker for 32-bit
8100 PC-relative branches. It is useful for linker relaxation. */
8111 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8113 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8115 /* This is a loop or jecxz type instruction. */
8117 if (i
.prefix
[ADDR_PREFIX
] != 0)
8119 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
8122 /* Pentium4 branch hints. */
8123 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8124 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8126 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
8135 if (flag_code
== CODE_16BIT
)
8138 if (i
.prefix
[DATA_PREFIX
] != 0)
8140 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
8142 code16
^= flip_code16(code16
);
8150 /* BND prefixed jump. */
8151 if (i
.prefix
[BND_PREFIX
] != 0)
8153 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
8157 if (i
.prefix
[REX_PREFIX
] != 0)
8159 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
8163 if (i
.prefixes
!= 0)
8164 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8166 p
= frag_more (i
.tm
.opcode_length
+ size
);
8167 switch (i
.tm
.opcode_length
)
8170 *p
++ = i
.tm
.base_opcode
>> 8;
8173 *p
++ = i
.tm
.base_opcode
;
8179 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8181 && jump_reloc
== NO_RELOC
8182 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8183 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8186 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8188 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8189 i
.op
[0].disps
, 1, jump_reloc
);
8191 /* All jumps handled here are signed, but don't use a signed limit
8192 check for 32 and 16 bit jumps as we want to allow wrap around at
8193 4G and 64k respectively. */
8195 fixP
->fx_signed
= 1;
8199 output_interseg_jump (void)
8207 if (flag_code
== CODE_16BIT
)
8211 if (i
.prefix
[DATA_PREFIX
] != 0)
8218 gas_assert (!i
.prefix
[REX_PREFIX
]);
8224 if (i
.prefixes
!= 0)
8225 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8227 /* 1 opcode; 2 segment; offset */
8228 p
= frag_more (prefix
+ 1 + 2 + size
);
8230 if (i
.prefix
[DATA_PREFIX
] != 0)
8231 *p
++ = DATA_PREFIX_OPCODE
;
8233 if (i
.prefix
[REX_PREFIX
] != 0)
8234 *p
++ = i
.prefix
[REX_PREFIX
];
8236 *p
++ = i
.tm
.base_opcode
;
8237 if (i
.op
[1].imms
->X_op
== O_constant
)
8239 offsetT n
= i
.op
[1].imms
->X_add_number
;
8242 && !fits_in_unsigned_word (n
)
8243 && !fits_in_signed_word (n
))
8245 as_bad (_("16-bit jump out of range"));
8248 md_number_to_chars (p
, n
, size
);
8251 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8252 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8253 if (i
.op
[0].imms
->X_op
!= O_constant
)
8254 as_bad (_("can't handle non absolute segment in `%s'"),
8256 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8259 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8264 asection
*seg
= now_seg
;
8265 subsegT subseg
= now_subseg
;
8267 unsigned int alignment
, align_size_1
;
8268 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8269 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8270 unsigned int padding
;
8272 if (!IS_ELF
|| !x86_used_note
)
8275 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8277 /* The .note.gnu.property section layout:
8279 Field Length Contents
8282 n_descsz 4 The note descriptor size
8283 n_type 4 NT_GNU_PROPERTY_TYPE_0
8285 n_desc n_descsz The program property array
8289 /* Create the .note.gnu.property section. */
8290 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8291 bfd_set_section_flags (sec
,
8298 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8309 bfd_set_section_alignment (sec
, alignment
);
8310 elf_section_type (sec
) = SHT_NOTE
;
8312 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8314 isa_1_descsz_raw
= 4 + 4 + 4;
8315 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8316 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8318 feature_2_descsz_raw
= isa_1_descsz
;
8319 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8321 feature_2_descsz_raw
+= 4 + 4 + 4;
8322 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8323 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8326 descsz
= feature_2_descsz
;
8327 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8328 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8330 /* Write n_namsz. */
8331 md_number_to_chars (p
, (valueT
) 4, 4);
8333 /* Write n_descsz. */
8334 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8337 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8340 memcpy (p
+ 4 * 3, "GNU", 4);
8342 /* Write 4-byte type. */
8343 md_number_to_chars (p
+ 4 * 4,
8344 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8346 /* Write 4-byte data size. */
8347 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8349 /* Write 4-byte data. */
8350 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8352 /* Zero out paddings. */
8353 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8355 memset (p
+ 4 * 7, 0, padding
);
8357 /* Write 4-byte type. */
8358 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8359 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8361 /* Write 4-byte data size. */
8362 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8364 /* Write 4-byte data. */
8365 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8366 (valueT
) x86_feature_2_used
, 4);
8368 /* Zero out paddings. */
8369 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8371 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8373 /* We probably can't restore the current segment, for there likely
8376 subseg_set (seg
, subseg
);
8381 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8382 const char *frag_now_ptr
)
8384 unsigned int len
= 0;
8386 if (start_frag
!= frag_now
)
8388 const fragS
*fr
= start_frag
;
8393 } while (fr
&& fr
!= frag_now
);
8396 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8399 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8400 be macro-fused with conditional jumps.
8401 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
8402 or is one of the following format:
8415 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
8417 /* No RIP address. */
8418 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8421 /* No VEX/EVEX encoding. */
8422 if (is_any_vex_encoding (&i
.tm
))
8425 /* add, sub without add/sub m, imm. */
8426 if (i
.tm
.base_opcode
<= 5
8427 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8428 || ((i
.tm
.base_opcode
| 3) == 0x83
8429 && (i
.tm
.extension_opcode
== 0x5
8430 || i
.tm
.extension_opcode
== 0x0)))
8432 *mf_cmp_p
= mf_cmp_alu_cmp
;
8433 return !(i
.mem_operands
&& i
.imm_operands
);
8436 /* and without and m, imm. */
8437 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8438 || ((i
.tm
.base_opcode
| 3) == 0x83
8439 && i
.tm
.extension_opcode
== 0x4))
8441 *mf_cmp_p
= mf_cmp_test_and
;
8442 return !(i
.mem_operands
&& i
.imm_operands
);
8445 /* test without test m imm. */
8446 if ((i
.tm
.base_opcode
| 1) == 0x85
8447 || (i
.tm
.base_opcode
| 1) == 0xa9
8448 || ((i
.tm
.base_opcode
| 1) == 0xf7
8449 && i
.tm
.extension_opcode
== 0))
8451 *mf_cmp_p
= mf_cmp_test_and
;
8452 return !(i
.mem_operands
&& i
.imm_operands
);
8455 /* cmp without cmp m, imm. */
8456 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8457 || ((i
.tm
.base_opcode
| 3) == 0x83
8458 && (i
.tm
.extension_opcode
== 0x7)))
8460 *mf_cmp_p
= mf_cmp_alu_cmp
;
8461 return !(i
.mem_operands
&& i
.imm_operands
);
8464 /* inc, dec without inc/dec m. */
8465 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8466 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8467 || ((i
.tm
.base_opcode
| 1) == 0xff
8468 && i
.tm
.extension_opcode
<= 0x1))
8470 *mf_cmp_p
= mf_cmp_incdec
;
8471 return !i
.mem_operands
;
8477 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
8480 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
8482 /* NB: Don't work with COND_JUMP86 without i386. */
8483 if (!align_branch_power
8484 || now_seg
== absolute_section
8485 || !cpu_arch_flags
.bitfield
.cpui386
8486 || !(align_branch
& align_branch_fused_bit
))
8489 if (maybe_fused_with_jcc_p (mf_cmp_p
))
8491 if (last_insn
.kind
== last_insn_other
8492 || last_insn
.seg
!= now_seg
)
8495 as_warn_where (last_insn
.file
, last_insn
.line
,
8496 _("`%s` skips -malign-branch-boundary on `%s`"),
8497 last_insn
.name
, i
.tm
.name
);
8503 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
8506 add_branch_prefix_frag_p (void)
8508 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
8509 to PadLock instructions since they include prefixes in opcode. */
8510 if (!align_branch_power
8511 || !align_branch_prefix_size
8512 || now_seg
== absolute_section
8513 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
8514 || !cpu_arch_flags
.bitfield
.cpui386
)
8517 /* Don't add prefix if it is a prefix or there is no operand in case
8518 that segment prefix is special. */
8519 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
8522 if (last_insn
.kind
== last_insn_other
8523 || last_insn
.seg
!= now_seg
)
8527 as_warn_where (last_insn
.file
, last_insn
.line
,
8528 _("`%s` skips -malign-branch-boundary on `%s`"),
8529 last_insn
.name
, i
.tm
.name
);
8534 /* Return 1 if a BRANCH_PADDING frag should be generated. */
8537 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
8538 enum mf_jcc_kind
*mf_jcc_p
)
8542 /* NB: Don't work with COND_JUMP86 without i386. */
8543 if (!align_branch_power
8544 || now_seg
== absolute_section
8545 || !cpu_arch_flags
.bitfield
.cpui386
)
8550 /* Check for jcc and direct jmp. */
8551 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8553 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
8555 *branch_p
= align_branch_jmp
;
8556 add_padding
= align_branch
& align_branch_jmp_bit
;
8560 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
8561 igore the lowest bit. */
8562 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
8563 *branch_p
= align_branch_jcc
;
8564 if ((align_branch
& align_branch_jcc_bit
))
8568 else if (is_any_vex_encoding (&i
.tm
))
8570 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
8573 *branch_p
= align_branch_ret
;
8574 if ((align_branch
& align_branch_ret_bit
))
8579 /* Check for indirect jmp, direct and indirect calls. */
8580 if (i
.tm
.base_opcode
== 0xe8)
8583 *branch_p
= align_branch_call
;
8584 if ((align_branch
& align_branch_call_bit
))
8587 else if (i
.tm
.base_opcode
== 0xff
8588 && (i
.tm
.extension_opcode
== 2
8589 || i
.tm
.extension_opcode
== 4))
8591 /* Indirect call and jmp. */
8592 *branch_p
= align_branch_indirect
;
8593 if ((align_branch
& align_branch_indirect_bit
))
8600 && (i
.op
[0].disps
->X_op
== O_symbol
8601 || (i
.op
[0].disps
->X_op
== O_subtract
8602 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
8604 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
8605 /* No padding to call to global or undefined tls_get_addr. */
8606 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
8607 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
8613 && last_insn
.kind
!= last_insn_other
8614 && last_insn
.seg
== now_seg
)
8617 as_warn_where (last_insn
.file
, last_insn
.line
,
8618 _("`%s` skips -malign-branch-boundary on `%s`"),
8619 last_insn
.name
, i
.tm
.name
);
8629 fragS
*insn_start_frag
;
8630 offsetT insn_start_off
;
8631 fragS
*fragP
= NULL
;
8632 enum align_branch_kind branch
= align_branch_none
;
8633 /* The initializer is arbitrary just to avoid uninitialized error.
8634 it's actually either assigned in add_branch_padding_frag_p
8635 or never be used. */
8636 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
8638 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8639 if (IS_ELF
&& x86_used_note
)
8641 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8642 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8643 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8644 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8645 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8646 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8647 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8648 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8649 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8650 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8651 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8652 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8653 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8654 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8655 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8656 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8657 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8658 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8659 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8660 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8661 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8662 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8663 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8664 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8665 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8666 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8667 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8668 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8669 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8670 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8671 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8672 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8673 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8674 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8675 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8676 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8677 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8678 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8679 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8680 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8681 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8682 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8683 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8684 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8685 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8686 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8687 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8688 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8689 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8690 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8692 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8693 || i
.tm
.cpu_flags
.bitfield
.cpu287
8694 || i
.tm
.cpu_flags
.bitfield
.cpu387
8695 || i
.tm
.cpu_flags
.bitfield
.cpu687
8696 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8697 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8699 || i
.tm
.base_opcode
== 0xf77 /* emms */
8700 || i
.tm
.base_opcode
== 0xf0e /* femms */
8701 || i
.tm
.base_opcode
== 0xf2a /* cvtpi2ps */
8702 || i
.tm
.base_opcode
== 0x660f2a /* cvtpi2pd */)
8703 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8705 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8707 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8709 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8710 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8711 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8712 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8713 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8714 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8715 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8716 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8717 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8721 /* Tie dwarf2 debug info to the address at the start of the insn.
8722 We can't do this after the insn has been output as the current
8723 frag may have been closed off. eg. by frag_var. */
8724 dwarf2_emit_insn (0);
8726 insn_start_frag
= frag_now
;
8727 insn_start_off
= frag_now_fix ();
8729 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
8732 /* Branch can be 8 bytes. Leave some room for prefixes. */
8733 unsigned int max_branch_padding_size
= 14;
8735 /* Align section to boundary. */
8736 record_alignment (now_seg
, align_branch_power
);
8738 /* Make room for padding. */
8739 frag_grow (max_branch_padding_size
);
8741 /* Start of the padding. */
8746 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
8747 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
8750 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
8751 fragP
->tc_frag_data
.branch_type
= branch
;
8752 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
8756 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8758 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
8759 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
8761 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
8762 output_interseg_jump ();
8765 /* Output normal instructions here. */
8769 unsigned int prefix
;
8770 enum mf_cmp_kind mf_cmp
;
8773 && (i
.tm
.base_opcode
== 0xfaee8
8774 || i
.tm
.base_opcode
== 0xfaef0
8775 || i
.tm
.base_opcode
== 0xfaef8))
8777 /* Encode lfence, mfence, and sfence as
8778 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8779 offsetT val
= 0x240483f0ULL
;
8781 md_number_to_chars (p
, val
, 5);
8785 /* Some processors fail on LOCK prefix. This options makes
8786 assembler ignore LOCK prefix and serves as a workaround. */
8787 if (omit_lock_prefix
)
8789 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8791 i
.prefix
[LOCK_PREFIX
] = 0;
8795 /* Skip if this is a branch. */
8797 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
8799 /* Make room for padding. */
8800 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
8805 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
8806 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
8809 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
8810 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
8811 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
8813 else if (add_branch_prefix_frag_p ())
8815 unsigned int max_prefix_size
= align_branch_prefix_size
;
8817 /* Make room for padding. */
8818 frag_grow (max_prefix_size
);
8823 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
8824 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
8827 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
8830 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8831 don't need the explicit prefix. */
8832 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8834 switch (i
.tm
.opcode_length
)
8837 if (i
.tm
.base_opcode
& 0xff000000)
8839 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8840 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8841 || prefix
!= REPE_PREFIX_OPCODE
8842 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8843 add_prefix (prefix
);
8847 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8849 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8850 add_prefix (prefix
);
8856 /* Check for pseudo prefixes. */
8857 as_bad_where (insn_start_frag
->fr_file
,
8858 insn_start_frag
->fr_line
,
8859 _("pseudo prefix without instruction"));
8865 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8866 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8867 R_X86_64_GOTTPOFF relocation so that linker can safely
8868 perform IE->LE optimization. A dummy REX_OPCODE prefix
8869 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
8870 relocation for GDesc -> IE/LE optimization. */
8871 if (x86_elf_abi
== X86_64_X32_ABI
8873 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8874 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
8875 && i
.prefix
[REX_PREFIX
] == 0)
8876 add_prefix (REX_OPCODE
);
8879 /* The prefix bytes. */
8880 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8882 FRAG_APPEND_1_CHAR (*q
);
8886 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8891 /* REX byte is encoded in VEX prefix. */
8895 FRAG_APPEND_1_CHAR (*q
);
8898 /* There should be no other prefixes for instructions
8903 /* For EVEX instructions i.vrex should become 0 after
8904 build_evex_prefix. For VEX instructions upper 16 registers
8905 aren't available, so VREX should be 0. */
8908 /* Now the VEX prefix. */
8909 p
= frag_more (i
.vex
.length
);
8910 for (j
= 0; j
< i
.vex
.length
; j
++)
8911 p
[j
] = i
.vex
.bytes
[j
];
8914 /* Now the opcode; be careful about word order here! */
8915 if (i
.tm
.opcode_length
== 1)
8917 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8921 switch (i
.tm
.opcode_length
)
8925 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8926 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8930 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8940 /* Put out high byte first: can't use md_number_to_chars! */
8941 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8942 *p
= i
.tm
.base_opcode
& 0xff;
8945 /* Now the modrm byte and sib byte (if present). */
8946 if (i
.tm
.opcode_modifier
.modrm
)
8948 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8951 /* If i.rm.regmem == ESP (4)
8952 && i.rm.mode != (Register mode)
8954 ==> need second modrm byte. */
8955 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8957 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8958 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8960 | i
.sib
.scale
<< 6));
8963 if (i
.disp_operands
)
8964 output_disp (insn_start_frag
, insn_start_off
);
8967 output_imm (insn_start_frag
, insn_start_off
);
8970 * frag_now_fix () returning plain abs_section_offset when we're in the
8971 * absolute section, and abs_section_offset not getting updated as data
8972 * gets added to the frag breaks the logic below.
8974 if (now_seg
!= absolute_section
)
8976 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
8978 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
8982 /* NB: Don't add prefix with GOTPC relocation since
8983 output_disp() above depends on the fixed encoding
8984 length. Can't add prefix with TLS relocation since
8985 it breaks TLS linker optimization. */
8986 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
8987 /* Prefix count on the current instruction. */
8988 unsigned int count
= i
.vex
.length
;
8990 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
8991 /* REX byte is encoded in VEX/EVEX prefix. */
8992 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
8995 /* Count prefixes for extended opcode maps. */
8997 switch (i
.tm
.opcode_length
)
9000 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
9003 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
9015 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
9024 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9027 /* Set the maximum prefix size in BRANCH_PREFIX
9029 if (fragP
->tc_frag_data
.max_bytes
> max
)
9030 fragP
->tc_frag_data
.max_bytes
= max
;
9031 if (fragP
->tc_frag_data
.max_bytes
> count
)
9032 fragP
->tc_frag_data
.max_bytes
-= count
;
9034 fragP
->tc_frag_data
.max_bytes
= 0;
9038 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9040 unsigned int max_prefix_size
;
9041 if (align_branch_prefix_size
> max
)
9042 max_prefix_size
= max
;
9044 max_prefix_size
= align_branch_prefix_size
;
9045 if (max_prefix_size
> count
)
9046 fragP
->tc_frag_data
.max_prefix_length
9047 = max_prefix_size
- count
;
9050 /* Use existing segment prefix if possible. Use CS
9051 segment prefix in 64-bit mode. In 32-bit mode, use SS
9052 segment prefix with ESP/EBP base register and use DS
9053 segment prefix without ESP/EBP base register. */
9054 if (i
.prefix
[SEG_PREFIX
])
9055 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9056 else if (flag_code
== CODE_64BIT
)
9057 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9059 && (i
.base_reg
->reg_num
== 4
9060 || i
.base_reg
->reg_num
== 5))
9061 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9063 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9068 /* NB: Don't work with COND_JUMP86 without i386. */
9069 if (align_branch_power
9070 && now_seg
!= absolute_section
9071 && cpu_arch_flags
.bitfield
.cpui386
)
9073 /* Terminate each frag so that we can add prefix and check for
9075 frag_wane (frag_now
);
9082 pi ("" /*line*/, &i
);
9084 #endif /* DEBUG386 */
9087 /* Return the size of the displacement operand N. */
9090 disp_size (unsigned int n
)
9094 if (i
.types
[n
].bitfield
.disp64
)
9096 else if (i
.types
[n
].bitfield
.disp8
)
9098 else if (i
.types
[n
].bitfield
.disp16
)
9103 /* Return the size of the immediate operand N. */
9106 imm_size (unsigned int n
)
9109 if (i
.types
[n
].bitfield
.imm64
)
9111 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9113 else if (i
.types
[n
].bitfield
.imm16
)
9119 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9124 for (n
= 0; n
< i
.operands
; n
++)
9126 if (operand_type_check (i
.types
[n
], disp
))
9128 if (i
.op
[n
].disps
->X_op
== O_constant
)
9130 int size
= disp_size (n
);
9131 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9133 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9135 p
= frag_more (size
);
9136 md_number_to_chars (p
, val
, size
);
9140 enum bfd_reloc_code_real reloc_type
;
9141 int size
= disp_size (n
);
9142 int sign
= i
.types
[n
].bitfield
.disp32s
;
9143 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9146 /* We can't have 8 bit displacement here. */
9147 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9149 /* The PC relative address is computed relative
9150 to the instruction boundary, so in case immediate
9151 fields follows, we need to adjust the value. */
9152 if (pcrel
&& i
.imm_operands
)
9157 for (n1
= 0; n1
< i
.operands
; n1
++)
9158 if (operand_type_check (i
.types
[n1
], imm
))
9160 /* Only one immediate is allowed for PC
9161 relative address. */
9162 gas_assert (sz
== 0);
9164 i
.op
[n
].disps
->X_add_number
-= sz
;
9166 /* We should find the immediate. */
9167 gas_assert (sz
!= 0);
9170 p
= frag_more (size
);
9171 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9173 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9174 && (((reloc_type
== BFD_RELOC_32
9175 || reloc_type
== BFD_RELOC_X86_64_32S
9176 || (reloc_type
== BFD_RELOC_64
9178 && (i
.op
[n
].disps
->X_op
== O_symbol
9179 || (i
.op
[n
].disps
->X_op
== O_add
9180 && ((symbol_get_value_expression
9181 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9183 || reloc_type
== BFD_RELOC_32_PCREL
))
9187 reloc_type
= BFD_RELOC_386_GOTPC
;
9188 i
.has_gotpc_tls_reloc
= TRUE
;
9189 i
.op
[n
].imms
->X_add_number
+=
9190 encoding_length (insn_start_frag
, insn_start_off
, p
);
9192 else if (reloc_type
== BFD_RELOC_64
)
9193 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9195 /* Don't do the adjustment for x86-64, as there
9196 the pcrel addressing is relative to the _next_
9197 insn, and that is taken care of in other code. */
9198 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9200 else if (align_branch_power
)
9204 case BFD_RELOC_386_TLS_GD
:
9205 case BFD_RELOC_386_TLS_LDM
:
9206 case BFD_RELOC_386_TLS_IE
:
9207 case BFD_RELOC_386_TLS_IE_32
:
9208 case BFD_RELOC_386_TLS_GOTIE
:
9209 case BFD_RELOC_386_TLS_GOTDESC
:
9210 case BFD_RELOC_386_TLS_DESC_CALL
:
9211 case BFD_RELOC_X86_64_TLSGD
:
9212 case BFD_RELOC_X86_64_TLSLD
:
9213 case BFD_RELOC_X86_64_GOTTPOFF
:
9214 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9215 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9216 i
.has_gotpc_tls_reloc
= TRUE
;
9221 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9222 size
, i
.op
[n
].disps
, pcrel
,
9224 /* Check for "call/jmp *mem", "mov mem, %reg",
9225 "test %reg, mem" and "binop mem, %reg" where binop
9226 is one of adc, add, and, cmp, or, sbb, sub, xor
9227 instructions without data prefix. Always generate
9228 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9229 if (i
.prefix
[DATA_PREFIX
] == 0
9230 && (generate_relax_relocations
9233 && i
.rm
.regmem
== 5))
9235 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9236 && !is_any_vex_encoding(&i
.tm
)
9237 && ((i
.operands
== 1
9238 && i
.tm
.base_opcode
== 0xff
9239 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9241 && (i
.tm
.base_opcode
== 0x8b
9242 || i
.tm
.base_opcode
== 0x85
9243 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9247 fixP
->fx_tcbit
= i
.rex
!= 0;
9249 && (i
.base_reg
->reg_num
== RegIP
))
9250 fixP
->fx_tcbit2
= 1;
9253 fixP
->fx_tcbit2
= 1;
9261 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9266 for (n
= 0; n
< i
.operands
; n
++)
9268 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9269 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9272 if (operand_type_check (i
.types
[n
], imm
))
9274 if (i
.op
[n
].imms
->X_op
== O_constant
)
9276 int size
= imm_size (n
);
9279 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9281 p
= frag_more (size
);
9282 md_number_to_chars (p
, val
, size
);
9286 /* Not absolute_section.
9287 Need a 32-bit fixup (don't support 8bit
9288 non-absolute imms). Try to support other
9290 enum bfd_reloc_code_real reloc_type
;
9291 int size
= imm_size (n
);
9294 if (i
.types
[n
].bitfield
.imm32s
9295 && (i
.suffix
== QWORD_MNEM_SUFFIX
9296 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9301 p
= frag_more (size
);
9302 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9304 /* This is tough to explain. We end up with this one if we
9305 * have operands that look like
9306 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9307 * obtain the absolute address of the GOT, and it is strongly
9308 * preferable from a performance point of view to avoid using
9309 * a runtime relocation for this. The actual sequence of
9310 * instructions often look something like:
9315 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9317 * The call and pop essentially return the absolute address
9318 * of the label .L66 and store it in %ebx. The linker itself
9319 * will ultimately change the first operand of the addl so
9320 * that %ebx points to the GOT, but to keep things simple, the
9321 * .o file must have this operand set so that it generates not
9322 * the absolute address of .L66, but the absolute address of
9323 * itself. This allows the linker itself simply treat a GOTPC
9324 * relocation as asking for a pcrel offset to the GOT to be
9325 * added in, and the addend of the relocation is stored in the
9326 * operand field for the instruction itself.
9328 * Our job here is to fix the operand so that it would add
9329 * the correct offset so that %ebx would point to itself. The
9330 * thing that is tricky is that .-.L66 will point to the
9331 * beginning of the instruction, so we need to further modify
9332 * the operand so that it will point to itself. There are
9333 * other cases where you have something like:
9335 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9337 * and here no correction would be required. Internally in
9338 * the assembler we treat operands of this form as not being
9339 * pcrel since the '.' is explicitly mentioned, and I wonder
9340 * whether it would simplify matters to do it this way. Who
9341 * knows. In earlier versions of the PIC patches, the
9342 * pcrel_adjust field was used to store the correction, but
9343 * since the expression is not pcrel, I felt it would be
9344 * confusing to do it this way. */
9346 if ((reloc_type
== BFD_RELOC_32
9347 || reloc_type
== BFD_RELOC_X86_64_32S
9348 || reloc_type
== BFD_RELOC_64
)
9350 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9351 && (i
.op
[n
].imms
->X_op
== O_symbol
9352 || (i
.op
[n
].imms
->X_op
== O_add
9353 && ((symbol_get_value_expression
9354 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9358 reloc_type
= BFD_RELOC_386_GOTPC
;
9360 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9362 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9363 i
.has_gotpc_tls_reloc
= TRUE
;
9364 i
.op
[n
].imms
->X_add_number
+=
9365 encoding_length (insn_start_frag
, insn_start_off
, p
);
9367 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9368 i
.op
[n
].imms
, 0, reloc_type
);
9374 /* x86_cons_fix_new is called via the expression parsing code when a
9375 reloc is needed. We use this hook to get the correct .got reloc. */
9376 static int cons_sign
= -1;
9379 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9380 expressionS
*exp
, bfd_reloc_code_real_type r
)
9382 r
= reloc (len
, 0, cons_sign
, r
);
9385 if (exp
->X_op
== O_secrel
)
9387 exp
->X_op
= O_symbol
;
9388 r
= BFD_RELOC_32_SECREL
;
9392 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9395 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9396 purpose of the `.dc.a' internal pseudo-op. */
9399 x86_address_bytes (void)
9401 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9403 return stdoutput
->arch_info
->bits_per_address
/ 8;
9406 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9408 # define lex_got(reloc, adjust, types) NULL
9410 /* Parse operands of the form
9411 <symbol>@GOTOFF+<nnn>
9412 and similar .plt or .got references.
9414 If we find one, set up the correct relocation in RELOC and copy the
9415 input string, minus the `@GOTOFF' into a malloc'd buffer for
9416 parsing by the calling routine. Return this buffer, and if ADJUST
9417 is non-null set it to the length of the string we removed from the
9418 input line. Otherwise return NULL. */
9420 lex_got (enum bfd_reloc_code_real
*rel
,
9422 i386_operand_type
*types
)
9424 /* Some of the relocations depend on the size of what field is to
9425 be relocated. But in our callers i386_immediate and i386_displacement
9426 we don't yet know the operand size (this will be set by insn
9427 matching). Hence we record the word32 relocation here,
9428 and adjust the reloc according to the real size in reloc(). */
9429 static const struct {
9432 const enum bfd_reloc_code_real rel
[2];
9433 const i386_operand_type types64
;
9435 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9436 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
9438 OPERAND_TYPE_IMM32_64
},
9440 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
9441 BFD_RELOC_X86_64_PLTOFF64
},
9442 OPERAND_TYPE_IMM64
},
9443 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
9444 BFD_RELOC_X86_64_PLT32
},
9445 OPERAND_TYPE_IMM32_32S_DISP32
},
9446 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
9447 BFD_RELOC_X86_64_GOTPLT64
},
9448 OPERAND_TYPE_IMM64_DISP64
},
9449 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
9450 BFD_RELOC_X86_64_GOTOFF64
},
9451 OPERAND_TYPE_IMM64_DISP64
},
9452 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
9453 BFD_RELOC_X86_64_GOTPCREL
},
9454 OPERAND_TYPE_IMM32_32S_DISP32
},
9455 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
9456 BFD_RELOC_X86_64_TLSGD
},
9457 OPERAND_TYPE_IMM32_32S_DISP32
},
9458 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
9459 _dummy_first_bfd_reloc_code_real
},
9460 OPERAND_TYPE_NONE
},
9461 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
9462 BFD_RELOC_X86_64_TLSLD
},
9463 OPERAND_TYPE_IMM32_32S_DISP32
},
9464 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
9465 BFD_RELOC_X86_64_GOTTPOFF
},
9466 OPERAND_TYPE_IMM32_32S_DISP32
},
9467 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
9468 BFD_RELOC_X86_64_TPOFF32
},
9469 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9470 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
9471 _dummy_first_bfd_reloc_code_real
},
9472 OPERAND_TYPE_NONE
},
9473 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
9474 BFD_RELOC_X86_64_DTPOFF32
},
9475 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9476 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
9477 _dummy_first_bfd_reloc_code_real
},
9478 OPERAND_TYPE_NONE
},
9479 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
9480 _dummy_first_bfd_reloc_code_real
},
9481 OPERAND_TYPE_NONE
},
9482 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
9483 BFD_RELOC_X86_64_GOT32
},
9484 OPERAND_TYPE_IMM32_32S_64_DISP32
},
9485 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
9486 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
9487 OPERAND_TYPE_IMM32_32S_DISP32
},
9488 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
9489 BFD_RELOC_X86_64_TLSDESC_CALL
},
9490 OPERAND_TYPE_IMM32_32S_DISP32
},
9495 #if defined (OBJ_MAYBE_ELF)
9500 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9501 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9504 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9506 int len
= gotrel
[j
].len
;
9507 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9509 if (gotrel
[j
].rel
[object_64bit
] != 0)
9512 char *tmpbuf
, *past_reloc
;
9514 *rel
= gotrel
[j
].rel
[object_64bit
];
9518 if (flag_code
!= CODE_64BIT
)
9520 types
->bitfield
.imm32
= 1;
9521 types
->bitfield
.disp32
= 1;
9524 *types
= gotrel
[j
].types64
;
9527 if (j
!= 0 && GOT_symbol
== NULL
)
9528 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
9530 /* The length of the first part of our input line. */
9531 first
= cp
- input_line_pointer
;
9533 /* The second part goes from after the reloc token until
9534 (and including) an end_of_line char or comma. */
9535 past_reloc
= cp
+ 1 + len
;
9537 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9539 second
= cp
+ 1 - past_reloc
;
9541 /* Allocate and copy string. The trailing NUL shouldn't
9542 be necessary, but be safe. */
9543 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9544 memcpy (tmpbuf
, input_line_pointer
, first
);
9545 if (second
!= 0 && *past_reloc
!= ' ')
9546 /* Replace the relocation token with ' ', so that
9547 errors like foo@GOTOFF1 will be detected. */
9548 tmpbuf
[first
++] = ' ';
9550 /* Increment length by 1 if the relocation token is
9555 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9556 tmpbuf
[first
+ second
] = '\0';
9560 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9561 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9566 /* Might be a symbol version string. Don't as_bad here. */
9575 /* Parse operands of the form
9576 <symbol>@SECREL32+<nnn>
9578 If we find one, set up the correct relocation in RELOC and copy the
9579 input string, minus the `@SECREL32' into a malloc'd buffer for
9580 parsing by the calling routine. Return this buffer, and if ADJUST
9581 is non-null set it to the length of the string we removed from the
9582 input line. Otherwise return NULL.
9584 This function is copied from the ELF version above adjusted for PE targets. */
9587 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
9588 int *adjust ATTRIBUTE_UNUSED
,
9589 i386_operand_type
*types
)
9595 const enum bfd_reloc_code_real rel
[2];
9596 const i386_operand_type types64
;
9600 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
9601 BFD_RELOC_32_SECREL
},
9602 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9608 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9609 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9612 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9614 int len
= gotrel
[j
].len
;
9616 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9618 if (gotrel
[j
].rel
[object_64bit
] != 0)
9621 char *tmpbuf
, *past_reloc
;
9623 *rel
= gotrel
[j
].rel
[object_64bit
];
9629 if (flag_code
!= CODE_64BIT
)
9631 types
->bitfield
.imm32
= 1;
9632 types
->bitfield
.disp32
= 1;
9635 *types
= gotrel
[j
].types64
;
9638 /* The length of the first part of our input line. */
9639 first
= cp
- input_line_pointer
;
9641 /* The second part goes from after the reloc token until
9642 (and including) an end_of_line char or comma. */
9643 past_reloc
= cp
+ 1 + len
;
9645 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9647 second
= cp
+ 1 - past_reloc
;
9649 /* Allocate and copy string. The trailing NUL shouldn't
9650 be necessary, but be safe. */
9651 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9652 memcpy (tmpbuf
, input_line_pointer
, first
);
9653 if (second
!= 0 && *past_reloc
!= ' ')
9654 /* Replace the relocation token with ' ', so that
9655 errors like foo@SECLREL321 will be detected. */
9656 tmpbuf
[first
++] = ' ';
9657 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9658 tmpbuf
[first
+ second
] = '\0';
9662 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9663 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9668 /* Might be a symbol version string. Don't as_bad here. */
9674 bfd_reloc_code_real_type
9675 x86_cons (expressionS
*exp
, int size
)
9677 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9679 intel_syntax
= -intel_syntax
;
9682 if (size
== 4 || (object_64bit
&& size
== 8))
9684 /* Handle @GOTOFF and the like in an expression. */
9686 char *gotfree_input_line
;
9689 save
= input_line_pointer
;
9690 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
9691 if (gotfree_input_line
)
9692 input_line_pointer
= gotfree_input_line
;
9696 if (gotfree_input_line
)
9698 /* expression () has merrily parsed up to the end of line,
9699 or a comma - in the wrong buffer. Transfer how far
9700 input_line_pointer has moved to the right buffer. */
9701 input_line_pointer
= (save
9702 + (input_line_pointer
- gotfree_input_line
)
9704 free (gotfree_input_line
);
9705 if (exp
->X_op
== O_constant
9706 || exp
->X_op
== O_absent
9707 || exp
->X_op
== O_illegal
9708 || exp
->X_op
== O_register
9709 || exp
->X_op
== O_big
)
9711 char c
= *input_line_pointer
;
9712 *input_line_pointer
= 0;
9713 as_bad (_("missing or invalid expression `%s'"), save
);
9714 *input_line_pointer
= c
;
9716 else if ((got_reloc
== BFD_RELOC_386_PLT32
9717 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9718 && exp
->X_op
!= O_symbol
)
9720 char c
= *input_line_pointer
;
9721 *input_line_pointer
= 0;
9722 as_bad (_("invalid PLT expression `%s'"), save
);
9723 *input_line_pointer
= c
;
9730 intel_syntax
= -intel_syntax
;
9733 i386_intel_simplify (exp
);
9739 signed_cons (int size
)
9741 if (flag_code
== CODE_64BIT
)
9749 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9756 if (exp
.X_op
== O_symbol
)
9757 exp
.X_op
= O_secrel
;
9759 emit_expr (&exp
, 4);
9761 while (*input_line_pointer
++ == ',');
9763 input_line_pointer
--;
9764 demand_empty_rest_of_line ();
9768 /* Handle Vector operations. */
9771 check_VecOperations (char *op_string
, char *op_end
)
9773 const reg_entry
*mask
;
9778 && (op_end
== NULL
|| op_string
< op_end
))
9781 if (*op_string
== '{')
9785 /* Check broadcasts. */
9786 if (strncmp (op_string
, "1to", 3) == 0)
9791 goto duplicated_vec_op
;
9794 if (*op_string
== '8')
9796 else if (*op_string
== '4')
9798 else if (*op_string
== '2')
9800 else if (*op_string
== '1'
9801 && *(op_string
+1) == '6')
9808 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9813 broadcast_op
.type
= bcst_type
;
9814 broadcast_op
.operand
= this_operand
;
9815 broadcast_op
.bytes
= 0;
9816 i
.broadcast
= &broadcast_op
;
9818 /* Check masking operation. */
9819 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9821 /* k0 can't be used for write mask. */
9822 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
9824 as_bad (_("`%s%s' can't be used for write mask"),
9825 register_prefix
, mask
->reg_name
);
9831 mask_op
.mask
= mask
;
9832 mask_op
.zeroing
= 0;
9833 mask_op
.operand
= this_operand
;
9839 goto duplicated_vec_op
;
9841 i
.mask
->mask
= mask
;
9843 /* Only "{z}" is allowed here. No need to check
9844 zeroing mask explicitly. */
9845 if (i
.mask
->operand
!= this_operand
)
9847 as_bad (_("invalid write mask `%s'"), saved
);
9854 /* Check zeroing-flag for masking operation. */
9855 else if (*op_string
== 'z')
9859 mask_op
.mask
= NULL
;
9860 mask_op
.zeroing
= 1;
9861 mask_op
.operand
= this_operand
;
9866 if (i
.mask
->zeroing
)
9869 as_bad (_("duplicated `%s'"), saved
);
9873 i
.mask
->zeroing
= 1;
9875 /* Only "{%k}" is allowed here. No need to check mask
9876 register explicitly. */
9877 if (i
.mask
->operand
!= this_operand
)
9879 as_bad (_("invalid zeroing-masking `%s'"),
9888 goto unknown_vec_op
;
9890 if (*op_string
!= '}')
9892 as_bad (_("missing `}' in `%s'"), saved
);
9897 /* Strip whitespace since the addition of pseudo prefixes
9898 changed how the scrubber treats '{'. */
9899 if (is_space_char (*op_string
))
9905 /* We don't know this one. */
9906 as_bad (_("unknown vector operation: `%s'"), saved
);
9910 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9912 as_bad (_("zeroing-masking only allowed with write mask"));
9920 i386_immediate (char *imm_start
)
9922 char *save_input_line_pointer
;
9923 char *gotfree_input_line
;
9926 i386_operand_type types
;
9928 operand_type_set (&types
, ~0);
9930 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9932 as_bad (_("at most %d immediate operands are allowed"),
9933 MAX_IMMEDIATE_OPERANDS
);
9937 exp
= &im_expressions
[i
.imm_operands
++];
9938 i
.op
[this_operand
].imms
= exp
;
9940 if (is_space_char (*imm_start
))
9943 save_input_line_pointer
= input_line_pointer
;
9944 input_line_pointer
= imm_start
;
9946 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9947 if (gotfree_input_line
)
9948 input_line_pointer
= gotfree_input_line
;
9950 exp_seg
= expression (exp
);
9954 /* Handle vector operations. */
9955 if (*input_line_pointer
== '{')
9957 input_line_pointer
= check_VecOperations (input_line_pointer
,
9959 if (input_line_pointer
== NULL
)
9963 if (*input_line_pointer
)
9964 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9966 input_line_pointer
= save_input_line_pointer
;
9967 if (gotfree_input_line
)
9969 free (gotfree_input_line
);
9971 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9972 exp
->X_op
= O_illegal
;
9975 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9979 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9980 i386_operand_type types
, const char *imm_start
)
9982 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9985 as_bad (_("missing or invalid immediate expression `%s'"),
9989 else if (exp
->X_op
== O_constant
)
9991 /* Size it properly later. */
9992 i
.types
[this_operand
].bitfield
.imm64
= 1;
9993 /* If not 64bit, sign extend val. */
9994 if (flag_code
!= CODE_64BIT
9995 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9997 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9999 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10000 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10001 && exp_seg
!= absolute_section
10002 && exp_seg
!= text_section
10003 && exp_seg
!= data_section
10004 && exp_seg
!= bss_section
10005 && exp_seg
!= undefined_section
10006 && !bfd_is_com_section (exp_seg
))
10008 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10012 else if (!intel_syntax
&& exp_seg
== reg_section
)
10015 as_bad (_("illegal immediate register operand %s"), imm_start
);
10020 /* This is an address. The size of the address will be
10021 determined later, depending on destination register,
10022 suffix, or the default for the section. */
10023 i
.types
[this_operand
].bitfield
.imm8
= 1;
10024 i
.types
[this_operand
].bitfield
.imm16
= 1;
10025 i
.types
[this_operand
].bitfield
.imm32
= 1;
10026 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10027 i
.types
[this_operand
].bitfield
.imm64
= 1;
10028 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10036 i386_scale (char *scale
)
10039 char *save
= input_line_pointer
;
10041 input_line_pointer
= scale
;
10042 val
= get_absolute_expression ();
10047 i
.log2_scale_factor
= 0;
10050 i
.log2_scale_factor
= 1;
10053 i
.log2_scale_factor
= 2;
10056 i
.log2_scale_factor
= 3;
10060 char sep
= *input_line_pointer
;
10062 *input_line_pointer
= '\0';
10063 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10065 *input_line_pointer
= sep
;
10066 input_line_pointer
= save
;
10070 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10072 as_warn (_("scale factor of %d without an index register"),
10073 1 << i
.log2_scale_factor
);
10074 i
.log2_scale_factor
= 0;
10076 scale
= input_line_pointer
;
10077 input_line_pointer
= save
;
10082 i386_displacement (char *disp_start
, char *disp_end
)
10086 char *save_input_line_pointer
;
10087 char *gotfree_input_line
;
10089 i386_operand_type bigdisp
, types
= anydisp
;
10092 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10094 as_bad (_("at most %d displacement operands are allowed"),
10095 MAX_MEMORY_OPERANDS
);
10099 operand_type_set (&bigdisp
, 0);
10101 || i
.types
[this_operand
].bitfield
.baseindex
10102 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10103 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10105 i386_addressing_mode ();
10106 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10107 if (flag_code
== CODE_64BIT
)
10111 bigdisp
.bitfield
.disp32s
= 1;
10112 bigdisp
.bitfield
.disp64
= 1;
10115 bigdisp
.bitfield
.disp32
= 1;
10117 else if ((flag_code
== CODE_16BIT
) ^ override
)
10118 bigdisp
.bitfield
.disp16
= 1;
10120 bigdisp
.bitfield
.disp32
= 1;
10124 /* For PC-relative branches, the width of the displacement may be
10125 dependent upon data size, but is never dependent upon address size.
10126 Also make sure to not unintentionally match against a non-PC-relative
10127 branch template. */
10128 static templates aux_templates
;
10129 const insn_template
*t
= current_templates
->start
;
10130 bfd_boolean has_intel64
= FALSE
;
10132 aux_templates
.start
= t
;
10133 while (++t
< current_templates
->end
)
10135 if (t
->opcode_modifier
.jump
10136 != current_templates
->start
->opcode_modifier
.jump
)
10138 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10139 has_intel64
= TRUE
;
10141 if (t
< current_templates
->end
)
10143 aux_templates
.end
= t
;
10144 current_templates
= &aux_templates
;
10147 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10148 if (flag_code
== CODE_64BIT
)
10150 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10151 && (!intel64
|| !has_intel64
))
10152 bigdisp
.bitfield
.disp16
= 1;
10154 bigdisp
.bitfield
.disp32s
= 1;
10159 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10161 : LONG_MNEM_SUFFIX
));
10162 bigdisp
.bitfield
.disp32
= 1;
10163 if ((flag_code
== CODE_16BIT
) ^ override
)
10165 bigdisp
.bitfield
.disp32
= 0;
10166 bigdisp
.bitfield
.disp16
= 1;
10170 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10173 exp
= &disp_expressions
[i
.disp_operands
];
10174 i
.op
[this_operand
].disps
= exp
;
10176 save_input_line_pointer
= input_line_pointer
;
10177 input_line_pointer
= disp_start
;
10178 END_STRING_AND_SAVE (disp_end
);
10180 #ifndef GCC_ASM_O_HACK
10181 #define GCC_ASM_O_HACK 0
10184 END_STRING_AND_SAVE (disp_end
+ 1);
10185 if (i
.types
[this_operand
].bitfield
.baseIndex
10186 && displacement_string_end
[-1] == '+')
10188 /* This hack is to avoid a warning when using the "o"
10189 constraint within gcc asm statements.
10192 #define _set_tssldt_desc(n,addr,limit,type) \
10193 __asm__ __volatile__ ( \
10194 "movw %w2,%0\n\t" \
10195 "movw %w1,2+%0\n\t" \
10196 "rorl $16,%1\n\t" \
10197 "movb %b1,4+%0\n\t" \
10198 "movb %4,5+%0\n\t" \
10199 "movb $0,6+%0\n\t" \
10200 "movb %h1,7+%0\n\t" \
10202 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10204 This works great except that the output assembler ends
10205 up looking a bit weird if it turns out that there is
10206 no offset. You end up producing code that looks like:
10219 So here we provide the missing zero. */
10221 *displacement_string_end
= '0';
10224 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10225 if (gotfree_input_line
)
10226 input_line_pointer
= gotfree_input_line
;
10228 exp_seg
= expression (exp
);
10230 SKIP_WHITESPACE ();
10231 if (*input_line_pointer
)
10232 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10234 RESTORE_END_STRING (disp_end
+ 1);
10236 input_line_pointer
= save_input_line_pointer
;
10237 if (gotfree_input_line
)
10239 free (gotfree_input_line
);
10241 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10242 exp
->X_op
= O_illegal
;
10245 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10247 RESTORE_END_STRING (disp_end
);
10253 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10254 i386_operand_type types
, const char *disp_start
)
10256 i386_operand_type bigdisp
;
10259 /* We do this to make sure that the section symbol is in
10260 the symbol table. We will ultimately change the relocation
10261 to be relative to the beginning of the section. */
10262 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10263 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10264 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10266 if (exp
->X_op
!= O_symbol
)
10269 if (S_IS_LOCAL (exp
->X_add_symbol
)
10270 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10271 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10272 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10273 exp
->X_op
= O_subtract
;
10274 exp
->X_op_symbol
= GOT_symbol
;
10275 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10276 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10277 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10278 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10280 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10283 else if (exp
->X_op
== O_absent
10284 || exp
->X_op
== O_illegal
10285 || exp
->X_op
== O_big
)
10288 as_bad (_("missing or invalid displacement expression `%s'"),
10293 else if (flag_code
== CODE_64BIT
10294 && !i
.prefix
[ADDR_PREFIX
]
10295 && exp
->X_op
== O_constant
)
10297 /* Since displacement is signed extended to 64bit, don't allow
10298 disp32 and turn off disp32s if they are out of range. */
10299 i
.types
[this_operand
].bitfield
.disp32
= 0;
10300 if (!fits_in_signed_long (exp
->X_add_number
))
10302 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10303 if (i
.types
[this_operand
].bitfield
.baseindex
)
10305 as_bad (_("0x%lx out range of signed 32bit displacement"),
10306 (long) exp
->X_add_number
);
10312 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10313 else if (exp
->X_op
!= O_constant
10314 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10315 && exp_seg
!= absolute_section
10316 && exp_seg
!= text_section
10317 && exp_seg
!= data_section
10318 && exp_seg
!= bss_section
10319 && exp_seg
!= undefined_section
10320 && !bfd_is_com_section (exp_seg
))
10322 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10327 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10328 /* Constants get taken care of by optimize_disp(). */
10329 && exp
->X_op
!= O_constant
)
10330 i
.types
[this_operand
].bitfield
.disp8
= 1;
10332 /* Check if this is a displacement only operand. */
10333 bigdisp
= i
.types
[this_operand
];
10334 bigdisp
.bitfield
.disp8
= 0;
10335 bigdisp
.bitfield
.disp16
= 0;
10336 bigdisp
.bitfield
.disp32
= 0;
10337 bigdisp
.bitfield
.disp32s
= 0;
10338 bigdisp
.bitfield
.disp64
= 0;
10339 if (operand_type_all_zero (&bigdisp
))
10340 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10346 /* Return the active addressing mode, taking address override and
10347 registers forming the address into consideration. Update the
10348 address override prefix if necessary. */
10350 static enum flag_code
10351 i386_addressing_mode (void)
10353 enum flag_code addr_mode
;
10355 if (i
.prefix
[ADDR_PREFIX
])
10356 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10359 addr_mode
= flag_code
;
10361 #if INFER_ADDR_PREFIX
10362 if (i
.mem_operands
== 0)
10364 /* Infer address prefix from the first memory operand. */
10365 const reg_entry
*addr_reg
= i
.base_reg
;
10367 if (addr_reg
== NULL
)
10368 addr_reg
= i
.index_reg
;
10372 if (addr_reg
->reg_type
.bitfield
.dword
)
10373 addr_mode
= CODE_32BIT
;
10374 else if (flag_code
!= CODE_64BIT
10375 && addr_reg
->reg_type
.bitfield
.word
)
10376 addr_mode
= CODE_16BIT
;
10378 if (addr_mode
!= flag_code
)
10380 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10382 /* Change the size of any displacement too. At most one
10383 of Disp16 or Disp32 is set.
10384 FIXME. There doesn't seem to be any real need for
10385 separate Disp16 and Disp32 flags. The same goes for
10386 Imm16 and Imm32. Removing them would probably clean
10387 up the code quite a lot. */
10388 if (flag_code
!= CODE_64BIT
10389 && (i
.types
[this_operand
].bitfield
.disp16
10390 || i
.types
[this_operand
].bitfield
.disp32
))
10391 i
.types
[this_operand
]
10392 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10402 /* Make sure the memory operand we've been dealt is valid.
10403 Return 1 on success, 0 on a failure. */
10406 i386_index_check (const char *operand_string
)
10408 const char *kind
= "base/index";
10409 enum flag_code addr_mode
= i386_addressing_mode ();
10411 if (current_templates
->start
->opcode_modifier
.isstring
10412 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
10413 && (current_templates
->end
[-1].opcode_modifier
.isstring
10414 || i
.mem_operands
))
10416 /* Memory operands of string insns are special in that they only allow
10417 a single register (rDI, rSI, or rBX) as their memory address. */
10418 const reg_entry
*expected_reg
;
10419 static const char *di_si
[][2] =
10425 static const char *bx
[] = { "ebx", "bx", "rbx" };
10427 kind
= "string address";
10429 if (current_templates
->start
->opcode_modifier
.repprefixok
)
10431 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
10432 - IS_STRING_ES_OP0
;
10435 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
10436 || ((!i
.mem_operands
!= !intel_syntax
)
10437 && current_templates
->end
[-1].operand_types
[1]
10438 .bitfield
.baseindex
))
10440 expected_reg
= hash_find (reg_hash
, di_si
[addr_mode
][op
== es_op
]);
10443 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
10445 if (i
.base_reg
!= expected_reg
10447 || operand_type_check (i
.types
[this_operand
], disp
))
10449 /* The second memory operand must have the same size as
10453 && !((addr_mode
== CODE_64BIT
10454 && i
.base_reg
->reg_type
.bitfield
.qword
)
10455 || (addr_mode
== CODE_32BIT
10456 ? i
.base_reg
->reg_type
.bitfield
.dword
10457 : i
.base_reg
->reg_type
.bitfield
.word
)))
10460 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
10462 intel_syntax
? '[' : '(',
10464 expected_reg
->reg_name
,
10465 intel_syntax
? ']' : ')');
10472 as_bad (_("`%s' is not a valid %s expression"),
10473 operand_string
, kind
);
10478 if (addr_mode
!= CODE_16BIT
)
10480 /* 32-bit/64-bit checks. */
10482 && ((addr_mode
== CODE_64BIT
10483 ? !i
.base_reg
->reg_type
.bitfield
.qword
10484 : !i
.base_reg
->reg_type
.bitfield
.dword
)
10485 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
10486 || i
.base_reg
->reg_num
== RegIZ
))
10488 && !i
.index_reg
->reg_type
.bitfield
.xmmword
10489 && !i
.index_reg
->reg_type
.bitfield
.ymmword
10490 && !i
.index_reg
->reg_type
.bitfield
.zmmword
10491 && ((addr_mode
== CODE_64BIT
10492 ? !i
.index_reg
->reg_type
.bitfield
.qword
10493 : !i
.index_reg
->reg_type
.bitfield
.dword
)
10494 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
10497 /* bndmk, bndldx, and bndstx have special restrictions. */
10498 if (current_templates
->start
->base_opcode
== 0xf30f1b
10499 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
10501 /* They cannot use RIP-relative addressing. */
10502 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
10504 as_bad (_("`%s' cannot be used here"), operand_string
);
10508 /* bndldx and bndstx ignore their scale factor. */
10509 if (current_templates
->start
->base_opcode
!= 0xf30f1b
10510 && i
.log2_scale_factor
)
10511 as_warn (_("register scaling is being ignored here"));
10516 /* 16-bit checks. */
10518 && (!i
.base_reg
->reg_type
.bitfield
.word
10519 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
10521 && (!i
.index_reg
->reg_type
.bitfield
.word
10522 || !i
.index_reg
->reg_type
.bitfield
.baseindex
10524 && i
.base_reg
->reg_num
< 6
10525 && i
.index_reg
->reg_num
>= 6
10526 && i
.log2_scale_factor
== 0))))
10533 /* Handle vector immediates. */
10536 RC_SAE_immediate (const char *imm_start
)
10538 unsigned int match_found
, j
;
10539 const char *pstr
= imm_start
;
10547 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
10549 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
10553 rc_op
.type
= RC_NamesTable
[j
].type
;
10554 rc_op
.operand
= this_operand
;
10555 i
.rounding
= &rc_op
;
10559 as_bad (_("duplicated `%s'"), imm_start
);
10562 pstr
+= RC_NamesTable
[j
].len
;
10570 if (*pstr
++ != '}')
10572 as_bad (_("Missing '}': '%s'"), imm_start
);
10575 /* RC/SAE immediate string should contain nothing more. */;
10578 as_bad (_("Junk after '}': '%s'"), imm_start
);
10582 exp
= &im_expressions
[i
.imm_operands
++];
10583 i
.op
[this_operand
].imms
= exp
;
10585 exp
->X_op
= O_constant
;
10586 exp
->X_add_number
= 0;
10587 exp
->X_add_symbol
= (symbolS
*) 0;
10588 exp
->X_op_symbol
= (symbolS
*) 0;
10590 i
.types
[this_operand
].bitfield
.imm8
= 1;
10594 /* Only string instructions can have a second memory operand, so
10595 reduce current_templates to just those if it contains any. */
10597 maybe_adjust_templates (void)
10599 const insn_template
*t
;
10601 gas_assert (i
.mem_operands
== 1);
10603 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
10604 if (t
->opcode_modifier
.isstring
)
10607 if (t
< current_templates
->end
)
10609 static templates aux_templates
;
10610 bfd_boolean recheck
;
10612 aux_templates
.start
= t
;
10613 for (; t
< current_templates
->end
; ++t
)
10614 if (!t
->opcode_modifier
.isstring
)
10616 aux_templates
.end
= t
;
10618 /* Determine whether to re-check the first memory operand. */
10619 recheck
= (aux_templates
.start
!= current_templates
->start
10620 || t
!= current_templates
->end
);
10622 current_templates
= &aux_templates
;
10626 i
.mem_operands
= 0;
10627 if (i
.memop1_string
!= NULL
10628 && i386_index_check (i
.memop1_string
) == 0)
10630 i
.mem_operands
= 1;
10637 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
10641 i386_att_operand (char *operand_string
)
10643 const reg_entry
*r
;
10645 char *op_string
= operand_string
;
10647 if (is_space_char (*op_string
))
10650 /* We check for an absolute prefix (differentiating,
10651 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
10652 if (*op_string
== ABSOLUTE_PREFIX
)
10655 if (is_space_char (*op_string
))
10657 i
.jumpabsolute
= TRUE
;
10660 /* Check if operand is a register. */
10661 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
10663 i386_operand_type temp
;
10665 /* Check for a segment override by searching for ':' after a
10666 segment register. */
10667 op_string
= end_op
;
10668 if (is_space_char (*op_string
))
10670 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
10672 switch (r
->reg_num
)
10675 i
.seg
[i
.mem_operands
] = &es
;
10678 i
.seg
[i
.mem_operands
] = &cs
;
10681 i
.seg
[i
.mem_operands
] = &ss
;
10684 i
.seg
[i
.mem_operands
] = &ds
;
10687 i
.seg
[i
.mem_operands
] = &fs
;
10690 i
.seg
[i
.mem_operands
] = &gs
;
10694 /* Skip the ':' and whitespace. */
10696 if (is_space_char (*op_string
))
10699 if (!is_digit_char (*op_string
)
10700 && !is_identifier_char (*op_string
)
10701 && *op_string
!= '('
10702 && *op_string
!= ABSOLUTE_PREFIX
)
10704 as_bad (_("bad memory operand `%s'"), op_string
);
10707 /* Handle case of %es:*foo. */
10708 if (*op_string
== ABSOLUTE_PREFIX
)
10711 if (is_space_char (*op_string
))
10713 i
.jumpabsolute
= TRUE
;
10715 goto do_memory_reference
;
10718 /* Handle vector operations. */
10719 if (*op_string
== '{')
10721 op_string
= check_VecOperations (op_string
, NULL
);
10722 if (op_string
== NULL
)
10728 as_bad (_("junk `%s' after register"), op_string
);
10731 temp
= r
->reg_type
;
10732 temp
.bitfield
.baseindex
= 0;
10733 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10735 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10736 i
.op
[this_operand
].regs
= r
;
10739 else if (*op_string
== REGISTER_PREFIX
)
10741 as_bad (_("bad register name `%s'"), op_string
);
10744 else if (*op_string
== IMMEDIATE_PREFIX
)
10747 if (i
.jumpabsolute
)
10749 as_bad (_("immediate operand illegal with absolute jump"));
10752 if (!i386_immediate (op_string
))
10755 else if (RC_SAE_immediate (operand_string
))
10757 /* If it is a RC or SAE immediate, do nothing. */
10760 else if (is_digit_char (*op_string
)
10761 || is_identifier_char (*op_string
)
10762 || *op_string
== '"'
10763 || *op_string
== '(')
10765 /* This is a memory reference of some sort. */
10768 /* Start and end of displacement string expression (if found). */
10769 char *displacement_string_start
;
10770 char *displacement_string_end
;
10773 do_memory_reference
:
10774 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10776 if ((i
.mem_operands
== 1
10777 && !current_templates
->start
->opcode_modifier
.isstring
)
10778 || i
.mem_operands
== 2)
10780 as_bad (_("too many memory references for `%s'"),
10781 current_templates
->start
->name
);
10785 /* Check for base index form. We detect the base index form by
10786 looking for an ')' at the end of the operand, searching
10787 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10789 base_string
= op_string
+ strlen (op_string
);
10791 /* Handle vector operations. */
10792 vop_start
= strchr (op_string
, '{');
10793 if (vop_start
&& vop_start
< base_string
)
10795 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10797 base_string
= vop_start
;
10801 if (is_space_char (*base_string
))
10804 /* If we only have a displacement, set-up for it to be parsed later. */
10805 displacement_string_start
= op_string
;
10806 displacement_string_end
= base_string
+ 1;
10808 if (*base_string
== ')')
10811 unsigned int parens_balanced
= 1;
10812 /* We've already checked that the number of left & right ()'s are
10813 equal, so this loop will not be infinite. */
10817 if (*base_string
== ')')
10819 if (*base_string
== '(')
10822 while (parens_balanced
);
10824 temp_string
= base_string
;
10826 /* Skip past '(' and whitespace. */
10828 if (is_space_char (*base_string
))
10831 if (*base_string
== ','
10832 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10835 displacement_string_end
= temp_string
;
10837 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10841 base_string
= end_op
;
10842 if (is_space_char (*base_string
))
10846 /* There may be an index reg or scale factor here. */
10847 if (*base_string
== ',')
10850 if (is_space_char (*base_string
))
10853 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10856 base_string
= end_op
;
10857 if (is_space_char (*base_string
))
10859 if (*base_string
== ',')
10862 if (is_space_char (*base_string
))
10865 else if (*base_string
!= ')')
10867 as_bad (_("expecting `,' or `)' "
10868 "after index register in `%s'"),
10873 else if (*base_string
== REGISTER_PREFIX
)
10875 end_op
= strchr (base_string
, ',');
10878 as_bad (_("bad register name `%s'"), base_string
);
10882 /* Check for scale factor. */
10883 if (*base_string
!= ')')
10885 char *end_scale
= i386_scale (base_string
);
10890 base_string
= end_scale
;
10891 if (is_space_char (*base_string
))
10893 if (*base_string
!= ')')
10895 as_bad (_("expecting `)' "
10896 "after scale factor in `%s'"),
10901 else if (!i
.index_reg
)
10903 as_bad (_("expecting index register or scale factor "
10904 "after `,'; got '%c'"),
10909 else if (*base_string
!= ')')
10911 as_bad (_("expecting `,' or `)' "
10912 "after base register in `%s'"),
10917 else if (*base_string
== REGISTER_PREFIX
)
10919 end_op
= strchr (base_string
, ',');
10922 as_bad (_("bad register name `%s'"), base_string
);
10927 /* If there's an expression beginning the operand, parse it,
10928 assuming displacement_string_start and
10929 displacement_string_end are meaningful. */
10930 if (displacement_string_start
!= displacement_string_end
)
10932 if (!i386_displacement (displacement_string_start
,
10933 displacement_string_end
))
10937 /* Special case for (%dx) while doing input/output op. */
10939 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
10940 && i
.base_reg
->reg_type
.bitfield
.word
10941 && i
.index_reg
== 0
10942 && i
.log2_scale_factor
== 0
10943 && i
.seg
[i
.mem_operands
] == 0
10944 && !operand_type_check (i
.types
[this_operand
], disp
))
10946 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10950 if (i386_index_check (operand_string
) == 0)
10952 i
.flags
[this_operand
] |= Operand_Mem
;
10953 if (i
.mem_operands
== 0)
10954 i
.memop1_string
= xstrdup (operand_string
);
10959 /* It's not a memory operand; argh! */
10960 as_bad (_("invalid char %s beginning operand %d `%s'"),
10961 output_invalid (*op_string
),
10966 return 1; /* Normal return. */
10969 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10970 that an rs_machine_dependent frag may reach. */
10973 i386_frag_max_var (fragS
*frag
)
10975 /* The only relaxable frags are for jumps.
10976 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10977 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10978 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10981 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10983 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10985 /* STT_GNU_IFUNC symbol must go through PLT. */
10986 if ((symbol_get_bfdsym (fr_symbol
)->flags
10987 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10990 if (!S_IS_EXTERNAL (fr_symbol
))
10991 /* Symbol may be weak or local. */
10992 return !S_IS_WEAK (fr_symbol
);
10994 /* Global symbols with non-default visibility can't be preempted. */
10995 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10998 if (fr_var
!= NO_RELOC
)
10999 switch ((enum bfd_reloc_code_real
) fr_var
)
11001 case BFD_RELOC_386_PLT32
:
11002 case BFD_RELOC_X86_64_PLT32
:
11003 /* Symbol with PLT relocation may be preempted. */
11009 /* Global symbols with default visibility in a shared library may be
11010 preempted by another definition. */
11015 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11016 Note also work for Skylake and Cascadelake.
11017 ---------------------------------------------------------------------
11018 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11019 | ------ | ----------- | ------- | -------- |
11021 | Jno | N | N | Y |
11022 | Jc/Jb | Y | N | Y |
11023 | Jae/Jnb | Y | N | Y |
11024 | Je/Jz | Y | Y | Y |
11025 | Jne/Jnz | Y | Y | Y |
11026 | Jna/Jbe | Y | N | Y |
11027 | Ja/Jnbe | Y | N | Y |
11029 | Jns | N | N | Y |
11030 | Jp/Jpe | N | N | Y |
11031 | Jnp/Jpo | N | N | Y |
11032 | Jl/Jnge | Y | Y | Y |
11033 | Jge/Jnl | Y | Y | Y |
11034 | Jle/Jng | Y | Y | Y |
11035 | Jg/Jnle | Y | Y | Y |
11036 --------------------------------------------------------------------- */
11038 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11040 if (mf_cmp
== mf_cmp_alu_cmp
)
11041 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11042 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11043 if (mf_cmp
== mf_cmp_incdec
)
11044 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11045 || mf_jcc
== mf_jcc_jle
);
11046 if (mf_cmp
== mf_cmp_test_and
)
11051 /* Return the next non-empty frag. */
11054 i386_next_non_empty_frag (fragS
*fragP
)
11056 /* There may be a frag with a ".fill 0" when there is no room in
11057 the current frag for frag_grow in output_insn. */
11058 for (fragP
= fragP
->fr_next
;
11060 && fragP
->fr_type
== rs_fill
11061 && fragP
->fr_fix
== 0);
11062 fragP
= fragP
->fr_next
)
11067 /* Return the next jcc frag after BRANCH_PADDING. */
11070 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11072 fragS
*branch_fragP
;
11076 if (pad_fragP
->fr_type
== rs_machine_dependent
11077 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11078 == BRANCH_PADDING
))
11080 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11081 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11083 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11084 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11085 pad_fragP
->tc_frag_data
.mf_type
))
11086 return branch_fragP
;
11092 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11095 i386_classify_machine_dependent_frag (fragS
*fragP
)
11099 fragS
*branch_fragP
;
11101 unsigned int max_prefix_length
;
11103 if (fragP
->tc_frag_data
.classified
)
11106 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11107 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11108 for (next_fragP
= fragP
;
11109 next_fragP
!= NULL
;
11110 next_fragP
= next_fragP
->fr_next
)
11112 next_fragP
->tc_frag_data
.classified
= 1;
11113 if (next_fragP
->fr_type
== rs_machine_dependent
)
11114 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11116 case BRANCH_PADDING
:
11117 /* The BRANCH_PADDING frag must be followed by a branch
11119 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11120 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11122 case FUSED_JCC_PADDING
:
11123 /* Check if this is a fused jcc:
11125 CMP like instruction
11129 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11130 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11131 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11134 /* The BRANCH_PADDING frag is merged with the
11135 FUSED_JCC_PADDING frag. */
11136 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11137 /* CMP like instruction size. */
11138 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11139 frag_wane (pad_fragP
);
11140 /* Skip to branch_fragP. */
11141 next_fragP
= branch_fragP
;
11143 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11145 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11147 next_fragP
->fr_subtype
11148 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11149 next_fragP
->tc_frag_data
.max_bytes
11150 = next_fragP
->tc_frag_data
.max_prefix_length
;
11151 /* This will be updated in the BRANCH_PREFIX scan. */
11152 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11155 frag_wane (next_fragP
);
11160 /* Stop if there is no BRANCH_PREFIX. */
11161 if (!align_branch_prefix_size
)
11164 /* Scan for BRANCH_PREFIX. */
11165 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11167 if (fragP
->fr_type
!= rs_machine_dependent
11168 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11172 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11173 COND_JUMP_PREFIX. */
11174 max_prefix_length
= 0;
11175 for (next_fragP
= fragP
;
11176 next_fragP
!= NULL
;
11177 next_fragP
= next_fragP
->fr_next
)
11179 if (next_fragP
->fr_type
== rs_fill
)
11180 /* Skip rs_fill frags. */
11182 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11183 /* Stop for all other frags. */
11186 /* rs_machine_dependent frags. */
11187 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11190 /* Count BRANCH_PREFIX frags. */
11191 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11193 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11194 frag_wane (next_fragP
);
11198 += next_fragP
->tc_frag_data
.max_bytes
;
11200 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11202 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11203 == FUSED_JCC_PADDING
))
11205 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11206 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11210 /* Stop for other rs_machine_dependent frags. */
11214 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11216 /* Skip to the next frag. */
11217 fragP
= next_fragP
;
11221 /* Compute padding size for
11224 CMP like instruction
11226 COND_JUMP/UNCOND_JUMP
11231 COND_JUMP/UNCOND_JUMP
11235 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11237 unsigned int offset
, size
, padding_size
;
11238 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11240 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11242 address
= fragP
->fr_address
;
11243 address
+= fragP
->fr_fix
;
11245 /* CMP like instrunction size. */
11246 size
= fragP
->tc_frag_data
.cmp_size
;
11248 /* The base size of the branch frag. */
11249 size
+= branch_fragP
->fr_fix
;
11251 /* Add opcode and displacement bytes for the rs_machine_dependent
11253 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11254 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11256 /* Check if branch is within boundary and doesn't end at the last
11258 offset
= address
& ((1U << align_branch_power
) - 1);
11259 if ((offset
+ size
) >= (1U << align_branch_power
))
11260 /* Padding needed to avoid crossing boundary. */
11261 padding_size
= (1U << align_branch_power
) - offset
;
11263 /* No padding needed. */
11266 /* The return value may be saved in tc_frag_data.length which is
11268 if (!fits_in_unsigned_byte (padding_size
))
11271 return padding_size
;
11274 /* i386_generic_table_relax_frag()
11276 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11277 grow/shrink padding to align branch frags. Hand others to
11281 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11283 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11284 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11286 long padding_size
= i386_branch_padding_size (fragP
, 0);
11287 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11289 /* When the BRANCH_PREFIX frag is used, the computed address
11290 must match the actual address and there should be no padding. */
11291 if (fragP
->tc_frag_data
.padding_address
11292 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11296 /* Update the padding size. */
11298 fragP
->tc_frag_data
.length
= padding_size
;
11302 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11304 fragS
*padding_fragP
, *next_fragP
;
11305 long padding_size
, left_size
, last_size
;
11307 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11308 if (!padding_fragP
)
11309 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11310 return (fragP
->tc_frag_data
.length
11311 - fragP
->tc_frag_data
.last_length
);
11313 /* Compute the relative address of the padding frag in the very
11314 first time where the BRANCH_PREFIX frag sizes are zero. */
11315 if (!fragP
->tc_frag_data
.padding_address
)
11316 fragP
->tc_frag_data
.padding_address
11317 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11319 /* First update the last length from the previous interation. */
11320 left_size
= fragP
->tc_frag_data
.prefix_length
;
11321 for (next_fragP
= fragP
;
11322 next_fragP
!= padding_fragP
;
11323 next_fragP
= next_fragP
->fr_next
)
11324 if (next_fragP
->fr_type
== rs_machine_dependent
11325 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11330 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11334 if (max
> left_size
)
11339 next_fragP
->tc_frag_data
.last_length
= size
;
11343 next_fragP
->tc_frag_data
.last_length
= 0;
11346 /* Check the padding size for the padding frag. */
11347 padding_size
= i386_branch_padding_size
11348 (padding_fragP
, (fragP
->fr_address
11349 + fragP
->tc_frag_data
.padding_address
));
11351 last_size
= fragP
->tc_frag_data
.prefix_length
;
11352 /* Check if there is change from the last interation. */
11353 if (padding_size
== last_size
)
11355 /* Update the expected address of the padding frag. */
11356 padding_fragP
->tc_frag_data
.padding_address
11357 = (fragP
->fr_address
+ padding_size
11358 + fragP
->tc_frag_data
.padding_address
);
11362 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11364 /* No padding if there is no sufficient room. Clear the
11365 expected address of the padding frag. */
11366 padding_fragP
->tc_frag_data
.padding_address
= 0;
11370 /* Store the expected address of the padding frag. */
11371 padding_fragP
->tc_frag_data
.padding_address
11372 = (fragP
->fr_address
+ padding_size
11373 + fragP
->tc_frag_data
.padding_address
);
11375 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11377 /* Update the length for the current interation. */
11378 left_size
= padding_size
;
11379 for (next_fragP
= fragP
;
11380 next_fragP
!= padding_fragP
;
11381 next_fragP
= next_fragP
->fr_next
)
11382 if (next_fragP
->fr_type
== rs_machine_dependent
11383 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11388 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11392 if (max
> left_size
)
11397 next_fragP
->tc_frag_data
.length
= size
;
11401 next_fragP
->tc_frag_data
.length
= 0;
11404 return (fragP
->tc_frag_data
.length
11405 - fragP
->tc_frag_data
.last_length
);
11407 return relax_frag (segment
, fragP
, stretch
);
11410 /* md_estimate_size_before_relax()
11412 Called just before relax() for rs_machine_dependent frags. The x86
11413 assembler uses these frags to handle variable size jump
11416 Any symbol that is now undefined will not become defined.
11417 Return the correct fr_subtype in the frag.
11418 Return the initial "guess for variable size of frag" to caller.
11419 The guess is actually the growth beyond the fixed part. Whatever
11420 we do to grow the fixed or variable part contributes to our
11424 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
11426 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11427 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
11428 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11430 i386_classify_machine_dependent_frag (fragP
);
11431 return fragP
->tc_frag_data
.length
;
11434 /* We've already got fragP->fr_subtype right; all we have to do is
11435 check for un-relaxable symbols. On an ELF system, we can't relax
11436 an externally visible symbol, because it may be overridden by a
11438 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
11439 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11441 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
11444 #if defined (OBJ_COFF) && defined (TE_PE)
11445 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
11446 && S_IS_WEAK (fragP
->fr_symbol
))
11450 /* Symbol is undefined in this segment, or we need to keep a
11451 reloc so that weak symbols can be overridden. */
11452 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
11453 enum bfd_reloc_code_real reloc_type
;
11454 unsigned char *opcode
;
11457 if (fragP
->fr_var
!= NO_RELOC
)
11458 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
11459 else if (size
== 2)
11460 reloc_type
= BFD_RELOC_16_PCREL
;
11461 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11462 else if (need_plt32_p (fragP
->fr_symbol
))
11463 reloc_type
= BFD_RELOC_X86_64_PLT32
;
11466 reloc_type
= BFD_RELOC_32_PCREL
;
11468 old_fr_fix
= fragP
->fr_fix
;
11469 opcode
= (unsigned char *) fragP
->fr_opcode
;
11471 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
11474 /* Make jmp (0xeb) a (d)word displacement jump. */
11476 fragP
->fr_fix
+= size
;
11477 fix_new (fragP
, old_fr_fix
, size
,
11479 fragP
->fr_offset
, 1,
11485 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
11487 /* Negate the condition, and branch past an
11488 unconditional jump. */
11491 /* Insert an unconditional jump. */
11493 /* We added two extra opcode bytes, and have a two byte
11495 fragP
->fr_fix
+= 2 + 2;
11496 fix_new (fragP
, old_fr_fix
+ 2, 2,
11498 fragP
->fr_offset
, 1,
11502 /* Fall through. */
11505 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
11509 fragP
->fr_fix
+= 1;
11510 fixP
= fix_new (fragP
, old_fr_fix
, 1,
11512 fragP
->fr_offset
, 1,
11513 BFD_RELOC_8_PCREL
);
11514 fixP
->fx_signed
= 1;
11518 /* This changes the byte-displacement jump 0x7N
11519 to the (d)word-displacement jump 0x0f,0x8N. */
11520 opcode
[1] = opcode
[0] + 0x10;
11521 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11522 /* We've added an opcode byte. */
11523 fragP
->fr_fix
+= 1 + size
;
11524 fix_new (fragP
, old_fr_fix
+ 1, size
,
11526 fragP
->fr_offset
, 1,
11531 BAD_CASE (fragP
->fr_subtype
);
11535 return fragP
->fr_fix
- old_fr_fix
;
11538 /* Guess size depending on current relax state. Initially the relax
11539 state will correspond to a short jump and we return 1, because
11540 the variable part of the frag (the branch offset) is one byte
11541 long. However, we can relax a section more than once and in that
11542 case we must either set fr_subtype back to the unrelaxed state,
11543 or return the value for the appropriate branch. */
11544 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
11547 /* Called after relax() is finished.
11549 In: Address of frag.
11550 fr_type == rs_machine_dependent.
11551 fr_subtype is what the address relaxed to.
11553 Out: Any fixSs and constants are set up.
11554 Caller will turn frag into a ".space 0". */
11557 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
11560 unsigned char *opcode
;
11561 unsigned char *where_to_put_displacement
= NULL
;
11562 offsetT target_address
;
11563 offsetT opcode_address
;
11564 unsigned int extension
= 0;
11565 offsetT displacement_from_opcode_start
;
11567 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11568 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
11569 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11571 /* Generate nop padding. */
11572 unsigned int size
= fragP
->tc_frag_data
.length
;
11575 if (size
> fragP
->tc_frag_data
.max_bytes
)
11581 const char *branch
= "branch";
11582 const char *prefix
= "";
11583 fragS
*padding_fragP
;
11584 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11587 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11588 switch (fragP
->tc_frag_data
.default_prefix
)
11593 case CS_PREFIX_OPCODE
:
11596 case DS_PREFIX_OPCODE
:
11599 case ES_PREFIX_OPCODE
:
11602 case FS_PREFIX_OPCODE
:
11605 case GS_PREFIX_OPCODE
:
11608 case SS_PREFIX_OPCODE
:
11613 msg
= _("%s:%u: add %d%s at 0x%llx to align "
11614 "%s within %d-byte boundary\n");
11616 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
11617 "align %s within %d-byte boundary\n");
11621 padding_fragP
= fragP
;
11622 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
11623 "%s within %d-byte boundary\n");
11627 switch (padding_fragP
->tc_frag_data
.branch_type
)
11629 case align_branch_jcc
:
11632 case align_branch_fused
:
11633 branch
= "fused jcc";
11635 case align_branch_jmp
:
11638 case align_branch_call
:
11641 case align_branch_indirect
:
11642 branch
= "indiret branch";
11644 case align_branch_ret
:
11651 fprintf (stdout
, msg
,
11652 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
11653 (long long) fragP
->fr_address
, branch
,
11654 1 << align_branch_power
);
11656 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11657 memset (fragP
->fr_opcode
,
11658 fragP
->tc_frag_data
.default_prefix
, size
);
11660 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
11662 fragP
->fr_fix
+= size
;
11667 opcode
= (unsigned char *) fragP
->fr_opcode
;
11669 /* Address we want to reach in file space. */
11670 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
11672 /* Address opcode resides at in file space. */
11673 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
11675 /* Displacement from opcode start to fill into instruction. */
11676 displacement_from_opcode_start
= target_address
- opcode_address
;
11678 if ((fragP
->fr_subtype
& BIG
) == 0)
11680 /* Don't have to change opcode. */
11681 extension
= 1; /* 1 opcode + 1 displacement */
11682 where_to_put_displacement
= &opcode
[1];
11686 if (no_cond_jump_promotion
11687 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
11688 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
11689 _("long jump required"));
11691 switch (fragP
->fr_subtype
)
11693 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
11694 extension
= 4; /* 1 opcode + 4 displacement */
11696 where_to_put_displacement
= &opcode
[1];
11699 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
11700 extension
= 2; /* 1 opcode + 2 displacement */
11702 where_to_put_displacement
= &opcode
[1];
11705 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
11706 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
11707 extension
= 5; /* 2 opcode + 4 displacement */
11708 opcode
[1] = opcode
[0] + 0x10;
11709 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11710 where_to_put_displacement
= &opcode
[2];
11713 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
11714 extension
= 3; /* 2 opcode + 2 displacement */
11715 opcode
[1] = opcode
[0] + 0x10;
11716 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11717 where_to_put_displacement
= &opcode
[2];
11720 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
11725 where_to_put_displacement
= &opcode
[3];
11729 BAD_CASE (fragP
->fr_subtype
);
11734 /* If size if less then four we are sure that the operand fits,
11735 but if it's 4, then it could be that the displacement is larger
11737 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
11739 && ((addressT
) (displacement_from_opcode_start
- extension
11740 + ((addressT
) 1 << 31))
11741 > (((addressT
) 2 << 31) - 1)))
11743 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
11744 _("jump target out of range"));
11745 /* Make us emit 0. */
11746 displacement_from_opcode_start
= extension
;
11748 /* Now put displacement after opcode. */
11749 md_number_to_chars ((char *) where_to_put_displacement
,
11750 (valueT
) (displacement_from_opcode_start
- extension
),
11751 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
11752 fragP
->fr_fix
+= extension
;
11755 /* Apply a fixup (fixP) to segment data, once it has been determined
11756 by our caller that we have all the info we need to fix it up.
11758 Parameter valP is the pointer to the value of the bits.
11760 On the 386, immediates, displacements, and data pointers are all in
11761 the same (little-endian) format, so we don't need to care about which
11762 we are handling. */
11765 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11767 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
11768 valueT value
= *valP
;
11770 #if !defined (TE_Mach)
11771 if (fixP
->fx_pcrel
)
11773 switch (fixP
->fx_r_type
)
11779 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
11782 case BFD_RELOC_X86_64_32S
:
11783 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
11786 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
11789 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
11794 if (fixP
->fx_addsy
!= NULL
11795 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
11796 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
11797 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
11798 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
11799 && !use_rela_relocations
)
11801 /* This is a hack. There should be a better way to handle this.
11802 This covers for the fact that bfd_install_relocation will
11803 subtract the current location (for partial_inplace, PC relative
11804 relocations); see more below. */
11808 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
11811 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11813 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11816 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
11818 if ((sym_seg
== seg
11819 || (symbol_section_p (fixP
->fx_addsy
)
11820 && sym_seg
!= absolute_section
))
11821 && !generic_force_reloc (fixP
))
11823 /* Yes, we add the values in twice. This is because
11824 bfd_install_relocation subtracts them out again. I think
11825 bfd_install_relocation is broken, but I don't dare change
11827 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11831 #if defined (OBJ_COFF) && defined (TE_PE)
11832 /* For some reason, the PE format does not store a
11833 section address offset for a PC relative symbol. */
11834 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
11835 || S_IS_WEAK (fixP
->fx_addsy
))
11836 value
+= md_pcrel_from (fixP
);
11839 #if defined (OBJ_COFF) && defined (TE_PE)
11840 if (fixP
->fx_addsy
!= NULL
11841 && S_IS_WEAK (fixP
->fx_addsy
)
11842 /* PR 16858: Do not modify weak function references. */
11843 && ! fixP
->fx_pcrel
)
11845 #if !defined (TE_PEP)
11846 /* For x86 PE weak function symbols are neither PC-relative
11847 nor do they set S_IS_FUNCTION. So the only reliable way
11848 to detect them is to check the flags of their containing
11850 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
11851 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
11855 value
-= S_GET_VALUE (fixP
->fx_addsy
);
11859 /* Fix a few things - the dynamic linker expects certain values here,
11860 and we must not disappoint it. */
11861 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11862 if (IS_ELF
&& fixP
->fx_addsy
)
11863 switch (fixP
->fx_r_type
)
11865 case BFD_RELOC_386_PLT32
:
11866 case BFD_RELOC_X86_64_PLT32
:
11867 /* Make the jump instruction point to the address of the operand.
11868 At runtime we merely add the offset to the actual PLT entry.
11869 NB: Subtract the offset size only for jump instructions. */
11870 if (fixP
->fx_pcrel
)
11874 case BFD_RELOC_386_TLS_GD
:
11875 case BFD_RELOC_386_TLS_LDM
:
11876 case BFD_RELOC_386_TLS_IE_32
:
11877 case BFD_RELOC_386_TLS_IE
:
11878 case BFD_RELOC_386_TLS_GOTIE
:
11879 case BFD_RELOC_386_TLS_GOTDESC
:
11880 case BFD_RELOC_X86_64_TLSGD
:
11881 case BFD_RELOC_X86_64_TLSLD
:
11882 case BFD_RELOC_X86_64_GOTTPOFF
:
11883 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11884 value
= 0; /* Fully resolved at runtime. No addend. */
11886 case BFD_RELOC_386_TLS_LE
:
11887 case BFD_RELOC_386_TLS_LDO_32
:
11888 case BFD_RELOC_386_TLS_LE_32
:
11889 case BFD_RELOC_X86_64_DTPOFF32
:
11890 case BFD_RELOC_X86_64_DTPOFF64
:
11891 case BFD_RELOC_X86_64_TPOFF32
:
11892 case BFD_RELOC_X86_64_TPOFF64
:
11893 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11896 case BFD_RELOC_386_TLS_DESC_CALL
:
11897 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11898 value
= 0; /* Fully resolved at runtime. No addend. */
11899 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11903 case BFD_RELOC_VTABLE_INHERIT
:
11904 case BFD_RELOC_VTABLE_ENTRY
:
11911 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
11913 #endif /* !defined (TE_Mach) */
11915 /* Are we finished with this relocation now? */
11916 if (fixP
->fx_addsy
== NULL
)
11918 #if defined (OBJ_COFF) && defined (TE_PE)
11919 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
11922 /* Remember value for tc_gen_reloc. */
11923 fixP
->fx_addnumber
= value
;
11924 /* Clear out the frag for now. */
11928 else if (use_rela_relocations
)
11930 fixP
->fx_no_overflow
= 1;
11931 /* Remember value for tc_gen_reloc. */
11932 fixP
->fx_addnumber
= value
;
11936 md_number_to_chars (p
, value
, fixP
->fx_size
);
11940 md_atof (int type
, char *litP
, int *sizeP
)
11942 /* This outputs the LITTLENUMs in REVERSE order;
11943 in accord with the bigendian 386. */
11944 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
11947 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
11950 output_invalid (int c
)
11953 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
11956 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
11957 "(0x%x)", (unsigned char) c
);
11958 return output_invalid_buf
;
11961 /* REG_STRING starts *before* REGISTER_PREFIX. */
11963 static const reg_entry
*
11964 parse_real_register (char *reg_string
, char **end_op
)
11966 char *s
= reg_string
;
11968 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
11969 const reg_entry
*r
;
11971 /* Skip possible REGISTER_PREFIX and possible whitespace. */
11972 if (*s
== REGISTER_PREFIX
)
11975 if (is_space_char (*s
))
11978 p
= reg_name_given
;
11979 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
11981 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
11982 return (const reg_entry
*) NULL
;
11986 /* For naked regs, make sure that we are not dealing with an identifier.
11987 This prevents confusing an identifier like `eax_var' with register
11989 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
11990 return (const reg_entry
*) NULL
;
11994 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
11996 /* Handle floating point regs, allowing spaces in the (i) part. */
11997 if (r
== i386_regtab
/* %st is first entry of table */)
11999 if (!cpu_arch_flags
.bitfield
.cpu8087
12000 && !cpu_arch_flags
.bitfield
.cpu287
12001 && !cpu_arch_flags
.bitfield
.cpu387
)
12002 return (const reg_entry
*) NULL
;
12004 if (is_space_char (*s
))
12009 if (is_space_char (*s
))
12011 if (*s
>= '0' && *s
<= '7')
12013 int fpr
= *s
- '0';
12015 if (is_space_char (*s
))
12020 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
12025 /* We have "%st(" then garbage. */
12026 return (const reg_entry
*) NULL
;
12030 if (r
== NULL
|| allow_pseudo_reg
)
12033 if (operand_type_all_zero (&r
->reg_type
))
12034 return (const reg_entry
*) NULL
;
12036 if ((r
->reg_type
.bitfield
.dword
12037 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12038 || r
->reg_type
.bitfield
.class == RegCR
12039 || r
->reg_type
.bitfield
.class == RegDR
12040 || r
->reg_type
.bitfield
.class == RegTR
)
12041 && !cpu_arch_flags
.bitfield
.cpui386
)
12042 return (const reg_entry
*) NULL
;
12044 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12045 return (const reg_entry
*) NULL
;
12047 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12049 if (r
->reg_type
.bitfield
.zmmword
12050 || r
->reg_type
.bitfield
.class == RegMask
)
12051 return (const reg_entry
*) NULL
;
12053 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12055 if (r
->reg_type
.bitfield
.ymmword
)
12056 return (const reg_entry
*) NULL
;
12058 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12059 return (const reg_entry
*) NULL
;
12063 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12064 return (const reg_entry
*) NULL
;
12066 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12067 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12068 return (const reg_entry
*) NULL
;
12070 /* Upper 16 vector registers are only available with VREX in 64bit
12071 mode, and require EVEX encoding. */
12072 if (r
->reg_flags
& RegVRex
)
12074 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12075 || flag_code
!= CODE_64BIT
)
12076 return (const reg_entry
*) NULL
;
12078 i
.vec_encoding
= vex_encoding_evex
;
12081 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12082 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12083 && flag_code
!= CODE_64BIT
)
12084 return (const reg_entry
*) NULL
;
12086 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12088 return (const reg_entry
*) NULL
;
12093 /* REG_STRING starts *before* REGISTER_PREFIX. */
12095 static const reg_entry
*
12096 parse_register (char *reg_string
, char **end_op
)
12098 const reg_entry
*r
;
12100 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12101 r
= parse_real_register (reg_string
, end_op
);
12106 char *save
= input_line_pointer
;
12110 input_line_pointer
= reg_string
;
12111 c
= get_symbol_name (®_string
);
12112 symbolP
= symbol_find (reg_string
);
12113 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12115 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12117 know (e
->X_op
== O_register
);
12118 know (e
->X_add_number
>= 0
12119 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12120 r
= i386_regtab
+ e
->X_add_number
;
12121 if ((r
->reg_flags
& RegVRex
))
12122 i
.vec_encoding
= vex_encoding_evex
;
12123 *end_op
= input_line_pointer
;
12125 *input_line_pointer
= c
;
12126 input_line_pointer
= save
;
12132 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12134 const reg_entry
*r
;
12135 char *end
= input_line_pointer
;
12138 r
= parse_register (name
, &input_line_pointer
);
12139 if (r
&& end
<= input_line_pointer
)
12141 *nextcharP
= *input_line_pointer
;
12142 *input_line_pointer
= 0;
12143 e
->X_op
= O_register
;
12144 e
->X_add_number
= r
- i386_regtab
;
12147 input_line_pointer
= end
;
12149 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12153 md_operand (expressionS
*e
)
12156 const reg_entry
*r
;
12158 switch (*input_line_pointer
)
12160 case REGISTER_PREFIX
:
12161 r
= parse_real_register (input_line_pointer
, &end
);
12164 e
->X_op
= O_register
;
12165 e
->X_add_number
= r
- i386_regtab
;
12166 input_line_pointer
= end
;
12171 gas_assert (intel_syntax
);
12172 end
= input_line_pointer
++;
12174 if (*input_line_pointer
== ']')
12176 ++input_line_pointer
;
12177 e
->X_op_symbol
= make_expr_symbol (e
);
12178 e
->X_add_symbol
= NULL
;
12179 e
->X_add_number
= 0;
12184 e
->X_op
= O_absent
;
12185 input_line_pointer
= end
;
12192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12193 const char *md_shortopts
= "kVQ:sqnO::";
12195 const char *md_shortopts
= "qnO::";
12198 #define OPTION_32 (OPTION_MD_BASE + 0)
12199 #define OPTION_64 (OPTION_MD_BASE + 1)
12200 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12201 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12202 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12203 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12204 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12205 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12206 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12207 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12208 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12209 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12210 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12211 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12212 #define OPTION_X32 (OPTION_MD_BASE + 14)
12213 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12214 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12215 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12216 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12217 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12218 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12219 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12220 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12221 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12222 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12223 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12224 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12225 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12226 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12227 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12228 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12230 struct option md_longopts
[] =
12232 {"32", no_argument
, NULL
, OPTION_32
},
12233 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12234 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12235 {"64", no_argument
, NULL
, OPTION_64
},
12237 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12238 {"x32", no_argument
, NULL
, OPTION_X32
},
12239 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12240 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12242 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12243 {"march", required_argument
, NULL
, OPTION_MARCH
},
12244 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12245 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12246 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12247 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12248 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12249 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12250 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12251 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12252 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12253 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12254 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12255 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12256 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12257 # if defined (TE_PE) || defined (TE_PEP)
12258 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12260 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12261 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12262 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12263 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12264 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12265 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12266 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12267 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12268 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12269 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12270 {NULL
, no_argument
, NULL
, 0}
12272 size_t md_longopts_size
= sizeof (md_longopts
);
12275 md_parse_option (int c
, const char *arg
)
12278 char *arch
, *next
, *saved
, *type
;
12283 optimize_align_code
= 0;
12287 quiet_warnings
= 1;
12290 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12291 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12292 should be emitted or not. FIXME: Not implemented. */
12294 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12298 /* -V: SVR4 argument to print version ID. */
12300 print_version_id ();
12303 /* -k: Ignore for FreeBSD compatibility. */
12308 /* -s: On i386 Solaris, this tells the native assembler to use
12309 .stab instead of .stab.excl. We always use .stab anyhow. */
12312 case OPTION_MSHARED
:
12316 case OPTION_X86_USED_NOTE
:
12317 if (strcasecmp (arg
, "yes") == 0)
12319 else if (strcasecmp (arg
, "no") == 0)
12322 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12327 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12328 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12331 const char **list
, **l
;
12333 list
= bfd_target_list ();
12334 for (l
= list
; *l
!= NULL
; l
++)
12335 if (CONST_STRNEQ (*l
, "elf64-x86-64")
12336 || strcmp (*l
, "coff-x86-64") == 0
12337 || strcmp (*l
, "pe-x86-64") == 0
12338 || strcmp (*l
, "pei-x86-64") == 0
12339 || strcmp (*l
, "mach-o-x86-64") == 0)
12341 default_arch
= "x86_64";
12345 as_fatal (_("no compiled in support for x86_64"));
12351 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12355 const char **list
, **l
;
12357 list
= bfd_target_list ();
12358 for (l
= list
; *l
!= NULL
; l
++)
12359 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
12361 default_arch
= "x86_64:32";
12365 as_fatal (_("no compiled in support for 32bit x86_64"));
12369 as_fatal (_("32bit x86_64 is only supported for ELF"));
12374 default_arch
= "i386";
12377 case OPTION_DIVIDE
:
12378 #ifdef SVR4_COMMENT_CHARS
12383 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
12385 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
12389 i386_comment_chars
= n
;
12395 saved
= xstrdup (arg
);
12397 /* Allow -march=+nosse. */
12403 as_fatal (_("invalid -march= option: `%s'"), arg
);
12404 next
= strchr (arch
, '+');
12407 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12409 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
12412 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12415 cpu_arch_name
= cpu_arch
[j
].name
;
12416 cpu_sub_arch_name
= NULL
;
12417 cpu_arch_flags
= cpu_arch
[j
].flags
;
12418 cpu_arch_isa
= cpu_arch
[j
].type
;
12419 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
12420 if (!cpu_arch_tune_set
)
12422 cpu_arch_tune
= cpu_arch_isa
;
12423 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12427 else if (*cpu_arch
[j
].name
== '.'
12428 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
12430 /* ISA extension. */
12431 i386_cpu_flags flags
;
12433 flags
= cpu_flags_or (cpu_arch_flags
,
12434 cpu_arch
[j
].flags
);
12436 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12438 if (cpu_sub_arch_name
)
12440 char *name
= cpu_sub_arch_name
;
12441 cpu_sub_arch_name
= concat (name
,
12443 (const char *) NULL
);
12447 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
12448 cpu_arch_flags
= flags
;
12449 cpu_arch_isa_flags
= flags
;
12453 = cpu_flags_or (cpu_arch_isa_flags
,
12454 cpu_arch
[j
].flags
);
12459 if (j
>= ARRAY_SIZE (cpu_arch
))
12461 /* Disable an ISA extension. */
12462 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12463 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
12465 i386_cpu_flags flags
;
12467 flags
= cpu_flags_and_not (cpu_arch_flags
,
12468 cpu_noarch
[j
].flags
);
12469 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12471 if (cpu_sub_arch_name
)
12473 char *name
= cpu_sub_arch_name
;
12474 cpu_sub_arch_name
= concat (arch
,
12475 (const char *) NULL
);
12479 cpu_sub_arch_name
= xstrdup (arch
);
12480 cpu_arch_flags
= flags
;
12481 cpu_arch_isa_flags
= flags
;
12486 if (j
>= ARRAY_SIZE (cpu_noarch
))
12487 j
= ARRAY_SIZE (cpu_arch
);
12490 if (j
>= ARRAY_SIZE (cpu_arch
))
12491 as_fatal (_("invalid -march= option: `%s'"), arg
);
12495 while (next
!= NULL
);
12501 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12502 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12504 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
12506 cpu_arch_tune_set
= 1;
12507 cpu_arch_tune
= cpu_arch
[j
].type
;
12508 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
12512 if (j
>= ARRAY_SIZE (cpu_arch
))
12513 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12516 case OPTION_MMNEMONIC
:
12517 if (strcasecmp (arg
, "att") == 0)
12518 intel_mnemonic
= 0;
12519 else if (strcasecmp (arg
, "intel") == 0)
12520 intel_mnemonic
= 1;
12522 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
12525 case OPTION_MSYNTAX
:
12526 if (strcasecmp (arg
, "att") == 0)
12528 else if (strcasecmp (arg
, "intel") == 0)
12531 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
12534 case OPTION_MINDEX_REG
:
12535 allow_index_reg
= 1;
12538 case OPTION_MNAKED_REG
:
12539 allow_naked_reg
= 1;
12542 case OPTION_MSSE2AVX
:
12546 case OPTION_MSSE_CHECK
:
12547 if (strcasecmp (arg
, "error") == 0)
12548 sse_check
= check_error
;
12549 else if (strcasecmp (arg
, "warning") == 0)
12550 sse_check
= check_warning
;
12551 else if (strcasecmp (arg
, "none") == 0)
12552 sse_check
= check_none
;
12554 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
12557 case OPTION_MOPERAND_CHECK
:
12558 if (strcasecmp (arg
, "error") == 0)
12559 operand_check
= check_error
;
12560 else if (strcasecmp (arg
, "warning") == 0)
12561 operand_check
= check_warning
;
12562 else if (strcasecmp (arg
, "none") == 0)
12563 operand_check
= check_none
;
12565 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
12568 case OPTION_MAVXSCALAR
:
12569 if (strcasecmp (arg
, "128") == 0)
12570 avxscalar
= vex128
;
12571 else if (strcasecmp (arg
, "256") == 0)
12572 avxscalar
= vex256
;
12574 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
12577 case OPTION_MVEXWIG
:
12578 if (strcmp (arg
, "0") == 0)
12580 else if (strcmp (arg
, "1") == 0)
12583 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
12586 case OPTION_MADD_BND_PREFIX
:
12587 add_bnd_prefix
= 1;
12590 case OPTION_MEVEXLIG
:
12591 if (strcmp (arg
, "128") == 0)
12592 evexlig
= evexl128
;
12593 else if (strcmp (arg
, "256") == 0)
12594 evexlig
= evexl256
;
12595 else if (strcmp (arg
, "512") == 0)
12596 evexlig
= evexl512
;
12598 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
12601 case OPTION_MEVEXRCIG
:
12602 if (strcmp (arg
, "rne") == 0)
12604 else if (strcmp (arg
, "rd") == 0)
12606 else if (strcmp (arg
, "ru") == 0)
12608 else if (strcmp (arg
, "rz") == 0)
12611 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
12614 case OPTION_MEVEXWIG
:
12615 if (strcmp (arg
, "0") == 0)
12617 else if (strcmp (arg
, "1") == 0)
12620 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
12623 # if defined (TE_PE) || defined (TE_PEP)
12624 case OPTION_MBIG_OBJ
:
12629 case OPTION_MOMIT_LOCK_PREFIX
:
12630 if (strcasecmp (arg
, "yes") == 0)
12631 omit_lock_prefix
= 1;
12632 else if (strcasecmp (arg
, "no") == 0)
12633 omit_lock_prefix
= 0;
12635 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
12638 case OPTION_MFENCE_AS_LOCK_ADD
:
12639 if (strcasecmp (arg
, "yes") == 0)
12641 else if (strcasecmp (arg
, "no") == 0)
12644 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
12647 case OPTION_MRELAX_RELOCATIONS
:
12648 if (strcasecmp (arg
, "yes") == 0)
12649 generate_relax_relocations
= 1;
12650 else if (strcasecmp (arg
, "no") == 0)
12651 generate_relax_relocations
= 0;
12653 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
12656 case OPTION_MALIGN_BRANCH_BOUNDARY
:
12659 long int align
= strtoul (arg
, &end
, 0);
12664 align_branch_power
= 0;
12667 else if (align
>= 16)
12670 for (align_power
= 0;
12672 align
>>= 1, align_power
++)
12674 /* Limit alignment power to 31. */
12675 if (align
== 1 && align_power
< 32)
12677 align_branch_power
= align_power
;
12682 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
12686 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
12689 int align
= strtoul (arg
, &end
, 0);
12690 /* Some processors only support 5 prefixes. */
12691 if (*end
== '\0' && align
>= 0 && align
< 6)
12693 align_branch_prefix_size
= align
;
12696 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
12701 case OPTION_MALIGN_BRANCH
:
12703 saved
= xstrdup (arg
);
12707 next
= strchr (type
, '+');
12710 if (strcasecmp (type
, "jcc") == 0)
12711 align_branch
|= align_branch_jcc_bit
;
12712 else if (strcasecmp (type
, "fused") == 0)
12713 align_branch
|= align_branch_fused_bit
;
12714 else if (strcasecmp (type
, "jmp") == 0)
12715 align_branch
|= align_branch_jmp_bit
;
12716 else if (strcasecmp (type
, "call") == 0)
12717 align_branch
|= align_branch_call_bit
;
12718 else if (strcasecmp (type
, "ret") == 0)
12719 align_branch
|= align_branch_ret_bit
;
12720 else if (strcasecmp (type
, "indirect") == 0)
12721 align_branch
|= align_branch_indirect_bit
;
12723 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
12726 while (next
!= NULL
);
12730 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
12731 align_branch_power
= 5;
12732 align_branch_prefix_size
= 5;
12733 align_branch
= (align_branch_jcc_bit
12734 | align_branch_fused_bit
12735 | align_branch_jmp_bit
);
12738 case OPTION_MAMD64
:
12742 case OPTION_MINTEL64
:
12750 /* Turn off -Os. */
12751 optimize_for_space
= 0;
12753 else if (*arg
== 's')
12755 optimize_for_space
= 1;
12756 /* Turn on all encoding optimizations. */
12757 optimize
= INT_MAX
;
12761 optimize
= atoi (arg
);
12762 /* Turn off -Os. */
12763 optimize_for_space
= 0;
12773 #define MESSAGE_TEMPLATE \
12777 output_message (FILE *stream
, char *p
, char *message
, char *start
,
12778 int *left_p
, const char *name
, int len
)
12780 int size
= sizeof (MESSAGE_TEMPLATE
);
12781 int left
= *left_p
;
12783 /* Reserve 2 spaces for ", " or ",\0" */
12786 /* Check if there is any room. */
12794 p
= mempcpy (p
, name
, len
);
12798 /* Output the current message now and start a new one. */
12801 fprintf (stream
, "%s\n", message
);
12803 left
= size
- (start
- message
) - len
- 2;
12805 gas_assert (left
>= 0);
12807 p
= mempcpy (p
, name
, len
);
12815 show_arch (FILE *stream
, int ext
, int check
)
12817 static char message
[] = MESSAGE_TEMPLATE
;
12818 char *start
= message
+ 27;
12820 int size
= sizeof (MESSAGE_TEMPLATE
);
12827 left
= size
- (start
- message
);
12828 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12830 /* Should it be skipped? */
12831 if (cpu_arch
[j
].skip
)
12834 name
= cpu_arch
[j
].name
;
12835 len
= cpu_arch
[j
].len
;
12838 /* It is an extension. Skip if we aren't asked to show it. */
12849 /* It is an processor. Skip if we show only extension. */
12852 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12854 /* It is an impossible processor - skip. */
12858 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
12861 /* Display disabled extensions. */
12863 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12865 name
= cpu_noarch
[j
].name
;
12866 len
= cpu_noarch
[j
].len
;
12867 p
= output_message (stream
, p
, message
, start
, &left
, name
,
12872 fprintf (stream
, "%s\n", message
);
12876 md_show_usage (FILE *stream
)
12878 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12879 fprintf (stream
, _("\
12880 -Qy, -Qn ignored\n\
12881 -V print assembler version number\n\
12884 fprintf (stream
, _("\
12885 -n Do not optimize code alignment\n\
12886 -q quieten some warnings\n"));
12887 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12888 fprintf (stream
, _("\
12891 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12892 || defined (TE_PE) || defined (TE_PEP))
12893 fprintf (stream
, _("\
12894 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
12896 #ifdef SVR4_COMMENT_CHARS
12897 fprintf (stream
, _("\
12898 --divide do not treat `/' as a comment character\n"));
12900 fprintf (stream
, _("\
12901 --divide ignored\n"));
12903 fprintf (stream
, _("\
12904 -march=CPU[,+EXTENSION...]\n\
12905 generate code for CPU and EXTENSION, CPU is one of:\n"));
12906 show_arch (stream
, 0, 1);
12907 fprintf (stream
, _("\
12908 EXTENSION is combination of:\n"));
12909 show_arch (stream
, 1, 0);
12910 fprintf (stream
, _("\
12911 -mtune=CPU optimize for CPU, CPU is one of:\n"));
12912 show_arch (stream
, 0, 0);
12913 fprintf (stream
, _("\
12914 -msse2avx encode SSE instructions with VEX prefix\n"));
12915 fprintf (stream
, _("\
12916 -msse-check=[none|error|warning] (default: warning)\n\
12917 check SSE instructions\n"));
12918 fprintf (stream
, _("\
12919 -moperand-check=[none|error|warning] (default: warning)\n\
12920 check operand combinations for validity\n"));
12921 fprintf (stream
, _("\
12922 -mavxscalar=[128|256] (default: 128)\n\
12923 encode scalar AVX instructions with specific vector\n\
12925 fprintf (stream
, _("\
12926 -mvexwig=[0|1] (default: 0)\n\
12927 encode VEX instructions with specific VEX.W value\n\
12928 for VEX.W bit ignored instructions\n"));
12929 fprintf (stream
, _("\
12930 -mevexlig=[128|256|512] (default: 128)\n\
12931 encode scalar EVEX instructions with specific vector\n\
12933 fprintf (stream
, _("\
12934 -mevexwig=[0|1] (default: 0)\n\
12935 encode EVEX instructions with specific EVEX.W value\n\
12936 for EVEX.W bit ignored instructions\n"));
12937 fprintf (stream
, _("\
12938 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
12939 encode EVEX instructions with specific EVEX.RC value\n\
12940 for SAE-only ignored instructions\n"));
12941 fprintf (stream
, _("\
12942 -mmnemonic=[att|intel] "));
12943 if (SYSV386_COMPAT
)
12944 fprintf (stream
, _("(default: att)\n"));
12946 fprintf (stream
, _("(default: intel)\n"));
12947 fprintf (stream
, _("\
12948 use AT&T/Intel mnemonic\n"));
12949 fprintf (stream
, _("\
12950 -msyntax=[att|intel] (default: att)\n\
12951 use AT&T/Intel syntax\n"));
12952 fprintf (stream
, _("\
12953 -mindex-reg support pseudo index registers\n"));
12954 fprintf (stream
, _("\
12955 -mnaked-reg don't require `%%' prefix for registers\n"));
12956 fprintf (stream
, _("\
12957 -madd-bnd-prefix add BND prefix for all valid branches\n"));
12958 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12959 fprintf (stream
, _("\
12960 -mshared disable branch optimization for shared code\n"));
12961 fprintf (stream
, _("\
12962 -mx86-used-note=[no|yes] "));
12963 if (DEFAULT_X86_USED_NOTE
)
12964 fprintf (stream
, _("(default: yes)\n"));
12966 fprintf (stream
, _("(default: no)\n"));
12967 fprintf (stream
, _("\
12968 generate x86 used ISA and feature properties\n"));
12970 #if defined (TE_PE) || defined (TE_PEP)
12971 fprintf (stream
, _("\
12972 -mbig-obj generate big object files\n"));
12974 fprintf (stream
, _("\
12975 -momit-lock-prefix=[no|yes] (default: no)\n\
12976 strip all lock prefixes\n"));
12977 fprintf (stream
, _("\
12978 -mfence-as-lock-add=[no|yes] (default: no)\n\
12979 encode lfence, mfence and sfence as\n\
12980 lock addl $0x0, (%%{re}sp)\n"));
12981 fprintf (stream
, _("\
12982 -mrelax-relocations=[no|yes] "));
12983 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
12984 fprintf (stream
, _("(default: yes)\n"));
12986 fprintf (stream
, _("(default: no)\n"));
12987 fprintf (stream
, _("\
12988 generate relax relocations\n"));
12989 fprintf (stream
, _("\
12990 -malign-branch-boundary=NUM (default: 0)\n\
12991 align branches within NUM byte boundary\n"));
12992 fprintf (stream
, _("\
12993 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
12994 TYPE is combination of jcc, fused, jmp, call, ret,\n\
12996 specify types of branches to align\n"));
12997 fprintf (stream
, _("\
12998 -malign-branch-prefix-size=NUM (default: 5)\n\
12999 align branches with NUM prefixes per instruction\n"));
13000 fprintf (stream
, _("\
13001 -mbranches-within-32B-boundaries\n\
13002 align branches within 32 byte boundary\n"));
13003 fprintf (stream
, _("\
13004 -mamd64 accept only AMD64 ISA [default]\n"));
13005 fprintf (stream
, _("\
13006 -mintel64 accept only Intel64 ISA\n"));
13009 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13010 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13011 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13013 /* Pick the target format to use. */
13016 i386_target_format (void)
13018 if (!strncmp (default_arch
, "x86_64", 6))
13020 update_code_flag (CODE_64BIT
, 1);
13021 if (default_arch
[6] == '\0')
13022 x86_elf_abi
= X86_64_ABI
;
13024 x86_elf_abi
= X86_64_X32_ABI
;
13026 else if (!strcmp (default_arch
, "i386"))
13027 update_code_flag (CODE_32BIT
, 1);
13028 else if (!strcmp (default_arch
, "iamcu"))
13030 update_code_flag (CODE_32BIT
, 1);
13031 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13033 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13034 cpu_arch_name
= "iamcu";
13035 cpu_sub_arch_name
= NULL
;
13036 cpu_arch_flags
= iamcu_flags
;
13037 cpu_arch_isa
= PROCESSOR_IAMCU
;
13038 cpu_arch_isa_flags
= iamcu_flags
;
13039 if (!cpu_arch_tune_set
)
13041 cpu_arch_tune
= cpu_arch_isa
;
13042 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13045 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13046 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13050 as_fatal (_("unknown architecture"));
13052 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13053 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13054 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13055 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13057 switch (OUTPUT_FLAVOR
)
13059 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13060 case bfd_target_aout_flavour
:
13061 return AOUT_TARGET_FORMAT
;
13063 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13064 # if defined (TE_PE) || defined (TE_PEP)
13065 case bfd_target_coff_flavour
:
13066 if (flag_code
== CODE_64BIT
)
13067 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13070 # elif defined (TE_GO32)
13071 case bfd_target_coff_flavour
:
13072 return "coff-go32";
13074 case bfd_target_coff_flavour
:
13075 return "coff-i386";
13078 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13079 case bfd_target_elf_flavour
:
13081 const char *format
;
13083 switch (x86_elf_abi
)
13086 format
= ELF_TARGET_FORMAT
;
13088 tls_get_addr
= "___tls_get_addr";
13092 use_rela_relocations
= 1;
13095 tls_get_addr
= "__tls_get_addr";
13097 format
= ELF_TARGET_FORMAT64
;
13099 case X86_64_X32_ABI
:
13100 use_rela_relocations
= 1;
13103 tls_get_addr
= "__tls_get_addr";
13105 disallow_64bit_reloc
= 1;
13106 format
= ELF_TARGET_FORMAT32
;
13109 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13111 if (x86_elf_abi
!= X86_64_ABI
)
13112 as_fatal (_("Intel L1OM is 64bit only"));
13113 return ELF_TARGET_L1OM_FORMAT
;
13115 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13117 if (x86_elf_abi
!= X86_64_ABI
)
13118 as_fatal (_("Intel K1OM is 64bit only"));
13119 return ELF_TARGET_K1OM_FORMAT
;
13121 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13123 if (x86_elf_abi
!= I386_ABI
)
13124 as_fatal (_("Intel MCU is 32bit only"));
13125 return ELF_TARGET_IAMCU_FORMAT
;
13131 #if defined (OBJ_MACH_O)
13132 case bfd_target_mach_o_flavour
:
13133 if (flag_code
== CODE_64BIT
)
13135 use_rela_relocations
= 1;
13137 return "mach-o-x86-64";
13140 return "mach-o-i386";
13148 #endif /* OBJ_MAYBE_ more than one */
13151 md_undefined_symbol (char *name
)
13153 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13154 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13155 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13156 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
13160 if (symbol_find (name
))
13161 as_bad (_("GOT already in symbol table"));
13162 GOT_symbol
= symbol_new (name
, undefined_section
,
13163 (valueT
) 0, &zero_address_frag
);
13170 /* Round up a section size to the appropriate boundary. */
13173 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
13175 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13176 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
13178 /* For a.out, force the section size to be aligned. If we don't do
13179 this, BFD will align it for us, but it will not write out the
13180 final bytes of the section. This may be a bug in BFD, but it is
13181 easier to fix it here since that is how the other a.out targets
13185 align
= bfd_section_alignment (segment
);
13186 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13193 /* On the i386, PC-relative offsets are relative to the start of the
13194 next instruction. That is, the address of the offset, plus its
13195 size, since the offset is always the last part of the insn. */
13198 md_pcrel_from (fixS
*fixP
)
13200 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13206 s_bss (int ignore ATTRIBUTE_UNUSED
)
13210 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13212 obj_elf_section_change_hook ();
13214 temp
= get_absolute_expression ();
13215 subseg_set (bss_section
, (subsegT
) temp
);
13216 demand_empty_rest_of_line ();
13221 /* Remember constant directive. */
13224 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13226 if (last_insn
.kind
!= last_insn_directive
13227 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13229 last_insn
.seg
= now_seg
;
13230 last_insn
.kind
= last_insn_directive
;
13231 last_insn
.name
= "constant directive";
13232 last_insn
.file
= as_where (&last_insn
.line
);
13237 i386_validate_fix (fixS
*fixp
)
13239 if (fixp
->fx_subsy
)
13241 if (fixp
->fx_subsy
== GOT_symbol
)
13243 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13247 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13248 if (fixp
->fx_tcbit2
)
13249 fixp
->fx_r_type
= (fixp
->fx_tcbit
13250 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13251 : BFD_RELOC_X86_64_GOTPCRELX
);
13254 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13259 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13261 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13263 fixp
->fx_subsy
= 0;
13266 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13267 else if (!object_64bit
)
13269 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13270 && fixp
->fx_tcbit2
)
13271 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
13277 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13280 bfd_reloc_code_real_type code
;
13282 switch (fixp
->fx_r_type
)
13284 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13285 case BFD_RELOC_SIZE32
:
13286 case BFD_RELOC_SIZE64
:
13287 if (S_IS_DEFINED (fixp
->fx_addsy
)
13288 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
13290 /* Resolve size relocation against local symbol to size of
13291 the symbol plus addend. */
13292 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
13293 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
13294 && !fits_in_unsigned_long (value
))
13295 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13296 _("symbol size computation overflow"));
13297 fixp
->fx_addsy
= NULL
;
13298 fixp
->fx_subsy
= NULL
;
13299 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
13303 /* Fall through. */
13305 case BFD_RELOC_X86_64_PLT32
:
13306 case BFD_RELOC_X86_64_GOT32
:
13307 case BFD_RELOC_X86_64_GOTPCREL
:
13308 case BFD_RELOC_X86_64_GOTPCRELX
:
13309 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13310 case BFD_RELOC_386_PLT32
:
13311 case BFD_RELOC_386_GOT32
:
13312 case BFD_RELOC_386_GOT32X
:
13313 case BFD_RELOC_386_GOTOFF
:
13314 case BFD_RELOC_386_GOTPC
:
13315 case BFD_RELOC_386_TLS_GD
:
13316 case BFD_RELOC_386_TLS_LDM
:
13317 case BFD_RELOC_386_TLS_LDO_32
:
13318 case BFD_RELOC_386_TLS_IE_32
:
13319 case BFD_RELOC_386_TLS_IE
:
13320 case BFD_RELOC_386_TLS_GOTIE
:
13321 case BFD_RELOC_386_TLS_LE_32
:
13322 case BFD_RELOC_386_TLS_LE
:
13323 case BFD_RELOC_386_TLS_GOTDESC
:
13324 case BFD_RELOC_386_TLS_DESC_CALL
:
13325 case BFD_RELOC_X86_64_TLSGD
:
13326 case BFD_RELOC_X86_64_TLSLD
:
13327 case BFD_RELOC_X86_64_DTPOFF32
:
13328 case BFD_RELOC_X86_64_DTPOFF64
:
13329 case BFD_RELOC_X86_64_GOTTPOFF
:
13330 case BFD_RELOC_X86_64_TPOFF32
:
13331 case BFD_RELOC_X86_64_TPOFF64
:
13332 case BFD_RELOC_X86_64_GOTOFF64
:
13333 case BFD_RELOC_X86_64_GOTPC32
:
13334 case BFD_RELOC_X86_64_GOT64
:
13335 case BFD_RELOC_X86_64_GOTPCREL64
:
13336 case BFD_RELOC_X86_64_GOTPC64
:
13337 case BFD_RELOC_X86_64_GOTPLT64
:
13338 case BFD_RELOC_X86_64_PLTOFF64
:
13339 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13340 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13341 case BFD_RELOC_RVA
:
13342 case BFD_RELOC_VTABLE_ENTRY
:
13343 case BFD_RELOC_VTABLE_INHERIT
:
13345 case BFD_RELOC_32_SECREL
:
13347 code
= fixp
->fx_r_type
;
13349 case BFD_RELOC_X86_64_32S
:
13350 if (!fixp
->fx_pcrel
)
13352 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
13353 code
= fixp
->fx_r_type
;
13356 /* Fall through. */
13358 if (fixp
->fx_pcrel
)
13360 switch (fixp
->fx_size
)
13363 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13364 _("can not do %d byte pc-relative relocation"),
13366 code
= BFD_RELOC_32_PCREL
;
13368 case 1: code
= BFD_RELOC_8_PCREL
; break;
13369 case 2: code
= BFD_RELOC_16_PCREL
; break;
13370 case 4: code
= BFD_RELOC_32_PCREL
; break;
13372 case 8: code
= BFD_RELOC_64_PCREL
; break;
13378 switch (fixp
->fx_size
)
13381 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13382 _("can not do %d byte relocation"),
13384 code
= BFD_RELOC_32
;
13386 case 1: code
= BFD_RELOC_8
; break;
13387 case 2: code
= BFD_RELOC_16
; break;
13388 case 4: code
= BFD_RELOC_32
; break;
13390 case 8: code
= BFD_RELOC_64
; break;
13397 if ((code
== BFD_RELOC_32
13398 || code
== BFD_RELOC_32_PCREL
13399 || code
== BFD_RELOC_X86_64_32S
)
13401 && fixp
->fx_addsy
== GOT_symbol
)
13404 code
= BFD_RELOC_386_GOTPC
;
13406 code
= BFD_RELOC_X86_64_GOTPC32
;
13408 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
13410 && fixp
->fx_addsy
== GOT_symbol
)
13412 code
= BFD_RELOC_X86_64_GOTPC64
;
13415 rel
= XNEW (arelent
);
13416 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
13417 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13419 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13421 if (!use_rela_relocations
)
13423 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
13424 vtable entry to be used in the relocation's section offset. */
13425 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13426 rel
->address
= fixp
->fx_offset
;
13427 #if defined (OBJ_COFF) && defined (TE_PE)
13428 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
13429 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
13434 /* Use the rela in 64bit mode. */
13437 if (disallow_64bit_reloc
)
13440 case BFD_RELOC_X86_64_DTPOFF64
:
13441 case BFD_RELOC_X86_64_TPOFF64
:
13442 case BFD_RELOC_64_PCREL
:
13443 case BFD_RELOC_X86_64_GOTOFF64
:
13444 case BFD_RELOC_X86_64_GOT64
:
13445 case BFD_RELOC_X86_64_GOTPCREL64
:
13446 case BFD_RELOC_X86_64_GOTPC64
:
13447 case BFD_RELOC_X86_64_GOTPLT64
:
13448 case BFD_RELOC_X86_64_PLTOFF64
:
13449 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13450 _("cannot represent relocation type %s in x32 mode"),
13451 bfd_get_reloc_code_name (code
));
13457 if (!fixp
->fx_pcrel
)
13458 rel
->addend
= fixp
->fx_offset
;
13462 case BFD_RELOC_X86_64_PLT32
:
13463 case BFD_RELOC_X86_64_GOT32
:
13464 case BFD_RELOC_X86_64_GOTPCREL
:
13465 case BFD_RELOC_X86_64_GOTPCRELX
:
13466 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13467 case BFD_RELOC_X86_64_TLSGD
:
13468 case BFD_RELOC_X86_64_TLSLD
:
13469 case BFD_RELOC_X86_64_GOTTPOFF
:
13470 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13471 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13472 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
13475 rel
->addend
= (section
->vma
13477 + fixp
->fx_addnumber
13478 + md_pcrel_from (fixp
));
13483 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13484 if (rel
->howto
== NULL
)
13486 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13487 _("cannot represent relocation type %s"),
13488 bfd_get_reloc_code_name (code
));
13489 /* Set howto to a garbage value so that we can keep going. */
13490 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
13491 gas_assert (rel
->howto
!= NULL
);
13497 #include "tc-i386-intel.c"
13500 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
13502 int saved_naked_reg
;
13503 char saved_register_dot
;
13505 saved_naked_reg
= allow_naked_reg
;
13506 allow_naked_reg
= 1;
13507 saved_register_dot
= register_chars
['.'];
13508 register_chars
['.'] = '.';
13509 allow_pseudo_reg
= 1;
13510 expression_and_evaluate (exp
);
13511 allow_pseudo_reg
= 0;
13512 register_chars
['.'] = saved_register_dot
;
13513 allow_naked_reg
= saved_naked_reg
;
13515 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
13517 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
13519 exp
->X_op
= O_constant
;
13520 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
13521 .dw2_regnum
[flag_code
>> 1];
13524 exp
->X_op
= O_illegal
;
13529 tc_x86_frame_initial_instructions (void)
13531 static unsigned int sp_regno
[2];
13533 if (!sp_regno
[flag_code
>> 1])
13535 char *saved_input
= input_line_pointer
;
13536 char sp
[][4] = {"esp", "rsp"};
13539 input_line_pointer
= sp
[flag_code
>> 1];
13540 tc_x86_parse_to_dw2regnum (&exp
);
13541 gas_assert (exp
.X_op
== O_constant
);
13542 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
13543 input_line_pointer
= saved_input
;
13546 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
13547 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
13551 x86_dwarf2_addr_size (void)
13553 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13554 if (x86_elf_abi
== X86_64_X32_ABI
)
13557 return bfd_arch_bits_per_address (stdoutput
) / 8;
13561 i386_elf_section_type (const char *str
, size_t len
)
13563 if (flag_code
== CODE_64BIT
13564 && len
== sizeof ("unwind") - 1
13565 && strncmp (str
, "unwind", 6) == 0)
13566 return SHT_X86_64_UNWIND
;
13573 i386_solaris_fix_up_eh_frame (segT sec
)
13575 if (flag_code
== CODE_64BIT
)
13576 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
13582 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
13586 exp
.X_op
= O_secrel
;
13587 exp
.X_add_symbol
= symbol
;
13588 exp
.X_add_number
= 0;
13589 emit_expr (&exp
, size
);
13593 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13594 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
13597 x86_64_section_letter (int letter
, const char **ptr_msg
)
13599 if (flag_code
== CODE_64BIT
)
13602 return SHF_X86_64_LARGE
;
13604 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
13607 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
13612 x86_64_section_word (char *str
, size_t len
)
13614 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
13615 return SHF_X86_64_LARGE
;
13621 handle_large_common (int small ATTRIBUTE_UNUSED
)
13623 if (flag_code
!= CODE_64BIT
)
13625 s_comm_internal (0, elf_common_parse
);
13626 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
13630 static segT lbss_section
;
13631 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
13632 asection
*saved_bss_section
= bss_section
;
13634 if (lbss_section
== NULL
)
13636 flagword applicable
;
13637 segT seg
= now_seg
;
13638 subsegT subseg
= now_subseg
;
13640 /* The .lbss section is for local .largecomm symbols. */
13641 lbss_section
= subseg_new (".lbss", 0);
13642 applicable
= bfd_applicable_section_flags (stdoutput
);
13643 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
13644 seg_info (lbss_section
)->bss
= 1;
13646 subseg_set (seg
, subseg
);
13649 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
13650 bss_section
= lbss_section
;
13652 s_comm_internal (0, elf_common_parse
);
13654 elf_com_section_ptr
= saved_com_section_ptr
;
13655 bss_section
= saved_bss_section
;
13658 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */