1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
139 /* Used to turn off indicated flags. */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 i386_cpu_flags flags
; /* cpu feature flags */
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
157 static void pe_directive_secrel (int);
159 static void signed_cons (int);
160 static char *output_invalid (int c
);
161 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
163 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS
*);
168 static int i386_intel_parse_name (const char *, expressionS
*);
169 static const reg_entry
*parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template
*match_template (void);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry
*build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS
*, offsetT
);
188 static void output_disp (fragS
*, offsetT
);
190 static void s_bss (int);
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
196 static const char *default_arch
= DEFAULT_ARCH
;
198 /* This struct describes rounding control and SAE in the instruction. */
212 static struct RC_Operation rc_op
;
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
219 const reg_entry
*mask
;
220 unsigned int zeroing
;
221 /* The operand where this operation is associated. */
225 static struct Mask_Operation mask_op
;
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
229 struct Broadcast_Operation
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
234 /* Index of broadcasted operand. */
238 static struct Broadcast_Operation broadcast_op
;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes
[4];
246 /* Destination or source register specifier. */
247 const reg_entry
*register_specifier
;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry
*regs
;
262 operand_size_mismatch
,
263 operand_type_mismatch
,
264 register_type_mismatch
,
265 number_of_operands_mismatch
,
266 invalid_instruction_suffix
,
269 unsupported_with_intel_mnemonic
,
272 invalid_vsib_address
,
273 invalid_vector_register_set
,
274 unsupported_vector_index_register
,
275 unsupported_broadcast
,
276 broadcast_not_on_src_operand
,
279 mask_not_on_destination
,
282 rc_sae_operand_not_last_imm
,
283 invalid_register_operand
,
289 /* TM holds the template for the insn were currently assembling. */
292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
296 /* OPERANDS gives the number of given operands. */
297 unsigned int operands
;
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
302 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
304 /* TYPES [i] is the type (see above #defines) which tells us how to
305 use OP[i] for the corresponding operand. */
306 i386_operand_type types
[MAX_OPERANDS
];
308 /* Displacement expression, immediate expression, or register for each
310 union i386_op op
[MAX_OPERANDS
];
312 /* Flags for operands. */
313 unsigned int flags
[MAX_OPERANDS
];
314 #define Operand_PCrel 1
316 /* Relocation type for operand */
317 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry
*base_reg
;
322 const reg_entry
*index_reg
;
323 unsigned int log2_scale_factor
;
325 /* SEG gives the seg_entries of this insn. They are zero unless
326 explicit segment overrides are given. */
327 const seg_entry
*seg
[2];
329 /* PREFIX holds all the given prefix opcodes (usually null).
330 PREFIXES is the number of prefix opcodes. */
331 unsigned int prefixes
;
332 unsigned char prefix
[MAX_PREFIXES
];
334 /* RM and SIB are the modrm byte and the sib byte where the
335 addressing modes of this insn are encoded. */
342 /* Masking attributes. */
343 struct Mask_Operation
*mask
;
345 /* Rounding control and SAE attributes. */
346 struct RC_Operation
*rounding
;
348 /* Broadcasting attributes. */
349 struct Broadcast_Operation
*broadcast
;
351 /* Compressed disp8*N attribute. */
352 unsigned int memshift
;
354 /* Swap operand in encoding. */
355 unsigned int swap_operand
;
357 /* Prefer 8bit or 32bit displacement in encoding. */
360 disp_encoding_default
= 0,
366 const char *rep_prefix
;
369 const char *hle_prefix
;
371 /* Have BND prefix. */
372 const char *bnd_prefix
;
374 /* Need VREX to support upper 16 registers. */
378 enum i386_error error
;
381 typedef struct _i386_insn i386_insn
;
383 /* Link RC type with corresponding string, that'll be looked for in
392 static const struct RC_name RC_NamesTable
[] =
394 { rne
, STRING_COMMA_LEN ("rn-sae") },
395 { rd
, STRING_COMMA_LEN ("rd-sae") },
396 { ru
, STRING_COMMA_LEN ("ru-sae") },
397 { rz
, STRING_COMMA_LEN ("rz-sae") },
398 { saeonly
, STRING_COMMA_LEN ("sae") },
401 /* List of chars besides those in app.c:symbol_chars that can start an
402 operand. Used to prevent the scrubber eating vital white-space. */
403 const char extra_symbol_chars
[] = "*%-([{"
412 #if (defined (TE_I386AIX) \
413 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
414 && !defined (TE_GNU) \
415 && !defined (TE_LINUX) \
416 && !defined (TE_NACL) \
417 && !defined (TE_NETWARE) \
418 && !defined (TE_FreeBSD) \
419 && !defined (TE_DragonFly) \
420 && !defined (TE_NetBSD)))
421 /* This array holds the chars that always start a comment. If the
422 pre-processor is disabled, these aren't very useful. The option
423 --divide will remove '/' from this list. */
424 const char *i386_comment_chars
= "#/";
425 #define SVR4_COMMENT_CHARS 1
426 #define PREFIX_SEPARATOR '\\'
429 const char *i386_comment_chars
= "#";
430 #define PREFIX_SEPARATOR '/'
433 /* This array holds the chars that only start a comment at the beginning of
434 a line. If the line seems to have the form '# 123 filename'
435 .line and .file directives will appear in the pre-processed output.
436 Note that input_file.c hand checks for '#' at the beginning of the
437 first line of the input file. This is because the compiler outputs
438 #NO_APP at the beginning of its output.
439 Also note that comments started like this one will always work if
440 '/' isn't otherwise defined. */
441 const char line_comment_chars
[] = "#/";
443 const char line_separator_chars
[] = ";";
445 /* Chars that can be used to separate mant from exp in floating point
447 const char EXP_CHARS
[] = "eE";
449 /* Chars that mean this number is a floating point constant
452 const char FLT_CHARS
[] = "fFdDxX";
454 /* Tables for lexical analysis. */
455 static char mnemonic_chars
[256];
456 static char register_chars
[256];
457 static char operand_chars
[256];
458 static char identifier_chars
[256];
459 static char digit_chars
[256];
461 /* Lexical macros. */
462 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
463 #define is_operand_char(x) (operand_chars[(unsigned char) x])
464 #define is_register_char(x) (register_chars[(unsigned char) x])
465 #define is_space_char(x) ((x) == ' ')
466 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
467 #define is_digit_char(x) (digit_chars[(unsigned char) x])
469 /* All non-digit non-letter characters that may occur in an operand. */
470 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
472 /* md_assemble() always leaves the strings it's passed unaltered. To
473 effect this we maintain a stack of saved characters that we've smashed
474 with '\0's (indicating end of strings for various sub-fields of the
475 assembler instruction). */
476 static char save_stack
[32];
477 static char *save_stack_p
;
478 #define END_STRING_AND_SAVE(s) \
479 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
480 #define RESTORE_END_STRING(s) \
481 do { *(s) = *--save_stack_p; } while (0)
483 /* The instruction we're assembling. */
486 /* Possible templates for current insn. */
487 static const templates
*current_templates
;
489 /* Per instruction expressionS buffers: max displacements & immediates. */
490 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
491 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
493 /* Current operand we are working on. */
494 static int this_operand
= -1;
496 /* We support four different modes. FLAG_CODE variable is used to distinguish
504 static enum flag_code flag_code
;
505 static unsigned int object_64bit
;
506 static unsigned int disallow_64bit_reloc
;
507 static int use_rela_relocations
= 0;
509 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
510 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
511 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
513 /* The ELF ABI to use. */
521 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
524 #if defined (TE_PE) || defined (TE_PEP)
525 /* Use big object file format. */
526 static int use_big_obj
= 0;
529 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
530 /* 1 if generating code for a shared library. */
531 static int shared
= 0;
534 /* 1 for intel syntax,
536 static int intel_syntax
= 0;
538 /* 1 for intel mnemonic,
539 0 if att mnemonic. */
540 static int intel_mnemonic
= !SYSV386_COMPAT
;
542 /* 1 if support old (<= 2.8.1) versions of gcc. */
543 static int old_gcc
= OLDGCC_COMPAT
;
545 /* 1 if pseudo registers are permitted. */
546 static int allow_pseudo_reg
= 0;
548 /* 1 if register prefix % not required. */
549 static int allow_naked_reg
= 0;
551 /* 1 if the assembler should add BND prefix for all control-tranferring
552 instructions supporting it, even if this prefix wasn't specified
554 static int add_bnd_prefix
= 0;
556 /* 1 if pseudo index register, eiz/riz, is allowed . */
557 static int allow_index_reg
= 0;
559 /* 1 if the assembler should ignore LOCK prefix, even if it was
560 specified explicitly. */
561 static int omit_lock_prefix
= 0;
563 /* 1 if the assembler should encode lfence, mfence, and sfence as
564 "lock addl $0, (%{re}sp)". */
565 static int avoid_fence
= 0;
567 /* 1 if the assembler should generate relax relocations. */
569 static int generate_relax_relocations
570 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
572 static enum check_kind
578 sse_check
, operand_check
= check_warning
;
580 /* Register prefix used for error message. */
581 static const char *register_prefix
= "%";
583 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
584 leave, push, and pop instructions so that gcc has the same stack
585 frame as in 32 bit mode. */
586 static char stackop_size
= '\0';
588 /* Non-zero to optimize code alignment. */
589 int optimize_align_code
= 1;
591 /* Non-zero to quieten some warnings. */
592 static int quiet_warnings
= 0;
595 static const char *cpu_arch_name
= NULL
;
596 static char *cpu_sub_arch_name
= NULL
;
598 /* CPU feature flags. */
599 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
601 /* If we have selected a cpu we are generating instructions for. */
602 static int cpu_arch_tune_set
= 0;
604 /* Cpu we are generating instructions for. */
605 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
607 /* CPU feature flags of cpu we are generating instructions for. */
608 static i386_cpu_flags cpu_arch_tune_flags
;
610 /* CPU instruction set architecture used. */
611 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
613 /* CPU feature flags of instruction set architecture used. */
614 i386_cpu_flags cpu_arch_isa_flags
;
616 /* If set, conditional jumps are not automatically promoted to handle
617 larger than a byte offset. */
618 static unsigned int no_cond_jump_promotion
= 0;
620 /* Encode SSE instructions with VEX prefix. */
621 static unsigned int sse2avx
;
623 /* Encode scalar AVX instructions with specific vector length. */
630 /* Encode scalar EVEX LIG instructions with specific vector length. */
638 /* Encode EVEX WIG instructions with specific evex.w. */
645 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
646 static enum rc_type evexrcig
= rne
;
648 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
649 static symbolS
*GOT_symbol
;
651 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
652 unsigned int x86_dwarf2_return_column
;
654 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
655 int x86_cie_data_alignment
;
657 /* Interface to relax_segment.
658 There are 3 major relax states for 386 jump insns because the
659 different types of jumps add different sizes to frags when we're
660 figuring out what sort of jump to choose to reach a given label. */
663 #define UNCOND_JUMP 0
665 #define COND_JUMP86 2
670 #define SMALL16 (SMALL | CODE16)
672 #define BIG16 (BIG | CODE16)
676 #define INLINE __inline__
682 #define ENCODE_RELAX_STATE(type, size) \
683 ((relax_substateT) (((type) << 2) | (size)))
684 #define TYPE_FROM_RELAX_STATE(s) \
686 #define DISP_SIZE_FROM_RELAX_STATE(s) \
687 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
689 /* This table is used by relax_frag to promote short jumps to long
690 ones where necessary. SMALL (short) jumps may be promoted to BIG
691 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
692 don't allow a short jump in a 32 bit code segment to be promoted to
693 a 16 bit offset jump because it's slower (requires data size
694 prefix), and doesn't work, unless the destination is in the bottom
695 64k of the code segment (The top 16 bits of eip are zeroed). */
697 const relax_typeS md_relax_table
[] =
700 1) most positive reach of this state,
701 2) most negative reach of this state,
702 3) how many bytes this mode will have in the variable part of the frag
703 4) which index into the table to try if we can't fit into this one. */
705 /* UNCOND_JUMP states. */
706 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
707 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
708 /* dword jmp adds 4 bytes to frag:
709 0 extra opcode bytes, 4 displacement bytes. */
711 /* word jmp adds 2 byte2 to frag:
712 0 extra opcode bytes, 2 displacement bytes. */
715 /* COND_JUMP states. */
716 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
717 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
718 /* dword conditionals adds 5 bytes to frag:
719 1 extra opcode byte, 4 displacement bytes. */
721 /* word conditionals add 3 bytes to frag:
722 1 extra opcode byte, 2 displacement bytes. */
725 /* COND_JUMP86 states. */
726 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
727 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
728 /* dword conditionals adds 5 bytes to frag:
729 1 extra opcode byte, 4 displacement bytes. */
731 /* word conditionals add 4 bytes to frag:
732 1 displacement byte and a 3 byte long branch insn. */
736 static const arch_entry cpu_arch
[] =
738 /* Do not replace the first two entries - i386_target_format()
739 relies on them being there in this order. */
740 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
741 CPU_GENERIC32_FLAGS
, 0 },
742 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
743 CPU_GENERIC64_FLAGS
, 0 },
744 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
746 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
748 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
750 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
752 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
754 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
756 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
758 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
760 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
761 CPU_PENTIUMPRO_FLAGS
, 0 },
762 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
764 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
766 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
768 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
770 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
771 CPU_NOCONA_FLAGS
, 0 },
772 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
774 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
776 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
777 CPU_CORE2_FLAGS
, 1 },
778 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
779 CPU_CORE2_FLAGS
, 0 },
780 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
781 CPU_COREI7_FLAGS
, 0 },
782 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
784 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
786 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
787 CPU_IAMCU_FLAGS
, 0 },
788 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
790 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
792 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
793 CPU_ATHLON_FLAGS
, 0 },
794 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
796 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
798 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
800 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
801 CPU_AMDFAM10_FLAGS
, 0 },
802 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
803 CPU_BDVER1_FLAGS
, 0 },
804 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
805 CPU_BDVER2_FLAGS
, 0 },
806 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
807 CPU_BDVER3_FLAGS
, 0 },
808 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
809 CPU_BDVER4_FLAGS
, 0 },
810 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
811 CPU_ZNVER1_FLAGS
, 0 },
812 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
813 CPU_BTVER1_FLAGS
, 0 },
814 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
815 CPU_BTVER2_FLAGS
, 0 },
816 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
818 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
820 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
822 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
824 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
826 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
828 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
830 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
831 CPU_SSSE3_FLAGS
, 0 },
832 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
833 CPU_SSE4_1_FLAGS
, 0 },
834 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
835 CPU_SSE4_2_FLAGS
, 0 },
836 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
837 CPU_SSE4_2_FLAGS
, 0 },
838 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
840 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
842 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
843 CPU_AVX512F_FLAGS
, 0 },
844 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
845 CPU_AVX512CD_FLAGS
, 0 },
846 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
847 CPU_AVX512ER_FLAGS
, 0 },
848 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
849 CPU_AVX512PF_FLAGS
, 0 },
850 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
851 CPU_AVX512DQ_FLAGS
, 0 },
852 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
853 CPU_AVX512BW_FLAGS
, 0 },
854 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
855 CPU_AVX512VL_FLAGS
, 0 },
856 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
858 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
859 CPU_VMFUNC_FLAGS
, 0 },
860 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
862 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
863 CPU_XSAVE_FLAGS
, 0 },
864 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
865 CPU_XSAVEOPT_FLAGS
, 0 },
866 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
867 CPU_XSAVEC_FLAGS
, 0 },
868 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
869 CPU_XSAVES_FLAGS
, 0 },
870 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
872 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
873 CPU_PCLMUL_FLAGS
, 0 },
874 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
875 CPU_PCLMUL_FLAGS
, 1 },
876 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
877 CPU_FSGSBASE_FLAGS
, 0 },
878 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
879 CPU_RDRND_FLAGS
, 0 },
880 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
882 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
884 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
886 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
888 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
890 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
892 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
893 CPU_MOVBE_FLAGS
, 0 },
894 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
896 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
898 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
899 CPU_LZCNT_FLAGS
, 0 },
900 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
902 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
904 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
905 CPU_INVPCID_FLAGS
, 0 },
906 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
907 CPU_CLFLUSH_FLAGS
, 0 },
908 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
910 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
911 CPU_SYSCALL_FLAGS
, 0 },
912 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
913 CPU_RDTSCP_FLAGS
, 0 },
914 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
915 CPU_3DNOW_FLAGS
, 0 },
916 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
917 CPU_3DNOWA_FLAGS
, 0 },
918 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
919 CPU_PADLOCK_FLAGS
, 0 },
920 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
922 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
924 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
925 CPU_SSE4A_FLAGS
, 0 },
926 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
928 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
930 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
932 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
934 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
935 CPU_RDSEED_FLAGS
, 0 },
936 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
937 CPU_PRFCHW_FLAGS
, 0 },
938 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
940 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
942 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
944 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
945 CPU_CLFLUSHOPT_FLAGS
, 0 },
946 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
947 CPU_PREFETCHWT1_FLAGS
, 0 },
948 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
950 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
952 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
953 CPU_PCOMMIT_FLAGS
, 0 },
954 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
955 CPU_AVX512IFMA_FLAGS
, 0 },
956 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
957 CPU_AVX512VBMI_FLAGS
, 0 },
958 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
959 CPU_CLZERO_FLAGS
, 0 },
960 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
961 CPU_MWAITX_FLAGS
, 0 },
962 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
963 CPU_OSPKE_FLAGS
, 0 },
964 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
965 CPU_RDPID_FLAGS
, 0 },
968 static const noarch_entry cpu_noarch
[] =
970 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
971 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
972 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
973 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
977 /* Like s_lcomm_internal in gas/read.c but the alignment string
978 is allowed to be optional. */
981 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
988 && *input_line_pointer
== ',')
990 align
= parse_align (needs_align
- 1);
992 if (align
== (addressT
) -1)
1007 bss_alloc (symbolP
, size
, align
);
1012 pe_lcomm (int needs_align
)
1014 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1018 const pseudo_typeS md_pseudo_table
[] =
1020 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1021 {"align", s_align_bytes
, 0},
1023 {"align", s_align_ptwo
, 0},
1025 {"arch", set_cpu_arch
, 0},
1029 {"lcomm", pe_lcomm
, 1},
1031 {"ffloat", float_cons
, 'f'},
1032 {"dfloat", float_cons
, 'd'},
1033 {"tfloat", float_cons
, 'x'},
1035 {"slong", signed_cons
, 4},
1036 {"noopt", s_ignore
, 0},
1037 {"optim", s_ignore
, 0},
1038 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1039 {"code16", set_code_flag
, CODE_16BIT
},
1040 {"code32", set_code_flag
, CODE_32BIT
},
1041 {"code64", set_code_flag
, CODE_64BIT
},
1042 {"intel_syntax", set_intel_syntax
, 1},
1043 {"att_syntax", set_intel_syntax
, 0},
1044 {"intel_mnemonic", set_intel_mnemonic
, 1},
1045 {"att_mnemonic", set_intel_mnemonic
, 0},
1046 {"allow_index_reg", set_allow_index_reg
, 1},
1047 {"disallow_index_reg", set_allow_index_reg
, 0},
1048 {"sse_check", set_check
, 0},
1049 {"operand_check", set_check
, 1},
1050 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1051 {"largecomm", handle_large_common
, 0},
1053 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1054 {"loc", dwarf2_directive_loc
, 0},
1055 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1058 {"secrel32", pe_directive_secrel
, 0},
1063 /* For interface with expression (). */
1064 extern char *input_line_pointer
;
1066 /* Hash table for instruction mnemonic lookup. */
1067 static struct hash_control
*op_hash
;
1069 /* Hash table for register lookup. */
1070 static struct hash_control
*reg_hash
;
1073 i386_align_code (fragS
*fragP
, int count
)
1075 /* Various efficient no-op patterns for aligning code labels.
1076 Note: Don't try to assemble the instructions in the comments.
1077 0L and 0w are not legal. */
1078 static const unsigned char f32_1
[] =
1080 static const unsigned char f32_2
[] =
1081 {0x66,0x90}; /* xchg %ax,%ax */
1082 static const unsigned char f32_3
[] =
1083 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1084 static const unsigned char f32_4
[] =
1085 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1086 static const unsigned char f32_5
[] =
1088 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1089 static const unsigned char f32_6
[] =
1090 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1091 static const unsigned char f32_7
[] =
1092 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1093 static const unsigned char f32_8
[] =
1095 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1096 static const unsigned char f32_9
[] =
1097 {0x89,0xf6, /* movl %esi,%esi */
1098 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1099 static const unsigned char f32_10
[] =
1100 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1101 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1102 static const unsigned char f32_11
[] =
1103 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1104 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1105 static const unsigned char f32_12
[] =
1106 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1107 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1108 static const unsigned char f32_13
[] =
1109 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1110 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1111 static const unsigned char f32_14
[] =
1112 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1113 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1114 static const unsigned char f16_3
[] =
1115 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1116 static const unsigned char f16_4
[] =
1117 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1118 static const unsigned char f16_5
[] =
1120 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1121 static const unsigned char f16_6
[] =
1122 {0x89,0xf6, /* mov %si,%si */
1123 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1124 static const unsigned char f16_7
[] =
1125 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1126 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1127 static const unsigned char f16_8
[] =
1128 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1129 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1130 static const unsigned char jump_31
[] =
1131 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1132 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1133 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1134 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1135 static const unsigned char *const f32_patt
[] = {
1136 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1137 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1139 static const unsigned char *const f16_patt
[] = {
1140 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1142 /* nopl (%[re]ax) */
1143 static const unsigned char alt_3
[] =
1145 /* nopl 0(%[re]ax) */
1146 static const unsigned char alt_4
[] =
1147 {0x0f,0x1f,0x40,0x00};
1148 /* nopl 0(%[re]ax,%[re]ax,1) */
1149 static const unsigned char alt_5
[] =
1150 {0x0f,0x1f,0x44,0x00,0x00};
1151 /* nopw 0(%[re]ax,%[re]ax,1) */
1152 static const unsigned char alt_6
[] =
1153 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1154 /* nopl 0L(%[re]ax) */
1155 static const unsigned char alt_7
[] =
1156 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1157 /* nopl 0L(%[re]ax,%[re]ax,1) */
1158 static const unsigned char alt_8
[] =
1159 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1160 /* nopw 0L(%[re]ax,%[re]ax,1) */
1161 static const unsigned char alt_9
[] =
1162 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1163 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1164 static const unsigned char alt_10
[] =
1165 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1166 static const unsigned char *const alt_patt
[] = {
1167 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1171 /* Only align for at least a positive non-zero boundary. */
1172 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1175 /* We need to decide which NOP sequence to use for 32bit and
1176 64bit. When -mtune= is used:
1178 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1179 PROCESSOR_GENERIC32, f32_patt will be used.
1180 2. For the rest, alt_patt will be used.
1182 When -mtune= isn't used, alt_patt will be used if
1183 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1186 When -march= or .arch is used, we can't use anything beyond
1187 cpu_arch_isa_flags. */
1189 if (flag_code
== CODE_16BIT
)
1193 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1195 /* Adjust jump offset. */
1196 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1199 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1200 f16_patt
[count
- 1], count
);
1204 const unsigned char *const *patt
= NULL
;
1206 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1208 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1209 switch (cpu_arch_tune
)
1211 case PROCESSOR_UNKNOWN
:
1212 /* We use cpu_arch_isa_flags to check if we SHOULD
1213 optimize with nops. */
1214 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1219 case PROCESSOR_PENTIUM4
:
1220 case PROCESSOR_NOCONA
:
1221 case PROCESSOR_CORE
:
1222 case PROCESSOR_CORE2
:
1223 case PROCESSOR_COREI7
:
1224 case PROCESSOR_L1OM
:
1225 case PROCESSOR_K1OM
:
1226 case PROCESSOR_GENERIC64
:
1228 case PROCESSOR_ATHLON
:
1230 case PROCESSOR_AMDFAM10
:
1232 case PROCESSOR_ZNVER
:
1236 case PROCESSOR_I386
:
1237 case PROCESSOR_I486
:
1238 case PROCESSOR_PENTIUM
:
1239 case PROCESSOR_PENTIUMPRO
:
1240 case PROCESSOR_IAMCU
:
1241 case PROCESSOR_GENERIC32
:
1248 switch (fragP
->tc_frag_data
.tune
)
1250 case PROCESSOR_UNKNOWN
:
1251 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1252 PROCESSOR_UNKNOWN. */
1256 case PROCESSOR_I386
:
1257 case PROCESSOR_I486
:
1258 case PROCESSOR_PENTIUM
:
1259 case PROCESSOR_IAMCU
:
1261 case PROCESSOR_ATHLON
:
1263 case PROCESSOR_AMDFAM10
:
1265 case PROCESSOR_ZNVER
:
1267 case PROCESSOR_GENERIC32
:
1268 /* We use cpu_arch_isa_flags to check if we CAN optimize
1270 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1275 case PROCESSOR_PENTIUMPRO
:
1276 case PROCESSOR_PENTIUM4
:
1277 case PROCESSOR_NOCONA
:
1278 case PROCESSOR_CORE
:
1279 case PROCESSOR_CORE2
:
1280 case PROCESSOR_COREI7
:
1281 case PROCESSOR_L1OM
:
1282 case PROCESSOR_K1OM
:
1283 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1288 case PROCESSOR_GENERIC64
:
1294 if (patt
== f32_patt
)
1296 /* If the padding is less than 15 bytes, we use the normal
1297 ones. Otherwise, we use a jump instruction and adjust
1301 /* For 64bit, the limit is 3 bytes. */
1302 if (flag_code
== CODE_64BIT
1303 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1308 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1309 patt
[count
- 1], count
);
1312 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1314 /* Adjust jump offset. */
1315 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1320 /* Maximum length of an instruction is 10 byte. If the
1321 padding is greater than 10 bytes and we don't use jump,
1322 we have to break it into smaller pieces. */
1323 int padding
= count
;
1324 while (padding
> 10)
1327 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1332 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1333 patt
[padding
- 1], padding
);
1336 fragP
->fr_var
= count
;
1340 operand_type_all_zero (const union i386_operand_type
*x
)
1342 switch (ARRAY_SIZE(x
->array
))
1351 return !x
->array
[0];
1358 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1360 switch (ARRAY_SIZE(x
->array
))
1375 operand_type_equal (const union i386_operand_type
*x
,
1376 const union i386_operand_type
*y
)
1378 switch (ARRAY_SIZE(x
->array
))
1381 if (x
->array
[2] != y
->array
[2])
1384 if (x
->array
[1] != y
->array
[1])
1387 return x
->array
[0] == y
->array
[0];
1395 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1397 switch (ARRAY_SIZE(x
->array
))
1406 return !x
->array
[0];
1413 cpu_flags_equal (const union i386_cpu_flags
*x
,
1414 const union i386_cpu_flags
*y
)
1416 switch (ARRAY_SIZE(x
->array
))
1419 if (x
->array
[2] != y
->array
[2])
1422 if (x
->array
[1] != y
->array
[1])
1425 return x
->array
[0] == y
->array
[0];
1433 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1435 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1436 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1439 static INLINE i386_cpu_flags
1440 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1442 switch (ARRAY_SIZE (x
.array
))
1445 x
.array
[2] &= y
.array
[2];
1447 x
.array
[1] &= y
.array
[1];
1449 x
.array
[0] &= y
.array
[0];
1457 static INLINE i386_cpu_flags
1458 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1460 switch (ARRAY_SIZE (x
.array
))
1463 x
.array
[2] |= y
.array
[2];
1465 x
.array
[1] |= y
.array
[1];
1467 x
.array
[0] |= y
.array
[0];
1475 static INLINE i386_cpu_flags
1476 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1478 switch (ARRAY_SIZE (x
.array
))
1481 x
.array
[2] &= ~y
.array
[2];
1483 x
.array
[1] &= ~y
.array
[1];
1485 x
.array
[0] &= ~y
.array
[0];
1494 valid_iamcu_cpu_flags (const i386_cpu_flags
*flags
)
1496 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
1498 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_COMPAT_FLAGS
;
1499 i386_cpu_flags compat_flags
;
1500 compat_flags
= cpu_flags_and_not (*flags
, iamcu_flags
);
1501 return cpu_flags_all_zero (&compat_flags
);
1507 #define CPU_FLAGS_ARCH_MATCH 0x1
1508 #define CPU_FLAGS_64BIT_MATCH 0x2
1509 #define CPU_FLAGS_AES_MATCH 0x4
1510 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1511 #define CPU_FLAGS_AVX_MATCH 0x10
1513 #define CPU_FLAGS_32BIT_MATCH \
1514 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1515 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1516 #define CPU_FLAGS_PERFECT_MATCH \
1517 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1519 /* Return CPU flags match bits. */
1522 cpu_flags_match (const insn_template
*t
)
1524 i386_cpu_flags x
= t
->cpu_flags
;
1525 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1527 x
.bitfield
.cpu64
= 0;
1528 x
.bitfield
.cpuno64
= 0;
1530 if (cpu_flags_all_zero (&x
))
1532 /* This instruction is available on all archs. */
1533 match
|= CPU_FLAGS_32BIT_MATCH
;
1537 /* This instruction is available only on some archs. */
1538 i386_cpu_flags cpu
= cpu_arch_flags
;
1540 cpu
.bitfield
.cpu64
= 0;
1541 cpu
.bitfield
.cpuno64
= 0;
1542 cpu
= cpu_flags_and (x
, cpu
);
1543 if (!cpu_flags_all_zero (&cpu
))
1545 if (x
.bitfield
.cpuavx
)
1547 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1548 if (cpu
.bitfield
.cpuavx
)
1550 /* Check SSE2AVX. */
1551 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1553 match
|= (CPU_FLAGS_ARCH_MATCH
1554 | CPU_FLAGS_AVX_MATCH
);
1556 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1557 match
|= CPU_FLAGS_AES_MATCH
;
1559 if (!x
.bitfield
.cpupclmul
1560 || cpu
.bitfield
.cpupclmul
)
1561 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1565 match
|= CPU_FLAGS_ARCH_MATCH
;
1567 else if (x
.bitfield
.cpuavx512vl
)
1569 /* Match AVX512VL. */
1570 if (cpu
.bitfield
.cpuavx512vl
)
1572 /* Need another match. */
1573 cpu
.bitfield
.cpuavx512vl
= 0;
1574 if (!cpu_flags_all_zero (&cpu
))
1575 match
|= CPU_FLAGS_32BIT_MATCH
;
1577 match
|= CPU_FLAGS_ARCH_MATCH
;
1580 match
|= CPU_FLAGS_ARCH_MATCH
;
1583 match
|= CPU_FLAGS_32BIT_MATCH
;
1589 static INLINE i386_operand_type
1590 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1592 switch (ARRAY_SIZE (x
.array
))
1595 x
.array
[2] &= y
.array
[2];
1597 x
.array
[1] &= y
.array
[1];
1599 x
.array
[0] &= y
.array
[0];
1607 static INLINE i386_operand_type
1608 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1610 switch (ARRAY_SIZE (x
.array
))
1613 x
.array
[2] |= y
.array
[2];
1615 x
.array
[1] |= y
.array
[1];
1617 x
.array
[0] |= y
.array
[0];
1625 static INLINE i386_operand_type
1626 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1628 switch (ARRAY_SIZE (x
.array
))
1631 x
.array
[2] ^= y
.array
[2];
1633 x
.array
[1] ^= y
.array
[1];
1635 x
.array
[0] ^= y
.array
[0];
1643 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1644 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1645 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1646 static const i386_operand_type inoutportreg
1647 = OPERAND_TYPE_INOUTPORTREG
;
1648 static const i386_operand_type reg16_inoutportreg
1649 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1650 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1651 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1652 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1653 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1654 static const i386_operand_type anydisp
1655 = OPERAND_TYPE_ANYDISP
;
1656 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1657 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1658 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1659 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1660 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1661 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1662 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1663 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1664 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1665 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1666 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1667 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1668 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1669 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1680 operand_type_check (i386_operand_type t
, enum operand_type c
)
1685 return (t
.bitfield
.reg8
1688 || t
.bitfield
.reg64
);
1691 return (t
.bitfield
.imm8
1695 || t
.bitfield
.imm32s
1696 || t
.bitfield
.imm64
);
1699 return (t
.bitfield
.disp8
1700 || t
.bitfield
.disp16
1701 || t
.bitfield
.disp32
1702 || t
.bitfield
.disp32s
1703 || t
.bitfield
.disp64
);
1706 return (t
.bitfield
.disp8
1707 || t
.bitfield
.disp16
1708 || t
.bitfield
.disp32
1709 || t
.bitfield
.disp32s
1710 || t
.bitfield
.disp64
1711 || t
.bitfield
.baseindex
);
1720 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1721 operand J for instruction template T. */
1724 match_reg_size (const insn_template
*t
, unsigned int j
)
1726 return !((i
.types
[j
].bitfield
.byte
1727 && !t
->operand_types
[j
].bitfield
.byte
)
1728 || (i
.types
[j
].bitfield
.word
1729 && !t
->operand_types
[j
].bitfield
.word
)
1730 || (i
.types
[j
].bitfield
.dword
1731 && !t
->operand_types
[j
].bitfield
.dword
)
1732 || (i
.types
[j
].bitfield
.qword
1733 && !t
->operand_types
[j
].bitfield
.qword
));
1736 /* Return 1 if there is no conflict in any size on operand J for
1737 instruction template T. */
1740 match_mem_size (const insn_template
*t
, unsigned int j
)
1742 return (match_reg_size (t
, j
)
1743 && !((i
.types
[j
].bitfield
.unspecified
1745 && !t
->operand_types
[j
].bitfield
.unspecified
)
1746 || (i
.types
[j
].bitfield
.fword
1747 && !t
->operand_types
[j
].bitfield
.fword
)
1748 || (i
.types
[j
].bitfield
.tbyte
1749 && !t
->operand_types
[j
].bitfield
.tbyte
)
1750 || (i
.types
[j
].bitfield
.xmmword
1751 && !t
->operand_types
[j
].bitfield
.xmmword
)
1752 || (i
.types
[j
].bitfield
.ymmword
1753 && !t
->operand_types
[j
].bitfield
.ymmword
)
1754 || (i
.types
[j
].bitfield
.zmmword
1755 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1758 /* Return 1 if there is no size conflict on any operands for
1759 instruction template T. */
1762 operand_size_match (const insn_template
*t
)
1767 /* Don't check jump instructions. */
1768 if (t
->opcode_modifier
.jump
1769 || t
->opcode_modifier
.jumpbyte
1770 || t
->opcode_modifier
.jumpdword
1771 || t
->opcode_modifier
.jumpintersegment
)
1774 /* Check memory and accumulator operand size. */
1775 for (j
= 0; j
< i
.operands
; j
++)
1777 if (t
->operand_types
[j
].bitfield
.anysize
)
1780 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1786 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1795 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1798 i
.error
= operand_size_mismatch
;
1802 /* Check reverse. */
1803 gas_assert (i
.operands
== 2);
1806 for (j
= 0; j
< 2; j
++)
1808 if (t
->operand_types
[j
].bitfield
.acc
1809 && !match_reg_size (t
, j
? 0 : 1))
1812 if (i
.types
[j
].bitfield
.mem
1813 && !match_mem_size (t
, j
? 0 : 1))
1821 operand_type_match (i386_operand_type overlap
,
1822 i386_operand_type given
)
1824 i386_operand_type temp
= overlap
;
1826 temp
.bitfield
.jumpabsolute
= 0;
1827 temp
.bitfield
.unspecified
= 0;
1828 temp
.bitfield
.byte
= 0;
1829 temp
.bitfield
.word
= 0;
1830 temp
.bitfield
.dword
= 0;
1831 temp
.bitfield
.fword
= 0;
1832 temp
.bitfield
.qword
= 0;
1833 temp
.bitfield
.tbyte
= 0;
1834 temp
.bitfield
.xmmword
= 0;
1835 temp
.bitfield
.ymmword
= 0;
1836 temp
.bitfield
.zmmword
= 0;
1837 if (operand_type_all_zero (&temp
))
1840 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1841 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1845 i
.error
= operand_type_mismatch
;
1849 /* If given types g0 and g1 are registers they must be of the same type
1850 unless the expected operand type register overlap is null.
1851 Note that Acc in a template matches every size of reg. */
1854 operand_type_register_match (i386_operand_type m0
,
1855 i386_operand_type g0
,
1856 i386_operand_type t0
,
1857 i386_operand_type m1
,
1858 i386_operand_type g1
,
1859 i386_operand_type t1
)
1861 if (!operand_type_check (g0
, reg
))
1864 if (!operand_type_check (g1
, reg
))
1867 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1868 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1869 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1870 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1873 if (m0
.bitfield
.acc
)
1875 t0
.bitfield
.reg8
= 1;
1876 t0
.bitfield
.reg16
= 1;
1877 t0
.bitfield
.reg32
= 1;
1878 t0
.bitfield
.reg64
= 1;
1881 if (m1
.bitfield
.acc
)
1883 t1
.bitfield
.reg8
= 1;
1884 t1
.bitfield
.reg16
= 1;
1885 t1
.bitfield
.reg32
= 1;
1886 t1
.bitfield
.reg64
= 1;
1889 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1890 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1891 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1892 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1895 i
.error
= register_type_mismatch
;
1900 static INLINE
unsigned int
1901 register_number (const reg_entry
*r
)
1903 unsigned int nr
= r
->reg_num
;
1905 if (r
->reg_flags
& RegRex
)
1908 if (r
->reg_flags
& RegVRex
)
1914 static INLINE
unsigned int
1915 mode_from_disp_size (i386_operand_type t
)
1917 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1919 else if (t
.bitfield
.disp16
1920 || t
.bitfield
.disp32
1921 || t
.bitfield
.disp32s
)
1928 fits_in_signed_byte (addressT num
)
1930 return num
+ 0x80 <= 0xff;
1934 fits_in_unsigned_byte (addressT num
)
1940 fits_in_unsigned_word (addressT num
)
1942 return num
<= 0xffff;
1946 fits_in_signed_word (addressT num
)
1948 return num
+ 0x8000 <= 0xffff;
1952 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1957 return num
+ 0x80000000 <= 0xffffffff;
1959 } /* fits_in_signed_long() */
1962 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
1967 return num
<= 0xffffffff;
1969 } /* fits_in_unsigned_long() */
1972 fits_in_vec_disp8 (offsetT num
)
1974 int shift
= i
.memshift
;
1980 mask
= (1 << shift
) - 1;
1982 /* Return 0 if NUM isn't properly aligned. */
1986 /* Check if NUM will fit in 8bit after shift. */
1987 return fits_in_signed_byte (num
>> shift
);
1991 fits_in_imm4 (offsetT num
)
1993 return (num
& 0xf) == num
;
1996 static i386_operand_type
1997 smallest_imm_type (offsetT num
)
1999 i386_operand_type t
;
2001 operand_type_set (&t
, 0);
2002 t
.bitfield
.imm64
= 1;
2004 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2006 /* This code is disabled on the 486 because all the Imm1 forms
2007 in the opcode table are slower on the i486. They're the
2008 versions with the implicitly specified single-position
2009 displacement, which has another syntax if you really want to
2011 t
.bitfield
.imm1
= 1;
2012 t
.bitfield
.imm8
= 1;
2013 t
.bitfield
.imm8s
= 1;
2014 t
.bitfield
.imm16
= 1;
2015 t
.bitfield
.imm32
= 1;
2016 t
.bitfield
.imm32s
= 1;
2018 else if (fits_in_signed_byte (num
))
2020 t
.bitfield
.imm8
= 1;
2021 t
.bitfield
.imm8s
= 1;
2022 t
.bitfield
.imm16
= 1;
2023 t
.bitfield
.imm32
= 1;
2024 t
.bitfield
.imm32s
= 1;
2026 else if (fits_in_unsigned_byte (num
))
2028 t
.bitfield
.imm8
= 1;
2029 t
.bitfield
.imm16
= 1;
2030 t
.bitfield
.imm32
= 1;
2031 t
.bitfield
.imm32s
= 1;
2033 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2035 t
.bitfield
.imm16
= 1;
2036 t
.bitfield
.imm32
= 1;
2037 t
.bitfield
.imm32s
= 1;
2039 else if (fits_in_signed_long (num
))
2041 t
.bitfield
.imm32
= 1;
2042 t
.bitfield
.imm32s
= 1;
2044 else if (fits_in_unsigned_long (num
))
2045 t
.bitfield
.imm32
= 1;
2051 offset_in_range (offsetT val
, int size
)
2057 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2058 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2059 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2061 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2067 /* If BFD64, sign extend val for 32bit address mode. */
2068 if (flag_code
!= CODE_64BIT
2069 || i
.prefix
[ADDR_PREFIX
])
2070 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2071 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2074 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2076 char buf1
[40], buf2
[40];
2078 sprint_value (buf1
, val
);
2079 sprint_value (buf2
, val
& mask
);
2080 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2094 a. PREFIX_EXIST if attempting to add a prefix where one from the
2095 same class already exists.
2096 b. PREFIX_LOCK if lock prefix is added.
2097 c. PREFIX_REP if rep/repne prefix is added.
2098 d. PREFIX_OTHER if other prefix is added.
2101 static enum PREFIX_GROUP
2102 add_prefix (unsigned int prefix
)
2104 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2107 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2108 && flag_code
== CODE_64BIT
)
2110 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2111 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2112 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2123 case CS_PREFIX_OPCODE
:
2124 case DS_PREFIX_OPCODE
:
2125 case ES_PREFIX_OPCODE
:
2126 case FS_PREFIX_OPCODE
:
2127 case GS_PREFIX_OPCODE
:
2128 case SS_PREFIX_OPCODE
:
2132 case REPNE_PREFIX_OPCODE
:
2133 case REPE_PREFIX_OPCODE
:
2138 case LOCK_PREFIX_OPCODE
:
2147 case ADDR_PREFIX_OPCODE
:
2151 case DATA_PREFIX_OPCODE
:
2155 if (i
.prefix
[q
] != 0)
2163 i
.prefix
[q
] |= prefix
;
2166 as_bad (_("same type of prefix used twice"));
2172 update_code_flag (int value
, int check
)
2174 PRINTF_LIKE ((*as_error
));
2176 flag_code
= (enum flag_code
) value
;
2177 if (flag_code
== CODE_64BIT
)
2179 cpu_arch_flags
.bitfield
.cpu64
= 1;
2180 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2184 cpu_arch_flags
.bitfield
.cpu64
= 0;
2185 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2187 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2190 as_error
= as_fatal
;
2193 (*as_error
) (_("64bit mode not supported on `%s'."),
2194 cpu_arch_name
? cpu_arch_name
: default_arch
);
2196 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2199 as_error
= as_fatal
;
2202 (*as_error
) (_("32bit mode not supported on `%s'."),
2203 cpu_arch_name
? cpu_arch_name
: default_arch
);
2205 stackop_size
= '\0';
2209 set_code_flag (int value
)
2211 update_code_flag (value
, 0);
2215 set_16bit_gcc_code_flag (int new_code_flag
)
2217 flag_code
= (enum flag_code
) new_code_flag
;
2218 if (flag_code
!= CODE_16BIT
)
2220 cpu_arch_flags
.bitfield
.cpu64
= 0;
2221 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2222 stackop_size
= LONG_MNEM_SUFFIX
;
2226 set_intel_syntax (int syntax_flag
)
2228 /* Find out if register prefixing is specified. */
2229 int ask_naked_reg
= 0;
2232 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2235 int e
= get_symbol_name (&string
);
2237 if (strcmp (string
, "prefix") == 0)
2239 else if (strcmp (string
, "noprefix") == 0)
2242 as_bad (_("bad argument to syntax directive."));
2243 (void) restore_line_pointer (e
);
2245 demand_empty_rest_of_line ();
2247 intel_syntax
= syntax_flag
;
2249 if (ask_naked_reg
== 0)
2250 allow_naked_reg
= (intel_syntax
2251 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2253 allow_naked_reg
= (ask_naked_reg
< 0);
2255 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2257 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2258 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2259 register_prefix
= allow_naked_reg
? "" : "%";
2263 set_intel_mnemonic (int mnemonic_flag
)
2265 intel_mnemonic
= mnemonic_flag
;
2269 set_allow_index_reg (int flag
)
2271 allow_index_reg
= flag
;
2275 set_check (int what
)
2277 enum check_kind
*kind
;
2282 kind
= &operand_check
;
2293 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2296 int e
= get_symbol_name (&string
);
2298 if (strcmp (string
, "none") == 0)
2300 else if (strcmp (string
, "warning") == 0)
2301 *kind
= check_warning
;
2302 else if (strcmp (string
, "error") == 0)
2303 *kind
= check_error
;
2305 as_bad (_("bad argument to %s_check directive."), str
);
2306 (void) restore_line_pointer (e
);
2309 as_bad (_("missing argument for %s_check directive"), str
);
2311 demand_empty_rest_of_line ();
2315 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2316 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2318 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2319 static const char *arch
;
2321 /* Intel LIOM is only supported on ELF. */
2327 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2328 use default_arch. */
2329 arch
= cpu_arch_name
;
2331 arch
= default_arch
;
2334 /* If we are targeting Intel MCU, we must enable it. */
2335 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2336 || new_flag
.bitfield
.cpuiamcu
)
2339 /* If we are targeting Intel L1OM, we must enable it. */
2340 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2341 || new_flag
.bitfield
.cpul1om
)
2344 /* If we are targeting Intel K1OM, we must enable it. */
2345 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2346 || new_flag
.bitfield
.cpuk1om
)
2349 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2354 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2358 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2361 int e
= get_symbol_name (&string
);
2363 i386_cpu_flags flags
;
2365 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2367 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2369 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2373 cpu_arch_name
= cpu_arch
[j
].name
;
2374 cpu_sub_arch_name
= NULL
;
2375 cpu_arch_flags
= cpu_arch
[j
].flags
;
2376 if (flag_code
== CODE_64BIT
)
2378 cpu_arch_flags
.bitfield
.cpu64
= 1;
2379 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2383 cpu_arch_flags
.bitfield
.cpu64
= 0;
2384 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2386 cpu_arch_isa
= cpu_arch
[j
].type
;
2387 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2388 if (!cpu_arch_tune_set
)
2390 cpu_arch_tune
= cpu_arch_isa
;
2391 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2396 flags
= cpu_flags_or (cpu_arch_flags
,
2399 if (!valid_iamcu_cpu_flags (&flags
))
2400 as_fatal (_("`%s' isn't valid for Intel MCU"),
2402 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2404 if (cpu_sub_arch_name
)
2406 char *name
= cpu_sub_arch_name
;
2407 cpu_sub_arch_name
= concat (name
,
2409 (const char *) NULL
);
2413 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2414 cpu_arch_flags
= flags
;
2415 cpu_arch_isa_flags
= flags
;
2417 (void) restore_line_pointer (e
);
2418 demand_empty_rest_of_line ();
2423 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2425 /* Disable an ISA entension. */
2426 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2427 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2429 flags
= cpu_flags_and_not (cpu_arch_flags
,
2430 cpu_noarch
[j
].flags
);
2431 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2433 if (cpu_sub_arch_name
)
2435 char *name
= cpu_sub_arch_name
;
2436 cpu_sub_arch_name
= concat (name
, string
,
2437 (const char *) NULL
);
2441 cpu_sub_arch_name
= xstrdup (string
);
2442 cpu_arch_flags
= flags
;
2443 cpu_arch_isa_flags
= flags
;
2445 (void) restore_line_pointer (e
);
2446 demand_empty_rest_of_line ();
2450 j
= ARRAY_SIZE (cpu_arch
);
2453 if (j
>= ARRAY_SIZE (cpu_arch
))
2454 as_bad (_("no such architecture: `%s'"), string
);
2456 *input_line_pointer
= e
;
2459 as_bad (_("missing cpu architecture"));
2461 no_cond_jump_promotion
= 0;
2462 if (*input_line_pointer
== ','
2463 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2468 ++input_line_pointer
;
2469 e
= get_symbol_name (&string
);
2471 if (strcmp (string
, "nojumps") == 0)
2472 no_cond_jump_promotion
= 1;
2473 else if (strcmp (string
, "jumps") == 0)
2476 as_bad (_("no such architecture modifier: `%s'"), string
);
2478 (void) restore_line_pointer (e
);
2481 demand_empty_rest_of_line ();
2484 enum bfd_architecture
2487 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2489 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2490 || flag_code
!= CODE_64BIT
)
2491 as_fatal (_("Intel L1OM is 64bit ELF only"));
2492 return bfd_arch_l1om
;
2494 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2496 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2497 || flag_code
!= CODE_64BIT
)
2498 as_fatal (_("Intel K1OM is 64bit ELF only"));
2499 return bfd_arch_k1om
;
2501 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2503 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2504 || flag_code
== CODE_64BIT
)
2505 as_fatal (_("Intel MCU is 32bit ELF only"));
2506 return bfd_arch_iamcu
;
2509 return bfd_arch_i386
;
2515 if (!strncmp (default_arch
, "x86_64", 6))
2517 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2519 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2520 || default_arch
[6] != '\0')
2521 as_fatal (_("Intel L1OM is 64bit ELF only"));
2522 return bfd_mach_l1om
;
2524 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2526 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2527 || default_arch
[6] != '\0')
2528 as_fatal (_("Intel K1OM is 64bit ELF only"));
2529 return bfd_mach_k1om
;
2531 else if (default_arch
[6] == '\0')
2532 return bfd_mach_x86_64
;
2534 return bfd_mach_x64_32
;
2536 else if (!strcmp (default_arch
, "i386")
2537 || !strcmp (default_arch
, "iamcu"))
2539 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2541 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2542 as_fatal (_("Intel MCU is 32bit ELF only"));
2543 return bfd_mach_i386_iamcu
;
2546 return bfd_mach_i386_i386
;
2549 as_fatal (_("unknown architecture"));
2555 const char *hash_err
;
2557 /* Initialize op_hash hash table. */
2558 op_hash
= hash_new ();
2561 const insn_template
*optab
;
2562 templates
*core_optab
;
2564 /* Setup for loop. */
2566 core_optab
= XNEW (templates
);
2567 core_optab
->start
= optab
;
2572 if (optab
->name
== NULL
2573 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2575 /* different name --> ship out current template list;
2576 add to hash table; & begin anew. */
2577 core_optab
->end
= optab
;
2578 hash_err
= hash_insert (op_hash
,
2580 (void *) core_optab
);
2583 as_fatal (_("can't hash %s: %s"),
2587 if (optab
->name
== NULL
)
2589 core_optab
= XNEW (templates
);
2590 core_optab
->start
= optab
;
2595 /* Initialize reg_hash hash table. */
2596 reg_hash
= hash_new ();
2598 const reg_entry
*regtab
;
2599 unsigned int regtab_size
= i386_regtab_size
;
2601 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2603 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2605 as_fatal (_("can't hash %s: %s"),
2611 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2616 for (c
= 0; c
< 256; c
++)
2621 mnemonic_chars
[c
] = c
;
2622 register_chars
[c
] = c
;
2623 operand_chars
[c
] = c
;
2625 else if (ISLOWER (c
))
2627 mnemonic_chars
[c
] = c
;
2628 register_chars
[c
] = c
;
2629 operand_chars
[c
] = c
;
2631 else if (ISUPPER (c
))
2633 mnemonic_chars
[c
] = TOLOWER (c
);
2634 register_chars
[c
] = mnemonic_chars
[c
];
2635 operand_chars
[c
] = c
;
2637 else if (c
== '{' || c
== '}')
2638 operand_chars
[c
] = c
;
2640 if (ISALPHA (c
) || ISDIGIT (c
))
2641 identifier_chars
[c
] = c
;
2644 identifier_chars
[c
] = c
;
2645 operand_chars
[c
] = c
;
2650 identifier_chars
['@'] = '@';
2653 identifier_chars
['?'] = '?';
2654 operand_chars
['?'] = '?';
2656 digit_chars
['-'] = '-';
2657 mnemonic_chars
['_'] = '_';
2658 mnemonic_chars
['-'] = '-';
2659 mnemonic_chars
['.'] = '.';
2660 identifier_chars
['_'] = '_';
2661 identifier_chars
['.'] = '.';
2663 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2664 operand_chars
[(unsigned char) *p
] = *p
;
2667 if (flag_code
== CODE_64BIT
)
2669 #if defined (OBJ_COFF) && defined (TE_PE)
2670 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2673 x86_dwarf2_return_column
= 16;
2675 x86_cie_data_alignment
= -8;
2679 x86_dwarf2_return_column
= 8;
2680 x86_cie_data_alignment
= -4;
2685 i386_print_statistics (FILE *file
)
2687 hash_print_statistics (file
, "i386 opcode", op_hash
);
2688 hash_print_statistics (file
, "i386 register", reg_hash
);
2693 /* Debugging routines for md_assemble. */
2694 static void pte (insn_template
*);
2695 static void pt (i386_operand_type
);
2696 static void pe (expressionS
*);
2697 static void ps (symbolS
*);
2700 pi (char *line
, i386_insn
*x
)
2704 fprintf (stdout
, "%s: template ", line
);
2706 fprintf (stdout
, " address: base %s index %s scale %x\n",
2707 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2708 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2709 x
->log2_scale_factor
);
2710 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2711 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2712 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2713 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2714 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2715 (x
->rex
& REX_W
) != 0,
2716 (x
->rex
& REX_R
) != 0,
2717 (x
->rex
& REX_X
) != 0,
2718 (x
->rex
& REX_B
) != 0);
2719 for (j
= 0; j
< x
->operands
; j
++)
2721 fprintf (stdout
, " #%d: ", j
+ 1);
2723 fprintf (stdout
, "\n");
2724 if (x
->types
[j
].bitfield
.reg8
2725 || x
->types
[j
].bitfield
.reg16
2726 || x
->types
[j
].bitfield
.reg32
2727 || x
->types
[j
].bitfield
.reg64
2728 || x
->types
[j
].bitfield
.regmmx
2729 || x
->types
[j
].bitfield
.regxmm
2730 || x
->types
[j
].bitfield
.regymm
2731 || x
->types
[j
].bitfield
.regzmm
2732 || x
->types
[j
].bitfield
.sreg2
2733 || x
->types
[j
].bitfield
.sreg3
2734 || x
->types
[j
].bitfield
.control
2735 || x
->types
[j
].bitfield
.debug
2736 || x
->types
[j
].bitfield
.test
)
2737 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2738 if (operand_type_check (x
->types
[j
], imm
))
2740 if (operand_type_check (x
->types
[j
], disp
))
2741 pe (x
->op
[j
].disps
);
2746 pte (insn_template
*t
)
2749 fprintf (stdout
, " %d operands ", t
->operands
);
2750 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2751 if (t
->extension_opcode
!= None
)
2752 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2753 if (t
->opcode_modifier
.d
)
2754 fprintf (stdout
, "D");
2755 if (t
->opcode_modifier
.w
)
2756 fprintf (stdout
, "W");
2757 fprintf (stdout
, "\n");
2758 for (j
= 0; j
< t
->operands
; j
++)
2760 fprintf (stdout
, " #%d type ", j
+ 1);
2761 pt (t
->operand_types
[j
]);
2762 fprintf (stdout
, "\n");
2769 fprintf (stdout
, " operation %d\n", e
->X_op
);
2770 fprintf (stdout
, " add_number %ld (%lx)\n",
2771 (long) e
->X_add_number
, (long) e
->X_add_number
);
2772 if (e
->X_add_symbol
)
2774 fprintf (stdout
, " add_symbol ");
2775 ps (e
->X_add_symbol
);
2776 fprintf (stdout
, "\n");
2780 fprintf (stdout
, " op_symbol ");
2781 ps (e
->X_op_symbol
);
2782 fprintf (stdout
, "\n");
2789 fprintf (stdout
, "%s type %s%s",
2791 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2792 segment_name (S_GET_SEGMENT (s
)));
2795 static struct type_name
2797 i386_operand_type mask
;
2800 const type_names
[] =
2802 { OPERAND_TYPE_REG8
, "r8" },
2803 { OPERAND_TYPE_REG16
, "r16" },
2804 { OPERAND_TYPE_REG32
, "r32" },
2805 { OPERAND_TYPE_REG64
, "r64" },
2806 { OPERAND_TYPE_IMM8
, "i8" },
2807 { OPERAND_TYPE_IMM8
, "i8s" },
2808 { OPERAND_TYPE_IMM16
, "i16" },
2809 { OPERAND_TYPE_IMM32
, "i32" },
2810 { OPERAND_TYPE_IMM32S
, "i32s" },
2811 { OPERAND_TYPE_IMM64
, "i64" },
2812 { OPERAND_TYPE_IMM1
, "i1" },
2813 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2814 { OPERAND_TYPE_DISP8
, "d8" },
2815 { OPERAND_TYPE_DISP16
, "d16" },
2816 { OPERAND_TYPE_DISP32
, "d32" },
2817 { OPERAND_TYPE_DISP32S
, "d32s" },
2818 { OPERAND_TYPE_DISP64
, "d64" },
2819 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2820 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2821 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2822 { OPERAND_TYPE_CONTROL
, "control reg" },
2823 { OPERAND_TYPE_TEST
, "test reg" },
2824 { OPERAND_TYPE_DEBUG
, "debug reg" },
2825 { OPERAND_TYPE_FLOATREG
, "FReg" },
2826 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2827 { OPERAND_TYPE_SREG2
, "SReg2" },
2828 { OPERAND_TYPE_SREG3
, "SReg3" },
2829 { OPERAND_TYPE_ACC
, "Acc" },
2830 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2831 { OPERAND_TYPE_REGMMX
, "rMMX" },
2832 { OPERAND_TYPE_REGXMM
, "rXMM" },
2833 { OPERAND_TYPE_REGYMM
, "rYMM" },
2834 { OPERAND_TYPE_REGZMM
, "rZMM" },
2835 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2836 { OPERAND_TYPE_ESSEG
, "es" },
2840 pt (i386_operand_type t
)
2843 i386_operand_type a
;
2845 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2847 a
= operand_type_and (t
, type_names
[j
].mask
);
2848 if (!operand_type_all_zero (&a
))
2849 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2854 #endif /* DEBUG386 */
2856 static bfd_reloc_code_real_type
2857 reloc (unsigned int size
,
2860 bfd_reloc_code_real_type other
)
2862 if (other
!= NO_RELOC
)
2864 reloc_howto_type
*rel
;
2869 case BFD_RELOC_X86_64_GOT32
:
2870 return BFD_RELOC_X86_64_GOT64
;
2872 case BFD_RELOC_X86_64_GOTPLT64
:
2873 return BFD_RELOC_X86_64_GOTPLT64
;
2875 case BFD_RELOC_X86_64_PLTOFF64
:
2876 return BFD_RELOC_X86_64_PLTOFF64
;
2878 case BFD_RELOC_X86_64_GOTPC32
:
2879 other
= BFD_RELOC_X86_64_GOTPC64
;
2881 case BFD_RELOC_X86_64_GOTPCREL
:
2882 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2884 case BFD_RELOC_X86_64_TPOFF32
:
2885 other
= BFD_RELOC_X86_64_TPOFF64
;
2887 case BFD_RELOC_X86_64_DTPOFF32
:
2888 other
= BFD_RELOC_X86_64_DTPOFF64
;
2894 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2895 if (other
== BFD_RELOC_SIZE32
)
2898 other
= BFD_RELOC_SIZE64
;
2901 as_bad (_("there are no pc-relative size relocations"));
2907 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2908 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2911 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2913 as_bad (_("unknown relocation (%u)"), other
);
2914 else if (size
!= bfd_get_reloc_size (rel
))
2915 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2916 bfd_get_reloc_size (rel
),
2918 else if (pcrel
&& !rel
->pc_relative
)
2919 as_bad (_("non-pc-relative relocation for pc-relative field"));
2920 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2922 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2924 as_bad (_("relocated field and relocation type differ in signedness"));
2933 as_bad (_("there are no unsigned pc-relative relocations"));
2936 case 1: return BFD_RELOC_8_PCREL
;
2937 case 2: return BFD_RELOC_16_PCREL
;
2938 case 4: return BFD_RELOC_32_PCREL
;
2939 case 8: return BFD_RELOC_64_PCREL
;
2941 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2948 case 4: return BFD_RELOC_X86_64_32S
;
2953 case 1: return BFD_RELOC_8
;
2954 case 2: return BFD_RELOC_16
;
2955 case 4: return BFD_RELOC_32
;
2956 case 8: return BFD_RELOC_64
;
2958 as_bad (_("cannot do %s %u byte relocation"),
2959 sign
> 0 ? "signed" : "unsigned", size
);
2965 /* Here we decide which fixups can be adjusted to make them relative to
2966 the beginning of the section instead of the symbol. Basically we need
2967 to make sure that the dynamic relocations are done correctly, so in
2968 some cases we force the original symbol to be used. */
2971 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2973 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2977 /* Don't adjust pc-relative references to merge sections in 64-bit
2979 if (use_rela_relocations
2980 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2984 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2985 and changed later by validate_fix. */
2986 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2987 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2990 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2991 for size relocations. */
2992 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2993 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2994 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2995 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2996 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2997 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
2998 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2999 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3000 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3001 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3002 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3003 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3004 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3005 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3006 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3007 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3008 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3009 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3010 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3011 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3012 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3013 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3014 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3015 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3016 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3017 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3018 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3019 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3020 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3021 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3022 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3023 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3024 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3031 intel_float_operand (const char *mnemonic
)
3033 /* Note that the value returned is meaningful only for opcodes with (memory)
3034 operands, hence the code here is free to improperly handle opcodes that
3035 have no operands (for better performance and smaller code). */
3037 if (mnemonic
[0] != 'f')
3038 return 0; /* non-math */
3040 switch (mnemonic
[1])
3042 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3043 the fs segment override prefix not currently handled because no
3044 call path can make opcodes without operands get here */
3046 return 2 /* integer op */;
3048 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3049 return 3; /* fldcw/fldenv */
3052 if (mnemonic
[2] != 'o' /* fnop */)
3053 return 3; /* non-waiting control op */
3056 if (mnemonic
[2] == 's')
3057 return 3; /* frstor/frstpm */
3060 if (mnemonic
[2] == 'a')
3061 return 3; /* fsave */
3062 if (mnemonic
[2] == 't')
3064 switch (mnemonic
[3])
3066 case 'c': /* fstcw */
3067 case 'd': /* fstdw */
3068 case 'e': /* fstenv */
3069 case 's': /* fsts[gw] */
3075 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3076 return 0; /* fxsave/fxrstor are not really math ops */
3083 /* Build the VEX prefix. */
3086 build_vex_prefix (const insn_template
*t
)
3088 unsigned int register_specifier
;
3089 unsigned int implied_prefix
;
3090 unsigned int vector_length
;
3092 /* Check register specifier. */
3093 if (i
.vex
.register_specifier
)
3095 register_specifier
=
3096 ~register_number (i
.vex
.register_specifier
) & 0xf;
3097 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3100 register_specifier
= 0xf;
3102 /* Use 2-byte VEX prefix by swappping destination and source
3105 && i
.operands
== i
.reg_operands
3106 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3107 && i
.tm
.opcode_modifier
.s
3110 unsigned int xchg
= i
.operands
- 1;
3111 union i386_op temp_op
;
3112 i386_operand_type temp_type
;
3114 temp_type
= i
.types
[xchg
];
3115 i
.types
[xchg
] = i
.types
[0];
3116 i
.types
[0] = temp_type
;
3117 temp_op
= i
.op
[xchg
];
3118 i
.op
[xchg
] = i
.op
[0];
3121 gas_assert (i
.rm
.mode
== 3);
3125 i
.rm
.regmem
= i
.rm
.reg
;
3128 /* Use the next insn. */
3132 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3133 vector_length
= avxscalar
;
3135 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3137 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3142 case DATA_PREFIX_OPCODE
:
3145 case REPE_PREFIX_OPCODE
:
3148 case REPNE_PREFIX_OPCODE
:
3155 /* Use 2-byte VEX prefix if possible. */
3156 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3157 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3158 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3160 /* 2-byte VEX prefix. */
3164 i
.vex
.bytes
[0] = 0xc5;
3166 /* Check the REX.R bit. */
3167 r
= (i
.rex
& REX_R
) ? 0 : 1;
3168 i
.vex
.bytes
[1] = (r
<< 7
3169 | register_specifier
<< 3
3170 | vector_length
<< 2
3175 /* 3-byte VEX prefix. */
3180 switch (i
.tm
.opcode_modifier
.vexopcode
)
3184 i
.vex
.bytes
[0] = 0xc4;
3188 i
.vex
.bytes
[0] = 0xc4;
3192 i
.vex
.bytes
[0] = 0xc4;
3196 i
.vex
.bytes
[0] = 0x8f;
3200 i
.vex
.bytes
[0] = 0x8f;
3204 i
.vex
.bytes
[0] = 0x8f;
3210 /* The high 3 bits of the second VEX byte are 1's compliment
3211 of RXB bits from REX. */
3212 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3214 /* Check the REX.W bit. */
3215 w
= (i
.rex
& REX_W
) ? 1 : 0;
3216 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3219 i
.vex
.bytes
[2] = (w
<< 7
3220 | register_specifier
<< 3
3221 | vector_length
<< 2
3226 /* Build the EVEX prefix. */
3229 build_evex_prefix (void)
3231 unsigned int register_specifier
;
3232 unsigned int implied_prefix
;
3234 rex_byte vrex_used
= 0;
3236 /* Check register specifier. */
3237 if (i
.vex
.register_specifier
)
3239 gas_assert ((i
.vrex
& REX_X
) == 0);
3241 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3242 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3243 register_specifier
+= 8;
3244 /* The upper 16 registers are encoded in the fourth byte of the
3246 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3247 i
.vex
.bytes
[3] = 0x8;
3248 register_specifier
= ~register_specifier
& 0xf;
3252 register_specifier
= 0xf;
3254 /* Encode upper 16 vector index register in the fourth byte of
3256 if (!(i
.vrex
& REX_X
))
3257 i
.vex
.bytes
[3] = 0x8;
3262 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3267 case DATA_PREFIX_OPCODE
:
3270 case REPE_PREFIX_OPCODE
:
3273 case REPNE_PREFIX_OPCODE
:
3280 /* 4 byte EVEX prefix. */
3282 i
.vex
.bytes
[0] = 0x62;
3285 switch (i
.tm
.opcode_modifier
.vexopcode
)
3301 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3303 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3305 /* The fifth bit of the second EVEX byte is 1's compliment of the
3306 REX_R bit in VREX. */
3307 if (!(i
.vrex
& REX_R
))
3308 i
.vex
.bytes
[1] |= 0x10;
3312 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3314 /* When all operands are registers, the REX_X bit in REX is not
3315 used. We reuse it to encode the upper 16 registers, which is
3316 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3317 as 1's compliment. */
3318 if ((i
.vrex
& REX_B
))
3321 i
.vex
.bytes
[1] &= ~0x40;
3325 /* EVEX instructions shouldn't need the REX prefix. */
3326 i
.vrex
&= ~vrex_used
;
3327 gas_assert (i
.vrex
== 0);
3329 /* Check the REX.W bit. */
3330 w
= (i
.rex
& REX_W
) ? 1 : 0;
3331 if (i
.tm
.opcode_modifier
.vexw
)
3333 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3336 /* If w is not set it means we are dealing with WIG instruction. */
3339 if (evexwig
== evexw1
)
3343 /* Encode the U bit. */
3344 implied_prefix
|= 0x4;
3346 /* The third byte of the EVEX prefix. */
3347 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3349 /* The fourth byte of the EVEX prefix. */
3350 /* The zeroing-masking bit. */
3351 if (i
.mask
&& i
.mask
->zeroing
)
3352 i
.vex
.bytes
[3] |= 0x80;
3354 /* Don't always set the broadcast bit if there is no RC. */
3357 /* Encode the vector length. */
3358 unsigned int vec_length
;
3360 switch (i
.tm
.opcode_modifier
.evex
)
3362 case EVEXLIG
: /* LL' is ignored */
3363 vec_length
= evexlig
<< 5;
3366 vec_length
= 0 << 5;
3369 vec_length
= 1 << 5;
3372 vec_length
= 2 << 5;
3378 i
.vex
.bytes
[3] |= vec_length
;
3379 /* Encode the broadcast bit. */
3381 i
.vex
.bytes
[3] |= 0x10;
3385 if (i
.rounding
->type
!= saeonly
)
3386 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3388 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3391 if (i
.mask
&& i
.mask
->mask
)
3392 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3396 process_immext (void)
3400 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3403 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3404 with an opcode suffix which is coded in the same place as an
3405 8-bit immediate field would be.
3406 Here we check those operands and remove them afterwards. */
3409 for (x
= 0; x
< i
.operands
; x
++)
3410 if (register_number (i
.op
[x
].regs
) != x
)
3411 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3412 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3418 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3420 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3421 suffix which is coded in the same place as an 8-bit immediate
3423 Here we check those operands and remove them afterwards. */
3426 if (i
.operands
!= 3)
3429 for (x
= 0; x
< 2; x
++)
3430 if (register_number (i
.op
[x
].regs
) != x
)
3431 goto bad_register_operand
;
3433 /* Check for third operand for mwaitx/monitorx insn. */
3434 if (register_number (i
.op
[x
].regs
)
3435 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3437 bad_register_operand
:
3438 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3439 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3446 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3447 which is coded in the same place as an 8-bit immediate field
3448 would be. Here we fake an 8-bit immediate operand from the
3449 opcode suffix stored in tm.extension_opcode.
3451 AVX instructions also use this encoding, for some of
3452 3 argument instructions. */
3454 gas_assert (i
.imm_operands
<= 1
3456 || ((i
.tm
.opcode_modifier
.vex
3457 || i
.tm
.opcode_modifier
.evex
)
3458 && i
.operands
<= 4)));
3460 exp
= &im_expressions
[i
.imm_operands
++];
3461 i
.op
[i
.operands
].imms
= exp
;
3462 i
.types
[i
.operands
] = imm8
;
3464 exp
->X_op
= O_constant
;
3465 exp
->X_add_number
= i
.tm
.extension_opcode
;
3466 i
.tm
.extension_opcode
= None
;
3473 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3478 as_bad (_("invalid instruction `%s' after `%s'"),
3479 i
.tm
.name
, i
.hle_prefix
);
3482 if (i
.prefix
[LOCK_PREFIX
])
3484 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3488 case HLEPrefixRelease
:
3489 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3491 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3495 if (i
.mem_operands
== 0
3496 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3498 as_bad (_("memory destination needed for instruction `%s'"
3499 " after `xrelease'"), i
.tm
.name
);
3506 /* This is the guts of the machine-dependent assembler. LINE points to a
3507 machine dependent instruction. This function is supposed to emit
3508 the frags/bytes it assembles to. */
3511 md_assemble (char *line
)
3514 char mnemonic
[MAX_MNEM_SIZE
];
3515 const insn_template
*t
;
3517 /* Initialize globals. */
3518 memset (&i
, '\0', sizeof (i
));
3519 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3520 i
.reloc
[j
] = NO_RELOC
;
3521 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3522 memset (im_expressions
, '\0', sizeof (im_expressions
));
3523 save_stack_p
= save_stack
;
3525 /* First parse an instruction mnemonic & call i386_operand for the operands.
3526 We assume that the scrubber has arranged it so that line[0] is the valid
3527 start of a (possibly prefixed) mnemonic. */
3529 line
= parse_insn (line
, mnemonic
);
3533 line
= parse_operands (line
, mnemonic
);
3538 /* Now we've parsed the mnemonic into a set of templates, and have the
3539 operands at hand. */
3541 /* All intel opcodes have reversed operands except for "bound" and
3542 "enter". We also don't reverse intersegment "jmp" and "call"
3543 instructions with 2 immediate operands so that the immediate segment
3544 precedes the offset, as it does when in AT&T mode. */
3547 && (strcmp (mnemonic
, "bound") != 0)
3548 && (strcmp (mnemonic
, "invlpga") != 0)
3549 && !(operand_type_check (i
.types
[0], imm
)
3550 && operand_type_check (i
.types
[1], imm
)))
3553 /* The order of the immediates should be reversed
3554 for 2 immediates extrq and insertq instructions */
3555 if (i
.imm_operands
== 2
3556 && (strcmp (mnemonic
, "extrq") == 0
3557 || strcmp (mnemonic
, "insertq") == 0))
3558 swap_2_operands (0, 1);
3563 /* Don't optimize displacement for movabs since it only takes 64bit
3566 && i
.disp_encoding
!= disp_encoding_32bit
3567 && (flag_code
!= CODE_64BIT
3568 || strcmp (mnemonic
, "movabs") != 0))
3571 /* Next, we find a template that matches the given insn,
3572 making sure the overlap of the given operands types is consistent
3573 with the template operand types. */
3575 if (!(t
= match_template ()))
3578 if (sse_check
!= check_none
3579 && !i
.tm
.opcode_modifier
.noavx
3580 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3581 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3582 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3583 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3584 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3585 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3587 (sse_check
== check_warning
3589 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3592 /* Zap movzx and movsx suffix. The suffix has been set from
3593 "word ptr" or "byte ptr" on the source operand in Intel syntax
3594 or extracted from mnemonic in AT&T syntax. But we'll use
3595 the destination register to choose the suffix for encoding. */
3596 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3598 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3599 there is no suffix, the default will be byte extension. */
3600 if (i
.reg_operands
!= 2
3603 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3608 if (i
.tm
.opcode_modifier
.fwait
)
3609 if (!add_prefix (FWAIT_OPCODE
))
3612 /* Check if REP prefix is OK. */
3613 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3615 as_bad (_("invalid instruction `%s' after `%s'"),
3616 i
.tm
.name
, i
.rep_prefix
);
3620 /* Check for lock without a lockable instruction. Destination operand
3621 must be memory unless it is xchg (0x86). */
3622 if (i
.prefix
[LOCK_PREFIX
]
3623 && (!i
.tm
.opcode_modifier
.islockable
3624 || i
.mem_operands
== 0
3625 || (i
.tm
.base_opcode
!= 0x86
3626 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3628 as_bad (_("expecting lockable instruction after `lock'"));
3632 /* Check if HLE prefix is OK. */
3633 if (i
.hle_prefix
&& !check_hle ())
3636 /* Check BND prefix. */
3637 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3638 as_bad (_("expecting valid branch instruction after `bnd'"));
3640 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3641 && flag_code
== CODE_64BIT
3642 && i
.prefix
[ADDR_PREFIX
])
3643 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3645 /* Insert BND prefix. */
3647 && i
.tm
.opcode_modifier
.bndprefixok
3648 && !i
.prefix
[BND_PREFIX
])
3649 add_prefix (BND_PREFIX_OPCODE
);
3651 /* Check string instruction segment overrides. */
3652 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3654 if (!check_string ())
3656 i
.disp_operands
= 0;
3659 if (!process_suffix ())
3662 /* Update operand types. */
3663 for (j
= 0; j
< i
.operands
; j
++)
3664 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3666 /* Make still unresolved immediate matches conform to size of immediate
3667 given in i.suffix. */
3668 if (!finalize_imm ())
3671 if (i
.types
[0].bitfield
.imm1
)
3672 i
.imm_operands
= 0; /* kludge for shift insns. */
3674 /* We only need to check those implicit registers for instructions
3675 with 3 operands or less. */
3676 if (i
.operands
<= 3)
3677 for (j
= 0; j
< i
.operands
; j
++)
3678 if (i
.types
[j
].bitfield
.inoutportreg
3679 || i
.types
[j
].bitfield
.shiftcount
3680 || i
.types
[j
].bitfield
.acc
3681 || i
.types
[j
].bitfield
.floatacc
)
3684 /* ImmExt should be processed after SSE2AVX. */
3685 if (!i
.tm
.opcode_modifier
.sse2avx
3686 && i
.tm
.opcode_modifier
.immext
)
3689 /* For insns with operands there are more diddles to do to the opcode. */
3692 if (!process_operands ())
3695 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3697 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3698 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3701 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3703 if (flag_code
== CODE_16BIT
)
3705 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3710 if (i
.tm
.opcode_modifier
.vex
)
3711 build_vex_prefix (t
);
3713 build_evex_prefix ();
3716 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3717 instructions may define INT_OPCODE as well, so avoid this corner
3718 case for those instructions that use MODRM. */
3719 if (i
.tm
.base_opcode
== INT_OPCODE
3720 && !i
.tm
.opcode_modifier
.modrm
3721 && i
.op
[0].imms
->X_add_number
== 3)
3723 i
.tm
.base_opcode
= INT3_OPCODE
;
3727 if ((i
.tm
.opcode_modifier
.jump
3728 || i
.tm
.opcode_modifier
.jumpbyte
3729 || i
.tm
.opcode_modifier
.jumpdword
)
3730 && i
.op
[0].disps
->X_op
== O_constant
)
3732 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3733 the absolute address given by the constant. Since ix86 jumps and
3734 calls are pc relative, we need to generate a reloc. */
3735 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3736 i
.op
[0].disps
->X_op
= O_symbol
;
3739 if (i
.tm
.opcode_modifier
.rex64
)
3742 /* For 8 bit registers we need an empty rex prefix. Also if the
3743 instruction already has a prefix, we need to convert old
3744 registers to new ones. */
3746 if ((i
.types
[0].bitfield
.reg8
3747 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3748 || (i
.types
[1].bitfield
.reg8
3749 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3750 || ((i
.types
[0].bitfield
.reg8
3751 || i
.types
[1].bitfield
.reg8
)
3756 i
.rex
|= REX_OPCODE
;
3757 for (x
= 0; x
< 2; x
++)
3759 /* Look for 8 bit operand that uses old registers. */
3760 if (i
.types
[x
].bitfield
.reg8
3761 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3763 /* In case it is "hi" register, give up. */
3764 if (i
.op
[x
].regs
->reg_num
> 3)
3765 as_bad (_("can't encode register '%s%s' in an "
3766 "instruction requiring REX prefix."),
3767 register_prefix
, i
.op
[x
].regs
->reg_name
);
3769 /* Otherwise it is equivalent to the extended register.
3770 Since the encoding doesn't change this is merely
3771 cosmetic cleanup for debug output. */
3773 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3779 add_prefix (REX_OPCODE
| i
.rex
);
3781 /* We are ready to output the insn. */
3786 parse_insn (char *line
, char *mnemonic
)
3789 char *token_start
= l
;
3792 const insn_template
*t
;
3798 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3803 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3805 as_bad (_("no such instruction: `%s'"), token_start
);
3810 if (!is_space_char (*l
)
3811 && *l
!= END_OF_INSN
3813 || (*l
!= PREFIX_SEPARATOR
3816 as_bad (_("invalid character %s in mnemonic"),
3817 output_invalid (*l
));
3820 if (token_start
== l
)
3822 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3823 as_bad (_("expecting prefix; got nothing"));
3825 as_bad (_("expecting mnemonic; got nothing"));
3829 /* Look up instruction (or prefix) via hash table. */
3830 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3832 if (*l
!= END_OF_INSN
3833 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3834 && current_templates
3835 && current_templates
->start
->opcode_modifier
.isprefix
)
3837 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3839 as_bad ((flag_code
!= CODE_64BIT
3840 ? _("`%s' is only supported in 64-bit mode")
3841 : _("`%s' is not supported in 64-bit mode")),
3842 current_templates
->start
->name
);
3845 /* If we are in 16-bit mode, do not allow addr16 or data16.
3846 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3847 if ((current_templates
->start
->opcode_modifier
.size16
3848 || current_templates
->start
->opcode_modifier
.size32
)
3849 && flag_code
!= CODE_64BIT
3850 && (current_templates
->start
->opcode_modifier
.size32
3851 ^ (flag_code
== CODE_16BIT
)))
3853 as_bad (_("redundant %s prefix"),
3854 current_templates
->start
->name
);
3857 /* Add prefix, checking for repeated prefixes. */
3858 switch (add_prefix (current_templates
->start
->base_opcode
))
3863 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3864 i
.hle_prefix
= current_templates
->start
->name
;
3865 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3866 i
.bnd_prefix
= current_templates
->start
->name
;
3868 i
.rep_prefix
= current_templates
->start
->name
;
3873 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3880 if (!current_templates
)
3882 /* Check if we should swap operand or force 32bit displacement in
3884 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3886 else if (mnem_p
- 3 == dot_p
3889 i
.disp_encoding
= disp_encoding_8bit
;
3890 else if (mnem_p
- 4 == dot_p
3894 i
.disp_encoding
= disp_encoding_32bit
;
3899 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3902 if (!current_templates
)
3905 /* See if we can get a match by trimming off a suffix. */
3908 case WORD_MNEM_SUFFIX
:
3909 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3910 i
.suffix
= SHORT_MNEM_SUFFIX
;
3912 case BYTE_MNEM_SUFFIX
:
3913 case QWORD_MNEM_SUFFIX
:
3914 i
.suffix
= mnem_p
[-1];
3916 current_templates
= (const templates
*) hash_find (op_hash
,
3919 case SHORT_MNEM_SUFFIX
:
3920 case LONG_MNEM_SUFFIX
:
3923 i
.suffix
= mnem_p
[-1];
3925 current_templates
= (const templates
*) hash_find (op_hash
,
3934 if (intel_float_operand (mnemonic
) == 1)
3935 i
.suffix
= SHORT_MNEM_SUFFIX
;
3937 i
.suffix
= LONG_MNEM_SUFFIX
;
3939 current_templates
= (const templates
*) hash_find (op_hash
,
3944 if (!current_templates
)
3946 as_bad (_("no such instruction: `%s'"), token_start
);
3951 if (current_templates
->start
->opcode_modifier
.jump
3952 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3954 /* Check for a branch hint. We allow ",pt" and ",pn" for
3955 predict taken and predict not taken respectively.
3956 I'm not sure that branch hints actually do anything on loop
3957 and jcxz insns (JumpByte) for current Pentium4 chips. They
3958 may work in the future and it doesn't hurt to accept them
3960 if (l
[0] == ',' && l
[1] == 'p')
3964 if (!add_prefix (DS_PREFIX_OPCODE
))
3968 else if (l
[2] == 'n')
3970 if (!add_prefix (CS_PREFIX_OPCODE
))
3976 /* Any other comma loses. */
3979 as_bad (_("invalid character %s in mnemonic"),
3980 output_invalid (*l
));
3984 /* Check if instruction is supported on specified architecture. */
3986 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3988 supported
|= cpu_flags_match (t
);
3989 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3993 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3995 as_bad (flag_code
== CODE_64BIT
3996 ? _("`%s' is not supported in 64-bit mode")
3997 : _("`%s' is only supported in 64-bit mode"),
3998 current_templates
->start
->name
);
4001 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
4003 as_bad (_("`%s' is not supported on `%s%s'"),
4004 current_templates
->start
->name
,
4005 cpu_arch_name
? cpu_arch_name
: default_arch
,
4006 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4011 if (!cpu_arch_flags
.bitfield
.cpui386
4012 && (flag_code
!= CODE_16BIT
))
4014 as_warn (_("use .code16 to ensure correct addressing mode"));
4021 parse_operands (char *l
, const char *mnemonic
)
4025 /* 1 if operand is pending after ','. */
4026 unsigned int expecting_operand
= 0;
4028 /* Non-zero if operand parens not balanced. */
4029 unsigned int paren_not_balanced
;
4031 while (*l
!= END_OF_INSN
)
4033 /* Skip optional white space before operand. */
4034 if (is_space_char (*l
))
4036 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4038 as_bad (_("invalid character %s before operand %d"),
4039 output_invalid (*l
),
4043 token_start
= l
; /* After white space. */
4044 paren_not_balanced
= 0;
4045 while (paren_not_balanced
|| *l
!= ',')
4047 if (*l
== END_OF_INSN
)
4049 if (paren_not_balanced
)
4052 as_bad (_("unbalanced parenthesis in operand %d."),
4055 as_bad (_("unbalanced brackets in operand %d."),
4060 break; /* we are done */
4062 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4064 as_bad (_("invalid character %s in operand %d"),
4065 output_invalid (*l
),
4072 ++paren_not_balanced
;
4074 --paren_not_balanced
;
4079 ++paren_not_balanced
;
4081 --paren_not_balanced
;
4085 if (l
!= token_start
)
4086 { /* Yes, we've read in another operand. */
4087 unsigned int operand_ok
;
4088 this_operand
= i
.operands
++;
4089 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4090 if (i
.operands
> MAX_OPERANDS
)
4092 as_bad (_("spurious operands; (%d operands/instruction max)"),
4096 /* Now parse operand adding info to 'i' as we go along. */
4097 END_STRING_AND_SAVE (l
);
4101 i386_intel_operand (token_start
,
4102 intel_float_operand (mnemonic
));
4104 operand_ok
= i386_att_operand (token_start
);
4106 RESTORE_END_STRING (l
);
4112 if (expecting_operand
)
4114 expecting_operand_after_comma
:
4115 as_bad (_("expecting operand after ','; got nothing"));
4120 as_bad (_("expecting operand before ','; got nothing"));
4125 /* Now *l must be either ',' or END_OF_INSN. */
4128 if (*++l
== END_OF_INSN
)
4130 /* Just skip it, if it's \n complain. */
4131 goto expecting_operand_after_comma
;
4133 expecting_operand
= 1;
4140 swap_2_operands (int xchg1
, int xchg2
)
4142 union i386_op temp_op
;
4143 i386_operand_type temp_type
;
4144 enum bfd_reloc_code_real temp_reloc
;
4146 temp_type
= i
.types
[xchg2
];
4147 i
.types
[xchg2
] = i
.types
[xchg1
];
4148 i
.types
[xchg1
] = temp_type
;
4149 temp_op
= i
.op
[xchg2
];
4150 i
.op
[xchg2
] = i
.op
[xchg1
];
4151 i
.op
[xchg1
] = temp_op
;
4152 temp_reloc
= i
.reloc
[xchg2
];
4153 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4154 i
.reloc
[xchg1
] = temp_reloc
;
4158 if (i
.mask
->operand
== xchg1
)
4159 i
.mask
->operand
= xchg2
;
4160 else if (i
.mask
->operand
== xchg2
)
4161 i
.mask
->operand
= xchg1
;
4165 if (i
.broadcast
->operand
== xchg1
)
4166 i
.broadcast
->operand
= xchg2
;
4167 else if (i
.broadcast
->operand
== xchg2
)
4168 i
.broadcast
->operand
= xchg1
;
4172 if (i
.rounding
->operand
== xchg1
)
4173 i
.rounding
->operand
= xchg2
;
4174 else if (i
.rounding
->operand
== xchg2
)
4175 i
.rounding
->operand
= xchg1
;
4180 swap_operands (void)
4186 swap_2_operands (1, i
.operands
- 2);
4189 swap_2_operands (0, i
.operands
- 1);
4195 if (i
.mem_operands
== 2)
4197 const seg_entry
*temp_seg
;
4198 temp_seg
= i
.seg
[0];
4199 i
.seg
[0] = i
.seg
[1];
4200 i
.seg
[1] = temp_seg
;
4204 /* Try to ensure constant immediates are represented in the smallest
4209 char guess_suffix
= 0;
4213 guess_suffix
= i
.suffix
;
4214 else if (i
.reg_operands
)
4216 /* Figure out a suffix from the last register operand specified.
4217 We can't do this properly yet, ie. excluding InOutPortReg,
4218 but the following works for instructions with immediates.
4219 In any case, we can't set i.suffix yet. */
4220 for (op
= i
.operands
; --op
>= 0;)
4221 if (i
.types
[op
].bitfield
.reg8
)
4223 guess_suffix
= BYTE_MNEM_SUFFIX
;
4226 else if (i
.types
[op
].bitfield
.reg16
)
4228 guess_suffix
= WORD_MNEM_SUFFIX
;
4231 else if (i
.types
[op
].bitfield
.reg32
)
4233 guess_suffix
= LONG_MNEM_SUFFIX
;
4236 else if (i
.types
[op
].bitfield
.reg64
)
4238 guess_suffix
= QWORD_MNEM_SUFFIX
;
4242 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4243 guess_suffix
= WORD_MNEM_SUFFIX
;
4245 for (op
= i
.operands
; --op
>= 0;)
4246 if (operand_type_check (i
.types
[op
], imm
))
4248 switch (i
.op
[op
].imms
->X_op
)
4251 /* If a suffix is given, this operand may be shortened. */
4252 switch (guess_suffix
)
4254 case LONG_MNEM_SUFFIX
:
4255 i
.types
[op
].bitfield
.imm32
= 1;
4256 i
.types
[op
].bitfield
.imm64
= 1;
4258 case WORD_MNEM_SUFFIX
:
4259 i
.types
[op
].bitfield
.imm16
= 1;
4260 i
.types
[op
].bitfield
.imm32
= 1;
4261 i
.types
[op
].bitfield
.imm32s
= 1;
4262 i
.types
[op
].bitfield
.imm64
= 1;
4264 case BYTE_MNEM_SUFFIX
:
4265 i
.types
[op
].bitfield
.imm8
= 1;
4266 i
.types
[op
].bitfield
.imm8s
= 1;
4267 i
.types
[op
].bitfield
.imm16
= 1;
4268 i
.types
[op
].bitfield
.imm32
= 1;
4269 i
.types
[op
].bitfield
.imm32s
= 1;
4270 i
.types
[op
].bitfield
.imm64
= 1;
4274 /* If this operand is at most 16 bits, convert it
4275 to a signed 16 bit number before trying to see
4276 whether it will fit in an even smaller size.
4277 This allows a 16-bit operand such as $0xffe0 to
4278 be recognised as within Imm8S range. */
4279 if ((i
.types
[op
].bitfield
.imm16
)
4280 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4282 i
.op
[op
].imms
->X_add_number
=
4283 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4286 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4287 if ((i
.types
[op
].bitfield
.imm32
)
4288 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4291 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4292 ^ ((offsetT
) 1 << 31))
4293 - ((offsetT
) 1 << 31));
4297 = operand_type_or (i
.types
[op
],
4298 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4300 /* We must avoid matching of Imm32 templates when 64bit
4301 only immediate is available. */
4302 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4303 i
.types
[op
].bitfield
.imm32
= 0;
4310 /* Symbols and expressions. */
4312 /* Convert symbolic operand to proper sizes for matching, but don't
4313 prevent matching a set of insns that only supports sizes other
4314 than those matching the insn suffix. */
4316 i386_operand_type mask
, allowed
;
4317 const insn_template
*t
;
4319 operand_type_set (&mask
, 0);
4320 operand_type_set (&allowed
, 0);
4322 for (t
= current_templates
->start
;
4323 t
< current_templates
->end
;
4325 allowed
= operand_type_or (allowed
,
4326 t
->operand_types
[op
]);
4327 switch (guess_suffix
)
4329 case QWORD_MNEM_SUFFIX
:
4330 mask
.bitfield
.imm64
= 1;
4331 mask
.bitfield
.imm32s
= 1;
4333 case LONG_MNEM_SUFFIX
:
4334 mask
.bitfield
.imm32
= 1;
4336 case WORD_MNEM_SUFFIX
:
4337 mask
.bitfield
.imm16
= 1;
4339 case BYTE_MNEM_SUFFIX
:
4340 mask
.bitfield
.imm8
= 1;
4345 allowed
= operand_type_and (mask
, allowed
);
4346 if (!operand_type_all_zero (&allowed
))
4347 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4354 /* Try to use the smallest displacement type too. */
4356 optimize_disp (void)
4360 for (op
= i
.operands
; --op
>= 0;)
4361 if (operand_type_check (i
.types
[op
], disp
))
4363 if (i
.op
[op
].disps
->X_op
== O_constant
)
4365 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4367 if (i
.types
[op
].bitfield
.disp16
4368 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4370 /* If this operand is at most 16 bits, convert
4371 to a signed 16 bit number and don't use 64bit
4373 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4374 i
.types
[op
].bitfield
.disp64
= 0;
4377 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4378 if (i
.types
[op
].bitfield
.disp32
4379 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4381 /* If this operand is at most 32 bits, convert
4382 to a signed 32 bit number and don't use 64bit
4384 op_disp
&= (((offsetT
) 2 << 31) - 1);
4385 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4386 i
.types
[op
].bitfield
.disp64
= 0;
4389 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4391 i
.types
[op
].bitfield
.disp8
= 0;
4392 i
.types
[op
].bitfield
.disp16
= 0;
4393 i
.types
[op
].bitfield
.disp32
= 0;
4394 i
.types
[op
].bitfield
.disp32s
= 0;
4395 i
.types
[op
].bitfield
.disp64
= 0;
4399 else if (flag_code
== CODE_64BIT
)
4401 if (fits_in_signed_long (op_disp
))
4403 i
.types
[op
].bitfield
.disp64
= 0;
4404 i
.types
[op
].bitfield
.disp32s
= 1;
4406 if (i
.prefix
[ADDR_PREFIX
]
4407 && fits_in_unsigned_long (op_disp
))
4408 i
.types
[op
].bitfield
.disp32
= 1;
4410 if ((i
.types
[op
].bitfield
.disp32
4411 || i
.types
[op
].bitfield
.disp32s
4412 || i
.types
[op
].bitfield
.disp16
)
4413 && fits_in_signed_byte (op_disp
))
4414 i
.types
[op
].bitfield
.disp8
= 1;
4416 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4417 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4419 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4420 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4421 i
.types
[op
].bitfield
.disp8
= 0;
4422 i
.types
[op
].bitfield
.disp16
= 0;
4423 i
.types
[op
].bitfield
.disp32
= 0;
4424 i
.types
[op
].bitfield
.disp32s
= 0;
4425 i
.types
[op
].bitfield
.disp64
= 0;
4428 /* We only support 64bit displacement on constants. */
4429 i
.types
[op
].bitfield
.disp64
= 0;
4433 /* Check if operands are valid for the instruction. */
4436 check_VecOperands (const insn_template
*t
)
4440 /* Without VSIB byte, we can't have a vector register for index. */
4441 if (!t
->opcode_modifier
.vecsib
4443 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4444 || i
.index_reg
->reg_type
.bitfield
.regymm
4445 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4447 i
.error
= unsupported_vector_index_register
;
4451 /* Check if default mask is allowed. */
4452 if (t
->opcode_modifier
.nodefmask
4453 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4455 i
.error
= no_default_mask
;
4459 /* For VSIB byte, we need a vector register for index, and all vector
4460 registers must be distinct. */
4461 if (t
->opcode_modifier
.vecsib
)
4464 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4465 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4466 || (t
->opcode_modifier
.vecsib
== VecSIB256
4467 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4468 || (t
->opcode_modifier
.vecsib
== VecSIB512
4469 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4471 i
.error
= invalid_vsib_address
;
4475 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4476 if (i
.reg_operands
== 2 && !i
.mask
)
4478 gas_assert (i
.types
[0].bitfield
.regxmm
4479 || i
.types
[0].bitfield
.regymm
);
4480 gas_assert (i
.types
[2].bitfield
.regxmm
4481 || i
.types
[2].bitfield
.regymm
);
4482 if (operand_check
== check_none
)
4484 if (register_number (i
.op
[0].regs
)
4485 != register_number (i
.index_reg
)
4486 && register_number (i
.op
[2].regs
)
4487 != register_number (i
.index_reg
)
4488 && register_number (i
.op
[0].regs
)
4489 != register_number (i
.op
[2].regs
))
4491 if (operand_check
== check_error
)
4493 i
.error
= invalid_vector_register_set
;
4496 as_warn (_("mask, index, and destination registers should be distinct"));
4498 else if (i
.reg_operands
== 1 && i
.mask
)
4500 if ((i
.types
[1].bitfield
.regymm
4501 || i
.types
[1].bitfield
.regzmm
)
4502 && (register_number (i
.op
[1].regs
)
4503 == register_number (i
.index_reg
)))
4505 if (operand_check
== check_error
)
4507 i
.error
= invalid_vector_register_set
;
4510 if (operand_check
!= check_none
)
4511 as_warn (_("index and destination registers should be distinct"));
4516 /* Check if broadcast is supported by the instruction and is applied
4517 to the memory operand. */
4520 int broadcasted_opnd_size
;
4522 /* Check if specified broadcast is supported in this instruction,
4523 and it's applied to memory operand of DWORD or QWORD type,
4524 depending on VecESize. */
4525 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4526 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4527 || (t
->opcode_modifier
.vecesize
== 0
4528 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4529 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4530 || (t
->opcode_modifier
.vecesize
== 1
4531 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4532 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4535 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4536 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4537 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4538 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4539 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4540 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4541 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4542 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4543 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4547 if ((broadcasted_opnd_size
== 256
4548 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4549 || (broadcasted_opnd_size
== 512
4550 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4553 i
.error
= unsupported_broadcast
;
4557 /* If broadcast is supported in this instruction, we need to check if
4558 operand of one-element size isn't specified without broadcast. */
4559 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4561 /* Find memory operand. */
4562 for (op
= 0; op
< i
.operands
; op
++)
4563 if (operand_type_check (i
.types
[op
], anymem
))
4565 gas_assert (op
< i
.operands
);
4566 /* Check size of the memory operand. */
4567 if ((t
->opcode_modifier
.vecesize
== 0
4568 && i
.types
[op
].bitfield
.dword
)
4569 || (t
->opcode_modifier
.vecesize
== 1
4570 && i
.types
[op
].bitfield
.qword
))
4572 i
.error
= broadcast_needed
;
4577 /* Check if requested masking is supported. */
4579 && (!t
->opcode_modifier
.masking
4581 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4583 i
.error
= unsupported_masking
;
4587 /* Check if masking is applied to dest operand. */
4588 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4590 i
.error
= mask_not_on_destination
;
4597 if ((i
.rounding
->type
!= saeonly
4598 && !t
->opcode_modifier
.staticrounding
)
4599 || (i
.rounding
->type
== saeonly
4600 && (t
->opcode_modifier
.staticrounding
4601 || !t
->opcode_modifier
.sae
)))
4603 i
.error
= unsupported_rc_sae
;
4606 /* If the instruction has several immediate operands and one of
4607 them is rounding, the rounding operand should be the last
4608 immediate operand. */
4609 if (i
.imm_operands
> 1
4610 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4612 i
.error
= rc_sae_operand_not_last_imm
;
4617 /* Check vector Disp8 operand. */
4618 if (t
->opcode_modifier
.disp8memshift
)
4621 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4623 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4625 for (op
= 0; op
< i
.operands
; op
++)
4626 if (operand_type_check (i
.types
[op
], disp
)
4627 && i
.op
[op
].disps
->X_op
== O_constant
)
4629 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4631 = (i
.disp_encoding
!= disp_encoding_32bit
4632 && fits_in_vec_disp8 (value
));
4633 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4636 i
.types
[op
].bitfield
.vec_disp8
= 1;
4639 /* Vector insn can only have Vec_Disp8/Disp32 in
4640 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4642 i
.types
[op
].bitfield
.disp8
= 0;
4643 if (flag_code
!= CODE_16BIT
)
4644 i
.types
[op
].bitfield
.disp16
= 0;
4647 else if (flag_code
!= CODE_16BIT
)
4649 /* One form of this instruction supports vector Disp8.
4650 Try vector Disp8 if we need to use Disp32. */
4651 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4653 i
.error
= try_vector_disp8
;
4665 /* Check if operands are valid for the instruction. Update VEX
4669 VEX_check_operands (const insn_template
*t
)
4671 /* VREX is only valid with EVEX prefix. */
4672 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4674 i
.error
= invalid_register_operand
;
4678 if (!t
->opcode_modifier
.vex
)
4681 /* Only check VEX_Imm4, which must be the first operand. */
4682 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4684 if (i
.op
[0].imms
->X_op
!= O_constant
4685 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4691 /* Turn off Imm8 so that update_imm won't complain. */
4692 i
.types
[0] = vec_imm4
;
4698 static const insn_template
*
4699 match_template (void)
4701 /* Points to template once we've found it. */
4702 const insn_template
*t
;
4703 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4704 i386_operand_type overlap4
;
4705 unsigned int found_reverse_match
;
4706 i386_opcode_modifier suffix_check
;
4707 i386_operand_type operand_types
[MAX_OPERANDS
];
4708 int addr_prefix_disp
;
4710 unsigned int found_cpu_match
;
4711 unsigned int check_register
;
4712 enum i386_error specific_error
= 0;
4714 #if MAX_OPERANDS != 5
4715 # error "MAX_OPERANDS must be 5."
4718 found_reverse_match
= 0;
4719 addr_prefix_disp
= -1;
4721 memset (&suffix_check
, 0, sizeof (suffix_check
));
4722 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4723 suffix_check
.no_bsuf
= 1;
4724 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4725 suffix_check
.no_wsuf
= 1;
4726 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4727 suffix_check
.no_ssuf
= 1;
4728 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4729 suffix_check
.no_lsuf
= 1;
4730 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4731 suffix_check
.no_qsuf
= 1;
4732 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4733 suffix_check
.no_ldsuf
= 1;
4735 /* Must have right number of operands. */
4736 i
.error
= number_of_operands_mismatch
;
4738 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4740 addr_prefix_disp
= -1;
4742 if (i
.operands
!= t
->operands
)
4745 /* Check processor support. */
4746 i
.error
= unsupported
;
4747 found_cpu_match
= (cpu_flags_match (t
)
4748 == CPU_FLAGS_PERFECT_MATCH
);
4749 if (!found_cpu_match
)
4752 /* Check old gcc support. */
4753 i
.error
= old_gcc_only
;
4754 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4757 /* Check AT&T mnemonic. */
4758 i
.error
= unsupported_with_intel_mnemonic
;
4759 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4762 /* Check AT&T/Intel syntax. */
4763 i
.error
= unsupported_syntax
;
4764 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4765 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4768 /* Check the suffix, except for some instructions in intel mode. */
4769 i
.error
= invalid_instruction_suffix
;
4770 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4771 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4772 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4773 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4774 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4775 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4776 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4779 if (!operand_size_match (t
))
4782 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4783 operand_types
[j
] = t
->operand_types
[j
];
4785 /* In general, don't allow 64-bit operands in 32-bit mode. */
4786 if (i
.suffix
== QWORD_MNEM_SUFFIX
4787 && flag_code
!= CODE_64BIT
4789 ? (!t
->opcode_modifier
.ignoresize
4790 && !intel_float_operand (t
->name
))
4791 : intel_float_operand (t
->name
) != 2)
4792 && ((!operand_types
[0].bitfield
.regmmx
4793 && !operand_types
[0].bitfield
.regxmm
4794 && !operand_types
[0].bitfield
.regymm
4795 && !operand_types
[0].bitfield
.regzmm
)
4796 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4797 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4798 && operand_types
[t
->operands
> 1].bitfield
.regymm
4799 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4800 && (t
->base_opcode
!= 0x0fc7
4801 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4804 /* In general, don't allow 32-bit operands on pre-386. */
4805 else if (i
.suffix
== LONG_MNEM_SUFFIX
4806 && !cpu_arch_flags
.bitfield
.cpui386
4808 ? (!t
->opcode_modifier
.ignoresize
4809 && !intel_float_operand (t
->name
))
4810 : intel_float_operand (t
->name
) != 2)
4811 && ((!operand_types
[0].bitfield
.regmmx
4812 && !operand_types
[0].bitfield
.regxmm
)
4813 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4814 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4817 /* Do not verify operands when there are none. */
4821 /* We've found a match; break out of loop. */
4825 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4826 into Disp32/Disp16/Disp32 operand. */
4827 if (i
.prefix
[ADDR_PREFIX
] != 0)
4829 /* There should be only one Disp operand. */
4833 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4835 if (operand_types
[j
].bitfield
.disp16
)
4837 addr_prefix_disp
= j
;
4838 operand_types
[j
].bitfield
.disp32
= 1;
4839 operand_types
[j
].bitfield
.disp16
= 0;
4845 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4847 if (operand_types
[j
].bitfield
.disp32
)
4849 addr_prefix_disp
= j
;
4850 operand_types
[j
].bitfield
.disp32
= 0;
4851 operand_types
[j
].bitfield
.disp16
= 1;
4857 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4859 if (operand_types
[j
].bitfield
.disp64
)
4861 addr_prefix_disp
= j
;
4862 operand_types
[j
].bitfield
.disp64
= 0;
4863 operand_types
[j
].bitfield
.disp32
= 1;
4871 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4872 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
4875 /* We check register size if needed. */
4876 check_register
= t
->opcode_modifier
.checkregsize
;
4877 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4878 switch (t
->operands
)
4881 if (!operand_type_match (overlap0
, i
.types
[0]))
4885 /* xchg %eax, %eax is a special case. It is an aliase for nop
4886 only in 32bit mode and we can use opcode 0x90. In 64bit
4887 mode, we can't use 0x90 for xchg %eax, %eax since it should
4888 zero-extend %eax to %rax. */
4889 if (flag_code
== CODE_64BIT
4890 && t
->base_opcode
== 0x90
4891 && operand_type_equal (&i
.types
[0], &acc32
)
4892 && operand_type_equal (&i
.types
[1], &acc32
))
4896 /* If we swap operand in encoding, we either match
4897 the next one or reverse direction of operands. */
4898 if (t
->opcode_modifier
.s
)
4900 else if (t
->opcode_modifier
.d
)
4905 /* If we swap operand in encoding, we match the next one. */
4906 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4910 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4911 if (!operand_type_match (overlap0
, i
.types
[0])
4912 || !operand_type_match (overlap1
, i
.types
[1])
4914 && !operand_type_register_match (overlap0
, i
.types
[0],
4916 overlap1
, i
.types
[1],
4919 /* Check if other direction is valid ... */
4920 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4924 /* Try reversing direction of operands. */
4925 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4926 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4927 if (!operand_type_match (overlap0
, i
.types
[0])
4928 || !operand_type_match (overlap1
, i
.types
[1])
4930 && !operand_type_register_match (overlap0
,
4937 /* Does not match either direction. */
4940 /* found_reverse_match holds which of D or FloatDR
4942 if (t
->opcode_modifier
.d
)
4943 found_reverse_match
= Opcode_D
;
4944 else if (t
->opcode_modifier
.floatd
)
4945 found_reverse_match
= Opcode_FloatD
;
4947 found_reverse_match
= 0;
4948 if (t
->opcode_modifier
.floatr
)
4949 found_reverse_match
|= Opcode_FloatR
;
4953 /* Found a forward 2 operand match here. */
4954 switch (t
->operands
)
4957 overlap4
= operand_type_and (i
.types
[4],
4960 overlap3
= operand_type_and (i
.types
[3],
4963 overlap2
= operand_type_and (i
.types
[2],
4968 switch (t
->operands
)
4971 if (!operand_type_match (overlap4
, i
.types
[4])
4972 || !operand_type_register_match (overlap3
,
4980 if (!operand_type_match (overlap3
, i
.types
[3])
4982 && !operand_type_register_match (overlap2
,
4990 /* Here we make use of the fact that there are no
4991 reverse match 3 operand instructions, and all 3
4992 operand instructions only need to be checked for
4993 register consistency between operands 2 and 3. */
4994 if (!operand_type_match (overlap2
, i
.types
[2])
4996 && !operand_type_register_match (overlap1
,
5006 /* Found either forward/reverse 2, 3 or 4 operand match here:
5007 slip through to break. */
5009 if (!found_cpu_match
)
5011 found_reverse_match
= 0;
5015 /* Check if vector and VEX operands are valid. */
5016 if (check_VecOperands (t
) || VEX_check_operands (t
))
5018 specific_error
= i
.error
;
5022 /* We've found a match; break out of loop. */
5026 if (t
== current_templates
->end
)
5028 /* We found no match. */
5029 const char *err_msg
;
5030 switch (specific_error
? specific_error
: i
.error
)
5034 case operand_size_mismatch
:
5035 err_msg
= _("operand size mismatch");
5037 case operand_type_mismatch
:
5038 err_msg
= _("operand type mismatch");
5040 case register_type_mismatch
:
5041 err_msg
= _("register type mismatch");
5043 case number_of_operands_mismatch
:
5044 err_msg
= _("number of operands mismatch");
5046 case invalid_instruction_suffix
:
5047 err_msg
= _("invalid instruction suffix");
5050 err_msg
= _("constant doesn't fit in 4 bits");
5053 err_msg
= _("only supported with old gcc");
5055 case unsupported_with_intel_mnemonic
:
5056 err_msg
= _("unsupported with Intel mnemonic");
5058 case unsupported_syntax
:
5059 err_msg
= _("unsupported syntax");
5062 as_bad (_("unsupported instruction `%s'"),
5063 current_templates
->start
->name
);
5065 case invalid_vsib_address
:
5066 err_msg
= _("invalid VSIB address");
5068 case invalid_vector_register_set
:
5069 err_msg
= _("mask, index, and destination registers must be distinct");
5071 case unsupported_vector_index_register
:
5072 err_msg
= _("unsupported vector index register");
5074 case unsupported_broadcast
:
5075 err_msg
= _("unsupported broadcast");
5077 case broadcast_not_on_src_operand
:
5078 err_msg
= _("broadcast not on source memory operand");
5080 case broadcast_needed
:
5081 err_msg
= _("broadcast is needed for operand of such type");
5083 case unsupported_masking
:
5084 err_msg
= _("unsupported masking");
5086 case mask_not_on_destination
:
5087 err_msg
= _("mask not on destination operand");
5089 case no_default_mask
:
5090 err_msg
= _("default mask isn't allowed");
5092 case unsupported_rc_sae
:
5093 err_msg
= _("unsupported static rounding/sae");
5095 case rc_sae_operand_not_last_imm
:
5097 err_msg
= _("RC/SAE operand must precede immediate operands");
5099 err_msg
= _("RC/SAE operand must follow immediate operands");
5101 case invalid_register_operand
:
5102 err_msg
= _("invalid register operand");
5105 as_bad (_("%s for `%s'"), err_msg
,
5106 current_templates
->start
->name
);
5110 if (!quiet_warnings
)
5113 && (i
.types
[0].bitfield
.jumpabsolute
5114 != operand_types
[0].bitfield
.jumpabsolute
))
5116 as_warn (_("indirect %s without `*'"), t
->name
);
5119 if (t
->opcode_modifier
.isprefix
5120 && t
->opcode_modifier
.ignoresize
)
5122 /* Warn them that a data or address size prefix doesn't
5123 affect assembly of the next line of code. */
5124 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5128 /* Copy the template we found. */
5131 if (addr_prefix_disp
!= -1)
5132 i
.tm
.operand_types
[addr_prefix_disp
]
5133 = operand_types
[addr_prefix_disp
];
5135 if (found_reverse_match
)
5137 /* If we found a reverse match we must alter the opcode
5138 direction bit. found_reverse_match holds bits to change
5139 (different for int & float insns). */
5141 i
.tm
.base_opcode
^= found_reverse_match
;
5143 i
.tm
.operand_types
[0] = operand_types
[1];
5144 i
.tm
.operand_types
[1] = operand_types
[0];
5153 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5154 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5156 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5158 as_bad (_("`%s' operand %d must use `%ses' segment"),
5164 /* There's only ever one segment override allowed per instruction.
5165 This instruction possibly has a legal segment override on the
5166 second operand, so copy the segment to where non-string
5167 instructions store it, allowing common code. */
5168 i
.seg
[0] = i
.seg
[1];
5170 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5172 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5174 as_bad (_("`%s' operand %d must use `%ses' segment"),
5185 process_suffix (void)
5187 /* If matched instruction specifies an explicit instruction mnemonic
5189 if (i
.tm
.opcode_modifier
.size16
)
5190 i
.suffix
= WORD_MNEM_SUFFIX
;
5191 else if (i
.tm
.opcode_modifier
.size32
)
5192 i
.suffix
= LONG_MNEM_SUFFIX
;
5193 else if (i
.tm
.opcode_modifier
.size64
)
5194 i
.suffix
= QWORD_MNEM_SUFFIX
;
5195 else if (i
.reg_operands
)
5197 /* If there's no instruction mnemonic suffix we try to invent one
5198 based on register operands. */
5201 /* We take i.suffix from the last register operand specified,
5202 Destination register type is more significant than source
5203 register type. crc32 in SSE4.2 prefers source register
5205 if (i
.tm
.base_opcode
== 0xf20f38f1)
5207 if (i
.types
[0].bitfield
.reg16
)
5208 i
.suffix
= WORD_MNEM_SUFFIX
;
5209 else if (i
.types
[0].bitfield
.reg32
)
5210 i
.suffix
= LONG_MNEM_SUFFIX
;
5211 else if (i
.types
[0].bitfield
.reg64
)
5212 i
.suffix
= QWORD_MNEM_SUFFIX
;
5214 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5216 if (i
.types
[0].bitfield
.reg8
)
5217 i
.suffix
= BYTE_MNEM_SUFFIX
;
5224 if (i
.tm
.base_opcode
== 0xf20f38f1
5225 || i
.tm
.base_opcode
== 0xf20f38f0)
5227 /* We have to know the operand size for crc32. */
5228 as_bad (_("ambiguous memory operand size for `%s`"),
5233 for (op
= i
.operands
; --op
>= 0;)
5234 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5236 if (i
.types
[op
].bitfield
.reg8
)
5238 i
.suffix
= BYTE_MNEM_SUFFIX
;
5241 else if (i
.types
[op
].bitfield
.reg16
)
5243 i
.suffix
= WORD_MNEM_SUFFIX
;
5246 else if (i
.types
[op
].bitfield
.reg32
)
5248 i
.suffix
= LONG_MNEM_SUFFIX
;
5251 else if (i
.types
[op
].bitfield
.reg64
)
5253 i
.suffix
= QWORD_MNEM_SUFFIX
;
5259 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5262 && i
.tm
.opcode_modifier
.ignoresize
5263 && i
.tm
.opcode_modifier
.no_bsuf
)
5265 else if (!check_byte_reg ())
5268 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5271 && i
.tm
.opcode_modifier
.ignoresize
5272 && i
.tm
.opcode_modifier
.no_lsuf
)
5274 else if (!check_long_reg ())
5277 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5280 && i
.tm
.opcode_modifier
.ignoresize
5281 && i
.tm
.opcode_modifier
.no_qsuf
)
5283 else if (!check_qword_reg ())
5286 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5289 && i
.tm
.opcode_modifier
.ignoresize
5290 && i
.tm
.opcode_modifier
.no_wsuf
)
5292 else if (!check_word_reg ())
5295 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5296 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5297 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5299 /* Skip if the instruction has x/y/z suffix. match_template
5300 should check if it is a valid suffix. */
5302 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5303 /* Do nothing if the instruction is going to ignore the prefix. */
5308 else if (i
.tm
.opcode_modifier
.defaultsize
5310 /* exclude fldenv/frstor/fsave/fstenv */
5311 && i
.tm
.opcode_modifier
.no_ssuf
)
5313 i
.suffix
= stackop_size
;
5315 else if (intel_syntax
5317 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5318 || i
.tm
.opcode_modifier
.jumpbyte
5319 || i
.tm
.opcode_modifier
.jumpintersegment
5320 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5321 && i
.tm
.extension_opcode
<= 3)))
5326 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5328 i
.suffix
= QWORD_MNEM_SUFFIX
;
5332 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5333 i
.suffix
= LONG_MNEM_SUFFIX
;
5336 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5337 i
.suffix
= WORD_MNEM_SUFFIX
;
5346 if (i
.tm
.opcode_modifier
.w
)
5348 as_bad (_("no instruction mnemonic suffix given and "
5349 "no register operands; can't size instruction"));
5355 unsigned int suffixes
;
5357 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5358 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5360 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5362 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5364 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5366 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5369 /* There are more than suffix matches. */
5370 if (i
.tm
.opcode_modifier
.w
5371 || ((suffixes
& (suffixes
- 1))
5372 && !i
.tm
.opcode_modifier
.defaultsize
5373 && !i
.tm
.opcode_modifier
.ignoresize
))
5375 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5381 /* Change the opcode based on the operand size given by i.suffix;
5382 We don't need to change things for byte insns. */
5385 && i
.suffix
!= BYTE_MNEM_SUFFIX
5386 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5387 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5388 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5390 /* It's not a byte, select word/dword operation. */
5391 if (i
.tm
.opcode_modifier
.w
)
5393 if (i
.tm
.opcode_modifier
.shortform
)
5394 i
.tm
.base_opcode
|= 8;
5396 i
.tm
.base_opcode
|= 1;
5399 /* Now select between word & dword operations via the operand
5400 size prefix, except for instructions that will ignore this
5402 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5404 /* The address size override prefix changes the size of the
5406 if ((flag_code
== CODE_32BIT
5407 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5408 || (flag_code
!= CODE_32BIT
5409 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5410 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5413 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5414 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5415 && !i
.tm
.opcode_modifier
.ignoresize
5416 && !i
.tm
.opcode_modifier
.floatmf
5417 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5418 || (flag_code
== CODE_64BIT
5419 && i
.tm
.opcode_modifier
.jumpbyte
)))
5421 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5423 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5424 prefix
= ADDR_PREFIX_OPCODE
;
5426 if (!add_prefix (prefix
))
5430 /* Set mode64 for an operand. */
5431 if (i
.suffix
== QWORD_MNEM_SUFFIX
5432 && flag_code
== CODE_64BIT
5433 && !i
.tm
.opcode_modifier
.norex64
)
5435 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5436 need rex64. cmpxchg8b is also a special case. */
5437 if (! (i
.operands
== 2
5438 && i
.tm
.base_opcode
== 0x90
5439 && i
.tm
.extension_opcode
== None
5440 && operand_type_equal (&i
.types
[0], &acc64
)
5441 && operand_type_equal (&i
.types
[1], &acc64
))
5442 && ! (i
.operands
== 1
5443 && i
.tm
.base_opcode
== 0xfc7
5444 && i
.tm
.extension_opcode
== 1
5445 && !operand_type_check (i
.types
[0], reg
)
5446 && operand_type_check (i
.types
[0], anymem
)))
5450 /* Size floating point instruction. */
5451 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5452 if (i
.tm
.opcode_modifier
.floatmf
)
5453 i
.tm
.base_opcode
^= 4;
5460 check_byte_reg (void)
5464 for (op
= i
.operands
; --op
>= 0;)
5466 /* If this is an eight bit register, it's OK. If it's the 16 or
5467 32 bit version of an eight bit register, we will just use the
5468 low portion, and that's OK too. */
5469 if (i
.types
[op
].bitfield
.reg8
)
5472 /* I/O port address operands are OK too. */
5473 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5476 /* crc32 doesn't generate this warning. */
5477 if (i
.tm
.base_opcode
== 0xf20f38f0)
5480 if ((i
.types
[op
].bitfield
.reg16
5481 || i
.types
[op
].bitfield
.reg32
5482 || i
.types
[op
].bitfield
.reg64
)
5483 && i
.op
[op
].regs
->reg_num
< 4
5484 /* Prohibit these changes in 64bit mode, since the lowering
5485 would be more complicated. */
5486 && flag_code
!= CODE_64BIT
)
5488 #if REGISTER_WARNINGS
5489 if (!quiet_warnings
)
5490 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5492 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5493 ? REGNAM_AL
- REGNAM_AX
5494 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5496 i
.op
[op
].regs
->reg_name
,
5501 /* Any other register is bad. */
5502 if (i
.types
[op
].bitfield
.reg16
5503 || i
.types
[op
].bitfield
.reg32
5504 || i
.types
[op
].bitfield
.reg64
5505 || i
.types
[op
].bitfield
.regmmx
5506 || i
.types
[op
].bitfield
.regxmm
5507 || i
.types
[op
].bitfield
.regymm
5508 || i
.types
[op
].bitfield
.regzmm
5509 || i
.types
[op
].bitfield
.sreg2
5510 || i
.types
[op
].bitfield
.sreg3
5511 || i
.types
[op
].bitfield
.control
5512 || i
.types
[op
].bitfield
.debug
5513 || i
.types
[op
].bitfield
.test
5514 || i
.types
[op
].bitfield
.floatreg
5515 || i
.types
[op
].bitfield
.floatacc
)
5517 as_bad (_("`%s%s' not allowed with `%s%c'"),
5519 i
.op
[op
].regs
->reg_name
,
5529 check_long_reg (void)
5533 for (op
= i
.operands
; --op
>= 0;)
5534 /* Reject eight bit registers, except where the template requires
5535 them. (eg. movzb) */
5536 if (i
.types
[op
].bitfield
.reg8
5537 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5538 || i
.tm
.operand_types
[op
].bitfield
.reg32
5539 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5541 as_bad (_("`%s%s' not allowed with `%s%c'"),
5543 i
.op
[op
].regs
->reg_name
,
5548 /* Warn if the e prefix on a general reg is missing. */
5549 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5550 && i
.types
[op
].bitfield
.reg16
5551 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5552 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5554 /* Prohibit these changes in the 64bit mode, since the
5555 lowering is more complicated. */
5556 if (flag_code
== CODE_64BIT
)
5558 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5559 register_prefix
, i
.op
[op
].regs
->reg_name
,
5563 #if REGISTER_WARNINGS
5564 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5566 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5567 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5570 /* Warn if the r prefix on a general reg is present. */
5571 else if (i
.types
[op
].bitfield
.reg64
5572 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5573 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5576 && i
.tm
.opcode_modifier
.toqword
5577 && !i
.types
[0].bitfield
.regxmm
)
5579 /* Convert to QWORD. We want REX byte. */
5580 i
.suffix
= QWORD_MNEM_SUFFIX
;
5584 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5585 register_prefix
, i
.op
[op
].regs
->reg_name
,
5594 check_qword_reg (void)
5598 for (op
= i
.operands
; --op
>= 0; )
5599 /* Reject eight bit registers, except where the template requires
5600 them. (eg. movzb) */
5601 if (i
.types
[op
].bitfield
.reg8
5602 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5603 || i
.tm
.operand_types
[op
].bitfield
.reg32
5604 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5606 as_bad (_("`%s%s' not allowed with `%s%c'"),
5608 i
.op
[op
].regs
->reg_name
,
5613 /* Warn if the r prefix on a general reg is missing. */
5614 else if ((i
.types
[op
].bitfield
.reg16
5615 || i
.types
[op
].bitfield
.reg32
)
5616 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5617 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5619 /* Prohibit these changes in the 64bit mode, since the
5620 lowering is more complicated. */
5622 && i
.tm
.opcode_modifier
.todword
5623 && !i
.types
[0].bitfield
.regxmm
)
5625 /* Convert to DWORD. We don't want REX byte. */
5626 i
.suffix
= LONG_MNEM_SUFFIX
;
5630 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5631 register_prefix
, i
.op
[op
].regs
->reg_name
,
5640 check_word_reg (void)
5643 for (op
= i
.operands
; --op
>= 0;)
5644 /* Reject eight bit registers, except where the template requires
5645 them. (eg. movzb) */
5646 if (i
.types
[op
].bitfield
.reg8
5647 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5648 || i
.tm
.operand_types
[op
].bitfield
.reg32
5649 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5651 as_bad (_("`%s%s' not allowed with `%s%c'"),
5653 i
.op
[op
].regs
->reg_name
,
5658 /* Warn if the e or r prefix on a general reg is present. */
5659 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5660 && (i
.types
[op
].bitfield
.reg32
5661 || i
.types
[op
].bitfield
.reg64
)
5662 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5663 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5665 /* Prohibit these changes in the 64bit mode, since the
5666 lowering is more complicated. */
5667 if (flag_code
== CODE_64BIT
)
5669 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5670 register_prefix
, i
.op
[op
].regs
->reg_name
,
5674 #if REGISTER_WARNINGS
5675 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5677 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5678 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5685 update_imm (unsigned int j
)
5687 i386_operand_type overlap
= i
.types
[j
];
5688 if ((overlap
.bitfield
.imm8
5689 || overlap
.bitfield
.imm8s
5690 || overlap
.bitfield
.imm16
5691 || overlap
.bitfield
.imm32
5692 || overlap
.bitfield
.imm32s
5693 || overlap
.bitfield
.imm64
)
5694 && !operand_type_equal (&overlap
, &imm8
)
5695 && !operand_type_equal (&overlap
, &imm8s
)
5696 && !operand_type_equal (&overlap
, &imm16
)
5697 && !operand_type_equal (&overlap
, &imm32
)
5698 && !operand_type_equal (&overlap
, &imm32s
)
5699 && !operand_type_equal (&overlap
, &imm64
))
5703 i386_operand_type temp
;
5705 operand_type_set (&temp
, 0);
5706 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5708 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5709 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5711 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5712 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5713 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5715 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5716 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5719 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5722 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5723 || operand_type_equal (&overlap
, &imm16_32
)
5724 || operand_type_equal (&overlap
, &imm16_32s
))
5726 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5731 if (!operand_type_equal (&overlap
, &imm8
)
5732 && !operand_type_equal (&overlap
, &imm8s
)
5733 && !operand_type_equal (&overlap
, &imm16
)
5734 && !operand_type_equal (&overlap
, &imm32
)
5735 && !operand_type_equal (&overlap
, &imm32s
)
5736 && !operand_type_equal (&overlap
, &imm64
))
5738 as_bad (_("no instruction mnemonic suffix given; "
5739 "can't determine immediate size"));
5743 i
.types
[j
] = overlap
;
5753 /* Update the first 2 immediate operands. */
5754 n
= i
.operands
> 2 ? 2 : i
.operands
;
5757 for (j
= 0; j
< n
; j
++)
5758 if (update_imm (j
) == 0)
5761 /* The 3rd operand can't be immediate operand. */
5762 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5769 bad_implicit_operand (int xmm
)
5771 const char *ireg
= xmm
? "xmm0" : "ymm0";
5774 as_bad (_("the last operand of `%s' must be `%s%s'"),
5775 i
.tm
.name
, register_prefix
, ireg
);
5777 as_bad (_("the first operand of `%s' must be `%s%s'"),
5778 i
.tm
.name
, register_prefix
, ireg
);
5783 process_operands (void)
5785 /* Default segment register this instruction will use for memory
5786 accesses. 0 means unknown. This is only for optimizing out
5787 unnecessary segment overrides. */
5788 const seg_entry
*default_seg
= 0;
5790 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5792 unsigned int dupl
= i
.operands
;
5793 unsigned int dest
= dupl
- 1;
5796 /* The destination must be an xmm register. */
5797 gas_assert (i
.reg_operands
5798 && MAX_OPERANDS
> dupl
5799 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5801 if (i
.tm
.opcode_modifier
.firstxmm0
)
5803 /* The first operand is implicit and must be xmm0. */
5804 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5805 if (register_number (i
.op
[0].regs
) != 0)
5806 return bad_implicit_operand (1);
5808 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5810 /* Keep xmm0 for instructions with VEX prefix and 3
5816 /* We remove the first xmm0 and keep the number of
5817 operands unchanged, which in fact duplicates the
5819 for (j
= 1; j
< i
.operands
; j
++)
5821 i
.op
[j
- 1] = i
.op
[j
];
5822 i
.types
[j
- 1] = i
.types
[j
];
5823 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5827 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5829 gas_assert ((MAX_OPERANDS
- 1) > dupl
5830 && (i
.tm
.opcode_modifier
.vexsources
5833 /* Add the implicit xmm0 for instructions with VEX prefix
5835 for (j
= i
.operands
; j
> 0; j
--)
5837 i
.op
[j
] = i
.op
[j
- 1];
5838 i
.types
[j
] = i
.types
[j
- 1];
5839 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5842 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5843 i
.types
[0] = regxmm
;
5844 i
.tm
.operand_types
[0] = regxmm
;
5847 i
.reg_operands
+= 2;
5852 i
.op
[dupl
] = i
.op
[dest
];
5853 i
.types
[dupl
] = i
.types
[dest
];
5854 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5863 i
.op
[dupl
] = i
.op
[dest
];
5864 i
.types
[dupl
] = i
.types
[dest
];
5865 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5868 if (i
.tm
.opcode_modifier
.immext
)
5871 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5875 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5876 gas_assert (i
.reg_operands
5877 && (operand_type_equal (&i
.types
[0], ®xmm
)
5878 || operand_type_equal (&i
.types
[0], ®ymm
)
5879 || operand_type_equal (&i
.types
[0], ®zmm
)));
5880 if (register_number (i
.op
[0].regs
) != 0)
5881 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5883 for (j
= 1; j
< i
.operands
; j
++)
5885 i
.op
[j
- 1] = i
.op
[j
];
5886 i
.types
[j
- 1] = i
.types
[j
];
5888 /* We need to adjust fields in i.tm since they are used by
5889 build_modrm_byte. */
5890 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5897 else if (i
.tm
.opcode_modifier
.regkludge
)
5899 /* The imul $imm, %reg instruction is converted into
5900 imul $imm, %reg, %reg, and the clr %reg instruction
5901 is converted into xor %reg, %reg. */
5903 unsigned int first_reg_op
;
5905 if (operand_type_check (i
.types
[0], reg
))
5909 /* Pretend we saw the extra register operand. */
5910 gas_assert (i
.reg_operands
== 1
5911 && i
.op
[first_reg_op
+ 1].regs
== 0);
5912 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5913 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5918 if (i
.tm
.opcode_modifier
.shortform
)
5920 if (i
.types
[0].bitfield
.sreg2
5921 || i
.types
[0].bitfield
.sreg3
)
5923 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5924 && i
.op
[0].regs
->reg_num
== 1)
5926 as_bad (_("you can't `pop %scs'"), register_prefix
);
5929 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5930 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5935 /* The register or float register operand is in operand
5939 if (i
.types
[0].bitfield
.floatreg
5940 || operand_type_check (i
.types
[0], reg
))
5944 /* Register goes in low 3 bits of opcode. */
5945 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5946 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5948 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5950 /* Warn about some common errors, but press on regardless.
5951 The first case can be generated by gcc (<= 2.8.1). */
5952 if (i
.operands
== 2)
5954 /* Reversed arguments on faddp, fsubp, etc. */
5955 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5956 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5957 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5961 /* Extraneous `l' suffix on fp insn. */
5962 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5963 register_prefix
, i
.op
[0].regs
->reg_name
);
5968 else if (i
.tm
.opcode_modifier
.modrm
)
5970 /* The opcode is completed (modulo i.tm.extension_opcode which
5971 must be put into the modrm byte). Now, we make the modrm and
5972 index base bytes based on all the info we've collected. */
5974 default_seg
= build_modrm_byte ();
5976 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5980 else if (i
.tm
.opcode_modifier
.isstring
)
5982 /* For the string instructions that allow a segment override
5983 on one of their operands, the default segment is ds. */
5987 if (i
.tm
.base_opcode
== 0x8d /* lea */
5990 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5992 /* If a segment was explicitly specified, and the specified segment
5993 is not the default, use an opcode prefix to select it. If we
5994 never figured out what the default segment is, then default_seg
5995 will be zero at this point, and the specified segment prefix will
5997 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5999 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6005 static const seg_entry
*
6006 build_modrm_byte (void)
6008 const seg_entry
*default_seg
= 0;
6009 unsigned int source
, dest
;
6012 /* The first operand of instructions with VEX prefix and 3 sources
6013 must be VEX_Imm4. */
6014 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6017 unsigned int nds
, reg_slot
;
6020 if (i
.tm
.opcode_modifier
.veximmext
6021 && i
.tm
.opcode_modifier
.immext
)
6023 dest
= i
.operands
- 2;
6024 gas_assert (dest
== 3);
6027 dest
= i
.operands
- 1;
6030 /* There are 2 kinds of instructions:
6031 1. 5 operands: 4 register operands or 3 register operands
6032 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6033 VexW0 or VexW1. The destination must be either XMM, YMM or
6035 2. 4 operands: 4 register operands or 3 register operands
6036 plus 1 memory operand, VexXDS, and VexImmExt */
6037 gas_assert ((i
.reg_operands
== 4
6038 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6039 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6040 && (i
.tm
.opcode_modifier
.veximmext
6041 || (i
.imm_operands
== 1
6042 && i
.types
[0].bitfield
.vec_imm4
6043 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
6044 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6045 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
6046 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
6047 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
6049 if (i
.imm_operands
== 0)
6051 /* When there is no immediate operand, generate an 8bit
6052 immediate operand to encode the first operand. */
6053 exp
= &im_expressions
[i
.imm_operands
++];
6054 i
.op
[i
.operands
].imms
= exp
;
6055 i
.types
[i
.operands
] = imm8
;
6057 /* If VexW1 is set, the first operand is the source and
6058 the second operand is encoded in the immediate operand. */
6059 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6070 /* FMA swaps REG and NDS. */
6071 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6079 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6081 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6083 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6085 exp
->X_op
= O_constant
;
6086 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6087 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6091 unsigned int imm_slot
;
6093 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6095 /* If VexW0 is set, the third operand is the source and
6096 the second operand is encoded in the immediate
6103 /* VexW1 is set, the second operand is the source and
6104 the third operand is encoded in the immediate
6110 if (i
.tm
.opcode_modifier
.immext
)
6112 /* When ImmExt is set, the immdiate byte is the last
6114 imm_slot
= i
.operands
- 1;
6122 /* Turn on Imm8 so that output_imm will generate it. */
6123 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6126 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6128 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6130 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6132 i
.op
[imm_slot
].imms
->X_add_number
6133 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6134 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6137 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6138 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6140 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6142 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6147 /* i.reg_operands MUST be the number of real register operands;
6148 implicit registers do not count. If there are 3 register
6149 operands, it must be a instruction with VexNDS. For a
6150 instruction with VexNDD, the destination register is encoded
6151 in VEX prefix. If there are 4 register operands, it must be
6152 a instruction with VEX prefix and 3 sources. */
6153 if (i
.mem_operands
== 0
6154 && ((i
.reg_operands
== 2
6155 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6156 || (i
.reg_operands
== 3
6157 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6158 || (i
.reg_operands
== 4 && vex_3_sources
)))
6166 /* When there are 3 operands, one of them may be immediate,
6167 which may be the first or the last operand. Otherwise,
6168 the first operand must be shift count register (cl) or it
6169 is an instruction with VexNDS. */
6170 gas_assert (i
.imm_operands
== 1
6171 || (i
.imm_operands
== 0
6172 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6173 || i
.types
[0].bitfield
.shiftcount
)));
6174 if (operand_type_check (i
.types
[0], imm
)
6175 || i
.types
[0].bitfield
.shiftcount
)
6181 /* When there are 4 operands, the first two must be 8bit
6182 immediate operands. The source operand will be the 3rd
6185 For instructions with VexNDS, if the first operand
6186 an imm8, the source operand is the 2nd one. If the last
6187 operand is imm8, the source operand is the first one. */
6188 gas_assert ((i
.imm_operands
== 2
6189 && i
.types
[0].bitfield
.imm8
6190 && i
.types
[1].bitfield
.imm8
)
6191 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6192 && i
.imm_operands
== 1
6193 && (i
.types
[0].bitfield
.imm8
6194 || i
.types
[i
.operands
- 1].bitfield
.imm8
6196 if (i
.imm_operands
== 2)
6200 if (i
.types
[0].bitfield
.imm8
)
6207 if (i
.tm
.opcode_modifier
.evex
)
6209 /* For EVEX instructions, when there are 5 operands, the
6210 first one must be immediate operand. If the second one
6211 is immediate operand, the source operand is the 3th
6212 one. If the last one is immediate operand, the source
6213 operand is the 2nd one. */
6214 gas_assert (i
.imm_operands
== 2
6215 && i
.tm
.opcode_modifier
.sae
6216 && operand_type_check (i
.types
[0], imm
));
6217 if (operand_type_check (i
.types
[1], imm
))
6219 else if (operand_type_check (i
.types
[4], imm
))
6233 /* RC/SAE operand could be between DEST and SRC. That happens
6234 when one operand is GPR and the other one is XMM/YMM/ZMM
6236 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6239 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6241 /* For instructions with VexNDS, the register-only source
6242 operand must be 32/64bit integer, XMM, YMM or ZMM
6243 register. It is encoded in VEX prefix. We need to
6244 clear RegMem bit before calling operand_type_equal. */
6246 i386_operand_type op
;
6249 /* Check register-only source operand when two source
6250 operands are swapped. */
6251 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6252 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6260 op
= i
.tm
.operand_types
[vvvv
];
6261 op
.bitfield
.regmem
= 0;
6262 if ((dest
+ 1) >= i
.operands
6263 || (!op
.bitfield
.reg32
6264 && op
.bitfield
.reg64
6265 && !operand_type_equal (&op
, ®xmm
)
6266 && !operand_type_equal (&op
, ®ymm
)
6267 && !operand_type_equal (&op
, ®zmm
)
6268 && !operand_type_equal (&op
, ®mask
)))
6270 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6276 /* One of the register operands will be encoded in the i.tm.reg
6277 field, the other in the combined i.tm.mode and i.tm.regmem
6278 fields. If no form of this instruction supports a memory
6279 destination operand, then we assume the source operand may
6280 sometimes be a memory operand and so we need to store the
6281 destination in the i.rm.reg field. */
6282 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6283 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6285 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6286 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6287 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6289 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6291 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6293 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6298 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6299 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6300 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6302 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6304 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6306 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6309 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6311 if (!i
.types
[0].bitfield
.control
6312 && !i
.types
[1].bitfield
.control
)
6314 i
.rex
&= ~(REX_R
| REX_B
);
6315 add_prefix (LOCK_PREFIX_OPCODE
);
6319 { /* If it's not 2 reg operands... */
6324 unsigned int fake_zero_displacement
= 0;
6327 for (op
= 0; op
< i
.operands
; op
++)
6328 if (operand_type_check (i
.types
[op
], anymem
))
6330 gas_assert (op
< i
.operands
);
6332 if (i
.tm
.opcode_modifier
.vecsib
)
6334 if (i
.index_reg
->reg_num
== RegEiz
6335 || i
.index_reg
->reg_num
== RegRiz
)
6338 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6341 i
.sib
.base
= NO_BASE_REGISTER
;
6342 i
.sib
.scale
= i
.log2_scale_factor
;
6343 /* No Vec_Disp8 if there is no base. */
6344 i
.types
[op
].bitfield
.vec_disp8
= 0;
6345 i
.types
[op
].bitfield
.disp8
= 0;
6346 i
.types
[op
].bitfield
.disp16
= 0;
6347 i
.types
[op
].bitfield
.disp64
= 0;
6348 if (flag_code
!= CODE_64BIT
)
6350 /* Must be 32 bit */
6351 i
.types
[op
].bitfield
.disp32
= 1;
6352 i
.types
[op
].bitfield
.disp32s
= 0;
6356 i
.types
[op
].bitfield
.disp32
= 0;
6357 i
.types
[op
].bitfield
.disp32s
= 1;
6360 i
.sib
.index
= i
.index_reg
->reg_num
;
6361 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6363 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6369 if (i
.base_reg
== 0)
6372 if (!i
.disp_operands
)
6374 fake_zero_displacement
= 1;
6375 /* Instructions with VSIB byte need 32bit displacement
6376 if there is no base register. */
6377 if (i
.tm
.opcode_modifier
.vecsib
)
6378 i
.types
[op
].bitfield
.disp32
= 1;
6380 if (i
.index_reg
== 0)
6382 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6383 /* Operand is just <disp> */
6384 if (flag_code
== CODE_64BIT
)
6386 /* 64bit mode overwrites the 32bit absolute
6387 addressing by RIP relative addressing and
6388 absolute addressing is encoded by one of the
6389 redundant SIB forms. */
6390 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6391 i
.sib
.base
= NO_BASE_REGISTER
;
6392 i
.sib
.index
= NO_INDEX_REGISTER
;
6393 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6394 ? disp32s
: disp32
);
6396 else if ((flag_code
== CODE_16BIT
)
6397 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6399 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6400 i
.types
[op
] = disp16
;
6404 i
.rm
.regmem
= NO_BASE_REGISTER
;
6405 i
.types
[op
] = disp32
;
6408 else if (!i
.tm
.opcode_modifier
.vecsib
)
6410 /* !i.base_reg && i.index_reg */
6411 if (i
.index_reg
->reg_num
== RegEiz
6412 || i
.index_reg
->reg_num
== RegRiz
)
6413 i
.sib
.index
= NO_INDEX_REGISTER
;
6415 i
.sib
.index
= i
.index_reg
->reg_num
;
6416 i
.sib
.base
= NO_BASE_REGISTER
;
6417 i
.sib
.scale
= i
.log2_scale_factor
;
6418 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6419 /* No Vec_Disp8 if there is no base. */
6420 i
.types
[op
].bitfield
.vec_disp8
= 0;
6421 i
.types
[op
].bitfield
.disp8
= 0;
6422 i
.types
[op
].bitfield
.disp16
= 0;
6423 i
.types
[op
].bitfield
.disp64
= 0;
6424 if (flag_code
!= CODE_64BIT
)
6426 /* Must be 32 bit */
6427 i
.types
[op
].bitfield
.disp32
= 1;
6428 i
.types
[op
].bitfield
.disp32s
= 0;
6432 i
.types
[op
].bitfield
.disp32
= 0;
6433 i
.types
[op
].bitfield
.disp32s
= 1;
6435 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6439 /* RIP addressing for 64bit mode. */
6440 else if (i
.base_reg
->reg_num
== RegRip
||
6441 i
.base_reg
->reg_num
== RegEip
)
6443 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6444 i
.rm
.regmem
= NO_BASE_REGISTER
;
6445 i
.types
[op
].bitfield
.disp8
= 0;
6446 i
.types
[op
].bitfield
.disp16
= 0;
6447 i
.types
[op
].bitfield
.disp32
= 0;
6448 i
.types
[op
].bitfield
.disp32s
= 1;
6449 i
.types
[op
].bitfield
.disp64
= 0;
6450 i
.types
[op
].bitfield
.vec_disp8
= 0;
6451 i
.flags
[op
] |= Operand_PCrel
;
6452 if (! i
.disp_operands
)
6453 fake_zero_displacement
= 1;
6455 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6457 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6458 switch (i
.base_reg
->reg_num
)
6461 if (i
.index_reg
== 0)
6463 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6464 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6468 if (i
.index_reg
== 0)
6471 if (operand_type_check (i
.types
[op
], disp
) == 0)
6473 /* fake (%bp) into 0(%bp) */
6474 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6475 i
.types
[op
].bitfield
.vec_disp8
= 1;
6477 i
.types
[op
].bitfield
.disp8
= 1;
6478 fake_zero_displacement
= 1;
6481 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6482 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6484 default: /* (%si) -> 4 or (%di) -> 5 */
6485 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6487 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6489 else /* i.base_reg and 32/64 bit mode */
6491 if (flag_code
== CODE_64BIT
6492 && operand_type_check (i
.types
[op
], disp
))
6494 i386_operand_type temp
;
6495 operand_type_set (&temp
, 0);
6496 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6497 temp
.bitfield
.vec_disp8
6498 = i
.types
[op
].bitfield
.vec_disp8
;
6500 if (i
.prefix
[ADDR_PREFIX
] == 0)
6501 i
.types
[op
].bitfield
.disp32s
= 1;
6503 i
.types
[op
].bitfield
.disp32
= 1;
6506 if (!i
.tm
.opcode_modifier
.vecsib
)
6507 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6508 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6510 i
.sib
.base
= i
.base_reg
->reg_num
;
6511 /* x86-64 ignores REX prefix bit here to avoid decoder
6513 if (!(i
.base_reg
->reg_flags
& RegRex
)
6514 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6515 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6517 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6519 fake_zero_displacement
= 1;
6520 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6521 i
.types
[op
].bitfield
.vec_disp8
= 1;
6523 i
.types
[op
].bitfield
.disp8
= 1;
6525 i
.sib
.scale
= i
.log2_scale_factor
;
6526 if (i
.index_reg
== 0)
6528 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6529 /* <disp>(%esp) becomes two byte modrm with no index
6530 register. We've already stored the code for esp
6531 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6532 Any base register besides %esp will not use the
6533 extra modrm byte. */
6534 i
.sib
.index
= NO_INDEX_REGISTER
;
6536 else if (!i
.tm
.opcode_modifier
.vecsib
)
6538 if (i
.index_reg
->reg_num
== RegEiz
6539 || i
.index_reg
->reg_num
== RegRiz
)
6540 i
.sib
.index
= NO_INDEX_REGISTER
;
6542 i
.sib
.index
= i
.index_reg
->reg_num
;
6543 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6544 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6549 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6550 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6554 if (!fake_zero_displacement
6558 fake_zero_displacement
= 1;
6559 if (i
.disp_encoding
== disp_encoding_8bit
)
6560 i
.types
[op
].bitfield
.disp8
= 1;
6562 i
.types
[op
].bitfield
.disp32
= 1;
6564 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6568 if (fake_zero_displacement
)
6570 /* Fakes a zero displacement assuming that i.types[op]
6571 holds the correct displacement size. */
6574 gas_assert (i
.op
[op
].disps
== 0);
6575 exp
= &disp_expressions
[i
.disp_operands
++];
6576 i
.op
[op
].disps
= exp
;
6577 exp
->X_op
= O_constant
;
6578 exp
->X_add_number
= 0;
6579 exp
->X_add_symbol
= (symbolS
*) 0;
6580 exp
->X_op_symbol
= (symbolS
*) 0;
6588 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6590 if (operand_type_check (i
.types
[0], imm
))
6591 i
.vex
.register_specifier
= NULL
;
6594 /* VEX.vvvv encodes one of the sources when the first
6595 operand is not an immediate. */
6596 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6597 i
.vex
.register_specifier
= i
.op
[0].regs
;
6599 i
.vex
.register_specifier
= i
.op
[1].regs
;
6602 /* Destination is a XMM register encoded in the ModRM.reg
6604 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6605 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6608 /* ModRM.rm and VEX.B encodes the other source. */
6609 if (!i
.mem_operands
)
6613 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6614 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6616 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6618 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6622 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6624 i
.vex
.register_specifier
= i
.op
[2].regs
;
6625 if (!i
.mem_operands
)
6628 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6629 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6633 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6634 (if any) based on i.tm.extension_opcode. Again, we must be
6635 careful to make sure that segment/control/debug/test/MMX
6636 registers are coded into the i.rm.reg field. */
6637 else if (i
.reg_operands
)
6640 unsigned int vex_reg
= ~0;
6642 for (op
= 0; op
< i
.operands
; op
++)
6643 if (i
.types
[op
].bitfield
.reg8
6644 || i
.types
[op
].bitfield
.reg16
6645 || i
.types
[op
].bitfield
.reg32
6646 || i
.types
[op
].bitfield
.reg64
6647 || i
.types
[op
].bitfield
.regmmx
6648 || i
.types
[op
].bitfield
.regxmm
6649 || i
.types
[op
].bitfield
.regymm
6650 || i
.types
[op
].bitfield
.regbnd
6651 || i
.types
[op
].bitfield
.regzmm
6652 || i
.types
[op
].bitfield
.regmask
6653 || i
.types
[op
].bitfield
.sreg2
6654 || i
.types
[op
].bitfield
.sreg3
6655 || i
.types
[op
].bitfield
.control
6656 || i
.types
[op
].bitfield
.debug
6657 || i
.types
[op
].bitfield
.test
)
6662 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6664 /* For instructions with VexNDS, the register-only
6665 source operand is encoded in VEX prefix. */
6666 gas_assert (mem
!= (unsigned int) ~0);
6671 gas_assert (op
< i
.operands
);
6675 /* Check register-only source operand when two source
6676 operands are swapped. */
6677 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6678 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6682 gas_assert (mem
== (vex_reg
+ 1)
6683 && op
< i
.operands
);
6688 gas_assert (vex_reg
< i
.operands
);
6692 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6694 /* For instructions with VexNDD, the register destination
6695 is encoded in VEX prefix. */
6696 if (i
.mem_operands
== 0)
6698 /* There is no memory operand. */
6699 gas_assert ((op
+ 2) == i
.operands
);
6704 /* There are only 2 operands. */
6705 gas_assert (op
< 2 && i
.operands
== 2);
6710 gas_assert (op
< i
.operands
);
6712 if (vex_reg
!= (unsigned int) ~0)
6714 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6716 if (type
->bitfield
.reg32
!= 1
6717 && type
->bitfield
.reg64
!= 1
6718 && !operand_type_equal (type
, ®xmm
)
6719 && !operand_type_equal (type
, ®ymm
)
6720 && !operand_type_equal (type
, ®zmm
)
6721 && !operand_type_equal (type
, ®mask
))
6724 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6727 /* Don't set OP operand twice. */
6730 /* If there is an extension opcode to put here, the
6731 register number must be put into the regmem field. */
6732 if (i
.tm
.extension_opcode
!= None
)
6734 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6735 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6737 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6742 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6743 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6745 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6750 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6751 must set it to 3 to indicate this is a register operand
6752 in the regmem field. */
6753 if (!i
.mem_operands
)
6757 /* Fill in i.rm.reg field with extension opcode (if any). */
6758 if (i
.tm
.extension_opcode
!= None
)
6759 i
.rm
.reg
= i
.tm
.extension_opcode
;
6765 output_branch (void)
6771 relax_substateT subtype
;
6775 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6776 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6779 if (i
.prefix
[DATA_PREFIX
] != 0)
6785 /* Pentium4 branch hints. */
6786 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6787 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6792 if (i
.prefix
[REX_PREFIX
] != 0)
6798 /* BND prefixed jump. */
6799 if (i
.prefix
[BND_PREFIX
] != 0)
6801 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6805 if (i
.prefixes
!= 0 && !intel_syntax
)
6806 as_warn (_("skipping prefixes on this instruction"));
6808 /* It's always a symbol; End frag & setup for relax.
6809 Make sure there is enough room in this frag for the largest
6810 instruction we may generate in md_convert_frag. This is 2
6811 bytes for the opcode and room for the prefix and largest
6813 frag_grow (prefix
+ 2 + 4);
6814 /* Prefix and 1 opcode byte go in fr_fix. */
6815 p
= frag_more (prefix
+ 1);
6816 if (i
.prefix
[DATA_PREFIX
] != 0)
6817 *p
++ = DATA_PREFIX_OPCODE
;
6818 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6819 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6820 *p
++ = i
.prefix
[SEG_PREFIX
];
6821 if (i
.prefix
[REX_PREFIX
] != 0)
6822 *p
++ = i
.prefix
[REX_PREFIX
];
6823 *p
= i
.tm
.base_opcode
;
6825 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6826 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6827 else if (cpu_arch_flags
.bitfield
.cpui386
)
6828 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6830 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6833 sym
= i
.op
[0].disps
->X_add_symbol
;
6834 off
= i
.op
[0].disps
->X_add_number
;
6836 if (i
.op
[0].disps
->X_op
!= O_constant
6837 && i
.op
[0].disps
->X_op
!= O_symbol
)
6839 /* Handle complex expressions. */
6840 sym
= make_expr_symbol (i
.op
[0].disps
);
6844 /* 1 possible extra opcode + 4 byte displacement go in var part.
6845 Pass reloc in fr_var. */
6846 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6856 if (i
.tm
.opcode_modifier
.jumpbyte
)
6858 /* This is a loop or jecxz type instruction. */
6860 if (i
.prefix
[ADDR_PREFIX
] != 0)
6862 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6865 /* Pentium4 branch hints. */
6866 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6867 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6869 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6878 if (flag_code
== CODE_16BIT
)
6881 if (i
.prefix
[DATA_PREFIX
] != 0)
6883 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6893 if (i
.prefix
[REX_PREFIX
] != 0)
6895 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6899 /* BND prefixed jump. */
6900 if (i
.prefix
[BND_PREFIX
] != 0)
6902 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6906 if (i
.prefixes
!= 0 && !intel_syntax
)
6907 as_warn (_("skipping prefixes on this instruction"));
6909 p
= frag_more (i
.tm
.opcode_length
+ size
);
6910 switch (i
.tm
.opcode_length
)
6913 *p
++ = i
.tm
.base_opcode
>> 8;
6915 *p
++ = i
.tm
.base_opcode
;
6921 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6922 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6924 /* All jumps handled here are signed, but don't use a signed limit
6925 check for 32 and 16 bit jumps as we want to allow wrap around at
6926 4G and 64k respectively. */
6928 fixP
->fx_signed
= 1;
6932 output_interseg_jump (void)
6940 if (flag_code
== CODE_16BIT
)
6944 if (i
.prefix
[DATA_PREFIX
] != 0)
6950 if (i
.prefix
[REX_PREFIX
] != 0)
6960 if (i
.prefixes
!= 0 && !intel_syntax
)
6961 as_warn (_("skipping prefixes on this instruction"));
6963 /* 1 opcode; 2 segment; offset */
6964 p
= frag_more (prefix
+ 1 + 2 + size
);
6966 if (i
.prefix
[DATA_PREFIX
] != 0)
6967 *p
++ = DATA_PREFIX_OPCODE
;
6969 if (i
.prefix
[REX_PREFIX
] != 0)
6970 *p
++ = i
.prefix
[REX_PREFIX
];
6972 *p
++ = i
.tm
.base_opcode
;
6973 if (i
.op
[1].imms
->X_op
== O_constant
)
6975 offsetT n
= i
.op
[1].imms
->X_add_number
;
6978 && !fits_in_unsigned_word (n
)
6979 && !fits_in_signed_word (n
))
6981 as_bad (_("16-bit jump out of range"));
6984 md_number_to_chars (p
, n
, size
);
6987 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6988 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6989 if (i
.op
[0].imms
->X_op
!= O_constant
)
6990 as_bad (_("can't handle non absolute segment in `%s'"),
6992 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6998 fragS
*insn_start_frag
;
6999 offsetT insn_start_off
;
7001 /* Tie dwarf2 debug info to the address at the start of the insn.
7002 We can't do this after the insn has been output as the current
7003 frag may have been closed off. eg. by frag_var. */
7004 dwarf2_emit_insn (0);
7006 insn_start_frag
= frag_now
;
7007 insn_start_off
= frag_now_fix ();
7010 if (i
.tm
.opcode_modifier
.jump
)
7012 else if (i
.tm
.opcode_modifier
.jumpbyte
7013 || i
.tm
.opcode_modifier
.jumpdword
)
7015 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7016 output_interseg_jump ();
7019 /* Output normal instructions here. */
7023 unsigned int prefix
;
7026 && i
.tm
.base_opcode
== 0xfae
7028 && i
.imm_operands
== 1
7029 && (i
.op
[0].imms
->X_add_number
== 0xe8
7030 || i
.op
[0].imms
->X_add_number
== 0xf0
7031 || i
.op
[0].imms
->X_add_number
== 0xf8))
7033 /* Encode lfence, mfence, and sfence as
7034 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7035 offsetT val
= 0x240483f0ULL
;
7037 md_number_to_chars (p
, val
, 5);
7041 /* Some processors fail on LOCK prefix. This options makes
7042 assembler ignore LOCK prefix and serves as a workaround. */
7043 if (omit_lock_prefix
)
7045 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7047 i
.prefix
[LOCK_PREFIX
] = 0;
7050 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7051 don't need the explicit prefix. */
7052 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7054 switch (i
.tm
.opcode_length
)
7057 if (i
.tm
.base_opcode
& 0xff000000)
7059 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7064 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7066 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7067 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7070 if (prefix
!= REPE_PREFIX_OPCODE
7071 || (i
.prefix
[REP_PREFIX
]
7072 != REPE_PREFIX_OPCODE
))
7073 add_prefix (prefix
);
7076 add_prefix (prefix
);
7085 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7086 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7087 R_X86_64_GOTTPOFF relocation so that linker can safely
7088 perform IE->LE optimization. */
7089 if (x86_elf_abi
== X86_64_X32_ABI
7091 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7092 && i
.prefix
[REX_PREFIX
] == 0)
7093 add_prefix (REX_OPCODE
);
7096 /* The prefix bytes. */
7097 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7099 FRAG_APPEND_1_CHAR (*q
);
7103 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7108 /* REX byte is encoded in VEX prefix. */
7112 FRAG_APPEND_1_CHAR (*q
);
7115 /* There should be no other prefixes for instructions
7120 /* For EVEX instructions i.vrex should become 0 after
7121 build_evex_prefix. For VEX instructions upper 16 registers
7122 aren't available, so VREX should be 0. */
7125 /* Now the VEX prefix. */
7126 p
= frag_more (i
.vex
.length
);
7127 for (j
= 0; j
< i
.vex
.length
; j
++)
7128 p
[j
] = i
.vex
.bytes
[j
];
7131 /* Now the opcode; be careful about word order here! */
7132 if (i
.tm
.opcode_length
== 1)
7134 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7138 switch (i
.tm
.opcode_length
)
7142 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7143 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7147 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7157 /* Put out high byte first: can't use md_number_to_chars! */
7158 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7159 *p
= i
.tm
.base_opcode
& 0xff;
7162 /* Now the modrm byte and sib byte (if present). */
7163 if (i
.tm
.opcode_modifier
.modrm
)
7165 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7168 /* If i.rm.regmem == ESP (4)
7169 && i.rm.mode != (Register mode)
7171 ==> need second modrm byte. */
7172 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7174 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7175 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7177 | i
.sib
.scale
<< 6));
7180 if (i
.disp_operands
)
7181 output_disp (insn_start_frag
, insn_start_off
);
7184 output_imm (insn_start_frag
, insn_start_off
);
7190 pi ("" /*line*/, &i
);
7192 #endif /* DEBUG386 */
7195 /* Return the size of the displacement operand N. */
7198 disp_size (unsigned int n
)
7202 /* Vec_Disp8 has to be 8bit. */
7203 if (i
.types
[n
].bitfield
.vec_disp8
)
7205 else if (i
.types
[n
].bitfield
.disp64
)
7207 else if (i
.types
[n
].bitfield
.disp8
)
7209 else if (i
.types
[n
].bitfield
.disp16
)
7214 /* Return the size of the immediate operand N. */
7217 imm_size (unsigned int n
)
7220 if (i
.types
[n
].bitfield
.imm64
)
7222 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7224 else if (i
.types
[n
].bitfield
.imm16
)
7230 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7235 for (n
= 0; n
< i
.operands
; n
++)
7237 if (i
.types
[n
].bitfield
.vec_disp8
7238 || operand_type_check (i
.types
[n
], disp
))
7240 if (i
.op
[n
].disps
->X_op
== O_constant
)
7242 int size
= disp_size (n
);
7243 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7245 if (i
.types
[n
].bitfield
.vec_disp8
)
7247 val
= offset_in_range (val
, size
);
7248 p
= frag_more (size
);
7249 md_number_to_chars (p
, val
, size
);
7253 enum bfd_reloc_code_real reloc_type
;
7254 int size
= disp_size (n
);
7255 int sign
= i
.types
[n
].bitfield
.disp32s
;
7256 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7259 /* We can't have 8 bit displacement here. */
7260 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7262 /* The PC relative address is computed relative
7263 to the instruction boundary, so in case immediate
7264 fields follows, we need to adjust the value. */
7265 if (pcrel
&& i
.imm_operands
)
7270 for (n1
= 0; n1
< i
.operands
; n1
++)
7271 if (operand_type_check (i
.types
[n1
], imm
))
7273 /* Only one immediate is allowed for PC
7274 relative address. */
7275 gas_assert (sz
== 0);
7277 i
.op
[n
].disps
->X_add_number
-= sz
;
7279 /* We should find the immediate. */
7280 gas_assert (sz
!= 0);
7283 p
= frag_more (size
);
7284 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7286 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7287 && (((reloc_type
== BFD_RELOC_32
7288 || reloc_type
== BFD_RELOC_X86_64_32S
7289 || (reloc_type
== BFD_RELOC_64
7291 && (i
.op
[n
].disps
->X_op
== O_symbol
7292 || (i
.op
[n
].disps
->X_op
== O_add
7293 && ((symbol_get_value_expression
7294 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7296 || reloc_type
== BFD_RELOC_32_PCREL
))
7300 if (insn_start_frag
== frag_now
)
7301 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7306 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7307 for (fr
= insn_start_frag
->fr_next
;
7308 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7310 add
+= p
- frag_now
->fr_literal
;
7315 reloc_type
= BFD_RELOC_386_GOTPC
;
7316 i
.op
[n
].imms
->X_add_number
+= add
;
7318 else if (reloc_type
== BFD_RELOC_64
)
7319 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7321 /* Don't do the adjustment for x86-64, as there
7322 the pcrel addressing is relative to the _next_
7323 insn, and that is taken care of in other code. */
7324 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7326 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7327 size
, i
.op
[n
].disps
, pcrel
,
7329 /* Check for "call/jmp *mem", "mov mem, %reg",
7330 "test %reg, mem" and "binop mem, %reg" where binop
7331 is one of adc, add, and, cmp, or, sbb, sub, xor
7332 instructions. Always generate R_386_GOT32X for
7333 "sym*GOT" operand in 32-bit mode. */
7334 if ((generate_relax_relocations
7337 && i
.rm
.regmem
== 5))
7339 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7340 && ((i
.operands
== 1
7341 && i
.tm
.base_opcode
== 0xff
7342 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7344 && (i
.tm
.base_opcode
== 0x8b
7345 || i
.tm
.base_opcode
== 0x85
7346 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7350 fixP
->fx_tcbit
= i
.rex
!= 0;
7352 && (i
.base_reg
->reg_num
== RegRip
7353 || i
.base_reg
->reg_num
== RegEip
))
7354 fixP
->fx_tcbit2
= 1;
7357 fixP
->fx_tcbit2
= 1;
7365 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7370 for (n
= 0; n
< i
.operands
; n
++)
7372 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7373 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7376 if (operand_type_check (i
.types
[n
], imm
))
7378 if (i
.op
[n
].imms
->X_op
== O_constant
)
7380 int size
= imm_size (n
);
7383 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7385 p
= frag_more (size
);
7386 md_number_to_chars (p
, val
, size
);
7390 /* Not absolute_section.
7391 Need a 32-bit fixup (don't support 8bit
7392 non-absolute imms). Try to support other
7394 enum bfd_reloc_code_real reloc_type
;
7395 int size
= imm_size (n
);
7398 if (i
.types
[n
].bitfield
.imm32s
7399 && (i
.suffix
== QWORD_MNEM_SUFFIX
7400 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7405 p
= frag_more (size
);
7406 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7408 /* This is tough to explain. We end up with this one if we
7409 * have operands that look like
7410 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7411 * obtain the absolute address of the GOT, and it is strongly
7412 * preferable from a performance point of view to avoid using
7413 * a runtime relocation for this. The actual sequence of
7414 * instructions often look something like:
7419 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7421 * The call and pop essentially return the absolute address
7422 * of the label .L66 and store it in %ebx. The linker itself
7423 * will ultimately change the first operand of the addl so
7424 * that %ebx points to the GOT, but to keep things simple, the
7425 * .o file must have this operand set so that it generates not
7426 * the absolute address of .L66, but the absolute address of
7427 * itself. This allows the linker itself simply treat a GOTPC
7428 * relocation as asking for a pcrel offset to the GOT to be
7429 * added in, and the addend of the relocation is stored in the
7430 * operand field for the instruction itself.
7432 * Our job here is to fix the operand so that it would add
7433 * the correct offset so that %ebx would point to itself. The
7434 * thing that is tricky is that .-.L66 will point to the
7435 * beginning of the instruction, so we need to further modify
7436 * the operand so that it will point to itself. There are
7437 * other cases where you have something like:
7439 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7441 * and here no correction would be required. Internally in
7442 * the assembler we treat operands of this form as not being
7443 * pcrel since the '.' is explicitly mentioned, and I wonder
7444 * whether it would simplify matters to do it this way. Who
7445 * knows. In earlier versions of the PIC patches, the
7446 * pcrel_adjust field was used to store the correction, but
7447 * since the expression is not pcrel, I felt it would be
7448 * confusing to do it this way. */
7450 if ((reloc_type
== BFD_RELOC_32
7451 || reloc_type
== BFD_RELOC_X86_64_32S
7452 || reloc_type
== BFD_RELOC_64
)
7454 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7455 && (i
.op
[n
].imms
->X_op
== O_symbol
7456 || (i
.op
[n
].imms
->X_op
== O_add
7457 && ((symbol_get_value_expression
7458 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7463 if (insn_start_frag
== frag_now
)
7464 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7469 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7470 for (fr
= insn_start_frag
->fr_next
;
7471 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7473 add
+= p
- frag_now
->fr_literal
;
7477 reloc_type
= BFD_RELOC_386_GOTPC
;
7479 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7481 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7482 i
.op
[n
].imms
->X_add_number
+= add
;
7484 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7485 i
.op
[n
].imms
, 0, reloc_type
);
7491 /* x86_cons_fix_new is called via the expression parsing code when a
7492 reloc is needed. We use this hook to get the correct .got reloc. */
7493 static int cons_sign
= -1;
7496 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7497 expressionS
*exp
, bfd_reloc_code_real_type r
)
7499 r
= reloc (len
, 0, cons_sign
, r
);
7502 if (exp
->X_op
== O_secrel
)
7504 exp
->X_op
= O_symbol
;
7505 r
= BFD_RELOC_32_SECREL
;
7509 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7512 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7513 purpose of the `.dc.a' internal pseudo-op. */
7516 x86_address_bytes (void)
7518 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7520 return stdoutput
->arch_info
->bits_per_address
/ 8;
7523 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7525 # define lex_got(reloc, adjust, types) NULL
7527 /* Parse operands of the form
7528 <symbol>@GOTOFF+<nnn>
7529 and similar .plt or .got references.
7531 If we find one, set up the correct relocation in RELOC and copy the
7532 input string, minus the `@GOTOFF' into a malloc'd buffer for
7533 parsing by the calling routine. Return this buffer, and if ADJUST
7534 is non-null set it to the length of the string we removed from the
7535 input line. Otherwise return NULL. */
7537 lex_got (enum bfd_reloc_code_real
*rel
,
7539 i386_operand_type
*types
)
7541 /* Some of the relocations depend on the size of what field is to
7542 be relocated. But in our callers i386_immediate and i386_displacement
7543 we don't yet know the operand size (this will be set by insn
7544 matching). Hence we record the word32 relocation here,
7545 and adjust the reloc according to the real size in reloc(). */
7546 static const struct {
7549 const enum bfd_reloc_code_real rel
[2];
7550 const i386_operand_type types64
;
7552 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7553 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7555 OPERAND_TYPE_IMM32_64
},
7557 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7558 BFD_RELOC_X86_64_PLTOFF64
},
7559 OPERAND_TYPE_IMM64
},
7560 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7561 BFD_RELOC_X86_64_PLT32
},
7562 OPERAND_TYPE_IMM32_32S_DISP32
},
7563 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7564 BFD_RELOC_X86_64_GOTPLT64
},
7565 OPERAND_TYPE_IMM64_DISP64
},
7566 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7567 BFD_RELOC_X86_64_GOTOFF64
},
7568 OPERAND_TYPE_IMM64_DISP64
},
7569 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7570 BFD_RELOC_X86_64_GOTPCREL
},
7571 OPERAND_TYPE_IMM32_32S_DISP32
},
7572 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7573 BFD_RELOC_X86_64_TLSGD
},
7574 OPERAND_TYPE_IMM32_32S_DISP32
},
7575 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7576 _dummy_first_bfd_reloc_code_real
},
7577 OPERAND_TYPE_NONE
},
7578 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7579 BFD_RELOC_X86_64_TLSLD
},
7580 OPERAND_TYPE_IMM32_32S_DISP32
},
7581 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7582 BFD_RELOC_X86_64_GOTTPOFF
},
7583 OPERAND_TYPE_IMM32_32S_DISP32
},
7584 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7585 BFD_RELOC_X86_64_TPOFF32
},
7586 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7587 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7588 _dummy_first_bfd_reloc_code_real
},
7589 OPERAND_TYPE_NONE
},
7590 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7591 BFD_RELOC_X86_64_DTPOFF32
},
7592 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7593 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7594 _dummy_first_bfd_reloc_code_real
},
7595 OPERAND_TYPE_NONE
},
7596 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7597 _dummy_first_bfd_reloc_code_real
},
7598 OPERAND_TYPE_NONE
},
7599 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7600 BFD_RELOC_X86_64_GOT32
},
7601 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7602 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7603 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7604 OPERAND_TYPE_IMM32_32S_DISP32
},
7605 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7606 BFD_RELOC_X86_64_TLSDESC_CALL
},
7607 OPERAND_TYPE_IMM32_32S_DISP32
},
7612 #if defined (OBJ_MAYBE_ELF)
7617 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7618 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7621 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7623 int len
= gotrel
[j
].len
;
7624 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7626 if (gotrel
[j
].rel
[object_64bit
] != 0)
7629 char *tmpbuf
, *past_reloc
;
7631 *rel
= gotrel
[j
].rel
[object_64bit
];
7635 if (flag_code
!= CODE_64BIT
)
7637 types
->bitfield
.imm32
= 1;
7638 types
->bitfield
.disp32
= 1;
7641 *types
= gotrel
[j
].types64
;
7644 if (j
!= 0 && GOT_symbol
== NULL
)
7645 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7647 /* The length of the first part of our input line. */
7648 first
= cp
- input_line_pointer
;
7650 /* The second part goes from after the reloc token until
7651 (and including) an end_of_line char or comma. */
7652 past_reloc
= cp
+ 1 + len
;
7654 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7656 second
= cp
+ 1 - past_reloc
;
7658 /* Allocate and copy string. The trailing NUL shouldn't
7659 be necessary, but be safe. */
7660 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7661 memcpy (tmpbuf
, input_line_pointer
, first
);
7662 if (second
!= 0 && *past_reloc
!= ' ')
7663 /* Replace the relocation token with ' ', so that
7664 errors like foo@GOTOFF1 will be detected. */
7665 tmpbuf
[first
++] = ' ';
7667 /* Increment length by 1 if the relocation token is
7672 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7673 tmpbuf
[first
+ second
] = '\0';
7677 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7678 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7683 /* Might be a symbol version string. Don't as_bad here. */
7692 /* Parse operands of the form
7693 <symbol>@SECREL32+<nnn>
7695 If we find one, set up the correct relocation in RELOC and copy the
7696 input string, minus the `@SECREL32' into a malloc'd buffer for
7697 parsing by the calling routine. Return this buffer, and if ADJUST
7698 is non-null set it to the length of the string we removed from the
7699 input line. Otherwise return NULL.
7701 This function is copied from the ELF version above adjusted for PE targets. */
7704 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7705 int *adjust ATTRIBUTE_UNUSED
,
7706 i386_operand_type
*types
)
7712 const enum bfd_reloc_code_real rel
[2];
7713 const i386_operand_type types64
;
7717 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7718 BFD_RELOC_32_SECREL
},
7719 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7725 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7726 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7729 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7731 int len
= gotrel
[j
].len
;
7733 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7735 if (gotrel
[j
].rel
[object_64bit
] != 0)
7738 char *tmpbuf
, *past_reloc
;
7740 *rel
= gotrel
[j
].rel
[object_64bit
];
7746 if (flag_code
!= CODE_64BIT
)
7748 types
->bitfield
.imm32
= 1;
7749 types
->bitfield
.disp32
= 1;
7752 *types
= gotrel
[j
].types64
;
7755 /* The length of the first part of our input line. */
7756 first
= cp
- input_line_pointer
;
7758 /* The second part goes from after the reloc token until
7759 (and including) an end_of_line char or comma. */
7760 past_reloc
= cp
+ 1 + len
;
7762 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7764 second
= cp
+ 1 - past_reloc
;
7766 /* Allocate and copy string. The trailing NUL shouldn't
7767 be necessary, but be safe. */
7768 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7769 memcpy (tmpbuf
, input_line_pointer
, first
);
7770 if (second
!= 0 && *past_reloc
!= ' ')
7771 /* Replace the relocation token with ' ', so that
7772 errors like foo@SECLREL321 will be detected. */
7773 tmpbuf
[first
++] = ' ';
7774 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7775 tmpbuf
[first
+ second
] = '\0';
7779 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7780 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7785 /* Might be a symbol version string. Don't as_bad here. */
7791 bfd_reloc_code_real_type
7792 x86_cons (expressionS
*exp
, int size
)
7794 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7796 intel_syntax
= -intel_syntax
;
7799 if (size
== 4 || (object_64bit
&& size
== 8))
7801 /* Handle @GOTOFF and the like in an expression. */
7803 char *gotfree_input_line
;
7806 save
= input_line_pointer
;
7807 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7808 if (gotfree_input_line
)
7809 input_line_pointer
= gotfree_input_line
;
7813 if (gotfree_input_line
)
7815 /* expression () has merrily parsed up to the end of line,
7816 or a comma - in the wrong buffer. Transfer how far
7817 input_line_pointer has moved to the right buffer. */
7818 input_line_pointer
= (save
7819 + (input_line_pointer
- gotfree_input_line
)
7821 free (gotfree_input_line
);
7822 if (exp
->X_op
== O_constant
7823 || exp
->X_op
== O_absent
7824 || exp
->X_op
== O_illegal
7825 || exp
->X_op
== O_register
7826 || exp
->X_op
== O_big
)
7828 char c
= *input_line_pointer
;
7829 *input_line_pointer
= 0;
7830 as_bad (_("missing or invalid expression `%s'"), save
);
7831 *input_line_pointer
= c
;
7838 intel_syntax
= -intel_syntax
;
7841 i386_intel_simplify (exp
);
7847 signed_cons (int size
)
7849 if (flag_code
== CODE_64BIT
)
7857 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7864 if (exp
.X_op
== O_symbol
)
7865 exp
.X_op
= O_secrel
;
7867 emit_expr (&exp
, 4);
7869 while (*input_line_pointer
++ == ',');
7871 input_line_pointer
--;
7872 demand_empty_rest_of_line ();
7876 /* Handle Vector operations. */
7879 check_VecOperations (char *op_string
, char *op_end
)
7881 const reg_entry
*mask
;
7886 && (op_end
== NULL
|| op_string
< op_end
))
7889 if (*op_string
== '{')
7893 /* Check broadcasts. */
7894 if (strncmp (op_string
, "1to", 3) == 0)
7899 goto duplicated_vec_op
;
7902 if (*op_string
== '8')
7903 bcst_type
= BROADCAST_1TO8
;
7904 else if (*op_string
== '4')
7905 bcst_type
= BROADCAST_1TO4
;
7906 else if (*op_string
== '2')
7907 bcst_type
= BROADCAST_1TO2
;
7908 else if (*op_string
== '1'
7909 && *(op_string
+1) == '6')
7911 bcst_type
= BROADCAST_1TO16
;
7916 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7921 broadcast_op
.type
= bcst_type
;
7922 broadcast_op
.operand
= this_operand
;
7923 i
.broadcast
= &broadcast_op
;
7925 /* Check masking operation. */
7926 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7928 /* k0 can't be used for write mask. */
7929 if (mask
->reg_num
== 0)
7931 as_bad (_("`%s' can't be used for write mask"),
7938 mask_op
.mask
= mask
;
7939 mask_op
.zeroing
= 0;
7940 mask_op
.operand
= this_operand
;
7946 goto duplicated_vec_op
;
7948 i
.mask
->mask
= mask
;
7950 /* Only "{z}" is allowed here. No need to check
7951 zeroing mask explicitly. */
7952 if (i
.mask
->operand
!= this_operand
)
7954 as_bad (_("invalid write mask `%s'"), saved
);
7961 /* Check zeroing-flag for masking operation. */
7962 else if (*op_string
== 'z')
7966 mask_op
.mask
= NULL
;
7967 mask_op
.zeroing
= 1;
7968 mask_op
.operand
= this_operand
;
7973 if (i
.mask
->zeroing
)
7976 as_bad (_("duplicated `%s'"), saved
);
7980 i
.mask
->zeroing
= 1;
7982 /* Only "{%k}" is allowed here. No need to check mask
7983 register explicitly. */
7984 if (i
.mask
->operand
!= this_operand
)
7986 as_bad (_("invalid zeroing-masking `%s'"),
7995 goto unknown_vec_op
;
7997 if (*op_string
!= '}')
7999 as_bad (_("missing `}' in `%s'"), saved
);
8006 /* We don't know this one. */
8007 as_bad (_("unknown vector operation: `%s'"), saved
);
8015 i386_immediate (char *imm_start
)
8017 char *save_input_line_pointer
;
8018 char *gotfree_input_line
;
8021 i386_operand_type types
;
8023 operand_type_set (&types
, ~0);
8025 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8027 as_bad (_("at most %d immediate operands are allowed"),
8028 MAX_IMMEDIATE_OPERANDS
);
8032 exp
= &im_expressions
[i
.imm_operands
++];
8033 i
.op
[this_operand
].imms
= exp
;
8035 if (is_space_char (*imm_start
))
8038 save_input_line_pointer
= input_line_pointer
;
8039 input_line_pointer
= imm_start
;
8041 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8042 if (gotfree_input_line
)
8043 input_line_pointer
= gotfree_input_line
;
8045 exp_seg
= expression (exp
);
8049 /* Handle vector operations. */
8050 if (*input_line_pointer
== '{')
8052 input_line_pointer
= check_VecOperations (input_line_pointer
,
8054 if (input_line_pointer
== NULL
)
8058 if (*input_line_pointer
)
8059 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8061 input_line_pointer
= save_input_line_pointer
;
8062 if (gotfree_input_line
)
8064 free (gotfree_input_line
);
8066 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8067 exp
->X_op
= O_illegal
;
8070 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8074 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8075 i386_operand_type types
, const char *imm_start
)
8077 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8080 as_bad (_("missing or invalid immediate expression `%s'"),
8084 else if (exp
->X_op
== O_constant
)
8086 /* Size it properly later. */
8087 i
.types
[this_operand
].bitfield
.imm64
= 1;
8088 /* If not 64bit, sign extend val. */
8089 if (flag_code
!= CODE_64BIT
8090 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8092 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8094 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8095 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8096 && exp_seg
!= absolute_section
8097 && exp_seg
!= text_section
8098 && exp_seg
!= data_section
8099 && exp_seg
!= bss_section
8100 && exp_seg
!= undefined_section
8101 && !bfd_is_com_section (exp_seg
))
8103 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8107 else if (!intel_syntax
&& exp_seg
== reg_section
)
8110 as_bad (_("illegal immediate register operand %s"), imm_start
);
8115 /* This is an address. The size of the address will be
8116 determined later, depending on destination register,
8117 suffix, or the default for the section. */
8118 i
.types
[this_operand
].bitfield
.imm8
= 1;
8119 i
.types
[this_operand
].bitfield
.imm16
= 1;
8120 i
.types
[this_operand
].bitfield
.imm32
= 1;
8121 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8122 i
.types
[this_operand
].bitfield
.imm64
= 1;
8123 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8131 i386_scale (char *scale
)
8134 char *save
= input_line_pointer
;
8136 input_line_pointer
= scale
;
8137 val
= get_absolute_expression ();
8142 i
.log2_scale_factor
= 0;
8145 i
.log2_scale_factor
= 1;
8148 i
.log2_scale_factor
= 2;
8151 i
.log2_scale_factor
= 3;
8155 char sep
= *input_line_pointer
;
8157 *input_line_pointer
= '\0';
8158 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8160 *input_line_pointer
= sep
;
8161 input_line_pointer
= save
;
8165 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8167 as_warn (_("scale factor of %d without an index register"),
8168 1 << i
.log2_scale_factor
);
8169 i
.log2_scale_factor
= 0;
8171 scale
= input_line_pointer
;
8172 input_line_pointer
= save
;
8177 i386_displacement (char *disp_start
, char *disp_end
)
8181 char *save_input_line_pointer
;
8182 char *gotfree_input_line
;
8184 i386_operand_type bigdisp
, types
= anydisp
;
8187 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8189 as_bad (_("at most %d displacement operands are allowed"),
8190 MAX_MEMORY_OPERANDS
);
8194 operand_type_set (&bigdisp
, 0);
8195 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8196 || (!current_templates
->start
->opcode_modifier
.jump
8197 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8199 bigdisp
.bitfield
.disp32
= 1;
8200 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8201 if (flag_code
== CODE_64BIT
)
8205 bigdisp
.bitfield
.disp32s
= 1;
8206 bigdisp
.bitfield
.disp64
= 1;
8209 else if ((flag_code
== CODE_16BIT
) ^ override
)
8211 bigdisp
.bitfield
.disp32
= 0;
8212 bigdisp
.bitfield
.disp16
= 1;
8217 /* For PC-relative branches, the width of the displacement
8218 is dependent upon data size, not address size. */
8219 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8220 if (flag_code
== CODE_64BIT
)
8222 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8223 bigdisp
.bitfield
.disp16
= 1;
8226 bigdisp
.bitfield
.disp32
= 1;
8227 bigdisp
.bitfield
.disp32s
= 1;
8233 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8235 : LONG_MNEM_SUFFIX
));
8236 bigdisp
.bitfield
.disp32
= 1;
8237 if ((flag_code
== CODE_16BIT
) ^ override
)
8239 bigdisp
.bitfield
.disp32
= 0;
8240 bigdisp
.bitfield
.disp16
= 1;
8244 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8247 exp
= &disp_expressions
[i
.disp_operands
];
8248 i
.op
[this_operand
].disps
= exp
;
8250 save_input_line_pointer
= input_line_pointer
;
8251 input_line_pointer
= disp_start
;
8252 END_STRING_AND_SAVE (disp_end
);
8254 #ifndef GCC_ASM_O_HACK
8255 #define GCC_ASM_O_HACK 0
8258 END_STRING_AND_SAVE (disp_end
+ 1);
8259 if (i
.types
[this_operand
].bitfield
.baseIndex
8260 && displacement_string_end
[-1] == '+')
8262 /* This hack is to avoid a warning when using the "o"
8263 constraint within gcc asm statements.
8266 #define _set_tssldt_desc(n,addr,limit,type) \
8267 __asm__ __volatile__ ( \
8269 "movw %w1,2+%0\n\t" \
8271 "movb %b1,4+%0\n\t" \
8272 "movb %4,5+%0\n\t" \
8273 "movb $0,6+%0\n\t" \
8274 "movb %h1,7+%0\n\t" \
8276 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8278 This works great except that the output assembler ends
8279 up looking a bit weird if it turns out that there is
8280 no offset. You end up producing code that looks like:
8293 So here we provide the missing zero. */
8295 *displacement_string_end
= '0';
8298 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8299 if (gotfree_input_line
)
8300 input_line_pointer
= gotfree_input_line
;
8302 exp_seg
= expression (exp
);
8305 if (*input_line_pointer
)
8306 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8308 RESTORE_END_STRING (disp_end
+ 1);
8310 input_line_pointer
= save_input_line_pointer
;
8311 if (gotfree_input_line
)
8313 free (gotfree_input_line
);
8315 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8316 exp
->X_op
= O_illegal
;
8319 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8321 RESTORE_END_STRING (disp_end
);
8327 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8328 i386_operand_type types
, const char *disp_start
)
8330 i386_operand_type bigdisp
;
8333 /* We do this to make sure that the section symbol is in
8334 the symbol table. We will ultimately change the relocation
8335 to be relative to the beginning of the section. */
8336 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8337 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8338 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8340 if (exp
->X_op
!= O_symbol
)
8343 if (S_IS_LOCAL (exp
->X_add_symbol
)
8344 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8345 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8346 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8347 exp
->X_op
= O_subtract
;
8348 exp
->X_op_symbol
= GOT_symbol
;
8349 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8350 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8351 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8352 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8354 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8357 else if (exp
->X_op
== O_absent
8358 || exp
->X_op
== O_illegal
8359 || exp
->X_op
== O_big
)
8362 as_bad (_("missing or invalid displacement expression `%s'"),
8367 else if (flag_code
== CODE_64BIT
8368 && !i
.prefix
[ADDR_PREFIX
]
8369 && exp
->X_op
== O_constant
)
8371 /* Since displacement is signed extended to 64bit, don't allow
8372 disp32 and turn off disp32s if they are out of range. */
8373 i
.types
[this_operand
].bitfield
.disp32
= 0;
8374 if (!fits_in_signed_long (exp
->X_add_number
))
8376 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8377 if (i
.types
[this_operand
].bitfield
.baseindex
)
8379 as_bad (_("0x%lx out range of signed 32bit displacement"),
8380 (long) exp
->X_add_number
);
8386 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8387 else if (exp
->X_op
!= O_constant
8388 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8389 && exp_seg
!= absolute_section
8390 && exp_seg
!= text_section
8391 && exp_seg
!= data_section
8392 && exp_seg
!= bss_section
8393 && exp_seg
!= undefined_section
8394 && !bfd_is_com_section (exp_seg
))
8396 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8401 /* Check if this is a displacement only operand. */
8402 bigdisp
= i
.types
[this_operand
];
8403 bigdisp
.bitfield
.disp8
= 0;
8404 bigdisp
.bitfield
.disp16
= 0;
8405 bigdisp
.bitfield
.disp32
= 0;
8406 bigdisp
.bitfield
.disp32s
= 0;
8407 bigdisp
.bitfield
.disp64
= 0;
8408 if (operand_type_all_zero (&bigdisp
))
8409 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8415 /* Make sure the memory operand we've been dealt is valid.
8416 Return 1 on success, 0 on a failure. */
8419 i386_index_check (const char *operand_string
)
8421 const char *kind
= "base/index";
8422 enum flag_code addr_mode
;
8424 if (i
.prefix
[ADDR_PREFIX
])
8425 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8428 addr_mode
= flag_code
;
8430 #if INFER_ADDR_PREFIX
8431 if (i
.mem_operands
== 0)
8433 /* Infer address prefix from the first memory operand. */
8434 const reg_entry
*addr_reg
= i
.base_reg
;
8436 if (addr_reg
== NULL
)
8437 addr_reg
= i
.index_reg
;
8441 if (addr_reg
->reg_num
== RegEip
8442 || addr_reg
->reg_num
== RegEiz
8443 || addr_reg
->reg_type
.bitfield
.reg32
)
8444 addr_mode
= CODE_32BIT
;
8445 else if (flag_code
!= CODE_64BIT
8446 && addr_reg
->reg_type
.bitfield
.reg16
)
8447 addr_mode
= CODE_16BIT
;
8449 if (addr_mode
!= flag_code
)
8451 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8453 /* Change the size of any displacement too. At most one
8454 of Disp16 or Disp32 is set.
8455 FIXME. There doesn't seem to be any real need for
8456 separate Disp16 and Disp32 flags. The same goes for
8457 Imm16 and Imm32. Removing them would probably clean
8458 up the code quite a lot. */
8459 if (flag_code
!= CODE_64BIT
8460 && (i
.types
[this_operand
].bitfield
.disp16
8461 || i
.types
[this_operand
].bitfield
.disp32
))
8462 i
.types
[this_operand
]
8463 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8470 if (current_templates
->start
->opcode_modifier
.isstring
8471 && !current_templates
->start
->opcode_modifier
.immext
8472 && (current_templates
->end
[-1].opcode_modifier
.isstring
8475 /* Memory operands of string insns are special in that they only allow
8476 a single register (rDI, rSI, or rBX) as their memory address. */
8477 const reg_entry
*expected_reg
;
8478 static const char *di_si
[][2] =
8484 static const char *bx
[] = { "ebx", "bx", "rbx" };
8486 kind
= "string address";
8488 if (current_templates
->start
->opcode_modifier
.w
)
8490 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8492 if (!type
.bitfield
.baseindex
8493 || ((!i
.mem_operands
!= !intel_syntax
)
8494 && current_templates
->end
[-1].operand_types
[1]
8495 .bitfield
.baseindex
))
8496 type
= current_templates
->end
[-1].operand_types
[1];
8497 expected_reg
= hash_find (reg_hash
,
8498 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8502 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8504 if (i
.base_reg
!= expected_reg
8506 || operand_type_check (i
.types
[this_operand
], disp
))
8508 /* The second memory operand must have the same size as
8512 && !((addr_mode
== CODE_64BIT
8513 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8514 || (addr_mode
== CODE_32BIT
8515 ? i
.base_reg
->reg_type
.bitfield
.reg32
8516 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8519 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8521 intel_syntax
? '[' : '(',
8523 expected_reg
->reg_name
,
8524 intel_syntax
? ']' : ')');
8531 as_bad (_("`%s' is not a valid %s expression"),
8532 operand_string
, kind
);
8537 if (addr_mode
!= CODE_16BIT
)
8539 /* 32-bit/64-bit checks. */
8541 && (addr_mode
== CODE_64BIT
8542 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8543 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8545 || (i
.base_reg
->reg_num
8546 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8548 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8549 && !i
.index_reg
->reg_type
.bitfield
.regymm
8550 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8551 && ((addr_mode
== CODE_64BIT
8552 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8553 || i
.index_reg
->reg_num
== RegRiz
)
8554 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8555 || i
.index_reg
->reg_num
== RegEiz
))
8556 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8561 /* 16-bit checks. */
8563 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8564 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8566 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8567 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8569 && i
.base_reg
->reg_num
< 6
8570 && i
.index_reg
->reg_num
>= 6
8571 && i
.log2_scale_factor
== 0))))
8578 /* Handle vector immediates. */
8581 RC_SAE_immediate (const char *imm_start
)
8583 unsigned int match_found
, j
;
8584 const char *pstr
= imm_start
;
8592 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8594 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8598 rc_op
.type
= RC_NamesTable
[j
].type
;
8599 rc_op
.operand
= this_operand
;
8600 i
.rounding
= &rc_op
;
8604 as_bad (_("duplicated `%s'"), imm_start
);
8607 pstr
+= RC_NamesTable
[j
].len
;
8617 as_bad (_("Missing '}': '%s'"), imm_start
);
8620 /* RC/SAE immediate string should contain nothing more. */;
8623 as_bad (_("Junk after '}': '%s'"), imm_start
);
8627 exp
= &im_expressions
[i
.imm_operands
++];
8628 i
.op
[this_operand
].imms
= exp
;
8630 exp
->X_op
= O_constant
;
8631 exp
->X_add_number
= 0;
8632 exp
->X_add_symbol
= (symbolS
*) 0;
8633 exp
->X_op_symbol
= (symbolS
*) 0;
8635 i
.types
[this_operand
].bitfield
.imm8
= 1;
8639 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8643 i386_att_operand (char *operand_string
)
8647 char *op_string
= operand_string
;
8649 if (is_space_char (*op_string
))
8652 /* We check for an absolute prefix (differentiating,
8653 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8654 if (*op_string
== ABSOLUTE_PREFIX
)
8657 if (is_space_char (*op_string
))
8659 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8662 /* Check if operand is a register. */
8663 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8665 i386_operand_type temp
;
8667 /* Check for a segment override by searching for ':' after a
8668 segment register. */
8670 if (is_space_char (*op_string
))
8672 if (*op_string
== ':'
8673 && (r
->reg_type
.bitfield
.sreg2
8674 || r
->reg_type
.bitfield
.sreg3
))
8679 i
.seg
[i
.mem_operands
] = &es
;
8682 i
.seg
[i
.mem_operands
] = &cs
;
8685 i
.seg
[i
.mem_operands
] = &ss
;
8688 i
.seg
[i
.mem_operands
] = &ds
;
8691 i
.seg
[i
.mem_operands
] = &fs
;
8694 i
.seg
[i
.mem_operands
] = &gs
;
8698 /* Skip the ':' and whitespace. */
8700 if (is_space_char (*op_string
))
8703 if (!is_digit_char (*op_string
)
8704 && !is_identifier_char (*op_string
)
8705 && *op_string
!= '('
8706 && *op_string
!= ABSOLUTE_PREFIX
)
8708 as_bad (_("bad memory operand `%s'"), op_string
);
8711 /* Handle case of %es:*foo. */
8712 if (*op_string
== ABSOLUTE_PREFIX
)
8715 if (is_space_char (*op_string
))
8717 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8719 goto do_memory_reference
;
8722 /* Handle vector operations. */
8723 if (*op_string
== '{')
8725 op_string
= check_VecOperations (op_string
, NULL
);
8726 if (op_string
== NULL
)
8732 as_bad (_("junk `%s' after register"), op_string
);
8736 temp
.bitfield
.baseindex
= 0;
8737 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8739 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8740 i
.op
[this_operand
].regs
= r
;
8743 else if (*op_string
== REGISTER_PREFIX
)
8745 as_bad (_("bad register name `%s'"), op_string
);
8748 else if (*op_string
== IMMEDIATE_PREFIX
)
8751 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8753 as_bad (_("immediate operand illegal with absolute jump"));
8756 if (!i386_immediate (op_string
))
8759 else if (RC_SAE_immediate (operand_string
))
8761 /* If it is a RC or SAE immediate, do nothing. */
8764 else if (is_digit_char (*op_string
)
8765 || is_identifier_char (*op_string
)
8766 || *op_string
== '"'
8767 || *op_string
== '(')
8769 /* This is a memory reference of some sort. */
8772 /* Start and end of displacement string expression (if found). */
8773 char *displacement_string_start
;
8774 char *displacement_string_end
;
8777 do_memory_reference
:
8778 if ((i
.mem_operands
== 1
8779 && !current_templates
->start
->opcode_modifier
.isstring
)
8780 || i
.mem_operands
== 2)
8782 as_bad (_("too many memory references for `%s'"),
8783 current_templates
->start
->name
);
8787 /* Check for base index form. We detect the base index form by
8788 looking for an ')' at the end of the operand, searching
8789 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8791 base_string
= op_string
+ strlen (op_string
);
8793 /* Handle vector operations. */
8794 vop_start
= strchr (op_string
, '{');
8795 if (vop_start
&& vop_start
< base_string
)
8797 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8799 base_string
= vop_start
;
8803 if (is_space_char (*base_string
))
8806 /* If we only have a displacement, set-up for it to be parsed later. */
8807 displacement_string_start
= op_string
;
8808 displacement_string_end
= base_string
+ 1;
8810 if (*base_string
== ')')
8813 unsigned int parens_balanced
= 1;
8814 /* We've already checked that the number of left & right ()'s are
8815 equal, so this loop will not be infinite. */
8819 if (*base_string
== ')')
8821 if (*base_string
== '(')
8824 while (parens_balanced
);
8826 temp_string
= base_string
;
8828 /* Skip past '(' and whitespace. */
8830 if (is_space_char (*base_string
))
8833 if (*base_string
== ','
8834 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8837 displacement_string_end
= temp_string
;
8839 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8843 base_string
= end_op
;
8844 if (is_space_char (*base_string
))
8848 /* There may be an index reg or scale factor here. */
8849 if (*base_string
== ',')
8852 if (is_space_char (*base_string
))
8855 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8858 base_string
= end_op
;
8859 if (is_space_char (*base_string
))
8861 if (*base_string
== ',')
8864 if (is_space_char (*base_string
))
8867 else if (*base_string
!= ')')
8869 as_bad (_("expecting `,' or `)' "
8870 "after index register in `%s'"),
8875 else if (*base_string
== REGISTER_PREFIX
)
8877 end_op
= strchr (base_string
, ',');
8880 as_bad (_("bad register name `%s'"), base_string
);
8884 /* Check for scale factor. */
8885 if (*base_string
!= ')')
8887 char *end_scale
= i386_scale (base_string
);
8892 base_string
= end_scale
;
8893 if (is_space_char (*base_string
))
8895 if (*base_string
!= ')')
8897 as_bad (_("expecting `)' "
8898 "after scale factor in `%s'"),
8903 else if (!i
.index_reg
)
8905 as_bad (_("expecting index register or scale factor "
8906 "after `,'; got '%c'"),
8911 else if (*base_string
!= ')')
8913 as_bad (_("expecting `,' or `)' "
8914 "after base register in `%s'"),
8919 else if (*base_string
== REGISTER_PREFIX
)
8921 end_op
= strchr (base_string
, ',');
8924 as_bad (_("bad register name `%s'"), base_string
);
8929 /* If there's an expression beginning the operand, parse it,
8930 assuming displacement_string_start and
8931 displacement_string_end are meaningful. */
8932 if (displacement_string_start
!= displacement_string_end
)
8934 if (!i386_displacement (displacement_string_start
,
8935 displacement_string_end
))
8939 /* Special case for (%dx) while doing input/output op. */
8941 && operand_type_equal (&i
.base_reg
->reg_type
,
8942 ®16_inoutportreg
)
8944 && i
.log2_scale_factor
== 0
8945 && i
.seg
[i
.mem_operands
] == 0
8946 && !operand_type_check (i
.types
[this_operand
], disp
))
8948 i
.types
[this_operand
] = inoutportreg
;
8952 if (i386_index_check (operand_string
) == 0)
8954 i
.types
[this_operand
].bitfield
.mem
= 1;
8959 /* It's not a memory operand; argh! */
8960 as_bad (_("invalid char %s beginning operand %d `%s'"),
8961 output_invalid (*op_string
),
8966 return 1; /* Normal return. */
8969 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8970 that an rs_machine_dependent frag may reach. */
8973 i386_frag_max_var (fragS
*frag
)
8975 /* The only relaxable frags are for jumps.
8976 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8977 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8978 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8981 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8983 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
8985 /* STT_GNU_IFUNC symbol must go through PLT. */
8986 if ((symbol_get_bfdsym (fr_symbol
)->flags
8987 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
8990 if (!S_IS_EXTERNAL (fr_symbol
))
8991 /* Symbol may be weak or local. */
8992 return !S_IS_WEAK (fr_symbol
);
8994 /* Global symbols with non-default visibility can't be preempted. */
8995 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
8998 if (fr_var
!= NO_RELOC
)
8999 switch ((enum bfd_reloc_code_real
) fr_var
)
9001 case BFD_RELOC_386_PLT32
:
9002 case BFD_RELOC_X86_64_PLT32
:
9003 /* Symbol with PLT relocatin may be preempted. */
9009 /* Global symbols with default visibility in a shared library may be
9010 preempted by another definition. */
9015 /* md_estimate_size_before_relax()
9017 Called just before relax() for rs_machine_dependent frags. The x86
9018 assembler uses these frags to handle variable size jump
9021 Any symbol that is now undefined will not become defined.
9022 Return the correct fr_subtype in the frag.
9023 Return the initial "guess for variable size of frag" to caller.
9024 The guess is actually the growth beyond the fixed part. Whatever
9025 we do to grow the fixed or variable part contributes to our
9029 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9031 /* We've already got fragP->fr_subtype right; all we have to do is
9032 check for un-relaxable symbols. On an ELF system, we can't relax
9033 an externally visible symbol, because it may be overridden by a
9035 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9036 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9038 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9041 #if defined (OBJ_COFF) && defined (TE_PE)
9042 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9043 && S_IS_WEAK (fragP
->fr_symbol
))
9047 /* Symbol is undefined in this segment, or we need to keep a
9048 reloc so that weak symbols can be overridden. */
9049 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9050 enum bfd_reloc_code_real reloc_type
;
9051 unsigned char *opcode
;
9054 if (fragP
->fr_var
!= NO_RELOC
)
9055 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9057 reloc_type
= BFD_RELOC_16_PCREL
;
9059 reloc_type
= BFD_RELOC_32_PCREL
;
9061 old_fr_fix
= fragP
->fr_fix
;
9062 opcode
= (unsigned char *) fragP
->fr_opcode
;
9064 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9067 /* Make jmp (0xeb) a (d)word displacement jump. */
9069 fragP
->fr_fix
+= size
;
9070 fix_new (fragP
, old_fr_fix
, size
,
9072 fragP
->fr_offset
, 1,
9078 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9080 /* Negate the condition, and branch past an
9081 unconditional jump. */
9084 /* Insert an unconditional jump. */
9086 /* We added two extra opcode bytes, and have a two byte
9088 fragP
->fr_fix
+= 2 + 2;
9089 fix_new (fragP
, old_fr_fix
+ 2, 2,
9091 fragP
->fr_offset
, 1,
9098 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9103 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9105 fragP
->fr_offset
, 1,
9107 fixP
->fx_signed
= 1;
9111 /* This changes the byte-displacement jump 0x7N
9112 to the (d)word-displacement jump 0x0f,0x8N. */
9113 opcode
[1] = opcode
[0] + 0x10;
9114 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9115 /* We've added an opcode byte. */
9116 fragP
->fr_fix
+= 1 + size
;
9117 fix_new (fragP
, old_fr_fix
+ 1, size
,
9119 fragP
->fr_offset
, 1,
9124 BAD_CASE (fragP
->fr_subtype
);
9128 return fragP
->fr_fix
- old_fr_fix
;
9131 /* Guess size depending on current relax state. Initially the relax
9132 state will correspond to a short jump and we return 1, because
9133 the variable part of the frag (the branch offset) is one byte
9134 long. However, we can relax a section more than once and in that
9135 case we must either set fr_subtype back to the unrelaxed state,
9136 or return the value for the appropriate branch. */
9137 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9140 /* Called after relax() is finished.
9142 In: Address of frag.
9143 fr_type == rs_machine_dependent.
9144 fr_subtype is what the address relaxed to.
9146 Out: Any fixSs and constants are set up.
9147 Caller will turn frag into a ".space 0". */
9150 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9153 unsigned char *opcode
;
9154 unsigned char *where_to_put_displacement
= NULL
;
9155 offsetT target_address
;
9156 offsetT opcode_address
;
9157 unsigned int extension
= 0;
9158 offsetT displacement_from_opcode_start
;
9160 opcode
= (unsigned char *) fragP
->fr_opcode
;
9162 /* Address we want to reach in file space. */
9163 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9165 /* Address opcode resides at in file space. */
9166 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9168 /* Displacement from opcode start to fill into instruction. */
9169 displacement_from_opcode_start
= target_address
- opcode_address
;
9171 if ((fragP
->fr_subtype
& BIG
) == 0)
9173 /* Don't have to change opcode. */
9174 extension
= 1; /* 1 opcode + 1 displacement */
9175 where_to_put_displacement
= &opcode
[1];
9179 if (no_cond_jump_promotion
9180 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9181 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9182 _("long jump required"));
9184 switch (fragP
->fr_subtype
)
9186 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9187 extension
= 4; /* 1 opcode + 4 displacement */
9189 where_to_put_displacement
= &opcode
[1];
9192 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9193 extension
= 2; /* 1 opcode + 2 displacement */
9195 where_to_put_displacement
= &opcode
[1];
9198 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9199 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9200 extension
= 5; /* 2 opcode + 4 displacement */
9201 opcode
[1] = opcode
[0] + 0x10;
9202 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9203 where_to_put_displacement
= &opcode
[2];
9206 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9207 extension
= 3; /* 2 opcode + 2 displacement */
9208 opcode
[1] = opcode
[0] + 0x10;
9209 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9210 where_to_put_displacement
= &opcode
[2];
9213 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9218 where_to_put_displacement
= &opcode
[3];
9222 BAD_CASE (fragP
->fr_subtype
);
9227 /* If size if less then four we are sure that the operand fits,
9228 but if it's 4, then it could be that the displacement is larger
9230 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9232 && ((addressT
) (displacement_from_opcode_start
- extension
9233 + ((addressT
) 1 << 31))
9234 > (((addressT
) 2 << 31) - 1)))
9236 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9237 _("jump target out of range"));
9238 /* Make us emit 0. */
9239 displacement_from_opcode_start
= extension
;
9241 /* Now put displacement after opcode. */
9242 md_number_to_chars ((char *) where_to_put_displacement
,
9243 (valueT
) (displacement_from_opcode_start
- extension
),
9244 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9245 fragP
->fr_fix
+= extension
;
9248 /* Apply a fixup (fixP) to segment data, once it has been determined
9249 by our caller that we have all the info we need to fix it up.
9251 Parameter valP is the pointer to the value of the bits.
9253 On the 386, immediates, displacements, and data pointers are all in
9254 the same (little-endian) format, so we don't need to care about which
9258 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9260 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9261 valueT value
= *valP
;
9263 #if !defined (TE_Mach)
9266 switch (fixP
->fx_r_type
)
9272 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9275 case BFD_RELOC_X86_64_32S
:
9276 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9279 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9282 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9287 if (fixP
->fx_addsy
!= NULL
9288 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9289 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9290 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9291 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9292 && !use_rela_relocations
)
9294 /* This is a hack. There should be a better way to handle this.
9295 This covers for the fact that bfd_install_relocation will
9296 subtract the current location (for partial_inplace, PC relative
9297 relocations); see more below. */
9301 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9304 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9306 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9309 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9312 || (symbol_section_p (fixP
->fx_addsy
)
9313 && sym_seg
!= absolute_section
))
9314 && !generic_force_reloc (fixP
))
9316 /* Yes, we add the values in twice. This is because
9317 bfd_install_relocation subtracts them out again. I think
9318 bfd_install_relocation is broken, but I don't dare change
9320 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9324 #if defined (OBJ_COFF) && defined (TE_PE)
9325 /* For some reason, the PE format does not store a
9326 section address offset for a PC relative symbol. */
9327 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9328 || S_IS_WEAK (fixP
->fx_addsy
))
9329 value
+= md_pcrel_from (fixP
);
9332 #if defined (OBJ_COFF) && defined (TE_PE)
9333 if (fixP
->fx_addsy
!= NULL
9334 && S_IS_WEAK (fixP
->fx_addsy
)
9335 /* PR 16858: Do not modify weak function references. */
9336 && ! fixP
->fx_pcrel
)
9338 #if !defined (TE_PEP)
9339 /* For x86 PE weak function symbols are neither PC-relative
9340 nor do they set S_IS_FUNCTION. So the only reliable way
9341 to detect them is to check the flags of their containing
9343 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9344 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9348 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9352 /* Fix a few things - the dynamic linker expects certain values here,
9353 and we must not disappoint it. */
9354 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9355 if (IS_ELF
&& fixP
->fx_addsy
)
9356 switch (fixP
->fx_r_type
)
9358 case BFD_RELOC_386_PLT32
:
9359 case BFD_RELOC_X86_64_PLT32
:
9360 /* Make the jump instruction point to the address of the operand. At
9361 runtime we merely add the offset to the actual PLT entry. */
9365 case BFD_RELOC_386_TLS_GD
:
9366 case BFD_RELOC_386_TLS_LDM
:
9367 case BFD_RELOC_386_TLS_IE_32
:
9368 case BFD_RELOC_386_TLS_IE
:
9369 case BFD_RELOC_386_TLS_GOTIE
:
9370 case BFD_RELOC_386_TLS_GOTDESC
:
9371 case BFD_RELOC_X86_64_TLSGD
:
9372 case BFD_RELOC_X86_64_TLSLD
:
9373 case BFD_RELOC_X86_64_GOTTPOFF
:
9374 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9375 value
= 0; /* Fully resolved at runtime. No addend. */
9377 case BFD_RELOC_386_TLS_LE
:
9378 case BFD_RELOC_386_TLS_LDO_32
:
9379 case BFD_RELOC_386_TLS_LE_32
:
9380 case BFD_RELOC_X86_64_DTPOFF32
:
9381 case BFD_RELOC_X86_64_DTPOFF64
:
9382 case BFD_RELOC_X86_64_TPOFF32
:
9383 case BFD_RELOC_X86_64_TPOFF64
:
9384 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9387 case BFD_RELOC_386_TLS_DESC_CALL
:
9388 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9389 value
= 0; /* Fully resolved at runtime. No addend. */
9390 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9394 case BFD_RELOC_VTABLE_INHERIT
:
9395 case BFD_RELOC_VTABLE_ENTRY
:
9402 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9404 #endif /* !defined (TE_Mach) */
9406 /* Are we finished with this relocation now? */
9407 if (fixP
->fx_addsy
== NULL
)
9409 #if defined (OBJ_COFF) && defined (TE_PE)
9410 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9413 /* Remember value for tc_gen_reloc. */
9414 fixP
->fx_addnumber
= value
;
9415 /* Clear out the frag for now. */
9419 else if (use_rela_relocations
)
9421 fixP
->fx_no_overflow
= 1;
9422 /* Remember value for tc_gen_reloc. */
9423 fixP
->fx_addnumber
= value
;
9427 md_number_to_chars (p
, value
, fixP
->fx_size
);
9431 md_atof (int type
, char *litP
, int *sizeP
)
9433 /* This outputs the LITTLENUMs in REVERSE order;
9434 in accord with the bigendian 386. */
9435 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9438 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9441 output_invalid (int c
)
9444 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9447 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9448 "(0x%x)", (unsigned char) c
);
9449 return output_invalid_buf
;
9452 /* REG_STRING starts *before* REGISTER_PREFIX. */
9454 static const reg_entry
*
9455 parse_real_register (char *reg_string
, char **end_op
)
9457 char *s
= reg_string
;
9459 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9462 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9463 if (*s
== REGISTER_PREFIX
)
9466 if (is_space_char (*s
))
9470 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9472 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9473 return (const reg_entry
*) NULL
;
9477 /* For naked regs, make sure that we are not dealing with an identifier.
9478 This prevents confusing an identifier like `eax_var' with register
9480 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9481 return (const reg_entry
*) NULL
;
9485 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9487 /* Handle floating point regs, allowing spaces in the (i) part. */
9488 if (r
== i386_regtab
/* %st is first entry of table */)
9490 if (is_space_char (*s
))
9495 if (is_space_char (*s
))
9497 if (*s
>= '0' && *s
<= '7')
9501 if (is_space_char (*s
))
9506 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9511 /* We have "%st(" then garbage. */
9512 return (const reg_entry
*) NULL
;
9516 if (r
== NULL
|| allow_pseudo_reg
)
9519 if (operand_type_all_zero (&r
->reg_type
))
9520 return (const reg_entry
*) NULL
;
9522 if ((r
->reg_type
.bitfield
.reg32
9523 || r
->reg_type
.bitfield
.sreg3
9524 || r
->reg_type
.bitfield
.control
9525 || r
->reg_type
.bitfield
.debug
9526 || r
->reg_type
.bitfield
.test
)
9527 && !cpu_arch_flags
.bitfield
.cpui386
)
9528 return (const reg_entry
*) NULL
;
9530 if (r
->reg_type
.bitfield
.floatreg
9531 && !cpu_arch_flags
.bitfield
.cpu8087
9532 && !cpu_arch_flags
.bitfield
.cpu287
9533 && !cpu_arch_flags
.bitfield
.cpu387
)
9534 return (const reg_entry
*) NULL
;
9536 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9537 return (const reg_entry
*) NULL
;
9539 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9540 return (const reg_entry
*) NULL
;
9542 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9543 return (const reg_entry
*) NULL
;
9545 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9546 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9547 return (const reg_entry
*) NULL
;
9549 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9550 if (!allow_index_reg
9551 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9552 return (const reg_entry
*) NULL
;
9554 /* Upper 16 vector register is only available with VREX in 64bit
9556 if ((r
->reg_flags
& RegVRex
))
9558 if (!cpu_arch_flags
.bitfield
.cpuvrex
9559 || flag_code
!= CODE_64BIT
)
9560 return (const reg_entry
*) NULL
;
9565 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9566 || r
->reg_type
.bitfield
.reg64
)
9567 && (!cpu_arch_flags
.bitfield
.cpulm
9568 || !operand_type_equal (&r
->reg_type
, &control
))
9569 && flag_code
!= CODE_64BIT
)
9570 return (const reg_entry
*) NULL
;
9572 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9573 return (const reg_entry
*) NULL
;
9578 /* REG_STRING starts *before* REGISTER_PREFIX. */
9580 static const reg_entry
*
9581 parse_register (char *reg_string
, char **end_op
)
9585 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9586 r
= parse_real_register (reg_string
, end_op
);
9591 char *save
= input_line_pointer
;
9595 input_line_pointer
= reg_string
;
9596 c
= get_symbol_name (®_string
);
9597 symbolP
= symbol_find (reg_string
);
9598 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9600 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9602 know (e
->X_op
== O_register
);
9603 know (e
->X_add_number
>= 0
9604 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9605 r
= i386_regtab
+ e
->X_add_number
;
9606 if ((r
->reg_flags
& RegVRex
))
9608 *end_op
= input_line_pointer
;
9610 *input_line_pointer
= c
;
9611 input_line_pointer
= save
;
9617 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9620 char *end
= input_line_pointer
;
9623 r
= parse_register (name
, &input_line_pointer
);
9624 if (r
&& end
<= input_line_pointer
)
9626 *nextcharP
= *input_line_pointer
;
9627 *input_line_pointer
= 0;
9628 e
->X_op
= O_register
;
9629 e
->X_add_number
= r
- i386_regtab
;
9632 input_line_pointer
= end
;
9634 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9638 md_operand (expressionS
*e
)
9643 switch (*input_line_pointer
)
9645 case REGISTER_PREFIX
:
9646 r
= parse_real_register (input_line_pointer
, &end
);
9649 e
->X_op
= O_register
;
9650 e
->X_add_number
= r
- i386_regtab
;
9651 input_line_pointer
= end
;
9656 gas_assert (intel_syntax
);
9657 end
= input_line_pointer
++;
9659 if (*input_line_pointer
== ']')
9661 ++input_line_pointer
;
9662 e
->X_op_symbol
= make_expr_symbol (e
);
9663 e
->X_add_symbol
= NULL
;
9664 e
->X_add_number
= 0;
9670 input_line_pointer
= end
;
9677 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9678 const char *md_shortopts
= "kVQ:sqn";
9680 const char *md_shortopts
= "qn";
9683 #define OPTION_32 (OPTION_MD_BASE + 0)
9684 #define OPTION_64 (OPTION_MD_BASE + 1)
9685 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9686 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9687 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9688 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9689 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9690 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9691 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9692 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9693 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9694 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9695 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9696 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9697 #define OPTION_X32 (OPTION_MD_BASE + 14)
9698 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9699 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9700 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9701 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9702 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9703 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9704 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9705 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9706 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9707 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9708 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
9710 struct option md_longopts
[] =
9712 {"32", no_argument
, NULL
, OPTION_32
},
9713 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9714 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9715 {"64", no_argument
, NULL
, OPTION_64
},
9717 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9718 {"x32", no_argument
, NULL
, OPTION_X32
},
9719 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
9721 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9722 {"march", required_argument
, NULL
, OPTION_MARCH
},
9723 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9724 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9725 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9726 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9727 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9728 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9729 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9730 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9731 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9732 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9733 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9734 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9735 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9736 # if defined (TE_PE) || defined (TE_PEP)
9737 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9739 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
9740 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
9741 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
9742 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9743 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
9744 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
9745 {NULL
, no_argument
, NULL
, 0}
9747 size_t md_longopts_size
= sizeof (md_longopts
);
9750 md_parse_option (int c
, const char *arg
)
9753 char *arch
, *next
, *saved
;
9758 optimize_align_code
= 0;
9765 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9766 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9767 should be emitted or not. FIXME: Not implemented. */
9771 /* -V: SVR4 argument to print version ID. */
9773 print_version_id ();
9776 /* -k: Ignore for FreeBSD compatibility. */
9781 /* -s: On i386 Solaris, this tells the native assembler to use
9782 .stab instead of .stab.excl. We always use .stab anyhow. */
9785 case OPTION_MSHARED
:
9789 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9790 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9793 const char **list
, **l
;
9795 list
= bfd_target_list ();
9796 for (l
= list
; *l
!= NULL
; l
++)
9797 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9798 || strcmp (*l
, "coff-x86-64") == 0
9799 || strcmp (*l
, "pe-x86-64") == 0
9800 || strcmp (*l
, "pei-x86-64") == 0
9801 || strcmp (*l
, "mach-o-x86-64") == 0)
9803 default_arch
= "x86_64";
9807 as_fatal (_("no compiled in support for x86_64"));
9813 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9817 const char **list
, **l
;
9819 list
= bfd_target_list ();
9820 for (l
= list
; *l
!= NULL
; l
++)
9821 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9823 default_arch
= "x86_64:32";
9827 as_fatal (_("no compiled in support for 32bit x86_64"));
9831 as_fatal (_("32bit x86_64 is only supported for ELF"));
9836 default_arch
= "i386";
9840 #ifdef SVR4_COMMENT_CHARS
9845 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
9847 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9851 i386_comment_chars
= n
;
9857 saved
= xstrdup (arg
);
9859 /* Allow -march=+nosse. */
9865 as_fatal (_("invalid -march= option: `%s'"), arg
);
9866 next
= strchr (arch
, '+');
9869 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9871 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9874 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9877 cpu_arch_name
= cpu_arch
[j
].name
;
9878 cpu_sub_arch_name
= NULL
;
9879 cpu_arch_flags
= cpu_arch
[j
].flags
;
9880 cpu_arch_isa
= cpu_arch
[j
].type
;
9881 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9882 if (!cpu_arch_tune_set
)
9884 cpu_arch_tune
= cpu_arch_isa
;
9885 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9889 else if (*cpu_arch
[j
].name
== '.'
9890 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9892 /* ISA entension. */
9893 i386_cpu_flags flags
;
9895 flags
= cpu_flags_or (cpu_arch_flags
,
9898 if (!valid_iamcu_cpu_flags (&flags
))
9899 as_fatal (_("`%s' isn't valid for Intel MCU"), arch
);
9900 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9902 if (cpu_sub_arch_name
)
9904 char *name
= cpu_sub_arch_name
;
9905 cpu_sub_arch_name
= concat (name
,
9907 (const char *) NULL
);
9911 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9912 cpu_arch_flags
= flags
;
9913 cpu_arch_isa_flags
= flags
;
9919 if (j
>= ARRAY_SIZE (cpu_arch
))
9921 /* Disable an ISA entension. */
9922 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
9923 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
9925 i386_cpu_flags flags
;
9927 flags
= cpu_flags_and_not (cpu_arch_flags
,
9928 cpu_noarch
[j
].flags
);
9929 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9931 if (cpu_sub_arch_name
)
9933 char *name
= cpu_sub_arch_name
;
9934 cpu_sub_arch_name
= concat (arch
,
9935 (const char *) NULL
);
9939 cpu_sub_arch_name
= xstrdup (arch
);
9940 cpu_arch_flags
= flags
;
9941 cpu_arch_isa_flags
= flags
;
9946 if (j
>= ARRAY_SIZE (cpu_noarch
))
9947 j
= ARRAY_SIZE (cpu_arch
);
9950 if (j
>= ARRAY_SIZE (cpu_arch
))
9951 as_fatal (_("invalid -march= option: `%s'"), arg
);
9955 while (next
!= NULL
);
9961 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9962 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9964 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9966 cpu_arch_tune_set
= 1;
9967 cpu_arch_tune
= cpu_arch
[j
].type
;
9968 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9972 if (j
>= ARRAY_SIZE (cpu_arch
))
9973 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9976 case OPTION_MMNEMONIC
:
9977 if (strcasecmp (arg
, "att") == 0)
9979 else if (strcasecmp (arg
, "intel") == 0)
9982 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9985 case OPTION_MSYNTAX
:
9986 if (strcasecmp (arg
, "att") == 0)
9988 else if (strcasecmp (arg
, "intel") == 0)
9991 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9994 case OPTION_MINDEX_REG
:
9995 allow_index_reg
= 1;
9998 case OPTION_MNAKED_REG
:
9999 allow_naked_reg
= 1;
10002 case OPTION_MOLD_GCC
:
10006 case OPTION_MSSE2AVX
:
10010 case OPTION_MSSE_CHECK
:
10011 if (strcasecmp (arg
, "error") == 0)
10012 sse_check
= check_error
;
10013 else if (strcasecmp (arg
, "warning") == 0)
10014 sse_check
= check_warning
;
10015 else if (strcasecmp (arg
, "none") == 0)
10016 sse_check
= check_none
;
10018 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10021 case OPTION_MOPERAND_CHECK
:
10022 if (strcasecmp (arg
, "error") == 0)
10023 operand_check
= check_error
;
10024 else if (strcasecmp (arg
, "warning") == 0)
10025 operand_check
= check_warning
;
10026 else if (strcasecmp (arg
, "none") == 0)
10027 operand_check
= check_none
;
10029 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10032 case OPTION_MAVXSCALAR
:
10033 if (strcasecmp (arg
, "128") == 0)
10034 avxscalar
= vex128
;
10035 else if (strcasecmp (arg
, "256") == 0)
10036 avxscalar
= vex256
;
10038 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10041 case OPTION_MADD_BND_PREFIX
:
10042 add_bnd_prefix
= 1;
10045 case OPTION_MEVEXLIG
:
10046 if (strcmp (arg
, "128") == 0)
10047 evexlig
= evexl128
;
10048 else if (strcmp (arg
, "256") == 0)
10049 evexlig
= evexl256
;
10050 else if (strcmp (arg
, "512") == 0)
10051 evexlig
= evexl512
;
10053 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10056 case OPTION_MEVEXRCIG
:
10057 if (strcmp (arg
, "rne") == 0)
10059 else if (strcmp (arg
, "rd") == 0)
10061 else if (strcmp (arg
, "ru") == 0)
10063 else if (strcmp (arg
, "rz") == 0)
10066 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10069 case OPTION_MEVEXWIG
:
10070 if (strcmp (arg
, "0") == 0)
10072 else if (strcmp (arg
, "1") == 0)
10075 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10078 # if defined (TE_PE) || defined (TE_PEP)
10079 case OPTION_MBIG_OBJ
:
10084 case OPTION_MOMIT_LOCK_PREFIX
:
10085 if (strcasecmp (arg
, "yes") == 0)
10086 omit_lock_prefix
= 1;
10087 else if (strcasecmp (arg
, "no") == 0)
10088 omit_lock_prefix
= 0;
10090 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10093 case OPTION_MFENCE_AS_LOCK_ADD
:
10094 if (strcasecmp (arg
, "yes") == 0)
10096 else if (strcasecmp (arg
, "no") == 0)
10099 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10102 case OPTION_MRELAX_RELOCATIONS
:
10103 if (strcasecmp (arg
, "yes") == 0)
10104 generate_relax_relocations
= 1;
10105 else if (strcasecmp (arg
, "no") == 0)
10106 generate_relax_relocations
= 0;
10108 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10111 case OPTION_MAMD64
:
10112 cpu_arch_flags
.bitfield
.cpuamd64
= 1;
10113 cpu_arch_flags
.bitfield
.cpuintel64
= 0;
10114 cpu_arch_isa_flags
.bitfield
.cpuamd64
= 1;
10115 cpu_arch_isa_flags
.bitfield
.cpuintel64
= 0;
10118 case OPTION_MINTEL64
:
10119 cpu_arch_flags
.bitfield
.cpuamd64
= 0;
10120 cpu_arch_flags
.bitfield
.cpuintel64
= 1;
10121 cpu_arch_isa_flags
.bitfield
.cpuamd64
= 0;
10122 cpu_arch_isa_flags
.bitfield
.cpuintel64
= 1;
10131 #define MESSAGE_TEMPLATE \
10135 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10136 int *left_p
, const char *name
, int len
)
10138 int size
= sizeof (MESSAGE_TEMPLATE
);
10139 int left
= *left_p
;
10141 /* Reserve 2 spaces for ", " or ",\0" */
10144 /* Check if there is any room. */
10152 p
= mempcpy (p
, name
, len
);
10156 /* Output the current message now and start a new one. */
10159 fprintf (stream
, "%s\n", message
);
10161 left
= size
- (start
- message
) - len
- 2;
10163 gas_assert (left
>= 0);
10165 p
= mempcpy (p
, name
, len
);
10173 show_arch (FILE *stream
, int ext
, int check
)
10175 static char message
[] = MESSAGE_TEMPLATE
;
10176 char *start
= message
+ 27;
10178 int size
= sizeof (MESSAGE_TEMPLATE
);
10185 left
= size
- (start
- message
);
10186 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10188 /* Should it be skipped? */
10189 if (cpu_arch
[j
].skip
)
10192 name
= cpu_arch
[j
].name
;
10193 len
= cpu_arch
[j
].len
;
10196 /* It is an extension. Skip if we aren't asked to show it. */
10207 /* It is an processor. Skip if we show only extension. */
10210 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10212 /* It is an impossible processor - skip. */
10216 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10219 /* Display disabled extensions. */
10221 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10223 name
= cpu_noarch
[j
].name
;
10224 len
= cpu_noarch
[j
].len
;
10225 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10230 fprintf (stream
, "%s\n", message
);
10234 md_show_usage (FILE *stream
)
10236 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10237 fprintf (stream
, _("\
10239 -V print assembler version number\n\
10242 fprintf (stream
, _("\
10243 -n Do not optimize code alignment\n\
10244 -q quieten some warnings\n"));
10245 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10246 fprintf (stream
, _("\
10249 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10250 || defined (TE_PE) || defined (TE_PEP))
10251 fprintf (stream
, _("\
10252 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10254 #ifdef SVR4_COMMENT_CHARS
10255 fprintf (stream
, _("\
10256 --divide do not treat `/' as a comment character\n"));
10258 fprintf (stream
, _("\
10259 --divide ignored\n"));
10261 fprintf (stream
, _("\
10262 -march=CPU[,+EXTENSION...]\n\
10263 generate code for CPU and EXTENSION, CPU is one of:\n"));
10264 show_arch (stream
, 0, 1);
10265 fprintf (stream
, _("\
10266 EXTENSION is combination of:\n"));
10267 show_arch (stream
, 1, 0);
10268 fprintf (stream
, _("\
10269 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10270 show_arch (stream
, 0, 0);
10271 fprintf (stream
, _("\
10272 -msse2avx encode SSE instructions with VEX prefix\n"));
10273 fprintf (stream
, _("\
10274 -msse-check=[none|error|warning]\n\
10275 check SSE instructions\n"));
10276 fprintf (stream
, _("\
10277 -moperand-check=[none|error|warning]\n\
10278 check operand combinations for validity\n"));
10279 fprintf (stream
, _("\
10280 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10282 fprintf (stream
, _("\
10283 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10285 fprintf (stream
, _("\
10286 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10287 for EVEX.W bit ignored instructions\n"));
10288 fprintf (stream
, _("\
10289 -mevexrcig=[rne|rd|ru|rz]\n\
10290 encode EVEX instructions with specific EVEX.RC value\n\
10291 for SAE-only ignored instructions\n"));
10292 fprintf (stream
, _("\
10293 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10294 fprintf (stream
, _("\
10295 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10296 fprintf (stream
, _("\
10297 -mindex-reg support pseudo index registers\n"));
10298 fprintf (stream
, _("\
10299 -mnaked-reg don't require `%%' prefix for registers\n"));
10300 fprintf (stream
, _("\
10301 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10302 fprintf (stream
, _("\
10303 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10304 fprintf (stream
, _("\
10305 -mshared disable branch optimization for shared code\n"));
10306 # if defined (TE_PE) || defined (TE_PEP)
10307 fprintf (stream
, _("\
10308 -mbig-obj generate big object files\n"));
10310 fprintf (stream
, _("\
10311 -momit-lock-prefix=[no|yes]\n\
10312 strip all lock prefixes\n"));
10313 fprintf (stream
, _("\
10314 -mfence-as-lock-add=[no|yes]\n\
10315 encode lfence, mfence and sfence as\n\
10316 lock addl $0x0, (%%{re}sp)\n"));
10317 fprintf (stream
, _("\
10318 -mrelax-relocations=[no|yes]\n\
10319 generate relax relocations\n"));
10320 fprintf (stream
, _("\
10321 -mamd64 accept only AMD64 ISA\n"));
10322 fprintf (stream
, _("\
10323 -mintel64 accept only Intel64 ISA\n"));
10326 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10327 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10328 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10330 /* Pick the target format to use. */
10333 i386_target_format (void)
10335 if (!strncmp (default_arch
, "x86_64", 6))
10337 update_code_flag (CODE_64BIT
, 1);
10338 if (default_arch
[6] == '\0')
10339 x86_elf_abi
= X86_64_ABI
;
10341 x86_elf_abi
= X86_64_X32_ABI
;
10343 else if (!strcmp (default_arch
, "i386"))
10344 update_code_flag (CODE_32BIT
, 1);
10345 else if (!strcmp (default_arch
, "iamcu"))
10347 update_code_flag (CODE_32BIT
, 1);
10348 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10350 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10351 cpu_arch_name
= "iamcu";
10352 cpu_sub_arch_name
= NULL
;
10353 cpu_arch_flags
= iamcu_flags
;
10354 cpu_arch_isa
= PROCESSOR_IAMCU
;
10355 cpu_arch_isa_flags
= iamcu_flags
;
10356 if (!cpu_arch_tune_set
)
10358 cpu_arch_tune
= cpu_arch_isa
;
10359 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10363 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10367 as_fatal (_("unknown architecture"));
10369 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10370 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10371 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10372 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10374 switch (OUTPUT_FLAVOR
)
10376 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10377 case bfd_target_aout_flavour
:
10378 return AOUT_TARGET_FORMAT
;
10380 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10381 # if defined (TE_PE) || defined (TE_PEP)
10382 case bfd_target_coff_flavour
:
10383 if (flag_code
== CODE_64BIT
)
10384 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10387 # elif defined (TE_GO32)
10388 case bfd_target_coff_flavour
:
10389 return "coff-go32";
10391 case bfd_target_coff_flavour
:
10392 return "coff-i386";
10395 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10396 case bfd_target_elf_flavour
:
10398 const char *format
;
10400 switch (x86_elf_abi
)
10403 format
= ELF_TARGET_FORMAT
;
10406 use_rela_relocations
= 1;
10408 format
= ELF_TARGET_FORMAT64
;
10410 case X86_64_X32_ABI
:
10411 use_rela_relocations
= 1;
10413 disallow_64bit_reloc
= 1;
10414 format
= ELF_TARGET_FORMAT32
;
10417 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10419 if (x86_elf_abi
!= X86_64_ABI
)
10420 as_fatal (_("Intel L1OM is 64bit only"));
10421 return ELF_TARGET_L1OM_FORMAT
;
10423 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10425 if (x86_elf_abi
!= X86_64_ABI
)
10426 as_fatal (_("Intel K1OM is 64bit only"));
10427 return ELF_TARGET_K1OM_FORMAT
;
10429 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10431 if (x86_elf_abi
!= I386_ABI
)
10432 as_fatal (_("Intel MCU is 32bit only"));
10433 return ELF_TARGET_IAMCU_FORMAT
;
10439 #if defined (OBJ_MACH_O)
10440 case bfd_target_mach_o_flavour
:
10441 if (flag_code
== CODE_64BIT
)
10443 use_rela_relocations
= 1;
10445 return "mach-o-x86-64";
10448 return "mach-o-i386";
10456 #endif /* OBJ_MAYBE_ more than one */
10459 md_undefined_symbol (char *name
)
10461 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10462 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10463 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10464 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10468 if (symbol_find (name
))
10469 as_bad (_("GOT already in symbol table"));
10470 GOT_symbol
= symbol_new (name
, undefined_section
,
10471 (valueT
) 0, &zero_address_frag
);
10478 /* Round up a section size to the appropriate boundary. */
10481 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10483 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10484 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10486 /* For a.out, force the section size to be aligned. If we don't do
10487 this, BFD will align it for us, but it will not write out the
10488 final bytes of the section. This may be a bug in BFD, but it is
10489 easier to fix it here since that is how the other a.out targets
10493 align
= bfd_get_section_alignment (stdoutput
, segment
);
10494 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
10501 /* On the i386, PC-relative offsets are relative to the start of the
10502 next instruction. That is, the address of the offset, plus its
10503 size, since the offset is always the last part of the insn. */
10506 md_pcrel_from (fixS
*fixP
)
10508 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10514 s_bss (int ignore ATTRIBUTE_UNUSED
)
10518 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10520 obj_elf_section_change_hook ();
10522 temp
= get_absolute_expression ();
10523 subseg_set (bss_section
, (subsegT
) temp
);
10524 demand_empty_rest_of_line ();
10530 i386_validate_fix (fixS
*fixp
)
10532 if (fixp
->fx_subsy
)
10534 if (fixp
->fx_subsy
== GOT_symbol
)
10536 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10540 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10541 if (fixp
->fx_tcbit2
)
10542 fixp
->fx_r_type
= (fixp
->fx_tcbit
10543 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10544 : BFD_RELOC_X86_64_GOTPCRELX
);
10547 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10552 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10554 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10556 fixp
->fx_subsy
= 0;
10559 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10560 else if (!object_64bit
)
10562 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
10563 && fixp
->fx_tcbit2
)
10564 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
10570 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10573 bfd_reloc_code_real_type code
;
10575 switch (fixp
->fx_r_type
)
10577 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10578 case BFD_RELOC_SIZE32
:
10579 case BFD_RELOC_SIZE64
:
10580 if (S_IS_DEFINED (fixp
->fx_addsy
)
10581 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10583 /* Resolve size relocation against local symbol to size of
10584 the symbol plus addend. */
10585 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10586 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10587 && !fits_in_unsigned_long (value
))
10588 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10589 _("symbol size computation overflow"));
10590 fixp
->fx_addsy
= NULL
;
10591 fixp
->fx_subsy
= NULL
;
10592 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10597 case BFD_RELOC_X86_64_PLT32
:
10598 case BFD_RELOC_X86_64_GOT32
:
10599 case BFD_RELOC_X86_64_GOTPCREL
:
10600 case BFD_RELOC_X86_64_GOTPCRELX
:
10601 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10602 case BFD_RELOC_386_PLT32
:
10603 case BFD_RELOC_386_GOT32
:
10604 case BFD_RELOC_386_GOT32X
:
10605 case BFD_RELOC_386_GOTOFF
:
10606 case BFD_RELOC_386_GOTPC
:
10607 case BFD_RELOC_386_TLS_GD
:
10608 case BFD_RELOC_386_TLS_LDM
:
10609 case BFD_RELOC_386_TLS_LDO_32
:
10610 case BFD_RELOC_386_TLS_IE_32
:
10611 case BFD_RELOC_386_TLS_IE
:
10612 case BFD_RELOC_386_TLS_GOTIE
:
10613 case BFD_RELOC_386_TLS_LE_32
:
10614 case BFD_RELOC_386_TLS_LE
:
10615 case BFD_RELOC_386_TLS_GOTDESC
:
10616 case BFD_RELOC_386_TLS_DESC_CALL
:
10617 case BFD_RELOC_X86_64_TLSGD
:
10618 case BFD_RELOC_X86_64_TLSLD
:
10619 case BFD_RELOC_X86_64_DTPOFF32
:
10620 case BFD_RELOC_X86_64_DTPOFF64
:
10621 case BFD_RELOC_X86_64_GOTTPOFF
:
10622 case BFD_RELOC_X86_64_TPOFF32
:
10623 case BFD_RELOC_X86_64_TPOFF64
:
10624 case BFD_RELOC_X86_64_GOTOFF64
:
10625 case BFD_RELOC_X86_64_GOTPC32
:
10626 case BFD_RELOC_X86_64_GOT64
:
10627 case BFD_RELOC_X86_64_GOTPCREL64
:
10628 case BFD_RELOC_X86_64_GOTPC64
:
10629 case BFD_RELOC_X86_64_GOTPLT64
:
10630 case BFD_RELOC_X86_64_PLTOFF64
:
10631 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10632 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10633 case BFD_RELOC_RVA
:
10634 case BFD_RELOC_VTABLE_ENTRY
:
10635 case BFD_RELOC_VTABLE_INHERIT
:
10637 case BFD_RELOC_32_SECREL
:
10639 code
= fixp
->fx_r_type
;
10641 case BFD_RELOC_X86_64_32S
:
10642 if (!fixp
->fx_pcrel
)
10644 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10645 code
= fixp
->fx_r_type
;
10649 if (fixp
->fx_pcrel
)
10651 switch (fixp
->fx_size
)
10654 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10655 _("can not do %d byte pc-relative relocation"),
10657 code
= BFD_RELOC_32_PCREL
;
10659 case 1: code
= BFD_RELOC_8_PCREL
; break;
10660 case 2: code
= BFD_RELOC_16_PCREL
; break;
10661 case 4: code
= BFD_RELOC_32_PCREL
; break;
10663 case 8: code
= BFD_RELOC_64_PCREL
; break;
10669 switch (fixp
->fx_size
)
10672 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10673 _("can not do %d byte relocation"),
10675 code
= BFD_RELOC_32
;
10677 case 1: code
= BFD_RELOC_8
; break;
10678 case 2: code
= BFD_RELOC_16
; break;
10679 case 4: code
= BFD_RELOC_32
; break;
10681 case 8: code
= BFD_RELOC_64
; break;
10688 if ((code
== BFD_RELOC_32
10689 || code
== BFD_RELOC_32_PCREL
10690 || code
== BFD_RELOC_X86_64_32S
)
10692 && fixp
->fx_addsy
== GOT_symbol
)
10695 code
= BFD_RELOC_386_GOTPC
;
10697 code
= BFD_RELOC_X86_64_GOTPC32
;
10699 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10701 && fixp
->fx_addsy
== GOT_symbol
)
10703 code
= BFD_RELOC_X86_64_GOTPC64
;
10706 rel
= XNEW (arelent
);
10707 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
10708 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10710 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10712 if (!use_rela_relocations
)
10714 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10715 vtable entry to be used in the relocation's section offset. */
10716 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10717 rel
->address
= fixp
->fx_offset
;
10718 #if defined (OBJ_COFF) && defined (TE_PE)
10719 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10720 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10725 /* Use the rela in 64bit mode. */
10728 if (disallow_64bit_reloc
)
10731 case BFD_RELOC_X86_64_DTPOFF64
:
10732 case BFD_RELOC_X86_64_TPOFF64
:
10733 case BFD_RELOC_64_PCREL
:
10734 case BFD_RELOC_X86_64_GOTOFF64
:
10735 case BFD_RELOC_X86_64_GOT64
:
10736 case BFD_RELOC_X86_64_GOTPCREL64
:
10737 case BFD_RELOC_X86_64_GOTPC64
:
10738 case BFD_RELOC_X86_64_GOTPLT64
:
10739 case BFD_RELOC_X86_64_PLTOFF64
:
10740 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10741 _("cannot represent relocation type %s in x32 mode"),
10742 bfd_get_reloc_code_name (code
));
10748 if (!fixp
->fx_pcrel
)
10749 rel
->addend
= fixp
->fx_offset
;
10753 case BFD_RELOC_X86_64_PLT32
:
10754 case BFD_RELOC_X86_64_GOT32
:
10755 case BFD_RELOC_X86_64_GOTPCREL
:
10756 case BFD_RELOC_X86_64_GOTPCRELX
:
10757 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10758 case BFD_RELOC_X86_64_TLSGD
:
10759 case BFD_RELOC_X86_64_TLSLD
:
10760 case BFD_RELOC_X86_64_GOTTPOFF
:
10761 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10762 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10763 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10766 rel
->addend
= (section
->vma
10768 + fixp
->fx_addnumber
10769 + md_pcrel_from (fixp
));
10774 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10775 if (rel
->howto
== NULL
)
10777 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10778 _("cannot represent relocation type %s"),
10779 bfd_get_reloc_code_name (code
));
10780 /* Set howto to a garbage value so that we can keep going. */
10781 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10782 gas_assert (rel
->howto
!= NULL
);
10788 #include "tc-i386-intel.c"
10791 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10793 int saved_naked_reg
;
10794 char saved_register_dot
;
10796 saved_naked_reg
= allow_naked_reg
;
10797 allow_naked_reg
= 1;
10798 saved_register_dot
= register_chars
['.'];
10799 register_chars
['.'] = '.';
10800 allow_pseudo_reg
= 1;
10801 expression_and_evaluate (exp
);
10802 allow_pseudo_reg
= 0;
10803 register_chars
['.'] = saved_register_dot
;
10804 allow_naked_reg
= saved_naked_reg
;
10806 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10808 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10810 exp
->X_op
= O_constant
;
10811 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10812 .dw2_regnum
[flag_code
>> 1];
10815 exp
->X_op
= O_illegal
;
10820 tc_x86_frame_initial_instructions (void)
10822 static unsigned int sp_regno
[2];
10824 if (!sp_regno
[flag_code
>> 1])
10826 char *saved_input
= input_line_pointer
;
10827 char sp
[][4] = {"esp", "rsp"};
10830 input_line_pointer
= sp
[flag_code
>> 1];
10831 tc_x86_parse_to_dw2regnum (&exp
);
10832 gas_assert (exp
.X_op
== O_constant
);
10833 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10834 input_line_pointer
= saved_input
;
10837 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10838 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10842 x86_dwarf2_addr_size (void)
10844 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10845 if (x86_elf_abi
== X86_64_X32_ABI
)
10848 return bfd_arch_bits_per_address (stdoutput
) / 8;
10852 i386_elf_section_type (const char *str
, size_t len
)
10854 if (flag_code
== CODE_64BIT
10855 && len
== sizeof ("unwind") - 1
10856 && strncmp (str
, "unwind", 6) == 0)
10857 return SHT_X86_64_UNWIND
;
10864 i386_solaris_fix_up_eh_frame (segT sec
)
10866 if (flag_code
== CODE_64BIT
)
10867 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10873 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10877 exp
.X_op
= O_secrel
;
10878 exp
.X_add_symbol
= symbol
;
10879 exp
.X_add_number
= 0;
10880 emit_expr (&exp
, size
);
10884 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10885 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10888 x86_64_section_letter (int letter
, const char **ptr_msg
)
10890 if (flag_code
== CODE_64BIT
)
10893 return SHF_X86_64_LARGE
;
10895 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10898 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10903 x86_64_section_word (char *str
, size_t len
)
10905 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10906 return SHF_X86_64_LARGE
;
10912 handle_large_common (int small ATTRIBUTE_UNUSED
)
10914 if (flag_code
!= CODE_64BIT
)
10916 s_comm_internal (0, elf_common_parse
);
10917 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10921 static segT lbss_section
;
10922 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10923 asection
*saved_bss_section
= bss_section
;
10925 if (lbss_section
== NULL
)
10927 flagword applicable
;
10928 segT seg
= now_seg
;
10929 subsegT subseg
= now_subseg
;
10931 /* The .lbss section is for local .largecomm symbols. */
10932 lbss_section
= subseg_new (".lbss", 0);
10933 applicable
= bfd_applicable_section_flags (stdoutput
);
10934 bfd_set_section_flags (stdoutput
, lbss_section
,
10935 applicable
& SEC_ALLOC
);
10936 seg_info (lbss_section
)->bss
= 1;
10938 subseg_set (seg
, subseg
);
10941 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10942 bss_section
= lbss_section
;
10944 s_comm_internal (0, elf_common_parse
);
10946 elf_com_section_ptr
= saved_com_section_ptr
;
10947 bss_section
= saved_bss_section
;
10950 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */