1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
139 /* Used to turn off indicated flags. */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 i386_cpu_flags flags
; /* cpu feature flags */
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
157 static void pe_directive_secrel (int);
159 static void signed_cons (int);
160 static char *output_invalid (int c
);
161 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
163 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS
*);
168 static int i386_intel_parse_name (const char *, expressionS
*);
169 static const reg_entry
*parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template
*match_template (void);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry
*build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS
*, offsetT
);
188 static void output_disp (fragS
*, offsetT
);
190 static void s_bss (int);
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
196 static const char *default_arch
= DEFAULT_ARCH
;
198 /* This struct describes rounding control and SAE in the instruction. */
212 static struct RC_Operation rc_op
;
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
219 const reg_entry
*mask
;
220 unsigned int zeroing
;
221 /* The operand where this operation is associated. */
225 static struct Mask_Operation mask_op
;
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
229 struct Broadcast_Operation
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
234 /* Index of broadcasted operand. */
238 static struct Broadcast_Operation broadcast_op
;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes
[4];
246 /* Destination or source register specifier. */
247 const reg_entry
*register_specifier
;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry
*regs
;
262 operand_size_mismatch
,
263 operand_type_mismatch
,
264 register_type_mismatch
,
265 number_of_operands_mismatch
,
266 invalid_instruction_suffix
,
269 unsupported_with_intel_mnemonic
,
272 invalid_vsib_address
,
273 invalid_vector_register_set
,
274 unsupported_vector_index_register
,
275 unsupported_broadcast
,
276 broadcast_not_on_src_operand
,
279 mask_not_on_destination
,
282 rc_sae_operand_not_last_imm
,
283 invalid_register_operand
,
289 /* TM holds the template for the insn were currently assembling. */
292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
296 /* OPERANDS gives the number of given operands. */
297 unsigned int operands
;
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
302 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
304 /* TYPES [i] is the type (see above #defines) which tells us how to
305 use OP[i] for the corresponding operand. */
306 i386_operand_type types
[MAX_OPERANDS
];
308 /* Displacement expression, immediate expression, or register for each
310 union i386_op op
[MAX_OPERANDS
];
312 /* Flags for operands. */
313 unsigned int flags
[MAX_OPERANDS
];
314 #define Operand_PCrel 1
316 /* Relocation type for operand */
317 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry
*base_reg
;
322 const reg_entry
*index_reg
;
323 unsigned int log2_scale_factor
;
325 /* SEG gives the seg_entries of this insn. They are zero unless
326 explicit segment overrides are given. */
327 const seg_entry
*seg
[2];
329 /* PREFIX holds all the given prefix opcodes (usually null).
330 PREFIXES is the number of prefix opcodes. */
331 unsigned int prefixes
;
332 unsigned char prefix
[MAX_PREFIXES
];
334 /* RM and SIB are the modrm byte and the sib byte where the
335 addressing modes of this insn are encoded. */
342 /* Masking attributes. */
343 struct Mask_Operation
*mask
;
345 /* Rounding control and SAE attributes. */
346 struct RC_Operation
*rounding
;
348 /* Broadcasting attributes. */
349 struct Broadcast_Operation
*broadcast
;
351 /* Compressed disp8*N attribute. */
352 unsigned int memshift
;
354 /* Swap operand in encoding. */
355 unsigned int swap_operand
;
357 /* Prefer 8bit or 32bit displacement in encoding. */
360 disp_encoding_default
= 0,
366 const char *rep_prefix
;
369 const char *hle_prefix
;
371 /* Have BND prefix. */
372 const char *bnd_prefix
;
374 /* Need VREX to support upper 16 registers. */
378 enum i386_error error
;
381 typedef struct _i386_insn i386_insn
;
383 /* Link RC type with corresponding string, that'll be looked for in
392 static const struct RC_name RC_NamesTable
[] =
394 { rne
, STRING_COMMA_LEN ("rn-sae") },
395 { rd
, STRING_COMMA_LEN ("rd-sae") },
396 { ru
, STRING_COMMA_LEN ("ru-sae") },
397 { rz
, STRING_COMMA_LEN ("rz-sae") },
398 { saeonly
, STRING_COMMA_LEN ("sae") },
401 /* List of chars besides those in app.c:symbol_chars that can start an
402 operand. Used to prevent the scrubber eating vital white-space. */
403 const char extra_symbol_chars
[] = "*%-([{"
412 #if (defined (TE_I386AIX) \
413 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
414 && !defined (TE_GNU) \
415 && !defined (TE_LINUX) \
416 && !defined (TE_NACL) \
417 && !defined (TE_NETWARE) \
418 && !defined (TE_FreeBSD) \
419 && !defined (TE_DragonFly) \
420 && !defined (TE_NetBSD)))
421 /* This array holds the chars that always start a comment. If the
422 pre-processor is disabled, these aren't very useful. The option
423 --divide will remove '/' from this list. */
424 const char *i386_comment_chars
= "#/";
425 #define SVR4_COMMENT_CHARS 1
426 #define PREFIX_SEPARATOR '\\'
429 const char *i386_comment_chars
= "#";
430 #define PREFIX_SEPARATOR '/'
433 /* This array holds the chars that only start a comment at the beginning of
434 a line. If the line seems to have the form '# 123 filename'
435 .line and .file directives will appear in the pre-processed output.
436 Note that input_file.c hand checks for '#' at the beginning of the
437 first line of the input file. This is because the compiler outputs
438 #NO_APP at the beginning of its output.
439 Also note that comments started like this one will always work if
440 '/' isn't otherwise defined. */
441 const char line_comment_chars
[] = "#/";
443 const char line_separator_chars
[] = ";";
445 /* Chars that can be used to separate mant from exp in floating point
447 const char EXP_CHARS
[] = "eE";
449 /* Chars that mean this number is a floating point constant
452 const char FLT_CHARS
[] = "fFdDxX";
454 /* Tables for lexical analysis. */
455 static char mnemonic_chars
[256];
456 static char register_chars
[256];
457 static char operand_chars
[256];
458 static char identifier_chars
[256];
459 static char digit_chars
[256];
461 /* Lexical macros. */
462 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
463 #define is_operand_char(x) (operand_chars[(unsigned char) x])
464 #define is_register_char(x) (register_chars[(unsigned char) x])
465 #define is_space_char(x) ((x) == ' ')
466 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
467 #define is_digit_char(x) (digit_chars[(unsigned char) x])
469 /* All non-digit non-letter characters that may occur in an operand. */
470 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
472 /* md_assemble() always leaves the strings it's passed unaltered. To
473 effect this we maintain a stack of saved characters that we've smashed
474 with '\0's (indicating end of strings for various sub-fields of the
475 assembler instruction). */
476 static char save_stack
[32];
477 static char *save_stack_p
;
478 #define END_STRING_AND_SAVE(s) \
479 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
480 #define RESTORE_END_STRING(s) \
481 do { *(s) = *--save_stack_p; } while (0)
483 /* The instruction we're assembling. */
486 /* Possible templates for current insn. */
487 static const templates
*current_templates
;
489 /* Per instruction expressionS buffers: max displacements & immediates. */
490 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
491 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
493 /* Current operand we are working on. */
494 static int this_operand
= -1;
496 /* We support four different modes. FLAG_CODE variable is used to distinguish
504 static enum flag_code flag_code
;
505 static unsigned int object_64bit
;
506 static unsigned int disallow_64bit_reloc
;
507 static int use_rela_relocations
= 0;
509 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
510 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
511 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
513 /* The ELF ABI to use. */
521 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
524 #if defined (TE_PE) || defined (TE_PEP)
525 /* Use big object file format. */
526 static int use_big_obj
= 0;
529 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
530 /* 1 if generating code for a shared library. */
531 static int shared
= 0;
534 /* 1 for intel syntax,
536 static int intel_syntax
= 0;
538 /* 1 for Intel64 ISA,
542 /* 1 for intel mnemonic,
543 0 if att mnemonic. */
544 static int intel_mnemonic
= !SYSV386_COMPAT
;
546 /* 1 if support old (<= 2.8.1) versions of gcc. */
547 static int old_gcc
= OLDGCC_COMPAT
;
549 /* 1 if pseudo registers are permitted. */
550 static int allow_pseudo_reg
= 0;
552 /* 1 if register prefix % not required. */
553 static int allow_naked_reg
= 0;
555 /* 1 if the assembler should add BND prefix for all control-tranferring
556 instructions supporting it, even if this prefix wasn't specified
558 static int add_bnd_prefix
= 0;
560 /* 1 if pseudo index register, eiz/riz, is allowed . */
561 static int allow_index_reg
= 0;
563 /* 1 if the assembler should ignore LOCK prefix, even if it was
564 specified explicitly. */
565 static int omit_lock_prefix
= 0;
567 /* 1 if the assembler should encode lfence, mfence, and sfence as
568 "lock addl $0, (%{re}sp)". */
569 static int avoid_fence
= 0;
571 /* 1 if the assembler should generate relax relocations. */
573 static int generate_relax_relocations
574 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
576 static enum check_kind
582 sse_check
, operand_check
= check_warning
;
584 /* Register prefix used for error message. */
585 static const char *register_prefix
= "%";
587 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
588 leave, push, and pop instructions so that gcc has the same stack
589 frame as in 32 bit mode. */
590 static char stackop_size
= '\0';
592 /* Non-zero to optimize code alignment. */
593 int optimize_align_code
= 1;
595 /* Non-zero to quieten some warnings. */
596 static int quiet_warnings
= 0;
599 static const char *cpu_arch_name
= NULL
;
600 static char *cpu_sub_arch_name
= NULL
;
602 /* CPU feature flags. */
603 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
605 /* If we have selected a cpu we are generating instructions for. */
606 static int cpu_arch_tune_set
= 0;
608 /* Cpu we are generating instructions for. */
609 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
611 /* CPU feature flags of cpu we are generating instructions for. */
612 static i386_cpu_flags cpu_arch_tune_flags
;
614 /* CPU instruction set architecture used. */
615 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
617 /* CPU feature flags of instruction set architecture used. */
618 i386_cpu_flags cpu_arch_isa_flags
;
620 /* If set, conditional jumps are not automatically promoted to handle
621 larger than a byte offset. */
622 static unsigned int no_cond_jump_promotion
= 0;
624 /* Encode SSE instructions with VEX prefix. */
625 static unsigned int sse2avx
;
627 /* Encode scalar AVX instructions with specific vector length. */
634 /* Encode scalar EVEX LIG instructions with specific vector length. */
642 /* Encode EVEX WIG instructions with specific evex.w. */
649 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
650 static enum rc_type evexrcig
= rne
;
652 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
653 static symbolS
*GOT_symbol
;
655 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
656 unsigned int x86_dwarf2_return_column
;
658 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
659 int x86_cie_data_alignment
;
661 /* Interface to relax_segment.
662 There are 3 major relax states for 386 jump insns because the
663 different types of jumps add different sizes to frags when we're
664 figuring out what sort of jump to choose to reach a given label. */
667 #define UNCOND_JUMP 0
669 #define COND_JUMP86 2
674 #define SMALL16 (SMALL | CODE16)
676 #define BIG16 (BIG | CODE16)
680 #define INLINE __inline__
686 #define ENCODE_RELAX_STATE(type, size) \
687 ((relax_substateT) (((type) << 2) | (size)))
688 #define TYPE_FROM_RELAX_STATE(s) \
690 #define DISP_SIZE_FROM_RELAX_STATE(s) \
691 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
693 /* This table is used by relax_frag to promote short jumps to long
694 ones where necessary. SMALL (short) jumps may be promoted to BIG
695 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
696 don't allow a short jump in a 32 bit code segment to be promoted to
697 a 16 bit offset jump because it's slower (requires data size
698 prefix), and doesn't work, unless the destination is in the bottom
699 64k of the code segment (The top 16 bits of eip are zeroed). */
701 const relax_typeS md_relax_table
[] =
704 1) most positive reach of this state,
705 2) most negative reach of this state,
706 3) how many bytes this mode will have in the variable part of the frag
707 4) which index into the table to try if we can't fit into this one. */
709 /* UNCOND_JUMP states. */
710 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
711 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
712 /* dword jmp adds 4 bytes to frag:
713 0 extra opcode bytes, 4 displacement bytes. */
715 /* word jmp adds 2 byte2 to frag:
716 0 extra opcode bytes, 2 displacement bytes. */
719 /* COND_JUMP states. */
720 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
721 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
722 /* dword conditionals adds 5 bytes to frag:
723 1 extra opcode byte, 4 displacement bytes. */
725 /* word conditionals add 3 bytes to frag:
726 1 extra opcode byte, 2 displacement bytes. */
729 /* COND_JUMP86 states. */
730 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
731 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
732 /* dword conditionals adds 5 bytes to frag:
733 1 extra opcode byte, 4 displacement bytes. */
735 /* word conditionals add 4 bytes to frag:
736 1 displacement byte and a 3 byte long branch insn. */
740 static const arch_entry cpu_arch
[] =
742 /* Do not replace the first two entries - i386_target_format()
743 relies on them being there in this order. */
744 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
745 CPU_GENERIC32_FLAGS
, 0 },
746 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
747 CPU_GENERIC64_FLAGS
, 0 },
748 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
750 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
752 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
754 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
756 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
758 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
760 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
762 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
764 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
765 CPU_PENTIUMPRO_FLAGS
, 0 },
766 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
768 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
770 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
772 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
774 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
775 CPU_NOCONA_FLAGS
, 0 },
776 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
778 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
780 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
781 CPU_CORE2_FLAGS
, 1 },
782 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
783 CPU_CORE2_FLAGS
, 0 },
784 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
785 CPU_COREI7_FLAGS
, 0 },
786 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
788 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
790 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
791 CPU_IAMCU_FLAGS
, 0 },
792 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
794 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
796 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
797 CPU_ATHLON_FLAGS
, 0 },
798 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
800 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
802 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
804 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
805 CPU_AMDFAM10_FLAGS
, 0 },
806 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
807 CPU_BDVER1_FLAGS
, 0 },
808 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
809 CPU_BDVER2_FLAGS
, 0 },
810 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
811 CPU_BDVER3_FLAGS
, 0 },
812 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
813 CPU_BDVER4_FLAGS
, 0 },
814 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
815 CPU_ZNVER1_FLAGS
, 0 },
816 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
817 CPU_BTVER1_FLAGS
, 0 },
818 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
819 CPU_BTVER2_FLAGS
, 0 },
820 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
822 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
824 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
826 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
828 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
830 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
832 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
834 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
836 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
837 CPU_SSSE3_FLAGS
, 0 },
838 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
839 CPU_SSE4_1_FLAGS
, 0 },
840 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
841 CPU_SSE4_2_FLAGS
, 0 },
842 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
843 CPU_SSE4_2_FLAGS
, 0 },
844 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
846 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
848 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
849 CPU_AVX512F_FLAGS
, 0 },
850 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
851 CPU_AVX512CD_FLAGS
, 0 },
852 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
853 CPU_AVX512ER_FLAGS
, 0 },
854 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
855 CPU_AVX512PF_FLAGS
, 0 },
856 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
857 CPU_AVX512DQ_FLAGS
, 0 },
858 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
859 CPU_AVX512BW_FLAGS
, 0 },
860 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
861 CPU_AVX512VL_FLAGS
, 0 },
862 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
864 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
865 CPU_VMFUNC_FLAGS
, 0 },
866 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
868 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
869 CPU_XSAVE_FLAGS
, 0 },
870 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
871 CPU_XSAVEOPT_FLAGS
, 0 },
872 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
873 CPU_XSAVEC_FLAGS
, 0 },
874 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
875 CPU_XSAVES_FLAGS
, 0 },
876 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
878 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
879 CPU_PCLMUL_FLAGS
, 0 },
880 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
881 CPU_PCLMUL_FLAGS
, 1 },
882 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
883 CPU_FSGSBASE_FLAGS
, 0 },
884 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
885 CPU_RDRND_FLAGS
, 0 },
886 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
888 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
890 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
892 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
894 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
896 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
898 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
899 CPU_MOVBE_FLAGS
, 0 },
900 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
902 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
904 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
905 CPU_LZCNT_FLAGS
, 0 },
906 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
908 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
910 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
911 CPU_INVPCID_FLAGS
, 0 },
912 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
913 CPU_CLFLUSH_FLAGS
, 0 },
914 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
916 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
917 CPU_SYSCALL_FLAGS
, 0 },
918 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
919 CPU_RDTSCP_FLAGS
, 0 },
920 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
921 CPU_3DNOW_FLAGS
, 0 },
922 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
923 CPU_3DNOWA_FLAGS
, 0 },
924 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
925 CPU_PADLOCK_FLAGS
, 0 },
926 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
928 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
930 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
931 CPU_SSE4A_FLAGS
, 0 },
932 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
934 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
936 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
938 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
940 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
941 CPU_RDSEED_FLAGS
, 0 },
942 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
943 CPU_PRFCHW_FLAGS
, 0 },
944 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
946 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
948 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
950 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
951 CPU_CLFLUSHOPT_FLAGS
, 0 },
952 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
953 CPU_PREFETCHWT1_FLAGS
, 0 },
954 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
956 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
958 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
959 CPU_PCOMMIT_FLAGS
, 0 },
960 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
961 CPU_AVX512IFMA_FLAGS
, 0 },
962 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
963 CPU_AVX512VBMI_FLAGS
, 0 },
964 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
965 CPU_CLZERO_FLAGS
, 0 },
966 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
967 CPU_MWAITX_FLAGS
, 0 },
968 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
969 CPU_OSPKE_FLAGS
, 0 },
970 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
971 CPU_RDPID_FLAGS
, 0 },
974 static const noarch_entry cpu_noarch
[] =
976 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
977 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
978 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
979 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
980 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
981 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
982 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
983 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
984 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
985 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
986 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
987 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
988 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
989 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
993 /* Like s_lcomm_internal in gas/read.c but the alignment string
994 is allowed to be optional. */
997 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1004 && *input_line_pointer
== ',')
1006 align
= parse_align (needs_align
- 1);
1008 if (align
== (addressT
) -1)
1023 bss_alloc (symbolP
, size
, align
);
1028 pe_lcomm (int needs_align
)
1030 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1034 const pseudo_typeS md_pseudo_table
[] =
1036 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1037 {"align", s_align_bytes
, 0},
1039 {"align", s_align_ptwo
, 0},
1041 {"arch", set_cpu_arch
, 0},
1045 {"lcomm", pe_lcomm
, 1},
1047 {"ffloat", float_cons
, 'f'},
1048 {"dfloat", float_cons
, 'd'},
1049 {"tfloat", float_cons
, 'x'},
1051 {"slong", signed_cons
, 4},
1052 {"noopt", s_ignore
, 0},
1053 {"optim", s_ignore
, 0},
1054 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1055 {"code16", set_code_flag
, CODE_16BIT
},
1056 {"code32", set_code_flag
, CODE_32BIT
},
1057 {"code64", set_code_flag
, CODE_64BIT
},
1058 {"intel_syntax", set_intel_syntax
, 1},
1059 {"att_syntax", set_intel_syntax
, 0},
1060 {"intel_mnemonic", set_intel_mnemonic
, 1},
1061 {"att_mnemonic", set_intel_mnemonic
, 0},
1062 {"allow_index_reg", set_allow_index_reg
, 1},
1063 {"disallow_index_reg", set_allow_index_reg
, 0},
1064 {"sse_check", set_check
, 0},
1065 {"operand_check", set_check
, 1},
1066 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1067 {"largecomm", handle_large_common
, 0},
1069 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1070 {"loc", dwarf2_directive_loc
, 0},
1071 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1074 {"secrel32", pe_directive_secrel
, 0},
1079 /* For interface with expression (). */
1080 extern char *input_line_pointer
;
1082 /* Hash table for instruction mnemonic lookup. */
1083 static struct hash_control
*op_hash
;
1085 /* Hash table for register lookup. */
1086 static struct hash_control
*reg_hash
;
1089 i386_align_code (fragS
*fragP
, int count
)
1091 /* Various efficient no-op patterns for aligning code labels.
1092 Note: Don't try to assemble the instructions in the comments.
1093 0L and 0w are not legal. */
1094 static const unsigned char f32_1
[] =
1096 static const unsigned char f32_2
[] =
1097 {0x66,0x90}; /* xchg %ax,%ax */
1098 static const unsigned char f32_3
[] =
1099 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1100 static const unsigned char f32_4
[] =
1101 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1102 static const unsigned char f32_5
[] =
1104 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1105 static const unsigned char f32_6
[] =
1106 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1107 static const unsigned char f32_7
[] =
1108 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1109 static const unsigned char f32_8
[] =
1111 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1112 static const unsigned char f32_9
[] =
1113 {0x89,0xf6, /* movl %esi,%esi */
1114 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1115 static const unsigned char f32_10
[] =
1116 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1117 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1118 static const unsigned char f32_11
[] =
1119 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1120 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1121 static const unsigned char f32_12
[] =
1122 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1123 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1124 static const unsigned char f32_13
[] =
1125 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1126 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1127 static const unsigned char f32_14
[] =
1128 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1129 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1130 static const unsigned char f16_3
[] =
1131 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1132 static const unsigned char f16_4
[] =
1133 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1134 static const unsigned char f16_5
[] =
1136 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1137 static const unsigned char f16_6
[] =
1138 {0x89,0xf6, /* mov %si,%si */
1139 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1140 static const unsigned char f16_7
[] =
1141 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1142 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1143 static const unsigned char f16_8
[] =
1144 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1145 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1146 static const unsigned char jump_31
[] =
1147 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1148 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1149 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1150 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1151 static const unsigned char *const f32_patt
[] = {
1152 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1153 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1155 static const unsigned char *const f16_patt
[] = {
1156 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1158 /* nopl (%[re]ax) */
1159 static const unsigned char alt_3
[] =
1161 /* nopl 0(%[re]ax) */
1162 static const unsigned char alt_4
[] =
1163 {0x0f,0x1f,0x40,0x00};
1164 /* nopl 0(%[re]ax,%[re]ax,1) */
1165 static const unsigned char alt_5
[] =
1166 {0x0f,0x1f,0x44,0x00,0x00};
1167 /* nopw 0(%[re]ax,%[re]ax,1) */
1168 static const unsigned char alt_6
[] =
1169 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1170 /* nopl 0L(%[re]ax) */
1171 static const unsigned char alt_7
[] =
1172 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1173 /* nopl 0L(%[re]ax,%[re]ax,1) */
1174 static const unsigned char alt_8
[] =
1175 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1176 /* nopw 0L(%[re]ax,%[re]ax,1) */
1177 static const unsigned char alt_9
[] =
1178 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1179 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1180 static const unsigned char alt_10
[] =
1181 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1182 static const unsigned char *const alt_patt
[] = {
1183 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1187 /* Only align for at least a positive non-zero boundary. */
1188 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1191 /* We need to decide which NOP sequence to use for 32bit and
1192 64bit. When -mtune= is used:
1194 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1195 PROCESSOR_GENERIC32, f32_patt will be used.
1196 2. For the rest, alt_patt will be used.
1198 When -mtune= isn't used, alt_patt will be used if
1199 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1202 When -march= or .arch is used, we can't use anything beyond
1203 cpu_arch_isa_flags. */
1205 if (flag_code
== CODE_16BIT
)
1209 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1211 /* Adjust jump offset. */
1212 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1215 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1216 f16_patt
[count
- 1], count
);
1220 const unsigned char *const *patt
= NULL
;
1222 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1224 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1225 switch (cpu_arch_tune
)
1227 case PROCESSOR_UNKNOWN
:
1228 /* We use cpu_arch_isa_flags to check if we SHOULD
1229 optimize with nops. */
1230 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1235 case PROCESSOR_PENTIUM4
:
1236 case PROCESSOR_NOCONA
:
1237 case PROCESSOR_CORE
:
1238 case PROCESSOR_CORE2
:
1239 case PROCESSOR_COREI7
:
1240 case PROCESSOR_L1OM
:
1241 case PROCESSOR_K1OM
:
1242 case PROCESSOR_GENERIC64
:
1244 case PROCESSOR_ATHLON
:
1246 case PROCESSOR_AMDFAM10
:
1248 case PROCESSOR_ZNVER
:
1252 case PROCESSOR_I386
:
1253 case PROCESSOR_I486
:
1254 case PROCESSOR_PENTIUM
:
1255 case PROCESSOR_PENTIUMPRO
:
1256 case PROCESSOR_IAMCU
:
1257 case PROCESSOR_GENERIC32
:
1264 switch (fragP
->tc_frag_data
.tune
)
1266 case PROCESSOR_UNKNOWN
:
1267 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1268 PROCESSOR_UNKNOWN. */
1272 case PROCESSOR_I386
:
1273 case PROCESSOR_I486
:
1274 case PROCESSOR_PENTIUM
:
1275 case PROCESSOR_IAMCU
:
1277 case PROCESSOR_ATHLON
:
1279 case PROCESSOR_AMDFAM10
:
1281 case PROCESSOR_ZNVER
:
1283 case PROCESSOR_GENERIC32
:
1284 /* We use cpu_arch_isa_flags to check if we CAN optimize
1286 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1291 case PROCESSOR_PENTIUMPRO
:
1292 case PROCESSOR_PENTIUM4
:
1293 case PROCESSOR_NOCONA
:
1294 case PROCESSOR_CORE
:
1295 case PROCESSOR_CORE2
:
1296 case PROCESSOR_COREI7
:
1297 case PROCESSOR_L1OM
:
1298 case PROCESSOR_K1OM
:
1299 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1304 case PROCESSOR_GENERIC64
:
1310 if (patt
== f32_patt
)
1312 /* If the padding is less than 15 bytes, we use the normal
1313 ones. Otherwise, we use a jump instruction and adjust
1317 /* For 64bit, the limit is 3 bytes. */
1318 if (flag_code
== CODE_64BIT
1319 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1324 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1325 patt
[count
- 1], count
);
1328 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1330 /* Adjust jump offset. */
1331 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1336 /* Maximum length of an instruction is 10 byte. If the
1337 padding is greater than 10 bytes and we don't use jump,
1338 we have to break it into smaller pieces. */
1339 int padding
= count
;
1340 while (padding
> 10)
1343 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1348 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1349 patt
[padding
- 1], padding
);
1352 fragP
->fr_var
= count
;
1356 operand_type_all_zero (const union i386_operand_type
*x
)
1358 switch (ARRAY_SIZE(x
->array
))
1367 return !x
->array
[0];
1374 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1376 switch (ARRAY_SIZE(x
->array
))
1391 operand_type_equal (const union i386_operand_type
*x
,
1392 const union i386_operand_type
*y
)
1394 switch (ARRAY_SIZE(x
->array
))
1397 if (x
->array
[2] != y
->array
[2])
1400 if (x
->array
[1] != y
->array
[1])
1403 return x
->array
[0] == y
->array
[0];
1411 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1413 switch (ARRAY_SIZE(x
->array
))
1422 return !x
->array
[0];
1429 cpu_flags_equal (const union i386_cpu_flags
*x
,
1430 const union i386_cpu_flags
*y
)
1432 switch (ARRAY_SIZE(x
->array
))
1435 if (x
->array
[2] != y
->array
[2])
1438 if (x
->array
[1] != y
->array
[1])
1441 return x
->array
[0] == y
->array
[0];
1449 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1451 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1452 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1455 static INLINE i386_cpu_flags
1456 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1458 switch (ARRAY_SIZE (x
.array
))
1461 x
.array
[2] &= y
.array
[2];
1463 x
.array
[1] &= y
.array
[1];
1465 x
.array
[0] &= y
.array
[0];
1473 static INLINE i386_cpu_flags
1474 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1476 switch (ARRAY_SIZE (x
.array
))
1479 x
.array
[2] |= y
.array
[2];
1481 x
.array
[1] |= y
.array
[1];
1483 x
.array
[0] |= y
.array
[0];
1491 static INLINE i386_cpu_flags
1492 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1494 switch (ARRAY_SIZE (x
.array
))
1497 x
.array
[2] &= ~y
.array
[2];
1499 x
.array
[1] &= ~y
.array
[1];
1501 x
.array
[0] &= ~y
.array
[0];
1510 valid_iamcu_cpu_flags (const i386_cpu_flags
*flags
)
1512 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
1514 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_COMPAT_FLAGS
;
1515 i386_cpu_flags compat_flags
;
1516 compat_flags
= cpu_flags_and_not (*flags
, iamcu_flags
);
1517 return cpu_flags_all_zero (&compat_flags
);
1523 #define CPU_FLAGS_ARCH_MATCH 0x1
1524 #define CPU_FLAGS_64BIT_MATCH 0x2
1525 #define CPU_FLAGS_AES_MATCH 0x4
1526 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1527 #define CPU_FLAGS_AVX_MATCH 0x10
1529 #define CPU_FLAGS_32BIT_MATCH \
1530 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1531 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1532 #define CPU_FLAGS_PERFECT_MATCH \
1533 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1535 /* Return CPU flags match bits. */
1538 cpu_flags_match (const insn_template
*t
)
1540 i386_cpu_flags x
= t
->cpu_flags
;
1541 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1543 x
.bitfield
.cpu64
= 0;
1544 x
.bitfield
.cpuno64
= 0;
1546 if (cpu_flags_all_zero (&x
))
1548 /* This instruction is available on all archs. */
1549 match
|= CPU_FLAGS_32BIT_MATCH
;
1553 /* This instruction is available only on some archs. */
1554 i386_cpu_flags cpu
= cpu_arch_flags
;
1556 cpu
= cpu_flags_and (x
, cpu
);
1557 if (!cpu_flags_all_zero (&cpu
))
1559 if (x
.bitfield
.cpuavx
)
1561 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1562 if (cpu
.bitfield
.cpuavx
)
1564 /* Check SSE2AVX. */
1565 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1567 match
|= (CPU_FLAGS_ARCH_MATCH
1568 | CPU_FLAGS_AVX_MATCH
);
1570 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1571 match
|= CPU_FLAGS_AES_MATCH
;
1573 if (!x
.bitfield
.cpupclmul
1574 || cpu
.bitfield
.cpupclmul
)
1575 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1579 match
|= CPU_FLAGS_ARCH_MATCH
;
1581 else if (x
.bitfield
.cpuavx512vl
)
1583 /* Match AVX512VL. */
1584 if (cpu
.bitfield
.cpuavx512vl
)
1586 /* Need another match. */
1587 cpu
.bitfield
.cpuavx512vl
= 0;
1588 if (!cpu_flags_all_zero (&cpu
))
1589 match
|= CPU_FLAGS_32BIT_MATCH
;
1591 match
|= CPU_FLAGS_ARCH_MATCH
;
1594 match
|= CPU_FLAGS_ARCH_MATCH
;
1597 match
|= CPU_FLAGS_32BIT_MATCH
;
1603 static INLINE i386_operand_type
1604 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1606 switch (ARRAY_SIZE (x
.array
))
1609 x
.array
[2] &= y
.array
[2];
1611 x
.array
[1] &= y
.array
[1];
1613 x
.array
[0] &= y
.array
[0];
1621 static INLINE i386_operand_type
1622 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1624 switch (ARRAY_SIZE (x
.array
))
1627 x
.array
[2] |= y
.array
[2];
1629 x
.array
[1] |= y
.array
[1];
1631 x
.array
[0] |= y
.array
[0];
1639 static INLINE i386_operand_type
1640 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1642 switch (ARRAY_SIZE (x
.array
))
1645 x
.array
[2] ^= y
.array
[2];
1647 x
.array
[1] ^= y
.array
[1];
1649 x
.array
[0] ^= y
.array
[0];
1657 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1658 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1659 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1660 static const i386_operand_type inoutportreg
1661 = OPERAND_TYPE_INOUTPORTREG
;
1662 static const i386_operand_type reg16_inoutportreg
1663 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1664 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1665 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1666 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1667 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1668 static const i386_operand_type anydisp
1669 = OPERAND_TYPE_ANYDISP
;
1670 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1671 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1672 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1673 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1674 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1675 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1676 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1677 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1678 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1679 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1680 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1681 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1682 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1683 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1694 operand_type_check (i386_operand_type t
, enum operand_type c
)
1699 return (t
.bitfield
.reg8
1702 || t
.bitfield
.reg64
);
1705 return (t
.bitfield
.imm8
1709 || t
.bitfield
.imm32s
1710 || t
.bitfield
.imm64
);
1713 return (t
.bitfield
.disp8
1714 || t
.bitfield
.disp16
1715 || t
.bitfield
.disp32
1716 || t
.bitfield
.disp32s
1717 || t
.bitfield
.disp64
);
1720 return (t
.bitfield
.disp8
1721 || t
.bitfield
.disp16
1722 || t
.bitfield
.disp32
1723 || t
.bitfield
.disp32s
1724 || t
.bitfield
.disp64
1725 || t
.bitfield
.baseindex
);
1734 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1735 operand J for instruction template T. */
1738 match_reg_size (const insn_template
*t
, unsigned int j
)
1740 return !((i
.types
[j
].bitfield
.byte
1741 && !t
->operand_types
[j
].bitfield
.byte
)
1742 || (i
.types
[j
].bitfield
.word
1743 && !t
->operand_types
[j
].bitfield
.word
)
1744 || (i
.types
[j
].bitfield
.dword
1745 && !t
->operand_types
[j
].bitfield
.dword
)
1746 || (i
.types
[j
].bitfield
.qword
1747 && !t
->operand_types
[j
].bitfield
.qword
));
1750 /* Return 1 if there is no conflict in any size on operand J for
1751 instruction template T. */
1754 match_mem_size (const insn_template
*t
, unsigned int j
)
1756 return (match_reg_size (t
, j
)
1757 && !((i
.types
[j
].bitfield
.unspecified
1759 && !t
->operand_types
[j
].bitfield
.unspecified
)
1760 || (i
.types
[j
].bitfield
.fword
1761 && !t
->operand_types
[j
].bitfield
.fword
)
1762 || (i
.types
[j
].bitfield
.tbyte
1763 && !t
->operand_types
[j
].bitfield
.tbyte
)
1764 || (i
.types
[j
].bitfield
.xmmword
1765 && !t
->operand_types
[j
].bitfield
.xmmword
)
1766 || (i
.types
[j
].bitfield
.ymmword
1767 && !t
->operand_types
[j
].bitfield
.ymmword
)
1768 || (i
.types
[j
].bitfield
.zmmword
1769 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1772 /* Return 1 if there is no size conflict on any operands for
1773 instruction template T. */
1776 operand_size_match (const insn_template
*t
)
1781 /* Don't check jump instructions. */
1782 if (t
->opcode_modifier
.jump
1783 || t
->opcode_modifier
.jumpbyte
1784 || t
->opcode_modifier
.jumpdword
1785 || t
->opcode_modifier
.jumpintersegment
)
1788 /* Check memory and accumulator operand size. */
1789 for (j
= 0; j
< i
.operands
; j
++)
1791 if (t
->operand_types
[j
].bitfield
.anysize
)
1794 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1800 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1809 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1812 i
.error
= operand_size_mismatch
;
1816 /* Check reverse. */
1817 gas_assert (i
.operands
== 2);
1820 for (j
= 0; j
< 2; j
++)
1822 if (t
->operand_types
[j
].bitfield
.acc
1823 && !match_reg_size (t
, j
? 0 : 1))
1826 if (i
.types
[j
].bitfield
.mem
1827 && !match_mem_size (t
, j
? 0 : 1))
1835 operand_type_match (i386_operand_type overlap
,
1836 i386_operand_type given
)
1838 i386_operand_type temp
= overlap
;
1840 temp
.bitfield
.jumpabsolute
= 0;
1841 temp
.bitfield
.unspecified
= 0;
1842 temp
.bitfield
.byte
= 0;
1843 temp
.bitfield
.word
= 0;
1844 temp
.bitfield
.dword
= 0;
1845 temp
.bitfield
.fword
= 0;
1846 temp
.bitfield
.qword
= 0;
1847 temp
.bitfield
.tbyte
= 0;
1848 temp
.bitfield
.xmmword
= 0;
1849 temp
.bitfield
.ymmword
= 0;
1850 temp
.bitfield
.zmmword
= 0;
1851 if (operand_type_all_zero (&temp
))
1854 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1855 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1859 i
.error
= operand_type_mismatch
;
1863 /* If given types g0 and g1 are registers they must be of the same type
1864 unless the expected operand type register overlap is null.
1865 Note that Acc in a template matches every size of reg. */
1868 operand_type_register_match (i386_operand_type m0
,
1869 i386_operand_type g0
,
1870 i386_operand_type t0
,
1871 i386_operand_type m1
,
1872 i386_operand_type g1
,
1873 i386_operand_type t1
)
1875 if (!operand_type_check (g0
, reg
))
1878 if (!operand_type_check (g1
, reg
))
1881 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1882 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1883 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1884 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1887 if (m0
.bitfield
.acc
)
1889 t0
.bitfield
.reg8
= 1;
1890 t0
.bitfield
.reg16
= 1;
1891 t0
.bitfield
.reg32
= 1;
1892 t0
.bitfield
.reg64
= 1;
1895 if (m1
.bitfield
.acc
)
1897 t1
.bitfield
.reg8
= 1;
1898 t1
.bitfield
.reg16
= 1;
1899 t1
.bitfield
.reg32
= 1;
1900 t1
.bitfield
.reg64
= 1;
1903 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1904 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1905 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1906 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1909 i
.error
= register_type_mismatch
;
1914 static INLINE
unsigned int
1915 register_number (const reg_entry
*r
)
1917 unsigned int nr
= r
->reg_num
;
1919 if (r
->reg_flags
& RegRex
)
1922 if (r
->reg_flags
& RegVRex
)
1928 static INLINE
unsigned int
1929 mode_from_disp_size (i386_operand_type t
)
1931 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1933 else if (t
.bitfield
.disp16
1934 || t
.bitfield
.disp32
1935 || t
.bitfield
.disp32s
)
1942 fits_in_signed_byte (addressT num
)
1944 return num
+ 0x80 <= 0xff;
1948 fits_in_unsigned_byte (addressT num
)
1954 fits_in_unsigned_word (addressT num
)
1956 return num
<= 0xffff;
1960 fits_in_signed_word (addressT num
)
1962 return num
+ 0x8000 <= 0xffff;
1966 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1971 return num
+ 0x80000000 <= 0xffffffff;
1973 } /* fits_in_signed_long() */
1976 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
1981 return num
<= 0xffffffff;
1983 } /* fits_in_unsigned_long() */
1986 fits_in_vec_disp8 (offsetT num
)
1988 int shift
= i
.memshift
;
1994 mask
= (1 << shift
) - 1;
1996 /* Return 0 if NUM isn't properly aligned. */
2000 /* Check if NUM will fit in 8bit after shift. */
2001 return fits_in_signed_byte (num
>> shift
);
2005 fits_in_imm4 (offsetT num
)
2007 return (num
& 0xf) == num
;
2010 static i386_operand_type
2011 smallest_imm_type (offsetT num
)
2013 i386_operand_type t
;
2015 operand_type_set (&t
, 0);
2016 t
.bitfield
.imm64
= 1;
2018 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2020 /* This code is disabled on the 486 because all the Imm1 forms
2021 in the opcode table are slower on the i486. They're the
2022 versions with the implicitly specified single-position
2023 displacement, which has another syntax if you really want to
2025 t
.bitfield
.imm1
= 1;
2026 t
.bitfield
.imm8
= 1;
2027 t
.bitfield
.imm8s
= 1;
2028 t
.bitfield
.imm16
= 1;
2029 t
.bitfield
.imm32
= 1;
2030 t
.bitfield
.imm32s
= 1;
2032 else if (fits_in_signed_byte (num
))
2034 t
.bitfield
.imm8
= 1;
2035 t
.bitfield
.imm8s
= 1;
2036 t
.bitfield
.imm16
= 1;
2037 t
.bitfield
.imm32
= 1;
2038 t
.bitfield
.imm32s
= 1;
2040 else if (fits_in_unsigned_byte (num
))
2042 t
.bitfield
.imm8
= 1;
2043 t
.bitfield
.imm16
= 1;
2044 t
.bitfield
.imm32
= 1;
2045 t
.bitfield
.imm32s
= 1;
2047 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2049 t
.bitfield
.imm16
= 1;
2050 t
.bitfield
.imm32
= 1;
2051 t
.bitfield
.imm32s
= 1;
2053 else if (fits_in_signed_long (num
))
2055 t
.bitfield
.imm32
= 1;
2056 t
.bitfield
.imm32s
= 1;
2058 else if (fits_in_unsigned_long (num
))
2059 t
.bitfield
.imm32
= 1;
2065 offset_in_range (offsetT val
, int size
)
2071 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2072 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2073 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2075 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2081 /* If BFD64, sign extend val for 32bit address mode. */
2082 if (flag_code
!= CODE_64BIT
2083 || i
.prefix
[ADDR_PREFIX
])
2084 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2085 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2088 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2090 char buf1
[40], buf2
[40];
2092 sprint_value (buf1
, val
);
2093 sprint_value (buf2
, val
& mask
);
2094 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2108 a. PREFIX_EXIST if attempting to add a prefix where one from the
2109 same class already exists.
2110 b. PREFIX_LOCK if lock prefix is added.
2111 c. PREFIX_REP if rep/repne prefix is added.
2112 d. PREFIX_OTHER if other prefix is added.
2115 static enum PREFIX_GROUP
2116 add_prefix (unsigned int prefix
)
2118 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2121 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2122 && flag_code
== CODE_64BIT
)
2124 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2125 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2126 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2137 case CS_PREFIX_OPCODE
:
2138 case DS_PREFIX_OPCODE
:
2139 case ES_PREFIX_OPCODE
:
2140 case FS_PREFIX_OPCODE
:
2141 case GS_PREFIX_OPCODE
:
2142 case SS_PREFIX_OPCODE
:
2146 case REPNE_PREFIX_OPCODE
:
2147 case REPE_PREFIX_OPCODE
:
2152 case LOCK_PREFIX_OPCODE
:
2161 case ADDR_PREFIX_OPCODE
:
2165 case DATA_PREFIX_OPCODE
:
2169 if (i
.prefix
[q
] != 0)
2177 i
.prefix
[q
] |= prefix
;
2180 as_bad (_("same type of prefix used twice"));
2186 update_code_flag (int value
, int check
)
2188 PRINTF_LIKE ((*as_error
));
2190 flag_code
= (enum flag_code
) value
;
2191 if (flag_code
== CODE_64BIT
)
2193 cpu_arch_flags
.bitfield
.cpu64
= 1;
2194 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2198 cpu_arch_flags
.bitfield
.cpu64
= 0;
2199 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2201 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2204 as_error
= as_fatal
;
2207 (*as_error
) (_("64bit mode not supported on `%s'."),
2208 cpu_arch_name
? cpu_arch_name
: default_arch
);
2210 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2213 as_error
= as_fatal
;
2216 (*as_error
) (_("32bit mode not supported on `%s'."),
2217 cpu_arch_name
? cpu_arch_name
: default_arch
);
2219 stackop_size
= '\0';
2223 set_code_flag (int value
)
2225 update_code_flag (value
, 0);
2229 set_16bit_gcc_code_flag (int new_code_flag
)
2231 flag_code
= (enum flag_code
) new_code_flag
;
2232 if (flag_code
!= CODE_16BIT
)
2234 cpu_arch_flags
.bitfield
.cpu64
= 0;
2235 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2236 stackop_size
= LONG_MNEM_SUFFIX
;
2240 set_intel_syntax (int syntax_flag
)
2242 /* Find out if register prefixing is specified. */
2243 int ask_naked_reg
= 0;
2246 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2249 int e
= get_symbol_name (&string
);
2251 if (strcmp (string
, "prefix") == 0)
2253 else if (strcmp (string
, "noprefix") == 0)
2256 as_bad (_("bad argument to syntax directive."));
2257 (void) restore_line_pointer (e
);
2259 demand_empty_rest_of_line ();
2261 intel_syntax
= syntax_flag
;
2263 if (ask_naked_reg
== 0)
2264 allow_naked_reg
= (intel_syntax
2265 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2267 allow_naked_reg
= (ask_naked_reg
< 0);
2269 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2271 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2272 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2273 register_prefix
= allow_naked_reg
? "" : "%";
2277 set_intel_mnemonic (int mnemonic_flag
)
2279 intel_mnemonic
= mnemonic_flag
;
2283 set_allow_index_reg (int flag
)
2285 allow_index_reg
= flag
;
2289 set_check (int what
)
2291 enum check_kind
*kind
;
2296 kind
= &operand_check
;
2307 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2310 int e
= get_symbol_name (&string
);
2312 if (strcmp (string
, "none") == 0)
2314 else if (strcmp (string
, "warning") == 0)
2315 *kind
= check_warning
;
2316 else if (strcmp (string
, "error") == 0)
2317 *kind
= check_error
;
2319 as_bad (_("bad argument to %s_check directive."), str
);
2320 (void) restore_line_pointer (e
);
2323 as_bad (_("missing argument for %s_check directive"), str
);
2325 demand_empty_rest_of_line ();
2329 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2330 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2332 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2333 static const char *arch
;
2335 /* Intel LIOM is only supported on ELF. */
2341 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2342 use default_arch. */
2343 arch
= cpu_arch_name
;
2345 arch
= default_arch
;
2348 /* If we are targeting Intel MCU, we must enable it. */
2349 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2350 || new_flag
.bitfield
.cpuiamcu
)
2353 /* If we are targeting Intel L1OM, we must enable it. */
2354 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2355 || new_flag
.bitfield
.cpul1om
)
2358 /* If we are targeting Intel K1OM, we must enable it. */
2359 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2360 || new_flag
.bitfield
.cpuk1om
)
2363 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2368 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2372 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2375 int e
= get_symbol_name (&string
);
2377 i386_cpu_flags flags
;
2379 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2381 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2383 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2387 cpu_arch_name
= cpu_arch
[j
].name
;
2388 cpu_sub_arch_name
= NULL
;
2389 cpu_arch_flags
= cpu_arch
[j
].flags
;
2390 if (flag_code
== CODE_64BIT
)
2392 cpu_arch_flags
.bitfield
.cpu64
= 1;
2393 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2397 cpu_arch_flags
.bitfield
.cpu64
= 0;
2398 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2400 cpu_arch_isa
= cpu_arch
[j
].type
;
2401 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2402 if (!cpu_arch_tune_set
)
2404 cpu_arch_tune
= cpu_arch_isa
;
2405 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2410 flags
= cpu_flags_or (cpu_arch_flags
,
2413 if (!valid_iamcu_cpu_flags (&flags
))
2414 as_fatal (_("`%s' isn't valid for Intel MCU"),
2416 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2418 if (cpu_sub_arch_name
)
2420 char *name
= cpu_sub_arch_name
;
2421 cpu_sub_arch_name
= concat (name
,
2423 (const char *) NULL
);
2427 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2428 cpu_arch_flags
= flags
;
2429 cpu_arch_isa_flags
= flags
;
2431 (void) restore_line_pointer (e
);
2432 demand_empty_rest_of_line ();
2437 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2439 /* Disable an ISA entension. */
2440 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2441 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2443 flags
= cpu_flags_and_not (cpu_arch_flags
,
2444 cpu_noarch
[j
].flags
);
2445 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2447 if (cpu_sub_arch_name
)
2449 char *name
= cpu_sub_arch_name
;
2450 cpu_sub_arch_name
= concat (name
, string
,
2451 (const char *) NULL
);
2455 cpu_sub_arch_name
= xstrdup (string
);
2456 cpu_arch_flags
= flags
;
2457 cpu_arch_isa_flags
= flags
;
2459 (void) restore_line_pointer (e
);
2460 demand_empty_rest_of_line ();
2464 j
= ARRAY_SIZE (cpu_arch
);
2467 if (j
>= ARRAY_SIZE (cpu_arch
))
2468 as_bad (_("no such architecture: `%s'"), string
);
2470 *input_line_pointer
= e
;
2473 as_bad (_("missing cpu architecture"));
2475 no_cond_jump_promotion
= 0;
2476 if (*input_line_pointer
== ','
2477 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2482 ++input_line_pointer
;
2483 e
= get_symbol_name (&string
);
2485 if (strcmp (string
, "nojumps") == 0)
2486 no_cond_jump_promotion
= 1;
2487 else if (strcmp (string
, "jumps") == 0)
2490 as_bad (_("no such architecture modifier: `%s'"), string
);
2492 (void) restore_line_pointer (e
);
2495 demand_empty_rest_of_line ();
2498 enum bfd_architecture
2501 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2503 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2504 || flag_code
!= CODE_64BIT
)
2505 as_fatal (_("Intel L1OM is 64bit ELF only"));
2506 return bfd_arch_l1om
;
2508 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2510 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2511 || flag_code
!= CODE_64BIT
)
2512 as_fatal (_("Intel K1OM is 64bit ELF only"));
2513 return bfd_arch_k1om
;
2515 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2517 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2518 || flag_code
== CODE_64BIT
)
2519 as_fatal (_("Intel MCU is 32bit ELF only"));
2520 return bfd_arch_iamcu
;
2523 return bfd_arch_i386
;
2529 if (!strncmp (default_arch
, "x86_64", 6))
2531 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2533 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2534 || default_arch
[6] != '\0')
2535 as_fatal (_("Intel L1OM is 64bit ELF only"));
2536 return bfd_mach_l1om
;
2538 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2540 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2541 || default_arch
[6] != '\0')
2542 as_fatal (_("Intel K1OM is 64bit ELF only"));
2543 return bfd_mach_k1om
;
2545 else if (default_arch
[6] == '\0')
2546 return bfd_mach_x86_64
;
2548 return bfd_mach_x64_32
;
2550 else if (!strcmp (default_arch
, "i386")
2551 || !strcmp (default_arch
, "iamcu"))
2553 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2555 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2556 as_fatal (_("Intel MCU is 32bit ELF only"));
2557 return bfd_mach_i386_iamcu
;
2560 return bfd_mach_i386_i386
;
2563 as_fatal (_("unknown architecture"));
2569 const char *hash_err
;
2571 /* Initialize op_hash hash table. */
2572 op_hash
= hash_new ();
2575 const insn_template
*optab
;
2576 templates
*core_optab
;
2578 /* Setup for loop. */
2580 core_optab
= XNEW (templates
);
2581 core_optab
->start
= optab
;
2586 if (optab
->name
== NULL
2587 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2589 /* different name --> ship out current template list;
2590 add to hash table; & begin anew. */
2591 core_optab
->end
= optab
;
2592 hash_err
= hash_insert (op_hash
,
2594 (void *) core_optab
);
2597 as_fatal (_("can't hash %s: %s"),
2601 if (optab
->name
== NULL
)
2603 core_optab
= XNEW (templates
);
2604 core_optab
->start
= optab
;
2609 /* Initialize reg_hash hash table. */
2610 reg_hash
= hash_new ();
2612 const reg_entry
*regtab
;
2613 unsigned int regtab_size
= i386_regtab_size
;
2615 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2617 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2619 as_fatal (_("can't hash %s: %s"),
2625 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2630 for (c
= 0; c
< 256; c
++)
2635 mnemonic_chars
[c
] = c
;
2636 register_chars
[c
] = c
;
2637 operand_chars
[c
] = c
;
2639 else if (ISLOWER (c
))
2641 mnemonic_chars
[c
] = c
;
2642 register_chars
[c
] = c
;
2643 operand_chars
[c
] = c
;
2645 else if (ISUPPER (c
))
2647 mnemonic_chars
[c
] = TOLOWER (c
);
2648 register_chars
[c
] = mnemonic_chars
[c
];
2649 operand_chars
[c
] = c
;
2651 else if (c
== '{' || c
== '}')
2652 operand_chars
[c
] = c
;
2654 if (ISALPHA (c
) || ISDIGIT (c
))
2655 identifier_chars
[c
] = c
;
2658 identifier_chars
[c
] = c
;
2659 operand_chars
[c
] = c
;
2664 identifier_chars
['@'] = '@';
2667 identifier_chars
['?'] = '?';
2668 operand_chars
['?'] = '?';
2670 digit_chars
['-'] = '-';
2671 mnemonic_chars
['_'] = '_';
2672 mnemonic_chars
['-'] = '-';
2673 mnemonic_chars
['.'] = '.';
2674 identifier_chars
['_'] = '_';
2675 identifier_chars
['.'] = '.';
2677 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2678 operand_chars
[(unsigned char) *p
] = *p
;
2681 if (flag_code
== CODE_64BIT
)
2683 #if defined (OBJ_COFF) && defined (TE_PE)
2684 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2687 x86_dwarf2_return_column
= 16;
2689 x86_cie_data_alignment
= -8;
2693 x86_dwarf2_return_column
= 8;
2694 x86_cie_data_alignment
= -4;
2699 i386_print_statistics (FILE *file
)
2701 hash_print_statistics (file
, "i386 opcode", op_hash
);
2702 hash_print_statistics (file
, "i386 register", reg_hash
);
2707 /* Debugging routines for md_assemble. */
2708 static void pte (insn_template
*);
2709 static void pt (i386_operand_type
);
2710 static void pe (expressionS
*);
2711 static void ps (symbolS
*);
2714 pi (char *line
, i386_insn
*x
)
2718 fprintf (stdout
, "%s: template ", line
);
2720 fprintf (stdout
, " address: base %s index %s scale %x\n",
2721 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2722 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2723 x
->log2_scale_factor
);
2724 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2725 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2726 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2727 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2728 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2729 (x
->rex
& REX_W
) != 0,
2730 (x
->rex
& REX_R
) != 0,
2731 (x
->rex
& REX_X
) != 0,
2732 (x
->rex
& REX_B
) != 0);
2733 for (j
= 0; j
< x
->operands
; j
++)
2735 fprintf (stdout
, " #%d: ", j
+ 1);
2737 fprintf (stdout
, "\n");
2738 if (x
->types
[j
].bitfield
.reg8
2739 || x
->types
[j
].bitfield
.reg16
2740 || x
->types
[j
].bitfield
.reg32
2741 || x
->types
[j
].bitfield
.reg64
2742 || x
->types
[j
].bitfield
.regmmx
2743 || x
->types
[j
].bitfield
.regxmm
2744 || x
->types
[j
].bitfield
.regymm
2745 || x
->types
[j
].bitfield
.regzmm
2746 || x
->types
[j
].bitfield
.sreg2
2747 || x
->types
[j
].bitfield
.sreg3
2748 || x
->types
[j
].bitfield
.control
2749 || x
->types
[j
].bitfield
.debug
2750 || x
->types
[j
].bitfield
.test
)
2751 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2752 if (operand_type_check (x
->types
[j
], imm
))
2754 if (operand_type_check (x
->types
[j
], disp
))
2755 pe (x
->op
[j
].disps
);
2760 pte (insn_template
*t
)
2763 fprintf (stdout
, " %d operands ", t
->operands
);
2764 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2765 if (t
->extension_opcode
!= None
)
2766 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2767 if (t
->opcode_modifier
.d
)
2768 fprintf (stdout
, "D");
2769 if (t
->opcode_modifier
.w
)
2770 fprintf (stdout
, "W");
2771 fprintf (stdout
, "\n");
2772 for (j
= 0; j
< t
->operands
; j
++)
2774 fprintf (stdout
, " #%d type ", j
+ 1);
2775 pt (t
->operand_types
[j
]);
2776 fprintf (stdout
, "\n");
2783 fprintf (stdout
, " operation %d\n", e
->X_op
);
2784 fprintf (stdout
, " add_number %ld (%lx)\n",
2785 (long) e
->X_add_number
, (long) e
->X_add_number
);
2786 if (e
->X_add_symbol
)
2788 fprintf (stdout
, " add_symbol ");
2789 ps (e
->X_add_symbol
);
2790 fprintf (stdout
, "\n");
2794 fprintf (stdout
, " op_symbol ");
2795 ps (e
->X_op_symbol
);
2796 fprintf (stdout
, "\n");
2803 fprintf (stdout
, "%s type %s%s",
2805 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2806 segment_name (S_GET_SEGMENT (s
)));
2809 static struct type_name
2811 i386_operand_type mask
;
2814 const type_names
[] =
2816 { OPERAND_TYPE_REG8
, "r8" },
2817 { OPERAND_TYPE_REG16
, "r16" },
2818 { OPERAND_TYPE_REG32
, "r32" },
2819 { OPERAND_TYPE_REG64
, "r64" },
2820 { OPERAND_TYPE_IMM8
, "i8" },
2821 { OPERAND_TYPE_IMM8
, "i8s" },
2822 { OPERAND_TYPE_IMM16
, "i16" },
2823 { OPERAND_TYPE_IMM32
, "i32" },
2824 { OPERAND_TYPE_IMM32S
, "i32s" },
2825 { OPERAND_TYPE_IMM64
, "i64" },
2826 { OPERAND_TYPE_IMM1
, "i1" },
2827 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2828 { OPERAND_TYPE_DISP8
, "d8" },
2829 { OPERAND_TYPE_DISP16
, "d16" },
2830 { OPERAND_TYPE_DISP32
, "d32" },
2831 { OPERAND_TYPE_DISP32S
, "d32s" },
2832 { OPERAND_TYPE_DISP64
, "d64" },
2833 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2834 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2835 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2836 { OPERAND_TYPE_CONTROL
, "control reg" },
2837 { OPERAND_TYPE_TEST
, "test reg" },
2838 { OPERAND_TYPE_DEBUG
, "debug reg" },
2839 { OPERAND_TYPE_FLOATREG
, "FReg" },
2840 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2841 { OPERAND_TYPE_SREG2
, "SReg2" },
2842 { OPERAND_TYPE_SREG3
, "SReg3" },
2843 { OPERAND_TYPE_ACC
, "Acc" },
2844 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2845 { OPERAND_TYPE_REGMMX
, "rMMX" },
2846 { OPERAND_TYPE_REGXMM
, "rXMM" },
2847 { OPERAND_TYPE_REGYMM
, "rYMM" },
2848 { OPERAND_TYPE_REGZMM
, "rZMM" },
2849 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2850 { OPERAND_TYPE_ESSEG
, "es" },
2854 pt (i386_operand_type t
)
2857 i386_operand_type a
;
2859 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2861 a
= operand_type_and (t
, type_names
[j
].mask
);
2862 if (!operand_type_all_zero (&a
))
2863 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2868 #endif /* DEBUG386 */
2870 static bfd_reloc_code_real_type
2871 reloc (unsigned int size
,
2874 bfd_reloc_code_real_type other
)
2876 if (other
!= NO_RELOC
)
2878 reloc_howto_type
*rel
;
2883 case BFD_RELOC_X86_64_GOT32
:
2884 return BFD_RELOC_X86_64_GOT64
;
2886 case BFD_RELOC_X86_64_GOTPLT64
:
2887 return BFD_RELOC_X86_64_GOTPLT64
;
2889 case BFD_RELOC_X86_64_PLTOFF64
:
2890 return BFD_RELOC_X86_64_PLTOFF64
;
2892 case BFD_RELOC_X86_64_GOTPC32
:
2893 other
= BFD_RELOC_X86_64_GOTPC64
;
2895 case BFD_RELOC_X86_64_GOTPCREL
:
2896 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2898 case BFD_RELOC_X86_64_TPOFF32
:
2899 other
= BFD_RELOC_X86_64_TPOFF64
;
2901 case BFD_RELOC_X86_64_DTPOFF32
:
2902 other
= BFD_RELOC_X86_64_DTPOFF64
;
2908 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2909 if (other
== BFD_RELOC_SIZE32
)
2912 other
= BFD_RELOC_SIZE64
;
2915 as_bad (_("there are no pc-relative size relocations"));
2921 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2922 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2925 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2927 as_bad (_("unknown relocation (%u)"), other
);
2928 else if (size
!= bfd_get_reloc_size (rel
))
2929 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2930 bfd_get_reloc_size (rel
),
2932 else if (pcrel
&& !rel
->pc_relative
)
2933 as_bad (_("non-pc-relative relocation for pc-relative field"));
2934 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2936 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2938 as_bad (_("relocated field and relocation type differ in signedness"));
2947 as_bad (_("there are no unsigned pc-relative relocations"));
2950 case 1: return BFD_RELOC_8_PCREL
;
2951 case 2: return BFD_RELOC_16_PCREL
;
2952 case 4: return BFD_RELOC_32_PCREL
;
2953 case 8: return BFD_RELOC_64_PCREL
;
2955 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2962 case 4: return BFD_RELOC_X86_64_32S
;
2967 case 1: return BFD_RELOC_8
;
2968 case 2: return BFD_RELOC_16
;
2969 case 4: return BFD_RELOC_32
;
2970 case 8: return BFD_RELOC_64
;
2972 as_bad (_("cannot do %s %u byte relocation"),
2973 sign
> 0 ? "signed" : "unsigned", size
);
2979 /* Here we decide which fixups can be adjusted to make them relative to
2980 the beginning of the section instead of the symbol. Basically we need
2981 to make sure that the dynamic relocations are done correctly, so in
2982 some cases we force the original symbol to be used. */
2985 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2987 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2991 /* Don't adjust pc-relative references to merge sections in 64-bit
2993 if (use_rela_relocations
2994 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2998 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2999 and changed later by validate_fix. */
3000 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3001 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3004 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3005 for size relocations. */
3006 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3007 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3008 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3009 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3010 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3011 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3012 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3013 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3014 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3015 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3016 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3017 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3018 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3019 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3020 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3021 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3022 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3023 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3024 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3025 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3026 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3027 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3028 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3029 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3030 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3031 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3032 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3033 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3034 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3035 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3036 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3037 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3038 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3045 intel_float_operand (const char *mnemonic
)
3047 /* Note that the value returned is meaningful only for opcodes with (memory)
3048 operands, hence the code here is free to improperly handle opcodes that
3049 have no operands (for better performance and smaller code). */
3051 if (mnemonic
[0] != 'f')
3052 return 0; /* non-math */
3054 switch (mnemonic
[1])
3056 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3057 the fs segment override prefix not currently handled because no
3058 call path can make opcodes without operands get here */
3060 return 2 /* integer op */;
3062 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3063 return 3; /* fldcw/fldenv */
3066 if (mnemonic
[2] != 'o' /* fnop */)
3067 return 3; /* non-waiting control op */
3070 if (mnemonic
[2] == 's')
3071 return 3; /* frstor/frstpm */
3074 if (mnemonic
[2] == 'a')
3075 return 3; /* fsave */
3076 if (mnemonic
[2] == 't')
3078 switch (mnemonic
[3])
3080 case 'c': /* fstcw */
3081 case 'd': /* fstdw */
3082 case 'e': /* fstenv */
3083 case 's': /* fsts[gw] */
3089 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3090 return 0; /* fxsave/fxrstor are not really math ops */
3097 /* Build the VEX prefix. */
3100 build_vex_prefix (const insn_template
*t
)
3102 unsigned int register_specifier
;
3103 unsigned int implied_prefix
;
3104 unsigned int vector_length
;
3106 /* Check register specifier. */
3107 if (i
.vex
.register_specifier
)
3109 register_specifier
=
3110 ~register_number (i
.vex
.register_specifier
) & 0xf;
3111 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3114 register_specifier
= 0xf;
3116 /* Use 2-byte VEX prefix by swappping destination and source
3119 && i
.operands
== i
.reg_operands
3120 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3121 && i
.tm
.opcode_modifier
.s
3124 unsigned int xchg
= i
.operands
- 1;
3125 union i386_op temp_op
;
3126 i386_operand_type temp_type
;
3128 temp_type
= i
.types
[xchg
];
3129 i
.types
[xchg
] = i
.types
[0];
3130 i
.types
[0] = temp_type
;
3131 temp_op
= i
.op
[xchg
];
3132 i
.op
[xchg
] = i
.op
[0];
3135 gas_assert (i
.rm
.mode
== 3);
3139 i
.rm
.regmem
= i
.rm
.reg
;
3142 /* Use the next insn. */
3146 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3147 vector_length
= avxscalar
;
3149 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3151 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3156 case DATA_PREFIX_OPCODE
:
3159 case REPE_PREFIX_OPCODE
:
3162 case REPNE_PREFIX_OPCODE
:
3169 /* Use 2-byte VEX prefix if possible. */
3170 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3171 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3172 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3174 /* 2-byte VEX prefix. */
3178 i
.vex
.bytes
[0] = 0xc5;
3180 /* Check the REX.R bit. */
3181 r
= (i
.rex
& REX_R
) ? 0 : 1;
3182 i
.vex
.bytes
[1] = (r
<< 7
3183 | register_specifier
<< 3
3184 | vector_length
<< 2
3189 /* 3-byte VEX prefix. */
3194 switch (i
.tm
.opcode_modifier
.vexopcode
)
3198 i
.vex
.bytes
[0] = 0xc4;
3202 i
.vex
.bytes
[0] = 0xc4;
3206 i
.vex
.bytes
[0] = 0xc4;
3210 i
.vex
.bytes
[0] = 0x8f;
3214 i
.vex
.bytes
[0] = 0x8f;
3218 i
.vex
.bytes
[0] = 0x8f;
3224 /* The high 3 bits of the second VEX byte are 1's compliment
3225 of RXB bits from REX. */
3226 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3228 /* Check the REX.W bit. */
3229 w
= (i
.rex
& REX_W
) ? 1 : 0;
3230 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3233 i
.vex
.bytes
[2] = (w
<< 7
3234 | register_specifier
<< 3
3235 | vector_length
<< 2
3240 /* Build the EVEX prefix. */
3243 build_evex_prefix (void)
3245 unsigned int register_specifier
;
3246 unsigned int implied_prefix
;
3248 rex_byte vrex_used
= 0;
3250 /* Check register specifier. */
3251 if (i
.vex
.register_specifier
)
3253 gas_assert ((i
.vrex
& REX_X
) == 0);
3255 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3256 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3257 register_specifier
+= 8;
3258 /* The upper 16 registers are encoded in the fourth byte of the
3260 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3261 i
.vex
.bytes
[3] = 0x8;
3262 register_specifier
= ~register_specifier
& 0xf;
3266 register_specifier
= 0xf;
3268 /* Encode upper 16 vector index register in the fourth byte of
3270 if (!(i
.vrex
& REX_X
))
3271 i
.vex
.bytes
[3] = 0x8;
3276 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3281 case DATA_PREFIX_OPCODE
:
3284 case REPE_PREFIX_OPCODE
:
3287 case REPNE_PREFIX_OPCODE
:
3294 /* 4 byte EVEX prefix. */
3296 i
.vex
.bytes
[0] = 0x62;
3299 switch (i
.tm
.opcode_modifier
.vexopcode
)
3315 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3317 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3319 /* The fifth bit of the second EVEX byte is 1's compliment of the
3320 REX_R bit in VREX. */
3321 if (!(i
.vrex
& REX_R
))
3322 i
.vex
.bytes
[1] |= 0x10;
3326 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3328 /* When all operands are registers, the REX_X bit in REX is not
3329 used. We reuse it to encode the upper 16 registers, which is
3330 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3331 as 1's compliment. */
3332 if ((i
.vrex
& REX_B
))
3335 i
.vex
.bytes
[1] &= ~0x40;
3339 /* EVEX instructions shouldn't need the REX prefix. */
3340 i
.vrex
&= ~vrex_used
;
3341 gas_assert (i
.vrex
== 0);
3343 /* Check the REX.W bit. */
3344 w
= (i
.rex
& REX_W
) ? 1 : 0;
3345 if (i
.tm
.opcode_modifier
.vexw
)
3347 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3350 /* If w is not set it means we are dealing with WIG instruction. */
3353 if (evexwig
== evexw1
)
3357 /* Encode the U bit. */
3358 implied_prefix
|= 0x4;
3360 /* The third byte of the EVEX prefix. */
3361 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3363 /* The fourth byte of the EVEX prefix. */
3364 /* The zeroing-masking bit. */
3365 if (i
.mask
&& i
.mask
->zeroing
)
3366 i
.vex
.bytes
[3] |= 0x80;
3368 /* Don't always set the broadcast bit if there is no RC. */
3371 /* Encode the vector length. */
3372 unsigned int vec_length
;
3374 switch (i
.tm
.opcode_modifier
.evex
)
3376 case EVEXLIG
: /* LL' is ignored */
3377 vec_length
= evexlig
<< 5;
3380 vec_length
= 0 << 5;
3383 vec_length
= 1 << 5;
3386 vec_length
= 2 << 5;
3392 i
.vex
.bytes
[3] |= vec_length
;
3393 /* Encode the broadcast bit. */
3395 i
.vex
.bytes
[3] |= 0x10;
3399 if (i
.rounding
->type
!= saeonly
)
3400 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3402 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3405 if (i
.mask
&& i
.mask
->mask
)
3406 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3410 process_immext (void)
3414 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3417 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3418 with an opcode suffix which is coded in the same place as an
3419 8-bit immediate field would be.
3420 Here we check those operands and remove them afterwards. */
3423 for (x
= 0; x
< i
.operands
; x
++)
3424 if (register_number (i
.op
[x
].regs
) != x
)
3425 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3426 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3432 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3434 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3435 suffix which is coded in the same place as an 8-bit immediate
3437 Here we check those operands and remove them afterwards. */
3440 if (i
.operands
!= 3)
3443 for (x
= 0; x
< 2; x
++)
3444 if (register_number (i
.op
[x
].regs
) != x
)
3445 goto bad_register_operand
;
3447 /* Check for third operand for mwaitx/monitorx insn. */
3448 if (register_number (i
.op
[x
].regs
)
3449 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3451 bad_register_operand
:
3452 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3453 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3460 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3461 which is coded in the same place as an 8-bit immediate field
3462 would be. Here we fake an 8-bit immediate operand from the
3463 opcode suffix stored in tm.extension_opcode.
3465 AVX instructions also use this encoding, for some of
3466 3 argument instructions. */
3468 gas_assert (i
.imm_operands
<= 1
3470 || ((i
.tm
.opcode_modifier
.vex
3471 || i
.tm
.opcode_modifier
.evex
)
3472 && i
.operands
<= 4)));
3474 exp
= &im_expressions
[i
.imm_operands
++];
3475 i
.op
[i
.operands
].imms
= exp
;
3476 i
.types
[i
.operands
] = imm8
;
3478 exp
->X_op
= O_constant
;
3479 exp
->X_add_number
= i
.tm
.extension_opcode
;
3480 i
.tm
.extension_opcode
= None
;
3487 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3492 as_bad (_("invalid instruction `%s' after `%s'"),
3493 i
.tm
.name
, i
.hle_prefix
);
3496 if (i
.prefix
[LOCK_PREFIX
])
3498 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3502 case HLEPrefixRelease
:
3503 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3505 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3509 if (i
.mem_operands
== 0
3510 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3512 as_bad (_("memory destination needed for instruction `%s'"
3513 " after `xrelease'"), i
.tm
.name
);
3520 /* This is the guts of the machine-dependent assembler. LINE points to a
3521 machine dependent instruction. This function is supposed to emit
3522 the frags/bytes it assembles to. */
3525 md_assemble (char *line
)
3528 char mnemonic
[MAX_MNEM_SIZE
];
3529 const insn_template
*t
;
3531 /* Initialize globals. */
3532 memset (&i
, '\0', sizeof (i
));
3533 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3534 i
.reloc
[j
] = NO_RELOC
;
3535 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3536 memset (im_expressions
, '\0', sizeof (im_expressions
));
3537 save_stack_p
= save_stack
;
3539 /* First parse an instruction mnemonic & call i386_operand for the operands.
3540 We assume that the scrubber has arranged it so that line[0] is the valid
3541 start of a (possibly prefixed) mnemonic. */
3543 line
= parse_insn (line
, mnemonic
);
3547 line
= parse_operands (line
, mnemonic
);
3552 /* Now we've parsed the mnemonic into a set of templates, and have the
3553 operands at hand. */
3555 /* All intel opcodes have reversed operands except for "bound" and
3556 "enter". We also don't reverse intersegment "jmp" and "call"
3557 instructions with 2 immediate operands so that the immediate segment
3558 precedes the offset, as it does when in AT&T mode. */
3561 && (strcmp (mnemonic
, "bound") != 0)
3562 && (strcmp (mnemonic
, "invlpga") != 0)
3563 && !(operand_type_check (i
.types
[0], imm
)
3564 && operand_type_check (i
.types
[1], imm
)))
3567 /* The order of the immediates should be reversed
3568 for 2 immediates extrq and insertq instructions */
3569 if (i
.imm_operands
== 2
3570 && (strcmp (mnemonic
, "extrq") == 0
3571 || strcmp (mnemonic
, "insertq") == 0))
3572 swap_2_operands (0, 1);
3577 /* Don't optimize displacement for movabs since it only takes 64bit
3580 && i
.disp_encoding
!= disp_encoding_32bit
3581 && (flag_code
!= CODE_64BIT
3582 || strcmp (mnemonic
, "movabs") != 0))
3585 /* Next, we find a template that matches the given insn,
3586 making sure the overlap of the given operands types is consistent
3587 with the template operand types. */
3589 if (!(t
= match_template ()))
3592 if (sse_check
!= check_none
3593 && !i
.tm
.opcode_modifier
.noavx
3594 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3595 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3596 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3597 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3598 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3599 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3601 (sse_check
== check_warning
3603 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3606 /* Zap movzx and movsx suffix. The suffix has been set from
3607 "word ptr" or "byte ptr" on the source operand in Intel syntax
3608 or extracted from mnemonic in AT&T syntax. But we'll use
3609 the destination register to choose the suffix for encoding. */
3610 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3612 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3613 there is no suffix, the default will be byte extension. */
3614 if (i
.reg_operands
!= 2
3617 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3622 if (i
.tm
.opcode_modifier
.fwait
)
3623 if (!add_prefix (FWAIT_OPCODE
))
3626 /* Check if REP prefix is OK. */
3627 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3629 as_bad (_("invalid instruction `%s' after `%s'"),
3630 i
.tm
.name
, i
.rep_prefix
);
3634 /* Check for lock without a lockable instruction. Destination operand
3635 must be memory unless it is xchg (0x86). */
3636 if (i
.prefix
[LOCK_PREFIX
]
3637 && (!i
.tm
.opcode_modifier
.islockable
3638 || i
.mem_operands
== 0
3639 || (i
.tm
.base_opcode
!= 0x86
3640 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3642 as_bad (_("expecting lockable instruction after `lock'"));
3646 /* Check if HLE prefix is OK. */
3647 if (i
.hle_prefix
&& !check_hle ())
3650 /* Check BND prefix. */
3651 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3652 as_bad (_("expecting valid branch instruction after `bnd'"));
3654 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3655 && flag_code
== CODE_64BIT
3656 && i
.prefix
[ADDR_PREFIX
])
3657 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3659 /* Insert BND prefix. */
3661 && i
.tm
.opcode_modifier
.bndprefixok
3662 && !i
.prefix
[BND_PREFIX
])
3663 add_prefix (BND_PREFIX_OPCODE
);
3665 /* Check string instruction segment overrides. */
3666 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3668 if (!check_string ())
3670 i
.disp_operands
= 0;
3673 if (!process_suffix ())
3676 /* Update operand types. */
3677 for (j
= 0; j
< i
.operands
; j
++)
3678 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3680 /* Make still unresolved immediate matches conform to size of immediate
3681 given in i.suffix. */
3682 if (!finalize_imm ())
3685 if (i
.types
[0].bitfield
.imm1
)
3686 i
.imm_operands
= 0; /* kludge for shift insns. */
3688 /* We only need to check those implicit registers for instructions
3689 with 3 operands or less. */
3690 if (i
.operands
<= 3)
3691 for (j
= 0; j
< i
.operands
; j
++)
3692 if (i
.types
[j
].bitfield
.inoutportreg
3693 || i
.types
[j
].bitfield
.shiftcount
3694 || i
.types
[j
].bitfield
.acc
3695 || i
.types
[j
].bitfield
.floatacc
)
3698 /* ImmExt should be processed after SSE2AVX. */
3699 if (!i
.tm
.opcode_modifier
.sse2avx
3700 && i
.tm
.opcode_modifier
.immext
)
3703 /* For insns with operands there are more diddles to do to the opcode. */
3706 if (!process_operands ())
3709 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3711 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3712 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3715 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3717 if (flag_code
== CODE_16BIT
)
3719 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3724 if (i
.tm
.opcode_modifier
.vex
)
3725 build_vex_prefix (t
);
3727 build_evex_prefix ();
3730 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3731 instructions may define INT_OPCODE as well, so avoid this corner
3732 case for those instructions that use MODRM. */
3733 if (i
.tm
.base_opcode
== INT_OPCODE
3734 && !i
.tm
.opcode_modifier
.modrm
3735 && i
.op
[0].imms
->X_add_number
== 3)
3737 i
.tm
.base_opcode
= INT3_OPCODE
;
3741 if ((i
.tm
.opcode_modifier
.jump
3742 || i
.tm
.opcode_modifier
.jumpbyte
3743 || i
.tm
.opcode_modifier
.jumpdword
)
3744 && i
.op
[0].disps
->X_op
== O_constant
)
3746 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3747 the absolute address given by the constant. Since ix86 jumps and
3748 calls are pc relative, we need to generate a reloc. */
3749 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3750 i
.op
[0].disps
->X_op
= O_symbol
;
3753 if (i
.tm
.opcode_modifier
.rex64
)
3756 /* For 8 bit registers we need an empty rex prefix. Also if the
3757 instruction already has a prefix, we need to convert old
3758 registers to new ones. */
3760 if ((i
.types
[0].bitfield
.reg8
3761 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3762 || (i
.types
[1].bitfield
.reg8
3763 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3764 || ((i
.types
[0].bitfield
.reg8
3765 || i
.types
[1].bitfield
.reg8
)
3770 i
.rex
|= REX_OPCODE
;
3771 for (x
= 0; x
< 2; x
++)
3773 /* Look for 8 bit operand that uses old registers. */
3774 if (i
.types
[x
].bitfield
.reg8
3775 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3777 /* In case it is "hi" register, give up. */
3778 if (i
.op
[x
].regs
->reg_num
> 3)
3779 as_bad (_("can't encode register '%s%s' in an "
3780 "instruction requiring REX prefix."),
3781 register_prefix
, i
.op
[x
].regs
->reg_name
);
3783 /* Otherwise it is equivalent to the extended register.
3784 Since the encoding doesn't change this is merely
3785 cosmetic cleanup for debug output. */
3787 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3793 add_prefix (REX_OPCODE
| i
.rex
);
3795 /* We are ready to output the insn. */
3800 parse_insn (char *line
, char *mnemonic
)
3803 char *token_start
= l
;
3806 const insn_template
*t
;
3812 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3817 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3819 as_bad (_("no such instruction: `%s'"), token_start
);
3824 if (!is_space_char (*l
)
3825 && *l
!= END_OF_INSN
3827 || (*l
!= PREFIX_SEPARATOR
3830 as_bad (_("invalid character %s in mnemonic"),
3831 output_invalid (*l
));
3834 if (token_start
== l
)
3836 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3837 as_bad (_("expecting prefix; got nothing"));
3839 as_bad (_("expecting mnemonic; got nothing"));
3843 /* Look up instruction (or prefix) via hash table. */
3844 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3846 if (*l
!= END_OF_INSN
3847 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3848 && current_templates
3849 && current_templates
->start
->opcode_modifier
.isprefix
)
3851 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3853 as_bad ((flag_code
!= CODE_64BIT
3854 ? _("`%s' is only supported in 64-bit mode")
3855 : _("`%s' is not supported in 64-bit mode")),
3856 current_templates
->start
->name
);
3859 /* If we are in 16-bit mode, do not allow addr16 or data16.
3860 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3861 if ((current_templates
->start
->opcode_modifier
.size16
3862 || current_templates
->start
->opcode_modifier
.size32
)
3863 && flag_code
!= CODE_64BIT
3864 && (current_templates
->start
->opcode_modifier
.size32
3865 ^ (flag_code
== CODE_16BIT
)))
3867 as_bad (_("redundant %s prefix"),
3868 current_templates
->start
->name
);
3871 /* Add prefix, checking for repeated prefixes. */
3872 switch (add_prefix (current_templates
->start
->base_opcode
))
3877 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3878 i
.hle_prefix
= current_templates
->start
->name
;
3879 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3880 i
.bnd_prefix
= current_templates
->start
->name
;
3882 i
.rep_prefix
= current_templates
->start
->name
;
3887 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3894 if (!current_templates
)
3896 /* Check if we should swap operand or force 32bit displacement in
3898 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3900 else if (mnem_p
- 3 == dot_p
3903 i
.disp_encoding
= disp_encoding_8bit
;
3904 else if (mnem_p
- 4 == dot_p
3908 i
.disp_encoding
= disp_encoding_32bit
;
3913 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3916 if (!current_templates
)
3919 /* See if we can get a match by trimming off a suffix. */
3922 case WORD_MNEM_SUFFIX
:
3923 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3924 i
.suffix
= SHORT_MNEM_SUFFIX
;
3926 case BYTE_MNEM_SUFFIX
:
3927 case QWORD_MNEM_SUFFIX
:
3928 i
.suffix
= mnem_p
[-1];
3930 current_templates
= (const templates
*) hash_find (op_hash
,
3933 case SHORT_MNEM_SUFFIX
:
3934 case LONG_MNEM_SUFFIX
:
3937 i
.suffix
= mnem_p
[-1];
3939 current_templates
= (const templates
*) hash_find (op_hash
,
3948 if (intel_float_operand (mnemonic
) == 1)
3949 i
.suffix
= SHORT_MNEM_SUFFIX
;
3951 i
.suffix
= LONG_MNEM_SUFFIX
;
3953 current_templates
= (const templates
*) hash_find (op_hash
,
3958 if (!current_templates
)
3960 as_bad (_("no such instruction: `%s'"), token_start
);
3965 if (current_templates
->start
->opcode_modifier
.jump
3966 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3968 /* Check for a branch hint. We allow ",pt" and ",pn" for
3969 predict taken and predict not taken respectively.
3970 I'm not sure that branch hints actually do anything on loop
3971 and jcxz insns (JumpByte) for current Pentium4 chips. They
3972 may work in the future and it doesn't hurt to accept them
3974 if (l
[0] == ',' && l
[1] == 'p')
3978 if (!add_prefix (DS_PREFIX_OPCODE
))
3982 else if (l
[2] == 'n')
3984 if (!add_prefix (CS_PREFIX_OPCODE
))
3990 /* Any other comma loses. */
3993 as_bad (_("invalid character %s in mnemonic"),
3994 output_invalid (*l
));
3998 /* Check if instruction is supported on specified architecture. */
4000 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4002 supported
|= cpu_flags_match (t
);
4003 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4007 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4009 as_bad (flag_code
== CODE_64BIT
4010 ? _("`%s' is not supported in 64-bit mode")
4011 : _("`%s' is only supported in 64-bit mode"),
4012 current_templates
->start
->name
);
4015 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
4017 as_bad (_("`%s' is not supported on `%s%s'"),
4018 current_templates
->start
->name
,
4019 cpu_arch_name
? cpu_arch_name
: default_arch
,
4020 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4025 if (!cpu_arch_flags
.bitfield
.cpui386
4026 && (flag_code
!= CODE_16BIT
))
4028 as_warn (_("use .code16 to ensure correct addressing mode"));
4035 parse_operands (char *l
, const char *mnemonic
)
4039 /* 1 if operand is pending after ','. */
4040 unsigned int expecting_operand
= 0;
4042 /* Non-zero if operand parens not balanced. */
4043 unsigned int paren_not_balanced
;
4045 while (*l
!= END_OF_INSN
)
4047 /* Skip optional white space before operand. */
4048 if (is_space_char (*l
))
4050 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4052 as_bad (_("invalid character %s before operand %d"),
4053 output_invalid (*l
),
4057 token_start
= l
; /* After white space. */
4058 paren_not_balanced
= 0;
4059 while (paren_not_balanced
|| *l
!= ',')
4061 if (*l
== END_OF_INSN
)
4063 if (paren_not_balanced
)
4066 as_bad (_("unbalanced parenthesis in operand %d."),
4069 as_bad (_("unbalanced brackets in operand %d."),
4074 break; /* we are done */
4076 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4078 as_bad (_("invalid character %s in operand %d"),
4079 output_invalid (*l
),
4086 ++paren_not_balanced
;
4088 --paren_not_balanced
;
4093 ++paren_not_balanced
;
4095 --paren_not_balanced
;
4099 if (l
!= token_start
)
4100 { /* Yes, we've read in another operand. */
4101 unsigned int operand_ok
;
4102 this_operand
= i
.operands
++;
4103 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4104 if (i
.operands
> MAX_OPERANDS
)
4106 as_bad (_("spurious operands; (%d operands/instruction max)"),
4110 /* Now parse operand adding info to 'i' as we go along. */
4111 END_STRING_AND_SAVE (l
);
4115 i386_intel_operand (token_start
,
4116 intel_float_operand (mnemonic
));
4118 operand_ok
= i386_att_operand (token_start
);
4120 RESTORE_END_STRING (l
);
4126 if (expecting_operand
)
4128 expecting_operand_after_comma
:
4129 as_bad (_("expecting operand after ','; got nothing"));
4134 as_bad (_("expecting operand before ','; got nothing"));
4139 /* Now *l must be either ',' or END_OF_INSN. */
4142 if (*++l
== END_OF_INSN
)
4144 /* Just skip it, if it's \n complain. */
4145 goto expecting_operand_after_comma
;
4147 expecting_operand
= 1;
4154 swap_2_operands (int xchg1
, int xchg2
)
4156 union i386_op temp_op
;
4157 i386_operand_type temp_type
;
4158 enum bfd_reloc_code_real temp_reloc
;
4160 temp_type
= i
.types
[xchg2
];
4161 i
.types
[xchg2
] = i
.types
[xchg1
];
4162 i
.types
[xchg1
] = temp_type
;
4163 temp_op
= i
.op
[xchg2
];
4164 i
.op
[xchg2
] = i
.op
[xchg1
];
4165 i
.op
[xchg1
] = temp_op
;
4166 temp_reloc
= i
.reloc
[xchg2
];
4167 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4168 i
.reloc
[xchg1
] = temp_reloc
;
4172 if (i
.mask
->operand
== xchg1
)
4173 i
.mask
->operand
= xchg2
;
4174 else if (i
.mask
->operand
== xchg2
)
4175 i
.mask
->operand
= xchg1
;
4179 if (i
.broadcast
->operand
== xchg1
)
4180 i
.broadcast
->operand
= xchg2
;
4181 else if (i
.broadcast
->operand
== xchg2
)
4182 i
.broadcast
->operand
= xchg1
;
4186 if (i
.rounding
->operand
== xchg1
)
4187 i
.rounding
->operand
= xchg2
;
4188 else if (i
.rounding
->operand
== xchg2
)
4189 i
.rounding
->operand
= xchg1
;
4194 swap_operands (void)
4200 swap_2_operands (1, i
.operands
- 2);
4203 swap_2_operands (0, i
.operands
- 1);
4209 if (i
.mem_operands
== 2)
4211 const seg_entry
*temp_seg
;
4212 temp_seg
= i
.seg
[0];
4213 i
.seg
[0] = i
.seg
[1];
4214 i
.seg
[1] = temp_seg
;
4218 /* Try to ensure constant immediates are represented in the smallest
4223 char guess_suffix
= 0;
4227 guess_suffix
= i
.suffix
;
4228 else if (i
.reg_operands
)
4230 /* Figure out a suffix from the last register operand specified.
4231 We can't do this properly yet, ie. excluding InOutPortReg,
4232 but the following works for instructions with immediates.
4233 In any case, we can't set i.suffix yet. */
4234 for (op
= i
.operands
; --op
>= 0;)
4235 if (i
.types
[op
].bitfield
.reg8
)
4237 guess_suffix
= BYTE_MNEM_SUFFIX
;
4240 else if (i
.types
[op
].bitfield
.reg16
)
4242 guess_suffix
= WORD_MNEM_SUFFIX
;
4245 else if (i
.types
[op
].bitfield
.reg32
)
4247 guess_suffix
= LONG_MNEM_SUFFIX
;
4250 else if (i
.types
[op
].bitfield
.reg64
)
4252 guess_suffix
= QWORD_MNEM_SUFFIX
;
4256 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4257 guess_suffix
= WORD_MNEM_SUFFIX
;
4259 for (op
= i
.operands
; --op
>= 0;)
4260 if (operand_type_check (i
.types
[op
], imm
))
4262 switch (i
.op
[op
].imms
->X_op
)
4265 /* If a suffix is given, this operand may be shortened. */
4266 switch (guess_suffix
)
4268 case LONG_MNEM_SUFFIX
:
4269 i
.types
[op
].bitfield
.imm32
= 1;
4270 i
.types
[op
].bitfield
.imm64
= 1;
4272 case WORD_MNEM_SUFFIX
:
4273 i
.types
[op
].bitfield
.imm16
= 1;
4274 i
.types
[op
].bitfield
.imm32
= 1;
4275 i
.types
[op
].bitfield
.imm32s
= 1;
4276 i
.types
[op
].bitfield
.imm64
= 1;
4278 case BYTE_MNEM_SUFFIX
:
4279 i
.types
[op
].bitfield
.imm8
= 1;
4280 i
.types
[op
].bitfield
.imm8s
= 1;
4281 i
.types
[op
].bitfield
.imm16
= 1;
4282 i
.types
[op
].bitfield
.imm32
= 1;
4283 i
.types
[op
].bitfield
.imm32s
= 1;
4284 i
.types
[op
].bitfield
.imm64
= 1;
4288 /* If this operand is at most 16 bits, convert it
4289 to a signed 16 bit number before trying to see
4290 whether it will fit in an even smaller size.
4291 This allows a 16-bit operand such as $0xffe0 to
4292 be recognised as within Imm8S range. */
4293 if ((i
.types
[op
].bitfield
.imm16
)
4294 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4296 i
.op
[op
].imms
->X_add_number
=
4297 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4300 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4301 if ((i
.types
[op
].bitfield
.imm32
)
4302 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4305 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4306 ^ ((offsetT
) 1 << 31))
4307 - ((offsetT
) 1 << 31));
4311 = operand_type_or (i
.types
[op
],
4312 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4314 /* We must avoid matching of Imm32 templates when 64bit
4315 only immediate is available. */
4316 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4317 i
.types
[op
].bitfield
.imm32
= 0;
4324 /* Symbols and expressions. */
4326 /* Convert symbolic operand to proper sizes for matching, but don't
4327 prevent matching a set of insns that only supports sizes other
4328 than those matching the insn suffix. */
4330 i386_operand_type mask
, allowed
;
4331 const insn_template
*t
;
4333 operand_type_set (&mask
, 0);
4334 operand_type_set (&allowed
, 0);
4336 for (t
= current_templates
->start
;
4337 t
< current_templates
->end
;
4339 allowed
= operand_type_or (allowed
,
4340 t
->operand_types
[op
]);
4341 switch (guess_suffix
)
4343 case QWORD_MNEM_SUFFIX
:
4344 mask
.bitfield
.imm64
= 1;
4345 mask
.bitfield
.imm32s
= 1;
4347 case LONG_MNEM_SUFFIX
:
4348 mask
.bitfield
.imm32
= 1;
4350 case WORD_MNEM_SUFFIX
:
4351 mask
.bitfield
.imm16
= 1;
4353 case BYTE_MNEM_SUFFIX
:
4354 mask
.bitfield
.imm8
= 1;
4359 allowed
= operand_type_and (mask
, allowed
);
4360 if (!operand_type_all_zero (&allowed
))
4361 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4368 /* Try to use the smallest displacement type too. */
4370 optimize_disp (void)
4374 for (op
= i
.operands
; --op
>= 0;)
4375 if (operand_type_check (i
.types
[op
], disp
))
4377 if (i
.op
[op
].disps
->X_op
== O_constant
)
4379 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4381 if (i
.types
[op
].bitfield
.disp16
4382 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4384 /* If this operand is at most 16 bits, convert
4385 to a signed 16 bit number and don't use 64bit
4387 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4388 i
.types
[op
].bitfield
.disp64
= 0;
4391 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4392 if (i
.types
[op
].bitfield
.disp32
4393 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4395 /* If this operand is at most 32 bits, convert
4396 to a signed 32 bit number and don't use 64bit
4398 op_disp
&= (((offsetT
) 2 << 31) - 1);
4399 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4400 i
.types
[op
].bitfield
.disp64
= 0;
4403 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4405 i
.types
[op
].bitfield
.disp8
= 0;
4406 i
.types
[op
].bitfield
.disp16
= 0;
4407 i
.types
[op
].bitfield
.disp32
= 0;
4408 i
.types
[op
].bitfield
.disp32s
= 0;
4409 i
.types
[op
].bitfield
.disp64
= 0;
4413 else if (flag_code
== CODE_64BIT
)
4415 if (fits_in_signed_long (op_disp
))
4417 i
.types
[op
].bitfield
.disp64
= 0;
4418 i
.types
[op
].bitfield
.disp32s
= 1;
4420 if (i
.prefix
[ADDR_PREFIX
]
4421 && fits_in_unsigned_long (op_disp
))
4422 i
.types
[op
].bitfield
.disp32
= 1;
4424 if ((i
.types
[op
].bitfield
.disp32
4425 || i
.types
[op
].bitfield
.disp32s
4426 || i
.types
[op
].bitfield
.disp16
)
4427 && fits_in_signed_byte (op_disp
))
4428 i
.types
[op
].bitfield
.disp8
= 1;
4430 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4431 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4433 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4434 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4435 i
.types
[op
].bitfield
.disp8
= 0;
4436 i
.types
[op
].bitfield
.disp16
= 0;
4437 i
.types
[op
].bitfield
.disp32
= 0;
4438 i
.types
[op
].bitfield
.disp32s
= 0;
4439 i
.types
[op
].bitfield
.disp64
= 0;
4442 /* We only support 64bit displacement on constants. */
4443 i
.types
[op
].bitfield
.disp64
= 0;
4447 /* Check if operands are valid for the instruction. */
4450 check_VecOperands (const insn_template
*t
)
4454 /* Without VSIB byte, we can't have a vector register for index. */
4455 if (!t
->opcode_modifier
.vecsib
4457 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4458 || i
.index_reg
->reg_type
.bitfield
.regymm
4459 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4461 i
.error
= unsupported_vector_index_register
;
4465 /* Check if default mask is allowed. */
4466 if (t
->opcode_modifier
.nodefmask
4467 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4469 i
.error
= no_default_mask
;
4473 /* For VSIB byte, we need a vector register for index, and all vector
4474 registers must be distinct. */
4475 if (t
->opcode_modifier
.vecsib
)
4478 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4479 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4480 || (t
->opcode_modifier
.vecsib
== VecSIB256
4481 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4482 || (t
->opcode_modifier
.vecsib
== VecSIB512
4483 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4485 i
.error
= invalid_vsib_address
;
4489 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4490 if (i
.reg_operands
== 2 && !i
.mask
)
4492 gas_assert (i
.types
[0].bitfield
.regxmm
4493 || i
.types
[0].bitfield
.regymm
);
4494 gas_assert (i
.types
[2].bitfield
.regxmm
4495 || i
.types
[2].bitfield
.regymm
);
4496 if (operand_check
== check_none
)
4498 if (register_number (i
.op
[0].regs
)
4499 != register_number (i
.index_reg
)
4500 && register_number (i
.op
[2].regs
)
4501 != register_number (i
.index_reg
)
4502 && register_number (i
.op
[0].regs
)
4503 != register_number (i
.op
[2].regs
))
4505 if (operand_check
== check_error
)
4507 i
.error
= invalid_vector_register_set
;
4510 as_warn (_("mask, index, and destination registers should be distinct"));
4512 else if (i
.reg_operands
== 1 && i
.mask
)
4514 if ((i
.types
[1].bitfield
.regymm
4515 || i
.types
[1].bitfield
.regzmm
)
4516 && (register_number (i
.op
[1].regs
)
4517 == register_number (i
.index_reg
)))
4519 if (operand_check
== check_error
)
4521 i
.error
= invalid_vector_register_set
;
4524 if (operand_check
!= check_none
)
4525 as_warn (_("index and destination registers should be distinct"));
4530 /* Check if broadcast is supported by the instruction and is applied
4531 to the memory operand. */
4534 int broadcasted_opnd_size
;
4536 /* Check if specified broadcast is supported in this instruction,
4537 and it's applied to memory operand of DWORD or QWORD type,
4538 depending on VecESize. */
4539 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4540 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4541 || (t
->opcode_modifier
.vecesize
== 0
4542 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4543 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4544 || (t
->opcode_modifier
.vecesize
== 1
4545 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4546 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4549 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4550 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4551 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4552 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4553 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4554 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4555 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4556 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4557 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4561 if ((broadcasted_opnd_size
== 256
4562 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4563 || (broadcasted_opnd_size
== 512
4564 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4567 i
.error
= unsupported_broadcast
;
4571 /* If broadcast is supported in this instruction, we need to check if
4572 operand of one-element size isn't specified without broadcast. */
4573 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4575 /* Find memory operand. */
4576 for (op
= 0; op
< i
.operands
; op
++)
4577 if (operand_type_check (i
.types
[op
], anymem
))
4579 gas_assert (op
< i
.operands
);
4580 /* Check size of the memory operand. */
4581 if ((t
->opcode_modifier
.vecesize
== 0
4582 && i
.types
[op
].bitfield
.dword
)
4583 || (t
->opcode_modifier
.vecesize
== 1
4584 && i
.types
[op
].bitfield
.qword
))
4586 i
.error
= broadcast_needed
;
4591 /* Check if requested masking is supported. */
4593 && (!t
->opcode_modifier
.masking
4595 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4597 i
.error
= unsupported_masking
;
4601 /* Check if masking is applied to dest operand. */
4602 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4604 i
.error
= mask_not_on_destination
;
4611 if ((i
.rounding
->type
!= saeonly
4612 && !t
->opcode_modifier
.staticrounding
)
4613 || (i
.rounding
->type
== saeonly
4614 && (t
->opcode_modifier
.staticrounding
4615 || !t
->opcode_modifier
.sae
)))
4617 i
.error
= unsupported_rc_sae
;
4620 /* If the instruction has several immediate operands and one of
4621 them is rounding, the rounding operand should be the last
4622 immediate operand. */
4623 if (i
.imm_operands
> 1
4624 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4626 i
.error
= rc_sae_operand_not_last_imm
;
4631 /* Check vector Disp8 operand. */
4632 if (t
->opcode_modifier
.disp8memshift
)
4635 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4637 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4639 for (op
= 0; op
< i
.operands
; op
++)
4640 if (operand_type_check (i
.types
[op
], disp
)
4641 && i
.op
[op
].disps
->X_op
== O_constant
)
4643 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4645 = (i
.disp_encoding
!= disp_encoding_32bit
4646 && fits_in_vec_disp8 (value
));
4647 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4650 i
.types
[op
].bitfield
.vec_disp8
= 1;
4653 /* Vector insn can only have Vec_Disp8/Disp32 in
4654 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4656 i
.types
[op
].bitfield
.disp8
= 0;
4657 if (flag_code
!= CODE_16BIT
)
4658 i
.types
[op
].bitfield
.disp16
= 0;
4661 else if (flag_code
!= CODE_16BIT
)
4663 /* One form of this instruction supports vector Disp8.
4664 Try vector Disp8 if we need to use Disp32. */
4665 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4667 i
.error
= try_vector_disp8
;
4679 /* Check if operands are valid for the instruction. Update VEX
4683 VEX_check_operands (const insn_template
*t
)
4685 /* VREX is only valid with EVEX prefix. */
4686 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4688 i
.error
= invalid_register_operand
;
4692 if (!t
->opcode_modifier
.vex
)
4695 /* Only check VEX_Imm4, which must be the first operand. */
4696 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4698 if (i
.op
[0].imms
->X_op
!= O_constant
4699 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4705 /* Turn off Imm8 so that update_imm won't complain. */
4706 i
.types
[0] = vec_imm4
;
4712 static const insn_template
*
4713 match_template (void)
4715 /* Points to template once we've found it. */
4716 const insn_template
*t
;
4717 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4718 i386_operand_type overlap4
;
4719 unsigned int found_reverse_match
;
4720 i386_opcode_modifier suffix_check
;
4721 i386_operand_type operand_types
[MAX_OPERANDS
];
4722 int addr_prefix_disp
;
4724 unsigned int found_cpu_match
;
4725 unsigned int check_register
;
4726 enum i386_error specific_error
= 0;
4728 #if MAX_OPERANDS != 5
4729 # error "MAX_OPERANDS must be 5."
4732 found_reverse_match
= 0;
4733 addr_prefix_disp
= -1;
4735 memset (&suffix_check
, 0, sizeof (suffix_check
));
4736 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4737 suffix_check
.no_bsuf
= 1;
4738 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4739 suffix_check
.no_wsuf
= 1;
4740 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4741 suffix_check
.no_ssuf
= 1;
4742 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4743 suffix_check
.no_lsuf
= 1;
4744 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4745 suffix_check
.no_qsuf
= 1;
4746 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4747 suffix_check
.no_ldsuf
= 1;
4749 /* Must have right number of operands. */
4750 i
.error
= number_of_operands_mismatch
;
4752 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4754 addr_prefix_disp
= -1;
4756 if (i
.operands
!= t
->operands
)
4759 /* Check processor support. */
4760 i
.error
= unsupported
;
4761 found_cpu_match
= (cpu_flags_match (t
)
4762 == CPU_FLAGS_PERFECT_MATCH
);
4763 if (!found_cpu_match
)
4766 /* Check old gcc support. */
4767 i
.error
= old_gcc_only
;
4768 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4771 /* Check AT&T mnemonic. */
4772 i
.error
= unsupported_with_intel_mnemonic
;
4773 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4776 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
4777 i
.error
= unsupported_syntax
;
4778 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4779 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
4780 || (intel64
&& t
->opcode_modifier
.amd64
)
4781 || (!intel64
&& t
->opcode_modifier
.intel64
))
4784 /* Check the suffix, except for some instructions in intel mode. */
4785 i
.error
= invalid_instruction_suffix
;
4786 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4787 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4788 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4789 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4790 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4791 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4792 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4795 if (!operand_size_match (t
))
4798 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4799 operand_types
[j
] = t
->operand_types
[j
];
4801 /* In general, don't allow 64-bit operands in 32-bit mode. */
4802 if (i
.suffix
== QWORD_MNEM_SUFFIX
4803 && flag_code
!= CODE_64BIT
4805 ? (!t
->opcode_modifier
.ignoresize
4806 && !intel_float_operand (t
->name
))
4807 : intel_float_operand (t
->name
) != 2)
4808 && ((!operand_types
[0].bitfield
.regmmx
4809 && !operand_types
[0].bitfield
.regxmm
4810 && !operand_types
[0].bitfield
.regymm
4811 && !operand_types
[0].bitfield
.regzmm
)
4812 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4813 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4814 && operand_types
[t
->operands
> 1].bitfield
.regymm
4815 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4816 && (t
->base_opcode
!= 0x0fc7
4817 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4820 /* In general, don't allow 32-bit operands on pre-386. */
4821 else if (i
.suffix
== LONG_MNEM_SUFFIX
4822 && !cpu_arch_flags
.bitfield
.cpui386
4824 ? (!t
->opcode_modifier
.ignoresize
4825 && !intel_float_operand (t
->name
))
4826 : intel_float_operand (t
->name
) != 2)
4827 && ((!operand_types
[0].bitfield
.regmmx
4828 && !operand_types
[0].bitfield
.regxmm
)
4829 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4830 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4833 /* Do not verify operands when there are none. */
4837 /* We've found a match; break out of loop. */
4841 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4842 into Disp32/Disp16/Disp32 operand. */
4843 if (i
.prefix
[ADDR_PREFIX
] != 0)
4845 /* There should be only one Disp operand. */
4849 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4851 if (operand_types
[j
].bitfield
.disp16
)
4853 addr_prefix_disp
= j
;
4854 operand_types
[j
].bitfield
.disp32
= 1;
4855 operand_types
[j
].bitfield
.disp16
= 0;
4861 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4863 if (operand_types
[j
].bitfield
.disp32
)
4865 addr_prefix_disp
= j
;
4866 operand_types
[j
].bitfield
.disp32
= 0;
4867 operand_types
[j
].bitfield
.disp16
= 1;
4873 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4875 if (operand_types
[j
].bitfield
.disp64
)
4877 addr_prefix_disp
= j
;
4878 operand_types
[j
].bitfield
.disp64
= 0;
4879 operand_types
[j
].bitfield
.disp32
= 1;
4887 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4888 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
4891 /* We check register size if needed. */
4892 check_register
= t
->opcode_modifier
.checkregsize
;
4893 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4894 switch (t
->operands
)
4897 if (!operand_type_match (overlap0
, i
.types
[0]))
4901 /* xchg %eax, %eax is a special case. It is an aliase for nop
4902 only in 32bit mode and we can use opcode 0x90. In 64bit
4903 mode, we can't use 0x90 for xchg %eax, %eax since it should
4904 zero-extend %eax to %rax. */
4905 if (flag_code
== CODE_64BIT
4906 && t
->base_opcode
== 0x90
4907 && operand_type_equal (&i
.types
[0], &acc32
)
4908 && operand_type_equal (&i
.types
[1], &acc32
))
4912 /* If we swap operand in encoding, we either match
4913 the next one or reverse direction of operands. */
4914 if (t
->opcode_modifier
.s
)
4916 else if (t
->opcode_modifier
.d
)
4921 /* If we swap operand in encoding, we match the next one. */
4922 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4926 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4927 if (!operand_type_match (overlap0
, i
.types
[0])
4928 || !operand_type_match (overlap1
, i
.types
[1])
4930 && !operand_type_register_match (overlap0
, i
.types
[0],
4932 overlap1
, i
.types
[1],
4935 /* Check if other direction is valid ... */
4936 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4940 /* Try reversing direction of operands. */
4941 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4942 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4943 if (!operand_type_match (overlap0
, i
.types
[0])
4944 || !operand_type_match (overlap1
, i
.types
[1])
4946 && !operand_type_register_match (overlap0
,
4953 /* Does not match either direction. */
4956 /* found_reverse_match holds which of D or FloatDR
4958 if (t
->opcode_modifier
.d
)
4959 found_reverse_match
= Opcode_D
;
4960 else if (t
->opcode_modifier
.floatd
)
4961 found_reverse_match
= Opcode_FloatD
;
4963 found_reverse_match
= 0;
4964 if (t
->opcode_modifier
.floatr
)
4965 found_reverse_match
|= Opcode_FloatR
;
4969 /* Found a forward 2 operand match here. */
4970 switch (t
->operands
)
4973 overlap4
= operand_type_and (i
.types
[4],
4976 overlap3
= operand_type_and (i
.types
[3],
4979 overlap2
= operand_type_and (i
.types
[2],
4984 switch (t
->operands
)
4987 if (!operand_type_match (overlap4
, i
.types
[4])
4988 || !operand_type_register_match (overlap3
,
4996 if (!operand_type_match (overlap3
, i
.types
[3])
4998 && !operand_type_register_match (overlap2
,
5006 /* Here we make use of the fact that there are no
5007 reverse match 3 operand instructions, and all 3
5008 operand instructions only need to be checked for
5009 register consistency between operands 2 and 3. */
5010 if (!operand_type_match (overlap2
, i
.types
[2])
5012 && !operand_type_register_match (overlap1
,
5022 /* Found either forward/reverse 2, 3 or 4 operand match here:
5023 slip through to break. */
5025 if (!found_cpu_match
)
5027 found_reverse_match
= 0;
5031 /* Check if vector and VEX operands are valid. */
5032 if (check_VecOperands (t
) || VEX_check_operands (t
))
5034 specific_error
= i
.error
;
5038 /* We've found a match; break out of loop. */
5042 if (t
== current_templates
->end
)
5044 /* We found no match. */
5045 const char *err_msg
;
5046 switch (specific_error
? specific_error
: i
.error
)
5050 case operand_size_mismatch
:
5051 err_msg
= _("operand size mismatch");
5053 case operand_type_mismatch
:
5054 err_msg
= _("operand type mismatch");
5056 case register_type_mismatch
:
5057 err_msg
= _("register type mismatch");
5059 case number_of_operands_mismatch
:
5060 err_msg
= _("number of operands mismatch");
5062 case invalid_instruction_suffix
:
5063 err_msg
= _("invalid instruction suffix");
5066 err_msg
= _("constant doesn't fit in 4 bits");
5069 err_msg
= _("only supported with old gcc");
5071 case unsupported_with_intel_mnemonic
:
5072 err_msg
= _("unsupported with Intel mnemonic");
5074 case unsupported_syntax
:
5075 err_msg
= _("unsupported syntax");
5078 as_bad (_("unsupported instruction `%s'"),
5079 current_templates
->start
->name
);
5081 case invalid_vsib_address
:
5082 err_msg
= _("invalid VSIB address");
5084 case invalid_vector_register_set
:
5085 err_msg
= _("mask, index, and destination registers must be distinct");
5087 case unsupported_vector_index_register
:
5088 err_msg
= _("unsupported vector index register");
5090 case unsupported_broadcast
:
5091 err_msg
= _("unsupported broadcast");
5093 case broadcast_not_on_src_operand
:
5094 err_msg
= _("broadcast not on source memory operand");
5096 case broadcast_needed
:
5097 err_msg
= _("broadcast is needed for operand of such type");
5099 case unsupported_masking
:
5100 err_msg
= _("unsupported masking");
5102 case mask_not_on_destination
:
5103 err_msg
= _("mask not on destination operand");
5105 case no_default_mask
:
5106 err_msg
= _("default mask isn't allowed");
5108 case unsupported_rc_sae
:
5109 err_msg
= _("unsupported static rounding/sae");
5111 case rc_sae_operand_not_last_imm
:
5113 err_msg
= _("RC/SAE operand must precede immediate operands");
5115 err_msg
= _("RC/SAE operand must follow immediate operands");
5117 case invalid_register_operand
:
5118 err_msg
= _("invalid register operand");
5121 as_bad (_("%s for `%s'"), err_msg
,
5122 current_templates
->start
->name
);
5126 if (!quiet_warnings
)
5129 && (i
.types
[0].bitfield
.jumpabsolute
5130 != operand_types
[0].bitfield
.jumpabsolute
))
5132 as_warn (_("indirect %s without `*'"), t
->name
);
5135 if (t
->opcode_modifier
.isprefix
5136 && t
->opcode_modifier
.ignoresize
)
5138 /* Warn them that a data or address size prefix doesn't
5139 affect assembly of the next line of code. */
5140 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5144 /* Copy the template we found. */
5147 if (addr_prefix_disp
!= -1)
5148 i
.tm
.operand_types
[addr_prefix_disp
]
5149 = operand_types
[addr_prefix_disp
];
5151 if (found_reverse_match
)
5153 /* If we found a reverse match we must alter the opcode
5154 direction bit. found_reverse_match holds bits to change
5155 (different for int & float insns). */
5157 i
.tm
.base_opcode
^= found_reverse_match
;
5159 i
.tm
.operand_types
[0] = operand_types
[1];
5160 i
.tm
.operand_types
[1] = operand_types
[0];
5169 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5170 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5172 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5174 as_bad (_("`%s' operand %d must use `%ses' segment"),
5180 /* There's only ever one segment override allowed per instruction.
5181 This instruction possibly has a legal segment override on the
5182 second operand, so copy the segment to where non-string
5183 instructions store it, allowing common code. */
5184 i
.seg
[0] = i
.seg
[1];
5186 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5188 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5190 as_bad (_("`%s' operand %d must use `%ses' segment"),
5201 process_suffix (void)
5203 /* If matched instruction specifies an explicit instruction mnemonic
5205 if (i
.tm
.opcode_modifier
.size16
)
5206 i
.suffix
= WORD_MNEM_SUFFIX
;
5207 else if (i
.tm
.opcode_modifier
.size32
)
5208 i
.suffix
= LONG_MNEM_SUFFIX
;
5209 else if (i
.tm
.opcode_modifier
.size64
)
5210 i
.suffix
= QWORD_MNEM_SUFFIX
;
5211 else if (i
.reg_operands
)
5213 /* If there's no instruction mnemonic suffix we try to invent one
5214 based on register operands. */
5217 /* We take i.suffix from the last register operand specified,
5218 Destination register type is more significant than source
5219 register type. crc32 in SSE4.2 prefers source register
5221 if (i
.tm
.base_opcode
== 0xf20f38f1)
5223 if (i
.types
[0].bitfield
.reg16
)
5224 i
.suffix
= WORD_MNEM_SUFFIX
;
5225 else if (i
.types
[0].bitfield
.reg32
)
5226 i
.suffix
= LONG_MNEM_SUFFIX
;
5227 else if (i
.types
[0].bitfield
.reg64
)
5228 i
.suffix
= QWORD_MNEM_SUFFIX
;
5230 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5232 if (i
.types
[0].bitfield
.reg8
)
5233 i
.suffix
= BYTE_MNEM_SUFFIX
;
5240 if (i
.tm
.base_opcode
== 0xf20f38f1
5241 || i
.tm
.base_opcode
== 0xf20f38f0)
5243 /* We have to know the operand size for crc32. */
5244 as_bad (_("ambiguous memory operand size for `%s`"),
5249 for (op
= i
.operands
; --op
>= 0;)
5250 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5252 if (i
.types
[op
].bitfield
.reg8
)
5254 i
.suffix
= BYTE_MNEM_SUFFIX
;
5257 else if (i
.types
[op
].bitfield
.reg16
)
5259 i
.suffix
= WORD_MNEM_SUFFIX
;
5262 else if (i
.types
[op
].bitfield
.reg32
)
5264 i
.suffix
= LONG_MNEM_SUFFIX
;
5267 else if (i
.types
[op
].bitfield
.reg64
)
5269 i
.suffix
= QWORD_MNEM_SUFFIX
;
5275 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5278 && i
.tm
.opcode_modifier
.ignoresize
5279 && i
.tm
.opcode_modifier
.no_bsuf
)
5281 else if (!check_byte_reg ())
5284 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5287 && i
.tm
.opcode_modifier
.ignoresize
5288 && i
.tm
.opcode_modifier
.no_lsuf
)
5290 else if (!check_long_reg ())
5293 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5296 && i
.tm
.opcode_modifier
.ignoresize
5297 && i
.tm
.opcode_modifier
.no_qsuf
)
5299 else if (!check_qword_reg ())
5302 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5305 && i
.tm
.opcode_modifier
.ignoresize
5306 && i
.tm
.opcode_modifier
.no_wsuf
)
5308 else if (!check_word_reg ())
5311 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5312 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5313 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5315 /* Skip if the instruction has x/y/z suffix. match_template
5316 should check if it is a valid suffix. */
5318 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5319 /* Do nothing if the instruction is going to ignore the prefix. */
5324 else if (i
.tm
.opcode_modifier
.defaultsize
5326 /* exclude fldenv/frstor/fsave/fstenv */
5327 && i
.tm
.opcode_modifier
.no_ssuf
)
5329 i
.suffix
= stackop_size
;
5331 else if (intel_syntax
5333 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5334 || i
.tm
.opcode_modifier
.jumpbyte
5335 || i
.tm
.opcode_modifier
.jumpintersegment
5336 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5337 && i
.tm
.extension_opcode
<= 3)))
5342 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5344 i
.suffix
= QWORD_MNEM_SUFFIX
;
5348 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5349 i
.suffix
= LONG_MNEM_SUFFIX
;
5352 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5353 i
.suffix
= WORD_MNEM_SUFFIX
;
5362 if (i
.tm
.opcode_modifier
.w
)
5364 as_bad (_("no instruction mnemonic suffix given and "
5365 "no register operands; can't size instruction"));
5371 unsigned int suffixes
;
5373 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5374 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5376 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5378 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5380 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5382 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5385 /* There are more than suffix matches. */
5386 if (i
.tm
.opcode_modifier
.w
5387 || ((suffixes
& (suffixes
- 1))
5388 && !i
.tm
.opcode_modifier
.defaultsize
5389 && !i
.tm
.opcode_modifier
.ignoresize
))
5391 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5397 /* Change the opcode based on the operand size given by i.suffix;
5398 We don't need to change things for byte insns. */
5401 && i
.suffix
!= BYTE_MNEM_SUFFIX
5402 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5403 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5404 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5406 /* It's not a byte, select word/dword operation. */
5407 if (i
.tm
.opcode_modifier
.w
)
5409 if (i
.tm
.opcode_modifier
.shortform
)
5410 i
.tm
.base_opcode
|= 8;
5412 i
.tm
.base_opcode
|= 1;
5415 /* Now select between word & dword operations via the operand
5416 size prefix, except for instructions that will ignore this
5418 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5420 /* The address size override prefix changes the size of the
5422 if ((flag_code
== CODE_32BIT
5423 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5424 || (flag_code
!= CODE_32BIT
5425 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5426 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5429 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5430 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5431 && !i
.tm
.opcode_modifier
.ignoresize
5432 && !i
.tm
.opcode_modifier
.floatmf
5433 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5434 || (flag_code
== CODE_64BIT
5435 && i
.tm
.opcode_modifier
.jumpbyte
)))
5437 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5439 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5440 prefix
= ADDR_PREFIX_OPCODE
;
5442 if (!add_prefix (prefix
))
5446 /* Set mode64 for an operand. */
5447 if (i
.suffix
== QWORD_MNEM_SUFFIX
5448 && flag_code
== CODE_64BIT
5449 && !i
.tm
.opcode_modifier
.norex64
)
5451 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5452 need rex64. cmpxchg8b is also a special case. */
5453 if (! (i
.operands
== 2
5454 && i
.tm
.base_opcode
== 0x90
5455 && i
.tm
.extension_opcode
== None
5456 && operand_type_equal (&i
.types
[0], &acc64
)
5457 && operand_type_equal (&i
.types
[1], &acc64
))
5458 && ! (i
.operands
== 1
5459 && i
.tm
.base_opcode
== 0xfc7
5460 && i
.tm
.extension_opcode
== 1
5461 && !operand_type_check (i
.types
[0], reg
)
5462 && operand_type_check (i
.types
[0], anymem
)))
5466 /* Size floating point instruction. */
5467 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5468 if (i
.tm
.opcode_modifier
.floatmf
)
5469 i
.tm
.base_opcode
^= 4;
5476 check_byte_reg (void)
5480 for (op
= i
.operands
; --op
>= 0;)
5482 /* If this is an eight bit register, it's OK. If it's the 16 or
5483 32 bit version of an eight bit register, we will just use the
5484 low portion, and that's OK too. */
5485 if (i
.types
[op
].bitfield
.reg8
)
5488 /* I/O port address operands are OK too. */
5489 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5492 /* crc32 doesn't generate this warning. */
5493 if (i
.tm
.base_opcode
== 0xf20f38f0)
5496 if ((i
.types
[op
].bitfield
.reg16
5497 || i
.types
[op
].bitfield
.reg32
5498 || i
.types
[op
].bitfield
.reg64
)
5499 && i
.op
[op
].regs
->reg_num
< 4
5500 /* Prohibit these changes in 64bit mode, since the lowering
5501 would be more complicated. */
5502 && flag_code
!= CODE_64BIT
)
5504 #if REGISTER_WARNINGS
5505 if (!quiet_warnings
)
5506 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5508 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5509 ? REGNAM_AL
- REGNAM_AX
5510 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5512 i
.op
[op
].regs
->reg_name
,
5517 /* Any other register is bad. */
5518 if (i
.types
[op
].bitfield
.reg16
5519 || i
.types
[op
].bitfield
.reg32
5520 || i
.types
[op
].bitfield
.reg64
5521 || i
.types
[op
].bitfield
.regmmx
5522 || i
.types
[op
].bitfield
.regxmm
5523 || i
.types
[op
].bitfield
.regymm
5524 || i
.types
[op
].bitfield
.regzmm
5525 || i
.types
[op
].bitfield
.sreg2
5526 || i
.types
[op
].bitfield
.sreg3
5527 || i
.types
[op
].bitfield
.control
5528 || i
.types
[op
].bitfield
.debug
5529 || i
.types
[op
].bitfield
.test
5530 || i
.types
[op
].bitfield
.floatreg
5531 || i
.types
[op
].bitfield
.floatacc
)
5533 as_bad (_("`%s%s' not allowed with `%s%c'"),
5535 i
.op
[op
].regs
->reg_name
,
5545 check_long_reg (void)
5549 for (op
= i
.operands
; --op
>= 0;)
5550 /* Reject eight bit registers, except where the template requires
5551 them. (eg. movzb) */
5552 if (i
.types
[op
].bitfield
.reg8
5553 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5554 || i
.tm
.operand_types
[op
].bitfield
.reg32
5555 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5557 as_bad (_("`%s%s' not allowed with `%s%c'"),
5559 i
.op
[op
].regs
->reg_name
,
5564 /* Warn if the e prefix on a general reg is missing. */
5565 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5566 && i
.types
[op
].bitfield
.reg16
5567 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5568 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5570 /* Prohibit these changes in the 64bit mode, since the
5571 lowering is more complicated. */
5572 if (flag_code
== CODE_64BIT
)
5574 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5575 register_prefix
, i
.op
[op
].regs
->reg_name
,
5579 #if REGISTER_WARNINGS
5580 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5582 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5583 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5586 /* Warn if the r prefix on a general reg is present. */
5587 else if (i
.types
[op
].bitfield
.reg64
5588 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5589 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5592 && i
.tm
.opcode_modifier
.toqword
5593 && !i
.types
[0].bitfield
.regxmm
)
5595 /* Convert to QWORD. We want REX byte. */
5596 i
.suffix
= QWORD_MNEM_SUFFIX
;
5600 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5601 register_prefix
, i
.op
[op
].regs
->reg_name
,
5610 check_qword_reg (void)
5614 for (op
= i
.operands
; --op
>= 0; )
5615 /* Reject eight bit registers, except where the template requires
5616 them. (eg. movzb) */
5617 if (i
.types
[op
].bitfield
.reg8
5618 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5619 || i
.tm
.operand_types
[op
].bitfield
.reg32
5620 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5622 as_bad (_("`%s%s' not allowed with `%s%c'"),
5624 i
.op
[op
].regs
->reg_name
,
5629 /* Warn if the r prefix on a general reg is missing. */
5630 else if ((i
.types
[op
].bitfield
.reg16
5631 || i
.types
[op
].bitfield
.reg32
)
5632 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5633 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5635 /* Prohibit these changes in the 64bit mode, since the
5636 lowering is more complicated. */
5638 && i
.tm
.opcode_modifier
.todword
5639 && !i
.types
[0].bitfield
.regxmm
)
5641 /* Convert to DWORD. We don't want REX byte. */
5642 i
.suffix
= LONG_MNEM_SUFFIX
;
5646 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5647 register_prefix
, i
.op
[op
].regs
->reg_name
,
5656 check_word_reg (void)
5659 for (op
= i
.operands
; --op
>= 0;)
5660 /* Reject eight bit registers, except where the template requires
5661 them. (eg. movzb) */
5662 if (i
.types
[op
].bitfield
.reg8
5663 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5664 || i
.tm
.operand_types
[op
].bitfield
.reg32
5665 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5667 as_bad (_("`%s%s' not allowed with `%s%c'"),
5669 i
.op
[op
].regs
->reg_name
,
5674 /* Warn if the e or r prefix on a general reg is present. */
5675 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5676 && (i
.types
[op
].bitfield
.reg32
5677 || i
.types
[op
].bitfield
.reg64
)
5678 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5679 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5681 /* Prohibit these changes in the 64bit mode, since the
5682 lowering is more complicated. */
5683 if (flag_code
== CODE_64BIT
)
5685 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5686 register_prefix
, i
.op
[op
].regs
->reg_name
,
5690 #if REGISTER_WARNINGS
5691 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5693 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5694 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5701 update_imm (unsigned int j
)
5703 i386_operand_type overlap
= i
.types
[j
];
5704 if ((overlap
.bitfield
.imm8
5705 || overlap
.bitfield
.imm8s
5706 || overlap
.bitfield
.imm16
5707 || overlap
.bitfield
.imm32
5708 || overlap
.bitfield
.imm32s
5709 || overlap
.bitfield
.imm64
)
5710 && !operand_type_equal (&overlap
, &imm8
)
5711 && !operand_type_equal (&overlap
, &imm8s
)
5712 && !operand_type_equal (&overlap
, &imm16
)
5713 && !operand_type_equal (&overlap
, &imm32
)
5714 && !operand_type_equal (&overlap
, &imm32s
)
5715 && !operand_type_equal (&overlap
, &imm64
))
5719 i386_operand_type temp
;
5721 operand_type_set (&temp
, 0);
5722 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5724 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5725 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5727 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5728 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5729 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5731 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5732 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5735 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5738 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5739 || operand_type_equal (&overlap
, &imm16_32
)
5740 || operand_type_equal (&overlap
, &imm16_32s
))
5742 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5747 if (!operand_type_equal (&overlap
, &imm8
)
5748 && !operand_type_equal (&overlap
, &imm8s
)
5749 && !operand_type_equal (&overlap
, &imm16
)
5750 && !operand_type_equal (&overlap
, &imm32
)
5751 && !operand_type_equal (&overlap
, &imm32s
)
5752 && !operand_type_equal (&overlap
, &imm64
))
5754 as_bad (_("no instruction mnemonic suffix given; "
5755 "can't determine immediate size"));
5759 i
.types
[j
] = overlap
;
5769 /* Update the first 2 immediate operands. */
5770 n
= i
.operands
> 2 ? 2 : i
.operands
;
5773 for (j
= 0; j
< n
; j
++)
5774 if (update_imm (j
) == 0)
5777 /* The 3rd operand can't be immediate operand. */
5778 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5785 bad_implicit_operand (int xmm
)
5787 const char *ireg
= xmm
? "xmm0" : "ymm0";
5790 as_bad (_("the last operand of `%s' must be `%s%s'"),
5791 i
.tm
.name
, register_prefix
, ireg
);
5793 as_bad (_("the first operand of `%s' must be `%s%s'"),
5794 i
.tm
.name
, register_prefix
, ireg
);
5799 process_operands (void)
5801 /* Default segment register this instruction will use for memory
5802 accesses. 0 means unknown. This is only for optimizing out
5803 unnecessary segment overrides. */
5804 const seg_entry
*default_seg
= 0;
5806 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5808 unsigned int dupl
= i
.operands
;
5809 unsigned int dest
= dupl
- 1;
5812 /* The destination must be an xmm register. */
5813 gas_assert (i
.reg_operands
5814 && MAX_OPERANDS
> dupl
5815 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5817 if (i
.tm
.opcode_modifier
.firstxmm0
)
5819 /* The first operand is implicit and must be xmm0. */
5820 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5821 if (register_number (i
.op
[0].regs
) != 0)
5822 return bad_implicit_operand (1);
5824 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5826 /* Keep xmm0 for instructions with VEX prefix and 3
5832 /* We remove the first xmm0 and keep the number of
5833 operands unchanged, which in fact duplicates the
5835 for (j
= 1; j
< i
.operands
; j
++)
5837 i
.op
[j
- 1] = i
.op
[j
];
5838 i
.types
[j
- 1] = i
.types
[j
];
5839 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5843 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5845 gas_assert ((MAX_OPERANDS
- 1) > dupl
5846 && (i
.tm
.opcode_modifier
.vexsources
5849 /* Add the implicit xmm0 for instructions with VEX prefix
5851 for (j
= i
.operands
; j
> 0; j
--)
5853 i
.op
[j
] = i
.op
[j
- 1];
5854 i
.types
[j
] = i
.types
[j
- 1];
5855 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5858 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5859 i
.types
[0] = regxmm
;
5860 i
.tm
.operand_types
[0] = regxmm
;
5863 i
.reg_operands
+= 2;
5868 i
.op
[dupl
] = i
.op
[dest
];
5869 i
.types
[dupl
] = i
.types
[dest
];
5870 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5879 i
.op
[dupl
] = i
.op
[dest
];
5880 i
.types
[dupl
] = i
.types
[dest
];
5881 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5884 if (i
.tm
.opcode_modifier
.immext
)
5887 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5891 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5892 gas_assert (i
.reg_operands
5893 && (operand_type_equal (&i
.types
[0], ®xmm
)
5894 || operand_type_equal (&i
.types
[0], ®ymm
)
5895 || operand_type_equal (&i
.types
[0], ®zmm
)));
5896 if (register_number (i
.op
[0].regs
) != 0)
5897 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5899 for (j
= 1; j
< i
.operands
; j
++)
5901 i
.op
[j
- 1] = i
.op
[j
];
5902 i
.types
[j
- 1] = i
.types
[j
];
5904 /* We need to adjust fields in i.tm since they are used by
5905 build_modrm_byte. */
5906 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5913 else if (i
.tm
.opcode_modifier
.regkludge
)
5915 /* The imul $imm, %reg instruction is converted into
5916 imul $imm, %reg, %reg, and the clr %reg instruction
5917 is converted into xor %reg, %reg. */
5919 unsigned int first_reg_op
;
5921 if (operand_type_check (i
.types
[0], reg
))
5925 /* Pretend we saw the extra register operand. */
5926 gas_assert (i
.reg_operands
== 1
5927 && i
.op
[first_reg_op
+ 1].regs
== 0);
5928 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5929 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5934 if (i
.tm
.opcode_modifier
.shortform
)
5936 if (i
.types
[0].bitfield
.sreg2
5937 || i
.types
[0].bitfield
.sreg3
)
5939 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5940 && i
.op
[0].regs
->reg_num
== 1)
5942 as_bad (_("you can't `pop %scs'"), register_prefix
);
5945 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5946 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5951 /* The register or float register operand is in operand
5955 if (i
.types
[0].bitfield
.floatreg
5956 || operand_type_check (i
.types
[0], reg
))
5960 /* Register goes in low 3 bits of opcode. */
5961 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5962 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5964 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5966 /* Warn about some common errors, but press on regardless.
5967 The first case can be generated by gcc (<= 2.8.1). */
5968 if (i
.operands
== 2)
5970 /* Reversed arguments on faddp, fsubp, etc. */
5971 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5972 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5973 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5977 /* Extraneous `l' suffix on fp insn. */
5978 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5979 register_prefix
, i
.op
[0].regs
->reg_name
);
5984 else if (i
.tm
.opcode_modifier
.modrm
)
5986 /* The opcode is completed (modulo i.tm.extension_opcode which
5987 must be put into the modrm byte). Now, we make the modrm and
5988 index base bytes based on all the info we've collected. */
5990 default_seg
= build_modrm_byte ();
5992 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5996 else if (i
.tm
.opcode_modifier
.isstring
)
5998 /* For the string instructions that allow a segment override
5999 on one of their operands, the default segment is ds. */
6003 if (i
.tm
.base_opcode
== 0x8d /* lea */
6006 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6008 /* If a segment was explicitly specified, and the specified segment
6009 is not the default, use an opcode prefix to select it. If we
6010 never figured out what the default segment is, then default_seg
6011 will be zero at this point, and the specified segment prefix will
6013 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6015 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6021 static const seg_entry
*
6022 build_modrm_byte (void)
6024 const seg_entry
*default_seg
= 0;
6025 unsigned int source
, dest
;
6028 /* The first operand of instructions with VEX prefix and 3 sources
6029 must be VEX_Imm4. */
6030 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6033 unsigned int nds
, reg_slot
;
6036 if (i
.tm
.opcode_modifier
.veximmext
6037 && i
.tm
.opcode_modifier
.immext
)
6039 dest
= i
.operands
- 2;
6040 gas_assert (dest
== 3);
6043 dest
= i
.operands
- 1;
6046 /* There are 2 kinds of instructions:
6047 1. 5 operands: 4 register operands or 3 register operands
6048 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6049 VexW0 or VexW1. The destination must be either XMM, YMM or
6051 2. 4 operands: 4 register operands or 3 register operands
6052 plus 1 memory operand, VexXDS, and VexImmExt */
6053 gas_assert ((i
.reg_operands
== 4
6054 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6055 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6056 && (i
.tm
.opcode_modifier
.veximmext
6057 || (i
.imm_operands
== 1
6058 && i
.types
[0].bitfield
.vec_imm4
6059 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
6060 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6061 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
6062 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
6063 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
6065 if (i
.imm_operands
== 0)
6067 /* When there is no immediate operand, generate an 8bit
6068 immediate operand to encode the first operand. */
6069 exp
= &im_expressions
[i
.imm_operands
++];
6070 i
.op
[i
.operands
].imms
= exp
;
6071 i
.types
[i
.operands
] = imm8
;
6073 /* If VexW1 is set, the first operand is the source and
6074 the second operand is encoded in the immediate operand. */
6075 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6086 /* FMA swaps REG and NDS. */
6087 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6095 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6097 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6099 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6101 exp
->X_op
= O_constant
;
6102 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6103 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6107 unsigned int imm_slot
;
6109 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6111 /* If VexW0 is set, the third operand is the source and
6112 the second operand is encoded in the immediate
6119 /* VexW1 is set, the second operand is the source and
6120 the third operand is encoded in the immediate
6126 if (i
.tm
.opcode_modifier
.immext
)
6128 /* When ImmExt is set, the immdiate byte is the last
6130 imm_slot
= i
.operands
- 1;
6138 /* Turn on Imm8 so that output_imm will generate it. */
6139 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6142 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6144 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6146 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6148 i
.op
[imm_slot
].imms
->X_add_number
6149 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6150 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6153 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6154 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6156 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6158 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6163 /* i.reg_operands MUST be the number of real register operands;
6164 implicit registers do not count. If there are 3 register
6165 operands, it must be a instruction with VexNDS. For a
6166 instruction with VexNDD, the destination register is encoded
6167 in VEX prefix. If there are 4 register operands, it must be
6168 a instruction with VEX prefix and 3 sources. */
6169 if (i
.mem_operands
== 0
6170 && ((i
.reg_operands
== 2
6171 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6172 || (i
.reg_operands
== 3
6173 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6174 || (i
.reg_operands
== 4 && vex_3_sources
)))
6182 /* When there are 3 operands, one of them may be immediate,
6183 which may be the first or the last operand. Otherwise,
6184 the first operand must be shift count register (cl) or it
6185 is an instruction with VexNDS. */
6186 gas_assert (i
.imm_operands
== 1
6187 || (i
.imm_operands
== 0
6188 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6189 || i
.types
[0].bitfield
.shiftcount
)));
6190 if (operand_type_check (i
.types
[0], imm
)
6191 || i
.types
[0].bitfield
.shiftcount
)
6197 /* When there are 4 operands, the first two must be 8bit
6198 immediate operands. The source operand will be the 3rd
6201 For instructions with VexNDS, if the first operand
6202 an imm8, the source operand is the 2nd one. If the last
6203 operand is imm8, the source operand is the first one. */
6204 gas_assert ((i
.imm_operands
== 2
6205 && i
.types
[0].bitfield
.imm8
6206 && i
.types
[1].bitfield
.imm8
)
6207 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6208 && i
.imm_operands
== 1
6209 && (i
.types
[0].bitfield
.imm8
6210 || i
.types
[i
.operands
- 1].bitfield
.imm8
6212 if (i
.imm_operands
== 2)
6216 if (i
.types
[0].bitfield
.imm8
)
6223 if (i
.tm
.opcode_modifier
.evex
)
6225 /* For EVEX instructions, when there are 5 operands, the
6226 first one must be immediate operand. If the second one
6227 is immediate operand, the source operand is the 3th
6228 one. If the last one is immediate operand, the source
6229 operand is the 2nd one. */
6230 gas_assert (i
.imm_operands
== 2
6231 && i
.tm
.opcode_modifier
.sae
6232 && operand_type_check (i
.types
[0], imm
));
6233 if (operand_type_check (i
.types
[1], imm
))
6235 else if (operand_type_check (i
.types
[4], imm
))
6249 /* RC/SAE operand could be between DEST and SRC. That happens
6250 when one operand is GPR and the other one is XMM/YMM/ZMM
6252 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6255 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6257 /* For instructions with VexNDS, the register-only source
6258 operand must be 32/64bit integer, XMM, YMM or ZMM
6259 register. It is encoded in VEX prefix. We need to
6260 clear RegMem bit before calling operand_type_equal. */
6262 i386_operand_type op
;
6265 /* Check register-only source operand when two source
6266 operands are swapped. */
6267 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6268 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6276 op
= i
.tm
.operand_types
[vvvv
];
6277 op
.bitfield
.regmem
= 0;
6278 if ((dest
+ 1) >= i
.operands
6279 || (!op
.bitfield
.reg32
6280 && op
.bitfield
.reg64
6281 && !operand_type_equal (&op
, ®xmm
)
6282 && !operand_type_equal (&op
, ®ymm
)
6283 && !operand_type_equal (&op
, ®zmm
)
6284 && !operand_type_equal (&op
, ®mask
)))
6286 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6292 /* One of the register operands will be encoded in the i.tm.reg
6293 field, the other in the combined i.tm.mode and i.tm.regmem
6294 fields. If no form of this instruction supports a memory
6295 destination operand, then we assume the source operand may
6296 sometimes be a memory operand and so we need to store the
6297 destination in the i.rm.reg field. */
6298 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6299 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6301 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6302 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6303 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6305 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6307 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6309 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6314 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6315 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6316 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6318 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6320 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6322 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6325 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6327 if (!i
.types
[0].bitfield
.control
6328 && !i
.types
[1].bitfield
.control
)
6330 i
.rex
&= ~(REX_R
| REX_B
);
6331 add_prefix (LOCK_PREFIX_OPCODE
);
6335 { /* If it's not 2 reg operands... */
6340 unsigned int fake_zero_displacement
= 0;
6343 for (op
= 0; op
< i
.operands
; op
++)
6344 if (operand_type_check (i
.types
[op
], anymem
))
6346 gas_assert (op
< i
.operands
);
6348 if (i
.tm
.opcode_modifier
.vecsib
)
6350 if (i
.index_reg
->reg_num
== RegEiz
6351 || i
.index_reg
->reg_num
== RegRiz
)
6354 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6357 i
.sib
.base
= NO_BASE_REGISTER
;
6358 i
.sib
.scale
= i
.log2_scale_factor
;
6359 /* No Vec_Disp8 if there is no base. */
6360 i
.types
[op
].bitfield
.vec_disp8
= 0;
6361 i
.types
[op
].bitfield
.disp8
= 0;
6362 i
.types
[op
].bitfield
.disp16
= 0;
6363 i
.types
[op
].bitfield
.disp64
= 0;
6364 if (flag_code
!= CODE_64BIT
)
6366 /* Must be 32 bit */
6367 i
.types
[op
].bitfield
.disp32
= 1;
6368 i
.types
[op
].bitfield
.disp32s
= 0;
6372 i
.types
[op
].bitfield
.disp32
= 0;
6373 i
.types
[op
].bitfield
.disp32s
= 1;
6376 i
.sib
.index
= i
.index_reg
->reg_num
;
6377 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6379 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6385 if (i
.base_reg
== 0)
6388 if (!i
.disp_operands
)
6390 fake_zero_displacement
= 1;
6391 /* Instructions with VSIB byte need 32bit displacement
6392 if there is no base register. */
6393 if (i
.tm
.opcode_modifier
.vecsib
)
6394 i
.types
[op
].bitfield
.disp32
= 1;
6396 if (i
.index_reg
== 0)
6398 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6399 /* Operand is just <disp> */
6400 if (flag_code
== CODE_64BIT
)
6402 /* 64bit mode overwrites the 32bit absolute
6403 addressing by RIP relative addressing and
6404 absolute addressing is encoded by one of the
6405 redundant SIB forms. */
6406 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6407 i
.sib
.base
= NO_BASE_REGISTER
;
6408 i
.sib
.index
= NO_INDEX_REGISTER
;
6409 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6410 ? disp32s
: disp32
);
6412 else if ((flag_code
== CODE_16BIT
)
6413 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6415 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6416 i
.types
[op
] = disp16
;
6420 i
.rm
.regmem
= NO_BASE_REGISTER
;
6421 i
.types
[op
] = disp32
;
6424 else if (!i
.tm
.opcode_modifier
.vecsib
)
6426 /* !i.base_reg && i.index_reg */
6427 if (i
.index_reg
->reg_num
== RegEiz
6428 || i
.index_reg
->reg_num
== RegRiz
)
6429 i
.sib
.index
= NO_INDEX_REGISTER
;
6431 i
.sib
.index
= i
.index_reg
->reg_num
;
6432 i
.sib
.base
= NO_BASE_REGISTER
;
6433 i
.sib
.scale
= i
.log2_scale_factor
;
6434 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6435 /* No Vec_Disp8 if there is no base. */
6436 i
.types
[op
].bitfield
.vec_disp8
= 0;
6437 i
.types
[op
].bitfield
.disp8
= 0;
6438 i
.types
[op
].bitfield
.disp16
= 0;
6439 i
.types
[op
].bitfield
.disp64
= 0;
6440 if (flag_code
!= CODE_64BIT
)
6442 /* Must be 32 bit */
6443 i
.types
[op
].bitfield
.disp32
= 1;
6444 i
.types
[op
].bitfield
.disp32s
= 0;
6448 i
.types
[op
].bitfield
.disp32
= 0;
6449 i
.types
[op
].bitfield
.disp32s
= 1;
6451 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6455 /* RIP addressing for 64bit mode. */
6456 else if (i
.base_reg
->reg_num
== RegRip
||
6457 i
.base_reg
->reg_num
== RegEip
)
6459 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6460 i
.rm
.regmem
= NO_BASE_REGISTER
;
6461 i
.types
[op
].bitfield
.disp8
= 0;
6462 i
.types
[op
].bitfield
.disp16
= 0;
6463 i
.types
[op
].bitfield
.disp32
= 0;
6464 i
.types
[op
].bitfield
.disp32s
= 1;
6465 i
.types
[op
].bitfield
.disp64
= 0;
6466 i
.types
[op
].bitfield
.vec_disp8
= 0;
6467 i
.flags
[op
] |= Operand_PCrel
;
6468 if (! i
.disp_operands
)
6469 fake_zero_displacement
= 1;
6471 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6473 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6474 switch (i
.base_reg
->reg_num
)
6477 if (i
.index_reg
== 0)
6479 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6480 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6484 if (i
.index_reg
== 0)
6487 if (operand_type_check (i
.types
[op
], disp
) == 0)
6489 /* fake (%bp) into 0(%bp) */
6490 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6491 i
.types
[op
].bitfield
.vec_disp8
= 1;
6493 i
.types
[op
].bitfield
.disp8
= 1;
6494 fake_zero_displacement
= 1;
6497 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6498 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6500 default: /* (%si) -> 4 or (%di) -> 5 */
6501 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6503 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6505 else /* i.base_reg and 32/64 bit mode */
6507 if (flag_code
== CODE_64BIT
6508 && operand_type_check (i
.types
[op
], disp
))
6510 i386_operand_type temp
;
6511 operand_type_set (&temp
, 0);
6512 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6513 temp
.bitfield
.vec_disp8
6514 = i
.types
[op
].bitfield
.vec_disp8
;
6516 if (i
.prefix
[ADDR_PREFIX
] == 0)
6517 i
.types
[op
].bitfield
.disp32s
= 1;
6519 i
.types
[op
].bitfield
.disp32
= 1;
6522 if (!i
.tm
.opcode_modifier
.vecsib
)
6523 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6524 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6526 i
.sib
.base
= i
.base_reg
->reg_num
;
6527 /* x86-64 ignores REX prefix bit here to avoid decoder
6529 if (!(i
.base_reg
->reg_flags
& RegRex
)
6530 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6531 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6533 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6535 fake_zero_displacement
= 1;
6536 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6537 i
.types
[op
].bitfield
.vec_disp8
= 1;
6539 i
.types
[op
].bitfield
.disp8
= 1;
6541 i
.sib
.scale
= i
.log2_scale_factor
;
6542 if (i
.index_reg
== 0)
6544 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6545 /* <disp>(%esp) becomes two byte modrm with no index
6546 register. We've already stored the code for esp
6547 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6548 Any base register besides %esp will not use the
6549 extra modrm byte. */
6550 i
.sib
.index
= NO_INDEX_REGISTER
;
6552 else if (!i
.tm
.opcode_modifier
.vecsib
)
6554 if (i
.index_reg
->reg_num
== RegEiz
6555 || i
.index_reg
->reg_num
== RegRiz
)
6556 i
.sib
.index
= NO_INDEX_REGISTER
;
6558 i
.sib
.index
= i
.index_reg
->reg_num
;
6559 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6560 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6565 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6566 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6570 if (!fake_zero_displacement
6574 fake_zero_displacement
= 1;
6575 if (i
.disp_encoding
== disp_encoding_8bit
)
6576 i
.types
[op
].bitfield
.disp8
= 1;
6578 i
.types
[op
].bitfield
.disp32
= 1;
6580 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6584 if (fake_zero_displacement
)
6586 /* Fakes a zero displacement assuming that i.types[op]
6587 holds the correct displacement size. */
6590 gas_assert (i
.op
[op
].disps
== 0);
6591 exp
= &disp_expressions
[i
.disp_operands
++];
6592 i
.op
[op
].disps
= exp
;
6593 exp
->X_op
= O_constant
;
6594 exp
->X_add_number
= 0;
6595 exp
->X_add_symbol
= (symbolS
*) 0;
6596 exp
->X_op_symbol
= (symbolS
*) 0;
6604 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6606 if (operand_type_check (i
.types
[0], imm
))
6607 i
.vex
.register_specifier
= NULL
;
6610 /* VEX.vvvv encodes one of the sources when the first
6611 operand is not an immediate. */
6612 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6613 i
.vex
.register_specifier
= i
.op
[0].regs
;
6615 i
.vex
.register_specifier
= i
.op
[1].regs
;
6618 /* Destination is a XMM register encoded in the ModRM.reg
6620 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6621 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6624 /* ModRM.rm and VEX.B encodes the other source. */
6625 if (!i
.mem_operands
)
6629 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6630 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6632 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6634 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6638 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6640 i
.vex
.register_specifier
= i
.op
[2].regs
;
6641 if (!i
.mem_operands
)
6644 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6645 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6649 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6650 (if any) based on i.tm.extension_opcode. Again, we must be
6651 careful to make sure that segment/control/debug/test/MMX
6652 registers are coded into the i.rm.reg field. */
6653 else if (i
.reg_operands
)
6656 unsigned int vex_reg
= ~0;
6658 for (op
= 0; op
< i
.operands
; op
++)
6659 if (i
.types
[op
].bitfield
.reg8
6660 || i
.types
[op
].bitfield
.reg16
6661 || i
.types
[op
].bitfield
.reg32
6662 || i
.types
[op
].bitfield
.reg64
6663 || i
.types
[op
].bitfield
.regmmx
6664 || i
.types
[op
].bitfield
.regxmm
6665 || i
.types
[op
].bitfield
.regymm
6666 || i
.types
[op
].bitfield
.regbnd
6667 || i
.types
[op
].bitfield
.regzmm
6668 || i
.types
[op
].bitfield
.regmask
6669 || i
.types
[op
].bitfield
.sreg2
6670 || i
.types
[op
].bitfield
.sreg3
6671 || i
.types
[op
].bitfield
.control
6672 || i
.types
[op
].bitfield
.debug
6673 || i
.types
[op
].bitfield
.test
)
6678 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6680 /* For instructions with VexNDS, the register-only
6681 source operand is encoded in VEX prefix. */
6682 gas_assert (mem
!= (unsigned int) ~0);
6687 gas_assert (op
< i
.operands
);
6691 /* Check register-only source operand when two source
6692 operands are swapped. */
6693 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6694 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6698 gas_assert (mem
== (vex_reg
+ 1)
6699 && op
< i
.operands
);
6704 gas_assert (vex_reg
< i
.operands
);
6708 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6710 /* For instructions with VexNDD, the register destination
6711 is encoded in VEX prefix. */
6712 if (i
.mem_operands
== 0)
6714 /* There is no memory operand. */
6715 gas_assert ((op
+ 2) == i
.operands
);
6720 /* There are only 2 operands. */
6721 gas_assert (op
< 2 && i
.operands
== 2);
6726 gas_assert (op
< i
.operands
);
6728 if (vex_reg
!= (unsigned int) ~0)
6730 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6732 if (type
->bitfield
.reg32
!= 1
6733 && type
->bitfield
.reg64
!= 1
6734 && !operand_type_equal (type
, ®xmm
)
6735 && !operand_type_equal (type
, ®ymm
)
6736 && !operand_type_equal (type
, ®zmm
)
6737 && !operand_type_equal (type
, ®mask
))
6740 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6743 /* Don't set OP operand twice. */
6746 /* If there is an extension opcode to put here, the
6747 register number must be put into the regmem field. */
6748 if (i
.tm
.extension_opcode
!= None
)
6750 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6751 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6753 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6758 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6759 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6761 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6766 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6767 must set it to 3 to indicate this is a register operand
6768 in the regmem field. */
6769 if (!i
.mem_operands
)
6773 /* Fill in i.rm.reg field with extension opcode (if any). */
6774 if (i
.tm
.extension_opcode
!= None
)
6775 i
.rm
.reg
= i
.tm
.extension_opcode
;
6781 output_branch (void)
6787 relax_substateT subtype
;
6791 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6792 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6795 if (i
.prefix
[DATA_PREFIX
] != 0)
6801 /* Pentium4 branch hints. */
6802 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6803 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6808 if (i
.prefix
[REX_PREFIX
] != 0)
6814 /* BND prefixed jump. */
6815 if (i
.prefix
[BND_PREFIX
] != 0)
6817 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6821 if (i
.prefixes
!= 0 && !intel_syntax
)
6822 as_warn (_("skipping prefixes on this instruction"));
6824 /* It's always a symbol; End frag & setup for relax.
6825 Make sure there is enough room in this frag for the largest
6826 instruction we may generate in md_convert_frag. This is 2
6827 bytes for the opcode and room for the prefix and largest
6829 frag_grow (prefix
+ 2 + 4);
6830 /* Prefix and 1 opcode byte go in fr_fix. */
6831 p
= frag_more (prefix
+ 1);
6832 if (i
.prefix
[DATA_PREFIX
] != 0)
6833 *p
++ = DATA_PREFIX_OPCODE
;
6834 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6835 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6836 *p
++ = i
.prefix
[SEG_PREFIX
];
6837 if (i
.prefix
[REX_PREFIX
] != 0)
6838 *p
++ = i
.prefix
[REX_PREFIX
];
6839 *p
= i
.tm
.base_opcode
;
6841 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6842 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6843 else if (cpu_arch_flags
.bitfield
.cpui386
)
6844 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6846 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6849 sym
= i
.op
[0].disps
->X_add_symbol
;
6850 off
= i
.op
[0].disps
->X_add_number
;
6852 if (i
.op
[0].disps
->X_op
!= O_constant
6853 && i
.op
[0].disps
->X_op
!= O_symbol
)
6855 /* Handle complex expressions. */
6856 sym
= make_expr_symbol (i
.op
[0].disps
);
6860 /* 1 possible extra opcode + 4 byte displacement go in var part.
6861 Pass reloc in fr_var. */
6862 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6872 if (i
.tm
.opcode_modifier
.jumpbyte
)
6874 /* This is a loop or jecxz type instruction. */
6876 if (i
.prefix
[ADDR_PREFIX
] != 0)
6878 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6881 /* Pentium4 branch hints. */
6882 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6883 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6885 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6894 if (flag_code
== CODE_16BIT
)
6897 if (i
.prefix
[DATA_PREFIX
] != 0)
6899 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6909 if (i
.prefix
[REX_PREFIX
] != 0)
6911 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6915 /* BND prefixed jump. */
6916 if (i
.prefix
[BND_PREFIX
] != 0)
6918 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6922 if (i
.prefixes
!= 0 && !intel_syntax
)
6923 as_warn (_("skipping prefixes on this instruction"));
6925 p
= frag_more (i
.tm
.opcode_length
+ size
);
6926 switch (i
.tm
.opcode_length
)
6929 *p
++ = i
.tm
.base_opcode
>> 8;
6931 *p
++ = i
.tm
.base_opcode
;
6937 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6938 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6940 /* All jumps handled here are signed, but don't use a signed limit
6941 check for 32 and 16 bit jumps as we want to allow wrap around at
6942 4G and 64k respectively. */
6944 fixP
->fx_signed
= 1;
6948 output_interseg_jump (void)
6956 if (flag_code
== CODE_16BIT
)
6960 if (i
.prefix
[DATA_PREFIX
] != 0)
6966 if (i
.prefix
[REX_PREFIX
] != 0)
6976 if (i
.prefixes
!= 0 && !intel_syntax
)
6977 as_warn (_("skipping prefixes on this instruction"));
6979 /* 1 opcode; 2 segment; offset */
6980 p
= frag_more (prefix
+ 1 + 2 + size
);
6982 if (i
.prefix
[DATA_PREFIX
] != 0)
6983 *p
++ = DATA_PREFIX_OPCODE
;
6985 if (i
.prefix
[REX_PREFIX
] != 0)
6986 *p
++ = i
.prefix
[REX_PREFIX
];
6988 *p
++ = i
.tm
.base_opcode
;
6989 if (i
.op
[1].imms
->X_op
== O_constant
)
6991 offsetT n
= i
.op
[1].imms
->X_add_number
;
6994 && !fits_in_unsigned_word (n
)
6995 && !fits_in_signed_word (n
))
6997 as_bad (_("16-bit jump out of range"));
7000 md_number_to_chars (p
, n
, size
);
7003 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7004 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7005 if (i
.op
[0].imms
->X_op
!= O_constant
)
7006 as_bad (_("can't handle non absolute segment in `%s'"),
7008 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7014 fragS
*insn_start_frag
;
7015 offsetT insn_start_off
;
7017 /* Tie dwarf2 debug info to the address at the start of the insn.
7018 We can't do this after the insn has been output as the current
7019 frag may have been closed off. eg. by frag_var. */
7020 dwarf2_emit_insn (0);
7022 insn_start_frag
= frag_now
;
7023 insn_start_off
= frag_now_fix ();
7026 if (i
.tm
.opcode_modifier
.jump
)
7028 else if (i
.tm
.opcode_modifier
.jumpbyte
7029 || i
.tm
.opcode_modifier
.jumpdword
)
7031 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7032 output_interseg_jump ();
7035 /* Output normal instructions here. */
7039 unsigned int prefix
;
7042 && i
.tm
.base_opcode
== 0xfae
7044 && i
.imm_operands
== 1
7045 && (i
.op
[0].imms
->X_add_number
== 0xe8
7046 || i
.op
[0].imms
->X_add_number
== 0xf0
7047 || i
.op
[0].imms
->X_add_number
== 0xf8))
7049 /* Encode lfence, mfence, and sfence as
7050 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7051 offsetT val
= 0x240483f0ULL
;
7053 md_number_to_chars (p
, val
, 5);
7057 /* Some processors fail on LOCK prefix. This options makes
7058 assembler ignore LOCK prefix and serves as a workaround. */
7059 if (omit_lock_prefix
)
7061 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7063 i
.prefix
[LOCK_PREFIX
] = 0;
7066 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7067 don't need the explicit prefix. */
7068 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7070 switch (i
.tm
.opcode_length
)
7073 if (i
.tm
.base_opcode
& 0xff000000)
7075 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7080 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7082 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7083 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7086 if (prefix
!= REPE_PREFIX_OPCODE
7087 || (i
.prefix
[REP_PREFIX
]
7088 != REPE_PREFIX_OPCODE
))
7089 add_prefix (prefix
);
7092 add_prefix (prefix
);
7101 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7102 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7103 R_X86_64_GOTTPOFF relocation so that linker can safely
7104 perform IE->LE optimization. */
7105 if (x86_elf_abi
== X86_64_X32_ABI
7107 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7108 && i
.prefix
[REX_PREFIX
] == 0)
7109 add_prefix (REX_OPCODE
);
7112 /* The prefix bytes. */
7113 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7115 FRAG_APPEND_1_CHAR (*q
);
7119 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7124 /* REX byte is encoded in VEX prefix. */
7128 FRAG_APPEND_1_CHAR (*q
);
7131 /* There should be no other prefixes for instructions
7136 /* For EVEX instructions i.vrex should become 0 after
7137 build_evex_prefix. For VEX instructions upper 16 registers
7138 aren't available, so VREX should be 0. */
7141 /* Now the VEX prefix. */
7142 p
= frag_more (i
.vex
.length
);
7143 for (j
= 0; j
< i
.vex
.length
; j
++)
7144 p
[j
] = i
.vex
.bytes
[j
];
7147 /* Now the opcode; be careful about word order here! */
7148 if (i
.tm
.opcode_length
== 1)
7150 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7154 switch (i
.tm
.opcode_length
)
7158 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7159 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7163 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7173 /* Put out high byte first: can't use md_number_to_chars! */
7174 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7175 *p
= i
.tm
.base_opcode
& 0xff;
7178 /* Now the modrm byte and sib byte (if present). */
7179 if (i
.tm
.opcode_modifier
.modrm
)
7181 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7184 /* If i.rm.regmem == ESP (4)
7185 && i.rm.mode != (Register mode)
7187 ==> need second modrm byte. */
7188 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7190 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7191 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7193 | i
.sib
.scale
<< 6));
7196 if (i
.disp_operands
)
7197 output_disp (insn_start_frag
, insn_start_off
);
7200 output_imm (insn_start_frag
, insn_start_off
);
7206 pi ("" /*line*/, &i
);
7208 #endif /* DEBUG386 */
7211 /* Return the size of the displacement operand N. */
7214 disp_size (unsigned int n
)
7218 /* Vec_Disp8 has to be 8bit. */
7219 if (i
.types
[n
].bitfield
.vec_disp8
)
7221 else if (i
.types
[n
].bitfield
.disp64
)
7223 else if (i
.types
[n
].bitfield
.disp8
)
7225 else if (i
.types
[n
].bitfield
.disp16
)
7230 /* Return the size of the immediate operand N. */
7233 imm_size (unsigned int n
)
7236 if (i
.types
[n
].bitfield
.imm64
)
7238 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7240 else if (i
.types
[n
].bitfield
.imm16
)
7246 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7251 for (n
= 0; n
< i
.operands
; n
++)
7253 if (i
.types
[n
].bitfield
.vec_disp8
7254 || operand_type_check (i
.types
[n
], disp
))
7256 if (i
.op
[n
].disps
->X_op
== O_constant
)
7258 int size
= disp_size (n
);
7259 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7261 if (i
.types
[n
].bitfield
.vec_disp8
)
7263 val
= offset_in_range (val
, size
);
7264 p
= frag_more (size
);
7265 md_number_to_chars (p
, val
, size
);
7269 enum bfd_reloc_code_real reloc_type
;
7270 int size
= disp_size (n
);
7271 int sign
= i
.types
[n
].bitfield
.disp32s
;
7272 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7275 /* We can't have 8 bit displacement here. */
7276 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7278 /* The PC relative address is computed relative
7279 to the instruction boundary, so in case immediate
7280 fields follows, we need to adjust the value. */
7281 if (pcrel
&& i
.imm_operands
)
7286 for (n1
= 0; n1
< i
.operands
; n1
++)
7287 if (operand_type_check (i
.types
[n1
], imm
))
7289 /* Only one immediate is allowed for PC
7290 relative address. */
7291 gas_assert (sz
== 0);
7293 i
.op
[n
].disps
->X_add_number
-= sz
;
7295 /* We should find the immediate. */
7296 gas_assert (sz
!= 0);
7299 p
= frag_more (size
);
7300 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7302 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7303 && (((reloc_type
== BFD_RELOC_32
7304 || reloc_type
== BFD_RELOC_X86_64_32S
7305 || (reloc_type
== BFD_RELOC_64
7307 && (i
.op
[n
].disps
->X_op
== O_symbol
7308 || (i
.op
[n
].disps
->X_op
== O_add
7309 && ((symbol_get_value_expression
7310 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7312 || reloc_type
== BFD_RELOC_32_PCREL
))
7316 if (insn_start_frag
== frag_now
)
7317 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7322 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7323 for (fr
= insn_start_frag
->fr_next
;
7324 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7326 add
+= p
- frag_now
->fr_literal
;
7331 reloc_type
= BFD_RELOC_386_GOTPC
;
7332 i
.op
[n
].imms
->X_add_number
+= add
;
7334 else if (reloc_type
== BFD_RELOC_64
)
7335 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7337 /* Don't do the adjustment for x86-64, as there
7338 the pcrel addressing is relative to the _next_
7339 insn, and that is taken care of in other code. */
7340 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7342 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7343 size
, i
.op
[n
].disps
, pcrel
,
7345 /* Check for "call/jmp *mem", "mov mem, %reg",
7346 "test %reg, mem" and "binop mem, %reg" where binop
7347 is one of adc, add, and, cmp, or, sbb, sub, xor
7348 instructions. Always generate R_386_GOT32X for
7349 "sym*GOT" operand in 32-bit mode. */
7350 if ((generate_relax_relocations
7353 && i
.rm
.regmem
== 5))
7355 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7356 && ((i
.operands
== 1
7357 && i
.tm
.base_opcode
== 0xff
7358 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7360 && (i
.tm
.base_opcode
== 0x8b
7361 || i
.tm
.base_opcode
== 0x85
7362 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7366 fixP
->fx_tcbit
= i
.rex
!= 0;
7368 && (i
.base_reg
->reg_num
== RegRip
7369 || i
.base_reg
->reg_num
== RegEip
))
7370 fixP
->fx_tcbit2
= 1;
7373 fixP
->fx_tcbit2
= 1;
7381 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7386 for (n
= 0; n
< i
.operands
; n
++)
7388 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7389 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7392 if (operand_type_check (i
.types
[n
], imm
))
7394 if (i
.op
[n
].imms
->X_op
== O_constant
)
7396 int size
= imm_size (n
);
7399 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7401 p
= frag_more (size
);
7402 md_number_to_chars (p
, val
, size
);
7406 /* Not absolute_section.
7407 Need a 32-bit fixup (don't support 8bit
7408 non-absolute imms). Try to support other
7410 enum bfd_reloc_code_real reloc_type
;
7411 int size
= imm_size (n
);
7414 if (i
.types
[n
].bitfield
.imm32s
7415 && (i
.suffix
== QWORD_MNEM_SUFFIX
7416 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7421 p
= frag_more (size
);
7422 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7424 /* This is tough to explain. We end up with this one if we
7425 * have operands that look like
7426 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7427 * obtain the absolute address of the GOT, and it is strongly
7428 * preferable from a performance point of view to avoid using
7429 * a runtime relocation for this. The actual sequence of
7430 * instructions often look something like:
7435 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7437 * The call and pop essentially return the absolute address
7438 * of the label .L66 and store it in %ebx. The linker itself
7439 * will ultimately change the first operand of the addl so
7440 * that %ebx points to the GOT, but to keep things simple, the
7441 * .o file must have this operand set so that it generates not
7442 * the absolute address of .L66, but the absolute address of
7443 * itself. This allows the linker itself simply treat a GOTPC
7444 * relocation as asking for a pcrel offset to the GOT to be
7445 * added in, and the addend of the relocation is stored in the
7446 * operand field for the instruction itself.
7448 * Our job here is to fix the operand so that it would add
7449 * the correct offset so that %ebx would point to itself. The
7450 * thing that is tricky is that .-.L66 will point to the
7451 * beginning of the instruction, so we need to further modify
7452 * the operand so that it will point to itself. There are
7453 * other cases where you have something like:
7455 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7457 * and here no correction would be required. Internally in
7458 * the assembler we treat operands of this form as not being
7459 * pcrel since the '.' is explicitly mentioned, and I wonder
7460 * whether it would simplify matters to do it this way. Who
7461 * knows. In earlier versions of the PIC patches, the
7462 * pcrel_adjust field was used to store the correction, but
7463 * since the expression is not pcrel, I felt it would be
7464 * confusing to do it this way. */
7466 if ((reloc_type
== BFD_RELOC_32
7467 || reloc_type
== BFD_RELOC_X86_64_32S
7468 || reloc_type
== BFD_RELOC_64
)
7470 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7471 && (i
.op
[n
].imms
->X_op
== O_symbol
7472 || (i
.op
[n
].imms
->X_op
== O_add
7473 && ((symbol_get_value_expression
7474 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7479 if (insn_start_frag
== frag_now
)
7480 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7485 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7486 for (fr
= insn_start_frag
->fr_next
;
7487 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7489 add
+= p
- frag_now
->fr_literal
;
7493 reloc_type
= BFD_RELOC_386_GOTPC
;
7495 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7497 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7498 i
.op
[n
].imms
->X_add_number
+= add
;
7500 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7501 i
.op
[n
].imms
, 0, reloc_type
);
7507 /* x86_cons_fix_new is called via the expression parsing code when a
7508 reloc is needed. We use this hook to get the correct .got reloc. */
7509 static int cons_sign
= -1;
7512 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7513 expressionS
*exp
, bfd_reloc_code_real_type r
)
7515 r
= reloc (len
, 0, cons_sign
, r
);
7518 if (exp
->X_op
== O_secrel
)
7520 exp
->X_op
= O_symbol
;
7521 r
= BFD_RELOC_32_SECREL
;
7525 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7528 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7529 purpose of the `.dc.a' internal pseudo-op. */
7532 x86_address_bytes (void)
7534 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7536 return stdoutput
->arch_info
->bits_per_address
/ 8;
7539 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7541 # define lex_got(reloc, adjust, types) NULL
7543 /* Parse operands of the form
7544 <symbol>@GOTOFF+<nnn>
7545 and similar .plt or .got references.
7547 If we find one, set up the correct relocation in RELOC and copy the
7548 input string, minus the `@GOTOFF' into a malloc'd buffer for
7549 parsing by the calling routine. Return this buffer, and if ADJUST
7550 is non-null set it to the length of the string we removed from the
7551 input line. Otherwise return NULL. */
7553 lex_got (enum bfd_reloc_code_real
*rel
,
7555 i386_operand_type
*types
)
7557 /* Some of the relocations depend on the size of what field is to
7558 be relocated. But in our callers i386_immediate and i386_displacement
7559 we don't yet know the operand size (this will be set by insn
7560 matching). Hence we record the word32 relocation here,
7561 and adjust the reloc according to the real size in reloc(). */
7562 static const struct {
7565 const enum bfd_reloc_code_real rel
[2];
7566 const i386_operand_type types64
;
7568 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7569 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7571 OPERAND_TYPE_IMM32_64
},
7573 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7574 BFD_RELOC_X86_64_PLTOFF64
},
7575 OPERAND_TYPE_IMM64
},
7576 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7577 BFD_RELOC_X86_64_PLT32
},
7578 OPERAND_TYPE_IMM32_32S_DISP32
},
7579 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7580 BFD_RELOC_X86_64_GOTPLT64
},
7581 OPERAND_TYPE_IMM64_DISP64
},
7582 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7583 BFD_RELOC_X86_64_GOTOFF64
},
7584 OPERAND_TYPE_IMM64_DISP64
},
7585 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7586 BFD_RELOC_X86_64_GOTPCREL
},
7587 OPERAND_TYPE_IMM32_32S_DISP32
},
7588 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7589 BFD_RELOC_X86_64_TLSGD
},
7590 OPERAND_TYPE_IMM32_32S_DISP32
},
7591 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7592 _dummy_first_bfd_reloc_code_real
},
7593 OPERAND_TYPE_NONE
},
7594 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7595 BFD_RELOC_X86_64_TLSLD
},
7596 OPERAND_TYPE_IMM32_32S_DISP32
},
7597 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7598 BFD_RELOC_X86_64_GOTTPOFF
},
7599 OPERAND_TYPE_IMM32_32S_DISP32
},
7600 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7601 BFD_RELOC_X86_64_TPOFF32
},
7602 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7603 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7604 _dummy_first_bfd_reloc_code_real
},
7605 OPERAND_TYPE_NONE
},
7606 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7607 BFD_RELOC_X86_64_DTPOFF32
},
7608 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7609 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7610 _dummy_first_bfd_reloc_code_real
},
7611 OPERAND_TYPE_NONE
},
7612 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7613 _dummy_first_bfd_reloc_code_real
},
7614 OPERAND_TYPE_NONE
},
7615 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7616 BFD_RELOC_X86_64_GOT32
},
7617 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7618 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7619 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7620 OPERAND_TYPE_IMM32_32S_DISP32
},
7621 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7622 BFD_RELOC_X86_64_TLSDESC_CALL
},
7623 OPERAND_TYPE_IMM32_32S_DISP32
},
7628 #if defined (OBJ_MAYBE_ELF)
7633 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7634 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7637 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7639 int len
= gotrel
[j
].len
;
7640 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7642 if (gotrel
[j
].rel
[object_64bit
] != 0)
7645 char *tmpbuf
, *past_reloc
;
7647 *rel
= gotrel
[j
].rel
[object_64bit
];
7651 if (flag_code
!= CODE_64BIT
)
7653 types
->bitfield
.imm32
= 1;
7654 types
->bitfield
.disp32
= 1;
7657 *types
= gotrel
[j
].types64
;
7660 if (j
!= 0 && GOT_symbol
== NULL
)
7661 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7663 /* The length of the first part of our input line. */
7664 first
= cp
- input_line_pointer
;
7666 /* The second part goes from after the reloc token until
7667 (and including) an end_of_line char or comma. */
7668 past_reloc
= cp
+ 1 + len
;
7670 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7672 second
= cp
+ 1 - past_reloc
;
7674 /* Allocate and copy string. The trailing NUL shouldn't
7675 be necessary, but be safe. */
7676 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7677 memcpy (tmpbuf
, input_line_pointer
, first
);
7678 if (second
!= 0 && *past_reloc
!= ' ')
7679 /* Replace the relocation token with ' ', so that
7680 errors like foo@GOTOFF1 will be detected. */
7681 tmpbuf
[first
++] = ' ';
7683 /* Increment length by 1 if the relocation token is
7688 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7689 tmpbuf
[first
+ second
] = '\0';
7693 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7694 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7699 /* Might be a symbol version string. Don't as_bad here. */
7708 /* Parse operands of the form
7709 <symbol>@SECREL32+<nnn>
7711 If we find one, set up the correct relocation in RELOC and copy the
7712 input string, minus the `@SECREL32' into a malloc'd buffer for
7713 parsing by the calling routine. Return this buffer, and if ADJUST
7714 is non-null set it to the length of the string we removed from the
7715 input line. Otherwise return NULL.
7717 This function is copied from the ELF version above adjusted for PE targets. */
7720 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7721 int *adjust ATTRIBUTE_UNUSED
,
7722 i386_operand_type
*types
)
7728 const enum bfd_reloc_code_real rel
[2];
7729 const i386_operand_type types64
;
7733 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7734 BFD_RELOC_32_SECREL
},
7735 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7741 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7742 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7745 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7747 int len
= gotrel
[j
].len
;
7749 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7751 if (gotrel
[j
].rel
[object_64bit
] != 0)
7754 char *tmpbuf
, *past_reloc
;
7756 *rel
= gotrel
[j
].rel
[object_64bit
];
7762 if (flag_code
!= CODE_64BIT
)
7764 types
->bitfield
.imm32
= 1;
7765 types
->bitfield
.disp32
= 1;
7768 *types
= gotrel
[j
].types64
;
7771 /* The length of the first part of our input line. */
7772 first
= cp
- input_line_pointer
;
7774 /* The second part goes from after the reloc token until
7775 (and including) an end_of_line char or comma. */
7776 past_reloc
= cp
+ 1 + len
;
7778 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7780 second
= cp
+ 1 - past_reloc
;
7782 /* Allocate and copy string. The trailing NUL shouldn't
7783 be necessary, but be safe. */
7784 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7785 memcpy (tmpbuf
, input_line_pointer
, first
);
7786 if (second
!= 0 && *past_reloc
!= ' ')
7787 /* Replace the relocation token with ' ', so that
7788 errors like foo@SECLREL321 will be detected. */
7789 tmpbuf
[first
++] = ' ';
7790 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7791 tmpbuf
[first
+ second
] = '\0';
7795 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7796 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7801 /* Might be a symbol version string. Don't as_bad here. */
7807 bfd_reloc_code_real_type
7808 x86_cons (expressionS
*exp
, int size
)
7810 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7812 intel_syntax
= -intel_syntax
;
7815 if (size
== 4 || (object_64bit
&& size
== 8))
7817 /* Handle @GOTOFF and the like in an expression. */
7819 char *gotfree_input_line
;
7822 save
= input_line_pointer
;
7823 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7824 if (gotfree_input_line
)
7825 input_line_pointer
= gotfree_input_line
;
7829 if (gotfree_input_line
)
7831 /* expression () has merrily parsed up to the end of line,
7832 or a comma - in the wrong buffer. Transfer how far
7833 input_line_pointer has moved to the right buffer. */
7834 input_line_pointer
= (save
7835 + (input_line_pointer
- gotfree_input_line
)
7837 free (gotfree_input_line
);
7838 if (exp
->X_op
== O_constant
7839 || exp
->X_op
== O_absent
7840 || exp
->X_op
== O_illegal
7841 || exp
->X_op
== O_register
7842 || exp
->X_op
== O_big
)
7844 char c
= *input_line_pointer
;
7845 *input_line_pointer
= 0;
7846 as_bad (_("missing or invalid expression `%s'"), save
);
7847 *input_line_pointer
= c
;
7854 intel_syntax
= -intel_syntax
;
7857 i386_intel_simplify (exp
);
7863 signed_cons (int size
)
7865 if (flag_code
== CODE_64BIT
)
7873 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7880 if (exp
.X_op
== O_symbol
)
7881 exp
.X_op
= O_secrel
;
7883 emit_expr (&exp
, 4);
7885 while (*input_line_pointer
++ == ',');
7887 input_line_pointer
--;
7888 demand_empty_rest_of_line ();
7892 /* Handle Vector operations. */
7895 check_VecOperations (char *op_string
, char *op_end
)
7897 const reg_entry
*mask
;
7902 && (op_end
== NULL
|| op_string
< op_end
))
7905 if (*op_string
== '{')
7909 /* Check broadcasts. */
7910 if (strncmp (op_string
, "1to", 3) == 0)
7915 goto duplicated_vec_op
;
7918 if (*op_string
== '8')
7919 bcst_type
= BROADCAST_1TO8
;
7920 else if (*op_string
== '4')
7921 bcst_type
= BROADCAST_1TO4
;
7922 else if (*op_string
== '2')
7923 bcst_type
= BROADCAST_1TO2
;
7924 else if (*op_string
== '1'
7925 && *(op_string
+1) == '6')
7927 bcst_type
= BROADCAST_1TO16
;
7932 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7937 broadcast_op
.type
= bcst_type
;
7938 broadcast_op
.operand
= this_operand
;
7939 i
.broadcast
= &broadcast_op
;
7941 /* Check masking operation. */
7942 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7944 /* k0 can't be used for write mask. */
7945 if (mask
->reg_num
== 0)
7947 as_bad (_("`%s' can't be used for write mask"),
7954 mask_op
.mask
= mask
;
7955 mask_op
.zeroing
= 0;
7956 mask_op
.operand
= this_operand
;
7962 goto duplicated_vec_op
;
7964 i
.mask
->mask
= mask
;
7966 /* Only "{z}" is allowed here. No need to check
7967 zeroing mask explicitly. */
7968 if (i
.mask
->operand
!= this_operand
)
7970 as_bad (_("invalid write mask `%s'"), saved
);
7977 /* Check zeroing-flag for masking operation. */
7978 else if (*op_string
== 'z')
7982 mask_op
.mask
= NULL
;
7983 mask_op
.zeroing
= 1;
7984 mask_op
.operand
= this_operand
;
7989 if (i
.mask
->zeroing
)
7992 as_bad (_("duplicated `%s'"), saved
);
7996 i
.mask
->zeroing
= 1;
7998 /* Only "{%k}" is allowed here. No need to check mask
7999 register explicitly. */
8000 if (i
.mask
->operand
!= this_operand
)
8002 as_bad (_("invalid zeroing-masking `%s'"),
8011 goto unknown_vec_op
;
8013 if (*op_string
!= '}')
8015 as_bad (_("missing `}' in `%s'"), saved
);
8022 /* We don't know this one. */
8023 as_bad (_("unknown vector operation: `%s'"), saved
);
8031 i386_immediate (char *imm_start
)
8033 char *save_input_line_pointer
;
8034 char *gotfree_input_line
;
8037 i386_operand_type types
;
8039 operand_type_set (&types
, ~0);
8041 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8043 as_bad (_("at most %d immediate operands are allowed"),
8044 MAX_IMMEDIATE_OPERANDS
);
8048 exp
= &im_expressions
[i
.imm_operands
++];
8049 i
.op
[this_operand
].imms
= exp
;
8051 if (is_space_char (*imm_start
))
8054 save_input_line_pointer
= input_line_pointer
;
8055 input_line_pointer
= imm_start
;
8057 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8058 if (gotfree_input_line
)
8059 input_line_pointer
= gotfree_input_line
;
8061 exp_seg
= expression (exp
);
8065 /* Handle vector operations. */
8066 if (*input_line_pointer
== '{')
8068 input_line_pointer
= check_VecOperations (input_line_pointer
,
8070 if (input_line_pointer
== NULL
)
8074 if (*input_line_pointer
)
8075 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8077 input_line_pointer
= save_input_line_pointer
;
8078 if (gotfree_input_line
)
8080 free (gotfree_input_line
);
8082 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8083 exp
->X_op
= O_illegal
;
8086 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8090 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8091 i386_operand_type types
, const char *imm_start
)
8093 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8096 as_bad (_("missing or invalid immediate expression `%s'"),
8100 else if (exp
->X_op
== O_constant
)
8102 /* Size it properly later. */
8103 i
.types
[this_operand
].bitfield
.imm64
= 1;
8104 /* If not 64bit, sign extend val. */
8105 if (flag_code
!= CODE_64BIT
8106 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8108 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8110 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8111 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8112 && exp_seg
!= absolute_section
8113 && exp_seg
!= text_section
8114 && exp_seg
!= data_section
8115 && exp_seg
!= bss_section
8116 && exp_seg
!= undefined_section
8117 && !bfd_is_com_section (exp_seg
))
8119 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8123 else if (!intel_syntax
&& exp_seg
== reg_section
)
8126 as_bad (_("illegal immediate register operand %s"), imm_start
);
8131 /* This is an address. The size of the address will be
8132 determined later, depending on destination register,
8133 suffix, or the default for the section. */
8134 i
.types
[this_operand
].bitfield
.imm8
= 1;
8135 i
.types
[this_operand
].bitfield
.imm16
= 1;
8136 i
.types
[this_operand
].bitfield
.imm32
= 1;
8137 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8138 i
.types
[this_operand
].bitfield
.imm64
= 1;
8139 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8147 i386_scale (char *scale
)
8150 char *save
= input_line_pointer
;
8152 input_line_pointer
= scale
;
8153 val
= get_absolute_expression ();
8158 i
.log2_scale_factor
= 0;
8161 i
.log2_scale_factor
= 1;
8164 i
.log2_scale_factor
= 2;
8167 i
.log2_scale_factor
= 3;
8171 char sep
= *input_line_pointer
;
8173 *input_line_pointer
= '\0';
8174 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8176 *input_line_pointer
= sep
;
8177 input_line_pointer
= save
;
8181 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8183 as_warn (_("scale factor of %d without an index register"),
8184 1 << i
.log2_scale_factor
);
8185 i
.log2_scale_factor
= 0;
8187 scale
= input_line_pointer
;
8188 input_line_pointer
= save
;
8193 i386_displacement (char *disp_start
, char *disp_end
)
8197 char *save_input_line_pointer
;
8198 char *gotfree_input_line
;
8200 i386_operand_type bigdisp
, types
= anydisp
;
8203 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8205 as_bad (_("at most %d displacement operands are allowed"),
8206 MAX_MEMORY_OPERANDS
);
8210 operand_type_set (&bigdisp
, 0);
8211 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8212 || (!current_templates
->start
->opcode_modifier
.jump
8213 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8215 bigdisp
.bitfield
.disp32
= 1;
8216 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8217 if (flag_code
== CODE_64BIT
)
8221 bigdisp
.bitfield
.disp32s
= 1;
8222 bigdisp
.bitfield
.disp64
= 1;
8225 else if ((flag_code
== CODE_16BIT
) ^ override
)
8227 bigdisp
.bitfield
.disp32
= 0;
8228 bigdisp
.bitfield
.disp16
= 1;
8233 /* For PC-relative branches, the width of the displacement
8234 is dependent upon data size, not address size. */
8235 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8236 if (flag_code
== CODE_64BIT
)
8238 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8239 bigdisp
.bitfield
.disp16
= 1;
8242 bigdisp
.bitfield
.disp32
= 1;
8243 bigdisp
.bitfield
.disp32s
= 1;
8249 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8251 : LONG_MNEM_SUFFIX
));
8252 bigdisp
.bitfield
.disp32
= 1;
8253 if ((flag_code
== CODE_16BIT
) ^ override
)
8255 bigdisp
.bitfield
.disp32
= 0;
8256 bigdisp
.bitfield
.disp16
= 1;
8260 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8263 exp
= &disp_expressions
[i
.disp_operands
];
8264 i
.op
[this_operand
].disps
= exp
;
8266 save_input_line_pointer
= input_line_pointer
;
8267 input_line_pointer
= disp_start
;
8268 END_STRING_AND_SAVE (disp_end
);
8270 #ifndef GCC_ASM_O_HACK
8271 #define GCC_ASM_O_HACK 0
8274 END_STRING_AND_SAVE (disp_end
+ 1);
8275 if (i
.types
[this_operand
].bitfield
.baseIndex
8276 && displacement_string_end
[-1] == '+')
8278 /* This hack is to avoid a warning when using the "o"
8279 constraint within gcc asm statements.
8282 #define _set_tssldt_desc(n,addr,limit,type) \
8283 __asm__ __volatile__ ( \
8285 "movw %w1,2+%0\n\t" \
8287 "movb %b1,4+%0\n\t" \
8288 "movb %4,5+%0\n\t" \
8289 "movb $0,6+%0\n\t" \
8290 "movb %h1,7+%0\n\t" \
8292 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8294 This works great except that the output assembler ends
8295 up looking a bit weird if it turns out that there is
8296 no offset. You end up producing code that looks like:
8309 So here we provide the missing zero. */
8311 *displacement_string_end
= '0';
8314 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8315 if (gotfree_input_line
)
8316 input_line_pointer
= gotfree_input_line
;
8318 exp_seg
= expression (exp
);
8321 if (*input_line_pointer
)
8322 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8324 RESTORE_END_STRING (disp_end
+ 1);
8326 input_line_pointer
= save_input_line_pointer
;
8327 if (gotfree_input_line
)
8329 free (gotfree_input_line
);
8331 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8332 exp
->X_op
= O_illegal
;
8335 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8337 RESTORE_END_STRING (disp_end
);
8343 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8344 i386_operand_type types
, const char *disp_start
)
8346 i386_operand_type bigdisp
;
8349 /* We do this to make sure that the section symbol is in
8350 the symbol table. We will ultimately change the relocation
8351 to be relative to the beginning of the section. */
8352 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8353 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8354 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8356 if (exp
->X_op
!= O_symbol
)
8359 if (S_IS_LOCAL (exp
->X_add_symbol
)
8360 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8361 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8362 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8363 exp
->X_op
= O_subtract
;
8364 exp
->X_op_symbol
= GOT_symbol
;
8365 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8366 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8367 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8368 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8370 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8373 else if (exp
->X_op
== O_absent
8374 || exp
->X_op
== O_illegal
8375 || exp
->X_op
== O_big
)
8378 as_bad (_("missing or invalid displacement expression `%s'"),
8383 else if (flag_code
== CODE_64BIT
8384 && !i
.prefix
[ADDR_PREFIX
]
8385 && exp
->X_op
== O_constant
)
8387 /* Since displacement is signed extended to 64bit, don't allow
8388 disp32 and turn off disp32s if they are out of range. */
8389 i
.types
[this_operand
].bitfield
.disp32
= 0;
8390 if (!fits_in_signed_long (exp
->X_add_number
))
8392 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8393 if (i
.types
[this_operand
].bitfield
.baseindex
)
8395 as_bad (_("0x%lx out range of signed 32bit displacement"),
8396 (long) exp
->X_add_number
);
8402 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8403 else if (exp
->X_op
!= O_constant
8404 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8405 && exp_seg
!= absolute_section
8406 && exp_seg
!= text_section
8407 && exp_seg
!= data_section
8408 && exp_seg
!= bss_section
8409 && exp_seg
!= undefined_section
8410 && !bfd_is_com_section (exp_seg
))
8412 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8417 /* Check if this is a displacement only operand. */
8418 bigdisp
= i
.types
[this_operand
];
8419 bigdisp
.bitfield
.disp8
= 0;
8420 bigdisp
.bitfield
.disp16
= 0;
8421 bigdisp
.bitfield
.disp32
= 0;
8422 bigdisp
.bitfield
.disp32s
= 0;
8423 bigdisp
.bitfield
.disp64
= 0;
8424 if (operand_type_all_zero (&bigdisp
))
8425 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8431 /* Make sure the memory operand we've been dealt is valid.
8432 Return 1 on success, 0 on a failure. */
8435 i386_index_check (const char *operand_string
)
8437 const char *kind
= "base/index";
8438 enum flag_code addr_mode
;
8440 if (i
.prefix
[ADDR_PREFIX
])
8441 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8444 addr_mode
= flag_code
;
8446 #if INFER_ADDR_PREFIX
8447 if (i
.mem_operands
== 0)
8449 /* Infer address prefix from the first memory operand. */
8450 const reg_entry
*addr_reg
= i
.base_reg
;
8452 if (addr_reg
== NULL
)
8453 addr_reg
= i
.index_reg
;
8457 if (addr_reg
->reg_num
== RegEip
8458 || addr_reg
->reg_num
== RegEiz
8459 || addr_reg
->reg_type
.bitfield
.reg32
)
8460 addr_mode
= CODE_32BIT
;
8461 else if (flag_code
!= CODE_64BIT
8462 && addr_reg
->reg_type
.bitfield
.reg16
)
8463 addr_mode
= CODE_16BIT
;
8465 if (addr_mode
!= flag_code
)
8467 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8469 /* Change the size of any displacement too. At most one
8470 of Disp16 or Disp32 is set.
8471 FIXME. There doesn't seem to be any real need for
8472 separate Disp16 and Disp32 flags. The same goes for
8473 Imm16 and Imm32. Removing them would probably clean
8474 up the code quite a lot. */
8475 if (flag_code
!= CODE_64BIT
8476 && (i
.types
[this_operand
].bitfield
.disp16
8477 || i
.types
[this_operand
].bitfield
.disp32
))
8478 i
.types
[this_operand
]
8479 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8486 if (current_templates
->start
->opcode_modifier
.isstring
8487 && !current_templates
->start
->opcode_modifier
.immext
8488 && (current_templates
->end
[-1].opcode_modifier
.isstring
8491 /* Memory operands of string insns are special in that they only allow
8492 a single register (rDI, rSI, or rBX) as their memory address. */
8493 const reg_entry
*expected_reg
;
8494 static const char *di_si
[][2] =
8500 static const char *bx
[] = { "ebx", "bx", "rbx" };
8502 kind
= "string address";
8504 if (current_templates
->start
->opcode_modifier
.w
)
8506 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8508 if (!type
.bitfield
.baseindex
8509 || ((!i
.mem_operands
!= !intel_syntax
)
8510 && current_templates
->end
[-1].operand_types
[1]
8511 .bitfield
.baseindex
))
8512 type
= current_templates
->end
[-1].operand_types
[1];
8513 expected_reg
= hash_find (reg_hash
,
8514 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8518 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8520 if (i
.base_reg
!= expected_reg
8522 || operand_type_check (i
.types
[this_operand
], disp
))
8524 /* The second memory operand must have the same size as
8528 && !((addr_mode
== CODE_64BIT
8529 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8530 || (addr_mode
== CODE_32BIT
8531 ? i
.base_reg
->reg_type
.bitfield
.reg32
8532 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8535 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8537 intel_syntax
? '[' : '(',
8539 expected_reg
->reg_name
,
8540 intel_syntax
? ']' : ')');
8547 as_bad (_("`%s' is not a valid %s expression"),
8548 operand_string
, kind
);
8553 if (addr_mode
!= CODE_16BIT
)
8555 /* 32-bit/64-bit checks. */
8557 && (addr_mode
== CODE_64BIT
8558 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8559 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8561 || (i
.base_reg
->reg_num
8562 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8564 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8565 && !i
.index_reg
->reg_type
.bitfield
.regymm
8566 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8567 && ((addr_mode
== CODE_64BIT
8568 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8569 || i
.index_reg
->reg_num
== RegRiz
)
8570 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8571 || i
.index_reg
->reg_num
== RegEiz
))
8572 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8577 /* 16-bit checks. */
8579 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8580 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8582 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8583 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8585 && i
.base_reg
->reg_num
< 6
8586 && i
.index_reg
->reg_num
>= 6
8587 && i
.log2_scale_factor
== 0))))
8594 /* Handle vector immediates. */
8597 RC_SAE_immediate (const char *imm_start
)
8599 unsigned int match_found
, j
;
8600 const char *pstr
= imm_start
;
8608 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8610 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8614 rc_op
.type
= RC_NamesTable
[j
].type
;
8615 rc_op
.operand
= this_operand
;
8616 i
.rounding
= &rc_op
;
8620 as_bad (_("duplicated `%s'"), imm_start
);
8623 pstr
+= RC_NamesTable
[j
].len
;
8633 as_bad (_("Missing '}': '%s'"), imm_start
);
8636 /* RC/SAE immediate string should contain nothing more. */;
8639 as_bad (_("Junk after '}': '%s'"), imm_start
);
8643 exp
= &im_expressions
[i
.imm_operands
++];
8644 i
.op
[this_operand
].imms
= exp
;
8646 exp
->X_op
= O_constant
;
8647 exp
->X_add_number
= 0;
8648 exp
->X_add_symbol
= (symbolS
*) 0;
8649 exp
->X_op_symbol
= (symbolS
*) 0;
8651 i
.types
[this_operand
].bitfield
.imm8
= 1;
8655 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8659 i386_att_operand (char *operand_string
)
8663 char *op_string
= operand_string
;
8665 if (is_space_char (*op_string
))
8668 /* We check for an absolute prefix (differentiating,
8669 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8670 if (*op_string
== ABSOLUTE_PREFIX
)
8673 if (is_space_char (*op_string
))
8675 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8678 /* Check if operand is a register. */
8679 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8681 i386_operand_type temp
;
8683 /* Check for a segment override by searching for ':' after a
8684 segment register. */
8686 if (is_space_char (*op_string
))
8688 if (*op_string
== ':'
8689 && (r
->reg_type
.bitfield
.sreg2
8690 || r
->reg_type
.bitfield
.sreg3
))
8695 i
.seg
[i
.mem_operands
] = &es
;
8698 i
.seg
[i
.mem_operands
] = &cs
;
8701 i
.seg
[i
.mem_operands
] = &ss
;
8704 i
.seg
[i
.mem_operands
] = &ds
;
8707 i
.seg
[i
.mem_operands
] = &fs
;
8710 i
.seg
[i
.mem_operands
] = &gs
;
8714 /* Skip the ':' and whitespace. */
8716 if (is_space_char (*op_string
))
8719 if (!is_digit_char (*op_string
)
8720 && !is_identifier_char (*op_string
)
8721 && *op_string
!= '('
8722 && *op_string
!= ABSOLUTE_PREFIX
)
8724 as_bad (_("bad memory operand `%s'"), op_string
);
8727 /* Handle case of %es:*foo. */
8728 if (*op_string
== ABSOLUTE_PREFIX
)
8731 if (is_space_char (*op_string
))
8733 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8735 goto do_memory_reference
;
8738 /* Handle vector operations. */
8739 if (*op_string
== '{')
8741 op_string
= check_VecOperations (op_string
, NULL
);
8742 if (op_string
== NULL
)
8748 as_bad (_("junk `%s' after register"), op_string
);
8752 temp
.bitfield
.baseindex
= 0;
8753 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8755 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8756 i
.op
[this_operand
].regs
= r
;
8759 else if (*op_string
== REGISTER_PREFIX
)
8761 as_bad (_("bad register name `%s'"), op_string
);
8764 else if (*op_string
== IMMEDIATE_PREFIX
)
8767 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8769 as_bad (_("immediate operand illegal with absolute jump"));
8772 if (!i386_immediate (op_string
))
8775 else if (RC_SAE_immediate (operand_string
))
8777 /* If it is a RC or SAE immediate, do nothing. */
8780 else if (is_digit_char (*op_string
)
8781 || is_identifier_char (*op_string
)
8782 || *op_string
== '"'
8783 || *op_string
== '(')
8785 /* This is a memory reference of some sort. */
8788 /* Start and end of displacement string expression (if found). */
8789 char *displacement_string_start
;
8790 char *displacement_string_end
;
8793 do_memory_reference
:
8794 if ((i
.mem_operands
== 1
8795 && !current_templates
->start
->opcode_modifier
.isstring
)
8796 || i
.mem_operands
== 2)
8798 as_bad (_("too many memory references for `%s'"),
8799 current_templates
->start
->name
);
8803 /* Check for base index form. We detect the base index form by
8804 looking for an ')' at the end of the operand, searching
8805 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8807 base_string
= op_string
+ strlen (op_string
);
8809 /* Handle vector operations. */
8810 vop_start
= strchr (op_string
, '{');
8811 if (vop_start
&& vop_start
< base_string
)
8813 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8815 base_string
= vop_start
;
8819 if (is_space_char (*base_string
))
8822 /* If we only have a displacement, set-up for it to be parsed later. */
8823 displacement_string_start
= op_string
;
8824 displacement_string_end
= base_string
+ 1;
8826 if (*base_string
== ')')
8829 unsigned int parens_balanced
= 1;
8830 /* We've already checked that the number of left & right ()'s are
8831 equal, so this loop will not be infinite. */
8835 if (*base_string
== ')')
8837 if (*base_string
== '(')
8840 while (parens_balanced
);
8842 temp_string
= base_string
;
8844 /* Skip past '(' and whitespace. */
8846 if (is_space_char (*base_string
))
8849 if (*base_string
== ','
8850 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8853 displacement_string_end
= temp_string
;
8855 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8859 base_string
= end_op
;
8860 if (is_space_char (*base_string
))
8864 /* There may be an index reg or scale factor here. */
8865 if (*base_string
== ',')
8868 if (is_space_char (*base_string
))
8871 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8874 base_string
= end_op
;
8875 if (is_space_char (*base_string
))
8877 if (*base_string
== ',')
8880 if (is_space_char (*base_string
))
8883 else if (*base_string
!= ')')
8885 as_bad (_("expecting `,' or `)' "
8886 "after index register in `%s'"),
8891 else if (*base_string
== REGISTER_PREFIX
)
8893 end_op
= strchr (base_string
, ',');
8896 as_bad (_("bad register name `%s'"), base_string
);
8900 /* Check for scale factor. */
8901 if (*base_string
!= ')')
8903 char *end_scale
= i386_scale (base_string
);
8908 base_string
= end_scale
;
8909 if (is_space_char (*base_string
))
8911 if (*base_string
!= ')')
8913 as_bad (_("expecting `)' "
8914 "after scale factor in `%s'"),
8919 else if (!i
.index_reg
)
8921 as_bad (_("expecting index register or scale factor "
8922 "after `,'; got '%c'"),
8927 else if (*base_string
!= ')')
8929 as_bad (_("expecting `,' or `)' "
8930 "after base register in `%s'"),
8935 else if (*base_string
== REGISTER_PREFIX
)
8937 end_op
= strchr (base_string
, ',');
8940 as_bad (_("bad register name `%s'"), base_string
);
8945 /* If there's an expression beginning the operand, parse it,
8946 assuming displacement_string_start and
8947 displacement_string_end are meaningful. */
8948 if (displacement_string_start
!= displacement_string_end
)
8950 if (!i386_displacement (displacement_string_start
,
8951 displacement_string_end
))
8955 /* Special case for (%dx) while doing input/output op. */
8957 && operand_type_equal (&i
.base_reg
->reg_type
,
8958 ®16_inoutportreg
)
8960 && i
.log2_scale_factor
== 0
8961 && i
.seg
[i
.mem_operands
] == 0
8962 && !operand_type_check (i
.types
[this_operand
], disp
))
8964 i
.types
[this_operand
] = inoutportreg
;
8968 if (i386_index_check (operand_string
) == 0)
8970 i
.types
[this_operand
].bitfield
.mem
= 1;
8975 /* It's not a memory operand; argh! */
8976 as_bad (_("invalid char %s beginning operand %d `%s'"),
8977 output_invalid (*op_string
),
8982 return 1; /* Normal return. */
8985 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8986 that an rs_machine_dependent frag may reach. */
8989 i386_frag_max_var (fragS
*frag
)
8991 /* The only relaxable frags are for jumps.
8992 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8993 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8994 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8997 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8999 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9001 /* STT_GNU_IFUNC symbol must go through PLT. */
9002 if ((symbol_get_bfdsym (fr_symbol
)->flags
9003 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9006 if (!S_IS_EXTERNAL (fr_symbol
))
9007 /* Symbol may be weak or local. */
9008 return !S_IS_WEAK (fr_symbol
);
9010 /* Global symbols with non-default visibility can't be preempted. */
9011 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9014 if (fr_var
!= NO_RELOC
)
9015 switch ((enum bfd_reloc_code_real
) fr_var
)
9017 case BFD_RELOC_386_PLT32
:
9018 case BFD_RELOC_X86_64_PLT32
:
9019 /* Symbol with PLT relocatin may be preempted. */
9025 /* Global symbols with default visibility in a shared library may be
9026 preempted by another definition. */
9031 /* md_estimate_size_before_relax()
9033 Called just before relax() for rs_machine_dependent frags. The x86
9034 assembler uses these frags to handle variable size jump
9037 Any symbol that is now undefined will not become defined.
9038 Return the correct fr_subtype in the frag.
9039 Return the initial "guess for variable size of frag" to caller.
9040 The guess is actually the growth beyond the fixed part. Whatever
9041 we do to grow the fixed or variable part contributes to our
9045 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9047 /* We've already got fragP->fr_subtype right; all we have to do is
9048 check for un-relaxable symbols. On an ELF system, we can't relax
9049 an externally visible symbol, because it may be overridden by a
9051 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9052 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9054 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9057 #if defined (OBJ_COFF) && defined (TE_PE)
9058 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9059 && S_IS_WEAK (fragP
->fr_symbol
))
9063 /* Symbol is undefined in this segment, or we need to keep a
9064 reloc so that weak symbols can be overridden. */
9065 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9066 enum bfd_reloc_code_real reloc_type
;
9067 unsigned char *opcode
;
9070 if (fragP
->fr_var
!= NO_RELOC
)
9071 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9073 reloc_type
= BFD_RELOC_16_PCREL
;
9075 reloc_type
= BFD_RELOC_32_PCREL
;
9077 old_fr_fix
= fragP
->fr_fix
;
9078 opcode
= (unsigned char *) fragP
->fr_opcode
;
9080 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9083 /* Make jmp (0xeb) a (d)word displacement jump. */
9085 fragP
->fr_fix
+= size
;
9086 fix_new (fragP
, old_fr_fix
, size
,
9088 fragP
->fr_offset
, 1,
9094 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9096 /* Negate the condition, and branch past an
9097 unconditional jump. */
9100 /* Insert an unconditional jump. */
9102 /* We added two extra opcode bytes, and have a two byte
9104 fragP
->fr_fix
+= 2 + 2;
9105 fix_new (fragP
, old_fr_fix
+ 2, 2,
9107 fragP
->fr_offset
, 1,
9114 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9119 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9121 fragP
->fr_offset
, 1,
9123 fixP
->fx_signed
= 1;
9127 /* This changes the byte-displacement jump 0x7N
9128 to the (d)word-displacement jump 0x0f,0x8N. */
9129 opcode
[1] = opcode
[0] + 0x10;
9130 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9131 /* We've added an opcode byte. */
9132 fragP
->fr_fix
+= 1 + size
;
9133 fix_new (fragP
, old_fr_fix
+ 1, size
,
9135 fragP
->fr_offset
, 1,
9140 BAD_CASE (fragP
->fr_subtype
);
9144 return fragP
->fr_fix
- old_fr_fix
;
9147 /* Guess size depending on current relax state. Initially the relax
9148 state will correspond to a short jump and we return 1, because
9149 the variable part of the frag (the branch offset) is one byte
9150 long. However, we can relax a section more than once and in that
9151 case we must either set fr_subtype back to the unrelaxed state,
9152 or return the value for the appropriate branch. */
9153 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9156 /* Called after relax() is finished.
9158 In: Address of frag.
9159 fr_type == rs_machine_dependent.
9160 fr_subtype is what the address relaxed to.
9162 Out: Any fixSs and constants are set up.
9163 Caller will turn frag into a ".space 0". */
9166 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9169 unsigned char *opcode
;
9170 unsigned char *where_to_put_displacement
= NULL
;
9171 offsetT target_address
;
9172 offsetT opcode_address
;
9173 unsigned int extension
= 0;
9174 offsetT displacement_from_opcode_start
;
9176 opcode
= (unsigned char *) fragP
->fr_opcode
;
9178 /* Address we want to reach in file space. */
9179 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9181 /* Address opcode resides at in file space. */
9182 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9184 /* Displacement from opcode start to fill into instruction. */
9185 displacement_from_opcode_start
= target_address
- opcode_address
;
9187 if ((fragP
->fr_subtype
& BIG
) == 0)
9189 /* Don't have to change opcode. */
9190 extension
= 1; /* 1 opcode + 1 displacement */
9191 where_to_put_displacement
= &opcode
[1];
9195 if (no_cond_jump_promotion
9196 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9197 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9198 _("long jump required"));
9200 switch (fragP
->fr_subtype
)
9202 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9203 extension
= 4; /* 1 opcode + 4 displacement */
9205 where_to_put_displacement
= &opcode
[1];
9208 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9209 extension
= 2; /* 1 opcode + 2 displacement */
9211 where_to_put_displacement
= &opcode
[1];
9214 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9215 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9216 extension
= 5; /* 2 opcode + 4 displacement */
9217 opcode
[1] = opcode
[0] + 0x10;
9218 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9219 where_to_put_displacement
= &opcode
[2];
9222 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9223 extension
= 3; /* 2 opcode + 2 displacement */
9224 opcode
[1] = opcode
[0] + 0x10;
9225 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9226 where_to_put_displacement
= &opcode
[2];
9229 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9234 where_to_put_displacement
= &opcode
[3];
9238 BAD_CASE (fragP
->fr_subtype
);
9243 /* If size if less then four we are sure that the operand fits,
9244 but if it's 4, then it could be that the displacement is larger
9246 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9248 && ((addressT
) (displacement_from_opcode_start
- extension
9249 + ((addressT
) 1 << 31))
9250 > (((addressT
) 2 << 31) - 1)))
9252 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9253 _("jump target out of range"));
9254 /* Make us emit 0. */
9255 displacement_from_opcode_start
= extension
;
9257 /* Now put displacement after opcode. */
9258 md_number_to_chars ((char *) where_to_put_displacement
,
9259 (valueT
) (displacement_from_opcode_start
- extension
),
9260 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9261 fragP
->fr_fix
+= extension
;
9264 /* Apply a fixup (fixP) to segment data, once it has been determined
9265 by our caller that we have all the info we need to fix it up.
9267 Parameter valP is the pointer to the value of the bits.
9269 On the 386, immediates, displacements, and data pointers are all in
9270 the same (little-endian) format, so we don't need to care about which
9274 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9276 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9277 valueT value
= *valP
;
9279 #if !defined (TE_Mach)
9282 switch (fixP
->fx_r_type
)
9288 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9291 case BFD_RELOC_X86_64_32S
:
9292 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9295 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9298 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9303 if (fixP
->fx_addsy
!= NULL
9304 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9305 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9306 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9307 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9308 && !use_rela_relocations
)
9310 /* This is a hack. There should be a better way to handle this.
9311 This covers for the fact that bfd_install_relocation will
9312 subtract the current location (for partial_inplace, PC relative
9313 relocations); see more below. */
9317 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9320 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9322 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9325 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9328 || (symbol_section_p (fixP
->fx_addsy
)
9329 && sym_seg
!= absolute_section
))
9330 && !generic_force_reloc (fixP
))
9332 /* Yes, we add the values in twice. This is because
9333 bfd_install_relocation subtracts them out again. I think
9334 bfd_install_relocation is broken, but I don't dare change
9336 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9340 #if defined (OBJ_COFF) && defined (TE_PE)
9341 /* For some reason, the PE format does not store a
9342 section address offset for a PC relative symbol. */
9343 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9344 || S_IS_WEAK (fixP
->fx_addsy
))
9345 value
+= md_pcrel_from (fixP
);
9348 #if defined (OBJ_COFF) && defined (TE_PE)
9349 if (fixP
->fx_addsy
!= NULL
9350 && S_IS_WEAK (fixP
->fx_addsy
)
9351 /* PR 16858: Do not modify weak function references. */
9352 && ! fixP
->fx_pcrel
)
9354 #if !defined (TE_PEP)
9355 /* For x86 PE weak function symbols are neither PC-relative
9356 nor do they set S_IS_FUNCTION. So the only reliable way
9357 to detect them is to check the flags of their containing
9359 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9360 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9364 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9368 /* Fix a few things - the dynamic linker expects certain values here,
9369 and we must not disappoint it. */
9370 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9371 if (IS_ELF
&& fixP
->fx_addsy
)
9372 switch (fixP
->fx_r_type
)
9374 case BFD_RELOC_386_PLT32
:
9375 case BFD_RELOC_X86_64_PLT32
:
9376 /* Make the jump instruction point to the address of the operand. At
9377 runtime we merely add the offset to the actual PLT entry. */
9381 case BFD_RELOC_386_TLS_GD
:
9382 case BFD_RELOC_386_TLS_LDM
:
9383 case BFD_RELOC_386_TLS_IE_32
:
9384 case BFD_RELOC_386_TLS_IE
:
9385 case BFD_RELOC_386_TLS_GOTIE
:
9386 case BFD_RELOC_386_TLS_GOTDESC
:
9387 case BFD_RELOC_X86_64_TLSGD
:
9388 case BFD_RELOC_X86_64_TLSLD
:
9389 case BFD_RELOC_X86_64_GOTTPOFF
:
9390 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9391 value
= 0; /* Fully resolved at runtime. No addend. */
9393 case BFD_RELOC_386_TLS_LE
:
9394 case BFD_RELOC_386_TLS_LDO_32
:
9395 case BFD_RELOC_386_TLS_LE_32
:
9396 case BFD_RELOC_X86_64_DTPOFF32
:
9397 case BFD_RELOC_X86_64_DTPOFF64
:
9398 case BFD_RELOC_X86_64_TPOFF32
:
9399 case BFD_RELOC_X86_64_TPOFF64
:
9400 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9403 case BFD_RELOC_386_TLS_DESC_CALL
:
9404 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9405 value
= 0; /* Fully resolved at runtime. No addend. */
9406 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9410 case BFD_RELOC_VTABLE_INHERIT
:
9411 case BFD_RELOC_VTABLE_ENTRY
:
9418 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9420 #endif /* !defined (TE_Mach) */
9422 /* Are we finished with this relocation now? */
9423 if (fixP
->fx_addsy
== NULL
)
9425 #if defined (OBJ_COFF) && defined (TE_PE)
9426 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9429 /* Remember value for tc_gen_reloc. */
9430 fixP
->fx_addnumber
= value
;
9431 /* Clear out the frag for now. */
9435 else if (use_rela_relocations
)
9437 fixP
->fx_no_overflow
= 1;
9438 /* Remember value for tc_gen_reloc. */
9439 fixP
->fx_addnumber
= value
;
9443 md_number_to_chars (p
, value
, fixP
->fx_size
);
9447 md_atof (int type
, char *litP
, int *sizeP
)
9449 /* This outputs the LITTLENUMs in REVERSE order;
9450 in accord with the bigendian 386. */
9451 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9454 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9457 output_invalid (int c
)
9460 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9463 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9464 "(0x%x)", (unsigned char) c
);
9465 return output_invalid_buf
;
9468 /* REG_STRING starts *before* REGISTER_PREFIX. */
9470 static const reg_entry
*
9471 parse_real_register (char *reg_string
, char **end_op
)
9473 char *s
= reg_string
;
9475 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9478 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9479 if (*s
== REGISTER_PREFIX
)
9482 if (is_space_char (*s
))
9486 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9488 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9489 return (const reg_entry
*) NULL
;
9493 /* For naked regs, make sure that we are not dealing with an identifier.
9494 This prevents confusing an identifier like `eax_var' with register
9496 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9497 return (const reg_entry
*) NULL
;
9501 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9503 /* Handle floating point regs, allowing spaces in the (i) part. */
9504 if (r
== i386_regtab
/* %st is first entry of table */)
9506 if (is_space_char (*s
))
9511 if (is_space_char (*s
))
9513 if (*s
>= '0' && *s
<= '7')
9517 if (is_space_char (*s
))
9522 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9527 /* We have "%st(" then garbage. */
9528 return (const reg_entry
*) NULL
;
9532 if (r
== NULL
|| allow_pseudo_reg
)
9535 if (operand_type_all_zero (&r
->reg_type
))
9536 return (const reg_entry
*) NULL
;
9538 if ((r
->reg_type
.bitfield
.reg32
9539 || r
->reg_type
.bitfield
.sreg3
9540 || r
->reg_type
.bitfield
.control
9541 || r
->reg_type
.bitfield
.debug
9542 || r
->reg_type
.bitfield
.test
)
9543 && !cpu_arch_flags
.bitfield
.cpui386
)
9544 return (const reg_entry
*) NULL
;
9546 if (r
->reg_type
.bitfield
.floatreg
9547 && !cpu_arch_flags
.bitfield
.cpu8087
9548 && !cpu_arch_flags
.bitfield
.cpu287
9549 && !cpu_arch_flags
.bitfield
.cpu387
)
9550 return (const reg_entry
*) NULL
;
9552 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpuregmmx
)
9553 return (const reg_entry
*) NULL
;
9555 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpuregxmm
)
9556 return (const reg_entry
*) NULL
;
9558 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuregymm
)
9559 return (const reg_entry
*) NULL
;
9561 if (r
->reg_type
.bitfield
.regzmm
&& !cpu_arch_flags
.bitfield
.cpuregzmm
)
9562 return (const reg_entry
*) NULL
;
9564 if (r
->reg_type
.bitfield
.regmask
9565 && !cpu_arch_flags
.bitfield
.cpuregmask
)
9566 return (const reg_entry
*) NULL
;
9568 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9569 if (!allow_index_reg
9570 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9571 return (const reg_entry
*) NULL
;
9573 /* Upper 16 vector register is only available with VREX in 64bit
9575 if ((r
->reg_flags
& RegVRex
))
9577 if (!cpu_arch_flags
.bitfield
.cpuvrex
9578 || flag_code
!= CODE_64BIT
)
9579 return (const reg_entry
*) NULL
;
9584 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9585 || r
->reg_type
.bitfield
.reg64
)
9586 && (!cpu_arch_flags
.bitfield
.cpulm
9587 || !operand_type_equal (&r
->reg_type
, &control
))
9588 && flag_code
!= CODE_64BIT
)
9589 return (const reg_entry
*) NULL
;
9591 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9592 return (const reg_entry
*) NULL
;
9597 /* REG_STRING starts *before* REGISTER_PREFIX. */
9599 static const reg_entry
*
9600 parse_register (char *reg_string
, char **end_op
)
9604 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9605 r
= parse_real_register (reg_string
, end_op
);
9610 char *save
= input_line_pointer
;
9614 input_line_pointer
= reg_string
;
9615 c
= get_symbol_name (®_string
);
9616 symbolP
= symbol_find (reg_string
);
9617 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9619 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9621 know (e
->X_op
== O_register
);
9622 know (e
->X_add_number
>= 0
9623 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9624 r
= i386_regtab
+ e
->X_add_number
;
9625 if ((r
->reg_flags
& RegVRex
))
9627 *end_op
= input_line_pointer
;
9629 *input_line_pointer
= c
;
9630 input_line_pointer
= save
;
9636 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9639 char *end
= input_line_pointer
;
9642 r
= parse_register (name
, &input_line_pointer
);
9643 if (r
&& end
<= input_line_pointer
)
9645 *nextcharP
= *input_line_pointer
;
9646 *input_line_pointer
= 0;
9647 e
->X_op
= O_register
;
9648 e
->X_add_number
= r
- i386_regtab
;
9651 input_line_pointer
= end
;
9653 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9657 md_operand (expressionS
*e
)
9662 switch (*input_line_pointer
)
9664 case REGISTER_PREFIX
:
9665 r
= parse_real_register (input_line_pointer
, &end
);
9668 e
->X_op
= O_register
;
9669 e
->X_add_number
= r
- i386_regtab
;
9670 input_line_pointer
= end
;
9675 gas_assert (intel_syntax
);
9676 end
= input_line_pointer
++;
9678 if (*input_line_pointer
== ']')
9680 ++input_line_pointer
;
9681 e
->X_op_symbol
= make_expr_symbol (e
);
9682 e
->X_add_symbol
= NULL
;
9683 e
->X_add_number
= 0;
9689 input_line_pointer
= end
;
9696 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9697 const char *md_shortopts
= "kVQ:sqn";
9699 const char *md_shortopts
= "qn";
9702 #define OPTION_32 (OPTION_MD_BASE + 0)
9703 #define OPTION_64 (OPTION_MD_BASE + 1)
9704 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9705 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9706 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9707 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9708 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9709 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9710 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9711 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9712 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9713 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9714 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9715 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9716 #define OPTION_X32 (OPTION_MD_BASE + 14)
9717 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9718 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9719 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9720 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9721 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9722 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9723 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9724 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9725 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9726 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9727 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
9729 struct option md_longopts
[] =
9731 {"32", no_argument
, NULL
, OPTION_32
},
9732 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9733 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9734 {"64", no_argument
, NULL
, OPTION_64
},
9736 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9737 {"x32", no_argument
, NULL
, OPTION_X32
},
9738 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
9740 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9741 {"march", required_argument
, NULL
, OPTION_MARCH
},
9742 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9743 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9744 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9745 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9746 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9747 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9748 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9749 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9750 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9751 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9752 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9753 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9754 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9755 # if defined (TE_PE) || defined (TE_PEP)
9756 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9758 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
9759 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
9760 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
9761 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9762 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
9763 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
9764 {NULL
, no_argument
, NULL
, 0}
9766 size_t md_longopts_size
= sizeof (md_longopts
);
9769 md_parse_option (int c
, const char *arg
)
9772 char *arch
, *next
, *saved
;
9777 optimize_align_code
= 0;
9784 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9785 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9786 should be emitted or not. FIXME: Not implemented. */
9790 /* -V: SVR4 argument to print version ID. */
9792 print_version_id ();
9795 /* -k: Ignore for FreeBSD compatibility. */
9800 /* -s: On i386 Solaris, this tells the native assembler to use
9801 .stab instead of .stab.excl. We always use .stab anyhow. */
9804 case OPTION_MSHARED
:
9808 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9809 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9812 const char **list
, **l
;
9814 list
= bfd_target_list ();
9815 for (l
= list
; *l
!= NULL
; l
++)
9816 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9817 || strcmp (*l
, "coff-x86-64") == 0
9818 || strcmp (*l
, "pe-x86-64") == 0
9819 || strcmp (*l
, "pei-x86-64") == 0
9820 || strcmp (*l
, "mach-o-x86-64") == 0)
9822 default_arch
= "x86_64";
9826 as_fatal (_("no compiled in support for x86_64"));
9832 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9836 const char **list
, **l
;
9838 list
= bfd_target_list ();
9839 for (l
= list
; *l
!= NULL
; l
++)
9840 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9842 default_arch
= "x86_64:32";
9846 as_fatal (_("no compiled in support for 32bit x86_64"));
9850 as_fatal (_("32bit x86_64 is only supported for ELF"));
9855 default_arch
= "i386";
9859 #ifdef SVR4_COMMENT_CHARS
9864 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
9866 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9870 i386_comment_chars
= n
;
9876 saved
= xstrdup (arg
);
9878 /* Allow -march=+nosse. */
9884 as_fatal (_("invalid -march= option: `%s'"), arg
);
9885 next
= strchr (arch
, '+');
9888 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9890 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9893 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9896 cpu_arch_name
= cpu_arch
[j
].name
;
9897 cpu_sub_arch_name
= NULL
;
9898 cpu_arch_flags
= cpu_arch
[j
].flags
;
9899 cpu_arch_isa
= cpu_arch
[j
].type
;
9900 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9901 if (!cpu_arch_tune_set
)
9903 cpu_arch_tune
= cpu_arch_isa
;
9904 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9908 else if (*cpu_arch
[j
].name
== '.'
9909 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9911 /* ISA entension. */
9912 i386_cpu_flags flags
;
9914 flags
= cpu_flags_or (cpu_arch_flags
,
9917 if (!valid_iamcu_cpu_flags (&flags
))
9918 as_fatal (_("`%s' isn't valid for Intel MCU"), arch
);
9919 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9921 if (cpu_sub_arch_name
)
9923 char *name
= cpu_sub_arch_name
;
9924 cpu_sub_arch_name
= concat (name
,
9926 (const char *) NULL
);
9930 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9931 cpu_arch_flags
= flags
;
9932 cpu_arch_isa_flags
= flags
;
9938 if (j
>= ARRAY_SIZE (cpu_arch
))
9940 /* Disable an ISA entension. */
9941 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
9942 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
9944 i386_cpu_flags flags
;
9946 flags
= cpu_flags_and_not (cpu_arch_flags
,
9947 cpu_noarch
[j
].flags
);
9948 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9950 if (cpu_sub_arch_name
)
9952 char *name
= cpu_sub_arch_name
;
9953 cpu_sub_arch_name
= concat (arch
,
9954 (const char *) NULL
);
9958 cpu_sub_arch_name
= xstrdup (arch
);
9959 cpu_arch_flags
= flags
;
9960 cpu_arch_isa_flags
= flags
;
9965 if (j
>= ARRAY_SIZE (cpu_noarch
))
9966 j
= ARRAY_SIZE (cpu_arch
);
9969 if (j
>= ARRAY_SIZE (cpu_arch
))
9970 as_fatal (_("invalid -march= option: `%s'"), arg
);
9974 while (next
!= NULL
);
9980 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9981 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9983 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9985 cpu_arch_tune_set
= 1;
9986 cpu_arch_tune
= cpu_arch
[j
].type
;
9987 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9991 if (j
>= ARRAY_SIZE (cpu_arch
))
9992 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9995 case OPTION_MMNEMONIC
:
9996 if (strcasecmp (arg
, "att") == 0)
9998 else if (strcasecmp (arg
, "intel") == 0)
10001 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10004 case OPTION_MSYNTAX
:
10005 if (strcasecmp (arg
, "att") == 0)
10007 else if (strcasecmp (arg
, "intel") == 0)
10010 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10013 case OPTION_MINDEX_REG
:
10014 allow_index_reg
= 1;
10017 case OPTION_MNAKED_REG
:
10018 allow_naked_reg
= 1;
10021 case OPTION_MOLD_GCC
:
10025 case OPTION_MSSE2AVX
:
10029 case OPTION_MSSE_CHECK
:
10030 if (strcasecmp (arg
, "error") == 0)
10031 sse_check
= check_error
;
10032 else if (strcasecmp (arg
, "warning") == 0)
10033 sse_check
= check_warning
;
10034 else if (strcasecmp (arg
, "none") == 0)
10035 sse_check
= check_none
;
10037 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10040 case OPTION_MOPERAND_CHECK
:
10041 if (strcasecmp (arg
, "error") == 0)
10042 operand_check
= check_error
;
10043 else if (strcasecmp (arg
, "warning") == 0)
10044 operand_check
= check_warning
;
10045 else if (strcasecmp (arg
, "none") == 0)
10046 operand_check
= check_none
;
10048 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10051 case OPTION_MAVXSCALAR
:
10052 if (strcasecmp (arg
, "128") == 0)
10053 avxscalar
= vex128
;
10054 else if (strcasecmp (arg
, "256") == 0)
10055 avxscalar
= vex256
;
10057 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10060 case OPTION_MADD_BND_PREFIX
:
10061 add_bnd_prefix
= 1;
10064 case OPTION_MEVEXLIG
:
10065 if (strcmp (arg
, "128") == 0)
10066 evexlig
= evexl128
;
10067 else if (strcmp (arg
, "256") == 0)
10068 evexlig
= evexl256
;
10069 else if (strcmp (arg
, "512") == 0)
10070 evexlig
= evexl512
;
10072 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10075 case OPTION_MEVEXRCIG
:
10076 if (strcmp (arg
, "rne") == 0)
10078 else if (strcmp (arg
, "rd") == 0)
10080 else if (strcmp (arg
, "ru") == 0)
10082 else if (strcmp (arg
, "rz") == 0)
10085 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10088 case OPTION_MEVEXWIG
:
10089 if (strcmp (arg
, "0") == 0)
10091 else if (strcmp (arg
, "1") == 0)
10094 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10097 # if defined (TE_PE) || defined (TE_PEP)
10098 case OPTION_MBIG_OBJ
:
10103 case OPTION_MOMIT_LOCK_PREFIX
:
10104 if (strcasecmp (arg
, "yes") == 0)
10105 omit_lock_prefix
= 1;
10106 else if (strcasecmp (arg
, "no") == 0)
10107 omit_lock_prefix
= 0;
10109 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10112 case OPTION_MFENCE_AS_LOCK_ADD
:
10113 if (strcasecmp (arg
, "yes") == 0)
10115 else if (strcasecmp (arg
, "no") == 0)
10118 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10121 case OPTION_MRELAX_RELOCATIONS
:
10122 if (strcasecmp (arg
, "yes") == 0)
10123 generate_relax_relocations
= 1;
10124 else if (strcasecmp (arg
, "no") == 0)
10125 generate_relax_relocations
= 0;
10127 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10130 case OPTION_MAMD64
:
10134 case OPTION_MINTEL64
:
10144 #define MESSAGE_TEMPLATE \
10148 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10149 int *left_p
, const char *name
, int len
)
10151 int size
= sizeof (MESSAGE_TEMPLATE
);
10152 int left
= *left_p
;
10154 /* Reserve 2 spaces for ", " or ",\0" */
10157 /* Check if there is any room. */
10165 p
= mempcpy (p
, name
, len
);
10169 /* Output the current message now and start a new one. */
10172 fprintf (stream
, "%s\n", message
);
10174 left
= size
- (start
- message
) - len
- 2;
10176 gas_assert (left
>= 0);
10178 p
= mempcpy (p
, name
, len
);
10186 show_arch (FILE *stream
, int ext
, int check
)
10188 static char message
[] = MESSAGE_TEMPLATE
;
10189 char *start
= message
+ 27;
10191 int size
= sizeof (MESSAGE_TEMPLATE
);
10198 left
= size
- (start
- message
);
10199 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10201 /* Should it be skipped? */
10202 if (cpu_arch
[j
].skip
)
10205 name
= cpu_arch
[j
].name
;
10206 len
= cpu_arch
[j
].len
;
10209 /* It is an extension. Skip if we aren't asked to show it. */
10220 /* It is an processor. Skip if we show only extension. */
10223 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10225 /* It is an impossible processor - skip. */
10229 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10232 /* Display disabled extensions. */
10234 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10236 name
= cpu_noarch
[j
].name
;
10237 len
= cpu_noarch
[j
].len
;
10238 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10243 fprintf (stream
, "%s\n", message
);
10247 md_show_usage (FILE *stream
)
10249 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10250 fprintf (stream
, _("\
10252 -V print assembler version number\n\
10255 fprintf (stream
, _("\
10256 -n Do not optimize code alignment\n\
10257 -q quieten some warnings\n"));
10258 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10259 fprintf (stream
, _("\
10262 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10263 || defined (TE_PE) || defined (TE_PEP))
10264 fprintf (stream
, _("\
10265 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10267 #ifdef SVR4_COMMENT_CHARS
10268 fprintf (stream
, _("\
10269 --divide do not treat `/' as a comment character\n"));
10271 fprintf (stream
, _("\
10272 --divide ignored\n"));
10274 fprintf (stream
, _("\
10275 -march=CPU[,+EXTENSION...]\n\
10276 generate code for CPU and EXTENSION, CPU is one of:\n"));
10277 show_arch (stream
, 0, 1);
10278 fprintf (stream
, _("\
10279 EXTENSION is combination of:\n"));
10280 show_arch (stream
, 1, 0);
10281 fprintf (stream
, _("\
10282 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10283 show_arch (stream
, 0, 0);
10284 fprintf (stream
, _("\
10285 -msse2avx encode SSE instructions with VEX prefix\n"));
10286 fprintf (stream
, _("\
10287 -msse-check=[none|error|warning]\n\
10288 check SSE instructions\n"));
10289 fprintf (stream
, _("\
10290 -moperand-check=[none|error|warning]\n\
10291 check operand combinations for validity\n"));
10292 fprintf (stream
, _("\
10293 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10295 fprintf (stream
, _("\
10296 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10298 fprintf (stream
, _("\
10299 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10300 for EVEX.W bit ignored instructions\n"));
10301 fprintf (stream
, _("\
10302 -mevexrcig=[rne|rd|ru|rz]\n\
10303 encode EVEX instructions with specific EVEX.RC value\n\
10304 for SAE-only ignored instructions\n"));
10305 fprintf (stream
, _("\
10306 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10307 fprintf (stream
, _("\
10308 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10309 fprintf (stream
, _("\
10310 -mindex-reg support pseudo index registers\n"));
10311 fprintf (stream
, _("\
10312 -mnaked-reg don't require `%%' prefix for registers\n"));
10313 fprintf (stream
, _("\
10314 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10315 fprintf (stream
, _("\
10316 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10317 fprintf (stream
, _("\
10318 -mshared disable branch optimization for shared code\n"));
10319 # if defined (TE_PE) || defined (TE_PEP)
10320 fprintf (stream
, _("\
10321 -mbig-obj generate big object files\n"));
10323 fprintf (stream
, _("\
10324 -momit-lock-prefix=[no|yes]\n\
10325 strip all lock prefixes\n"));
10326 fprintf (stream
, _("\
10327 -mfence-as-lock-add=[no|yes]\n\
10328 encode lfence, mfence and sfence as\n\
10329 lock addl $0x0, (%%{re}sp)\n"));
10330 fprintf (stream
, _("\
10331 -mrelax-relocations=[no|yes]\n\
10332 generate relax relocations\n"));
10333 fprintf (stream
, _("\
10334 -mamd64 accept only AMD64 ISA\n"));
10335 fprintf (stream
, _("\
10336 -mintel64 accept only Intel64 ISA\n"));
10339 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10340 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10341 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10343 /* Pick the target format to use. */
10346 i386_target_format (void)
10348 if (!strncmp (default_arch
, "x86_64", 6))
10350 update_code_flag (CODE_64BIT
, 1);
10351 if (default_arch
[6] == '\0')
10352 x86_elf_abi
= X86_64_ABI
;
10354 x86_elf_abi
= X86_64_X32_ABI
;
10356 else if (!strcmp (default_arch
, "i386"))
10357 update_code_flag (CODE_32BIT
, 1);
10358 else if (!strcmp (default_arch
, "iamcu"))
10360 update_code_flag (CODE_32BIT
, 1);
10361 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10363 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10364 cpu_arch_name
= "iamcu";
10365 cpu_sub_arch_name
= NULL
;
10366 cpu_arch_flags
= iamcu_flags
;
10367 cpu_arch_isa
= PROCESSOR_IAMCU
;
10368 cpu_arch_isa_flags
= iamcu_flags
;
10369 if (!cpu_arch_tune_set
)
10371 cpu_arch_tune
= cpu_arch_isa
;
10372 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10376 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10380 as_fatal (_("unknown architecture"));
10382 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10383 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10384 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10385 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10387 switch (OUTPUT_FLAVOR
)
10389 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10390 case bfd_target_aout_flavour
:
10391 return AOUT_TARGET_FORMAT
;
10393 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10394 # if defined (TE_PE) || defined (TE_PEP)
10395 case bfd_target_coff_flavour
:
10396 if (flag_code
== CODE_64BIT
)
10397 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10400 # elif defined (TE_GO32)
10401 case bfd_target_coff_flavour
:
10402 return "coff-go32";
10404 case bfd_target_coff_flavour
:
10405 return "coff-i386";
10408 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10409 case bfd_target_elf_flavour
:
10411 const char *format
;
10413 switch (x86_elf_abi
)
10416 format
= ELF_TARGET_FORMAT
;
10419 use_rela_relocations
= 1;
10421 format
= ELF_TARGET_FORMAT64
;
10423 case X86_64_X32_ABI
:
10424 use_rela_relocations
= 1;
10426 disallow_64bit_reloc
= 1;
10427 format
= ELF_TARGET_FORMAT32
;
10430 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10432 if (x86_elf_abi
!= X86_64_ABI
)
10433 as_fatal (_("Intel L1OM is 64bit only"));
10434 return ELF_TARGET_L1OM_FORMAT
;
10436 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10438 if (x86_elf_abi
!= X86_64_ABI
)
10439 as_fatal (_("Intel K1OM is 64bit only"));
10440 return ELF_TARGET_K1OM_FORMAT
;
10442 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10444 if (x86_elf_abi
!= I386_ABI
)
10445 as_fatal (_("Intel MCU is 32bit only"));
10446 return ELF_TARGET_IAMCU_FORMAT
;
10452 #if defined (OBJ_MACH_O)
10453 case bfd_target_mach_o_flavour
:
10454 if (flag_code
== CODE_64BIT
)
10456 use_rela_relocations
= 1;
10458 return "mach-o-x86-64";
10461 return "mach-o-i386";
10469 #endif /* OBJ_MAYBE_ more than one */
10472 md_undefined_symbol (char *name
)
10474 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10475 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10476 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10477 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10481 if (symbol_find (name
))
10482 as_bad (_("GOT already in symbol table"));
10483 GOT_symbol
= symbol_new (name
, undefined_section
,
10484 (valueT
) 0, &zero_address_frag
);
10491 /* Round up a section size to the appropriate boundary. */
10494 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10496 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10497 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10499 /* For a.out, force the section size to be aligned. If we don't do
10500 this, BFD will align it for us, but it will not write out the
10501 final bytes of the section. This may be a bug in BFD, but it is
10502 easier to fix it here since that is how the other a.out targets
10506 align
= bfd_get_section_alignment (stdoutput
, segment
);
10507 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
10514 /* On the i386, PC-relative offsets are relative to the start of the
10515 next instruction. That is, the address of the offset, plus its
10516 size, since the offset is always the last part of the insn. */
10519 md_pcrel_from (fixS
*fixP
)
10521 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10527 s_bss (int ignore ATTRIBUTE_UNUSED
)
10531 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10533 obj_elf_section_change_hook ();
10535 temp
= get_absolute_expression ();
10536 subseg_set (bss_section
, (subsegT
) temp
);
10537 demand_empty_rest_of_line ();
10543 i386_validate_fix (fixS
*fixp
)
10545 if (fixp
->fx_subsy
)
10547 if (fixp
->fx_subsy
== GOT_symbol
)
10549 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10553 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10554 if (fixp
->fx_tcbit2
)
10555 fixp
->fx_r_type
= (fixp
->fx_tcbit
10556 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10557 : BFD_RELOC_X86_64_GOTPCRELX
);
10560 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10565 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10567 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10569 fixp
->fx_subsy
= 0;
10572 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10573 else if (!object_64bit
)
10575 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
10576 && fixp
->fx_tcbit2
)
10577 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
10583 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10586 bfd_reloc_code_real_type code
;
10588 switch (fixp
->fx_r_type
)
10590 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10591 case BFD_RELOC_SIZE32
:
10592 case BFD_RELOC_SIZE64
:
10593 if (S_IS_DEFINED (fixp
->fx_addsy
)
10594 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10596 /* Resolve size relocation against local symbol to size of
10597 the symbol plus addend. */
10598 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10599 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10600 && !fits_in_unsigned_long (value
))
10601 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10602 _("symbol size computation overflow"));
10603 fixp
->fx_addsy
= NULL
;
10604 fixp
->fx_subsy
= NULL
;
10605 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10610 case BFD_RELOC_X86_64_PLT32
:
10611 case BFD_RELOC_X86_64_GOT32
:
10612 case BFD_RELOC_X86_64_GOTPCREL
:
10613 case BFD_RELOC_X86_64_GOTPCRELX
:
10614 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10615 case BFD_RELOC_386_PLT32
:
10616 case BFD_RELOC_386_GOT32
:
10617 case BFD_RELOC_386_GOT32X
:
10618 case BFD_RELOC_386_GOTOFF
:
10619 case BFD_RELOC_386_GOTPC
:
10620 case BFD_RELOC_386_TLS_GD
:
10621 case BFD_RELOC_386_TLS_LDM
:
10622 case BFD_RELOC_386_TLS_LDO_32
:
10623 case BFD_RELOC_386_TLS_IE_32
:
10624 case BFD_RELOC_386_TLS_IE
:
10625 case BFD_RELOC_386_TLS_GOTIE
:
10626 case BFD_RELOC_386_TLS_LE_32
:
10627 case BFD_RELOC_386_TLS_LE
:
10628 case BFD_RELOC_386_TLS_GOTDESC
:
10629 case BFD_RELOC_386_TLS_DESC_CALL
:
10630 case BFD_RELOC_X86_64_TLSGD
:
10631 case BFD_RELOC_X86_64_TLSLD
:
10632 case BFD_RELOC_X86_64_DTPOFF32
:
10633 case BFD_RELOC_X86_64_DTPOFF64
:
10634 case BFD_RELOC_X86_64_GOTTPOFF
:
10635 case BFD_RELOC_X86_64_TPOFF32
:
10636 case BFD_RELOC_X86_64_TPOFF64
:
10637 case BFD_RELOC_X86_64_GOTOFF64
:
10638 case BFD_RELOC_X86_64_GOTPC32
:
10639 case BFD_RELOC_X86_64_GOT64
:
10640 case BFD_RELOC_X86_64_GOTPCREL64
:
10641 case BFD_RELOC_X86_64_GOTPC64
:
10642 case BFD_RELOC_X86_64_GOTPLT64
:
10643 case BFD_RELOC_X86_64_PLTOFF64
:
10644 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10645 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10646 case BFD_RELOC_RVA
:
10647 case BFD_RELOC_VTABLE_ENTRY
:
10648 case BFD_RELOC_VTABLE_INHERIT
:
10650 case BFD_RELOC_32_SECREL
:
10652 code
= fixp
->fx_r_type
;
10654 case BFD_RELOC_X86_64_32S
:
10655 if (!fixp
->fx_pcrel
)
10657 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10658 code
= fixp
->fx_r_type
;
10662 if (fixp
->fx_pcrel
)
10664 switch (fixp
->fx_size
)
10667 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10668 _("can not do %d byte pc-relative relocation"),
10670 code
= BFD_RELOC_32_PCREL
;
10672 case 1: code
= BFD_RELOC_8_PCREL
; break;
10673 case 2: code
= BFD_RELOC_16_PCREL
; break;
10674 case 4: code
= BFD_RELOC_32_PCREL
; break;
10676 case 8: code
= BFD_RELOC_64_PCREL
; break;
10682 switch (fixp
->fx_size
)
10685 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10686 _("can not do %d byte relocation"),
10688 code
= BFD_RELOC_32
;
10690 case 1: code
= BFD_RELOC_8
; break;
10691 case 2: code
= BFD_RELOC_16
; break;
10692 case 4: code
= BFD_RELOC_32
; break;
10694 case 8: code
= BFD_RELOC_64
; break;
10701 if ((code
== BFD_RELOC_32
10702 || code
== BFD_RELOC_32_PCREL
10703 || code
== BFD_RELOC_X86_64_32S
)
10705 && fixp
->fx_addsy
== GOT_symbol
)
10708 code
= BFD_RELOC_386_GOTPC
;
10710 code
= BFD_RELOC_X86_64_GOTPC32
;
10712 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10714 && fixp
->fx_addsy
== GOT_symbol
)
10716 code
= BFD_RELOC_X86_64_GOTPC64
;
10719 rel
= XNEW (arelent
);
10720 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
10721 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10723 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10725 if (!use_rela_relocations
)
10727 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10728 vtable entry to be used in the relocation's section offset. */
10729 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10730 rel
->address
= fixp
->fx_offset
;
10731 #if defined (OBJ_COFF) && defined (TE_PE)
10732 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10733 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10738 /* Use the rela in 64bit mode. */
10741 if (disallow_64bit_reloc
)
10744 case BFD_RELOC_X86_64_DTPOFF64
:
10745 case BFD_RELOC_X86_64_TPOFF64
:
10746 case BFD_RELOC_64_PCREL
:
10747 case BFD_RELOC_X86_64_GOTOFF64
:
10748 case BFD_RELOC_X86_64_GOT64
:
10749 case BFD_RELOC_X86_64_GOTPCREL64
:
10750 case BFD_RELOC_X86_64_GOTPC64
:
10751 case BFD_RELOC_X86_64_GOTPLT64
:
10752 case BFD_RELOC_X86_64_PLTOFF64
:
10753 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10754 _("cannot represent relocation type %s in x32 mode"),
10755 bfd_get_reloc_code_name (code
));
10761 if (!fixp
->fx_pcrel
)
10762 rel
->addend
= fixp
->fx_offset
;
10766 case BFD_RELOC_X86_64_PLT32
:
10767 case BFD_RELOC_X86_64_GOT32
:
10768 case BFD_RELOC_X86_64_GOTPCREL
:
10769 case BFD_RELOC_X86_64_GOTPCRELX
:
10770 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10771 case BFD_RELOC_X86_64_TLSGD
:
10772 case BFD_RELOC_X86_64_TLSLD
:
10773 case BFD_RELOC_X86_64_GOTTPOFF
:
10774 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10775 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10776 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10779 rel
->addend
= (section
->vma
10781 + fixp
->fx_addnumber
10782 + md_pcrel_from (fixp
));
10787 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10788 if (rel
->howto
== NULL
)
10790 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10791 _("cannot represent relocation type %s"),
10792 bfd_get_reloc_code_name (code
));
10793 /* Set howto to a garbage value so that we can keep going. */
10794 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10795 gas_assert (rel
->howto
!= NULL
);
10801 #include "tc-i386-intel.c"
10804 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10806 int saved_naked_reg
;
10807 char saved_register_dot
;
10809 saved_naked_reg
= allow_naked_reg
;
10810 allow_naked_reg
= 1;
10811 saved_register_dot
= register_chars
['.'];
10812 register_chars
['.'] = '.';
10813 allow_pseudo_reg
= 1;
10814 expression_and_evaluate (exp
);
10815 allow_pseudo_reg
= 0;
10816 register_chars
['.'] = saved_register_dot
;
10817 allow_naked_reg
= saved_naked_reg
;
10819 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10821 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10823 exp
->X_op
= O_constant
;
10824 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10825 .dw2_regnum
[flag_code
>> 1];
10828 exp
->X_op
= O_illegal
;
10833 tc_x86_frame_initial_instructions (void)
10835 static unsigned int sp_regno
[2];
10837 if (!sp_regno
[flag_code
>> 1])
10839 char *saved_input
= input_line_pointer
;
10840 char sp
[][4] = {"esp", "rsp"};
10843 input_line_pointer
= sp
[flag_code
>> 1];
10844 tc_x86_parse_to_dw2regnum (&exp
);
10845 gas_assert (exp
.X_op
== O_constant
);
10846 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10847 input_line_pointer
= saved_input
;
10850 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10851 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10855 x86_dwarf2_addr_size (void)
10857 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10858 if (x86_elf_abi
== X86_64_X32_ABI
)
10861 return bfd_arch_bits_per_address (stdoutput
) / 8;
10865 i386_elf_section_type (const char *str
, size_t len
)
10867 if (flag_code
== CODE_64BIT
10868 && len
== sizeof ("unwind") - 1
10869 && strncmp (str
, "unwind", 6) == 0)
10870 return SHT_X86_64_UNWIND
;
10877 i386_solaris_fix_up_eh_frame (segT sec
)
10879 if (flag_code
== CODE_64BIT
)
10880 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10886 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10890 exp
.X_op
= O_secrel
;
10891 exp
.X_add_symbol
= symbol
;
10892 exp
.X_add_number
= 0;
10893 emit_expr (&exp
, size
);
10897 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10898 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10901 x86_64_section_letter (int letter
, const char **ptr_msg
)
10903 if (flag_code
== CODE_64BIT
)
10906 return SHF_X86_64_LARGE
;
10908 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10911 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10916 x86_64_section_word (char *str
, size_t len
)
10918 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10919 return SHF_X86_64_LARGE
;
10925 handle_large_common (int small ATTRIBUTE_UNUSED
)
10927 if (flag_code
!= CODE_64BIT
)
10929 s_comm_internal (0, elf_common_parse
);
10930 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10934 static segT lbss_section
;
10935 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10936 asection
*saved_bss_section
= bss_section
;
10938 if (lbss_section
== NULL
)
10940 flagword applicable
;
10941 segT seg
= now_seg
;
10942 subsegT subseg
= now_subseg
;
10944 /* The .lbss section is for local .largecomm symbols. */
10945 lbss_section
= subseg_new (".lbss", 0);
10946 applicable
= bfd_applicable_section_flags (stdoutput
);
10947 bfd_set_section_flags (stdoutput
, lbss_section
,
10948 applicable
& SEC_ALLOC
);
10949 seg_info (lbss_section
)->bss
= 1;
10951 subseg_set (seg
, subseg
);
10954 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10955 bss_section
= lbss_section
;
10957 s_comm_internal (0, elf_common_parse
);
10959 elf_com_section_ptr
= saved_com_section_ptr
;
10960 bss_section
= saved_bss_section
;
10963 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */