1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static INLINE
unsigned int mode_from_disp_size
PARAMS ((unsigned int));
67 static INLINE
int fits_in_signed_byte
PARAMS ((offsetT
));
68 static INLINE
int fits_in_unsigned_byte
PARAMS ((offsetT
));
69 static INLINE
int fits_in_unsigned_word
PARAMS ((offsetT
));
70 static INLINE
int fits_in_signed_word
PARAMS ((offsetT
));
71 static INLINE
int fits_in_unsigned_long
PARAMS ((offsetT
));
72 static INLINE
int fits_in_signed_long
PARAMS ((offsetT
));
73 static int smallest_imm_type
PARAMS ((offsetT
));
74 static offsetT offset_in_range
PARAMS ((offsetT
, int));
75 static int add_prefix
PARAMS ((unsigned int));
76 static void set_code_flag
PARAMS ((int));
77 static void set_16bit_gcc_code_flag
PARAMS ((int));
78 static void set_intel_syntax
PARAMS ((int));
79 static void set_cpu_arch
PARAMS ((int));
81 static void pe_directive_secrel
PARAMS ((int));
83 static char *output_invalid
PARAMS ((int c
));
84 static int i386_operand
PARAMS ((char *operand_string
));
85 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
86 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
88 static char *parse_insn
PARAMS ((char *, char *));
89 static char *parse_operands
PARAMS ((char *, const char *));
90 static void swap_operands
PARAMS ((void));
91 static void optimize_imm
PARAMS ((void));
92 static void optimize_disp
PARAMS ((void));
93 static int match_template
PARAMS ((void));
94 static int check_string
PARAMS ((void));
95 static int process_suffix
PARAMS ((void));
96 static int check_byte_reg
PARAMS ((void));
97 static int check_long_reg
PARAMS ((void));
98 static int check_qword_reg
PARAMS ((void));
99 static int check_word_reg
PARAMS ((void));
100 static int finalize_imm
PARAMS ((void));
101 static int process_operands
PARAMS ((void));
102 static const seg_entry
*build_modrm_byte
PARAMS ((void));
103 static void output_insn
PARAMS ((void));
104 static void output_branch
PARAMS ((void));
105 static void output_jump
PARAMS ((void));
106 static void output_interseg_jump
PARAMS ((void));
107 static void output_imm
PARAMS ((fragS
*insn_start_frag
,
108 offsetT insn_start_off
));
109 static void output_disp
PARAMS ((fragS
*insn_start_frag
,
110 offsetT insn_start_off
));
112 static void s_bss
PARAMS ((int));
115 static const char *default_arch
= DEFAULT_ARCH
;
117 /* 'md_assemble ()' gathers together information and puts it into a
124 const reg_entry
*regs
;
129 /* TM holds the template for the insn were currently assembling. */
132 /* SUFFIX holds the instruction mnemonic suffix if given.
133 (e.g. 'l' for 'movl') */
136 /* OPERANDS gives the number of given operands. */
137 unsigned int operands
;
139 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
140 of given register, displacement, memory operands and immediate
142 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
144 /* TYPES [i] is the type (see above #defines) which tells us how to
145 use OP[i] for the corresponding operand. */
146 unsigned int types
[MAX_OPERANDS
];
148 /* Displacement expression, immediate expression, or register for each
150 union i386_op op
[MAX_OPERANDS
];
152 /* Flags for operands. */
153 unsigned int flags
[MAX_OPERANDS
];
154 #define Operand_PCrel 1
156 /* Relocation type for operand */
157 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
159 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
160 the base index byte below. */
161 const reg_entry
*base_reg
;
162 const reg_entry
*index_reg
;
163 unsigned int log2_scale_factor
;
165 /* SEG gives the seg_entries of this insn. They are zero unless
166 explicit segment overrides are given. */
167 const seg_entry
*seg
[2];
169 /* PREFIX holds all the given prefix opcodes (usually null).
170 PREFIXES is the number of prefix opcodes. */
171 unsigned int prefixes
;
172 unsigned char prefix
[MAX_PREFIXES
];
174 /* RM and SIB are the modrm byte and the sib byte where the
175 addressing modes of this insn are encoded. */
182 typedef struct _i386_insn i386_insn
;
184 /* List of chars besides those in app.c:symbol_chars that can start an
185 operand. Used to prevent the scrubber eating vital white-space. */
186 const char extra_symbol_chars
[] = "*%-(["
195 #if (defined (TE_I386AIX) \
196 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
197 && !defined (TE_LINUX) \
198 && !defined (TE_NETWARE) \
199 && !defined (TE_FreeBSD) \
200 && !defined (TE_NetBSD)))
201 /* This array holds the chars that always start a comment. If the
202 pre-processor is disabled, these aren't very useful. */
203 const char comment_chars
[] = "#/";
204 #define PREFIX_SEPARATOR '\\'
206 /* This array holds the chars that only start a comment at the beginning of
207 a line. If the line seems to have the form '# 123 filename'
208 .line and .file directives will appear in the pre-processed output.
209 Note that input_file.c hand checks for '#' at the beginning of the
210 first line of the input file. This is because the compiler outputs
211 #NO_APP at the beginning of its output.
212 Also note that comments started like this one will always work if
213 '/' isn't otherwise defined. */
214 const char line_comment_chars
[] = "#";
217 /* Putting '/' here makes it impossible to use the divide operator.
218 However, we need it for compatibility with SVR4 systems. */
219 const char comment_chars
[] = "#";
220 #define PREFIX_SEPARATOR '/'
222 const char line_comment_chars
[] = "/#";
225 const char line_separator_chars
[] = ";";
227 /* Chars that can be used to separate mant from exp in floating point
229 const char EXP_CHARS
[] = "eE";
231 /* Chars that mean this number is a floating point constant
234 const char FLT_CHARS
[] = "fFdDxX";
236 /* Tables for lexical analysis. */
237 static char mnemonic_chars
[256];
238 static char register_chars
[256];
239 static char operand_chars
[256];
240 static char identifier_chars
[256];
241 static char digit_chars
[256];
243 /* Lexical macros. */
244 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
245 #define is_operand_char(x) (operand_chars[(unsigned char) x])
246 #define is_register_char(x) (register_chars[(unsigned char) x])
247 #define is_space_char(x) ((x) == ' ')
248 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
249 #define is_digit_char(x) (digit_chars[(unsigned char) x])
251 /* All non-digit non-letter characters that may occur in an operand. */
252 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
254 /* md_assemble() always leaves the strings it's passed unaltered. To
255 effect this we maintain a stack of saved characters that we've smashed
256 with '\0's (indicating end of strings for various sub-fields of the
257 assembler instruction). */
258 static char save_stack
[32];
259 static char *save_stack_p
;
260 #define END_STRING_AND_SAVE(s) \
261 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
262 #define RESTORE_END_STRING(s) \
263 do { *(s) = *--save_stack_p; } while (0)
265 /* The instruction we're assembling. */
268 /* Possible templates for current insn. */
269 static const templates
*current_templates
;
271 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
272 static expressionS disp_expressions
[2], im_expressions
[2];
274 /* Current operand we are working on. */
275 static int this_operand
;
277 /* We support four different modes. FLAG_CODE variable is used to distinguish
284 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
286 static enum flag_code flag_code
;
287 static int use_rela_relocations
= 0;
289 /* The names used to print error messages. */
290 static const char *flag_code_names
[] =
297 /* 1 for intel syntax,
299 static int intel_syntax
= 0;
301 /* 1 if register prefix % not required. */
302 static int allow_naked_reg
= 0;
304 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
305 leave, push, and pop instructions so that gcc has the same stack
306 frame as in 32 bit mode. */
307 static char stackop_size
= '\0';
309 /* Non-zero to optimize code alignment. */
310 int optimize_align_code
= 1;
312 /* Non-zero to quieten some warnings. */
313 static int quiet_warnings
= 0;
316 static const char *cpu_arch_name
= NULL
;
317 static const char *cpu_sub_arch_name
= NULL
;
319 /* CPU feature flags. */
320 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
322 /* If set, conditional jumps are not automatically promoted to handle
323 larger than a byte offset. */
324 static unsigned int no_cond_jump_promotion
= 0;
326 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
327 static symbolS
*GOT_symbol
;
329 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
330 unsigned int x86_dwarf2_return_column
;
332 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
333 int x86_cie_data_alignment
;
335 /* Interface to relax_segment.
336 There are 3 major relax states for 386 jump insns because the
337 different types of jumps add different sizes to frags when we're
338 figuring out what sort of jump to choose to reach a given label. */
341 #define UNCOND_JUMP 0
343 #define COND_JUMP86 2
348 #define SMALL16 (SMALL | CODE16)
350 #define BIG16 (BIG | CODE16)
354 #define INLINE __inline__
360 #define ENCODE_RELAX_STATE(type, size) \
361 ((relax_substateT) (((type) << 2) | (size)))
362 #define TYPE_FROM_RELAX_STATE(s) \
364 #define DISP_SIZE_FROM_RELAX_STATE(s) \
365 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
367 /* This table is used by relax_frag to promote short jumps to long
368 ones where necessary. SMALL (short) jumps may be promoted to BIG
369 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
370 don't allow a short jump in a 32 bit code segment to be promoted to
371 a 16 bit offset jump because it's slower (requires data size
372 prefix), and doesn't work, unless the destination is in the bottom
373 64k of the code segment (The top 16 bits of eip are zeroed). */
375 const relax_typeS md_relax_table
[] =
378 1) most positive reach of this state,
379 2) most negative reach of this state,
380 3) how many bytes this mode will have in the variable part of the frag
381 4) which index into the table to try if we can't fit into this one. */
383 /* UNCOND_JUMP states. */
384 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
385 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
386 /* dword jmp adds 4 bytes to frag:
387 0 extra opcode bytes, 4 displacement bytes. */
389 /* word jmp adds 2 byte2 to frag:
390 0 extra opcode bytes, 2 displacement bytes. */
393 /* COND_JUMP states. */
394 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
395 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
396 /* dword conditionals adds 5 bytes to frag:
397 1 extra opcode byte, 4 displacement bytes. */
399 /* word conditionals add 3 bytes to frag:
400 1 extra opcode byte, 2 displacement bytes. */
403 /* COND_JUMP86 states. */
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
406 /* dword conditionals adds 5 bytes to frag:
407 1 extra opcode byte, 4 displacement bytes. */
409 /* word conditionals add 4 bytes to frag:
410 1 displacement byte and a 3 byte long branch insn. */
414 static const arch_entry cpu_arch
[] = {
416 {"i186", Cpu086
|Cpu186
},
417 {"i286", Cpu086
|Cpu186
|Cpu286
},
418 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
419 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
420 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
421 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
422 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
423 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
424 {"pentiumii", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
},
425 {"pentiumiii",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuMMX2
|CpuSSE
},
426 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
427 {"prescott", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuPNI
},
428 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
},
429 {"k6_2", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
430 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
431 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
433 {".sse", CpuMMX
|CpuMMX2
|CpuSSE
},
434 {".sse2", CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
435 {".3dnow", CpuMMX
|Cpu3dnow
},
436 {".3dnowa", CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
437 {".padlock", CpuPadLock
},
441 const pseudo_typeS md_pseudo_table
[] =
443 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
444 {"align", s_align_bytes
, 0},
446 {"align", s_align_ptwo
, 0},
448 {"arch", set_cpu_arch
, 0},
452 {"ffloat", float_cons
, 'f'},
453 {"dfloat", float_cons
, 'd'},
454 {"tfloat", float_cons
, 'x'},
456 {"noopt", s_ignore
, 0},
457 {"optim", s_ignore
, 0},
458 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
459 {"code16", set_code_flag
, CODE_16BIT
},
460 {"code32", set_code_flag
, CODE_32BIT
},
461 {"code64", set_code_flag
, CODE_64BIT
},
462 {"intel_syntax", set_intel_syntax
, 1},
463 {"att_syntax", set_intel_syntax
, 0},
464 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0},
465 {"loc", dwarf2_directive_loc
, 0},
467 {"secrel32", pe_directive_secrel
, 0},
472 /* For interface with expression (). */
473 extern char *input_line_pointer
;
475 /* Hash table for instruction mnemonic lookup. */
476 static struct hash_control
*op_hash
;
478 /* Hash table for register lookup. */
479 static struct hash_control
*reg_hash
;
482 i386_align_code (fragP
, count
)
486 /* Various efficient no-op patterns for aligning code labels.
487 Note: Don't try to assemble the instructions in the comments.
488 0L and 0w are not legal. */
489 static const char f32_1
[] =
491 static const char f32_2
[] =
492 {0x89,0xf6}; /* movl %esi,%esi */
493 static const char f32_3
[] =
494 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
495 static const char f32_4
[] =
496 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
497 static const char f32_5
[] =
499 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
500 static const char f32_6
[] =
501 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
502 static const char f32_7
[] =
503 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
504 static const char f32_8
[] =
506 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
507 static const char f32_9
[] =
508 {0x89,0xf6, /* movl %esi,%esi */
509 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
510 static const char f32_10
[] =
511 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
512 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
513 static const char f32_11
[] =
514 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
515 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
516 static const char f32_12
[] =
517 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
518 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
519 static const char f32_13
[] =
520 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
521 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
522 static const char f32_14
[] =
523 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
524 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
525 static const char f32_15
[] =
526 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
527 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
528 static const char f16_3
[] =
529 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
530 static const char f16_4
[] =
531 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
532 static const char f16_5
[] =
534 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
535 static const char f16_6
[] =
536 {0x89,0xf6, /* mov %si,%si */
537 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
538 static const char f16_7
[] =
539 {0x8d,0x74,0x00, /* lea 0(%si),%si */
540 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
541 static const char f16_8
[] =
542 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
543 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
544 static const char *const f32_patt
[] = {
545 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
546 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
548 static const char *const f16_patt
[] = {
549 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
550 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
553 if (count
<= 0 || count
> 15)
556 /* The recommended way to pad 64bit code is to use NOPs preceded by
557 maximally four 0x66 prefixes. Balance the size of nops. */
558 if (flag_code
== CODE_64BIT
)
561 int nnops
= (count
+ 3) / 4;
562 int len
= count
/ nnops
;
563 int remains
= count
- nnops
* len
;
566 for (i
= 0; i
< remains
; i
++)
568 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
569 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
572 for (; i
< nnops
; i
++)
574 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
575 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
580 if (flag_code
== CODE_16BIT
)
582 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
583 f16_patt
[count
- 1], count
);
585 /* Adjust jump offset. */
586 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
589 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
590 f32_patt
[count
- 1], count
);
591 fragP
->fr_var
= count
;
594 static INLINE
unsigned int
595 mode_from_disp_size (t
)
598 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
602 fits_in_signed_byte (num
)
605 return (num
>= -128) && (num
<= 127);
609 fits_in_unsigned_byte (num
)
612 return (num
& 0xff) == num
;
616 fits_in_unsigned_word (num
)
619 return (num
& 0xffff) == num
;
623 fits_in_signed_word (num
)
626 return (-32768 <= num
) && (num
<= 32767);
629 fits_in_signed_long (num
)
630 offsetT num ATTRIBUTE_UNUSED
;
635 return (!(((offsetT
) -1 << 31) & num
)
636 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
638 } /* fits_in_signed_long() */
640 fits_in_unsigned_long (num
)
641 offsetT num ATTRIBUTE_UNUSED
;
646 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
648 } /* fits_in_unsigned_long() */
651 smallest_imm_type (num
)
654 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
656 /* This code is disabled on the 486 because all the Imm1 forms
657 in the opcode table are slower on the i486. They're the
658 versions with the implicitly specified single-position
659 displacement, which has another syntax if you really want to
662 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
664 return (fits_in_signed_byte (num
)
665 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
666 : fits_in_unsigned_byte (num
)
667 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
668 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
669 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
670 : fits_in_signed_long (num
)
671 ? (Imm32
| Imm32S
| Imm64
)
672 : fits_in_unsigned_long (num
)
678 offset_in_range (val
, size
)
686 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
687 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
688 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
690 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
695 /* If BFD64, sign extend val. */
696 if (!use_rela_relocations
)
697 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
698 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
700 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
702 char buf1
[40], buf2
[40];
704 sprint_value (buf1
, val
);
705 sprint_value (buf2
, val
& mask
);
706 as_warn (_("%s shortened to %s"), buf1
, buf2
);
711 /* Returns 0 if attempting to add a prefix where one from the same
712 class already exists, 1 if non rep/repne added, 2 if rep/repne
721 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
722 && flag_code
== CODE_64BIT
)
730 case CS_PREFIX_OPCODE
:
731 case DS_PREFIX_OPCODE
:
732 case ES_PREFIX_OPCODE
:
733 case FS_PREFIX_OPCODE
:
734 case GS_PREFIX_OPCODE
:
735 case SS_PREFIX_OPCODE
:
739 case REPNE_PREFIX_OPCODE
:
740 case REPE_PREFIX_OPCODE
:
743 case LOCK_PREFIX_OPCODE
:
751 case ADDR_PREFIX_OPCODE
:
755 case DATA_PREFIX_OPCODE
:
760 if (i
.prefix
[q
] != 0)
762 as_bad (_("same type of prefix used twice"));
767 i
.prefix
[q
] = prefix
;
772 set_code_flag (value
)
776 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
777 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
778 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
780 as_bad (_("64bit mode not supported on this CPU."));
782 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
784 as_bad (_("32bit mode not supported on this CPU."));
790 set_16bit_gcc_code_flag (new_code_flag
)
793 flag_code
= new_code_flag
;
794 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
795 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
796 stackop_size
= LONG_MNEM_SUFFIX
;
800 set_intel_syntax (syntax_flag
)
803 /* Find out if register prefixing is specified. */
804 int ask_naked_reg
= 0;
807 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
809 char *string
= input_line_pointer
;
810 int e
= get_symbol_end ();
812 if (strcmp (string
, "prefix") == 0)
814 else if (strcmp (string
, "noprefix") == 0)
817 as_bad (_("bad argument to syntax directive."));
818 *input_line_pointer
= e
;
820 demand_empty_rest_of_line ();
822 intel_syntax
= syntax_flag
;
824 if (ask_naked_reg
== 0)
825 allow_naked_reg
= (intel_syntax
826 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
828 allow_naked_reg
= (ask_naked_reg
< 0);
830 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
831 identifier_chars
['$'] = intel_syntax
? '$' : 0;
836 int dummy ATTRIBUTE_UNUSED
;
840 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
842 char *string
= input_line_pointer
;
843 int e
= get_symbol_end ();
846 for (i
= 0; cpu_arch
[i
].name
; i
++)
848 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
852 cpu_arch_name
= cpu_arch
[i
].name
;
853 cpu_sub_arch_name
= NULL
;
854 cpu_arch_flags
= (cpu_arch
[i
].flags
855 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
858 if ((cpu_arch_flags
| cpu_arch
[i
].flags
) != cpu_arch_flags
)
860 cpu_sub_arch_name
= cpu_arch
[i
].name
;
861 cpu_arch_flags
|= cpu_arch
[i
].flags
;
863 *input_line_pointer
= e
;
864 demand_empty_rest_of_line ();
868 if (!cpu_arch
[i
].name
)
869 as_bad (_("no such architecture: `%s'"), string
);
871 *input_line_pointer
= e
;
874 as_bad (_("missing cpu architecture"));
876 no_cond_jump_promotion
= 0;
877 if (*input_line_pointer
== ','
878 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
880 char *string
= ++input_line_pointer
;
881 int e
= get_symbol_end ();
883 if (strcmp (string
, "nojumps") == 0)
884 no_cond_jump_promotion
= 1;
885 else if (strcmp (string
, "jumps") == 0)
888 as_bad (_("no such architecture modifier: `%s'"), string
);
890 *input_line_pointer
= e
;
893 demand_empty_rest_of_line ();
899 if (!strcmp (default_arch
, "x86_64"))
900 return bfd_mach_x86_64
;
901 else if (!strcmp (default_arch
, "i386"))
902 return bfd_mach_i386_i386
;
904 as_fatal (_("Unknown architecture"));
910 const char *hash_err
;
912 /* Initialize op_hash hash table. */
913 op_hash
= hash_new ();
916 const template *optab
;
917 templates
*core_optab
;
919 /* Setup for loop. */
921 core_optab
= (templates
*) xmalloc (sizeof (templates
));
922 core_optab
->start
= optab
;
927 if (optab
->name
== NULL
928 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
930 /* different name --> ship out current template list;
931 add to hash table; & begin anew. */
932 core_optab
->end
= optab
;
933 hash_err
= hash_insert (op_hash
,
938 as_fatal (_("Internal Error: Can't hash %s: %s"),
942 if (optab
->name
== NULL
)
944 core_optab
= (templates
*) xmalloc (sizeof (templates
));
945 core_optab
->start
= optab
;
950 /* Initialize reg_hash hash table. */
951 reg_hash
= hash_new ();
953 const reg_entry
*regtab
;
955 for (regtab
= i386_regtab
;
956 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
959 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
961 as_fatal (_("Internal Error: Can't hash %s: %s"),
967 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
972 for (c
= 0; c
< 256; c
++)
977 mnemonic_chars
[c
] = c
;
978 register_chars
[c
] = c
;
979 operand_chars
[c
] = c
;
981 else if (ISLOWER (c
))
983 mnemonic_chars
[c
] = c
;
984 register_chars
[c
] = c
;
985 operand_chars
[c
] = c
;
987 else if (ISUPPER (c
))
989 mnemonic_chars
[c
] = TOLOWER (c
);
990 register_chars
[c
] = mnemonic_chars
[c
];
991 operand_chars
[c
] = c
;
994 if (ISALPHA (c
) || ISDIGIT (c
))
995 identifier_chars
[c
] = c
;
998 identifier_chars
[c
] = c
;
999 operand_chars
[c
] = c
;
1004 identifier_chars
['@'] = '@';
1007 identifier_chars
['?'] = '?';
1008 operand_chars
['?'] = '?';
1010 digit_chars
['-'] = '-';
1011 mnemonic_chars
['-'] = '-';
1012 identifier_chars
['_'] = '_';
1013 identifier_chars
['.'] = '.';
1015 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1016 operand_chars
[(unsigned char) *p
] = *p
;
1019 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1020 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1022 record_alignment (text_section
, 2);
1023 record_alignment (data_section
, 2);
1024 record_alignment (bss_section
, 2);
1028 if (flag_code
== CODE_64BIT
)
1030 x86_dwarf2_return_column
= 16;
1031 x86_cie_data_alignment
= -8;
1035 x86_dwarf2_return_column
= 8;
1036 x86_cie_data_alignment
= -4;
1041 i386_print_statistics (file
)
1044 hash_print_statistics (file
, "i386 opcode", op_hash
);
1045 hash_print_statistics (file
, "i386 register", reg_hash
);
1050 /* Debugging routines for md_assemble. */
1051 static void pi
PARAMS ((char *, i386_insn
*));
1052 static void pte
PARAMS ((template *));
1053 static void pt
PARAMS ((unsigned int));
1054 static void pe
PARAMS ((expressionS
*));
1055 static void ps
PARAMS ((symbolS
*));
1064 fprintf (stdout
, "%s: template ", line
);
1066 fprintf (stdout
, " address: base %s index %s scale %x\n",
1067 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1068 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1069 x
->log2_scale_factor
);
1070 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1071 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1072 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1073 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1074 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1075 (x
->rex
& REX_MODE64
) != 0,
1076 (x
->rex
& REX_EXTX
) != 0,
1077 (x
->rex
& REX_EXTY
) != 0,
1078 (x
->rex
& REX_EXTZ
) != 0);
1079 for (i
= 0; i
< x
->operands
; i
++)
1081 fprintf (stdout
, " #%d: ", i
+ 1);
1083 fprintf (stdout
, "\n");
1085 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1086 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1087 if (x
->types
[i
] & Imm
)
1089 if (x
->types
[i
] & Disp
)
1090 pe (x
->op
[i
].disps
);
1099 fprintf (stdout
, " %d operands ", t
->operands
);
1100 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1101 if (t
->extension_opcode
!= None
)
1102 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1103 if (t
->opcode_modifier
& D
)
1104 fprintf (stdout
, "D");
1105 if (t
->opcode_modifier
& W
)
1106 fprintf (stdout
, "W");
1107 fprintf (stdout
, "\n");
1108 for (i
= 0; i
< t
->operands
; i
++)
1110 fprintf (stdout
, " #%d type ", i
+ 1);
1111 pt (t
->operand_types
[i
]);
1112 fprintf (stdout
, "\n");
1120 fprintf (stdout
, " operation %d\n", e
->X_op
);
1121 fprintf (stdout
, " add_number %ld (%lx)\n",
1122 (long) e
->X_add_number
, (long) e
->X_add_number
);
1123 if (e
->X_add_symbol
)
1125 fprintf (stdout
, " add_symbol ");
1126 ps (e
->X_add_symbol
);
1127 fprintf (stdout
, "\n");
1131 fprintf (stdout
, " op_symbol ");
1132 ps (e
->X_op_symbol
);
1133 fprintf (stdout
, "\n");
1141 fprintf (stdout
, "%s type %s%s",
1143 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1144 segment_name (S_GET_SEGMENT (s
)));
1153 static const type_names
[] =
1166 { BaseIndex
, "BaseIndex" },
1170 { Disp32S
, "d32s" },
1172 { InOutPortReg
, "InOutPortReg" },
1173 { ShiftCount
, "ShiftCount" },
1174 { Control
, "control reg" },
1175 { Test
, "test reg" },
1176 { Debug
, "debug reg" },
1177 { FloatReg
, "FReg" },
1178 { FloatAcc
, "FAcc" },
1182 { JumpAbsolute
, "Jump Absolute" },
1193 const struct type_name
*ty
;
1195 for (ty
= type_names
; ty
->mask
; ty
++)
1197 fprintf (stdout
, "%s, ", ty
->tname
);
1201 #endif /* DEBUG386 */
1203 static bfd_reloc_code_real_type reloc
1204 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
1206 static bfd_reloc_code_real_type
1207 reloc (size
, pcrel
, sign
, other
)
1211 bfd_reloc_code_real_type other
;
1213 if (other
!= NO_RELOC
)
1219 as_bad (_("There are no unsigned pc-relative relocations"));
1222 case 1: return BFD_RELOC_8_PCREL
;
1223 case 2: return BFD_RELOC_16_PCREL
;
1224 case 4: return BFD_RELOC_32_PCREL
;
1226 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1233 case 4: return BFD_RELOC_X86_64_32S
;
1238 case 1: return BFD_RELOC_8
;
1239 case 2: return BFD_RELOC_16
;
1240 case 4: return BFD_RELOC_32
;
1241 case 8: return BFD_RELOC_64
;
1243 as_bad (_("can not do %s %d byte relocation"),
1244 sign
? "signed" : "unsigned", size
);
1248 return BFD_RELOC_NONE
;
1251 /* Here we decide which fixups can be adjusted to make them relative to
1252 the beginning of the section instead of the symbol. Basically we need
1253 to make sure that the dynamic relocations are done correctly, so in
1254 some cases we force the original symbol to be used. */
1257 tc_i386_fix_adjustable (fixP
)
1258 fixS
*fixP ATTRIBUTE_UNUSED
;
1260 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1261 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
1264 /* Don't adjust pc-relative references to merge sections in 64-bit
1266 if (use_rela_relocations
1267 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1271 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1272 and changed later by validate_fix. */
1273 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
1274 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
1277 /* adjust_reloc_syms doesn't know about the GOT. */
1278 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1279 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1280 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1281 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1282 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1283 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1284 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1285 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1286 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1287 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1288 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1289 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1290 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1291 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1292 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1293 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1294 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1295 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1296 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1297 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1298 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1304 static int intel_float_operand
PARAMS ((const char *mnemonic
));
1307 intel_float_operand (mnemonic
)
1308 const char *mnemonic
;
1310 /* Note that the value returned is meaningful only for opcodes with (memory)
1311 operands, hence the code here is free to improperly handle opcodes that
1312 have no operands (for better performance and smaller code). */
1314 if (mnemonic
[0] != 'f')
1315 return 0; /* non-math */
1317 switch (mnemonic
[1])
1319 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1320 the fs segment override prefix not currently handled because no
1321 call path can make opcodes without operands get here */
1323 return 2 /* integer op */;
1325 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
1326 return 3; /* fldcw/fldenv */
1329 if (mnemonic
[2] != 'o' /* fnop */)
1330 return 3; /* non-waiting control op */
1333 if (mnemonic
[2] == 's')
1334 return 3; /* frstor/frstpm */
1337 if (mnemonic
[2] == 'a')
1338 return 3; /* fsave */
1339 if (mnemonic
[2] == 't')
1341 switch (mnemonic
[3])
1343 case 'c': /* fstcw */
1344 case 'd': /* fstdw */
1345 case 'e': /* fstenv */
1346 case 's': /* fsts[gw] */
1352 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
1353 return 0; /* fxsave/fxrstor are not really math ops */
1360 /* This is the guts of the machine-dependent assembler. LINE points to a
1361 machine dependent instruction. This function is supposed to emit
1362 the frags/bytes it assembles to. */
1369 char mnemonic
[MAX_MNEM_SIZE
];
1371 /* Initialize globals. */
1372 memset (&i
, '\0', sizeof (i
));
1373 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1374 i
.reloc
[j
] = NO_RELOC
;
1375 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1376 memset (im_expressions
, '\0', sizeof (im_expressions
));
1377 save_stack_p
= save_stack
;
1379 /* First parse an instruction mnemonic & call i386_operand for the operands.
1380 We assume that the scrubber has arranged it so that line[0] is the valid
1381 start of a (possibly prefixed) mnemonic. */
1383 line
= parse_insn (line
, mnemonic
);
1387 line
= parse_operands (line
, mnemonic
);
1391 /* Now we've parsed the mnemonic into a set of templates, and have the
1392 operands at hand. */
1394 /* All intel opcodes have reversed operands except for "bound" and
1395 "enter". We also don't reverse intersegment "jmp" and "call"
1396 instructions with 2 immediate operands so that the immediate segment
1397 precedes the offset, as it does when in AT&T mode. "enter" and the
1398 intersegment "jmp" and "call" instructions are the only ones that
1399 have two immediate operands. */
1400 if (intel_syntax
&& i
.operands
> 1
1401 && (strcmp (mnemonic
, "bound") != 0)
1402 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1408 if (i
.disp_operands
)
1411 /* Next, we find a template that matches the given insn,
1412 making sure the overlap of the given operands types is consistent
1413 with the template operand types. */
1415 if (!match_template ())
1420 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1422 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1423 i
.tm
.base_opcode
^= FloatR
;
1425 /* Zap movzx and movsx suffix. The suffix may have been set from
1426 "word ptr" or "byte ptr" on the source operand, but we'll use
1427 the suffix later to choose the destination register. */
1428 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1430 if (i
.reg_operands
< 2
1432 && (~i
.tm
.opcode_modifier
1439 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
1445 if (i
.tm
.opcode_modifier
& FWait
)
1446 if (!add_prefix (FWAIT_OPCODE
))
1449 /* Check string instruction segment overrides. */
1450 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1452 if (!check_string ())
1456 if (!process_suffix ())
1459 /* Make still unresolved immediate matches conform to size of immediate
1460 given in i.suffix. */
1461 if (!finalize_imm ())
1464 if (i
.types
[0] & Imm1
)
1465 i
.imm_operands
= 0; /* kludge for shift insns. */
1466 if (i
.types
[0] & ImplicitRegister
)
1468 if (i
.types
[1] & ImplicitRegister
)
1470 if (i
.types
[2] & ImplicitRegister
)
1473 if (i
.tm
.opcode_modifier
& ImmExt
)
1477 if ((i
.tm
.cpu_flags
& CpuPNI
) && i
.operands
> 0)
1479 /* These Intel Prescott New Instructions have the fixed
1480 operands with an opcode suffix which is coded in the same
1481 place as an 8-bit immediate field would be. Here we check
1482 those operands and remove them afterwards. */
1485 for (x
= 0; x
< i
.operands
; x
++)
1486 if (i
.op
[x
].regs
->reg_num
!= x
)
1487 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1488 i
.op
[x
].regs
->reg_name
, x
+ 1, i
.tm
.name
);
1492 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1493 opcode suffix which is coded in the same place as an 8-bit
1494 immediate field would be. Here we fake an 8-bit immediate
1495 operand from the opcode suffix stored in tm.extension_opcode. */
1497 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1499 exp
= &im_expressions
[i
.imm_operands
++];
1500 i
.op
[i
.operands
].imms
= exp
;
1501 i
.types
[i
.operands
++] = Imm8
;
1502 exp
->X_op
= O_constant
;
1503 exp
->X_add_number
= i
.tm
.extension_opcode
;
1504 i
.tm
.extension_opcode
= None
;
1507 /* For insns with operands there are more diddles to do to the opcode. */
1510 if (!process_operands ())
1513 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1515 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1516 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1519 /* Handle conversion of 'int $3' --> special int3 insn. */
1520 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1522 i
.tm
.base_opcode
= INT3_OPCODE
;
1526 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1527 && i
.op
[0].disps
->X_op
== O_constant
)
1529 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1530 the absolute address given by the constant. Since ix86 jumps and
1531 calls are pc relative, we need to generate a reloc. */
1532 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1533 i
.op
[0].disps
->X_op
= O_symbol
;
1536 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1537 i
.rex
|= REX_MODE64
;
1539 /* For 8 bit registers we need an empty rex prefix. Also if the
1540 instruction already has a prefix, we need to convert old
1541 registers to new ones. */
1543 if (((i
.types
[0] & Reg8
) != 0
1544 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1545 || ((i
.types
[1] & Reg8
) != 0
1546 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1547 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1552 i
.rex
|= REX_OPCODE
;
1553 for (x
= 0; x
< 2; x
++)
1555 /* Look for 8 bit operand that uses old registers. */
1556 if ((i
.types
[x
] & Reg8
) != 0
1557 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1559 /* In case it is "hi" register, give up. */
1560 if (i
.op
[x
].regs
->reg_num
> 3)
1561 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1562 i
.op
[x
].regs
->reg_name
);
1564 /* Otherwise it is equivalent to the extended register.
1565 Since the encoding doesn't change this is merely
1566 cosmetic cleanup for debug output. */
1568 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1574 add_prefix (REX_OPCODE
| i
.rex
);
1576 /* We are ready to output the insn. */
1581 parse_insn (line
, mnemonic
)
1586 char *token_start
= l
;
1591 /* Non-zero if we found a prefix only acceptable with string insns. */
1592 const char *expecting_string_instruction
= NULL
;
1597 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1600 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1602 as_bad (_("no such instruction: `%s'"), token_start
);
1607 if (!is_space_char (*l
)
1608 && *l
!= END_OF_INSN
1610 || (*l
!= PREFIX_SEPARATOR
1613 as_bad (_("invalid character %s in mnemonic"),
1614 output_invalid (*l
));
1617 if (token_start
== l
)
1619 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
1620 as_bad (_("expecting prefix; got nothing"));
1622 as_bad (_("expecting mnemonic; got nothing"));
1626 /* Look up instruction (or prefix) via hash table. */
1627 current_templates
= hash_find (op_hash
, mnemonic
);
1629 if (*l
!= END_OF_INSN
1630 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1631 && current_templates
1632 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1634 /* If we are in 16-bit mode, do not allow addr16 or data16.
1635 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1636 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1637 && flag_code
!= CODE_64BIT
1638 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1639 ^ (flag_code
== CODE_16BIT
)))
1641 as_bad (_("redundant %s prefix"),
1642 current_templates
->start
->name
);
1645 /* Add prefix, checking for repeated prefixes. */
1646 switch (add_prefix (current_templates
->start
->base_opcode
))
1651 expecting_string_instruction
= current_templates
->start
->name
;
1654 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1661 if (!current_templates
)
1663 /* See if we can get a match by trimming off a suffix. */
1666 case WORD_MNEM_SUFFIX
:
1667 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
1668 i
.suffix
= SHORT_MNEM_SUFFIX
;
1670 case BYTE_MNEM_SUFFIX
:
1671 case QWORD_MNEM_SUFFIX
:
1672 i
.suffix
= mnem_p
[-1];
1674 current_templates
= hash_find (op_hash
, mnemonic
);
1676 case SHORT_MNEM_SUFFIX
:
1677 case LONG_MNEM_SUFFIX
:
1680 i
.suffix
= mnem_p
[-1];
1682 current_templates
= hash_find (op_hash
, mnemonic
);
1690 if (intel_float_operand (mnemonic
) == 1)
1691 i
.suffix
= SHORT_MNEM_SUFFIX
;
1693 i
.suffix
= LONG_MNEM_SUFFIX
;
1695 current_templates
= hash_find (op_hash
, mnemonic
);
1699 if (!current_templates
)
1701 as_bad (_("no such instruction: `%s'"), token_start
);
1706 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1708 /* Check for a branch hint. We allow ",pt" and ",pn" for
1709 predict taken and predict not taken respectively.
1710 I'm not sure that branch hints actually do anything on loop
1711 and jcxz insns (JumpByte) for current Pentium4 chips. They
1712 may work in the future and it doesn't hurt to accept them
1714 if (l
[0] == ',' && l
[1] == 'p')
1718 if (!add_prefix (DS_PREFIX_OPCODE
))
1722 else if (l
[2] == 'n')
1724 if (!add_prefix (CS_PREFIX_OPCODE
))
1730 /* Any other comma loses. */
1733 as_bad (_("invalid character %s in mnemonic"),
1734 output_invalid (*l
));
1738 /* Check if instruction is supported on specified architecture. */
1740 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
1742 if (!((t
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1743 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
))))
1745 if (!(t
->cpu_flags
& (flag_code
== CODE_64BIT
? CpuNo64
: Cpu64
)))
1748 if (!(supported
& 2))
1750 as_bad (flag_code
== CODE_64BIT
1751 ? _("`%s' is not supported in 64-bit mode")
1752 : _("`%s' is only supported in 64-bit mode"),
1753 current_templates
->start
->name
);
1756 if (!(supported
& 1))
1758 as_warn (_("`%s' is not supported on `%s%s'"),
1759 current_templates
->start
->name
,
1761 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
1763 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1765 as_warn (_("use .code16 to ensure correct addressing mode"));
1768 /* Check for rep/repne without a string instruction. */
1769 if (expecting_string_instruction
)
1771 static templates override
;
1773 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
1774 if (t
->opcode_modifier
& IsString
)
1776 if (t
>= current_templates
->end
)
1778 as_bad (_("expecting string instruction after `%s'"),
1779 expecting_string_instruction
);
1782 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
1783 if (!(t
->opcode_modifier
& IsString
))
1786 current_templates
= &override
;
1793 parse_operands (l
, mnemonic
)
1795 const char *mnemonic
;
1799 /* 1 if operand is pending after ','. */
1800 unsigned int expecting_operand
= 0;
1802 /* Non-zero if operand parens not balanced. */
1803 unsigned int paren_not_balanced
;
1805 while (*l
!= END_OF_INSN
)
1807 /* Skip optional white space before operand. */
1808 if (is_space_char (*l
))
1810 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1812 as_bad (_("invalid character %s before operand %d"),
1813 output_invalid (*l
),
1817 token_start
= l
; /* after white space */
1818 paren_not_balanced
= 0;
1819 while (paren_not_balanced
|| *l
!= ',')
1821 if (*l
== END_OF_INSN
)
1823 if (paren_not_balanced
)
1826 as_bad (_("unbalanced parenthesis in operand %d."),
1829 as_bad (_("unbalanced brackets in operand %d."),
1834 break; /* we are done */
1836 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1838 as_bad (_("invalid character %s in operand %d"),
1839 output_invalid (*l
),
1846 ++paren_not_balanced
;
1848 --paren_not_balanced
;
1853 ++paren_not_balanced
;
1855 --paren_not_balanced
;
1859 if (l
!= token_start
)
1860 { /* Yes, we've read in another operand. */
1861 unsigned int operand_ok
;
1862 this_operand
= i
.operands
++;
1863 if (i
.operands
> MAX_OPERANDS
)
1865 as_bad (_("spurious operands; (%d operands/instruction max)"),
1869 /* Now parse operand adding info to 'i' as we go along. */
1870 END_STRING_AND_SAVE (l
);
1874 i386_intel_operand (token_start
,
1875 intel_float_operand (mnemonic
));
1877 operand_ok
= i386_operand (token_start
);
1879 RESTORE_END_STRING (l
);
1885 if (expecting_operand
)
1887 expecting_operand_after_comma
:
1888 as_bad (_("expecting operand after ','; got nothing"));
1893 as_bad (_("expecting operand before ','; got nothing"));
1898 /* Now *l must be either ',' or END_OF_INSN. */
1901 if (*++l
== END_OF_INSN
)
1903 /* Just skip it, if it's \n complain. */
1904 goto expecting_operand_after_comma
;
1906 expecting_operand
= 1;
1915 union i386_op temp_op
;
1916 unsigned int temp_type
;
1917 enum bfd_reloc_code_real temp_reloc
;
1921 if (i
.operands
== 2)
1926 else if (i
.operands
== 3)
1931 temp_type
= i
.types
[xchg2
];
1932 i
.types
[xchg2
] = i
.types
[xchg1
];
1933 i
.types
[xchg1
] = temp_type
;
1934 temp_op
= i
.op
[xchg2
];
1935 i
.op
[xchg2
] = i
.op
[xchg1
];
1936 i
.op
[xchg1
] = temp_op
;
1937 temp_reloc
= i
.reloc
[xchg2
];
1938 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1939 i
.reloc
[xchg1
] = temp_reloc
;
1941 if (i
.mem_operands
== 2)
1943 const seg_entry
*temp_seg
;
1944 temp_seg
= i
.seg
[0];
1945 i
.seg
[0] = i
.seg
[1];
1946 i
.seg
[1] = temp_seg
;
1950 /* Try to ensure constant immediates are represented in the smallest
1955 char guess_suffix
= 0;
1959 guess_suffix
= i
.suffix
;
1960 else if (i
.reg_operands
)
1962 /* Figure out a suffix from the last register operand specified.
1963 We can't do this properly yet, ie. excluding InOutPortReg,
1964 but the following works for instructions with immediates.
1965 In any case, we can't set i.suffix yet. */
1966 for (op
= i
.operands
; --op
>= 0;)
1967 if (i
.types
[op
] & Reg
)
1969 if (i
.types
[op
] & Reg8
)
1970 guess_suffix
= BYTE_MNEM_SUFFIX
;
1971 else if (i
.types
[op
] & Reg16
)
1972 guess_suffix
= WORD_MNEM_SUFFIX
;
1973 else if (i
.types
[op
] & Reg32
)
1974 guess_suffix
= LONG_MNEM_SUFFIX
;
1975 else if (i
.types
[op
] & Reg64
)
1976 guess_suffix
= QWORD_MNEM_SUFFIX
;
1980 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1981 guess_suffix
= WORD_MNEM_SUFFIX
;
1983 for (op
= i
.operands
; --op
>= 0;)
1984 if (i
.types
[op
] & Imm
)
1986 switch (i
.op
[op
].imms
->X_op
)
1989 /* If a suffix is given, this operand may be shortened. */
1990 switch (guess_suffix
)
1992 case LONG_MNEM_SUFFIX
:
1993 i
.types
[op
] |= Imm32
| Imm64
;
1995 case WORD_MNEM_SUFFIX
:
1996 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1998 case BYTE_MNEM_SUFFIX
:
1999 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
2003 /* If this operand is at most 16 bits, convert it
2004 to a signed 16 bit number before trying to see
2005 whether it will fit in an even smaller size.
2006 This allows a 16-bit operand such as $0xffe0 to
2007 be recognised as within Imm8S range. */
2008 if ((i
.types
[op
] & Imm16
)
2009 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
2011 i
.op
[op
].imms
->X_add_number
=
2012 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2014 if ((i
.types
[op
] & Imm32
)
2015 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2018 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2019 ^ ((offsetT
) 1 << 31))
2020 - ((offsetT
) 1 << 31));
2022 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
2024 /* We must avoid matching of Imm32 templates when 64bit
2025 only immediate is available. */
2026 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2027 i
.types
[op
] &= ~Imm32
;
2034 /* Symbols and expressions. */
2036 /* Convert symbolic operand to proper sizes for matching. */
2037 switch (guess_suffix
)
2039 case QWORD_MNEM_SUFFIX
:
2040 i
.types
[op
] = Imm64
| Imm32S
;
2042 case LONG_MNEM_SUFFIX
:
2043 i
.types
[op
] = Imm32
;
2045 case WORD_MNEM_SUFFIX
:
2046 i
.types
[op
] = Imm16
;
2048 case BYTE_MNEM_SUFFIX
:
2049 i
.types
[op
] = Imm8
| Imm8S
;
2057 /* Try to use the smallest displacement type too. */
2063 for (op
= i
.operands
; --op
>= 0;)
2064 if ((i
.types
[op
] & Disp
) && i
.op
[op
].disps
->X_op
== O_constant
)
2066 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
2068 if (i
.types
[op
] & Disp16
)
2070 /* We know this operand is at most 16 bits, so
2071 convert to a signed 16 bit number before trying
2072 to see whether it will fit in an even smaller
2075 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
2077 else if (i
.types
[op
] & Disp32
)
2079 /* We know this operand is at most 32 bits, so convert to a
2080 signed 32 bit number before trying to see whether it will
2081 fit in an even smaller size. */
2082 disp
&= (((offsetT
) 2 << 31) - 1);
2083 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
2085 if (flag_code
== CODE_64BIT
)
2087 if (fits_in_signed_long (disp
))
2088 i
.types
[op
] |= Disp32S
;
2089 if (fits_in_unsigned_long (disp
))
2090 i
.types
[op
] |= Disp32
;
2092 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
2093 && fits_in_signed_byte (disp
))
2094 i
.types
[op
] |= Disp8
;
2101 /* Points to template once we've found it. */
2103 unsigned int overlap0
, overlap1
, overlap2
;
2104 unsigned int found_reverse_match
;
2107 #define MATCH(overlap, given, template) \
2108 ((overlap & ~JumpAbsolute) \
2109 && (((given) & (BaseIndex | JumpAbsolute)) \
2110 == ((overlap) & (BaseIndex | JumpAbsolute))))
2112 /* If given types r0 and r1 are registers they must be of the same type
2113 unless the expected operand type register overlap is null.
2114 Note that Acc in a template matches every size of reg. */
2115 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2116 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2117 || ((g0) & Reg) == ((g1) & Reg) \
2118 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2123 found_reverse_match
= 0;
2124 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
2126 : (i
.suffix
== WORD_MNEM_SUFFIX
2128 : (i
.suffix
== SHORT_MNEM_SUFFIX
2130 : (i
.suffix
== LONG_MNEM_SUFFIX
2132 : (i
.suffix
== QWORD_MNEM_SUFFIX
2134 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
2135 ? No_xSuf
: 0))))));
2137 t
= current_templates
->start
;
2138 if (i
.suffix
== QWORD_MNEM_SUFFIX
2139 && flag_code
!= CODE_64BIT
2141 ? !(t
->opcode_modifier
& IgnoreSize
)
2142 && !intel_float_operand (t
->name
)
2143 : intel_float_operand (t
->name
) != 2)
2144 && (!(t
->operand_types
[0] & (RegMMX
| RegXMM
))
2145 || !(t
->operand_types
[t
->operands
> 1] & (RegMMX
| RegXMM
)))
2146 && (t
->base_opcode
!= 0x0fc7
2147 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
2148 t
= current_templates
->end
;
2149 for (; t
< current_templates
->end
; t
++)
2151 /* Must have right number of operands. */
2152 if (i
.operands
!= t
->operands
)
2155 /* Check the suffix, except for some instructions in intel mode. */
2156 if ((t
->opcode_modifier
& suffix_check
)
2158 && (t
->opcode_modifier
& IgnoreSize
)))
2161 /* Do not verify operands when there are none. */
2162 else if (!t
->operands
)
2164 if (t
->cpu_flags
& ~cpu_arch_flags
)
2166 /* We've found a match; break out of loop. */
2170 overlap0
= i
.types
[0] & t
->operand_types
[0];
2171 switch (t
->operands
)
2174 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
2179 overlap1
= i
.types
[1] & t
->operand_types
[1];
2180 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
2181 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
2182 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2183 t
->operand_types
[0],
2184 overlap1
, i
.types
[1],
2185 t
->operand_types
[1]))
2187 /* Check if other direction is valid ... */
2188 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2191 /* Try reversing direction of operands. */
2192 overlap0
= i
.types
[0] & t
->operand_types
[1];
2193 overlap1
= i
.types
[1] & t
->operand_types
[0];
2194 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
2195 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
2196 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2197 t
->operand_types
[1],
2198 overlap1
, i
.types
[1],
2199 t
->operand_types
[0]))
2201 /* Does not match either direction. */
2204 /* found_reverse_match holds which of D or FloatDR
2206 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2208 /* Found a forward 2 operand match here. */
2209 else if (t
->operands
== 3)
2211 /* Here we make use of the fact that there are no
2212 reverse match 3 operand instructions, and all 3
2213 operand instructions only need to be checked for
2214 register consistency between operands 2 and 3. */
2215 overlap2
= i
.types
[2] & t
->operand_types
[2];
2216 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
2217 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
2218 t
->operand_types
[1],
2219 overlap2
, i
.types
[2],
2220 t
->operand_types
[2]))
2224 /* Found either forward/reverse 2 or 3 operand match here:
2225 slip through to break. */
2227 if (t
->cpu_flags
& ~cpu_arch_flags
)
2229 found_reverse_match
= 0;
2232 /* We've found a match; break out of loop. */
2236 if (t
== current_templates
->end
)
2238 /* We found no match. */
2239 as_bad (_("suffix or operands invalid for `%s'"),
2240 current_templates
->start
->name
);
2244 if (!quiet_warnings
)
2247 && ((i
.types
[0] & JumpAbsolute
)
2248 != (t
->operand_types
[0] & JumpAbsolute
)))
2250 as_warn (_("indirect %s without `*'"), t
->name
);
2253 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2254 == (IsPrefix
| IgnoreSize
))
2256 /* Warn them that a data or address size prefix doesn't
2257 affect assembly of the next line of code. */
2258 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2262 /* Copy the template we found. */
2264 if (found_reverse_match
)
2266 /* If we found a reverse match we must alter the opcode
2267 direction bit. found_reverse_match holds bits to change
2268 (different for int & float insns). */
2270 i
.tm
.base_opcode
^= found_reverse_match
;
2272 i
.tm
.operand_types
[0] = t
->operand_types
[1];
2273 i
.tm
.operand_types
[1] = t
->operand_types
[0];
2282 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2283 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2285 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2287 as_bad (_("`%s' operand %d must use `%%es' segment"),
2292 /* There's only ever one segment override allowed per instruction.
2293 This instruction possibly has a legal segment override on the
2294 second operand, so copy the segment to where non-string
2295 instructions store it, allowing common code. */
2296 i
.seg
[0] = i
.seg
[1];
2298 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2300 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2302 as_bad (_("`%s' operand %d must use `%%es' segment"),
2312 process_suffix (void)
2314 /* If matched instruction specifies an explicit instruction mnemonic
2316 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2318 if (i
.tm
.opcode_modifier
& Size16
)
2319 i
.suffix
= WORD_MNEM_SUFFIX
;
2320 else if (i
.tm
.opcode_modifier
& Size64
)
2321 i
.suffix
= QWORD_MNEM_SUFFIX
;
2323 i
.suffix
= LONG_MNEM_SUFFIX
;
2325 else if (i
.reg_operands
)
2327 /* If there's no instruction mnemonic suffix we try to invent one
2328 based on register operands. */
2331 /* We take i.suffix from the last register operand specified,
2332 Destination register type is more significant than source
2336 for (op
= i
.operands
; --op
>= 0;)
2337 if ((i
.types
[op
] & Reg
)
2338 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2340 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2341 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2342 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2347 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2349 if (!check_byte_reg ())
2352 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2354 if (!check_long_reg ())
2357 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2359 if (!check_qword_reg ())
2362 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2364 if (!check_word_reg ())
2367 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2368 /* Do nothing if the instruction is going to ignore the prefix. */
2373 else if ((i
.tm
.opcode_modifier
& DefaultSize
)
2375 /* exclude fldenv/frstor/fsave/fstenv */
2376 && (i
.tm
.opcode_modifier
& No_sSuf
))
2378 i
.suffix
= stackop_size
;
2380 else if (intel_syntax
2382 && ((i
.tm
.operand_types
[0] & JumpAbsolute
)
2383 || (i
.tm
.opcode_modifier
& (JumpByte
|JumpInterSegment
))
2384 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
2385 && i
.tm
.extension_opcode
<= 3)))
2390 if (!(i
.tm
.opcode_modifier
& No_qSuf
))
2392 i
.suffix
= QWORD_MNEM_SUFFIX
;
2396 if (!(i
.tm
.opcode_modifier
& No_lSuf
))
2397 i
.suffix
= LONG_MNEM_SUFFIX
;
2400 if (!(i
.tm
.opcode_modifier
& No_wSuf
))
2401 i
.suffix
= WORD_MNEM_SUFFIX
;
2410 if (i
.tm
.opcode_modifier
& W
)
2412 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2418 unsigned int suffixes
= ~i
.tm
.opcode_modifier
2426 if ((i
.tm
.opcode_modifier
& W
)
2427 || ((suffixes
& (suffixes
- 1))
2428 && !(i
.tm
.opcode_modifier
& (DefaultSize
| IgnoreSize
))))
2430 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2436 /* Change the opcode based on the operand size given by i.suffix;
2437 We don't need to change things for byte insns. */
2439 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2441 /* It's not a byte, select word/dword operation. */
2442 if (i
.tm
.opcode_modifier
& W
)
2444 if (i
.tm
.opcode_modifier
& ShortForm
)
2445 i
.tm
.base_opcode
|= 8;
2447 i
.tm
.base_opcode
|= 1;
2450 /* Now select between word & dword operations via the operand
2451 size prefix, except for instructions that will ignore this
2453 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2454 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
2455 && !(i
.tm
.opcode_modifier
& (IgnoreSize
| FloatMF
))
2456 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2457 || (flag_code
== CODE_64BIT
2458 && (i
.tm
.opcode_modifier
& JumpByte
))))
2460 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2462 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2463 prefix
= ADDR_PREFIX_OPCODE
;
2465 if (!add_prefix (prefix
))
2469 /* Set mode64 for an operand. */
2470 if (i
.suffix
== QWORD_MNEM_SUFFIX
2471 && flag_code
== CODE_64BIT
2472 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2473 i
.rex
|= REX_MODE64
;
2475 /* Size floating point instruction. */
2476 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2477 if (i
.tm
.opcode_modifier
& FloatMF
)
2478 i
.tm
.base_opcode
^= 4;
2485 check_byte_reg (void)
2489 for (op
= i
.operands
; --op
>= 0;)
2491 /* If this is an eight bit register, it's OK. If it's the 16 or
2492 32 bit version of an eight bit register, we will just use the
2493 low portion, and that's OK too. */
2494 if (i
.types
[op
] & Reg8
)
2497 /* movzx and movsx should not generate this warning. */
2499 && (i
.tm
.base_opcode
== 0xfb7
2500 || i
.tm
.base_opcode
== 0xfb6
2501 || i
.tm
.base_opcode
== 0x63
2502 || i
.tm
.base_opcode
== 0xfbe
2503 || i
.tm
.base_opcode
== 0xfbf))
2506 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4)
2508 /* Prohibit these changes in the 64bit mode, since the
2509 lowering is more complicated. */
2510 if (flag_code
== CODE_64BIT
2511 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2513 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2514 i
.op
[op
].regs
->reg_name
,
2518 #if REGISTER_WARNINGS
2520 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2521 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2522 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
2523 ? REGNAM_AL
- REGNAM_AX
2524 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2525 i
.op
[op
].regs
->reg_name
,
2530 /* Any other register is bad. */
2531 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2533 | Control
| Debug
| Test
2534 | FloatReg
| FloatAcc
))
2536 as_bad (_("`%%%s' not allowed with `%s%c'"),
2537 i
.op
[op
].regs
->reg_name
,
2551 for (op
= i
.operands
; --op
>= 0;)
2552 /* Reject eight bit registers, except where the template requires
2553 them. (eg. movzb) */
2554 if ((i
.types
[op
] & Reg8
) != 0
2555 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2557 as_bad (_("`%%%s' not allowed with `%s%c'"),
2558 i
.op
[op
].regs
->reg_name
,
2563 /* Warn if the e prefix on a general reg is missing. */
2564 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2565 && (i
.types
[op
] & Reg16
) != 0
2566 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2568 /* Prohibit these changes in the 64bit mode, since the
2569 lowering is more complicated. */
2570 if (flag_code
== CODE_64BIT
)
2572 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2573 i
.op
[op
].regs
->reg_name
,
2577 #if REGISTER_WARNINGS
2579 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2580 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2581 i
.op
[op
].regs
->reg_name
,
2585 /* Warn if the r prefix on a general reg is missing. */
2586 else if ((i
.types
[op
] & Reg64
) != 0
2587 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2589 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2590 i
.op
[op
].regs
->reg_name
,
2602 for (op
= i
.operands
; --op
>= 0; )
2603 /* Reject eight bit registers, except where the template requires
2604 them. (eg. movzb) */
2605 if ((i
.types
[op
] & Reg8
) != 0
2606 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2608 as_bad (_("`%%%s' not allowed with `%s%c'"),
2609 i
.op
[op
].regs
->reg_name
,
2614 /* Warn if the e prefix on a general reg is missing. */
2615 else if (((i
.types
[op
] & Reg16
) != 0
2616 || (i
.types
[op
] & Reg32
) != 0)
2617 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2619 /* Prohibit these changes in the 64bit mode, since the
2620 lowering is more complicated. */
2621 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2622 i
.op
[op
].regs
->reg_name
,
2633 for (op
= i
.operands
; --op
>= 0;)
2634 /* Reject eight bit registers, except where the template requires
2635 them. (eg. movzb) */
2636 if ((i
.types
[op
] & Reg8
) != 0
2637 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2639 as_bad (_("`%%%s' not allowed with `%s%c'"),
2640 i
.op
[op
].regs
->reg_name
,
2645 /* Warn if the e prefix on a general reg is present. */
2646 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2647 && (i
.types
[op
] & Reg32
) != 0
2648 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
2650 /* Prohibit these changes in the 64bit mode, since the
2651 lowering is more complicated. */
2652 if (flag_code
== CODE_64BIT
)
2654 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2655 i
.op
[op
].regs
->reg_name
,
2660 #if REGISTER_WARNINGS
2661 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2662 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2663 i
.op
[op
].regs
->reg_name
,
2673 unsigned int overlap0
, overlap1
, overlap2
;
2675 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
2676 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
))
2677 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2678 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2679 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2683 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2685 : (i
.suffix
== WORD_MNEM_SUFFIX
2687 : (i
.suffix
== QWORD_MNEM_SUFFIX
2691 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2692 || overlap0
== (Imm16
| Imm32
)
2693 || overlap0
== (Imm16
| Imm32S
))
2695 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2698 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2699 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2700 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2702 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2706 i
.types
[0] = overlap0
;
2708 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
2709 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
| Imm64
))
2710 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2711 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2712 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2716 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2718 : (i
.suffix
== WORD_MNEM_SUFFIX
2720 : (i
.suffix
== QWORD_MNEM_SUFFIX
2724 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2725 || overlap1
== (Imm16
| Imm32
)
2726 || overlap1
== (Imm16
| Imm32S
))
2728 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2731 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2732 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2733 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2735 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2739 i
.types
[1] = overlap1
;
2741 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
2742 assert ((overlap2
& Imm
) == 0);
2743 i
.types
[2] = overlap2
;
2751 /* Default segment register this instruction will use for memory
2752 accesses. 0 means unknown. This is only for optimizing out
2753 unnecessary segment overrides. */
2754 const seg_entry
*default_seg
= 0;
2756 /* The imul $imm, %reg instruction is converted into
2757 imul $imm, %reg, %reg, and the clr %reg instruction
2758 is converted into xor %reg, %reg. */
2759 if (i
.tm
.opcode_modifier
& regKludge
)
2761 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2762 /* Pretend we saw the extra register operand. */
2763 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2764 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2765 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2769 if (i
.tm
.opcode_modifier
& ShortForm
)
2771 /* The register or float register operand is in operand 0 or 1. */
2772 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2773 /* Register goes in low 3 bits of opcode. */
2774 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2775 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2777 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2779 /* Warn about some common errors, but press on regardless.
2780 The first case can be generated by gcc (<= 2.8.1). */
2781 if (i
.operands
== 2)
2783 /* Reversed arguments on faddp, fsubp, etc. */
2784 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2785 i
.op
[1].regs
->reg_name
,
2786 i
.op
[0].regs
->reg_name
);
2790 /* Extraneous `l' suffix on fp insn. */
2791 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2792 i
.op
[0].regs
->reg_name
);
2796 else if (i
.tm
.opcode_modifier
& Modrm
)
2798 /* The opcode is completed (modulo i.tm.extension_opcode which
2799 must be put into the modrm byte). Now, we make the modrm and
2800 index base bytes based on all the info we've collected. */
2802 default_seg
= build_modrm_byte ();
2804 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2806 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2807 && i
.op
[0].regs
->reg_num
== 1)
2809 as_bad (_("you can't `pop %%cs'"));
2812 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2813 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
2816 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
2820 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2822 /* For the string instructions that allow a segment override
2823 on one of their operands, the default segment is ds. */
2827 if (i
.tm
.base_opcode
== 0x8d /* lea */ && i
.seg
[0] && !quiet_warnings
)
2828 as_warn (_("segment override on `lea' is ineffectual"));
2830 /* If a segment was explicitly specified, and the specified segment
2831 is not the default, use an opcode prefix to select it. If we
2832 never figured out what the default segment is, then default_seg
2833 will be zero at this point, and the specified segment prefix will
2835 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2837 if (!add_prefix (i
.seg
[0]->seg_prefix
))
2843 static const seg_entry
*
2846 const seg_entry
*default_seg
= 0;
2848 /* i.reg_operands MUST be the number of real register operands;
2849 implicit registers do not count. */
2850 if (i
.reg_operands
== 2)
2852 unsigned int source
, dest
;
2853 source
= ((i
.types
[0]
2854 & (Reg
| RegMMX
| RegXMM
2856 | Control
| Debug
| Test
))
2861 /* One of the register operands will be encoded in the i.tm.reg
2862 field, the other in the combined i.tm.mode and i.tm.regmem
2863 fields. If no form of this instruction supports a memory
2864 destination operand, then we assume the source operand may
2865 sometimes be a memory operand and so we need to store the
2866 destination in the i.rm.reg field. */
2867 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2869 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2870 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2871 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2873 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2878 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2879 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2880 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2882 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2885 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_EXTX
| REX_EXTZ
)))
2887 if (!((i
.types
[0] | i
.types
[1]) & Control
))
2889 i
.rex
&= ~(REX_EXTX
| REX_EXTZ
);
2890 add_prefix (LOCK_PREFIX_OPCODE
);
2894 { /* If it's not 2 reg operands... */
2897 unsigned int fake_zero_displacement
= 0;
2898 unsigned int op
= ((i
.types
[0] & AnyMem
)
2900 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2904 if (i
.base_reg
== 0)
2907 if (!i
.disp_operands
)
2908 fake_zero_displacement
= 1;
2909 if (i
.index_reg
== 0)
2911 /* Operand is just <disp> */
2912 if (flag_code
== CODE_64BIT
)
2914 /* 64bit mode overwrites the 32bit absolute
2915 addressing by RIP relative addressing and
2916 absolute addressing is encoded by one of the
2917 redundant SIB forms. */
2918 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2919 i
.sib
.base
= NO_BASE_REGISTER
;
2920 i
.sib
.index
= NO_INDEX_REGISTER
;
2921 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0) ? Disp32S
: Disp32
);
2923 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2925 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2926 i
.types
[op
] = Disp16
;
2930 i
.rm
.regmem
= NO_BASE_REGISTER
;
2931 i
.types
[op
] = Disp32
;
2934 else /* !i.base_reg && i.index_reg */
2936 i
.sib
.index
= i
.index_reg
->reg_num
;
2937 i
.sib
.base
= NO_BASE_REGISTER
;
2938 i
.sib
.scale
= i
.log2_scale_factor
;
2939 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2940 i
.types
[op
] &= ~Disp
;
2941 if (flag_code
!= CODE_64BIT
)
2942 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2944 i
.types
[op
] |= Disp32S
;
2945 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2949 /* RIP addressing for 64bit mode. */
2950 else if (i
.base_reg
->reg_type
== BaseIndex
)
2952 i
.rm
.regmem
= NO_BASE_REGISTER
;
2953 i
.types
[op
] &= ~ Disp
;
2954 i
.types
[op
] |= Disp32S
;
2955 i
.flags
[op
] = Operand_PCrel
;
2956 if (! i
.disp_operands
)
2957 fake_zero_displacement
= 1;
2959 else if (i
.base_reg
->reg_type
& Reg16
)
2961 switch (i
.base_reg
->reg_num
)
2964 if (i
.index_reg
== 0)
2966 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2967 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2971 if (i
.index_reg
== 0)
2974 if ((i
.types
[op
] & Disp
) == 0)
2976 /* fake (%bp) into 0(%bp) */
2977 i
.types
[op
] |= Disp8
;
2978 fake_zero_displacement
= 1;
2981 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2982 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2984 default: /* (%si) -> 4 or (%di) -> 5 */
2985 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2987 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2989 else /* i.base_reg and 32/64 bit mode */
2991 if (flag_code
== CODE_64BIT
2992 && (i
.types
[op
] & Disp
))
2993 i
.types
[op
] = (i
.types
[op
] & Disp8
) | (i
.prefix
[ADDR_PREFIX
] == 0 ? Disp32S
: Disp32
);
2995 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2996 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
2998 i
.sib
.base
= i
.base_reg
->reg_num
;
2999 /* x86-64 ignores REX prefix bit here to avoid decoder
3001 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
3004 if (i
.disp_operands
== 0)
3006 fake_zero_displacement
= 1;
3007 i
.types
[op
] |= Disp8
;
3010 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
3014 i
.sib
.scale
= i
.log2_scale_factor
;
3015 if (i
.index_reg
== 0)
3017 /* <disp>(%esp) becomes two byte modrm with no index
3018 register. We've already stored the code for esp
3019 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3020 Any base register besides %esp will not use the
3021 extra modrm byte. */
3022 i
.sib
.index
= NO_INDEX_REGISTER
;
3023 #if !SCALE1_WHEN_NO_INDEX
3024 /* Another case where we force the second modrm byte. */
3025 if (i
.log2_scale_factor
)
3026 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3031 i
.sib
.index
= i
.index_reg
->reg_num
;
3032 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3033 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3036 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3039 if (fake_zero_displacement
)
3041 /* Fakes a zero displacement assuming that i.types[op]
3042 holds the correct displacement size. */
3045 assert (i
.op
[op
].disps
== 0);
3046 exp
= &disp_expressions
[i
.disp_operands
++];
3047 i
.op
[op
].disps
= exp
;
3048 exp
->X_op
= O_constant
;
3049 exp
->X_add_number
= 0;
3050 exp
->X_add_symbol
= (symbolS
*) 0;
3051 exp
->X_op_symbol
= (symbolS
*) 0;
3055 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3056 (if any) based on i.tm.extension_opcode. Again, we must be
3057 careful to make sure that segment/control/debug/test/MMX
3058 registers are coded into the i.rm.reg field. */
3063 & (Reg
| RegMMX
| RegXMM
3065 | Control
| Debug
| Test
))
3068 & (Reg
| RegMMX
| RegXMM
3070 | Control
| Debug
| Test
))
3073 /* If there is an extension opcode to put here, the register
3074 number must be put into the regmem field. */
3075 if (i
.tm
.extension_opcode
!= None
)
3077 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
3078 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3083 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
3084 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3088 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3089 must set it to 3 to indicate this is a register operand
3090 in the regmem field. */
3091 if (!i
.mem_operands
)
3095 /* Fill in i.rm.reg field with extension opcode (if any). */
3096 if (i
.tm
.extension_opcode
!= None
)
3097 i
.rm
.reg
= i
.tm
.extension_opcode
;
3108 relax_substateT subtype
;
3113 if (flag_code
== CODE_16BIT
)
3117 if (i
.prefix
[DATA_PREFIX
] != 0)
3123 /* Pentium4 branch hints. */
3124 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3125 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3130 if (i
.prefix
[REX_PREFIX
] != 0)
3136 if (i
.prefixes
!= 0 && !intel_syntax
)
3137 as_warn (_("skipping prefixes on this instruction"));
3139 /* It's always a symbol; End frag & setup for relax.
3140 Make sure there is enough room in this frag for the largest
3141 instruction we may generate in md_convert_frag. This is 2
3142 bytes for the opcode and room for the prefix and largest
3144 frag_grow (prefix
+ 2 + 4);
3145 /* Prefix and 1 opcode byte go in fr_fix. */
3146 p
= frag_more (prefix
+ 1);
3147 if (i
.prefix
[DATA_PREFIX
] != 0)
3148 *p
++ = DATA_PREFIX_OPCODE
;
3149 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
3150 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
3151 *p
++ = i
.prefix
[SEG_PREFIX
];
3152 if (i
.prefix
[REX_PREFIX
] != 0)
3153 *p
++ = i
.prefix
[REX_PREFIX
];
3154 *p
= i
.tm
.base_opcode
;
3156 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
3157 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
3158 else if ((cpu_arch_flags
& Cpu386
) != 0)
3159 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
3161 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
3164 sym
= i
.op
[0].disps
->X_add_symbol
;
3165 off
= i
.op
[0].disps
->X_add_number
;
3167 if (i
.op
[0].disps
->X_op
!= O_constant
3168 && i
.op
[0].disps
->X_op
!= O_symbol
)
3170 /* Handle complex expressions. */
3171 sym
= make_expr_symbol (i
.op
[0].disps
);
3175 /* 1 possible extra opcode + 4 byte displacement go in var part.
3176 Pass reloc in fr_var. */
3177 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
3187 if (i
.tm
.opcode_modifier
& JumpByte
)
3189 /* This is a loop or jecxz type instruction. */
3191 if (i
.prefix
[ADDR_PREFIX
] != 0)
3193 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3196 /* Pentium4 branch hints. */
3197 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3198 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3200 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3209 if (flag_code
== CODE_16BIT
)
3212 if (i
.prefix
[DATA_PREFIX
] != 0)
3214 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3224 if (i
.prefix
[REX_PREFIX
] != 0)
3226 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3230 if (i
.prefixes
!= 0 && !intel_syntax
)
3231 as_warn (_("skipping prefixes on this instruction"));
3233 p
= frag_more (1 + size
);
3234 *p
++ = i
.tm
.base_opcode
;
3236 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3237 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3239 /* All jumps handled here are signed, but don't use a signed limit
3240 check for 32 and 16 bit jumps as we want to allow wrap around at
3241 4G and 64k respectively. */
3243 fixP
->fx_signed
= 1;
3247 output_interseg_jump ()
3255 if (flag_code
== CODE_16BIT
)
3259 if (i
.prefix
[DATA_PREFIX
] != 0)
3265 if (i
.prefix
[REX_PREFIX
] != 0)
3275 if (i
.prefixes
!= 0 && !intel_syntax
)
3276 as_warn (_("skipping prefixes on this instruction"));
3278 /* 1 opcode; 2 segment; offset */
3279 p
= frag_more (prefix
+ 1 + 2 + size
);
3281 if (i
.prefix
[DATA_PREFIX
] != 0)
3282 *p
++ = DATA_PREFIX_OPCODE
;
3284 if (i
.prefix
[REX_PREFIX
] != 0)
3285 *p
++ = i
.prefix
[REX_PREFIX
];
3287 *p
++ = i
.tm
.base_opcode
;
3288 if (i
.op
[1].imms
->X_op
== O_constant
)
3290 offsetT n
= i
.op
[1].imms
->X_add_number
;
3293 && !fits_in_unsigned_word (n
)
3294 && !fits_in_signed_word (n
))
3296 as_bad (_("16-bit jump out of range"));
3299 md_number_to_chars (p
, n
, size
);
3302 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3303 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3304 if (i
.op
[0].imms
->X_op
!= O_constant
)
3305 as_bad (_("can't handle non absolute segment in `%s'"),
3307 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3313 fragS
*insn_start_frag
;
3314 offsetT insn_start_off
;
3316 /* Tie dwarf2 debug info to the address at the start of the insn.
3317 We can't do this after the insn has been output as the current
3318 frag may have been closed off. eg. by frag_var. */
3319 dwarf2_emit_insn (0);
3321 insn_start_frag
= frag_now
;
3322 insn_start_off
= frag_now_fix ();
3325 if (i
.tm
.opcode_modifier
& Jump
)
3327 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3329 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3330 output_interseg_jump ();
3333 /* Output normal instructions here. */
3337 /* All opcodes on i386 have either 1 or 2 bytes. We may use one
3338 more higher byte to specify a prefix the instruction
3340 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
3342 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0)
3344 unsigned int prefix
;
3345 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
3347 if (prefix
!= REPE_PREFIX_OPCODE
3348 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
3349 add_prefix (prefix
);
3352 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
3355 /* The prefix bytes. */
3357 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3363 md_number_to_chars (p
, (valueT
) *q
, 1);
3367 /* Now the opcode; be careful about word order here! */
3368 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3370 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3376 /* Put out high byte first: can't use md_number_to_chars! */
3377 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3378 *p
= i
.tm
.base_opcode
& 0xff;
3381 /* Now the modrm byte and sib byte (if present). */
3382 if (i
.tm
.opcode_modifier
& Modrm
)
3385 md_number_to_chars (p
,
3386 (valueT
) (i
.rm
.regmem
<< 0
3390 /* If i.rm.regmem == ESP (4)
3391 && i.rm.mode != (Register mode)
3393 ==> need second modrm byte. */
3394 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3396 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3399 md_number_to_chars (p
,
3400 (valueT
) (i
.sib
.base
<< 0
3402 | i
.sib
.scale
<< 6),
3407 if (i
.disp_operands
)
3408 output_disp (insn_start_frag
, insn_start_off
);
3411 output_imm (insn_start_frag
, insn_start_off
);
3419 #endif /* DEBUG386 */
3423 output_disp (insn_start_frag
, insn_start_off
)
3424 fragS
*insn_start_frag
;
3425 offsetT insn_start_off
;
3430 for (n
= 0; n
< i
.operands
; n
++)
3432 if (i
.types
[n
] & Disp
)
3434 if (i
.op
[n
].disps
->X_op
== O_constant
)
3440 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
3443 if (i
.types
[n
] & Disp8
)
3445 if (i
.types
[n
] & Disp64
)
3448 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3450 p
= frag_more (size
);
3451 md_number_to_chars (p
, val
, size
);
3455 enum bfd_reloc_code_real reloc_type
;
3458 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3460 /* The PC relative address is computed relative
3461 to the instruction boundary, so in case immediate
3462 fields follows, we need to adjust the value. */
3463 if (pcrel
&& i
.imm_operands
)
3468 for (n1
= 0; n1
< i
.operands
; n1
++)
3469 if (i
.types
[n1
] & Imm
)
3471 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3474 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3476 if (i
.types
[n1
] & Imm64
)
3481 /* We should find the immediate. */
3482 if (n1
== i
.operands
)
3484 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3487 if (i
.types
[n
] & Disp32S
)
3490 if (i
.types
[n
] & (Disp16
| Disp64
))
3493 if (i
.types
[n
] & Disp64
)
3497 p
= frag_more (size
);
3498 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
3499 if (reloc_type
== BFD_RELOC_32
3501 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
3502 && (i
.op
[n
].disps
->X_op
== O_symbol
3503 || (i
.op
[n
].disps
->X_op
== O_add
3504 && ((symbol_get_value_expression
3505 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
3510 if (insn_start_frag
== frag_now
)
3511 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3516 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3517 for (fr
= insn_start_frag
->fr_next
;
3518 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3520 add
+= p
- frag_now
->fr_literal
;
3523 /* We don't support dynamic linking on x86-64 yet. */
3524 if (flag_code
== CODE_64BIT
)
3526 reloc_type
= BFD_RELOC_386_GOTPC
;
3527 i
.op
[n
].disps
->X_add_number
+= add
;
3529 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3530 i
.op
[n
].disps
, pcrel
, reloc_type
);
3537 output_imm (insn_start_frag
, insn_start_off
)
3538 fragS
*insn_start_frag
;
3539 offsetT insn_start_off
;
3544 for (n
= 0; n
< i
.operands
; n
++)
3546 if (i
.types
[n
] & Imm
)
3548 if (i
.op
[n
].imms
->X_op
== O_constant
)
3554 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3557 if (i
.types
[n
] & (Imm8
| Imm8S
))
3559 else if (i
.types
[n
] & Imm64
)
3562 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3564 p
= frag_more (size
);
3565 md_number_to_chars (p
, val
, size
);
3569 /* Not absolute_section.
3570 Need a 32-bit fixup (don't support 8bit
3571 non-absolute imms). Try to support other
3573 enum bfd_reloc_code_real reloc_type
;
3577 if ((i
.types
[n
] & (Imm32S
))
3578 && (i
.suffix
== QWORD_MNEM_SUFFIX
3579 || (!i
.suffix
&& (i
.tm
.opcode_modifier
& No_lSuf
))))
3581 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3584 if (i
.types
[n
] & (Imm8
| Imm8S
))
3586 if (i
.types
[n
] & Imm64
)
3590 p
= frag_more (size
);
3591 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3593 /* This is tough to explain. We end up with this one if we
3594 * have operands that look like
3595 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3596 * obtain the absolute address of the GOT, and it is strongly
3597 * preferable from a performance point of view to avoid using
3598 * a runtime relocation for this. The actual sequence of
3599 * instructions often look something like:
3604 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3606 * The call and pop essentially return the absolute address
3607 * of the label .L66 and store it in %ebx. The linker itself
3608 * will ultimately change the first operand of the addl so
3609 * that %ebx points to the GOT, but to keep things simple, the
3610 * .o file must have this operand set so that it generates not
3611 * the absolute address of .L66, but the absolute address of
3612 * itself. This allows the linker itself simply treat a GOTPC
3613 * relocation as asking for a pcrel offset to the GOT to be
3614 * added in, and the addend of the relocation is stored in the
3615 * operand field for the instruction itself.
3617 * Our job here is to fix the operand so that it would add
3618 * the correct offset so that %ebx would point to itself. The
3619 * thing that is tricky is that .-.L66 will point to the
3620 * beginning of the instruction, so we need to further modify
3621 * the operand so that it will point to itself. There are
3622 * other cases where you have something like:
3624 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3626 * and here no correction would be required. Internally in
3627 * the assembler we treat operands of this form as not being
3628 * pcrel since the '.' is explicitly mentioned, and I wonder
3629 * whether it would simplify matters to do it this way. Who
3630 * knows. In earlier versions of the PIC patches, the
3631 * pcrel_adjust field was used to store the correction, but
3632 * since the expression is not pcrel, I felt it would be
3633 * confusing to do it this way. */
3635 if (reloc_type
== BFD_RELOC_32
3637 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3638 && (i
.op
[n
].imms
->X_op
== O_symbol
3639 || (i
.op
[n
].imms
->X_op
== O_add
3640 && ((symbol_get_value_expression
3641 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3646 if (insn_start_frag
== frag_now
)
3647 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3652 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3653 for (fr
= insn_start_frag
->fr_next
;
3654 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3656 add
+= p
- frag_now
->fr_literal
;
3659 /* We don't support dynamic linking on x86-64 yet. */
3660 if (flag_code
== CODE_64BIT
)
3662 reloc_type
= BFD_RELOC_386_GOTPC
;
3663 i
.op
[n
].imms
->X_add_number
+= add
;
3665 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3666 i
.op
[n
].imms
, 0, reloc_type
);
3673 static char *lex_got
PARAMS ((enum bfd_reloc_code_real
*, int *));
3675 /* Parse operands of the form
3676 <symbol>@GOTOFF+<nnn>
3677 and similar .plt or .got references.
3679 If we find one, set up the correct relocation in RELOC and copy the
3680 input string, minus the `@GOTOFF' into a malloc'd buffer for
3681 parsing by the calling routine. Return this buffer, and if ADJUST
3682 is non-null set it to the length of the string we removed from the
3683 input line. Otherwise return NULL. */
3685 lex_got (reloc
, adjust
)
3686 enum bfd_reloc_code_real
*reloc
;
3689 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3690 static const struct {
3692 const enum bfd_reloc_code_real rel
[NUM_FLAG_CODE
];
3694 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
} },
3695 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, 0 } },
3696 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
} },
3697 { "TLSGD", { BFD_RELOC_386_TLS_GD
, 0, BFD_RELOC_X86_64_TLSGD
} },
3698 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
, 0, 0 } },
3699 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD
} },
3700 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
, 0, BFD_RELOC_X86_64_GOTTPOFF
} },
3701 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
, 0, BFD_RELOC_X86_64_TPOFF32
} },
3702 { "NTPOFF", { BFD_RELOC_386_TLS_LE
, 0, 0 } },
3703 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
, 0, BFD_RELOC_X86_64_DTPOFF32
} },
3704 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
, 0, 0 } },
3705 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
, 0, 0 } },
3706 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
} }
3711 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3712 if (is_end_of_line
[(unsigned char) *cp
])
3715 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3719 len
= strlen (gotrel
[j
].str
);
3720 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3722 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3725 char *tmpbuf
, *past_reloc
;
3727 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3731 if (GOT_symbol
== NULL
)
3732 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3734 /* Replace the relocation token with ' ', so that
3735 errors like foo@GOTOFF1 will be detected. */
3737 /* The length of the first part of our input line. */
3738 first
= cp
- input_line_pointer
;
3740 /* The second part goes from after the reloc token until
3741 (and including) an end_of_line char. Don't use strlen
3742 here as the end_of_line char may not be a NUL. */
3743 past_reloc
= cp
+ 1 + len
;
3744 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3746 second
= cp
- past_reloc
;
3748 /* Allocate and copy string. The trailing NUL shouldn't
3749 be necessary, but be safe. */
3750 tmpbuf
= xmalloc (first
+ second
+ 2);
3751 memcpy (tmpbuf
, input_line_pointer
, first
);
3752 tmpbuf
[first
] = ' ';
3753 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3754 tmpbuf
[first
+ second
+ 1] = '\0';
3758 as_bad (_("@%s reloc is not supported in %s bit mode"),
3759 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3764 /* Might be a symbol version string. Don't as_bad here. */
3768 /* x86_cons_fix_new is called via the expression parsing code when a
3769 reloc is needed. We use this hook to get the correct .got reloc. */
3770 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
3773 x86_cons_fix_new (frag
, off
, len
, exp
)
3779 enum bfd_reloc_code_real r
= reloc (len
, 0, 0, got_reloc
);
3780 got_reloc
= NO_RELOC
;
3781 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3785 x86_cons (exp
, size
)
3791 /* Handle @GOTOFF and the like in an expression. */
3793 char *gotfree_input_line
;
3796 save
= input_line_pointer
;
3797 gotfree_input_line
= lex_got (&got_reloc
, &adjust
);
3798 if (gotfree_input_line
)
3799 input_line_pointer
= gotfree_input_line
;
3803 if (gotfree_input_line
)
3805 /* expression () has merrily parsed up to the end of line,
3806 or a comma - in the wrong buffer. Transfer how far
3807 input_line_pointer has moved to the right buffer. */
3808 input_line_pointer
= (save
3809 + (input_line_pointer
- gotfree_input_line
)
3811 free (gotfree_input_line
);
3822 x86_pe_cons_fix_new (frag
, off
, len
, exp
)
3828 enum bfd_reloc_code_real r
= reloc (len
, 0, 0, NO_RELOC
);
3830 if (exp
->X_op
== O_secrel
)
3832 exp
->X_op
= O_symbol
;
3833 r
= BFD_RELOC_32_SECREL
;
3836 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3840 pe_directive_secrel (dummy
)
3841 int dummy ATTRIBUTE_UNUSED
;
3848 if (exp
.X_op
== O_symbol
)
3849 exp
.X_op
= O_secrel
;
3851 emit_expr (&exp
, 4);
3853 while (*input_line_pointer
++ == ',');
3855 input_line_pointer
--;
3856 demand_empty_rest_of_line ();
3861 static int i386_immediate
PARAMS ((char *));
3864 i386_immediate (imm_start
)
3867 char *save_input_line_pointer
;
3869 char *gotfree_input_line
;
3874 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3876 as_bad (_("only 1 or 2 immediate operands are allowed"));
3880 exp
= &im_expressions
[i
.imm_operands
++];
3881 i
.op
[this_operand
].imms
= exp
;
3883 if (is_space_char (*imm_start
))
3886 save_input_line_pointer
= input_line_pointer
;
3887 input_line_pointer
= imm_start
;
3890 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3891 if (gotfree_input_line
)
3892 input_line_pointer
= gotfree_input_line
;
3895 exp_seg
= expression (exp
);
3898 if (*input_line_pointer
)
3899 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3901 input_line_pointer
= save_input_line_pointer
;
3903 if (gotfree_input_line
)
3904 free (gotfree_input_line
);
3907 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3909 /* Missing or bad expr becomes absolute 0. */
3910 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3912 exp
->X_op
= O_constant
;
3913 exp
->X_add_number
= 0;
3914 exp
->X_add_symbol
= (symbolS
*) 0;
3915 exp
->X_op_symbol
= (symbolS
*) 0;
3917 else if (exp
->X_op
== O_constant
)
3919 /* Size it properly later. */
3920 i
.types
[this_operand
] |= Imm64
;
3921 /* If BFD64, sign extend val. */
3922 if (!use_rela_relocations
)
3923 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3924 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3926 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3927 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
3928 && exp_seg
!= absolute_section
3929 && exp_seg
!= text_section
3930 && exp_seg
!= data_section
3931 && exp_seg
!= bss_section
3932 && exp_seg
!= undefined_section
3933 && !bfd_is_com_section (exp_seg
))
3935 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3941 /* This is an address. The size of the address will be
3942 determined later, depending on destination register,
3943 suffix, or the default for the section. */
3944 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3950 static char *i386_scale
PARAMS ((char *));
3957 char *save
= input_line_pointer
;
3959 input_line_pointer
= scale
;
3960 val
= get_absolute_expression ();
3965 i
.log2_scale_factor
= 0;
3968 i
.log2_scale_factor
= 1;
3971 i
.log2_scale_factor
= 2;
3974 i
.log2_scale_factor
= 3;
3978 char sep
= *input_line_pointer
;
3980 *input_line_pointer
= '\0';
3981 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3983 *input_line_pointer
= sep
;
3984 input_line_pointer
= save
;
3988 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
3990 as_warn (_("scale factor of %d without an index register"),
3991 1 << i
.log2_scale_factor
);
3992 #if SCALE1_WHEN_NO_INDEX
3993 i
.log2_scale_factor
= 0;
3996 scale
= input_line_pointer
;
3997 input_line_pointer
= save
;
4001 static int i386_displacement
PARAMS ((char *, char *));
4004 i386_displacement (disp_start
, disp_end
)
4010 char *save_input_line_pointer
;
4012 char *gotfree_input_line
;
4014 int bigdisp
= Disp32
;
4016 if (flag_code
== CODE_64BIT
)
4018 if (i
.prefix
[ADDR_PREFIX
] == 0)
4021 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4023 i
.types
[this_operand
] |= bigdisp
;
4025 exp
= &disp_expressions
[i
.disp_operands
];
4026 i
.op
[this_operand
].disps
= exp
;
4028 save_input_line_pointer
= input_line_pointer
;
4029 input_line_pointer
= disp_start
;
4030 END_STRING_AND_SAVE (disp_end
);
4032 #ifndef GCC_ASM_O_HACK
4033 #define GCC_ASM_O_HACK 0
4036 END_STRING_AND_SAVE (disp_end
+ 1);
4037 if ((i
.types
[this_operand
] & BaseIndex
) != 0
4038 && displacement_string_end
[-1] == '+')
4040 /* This hack is to avoid a warning when using the "o"
4041 constraint within gcc asm statements.
4044 #define _set_tssldt_desc(n,addr,limit,type) \
4045 __asm__ __volatile__ ( \
4047 "movw %w1,2+%0\n\t" \
4049 "movb %b1,4+%0\n\t" \
4050 "movb %4,5+%0\n\t" \
4051 "movb $0,6+%0\n\t" \
4052 "movb %h1,7+%0\n\t" \
4054 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4056 This works great except that the output assembler ends
4057 up looking a bit weird if it turns out that there is
4058 no offset. You end up producing code that looks like:
4071 So here we provide the missing zero. */
4073 *displacement_string_end
= '0';
4077 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
4078 if (gotfree_input_line
)
4079 input_line_pointer
= gotfree_input_line
;
4082 exp_seg
= expression (exp
);
4085 if (*input_line_pointer
)
4086 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4088 RESTORE_END_STRING (disp_end
+ 1);
4090 RESTORE_END_STRING (disp_end
);
4091 input_line_pointer
= save_input_line_pointer
;
4093 if (gotfree_input_line
)
4094 free (gotfree_input_line
);
4097 /* We do this to make sure that the section symbol is in
4098 the symbol table. We will ultimately change the relocation
4099 to be relative to the beginning of the section. */
4100 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
4101 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
4103 if (exp
->X_op
!= O_symbol
)
4105 as_bad (_("bad expression used with @%s"),
4106 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4112 if (S_IS_LOCAL (exp
->X_add_symbol
)
4113 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
4114 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
4115 exp
->X_op
= O_subtract
;
4116 exp
->X_op_symbol
= GOT_symbol
;
4117 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
4118 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
4120 i
.reloc
[this_operand
] = BFD_RELOC_32
;
4123 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4125 /* Missing or bad expr becomes absolute 0. */
4126 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4128 exp
->X_op
= O_constant
;
4129 exp
->X_add_number
= 0;
4130 exp
->X_add_symbol
= (symbolS
*) 0;
4131 exp
->X_op_symbol
= (symbolS
*) 0;
4134 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4135 if (exp
->X_op
!= O_constant
4136 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
4137 && exp_seg
!= absolute_section
4138 && exp_seg
!= text_section
4139 && exp_seg
!= data_section
4140 && exp_seg
!= bss_section
4141 && exp_seg
!= undefined_section
4142 && !bfd_is_com_section (exp_seg
))
4144 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4148 else if (flag_code
== CODE_64BIT
)
4149 i
.types
[this_operand
] |= Disp32S
| Disp32
;
4153 static int i386_index_check
PARAMS ((const char *));
4155 /* Make sure the memory operand we've been dealt is valid.
4156 Return 1 on success, 0 on a failure. */
4159 i386_index_check (operand_string
)
4160 const char *operand_string
;
4163 #if INFER_ADDR_PREFIX
4169 if (flag_code
== CODE_64BIT
)
4171 unsigned RegXX
= (i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
);
4174 && ((i
.base_reg
->reg_type
& RegXX
) == 0)
4175 && (i
.base_reg
->reg_type
!= BaseIndex
4178 && ((i
.index_reg
->reg_type
& (RegXX
| BaseIndex
))
4179 != (RegXX
| BaseIndex
))))
4184 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4188 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
4189 != (Reg16
| BaseIndex
)))
4191 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
4192 != (Reg16
| BaseIndex
))
4194 && i
.base_reg
->reg_num
< 6
4195 && i
.index_reg
->reg_num
>= 6
4196 && i
.log2_scale_factor
== 0))))
4203 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
4205 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
4206 != (Reg32
| BaseIndex
))))
4212 #if INFER_ADDR_PREFIX
4213 if (i
.prefix
[ADDR_PREFIX
] == 0)
4215 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
4217 /* Change the size of any displacement too. At most one of
4218 Disp16 or Disp32 is set.
4219 FIXME. There doesn't seem to be any real need for separate
4220 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4221 Removing them would probably clean up the code quite a lot. */
4222 if (flag_code
!= CODE_64BIT
&& (i
.types
[this_operand
] & (Disp16
| Disp32
)))
4223 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
4228 as_bad (_("`%s' is not a valid base/index expression"),
4232 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4234 flag_code_names
[flag_code
]);
4239 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4243 i386_operand (operand_string
)
4244 char *operand_string
;
4248 char *op_string
= operand_string
;
4250 if (is_space_char (*op_string
))
4253 /* We check for an absolute prefix (differentiating,
4254 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4255 if (*op_string
== ABSOLUTE_PREFIX
)
4258 if (is_space_char (*op_string
))
4260 i
.types
[this_operand
] |= JumpAbsolute
;
4263 /* Check if operand is a register. */
4264 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4265 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
4267 /* Check for a segment override by searching for ':' after a
4268 segment register. */
4270 if (is_space_char (*op_string
))
4272 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
4277 i
.seg
[i
.mem_operands
] = &es
;
4280 i
.seg
[i
.mem_operands
] = &cs
;
4283 i
.seg
[i
.mem_operands
] = &ss
;
4286 i
.seg
[i
.mem_operands
] = &ds
;
4289 i
.seg
[i
.mem_operands
] = &fs
;
4292 i
.seg
[i
.mem_operands
] = &gs
;
4296 /* Skip the ':' and whitespace. */
4298 if (is_space_char (*op_string
))
4301 if (!is_digit_char (*op_string
)
4302 && !is_identifier_char (*op_string
)
4303 && *op_string
!= '('
4304 && *op_string
!= ABSOLUTE_PREFIX
)
4306 as_bad (_("bad memory operand `%s'"), op_string
);
4309 /* Handle case of %es:*foo. */
4310 if (*op_string
== ABSOLUTE_PREFIX
)
4313 if (is_space_char (*op_string
))
4315 i
.types
[this_operand
] |= JumpAbsolute
;
4317 goto do_memory_reference
;
4321 as_bad (_("junk `%s' after register"), op_string
);
4324 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
4325 i
.op
[this_operand
].regs
= r
;
4328 else if (*op_string
== REGISTER_PREFIX
)
4330 as_bad (_("bad register name `%s'"), op_string
);
4333 else if (*op_string
== IMMEDIATE_PREFIX
)
4336 if (i
.types
[this_operand
] & JumpAbsolute
)
4338 as_bad (_("immediate operand illegal with absolute jump"));
4341 if (!i386_immediate (op_string
))
4344 else if (is_digit_char (*op_string
)
4345 || is_identifier_char (*op_string
)
4346 || *op_string
== '(')
4348 /* This is a memory reference of some sort. */
4351 /* Start and end of displacement string expression (if found). */
4352 char *displacement_string_start
;
4353 char *displacement_string_end
;
4355 do_memory_reference
:
4356 if ((i
.mem_operands
== 1
4357 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4358 || i
.mem_operands
== 2)
4360 as_bad (_("too many memory references for `%s'"),
4361 current_templates
->start
->name
);
4365 /* Check for base index form. We detect the base index form by
4366 looking for an ')' at the end of the operand, searching
4367 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4369 base_string
= op_string
+ strlen (op_string
);
4372 if (is_space_char (*base_string
))
4375 /* If we only have a displacement, set-up for it to be parsed later. */
4376 displacement_string_start
= op_string
;
4377 displacement_string_end
= base_string
+ 1;
4379 if (*base_string
== ')')
4382 unsigned int parens_balanced
= 1;
4383 /* We've already checked that the number of left & right ()'s are
4384 equal, so this loop will not be infinite. */
4388 if (*base_string
== ')')
4390 if (*base_string
== '(')
4393 while (parens_balanced
);
4395 temp_string
= base_string
;
4397 /* Skip past '(' and whitespace. */
4399 if (is_space_char (*base_string
))
4402 if (*base_string
== ','
4403 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4404 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
4406 displacement_string_end
= temp_string
;
4408 i
.types
[this_operand
] |= BaseIndex
;
4412 base_string
= end_op
;
4413 if (is_space_char (*base_string
))
4417 /* There may be an index reg or scale factor here. */
4418 if (*base_string
== ',')
4421 if (is_space_char (*base_string
))
4424 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4425 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
4427 base_string
= end_op
;
4428 if (is_space_char (*base_string
))
4430 if (*base_string
== ',')
4433 if (is_space_char (*base_string
))
4436 else if (*base_string
!= ')')
4438 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4443 else if (*base_string
== REGISTER_PREFIX
)
4445 as_bad (_("bad register name `%s'"), base_string
);
4449 /* Check for scale factor. */
4450 if (*base_string
!= ')')
4452 char *end_scale
= i386_scale (base_string
);
4457 base_string
= end_scale
;
4458 if (is_space_char (*base_string
))
4460 if (*base_string
!= ')')
4462 as_bad (_("expecting `)' after scale factor in `%s'"),
4467 else if (!i
.index_reg
)
4469 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4474 else if (*base_string
!= ')')
4476 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4481 else if (*base_string
== REGISTER_PREFIX
)
4483 as_bad (_("bad register name `%s'"), base_string
);
4488 /* If there's an expression beginning the operand, parse it,
4489 assuming displacement_string_start and
4490 displacement_string_end are meaningful. */
4491 if (displacement_string_start
!= displacement_string_end
)
4493 if (!i386_displacement (displacement_string_start
,
4494 displacement_string_end
))
4498 /* Special case for (%dx) while doing input/output op. */
4500 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
4502 && i
.log2_scale_factor
== 0
4503 && i
.seg
[i
.mem_operands
] == 0
4504 && (i
.types
[this_operand
] & Disp
) == 0)
4506 i
.types
[this_operand
] = InOutPortReg
;
4510 if (i386_index_check (operand_string
) == 0)
4516 /* It's not a memory operand; argh! */
4517 as_bad (_("invalid char %s beginning operand %d `%s'"),
4518 output_invalid (*op_string
),
4523 return 1; /* Normal return. */
4526 /* md_estimate_size_before_relax()
4528 Called just before relax() for rs_machine_dependent frags. The x86
4529 assembler uses these frags to handle variable size jump
4532 Any symbol that is now undefined will not become defined.
4533 Return the correct fr_subtype in the frag.
4534 Return the initial "guess for variable size of frag" to caller.
4535 The guess is actually the growth beyond the fixed part. Whatever
4536 we do to grow the fixed or variable part contributes to our
4540 md_estimate_size_before_relax (fragP
, segment
)
4544 /* We've already got fragP->fr_subtype right; all we have to do is
4545 check for un-relaxable symbols. On an ELF system, we can't relax
4546 an externally visible symbol, because it may be overridden by a
4548 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4549 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4550 || (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4551 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
4552 || S_IS_WEAK (fragP
->fr_symbol
)))
4556 /* Symbol is undefined in this segment, or we need to keep a
4557 reloc so that weak symbols can be overridden. */
4558 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
4559 enum bfd_reloc_code_real reloc_type
;
4560 unsigned char *opcode
;
4563 if (fragP
->fr_var
!= NO_RELOC
)
4564 reloc_type
= fragP
->fr_var
;
4566 reloc_type
= BFD_RELOC_16_PCREL
;
4568 reloc_type
= BFD_RELOC_32_PCREL
;
4570 old_fr_fix
= fragP
->fr_fix
;
4571 opcode
= (unsigned char *) fragP
->fr_opcode
;
4573 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4576 /* Make jmp (0xeb) a (d)word displacement jump. */
4578 fragP
->fr_fix
+= size
;
4579 fix_new (fragP
, old_fr_fix
, size
,
4581 fragP
->fr_offset
, 1,
4587 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
4589 /* Negate the condition, and branch past an
4590 unconditional jump. */
4593 /* Insert an unconditional jump. */
4595 /* We added two extra opcode bytes, and have a two byte
4597 fragP
->fr_fix
+= 2 + 2;
4598 fix_new (fragP
, old_fr_fix
+ 2, 2,
4600 fragP
->fr_offset
, 1,
4607 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
4612 fixP
= fix_new (fragP
, old_fr_fix
, 1,
4614 fragP
->fr_offset
, 1,
4616 fixP
->fx_signed
= 1;
4620 /* This changes the byte-displacement jump 0x7N
4621 to the (d)word-displacement jump 0x0f,0x8N. */
4622 opcode
[1] = opcode
[0] + 0x10;
4623 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4624 /* We've added an opcode byte. */
4625 fragP
->fr_fix
+= 1 + size
;
4626 fix_new (fragP
, old_fr_fix
+ 1, size
,
4628 fragP
->fr_offset
, 1,
4633 BAD_CASE (fragP
->fr_subtype
);
4637 return fragP
->fr_fix
- old_fr_fix
;
4640 /* Guess size depending on current relax state. Initially the relax
4641 state will correspond to a short jump and we return 1, because
4642 the variable part of the frag (the branch offset) is one byte
4643 long. However, we can relax a section more than once and in that
4644 case we must either set fr_subtype back to the unrelaxed state,
4645 or return the value for the appropriate branch. */
4646 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4649 /* Called after relax() is finished.
4651 In: Address of frag.
4652 fr_type == rs_machine_dependent.
4653 fr_subtype is what the address relaxed to.
4655 Out: Any fixSs and constants are set up.
4656 Caller will turn frag into a ".space 0". */
4659 md_convert_frag (abfd
, sec
, fragP
)
4660 bfd
*abfd ATTRIBUTE_UNUSED
;
4661 segT sec ATTRIBUTE_UNUSED
;
4664 unsigned char *opcode
;
4665 unsigned char *where_to_put_displacement
= NULL
;
4666 offsetT target_address
;
4667 offsetT opcode_address
;
4668 unsigned int extension
= 0;
4669 offsetT displacement_from_opcode_start
;
4671 opcode
= (unsigned char *) fragP
->fr_opcode
;
4673 /* Address we want to reach in file space. */
4674 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4676 /* Address opcode resides at in file space. */
4677 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4679 /* Displacement from opcode start to fill into instruction. */
4680 displacement_from_opcode_start
= target_address
- opcode_address
;
4682 if ((fragP
->fr_subtype
& BIG
) == 0)
4684 /* Don't have to change opcode. */
4685 extension
= 1; /* 1 opcode + 1 displacement */
4686 where_to_put_displacement
= &opcode
[1];
4690 if (no_cond_jump_promotion
4691 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4692 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4694 switch (fragP
->fr_subtype
)
4696 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4697 extension
= 4; /* 1 opcode + 4 displacement */
4699 where_to_put_displacement
= &opcode
[1];
4702 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4703 extension
= 2; /* 1 opcode + 2 displacement */
4705 where_to_put_displacement
= &opcode
[1];
4708 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4709 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4710 extension
= 5; /* 2 opcode + 4 displacement */
4711 opcode
[1] = opcode
[0] + 0x10;
4712 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4713 where_to_put_displacement
= &opcode
[2];
4716 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4717 extension
= 3; /* 2 opcode + 2 displacement */
4718 opcode
[1] = opcode
[0] + 0x10;
4719 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4720 where_to_put_displacement
= &opcode
[2];
4723 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4728 where_to_put_displacement
= &opcode
[3];
4732 BAD_CASE (fragP
->fr_subtype
);
4737 /* Now put displacement after opcode. */
4738 md_number_to_chars ((char *) where_to_put_displacement
,
4739 (valueT
) (displacement_from_opcode_start
- extension
),
4740 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4741 fragP
->fr_fix
+= extension
;
4744 /* Size of byte displacement jmp. */
4745 int md_short_jump_size
= 2;
4747 /* Size of dword displacement jmp. */
4748 int md_long_jump_size
= 5;
4750 /* Size of relocation record. */
4751 const int md_reloc_size
= 8;
4754 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4756 addressT from_addr
, to_addr
;
4757 fragS
*frag ATTRIBUTE_UNUSED
;
4758 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4762 offset
= to_addr
- (from_addr
+ 2);
4763 /* Opcode for byte-disp jump. */
4764 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4765 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4769 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4771 addressT from_addr
, to_addr
;
4772 fragS
*frag ATTRIBUTE_UNUSED
;
4773 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4777 offset
= to_addr
- (from_addr
+ 5);
4778 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4779 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4782 /* Apply a fixup (fixS) to segment data, once it has been determined
4783 by our caller that we have all the info we need to fix it up.
4785 On the 386, immediates, displacements, and data pointers are all in
4786 the same (little-endian) format, so we don't need to care about which
4790 md_apply_fix3 (fixP
, valP
, seg
)
4791 /* The fix we're to put in. */
4793 /* Pointer to the value of the bits. */
4795 /* Segment fix is from. */
4796 segT seg ATTRIBUTE_UNUSED
;
4798 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4799 valueT value
= *valP
;
4801 #if !defined (TE_Mach)
4804 switch (fixP
->fx_r_type
)
4810 case BFD_RELOC_X86_64_32S
:
4811 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4814 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4817 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4822 if (fixP
->fx_addsy
!= NULL
4823 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4824 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4825 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4826 && !use_rela_relocations
)
4828 /* This is a hack. There should be a better way to handle this.
4829 This covers for the fact that bfd_install_relocation will
4830 subtract the current location (for partial_inplace, PC relative
4831 relocations); see more below. */
4833 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4835 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4838 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4840 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4841 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4843 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4846 || (symbol_section_p (fixP
->fx_addsy
)
4847 && sym_seg
!= absolute_section
))
4848 && !generic_force_reloc (fixP
))
4850 /* Yes, we add the values in twice. This is because
4851 bfd_install_relocation subtracts them out again. I think
4852 bfd_install_relocation is broken, but I don't dare change
4854 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4858 #if defined (OBJ_COFF) && defined (TE_PE)
4859 /* For some reason, the PE format does not store a
4860 section address offset for a PC relative symbol. */
4861 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
4862 #if defined(BFD_ASSEMBLER) || defined(S_IS_WEAK)
4863 || S_IS_WEAK (fixP
->fx_addsy
)
4866 value
+= md_pcrel_from (fixP
);
4870 /* Fix a few things - the dynamic linker expects certain values here,
4871 and we must not disappoint it. */
4872 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4873 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4875 switch (fixP
->fx_r_type
)
4877 case BFD_RELOC_386_PLT32
:
4878 case BFD_RELOC_X86_64_PLT32
:
4879 /* Make the jump instruction point to the address of the operand. At
4880 runtime we merely add the offset to the actual PLT entry. */
4884 case BFD_RELOC_386_TLS_GD
:
4885 case BFD_RELOC_386_TLS_LDM
:
4886 case BFD_RELOC_386_TLS_IE_32
:
4887 case BFD_RELOC_386_TLS_IE
:
4888 case BFD_RELOC_386_TLS_GOTIE
:
4889 case BFD_RELOC_X86_64_TLSGD
:
4890 case BFD_RELOC_X86_64_TLSLD
:
4891 case BFD_RELOC_X86_64_GOTTPOFF
:
4892 value
= 0; /* Fully resolved at runtime. No addend. */
4894 case BFD_RELOC_386_TLS_LE
:
4895 case BFD_RELOC_386_TLS_LDO_32
:
4896 case BFD_RELOC_386_TLS_LE_32
:
4897 case BFD_RELOC_X86_64_DTPOFF32
:
4898 case BFD_RELOC_X86_64_TPOFF32
:
4899 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
4902 case BFD_RELOC_386_GOT32
:
4903 case BFD_RELOC_X86_64_GOT32
:
4904 value
= 0; /* Fully resolved at runtime. No addend. */
4907 case BFD_RELOC_VTABLE_INHERIT
:
4908 case BFD_RELOC_VTABLE_ENTRY
:
4915 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4917 #endif /* !defined (TE_Mach) */
4919 /* Are we finished with this relocation now? */
4920 if (fixP
->fx_addsy
== NULL
)
4922 else if (use_rela_relocations
)
4924 fixP
->fx_no_overflow
= 1;
4925 /* Remember value for tc_gen_reloc. */
4926 fixP
->fx_addnumber
= value
;
4930 md_number_to_chars (p
, value
, fixP
->fx_size
);
4933 #define MAX_LITTLENUMS 6
4935 /* Turn the string pointed to by litP into a floating point constant
4936 of type TYPE, and emit the appropriate bytes. The number of
4937 LITTLENUMS emitted is stored in *SIZEP. An error message is
4938 returned, or NULL on OK. */
4941 md_atof (type
, litP
, sizeP
)
4947 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4948 LITTLENUM_TYPE
*wordP
;
4970 return _("Bad call to md_atof ()");
4972 t
= atof_ieee (input_line_pointer
, type
, words
);
4974 input_line_pointer
= t
;
4976 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4977 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4978 the bigendian 386. */
4979 for (wordP
= words
+ prec
- 1; prec
--;)
4981 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4982 litP
+= sizeof (LITTLENUM_TYPE
);
4987 static char output_invalid_buf
[8];
4994 sprintf (output_invalid_buf
, "'%c'", c
);
4996 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4997 return output_invalid_buf
;
5000 /* REG_STRING starts *before* REGISTER_PREFIX. */
5002 static const reg_entry
*
5003 parse_register (reg_string
, end_op
)
5007 char *s
= reg_string
;
5009 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
5012 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5013 if (*s
== REGISTER_PREFIX
)
5016 if (is_space_char (*s
))
5020 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
5022 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
5023 return (const reg_entry
*) NULL
;
5027 /* For naked regs, make sure that we are not dealing with an identifier.
5028 This prevents confusing an identifier like `eax_var' with register
5030 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
5031 return (const reg_entry
*) NULL
;
5035 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
5037 /* Handle floating point regs, allowing spaces in the (i) part. */
5038 if (r
== i386_regtab
/* %st is first entry of table */)
5040 if (is_space_char (*s
))
5045 if (is_space_char (*s
))
5047 if (*s
>= '0' && *s
<= '7')
5049 r
= &i386_float_regtab
[*s
- '0'];
5051 if (is_space_char (*s
))
5059 /* We have "%st(" then garbage. */
5060 return (const reg_entry
*) NULL
;
5065 && ((r
->reg_flags
& (RegRex64
| RegRex
)) | (r
->reg_type
& Reg64
)) != 0
5066 && (r
->reg_type
!= Control
|| !(cpu_arch_flags
& CpuSledgehammer
))
5067 && flag_code
!= CODE_64BIT
)
5068 return (const reg_entry
*) NULL
;
5073 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5074 const char *md_shortopts
= "kVQ:sqn";
5076 const char *md_shortopts
= "qn";
5079 struct option md_longopts
[] = {
5080 #define OPTION_32 (OPTION_MD_BASE + 0)
5081 {"32", no_argument
, NULL
, OPTION_32
},
5082 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5083 #define OPTION_64 (OPTION_MD_BASE + 1)
5084 {"64", no_argument
, NULL
, OPTION_64
},
5086 {NULL
, no_argument
, NULL
, 0}
5088 size_t md_longopts_size
= sizeof (md_longopts
);
5091 md_parse_option (c
, arg
)
5093 char *arg ATTRIBUTE_UNUSED
;
5098 optimize_align_code
= 0;
5105 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5106 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5107 should be emitted or not. FIXME: Not implemented. */
5111 /* -V: SVR4 argument to print version ID. */
5113 print_version_id ();
5116 /* -k: Ignore for FreeBSD compatibility. */
5121 /* -s: On i386 Solaris, this tells the native assembler to use
5122 .stab instead of .stab.excl. We always use .stab anyhow. */
5127 const char **list
, **l
;
5129 list
= bfd_target_list ();
5130 for (l
= list
; *l
!= NULL
; l
++)
5131 if (strcmp (*l
, "elf64-x86-64") == 0)
5133 default_arch
= "x86_64";
5137 as_fatal (_("No compiled in support for x86_64"));
5144 default_arch
= "i386";
5154 md_show_usage (stream
)
5157 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5158 fprintf (stream
, _("\
5160 -V print assembler version number\n\
5162 -n Do not optimize code alignment\n\
5163 -q quieten some warnings\n\
5166 fprintf (stream
, _("\
5167 -n Do not optimize code alignment\n\
5168 -q quieten some warnings\n"));
5172 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5173 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5175 /* Pick the target format to use. */
5178 i386_target_format ()
5180 if (!strcmp (default_arch
, "x86_64"))
5181 set_code_flag (CODE_64BIT
);
5182 else if (!strcmp (default_arch
, "i386"))
5183 set_code_flag (CODE_32BIT
);
5185 as_fatal (_("Unknown architecture"));
5186 switch (OUTPUT_FLAVOR
)
5188 #ifdef OBJ_MAYBE_AOUT
5189 case bfd_target_aout_flavour
:
5190 return AOUT_TARGET_FORMAT
;
5192 #ifdef OBJ_MAYBE_COFF
5193 case bfd_target_coff_flavour
:
5196 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5197 case bfd_target_elf_flavour
:
5199 if (flag_code
== CODE_64BIT
)
5200 use_rela_relocations
= 1;
5201 return flag_code
== CODE_64BIT
? "elf64-x86-64" : ELF_TARGET_FORMAT
;
5210 #endif /* OBJ_MAYBE_ more than one */
5212 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5213 void i386_elf_emit_arch_note ()
5215 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
5216 && cpu_arch_name
!= NULL
)
5219 asection
*seg
= now_seg
;
5220 subsegT subseg
= now_subseg
;
5221 Elf_Internal_Note i_note
;
5222 Elf_External_Note e_note
;
5223 asection
*note_secp
;
5226 /* Create the .note section. */
5227 note_secp
= subseg_new (".note", 0);
5228 bfd_set_section_flags (stdoutput
,
5230 SEC_HAS_CONTENTS
| SEC_READONLY
);
5232 /* Process the arch string. */
5233 len
= strlen (cpu_arch_name
);
5235 i_note
.namesz
= len
+ 1;
5237 i_note
.type
= NT_ARCH
;
5238 p
= frag_more (sizeof (e_note
.namesz
));
5239 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
5240 p
= frag_more (sizeof (e_note
.descsz
));
5241 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
5242 p
= frag_more (sizeof (e_note
.type
));
5243 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
5244 p
= frag_more (len
+ 1);
5245 strcpy (p
, cpu_arch_name
);
5247 frag_align (2, 0, 0);
5249 subseg_set (seg
, subseg
);
5255 md_undefined_symbol (name
)
5258 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
5259 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
5260 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
5261 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
5265 if (symbol_find (name
))
5266 as_bad (_("GOT already in symbol table"));
5267 GOT_symbol
= symbol_new (name
, undefined_section
,
5268 (valueT
) 0, &zero_address_frag
);
5275 /* Round up a section size to the appropriate boundary. */
5278 md_section_align (segment
, size
)
5279 segT segment ATTRIBUTE_UNUSED
;
5282 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5283 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
5285 /* For a.out, force the section size to be aligned. If we don't do
5286 this, BFD will align it for us, but it will not write out the
5287 final bytes of the section. This may be a bug in BFD, but it is
5288 easier to fix it here since that is how the other a.out targets
5292 align
= bfd_get_section_alignment (stdoutput
, segment
);
5293 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
5300 /* On the i386, PC-relative offsets are relative to the start of the
5301 next instruction. That is, the address of the offset, plus its
5302 size, since the offset is always the last part of the insn. */
5305 md_pcrel_from (fixP
)
5308 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5315 int ignore ATTRIBUTE_UNUSED
;
5319 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5321 obj_elf_section_change_hook ();
5323 temp
= get_absolute_expression ();
5324 subseg_set (bss_section
, (subsegT
) temp
);
5325 demand_empty_rest_of_line ();
5331 i386_validate_fix (fixp
)
5334 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
5336 /* GOTOFF relocation are nonsense in 64bit mode. */
5337 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
5339 if (flag_code
!= CODE_64BIT
)
5341 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
5345 if (flag_code
== CODE_64BIT
)
5347 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
5354 tc_gen_reloc (section
, fixp
)
5355 asection
*section ATTRIBUTE_UNUSED
;
5359 bfd_reloc_code_real_type code
;
5361 switch (fixp
->fx_r_type
)
5363 case BFD_RELOC_X86_64_PLT32
:
5364 case BFD_RELOC_X86_64_GOT32
:
5365 case BFD_RELOC_X86_64_GOTPCREL
:
5366 case BFD_RELOC_386_PLT32
:
5367 case BFD_RELOC_386_GOT32
:
5368 case BFD_RELOC_386_GOTOFF
:
5369 case BFD_RELOC_386_GOTPC
:
5370 case BFD_RELOC_386_TLS_GD
:
5371 case BFD_RELOC_386_TLS_LDM
:
5372 case BFD_RELOC_386_TLS_LDO_32
:
5373 case BFD_RELOC_386_TLS_IE_32
:
5374 case BFD_RELOC_386_TLS_IE
:
5375 case BFD_RELOC_386_TLS_GOTIE
:
5376 case BFD_RELOC_386_TLS_LE_32
:
5377 case BFD_RELOC_386_TLS_LE
:
5378 case BFD_RELOC_X86_64_TLSGD
:
5379 case BFD_RELOC_X86_64_TLSLD
:
5380 case BFD_RELOC_X86_64_DTPOFF32
:
5381 case BFD_RELOC_X86_64_GOTTPOFF
:
5382 case BFD_RELOC_X86_64_TPOFF32
:
5384 case BFD_RELOC_VTABLE_ENTRY
:
5385 case BFD_RELOC_VTABLE_INHERIT
:
5387 case BFD_RELOC_32_SECREL
:
5389 code
= fixp
->fx_r_type
;
5391 case BFD_RELOC_X86_64_32S
:
5392 if (!fixp
->fx_pcrel
)
5394 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5395 code
= fixp
->fx_r_type
;
5401 switch (fixp
->fx_size
)
5404 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5405 _("can not do %d byte pc-relative relocation"),
5407 code
= BFD_RELOC_32_PCREL
;
5409 case 1: code
= BFD_RELOC_8_PCREL
; break;
5410 case 2: code
= BFD_RELOC_16_PCREL
; break;
5411 case 4: code
= BFD_RELOC_32_PCREL
; break;
5416 switch (fixp
->fx_size
)
5419 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5420 _("can not do %d byte relocation"),
5422 code
= BFD_RELOC_32
;
5424 case 1: code
= BFD_RELOC_8
; break;
5425 case 2: code
= BFD_RELOC_16
; break;
5426 case 4: code
= BFD_RELOC_32
; break;
5428 case 8: code
= BFD_RELOC_64
; break;
5435 if (code
== BFD_RELOC_32
5437 && fixp
->fx_addsy
== GOT_symbol
)
5439 /* We don't support GOTPC on 64bit targets. */
5440 if (flag_code
== CODE_64BIT
)
5442 code
= BFD_RELOC_386_GOTPC
;
5445 rel
= (arelent
*) xmalloc (sizeof (arelent
));
5446 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5447 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5449 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5451 if (!use_rela_relocations
)
5453 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5454 vtable entry to be used in the relocation's section offset. */
5455 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5456 rel
->address
= fixp
->fx_offset
;
5460 /* Use the rela in 64bit mode. */
5463 if (!fixp
->fx_pcrel
)
5464 rel
->addend
= fixp
->fx_offset
;
5468 case BFD_RELOC_X86_64_PLT32
:
5469 case BFD_RELOC_X86_64_GOT32
:
5470 case BFD_RELOC_X86_64_GOTPCREL
:
5471 case BFD_RELOC_X86_64_TLSGD
:
5472 case BFD_RELOC_X86_64_TLSLD
:
5473 case BFD_RELOC_X86_64_GOTTPOFF
:
5474 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
5477 rel
->addend
= (section
->vma
5479 + fixp
->fx_addnumber
5480 + md_pcrel_from (fixp
));
5485 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
5486 if (rel
->howto
== NULL
)
5488 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5489 _("cannot represent relocation type %s"),
5490 bfd_get_reloc_code_name (code
));
5491 /* Set howto to a garbage value so that we can keep going. */
5492 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
5493 assert (rel
->howto
!= NULL
);
5500 /* Parse operands using Intel syntax. This implements a recursive descent
5501 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5504 FIXME: We do not recognize the full operand grammar defined in the MASM
5505 documentation. In particular, all the structure/union and
5506 high-level macro operands are missing.
5508 Uppercase words are terminals, lower case words are non-terminals.
5509 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5510 bars '|' denote choices. Most grammar productions are implemented in
5511 functions called 'intel_<production>'.
5513 Initial production is 'expr'.
5519 binOp & | AND | \| | OR | ^ | XOR
5521 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5523 constant digits [[ radixOverride ]]
5525 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
5563 => expr expr cmpOp e04
5566 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5567 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5569 hexdigit a | b | c | d | e | f
5570 | A | B | C | D | E | F
5576 mulOp * | / | % | MOD | << | SHL | >> | SHR
5580 register specialRegister
5584 segmentRegister CS | DS | ES | FS | GS | SS
5586 specialRegister CR0 | CR2 | CR3 | CR4
5587 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5588 | TR3 | TR4 | TR5 | TR6 | TR7
5590 We simplify the grammar in obvious places (e.g., register parsing is
5591 done by calling parse_register) and eliminate immediate left recursion
5592 to implement a recursive-descent parser.
5596 expr' cmpOp e04 expr'
5647 /* Parsing structure for the intel syntax parser. Used to implement the
5648 semantic actions for the operand grammar. */
5649 struct intel_parser_s
5651 char *op_string
; /* The string being parsed. */
5652 int got_a_float
; /* Whether the operand is a float. */
5653 int op_modifier
; /* Operand modifier. */
5654 int is_mem
; /* 1 if operand is memory reference. */
5655 int in_offset
; /* >=1 if parsing operand of offset. */
5656 int in_bracket
; /* >=1 if parsing operand in brackets. */
5657 const reg_entry
*reg
; /* Last register reference found. */
5658 char *disp
; /* Displacement string being built. */
5659 char *next_operand
; /* Resume point when splitting operands. */
5662 static struct intel_parser_s intel_parser
;
5664 /* Token structure for parsing intel syntax. */
5667 int code
; /* Token code. */
5668 const reg_entry
*reg
; /* Register entry for register tokens. */
5669 char *str
; /* String representation. */
5672 static struct intel_token cur_token
, prev_token
;
5674 /* Token codes for the intel parser. Since T_SHORT is already used
5675 by COFF, undefine it first to prevent a warning. */
5694 /* Prototypes for intel parser functions. */
5695 static int intel_match_token
PARAMS ((int code
));
5696 static void intel_get_token
PARAMS ((void));
5697 static void intel_putback_token
PARAMS ((void));
5698 static int intel_expr
PARAMS ((void));
5699 static int intel_e04
PARAMS ((void));
5700 static int intel_e05
PARAMS ((void));
5701 static int intel_e06
PARAMS ((void));
5702 static int intel_e09
PARAMS ((void));
5703 static int intel_bracket_expr
PARAMS ((void));
5704 static int intel_e10
PARAMS ((void));
5705 static int intel_e11
PARAMS ((void));
5708 i386_intel_operand (operand_string
, got_a_float
)
5709 char *operand_string
;
5715 p
= intel_parser
.op_string
= xstrdup (operand_string
);
5716 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
5720 /* Initialize token holders. */
5721 cur_token
.code
= prev_token
.code
= T_NIL
;
5722 cur_token
.reg
= prev_token
.reg
= NULL
;
5723 cur_token
.str
= prev_token
.str
= NULL
;
5725 /* Initialize parser structure. */
5726 intel_parser
.got_a_float
= got_a_float
;
5727 intel_parser
.op_modifier
= 0;
5728 intel_parser
.is_mem
= 0;
5729 intel_parser
.in_offset
= 0;
5730 intel_parser
.in_bracket
= 0;
5731 intel_parser
.reg
= NULL
;
5732 intel_parser
.disp
[0] = '\0';
5733 intel_parser
.next_operand
= NULL
;
5735 /* Read the first token and start the parser. */
5737 ret
= intel_expr ();
5742 if (cur_token
.code
!= T_NIL
)
5744 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
5745 current_templates
->start
->name
, cur_token
.str
);
5748 /* If we found a memory reference, hand it over to i386_displacement
5749 to fill in the rest of the operand fields. */
5750 else if (intel_parser
.is_mem
)
5752 if ((i
.mem_operands
== 1
5753 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5754 || i
.mem_operands
== 2)
5756 as_bad (_("too many memory references for '%s'"),
5757 current_templates
->start
->name
);
5762 char *s
= intel_parser
.disp
;
5765 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
5766 /* See the comments in intel_bracket_expr. */
5767 as_warn (_("Treating `%s' as memory reference"), operand_string
);
5769 /* Add the displacement expression. */
5771 ret
= i386_displacement (s
, s
+ strlen (s
));
5774 /* Swap base and index in 16-bit memory operands like
5775 [si+bx]. Since i386_index_check is also used in AT&T
5776 mode we have to do that here. */
5779 && (i
.base_reg
->reg_type
& Reg16
)
5780 && (i
.index_reg
->reg_type
& Reg16
)
5781 && i
.base_reg
->reg_num
>= 6
5782 && i
.index_reg
->reg_num
< 6)
5784 const reg_entry
*base
= i
.index_reg
;
5786 i
.index_reg
= i
.base_reg
;
5789 ret
= i386_index_check (operand_string
);
5794 /* Constant and OFFSET expressions are handled by i386_immediate. */
5795 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
5796 || intel_parser
.reg
== NULL
)
5797 ret
= i386_immediate (intel_parser
.disp
);
5799 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
5801 if (!ret
|| !intel_parser
.next_operand
)
5803 intel_parser
.op_string
= intel_parser
.next_operand
;
5804 this_operand
= i
.operands
++;
5808 free (intel_parser
.disp
);
5813 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
5817 expr' cmpOp e04 expr'
5822 /* XXX Implement the comparison operators. */
5823 return intel_e04 ();
5840 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
5841 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
5843 if (cur_token
.code
== '+')
5845 else if (cur_token
.code
== '-')
5846 nregs
= NUM_ADDRESS_REGS
;
5850 strcat (intel_parser
.disp
, cur_token
.str
);
5851 intel_match_token (cur_token
.code
);
5862 int nregs
= ~NUM_ADDRESS_REGS
;
5869 if (cur_token
.code
== '&' || cur_token
.code
== '|' || cur_token
.code
== '^')
5873 str
[0] = cur_token
.code
;
5875 strcat (intel_parser
.disp
, str
);
5880 intel_match_token (cur_token
.code
);
5885 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
5886 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
5897 int nregs
= ~NUM_ADDRESS_REGS
;
5904 if (cur_token
.code
== '*' || cur_token
.code
== '/' || cur_token
.code
== '%')
5908 str
[0] = cur_token
.code
;
5910 strcat (intel_parser
.disp
, str
);
5912 else if (cur_token
.code
== T_SHL
)
5913 strcat (intel_parser
.disp
, "<<");
5914 else if (cur_token
.code
== T_SHR
)
5915 strcat (intel_parser
.disp
, ">>");
5919 intel_match_token (cur_token
.code
);
5924 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
5925 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
5943 int nregs
= ~NUM_ADDRESS_REGS
;
5948 /* Don't consume constants here. */
5949 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5951 /* Need to look one token ahead - if the next token
5952 is a constant, the current token is its sign. */
5955 intel_match_token (cur_token
.code
);
5956 next_code
= cur_token
.code
;
5957 intel_putback_token ();
5958 if (next_code
== T_CONST
)
5962 /* e09 OFFSET e09 */
5963 if (cur_token
.code
== T_OFFSET
)
5966 ++intel_parser
.in_offset
;
5970 else if (cur_token
.code
== T_SHORT
)
5971 intel_parser
.op_modifier
|= 1 << T_SHORT
;
5974 else if (cur_token
.code
== '+')
5975 strcat (intel_parser
.disp
, "+");
5980 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
5986 str
[0] = cur_token
.code
;
5988 strcat (intel_parser
.disp
, str
);
5995 intel_match_token (cur_token
.code
);
6003 /* e09' PTR e10 e09' */
6004 if (cur_token
.code
== T_PTR
)
6008 if (prev_token
.code
== T_BYTE
)
6009 suffix
= BYTE_MNEM_SUFFIX
;
6011 else if (prev_token
.code
== T_WORD
)
6013 if (current_templates
->start
->name
[0] == 'l'
6014 && current_templates
->start
->name
[2] == 's'
6015 && current_templates
->start
->name
[3] == 0)
6016 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6017 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
6018 suffix
= SHORT_MNEM_SUFFIX
;
6020 suffix
= WORD_MNEM_SUFFIX
;
6023 else if (prev_token
.code
== T_DWORD
)
6025 if (current_templates
->start
->name
[0] == 'l'
6026 && current_templates
->start
->name
[2] == 's'
6027 && current_templates
->start
->name
[3] == 0)
6028 suffix
= WORD_MNEM_SUFFIX
;
6029 else if (flag_code
== CODE_16BIT
6030 && (current_templates
->start
->opcode_modifier
6031 & (Jump
|JumpDword
|JumpInterSegment
)))
6032 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6033 else if (intel_parser
.got_a_float
== 1) /* "f..." */
6034 suffix
= SHORT_MNEM_SUFFIX
;
6036 suffix
= LONG_MNEM_SUFFIX
;
6039 else if (prev_token
.code
== T_FWORD
)
6041 if (current_templates
->start
->name
[0] == 'l'
6042 && current_templates
->start
->name
[2] == 's'
6043 && current_templates
->start
->name
[3] == 0)
6044 suffix
= LONG_MNEM_SUFFIX
;
6045 else if (!intel_parser
.got_a_float
)
6047 if (flag_code
== CODE_16BIT
)
6048 add_prefix (DATA_PREFIX_OPCODE
);
6049 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6052 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6055 else if (prev_token
.code
== T_QWORD
)
6057 if (intel_parser
.got_a_float
== 1) /* "f..." */
6058 suffix
= LONG_MNEM_SUFFIX
;
6060 suffix
= QWORD_MNEM_SUFFIX
;
6063 else if (prev_token
.code
== T_TBYTE
)
6065 if (intel_parser
.got_a_float
== 1)
6066 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6068 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6071 else if (prev_token
.code
== T_XMMWORD
)
6073 /* XXX ignored for now, but accepted since gcc uses it */
6079 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
6083 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
6087 else if (i
.suffix
!= suffix
)
6089 as_bad (_("Conflicting operand modifiers"));
6095 /* e09' : e10 e09' */
6096 else if (cur_token
.code
== ':')
6098 if (prev_token
.code
!= T_REG
)
6100 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6101 segment/group identifier (which we don't have), using comma
6102 as the operand separator there is even less consistent, since
6103 there all branches only have a single operand. */
6104 if (this_operand
!= 0
6105 || intel_parser
.in_offset
6106 || intel_parser
.in_bracket
6107 || (!(current_templates
->start
->opcode_modifier
6108 & (Jump
|JumpDword
|JumpInterSegment
))
6109 && !(current_templates
->start
->operand_types
[0]
6111 return intel_match_token (T_NIL
);
6112 /* Remember the start of the 2nd operand and terminate 1st
6114 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6115 another expression), but it gets at least the simplest case
6116 (a plain number or symbol on the left side) right. */
6117 intel_parser
.next_operand
= intel_parser
.op_string
;
6118 *--intel_parser
.op_string
= '\0';
6119 return intel_match_token (':');
6127 intel_match_token (cur_token
.code
);
6133 --intel_parser
.in_offset
;
6136 if (NUM_ADDRESS_REGS
> nregs
)
6138 as_bad (_("Invalid operand to `OFFSET'"));
6141 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
6144 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6145 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
6150 intel_bracket_expr ()
6152 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
6153 const char *start
= intel_parser
.op_string
;
6156 if (i
.op
[this_operand
].regs
)
6157 return intel_match_token (T_NIL
);
6159 intel_match_token ('[');
6161 /* Mark as a memory operand only if it's not already known to be an
6162 offset expression. If it's an offset expression, we need to keep
6164 if (!intel_parser
.in_offset
)
6166 ++intel_parser
.in_bracket
;
6167 /* Unfortunately gas always diverged from MASM in a respect that can't
6168 be easily fixed without risking to break code sequences likely to be
6169 encountered (the testsuite even check for this): MASM doesn't consider
6170 an expression inside brackets unconditionally as a memory reference.
6171 When that is e.g. a constant, an offset expression, or the sum of the
6172 two, this is still taken as a constant load. gas, however, always
6173 treated these as memory references. As a compromise, we'll try to make
6174 offset expressions inside brackets work the MASM way (since that's
6175 less likely to be found in real world code), but make constants alone
6176 continue to work the traditional gas way. In either case, issue a
6178 intel_parser
.op_modifier
&= ~was_offset
;
6181 strcat (intel_parser
.disp
, "[");
6183 /* Add a '+' to the displacement string if necessary. */
6184 if (*intel_parser
.disp
!= '\0'
6185 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
6186 strcat (intel_parser
.disp
, "+");
6189 && (len
= intel_parser
.op_string
- start
- 1,
6190 intel_match_token (']')))
6192 /* Preserve brackets when the operand is an offset expression. */
6193 if (intel_parser
.in_offset
)
6194 strcat (intel_parser
.disp
, "]");
6197 --intel_parser
.in_bracket
;
6198 if (i
.base_reg
|| i
.index_reg
)
6199 intel_parser
.is_mem
= 1;
6200 if (!intel_parser
.is_mem
)
6202 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
6203 /* Defer the warning until all of the operand was parsed. */
6204 intel_parser
.is_mem
= -1;
6205 else if (!quiet_warnings
)
6206 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len
, start
, len
, start
);
6209 intel_parser
.op_modifier
|= was_offset
;
6226 while (cur_token
.code
== '[')
6228 if (!intel_bracket_expr ())
6253 switch (cur_token
.code
)
6257 intel_match_token ('(');
6258 strcat (intel_parser
.disp
, "(");
6260 if (intel_expr () && intel_match_token (')'))
6262 strcat (intel_parser
.disp
, ")");
6269 /* Operands for jump/call inside brackets denote absolute addresses.
6270 XXX This shouldn't be needed anymore (or if it should rather live
6271 in intel_bracket_expr). */
6272 if (current_templates
->start
->opcode_modifier
6273 & (Jump
|JumpDword
|JumpByte
|JumpInterSegment
))
6274 i
.types
[this_operand
] |= JumpAbsolute
;
6276 return intel_bracket_expr ();
6281 strcat (intel_parser
.disp
, cur_token
.str
);
6282 intel_match_token (cur_token
.code
);
6284 /* Mark as a memory operand only if it's not already known to be an
6285 offset expression. */
6286 if (!intel_parser
.in_offset
)
6287 intel_parser
.is_mem
= 1;
6294 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
6296 intel_match_token (T_REG
);
6298 /* Check for segment change. */
6299 if (cur_token
.code
== ':')
6301 if (!(reg
->reg_type
& (SReg2
| SReg3
)))
6303 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
6306 else if (i
.seg
[i
.mem_operands
])
6307 as_warn (_("Extra segment override ignored"));
6310 if (!intel_parser
.in_offset
)
6311 intel_parser
.is_mem
= 1;
6312 switch (reg
->reg_num
)
6315 i
.seg
[i
.mem_operands
] = &es
;
6318 i
.seg
[i
.mem_operands
] = &cs
;
6321 i
.seg
[i
.mem_operands
] = &ss
;
6324 i
.seg
[i
.mem_operands
] = &ds
;
6327 i
.seg
[i
.mem_operands
] = &fs
;
6330 i
.seg
[i
.mem_operands
] = &gs
;
6336 /* Not a segment register. Check for register scaling. */
6337 else if (cur_token
.code
== '*')
6339 if (!intel_parser
.in_bracket
)
6341 as_bad (_("Register scaling only allowed in memory operands"));
6345 if (reg
->reg_type
& Reg16
) /* Disallow things like [si*1]. */
6346 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
6347 else if (i
.index_reg
)
6348 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
6350 /* What follows must be a valid scale. */
6351 intel_match_token ('*');
6353 i
.types
[this_operand
] |= BaseIndex
;
6355 /* Set the scale after setting the register (otherwise,
6356 i386_scale will complain) */
6357 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6359 char *str
, sign
= cur_token
.code
;
6360 intel_match_token (cur_token
.code
);
6361 if (cur_token
.code
!= T_CONST
)
6363 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6367 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
6368 strcpy (str
+ 1, cur_token
.str
);
6370 if (!i386_scale (str
))
6374 else if (!i386_scale (cur_token
.str
))
6376 intel_match_token (cur_token
.code
);
6379 /* No scaling. If this is a memory operand, the register is either a
6380 base register (first occurrence) or an index register (second
6382 else if (intel_parser
.in_bracket
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
6387 else if (!i
.index_reg
)
6391 as_bad (_("Too many register references in memory operand"));
6395 i
.types
[this_operand
] |= BaseIndex
;
6398 /* Offset modifier. Add the register to the displacement string to be
6399 parsed as an immediate expression after we're done. */
6400 else if (intel_parser
.in_offset
)
6402 as_warn (_("Using register names in OFFSET expressions is deprecated"));
6403 strcat (intel_parser
.disp
, reg
->reg_name
);
6406 /* It's neither base nor index nor offset. */
6407 else if (!intel_parser
.is_mem
)
6409 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
6410 i
.op
[this_operand
].regs
= reg
;
6415 as_bad (_("Invalid use of register"));
6419 /* Since registers are not part of the displacement string (except
6420 when we're parsing offset operands), we may need to remove any
6421 preceding '+' from the displacement string. */
6422 if (*intel_parser
.disp
!= '\0'
6423 && !intel_parser
.in_offset
)
6425 char *s
= intel_parser
.disp
;
6426 s
+= strlen (s
) - 1;
6449 intel_match_token (cur_token
.code
);
6451 if (cur_token
.code
== T_PTR
)
6454 /* It must have been an identifier. */
6455 intel_putback_token ();
6456 cur_token
.code
= T_ID
;
6462 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
6466 /* The identifier represents a memory reference only if it's not
6467 preceded by an offset modifier and if it's not an equate. */
6468 symbolP
= symbol_find(cur_token
.str
);
6469 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
6470 intel_parser
.is_mem
= 1;
6478 char *save_str
, sign
= 0;
6480 /* Allow constants that start with `+' or `-'. */
6481 if (cur_token
.code
== '-' || cur_token
.code
== '+')
6483 sign
= cur_token
.code
;
6484 intel_match_token (cur_token
.code
);
6485 if (cur_token
.code
!= T_CONST
)
6487 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6493 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
6494 strcpy (save_str
+ !!sign
, cur_token
.str
);
6498 /* Get the next token to check for register scaling. */
6499 intel_match_token (cur_token
.code
);
6501 /* Check if this constant is a scaling factor for an index register. */
6502 if (cur_token
.code
== '*')
6504 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
6506 const reg_entry
*reg
= cur_token
.reg
;
6508 if (!intel_parser
.in_bracket
)
6510 as_bad (_("Register scaling only allowed in memory operands"));
6514 if (reg
->reg_type
& Reg16
) /* Disallow things like [1*si]. */
6515 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
6516 else if (i
.index_reg
)
6517 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
6519 /* The constant is followed by `* reg', so it must be
6522 i
.types
[this_operand
] |= BaseIndex
;
6524 /* Set the scale after setting the register (otherwise,
6525 i386_scale will complain) */
6526 if (!i386_scale (save_str
))
6528 intel_match_token (T_REG
);
6530 /* Since registers are not part of the displacement
6531 string, we may need to remove any preceding '+' from
6532 the displacement string. */
6533 if (*intel_parser
.disp
!= '\0')
6535 char *s
= intel_parser
.disp
;
6536 s
+= strlen (s
) - 1;
6546 /* The constant was not used for register scaling. Since we have
6547 already consumed the token following `*' we now need to put it
6548 back in the stream. */
6549 intel_putback_token ();
6552 /* Add the constant to the displacement string. */
6553 strcat (intel_parser
.disp
, save_str
);
6560 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
6564 /* Match the given token against cur_token. If they match, read the next
6565 token from the operand string. */
6567 intel_match_token (code
)
6570 if (cur_token
.code
== code
)
6577 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
6582 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6587 const reg_entry
*reg
;
6588 struct intel_token new_token
;
6590 new_token
.code
= T_NIL
;
6591 new_token
.reg
= NULL
;
6592 new_token
.str
= NULL
;
6594 /* Free the memory allocated to the previous token and move
6595 cur_token to prev_token. */
6597 free (prev_token
.str
);
6599 prev_token
= cur_token
;
6601 /* Skip whitespace. */
6602 while (is_space_char (*intel_parser
.op_string
))
6603 intel_parser
.op_string
++;
6605 /* Return an empty token if we find nothing else on the line. */
6606 if (*intel_parser
.op_string
== '\0')
6608 cur_token
= new_token
;
6612 /* The new token cannot be larger than the remainder of the operand
6614 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
6615 new_token
.str
[0] = '\0';
6617 if (strchr ("0123456789", *intel_parser
.op_string
))
6619 char *p
= new_token
.str
;
6620 char *q
= intel_parser
.op_string
;
6621 new_token
.code
= T_CONST
;
6623 /* Allow any kind of identifier char to encompass floating point and
6624 hexadecimal numbers. */
6625 while (is_identifier_char (*q
))
6629 /* Recognize special symbol names [0-9][bf]. */
6630 if (strlen (intel_parser
.op_string
) == 2
6631 && (intel_parser
.op_string
[1] == 'b'
6632 || intel_parser
.op_string
[1] == 'f'))
6633 new_token
.code
= T_ID
;
6636 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6637 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
6639 new_token
.code
= T_REG
;
6640 new_token
.reg
= reg
;
6642 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
6644 new_token
.str
[0] = REGISTER_PREFIX
;
6645 new_token
.str
[1] = '\0';
6648 strcat (new_token
.str
, reg
->reg_name
);
6651 else if (is_identifier_char (*intel_parser
.op_string
))
6653 char *p
= new_token
.str
;
6654 char *q
= intel_parser
.op_string
;
6656 /* A '.' or '$' followed by an identifier char is an identifier.
6657 Otherwise, it's operator '.' followed by an expression. */
6658 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
6660 new_token
.code
= '.';
6661 new_token
.str
[0] = '.';
6662 new_token
.str
[1] = '\0';
6666 while (is_identifier_char (*q
) || *q
== '@')
6670 if (strcasecmp (new_token
.str
, "NOT") == 0)
6671 new_token
.code
= '~';
6673 else if (strcasecmp (new_token
.str
, "MOD") == 0)
6674 new_token
.code
= '%';
6676 else if (strcasecmp (new_token
.str
, "AND") == 0)
6677 new_token
.code
= '&';
6679 else if (strcasecmp (new_token
.str
, "OR") == 0)
6680 new_token
.code
= '|';
6682 else if (strcasecmp (new_token
.str
, "XOR") == 0)
6683 new_token
.code
= '^';
6685 else if (strcasecmp (new_token
.str
, "SHL") == 0)
6686 new_token
.code
= T_SHL
;
6688 else if (strcasecmp (new_token
.str
, "SHR") == 0)
6689 new_token
.code
= T_SHR
;
6691 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
6692 new_token
.code
= T_BYTE
;
6694 else if (strcasecmp (new_token
.str
, "WORD") == 0)
6695 new_token
.code
= T_WORD
;
6697 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
6698 new_token
.code
= T_DWORD
;
6700 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
6701 new_token
.code
= T_FWORD
;
6703 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
6704 new_token
.code
= T_QWORD
;
6706 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
6707 /* XXX remove (gcc still uses it) */
6708 || strcasecmp (new_token
.str
, "XWORD") == 0)
6709 new_token
.code
= T_TBYTE
;
6711 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
6712 || strcasecmp (new_token
.str
, "OWORD") == 0)
6713 new_token
.code
= T_XMMWORD
;
6715 else if (strcasecmp (new_token
.str
, "PTR") == 0)
6716 new_token
.code
= T_PTR
;
6718 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
6719 new_token
.code
= T_SHORT
;
6721 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
6723 new_token
.code
= T_OFFSET
;
6725 /* ??? This is not mentioned in the MASM grammar but gcc
6726 makes use of it with -mintel-syntax. OFFSET may be
6727 followed by FLAT: */
6728 if (strncasecmp (q
, " FLAT:", 6) == 0)
6729 strcat (new_token
.str
, " FLAT:");
6732 /* ??? This is not mentioned in the MASM grammar. */
6733 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
6735 new_token
.code
= T_OFFSET
;
6737 strcat (new_token
.str
, ":");
6739 as_bad (_("`:' expected"));
6743 new_token
.code
= T_ID
;
6747 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
6749 new_token
.code
= *intel_parser
.op_string
;
6750 new_token
.str
[0] = *intel_parser
.op_string
;
6751 new_token
.str
[1] = '\0';
6754 else if (strchr ("<>", *intel_parser
.op_string
)
6755 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
6757 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
6758 new_token
.str
[0] = *intel_parser
.op_string
;
6759 new_token
.str
[1] = *intel_parser
.op_string
;
6760 new_token
.str
[2] = '\0';
6764 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
6766 intel_parser
.op_string
+= strlen (new_token
.str
);
6767 cur_token
= new_token
;
6770 /* Put cur_token back into the token stream and make cur_token point to
6773 intel_putback_token ()
6775 if (cur_token
.code
!= T_NIL
)
6777 intel_parser
.op_string
-= strlen (cur_token
.str
);
6778 free (cur_token
.str
);
6780 cur_token
= prev_token
;
6782 /* Forget prev_token. */
6783 prev_token
.code
= T_NIL
;
6784 prev_token
.reg
= NULL
;
6785 prev_token
.str
= NULL
;
6789 tc_x86_regname_to_dw2regnum (const char *regname
)
6791 unsigned int regnum
;
6792 unsigned int regnames_count
;
6793 static const char *const regnames_32
[] =
6795 "eax", "ecx", "edx", "ebx",
6796 "esp", "ebp", "esi", "edi",
6797 "eip", "eflags", NULL
,
6798 "st0", "st1", "st2", "st3",
6799 "st4", "st5", "st6", "st7",
6801 "xmm0", "xmm1", "xmm2", "xmm3",
6802 "xmm4", "xmm5", "xmm6", "xmm7",
6803 "mm0", "mm1", "mm2", "mm3",
6804 "mm4", "mm5", "mm6", "mm7"
6806 static const char *const regnames_64
[] =
6808 "rax", "rdx", "rcx", "rbx",
6809 "rsi", "rdi", "rbp", "rsp",
6810 "r8", "r9", "r10", "r11",
6811 "r12", "r13", "r14", "r15",
6813 "xmm0", "xmm1", "xmm2", "xmm3",
6814 "xmm4", "xmm5", "xmm6", "xmm7",
6815 "xmm8", "xmm9", "xmm10", "xmm11",
6816 "xmm12", "xmm13", "xmm14", "xmm15",
6817 "st0", "st1", "st2", "st3",
6818 "st4", "st5", "st6", "st7",
6819 "mm0", "mm1", "mm2", "mm3",
6820 "mm4", "mm5", "mm6", "mm7"
6822 const char *const *regnames
;
6824 if (flag_code
== CODE_64BIT
)
6826 regnames
= regnames_64
;
6827 regnames_count
= ARRAY_SIZE (regnames_64
);
6831 regnames
= regnames_32
;
6832 regnames_count
= ARRAY_SIZE (regnames_32
);
6835 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
6836 if (regnames
[regnum
] != NULL
6837 && strcmp (regname
, regnames
[regnum
]) == 0)
6844 tc_x86_frame_initial_instructions (void)
6846 static unsigned int sp_regno
;
6849 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
6852 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
6853 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
6857 i386_elf_section_type (const char *str
, size_t len
)
6859 if (flag_code
== CODE_64BIT
6860 && len
== sizeof ("unwind") - 1
6861 && strncmp (str
, "unwind", 6) == 0)
6862 return SHT_X86_64_UNWIND
;
6869 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
6873 expr
.X_op
= O_secrel
;
6874 expr
.X_add_symbol
= symbol
;
6875 expr
.X_add_number
= 0;
6876 emit_expr (&expr
, size
);