1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
37 #ifndef REGISTER_WARNINGS
38 #define REGISTER_WARNINGS 1
41 #ifndef INFER_ADDR_PREFIX
42 #define INFER_ADDR_PREFIX 1
45 #ifndef SCALE1_WHEN_NO_INDEX
46 /* Specifying a scale factor besides 1 when there is no index is
47 futile. eg. `mov (%ebx,2),%al' does exactly the same as
48 `mov (%ebx),%al'. To slavishly follow what the programmer
49 specified, set SCALE1_WHEN_NO_INDEX to 0. */
50 #define SCALE1_WHEN_NO_INDEX 1
54 #define DEFAULT_ARCH "i386"
59 #define INLINE __inline__
65 static void set_code_flag (int);
66 static void set_16bit_gcc_code_flag (int);
67 static void set_intel_syntax (int);
68 static void set_cpu_arch (int);
70 static void pe_directive_secrel (int);
72 static void signed_cons (int);
73 static char *output_invalid (int c
);
74 static int i386_operand (char *);
75 static int i386_intel_operand (char *, int);
76 static const reg_entry
*parse_register (char *, char **);
77 static char *parse_insn (char *, char *);
78 static char *parse_operands (char *, const char *);
79 static void swap_operands (void);
80 static void swap_2_operands (int, int);
81 static void optimize_imm (void);
82 static void optimize_disp (void);
83 static int match_template (void);
84 static int check_string (void);
85 static int process_suffix (void);
86 static int check_byte_reg (void);
87 static int check_long_reg (void);
88 static int check_qword_reg (void);
89 static int check_word_reg (void);
90 static int finalize_imm (void);
91 static int process_operands (void);
92 static const seg_entry
*build_modrm_byte (void);
93 static void output_insn (void);
94 static void output_imm (fragS
*, offsetT
);
95 static void output_disp (fragS
*, offsetT
);
97 static void s_bss (int);
99 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
100 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
103 static const char *default_arch
= DEFAULT_ARCH
;
105 /* 'md_assemble ()' gathers together information and puts it into a
112 const reg_entry
*regs
;
117 /* TM holds the template for the insn were currently assembling. */
120 /* SUFFIX holds the instruction mnemonic suffix if given.
121 (e.g. 'l' for 'movl') */
124 /* OPERANDS gives the number of given operands. */
125 unsigned int operands
;
127 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
128 of given register, displacement, memory operands and immediate
130 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
132 /* TYPES [i] is the type (see above #defines) which tells us how to
133 use OP[i] for the corresponding operand. */
134 unsigned int types
[MAX_OPERANDS
];
136 /* Displacement expression, immediate expression, or register for each
138 union i386_op op
[MAX_OPERANDS
];
140 /* Flags for operands. */
141 unsigned int flags
[MAX_OPERANDS
];
142 #define Operand_PCrel 1
144 /* Relocation type for operand */
145 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
147 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
148 the base index byte below. */
149 const reg_entry
*base_reg
;
150 const reg_entry
*index_reg
;
151 unsigned int log2_scale_factor
;
153 /* SEG gives the seg_entries of this insn. They are zero unless
154 explicit segment overrides are given. */
155 const seg_entry
*seg
[2];
157 /* PREFIX holds all the given prefix opcodes (usually null).
158 PREFIXES is the number of prefix opcodes. */
159 unsigned int prefixes
;
160 unsigned char prefix
[MAX_PREFIXES
];
162 /* RM and SIB are the modrm byte and the sib byte where the
163 addressing modes of this insn are encoded. */
170 typedef struct _i386_insn i386_insn
;
172 /* List of chars besides those in app.c:symbol_chars that can start an
173 operand. Used to prevent the scrubber eating vital white-space. */
174 const char extra_symbol_chars
[] = "*%-(["
183 #if (defined (TE_I386AIX) \
184 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
185 && !defined (TE_GNU) \
186 && !defined (TE_LINUX) \
187 && !defined (TE_NETWARE) \
188 && !defined (TE_FreeBSD) \
189 && !defined (TE_NetBSD)))
190 /* This array holds the chars that always start a comment. If the
191 pre-processor is disabled, these aren't very useful. The option
192 --divide will remove '/' from this list. */
193 const char *i386_comment_chars
= "#/";
194 #define SVR4_COMMENT_CHARS 1
195 #define PREFIX_SEPARATOR '\\'
198 const char *i386_comment_chars
= "#";
199 #define PREFIX_SEPARATOR '/'
202 /* This array holds the chars that only start a comment at the beginning of
203 a line. If the line seems to have the form '# 123 filename'
204 .line and .file directives will appear in the pre-processed output.
205 Note that input_file.c hand checks for '#' at the beginning of the
206 first line of the input file. This is because the compiler outputs
207 #NO_APP at the beginning of its output.
208 Also note that comments started like this one will always work if
209 '/' isn't otherwise defined. */
210 const char line_comment_chars
[] = "#/";
212 const char line_separator_chars
[] = ";";
214 /* Chars that can be used to separate mant from exp in floating point
216 const char EXP_CHARS
[] = "eE";
218 /* Chars that mean this number is a floating point constant
221 const char FLT_CHARS
[] = "fFdDxX";
223 /* Tables for lexical analysis. */
224 static char mnemonic_chars
[256];
225 static char register_chars
[256];
226 static char operand_chars
[256];
227 static char identifier_chars
[256];
228 static char digit_chars
[256];
230 /* Lexical macros. */
231 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
232 #define is_operand_char(x) (operand_chars[(unsigned char) x])
233 #define is_register_char(x) (register_chars[(unsigned char) x])
234 #define is_space_char(x) ((x) == ' ')
235 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
236 #define is_digit_char(x) (digit_chars[(unsigned char) x])
238 /* All non-digit non-letter characters that may occur in an operand. */
239 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
241 /* md_assemble() always leaves the strings it's passed unaltered. To
242 effect this we maintain a stack of saved characters that we've smashed
243 with '\0's (indicating end of strings for various sub-fields of the
244 assembler instruction). */
245 static char save_stack
[32];
246 static char *save_stack_p
;
247 #define END_STRING_AND_SAVE(s) \
248 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
249 #define RESTORE_END_STRING(s) \
250 do { *(s) = *--save_stack_p; } while (0)
252 /* The instruction we're assembling. */
255 /* Possible templates for current insn. */
256 static const templates
*current_templates
;
258 /* Per instruction expressionS buffers: max displacements & immediates. */
259 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
260 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
262 /* Current operand we are working on. */
263 static int this_operand
;
265 /* We support four different modes. FLAG_CODE variable is used to distinguish
272 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
274 static enum flag_code flag_code
;
275 static unsigned int object_64bit
;
276 static int use_rela_relocations
= 0;
278 /* The names used to print error messages. */
279 static const char *flag_code_names
[] =
286 /* 1 for intel syntax,
288 static int intel_syntax
= 0;
290 /* 1 if register prefix % not required. */
291 static int allow_naked_reg
= 0;
293 /* Register prefix used for error message. */
294 static const char *register_prefix
= "%";
296 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
297 leave, push, and pop instructions so that gcc has the same stack
298 frame as in 32 bit mode. */
299 static char stackop_size
= '\0';
301 /* Non-zero to optimize code alignment. */
302 int optimize_align_code
= 1;
304 /* Non-zero to quieten some warnings. */
305 static int quiet_warnings
= 0;
308 static const char *cpu_arch_name
= NULL
;
309 static const char *cpu_sub_arch_name
= NULL
;
311 /* CPU feature flags. */
312 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
314 /* If we have selected a cpu we are generating instructions for. */
315 static int cpu_arch_tune_set
= 0;
317 /* Cpu we are generating instructions for. */
318 static enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
320 /* CPU feature flags of cpu we are generating instructions for. */
321 static unsigned int cpu_arch_tune_flags
= 0;
323 /* CPU instruction set architecture used. */
324 static enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
326 /* CPU feature flags of instruction set architecture used. */
327 static unsigned int cpu_arch_isa_flags
= 0;
329 /* If set, conditional jumps are not automatically promoted to handle
330 larger than a byte offset. */
331 static unsigned int no_cond_jump_promotion
= 0;
333 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
334 static symbolS
*GOT_symbol
;
336 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
337 unsigned int x86_dwarf2_return_column
;
339 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
340 int x86_cie_data_alignment
;
342 /* Interface to relax_segment.
343 There are 3 major relax states for 386 jump insns because the
344 different types of jumps add different sizes to frags when we're
345 figuring out what sort of jump to choose to reach a given label. */
348 #define UNCOND_JUMP 0
350 #define COND_JUMP86 2
355 #define SMALL16 (SMALL | CODE16)
357 #define BIG16 (BIG | CODE16)
361 #define INLINE __inline__
367 #define ENCODE_RELAX_STATE(type, size) \
368 ((relax_substateT) (((type) << 2) | (size)))
369 #define TYPE_FROM_RELAX_STATE(s) \
371 #define DISP_SIZE_FROM_RELAX_STATE(s) \
372 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
374 /* This table is used by relax_frag to promote short jumps to long
375 ones where necessary. SMALL (short) jumps may be promoted to BIG
376 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
377 don't allow a short jump in a 32 bit code segment to be promoted to
378 a 16 bit offset jump because it's slower (requires data size
379 prefix), and doesn't work, unless the destination is in the bottom
380 64k of the code segment (The top 16 bits of eip are zeroed). */
382 const relax_typeS md_relax_table
[] =
385 1) most positive reach of this state,
386 2) most negative reach of this state,
387 3) how many bytes this mode will have in the variable part of the frag
388 4) which index into the table to try if we can't fit into this one. */
390 /* UNCOND_JUMP states. */
391 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
393 /* dword jmp adds 4 bytes to frag:
394 0 extra opcode bytes, 4 displacement bytes. */
396 /* word jmp adds 2 byte2 to frag:
397 0 extra opcode bytes, 2 displacement bytes. */
400 /* COND_JUMP states. */
401 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
403 /* dword conditionals adds 5 bytes to frag:
404 1 extra opcode byte, 4 displacement bytes. */
406 /* word conditionals add 3 bytes to frag:
407 1 extra opcode byte, 2 displacement bytes. */
410 /* COND_JUMP86 states. */
411 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
412 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
413 /* dword conditionals adds 5 bytes to frag:
414 1 extra opcode byte, 4 displacement bytes. */
416 /* word conditionals add 4 bytes to frag:
417 1 displacement byte and a 3 byte long branch insn. */
421 static const arch_entry cpu_arch
[] =
423 {"generic32", PROCESSOR_GENERIC32
,
424 Cpu186
|Cpu286
|Cpu386
},
425 {"generic64", PROCESSOR_GENERIC64
,
426 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
427 |CpuMMX2
|CpuSSE
|CpuSSE2
},
428 {"i8086", PROCESSOR_UNKNOWN
,
430 {"i186", PROCESSOR_UNKNOWN
,
432 {"i286", PROCESSOR_UNKNOWN
,
434 {"i386", PROCESSOR_GENERIC32
,
435 Cpu186
|Cpu286
|Cpu386
},
436 {"i486", PROCESSOR_I486
,
437 Cpu186
|Cpu286
|Cpu386
|Cpu486
},
438 {"i586", PROCESSOR_PENTIUM
,
439 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
440 {"i686", PROCESSOR_PENTIUMPRO
,
441 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
442 {"pentium", PROCESSOR_PENTIUM
,
443 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
444 {"pentiumpro",PROCESSOR_PENTIUMPRO
,
445 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
446 {"pentiumii", PROCESSOR_PENTIUMPRO
,
447 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
},
448 {"pentiumiii",PROCESSOR_PENTIUMPRO
,
449 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuMMX2
|CpuSSE
},
450 {"pentium4", PROCESSOR_PENTIUM4
,
451 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
452 |CpuMMX2
|CpuSSE
|CpuSSE2
},
453 {"prescott", PROCESSOR_NOCONA
,
454 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
455 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
456 {"nocona", PROCESSOR_NOCONA
,
457 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
458 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
459 {"yonah", PROCESSOR_CORE
,
460 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
461 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
462 {"core", PROCESSOR_CORE
,
463 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
464 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
465 {"merom", PROCESSOR_CORE2
,
466 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
467 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
},
468 {"core2", PROCESSOR_CORE2
,
469 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
470 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
},
472 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
},
473 {"k6_2", PROCESSOR_K6
,
474 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
475 {"athlon", PROCESSOR_ATHLON
,
476 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
477 |CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
478 {"sledgehammer", PROCESSOR_K8
,
479 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
480 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
481 {"opteron", PROCESSOR_K8
,
482 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
483 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
485 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
486 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
487 {"amdfam10", PROCESSOR_AMDFAM10
,
488 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuSledgehammer
489 |CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSE4a
491 {".mmx", PROCESSOR_UNKNOWN
,
493 {".sse", PROCESSOR_UNKNOWN
,
494 CpuMMX
|CpuMMX2
|CpuSSE
},
495 {".sse2", PROCESSOR_UNKNOWN
,
496 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
497 {".sse3", PROCESSOR_UNKNOWN
,
498 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
499 {".ssse3", PROCESSOR_UNKNOWN
,
500 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
},
501 {".sse4.1", PROCESSOR_UNKNOWN
,
502 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
|CpuSSE4_1
},
503 {".sse4.2", PROCESSOR_UNKNOWN
,
504 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
|CpuSSE4
},
505 {".sse4", PROCESSOR_UNKNOWN
,
506 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
|CpuSSE4
},
507 {".3dnow", PROCESSOR_UNKNOWN
,
509 {".3dnowa", PROCESSOR_UNKNOWN
,
510 CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
511 {".padlock", PROCESSOR_UNKNOWN
,
513 {".pacifica", PROCESSOR_UNKNOWN
,
515 {".svme", PROCESSOR_UNKNOWN
,
517 {".sse4a", PROCESSOR_UNKNOWN
,
518 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSE4a
},
519 {".abm", PROCESSOR_UNKNOWN
,
523 const pseudo_typeS md_pseudo_table
[] =
525 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
526 {"align", s_align_bytes
, 0},
528 {"align", s_align_ptwo
, 0},
530 {"arch", set_cpu_arch
, 0},
534 {"ffloat", float_cons
, 'f'},
535 {"dfloat", float_cons
, 'd'},
536 {"tfloat", float_cons
, 'x'},
538 {"slong", signed_cons
, 4},
539 {"noopt", s_ignore
, 0},
540 {"optim", s_ignore
, 0},
541 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
542 {"code16", set_code_flag
, CODE_16BIT
},
543 {"code32", set_code_flag
, CODE_32BIT
},
544 {"code64", set_code_flag
, CODE_64BIT
},
545 {"intel_syntax", set_intel_syntax
, 1},
546 {"att_syntax", set_intel_syntax
, 0},
547 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
548 {"largecomm", handle_large_common
, 0},
550 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
551 {"loc", dwarf2_directive_loc
, 0},
552 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
555 {"secrel32", pe_directive_secrel
, 0},
560 /* For interface with expression (). */
561 extern char *input_line_pointer
;
563 /* Hash table for instruction mnemonic lookup. */
564 static struct hash_control
*op_hash
;
566 /* Hash table for register lookup. */
567 static struct hash_control
*reg_hash
;
570 i386_align_code (fragS
*fragP
, int count
)
572 /* Various efficient no-op patterns for aligning code labels.
573 Note: Don't try to assemble the instructions in the comments.
574 0L and 0w are not legal. */
575 static const char f32_1
[] =
577 static const char f32_2
[] =
578 {0x66,0x90}; /* xchg %ax,%ax */
579 static const char f32_3
[] =
580 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
581 static const char f32_4
[] =
582 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
583 static const char f32_5
[] =
585 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
586 static const char f32_6
[] =
587 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
588 static const char f32_7
[] =
589 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
590 static const char f32_8
[] =
592 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
593 static const char f32_9
[] =
594 {0x89,0xf6, /* movl %esi,%esi */
595 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
596 static const char f32_10
[] =
597 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
598 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
599 static const char f32_11
[] =
600 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
601 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
602 static const char f32_12
[] =
603 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
604 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
605 static const char f32_13
[] =
606 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
607 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
608 static const char f32_14
[] =
609 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
610 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
611 static const char f32_15
[] =
612 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
613 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
614 static const char f16_3
[] =
615 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
616 static const char f16_4
[] =
617 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
618 static const char f16_5
[] =
620 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
621 static const char f16_6
[] =
622 {0x89,0xf6, /* mov %si,%si */
623 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
624 static const char f16_7
[] =
625 {0x8d,0x74,0x00, /* lea 0(%si),%si */
626 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
627 static const char f16_8
[] =
628 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
629 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
630 static const char *const f32_patt
[] = {
631 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
632 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
634 static const char *const f16_patt
[] = {
635 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
636 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
639 static const char alt_3
[] =
641 /* nopl 0(%[re]ax) */
642 static const char alt_4
[] =
643 {0x0f,0x1f,0x40,0x00};
644 /* nopl 0(%[re]ax,%[re]ax,1) */
645 static const char alt_5
[] =
646 {0x0f,0x1f,0x44,0x00,0x00};
647 /* nopw 0(%[re]ax,%[re]ax,1) */
648 static const char alt_6
[] =
649 {0x66,0x0f,0x1f,0x44,0x00,0x00};
650 /* nopl 0L(%[re]ax) */
651 static const char alt_7
[] =
652 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
653 /* nopl 0L(%[re]ax,%[re]ax,1) */
654 static const char alt_8
[] =
655 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
656 /* nopw 0L(%[re]ax,%[re]ax,1) */
657 static const char alt_9
[] =
658 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
659 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
660 static const char alt_10
[] =
661 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
663 nopw %cs:0L(%[re]ax,%[re]ax,1) */
664 static const char alt_long_11
[] =
666 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
669 nopw %cs:0L(%[re]ax,%[re]ax,1) */
670 static const char alt_long_12
[] =
673 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
677 nopw %cs:0L(%[re]ax,%[re]ax,1) */
678 static const char alt_long_13
[] =
682 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
687 nopw %cs:0L(%[re]ax,%[re]ax,1) */
688 static const char alt_long_14
[] =
693 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
699 nopw %cs:0L(%[re]ax,%[re]ax,1) */
700 static const char alt_long_15
[] =
706 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
707 /* nopl 0(%[re]ax,%[re]ax,1)
708 nopw 0(%[re]ax,%[re]ax,1) */
709 static const char alt_short_11
[] =
710 {0x0f,0x1f,0x44,0x00,0x00,
711 0x66,0x0f,0x1f,0x44,0x00,0x00};
712 /* nopw 0(%[re]ax,%[re]ax,1)
713 nopw 0(%[re]ax,%[re]ax,1) */
714 static const char alt_short_12
[] =
715 {0x66,0x0f,0x1f,0x44,0x00,0x00,
716 0x66,0x0f,0x1f,0x44,0x00,0x00};
717 /* nopw 0(%[re]ax,%[re]ax,1)
719 static const char alt_short_13
[] =
720 {0x66,0x0f,0x1f,0x44,0x00,0x00,
721 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
724 static const char alt_short_14
[] =
725 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
726 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
728 nopl 0L(%[re]ax,%[re]ax,1) */
729 static const char alt_short_15
[] =
730 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
731 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
732 static const char *const alt_short_patt
[] = {
733 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
734 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
735 alt_short_14
, alt_short_15
737 static const char *const alt_long_patt
[] = {
738 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
739 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
740 alt_long_14
, alt_long_15
743 if (count
<= 0 || count
> 15)
746 /* We need to decide which NOP sequence to use for 32bit and
747 64bit. When -mtune= is used:
749 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
750 f32_patt will be used.
751 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with
752 0x66 prefix will be used.
753 3. For PROCESSOR_CORE2, alt_long_patt will be used.
754 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
755 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
756 and PROCESSOR_GENERIC64, alt_short_patt will be used.
758 When -mtune= isn't used, alt_short_patt will be used if
759 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
761 When -march= or .arch is used, we can't use anything beyond
762 cpu_arch_isa_flags. */
764 if (flag_code
== CODE_16BIT
)
766 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
767 f16_patt
[count
- 1], count
);
769 /* Adjust jump offset. */
770 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
772 else if (flag_code
== CODE_64BIT
&& cpu_arch_tune
== PROCESSOR_K8
)
775 int nnops
= (count
+ 3) / 4;
776 int len
= count
/ nnops
;
777 int remains
= count
- nnops
* len
;
780 /* The recommended way to pad 64bit code is to use NOPs preceded
781 by maximally four 0x66 prefixes. Balance the size of nops. */
782 for (i
= 0; i
< remains
; i
++)
784 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
785 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
788 for (; i
< nnops
; i
++)
790 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
791 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
797 const char *const *patt
= NULL
;
799 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
801 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
802 switch (cpu_arch_tune
)
804 case PROCESSOR_UNKNOWN
:
805 /* We use cpu_arch_isa_flags to check if we SHOULD
806 optimize for Cpu686. */
807 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
808 patt
= alt_short_patt
;
812 case PROCESSOR_CORE2
:
813 patt
= alt_long_patt
;
815 case PROCESSOR_PENTIUMPRO
:
816 case PROCESSOR_PENTIUM4
:
817 case PROCESSOR_NOCONA
:
820 case PROCESSOR_ATHLON
:
822 case PROCESSOR_GENERIC64
:
823 case PROCESSOR_AMDFAM10
:
824 patt
= alt_short_patt
;
827 case PROCESSOR_PENTIUM
:
828 case PROCESSOR_GENERIC32
:
835 switch (cpu_arch_tune
)
837 case PROCESSOR_UNKNOWN
:
838 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
839 PROCESSOR_UNKNOWN. */
844 case PROCESSOR_PENTIUM
:
845 case PROCESSOR_PENTIUMPRO
:
846 case PROCESSOR_PENTIUM4
:
847 case PROCESSOR_NOCONA
:
850 case PROCESSOR_ATHLON
:
852 case PROCESSOR_AMDFAM10
:
853 case PROCESSOR_GENERIC32
:
854 /* We use cpu_arch_isa_flags to check if we CAN optimize
856 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
857 patt
= alt_short_patt
;
861 case PROCESSOR_CORE2
:
862 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
863 patt
= alt_long_patt
;
867 case PROCESSOR_GENERIC64
:
868 patt
= alt_short_patt
;
873 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
874 patt
[count
- 1], count
);
876 fragP
->fr_var
= count
;
879 static INLINE
unsigned int
880 mode_from_disp_size (unsigned int t
)
882 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
886 fits_in_signed_byte (offsetT num
)
888 return (num
>= -128) && (num
<= 127);
892 fits_in_unsigned_byte (offsetT num
)
894 return (num
& 0xff) == num
;
898 fits_in_unsigned_word (offsetT num
)
900 return (num
& 0xffff) == num
;
904 fits_in_signed_word (offsetT num
)
906 return (-32768 <= num
) && (num
<= 32767);
910 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
915 return (!(((offsetT
) -1 << 31) & num
)
916 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
918 } /* fits_in_signed_long() */
921 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
926 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
928 } /* fits_in_unsigned_long() */
931 smallest_imm_type (offsetT num
)
933 if (cpu_arch_flags
!= (Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
935 /* This code is disabled on the 486 because all the Imm1 forms
936 in the opcode table are slower on the i486. They're the
937 versions with the implicitly specified single-position
938 displacement, which has another syntax if you really want to
941 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
943 return (fits_in_signed_byte (num
)
944 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
945 : fits_in_unsigned_byte (num
)
946 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
947 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
948 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
949 : fits_in_signed_long (num
)
950 ? (Imm32
| Imm32S
| Imm64
)
951 : fits_in_unsigned_long (num
)
957 offset_in_range (offsetT val
, int size
)
963 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
964 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
965 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
967 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
972 /* If BFD64, sign extend val. */
973 if (!use_rela_relocations
)
974 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
975 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
977 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
979 char buf1
[40], buf2
[40];
981 sprint_value (buf1
, val
);
982 sprint_value (buf2
, val
& mask
);
983 as_warn (_("%s shortened to %s"), buf1
, buf2
);
988 /* Returns 0 if attempting to add a prefix where one from the same
989 class already exists, 1 if non rep/repne added, 2 if rep/repne
992 add_prefix (unsigned int prefix
)
997 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
998 && flag_code
== CODE_64BIT
)
1000 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1001 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1002 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1013 case CS_PREFIX_OPCODE
:
1014 case DS_PREFIX_OPCODE
:
1015 case ES_PREFIX_OPCODE
:
1016 case FS_PREFIX_OPCODE
:
1017 case GS_PREFIX_OPCODE
:
1018 case SS_PREFIX_OPCODE
:
1022 case REPNE_PREFIX_OPCODE
:
1023 case REPE_PREFIX_OPCODE
:
1026 case LOCK_PREFIX_OPCODE
:
1034 case ADDR_PREFIX_OPCODE
:
1038 case DATA_PREFIX_OPCODE
:
1042 if (i
.prefix
[q
] != 0)
1050 i
.prefix
[q
] |= prefix
;
1053 as_bad (_("same type of prefix used twice"));
1059 set_code_flag (int value
)
1062 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
1063 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
1064 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
1066 as_bad (_("64bit mode not supported on this CPU."));
1068 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
1070 as_bad (_("32bit mode not supported on this CPU."));
1072 stackop_size
= '\0';
1076 set_16bit_gcc_code_flag (int new_code_flag
)
1078 flag_code
= new_code_flag
;
1079 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
1080 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
1081 stackop_size
= LONG_MNEM_SUFFIX
;
1085 set_intel_syntax (int syntax_flag
)
1087 /* Find out if register prefixing is specified. */
1088 int ask_naked_reg
= 0;
1091 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1093 char *string
= input_line_pointer
;
1094 int e
= get_symbol_end ();
1096 if (strcmp (string
, "prefix") == 0)
1098 else if (strcmp (string
, "noprefix") == 0)
1101 as_bad (_("bad argument to syntax directive."));
1102 *input_line_pointer
= e
;
1104 demand_empty_rest_of_line ();
1106 intel_syntax
= syntax_flag
;
1108 if (ask_naked_reg
== 0)
1109 allow_naked_reg
= (intel_syntax
1110 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1112 allow_naked_reg
= (ask_naked_reg
< 0);
1114 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1115 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1116 register_prefix
= allow_naked_reg
? "" : "%";
1120 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1124 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1126 char *string
= input_line_pointer
;
1127 int e
= get_symbol_end ();
1130 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1132 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1136 cpu_arch_name
= cpu_arch
[i
].name
;
1137 cpu_sub_arch_name
= NULL
;
1138 cpu_arch_flags
= (cpu_arch
[i
].flags
1139 | (flag_code
== CODE_64BIT
1140 ? Cpu64
: CpuNo64
));
1141 cpu_arch_isa
= cpu_arch
[i
].type
;
1142 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1143 if (!cpu_arch_tune_set
)
1145 cpu_arch_tune
= cpu_arch_isa
;
1146 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1150 if ((cpu_arch_flags
| cpu_arch
[i
].flags
) != cpu_arch_flags
)
1152 cpu_sub_arch_name
= cpu_arch
[i
].name
;
1153 cpu_arch_flags
|= cpu_arch
[i
].flags
;
1155 *input_line_pointer
= e
;
1156 demand_empty_rest_of_line ();
1160 if (i
>= ARRAY_SIZE (cpu_arch
))
1161 as_bad (_("no such architecture: `%s'"), string
);
1163 *input_line_pointer
= e
;
1166 as_bad (_("missing cpu architecture"));
1168 no_cond_jump_promotion
= 0;
1169 if (*input_line_pointer
== ','
1170 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
1172 char *string
= ++input_line_pointer
;
1173 int e
= get_symbol_end ();
1175 if (strcmp (string
, "nojumps") == 0)
1176 no_cond_jump_promotion
= 1;
1177 else if (strcmp (string
, "jumps") == 0)
1180 as_bad (_("no such architecture modifier: `%s'"), string
);
1182 *input_line_pointer
= e
;
1185 demand_empty_rest_of_line ();
1191 if (!strcmp (default_arch
, "x86_64"))
1192 return bfd_mach_x86_64
;
1193 else if (!strcmp (default_arch
, "i386"))
1194 return bfd_mach_i386_i386
;
1196 as_fatal (_("Unknown architecture"));
1202 const char *hash_err
;
1204 /* Initialize op_hash hash table. */
1205 op_hash
= hash_new ();
1208 const template *optab
;
1209 templates
*core_optab
;
1211 /* Setup for loop. */
1213 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1214 core_optab
->start
= optab
;
1219 if (optab
->name
== NULL
1220 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
1222 /* different name --> ship out current template list;
1223 add to hash table; & begin anew. */
1224 core_optab
->end
= optab
;
1225 hash_err
= hash_insert (op_hash
,
1230 as_fatal (_("Internal Error: Can't hash %s: %s"),
1234 if (optab
->name
== NULL
)
1236 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1237 core_optab
->start
= optab
;
1242 /* Initialize reg_hash hash table. */
1243 reg_hash
= hash_new ();
1245 const reg_entry
*regtab
;
1246 unsigned int regtab_size
= i386_regtab_size
;
1248 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
1250 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
1252 as_fatal (_("Internal Error: Can't hash %s: %s"),
1258 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1263 for (c
= 0; c
< 256; c
++)
1268 mnemonic_chars
[c
] = c
;
1269 register_chars
[c
] = c
;
1270 operand_chars
[c
] = c
;
1272 else if (ISLOWER (c
))
1274 mnemonic_chars
[c
] = c
;
1275 register_chars
[c
] = c
;
1276 operand_chars
[c
] = c
;
1278 else if (ISUPPER (c
))
1280 mnemonic_chars
[c
] = TOLOWER (c
);
1281 register_chars
[c
] = mnemonic_chars
[c
];
1282 operand_chars
[c
] = c
;
1285 if (ISALPHA (c
) || ISDIGIT (c
))
1286 identifier_chars
[c
] = c
;
1289 identifier_chars
[c
] = c
;
1290 operand_chars
[c
] = c
;
1295 identifier_chars
['@'] = '@';
1298 identifier_chars
['?'] = '?';
1299 operand_chars
['?'] = '?';
1301 digit_chars
['-'] = '-';
1302 mnemonic_chars
['-'] = '-';
1303 mnemonic_chars
['.'] = '.';
1304 identifier_chars
['_'] = '_';
1305 identifier_chars
['.'] = '.';
1307 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1308 operand_chars
[(unsigned char) *p
] = *p
;
1311 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1314 record_alignment (text_section
, 2);
1315 record_alignment (data_section
, 2);
1316 record_alignment (bss_section
, 2);
1320 if (flag_code
== CODE_64BIT
)
1322 x86_dwarf2_return_column
= 16;
1323 x86_cie_data_alignment
= -8;
1327 x86_dwarf2_return_column
= 8;
1328 x86_cie_data_alignment
= -4;
1333 i386_print_statistics (FILE *file
)
1335 hash_print_statistics (file
, "i386 opcode", op_hash
);
1336 hash_print_statistics (file
, "i386 register", reg_hash
);
1341 /* Debugging routines for md_assemble. */
1342 static void pte (template *);
1343 static void pt (unsigned int);
1344 static void pe (expressionS
*);
1345 static void ps (symbolS
*);
1348 pi (char *line
, i386_insn
*x
)
1352 fprintf (stdout
, "%s: template ", line
);
1354 fprintf (stdout
, " address: base %s index %s scale %x\n",
1355 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1356 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1357 x
->log2_scale_factor
);
1358 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1359 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1360 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1361 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1362 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1363 (x
->rex
& REX_W
) != 0,
1364 (x
->rex
& REX_R
) != 0,
1365 (x
->rex
& REX_X
) != 0,
1366 (x
->rex
& REX_B
) != 0);
1367 for (i
= 0; i
< x
->operands
; i
++)
1369 fprintf (stdout
, " #%d: ", i
+ 1);
1371 fprintf (stdout
, "\n");
1373 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1374 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1375 if (x
->types
[i
] & Imm
)
1377 if (x
->types
[i
] & Disp
)
1378 pe (x
->op
[i
].disps
);
1386 fprintf (stdout
, " %d operands ", t
->operands
);
1387 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1388 if (t
->extension_opcode
!= None
)
1389 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1390 if (t
->opcode_modifier
& D
)
1391 fprintf (stdout
, "D");
1392 if (t
->opcode_modifier
& W
)
1393 fprintf (stdout
, "W");
1394 fprintf (stdout
, "\n");
1395 for (i
= 0; i
< t
->operands
; i
++)
1397 fprintf (stdout
, " #%d type ", i
+ 1);
1398 pt (t
->operand_types
[i
]);
1399 fprintf (stdout
, "\n");
1406 fprintf (stdout
, " operation %d\n", e
->X_op
);
1407 fprintf (stdout
, " add_number %ld (%lx)\n",
1408 (long) e
->X_add_number
, (long) e
->X_add_number
);
1409 if (e
->X_add_symbol
)
1411 fprintf (stdout
, " add_symbol ");
1412 ps (e
->X_add_symbol
);
1413 fprintf (stdout
, "\n");
1417 fprintf (stdout
, " op_symbol ");
1418 ps (e
->X_op_symbol
);
1419 fprintf (stdout
, "\n");
1426 fprintf (stdout
, "%s type %s%s",
1428 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1429 segment_name (S_GET_SEGMENT (s
)));
1432 static struct type_name
1437 const type_names
[] =
1450 { BaseIndex
, "BaseIndex" },
1454 { Disp32S
, "d32s" },
1456 { InOutPortReg
, "InOutPortReg" },
1457 { ShiftCount
, "ShiftCount" },
1458 { Control
, "control reg" },
1459 { Test
, "test reg" },
1460 { Debug
, "debug reg" },
1461 { FloatReg
, "FReg" },
1462 { FloatAcc
, "FAcc" },
1466 { JumpAbsolute
, "Jump Absolute" },
1477 const struct type_name
*ty
;
1479 for (ty
= type_names
; ty
->mask
; ty
++)
1481 fprintf (stdout
, "%s, ", ty
->tname
);
1485 #endif /* DEBUG386 */
1487 static bfd_reloc_code_real_type
1488 reloc (unsigned int size
,
1491 bfd_reloc_code_real_type other
)
1493 if (other
!= NO_RELOC
)
1495 reloc_howto_type
*reloc
;
1500 case BFD_RELOC_X86_64_GOT32
:
1501 return BFD_RELOC_X86_64_GOT64
;
1503 case BFD_RELOC_X86_64_PLTOFF64
:
1504 return BFD_RELOC_X86_64_PLTOFF64
;
1506 case BFD_RELOC_X86_64_GOTPC32
:
1507 other
= BFD_RELOC_X86_64_GOTPC64
;
1509 case BFD_RELOC_X86_64_GOTPCREL
:
1510 other
= BFD_RELOC_X86_64_GOTPCREL64
;
1512 case BFD_RELOC_X86_64_TPOFF32
:
1513 other
= BFD_RELOC_X86_64_TPOFF64
;
1515 case BFD_RELOC_X86_64_DTPOFF32
:
1516 other
= BFD_RELOC_X86_64_DTPOFF64
;
1522 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1523 if (size
== 4 && flag_code
!= CODE_64BIT
)
1526 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
1528 as_bad (_("unknown relocation (%u)"), other
);
1529 else if (size
!= bfd_get_reloc_size (reloc
))
1530 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1531 bfd_get_reloc_size (reloc
),
1533 else if (pcrel
&& !reloc
->pc_relative
)
1534 as_bad (_("non-pc-relative relocation for pc-relative field"));
1535 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
1537 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
1539 as_bad (_("relocated field and relocation type differ in signedness"));
1548 as_bad (_("there are no unsigned pc-relative relocations"));
1551 case 1: return BFD_RELOC_8_PCREL
;
1552 case 2: return BFD_RELOC_16_PCREL
;
1553 case 4: return BFD_RELOC_32_PCREL
;
1554 case 8: return BFD_RELOC_64_PCREL
;
1556 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
1563 case 4: return BFD_RELOC_X86_64_32S
;
1568 case 1: return BFD_RELOC_8
;
1569 case 2: return BFD_RELOC_16
;
1570 case 4: return BFD_RELOC_32
;
1571 case 8: return BFD_RELOC_64
;
1573 as_bad (_("cannot do %s %u byte relocation"),
1574 sign
> 0 ? "signed" : "unsigned", size
);
1578 return BFD_RELOC_NONE
;
1581 /* Here we decide which fixups can be adjusted to make them relative to
1582 the beginning of the section instead of the symbol. Basically we need
1583 to make sure that the dynamic relocations are done correctly, so in
1584 some cases we force the original symbol to be used. */
1587 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
1589 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1593 /* Don't adjust pc-relative references to merge sections in 64-bit
1595 if (use_rela_relocations
1596 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1600 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1601 and changed later by validate_fix. */
1602 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
1603 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
1606 /* adjust_reloc_syms doesn't know about the GOT. */
1607 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1608 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1609 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1610 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1611 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1612 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1613 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1614 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1615 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1616 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1617 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1618 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
1619 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
1620 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1621 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1622 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1623 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1624 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1625 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1626 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
1627 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1628 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1629 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
1630 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
1631 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
1632 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
1633 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1634 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1641 intel_float_operand (const char *mnemonic
)
1643 /* Note that the value returned is meaningful only for opcodes with (memory)
1644 operands, hence the code here is free to improperly handle opcodes that
1645 have no operands (for better performance and smaller code). */
1647 if (mnemonic
[0] != 'f')
1648 return 0; /* non-math */
1650 switch (mnemonic
[1])
1652 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1653 the fs segment override prefix not currently handled because no
1654 call path can make opcodes without operands get here */
1656 return 2 /* integer op */;
1658 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
1659 return 3; /* fldcw/fldenv */
1662 if (mnemonic
[2] != 'o' /* fnop */)
1663 return 3; /* non-waiting control op */
1666 if (mnemonic
[2] == 's')
1667 return 3; /* frstor/frstpm */
1670 if (mnemonic
[2] == 'a')
1671 return 3; /* fsave */
1672 if (mnemonic
[2] == 't')
1674 switch (mnemonic
[3])
1676 case 'c': /* fstcw */
1677 case 'd': /* fstdw */
1678 case 'e': /* fstenv */
1679 case 's': /* fsts[gw] */
1685 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
1686 return 0; /* fxsave/fxrstor are not really math ops */
1693 /* This is the guts of the machine-dependent assembler. LINE points to a
1694 machine dependent instruction. This function is supposed to emit
1695 the frags/bytes it assembles to. */
1702 char mnemonic
[MAX_MNEM_SIZE
];
1704 /* Initialize globals. */
1705 memset (&i
, '\0', sizeof (i
));
1706 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1707 i
.reloc
[j
] = NO_RELOC
;
1708 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1709 memset (im_expressions
, '\0', sizeof (im_expressions
));
1710 save_stack_p
= save_stack
;
1712 /* First parse an instruction mnemonic & call i386_operand for the operands.
1713 We assume that the scrubber has arranged it so that line[0] is the valid
1714 start of a (possibly prefixed) mnemonic. */
1716 line
= parse_insn (line
, mnemonic
);
1720 line
= parse_operands (line
, mnemonic
);
1724 /* The order of the immediates should be reversed
1725 for 2 immediates extrq and insertq instructions */
1726 if ((i
.imm_operands
== 2)
1727 && ((strcmp (mnemonic
, "extrq") == 0)
1728 || (strcmp (mnemonic
, "insertq") == 0)))
1730 swap_2_operands (0, 1);
1731 /* "extrq" and insertq" are the only two instructions whose operands
1732 have to be reversed even though they have two immediate operands.
1738 /* Now we've parsed the mnemonic into a set of templates, and have the
1739 operands at hand. */
1741 /* All intel opcodes have reversed operands except for "bound" and
1742 "enter". We also don't reverse intersegment "jmp" and "call"
1743 instructions with 2 immediate operands so that the immediate segment
1744 precedes the offset, as it does when in AT&T mode. */
1747 && (strcmp (mnemonic
, "bound") != 0)
1748 && (strcmp (mnemonic
, "invlpga") != 0)
1749 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1755 /* Don't optimize displacement for movabs since it only takes 64bit
1758 && (flag_code
!= CODE_64BIT
1759 || strcmp (mnemonic
, "movabs") != 0))
1762 /* Next, we find a template that matches the given insn,
1763 making sure the overlap of the given operands types is consistent
1764 with the template operand types. */
1766 if (!match_template ())
1771 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1773 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1774 i
.tm
.base_opcode
^= Opcode_FloatR
;
1776 /* Zap movzx and movsx suffix. The suffix may have been set from
1777 "word ptr" or "byte ptr" on the source operand, but we'll use
1778 the suffix later to choose the destination register. */
1779 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1781 if (i
.reg_operands
< 2
1783 && (~i
.tm
.opcode_modifier
1790 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
1796 if (i
.tm
.opcode_modifier
& FWait
)
1797 if (!add_prefix (FWAIT_OPCODE
))
1800 /* Check string instruction segment overrides. */
1801 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1803 if (!check_string ())
1807 if (!process_suffix ())
1810 /* Make still unresolved immediate matches conform to size of immediate
1811 given in i.suffix. */
1812 if (!finalize_imm ())
1815 if (i
.types
[0] & Imm1
)
1816 i
.imm_operands
= 0; /* kludge for shift insns. */
1817 if (i
.types
[0] & ImplicitRegister
)
1819 if (i
.types
[1] & ImplicitRegister
)
1821 if (i
.types
[2] & ImplicitRegister
)
1824 if (i
.tm
.opcode_modifier
& ImmExt
)
1828 if ((i
.tm
.cpu_flags
& CpuSSE3
) && i
.operands
> 0)
1830 /* Streaming SIMD extensions 3 Instructions have the fixed
1831 operands with an opcode suffix which is coded in the same
1832 place as an 8-bit immediate field would be. Here we check
1833 those operands and remove them afterwards. */
1836 for (x
= 0; x
< i
.operands
; x
++)
1837 if (i
.op
[x
].regs
->reg_num
!= x
)
1838 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1839 i
.op
[x
].regs
->reg_name
, x
+ 1, i
.tm
.name
);
1843 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1844 opcode suffix which is coded in the same place as an 8-bit
1845 immediate field would be. Here we fake an 8-bit immediate
1846 operand from the opcode suffix stored in tm.extension_opcode. */
1848 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1850 exp
= &im_expressions
[i
.imm_operands
++];
1851 i
.op
[i
.operands
].imms
= exp
;
1852 i
.types
[i
.operands
++] = Imm8
;
1853 exp
->X_op
= O_constant
;
1854 exp
->X_add_number
= i
.tm
.extension_opcode
;
1855 i
.tm
.extension_opcode
= None
;
1858 /* For insns with operands there are more diddles to do to the opcode. */
1861 if (!process_operands ())
1864 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1866 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1867 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1870 /* Handle conversion of 'int $3' --> special int3 insn. */
1871 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1873 i
.tm
.base_opcode
= INT3_OPCODE
;
1877 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1878 && i
.op
[0].disps
->X_op
== O_constant
)
1880 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1881 the absolute address given by the constant. Since ix86 jumps and
1882 calls are pc relative, we need to generate a reloc. */
1883 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1884 i
.op
[0].disps
->X_op
= O_symbol
;
1887 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1890 /* For 8 bit registers we need an empty rex prefix. Also if the
1891 instruction already has a prefix, we need to convert old
1892 registers to new ones. */
1894 if (((i
.types
[0] & Reg8
) != 0
1895 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1896 || ((i
.types
[1] & Reg8
) != 0
1897 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1898 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1903 i
.rex
|= REX_OPCODE
;
1904 for (x
= 0; x
< 2; x
++)
1906 /* Look for 8 bit operand that uses old registers. */
1907 if ((i
.types
[x
] & Reg8
) != 0
1908 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1910 /* In case it is "hi" register, give up. */
1911 if (i
.op
[x
].regs
->reg_num
> 3)
1912 as_bad (_("can't encode register '%%%s' in an "
1913 "instruction requiring REX prefix."),
1914 i
.op
[x
].regs
->reg_name
);
1916 /* Otherwise it is equivalent to the extended register.
1917 Since the encoding doesn't change this is merely
1918 cosmetic cleanup for debug output. */
1920 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1926 add_prefix (REX_OPCODE
| i
.rex
);
1928 /* We are ready to output the insn. */
1933 parse_insn (char *line
, char *mnemonic
)
1936 char *token_start
= l
;
1941 /* Non-zero if we found a prefix only acceptable with string insns. */
1942 const char *expecting_string_instruction
= NULL
;
1947 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1950 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1952 as_bad (_("no such instruction: `%s'"), token_start
);
1957 if (!is_space_char (*l
)
1958 && *l
!= END_OF_INSN
1960 || (*l
!= PREFIX_SEPARATOR
1963 as_bad (_("invalid character %s in mnemonic"),
1964 output_invalid (*l
));
1967 if (token_start
== l
)
1969 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
1970 as_bad (_("expecting prefix; got nothing"));
1972 as_bad (_("expecting mnemonic; got nothing"));
1976 /* Look up instruction (or prefix) via hash table. */
1977 current_templates
= hash_find (op_hash
, mnemonic
);
1979 if (*l
!= END_OF_INSN
1980 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1981 && current_templates
1982 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1984 if (current_templates
->start
->cpu_flags
1985 & (flag_code
!= CODE_64BIT
? Cpu64
: CpuNo64
))
1987 as_bad ((flag_code
!= CODE_64BIT
1988 ? _("`%s' is only supported in 64-bit mode")
1989 : _("`%s' is not supported in 64-bit mode")),
1990 current_templates
->start
->name
);
1993 /* If we are in 16-bit mode, do not allow addr16 or data16.
1994 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1995 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1996 && flag_code
!= CODE_64BIT
1997 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1998 ^ (flag_code
== CODE_16BIT
)))
2000 as_bad (_("redundant %s prefix"),
2001 current_templates
->start
->name
);
2004 /* Add prefix, checking for repeated prefixes. */
2005 switch (add_prefix (current_templates
->start
->base_opcode
))
2010 expecting_string_instruction
= current_templates
->start
->name
;
2013 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2020 if (!current_templates
)
2022 /* See if we can get a match by trimming off a suffix. */
2025 case WORD_MNEM_SUFFIX
:
2026 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
2027 i
.suffix
= SHORT_MNEM_SUFFIX
;
2029 case BYTE_MNEM_SUFFIX
:
2030 case QWORD_MNEM_SUFFIX
:
2031 i
.suffix
= mnem_p
[-1];
2033 current_templates
= hash_find (op_hash
, mnemonic
);
2035 case SHORT_MNEM_SUFFIX
:
2036 case LONG_MNEM_SUFFIX
:
2039 i
.suffix
= mnem_p
[-1];
2041 current_templates
= hash_find (op_hash
, mnemonic
);
2049 if (intel_float_operand (mnemonic
) == 1)
2050 i
.suffix
= SHORT_MNEM_SUFFIX
;
2052 i
.suffix
= LONG_MNEM_SUFFIX
;
2054 current_templates
= hash_find (op_hash
, mnemonic
);
2058 if (!current_templates
)
2060 as_bad (_("no such instruction: `%s'"), token_start
);
2065 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
2067 /* Check for a branch hint. We allow ",pt" and ",pn" for
2068 predict taken and predict not taken respectively.
2069 I'm not sure that branch hints actually do anything on loop
2070 and jcxz insns (JumpByte) for current Pentium4 chips. They
2071 may work in the future and it doesn't hurt to accept them
2073 if (l
[0] == ',' && l
[1] == 'p')
2077 if (!add_prefix (DS_PREFIX_OPCODE
))
2081 else if (l
[2] == 'n')
2083 if (!add_prefix (CS_PREFIX_OPCODE
))
2089 /* Any other comma loses. */
2092 as_bad (_("invalid character %s in mnemonic"),
2093 output_invalid (*l
));
2097 /* Check if instruction is supported on specified architecture. */
2099 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2101 if (!((t
->cpu_flags
& ~(Cpu64
| CpuNo64
))
2102 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
))))
2104 if (!(t
->cpu_flags
& (flag_code
== CODE_64BIT
? CpuNo64
: Cpu64
)))
2107 if (!(supported
& 2))
2109 as_bad (flag_code
== CODE_64BIT
2110 ? _("`%s' is not supported in 64-bit mode")
2111 : _("`%s' is only supported in 64-bit mode"),
2112 current_templates
->start
->name
);
2115 if (!(supported
& 1))
2117 as_warn (_("`%s' is not supported on `%s%s'"),
2118 current_templates
->start
->name
,
2120 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
2122 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
2124 as_warn (_("use .code16 to ensure correct addressing mode"));
2127 /* Check for rep/repne without a string instruction. */
2128 if (expecting_string_instruction
)
2130 static templates override
;
2132 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2133 if (t
->opcode_modifier
& IsString
)
2135 if (t
>= current_templates
->end
)
2137 as_bad (_("expecting string instruction after `%s'"),
2138 expecting_string_instruction
);
2141 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
2142 if (!(t
->opcode_modifier
& IsString
))
2145 current_templates
= &override
;
2152 parse_operands (char *l
, const char *mnemonic
)
2156 /* 1 if operand is pending after ','. */
2157 unsigned int expecting_operand
= 0;
2159 /* Non-zero if operand parens not balanced. */
2160 unsigned int paren_not_balanced
;
2162 while (*l
!= END_OF_INSN
)
2164 /* Skip optional white space before operand. */
2165 if (is_space_char (*l
))
2167 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
2169 as_bad (_("invalid character %s before operand %d"),
2170 output_invalid (*l
),
2174 token_start
= l
; /* after white space */
2175 paren_not_balanced
= 0;
2176 while (paren_not_balanced
|| *l
!= ',')
2178 if (*l
== END_OF_INSN
)
2180 if (paren_not_balanced
)
2183 as_bad (_("unbalanced parenthesis in operand %d."),
2186 as_bad (_("unbalanced brackets in operand %d."),
2191 break; /* we are done */
2193 else if (!is_operand_char (*l
) && !is_space_char (*l
))
2195 as_bad (_("invalid character %s in operand %d"),
2196 output_invalid (*l
),
2203 ++paren_not_balanced
;
2205 --paren_not_balanced
;
2210 ++paren_not_balanced
;
2212 --paren_not_balanced
;
2216 if (l
!= token_start
)
2217 { /* Yes, we've read in another operand. */
2218 unsigned int operand_ok
;
2219 this_operand
= i
.operands
++;
2220 if (i
.operands
> MAX_OPERANDS
)
2222 as_bad (_("spurious operands; (%d operands/instruction max)"),
2226 /* Now parse operand adding info to 'i' as we go along. */
2227 END_STRING_AND_SAVE (l
);
2231 i386_intel_operand (token_start
,
2232 intel_float_operand (mnemonic
));
2234 operand_ok
= i386_operand (token_start
);
2236 RESTORE_END_STRING (l
);
2242 if (expecting_operand
)
2244 expecting_operand_after_comma
:
2245 as_bad (_("expecting operand after ','; got nothing"));
2250 as_bad (_("expecting operand before ','; got nothing"));
2255 /* Now *l must be either ',' or END_OF_INSN. */
2258 if (*++l
== END_OF_INSN
)
2260 /* Just skip it, if it's \n complain. */
2261 goto expecting_operand_after_comma
;
2263 expecting_operand
= 1;
2270 swap_2_operands (int xchg1
, int xchg2
)
2272 union i386_op temp_op
;
2273 unsigned int temp_type
;
2274 enum bfd_reloc_code_real temp_reloc
;
2276 temp_type
= i
.types
[xchg2
];
2277 i
.types
[xchg2
] = i
.types
[xchg1
];
2278 i
.types
[xchg1
] = temp_type
;
2279 temp_op
= i
.op
[xchg2
];
2280 i
.op
[xchg2
] = i
.op
[xchg1
];
2281 i
.op
[xchg1
] = temp_op
;
2282 temp_reloc
= i
.reloc
[xchg2
];
2283 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
2284 i
.reloc
[xchg1
] = temp_reloc
;
2288 swap_operands (void)
2293 swap_2_operands (1, i
.operands
- 2);
2296 swap_2_operands (0, i
.operands
- 1);
2302 if (i
.mem_operands
== 2)
2304 const seg_entry
*temp_seg
;
2305 temp_seg
= i
.seg
[0];
2306 i
.seg
[0] = i
.seg
[1];
2307 i
.seg
[1] = temp_seg
;
2311 /* Try to ensure constant immediates are represented in the smallest
2316 char guess_suffix
= 0;
2320 guess_suffix
= i
.suffix
;
2321 else if (i
.reg_operands
)
2323 /* Figure out a suffix from the last register operand specified.
2324 We can't do this properly yet, ie. excluding InOutPortReg,
2325 but the following works for instructions with immediates.
2326 In any case, we can't set i.suffix yet. */
2327 for (op
= i
.operands
; --op
>= 0;)
2328 if (i
.types
[op
] & Reg
)
2330 if (i
.types
[op
] & Reg8
)
2331 guess_suffix
= BYTE_MNEM_SUFFIX
;
2332 else if (i
.types
[op
] & Reg16
)
2333 guess_suffix
= WORD_MNEM_SUFFIX
;
2334 else if (i
.types
[op
] & Reg32
)
2335 guess_suffix
= LONG_MNEM_SUFFIX
;
2336 else if (i
.types
[op
] & Reg64
)
2337 guess_suffix
= QWORD_MNEM_SUFFIX
;
2341 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
2342 guess_suffix
= WORD_MNEM_SUFFIX
;
2344 for (op
= i
.operands
; --op
>= 0;)
2345 if (i
.types
[op
] & Imm
)
2347 switch (i
.op
[op
].imms
->X_op
)
2350 /* If a suffix is given, this operand may be shortened. */
2351 switch (guess_suffix
)
2353 case LONG_MNEM_SUFFIX
:
2354 i
.types
[op
] |= Imm32
| Imm64
;
2356 case WORD_MNEM_SUFFIX
:
2357 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
2359 case BYTE_MNEM_SUFFIX
:
2360 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
2364 /* If this operand is at most 16 bits, convert it
2365 to a signed 16 bit number before trying to see
2366 whether it will fit in an even smaller size.
2367 This allows a 16-bit operand such as $0xffe0 to
2368 be recognised as within Imm8S range. */
2369 if ((i
.types
[op
] & Imm16
)
2370 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
2372 i
.op
[op
].imms
->X_add_number
=
2373 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2375 if ((i
.types
[op
] & Imm32
)
2376 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2379 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2380 ^ ((offsetT
) 1 << 31))
2381 - ((offsetT
) 1 << 31));
2383 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
2385 /* We must avoid matching of Imm32 templates when 64bit
2386 only immediate is available. */
2387 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2388 i
.types
[op
] &= ~Imm32
;
2395 /* Symbols and expressions. */
2397 /* Convert symbolic operand to proper sizes for matching, but don't
2398 prevent matching a set of insns that only supports sizes other
2399 than those matching the insn suffix. */
2401 unsigned int mask
, allowed
= 0;
2404 for (t
= current_templates
->start
;
2405 t
< current_templates
->end
;
2407 allowed
|= t
->operand_types
[op
];
2408 switch (guess_suffix
)
2410 case QWORD_MNEM_SUFFIX
:
2411 mask
= Imm64
| Imm32S
;
2413 case LONG_MNEM_SUFFIX
:
2416 case WORD_MNEM_SUFFIX
:
2419 case BYTE_MNEM_SUFFIX
:
2427 i
.types
[op
] &= mask
;
2434 /* Try to use the smallest displacement type too. */
2436 optimize_disp (void)
2440 for (op
= i
.operands
; --op
>= 0;)
2441 if (i
.types
[op
] & Disp
)
2443 if (i
.op
[op
].disps
->X_op
== O_constant
)
2445 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
2447 if ((i
.types
[op
] & Disp16
)
2448 && (disp
& ~(offsetT
) 0xffff) == 0)
2450 /* If this operand is at most 16 bits, convert
2451 to a signed 16 bit number and don't use 64bit
2453 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
2454 i
.types
[op
] &= ~Disp64
;
2456 if ((i
.types
[op
] & Disp32
)
2457 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
2459 /* If this operand is at most 32 bits, convert
2460 to a signed 32 bit number and don't use 64bit
2462 disp
&= (((offsetT
) 2 << 31) - 1);
2463 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
2464 i
.types
[op
] &= ~Disp64
;
2466 if (!disp
&& (i
.types
[op
] & BaseIndex
))
2468 i
.types
[op
] &= ~Disp
;
2472 else if (flag_code
== CODE_64BIT
)
2474 if (fits_in_signed_long (disp
))
2476 i
.types
[op
] &= ~Disp64
;
2477 i
.types
[op
] |= Disp32S
;
2479 if (fits_in_unsigned_long (disp
))
2480 i
.types
[op
] |= Disp32
;
2482 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
2483 && fits_in_signed_byte (disp
))
2484 i
.types
[op
] |= Disp8
;
2486 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
2487 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
2489 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
2490 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
2491 i
.types
[op
] &= ~Disp
;
2494 /* We only support 64bit displacement on constants. */
2495 i
.types
[op
] &= ~Disp64
;
2500 match_template (void)
2502 /* Points to template once we've found it. */
2504 unsigned int overlap0
, overlap1
, overlap2
, overlap3
;
2505 unsigned int found_reverse_match
;
2507 unsigned int operand_types
[MAX_OPERANDS
];
2508 int addr_prefix_disp
;
2511 #if MAX_OPERANDS != 4
2512 # error "MAX_OPERANDS must be 4."
2515 #define MATCH(overlap, given, template) \
2516 ((overlap & ~JumpAbsolute) \
2517 && (((given) & (BaseIndex | JumpAbsolute)) \
2518 == ((overlap) & (BaseIndex | JumpAbsolute))))
2520 /* If given types r0 and r1 are registers they must be of the same type
2521 unless the expected operand type register overlap is null.
2522 Note that Acc in a template matches every size of reg. */
2523 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2524 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2525 || ((g0) & Reg) == ((g1) & Reg) \
2526 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2532 found_reverse_match
= 0;
2533 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2534 operand_types
[j
] = 0;
2535 addr_prefix_disp
= -1;
2536 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
2538 : (i
.suffix
== WORD_MNEM_SUFFIX
2540 : (i
.suffix
== SHORT_MNEM_SUFFIX
2542 : (i
.suffix
== LONG_MNEM_SUFFIX
2544 : (i
.suffix
== QWORD_MNEM_SUFFIX
2546 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
2547 ? No_xSuf
: 0))))));
2549 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
2551 addr_prefix_disp
= -1;
2553 /* Must have right number of operands. */
2554 if (i
.operands
!= t
->operands
)
2557 /* Check the suffix, except for some instructions in intel mode. */
2558 if ((t
->opcode_modifier
& suffix_check
)
2560 && (t
->opcode_modifier
& IgnoreSize
)))
2563 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2564 operand_types
[j
] = t
->operand_types
[j
];
2566 /* In general, don't allow 64-bit operands in 32-bit mode. */
2567 if (i
.suffix
== QWORD_MNEM_SUFFIX
2568 && flag_code
!= CODE_64BIT
2570 ? (!(t
->opcode_modifier
& IgnoreSize
)
2571 && !intel_float_operand (t
->name
))
2572 : intel_float_operand (t
->name
) != 2)
2573 && (!(operand_types
[0] & (RegMMX
| RegXMM
))
2574 || !(operand_types
[t
->operands
> 1] & (RegMMX
| RegXMM
)))
2575 && (t
->base_opcode
!= 0x0fc7
2576 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
2579 /* Do not verify operands when there are none. */
2580 else if (!t
->operands
)
2582 if (t
->cpu_flags
& ~cpu_arch_flags
)
2584 /* We've found a match; break out of loop. */
2588 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2589 into Disp32/Disp16/Disp32 operand. */
2590 if (i
.prefix
[ADDR_PREFIX
] != 0)
2592 unsigned int DispOn
= 0, DispOff
= 0;
2610 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2612 /* There should be only one Disp operand. */
2613 if ((operand_types
[j
] & DispOff
))
2615 addr_prefix_disp
= j
;
2616 operand_types
[j
] |= DispOn
;
2617 operand_types
[j
] &= ~DispOff
;
2623 overlap0
= i
.types
[0] & operand_types
[0];
2624 switch (t
->operands
)
2627 if (!MATCH (overlap0
, i
.types
[0], operand_types
[0]))
2631 /* xchg %eax, %eax is a special case. It is an aliase for nop
2632 only in 32bit mode and we can use opcode 0x90. In 64bit
2633 mode, we can't use 0x90 for xchg %eax, %eax since it should
2634 zero-extend %eax to %rax. */
2635 if (flag_code
== CODE_64BIT
2636 && t
->base_opcode
== 0x90
2637 && i
.types
[0] == (Acc
| Reg32
)
2638 && i
.types
[1] == (Acc
| Reg32
))
2642 overlap1
= i
.types
[1] & operand_types
[1];
2643 if (!MATCH (overlap0
, i
.types
[0], operand_types
[0])
2644 || !MATCH (overlap1
, i
.types
[1], operand_types
[1])
2645 /* monitor in SSE3 is a very special case. The first
2646 register and the second register may have different
2647 sizes. The same applies to crc32 in SSE4.2. */
2648 || !((t
->base_opcode
== 0x0f01
2649 && t
->extension_opcode
== 0xc8)
2650 || t
->base_opcode
== 0xf20f38f1
2651 || CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2653 overlap1
, i
.types
[1],
2656 /* Check if other direction is valid ... */
2657 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2660 /* Try reversing direction of operands. */
2661 overlap0
= i
.types
[0] & operand_types
[1];
2662 overlap1
= i
.types
[1] & operand_types
[0];
2663 if (!MATCH (overlap0
, i
.types
[0], operand_types
[1])
2664 || !MATCH (overlap1
, i
.types
[1], operand_types
[0])
2665 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2667 overlap1
, i
.types
[1],
2670 /* Does not match either direction. */
2673 /* found_reverse_match holds which of D or FloatDR
2675 if ((t
->opcode_modifier
& D
))
2676 found_reverse_match
= Opcode_D
;
2677 else if ((t
->opcode_modifier
& FloatD
))
2678 found_reverse_match
= Opcode_FloatD
;
2680 found_reverse_match
= 0;
2681 if ((t
->opcode_modifier
& FloatR
))
2682 found_reverse_match
|= Opcode_FloatR
;
2686 /* Found a forward 2 operand match here. */
2687 switch (t
->operands
)
2690 overlap3
= i
.types
[3] & operand_types
[3];
2692 overlap2
= i
.types
[2] & operand_types
[2];
2696 switch (t
->operands
)
2699 if (!MATCH (overlap3
, i
.types
[3], operand_types
[3])
2700 || !CONSISTENT_REGISTER_MATCH (overlap2
,
2708 /* Here we make use of the fact that there are no
2709 reverse match 3 operand instructions, and all 3
2710 operand instructions only need to be checked for
2711 register consistency between operands 2 and 3. */
2712 if (!MATCH (overlap2
, i
.types
[2], operand_types
[2])
2713 || !CONSISTENT_REGISTER_MATCH (overlap1
,
2723 /* Found either forward/reverse 2, 3 or 4 operand match here:
2724 slip through to break. */
2726 if (t
->cpu_flags
& ~cpu_arch_flags
)
2728 found_reverse_match
= 0;
2731 /* We've found a match; break out of loop. */
2735 if (t
== current_templates
->end
)
2737 /* We found no match. */
2738 as_bad (_("suffix or operands invalid for `%s'"),
2739 current_templates
->start
->name
);
2743 if (!quiet_warnings
)
2746 && ((i
.types
[0] & JumpAbsolute
)
2747 != (operand_types
[0] & JumpAbsolute
)))
2749 as_warn (_("indirect %s without `*'"), t
->name
);
2752 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2753 == (IsPrefix
| IgnoreSize
))
2755 /* Warn them that a data or address size prefix doesn't
2756 affect assembly of the next line of code. */
2757 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2761 /* Copy the template we found. */
2764 if (addr_prefix_disp
!= -1)
2765 i
.tm
.operand_types
[addr_prefix_disp
]
2766 = operand_types
[addr_prefix_disp
];
2768 if (found_reverse_match
)
2770 /* If we found a reverse match we must alter the opcode
2771 direction bit. found_reverse_match holds bits to change
2772 (different for int & float insns). */
2774 i
.tm
.base_opcode
^= found_reverse_match
;
2776 i
.tm
.operand_types
[0] = operand_types
[1];
2777 i
.tm
.operand_types
[1] = operand_types
[0];
2786 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2787 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2789 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2791 as_bad (_("`%s' operand %d must use `%%es' segment"),
2796 /* There's only ever one segment override allowed per instruction.
2797 This instruction possibly has a legal segment override on the
2798 second operand, so copy the segment to where non-string
2799 instructions store it, allowing common code. */
2800 i
.seg
[0] = i
.seg
[1];
2802 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2804 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2806 as_bad (_("`%s' operand %d must use `%%es' segment"),
2816 process_suffix (void)
2818 /* If matched instruction specifies an explicit instruction mnemonic
2820 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2822 if (i
.tm
.opcode_modifier
& Size16
)
2823 i
.suffix
= WORD_MNEM_SUFFIX
;
2824 else if (i
.tm
.opcode_modifier
& Size64
)
2825 i
.suffix
= QWORD_MNEM_SUFFIX
;
2827 i
.suffix
= LONG_MNEM_SUFFIX
;
2829 else if (i
.reg_operands
)
2831 /* If there's no instruction mnemonic suffix we try to invent one
2832 based on register operands. */
2835 /* We take i.suffix from the last register operand specified,
2836 Destination register type is more significant than source
2837 register type. crc32 in SSE4.2 prefers source register
2839 if (i
.tm
.base_opcode
== 0xf20f38f1)
2841 if ((i
.types
[0] & Reg
))
2842 i
.suffix
= ((i
.types
[0] & Reg16
) ? WORD_MNEM_SUFFIX
:
2850 for (op
= i
.operands
; --op
>= 0;)
2851 if ((i
.types
[op
] & Reg
)
2852 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2854 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2855 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2856 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2862 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2864 if (!check_byte_reg ())
2867 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2869 if (!check_long_reg ())
2872 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2874 if (!check_qword_reg ())
2877 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2879 if (!check_word_reg ())
2882 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2883 /* Do nothing if the instruction is going to ignore the prefix. */
2888 else if ((i
.tm
.opcode_modifier
& DefaultSize
)
2890 /* exclude fldenv/frstor/fsave/fstenv */
2891 && (i
.tm
.opcode_modifier
& No_sSuf
))
2893 i
.suffix
= stackop_size
;
2895 else if (intel_syntax
2897 && ((i
.tm
.operand_types
[0] & JumpAbsolute
)
2898 || (i
.tm
.opcode_modifier
& (JumpByte
|JumpInterSegment
))
2899 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
2900 && i
.tm
.extension_opcode
<= 3)))
2905 if (!(i
.tm
.opcode_modifier
& No_qSuf
))
2907 i
.suffix
= QWORD_MNEM_SUFFIX
;
2911 if (!(i
.tm
.opcode_modifier
& No_lSuf
))
2912 i
.suffix
= LONG_MNEM_SUFFIX
;
2915 if (!(i
.tm
.opcode_modifier
& No_wSuf
))
2916 i
.suffix
= WORD_MNEM_SUFFIX
;
2925 if (i
.tm
.opcode_modifier
& W
)
2927 as_bad (_("no instruction mnemonic suffix given and "
2928 "no register operands; can't size instruction"));
2934 unsigned int suffixes
= (~i
.tm
.opcode_modifier
2942 if ((i
.tm
.opcode_modifier
& W
)
2943 || ((suffixes
& (suffixes
- 1))
2944 && !(i
.tm
.opcode_modifier
& (DefaultSize
| IgnoreSize
))))
2946 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2952 /* Change the opcode based on the operand size given by i.suffix;
2953 We don't need to change things for byte insns. */
2955 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2957 /* It's not a byte, select word/dword operation. */
2958 if (i
.tm
.opcode_modifier
& W
)
2960 if (i
.tm
.opcode_modifier
& ShortForm
)
2961 i
.tm
.base_opcode
|= 8;
2963 i
.tm
.base_opcode
|= 1;
2966 /* Now select between word & dword operations via the operand
2967 size prefix, except for instructions that will ignore this
2969 if (i
.tm
.base_opcode
== 0x0f01 && i
.tm
.extension_opcode
== 0xc8)
2971 /* monitor in SSE3 is a very special case. The default size
2972 of AX is the size of mode. The address size override
2973 prefix will change the size of AX. */
2974 if (i
.op
->regs
[0].reg_type
&
2975 (flag_code
== CODE_32BIT
? Reg16
: Reg32
))
2976 if (!add_prefix (ADDR_PREFIX_OPCODE
))
2979 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
2980 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
2981 && !(i
.tm
.opcode_modifier
& (IgnoreSize
| FloatMF
))
2982 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2983 || (flag_code
== CODE_64BIT
2984 && (i
.tm
.opcode_modifier
& JumpByte
))))
2986 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2988 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2989 prefix
= ADDR_PREFIX_OPCODE
;
2991 if (!add_prefix (prefix
))
2995 /* Set mode64 for an operand. */
2996 if (i
.suffix
== QWORD_MNEM_SUFFIX
2997 && flag_code
== CODE_64BIT
2998 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
3000 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3003 || i
.types
[0] != (Acc
| Reg64
)
3004 || i
.types
[1] != (Acc
| Reg64
)
3005 || i
.tm
.base_opcode
!= 0x90)
3009 /* Size floating point instruction. */
3010 if (i
.suffix
== LONG_MNEM_SUFFIX
)
3011 if (i
.tm
.opcode_modifier
& FloatMF
)
3012 i
.tm
.base_opcode
^= 4;
3019 check_byte_reg (void)
3023 for (op
= i
.operands
; --op
>= 0;)
3025 /* If this is an eight bit register, it's OK. If it's the 16 or
3026 32 bit version of an eight bit register, we will just use the
3027 low portion, and that's OK too. */
3028 if (i
.types
[op
] & Reg8
)
3031 /* movzx and movsx should not generate this warning. */
3033 && (i
.tm
.base_opcode
== 0xfb7
3034 || i
.tm
.base_opcode
== 0xfb6
3035 || i
.tm
.base_opcode
== 0x63
3036 || i
.tm
.base_opcode
== 0xfbe
3037 || i
.tm
.base_opcode
== 0xfbf))
3040 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4)
3042 /* Prohibit these changes in the 64bit mode, since the
3043 lowering is more complicated. */
3044 if (flag_code
== CODE_64BIT
3045 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
3047 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3048 register_prefix
, i
.op
[op
].regs
->reg_name
,
3052 #if REGISTER_WARNINGS
3054 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
3055 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3056 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
3057 ? REGNAM_AL
- REGNAM_AX
3058 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
3059 i
.op
[op
].regs
->reg_name
,
3064 /* Any other register is bad. */
3065 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
3067 | Control
| Debug
| Test
3068 | FloatReg
| FloatAcc
))
3070 as_bad (_("`%%%s' not allowed with `%s%c'"),
3071 i
.op
[op
].regs
->reg_name
,
3081 check_long_reg (void)
3085 for (op
= i
.operands
; --op
>= 0;)
3086 /* Reject eight bit registers, except where the template requires
3087 them. (eg. movzb) */
3088 if ((i
.types
[op
] & Reg8
) != 0
3089 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3091 as_bad (_("`%%%s' not allowed with `%s%c'"),
3092 i
.op
[op
].regs
->reg_name
,
3097 /* Warn if the e prefix on a general reg is missing. */
3098 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3099 && (i
.types
[op
] & Reg16
) != 0
3100 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3102 /* Prohibit these changes in the 64bit mode, since the
3103 lowering is more complicated. */
3104 if (flag_code
== CODE_64BIT
)
3106 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3107 register_prefix
, i
.op
[op
].regs
->reg_name
,
3111 #if REGISTER_WARNINGS
3113 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3114 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
3115 i
.op
[op
].regs
->reg_name
,
3119 /* Warn if the r prefix on a general reg is missing. */
3120 else if ((i
.types
[op
] & Reg64
) != 0
3121 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3123 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3124 register_prefix
, i
.op
[op
].regs
->reg_name
,
3132 check_qword_reg (void)
3136 for (op
= i
.operands
; --op
>= 0; )
3137 /* Reject eight bit registers, except where the template requires
3138 them. (eg. movzb) */
3139 if ((i
.types
[op
] & Reg8
) != 0
3140 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3142 as_bad (_("`%%%s' not allowed with `%s%c'"),
3143 i
.op
[op
].regs
->reg_name
,
3148 /* Warn if the e prefix on a general reg is missing. */
3149 else if (((i
.types
[op
] & Reg16
) != 0
3150 || (i
.types
[op
] & Reg32
) != 0)
3151 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3153 /* Prohibit these changes in the 64bit mode, since the
3154 lowering is more complicated. */
3155 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3156 register_prefix
, i
.op
[op
].regs
->reg_name
,
3164 check_word_reg (void)
3167 for (op
= i
.operands
; --op
>= 0;)
3168 /* Reject eight bit registers, except where the template requires
3169 them. (eg. movzb) */
3170 if ((i
.types
[op
] & Reg8
) != 0
3171 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3173 as_bad (_("`%%%s' not allowed with `%s%c'"),
3174 i
.op
[op
].regs
->reg_name
,
3179 /* Warn if the e prefix on a general reg is present. */
3180 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3181 && (i
.types
[op
] & Reg32
) != 0
3182 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
3184 /* Prohibit these changes in the 64bit mode, since the
3185 lowering is more complicated. */
3186 if (flag_code
== CODE_64BIT
)
3188 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3189 register_prefix
, i
.op
[op
].regs
->reg_name
,
3194 #if REGISTER_WARNINGS
3195 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3196 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
3197 i
.op
[op
].regs
->reg_name
,
3207 unsigned int overlap0
, overlap1
, overlap2
;
3209 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
3210 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
))
3211 && overlap0
!= Imm8
&& overlap0
!= Imm8S
3212 && overlap0
!= Imm16
&& overlap0
!= Imm32S
3213 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
3217 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
3219 : (i
.suffix
== WORD_MNEM_SUFFIX
3221 : (i
.suffix
== QWORD_MNEM_SUFFIX
3225 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
3226 || overlap0
== (Imm16
| Imm32
)
3227 || overlap0
== (Imm16
| Imm32S
))
3229 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
3232 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
3233 && overlap0
!= Imm16
&& overlap0
!= Imm32S
3234 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
3236 as_bad (_("no instruction mnemonic suffix given; "
3237 "can't determine immediate size"));
3241 i
.types
[0] = overlap0
;
3243 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
3244 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
| Imm64
))
3245 && overlap1
!= Imm8
&& overlap1
!= Imm8S
3246 && overlap1
!= Imm16
&& overlap1
!= Imm32S
3247 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
3251 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
3253 : (i
.suffix
== WORD_MNEM_SUFFIX
3255 : (i
.suffix
== QWORD_MNEM_SUFFIX
3259 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
3260 || overlap1
== (Imm16
| Imm32
)
3261 || overlap1
== (Imm16
| Imm32S
))
3263 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
3266 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
3267 && overlap1
!= Imm16
&& overlap1
!= Imm32S
3268 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
3270 as_bad (_("no instruction mnemonic suffix given; "
3271 "can't determine immediate size %x %c"),
3272 overlap1
, i
.suffix
);
3276 i
.types
[1] = overlap1
;
3278 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
3279 assert ((overlap2
& Imm
) == 0);
3280 i
.types
[2] = overlap2
;
3286 process_operands (void)
3288 /* Default segment register this instruction will use for memory
3289 accesses. 0 means unknown. This is only for optimizing out
3290 unnecessary segment overrides. */
3291 const seg_entry
*default_seg
= 0;
3293 /* The imul $imm, %reg instruction is converted into
3294 imul $imm, %reg, %reg, and the clr %reg instruction
3295 is converted into xor %reg, %reg. */
3296 if (i
.tm
.opcode_modifier
& regKludge
)
3298 if ((i
.tm
.cpu_flags
& CpuSSE4_1
))
3300 /* The first operand in instruction blendvpd, blendvps and
3301 pblendvb in SSE4.1 is implicit and must be xmm0. */
3302 assert (i
.operands
== 3
3303 && i
.reg_operands
>= 2
3304 && i
.types
[0] == RegXMM
);
3305 if (i
.op
[0].regs
->reg_num
!= 0)
3308 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
3309 i
.tm
.name
, register_prefix
);
3311 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
3312 i
.tm
.name
, register_prefix
);
3317 i
.types
[0] = i
.types
[1];
3318 i
.types
[1] = i
.types
[2];
3322 /* We need to adjust fields in i.tm since they are used by
3323 build_modrm_byte. */
3324 i
.tm
.operand_types
[0] = i
.tm
.operand_types
[1];
3325 i
.tm
.operand_types
[1] = i
.tm
.operand_types
[2];
3330 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
3331 /* Pretend we saw the extra register operand. */
3332 assert (i
.reg_operands
== 1
3333 && i
.op
[first_reg_op
+ 1].regs
== 0);
3334 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
3335 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
3341 if (i
.tm
.opcode_modifier
& ShortForm
)
3343 if (i
.types
[0] & (SReg2
| SReg3
))
3345 if (i
.tm
.base_opcode
== POP_SEG_SHORT
3346 && i
.op
[0].regs
->reg_num
== 1)
3348 as_bad (_("you can't `pop %%cs'"));
3351 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
3352 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
3357 /* The register or float register operand is in operand 0 or 1. */
3358 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
3359 /* Register goes in low 3 bits of opcode. */
3360 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
3361 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3363 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
3365 /* Warn about some common errors, but press on regardless.
3366 The first case can be generated by gcc (<= 2.8.1). */
3367 if (i
.operands
== 2)
3369 /* Reversed arguments on faddp, fsubp, etc. */
3370 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
3371 i
.op
[1].regs
->reg_name
,
3372 i
.op
[0].regs
->reg_name
);
3376 /* Extraneous `l' suffix on fp insn. */
3377 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
3378 i
.op
[0].regs
->reg_name
);
3383 else if (i
.tm
.opcode_modifier
& Modrm
)
3385 /* The opcode is completed (modulo i.tm.extension_opcode which
3386 must be put into the modrm byte). Now, we make the modrm and
3387 index base bytes based on all the info we've collected. */
3389 default_seg
= build_modrm_byte ();
3391 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
3395 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
3397 /* For the string instructions that allow a segment override
3398 on one of their operands, the default segment is ds. */
3402 if ((i
.tm
.base_opcode
== 0x8d /* lea */
3403 || (i
.tm
.cpu_flags
& CpuSVME
))
3404 && i
.seg
[0] && !quiet_warnings
)
3405 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
3407 /* If a segment was explicitly specified, and the specified segment
3408 is not the default, use an opcode prefix to select it. If we
3409 never figured out what the default segment is, then default_seg
3410 will be zero at this point, and the specified segment prefix will
3412 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
3414 if (!add_prefix (i
.seg
[0]->seg_prefix
))
3420 static const seg_entry
*
3421 build_modrm_byte (void)
3423 const seg_entry
*default_seg
= 0;
3425 /* i.reg_operands MUST be the number of real register operands;
3426 implicit registers do not count. */
3427 if (i
.reg_operands
== 2)
3429 unsigned int source
, dest
;
3437 /* When there are 3 operands, one of them may be immediate,
3438 which may be the first or the last operand. Otherwise,
3439 the first operand must be shift count register (cl). */
3440 assert (i
.imm_operands
== 1
3441 || (i
.imm_operands
== 0
3442 && (i
.types
[0] & ShiftCount
)));
3443 source
= (i
.types
[0] & (Imm
| ShiftCount
)) ? 1 : 0;
3446 /* When there are 4 operands, the first two must be immediate
3447 operands. The source operand will be the 3rd one. */
3448 assert (i
.imm_operands
== 2
3449 && (i
.types
[0] & Imm
)
3450 && (i
.types
[1] & Imm
));
3460 /* One of the register operands will be encoded in the i.tm.reg
3461 field, the other in the combined i.tm.mode and i.tm.regmem
3462 fields. If no form of this instruction supports a memory
3463 destination operand, then we assume the source operand may
3464 sometimes be a memory operand and so we need to store the
3465 destination in the i.rm.reg field. */
3466 if ((i
.tm
.operand_types
[dest
] & (AnyMem
| RegMem
)) == 0)
3468 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
3469 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
3470 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
3472 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
3477 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
3478 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
3479 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
3481 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
3484 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
3486 if (!((i
.types
[0] | i
.types
[1]) & Control
))
3488 i
.rex
&= ~(REX_R
| REX_B
);
3489 add_prefix (LOCK_PREFIX_OPCODE
);
3493 { /* If it's not 2 reg operands... */
3496 unsigned int fake_zero_displacement
= 0;
3499 for (op
= 0; op
< i
.operands
; op
++)
3500 if ((i
.types
[op
] & AnyMem
))
3502 assert (op
< i
.operands
);
3506 if (i
.base_reg
== 0)
3509 if (!i
.disp_operands
)
3510 fake_zero_displacement
= 1;
3511 if (i
.index_reg
== 0)
3513 /* Operand is just <disp> */
3514 if (flag_code
== CODE_64BIT
)
3516 /* 64bit mode overwrites the 32bit absolute
3517 addressing by RIP relative addressing and
3518 absolute addressing is encoded by one of the
3519 redundant SIB forms. */
3520 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3521 i
.sib
.base
= NO_BASE_REGISTER
;
3522 i
.sib
.index
= NO_INDEX_REGISTER
;
3523 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
3524 ? Disp32S
: Disp32
);
3526 else if ((flag_code
== CODE_16BIT
)
3527 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3529 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
3530 i
.types
[op
] = Disp16
;
3534 i
.rm
.regmem
= NO_BASE_REGISTER
;
3535 i
.types
[op
] = Disp32
;
3538 else /* !i.base_reg && i.index_reg */
3540 i
.sib
.index
= i
.index_reg
->reg_num
;
3541 i
.sib
.base
= NO_BASE_REGISTER
;
3542 i
.sib
.scale
= i
.log2_scale_factor
;
3543 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3544 i
.types
[op
] &= ~Disp
;
3545 if (flag_code
!= CODE_64BIT
)
3546 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
3548 i
.types
[op
] |= Disp32S
;
3549 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3553 /* RIP addressing for 64bit mode. */
3554 else if (i
.base_reg
->reg_type
== BaseIndex
)
3556 i
.rm
.regmem
= NO_BASE_REGISTER
;
3557 i
.types
[op
] &= ~ Disp
;
3558 i
.types
[op
] |= Disp32S
;
3559 i
.flags
[op
] |= Operand_PCrel
;
3560 if (! i
.disp_operands
)
3561 fake_zero_displacement
= 1;
3563 else if (i
.base_reg
->reg_type
& Reg16
)
3565 switch (i
.base_reg
->reg_num
)
3568 if (i
.index_reg
== 0)
3570 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3571 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
3575 if (i
.index_reg
== 0)
3578 if ((i
.types
[op
] & Disp
) == 0)
3580 /* fake (%bp) into 0(%bp) */
3581 i
.types
[op
] |= Disp8
;
3582 fake_zero_displacement
= 1;
3585 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3586 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
3588 default: /* (%si) -> 4 or (%di) -> 5 */
3589 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
3591 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3593 else /* i.base_reg and 32/64 bit mode */
3595 if (flag_code
== CODE_64BIT
3596 && (i
.types
[op
] & Disp
))
3597 i
.types
[op
] = ((i
.types
[op
] & Disp8
)
3598 | (i
.prefix
[ADDR_PREFIX
] == 0
3599 ? Disp32S
: Disp32
));
3601 i
.rm
.regmem
= i
.base_reg
->reg_num
;
3602 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
3604 i
.sib
.base
= i
.base_reg
->reg_num
;
3605 /* x86-64 ignores REX prefix bit here to avoid decoder
3607 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
3610 if (i
.disp_operands
== 0)
3612 fake_zero_displacement
= 1;
3613 i
.types
[op
] |= Disp8
;
3616 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
3620 i
.sib
.scale
= i
.log2_scale_factor
;
3621 if (i
.index_reg
== 0)
3623 /* <disp>(%esp) becomes two byte modrm with no index
3624 register. We've already stored the code for esp
3625 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3626 Any base register besides %esp will not use the
3627 extra modrm byte. */
3628 i
.sib
.index
= NO_INDEX_REGISTER
;
3629 #if !SCALE1_WHEN_NO_INDEX
3630 /* Another case where we force the second modrm byte. */
3631 if (i
.log2_scale_factor
)
3632 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3637 i
.sib
.index
= i
.index_reg
->reg_num
;
3638 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3639 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3644 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3645 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
3648 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3651 if (fake_zero_displacement
)
3653 /* Fakes a zero displacement assuming that i.types[op]
3654 holds the correct displacement size. */
3657 assert (i
.op
[op
].disps
== 0);
3658 exp
= &disp_expressions
[i
.disp_operands
++];
3659 i
.op
[op
].disps
= exp
;
3660 exp
->X_op
= O_constant
;
3661 exp
->X_add_number
= 0;
3662 exp
->X_add_symbol
= (symbolS
*) 0;
3663 exp
->X_op_symbol
= (symbolS
*) 0;
3667 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3668 (if any) based on i.tm.extension_opcode. Again, we must be
3669 careful to make sure that segment/control/debug/test/MMX
3670 registers are coded into the i.rm.reg field. */
3675 for (op
= 0; op
< i
.operands
; op
++)
3676 if ((i
.types
[op
] & (Reg
| RegMMX
| RegXMM
3678 | Control
| Debug
| Test
)))
3680 assert (op
< i
.operands
);
3682 /* If there is an extension opcode to put here, the register
3683 number must be put into the regmem field. */
3684 if (i
.tm
.extension_opcode
!= None
)
3686 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
3687 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3692 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
3693 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3697 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3698 must set it to 3 to indicate this is a register operand
3699 in the regmem field. */
3700 if (!i
.mem_operands
)
3704 /* Fill in i.rm.reg field with extension opcode (if any). */
3705 if (i
.tm
.extension_opcode
!= None
)
3706 i
.rm
.reg
= i
.tm
.extension_opcode
;
3712 output_branch (void)
3717 relax_substateT subtype
;
3722 if (flag_code
== CODE_16BIT
)
3726 if (i
.prefix
[DATA_PREFIX
] != 0)
3732 /* Pentium4 branch hints. */
3733 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3734 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3739 if (i
.prefix
[REX_PREFIX
] != 0)
3745 if (i
.prefixes
!= 0 && !intel_syntax
)
3746 as_warn (_("skipping prefixes on this instruction"));
3748 /* It's always a symbol; End frag & setup for relax.
3749 Make sure there is enough room in this frag for the largest
3750 instruction we may generate in md_convert_frag. This is 2
3751 bytes for the opcode and room for the prefix and largest
3753 frag_grow (prefix
+ 2 + 4);
3754 /* Prefix and 1 opcode byte go in fr_fix. */
3755 p
= frag_more (prefix
+ 1);
3756 if (i
.prefix
[DATA_PREFIX
] != 0)
3757 *p
++ = DATA_PREFIX_OPCODE
;
3758 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
3759 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
3760 *p
++ = i
.prefix
[SEG_PREFIX
];
3761 if (i
.prefix
[REX_PREFIX
] != 0)
3762 *p
++ = i
.prefix
[REX_PREFIX
];
3763 *p
= i
.tm
.base_opcode
;
3765 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
3766 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
3767 else if ((cpu_arch_flags
& Cpu386
) != 0)
3768 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
3770 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
3773 sym
= i
.op
[0].disps
->X_add_symbol
;
3774 off
= i
.op
[0].disps
->X_add_number
;
3776 if (i
.op
[0].disps
->X_op
!= O_constant
3777 && i
.op
[0].disps
->X_op
!= O_symbol
)
3779 /* Handle complex expressions. */
3780 sym
= make_expr_symbol (i
.op
[0].disps
);
3784 /* 1 possible extra opcode + 4 byte displacement go in var part.
3785 Pass reloc in fr_var. */
3786 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
3796 if (i
.tm
.opcode_modifier
& JumpByte
)
3798 /* This is a loop or jecxz type instruction. */
3800 if (i
.prefix
[ADDR_PREFIX
] != 0)
3802 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3805 /* Pentium4 branch hints. */
3806 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3807 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3809 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3818 if (flag_code
== CODE_16BIT
)
3821 if (i
.prefix
[DATA_PREFIX
] != 0)
3823 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3833 if (i
.prefix
[REX_PREFIX
] != 0)
3835 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3839 if (i
.prefixes
!= 0 && !intel_syntax
)
3840 as_warn (_("skipping prefixes on this instruction"));
3842 p
= frag_more (1 + size
);
3843 *p
++ = i
.tm
.base_opcode
;
3845 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3846 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3848 /* All jumps handled here are signed, but don't use a signed limit
3849 check for 32 and 16 bit jumps as we want to allow wrap around at
3850 4G and 64k respectively. */
3852 fixP
->fx_signed
= 1;
3856 output_interseg_jump (void)
3864 if (flag_code
== CODE_16BIT
)
3868 if (i
.prefix
[DATA_PREFIX
] != 0)
3874 if (i
.prefix
[REX_PREFIX
] != 0)
3884 if (i
.prefixes
!= 0 && !intel_syntax
)
3885 as_warn (_("skipping prefixes on this instruction"));
3887 /* 1 opcode; 2 segment; offset */
3888 p
= frag_more (prefix
+ 1 + 2 + size
);
3890 if (i
.prefix
[DATA_PREFIX
] != 0)
3891 *p
++ = DATA_PREFIX_OPCODE
;
3893 if (i
.prefix
[REX_PREFIX
] != 0)
3894 *p
++ = i
.prefix
[REX_PREFIX
];
3896 *p
++ = i
.tm
.base_opcode
;
3897 if (i
.op
[1].imms
->X_op
== O_constant
)
3899 offsetT n
= i
.op
[1].imms
->X_add_number
;
3902 && !fits_in_unsigned_word (n
)
3903 && !fits_in_signed_word (n
))
3905 as_bad (_("16-bit jump out of range"));
3908 md_number_to_chars (p
, n
, size
);
3911 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3912 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3913 if (i
.op
[0].imms
->X_op
!= O_constant
)
3914 as_bad (_("can't handle non absolute segment in `%s'"),
3916 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3922 fragS
*insn_start_frag
;
3923 offsetT insn_start_off
;
3925 /* Tie dwarf2 debug info to the address at the start of the insn.
3926 We can't do this after the insn has been output as the current
3927 frag may have been closed off. eg. by frag_var. */
3928 dwarf2_emit_insn (0);
3930 insn_start_frag
= frag_now
;
3931 insn_start_off
= frag_now_fix ();
3934 if (i
.tm
.opcode_modifier
& Jump
)
3936 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3938 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3939 output_interseg_jump ();
3942 /* Output normal instructions here. */
3945 unsigned int prefix
;
3947 /* All opcodes on i386 have either 1 or 2 bytes. SSSE3 and
3948 SSE4 instructions have 3 bytes. We may use one more higher
3949 byte to specify a prefix the instruction requires. Exclude
3950 instructions which are in both SSE4 and ABM. */
3951 if ((i
.tm
.cpu_flags
& (CpuSSSE3
| CpuSSE4
)) != 0
3952 && (i
.tm
.cpu_flags
& CpuABM
) == 0)
3954 if (i
.tm
.base_opcode
& 0xff000000)
3956 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
3960 else if ((i
.tm
.base_opcode
& 0xff0000) != 0)
3962 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
3963 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0)
3966 if (prefix
!= REPE_PREFIX_OPCODE
3967 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
3968 add_prefix (prefix
);
3971 add_prefix (prefix
);
3974 /* The prefix bytes. */
3976 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3982 md_number_to_chars (p
, (valueT
) *q
, 1);
3986 /* Now the opcode; be careful about word order here! */
3987 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3989 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3993 if ((i
.tm
.cpu_flags
& (CpuSSSE3
| CpuSSE4
)) != 0
3994 && (i
.tm
.cpu_flags
& CpuABM
) == 0)
3997 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
4002 /* Put out high byte first: can't use md_number_to_chars! */
4003 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
4004 *p
= i
.tm
.base_opcode
& 0xff;
4007 /* Now the modrm byte and sib byte (if present). */
4008 if (i
.tm
.opcode_modifier
& Modrm
)
4011 md_number_to_chars (p
,
4012 (valueT
) (i
.rm
.regmem
<< 0
4016 /* If i.rm.regmem == ESP (4)
4017 && i.rm.mode != (Register mode)
4019 ==> need second modrm byte. */
4020 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
4022 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
4025 md_number_to_chars (p
,
4026 (valueT
) (i
.sib
.base
<< 0
4028 | i
.sib
.scale
<< 6),
4033 if (i
.disp_operands
)
4034 output_disp (insn_start_frag
, insn_start_off
);
4037 output_imm (insn_start_frag
, insn_start_off
);
4043 pi ("" /*line*/, &i
);
4045 #endif /* DEBUG386 */
4049 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
4054 for (n
= 0; n
< i
.operands
; n
++)
4056 if (i
.types
[n
] & Disp
)
4058 if (i
.op
[n
].disps
->X_op
== O_constant
)
4064 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
4067 if (i
.types
[n
] & Disp8
)
4069 if (i
.types
[n
] & Disp64
)
4072 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
4074 p
= frag_more (size
);
4075 md_number_to_chars (p
, val
, size
);
4079 enum bfd_reloc_code_real reloc_type
;
4082 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
4084 /* The PC relative address is computed relative
4085 to the instruction boundary, so in case immediate
4086 fields follows, we need to adjust the value. */
4087 if (pcrel
&& i
.imm_operands
)
4092 for (n1
= 0; n1
< i
.operands
; n1
++)
4093 if (i
.types
[n1
] & Imm
)
4095 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
4098 if (i
.types
[n1
] & (Imm8
| Imm8S
))
4100 if (i
.types
[n1
] & Imm64
)
4105 /* We should find the immediate. */
4106 if (n1
== i
.operands
)
4108 i
.op
[n
].disps
->X_add_number
-= imm_size
;
4111 if (i
.types
[n
] & Disp32S
)
4114 if (i
.types
[n
] & (Disp16
| Disp64
))
4117 if (i
.types
[n
] & Disp64
)
4121 p
= frag_more (size
);
4122 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
4124 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
4125 && (((reloc_type
== BFD_RELOC_32
4126 || reloc_type
== BFD_RELOC_X86_64_32S
4127 || (reloc_type
== BFD_RELOC_64
4129 && (i
.op
[n
].disps
->X_op
== O_symbol
4130 || (i
.op
[n
].disps
->X_op
== O_add
4131 && ((symbol_get_value_expression
4132 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
4134 || reloc_type
== BFD_RELOC_32_PCREL
))
4138 if (insn_start_frag
== frag_now
)
4139 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
4144 add
= insn_start_frag
->fr_fix
- insn_start_off
;
4145 for (fr
= insn_start_frag
->fr_next
;
4146 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
4148 add
+= p
- frag_now
->fr_literal
;
4153 reloc_type
= BFD_RELOC_386_GOTPC
;
4154 i
.op
[n
].imms
->X_add_number
+= add
;
4156 else if (reloc_type
== BFD_RELOC_64
)
4157 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
4159 /* Don't do the adjustment for x86-64, as there
4160 the pcrel addressing is relative to the _next_
4161 insn, and that is taken care of in other code. */
4162 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
4164 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4165 i
.op
[n
].disps
, pcrel
, reloc_type
);
4172 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
4177 for (n
= 0; n
< i
.operands
; n
++)
4179 if (i
.types
[n
] & Imm
)
4181 if (i
.op
[n
].imms
->X_op
== O_constant
)
4187 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
4190 if (i
.types
[n
] & (Imm8
| Imm8S
))
4192 else if (i
.types
[n
] & Imm64
)
4195 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
4197 p
= frag_more (size
);
4198 md_number_to_chars (p
, val
, size
);
4202 /* Not absolute_section.
4203 Need a 32-bit fixup (don't support 8bit
4204 non-absolute imms). Try to support other
4206 enum bfd_reloc_code_real reloc_type
;
4210 if ((i
.types
[n
] & (Imm32S
))
4211 && (i
.suffix
== QWORD_MNEM_SUFFIX
4212 || (!i
.suffix
&& (i
.tm
.opcode_modifier
& No_lSuf
))))
4214 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
4217 if (i
.types
[n
] & (Imm8
| Imm8S
))
4219 if (i
.types
[n
] & Imm64
)
4223 p
= frag_more (size
);
4224 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
4226 /* This is tough to explain. We end up with this one if we
4227 * have operands that look like
4228 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4229 * obtain the absolute address of the GOT, and it is strongly
4230 * preferable from a performance point of view to avoid using
4231 * a runtime relocation for this. The actual sequence of
4232 * instructions often look something like:
4237 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4239 * The call and pop essentially return the absolute address
4240 * of the label .L66 and store it in %ebx. The linker itself
4241 * will ultimately change the first operand of the addl so
4242 * that %ebx points to the GOT, but to keep things simple, the
4243 * .o file must have this operand set so that it generates not
4244 * the absolute address of .L66, but the absolute address of
4245 * itself. This allows the linker itself simply treat a GOTPC
4246 * relocation as asking for a pcrel offset to the GOT to be
4247 * added in, and the addend of the relocation is stored in the
4248 * operand field for the instruction itself.
4250 * Our job here is to fix the operand so that it would add
4251 * the correct offset so that %ebx would point to itself. The
4252 * thing that is tricky is that .-.L66 will point to the
4253 * beginning of the instruction, so we need to further modify
4254 * the operand so that it will point to itself. There are
4255 * other cases where you have something like:
4257 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4259 * and here no correction would be required. Internally in
4260 * the assembler we treat operands of this form as not being
4261 * pcrel since the '.' is explicitly mentioned, and I wonder
4262 * whether it would simplify matters to do it this way. Who
4263 * knows. In earlier versions of the PIC patches, the
4264 * pcrel_adjust field was used to store the correction, but
4265 * since the expression is not pcrel, I felt it would be
4266 * confusing to do it this way. */
4268 if ((reloc_type
== BFD_RELOC_32
4269 || reloc_type
== BFD_RELOC_X86_64_32S
4270 || reloc_type
== BFD_RELOC_64
)
4272 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
4273 && (i
.op
[n
].imms
->X_op
== O_symbol
4274 || (i
.op
[n
].imms
->X_op
== O_add
4275 && ((symbol_get_value_expression
4276 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
4281 if (insn_start_frag
== frag_now
)
4282 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
4287 add
= insn_start_frag
->fr_fix
- insn_start_off
;
4288 for (fr
= insn_start_frag
->fr_next
;
4289 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
4291 add
+= p
- frag_now
->fr_literal
;
4295 reloc_type
= BFD_RELOC_386_GOTPC
;
4297 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
4299 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
4300 i
.op
[n
].imms
->X_add_number
+= add
;
4302 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4303 i
.op
[n
].imms
, 0, reloc_type
);
4309 /* x86_cons_fix_new is called via the expression parsing code when a
4310 reloc is needed. We use this hook to get the correct .got reloc. */
4311 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
4312 static int cons_sign
= -1;
4315 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
4318 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
4320 got_reloc
= NO_RELOC
;
4323 if (exp
->X_op
== O_secrel
)
4325 exp
->X_op
= O_symbol
;
4326 r
= BFD_RELOC_32_SECREL
;
4330 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
4333 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4334 # define lex_got(reloc, adjust, types) NULL
4336 /* Parse operands of the form
4337 <symbol>@GOTOFF+<nnn>
4338 and similar .plt or .got references.
4340 If we find one, set up the correct relocation in RELOC and copy the
4341 input string, minus the `@GOTOFF' into a malloc'd buffer for
4342 parsing by the calling routine. Return this buffer, and if ADJUST
4343 is non-null set it to the length of the string we removed from the
4344 input line. Otherwise return NULL. */
4346 lex_got (enum bfd_reloc_code_real
*reloc
,
4348 unsigned int *types
)
4350 /* Some of the relocations depend on the size of what field is to
4351 be relocated. But in our callers i386_immediate and i386_displacement
4352 we don't yet know the operand size (this will be set by insn
4353 matching). Hence we record the word32 relocation here,
4354 and adjust the reloc according to the real size in reloc(). */
4355 static const struct {
4357 const enum bfd_reloc_code_real rel
[2];
4358 const unsigned int types64
;
4361 BFD_RELOC_X86_64_PLTOFF64
},
4363 { "PLT", { BFD_RELOC_386_PLT32
,
4364 BFD_RELOC_X86_64_PLT32
},
4365 Imm32
| Imm32S
| Disp32
},
4367 BFD_RELOC_X86_64_GOTPLT64
},
4369 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
4370 BFD_RELOC_X86_64_GOTOFF64
},
4373 BFD_RELOC_X86_64_GOTPCREL
},
4374 Imm32
| Imm32S
| Disp32
},
4375 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
4376 BFD_RELOC_X86_64_TLSGD
},
4377 Imm32
| Imm32S
| Disp32
},
4378 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
4382 BFD_RELOC_X86_64_TLSLD
},
4383 Imm32
| Imm32S
| Disp32
},
4384 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
4385 BFD_RELOC_X86_64_GOTTPOFF
},
4386 Imm32
| Imm32S
| Disp32
},
4387 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
4388 BFD_RELOC_X86_64_TPOFF32
},
4389 Imm32
| Imm32S
| Imm64
| Disp32
| Disp64
},
4390 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
4393 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
4394 BFD_RELOC_X86_64_DTPOFF32
},
4395 Imm32
| Imm32S
| Imm64
| Disp32
| Disp64
},
4396 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
4399 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
4402 { "GOT", { BFD_RELOC_386_GOT32
,
4403 BFD_RELOC_X86_64_GOT32
},
4404 Imm32
| Imm32S
| Disp32
| Imm64
},
4405 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
4406 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
4407 Imm32
| Imm32S
| Disp32
},
4408 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
4409 BFD_RELOC_X86_64_TLSDESC_CALL
},
4410 Imm32
| Imm32S
| Disp32
}
4418 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
4419 if (is_end_of_line
[(unsigned char) *cp
])
4422 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
4426 len
= strlen (gotrel
[j
].str
);
4427 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
4429 if (gotrel
[j
].rel
[object_64bit
] != 0)
4432 char *tmpbuf
, *past_reloc
;
4434 *reloc
= gotrel
[j
].rel
[object_64bit
];
4440 if (flag_code
!= CODE_64BIT
)
4441 *types
= Imm32
| Disp32
;
4443 *types
= gotrel
[j
].types64
;
4446 if (GOT_symbol
== NULL
)
4447 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
4449 /* Replace the relocation token with ' ', so that
4450 errors like foo@GOTOFF1 will be detected. */
4452 /* The length of the first part of our input line. */
4453 first
= cp
- input_line_pointer
;
4455 /* The second part goes from after the reloc token until
4456 (and including) an end_of_line char. Don't use strlen
4457 here as the end_of_line char may not be a NUL. */
4458 past_reloc
= cp
+ 1 + len
;
4459 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
4461 second
= cp
- past_reloc
;
4463 /* Allocate and copy string. The trailing NUL shouldn't
4464 be necessary, but be safe. */
4465 tmpbuf
= xmalloc (first
+ second
+ 2);
4466 memcpy (tmpbuf
, input_line_pointer
, first
);
4467 tmpbuf
[first
] = ' ';
4468 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
4469 tmpbuf
[first
+ second
+ 1] = '\0';
4473 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4474 gotrel
[j
].str
, 1 << (5 + object_64bit
));
4479 /* Might be a symbol version string. Don't as_bad here. */
4484 x86_cons (expressionS
*exp
, int size
)
4486 if (size
== 4 || (object_64bit
&& size
== 8))
4488 /* Handle @GOTOFF and the like in an expression. */
4490 char *gotfree_input_line
;
4493 save
= input_line_pointer
;
4494 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
4495 if (gotfree_input_line
)
4496 input_line_pointer
= gotfree_input_line
;
4500 if (gotfree_input_line
)
4502 /* expression () has merrily parsed up to the end of line,
4503 or a comma - in the wrong buffer. Transfer how far
4504 input_line_pointer has moved to the right buffer. */
4505 input_line_pointer
= (save
4506 + (input_line_pointer
- gotfree_input_line
)
4508 free (gotfree_input_line
);
4516 static void signed_cons (int size
)
4518 if (flag_code
== CODE_64BIT
)
4526 pe_directive_secrel (dummy
)
4527 int dummy ATTRIBUTE_UNUSED
;
4534 if (exp
.X_op
== O_symbol
)
4535 exp
.X_op
= O_secrel
;
4537 emit_expr (&exp
, 4);
4539 while (*input_line_pointer
++ == ',');
4541 input_line_pointer
--;
4542 demand_empty_rest_of_line ();
4547 i386_immediate (char *imm_start
)
4549 char *save_input_line_pointer
;
4550 char *gotfree_input_line
;
4553 unsigned int types
= ~0U;
4555 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
4557 as_bad (_("at most %d immediate operands are allowed"),
4558 MAX_IMMEDIATE_OPERANDS
);
4562 exp
= &im_expressions
[i
.imm_operands
++];
4563 i
.op
[this_operand
].imms
= exp
;
4565 if (is_space_char (*imm_start
))
4568 save_input_line_pointer
= input_line_pointer
;
4569 input_line_pointer
= imm_start
;
4571 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4572 if (gotfree_input_line
)
4573 input_line_pointer
= gotfree_input_line
;
4575 exp_seg
= expression (exp
);
4578 if (*input_line_pointer
)
4579 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4581 input_line_pointer
= save_input_line_pointer
;
4582 if (gotfree_input_line
)
4583 free (gotfree_input_line
);
4585 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4587 /* Missing or bad expr becomes absolute 0. */
4588 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
4590 exp
->X_op
= O_constant
;
4591 exp
->X_add_number
= 0;
4592 exp
->X_add_symbol
= (symbolS
*) 0;
4593 exp
->X_op_symbol
= (symbolS
*) 0;
4595 else if (exp
->X_op
== O_constant
)
4597 /* Size it properly later. */
4598 i
.types
[this_operand
] |= Imm64
;
4599 /* If BFD64, sign extend val. */
4600 if (!use_rela_relocations
4601 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
4603 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
4605 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4606 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
4607 && exp_seg
!= absolute_section
4608 && exp_seg
!= text_section
4609 && exp_seg
!= data_section
4610 && exp_seg
!= bss_section
4611 && exp_seg
!= undefined_section
4612 && !bfd_is_com_section (exp_seg
))
4614 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4618 else if (!intel_syntax
&& exp
->X_op
== O_register
)
4620 as_bad (_("illegal immediate register operand %s"), imm_start
);
4625 /* This is an address. The size of the address will be
4626 determined later, depending on destination register,
4627 suffix, or the default for the section. */
4628 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
4629 i
.types
[this_operand
] &= types
;
4636 i386_scale (char *scale
)
4639 char *save
= input_line_pointer
;
4641 input_line_pointer
= scale
;
4642 val
= get_absolute_expression ();
4647 i
.log2_scale_factor
= 0;
4650 i
.log2_scale_factor
= 1;
4653 i
.log2_scale_factor
= 2;
4656 i
.log2_scale_factor
= 3;
4660 char sep
= *input_line_pointer
;
4662 *input_line_pointer
= '\0';
4663 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4665 *input_line_pointer
= sep
;
4666 input_line_pointer
= save
;
4670 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
4672 as_warn (_("scale factor of %d without an index register"),
4673 1 << i
.log2_scale_factor
);
4674 #if SCALE1_WHEN_NO_INDEX
4675 i
.log2_scale_factor
= 0;
4678 scale
= input_line_pointer
;
4679 input_line_pointer
= save
;
4684 i386_displacement (char *disp_start
, char *disp_end
)
4688 char *save_input_line_pointer
;
4689 char *gotfree_input_line
;
4690 int bigdisp
, override
;
4691 unsigned int types
= Disp
;
4693 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
4695 as_bad (_("at most %d displacement operands are allowed"),
4696 MAX_MEMORY_OPERANDS
);
4700 if ((i
.types
[this_operand
] & JumpAbsolute
)
4701 || !(current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
)))
4704 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
4708 /* For PC-relative branches, the width of the displacement
4709 is dependent upon data size, not address size. */
4711 override
= (i
.prefix
[DATA_PREFIX
] != 0);
4713 if (flag_code
== CODE_64BIT
)
4716 bigdisp
= ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
4718 : Disp32S
| Disp32
);
4720 bigdisp
= Disp64
| Disp32S
| Disp32
;
4727 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
4729 : LONG_MNEM_SUFFIX
));
4732 if ((flag_code
== CODE_16BIT
) ^ override
)
4735 i
.types
[this_operand
] |= bigdisp
;
4737 exp
= &disp_expressions
[i
.disp_operands
];
4738 i
.op
[this_operand
].disps
= exp
;
4740 save_input_line_pointer
= input_line_pointer
;
4741 input_line_pointer
= disp_start
;
4742 END_STRING_AND_SAVE (disp_end
);
4744 #ifndef GCC_ASM_O_HACK
4745 #define GCC_ASM_O_HACK 0
4748 END_STRING_AND_SAVE (disp_end
+ 1);
4749 if ((i
.types
[this_operand
] & BaseIndex
) != 0
4750 && displacement_string_end
[-1] == '+')
4752 /* This hack is to avoid a warning when using the "o"
4753 constraint within gcc asm statements.
4756 #define _set_tssldt_desc(n,addr,limit,type) \
4757 __asm__ __volatile__ ( \
4759 "movw %w1,2+%0\n\t" \
4761 "movb %b1,4+%0\n\t" \
4762 "movb %4,5+%0\n\t" \
4763 "movb $0,6+%0\n\t" \
4764 "movb %h1,7+%0\n\t" \
4766 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4768 This works great except that the output assembler ends
4769 up looking a bit weird if it turns out that there is
4770 no offset. You end up producing code that looks like:
4783 So here we provide the missing zero. */
4785 *displacement_string_end
= '0';
4788 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4789 if (gotfree_input_line
)
4790 input_line_pointer
= gotfree_input_line
;
4792 exp_seg
= expression (exp
);
4795 if (*input_line_pointer
)
4796 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4798 RESTORE_END_STRING (disp_end
+ 1);
4800 RESTORE_END_STRING (disp_end
);
4801 input_line_pointer
= save_input_line_pointer
;
4802 if (gotfree_input_line
)
4803 free (gotfree_input_line
);
4805 /* We do this to make sure that the section symbol is in
4806 the symbol table. We will ultimately change the relocation
4807 to be relative to the beginning of the section. */
4808 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
4809 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4810 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4812 if (exp
->X_op
!= O_symbol
)
4814 as_bad (_("bad expression used with @%s"),
4815 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4821 if (S_IS_LOCAL (exp
->X_add_symbol
)
4822 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
4823 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
4824 exp
->X_op
= O_subtract
;
4825 exp
->X_op_symbol
= GOT_symbol
;
4826 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
4827 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
4828 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4829 i
.reloc
[this_operand
] = BFD_RELOC_64
;
4831 i
.reloc
[this_operand
] = BFD_RELOC_32
;
4834 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4836 /* Missing or bad expr becomes absolute 0. */
4837 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4839 exp
->X_op
= O_constant
;
4840 exp
->X_add_number
= 0;
4841 exp
->X_add_symbol
= (symbolS
*) 0;
4842 exp
->X_op_symbol
= (symbolS
*) 0;
4845 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4846 if (exp
->X_op
!= O_constant
4847 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
4848 && exp_seg
!= absolute_section
4849 && exp_seg
!= text_section
4850 && exp_seg
!= data_section
4851 && exp_seg
!= bss_section
4852 && exp_seg
!= undefined_section
4853 && !bfd_is_com_section (exp_seg
))
4855 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4860 if (!(i
.types
[this_operand
] & ~Disp
))
4861 i
.types
[this_operand
] &= types
;
4866 /* Make sure the memory operand we've been dealt is valid.
4867 Return 1 on success, 0 on a failure. */
4870 i386_index_check (const char *operand_string
)
4873 #if INFER_ADDR_PREFIX
4879 if ((current_templates
->start
->cpu_flags
& CpuSVME
)
4880 && current_templates
->end
[-1].operand_types
[0] == AnyMem
)
4882 /* Memory operands of SVME insns are special in that they only allow
4883 rAX as their memory address and ignore any segment override. */
4886 /* SKINIT is even more restrictive: it always requires EAX. */
4887 if (strcmp (current_templates
->start
->name
, "skinit") == 0)
4889 else if (flag_code
== CODE_64BIT
)
4890 RegXX
= i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
;
4892 RegXX
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0)
4896 || !(i
.base_reg
->reg_type
& Acc
)
4897 || !(i
.base_reg
->reg_type
& RegXX
)
4899 || (i
.types
[0] & Disp
))
4902 else if (flag_code
== CODE_64BIT
)
4904 unsigned RegXX
= (i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
);
4907 && ((i
.base_reg
->reg_type
& RegXX
) == 0)
4908 && (i
.base_reg
->reg_type
!= BaseIndex
4911 && ((i
.index_reg
->reg_type
& (RegXX
| BaseIndex
))
4912 != (RegXX
| BaseIndex
))))
4917 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4921 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
4922 != (Reg16
| BaseIndex
)))
4924 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
4925 != (Reg16
| BaseIndex
))
4927 && i
.base_reg
->reg_num
< 6
4928 && i
.index_reg
->reg_num
>= 6
4929 && i
.log2_scale_factor
== 0))))
4936 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
4938 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
4939 != (Reg32
| BaseIndex
))))
4945 #if INFER_ADDR_PREFIX
4946 if (i
.prefix
[ADDR_PREFIX
] == 0)
4948 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
4950 /* Change the size of any displacement too. At most one of
4951 Disp16 or Disp32 is set.
4952 FIXME. There doesn't seem to be any real need for separate
4953 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4954 Removing them would probably clean up the code quite a lot. */
4955 if (flag_code
!= CODE_64BIT
4956 && (i
.types
[this_operand
] & (Disp16
| Disp32
)))
4957 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
4962 as_bad (_("`%s' is not a valid base/index expression"),
4966 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4968 flag_code_names
[flag_code
]);
4973 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4977 i386_operand (char *operand_string
)
4981 char *op_string
= operand_string
;
4983 if (is_space_char (*op_string
))
4986 /* We check for an absolute prefix (differentiating,
4987 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4988 if (*op_string
== ABSOLUTE_PREFIX
)
4991 if (is_space_char (*op_string
))
4993 i
.types
[this_operand
] |= JumpAbsolute
;
4996 /* Check if operand is a register. */
4997 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
4999 /* Check for a segment override by searching for ':' after a
5000 segment register. */
5002 if (is_space_char (*op_string
))
5004 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
5009 i
.seg
[i
.mem_operands
] = &es
;
5012 i
.seg
[i
.mem_operands
] = &cs
;
5015 i
.seg
[i
.mem_operands
] = &ss
;
5018 i
.seg
[i
.mem_operands
] = &ds
;
5021 i
.seg
[i
.mem_operands
] = &fs
;
5024 i
.seg
[i
.mem_operands
] = &gs
;
5028 /* Skip the ':' and whitespace. */
5030 if (is_space_char (*op_string
))
5033 if (!is_digit_char (*op_string
)
5034 && !is_identifier_char (*op_string
)
5035 && *op_string
!= '('
5036 && *op_string
!= ABSOLUTE_PREFIX
)
5038 as_bad (_("bad memory operand `%s'"), op_string
);
5041 /* Handle case of %es:*foo. */
5042 if (*op_string
== ABSOLUTE_PREFIX
)
5045 if (is_space_char (*op_string
))
5047 i
.types
[this_operand
] |= JumpAbsolute
;
5049 goto do_memory_reference
;
5053 as_bad (_("junk `%s' after register"), op_string
);
5056 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
5057 i
.op
[this_operand
].regs
= r
;
5060 else if (*op_string
== REGISTER_PREFIX
)
5062 as_bad (_("bad register name `%s'"), op_string
);
5065 else if (*op_string
== IMMEDIATE_PREFIX
)
5068 if (i
.types
[this_operand
] & JumpAbsolute
)
5070 as_bad (_("immediate operand illegal with absolute jump"));
5073 if (!i386_immediate (op_string
))
5076 else if (is_digit_char (*op_string
)
5077 || is_identifier_char (*op_string
)
5078 || *op_string
== '(')
5080 /* This is a memory reference of some sort. */
5083 /* Start and end of displacement string expression (if found). */
5084 char *displacement_string_start
;
5085 char *displacement_string_end
;
5087 do_memory_reference
:
5088 if ((i
.mem_operands
== 1
5089 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5090 || i
.mem_operands
== 2)
5092 as_bad (_("too many memory references for `%s'"),
5093 current_templates
->start
->name
);
5097 /* Check for base index form. We detect the base index form by
5098 looking for an ')' at the end of the operand, searching
5099 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5101 base_string
= op_string
+ strlen (op_string
);
5104 if (is_space_char (*base_string
))
5107 /* If we only have a displacement, set-up for it to be parsed later. */
5108 displacement_string_start
= op_string
;
5109 displacement_string_end
= base_string
+ 1;
5111 if (*base_string
== ')')
5114 unsigned int parens_balanced
= 1;
5115 /* We've already checked that the number of left & right ()'s are
5116 equal, so this loop will not be infinite. */
5120 if (*base_string
== ')')
5122 if (*base_string
== '(')
5125 while (parens_balanced
);
5127 temp_string
= base_string
;
5129 /* Skip past '(' and whitespace. */
5131 if (is_space_char (*base_string
))
5134 if (*base_string
== ','
5135 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
5138 displacement_string_end
= temp_string
;
5140 i
.types
[this_operand
] |= BaseIndex
;
5144 base_string
= end_op
;
5145 if (is_space_char (*base_string
))
5149 /* There may be an index reg or scale factor here. */
5150 if (*base_string
== ',')
5153 if (is_space_char (*base_string
))
5156 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
5159 base_string
= end_op
;
5160 if (is_space_char (*base_string
))
5162 if (*base_string
== ',')
5165 if (is_space_char (*base_string
))
5168 else if (*base_string
!= ')')
5170 as_bad (_("expecting `,' or `)' "
5171 "after index register in `%s'"),
5176 else if (*base_string
== REGISTER_PREFIX
)
5178 as_bad (_("bad register name `%s'"), base_string
);
5182 /* Check for scale factor. */
5183 if (*base_string
!= ')')
5185 char *end_scale
= i386_scale (base_string
);
5190 base_string
= end_scale
;
5191 if (is_space_char (*base_string
))
5193 if (*base_string
!= ')')
5195 as_bad (_("expecting `)' "
5196 "after scale factor in `%s'"),
5201 else if (!i
.index_reg
)
5203 as_bad (_("expecting index register or scale factor "
5204 "after `,'; got '%c'"),
5209 else if (*base_string
!= ')')
5211 as_bad (_("expecting `,' or `)' "
5212 "after base register in `%s'"),
5217 else if (*base_string
== REGISTER_PREFIX
)
5219 as_bad (_("bad register name `%s'"), base_string
);
5224 /* If there's an expression beginning the operand, parse it,
5225 assuming displacement_string_start and
5226 displacement_string_end are meaningful. */
5227 if (displacement_string_start
!= displacement_string_end
)
5229 if (!i386_displacement (displacement_string_start
,
5230 displacement_string_end
))
5234 /* Special case for (%dx) while doing input/output op. */
5236 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
5238 && i
.log2_scale_factor
== 0
5239 && i
.seg
[i
.mem_operands
] == 0
5240 && (i
.types
[this_operand
] & Disp
) == 0)
5242 i
.types
[this_operand
] = InOutPortReg
;
5246 if (i386_index_check (operand_string
) == 0)
5252 /* It's not a memory operand; argh! */
5253 as_bad (_("invalid char %s beginning operand %d `%s'"),
5254 output_invalid (*op_string
),
5259 return 1; /* Normal return. */
5262 /* md_estimate_size_before_relax()
5264 Called just before relax() for rs_machine_dependent frags. The x86
5265 assembler uses these frags to handle variable size jump
5268 Any symbol that is now undefined will not become defined.
5269 Return the correct fr_subtype in the frag.
5270 Return the initial "guess for variable size of frag" to caller.
5271 The guess is actually the growth beyond the fixed part. Whatever
5272 we do to grow the fixed or variable part contributes to our
5276 md_estimate_size_before_relax (fragP
, segment
)
5280 /* We've already got fragP->fr_subtype right; all we have to do is
5281 check for un-relaxable symbols. On an ELF system, we can't relax
5282 an externally visible symbol, because it may be overridden by a
5284 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
5285 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5287 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
5288 || S_IS_WEAK (fragP
->fr_symbol
)))
5292 /* Symbol is undefined in this segment, or we need to keep a
5293 reloc so that weak symbols can be overridden. */
5294 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
5295 enum bfd_reloc_code_real reloc_type
;
5296 unsigned char *opcode
;
5299 if (fragP
->fr_var
!= NO_RELOC
)
5300 reloc_type
= fragP
->fr_var
;
5302 reloc_type
= BFD_RELOC_16_PCREL
;
5304 reloc_type
= BFD_RELOC_32_PCREL
;
5306 old_fr_fix
= fragP
->fr_fix
;
5307 opcode
= (unsigned char *) fragP
->fr_opcode
;
5309 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
5312 /* Make jmp (0xeb) a (d)word displacement jump. */
5314 fragP
->fr_fix
+= size
;
5315 fix_new (fragP
, old_fr_fix
, size
,
5317 fragP
->fr_offset
, 1,
5323 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
5325 /* Negate the condition, and branch past an
5326 unconditional jump. */
5329 /* Insert an unconditional jump. */
5331 /* We added two extra opcode bytes, and have a two byte
5333 fragP
->fr_fix
+= 2 + 2;
5334 fix_new (fragP
, old_fr_fix
+ 2, 2,
5336 fragP
->fr_offset
, 1,
5343 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
5348 fixP
= fix_new (fragP
, old_fr_fix
, 1,
5350 fragP
->fr_offset
, 1,
5352 fixP
->fx_signed
= 1;
5356 /* This changes the byte-displacement jump 0x7N
5357 to the (d)word-displacement jump 0x0f,0x8N. */
5358 opcode
[1] = opcode
[0] + 0x10;
5359 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5360 /* We've added an opcode byte. */
5361 fragP
->fr_fix
+= 1 + size
;
5362 fix_new (fragP
, old_fr_fix
+ 1, size
,
5364 fragP
->fr_offset
, 1,
5369 BAD_CASE (fragP
->fr_subtype
);
5373 return fragP
->fr_fix
- old_fr_fix
;
5376 /* Guess size depending on current relax state. Initially the relax
5377 state will correspond to a short jump and we return 1, because
5378 the variable part of the frag (the branch offset) is one byte
5379 long. However, we can relax a section more than once and in that
5380 case we must either set fr_subtype back to the unrelaxed state,
5381 or return the value for the appropriate branch. */
5382 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
5385 /* Called after relax() is finished.
5387 In: Address of frag.
5388 fr_type == rs_machine_dependent.
5389 fr_subtype is what the address relaxed to.
5391 Out: Any fixSs and constants are set up.
5392 Caller will turn frag into a ".space 0". */
5395 md_convert_frag (abfd
, sec
, fragP
)
5396 bfd
*abfd ATTRIBUTE_UNUSED
;
5397 segT sec ATTRIBUTE_UNUSED
;
5400 unsigned char *opcode
;
5401 unsigned char *where_to_put_displacement
= NULL
;
5402 offsetT target_address
;
5403 offsetT opcode_address
;
5404 unsigned int extension
= 0;
5405 offsetT displacement_from_opcode_start
;
5407 opcode
= (unsigned char *) fragP
->fr_opcode
;
5409 /* Address we want to reach in file space. */
5410 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
5412 /* Address opcode resides at in file space. */
5413 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
5415 /* Displacement from opcode start to fill into instruction. */
5416 displacement_from_opcode_start
= target_address
- opcode_address
;
5418 if ((fragP
->fr_subtype
& BIG
) == 0)
5420 /* Don't have to change opcode. */
5421 extension
= 1; /* 1 opcode + 1 displacement */
5422 where_to_put_displacement
= &opcode
[1];
5426 if (no_cond_jump_promotion
5427 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
5428 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
5429 _("long jump required"));
5431 switch (fragP
->fr_subtype
)
5433 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
5434 extension
= 4; /* 1 opcode + 4 displacement */
5436 where_to_put_displacement
= &opcode
[1];
5439 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
5440 extension
= 2; /* 1 opcode + 2 displacement */
5442 where_to_put_displacement
= &opcode
[1];
5445 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
5446 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
5447 extension
= 5; /* 2 opcode + 4 displacement */
5448 opcode
[1] = opcode
[0] + 0x10;
5449 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5450 where_to_put_displacement
= &opcode
[2];
5453 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
5454 extension
= 3; /* 2 opcode + 2 displacement */
5455 opcode
[1] = opcode
[0] + 0x10;
5456 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5457 where_to_put_displacement
= &opcode
[2];
5460 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
5465 where_to_put_displacement
= &opcode
[3];
5469 BAD_CASE (fragP
->fr_subtype
);
5474 /* If size if less then four we are sure that the operand fits,
5475 but if it's 4, then it could be that the displacement is larger
5477 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
5479 && ((addressT
) (displacement_from_opcode_start
- extension
5480 + ((addressT
) 1 << 31))
5481 > (((addressT
) 2 << 31) - 1)))
5483 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5484 _("jump target out of range"));
5485 /* Make us emit 0. */
5486 displacement_from_opcode_start
= extension
;
5488 /* Now put displacement after opcode. */
5489 md_number_to_chars ((char *) where_to_put_displacement
,
5490 (valueT
) (displacement_from_opcode_start
- extension
),
5491 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
5492 fragP
->fr_fix
+= extension
;
5495 /* Size of byte displacement jmp. */
5496 int md_short_jump_size
= 2;
5498 /* Size of dword displacement jmp. */
5499 int md_long_jump_size
= 5;
5502 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5504 addressT from_addr
, to_addr
;
5505 fragS
*frag ATTRIBUTE_UNUSED
;
5506 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
5510 offset
= to_addr
- (from_addr
+ 2);
5511 /* Opcode for byte-disp jump. */
5512 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
5513 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
5517 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5519 addressT from_addr
, to_addr
;
5520 fragS
*frag ATTRIBUTE_UNUSED
;
5521 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
5525 offset
= to_addr
- (from_addr
+ 5);
5526 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
5527 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
5530 /* Apply a fixup (fixS) to segment data, once it has been determined
5531 by our caller that we have all the info we need to fix it up.
5533 On the 386, immediates, displacements, and data pointers are all in
5534 the same (little-endian) format, so we don't need to care about which
5538 md_apply_fix (fixP
, valP
, seg
)
5539 /* The fix we're to put in. */
5541 /* Pointer to the value of the bits. */
5543 /* Segment fix is from. */
5544 segT seg ATTRIBUTE_UNUSED
;
5546 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
5547 valueT value
= *valP
;
5549 #if !defined (TE_Mach)
5552 switch (fixP
->fx_r_type
)
5558 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
5561 case BFD_RELOC_X86_64_32S
:
5562 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
5565 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
5568 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
5573 if (fixP
->fx_addsy
!= NULL
5574 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
5575 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
5576 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
5577 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
5578 && !use_rela_relocations
)
5580 /* This is a hack. There should be a better way to handle this.
5581 This covers for the fact that bfd_install_relocation will
5582 subtract the current location (for partial_inplace, PC relative
5583 relocations); see more below. */
5587 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
5590 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5592 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5595 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
5598 || (symbol_section_p (fixP
->fx_addsy
)
5599 && sym_seg
!= absolute_section
))
5600 && !generic_force_reloc (fixP
))
5602 /* Yes, we add the values in twice. This is because
5603 bfd_install_relocation subtracts them out again. I think
5604 bfd_install_relocation is broken, but I don't dare change
5606 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5610 #if defined (OBJ_COFF) && defined (TE_PE)
5611 /* For some reason, the PE format does not store a
5612 section address offset for a PC relative symbol. */
5613 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
5614 || S_IS_WEAK (fixP
->fx_addsy
))
5615 value
+= md_pcrel_from (fixP
);
5619 /* Fix a few things - the dynamic linker expects certain values here,
5620 and we must not disappoint it. */
5621 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5622 if (IS_ELF
&& fixP
->fx_addsy
)
5623 switch (fixP
->fx_r_type
)
5625 case BFD_RELOC_386_PLT32
:
5626 case BFD_RELOC_X86_64_PLT32
:
5627 /* Make the jump instruction point to the address of the operand. At
5628 runtime we merely add the offset to the actual PLT entry. */
5632 case BFD_RELOC_386_TLS_GD
:
5633 case BFD_RELOC_386_TLS_LDM
:
5634 case BFD_RELOC_386_TLS_IE_32
:
5635 case BFD_RELOC_386_TLS_IE
:
5636 case BFD_RELOC_386_TLS_GOTIE
:
5637 case BFD_RELOC_386_TLS_GOTDESC
:
5638 case BFD_RELOC_X86_64_TLSGD
:
5639 case BFD_RELOC_X86_64_TLSLD
:
5640 case BFD_RELOC_X86_64_GOTTPOFF
:
5641 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
5642 value
= 0; /* Fully resolved at runtime. No addend. */
5644 case BFD_RELOC_386_TLS_LE
:
5645 case BFD_RELOC_386_TLS_LDO_32
:
5646 case BFD_RELOC_386_TLS_LE_32
:
5647 case BFD_RELOC_X86_64_DTPOFF32
:
5648 case BFD_RELOC_X86_64_DTPOFF64
:
5649 case BFD_RELOC_X86_64_TPOFF32
:
5650 case BFD_RELOC_X86_64_TPOFF64
:
5651 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5654 case BFD_RELOC_386_TLS_DESC_CALL
:
5655 case BFD_RELOC_X86_64_TLSDESC_CALL
:
5656 value
= 0; /* Fully resolved at runtime. No addend. */
5657 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5661 case BFD_RELOC_386_GOT32
:
5662 case BFD_RELOC_X86_64_GOT32
:
5663 value
= 0; /* Fully resolved at runtime. No addend. */
5666 case BFD_RELOC_VTABLE_INHERIT
:
5667 case BFD_RELOC_VTABLE_ENTRY
:
5674 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5676 #endif /* !defined (TE_Mach) */
5678 /* Are we finished with this relocation now? */
5679 if (fixP
->fx_addsy
== NULL
)
5681 else if (use_rela_relocations
)
5683 fixP
->fx_no_overflow
= 1;
5684 /* Remember value for tc_gen_reloc. */
5685 fixP
->fx_addnumber
= value
;
5689 md_number_to_chars (p
, value
, fixP
->fx_size
);
5692 #define MAX_LITTLENUMS 6
5694 /* Turn the string pointed to by litP into a floating point constant
5695 of type TYPE, and emit the appropriate bytes. The number of
5696 LITTLENUMS emitted is stored in *SIZEP. An error message is
5697 returned, or NULL on OK. */
5700 md_atof (type
, litP
, sizeP
)
5706 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5707 LITTLENUM_TYPE
*wordP
;
5729 return _("Bad call to md_atof ()");
5731 t
= atof_ieee (input_line_pointer
, type
, words
);
5733 input_line_pointer
= t
;
5735 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
5736 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5737 the bigendian 386. */
5738 for (wordP
= words
+ prec
- 1; prec
--;)
5740 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
5741 litP
+= sizeof (LITTLENUM_TYPE
);
5746 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
5749 output_invalid (int c
)
5752 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
5755 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
5756 "(0x%x)", (unsigned char) c
);
5757 return output_invalid_buf
;
5760 /* REG_STRING starts *before* REGISTER_PREFIX. */
5762 static const reg_entry
*
5763 parse_real_register (char *reg_string
, char **end_op
)
5765 char *s
= reg_string
;
5767 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
5770 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5771 if (*s
== REGISTER_PREFIX
)
5774 if (is_space_char (*s
))
5778 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
5780 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
5781 return (const reg_entry
*) NULL
;
5785 /* For naked regs, make sure that we are not dealing with an identifier.
5786 This prevents confusing an identifier like `eax_var' with register
5788 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
5789 return (const reg_entry
*) NULL
;
5793 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
5795 /* Handle floating point regs, allowing spaces in the (i) part. */
5796 if (r
== i386_regtab
/* %st is first entry of table */)
5798 if (is_space_char (*s
))
5803 if (is_space_char (*s
))
5805 if (*s
>= '0' && *s
<= '7')
5809 if (is_space_char (*s
))
5814 r
= hash_find (reg_hash
, "st(0)");
5819 /* We have "%st(" then garbage. */
5820 return (const reg_entry
*) NULL
;
5825 && ((r
->reg_flags
& (RegRex64
| RegRex
)) | (r
->reg_type
& Reg64
)) != 0
5826 && (r
->reg_type
!= Control
|| !(cpu_arch_flags
& CpuSledgehammer
))
5827 && flag_code
!= CODE_64BIT
)
5828 return (const reg_entry
*) NULL
;
5833 /* REG_STRING starts *before* REGISTER_PREFIX. */
5835 static const reg_entry
*
5836 parse_register (char *reg_string
, char **end_op
)
5840 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5841 r
= parse_real_register (reg_string
, end_op
);
5846 char *save
= input_line_pointer
;
5850 input_line_pointer
= reg_string
;
5851 c
= get_symbol_end ();
5852 symbolP
= symbol_find (reg_string
);
5853 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
5855 const expressionS
*e
= symbol_get_value_expression (symbolP
);
5857 know (e
->X_op
== O_register
);
5858 know (e
->X_add_number
>= 0
5859 && (valueT
) e
->X_add_number
< i386_regtab_size
);
5860 r
= i386_regtab
+ e
->X_add_number
;
5861 *end_op
= input_line_pointer
;
5863 *input_line_pointer
= c
;
5864 input_line_pointer
= save
;
5870 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
5873 char *end
= input_line_pointer
;
5876 r
= parse_register (name
, &input_line_pointer
);
5877 if (r
&& end
<= input_line_pointer
)
5879 *nextcharP
= *input_line_pointer
;
5880 *input_line_pointer
= 0;
5881 e
->X_op
= O_register
;
5882 e
->X_add_number
= r
- i386_regtab
;
5885 input_line_pointer
= end
;
5891 md_operand (expressionS
*e
)
5893 if (*input_line_pointer
== REGISTER_PREFIX
)
5896 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
5900 e
->X_op
= O_register
;
5901 e
->X_add_number
= r
- i386_regtab
;
5902 input_line_pointer
= end
;
5908 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5909 const char *md_shortopts
= "kVQ:sqn";
5911 const char *md_shortopts
= "qn";
5914 #define OPTION_32 (OPTION_MD_BASE + 0)
5915 #define OPTION_64 (OPTION_MD_BASE + 1)
5916 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5917 #define OPTION_MARCH (OPTION_MD_BASE + 3)
5918 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
5920 struct option md_longopts
[] =
5922 {"32", no_argument
, NULL
, OPTION_32
},
5923 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5924 {"64", no_argument
, NULL
, OPTION_64
},
5926 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
5927 {"march", required_argument
, NULL
, OPTION_MARCH
},
5928 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
5929 {NULL
, no_argument
, NULL
, 0}
5931 size_t md_longopts_size
= sizeof (md_longopts
);
5934 md_parse_option (int c
, char *arg
)
5941 optimize_align_code
= 0;
5948 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5949 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5950 should be emitted or not. FIXME: Not implemented. */
5954 /* -V: SVR4 argument to print version ID. */
5956 print_version_id ();
5959 /* -k: Ignore for FreeBSD compatibility. */
5964 /* -s: On i386 Solaris, this tells the native assembler to use
5965 .stab instead of .stab.excl. We always use .stab anyhow. */
5968 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5971 const char **list
, **l
;
5973 list
= bfd_target_list ();
5974 for (l
= list
; *l
!= NULL
; l
++)
5975 if (CONST_STRNEQ (*l
, "elf64-x86-64")
5976 || strcmp (*l
, "coff-x86-64") == 0
5977 || strcmp (*l
, "pe-x86-64") == 0
5978 || strcmp (*l
, "pei-x86-64") == 0)
5980 default_arch
= "x86_64";
5984 as_fatal (_("No compiled in support for x86_64"));
5991 default_arch
= "i386";
5995 #ifdef SVR4_COMMENT_CHARS
6000 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
6002 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
6006 i386_comment_chars
= n
;
6013 as_fatal (_("Invalid -march= option: `%s'"), arg
);
6014 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
6016 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
6018 cpu_arch_isa
= cpu_arch
[i
].type
;
6019 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
6020 if (!cpu_arch_tune_set
)
6022 cpu_arch_tune
= cpu_arch_isa
;
6023 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
6028 if (i
>= ARRAY_SIZE (cpu_arch
))
6029 as_fatal (_("Invalid -march= option: `%s'"), arg
);
6034 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
6035 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
6037 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
6039 cpu_arch_tune_set
= 1;
6040 cpu_arch_tune
= cpu_arch
[i
].type
;
6041 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
6045 if (i
>= ARRAY_SIZE (cpu_arch
))
6046 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
6056 md_show_usage (stream
)
6059 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6060 fprintf (stream
, _("\
6062 -V print assembler version number\n\
6065 fprintf (stream
, _("\
6066 -n Do not optimize code alignment\n\
6067 -q quieten some warnings\n"));
6068 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6069 fprintf (stream
, _("\
6072 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6073 fprintf (stream
, _("\
6074 --32/--64 generate 32bit/64bit code\n"));
6076 #ifdef SVR4_COMMENT_CHARS
6077 fprintf (stream
, _("\
6078 --divide do not treat `/' as a comment character\n"));
6080 fprintf (stream
, _("\
6081 --divide ignored\n"));
6083 fprintf (stream
, _("\
6084 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6085 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
6086 core, core2, k6, athlon, k8, generic32, generic64\n"));
6092 x86_64_target_format (void)
6094 if (strcmp (default_arch
, "x86_64") == 0)
6096 set_code_flag (CODE_64BIT
);
6097 return COFF_TARGET_FORMAT
;
6099 else if (strcmp (default_arch
, "i386") == 0)
6101 set_code_flag (CODE_32BIT
);
6105 as_fatal (_("Unknown architecture"));
6110 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6111 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6113 /* Pick the target format to use. */
6116 i386_target_format (void)
6118 if (!strcmp (default_arch
, "x86_64"))
6120 set_code_flag (CODE_64BIT
);
6121 if (cpu_arch_isa_flags
== 0)
6122 cpu_arch_isa_flags
= Cpu186
|Cpu286
|Cpu386
|Cpu486
6123 |Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
6125 if (cpu_arch_tune_flags
== 0)
6126 cpu_arch_tune_flags
= Cpu186
|Cpu286
|Cpu386
|Cpu486
6127 |Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
6130 else if (!strcmp (default_arch
, "i386"))
6132 set_code_flag (CODE_32BIT
);
6133 if (cpu_arch_isa_flags
== 0)
6134 cpu_arch_isa_flags
= Cpu186
|Cpu286
|Cpu386
;
6135 if (cpu_arch_tune_flags
== 0)
6136 cpu_arch_tune_flags
= Cpu186
|Cpu286
|Cpu386
;
6139 as_fatal (_("Unknown architecture"));
6140 switch (OUTPUT_FLAVOR
)
6142 #ifdef OBJ_MAYBE_AOUT
6143 case bfd_target_aout_flavour
:
6144 return AOUT_TARGET_FORMAT
;
6146 #ifdef OBJ_MAYBE_COFF
6147 case bfd_target_coff_flavour
:
6150 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6151 case bfd_target_elf_flavour
:
6153 if (flag_code
== CODE_64BIT
)
6156 use_rela_relocations
= 1;
6158 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
6167 #endif /* OBJ_MAYBE_ more than one */
6169 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6171 i386_elf_emit_arch_note (void)
6173 if (IS_ELF
&& cpu_arch_name
!= NULL
)
6176 asection
*seg
= now_seg
;
6177 subsegT subseg
= now_subseg
;
6178 Elf_Internal_Note i_note
;
6179 Elf_External_Note e_note
;
6180 asection
*note_secp
;
6183 /* Create the .note section. */
6184 note_secp
= subseg_new (".note", 0);
6185 bfd_set_section_flags (stdoutput
,
6187 SEC_HAS_CONTENTS
| SEC_READONLY
);
6189 /* Process the arch string. */
6190 len
= strlen (cpu_arch_name
);
6192 i_note
.namesz
= len
+ 1;
6194 i_note
.type
= NT_ARCH
;
6195 p
= frag_more (sizeof (e_note
.namesz
));
6196 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
6197 p
= frag_more (sizeof (e_note
.descsz
));
6198 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
6199 p
= frag_more (sizeof (e_note
.type
));
6200 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
6201 p
= frag_more (len
+ 1);
6202 strcpy (p
, cpu_arch_name
);
6204 frag_align (2, 0, 0);
6206 subseg_set (seg
, subseg
);
6212 md_undefined_symbol (name
)
6215 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
6216 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
6217 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
6218 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
6222 if (symbol_find (name
))
6223 as_bad (_("GOT already in symbol table"));
6224 GOT_symbol
= symbol_new (name
, undefined_section
,
6225 (valueT
) 0, &zero_address_frag
);
6232 /* Round up a section size to the appropriate boundary. */
6235 md_section_align (segment
, size
)
6236 segT segment ATTRIBUTE_UNUSED
;
6239 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6240 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
6242 /* For a.out, force the section size to be aligned. If we don't do
6243 this, BFD will align it for us, but it will not write out the
6244 final bytes of the section. This may be a bug in BFD, but it is
6245 easier to fix it here since that is how the other a.out targets
6249 align
= bfd_get_section_alignment (stdoutput
, segment
);
6250 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
6257 /* On the i386, PC-relative offsets are relative to the start of the
6258 next instruction. That is, the address of the offset, plus its
6259 size, since the offset is always the last part of the insn. */
6262 md_pcrel_from (fixS
*fixP
)
6264 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6270 s_bss (int ignore ATTRIBUTE_UNUSED
)
6274 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6276 obj_elf_section_change_hook ();
6278 temp
= get_absolute_expression ();
6279 subseg_set (bss_section
, (subsegT
) temp
);
6280 demand_empty_rest_of_line ();
6286 i386_validate_fix (fixS
*fixp
)
6288 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
6290 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
6294 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
6299 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
6301 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
6308 tc_gen_reloc (section
, fixp
)
6309 asection
*section ATTRIBUTE_UNUSED
;
6313 bfd_reloc_code_real_type code
;
6315 switch (fixp
->fx_r_type
)
6317 case BFD_RELOC_X86_64_PLT32
:
6318 case BFD_RELOC_X86_64_GOT32
:
6319 case BFD_RELOC_X86_64_GOTPCREL
:
6320 case BFD_RELOC_386_PLT32
:
6321 case BFD_RELOC_386_GOT32
:
6322 case BFD_RELOC_386_GOTOFF
:
6323 case BFD_RELOC_386_GOTPC
:
6324 case BFD_RELOC_386_TLS_GD
:
6325 case BFD_RELOC_386_TLS_LDM
:
6326 case BFD_RELOC_386_TLS_LDO_32
:
6327 case BFD_RELOC_386_TLS_IE_32
:
6328 case BFD_RELOC_386_TLS_IE
:
6329 case BFD_RELOC_386_TLS_GOTIE
:
6330 case BFD_RELOC_386_TLS_LE_32
:
6331 case BFD_RELOC_386_TLS_LE
:
6332 case BFD_RELOC_386_TLS_GOTDESC
:
6333 case BFD_RELOC_386_TLS_DESC_CALL
:
6334 case BFD_RELOC_X86_64_TLSGD
:
6335 case BFD_RELOC_X86_64_TLSLD
:
6336 case BFD_RELOC_X86_64_DTPOFF32
:
6337 case BFD_RELOC_X86_64_DTPOFF64
:
6338 case BFD_RELOC_X86_64_GOTTPOFF
:
6339 case BFD_RELOC_X86_64_TPOFF32
:
6340 case BFD_RELOC_X86_64_TPOFF64
:
6341 case BFD_RELOC_X86_64_GOTOFF64
:
6342 case BFD_RELOC_X86_64_GOTPC32
:
6343 case BFD_RELOC_X86_64_GOT64
:
6344 case BFD_RELOC_X86_64_GOTPCREL64
:
6345 case BFD_RELOC_X86_64_GOTPC64
:
6346 case BFD_RELOC_X86_64_GOTPLT64
:
6347 case BFD_RELOC_X86_64_PLTOFF64
:
6348 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
6349 case BFD_RELOC_X86_64_TLSDESC_CALL
:
6351 case BFD_RELOC_VTABLE_ENTRY
:
6352 case BFD_RELOC_VTABLE_INHERIT
:
6354 case BFD_RELOC_32_SECREL
:
6356 code
= fixp
->fx_r_type
;
6358 case BFD_RELOC_X86_64_32S
:
6359 if (!fixp
->fx_pcrel
)
6361 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6362 code
= fixp
->fx_r_type
;
6368 switch (fixp
->fx_size
)
6371 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6372 _("can not do %d byte pc-relative relocation"),
6374 code
= BFD_RELOC_32_PCREL
;
6376 case 1: code
= BFD_RELOC_8_PCREL
; break;
6377 case 2: code
= BFD_RELOC_16_PCREL
; break;
6378 case 4: code
= BFD_RELOC_32_PCREL
; break;
6380 case 8: code
= BFD_RELOC_64_PCREL
; break;
6386 switch (fixp
->fx_size
)
6389 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6390 _("can not do %d byte relocation"),
6392 code
= BFD_RELOC_32
;
6394 case 1: code
= BFD_RELOC_8
; break;
6395 case 2: code
= BFD_RELOC_16
; break;
6396 case 4: code
= BFD_RELOC_32
; break;
6398 case 8: code
= BFD_RELOC_64
; break;
6405 if ((code
== BFD_RELOC_32
6406 || code
== BFD_RELOC_32_PCREL
6407 || code
== BFD_RELOC_X86_64_32S
)
6409 && fixp
->fx_addsy
== GOT_symbol
)
6412 code
= BFD_RELOC_386_GOTPC
;
6414 code
= BFD_RELOC_X86_64_GOTPC32
;
6416 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
6418 && fixp
->fx_addsy
== GOT_symbol
)
6420 code
= BFD_RELOC_X86_64_GOTPC64
;
6423 rel
= (arelent
*) xmalloc (sizeof (arelent
));
6424 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
6425 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6427 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6429 if (!use_rela_relocations
)
6431 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6432 vtable entry to be used in the relocation's section offset. */
6433 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
6434 rel
->address
= fixp
->fx_offset
;
6438 /* Use the rela in 64bit mode. */
6441 if (!fixp
->fx_pcrel
)
6442 rel
->addend
= fixp
->fx_offset
;
6446 case BFD_RELOC_X86_64_PLT32
:
6447 case BFD_RELOC_X86_64_GOT32
:
6448 case BFD_RELOC_X86_64_GOTPCREL
:
6449 case BFD_RELOC_X86_64_TLSGD
:
6450 case BFD_RELOC_X86_64_TLSLD
:
6451 case BFD_RELOC_X86_64_GOTTPOFF
:
6452 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
6453 case BFD_RELOC_X86_64_TLSDESC_CALL
:
6454 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
6457 rel
->addend
= (section
->vma
6459 + fixp
->fx_addnumber
6460 + md_pcrel_from (fixp
));
6465 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
6466 if (rel
->howto
== NULL
)
6468 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6469 _("cannot represent relocation type %s"),
6470 bfd_get_reloc_code_name (code
));
6471 /* Set howto to a garbage value so that we can keep going. */
6472 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
6473 assert (rel
->howto
!= NULL
);
6480 /* Parse operands using Intel syntax. This implements a recursive descent
6481 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6484 FIXME: We do not recognize the full operand grammar defined in the MASM
6485 documentation. In particular, all the structure/union and
6486 high-level macro operands are missing.
6488 Uppercase words are terminals, lower case words are non-terminals.
6489 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6490 bars '|' denote choices. Most grammar productions are implemented in
6491 functions called 'intel_<production>'.
6493 Initial production is 'expr'.
6499 binOp & | AND | \| | OR | ^ | XOR
6501 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6503 constant digits [[ radixOverride ]]
6505 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
6543 => expr expr cmpOp e04
6546 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
6547 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
6549 hexdigit a | b | c | d | e | f
6550 | A | B | C | D | E | F
6556 mulOp * | / | % | MOD | << | SHL | >> | SHR
6560 register specialRegister
6564 segmentRegister CS | DS | ES | FS | GS | SS
6566 specialRegister CR0 | CR2 | CR3 | CR4
6567 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
6568 | TR3 | TR4 | TR5 | TR6 | TR7
6570 We simplify the grammar in obvious places (e.g., register parsing is
6571 done by calling parse_register) and eliminate immediate left recursion
6572 to implement a recursive-descent parser.
6576 expr' cmpOp e04 expr'
6627 /* Parsing structure for the intel syntax parser. Used to implement the
6628 semantic actions for the operand grammar. */
6629 struct intel_parser_s
6631 char *op_string
; /* The string being parsed. */
6632 int got_a_float
; /* Whether the operand is a float. */
6633 int op_modifier
; /* Operand modifier. */
6634 int is_mem
; /* 1 if operand is memory reference. */
6635 int in_offset
; /* >=1 if parsing operand of offset. */
6636 int in_bracket
; /* >=1 if parsing operand in brackets. */
6637 const reg_entry
*reg
; /* Last register reference found. */
6638 char *disp
; /* Displacement string being built. */
6639 char *next_operand
; /* Resume point when splitting operands. */
6642 static struct intel_parser_s intel_parser
;
6644 /* Token structure for parsing intel syntax. */
6647 int code
; /* Token code. */
6648 const reg_entry
*reg
; /* Register entry for register tokens. */
6649 char *str
; /* String representation. */
6652 static struct intel_token cur_token
, prev_token
;
6654 /* Token codes for the intel parser. Since T_SHORT is already used
6655 by COFF, undefine it first to prevent a warning. */
6674 /* Prototypes for intel parser functions. */
6675 static int intel_match_token (int);
6676 static void intel_putback_token (void);
6677 static void intel_get_token (void);
6678 static int intel_expr (void);
6679 static int intel_e04 (void);
6680 static int intel_e05 (void);
6681 static int intel_e06 (void);
6682 static int intel_e09 (void);
6683 static int intel_e10 (void);
6684 static int intel_e11 (void);
6687 i386_intel_operand (char *operand_string
, int got_a_float
)
6692 p
= intel_parser
.op_string
= xstrdup (operand_string
);
6693 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
6697 /* Initialize token holders. */
6698 cur_token
.code
= prev_token
.code
= T_NIL
;
6699 cur_token
.reg
= prev_token
.reg
= NULL
;
6700 cur_token
.str
= prev_token
.str
= NULL
;
6702 /* Initialize parser structure. */
6703 intel_parser
.got_a_float
= got_a_float
;
6704 intel_parser
.op_modifier
= 0;
6705 intel_parser
.is_mem
= 0;
6706 intel_parser
.in_offset
= 0;
6707 intel_parser
.in_bracket
= 0;
6708 intel_parser
.reg
= NULL
;
6709 intel_parser
.disp
[0] = '\0';
6710 intel_parser
.next_operand
= NULL
;
6712 /* Read the first token and start the parser. */
6714 ret
= intel_expr ();
6719 if (cur_token
.code
!= T_NIL
)
6721 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6722 current_templates
->start
->name
, cur_token
.str
);
6725 /* If we found a memory reference, hand it over to i386_displacement
6726 to fill in the rest of the operand fields. */
6727 else if (intel_parser
.is_mem
)
6729 if ((i
.mem_operands
== 1
6730 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
6731 || i
.mem_operands
== 2)
6733 as_bad (_("too many memory references for '%s'"),
6734 current_templates
->start
->name
);
6739 char *s
= intel_parser
.disp
;
6742 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
6743 /* See the comments in intel_bracket_expr. */
6744 as_warn (_("Treating `%s' as memory reference"), operand_string
);
6746 /* Add the displacement expression. */
6748 ret
= i386_displacement (s
, s
+ strlen (s
));
6751 /* Swap base and index in 16-bit memory operands like
6752 [si+bx]. Since i386_index_check is also used in AT&T
6753 mode we have to do that here. */
6756 && (i
.base_reg
->reg_type
& Reg16
)
6757 && (i
.index_reg
->reg_type
& Reg16
)
6758 && i
.base_reg
->reg_num
>= 6
6759 && i
.index_reg
->reg_num
< 6)
6761 const reg_entry
*base
= i
.index_reg
;
6763 i
.index_reg
= i
.base_reg
;
6766 ret
= i386_index_check (operand_string
);
6771 /* Constant and OFFSET expressions are handled by i386_immediate. */
6772 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
6773 || intel_parser
.reg
== NULL
)
6774 ret
= i386_immediate (intel_parser
.disp
);
6776 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
6778 if (!ret
|| !intel_parser
.next_operand
)
6780 intel_parser
.op_string
= intel_parser
.next_operand
;
6781 this_operand
= i
.operands
++;
6785 free (intel_parser
.disp
);
6790 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6794 expr' cmpOp e04 expr'
6799 /* XXX Implement the comparison operators. */
6800 return intel_e04 ();
6817 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6818 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
6820 if (cur_token
.code
== '+')
6822 else if (cur_token
.code
== '-')
6823 nregs
= NUM_ADDRESS_REGS
;
6827 strcat (intel_parser
.disp
, cur_token
.str
);
6828 intel_match_token (cur_token
.code
);
6839 int nregs
= ~NUM_ADDRESS_REGS
;
6846 if (cur_token
.code
== '&'
6847 || cur_token
.code
== '|'
6848 || cur_token
.code
== '^')
6852 str
[0] = cur_token
.code
;
6854 strcat (intel_parser
.disp
, str
);
6859 intel_match_token (cur_token
.code
);
6864 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6865 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
6876 int nregs
= ~NUM_ADDRESS_REGS
;
6883 if (cur_token
.code
== '*'
6884 || cur_token
.code
== '/'
6885 || cur_token
.code
== '%')
6889 str
[0] = cur_token
.code
;
6891 strcat (intel_parser
.disp
, str
);
6893 else if (cur_token
.code
== T_SHL
)
6894 strcat (intel_parser
.disp
, "<<");
6895 else if (cur_token
.code
== T_SHR
)
6896 strcat (intel_parser
.disp
, ">>");
6900 intel_match_token (cur_token
.code
);
6905 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6906 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
6924 int nregs
= ~NUM_ADDRESS_REGS
;
6929 /* Don't consume constants here. */
6930 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6932 /* Need to look one token ahead - if the next token
6933 is a constant, the current token is its sign. */
6936 intel_match_token (cur_token
.code
);
6937 next_code
= cur_token
.code
;
6938 intel_putback_token ();
6939 if (next_code
== T_CONST
)
6943 /* e09 OFFSET e09 */
6944 if (cur_token
.code
== T_OFFSET
)
6947 ++intel_parser
.in_offset
;
6951 else if (cur_token
.code
== T_SHORT
)
6952 intel_parser
.op_modifier
|= 1 << T_SHORT
;
6955 else if (cur_token
.code
== '+')
6956 strcat (intel_parser
.disp
, "+");
6961 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
6967 str
[0] = cur_token
.code
;
6969 strcat (intel_parser
.disp
, str
);
6976 intel_match_token (cur_token
.code
);
6984 /* e09' PTR e10 e09' */
6985 if (cur_token
.code
== T_PTR
)
6989 if (prev_token
.code
== T_BYTE
)
6990 suffix
= BYTE_MNEM_SUFFIX
;
6992 else if (prev_token
.code
== T_WORD
)
6994 if (current_templates
->start
->name
[0] == 'l'
6995 && current_templates
->start
->name
[2] == 's'
6996 && current_templates
->start
->name
[3] == 0)
6997 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6998 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
6999 suffix
= SHORT_MNEM_SUFFIX
;
7001 suffix
= WORD_MNEM_SUFFIX
;
7004 else if (prev_token
.code
== T_DWORD
)
7006 if (current_templates
->start
->name
[0] == 'l'
7007 && current_templates
->start
->name
[2] == 's'
7008 && current_templates
->start
->name
[3] == 0)
7009 suffix
= WORD_MNEM_SUFFIX
;
7010 else if (flag_code
== CODE_16BIT
7011 && (current_templates
->start
->opcode_modifier
7012 & (Jump
| JumpDword
)))
7013 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
7014 else if (intel_parser
.got_a_float
== 1) /* "f..." */
7015 suffix
= SHORT_MNEM_SUFFIX
;
7017 suffix
= LONG_MNEM_SUFFIX
;
7020 else if (prev_token
.code
== T_FWORD
)
7022 if (current_templates
->start
->name
[0] == 'l'
7023 && current_templates
->start
->name
[2] == 's'
7024 && current_templates
->start
->name
[3] == 0)
7025 suffix
= LONG_MNEM_SUFFIX
;
7026 else if (!intel_parser
.got_a_float
)
7028 if (flag_code
== CODE_16BIT
)
7029 add_prefix (DATA_PREFIX_OPCODE
);
7030 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
7033 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
7036 else if (prev_token
.code
== T_QWORD
)
7038 if (intel_parser
.got_a_float
== 1) /* "f..." */
7039 suffix
= LONG_MNEM_SUFFIX
;
7041 suffix
= QWORD_MNEM_SUFFIX
;
7044 else if (prev_token
.code
== T_TBYTE
)
7046 if (intel_parser
.got_a_float
== 1)
7047 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
7049 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
7052 else if (prev_token
.code
== T_XMMWORD
)
7054 /* XXX ignored for now, but accepted since gcc uses it */
7060 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
7064 /* Operands for jump/call using 'ptr' notation denote absolute
7066 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
))
7067 i
.types
[this_operand
] |= JumpAbsolute
;
7069 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
7073 else if (i
.suffix
!= suffix
)
7075 as_bad (_("Conflicting operand modifiers"));
7081 /* e09' : e10 e09' */
7082 else if (cur_token
.code
== ':')
7084 if (prev_token
.code
!= T_REG
)
7086 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7087 segment/group identifier (which we don't have), using comma
7088 as the operand separator there is even less consistent, since
7089 there all branches only have a single operand. */
7090 if (this_operand
!= 0
7091 || intel_parser
.in_offset
7092 || intel_parser
.in_bracket
7093 || (!(current_templates
->start
->opcode_modifier
7094 & (Jump
|JumpDword
|JumpInterSegment
))
7095 && !(current_templates
->start
->operand_types
[0]
7097 return intel_match_token (T_NIL
);
7098 /* Remember the start of the 2nd operand and terminate 1st
7100 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7101 another expression), but it gets at least the simplest case
7102 (a plain number or symbol on the left side) right. */
7103 intel_parser
.next_operand
= intel_parser
.op_string
;
7104 *--intel_parser
.op_string
= '\0';
7105 return intel_match_token (':');
7113 intel_match_token (cur_token
.code
);
7119 --intel_parser
.in_offset
;
7122 if (NUM_ADDRESS_REGS
> nregs
)
7124 as_bad (_("Invalid operand to `OFFSET'"));
7127 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
7130 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
7131 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
7136 intel_bracket_expr (void)
7138 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
7139 const char *start
= intel_parser
.op_string
;
7142 if (i
.op
[this_operand
].regs
)
7143 return intel_match_token (T_NIL
);
7145 intel_match_token ('[');
7147 /* Mark as a memory operand only if it's not already known to be an
7148 offset expression. If it's an offset expression, we need to keep
7150 if (!intel_parser
.in_offset
)
7152 ++intel_parser
.in_bracket
;
7154 /* Operands for jump/call inside brackets denote absolute addresses. */
7155 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
))
7156 i
.types
[this_operand
] |= JumpAbsolute
;
7158 /* Unfortunately gas always diverged from MASM in a respect that can't
7159 be easily fixed without risking to break code sequences likely to be
7160 encountered (the testsuite even check for this): MASM doesn't consider
7161 an expression inside brackets unconditionally as a memory reference.
7162 When that is e.g. a constant, an offset expression, or the sum of the
7163 two, this is still taken as a constant load. gas, however, always
7164 treated these as memory references. As a compromise, we'll try to make
7165 offset expressions inside brackets work the MASM way (since that's
7166 less likely to be found in real world code), but make constants alone
7167 continue to work the traditional gas way. In either case, issue a
7169 intel_parser
.op_modifier
&= ~was_offset
;
7172 strcat (intel_parser
.disp
, "[");
7174 /* Add a '+' to the displacement string if necessary. */
7175 if (*intel_parser
.disp
!= '\0'
7176 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
7177 strcat (intel_parser
.disp
, "+");
7180 && (len
= intel_parser
.op_string
- start
- 1,
7181 intel_match_token (']')))
7183 /* Preserve brackets when the operand is an offset expression. */
7184 if (intel_parser
.in_offset
)
7185 strcat (intel_parser
.disp
, "]");
7188 --intel_parser
.in_bracket
;
7189 if (i
.base_reg
|| i
.index_reg
)
7190 intel_parser
.is_mem
= 1;
7191 if (!intel_parser
.is_mem
)
7193 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
7194 /* Defer the warning until all of the operand was parsed. */
7195 intel_parser
.is_mem
= -1;
7196 else if (!quiet_warnings
)
7197 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
7198 len
, start
, len
, start
);
7201 intel_parser
.op_modifier
|= was_offset
;
7218 while (cur_token
.code
== '[')
7220 if (!intel_bracket_expr ())
7245 switch (cur_token
.code
)
7249 intel_match_token ('(');
7250 strcat (intel_parser
.disp
, "(");
7252 if (intel_expr () && intel_match_token (')'))
7254 strcat (intel_parser
.disp
, ")");
7261 return intel_bracket_expr ();
7266 strcat (intel_parser
.disp
, cur_token
.str
);
7267 intel_match_token (cur_token
.code
);
7269 /* Mark as a memory operand only if it's not already known to be an
7270 offset expression. */
7271 if (!intel_parser
.in_offset
)
7272 intel_parser
.is_mem
= 1;
7279 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
7281 intel_match_token (T_REG
);
7283 /* Check for segment change. */
7284 if (cur_token
.code
== ':')
7286 if (!(reg
->reg_type
& (SReg2
| SReg3
)))
7288 as_bad (_("`%s' is not a valid segment register"),
7292 else if (i
.seg
[i
.mem_operands
])
7293 as_warn (_("Extra segment override ignored"));
7296 if (!intel_parser
.in_offset
)
7297 intel_parser
.is_mem
= 1;
7298 switch (reg
->reg_num
)
7301 i
.seg
[i
.mem_operands
] = &es
;
7304 i
.seg
[i
.mem_operands
] = &cs
;
7307 i
.seg
[i
.mem_operands
] = &ss
;
7310 i
.seg
[i
.mem_operands
] = &ds
;
7313 i
.seg
[i
.mem_operands
] = &fs
;
7316 i
.seg
[i
.mem_operands
] = &gs
;
7322 /* Not a segment register. Check for register scaling. */
7323 else if (cur_token
.code
== '*')
7325 if (!intel_parser
.in_bracket
)
7327 as_bad (_("Register scaling only allowed in memory operands"));
7331 if (reg
->reg_type
& Reg16
) /* Disallow things like [si*1]. */
7332 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
7333 else if (i
.index_reg
)
7334 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
7336 /* What follows must be a valid scale. */
7337 intel_match_token ('*');
7339 i
.types
[this_operand
] |= BaseIndex
;
7341 /* Set the scale after setting the register (otherwise,
7342 i386_scale will complain) */
7343 if (cur_token
.code
== '+' || cur_token
.code
== '-')
7345 char *str
, sign
= cur_token
.code
;
7346 intel_match_token (cur_token
.code
);
7347 if (cur_token
.code
!= T_CONST
)
7349 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7353 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
7354 strcpy (str
+ 1, cur_token
.str
);
7356 if (!i386_scale (str
))
7360 else if (!i386_scale (cur_token
.str
))
7362 intel_match_token (cur_token
.code
);
7365 /* No scaling. If this is a memory operand, the register is either a
7366 base register (first occurrence) or an index register (second
7368 else if (intel_parser
.in_bracket
)
7373 else if (!i
.index_reg
)
7377 as_bad (_("Too many register references in memory operand"));
7381 i
.types
[this_operand
] |= BaseIndex
;
7384 /* It's neither base nor index. */
7385 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
7387 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
7388 i
.op
[this_operand
].regs
= reg
;
7393 as_bad (_("Invalid use of register"));
7397 /* Since registers are not part of the displacement string (except
7398 when we're parsing offset operands), we may need to remove any
7399 preceding '+' from the displacement string. */
7400 if (*intel_parser
.disp
!= '\0'
7401 && !intel_parser
.in_offset
)
7403 char *s
= intel_parser
.disp
;
7404 s
+= strlen (s
) - 1;
7427 intel_match_token (cur_token
.code
);
7429 if (cur_token
.code
== T_PTR
)
7432 /* It must have been an identifier. */
7433 intel_putback_token ();
7434 cur_token
.code
= T_ID
;
7440 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
7444 /* The identifier represents a memory reference only if it's not
7445 preceded by an offset modifier and if it's not an equate. */
7446 symbolP
= symbol_find(cur_token
.str
);
7447 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
7448 intel_parser
.is_mem
= 1;
7456 char *save_str
, sign
= 0;
7458 /* Allow constants that start with `+' or `-'. */
7459 if (cur_token
.code
== '-' || cur_token
.code
== '+')
7461 sign
= cur_token
.code
;
7462 intel_match_token (cur_token
.code
);
7463 if (cur_token
.code
!= T_CONST
)
7465 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7471 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
7472 strcpy (save_str
+ !!sign
, cur_token
.str
);
7476 /* Get the next token to check for register scaling. */
7477 intel_match_token (cur_token
.code
);
7479 /* Check if this constant is a scaling factor for an
7481 if (cur_token
.code
== '*')
7483 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
7485 const reg_entry
*reg
= cur_token
.reg
;
7487 if (!intel_parser
.in_bracket
)
7489 as_bad (_("Register scaling only allowed "
7490 "in memory operands"));
7494 /* Disallow things like [1*si].
7495 sp and esp are invalid as index. */
7496 if (reg
->reg_type
& Reg16
)
7497 reg
= i386_regtab
+ REGNAM_AX
+ 4;
7498 else if (i
.index_reg
)
7499 reg
= i386_regtab
+ REGNAM_EAX
+ 4;
7501 /* The constant is followed by `* reg', so it must be
7504 i
.types
[this_operand
] |= BaseIndex
;
7506 /* Set the scale after setting the register (otherwise,
7507 i386_scale will complain) */
7508 if (!i386_scale (save_str
))
7510 intel_match_token (T_REG
);
7512 /* Since registers are not part of the displacement
7513 string, we may need to remove any preceding '+' from
7514 the displacement string. */
7515 if (*intel_parser
.disp
!= '\0')
7517 char *s
= intel_parser
.disp
;
7518 s
+= strlen (s
) - 1;
7528 /* The constant was not used for register scaling. Since we have
7529 already consumed the token following `*' we now need to put it
7530 back in the stream. */
7531 intel_putback_token ();
7534 /* Add the constant to the displacement string. */
7535 strcat (intel_parser
.disp
, save_str
);
7542 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
7546 /* Match the given token against cur_token. If they match, read the next
7547 token from the operand string. */
7549 intel_match_token (int code
)
7551 if (cur_token
.code
== code
)
7558 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
7563 /* Read a new token from intel_parser.op_string and store it in cur_token. */
7565 intel_get_token (void)
7568 const reg_entry
*reg
;
7569 struct intel_token new_token
;
7571 new_token
.code
= T_NIL
;
7572 new_token
.reg
= NULL
;
7573 new_token
.str
= NULL
;
7575 /* Free the memory allocated to the previous token and move
7576 cur_token to prev_token. */
7578 free (prev_token
.str
);
7580 prev_token
= cur_token
;
7582 /* Skip whitespace. */
7583 while (is_space_char (*intel_parser
.op_string
))
7584 intel_parser
.op_string
++;
7586 /* Return an empty token if we find nothing else on the line. */
7587 if (*intel_parser
.op_string
== '\0')
7589 cur_token
= new_token
;
7593 /* The new token cannot be larger than the remainder of the operand
7595 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
7596 new_token
.str
[0] = '\0';
7598 if (strchr ("0123456789", *intel_parser
.op_string
))
7600 char *p
= new_token
.str
;
7601 char *q
= intel_parser
.op_string
;
7602 new_token
.code
= T_CONST
;
7604 /* Allow any kind of identifier char to encompass floating point and
7605 hexadecimal numbers. */
7606 while (is_identifier_char (*q
))
7610 /* Recognize special symbol names [0-9][bf]. */
7611 if (strlen (intel_parser
.op_string
) == 2
7612 && (intel_parser
.op_string
[1] == 'b'
7613 || intel_parser
.op_string
[1] == 'f'))
7614 new_token
.code
= T_ID
;
7617 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
7619 size_t len
= end_op
- intel_parser
.op_string
;
7621 new_token
.code
= T_REG
;
7622 new_token
.reg
= reg
;
7624 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
7625 new_token
.str
[len
] = '\0';
7628 else if (is_identifier_char (*intel_parser
.op_string
))
7630 char *p
= new_token
.str
;
7631 char *q
= intel_parser
.op_string
;
7633 /* A '.' or '$' followed by an identifier char is an identifier.
7634 Otherwise, it's operator '.' followed by an expression. */
7635 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
7637 new_token
.code
= '.';
7638 new_token
.str
[0] = '.';
7639 new_token
.str
[1] = '\0';
7643 while (is_identifier_char (*q
) || *q
== '@')
7647 if (strcasecmp (new_token
.str
, "NOT") == 0)
7648 new_token
.code
= '~';
7650 else if (strcasecmp (new_token
.str
, "MOD") == 0)
7651 new_token
.code
= '%';
7653 else if (strcasecmp (new_token
.str
, "AND") == 0)
7654 new_token
.code
= '&';
7656 else if (strcasecmp (new_token
.str
, "OR") == 0)
7657 new_token
.code
= '|';
7659 else if (strcasecmp (new_token
.str
, "XOR") == 0)
7660 new_token
.code
= '^';
7662 else if (strcasecmp (new_token
.str
, "SHL") == 0)
7663 new_token
.code
= T_SHL
;
7665 else if (strcasecmp (new_token
.str
, "SHR") == 0)
7666 new_token
.code
= T_SHR
;
7668 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
7669 new_token
.code
= T_BYTE
;
7671 else if (strcasecmp (new_token
.str
, "WORD") == 0)
7672 new_token
.code
= T_WORD
;
7674 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
7675 new_token
.code
= T_DWORD
;
7677 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
7678 new_token
.code
= T_FWORD
;
7680 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
7681 new_token
.code
= T_QWORD
;
7683 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
7684 /* XXX remove (gcc still uses it) */
7685 || strcasecmp (new_token
.str
, "XWORD") == 0)
7686 new_token
.code
= T_TBYTE
;
7688 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
7689 || strcasecmp (new_token
.str
, "OWORD") == 0)
7690 new_token
.code
= T_XMMWORD
;
7692 else if (strcasecmp (new_token
.str
, "PTR") == 0)
7693 new_token
.code
= T_PTR
;
7695 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
7696 new_token
.code
= T_SHORT
;
7698 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
7700 new_token
.code
= T_OFFSET
;
7702 /* ??? This is not mentioned in the MASM grammar but gcc
7703 makes use of it with -mintel-syntax. OFFSET may be
7704 followed by FLAT: */
7705 if (strncasecmp (q
, " FLAT:", 6) == 0)
7706 strcat (new_token
.str
, " FLAT:");
7709 /* ??? This is not mentioned in the MASM grammar. */
7710 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
7712 new_token
.code
= T_OFFSET
;
7714 strcat (new_token
.str
, ":");
7716 as_bad (_("`:' expected"));
7720 new_token
.code
= T_ID
;
7724 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
7726 new_token
.code
= *intel_parser
.op_string
;
7727 new_token
.str
[0] = *intel_parser
.op_string
;
7728 new_token
.str
[1] = '\0';
7731 else if (strchr ("<>", *intel_parser
.op_string
)
7732 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
7734 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
7735 new_token
.str
[0] = *intel_parser
.op_string
;
7736 new_token
.str
[1] = *intel_parser
.op_string
;
7737 new_token
.str
[2] = '\0';
7741 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
7743 intel_parser
.op_string
+= strlen (new_token
.str
);
7744 cur_token
= new_token
;
7747 /* Put cur_token back into the token stream and make cur_token point to
7750 intel_putback_token (void)
7752 if (cur_token
.code
!= T_NIL
)
7754 intel_parser
.op_string
-= strlen (cur_token
.str
);
7755 free (cur_token
.str
);
7757 cur_token
= prev_token
;
7759 /* Forget prev_token. */
7760 prev_token
.code
= T_NIL
;
7761 prev_token
.reg
= NULL
;
7762 prev_token
.str
= NULL
;
7766 tc_x86_regname_to_dw2regnum (char *regname
)
7768 unsigned int regnum
;
7769 unsigned int regnames_count
;
7770 static const char *const regnames_32
[] =
7772 "eax", "ecx", "edx", "ebx",
7773 "esp", "ebp", "esi", "edi",
7774 "eip", "eflags", NULL
,
7775 "st0", "st1", "st2", "st3",
7776 "st4", "st5", "st6", "st7",
7778 "xmm0", "xmm1", "xmm2", "xmm3",
7779 "xmm4", "xmm5", "xmm6", "xmm7",
7780 "mm0", "mm1", "mm2", "mm3",
7781 "mm4", "mm5", "mm6", "mm7",
7782 "fcw", "fsw", "mxcsr",
7783 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
7786 static const char *const regnames_64
[] =
7788 "rax", "rdx", "rcx", "rbx",
7789 "rsi", "rdi", "rbp", "rsp",
7790 "r8", "r9", "r10", "r11",
7791 "r12", "r13", "r14", "r15",
7793 "xmm0", "xmm1", "xmm2", "xmm3",
7794 "xmm4", "xmm5", "xmm6", "xmm7",
7795 "xmm8", "xmm9", "xmm10", "xmm11",
7796 "xmm12", "xmm13", "xmm14", "xmm15",
7797 "st0", "st1", "st2", "st3",
7798 "st4", "st5", "st6", "st7",
7799 "mm0", "mm1", "mm2", "mm3",
7800 "mm4", "mm5", "mm6", "mm7",
7802 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
7803 "fs.base", "gs.base", NULL
, NULL
,
7805 "mxcsr", "fcw", "fsw"
7807 const char *const *regnames
;
7809 if (flag_code
== CODE_64BIT
)
7811 regnames
= regnames_64
;
7812 regnames_count
= ARRAY_SIZE (regnames_64
);
7816 regnames
= regnames_32
;
7817 regnames_count
= ARRAY_SIZE (regnames_32
);
7820 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
7821 if (regnames
[regnum
] != NULL
7822 && strcmp (regname
, regnames
[regnum
]) == 0)
7829 tc_x86_frame_initial_instructions (void)
7831 static unsigned int sp_regno
;
7834 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
7837 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
7838 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
7842 i386_elf_section_type (const char *str
, size_t len
)
7844 if (flag_code
== CODE_64BIT
7845 && len
== sizeof ("unwind") - 1
7846 && strncmp (str
, "unwind", 6) == 0)
7847 return SHT_X86_64_UNWIND
;
7854 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
7858 expr
.X_op
= O_secrel
;
7859 expr
.X_add_symbol
= symbol
;
7860 expr
.X_add_number
= 0;
7861 emit_expr (&expr
, size
);
7865 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7866 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7869 x86_64_section_letter (int letter
, char **ptr_msg
)
7871 if (flag_code
== CODE_64BIT
)
7874 return SHF_X86_64_LARGE
;
7876 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7879 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
7884 x86_64_section_word (char *str
, size_t len
)
7886 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
7887 return SHF_X86_64_LARGE
;
7893 handle_large_common (int small ATTRIBUTE_UNUSED
)
7895 if (flag_code
!= CODE_64BIT
)
7897 s_comm_internal (0, elf_common_parse
);
7898 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7902 static segT lbss_section
;
7903 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
7904 asection
*saved_bss_section
= bss_section
;
7906 if (lbss_section
== NULL
)
7908 flagword applicable
;
7910 subsegT subseg
= now_subseg
;
7912 /* The .lbss section is for local .largecomm symbols. */
7913 lbss_section
= subseg_new (".lbss", 0);
7914 applicable
= bfd_applicable_section_flags (stdoutput
);
7915 bfd_set_section_flags (stdoutput
, lbss_section
,
7916 applicable
& SEC_ALLOC
);
7917 seg_info (lbss_section
)->bss
= 1;
7919 subseg_set (seg
, subseg
);
7922 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
7923 bss_section
= lbss_section
;
7925 s_comm_internal (0, elf_common_parse
);
7927 elf_com_section_ptr
= saved_com_section_ptr
;
7928 bss_section
= saved_bss_section
;
7931 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */