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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
20
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
27
28 #include "as.h"
29 #include "safe-ctype.h"
30 #include "subsegs.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
35
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
38 #endif
39
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
42 #endif
43
44 #ifndef DEFAULT_ARCH
45 #define DEFAULT_ARCH "i386"
46 #endif
47
48 #ifndef INLINE
49 #if __GNUC__ >= 2
50 #define INLINE __inline__
51 #else
52 #define INLINE
53 #endif
54 #endif
55
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
61 #define WAIT_PREFIX 0
62 #define SEG_PREFIX 1
63 #define ADDR_PREFIX 2
64 #define DATA_PREFIX 3
65 #define REP_PREFIX 4
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
68 #define LOCK_PREFIX 5
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
71
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
76
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
85 in instructions. */
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
87
88 #define END_OF_INSN '\0'
89
90 /*
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
95 END.
96 */
97 typedef struct
98 {
99 const insn_template *start;
100 const insn_template *end;
101 }
102 templates;
103
104 /* 386 operand encoding bytes: see 386 book for details of this. */
105 typedef struct
106 {
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
110 }
111 modrm_byte;
112
113 /* x86-64 extension prefix. */
114 typedef int rex_byte;
115
116 /* 386 opcode byte to code indirect addressing. */
117 typedef struct
118 {
119 unsigned base;
120 unsigned index;
121 unsigned scale;
122 }
123 sib_byte;
124
125 /* x86 arch names, types and features */
126 typedef struct
127 {
128 const char *name; /* arch name */
129 unsigned int len; /* arch string length */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132 unsigned int skip; /* show_arch should skip this. */
133 }
134 arch_entry;
135
136 /* Used to turn off indicated flags. */
137 typedef struct
138 {
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
142 }
143 noarch_entry;
144
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
153 #ifdef TE_PE
154 static void pe_directive_secrel (int);
155 #endif
156 static void signed_cons (int);
157 static char *output_invalid (int c);
158 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
159 const char *);
160 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
161 const char *);
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS *);
165 static int i386_intel_parse_name (const char *, expressionS *);
166 static const reg_entry *parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template *match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry *build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS *, offsetT);
185 static void output_disp (fragS *, offsetT);
186 #ifndef I386COFF
187 static void s_bss (int);
188 #endif
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED);
191 #endif
192
193 static const char *default_arch = DEFAULT_ARCH;
194
195 /* This struct describes rounding control and SAE in the instruction. */
196 struct RC_Operation
197 {
198 enum rc_type
199 {
200 rne = 0,
201 rd,
202 ru,
203 rz,
204 saeonly
205 } type;
206 int operand;
207 };
208
209 static struct RC_Operation rc_op;
210
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
215 {
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
219 int operand;
220 };
221
222 static struct Mask_Operation mask_op;
223
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
225 broadcast factor. */
226 struct Broadcast_Operation
227 {
228 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
229 int type;
230
231 /* Index of broadcasted operand. */
232 int operand;
233 };
234
235 static struct Broadcast_Operation broadcast_op;
236
237 /* VEX prefix. */
238 typedef struct
239 {
240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
242 unsigned int length;
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
245 } vex_prefix;
246
247 /* 'md_assemble ()' gathers together information and puts it into a
248 i386_insn. */
249
250 union i386_op
251 {
252 expressionS *disps;
253 expressionS *imms;
254 const reg_entry *regs;
255 };
256
257 enum i386_error
258 {
259 operand_size_mismatch,
260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
264 bad_imm4,
265 old_gcc_only,
266 unsupported_with_intel_mnemonic,
267 unsupported_syntax,
268 unsupported,
269 invalid_vsib_address,
270 invalid_vector_register_set,
271 unsupported_vector_index_register,
272 unsupported_broadcast,
273 broadcast_not_on_src_operand,
274 broadcast_needed,
275 unsupported_masking,
276 mask_not_on_destination,
277 no_default_mask,
278 unsupported_rc_sae,
279 rc_sae_operand_not_last_imm,
280 invalid_register_operand,
281 };
282
283 struct _i386_insn
284 {
285 /* TM holds the template for the insn were currently assembling. */
286 insn_template tm;
287
288 /* SUFFIX holds the instruction size suffix for byte, word, dword
289 or qword, if given. */
290 char suffix;
291
292 /* OPERANDS gives the number of given operands. */
293 unsigned int operands;
294
295 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
296 of given register, displacement, memory operands and immediate
297 operands. */
298 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
299
300 /* TYPES [i] is the type (see above #defines) which tells us how to
301 use OP[i] for the corresponding operand. */
302 i386_operand_type types[MAX_OPERANDS];
303
304 /* Displacement expression, immediate expression, or register for each
305 operand. */
306 union i386_op op[MAX_OPERANDS];
307
308 /* Flags for operands. */
309 unsigned int flags[MAX_OPERANDS];
310 #define Operand_PCrel 1
311
312 /* Relocation type for operand */
313 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
314
315 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
316 the base index byte below. */
317 const reg_entry *base_reg;
318 const reg_entry *index_reg;
319 unsigned int log2_scale_factor;
320
321 /* SEG gives the seg_entries of this insn. They are zero unless
322 explicit segment overrides are given. */
323 const seg_entry *seg[2];
324
325 /* Copied first memory operand string, for re-checking. */
326 char *memop1_string;
327
328 /* PREFIX holds all the given prefix opcodes (usually null).
329 PREFIXES is the number of prefix opcodes. */
330 unsigned int prefixes;
331 unsigned char prefix[MAX_PREFIXES];
332
333 /* RM and SIB are the modrm byte and the sib byte where the
334 addressing modes of this insn are encoded. */
335 modrm_byte rm;
336 rex_byte rex;
337 rex_byte vrex;
338 sib_byte sib;
339 vex_prefix vex;
340
341 /* Masking attributes. */
342 struct Mask_Operation *mask;
343
344 /* Rounding control and SAE attributes. */
345 struct RC_Operation *rounding;
346
347 /* Broadcasting attributes. */
348 struct Broadcast_Operation *broadcast;
349
350 /* Compressed disp8*N attribute. */
351 unsigned int memshift;
352
353 /* Prefer load or store in encoding. */
354 enum
355 {
356 dir_encoding_default = 0,
357 dir_encoding_load,
358 dir_encoding_store
359 } dir_encoding;
360
361 /* Prefer 8bit or 32bit displacement in encoding. */
362 enum
363 {
364 disp_encoding_default = 0,
365 disp_encoding_8bit,
366 disp_encoding_32bit
367 } disp_encoding;
368
369 /* Prefer the REX byte in encoding. */
370 bfd_boolean rex_encoding;
371
372 /* Disable instruction size optimization. */
373 bfd_boolean no_optimize;
374
375 /* How to encode vector instructions. */
376 enum
377 {
378 vex_encoding_default = 0,
379 vex_encoding_vex2,
380 vex_encoding_vex3,
381 vex_encoding_evex
382 } vec_encoding;
383
384 /* REP prefix. */
385 const char *rep_prefix;
386
387 /* HLE prefix. */
388 const char *hle_prefix;
389
390 /* Have BND prefix. */
391 const char *bnd_prefix;
392
393 /* Have NOTRACK prefix. */
394 const char *notrack_prefix;
395
396 /* Error message. */
397 enum i386_error error;
398 };
399
400 typedef struct _i386_insn i386_insn;
401
402 /* Link RC type with corresponding string, that'll be looked for in
403 asm. */
404 struct RC_name
405 {
406 enum rc_type type;
407 const char *name;
408 unsigned int len;
409 };
410
411 static const struct RC_name RC_NamesTable[] =
412 {
413 { rne, STRING_COMMA_LEN ("rn-sae") },
414 { rd, STRING_COMMA_LEN ("rd-sae") },
415 { ru, STRING_COMMA_LEN ("ru-sae") },
416 { rz, STRING_COMMA_LEN ("rz-sae") },
417 { saeonly, STRING_COMMA_LEN ("sae") },
418 };
419
420 /* List of chars besides those in app.c:symbol_chars that can start an
421 operand. Used to prevent the scrubber eating vital white-space. */
422 const char extra_symbol_chars[] = "*%-([{}"
423 #ifdef LEX_AT
424 "@"
425 #endif
426 #ifdef LEX_QM
427 "?"
428 #endif
429 ;
430
431 #if (defined (TE_I386AIX) \
432 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
433 && !defined (TE_GNU) \
434 && !defined (TE_LINUX) \
435 && !defined (TE_NACL) \
436 && !defined (TE_NETWARE) \
437 && !defined (TE_FreeBSD) \
438 && !defined (TE_DragonFly) \
439 && !defined (TE_NetBSD)))
440 /* This array holds the chars that always start a comment. If the
441 pre-processor is disabled, these aren't very useful. The option
442 --divide will remove '/' from this list. */
443 const char *i386_comment_chars = "#/";
444 #define SVR4_COMMENT_CHARS 1
445 #define PREFIX_SEPARATOR '\\'
446
447 #else
448 const char *i386_comment_chars = "#";
449 #define PREFIX_SEPARATOR '/'
450 #endif
451
452 /* This array holds the chars that only start a comment at the beginning of
453 a line. If the line seems to have the form '# 123 filename'
454 .line and .file directives will appear in the pre-processed output.
455 Note that input_file.c hand checks for '#' at the beginning of the
456 first line of the input file. This is because the compiler outputs
457 #NO_APP at the beginning of its output.
458 Also note that comments started like this one will always work if
459 '/' isn't otherwise defined. */
460 const char line_comment_chars[] = "#/";
461
462 const char line_separator_chars[] = ";";
463
464 /* Chars that can be used to separate mant from exp in floating point
465 nums. */
466 const char EXP_CHARS[] = "eE";
467
468 /* Chars that mean this number is a floating point constant
469 As in 0f12.456
470 or 0d1.2345e12. */
471 const char FLT_CHARS[] = "fFdDxX";
472
473 /* Tables for lexical analysis. */
474 static char mnemonic_chars[256];
475 static char register_chars[256];
476 static char operand_chars[256];
477 static char identifier_chars[256];
478 static char digit_chars[256];
479
480 /* Lexical macros. */
481 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
482 #define is_operand_char(x) (operand_chars[(unsigned char) x])
483 #define is_register_char(x) (register_chars[(unsigned char) x])
484 #define is_space_char(x) ((x) == ' ')
485 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
486 #define is_digit_char(x) (digit_chars[(unsigned char) x])
487
488 /* All non-digit non-letter characters that may occur in an operand. */
489 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
490
491 /* md_assemble() always leaves the strings it's passed unaltered. To
492 effect this we maintain a stack of saved characters that we've smashed
493 with '\0's (indicating end of strings for various sub-fields of the
494 assembler instruction). */
495 static char save_stack[32];
496 static char *save_stack_p;
497 #define END_STRING_AND_SAVE(s) \
498 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
499 #define RESTORE_END_STRING(s) \
500 do { *(s) = *--save_stack_p; } while (0)
501
502 /* The instruction we're assembling. */
503 static i386_insn i;
504
505 /* Possible templates for current insn. */
506 static const templates *current_templates;
507
508 /* Per instruction expressionS buffers: max displacements & immediates. */
509 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
510 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
511
512 /* Current operand we are working on. */
513 static int this_operand = -1;
514
515 /* We support four different modes. FLAG_CODE variable is used to distinguish
516 these. */
517
518 enum flag_code {
519 CODE_32BIT,
520 CODE_16BIT,
521 CODE_64BIT };
522
523 static enum flag_code flag_code;
524 static unsigned int object_64bit;
525 static unsigned int disallow_64bit_reloc;
526 static int use_rela_relocations = 0;
527
528 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
529 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
530 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
531
532 /* The ELF ABI to use. */
533 enum x86_elf_abi
534 {
535 I386_ABI,
536 X86_64_ABI,
537 X86_64_X32_ABI
538 };
539
540 static enum x86_elf_abi x86_elf_abi = I386_ABI;
541 #endif
542
543 #if defined (TE_PE) || defined (TE_PEP)
544 /* Use big object file format. */
545 static int use_big_obj = 0;
546 #endif
547
548 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
549 /* 1 if generating code for a shared library. */
550 static int shared = 0;
551 #endif
552
553 /* 1 for intel syntax,
554 0 if att syntax. */
555 static int intel_syntax = 0;
556
557 /* 1 for Intel64 ISA,
558 0 if AMD64 ISA. */
559 static int intel64;
560
561 /* 1 for intel mnemonic,
562 0 if att mnemonic. */
563 static int intel_mnemonic = !SYSV386_COMPAT;
564
565 /* 1 if support old (<= 2.8.1) versions of gcc. */
566 static int old_gcc = OLDGCC_COMPAT;
567
568 /* 1 if pseudo registers are permitted. */
569 static int allow_pseudo_reg = 0;
570
571 /* 1 if register prefix % not required. */
572 static int allow_naked_reg = 0;
573
574 /* 1 if the assembler should add BND prefix for all control-transferring
575 instructions supporting it, even if this prefix wasn't specified
576 explicitly. */
577 static int add_bnd_prefix = 0;
578
579 /* 1 if pseudo index register, eiz/riz, is allowed . */
580 static int allow_index_reg = 0;
581
582 /* 1 if the assembler should ignore LOCK prefix, even if it was
583 specified explicitly. */
584 static int omit_lock_prefix = 0;
585
586 /* 1 if the assembler should encode lfence, mfence, and sfence as
587 "lock addl $0, (%{re}sp)". */
588 static int avoid_fence = 0;
589
590 /* 1 if the assembler should generate relax relocations. */
591
592 static int generate_relax_relocations
593 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
594
595 static enum check_kind
596 {
597 check_none = 0,
598 check_warning,
599 check_error
600 }
601 sse_check, operand_check = check_warning;
602
603 /* Optimization:
604 1. Clear the REX_W bit with register operand if possible.
605 2. Above plus use 128bit vector instruction to clear the full vector
606 register.
607 */
608 static int optimize = 0;
609
610 /* Optimization:
611 1. Clear the REX_W bit with register operand if possible.
612 2. Above plus use 128bit vector instruction to clear the full vector
613 register.
614 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
615 "testb $imm7,%r8".
616 */
617 static int optimize_for_space = 0;
618
619 /* Register prefix used for error message. */
620 static const char *register_prefix = "%";
621
622 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
623 leave, push, and pop instructions so that gcc has the same stack
624 frame as in 32 bit mode. */
625 static char stackop_size = '\0';
626
627 /* Non-zero to optimize code alignment. */
628 int optimize_align_code = 1;
629
630 /* Non-zero to quieten some warnings. */
631 static int quiet_warnings = 0;
632
633 /* CPU name. */
634 static const char *cpu_arch_name = NULL;
635 static char *cpu_sub_arch_name = NULL;
636
637 /* CPU feature flags. */
638 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
639
640 /* If we have selected a cpu we are generating instructions for. */
641 static int cpu_arch_tune_set = 0;
642
643 /* Cpu we are generating instructions for. */
644 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
645
646 /* CPU feature flags of cpu we are generating instructions for. */
647 static i386_cpu_flags cpu_arch_tune_flags;
648
649 /* CPU instruction set architecture used. */
650 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
651
652 /* CPU feature flags of instruction set architecture used. */
653 i386_cpu_flags cpu_arch_isa_flags;
654
655 /* If set, conditional jumps are not automatically promoted to handle
656 larger than a byte offset. */
657 static unsigned int no_cond_jump_promotion = 0;
658
659 /* Encode SSE instructions with VEX prefix. */
660 static unsigned int sse2avx;
661
662 /* Encode scalar AVX instructions with specific vector length. */
663 static enum
664 {
665 vex128 = 0,
666 vex256
667 } avxscalar;
668
669 /* Encode scalar EVEX LIG instructions with specific vector length. */
670 static enum
671 {
672 evexl128 = 0,
673 evexl256,
674 evexl512
675 } evexlig;
676
677 /* Encode EVEX WIG instructions with specific evex.w. */
678 static enum
679 {
680 evexw0 = 0,
681 evexw1
682 } evexwig;
683
684 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
685 static enum rc_type evexrcig = rne;
686
687 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
688 static symbolS *GOT_symbol;
689
690 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
691 unsigned int x86_dwarf2_return_column;
692
693 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
694 int x86_cie_data_alignment;
695
696 /* Interface to relax_segment.
697 There are 3 major relax states for 386 jump insns because the
698 different types of jumps add different sizes to frags when we're
699 figuring out what sort of jump to choose to reach a given label. */
700
701 /* Types. */
702 #define UNCOND_JUMP 0
703 #define COND_JUMP 1
704 #define COND_JUMP86 2
705
706 /* Sizes. */
707 #define CODE16 1
708 #define SMALL 0
709 #define SMALL16 (SMALL | CODE16)
710 #define BIG 2
711 #define BIG16 (BIG | CODE16)
712
713 #ifndef INLINE
714 #ifdef __GNUC__
715 #define INLINE __inline__
716 #else
717 #define INLINE
718 #endif
719 #endif
720
721 #define ENCODE_RELAX_STATE(type, size) \
722 ((relax_substateT) (((type) << 2) | (size)))
723 #define TYPE_FROM_RELAX_STATE(s) \
724 ((s) >> 2)
725 #define DISP_SIZE_FROM_RELAX_STATE(s) \
726 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
727
728 /* This table is used by relax_frag to promote short jumps to long
729 ones where necessary. SMALL (short) jumps may be promoted to BIG
730 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
731 don't allow a short jump in a 32 bit code segment to be promoted to
732 a 16 bit offset jump because it's slower (requires data size
733 prefix), and doesn't work, unless the destination is in the bottom
734 64k of the code segment (The top 16 bits of eip are zeroed). */
735
736 const relax_typeS md_relax_table[] =
737 {
738 /* The fields are:
739 1) most positive reach of this state,
740 2) most negative reach of this state,
741 3) how many bytes this mode will have in the variable part of the frag
742 4) which index into the table to try if we can't fit into this one. */
743
744 /* UNCOND_JUMP states. */
745 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
746 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
747 /* dword jmp adds 4 bytes to frag:
748 0 extra opcode bytes, 4 displacement bytes. */
749 {0, 0, 4, 0},
750 /* word jmp adds 2 byte2 to frag:
751 0 extra opcode bytes, 2 displacement bytes. */
752 {0, 0, 2, 0},
753
754 /* COND_JUMP states. */
755 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
756 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
757 /* dword conditionals adds 5 bytes to frag:
758 1 extra opcode byte, 4 displacement bytes. */
759 {0, 0, 5, 0},
760 /* word conditionals add 3 bytes to frag:
761 1 extra opcode byte, 2 displacement bytes. */
762 {0, 0, 3, 0},
763
764 /* COND_JUMP86 states. */
765 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
766 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
767 /* dword conditionals adds 5 bytes to frag:
768 1 extra opcode byte, 4 displacement bytes. */
769 {0, 0, 5, 0},
770 /* word conditionals add 4 bytes to frag:
771 1 displacement byte and a 3 byte long branch insn. */
772 {0, 0, 4, 0}
773 };
774
775 static const arch_entry cpu_arch[] =
776 {
777 /* Do not replace the first two entries - i386_target_format()
778 relies on them being there in this order. */
779 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
780 CPU_GENERIC32_FLAGS, 0 },
781 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
782 CPU_GENERIC64_FLAGS, 0 },
783 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
784 CPU_NONE_FLAGS, 0 },
785 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
786 CPU_I186_FLAGS, 0 },
787 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
788 CPU_I286_FLAGS, 0 },
789 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
790 CPU_I386_FLAGS, 0 },
791 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
792 CPU_I486_FLAGS, 0 },
793 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
794 CPU_I586_FLAGS, 0 },
795 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
796 CPU_I686_FLAGS, 0 },
797 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
798 CPU_I586_FLAGS, 0 },
799 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
800 CPU_PENTIUMPRO_FLAGS, 0 },
801 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
802 CPU_P2_FLAGS, 0 },
803 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
804 CPU_P3_FLAGS, 0 },
805 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
806 CPU_P4_FLAGS, 0 },
807 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
808 CPU_CORE_FLAGS, 0 },
809 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
810 CPU_NOCONA_FLAGS, 0 },
811 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
812 CPU_CORE_FLAGS, 1 },
813 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
814 CPU_CORE_FLAGS, 0 },
815 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
816 CPU_CORE2_FLAGS, 1 },
817 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
818 CPU_CORE2_FLAGS, 0 },
819 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
820 CPU_COREI7_FLAGS, 0 },
821 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
822 CPU_L1OM_FLAGS, 0 },
823 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
824 CPU_K1OM_FLAGS, 0 },
825 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
826 CPU_IAMCU_FLAGS, 0 },
827 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
828 CPU_K6_FLAGS, 0 },
829 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
830 CPU_K6_2_FLAGS, 0 },
831 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
832 CPU_ATHLON_FLAGS, 0 },
833 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
834 CPU_K8_FLAGS, 1 },
835 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
836 CPU_K8_FLAGS, 0 },
837 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
838 CPU_K8_FLAGS, 0 },
839 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
840 CPU_AMDFAM10_FLAGS, 0 },
841 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
842 CPU_BDVER1_FLAGS, 0 },
843 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
844 CPU_BDVER2_FLAGS, 0 },
845 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
846 CPU_BDVER3_FLAGS, 0 },
847 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
848 CPU_BDVER4_FLAGS, 0 },
849 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
850 CPU_ZNVER1_FLAGS, 0 },
851 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
852 CPU_BTVER1_FLAGS, 0 },
853 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
854 CPU_BTVER2_FLAGS, 0 },
855 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
856 CPU_8087_FLAGS, 0 },
857 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
858 CPU_287_FLAGS, 0 },
859 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
860 CPU_387_FLAGS, 0 },
861 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
862 CPU_687_FLAGS, 0 },
863 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
864 CPU_MMX_FLAGS, 0 },
865 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
866 CPU_SSE_FLAGS, 0 },
867 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
868 CPU_SSE2_FLAGS, 0 },
869 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
870 CPU_SSE3_FLAGS, 0 },
871 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
872 CPU_SSSE3_FLAGS, 0 },
873 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
874 CPU_SSE4_1_FLAGS, 0 },
875 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
876 CPU_SSE4_2_FLAGS, 0 },
877 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
878 CPU_SSE4_2_FLAGS, 0 },
879 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
880 CPU_AVX_FLAGS, 0 },
881 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
882 CPU_AVX2_FLAGS, 0 },
883 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
884 CPU_AVX512F_FLAGS, 0 },
885 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
886 CPU_AVX512CD_FLAGS, 0 },
887 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
888 CPU_AVX512ER_FLAGS, 0 },
889 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
890 CPU_AVX512PF_FLAGS, 0 },
891 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
892 CPU_AVX512DQ_FLAGS, 0 },
893 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
894 CPU_AVX512BW_FLAGS, 0 },
895 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
896 CPU_AVX512VL_FLAGS, 0 },
897 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
898 CPU_VMX_FLAGS, 0 },
899 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
900 CPU_VMFUNC_FLAGS, 0 },
901 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
902 CPU_SMX_FLAGS, 0 },
903 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
904 CPU_XSAVE_FLAGS, 0 },
905 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
906 CPU_XSAVEOPT_FLAGS, 0 },
907 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
908 CPU_XSAVEC_FLAGS, 0 },
909 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
910 CPU_XSAVES_FLAGS, 0 },
911 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
912 CPU_AES_FLAGS, 0 },
913 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
914 CPU_PCLMUL_FLAGS, 0 },
915 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
916 CPU_PCLMUL_FLAGS, 1 },
917 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
918 CPU_FSGSBASE_FLAGS, 0 },
919 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
920 CPU_RDRND_FLAGS, 0 },
921 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
922 CPU_F16C_FLAGS, 0 },
923 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
924 CPU_BMI2_FLAGS, 0 },
925 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
926 CPU_FMA_FLAGS, 0 },
927 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
928 CPU_FMA4_FLAGS, 0 },
929 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
930 CPU_XOP_FLAGS, 0 },
931 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
932 CPU_LWP_FLAGS, 0 },
933 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
934 CPU_MOVBE_FLAGS, 0 },
935 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
936 CPU_CX16_FLAGS, 0 },
937 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
938 CPU_EPT_FLAGS, 0 },
939 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
940 CPU_LZCNT_FLAGS, 0 },
941 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
942 CPU_HLE_FLAGS, 0 },
943 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
944 CPU_RTM_FLAGS, 0 },
945 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
946 CPU_INVPCID_FLAGS, 0 },
947 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
948 CPU_CLFLUSH_FLAGS, 0 },
949 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
950 CPU_NOP_FLAGS, 0 },
951 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
952 CPU_SYSCALL_FLAGS, 0 },
953 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
954 CPU_RDTSCP_FLAGS, 0 },
955 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
956 CPU_3DNOW_FLAGS, 0 },
957 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
958 CPU_3DNOWA_FLAGS, 0 },
959 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
960 CPU_PADLOCK_FLAGS, 0 },
961 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
962 CPU_SVME_FLAGS, 1 },
963 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
964 CPU_SVME_FLAGS, 0 },
965 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
966 CPU_SSE4A_FLAGS, 0 },
967 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
968 CPU_ABM_FLAGS, 0 },
969 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
970 CPU_BMI_FLAGS, 0 },
971 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
972 CPU_TBM_FLAGS, 0 },
973 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
974 CPU_ADX_FLAGS, 0 },
975 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
976 CPU_RDSEED_FLAGS, 0 },
977 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
978 CPU_PRFCHW_FLAGS, 0 },
979 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
980 CPU_SMAP_FLAGS, 0 },
981 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
982 CPU_MPX_FLAGS, 0 },
983 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
984 CPU_SHA_FLAGS, 0 },
985 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
986 CPU_CLFLUSHOPT_FLAGS, 0 },
987 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
988 CPU_PREFETCHWT1_FLAGS, 0 },
989 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
990 CPU_SE1_FLAGS, 0 },
991 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
992 CPU_CLWB_FLAGS, 0 },
993 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
994 CPU_AVX512IFMA_FLAGS, 0 },
995 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
996 CPU_AVX512VBMI_FLAGS, 0 },
997 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
998 CPU_AVX512_4FMAPS_FLAGS, 0 },
999 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
1000 CPU_AVX512_4VNNIW_FLAGS, 0 },
1001 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
1002 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
1003 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1004 CPU_AVX512_VBMI2_FLAGS, 0 },
1005 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1006 CPU_AVX512_VNNI_FLAGS, 0 },
1007 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1008 CPU_AVX512_BITALG_FLAGS, 0 },
1009 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1010 CPU_CLZERO_FLAGS, 0 },
1011 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1012 CPU_MWAITX_FLAGS, 0 },
1013 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1014 CPU_OSPKE_FLAGS, 0 },
1015 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1016 CPU_RDPID_FLAGS, 0 },
1017 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1018 CPU_PTWRITE_FLAGS, 0 },
1019 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1020 CPU_IBT_FLAGS, 0 },
1021 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1022 CPU_SHSTK_FLAGS, 0 },
1023 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1024 CPU_GFNI_FLAGS, 0 },
1025 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1026 CPU_VAES_FLAGS, 0 },
1027 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1028 CPU_VPCLMULQDQ_FLAGS, 0 },
1029 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1030 CPU_WBNOINVD_FLAGS, 0 },
1031 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1032 CPU_PCONFIG_FLAGS, 0 },
1033 };
1034
1035 static const noarch_entry cpu_noarch[] =
1036 {
1037 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1038 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1039 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1040 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1041 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1042 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1043 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1044 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1045 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1046 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1047 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1048 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1049 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1050 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1051 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1052 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1053 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1054 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1055 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1062 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1063 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1064 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1065 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1066 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1067 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1068 };
1069
1070 #ifdef I386COFF
1071 /* Like s_lcomm_internal in gas/read.c but the alignment string
1072 is allowed to be optional. */
1073
1074 static symbolS *
1075 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1076 {
1077 addressT align = 0;
1078
1079 SKIP_WHITESPACE ();
1080
1081 if (needs_align
1082 && *input_line_pointer == ',')
1083 {
1084 align = parse_align (needs_align - 1);
1085
1086 if (align == (addressT) -1)
1087 return NULL;
1088 }
1089 else
1090 {
1091 if (size >= 8)
1092 align = 3;
1093 else if (size >= 4)
1094 align = 2;
1095 else if (size >= 2)
1096 align = 1;
1097 else
1098 align = 0;
1099 }
1100
1101 bss_alloc (symbolP, size, align);
1102 return symbolP;
1103 }
1104
1105 static void
1106 pe_lcomm (int needs_align)
1107 {
1108 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1109 }
1110 #endif
1111
1112 const pseudo_typeS md_pseudo_table[] =
1113 {
1114 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1115 {"align", s_align_bytes, 0},
1116 #else
1117 {"align", s_align_ptwo, 0},
1118 #endif
1119 {"arch", set_cpu_arch, 0},
1120 #ifndef I386COFF
1121 {"bss", s_bss, 0},
1122 #else
1123 {"lcomm", pe_lcomm, 1},
1124 #endif
1125 {"ffloat", float_cons, 'f'},
1126 {"dfloat", float_cons, 'd'},
1127 {"tfloat", float_cons, 'x'},
1128 {"value", cons, 2},
1129 {"slong", signed_cons, 4},
1130 {"noopt", s_ignore, 0},
1131 {"optim", s_ignore, 0},
1132 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1133 {"code16", set_code_flag, CODE_16BIT},
1134 {"code32", set_code_flag, CODE_32BIT},
1135 #ifdef BFD64
1136 {"code64", set_code_flag, CODE_64BIT},
1137 #endif
1138 {"intel_syntax", set_intel_syntax, 1},
1139 {"att_syntax", set_intel_syntax, 0},
1140 {"intel_mnemonic", set_intel_mnemonic, 1},
1141 {"att_mnemonic", set_intel_mnemonic, 0},
1142 {"allow_index_reg", set_allow_index_reg, 1},
1143 {"disallow_index_reg", set_allow_index_reg, 0},
1144 {"sse_check", set_check, 0},
1145 {"operand_check", set_check, 1},
1146 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1147 {"largecomm", handle_large_common, 0},
1148 #else
1149 {"file", dwarf2_directive_file, 0},
1150 {"loc", dwarf2_directive_loc, 0},
1151 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1152 #endif
1153 #ifdef TE_PE
1154 {"secrel32", pe_directive_secrel, 0},
1155 #endif
1156 {0, 0, 0}
1157 };
1158
1159 /* For interface with expression (). */
1160 extern char *input_line_pointer;
1161
1162 /* Hash table for instruction mnemonic lookup. */
1163 static struct hash_control *op_hash;
1164
1165 /* Hash table for register lookup. */
1166 static struct hash_control *reg_hash;
1167 \f
1168 /* Various efficient no-op patterns for aligning code labels.
1169 Note: Don't try to assemble the instructions in the comments.
1170 0L and 0w are not legal. */
1171 static const unsigned char f32_1[] =
1172 {0x90}; /* nop */
1173 static const unsigned char f32_2[] =
1174 {0x66,0x90}; /* xchg %ax,%ax */
1175 static const unsigned char f32_3[] =
1176 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1177 static const unsigned char f32_4[] =
1178 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1179 static const unsigned char f32_6[] =
1180 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1181 static const unsigned char f32_7[] =
1182 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1183 static const unsigned char f16_3[] =
1184 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1185 static const unsigned char f16_4[] =
1186 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1187 static const unsigned char jump_disp8[] =
1188 {0xeb}; /* jmp disp8 */
1189 static const unsigned char jump32_disp32[] =
1190 {0xe9}; /* jmp disp32 */
1191 static const unsigned char jump16_disp32[] =
1192 {0x66,0xe9}; /* jmp disp32 */
1193 /* 32-bit NOPs patterns. */
1194 static const unsigned char *const f32_patt[] = {
1195 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1196 };
1197 /* 16-bit NOPs patterns. */
1198 static const unsigned char *const f16_patt[] = {
1199 f32_1, f32_2, f16_3, f16_4
1200 };
1201 /* nopl (%[re]ax) */
1202 static const unsigned char alt_3[] =
1203 {0x0f,0x1f,0x00};
1204 /* nopl 0(%[re]ax) */
1205 static const unsigned char alt_4[] =
1206 {0x0f,0x1f,0x40,0x00};
1207 /* nopl 0(%[re]ax,%[re]ax,1) */
1208 static const unsigned char alt_5[] =
1209 {0x0f,0x1f,0x44,0x00,0x00};
1210 /* nopw 0(%[re]ax,%[re]ax,1) */
1211 static const unsigned char alt_6[] =
1212 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1213 /* nopl 0L(%[re]ax) */
1214 static const unsigned char alt_7[] =
1215 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1216 /* nopl 0L(%[re]ax,%[re]ax,1) */
1217 static const unsigned char alt_8[] =
1218 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1219 /* nopw 0L(%[re]ax,%[re]ax,1) */
1220 static const unsigned char alt_9[] =
1221 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1222 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1223 static const unsigned char alt_10[] =
1224 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1225 /* data16 nopw %cs:0L(%eax,%eax,1) */
1226 static const unsigned char alt_11[] =
1227 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1228 /* 32-bit and 64-bit NOPs patterns. */
1229 static const unsigned char *const alt_patt[] = {
1230 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1231 alt_9, alt_10, alt_11
1232 };
1233
1234 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1235 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1236
1237 static void
1238 i386_output_nops (char *where, const unsigned char *const *patt,
1239 int count, int max_single_nop_size)
1240
1241 {
1242 /* Place the longer NOP first. */
1243 int last;
1244 int offset;
1245 const unsigned char *nops = patt[max_single_nop_size - 1];
1246
1247 /* Use the smaller one if the requsted one isn't available. */
1248 if (nops == NULL)
1249 {
1250 max_single_nop_size--;
1251 nops = patt[max_single_nop_size - 1];
1252 }
1253
1254 last = count % max_single_nop_size;
1255
1256 count -= last;
1257 for (offset = 0; offset < count; offset += max_single_nop_size)
1258 memcpy (where + offset, nops, max_single_nop_size);
1259
1260 if (last)
1261 {
1262 nops = patt[last - 1];
1263 if (nops == NULL)
1264 {
1265 /* Use the smaller one plus one-byte NOP if the needed one
1266 isn't available. */
1267 last--;
1268 nops = patt[last - 1];
1269 memcpy (where + offset, nops, last);
1270 where[offset + last] = *patt[0];
1271 }
1272 else
1273 memcpy (where + offset, nops, last);
1274 }
1275 }
1276
1277 static INLINE int
1278 fits_in_imm7 (offsetT num)
1279 {
1280 return (num & 0x7f) == num;
1281 }
1282
1283 static INLINE int
1284 fits_in_imm31 (offsetT num)
1285 {
1286 return (num & 0x7fffffff) == num;
1287 }
1288
1289 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1290 single NOP instruction LIMIT. */
1291
1292 void
1293 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1294 {
1295 const unsigned char *const *patt = NULL;
1296 int max_single_nop_size;
1297 /* Maximum number of NOPs before switching to jump over NOPs. */
1298 int max_number_of_nops;
1299
1300 switch (fragP->fr_type)
1301 {
1302 case rs_fill_nop:
1303 case rs_align_code:
1304 break;
1305 default:
1306 return;
1307 }
1308
1309 /* We need to decide which NOP sequence to use for 32bit and
1310 64bit. When -mtune= is used:
1311
1312 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1313 PROCESSOR_GENERIC32, f32_patt will be used.
1314 2. For the rest, alt_patt will be used.
1315
1316 When -mtune= isn't used, alt_patt will be used if
1317 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1318 be used.
1319
1320 When -march= or .arch is used, we can't use anything beyond
1321 cpu_arch_isa_flags. */
1322
1323 if (flag_code == CODE_16BIT)
1324 {
1325 patt = f16_patt;
1326 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1327 /* Limit number of NOPs to 2 in 16-bit mode. */
1328 max_number_of_nops = 2;
1329 }
1330 else
1331 {
1332 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1333 {
1334 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1335 switch (cpu_arch_tune)
1336 {
1337 case PROCESSOR_UNKNOWN:
1338 /* We use cpu_arch_isa_flags to check if we SHOULD
1339 optimize with nops. */
1340 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1341 patt = alt_patt;
1342 else
1343 patt = f32_patt;
1344 break;
1345 case PROCESSOR_PENTIUM4:
1346 case PROCESSOR_NOCONA:
1347 case PROCESSOR_CORE:
1348 case PROCESSOR_CORE2:
1349 case PROCESSOR_COREI7:
1350 case PROCESSOR_L1OM:
1351 case PROCESSOR_K1OM:
1352 case PROCESSOR_GENERIC64:
1353 case PROCESSOR_K6:
1354 case PROCESSOR_ATHLON:
1355 case PROCESSOR_K8:
1356 case PROCESSOR_AMDFAM10:
1357 case PROCESSOR_BD:
1358 case PROCESSOR_ZNVER:
1359 case PROCESSOR_BT:
1360 patt = alt_patt;
1361 break;
1362 case PROCESSOR_I386:
1363 case PROCESSOR_I486:
1364 case PROCESSOR_PENTIUM:
1365 case PROCESSOR_PENTIUMPRO:
1366 case PROCESSOR_IAMCU:
1367 case PROCESSOR_GENERIC32:
1368 patt = f32_patt;
1369 break;
1370 }
1371 }
1372 else
1373 {
1374 switch (fragP->tc_frag_data.tune)
1375 {
1376 case PROCESSOR_UNKNOWN:
1377 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1378 PROCESSOR_UNKNOWN. */
1379 abort ();
1380 break;
1381
1382 case PROCESSOR_I386:
1383 case PROCESSOR_I486:
1384 case PROCESSOR_PENTIUM:
1385 case PROCESSOR_IAMCU:
1386 case PROCESSOR_K6:
1387 case PROCESSOR_ATHLON:
1388 case PROCESSOR_K8:
1389 case PROCESSOR_AMDFAM10:
1390 case PROCESSOR_BD:
1391 case PROCESSOR_ZNVER:
1392 case PROCESSOR_BT:
1393 case PROCESSOR_GENERIC32:
1394 /* We use cpu_arch_isa_flags to check if we CAN optimize
1395 with nops. */
1396 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1397 patt = alt_patt;
1398 else
1399 patt = f32_patt;
1400 break;
1401 case PROCESSOR_PENTIUMPRO:
1402 case PROCESSOR_PENTIUM4:
1403 case PROCESSOR_NOCONA:
1404 case PROCESSOR_CORE:
1405 case PROCESSOR_CORE2:
1406 case PROCESSOR_COREI7:
1407 case PROCESSOR_L1OM:
1408 case PROCESSOR_K1OM:
1409 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1410 patt = alt_patt;
1411 else
1412 patt = f32_patt;
1413 break;
1414 case PROCESSOR_GENERIC64:
1415 patt = alt_patt;
1416 break;
1417 }
1418 }
1419
1420 if (patt == f32_patt)
1421 {
1422 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1423 /* Limit number of NOPs to 2 for older processors. */
1424 max_number_of_nops = 2;
1425 }
1426 else
1427 {
1428 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1429 /* Limit number of NOPs to 7 for newer processors. */
1430 max_number_of_nops = 7;
1431 }
1432 }
1433
1434 if (limit == 0)
1435 limit = max_single_nop_size;
1436
1437 if (fragP->fr_type == rs_fill_nop)
1438 {
1439 /* Output NOPs for .nop directive. */
1440 if (limit > max_single_nop_size)
1441 {
1442 as_bad_where (fragP->fr_file, fragP->fr_line,
1443 _("invalid single nop size: %d "
1444 "(expect within [0, %d])"),
1445 limit, max_single_nop_size);
1446 return;
1447 }
1448 }
1449 else
1450 fragP->fr_var = count;
1451
1452 if ((count / max_single_nop_size) > max_number_of_nops)
1453 {
1454 /* Generate jump over NOPs. */
1455 offsetT disp = count - 2;
1456 if (fits_in_imm7 (disp))
1457 {
1458 /* Use "jmp disp8" if possible. */
1459 count = disp;
1460 where[0] = jump_disp8[0];
1461 where[1] = count;
1462 where += 2;
1463 }
1464 else
1465 {
1466 unsigned int size_of_jump;
1467
1468 if (flag_code == CODE_16BIT)
1469 {
1470 where[0] = jump16_disp32[0];
1471 where[1] = jump16_disp32[1];
1472 size_of_jump = 2;
1473 }
1474 else
1475 {
1476 where[0] = jump32_disp32[0];
1477 size_of_jump = 1;
1478 }
1479
1480 count -= size_of_jump + 4;
1481 if (!fits_in_imm31 (count))
1482 {
1483 as_bad_where (fragP->fr_file, fragP->fr_line,
1484 _("jump over nop padding out of range"));
1485 return;
1486 }
1487
1488 md_number_to_chars (where + size_of_jump, count, 4);
1489 where += size_of_jump + 4;
1490 }
1491 }
1492
1493 /* Generate multiple NOPs. */
1494 i386_output_nops (where, patt, count, limit);
1495 }
1496
1497 static INLINE int
1498 operand_type_all_zero (const union i386_operand_type *x)
1499 {
1500 switch (ARRAY_SIZE(x->array))
1501 {
1502 case 3:
1503 if (x->array[2])
1504 return 0;
1505 /* Fall through. */
1506 case 2:
1507 if (x->array[1])
1508 return 0;
1509 /* Fall through. */
1510 case 1:
1511 return !x->array[0];
1512 default:
1513 abort ();
1514 }
1515 }
1516
1517 static INLINE void
1518 operand_type_set (union i386_operand_type *x, unsigned int v)
1519 {
1520 switch (ARRAY_SIZE(x->array))
1521 {
1522 case 3:
1523 x->array[2] = v;
1524 /* Fall through. */
1525 case 2:
1526 x->array[1] = v;
1527 /* Fall through. */
1528 case 1:
1529 x->array[0] = v;
1530 /* Fall through. */
1531 break;
1532 default:
1533 abort ();
1534 }
1535 }
1536
1537 static INLINE int
1538 operand_type_equal (const union i386_operand_type *x,
1539 const union i386_operand_type *y)
1540 {
1541 switch (ARRAY_SIZE(x->array))
1542 {
1543 case 3:
1544 if (x->array[2] != y->array[2])
1545 return 0;
1546 /* Fall through. */
1547 case 2:
1548 if (x->array[1] != y->array[1])
1549 return 0;
1550 /* Fall through. */
1551 case 1:
1552 return x->array[0] == y->array[0];
1553 break;
1554 default:
1555 abort ();
1556 }
1557 }
1558
1559 static INLINE int
1560 cpu_flags_all_zero (const union i386_cpu_flags *x)
1561 {
1562 switch (ARRAY_SIZE(x->array))
1563 {
1564 case 4:
1565 if (x->array[3])
1566 return 0;
1567 /* Fall through. */
1568 case 3:
1569 if (x->array[2])
1570 return 0;
1571 /* Fall through. */
1572 case 2:
1573 if (x->array[1])
1574 return 0;
1575 /* Fall through. */
1576 case 1:
1577 return !x->array[0];
1578 default:
1579 abort ();
1580 }
1581 }
1582
1583 static INLINE int
1584 cpu_flags_equal (const union i386_cpu_flags *x,
1585 const union i386_cpu_flags *y)
1586 {
1587 switch (ARRAY_SIZE(x->array))
1588 {
1589 case 4:
1590 if (x->array[3] != y->array[3])
1591 return 0;
1592 /* Fall through. */
1593 case 3:
1594 if (x->array[2] != y->array[2])
1595 return 0;
1596 /* Fall through. */
1597 case 2:
1598 if (x->array[1] != y->array[1])
1599 return 0;
1600 /* Fall through. */
1601 case 1:
1602 return x->array[0] == y->array[0];
1603 break;
1604 default:
1605 abort ();
1606 }
1607 }
1608
1609 static INLINE int
1610 cpu_flags_check_cpu64 (i386_cpu_flags f)
1611 {
1612 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1613 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1614 }
1615
1616 static INLINE i386_cpu_flags
1617 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1618 {
1619 switch (ARRAY_SIZE (x.array))
1620 {
1621 case 4:
1622 x.array [3] &= y.array [3];
1623 /* Fall through. */
1624 case 3:
1625 x.array [2] &= y.array [2];
1626 /* Fall through. */
1627 case 2:
1628 x.array [1] &= y.array [1];
1629 /* Fall through. */
1630 case 1:
1631 x.array [0] &= y.array [0];
1632 break;
1633 default:
1634 abort ();
1635 }
1636 return x;
1637 }
1638
1639 static INLINE i386_cpu_flags
1640 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1641 {
1642 switch (ARRAY_SIZE (x.array))
1643 {
1644 case 4:
1645 x.array [3] |= y.array [3];
1646 /* Fall through. */
1647 case 3:
1648 x.array [2] |= y.array [2];
1649 /* Fall through. */
1650 case 2:
1651 x.array [1] |= y.array [1];
1652 /* Fall through. */
1653 case 1:
1654 x.array [0] |= y.array [0];
1655 break;
1656 default:
1657 abort ();
1658 }
1659 return x;
1660 }
1661
1662 static INLINE i386_cpu_flags
1663 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1664 {
1665 switch (ARRAY_SIZE (x.array))
1666 {
1667 case 4:
1668 x.array [3] &= ~y.array [3];
1669 /* Fall through. */
1670 case 3:
1671 x.array [2] &= ~y.array [2];
1672 /* Fall through. */
1673 case 2:
1674 x.array [1] &= ~y.array [1];
1675 /* Fall through. */
1676 case 1:
1677 x.array [0] &= ~y.array [0];
1678 break;
1679 default:
1680 abort ();
1681 }
1682 return x;
1683 }
1684
1685 #define CPU_FLAGS_ARCH_MATCH 0x1
1686 #define CPU_FLAGS_64BIT_MATCH 0x2
1687
1688 #define CPU_FLAGS_PERFECT_MATCH \
1689 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1690
1691 /* Return CPU flags match bits. */
1692
1693 static int
1694 cpu_flags_match (const insn_template *t)
1695 {
1696 i386_cpu_flags x = t->cpu_flags;
1697 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1698
1699 x.bitfield.cpu64 = 0;
1700 x.bitfield.cpuno64 = 0;
1701
1702 if (cpu_flags_all_zero (&x))
1703 {
1704 /* This instruction is available on all archs. */
1705 match |= CPU_FLAGS_ARCH_MATCH;
1706 }
1707 else
1708 {
1709 /* This instruction is available only on some archs. */
1710 i386_cpu_flags cpu = cpu_arch_flags;
1711
1712 /* AVX512VL is no standalone feature - match it and then strip it. */
1713 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1714 return match;
1715 x.bitfield.cpuavx512vl = 0;
1716
1717 cpu = cpu_flags_and (x, cpu);
1718 if (!cpu_flags_all_zero (&cpu))
1719 {
1720 if (x.bitfield.cpuavx)
1721 {
1722 /* We need to check a few extra flags with AVX. */
1723 if (cpu.bitfield.cpuavx
1724 && (!t->opcode_modifier.sse2avx || sse2avx)
1725 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1726 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1727 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1728 match |= CPU_FLAGS_ARCH_MATCH;
1729 }
1730 else if (x.bitfield.cpuavx512f)
1731 {
1732 /* We need to check a few extra flags with AVX512F. */
1733 if (cpu.bitfield.cpuavx512f
1734 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1735 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1736 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1737 match |= CPU_FLAGS_ARCH_MATCH;
1738 }
1739 else
1740 match |= CPU_FLAGS_ARCH_MATCH;
1741 }
1742 }
1743 return match;
1744 }
1745
1746 static INLINE i386_operand_type
1747 operand_type_and (i386_operand_type x, i386_operand_type y)
1748 {
1749 switch (ARRAY_SIZE (x.array))
1750 {
1751 case 3:
1752 x.array [2] &= y.array [2];
1753 /* Fall through. */
1754 case 2:
1755 x.array [1] &= y.array [1];
1756 /* Fall through. */
1757 case 1:
1758 x.array [0] &= y.array [0];
1759 break;
1760 default:
1761 abort ();
1762 }
1763 return x;
1764 }
1765
1766 static INLINE i386_operand_type
1767 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1768 {
1769 switch (ARRAY_SIZE (x.array))
1770 {
1771 case 3:
1772 x.array [2] &= ~y.array [2];
1773 /* Fall through. */
1774 case 2:
1775 x.array [1] &= ~y.array [1];
1776 /* Fall through. */
1777 case 1:
1778 x.array [0] &= ~y.array [0];
1779 break;
1780 default:
1781 abort ();
1782 }
1783 return x;
1784 }
1785
1786 static INLINE i386_operand_type
1787 operand_type_or (i386_operand_type x, i386_operand_type y)
1788 {
1789 switch (ARRAY_SIZE (x.array))
1790 {
1791 case 3:
1792 x.array [2] |= y.array [2];
1793 /* Fall through. */
1794 case 2:
1795 x.array [1] |= y.array [1];
1796 /* Fall through. */
1797 case 1:
1798 x.array [0] |= y.array [0];
1799 break;
1800 default:
1801 abort ();
1802 }
1803 return x;
1804 }
1805
1806 static INLINE i386_operand_type
1807 operand_type_xor (i386_operand_type x, i386_operand_type y)
1808 {
1809 switch (ARRAY_SIZE (x.array))
1810 {
1811 case 3:
1812 x.array [2] ^= y.array [2];
1813 /* Fall through. */
1814 case 2:
1815 x.array [1] ^= y.array [1];
1816 /* Fall through. */
1817 case 1:
1818 x.array [0] ^= y.array [0];
1819 break;
1820 default:
1821 abort ();
1822 }
1823 return x;
1824 }
1825
1826 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1827 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1828 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1829 static const i386_operand_type inoutportreg
1830 = OPERAND_TYPE_INOUTPORTREG;
1831 static const i386_operand_type reg16_inoutportreg
1832 = OPERAND_TYPE_REG16_INOUTPORTREG;
1833 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1834 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1835 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1836 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1837 static const i386_operand_type anydisp
1838 = OPERAND_TYPE_ANYDISP;
1839 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1840 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1841 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1842 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1843 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1844 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1845 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1846 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1847 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1848 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1849 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1850 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1851
1852 enum operand_type
1853 {
1854 reg,
1855 imm,
1856 disp,
1857 anymem
1858 };
1859
1860 static INLINE int
1861 operand_type_check (i386_operand_type t, enum operand_type c)
1862 {
1863 switch (c)
1864 {
1865 case reg:
1866 return t.bitfield.reg;
1867
1868 case imm:
1869 return (t.bitfield.imm8
1870 || t.bitfield.imm8s
1871 || t.bitfield.imm16
1872 || t.bitfield.imm32
1873 || t.bitfield.imm32s
1874 || t.bitfield.imm64);
1875
1876 case disp:
1877 return (t.bitfield.disp8
1878 || t.bitfield.disp16
1879 || t.bitfield.disp32
1880 || t.bitfield.disp32s
1881 || t.bitfield.disp64);
1882
1883 case anymem:
1884 return (t.bitfield.disp8
1885 || t.bitfield.disp16
1886 || t.bitfield.disp32
1887 || t.bitfield.disp32s
1888 || t.bitfield.disp64
1889 || t.bitfield.baseindex);
1890
1891 default:
1892 abort ();
1893 }
1894
1895 return 0;
1896 }
1897
1898 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1899 operand J for instruction template T. */
1900
1901 static INLINE int
1902 match_reg_size (const insn_template *t, unsigned int j)
1903 {
1904 return !((i.types[j].bitfield.byte
1905 && !t->operand_types[j].bitfield.byte)
1906 || (i.types[j].bitfield.word
1907 && !t->operand_types[j].bitfield.word)
1908 || (i.types[j].bitfield.dword
1909 && !t->operand_types[j].bitfield.dword)
1910 || (i.types[j].bitfield.qword
1911 && !t->operand_types[j].bitfield.qword)
1912 || (i.types[j].bitfield.tbyte
1913 && !t->operand_types[j].bitfield.tbyte));
1914 }
1915
1916 /* Return 1 if there is no conflict in SIMD register on
1917 operand J for instruction template T. */
1918
1919 static INLINE int
1920 match_simd_size (const insn_template *t, unsigned int j)
1921 {
1922 return !((i.types[j].bitfield.xmmword
1923 && !t->operand_types[j].bitfield.xmmword)
1924 || (i.types[j].bitfield.ymmword
1925 && !t->operand_types[j].bitfield.ymmword)
1926 || (i.types[j].bitfield.zmmword
1927 && !t->operand_types[j].bitfield.zmmword));
1928 }
1929
1930 /* Return 1 if there is no conflict in any size on operand J for
1931 instruction template T. */
1932
1933 static INLINE int
1934 match_mem_size (const insn_template *t, unsigned int j)
1935 {
1936 return (match_reg_size (t, j)
1937 && !((i.types[j].bitfield.unspecified
1938 && !i.broadcast
1939 && !t->operand_types[j].bitfield.unspecified)
1940 || (i.types[j].bitfield.fword
1941 && !t->operand_types[j].bitfield.fword)
1942 /* For scalar opcode templates to allow register and memory
1943 operands at the same time, some special casing is needed
1944 here. */
1945 || ((t->operand_types[j].bitfield.regsimd
1946 && !t->opcode_modifier.broadcast
1947 && (t->operand_types[j].bitfield.dword
1948 || t->operand_types[j].bitfield.qword))
1949 ? (i.types[j].bitfield.xmmword
1950 || i.types[j].bitfield.ymmword
1951 || i.types[j].bitfield.zmmword)
1952 : !match_simd_size(t, j))));
1953 }
1954
1955 /* Return 1 if there is no size conflict on any operands for
1956 instruction template T. */
1957
1958 static INLINE int
1959 operand_size_match (const insn_template *t)
1960 {
1961 unsigned int j;
1962 int match = 1;
1963
1964 /* Don't check jump instructions. */
1965 if (t->opcode_modifier.jump
1966 || t->opcode_modifier.jumpbyte
1967 || t->opcode_modifier.jumpdword
1968 || t->opcode_modifier.jumpintersegment)
1969 return match;
1970
1971 /* Check memory and accumulator operand size. */
1972 for (j = 0; j < i.operands; j++)
1973 {
1974 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1975 && t->operand_types[j].bitfield.anysize)
1976 continue;
1977
1978 if (t->operand_types[j].bitfield.reg
1979 && !match_reg_size (t, j))
1980 {
1981 match = 0;
1982 break;
1983 }
1984
1985 if (t->operand_types[j].bitfield.regsimd
1986 && !match_simd_size (t, j))
1987 {
1988 match = 0;
1989 break;
1990 }
1991
1992 if (t->operand_types[j].bitfield.acc
1993 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
1994 {
1995 match = 0;
1996 break;
1997 }
1998
1999 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
2000 {
2001 match = 0;
2002 break;
2003 }
2004 }
2005
2006 if (match)
2007 return match;
2008 else if (!t->opcode_modifier.d)
2009 {
2010 mismatch:
2011 i.error = operand_size_mismatch;
2012 return 0;
2013 }
2014
2015 /* Check reverse. */
2016 gas_assert (i.operands == 2);
2017
2018 match = 1;
2019 for (j = 0; j < 2; j++)
2020 {
2021 if ((t->operand_types[j].bitfield.reg
2022 || t->operand_types[j].bitfield.acc)
2023 && !match_reg_size (t, j ? 0 : 1))
2024 goto mismatch;
2025
2026 if (i.types[j].bitfield.mem
2027 && !match_mem_size (t, j ? 0 : 1))
2028 goto mismatch;
2029 }
2030
2031 return match;
2032 }
2033
2034 static INLINE int
2035 operand_type_match (i386_operand_type overlap,
2036 i386_operand_type given)
2037 {
2038 i386_operand_type temp = overlap;
2039
2040 temp.bitfield.jumpabsolute = 0;
2041 temp.bitfield.unspecified = 0;
2042 temp.bitfield.byte = 0;
2043 temp.bitfield.word = 0;
2044 temp.bitfield.dword = 0;
2045 temp.bitfield.fword = 0;
2046 temp.bitfield.qword = 0;
2047 temp.bitfield.tbyte = 0;
2048 temp.bitfield.xmmword = 0;
2049 temp.bitfield.ymmword = 0;
2050 temp.bitfield.zmmword = 0;
2051 if (operand_type_all_zero (&temp))
2052 goto mismatch;
2053
2054 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2055 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2056 return 1;
2057
2058 mismatch:
2059 i.error = operand_type_mismatch;
2060 return 0;
2061 }
2062
2063 /* If given types g0 and g1 are registers they must be of the same type
2064 unless the expected operand type register overlap is null.
2065 Memory operand size of certain SIMD instructions is also being checked
2066 here. */
2067
2068 static INLINE int
2069 operand_type_register_match (i386_operand_type g0,
2070 i386_operand_type t0,
2071 i386_operand_type g1,
2072 i386_operand_type t1)
2073 {
2074 if (!g0.bitfield.reg
2075 && !g0.bitfield.regsimd
2076 && (!operand_type_check (g0, anymem)
2077 || g0.bitfield.unspecified
2078 || !t0.bitfield.regsimd))
2079 return 1;
2080
2081 if (!g1.bitfield.reg
2082 && !g1.bitfield.regsimd
2083 && (!operand_type_check (g1, anymem)
2084 || g1.bitfield.unspecified
2085 || !t1.bitfield.regsimd))
2086 return 1;
2087
2088 if (g0.bitfield.byte == g1.bitfield.byte
2089 && g0.bitfield.word == g1.bitfield.word
2090 && g0.bitfield.dword == g1.bitfield.dword
2091 && g0.bitfield.qword == g1.bitfield.qword
2092 && g0.bitfield.xmmword == g1.bitfield.xmmword
2093 && g0.bitfield.ymmword == g1.bitfield.ymmword
2094 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2095 return 1;
2096
2097 if (!(t0.bitfield.byte & t1.bitfield.byte)
2098 && !(t0.bitfield.word & t1.bitfield.word)
2099 && !(t0.bitfield.dword & t1.bitfield.dword)
2100 && !(t0.bitfield.qword & t1.bitfield.qword)
2101 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2102 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2103 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2104 return 1;
2105
2106 i.error = register_type_mismatch;
2107
2108 return 0;
2109 }
2110
2111 static INLINE unsigned int
2112 register_number (const reg_entry *r)
2113 {
2114 unsigned int nr = r->reg_num;
2115
2116 if (r->reg_flags & RegRex)
2117 nr += 8;
2118
2119 if (r->reg_flags & RegVRex)
2120 nr += 16;
2121
2122 return nr;
2123 }
2124
2125 static INLINE unsigned int
2126 mode_from_disp_size (i386_operand_type t)
2127 {
2128 if (t.bitfield.disp8)
2129 return 1;
2130 else if (t.bitfield.disp16
2131 || t.bitfield.disp32
2132 || t.bitfield.disp32s)
2133 return 2;
2134 else
2135 return 0;
2136 }
2137
2138 static INLINE int
2139 fits_in_signed_byte (addressT num)
2140 {
2141 return num + 0x80 <= 0xff;
2142 }
2143
2144 static INLINE int
2145 fits_in_unsigned_byte (addressT num)
2146 {
2147 return num <= 0xff;
2148 }
2149
2150 static INLINE int
2151 fits_in_unsigned_word (addressT num)
2152 {
2153 return num <= 0xffff;
2154 }
2155
2156 static INLINE int
2157 fits_in_signed_word (addressT num)
2158 {
2159 return num + 0x8000 <= 0xffff;
2160 }
2161
2162 static INLINE int
2163 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2164 {
2165 #ifndef BFD64
2166 return 1;
2167 #else
2168 return num + 0x80000000 <= 0xffffffff;
2169 #endif
2170 } /* fits_in_signed_long() */
2171
2172 static INLINE int
2173 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2174 {
2175 #ifndef BFD64
2176 return 1;
2177 #else
2178 return num <= 0xffffffff;
2179 #endif
2180 } /* fits_in_unsigned_long() */
2181
2182 static INLINE int
2183 fits_in_disp8 (offsetT num)
2184 {
2185 int shift = i.memshift;
2186 unsigned int mask;
2187
2188 if (shift == -1)
2189 abort ();
2190
2191 mask = (1 << shift) - 1;
2192
2193 /* Return 0 if NUM isn't properly aligned. */
2194 if ((num & mask))
2195 return 0;
2196
2197 /* Check if NUM will fit in 8bit after shift. */
2198 return fits_in_signed_byte (num >> shift);
2199 }
2200
2201 static INLINE int
2202 fits_in_imm4 (offsetT num)
2203 {
2204 return (num & 0xf) == num;
2205 }
2206
2207 static i386_operand_type
2208 smallest_imm_type (offsetT num)
2209 {
2210 i386_operand_type t;
2211
2212 operand_type_set (&t, 0);
2213 t.bitfield.imm64 = 1;
2214
2215 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2216 {
2217 /* This code is disabled on the 486 because all the Imm1 forms
2218 in the opcode table are slower on the i486. They're the
2219 versions with the implicitly specified single-position
2220 displacement, which has another syntax if you really want to
2221 use that form. */
2222 t.bitfield.imm1 = 1;
2223 t.bitfield.imm8 = 1;
2224 t.bitfield.imm8s = 1;
2225 t.bitfield.imm16 = 1;
2226 t.bitfield.imm32 = 1;
2227 t.bitfield.imm32s = 1;
2228 }
2229 else if (fits_in_signed_byte (num))
2230 {
2231 t.bitfield.imm8 = 1;
2232 t.bitfield.imm8s = 1;
2233 t.bitfield.imm16 = 1;
2234 t.bitfield.imm32 = 1;
2235 t.bitfield.imm32s = 1;
2236 }
2237 else if (fits_in_unsigned_byte (num))
2238 {
2239 t.bitfield.imm8 = 1;
2240 t.bitfield.imm16 = 1;
2241 t.bitfield.imm32 = 1;
2242 t.bitfield.imm32s = 1;
2243 }
2244 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2245 {
2246 t.bitfield.imm16 = 1;
2247 t.bitfield.imm32 = 1;
2248 t.bitfield.imm32s = 1;
2249 }
2250 else if (fits_in_signed_long (num))
2251 {
2252 t.bitfield.imm32 = 1;
2253 t.bitfield.imm32s = 1;
2254 }
2255 else if (fits_in_unsigned_long (num))
2256 t.bitfield.imm32 = 1;
2257
2258 return t;
2259 }
2260
2261 static offsetT
2262 offset_in_range (offsetT val, int size)
2263 {
2264 addressT mask;
2265
2266 switch (size)
2267 {
2268 case 1: mask = ((addressT) 1 << 8) - 1; break;
2269 case 2: mask = ((addressT) 1 << 16) - 1; break;
2270 case 4: mask = ((addressT) 2 << 31) - 1; break;
2271 #ifdef BFD64
2272 case 8: mask = ((addressT) 2 << 63) - 1; break;
2273 #endif
2274 default: abort ();
2275 }
2276
2277 #ifdef BFD64
2278 /* If BFD64, sign extend val for 32bit address mode. */
2279 if (flag_code != CODE_64BIT
2280 || i.prefix[ADDR_PREFIX])
2281 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2282 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2283 #endif
2284
2285 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2286 {
2287 char buf1[40], buf2[40];
2288
2289 sprint_value (buf1, val);
2290 sprint_value (buf2, val & mask);
2291 as_warn (_("%s shortened to %s"), buf1, buf2);
2292 }
2293 return val & mask;
2294 }
2295
2296 enum PREFIX_GROUP
2297 {
2298 PREFIX_EXIST = 0,
2299 PREFIX_LOCK,
2300 PREFIX_REP,
2301 PREFIX_DS,
2302 PREFIX_OTHER
2303 };
2304
2305 /* Returns
2306 a. PREFIX_EXIST if attempting to add a prefix where one from the
2307 same class already exists.
2308 b. PREFIX_LOCK if lock prefix is added.
2309 c. PREFIX_REP if rep/repne prefix is added.
2310 d. PREFIX_DS if ds prefix is added.
2311 e. PREFIX_OTHER if other prefix is added.
2312 */
2313
2314 static enum PREFIX_GROUP
2315 add_prefix (unsigned int prefix)
2316 {
2317 enum PREFIX_GROUP ret = PREFIX_OTHER;
2318 unsigned int q;
2319
2320 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2321 && flag_code == CODE_64BIT)
2322 {
2323 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2324 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2325 && (prefix & (REX_R | REX_X | REX_B))))
2326 ret = PREFIX_EXIST;
2327 q = REX_PREFIX;
2328 }
2329 else
2330 {
2331 switch (prefix)
2332 {
2333 default:
2334 abort ();
2335
2336 case DS_PREFIX_OPCODE:
2337 ret = PREFIX_DS;
2338 /* Fall through. */
2339 case CS_PREFIX_OPCODE:
2340 case ES_PREFIX_OPCODE:
2341 case FS_PREFIX_OPCODE:
2342 case GS_PREFIX_OPCODE:
2343 case SS_PREFIX_OPCODE:
2344 q = SEG_PREFIX;
2345 break;
2346
2347 case REPNE_PREFIX_OPCODE:
2348 case REPE_PREFIX_OPCODE:
2349 q = REP_PREFIX;
2350 ret = PREFIX_REP;
2351 break;
2352
2353 case LOCK_PREFIX_OPCODE:
2354 q = LOCK_PREFIX;
2355 ret = PREFIX_LOCK;
2356 break;
2357
2358 case FWAIT_OPCODE:
2359 q = WAIT_PREFIX;
2360 break;
2361
2362 case ADDR_PREFIX_OPCODE:
2363 q = ADDR_PREFIX;
2364 break;
2365
2366 case DATA_PREFIX_OPCODE:
2367 q = DATA_PREFIX;
2368 break;
2369 }
2370 if (i.prefix[q] != 0)
2371 ret = PREFIX_EXIST;
2372 }
2373
2374 if (ret)
2375 {
2376 if (!i.prefix[q])
2377 ++i.prefixes;
2378 i.prefix[q] |= prefix;
2379 }
2380 else
2381 as_bad (_("same type of prefix used twice"));
2382
2383 return ret;
2384 }
2385
2386 static void
2387 update_code_flag (int value, int check)
2388 {
2389 PRINTF_LIKE ((*as_error));
2390
2391 flag_code = (enum flag_code) value;
2392 if (flag_code == CODE_64BIT)
2393 {
2394 cpu_arch_flags.bitfield.cpu64 = 1;
2395 cpu_arch_flags.bitfield.cpuno64 = 0;
2396 }
2397 else
2398 {
2399 cpu_arch_flags.bitfield.cpu64 = 0;
2400 cpu_arch_flags.bitfield.cpuno64 = 1;
2401 }
2402 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2403 {
2404 if (check)
2405 as_error = as_fatal;
2406 else
2407 as_error = as_bad;
2408 (*as_error) (_("64bit mode not supported on `%s'."),
2409 cpu_arch_name ? cpu_arch_name : default_arch);
2410 }
2411 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2412 {
2413 if (check)
2414 as_error = as_fatal;
2415 else
2416 as_error = as_bad;
2417 (*as_error) (_("32bit mode not supported on `%s'."),
2418 cpu_arch_name ? cpu_arch_name : default_arch);
2419 }
2420 stackop_size = '\0';
2421 }
2422
2423 static void
2424 set_code_flag (int value)
2425 {
2426 update_code_flag (value, 0);
2427 }
2428
2429 static void
2430 set_16bit_gcc_code_flag (int new_code_flag)
2431 {
2432 flag_code = (enum flag_code) new_code_flag;
2433 if (flag_code != CODE_16BIT)
2434 abort ();
2435 cpu_arch_flags.bitfield.cpu64 = 0;
2436 cpu_arch_flags.bitfield.cpuno64 = 1;
2437 stackop_size = LONG_MNEM_SUFFIX;
2438 }
2439
2440 static void
2441 set_intel_syntax (int syntax_flag)
2442 {
2443 /* Find out if register prefixing is specified. */
2444 int ask_naked_reg = 0;
2445
2446 SKIP_WHITESPACE ();
2447 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2448 {
2449 char *string;
2450 int e = get_symbol_name (&string);
2451
2452 if (strcmp (string, "prefix") == 0)
2453 ask_naked_reg = 1;
2454 else if (strcmp (string, "noprefix") == 0)
2455 ask_naked_reg = -1;
2456 else
2457 as_bad (_("bad argument to syntax directive."));
2458 (void) restore_line_pointer (e);
2459 }
2460 demand_empty_rest_of_line ();
2461
2462 intel_syntax = syntax_flag;
2463
2464 if (ask_naked_reg == 0)
2465 allow_naked_reg = (intel_syntax
2466 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2467 else
2468 allow_naked_reg = (ask_naked_reg < 0);
2469
2470 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2471
2472 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2473 identifier_chars['$'] = intel_syntax ? '$' : 0;
2474 register_prefix = allow_naked_reg ? "" : "%";
2475 }
2476
2477 static void
2478 set_intel_mnemonic (int mnemonic_flag)
2479 {
2480 intel_mnemonic = mnemonic_flag;
2481 }
2482
2483 static void
2484 set_allow_index_reg (int flag)
2485 {
2486 allow_index_reg = flag;
2487 }
2488
2489 static void
2490 set_check (int what)
2491 {
2492 enum check_kind *kind;
2493 const char *str;
2494
2495 if (what)
2496 {
2497 kind = &operand_check;
2498 str = "operand";
2499 }
2500 else
2501 {
2502 kind = &sse_check;
2503 str = "sse";
2504 }
2505
2506 SKIP_WHITESPACE ();
2507
2508 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2509 {
2510 char *string;
2511 int e = get_symbol_name (&string);
2512
2513 if (strcmp (string, "none") == 0)
2514 *kind = check_none;
2515 else if (strcmp (string, "warning") == 0)
2516 *kind = check_warning;
2517 else if (strcmp (string, "error") == 0)
2518 *kind = check_error;
2519 else
2520 as_bad (_("bad argument to %s_check directive."), str);
2521 (void) restore_line_pointer (e);
2522 }
2523 else
2524 as_bad (_("missing argument for %s_check directive"), str);
2525
2526 demand_empty_rest_of_line ();
2527 }
2528
2529 static void
2530 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2531 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2532 {
2533 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2534 static const char *arch;
2535
2536 /* Intel LIOM is only supported on ELF. */
2537 if (!IS_ELF)
2538 return;
2539
2540 if (!arch)
2541 {
2542 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2543 use default_arch. */
2544 arch = cpu_arch_name;
2545 if (!arch)
2546 arch = default_arch;
2547 }
2548
2549 /* If we are targeting Intel MCU, we must enable it. */
2550 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2551 || new_flag.bitfield.cpuiamcu)
2552 return;
2553
2554 /* If we are targeting Intel L1OM, we must enable it. */
2555 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2556 || new_flag.bitfield.cpul1om)
2557 return;
2558
2559 /* If we are targeting Intel K1OM, we must enable it. */
2560 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2561 || new_flag.bitfield.cpuk1om)
2562 return;
2563
2564 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2565 #endif
2566 }
2567
2568 static void
2569 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2570 {
2571 SKIP_WHITESPACE ();
2572
2573 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2574 {
2575 char *string;
2576 int e = get_symbol_name (&string);
2577 unsigned int j;
2578 i386_cpu_flags flags;
2579
2580 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2581 {
2582 if (strcmp (string, cpu_arch[j].name) == 0)
2583 {
2584 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2585
2586 if (*string != '.')
2587 {
2588 cpu_arch_name = cpu_arch[j].name;
2589 cpu_sub_arch_name = NULL;
2590 cpu_arch_flags = cpu_arch[j].flags;
2591 if (flag_code == CODE_64BIT)
2592 {
2593 cpu_arch_flags.bitfield.cpu64 = 1;
2594 cpu_arch_flags.bitfield.cpuno64 = 0;
2595 }
2596 else
2597 {
2598 cpu_arch_flags.bitfield.cpu64 = 0;
2599 cpu_arch_flags.bitfield.cpuno64 = 1;
2600 }
2601 cpu_arch_isa = cpu_arch[j].type;
2602 cpu_arch_isa_flags = cpu_arch[j].flags;
2603 if (!cpu_arch_tune_set)
2604 {
2605 cpu_arch_tune = cpu_arch_isa;
2606 cpu_arch_tune_flags = cpu_arch_isa_flags;
2607 }
2608 break;
2609 }
2610
2611 flags = cpu_flags_or (cpu_arch_flags,
2612 cpu_arch[j].flags);
2613
2614 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2615 {
2616 if (cpu_sub_arch_name)
2617 {
2618 char *name = cpu_sub_arch_name;
2619 cpu_sub_arch_name = concat (name,
2620 cpu_arch[j].name,
2621 (const char *) NULL);
2622 free (name);
2623 }
2624 else
2625 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2626 cpu_arch_flags = flags;
2627 cpu_arch_isa_flags = flags;
2628 }
2629 (void) restore_line_pointer (e);
2630 demand_empty_rest_of_line ();
2631 return;
2632 }
2633 }
2634
2635 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2636 {
2637 /* Disable an ISA extension. */
2638 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2639 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2640 {
2641 flags = cpu_flags_and_not (cpu_arch_flags,
2642 cpu_noarch[j].flags);
2643 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2644 {
2645 if (cpu_sub_arch_name)
2646 {
2647 char *name = cpu_sub_arch_name;
2648 cpu_sub_arch_name = concat (name, string,
2649 (const char *) NULL);
2650 free (name);
2651 }
2652 else
2653 cpu_sub_arch_name = xstrdup (string);
2654 cpu_arch_flags = flags;
2655 cpu_arch_isa_flags = flags;
2656 }
2657 (void) restore_line_pointer (e);
2658 demand_empty_rest_of_line ();
2659 return;
2660 }
2661
2662 j = ARRAY_SIZE (cpu_arch);
2663 }
2664
2665 if (j >= ARRAY_SIZE (cpu_arch))
2666 as_bad (_("no such architecture: `%s'"), string);
2667
2668 *input_line_pointer = e;
2669 }
2670 else
2671 as_bad (_("missing cpu architecture"));
2672
2673 no_cond_jump_promotion = 0;
2674 if (*input_line_pointer == ','
2675 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2676 {
2677 char *string;
2678 char e;
2679
2680 ++input_line_pointer;
2681 e = get_symbol_name (&string);
2682
2683 if (strcmp (string, "nojumps") == 0)
2684 no_cond_jump_promotion = 1;
2685 else if (strcmp (string, "jumps") == 0)
2686 ;
2687 else
2688 as_bad (_("no such architecture modifier: `%s'"), string);
2689
2690 (void) restore_line_pointer (e);
2691 }
2692
2693 demand_empty_rest_of_line ();
2694 }
2695
2696 enum bfd_architecture
2697 i386_arch (void)
2698 {
2699 if (cpu_arch_isa == PROCESSOR_L1OM)
2700 {
2701 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2702 || flag_code != CODE_64BIT)
2703 as_fatal (_("Intel L1OM is 64bit ELF only"));
2704 return bfd_arch_l1om;
2705 }
2706 else if (cpu_arch_isa == PROCESSOR_K1OM)
2707 {
2708 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2709 || flag_code != CODE_64BIT)
2710 as_fatal (_("Intel K1OM is 64bit ELF only"));
2711 return bfd_arch_k1om;
2712 }
2713 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2714 {
2715 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2716 || flag_code == CODE_64BIT)
2717 as_fatal (_("Intel MCU is 32bit ELF only"));
2718 return bfd_arch_iamcu;
2719 }
2720 else
2721 return bfd_arch_i386;
2722 }
2723
2724 unsigned long
2725 i386_mach (void)
2726 {
2727 if (!strncmp (default_arch, "x86_64", 6))
2728 {
2729 if (cpu_arch_isa == PROCESSOR_L1OM)
2730 {
2731 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2732 || default_arch[6] != '\0')
2733 as_fatal (_("Intel L1OM is 64bit ELF only"));
2734 return bfd_mach_l1om;
2735 }
2736 else if (cpu_arch_isa == PROCESSOR_K1OM)
2737 {
2738 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2739 || default_arch[6] != '\0')
2740 as_fatal (_("Intel K1OM is 64bit ELF only"));
2741 return bfd_mach_k1om;
2742 }
2743 else if (default_arch[6] == '\0')
2744 return bfd_mach_x86_64;
2745 else
2746 return bfd_mach_x64_32;
2747 }
2748 else if (!strcmp (default_arch, "i386")
2749 || !strcmp (default_arch, "iamcu"))
2750 {
2751 if (cpu_arch_isa == PROCESSOR_IAMCU)
2752 {
2753 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2754 as_fatal (_("Intel MCU is 32bit ELF only"));
2755 return bfd_mach_i386_iamcu;
2756 }
2757 else
2758 return bfd_mach_i386_i386;
2759 }
2760 else
2761 as_fatal (_("unknown architecture"));
2762 }
2763 \f
2764 void
2765 md_begin (void)
2766 {
2767 const char *hash_err;
2768
2769 /* Support pseudo prefixes like {disp32}. */
2770 lex_type ['{'] = LEX_BEGIN_NAME;
2771
2772 /* Initialize op_hash hash table. */
2773 op_hash = hash_new ();
2774
2775 {
2776 const insn_template *optab;
2777 templates *core_optab;
2778
2779 /* Setup for loop. */
2780 optab = i386_optab;
2781 core_optab = XNEW (templates);
2782 core_optab->start = optab;
2783
2784 while (1)
2785 {
2786 ++optab;
2787 if (optab->name == NULL
2788 || strcmp (optab->name, (optab - 1)->name) != 0)
2789 {
2790 /* different name --> ship out current template list;
2791 add to hash table; & begin anew. */
2792 core_optab->end = optab;
2793 hash_err = hash_insert (op_hash,
2794 (optab - 1)->name,
2795 (void *) core_optab);
2796 if (hash_err)
2797 {
2798 as_fatal (_("can't hash %s: %s"),
2799 (optab - 1)->name,
2800 hash_err);
2801 }
2802 if (optab->name == NULL)
2803 break;
2804 core_optab = XNEW (templates);
2805 core_optab->start = optab;
2806 }
2807 }
2808 }
2809
2810 /* Initialize reg_hash hash table. */
2811 reg_hash = hash_new ();
2812 {
2813 const reg_entry *regtab;
2814 unsigned int regtab_size = i386_regtab_size;
2815
2816 for (regtab = i386_regtab; regtab_size--; regtab++)
2817 {
2818 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2819 if (hash_err)
2820 as_fatal (_("can't hash %s: %s"),
2821 regtab->reg_name,
2822 hash_err);
2823 }
2824 }
2825
2826 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2827 {
2828 int c;
2829 char *p;
2830
2831 for (c = 0; c < 256; c++)
2832 {
2833 if (ISDIGIT (c))
2834 {
2835 digit_chars[c] = c;
2836 mnemonic_chars[c] = c;
2837 register_chars[c] = c;
2838 operand_chars[c] = c;
2839 }
2840 else if (ISLOWER (c))
2841 {
2842 mnemonic_chars[c] = c;
2843 register_chars[c] = c;
2844 operand_chars[c] = c;
2845 }
2846 else if (ISUPPER (c))
2847 {
2848 mnemonic_chars[c] = TOLOWER (c);
2849 register_chars[c] = mnemonic_chars[c];
2850 operand_chars[c] = c;
2851 }
2852 else if (c == '{' || c == '}')
2853 {
2854 mnemonic_chars[c] = c;
2855 operand_chars[c] = c;
2856 }
2857
2858 if (ISALPHA (c) || ISDIGIT (c))
2859 identifier_chars[c] = c;
2860 else if (c >= 128)
2861 {
2862 identifier_chars[c] = c;
2863 operand_chars[c] = c;
2864 }
2865 }
2866
2867 #ifdef LEX_AT
2868 identifier_chars['@'] = '@';
2869 #endif
2870 #ifdef LEX_QM
2871 identifier_chars['?'] = '?';
2872 operand_chars['?'] = '?';
2873 #endif
2874 digit_chars['-'] = '-';
2875 mnemonic_chars['_'] = '_';
2876 mnemonic_chars['-'] = '-';
2877 mnemonic_chars['.'] = '.';
2878 identifier_chars['_'] = '_';
2879 identifier_chars['.'] = '.';
2880
2881 for (p = operand_special_chars; *p != '\0'; p++)
2882 operand_chars[(unsigned char) *p] = *p;
2883 }
2884
2885 if (flag_code == CODE_64BIT)
2886 {
2887 #if defined (OBJ_COFF) && defined (TE_PE)
2888 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2889 ? 32 : 16);
2890 #else
2891 x86_dwarf2_return_column = 16;
2892 #endif
2893 x86_cie_data_alignment = -8;
2894 }
2895 else
2896 {
2897 x86_dwarf2_return_column = 8;
2898 x86_cie_data_alignment = -4;
2899 }
2900 }
2901
2902 void
2903 i386_print_statistics (FILE *file)
2904 {
2905 hash_print_statistics (file, "i386 opcode", op_hash);
2906 hash_print_statistics (file, "i386 register", reg_hash);
2907 }
2908 \f
2909 #ifdef DEBUG386
2910
2911 /* Debugging routines for md_assemble. */
2912 static void pte (insn_template *);
2913 static void pt (i386_operand_type);
2914 static void pe (expressionS *);
2915 static void ps (symbolS *);
2916
2917 static void
2918 pi (char *line, i386_insn *x)
2919 {
2920 unsigned int j;
2921
2922 fprintf (stdout, "%s: template ", line);
2923 pte (&x->tm);
2924 fprintf (stdout, " address: base %s index %s scale %x\n",
2925 x->base_reg ? x->base_reg->reg_name : "none",
2926 x->index_reg ? x->index_reg->reg_name : "none",
2927 x->log2_scale_factor);
2928 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2929 x->rm.mode, x->rm.reg, x->rm.regmem);
2930 fprintf (stdout, " sib: base %x index %x scale %x\n",
2931 x->sib.base, x->sib.index, x->sib.scale);
2932 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2933 (x->rex & REX_W) != 0,
2934 (x->rex & REX_R) != 0,
2935 (x->rex & REX_X) != 0,
2936 (x->rex & REX_B) != 0);
2937 for (j = 0; j < x->operands; j++)
2938 {
2939 fprintf (stdout, " #%d: ", j + 1);
2940 pt (x->types[j]);
2941 fprintf (stdout, "\n");
2942 if (x->types[j].bitfield.reg
2943 || x->types[j].bitfield.regmmx
2944 || x->types[j].bitfield.regsimd
2945 || x->types[j].bitfield.sreg2
2946 || x->types[j].bitfield.sreg3
2947 || x->types[j].bitfield.control
2948 || x->types[j].bitfield.debug
2949 || x->types[j].bitfield.test)
2950 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2951 if (operand_type_check (x->types[j], imm))
2952 pe (x->op[j].imms);
2953 if (operand_type_check (x->types[j], disp))
2954 pe (x->op[j].disps);
2955 }
2956 }
2957
2958 static void
2959 pte (insn_template *t)
2960 {
2961 unsigned int j;
2962 fprintf (stdout, " %d operands ", t->operands);
2963 fprintf (stdout, "opcode %x ", t->base_opcode);
2964 if (t->extension_opcode != None)
2965 fprintf (stdout, "ext %x ", t->extension_opcode);
2966 if (t->opcode_modifier.d)
2967 fprintf (stdout, "D");
2968 if (t->opcode_modifier.w)
2969 fprintf (stdout, "W");
2970 fprintf (stdout, "\n");
2971 for (j = 0; j < t->operands; j++)
2972 {
2973 fprintf (stdout, " #%d type ", j + 1);
2974 pt (t->operand_types[j]);
2975 fprintf (stdout, "\n");
2976 }
2977 }
2978
2979 static void
2980 pe (expressionS *e)
2981 {
2982 fprintf (stdout, " operation %d\n", e->X_op);
2983 fprintf (stdout, " add_number %ld (%lx)\n",
2984 (long) e->X_add_number, (long) e->X_add_number);
2985 if (e->X_add_symbol)
2986 {
2987 fprintf (stdout, " add_symbol ");
2988 ps (e->X_add_symbol);
2989 fprintf (stdout, "\n");
2990 }
2991 if (e->X_op_symbol)
2992 {
2993 fprintf (stdout, " op_symbol ");
2994 ps (e->X_op_symbol);
2995 fprintf (stdout, "\n");
2996 }
2997 }
2998
2999 static void
3000 ps (symbolS *s)
3001 {
3002 fprintf (stdout, "%s type %s%s",
3003 S_GET_NAME (s),
3004 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3005 segment_name (S_GET_SEGMENT (s)));
3006 }
3007
3008 static struct type_name
3009 {
3010 i386_operand_type mask;
3011 const char *name;
3012 }
3013 const type_names[] =
3014 {
3015 { OPERAND_TYPE_REG8, "r8" },
3016 { OPERAND_TYPE_REG16, "r16" },
3017 { OPERAND_TYPE_REG32, "r32" },
3018 { OPERAND_TYPE_REG64, "r64" },
3019 { OPERAND_TYPE_IMM8, "i8" },
3020 { OPERAND_TYPE_IMM8, "i8s" },
3021 { OPERAND_TYPE_IMM16, "i16" },
3022 { OPERAND_TYPE_IMM32, "i32" },
3023 { OPERAND_TYPE_IMM32S, "i32s" },
3024 { OPERAND_TYPE_IMM64, "i64" },
3025 { OPERAND_TYPE_IMM1, "i1" },
3026 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3027 { OPERAND_TYPE_DISP8, "d8" },
3028 { OPERAND_TYPE_DISP16, "d16" },
3029 { OPERAND_TYPE_DISP32, "d32" },
3030 { OPERAND_TYPE_DISP32S, "d32s" },
3031 { OPERAND_TYPE_DISP64, "d64" },
3032 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3033 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3034 { OPERAND_TYPE_CONTROL, "control reg" },
3035 { OPERAND_TYPE_TEST, "test reg" },
3036 { OPERAND_TYPE_DEBUG, "debug reg" },
3037 { OPERAND_TYPE_FLOATREG, "FReg" },
3038 { OPERAND_TYPE_FLOATACC, "FAcc" },
3039 { OPERAND_TYPE_SREG2, "SReg2" },
3040 { OPERAND_TYPE_SREG3, "SReg3" },
3041 { OPERAND_TYPE_ACC, "Acc" },
3042 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3043 { OPERAND_TYPE_REGMMX, "rMMX" },
3044 { OPERAND_TYPE_REGXMM, "rXMM" },
3045 { OPERAND_TYPE_REGYMM, "rYMM" },
3046 { OPERAND_TYPE_REGZMM, "rZMM" },
3047 { OPERAND_TYPE_REGMASK, "Mask reg" },
3048 { OPERAND_TYPE_ESSEG, "es" },
3049 };
3050
3051 static void
3052 pt (i386_operand_type t)
3053 {
3054 unsigned int j;
3055 i386_operand_type a;
3056
3057 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3058 {
3059 a = operand_type_and (t, type_names[j].mask);
3060 if (!operand_type_all_zero (&a))
3061 fprintf (stdout, "%s, ", type_names[j].name);
3062 }
3063 fflush (stdout);
3064 }
3065
3066 #endif /* DEBUG386 */
3067 \f
3068 static bfd_reloc_code_real_type
3069 reloc (unsigned int size,
3070 int pcrel,
3071 int sign,
3072 bfd_reloc_code_real_type other)
3073 {
3074 if (other != NO_RELOC)
3075 {
3076 reloc_howto_type *rel;
3077
3078 if (size == 8)
3079 switch (other)
3080 {
3081 case BFD_RELOC_X86_64_GOT32:
3082 return BFD_RELOC_X86_64_GOT64;
3083 break;
3084 case BFD_RELOC_X86_64_GOTPLT64:
3085 return BFD_RELOC_X86_64_GOTPLT64;
3086 break;
3087 case BFD_RELOC_X86_64_PLTOFF64:
3088 return BFD_RELOC_X86_64_PLTOFF64;
3089 break;
3090 case BFD_RELOC_X86_64_GOTPC32:
3091 other = BFD_RELOC_X86_64_GOTPC64;
3092 break;
3093 case BFD_RELOC_X86_64_GOTPCREL:
3094 other = BFD_RELOC_X86_64_GOTPCREL64;
3095 break;
3096 case BFD_RELOC_X86_64_TPOFF32:
3097 other = BFD_RELOC_X86_64_TPOFF64;
3098 break;
3099 case BFD_RELOC_X86_64_DTPOFF32:
3100 other = BFD_RELOC_X86_64_DTPOFF64;
3101 break;
3102 default:
3103 break;
3104 }
3105
3106 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3107 if (other == BFD_RELOC_SIZE32)
3108 {
3109 if (size == 8)
3110 other = BFD_RELOC_SIZE64;
3111 if (pcrel)
3112 {
3113 as_bad (_("there are no pc-relative size relocations"));
3114 return NO_RELOC;
3115 }
3116 }
3117 #endif
3118
3119 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3120 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3121 sign = -1;
3122
3123 rel = bfd_reloc_type_lookup (stdoutput, other);
3124 if (!rel)
3125 as_bad (_("unknown relocation (%u)"), other);
3126 else if (size != bfd_get_reloc_size (rel))
3127 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3128 bfd_get_reloc_size (rel),
3129 size);
3130 else if (pcrel && !rel->pc_relative)
3131 as_bad (_("non-pc-relative relocation for pc-relative field"));
3132 else if ((rel->complain_on_overflow == complain_overflow_signed
3133 && !sign)
3134 || (rel->complain_on_overflow == complain_overflow_unsigned
3135 && sign > 0))
3136 as_bad (_("relocated field and relocation type differ in signedness"));
3137 else
3138 return other;
3139 return NO_RELOC;
3140 }
3141
3142 if (pcrel)
3143 {
3144 if (!sign)
3145 as_bad (_("there are no unsigned pc-relative relocations"));
3146 switch (size)
3147 {
3148 case 1: return BFD_RELOC_8_PCREL;
3149 case 2: return BFD_RELOC_16_PCREL;
3150 case 4: return BFD_RELOC_32_PCREL;
3151 case 8: return BFD_RELOC_64_PCREL;
3152 }
3153 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3154 }
3155 else
3156 {
3157 if (sign > 0)
3158 switch (size)
3159 {
3160 case 4: return BFD_RELOC_X86_64_32S;
3161 }
3162 else
3163 switch (size)
3164 {
3165 case 1: return BFD_RELOC_8;
3166 case 2: return BFD_RELOC_16;
3167 case 4: return BFD_RELOC_32;
3168 case 8: return BFD_RELOC_64;
3169 }
3170 as_bad (_("cannot do %s %u byte relocation"),
3171 sign > 0 ? "signed" : "unsigned", size);
3172 }
3173
3174 return NO_RELOC;
3175 }
3176
3177 /* Here we decide which fixups can be adjusted to make them relative to
3178 the beginning of the section instead of the symbol. Basically we need
3179 to make sure that the dynamic relocations are done correctly, so in
3180 some cases we force the original symbol to be used. */
3181
3182 int
3183 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3184 {
3185 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3186 if (!IS_ELF)
3187 return 1;
3188
3189 /* Don't adjust pc-relative references to merge sections in 64-bit
3190 mode. */
3191 if (use_rela_relocations
3192 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3193 && fixP->fx_pcrel)
3194 return 0;
3195
3196 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3197 and changed later by validate_fix. */
3198 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3199 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3200 return 0;
3201
3202 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3203 for size relocations. */
3204 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3205 || fixP->fx_r_type == BFD_RELOC_SIZE64
3206 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3207 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3208 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3209 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3210 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3211 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3212 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3213 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3214 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3215 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3216 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3217 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3218 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3219 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3220 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3221 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3222 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3223 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3224 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3225 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3226 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3227 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3228 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3229 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3230 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3231 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3232 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3233 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3234 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3235 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3236 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3237 return 0;
3238 #endif
3239 return 1;
3240 }
3241
3242 static int
3243 intel_float_operand (const char *mnemonic)
3244 {
3245 /* Note that the value returned is meaningful only for opcodes with (memory)
3246 operands, hence the code here is free to improperly handle opcodes that
3247 have no operands (for better performance and smaller code). */
3248
3249 if (mnemonic[0] != 'f')
3250 return 0; /* non-math */
3251
3252 switch (mnemonic[1])
3253 {
3254 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3255 the fs segment override prefix not currently handled because no
3256 call path can make opcodes without operands get here */
3257 case 'i':
3258 return 2 /* integer op */;
3259 case 'l':
3260 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3261 return 3; /* fldcw/fldenv */
3262 break;
3263 case 'n':
3264 if (mnemonic[2] != 'o' /* fnop */)
3265 return 3; /* non-waiting control op */
3266 break;
3267 case 'r':
3268 if (mnemonic[2] == 's')
3269 return 3; /* frstor/frstpm */
3270 break;
3271 case 's':
3272 if (mnemonic[2] == 'a')
3273 return 3; /* fsave */
3274 if (mnemonic[2] == 't')
3275 {
3276 switch (mnemonic[3])
3277 {
3278 case 'c': /* fstcw */
3279 case 'd': /* fstdw */
3280 case 'e': /* fstenv */
3281 case 's': /* fsts[gw] */
3282 return 3;
3283 }
3284 }
3285 break;
3286 case 'x':
3287 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3288 return 0; /* fxsave/fxrstor are not really math ops */
3289 break;
3290 }
3291
3292 return 1;
3293 }
3294
3295 /* Build the VEX prefix. */
3296
3297 static void
3298 build_vex_prefix (const insn_template *t)
3299 {
3300 unsigned int register_specifier;
3301 unsigned int implied_prefix;
3302 unsigned int vector_length;
3303
3304 /* Check register specifier. */
3305 if (i.vex.register_specifier)
3306 {
3307 register_specifier =
3308 ~register_number (i.vex.register_specifier) & 0xf;
3309 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3310 }
3311 else
3312 register_specifier = 0xf;
3313
3314 /* Use 2-byte VEX prefix by swapping destination and source
3315 operand. */
3316 if (i.vec_encoding != vex_encoding_vex3
3317 && i.dir_encoding == dir_encoding_default
3318 && i.operands == i.reg_operands
3319 && i.tm.opcode_modifier.vexopcode == VEX0F
3320 && i.tm.opcode_modifier.load
3321 && i.rex == REX_B)
3322 {
3323 unsigned int xchg = i.operands - 1;
3324 union i386_op temp_op;
3325 i386_operand_type temp_type;
3326
3327 temp_type = i.types[xchg];
3328 i.types[xchg] = i.types[0];
3329 i.types[0] = temp_type;
3330 temp_op = i.op[xchg];
3331 i.op[xchg] = i.op[0];
3332 i.op[0] = temp_op;
3333
3334 gas_assert (i.rm.mode == 3);
3335
3336 i.rex = REX_R;
3337 xchg = i.rm.regmem;
3338 i.rm.regmem = i.rm.reg;
3339 i.rm.reg = xchg;
3340
3341 /* Use the next insn. */
3342 i.tm = t[1];
3343 }
3344
3345 if (i.tm.opcode_modifier.vex == VEXScalar)
3346 vector_length = avxscalar;
3347 else if (i.tm.opcode_modifier.vex == VEX256)
3348 vector_length = 1;
3349 else
3350 {
3351 unsigned int op;
3352
3353 vector_length = 0;
3354 for (op = 0; op < t->operands; ++op)
3355 if (t->operand_types[op].bitfield.xmmword
3356 && t->operand_types[op].bitfield.ymmword
3357 && i.types[op].bitfield.ymmword)
3358 {
3359 vector_length = 1;
3360 break;
3361 }
3362 }
3363
3364 switch ((i.tm.base_opcode >> 8) & 0xff)
3365 {
3366 case 0:
3367 implied_prefix = 0;
3368 break;
3369 case DATA_PREFIX_OPCODE:
3370 implied_prefix = 1;
3371 break;
3372 case REPE_PREFIX_OPCODE:
3373 implied_prefix = 2;
3374 break;
3375 case REPNE_PREFIX_OPCODE:
3376 implied_prefix = 3;
3377 break;
3378 default:
3379 abort ();
3380 }
3381
3382 /* Use 2-byte VEX prefix if possible. */
3383 if (i.vec_encoding != vex_encoding_vex3
3384 && i.tm.opcode_modifier.vexopcode == VEX0F
3385 && i.tm.opcode_modifier.vexw != VEXW1
3386 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3387 {
3388 /* 2-byte VEX prefix. */
3389 unsigned int r;
3390
3391 i.vex.length = 2;
3392 i.vex.bytes[0] = 0xc5;
3393
3394 /* Check the REX.R bit. */
3395 r = (i.rex & REX_R) ? 0 : 1;
3396 i.vex.bytes[1] = (r << 7
3397 | register_specifier << 3
3398 | vector_length << 2
3399 | implied_prefix);
3400 }
3401 else
3402 {
3403 /* 3-byte VEX prefix. */
3404 unsigned int m, w;
3405
3406 i.vex.length = 3;
3407
3408 switch (i.tm.opcode_modifier.vexopcode)
3409 {
3410 case VEX0F:
3411 m = 0x1;
3412 i.vex.bytes[0] = 0xc4;
3413 break;
3414 case VEX0F38:
3415 m = 0x2;
3416 i.vex.bytes[0] = 0xc4;
3417 break;
3418 case VEX0F3A:
3419 m = 0x3;
3420 i.vex.bytes[0] = 0xc4;
3421 break;
3422 case XOP08:
3423 m = 0x8;
3424 i.vex.bytes[0] = 0x8f;
3425 break;
3426 case XOP09:
3427 m = 0x9;
3428 i.vex.bytes[0] = 0x8f;
3429 break;
3430 case XOP0A:
3431 m = 0xa;
3432 i.vex.bytes[0] = 0x8f;
3433 break;
3434 default:
3435 abort ();
3436 }
3437
3438 /* The high 3 bits of the second VEX byte are 1's compliment
3439 of RXB bits from REX. */
3440 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3441
3442 /* Check the REX.W bit. */
3443 w = (i.rex & REX_W) ? 1 : 0;
3444 if (i.tm.opcode_modifier.vexw == VEXW1)
3445 w = 1;
3446
3447 i.vex.bytes[2] = (w << 7
3448 | register_specifier << 3
3449 | vector_length << 2
3450 | implied_prefix);
3451 }
3452 }
3453
3454 /* Build the EVEX prefix. */
3455
3456 static void
3457 build_evex_prefix (void)
3458 {
3459 unsigned int register_specifier;
3460 unsigned int implied_prefix;
3461 unsigned int m, w;
3462 rex_byte vrex_used = 0;
3463
3464 /* Check register specifier. */
3465 if (i.vex.register_specifier)
3466 {
3467 gas_assert ((i.vrex & REX_X) == 0);
3468
3469 register_specifier = i.vex.register_specifier->reg_num;
3470 if ((i.vex.register_specifier->reg_flags & RegRex))
3471 register_specifier += 8;
3472 /* The upper 16 registers are encoded in the fourth byte of the
3473 EVEX prefix. */
3474 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3475 i.vex.bytes[3] = 0x8;
3476 register_specifier = ~register_specifier & 0xf;
3477 }
3478 else
3479 {
3480 register_specifier = 0xf;
3481
3482 /* Encode upper 16 vector index register in the fourth byte of
3483 the EVEX prefix. */
3484 if (!(i.vrex & REX_X))
3485 i.vex.bytes[3] = 0x8;
3486 else
3487 vrex_used |= REX_X;
3488 }
3489
3490 switch ((i.tm.base_opcode >> 8) & 0xff)
3491 {
3492 case 0:
3493 implied_prefix = 0;
3494 break;
3495 case DATA_PREFIX_OPCODE:
3496 implied_prefix = 1;
3497 break;
3498 case REPE_PREFIX_OPCODE:
3499 implied_prefix = 2;
3500 break;
3501 case REPNE_PREFIX_OPCODE:
3502 implied_prefix = 3;
3503 break;
3504 default:
3505 abort ();
3506 }
3507
3508 /* 4 byte EVEX prefix. */
3509 i.vex.length = 4;
3510 i.vex.bytes[0] = 0x62;
3511
3512 /* mmmm bits. */
3513 switch (i.tm.opcode_modifier.vexopcode)
3514 {
3515 case VEX0F:
3516 m = 1;
3517 break;
3518 case VEX0F38:
3519 m = 2;
3520 break;
3521 case VEX0F3A:
3522 m = 3;
3523 break;
3524 default:
3525 abort ();
3526 break;
3527 }
3528
3529 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3530 bits from REX. */
3531 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3532
3533 /* The fifth bit of the second EVEX byte is 1's compliment of the
3534 REX_R bit in VREX. */
3535 if (!(i.vrex & REX_R))
3536 i.vex.bytes[1] |= 0x10;
3537 else
3538 vrex_used |= REX_R;
3539
3540 if ((i.reg_operands + i.imm_operands) == i.operands)
3541 {
3542 /* When all operands are registers, the REX_X bit in REX is not
3543 used. We reuse it to encode the upper 16 registers, which is
3544 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3545 as 1's compliment. */
3546 if ((i.vrex & REX_B))
3547 {
3548 vrex_used |= REX_B;
3549 i.vex.bytes[1] &= ~0x40;
3550 }
3551 }
3552
3553 /* EVEX instructions shouldn't need the REX prefix. */
3554 i.vrex &= ~vrex_used;
3555 gas_assert (i.vrex == 0);
3556
3557 /* Check the REX.W bit. */
3558 w = (i.rex & REX_W) ? 1 : 0;
3559 if (i.tm.opcode_modifier.vexw)
3560 {
3561 if (i.tm.opcode_modifier.vexw == VEXW1)
3562 w = 1;
3563 }
3564 /* If w is not set it means we are dealing with WIG instruction. */
3565 else if (!w)
3566 {
3567 if (evexwig == evexw1)
3568 w = 1;
3569 }
3570
3571 /* Encode the U bit. */
3572 implied_prefix |= 0x4;
3573
3574 /* The third byte of the EVEX prefix. */
3575 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3576
3577 /* The fourth byte of the EVEX prefix. */
3578 /* The zeroing-masking bit. */
3579 if (i.mask && i.mask->zeroing)
3580 i.vex.bytes[3] |= 0x80;
3581
3582 /* Don't always set the broadcast bit if there is no RC. */
3583 if (!i.rounding)
3584 {
3585 /* Encode the vector length. */
3586 unsigned int vec_length;
3587
3588 switch (i.tm.opcode_modifier.evex)
3589 {
3590 case EVEXLIG: /* LL' is ignored */
3591 vec_length = evexlig << 5;
3592 break;
3593 case EVEX128:
3594 vec_length = 0 << 5;
3595 break;
3596 case EVEX256:
3597 vec_length = 1 << 5;
3598 break;
3599 case EVEX512:
3600 vec_length = 2 << 5;
3601 break;
3602 default:
3603 abort ();
3604 break;
3605 }
3606 i.vex.bytes[3] |= vec_length;
3607 /* Encode the broadcast bit. */
3608 if (i.broadcast)
3609 i.vex.bytes[3] |= 0x10;
3610 }
3611 else
3612 {
3613 if (i.rounding->type != saeonly)
3614 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3615 else
3616 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3617 }
3618
3619 if (i.mask && i.mask->mask)
3620 i.vex.bytes[3] |= i.mask->mask->reg_num;
3621 }
3622
3623 static void
3624 process_immext (void)
3625 {
3626 expressionS *exp;
3627
3628 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3629 && i.operands > 0)
3630 {
3631 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3632 with an opcode suffix which is coded in the same place as an
3633 8-bit immediate field would be.
3634 Here we check those operands and remove them afterwards. */
3635 unsigned int x;
3636
3637 for (x = 0; x < i.operands; x++)
3638 if (register_number (i.op[x].regs) != x)
3639 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3640 register_prefix, i.op[x].regs->reg_name, x + 1,
3641 i.tm.name);
3642
3643 i.operands = 0;
3644 }
3645
3646 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3647 {
3648 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3649 suffix which is coded in the same place as an 8-bit immediate
3650 field would be.
3651 Here we check those operands and remove them afterwards. */
3652 unsigned int x;
3653
3654 if (i.operands != 3)
3655 abort();
3656
3657 for (x = 0; x < 2; x++)
3658 if (register_number (i.op[x].regs) != x)
3659 goto bad_register_operand;
3660
3661 /* Check for third operand for mwaitx/monitorx insn. */
3662 if (register_number (i.op[x].regs)
3663 != (x + (i.tm.extension_opcode == 0xfb)))
3664 {
3665 bad_register_operand:
3666 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3667 register_prefix, i.op[x].regs->reg_name, x+1,
3668 i.tm.name);
3669 }
3670
3671 i.operands = 0;
3672 }
3673
3674 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3675 which is coded in the same place as an 8-bit immediate field
3676 would be. Here we fake an 8-bit immediate operand from the
3677 opcode suffix stored in tm.extension_opcode.
3678
3679 AVX instructions also use this encoding, for some of
3680 3 argument instructions. */
3681
3682 gas_assert (i.imm_operands <= 1
3683 && (i.operands <= 2
3684 || ((i.tm.opcode_modifier.vex
3685 || i.tm.opcode_modifier.evex)
3686 && i.operands <= 4)));
3687
3688 exp = &im_expressions[i.imm_operands++];
3689 i.op[i.operands].imms = exp;
3690 i.types[i.operands] = imm8;
3691 i.operands++;
3692 exp->X_op = O_constant;
3693 exp->X_add_number = i.tm.extension_opcode;
3694 i.tm.extension_opcode = None;
3695 }
3696
3697
3698 static int
3699 check_hle (void)
3700 {
3701 switch (i.tm.opcode_modifier.hleprefixok)
3702 {
3703 default:
3704 abort ();
3705 case HLEPrefixNone:
3706 as_bad (_("invalid instruction `%s' after `%s'"),
3707 i.tm.name, i.hle_prefix);
3708 return 0;
3709 case HLEPrefixLock:
3710 if (i.prefix[LOCK_PREFIX])
3711 return 1;
3712 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3713 return 0;
3714 case HLEPrefixAny:
3715 return 1;
3716 case HLEPrefixRelease:
3717 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3718 {
3719 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3720 i.tm.name);
3721 return 0;
3722 }
3723 if (i.mem_operands == 0
3724 || !operand_type_check (i.types[i.operands - 1], anymem))
3725 {
3726 as_bad (_("memory destination needed for instruction `%s'"
3727 " after `xrelease'"), i.tm.name);
3728 return 0;
3729 }
3730 return 1;
3731 }
3732 }
3733
3734 /* Try the shortest encoding by shortening operand size. */
3735
3736 static void
3737 optimize_encoding (void)
3738 {
3739 int j;
3740
3741 if (optimize_for_space
3742 && i.reg_operands == 1
3743 && i.imm_operands == 1
3744 && !i.types[1].bitfield.byte
3745 && i.op[0].imms->X_op == O_constant
3746 && fits_in_imm7 (i.op[0].imms->X_add_number)
3747 && ((i.tm.base_opcode == 0xa8
3748 && i.tm.extension_opcode == None)
3749 || (i.tm.base_opcode == 0xf6
3750 && i.tm.extension_opcode == 0x0)))
3751 {
3752 /* Optimize: -Os:
3753 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3754 */
3755 unsigned int base_regnum = i.op[1].regs->reg_num;
3756 if (flag_code == CODE_64BIT || base_regnum < 4)
3757 {
3758 i.types[1].bitfield.byte = 1;
3759 /* Ignore the suffix. */
3760 i.suffix = 0;
3761 if (base_regnum >= 4
3762 && !(i.op[1].regs->reg_flags & RegRex))
3763 {
3764 /* Handle SP, BP, SI and DI registers. */
3765 if (i.types[1].bitfield.word)
3766 j = 16;
3767 else if (i.types[1].bitfield.dword)
3768 j = 32;
3769 else
3770 j = 48;
3771 i.op[1].regs -= j;
3772 }
3773 }
3774 }
3775 else if (flag_code == CODE_64BIT
3776 && ((i.reg_operands == 1
3777 && i.imm_operands == 1
3778 && i.op[0].imms->X_op == O_constant
3779 && ((i.tm.base_opcode == 0xb0
3780 && i.tm.extension_opcode == None
3781 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3782 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3783 && (((i.tm.base_opcode == 0x24
3784 || i.tm.base_opcode == 0xa8)
3785 && i.tm.extension_opcode == None)
3786 || (i.tm.base_opcode == 0x80
3787 && i.tm.extension_opcode == 0x4)
3788 || ((i.tm.base_opcode == 0xf6
3789 || i.tm.base_opcode == 0xc6)
3790 && i.tm.extension_opcode == 0x0)))))
3791 || (i.reg_operands == 2
3792 && i.op[0].regs == i.op[1].regs
3793 && ((i.tm.base_opcode == 0x30
3794 || i.tm.base_opcode == 0x28)
3795 && i.tm.extension_opcode == None)))
3796 && i.types[1].bitfield.qword)
3797 {
3798 /* Optimize: -O:
3799 andq $imm31, %r64 -> andl $imm31, %r32
3800 testq $imm31, %r64 -> testl $imm31, %r32
3801 xorq %r64, %r64 -> xorl %r32, %r32
3802 subq %r64, %r64 -> subl %r32, %r32
3803 movq $imm31, %r64 -> movl $imm31, %r32
3804 movq $imm32, %r64 -> movl $imm32, %r32
3805 */
3806 i.tm.opcode_modifier.norex64 = 1;
3807 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3808 {
3809 /* Handle
3810 movq $imm31, %r64 -> movl $imm31, %r32
3811 movq $imm32, %r64 -> movl $imm32, %r32
3812 */
3813 i.tm.operand_types[0].bitfield.imm32 = 1;
3814 i.tm.operand_types[0].bitfield.imm32s = 0;
3815 i.tm.operand_types[0].bitfield.imm64 = 0;
3816 i.types[0].bitfield.imm32 = 1;
3817 i.types[0].bitfield.imm32s = 0;
3818 i.types[0].bitfield.imm64 = 0;
3819 i.types[1].bitfield.dword = 1;
3820 i.types[1].bitfield.qword = 0;
3821 if (i.tm.base_opcode == 0xc6)
3822 {
3823 /* Handle
3824 movq $imm31, %r64 -> movl $imm31, %r32
3825 */
3826 i.tm.base_opcode = 0xb0;
3827 i.tm.extension_opcode = None;
3828 i.tm.opcode_modifier.shortform = 1;
3829 i.tm.opcode_modifier.modrm = 0;
3830 }
3831 }
3832 }
3833 else if (optimize > 1
3834 && i.reg_operands == 3
3835 && i.op[0].regs == i.op[1].regs
3836 && !i.types[2].bitfield.xmmword
3837 && (i.tm.opcode_modifier.vex
3838 || (!i.mask
3839 && !i.rounding
3840 && i.tm.opcode_modifier.evex
3841 && cpu_arch_flags.bitfield.cpuavx512vl))
3842 && ((i.tm.base_opcode == 0x55
3843 || i.tm.base_opcode == 0x6655
3844 || i.tm.base_opcode == 0x66df
3845 || i.tm.base_opcode == 0x57
3846 || i.tm.base_opcode == 0x6657
3847 || i.tm.base_opcode == 0x66ef
3848 || i.tm.base_opcode == 0x66f8
3849 || i.tm.base_opcode == 0x66f9
3850 || i.tm.base_opcode == 0x66fa
3851 || i.tm.base_opcode == 0x66fb)
3852 && i.tm.extension_opcode == None))
3853 {
3854 /* Optimize: -O2:
3855 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3856 vpsubq and vpsubw:
3857 EVEX VOP %zmmM, %zmmM, %zmmN
3858 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3859 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3860 EVEX VOP %ymmM, %ymmM, %ymmN
3861 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3862 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3863 VEX VOP %ymmM, %ymmM, %ymmN
3864 -> VEX VOP %xmmM, %xmmM, %xmmN
3865 VOP, one of vpandn and vpxor:
3866 VEX VOP %ymmM, %ymmM, %ymmN
3867 -> VEX VOP %xmmM, %xmmM, %xmmN
3868 VOP, one of vpandnd and vpandnq:
3869 EVEX VOP %zmmM, %zmmM, %zmmN
3870 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3871 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3872 EVEX VOP %ymmM, %ymmM, %ymmN
3873 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3874 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3875 VOP, one of vpxord and vpxorq:
3876 EVEX VOP %zmmM, %zmmM, %zmmN
3877 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3878 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3879 EVEX VOP %ymmM, %ymmM, %ymmN
3880 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3881 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3882 */
3883 if (i.tm.opcode_modifier.evex)
3884 {
3885 /* If only lower 16 vector registers are used, we can use
3886 VEX encoding. */
3887 for (j = 0; j < 3; j++)
3888 if (register_number (i.op[j].regs) > 15)
3889 break;
3890
3891 if (j < 3)
3892 i.tm.opcode_modifier.evex = EVEX128;
3893 else
3894 {
3895 i.tm.opcode_modifier.vex = VEX128;
3896 i.tm.opcode_modifier.vexw = VEXW0;
3897 i.tm.opcode_modifier.evex = 0;
3898 }
3899 }
3900 else
3901 i.tm.opcode_modifier.vex = VEX128;
3902
3903 if (i.tm.opcode_modifier.vex)
3904 for (j = 0; j < 3; j++)
3905 {
3906 i.types[j].bitfield.xmmword = 1;
3907 i.types[j].bitfield.ymmword = 0;
3908 }
3909 }
3910 }
3911
3912 /* This is the guts of the machine-dependent assembler. LINE points to a
3913 machine dependent instruction. This function is supposed to emit
3914 the frags/bytes it assembles to. */
3915
3916 void
3917 md_assemble (char *line)
3918 {
3919 unsigned int j;
3920 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
3921 const insn_template *t;
3922
3923 /* Initialize globals. */
3924 memset (&i, '\0', sizeof (i));
3925 for (j = 0; j < MAX_OPERANDS; j++)
3926 i.reloc[j] = NO_RELOC;
3927 memset (disp_expressions, '\0', sizeof (disp_expressions));
3928 memset (im_expressions, '\0', sizeof (im_expressions));
3929 save_stack_p = save_stack;
3930
3931 /* First parse an instruction mnemonic & call i386_operand for the operands.
3932 We assume that the scrubber has arranged it so that line[0] is the valid
3933 start of a (possibly prefixed) mnemonic. */
3934
3935 line = parse_insn (line, mnemonic);
3936 if (line == NULL)
3937 return;
3938 mnem_suffix = i.suffix;
3939
3940 line = parse_operands (line, mnemonic);
3941 this_operand = -1;
3942 xfree (i.memop1_string);
3943 i.memop1_string = NULL;
3944 if (line == NULL)
3945 return;
3946
3947 /* Now we've parsed the mnemonic into a set of templates, and have the
3948 operands at hand. */
3949
3950 /* All intel opcodes have reversed operands except for "bound" and
3951 "enter". We also don't reverse intersegment "jmp" and "call"
3952 instructions with 2 immediate operands so that the immediate segment
3953 precedes the offset, as it does when in AT&T mode. */
3954 if (intel_syntax
3955 && i.operands > 1
3956 && (strcmp (mnemonic, "bound") != 0)
3957 && (strcmp (mnemonic, "invlpga") != 0)
3958 && !(operand_type_check (i.types[0], imm)
3959 && operand_type_check (i.types[1], imm)))
3960 swap_operands ();
3961
3962 /* The order of the immediates should be reversed
3963 for 2 immediates extrq and insertq instructions */
3964 if (i.imm_operands == 2
3965 && (strcmp (mnemonic, "extrq") == 0
3966 || strcmp (mnemonic, "insertq") == 0))
3967 swap_2_operands (0, 1);
3968
3969 if (i.imm_operands)
3970 optimize_imm ();
3971
3972 /* Don't optimize displacement for movabs since it only takes 64bit
3973 displacement. */
3974 if (i.disp_operands
3975 && i.disp_encoding != disp_encoding_32bit
3976 && (flag_code != CODE_64BIT
3977 || strcmp (mnemonic, "movabs") != 0))
3978 optimize_disp ();
3979
3980 /* Next, we find a template that matches the given insn,
3981 making sure the overlap of the given operands types is consistent
3982 with the template operand types. */
3983
3984 if (!(t = match_template (mnem_suffix)))
3985 return;
3986
3987 if (sse_check != check_none
3988 && !i.tm.opcode_modifier.noavx
3989 && !i.tm.cpu_flags.bitfield.cpuavx
3990 && (i.tm.cpu_flags.bitfield.cpusse
3991 || i.tm.cpu_flags.bitfield.cpusse2
3992 || i.tm.cpu_flags.bitfield.cpusse3
3993 || i.tm.cpu_flags.bitfield.cpussse3
3994 || i.tm.cpu_flags.bitfield.cpusse4_1
3995 || i.tm.cpu_flags.bitfield.cpusse4_2
3996 || i.tm.cpu_flags.bitfield.cpupclmul
3997 || i.tm.cpu_flags.bitfield.cpuaes
3998 || i.tm.cpu_flags.bitfield.cpugfni))
3999 {
4000 (sse_check == check_warning
4001 ? as_warn
4002 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4003 }
4004
4005 /* Zap movzx and movsx suffix. The suffix has been set from
4006 "word ptr" or "byte ptr" on the source operand in Intel syntax
4007 or extracted from mnemonic in AT&T syntax. But we'll use
4008 the destination register to choose the suffix for encoding. */
4009 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4010 {
4011 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4012 there is no suffix, the default will be byte extension. */
4013 if (i.reg_operands != 2
4014 && !i.suffix
4015 && intel_syntax)
4016 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4017
4018 i.suffix = 0;
4019 }
4020
4021 if (i.tm.opcode_modifier.fwait)
4022 if (!add_prefix (FWAIT_OPCODE))
4023 return;
4024
4025 /* Check if REP prefix is OK. */
4026 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4027 {
4028 as_bad (_("invalid instruction `%s' after `%s'"),
4029 i.tm.name, i.rep_prefix);
4030 return;
4031 }
4032
4033 /* Check for lock without a lockable instruction. Destination operand
4034 must be memory unless it is xchg (0x86). */
4035 if (i.prefix[LOCK_PREFIX]
4036 && (!i.tm.opcode_modifier.islockable
4037 || i.mem_operands == 0
4038 || (i.tm.base_opcode != 0x86
4039 && !operand_type_check (i.types[i.operands - 1], anymem))))
4040 {
4041 as_bad (_("expecting lockable instruction after `lock'"));
4042 return;
4043 }
4044
4045 /* Check if HLE prefix is OK. */
4046 if (i.hle_prefix && !check_hle ())
4047 return;
4048
4049 /* Check BND prefix. */
4050 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4051 as_bad (_("expecting valid branch instruction after `bnd'"));
4052
4053 /* Check NOTRACK prefix. */
4054 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4055 as_bad (_("expecting indirect branch instruction after `notrack'"));
4056
4057 if (i.tm.cpu_flags.bitfield.cpumpx)
4058 {
4059 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4060 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4061 else if (flag_code != CODE_16BIT
4062 ? i.prefix[ADDR_PREFIX]
4063 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4064 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4065 }
4066
4067 /* Insert BND prefix. */
4068 if (add_bnd_prefix
4069 && i.tm.opcode_modifier.bndprefixok
4070 && !i.prefix[BND_PREFIX])
4071 add_prefix (BND_PREFIX_OPCODE);
4072
4073 /* Check string instruction segment overrides. */
4074 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4075 {
4076 if (!check_string ())
4077 return;
4078 i.disp_operands = 0;
4079 }
4080
4081 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4082 optimize_encoding ();
4083
4084 if (!process_suffix ())
4085 return;
4086
4087 /* Update operand types. */
4088 for (j = 0; j < i.operands; j++)
4089 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4090
4091 /* Make still unresolved immediate matches conform to size of immediate
4092 given in i.suffix. */
4093 if (!finalize_imm ())
4094 return;
4095
4096 if (i.types[0].bitfield.imm1)
4097 i.imm_operands = 0; /* kludge for shift insns. */
4098
4099 /* We only need to check those implicit registers for instructions
4100 with 3 operands or less. */
4101 if (i.operands <= 3)
4102 for (j = 0; j < i.operands; j++)
4103 if (i.types[j].bitfield.inoutportreg
4104 || i.types[j].bitfield.shiftcount
4105 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4106 i.reg_operands--;
4107
4108 /* ImmExt should be processed after SSE2AVX. */
4109 if (!i.tm.opcode_modifier.sse2avx
4110 && i.tm.opcode_modifier.immext)
4111 process_immext ();
4112
4113 /* For insns with operands there are more diddles to do to the opcode. */
4114 if (i.operands)
4115 {
4116 if (!process_operands ())
4117 return;
4118 }
4119 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4120 {
4121 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4122 as_warn (_("translating to `%sp'"), i.tm.name);
4123 }
4124
4125 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
4126 {
4127 if (flag_code == CODE_16BIT)
4128 {
4129 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4130 i.tm.name);
4131 return;
4132 }
4133
4134 if (i.tm.opcode_modifier.vex)
4135 build_vex_prefix (t);
4136 else
4137 build_evex_prefix ();
4138 }
4139
4140 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4141 instructions may define INT_OPCODE as well, so avoid this corner
4142 case for those instructions that use MODRM. */
4143 if (i.tm.base_opcode == INT_OPCODE
4144 && !i.tm.opcode_modifier.modrm
4145 && i.op[0].imms->X_add_number == 3)
4146 {
4147 i.tm.base_opcode = INT3_OPCODE;
4148 i.imm_operands = 0;
4149 }
4150
4151 if ((i.tm.opcode_modifier.jump
4152 || i.tm.opcode_modifier.jumpbyte
4153 || i.tm.opcode_modifier.jumpdword)
4154 && i.op[0].disps->X_op == O_constant)
4155 {
4156 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4157 the absolute address given by the constant. Since ix86 jumps and
4158 calls are pc relative, we need to generate a reloc. */
4159 i.op[0].disps->X_add_symbol = &abs_symbol;
4160 i.op[0].disps->X_op = O_symbol;
4161 }
4162
4163 if (i.tm.opcode_modifier.rex64)
4164 i.rex |= REX_W;
4165
4166 /* For 8 bit registers we need an empty rex prefix. Also if the
4167 instruction already has a prefix, we need to convert old
4168 registers to new ones. */
4169
4170 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4171 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4172 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4173 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4174 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4175 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4176 && i.rex != 0))
4177 {
4178 int x;
4179
4180 i.rex |= REX_OPCODE;
4181 for (x = 0; x < 2; x++)
4182 {
4183 /* Look for 8 bit operand that uses old registers. */
4184 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4185 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4186 {
4187 /* In case it is "hi" register, give up. */
4188 if (i.op[x].regs->reg_num > 3)
4189 as_bad (_("can't encode register '%s%s' in an "
4190 "instruction requiring REX prefix."),
4191 register_prefix, i.op[x].regs->reg_name);
4192
4193 /* Otherwise it is equivalent to the extended register.
4194 Since the encoding doesn't change this is merely
4195 cosmetic cleanup for debug output. */
4196
4197 i.op[x].regs = i.op[x].regs + 8;
4198 }
4199 }
4200 }
4201
4202 if (i.rex == 0 && i.rex_encoding)
4203 {
4204 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4205 that uses legacy register. If it is "hi" register, don't add
4206 the REX_OPCODE byte. */
4207 int x;
4208 for (x = 0; x < 2; x++)
4209 if (i.types[x].bitfield.reg
4210 && i.types[x].bitfield.byte
4211 && (i.op[x].regs->reg_flags & RegRex64) == 0
4212 && i.op[x].regs->reg_num > 3)
4213 {
4214 i.rex_encoding = FALSE;
4215 break;
4216 }
4217
4218 if (i.rex_encoding)
4219 i.rex = REX_OPCODE;
4220 }
4221
4222 if (i.rex != 0)
4223 add_prefix (REX_OPCODE | i.rex);
4224
4225 /* We are ready to output the insn. */
4226 output_insn ();
4227 }
4228
4229 static char *
4230 parse_insn (char *line, char *mnemonic)
4231 {
4232 char *l = line;
4233 char *token_start = l;
4234 char *mnem_p;
4235 int supported;
4236 const insn_template *t;
4237 char *dot_p = NULL;
4238
4239 while (1)
4240 {
4241 mnem_p = mnemonic;
4242 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4243 {
4244 if (*mnem_p == '.')
4245 dot_p = mnem_p;
4246 mnem_p++;
4247 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4248 {
4249 as_bad (_("no such instruction: `%s'"), token_start);
4250 return NULL;
4251 }
4252 l++;
4253 }
4254 if (!is_space_char (*l)
4255 && *l != END_OF_INSN
4256 && (intel_syntax
4257 || (*l != PREFIX_SEPARATOR
4258 && *l != ',')))
4259 {
4260 as_bad (_("invalid character %s in mnemonic"),
4261 output_invalid (*l));
4262 return NULL;
4263 }
4264 if (token_start == l)
4265 {
4266 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4267 as_bad (_("expecting prefix; got nothing"));
4268 else
4269 as_bad (_("expecting mnemonic; got nothing"));
4270 return NULL;
4271 }
4272
4273 /* Look up instruction (or prefix) via hash table. */
4274 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4275
4276 if (*l != END_OF_INSN
4277 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4278 && current_templates
4279 && current_templates->start->opcode_modifier.isprefix)
4280 {
4281 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4282 {
4283 as_bad ((flag_code != CODE_64BIT
4284 ? _("`%s' is only supported in 64-bit mode")
4285 : _("`%s' is not supported in 64-bit mode")),
4286 current_templates->start->name);
4287 return NULL;
4288 }
4289 /* If we are in 16-bit mode, do not allow addr16 or data16.
4290 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4291 if ((current_templates->start->opcode_modifier.size16
4292 || current_templates->start->opcode_modifier.size32)
4293 && flag_code != CODE_64BIT
4294 && (current_templates->start->opcode_modifier.size32
4295 ^ (flag_code == CODE_16BIT)))
4296 {
4297 as_bad (_("redundant %s prefix"),
4298 current_templates->start->name);
4299 return NULL;
4300 }
4301 if (current_templates->start->opcode_length == 0)
4302 {
4303 /* Handle pseudo prefixes. */
4304 switch (current_templates->start->base_opcode)
4305 {
4306 case 0x0:
4307 /* {disp8} */
4308 i.disp_encoding = disp_encoding_8bit;
4309 break;
4310 case 0x1:
4311 /* {disp32} */
4312 i.disp_encoding = disp_encoding_32bit;
4313 break;
4314 case 0x2:
4315 /* {load} */
4316 i.dir_encoding = dir_encoding_load;
4317 break;
4318 case 0x3:
4319 /* {store} */
4320 i.dir_encoding = dir_encoding_store;
4321 break;
4322 case 0x4:
4323 /* {vex2} */
4324 i.vec_encoding = vex_encoding_vex2;
4325 break;
4326 case 0x5:
4327 /* {vex3} */
4328 i.vec_encoding = vex_encoding_vex3;
4329 break;
4330 case 0x6:
4331 /* {evex} */
4332 i.vec_encoding = vex_encoding_evex;
4333 break;
4334 case 0x7:
4335 /* {rex} */
4336 i.rex_encoding = TRUE;
4337 break;
4338 case 0x8:
4339 /* {nooptimize} */
4340 i.no_optimize = TRUE;
4341 break;
4342 default:
4343 abort ();
4344 }
4345 }
4346 else
4347 {
4348 /* Add prefix, checking for repeated prefixes. */
4349 switch (add_prefix (current_templates->start->base_opcode))
4350 {
4351 case PREFIX_EXIST:
4352 return NULL;
4353 case PREFIX_DS:
4354 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4355 i.notrack_prefix = current_templates->start->name;
4356 break;
4357 case PREFIX_REP:
4358 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4359 i.hle_prefix = current_templates->start->name;
4360 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4361 i.bnd_prefix = current_templates->start->name;
4362 else
4363 i.rep_prefix = current_templates->start->name;
4364 break;
4365 default:
4366 break;
4367 }
4368 }
4369 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4370 token_start = ++l;
4371 }
4372 else
4373 break;
4374 }
4375
4376 if (!current_templates)
4377 {
4378 /* Check if we should swap operand or force 32bit displacement in
4379 encoding. */
4380 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4381 i.dir_encoding = dir_encoding_store;
4382 else if (mnem_p - 3 == dot_p
4383 && dot_p[1] == 'd'
4384 && dot_p[2] == '8')
4385 i.disp_encoding = disp_encoding_8bit;
4386 else if (mnem_p - 4 == dot_p
4387 && dot_p[1] == 'd'
4388 && dot_p[2] == '3'
4389 && dot_p[3] == '2')
4390 i.disp_encoding = disp_encoding_32bit;
4391 else
4392 goto check_suffix;
4393 mnem_p = dot_p;
4394 *dot_p = '\0';
4395 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4396 }
4397
4398 if (!current_templates)
4399 {
4400 check_suffix:
4401 /* See if we can get a match by trimming off a suffix. */
4402 switch (mnem_p[-1])
4403 {
4404 case WORD_MNEM_SUFFIX:
4405 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4406 i.suffix = SHORT_MNEM_SUFFIX;
4407 else
4408 /* Fall through. */
4409 case BYTE_MNEM_SUFFIX:
4410 case QWORD_MNEM_SUFFIX:
4411 i.suffix = mnem_p[-1];
4412 mnem_p[-1] = '\0';
4413 current_templates = (const templates *) hash_find (op_hash,
4414 mnemonic);
4415 break;
4416 case SHORT_MNEM_SUFFIX:
4417 case LONG_MNEM_SUFFIX:
4418 if (!intel_syntax)
4419 {
4420 i.suffix = mnem_p[-1];
4421 mnem_p[-1] = '\0';
4422 current_templates = (const templates *) hash_find (op_hash,
4423 mnemonic);
4424 }
4425 break;
4426
4427 /* Intel Syntax. */
4428 case 'd':
4429 if (intel_syntax)
4430 {
4431 if (intel_float_operand (mnemonic) == 1)
4432 i.suffix = SHORT_MNEM_SUFFIX;
4433 else
4434 i.suffix = LONG_MNEM_SUFFIX;
4435 mnem_p[-1] = '\0';
4436 current_templates = (const templates *) hash_find (op_hash,
4437 mnemonic);
4438 }
4439 break;
4440 }
4441 if (!current_templates)
4442 {
4443 as_bad (_("no such instruction: `%s'"), token_start);
4444 return NULL;
4445 }
4446 }
4447
4448 if (current_templates->start->opcode_modifier.jump
4449 || current_templates->start->opcode_modifier.jumpbyte)
4450 {
4451 /* Check for a branch hint. We allow ",pt" and ",pn" for
4452 predict taken and predict not taken respectively.
4453 I'm not sure that branch hints actually do anything on loop
4454 and jcxz insns (JumpByte) for current Pentium4 chips. They
4455 may work in the future and it doesn't hurt to accept them
4456 now. */
4457 if (l[0] == ',' && l[1] == 'p')
4458 {
4459 if (l[2] == 't')
4460 {
4461 if (!add_prefix (DS_PREFIX_OPCODE))
4462 return NULL;
4463 l += 3;
4464 }
4465 else if (l[2] == 'n')
4466 {
4467 if (!add_prefix (CS_PREFIX_OPCODE))
4468 return NULL;
4469 l += 3;
4470 }
4471 }
4472 }
4473 /* Any other comma loses. */
4474 if (*l == ',')
4475 {
4476 as_bad (_("invalid character %s in mnemonic"),
4477 output_invalid (*l));
4478 return NULL;
4479 }
4480
4481 /* Check if instruction is supported on specified architecture. */
4482 supported = 0;
4483 for (t = current_templates->start; t < current_templates->end; ++t)
4484 {
4485 supported |= cpu_flags_match (t);
4486 if (supported == CPU_FLAGS_PERFECT_MATCH)
4487 {
4488 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4489 as_warn (_("use .code16 to ensure correct addressing mode"));
4490
4491 return l;
4492 }
4493 }
4494
4495 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4496 as_bad (flag_code == CODE_64BIT
4497 ? _("`%s' is not supported in 64-bit mode")
4498 : _("`%s' is only supported in 64-bit mode"),
4499 current_templates->start->name);
4500 else
4501 as_bad (_("`%s' is not supported on `%s%s'"),
4502 current_templates->start->name,
4503 cpu_arch_name ? cpu_arch_name : default_arch,
4504 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4505
4506 return NULL;
4507 }
4508
4509 static char *
4510 parse_operands (char *l, const char *mnemonic)
4511 {
4512 char *token_start;
4513
4514 /* 1 if operand is pending after ','. */
4515 unsigned int expecting_operand = 0;
4516
4517 /* Non-zero if operand parens not balanced. */
4518 unsigned int paren_not_balanced;
4519
4520 while (*l != END_OF_INSN)
4521 {
4522 /* Skip optional white space before operand. */
4523 if (is_space_char (*l))
4524 ++l;
4525 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4526 {
4527 as_bad (_("invalid character %s before operand %d"),
4528 output_invalid (*l),
4529 i.operands + 1);
4530 return NULL;
4531 }
4532 token_start = l; /* After white space. */
4533 paren_not_balanced = 0;
4534 while (paren_not_balanced || *l != ',')
4535 {
4536 if (*l == END_OF_INSN)
4537 {
4538 if (paren_not_balanced)
4539 {
4540 if (!intel_syntax)
4541 as_bad (_("unbalanced parenthesis in operand %d."),
4542 i.operands + 1);
4543 else
4544 as_bad (_("unbalanced brackets in operand %d."),
4545 i.operands + 1);
4546 return NULL;
4547 }
4548 else
4549 break; /* we are done */
4550 }
4551 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4552 {
4553 as_bad (_("invalid character %s in operand %d"),
4554 output_invalid (*l),
4555 i.operands + 1);
4556 return NULL;
4557 }
4558 if (!intel_syntax)
4559 {
4560 if (*l == '(')
4561 ++paren_not_balanced;
4562 if (*l == ')')
4563 --paren_not_balanced;
4564 }
4565 else
4566 {
4567 if (*l == '[')
4568 ++paren_not_balanced;
4569 if (*l == ']')
4570 --paren_not_balanced;
4571 }
4572 l++;
4573 }
4574 if (l != token_start)
4575 { /* Yes, we've read in another operand. */
4576 unsigned int operand_ok;
4577 this_operand = i.operands++;
4578 if (i.operands > MAX_OPERANDS)
4579 {
4580 as_bad (_("spurious operands; (%d operands/instruction max)"),
4581 MAX_OPERANDS);
4582 return NULL;
4583 }
4584 i.types[this_operand].bitfield.unspecified = 1;
4585 /* Now parse operand adding info to 'i' as we go along. */
4586 END_STRING_AND_SAVE (l);
4587
4588 if (intel_syntax)
4589 operand_ok =
4590 i386_intel_operand (token_start,
4591 intel_float_operand (mnemonic));
4592 else
4593 operand_ok = i386_att_operand (token_start);
4594
4595 RESTORE_END_STRING (l);
4596 if (!operand_ok)
4597 return NULL;
4598 }
4599 else
4600 {
4601 if (expecting_operand)
4602 {
4603 expecting_operand_after_comma:
4604 as_bad (_("expecting operand after ','; got nothing"));
4605 return NULL;
4606 }
4607 if (*l == ',')
4608 {
4609 as_bad (_("expecting operand before ','; got nothing"));
4610 return NULL;
4611 }
4612 }
4613
4614 /* Now *l must be either ',' or END_OF_INSN. */
4615 if (*l == ',')
4616 {
4617 if (*++l == END_OF_INSN)
4618 {
4619 /* Just skip it, if it's \n complain. */
4620 goto expecting_operand_after_comma;
4621 }
4622 expecting_operand = 1;
4623 }
4624 }
4625 return l;
4626 }
4627
4628 static void
4629 swap_2_operands (int xchg1, int xchg2)
4630 {
4631 union i386_op temp_op;
4632 i386_operand_type temp_type;
4633 enum bfd_reloc_code_real temp_reloc;
4634
4635 temp_type = i.types[xchg2];
4636 i.types[xchg2] = i.types[xchg1];
4637 i.types[xchg1] = temp_type;
4638 temp_op = i.op[xchg2];
4639 i.op[xchg2] = i.op[xchg1];
4640 i.op[xchg1] = temp_op;
4641 temp_reloc = i.reloc[xchg2];
4642 i.reloc[xchg2] = i.reloc[xchg1];
4643 i.reloc[xchg1] = temp_reloc;
4644
4645 if (i.mask)
4646 {
4647 if (i.mask->operand == xchg1)
4648 i.mask->operand = xchg2;
4649 else if (i.mask->operand == xchg2)
4650 i.mask->operand = xchg1;
4651 }
4652 if (i.broadcast)
4653 {
4654 if (i.broadcast->operand == xchg1)
4655 i.broadcast->operand = xchg2;
4656 else if (i.broadcast->operand == xchg2)
4657 i.broadcast->operand = xchg1;
4658 }
4659 if (i.rounding)
4660 {
4661 if (i.rounding->operand == xchg1)
4662 i.rounding->operand = xchg2;
4663 else if (i.rounding->operand == xchg2)
4664 i.rounding->operand = xchg1;
4665 }
4666 }
4667
4668 static void
4669 swap_operands (void)
4670 {
4671 switch (i.operands)
4672 {
4673 case 5:
4674 case 4:
4675 swap_2_operands (1, i.operands - 2);
4676 /* Fall through. */
4677 case 3:
4678 case 2:
4679 swap_2_operands (0, i.operands - 1);
4680 break;
4681 default:
4682 abort ();
4683 }
4684
4685 if (i.mem_operands == 2)
4686 {
4687 const seg_entry *temp_seg;
4688 temp_seg = i.seg[0];
4689 i.seg[0] = i.seg[1];
4690 i.seg[1] = temp_seg;
4691 }
4692 }
4693
4694 /* Try to ensure constant immediates are represented in the smallest
4695 opcode possible. */
4696 static void
4697 optimize_imm (void)
4698 {
4699 char guess_suffix = 0;
4700 int op;
4701
4702 if (i.suffix)
4703 guess_suffix = i.suffix;
4704 else if (i.reg_operands)
4705 {
4706 /* Figure out a suffix from the last register operand specified.
4707 We can't do this properly yet, ie. excluding InOutPortReg,
4708 but the following works for instructions with immediates.
4709 In any case, we can't set i.suffix yet. */
4710 for (op = i.operands; --op >= 0;)
4711 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4712 {
4713 guess_suffix = BYTE_MNEM_SUFFIX;
4714 break;
4715 }
4716 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4717 {
4718 guess_suffix = WORD_MNEM_SUFFIX;
4719 break;
4720 }
4721 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4722 {
4723 guess_suffix = LONG_MNEM_SUFFIX;
4724 break;
4725 }
4726 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4727 {
4728 guess_suffix = QWORD_MNEM_SUFFIX;
4729 break;
4730 }
4731 }
4732 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4733 guess_suffix = WORD_MNEM_SUFFIX;
4734
4735 for (op = i.operands; --op >= 0;)
4736 if (operand_type_check (i.types[op], imm))
4737 {
4738 switch (i.op[op].imms->X_op)
4739 {
4740 case O_constant:
4741 /* If a suffix is given, this operand may be shortened. */
4742 switch (guess_suffix)
4743 {
4744 case LONG_MNEM_SUFFIX:
4745 i.types[op].bitfield.imm32 = 1;
4746 i.types[op].bitfield.imm64 = 1;
4747 break;
4748 case WORD_MNEM_SUFFIX:
4749 i.types[op].bitfield.imm16 = 1;
4750 i.types[op].bitfield.imm32 = 1;
4751 i.types[op].bitfield.imm32s = 1;
4752 i.types[op].bitfield.imm64 = 1;
4753 break;
4754 case BYTE_MNEM_SUFFIX:
4755 i.types[op].bitfield.imm8 = 1;
4756 i.types[op].bitfield.imm8s = 1;
4757 i.types[op].bitfield.imm16 = 1;
4758 i.types[op].bitfield.imm32 = 1;
4759 i.types[op].bitfield.imm32s = 1;
4760 i.types[op].bitfield.imm64 = 1;
4761 break;
4762 }
4763
4764 /* If this operand is at most 16 bits, convert it
4765 to a signed 16 bit number before trying to see
4766 whether it will fit in an even smaller size.
4767 This allows a 16-bit operand such as $0xffe0 to
4768 be recognised as within Imm8S range. */
4769 if ((i.types[op].bitfield.imm16)
4770 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4771 {
4772 i.op[op].imms->X_add_number =
4773 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4774 }
4775 #ifdef BFD64
4776 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4777 if ((i.types[op].bitfield.imm32)
4778 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4779 == 0))
4780 {
4781 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4782 ^ ((offsetT) 1 << 31))
4783 - ((offsetT) 1 << 31));
4784 }
4785 #endif
4786 i.types[op]
4787 = operand_type_or (i.types[op],
4788 smallest_imm_type (i.op[op].imms->X_add_number));
4789
4790 /* We must avoid matching of Imm32 templates when 64bit
4791 only immediate is available. */
4792 if (guess_suffix == QWORD_MNEM_SUFFIX)
4793 i.types[op].bitfield.imm32 = 0;
4794 break;
4795
4796 case O_absent:
4797 case O_register:
4798 abort ();
4799
4800 /* Symbols and expressions. */
4801 default:
4802 /* Convert symbolic operand to proper sizes for matching, but don't
4803 prevent matching a set of insns that only supports sizes other
4804 than those matching the insn suffix. */
4805 {
4806 i386_operand_type mask, allowed;
4807 const insn_template *t;
4808
4809 operand_type_set (&mask, 0);
4810 operand_type_set (&allowed, 0);
4811
4812 for (t = current_templates->start;
4813 t < current_templates->end;
4814 ++t)
4815 allowed = operand_type_or (allowed,
4816 t->operand_types[op]);
4817 switch (guess_suffix)
4818 {
4819 case QWORD_MNEM_SUFFIX:
4820 mask.bitfield.imm64 = 1;
4821 mask.bitfield.imm32s = 1;
4822 break;
4823 case LONG_MNEM_SUFFIX:
4824 mask.bitfield.imm32 = 1;
4825 break;
4826 case WORD_MNEM_SUFFIX:
4827 mask.bitfield.imm16 = 1;
4828 break;
4829 case BYTE_MNEM_SUFFIX:
4830 mask.bitfield.imm8 = 1;
4831 break;
4832 default:
4833 break;
4834 }
4835 allowed = operand_type_and (mask, allowed);
4836 if (!operand_type_all_zero (&allowed))
4837 i.types[op] = operand_type_and (i.types[op], mask);
4838 }
4839 break;
4840 }
4841 }
4842 }
4843
4844 /* Try to use the smallest displacement type too. */
4845 static void
4846 optimize_disp (void)
4847 {
4848 int op;
4849
4850 for (op = i.operands; --op >= 0;)
4851 if (operand_type_check (i.types[op], disp))
4852 {
4853 if (i.op[op].disps->X_op == O_constant)
4854 {
4855 offsetT op_disp = i.op[op].disps->X_add_number;
4856
4857 if (i.types[op].bitfield.disp16
4858 && (op_disp & ~(offsetT) 0xffff) == 0)
4859 {
4860 /* If this operand is at most 16 bits, convert
4861 to a signed 16 bit number and don't use 64bit
4862 displacement. */
4863 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4864 i.types[op].bitfield.disp64 = 0;
4865 }
4866 #ifdef BFD64
4867 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4868 if (i.types[op].bitfield.disp32
4869 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4870 {
4871 /* If this operand is at most 32 bits, convert
4872 to a signed 32 bit number and don't use 64bit
4873 displacement. */
4874 op_disp &= (((offsetT) 2 << 31) - 1);
4875 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4876 i.types[op].bitfield.disp64 = 0;
4877 }
4878 #endif
4879 if (!op_disp && i.types[op].bitfield.baseindex)
4880 {
4881 i.types[op].bitfield.disp8 = 0;
4882 i.types[op].bitfield.disp16 = 0;
4883 i.types[op].bitfield.disp32 = 0;
4884 i.types[op].bitfield.disp32s = 0;
4885 i.types[op].bitfield.disp64 = 0;
4886 i.op[op].disps = 0;
4887 i.disp_operands--;
4888 }
4889 else if (flag_code == CODE_64BIT)
4890 {
4891 if (fits_in_signed_long (op_disp))
4892 {
4893 i.types[op].bitfield.disp64 = 0;
4894 i.types[op].bitfield.disp32s = 1;
4895 }
4896 if (i.prefix[ADDR_PREFIX]
4897 && fits_in_unsigned_long (op_disp))
4898 i.types[op].bitfield.disp32 = 1;
4899 }
4900 if ((i.types[op].bitfield.disp32
4901 || i.types[op].bitfield.disp32s
4902 || i.types[op].bitfield.disp16)
4903 && fits_in_disp8 (op_disp))
4904 i.types[op].bitfield.disp8 = 1;
4905 }
4906 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4907 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4908 {
4909 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4910 i.op[op].disps, 0, i.reloc[op]);
4911 i.types[op].bitfield.disp8 = 0;
4912 i.types[op].bitfield.disp16 = 0;
4913 i.types[op].bitfield.disp32 = 0;
4914 i.types[op].bitfield.disp32s = 0;
4915 i.types[op].bitfield.disp64 = 0;
4916 }
4917 else
4918 /* We only support 64bit displacement on constants. */
4919 i.types[op].bitfield.disp64 = 0;
4920 }
4921 }
4922
4923 /* Check if operands are valid for the instruction. */
4924
4925 static int
4926 check_VecOperands (const insn_template *t)
4927 {
4928 unsigned int op;
4929
4930 /* Without VSIB byte, we can't have a vector register for index. */
4931 if (!t->opcode_modifier.vecsib
4932 && i.index_reg
4933 && (i.index_reg->reg_type.bitfield.xmmword
4934 || i.index_reg->reg_type.bitfield.ymmword
4935 || i.index_reg->reg_type.bitfield.zmmword))
4936 {
4937 i.error = unsupported_vector_index_register;
4938 return 1;
4939 }
4940
4941 /* Check if default mask is allowed. */
4942 if (t->opcode_modifier.nodefmask
4943 && (!i.mask || i.mask->mask->reg_num == 0))
4944 {
4945 i.error = no_default_mask;
4946 return 1;
4947 }
4948
4949 /* For VSIB byte, we need a vector register for index, and all vector
4950 registers must be distinct. */
4951 if (t->opcode_modifier.vecsib)
4952 {
4953 if (!i.index_reg
4954 || !((t->opcode_modifier.vecsib == VecSIB128
4955 && i.index_reg->reg_type.bitfield.xmmword)
4956 || (t->opcode_modifier.vecsib == VecSIB256
4957 && i.index_reg->reg_type.bitfield.ymmword)
4958 || (t->opcode_modifier.vecsib == VecSIB512
4959 && i.index_reg->reg_type.bitfield.zmmword)))
4960 {
4961 i.error = invalid_vsib_address;
4962 return 1;
4963 }
4964
4965 gas_assert (i.reg_operands == 2 || i.mask);
4966 if (i.reg_operands == 2 && !i.mask)
4967 {
4968 gas_assert (i.types[0].bitfield.regsimd);
4969 gas_assert (i.types[0].bitfield.xmmword
4970 || i.types[0].bitfield.ymmword);
4971 gas_assert (i.types[2].bitfield.regsimd);
4972 gas_assert (i.types[2].bitfield.xmmword
4973 || i.types[2].bitfield.ymmword);
4974 if (operand_check == check_none)
4975 return 0;
4976 if (register_number (i.op[0].regs)
4977 != register_number (i.index_reg)
4978 && register_number (i.op[2].regs)
4979 != register_number (i.index_reg)
4980 && register_number (i.op[0].regs)
4981 != register_number (i.op[2].regs))
4982 return 0;
4983 if (operand_check == check_error)
4984 {
4985 i.error = invalid_vector_register_set;
4986 return 1;
4987 }
4988 as_warn (_("mask, index, and destination registers should be distinct"));
4989 }
4990 else if (i.reg_operands == 1 && i.mask)
4991 {
4992 if (i.types[1].bitfield.regsimd
4993 && (i.types[1].bitfield.xmmword
4994 || i.types[1].bitfield.ymmword
4995 || i.types[1].bitfield.zmmword)
4996 && (register_number (i.op[1].regs)
4997 == register_number (i.index_reg)))
4998 {
4999 if (operand_check == check_error)
5000 {
5001 i.error = invalid_vector_register_set;
5002 return 1;
5003 }
5004 if (operand_check != check_none)
5005 as_warn (_("index and destination registers should be distinct"));
5006 }
5007 }
5008 }
5009
5010 /* Check if broadcast is supported by the instruction and is applied
5011 to the memory operand. */
5012 if (i.broadcast)
5013 {
5014 int broadcasted_opnd_size;
5015
5016 /* Check if specified broadcast is supported in this instruction,
5017 and it's applied to memory operand of DWORD or QWORD type,
5018 depending on VecESize. */
5019 if (i.broadcast->type != t->opcode_modifier.broadcast
5020 || !i.types[i.broadcast->operand].bitfield.mem
5021 || (t->opcode_modifier.vecesize == 0
5022 && !i.types[i.broadcast->operand].bitfield.dword
5023 && !i.types[i.broadcast->operand].bitfield.unspecified)
5024 || (t->opcode_modifier.vecesize == 1
5025 && !i.types[i.broadcast->operand].bitfield.qword
5026 && !i.types[i.broadcast->operand].bitfield.unspecified))
5027 goto bad_broadcast;
5028
5029 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
5030 if (i.broadcast->type == BROADCAST_1TO16)
5031 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
5032 else if (i.broadcast->type == BROADCAST_1TO8)
5033 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
5034 else if (i.broadcast->type == BROADCAST_1TO4)
5035 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
5036 else if (i.broadcast->type == BROADCAST_1TO2)
5037 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
5038 else
5039 goto bad_broadcast;
5040
5041 if ((broadcasted_opnd_size == 256
5042 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
5043 || (broadcasted_opnd_size == 512
5044 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
5045 {
5046 bad_broadcast:
5047 i.error = unsupported_broadcast;
5048 return 1;
5049 }
5050 }
5051 /* If broadcast is supported in this instruction, we need to check if
5052 operand of one-element size isn't specified without broadcast. */
5053 else if (t->opcode_modifier.broadcast && i.mem_operands)
5054 {
5055 /* Find memory operand. */
5056 for (op = 0; op < i.operands; op++)
5057 if (operand_type_check (i.types[op], anymem))
5058 break;
5059 gas_assert (op < i.operands);
5060 /* Check size of the memory operand. */
5061 if ((t->opcode_modifier.vecesize == 0
5062 && i.types[op].bitfield.dword)
5063 || (t->opcode_modifier.vecesize == 1
5064 && i.types[op].bitfield.qword))
5065 {
5066 i.error = broadcast_needed;
5067 return 1;
5068 }
5069 }
5070
5071 /* Check if requested masking is supported. */
5072 if (i.mask
5073 && (!t->opcode_modifier.masking
5074 || (i.mask->zeroing
5075 && t->opcode_modifier.masking == MERGING_MASKING)))
5076 {
5077 i.error = unsupported_masking;
5078 return 1;
5079 }
5080
5081 /* Check if masking is applied to dest operand. */
5082 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5083 {
5084 i.error = mask_not_on_destination;
5085 return 1;
5086 }
5087
5088 /* Check RC/SAE. */
5089 if (i.rounding)
5090 {
5091 if ((i.rounding->type != saeonly
5092 && !t->opcode_modifier.staticrounding)
5093 || (i.rounding->type == saeonly
5094 && (t->opcode_modifier.staticrounding
5095 || !t->opcode_modifier.sae)))
5096 {
5097 i.error = unsupported_rc_sae;
5098 return 1;
5099 }
5100 /* If the instruction has several immediate operands and one of
5101 them is rounding, the rounding operand should be the last
5102 immediate operand. */
5103 if (i.imm_operands > 1
5104 && i.rounding->operand != (int) (i.imm_operands - 1))
5105 {
5106 i.error = rc_sae_operand_not_last_imm;
5107 return 1;
5108 }
5109 }
5110
5111 /* Check vector Disp8 operand. */
5112 if (t->opcode_modifier.disp8memshift
5113 && i.disp_encoding != disp_encoding_32bit)
5114 {
5115 if (i.broadcast)
5116 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
5117 else
5118 i.memshift = t->opcode_modifier.disp8memshift;
5119
5120 for (op = 0; op < i.operands; op++)
5121 if (operand_type_check (i.types[op], disp)
5122 && i.op[op].disps->X_op == O_constant)
5123 {
5124 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5125 {
5126 i.types[op].bitfield.disp8 = 1;
5127 return 0;
5128 }
5129 i.types[op].bitfield.disp8 = 0;
5130 }
5131 }
5132
5133 i.memshift = 0;
5134
5135 return 0;
5136 }
5137
5138 /* Check if operands are valid for the instruction. Update VEX
5139 operand types. */
5140
5141 static int
5142 VEX_check_operands (const insn_template *t)
5143 {
5144 if (i.vec_encoding == vex_encoding_evex)
5145 {
5146 /* This instruction must be encoded with EVEX prefix. */
5147 if (!t->opcode_modifier.evex)
5148 {
5149 i.error = unsupported;
5150 return 1;
5151 }
5152 return 0;
5153 }
5154
5155 if (!t->opcode_modifier.vex)
5156 {
5157 /* This instruction template doesn't have VEX prefix. */
5158 if (i.vec_encoding != vex_encoding_default)
5159 {
5160 i.error = unsupported;
5161 return 1;
5162 }
5163 return 0;
5164 }
5165
5166 /* Only check VEX_Imm4, which must be the first operand. */
5167 if (t->operand_types[0].bitfield.vec_imm4)
5168 {
5169 if (i.op[0].imms->X_op != O_constant
5170 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5171 {
5172 i.error = bad_imm4;
5173 return 1;
5174 }
5175
5176 /* Turn off Imm8 so that update_imm won't complain. */
5177 i.types[0] = vec_imm4;
5178 }
5179
5180 return 0;
5181 }
5182
5183 static const insn_template *
5184 match_template (char mnem_suffix)
5185 {
5186 /* Points to template once we've found it. */
5187 const insn_template *t;
5188 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5189 i386_operand_type overlap4;
5190 unsigned int found_reverse_match;
5191 i386_opcode_modifier suffix_check, mnemsuf_check;
5192 i386_operand_type operand_types [MAX_OPERANDS];
5193 int addr_prefix_disp;
5194 unsigned int j;
5195 unsigned int found_cpu_match;
5196 unsigned int check_register;
5197 enum i386_error specific_error = 0;
5198
5199 #if MAX_OPERANDS != 5
5200 # error "MAX_OPERANDS must be 5."
5201 #endif
5202
5203 found_reverse_match = 0;
5204 addr_prefix_disp = -1;
5205
5206 memset (&suffix_check, 0, sizeof (suffix_check));
5207 if (i.suffix == BYTE_MNEM_SUFFIX)
5208 suffix_check.no_bsuf = 1;
5209 else if (i.suffix == WORD_MNEM_SUFFIX)
5210 suffix_check.no_wsuf = 1;
5211 else if (i.suffix == SHORT_MNEM_SUFFIX)
5212 suffix_check.no_ssuf = 1;
5213 else if (i.suffix == LONG_MNEM_SUFFIX)
5214 suffix_check.no_lsuf = 1;
5215 else if (i.suffix == QWORD_MNEM_SUFFIX)
5216 suffix_check.no_qsuf = 1;
5217 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5218 suffix_check.no_ldsuf = 1;
5219
5220 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5221 if (intel_syntax)
5222 {
5223 switch (mnem_suffix)
5224 {
5225 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5226 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5227 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5228 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5229 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5230 }
5231 }
5232
5233 /* Must have right number of operands. */
5234 i.error = number_of_operands_mismatch;
5235
5236 for (t = current_templates->start; t < current_templates->end; t++)
5237 {
5238 addr_prefix_disp = -1;
5239
5240 if (i.operands != t->operands)
5241 continue;
5242
5243 /* Check processor support. */
5244 i.error = unsupported;
5245 found_cpu_match = (cpu_flags_match (t)
5246 == CPU_FLAGS_PERFECT_MATCH);
5247 if (!found_cpu_match)
5248 continue;
5249
5250 /* Check old gcc support. */
5251 i.error = old_gcc_only;
5252 if (!old_gcc && t->opcode_modifier.oldgcc)
5253 continue;
5254
5255 /* Check AT&T mnemonic. */
5256 i.error = unsupported_with_intel_mnemonic;
5257 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5258 continue;
5259
5260 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5261 i.error = unsupported_syntax;
5262 if ((intel_syntax && t->opcode_modifier.attsyntax)
5263 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5264 || (intel64 && t->opcode_modifier.amd64)
5265 || (!intel64 && t->opcode_modifier.intel64))
5266 continue;
5267
5268 /* Check the suffix, except for some instructions in intel mode. */
5269 i.error = invalid_instruction_suffix;
5270 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5271 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5272 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5273 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5274 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5275 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5276 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5277 continue;
5278 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5279 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5280 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5281 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5282 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5283 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5284 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5285 continue;
5286
5287 if (!operand_size_match (t))
5288 continue;
5289
5290 for (j = 0; j < MAX_OPERANDS; j++)
5291 operand_types[j] = t->operand_types[j];
5292
5293 /* In general, don't allow 64-bit operands in 32-bit mode. */
5294 if (i.suffix == QWORD_MNEM_SUFFIX
5295 && flag_code != CODE_64BIT
5296 && (intel_syntax
5297 ? (!t->opcode_modifier.ignoresize
5298 && !intel_float_operand (t->name))
5299 : intel_float_operand (t->name) != 2)
5300 && ((!operand_types[0].bitfield.regmmx
5301 && !operand_types[0].bitfield.regsimd)
5302 || (!operand_types[t->operands > 1].bitfield.regmmx
5303 && !operand_types[t->operands > 1].bitfield.regsimd))
5304 && (t->base_opcode != 0x0fc7
5305 || t->extension_opcode != 1 /* cmpxchg8b */))
5306 continue;
5307
5308 /* In general, don't allow 32-bit operands on pre-386. */
5309 else if (i.suffix == LONG_MNEM_SUFFIX
5310 && !cpu_arch_flags.bitfield.cpui386
5311 && (intel_syntax
5312 ? (!t->opcode_modifier.ignoresize
5313 && !intel_float_operand (t->name))
5314 : intel_float_operand (t->name) != 2)
5315 && ((!operand_types[0].bitfield.regmmx
5316 && !operand_types[0].bitfield.regsimd)
5317 || (!operand_types[t->operands > 1].bitfield.regmmx
5318 && !operand_types[t->operands > 1].bitfield.regsimd)))
5319 continue;
5320
5321 /* Do not verify operands when there are none. */
5322 else
5323 {
5324 if (!t->operands)
5325 /* We've found a match; break out of loop. */
5326 break;
5327 }
5328
5329 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5330 into Disp32/Disp16/Disp32 operand. */
5331 if (i.prefix[ADDR_PREFIX] != 0)
5332 {
5333 /* There should be only one Disp operand. */
5334 switch (flag_code)
5335 {
5336 case CODE_16BIT:
5337 for (j = 0; j < MAX_OPERANDS; j++)
5338 {
5339 if (operand_types[j].bitfield.disp16)
5340 {
5341 addr_prefix_disp = j;
5342 operand_types[j].bitfield.disp32 = 1;
5343 operand_types[j].bitfield.disp16 = 0;
5344 break;
5345 }
5346 }
5347 break;
5348 case CODE_32BIT:
5349 for (j = 0; j < MAX_OPERANDS; j++)
5350 {
5351 if (operand_types[j].bitfield.disp32)
5352 {
5353 addr_prefix_disp = j;
5354 operand_types[j].bitfield.disp32 = 0;
5355 operand_types[j].bitfield.disp16 = 1;
5356 break;
5357 }
5358 }
5359 break;
5360 case CODE_64BIT:
5361 for (j = 0; j < MAX_OPERANDS; j++)
5362 {
5363 if (operand_types[j].bitfield.disp64)
5364 {
5365 addr_prefix_disp = j;
5366 operand_types[j].bitfield.disp64 = 0;
5367 operand_types[j].bitfield.disp32 = 1;
5368 break;
5369 }
5370 }
5371 break;
5372 }
5373 }
5374
5375 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5376 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5377 continue;
5378
5379 /* We check register size if needed. */
5380 check_register = t->opcode_modifier.checkregsize;
5381 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5382 switch (t->operands)
5383 {
5384 case 1:
5385 if (!operand_type_match (overlap0, i.types[0]))
5386 continue;
5387 break;
5388 case 2:
5389 /* xchg %eax, %eax is a special case. It is an alias for nop
5390 only in 32bit mode and we can use opcode 0x90. In 64bit
5391 mode, we can't use 0x90 for xchg %eax, %eax since it should
5392 zero-extend %eax to %rax. */
5393 if (flag_code == CODE_64BIT
5394 && t->base_opcode == 0x90
5395 && operand_type_equal (&i.types [0], &acc32)
5396 && operand_type_equal (&i.types [1], &acc32))
5397 continue;
5398 /* If we want store form, we reverse direction of operands. */
5399 if (i.dir_encoding == dir_encoding_store
5400 && t->opcode_modifier.d)
5401 goto check_reverse;
5402 /* Fall through. */
5403
5404 case 3:
5405 /* If we want store form, we skip the current load. */
5406 if (i.dir_encoding == dir_encoding_store
5407 && i.mem_operands == 0
5408 && t->opcode_modifier.load)
5409 continue;
5410 /* Fall through. */
5411 case 4:
5412 case 5:
5413 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5414 if (!operand_type_match (overlap0, i.types[0])
5415 || !operand_type_match (overlap1, i.types[1])
5416 || (check_register
5417 && !operand_type_register_match (i.types[0],
5418 operand_types[0],
5419 i.types[1],
5420 operand_types[1])))
5421 {
5422 /* Check if other direction is valid ... */
5423 if (!t->opcode_modifier.d)
5424 continue;
5425
5426 check_reverse:
5427 /* Try reversing direction of operands. */
5428 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5429 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5430 if (!operand_type_match (overlap0, i.types[0])
5431 || !operand_type_match (overlap1, i.types[1])
5432 || (check_register
5433 && !operand_type_register_match (i.types[0],
5434 operand_types[1],
5435 i.types[1],
5436 operand_types[0])))
5437 {
5438 /* Does not match either direction. */
5439 continue;
5440 }
5441 /* found_reverse_match holds which of D or FloatR
5442 we've found. */
5443 if (!t->opcode_modifier.d)
5444 found_reverse_match = 0;
5445 else if (operand_types[0].bitfield.tbyte)
5446 found_reverse_match = Opcode_FloatD;
5447 else
5448 found_reverse_match = Opcode_D;
5449 if (t->opcode_modifier.floatr)
5450 found_reverse_match |= Opcode_FloatR;
5451 }
5452 else
5453 {
5454 /* Found a forward 2 operand match here. */
5455 switch (t->operands)
5456 {
5457 case 5:
5458 overlap4 = operand_type_and (i.types[4],
5459 operand_types[4]);
5460 /* Fall through. */
5461 case 4:
5462 overlap3 = operand_type_and (i.types[3],
5463 operand_types[3]);
5464 /* Fall through. */
5465 case 3:
5466 overlap2 = operand_type_and (i.types[2],
5467 operand_types[2]);
5468 break;
5469 }
5470
5471 switch (t->operands)
5472 {
5473 case 5:
5474 if (!operand_type_match (overlap4, i.types[4])
5475 || !operand_type_register_match (i.types[3],
5476 operand_types[3],
5477 i.types[4],
5478 operand_types[4]))
5479 continue;
5480 /* Fall through. */
5481 case 4:
5482 if (!operand_type_match (overlap3, i.types[3])
5483 || (check_register
5484 && !operand_type_register_match (i.types[2],
5485 operand_types[2],
5486 i.types[3],
5487 operand_types[3])))
5488 continue;
5489 /* Fall through. */
5490 case 3:
5491 /* Here we make use of the fact that there are no
5492 reverse match 3 operand instructions. */
5493 if (!operand_type_match (overlap2, i.types[2])
5494 || (check_register
5495 && (!operand_type_register_match (i.types[0],
5496 operand_types[0],
5497 i.types[2],
5498 operand_types[2])
5499 || !operand_type_register_match (i.types[1],
5500 operand_types[1],
5501 i.types[2],
5502 operand_types[2]))))
5503 continue;
5504 break;
5505 }
5506 }
5507 /* Found either forward/reverse 2, 3 or 4 operand match here:
5508 slip through to break. */
5509 }
5510 if (!found_cpu_match)
5511 {
5512 found_reverse_match = 0;
5513 continue;
5514 }
5515
5516 /* Check if vector and VEX operands are valid. */
5517 if (check_VecOperands (t) || VEX_check_operands (t))
5518 {
5519 specific_error = i.error;
5520 continue;
5521 }
5522
5523 /* We've found a match; break out of loop. */
5524 break;
5525 }
5526
5527 if (t == current_templates->end)
5528 {
5529 /* We found no match. */
5530 const char *err_msg;
5531 switch (specific_error ? specific_error : i.error)
5532 {
5533 default:
5534 abort ();
5535 case operand_size_mismatch:
5536 err_msg = _("operand size mismatch");
5537 break;
5538 case operand_type_mismatch:
5539 err_msg = _("operand type mismatch");
5540 break;
5541 case register_type_mismatch:
5542 err_msg = _("register type mismatch");
5543 break;
5544 case number_of_operands_mismatch:
5545 err_msg = _("number of operands mismatch");
5546 break;
5547 case invalid_instruction_suffix:
5548 err_msg = _("invalid instruction suffix");
5549 break;
5550 case bad_imm4:
5551 err_msg = _("constant doesn't fit in 4 bits");
5552 break;
5553 case old_gcc_only:
5554 err_msg = _("only supported with old gcc");
5555 break;
5556 case unsupported_with_intel_mnemonic:
5557 err_msg = _("unsupported with Intel mnemonic");
5558 break;
5559 case unsupported_syntax:
5560 err_msg = _("unsupported syntax");
5561 break;
5562 case unsupported:
5563 as_bad (_("unsupported instruction `%s'"),
5564 current_templates->start->name);
5565 return NULL;
5566 case invalid_vsib_address:
5567 err_msg = _("invalid VSIB address");
5568 break;
5569 case invalid_vector_register_set:
5570 err_msg = _("mask, index, and destination registers must be distinct");
5571 break;
5572 case unsupported_vector_index_register:
5573 err_msg = _("unsupported vector index register");
5574 break;
5575 case unsupported_broadcast:
5576 err_msg = _("unsupported broadcast");
5577 break;
5578 case broadcast_not_on_src_operand:
5579 err_msg = _("broadcast not on source memory operand");
5580 break;
5581 case broadcast_needed:
5582 err_msg = _("broadcast is needed for operand of such type");
5583 break;
5584 case unsupported_masking:
5585 err_msg = _("unsupported masking");
5586 break;
5587 case mask_not_on_destination:
5588 err_msg = _("mask not on destination operand");
5589 break;
5590 case no_default_mask:
5591 err_msg = _("default mask isn't allowed");
5592 break;
5593 case unsupported_rc_sae:
5594 err_msg = _("unsupported static rounding/sae");
5595 break;
5596 case rc_sae_operand_not_last_imm:
5597 if (intel_syntax)
5598 err_msg = _("RC/SAE operand must precede immediate operands");
5599 else
5600 err_msg = _("RC/SAE operand must follow immediate operands");
5601 break;
5602 case invalid_register_operand:
5603 err_msg = _("invalid register operand");
5604 break;
5605 }
5606 as_bad (_("%s for `%s'"), err_msg,
5607 current_templates->start->name);
5608 return NULL;
5609 }
5610
5611 if (!quiet_warnings)
5612 {
5613 if (!intel_syntax
5614 && (i.types[0].bitfield.jumpabsolute
5615 != operand_types[0].bitfield.jumpabsolute))
5616 {
5617 as_warn (_("indirect %s without `*'"), t->name);
5618 }
5619
5620 if (t->opcode_modifier.isprefix
5621 && t->opcode_modifier.ignoresize)
5622 {
5623 /* Warn them that a data or address size prefix doesn't
5624 affect assembly of the next line of code. */
5625 as_warn (_("stand-alone `%s' prefix"), t->name);
5626 }
5627 }
5628
5629 /* Copy the template we found. */
5630 i.tm = *t;
5631
5632 if (addr_prefix_disp != -1)
5633 i.tm.operand_types[addr_prefix_disp]
5634 = operand_types[addr_prefix_disp];
5635
5636 if (found_reverse_match)
5637 {
5638 /* If we found a reverse match we must alter the opcode
5639 direction bit. found_reverse_match holds bits to change
5640 (different for int & float insns). */
5641
5642 i.tm.base_opcode ^= found_reverse_match;
5643
5644 i.tm.operand_types[0] = operand_types[1];
5645 i.tm.operand_types[1] = operand_types[0];
5646 }
5647
5648 return t;
5649 }
5650
5651 static int
5652 check_string (void)
5653 {
5654 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5655 if (i.tm.operand_types[mem_op].bitfield.esseg)
5656 {
5657 if (i.seg[0] != NULL && i.seg[0] != &es)
5658 {
5659 as_bad (_("`%s' operand %d must use `%ses' segment"),
5660 i.tm.name,
5661 mem_op + 1,
5662 register_prefix);
5663 return 0;
5664 }
5665 /* There's only ever one segment override allowed per instruction.
5666 This instruction possibly has a legal segment override on the
5667 second operand, so copy the segment to where non-string
5668 instructions store it, allowing common code. */
5669 i.seg[0] = i.seg[1];
5670 }
5671 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5672 {
5673 if (i.seg[1] != NULL && i.seg[1] != &es)
5674 {
5675 as_bad (_("`%s' operand %d must use `%ses' segment"),
5676 i.tm.name,
5677 mem_op + 2,
5678 register_prefix);
5679 return 0;
5680 }
5681 }
5682 return 1;
5683 }
5684
5685 static int
5686 process_suffix (void)
5687 {
5688 /* If matched instruction specifies an explicit instruction mnemonic
5689 suffix, use it. */
5690 if (i.tm.opcode_modifier.size16)
5691 i.suffix = WORD_MNEM_SUFFIX;
5692 else if (i.tm.opcode_modifier.size32)
5693 i.suffix = LONG_MNEM_SUFFIX;
5694 else if (i.tm.opcode_modifier.size64)
5695 i.suffix = QWORD_MNEM_SUFFIX;
5696 else if (i.reg_operands)
5697 {
5698 /* If there's no instruction mnemonic suffix we try to invent one
5699 based on register operands. */
5700 if (!i.suffix)
5701 {
5702 /* We take i.suffix from the last register operand specified,
5703 Destination register type is more significant than source
5704 register type. crc32 in SSE4.2 prefers source register
5705 type. */
5706 if (i.tm.base_opcode == 0xf20f38f1)
5707 {
5708 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5709 i.suffix = WORD_MNEM_SUFFIX;
5710 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5711 i.suffix = LONG_MNEM_SUFFIX;
5712 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5713 i.suffix = QWORD_MNEM_SUFFIX;
5714 }
5715 else if (i.tm.base_opcode == 0xf20f38f0)
5716 {
5717 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5718 i.suffix = BYTE_MNEM_SUFFIX;
5719 }
5720
5721 if (!i.suffix)
5722 {
5723 int op;
5724
5725 if (i.tm.base_opcode == 0xf20f38f1
5726 || i.tm.base_opcode == 0xf20f38f0)
5727 {
5728 /* We have to know the operand size for crc32. */
5729 as_bad (_("ambiguous memory operand size for `%s`"),
5730 i.tm.name);
5731 return 0;
5732 }
5733
5734 for (op = i.operands; --op >= 0;)
5735 if (!i.tm.operand_types[op].bitfield.inoutportreg
5736 && !i.tm.operand_types[op].bitfield.shiftcount)
5737 {
5738 if (!i.types[op].bitfield.reg)
5739 continue;
5740 if (i.types[op].bitfield.byte)
5741 i.suffix = BYTE_MNEM_SUFFIX;
5742 else if (i.types[op].bitfield.word)
5743 i.suffix = WORD_MNEM_SUFFIX;
5744 else if (i.types[op].bitfield.dword)
5745 i.suffix = LONG_MNEM_SUFFIX;
5746 else if (i.types[op].bitfield.qword)
5747 i.suffix = QWORD_MNEM_SUFFIX;
5748 else
5749 continue;
5750 break;
5751 }
5752 }
5753 }
5754 else if (i.suffix == BYTE_MNEM_SUFFIX)
5755 {
5756 if (intel_syntax
5757 && i.tm.opcode_modifier.ignoresize
5758 && i.tm.opcode_modifier.no_bsuf)
5759 i.suffix = 0;
5760 else if (!check_byte_reg ())
5761 return 0;
5762 }
5763 else if (i.suffix == LONG_MNEM_SUFFIX)
5764 {
5765 if (intel_syntax
5766 && i.tm.opcode_modifier.ignoresize
5767 && i.tm.opcode_modifier.no_lsuf)
5768 i.suffix = 0;
5769 else if (!check_long_reg ())
5770 return 0;
5771 }
5772 else if (i.suffix == QWORD_MNEM_SUFFIX)
5773 {
5774 if (intel_syntax
5775 && i.tm.opcode_modifier.ignoresize
5776 && i.tm.opcode_modifier.no_qsuf)
5777 i.suffix = 0;
5778 else if (!check_qword_reg ())
5779 return 0;
5780 }
5781 else if (i.suffix == WORD_MNEM_SUFFIX)
5782 {
5783 if (intel_syntax
5784 && i.tm.opcode_modifier.ignoresize
5785 && i.tm.opcode_modifier.no_wsuf)
5786 i.suffix = 0;
5787 else if (!check_word_reg ())
5788 return 0;
5789 }
5790 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5791 /* Do nothing if the instruction is going to ignore the prefix. */
5792 ;
5793 else
5794 abort ();
5795 }
5796 else if (i.tm.opcode_modifier.defaultsize
5797 && !i.suffix
5798 /* exclude fldenv/frstor/fsave/fstenv */
5799 && i.tm.opcode_modifier.no_ssuf)
5800 {
5801 i.suffix = stackop_size;
5802 }
5803 else if (intel_syntax
5804 && !i.suffix
5805 && (i.tm.operand_types[0].bitfield.jumpabsolute
5806 || i.tm.opcode_modifier.jumpbyte
5807 || i.tm.opcode_modifier.jumpintersegment
5808 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5809 && i.tm.extension_opcode <= 3)))
5810 {
5811 switch (flag_code)
5812 {
5813 case CODE_64BIT:
5814 if (!i.tm.opcode_modifier.no_qsuf)
5815 {
5816 i.suffix = QWORD_MNEM_SUFFIX;
5817 break;
5818 }
5819 /* Fall through. */
5820 case CODE_32BIT:
5821 if (!i.tm.opcode_modifier.no_lsuf)
5822 i.suffix = LONG_MNEM_SUFFIX;
5823 break;
5824 case CODE_16BIT:
5825 if (!i.tm.opcode_modifier.no_wsuf)
5826 i.suffix = WORD_MNEM_SUFFIX;
5827 break;
5828 }
5829 }
5830
5831 if (!i.suffix)
5832 {
5833 if (!intel_syntax)
5834 {
5835 if (i.tm.opcode_modifier.w)
5836 {
5837 as_bad (_("no instruction mnemonic suffix given and "
5838 "no register operands; can't size instruction"));
5839 return 0;
5840 }
5841 }
5842 else
5843 {
5844 unsigned int suffixes;
5845
5846 suffixes = !i.tm.opcode_modifier.no_bsuf;
5847 if (!i.tm.opcode_modifier.no_wsuf)
5848 suffixes |= 1 << 1;
5849 if (!i.tm.opcode_modifier.no_lsuf)
5850 suffixes |= 1 << 2;
5851 if (!i.tm.opcode_modifier.no_ldsuf)
5852 suffixes |= 1 << 3;
5853 if (!i.tm.opcode_modifier.no_ssuf)
5854 suffixes |= 1 << 4;
5855 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
5856 suffixes |= 1 << 5;
5857
5858 /* There are more than suffix matches. */
5859 if (i.tm.opcode_modifier.w
5860 || ((suffixes & (suffixes - 1))
5861 && !i.tm.opcode_modifier.defaultsize
5862 && !i.tm.opcode_modifier.ignoresize))
5863 {
5864 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5865 return 0;
5866 }
5867 }
5868 }
5869
5870 /* Change the opcode based on the operand size given by i.suffix. */
5871 switch (i.suffix)
5872 {
5873 /* Size floating point instruction. */
5874 case LONG_MNEM_SUFFIX:
5875 if (i.tm.opcode_modifier.floatmf)
5876 {
5877 i.tm.base_opcode ^= 4;
5878 break;
5879 }
5880 /* fall through */
5881 case WORD_MNEM_SUFFIX:
5882 case QWORD_MNEM_SUFFIX:
5883 /* It's not a byte, select word/dword operation. */
5884 if (i.tm.opcode_modifier.w)
5885 {
5886 if (i.tm.opcode_modifier.shortform)
5887 i.tm.base_opcode |= 8;
5888 else
5889 i.tm.base_opcode |= 1;
5890 }
5891 /* fall through */
5892 case SHORT_MNEM_SUFFIX:
5893 /* Now select between word & dword operations via the operand
5894 size prefix, except for instructions that will ignore this
5895 prefix anyway. */
5896 if (i.tm.opcode_modifier.addrprefixop0)
5897 {
5898 /* The address size override prefix changes the size of the
5899 first operand. */
5900 if ((flag_code == CODE_32BIT
5901 && i.op->regs[0].reg_type.bitfield.word)
5902 || (flag_code != CODE_32BIT
5903 && i.op->regs[0].reg_type.bitfield.dword))
5904 if (!add_prefix (ADDR_PREFIX_OPCODE))
5905 return 0;
5906 }
5907 else if (i.suffix != QWORD_MNEM_SUFFIX
5908 && !i.tm.opcode_modifier.ignoresize
5909 && !i.tm.opcode_modifier.floatmf
5910 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5911 || (flag_code == CODE_64BIT
5912 && i.tm.opcode_modifier.jumpbyte)))
5913 {
5914 unsigned int prefix = DATA_PREFIX_OPCODE;
5915
5916 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5917 prefix = ADDR_PREFIX_OPCODE;
5918
5919 if (!add_prefix (prefix))
5920 return 0;
5921 }
5922
5923 /* Set mode64 for an operand. */
5924 if (i.suffix == QWORD_MNEM_SUFFIX
5925 && flag_code == CODE_64BIT
5926 && !i.tm.opcode_modifier.norex64
5927 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5928 need rex64. */
5929 && ! (i.operands == 2
5930 && i.tm.base_opcode == 0x90
5931 && i.tm.extension_opcode == None
5932 && operand_type_equal (&i.types [0], &acc64)
5933 && operand_type_equal (&i.types [1], &acc64)))
5934 i.rex |= REX_W;
5935
5936 break;
5937 }
5938
5939 return 1;
5940 }
5941
5942 static int
5943 check_byte_reg (void)
5944 {
5945 int op;
5946
5947 for (op = i.operands; --op >= 0;)
5948 {
5949 /* Skip non-register operands. */
5950 if (!i.types[op].bitfield.reg)
5951 continue;
5952
5953 /* If this is an eight bit register, it's OK. If it's the 16 or
5954 32 bit version of an eight bit register, we will just use the
5955 low portion, and that's OK too. */
5956 if (i.types[op].bitfield.byte)
5957 continue;
5958
5959 /* I/O port address operands are OK too. */
5960 if (i.tm.operand_types[op].bitfield.inoutportreg)
5961 continue;
5962
5963 /* crc32 doesn't generate this warning. */
5964 if (i.tm.base_opcode == 0xf20f38f0)
5965 continue;
5966
5967 if ((i.types[op].bitfield.word
5968 || i.types[op].bitfield.dword
5969 || i.types[op].bitfield.qword)
5970 && i.op[op].regs->reg_num < 4
5971 /* Prohibit these changes in 64bit mode, since the lowering
5972 would be more complicated. */
5973 && flag_code != CODE_64BIT)
5974 {
5975 #if REGISTER_WARNINGS
5976 if (!quiet_warnings)
5977 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5978 register_prefix,
5979 (i.op[op].regs + (i.types[op].bitfield.word
5980 ? REGNAM_AL - REGNAM_AX
5981 : REGNAM_AL - REGNAM_EAX))->reg_name,
5982 register_prefix,
5983 i.op[op].regs->reg_name,
5984 i.suffix);
5985 #endif
5986 continue;
5987 }
5988 /* Any other register is bad. */
5989 if (i.types[op].bitfield.reg
5990 || i.types[op].bitfield.regmmx
5991 || i.types[op].bitfield.regsimd
5992 || i.types[op].bitfield.sreg2
5993 || i.types[op].bitfield.sreg3
5994 || i.types[op].bitfield.control
5995 || i.types[op].bitfield.debug
5996 || i.types[op].bitfield.test)
5997 {
5998 as_bad (_("`%s%s' not allowed with `%s%c'"),
5999 register_prefix,
6000 i.op[op].regs->reg_name,
6001 i.tm.name,
6002 i.suffix);
6003 return 0;
6004 }
6005 }
6006 return 1;
6007 }
6008
6009 static int
6010 check_long_reg (void)
6011 {
6012 int op;
6013
6014 for (op = i.operands; --op >= 0;)
6015 /* Skip non-register operands. */
6016 if (!i.types[op].bitfield.reg)
6017 continue;
6018 /* Reject eight bit registers, except where the template requires
6019 them. (eg. movzb) */
6020 else if (i.types[op].bitfield.byte
6021 && (i.tm.operand_types[op].bitfield.reg
6022 || i.tm.operand_types[op].bitfield.acc)
6023 && (i.tm.operand_types[op].bitfield.word
6024 || i.tm.operand_types[op].bitfield.dword))
6025 {
6026 as_bad (_("`%s%s' not allowed with `%s%c'"),
6027 register_prefix,
6028 i.op[op].regs->reg_name,
6029 i.tm.name,
6030 i.suffix);
6031 return 0;
6032 }
6033 /* Warn if the e prefix on a general reg is missing. */
6034 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6035 && i.types[op].bitfield.word
6036 && (i.tm.operand_types[op].bitfield.reg
6037 || i.tm.operand_types[op].bitfield.acc)
6038 && i.tm.operand_types[op].bitfield.dword)
6039 {
6040 /* Prohibit these changes in the 64bit mode, since the
6041 lowering is more complicated. */
6042 if (flag_code == CODE_64BIT)
6043 {
6044 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6045 register_prefix, i.op[op].regs->reg_name,
6046 i.suffix);
6047 return 0;
6048 }
6049 #if REGISTER_WARNINGS
6050 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6051 register_prefix,
6052 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6053 register_prefix, i.op[op].regs->reg_name, i.suffix);
6054 #endif
6055 }
6056 /* Warn if the r prefix on a general reg is present. */
6057 else if (i.types[op].bitfield.qword
6058 && (i.tm.operand_types[op].bitfield.reg
6059 || i.tm.operand_types[op].bitfield.acc)
6060 && i.tm.operand_types[op].bitfield.dword)
6061 {
6062 if (intel_syntax
6063 && i.tm.opcode_modifier.toqword
6064 && !i.types[0].bitfield.regsimd)
6065 {
6066 /* Convert to QWORD. We want REX byte. */
6067 i.suffix = QWORD_MNEM_SUFFIX;
6068 }
6069 else
6070 {
6071 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6072 register_prefix, i.op[op].regs->reg_name,
6073 i.suffix);
6074 return 0;
6075 }
6076 }
6077 return 1;
6078 }
6079
6080 static int
6081 check_qword_reg (void)
6082 {
6083 int op;
6084
6085 for (op = i.operands; --op >= 0; )
6086 /* Skip non-register operands. */
6087 if (!i.types[op].bitfield.reg)
6088 continue;
6089 /* Reject eight bit registers, except where the template requires
6090 them. (eg. movzb) */
6091 else if (i.types[op].bitfield.byte
6092 && (i.tm.operand_types[op].bitfield.reg
6093 || i.tm.operand_types[op].bitfield.acc)
6094 && (i.tm.operand_types[op].bitfield.word
6095 || i.tm.operand_types[op].bitfield.dword))
6096 {
6097 as_bad (_("`%s%s' not allowed with `%s%c'"),
6098 register_prefix,
6099 i.op[op].regs->reg_name,
6100 i.tm.name,
6101 i.suffix);
6102 return 0;
6103 }
6104 /* Warn if the r prefix on a general reg is missing. */
6105 else if ((i.types[op].bitfield.word
6106 || i.types[op].bitfield.dword)
6107 && (i.tm.operand_types[op].bitfield.reg
6108 || i.tm.operand_types[op].bitfield.acc)
6109 && i.tm.operand_types[op].bitfield.qword)
6110 {
6111 /* Prohibit these changes in the 64bit mode, since the
6112 lowering is more complicated. */
6113 if (intel_syntax
6114 && i.tm.opcode_modifier.todword
6115 && !i.types[0].bitfield.regsimd)
6116 {
6117 /* Convert to DWORD. We don't want REX byte. */
6118 i.suffix = LONG_MNEM_SUFFIX;
6119 }
6120 else
6121 {
6122 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6123 register_prefix, i.op[op].regs->reg_name,
6124 i.suffix);
6125 return 0;
6126 }
6127 }
6128 return 1;
6129 }
6130
6131 static int
6132 check_word_reg (void)
6133 {
6134 int op;
6135 for (op = i.operands; --op >= 0;)
6136 /* Skip non-register operands. */
6137 if (!i.types[op].bitfield.reg)
6138 continue;
6139 /* Reject eight bit registers, except where the template requires
6140 them. (eg. movzb) */
6141 else if (i.types[op].bitfield.byte
6142 && (i.tm.operand_types[op].bitfield.reg
6143 || i.tm.operand_types[op].bitfield.acc)
6144 && (i.tm.operand_types[op].bitfield.word
6145 || i.tm.operand_types[op].bitfield.dword))
6146 {
6147 as_bad (_("`%s%s' not allowed with `%s%c'"),
6148 register_prefix,
6149 i.op[op].regs->reg_name,
6150 i.tm.name,
6151 i.suffix);
6152 return 0;
6153 }
6154 /* Warn if the e or r prefix on a general reg is present. */
6155 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6156 && (i.types[op].bitfield.dword
6157 || i.types[op].bitfield.qword)
6158 && (i.tm.operand_types[op].bitfield.reg
6159 || i.tm.operand_types[op].bitfield.acc)
6160 && i.tm.operand_types[op].bitfield.word)
6161 {
6162 /* Prohibit these changes in the 64bit mode, since the
6163 lowering is more complicated. */
6164 if (flag_code == CODE_64BIT)
6165 {
6166 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6167 register_prefix, i.op[op].regs->reg_name,
6168 i.suffix);
6169 return 0;
6170 }
6171 #if REGISTER_WARNINGS
6172 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6173 register_prefix,
6174 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6175 register_prefix, i.op[op].regs->reg_name, i.suffix);
6176 #endif
6177 }
6178 return 1;
6179 }
6180
6181 static int
6182 update_imm (unsigned int j)
6183 {
6184 i386_operand_type overlap = i.types[j];
6185 if ((overlap.bitfield.imm8
6186 || overlap.bitfield.imm8s
6187 || overlap.bitfield.imm16
6188 || overlap.bitfield.imm32
6189 || overlap.bitfield.imm32s
6190 || overlap.bitfield.imm64)
6191 && !operand_type_equal (&overlap, &imm8)
6192 && !operand_type_equal (&overlap, &imm8s)
6193 && !operand_type_equal (&overlap, &imm16)
6194 && !operand_type_equal (&overlap, &imm32)
6195 && !operand_type_equal (&overlap, &imm32s)
6196 && !operand_type_equal (&overlap, &imm64))
6197 {
6198 if (i.suffix)
6199 {
6200 i386_operand_type temp;
6201
6202 operand_type_set (&temp, 0);
6203 if (i.suffix == BYTE_MNEM_SUFFIX)
6204 {
6205 temp.bitfield.imm8 = overlap.bitfield.imm8;
6206 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6207 }
6208 else if (i.suffix == WORD_MNEM_SUFFIX)
6209 temp.bitfield.imm16 = overlap.bitfield.imm16;
6210 else if (i.suffix == QWORD_MNEM_SUFFIX)
6211 {
6212 temp.bitfield.imm64 = overlap.bitfield.imm64;
6213 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6214 }
6215 else
6216 temp.bitfield.imm32 = overlap.bitfield.imm32;
6217 overlap = temp;
6218 }
6219 else if (operand_type_equal (&overlap, &imm16_32_32s)
6220 || operand_type_equal (&overlap, &imm16_32)
6221 || operand_type_equal (&overlap, &imm16_32s))
6222 {
6223 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6224 overlap = imm16;
6225 else
6226 overlap = imm32s;
6227 }
6228 if (!operand_type_equal (&overlap, &imm8)
6229 && !operand_type_equal (&overlap, &imm8s)
6230 && !operand_type_equal (&overlap, &imm16)
6231 && !operand_type_equal (&overlap, &imm32)
6232 && !operand_type_equal (&overlap, &imm32s)
6233 && !operand_type_equal (&overlap, &imm64))
6234 {
6235 as_bad (_("no instruction mnemonic suffix given; "
6236 "can't determine immediate size"));
6237 return 0;
6238 }
6239 }
6240 i.types[j] = overlap;
6241
6242 return 1;
6243 }
6244
6245 static int
6246 finalize_imm (void)
6247 {
6248 unsigned int j, n;
6249
6250 /* Update the first 2 immediate operands. */
6251 n = i.operands > 2 ? 2 : i.operands;
6252 if (n)
6253 {
6254 for (j = 0; j < n; j++)
6255 if (update_imm (j) == 0)
6256 return 0;
6257
6258 /* The 3rd operand can't be immediate operand. */
6259 gas_assert (operand_type_check (i.types[2], imm) == 0);
6260 }
6261
6262 return 1;
6263 }
6264
6265 static int
6266 process_operands (void)
6267 {
6268 /* Default segment register this instruction will use for memory
6269 accesses. 0 means unknown. This is only for optimizing out
6270 unnecessary segment overrides. */
6271 const seg_entry *default_seg = 0;
6272
6273 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6274 {
6275 unsigned int dupl = i.operands;
6276 unsigned int dest = dupl - 1;
6277 unsigned int j;
6278
6279 /* The destination must be an xmm register. */
6280 gas_assert (i.reg_operands
6281 && MAX_OPERANDS > dupl
6282 && operand_type_equal (&i.types[dest], &regxmm));
6283
6284 if (i.tm.operand_types[0].bitfield.acc
6285 && i.tm.operand_types[0].bitfield.xmmword)
6286 {
6287 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6288 {
6289 /* Keep xmm0 for instructions with VEX prefix and 3
6290 sources. */
6291 i.tm.operand_types[0].bitfield.acc = 0;
6292 i.tm.operand_types[0].bitfield.regsimd = 1;
6293 goto duplicate;
6294 }
6295 else
6296 {
6297 /* We remove the first xmm0 and keep the number of
6298 operands unchanged, which in fact duplicates the
6299 destination. */
6300 for (j = 1; j < i.operands; j++)
6301 {
6302 i.op[j - 1] = i.op[j];
6303 i.types[j - 1] = i.types[j];
6304 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6305 }
6306 }
6307 }
6308 else if (i.tm.opcode_modifier.implicit1stxmm0)
6309 {
6310 gas_assert ((MAX_OPERANDS - 1) > dupl
6311 && (i.tm.opcode_modifier.vexsources
6312 == VEX3SOURCES));
6313
6314 /* Add the implicit xmm0 for instructions with VEX prefix
6315 and 3 sources. */
6316 for (j = i.operands; j > 0; j--)
6317 {
6318 i.op[j] = i.op[j - 1];
6319 i.types[j] = i.types[j - 1];
6320 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6321 }
6322 i.op[0].regs
6323 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6324 i.types[0] = regxmm;
6325 i.tm.operand_types[0] = regxmm;
6326
6327 i.operands += 2;
6328 i.reg_operands += 2;
6329 i.tm.operands += 2;
6330
6331 dupl++;
6332 dest++;
6333 i.op[dupl] = i.op[dest];
6334 i.types[dupl] = i.types[dest];
6335 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6336 }
6337 else
6338 {
6339 duplicate:
6340 i.operands++;
6341 i.reg_operands++;
6342 i.tm.operands++;
6343
6344 i.op[dupl] = i.op[dest];
6345 i.types[dupl] = i.types[dest];
6346 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6347 }
6348
6349 if (i.tm.opcode_modifier.immext)
6350 process_immext ();
6351 }
6352 else if (i.tm.operand_types[0].bitfield.acc
6353 && i.tm.operand_types[0].bitfield.xmmword)
6354 {
6355 unsigned int j;
6356
6357 for (j = 1; j < i.operands; j++)
6358 {
6359 i.op[j - 1] = i.op[j];
6360 i.types[j - 1] = i.types[j];
6361
6362 /* We need to adjust fields in i.tm since they are used by
6363 build_modrm_byte. */
6364 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6365 }
6366
6367 i.operands--;
6368 i.reg_operands--;
6369 i.tm.operands--;
6370 }
6371 else if (i.tm.opcode_modifier.implicitquadgroup)
6372 {
6373 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6374
6375 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6376 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6377 regnum = register_number (i.op[1].regs);
6378 first_reg_in_group = regnum & ~3;
6379 last_reg_in_group = first_reg_in_group + 3;
6380 if (regnum != first_reg_in_group)
6381 as_warn (_("source register `%s%s' implicitly denotes"
6382 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6383 register_prefix, i.op[1].regs->reg_name,
6384 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6385 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6386 i.tm.name);
6387 }
6388 else if (i.tm.opcode_modifier.regkludge)
6389 {
6390 /* The imul $imm, %reg instruction is converted into
6391 imul $imm, %reg, %reg, and the clr %reg instruction
6392 is converted into xor %reg, %reg. */
6393
6394 unsigned int first_reg_op;
6395
6396 if (operand_type_check (i.types[0], reg))
6397 first_reg_op = 0;
6398 else
6399 first_reg_op = 1;
6400 /* Pretend we saw the extra register operand. */
6401 gas_assert (i.reg_operands == 1
6402 && i.op[first_reg_op + 1].regs == 0);
6403 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6404 i.types[first_reg_op + 1] = i.types[first_reg_op];
6405 i.operands++;
6406 i.reg_operands++;
6407 }
6408
6409 if (i.tm.opcode_modifier.shortform)
6410 {
6411 if (i.types[0].bitfield.sreg2
6412 || i.types[0].bitfield.sreg3)
6413 {
6414 if (i.tm.base_opcode == POP_SEG_SHORT
6415 && i.op[0].regs->reg_num == 1)
6416 {
6417 as_bad (_("you can't `pop %scs'"), register_prefix);
6418 return 0;
6419 }
6420 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6421 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6422 i.rex |= REX_B;
6423 }
6424 else
6425 {
6426 /* The register or float register operand is in operand
6427 0 or 1. */
6428 unsigned int op;
6429
6430 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6431 || operand_type_check (i.types[0], reg))
6432 op = 0;
6433 else
6434 op = 1;
6435 /* Register goes in low 3 bits of opcode. */
6436 i.tm.base_opcode |= i.op[op].regs->reg_num;
6437 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6438 i.rex |= REX_B;
6439 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6440 {
6441 /* Warn about some common errors, but press on regardless.
6442 The first case can be generated by gcc (<= 2.8.1). */
6443 if (i.operands == 2)
6444 {
6445 /* Reversed arguments on faddp, fsubp, etc. */
6446 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6447 register_prefix, i.op[!intel_syntax].regs->reg_name,
6448 register_prefix, i.op[intel_syntax].regs->reg_name);
6449 }
6450 else
6451 {
6452 /* Extraneous `l' suffix on fp insn. */
6453 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6454 register_prefix, i.op[0].regs->reg_name);
6455 }
6456 }
6457 }
6458 }
6459 else if (i.tm.opcode_modifier.modrm)
6460 {
6461 /* The opcode is completed (modulo i.tm.extension_opcode which
6462 must be put into the modrm byte). Now, we make the modrm and
6463 index base bytes based on all the info we've collected. */
6464
6465 default_seg = build_modrm_byte ();
6466 }
6467 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6468 {
6469 default_seg = &ds;
6470 }
6471 else if (i.tm.opcode_modifier.isstring)
6472 {
6473 /* For the string instructions that allow a segment override
6474 on one of their operands, the default segment is ds. */
6475 default_seg = &ds;
6476 }
6477
6478 if (i.tm.base_opcode == 0x8d /* lea */
6479 && i.seg[0]
6480 && !quiet_warnings)
6481 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6482
6483 /* If a segment was explicitly specified, and the specified segment
6484 is not the default, use an opcode prefix to select it. If we
6485 never figured out what the default segment is, then default_seg
6486 will be zero at this point, and the specified segment prefix will
6487 always be used. */
6488 if ((i.seg[0]) && (i.seg[0] != default_seg))
6489 {
6490 if (!add_prefix (i.seg[0]->seg_prefix))
6491 return 0;
6492 }
6493 return 1;
6494 }
6495
6496 static const seg_entry *
6497 build_modrm_byte (void)
6498 {
6499 const seg_entry *default_seg = 0;
6500 unsigned int source, dest;
6501 int vex_3_sources;
6502
6503 /* The first operand of instructions with VEX prefix and 3 sources
6504 must be VEX_Imm4. */
6505 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6506 if (vex_3_sources)
6507 {
6508 unsigned int nds, reg_slot;
6509 expressionS *exp;
6510
6511 if (i.tm.opcode_modifier.veximmext
6512 && i.tm.opcode_modifier.immext)
6513 {
6514 dest = i.operands - 2;
6515 gas_assert (dest == 3);
6516 }
6517 else
6518 dest = i.operands - 1;
6519 nds = dest - 1;
6520
6521 /* There are 2 kinds of instructions:
6522 1. 5 operands: 4 register operands or 3 register operands
6523 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6524 VexW0 or VexW1. The destination must be either XMM, YMM or
6525 ZMM register.
6526 2. 4 operands: 4 register operands or 3 register operands
6527 plus 1 memory operand, VexXDS, and VexImmExt */
6528 gas_assert ((i.reg_operands == 4
6529 || (i.reg_operands == 3 && i.mem_operands == 1))
6530 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6531 && (i.tm.opcode_modifier.veximmext
6532 || (i.imm_operands == 1
6533 && i.types[0].bitfield.vec_imm4
6534 && (i.tm.opcode_modifier.vexw == VEXW0
6535 || i.tm.opcode_modifier.vexw == VEXW1)
6536 && i.tm.operand_types[dest].bitfield.regsimd)));
6537
6538 if (i.imm_operands == 0)
6539 {
6540 /* When there is no immediate operand, generate an 8bit
6541 immediate operand to encode the first operand. */
6542 exp = &im_expressions[i.imm_operands++];
6543 i.op[i.operands].imms = exp;
6544 i.types[i.operands] = imm8;
6545 i.operands++;
6546 /* If VexW1 is set, the first operand is the source and
6547 the second operand is encoded in the immediate operand. */
6548 if (i.tm.opcode_modifier.vexw == VEXW1)
6549 {
6550 source = 0;
6551 reg_slot = 1;
6552 }
6553 else
6554 {
6555 source = 1;
6556 reg_slot = 0;
6557 }
6558
6559 /* FMA swaps REG and NDS. */
6560 if (i.tm.cpu_flags.bitfield.cpufma)
6561 {
6562 unsigned int tmp;
6563 tmp = reg_slot;
6564 reg_slot = nds;
6565 nds = tmp;
6566 }
6567
6568 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6569 exp->X_op = O_constant;
6570 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6571 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6572 }
6573 else
6574 {
6575 unsigned int imm_slot;
6576
6577 if (i.tm.opcode_modifier.vexw == VEXW0)
6578 {
6579 /* If VexW0 is set, the third operand is the source and
6580 the second operand is encoded in the immediate
6581 operand. */
6582 source = 2;
6583 reg_slot = 1;
6584 }
6585 else
6586 {
6587 /* VexW1 is set, the second operand is the source and
6588 the third operand is encoded in the immediate
6589 operand. */
6590 source = 1;
6591 reg_slot = 2;
6592 }
6593
6594 if (i.tm.opcode_modifier.immext)
6595 {
6596 /* When ImmExt is set, the immediate byte is the last
6597 operand. */
6598 imm_slot = i.operands - 1;
6599 source--;
6600 reg_slot--;
6601 }
6602 else
6603 {
6604 imm_slot = 0;
6605
6606 /* Turn on Imm8 so that output_imm will generate it. */
6607 i.types[imm_slot].bitfield.imm8 = 1;
6608 }
6609
6610 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6611 i.op[imm_slot].imms->X_add_number
6612 |= register_number (i.op[reg_slot].regs) << 4;
6613 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6614 }
6615
6616 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6617 i.vex.register_specifier = i.op[nds].regs;
6618 }
6619 else
6620 source = dest = 0;
6621
6622 /* i.reg_operands MUST be the number of real register operands;
6623 implicit registers do not count. If there are 3 register
6624 operands, it must be a instruction with VexNDS. For a
6625 instruction with VexNDD, the destination register is encoded
6626 in VEX prefix. If there are 4 register operands, it must be
6627 a instruction with VEX prefix and 3 sources. */
6628 if (i.mem_operands == 0
6629 && ((i.reg_operands == 2
6630 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6631 || (i.reg_operands == 3
6632 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6633 || (i.reg_operands == 4 && vex_3_sources)))
6634 {
6635 switch (i.operands)
6636 {
6637 case 2:
6638 source = 0;
6639 break;
6640 case 3:
6641 /* When there are 3 operands, one of them may be immediate,
6642 which may be the first or the last operand. Otherwise,
6643 the first operand must be shift count register (cl) or it
6644 is an instruction with VexNDS. */
6645 gas_assert (i.imm_operands == 1
6646 || (i.imm_operands == 0
6647 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6648 || i.types[0].bitfield.shiftcount)));
6649 if (operand_type_check (i.types[0], imm)
6650 || i.types[0].bitfield.shiftcount)
6651 source = 1;
6652 else
6653 source = 0;
6654 break;
6655 case 4:
6656 /* When there are 4 operands, the first two must be 8bit
6657 immediate operands. The source operand will be the 3rd
6658 one.
6659
6660 For instructions with VexNDS, if the first operand
6661 an imm8, the source operand is the 2nd one. If the last
6662 operand is imm8, the source operand is the first one. */
6663 gas_assert ((i.imm_operands == 2
6664 && i.types[0].bitfield.imm8
6665 && i.types[1].bitfield.imm8)
6666 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6667 && i.imm_operands == 1
6668 && (i.types[0].bitfield.imm8
6669 || i.types[i.operands - 1].bitfield.imm8
6670 || i.rounding)));
6671 if (i.imm_operands == 2)
6672 source = 2;
6673 else
6674 {
6675 if (i.types[0].bitfield.imm8)
6676 source = 1;
6677 else
6678 source = 0;
6679 }
6680 break;
6681 case 5:
6682 if (i.tm.opcode_modifier.evex)
6683 {
6684 /* For EVEX instructions, when there are 5 operands, the
6685 first one must be immediate operand. If the second one
6686 is immediate operand, the source operand is the 3th
6687 one. If the last one is immediate operand, the source
6688 operand is the 2nd one. */
6689 gas_assert (i.imm_operands == 2
6690 && i.tm.opcode_modifier.sae
6691 && operand_type_check (i.types[0], imm));
6692 if (operand_type_check (i.types[1], imm))
6693 source = 2;
6694 else if (operand_type_check (i.types[4], imm))
6695 source = 1;
6696 else
6697 abort ();
6698 }
6699 break;
6700 default:
6701 abort ();
6702 }
6703
6704 if (!vex_3_sources)
6705 {
6706 dest = source + 1;
6707
6708 /* RC/SAE operand could be between DEST and SRC. That happens
6709 when one operand is GPR and the other one is XMM/YMM/ZMM
6710 register. */
6711 if (i.rounding && i.rounding->operand == (int) dest)
6712 dest++;
6713
6714 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6715 {
6716 /* For instructions with VexNDS, the register-only source
6717 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6718 register. It is encoded in VEX prefix. We need to
6719 clear RegMem bit before calling operand_type_equal. */
6720
6721 i386_operand_type op;
6722 unsigned int vvvv;
6723
6724 /* Check register-only source operand when two source
6725 operands are swapped. */
6726 if (!i.tm.operand_types[source].bitfield.baseindex
6727 && i.tm.operand_types[dest].bitfield.baseindex)
6728 {
6729 vvvv = source;
6730 source = dest;
6731 }
6732 else
6733 vvvv = dest;
6734
6735 op = i.tm.operand_types[vvvv];
6736 op.bitfield.regmem = 0;
6737 if ((dest + 1) >= i.operands
6738 || ((!op.bitfield.reg
6739 || (!op.bitfield.dword && !op.bitfield.qword))
6740 && !op.bitfield.regsimd
6741 && !operand_type_equal (&op, &regmask)))
6742 abort ();
6743 i.vex.register_specifier = i.op[vvvv].regs;
6744 dest++;
6745 }
6746 }
6747
6748 i.rm.mode = 3;
6749 /* One of the register operands will be encoded in the i.tm.reg
6750 field, the other in the combined i.tm.mode and i.tm.regmem
6751 fields. If no form of this instruction supports a memory
6752 destination operand, then we assume the source operand may
6753 sometimes be a memory operand and so we need to store the
6754 destination in the i.rm.reg field. */
6755 if (!i.tm.operand_types[dest].bitfield.regmem
6756 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6757 {
6758 i.rm.reg = i.op[dest].regs->reg_num;
6759 i.rm.regmem = i.op[source].regs->reg_num;
6760 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6761 i.rex |= REX_R;
6762 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6763 i.vrex |= REX_R;
6764 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6765 i.rex |= REX_B;
6766 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6767 i.vrex |= REX_B;
6768 }
6769 else
6770 {
6771 i.rm.reg = i.op[source].regs->reg_num;
6772 i.rm.regmem = i.op[dest].regs->reg_num;
6773 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6774 i.rex |= REX_B;
6775 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6776 i.vrex |= REX_B;
6777 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6778 i.rex |= REX_R;
6779 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6780 i.vrex |= REX_R;
6781 }
6782 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6783 {
6784 if (!i.types[0].bitfield.control
6785 && !i.types[1].bitfield.control)
6786 abort ();
6787 i.rex &= ~(REX_R | REX_B);
6788 add_prefix (LOCK_PREFIX_OPCODE);
6789 }
6790 }
6791 else
6792 { /* If it's not 2 reg operands... */
6793 unsigned int mem;
6794
6795 if (i.mem_operands)
6796 {
6797 unsigned int fake_zero_displacement = 0;
6798 unsigned int op;
6799
6800 for (op = 0; op < i.operands; op++)
6801 if (operand_type_check (i.types[op], anymem))
6802 break;
6803 gas_assert (op < i.operands);
6804
6805 if (i.tm.opcode_modifier.vecsib)
6806 {
6807 if (i.index_reg->reg_num == RegEiz
6808 || i.index_reg->reg_num == RegRiz)
6809 abort ();
6810
6811 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6812 if (!i.base_reg)
6813 {
6814 i.sib.base = NO_BASE_REGISTER;
6815 i.sib.scale = i.log2_scale_factor;
6816 i.types[op].bitfield.disp8 = 0;
6817 i.types[op].bitfield.disp16 = 0;
6818 i.types[op].bitfield.disp64 = 0;
6819 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6820 {
6821 /* Must be 32 bit */
6822 i.types[op].bitfield.disp32 = 1;
6823 i.types[op].bitfield.disp32s = 0;
6824 }
6825 else
6826 {
6827 i.types[op].bitfield.disp32 = 0;
6828 i.types[op].bitfield.disp32s = 1;
6829 }
6830 }
6831 i.sib.index = i.index_reg->reg_num;
6832 if ((i.index_reg->reg_flags & RegRex) != 0)
6833 i.rex |= REX_X;
6834 if ((i.index_reg->reg_flags & RegVRex) != 0)
6835 i.vrex |= REX_X;
6836 }
6837
6838 default_seg = &ds;
6839
6840 if (i.base_reg == 0)
6841 {
6842 i.rm.mode = 0;
6843 if (!i.disp_operands)
6844 fake_zero_displacement = 1;
6845 if (i.index_reg == 0)
6846 {
6847 i386_operand_type newdisp;
6848
6849 gas_assert (!i.tm.opcode_modifier.vecsib);
6850 /* Operand is just <disp> */
6851 if (flag_code == CODE_64BIT)
6852 {
6853 /* 64bit mode overwrites the 32bit absolute
6854 addressing by RIP relative addressing and
6855 absolute addressing is encoded by one of the
6856 redundant SIB forms. */
6857 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6858 i.sib.base = NO_BASE_REGISTER;
6859 i.sib.index = NO_INDEX_REGISTER;
6860 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
6861 }
6862 else if ((flag_code == CODE_16BIT)
6863 ^ (i.prefix[ADDR_PREFIX] != 0))
6864 {
6865 i.rm.regmem = NO_BASE_REGISTER_16;
6866 newdisp = disp16;
6867 }
6868 else
6869 {
6870 i.rm.regmem = NO_BASE_REGISTER;
6871 newdisp = disp32;
6872 }
6873 i.types[op] = operand_type_and_not (i.types[op], anydisp);
6874 i.types[op] = operand_type_or (i.types[op], newdisp);
6875 }
6876 else if (!i.tm.opcode_modifier.vecsib)
6877 {
6878 /* !i.base_reg && i.index_reg */
6879 if (i.index_reg->reg_num == RegEiz
6880 || i.index_reg->reg_num == RegRiz)
6881 i.sib.index = NO_INDEX_REGISTER;
6882 else
6883 i.sib.index = i.index_reg->reg_num;
6884 i.sib.base = NO_BASE_REGISTER;
6885 i.sib.scale = i.log2_scale_factor;
6886 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6887 i.types[op].bitfield.disp8 = 0;
6888 i.types[op].bitfield.disp16 = 0;
6889 i.types[op].bitfield.disp64 = 0;
6890 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6891 {
6892 /* Must be 32 bit */
6893 i.types[op].bitfield.disp32 = 1;
6894 i.types[op].bitfield.disp32s = 0;
6895 }
6896 else
6897 {
6898 i.types[op].bitfield.disp32 = 0;
6899 i.types[op].bitfield.disp32s = 1;
6900 }
6901 if ((i.index_reg->reg_flags & RegRex) != 0)
6902 i.rex |= REX_X;
6903 }
6904 }
6905 /* RIP addressing for 64bit mode. */
6906 else if (i.base_reg->reg_num == RegRip ||
6907 i.base_reg->reg_num == RegEip)
6908 {
6909 gas_assert (!i.tm.opcode_modifier.vecsib);
6910 i.rm.regmem = NO_BASE_REGISTER;
6911 i.types[op].bitfield.disp8 = 0;
6912 i.types[op].bitfield.disp16 = 0;
6913 i.types[op].bitfield.disp32 = 0;
6914 i.types[op].bitfield.disp32s = 1;
6915 i.types[op].bitfield.disp64 = 0;
6916 i.flags[op] |= Operand_PCrel;
6917 if (! i.disp_operands)
6918 fake_zero_displacement = 1;
6919 }
6920 else if (i.base_reg->reg_type.bitfield.word)
6921 {
6922 gas_assert (!i.tm.opcode_modifier.vecsib);
6923 switch (i.base_reg->reg_num)
6924 {
6925 case 3: /* (%bx) */
6926 if (i.index_reg == 0)
6927 i.rm.regmem = 7;
6928 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6929 i.rm.regmem = i.index_reg->reg_num - 6;
6930 break;
6931 case 5: /* (%bp) */
6932 default_seg = &ss;
6933 if (i.index_reg == 0)
6934 {
6935 i.rm.regmem = 6;
6936 if (operand_type_check (i.types[op], disp) == 0)
6937 {
6938 /* fake (%bp) into 0(%bp) */
6939 i.types[op].bitfield.disp8 = 1;
6940 fake_zero_displacement = 1;
6941 }
6942 }
6943 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6944 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6945 break;
6946 default: /* (%si) -> 4 or (%di) -> 5 */
6947 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6948 }
6949 i.rm.mode = mode_from_disp_size (i.types[op]);
6950 }
6951 else /* i.base_reg and 32/64 bit mode */
6952 {
6953 if (flag_code == CODE_64BIT
6954 && operand_type_check (i.types[op], disp))
6955 {
6956 i.types[op].bitfield.disp16 = 0;
6957 i.types[op].bitfield.disp64 = 0;
6958 if (i.prefix[ADDR_PREFIX] == 0)
6959 {
6960 i.types[op].bitfield.disp32 = 0;
6961 i.types[op].bitfield.disp32s = 1;
6962 }
6963 else
6964 {
6965 i.types[op].bitfield.disp32 = 1;
6966 i.types[op].bitfield.disp32s = 0;
6967 }
6968 }
6969
6970 if (!i.tm.opcode_modifier.vecsib)
6971 i.rm.regmem = i.base_reg->reg_num;
6972 if ((i.base_reg->reg_flags & RegRex) != 0)
6973 i.rex |= REX_B;
6974 i.sib.base = i.base_reg->reg_num;
6975 /* x86-64 ignores REX prefix bit here to avoid decoder
6976 complications. */
6977 if (!(i.base_reg->reg_flags & RegRex)
6978 && (i.base_reg->reg_num == EBP_REG_NUM
6979 || i.base_reg->reg_num == ESP_REG_NUM))
6980 default_seg = &ss;
6981 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
6982 {
6983 fake_zero_displacement = 1;
6984 i.types[op].bitfield.disp8 = 1;
6985 }
6986 i.sib.scale = i.log2_scale_factor;
6987 if (i.index_reg == 0)
6988 {
6989 gas_assert (!i.tm.opcode_modifier.vecsib);
6990 /* <disp>(%esp) becomes two byte modrm with no index
6991 register. We've already stored the code for esp
6992 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6993 Any base register besides %esp will not use the
6994 extra modrm byte. */
6995 i.sib.index = NO_INDEX_REGISTER;
6996 }
6997 else if (!i.tm.opcode_modifier.vecsib)
6998 {
6999 if (i.index_reg->reg_num == RegEiz
7000 || i.index_reg->reg_num == RegRiz)
7001 i.sib.index = NO_INDEX_REGISTER;
7002 else
7003 i.sib.index = i.index_reg->reg_num;
7004 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7005 if ((i.index_reg->reg_flags & RegRex) != 0)
7006 i.rex |= REX_X;
7007 }
7008
7009 if (i.disp_operands
7010 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7011 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7012 i.rm.mode = 0;
7013 else
7014 {
7015 if (!fake_zero_displacement
7016 && !i.disp_operands
7017 && i.disp_encoding)
7018 {
7019 fake_zero_displacement = 1;
7020 if (i.disp_encoding == disp_encoding_8bit)
7021 i.types[op].bitfield.disp8 = 1;
7022 else
7023 i.types[op].bitfield.disp32 = 1;
7024 }
7025 i.rm.mode = mode_from_disp_size (i.types[op]);
7026 }
7027 }
7028
7029 if (fake_zero_displacement)
7030 {
7031 /* Fakes a zero displacement assuming that i.types[op]
7032 holds the correct displacement size. */
7033 expressionS *exp;
7034
7035 gas_assert (i.op[op].disps == 0);
7036 exp = &disp_expressions[i.disp_operands++];
7037 i.op[op].disps = exp;
7038 exp->X_op = O_constant;
7039 exp->X_add_number = 0;
7040 exp->X_add_symbol = (symbolS *) 0;
7041 exp->X_op_symbol = (symbolS *) 0;
7042 }
7043
7044 mem = op;
7045 }
7046 else
7047 mem = ~0;
7048
7049 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7050 {
7051 if (operand_type_check (i.types[0], imm))
7052 i.vex.register_specifier = NULL;
7053 else
7054 {
7055 /* VEX.vvvv encodes one of the sources when the first
7056 operand is not an immediate. */
7057 if (i.tm.opcode_modifier.vexw == VEXW0)
7058 i.vex.register_specifier = i.op[0].regs;
7059 else
7060 i.vex.register_specifier = i.op[1].regs;
7061 }
7062
7063 /* Destination is a XMM register encoded in the ModRM.reg
7064 and VEX.R bit. */
7065 i.rm.reg = i.op[2].regs->reg_num;
7066 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7067 i.rex |= REX_R;
7068
7069 /* ModRM.rm and VEX.B encodes the other source. */
7070 if (!i.mem_operands)
7071 {
7072 i.rm.mode = 3;
7073
7074 if (i.tm.opcode_modifier.vexw == VEXW0)
7075 i.rm.regmem = i.op[1].regs->reg_num;
7076 else
7077 i.rm.regmem = i.op[0].regs->reg_num;
7078
7079 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7080 i.rex |= REX_B;
7081 }
7082 }
7083 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7084 {
7085 i.vex.register_specifier = i.op[2].regs;
7086 if (!i.mem_operands)
7087 {
7088 i.rm.mode = 3;
7089 i.rm.regmem = i.op[1].regs->reg_num;
7090 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7091 i.rex |= REX_B;
7092 }
7093 }
7094 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7095 (if any) based on i.tm.extension_opcode. Again, we must be
7096 careful to make sure that segment/control/debug/test/MMX
7097 registers are coded into the i.rm.reg field. */
7098 else if (i.reg_operands)
7099 {
7100 unsigned int op;
7101 unsigned int vex_reg = ~0;
7102
7103 for (op = 0; op < i.operands; op++)
7104 if (i.types[op].bitfield.reg
7105 || i.types[op].bitfield.regmmx
7106 || i.types[op].bitfield.regsimd
7107 || i.types[op].bitfield.regbnd
7108 || i.types[op].bitfield.regmask
7109 || i.types[op].bitfield.sreg2
7110 || i.types[op].bitfield.sreg3
7111 || i.types[op].bitfield.control
7112 || i.types[op].bitfield.debug
7113 || i.types[op].bitfield.test)
7114 break;
7115
7116 if (vex_3_sources)
7117 op = dest;
7118 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7119 {
7120 /* For instructions with VexNDS, the register-only
7121 source operand is encoded in VEX prefix. */
7122 gas_assert (mem != (unsigned int) ~0);
7123
7124 if (op > mem)
7125 {
7126 vex_reg = op++;
7127 gas_assert (op < i.operands);
7128 }
7129 else
7130 {
7131 /* Check register-only source operand when two source
7132 operands are swapped. */
7133 if (!i.tm.operand_types[op].bitfield.baseindex
7134 && i.tm.operand_types[op + 1].bitfield.baseindex)
7135 {
7136 vex_reg = op;
7137 op += 2;
7138 gas_assert (mem == (vex_reg + 1)
7139 && op < i.operands);
7140 }
7141 else
7142 {
7143 vex_reg = op + 1;
7144 gas_assert (vex_reg < i.operands);
7145 }
7146 }
7147 }
7148 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7149 {
7150 /* For instructions with VexNDD, the register destination
7151 is encoded in VEX prefix. */
7152 if (i.mem_operands == 0)
7153 {
7154 /* There is no memory operand. */
7155 gas_assert ((op + 2) == i.operands);
7156 vex_reg = op + 1;
7157 }
7158 else
7159 {
7160 /* There are only 2 non-immediate operands. */
7161 gas_assert (op < i.imm_operands + 2
7162 && i.operands == i.imm_operands + 2);
7163 vex_reg = i.imm_operands + 1;
7164 }
7165 }
7166 else
7167 gas_assert (op < i.operands);
7168
7169 if (vex_reg != (unsigned int) ~0)
7170 {
7171 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7172
7173 if ((!type->bitfield.reg
7174 || (!type->bitfield.dword && !type->bitfield.qword))
7175 && !type->bitfield.regsimd
7176 && !operand_type_equal (type, &regmask))
7177 abort ();
7178
7179 i.vex.register_specifier = i.op[vex_reg].regs;
7180 }
7181
7182 /* Don't set OP operand twice. */
7183 if (vex_reg != op)
7184 {
7185 /* If there is an extension opcode to put here, the
7186 register number must be put into the regmem field. */
7187 if (i.tm.extension_opcode != None)
7188 {
7189 i.rm.regmem = i.op[op].regs->reg_num;
7190 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7191 i.rex |= REX_B;
7192 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7193 i.vrex |= REX_B;
7194 }
7195 else
7196 {
7197 i.rm.reg = i.op[op].regs->reg_num;
7198 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7199 i.rex |= REX_R;
7200 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7201 i.vrex |= REX_R;
7202 }
7203 }
7204
7205 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7206 must set it to 3 to indicate this is a register operand
7207 in the regmem field. */
7208 if (!i.mem_operands)
7209 i.rm.mode = 3;
7210 }
7211
7212 /* Fill in i.rm.reg field with extension opcode (if any). */
7213 if (i.tm.extension_opcode != None)
7214 i.rm.reg = i.tm.extension_opcode;
7215 }
7216 return default_seg;
7217 }
7218
7219 static void
7220 output_branch (void)
7221 {
7222 char *p;
7223 int size;
7224 int code16;
7225 int prefix;
7226 relax_substateT subtype;
7227 symbolS *sym;
7228 offsetT off;
7229
7230 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7231 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7232
7233 prefix = 0;
7234 if (i.prefix[DATA_PREFIX] != 0)
7235 {
7236 prefix = 1;
7237 i.prefixes -= 1;
7238 code16 ^= CODE16;
7239 }
7240 /* Pentium4 branch hints. */
7241 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7242 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7243 {
7244 prefix++;
7245 i.prefixes--;
7246 }
7247 if (i.prefix[REX_PREFIX] != 0)
7248 {
7249 prefix++;
7250 i.prefixes--;
7251 }
7252
7253 /* BND prefixed jump. */
7254 if (i.prefix[BND_PREFIX] != 0)
7255 {
7256 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7257 i.prefixes -= 1;
7258 }
7259
7260 if (i.prefixes != 0 && !intel_syntax)
7261 as_warn (_("skipping prefixes on this instruction"));
7262
7263 /* It's always a symbol; End frag & setup for relax.
7264 Make sure there is enough room in this frag for the largest
7265 instruction we may generate in md_convert_frag. This is 2
7266 bytes for the opcode and room for the prefix and largest
7267 displacement. */
7268 frag_grow (prefix + 2 + 4);
7269 /* Prefix and 1 opcode byte go in fr_fix. */
7270 p = frag_more (prefix + 1);
7271 if (i.prefix[DATA_PREFIX] != 0)
7272 *p++ = DATA_PREFIX_OPCODE;
7273 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7274 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7275 *p++ = i.prefix[SEG_PREFIX];
7276 if (i.prefix[REX_PREFIX] != 0)
7277 *p++ = i.prefix[REX_PREFIX];
7278 *p = i.tm.base_opcode;
7279
7280 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7281 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7282 else if (cpu_arch_flags.bitfield.cpui386)
7283 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7284 else
7285 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7286 subtype |= code16;
7287
7288 sym = i.op[0].disps->X_add_symbol;
7289 off = i.op[0].disps->X_add_number;
7290
7291 if (i.op[0].disps->X_op != O_constant
7292 && i.op[0].disps->X_op != O_symbol)
7293 {
7294 /* Handle complex expressions. */
7295 sym = make_expr_symbol (i.op[0].disps);
7296 off = 0;
7297 }
7298
7299 /* 1 possible extra opcode + 4 byte displacement go in var part.
7300 Pass reloc in fr_var. */
7301 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7302 }
7303
7304 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7305 /* Return TRUE iff PLT32 relocation should be used for branching to
7306 symbol S. */
7307
7308 static bfd_boolean
7309 need_plt32_p (symbolS *s)
7310 {
7311 /* PLT32 relocation is ELF only. */
7312 if (!IS_ELF)
7313 return FALSE;
7314
7315 /* Since there is no need to prepare for PLT branch on x86-64, we
7316 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7317 be used as a marker for 32-bit PC-relative branches. */
7318 if (!object_64bit)
7319 return FALSE;
7320
7321 /* Weak or undefined symbol need PLT32 relocation. */
7322 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7323 return TRUE;
7324
7325 /* Non-global symbol doesn't need PLT32 relocation. */
7326 if (! S_IS_EXTERNAL (s))
7327 return FALSE;
7328
7329 /* Other global symbols need PLT32 relocation. NB: Symbol with
7330 non-default visibilities are treated as normal global symbol
7331 so that PLT32 relocation can be used as a marker for 32-bit
7332 PC-relative branches. It is useful for linker relaxation. */
7333 return TRUE;
7334 }
7335 #endif
7336
7337 static void
7338 output_jump (void)
7339 {
7340 char *p;
7341 int size;
7342 fixS *fixP;
7343 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7344
7345 if (i.tm.opcode_modifier.jumpbyte)
7346 {
7347 /* This is a loop or jecxz type instruction. */
7348 size = 1;
7349 if (i.prefix[ADDR_PREFIX] != 0)
7350 {
7351 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7352 i.prefixes -= 1;
7353 }
7354 /* Pentium4 branch hints. */
7355 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7356 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7357 {
7358 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7359 i.prefixes--;
7360 }
7361 }
7362 else
7363 {
7364 int code16;
7365
7366 code16 = 0;
7367 if (flag_code == CODE_16BIT)
7368 code16 = CODE16;
7369
7370 if (i.prefix[DATA_PREFIX] != 0)
7371 {
7372 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7373 i.prefixes -= 1;
7374 code16 ^= CODE16;
7375 }
7376
7377 size = 4;
7378 if (code16)
7379 size = 2;
7380 }
7381
7382 if (i.prefix[REX_PREFIX] != 0)
7383 {
7384 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7385 i.prefixes -= 1;
7386 }
7387
7388 /* BND prefixed jump. */
7389 if (i.prefix[BND_PREFIX] != 0)
7390 {
7391 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7392 i.prefixes -= 1;
7393 }
7394
7395 if (i.prefixes != 0 && !intel_syntax)
7396 as_warn (_("skipping prefixes on this instruction"));
7397
7398 p = frag_more (i.tm.opcode_length + size);
7399 switch (i.tm.opcode_length)
7400 {
7401 case 2:
7402 *p++ = i.tm.base_opcode >> 8;
7403 /* Fall through. */
7404 case 1:
7405 *p++ = i.tm.base_opcode;
7406 break;
7407 default:
7408 abort ();
7409 }
7410
7411 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7412 if (size == 4
7413 && jump_reloc == NO_RELOC
7414 && need_plt32_p (i.op[0].disps->X_add_symbol))
7415 jump_reloc = BFD_RELOC_X86_64_PLT32;
7416 #endif
7417
7418 jump_reloc = reloc (size, 1, 1, jump_reloc);
7419
7420 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7421 i.op[0].disps, 1, jump_reloc);
7422
7423 /* All jumps handled here are signed, but don't use a signed limit
7424 check for 32 and 16 bit jumps as we want to allow wrap around at
7425 4G and 64k respectively. */
7426 if (size == 1)
7427 fixP->fx_signed = 1;
7428 }
7429
7430 static void
7431 output_interseg_jump (void)
7432 {
7433 char *p;
7434 int size;
7435 int prefix;
7436 int code16;
7437
7438 code16 = 0;
7439 if (flag_code == CODE_16BIT)
7440 code16 = CODE16;
7441
7442 prefix = 0;
7443 if (i.prefix[DATA_PREFIX] != 0)
7444 {
7445 prefix = 1;
7446 i.prefixes -= 1;
7447 code16 ^= CODE16;
7448 }
7449 if (i.prefix[REX_PREFIX] != 0)
7450 {
7451 prefix++;
7452 i.prefixes -= 1;
7453 }
7454
7455 size = 4;
7456 if (code16)
7457 size = 2;
7458
7459 if (i.prefixes != 0 && !intel_syntax)
7460 as_warn (_("skipping prefixes on this instruction"));
7461
7462 /* 1 opcode; 2 segment; offset */
7463 p = frag_more (prefix + 1 + 2 + size);
7464
7465 if (i.prefix[DATA_PREFIX] != 0)
7466 *p++ = DATA_PREFIX_OPCODE;
7467
7468 if (i.prefix[REX_PREFIX] != 0)
7469 *p++ = i.prefix[REX_PREFIX];
7470
7471 *p++ = i.tm.base_opcode;
7472 if (i.op[1].imms->X_op == O_constant)
7473 {
7474 offsetT n = i.op[1].imms->X_add_number;
7475
7476 if (size == 2
7477 && !fits_in_unsigned_word (n)
7478 && !fits_in_signed_word (n))
7479 {
7480 as_bad (_("16-bit jump out of range"));
7481 return;
7482 }
7483 md_number_to_chars (p, n, size);
7484 }
7485 else
7486 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7487 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7488 if (i.op[0].imms->X_op != O_constant)
7489 as_bad (_("can't handle non absolute segment in `%s'"),
7490 i.tm.name);
7491 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7492 }
7493
7494 static void
7495 output_insn (void)
7496 {
7497 fragS *insn_start_frag;
7498 offsetT insn_start_off;
7499
7500 /* Tie dwarf2 debug info to the address at the start of the insn.
7501 We can't do this after the insn has been output as the current
7502 frag may have been closed off. eg. by frag_var. */
7503 dwarf2_emit_insn (0);
7504
7505 insn_start_frag = frag_now;
7506 insn_start_off = frag_now_fix ();
7507
7508 /* Output jumps. */
7509 if (i.tm.opcode_modifier.jump)
7510 output_branch ();
7511 else if (i.tm.opcode_modifier.jumpbyte
7512 || i.tm.opcode_modifier.jumpdword)
7513 output_jump ();
7514 else if (i.tm.opcode_modifier.jumpintersegment)
7515 output_interseg_jump ();
7516 else
7517 {
7518 /* Output normal instructions here. */
7519 char *p;
7520 unsigned char *q;
7521 unsigned int j;
7522 unsigned int prefix;
7523
7524 if (avoid_fence
7525 && i.tm.base_opcode == 0xfae
7526 && i.operands == 1
7527 && i.imm_operands == 1
7528 && (i.op[0].imms->X_add_number == 0xe8
7529 || i.op[0].imms->X_add_number == 0xf0
7530 || i.op[0].imms->X_add_number == 0xf8))
7531 {
7532 /* Encode lfence, mfence, and sfence as
7533 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7534 offsetT val = 0x240483f0ULL;
7535 p = frag_more (5);
7536 md_number_to_chars (p, val, 5);
7537 return;
7538 }
7539
7540 /* Some processors fail on LOCK prefix. This options makes
7541 assembler ignore LOCK prefix and serves as a workaround. */
7542 if (omit_lock_prefix)
7543 {
7544 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7545 return;
7546 i.prefix[LOCK_PREFIX] = 0;
7547 }
7548
7549 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7550 don't need the explicit prefix. */
7551 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7552 {
7553 switch (i.tm.opcode_length)
7554 {
7555 case 3:
7556 if (i.tm.base_opcode & 0xff000000)
7557 {
7558 prefix = (i.tm.base_opcode >> 24) & 0xff;
7559 goto check_prefix;
7560 }
7561 break;
7562 case 2:
7563 if ((i.tm.base_opcode & 0xff0000) != 0)
7564 {
7565 prefix = (i.tm.base_opcode >> 16) & 0xff;
7566 if (i.tm.cpu_flags.bitfield.cpupadlock)
7567 {
7568 check_prefix:
7569 if (prefix != REPE_PREFIX_OPCODE
7570 || (i.prefix[REP_PREFIX]
7571 != REPE_PREFIX_OPCODE))
7572 add_prefix (prefix);
7573 }
7574 else
7575 add_prefix (prefix);
7576 }
7577 break;
7578 case 1:
7579 break;
7580 case 0:
7581 /* Check for pseudo prefixes. */
7582 as_bad_where (insn_start_frag->fr_file,
7583 insn_start_frag->fr_line,
7584 _("pseudo prefix without instruction"));
7585 return;
7586 default:
7587 abort ();
7588 }
7589
7590 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7591 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7592 R_X86_64_GOTTPOFF relocation so that linker can safely
7593 perform IE->LE optimization. */
7594 if (x86_elf_abi == X86_64_X32_ABI
7595 && i.operands == 2
7596 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7597 && i.prefix[REX_PREFIX] == 0)
7598 add_prefix (REX_OPCODE);
7599 #endif
7600
7601 /* The prefix bytes. */
7602 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7603 if (*q)
7604 FRAG_APPEND_1_CHAR (*q);
7605 }
7606 else
7607 {
7608 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7609 if (*q)
7610 switch (j)
7611 {
7612 case REX_PREFIX:
7613 /* REX byte is encoded in VEX prefix. */
7614 break;
7615 case SEG_PREFIX:
7616 case ADDR_PREFIX:
7617 FRAG_APPEND_1_CHAR (*q);
7618 break;
7619 default:
7620 /* There should be no other prefixes for instructions
7621 with VEX prefix. */
7622 abort ();
7623 }
7624
7625 /* For EVEX instructions i.vrex should become 0 after
7626 build_evex_prefix. For VEX instructions upper 16 registers
7627 aren't available, so VREX should be 0. */
7628 if (i.vrex)
7629 abort ();
7630 /* Now the VEX prefix. */
7631 p = frag_more (i.vex.length);
7632 for (j = 0; j < i.vex.length; j++)
7633 p[j] = i.vex.bytes[j];
7634 }
7635
7636 /* Now the opcode; be careful about word order here! */
7637 if (i.tm.opcode_length == 1)
7638 {
7639 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7640 }
7641 else
7642 {
7643 switch (i.tm.opcode_length)
7644 {
7645 case 4:
7646 p = frag_more (4);
7647 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7648 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7649 break;
7650 case 3:
7651 p = frag_more (3);
7652 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7653 break;
7654 case 2:
7655 p = frag_more (2);
7656 break;
7657 default:
7658 abort ();
7659 break;
7660 }
7661
7662 /* Put out high byte first: can't use md_number_to_chars! */
7663 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7664 *p = i.tm.base_opcode & 0xff;
7665 }
7666
7667 /* Now the modrm byte and sib byte (if present). */
7668 if (i.tm.opcode_modifier.modrm)
7669 {
7670 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7671 | i.rm.reg << 3
7672 | i.rm.mode << 6));
7673 /* If i.rm.regmem == ESP (4)
7674 && i.rm.mode != (Register mode)
7675 && not 16 bit
7676 ==> need second modrm byte. */
7677 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7678 && i.rm.mode != 3
7679 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7680 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7681 | i.sib.index << 3
7682 | i.sib.scale << 6));
7683 }
7684
7685 if (i.disp_operands)
7686 output_disp (insn_start_frag, insn_start_off);
7687
7688 if (i.imm_operands)
7689 output_imm (insn_start_frag, insn_start_off);
7690 }
7691
7692 #ifdef DEBUG386
7693 if (flag_debug)
7694 {
7695 pi ("" /*line*/, &i);
7696 }
7697 #endif /* DEBUG386 */
7698 }
7699
7700 /* Return the size of the displacement operand N. */
7701
7702 static int
7703 disp_size (unsigned int n)
7704 {
7705 int size = 4;
7706
7707 if (i.types[n].bitfield.disp64)
7708 size = 8;
7709 else if (i.types[n].bitfield.disp8)
7710 size = 1;
7711 else if (i.types[n].bitfield.disp16)
7712 size = 2;
7713 return size;
7714 }
7715
7716 /* Return the size of the immediate operand N. */
7717
7718 static int
7719 imm_size (unsigned int n)
7720 {
7721 int size = 4;
7722 if (i.types[n].bitfield.imm64)
7723 size = 8;
7724 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7725 size = 1;
7726 else if (i.types[n].bitfield.imm16)
7727 size = 2;
7728 return size;
7729 }
7730
7731 static void
7732 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7733 {
7734 char *p;
7735 unsigned int n;
7736
7737 for (n = 0; n < i.operands; n++)
7738 {
7739 if (operand_type_check (i.types[n], disp))
7740 {
7741 if (i.op[n].disps->X_op == O_constant)
7742 {
7743 int size = disp_size (n);
7744 offsetT val = i.op[n].disps->X_add_number;
7745
7746 val = offset_in_range (val >> i.memshift, size);
7747 p = frag_more (size);
7748 md_number_to_chars (p, val, size);
7749 }
7750 else
7751 {
7752 enum bfd_reloc_code_real reloc_type;
7753 int size = disp_size (n);
7754 int sign = i.types[n].bitfield.disp32s;
7755 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7756 fixS *fixP;
7757
7758 /* We can't have 8 bit displacement here. */
7759 gas_assert (!i.types[n].bitfield.disp8);
7760
7761 /* The PC relative address is computed relative
7762 to the instruction boundary, so in case immediate
7763 fields follows, we need to adjust the value. */
7764 if (pcrel && i.imm_operands)
7765 {
7766 unsigned int n1;
7767 int sz = 0;
7768
7769 for (n1 = 0; n1 < i.operands; n1++)
7770 if (operand_type_check (i.types[n1], imm))
7771 {
7772 /* Only one immediate is allowed for PC
7773 relative address. */
7774 gas_assert (sz == 0);
7775 sz = imm_size (n1);
7776 i.op[n].disps->X_add_number -= sz;
7777 }
7778 /* We should find the immediate. */
7779 gas_assert (sz != 0);
7780 }
7781
7782 p = frag_more (size);
7783 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7784 if (GOT_symbol
7785 && GOT_symbol == i.op[n].disps->X_add_symbol
7786 && (((reloc_type == BFD_RELOC_32
7787 || reloc_type == BFD_RELOC_X86_64_32S
7788 || (reloc_type == BFD_RELOC_64
7789 && object_64bit))
7790 && (i.op[n].disps->X_op == O_symbol
7791 || (i.op[n].disps->X_op == O_add
7792 && ((symbol_get_value_expression
7793 (i.op[n].disps->X_op_symbol)->X_op)
7794 == O_subtract))))
7795 || reloc_type == BFD_RELOC_32_PCREL))
7796 {
7797 offsetT add;
7798
7799 if (insn_start_frag == frag_now)
7800 add = (p - frag_now->fr_literal) - insn_start_off;
7801 else
7802 {
7803 fragS *fr;
7804
7805 add = insn_start_frag->fr_fix - insn_start_off;
7806 for (fr = insn_start_frag->fr_next;
7807 fr && fr != frag_now; fr = fr->fr_next)
7808 add += fr->fr_fix;
7809 add += p - frag_now->fr_literal;
7810 }
7811
7812 if (!object_64bit)
7813 {
7814 reloc_type = BFD_RELOC_386_GOTPC;
7815 i.op[n].imms->X_add_number += add;
7816 }
7817 else if (reloc_type == BFD_RELOC_64)
7818 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7819 else
7820 /* Don't do the adjustment for x86-64, as there
7821 the pcrel addressing is relative to the _next_
7822 insn, and that is taken care of in other code. */
7823 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7824 }
7825 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7826 size, i.op[n].disps, pcrel,
7827 reloc_type);
7828 /* Check for "call/jmp *mem", "mov mem, %reg",
7829 "test %reg, mem" and "binop mem, %reg" where binop
7830 is one of adc, add, and, cmp, or, sbb, sub, xor
7831 instructions. Always generate R_386_GOT32X for
7832 "sym*GOT" operand in 32-bit mode. */
7833 if ((generate_relax_relocations
7834 || (!object_64bit
7835 && i.rm.mode == 0
7836 && i.rm.regmem == 5))
7837 && (i.rm.mode == 2
7838 || (i.rm.mode == 0 && i.rm.regmem == 5))
7839 && ((i.operands == 1
7840 && i.tm.base_opcode == 0xff
7841 && (i.rm.reg == 2 || i.rm.reg == 4))
7842 || (i.operands == 2
7843 && (i.tm.base_opcode == 0x8b
7844 || i.tm.base_opcode == 0x85
7845 || (i.tm.base_opcode & 0xc7) == 0x03))))
7846 {
7847 if (object_64bit)
7848 {
7849 fixP->fx_tcbit = i.rex != 0;
7850 if (i.base_reg
7851 && (i.base_reg->reg_num == RegRip
7852 || i.base_reg->reg_num == RegEip))
7853 fixP->fx_tcbit2 = 1;
7854 }
7855 else
7856 fixP->fx_tcbit2 = 1;
7857 }
7858 }
7859 }
7860 }
7861 }
7862
7863 static void
7864 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7865 {
7866 char *p;
7867 unsigned int n;
7868
7869 for (n = 0; n < i.operands; n++)
7870 {
7871 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7872 if (i.rounding && (int) n == i.rounding->operand)
7873 continue;
7874
7875 if (operand_type_check (i.types[n], imm))
7876 {
7877 if (i.op[n].imms->X_op == O_constant)
7878 {
7879 int size = imm_size (n);
7880 offsetT val;
7881
7882 val = offset_in_range (i.op[n].imms->X_add_number,
7883 size);
7884 p = frag_more (size);
7885 md_number_to_chars (p, val, size);
7886 }
7887 else
7888 {
7889 /* Not absolute_section.
7890 Need a 32-bit fixup (don't support 8bit
7891 non-absolute imms). Try to support other
7892 sizes ... */
7893 enum bfd_reloc_code_real reloc_type;
7894 int size = imm_size (n);
7895 int sign;
7896
7897 if (i.types[n].bitfield.imm32s
7898 && (i.suffix == QWORD_MNEM_SUFFIX
7899 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7900 sign = 1;
7901 else
7902 sign = 0;
7903
7904 p = frag_more (size);
7905 reloc_type = reloc (size, 0, sign, i.reloc[n]);
7906
7907 /* This is tough to explain. We end up with this one if we
7908 * have operands that look like
7909 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7910 * obtain the absolute address of the GOT, and it is strongly
7911 * preferable from a performance point of view to avoid using
7912 * a runtime relocation for this. The actual sequence of
7913 * instructions often look something like:
7914 *
7915 * call .L66
7916 * .L66:
7917 * popl %ebx
7918 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7919 *
7920 * The call and pop essentially return the absolute address
7921 * of the label .L66 and store it in %ebx. The linker itself
7922 * will ultimately change the first operand of the addl so
7923 * that %ebx points to the GOT, but to keep things simple, the
7924 * .o file must have this operand set so that it generates not
7925 * the absolute address of .L66, but the absolute address of
7926 * itself. This allows the linker itself simply treat a GOTPC
7927 * relocation as asking for a pcrel offset to the GOT to be
7928 * added in, and the addend of the relocation is stored in the
7929 * operand field for the instruction itself.
7930 *
7931 * Our job here is to fix the operand so that it would add
7932 * the correct offset so that %ebx would point to itself. The
7933 * thing that is tricky is that .-.L66 will point to the
7934 * beginning of the instruction, so we need to further modify
7935 * the operand so that it will point to itself. There are
7936 * other cases where you have something like:
7937 *
7938 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7939 *
7940 * and here no correction would be required. Internally in
7941 * the assembler we treat operands of this form as not being
7942 * pcrel since the '.' is explicitly mentioned, and I wonder
7943 * whether it would simplify matters to do it this way. Who
7944 * knows. In earlier versions of the PIC patches, the
7945 * pcrel_adjust field was used to store the correction, but
7946 * since the expression is not pcrel, I felt it would be
7947 * confusing to do it this way. */
7948
7949 if ((reloc_type == BFD_RELOC_32
7950 || reloc_type == BFD_RELOC_X86_64_32S
7951 || reloc_type == BFD_RELOC_64)
7952 && GOT_symbol
7953 && GOT_symbol == i.op[n].imms->X_add_symbol
7954 && (i.op[n].imms->X_op == O_symbol
7955 || (i.op[n].imms->X_op == O_add
7956 && ((symbol_get_value_expression
7957 (i.op[n].imms->X_op_symbol)->X_op)
7958 == O_subtract))))
7959 {
7960 offsetT add;
7961
7962 if (insn_start_frag == frag_now)
7963 add = (p - frag_now->fr_literal) - insn_start_off;
7964 else
7965 {
7966 fragS *fr;
7967
7968 add = insn_start_frag->fr_fix - insn_start_off;
7969 for (fr = insn_start_frag->fr_next;
7970 fr && fr != frag_now; fr = fr->fr_next)
7971 add += fr->fr_fix;
7972 add += p - frag_now->fr_literal;
7973 }
7974
7975 if (!object_64bit)
7976 reloc_type = BFD_RELOC_386_GOTPC;
7977 else if (size == 4)
7978 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7979 else if (size == 8)
7980 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7981 i.op[n].imms->X_add_number += add;
7982 }
7983 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7984 i.op[n].imms, 0, reloc_type);
7985 }
7986 }
7987 }
7988 }
7989 \f
7990 /* x86_cons_fix_new is called via the expression parsing code when a
7991 reloc is needed. We use this hook to get the correct .got reloc. */
7992 static int cons_sign = -1;
7993
7994 void
7995 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
7996 expressionS *exp, bfd_reloc_code_real_type r)
7997 {
7998 r = reloc (len, 0, cons_sign, r);
7999
8000 #ifdef TE_PE
8001 if (exp->X_op == O_secrel)
8002 {
8003 exp->X_op = O_symbol;
8004 r = BFD_RELOC_32_SECREL;
8005 }
8006 #endif
8007
8008 fix_new_exp (frag, off, len, exp, 0, r);
8009 }
8010
8011 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8012 purpose of the `.dc.a' internal pseudo-op. */
8013
8014 int
8015 x86_address_bytes (void)
8016 {
8017 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8018 return 4;
8019 return stdoutput->arch_info->bits_per_address / 8;
8020 }
8021
8022 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8023 || defined (LEX_AT)
8024 # define lex_got(reloc, adjust, types) NULL
8025 #else
8026 /* Parse operands of the form
8027 <symbol>@GOTOFF+<nnn>
8028 and similar .plt or .got references.
8029
8030 If we find one, set up the correct relocation in RELOC and copy the
8031 input string, minus the `@GOTOFF' into a malloc'd buffer for
8032 parsing by the calling routine. Return this buffer, and if ADJUST
8033 is non-null set it to the length of the string we removed from the
8034 input line. Otherwise return NULL. */
8035 static char *
8036 lex_got (enum bfd_reloc_code_real *rel,
8037 int *adjust,
8038 i386_operand_type *types)
8039 {
8040 /* Some of the relocations depend on the size of what field is to
8041 be relocated. But in our callers i386_immediate and i386_displacement
8042 we don't yet know the operand size (this will be set by insn
8043 matching). Hence we record the word32 relocation here,
8044 and adjust the reloc according to the real size in reloc(). */
8045 static const struct {
8046 const char *str;
8047 int len;
8048 const enum bfd_reloc_code_real rel[2];
8049 const i386_operand_type types64;
8050 } gotrel[] = {
8051 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8052 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8053 BFD_RELOC_SIZE32 },
8054 OPERAND_TYPE_IMM32_64 },
8055 #endif
8056 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8057 BFD_RELOC_X86_64_PLTOFF64 },
8058 OPERAND_TYPE_IMM64 },
8059 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8060 BFD_RELOC_X86_64_PLT32 },
8061 OPERAND_TYPE_IMM32_32S_DISP32 },
8062 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8063 BFD_RELOC_X86_64_GOTPLT64 },
8064 OPERAND_TYPE_IMM64_DISP64 },
8065 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8066 BFD_RELOC_X86_64_GOTOFF64 },
8067 OPERAND_TYPE_IMM64_DISP64 },
8068 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8069 BFD_RELOC_X86_64_GOTPCREL },
8070 OPERAND_TYPE_IMM32_32S_DISP32 },
8071 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8072 BFD_RELOC_X86_64_TLSGD },
8073 OPERAND_TYPE_IMM32_32S_DISP32 },
8074 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8075 _dummy_first_bfd_reloc_code_real },
8076 OPERAND_TYPE_NONE },
8077 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8078 BFD_RELOC_X86_64_TLSLD },
8079 OPERAND_TYPE_IMM32_32S_DISP32 },
8080 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8081 BFD_RELOC_X86_64_GOTTPOFF },
8082 OPERAND_TYPE_IMM32_32S_DISP32 },
8083 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8084 BFD_RELOC_X86_64_TPOFF32 },
8085 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8086 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8087 _dummy_first_bfd_reloc_code_real },
8088 OPERAND_TYPE_NONE },
8089 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8090 BFD_RELOC_X86_64_DTPOFF32 },
8091 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8092 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8093 _dummy_first_bfd_reloc_code_real },
8094 OPERAND_TYPE_NONE },
8095 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8096 _dummy_first_bfd_reloc_code_real },
8097 OPERAND_TYPE_NONE },
8098 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8099 BFD_RELOC_X86_64_GOT32 },
8100 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8101 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8102 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8103 OPERAND_TYPE_IMM32_32S_DISP32 },
8104 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8105 BFD_RELOC_X86_64_TLSDESC_CALL },
8106 OPERAND_TYPE_IMM32_32S_DISP32 },
8107 };
8108 char *cp;
8109 unsigned int j;
8110
8111 #if defined (OBJ_MAYBE_ELF)
8112 if (!IS_ELF)
8113 return NULL;
8114 #endif
8115
8116 for (cp = input_line_pointer; *cp != '@'; cp++)
8117 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8118 return NULL;
8119
8120 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8121 {
8122 int len = gotrel[j].len;
8123 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8124 {
8125 if (gotrel[j].rel[object_64bit] != 0)
8126 {
8127 int first, second;
8128 char *tmpbuf, *past_reloc;
8129
8130 *rel = gotrel[j].rel[object_64bit];
8131
8132 if (types)
8133 {
8134 if (flag_code != CODE_64BIT)
8135 {
8136 types->bitfield.imm32 = 1;
8137 types->bitfield.disp32 = 1;
8138 }
8139 else
8140 *types = gotrel[j].types64;
8141 }
8142
8143 if (j != 0 && GOT_symbol == NULL)
8144 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8145
8146 /* The length of the first part of our input line. */
8147 first = cp - input_line_pointer;
8148
8149 /* The second part goes from after the reloc token until
8150 (and including) an end_of_line char or comma. */
8151 past_reloc = cp + 1 + len;
8152 cp = past_reloc;
8153 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8154 ++cp;
8155 second = cp + 1 - past_reloc;
8156
8157 /* Allocate and copy string. The trailing NUL shouldn't
8158 be necessary, but be safe. */
8159 tmpbuf = XNEWVEC (char, first + second + 2);
8160 memcpy (tmpbuf, input_line_pointer, first);
8161 if (second != 0 && *past_reloc != ' ')
8162 /* Replace the relocation token with ' ', so that
8163 errors like foo@GOTOFF1 will be detected. */
8164 tmpbuf[first++] = ' ';
8165 else
8166 /* Increment length by 1 if the relocation token is
8167 removed. */
8168 len++;
8169 if (adjust)
8170 *adjust = len;
8171 memcpy (tmpbuf + first, past_reloc, second);
8172 tmpbuf[first + second] = '\0';
8173 return tmpbuf;
8174 }
8175
8176 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8177 gotrel[j].str, 1 << (5 + object_64bit));
8178 return NULL;
8179 }
8180 }
8181
8182 /* Might be a symbol version string. Don't as_bad here. */
8183 return NULL;
8184 }
8185 #endif
8186
8187 #ifdef TE_PE
8188 #ifdef lex_got
8189 #undef lex_got
8190 #endif
8191 /* Parse operands of the form
8192 <symbol>@SECREL32+<nnn>
8193
8194 If we find one, set up the correct relocation in RELOC and copy the
8195 input string, minus the `@SECREL32' into a malloc'd buffer for
8196 parsing by the calling routine. Return this buffer, and if ADJUST
8197 is non-null set it to the length of the string we removed from the
8198 input line. Otherwise return NULL.
8199
8200 This function is copied from the ELF version above adjusted for PE targets. */
8201
8202 static char *
8203 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8204 int *adjust ATTRIBUTE_UNUSED,
8205 i386_operand_type *types)
8206 {
8207 static const struct
8208 {
8209 const char *str;
8210 int len;
8211 const enum bfd_reloc_code_real rel[2];
8212 const i386_operand_type types64;
8213 }
8214 gotrel[] =
8215 {
8216 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8217 BFD_RELOC_32_SECREL },
8218 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8219 };
8220
8221 char *cp;
8222 unsigned j;
8223
8224 for (cp = input_line_pointer; *cp != '@'; cp++)
8225 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8226 return NULL;
8227
8228 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8229 {
8230 int len = gotrel[j].len;
8231
8232 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8233 {
8234 if (gotrel[j].rel[object_64bit] != 0)
8235 {
8236 int first, second;
8237 char *tmpbuf, *past_reloc;
8238
8239 *rel = gotrel[j].rel[object_64bit];
8240 if (adjust)
8241 *adjust = len;
8242
8243 if (types)
8244 {
8245 if (flag_code != CODE_64BIT)
8246 {
8247 types->bitfield.imm32 = 1;
8248 types->bitfield.disp32 = 1;
8249 }
8250 else
8251 *types = gotrel[j].types64;
8252 }
8253
8254 /* The length of the first part of our input line. */
8255 first = cp - input_line_pointer;
8256
8257 /* The second part goes from after the reloc token until
8258 (and including) an end_of_line char or comma. */
8259 past_reloc = cp + 1 + len;
8260 cp = past_reloc;
8261 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8262 ++cp;
8263 second = cp + 1 - past_reloc;
8264
8265 /* Allocate and copy string. The trailing NUL shouldn't
8266 be necessary, but be safe. */
8267 tmpbuf = XNEWVEC (char, first + second + 2);
8268 memcpy (tmpbuf, input_line_pointer, first);
8269 if (second != 0 && *past_reloc != ' ')
8270 /* Replace the relocation token with ' ', so that
8271 errors like foo@SECLREL321 will be detected. */
8272 tmpbuf[first++] = ' ';
8273 memcpy (tmpbuf + first, past_reloc, second);
8274 tmpbuf[first + second] = '\0';
8275 return tmpbuf;
8276 }
8277
8278 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8279 gotrel[j].str, 1 << (5 + object_64bit));
8280 return NULL;
8281 }
8282 }
8283
8284 /* Might be a symbol version string. Don't as_bad here. */
8285 return NULL;
8286 }
8287
8288 #endif /* TE_PE */
8289
8290 bfd_reloc_code_real_type
8291 x86_cons (expressionS *exp, int size)
8292 {
8293 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8294
8295 intel_syntax = -intel_syntax;
8296
8297 exp->X_md = 0;
8298 if (size == 4 || (object_64bit && size == 8))
8299 {
8300 /* Handle @GOTOFF and the like in an expression. */
8301 char *save;
8302 char *gotfree_input_line;
8303 int adjust = 0;
8304
8305 save = input_line_pointer;
8306 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8307 if (gotfree_input_line)
8308 input_line_pointer = gotfree_input_line;
8309
8310 expression (exp);
8311
8312 if (gotfree_input_line)
8313 {
8314 /* expression () has merrily parsed up to the end of line,
8315 or a comma - in the wrong buffer. Transfer how far
8316 input_line_pointer has moved to the right buffer. */
8317 input_line_pointer = (save
8318 + (input_line_pointer - gotfree_input_line)
8319 + adjust);
8320 free (gotfree_input_line);
8321 if (exp->X_op == O_constant
8322 || exp->X_op == O_absent
8323 || exp->X_op == O_illegal
8324 || exp->X_op == O_register
8325 || exp->X_op == O_big)
8326 {
8327 char c = *input_line_pointer;
8328 *input_line_pointer = 0;
8329 as_bad (_("missing or invalid expression `%s'"), save);
8330 *input_line_pointer = c;
8331 }
8332 }
8333 }
8334 else
8335 expression (exp);
8336
8337 intel_syntax = -intel_syntax;
8338
8339 if (intel_syntax)
8340 i386_intel_simplify (exp);
8341
8342 return got_reloc;
8343 }
8344
8345 static void
8346 signed_cons (int size)
8347 {
8348 if (flag_code == CODE_64BIT)
8349 cons_sign = 1;
8350 cons (size);
8351 cons_sign = -1;
8352 }
8353
8354 #ifdef TE_PE
8355 static void
8356 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8357 {
8358 expressionS exp;
8359
8360 do
8361 {
8362 expression (&exp);
8363 if (exp.X_op == O_symbol)
8364 exp.X_op = O_secrel;
8365
8366 emit_expr (&exp, 4);
8367 }
8368 while (*input_line_pointer++ == ',');
8369
8370 input_line_pointer--;
8371 demand_empty_rest_of_line ();
8372 }
8373 #endif
8374
8375 /* Handle Vector operations. */
8376
8377 static char *
8378 check_VecOperations (char *op_string, char *op_end)
8379 {
8380 const reg_entry *mask;
8381 const char *saved;
8382 char *end_op;
8383
8384 while (*op_string
8385 && (op_end == NULL || op_string < op_end))
8386 {
8387 saved = op_string;
8388 if (*op_string == '{')
8389 {
8390 op_string++;
8391
8392 /* Check broadcasts. */
8393 if (strncmp (op_string, "1to", 3) == 0)
8394 {
8395 int bcst_type;
8396
8397 if (i.broadcast)
8398 goto duplicated_vec_op;
8399
8400 op_string += 3;
8401 if (*op_string == '8')
8402 bcst_type = BROADCAST_1TO8;
8403 else if (*op_string == '4')
8404 bcst_type = BROADCAST_1TO4;
8405 else if (*op_string == '2')
8406 bcst_type = BROADCAST_1TO2;
8407 else if (*op_string == '1'
8408 && *(op_string+1) == '6')
8409 {
8410 bcst_type = BROADCAST_1TO16;
8411 op_string++;
8412 }
8413 else
8414 {
8415 as_bad (_("Unsupported broadcast: `%s'"), saved);
8416 return NULL;
8417 }
8418 op_string++;
8419
8420 broadcast_op.type = bcst_type;
8421 broadcast_op.operand = this_operand;
8422 i.broadcast = &broadcast_op;
8423 }
8424 /* Check masking operation. */
8425 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8426 {
8427 /* k0 can't be used for write mask. */
8428 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8429 {
8430 as_bad (_("`%s%s' can't be used for write mask"),
8431 register_prefix, mask->reg_name);
8432 return NULL;
8433 }
8434
8435 if (!i.mask)
8436 {
8437 mask_op.mask = mask;
8438 mask_op.zeroing = 0;
8439 mask_op.operand = this_operand;
8440 i.mask = &mask_op;
8441 }
8442 else
8443 {
8444 if (i.mask->mask)
8445 goto duplicated_vec_op;
8446
8447 i.mask->mask = mask;
8448
8449 /* Only "{z}" is allowed here. No need to check
8450 zeroing mask explicitly. */
8451 if (i.mask->operand != this_operand)
8452 {
8453 as_bad (_("invalid write mask `%s'"), saved);
8454 return NULL;
8455 }
8456 }
8457
8458 op_string = end_op;
8459 }
8460 /* Check zeroing-flag for masking operation. */
8461 else if (*op_string == 'z')
8462 {
8463 if (!i.mask)
8464 {
8465 mask_op.mask = NULL;
8466 mask_op.zeroing = 1;
8467 mask_op.operand = this_operand;
8468 i.mask = &mask_op;
8469 }
8470 else
8471 {
8472 if (i.mask->zeroing)
8473 {
8474 duplicated_vec_op:
8475 as_bad (_("duplicated `%s'"), saved);
8476 return NULL;
8477 }
8478
8479 i.mask->zeroing = 1;
8480
8481 /* Only "{%k}" is allowed here. No need to check mask
8482 register explicitly. */
8483 if (i.mask->operand != this_operand)
8484 {
8485 as_bad (_("invalid zeroing-masking `%s'"),
8486 saved);
8487 return NULL;
8488 }
8489 }
8490
8491 op_string++;
8492 }
8493 else
8494 goto unknown_vec_op;
8495
8496 if (*op_string != '}')
8497 {
8498 as_bad (_("missing `}' in `%s'"), saved);
8499 return NULL;
8500 }
8501 op_string++;
8502 continue;
8503 }
8504 unknown_vec_op:
8505 /* We don't know this one. */
8506 as_bad (_("unknown vector operation: `%s'"), saved);
8507 return NULL;
8508 }
8509
8510 if (i.mask && i.mask->zeroing && !i.mask->mask)
8511 {
8512 as_bad (_("zeroing-masking only allowed with write mask"));
8513 return NULL;
8514 }
8515
8516 return op_string;
8517 }
8518
8519 static int
8520 i386_immediate (char *imm_start)
8521 {
8522 char *save_input_line_pointer;
8523 char *gotfree_input_line;
8524 segT exp_seg = 0;
8525 expressionS *exp;
8526 i386_operand_type types;
8527
8528 operand_type_set (&types, ~0);
8529
8530 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8531 {
8532 as_bad (_("at most %d immediate operands are allowed"),
8533 MAX_IMMEDIATE_OPERANDS);
8534 return 0;
8535 }
8536
8537 exp = &im_expressions[i.imm_operands++];
8538 i.op[this_operand].imms = exp;
8539
8540 if (is_space_char (*imm_start))
8541 ++imm_start;
8542
8543 save_input_line_pointer = input_line_pointer;
8544 input_line_pointer = imm_start;
8545
8546 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8547 if (gotfree_input_line)
8548 input_line_pointer = gotfree_input_line;
8549
8550 exp_seg = expression (exp);
8551
8552 SKIP_WHITESPACE ();
8553
8554 /* Handle vector operations. */
8555 if (*input_line_pointer == '{')
8556 {
8557 input_line_pointer = check_VecOperations (input_line_pointer,
8558 NULL);
8559 if (input_line_pointer == NULL)
8560 return 0;
8561 }
8562
8563 if (*input_line_pointer)
8564 as_bad (_("junk `%s' after expression"), input_line_pointer);
8565
8566 input_line_pointer = save_input_line_pointer;
8567 if (gotfree_input_line)
8568 {
8569 free (gotfree_input_line);
8570
8571 if (exp->X_op == O_constant || exp->X_op == O_register)
8572 exp->X_op = O_illegal;
8573 }
8574
8575 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8576 }
8577
8578 static int
8579 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8580 i386_operand_type types, const char *imm_start)
8581 {
8582 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8583 {
8584 if (imm_start)
8585 as_bad (_("missing or invalid immediate expression `%s'"),
8586 imm_start);
8587 return 0;
8588 }
8589 else if (exp->X_op == O_constant)
8590 {
8591 /* Size it properly later. */
8592 i.types[this_operand].bitfield.imm64 = 1;
8593 /* If not 64bit, sign extend val. */
8594 if (flag_code != CODE_64BIT
8595 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8596 exp->X_add_number
8597 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8598 }
8599 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8600 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8601 && exp_seg != absolute_section
8602 && exp_seg != text_section
8603 && exp_seg != data_section
8604 && exp_seg != bss_section
8605 && exp_seg != undefined_section
8606 && !bfd_is_com_section (exp_seg))
8607 {
8608 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8609 return 0;
8610 }
8611 #endif
8612 else if (!intel_syntax && exp_seg == reg_section)
8613 {
8614 if (imm_start)
8615 as_bad (_("illegal immediate register operand %s"), imm_start);
8616 return 0;
8617 }
8618 else
8619 {
8620 /* This is an address. The size of the address will be
8621 determined later, depending on destination register,
8622 suffix, or the default for the section. */
8623 i.types[this_operand].bitfield.imm8 = 1;
8624 i.types[this_operand].bitfield.imm16 = 1;
8625 i.types[this_operand].bitfield.imm32 = 1;
8626 i.types[this_operand].bitfield.imm32s = 1;
8627 i.types[this_operand].bitfield.imm64 = 1;
8628 i.types[this_operand] = operand_type_and (i.types[this_operand],
8629 types);
8630 }
8631
8632 return 1;
8633 }
8634
8635 static char *
8636 i386_scale (char *scale)
8637 {
8638 offsetT val;
8639 char *save = input_line_pointer;
8640
8641 input_line_pointer = scale;
8642 val = get_absolute_expression ();
8643
8644 switch (val)
8645 {
8646 case 1:
8647 i.log2_scale_factor = 0;
8648 break;
8649 case 2:
8650 i.log2_scale_factor = 1;
8651 break;
8652 case 4:
8653 i.log2_scale_factor = 2;
8654 break;
8655 case 8:
8656 i.log2_scale_factor = 3;
8657 break;
8658 default:
8659 {
8660 char sep = *input_line_pointer;
8661
8662 *input_line_pointer = '\0';
8663 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8664 scale);
8665 *input_line_pointer = sep;
8666 input_line_pointer = save;
8667 return NULL;
8668 }
8669 }
8670 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8671 {
8672 as_warn (_("scale factor of %d without an index register"),
8673 1 << i.log2_scale_factor);
8674 i.log2_scale_factor = 0;
8675 }
8676 scale = input_line_pointer;
8677 input_line_pointer = save;
8678 return scale;
8679 }
8680
8681 static int
8682 i386_displacement (char *disp_start, char *disp_end)
8683 {
8684 expressionS *exp;
8685 segT exp_seg = 0;
8686 char *save_input_line_pointer;
8687 char *gotfree_input_line;
8688 int override;
8689 i386_operand_type bigdisp, types = anydisp;
8690 int ret;
8691
8692 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8693 {
8694 as_bad (_("at most %d displacement operands are allowed"),
8695 MAX_MEMORY_OPERANDS);
8696 return 0;
8697 }
8698
8699 operand_type_set (&bigdisp, 0);
8700 if ((i.types[this_operand].bitfield.jumpabsolute)
8701 || (!current_templates->start->opcode_modifier.jump
8702 && !current_templates->start->opcode_modifier.jumpdword))
8703 {
8704 bigdisp.bitfield.disp32 = 1;
8705 override = (i.prefix[ADDR_PREFIX] != 0);
8706 if (flag_code == CODE_64BIT)
8707 {
8708 if (!override)
8709 {
8710 bigdisp.bitfield.disp32s = 1;
8711 bigdisp.bitfield.disp64 = 1;
8712 }
8713 }
8714 else if ((flag_code == CODE_16BIT) ^ override)
8715 {
8716 bigdisp.bitfield.disp32 = 0;
8717 bigdisp.bitfield.disp16 = 1;
8718 }
8719 }
8720 else
8721 {
8722 /* For PC-relative branches, the width of the displacement
8723 is dependent upon data size, not address size. */
8724 override = (i.prefix[DATA_PREFIX] != 0);
8725 if (flag_code == CODE_64BIT)
8726 {
8727 if (override || i.suffix == WORD_MNEM_SUFFIX)
8728 bigdisp.bitfield.disp16 = 1;
8729 else
8730 {
8731 bigdisp.bitfield.disp32 = 1;
8732 bigdisp.bitfield.disp32s = 1;
8733 }
8734 }
8735 else
8736 {
8737 if (!override)
8738 override = (i.suffix == (flag_code != CODE_16BIT
8739 ? WORD_MNEM_SUFFIX
8740 : LONG_MNEM_SUFFIX));
8741 bigdisp.bitfield.disp32 = 1;
8742 if ((flag_code == CODE_16BIT) ^ override)
8743 {
8744 bigdisp.bitfield.disp32 = 0;
8745 bigdisp.bitfield.disp16 = 1;
8746 }
8747 }
8748 }
8749 i.types[this_operand] = operand_type_or (i.types[this_operand],
8750 bigdisp);
8751
8752 exp = &disp_expressions[i.disp_operands];
8753 i.op[this_operand].disps = exp;
8754 i.disp_operands++;
8755 save_input_line_pointer = input_line_pointer;
8756 input_line_pointer = disp_start;
8757 END_STRING_AND_SAVE (disp_end);
8758
8759 #ifndef GCC_ASM_O_HACK
8760 #define GCC_ASM_O_HACK 0
8761 #endif
8762 #if GCC_ASM_O_HACK
8763 END_STRING_AND_SAVE (disp_end + 1);
8764 if (i.types[this_operand].bitfield.baseIndex
8765 && displacement_string_end[-1] == '+')
8766 {
8767 /* This hack is to avoid a warning when using the "o"
8768 constraint within gcc asm statements.
8769 For instance:
8770
8771 #define _set_tssldt_desc(n,addr,limit,type) \
8772 __asm__ __volatile__ ( \
8773 "movw %w2,%0\n\t" \
8774 "movw %w1,2+%0\n\t" \
8775 "rorl $16,%1\n\t" \
8776 "movb %b1,4+%0\n\t" \
8777 "movb %4,5+%0\n\t" \
8778 "movb $0,6+%0\n\t" \
8779 "movb %h1,7+%0\n\t" \
8780 "rorl $16,%1" \
8781 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8782
8783 This works great except that the output assembler ends
8784 up looking a bit weird if it turns out that there is
8785 no offset. You end up producing code that looks like:
8786
8787 #APP
8788 movw $235,(%eax)
8789 movw %dx,2+(%eax)
8790 rorl $16,%edx
8791 movb %dl,4+(%eax)
8792 movb $137,5+(%eax)
8793 movb $0,6+(%eax)
8794 movb %dh,7+(%eax)
8795 rorl $16,%edx
8796 #NO_APP
8797
8798 So here we provide the missing zero. */
8799
8800 *displacement_string_end = '0';
8801 }
8802 #endif
8803 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8804 if (gotfree_input_line)
8805 input_line_pointer = gotfree_input_line;
8806
8807 exp_seg = expression (exp);
8808
8809 SKIP_WHITESPACE ();
8810 if (*input_line_pointer)
8811 as_bad (_("junk `%s' after expression"), input_line_pointer);
8812 #if GCC_ASM_O_HACK
8813 RESTORE_END_STRING (disp_end + 1);
8814 #endif
8815 input_line_pointer = save_input_line_pointer;
8816 if (gotfree_input_line)
8817 {
8818 free (gotfree_input_line);
8819
8820 if (exp->X_op == O_constant || exp->X_op == O_register)
8821 exp->X_op = O_illegal;
8822 }
8823
8824 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8825
8826 RESTORE_END_STRING (disp_end);
8827
8828 return ret;
8829 }
8830
8831 static int
8832 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8833 i386_operand_type types, const char *disp_start)
8834 {
8835 i386_operand_type bigdisp;
8836 int ret = 1;
8837
8838 /* We do this to make sure that the section symbol is in
8839 the symbol table. We will ultimately change the relocation
8840 to be relative to the beginning of the section. */
8841 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8842 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8843 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8844 {
8845 if (exp->X_op != O_symbol)
8846 goto inv_disp;
8847
8848 if (S_IS_LOCAL (exp->X_add_symbol)
8849 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8850 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8851 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8852 exp->X_op = O_subtract;
8853 exp->X_op_symbol = GOT_symbol;
8854 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8855 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8856 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8857 i.reloc[this_operand] = BFD_RELOC_64;
8858 else
8859 i.reloc[this_operand] = BFD_RELOC_32;
8860 }
8861
8862 else if (exp->X_op == O_absent
8863 || exp->X_op == O_illegal
8864 || exp->X_op == O_big)
8865 {
8866 inv_disp:
8867 as_bad (_("missing or invalid displacement expression `%s'"),
8868 disp_start);
8869 ret = 0;
8870 }
8871
8872 else if (flag_code == CODE_64BIT
8873 && !i.prefix[ADDR_PREFIX]
8874 && exp->X_op == O_constant)
8875 {
8876 /* Since displacement is signed extended to 64bit, don't allow
8877 disp32 and turn off disp32s if they are out of range. */
8878 i.types[this_operand].bitfield.disp32 = 0;
8879 if (!fits_in_signed_long (exp->X_add_number))
8880 {
8881 i.types[this_operand].bitfield.disp32s = 0;
8882 if (i.types[this_operand].bitfield.baseindex)
8883 {
8884 as_bad (_("0x%lx out range of signed 32bit displacement"),
8885 (long) exp->X_add_number);
8886 ret = 0;
8887 }
8888 }
8889 }
8890
8891 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8892 else if (exp->X_op != O_constant
8893 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8894 && exp_seg != absolute_section
8895 && exp_seg != text_section
8896 && exp_seg != data_section
8897 && exp_seg != bss_section
8898 && exp_seg != undefined_section
8899 && !bfd_is_com_section (exp_seg))
8900 {
8901 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8902 ret = 0;
8903 }
8904 #endif
8905
8906 /* Check if this is a displacement only operand. */
8907 bigdisp = i.types[this_operand];
8908 bigdisp.bitfield.disp8 = 0;
8909 bigdisp.bitfield.disp16 = 0;
8910 bigdisp.bitfield.disp32 = 0;
8911 bigdisp.bitfield.disp32s = 0;
8912 bigdisp.bitfield.disp64 = 0;
8913 if (operand_type_all_zero (&bigdisp))
8914 i.types[this_operand] = operand_type_and (i.types[this_operand],
8915 types);
8916
8917 return ret;
8918 }
8919
8920 /* Return the active addressing mode, taking address override and
8921 registers forming the address into consideration. Update the
8922 address override prefix if necessary. */
8923
8924 static enum flag_code
8925 i386_addressing_mode (void)
8926 {
8927 enum flag_code addr_mode;
8928
8929 if (i.prefix[ADDR_PREFIX])
8930 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8931 else
8932 {
8933 addr_mode = flag_code;
8934
8935 #if INFER_ADDR_PREFIX
8936 if (i.mem_operands == 0)
8937 {
8938 /* Infer address prefix from the first memory operand. */
8939 const reg_entry *addr_reg = i.base_reg;
8940
8941 if (addr_reg == NULL)
8942 addr_reg = i.index_reg;
8943
8944 if (addr_reg)
8945 {
8946 if (addr_reg->reg_num == RegEip
8947 || addr_reg->reg_num == RegEiz
8948 || addr_reg->reg_type.bitfield.dword)
8949 addr_mode = CODE_32BIT;
8950 else if (flag_code != CODE_64BIT
8951 && addr_reg->reg_type.bitfield.word)
8952 addr_mode = CODE_16BIT;
8953
8954 if (addr_mode != flag_code)
8955 {
8956 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8957 i.prefixes += 1;
8958 /* Change the size of any displacement too. At most one
8959 of Disp16 or Disp32 is set.
8960 FIXME. There doesn't seem to be any real need for
8961 separate Disp16 and Disp32 flags. The same goes for
8962 Imm16 and Imm32. Removing them would probably clean
8963 up the code quite a lot. */
8964 if (flag_code != CODE_64BIT
8965 && (i.types[this_operand].bitfield.disp16
8966 || i.types[this_operand].bitfield.disp32))
8967 i.types[this_operand]
8968 = operand_type_xor (i.types[this_operand], disp16_32);
8969 }
8970 }
8971 }
8972 #endif
8973 }
8974
8975 return addr_mode;
8976 }
8977
8978 /* Make sure the memory operand we've been dealt is valid.
8979 Return 1 on success, 0 on a failure. */
8980
8981 static int
8982 i386_index_check (const char *operand_string)
8983 {
8984 const char *kind = "base/index";
8985 enum flag_code addr_mode = i386_addressing_mode ();
8986
8987 if (current_templates->start->opcode_modifier.isstring
8988 && !current_templates->start->opcode_modifier.immext
8989 && (current_templates->end[-1].opcode_modifier.isstring
8990 || i.mem_operands))
8991 {
8992 /* Memory operands of string insns are special in that they only allow
8993 a single register (rDI, rSI, or rBX) as their memory address. */
8994 const reg_entry *expected_reg;
8995 static const char *di_si[][2] =
8996 {
8997 { "esi", "edi" },
8998 { "si", "di" },
8999 { "rsi", "rdi" }
9000 };
9001 static const char *bx[] = { "ebx", "bx", "rbx" };
9002
9003 kind = "string address";
9004
9005 if (current_templates->start->opcode_modifier.repprefixok)
9006 {
9007 i386_operand_type type = current_templates->end[-1].operand_types[0];
9008
9009 if (!type.bitfield.baseindex
9010 || ((!i.mem_operands != !intel_syntax)
9011 && current_templates->end[-1].operand_types[1]
9012 .bitfield.baseindex))
9013 type = current_templates->end[-1].operand_types[1];
9014 expected_reg = hash_find (reg_hash,
9015 di_si[addr_mode][type.bitfield.esseg]);
9016
9017 }
9018 else
9019 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9020
9021 if (i.base_reg != expected_reg
9022 || i.index_reg
9023 || operand_type_check (i.types[this_operand], disp))
9024 {
9025 /* The second memory operand must have the same size as
9026 the first one. */
9027 if (i.mem_operands
9028 && i.base_reg
9029 && !((addr_mode == CODE_64BIT
9030 && i.base_reg->reg_type.bitfield.qword)
9031 || (addr_mode == CODE_32BIT
9032 ? i.base_reg->reg_type.bitfield.dword
9033 : i.base_reg->reg_type.bitfield.word)))
9034 goto bad_address;
9035
9036 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9037 operand_string,
9038 intel_syntax ? '[' : '(',
9039 register_prefix,
9040 expected_reg->reg_name,
9041 intel_syntax ? ']' : ')');
9042 return 1;
9043 }
9044 else
9045 return 1;
9046
9047 bad_address:
9048 as_bad (_("`%s' is not a valid %s expression"),
9049 operand_string, kind);
9050 return 0;
9051 }
9052 else
9053 {
9054 if (addr_mode != CODE_16BIT)
9055 {
9056 /* 32-bit/64-bit checks. */
9057 if ((i.base_reg
9058 && (addr_mode == CODE_64BIT
9059 ? !i.base_reg->reg_type.bitfield.qword
9060 : !i.base_reg->reg_type.bitfield.dword)
9061 && (i.index_reg
9062 || (i.base_reg->reg_num
9063 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9064 || (i.index_reg
9065 && !i.index_reg->reg_type.bitfield.xmmword
9066 && !i.index_reg->reg_type.bitfield.ymmword
9067 && !i.index_reg->reg_type.bitfield.zmmword
9068 && ((addr_mode == CODE_64BIT
9069 ? !(i.index_reg->reg_type.bitfield.qword
9070 || i.index_reg->reg_num == RegRiz)
9071 : !(i.index_reg->reg_type.bitfield.dword
9072 || i.index_reg->reg_num == RegEiz))
9073 || !i.index_reg->reg_type.bitfield.baseindex)))
9074 goto bad_address;
9075
9076 /* bndmk, bndldx, and bndstx have special restrictions. */
9077 if (current_templates->start->base_opcode == 0xf30f1b
9078 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9079 {
9080 /* They cannot use RIP-relative addressing. */
9081 if (i.base_reg && i.base_reg->reg_num == RegRip)
9082 {
9083 as_bad (_("`%s' cannot be used here"), operand_string);
9084 return 0;
9085 }
9086
9087 /* bndldx and bndstx ignore their scale factor. */
9088 if (current_templates->start->base_opcode != 0xf30f1b
9089 && i.log2_scale_factor)
9090 as_warn (_("register scaling is being ignored here"));
9091 }
9092 }
9093 else
9094 {
9095 /* 16-bit checks. */
9096 if ((i.base_reg
9097 && (!i.base_reg->reg_type.bitfield.word
9098 || !i.base_reg->reg_type.bitfield.baseindex))
9099 || (i.index_reg
9100 && (!i.index_reg->reg_type.bitfield.word
9101 || !i.index_reg->reg_type.bitfield.baseindex
9102 || !(i.base_reg
9103 && i.base_reg->reg_num < 6
9104 && i.index_reg->reg_num >= 6
9105 && i.log2_scale_factor == 0))))
9106 goto bad_address;
9107 }
9108 }
9109 return 1;
9110 }
9111
9112 /* Handle vector immediates. */
9113
9114 static int
9115 RC_SAE_immediate (const char *imm_start)
9116 {
9117 unsigned int match_found, j;
9118 const char *pstr = imm_start;
9119 expressionS *exp;
9120
9121 if (*pstr != '{')
9122 return 0;
9123
9124 pstr++;
9125 match_found = 0;
9126 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9127 {
9128 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9129 {
9130 if (!i.rounding)
9131 {
9132 rc_op.type = RC_NamesTable[j].type;
9133 rc_op.operand = this_operand;
9134 i.rounding = &rc_op;
9135 }
9136 else
9137 {
9138 as_bad (_("duplicated `%s'"), imm_start);
9139 return 0;
9140 }
9141 pstr += RC_NamesTable[j].len;
9142 match_found = 1;
9143 break;
9144 }
9145 }
9146 if (!match_found)
9147 return 0;
9148
9149 if (*pstr++ != '}')
9150 {
9151 as_bad (_("Missing '}': '%s'"), imm_start);
9152 return 0;
9153 }
9154 /* RC/SAE immediate string should contain nothing more. */;
9155 if (*pstr != 0)
9156 {
9157 as_bad (_("Junk after '}': '%s'"), imm_start);
9158 return 0;
9159 }
9160
9161 exp = &im_expressions[i.imm_operands++];
9162 i.op[this_operand].imms = exp;
9163
9164 exp->X_op = O_constant;
9165 exp->X_add_number = 0;
9166 exp->X_add_symbol = (symbolS *) 0;
9167 exp->X_op_symbol = (symbolS *) 0;
9168
9169 i.types[this_operand].bitfield.imm8 = 1;
9170 return 1;
9171 }
9172
9173 /* Only string instructions can have a second memory operand, so
9174 reduce current_templates to just those if it contains any. */
9175 static int
9176 maybe_adjust_templates (void)
9177 {
9178 const insn_template *t;
9179
9180 gas_assert (i.mem_operands == 1);
9181
9182 for (t = current_templates->start; t < current_templates->end; ++t)
9183 if (t->opcode_modifier.isstring)
9184 break;
9185
9186 if (t < current_templates->end)
9187 {
9188 static templates aux_templates;
9189 bfd_boolean recheck;
9190
9191 aux_templates.start = t;
9192 for (; t < current_templates->end; ++t)
9193 if (!t->opcode_modifier.isstring)
9194 break;
9195 aux_templates.end = t;
9196
9197 /* Determine whether to re-check the first memory operand. */
9198 recheck = (aux_templates.start != current_templates->start
9199 || t != current_templates->end);
9200
9201 current_templates = &aux_templates;
9202
9203 if (recheck)
9204 {
9205 i.mem_operands = 0;
9206 if (i.memop1_string != NULL
9207 && i386_index_check (i.memop1_string) == 0)
9208 return 0;
9209 i.mem_operands = 1;
9210 }
9211 }
9212
9213 return 1;
9214 }
9215
9216 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9217 on error. */
9218
9219 static int
9220 i386_att_operand (char *operand_string)
9221 {
9222 const reg_entry *r;
9223 char *end_op;
9224 char *op_string = operand_string;
9225
9226 if (is_space_char (*op_string))
9227 ++op_string;
9228
9229 /* We check for an absolute prefix (differentiating,
9230 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9231 if (*op_string == ABSOLUTE_PREFIX)
9232 {
9233 ++op_string;
9234 if (is_space_char (*op_string))
9235 ++op_string;
9236 i.types[this_operand].bitfield.jumpabsolute = 1;
9237 }
9238
9239 /* Check if operand is a register. */
9240 if ((r = parse_register (op_string, &end_op)) != NULL)
9241 {
9242 i386_operand_type temp;
9243
9244 /* Check for a segment override by searching for ':' after a
9245 segment register. */
9246 op_string = end_op;
9247 if (is_space_char (*op_string))
9248 ++op_string;
9249 if (*op_string == ':'
9250 && (r->reg_type.bitfield.sreg2
9251 || r->reg_type.bitfield.sreg3))
9252 {
9253 switch (r->reg_num)
9254 {
9255 case 0:
9256 i.seg[i.mem_operands] = &es;
9257 break;
9258 case 1:
9259 i.seg[i.mem_operands] = &cs;
9260 break;
9261 case 2:
9262 i.seg[i.mem_operands] = &ss;
9263 break;
9264 case 3:
9265 i.seg[i.mem_operands] = &ds;
9266 break;
9267 case 4:
9268 i.seg[i.mem_operands] = &fs;
9269 break;
9270 case 5:
9271 i.seg[i.mem_operands] = &gs;
9272 break;
9273 }
9274
9275 /* Skip the ':' and whitespace. */
9276 ++op_string;
9277 if (is_space_char (*op_string))
9278 ++op_string;
9279
9280 if (!is_digit_char (*op_string)
9281 && !is_identifier_char (*op_string)
9282 && *op_string != '('
9283 && *op_string != ABSOLUTE_PREFIX)
9284 {
9285 as_bad (_("bad memory operand `%s'"), op_string);
9286 return 0;
9287 }
9288 /* Handle case of %es:*foo. */
9289 if (*op_string == ABSOLUTE_PREFIX)
9290 {
9291 ++op_string;
9292 if (is_space_char (*op_string))
9293 ++op_string;
9294 i.types[this_operand].bitfield.jumpabsolute = 1;
9295 }
9296 goto do_memory_reference;
9297 }
9298
9299 /* Handle vector operations. */
9300 if (*op_string == '{')
9301 {
9302 op_string = check_VecOperations (op_string, NULL);
9303 if (op_string == NULL)
9304 return 0;
9305 }
9306
9307 if (*op_string)
9308 {
9309 as_bad (_("junk `%s' after register"), op_string);
9310 return 0;
9311 }
9312 temp = r->reg_type;
9313 temp.bitfield.baseindex = 0;
9314 i.types[this_operand] = operand_type_or (i.types[this_operand],
9315 temp);
9316 i.types[this_operand].bitfield.unspecified = 0;
9317 i.op[this_operand].regs = r;
9318 i.reg_operands++;
9319 }
9320 else if (*op_string == REGISTER_PREFIX)
9321 {
9322 as_bad (_("bad register name `%s'"), op_string);
9323 return 0;
9324 }
9325 else if (*op_string == IMMEDIATE_PREFIX)
9326 {
9327 ++op_string;
9328 if (i.types[this_operand].bitfield.jumpabsolute)
9329 {
9330 as_bad (_("immediate operand illegal with absolute jump"));
9331 return 0;
9332 }
9333 if (!i386_immediate (op_string))
9334 return 0;
9335 }
9336 else if (RC_SAE_immediate (operand_string))
9337 {
9338 /* If it is a RC or SAE immediate, do nothing. */
9339 ;
9340 }
9341 else if (is_digit_char (*op_string)
9342 || is_identifier_char (*op_string)
9343 || *op_string == '"'
9344 || *op_string == '(')
9345 {
9346 /* This is a memory reference of some sort. */
9347 char *base_string;
9348
9349 /* Start and end of displacement string expression (if found). */
9350 char *displacement_string_start;
9351 char *displacement_string_end;
9352 char *vop_start;
9353
9354 do_memory_reference:
9355 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9356 return 0;
9357 if ((i.mem_operands == 1
9358 && !current_templates->start->opcode_modifier.isstring)
9359 || i.mem_operands == 2)
9360 {
9361 as_bad (_("too many memory references for `%s'"),
9362 current_templates->start->name);
9363 return 0;
9364 }
9365
9366 /* Check for base index form. We detect the base index form by
9367 looking for an ')' at the end of the operand, searching
9368 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9369 after the '('. */
9370 base_string = op_string + strlen (op_string);
9371
9372 /* Handle vector operations. */
9373 vop_start = strchr (op_string, '{');
9374 if (vop_start && vop_start < base_string)
9375 {
9376 if (check_VecOperations (vop_start, base_string) == NULL)
9377 return 0;
9378 base_string = vop_start;
9379 }
9380
9381 --base_string;
9382 if (is_space_char (*base_string))
9383 --base_string;
9384
9385 /* If we only have a displacement, set-up for it to be parsed later. */
9386 displacement_string_start = op_string;
9387 displacement_string_end = base_string + 1;
9388
9389 if (*base_string == ')')
9390 {
9391 char *temp_string;
9392 unsigned int parens_balanced = 1;
9393 /* We've already checked that the number of left & right ()'s are
9394 equal, so this loop will not be infinite. */
9395 do
9396 {
9397 base_string--;
9398 if (*base_string == ')')
9399 parens_balanced++;
9400 if (*base_string == '(')
9401 parens_balanced--;
9402 }
9403 while (parens_balanced);
9404
9405 temp_string = base_string;
9406
9407 /* Skip past '(' and whitespace. */
9408 ++base_string;
9409 if (is_space_char (*base_string))
9410 ++base_string;
9411
9412 if (*base_string == ','
9413 || ((i.base_reg = parse_register (base_string, &end_op))
9414 != NULL))
9415 {
9416 displacement_string_end = temp_string;
9417
9418 i.types[this_operand].bitfield.baseindex = 1;
9419
9420 if (i.base_reg)
9421 {
9422 base_string = end_op;
9423 if (is_space_char (*base_string))
9424 ++base_string;
9425 }
9426
9427 /* There may be an index reg or scale factor here. */
9428 if (*base_string == ',')
9429 {
9430 ++base_string;
9431 if (is_space_char (*base_string))
9432 ++base_string;
9433
9434 if ((i.index_reg = parse_register (base_string, &end_op))
9435 != NULL)
9436 {
9437 base_string = end_op;
9438 if (is_space_char (*base_string))
9439 ++base_string;
9440 if (*base_string == ',')
9441 {
9442 ++base_string;
9443 if (is_space_char (*base_string))
9444 ++base_string;
9445 }
9446 else if (*base_string != ')')
9447 {
9448 as_bad (_("expecting `,' or `)' "
9449 "after index register in `%s'"),
9450 operand_string);
9451 return 0;
9452 }
9453 }
9454 else if (*base_string == REGISTER_PREFIX)
9455 {
9456 end_op = strchr (base_string, ',');
9457 if (end_op)
9458 *end_op = '\0';
9459 as_bad (_("bad register name `%s'"), base_string);
9460 return 0;
9461 }
9462
9463 /* Check for scale factor. */
9464 if (*base_string != ')')
9465 {
9466 char *end_scale = i386_scale (base_string);
9467
9468 if (!end_scale)
9469 return 0;
9470
9471 base_string = end_scale;
9472 if (is_space_char (*base_string))
9473 ++base_string;
9474 if (*base_string != ')')
9475 {
9476 as_bad (_("expecting `)' "
9477 "after scale factor in `%s'"),
9478 operand_string);
9479 return 0;
9480 }
9481 }
9482 else if (!i.index_reg)
9483 {
9484 as_bad (_("expecting index register or scale factor "
9485 "after `,'; got '%c'"),
9486 *base_string);
9487 return 0;
9488 }
9489 }
9490 else if (*base_string != ')')
9491 {
9492 as_bad (_("expecting `,' or `)' "
9493 "after base register in `%s'"),
9494 operand_string);
9495 return 0;
9496 }
9497 }
9498 else if (*base_string == REGISTER_PREFIX)
9499 {
9500 end_op = strchr (base_string, ',');
9501 if (end_op)
9502 *end_op = '\0';
9503 as_bad (_("bad register name `%s'"), base_string);
9504 return 0;
9505 }
9506 }
9507
9508 /* If there's an expression beginning the operand, parse it,
9509 assuming displacement_string_start and
9510 displacement_string_end are meaningful. */
9511 if (displacement_string_start != displacement_string_end)
9512 {
9513 if (!i386_displacement (displacement_string_start,
9514 displacement_string_end))
9515 return 0;
9516 }
9517
9518 /* Special case for (%dx) while doing input/output op. */
9519 if (i.base_reg
9520 && operand_type_equal (&i.base_reg->reg_type,
9521 &reg16_inoutportreg)
9522 && i.index_reg == 0
9523 && i.log2_scale_factor == 0
9524 && i.seg[i.mem_operands] == 0
9525 && !operand_type_check (i.types[this_operand], disp))
9526 {
9527 i.types[this_operand] = inoutportreg;
9528 return 1;
9529 }
9530
9531 if (i386_index_check (operand_string) == 0)
9532 return 0;
9533 i.types[this_operand].bitfield.mem = 1;
9534 if (i.mem_operands == 0)
9535 i.memop1_string = xstrdup (operand_string);
9536 i.mem_operands++;
9537 }
9538 else
9539 {
9540 /* It's not a memory operand; argh! */
9541 as_bad (_("invalid char %s beginning operand %d `%s'"),
9542 output_invalid (*op_string),
9543 this_operand + 1,
9544 op_string);
9545 return 0;
9546 }
9547 return 1; /* Normal return. */
9548 }
9549 \f
9550 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9551 that an rs_machine_dependent frag may reach. */
9552
9553 unsigned int
9554 i386_frag_max_var (fragS *frag)
9555 {
9556 /* The only relaxable frags are for jumps.
9557 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9558 gas_assert (frag->fr_type == rs_machine_dependent);
9559 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9560 }
9561
9562 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9563 static int
9564 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9565 {
9566 /* STT_GNU_IFUNC symbol must go through PLT. */
9567 if ((symbol_get_bfdsym (fr_symbol)->flags
9568 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9569 return 0;
9570
9571 if (!S_IS_EXTERNAL (fr_symbol))
9572 /* Symbol may be weak or local. */
9573 return !S_IS_WEAK (fr_symbol);
9574
9575 /* Global symbols with non-default visibility can't be preempted. */
9576 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9577 return 1;
9578
9579 if (fr_var != NO_RELOC)
9580 switch ((enum bfd_reloc_code_real) fr_var)
9581 {
9582 case BFD_RELOC_386_PLT32:
9583 case BFD_RELOC_X86_64_PLT32:
9584 /* Symbol with PLT relocation may be preempted. */
9585 return 0;
9586 default:
9587 abort ();
9588 }
9589
9590 /* Global symbols with default visibility in a shared library may be
9591 preempted by another definition. */
9592 return !shared;
9593 }
9594 #endif
9595
9596 /* md_estimate_size_before_relax()
9597
9598 Called just before relax() for rs_machine_dependent frags. The x86
9599 assembler uses these frags to handle variable size jump
9600 instructions.
9601
9602 Any symbol that is now undefined will not become defined.
9603 Return the correct fr_subtype in the frag.
9604 Return the initial "guess for variable size of frag" to caller.
9605 The guess is actually the growth beyond the fixed part. Whatever
9606 we do to grow the fixed or variable part contributes to our
9607 returned value. */
9608
9609 int
9610 md_estimate_size_before_relax (fragS *fragP, segT segment)
9611 {
9612 /* We've already got fragP->fr_subtype right; all we have to do is
9613 check for un-relaxable symbols. On an ELF system, we can't relax
9614 an externally visible symbol, because it may be overridden by a
9615 shared library. */
9616 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9617 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9618 || (IS_ELF
9619 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9620 fragP->fr_var))
9621 #endif
9622 #if defined (OBJ_COFF) && defined (TE_PE)
9623 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9624 && S_IS_WEAK (fragP->fr_symbol))
9625 #endif
9626 )
9627 {
9628 /* Symbol is undefined in this segment, or we need to keep a
9629 reloc so that weak symbols can be overridden. */
9630 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9631 enum bfd_reloc_code_real reloc_type;
9632 unsigned char *opcode;
9633 int old_fr_fix;
9634
9635 if (fragP->fr_var != NO_RELOC)
9636 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9637 else if (size == 2)
9638 reloc_type = BFD_RELOC_16_PCREL;
9639 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9640 else if (need_plt32_p (fragP->fr_symbol))
9641 reloc_type = BFD_RELOC_X86_64_PLT32;
9642 #endif
9643 else
9644 reloc_type = BFD_RELOC_32_PCREL;
9645
9646 old_fr_fix = fragP->fr_fix;
9647 opcode = (unsigned char *) fragP->fr_opcode;
9648
9649 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9650 {
9651 case UNCOND_JUMP:
9652 /* Make jmp (0xeb) a (d)word displacement jump. */
9653 opcode[0] = 0xe9;
9654 fragP->fr_fix += size;
9655 fix_new (fragP, old_fr_fix, size,
9656 fragP->fr_symbol,
9657 fragP->fr_offset, 1,
9658 reloc_type);
9659 break;
9660
9661 case COND_JUMP86:
9662 if (size == 2
9663 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9664 {
9665 /* Negate the condition, and branch past an
9666 unconditional jump. */
9667 opcode[0] ^= 1;
9668 opcode[1] = 3;
9669 /* Insert an unconditional jump. */
9670 opcode[2] = 0xe9;
9671 /* We added two extra opcode bytes, and have a two byte
9672 offset. */
9673 fragP->fr_fix += 2 + 2;
9674 fix_new (fragP, old_fr_fix + 2, 2,
9675 fragP->fr_symbol,
9676 fragP->fr_offset, 1,
9677 reloc_type);
9678 break;
9679 }
9680 /* Fall through. */
9681
9682 case COND_JUMP:
9683 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9684 {
9685 fixS *fixP;
9686
9687 fragP->fr_fix += 1;
9688 fixP = fix_new (fragP, old_fr_fix, 1,
9689 fragP->fr_symbol,
9690 fragP->fr_offset, 1,
9691 BFD_RELOC_8_PCREL);
9692 fixP->fx_signed = 1;
9693 break;
9694 }
9695
9696 /* This changes the byte-displacement jump 0x7N
9697 to the (d)word-displacement jump 0x0f,0x8N. */
9698 opcode[1] = opcode[0] + 0x10;
9699 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9700 /* We've added an opcode byte. */
9701 fragP->fr_fix += 1 + size;
9702 fix_new (fragP, old_fr_fix + 1, size,
9703 fragP->fr_symbol,
9704 fragP->fr_offset, 1,
9705 reloc_type);
9706 break;
9707
9708 default:
9709 BAD_CASE (fragP->fr_subtype);
9710 break;
9711 }
9712 frag_wane (fragP);
9713 return fragP->fr_fix - old_fr_fix;
9714 }
9715
9716 /* Guess size depending on current relax state. Initially the relax
9717 state will correspond to a short jump and we return 1, because
9718 the variable part of the frag (the branch offset) is one byte
9719 long. However, we can relax a section more than once and in that
9720 case we must either set fr_subtype back to the unrelaxed state,
9721 or return the value for the appropriate branch. */
9722 return md_relax_table[fragP->fr_subtype].rlx_length;
9723 }
9724
9725 /* Called after relax() is finished.
9726
9727 In: Address of frag.
9728 fr_type == rs_machine_dependent.
9729 fr_subtype is what the address relaxed to.
9730
9731 Out: Any fixSs and constants are set up.
9732 Caller will turn frag into a ".space 0". */
9733
9734 void
9735 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9736 fragS *fragP)
9737 {
9738 unsigned char *opcode;
9739 unsigned char *where_to_put_displacement = NULL;
9740 offsetT target_address;
9741 offsetT opcode_address;
9742 unsigned int extension = 0;
9743 offsetT displacement_from_opcode_start;
9744
9745 opcode = (unsigned char *) fragP->fr_opcode;
9746
9747 /* Address we want to reach in file space. */
9748 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9749
9750 /* Address opcode resides at in file space. */
9751 opcode_address = fragP->fr_address + fragP->fr_fix;
9752
9753 /* Displacement from opcode start to fill into instruction. */
9754 displacement_from_opcode_start = target_address - opcode_address;
9755
9756 if ((fragP->fr_subtype & BIG) == 0)
9757 {
9758 /* Don't have to change opcode. */
9759 extension = 1; /* 1 opcode + 1 displacement */
9760 where_to_put_displacement = &opcode[1];
9761 }
9762 else
9763 {
9764 if (no_cond_jump_promotion
9765 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9766 as_warn_where (fragP->fr_file, fragP->fr_line,
9767 _("long jump required"));
9768
9769 switch (fragP->fr_subtype)
9770 {
9771 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9772 extension = 4; /* 1 opcode + 4 displacement */
9773 opcode[0] = 0xe9;
9774 where_to_put_displacement = &opcode[1];
9775 break;
9776
9777 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9778 extension = 2; /* 1 opcode + 2 displacement */
9779 opcode[0] = 0xe9;
9780 where_to_put_displacement = &opcode[1];
9781 break;
9782
9783 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9784 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9785 extension = 5; /* 2 opcode + 4 displacement */
9786 opcode[1] = opcode[0] + 0x10;
9787 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9788 where_to_put_displacement = &opcode[2];
9789 break;
9790
9791 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9792 extension = 3; /* 2 opcode + 2 displacement */
9793 opcode[1] = opcode[0] + 0x10;
9794 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9795 where_to_put_displacement = &opcode[2];
9796 break;
9797
9798 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9799 extension = 4;
9800 opcode[0] ^= 1;
9801 opcode[1] = 3;
9802 opcode[2] = 0xe9;
9803 where_to_put_displacement = &opcode[3];
9804 break;
9805
9806 default:
9807 BAD_CASE (fragP->fr_subtype);
9808 break;
9809 }
9810 }
9811
9812 /* If size if less then four we are sure that the operand fits,
9813 but if it's 4, then it could be that the displacement is larger
9814 then -/+ 2GB. */
9815 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9816 && object_64bit
9817 && ((addressT) (displacement_from_opcode_start - extension
9818 + ((addressT) 1 << 31))
9819 > (((addressT) 2 << 31) - 1)))
9820 {
9821 as_bad_where (fragP->fr_file, fragP->fr_line,
9822 _("jump target out of range"));
9823 /* Make us emit 0. */
9824 displacement_from_opcode_start = extension;
9825 }
9826 /* Now put displacement after opcode. */
9827 md_number_to_chars ((char *) where_to_put_displacement,
9828 (valueT) (displacement_from_opcode_start - extension),
9829 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9830 fragP->fr_fix += extension;
9831 }
9832 \f
9833 /* Apply a fixup (fixP) to segment data, once it has been determined
9834 by our caller that we have all the info we need to fix it up.
9835
9836 Parameter valP is the pointer to the value of the bits.
9837
9838 On the 386, immediates, displacements, and data pointers are all in
9839 the same (little-endian) format, so we don't need to care about which
9840 we are handling. */
9841
9842 void
9843 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9844 {
9845 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9846 valueT value = *valP;
9847
9848 #if !defined (TE_Mach)
9849 if (fixP->fx_pcrel)
9850 {
9851 switch (fixP->fx_r_type)
9852 {
9853 default:
9854 break;
9855
9856 case BFD_RELOC_64:
9857 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9858 break;
9859 case BFD_RELOC_32:
9860 case BFD_RELOC_X86_64_32S:
9861 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9862 break;
9863 case BFD_RELOC_16:
9864 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9865 break;
9866 case BFD_RELOC_8:
9867 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9868 break;
9869 }
9870 }
9871
9872 if (fixP->fx_addsy != NULL
9873 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9874 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9875 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9876 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9877 && !use_rela_relocations)
9878 {
9879 /* This is a hack. There should be a better way to handle this.
9880 This covers for the fact that bfd_install_relocation will
9881 subtract the current location (for partial_inplace, PC relative
9882 relocations); see more below. */
9883 #ifndef OBJ_AOUT
9884 if (IS_ELF
9885 #ifdef TE_PE
9886 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9887 #endif
9888 )
9889 value += fixP->fx_where + fixP->fx_frag->fr_address;
9890 #endif
9891 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9892 if (IS_ELF)
9893 {
9894 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9895
9896 if ((sym_seg == seg
9897 || (symbol_section_p (fixP->fx_addsy)
9898 && sym_seg != absolute_section))
9899 && !generic_force_reloc (fixP))
9900 {
9901 /* Yes, we add the values in twice. This is because
9902 bfd_install_relocation subtracts them out again. I think
9903 bfd_install_relocation is broken, but I don't dare change
9904 it. FIXME. */
9905 value += fixP->fx_where + fixP->fx_frag->fr_address;
9906 }
9907 }
9908 #endif
9909 #if defined (OBJ_COFF) && defined (TE_PE)
9910 /* For some reason, the PE format does not store a
9911 section address offset for a PC relative symbol. */
9912 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9913 || S_IS_WEAK (fixP->fx_addsy))
9914 value += md_pcrel_from (fixP);
9915 #endif
9916 }
9917 #if defined (OBJ_COFF) && defined (TE_PE)
9918 if (fixP->fx_addsy != NULL
9919 && S_IS_WEAK (fixP->fx_addsy)
9920 /* PR 16858: Do not modify weak function references. */
9921 && ! fixP->fx_pcrel)
9922 {
9923 #if !defined (TE_PEP)
9924 /* For x86 PE weak function symbols are neither PC-relative
9925 nor do they set S_IS_FUNCTION. So the only reliable way
9926 to detect them is to check the flags of their containing
9927 section. */
9928 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9929 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9930 ;
9931 else
9932 #endif
9933 value -= S_GET_VALUE (fixP->fx_addsy);
9934 }
9935 #endif
9936
9937 /* Fix a few things - the dynamic linker expects certain values here,
9938 and we must not disappoint it. */
9939 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9940 if (IS_ELF && fixP->fx_addsy)
9941 switch (fixP->fx_r_type)
9942 {
9943 case BFD_RELOC_386_PLT32:
9944 case BFD_RELOC_X86_64_PLT32:
9945 /* Make the jump instruction point to the address of the operand. At
9946 runtime we merely add the offset to the actual PLT entry. */
9947 value = -4;
9948 break;
9949
9950 case BFD_RELOC_386_TLS_GD:
9951 case BFD_RELOC_386_TLS_LDM:
9952 case BFD_RELOC_386_TLS_IE_32:
9953 case BFD_RELOC_386_TLS_IE:
9954 case BFD_RELOC_386_TLS_GOTIE:
9955 case BFD_RELOC_386_TLS_GOTDESC:
9956 case BFD_RELOC_X86_64_TLSGD:
9957 case BFD_RELOC_X86_64_TLSLD:
9958 case BFD_RELOC_X86_64_GOTTPOFF:
9959 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9960 value = 0; /* Fully resolved at runtime. No addend. */
9961 /* Fallthrough */
9962 case BFD_RELOC_386_TLS_LE:
9963 case BFD_RELOC_386_TLS_LDO_32:
9964 case BFD_RELOC_386_TLS_LE_32:
9965 case BFD_RELOC_X86_64_DTPOFF32:
9966 case BFD_RELOC_X86_64_DTPOFF64:
9967 case BFD_RELOC_X86_64_TPOFF32:
9968 case BFD_RELOC_X86_64_TPOFF64:
9969 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9970 break;
9971
9972 case BFD_RELOC_386_TLS_DESC_CALL:
9973 case BFD_RELOC_X86_64_TLSDESC_CALL:
9974 value = 0; /* Fully resolved at runtime. No addend. */
9975 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9976 fixP->fx_done = 0;
9977 return;
9978
9979 case BFD_RELOC_VTABLE_INHERIT:
9980 case BFD_RELOC_VTABLE_ENTRY:
9981 fixP->fx_done = 0;
9982 return;
9983
9984 default:
9985 break;
9986 }
9987 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9988 *valP = value;
9989 #endif /* !defined (TE_Mach) */
9990
9991 /* Are we finished with this relocation now? */
9992 if (fixP->fx_addsy == NULL)
9993 fixP->fx_done = 1;
9994 #if defined (OBJ_COFF) && defined (TE_PE)
9995 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9996 {
9997 fixP->fx_done = 0;
9998 /* Remember value for tc_gen_reloc. */
9999 fixP->fx_addnumber = value;
10000 /* Clear out the frag for now. */
10001 value = 0;
10002 }
10003 #endif
10004 else if (use_rela_relocations)
10005 {
10006 fixP->fx_no_overflow = 1;
10007 /* Remember value for tc_gen_reloc. */
10008 fixP->fx_addnumber = value;
10009 value = 0;
10010 }
10011
10012 md_number_to_chars (p, value, fixP->fx_size);
10013 }
10014 \f
10015 const char *
10016 md_atof (int type, char *litP, int *sizeP)
10017 {
10018 /* This outputs the LITTLENUMs in REVERSE order;
10019 in accord with the bigendian 386. */
10020 return ieee_md_atof (type, litP, sizeP, FALSE);
10021 }
10022 \f
10023 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10024
10025 static char *
10026 output_invalid (int c)
10027 {
10028 if (ISPRINT (c))
10029 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10030 "'%c'", c);
10031 else
10032 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10033 "(0x%x)", (unsigned char) c);
10034 return output_invalid_buf;
10035 }
10036
10037 /* REG_STRING starts *before* REGISTER_PREFIX. */
10038
10039 static const reg_entry *
10040 parse_real_register (char *reg_string, char **end_op)
10041 {
10042 char *s = reg_string;
10043 char *p;
10044 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10045 const reg_entry *r;
10046
10047 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10048 if (*s == REGISTER_PREFIX)
10049 ++s;
10050
10051 if (is_space_char (*s))
10052 ++s;
10053
10054 p = reg_name_given;
10055 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10056 {
10057 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10058 return (const reg_entry *) NULL;
10059 s++;
10060 }
10061
10062 /* For naked regs, make sure that we are not dealing with an identifier.
10063 This prevents confusing an identifier like `eax_var' with register
10064 `eax'. */
10065 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10066 return (const reg_entry *) NULL;
10067
10068 *end_op = s;
10069
10070 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10071
10072 /* Handle floating point regs, allowing spaces in the (i) part. */
10073 if (r == i386_regtab /* %st is first entry of table */)
10074 {
10075 if (is_space_char (*s))
10076 ++s;
10077 if (*s == '(')
10078 {
10079 ++s;
10080 if (is_space_char (*s))
10081 ++s;
10082 if (*s >= '0' && *s <= '7')
10083 {
10084 int fpr = *s - '0';
10085 ++s;
10086 if (is_space_char (*s))
10087 ++s;
10088 if (*s == ')')
10089 {
10090 *end_op = s + 1;
10091 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10092 know (r);
10093 return r + fpr;
10094 }
10095 }
10096 /* We have "%st(" then garbage. */
10097 return (const reg_entry *) NULL;
10098 }
10099 }
10100
10101 if (r == NULL || allow_pseudo_reg)
10102 return r;
10103
10104 if (operand_type_all_zero (&r->reg_type))
10105 return (const reg_entry *) NULL;
10106
10107 if ((r->reg_type.bitfield.dword
10108 || r->reg_type.bitfield.sreg3
10109 || r->reg_type.bitfield.control
10110 || r->reg_type.bitfield.debug
10111 || r->reg_type.bitfield.test)
10112 && !cpu_arch_flags.bitfield.cpui386)
10113 return (const reg_entry *) NULL;
10114
10115 if (r->reg_type.bitfield.tbyte
10116 && !cpu_arch_flags.bitfield.cpu8087
10117 && !cpu_arch_flags.bitfield.cpu287
10118 && !cpu_arch_flags.bitfield.cpu387)
10119 return (const reg_entry *) NULL;
10120
10121 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
10122 return (const reg_entry *) NULL;
10123
10124 if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
10125 return (const reg_entry *) NULL;
10126
10127 if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
10128 return (const reg_entry *) NULL;
10129
10130 if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
10131 return (const reg_entry *) NULL;
10132
10133 if (r->reg_type.bitfield.regmask
10134 && !cpu_arch_flags.bitfield.cpuregmask)
10135 return (const reg_entry *) NULL;
10136
10137 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10138 if (!allow_index_reg
10139 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10140 return (const reg_entry *) NULL;
10141
10142 /* Upper 16 vector register is only available with VREX in 64bit
10143 mode. */
10144 if ((r->reg_flags & RegVRex))
10145 {
10146 if (i.vec_encoding == vex_encoding_default)
10147 i.vec_encoding = vex_encoding_evex;
10148
10149 if (!cpu_arch_flags.bitfield.cpuvrex
10150 || i.vec_encoding != vex_encoding_evex
10151 || flag_code != CODE_64BIT)
10152 return (const reg_entry *) NULL;
10153 }
10154
10155 if (((r->reg_flags & (RegRex64 | RegRex))
10156 || r->reg_type.bitfield.qword)
10157 && (!cpu_arch_flags.bitfield.cpulm
10158 || !operand_type_equal (&r->reg_type, &control))
10159 && flag_code != CODE_64BIT)
10160 return (const reg_entry *) NULL;
10161
10162 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10163 return (const reg_entry *) NULL;
10164
10165 return r;
10166 }
10167
10168 /* REG_STRING starts *before* REGISTER_PREFIX. */
10169
10170 static const reg_entry *
10171 parse_register (char *reg_string, char **end_op)
10172 {
10173 const reg_entry *r;
10174
10175 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10176 r = parse_real_register (reg_string, end_op);
10177 else
10178 r = NULL;
10179 if (!r)
10180 {
10181 char *save = input_line_pointer;
10182 char c;
10183 symbolS *symbolP;
10184
10185 input_line_pointer = reg_string;
10186 c = get_symbol_name (&reg_string);
10187 symbolP = symbol_find (reg_string);
10188 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10189 {
10190 const expressionS *e = symbol_get_value_expression (symbolP);
10191
10192 know (e->X_op == O_register);
10193 know (e->X_add_number >= 0
10194 && (valueT) e->X_add_number < i386_regtab_size);
10195 r = i386_regtab + e->X_add_number;
10196 if ((r->reg_flags & RegVRex))
10197 i.vec_encoding = vex_encoding_evex;
10198 *end_op = input_line_pointer;
10199 }
10200 *input_line_pointer = c;
10201 input_line_pointer = save;
10202 }
10203 return r;
10204 }
10205
10206 int
10207 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10208 {
10209 const reg_entry *r;
10210 char *end = input_line_pointer;
10211
10212 *end = *nextcharP;
10213 r = parse_register (name, &input_line_pointer);
10214 if (r && end <= input_line_pointer)
10215 {
10216 *nextcharP = *input_line_pointer;
10217 *input_line_pointer = 0;
10218 e->X_op = O_register;
10219 e->X_add_number = r - i386_regtab;
10220 return 1;
10221 }
10222 input_line_pointer = end;
10223 *end = 0;
10224 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10225 }
10226
10227 void
10228 md_operand (expressionS *e)
10229 {
10230 char *end;
10231 const reg_entry *r;
10232
10233 switch (*input_line_pointer)
10234 {
10235 case REGISTER_PREFIX:
10236 r = parse_real_register (input_line_pointer, &end);
10237 if (r)
10238 {
10239 e->X_op = O_register;
10240 e->X_add_number = r - i386_regtab;
10241 input_line_pointer = end;
10242 }
10243 break;
10244
10245 case '[':
10246 gas_assert (intel_syntax);
10247 end = input_line_pointer++;
10248 expression (e);
10249 if (*input_line_pointer == ']')
10250 {
10251 ++input_line_pointer;
10252 e->X_op_symbol = make_expr_symbol (e);
10253 e->X_add_symbol = NULL;
10254 e->X_add_number = 0;
10255 e->X_op = O_index;
10256 }
10257 else
10258 {
10259 e->X_op = O_absent;
10260 input_line_pointer = end;
10261 }
10262 break;
10263 }
10264 }
10265
10266 \f
10267 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10268 const char *md_shortopts = "kVQ:sqnO::";
10269 #else
10270 const char *md_shortopts = "qnO::";
10271 #endif
10272
10273 #define OPTION_32 (OPTION_MD_BASE + 0)
10274 #define OPTION_64 (OPTION_MD_BASE + 1)
10275 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10276 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10277 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10278 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10279 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10280 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10281 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10282 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
10283 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10284 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10285 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10286 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10287 #define OPTION_X32 (OPTION_MD_BASE + 14)
10288 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10289 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10290 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10291 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10292 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10293 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10294 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10295 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10296 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10297 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10298 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
10299
10300 struct option md_longopts[] =
10301 {
10302 {"32", no_argument, NULL, OPTION_32},
10303 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10304 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10305 {"64", no_argument, NULL, OPTION_64},
10306 #endif
10307 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10308 {"x32", no_argument, NULL, OPTION_X32},
10309 {"mshared", no_argument, NULL, OPTION_MSHARED},
10310 #endif
10311 {"divide", no_argument, NULL, OPTION_DIVIDE},
10312 {"march", required_argument, NULL, OPTION_MARCH},
10313 {"mtune", required_argument, NULL, OPTION_MTUNE},
10314 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10315 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10316 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10317 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10318 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
10319 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10320 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10321 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10322 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10323 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10324 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10325 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10326 # if defined (TE_PE) || defined (TE_PEP)
10327 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10328 #endif
10329 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10330 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10331 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10332 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10333 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10334 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10335 {NULL, no_argument, NULL, 0}
10336 };
10337 size_t md_longopts_size = sizeof (md_longopts);
10338
10339 int
10340 md_parse_option (int c, const char *arg)
10341 {
10342 unsigned int j;
10343 char *arch, *next, *saved;
10344
10345 switch (c)
10346 {
10347 case 'n':
10348 optimize_align_code = 0;
10349 break;
10350
10351 case 'q':
10352 quiet_warnings = 1;
10353 break;
10354
10355 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10356 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10357 should be emitted or not. FIXME: Not implemented. */
10358 case 'Q':
10359 break;
10360
10361 /* -V: SVR4 argument to print version ID. */
10362 case 'V':
10363 print_version_id ();
10364 break;
10365
10366 /* -k: Ignore for FreeBSD compatibility. */
10367 case 'k':
10368 break;
10369
10370 case 's':
10371 /* -s: On i386 Solaris, this tells the native assembler to use
10372 .stab instead of .stab.excl. We always use .stab anyhow. */
10373 break;
10374
10375 case OPTION_MSHARED:
10376 shared = 1;
10377 break;
10378 #endif
10379 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10380 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10381 case OPTION_64:
10382 {
10383 const char **list, **l;
10384
10385 list = bfd_target_list ();
10386 for (l = list; *l != NULL; l++)
10387 if (CONST_STRNEQ (*l, "elf64-x86-64")
10388 || strcmp (*l, "coff-x86-64") == 0
10389 || strcmp (*l, "pe-x86-64") == 0
10390 || strcmp (*l, "pei-x86-64") == 0
10391 || strcmp (*l, "mach-o-x86-64") == 0)
10392 {
10393 default_arch = "x86_64";
10394 break;
10395 }
10396 if (*l == NULL)
10397 as_fatal (_("no compiled in support for x86_64"));
10398 free (list);
10399 }
10400 break;
10401 #endif
10402
10403 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10404 case OPTION_X32:
10405 if (IS_ELF)
10406 {
10407 const char **list, **l;
10408
10409 list = bfd_target_list ();
10410 for (l = list; *l != NULL; l++)
10411 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10412 {
10413 default_arch = "x86_64:32";
10414 break;
10415 }
10416 if (*l == NULL)
10417 as_fatal (_("no compiled in support for 32bit x86_64"));
10418 free (list);
10419 }
10420 else
10421 as_fatal (_("32bit x86_64 is only supported for ELF"));
10422 break;
10423 #endif
10424
10425 case OPTION_32:
10426 default_arch = "i386";
10427 break;
10428
10429 case OPTION_DIVIDE:
10430 #ifdef SVR4_COMMENT_CHARS
10431 {
10432 char *n, *t;
10433 const char *s;
10434
10435 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10436 t = n;
10437 for (s = i386_comment_chars; *s != '\0'; s++)
10438 if (*s != '/')
10439 *t++ = *s;
10440 *t = '\0';
10441 i386_comment_chars = n;
10442 }
10443 #endif
10444 break;
10445
10446 case OPTION_MARCH:
10447 saved = xstrdup (arg);
10448 arch = saved;
10449 /* Allow -march=+nosse. */
10450 if (*arch == '+')
10451 arch++;
10452 do
10453 {
10454 if (*arch == '.')
10455 as_fatal (_("invalid -march= option: `%s'"), arg);
10456 next = strchr (arch, '+');
10457 if (next)
10458 *next++ = '\0';
10459 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10460 {
10461 if (strcmp (arch, cpu_arch [j].name) == 0)
10462 {
10463 /* Processor. */
10464 if (! cpu_arch[j].flags.bitfield.cpui386)
10465 continue;
10466
10467 cpu_arch_name = cpu_arch[j].name;
10468 cpu_sub_arch_name = NULL;
10469 cpu_arch_flags = cpu_arch[j].flags;
10470 cpu_arch_isa = cpu_arch[j].type;
10471 cpu_arch_isa_flags = cpu_arch[j].flags;
10472 if (!cpu_arch_tune_set)
10473 {
10474 cpu_arch_tune = cpu_arch_isa;
10475 cpu_arch_tune_flags = cpu_arch_isa_flags;
10476 }
10477 break;
10478 }
10479 else if (*cpu_arch [j].name == '.'
10480 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10481 {
10482 /* ISA extension. */
10483 i386_cpu_flags flags;
10484
10485 flags = cpu_flags_or (cpu_arch_flags,
10486 cpu_arch[j].flags);
10487
10488 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10489 {
10490 if (cpu_sub_arch_name)
10491 {
10492 char *name = cpu_sub_arch_name;
10493 cpu_sub_arch_name = concat (name,
10494 cpu_arch[j].name,
10495 (const char *) NULL);
10496 free (name);
10497 }
10498 else
10499 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10500 cpu_arch_flags = flags;
10501 cpu_arch_isa_flags = flags;
10502 }
10503 break;
10504 }
10505 }
10506
10507 if (j >= ARRAY_SIZE (cpu_arch))
10508 {
10509 /* Disable an ISA extension. */
10510 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10511 if (strcmp (arch, cpu_noarch [j].name) == 0)
10512 {
10513 i386_cpu_flags flags;
10514
10515 flags = cpu_flags_and_not (cpu_arch_flags,
10516 cpu_noarch[j].flags);
10517 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10518 {
10519 if (cpu_sub_arch_name)
10520 {
10521 char *name = cpu_sub_arch_name;
10522 cpu_sub_arch_name = concat (arch,
10523 (const char *) NULL);
10524 free (name);
10525 }
10526 else
10527 cpu_sub_arch_name = xstrdup (arch);
10528 cpu_arch_flags = flags;
10529 cpu_arch_isa_flags = flags;
10530 }
10531 break;
10532 }
10533
10534 if (j >= ARRAY_SIZE (cpu_noarch))
10535 j = ARRAY_SIZE (cpu_arch);
10536 }
10537
10538 if (j >= ARRAY_SIZE (cpu_arch))
10539 as_fatal (_("invalid -march= option: `%s'"), arg);
10540
10541 arch = next;
10542 }
10543 while (next != NULL);
10544 free (saved);
10545 break;
10546
10547 case OPTION_MTUNE:
10548 if (*arg == '.')
10549 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10550 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10551 {
10552 if (strcmp (arg, cpu_arch [j].name) == 0)
10553 {
10554 cpu_arch_tune_set = 1;
10555 cpu_arch_tune = cpu_arch [j].type;
10556 cpu_arch_tune_flags = cpu_arch[j].flags;
10557 break;
10558 }
10559 }
10560 if (j >= ARRAY_SIZE (cpu_arch))
10561 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10562 break;
10563
10564 case OPTION_MMNEMONIC:
10565 if (strcasecmp (arg, "att") == 0)
10566 intel_mnemonic = 0;
10567 else if (strcasecmp (arg, "intel") == 0)
10568 intel_mnemonic = 1;
10569 else
10570 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10571 break;
10572
10573 case OPTION_MSYNTAX:
10574 if (strcasecmp (arg, "att") == 0)
10575 intel_syntax = 0;
10576 else if (strcasecmp (arg, "intel") == 0)
10577 intel_syntax = 1;
10578 else
10579 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10580 break;
10581
10582 case OPTION_MINDEX_REG:
10583 allow_index_reg = 1;
10584 break;
10585
10586 case OPTION_MNAKED_REG:
10587 allow_naked_reg = 1;
10588 break;
10589
10590 case OPTION_MOLD_GCC:
10591 old_gcc = 1;
10592 break;
10593
10594 case OPTION_MSSE2AVX:
10595 sse2avx = 1;
10596 break;
10597
10598 case OPTION_MSSE_CHECK:
10599 if (strcasecmp (arg, "error") == 0)
10600 sse_check = check_error;
10601 else if (strcasecmp (arg, "warning") == 0)
10602 sse_check = check_warning;
10603 else if (strcasecmp (arg, "none") == 0)
10604 sse_check = check_none;
10605 else
10606 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10607 break;
10608
10609 case OPTION_MOPERAND_CHECK:
10610 if (strcasecmp (arg, "error") == 0)
10611 operand_check = check_error;
10612 else if (strcasecmp (arg, "warning") == 0)
10613 operand_check = check_warning;
10614 else if (strcasecmp (arg, "none") == 0)
10615 operand_check = check_none;
10616 else
10617 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10618 break;
10619
10620 case OPTION_MAVXSCALAR:
10621 if (strcasecmp (arg, "128") == 0)
10622 avxscalar = vex128;
10623 else if (strcasecmp (arg, "256") == 0)
10624 avxscalar = vex256;
10625 else
10626 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10627 break;
10628
10629 case OPTION_MADD_BND_PREFIX:
10630 add_bnd_prefix = 1;
10631 break;
10632
10633 case OPTION_MEVEXLIG:
10634 if (strcmp (arg, "128") == 0)
10635 evexlig = evexl128;
10636 else if (strcmp (arg, "256") == 0)
10637 evexlig = evexl256;
10638 else if (strcmp (arg, "512") == 0)
10639 evexlig = evexl512;
10640 else
10641 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10642 break;
10643
10644 case OPTION_MEVEXRCIG:
10645 if (strcmp (arg, "rne") == 0)
10646 evexrcig = rne;
10647 else if (strcmp (arg, "rd") == 0)
10648 evexrcig = rd;
10649 else if (strcmp (arg, "ru") == 0)
10650 evexrcig = ru;
10651 else if (strcmp (arg, "rz") == 0)
10652 evexrcig = rz;
10653 else
10654 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10655 break;
10656
10657 case OPTION_MEVEXWIG:
10658 if (strcmp (arg, "0") == 0)
10659 evexwig = evexw0;
10660 else if (strcmp (arg, "1") == 0)
10661 evexwig = evexw1;
10662 else
10663 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10664 break;
10665
10666 # if defined (TE_PE) || defined (TE_PEP)
10667 case OPTION_MBIG_OBJ:
10668 use_big_obj = 1;
10669 break;
10670 #endif
10671
10672 case OPTION_MOMIT_LOCK_PREFIX:
10673 if (strcasecmp (arg, "yes") == 0)
10674 omit_lock_prefix = 1;
10675 else if (strcasecmp (arg, "no") == 0)
10676 omit_lock_prefix = 0;
10677 else
10678 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10679 break;
10680
10681 case OPTION_MFENCE_AS_LOCK_ADD:
10682 if (strcasecmp (arg, "yes") == 0)
10683 avoid_fence = 1;
10684 else if (strcasecmp (arg, "no") == 0)
10685 avoid_fence = 0;
10686 else
10687 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10688 break;
10689
10690 case OPTION_MRELAX_RELOCATIONS:
10691 if (strcasecmp (arg, "yes") == 0)
10692 generate_relax_relocations = 1;
10693 else if (strcasecmp (arg, "no") == 0)
10694 generate_relax_relocations = 0;
10695 else
10696 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10697 break;
10698
10699 case OPTION_MAMD64:
10700 intel64 = 0;
10701 break;
10702
10703 case OPTION_MINTEL64:
10704 intel64 = 1;
10705 break;
10706
10707 case 'O':
10708 if (arg == NULL)
10709 {
10710 optimize = 1;
10711 /* Turn off -Os. */
10712 optimize_for_space = 0;
10713 }
10714 else if (*arg == 's')
10715 {
10716 optimize_for_space = 1;
10717 /* Turn on all encoding optimizations. */
10718 optimize = -1;
10719 }
10720 else
10721 {
10722 optimize = atoi (arg);
10723 /* Turn off -Os. */
10724 optimize_for_space = 0;
10725 }
10726 break;
10727
10728 default:
10729 return 0;
10730 }
10731 return 1;
10732 }
10733
10734 #define MESSAGE_TEMPLATE \
10735 " "
10736
10737 static char *
10738 output_message (FILE *stream, char *p, char *message, char *start,
10739 int *left_p, const char *name, int len)
10740 {
10741 int size = sizeof (MESSAGE_TEMPLATE);
10742 int left = *left_p;
10743
10744 /* Reserve 2 spaces for ", " or ",\0" */
10745 left -= len + 2;
10746
10747 /* Check if there is any room. */
10748 if (left >= 0)
10749 {
10750 if (p != start)
10751 {
10752 *p++ = ',';
10753 *p++ = ' ';
10754 }
10755 p = mempcpy (p, name, len);
10756 }
10757 else
10758 {
10759 /* Output the current message now and start a new one. */
10760 *p++ = ',';
10761 *p = '\0';
10762 fprintf (stream, "%s\n", message);
10763 p = start;
10764 left = size - (start - message) - len - 2;
10765
10766 gas_assert (left >= 0);
10767
10768 p = mempcpy (p, name, len);
10769 }
10770
10771 *left_p = left;
10772 return p;
10773 }
10774
10775 static void
10776 show_arch (FILE *stream, int ext, int check)
10777 {
10778 static char message[] = MESSAGE_TEMPLATE;
10779 char *start = message + 27;
10780 char *p;
10781 int size = sizeof (MESSAGE_TEMPLATE);
10782 int left;
10783 const char *name;
10784 int len;
10785 unsigned int j;
10786
10787 p = start;
10788 left = size - (start - message);
10789 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10790 {
10791 /* Should it be skipped? */
10792 if (cpu_arch [j].skip)
10793 continue;
10794
10795 name = cpu_arch [j].name;
10796 len = cpu_arch [j].len;
10797 if (*name == '.')
10798 {
10799 /* It is an extension. Skip if we aren't asked to show it. */
10800 if (ext)
10801 {
10802 name++;
10803 len--;
10804 }
10805 else
10806 continue;
10807 }
10808 else if (ext)
10809 {
10810 /* It is an processor. Skip if we show only extension. */
10811 continue;
10812 }
10813 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10814 {
10815 /* It is an impossible processor - skip. */
10816 continue;
10817 }
10818
10819 p = output_message (stream, p, message, start, &left, name, len);
10820 }
10821
10822 /* Display disabled extensions. */
10823 if (ext)
10824 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10825 {
10826 name = cpu_noarch [j].name;
10827 len = cpu_noarch [j].len;
10828 p = output_message (stream, p, message, start, &left, name,
10829 len);
10830 }
10831
10832 *p = '\0';
10833 fprintf (stream, "%s\n", message);
10834 }
10835
10836 void
10837 md_show_usage (FILE *stream)
10838 {
10839 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10840 fprintf (stream, _("\
10841 -Q ignored\n\
10842 -V print assembler version number\n\
10843 -k ignored\n"));
10844 #endif
10845 fprintf (stream, _("\
10846 -n Do not optimize code alignment\n\
10847 -q quieten some warnings\n"));
10848 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10849 fprintf (stream, _("\
10850 -s ignored\n"));
10851 #endif
10852 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10853 || defined (TE_PE) || defined (TE_PEP))
10854 fprintf (stream, _("\
10855 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10856 #endif
10857 #ifdef SVR4_COMMENT_CHARS
10858 fprintf (stream, _("\
10859 --divide do not treat `/' as a comment character\n"));
10860 #else
10861 fprintf (stream, _("\
10862 --divide ignored\n"));
10863 #endif
10864 fprintf (stream, _("\
10865 -march=CPU[,+EXTENSION...]\n\
10866 generate code for CPU and EXTENSION, CPU is one of:\n"));
10867 show_arch (stream, 0, 1);
10868 fprintf (stream, _("\
10869 EXTENSION is combination of:\n"));
10870 show_arch (stream, 1, 0);
10871 fprintf (stream, _("\
10872 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10873 show_arch (stream, 0, 0);
10874 fprintf (stream, _("\
10875 -msse2avx encode SSE instructions with VEX prefix\n"));
10876 fprintf (stream, _("\
10877 -msse-check=[none|error|warning]\n\
10878 check SSE instructions\n"));
10879 fprintf (stream, _("\
10880 -moperand-check=[none|error|warning]\n\
10881 check operand combinations for validity\n"));
10882 fprintf (stream, _("\
10883 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10884 length\n"));
10885 fprintf (stream, _("\
10886 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10887 length\n"));
10888 fprintf (stream, _("\
10889 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10890 for EVEX.W bit ignored instructions\n"));
10891 fprintf (stream, _("\
10892 -mevexrcig=[rne|rd|ru|rz]\n\
10893 encode EVEX instructions with specific EVEX.RC value\n\
10894 for SAE-only ignored instructions\n"));
10895 fprintf (stream, _("\
10896 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10897 fprintf (stream, _("\
10898 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10899 fprintf (stream, _("\
10900 -mindex-reg support pseudo index registers\n"));
10901 fprintf (stream, _("\
10902 -mnaked-reg don't require `%%' prefix for registers\n"));
10903 fprintf (stream, _("\
10904 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10905 fprintf (stream, _("\
10906 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10907 fprintf (stream, _("\
10908 -mshared disable branch optimization for shared code\n"));
10909 # if defined (TE_PE) || defined (TE_PEP)
10910 fprintf (stream, _("\
10911 -mbig-obj generate big object files\n"));
10912 #endif
10913 fprintf (stream, _("\
10914 -momit-lock-prefix=[no|yes]\n\
10915 strip all lock prefixes\n"));
10916 fprintf (stream, _("\
10917 -mfence-as-lock-add=[no|yes]\n\
10918 encode lfence, mfence and sfence as\n\
10919 lock addl $0x0, (%%{re}sp)\n"));
10920 fprintf (stream, _("\
10921 -mrelax-relocations=[no|yes]\n\
10922 generate relax relocations\n"));
10923 fprintf (stream, _("\
10924 -mamd64 accept only AMD64 ISA\n"));
10925 fprintf (stream, _("\
10926 -mintel64 accept only Intel64 ISA\n"));
10927 }
10928
10929 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10930 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10931 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10932
10933 /* Pick the target format to use. */
10934
10935 const char *
10936 i386_target_format (void)
10937 {
10938 if (!strncmp (default_arch, "x86_64", 6))
10939 {
10940 update_code_flag (CODE_64BIT, 1);
10941 if (default_arch[6] == '\0')
10942 x86_elf_abi = X86_64_ABI;
10943 else
10944 x86_elf_abi = X86_64_X32_ABI;
10945 }
10946 else if (!strcmp (default_arch, "i386"))
10947 update_code_flag (CODE_32BIT, 1);
10948 else if (!strcmp (default_arch, "iamcu"))
10949 {
10950 update_code_flag (CODE_32BIT, 1);
10951 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10952 {
10953 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10954 cpu_arch_name = "iamcu";
10955 cpu_sub_arch_name = NULL;
10956 cpu_arch_flags = iamcu_flags;
10957 cpu_arch_isa = PROCESSOR_IAMCU;
10958 cpu_arch_isa_flags = iamcu_flags;
10959 if (!cpu_arch_tune_set)
10960 {
10961 cpu_arch_tune = cpu_arch_isa;
10962 cpu_arch_tune_flags = cpu_arch_isa_flags;
10963 }
10964 }
10965 else if (cpu_arch_isa != PROCESSOR_IAMCU)
10966 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10967 cpu_arch_name);
10968 }
10969 else
10970 as_fatal (_("unknown architecture"));
10971
10972 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10973 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10974 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10975 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10976
10977 switch (OUTPUT_FLAVOR)
10978 {
10979 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10980 case bfd_target_aout_flavour:
10981 return AOUT_TARGET_FORMAT;
10982 #endif
10983 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10984 # if defined (TE_PE) || defined (TE_PEP)
10985 case bfd_target_coff_flavour:
10986 if (flag_code == CODE_64BIT)
10987 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10988 else
10989 return "pe-i386";
10990 # elif defined (TE_GO32)
10991 case bfd_target_coff_flavour:
10992 return "coff-go32";
10993 # else
10994 case bfd_target_coff_flavour:
10995 return "coff-i386";
10996 # endif
10997 #endif
10998 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10999 case bfd_target_elf_flavour:
11000 {
11001 const char *format;
11002
11003 switch (x86_elf_abi)
11004 {
11005 default:
11006 format = ELF_TARGET_FORMAT;
11007 break;
11008 case X86_64_ABI:
11009 use_rela_relocations = 1;
11010 object_64bit = 1;
11011 format = ELF_TARGET_FORMAT64;
11012 break;
11013 case X86_64_X32_ABI:
11014 use_rela_relocations = 1;
11015 object_64bit = 1;
11016 disallow_64bit_reloc = 1;
11017 format = ELF_TARGET_FORMAT32;
11018 break;
11019 }
11020 if (cpu_arch_isa == PROCESSOR_L1OM)
11021 {
11022 if (x86_elf_abi != X86_64_ABI)
11023 as_fatal (_("Intel L1OM is 64bit only"));
11024 return ELF_TARGET_L1OM_FORMAT;
11025 }
11026 else if (cpu_arch_isa == PROCESSOR_K1OM)
11027 {
11028 if (x86_elf_abi != X86_64_ABI)
11029 as_fatal (_("Intel K1OM is 64bit only"));
11030 return ELF_TARGET_K1OM_FORMAT;
11031 }
11032 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11033 {
11034 if (x86_elf_abi != I386_ABI)
11035 as_fatal (_("Intel MCU is 32bit only"));
11036 return ELF_TARGET_IAMCU_FORMAT;
11037 }
11038 else
11039 return format;
11040 }
11041 #endif
11042 #if defined (OBJ_MACH_O)
11043 case bfd_target_mach_o_flavour:
11044 if (flag_code == CODE_64BIT)
11045 {
11046 use_rela_relocations = 1;
11047 object_64bit = 1;
11048 return "mach-o-x86-64";
11049 }
11050 else
11051 return "mach-o-i386";
11052 #endif
11053 default:
11054 abort ();
11055 return NULL;
11056 }
11057 }
11058
11059 #endif /* OBJ_MAYBE_ more than one */
11060 \f
11061 symbolS *
11062 md_undefined_symbol (char *name)
11063 {
11064 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11065 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11066 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11067 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11068 {
11069 if (!GOT_symbol)
11070 {
11071 if (symbol_find (name))
11072 as_bad (_("GOT already in symbol table"));
11073 GOT_symbol = symbol_new (name, undefined_section,
11074 (valueT) 0, &zero_address_frag);
11075 };
11076 return GOT_symbol;
11077 }
11078 return 0;
11079 }
11080
11081 /* Round up a section size to the appropriate boundary. */
11082
11083 valueT
11084 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11085 {
11086 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11087 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11088 {
11089 /* For a.out, force the section size to be aligned. If we don't do
11090 this, BFD will align it for us, but it will not write out the
11091 final bytes of the section. This may be a bug in BFD, but it is
11092 easier to fix it here since that is how the other a.out targets
11093 work. */
11094 int align;
11095
11096 align = bfd_get_section_alignment (stdoutput, segment);
11097 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11098 }
11099 #endif
11100
11101 return size;
11102 }
11103
11104 /* On the i386, PC-relative offsets are relative to the start of the
11105 next instruction. That is, the address of the offset, plus its
11106 size, since the offset is always the last part of the insn. */
11107
11108 long
11109 md_pcrel_from (fixS *fixP)
11110 {
11111 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11112 }
11113
11114 #ifndef I386COFF
11115
11116 static void
11117 s_bss (int ignore ATTRIBUTE_UNUSED)
11118 {
11119 int temp;
11120
11121 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11122 if (IS_ELF)
11123 obj_elf_section_change_hook ();
11124 #endif
11125 temp = get_absolute_expression ();
11126 subseg_set (bss_section, (subsegT) temp);
11127 demand_empty_rest_of_line ();
11128 }
11129
11130 #endif
11131
11132 void
11133 i386_validate_fix (fixS *fixp)
11134 {
11135 if (fixp->fx_subsy)
11136 {
11137 if (fixp->fx_subsy == GOT_symbol)
11138 {
11139 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11140 {
11141 if (!object_64bit)
11142 abort ();
11143 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11144 if (fixp->fx_tcbit2)
11145 fixp->fx_r_type = (fixp->fx_tcbit
11146 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11147 : BFD_RELOC_X86_64_GOTPCRELX);
11148 else
11149 #endif
11150 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11151 }
11152 else
11153 {
11154 if (!object_64bit)
11155 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11156 else
11157 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11158 }
11159 fixp->fx_subsy = 0;
11160 }
11161 }
11162 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11163 else if (!object_64bit)
11164 {
11165 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11166 && fixp->fx_tcbit2)
11167 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11168 }
11169 #endif
11170 }
11171
11172 arelent *
11173 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
11174 {
11175 arelent *rel;
11176 bfd_reloc_code_real_type code;
11177
11178 switch (fixp->fx_r_type)
11179 {
11180 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11181 case BFD_RELOC_SIZE32:
11182 case BFD_RELOC_SIZE64:
11183 if (S_IS_DEFINED (fixp->fx_addsy)
11184 && !S_IS_EXTERNAL (fixp->fx_addsy))
11185 {
11186 /* Resolve size relocation against local symbol to size of
11187 the symbol plus addend. */
11188 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11189 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11190 && !fits_in_unsigned_long (value))
11191 as_bad_where (fixp->fx_file, fixp->fx_line,
11192 _("symbol size computation overflow"));
11193 fixp->fx_addsy = NULL;
11194 fixp->fx_subsy = NULL;
11195 md_apply_fix (fixp, (valueT *) &value, NULL);
11196 return NULL;
11197 }
11198 #endif
11199 /* Fall through. */
11200
11201 case BFD_RELOC_X86_64_PLT32:
11202 case BFD_RELOC_X86_64_GOT32:
11203 case BFD_RELOC_X86_64_GOTPCREL:
11204 case BFD_RELOC_X86_64_GOTPCRELX:
11205 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11206 case BFD_RELOC_386_PLT32:
11207 case BFD_RELOC_386_GOT32:
11208 case BFD_RELOC_386_GOT32X:
11209 case BFD_RELOC_386_GOTOFF:
11210 case BFD_RELOC_386_GOTPC:
11211 case BFD_RELOC_386_TLS_GD:
11212 case BFD_RELOC_386_TLS_LDM:
11213 case BFD_RELOC_386_TLS_LDO_32:
11214 case BFD_RELOC_386_TLS_IE_32:
11215 case BFD_RELOC_386_TLS_IE:
11216 case BFD_RELOC_386_TLS_GOTIE:
11217 case BFD_RELOC_386_TLS_LE_32:
11218 case BFD_RELOC_386_TLS_LE:
11219 case BFD_RELOC_386_TLS_GOTDESC:
11220 case BFD_RELOC_386_TLS_DESC_CALL:
11221 case BFD_RELOC_X86_64_TLSGD:
11222 case BFD_RELOC_X86_64_TLSLD:
11223 case BFD_RELOC_X86_64_DTPOFF32:
11224 case BFD_RELOC_X86_64_DTPOFF64:
11225 case BFD_RELOC_X86_64_GOTTPOFF:
11226 case BFD_RELOC_X86_64_TPOFF32:
11227 case BFD_RELOC_X86_64_TPOFF64:
11228 case BFD_RELOC_X86_64_GOTOFF64:
11229 case BFD_RELOC_X86_64_GOTPC32:
11230 case BFD_RELOC_X86_64_GOT64:
11231 case BFD_RELOC_X86_64_GOTPCREL64:
11232 case BFD_RELOC_X86_64_GOTPC64:
11233 case BFD_RELOC_X86_64_GOTPLT64:
11234 case BFD_RELOC_X86_64_PLTOFF64:
11235 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11236 case BFD_RELOC_X86_64_TLSDESC_CALL:
11237 case BFD_RELOC_RVA:
11238 case BFD_RELOC_VTABLE_ENTRY:
11239 case BFD_RELOC_VTABLE_INHERIT:
11240 #ifdef TE_PE
11241 case BFD_RELOC_32_SECREL:
11242 #endif
11243 code = fixp->fx_r_type;
11244 break;
11245 case BFD_RELOC_X86_64_32S:
11246 if (!fixp->fx_pcrel)
11247 {
11248 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11249 code = fixp->fx_r_type;
11250 break;
11251 }
11252 /* Fall through. */
11253 default:
11254 if (fixp->fx_pcrel)
11255 {
11256 switch (fixp->fx_size)
11257 {
11258 default:
11259 as_bad_where (fixp->fx_file, fixp->fx_line,
11260 _("can not do %d byte pc-relative relocation"),
11261 fixp->fx_size);
11262 code = BFD_RELOC_32_PCREL;
11263 break;
11264 case 1: code = BFD_RELOC_8_PCREL; break;
11265 case 2: code = BFD_RELOC_16_PCREL; break;
11266 case 4: code = BFD_RELOC_32_PCREL; break;
11267 #ifdef BFD64
11268 case 8: code = BFD_RELOC_64_PCREL; break;
11269 #endif
11270 }
11271 }
11272 else
11273 {
11274 switch (fixp->fx_size)
11275 {
11276 default:
11277 as_bad_where (fixp->fx_file, fixp->fx_line,
11278 _("can not do %d byte relocation"),
11279 fixp->fx_size);
11280 code = BFD_RELOC_32;
11281 break;
11282 case 1: code = BFD_RELOC_8; break;
11283 case 2: code = BFD_RELOC_16; break;
11284 case 4: code = BFD_RELOC_32; break;
11285 #ifdef BFD64
11286 case 8: code = BFD_RELOC_64; break;
11287 #endif
11288 }
11289 }
11290 break;
11291 }
11292
11293 if ((code == BFD_RELOC_32
11294 || code == BFD_RELOC_32_PCREL
11295 || code == BFD_RELOC_X86_64_32S)
11296 && GOT_symbol
11297 && fixp->fx_addsy == GOT_symbol)
11298 {
11299 if (!object_64bit)
11300 code = BFD_RELOC_386_GOTPC;
11301 else
11302 code = BFD_RELOC_X86_64_GOTPC32;
11303 }
11304 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11305 && GOT_symbol
11306 && fixp->fx_addsy == GOT_symbol)
11307 {
11308 code = BFD_RELOC_X86_64_GOTPC64;
11309 }
11310
11311 rel = XNEW (arelent);
11312 rel->sym_ptr_ptr = XNEW (asymbol *);
11313 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11314
11315 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11316
11317 if (!use_rela_relocations)
11318 {
11319 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11320 vtable entry to be used in the relocation's section offset. */
11321 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11322 rel->address = fixp->fx_offset;
11323 #if defined (OBJ_COFF) && defined (TE_PE)
11324 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11325 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11326 else
11327 #endif
11328 rel->addend = 0;
11329 }
11330 /* Use the rela in 64bit mode. */
11331 else
11332 {
11333 if (disallow_64bit_reloc)
11334 switch (code)
11335 {
11336 case BFD_RELOC_X86_64_DTPOFF64:
11337 case BFD_RELOC_X86_64_TPOFF64:
11338 case BFD_RELOC_64_PCREL:
11339 case BFD_RELOC_X86_64_GOTOFF64:
11340 case BFD_RELOC_X86_64_GOT64:
11341 case BFD_RELOC_X86_64_GOTPCREL64:
11342 case BFD_RELOC_X86_64_GOTPC64:
11343 case BFD_RELOC_X86_64_GOTPLT64:
11344 case BFD_RELOC_X86_64_PLTOFF64:
11345 as_bad_where (fixp->fx_file, fixp->fx_line,
11346 _("cannot represent relocation type %s in x32 mode"),
11347 bfd_get_reloc_code_name (code));
11348 break;
11349 default:
11350 break;
11351 }
11352
11353 if (!fixp->fx_pcrel)
11354 rel->addend = fixp->fx_offset;
11355 else
11356 switch (code)
11357 {
11358 case BFD_RELOC_X86_64_PLT32:
11359 case BFD_RELOC_X86_64_GOT32:
11360 case BFD_RELOC_X86_64_GOTPCREL:
11361 case BFD_RELOC_X86_64_GOTPCRELX:
11362 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11363 case BFD_RELOC_X86_64_TLSGD:
11364 case BFD_RELOC_X86_64_TLSLD:
11365 case BFD_RELOC_X86_64_GOTTPOFF:
11366 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11367 case BFD_RELOC_X86_64_TLSDESC_CALL:
11368 rel->addend = fixp->fx_offset - fixp->fx_size;
11369 break;
11370 default:
11371 rel->addend = (section->vma
11372 - fixp->fx_size
11373 + fixp->fx_addnumber
11374 + md_pcrel_from (fixp));
11375 break;
11376 }
11377 }
11378
11379 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11380 if (rel->howto == NULL)
11381 {
11382 as_bad_where (fixp->fx_file, fixp->fx_line,
11383 _("cannot represent relocation type %s"),
11384 bfd_get_reloc_code_name (code));
11385 /* Set howto to a garbage value so that we can keep going. */
11386 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11387 gas_assert (rel->howto != NULL);
11388 }
11389
11390 return rel;
11391 }
11392
11393 #include "tc-i386-intel.c"
11394
11395 void
11396 tc_x86_parse_to_dw2regnum (expressionS *exp)
11397 {
11398 int saved_naked_reg;
11399 char saved_register_dot;
11400
11401 saved_naked_reg = allow_naked_reg;
11402 allow_naked_reg = 1;
11403 saved_register_dot = register_chars['.'];
11404 register_chars['.'] = '.';
11405 allow_pseudo_reg = 1;
11406 expression_and_evaluate (exp);
11407 allow_pseudo_reg = 0;
11408 register_chars['.'] = saved_register_dot;
11409 allow_naked_reg = saved_naked_reg;
11410
11411 if (exp->X_op == O_register && exp->X_add_number >= 0)
11412 {
11413 if ((addressT) exp->X_add_number < i386_regtab_size)
11414 {
11415 exp->X_op = O_constant;
11416 exp->X_add_number = i386_regtab[exp->X_add_number]
11417 .dw2_regnum[flag_code >> 1];
11418 }
11419 else
11420 exp->X_op = O_illegal;
11421 }
11422 }
11423
11424 void
11425 tc_x86_frame_initial_instructions (void)
11426 {
11427 static unsigned int sp_regno[2];
11428
11429 if (!sp_regno[flag_code >> 1])
11430 {
11431 char *saved_input = input_line_pointer;
11432 char sp[][4] = {"esp", "rsp"};
11433 expressionS exp;
11434
11435 input_line_pointer = sp[flag_code >> 1];
11436 tc_x86_parse_to_dw2regnum (&exp);
11437 gas_assert (exp.X_op == O_constant);
11438 sp_regno[flag_code >> 1] = exp.X_add_number;
11439 input_line_pointer = saved_input;
11440 }
11441
11442 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11443 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11444 }
11445
11446 int
11447 x86_dwarf2_addr_size (void)
11448 {
11449 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11450 if (x86_elf_abi == X86_64_X32_ABI)
11451 return 4;
11452 #endif
11453 return bfd_arch_bits_per_address (stdoutput) / 8;
11454 }
11455
11456 int
11457 i386_elf_section_type (const char *str, size_t len)
11458 {
11459 if (flag_code == CODE_64BIT
11460 && len == sizeof ("unwind") - 1
11461 && strncmp (str, "unwind", 6) == 0)
11462 return SHT_X86_64_UNWIND;
11463
11464 return -1;
11465 }
11466
11467 #ifdef TE_SOLARIS
11468 void
11469 i386_solaris_fix_up_eh_frame (segT sec)
11470 {
11471 if (flag_code == CODE_64BIT)
11472 elf_section_type (sec) = SHT_X86_64_UNWIND;
11473 }
11474 #endif
11475
11476 #ifdef TE_PE
11477 void
11478 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11479 {
11480 expressionS exp;
11481
11482 exp.X_op = O_secrel;
11483 exp.X_add_symbol = symbol;
11484 exp.X_add_number = 0;
11485 emit_expr (&exp, size);
11486 }
11487 #endif
11488
11489 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11490 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11491
11492 bfd_vma
11493 x86_64_section_letter (int letter, const char **ptr_msg)
11494 {
11495 if (flag_code == CODE_64BIT)
11496 {
11497 if (letter == 'l')
11498 return SHF_X86_64_LARGE;
11499
11500 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11501 }
11502 else
11503 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11504 return -1;
11505 }
11506
11507 bfd_vma
11508 x86_64_section_word (char *str, size_t len)
11509 {
11510 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11511 return SHF_X86_64_LARGE;
11512
11513 return -1;
11514 }
11515
11516 static void
11517 handle_large_common (int small ATTRIBUTE_UNUSED)
11518 {
11519 if (flag_code != CODE_64BIT)
11520 {
11521 s_comm_internal (0, elf_common_parse);
11522 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11523 }
11524 else
11525 {
11526 static segT lbss_section;
11527 asection *saved_com_section_ptr = elf_com_section_ptr;
11528 asection *saved_bss_section = bss_section;
11529
11530 if (lbss_section == NULL)
11531 {
11532 flagword applicable;
11533 segT seg = now_seg;
11534 subsegT subseg = now_subseg;
11535
11536 /* The .lbss section is for local .largecomm symbols. */
11537 lbss_section = subseg_new (".lbss", 0);
11538 applicable = bfd_applicable_section_flags (stdoutput);
11539 bfd_set_section_flags (stdoutput, lbss_section,
11540 applicable & SEC_ALLOC);
11541 seg_info (lbss_section)->bss = 1;
11542
11543 subseg_set (seg, subseg);
11544 }
11545
11546 elf_com_section_ptr = &_bfd_elf_large_com_section;
11547 bss_section = lbss_section;
11548
11549 s_comm_internal (0, elf_common_parse);
11550
11551 elf_com_section_ptr = saved_com_section_ptr;
11552 bss_section = saved_bss_section;
11553 }
11554 }
11555 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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