1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
5 Free Software Foundation, Inc.
7 This file is part of GAS, the GNU Assembler.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
21 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 /* Intel 80386 machine specific gas.
25 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
26 x86_64 support by Jan Hubicka (jh@suse.cz)
27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
28 Bugs & suggestions are completely welcome. This is free software.
29 Please help us make it better. */
32 #include "safe-ctype.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
36 #include "elf/x86-64.h"
37 #include "opcodes/i386-init.h"
39 #ifndef REGISTER_WARNINGS
40 #define REGISTER_WARNINGS 1
43 #ifndef INFER_ADDR_PREFIX
44 #define INFER_ADDR_PREFIX 1
48 #define DEFAULT_ARCH "i386"
53 #define INLINE __inline__
59 /* Prefixes will be emitted in the order defined below.
60 WAIT_PREFIX must be the first prefix since FWAIT is really is an
61 instruction, and so must come before any prefixes.
62 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
63 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
69 #define HLE_PREFIX REP_PREFIX
70 #define BND_PREFIX REP_PREFIX
72 #define REX_PREFIX 6 /* must come last. */
73 #define MAX_PREFIXES 7 /* max prefixes per opcode */
75 /* we define the syntax here (modulo base,index,scale syntax) */
76 #define REGISTER_PREFIX '%'
77 #define IMMEDIATE_PREFIX '$'
78 #define ABSOLUTE_PREFIX '*'
80 /* these are the instruction mnemonic suffixes in AT&T syntax or
81 memory operand size in Intel syntax. */
82 #define WORD_MNEM_SUFFIX 'w'
83 #define BYTE_MNEM_SUFFIX 'b'
84 #define SHORT_MNEM_SUFFIX 's'
85 #define LONG_MNEM_SUFFIX 'l'
86 #define QWORD_MNEM_SUFFIX 'q'
87 #define XMMWORD_MNEM_SUFFIX 'x'
88 #define YMMWORD_MNEM_SUFFIX 'y'
89 #define ZMMWORD_MNEM_SUFFIX 'z'
90 /* Intel Syntax. Use a non-ascii letter since since it never appears
92 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
94 #define END_OF_INSN '\0'
97 'templates' is for grouping together 'template' structures for opcodes
98 of the same name. This is only used for storing the insns in the grand
99 ole hash table of insns.
100 The templates themselves start at START and range up to (but not including)
105 const insn_template
*start
;
106 const insn_template
*end
;
110 /* 386 operand encoding bytes: see 386 book for details of this. */
113 unsigned int regmem
; /* codes register or memory operand */
114 unsigned int reg
; /* codes register operand (or extended opcode) */
115 unsigned int mode
; /* how to interpret regmem & reg */
119 /* x86-64 extension prefix. */
120 typedef int rex_byte
;
122 /* 386 opcode byte to code indirect addressing. */
131 /* x86 arch names, types and features */
134 const char *name
; /* arch name */
135 unsigned int len
; /* arch string length */
136 enum processor_type type
; /* arch type */
137 i386_cpu_flags flags
; /* cpu feature flags */
138 unsigned int skip
; /* show_arch should skip this. */
139 unsigned int negated
; /* turn off indicated flags. */
143 static void update_code_flag (int, int);
144 static void set_code_flag (int);
145 static void set_16bit_gcc_code_flag (int);
146 static void set_intel_syntax (int);
147 static void set_intel_mnemonic (int);
148 static void set_allow_index_reg (int);
149 static void set_check (int);
150 static void set_cpu_arch (int);
152 static void pe_directive_secrel (int);
154 static void signed_cons (int);
155 static char *output_invalid (int c
);
156 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
158 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
160 static int i386_att_operand (char *);
161 static int i386_intel_operand (char *, int);
162 static int i386_intel_simplify (expressionS
*);
163 static int i386_intel_parse_name (const char *, expressionS
*);
164 static const reg_entry
*parse_register (char *, char **);
165 static char *parse_insn (char *, char *);
166 static char *parse_operands (char *, const char *);
167 static void swap_operands (void);
168 static void swap_2_operands (int, int);
169 static void optimize_imm (void);
170 static void optimize_disp (void);
171 static const insn_template
*match_template (void);
172 static int check_string (void);
173 static int process_suffix (void);
174 static int check_byte_reg (void);
175 static int check_long_reg (void);
176 static int check_qword_reg (void);
177 static int check_word_reg (void);
178 static int finalize_imm (void);
179 static int process_operands (void);
180 static const seg_entry
*build_modrm_byte (void);
181 static void output_insn (void);
182 static void output_imm (fragS
*, offsetT
);
183 static void output_disp (fragS
*, offsetT
);
185 static void s_bss (int);
187 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
188 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
191 static const char *default_arch
= DEFAULT_ARCH
;
193 /* This struct describes rounding control and SAE in the instruction. */
207 static struct RC_Operation rc_op
;
209 /* The struct describes masking, applied to OPERAND in the instruction.
210 MASK is a pointer to the corresponding mask register. ZEROING tells
211 whether merging or zeroing mask is used. */
212 struct Mask_Operation
214 const reg_entry
*mask
;
215 unsigned int zeroing
;
216 /* The operand where this operation is associated. */
220 static struct Mask_Operation mask_op
;
222 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
224 struct Broadcast_Operation
226 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
229 /* Index of broadcasted operand. */
233 static struct Broadcast_Operation broadcast_op
;
238 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
239 unsigned char bytes
[4];
241 /* Destination or source register specifier. */
242 const reg_entry
*register_specifier
;
245 /* 'md_assemble ()' gathers together information and puts it into a
252 const reg_entry
*regs
;
257 operand_size_mismatch
,
258 operand_type_mismatch
,
259 register_type_mismatch
,
260 number_of_operands_mismatch
,
261 invalid_instruction_suffix
,
264 unsupported_with_intel_mnemonic
,
267 invalid_vsib_address
,
268 invalid_vector_register_set
,
269 unsupported_vector_index_register
,
270 unsupported_broadcast
,
271 broadcast_not_on_src_operand
,
274 mask_not_on_destination
,
277 rc_sae_operand_not_last_imm
,
278 invalid_register_operand
,
284 /* TM holds the template for the insn were currently assembling. */
287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
291 /* OPERANDS gives the number of given operands. */
292 unsigned int operands
;
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
297 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
299 /* TYPES [i] is the type (see above #defines) which tells us how to
300 use OP[i] for the corresponding operand. */
301 i386_operand_type types
[MAX_OPERANDS
];
303 /* Displacement expression, immediate expression, or register for each
305 union i386_op op
[MAX_OPERANDS
];
307 /* Flags for operands. */
308 unsigned int flags
[MAX_OPERANDS
];
309 #define Operand_PCrel 1
311 /* Relocation type for operand */
312 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry
*base_reg
;
317 const reg_entry
*index_reg
;
318 unsigned int log2_scale_factor
;
320 /* SEG gives the seg_entries of this insn. They are zero unless
321 explicit segment overrides are given. */
322 const seg_entry
*seg
[2];
324 /* PREFIX holds all the given prefix opcodes (usually null).
325 PREFIXES is the number of prefix opcodes. */
326 unsigned int prefixes
;
327 unsigned char prefix
[MAX_PREFIXES
];
329 /* RM and SIB are the modrm byte and the sib byte where the
330 addressing modes of this insn are encoded. */
337 /* Masking attributes. */
338 struct Mask_Operation
*mask
;
340 /* Rounding control and SAE attributes. */
341 struct RC_Operation
*rounding
;
343 /* Broadcasting attributes. */
344 struct Broadcast_Operation
*broadcast
;
346 /* Compressed disp8*N attribute. */
347 unsigned int memshift
;
349 /* Swap operand in encoding. */
350 unsigned int swap_operand
;
352 /* Prefer 8bit or 32bit displacement in encoding. */
355 disp_encoding_default
= 0,
361 const char *rep_prefix
;
364 const char *hle_prefix
;
366 /* Have BND prefix. */
367 const char *bnd_prefix
;
369 /* Need VREX to support upper 16 registers. */
373 enum i386_error error
;
376 typedef struct _i386_insn i386_insn
;
378 /* Link RC type with corresponding string, that'll be looked for in
387 static const struct RC_name RC_NamesTable
[] =
389 { rne
, STRING_COMMA_LEN ("rn-sae") },
390 { rd
, STRING_COMMA_LEN ("rd-sae") },
391 { ru
, STRING_COMMA_LEN ("ru-sae") },
392 { rz
, STRING_COMMA_LEN ("rz-sae") },
393 { saeonly
, STRING_COMMA_LEN ("sae") },
396 /* List of chars besides those in app.c:symbol_chars that can start an
397 operand. Used to prevent the scrubber eating vital white-space. */
398 const char extra_symbol_chars
[] = "*%-([{"
407 #if (defined (TE_I386AIX) \
408 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
409 && !defined (TE_GNU) \
410 && !defined (TE_LINUX) \
411 && !defined (TE_NACL) \
412 && !defined (TE_NETWARE) \
413 && !defined (TE_FreeBSD) \
414 && !defined (TE_DragonFly) \
415 && !defined (TE_NetBSD)))
416 /* This array holds the chars that always start a comment. If the
417 pre-processor is disabled, these aren't very useful. The option
418 --divide will remove '/' from this list. */
419 const char *i386_comment_chars
= "#/";
420 #define SVR4_COMMENT_CHARS 1
421 #define PREFIX_SEPARATOR '\\'
424 const char *i386_comment_chars
= "#";
425 #define PREFIX_SEPARATOR '/'
428 /* This array holds the chars that only start a comment at the beginning of
429 a line. If the line seems to have the form '# 123 filename'
430 .line and .file directives will appear in the pre-processed output.
431 Note that input_file.c hand checks for '#' at the beginning of the
432 first line of the input file. This is because the compiler outputs
433 #NO_APP at the beginning of its output.
434 Also note that comments started like this one will always work if
435 '/' isn't otherwise defined. */
436 const char line_comment_chars
[] = "#/";
438 const char line_separator_chars
[] = ";";
440 /* Chars that can be used to separate mant from exp in floating point
442 const char EXP_CHARS
[] = "eE";
444 /* Chars that mean this number is a floating point constant
447 const char FLT_CHARS
[] = "fFdDxX";
449 /* Tables for lexical analysis. */
450 static char mnemonic_chars
[256];
451 static char register_chars
[256];
452 static char operand_chars
[256];
453 static char identifier_chars
[256];
454 static char digit_chars
[256];
456 /* Lexical macros. */
457 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
458 #define is_operand_char(x) (operand_chars[(unsigned char) x])
459 #define is_register_char(x) (register_chars[(unsigned char) x])
460 #define is_space_char(x) ((x) == ' ')
461 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
462 #define is_digit_char(x) (digit_chars[(unsigned char) x])
464 /* All non-digit non-letter characters that may occur in an operand. */
465 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
467 /* md_assemble() always leaves the strings it's passed unaltered. To
468 effect this we maintain a stack of saved characters that we've smashed
469 with '\0's (indicating end of strings for various sub-fields of the
470 assembler instruction). */
471 static char save_stack
[32];
472 static char *save_stack_p
;
473 #define END_STRING_AND_SAVE(s) \
474 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
475 #define RESTORE_END_STRING(s) \
476 do { *(s) = *--save_stack_p; } while (0)
478 /* The instruction we're assembling. */
481 /* Possible templates for current insn. */
482 static const templates
*current_templates
;
484 /* Per instruction expressionS buffers: max displacements & immediates. */
485 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
486 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
488 /* Current operand we are working on. */
489 static int this_operand
= -1;
491 /* We support four different modes. FLAG_CODE variable is used to distinguish
499 static enum flag_code flag_code
;
500 static unsigned int object_64bit
;
501 static unsigned int disallow_64bit_reloc
;
502 static int use_rela_relocations
= 0;
504 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
505 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
506 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
508 /* The ELF ABI to use. */
516 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
519 /* 1 for intel syntax,
521 static int intel_syntax
= 0;
523 /* 1 for intel mnemonic,
524 0 if att mnemonic. */
525 static int intel_mnemonic
= !SYSV386_COMPAT
;
527 /* 1 if support old (<= 2.8.1) versions of gcc. */
528 static int old_gcc
= OLDGCC_COMPAT
;
530 /* 1 if pseudo registers are permitted. */
531 static int allow_pseudo_reg
= 0;
533 /* 1 if register prefix % not required. */
534 static int allow_naked_reg
= 0;
536 /* 1 if the assembler should add BND prefix for all control-tranferring
537 instructions supporting it, even if this prefix wasn't specified
539 static int add_bnd_prefix
= 0;
541 /* 1 if pseudo index register, eiz/riz, is allowed . */
542 static int allow_index_reg
= 0;
544 static enum check_kind
550 sse_check
, operand_check
= check_warning
;
552 /* Register prefix used for error message. */
553 static const char *register_prefix
= "%";
555 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
556 leave, push, and pop instructions so that gcc has the same stack
557 frame as in 32 bit mode. */
558 static char stackop_size
= '\0';
560 /* Non-zero to optimize code alignment. */
561 int optimize_align_code
= 1;
563 /* Non-zero to quieten some warnings. */
564 static int quiet_warnings
= 0;
567 static const char *cpu_arch_name
= NULL
;
568 static char *cpu_sub_arch_name
= NULL
;
570 /* CPU feature flags. */
571 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
573 /* If we have selected a cpu we are generating instructions for. */
574 static int cpu_arch_tune_set
= 0;
576 /* Cpu we are generating instructions for. */
577 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
579 /* CPU feature flags of cpu we are generating instructions for. */
580 static i386_cpu_flags cpu_arch_tune_flags
;
582 /* CPU instruction set architecture used. */
583 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
585 /* CPU feature flags of instruction set architecture used. */
586 i386_cpu_flags cpu_arch_isa_flags
;
588 /* If set, conditional jumps are not automatically promoted to handle
589 larger than a byte offset. */
590 static unsigned int no_cond_jump_promotion
= 0;
592 /* Encode SSE instructions with VEX prefix. */
593 static unsigned int sse2avx
;
595 /* Encode scalar AVX instructions with specific vector length. */
602 /* Encode scalar EVEX LIG instructions with specific vector length. */
610 /* Encode EVEX WIG instructions with specific evex.w. */
617 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
618 static symbolS
*GOT_symbol
;
620 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
621 unsigned int x86_dwarf2_return_column
;
623 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
624 int x86_cie_data_alignment
;
626 /* Interface to relax_segment.
627 There are 3 major relax states for 386 jump insns because the
628 different types of jumps add different sizes to frags when we're
629 figuring out what sort of jump to choose to reach a given label. */
632 #define UNCOND_JUMP 0
634 #define COND_JUMP86 2
639 #define SMALL16 (SMALL | CODE16)
641 #define BIG16 (BIG | CODE16)
645 #define INLINE __inline__
651 #define ENCODE_RELAX_STATE(type, size) \
652 ((relax_substateT) (((type) << 2) | (size)))
653 #define TYPE_FROM_RELAX_STATE(s) \
655 #define DISP_SIZE_FROM_RELAX_STATE(s) \
656 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
658 /* This table is used by relax_frag to promote short jumps to long
659 ones where necessary. SMALL (short) jumps may be promoted to BIG
660 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
661 don't allow a short jump in a 32 bit code segment to be promoted to
662 a 16 bit offset jump because it's slower (requires data size
663 prefix), and doesn't work, unless the destination is in the bottom
664 64k of the code segment (The top 16 bits of eip are zeroed). */
666 const relax_typeS md_relax_table
[] =
669 1) most positive reach of this state,
670 2) most negative reach of this state,
671 3) how many bytes this mode will have in the variable part of the frag
672 4) which index into the table to try if we can't fit into this one. */
674 /* UNCOND_JUMP states. */
675 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
676 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
677 /* dword jmp adds 4 bytes to frag:
678 0 extra opcode bytes, 4 displacement bytes. */
680 /* word jmp adds 2 byte2 to frag:
681 0 extra opcode bytes, 2 displacement bytes. */
684 /* COND_JUMP states. */
685 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
686 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
687 /* dword conditionals adds 5 bytes to frag:
688 1 extra opcode byte, 4 displacement bytes. */
690 /* word conditionals add 3 bytes to frag:
691 1 extra opcode byte, 2 displacement bytes. */
694 /* COND_JUMP86 states. */
695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
696 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
697 /* dword conditionals adds 5 bytes to frag:
698 1 extra opcode byte, 4 displacement bytes. */
700 /* word conditionals add 4 bytes to frag:
701 1 displacement byte and a 3 byte long branch insn. */
705 static const arch_entry cpu_arch
[] =
707 /* Do not replace the first two entries - i386_target_format()
708 relies on them being there in this order. */
709 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
710 CPU_GENERIC32_FLAGS
, 0, 0 },
711 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
712 CPU_GENERIC64_FLAGS
, 0, 0 },
713 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
714 CPU_NONE_FLAGS
, 0, 0 },
715 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
716 CPU_I186_FLAGS
, 0, 0 },
717 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
718 CPU_I286_FLAGS
, 0, 0 },
719 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
720 CPU_I386_FLAGS
, 0, 0 },
721 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
722 CPU_I486_FLAGS
, 0, 0 },
723 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
724 CPU_I586_FLAGS
, 0, 0 },
725 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
726 CPU_I686_FLAGS
, 0, 0 },
727 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
728 CPU_I586_FLAGS
, 0, 0 },
729 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
730 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
731 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
732 CPU_P2_FLAGS
, 0, 0 },
733 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
734 CPU_P3_FLAGS
, 0, 0 },
735 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
736 CPU_P4_FLAGS
, 0, 0 },
737 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
738 CPU_CORE_FLAGS
, 0, 0 },
739 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
740 CPU_NOCONA_FLAGS
, 0, 0 },
741 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
742 CPU_CORE_FLAGS
, 1, 0 },
743 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
744 CPU_CORE_FLAGS
, 0, 0 },
745 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
746 CPU_CORE2_FLAGS
, 1, 0 },
747 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
748 CPU_CORE2_FLAGS
, 0, 0 },
749 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
750 CPU_COREI7_FLAGS
, 0, 0 },
751 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
752 CPU_L1OM_FLAGS
, 0, 0 },
753 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
754 CPU_K1OM_FLAGS
, 0, 0 },
755 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
756 CPU_K6_FLAGS
, 0, 0 },
757 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
758 CPU_K6_2_FLAGS
, 0, 0 },
759 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
760 CPU_ATHLON_FLAGS
, 0, 0 },
761 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
762 CPU_K8_FLAGS
, 1, 0 },
763 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
764 CPU_K8_FLAGS
, 0, 0 },
765 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
766 CPU_K8_FLAGS
, 0, 0 },
767 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
768 CPU_AMDFAM10_FLAGS
, 0, 0 },
769 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
770 CPU_BDVER1_FLAGS
, 0, 0 },
771 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
772 CPU_BDVER2_FLAGS
, 0, 0 },
773 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
774 CPU_BDVER3_FLAGS
, 0, 0 },
775 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
776 CPU_BTVER1_FLAGS
, 0, 0 },
777 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
778 CPU_BTVER2_FLAGS
, 0, 0 },
779 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
780 CPU_8087_FLAGS
, 0, 0 },
781 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
782 CPU_287_FLAGS
, 0, 0 },
783 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
784 CPU_387_FLAGS
, 0, 0 },
785 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
786 CPU_ANY87_FLAGS
, 0, 1 },
787 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
788 CPU_MMX_FLAGS
, 0, 0 },
789 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
790 CPU_3DNOWA_FLAGS
, 0, 1 },
791 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
792 CPU_SSE_FLAGS
, 0, 0 },
793 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
794 CPU_SSE2_FLAGS
, 0, 0 },
795 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
796 CPU_SSE3_FLAGS
, 0, 0 },
797 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
798 CPU_SSSE3_FLAGS
, 0, 0 },
799 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
800 CPU_SSE4_1_FLAGS
, 0, 0 },
801 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
802 CPU_SSE4_2_FLAGS
, 0, 0 },
803 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
804 CPU_SSE4_2_FLAGS
, 0, 0 },
805 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
806 CPU_ANY_SSE_FLAGS
, 0, 1 },
807 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
808 CPU_AVX_FLAGS
, 0, 0 },
809 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
810 CPU_AVX2_FLAGS
, 0, 0 },
811 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
812 CPU_AVX512F_FLAGS
, 0, 0 },
813 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
814 CPU_AVX512CD_FLAGS
, 0, 0 },
815 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
816 CPU_AVX512ER_FLAGS
, 0, 0 },
817 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
818 CPU_AVX512PF_FLAGS
, 0, 0 },
819 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
820 CPU_ANY_AVX_FLAGS
, 0, 1 },
821 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
822 CPU_VMX_FLAGS
, 0, 0 },
823 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
824 CPU_VMFUNC_FLAGS
, 0, 0 },
825 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
826 CPU_SMX_FLAGS
, 0, 0 },
827 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
828 CPU_XSAVE_FLAGS
, 0, 0 },
829 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
830 CPU_XSAVEOPT_FLAGS
, 0, 0 },
831 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
832 CPU_AES_FLAGS
, 0, 0 },
833 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
834 CPU_PCLMUL_FLAGS
, 0, 0 },
835 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
836 CPU_PCLMUL_FLAGS
, 1, 0 },
837 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
838 CPU_FSGSBASE_FLAGS
, 0, 0 },
839 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
840 CPU_RDRND_FLAGS
, 0, 0 },
841 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
842 CPU_F16C_FLAGS
, 0, 0 },
843 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
844 CPU_BMI2_FLAGS
, 0, 0 },
845 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
846 CPU_FMA_FLAGS
, 0, 0 },
847 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
848 CPU_FMA4_FLAGS
, 0, 0 },
849 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
850 CPU_XOP_FLAGS
, 0, 0 },
851 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
852 CPU_LWP_FLAGS
, 0, 0 },
853 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
854 CPU_MOVBE_FLAGS
, 0, 0 },
855 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
856 CPU_CX16_FLAGS
, 0, 0 },
857 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
858 CPU_EPT_FLAGS
, 0, 0 },
859 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
860 CPU_LZCNT_FLAGS
, 0, 0 },
861 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
862 CPU_HLE_FLAGS
, 0, 0 },
863 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
864 CPU_RTM_FLAGS
, 0, 0 },
865 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
866 CPU_INVPCID_FLAGS
, 0, 0 },
867 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
868 CPU_CLFLUSH_FLAGS
, 0, 0 },
869 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
870 CPU_NOP_FLAGS
, 0, 0 },
871 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
872 CPU_SYSCALL_FLAGS
, 0, 0 },
873 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
874 CPU_RDTSCP_FLAGS
, 0, 0 },
875 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
876 CPU_3DNOW_FLAGS
, 0, 0 },
877 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
878 CPU_3DNOWA_FLAGS
, 0, 0 },
879 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
880 CPU_PADLOCK_FLAGS
, 0, 0 },
881 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
882 CPU_SVME_FLAGS
, 1, 0 },
883 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
884 CPU_SVME_FLAGS
, 0, 0 },
885 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
886 CPU_SSE4A_FLAGS
, 0, 0 },
887 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
888 CPU_ABM_FLAGS
, 0, 0 },
889 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
890 CPU_BMI_FLAGS
, 0, 0 },
891 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
892 CPU_TBM_FLAGS
, 0, 0 },
893 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
894 CPU_ADX_FLAGS
, 0, 0 },
895 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
896 CPU_RDSEED_FLAGS
, 0, 0 },
897 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
898 CPU_PRFCHW_FLAGS
, 0, 0 },
899 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
900 CPU_SMAP_FLAGS
, 0, 0 },
901 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
902 CPU_MPX_FLAGS
, 0, 0 },
903 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
904 CPU_SHA_FLAGS
, 0, 0 },
908 /* Like s_lcomm_internal in gas/read.c but the alignment string
909 is allowed to be optional. */
912 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
919 && *input_line_pointer
== ',')
921 align
= parse_align (needs_align
- 1);
923 if (align
== (addressT
) -1)
938 bss_alloc (symbolP
, size
, align
);
943 pe_lcomm (int needs_align
)
945 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
949 const pseudo_typeS md_pseudo_table
[] =
951 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
952 {"align", s_align_bytes
, 0},
954 {"align", s_align_ptwo
, 0},
956 {"arch", set_cpu_arch
, 0},
960 {"lcomm", pe_lcomm
, 1},
962 {"ffloat", float_cons
, 'f'},
963 {"dfloat", float_cons
, 'd'},
964 {"tfloat", float_cons
, 'x'},
966 {"slong", signed_cons
, 4},
967 {"noopt", s_ignore
, 0},
968 {"optim", s_ignore
, 0},
969 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
970 {"code16", set_code_flag
, CODE_16BIT
},
971 {"code32", set_code_flag
, CODE_32BIT
},
972 {"code64", set_code_flag
, CODE_64BIT
},
973 {"intel_syntax", set_intel_syntax
, 1},
974 {"att_syntax", set_intel_syntax
, 0},
975 {"intel_mnemonic", set_intel_mnemonic
, 1},
976 {"att_mnemonic", set_intel_mnemonic
, 0},
977 {"allow_index_reg", set_allow_index_reg
, 1},
978 {"disallow_index_reg", set_allow_index_reg
, 0},
979 {"sse_check", set_check
, 0},
980 {"operand_check", set_check
, 1},
981 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
982 {"largecomm", handle_large_common
, 0},
984 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
985 {"loc", dwarf2_directive_loc
, 0},
986 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
989 {"secrel32", pe_directive_secrel
, 0},
994 /* For interface with expression (). */
995 extern char *input_line_pointer
;
997 /* Hash table for instruction mnemonic lookup. */
998 static struct hash_control
*op_hash
;
1000 /* Hash table for register lookup. */
1001 static struct hash_control
*reg_hash
;
1004 i386_align_code (fragS
*fragP
, int count
)
1006 /* Various efficient no-op patterns for aligning code labels.
1007 Note: Don't try to assemble the instructions in the comments.
1008 0L and 0w are not legal. */
1009 static const char f32_1
[] =
1011 static const char f32_2
[] =
1012 {0x66,0x90}; /* xchg %ax,%ax */
1013 static const char f32_3
[] =
1014 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1015 static const char f32_4
[] =
1016 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1017 static const char f32_5
[] =
1019 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1020 static const char f32_6
[] =
1021 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1022 static const char f32_7
[] =
1023 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1024 static const char f32_8
[] =
1026 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1027 static const char f32_9
[] =
1028 {0x89,0xf6, /* movl %esi,%esi */
1029 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1030 static const char f32_10
[] =
1031 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1032 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1033 static const char f32_11
[] =
1034 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1035 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1036 static const char f32_12
[] =
1037 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1038 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1039 static const char f32_13
[] =
1040 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1041 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1042 static const char f32_14
[] =
1043 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1044 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1045 static const char f16_3
[] =
1046 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1047 static const char f16_4
[] =
1048 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1049 static const char f16_5
[] =
1051 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1052 static const char f16_6
[] =
1053 {0x89,0xf6, /* mov %si,%si */
1054 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1055 static const char f16_7
[] =
1056 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1057 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1058 static const char f16_8
[] =
1059 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1060 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1061 static const char jump_31
[] =
1062 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1063 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1064 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1065 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1066 static const char *const f32_patt
[] = {
1067 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1068 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1070 static const char *const f16_patt
[] = {
1071 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1073 /* nopl (%[re]ax) */
1074 static const char alt_3
[] =
1076 /* nopl 0(%[re]ax) */
1077 static const char alt_4
[] =
1078 {0x0f,0x1f,0x40,0x00};
1079 /* nopl 0(%[re]ax,%[re]ax,1) */
1080 static const char alt_5
[] =
1081 {0x0f,0x1f,0x44,0x00,0x00};
1082 /* nopw 0(%[re]ax,%[re]ax,1) */
1083 static const char alt_6
[] =
1084 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1085 /* nopl 0L(%[re]ax) */
1086 static const char alt_7
[] =
1087 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1088 /* nopl 0L(%[re]ax,%[re]ax,1) */
1089 static const char alt_8
[] =
1090 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1091 /* nopw 0L(%[re]ax,%[re]ax,1) */
1092 static const char alt_9
[] =
1093 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1094 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1095 static const char alt_10
[] =
1096 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1098 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1099 static const char alt_long_11
[] =
1101 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1104 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1105 static const char alt_long_12
[] =
1108 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1112 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1113 static const char alt_long_13
[] =
1117 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1122 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1123 static const char alt_long_14
[] =
1128 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1134 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1135 static const char alt_long_15
[] =
1141 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1142 /* nopl 0(%[re]ax,%[re]ax,1)
1143 nopw 0(%[re]ax,%[re]ax,1) */
1144 static const char alt_short_11
[] =
1145 {0x0f,0x1f,0x44,0x00,0x00,
1146 0x66,0x0f,0x1f,0x44,0x00,0x00};
1147 /* nopw 0(%[re]ax,%[re]ax,1)
1148 nopw 0(%[re]ax,%[re]ax,1) */
1149 static const char alt_short_12
[] =
1150 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1151 0x66,0x0f,0x1f,0x44,0x00,0x00};
1152 /* nopw 0(%[re]ax,%[re]ax,1)
1154 static const char alt_short_13
[] =
1155 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1156 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1159 static const char alt_short_14
[] =
1160 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1161 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1163 nopl 0L(%[re]ax,%[re]ax,1) */
1164 static const char alt_short_15
[] =
1165 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1166 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1167 static const char *const alt_short_patt
[] = {
1168 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1169 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1170 alt_short_14
, alt_short_15
1172 static const char *const alt_long_patt
[] = {
1173 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1174 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1175 alt_long_14
, alt_long_15
1178 /* Only align for at least a positive non-zero boundary. */
1179 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1182 /* We need to decide which NOP sequence to use for 32bit and
1183 64bit. When -mtune= is used:
1185 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1186 PROCESSOR_GENERIC32, f32_patt will be used.
1187 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1188 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1189 PROCESSOR_GENERIC64, alt_long_patt will be used.
1190 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1191 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1194 When -mtune= isn't used, alt_long_patt will be used if
1195 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1198 When -march= or .arch is used, we can't use anything beyond
1199 cpu_arch_isa_flags. */
1201 if (flag_code
== CODE_16BIT
)
1205 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1207 /* Adjust jump offset. */
1208 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1211 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1212 f16_patt
[count
- 1], count
);
1216 const char *const *patt
= NULL
;
1218 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1220 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1221 switch (cpu_arch_tune
)
1223 case PROCESSOR_UNKNOWN
:
1224 /* We use cpu_arch_isa_flags to check if we SHOULD
1225 optimize with nops. */
1226 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1227 patt
= alt_long_patt
;
1231 case PROCESSOR_PENTIUM4
:
1232 case PROCESSOR_NOCONA
:
1233 case PROCESSOR_CORE
:
1234 case PROCESSOR_CORE2
:
1235 case PROCESSOR_COREI7
:
1236 case PROCESSOR_L1OM
:
1237 case PROCESSOR_K1OM
:
1238 case PROCESSOR_GENERIC64
:
1239 patt
= alt_long_patt
;
1242 case PROCESSOR_ATHLON
:
1244 case PROCESSOR_AMDFAM10
:
1247 patt
= alt_short_patt
;
1249 case PROCESSOR_I386
:
1250 case PROCESSOR_I486
:
1251 case PROCESSOR_PENTIUM
:
1252 case PROCESSOR_PENTIUMPRO
:
1253 case PROCESSOR_GENERIC32
:
1260 switch (fragP
->tc_frag_data
.tune
)
1262 case PROCESSOR_UNKNOWN
:
1263 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1264 PROCESSOR_UNKNOWN. */
1268 case PROCESSOR_I386
:
1269 case PROCESSOR_I486
:
1270 case PROCESSOR_PENTIUM
:
1272 case PROCESSOR_ATHLON
:
1274 case PROCESSOR_AMDFAM10
:
1277 case PROCESSOR_GENERIC32
:
1278 /* We use cpu_arch_isa_flags to check if we CAN optimize
1280 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1281 patt
= alt_short_patt
;
1285 case PROCESSOR_PENTIUMPRO
:
1286 case PROCESSOR_PENTIUM4
:
1287 case PROCESSOR_NOCONA
:
1288 case PROCESSOR_CORE
:
1289 case PROCESSOR_CORE2
:
1290 case PROCESSOR_COREI7
:
1291 case PROCESSOR_L1OM
:
1292 case PROCESSOR_K1OM
:
1293 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1294 patt
= alt_long_patt
;
1298 case PROCESSOR_GENERIC64
:
1299 patt
= alt_long_patt
;
1304 if (patt
== f32_patt
)
1306 /* If the padding is less than 15 bytes, we use the normal
1307 ones. Otherwise, we use a jump instruction and adjust
1311 /* For 64bit, the limit is 3 bytes. */
1312 if (flag_code
== CODE_64BIT
1313 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1318 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1319 patt
[count
- 1], count
);
1322 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1324 /* Adjust jump offset. */
1325 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1330 /* Maximum length of an instruction is 15 byte. If the
1331 padding is greater than 15 bytes and we don't use jump,
1332 we have to break it into smaller pieces. */
1333 int padding
= count
;
1334 while (padding
> 15)
1337 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1342 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1343 patt
[padding
- 1], padding
);
1346 fragP
->fr_var
= count
;
1350 operand_type_all_zero (const union i386_operand_type
*x
)
1352 switch (ARRAY_SIZE(x
->array
))
1361 return !x
->array
[0];
1368 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1370 switch (ARRAY_SIZE(x
->array
))
1385 operand_type_equal (const union i386_operand_type
*x
,
1386 const union i386_operand_type
*y
)
1388 switch (ARRAY_SIZE(x
->array
))
1391 if (x
->array
[2] != y
->array
[2])
1394 if (x
->array
[1] != y
->array
[1])
1397 return x
->array
[0] == y
->array
[0];
1405 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1407 switch (ARRAY_SIZE(x
->array
))
1416 return !x
->array
[0];
1423 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1425 switch (ARRAY_SIZE(x
->array
))
1440 cpu_flags_equal (const union i386_cpu_flags
*x
,
1441 const union i386_cpu_flags
*y
)
1443 switch (ARRAY_SIZE(x
->array
))
1446 if (x
->array
[2] != y
->array
[2])
1449 if (x
->array
[1] != y
->array
[1])
1452 return x
->array
[0] == y
->array
[0];
1460 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1462 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1463 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1466 static INLINE i386_cpu_flags
1467 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1469 switch (ARRAY_SIZE (x
.array
))
1472 x
.array
[2] &= y
.array
[2];
1474 x
.array
[1] &= y
.array
[1];
1476 x
.array
[0] &= y
.array
[0];
1484 static INLINE i386_cpu_flags
1485 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1487 switch (ARRAY_SIZE (x
.array
))
1490 x
.array
[2] |= y
.array
[2];
1492 x
.array
[1] |= y
.array
[1];
1494 x
.array
[0] |= y
.array
[0];
1502 static INLINE i386_cpu_flags
1503 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1505 switch (ARRAY_SIZE (x
.array
))
1508 x
.array
[2] &= ~y
.array
[2];
1510 x
.array
[1] &= ~y
.array
[1];
1512 x
.array
[0] &= ~y
.array
[0];
1520 #define CPU_FLAGS_ARCH_MATCH 0x1
1521 #define CPU_FLAGS_64BIT_MATCH 0x2
1522 #define CPU_FLAGS_AES_MATCH 0x4
1523 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1524 #define CPU_FLAGS_AVX_MATCH 0x10
1526 #define CPU_FLAGS_32BIT_MATCH \
1527 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1528 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1529 #define CPU_FLAGS_PERFECT_MATCH \
1530 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1532 /* Return CPU flags match bits. */
1535 cpu_flags_match (const insn_template
*t
)
1537 i386_cpu_flags x
= t
->cpu_flags
;
1538 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1540 x
.bitfield
.cpu64
= 0;
1541 x
.bitfield
.cpuno64
= 0;
1543 if (cpu_flags_all_zero (&x
))
1545 /* This instruction is available on all archs. */
1546 match
|= CPU_FLAGS_32BIT_MATCH
;
1550 /* This instruction is available only on some archs. */
1551 i386_cpu_flags cpu
= cpu_arch_flags
;
1553 cpu
.bitfield
.cpu64
= 0;
1554 cpu
.bitfield
.cpuno64
= 0;
1555 cpu
= cpu_flags_and (x
, cpu
);
1556 if (!cpu_flags_all_zero (&cpu
))
1558 if (x
.bitfield
.cpuavx
)
1560 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1561 if (cpu
.bitfield
.cpuavx
)
1563 /* Check SSE2AVX. */
1564 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1566 match
|= (CPU_FLAGS_ARCH_MATCH
1567 | CPU_FLAGS_AVX_MATCH
);
1569 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1570 match
|= CPU_FLAGS_AES_MATCH
;
1572 if (!x
.bitfield
.cpupclmul
1573 || cpu
.bitfield
.cpupclmul
)
1574 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1578 match
|= CPU_FLAGS_ARCH_MATCH
;
1581 match
|= CPU_FLAGS_32BIT_MATCH
;
1587 static INLINE i386_operand_type
1588 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1590 switch (ARRAY_SIZE (x
.array
))
1593 x
.array
[2] &= y
.array
[2];
1595 x
.array
[1] &= y
.array
[1];
1597 x
.array
[0] &= y
.array
[0];
1605 static INLINE i386_operand_type
1606 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1608 switch (ARRAY_SIZE (x
.array
))
1611 x
.array
[2] |= y
.array
[2];
1613 x
.array
[1] |= y
.array
[1];
1615 x
.array
[0] |= y
.array
[0];
1623 static INLINE i386_operand_type
1624 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1626 switch (ARRAY_SIZE (x
.array
))
1629 x
.array
[2] ^= y
.array
[2];
1631 x
.array
[1] ^= y
.array
[1];
1633 x
.array
[0] ^= y
.array
[0];
1641 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1642 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1643 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1644 static const i386_operand_type inoutportreg
1645 = OPERAND_TYPE_INOUTPORTREG
;
1646 static const i386_operand_type reg16_inoutportreg
1647 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1648 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1649 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1650 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1651 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1652 static const i386_operand_type anydisp
1653 = OPERAND_TYPE_ANYDISP
;
1654 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1655 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1656 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1657 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1658 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1659 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1660 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1661 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1662 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1663 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1664 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1665 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1666 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1667 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1668 static const i386_operand_type regbnd
= OPERAND_TYPE_REGBND
;
1669 static const i386_operand_type vec_disp8
= OPERAND_TYPE_VEC_DISP8
;
1680 operand_type_check (i386_operand_type t
, enum operand_type c
)
1685 return (t
.bitfield
.reg8
1688 || t
.bitfield
.reg64
);
1691 return (t
.bitfield
.imm8
1695 || t
.bitfield
.imm32s
1696 || t
.bitfield
.imm64
);
1699 return (t
.bitfield
.disp8
1700 || t
.bitfield
.disp16
1701 || t
.bitfield
.disp32
1702 || t
.bitfield
.disp32s
1703 || t
.bitfield
.disp64
);
1706 return (t
.bitfield
.disp8
1707 || t
.bitfield
.disp16
1708 || t
.bitfield
.disp32
1709 || t
.bitfield
.disp32s
1710 || t
.bitfield
.disp64
1711 || t
.bitfield
.baseindex
);
1720 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1721 operand J for instruction template T. */
1724 match_reg_size (const insn_template
*t
, unsigned int j
)
1726 return !((i
.types
[j
].bitfield
.byte
1727 && !t
->operand_types
[j
].bitfield
.byte
)
1728 || (i
.types
[j
].bitfield
.word
1729 && !t
->operand_types
[j
].bitfield
.word
)
1730 || (i
.types
[j
].bitfield
.dword
1731 && !t
->operand_types
[j
].bitfield
.dword
)
1732 || (i
.types
[j
].bitfield
.qword
1733 && !t
->operand_types
[j
].bitfield
.qword
));
1736 /* Return 1 if there is no conflict in any size on operand J for
1737 instruction template T. */
1740 match_mem_size (const insn_template
*t
, unsigned int j
)
1742 return (match_reg_size (t
, j
)
1743 && !((i
.types
[j
].bitfield
.unspecified
1744 && !t
->operand_types
[j
].bitfield
.unspecified
)
1745 || (i
.types
[j
].bitfield
.fword
1746 && !t
->operand_types
[j
].bitfield
.fword
)
1747 || (i
.types
[j
].bitfield
.tbyte
1748 && !t
->operand_types
[j
].bitfield
.tbyte
)
1749 || (i
.types
[j
].bitfield
.xmmword
1750 && !t
->operand_types
[j
].bitfield
.xmmword
)
1751 || (i
.types
[j
].bitfield
.ymmword
1752 && !t
->operand_types
[j
].bitfield
.ymmword
)
1753 || (i
.types
[j
].bitfield
.zmmword
1754 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1757 /* Return 1 if there is no size conflict on any operands for
1758 instruction template T. */
1761 operand_size_match (const insn_template
*t
)
1766 /* Don't check jump instructions. */
1767 if (t
->opcode_modifier
.jump
1768 || t
->opcode_modifier
.jumpbyte
1769 || t
->opcode_modifier
.jumpdword
1770 || t
->opcode_modifier
.jumpintersegment
)
1773 /* Check memory and accumulator operand size. */
1774 for (j
= 0; j
< i
.operands
; j
++)
1776 if (t
->operand_types
[j
].bitfield
.anysize
)
1779 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1785 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1794 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1797 i
.error
= operand_size_mismatch
;
1801 /* Check reverse. */
1802 gas_assert (i
.operands
== 2);
1805 for (j
= 0; j
< 2; j
++)
1807 if (t
->operand_types
[j
].bitfield
.acc
1808 && !match_reg_size (t
, j
? 0 : 1))
1811 if (i
.types
[j
].bitfield
.mem
1812 && !match_mem_size (t
, j
? 0 : 1))
1820 operand_type_match (i386_operand_type overlap
,
1821 i386_operand_type given
)
1823 i386_operand_type temp
= overlap
;
1825 temp
.bitfield
.jumpabsolute
= 0;
1826 temp
.bitfield
.unspecified
= 0;
1827 temp
.bitfield
.byte
= 0;
1828 temp
.bitfield
.word
= 0;
1829 temp
.bitfield
.dword
= 0;
1830 temp
.bitfield
.fword
= 0;
1831 temp
.bitfield
.qword
= 0;
1832 temp
.bitfield
.tbyte
= 0;
1833 temp
.bitfield
.xmmword
= 0;
1834 temp
.bitfield
.ymmword
= 0;
1835 temp
.bitfield
.zmmword
= 0;
1836 if (operand_type_all_zero (&temp
))
1839 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1840 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1844 i
.error
= operand_type_mismatch
;
1848 /* If given types g0 and g1 are registers they must be of the same type
1849 unless the expected operand type register overlap is null.
1850 Note that Acc in a template matches every size of reg. */
1853 operand_type_register_match (i386_operand_type m0
,
1854 i386_operand_type g0
,
1855 i386_operand_type t0
,
1856 i386_operand_type m1
,
1857 i386_operand_type g1
,
1858 i386_operand_type t1
)
1860 if (!operand_type_check (g0
, reg
))
1863 if (!operand_type_check (g1
, reg
))
1866 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1867 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1868 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1869 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1872 if (m0
.bitfield
.acc
)
1874 t0
.bitfield
.reg8
= 1;
1875 t0
.bitfield
.reg16
= 1;
1876 t0
.bitfield
.reg32
= 1;
1877 t0
.bitfield
.reg64
= 1;
1880 if (m1
.bitfield
.acc
)
1882 t1
.bitfield
.reg8
= 1;
1883 t1
.bitfield
.reg16
= 1;
1884 t1
.bitfield
.reg32
= 1;
1885 t1
.bitfield
.reg64
= 1;
1888 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1889 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1890 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1891 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1894 i
.error
= register_type_mismatch
;
1899 static INLINE
unsigned int
1900 register_number (const reg_entry
*r
)
1902 unsigned int nr
= r
->reg_num
;
1904 if (r
->reg_flags
& RegRex
)
1910 static INLINE
unsigned int
1911 mode_from_disp_size (i386_operand_type t
)
1913 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1915 else if (t
.bitfield
.disp16
1916 || t
.bitfield
.disp32
1917 || t
.bitfield
.disp32s
)
1924 fits_in_signed_byte (offsetT num
)
1926 return (num
>= -128) && (num
<= 127);
1930 fits_in_unsigned_byte (offsetT num
)
1932 return (num
& 0xff) == num
;
1936 fits_in_unsigned_word (offsetT num
)
1938 return (num
& 0xffff) == num
;
1942 fits_in_signed_word (offsetT num
)
1944 return (-32768 <= num
) && (num
<= 32767);
1948 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1953 return (!(((offsetT
) -1 << 31) & num
)
1954 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1956 } /* fits_in_signed_long() */
1959 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1964 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1966 } /* fits_in_unsigned_long() */
1969 fits_in_vec_disp8 (offsetT num
)
1971 int shift
= i
.memshift
;
1977 mask
= (1 << shift
) - 1;
1979 /* Return 0 if NUM isn't properly aligned. */
1983 /* Check if NUM will fit in 8bit after shift. */
1984 return fits_in_signed_byte (num
>> shift
);
1988 fits_in_imm4 (offsetT num
)
1990 return (num
& 0xf) == num
;
1993 static i386_operand_type
1994 smallest_imm_type (offsetT num
)
1996 i386_operand_type t
;
1998 operand_type_set (&t
, 0);
1999 t
.bitfield
.imm64
= 1;
2001 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2003 /* This code is disabled on the 486 because all the Imm1 forms
2004 in the opcode table are slower on the i486. They're the
2005 versions with the implicitly specified single-position
2006 displacement, which has another syntax if you really want to
2008 t
.bitfield
.imm1
= 1;
2009 t
.bitfield
.imm8
= 1;
2010 t
.bitfield
.imm8s
= 1;
2011 t
.bitfield
.imm16
= 1;
2012 t
.bitfield
.imm32
= 1;
2013 t
.bitfield
.imm32s
= 1;
2015 else if (fits_in_signed_byte (num
))
2017 t
.bitfield
.imm8
= 1;
2018 t
.bitfield
.imm8s
= 1;
2019 t
.bitfield
.imm16
= 1;
2020 t
.bitfield
.imm32
= 1;
2021 t
.bitfield
.imm32s
= 1;
2023 else if (fits_in_unsigned_byte (num
))
2025 t
.bitfield
.imm8
= 1;
2026 t
.bitfield
.imm16
= 1;
2027 t
.bitfield
.imm32
= 1;
2028 t
.bitfield
.imm32s
= 1;
2030 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2032 t
.bitfield
.imm16
= 1;
2033 t
.bitfield
.imm32
= 1;
2034 t
.bitfield
.imm32s
= 1;
2036 else if (fits_in_signed_long (num
))
2038 t
.bitfield
.imm32
= 1;
2039 t
.bitfield
.imm32s
= 1;
2041 else if (fits_in_unsigned_long (num
))
2042 t
.bitfield
.imm32
= 1;
2048 offset_in_range (offsetT val
, int size
)
2054 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2055 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2056 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2058 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2064 /* If BFD64, sign extend val for 32bit address mode. */
2065 if (flag_code
!= CODE_64BIT
2066 || i
.prefix
[ADDR_PREFIX
])
2067 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2068 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2071 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2073 char buf1
[40], buf2
[40];
2075 sprint_value (buf1
, val
);
2076 sprint_value (buf2
, val
& mask
);
2077 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2091 a. PREFIX_EXIST if attempting to add a prefix where one from the
2092 same class already exists.
2093 b. PREFIX_LOCK if lock prefix is added.
2094 c. PREFIX_REP if rep/repne prefix is added.
2095 d. PREFIX_OTHER if other prefix is added.
2098 static enum PREFIX_GROUP
2099 add_prefix (unsigned int prefix
)
2101 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2104 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2105 && flag_code
== CODE_64BIT
)
2107 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2108 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2109 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2120 case CS_PREFIX_OPCODE
:
2121 case DS_PREFIX_OPCODE
:
2122 case ES_PREFIX_OPCODE
:
2123 case FS_PREFIX_OPCODE
:
2124 case GS_PREFIX_OPCODE
:
2125 case SS_PREFIX_OPCODE
:
2129 case REPNE_PREFIX_OPCODE
:
2130 case REPE_PREFIX_OPCODE
:
2135 case LOCK_PREFIX_OPCODE
:
2144 case ADDR_PREFIX_OPCODE
:
2148 case DATA_PREFIX_OPCODE
:
2152 if (i
.prefix
[q
] != 0)
2160 i
.prefix
[q
] |= prefix
;
2163 as_bad (_("same type of prefix used twice"));
2169 update_code_flag (int value
, int check
)
2171 PRINTF_LIKE ((*as_error
));
2173 flag_code
= (enum flag_code
) value
;
2174 if (flag_code
== CODE_64BIT
)
2176 cpu_arch_flags
.bitfield
.cpu64
= 1;
2177 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2181 cpu_arch_flags
.bitfield
.cpu64
= 0;
2182 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2184 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2187 as_error
= as_fatal
;
2190 (*as_error
) (_("64bit mode not supported on `%s'."),
2191 cpu_arch_name
? cpu_arch_name
: default_arch
);
2193 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2196 as_error
= as_fatal
;
2199 (*as_error
) (_("32bit mode not supported on `%s'."),
2200 cpu_arch_name
? cpu_arch_name
: default_arch
);
2202 stackop_size
= '\0';
2206 set_code_flag (int value
)
2208 update_code_flag (value
, 0);
2212 set_16bit_gcc_code_flag (int new_code_flag
)
2214 flag_code
= (enum flag_code
) new_code_flag
;
2215 if (flag_code
!= CODE_16BIT
)
2217 cpu_arch_flags
.bitfield
.cpu64
= 0;
2218 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2219 stackop_size
= LONG_MNEM_SUFFIX
;
2223 set_intel_syntax (int syntax_flag
)
2225 /* Find out if register prefixing is specified. */
2226 int ask_naked_reg
= 0;
2229 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2231 char *string
= input_line_pointer
;
2232 int e
= get_symbol_end ();
2234 if (strcmp (string
, "prefix") == 0)
2236 else if (strcmp (string
, "noprefix") == 0)
2239 as_bad (_("bad argument to syntax directive."));
2240 *input_line_pointer
= e
;
2242 demand_empty_rest_of_line ();
2244 intel_syntax
= syntax_flag
;
2246 if (ask_naked_reg
== 0)
2247 allow_naked_reg
= (intel_syntax
2248 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2250 allow_naked_reg
= (ask_naked_reg
< 0);
2252 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2254 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2255 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2256 register_prefix
= allow_naked_reg
? "" : "%";
2260 set_intel_mnemonic (int mnemonic_flag
)
2262 intel_mnemonic
= mnemonic_flag
;
2266 set_allow_index_reg (int flag
)
2268 allow_index_reg
= flag
;
2272 set_check (int what
)
2274 enum check_kind
*kind
;
2279 kind
= &operand_check
;
2290 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2292 char *string
= input_line_pointer
;
2293 int e
= get_symbol_end ();
2295 if (strcmp (string
, "none") == 0)
2297 else if (strcmp (string
, "warning") == 0)
2298 *kind
= check_warning
;
2299 else if (strcmp (string
, "error") == 0)
2300 *kind
= check_error
;
2302 as_bad (_("bad argument to %s_check directive."), str
);
2303 *input_line_pointer
= e
;
2306 as_bad (_("missing argument for %s_check directive"), str
);
2308 demand_empty_rest_of_line ();
2312 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2313 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2315 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2316 static const char *arch
;
2318 /* Intel LIOM is only supported on ELF. */
2324 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2325 use default_arch. */
2326 arch
= cpu_arch_name
;
2328 arch
= default_arch
;
2331 /* If we are targeting Intel L1OM, we must enable it. */
2332 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2333 || new_flag
.bitfield
.cpul1om
)
2336 /* If we are targeting Intel K1OM, we must enable it. */
2337 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2338 || new_flag
.bitfield
.cpuk1om
)
2341 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2346 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2350 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2352 char *string
= input_line_pointer
;
2353 int e
= get_symbol_end ();
2355 i386_cpu_flags flags
;
2357 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2359 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2361 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2365 cpu_arch_name
= cpu_arch
[j
].name
;
2366 cpu_sub_arch_name
= NULL
;
2367 cpu_arch_flags
= cpu_arch
[j
].flags
;
2368 if (flag_code
== CODE_64BIT
)
2370 cpu_arch_flags
.bitfield
.cpu64
= 1;
2371 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2375 cpu_arch_flags
.bitfield
.cpu64
= 0;
2376 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2378 cpu_arch_isa
= cpu_arch
[j
].type
;
2379 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2380 if (!cpu_arch_tune_set
)
2382 cpu_arch_tune
= cpu_arch_isa
;
2383 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2388 if (!cpu_arch
[j
].negated
)
2389 flags
= cpu_flags_or (cpu_arch_flags
,
2392 flags
= cpu_flags_and_not (cpu_arch_flags
,
2394 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2396 if (cpu_sub_arch_name
)
2398 char *name
= cpu_sub_arch_name
;
2399 cpu_sub_arch_name
= concat (name
,
2401 (const char *) NULL
);
2405 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2406 cpu_arch_flags
= flags
;
2407 cpu_arch_isa_flags
= flags
;
2409 *input_line_pointer
= e
;
2410 demand_empty_rest_of_line ();
2414 if (j
>= ARRAY_SIZE (cpu_arch
))
2415 as_bad (_("no such architecture: `%s'"), string
);
2417 *input_line_pointer
= e
;
2420 as_bad (_("missing cpu architecture"));
2422 no_cond_jump_promotion
= 0;
2423 if (*input_line_pointer
== ','
2424 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2426 char *string
= ++input_line_pointer
;
2427 int e
= get_symbol_end ();
2429 if (strcmp (string
, "nojumps") == 0)
2430 no_cond_jump_promotion
= 1;
2431 else if (strcmp (string
, "jumps") == 0)
2434 as_bad (_("no such architecture modifier: `%s'"), string
);
2436 *input_line_pointer
= e
;
2439 demand_empty_rest_of_line ();
2442 enum bfd_architecture
2445 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2447 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2448 || flag_code
!= CODE_64BIT
)
2449 as_fatal (_("Intel L1OM is 64bit ELF only"));
2450 return bfd_arch_l1om
;
2452 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2454 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2455 || flag_code
!= CODE_64BIT
)
2456 as_fatal (_("Intel K1OM is 64bit ELF only"));
2457 return bfd_arch_k1om
;
2460 return bfd_arch_i386
;
2466 if (!strncmp (default_arch
, "x86_64", 6))
2468 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2470 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2471 || default_arch
[6] != '\0')
2472 as_fatal (_("Intel L1OM is 64bit ELF only"));
2473 return bfd_mach_l1om
;
2475 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2477 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2478 || default_arch
[6] != '\0')
2479 as_fatal (_("Intel K1OM is 64bit ELF only"));
2480 return bfd_mach_k1om
;
2482 else if (default_arch
[6] == '\0')
2483 return bfd_mach_x86_64
;
2485 return bfd_mach_x64_32
;
2487 else if (!strcmp (default_arch
, "i386"))
2488 return bfd_mach_i386_i386
;
2490 as_fatal (_("unknown architecture"));
2496 const char *hash_err
;
2498 /* Initialize op_hash hash table. */
2499 op_hash
= hash_new ();
2502 const insn_template
*optab
;
2503 templates
*core_optab
;
2505 /* Setup for loop. */
2507 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2508 core_optab
->start
= optab
;
2513 if (optab
->name
== NULL
2514 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2516 /* different name --> ship out current template list;
2517 add to hash table; & begin anew. */
2518 core_optab
->end
= optab
;
2519 hash_err
= hash_insert (op_hash
,
2521 (void *) core_optab
);
2524 as_fatal (_("can't hash %s: %s"),
2528 if (optab
->name
== NULL
)
2530 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2531 core_optab
->start
= optab
;
2536 /* Initialize reg_hash hash table. */
2537 reg_hash
= hash_new ();
2539 const reg_entry
*regtab
;
2540 unsigned int regtab_size
= i386_regtab_size
;
2542 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2544 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2546 as_fatal (_("can't hash %s: %s"),
2552 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2557 for (c
= 0; c
< 256; c
++)
2562 mnemonic_chars
[c
] = c
;
2563 register_chars
[c
] = c
;
2564 operand_chars
[c
] = c
;
2566 else if (ISLOWER (c
))
2568 mnemonic_chars
[c
] = c
;
2569 register_chars
[c
] = c
;
2570 operand_chars
[c
] = c
;
2572 else if (ISUPPER (c
))
2574 mnemonic_chars
[c
] = TOLOWER (c
);
2575 register_chars
[c
] = mnemonic_chars
[c
];
2576 operand_chars
[c
] = c
;
2578 else if (c
== '{' || c
== '}')
2579 operand_chars
[c
] = c
;
2581 if (ISALPHA (c
) || ISDIGIT (c
))
2582 identifier_chars
[c
] = c
;
2585 identifier_chars
[c
] = c
;
2586 operand_chars
[c
] = c
;
2591 identifier_chars
['@'] = '@';
2594 identifier_chars
['?'] = '?';
2595 operand_chars
['?'] = '?';
2597 digit_chars
['-'] = '-';
2598 mnemonic_chars
['_'] = '_';
2599 mnemonic_chars
['-'] = '-';
2600 mnemonic_chars
['.'] = '.';
2601 identifier_chars
['_'] = '_';
2602 identifier_chars
['.'] = '.';
2604 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2605 operand_chars
[(unsigned char) *p
] = *p
;
2608 if (flag_code
== CODE_64BIT
)
2610 #if defined (OBJ_COFF) && defined (TE_PE)
2611 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2614 x86_dwarf2_return_column
= 16;
2616 x86_cie_data_alignment
= -8;
2620 x86_dwarf2_return_column
= 8;
2621 x86_cie_data_alignment
= -4;
2626 i386_print_statistics (FILE *file
)
2628 hash_print_statistics (file
, "i386 opcode", op_hash
);
2629 hash_print_statistics (file
, "i386 register", reg_hash
);
2634 /* Debugging routines for md_assemble. */
2635 static void pte (insn_template
*);
2636 static void pt (i386_operand_type
);
2637 static void pe (expressionS
*);
2638 static void ps (symbolS
*);
2641 pi (char *line
, i386_insn
*x
)
2645 fprintf (stdout
, "%s: template ", line
);
2647 fprintf (stdout
, " address: base %s index %s scale %x\n",
2648 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2649 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2650 x
->log2_scale_factor
);
2651 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2652 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2653 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2654 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2655 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2656 (x
->rex
& REX_W
) != 0,
2657 (x
->rex
& REX_R
) != 0,
2658 (x
->rex
& REX_X
) != 0,
2659 (x
->rex
& REX_B
) != 0);
2660 for (j
= 0; j
< x
->operands
; j
++)
2662 fprintf (stdout
, " #%d: ", j
+ 1);
2664 fprintf (stdout
, "\n");
2665 if (x
->types
[j
].bitfield
.reg8
2666 || x
->types
[j
].bitfield
.reg16
2667 || x
->types
[j
].bitfield
.reg32
2668 || x
->types
[j
].bitfield
.reg64
2669 || x
->types
[j
].bitfield
.regmmx
2670 || x
->types
[j
].bitfield
.regxmm
2671 || x
->types
[j
].bitfield
.regymm
2672 || x
->types
[j
].bitfield
.regzmm
2673 || x
->types
[j
].bitfield
.sreg2
2674 || x
->types
[j
].bitfield
.sreg3
2675 || x
->types
[j
].bitfield
.control
2676 || x
->types
[j
].bitfield
.debug
2677 || x
->types
[j
].bitfield
.test
)
2678 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2679 if (operand_type_check (x
->types
[j
], imm
))
2681 if (operand_type_check (x
->types
[j
], disp
))
2682 pe (x
->op
[j
].disps
);
2687 pte (insn_template
*t
)
2690 fprintf (stdout
, " %d operands ", t
->operands
);
2691 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2692 if (t
->extension_opcode
!= None
)
2693 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2694 if (t
->opcode_modifier
.d
)
2695 fprintf (stdout
, "D");
2696 if (t
->opcode_modifier
.w
)
2697 fprintf (stdout
, "W");
2698 fprintf (stdout
, "\n");
2699 for (j
= 0; j
< t
->operands
; j
++)
2701 fprintf (stdout
, " #%d type ", j
+ 1);
2702 pt (t
->operand_types
[j
]);
2703 fprintf (stdout
, "\n");
2710 fprintf (stdout
, " operation %d\n", e
->X_op
);
2711 fprintf (stdout
, " add_number %ld (%lx)\n",
2712 (long) e
->X_add_number
, (long) e
->X_add_number
);
2713 if (e
->X_add_symbol
)
2715 fprintf (stdout
, " add_symbol ");
2716 ps (e
->X_add_symbol
);
2717 fprintf (stdout
, "\n");
2721 fprintf (stdout
, " op_symbol ");
2722 ps (e
->X_op_symbol
);
2723 fprintf (stdout
, "\n");
2730 fprintf (stdout
, "%s type %s%s",
2732 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2733 segment_name (S_GET_SEGMENT (s
)));
2736 static struct type_name
2738 i386_operand_type mask
;
2741 const type_names
[] =
2743 { OPERAND_TYPE_REG8
, "r8" },
2744 { OPERAND_TYPE_REG16
, "r16" },
2745 { OPERAND_TYPE_REG32
, "r32" },
2746 { OPERAND_TYPE_REG64
, "r64" },
2747 { OPERAND_TYPE_IMM8
, "i8" },
2748 { OPERAND_TYPE_IMM8
, "i8s" },
2749 { OPERAND_TYPE_IMM16
, "i16" },
2750 { OPERAND_TYPE_IMM32
, "i32" },
2751 { OPERAND_TYPE_IMM32S
, "i32s" },
2752 { OPERAND_TYPE_IMM64
, "i64" },
2753 { OPERAND_TYPE_IMM1
, "i1" },
2754 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2755 { OPERAND_TYPE_DISP8
, "d8" },
2756 { OPERAND_TYPE_DISP16
, "d16" },
2757 { OPERAND_TYPE_DISP32
, "d32" },
2758 { OPERAND_TYPE_DISP32S
, "d32s" },
2759 { OPERAND_TYPE_DISP64
, "d64" },
2760 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2761 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2762 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2763 { OPERAND_TYPE_CONTROL
, "control reg" },
2764 { OPERAND_TYPE_TEST
, "test reg" },
2765 { OPERAND_TYPE_DEBUG
, "debug reg" },
2766 { OPERAND_TYPE_FLOATREG
, "FReg" },
2767 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2768 { OPERAND_TYPE_SREG2
, "SReg2" },
2769 { OPERAND_TYPE_SREG3
, "SReg3" },
2770 { OPERAND_TYPE_ACC
, "Acc" },
2771 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2772 { OPERAND_TYPE_REGMMX
, "rMMX" },
2773 { OPERAND_TYPE_REGXMM
, "rXMM" },
2774 { OPERAND_TYPE_REGYMM
, "rYMM" },
2775 { OPERAND_TYPE_REGZMM
, "rZMM" },
2776 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2777 { OPERAND_TYPE_ESSEG
, "es" },
2781 pt (i386_operand_type t
)
2784 i386_operand_type a
;
2786 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2788 a
= operand_type_and (t
, type_names
[j
].mask
);
2789 if (!operand_type_all_zero (&a
))
2790 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2795 #endif /* DEBUG386 */
2797 static bfd_reloc_code_real_type
2798 reloc (unsigned int size
,
2801 bfd_reloc_code_real_type other
)
2803 if (other
!= NO_RELOC
)
2805 reloc_howto_type
*rel
;
2810 case BFD_RELOC_X86_64_GOT32
:
2811 return BFD_RELOC_X86_64_GOT64
;
2813 case BFD_RELOC_X86_64_PLTOFF64
:
2814 return BFD_RELOC_X86_64_PLTOFF64
;
2816 case BFD_RELOC_X86_64_GOTPC32
:
2817 other
= BFD_RELOC_X86_64_GOTPC64
;
2819 case BFD_RELOC_X86_64_GOTPCREL
:
2820 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2822 case BFD_RELOC_X86_64_TPOFF32
:
2823 other
= BFD_RELOC_X86_64_TPOFF64
;
2825 case BFD_RELOC_X86_64_DTPOFF32
:
2826 other
= BFD_RELOC_X86_64_DTPOFF64
;
2832 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2833 if (other
== BFD_RELOC_SIZE32
)
2836 return BFD_RELOC_SIZE64
;
2838 as_bad (_("there are no pc-relative size relocations"));
2842 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2843 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2846 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2848 as_bad (_("unknown relocation (%u)"), other
);
2849 else if (size
!= bfd_get_reloc_size (rel
))
2850 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2851 bfd_get_reloc_size (rel
),
2853 else if (pcrel
&& !rel
->pc_relative
)
2854 as_bad (_("non-pc-relative relocation for pc-relative field"));
2855 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2857 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2859 as_bad (_("relocated field and relocation type differ in signedness"));
2868 as_bad (_("there are no unsigned pc-relative relocations"));
2871 case 1: return BFD_RELOC_8_PCREL
;
2872 case 2: return BFD_RELOC_16_PCREL
;
2873 case 4: return BFD_RELOC_32_PCREL
;
2874 case 8: return BFD_RELOC_64_PCREL
;
2876 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2883 case 4: return BFD_RELOC_X86_64_32S
;
2888 case 1: return BFD_RELOC_8
;
2889 case 2: return BFD_RELOC_16
;
2890 case 4: return BFD_RELOC_32
;
2891 case 8: return BFD_RELOC_64
;
2893 as_bad (_("cannot do %s %u byte relocation"),
2894 sign
> 0 ? "signed" : "unsigned", size
);
2900 /* Here we decide which fixups can be adjusted to make them relative to
2901 the beginning of the section instead of the symbol. Basically we need
2902 to make sure that the dynamic relocations are done correctly, so in
2903 some cases we force the original symbol to be used. */
2906 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2908 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2912 /* Don't adjust pc-relative references to merge sections in 64-bit
2914 if (use_rela_relocations
2915 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2919 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2920 and changed later by validate_fix. */
2921 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2922 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2925 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2926 for size relocations. */
2927 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2928 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2929 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2930 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2931 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2932 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2933 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2934 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2935 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2936 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2937 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2938 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2939 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2940 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2941 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2942 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2943 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2944 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2945 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2946 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2947 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2948 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2949 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2950 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2951 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2952 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2953 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2954 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2955 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2956 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2963 intel_float_operand (const char *mnemonic
)
2965 /* Note that the value returned is meaningful only for opcodes with (memory)
2966 operands, hence the code here is free to improperly handle opcodes that
2967 have no operands (for better performance and smaller code). */
2969 if (mnemonic
[0] != 'f')
2970 return 0; /* non-math */
2972 switch (mnemonic
[1])
2974 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2975 the fs segment override prefix not currently handled because no
2976 call path can make opcodes without operands get here */
2978 return 2 /* integer op */;
2980 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2981 return 3; /* fldcw/fldenv */
2984 if (mnemonic
[2] != 'o' /* fnop */)
2985 return 3; /* non-waiting control op */
2988 if (mnemonic
[2] == 's')
2989 return 3; /* frstor/frstpm */
2992 if (mnemonic
[2] == 'a')
2993 return 3; /* fsave */
2994 if (mnemonic
[2] == 't')
2996 switch (mnemonic
[3])
2998 case 'c': /* fstcw */
2999 case 'd': /* fstdw */
3000 case 'e': /* fstenv */
3001 case 's': /* fsts[gw] */
3007 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3008 return 0; /* fxsave/fxrstor are not really math ops */
3015 /* Build the VEX prefix. */
3018 build_vex_prefix (const insn_template
*t
)
3020 unsigned int register_specifier
;
3021 unsigned int implied_prefix
;
3022 unsigned int vector_length
;
3024 /* Check register specifier. */
3025 if (i
.vex
.register_specifier
)
3027 register_specifier
=
3028 ~register_number (i
.vex
.register_specifier
) & 0xf;
3029 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3032 register_specifier
= 0xf;
3034 /* Use 2-byte VEX prefix by swappping destination and source
3037 && i
.operands
== i
.reg_operands
3038 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3039 && i
.tm
.opcode_modifier
.s
3042 unsigned int xchg
= i
.operands
- 1;
3043 union i386_op temp_op
;
3044 i386_operand_type temp_type
;
3046 temp_type
= i
.types
[xchg
];
3047 i
.types
[xchg
] = i
.types
[0];
3048 i
.types
[0] = temp_type
;
3049 temp_op
= i
.op
[xchg
];
3050 i
.op
[xchg
] = i
.op
[0];
3053 gas_assert (i
.rm
.mode
== 3);
3057 i
.rm
.regmem
= i
.rm
.reg
;
3060 /* Use the next insn. */
3064 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3065 vector_length
= avxscalar
;
3067 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3069 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3074 case DATA_PREFIX_OPCODE
:
3077 case REPE_PREFIX_OPCODE
:
3080 case REPNE_PREFIX_OPCODE
:
3087 /* Use 2-byte VEX prefix if possible. */
3088 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3089 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3090 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3092 /* 2-byte VEX prefix. */
3096 i
.vex
.bytes
[0] = 0xc5;
3098 /* Check the REX.R bit. */
3099 r
= (i
.rex
& REX_R
) ? 0 : 1;
3100 i
.vex
.bytes
[1] = (r
<< 7
3101 | register_specifier
<< 3
3102 | vector_length
<< 2
3107 /* 3-byte VEX prefix. */
3112 switch (i
.tm
.opcode_modifier
.vexopcode
)
3116 i
.vex
.bytes
[0] = 0xc4;
3120 i
.vex
.bytes
[0] = 0xc4;
3124 i
.vex
.bytes
[0] = 0xc4;
3128 i
.vex
.bytes
[0] = 0x8f;
3132 i
.vex
.bytes
[0] = 0x8f;
3136 i
.vex
.bytes
[0] = 0x8f;
3142 /* The high 3 bits of the second VEX byte are 1's compliment
3143 of RXB bits from REX. */
3144 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3146 /* Check the REX.W bit. */
3147 w
= (i
.rex
& REX_W
) ? 1 : 0;
3148 if (i
.tm
.opcode_modifier
.vexw
)
3153 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3157 i
.vex
.bytes
[2] = (w
<< 7
3158 | register_specifier
<< 3
3159 | vector_length
<< 2
3164 /* Build the EVEX prefix. */
3167 build_evex_prefix (void)
3169 unsigned int register_specifier
;
3170 unsigned int implied_prefix
;
3172 rex_byte vrex_used
= 0;
3174 /* Check register specifier. */
3175 if (i
.vex
.register_specifier
)
3177 gas_assert ((i
.vrex
& REX_X
) == 0);
3179 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3180 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3181 register_specifier
+= 8;
3182 /* The upper 16 registers are encoded in the fourth byte of the
3184 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3185 i
.vex
.bytes
[3] = 0x8;
3186 register_specifier
= ~register_specifier
& 0xf;
3190 register_specifier
= 0xf;
3192 /* Encode upper 16 vector index register in the fourth byte of
3194 if (!(i
.vrex
& REX_X
))
3195 i
.vex
.bytes
[3] = 0x8;
3200 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3205 case DATA_PREFIX_OPCODE
:
3208 case REPE_PREFIX_OPCODE
:
3211 case REPNE_PREFIX_OPCODE
:
3218 /* 4 byte EVEX prefix. */
3220 i
.vex
.bytes
[0] = 0x62;
3223 switch (i
.tm
.opcode_modifier
.vexopcode
)
3239 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3241 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3243 /* The fifth bit of the second EVEX byte is 1's compliment of the
3244 REX_R bit in VREX. */
3245 if (!(i
.vrex
& REX_R
))
3246 i
.vex
.bytes
[1] |= 0x10;
3250 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3252 /* When all operands are registers, the REX_X bit in REX is not
3253 used. We reuse it to encode the upper 16 registers, which is
3254 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3255 as 1's compliment. */
3256 if ((i
.vrex
& REX_B
))
3259 i
.vex
.bytes
[1] &= ~0x40;
3263 /* EVEX instructions shouldn't need the REX prefix. */
3264 i
.vrex
&= ~vrex_used
;
3265 gas_assert (i
.vrex
== 0);
3267 /* Check the REX.W bit. */
3268 w
= (i
.rex
& REX_W
) ? 1 : 0;
3269 if (i
.tm
.opcode_modifier
.vexw
)
3271 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3274 /* If w is not set it means we are dealing with WIG instruction. */
3277 if (evexwig
== evexw1
)
3281 /* Encode the U bit. */
3282 implied_prefix
|= 0x4;
3284 /* The third byte of the EVEX prefix. */
3285 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3287 /* The fourth byte of the EVEX prefix. */
3288 /* The zeroing-masking bit. */
3289 if (i
.mask
&& i
.mask
->zeroing
)
3290 i
.vex
.bytes
[3] |= 0x80;
3292 /* Don't always set the broadcast bit if there is no RC. */
3295 /* Encode the vector length. */
3296 unsigned int vec_length
;
3298 switch (i
.tm
.opcode_modifier
.evex
)
3300 case EVEXLIG
: /* LL' is ignored */
3301 vec_length
= evexlig
<< 5;
3304 vec_length
= 0 << 5;
3307 vec_length
= 1 << 5;
3310 vec_length
= 2 << 5;
3316 i
.vex
.bytes
[3] |= vec_length
;
3317 /* Encode the broadcast bit. */
3319 i
.vex
.bytes
[3] |= 0x10;
3323 if (i
.rounding
->type
!= saeonly
)
3324 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3326 i
.vex
.bytes
[3] |= 0x10;
3329 if (i
.mask
&& i
.mask
->mask
)
3330 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3334 process_immext (void)
3338 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3341 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3342 with an opcode suffix which is coded in the same place as an
3343 8-bit immediate field would be.
3344 Here we check those operands and remove them afterwards. */
3347 for (x
= 0; x
< i
.operands
; x
++)
3348 if (register_number (i
.op
[x
].regs
) != x
)
3349 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3350 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3356 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3357 which is coded in the same place as an 8-bit immediate field
3358 would be. Here we fake an 8-bit immediate operand from the
3359 opcode suffix stored in tm.extension_opcode.
3361 AVX instructions also use this encoding, for some of
3362 3 argument instructions. */
3364 gas_assert (i
.imm_operands
<= 1
3366 || ((i
.tm
.opcode_modifier
.vex
3367 || i
.tm
.opcode_modifier
.evex
)
3368 && i
.operands
<= 4)));
3370 exp
= &im_expressions
[i
.imm_operands
++];
3371 i
.op
[i
.operands
].imms
= exp
;
3372 i
.types
[i
.operands
] = imm8
;
3374 exp
->X_op
= O_constant
;
3375 exp
->X_add_number
= i
.tm
.extension_opcode
;
3376 i
.tm
.extension_opcode
= None
;
3383 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3388 as_bad (_("invalid instruction `%s' after `%s'"),
3389 i
.tm
.name
, i
.hle_prefix
);
3392 if (i
.prefix
[LOCK_PREFIX
])
3394 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3398 case HLEPrefixRelease
:
3399 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3401 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3405 if (i
.mem_operands
== 0
3406 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3408 as_bad (_("memory destination needed for instruction `%s'"
3409 " after `xrelease'"), i
.tm
.name
);
3416 /* This is the guts of the machine-dependent assembler. LINE points to a
3417 machine dependent instruction. This function is supposed to emit
3418 the frags/bytes it assembles to. */
3421 md_assemble (char *line
)
3424 char mnemonic
[MAX_MNEM_SIZE
];
3425 const insn_template
*t
;
3427 /* Initialize globals. */
3428 memset (&i
, '\0', sizeof (i
));
3429 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3430 i
.reloc
[j
] = NO_RELOC
;
3431 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3432 memset (im_expressions
, '\0', sizeof (im_expressions
));
3433 save_stack_p
= save_stack
;
3435 /* First parse an instruction mnemonic & call i386_operand for the operands.
3436 We assume that the scrubber has arranged it so that line[0] is the valid
3437 start of a (possibly prefixed) mnemonic. */
3439 line
= parse_insn (line
, mnemonic
);
3443 line
= parse_operands (line
, mnemonic
);
3448 /* Now we've parsed the mnemonic into a set of templates, and have the
3449 operands at hand. */
3451 /* All intel opcodes have reversed operands except for "bound" and
3452 "enter". We also don't reverse intersegment "jmp" and "call"
3453 instructions with 2 immediate operands so that the immediate segment
3454 precedes the offset, as it does when in AT&T mode. */
3457 && (strcmp (mnemonic
, "bound") != 0)
3458 && (strcmp (mnemonic
, "invlpga") != 0)
3459 && !(operand_type_check (i
.types
[0], imm
)
3460 && operand_type_check (i
.types
[1], imm
)))
3463 /* The order of the immediates should be reversed
3464 for 2 immediates extrq and insertq instructions */
3465 if (i
.imm_operands
== 2
3466 && (strcmp (mnemonic
, "extrq") == 0
3467 || strcmp (mnemonic
, "insertq") == 0))
3468 swap_2_operands (0, 1);
3473 /* Don't optimize displacement for movabs since it only takes 64bit
3476 && i
.disp_encoding
!= disp_encoding_32bit
3477 && (flag_code
!= CODE_64BIT
3478 || strcmp (mnemonic
, "movabs") != 0))
3481 /* Next, we find a template that matches the given insn,
3482 making sure the overlap of the given operands types is consistent
3483 with the template operand types. */
3485 if (!(t
= match_template ()))
3488 if (sse_check
!= check_none
3489 && !i
.tm
.opcode_modifier
.noavx
3490 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3491 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3492 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3493 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3494 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3495 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3497 (sse_check
== check_warning
3499 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3502 /* Zap movzx and movsx suffix. The suffix has been set from
3503 "word ptr" or "byte ptr" on the source operand in Intel syntax
3504 or extracted from mnemonic in AT&T syntax. But we'll use
3505 the destination register to choose the suffix for encoding. */
3506 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3508 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3509 there is no suffix, the default will be byte extension. */
3510 if (i
.reg_operands
!= 2
3513 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3518 if (i
.tm
.opcode_modifier
.fwait
)
3519 if (!add_prefix (FWAIT_OPCODE
))
3522 /* Check if REP prefix is OK. */
3523 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3525 as_bad (_("invalid instruction `%s' after `%s'"),
3526 i
.tm
.name
, i
.rep_prefix
);
3530 /* Check for lock without a lockable instruction. Destination operand
3531 must be memory unless it is xchg (0x86). */
3532 if (i
.prefix
[LOCK_PREFIX
]
3533 && (!i
.tm
.opcode_modifier
.islockable
3534 || i
.mem_operands
== 0
3535 || (i
.tm
.base_opcode
!= 0x86
3536 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3538 as_bad (_("expecting lockable instruction after `lock'"));
3542 /* Check if HLE prefix is OK. */
3543 if (i
.hle_prefix
&& !check_hle ())
3546 /* Check BND prefix. */
3547 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3548 as_bad (_("expecting valid branch instruction after `bnd'"));
3550 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3551 && flag_code
== CODE_64BIT
3552 && i
.prefix
[ADDR_PREFIX
])
3553 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3555 /* Insert BND prefix. */
3557 && i
.tm
.opcode_modifier
.bndprefixok
3558 && !i
.prefix
[BND_PREFIX
])
3559 add_prefix (BND_PREFIX_OPCODE
);
3561 /* Check string instruction segment overrides. */
3562 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3564 if (!check_string ())
3566 i
.disp_operands
= 0;
3569 if (!process_suffix ())
3572 /* Update operand types. */
3573 for (j
= 0; j
< i
.operands
; j
++)
3574 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3576 /* Make still unresolved immediate matches conform to size of immediate
3577 given in i.suffix. */
3578 if (!finalize_imm ())
3581 if (i
.types
[0].bitfield
.imm1
)
3582 i
.imm_operands
= 0; /* kludge for shift insns. */
3584 /* We only need to check those implicit registers for instructions
3585 with 3 operands or less. */
3586 if (i
.operands
<= 3)
3587 for (j
= 0; j
< i
.operands
; j
++)
3588 if (i
.types
[j
].bitfield
.inoutportreg
3589 || i
.types
[j
].bitfield
.shiftcount
3590 || i
.types
[j
].bitfield
.acc
3591 || i
.types
[j
].bitfield
.floatacc
)
3594 /* ImmExt should be processed after SSE2AVX. */
3595 if (!i
.tm
.opcode_modifier
.sse2avx
3596 && i
.tm
.opcode_modifier
.immext
)
3599 /* For insns with operands there are more diddles to do to the opcode. */
3602 if (!process_operands ())
3605 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3607 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3608 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3611 if (i
.tm
.opcode_modifier
.vex
)
3612 build_vex_prefix (t
);
3614 if (i
.tm
.opcode_modifier
.evex
)
3615 build_evex_prefix ();
3617 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3618 instructions may define INT_OPCODE as well, so avoid this corner
3619 case for those instructions that use MODRM. */
3620 if (i
.tm
.base_opcode
== INT_OPCODE
3621 && !i
.tm
.opcode_modifier
.modrm
3622 && i
.op
[0].imms
->X_add_number
== 3)
3624 i
.tm
.base_opcode
= INT3_OPCODE
;
3628 if ((i
.tm
.opcode_modifier
.jump
3629 || i
.tm
.opcode_modifier
.jumpbyte
3630 || i
.tm
.opcode_modifier
.jumpdword
)
3631 && i
.op
[0].disps
->X_op
== O_constant
)
3633 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3634 the absolute address given by the constant. Since ix86 jumps and
3635 calls are pc relative, we need to generate a reloc. */
3636 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3637 i
.op
[0].disps
->X_op
= O_symbol
;
3640 if (i
.tm
.opcode_modifier
.rex64
)
3643 /* For 8 bit registers we need an empty rex prefix. Also if the
3644 instruction already has a prefix, we need to convert old
3645 registers to new ones. */
3647 if ((i
.types
[0].bitfield
.reg8
3648 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3649 || (i
.types
[1].bitfield
.reg8
3650 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3651 || ((i
.types
[0].bitfield
.reg8
3652 || i
.types
[1].bitfield
.reg8
)
3657 i
.rex
|= REX_OPCODE
;
3658 for (x
= 0; x
< 2; x
++)
3660 /* Look for 8 bit operand that uses old registers. */
3661 if (i
.types
[x
].bitfield
.reg8
3662 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3664 /* In case it is "hi" register, give up. */
3665 if (i
.op
[x
].regs
->reg_num
> 3)
3666 as_bad (_("can't encode register '%s%s' in an "
3667 "instruction requiring REX prefix."),
3668 register_prefix
, i
.op
[x
].regs
->reg_name
);
3670 /* Otherwise it is equivalent to the extended register.
3671 Since the encoding doesn't change this is merely
3672 cosmetic cleanup for debug output. */
3674 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3680 add_prefix (REX_OPCODE
| i
.rex
);
3682 /* We are ready to output the insn. */
3687 parse_insn (char *line
, char *mnemonic
)
3690 char *token_start
= l
;
3693 const insn_template
*t
;
3699 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3704 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3706 as_bad (_("no such instruction: `%s'"), token_start
);
3711 if (!is_space_char (*l
)
3712 && *l
!= END_OF_INSN
3714 || (*l
!= PREFIX_SEPARATOR
3717 as_bad (_("invalid character %s in mnemonic"),
3718 output_invalid (*l
));
3721 if (token_start
== l
)
3723 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3724 as_bad (_("expecting prefix; got nothing"));
3726 as_bad (_("expecting mnemonic; got nothing"));
3730 /* Look up instruction (or prefix) via hash table. */
3731 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3733 if (*l
!= END_OF_INSN
3734 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3735 && current_templates
3736 && current_templates
->start
->opcode_modifier
.isprefix
)
3738 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3740 as_bad ((flag_code
!= CODE_64BIT
3741 ? _("`%s' is only supported in 64-bit mode")
3742 : _("`%s' is not supported in 64-bit mode")),
3743 current_templates
->start
->name
);
3746 /* If we are in 16-bit mode, do not allow addr16 or data16.
3747 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3748 if ((current_templates
->start
->opcode_modifier
.size16
3749 || current_templates
->start
->opcode_modifier
.size32
)
3750 && flag_code
!= CODE_64BIT
3751 && (current_templates
->start
->opcode_modifier
.size32
3752 ^ (flag_code
== CODE_16BIT
)))
3754 as_bad (_("redundant %s prefix"),
3755 current_templates
->start
->name
);
3758 /* Add prefix, checking for repeated prefixes. */
3759 switch (add_prefix (current_templates
->start
->base_opcode
))
3764 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3765 i
.hle_prefix
= current_templates
->start
->name
;
3766 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3767 i
.bnd_prefix
= current_templates
->start
->name
;
3769 i
.rep_prefix
= current_templates
->start
->name
;
3774 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3781 if (!current_templates
)
3783 /* Check if we should swap operand or force 32bit displacement in
3785 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3787 else if (mnem_p
- 3 == dot_p
3790 i
.disp_encoding
= disp_encoding_8bit
;
3791 else if (mnem_p
- 4 == dot_p
3795 i
.disp_encoding
= disp_encoding_32bit
;
3800 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3803 if (!current_templates
)
3806 /* See if we can get a match by trimming off a suffix. */
3809 case WORD_MNEM_SUFFIX
:
3810 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3811 i
.suffix
= SHORT_MNEM_SUFFIX
;
3813 case BYTE_MNEM_SUFFIX
:
3814 case QWORD_MNEM_SUFFIX
:
3815 i
.suffix
= mnem_p
[-1];
3817 current_templates
= (const templates
*) hash_find (op_hash
,
3820 case SHORT_MNEM_SUFFIX
:
3821 case LONG_MNEM_SUFFIX
:
3824 i
.suffix
= mnem_p
[-1];
3826 current_templates
= (const templates
*) hash_find (op_hash
,
3835 if (intel_float_operand (mnemonic
) == 1)
3836 i
.suffix
= SHORT_MNEM_SUFFIX
;
3838 i
.suffix
= LONG_MNEM_SUFFIX
;
3840 current_templates
= (const templates
*) hash_find (op_hash
,
3845 if (!current_templates
)
3847 as_bad (_("no such instruction: `%s'"), token_start
);
3852 if (current_templates
->start
->opcode_modifier
.jump
3853 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3855 /* Check for a branch hint. We allow ",pt" and ",pn" for
3856 predict taken and predict not taken respectively.
3857 I'm not sure that branch hints actually do anything on loop
3858 and jcxz insns (JumpByte) for current Pentium4 chips. They
3859 may work in the future and it doesn't hurt to accept them
3861 if (l
[0] == ',' && l
[1] == 'p')
3865 if (!add_prefix (DS_PREFIX_OPCODE
))
3869 else if (l
[2] == 'n')
3871 if (!add_prefix (CS_PREFIX_OPCODE
))
3877 /* Any other comma loses. */
3880 as_bad (_("invalid character %s in mnemonic"),
3881 output_invalid (*l
));
3885 /* Check if instruction is supported on specified architecture. */
3887 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3889 supported
|= cpu_flags_match (t
);
3890 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3894 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3896 as_bad (flag_code
== CODE_64BIT
3897 ? _("`%s' is not supported in 64-bit mode")
3898 : _("`%s' is only supported in 64-bit mode"),
3899 current_templates
->start
->name
);
3902 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3904 as_bad (_("`%s' is not supported on `%s%s'"),
3905 current_templates
->start
->name
,
3906 cpu_arch_name
? cpu_arch_name
: default_arch
,
3907 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3912 if (!cpu_arch_flags
.bitfield
.cpui386
3913 && (flag_code
!= CODE_16BIT
))
3915 as_warn (_("use .code16 to ensure correct addressing mode"));
3922 parse_operands (char *l
, const char *mnemonic
)
3926 /* 1 if operand is pending after ','. */
3927 unsigned int expecting_operand
= 0;
3929 /* Non-zero if operand parens not balanced. */
3930 unsigned int paren_not_balanced
;
3932 while (*l
!= END_OF_INSN
)
3934 /* Skip optional white space before operand. */
3935 if (is_space_char (*l
))
3937 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3939 as_bad (_("invalid character %s before operand %d"),
3940 output_invalid (*l
),
3944 token_start
= l
; /* after white space */
3945 paren_not_balanced
= 0;
3946 while (paren_not_balanced
|| *l
!= ',')
3948 if (*l
== END_OF_INSN
)
3950 if (paren_not_balanced
)
3953 as_bad (_("unbalanced parenthesis in operand %d."),
3956 as_bad (_("unbalanced brackets in operand %d."),
3961 break; /* we are done */
3963 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3965 as_bad (_("invalid character %s in operand %d"),
3966 output_invalid (*l
),
3973 ++paren_not_balanced
;
3975 --paren_not_balanced
;
3980 ++paren_not_balanced
;
3982 --paren_not_balanced
;
3986 if (l
!= token_start
)
3987 { /* Yes, we've read in another operand. */
3988 unsigned int operand_ok
;
3989 this_operand
= i
.operands
++;
3990 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3991 if (i
.operands
> MAX_OPERANDS
)
3993 as_bad (_("spurious operands; (%d operands/instruction max)"),
3997 /* Now parse operand adding info to 'i' as we go along. */
3998 END_STRING_AND_SAVE (l
);
4002 i386_intel_operand (token_start
,
4003 intel_float_operand (mnemonic
));
4005 operand_ok
= i386_att_operand (token_start
);
4007 RESTORE_END_STRING (l
);
4013 if (expecting_operand
)
4015 expecting_operand_after_comma
:
4016 as_bad (_("expecting operand after ','; got nothing"));
4021 as_bad (_("expecting operand before ','; got nothing"));
4026 /* Now *l must be either ',' or END_OF_INSN. */
4029 if (*++l
== END_OF_INSN
)
4031 /* Just skip it, if it's \n complain. */
4032 goto expecting_operand_after_comma
;
4034 expecting_operand
= 1;
4041 swap_2_operands (int xchg1
, int xchg2
)
4043 union i386_op temp_op
;
4044 i386_operand_type temp_type
;
4045 enum bfd_reloc_code_real temp_reloc
;
4047 temp_type
= i
.types
[xchg2
];
4048 i
.types
[xchg2
] = i
.types
[xchg1
];
4049 i
.types
[xchg1
] = temp_type
;
4050 temp_op
= i
.op
[xchg2
];
4051 i
.op
[xchg2
] = i
.op
[xchg1
];
4052 i
.op
[xchg1
] = temp_op
;
4053 temp_reloc
= i
.reloc
[xchg2
];
4054 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4055 i
.reloc
[xchg1
] = temp_reloc
;
4059 if (i
.mask
->operand
== xchg1
)
4060 i
.mask
->operand
= xchg2
;
4061 else if (i
.mask
->operand
== xchg2
)
4062 i
.mask
->operand
= xchg1
;
4066 if (i
.broadcast
->operand
== xchg1
)
4067 i
.broadcast
->operand
= xchg2
;
4068 else if (i
.broadcast
->operand
== xchg2
)
4069 i
.broadcast
->operand
= xchg1
;
4073 if (i
.rounding
->operand
== xchg1
)
4074 i
.rounding
->operand
= xchg2
;
4075 else if (i
.rounding
->operand
== xchg2
)
4076 i
.rounding
->operand
= xchg1
;
4081 swap_operands (void)
4087 swap_2_operands (1, i
.operands
- 2);
4090 swap_2_operands (0, i
.operands
- 1);
4096 if (i
.mem_operands
== 2)
4098 const seg_entry
*temp_seg
;
4099 temp_seg
= i
.seg
[0];
4100 i
.seg
[0] = i
.seg
[1];
4101 i
.seg
[1] = temp_seg
;
4105 /* Try to ensure constant immediates are represented in the smallest
4110 char guess_suffix
= 0;
4114 guess_suffix
= i
.suffix
;
4115 else if (i
.reg_operands
)
4117 /* Figure out a suffix from the last register operand specified.
4118 We can't do this properly yet, ie. excluding InOutPortReg,
4119 but the following works for instructions with immediates.
4120 In any case, we can't set i.suffix yet. */
4121 for (op
= i
.operands
; --op
>= 0;)
4122 if (i
.types
[op
].bitfield
.reg8
)
4124 guess_suffix
= BYTE_MNEM_SUFFIX
;
4127 else if (i
.types
[op
].bitfield
.reg16
)
4129 guess_suffix
= WORD_MNEM_SUFFIX
;
4132 else if (i
.types
[op
].bitfield
.reg32
)
4134 guess_suffix
= LONG_MNEM_SUFFIX
;
4137 else if (i
.types
[op
].bitfield
.reg64
)
4139 guess_suffix
= QWORD_MNEM_SUFFIX
;
4143 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4144 guess_suffix
= WORD_MNEM_SUFFIX
;
4146 for (op
= i
.operands
; --op
>= 0;)
4147 if (operand_type_check (i
.types
[op
], imm
))
4149 switch (i
.op
[op
].imms
->X_op
)
4152 /* If a suffix is given, this operand may be shortened. */
4153 switch (guess_suffix
)
4155 case LONG_MNEM_SUFFIX
:
4156 i
.types
[op
].bitfield
.imm32
= 1;
4157 i
.types
[op
].bitfield
.imm64
= 1;
4159 case WORD_MNEM_SUFFIX
:
4160 i
.types
[op
].bitfield
.imm16
= 1;
4161 i
.types
[op
].bitfield
.imm32
= 1;
4162 i
.types
[op
].bitfield
.imm32s
= 1;
4163 i
.types
[op
].bitfield
.imm64
= 1;
4165 case BYTE_MNEM_SUFFIX
:
4166 i
.types
[op
].bitfield
.imm8
= 1;
4167 i
.types
[op
].bitfield
.imm8s
= 1;
4168 i
.types
[op
].bitfield
.imm16
= 1;
4169 i
.types
[op
].bitfield
.imm32
= 1;
4170 i
.types
[op
].bitfield
.imm32s
= 1;
4171 i
.types
[op
].bitfield
.imm64
= 1;
4175 /* If this operand is at most 16 bits, convert it
4176 to a signed 16 bit number before trying to see
4177 whether it will fit in an even smaller size.
4178 This allows a 16-bit operand such as $0xffe0 to
4179 be recognised as within Imm8S range. */
4180 if ((i
.types
[op
].bitfield
.imm16
)
4181 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4183 i
.op
[op
].imms
->X_add_number
=
4184 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4186 if ((i
.types
[op
].bitfield
.imm32
)
4187 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4190 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4191 ^ ((offsetT
) 1 << 31))
4192 - ((offsetT
) 1 << 31));
4195 = operand_type_or (i
.types
[op
],
4196 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4198 /* We must avoid matching of Imm32 templates when 64bit
4199 only immediate is available. */
4200 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4201 i
.types
[op
].bitfield
.imm32
= 0;
4208 /* Symbols and expressions. */
4210 /* Convert symbolic operand to proper sizes for matching, but don't
4211 prevent matching a set of insns that only supports sizes other
4212 than those matching the insn suffix. */
4214 i386_operand_type mask
, allowed
;
4215 const insn_template
*t
;
4217 operand_type_set (&mask
, 0);
4218 operand_type_set (&allowed
, 0);
4220 for (t
= current_templates
->start
;
4221 t
< current_templates
->end
;
4223 allowed
= operand_type_or (allowed
,
4224 t
->operand_types
[op
]);
4225 switch (guess_suffix
)
4227 case QWORD_MNEM_SUFFIX
:
4228 mask
.bitfield
.imm64
= 1;
4229 mask
.bitfield
.imm32s
= 1;
4231 case LONG_MNEM_SUFFIX
:
4232 mask
.bitfield
.imm32
= 1;
4234 case WORD_MNEM_SUFFIX
:
4235 mask
.bitfield
.imm16
= 1;
4237 case BYTE_MNEM_SUFFIX
:
4238 mask
.bitfield
.imm8
= 1;
4243 allowed
= operand_type_and (mask
, allowed
);
4244 if (!operand_type_all_zero (&allowed
))
4245 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4252 /* Try to use the smallest displacement type too. */
4254 optimize_disp (void)
4258 for (op
= i
.operands
; --op
>= 0;)
4259 if (operand_type_check (i
.types
[op
], disp
))
4261 if (i
.op
[op
].disps
->X_op
== O_constant
)
4263 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4265 if (i
.types
[op
].bitfield
.disp16
4266 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4268 /* If this operand is at most 16 bits, convert
4269 to a signed 16 bit number and don't use 64bit
4271 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4272 i
.types
[op
].bitfield
.disp64
= 0;
4274 if (i
.types
[op
].bitfield
.disp32
4275 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4277 /* If this operand is at most 32 bits, convert
4278 to a signed 32 bit number and don't use 64bit
4280 op_disp
&= (((offsetT
) 2 << 31) - 1);
4281 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4282 i
.types
[op
].bitfield
.disp64
= 0;
4284 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4286 i
.types
[op
].bitfield
.disp8
= 0;
4287 i
.types
[op
].bitfield
.disp16
= 0;
4288 i
.types
[op
].bitfield
.disp32
= 0;
4289 i
.types
[op
].bitfield
.disp32s
= 0;
4290 i
.types
[op
].bitfield
.disp64
= 0;
4294 else if (flag_code
== CODE_64BIT
)
4296 if (fits_in_signed_long (op_disp
))
4298 i
.types
[op
].bitfield
.disp64
= 0;
4299 i
.types
[op
].bitfield
.disp32s
= 1;
4301 if (i
.prefix
[ADDR_PREFIX
]
4302 && fits_in_unsigned_long (op_disp
))
4303 i
.types
[op
].bitfield
.disp32
= 1;
4305 if ((i
.types
[op
].bitfield
.disp32
4306 || i
.types
[op
].bitfield
.disp32s
4307 || i
.types
[op
].bitfield
.disp16
)
4308 && fits_in_signed_byte (op_disp
))
4309 i
.types
[op
].bitfield
.disp8
= 1;
4311 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4312 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4314 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4315 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4316 i
.types
[op
].bitfield
.disp8
= 0;
4317 i
.types
[op
].bitfield
.disp16
= 0;
4318 i
.types
[op
].bitfield
.disp32
= 0;
4319 i
.types
[op
].bitfield
.disp32s
= 0;
4320 i
.types
[op
].bitfield
.disp64
= 0;
4323 /* We only support 64bit displacement on constants. */
4324 i
.types
[op
].bitfield
.disp64
= 0;
4328 /* Check if operands are valid for the instruction. */
4331 check_VecOperands (const insn_template
*t
)
4335 /* Without VSIB byte, we can't have a vector register for index. */
4336 if (!t
->opcode_modifier
.vecsib
4338 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4339 || i
.index_reg
->reg_type
.bitfield
.regymm
4340 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4342 i
.error
= unsupported_vector_index_register
;
4346 /* For VSIB byte, we need a vector register for index, and all vector
4347 registers must be distinct. */
4348 if (t
->opcode_modifier
.vecsib
)
4351 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4352 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4353 || (t
->opcode_modifier
.vecsib
== VecSIB256
4354 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4355 || (t
->opcode_modifier
.vecsib
== VecSIB512
4356 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4358 i
.error
= invalid_vsib_address
;
4362 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4363 if (i
.reg_operands
== 2 && !i
.mask
)
4365 gas_assert (i
.types
[0].bitfield
.regxmm
4366 || i
.types
[0].bitfield
.regymm
4367 || i
.types
[0].bitfield
.regzmm
);
4368 gas_assert (i
.types
[2].bitfield
.regxmm
4369 || i
.types
[2].bitfield
.regymm
4370 || i
.types
[2].bitfield
.regzmm
);
4371 if (operand_check
== check_none
)
4373 if (register_number (i
.op
[0].regs
)
4374 != register_number (i
.index_reg
)
4375 && register_number (i
.op
[2].regs
)
4376 != register_number (i
.index_reg
)
4377 && register_number (i
.op
[0].regs
)
4378 != register_number (i
.op
[2].regs
))
4380 if (operand_check
== check_error
)
4382 i
.error
= invalid_vector_register_set
;
4385 as_warn (_("mask, index, and destination registers should be distinct"));
4389 /* Check if broadcast is supported by the instruction and is applied
4390 to the memory operand. */
4393 int broadcasted_opnd_size
;
4395 /* Check if specified broadcast is supported in this instruction,
4396 and it's applied to memory operand of DWORD or QWORD type,
4397 depending on VecESize. */
4398 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4399 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4400 || (t
->opcode_modifier
.vecesize
== 0
4401 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4402 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4403 || (t
->opcode_modifier
.vecesize
== 1
4404 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4405 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4408 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4409 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4410 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4411 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4412 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4416 if ((broadcasted_opnd_size
== 256
4417 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4418 || (broadcasted_opnd_size
== 512
4419 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4422 i
.error
= unsupported_broadcast
;
4426 /* If broadcast is supported in this instruction, we need to check if
4427 operand of one-element size isn't specified without broadcast. */
4428 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4430 /* Find memory operand. */
4431 for (op
= 0; op
< i
.operands
; op
++)
4432 if (operand_type_check (i
.types
[op
], anymem
))
4434 gas_assert (op
< i
.operands
);
4435 /* Check size of the memory operand. */
4436 if ((t
->opcode_modifier
.vecesize
== 0
4437 && i
.types
[op
].bitfield
.dword
)
4438 || (t
->opcode_modifier
.vecesize
== 1
4439 && i
.types
[op
].bitfield
.qword
))
4441 i
.error
= broadcast_needed
;
4446 /* Check if requested masking is supported. */
4448 && (!t
->opcode_modifier
.masking
4450 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4452 i
.error
= unsupported_masking
;
4456 /* Check if masking is applied to dest operand. */
4457 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4459 i
.error
= mask_not_on_destination
;
4463 /* Check if default mask is allowed. */
4464 if (t
->opcode_modifier
.nodefmask
4465 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4467 i
.error
= no_default_mask
;
4474 if ((i
.rounding
->type
!= saeonly
4475 && !t
->opcode_modifier
.staticrounding
)
4476 || (i
.rounding
->type
== saeonly
4477 && (t
->opcode_modifier
.staticrounding
4478 || !t
->opcode_modifier
.sae
)))
4480 i
.error
= unsupported_rc_sae
;
4483 /* If the instruction has several immediate operands and one of
4484 them is rounding, the rounding operand should be the last
4485 immediate operand. */
4486 if (i
.imm_operands
> 1
4487 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4489 i
.error
= rc_sae_operand_not_last_imm
;
4494 /* Check vector Disp8 operand. */
4495 if (t
->opcode_modifier
.disp8memshift
)
4498 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4500 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4502 for (op
= 0; op
< i
.operands
; op
++)
4503 if (operand_type_check (i
.types
[op
], disp
)
4504 && i
.op
[op
].disps
->X_op
== O_constant
)
4506 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4507 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4508 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4511 i
.types
[op
].bitfield
.vec_disp8
= 1;
4514 /* Vector insn can only have Vec_Disp8/Disp32 in
4515 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4517 i
.types
[op
].bitfield
.disp8
= 0;
4518 if (flag_code
!= CODE_16BIT
)
4519 i
.types
[op
].bitfield
.disp16
= 0;
4522 else if (flag_code
!= CODE_16BIT
)
4524 /* One form of this instruction supports vector Disp8.
4525 Try vector Disp8 if we need to use Disp32. */
4526 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4528 i
.error
= try_vector_disp8
;
4540 /* Check if operands are valid for the instruction. Update VEX
4544 VEX_check_operands (const insn_template
*t
)
4546 /* VREX is only valid with EVEX prefix. */
4547 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4549 i
.error
= invalid_register_operand
;
4553 if (!t
->opcode_modifier
.vex
)
4556 /* Only check VEX_Imm4, which must be the first operand. */
4557 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4559 if (i
.op
[0].imms
->X_op
!= O_constant
4560 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4566 /* Turn off Imm8 so that update_imm won't complain. */
4567 i
.types
[0] = vec_imm4
;
4573 static const insn_template
*
4574 match_template (void)
4576 /* Points to template once we've found it. */
4577 const insn_template
*t
;
4578 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4579 i386_operand_type overlap4
;
4580 unsigned int found_reverse_match
;
4581 i386_opcode_modifier suffix_check
;
4582 i386_operand_type operand_types
[MAX_OPERANDS
];
4583 int addr_prefix_disp
;
4585 unsigned int found_cpu_match
;
4586 unsigned int check_register
;
4587 enum i386_error specific_error
= 0;
4589 #if MAX_OPERANDS != 5
4590 # error "MAX_OPERANDS must be 5."
4593 found_reverse_match
= 0;
4594 addr_prefix_disp
= -1;
4596 memset (&suffix_check
, 0, sizeof (suffix_check
));
4597 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4598 suffix_check
.no_bsuf
= 1;
4599 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4600 suffix_check
.no_wsuf
= 1;
4601 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4602 suffix_check
.no_ssuf
= 1;
4603 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4604 suffix_check
.no_lsuf
= 1;
4605 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4606 suffix_check
.no_qsuf
= 1;
4607 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4608 suffix_check
.no_ldsuf
= 1;
4610 /* Must have right number of operands. */
4611 i
.error
= number_of_operands_mismatch
;
4613 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4615 addr_prefix_disp
= -1;
4617 if (i
.operands
!= t
->operands
)
4620 /* Check processor support. */
4621 i
.error
= unsupported
;
4622 found_cpu_match
= (cpu_flags_match (t
)
4623 == CPU_FLAGS_PERFECT_MATCH
);
4624 if (!found_cpu_match
)
4627 /* Check old gcc support. */
4628 i
.error
= old_gcc_only
;
4629 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4632 /* Check AT&T mnemonic. */
4633 i
.error
= unsupported_with_intel_mnemonic
;
4634 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4637 /* Check AT&T/Intel syntax. */
4638 i
.error
= unsupported_syntax
;
4639 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4640 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4643 /* Check the suffix, except for some instructions in intel mode. */
4644 i
.error
= invalid_instruction_suffix
;
4645 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4646 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4647 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4648 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4649 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4650 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4651 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4654 if (!operand_size_match (t
))
4657 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4658 operand_types
[j
] = t
->operand_types
[j
];
4660 /* In general, don't allow 64-bit operands in 32-bit mode. */
4661 if (i
.suffix
== QWORD_MNEM_SUFFIX
4662 && flag_code
!= CODE_64BIT
4664 ? (!t
->opcode_modifier
.ignoresize
4665 && !intel_float_operand (t
->name
))
4666 : intel_float_operand (t
->name
) != 2)
4667 && ((!operand_types
[0].bitfield
.regmmx
4668 && !operand_types
[0].bitfield
.regxmm
4669 && !operand_types
[0].bitfield
.regymm
4670 && !operand_types
[0].bitfield
.regzmm
)
4671 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4672 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
4673 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
4674 && !!operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4675 && (t
->base_opcode
!= 0x0fc7
4676 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4679 /* In general, don't allow 32-bit operands on pre-386. */
4680 else if (i
.suffix
== LONG_MNEM_SUFFIX
4681 && !cpu_arch_flags
.bitfield
.cpui386
4683 ? (!t
->opcode_modifier
.ignoresize
4684 && !intel_float_operand (t
->name
))
4685 : intel_float_operand (t
->name
) != 2)
4686 && ((!operand_types
[0].bitfield
.regmmx
4687 && !operand_types
[0].bitfield
.regxmm
)
4688 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4689 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4692 /* Do not verify operands when there are none. */
4696 /* We've found a match; break out of loop. */
4700 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4701 into Disp32/Disp16/Disp32 operand. */
4702 if (i
.prefix
[ADDR_PREFIX
] != 0)
4704 /* There should be only one Disp operand. */
4708 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4710 if (operand_types
[j
].bitfield
.disp16
)
4712 addr_prefix_disp
= j
;
4713 operand_types
[j
].bitfield
.disp32
= 1;
4714 operand_types
[j
].bitfield
.disp16
= 0;
4720 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4722 if (operand_types
[j
].bitfield
.disp32
)
4724 addr_prefix_disp
= j
;
4725 operand_types
[j
].bitfield
.disp32
= 0;
4726 operand_types
[j
].bitfield
.disp16
= 1;
4732 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4734 if (operand_types
[j
].bitfield
.disp64
)
4736 addr_prefix_disp
= j
;
4737 operand_types
[j
].bitfield
.disp64
= 0;
4738 operand_types
[j
].bitfield
.disp32
= 1;
4746 /* We check register size if needed. */
4747 check_register
= t
->opcode_modifier
.checkregsize
;
4748 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4749 switch (t
->operands
)
4752 if (!operand_type_match (overlap0
, i
.types
[0]))
4756 /* xchg %eax, %eax is a special case. It is an aliase for nop
4757 only in 32bit mode and we can use opcode 0x90. In 64bit
4758 mode, we can't use 0x90 for xchg %eax, %eax since it should
4759 zero-extend %eax to %rax. */
4760 if (flag_code
== CODE_64BIT
4761 && t
->base_opcode
== 0x90
4762 && operand_type_equal (&i
.types
[0], &acc32
)
4763 && operand_type_equal (&i
.types
[1], &acc32
))
4767 /* If we swap operand in encoding, we either match
4768 the next one or reverse direction of operands. */
4769 if (t
->opcode_modifier
.s
)
4771 else if (t
->opcode_modifier
.d
)
4776 /* If we swap operand in encoding, we match the next one. */
4777 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4781 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4782 if (!operand_type_match (overlap0
, i
.types
[0])
4783 || !operand_type_match (overlap1
, i
.types
[1])
4785 && !operand_type_register_match (overlap0
, i
.types
[0],
4787 overlap1
, i
.types
[1],
4790 /* Check if other direction is valid ... */
4791 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4795 /* Try reversing direction of operands. */
4796 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4797 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4798 if (!operand_type_match (overlap0
, i
.types
[0])
4799 || !operand_type_match (overlap1
, i
.types
[1])
4801 && !operand_type_register_match (overlap0
,
4808 /* Does not match either direction. */
4811 /* found_reverse_match holds which of D or FloatDR
4813 if (t
->opcode_modifier
.d
)
4814 found_reverse_match
= Opcode_D
;
4815 else if (t
->opcode_modifier
.floatd
)
4816 found_reverse_match
= Opcode_FloatD
;
4818 found_reverse_match
= 0;
4819 if (t
->opcode_modifier
.floatr
)
4820 found_reverse_match
|= Opcode_FloatR
;
4824 /* Found a forward 2 operand match here. */
4825 switch (t
->operands
)
4828 overlap4
= operand_type_and (i
.types
[4],
4831 overlap3
= operand_type_and (i
.types
[3],
4834 overlap2
= operand_type_and (i
.types
[2],
4839 switch (t
->operands
)
4842 if (!operand_type_match (overlap4
, i
.types
[4])
4843 || !operand_type_register_match (overlap3
,
4851 if (!operand_type_match (overlap3
, i
.types
[3])
4853 && !operand_type_register_match (overlap2
,
4861 /* Here we make use of the fact that there are no
4862 reverse match 3 operand instructions, and all 3
4863 operand instructions only need to be checked for
4864 register consistency between operands 2 and 3. */
4865 if (!operand_type_match (overlap2
, i
.types
[2])
4867 && !operand_type_register_match (overlap1
,
4877 /* Found either forward/reverse 2, 3 or 4 operand match here:
4878 slip through to break. */
4880 if (!found_cpu_match
)
4882 found_reverse_match
= 0;
4886 /* Check if vector and VEX operands are valid. */
4887 if (check_VecOperands (t
) || VEX_check_operands (t
))
4889 specific_error
= i
.error
;
4893 /* We've found a match; break out of loop. */
4897 if (t
== current_templates
->end
)
4899 /* We found no match. */
4900 const char *err_msg
;
4901 switch (specific_error
? specific_error
: i
.error
)
4905 case operand_size_mismatch
:
4906 err_msg
= _("operand size mismatch");
4908 case operand_type_mismatch
:
4909 err_msg
= _("operand type mismatch");
4911 case register_type_mismatch
:
4912 err_msg
= _("register type mismatch");
4914 case number_of_operands_mismatch
:
4915 err_msg
= _("number of operands mismatch");
4917 case invalid_instruction_suffix
:
4918 err_msg
= _("invalid instruction suffix");
4921 err_msg
= _("constant doesn't fit in 4 bits");
4924 err_msg
= _("only supported with old gcc");
4926 case unsupported_with_intel_mnemonic
:
4927 err_msg
= _("unsupported with Intel mnemonic");
4929 case unsupported_syntax
:
4930 err_msg
= _("unsupported syntax");
4933 as_bad (_("unsupported instruction `%s'"),
4934 current_templates
->start
->name
);
4936 case invalid_vsib_address
:
4937 err_msg
= _("invalid VSIB address");
4939 case invalid_vector_register_set
:
4940 err_msg
= _("mask, index, and destination registers must be distinct");
4942 case unsupported_vector_index_register
:
4943 err_msg
= _("unsupported vector index register");
4945 case unsupported_broadcast
:
4946 err_msg
= _("unsupported broadcast");
4948 case broadcast_not_on_src_operand
:
4949 err_msg
= _("broadcast not on source memory operand");
4951 case broadcast_needed
:
4952 err_msg
= _("broadcast is needed for operand of such type");
4954 case unsupported_masking
:
4955 err_msg
= _("unsupported masking");
4957 case mask_not_on_destination
:
4958 err_msg
= _("mask not on destination operand");
4960 case no_default_mask
:
4961 err_msg
= _("default mask isn't allowed");
4963 case unsupported_rc_sae
:
4964 err_msg
= _("unsupported static rounding/sae");
4966 case rc_sae_operand_not_last_imm
:
4968 err_msg
= _("RC/SAE operand must precede immediate operands");
4970 err_msg
= _("RC/SAE operand must follow immediate operands");
4972 case invalid_register_operand
:
4973 err_msg
= _("invalid register operand");
4976 as_bad (_("%s for `%s'"), err_msg
,
4977 current_templates
->start
->name
);
4981 if (!quiet_warnings
)
4984 && (i
.types
[0].bitfield
.jumpabsolute
4985 != operand_types
[0].bitfield
.jumpabsolute
))
4987 as_warn (_("indirect %s without `*'"), t
->name
);
4990 if (t
->opcode_modifier
.isprefix
4991 && t
->opcode_modifier
.ignoresize
)
4993 /* Warn them that a data or address size prefix doesn't
4994 affect assembly of the next line of code. */
4995 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4999 /* Copy the template we found. */
5002 if (addr_prefix_disp
!= -1)
5003 i
.tm
.operand_types
[addr_prefix_disp
]
5004 = operand_types
[addr_prefix_disp
];
5006 if (found_reverse_match
)
5008 /* If we found a reverse match we must alter the opcode
5009 direction bit. found_reverse_match holds bits to change
5010 (different for int & float insns). */
5012 i
.tm
.base_opcode
^= found_reverse_match
;
5014 i
.tm
.operand_types
[0] = operand_types
[1];
5015 i
.tm
.operand_types
[1] = operand_types
[0];
5024 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5025 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5027 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5029 as_bad (_("`%s' operand %d must use `%ses' segment"),
5035 /* There's only ever one segment override allowed per instruction.
5036 This instruction possibly has a legal segment override on the
5037 second operand, so copy the segment to where non-string
5038 instructions store it, allowing common code. */
5039 i
.seg
[0] = i
.seg
[1];
5041 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5043 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5045 as_bad (_("`%s' operand %d must use `%ses' segment"),
5056 process_suffix (void)
5058 /* If matched instruction specifies an explicit instruction mnemonic
5060 if (i
.tm
.opcode_modifier
.size16
)
5061 i
.suffix
= WORD_MNEM_SUFFIX
;
5062 else if (i
.tm
.opcode_modifier
.size32
)
5063 i
.suffix
= LONG_MNEM_SUFFIX
;
5064 else if (i
.tm
.opcode_modifier
.size64
)
5065 i
.suffix
= QWORD_MNEM_SUFFIX
;
5066 else if (i
.reg_operands
)
5068 /* If there's no instruction mnemonic suffix we try to invent one
5069 based on register operands. */
5072 /* We take i.suffix from the last register operand specified,
5073 Destination register type is more significant than source
5074 register type. crc32 in SSE4.2 prefers source register
5076 if (i
.tm
.base_opcode
== 0xf20f38f1)
5078 if (i
.types
[0].bitfield
.reg16
)
5079 i
.suffix
= WORD_MNEM_SUFFIX
;
5080 else if (i
.types
[0].bitfield
.reg32
)
5081 i
.suffix
= LONG_MNEM_SUFFIX
;
5082 else if (i
.types
[0].bitfield
.reg64
)
5083 i
.suffix
= QWORD_MNEM_SUFFIX
;
5085 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5087 if (i
.types
[0].bitfield
.reg8
)
5088 i
.suffix
= BYTE_MNEM_SUFFIX
;
5095 if (i
.tm
.base_opcode
== 0xf20f38f1
5096 || i
.tm
.base_opcode
== 0xf20f38f0)
5098 /* We have to know the operand size for crc32. */
5099 as_bad (_("ambiguous memory operand size for `%s`"),
5104 for (op
= i
.operands
; --op
>= 0;)
5105 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5107 if (i
.types
[op
].bitfield
.reg8
)
5109 i
.suffix
= BYTE_MNEM_SUFFIX
;
5112 else if (i
.types
[op
].bitfield
.reg16
)
5114 i
.suffix
= WORD_MNEM_SUFFIX
;
5117 else if (i
.types
[op
].bitfield
.reg32
)
5119 i
.suffix
= LONG_MNEM_SUFFIX
;
5122 else if (i
.types
[op
].bitfield
.reg64
)
5124 i
.suffix
= QWORD_MNEM_SUFFIX
;
5130 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5133 && i
.tm
.opcode_modifier
.ignoresize
5134 && i
.tm
.opcode_modifier
.no_bsuf
)
5136 else if (!check_byte_reg ())
5139 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5142 && i
.tm
.opcode_modifier
.ignoresize
5143 && i
.tm
.opcode_modifier
.no_lsuf
)
5145 else if (!check_long_reg ())
5148 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5151 && i
.tm
.opcode_modifier
.ignoresize
5152 && i
.tm
.opcode_modifier
.no_qsuf
)
5154 else if (!check_qword_reg ())
5157 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5160 && i
.tm
.opcode_modifier
.ignoresize
5161 && i
.tm
.opcode_modifier
.no_wsuf
)
5163 else if (!check_word_reg ())
5166 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5167 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5168 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5170 /* Skip if the instruction has x/y/z suffix. match_template
5171 should check if it is a valid suffix. */
5173 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5174 /* Do nothing if the instruction is going to ignore the prefix. */
5179 else if (i
.tm
.opcode_modifier
.defaultsize
5181 /* exclude fldenv/frstor/fsave/fstenv */
5182 && i
.tm
.opcode_modifier
.no_ssuf
)
5184 i
.suffix
= stackop_size
;
5186 else if (intel_syntax
5188 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5189 || i
.tm
.opcode_modifier
.jumpbyte
5190 || i
.tm
.opcode_modifier
.jumpintersegment
5191 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5192 && i
.tm
.extension_opcode
<= 3)))
5197 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5199 i
.suffix
= QWORD_MNEM_SUFFIX
;
5203 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5204 i
.suffix
= LONG_MNEM_SUFFIX
;
5207 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5208 i
.suffix
= WORD_MNEM_SUFFIX
;
5217 if (i
.tm
.opcode_modifier
.w
)
5219 as_bad (_("no instruction mnemonic suffix given and "
5220 "no register operands; can't size instruction"));
5226 unsigned int suffixes
;
5228 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5229 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5231 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5233 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5235 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5237 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5240 /* There are more than suffix matches. */
5241 if (i
.tm
.opcode_modifier
.w
5242 || ((suffixes
& (suffixes
- 1))
5243 && !i
.tm
.opcode_modifier
.defaultsize
5244 && !i
.tm
.opcode_modifier
.ignoresize
))
5246 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5252 /* Change the opcode based on the operand size given by i.suffix;
5253 We don't need to change things for byte insns. */
5256 && i
.suffix
!= BYTE_MNEM_SUFFIX
5257 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5258 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5259 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5261 /* It's not a byte, select word/dword operation. */
5262 if (i
.tm
.opcode_modifier
.w
)
5264 if (i
.tm
.opcode_modifier
.shortform
)
5265 i
.tm
.base_opcode
|= 8;
5267 i
.tm
.base_opcode
|= 1;
5270 /* Now select between word & dword operations via the operand
5271 size prefix, except for instructions that will ignore this
5273 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5275 /* The address size override prefix changes the size of the
5277 if ((flag_code
== CODE_32BIT
5278 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5279 || (flag_code
!= CODE_32BIT
5280 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5281 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5284 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5285 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5286 && !i
.tm
.opcode_modifier
.ignoresize
5287 && !i
.tm
.opcode_modifier
.floatmf
5288 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5289 || (flag_code
== CODE_64BIT
5290 && i
.tm
.opcode_modifier
.jumpbyte
)))
5292 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5294 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5295 prefix
= ADDR_PREFIX_OPCODE
;
5297 if (!add_prefix (prefix
))
5301 /* Set mode64 for an operand. */
5302 if (i
.suffix
== QWORD_MNEM_SUFFIX
5303 && flag_code
== CODE_64BIT
5304 && !i
.tm
.opcode_modifier
.norex64
)
5306 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5307 need rex64. cmpxchg8b is also a special case. */
5308 if (! (i
.operands
== 2
5309 && i
.tm
.base_opcode
== 0x90
5310 && i
.tm
.extension_opcode
== None
5311 && operand_type_equal (&i
.types
[0], &acc64
)
5312 && operand_type_equal (&i
.types
[1], &acc64
))
5313 && ! (i
.operands
== 1
5314 && i
.tm
.base_opcode
== 0xfc7
5315 && i
.tm
.extension_opcode
== 1
5316 && !operand_type_check (i
.types
[0], reg
)
5317 && operand_type_check (i
.types
[0], anymem
)))
5321 /* Size floating point instruction. */
5322 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5323 if (i
.tm
.opcode_modifier
.floatmf
)
5324 i
.tm
.base_opcode
^= 4;
5331 check_byte_reg (void)
5335 for (op
= i
.operands
; --op
>= 0;)
5337 /* If this is an eight bit register, it's OK. If it's the 16 or
5338 32 bit version of an eight bit register, we will just use the
5339 low portion, and that's OK too. */
5340 if (i
.types
[op
].bitfield
.reg8
)
5343 /* I/O port address operands are OK too. */
5344 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5347 /* crc32 doesn't generate this warning. */
5348 if (i
.tm
.base_opcode
== 0xf20f38f0)
5351 if ((i
.types
[op
].bitfield
.reg16
5352 || i
.types
[op
].bitfield
.reg32
5353 || i
.types
[op
].bitfield
.reg64
)
5354 && i
.op
[op
].regs
->reg_num
< 4
5355 /* Prohibit these changes in 64bit mode, since the lowering
5356 would be more complicated. */
5357 && flag_code
!= CODE_64BIT
)
5359 #if REGISTER_WARNINGS
5360 if (!quiet_warnings
)
5361 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5363 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5364 ? REGNAM_AL
- REGNAM_AX
5365 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5367 i
.op
[op
].regs
->reg_name
,
5372 /* Any other register is bad. */
5373 if (i
.types
[op
].bitfield
.reg16
5374 || i
.types
[op
].bitfield
.reg32
5375 || i
.types
[op
].bitfield
.reg64
5376 || i
.types
[op
].bitfield
.regmmx
5377 || i
.types
[op
].bitfield
.regxmm
5378 || i
.types
[op
].bitfield
.regymm
5379 || i
.types
[op
].bitfield
.regzmm
5380 || i
.types
[op
].bitfield
.sreg2
5381 || i
.types
[op
].bitfield
.sreg3
5382 || i
.types
[op
].bitfield
.control
5383 || i
.types
[op
].bitfield
.debug
5384 || i
.types
[op
].bitfield
.test
5385 || i
.types
[op
].bitfield
.floatreg
5386 || i
.types
[op
].bitfield
.floatacc
)
5388 as_bad (_("`%s%s' not allowed with `%s%c'"),
5390 i
.op
[op
].regs
->reg_name
,
5400 check_long_reg (void)
5404 for (op
= i
.operands
; --op
>= 0;)
5405 /* Reject eight bit registers, except where the template requires
5406 them. (eg. movzb) */
5407 if (i
.types
[op
].bitfield
.reg8
5408 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5409 || i
.tm
.operand_types
[op
].bitfield
.reg32
5410 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5412 as_bad (_("`%s%s' not allowed with `%s%c'"),
5414 i
.op
[op
].regs
->reg_name
,
5419 /* Warn if the e prefix on a general reg is missing. */
5420 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5421 && i
.types
[op
].bitfield
.reg16
5422 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5423 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5425 /* Prohibit these changes in the 64bit mode, since the
5426 lowering is more complicated. */
5427 if (flag_code
== CODE_64BIT
)
5429 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5430 register_prefix
, i
.op
[op
].regs
->reg_name
,
5434 #if REGISTER_WARNINGS
5436 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5438 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5440 i
.op
[op
].regs
->reg_name
,
5444 /* Warn if the r prefix on a general reg is missing. */
5445 else if (i
.types
[op
].bitfield
.reg64
5446 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5447 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5450 && i
.tm
.opcode_modifier
.toqword
5451 && !i
.types
[0].bitfield
.regxmm
)
5453 /* Convert to QWORD. We want REX byte. */
5454 i
.suffix
= QWORD_MNEM_SUFFIX
;
5458 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5459 register_prefix
, i
.op
[op
].regs
->reg_name
,
5468 check_qword_reg (void)
5472 for (op
= i
.operands
; --op
>= 0; )
5473 /* Reject eight bit registers, except where the template requires
5474 them. (eg. movzb) */
5475 if (i
.types
[op
].bitfield
.reg8
5476 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5477 || i
.tm
.operand_types
[op
].bitfield
.reg32
5478 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5480 as_bad (_("`%s%s' not allowed with `%s%c'"),
5482 i
.op
[op
].regs
->reg_name
,
5487 /* Warn if the e prefix on a general reg is missing. */
5488 else if ((i
.types
[op
].bitfield
.reg16
5489 || i
.types
[op
].bitfield
.reg32
)
5490 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5491 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5493 /* Prohibit these changes in the 64bit mode, since the
5494 lowering is more complicated. */
5496 && i
.tm
.opcode_modifier
.todword
5497 && !i
.types
[0].bitfield
.regxmm
)
5499 /* Convert to DWORD. We don't want REX byte. */
5500 i
.suffix
= LONG_MNEM_SUFFIX
;
5504 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5505 register_prefix
, i
.op
[op
].regs
->reg_name
,
5514 check_word_reg (void)
5517 for (op
= i
.operands
; --op
>= 0;)
5518 /* Reject eight bit registers, except where the template requires
5519 them. (eg. movzb) */
5520 if (i
.types
[op
].bitfield
.reg8
5521 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5522 || i
.tm
.operand_types
[op
].bitfield
.reg32
5523 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5525 as_bad (_("`%s%s' not allowed with `%s%c'"),
5527 i
.op
[op
].regs
->reg_name
,
5532 /* Warn if the e prefix on a general reg is present. */
5533 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5534 && i
.types
[op
].bitfield
.reg32
5535 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5536 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5538 /* Prohibit these changes in the 64bit mode, since the
5539 lowering is more complicated. */
5540 if (flag_code
== CODE_64BIT
)
5542 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5543 register_prefix
, i
.op
[op
].regs
->reg_name
,
5548 #if REGISTER_WARNINGS
5549 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5551 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5553 i
.op
[op
].regs
->reg_name
,
5561 update_imm (unsigned int j
)
5563 i386_operand_type overlap
= i
.types
[j
];
5564 if ((overlap
.bitfield
.imm8
5565 || overlap
.bitfield
.imm8s
5566 || overlap
.bitfield
.imm16
5567 || overlap
.bitfield
.imm32
5568 || overlap
.bitfield
.imm32s
5569 || overlap
.bitfield
.imm64
)
5570 && !operand_type_equal (&overlap
, &imm8
)
5571 && !operand_type_equal (&overlap
, &imm8s
)
5572 && !operand_type_equal (&overlap
, &imm16
)
5573 && !operand_type_equal (&overlap
, &imm32
)
5574 && !operand_type_equal (&overlap
, &imm32s
)
5575 && !operand_type_equal (&overlap
, &imm64
))
5579 i386_operand_type temp
;
5581 operand_type_set (&temp
, 0);
5582 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5584 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5585 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5587 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5588 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5589 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5591 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5592 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5595 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5598 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5599 || operand_type_equal (&overlap
, &imm16_32
)
5600 || operand_type_equal (&overlap
, &imm16_32s
))
5602 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5607 if (!operand_type_equal (&overlap
, &imm8
)
5608 && !operand_type_equal (&overlap
, &imm8s
)
5609 && !operand_type_equal (&overlap
, &imm16
)
5610 && !operand_type_equal (&overlap
, &imm32
)
5611 && !operand_type_equal (&overlap
, &imm32s
)
5612 && !operand_type_equal (&overlap
, &imm64
))
5614 as_bad (_("no instruction mnemonic suffix given; "
5615 "can't determine immediate size"));
5619 i
.types
[j
] = overlap
;
5629 /* Update the first 2 immediate operands. */
5630 n
= i
.operands
> 2 ? 2 : i
.operands
;
5633 for (j
= 0; j
< n
; j
++)
5634 if (update_imm (j
) == 0)
5637 /* The 3rd operand can't be immediate operand. */
5638 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5645 bad_implicit_operand (int xmm
)
5647 const char *ireg
= xmm
? "xmm0" : "ymm0";
5650 as_bad (_("the last operand of `%s' must be `%s%s'"),
5651 i
.tm
.name
, register_prefix
, ireg
);
5653 as_bad (_("the first operand of `%s' must be `%s%s'"),
5654 i
.tm
.name
, register_prefix
, ireg
);
5659 process_operands (void)
5661 /* Default segment register this instruction will use for memory
5662 accesses. 0 means unknown. This is only for optimizing out
5663 unnecessary segment overrides. */
5664 const seg_entry
*default_seg
= 0;
5666 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5668 unsigned int dupl
= i
.operands
;
5669 unsigned int dest
= dupl
- 1;
5672 /* The destination must be an xmm register. */
5673 gas_assert (i
.reg_operands
5674 && MAX_OPERANDS
> dupl
5675 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5677 if (i
.tm
.opcode_modifier
.firstxmm0
)
5679 /* The first operand is implicit and must be xmm0. */
5680 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5681 if (register_number (i
.op
[0].regs
) != 0)
5682 return bad_implicit_operand (1);
5684 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5686 /* Keep xmm0 for instructions with VEX prefix and 3
5692 /* We remove the first xmm0 and keep the number of
5693 operands unchanged, which in fact duplicates the
5695 for (j
= 1; j
< i
.operands
; j
++)
5697 i
.op
[j
- 1] = i
.op
[j
];
5698 i
.types
[j
- 1] = i
.types
[j
];
5699 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5703 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5705 gas_assert ((MAX_OPERANDS
- 1) > dupl
5706 && (i
.tm
.opcode_modifier
.vexsources
5709 /* Add the implicit xmm0 for instructions with VEX prefix
5711 for (j
= i
.operands
; j
> 0; j
--)
5713 i
.op
[j
] = i
.op
[j
- 1];
5714 i
.types
[j
] = i
.types
[j
- 1];
5715 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5718 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5719 i
.types
[0] = regxmm
;
5720 i
.tm
.operand_types
[0] = regxmm
;
5723 i
.reg_operands
+= 2;
5728 i
.op
[dupl
] = i
.op
[dest
];
5729 i
.types
[dupl
] = i
.types
[dest
];
5730 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5739 i
.op
[dupl
] = i
.op
[dest
];
5740 i
.types
[dupl
] = i
.types
[dest
];
5741 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5744 if (i
.tm
.opcode_modifier
.immext
)
5747 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5751 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5752 gas_assert (i
.reg_operands
5753 && (operand_type_equal (&i
.types
[0], ®xmm
)
5754 || operand_type_equal (&i
.types
[0], ®ymm
)
5755 || operand_type_equal (&i
.types
[0], ®zmm
)));
5756 if (register_number (i
.op
[0].regs
) != 0)
5757 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5759 for (j
= 1; j
< i
.operands
; j
++)
5761 i
.op
[j
- 1] = i
.op
[j
];
5762 i
.types
[j
- 1] = i
.types
[j
];
5764 /* We need to adjust fields in i.tm since they are used by
5765 build_modrm_byte. */
5766 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5773 else if (i
.tm
.opcode_modifier
.regkludge
)
5775 /* The imul $imm, %reg instruction is converted into
5776 imul $imm, %reg, %reg, and the clr %reg instruction
5777 is converted into xor %reg, %reg. */
5779 unsigned int first_reg_op
;
5781 if (operand_type_check (i
.types
[0], reg
))
5785 /* Pretend we saw the extra register operand. */
5786 gas_assert (i
.reg_operands
== 1
5787 && i
.op
[first_reg_op
+ 1].regs
== 0);
5788 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5789 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5794 if (i
.tm
.opcode_modifier
.shortform
)
5796 if (i
.types
[0].bitfield
.sreg2
5797 || i
.types
[0].bitfield
.sreg3
)
5799 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5800 && i
.op
[0].regs
->reg_num
== 1)
5802 as_bad (_("you can't `pop %scs'"), register_prefix
);
5805 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5806 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5811 /* The register or float register operand is in operand
5815 if (i
.types
[0].bitfield
.floatreg
5816 || operand_type_check (i
.types
[0], reg
))
5820 /* Register goes in low 3 bits of opcode. */
5821 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5822 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5824 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5826 /* Warn about some common errors, but press on regardless.
5827 The first case can be generated by gcc (<= 2.8.1). */
5828 if (i
.operands
== 2)
5830 /* Reversed arguments on faddp, fsubp, etc. */
5831 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5832 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5833 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5837 /* Extraneous `l' suffix on fp insn. */
5838 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5839 register_prefix
, i
.op
[0].regs
->reg_name
);
5844 else if (i
.tm
.opcode_modifier
.modrm
)
5846 /* The opcode is completed (modulo i.tm.extension_opcode which
5847 must be put into the modrm byte). Now, we make the modrm and
5848 index base bytes based on all the info we've collected. */
5850 default_seg
= build_modrm_byte ();
5852 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5856 else if (i
.tm
.opcode_modifier
.isstring
)
5858 /* For the string instructions that allow a segment override
5859 on one of their operands, the default segment is ds. */
5863 if (i
.tm
.base_opcode
== 0x8d /* lea */
5866 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5868 /* If a segment was explicitly specified, and the specified segment
5869 is not the default, use an opcode prefix to select it. If we
5870 never figured out what the default segment is, then default_seg
5871 will be zero at this point, and the specified segment prefix will
5873 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5875 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5881 static const seg_entry
*
5882 build_modrm_byte (void)
5884 const seg_entry
*default_seg
= 0;
5885 unsigned int source
, dest
;
5888 /* The first operand of instructions with VEX prefix and 3 sources
5889 must be VEX_Imm4. */
5890 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5893 unsigned int nds
, reg_slot
;
5896 if (i
.tm
.opcode_modifier
.veximmext
5897 && i
.tm
.opcode_modifier
.immext
)
5899 dest
= i
.operands
- 2;
5900 gas_assert (dest
== 3);
5903 dest
= i
.operands
- 1;
5906 /* There are 2 kinds of instructions:
5907 1. 5 operands: 4 register operands or 3 register operands
5908 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5909 VexW0 or VexW1. The destination must be either XMM, YMM or
5911 2. 4 operands: 4 register operands or 3 register operands
5912 plus 1 memory operand, VexXDS, and VexImmExt */
5913 gas_assert ((i
.reg_operands
== 4
5914 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5915 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5916 && (i
.tm
.opcode_modifier
.veximmext
5917 || (i
.imm_operands
== 1
5918 && i
.types
[0].bitfield
.vec_imm4
5919 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5920 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5921 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5922 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5923 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5925 if (i
.imm_operands
== 0)
5927 /* When there is no immediate operand, generate an 8bit
5928 immediate operand to encode the first operand. */
5929 exp
= &im_expressions
[i
.imm_operands
++];
5930 i
.op
[i
.operands
].imms
= exp
;
5931 i
.types
[i
.operands
] = imm8
;
5933 /* If VexW1 is set, the first operand is the source and
5934 the second operand is encoded in the immediate operand. */
5935 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5946 /* FMA swaps REG and NDS. */
5947 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5955 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5957 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5959 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5961 exp
->X_op
= O_constant
;
5962 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
5963 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
5967 unsigned int imm_slot
;
5969 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5971 /* If VexW0 is set, the third operand is the source and
5972 the second operand is encoded in the immediate
5979 /* VexW1 is set, the second operand is the source and
5980 the third operand is encoded in the immediate
5986 if (i
.tm
.opcode_modifier
.immext
)
5988 /* When ImmExt is set, the immdiate byte is the last
5990 imm_slot
= i
.operands
- 1;
5998 /* Turn on Imm8 so that output_imm will generate it. */
5999 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6002 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6004 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6006 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6008 i
.op
[imm_slot
].imms
->X_add_number
6009 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6010 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6013 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6014 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6016 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6018 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6023 /* i.reg_operands MUST be the number of real register operands;
6024 implicit registers do not count. If there are 3 register
6025 operands, it must be a instruction with VexNDS. For a
6026 instruction with VexNDD, the destination register is encoded
6027 in VEX prefix. If there are 4 register operands, it must be
6028 a instruction with VEX prefix and 3 sources. */
6029 if (i
.mem_operands
== 0
6030 && ((i
.reg_operands
== 2
6031 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6032 || (i
.reg_operands
== 3
6033 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6034 || (i
.reg_operands
== 4 && vex_3_sources
)))
6042 /* When there are 3 operands, one of them may be immediate,
6043 which may be the first or the last operand. Otherwise,
6044 the first operand must be shift count register (cl) or it
6045 is an instruction with VexNDS. */
6046 gas_assert (i
.imm_operands
== 1
6047 || (i
.imm_operands
== 0
6048 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6049 || i
.types
[0].bitfield
.shiftcount
)));
6050 if (operand_type_check (i
.types
[0], imm
)
6051 || i
.types
[0].bitfield
.shiftcount
)
6057 /* When there are 4 operands, the first two must be 8bit
6058 immediate operands. The source operand will be the 3rd
6061 For instructions with VexNDS, if the first operand
6062 an imm8, the source operand is the 2nd one. If the last
6063 operand is imm8, the source operand is the first one. */
6064 gas_assert ((i
.imm_operands
== 2
6065 && i
.types
[0].bitfield
.imm8
6066 && i
.types
[1].bitfield
.imm8
)
6067 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6068 && i
.imm_operands
== 1
6069 && (i
.types
[0].bitfield
.imm8
6070 || i
.types
[i
.operands
- 1].bitfield
.imm8
6072 if (i
.imm_operands
== 2)
6076 if (i
.types
[0].bitfield
.imm8
)
6083 if (i
.tm
.opcode_modifier
.evex
)
6085 /* For EVEX instructions, when there are 5 operands, the
6086 first one must be immediate operand. If the second one
6087 is immediate operand, the source operand is the 3th
6088 one. If the last one is immediate operand, the source
6089 operand is the 2nd one. */
6090 gas_assert (i
.imm_operands
== 2
6091 && i
.tm
.opcode_modifier
.sae
6092 && operand_type_check (i
.types
[0], imm
));
6093 if (operand_type_check (i
.types
[1], imm
))
6095 else if (operand_type_check (i
.types
[4], imm
))
6109 /* RC/SAE operand could be between DEST and SRC. That happens
6110 when one operand is GPR and the other one is XMM/YMM/ZMM
6112 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6115 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6117 /* For instructions with VexNDS, the register-only source
6118 operand must be 32/64bit integer, XMM, YMM or ZMM
6119 register. It is encoded in VEX prefix. We need to
6120 clear RegMem bit before calling operand_type_equal. */
6122 i386_operand_type op
;
6125 /* Check register-only source operand when two source
6126 operands are swapped. */
6127 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6128 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6136 op
= i
.tm
.operand_types
[vvvv
];
6137 op
.bitfield
.regmem
= 0;
6138 if ((dest
+ 1) >= i
.operands
6139 || (op
.bitfield
.reg32
!= 1
6140 && !op
.bitfield
.reg64
!= 1
6141 && !operand_type_equal (&op
, ®xmm
)
6142 && !operand_type_equal (&op
, ®ymm
)
6143 && !operand_type_equal (&op
, ®zmm
)
6144 && !operand_type_equal (&op
, ®mask
)))
6146 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6152 /* One of the register operands will be encoded in the i.tm.reg
6153 field, the other in the combined i.tm.mode and i.tm.regmem
6154 fields. If no form of this instruction supports a memory
6155 destination operand, then we assume the source operand may
6156 sometimes be a memory operand and so we need to store the
6157 destination in the i.rm.reg field. */
6158 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6159 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6161 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6162 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6163 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6165 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6167 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6169 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6174 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6175 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6176 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6178 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6180 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6182 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6185 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6187 if (!i
.types
[0].bitfield
.control
6188 && !i
.types
[1].bitfield
.control
)
6190 i
.rex
&= ~(REX_R
| REX_B
);
6191 add_prefix (LOCK_PREFIX_OPCODE
);
6195 { /* If it's not 2 reg operands... */
6200 unsigned int fake_zero_displacement
= 0;
6203 for (op
= 0; op
< i
.operands
; op
++)
6204 if (operand_type_check (i
.types
[op
], anymem
))
6206 gas_assert (op
< i
.operands
);
6208 if (i
.tm
.opcode_modifier
.vecsib
)
6210 if (i
.index_reg
->reg_num
== RegEiz
6211 || i
.index_reg
->reg_num
== RegRiz
)
6214 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6217 i
.sib
.base
= NO_BASE_REGISTER
;
6218 i
.sib
.scale
= i
.log2_scale_factor
;
6219 /* No Vec_Disp8 if there is no base. */
6220 i
.types
[op
].bitfield
.vec_disp8
= 0;
6221 i
.types
[op
].bitfield
.disp8
= 0;
6222 i
.types
[op
].bitfield
.disp16
= 0;
6223 i
.types
[op
].bitfield
.disp64
= 0;
6224 if (flag_code
!= CODE_64BIT
)
6226 /* Must be 32 bit */
6227 i
.types
[op
].bitfield
.disp32
= 1;
6228 i
.types
[op
].bitfield
.disp32s
= 0;
6232 i
.types
[op
].bitfield
.disp32
= 0;
6233 i
.types
[op
].bitfield
.disp32s
= 1;
6236 i
.sib
.index
= i
.index_reg
->reg_num
;
6237 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6239 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6245 if (i
.base_reg
== 0)
6248 if (!i
.disp_operands
)
6250 fake_zero_displacement
= 1;
6251 /* Instructions with VSIB byte need 32bit displacement
6252 if there is no base register. */
6253 if (i
.tm
.opcode_modifier
.vecsib
)
6254 i
.types
[op
].bitfield
.disp32
= 1;
6256 if (i
.index_reg
== 0)
6258 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6259 /* Operand is just <disp> */
6260 if (flag_code
== CODE_64BIT
)
6262 /* 64bit mode overwrites the 32bit absolute
6263 addressing by RIP relative addressing and
6264 absolute addressing is encoded by one of the
6265 redundant SIB forms. */
6266 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6267 i
.sib
.base
= NO_BASE_REGISTER
;
6268 i
.sib
.index
= NO_INDEX_REGISTER
;
6269 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6270 ? disp32s
: disp32
);
6272 else if ((flag_code
== CODE_16BIT
)
6273 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6275 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6276 i
.types
[op
] = disp16
;
6280 i
.rm
.regmem
= NO_BASE_REGISTER
;
6281 i
.types
[op
] = disp32
;
6284 else if (!i
.tm
.opcode_modifier
.vecsib
)
6286 /* !i.base_reg && i.index_reg */
6287 if (i
.index_reg
->reg_num
== RegEiz
6288 || i
.index_reg
->reg_num
== RegRiz
)
6289 i
.sib
.index
= NO_INDEX_REGISTER
;
6291 i
.sib
.index
= i
.index_reg
->reg_num
;
6292 i
.sib
.base
= NO_BASE_REGISTER
;
6293 i
.sib
.scale
= i
.log2_scale_factor
;
6294 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6295 /* No Vec_Disp8 if there is no base. */
6296 i
.types
[op
].bitfield
.vec_disp8
= 0;
6297 i
.types
[op
].bitfield
.disp8
= 0;
6298 i
.types
[op
].bitfield
.disp16
= 0;
6299 i
.types
[op
].bitfield
.disp64
= 0;
6300 if (flag_code
!= CODE_64BIT
)
6302 /* Must be 32 bit */
6303 i
.types
[op
].bitfield
.disp32
= 1;
6304 i
.types
[op
].bitfield
.disp32s
= 0;
6308 i
.types
[op
].bitfield
.disp32
= 0;
6309 i
.types
[op
].bitfield
.disp32s
= 1;
6311 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6315 /* RIP addressing for 64bit mode. */
6316 else if (i
.base_reg
->reg_num
== RegRip
||
6317 i
.base_reg
->reg_num
== RegEip
)
6319 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6320 i
.rm
.regmem
= NO_BASE_REGISTER
;
6321 i
.types
[op
].bitfield
.disp8
= 0;
6322 i
.types
[op
].bitfield
.disp16
= 0;
6323 i
.types
[op
].bitfield
.disp32
= 0;
6324 i
.types
[op
].bitfield
.disp32s
= 1;
6325 i
.types
[op
].bitfield
.disp64
= 0;
6326 i
.types
[op
].bitfield
.vec_disp8
= 0;
6327 i
.flags
[op
] |= Operand_PCrel
;
6328 if (! i
.disp_operands
)
6329 fake_zero_displacement
= 1;
6331 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6333 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6334 switch (i
.base_reg
->reg_num
)
6337 if (i
.index_reg
== 0)
6339 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6340 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6344 if (i
.index_reg
== 0)
6347 if (operand_type_check (i
.types
[op
], disp
) == 0)
6349 /* fake (%bp) into 0(%bp) */
6350 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6351 i
.types
[op
].bitfield
.vec_disp8
= 1;
6353 i
.types
[op
].bitfield
.disp8
= 1;
6354 fake_zero_displacement
= 1;
6357 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6358 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6360 default: /* (%si) -> 4 or (%di) -> 5 */
6361 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6363 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6365 else /* i.base_reg and 32/64 bit mode */
6367 if (flag_code
== CODE_64BIT
6368 && operand_type_check (i
.types
[op
], disp
))
6370 i386_operand_type temp
;
6371 operand_type_set (&temp
, 0);
6372 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6373 temp
.bitfield
.vec_disp8
6374 = i
.types
[op
].bitfield
.vec_disp8
;
6376 if (i
.prefix
[ADDR_PREFIX
] == 0)
6377 i
.types
[op
].bitfield
.disp32s
= 1;
6379 i
.types
[op
].bitfield
.disp32
= 1;
6382 if (!i
.tm
.opcode_modifier
.vecsib
)
6383 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6384 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6386 i
.sib
.base
= i
.base_reg
->reg_num
;
6387 /* x86-64 ignores REX prefix bit here to avoid decoder
6389 if (!(i
.base_reg
->reg_flags
& RegRex
)
6390 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6391 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6393 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6395 fake_zero_displacement
= 1;
6396 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6397 i
.types
[op
].bitfield
.vec_disp8
= 1;
6399 i
.types
[op
].bitfield
.disp8
= 1;
6401 i
.sib
.scale
= i
.log2_scale_factor
;
6402 if (i
.index_reg
== 0)
6404 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6405 /* <disp>(%esp) becomes two byte modrm with no index
6406 register. We've already stored the code for esp
6407 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6408 Any base register besides %esp will not use the
6409 extra modrm byte. */
6410 i
.sib
.index
= NO_INDEX_REGISTER
;
6412 else if (!i
.tm
.opcode_modifier
.vecsib
)
6414 if (i
.index_reg
->reg_num
== RegEiz
6415 || i
.index_reg
->reg_num
== RegRiz
)
6416 i
.sib
.index
= NO_INDEX_REGISTER
;
6418 i
.sib
.index
= i
.index_reg
->reg_num
;
6419 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6420 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6425 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6426 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6430 if (!fake_zero_displacement
6434 fake_zero_displacement
= 1;
6435 if (i
.disp_encoding
== disp_encoding_8bit
)
6436 i
.types
[op
].bitfield
.disp8
= 1;
6438 i
.types
[op
].bitfield
.disp32
= 1;
6440 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6444 if (fake_zero_displacement
)
6446 /* Fakes a zero displacement assuming that i.types[op]
6447 holds the correct displacement size. */
6450 gas_assert (i
.op
[op
].disps
== 0);
6451 exp
= &disp_expressions
[i
.disp_operands
++];
6452 i
.op
[op
].disps
= exp
;
6453 exp
->X_op
= O_constant
;
6454 exp
->X_add_number
= 0;
6455 exp
->X_add_symbol
= (symbolS
*) 0;
6456 exp
->X_op_symbol
= (symbolS
*) 0;
6464 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6466 if (operand_type_check (i
.types
[0], imm
))
6467 i
.vex
.register_specifier
= NULL
;
6470 /* VEX.vvvv encodes one of the sources when the first
6471 operand is not an immediate. */
6472 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6473 i
.vex
.register_specifier
= i
.op
[0].regs
;
6475 i
.vex
.register_specifier
= i
.op
[1].regs
;
6478 /* Destination is a XMM register encoded in the ModRM.reg
6480 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6481 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6484 /* ModRM.rm and VEX.B encodes the other source. */
6485 if (!i
.mem_operands
)
6489 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6490 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6492 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6494 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6498 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6500 i
.vex
.register_specifier
= i
.op
[2].regs
;
6501 if (!i
.mem_operands
)
6504 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6505 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6509 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6510 (if any) based on i.tm.extension_opcode. Again, we must be
6511 careful to make sure that segment/control/debug/test/MMX
6512 registers are coded into the i.rm.reg field. */
6513 else if (i
.reg_operands
)
6516 unsigned int vex_reg
= ~0;
6518 for (op
= 0; op
< i
.operands
; op
++)
6519 if (i
.types
[op
].bitfield
.reg8
6520 || i
.types
[op
].bitfield
.reg16
6521 || i
.types
[op
].bitfield
.reg32
6522 || i
.types
[op
].bitfield
.reg64
6523 || i
.types
[op
].bitfield
.regmmx
6524 || i
.types
[op
].bitfield
.regxmm
6525 || i
.types
[op
].bitfield
.regymm
6526 || i
.types
[op
].bitfield
.regbnd
6527 || i
.types
[op
].bitfield
.regzmm
6528 || i
.types
[op
].bitfield
.regmask
6529 || i
.types
[op
].bitfield
.sreg2
6530 || i
.types
[op
].bitfield
.sreg3
6531 || i
.types
[op
].bitfield
.control
6532 || i
.types
[op
].bitfield
.debug
6533 || i
.types
[op
].bitfield
.test
)
6538 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6540 /* For instructions with VexNDS, the register-only
6541 source operand is encoded in VEX prefix. */
6542 gas_assert (mem
!= (unsigned int) ~0);
6547 gas_assert (op
< i
.operands
);
6551 /* Check register-only source operand when two source
6552 operands are swapped. */
6553 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6554 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6558 gas_assert (mem
== (vex_reg
+ 1)
6559 && op
< i
.operands
);
6564 gas_assert (vex_reg
< i
.operands
);
6568 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6570 /* For instructions with VexNDD, the register destination
6571 is encoded in VEX prefix. */
6572 if (i
.mem_operands
== 0)
6574 /* There is no memory operand. */
6575 gas_assert ((op
+ 2) == i
.operands
);
6580 /* There are only 2 operands. */
6581 gas_assert (op
< 2 && i
.operands
== 2);
6586 gas_assert (op
< i
.operands
);
6588 if (vex_reg
!= (unsigned int) ~0)
6590 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6592 if (type
->bitfield
.reg32
!= 1
6593 && type
->bitfield
.reg64
!= 1
6594 && !operand_type_equal (type
, ®xmm
)
6595 && !operand_type_equal (type
, ®ymm
)
6596 && !operand_type_equal (type
, ®zmm
)
6597 && !operand_type_equal (type
, ®mask
))
6600 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6603 /* Don't set OP operand twice. */
6606 /* If there is an extension opcode to put here, the
6607 register number must be put into the regmem field. */
6608 if (i
.tm
.extension_opcode
!= None
)
6610 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6611 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6613 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6618 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6619 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6621 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6626 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6627 must set it to 3 to indicate this is a register operand
6628 in the regmem field. */
6629 if (!i
.mem_operands
)
6633 /* Fill in i.rm.reg field with extension opcode (if any). */
6634 if (i
.tm
.extension_opcode
!= None
)
6635 i
.rm
.reg
= i
.tm
.extension_opcode
;
6641 output_branch (void)
6647 relax_substateT subtype
;
6651 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6652 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6655 if (i
.prefix
[DATA_PREFIX
] != 0)
6661 /* Pentium4 branch hints. */
6662 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6663 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6668 if (i
.prefix
[REX_PREFIX
] != 0)
6674 /* BND prefixed jump. */
6675 if (i
.prefix
[BND_PREFIX
] != 0)
6677 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6681 if (i
.prefixes
!= 0 && !intel_syntax
)
6682 as_warn (_("skipping prefixes on this instruction"));
6684 /* It's always a symbol; End frag & setup for relax.
6685 Make sure there is enough room in this frag for the largest
6686 instruction we may generate in md_convert_frag. This is 2
6687 bytes for the opcode and room for the prefix and largest
6689 frag_grow (prefix
+ 2 + 4);
6690 /* Prefix and 1 opcode byte go in fr_fix. */
6691 p
= frag_more (prefix
+ 1);
6692 if (i
.prefix
[DATA_PREFIX
] != 0)
6693 *p
++ = DATA_PREFIX_OPCODE
;
6694 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6695 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6696 *p
++ = i
.prefix
[SEG_PREFIX
];
6697 if (i
.prefix
[REX_PREFIX
] != 0)
6698 *p
++ = i
.prefix
[REX_PREFIX
];
6699 *p
= i
.tm
.base_opcode
;
6701 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6702 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6703 else if (cpu_arch_flags
.bitfield
.cpui386
)
6704 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6706 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6709 sym
= i
.op
[0].disps
->X_add_symbol
;
6710 off
= i
.op
[0].disps
->X_add_number
;
6712 if (i
.op
[0].disps
->X_op
!= O_constant
6713 && i
.op
[0].disps
->X_op
!= O_symbol
)
6715 /* Handle complex expressions. */
6716 sym
= make_expr_symbol (i
.op
[0].disps
);
6720 /* 1 possible extra opcode + 4 byte displacement go in var part.
6721 Pass reloc in fr_var. */
6722 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6732 if (i
.tm
.opcode_modifier
.jumpbyte
)
6734 /* This is a loop or jecxz type instruction. */
6736 if (i
.prefix
[ADDR_PREFIX
] != 0)
6738 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6741 /* Pentium4 branch hints. */
6742 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6743 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6745 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6754 if (flag_code
== CODE_16BIT
)
6757 if (i
.prefix
[DATA_PREFIX
] != 0)
6759 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6769 if (i
.prefix
[REX_PREFIX
] != 0)
6771 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6775 /* BND prefixed jump. */
6776 if (i
.prefix
[BND_PREFIX
] != 0)
6778 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6782 if (i
.prefixes
!= 0 && !intel_syntax
)
6783 as_warn (_("skipping prefixes on this instruction"));
6785 p
= frag_more (i
.tm
.opcode_length
+ size
);
6786 switch (i
.tm
.opcode_length
)
6789 *p
++ = i
.tm
.base_opcode
>> 8;
6791 *p
++ = i
.tm
.base_opcode
;
6797 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6798 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6800 /* All jumps handled here are signed, but don't use a signed limit
6801 check for 32 and 16 bit jumps as we want to allow wrap around at
6802 4G and 64k respectively. */
6804 fixP
->fx_signed
= 1;
6808 output_interseg_jump (void)
6816 if (flag_code
== CODE_16BIT
)
6820 if (i
.prefix
[DATA_PREFIX
] != 0)
6826 if (i
.prefix
[REX_PREFIX
] != 0)
6836 if (i
.prefixes
!= 0 && !intel_syntax
)
6837 as_warn (_("skipping prefixes on this instruction"));
6839 /* 1 opcode; 2 segment; offset */
6840 p
= frag_more (prefix
+ 1 + 2 + size
);
6842 if (i
.prefix
[DATA_PREFIX
] != 0)
6843 *p
++ = DATA_PREFIX_OPCODE
;
6845 if (i
.prefix
[REX_PREFIX
] != 0)
6846 *p
++ = i
.prefix
[REX_PREFIX
];
6848 *p
++ = i
.tm
.base_opcode
;
6849 if (i
.op
[1].imms
->X_op
== O_constant
)
6851 offsetT n
= i
.op
[1].imms
->X_add_number
;
6854 && !fits_in_unsigned_word (n
)
6855 && !fits_in_signed_word (n
))
6857 as_bad (_("16-bit jump out of range"));
6860 md_number_to_chars (p
, n
, size
);
6863 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6864 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6865 if (i
.op
[0].imms
->X_op
!= O_constant
)
6866 as_bad (_("can't handle non absolute segment in `%s'"),
6868 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6874 fragS
*insn_start_frag
;
6875 offsetT insn_start_off
;
6877 /* Tie dwarf2 debug info to the address at the start of the insn.
6878 We can't do this after the insn has been output as the current
6879 frag may have been closed off. eg. by frag_var. */
6880 dwarf2_emit_insn (0);
6882 insn_start_frag
= frag_now
;
6883 insn_start_off
= frag_now_fix ();
6886 if (i
.tm
.opcode_modifier
.jump
)
6888 else if (i
.tm
.opcode_modifier
.jumpbyte
6889 || i
.tm
.opcode_modifier
.jumpdword
)
6891 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6892 output_interseg_jump ();
6895 /* Output normal instructions here. */
6899 unsigned int prefix
;
6901 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6902 don't need the explicit prefix. */
6903 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6905 switch (i
.tm
.opcode_length
)
6908 if (i
.tm
.base_opcode
& 0xff000000)
6910 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6915 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6917 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6918 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6921 if (prefix
!= REPE_PREFIX_OPCODE
6922 || (i
.prefix
[REP_PREFIX
]
6923 != REPE_PREFIX_OPCODE
))
6924 add_prefix (prefix
);
6927 add_prefix (prefix
);
6936 /* The prefix bytes. */
6937 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6939 FRAG_APPEND_1_CHAR (*q
);
6943 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
6948 /* REX byte is encoded in VEX prefix. */
6952 FRAG_APPEND_1_CHAR (*q
);
6955 /* There should be no other prefixes for instructions
6960 /* For EVEX instructions i.vrex should become 0 after
6961 build_evex_prefix. For VEX instructions upper 16 registers
6962 aren't available, so VREX should be 0. */
6965 /* Now the VEX prefix. */
6966 p
= frag_more (i
.vex
.length
);
6967 for (j
= 0; j
< i
.vex
.length
; j
++)
6968 p
[j
] = i
.vex
.bytes
[j
];
6971 /* Now the opcode; be careful about word order here! */
6972 if (i
.tm
.opcode_length
== 1)
6974 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
6978 switch (i
.tm
.opcode_length
)
6982 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
6983 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
6987 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
6997 /* Put out high byte first: can't use md_number_to_chars! */
6998 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
6999 *p
= i
.tm
.base_opcode
& 0xff;
7002 /* Now the modrm byte and sib byte (if present). */
7003 if (i
.tm
.opcode_modifier
.modrm
)
7005 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7008 /* If i.rm.regmem == ESP (4)
7009 && i.rm.mode != (Register mode)
7011 ==> need second modrm byte. */
7012 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7014 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7015 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7017 | i
.sib
.scale
<< 6));
7020 if (i
.disp_operands
)
7021 output_disp (insn_start_frag
, insn_start_off
);
7024 output_imm (insn_start_frag
, insn_start_off
);
7030 pi ("" /*line*/, &i
);
7032 #endif /* DEBUG386 */
7035 /* Return the size of the displacement operand N. */
7038 disp_size (unsigned int n
)
7042 /* Vec_Disp8 has to be 8bit. */
7043 if (i
.types
[n
].bitfield
.vec_disp8
)
7045 else if (i
.types
[n
].bitfield
.disp64
)
7047 else if (i
.types
[n
].bitfield
.disp8
)
7049 else if (i
.types
[n
].bitfield
.disp16
)
7054 /* Return the size of the immediate operand N. */
7057 imm_size (unsigned int n
)
7060 if (i
.types
[n
].bitfield
.imm64
)
7062 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7064 else if (i
.types
[n
].bitfield
.imm16
)
7070 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7075 for (n
= 0; n
< i
.operands
; n
++)
7077 if (i
.types
[n
].bitfield
.vec_disp8
7078 || operand_type_check (i
.types
[n
], disp
))
7080 if (i
.op
[n
].disps
->X_op
== O_constant
)
7082 int size
= disp_size (n
);
7083 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7085 if (i
.types
[n
].bitfield
.vec_disp8
)
7087 val
= offset_in_range (val
, size
);
7088 p
= frag_more (size
);
7089 md_number_to_chars (p
, val
, size
);
7093 enum bfd_reloc_code_real reloc_type
;
7094 int size
= disp_size (n
);
7095 int sign
= i
.types
[n
].bitfield
.disp32s
;
7096 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7098 /* We can't have 8 bit displacement here. */
7099 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7101 /* The PC relative address is computed relative
7102 to the instruction boundary, so in case immediate
7103 fields follows, we need to adjust the value. */
7104 if (pcrel
&& i
.imm_operands
)
7109 for (n1
= 0; n1
< i
.operands
; n1
++)
7110 if (operand_type_check (i
.types
[n1
], imm
))
7112 /* Only one immediate is allowed for PC
7113 relative address. */
7114 gas_assert (sz
== 0);
7116 i
.op
[n
].disps
->X_add_number
-= sz
;
7118 /* We should find the immediate. */
7119 gas_assert (sz
!= 0);
7122 p
= frag_more (size
);
7123 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7125 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7126 && (((reloc_type
== BFD_RELOC_32
7127 || reloc_type
== BFD_RELOC_X86_64_32S
7128 || (reloc_type
== BFD_RELOC_64
7130 && (i
.op
[n
].disps
->X_op
== O_symbol
7131 || (i
.op
[n
].disps
->X_op
== O_add
7132 && ((symbol_get_value_expression
7133 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7135 || reloc_type
== BFD_RELOC_32_PCREL
))
7139 if (insn_start_frag
== frag_now
)
7140 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7145 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7146 for (fr
= insn_start_frag
->fr_next
;
7147 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7149 add
+= p
- frag_now
->fr_literal
;
7154 reloc_type
= BFD_RELOC_386_GOTPC
;
7155 i
.op
[n
].imms
->X_add_number
+= add
;
7157 else if (reloc_type
== BFD_RELOC_64
)
7158 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7160 /* Don't do the adjustment for x86-64, as there
7161 the pcrel addressing is relative to the _next_
7162 insn, and that is taken care of in other code. */
7163 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7165 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7166 i
.op
[n
].disps
, pcrel
, reloc_type
);
7173 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7178 for (n
= 0; n
< i
.operands
; n
++)
7180 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7181 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7184 if (operand_type_check (i
.types
[n
], imm
))
7186 if (i
.op
[n
].imms
->X_op
== O_constant
)
7188 int size
= imm_size (n
);
7191 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7193 p
= frag_more (size
);
7194 md_number_to_chars (p
, val
, size
);
7198 /* Not absolute_section.
7199 Need a 32-bit fixup (don't support 8bit
7200 non-absolute imms). Try to support other
7202 enum bfd_reloc_code_real reloc_type
;
7203 int size
= imm_size (n
);
7206 if (i
.types
[n
].bitfield
.imm32s
7207 && (i
.suffix
== QWORD_MNEM_SUFFIX
7208 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7213 p
= frag_more (size
);
7214 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7216 /* This is tough to explain. We end up with this one if we
7217 * have operands that look like
7218 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7219 * obtain the absolute address of the GOT, and it is strongly
7220 * preferable from a performance point of view to avoid using
7221 * a runtime relocation for this. The actual sequence of
7222 * instructions often look something like:
7227 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7229 * The call and pop essentially return the absolute address
7230 * of the label .L66 and store it in %ebx. The linker itself
7231 * will ultimately change the first operand of the addl so
7232 * that %ebx points to the GOT, but to keep things simple, the
7233 * .o file must have this operand set so that it generates not
7234 * the absolute address of .L66, but the absolute address of
7235 * itself. This allows the linker itself simply treat a GOTPC
7236 * relocation as asking for a pcrel offset to the GOT to be
7237 * added in, and the addend of the relocation is stored in the
7238 * operand field for the instruction itself.
7240 * Our job here is to fix the operand so that it would add
7241 * the correct offset so that %ebx would point to itself. The
7242 * thing that is tricky is that .-.L66 will point to the
7243 * beginning of the instruction, so we need to further modify
7244 * the operand so that it will point to itself. There are
7245 * other cases where you have something like:
7247 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7249 * and here no correction would be required. Internally in
7250 * the assembler we treat operands of this form as not being
7251 * pcrel since the '.' is explicitly mentioned, and I wonder
7252 * whether it would simplify matters to do it this way. Who
7253 * knows. In earlier versions of the PIC patches, the
7254 * pcrel_adjust field was used to store the correction, but
7255 * since the expression is not pcrel, I felt it would be
7256 * confusing to do it this way. */
7258 if ((reloc_type
== BFD_RELOC_32
7259 || reloc_type
== BFD_RELOC_X86_64_32S
7260 || reloc_type
== BFD_RELOC_64
)
7262 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7263 && (i
.op
[n
].imms
->X_op
== O_symbol
7264 || (i
.op
[n
].imms
->X_op
== O_add
7265 && ((symbol_get_value_expression
7266 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7271 if (insn_start_frag
== frag_now
)
7272 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7277 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7278 for (fr
= insn_start_frag
->fr_next
;
7279 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7281 add
+= p
- frag_now
->fr_literal
;
7285 reloc_type
= BFD_RELOC_386_GOTPC
;
7287 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7289 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7290 i
.op
[n
].imms
->X_add_number
+= add
;
7292 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7293 i
.op
[n
].imms
, 0, reloc_type
);
7299 /* x86_cons_fix_new is called via the expression parsing code when a
7300 reloc is needed. We use this hook to get the correct .got reloc. */
7301 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
7302 static int cons_sign
= -1;
7305 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7308 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
7310 got_reloc
= NO_RELOC
;
7313 if (exp
->X_op
== O_secrel
)
7315 exp
->X_op
= O_symbol
;
7316 r
= BFD_RELOC_32_SECREL
;
7320 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7323 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7324 purpose of the `.dc.a' internal pseudo-op. */
7327 x86_address_bytes (void)
7329 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7331 return stdoutput
->arch_info
->bits_per_address
/ 8;
7334 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7336 # define lex_got(reloc, adjust, types) NULL
7338 /* Parse operands of the form
7339 <symbol>@GOTOFF+<nnn>
7340 and similar .plt or .got references.
7342 If we find one, set up the correct relocation in RELOC and copy the
7343 input string, minus the `@GOTOFF' into a malloc'd buffer for
7344 parsing by the calling routine. Return this buffer, and if ADJUST
7345 is non-null set it to the length of the string we removed from the
7346 input line. Otherwise return NULL. */
7348 lex_got (enum bfd_reloc_code_real
*rel
,
7350 i386_operand_type
*types
)
7352 /* Some of the relocations depend on the size of what field is to
7353 be relocated. But in our callers i386_immediate and i386_displacement
7354 we don't yet know the operand size (this will be set by insn
7355 matching). Hence we record the word32 relocation here,
7356 and adjust the reloc according to the real size in reloc(). */
7357 static const struct {
7360 const enum bfd_reloc_code_real rel
[2];
7361 const i386_operand_type types64
;
7363 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7364 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7366 OPERAND_TYPE_IMM32_64
},
7368 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7369 BFD_RELOC_X86_64_PLTOFF64
},
7370 OPERAND_TYPE_IMM64
},
7371 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7372 BFD_RELOC_X86_64_PLT32
},
7373 OPERAND_TYPE_IMM32_32S_DISP32
},
7374 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7375 BFD_RELOC_X86_64_GOTPLT64
},
7376 OPERAND_TYPE_IMM64_DISP64
},
7377 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7378 BFD_RELOC_X86_64_GOTOFF64
},
7379 OPERAND_TYPE_IMM64_DISP64
},
7380 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7381 BFD_RELOC_X86_64_GOTPCREL
},
7382 OPERAND_TYPE_IMM32_32S_DISP32
},
7383 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7384 BFD_RELOC_X86_64_TLSGD
},
7385 OPERAND_TYPE_IMM32_32S_DISP32
},
7386 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7387 _dummy_first_bfd_reloc_code_real
},
7388 OPERAND_TYPE_NONE
},
7389 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7390 BFD_RELOC_X86_64_TLSLD
},
7391 OPERAND_TYPE_IMM32_32S_DISP32
},
7392 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7393 BFD_RELOC_X86_64_GOTTPOFF
},
7394 OPERAND_TYPE_IMM32_32S_DISP32
},
7395 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7396 BFD_RELOC_X86_64_TPOFF32
},
7397 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7398 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7399 _dummy_first_bfd_reloc_code_real
},
7400 OPERAND_TYPE_NONE
},
7401 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7402 BFD_RELOC_X86_64_DTPOFF32
},
7403 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7404 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7405 _dummy_first_bfd_reloc_code_real
},
7406 OPERAND_TYPE_NONE
},
7407 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7408 _dummy_first_bfd_reloc_code_real
},
7409 OPERAND_TYPE_NONE
},
7410 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7411 BFD_RELOC_X86_64_GOT32
},
7412 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7413 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7414 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7415 OPERAND_TYPE_IMM32_32S_DISP32
},
7416 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7417 BFD_RELOC_X86_64_TLSDESC_CALL
},
7418 OPERAND_TYPE_IMM32_32S_DISP32
},
7423 #if defined (OBJ_MAYBE_ELF)
7428 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7429 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7432 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7434 int len
= gotrel
[j
].len
;
7435 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7437 if (gotrel
[j
].rel
[object_64bit
] != 0)
7440 char *tmpbuf
, *past_reloc
;
7442 *rel
= gotrel
[j
].rel
[object_64bit
];
7446 if (flag_code
!= CODE_64BIT
)
7448 types
->bitfield
.imm32
= 1;
7449 types
->bitfield
.disp32
= 1;
7452 *types
= gotrel
[j
].types64
;
7455 if (j
!= 0 && GOT_symbol
== NULL
)
7456 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7458 /* The length of the first part of our input line. */
7459 first
= cp
- input_line_pointer
;
7461 /* The second part goes from after the reloc token until
7462 (and including) an end_of_line char or comma. */
7463 past_reloc
= cp
+ 1 + len
;
7465 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7467 second
= cp
+ 1 - past_reloc
;
7469 /* Allocate and copy string. The trailing NUL shouldn't
7470 be necessary, but be safe. */
7471 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7472 memcpy (tmpbuf
, input_line_pointer
, first
);
7473 if (second
!= 0 && *past_reloc
!= ' ')
7474 /* Replace the relocation token with ' ', so that
7475 errors like foo@GOTOFF1 will be detected. */
7476 tmpbuf
[first
++] = ' ';
7478 /* Increment length by 1 if the relocation token is
7483 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7484 tmpbuf
[first
+ second
] = '\0';
7488 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7489 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7494 /* Might be a symbol version string. Don't as_bad here. */
7503 /* Parse operands of the form
7504 <symbol>@SECREL32+<nnn>
7506 If we find one, set up the correct relocation in RELOC and copy the
7507 input string, minus the `@SECREL32' into a malloc'd buffer for
7508 parsing by the calling routine. Return this buffer, and if ADJUST
7509 is non-null set it to the length of the string we removed from the
7510 input line. Otherwise return NULL.
7512 This function is copied from the ELF version above adjusted for PE targets. */
7515 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7516 int *adjust ATTRIBUTE_UNUSED
,
7517 i386_operand_type
*types ATTRIBUTE_UNUSED
)
7523 const enum bfd_reloc_code_real rel
[2];
7524 const i386_operand_type types64
;
7528 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7529 BFD_RELOC_32_SECREL
},
7530 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7536 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7537 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7540 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7542 int len
= gotrel
[j
].len
;
7544 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7546 if (gotrel
[j
].rel
[object_64bit
] != 0)
7549 char *tmpbuf
, *past_reloc
;
7551 *rel
= gotrel
[j
].rel
[object_64bit
];
7557 if (flag_code
!= CODE_64BIT
)
7559 types
->bitfield
.imm32
= 1;
7560 types
->bitfield
.disp32
= 1;
7563 *types
= gotrel
[j
].types64
;
7566 /* The length of the first part of our input line. */
7567 first
= cp
- input_line_pointer
;
7569 /* The second part goes from after the reloc token until
7570 (and including) an end_of_line char or comma. */
7571 past_reloc
= cp
+ 1 + len
;
7573 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7575 second
= cp
+ 1 - past_reloc
;
7577 /* Allocate and copy string. The trailing NUL shouldn't
7578 be necessary, but be safe. */
7579 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7580 memcpy (tmpbuf
, input_line_pointer
, first
);
7581 if (second
!= 0 && *past_reloc
!= ' ')
7582 /* Replace the relocation token with ' ', so that
7583 errors like foo@SECLREL321 will be detected. */
7584 tmpbuf
[first
++] = ' ';
7585 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7586 tmpbuf
[first
+ second
] = '\0';
7590 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7591 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7596 /* Might be a symbol version string. Don't as_bad here. */
7603 x86_cons (expressionS
*exp
, int size
)
7605 intel_syntax
= -intel_syntax
;
7608 if (size
== 4 || (object_64bit
&& size
== 8))
7610 /* Handle @GOTOFF and the like in an expression. */
7612 char *gotfree_input_line
;
7615 save
= input_line_pointer
;
7616 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7617 if (gotfree_input_line
)
7618 input_line_pointer
= gotfree_input_line
;
7622 if (gotfree_input_line
)
7624 /* expression () has merrily parsed up to the end of line,
7625 or a comma - in the wrong buffer. Transfer how far
7626 input_line_pointer has moved to the right buffer. */
7627 input_line_pointer
= (save
7628 + (input_line_pointer
- gotfree_input_line
)
7630 free (gotfree_input_line
);
7631 if (exp
->X_op
== O_constant
7632 || exp
->X_op
== O_absent
7633 || exp
->X_op
== O_illegal
7634 || exp
->X_op
== O_register
7635 || exp
->X_op
== O_big
)
7637 char c
= *input_line_pointer
;
7638 *input_line_pointer
= 0;
7639 as_bad (_("missing or invalid expression `%s'"), save
);
7640 *input_line_pointer
= c
;
7647 intel_syntax
= -intel_syntax
;
7650 i386_intel_simplify (exp
);
7654 signed_cons (int size
)
7656 if (flag_code
== CODE_64BIT
)
7664 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7671 if (exp
.X_op
== O_symbol
)
7672 exp
.X_op
= O_secrel
;
7674 emit_expr (&exp
, 4);
7676 while (*input_line_pointer
++ == ',');
7678 input_line_pointer
--;
7679 demand_empty_rest_of_line ();
7683 /* Handle Vector operations. */
7686 check_VecOperations (char *op_string
, char *op_end
)
7688 const reg_entry
*mask
;
7693 && (op_end
== NULL
|| op_string
< op_end
))
7696 if (*op_string
== '{')
7700 /* Check broadcasts. */
7701 if (strncmp (op_string
, "1to", 3) == 0)
7706 goto duplicated_vec_op
;
7709 if (*op_string
== '8')
7710 bcst_type
= BROADCAST_1TO8
;
7711 else if (*op_string
== '1'
7712 && *(op_string
+1) == '6')
7714 bcst_type
= BROADCAST_1TO16
;
7719 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7724 broadcast_op
.type
= bcst_type
;
7725 broadcast_op
.operand
= this_operand
;
7726 i
.broadcast
= &broadcast_op
;
7728 /* Check masking operation. */
7729 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7731 /* k0 can't be used for write mask. */
7732 if (mask
->reg_num
== 0)
7734 as_bad (_("`%s' can't be used for write mask"),
7741 mask_op
.mask
= mask
;
7742 mask_op
.zeroing
= 0;
7743 mask_op
.operand
= this_operand
;
7749 goto duplicated_vec_op
;
7751 i
.mask
->mask
= mask
;
7753 /* Only "{z}" is allowed here. No need to check
7754 zeroing mask explicitly. */
7755 if (i
.mask
->operand
!= this_operand
)
7757 as_bad (_("invalid write mask `%s'"), saved
);
7764 /* Check zeroing-flag for masking operation. */
7765 else if (*op_string
== 'z')
7769 mask_op
.mask
= NULL
;
7770 mask_op
.zeroing
= 1;
7771 mask_op
.operand
= this_operand
;
7776 if (i
.mask
->zeroing
)
7779 as_bad (_("duplicated `%s'"), saved
);
7783 i
.mask
->zeroing
= 1;
7785 /* Only "{%k}" is allowed here. No need to check mask
7786 register explicitly. */
7787 if (i
.mask
->operand
!= this_operand
)
7789 as_bad (_("invalid zeroing-masking `%s'"),
7798 goto unknown_vec_op
;
7800 if (*op_string
!= '}')
7802 as_bad (_("missing `}' in `%s'"), saved
);
7809 /* We don't know this one. */
7810 as_bad (_("unknown vector operation: `%s'"), saved
);
7818 i386_immediate (char *imm_start
)
7820 char *save_input_line_pointer
;
7821 char *gotfree_input_line
;
7824 i386_operand_type types
;
7826 operand_type_set (&types
, ~0);
7828 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7830 as_bad (_("at most %d immediate operands are allowed"),
7831 MAX_IMMEDIATE_OPERANDS
);
7835 exp
= &im_expressions
[i
.imm_operands
++];
7836 i
.op
[this_operand
].imms
= exp
;
7838 if (is_space_char (*imm_start
))
7841 save_input_line_pointer
= input_line_pointer
;
7842 input_line_pointer
= imm_start
;
7844 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7845 if (gotfree_input_line
)
7846 input_line_pointer
= gotfree_input_line
;
7848 exp_seg
= expression (exp
);
7852 /* Handle vector operations. */
7853 if (*input_line_pointer
== '{')
7855 input_line_pointer
= check_VecOperations (input_line_pointer
,
7857 if (input_line_pointer
== NULL
)
7861 if (*input_line_pointer
)
7862 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7864 input_line_pointer
= save_input_line_pointer
;
7865 if (gotfree_input_line
)
7867 free (gotfree_input_line
);
7869 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7870 exp
->X_op
= O_illegal
;
7873 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7877 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7878 i386_operand_type types
, const char *imm_start
)
7880 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7883 as_bad (_("missing or invalid immediate expression `%s'"),
7887 else if (exp
->X_op
== O_constant
)
7889 /* Size it properly later. */
7890 i
.types
[this_operand
].bitfield
.imm64
= 1;
7891 /* If not 64bit, sign extend val. */
7892 if (flag_code
!= CODE_64BIT
7893 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7895 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7897 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7898 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7899 && exp_seg
!= absolute_section
7900 && exp_seg
!= text_section
7901 && exp_seg
!= data_section
7902 && exp_seg
!= bss_section
7903 && exp_seg
!= undefined_section
7904 && !bfd_is_com_section (exp_seg
))
7906 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7910 else if (!intel_syntax
&& exp
->X_op
== O_register
)
7913 as_bad (_("illegal immediate register operand %s"), imm_start
);
7918 /* This is an address. The size of the address will be
7919 determined later, depending on destination register,
7920 suffix, or the default for the section. */
7921 i
.types
[this_operand
].bitfield
.imm8
= 1;
7922 i
.types
[this_operand
].bitfield
.imm16
= 1;
7923 i
.types
[this_operand
].bitfield
.imm32
= 1;
7924 i
.types
[this_operand
].bitfield
.imm32s
= 1;
7925 i
.types
[this_operand
].bitfield
.imm64
= 1;
7926 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7934 i386_scale (char *scale
)
7937 char *save
= input_line_pointer
;
7939 input_line_pointer
= scale
;
7940 val
= get_absolute_expression ();
7945 i
.log2_scale_factor
= 0;
7948 i
.log2_scale_factor
= 1;
7951 i
.log2_scale_factor
= 2;
7954 i
.log2_scale_factor
= 3;
7958 char sep
= *input_line_pointer
;
7960 *input_line_pointer
= '\0';
7961 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7963 *input_line_pointer
= sep
;
7964 input_line_pointer
= save
;
7968 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
7970 as_warn (_("scale factor of %d without an index register"),
7971 1 << i
.log2_scale_factor
);
7972 i
.log2_scale_factor
= 0;
7974 scale
= input_line_pointer
;
7975 input_line_pointer
= save
;
7980 i386_displacement (char *disp_start
, char *disp_end
)
7984 char *save_input_line_pointer
;
7985 char *gotfree_input_line
;
7987 i386_operand_type bigdisp
, types
= anydisp
;
7990 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
7992 as_bad (_("at most %d displacement operands are allowed"),
7993 MAX_MEMORY_OPERANDS
);
7997 operand_type_set (&bigdisp
, 0);
7998 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
7999 || (!current_templates
->start
->opcode_modifier
.jump
8000 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8002 bigdisp
.bitfield
.disp32
= 1;
8003 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8004 if (flag_code
== CODE_64BIT
)
8008 bigdisp
.bitfield
.disp32s
= 1;
8009 bigdisp
.bitfield
.disp64
= 1;
8012 else if ((flag_code
== CODE_16BIT
) ^ override
)
8014 bigdisp
.bitfield
.disp32
= 0;
8015 bigdisp
.bitfield
.disp16
= 1;
8020 /* For PC-relative branches, the width of the displacement
8021 is dependent upon data size, not address size. */
8022 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8023 if (flag_code
== CODE_64BIT
)
8025 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8026 bigdisp
.bitfield
.disp16
= 1;
8029 bigdisp
.bitfield
.disp32
= 1;
8030 bigdisp
.bitfield
.disp32s
= 1;
8036 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8038 : LONG_MNEM_SUFFIX
));
8039 bigdisp
.bitfield
.disp32
= 1;
8040 if ((flag_code
== CODE_16BIT
) ^ override
)
8042 bigdisp
.bitfield
.disp32
= 0;
8043 bigdisp
.bitfield
.disp16
= 1;
8047 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8050 exp
= &disp_expressions
[i
.disp_operands
];
8051 i
.op
[this_operand
].disps
= exp
;
8053 save_input_line_pointer
= input_line_pointer
;
8054 input_line_pointer
= disp_start
;
8055 END_STRING_AND_SAVE (disp_end
);
8057 #ifndef GCC_ASM_O_HACK
8058 #define GCC_ASM_O_HACK 0
8061 END_STRING_AND_SAVE (disp_end
+ 1);
8062 if (i
.types
[this_operand
].bitfield
.baseIndex
8063 && displacement_string_end
[-1] == '+')
8065 /* This hack is to avoid a warning when using the "o"
8066 constraint within gcc asm statements.
8069 #define _set_tssldt_desc(n,addr,limit,type) \
8070 __asm__ __volatile__ ( \
8072 "movw %w1,2+%0\n\t" \
8074 "movb %b1,4+%0\n\t" \
8075 "movb %4,5+%0\n\t" \
8076 "movb $0,6+%0\n\t" \
8077 "movb %h1,7+%0\n\t" \
8079 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8081 This works great except that the output assembler ends
8082 up looking a bit weird if it turns out that there is
8083 no offset. You end up producing code that looks like:
8096 So here we provide the missing zero. */
8098 *displacement_string_end
= '0';
8101 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8102 if (gotfree_input_line
)
8103 input_line_pointer
= gotfree_input_line
;
8105 exp_seg
= expression (exp
);
8108 if (*input_line_pointer
)
8109 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8111 RESTORE_END_STRING (disp_end
+ 1);
8113 input_line_pointer
= save_input_line_pointer
;
8114 if (gotfree_input_line
)
8116 free (gotfree_input_line
);
8118 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8119 exp
->X_op
= O_illegal
;
8122 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8124 RESTORE_END_STRING (disp_end
);
8130 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8131 i386_operand_type types
, const char *disp_start
)
8133 i386_operand_type bigdisp
;
8136 /* We do this to make sure that the section symbol is in
8137 the symbol table. We will ultimately change the relocation
8138 to be relative to the beginning of the section. */
8139 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8140 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8141 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8143 if (exp
->X_op
!= O_symbol
)
8146 if (S_IS_LOCAL (exp
->X_add_symbol
)
8147 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8148 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8149 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8150 exp
->X_op
= O_subtract
;
8151 exp
->X_op_symbol
= GOT_symbol
;
8152 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8153 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8154 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8155 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8157 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8160 else if (exp
->X_op
== O_absent
8161 || exp
->X_op
== O_illegal
8162 || exp
->X_op
== O_big
)
8165 as_bad (_("missing or invalid displacement expression `%s'"),
8170 else if (flag_code
== CODE_64BIT
8171 && !i
.prefix
[ADDR_PREFIX
]
8172 && exp
->X_op
== O_constant
)
8174 /* Since displacement is signed extended to 64bit, don't allow
8175 disp32 and turn off disp32s if they are out of range. */
8176 i
.types
[this_operand
].bitfield
.disp32
= 0;
8177 if (!fits_in_signed_long (exp
->X_add_number
))
8179 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8180 if (i
.types
[this_operand
].bitfield
.baseindex
)
8182 as_bad (_("0x%lx out range of signed 32bit displacement"),
8183 (long) exp
->X_add_number
);
8189 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8190 else if (exp
->X_op
!= O_constant
8191 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8192 && exp_seg
!= absolute_section
8193 && exp_seg
!= text_section
8194 && exp_seg
!= data_section
8195 && exp_seg
!= bss_section
8196 && exp_seg
!= undefined_section
8197 && !bfd_is_com_section (exp_seg
))
8199 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8204 /* Check if this is a displacement only operand. */
8205 bigdisp
= i
.types
[this_operand
];
8206 bigdisp
.bitfield
.disp8
= 0;
8207 bigdisp
.bitfield
.disp16
= 0;
8208 bigdisp
.bitfield
.disp32
= 0;
8209 bigdisp
.bitfield
.disp32s
= 0;
8210 bigdisp
.bitfield
.disp64
= 0;
8211 if (operand_type_all_zero (&bigdisp
))
8212 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8218 /* Make sure the memory operand we've been dealt is valid.
8219 Return 1 on success, 0 on a failure. */
8222 i386_index_check (const char *operand_string
)
8224 const char *kind
= "base/index";
8225 enum flag_code addr_mode
;
8227 if (i
.prefix
[ADDR_PREFIX
])
8228 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8231 addr_mode
= flag_code
;
8233 #if INFER_ADDR_PREFIX
8234 if (i
.mem_operands
== 0)
8236 /* Infer address prefix from the first memory operand. */
8237 const reg_entry
*addr_reg
= i
.base_reg
;
8239 if (addr_reg
== NULL
)
8240 addr_reg
= i
.index_reg
;
8244 if (addr_reg
->reg_num
== RegEip
8245 || addr_reg
->reg_num
== RegEiz
8246 || addr_reg
->reg_type
.bitfield
.reg32
)
8247 addr_mode
= CODE_32BIT
;
8248 else if (flag_code
!= CODE_64BIT
8249 && addr_reg
->reg_type
.bitfield
.reg16
)
8250 addr_mode
= CODE_16BIT
;
8252 if (addr_mode
!= flag_code
)
8254 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8256 /* Change the size of any displacement too. At most one
8257 of Disp16 or Disp32 is set.
8258 FIXME. There doesn't seem to be any real need for
8259 separate Disp16 and Disp32 flags. The same goes for
8260 Imm16 and Imm32. Removing them would probably clean
8261 up the code quite a lot. */
8262 if (flag_code
!= CODE_64BIT
8263 && (i
.types
[this_operand
].bitfield
.disp16
8264 || i
.types
[this_operand
].bitfield
.disp32
))
8265 i
.types
[this_operand
]
8266 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8273 if (current_templates
->start
->opcode_modifier
.isstring
8274 && !current_templates
->start
->opcode_modifier
.immext
8275 && (current_templates
->end
[-1].opcode_modifier
.isstring
8278 /* Memory operands of string insns are special in that they only allow
8279 a single register (rDI, rSI, or rBX) as their memory address. */
8280 const reg_entry
*expected_reg
;
8281 static const char *di_si
[][2] =
8287 static const char *bx
[] = { "ebx", "bx", "rbx" };
8289 kind
= "string address";
8291 if (current_templates
->start
->opcode_modifier
.w
)
8293 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8295 if (!type
.bitfield
.baseindex
8296 || ((!i
.mem_operands
!= !intel_syntax
)
8297 && current_templates
->end
[-1].operand_types
[1]
8298 .bitfield
.baseindex
))
8299 type
= current_templates
->end
[-1].operand_types
[1];
8300 expected_reg
= hash_find (reg_hash
,
8301 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8305 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8307 if (i
.base_reg
!= expected_reg
8309 || operand_type_check (i
.types
[this_operand
], disp
))
8311 /* The second memory operand must have the same size as
8315 && !((addr_mode
== CODE_64BIT
8316 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8317 || (addr_mode
== CODE_32BIT
8318 ? i
.base_reg
->reg_type
.bitfield
.reg32
8319 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8322 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8324 intel_syntax
? '[' : '(',
8326 expected_reg
->reg_name
,
8327 intel_syntax
? ']' : ')');
8334 as_bad (_("`%s' is not a valid %s expression"),
8335 operand_string
, kind
);
8340 if (addr_mode
!= CODE_16BIT
)
8342 /* 32-bit/64-bit checks. */
8344 && (addr_mode
== CODE_64BIT
8345 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8346 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8348 || (i
.base_reg
->reg_num
8349 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8351 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8352 && !i
.index_reg
->reg_type
.bitfield
.regymm
8353 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8354 && ((addr_mode
== CODE_64BIT
8355 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8356 || i
.index_reg
->reg_num
== RegRiz
)
8357 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8358 || i
.index_reg
->reg_num
== RegEiz
))
8359 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8364 /* 16-bit checks. */
8366 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8367 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8369 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8370 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8372 && i
.base_reg
->reg_num
< 6
8373 && i
.index_reg
->reg_num
>= 6
8374 && i
.log2_scale_factor
== 0))))
8381 /* Handle vector immediates. */
8384 RC_SAE_immediate (const char *imm_start
)
8386 unsigned int match_found
, j
;
8387 const char *pstr
= imm_start
;
8395 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8397 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8401 rc_op
.type
= RC_NamesTable
[j
].type
;
8402 rc_op
.operand
= this_operand
;
8403 i
.rounding
= &rc_op
;
8407 as_bad (_("duplicated `%s'"), imm_start
);
8410 pstr
+= RC_NamesTable
[j
].len
;
8420 as_bad (_("Missing '}': '%s'"), imm_start
);
8423 /* RC/SAE immediate string should contain nothing more. */;
8426 as_bad (_("Junk after '}': '%s'"), imm_start
);
8430 exp
= &im_expressions
[i
.imm_operands
++];
8431 i
.op
[this_operand
].imms
= exp
;
8433 exp
->X_op
= O_constant
;
8434 exp
->X_add_number
= 0;
8435 exp
->X_add_symbol
= (symbolS
*) 0;
8436 exp
->X_op_symbol
= (symbolS
*) 0;
8438 i
.types
[this_operand
].bitfield
.imm8
= 1;
8442 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8446 i386_att_operand (char *operand_string
)
8450 char *op_string
= operand_string
;
8452 if (is_space_char (*op_string
))
8455 /* We check for an absolute prefix (differentiating,
8456 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8457 if (*op_string
== ABSOLUTE_PREFIX
)
8460 if (is_space_char (*op_string
))
8462 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8465 /* Check if operand is a register. */
8466 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8468 i386_operand_type temp
;
8470 /* Check for a segment override by searching for ':' after a
8471 segment register. */
8473 if (is_space_char (*op_string
))
8475 if (*op_string
== ':'
8476 && (r
->reg_type
.bitfield
.sreg2
8477 || r
->reg_type
.bitfield
.sreg3
))
8482 i
.seg
[i
.mem_operands
] = &es
;
8485 i
.seg
[i
.mem_operands
] = &cs
;
8488 i
.seg
[i
.mem_operands
] = &ss
;
8491 i
.seg
[i
.mem_operands
] = &ds
;
8494 i
.seg
[i
.mem_operands
] = &fs
;
8497 i
.seg
[i
.mem_operands
] = &gs
;
8501 /* Skip the ':' and whitespace. */
8503 if (is_space_char (*op_string
))
8506 if (!is_digit_char (*op_string
)
8507 && !is_identifier_char (*op_string
)
8508 && *op_string
!= '('
8509 && *op_string
!= ABSOLUTE_PREFIX
)
8511 as_bad (_("bad memory operand `%s'"), op_string
);
8514 /* Handle case of %es:*foo. */
8515 if (*op_string
== ABSOLUTE_PREFIX
)
8518 if (is_space_char (*op_string
))
8520 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8522 goto do_memory_reference
;
8525 /* Handle vector operations. */
8526 if (*op_string
== '{')
8528 op_string
= check_VecOperations (op_string
, NULL
);
8529 if (op_string
== NULL
)
8535 as_bad (_("junk `%s' after register"), op_string
);
8539 temp
.bitfield
.baseindex
= 0;
8540 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8542 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8543 i
.op
[this_operand
].regs
= r
;
8546 else if (*op_string
== REGISTER_PREFIX
)
8548 as_bad (_("bad register name `%s'"), op_string
);
8551 else if (*op_string
== IMMEDIATE_PREFIX
)
8554 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8556 as_bad (_("immediate operand illegal with absolute jump"));
8559 if (!i386_immediate (op_string
))
8562 else if (RC_SAE_immediate (operand_string
))
8564 /* If it is a RC or SAE immediate, do nothing. */
8567 else if (is_digit_char (*op_string
)
8568 || is_identifier_char (*op_string
)
8569 || *op_string
== '(')
8571 /* This is a memory reference of some sort. */
8574 /* Start and end of displacement string expression (if found). */
8575 char *displacement_string_start
;
8576 char *displacement_string_end
;
8579 do_memory_reference
:
8580 if ((i
.mem_operands
== 1
8581 && !current_templates
->start
->opcode_modifier
.isstring
)
8582 || i
.mem_operands
== 2)
8584 as_bad (_("too many memory references for `%s'"),
8585 current_templates
->start
->name
);
8589 /* Check for base index form. We detect the base index form by
8590 looking for an ')' at the end of the operand, searching
8591 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8593 base_string
= op_string
+ strlen (op_string
);
8595 /* Handle vector operations. */
8596 vop_start
= strchr (op_string
, '{');
8597 if (vop_start
&& vop_start
< base_string
)
8599 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8601 base_string
= vop_start
;
8605 if (is_space_char (*base_string
))
8608 /* If we only have a displacement, set-up for it to be parsed later. */
8609 displacement_string_start
= op_string
;
8610 displacement_string_end
= base_string
+ 1;
8612 if (*base_string
== ')')
8615 unsigned int parens_balanced
= 1;
8616 /* We've already checked that the number of left & right ()'s are
8617 equal, so this loop will not be infinite. */
8621 if (*base_string
== ')')
8623 if (*base_string
== '(')
8626 while (parens_balanced
);
8628 temp_string
= base_string
;
8630 /* Skip past '(' and whitespace. */
8632 if (is_space_char (*base_string
))
8635 if (*base_string
== ','
8636 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8639 displacement_string_end
= temp_string
;
8641 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8645 base_string
= end_op
;
8646 if (is_space_char (*base_string
))
8650 /* There may be an index reg or scale factor here. */
8651 if (*base_string
== ',')
8654 if (is_space_char (*base_string
))
8657 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8660 base_string
= end_op
;
8661 if (is_space_char (*base_string
))
8663 if (*base_string
== ',')
8666 if (is_space_char (*base_string
))
8669 else if (*base_string
!= ')')
8671 as_bad (_("expecting `,' or `)' "
8672 "after index register in `%s'"),
8677 else if (*base_string
== REGISTER_PREFIX
)
8679 end_op
= strchr (base_string
, ',');
8682 as_bad (_("bad register name `%s'"), base_string
);
8686 /* Check for scale factor. */
8687 if (*base_string
!= ')')
8689 char *end_scale
= i386_scale (base_string
);
8694 base_string
= end_scale
;
8695 if (is_space_char (*base_string
))
8697 if (*base_string
!= ')')
8699 as_bad (_("expecting `)' "
8700 "after scale factor in `%s'"),
8705 else if (!i
.index_reg
)
8707 as_bad (_("expecting index register or scale factor "
8708 "after `,'; got '%c'"),
8713 else if (*base_string
!= ')')
8715 as_bad (_("expecting `,' or `)' "
8716 "after base register in `%s'"),
8721 else if (*base_string
== REGISTER_PREFIX
)
8723 end_op
= strchr (base_string
, ',');
8726 as_bad (_("bad register name `%s'"), base_string
);
8731 /* If there's an expression beginning the operand, parse it,
8732 assuming displacement_string_start and
8733 displacement_string_end are meaningful. */
8734 if (displacement_string_start
!= displacement_string_end
)
8736 if (!i386_displacement (displacement_string_start
,
8737 displacement_string_end
))
8741 /* Special case for (%dx) while doing input/output op. */
8743 && operand_type_equal (&i
.base_reg
->reg_type
,
8744 ®16_inoutportreg
)
8746 && i
.log2_scale_factor
== 0
8747 && i
.seg
[i
.mem_operands
] == 0
8748 && !operand_type_check (i
.types
[this_operand
], disp
))
8750 i
.types
[this_operand
] = inoutportreg
;
8754 if (i386_index_check (operand_string
) == 0)
8756 i
.types
[this_operand
].bitfield
.mem
= 1;
8761 /* It's not a memory operand; argh! */
8762 as_bad (_("invalid char %s beginning operand %d `%s'"),
8763 output_invalid (*op_string
),
8768 return 1; /* Normal return. */
8771 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8772 that an rs_machine_dependent frag may reach. */
8775 i386_frag_max_var (fragS
*frag
)
8777 /* The only relaxable frags are for jumps.
8778 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8779 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8780 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8783 /* md_estimate_size_before_relax()
8785 Called just before relax() for rs_machine_dependent frags. The x86
8786 assembler uses these frags to handle variable size jump
8789 Any symbol that is now undefined will not become defined.
8790 Return the correct fr_subtype in the frag.
8791 Return the initial "guess for variable size of frag" to caller.
8792 The guess is actually the growth beyond the fixed part. Whatever
8793 we do to grow the fixed or variable part contributes to our
8797 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8799 /* We've already got fragP->fr_subtype right; all we have to do is
8800 check for un-relaxable symbols. On an ELF system, we can't relax
8801 an externally visible symbol, because it may be overridden by a
8803 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8804 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8806 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
8807 || S_IS_WEAK (fragP
->fr_symbol
)
8808 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
8809 & BSF_GNU_INDIRECT_FUNCTION
))))
8811 #if defined (OBJ_COFF) && defined (TE_PE)
8812 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8813 && S_IS_WEAK (fragP
->fr_symbol
))
8817 /* Symbol is undefined in this segment, or we need to keep a
8818 reloc so that weak symbols can be overridden. */
8819 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8820 enum bfd_reloc_code_real reloc_type
;
8821 unsigned char *opcode
;
8824 if (fragP
->fr_var
!= NO_RELOC
)
8825 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8827 reloc_type
= BFD_RELOC_16_PCREL
;
8829 reloc_type
= BFD_RELOC_32_PCREL
;
8831 old_fr_fix
= fragP
->fr_fix
;
8832 opcode
= (unsigned char *) fragP
->fr_opcode
;
8834 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
8837 /* Make jmp (0xeb) a (d)word displacement jump. */
8839 fragP
->fr_fix
+= size
;
8840 fix_new (fragP
, old_fr_fix
, size
,
8842 fragP
->fr_offset
, 1,
8848 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
8850 /* Negate the condition, and branch past an
8851 unconditional jump. */
8854 /* Insert an unconditional jump. */
8856 /* We added two extra opcode bytes, and have a two byte
8858 fragP
->fr_fix
+= 2 + 2;
8859 fix_new (fragP
, old_fr_fix
+ 2, 2,
8861 fragP
->fr_offset
, 1,
8868 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8873 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8875 fragP
->fr_offset
, 1,
8877 fixP
->fx_signed
= 1;
8881 /* This changes the byte-displacement jump 0x7N
8882 to the (d)word-displacement jump 0x0f,0x8N. */
8883 opcode
[1] = opcode
[0] + 0x10;
8884 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8885 /* We've added an opcode byte. */
8886 fragP
->fr_fix
+= 1 + size
;
8887 fix_new (fragP
, old_fr_fix
+ 1, size
,
8889 fragP
->fr_offset
, 1,
8894 BAD_CASE (fragP
->fr_subtype
);
8898 return fragP
->fr_fix
- old_fr_fix
;
8901 /* Guess size depending on current relax state. Initially the relax
8902 state will correspond to a short jump and we return 1, because
8903 the variable part of the frag (the branch offset) is one byte
8904 long. However, we can relax a section more than once and in that
8905 case we must either set fr_subtype back to the unrelaxed state,
8906 or return the value for the appropriate branch. */
8907 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
8910 /* Called after relax() is finished.
8912 In: Address of frag.
8913 fr_type == rs_machine_dependent.
8914 fr_subtype is what the address relaxed to.
8916 Out: Any fixSs and constants are set up.
8917 Caller will turn frag into a ".space 0". */
8920 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
8923 unsigned char *opcode
;
8924 unsigned char *where_to_put_displacement
= NULL
;
8925 offsetT target_address
;
8926 offsetT opcode_address
;
8927 unsigned int extension
= 0;
8928 offsetT displacement_from_opcode_start
;
8930 opcode
= (unsigned char *) fragP
->fr_opcode
;
8932 /* Address we want to reach in file space. */
8933 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
8935 /* Address opcode resides at in file space. */
8936 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
8938 /* Displacement from opcode start to fill into instruction. */
8939 displacement_from_opcode_start
= target_address
- opcode_address
;
8941 if ((fragP
->fr_subtype
& BIG
) == 0)
8943 /* Don't have to change opcode. */
8944 extension
= 1; /* 1 opcode + 1 displacement */
8945 where_to_put_displacement
= &opcode
[1];
8949 if (no_cond_jump_promotion
8950 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
8951 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
8952 _("long jump required"));
8954 switch (fragP
->fr_subtype
)
8956 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
8957 extension
= 4; /* 1 opcode + 4 displacement */
8959 where_to_put_displacement
= &opcode
[1];
8962 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
8963 extension
= 2; /* 1 opcode + 2 displacement */
8965 where_to_put_displacement
= &opcode
[1];
8968 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
8969 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
8970 extension
= 5; /* 2 opcode + 4 displacement */
8971 opcode
[1] = opcode
[0] + 0x10;
8972 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8973 where_to_put_displacement
= &opcode
[2];
8976 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
8977 extension
= 3; /* 2 opcode + 2 displacement */
8978 opcode
[1] = opcode
[0] + 0x10;
8979 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8980 where_to_put_displacement
= &opcode
[2];
8983 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
8988 where_to_put_displacement
= &opcode
[3];
8992 BAD_CASE (fragP
->fr_subtype
);
8997 /* If size if less then four we are sure that the operand fits,
8998 but if it's 4, then it could be that the displacement is larger
9000 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9002 && ((addressT
) (displacement_from_opcode_start
- extension
9003 + ((addressT
) 1 << 31))
9004 > (((addressT
) 2 << 31) - 1)))
9006 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9007 _("jump target out of range"));
9008 /* Make us emit 0. */
9009 displacement_from_opcode_start
= extension
;
9011 /* Now put displacement after opcode. */
9012 md_number_to_chars ((char *) where_to_put_displacement
,
9013 (valueT
) (displacement_from_opcode_start
- extension
),
9014 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9015 fragP
->fr_fix
+= extension
;
9018 /* Apply a fixup (fixP) to segment data, once it has been determined
9019 by our caller that we have all the info we need to fix it up.
9021 Parameter valP is the pointer to the value of the bits.
9023 On the 386, immediates, displacements, and data pointers are all in
9024 the same (little-endian) format, so we don't need to care about which
9028 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9030 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9031 valueT value
= *valP
;
9033 #if !defined (TE_Mach)
9036 switch (fixP
->fx_r_type
)
9042 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9045 case BFD_RELOC_X86_64_32S
:
9046 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9049 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9052 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9057 if (fixP
->fx_addsy
!= NULL
9058 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9059 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9060 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9061 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9062 && !use_rela_relocations
)
9064 /* This is a hack. There should be a better way to handle this.
9065 This covers for the fact that bfd_install_relocation will
9066 subtract the current location (for partial_inplace, PC relative
9067 relocations); see more below. */
9071 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9074 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9076 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9079 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9082 || (symbol_section_p (fixP
->fx_addsy
)
9083 && sym_seg
!= absolute_section
))
9084 && !generic_force_reloc (fixP
))
9086 /* Yes, we add the values in twice. This is because
9087 bfd_install_relocation subtracts them out again. I think
9088 bfd_install_relocation is broken, but I don't dare change
9090 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9094 #if defined (OBJ_COFF) && defined (TE_PE)
9095 /* For some reason, the PE format does not store a
9096 section address offset for a PC relative symbol. */
9097 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9098 || S_IS_WEAK (fixP
->fx_addsy
))
9099 value
+= md_pcrel_from (fixP
);
9102 #if defined (OBJ_COFF) && defined (TE_PE)
9103 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9105 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9109 /* Fix a few things - the dynamic linker expects certain values here,
9110 and we must not disappoint it. */
9111 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9112 if (IS_ELF
&& fixP
->fx_addsy
)
9113 switch (fixP
->fx_r_type
)
9115 case BFD_RELOC_386_PLT32
:
9116 case BFD_RELOC_X86_64_PLT32
:
9117 /* Make the jump instruction point to the address of the operand. At
9118 runtime we merely add the offset to the actual PLT entry. */
9122 case BFD_RELOC_386_TLS_GD
:
9123 case BFD_RELOC_386_TLS_LDM
:
9124 case BFD_RELOC_386_TLS_IE_32
:
9125 case BFD_RELOC_386_TLS_IE
:
9126 case BFD_RELOC_386_TLS_GOTIE
:
9127 case BFD_RELOC_386_TLS_GOTDESC
:
9128 case BFD_RELOC_X86_64_TLSGD
:
9129 case BFD_RELOC_X86_64_TLSLD
:
9130 case BFD_RELOC_X86_64_GOTTPOFF
:
9131 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9132 value
= 0; /* Fully resolved at runtime. No addend. */
9134 case BFD_RELOC_386_TLS_LE
:
9135 case BFD_RELOC_386_TLS_LDO_32
:
9136 case BFD_RELOC_386_TLS_LE_32
:
9137 case BFD_RELOC_X86_64_DTPOFF32
:
9138 case BFD_RELOC_X86_64_DTPOFF64
:
9139 case BFD_RELOC_X86_64_TPOFF32
:
9140 case BFD_RELOC_X86_64_TPOFF64
:
9141 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9144 case BFD_RELOC_386_TLS_DESC_CALL
:
9145 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9146 value
= 0; /* Fully resolved at runtime. No addend. */
9147 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9151 case BFD_RELOC_386_GOT32
:
9152 case BFD_RELOC_X86_64_GOT32
:
9153 value
= 0; /* Fully resolved at runtime. No addend. */
9156 case BFD_RELOC_VTABLE_INHERIT
:
9157 case BFD_RELOC_VTABLE_ENTRY
:
9164 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9166 #endif /* !defined (TE_Mach) */
9168 /* Are we finished with this relocation now? */
9169 if (fixP
->fx_addsy
== NULL
)
9171 #if defined (OBJ_COFF) && defined (TE_PE)
9172 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9175 /* Remember value for tc_gen_reloc. */
9176 fixP
->fx_addnumber
= value
;
9177 /* Clear out the frag for now. */
9181 else if (use_rela_relocations
)
9183 fixP
->fx_no_overflow
= 1;
9184 /* Remember value for tc_gen_reloc. */
9185 fixP
->fx_addnumber
= value
;
9189 md_number_to_chars (p
, value
, fixP
->fx_size
);
9193 md_atof (int type
, char *litP
, int *sizeP
)
9195 /* This outputs the LITTLENUMs in REVERSE order;
9196 in accord with the bigendian 386. */
9197 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9200 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9203 output_invalid (int c
)
9206 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9209 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9210 "(0x%x)", (unsigned char) c
);
9211 return output_invalid_buf
;
9214 /* REG_STRING starts *before* REGISTER_PREFIX. */
9216 static const reg_entry
*
9217 parse_real_register (char *reg_string
, char **end_op
)
9219 char *s
= reg_string
;
9221 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9224 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9225 if (*s
== REGISTER_PREFIX
)
9228 if (is_space_char (*s
))
9232 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9234 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9235 return (const reg_entry
*) NULL
;
9239 /* For naked regs, make sure that we are not dealing with an identifier.
9240 This prevents confusing an identifier like `eax_var' with register
9242 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9243 return (const reg_entry
*) NULL
;
9247 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9249 /* Handle floating point regs, allowing spaces in the (i) part. */
9250 if (r
== i386_regtab
/* %st is first entry of table */)
9252 if (is_space_char (*s
))
9257 if (is_space_char (*s
))
9259 if (*s
>= '0' && *s
<= '7')
9263 if (is_space_char (*s
))
9268 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9273 /* We have "%st(" then garbage. */
9274 return (const reg_entry
*) NULL
;
9278 if (r
== NULL
|| allow_pseudo_reg
)
9281 if (operand_type_all_zero (&r
->reg_type
))
9282 return (const reg_entry
*) NULL
;
9284 if ((r
->reg_type
.bitfield
.reg32
9285 || r
->reg_type
.bitfield
.sreg3
9286 || r
->reg_type
.bitfield
.control
9287 || r
->reg_type
.bitfield
.debug
9288 || r
->reg_type
.bitfield
.test
)
9289 && !cpu_arch_flags
.bitfield
.cpui386
)
9290 return (const reg_entry
*) NULL
;
9292 if (r
->reg_type
.bitfield
.floatreg
9293 && !cpu_arch_flags
.bitfield
.cpu8087
9294 && !cpu_arch_flags
.bitfield
.cpu287
9295 && !cpu_arch_flags
.bitfield
.cpu387
)
9296 return (const reg_entry
*) NULL
;
9298 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9299 return (const reg_entry
*) NULL
;
9301 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9302 return (const reg_entry
*) NULL
;
9304 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9305 return (const reg_entry
*) NULL
;
9307 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9308 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9309 return (const reg_entry
*) NULL
;
9311 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9312 if (!allow_index_reg
9313 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9314 return (const reg_entry
*) NULL
;
9316 /* Upper 16 vector register is only available with VREX in 64bit
9318 if ((r
->reg_flags
& RegVRex
))
9320 if (!cpu_arch_flags
.bitfield
.cpuvrex
9321 || flag_code
!= CODE_64BIT
)
9322 return (const reg_entry
*) NULL
;
9327 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9328 || r
->reg_type
.bitfield
.reg64
)
9329 && (!cpu_arch_flags
.bitfield
.cpulm
9330 || !operand_type_equal (&r
->reg_type
, &control
))
9331 && flag_code
!= CODE_64BIT
)
9332 return (const reg_entry
*) NULL
;
9334 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9335 return (const reg_entry
*) NULL
;
9340 /* REG_STRING starts *before* REGISTER_PREFIX. */
9342 static const reg_entry
*
9343 parse_register (char *reg_string
, char **end_op
)
9347 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9348 r
= parse_real_register (reg_string
, end_op
);
9353 char *save
= input_line_pointer
;
9357 input_line_pointer
= reg_string
;
9358 c
= get_symbol_end ();
9359 symbolP
= symbol_find (reg_string
);
9360 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9362 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9364 know (e
->X_op
== O_register
);
9365 know (e
->X_add_number
>= 0
9366 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9367 r
= i386_regtab
+ e
->X_add_number
;
9368 *end_op
= input_line_pointer
;
9370 *input_line_pointer
= c
;
9371 input_line_pointer
= save
;
9377 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9380 char *end
= input_line_pointer
;
9383 r
= parse_register (name
, &input_line_pointer
);
9384 if (r
&& end
<= input_line_pointer
)
9386 *nextcharP
= *input_line_pointer
;
9387 *input_line_pointer
= 0;
9388 e
->X_op
= O_register
;
9389 e
->X_add_number
= r
- i386_regtab
;
9392 input_line_pointer
= end
;
9394 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9398 md_operand (expressionS
*e
)
9403 switch (*input_line_pointer
)
9405 case REGISTER_PREFIX
:
9406 r
= parse_real_register (input_line_pointer
, &end
);
9409 e
->X_op
= O_register
;
9410 e
->X_add_number
= r
- i386_regtab
;
9411 input_line_pointer
= end
;
9416 gas_assert (intel_syntax
);
9417 end
= input_line_pointer
++;
9419 if (*input_line_pointer
== ']')
9421 ++input_line_pointer
;
9422 e
->X_op_symbol
= make_expr_symbol (e
);
9423 e
->X_add_symbol
= NULL
;
9424 e
->X_add_number
= 0;
9430 input_line_pointer
= end
;
9437 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9438 const char *md_shortopts
= "kVQ:sqn";
9440 const char *md_shortopts
= "qn";
9443 #define OPTION_32 (OPTION_MD_BASE + 0)
9444 #define OPTION_64 (OPTION_MD_BASE + 1)
9445 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9446 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9447 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9448 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9449 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9450 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9451 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9452 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9453 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9454 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9455 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9456 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9457 #define OPTION_X32 (OPTION_MD_BASE + 14)
9458 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9459 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9460 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9462 struct option md_longopts
[] =
9464 {"32", no_argument
, NULL
, OPTION_32
},
9465 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9466 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9467 {"64", no_argument
, NULL
, OPTION_64
},
9469 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9470 {"x32", no_argument
, NULL
, OPTION_X32
},
9472 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9473 {"march", required_argument
, NULL
, OPTION_MARCH
},
9474 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9475 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9476 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9477 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9478 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9479 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9480 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9481 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9482 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9483 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9484 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9485 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9486 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9487 {NULL
, no_argument
, NULL
, 0}
9489 size_t md_longopts_size
= sizeof (md_longopts
);
9492 md_parse_option (int c
, char *arg
)
9500 optimize_align_code
= 0;
9507 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9508 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9509 should be emitted or not. FIXME: Not implemented. */
9513 /* -V: SVR4 argument to print version ID. */
9515 print_version_id ();
9518 /* -k: Ignore for FreeBSD compatibility. */
9523 /* -s: On i386 Solaris, this tells the native assembler to use
9524 .stab instead of .stab.excl. We always use .stab anyhow. */
9527 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9531 const char **list
, **l
;
9533 list
= bfd_target_list ();
9534 for (l
= list
; *l
!= NULL
; l
++)
9535 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9536 || strcmp (*l
, "coff-x86-64") == 0
9537 || strcmp (*l
, "pe-x86-64") == 0
9538 || strcmp (*l
, "pei-x86-64") == 0
9539 || strcmp (*l
, "mach-o-x86-64") == 0)
9541 default_arch
= "x86_64";
9545 as_fatal (_("no compiled in support for x86_64"));
9551 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9555 const char **list
, **l
;
9557 list
= bfd_target_list ();
9558 for (l
= list
; *l
!= NULL
; l
++)
9559 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9561 default_arch
= "x86_64:32";
9565 as_fatal (_("no compiled in support for 32bit x86_64"));
9569 as_fatal (_("32bit x86_64 is only supported for ELF"));
9574 default_arch
= "i386";
9578 #ifdef SVR4_COMMENT_CHARS
9583 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9585 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9589 i386_comment_chars
= n
;
9595 arch
= xstrdup (arg
);
9599 as_fatal (_("invalid -march= option: `%s'"), arg
);
9600 next
= strchr (arch
, '+');
9603 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9605 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9608 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9611 cpu_arch_name
= cpu_arch
[j
].name
;
9612 cpu_sub_arch_name
= NULL
;
9613 cpu_arch_flags
= cpu_arch
[j
].flags
;
9614 cpu_arch_isa
= cpu_arch
[j
].type
;
9615 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9616 if (!cpu_arch_tune_set
)
9618 cpu_arch_tune
= cpu_arch_isa
;
9619 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9623 else if (*cpu_arch
[j
].name
== '.'
9624 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9626 /* ISA entension. */
9627 i386_cpu_flags flags
;
9629 if (!cpu_arch
[j
].negated
)
9630 flags
= cpu_flags_or (cpu_arch_flags
,
9633 flags
= cpu_flags_and_not (cpu_arch_flags
,
9635 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9637 if (cpu_sub_arch_name
)
9639 char *name
= cpu_sub_arch_name
;
9640 cpu_sub_arch_name
= concat (name
,
9642 (const char *) NULL
);
9646 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9647 cpu_arch_flags
= flags
;
9648 cpu_arch_isa_flags
= flags
;
9654 if (j
>= ARRAY_SIZE (cpu_arch
))
9655 as_fatal (_("invalid -march= option: `%s'"), arg
);
9659 while (next
!= NULL
);
9664 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9665 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9667 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9669 cpu_arch_tune_set
= 1;
9670 cpu_arch_tune
= cpu_arch
[j
].type
;
9671 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9675 if (j
>= ARRAY_SIZE (cpu_arch
))
9676 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9679 case OPTION_MMNEMONIC
:
9680 if (strcasecmp (arg
, "att") == 0)
9682 else if (strcasecmp (arg
, "intel") == 0)
9685 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9688 case OPTION_MSYNTAX
:
9689 if (strcasecmp (arg
, "att") == 0)
9691 else if (strcasecmp (arg
, "intel") == 0)
9694 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9697 case OPTION_MINDEX_REG
:
9698 allow_index_reg
= 1;
9701 case OPTION_MNAKED_REG
:
9702 allow_naked_reg
= 1;
9705 case OPTION_MOLD_GCC
:
9709 case OPTION_MSSE2AVX
:
9713 case OPTION_MSSE_CHECK
:
9714 if (strcasecmp (arg
, "error") == 0)
9715 sse_check
= check_error
;
9716 else if (strcasecmp (arg
, "warning") == 0)
9717 sse_check
= check_warning
;
9718 else if (strcasecmp (arg
, "none") == 0)
9719 sse_check
= check_none
;
9721 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9724 case OPTION_MOPERAND_CHECK
:
9725 if (strcasecmp (arg
, "error") == 0)
9726 operand_check
= check_error
;
9727 else if (strcasecmp (arg
, "warning") == 0)
9728 operand_check
= check_warning
;
9729 else if (strcasecmp (arg
, "none") == 0)
9730 operand_check
= check_none
;
9732 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9735 case OPTION_MAVXSCALAR
:
9736 if (strcasecmp (arg
, "128") == 0)
9738 else if (strcasecmp (arg
, "256") == 0)
9741 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9744 case OPTION_MADD_BND_PREFIX
:
9748 case OPTION_MEVEXLIG
:
9749 if (strcmp (arg
, "128") == 0)
9751 else if (strcmp (arg
, "256") == 0)
9753 else if (strcmp (arg
, "512") == 0)
9756 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9759 case OPTION_MEVEXWIG
:
9760 if (strcmp (arg
, "0") == 0)
9762 else if (strcmp (arg
, "1") == 0)
9765 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9774 #define MESSAGE_TEMPLATE \
9778 show_arch (FILE *stream
, int ext
, int check
)
9780 static char message
[] = MESSAGE_TEMPLATE
;
9781 char *start
= message
+ 27;
9783 int size
= sizeof (MESSAGE_TEMPLATE
);
9790 left
= size
- (start
- message
);
9791 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9793 /* Should it be skipped? */
9794 if (cpu_arch
[j
].skip
)
9797 name
= cpu_arch
[j
].name
;
9798 len
= cpu_arch
[j
].len
;
9801 /* It is an extension. Skip if we aren't asked to show it. */
9812 /* It is an processor. Skip if we show only extension. */
9815 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9817 /* It is an impossible processor - skip. */
9821 /* Reserve 2 spaces for ", " or ",\0" */
9824 /* Check if there is any room. */
9832 p
= mempcpy (p
, name
, len
);
9836 /* Output the current message now and start a new one. */
9839 fprintf (stream
, "%s\n", message
);
9841 left
= size
- (start
- message
) - len
- 2;
9843 gas_assert (left
>= 0);
9845 p
= mempcpy (p
, name
, len
);
9850 fprintf (stream
, "%s\n", message
);
9854 md_show_usage (FILE *stream
)
9856 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9857 fprintf (stream
, _("\
9859 -V print assembler version number\n\
9862 fprintf (stream
, _("\
9863 -n Do not optimize code alignment\n\
9864 -q quieten some warnings\n"));
9865 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9866 fprintf (stream
, _("\
9869 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9870 || defined (TE_PE) || defined (TE_PEP))
9871 fprintf (stream
, _("\
9872 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
9874 #ifdef SVR4_COMMENT_CHARS
9875 fprintf (stream
, _("\
9876 --divide do not treat `/' as a comment character\n"));
9878 fprintf (stream
, _("\
9879 --divide ignored\n"));
9881 fprintf (stream
, _("\
9882 -march=CPU[,+EXTENSION...]\n\
9883 generate code for CPU and EXTENSION, CPU is one of:\n"));
9884 show_arch (stream
, 0, 1);
9885 fprintf (stream
, _("\
9886 EXTENSION is combination of:\n"));
9887 show_arch (stream
, 1, 0);
9888 fprintf (stream
, _("\
9889 -mtune=CPU optimize for CPU, CPU is one of:\n"));
9890 show_arch (stream
, 0, 0);
9891 fprintf (stream
, _("\
9892 -msse2avx encode SSE instructions with VEX prefix\n"));
9893 fprintf (stream
, _("\
9894 -msse-check=[none|error|warning]\n\
9895 check SSE instructions\n"));
9896 fprintf (stream
, _("\
9897 -moperand-check=[none|error|warning]\n\
9898 check operand combinations for validity\n"));
9899 fprintf (stream
, _("\
9900 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
9902 fprintf (stream
, _("\
9903 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
9905 fprintf (stream
, _("\
9906 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
9907 for EVEX.W bit ignored instructions\n"));
9908 fprintf (stream
, _("\
9909 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
9910 fprintf (stream
, _("\
9911 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
9912 fprintf (stream
, _("\
9913 -mindex-reg support pseudo index registers\n"));
9914 fprintf (stream
, _("\
9915 -mnaked-reg don't require `%%' prefix for registers\n"));
9916 fprintf (stream
, _("\
9917 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
9918 fprintf (stream
, _("\
9919 -madd-bnd-prefix add BND prefix for all valid branches\n"));
9922 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
9923 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9924 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9926 /* Pick the target format to use. */
9929 i386_target_format (void)
9931 if (!strncmp (default_arch
, "x86_64", 6))
9933 update_code_flag (CODE_64BIT
, 1);
9934 if (default_arch
[6] == '\0')
9935 x86_elf_abi
= X86_64_ABI
;
9937 x86_elf_abi
= X86_64_X32_ABI
;
9939 else if (!strcmp (default_arch
, "i386"))
9940 update_code_flag (CODE_32BIT
, 1);
9942 as_fatal (_("unknown architecture"));
9944 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
9945 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
9946 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
9947 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
9949 switch (OUTPUT_FLAVOR
)
9951 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
9952 case bfd_target_aout_flavour
:
9953 return AOUT_TARGET_FORMAT
;
9955 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
9956 # if defined (TE_PE) || defined (TE_PEP)
9957 case bfd_target_coff_flavour
:
9958 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
9959 # elif defined (TE_GO32)
9960 case bfd_target_coff_flavour
:
9963 case bfd_target_coff_flavour
:
9967 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9968 case bfd_target_elf_flavour
:
9972 switch (x86_elf_abi
)
9975 format
= ELF_TARGET_FORMAT
;
9978 use_rela_relocations
= 1;
9980 format
= ELF_TARGET_FORMAT64
;
9982 case X86_64_X32_ABI
:
9983 use_rela_relocations
= 1;
9985 disallow_64bit_reloc
= 1;
9986 format
= ELF_TARGET_FORMAT32
;
9989 if (cpu_arch_isa
== PROCESSOR_L1OM
)
9991 if (x86_elf_abi
!= X86_64_ABI
)
9992 as_fatal (_("Intel L1OM is 64bit only"));
9993 return ELF_TARGET_L1OM_FORMAT
;
9995 if (cpu_arch_isa
== PROCESSOR_K1OM
)
9997 if (x86_elf_abi
!= X86_64_ABI
)
9998 as_fatal (_("Intel K1OM is 64bit only"));
9999 return ELF_TARGET_K1OM_FORMAT
;
10005 #if defined (OBJ_MACH_O)
10006 case bfd_target_mach_o_flavour
:
10007 if (flag_code
== CODE_64BIT
)
10009 use_rela_relocations
= 1;
10011 return "mach-o-x86-64";
10014 return "mach-o-i386";
10022 #endif /* OBJ_MAYBE_ more than one */
10024 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
10026 i386_elf_emit_arch_note (void)
10028 if (IS_ELF
&& cpu_arch_name
!= NULL
)
10031 asection
*seg
= now_seg
;
10032 subsegT subseg
= now_subseg
;
10033 Elf_Internal_Note i_note
;
10034 Elf_External_Note e_note
;
10035 asection
*note_secp
;
10038 /* Create the .note section. */
10039 note_secp
= subseg_new (".note", 0);
10040 bfd_set_section_flags (stdoutput
,
10042 SEC_HAS_CONTENTS
| SEC_READONLY
);
10044 /* Process the arch string. */
10045 len
= strlen (cpu_arch_name
);
10047 i_note
.namesz
= len
+ 1;
10049 i_note
.type
= NT_ARCH
;
10050 p
= frag_more (sizeof (e_note
.namesz
));
10051 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
10052 p
= frag_more (sizeof (e_note
.descsz
));
10053 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
10054 p
= frag_more (sizeof (e_note
.type
));
10055 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
10056 p
= frag_more (len
+ 1);
10057 strcpy (p
, cpu_arch_name
);
10059 frag_align (2, 0, 0);
10061 subseg_set (seg
, subseg
);
10067 md_undefined_symbol (char *name
)
10069 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10070 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10071 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10072 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10076 if (symbol_find (name
))
10077 as_bad (_("GOT already in symbol table"));
10078 GOT_symbol
= symbol_new (name
, undefined_section
,
10079 (valueT
) 0, &zero_address_frag
);
10086 /* Round up a section size to the appropriate boundary. */
10089 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10091 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10092 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10094 /* For a.out, force the section size to be aligned. If we don't do
10095 this, BFD will align it for us, but it will not write out the
10096 final bytes of the section. This may be a bug in BFD, but it is
10097 easier to fix it here since that is how the other a.out targets
10101 align
= bfd_get_section_alignment (stdoutput
, segment
);
10102 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
10109 /* On the i386, PC-relative offsets are relative to the start of the
10110 next instruction. That is, the address of the offset, plus its
10111 size, since the offset is always the last part of the insn. */
10114 md_pcrel_from (fixS
*fixP
)
10116 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10122 s_bss (int ignore ATTRIBUTE_UNUSED
)
10126 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10128 obj_elf_section_change_hook ();
10130 temp
= get_absolute_expression ();
10131 subseg_set (bss_section
, (subsegT
) temp
);
10132 demand_empty_rest_of_line ();
10138 i386_validate_fix (fixS
*fixp
)
10140 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
10142 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10146 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10151 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10153 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10155 fixp
->fx_subsy
= 0;
10160 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10163 bfd_reloc_code_real_type code
;
10165 switch (fixp
->fx_r_type
)
10167 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10168 case BFD_RELOC_SIZE32
:
10169 case BFD_RELOC_SIZE64
:
10170 if (S_IS_DEFINED (fixp
->fx_addsy
)
10171 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10173 /* Resolve size relocation against local symbol to size of
10174 the symbol plus addend. */
10175 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10176 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10177 && !fits_in_unsigned_long (value
))
10178 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10179 _("symbol size computation overflow"));
10180 fixp
->fx_addsy
= NULL
;
10181 fixp
->fx_subsy
= NULL
;
10182 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10187 case BFD_RELOC_X86_64_PLT32
:
10188 case BFD_RELOC_X86_64_GOT32
:
10189 case BFD_RELOC_X86_64_GOTPCREL
:
10190 case BFD_RELOC_386_PLT32
:
10191 case BFD_RELOC_386_GOT32
:
10192 case BFD_RELOC_386_GOTOFF
:
10193 case BFD_RELOC_386_GOTPC
:
10194 case BFD_RELOC_386_TLS_GD
:
10195 case BFD_RELOC_386_TLS_LDM
:
10196 case BFD_RELOC_386_TLS_LDO_32
:
10197 case BFD_RELOC_386_TLS_IE_32
:
10198 case BFD_RELOC_386_TLS_IE
:
10199 case BFD_RELOC_386_TLS_GOTIE
:
10200 case BFD_RELOC_386_TLS_LE_32
:
10201 case BFD_RELOC_386_TLS_LE
:
10202 case BFD_RELOC_386_TLS_GOTDESC
:
10203 case BFD_RELOC_386_TLS_DESC_CALL
:
10204 case BFD_RELOC_X86_64_TLSGD
:
10205 case BFD_RELOC_X86_64_TLSLD
:
10206 case BFD_RELOC_X86_64_DTPOFF32
:
10207 case BFD_RELOC_X86_64_DTPOFF64
:
10208 case BFD_RELOC_X86_64_GOTTPOFF
:
10209 case BFD_RELOC_X86_64_TPOFF32
:
10210 case BFD_RELOC_X86_64_TPOFF64
:
10211 case BFD_RELOC_X86_64_GOTOFF64
:
10212 case BFD_RELOC_X86_64_GOTPC32
:
10213 case BFD_RELOC_X86_64_GOT64
:
10214 case BFD_RELOC_X86_64_GOTPCREL64
:
10215 case BFD_RELOC_X86_64_GOTPC64
:
10216 case BFD_RELOC_X86_64_GOTPLT64
:
10217 case BFD_RELOC_X86_64_PLTOFF64
:
10218 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10219 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10220 case BFD_RELOC_RVA
:
10221 case BFD_RELOC_VTABLE_ENTRY
:
10222 case BFD_RELOC_VTABLE_INHERIT
:
10224 case BFD_RELOC_32_SECREL
:
10226 code
= fixp
->fx_r_type
;
10228 case BFD_RELOC_X86_64_32S
:
10229 if (!fixp
->fx_pcrel
)
10231 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10232 code
= fixp
->fx_r_type
;
10236 if (fixp
->fx_pcrel
)
10238 switch (fixp
->fx_size
)
10241 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10242 _("can not do %d byte pc-relative relocation"),
10244 code
= BFD_RELOC_32_PCREL
;
10246 case 1: code
= BFD_RELOC_8_PCREL
; break;
10247 case 2: code
= BFD_RELOC_16_PCREL
; break;
10248 case 4: code
= BFD_RELOC_32_PCREL
; break;
10250 case 8: code
= BFD_RELOC_64_PCREL
; break;
10256 switch (fixp
->fx_size
)
10259 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10260 _("can not do %d byte relocation"),
10262 code
= BFD_RELOC_32
;
10264 case 1: code
= BFD_RELOC_8
; break;
10265 case 2: code
= BFD_RELOC_16
; break;
10266 case 4: code
= BFD_RELOC_32
; break;
10268 case 8: code
= BFD_RELOC_64
; break;
10275 if ((code
== BFD_RELOC_32
10276 || code
== BFD_RELOC_32_PCREL
10277 || code
== BFD_RELOC_X86_64_32S
)
10279 && fixp
->fx_addsy
== GOT_symbol
)
10282 code
= BFD_RELOC_386_GOTPC
;
10284 code
= BFD_RELOC_X86_64_GOTPC32
;
10286 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10288 && fixp
->fx_addsy
== GOT_symbol
)
10290 code
= BFD_RELOC_X86_64_GOTPC64
;
10293 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10294 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10295 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10297 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10299 if (!use_rela_relocations
)
10301 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10302 vtable entry to be used in the relocation's section offset. */
10303 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10304 rel
->address
= fixp
->fx_offset
;
10305 #if defined (OBJ_COFF) && defined (TE_PE)
10306 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10307 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10312 /* Use the rela in 64bit mode. */
10315 if (disallow_64bit_reloc
)
10318 case BFD_RELOC_X86_64_DTPOFF64
:
10319 case BFD_RELOC_X86_64_TPOFF64
:
10320 case BFD_RELOC_64_PCREL
:
10321 case BFD_RELOC_X86_64_GOTOFF64
:
10322 case BFD_RELOC_X86_64_GOT64
:
10323 case BFD_RELOC_X86_64_GOTPCREL64
:
10324 case BFD_RELOC_X86_64_GOTPC64
:
10325 case BFD_RELOC_X86_64_GOTPLT64
:
10326 case BFD_RELOC_X86_64_PLTOFF64
:
10327 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10328 _("cannot represent relocation type %s in x32 mode"),
10329 bfd_get_reloc_code_name (code
));
10335 if (!fixp
->fx_pcrel
)
10336 rel
->addend
= fixp
->fx_offset
;
10340 case BFD_RELOC_X86_64_PLT32
:
10341 case BFD_RELOC_X86_64_GOT32
:
10342 case BFD_RELOC_X86_64_GOTPCREL
:
10343 case BFD_RELOC_X86_64_TLSGD
:
10344 case BFD_RELOC_X86_64_TLSLD
:
10345 case BFD_RELOC_X86_64_GOTTPOFF
:
10346 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10347 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10348 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10351 rel
->addend
= (section
->vma
10353 + fixp
->fx_addnumber
10354 + md_pcrel_from (fixp
));
10359 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10360 if (rel
->howto
== NULL
)
10362 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10363 _("cannot represent relocation type %s"),
10364 bfd_get_reloc_code_name (code
));
10365 /* Set howto to a garbage value so that we can keep going. */
10366 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10367 gas_assert (rel
->howto
!= NULL
);
10373 #include "tc-i386-intel.c"
10376 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10378 int saved_naked_reg
;
10379 char saved_register_dot
;
10381 saved_naked_reg
= allow_naked_reg
;
10382 allow_naked_reg
= 1;
10383 saved_register_dot
= register_chars
['.'];
10384 register_chars
['.'] = '.';
10385 allow_pseudo_reg
= 1;
10386 expression_and_evaluate (exp
);
10387 allow_pseudo_reg
= 0;
10388 register_chars
['.'] = saved_register_dot
;
10389 allow_naked_reg
= saved_naked_reg
;
10391 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10393 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10395 exp
->X_op
= O_constant
;
10396 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10397 .dw2_regnum
[flag_code
>> 1];
10400 exp
->X_op
= O_illegal
;
10405 tc_x86_frame_initial_instructions (void)
10407 static unsigned int sp_regno
[2];
10409 if (!sp_regno
[flag_code
>> 1])
10411 char *saved_input
= input_line_pointer
;
10412 char sp
[][4] = {"esp", "rsp"};
10415 input_line_pointer
= sp
[flag_code
>> 1];
10416 tc_x86_parse_to_dw2regnum (&exp
);
10417 gas_assert (exp
.X_op
== O_constant
);
10418 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10419 input_line_pointer
= saved_input
;
10422 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10423 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10427 x86_dwarf2_addr_size (void)
10429 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10430 if (x86_elf_abi
== X86_64_X32_ABI
)
10433 return bfd_arch_bits_per_address (stdoutput
) / 8;
10437 i386_elf_section_type (const char *str
, size_t len
)
10439 if (flag_code
== CODE_64BIT
10440 && len
== sizeof ("unwind") - 1
10441 && strncmp (str
, "unwind", 6) == 0)
10442 return SHT_X86_64_UNWIND
;
10449 i386_solaris_fix_up_eh_frame (segT sec
)
10451 if (flag_code
== CODE_64BIT
)
10452 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10458 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10462 exp
.X_op
= O_secrel
;
10463 exp
.X_add_symbol
= symbol
;
10464 exp
.X_add_number
= 0;
10465 emit_expr (&exp
, size
);
10469 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10470 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10473 x86_64_section_letter (int letter
, char **ptr_msg
)
10475 if (flag_code
== CODE_64BIT
)
10478 return SHF_X86_64_LARGE
;
10480 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10483 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10488 x86_64_section_word (char *str
, size_t len
)
10490 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10491 return SHF_X86_64_LARGE
;
10497 handle_large_common (int small ATTRIBUTE_UNUSED
)
10499 if (flag_code
!= CODE_64BIT
)
10501 s_comm_internal (0, elf_common_parse
);
10502 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10506 static segT lbss_section
;
10507 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10508 asection
*saved_bss_section
= bss_section
;
10510 if (lbss_section
== NULL
)
10512 flagword applicable
;
10513 segT seg
= now_seg
;
10514 subsegT subseg
= now_subseg
;
10516 /* The .lbss section is for local .largecomm symbols. */
10517 lbss_section
= subseg_new (".lbss", 0);
10518 applicable
= bfd_applicable_section_flags (stdoutput
);
10519 bfd_set_section_flags (stdoutput
, lbss_section
,
10520 applicable
& SEC_ALLOC
);
10521 seg_info (lbss_section
)->bss
= 1;
10523 subseg_set (seg
, subseg
);
10526 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10527 bss_section
= lbss_section
;
10529 s_comm_internal (0, elf_common_parse
);
10531 elf_com_section_ptr
= saved_com_section_ptr
;
10532 bss_section
= saved_bss_section
;
10535 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */