1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 REP_PREFIX, LOCK_PREFIX. */
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 /* Intel Syntax. Use a non-ascii letter since since it never appears
88 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
90 #define END_OF_INSN '\0'
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
; /* arch string length */
132 enum processor_type type
; /* arch type */
133 i386_cpu_flags flags
; /* cpu feature flags */
134 unsigned int skip
; /* show_arch should skip this. */
135 unsigned int negated
; /* turn off indicated flags. */
139 static void update_code_flag (int, int);
140 static void set_code_flag (int);
141 static void set_16bit_gcc_code_flag (int);
142 static void set_intel_syntax (int);
143 static void set_intel_mnemonic (int);
144 static void set_allow_index_reg (int);
145 static void set_sse_check (int);
146 static void set_cpu_arch (int);
148 static void pe_directive_secrel (int);
150 static void signed_cons (int);
151 static char *output_invalid (int c
);
152 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
154 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
156 static int i386_att_operand (char *);
157 static int i386_intel_operand (char *, int);
158 static int i386_intel_simplify (expressionS
*);
159 static int i386_intel_parse_name (const char *, expressionS
*);
160 static const reg_entry
*parse_register (char *, char **);
161 static char *parse_insn (char *, char *);
162 static char *parse_operands (char *, const char *);
163 static void swap_operands (void);
164 static void swap_2_operands (int, int);
165 static void optimize_imm (void);
166 static void optimize_disp (void);
167 static const insn_template
*match_template (void);
168 static int check_string (void);
169 static int process_suffix (void);
170 static int check_byte_reg (void);
171 static int check_long_reg (void);
172 static int check_qword_reg (void);
173 static int check_word_reg (void);
174 static int finalize_imm (void);
175 static int process_operands (void);
176 static const seg_entry
*build_modrm_byte (void);
177 static void output_insn (void);
178 static void output_imm (fragS
*, offsetT
);
179 static void output_disp (fragS
*, offsetT
);
181 static void s_bss (int);
183 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
184 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
185 static void handle_quad (int);
188 static const char *default_arch
= DEFAULT_ARCH
;
193 /* VEX prefix is either 2 byte or 3 byte. */
194 unsigned char bytes
[3];
196 /* Destination or source register specifier. */
197 const reg_entry
*register_specifier
;
200 /* 'md_assemble ()' gathers together information and puts it into a
207 const reg_entry
*regs
;
212 operand_size_mismatch
,
213 operand_type_mismatch
,
214 register_type_mismatch
,
215 number_of_operands_mismatch
,
216 invalid_instruction_suffix
,
219 unsupported_with_intel_mnemonic
,
226 /* TM holds the template for the insn were currently assembling. */
229 /* SUFFIX holds the instruction size suffix for byte, word, dword
230 or qword, if given. */
233 /* OPERANDS gives the number of given operands. */
234 unsigned int operands
;
236 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
237 of given register, displacement, memory operands and immediate
239 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
241 /* TYPES [i] is the type (see above #defines) which tells us how to
242 use OP[i] for the corresponding operand. */
243 i386_operand_type types
[MAX_OPERANDS
];
245 /* Displacement expression, immediate expression, or register for each
247 union i386_op op
[MAX_OPERANDS
];
249 /* Flags for operands. */
250 unsigned int flags
[MAX_OPERANDS
];
251 #define Operand_PCrel 1
253 /* Relocation type for operand */
254 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
256 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
257 the base index byte below. */
258 const reg_entry
*base_reg
;
259 const reg_entry
*index_reg
;
260 unsigned int log2_scale_factor
;
262 /* SEG gives the seg_entries of this insn. They are zero unless
263 explicit segment overrides are given. */
264 const seg_entry
*seg
[2];
266 /* PREFIX holds all the given prefix opcodes (usually null).
267 PREFIXES is the number of prefix opcodes. */
268 unsigned int prefixes
;
269 unsigned char prefix
[MAX_PREFIXES
];
271 /* RM and SIB are the modrm byte and the sib byte where the
272 addressing modes of this insn are encoded. */
278 /* Swap operand in encoding. */
279 unsigned int swap_operand
;
281 /* Force 32bit displacement in encoding. */
282 unsigned int disp32_encoding
;
285 enum i386_error error
;
288 typedef struct _i386_insn i386_insn
;
290 /* List of chars besides those in app.c:symbol_chars that can start an
291 operand. Used to prevent the scrubber eating vital white-space. */
292 const char extra_symbol_chars
[] = "*%-(["
301 #if (defined (TE_I386AIX) \
302 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
303 && !defined (TE_GNU) \
304 && !defined (TE_LINUX) \
305 && !defined (TE_NETWARE) \
306 && !defined (TE_FreeBSD) \
307 && !defined (TE_DragonFly) \
308 && !defined (TE_NetBSD)))
309 /* This array holds the chars that always start a comment. If the
310 pre-processor is disabled, these aren't very useful. The option
311 --divide will remove '/' from this list. */
312 const char *i386_comment_chars
= "#/";
313 #define SVR4_COMMENT_CHARS 1
314 #define PREFIX_SEPARATOR '\\'
317 const char *i386_comment_chars
= "#";
318 #define PREFIX_SEPARATOR '/'
321 /* This array holds the chars that only start a comment at the beginning of
322 a line. If the line seems to have the form '# 123 filename'
323 .line and .file directives will appear in the pre-processed output.
324 Note that input_file.c hand checks for '#' at the beginning of the
325 first line of the input file. This is because the compiler outputs
326 #NO_APP at the beginning of its output.
327 Also note that comments started like this one will always work if
328 '/' isn't otherwise defined. */
329 const char line_comment_chars
[] = "#/";
331 const char line_separator_chars
[] = ";";
333 /* Chars that can be used to separate mant from exp in floating point
335 const char EXP_CHARS
[] = "eE";
337 /* Chars that mean this number is a floating point constant
340 const char FLT_CHARS
[] = "fFdDxX";
342 /* Tables for lexical analysis. */
343 static char mnemonic_chars
[256];
344 static char register_chars
[256];
345 static char operand_chars
[256];
346 static char identifier_chars
[256];
347 static char digit_chars
[256];
349 /* Lexical macros. */
350 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
351 #define is_operand_char(x) (operand_chars[(unsigned char) x])
352 #define is_register_char(x) (register_chars[(unsigned char) x])
353 #define is_space_char(x) ((x) == ' ')
354 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
355 #define is_digit_char(x) (digit_chars[(unsigned char) x])
357 /* All non-digit non-letter characters that may occur in an operand. */
358 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
360 /* md_assemble() always leaves the strings it's passed unaltered. To
361 effect this we maintain a stack of saved characters that we've smashed
362 with '\0's (indicating end of strings for various sub-fields of the
363 assembler instruction). */
364 static char save_stack
[32];
365 static char *save_stack_p
;
366 #define END_STRING_AND_SAVE(s) \
367 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
368 #define RESTORE_END_STRING(s) \
369 do { *(s) = *--save_stack_p; } while (0)
371 /* The instruction we're assembling. */
374 /* Possible templates for current insn. */
375 static const templates
*current_templates
;
377 /* Per instruction expressionS buffers: max displacements & immediates. */
378 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
379 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
381 /* Current operand we are working on. */
382 static int this_operand
= -1;
384 /* We support four different modes. FLAG_CODE variable is used to distinguish
392 static enum flag_code flag_code
;
393 static unsigned int object_64bit
;
394 static unsigned int disallow_64bit_reloc
;
395 static int use_rela_relocations
= 0;
397 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
398 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
399 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
401 /* The ELF ABI to use. */
409 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
412 /* The names used to print error messages. */
413 static const char *flag_code_names
[] =
420 /* 1 for intel syntax,
422 static int intel_syntax
= 0;
424 /* 1 for intel mnemonic,
425 0 if att mnemonic. */
426 static int intel_mnemonic
= !SYSV386_COMPAT
;
428 /* 1 if support old (<= 2.8.1) versions of gcc. */
429 static int old_gcc
= OLDGCC_COMPAT
;
431 /* 1 if pseudo registers are permitted. */
432 static int allow_pseudo_reg
= 0;
434 /* 1 if register prefix % not required. */
435 static int allow_naked_reg
= 0;
437 /* 1 if pseudo index register, eiz/riz, is allowed . */
438 static int allow_index_reg
= 0;
448 /* Register prefix used for error message. */
449 static const char *register_prefix
= "%";
451 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
452 leave, push, and pop instructions so that gcc has the same stack
453 frame as in 32 bit mode. */
454 static char stackop_size
= '\0';
456 /* Non-zero to optimize code alignment. */
457 int optimize_align_code
= 1;
459 /* Non-zero to quieten some warnings. */
460 static int quiet_warnings
= 0;
463 static const char *cpu_arch_name
= NULL
;
464 static char *cpu_sub_arch_name
= NULL
;
466 /* CPU feature flags. */
467 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
469 /* If we have selected a cpu we are generating instructions for. */
470 static int cpu_arch_tune_set
= 0;
472 /* Cpu we are generating instructions for. */
473 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
475 /* CPU feature flags of cpu we are generating instructions for. */
476 static i386_cpu_flags cpu_arch_tune_flags
;
478 /* CPU instruction set architecture used. */
479 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
481 /* CPU feature flags of instruction set architecture used. */
482 i386_cpu_flags cpu_arch_isa_flags
;
484 /* If set, conditional jumps are not automatically promoted to handle
485 larger than a byte offset. */
486 static unsigned int no_cond_jump_promotion
= 0;
488 /* Encode SSE instructions with VEX prefix. */
489 static unsigned int sse2avx
;
491 /* Encode scalar AVX instructions with specific vector length. */
498 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
499 static symbolS
*GOT_symbol
;
501 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
502 unsigned int x86_dwarf2_return_column
;
504 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
505 int x86_cie_data_alignment
;
507 /* Interface to relax_segment.
508 There are 3 major relax states for 386 jump insns because the
509 different types of jumps add different sizes to frags when we're
510 figuring out what sort of jump to choose to reach a given label. */
513 #define UNCOND_JUMP 0
515 #define COND_JUMP86 2
520 #define SMALL16 (SMALL | CODE16)
522 #define BIG16 (BIG | CODE16)
526 #define INLINE __inline__
532 #define ENCODE_RELAX_STATE(type, size) \
533 ((relax_substateT) (((type) << 2) | (size)))
534 #define TYPE_FROM_RELAX_STATE(s) \
536 #define DISP_SIZE_FROM_RELAX_STATE(s) \
537 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
539 /* This table is used by relax_frag to promote short jumps to long
540 ones where necessary. SMALL (short) jumps may be promoted to BIG
541 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
542 don't allow a short jump in a 32 bit code segment to be promoted to
543 a 16 bit offset jump because it's slower (requires data size
544 prefix), and doesn't work, unless the destination is in the bottom
545 64k of the code segment (The top 16 bits of eip are zeroed). */
547 const relax_typeS md_relax_table
[] =
550 1) most positive reach of this state,
551 2) most negative reach of this state,
552 3) how many bytes this mode will have in the variable part of the frag
553 4) which index into the table to try if we can't fit into this one. */
555 /* UNCOND_JUMP states. */
556 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
557 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
558 /* dword jmp adds 4 bytes to frag:
559 0 extra opcode bytes, 4 displacement bytes. */
561 /* word jmp adds 2 byte2 to frag:
562 0 extra opcode bytes, 2 displacement bytes. */
565 /* COND_JUMP states. */
566 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
567 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
568 /* dword conditionals adds 5 bytes to frag:
569 1 extra opcode byte, 4 displacement bytes. */
571 /* word conditionals add 3 bytes to frag:
572 1 extra opcode byte, 2 displacement bytes. */
575 /* COND_JUMP86 states. */
576 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
577 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
578 /* dword conditionals adds 5 bytes to frag:
579 1 extra opcode byte, 4 displacement bytes. */
581 /* word conditionals add 4 bytes to frag:
582 1 displacement byte and a 3 byte long branch insn. */
586 static const arch_entry cpu_arch
[] =
588 /* Do not replace the first two entries - i386_target_format()
589 relies on them being there in this order. */
590 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
591 CPU_GENERIC32_FLAGS
, 0, 0 },
592 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
593 CPU_GENERIC64_FLAGS
, 0, 0 },
594 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
595 CPU_NONE_FLAGS
, 0, 0 },
596 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
597 CPU_I186_FLAGS
, 0, 0 },
598 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
599 CPU_I286_FLAGS
, 0, 0 },
600 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
601 CPU_I386_FLAGS
, 0, 0 },
602 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
603 CPU_I486_FLAGS
, 0, 0 },
604 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
605 CPU_I586_FLAGS
, 0, 0 },
606 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
607 CPU_I686_FLAGS
, 0, 0 },
608 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
609 CPU_I586_FLAGS
, 0, 0 },
610 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
611 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
612 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
613 CPU_P2_FLAGS
, 0, 0 },
614 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
615 CPU_P3_FLAGS
, 0, 0 },
616 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
617 CPU_P4_FLAGS
, 0, 0 },
618 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
619 CPU_CORE_FLAGS
, 0, 0 },
620 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
621 CPU_NOCONA_FLAGS
, 0, 0 },
622 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
623 CPU_CORE_FLAGS
, 1, 0 },
624 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
625 CPU_CORE_FLAGS
, 0, 0 },
626 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
627 CPU_CORE2_FLAGS
, 1, 0 },
628 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
629 CPU_CORE2_FLAGS
, 0, 0 },
630 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
631 CPU_COREI7_FLAGS
, 0, 0 },
632 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
633 CPU_L1OM_FLAGS
, 0, 0 },
634 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
635 CPU_K6_FLAGS
, 0, 0 },
636 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
637 CPU_K6_2_FLAGS
, 0, 0 },
638 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
639 CPU_ATHLON_FLAGS
, 0, 0 },
640 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
641 CPU_K8_FLAGS
, 1, 0 },
642 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
643 CPU_K8_FLAGS
, 0, 0 },
644 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
645 CPU_K8_FLAGS
, 0, 0 },
646 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
647 CPU_AMDFAM10_FLAGS
, 0, 0 },
648 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER
,
649 CPU_BDVER1_FLAGS
, 0, 0 },
650 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BDVER
,
651 CPU_BDVER2_FLAGS
, 0, 0 },
652 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
653 CPU_8087_FLAGS
, 0, 0 },
654 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
655 CPU_287_FLAGS
, 0, 0 },
656 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
657 CPU_387_FLAGS
, 0, 0 },
658 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
659 CPU_ANY87_FLAGS
, 0, 1 },
660 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
661 CPU_MMX_FLAGS
, 0, 0 },
662 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
663 CPU_3DNOWA_FLAGS
, 0, 1 },
664 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
665 CPU_SSE_FLAGS
, 0, 0 },
666 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
667 CPU_SSE2_FLAGS
, 0, 0 },
668 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
669 CPU_SSE3_FLAGS
, 0, 0 },
670 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
671 CPU_SSSE3_FLAGS
, 0, 0 },
672 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
673 CPU_SSE4_1_FLAGS
, 0, 0 },
674 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
675 CPU_SSE4_2_FLAGS
, 0, 0 },
676 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
677 CPU_SSE4_2_FLAGS
, 0, 0 },
678 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
679 CPU_ANY_SSE_FLAGS
, 0, 1 },
680 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
681 CPU_AVX_FLAGS
, 0, 0 },
682 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
683 CPU_ANY_AVX_FLAGS
, 0, 1 },
684 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
685 CPU_VMX_FLAGS
, 0, 0 },
686 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
687 CPU_SMX_FLAGS
, 0, 0 },
688 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
689 CPU_XSAVE_FLAGS
, 0, 0 },
690 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
691 CPU_XSAVEOPT_FLAGS
, 0, 0 },
692 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
693 CPU_AES_FLAGS
, 0, 0 },
694 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
695 CPU_PCLMUL_FLAGS
, 0, 0 },
696 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
697 CPU_PCLMUL_FLAGS
, 1, 0 },
698 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
699 CPU_FSGSBASE_FLAGS
, 0, 0 },
700 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
701 CPU_RDRND_FLAGS
, 0, 0 },
702 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
703 CPU_F16C_FLAGS
, 0, 0 },
704 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
705 CPU_FMA_FLAGS
, 0, 0 },
706 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
707 CPU_FMA4_FLAGS
, 0, 0 },
708 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
709 CPU_XOP_FLAGS
, 0, 0 },
710 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
711 CPU_LWP_FLAGS
, 0, 0 },
712 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
713 CPU_MOVBE_FLAGS
, 0, 0 },
714 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
715 CPU_EPT_FLAGS
, 0, 0 },
716 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
717 CPU_CLFLUSH_FLAGS
, 0, 0 },
718 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
719 CPU_NOP_FLAGS
, 0, 0 },
720 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
721 CPU_SYSCALL_FLAGS
, 0, 0 },
722 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
723 CPU_RDTSCP_FLAGS
, 0, 0 },
724 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
725 CPU_3DNOW_FLAGS
, 0, 0 },
726 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
727 CPU_3DNOWA_FLAGS
, 0, 0 },
728 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
729 CPU_PADLOCK_FLAGS
, 0, 0 },
730 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
731 CPU_SVME_FLAGS
, 1, 0 },
732 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
733 CPU_SVME_FLAGS
, 0, 0 },
734 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
735 CPU_SSE4A_FLAGS
, 0, 0 },
736 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
737 CPU_ABM_FLAGS
, 0, 0 },
738 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
739 CPU_BMI_FLAGS
, 0, 0 },
740 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
741 CPU_TBM_FLAGS
, 0, 0 },
745 /* Like s_lcomm_internal in gas/read.c but the alignment string
746 is allowed to be optional. */
749 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
756 && *input_line_pointer
== ',')
758 align
= parse_align (needs_align
- 1);
760 if (align
== (addressT
) -1)
775 bss_alloc (symbolP
, size
, align
);
780 pe_lcomm (int needs_align
)
782 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
786 const pseudo_typeS md_pseudo_table
[] =
788 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
789 {"align", s_align_bytes
, 0},
791 {"align", s_align_ptwo
, 0},
793 {"arch", set_cpu_arch
, 0},
797 {"lcomm", pe_lcomm
, 1},
799 {"ffloat", float_cons
, 'f'},
800 {"dfloat", float_cons
, 'd'},
801 {"tfloat", float_cons
, 'x'},
803 {"slong", signed_cons
, 4},
804 {"noopt", s_ignore
, 0},
805 {"optim", s_ignore
, 0},
806 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
807 {"code16", set_code_flag
, CODE_16BIT
},
808 {"code32", set_code_flag
, CODE_32BIT
},
809 {"code64", set_code_flag
, CODE_64BIT
},
810 {"intel_syntax", set_intel_syntax
, 1},
811 {"att_syntax", set_intel_syntax
, 0},
812 {"intel_mnemonic", set_intel_mnemonic
, 1},
813 {"att_mnemonic", set_intel_mnemonic
, 0},
814 {"allow_index_reg", set_allow_index_reg
, 1},
815 {"disallow_index_reg", set_allow_index_reg
, 0},
816 {"sse_check", set_sse_check
, 0},
817 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
818 {"largecomm", handle_large_common
, 0},
819 {"quad", handle_quad
, 8},
821 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
822 {"loc", dwarf2_directive_loc
, 0},
823 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
826 {"secrel32", pe_directive_secrel
, 0},
831 /* For interface with expression (). */
832 extern char *input_line_pointer
;
834 /* Hash table for instruction mnemonic lookup. */
835 static struct hash_control
*op_hash
;
837 /* Hash table for register lookup. */
838 static struct hash_control
*reg_hash
;
841 i386_align_code (fragS
*fragP
, int count
)
843 /* Various efficient no-op patterns for aligning code labels.
844 Note: Don't try to assemble the instructions in the comments.
845 0L and 0w are not legal. */
846 static const char f32_1
[] =
848 static const char f32_2
[] =
849 {0x66,0x90}; /* xchg %ax,%ax */
850 static const char f32_3
[] =
851 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
852 static const char f32_4
[] =
853 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
854 static const char f32_5
[] =
856 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
857 static const char f32_6
[] =
858 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
859 static const char f32_7
[] =
860 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
861 static const char f32_8
[] =
863 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
864 static const char f32_9
[] =
865 {0x89,0xf6, /* movl %esi,%esi */
866 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
867 static const char f32_10
[] =
868 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
869 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
870 static const char f32_11
[] =
871 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
872 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
873 static const char f32_12
[] =
874 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
875 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
876 static const char f32_13
[] =
877 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
878 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
879 static const char f32_14
[] =
880 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
881 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
882 static const char f16_3
[] =
883 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
884 static const char f16_4
[] =
885 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
886 static const char f16_5
[] =
888 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
889 static const char f16_6
[] =
890 {0x89,0xf6, /* mov %si,%si */
891 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
892 static const char f16_7
[] =
893 {0x8d,0x74,0x00, /* lea 0(%si),%si */
894 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
895 static const char f16_8
[] =
896 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
897 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
898 static const char jump_31
[] =
899 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
900 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
901 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
902 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
903 static const char *const f32_patt
[] = {
904 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
905 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
907 static const char *const f16_patt
[] = {
908 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
911 static const char alt_3
[] =
913 /* nopl 0(%[re]ax) */
914 static const char alt_4
[] =
915 {0x0f,0x1f,0x40,0x00};
916 /* nopl 0(%[re]ax,%[re]ax,1) */
917 static const char alt_5
[] =
918 {0x0f,0x1f,0x44,0x00,0x00};
919 /* nopw 0(%[re]ax,%[re]ax,1) */
920 static const char alt_6
[] =
921 {0x66,0x0f,0x1f,0x44,0x00,0x00};
922 /* nopl 0L(%[re]ax) */
923 static const char alt_7
[] =
924 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
925 /* nopl 0L(%[re]ax,%[re]ax,1) */
926 static const char alt_8
[] =
927 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
928 /* nopw 0L(%[re]ax,%[re]ax,1) */
929 static const char alt_9
[] =
930 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
931 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
932 static const char alt_10
[] =
933 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
935 nopw %cs:0L(%[re]ax,%[re]ax,1) */
936 static const char alt_long_11
[] =
938 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
941 nopw %cs:0L(%[re]ax,%[re]ax,1) */
942 static const char alt_long_12
[] =
945 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
949 nopw %cs:0L(%[re]ax,%[re]ax,1) */
950 static const char alt_long_13
[] =
954 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
959 nopw %cs:0L(%[re]ax,%[re]ax,1) */
960 static const char alt_long_14
[] =
965 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
971 nopw %cs:0L(%[re]ax,%[re]ax,1) */
972 static const char alt_long_15
[] =
978 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
979 /* nopl 0(%[re]ax,%[re]ax,1)
980 nopw 0(%[re]ax,%[re]ax,1) */
981 static const char alt_short_11
[] =
982 {0x0f,0x1f,0x44,0x00,0x00,
983 0x66,0x0f,0x1f,0x44,0x00,0x00};
984 /* nopw 0(%[re]ax,%[re]ax,1)
985 nopw 0(%[re]ax,%[re]ax,1) */
986 static const char alt_short_12
[] =
987 {0x66,0x0f,0x1f,0x44,0x00,0x00,
988 0x66,0x0f,0x1f,0x44,0x00,0x00};
989 /* nopw 0(%[re]ax,%[re]ax,1)
991 static const char alt_short_13
[] =
992 {0x66,0x0f,0x1f,0x44,0x00,0x00,
993 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
996 static const char alt_short_14
[] =
997 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
998 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1000 nopl 0L(%[re]ax,%[re]ax,1) */
1001 static const char alt_short_15
[] =
1002 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1003 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1004 static const char *const alt_short_patt
[] = {
1005 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1006 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1007 alt_short_14
, alt_short_15
1009 static const char *const alt_long_patt
[] = {
1010 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1011 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1012 alt_long_14
, alt_long_15
1015 /* Only align for at least a positive non-zero boundary. */
1016 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1019 /* We need to decide which NOP sequence to use for 32bit and
1020 64bit. When -mtune= is used:
1022 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1023 PROCESSOR_GENERIC32, f32_patt will be used.
1024 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1025 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1026 PROCESSOR_GENERIC64, alt_long_patt will be used.
1027 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1028 PROCESSOR_AMDFAM10, and PROCESSOR_BDVER, alt_short_patt
1031 When -mtune= isn't used, alt_long_patt will be used if
1032 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1035 When -march= or .arch is used, we can't use anything beyond
1036 cpu_arch_isa_flags. */
1038 if (flag_code
== CODE_16BIT
)
1042 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1044 /* Adjust jump offset. */
1045 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1048 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1049 f16_patt
[count
- 1], count
);
1053 const char *const *patt
= NULL
;
1055 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1057 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1058 switch (cpu_arch_tune
)
1060 case PROCESSOR_UNKNOWN
:
1061 /* We use cpu_arch_isa_flags to check if we SHOULD
1062 optimize with nops. */
1063 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1064 patt
= alt_long_patt
;
1068 case PROCESSOR_PENTIUM4
:
1069 case PROCESSOR_NOCONA
:
1070 case PROCESSOR_CORE
:
1071 case PROCESSOR_CORE2
:
1072 case PROCESSOR_COREI7
:
1073 case PROCESSOR_L1OM
:
1074 case PROCESSOR_GENERIC64
:
1075 patt
= alt_long_patt
;
1078 case PROCESSOR_ATHLON
:
1080 case PROCESSOR_AMDFAM10
:
1081 case PROCESSOR_BDVER
:
1082 patt
= alt_short_patt
;
1084 case PROCESSOR_I386
:
1085 case PROCESSOR_I486
:
1086 case PROCESSOR_PENTIUM
:
1087 case PROCESSOR_PENTIUMPRO
:
1088 case PROCESSOR_GENERIC32
:
1095 switch (fragP
->tc_frag_data
.tune
)
1097 case PROCESSOR_UNKNOWN
:
1098 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1099 PROCESSOR_UNKNOWN. */
1103 case PROCESSOR_I386
:
1104 case PROCESSOR_I486
:
1105 case PROCESSOR_PENTIUM
:
1107 case PROCESSOR_ATHLON
:
1109 case PROCESSOR_AMDFAM10
:
1110 case PROCESSOR_BDVER
:
1111 case PROCESSOR_GENERIC32
:
1112 /* We use cpu_arch_isa_flags to check if we CAN optimize
1114 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1115 patt
= alt_short_patt
;
1119 case PROCESSOR_PENTIUMPRO
:
1120 case PROCESSOR_PENTIUM4
:
1121 case PROCESSOR_NOCONA
:
1122 case PROCESSOR_CORE
:
1123 case PROCESSOR_CORE2
:
1124 case PROCESSOR_COREI7
:
1125 case PROCESSOR_L1OM
:
1126 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1127 patt
= alt_long_patt
;
1131 case PROCESSOR_GENERIC64
:
1132 patt
= alt_long_patt
;
1137 if (patt
== f32_patt
)
1139 /* If the padding is less than 15 bytes, we use the normal
1140 ones. Otherwise, we use a jump instruction and adjust
1144 /* For 64bit, the limit is 3 bytes. */
1145 if (flag_code
== CODE_64BIT
1146 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1151 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1152 patt
[count
- 1], count
);
1155 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1157 /* Adjust jump offset. */
1158 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1163 /* Maximum length of an instruction is 15 byte. If the
1164 padding is greater than 15 bytes and we don't use jump,
1165 we have to break it into smaller pieces. */
1166 int padding
= count
;
1167 while (padding
> 15)
1170 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1175 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1176 patt
[padding
- 1], padding
);
1179 fragP
->fr_var
= count
;
1183 operand_type_all_zero (const union i386_operand_type
*x
)
1185 switch (ARRAY_SIZE(x
->array
))
1194 return !x
->array
[0];
1201 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1203 switch (ARRAY_SIZE(x
->array
))
1218 operand_type_equal (const union i386_operand_type
*x
,
1219 const union i386_operand_type
*y
)
1221 switch (ARRAY_SIZE(x
->array
))
1224 if (x
->array
[2] != y
->array
[2])
1227 if (x
->array
[1] != y
->array
[1])
1230 return x
->array
[0] == y
->array
[0];
1238 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1240 switch (ARRAY_SIZE(x
->array
))
1249 return !x
->array
[0];
1256 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1258 switch (ARRAY_SIZE(x
->array
))
1273 cpu_flags_equal (const union i386_cpu_flags
*x
,
1274 const union i386_cpu_flags
*y
)
1276 switch (ARRAY_SIZE(x
->array
))
1279 if (x
->array
[2] != y
->array
[2])
1282 if (x
->array
[1] != y
->array
[1])
1285 return x
->array
[0] == y
->array
[0];
1293 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1295 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1296 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1299 static INLINE i386_cpu_flags
1300 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1302 switch (ARRAY_SIZE (x
.array
))
1305 x
.array
[2] &= y
.array
[2];
1307 x
.array
[1] &= y
.array
[1];
1309 x
.array
[0] &= y
.array
[0];
1317 static INLINE i386_cpu_flags
1318 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1320 switch (ARRAY_SIZE (x
.array
))
1323 x
.array
[2] |= y
.array
[2];
1325 x
.array
[1] |= y
.array
[1];
1327 x
.array
[0] |= y
.array
[0];
1335 static INLINE i386_cpu_flags
1336 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1338 switch (ARRAY_SIZE (x
.array
))
1341 x
.array
[2] &= ~y
.array
[2];
1343 x
.array
[1] &= ~y
.array
[1];
1345 x
.array
[0] &= ~y
.array
[0];
1353 #define CPU_FLAGS_ARCH_MATCH 0x1
1354 #define CPU_FLAGS_64BIT_MATCH 0x2
1355 #define CPU_FLAGS_AES_MATCH 0x4
1356 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1357 #define CPU_FLAGS_AVX_MATCH 0x10
1359 #define CPU_FLAGS_32BIT_MATCH \
1360 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1361 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1362 #define CPU_FLAGS_PERFECT_MATCH \
1363 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1365 /* Return CPU flags match bits. */
1368 cpu_flags_match (const insn_template
*t
)
1370 i386_cpu_flags x
= t
->cpu_flags
;
1371 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1373 x
.bitfield
.cpu64
= 0;
1374 x
.bitfield
.cpuno64
= 0;
1376 if (cpu_flags_all_zero (&x
))
1378 /* This instruction is available on all archs. */
1379 match
|= CPU_FLAGS_32BIT_MATCH
;
1383 /* This instruction is available only on some archs. */
1384 i386_cpu_flags cpu
= cpu_arch_flags
;
1386 cpu
.bitfield
.cpu64
= 0;
1387 cpu
.bitfield
.cpuno64
= 0;
1388 cpu
= cpu_flags_and (x
, cpu
);
1389 if (!cpu_flags_all_zero (&cpu
))
1391 if (x
.bitfield
.cpuavx
)
1393 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1394 if (cpu
.bitfield
.cpuavx
)
1396 /* Check SSE2AVX. */
1397 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1399 match
|= (CPU_FLAGS_ARCH_MATCH
1400 | CPU_FLAGS_AVX_MATCH
);
1402 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1403 match
|= CPU_FLAGS_AES_MATCH
;
1405 if (!x
.bitfield
.cpupclmul
1406 || cpu
.bitfield
.cpupclmul
)
1407 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1411 match
|= CPU_FLAGS_ARCH_MATCH
;
1414 match
|= CPU_FLAGS_32BIT_MATCH
;
1420 static INLINE i386_operand_type
1421 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1423 switch (ARRAY_SIZE (x
.array
))
1426 x
.array
[2] &= y
.array
[2];
1428 x
.array
[1] &= y
.array
[1];
1430 x
.array
[0] &= y
.array
[0];
1438 static INLINE i386_operand_type
1439 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1441 switch (ARRAY_SIZE (x
.array
))
1444 x
.array
[2] |= y
.array
[2];
1446 x
.array
[1] |= y
.array
[1];
1448 x
.array
[0] |= y
.array
[0];
1456 static INLINE i386_operand_type
1457 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1459 switch (ARRAY_SIZE (x
.array
))
1462 x
.array
[2] ^= y
.array
[2];
1464 x
.array
[1] ^= y
.array
[1];
1466 x
.array
[0] ^= y
.array
[0];
1474 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1475 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1476 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1477 static const i386_operand_type inoutportreg
1478 = OPERAND_TYPE_INOUTPORTREG
;
1479 static const i386_operand_type reg16_inoutportreg
1480 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1481 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1482 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1483 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1484 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1485 static const i386_operand_type anydisp
1486 = OPERAND_TYPE_ANYDISP
;
1487 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1488 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1489 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1490 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1491 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1492 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1493 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1494 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1495 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1496 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1497 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1498 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1509 operand_type_check (i386_operand_type t
, enum operand_type c
)
1514 return (t
.bitfield
.reg8
1517 || t
.bitfield
.reg64
);
1520 return (t
.bitfield
.imm8
1524 || t
.bitfield
.imm32s
1525 || t
.bitfield
.imm64
);
1528 return (t
.bitfield
.disp8
1529 || t
.bitfield
.disp16
1530 || t
.bitfield
.disp32
1531 || t
.bitfield
.disp32s
1532 || t
.bitfield
.disp64
);
1535 return (t
.bitfield
.disp8
1536 || t
.bitfield
.disp16
1537 || t
.bitfield
.disp32
1538 || t
.bitfield
.disp32s
1539 || t
.bitfield
.disp64
1540 || t
.bitfield
.baseindex
);
1549 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1550 operand J for instruction template T. */
1553 match_reg_size (const insn_template
*t
, unsigned int j
)
1555 return !((i
.types
[j
].bitfield
.byte
1556 && !t
->operand_types
[j
].bitfield
.byte
)
1557 || (i
.types
[j
].bitfield
.word
1558 && !t
->operand_types
[j
].bitfield
.word
)
1559 || (i
.types
[j
].bitfield
.dword
1560 && !t
->operand_types
[j
].bitfield
.dword
)
1561 || (i
.types
[j
].bitfield
.qword
1562 && !t
->operand_types
[j
].bitfield
.qword
));
1565 /* Return 1 if there is no conflict in any size on operand J for
1566 instruction template T. */
1569 match_mem_size (const insn_template
*t
, unsigned int j
)
1571 return (match_reg_size (t
, j
)
1572 && !((i
.types
[j
].bitfield
.unspecified
1573 && !t
->operand_types
[j
].bitfield
.unspecified
)
1574 || (i
.types
[j
].bitfield
.fword
1575 && !t
->operand_types
[j
].bitfield
.fword
)
1576 || (i
.types
[j
].bitfield
.tbyte
1577 && !t
->operand_types
[j
].bitfield
.tbyte
)
1578 || (i
.types
[j
].bitfield
.xmmword
1579 && !t
->operand_types
[j
].bitfield
.xmmword
)
1580 || (i
.types
[j
].bitfield
.ymmword
1581 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1584 /* Return 1 if there is no size conflict on any operands for
1585 instruction template T. */
1588 operand_size_match (const insn_template
*t
)
1593 /* Don't check jump instructions. */
1594 if (t
->opcode_modifier
.jump
1595 || t
->opcode_modifier
.jumpbyte
1596 || t
->opcode_modifier
.jumpdword
1597 || t
->opcode_modifier
.jumpintersegment
)
1600 /* Check memory and accumulator operand size. */
1601 for (j
= 0; j
< i
.operands
; j
++)
1603 if (t
->operand_types
[j
].bitfield
.anysize
)
1606 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1612 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1621 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1624 i
.error
= operand_size_mismatch
;
1628 /* Check reverse. */
1629 gas_assert (i
.operands
== 2);
1632 for (j
= 0; j
< 2; j
++)
1634 if (t
->operand_types
[j
].bitfield
.acc
1635 && !match_reg_size (t
, j
? 0 : 1))
1638 if (i
.types
[j
].bitfield
.mem
1639 && !match_mem_size (t
, j
? 0 : 1))
1647 operand_type_match (i386_operand_type overlap
,
1648 i386_operand_type given
)
1650 i386_operand_type temp
= overlap
;
1652 temp
.bitfield
.jumpabsolute
= 0;
1653 temp
.bitfield
.unspecified
= 0;
1654 temp
.bitfield
.byte
= 0;
1655 temp
.bitfield
.word
= 0;
1656 temp
.bitfield
.dword
= 0;
1657 temp
.bitfield
.fword
= 0;
1658 temp
.bitfield
.qword
= 0;
1659 temp
.bitfield
.tbyte
= 0;
1660 temp
.bitfield
.xmmword
= 0;
1661 temp
.bitfield
.ymmword
= 0;
1662 if (operand_type_all_zero (&temp
))
1665 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1666 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1670 i
.error
= operand_type_mismatch
;
1674 /* If given types g0 and g1 are registers they must be of the same type
1675 unless the expected operand type register overlap is null.
1676 Note that Acc in a template matches every size of reg. */
1679 operand_type_register_match (i386_operand_type m0
,
1680 i386_operand_type g0
,
1681 i386_operand_type t0
,
1682 i386_operand_type m1
,
1683 i386_operand_type g1
,
1684 i386_operand_type t1
)
1686 if (!operand_type_check (g0
, reg
))
1689 if (!operand_type_check (g1
, reg
))
1692 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1693 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1694 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1695 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1698 if (m0
.bitfield
.acc
)
1700 t0
.bitfield
.reg8
= 1;
1701 t0
.bitfield
.reg16
= 1;
1702 t0
.bitfield
.reg32
= 1;
1703 t0
.bitfield
.reg64
= 1;
1706 if (m1
.bitfield
.acc
)
1708 t1
.bitfield
.reg8
= 1;
1709 t1
.bitfield
.reg16
= 1;
1710 t1
.bitfield
.reg32
= 1;
1711 t1
.bitfield
.reg64
= 1;
1714 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1715 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1716 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1717 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1720 i
.error
= register_type_mismatch
;
1725 static INLINE
unsigned int
1726 mode_from_disp_size (i386_operand_type t
)
1728 if (t
.bitfield
.disp8
)
1730 else if (t
.bitfield
.disp16
1731 || t
.bitfield
.disp32
1732 || t
.bitfield
.disp32s
)
1739 fits_in_signed_byte (offsetT num
)
1741 return (num
>= -128) && (num
<= 127);
1745 fits_in_unsigned_byte (offsetT num
)
1747 return (num
& 0xff) == num
;
1751 fits_in_unsigned_word (offsetT num
)
1753 return (num
& 0xffff) == num
;
1757 fits_in_signed_word (offsetT num
)
1759 return (-32768 <= num
) && (num
<= 32767);
1763 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1768 return (!(((offsetT
) -1 << 31) & num
)
1769 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1771 } /* fits_in_signed_long() */
1774 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1779 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1781 } /* fits_in_unsigned_long() */
1784 fits_in_imm4 (offsetT num
)
1786 return (num
& 0xf) == num
;
1789 static i386_operand_type
1790 smallest_imm_type (offsetT num
)
1792 i386_operand_type t
;
1794 operand_type_set (&t
, 0);
1795 t
.bitfield
.imm64
= 1;
1797 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1799 /* This code is disabled on the 486 because all the Imm1 forms
1800 in the opcode table are slower on the i486. They're the
1801 versions with the implicitly specified single-position
1802 displacement, which has another syntax if you really want to
1804 t
.bitfield
.imm1
= 1;
1805 t
.bitfield
.imm8
= 1;
1806 t
.bitfield
.imm8s
= 1;
1807 t
.bitfield
.imm16
= 1;
1808 t
.bitfield
.imm32
= 1;
1809 t
.bitfield
.imm32s
= 1;
1811 else if (fits_in_signed_byte (num
))
1813 t
.bitfield
.imm8
= 1;
1814 t
.bitfield
.imm8s
= 1;
1815 t
.bitfield
.imm16
= 1;
1816 t
.bitfield
.imm32
= 1;
1817 t
.bitfield
.imm32s
= 1;
1819 else if (fits_in_unsigned_byte (num
))
1821 t
.bitfield
.imm8
= 1;
1822 t
.bitfield
.imm16
= 1;
1823 t
.bitfield
.imm32
= 1;
1824 t
.bitfield
.imm32s
= 1;
1826 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1828 t
.bitfield
.imm16
= 1;
1829 t
.bitfield
.imm32
= 1;
1830 t
.bitfield
.imm32s
= 1;
1832 else if (fits_in_signed_long (num
))
1834 t
.bitfield
.imm32
= 1;
1835 t
.bitfield
.imm32s
= 1;
1837 else if (fits_in_unsigned_long (num
))
1838 t
.bitfield
.imm32
= 1;
1844 offset_in_range (offsetT val
, int size
)
1850 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1851 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1852 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1854 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1860 /* If BFD64, sign extend val for 32bit address mode. */
1861 if (flag_code
!= CODE_64BIT
1862 || i
.prefix
[ADDR_PREFIX
])
1863 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1864 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1867 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1869 char buf1
[40], buf2
[40];
1871 sprint_value (buf1
, val
);
1872 sprint_value (buf2
, val
& mask
);
1873 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1887 a. PREFIX_EXIST if attempting to add a prefix where one from the
1888 same class already exists.
1889 b. PREFIX_LOCK if lock prefix is added.
1890 c. PREFIX_REP if rep/repne prefix is added.
1891 d. PREFIX_OTHER if other prefix is added.
1894 static enum PREFIX_GROUP
1895 add_prefix (unsigned int prefix
)
1897 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
1900 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1901 && flag_code
== CODE_64BIT
)
1903 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1904 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1905 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1916 case CS_PREFIX_OPCODE
:
1917 case DS_PREFIX_OPCODE
:
1918 case ES_PREFIX_OPCODE
:
1919 case FS_PREFIX_OPCODE
:
1920 case GS_PREFIX_OPCODE
:
1921 case SS_PREFIX_OPCODE
:
1925 case REPNE_PREFIX_OPCODE
:
1926 case REPE_PREFIX_OPCODE
:
1931 case LOCK_PREFIX_OPCODE
:
1940 case ADDR_PREFIX_OPCODE
:
1944 case DATA_PREFIX_OPCODE
:
1948 if (i
.prefix
[q
] != 0)
1956 i
.prefix
[q
] |= prefix
;
1959 as_bad (_("same type of prefix used twice"));
1965 update_code_flag (int value
, int check
)
1967 PRINTF_LIKE ((*as_error
));
1969 flag_code
= (enum flag_code
) value
;
1970 if (flag_code
== CODE_64BIT
)
1972 cpu_arch_flags
.bitfield
.cpu64
= 1;
1973 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1977 cpu_arch_flags
.bitfield
.cpu64
= 0;
1978 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1980 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1983 as_error
= as_fatal
;
1986 (*as_error
) (_("64bit mode not supported on `%s'."),
1987 cpu_arch_name
? cpu_arch_name
: default_arch
);
1989 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1992 as_error
= as_fatal
;
1995 (*as_error
) (_("32bit mode not supported on `%s'."),
1996 cpu_arch_name
? cpu_arch_name
: default_arch
);
1998 stackop_size
= '\0';
2002 set_code_flag (int value
)
2004 update_code_flag (value
, 0);
2008 set_16bit_gcc_code_flag (int new_code_flag
)
2010 flag_code
= (enum flag_code
) new_code_flag
;
2011 if (flag_code
!= CODE_16BIT
)
2013 cpu_arch_flags
.bitfield
.cpu64
= 0;
2014 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2015 stackop_size
= LONG_MNEM_SUFFIX
;
2019 set_intel_syntax (int syntax_flag
)
2021 /* Find out if register prefixing is specified. */
2022 int ask_naked_reg
= 0;
2025 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2027 char *string
= input_line_pointer
;
2028 int e
= get_symbol_end ();
2030 if (strcmp (string
, "prefix") == 0)
2032 else if (strcmp (string
, "noprefix") == 0)
2035 as_bad (_("bad argument to syntax directive."));
2036 *input_line_pointer
= e
;
2038 demand_empty_rest_of_line ();
2040 intel_syntax
= syntax_flag
;
2042 if (ask_naked_reg
== 0)
2043 allow_naked_reg
= (intel_syntax
2044 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2046 allow_naked_reg
= (ask_naked_reg
< 0);
2048 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2050 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2051 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2052 register_prefix
= allow_naked_reg
? "" : "%";
2056 set_intel_mnemonic (int mnemonic_flag
)
2058 intel_mnemonic
= mnemonic_flag
;
2062 set_allow_index_reg (int flag
)
2064 allow_index_reg
= flag
;
2068 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
2072 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2074 char *string
= input_line_pointer
;
2075 int e
= get_symbol_end ();
2077 if (strcmp (string
, "none") == 0)
2078 sse_check
= sse_check_none
;
2079 else if (strcmp (string
, "warning") == 0)
2080 sse_check
= sse_check_warning
;
2081 else if (strcmp (string
, "error") == 0)
2082 sse_check
= sse_check_error
;
2084 as_bad (_("bad argument to sse_check directive."));
2085 *input_line_pointer
= e
;
2088 as_bad (_("missing argument for sse_check directive"));
2090 demand_empty_rest_of_line ();
2094 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2095 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2097 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2098 static const char *arch
;
2100 /* Intel LIOM is only supported on ELF. */
2106 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2107 use default_arch. */
2108 arch
= cpu_arch_name
;
2110 arch
= default_arch
;
2113 /* If we are targeting Intel L1OM, we must enable it. */
2114 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2115 || new_flag
.bitfield
.cpul1om
)
2118 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2123 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2127 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2129 char *string
= input_line_pointer
;
2130 int e
= get_symbol_end ();
2132 i386_cpu_flags flags
;
2134 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2136 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2138 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2142 cpu_arch_name
= cpu_arch
[j
].name
;
2143 cpu_sub_arch_name
= NULL
;
2144 cpu_arch_flags
= cpu_arch
[j
].flags
;
2145 if (flag_code
== CODE_64BIT
)
2147 cpu_arch_flags
.bitfield
.cpu64
= 1;
2148 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2152 cpu_arch_flags
.bitfield
.cpu64
= 0;
2153 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2155 cpu_arch_isa
= cpu_arch
[j
].type
;
2156 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2157 if (!cpu_arch_tune_set
)
2159 cpu_arch_tune
= cpu_arch_isa
;
2160 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2165 if (!cpu_arch
[j
].negated
)
2166 flags
= cpu_flags_or (cpu_arch_flags
,
2169 flags
= cpu_flags_and_not (cpu_arch_flags
,
2171 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2173 if (cpu_sub_arch_name
)
2175 char *name
= cpu_sub_arch_name
;
2176 cpu_sub_arch_name
= concat (name
,
2178 (const char *) NULL
);
2182 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2183 cpu_arch_flags
= flags
;
2184 cpu_arch_isa_flags
= flags
;
2186 *input_line_pointer
= e
;
2187 demand_empty_rest_of_line ();
2191 if (j
>= ARRAY_SIZE (cpu_arch
))
2192 as_bad (_("no such architecture: `%s'"), string
);
2194 *input_line_pointer
= e
;
2197 as_bad (_("missing cpu architecture"));
2199 no_cond_jump_promotion
= 0;
2200 if (*input_line_pointer
== ','
2201 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2203 char *string
= ++input_line_pointer
;
2204 int e
= get_symbol_end ();
2206 if (strcmp (string
, "nojumps") == 0)
2207 no_cond_jump_promotion
= 1;
2208 else if (strcmp (string
, "jumps") == 0)
2211 as_bad (_("no such architecture modifier: `%s'"), string
);
2213 *input_line_pointer
= e
;
2216 demand_empty_rest_of_line ();
2219 enum bfd_architecture
2222 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2224 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2225 || flag_code
!= CODE_64BIT
)
2226 as_fatal (_("Intel L1OM is 64bit ELF only"));
2227 return bfd_arch_l1om
;
2230 return bfd_arch_i386
;
2236 if (!strncmp (default_arch
, "x86_64", 6))
2238 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2240 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2241 || default_arch
[6] != '\0')
2242 as_fatal (_("Intel L1OM is 64bit ELF only"));
2243 return bfd_mach_l1om
;
2245 else if (default_arch
[6] == '\0')
2246 return bfd_mach_x86_64
;
2248 return bfd_mach_x64_32
;
2250 else if (!strcmp (default_arch
, "i386"))
2251 return bfd_mach_i386_i386
;
2253 as_fatal (_("unknown architecture"));
2259 const char *hash_err
;
2261 /* Initialize op_hash hash table. */
2262 op_hash
= hash_new ();
2265 const insn_template
*optab
;
2266 templates
*core_optab
;
2268 /* Setup for loop. */
2270 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2271 core_optab
->start
= optab
;
2276 if (optab
->name
== NULL
2277 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2279 /* different name --> ship out current template list;
2280 add to hash table; & begin anew. */
2281 core_optab
->end
= optab
;
2282 hash_err
= hash_insert (op_hash
,
2284 (void *) core_optab
);
2287 as_fatal (_("internal Error: Can't hash %s: %s"),
2291 if (optab
->name
== NULL
)
2293 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2294 core_optab
->start
= optab
;
2299 /* Initialize reg_hash hash table. */
2300 reg_hash
= hash_new ();
2302 const reg_entry
*regtab
;
2303 unsigned int regtab_size
= i386_regtab_size
;
2305 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2307 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2309 as_fatal (_("internal Error: Can't hash %s: %s"),
2315 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2320 for (c
= 0; c
< 256; c
++)
2325 mnemonic_chars
[c
] = c
;
2326 register_chars
[c
] = c
;
2327 operand_chars
[c
] = c
;
2329 else if (ISLOWER (c
))
2331 mnemonic_chars
[c
] = c
;
2332 register_chars
[c
] = c
;
2333 operand_chars
[c
] = c
;
2335 else if (ISUPPER (c
))
2337 mnemonic_chars
[c
] = TOLOWER (c
);
2338 register_chars
[c
] = mnemonic_chars
[c
];
2339 operand_chars
[c
] = c
;
2342 if (ISALPHA (c
) || ISDIGIT (c
))
2343 identifier_chars
[c
] = c
;
2346 identifier_chars
[c
] = c
;
2347 operand_chars
[c
] = c
;
2352 identifier_chars
['@'] = '@';
2355 identifier_chars
['?'] = '?';
2356 operand_chars
['?'] = '?';
2358 digit_chars
['-'] = '-';
2359 mnemonic_chars
['_'] = '_';
2360 mnemonic_chars
['-'] = '-';
2361 mnemonic_chars
['.'] = '.';
2362 identifier_chars
['_'] = '_';
2363 identifier_chars
['.'] = '.';
2365 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2366 operand_chars
[(unsigned char) *p
] = *p
;
2369 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2372 record_alignment (text_section
, 2);
2373 record_alignment (data_section
, 2);
2374 record_alignment (bss_section
, 2);
2378 if (flag_code
== CODE_64BIT
)
2380 #if defined (OBJ_COFF) && defined (TE_PE)
2381 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2384 x86_dwarf2_return_column
= 16;
2386 x86_cie_data_alignment
= -8;
2390 x86_dwarf2_return_column
= 8;
2391 x86_cie_data_alignment
= -4;
2396 i386_print_statistics (FILE *file
)
2398 hash_print_statistics (file
, "i386 opcode", op_hash
);
2399 hash_print_statistics (file
, "i386 register", reg_hash
);
2404 /* Debugging routines for md_assemble. */
2405 static void pte (insn_template
*);
2406 static void pt (i386_operand_type
);
2407 static void pe (expressionS
*);
2408 static void ps (symbolS
*);
2411 pi (char *line
, i386_insn
*x
)
2415 fprintf (stdout
, "%s: template ", line
);
2417 fprintf (stdout
, " address: base %s index %s scale %x\n",
2418 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2419 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2420 x
->log2_scale_factor
);
2421 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2422 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2423 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2424 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2425 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2426 (x
->rex
& REX_W
) != 0,
2427 (x
->rex
& REX_R
) != 0,
2428 (x
->rex
& REX_X
) != 0,
2429 (x
->rex
& REX_B
) != 0);
2430 for (j
= 0; j
< x
->operands
; j
++)
2432 fprintf (stdout
, " #%d: ", j
+ 1);
2434 fprintf (stdout
, "\n");
2435 if (x
->types
[j
].bitfield
.reg8
2436 || x
->types
[j
].bitfield
.reg16
2437 || x
->types
[j
].bitfield
.reg32
2438 || x
->types
[j
].bitfield
.reg64
2439 || x
->types
[j
].bitfield
.regmmx
2440 || x
->types
[j
].bitfield
.regxmm
2441 || x
->types
[j
].bitfield
.regymm
2442 || x
->types
[j
].bitfield
.sreg2
2443 || x
->types
[j
].bitfield
.sreg3
2444 || x
->types
[j
].bitfield
.control
2445 || x
->types
[j
].bitfield
.debug
2446 || x
->types
[j
].bitfield
.test
)
2447 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2448 if (operand_type_check (x
->types
[j
], imm
))
2450 if (operand_type_check (x
->types
[j
], disp
))
2451 pe (x
->op
[j
].disps
);
2456 pte (insn_template
*t
)
2459 fprintf (stdout
, " %d operands ", t
->operands
);
2460 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2461 if (t
->extension_opcode
!= None
)
2462 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2463 if (t
->opcode_modifier
.d
)
2464 fprintf (stdout
, "D");
2465 if (t
->opcode_modifier
.w
)
2466 fprintf (stdout
, "W");
2467 fprintf (stdout
, "\n");
2468 for (j
= 0; j
< t
->operands
; j
++)
2470 fprintf (stdout
, " #%d type ", j
+ 1);
2471 pt (t
->operand_types
[j
]);
2472 fprintf (stdout
, "\n");
2479 fprintf (stdout
, " operation %d\n", e
->X_op
);
2480 fprintf (stdout
, " add_number %ld (%lx)\n",
2481 (long) e
->X_add_number
, (long) e
->X_add_number
);
2482 if (e
->X_add_symbol
)
2484 fprintf (stdout
, " add_symbol ");
2485 ps (e
->X_add_symbol
);
2486 fprintf (stdout
, "\n");
2490 fprintf (stdout
, " op_symbol ");
2491 ps (e
->X_op_symbol
);
2492 fprintf (stdout
, "\n");
2499 fprintf (stdout
, "%s type %s%s",
2501 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2502 segment_name (S_GET_SEGMENT (s
)));
2505 static struct type_name
2507 i386_operand_type mask
;
2510 const type_names
[] =
2512 { OPERAND_TYPE_REG8
, "r8" },
2513 { OPERAND_TYPE_REG16
, "r16" },
2514 { OPERAND_TYPE_REG32
, "r32" },
2515 { OPERAND_TYPE_REG64
, "r64" },
2516 { OPERAND_TYPE_IMM8
, "i8" },
2517 { OPERAND_TYPE_IMM8
, "i8s" },
2518 { OPERAND_TYPE_IMM16
, "i16" },
2519 { OPERAND_TYPE_IMM32
, "i32" },
2520 { OPERAND_TYPE_IMM32S
, "i32s" },
2521 { OPERAND_TYPE_IMM64
, "i64" },
2522 { OPERAND_TYPE_IMM1
, "i1" },
2523 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2524 { OPERAND_TYPE_DISP8
, "d8" },
2525 { OPERAND_TYPE_DISP16
, "d16" },
2526 { OPERAND_TYPE_DISP32
, "d32" },
2527 { OPERAND_TYPE_DISP32S
, "d32s" },
2528 { OPERAND_TYPE_DISP64
, "d64" },
2529 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2530 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2531 { OPERAND_TYPE_CONTROL
, "control reg" },
2532 { OPERAND_TYPE_TEST
, "test reg" },
2533 { OPERAND_TYPE_DEBUG
, "debug reg" },
2534 { OPERAND_TYPE_FLOATREG
, "FReg" },
2535 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2536 { OPERAND_TYPE_SREG2
, "SReg2" },
2537 { OPERAND_TYPE_SREG3
, "SReg3" },
2538 { OPERAND_TYPE_ACC
, "Acc" },
2539 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2540 { OPERAND_TYPE_REGMMX
, "rMMX" },
2541 { OPERAND_TYPE_REGXMM
, "rXMM" },
2542 { OPERAND_TYPE_REGYMM
, "rYMM" },
2543 { OPERAND_TYPE_ESSEG
, "es" },
2547 pt (i386_operand_type t
)
2550 i386_operand_type a
;
2552 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2554 a
= operand_type_and (t
, type_names
[j
].mask
);
2555 if (!operand_type_all_zero (&a
))
2556 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2561 #endif /* DEBUG386 */
2563 static bfd_reloc_code_real_type
2564 reloc (unsigned int size
,
2567 bfd_reloc_code_real_type other
)
2569 if (other
!= NO_RELOC
)
2571 reloc_howto_type
*rel
;
2576 case BFD_RELOC_X86_64_GOT32
:
2577 return BFD_RELOC_X86_64_GOT64
;
2579 case BFD_RELOC_X86_64_PLTOFF64
:
2580 return BFD_RELOC_X86_64_PLTOFF64
;
2582 case BFD_RELOC_X86_64_GOTPC32
:
2583 other
= BFD_RELOC_X86_64_GOTPC64
;
2585 case BFD_RELOC_X86_64_GOTPCREL
:
2586 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2588 case BFD_RELOC_X86_64_TPOFF32
:
2589 other
= BFD_RELOC_X86_64_TPOFF64
;
2591 case BFD_RELOC_X86_64_DTPOFF32
:
2592 other
= BFD_RELOC_X86_64_DTPOFF64
;
2598 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2599 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2602 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2604 as_bad (_("unknown relocation (%u)"), other
);
2605 else if (size
!= bfd_get_reloc_size (rel
))
2606 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2607 bfd_get_reloc_size (rel
),
2609 else if (pcrel
&& !rel
->pc_relative
)
2610 as_bad (_("non-pc-relative relocation for pc-relative field"));
2611 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2613 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2615 as_bad (_("relocated field and relocation type differ in signedness"));
2624 as_bad (_("there are no unsigned pc-relative relocations"));
2627 case 1: return BFD_RELOC_8_PCREL
;
2628 case 2: return BFD_RELOC_16_PCREL
;
2629 case 4: return BFD_RELOC_32_PCREL
;
2630 case 8: return BFD_RELOC_64_PCREL
;
2632 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2639 case 4: return BFD_RELOC_X86_64_32S
;
2644 case 1: return BFD_RELOC_8
;
2645 case 2: return BFD_RELOC_16
;
2646 case 4: return BFD_RELOC_32
;
2647 case 8: return BFD_RELOC_64
;
2649 as_bad (_("cannot do %s %u byte relocation"),
2650 sign
> 0 ? "signed" : "unsigned", size
);
2656 /* Here we decide which fixups can be adjusted to make them relative to
2657 the beginning of the section instead of the symbol. Basically we need
2658 to make sure that the dynamic relocations are done correctly, so in
2659 some cases we force the original symbol to be used. */
2662 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2664 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2668 /* Don't adjust pc-relative references to merge sections in 64-bit
2670 if (use_rela_relocations
2671 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2675 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2676 and changed later by validate_fix. */
2677 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2678 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2681 /* adjust_reloc_syms doesn't know about the GOT. */
2682 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2683 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2684 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2685 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2686 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2687 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2688 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2689 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2690 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2691 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2692 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2693 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2694 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2695 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2696 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2697 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2698 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2699 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2700 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2701 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2702 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2703 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2704 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2705 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2706 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2707 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2708 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2709 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2716 intel_float_operand (const char *mnemonic
)
2718 /* Note that the value returned is meaningful only for opcodes with (memory)
2719 operands, hence the code here is free to improperly handle opcodes that
2720 have no operands (for better performance and smaller code). */
2722 if (mnemonic
[0] != 'f')
2723 return 0; /* non-math */
2725 switch (mnemonic
[1])
2727 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2728 the fs segment override prefix not currently handled because no
2729 call path can make opcodes without operands get here */
2731 return 2 /* integer op */;
2733 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2734 return 3; /* fldcw/fldenv */
2737 if (mnemonic
[2] != 'o' /* fnop */)
2738 return 3; /* non-waiting control op */
2741 if (mnemonic
[2] == 's')
2742 return 3; /* frstor/frstpm */
2745 if (mnemonic
[2] == 'a')
2746 return 3; /* fsave */
2747 if (mnemonic
[2] == 't')
2749 switch (mnemonic
[3])
2751 case 'c': /* fstcw */
2752 case 'd': /* fstdw */
2753 case 'e': /* fstenv */
2754 case 's': /* fsts[gw] */
2760 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2761 return 0; /* fxsave/fxrstor are not really math ops */
2768 /* Build the VEX prefix. */
2771 build_vex_prefix (const insn_template
*t
)
2773 unsigned int register_specifier
;
2774 unsigned int implied_prefix
;
2775 unsigned int vector_length
;
2777 /* Check register specifier. */
2778 if (i
.vex
.register_specifier
)
2780 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2781 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2782 register_specifier
+= 8;
2783 register_specifier
= ~register_specifier
& 0xf;
2786 register_specifier
= 0xf;
2788 /* Use 2-byte VEX prefix by swappping destination and source
2791 && i
.operands
== i
.reg_operands
2792 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2793 && i
.tm
.opcode_modifier
.s
2796 unsigned int xchg
= i
.operands
- 1;
2797 union i386_op temp_op
;
2798 i386_operand_type temp_type
;
2800 temp_type
= i
.types
[xchg
];
2801 i
.types
[xchg
] = i
.types
[0];
2802 i
.types
[0] = temp_type
;
2803 temp_op
= i
.op
[xchg
];
2804 i
.op
[xchg
] = i
.op
[0];
2807 gas_assert (i
.rm
.mode
== 3);
2811 i
.rm
.regmem
= i
.rm
.reg
;
2814 /* Use the next insn. */
2818 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
2819 vector_length
= avxscalar
;
2821 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
2823 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2828 case DATA_PREFIX_OPCODE
:
2831 case REPE_PREFIX_OPCODE
:
2834 case REPNE_PREFIX_OPCODE
:
2841 /* Use 2-byte VEX prefix if possible. */
2842 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2843 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
2844 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2846 /* 2-byte VEX prefix. */
2850 i
.vex
.bytes
[0] = 0xc5;
2852 /* Check the REX.R bit. */
2853 r
= (i
.rex
& REX_R
) ? 0 : 1;
2854 i
.vex
.bytes
[1] = (r
<< 7
2855 | register_specifier
<< 3
2856 | vector_length
<< 2
2861 /* 3-byte VEX prefix. */
2866 switch (i
.tm
.opcode_modifier
.vexopcode
)
2870 i
.vex
.bytes
[0] = 0xc4;
2874 i
.vex
.bytes
[0] = 0xc4;
2878 i
.vex
.bytes
[0] = 0xc4;
2882 i
.vex
.bytes
[0] = 0x8f;
2886 i
.vex
.bytes
[0] = 0x8f;
2890 i
.vex
.bytes
[0] = 0x8f;
2896 /* The high 3 bits of the second VEX byte are 1's compliment
2897 of RXB bits from REX. */
2898 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2900 /* Check the REX.W bit. */
2901 w
= (i
.rex
& REX_W
) ? 1 : 0;
2902 if (i
.tm
.opcode_modifier
.vexw
)
2907 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
2911 i
.vex
.bytes
[2] = (w
<< 7
2912 | register_specifier
<< 3
2913 | vector_length
<< 2
2919 process_immext (void)
2923 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2925 /* SSE3 Instructions have the fixed operands with an opcode
2926 suffix which is coded in the same place as an 8-bit immediate
2927 field would be. Here we check those operands and remove them
2931 for (x
= 0; x
< i
.operands
; x
++)
2932 if (i
.op
[x
].regs
->reg_num
!= x
)
2933 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2934 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2940 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2941 which is coded in the same place as an 8-bit immediate field
2942 would be. Here we fake an 8-bit immediate operand from the
2943 opcode suffix stored in tm.extension_opcode.
2945 AVX instructions also use this encoding, for some of
2946 3 argument instructions. */
2948 gas_assert (i
.imm_operands
== 0
2950 || (i
.tm
.opcode_modifier
.vex
2951 && i
.operands
<= 4)));
2953 exp
= &im_expressions
[i
.imm_operands
++];
2954 i
.op
[i
.operands
].imms
= exp
;
2955 i
.types
[i
.operands
] = imm8
;
2957 exp
->X_op
= O_constant
;
2958 exp
->X_add_number
= i
.tm
.extension_opcode
;
2959 i
.tm
.extension_opcode
= None
;
2962 /* This is the guts of the machine-dependent assembler. LINE points to a
2963 machine dependent instruction. This function is supposed to emit
2964 the frags/bytes it assembles to. */
2967 md_assemble (char *line
)
2970 char mnemonic
[MAX_MNEM_SIZE
];
2971 const insn_template
*t
;
2973 /* Initialize globals. */
2974 memset (&i
, '\0', sizeof (i
));
2975 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2976 i
.reloc
[j
] = NO_RELOC
;
2977 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2978 memset (im_expressions
, '\0', sizeof (im_expressions
));
2979 save_stack_p
= save_stack
;
2981 /* First parse an instruction mnemonic & call i386_operand for the operands.
2982 We assume that the scrubber has arranged it so that line[0] is the valid
2983 start of a (possibly prefixed) mnemonic. */
2985 line
= parse_insn (line
, mnemonic
);
2989 line
= parse_operands (line
, mnemonic
);
2994 /* Now we've parsed the mnemonic into a set of templates, and have the
2995 operands at hand. */
2997 /* All intel opcodes have reversed operands except for "bound" and
2998 "enter". We also don't reverse intersegment "jmp" and "call"
2999 instructions with 2 immediate operands so that the immediate segment
3000 precedes the offset, as it does when in AT&T mode. */
3003 && (strcmp (mnemonic
, "bound") != 0)
3004 && (strcmp (mnemonic
, "invlpga") != 0)
3005 && !(operand_type_check (i
.types
[0], imm
)
3006 && operand_type_check (i
.types
[1], imm
)))
3009 /* The order of the immediates should be reversed
3010 for 2 immediates extrq and insertq instructions */
3011 if (i
.imm_operands
== 2
3012 && (strcmp (mnemonic
, "extrq") == 0
3013 || strcmp (mnemonic
, "insertq") == 0))
3014 swap_2_operands (0, 1);
3019 /* Don't optimize displacement for movabs since it only takes 64bit
3022 && !i
.disp32_encoding
3023 && (flag_code
!= CODE_64BIT
3024 || strcmp (mnemonic
, "movabs") != 0))
3027 /* Next, we find a template that matches the given insn,
3028 making sure the overlap of the given operands types is consistent
3029 with the template operand types. */
3031 if (!(t
= match_template ()))
3034 if (sse_check
!= sse_check_none
3035 && !i
.tm
.opcode_modifier
.noavx
3036 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3037 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3038 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3039 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3040 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3041 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3043 (sse_check
== sse_check_warning
3045 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3048 /* Zap movzx and movsx suffix. The suffix has been set from
3049 "word ptr" or "byte ptr" on the source operand in Intel syntax
3050 or extracted from mnemonic in AT&T syntax. But we'll use
3051 the destination register to choose the suffix for encoding. */
3052 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3054 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3055 there is no suffix, the default will be byte extension. */
3056 if (i
.reg_operands
!= 2
3059 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3064 if (i
.tm
.opcode_modifier
.fwait
)
3065 if (!add_prefix (FWAIT_OPCODE
))
3068 /* Check for lock without a lockable instruction. Destination operand
3069 must be memory unless it is xchg (0x86). */
3070 if (i
.prefix
[LOCK_PREFIX
]
3071 && (!i
.tm
.opcode_modifier
.islockable
3072 || i
.mem_operands
== 0
3073 || (i
.tm
.base_opcode
!= 0x86
3074 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3076 as_bad (_("expecting lockable instruction after `lock'"));
3080 /* Check string instruction segment overrides. */
3081 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3083 if (!check_string ())
3085 i
.disp_operands
= 0;
3088 if (!process_suffix ())
3091 /* Update operand types. */
3092 for (j
= 0; j
< i
.operands
; j
++)
3093 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3095 /* Make still unresolved immediate matches conform to size of immediate
3096 given in i.suffix. */
3097 if (!finalize_imm ())
3100 if (i
.types
[0].bitfield
.imm1
)
3101 i
.imm_operands
= 0; /* kludge for shift insns. */
3103 /* We only need to check those implicit registers for instructions
3104 with 3 operands or less. */
3105 if (i
.operands
<= 3)
3106 for (j
= 0; j
< i
.operands
; j
++)
3107 if (i
.types
[j
].bitfield
.inoutportreg
3108 || i
.types
[j
].bitfield
.shiftcount
3109 || i
.types
[j
].bitfield
.acc
3110 || i
.types
[j
].bitfield
.floatacc
)
3113 /* ImmExt should be processed after SSE2AVX. */
3114 if (!i
.tm
.opcode_modifier
.sse2avx
3115 && i
.tm
.opcode_modifier
.immext
)
3118 /* For insns with operands there are more diddles to do to the opcode. */
3121 if (!process_operands ())
3124 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3126 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3127 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3130 if (i
.tm
.opcode_modifier
.vex
)
3131 build_vex_prefix (t
);
3133 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3134 instructions may define INT_OPCODE as well, so avoid this corner
3135 case for those instructions that use MODRM. */
3136 if (i
.tm
.base_opcode
== INT_OPCODE
3137 && !i
.tm
.opcode_modifier
.modrm
3138 && i
.op
[0].imms
->X_add_number
== 3)
3140 i
.tm
.base_opcode
= INT3_OPCODE
;
3144 if ((i
.tm
.opcode_modifier
.jump
3145 || i
.tm
.opcode_modifier
.jumpbyte
3146 || i
.tm
.opcode_modifier
.jumpdword
)
3147 && i
.op
[0].disps
->X_op
== O_constant
)
3149 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3150 the absolute address given by the constant. Since ix86 jumps and
3151 calls are pc relative, we need to generate a reloc. */
3152 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3153 i
.op
[0].disps
->X_op
= O_symbol
;
3156 if (i
.tm
.opcode_modifier
.rex64
)
3159 /* For 8 bit registers we need an empty rex prefix. Also if the
3160 instruction already has a prefix, we need to convert old
3161 registers to new ones. */
3163 if ((i
.types
[0].bitfield
.reg8
3164 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3165 || (i
.types
[1].bitfield
.reg8
3166 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3167 || ((i
.types
[0].bitfield
.reg8
3168 || i
.types
[1].bitfield
.reg8
)
3173 i
.rex
|= REX_OPCODE
;
3174 for (x
= 0; x
< 2; x
++)
3176 /* Look for 8 bit operand that uses old registers. */
3177 if (i
.types
[x
].bitfield
.reg8
3178 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3180 /* In case it is "hi" register, give up. */
3181 if (i
.op
[x
].regs
->reg_num
> 3)
3182 as_bad (_("can't encode register '%s%s' in an "
3183 "instruction requiring REX prefix."),
3184 register_prefix
, i
.op
[x
].regs
->reg_name
);
3186 /* Otherwise it is equivalent to the extended register.
3187 Since the encoding doesn't change this is merely
3188 cosmetic cleanup for debug output. */
3190 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3196 add_prefix (REX_OPCODE
| i
.rex
);
3198 /* We are ready to output the insn. */
3203 parse_insn (char *line
, char *mnemonic
)
3206 char *token_start
= l
;
3209 const insn_template
*t
;
3212 /* Non-zero if we found a prefix only acceptable with string insns. */
3213 const char *expecting_string_instruction
= NULL
;
3218 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3223 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3225 as_bad (_("no such instruction: `%s'"), token_start
);
3230 if (!is_space_char (*l
)
3231 && *l
!= END_OF_INSN
3233 || (*l
!= PREFIX_SEPARATOR
3236 as_bad (_("invalid character %s in mnemonic"),
3237 output_invalid (*l
));
3240 if (token_start
== l
)
3242 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3243 as_bad (_("expecting prefix; got nothing"));
3245 as_bad (_("expecting mnemonic; got nothing"));
3249 /* Look up instruction (or prefix) via hash table. */
3250 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3252 if (*l
!= END_OF_INSN
3253 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3254 && current_templates
3255 && current_templates
->start
->opcode_modifier
.isprefix
)
3257 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3259 as_bad ((flag_code
!= CODE_64BIT
3260 ? _("`%s' is only supported in 64-bit mode")
3261 : _("`%s' is not supported in 64-bit mode")),
3262 current_templates
->start
->name
);
3265 /* If we are in 16-bit mode, do not allow addr16 or data16.
3266 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3267 if ((current_templates
->start
->opcode_modifier
.size16
3268 || current_templates
->start
->opcode_modifier
.size32
)
3269 && flag_code
!= CODE_64BIT
3270 && (current_templates
->start
->opcode_modifier
.size32
3271 ^ (flag_code
== CODE_16BIT
)))
3273 as_bad (_("redundant %s prefix"),
3274 current_templates
->start
->name
);
3277 /* Add prefix, checking for repeated prefixes. */
3278 switch (add_prefix (current_templates
->start
->base_opcode
))
3283 expecting_string_instruction
= current_templates
->start
->name
;
3288 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3295 if (!current_templates
)
3297 /* Check if we should swap operand or force 32bit displacement in
3299 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3301 else if (mnem_p
- 4 == dot_p
3305 i
.disp32_encoding
= 1;
3310 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3313 if (!current_templates
)
3316 /* See if we can get a match by trimming off a suffix. */
3319 case WORD_MNEM_SUFFIX
:
3320 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3321 i
.suffix
= SHORT_MNEM_SUFFIX
;
3323 case BYTE_MNEM_SUFFIX
:
3324 case QWORD_MNEM_SUFFIX
:
3325 i
.suffix
= mnem_p
[-1];
3327 current_templates
= (const templates
*) hash_find (op_hash
,
3330 case SHORT_MNEM_SUFFIX
:
3331 case LONG_MNEM_SUFFIX
:
3334 i
.suffix
= mnem_p
[-1];
3336 current_templates
= (const templates
*) hash_find (op_hash
,
3345 if (intel_float_operand (mnemonic
) == 1)
3346 i
.suffix
= SHORT_MNEM_SUFFIX
;
3348 i
.suffix
= LONG_MNEM_SUFFIX
;
3350 current_templates
= (const templates
*) hash_find (op_hash
,
3355 if (!current_templates
)
3357 as_bad (_("no such instruction: `%s'"), token_start
);
3362 if (current_templates
->start
->opcode_modifier
.jump
3363 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3365 /* Check for a branch hint. We allow ",pt" and ",pn" for
3366 predict taken and predict not taken respectively.
3367 I'm not sure that branch hints actually do anything on loop
3368 and jcxz insns (JumpByte) for current Pentium4 chips. They
3369 may work in the future and it doesn't hurt to accept them
3371 if (l
[0] == ',' && l
[1] == 'p')
3375 if (!add_prefix (DS_PREFIX_OPCODE
))
3379 else if (l
[2] == 'n')
3381 if (!add_prefix (CS_PREFIX_OPCODE
))
3387 /* Any other comma loses. */
3390 as_bad (_("invalid character %s in mnemonic"),
3391 output_invalid (*l
));
3395 /* Check if instruction is supported on specified architecture. */
3397 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3399 supported
|= cpu_flags_match (t
);
3400 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3404 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3406 as_bad (flag_code
== CODE_64BIT
3407 ? _("`%s' is not supported in 64-bit mode")
3408 : _("`%s' is only supported in 64-bit mode"),
3409 current_templates
->start
->name
);
3412 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3414 as_bad (_("`%s' is not supported on `%s%s'"),
3415 current_templates
->start
->name
,
3416 cpu_arch_name
? cpu_arch_name
: default_arch
,
3417 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3422 if (!cpu_arch_flags
.bitfield
.cpui386
3423 && (flag_code
!= CODE_16BIT
))
3425 as_warn (_("use .code16 to ensure correct addressing mode"));
3428 /* Check for rep/repne without a string instruction. */
3429 if (expecting_string_instruction
)
3431 static templates override
;
3433 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3434 if (t
->opcode_modifier
.isstring
)
3436 if (t
>= current_templates
->end
)
3438 as_bad (_("expecting string instruction after `%s'"),
3439 expecting_string_instruction
);
3442 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3443 if (!t
->opcode_modifier
.isstring
)
3446 current_templates
= &override
;
3453 parse_operands (char *l
, const char *mnemonic
)
3457 /* 1 if operand is pending after ','. */
3458 unsigned int expecting_operand
= 0;
3460 /* Non-zero if operand parens not balanced. */
3461 unsigned int paren_not_balanced
;
3463 while (*l
!= END_OF_INSN
)
3465 /* Skip optional white space before operand. */
3466 if (is_space_char (*l
))
3468 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3470 as_bad (_("invalid character %s before operand %d"),
3471 output_invalid (*l
),
3475 token_start
= l
; /* after white space */
3476 paren_not_balanced
= 0;
3477 while (paren_not_balanced
|| *l
!= ',')
3479 if (*l
== END_OF_INSN
)
3481 if (paren_not_balanced
)
3484 as_bad (_("unbalanced parenthesis in operand %d."),
3487 as_bad (_("unbalanced brackets in operand %d."),
3492 break; /* we are done */
3494 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3496 as_bad (_("invalid character %s in operand %d"),
3497 output_invalid (*l
),
3504 ++paren_not_balanced
;
3506 --paren_not_balanced
;
3511 ++paren_not_balanced
;
3513 --paren_not_balanced
;
3517 if (l
!= token_start
)
3518 { /* Yes, we've read in another operand. */
3519 unsigned int operand_ok
;
3520 this_operand
= i
.operands
++;
3521 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3522 if (i
.operands
> MAX_OPERANDS
)
3524 as_bad (_("spurious operands; (%d operands/instruction max)"),
3528 /* Now parse operand adding info to 'i' as we go along. */
3529 END_STRING_AND_SAVE (l
);
3533 i386_intel_operand (token_start
,
3534 intel_float_operand (mnemonic
));
3536 operand_ok
= i386_att_operand (token_start
);
3538 RESTORE_END_STRING (l
);
3544 if (expecting_operand
)
3546 expecting_operand_after_comma
:
3547 as_bad (_("expecting operand after ','; got nothing"));
3552 as_bad (_("expecting operand before ','; got nothing"));
3557 /* Now *l must be either ',' or END_OF_INSN. */
3560 if (*++l
== END_OF_INSN
)
3562 /* Just skip it, if it's \n complain. */
3563 goto expecting_operand_after_comma
;
3565 expecting_operand
= 1;
3572 swap_2_operands (int xchg1
, int xchg2
)
3574 union i386_op temp_op
;
3575 i386_operand_type temp_type
;
3576 enum bfd_reloc_code_real temp_reloc
;
3578 temp_type
= i
.types
[xchg2
];
3579 i
.types
[xchg2
] = i
.types
[xchg1
];
3580 i
.types
[xchg1
] = temp_type
;
3581 temp_op
= i
.op
[xchg2
];
3582 i
.op
[xchg2
] = i
.op
[xchg1
];
3583 i
.op
[xchg1
] = temp_op
;
3584 temp_reloc
= i
.reloc
[xchg2
];
3585 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3586 i
.reloc
[xchg1
] = temp_reloc
;
3590 swap_operands (void)
3596 swap_2_operands (1, i
.operands
- 2);
3599 swap_2_operands (0, i
.operands
- 1);
3605 if (i
.mem_operands
== 2)
3607 const seg_entry
*temp_seg
;
3608 temp_seg
= i
.seg
[0];
3609 i
.seg
[0] = i
.seg
[1];
3610 i
.seg
[1] = temp_seg
;
3614 /* Try to ensure constant immediates are represented in the smallest
3619 char guess_suffix
= 0;
3623 guess_suffix
= i
.suffix
;
3624 else if (i
.reg_operands
)
3626 /* Figure out a suffix from the last register operand specified.
3627 We can't do this properly yet, ie. excluding InOutPortReg,
3628 but the following works for instructions with immediates.
3629 In any case, we can't set i.suffix yet. */
3630 for (op
= i
.operands
; --op
>= 0;)
3631 if (i
.types
[op
].bitfield
.reg8
)
3633 guess_suffix
= BYTE_MNEM_SUFFIX
;
3636 else if (i
.types
[op
].bitfield
.reg16
)
3638 guess_suffix
= WORD_MNEM_SUFFIX
;
3641 else if (i
.types
[op
].bitfield
.reg32
)
3643 guess_suffix
= LONG_MNEM_SUFFIX
;
3646 else if (i
.types
[op
].bitfield
.reg64
)
3648 guess_suffix
= QWORD_MNEM_SUFFIX
;
3652 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3653 guess_suffix
= WORD_MNEM_SUFFIX
;
3655 for (op
= i
.operands
; --op
>= 0;)
3656 if (operand_type_check (i
.types
[op
], imm
))
3658 switch (i
.op
[op
].imms
->X_op
)
3661 /* If a suffix is given, this operand may be shortened. */
3662 switch (guess_suffix
)
3664 case LONG_MNEM_SUFFIX
:
3665 i
.types
[op
].bitfield
.imm32
= 1;
3666 i
.types
[op
].bitfield
.imm64
= 1;
3668 case WORD_MNEM_SUFFIX
:
3669 i
.types
[op
].bitfield
.imm16
= 1;
3670 i
.types
[op
].bitfield
.imm32
= 1;
3671 i
.types
[op
].bitfield
.imm32s
= 1;
3672 i
.types
[op
].bitfield
.imm64
= 1;
3674 case BYTE_MNEM_SUFFIX
:
3675 i
.types
[op
].bitfield
.imm8
= 1;
3676 i
.types
[op
].bitfield
.imm8s
= 1;
3677 i
.types
[op
].bitfield
.imm16
= 1;
3678 i
.types
[op
].bitfield
.imm32
= 1;
3679 i
.types
[op
].bitfield
.imm32s
= 1;
3680 i
.types
[op
].bitfield
.imm64
= 1;
3684 /* If this operand is at most 16 bits, convert it
3685 to a signed 16 bit number before trying to see
3686 whether it will fit in an even smaller size.
3687 This allows a 16-bit operand such as $0xffe0 to
3688 be recognised as within Imm8S range. */
3689 if ((i
.types
[op
].bitfield
.imm16
)
3690 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3692 i
.op
[op
].imms
->X_add_number
=
3693 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3695 if ((i
.types
[op
].bitfield
.imm32
)
3696 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3699 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3700 ^ ((offsetT
) 1 << 31))
3701 - ((offsetT
) 1 << 31));
3704 = operand_type_or (i
.types
[op
],
3705 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3707 /* We must avoid matching of Imm32 templates when 64bit
3708 only immediate is available. */
3709 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3710 i
.types
[op
].bitfield
.imm32
= 0;
3717 /* Symbols and expressions. */
3719 /* Convert symbolic operand to proper sizes for matching, but don't
3720 prevent matching a set of insns that only supports sizes other
3721 than those matching the insn suffix. */
3723 i386_operand_type mask
, allowed
;
3724 const insn_template
*t
;
3726 operand_type_set (&mask
, 0);
3727 operand_type_set (&allowed
, 0);
3729 for (t
= current_templates
->start
;
3730 t
< current_templates
->end
;
3732 allowed
= operand_type_or (allowed
,
3733 t
->operand_types
[op
]);
3734 switch (guess_suffix
)
3736 case QWORD_MNEM_SUFFIX
:
3737 mask
.bitfield
.imm64
= 1;
3738 mask
.bitfield
.imm32s
= 1;
3740 case LONG_MNEM_SUFFIX
:
3741 mask
.bitfield
.imm32
= 1;
3743 case WORD_MNEM_SUFFIX
:
3744 mask
.bitfield
.imm16
= 1;
3746 case BYTE_MNEM_SUFFIX
:
3747 mask
.bitfield
.imm8
= 1;
3752 allowed
= operand_type_and (mask
, allowed
);
3753 if (!operand_type_all_zero (&allowed
))
3754 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3761 /* Try to use the smallest displacement type too. */
3763 optimize_disp (void)
3767 for (op
= i
.operands
; --op
>= 0;)
3768 if (operand_type_check (i
.types
[op
], disp
))
3770 if (i
.op
[op
].disps
->X_op
== O_constant
)
3772 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
3774 if (i
.types
[op
].bitfield
.disp16
3775 && (op_disp
& ~(offsetT
) 0xffff) == 0)
3777 /* If this operand is at most 16 bits, convert
3778 to a signed 16 bit number and don't use 64bit
3780 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
3781 i
.types
[op
].bitfield
.disp64
= 0;
3783 if (i
.types
[op
].bitfield
.disp32
3784 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3786 /* If this operand is at most 32 bits, convert
3787 to a signed 32 bit number and don't use 64bit
3789 op_disp
&= (((offsetT
) 2 << 31) - 1);
3790 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3791 i
.types
[op
].bitfield
.disp64
= 0;
3793 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
3795 i
.types
[op
].bitfield
.disp8
= 0;
3796 i
.types
[op
].bitfield
.disp16
= 0;
3797 i
.types
[op
].bitfield
.disp32
= 0;
3798 i
.types
[op
].bitfield
.disp32s
= 0;
3799 i
.types
[op
].bitfield
.disp64
= 0;
3803 else if (flag_code
== CODE_64BIT
)
3805 if (fits_in_signed_long (op_disp
))
3807 i
.types
[op
].bitfield
.disp64
= 0;
3808 i
.types
[op
].bitfield
.disp32s
= 1;
3810 if (i
.prefix
[ADDR_PREFIX
]
3811 && fits_in_unsigned_long (op_disp
))
3812 i
.types
[op
].bitfield
.disp32
= 1;
3814 if ((i
.types
[op
].bitfield
.disp32
3815 || i
.types
[op
].bitfield
.disp32s
3816 || i
.types
[op
].bitfield
.disp16
)
3817 && fits_in_signed_byte (op_disp
))
3818 i
.types
[op
].bitfield
.disp8
= 1;
3820 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3821 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3823 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3824 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3825 i
.types
[op
].bitfield
.disp8
= 0;
3826 i
.types
[op
].bitfield
.disp16
= 0;
3827 i
.types
[op
].bitfield
.disp32
= 0;
3828 i
.types
[op
].bitfield
.disp32s
= 0;
3829 i
.types
[op
].bitfield
.disp64
= 0;
3832 /* We only support 64bit displacement on constants. */
3833 i
.types
[op
].bitfield
.disp64
= 0;
3837 /* Check if operands are valid for the instruction. Update VEX
3841 VEX_check_operands (const insn_template
*t
)
3843 if (!t
->opcode_modifier
.vex
)
3846 /* Only check VEX_Imm4, which must be the first operand. */
3847 if (t
->operand_types
[0].bitfield
.vec_imm4
)
3849 if (i
.op
[0].imms
->X_op
!= O_constant
3850 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
3856 /* Turn off Imm8 so that update_imm won't complain. */
3857 i
.types
[0] = vec_imm4
;
3863 static const insn_template
*
3864 match_template (void)
3866 /* Points to template once we've found it. */
3867 const insn_template
*t
;
3868 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3869 i386_operand_type overlap4
;
3870 unsigned int found_reverse_match
;
3871 i386_opcode_modifier suffix_check
;
3872 i386_operand_type operand_types
[MAX_OPERANDS
];
3873 int addr_prefix_disp
;
3875 unsigned int found_cpu_match
;
3876 unsigned int check_register
;
3878 #if MAX_OPERANDS != 5
3879 # error "MAX_OPERANDS must be 5."
3882 found_reverse_match
= 0;
3883 addr_prefix_disp
= -1;
3885 memset (&suffix_check
, 0, sizeof (suffix_check
));
3886 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3887 suffix_check
.no_bsuf
= 1;
3888 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3889 suffix_check
.no_wsuf
= 1;
3890 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3891 suffix_check
.no_ssuf
= 1;
3892 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3893 suffix_check
.no_lsuf
= 1;
3894 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3895 suffix_check
.no_qsuf
= 1;
3896 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3897 suffix_check
.no_ldsuf
= 1;
3899 /* Must have right number of operands. */
3900 i
.error
= number_of_operands_mismatch
;
3902 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3904 addr_prefix_disp
= -1;
3906 if (i
.operands
!= t
->operands
)
3909 /* Check processor support. */
3910 i
.error
= unsupported
;
3911 found_cpu_match
= (cpu_flags_match (t
)
3912 == CPU_FLAGS_PERFECT_MATCH
);
3913 if (!found_cpu_match
)
3916 /* Check old gcc support. */
3917 i
.error
= old_gcc_only
;
3918 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3921 /* Check AT&T mnemonic. */
3922 i
.error
= unsupported_with_intel_mnemonic
;
3923 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3926 /* Check AT&T/Intel syntax. */
3927 i
.error
= unsupported_syntax
;
3928 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3929 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3932 /* Check the suffix, except for some instructions in intel mode. */
3933 i
.error
= invalid_instruction_suffix
;
3934 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3935 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3936 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3937 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3938 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3939 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3940 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3943 if (!operand_size_match (t
))
3946 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3947 operand_types
[j
] = t
->operand_types
[j
];
3949 /* In general, don't allow 64-bit operands in 32-bit mode. */
3950 if (i
.suffix
== QWORD_MNEM_SUFFIX
3951 && flag_code
!= CODE_64BIT
3953 ? (!t
->opcode_modifier
.ignoresize
3954 && !intel_float_operand (t
->name
))
3955 : intel_float_operand (t
->name
) != 2)
3956 && ((!operand_types
[0].bitfield
.regmmx
3957 && !operand_types
[0].bitfield
.regxmm
3958 && !operand_types
[0].bitfield
.regymm
)
3959 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3960 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3961 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3962 && (t
->base_opcode
!= 0x0fc7
3963 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3966 /* In general, don't allow 32-bit operands on pre-386. */
3967 else if (i
.suffix
== LONG_MNEM_SUFFIX
3968 && !cpu_arch_flags
.bitfield
.cpui386
3970 ? (!t
->opcode_modifier
.ignoresize
3971 && !intel_float_operand (t
->name
))
3972 : intel_float_operand (t
->name
) != 2)
3973 && ((!operand_types
[0].bitfield
.regmmx
3974 && !operand_types
[0].bitfield
.regxmm
)
3975 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3976 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3979 /* Do not verify operands when there are none. */
3983 /* We've found a match; break out of loop. */
3987 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3988 into Disp32/Disp16/Disp32 operand. */
3989 if (i
.prefix
[ADDR_PREFIX
] != 0)
3991 /* There should be only one Disp operand. */
3995 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3997 if (operand_types
[j
].bitfield
.disp16
)
3999 addr_prefix_disp
= j
;
4000 operand_types
[j
].bitfield
.disp32
= 1;
4001 operand_types
[j
].bitfield
.disp16
= 0;
4007 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4009 if (operand_types
[j
].bitfield
.disp32
)
4011 addr_prefix_disp
= j
;
4012 operand_types
[j
].bitfield
.disp32
= 0;
4013 operand_types
[j
].bitfield
.disp16
= 1;
4019 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4021 if (operand_types
[j
].bitfield
.disp64
)
4023 addr_prefix_disp
= j
;
4024 operand_types
[j
].bitfield
.disp64
= 0;
4025 operand_types
[j
].bitfield
.disp32
= 1;
4033 /* We check register size if needed. */
4034 check_register
= t
->opcode_modifier
.checkregsize
;
4035 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4036 switch (t
->operands
)
4039 if (!operand_type_match (overlap0
, i
.types
[0]))
4043 /* xchg %eax, %eax is a special case. It is an aliase for nop
4044 only in 32bit mode and we can use opcode 0x90. In 64bit
4045 mode, we can't use 0x90 for xchg %eax, %eax since it should
4046 zero-extend %eax to %rax. */
4047 if (flag_code
== CODE_64BIT
4048 && t
->base_opcode
== 0x90
4049 && operand_type_equal (&i
.types
[0], &acc32
)
4050 && operand_type_equal (&i
.types
[1], &acc32
))
4054 /* If we swap operand in encoding, we either match
4055 the next one or reverse direction of operands. */
4056 if (t
->opcode_modifier
.s
)
4058 else if (t
->opcode_modifier
.d
)
4063 /* If we swap operand in encoding, we match the next one. */
4064 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4068 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4069 if (!operand_type_match (overlap0
, i
.types
[0])
4070 || !operand_type_match (overlap1
, i
.types
[1])
4072 && !operand_type_register_match (overlap0
, i
.types
[0],
4074 overlap1
, i
.types
[1],
4077 /* Check if other direction is valid ... */
4078 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4082 /* Try reversing direction of operands. */
4083 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4084 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4085 if (!operand_type_match (overlap0
, i
.types
[0])
4086 || !operand_type_match (overlap1
, i
.types
[1])
4088 && !operand_type_register_match (overlap0
,
4095 /* Does not match either direction. */
4098 /* found_reverse_match holds which of D or FloatDR
4100 if (t
->opcode_modifier
.d
)
4101 found_reverse_match
= Opcode_D
;
4102 else if (t
->opcode_modifier
.floatd
)
4103 found_reverse_match
= Opcode_FloatD
;
4105 found_reverse_match
= 0;
4106 if (t
->opcode_modifier
.floatr
)
4107 found_reverse_match
|= Opcode_FloatR
;
4111 /* Found a forward 2 operand match here. */
4112 switch (t
->operands
)
4115 overlap4
= operand_type_and (i
.types
[4],
4118 overlap3
= operand_type_and (i
.types
[3],
4121 overlap2
= operand_type_and (i
.types
[2],
4126 switch (t
->operands
)
4129 if (!operand_type_match (overlap4
, i
.types
[4])
4130 || !operand_type_register_match (overlap3
,
4138 if (!operand_type_match (overlap3
, i
.types
[3])
4140 && !operand_type_register_match (overlap2
,
4148 /* Here we make use of the fact that there are no
4149 reverse match 3 operand instructions, and all 3
4150 operand instructions only need to be checked for
4151 register consistency between operands 2 and 3. */
4152 if (!operand_type_match (overlap2
, i
.types
[2])
4154 && !operand_type_register_match (overlap1
,
4164 /* Found either forward/reverse 2, 3 or 4 operand match here:
4165 slip through to break. */
4167 if (!found_cpu_match
)
4169 found_reverse_match
= 0;
4173 /* Check if VEX operands are valid. */
4174 if (VEX_check_operands (t
))
4177 /* We've found a match; break out of loop. */
4181 if (t
== current_templates
->end
)
4183 /* We found no match. */
4184 const char *err_msg
;
4189 case operand_size_mismatch
:
4190 err_msg
= _("operand size mismatch");
4192 case operand_type_mismatch
:
4193 err_msg
= _("operand type mismatch");
4195 case register_type_mismatch
:
4196 err_msg
= _("register type mismatch");
4198 case number_of_operands_mismatch
:
4199 err_msg
= _("number of operands mismatch");
4201 case invalid_instruction_suffix
:
4202 err_msg
= _("invalid instruction suffix");
4205 err_msg
= _("Imm4 isn't the first operand");
4208 err_msg
= _("only supported with old gcc");
4210 case unsupported_with_intel_mnemonic
:
4211 err_msg
= _("unsupported with Intel mnemonic");
4213 case unsupported_syntax
:
4214 err_msg
= _("unsupported syntax");
4217 err_msg
= _("unsupported");
4220 as_bad (_("%s for `%s'"), err_msg
,
4221 current_templates
->start
->name
);
4225 if (!quiet_warnings
)
4228 && (i
.types
[0].bitfield
.jumpabsolute
4229 != operand_types
[0].bitfield
.jumpabsolute
))
4231 as_warn (_("indirect %s without `*'"), t
->name
);
4234 if (t
->opcode_modifier
.isprefix
4235 && t
->opcode_modifier
.ignoresize
)
4237 /* Warn them that a data or address size prefix doesn't
4238 affect assembly of the next line of code. */
4239 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4243 /* Copy the template we found. */
4246 if (addr_prefix_disp
!= -1)
4247 i
.tm
.operand_types
[addr_prefix_disp
]
4248 = operand_types
[addr_prefix_disp
];
4250 if (found_reverse_match
)
4252 /* If we found a reverse match we must alter the opcode
4253 direction bit. found_reverse_match holds bits to change
4254 (different for int & float insns). */
4256 i
.tm
.base_opcode
^= found_reverse_match
;
4258 i
.tm
.operand_types
[0] = operand_types
[1];
4259 i
.tm
.operand_types
[1] = operand_types
[0];
4268 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4269 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4271 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4273 as_bad (_("`%s' operand %d must use `%ses' segment"),
4279 /* There's only ever one segment override allowed per instruction.
4280 This instruction possibly has a legal segment override on the
4281 second operand, so copy the segment to where non-string
4282 instructions store it, allowing common code. */
4283 i
.seg
[0] = i
.seg
[1];
4285 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4287 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4289 as_bad (_("`%s' operand %d must use `%ses' segment"),
4300 process_suffix (void)
4302 /* If matched instruction specifies an explicit instruction mnemonic
4304 if (i
.tm
.opcode_modifier
.size16
)
4305 i
.suffix
= WORD_MNEM_SUFFIX
;
4306 else if (i
.tm
.opcode_modifier
.size32
)
4307 i
.suffix
= LONG_MNEM_SUFFIX
;
4308 else if (i
.tm
.opcode_modifier
.size64
)
4309 i
.suffix
= QWORD_MNEM_SUFFIX
;
4310 else if (i
.reg_operands
)
4312 /* If there's no instruction mnemonic suffix we try to invent one
4313 based on register operands. */
4316 /* We take i.suffix from the last register operand specified,
4317 Destination register type is more significant than source
4318 register type. crc32 in SSE4.2 prefers source register
4320 if (i
.tm
.base_opcode
== 0xf20f38f1)
4322 if (i
.types
[0].bitfield
.reg16
)
4323 i
.suffix
= WORD_MNEM_SUFFIX
;
4324 else if (i
.types
[0].bitfield
.reg32
)
4325 i
.suffix
= LONG_MNEM_SUFFIX
;
4326 else if (i
.types
[0].bitfield
.reg64
)
4327 i
.suffix
= QWORD_MNEM_SUFFIX
;
4329 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4331 if (i
.types
[0].bitfield
.reg8
)
4332 i
.suffix
= BYTE_MNEM_SUFFIX
;
4339 if (i
.tm
.base_opcode
== 0xf20f38f1
4340 || i
.tm
.base_opcode
== 0xf20f38f0)
4342 /* We have to know the operand size for crc32. */
4343 as_bad (_("ambiguous memory operand size for `%s`"),
4348 for (op
= i
.operands
; --op
>= 0;)
4349 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4351 if (i
.types
[op
].bitfield
.reg8
)
4353 i
.suffix
= BYTE_MNEM_SUFFIX
;
4356 else if (i
.types
[op
].bitfield
.reg16
)
4358 i
.suffix
= WORD_MNEM_SUFFIX
;
4361 else if (i
.types
[op
].bitfield
.reg32
)
4363 i
.suffix
= LONG_MNEM_SUFFIX
;
4366 else if (i
.types
[op
].bitfield
.reg64
)
4368 i
.suffix
= QWORD_MNEM_SUFFIX
;
4374 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4377 && i
.tm
.opcode_modifier
.ignoresize
4378 && i
.tm
.opcode_modifier
.no_bsuf
)
4380 else if (!check_byte_reg ())
4383 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4386 && i
.tm
.opcode_modifier
.ignoresize
4387 && i
.tm
.opcode_modifier
.no_lsuf
)
4389 else if (!check_long_reg ())
4392 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4395 && i
.tm
.opcode_modifier
.ignoresize
4396 && i
.tm
.opcode_modifier
.no_qsuf
)
4398 else if (!check_qword_reg ())
4401 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4404 && i
.tm
.opcode_modifier
.ignoresize
4405 && i
.tm
.opcode_modifier
.no_wsuf
)
4407 else if (!check_word_reg ())
4410 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4411 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4413 /* Skip if the instruction has x/y suffix. match_template
4414 should check if it is a valid suffix. */
4416 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4417 /* Do nothing if the instruction is going to ignore the prefix. */
4422 else if (i
.tm
.opcode_modifier
.defaultsize
4424 /* exclude fldenv/frstor/fsave/fstenv */
4425 && i
.tm
.opcode_modifier
.no_ssuf
)
4427 i
.suffix
= stackop_size
;
4429 else if (intel_syntax
4431 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4432 || i
.tm
.opcode_modifier
.jumpbyte
4433 || i
.tm
.opcode_modifier
.jumpintersegment
4434 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4435 && i
.tm
.extension_opcode
<= 3)))
4440 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4442 i
.suffix
= QWORD_MNEM_SUFFIX
;
4446 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4447 i
.suffix
= LONG_MNEM_SUFFIX
;
4450 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4451 i
.suffix
= WORD_MNEM_SUFFIX
;
4460 if (i
.tm
.opcode_modifier
.w
)
4462 as_bad (_("no instruction mnemonic suffix given and "
4463 "no register operands; can't size instruction"));
4469 unsigned int suffixes
;
4471 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4472 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4474 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4476 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4478 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4480 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4483 /* There are more than suffix matches. */
4484 if (i
.tm
.opcode_modifier
.w
4485 || ((suffixes
& (suffixes
- 1))
4486 && !i
.tm
.opcode_modifier
.defaultsize
4487 && !i
.tm
.opcode_modifier
.ignoresize
))
4489 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4495 /* Change the opcode based on the operand size given by i.suffix;
4496 We don't need to change things for byte insns. */
4499 && i
.suffix
!= BYTE_MNEM_SUFFIX
4500 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4501 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4503 /* It's not a byte, select word/dword operation. */
4504 if (i
.tm
.opcode_modifier
.w
)
4506 if (i
.tm
.opcode_modifier
.shortform
)
4507 i
.tm
.base_opcode
|= 8;
4509 i
.tm
.base_opcode
|= 1;
4512 /* Now select between word & dword operations via the operand
4513 size prefix, except for instructions that will ignore this
4515 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4517 /* The address size override prefix changes the size of the
4519 if ((flag_code
== CODE_32BIT
4520 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4521 || (flag_code
!= CODE_32BIT
4522 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4523 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4526 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4527 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4528 && !i
.tm
.opcode_modifier
.ignoresize
4529 && !i
.tm
.opcode_modifier
.floatmf
4530 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4531 || (flag_code
== CODE_64BIT
4532 && i
.tm
.opcode_modifier
.jumpbyte
)))
4534 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4536 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4537 prefix
= ADDR_PREFIX_OPCODE
;
4539 if (!add_prefix (prefix
))
4543 /* Set mode64 for an operand. */
4544 if (i
.suffix
== QWORD_MNEM_SUFFIX
4545 && flag_code
== CODE_64BIT
4546 && !i
.tm
.opcode_modifier
.norex64
)
4548 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4549 need rex64. cmpxchg8b is also a special case. */
4550 if (! (i
.operands
== 2
4551 && i
.tm
.base_opcode
== 0x90
4552 && i
.tm
.extension_opcode
== None
4553 && operand_type_equal (&i
.types
[0], &acc64
)
4554 && operand_type_equal (&i
.types
[1], &acc64
))
4555 && ! (i
.operands
== 1
4556 && i
.tm
.base_opcode
== 0xfc7
4557 && i
.tm
.extension_opcode
== 1
4558 && !operand_type_check (i
.types
[0], reg
)
4559 && operand_type_check (i
.types
[0], anymem
)))
4563 /* Size floating point instruction. */
4564 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4565 if (i
.tm
.opcode_modifier
.floatmf
)
4566 i
.tm
.base_opcode
^= 4;
4573 check_byte_reg (void)
4577 for (op
= i
.operands
; --op
>= 0;)
4579 /* If this is an eight bit register, it's OK. If it's the 16 or
4580 32 bit version of an eight bit register, we will just use the
4581 low portion, and that's OK too. */
4582 if (i
.types
[op
].bitfield
.reg8
)
4585 /* crc32 doesn't generate this warning. */
4586 if (i
.tm
.base_opcode
== 0xf20f38f0)
4589 if ((i
.types
[op
].bitfield
.reg16
4590 || i
.types
[op
].bitfield
.reg32
4591 || i
.types
[op
].bitfield
.reg64
)
4592 && i
.op
[op
].regs
->reg_num
< 4)
4594 /* Prohibit these changes in the 64bit mode, since the
4595 lowering is more complicated. */
4596 if (flag_code
== CODE_64BIT
4597 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4599 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4600 register_prefix
, i
.op
[op
].regs
->reg_name
,
4604 #if REGISTER_WARNINGS
4606 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4607 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4609 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4610 ? REGNAM_AL
- REGNAM_AX
4611 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4613 i
.op
[op
].regs
->reg_name
,
4618 /* Any other register is bad. */
4619 if (i
.types
[op
].bitfield
.reg16
4620 || i
.types
[op
].bitfield
.reg32
4621 || i
.types
[op
].bitfield
.reg64
4622 || i
.types
[op
].bitfield
.regmmx
4623 || i
.types
[op
].bitfield
.regxmm
4624 || i
.types
[op
].bitfield
.regymm
4625 || i
.types
[op
].bitfield
.sreg2
4626 || i
.types
[op
].bitfield
.sreg3
4627 || i
.types
[op
].bitfield
.control
4628 || i
.types
[op
].bitfield
.debug
4629 || i
.types
[op
].bitfield
.test
4630 || i
.types
[op
].bitfield
.floatreg
4631 || i
.types
[op
].bitfield
.floatacc
)
4633 as_bad (_("`%s%s' not allowed with `%s%c'"),
4635 i
.op
[op
].regs
->reg_name
,
4645 check_long_reg (void)
4649 for (op
= i
.operands
; --op
>= 0;)
4650 /* Reject eight bit registers, except where the template requires
4651 them. (eg. movzb) */
4652 if (i
.types
[op
].bitfield
.reg8
4653 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4654 || i
.tm
.operand_types
[op
].bitfield
.reg32
4655 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4657 as_bad (_("`%s%s' not allowed with `%s%c'"),
4659 i
.op
[op
].regs
->reg_name
,
4664 /* Warn if the e prefix on a general reg is missing. */
4665 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4666 && i
.types
[op
].bitfield
.reg16
4667 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4668 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4670 /* Prohibit these changes in the 64bit mode, since the
4671 lowering is more complicated. */
4672 if (flag_code
== CODE_64BIT
)
4674 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4675 register_prefix
, i
.op
[op
].regs
->reg_name
,
4679 #if REGISTER_WARNINGS
4681 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4683 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4685 i
.op
[op
].regs
->reg_name
,
4689 /* Warn if the r prefix on a general reg is missing. */
4690 else if (i
.types
[op
].bitfield
.reg64
4691 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4692 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4695 && i
.tm
.opcode_modifier
.toqword
4696 && !i
.types
[0].bitfield
.regxmm
)
4698 /* Convert to QWORD. We want REX byte. */
4699 i
.suffix
= QWORD_MNEM_SUFFIX
;
4703 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4704 register_prefix
, i
.op
[op
].regs
->reg_name
,
4713 check_qword_reg (void)
4717 for (op
= i
.operands
; --op
>= 0; )
4718 /* Reject eight bit registers, except where the template requires
4719 them. (eg. movzb) */
4720 if (i
.types
[op
].bitfield
.reg8
4721 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4722 || i
.tm
.operand_types
[op
].bitfield
.reg32
4723 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4725 as_bad (_("`%s%s' not allowed with `%s%c'"),
4727 i
.op
[op
].regs
->reg_name
,
4732 /* Warn if the e prefix on a general reg is missing. */
4733 else if ((i
.types
[op
].bitfield
.reg16
4734 || i
.types
[op
].bitfield
.reg32
)
4735 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4736 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4738 /* Prohibit these changes in the 64bit mode, since the
4739 lowering is more complicated. */
4741 && i
.tm
.opcode_modifier
.todword
4742 && !i
.types
[0].bitfield
.regxmm
)
4744 /* Convert to DWORD. We don't want REX byte. */
4745 i
.suffix
= LONG_MNEM_SUFFIX
;
4749 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4750 register_prefix
, i
.op
[op
].regs
->reg_name
,
4759 check_word_reg (void)
4762 for (op
= i
.operands
; --op
>= 0;)
4763 /* Reject eight bit registers, except where the template requires
4764 them. (eg. movzb) */
4765 if (i
.types
[op
].bitfield
.reg8
4766 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4767 || i
.tm
.operand_types
[op
].bitfield
.reg32
4768 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4770 as_bad (_("`%s%s' not allowed with `%s%c'"),
4772 i
.op
[op
].regs
->reg_name
,
4777 /* Warn if the e prefix on a general reg is present. */
4778 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4779 && i
.types
[op
].bitfield
.reg32
4780 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4781 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4783 /* Prohibit these changes in the 64bit mode, since the
4784 lowering is more complicated. */
4785 if (flag_code
== CODE_64BIT
)
4787 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4788 register_prefix
, i
.op
[op
].regs
->reg_name
,
4793 #if REGISTER_WARNINGS
4794 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4796 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4798 i
.op
[op
].regs
->reg_name
,
4806 update_imm (unsigned int j
)
4808 i386_operand_type overlap
= i
.types
[j
];
4809 if ((overlap
.bitfield
.imm8
4810 || overlap
.bitfield
.imm8s
4811 || overlap
.bitfield
.imm16
4812 || overlap
.bitfield
.imm32
4813 || overlap
.bitfield
.imm32s
4814 || overlap
.bitfield
.imm64
)
4815 && !operand_type_equal (&overlap
, &imm8
)
4816 && !operand_type_equal (&overlap
, &imm8s
)
4817 && !operand_type_equal (&overlap
, &imm16
)
4818 && !operand_type_equal (&overlap
, &imm32
)
4819 && !operand_type_equal (&overlap
, &imm32s
)
4820 && !operand_type_equal (&overlap
, &imm64
))
4824 i386_operand_type temp
;
4826 operand_type_set (&temp
, 0);
4827 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4829 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4830 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4832 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4833 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4834 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4836 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4837 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4840 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4843 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4844 || operand_type_equal (&overlap
, &imm16_32
)
4845 || operand_type_equal (&overlap
, &imm16_32s
))
4847 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4852 if (!operand_type_equal (&overlap
, &imm8
)
4853 && !operand_type_equal (&overlap
, &imm8s
)
4854 && !operand_type_equal (&overlap
, &imm16
)
4855 && !operand_type_equal (&overlap
, &imm32
)
4856 && !operand_type_equal (&overlap
, &imm32s
)
4857 && !operand_type_equal (&overlap
, &imm64
))
4859 as_bad (_("no instruction mnemonic suffix given; "
4860 "can't determine immediate size"));
4864 i
.types
[j
] = overlap
;
4874 /* Update the first 2 immediate operands. */
4875 n
= i
.operands
> 2 ? 2 : i
.operands
;
4878 for (j
= 0; j
< n
; j
++)
4879 if (update_imm (j
) == 0)
4882 /* The 3rd operand can't be immediate operand. */
4883 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4890 bad_implicit_operand (int xmm
)
4892 const char *ireg
= xmm
? "xmm0" : "ymm0";
4895 as_bad (_("the last operand of `%s' must be `%s%s'"),
4896 i
.tm
.name
, register_prefix
, ireg
);
4898 as_bad (_("the first operand of `%s' must be `%s%s'"),
4899 i
.tm
.name
, register_prefix
, ireg
);
4904 process_operands (void)
4906 /* Default segment register this instruction will use for memory
4907 accesses. 0 means unknown. This is only for optimizing out
4908 unnecessary segment overrides. */
4909 const seg_entry
*default_seg
= 0;
4911 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
4913 unsigned int dupl
= i
.operands
;
4914 unsigned int dest
= dupl
- 1;
4917 /* The destination must be an xmm register. */
4918 gas_assert (i
.reg_operands
4919 && MAX_OPERANDS
> dupl
4920 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4922 if (i
.tm
.opcode_modifier
.firstxmm0
)
4924 /* The first operand is implicit and must be xmm0. */
4925 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4926 if (i
.op
[0].regs
->reg_num
!= 0)
4927 return bad_implicit_operand (1);
4929 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4931 /* Keep xmm0 for instructions with VEX prefix and 3
4937 /* We remove the first xmm0 and keep the number of
4938 operands unchanged, which in fact duplicates the
4940 for (j
= 1; j
< i
.operands
; j
++)
4942 i
.op
[j
- 1] = i
.op
[j
];
4943 i
.types
[j
- 1] = i
.types
[j
];
4944 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4948 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4950 gas_assert ((MAX_OPERANDS
- 1) > dupl
4951 && (i
.tm
.opcode_modifier
.vexsources
4954 /* Add the implicit xmm0 for instructions with VEX prefix
4956 for (j
= i
.operands
; j
> 0; j
--)
4958 i
.op
[j
] = i
.op
[j
- 1];
4959 i
.types
[j
] = i
.types
[j
- 1];
4960 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4963 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4964 i
.types
[0] = regxmm
;
4965 i
.tm
.operand_types
[0] = regxmm
;
4968 i
.reg_operands
+= 2;
4973 i
.op
[dupl
] = i
.op
[dest
];
4974 i
.types
[dupl
] = i
.types
[dest
];
4975 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4984 i
.op
[dupl
] = i
.op
[dest
];
4985 i
.types
[dupl
] = i
.types
[dest
];
4986 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4989 if (i
.tm
.opcode_modifier
.immext
)
4992 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4996 /* The first operand is implicit and must be xmm0/ymm0. */
4997 gas_assert (i
.reg_operands
4998 && (operand_type_equal (&i
.types
[0], ®xmm
)
4999 || operand_type_equal (&i
.types
[0], ®ymm
)));
5000 if (i
.op
[0].regs
->reg_num
!= 0)
5001 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5003 for (j
= 1; j
< i
.operands
; j
++)
5005 i
.op
[j
- 1] = i
.op
[j
];
5006 i
.types
[j
- 1] = i
.types
[j
];
5008 /* We need to adjust fields in i.tm since they are used by
5009 build_modrm_byte. */
5010 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5017 else if (i
.tm
.opcode_modifier
.regkludge
)
5019 /* The imul $imm, %reg instruction is converted into
5020 imul $imm, %reg, %reg, and the clr %reg instruction
5021 is converted into xor %reg, %reg. */
5023 unsigned int first_reg_op
;
5025 if (operand_type_check (i
.types
[0], reg
))
5029 /* Pretend we saw the extra register operand. */
5030 gas_assert (i
.reg_operands
== 1
5031 && i
.op
[first_reg_op
+ 1].regs
== 0);
5032 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5033 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5038 if (i
.tm
.opcode_modifier
.shortform
)
5040 if (i
.types
[0].bitfield
.sreg2
5041 || i
.types
[0].bitfield
.sreg3
)
5043 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5044 && i
.op
[0].regs
->reg_num
== 1)
5046 as_bad (_("you can't `pop %scs'"), register_prefix
);
5049 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5050 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5055 /* The register or float register operand is in operand
5059 if (i
.types
[0].bitfield
.floatreg
5060 || operand_type_check (i
.types
[0], reg
))
5064 /* Register goes in low 3 bits of opcode. */
5065 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5066 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5068 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5070 /* Warn about some common errors, but press on regardless.
5071 The first case can be generated by gcc (<= 2.8.1). */
5072 if (i
.operands
== 2)
5074 /* Reversed arguments on faddp, fsubp, etc. */
5075 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5076 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5077 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5081 /* Extraneous `l' suffix on fp insn. */
5082 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5083 register_prefix
, i
.op
[0].regs
->reg_name
);
5088 else if (i
.tm
.opcode_modifier
.modrm
)
5090 /* The opcode is completed (modulo i.tm.extension_opcode which
5091 must be put into the modrm byte). Now, we make the modrm and
5092 index base bytes based on all the info we've collected. */
5094 default_seg
= build_modrm_byte ();
5096 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5100 else if (i
.tm
.opcode_modifier
.isstring
)
5102 /* For the string instructions that allow a segment override
5103 on one of their operands, the default segment is ds. */
5107 if (i
.tm
.base_opcode
== 0x8d /* lea */
5110 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5112 /* If a segment was explicitly specified, and the specified segment
5113 is not the default, use an opcode prefix to select it. If we
5114 never figured out what the default segment is, then default_seg
5115 will be zero at this point, and the specified segment prefix will
5117 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5119 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5125 static const seg_entry
*
5126 build_modrm_byte (void)
5128 const seg_entry
*default_seg
= 0;
5129 unsigned int source
, dest
;
5132 /* The first operand of instructions with VEX prefix and 3 sources
5133 must be VEX_Imm4. */
5134 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5137 unsigned int nds
, reg_slot
;
5140 if (i
.tm
.opcode_modifier
.veximmext
5141 && i
.tm
.opcode_modifier
.immext
)
5143 dest
= i
.operands
- 2;
5144 gas_assert (dest
== 3);
5147 dest
= i
.operands
- 1;
5150 /* There are 2 kinds of instructions:
5151 1. 5 operands: 4 register operands or 3 register operands
5152 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5153 VexW0 or VexW1. The destination must be either XMM or YMM
5155 2. 4 operands: 4 register operands or 3 register operands
5156 plus 1 memory operand, VexXDS, and VexImmExt */
5157 gas_assert ((i
.reg_operands
== 4
5158 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5159 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5160 && (i
.tm
.opcode_modifier
.veximmext
5161 || (i
.imm_operands
== 1
5162 && i
.types
[0].bitfield
.vec_imm4
5163 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5164 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5165 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5166 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)))));
5168 if (i
.imm_operands
== 0)
5170 /* When there is no immediate operand, generate an 8bit
5171 immediate operand to encode the first operand. */
5172 exp
= &im_expressions
[i
.imm_operands
++];
5173 i
.op
[i
.operands
].imms
= exp
;
5174 i
.types
[i
.operands
] = imm8
;
5176 /* If VexW1 is set, the first operand is the source and
5177 the second operand is encoded in the immediate operand. */
5178 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5189 /* FMA swaps REG and NDS. */
5190 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5198 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5200 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5202 exp
->X_op
= O_constant
;
5204 = ((i
.op
[reg_slot
].regs
->reg_num
5205 + ((i
.op
[reg_slot
].regs
->reg_flags
& RegRex
) ? 8 : 0))
5210 unsigned int imm_slot
;
5212 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5214 /* If VexW0 is set, the third operand is the source and
5215 the second operand is encoded in the immediate
5222 /* VexW1 is set, the second operand is the source and
5223 the third operand is encoded in the immediate
5229 if (i
.tm
.opcode_modifier
.immext
)
5231 /* When ImmExt is set, the immdiate byte is the last
5233 imm_slot
= i
.operands
- 1;
5241 /* Turn on Imm8 so that output_imm will generate it. */
5242 i
.types
[imm_slot
].bitfield
.imm8
= 1;
5245 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5247 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5249 i
.op
[imm_slot
].imms
->X_add_number
5250 |= ((i
.op
[reg_slot
].regs
->reg_num
5251 + ((i
.op
[reg_slot
].regs
->reg_flags
& RegRex
) ? 8 : 0))
5255 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
5256 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5258 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5263 /* i.reg_operands MUST be the number of real register operands;
5264 implicit registers do not count. If there are 3 register
5265 operands, it must be a instruction with VexNDS. For a
5266 instruction with VexNDD, the destination register is encoded
5267 in VEX prefix. If there are 4 register operands, it must be
5268 a instruction with VEX prefix and 3 sources. */
5269 if (i
.mem_operands
== 0
5270 && ((i
.reg_operands
== 2
5271 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
5272 || (i
.reg_operands
== 3
5273 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5274 || (i
.reg_operands
== 4 && vex_3_sources
)))
5282 /* When there are 3 operands, one of them may be immediate,
5283 which may be the first or the last operand. Otherwise,
5284 the first operand must be shift count register (cl) or it
5285 is an instruction with VexNDS. */
5286 gas_assert (i
.imm_operands
== 1
5287 || (i
.imm_operands
== 0
5288 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5289 || i
.types
[0].bitfield
.shiftcount
)));
5290 if (operand_type_check (i
.types
[0], imm
)
5291 || i
.types
[0].bitfield
.shiftcount
)
5297 /* When there are 4 operands, the first two must be 8bit
5298 immediate operands. The source operand will be the 3rd
5301 For instructions with VexNDS, if the first operand
5302 an imm8, the source operand is the 2nd one. If the last
5303 operand is imm8, the source operand is the first one. */
5304 gas_assert ((i
.imm_operands
== 2
5305 && i
.types
[0].bitfield
.imm8
5306 && i
.types
[1].bitfield
.imm8
)
5307 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5308 && i
.imm_operands
== 1
5309 && (i
.types
[0].bitfield
.imm8
5310 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5311 if (i
.imm_operands
== 2)
5315 if (i
.types
[0].bitfield
.imm8
)
5331 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5333 /* For instructions with VexNDS, the register-only
5334 source operand must be 32/64bit integer, XMM or
5335 YMM register. It is encoded in VEX prefix. We
5336 need to clear RegMem bit before calling
5337 operand_type_equal. */
5339 i386_operand_type op
;
5342 /* Check register-only source operand when two source
5343 operands are swapped. */
5344 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
5345 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
5353 op
= i
.tm
.operand_types
[vvvv
];
5354 op
.bitfield
.regmem
= 0;
5355 if ((dest
+ 1) >= i
.operands
5356 || (op
.bitfield
.reg32
!= 1
5357 && !op
.bitfield
.reg64
!= 1
5358 && !operand_type_equal (&op
, ®xmm
)
5359 && !operand_type_equal (&op
, ®ymm
)))
5361 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
5367 /* One of the register operands will be encoded in the i.tm.reg
5368 field, the other in the combined i.tm.mode and i.tm.regmem
5369 fields. If no form of this instruction supports a memory
5370 destination operand, then we assume the source operand may
5371 sometimes be a memory operand and so we need to store the
5372 destination in the i.rm.reg field. */
5373 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5374 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5376 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5377 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5378 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5380 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5385 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5386 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5387 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5389 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5392 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5394 if (!i
.types
[0].bitfield
.control
5395 && !i
.types
[1].bitfield
.control
)
5397 i
.rex
&= ~(REX_R
| REX_B
);
5398 add_prefix (LOCK_PREFIX_OPCODE
);
5402 { /* If it's not 2 reg operands... */
5407 unsigned int fake_zero_displacement
= 0;
5410 for (op
= 0; op
< i
.operands
; op
++)
5411 if (operand_type_check (i
.types
[op
], anymem
))
5413 gas_assert (op
< i
.operands
);
5417 if (i
.base_reg
== 0)
5420 if (!i
.disp_operands
)
5421 fake_zero_displacement
= 1;
5422 if (i
.index_reg
== 0)
5424 /* Operand is just <disp> */
5425 if (flag_code
== CODE_64BIT
)
5427 /* 64bit mode overwrites the 32bit absolute
5428 addressing by RIP relative addressing and
5429 absolute addressing is encoded by one of the
5430 redundant SIB forms. */
5431 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5432 i
.sib
.base
= NO_BASE_REGISTER
;
5433 i
.sib
.index
= NO_INDEX_REGISTER
;
5434 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5435 ? disp32s
: disp32
);
5437 else if ((flag_code
== CODE_16BIT
)
5438 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5440 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5441 i
.types
[op
] = disp16
;
5445 i
.rm
.regmem
= NO_BASE_REGISTER
;
5446 i
.types
[op
] = disp32
;
5449 else /* !i.base_reg && i.index_reg */
5451 if (i
.index_reg
->reg_num
== RegEiz
5452 || i
.index_reg
->reg_num
== RegRiz
)
5453 i
.sib
.index
= NO_INDEX_REGISTER
;
5455 i
.sib
.index
= i
.index_reg
->reg_num
;
5456 i
.sib
.base
= NO_BASE_REGISTER
;
5457 i
.sib
.scale
= i
.log2_scale_factor
;
5458 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5459 i
.types
[op
].bitfield
.disp8
= 0;
5460 i
.types
[op
].bitfield
.disp16
= 0;
5461 i
.types
[op
].bitfield
.disp64
= 0;
5462 if (flag_code
!= CODE_64BIT
)
5464 /* Must be 32 bit */
5465 i
.types
[op
].bitfield
.disp32
= 1;
5466 i
.types
[op
].bitfield
.disp32s
= 0;
5470 i
.types
[op
].bitfield
.disp32
= 0;
5471 i
.types
[op
].bitfield
.disp32s
= 1;
5473 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5477 /* RIP addressing for 64bit mode. */
5478 else if (i
.base_reg
->reg_num
== RegRip
||
5479 i
.base_reg
->reg_num
== RegEip
)
5481 i
.rm
.regmem
= NO_BASE_REGISTER
;
5482 i
.types
[op
].bitfield
.disp8
= 0;
5483 i
.types
[op
].bitfield
.disp16
= 0;
5484 i
.types
[op
].bitfield
.disp32
= 0;
5485 i
.types
[op
].bitfield
.disp32s
= 1;
5486 i
.types
[op
].bitfield
.disp64
= 0;
5487 i
.flags
[op
] |= Operand_PCrel
;
5488 if (! i
.disp_operands
)
5489 fake_zero_displacement
= 1;
5491 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5493 switch (i
.base_reg
->reg_num
)
5496 if (i
.index_reg
== 0)
5498 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5499 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5503 if (i
.index_reg
== 0)
5506 if (operand_type_check (i
.types
[op
], disp
) == 0)
5508 /* fake (%bp) into 0(%bp) */
5509 i
.types
[op
].bitfield
.disp8
= 1;
5510 fake_zero_displacement
= 1;
5513 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5514 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5516 default: /* (%si) -> 4 or (%di) -> 5 */
5517 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5519 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5521 else /* i.base_reg and 32/64 bit mode */
5523 if (flag_code
== CODE_64BIT
5524 && operand_type_check (i
.types
[op
], disp
))
5526 i386_operand_type temp
;
5527 operand_type_set (&temp
, 0);
5528 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5530 if (i
.prefix
[ADDR_PREFIX
] == 0)
5531 i
.types
[op
].bitfield
.disp32s
= 1;
5533 i
.types
[op
].bitfield
.disp32
= 1;
5536 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5537 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5539 i
.sib
.base
= i
.base_reg
->reg_num
;
5540 /* x86-64 ignores REX prefix bit here to avoid decoder
5542 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5545 if (i
.disp_operands
== 0)
5547 fake_zero_displacement
= 1;
5548 i
.types
[op
].bitfield
.disp8
= 1;
5551 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5555 i
.sib
.scale
= i
.log2_scale_factor
;
5556 if (i
.index_reg
== 0)
5558 /* <disp>(%esp) becomes two byte modrm with no index
5559 register. We've already stored the code for esp
5560 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5561 Any base register besides %esp will not use the
5562 extra modrm byte. */
5563 i
.sib
.index
= NO_INDEX_REGISTER
;
5567 if (i
.index_reg
->reg_num
== RegEiz
5568 || i
.index_reg
->reg_num
== RegRiz
)
5569 i
.sib
.index
= NO_INDEX_REGISTER
;
5571 i
.sib
.index
= i
.index_reg
->reg_num
;
5572 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5573 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5578 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5579 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5582 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5585 if (fake_zero_displacement
)
5587 /* Fakes a zero displacement assuming that i.types[op]
5588 holds the correct displacement size. */
5591 gas_assert (i
.op
[op
].disps
== 0);
5592 exp
= &disp_expressions
[i
.disp_operands
++];
5593 i
.op
[op
].disps
= exp
;
5594 exp
->X_op
= O_constant
;
5595 exp
->X_add_number
= 0;
5596 exp
->X_add_symbol
= (symbolS
*) 0;
5597 exp
->X_op_symbol
= (symbolS
*) 0;
5605 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
5607 if (operand_type_check (i
.types
[0], imm
))
5608 i
.vex
.register_specifier
= NULL
;
5611 /* VEX.vvvv encodes one of the sources when the first
5612 operand is not an immediate. */
5613 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5614 i
.vex
.register_specifier
= i
.op
[0].regs
;
5616 i
.vex
.register_specifier
= i
.op
[1].regs
;
5619 /* Destination is a XMM register encoded in the ModRM.reg
5621 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
5622 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
5625 /* ModRM.rm and VEX.B encodes the other source. */
5626 if (!i
.mem_operands
)
5630 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5631 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5633 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
5635 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5639 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
5641 i
.vex
.register_specifier
= i
.op
[2].regs
;
5642 if (!i
.mem_operands
)
5645 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5646 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5650 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5651 (if any) based on i.tm.extension_opcode. Again, we must be
5652 careful to make sure that segment/control/debug/test/MMX
5653 registers are coded into the i.rm.reg field. */
5654 else if (i
.reg_operands
)
5657 unsigned int vex_reg
= ~0;
5659 for (op
= 0; op
< i
.operands
; op
++)
5660 if (i
.types
[op
].bitfield
.reg8
5661 || i
.types
[op
].bitfield
.reg16
5662 || i
.types
[op
].bitfield
.reg32
5663 || i
.types
[op
].bitfield
.reg64
5664 || i
.types
[op
].bitfield
.regmmx
5665 || i
.types
[op
].bitfield
.regxmm
5666 || i
.types
[op
].bitfield
.regymm
5667 || i
.types
[op
].bitfield
.sreg2
5668 || i
.types
[op
].bitfield
.sreg3
5669 || i
.types
[op
].bitfield
.control
5670 || i
.types
[op
].bitfield
.debug
5671 || i
.types
[op
].bitfield
.test
)
5676 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5678 /* For instructions with VexNDS, the register-only
5679 source operand is encoded in VEX prefix. */
5680 gas_assert (mem
!= (unsigned int) ~0);
5685 gas_assert (op
< i
.operands
);
5689 /* Check register-only source operand when two source
5690 operands are swapped. */
5691 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
5692 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
5696 gas_assert (mem
== (vex_reg
+ 1)
5697 && op
< i
.operands
);
5702 gas_assert (vex_reg
< i
.operands
);
5706 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
5708 /* For instructions with VexNDD, the register destination
5709 is encoded in VEX prefix. */
5710 if (i
.mem_operands
== 0)
5712 /* There is no memory operand. */
5713 gas_assert ((op
+ 2) == i
.operands
);
5718 /* There are only 2 operands. */
5719 gas_assert (op
< 2 && i
.operands
== 2);
5724 gas_assert (op
< i
.operands
);
5726 if (vex_reg
!= (unsigned int) ~0)
5728 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
5730 if (type
->bitfield
.reg32
!= 1
5731 && type
->bitfield
.reg64
!= 1
5732 && !operand_type_equal (type
, ®xmm
)
5733 && !operand_type_equal (type
, ®ymm
))
5736 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5739 /* Don't set OP operand twice. */
5742 /* If there is an extension opcode to put here, the
5743 register number must be put into the regmem field. */
5744 if (i
.tm
.extension_opcode
!= None
)
5746 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5747 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5752 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5753 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5758 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5759 must set it to 3 to indicate this is a register operand
5760 in the regmem field. */
5761 if (!i
.mem_operands
)
5765 /* Fill in i.rm.reg field with extension opcode (if any). */
5766 if (i
.tm
.extension_opcode
!= None
)
5767 i
.rm
.reg
= i
.tm
.extension_opcode
;
5773 output_branch (void)
5779 relax_substateT subtype
;
5783 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
5784 size
= i
.disp32_encoding
? BIG
: SMALL
;
5787 if (i
.prefix
[DATA_PREFIX
] != 0)
5793 /* Pentium4 branch hints. */
5794 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5795 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5800 if (i
.prefix
[REX_PREFIX
] != 0)
5806 if (i
.prefixes
!= 0 && !intel_syntax
)
5807 as_warn (_("skipping prefixes on this instruction"));
5809 /* It's always a symbol; End frag & setup for relax.
5810 Make sure there is enough room in this frag for the largest
5811 instruction we may generate in md_convert_frag. This is 2
5812 bytes for the opcode and room for the prefix and largest
5814 frag_grow (prefix
+ 2 + 4);
5815 /* Prefix and 1 opcode byte go in fr_fix. */
5816 p
= frag_more (prefix
+ 1);
5817 if (i
.prefix
[DATA_PREFIX
] != 0)
5818 *p
++ = DATA_PREFIX_OPCODE
;
5819 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5820 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5821 *p
++ = i
.prefix
[SEG_PREFIX
];
5822 if (i
.prefix
[REX_PREFIX
] != 0)
5823 *p
++ = i
.prefix
[REX_PREFIX
];
5824 *p
= i
.tm
.base_opcode
;
5826 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5827 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
5828 else if (cpu_arch_flags
.bitfield
.cpui386
)
5829 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
5831 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
5834 sym
= i
.op
[0].disps
->X_add_symbol
;
5835 off
= i
.op
[0].disps
->X_add_number
;
5837 if (i
.op
[0].disps
->X_op
!= O_constant
5838 && i
.op
[0].disps
->X_op
!= O_symbol
)
5840 /* Handle complex expressions. */
5841 sym
= make_expr_symbol (i
.op
[0].disps
);
5845 /* 1 possible extra opcode + 4 byte displacement go in var part.
5846 Pass reloc in fr_var. */
5847 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5857 if (i
.tm
.opcode_modifier
.jumpbyte
)
5859 /* This is a loop or jecxz type instruction. */
5861 if (i
.prefix
[ADDR_PREFIX
] != 0)
5863 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5866 /* Pentium4 branch hints. */
5867 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5868 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5870 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5879 if (flag_code
== CODE_16BIT
)
5882 if (i
.prefix
[DATA_PREFIX
] != 0)
5884 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5894 if (i
.prefix
[REX_PREFIX
] != 0)
5896 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5900 if (i
.prefixes
!= 0 && !intel_syntax
)
5901 as_warn (_("skipping prefixes on this instruction"));
5903 p
= frag_more (1 + size
);
5904 *p
++ = i
.tm
.base_opcode
;
5906 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5907 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5909 /* All jumps handled here are signed, but don't use a signed limit
5910 check for 32 and 16 bit jumps as we want to allow wrap around at
5911 4G and 64k respectively. */
5913 fixP
->fx_signed
= 1;
5917 output_interseg_jump (void)
5925 if (flag_code
== CODE_16BIT
)
5929 if (i
.prefix
[DATA_PREFIX
] != 0)
5935 if (i
.prefix
[REX_PREFIX
] != 0)
5945 if (i
.prefixes
!= 0 && !intel_syntax
)
5946 as_warn (_("skipping prefixes on this instruction"));
5948 /* 1 opcode; 2 segment; offset */
5949 p
= frag_more (prefix
+ 1 + 2 + size
);
5951 if (i
.prefix
[DATA_PREFIX
] != 0)
5952 *p
++ = DATA_PREFIX_OPCODE
;
5954 if (i
.prefix
[REX_PREFIX
] != 0)
5955 *p
++ = i
.prefix
[REX_PREFIX
];
5957 *p
++ = i
.tm
.base_opcode
;
5958 if (i
.op
[1].imms
->X_op
== O_constant
)
5960 offsetT n
= i
.op
[1].imms
->X_add_number
;
5963 && !fits_in_unsigned_word (n
)
5964 && !fits_in_signed_word (n
))
5966 as_bad (_("16-bit jump out of range"));
5969 md_number_to_chars (p
, n
, size
);
5972 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5973 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5974 if (i
.op
[0].imms
->X_op
!= O_constant
)
5975 as_bad (_("can't handle non absolute segment in `%s'"),
5977 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5983 fragS
*insn_start_frag
;
5984 offsetT insn_start_off
;
5986 /* Tie dwarf2 debug info to the address at the start of the insn.
5987 We can't do this after the insn has been output as the current
5988 frag may have been closed off. eg. by frag_var. */
5989 dwarf2_emit_insn (0);
5991 insn_start_frag
= frag_now
;
5992 insn_start_off
= frag_now_fix ();
5995 if (i
.tm
.opcode_modifier
.jump
)
5997 else if (i
.tm
.opcode_modifier
.jumpbyte
5998 || i
.tm
.opcode_modifier
.jumpdword
)
6000 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6001 output_interseg_jump ();
6004 /* Output normal instructions here. */
6008 unsigned int prefix
;
6010 /* Since the VEX prefix contains the implicit prefix, we don't
6011 need the explicit prefix. */
6012 if (!i
.tm
.opcode_modifier
.vex
)
6014 switch (i
.tm
.opcode_length
)
6017 if (i
.tm
.base_opcode
& 0xff000000)
6019 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6024 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6026 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6027 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6030 if (prefix
!= REPE_PREFIX_OPCODE
6031 || (i
.prefix
[REP_PREFIX
]
6032 != REPE_PREFIX_OPCODE
))
6033 add_prefix (prefix
);
6036 add_prefix (prefix
);
6045 /* The prefix bytes. */
6046 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6048 FRAG_APPEND_1_CHAR (*q
);
6051 if (i
.tm
.opcode_modifier
.vex
)
6053 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
6058 /* REX byte is encoded in VEX prefix. */
6062 FRAG_APPEND_1_CHAR (*q
);
6065 /* There should be no other prefixes for instructions
6070 /* Now the VEX prefix. */
6071 p
= frag_more (i
.vex
.length
);
6072 for (j
= 0; j
< i
.vex
.length
; j
++)
6073 p
[j
] = i
.vex
.bytes
[j
];
6076 /* Now the opcode; be careful about word order here! */
6077 if (i
.tm
.opcode_length
== 1)
6079 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
6083 switch (i
.tm
.opcode_length
)
6087 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
6097 /* Put out high byte first: can't use md_number_to_chars! */
6098 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
6099 *p
= i
.tm
.base_opcode
& 0xff;
6102 /* Now the modrm byte and sib byte (if present). */
6103 if (i
.tm
.opcode_modifier
.modrm
)
6105 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
6108 /* If i.rm.regmem == ESP (4)
6109 && i.rm.mode != (Register mode)
6111 ==> need second modrm byte. */
6112 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
6114 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
6115 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
6117 | i
.sib
.scale
<< 6));
6120 if (i
.disp_operands
)
6121 output_disp (insn_start_frag
, insn_start_off
);
6124 output_imm (insn_start_frag
, insn_start_off
);
6130 pi ("" /*line*/, &i
);
6132 #endif /* DEBUG386 */
6135 /* Return the size of the displacement operand N. */
6138 disp_size (unsigned int n
)
6141 if (i
.types
[n
].bitfield
.disp64
)
6143 else if (i
.types
[n
].bitfield
.disp8
)
6145 else if (i
.types
[n
].bitfield
.disp16
)
6150 /* Return the size of the immediate operand N. */
6153 imm_size (unsigned int n
)
6156 if (i
.types
[n
].bitfield
.imm64
)
6158 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6160 else if (i
.types
[n
].bitfield
.imm16
)
6166 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6171 for (n
= 0; n
< i
.operands
; n
++)
6173 if (operand_type_check (i
.types
[n
], disp
))
6175 if (i
.op
[n
].disps
->X_op
== O_constant
)
6177 int size
= disp_size (n
);
6180 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6182 p
= frag_more (size
);
6183 md_number_to_chars (p
, val
, size
);
6187 enum bfd_reloc_code_real reloc_type
;
6188 int size
= disp_size (n
);
6189 int sign
= i
.types
[n
].bitfield
.disp32s
;
6190 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6192 /* We can't have 8 bit displacement here. */
6193 gas_assert (!i
.types
[n
].bitfield
.disp8
);
6195 /* The PC relative address is computed relative
6196 to the instruction boundary, so in case immediate
6197 fields follows, we need to adjust the value. */
6198 if (pcrel
&& i
.imm_operands
)
6203 for (n1
= 0; n1
< i
.operands
; n1
++)
6204 if (operand_type_check (i
.types
[n1
], imm
))
6206 /* Only one immediate is allowed for PC
6207 relative address. */
6208 gas_assert (sz
== 0);
6210 i
.op
[n
].disps
->X_add_number
-= sz
;
6212 /* We should find the immediate. */
6213 gas_assert (sz
!= 0);
6216 p
= frag_more (size
);
6217 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6219 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6220 && (((reloc_type
== BFD_RELOC_32
6221 || reloc_type
== BFD_RELOC_X86_64_32S
6222 || (reloc_type
== BFD_RELOC_64
6224 && (i
.op
[n
].disps
->X_op
== O_symbol
6225 || (i
.op
[n
].disps
->X_op
== O_add
6226 && ((symbol_get_value_expression
6227 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6229 || reloc_type
== BFD_RELOC_32_PCREL
))
6233 if (insn_start_frag
== frag_now
)
6234 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6239 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6240 for (fr
= insn_start_frag
->fr_next
;
6241 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6243 add
+= p
- frag_now
->fr_literal
;
6248 reloc_type
= BFD_RELOC_386_GOTPC
;
6249 i
.op
[n
].imms
->X_add_number
+= add
;
6251 else if (reloc_type
== BFD_RELOC_64
)
6252 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6254 /* Don't do the adjustment for x86-64, as there
6255 the pcrel addressing is relative to the _next_
6256 insn, and that is taken care of in other code. */
6257 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6259 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6260 i
.op
[n
].disps
, pcrel
, reloc_type
);
6267 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6272 for (n
= 0; n
< i
.operands
; n
++)
6274 if (operand_type_check (i
.types
[n
], imm
))
6276 if (i
.op
[n
].imms
->X_op
== O_constant
)
6278 int size
= imm_size (n
);
6281 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6283 p
= frag_more (size
);
6284 md_number_to_chars (p
, val
, size
);
6288 /* Not absolute_section.
6289 Need a 32-bit fixup (don't support 8bit
6290 non-absolute imms). Try to support other
6292 enum bfd_reloc_code_real reloc_type
;
6293 int size
= imm_size (n
);
6296 if (i
.types
[n
].bitfield
.imm32s
6297 && (i
.suffix
== QWORD_MNEM_SUFFIX
6298 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6303 p
= frag_more (size
);
6304 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6306 /* This is tough to explain. We end up with this one if we
6307 * have operands that look like
6308 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6309 * obtain the absolute address of the GOT, and it is strongly
6310 * preferable from a performance point of view to avoid using
6311 * a runtime relocation for this. The actual sequence of
6312 * instructions often look something like:
6317 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6319 * The call and pop essentially return the absolute address
6320 * of the label .L66 and store it in %ebx. The linker itself
6321 * will ultimately change the first operand of the addl so
6322 * that %ebx points to the GOT, but to keep things simple, the
6323 * .o file must have this operand set so that it generates not
6324 * the absolute address of .L66, but the absolute address of
6325 * itself. This allows the linker itself simply treat a GOTPC
6326 * relocation as asking for a pcrel offset to the GOT to be
6327 * added in, and the addend of the relocation is stored in the
6328 * operand field for the instruction itself.
6330 * Our job here is to fix the operand so that it would add
6331 * the correct offset so that %ebx would point to itself. The
6332 * thing that is tricky is that .-.L66 will point to the
6333 * beginning of the instruction, so we need to further modify
6334 * the operand so that it will point to itself. There are
6335 * other cases where you have something like:
6337 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6339 * and here no correction would be required. Internally in
6340 * the assembler we treat operands of this form as not being
6341 * pcrel since the '.' is explicitly mentioned, and I wonder
6342 * whether it would simplify matters to do it this way. Who
6343 * knows. In earlier versions of the PIC patches, the
6344 * pcrel_adjust field was used to store the correction, but
6345 * since the expression is not pcrel, I felt it would be
6346 * confusing to do it this way. */
6348 if ((reloc_type
== BFD_RELOC_32
6349 || reloc_type
== BFD_RELOC_X86_64_32S
6350 || reloc_type
== BFD_RELOC_64
)
6352 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6353 && (i
.op
[n
].imms
->X_op
== O_symbol
6354 || (i
.op
[n
].imms
->X_op
== O_add
6355 && ((symbol_get_value_expression
6356 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6361 if (insn_start_frag
== frag_now
)
6362 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6367 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6368 for (fr
= insn_start_frag
->fr_next
;
6369 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6371 add
+= p
- frag_now
->fr_literal
;
6375 reloc_type
= BFD_RELOC_386_GOTPC
;
6377 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6379 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6380 i
.op
[n
].imms
->X_add_number
+= add
;
6382 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6383 i
.op
[n
].imms
, 0, reloc_type
);
6389 /* x86_cons_fix_new is called via the expression parsing code when a
6390 reloc is needed. We use this hook to get the correct .got reloc. */
6391 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6392 static int cons_sign
= -1;
6395 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6398 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6400 got_reloc
= NO_RELOC
;
6403 if (exp
->X_op
== O_secrel
)
6405 exp
->X_op
= O_symbol
;
6406 r
= BFD_RELOC_32_SECREL
;
6410 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6413 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6414 # define lex_got(reloc, adjust, types) NULL
6416 /* Parse operands of the form
6417 <symbol>@GOTOFF+<nnn>
6418 and similar .plt or .got references.
6420 If we find one, set up the correct relocation in RELOC and copy the
6421 input string, minus the `@GOTOFF' into a malloc'd buffer for
6422 parsing by the calling routine. Return this buffer, and if ADJUST
6423 is non-null set it to the length of the string we removed from the
6424 input line. Otherwise return NULL. */
6426 lex_got (enum bfd_reloc_code_real
*rel
,
6428 i386_operand_type
*types
)
6430 /* Some of the relocations depend on the size of what field is to
6431 be relocated. But in our callers i386_immediate and i386_displacement
6432 we don't yet know the operand size (this will be set by insn
6433 matching). Hence we record the word32 relocation here,
6434 and adjust the reloc according to the real size in reloc(). */
6435 static const struct {
6438 const enum bfd_reloc_code_real rel
[2];
6439 const i386_operand_type types64
;
6441 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
6442 BFD_RELOC_X86_64_PLTOFF64
},
6443 OPERAND_TYPE_IMM64
},
6444 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
6445 BFD_RELOC_X86_64_PLT32
},
6446 OPERAND_TYPE_IMM32_32S_DISP32
},
6447 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
6448 BFD_RELOC_X86_64_GOTPLT64
},
6449 OPERAND_TYPE_IMM64_DISP64
},
6450 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
6451 BFD_RELOC_X86_64_GOTOFF64
},
6452 OPERAND_TYPE_IMM64_DISP64
},
6453 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
6454 BFD_RELOC_X86_64_GOTPCREL
},
6455 OPERAND_TYPE_IMM32_32S_DISP32
},
6456 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
6457 BFD_RELOC_X86_64_TLSGD
},
6458 OPERAND_TYPE_IMM32_32S_DISP32
},
6459 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
6460 _dummy_first_bfd_reloc_code_real
},
6461 OPERAND_TYPE_NONE
},
6462 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
6463 BFD_RELOC_X86_64_TLSLD
},
6464 OPERAND_TYPE_IMM32_32S_DISP32
},
6465 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
6466 BFD_RELOC_X86_64_GOTTPOFF
},
6467 OPERAND_TYPE_IMM32_32S_DISP32
},
6468 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
6469 BFD_RELOC_X86_64_TPOFF32
},
6470 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6471 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
6472 _dummy_first_bfd_reloc_code_real
},
6473 OPERAND_TYPE_NONE
},
6474 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
6475 BFD_RELOC_X86_64_DTPOFF32
},
6476 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6477 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
6478 _dummy_first_bfd_reloc_code_real
},
6479 OPERAND_TYPE_NONE
},
6480 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
6481 _dummy_first_bfd_reloc_code_real
},
6482 OPERAND_TYPE_NONE
},
6483 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
6484 BFD_RELOC_X86_64_GOT32
},
6485 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6486 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
6487 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6488 OPERAND_TYPE_IMM32_32S_DISP32
},
6489 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
6490 BFD_RELOC_X86_64_TLSDESC_CALL
},
6491 OPERAND_TYPE_IMM32_32S_DISP32
},
6499 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6500 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6503 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6505 int len
= gotrel
[j
].len
;
6506 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6508 if (gotrel
[j
].rel
[object_64bit
] != 0)
6511 char *tmpbuf
, *past_reloc
;
6513 *rel
= gotrel
[j
].rel
[object_64bit
];
6519 if (flag_code
!= CODE_64BIT
)
6521 types
->bitfield
.imm32
= 1;
6522 types
->bitfield
.disp32
= 1;
6525 *types
= gotrel
[j
].types64
;
6528 if (GOT_symbol
== NULL
)
6529 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6531 /* The length of the first part of our input line. */
6532 first
= cp
- input_line_pointer
;
6534 /* The second part goes from after the reloc token until
6535 (and including) an end_of_line char or comma. */
6536 past_reloc
= cp
+ 1 + len
;
6538 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6540 second
= cp
+ 1 - past_reloc
;
6542 /* Allocate and copy string. The trailing NUL shouldn't
6543 be necessary, but be safe. */
6544 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6545 memcpy (tmpbuf
, input_line_pointer
, first
);
6546 if (second
!= 0 && *past_reloc
!= ' ')
6547 /* Replace the relocation token with ' ', so that
6548 errors like foo@GOTOFF1 will be detected. */
6549 tmpbuf
[first
++] = ' ';
6550 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6551 tmpbuf
[first
+ second
] = '\0';
6555 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6556 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6561 /* Might be a symbol version string. Don't as_bad here. */
6567 x86_cons (expressionS
*exp
, int size
)
6569 intel_syntax
= -intel_syntax
;
6572 if (size
== 4 || (object_64bit
&& size
== 8))
6574 /* Handle @GOTOFF and the like in an expression. */
6576 char *gotfree_input_line
;
6579 save
= input_line_pointer
;
6580 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6581 if (gotfree_input_line
)
6582 input_line_pointer
= gotfree_input_line
;
6586 if (gotfree_input_line
)
6588 /* expression () has merrily parsed up to the end of line,
6589 or a comma - in the wrong buffer. Transfer how far
6590 input_line_pointer has moved to the right buffer. */
6591 input_line_pointer
= (save
6592 + (input_line_pointer
- gotfree_input_line
)
6594 free (gotfree_input_line
);
6595 if (exp
->X_op
== O_constant
6596 || exp
->X_op
== O_absent
6597 || exp
->X_op
== O_illegal
6598 || exp
->X_op
== O_register
6599 || exp
->X_op
== O_big
)
6601 char c
= *input_line_pointer
;
6602 *input_line_pointer
= 0;
6603 as_bad (_("missing or invalid expression `%s'"), save
);
6604 *input_line_pointer
= c
;
6611 intel_syntax
= -intel_syntax
;
6614 i386_intel_simplify (exp
);
6618 signed_cons (int size
)
6620 if (flag_code
== CODE_64BIT
)
6628 pe_directive_secrel (dummy
)
6629 int dummy ATTRIBUTE_UNUSED
;
6636 if (exp
.X_op
== O_symbol
)
6637 exp
.X_op
= O_secrel
;
6639 emit_expr (&exp
, 4);
6641 while (*input_line_pointer
++ == ',');
6643 input_line_pointer
--;
6644 demand_empty_rest_of_line ();
6649 i386_immediate (char *imm_start
)
6651 char *save_input_line_pointer
;
6652 char *gotfree_input_line
;
6655 i386_operand_type types
;
6657 operand_type_set (&types
, ~0);
6659 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6661 as_bad (_("at most %d immediate operands are allowed"),
6662 MAX_IMMEDIATE_OPERANDS
);
6666 exp
= &im_expressions
[i
.imm_operands
++];
6667 i
.op
[this_operand
].imms
= exp
;
6669 if (is_space_char (*imm_start
))
6672 save_input_line_pointer
= input_line_pointer
;
6673 input_line_pointer
= imm_start
;
6675 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6676 if (gotfree_input_line
)
6677 input_line_pointer
= gotfree_input_line
;
6679 exp_seg
= expression (exp
);
6682 if (*input_line_pointer
)
6683 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6685 input_line_pointer
= save_input_line_pointer
;
6686 if (gotfree_input_line
)
6688 free (gotfree_input_line
);
6690 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6691 exp
->X_op
= O_illegal
;
6694 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6698 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6699 i386_operand_type types
, const char *imm_start
)
6701 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6704 as_bad (_("missing or invalid immediate expression `%s'"),
6708 else if (exp
->X_op
== O_constant
)
6710 /* Size it properly later. */
6711 i
.types
[this_operand
].bitfield
.imm64
= 1;
6712 /* If not 64bit, sign extend val. */
6713 if (flag_code
!= CODE_64BIT
6714 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6716 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6718 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6719 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6720 && exp_seg
!= absolute_section
6721 && exp_seg
!= text_section
6722 && exp_seg
!= data_section
6723 && exp_seg
!= bss_section
6724 && exp_seg
!= undefined_section
6725 && !bfd_is_com_section (exp_seg
))
6727 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6731 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6734 as_bad (_("illegal immediate register operand %s"), imm_start
);
6739 /* This is an address. The size of the address will be
6740 determined later, depending on destination register,
6741 suffix, or the default for the section. */
6742 i
.types
[this_operand
].bitfield
.imm8
= 1;
6743 i
.types
[this_operand
].bitfield
.imm16
= 1;
6744 i
.types
[this_operand
].bitfield
.imm32
= 1;
6745 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6746 i
.types
[this_operand
].bitfield
.imm64
= 1;
6747 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6755 i386_scale (char *scale
)
6758 char *save
= input_line_pointer
;
6760 input_line_pointer
= scale
;
6761 val
= get_absolute_expression ();
6766 i
.log2_scale_factor
= 0;
6769 i
.log2_scale_factor
= 1;
6772 i
.log2_scale_factor
= 2;
6775 i
.log2_scale_factor
= 3;
6779 char sep
= *input_line_pointer
;
6781 *input_line_pointer
= '\0';
6782 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6784 *input_line_pointer
= sep
;
6785 input_line_pointer
= save
;
6789 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6791 as_warn (_("scale factor of %d without an index register"),
6792 1 << i
.log2_scale_factor
);
6793 i
.log2_scale_factor
= 0;
6795 scale
= input_line_pointer
;
6796 input_line_pointer
= save
;
6801 i386_displacement (char *disp_start
, char *disp_end
)
6805 char *save_input_line_pointer
;
6806 char *gotfree_input_line
;
6808 i386_operand_type bigdisp
, types
= anydisp
;
6811 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6813 as_bad (_("at most %d displacement operands are allowed"),
6814 MAX_MEMORY_OPERANDS
);
6818 operand_type_set (&bigdisp
, 0);
6819 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6820 || (!current_templates
->start
->opcode_modifier
.jump
6821 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6823 bigdisp
.bitfield
.disp32
= 1;
6824 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6825 if (flag_code
== CODE_64BIT
)
6829 bigdisp
.bitfield
.disp32s
= 1;
6830 bigdisp
.bitfield
.disp64
= 1;
6833 else if ((flag_code
== CODE_16BIT
) ^ override
)
6835 bigdisp
.bitfield
.disp32
= 0;
6836 bigdisp
.bitfield
.disp16
= 1;
6841 /* For PC-relative branches, the width of the displacement
6842 is dependent upon data size, not address size. */
6843 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6844 if (flag_code
== CODE_64BIT
)
6846 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6847 bigdisp
.bitfield
.disp16
= 1;
6850 bigdisp
.bitfield
.disp32
= 1;
6851 bigdisp
.bitfield
.disp32s
= 1;
6857 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6859 : LONG_MNEM_SUFFIX
));
6860 bigdisp
.bitfield
.disp32
= 1;
6861 if ((flag_code
== CODE_16BIT
) ^ override
)
6863 bigdisp
.bitfield
.disp32
= 0;
6864 bigdisp
.bitfield
.disp16
= 1;
6868 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6871 exp
= &disp_expressions
[i
.disp_operands
];
6872 i
.op
[this_operand
].disps
= exp
;
6874 save_input_line_pointer
= input_line_pointer
;
6875 input_line_pointer
= disp_start
;
6876 END_STRING_AND_SAVE (disp_end
);
6878 #ifndef GCC_ASM_O_HACK
6879 #define GCC_ASM_O_HACK 0
6882 END_STRING_AND_SAVE (disp_end
+ 1);
6883 if (i
.types
[this_operand
].bitfield
.baseIndex
6884 && displacement_string_end
[-1] == '+')
6886 /* This hack is to avoid a warning when using the "o"
6887 constraint within gcc asm statements.
6890 #define _set_tssldt_desc(n,addr,limit,type) \
6891 __asm__ __volatile__ ( \
6893 "movw %w1,2+%0\n\t" \
6895 "movb %b1,4+%0\n\t" \
6896 "movb %4,5+%0\n\t" \
6897 "movb $0,6+%0\n\t" \
6898 "movb %h1,7+%0\n\t" \
6900 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6902 This works great except that the output assembler ends
6903 up looking a bit weird if it turns out that there is
6904 no offset. You end up producing code that looks like:
6917 So here we provide the missing zero. */
6919 *displacement_string_end
= '0';
6922 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6923 if (gotfree_input_line
)
6924 input_line_pointer
= gotfree_input_line
;
6926 exp_seg
= expression (exp
);
6929 if (*input_line_pointer
)
6930 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6932 RESTORE_END_STRING (disp_end
+ 1);
6934 input_line_pointer
= save_input_line_pointer
;
6935 if (gotfree_input_line
)
6937 free (gotfree_input_line
);
6939 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6940 exp
->X_op
= O_illegal
;
6943 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6945 RESTORE_END_STRING (disp_end
);
6951 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6952 i386_operand_type types
, const char *disp_start
)
6954 i386_operand_type bigdisp
;
6957 /* We do this to make sure that the section symbol is in
6958 the symbol table. We will ultimately change the relocation
6959 to be relative to the beginning of the section. */
6960 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6961 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6962 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6964 if (exp
->X_op
!= O_symbol
)
6967 if (S_IS_LOCAL (exp
->X_add_symbol
)
6968 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
6969 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
6970 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6971 exp
->X_op
= O_subtract
;
6972 exp
->X_op_symbol
= GOT_symbol
;
6973 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6974 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6975 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6976 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6978 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6981 else if (exp
->X_op
== O_absent
6982 || exp
->X_op
== O_illegal
6983 || exp
->X_op
== O_big
)
6986 as_bad (_("missing or invalid displacement expression `%s'"),
6991 else if (flag_code
== CODE_64BIT
6992 && !i
.prefix
[ADDR_PREFIX
]
6993 && exp
->X_op
== O_constant
)
6995 /* Since displacement is signed extended to 64bit, don't allow
6996 disp32 and turn off disp32s if they are out of range. */
6997 i
.types
[this_operand
].bitfield
.disp32
= 0;
6998 if (!fits_in_signed_long (exp
->X_add_number
))
7000 i
.types
[this_operand
].bitfield
.disp32s
= 0;
7001 if (i
.types
[this_operand
].bitfield
.baseindex
)
7003 as_bad (_("0x%lx out range of signed 32bit displacement"),
7004 (long) exp
->X_add_number
);
7010 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7011 else if (exp
->X_op
!= O_constant
7012 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
7013 && exp_seg
!= absolute_section
7014 && exp_seg
!= text_section
7015 && exp_seg
!= data_section
7016 && exp_seg
!= bss_section
7017 && exp_seg
!= undefined_section
7018 && !bfd_is_com_section (exp_seg
))
7020 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7025 /* Check if this is a displacement only operand. */
7026 bigdisp
= i
.types
[this_operand
];
7027 bigdisp
.bitfield
.disp8
= 0;
7028 bigdisp
.bitfield
.disp16
= 0;
7029 bigdisp
.bitfield
.disp32
= 0;
7030 bigdisp
.bitfield
.disp32s
= 0;
7031 bigdisp
.bitfield
.disp64
= 0;
7032 if (operand_type_all_zero (&bigdisp
))
7033 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7039 /* Make sure the memory operand we've been dealt is valid.
7040 Return 1 on success, 0 on a failure. */
7043 i386_index_check (const char *operand_string
)
7046 const char *kind
= "base/index";
7047 #if INFER_ADDR_PREFIX
7053 if (current_templates
->start
->opcode_modifier
.isstring
7054 && !current_templates
->start
->opcode_modifier
.immext
7055 && (current_templates
->end
[-1].opcode_modifier
.isstring
7058 /* Memory operands of string insns are special in that they only allow
7059 a single register (rDI, rSI, or rBX) as their memory address. */
7060 unsigned int expected
;
7062 kind
= "string address";
7064 if (current_templates
->start
->opcode_modifier
.w
)
7066 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
7068 if (!type
.bitfield
.baseindex
7069 || ((!i
.mem_operands
!= !intel_syntax
)
7070 && current_templates
->end
[-1].operand_types
[1]
7071 .bitfield
.baseindex
))
7072 type
= current_templates
->end
[-1].operand_types
[1];
7073 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
7076 expected
= 3 /* rBX */;
7078 if (!i
.base_reg
|| i
.index_reg
7079 || operand_type_check (i
.types
[this_operand
], disp
))
7081 else if (!(flag_code
== CODE_64BIT
7082 ? i
.prefix
[ADDR_PREFIX
]
7083 ? i
.base_reg
->reg_type
.bitfield
.reg32
7084 : i
.base_reg
->reg_type
.bitfield
.reg64
7085 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
7086 ? i
.base_reg
->reg_type
.bitfield
.reg32
7087 : i
.base_reg
->reg_type
.bitfield
.reg16
))
7089 else if (i
.base_reg
->reg_num
!= expected
)
7096 for (j
= 0; j
< i386_regtab_size
; ++j
)
7097 if ((flag_code
== CODE_64BIT
7098 ? i
.prefix
[ADDR_PREFIX
]
7099 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7100 : i386_regtab
[j
].reg_type
.bitfield
.reg64
7101 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
7102 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7103 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
7104 && i386_regtab
[j
].reg_num
== expected
)
7106 gas_assert (j
< i386_regtab_size
);
7107 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7109 intel_syntax
? '[' : '(',
7111 i386_regtab
[j
].reg_name
,
7112 intel_syntax
? ']' : ')');
7116 else if (flag_code
== CODE_64BIT
)
7119 && ((i
.prefix
[ADDR_PREFIX
] == 0
7120 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
7121 || (i
.prefix
[ADDR_PREFIX
]
7122 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
7124 || i
.base_reg
->reg_num
!=
7125 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
7127 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
7128 || (i
.prefix
[ADDR_PREFIX
] == 0
7129 && i
.index_reg
->reg_num
!= RegRiz
7130 && !i
.index_reg
->reg_type
.bitfield
.reg64
7132 || (i
.prefix
[ADDR_PREFIX
]
7133 && i
.index_reg
->reg_num
!= RegEiz
7134 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
7139 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7143 && (!i
.base_reg
->reg_type
.bitfield
.reg16
7144 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
7146 && (!i
.index_reg
->reg_type
.bitfield
.reg16
7147 || !i
.index_reg
->reg_type
.bitfield
.baseindex
7149 && i
.base_reg
->reg_num
< 6
7150 && i
.index_reg
->reg_num
>= 6
7151 && i
.log2_scale_factor
== 0))))
7158 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
7160 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
7161 && i
.index_reg
->reg_num
!= RegEiz
)
7162 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7168 #if INFER_ADDR_PREFIX
7169 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
7171 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7173 /* Change the size of any displacement too. At most one of
7174 Disp16 or Disp32 is set.
7175 FIXME. There doesn't seem to be any real need for separate
7176 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
7177 Removing them would probably clean up the code quite a lot. */
7178 if (flag_code
!= CODE_64BIT
7179 && (i
.types
[this_operand
].bitfield
.disp16
7180 || i
.types
[this_operand
].bitfield
.disp32
))
7181 i
.types
[this_operand
]
7182 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7187 as_bad (_("`%s' is not a valid %s expression"),
7192 as_bad (_("`%s' is not a valid %s-bit %s expression"),
7194 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
7195 ? flag_code
== CODE_32BIT
7204 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7208 i386_att_operand (char *operand_string
)
7212 char *op_string
= operand_string
;
7214 if (is_space_char (*op_string
))
7217 /* We check for an absolute prefix (differentiating,
7218 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7219 if (*op_string
== ABSOLUTE_PREFIX
)
7222 if (is_space_char (*op_string
))
7224 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7227 /* Check if operand is a register. */
7228 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7230 i386_operand_type temp
;
7232 /* Check for a segment override by searching for ':' after a
7233 segment register. */
7235 if (is_space_char (*op_string
))
7237 if (*op_string
== ':'
7238 && (r
->reg_type
.bitfield
.sreg2
7239 || r
->reg_type
.bitfield
.sreg3
))
7244 i
.seg
[i
.mem_operands
] = &es
;
7247 i
.seg
[i
.mem_operands
] = &cs
;
7250 i
.seg
[i
.mem_operands
] = &ss
;
7253 i
.seg
[i
.mem_operands
] = &ds
;
7256 i
.seg
[i
.mem_operands
] = &fs
;
7259 i
.seg
[i
.mem_operands
] = &gs
;
7263 /* Skip the ':' and whitespace. */
7265 if (is_space_char (*op_string
))
7268 if (!is_digit_char (*op_string
)
7269 && !is_identifier_char (*op_string
)
7270 && *op_string
!= '('
7271 && *op_string
!= ABSOLUTE_PREFIX
)
7273 as_bad (_("bad memory operand `%s'"), op_string
);
7276 /* Handle case of %es:*foo. */
7277 if (*op_string
== ABSOLUTE_PREFIX
)
7280 if (is_space_char (*op_string
))
7282 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7284 goto do_memory_reference
;
7288 as_bad (_("junk `%s' after register"), op_string
);
7292 temp
.bitfield
.baseindex
= 0;
7293 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7295 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7296 i
.op
[this_operand
].regs
= r
;
7299 else if (*op_string
== REGISTER_PREFIX
)
7301 as_bad (_("bad register name `%s'"), op_string
);
7304 else if (*op_string
== IMMEDIATE_PREFIX
)
7307 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7309 as_bad (_("immediate operand illegal with absolute jump"));
7312 if (!i386_immediate (op_string
))
7315 else if (is_digit_char (*op_string
)
7316 || is_identifier_char (*op_string
)
7317 || *op_string
== '(')
7319 /* This is a memory reference of some sort. */
7322 /* Start and end of displacement string expression (if found). */
7323 char *displacement_string_start
;
7324 char *displacement_string_end
;
7326 do_memory_reference
:
7327 if ((i
.mem_operands
== 1
7328 && !current_templates
->start
->opcode_modifier
.isstring
)
7329 || i
.mem_operands
== 2)
7331 as_bad (_("too many memory references for `%s'"),
7332 current_templates
->start
->name
);
7336 /* Check for base index form. We detect the base index form by
7337 looking for an ')' at the end of the operand, searching
7338 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7340 base_string
= op_string
+ strlen (op_string
);
7343 if (is_space_char (*base_string
))
7346 /* If we only have a displacement, set-up for it to be parsed later. */
7347 displacement_string_start
= op_string
;
7348 displacement_string_end
= base_string
+ 1;
7350 if (*base_string
== ')')
7353 unsigned int parens_balanced
= 1;
7354 /* We've already checked that the number of left & right ()'s are
7355 equal, so this loop will not be infinite. */
7359 if (*base_string
== ')')
7361 if (*base_string
== '(')
7364 while (parens_balanced
);
7366 temp_string
= base_string
;
7368 /* Skip past '(' and whitespace. */
7370 if (is_space_char (*base_string
))
7373 if (*base_string
== ','
7374 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7377 displacement_string_end
= temp_string
;
7379 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7383 base_string
= end_op
;
7384 if (is_space_char (*base_string
))
7388 /* There may be an index reg or scale factor here. */
7389 if (*base_string
== ',')
7392 if (is_space_char (*base_string
))
7395 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7398 base_string
= end_op
;
7399 if (is_space_char (*base_string
))
7401 if (*base_string
== ',')
7404 if (is_space_char (*base_string
))
7407 else if (*base_string
!= ')')
7409 as_bad (_("expecting `,' or `)' "
7410 "after index register in `%s'"),
7415 else if (*base_string
== REGISTER_PREFIX
)
7417 as_bad (_("bad register name `%s'"), base_string
);
7421 /* Check for scale factor. */
7422 if (*base_string
!= ')')
7424 char *end_scale
= i386_scale (base_string
);
7429 base_string
= end_scale
;
7430 if (is_space_char (*base_string
))
7432 if (*base_string
!= ')')
7434 as_bad (_("expecting `)' "
7435 "after scale factor in `%s'"),
7440 else if (!i
.index_reg
)
7442 as_bad (_("expecting index register or scale factor "
7443 "after `,'; got '%c'"),
7448 else if (*base_string
!= ')')
7450 as_bad (_("expecting `,' or `)' "
7451 "after base register in `%s'"),
7456 else if (*base_string
== REGISTER_PREFIX
)
7458 as_bad (_("bad register name `%s'"), base_string
);
7463 /* If there's an expression beginning the operand, parse it,
7464 assuming displacement_string_start and
7465 displacement_string_end are meaningful. */
7466 if (displacement_string_start
!= displacement_string_end
)
7468 if (!i386_displacement (displacement_string_start
,
7469 displacement_string_end
))
7473 /* Special case for (%dx) while doing input/output op. */
7475 && operand_type_equal (&i
.base_reg
->reg_type
,
7476 ®16_inoutportreg
)
7478 && i
.log2_scale_factor
== 0
7479 && i
.seg
[i
.mem_operands
] == 0
7480 && !operand_type_check (i
.types
[this_operand
], disp
))
7482 i
.types
[this_operand
] = inoutportreg
;
7486 if (i386_index_check (operand_string
) == 0)
7488 i
.types
[this_operand
].bitfield
.mem
= 1;
7493 /* It's not a memory operand; argh! */
7494 as_bad (_("invalid char %s beginning operand %d `%s'"),
7495 output_invalid (*op_string
),
7500 return 1; /* Normal return. */
7503 /* md_estimate_size_before_relax()
7505 Called just before relax() for rs_machine_dependent frags. The x86
7506 assembler uses these frags to handle variable size jump
7509 Any symbol that is now undefined will not become defined.
7510 Return the correct fr_subtype in the frag.
7511 Return the initial "guess for variable size of frag" to caller.
7512 The guess is actually the growth beyond the fixed part. Whatever
7513 we do to grow the fixed or variable part contributes to our
7517 md_estimate_size_before_relax (fragP
, segment
)
7521 /* We've already got fragP->fr_subtype right; all we have to do is
7522 check for un-relaxable symbols. On an ELF system, we can't relax
7523 an externally visible symbol, because it may be overridden by a
7525 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7526 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7528 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7529 || S_IS_WEAK (fragP
->fr_symbol
)
7530 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7531 & BSF_GNU_INDIRECT_FUNCTION
))))
7533 #if defined (OBJ_COFF) && defined (TE_PE)
7534 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7535 && S_IS_WEAK (fragP
->fr_symbol
))
7539 /* Symbol is undefined in this segment, or we need to keep a
7540 reloc so that weak symbols can be overridden. */
7541 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7542 enum bfd_reloc_code_real reloc_type
;
7543 unsigned char *opcode
;
7546 if (fragP
->fr_var
!= NO_RELOC
)
7547 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7549 reloc_type
= BFD_RELOC_16_PCREL
;
7551 reloc_type
= BFD_RELOC_32_PCREL
;
7553 old_fr_fix
= fragP
->fr_fix
;
7554 opcode
= (unsigned char *) fragP
->fr_opcode
;
7556 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7559 /* Make jmp (0xeb) a (d)word displacement jump. */
7561 fragP
->fr_fix
+= size
;
7562 fix_new (fragP
, old_fr_fix
, size
,
7564 fragP
->fr_offset
, 1,
7570 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7572 /* Negate the condition, and branch past an
7573 unconditional jump. */
7576 /* Insert an unconditional jump. */
7578 /* We added two extra opcode bytes, and have a two byte
7580 fragP
->fr_fix
+= 2 + 2;
7581 fix_new (fragP
, old_fr_fix
+ 2, 2,
7583 fragP
->fr_offset
, 1,
7590 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7595 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7597 fragP
->fr_offset
, 1,
7599 fixP
->fx_signed
= 1;
7603 /* This changes the byte-displacement jump 0x7N
7604 to the (d)word-displacement jump 0x0f,0x8N. */
7605 opcode
[1] = opcode
[0] + 0x10;
7606 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7607 /* We've added an opcode byte. */
7608 fragP
->fr_fix
+= 1 + size
;
7609 fix_new (fragP
, old_fr_fix
+ 1, size
,
7611 fragP
->fr_offset
, 1,
7616 BAD_CASE (fragP
->fr_subtype
);
7620 return fragP
->fr_fix
- old_fr_fix
;
7623 /* Guess size depending on current relax state. Initially the relax
7624 state will correspond to a short jump and we return 1, because
7625 the variable part of the frag (the branch offset) is one byte
7626 long. However, we can relax a section more than once and in that
7627 case we must either set fr_subtype back to the unrelaxed state,
7628 or return the value for the appropriate branch. */
7629 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7632 /* Called after relax() is finished.
7634 In: Address of frag.
7635 fr_type == rs_machine_dependent.
7636 fr_subtype is what the address relaxed to.
7638 Out: Any fixSs and constants are set up.
7639 Caller will turn frag into a ".space 0". */
7642 md_convert_frag (abfd
, sec
, fragP
)
7643 bfd
*abfd ATTRIBUTE_UNUSED
;
7644 segT sec ATTRIBUTE_UNUSED
;
7647 unsigned char *opcode
;
7648 unsigned char *where_to_put_displacement
= NULL
;
7649 offsetT target_address
;
7650 offsetT opcode_address
;
7651 unsigned int extension
= 0;
7652 offsetT displacement_from_opcode_start
;
7654 opcode
= (unsigned char *) fragP
->fr_opcode
;
7656 /* Address we want to reach in file space. */
7657 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7659 /* Address opcode resides at in file space. */
7660 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7662 /* Displacement from opcode start to fill into instruction. */
7663 displacement_from_opcode_start
= target_address
- opcode_address
;
7665 if ((fragP
->fr_subtype
& BIG
) == 0)
7667 /* Don't have to change opcode. */
7668 extension
= 1; /* 1 opcode + 1 displacement */
7669 where_to_put_displacement
= &opcode
[1];
7673 if (no_cond_jump_promotion
7674 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7675 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7676 _("long jump required"));
7678 switch (fragP
->fr_subtype
)
7680 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7681 extension
= 4; /* 1 opcode + 4 displacement */
7683 where_to_put_displacement
= &opcode
[1];
7686 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7687 extension
= 2; /* 1 opcode + 2 displacement */
7689 where_to_put_displacement
= &opcode
[1];
7692 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7693 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7694 extension
= 5; /* 2 opcode + 4 displacement */
7695 opcode
[1] = opcode
[0] + 0x10;
7696 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7697 where_to_put_displacement
= &opcode
[2];
7700 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7701 extension
= 3; /* 2 opcode + 2 displacement */
7702 opcode
[1] = opcode
[0] + 0x10;
7703 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7704 where_to_put_displacement
= &opcode
[2];
7707 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7712 where_to_put_displacement
= &opcode
[3];
7716 BAD_CASE (fragP
->fr_subtype
);
7721 /* If size if less then four we are sure that the operand fits,
7722 but if it's 4, then it could be that the displacement is larger
7724 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7726 && ((addressT
) (displacement_from_opcode_start
- extension
7727 + ((addressT
) 1 << 31))
7728 > (((addressT
) 2 << 31) - 1)))
7730 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7731 _("jump target out of range"));
7732 /* Make us emit 0. */
7733 displacement_from_opcode_start
= extension
;
7735 /* Now put displacement after opcode. */
7736 md_number_to_chars ((char *) where_to_put_displacement
,
7737 (valueT
) (displacement_from_opcode_start
- extension
),
7738 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7739 fragP
->fr_fix
+= extension
;
7742 /* Apply a fixup (fixS) to segment data, once it has been determined
7743 by our caller that we have all the info we need to fix it up.
7745 On the 386, immediates, displacements, and data pointers are all in
7746 the same (little-endian) format, so we don't need to care about which
7750 md_apply_fix (fixP
, valP
, seg
)
7751 /* The fix we're to put in. */
7753 /* Pointer to the value of the bits. */
7755 /* Segment fix is from. */
7756 segT seg ATTRIBUTE_UNUSED
;
7758 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7759 valueT value
= *valP
;
7761 #if !defined (TE_Mach)
7764 switch (fixP
->fx_r_type
)
7770 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7773 case BFD_RELOC_X86_64_32S
:
7774 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7777 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7780 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7785 if (fixP
->fx_addsy
!= NULL
7786 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7787 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7788 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7789 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7790 && !use_rela_relocations
)
7792 /* This is a hack. There should be a better way to handle this.
7793 This covers for the fact that bfd_install_relocation will
7794 subtract the current location (for partial_inplace, PC relative
7795 relocations); see more below. */
7799 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7802 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7804 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7807 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7810 || (symbol_section_p (fixP
->fx_addsy
)
7811 && sym_seg
!= absolute_section
))
7812 && !generic_force_reloc (fixP
))
7814 /* Yes, we add the values in twice. This is because
7815 bfd_install_relocation subtracts them out again. I think
7816 bfd_install_relocation is broken, but I don't dare change
7818 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7822 #if defined (OBJ_COFF) && defined (TE_PE)
7823 /* For some reason, the PE format does not store a
7824 section address offset for a PC relative symbol. */
7825 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7826 || S_IS_WEAK (fixP
->fx_addsy
))
7827 value
+= md_pcrel_from (fixP
);
7830 #if defined (OBJ_COFF) && defined (TE_PE)
7831 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7833 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7837 /* Fix a few things - the dynamic linker expects certain values here,
7838 and we must not disappoint it. */
7839 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7840 if (IS_ELF
&& fixP
->fx_addsy
)
7841 switch (fixP
->fx_r_type
)
7843 case BFD_RELOC_386_PLT32
:
7844 case BFD_RELOC_X86_64_PLT32
:
7845 /* Make the jump instruction point to the address of the operand. At
7846 runtime we merely add the offset to the actual PLT entry. */
7850 case BFD_RELOC_386_TLS_GD
:
7851 case BFD_RELOC_386_TLS_LDM
:
7852 case BFD_RELOC_386_TLS_IE_32
:
7853 case BFD_RELOC_386_TLS_IE
:
7854 case BFD_RELOC_386_TLS_GOTIE
:
7855 case BFD_RELOC_386_TLS_GOTDESC
:
7856 case BFD_RELOC_X86_64_TLSGD
:
7857 case BFD_RELOC_X86_64_TLSLD
:
7858 case BFD_RELOC_X86_64_GOTTPOFF
:
7859 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7860 value
= 0; /* Fully resolved at runtime. No addend. */
7862 case BFD_RELOC_386_TLS_LE
:
7863 case BFD_RELOC_386_TLS_LDO_32
:
7864 case BFD_RELOC_386_TLS_LE_32
:
7865 case BFD_RELOC_X86_64_DTPOFF32
:
7866 case BFD_RELOC_X86_64_DTPOFF64
:
7867 case BFD_RELOC_X86_64_TPOFF32
:
7868 case BFD_RELOC_X86_64_TPOFF64
:
7869 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7872 case BFD_RELOC_386_TLS_DESC_CALL
:
7873 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7874 value
= 0; /* Fully resolved at runtime. No addend. */
7875 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7879 case BFD_RELOC_386_GOT32
:
7880 case BFD_RELOC_X86_64_GOT32
:
7881 value
= 0; /* Fully resolved at runtime. No addend. */
7884 case BFD_RELOC_VTABLE_INHERIT
:
7885 case BFD_RELOC_VTABLE_ENTRY
:
7892 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7894 #endif /* !defined (TE_Mach) */
7896 /* Are we finished with this relocation now? */
7897 if (fixP
->fx_addsy
== NULL
)
7899 #if defined (OBJ_COFF) && defined (TE_PE)
7900 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7903 /* Remember value for tc_gen_reloc. */
7904 fixP
->fx_addnumber
= value
;
7905 /* Clear out the frag for now. */
7909 else if (use_rela_relocations
)
7911 fixP
->fx_no_overflow
= 1;
7912 /* Remember value for tc_gen_reloc. */
7913 fixP
->fx_addnumber
= value
;
7917 md_number_to_chars (p
, value
, fixP
->fx_size
);
7921 md_atof (int type
, char *litP
, int *sizeP
)
7923 /* This outputs the LITTLENUMs in REVERSE order;
7924 in accord with the bigendian 386. */
7925 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7928 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7931 output_invalid (int c
)
7934 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7937 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7938 "(0x%x)", (unsigned char) c
);
7939 return output_invalid_buf
;
7942 /* REG_STRING starts *before* REGISTER_PREFIX. */
7944 static const reg_entry
*
7945 parse_real_register (char *reg_string
, char **end_op
)
7947 char *s
= reg_string
;
7949 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7952 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7953 if (*s
== REGISTER_PREFIX
)
7956 if (is_space_char (*s
))
7960 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7962 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7963 return (const reg_entry
*) NULL
;
7967 /* For naked regs, make sure that we are not dealing with an identifier.
7968 This prevents confusing an identifier like `eax_var' with register
7970 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7971 return (const reg_entry
*) NULL
;
7975 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7977 /* Handle floating point regs, allowing spaces in the (i) part. */
7978 if (r
== i386_regtab
/* %st is first entry of table */)
7980 if (is_space_char (*s
))
7985 if (is_space_char (*s
))
7987 if (*s
>= '0' && *s
<= '7')
7991 if (is_space_char (*s
))
7996 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
8001 /* We have "%st(" then garbage. */
8002 return (const reg_entry
*) NULL
;
8006 if (r
== NULL
|| allow_pseudo_reg
)
8009 if (operand_type_all_zero (&r
->reg_type
))
8010 return (const reg_entry
*) NULL
;
8012 if ((r
->reg_type
.bitfield
.reg32
8013 || r
->reg_type
.bitfield
.sreg3
8014 || r
->reg_type
.bitfield
.control
8015 || r
->reg_type
.bitfield
.debug
8016 || r
->reg_type
.bitfield
.test
)
8017 && !cpu_arch_flags
.bitfield
.cpui386
)
8018 return (const reg_entry
*) NULL
;
8020 if (r
->reg_type
.bitfield
.floatreg
8021 && !cpu_arch_flags
.bitfield
.cpu8087
8022 && !cpu_arch_flags
.bitfield
.cpu287
8023 && !cpu_arch_flags
.bitfield
.cpu387
)
8024 return (const reg_entry
*) NULL
;
8026 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
8027 return (const reg_entry
*) NULL
;
8029 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
8030 return (const reg_entry
*) NULL
;
8032 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
8033 return (const reg_entry
*) NULL
;
8035 /* Don't allow fake index register unless allow_index_reg isn't 0. */
8036 if (!allow_index_reg
8037 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
8038 return (const reg_entry
*) NULL
;
8040 if (((r
->reg_flags
& (RegRex64
| RegRex
))
8041 || r
->reg_type
.bitfield
.reg64
)
8042 && (!cpu_arch_flags
.bitfield
.cpulm
8043 || !operand_type_equal (&r
->reg_type
, &control
))
8044 && flag_code
!= CODE_64BIT
)
8045 return (const reg_entry
*) NULL
;
8047 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
8048 return (const reg_entry
*) NULL
;
8053 /* REG_STRING starts *before* REGISTER_PREFIX. */
8055 static const reg_entry
*
8056 parse_register (char *reg_string
, char **end_op
)
8060 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
8061 r
= parse_real_register (reg_string
, end_op
);
8066 char *save
= input_line_pointer
;
8070 input_line_pointer
= reg_string
;
8071 c
= get_symbol_end ();
8072 symbolP
= symbol_find (reg_string
);
8073 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
8075 const expressionS
*e
= symbol_get_value_expression (symbolP
);
8077 know (e
->X_op
== O_register
);
8078 know (e
->X_add_number
>= 0
8079 && (valueT
) e
->X_add_number
< i386_regtab_size
);
8080 r
= i386_regtab
+ e
->X_add_number
;
8081 *end_op
= input_line_pointer
;
8083 *input_line_pointer
= c
;
8084 input_line_pointer
= save
;
8090 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
8093 char *end
= input_line_pointer
;
8096 r
= parse_register (name
, &input_line_pointer
);
8097 if (r
&& end
<= input_line_pointer
)
8099 *nextcharP
= *input_line_pointer
;
8100 *input_line_pointer
= 0;
8101 e
->X_op
= O_register
;
8102 e
->X_add_number
= r
- i386_regtab
;
8105 input_line_pointer
= end
;
8107 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
8111 md_operand (expressionS
*e
)
8116 switch (*input_line_pointer
)
8118 case REGISTER_PREFIX
:
8119 r
= parse_real_register (input_line_pointer
, &end
);
8122 e
->X_op
= O_register
;
8123 e
->X_add_number
= r
- i386_regtab
;
8124 input_line_pointer
= end
;
8129 gas_assert (intel_syntax
);
8130 end
= input_line_pointer
++;
8132 if (*input_line_pointer
== ']')
8134 ++input_line_pointer
;
8135 e
->X_op_symbol
= make_expr_symbol (e
);
8136 e
->X_add_symbol
= NULL
;
8137 e
->X_add_number
= 0;
8143 input_line_pointer
= end
;
8150 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8151 const char *md_shortopts
= "kVQ:sqn";
8153 const char *md_shortopts
= "qn";
8156 #define OPTION_32 (OPTION_MD_BASE + 0)
8157 #define OPTION_64 (OPTION_MD_BASE + 1)
8158 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
8159 #define OPTION_MARCH (OPTION_MD_BASE + 3)
8160 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
8161 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8162 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8163 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8164 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8165 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
8166 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
8167 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
8168 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12)
8169 #define OPTION_X32 (OPTION_MD_BASE + 13)
8171 struct option md_longopts
[] =
8173 {"32", no_argument
, NULL
, OPTION_32
},
8174 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8175 || defined (TE_PE) || defined (TE_PEP))
8176 {"64", no_argument
, NULL
, OPTION_64
},
8178 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8179 {"x32", no_argument
, NULL
, OPTION_X32
},
8181 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
8182 {"march", required_argument
, NULL
, OPTION_MARCH
},
8183 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
8184 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
8185 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
8186 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
8187 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
8188 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
8189 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
8190 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
8191 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
8192 {NULL
, no_argument
, NULL
, 0}
8194 size_t md_longopts_size
= sizeof (md_longopts
);
8197 md_parse_option (int c
, char *arg
)
8205 optimize_align_code
= 0;
8212 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8213 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8214 should be emitted or not. FIXME: Not implemented. */
8218 /* -V: SVR4 argument to print version ID. */
8220 print_version_id ();
8223 /* -k: Ignore for FreeBSD compatibility. */
8228 /* -s: On i386 Solaris, this tells the native assembler to use
8229 .stab instead of .stab.excl. We always use .stab anyhow. */
8232 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8233 || defined (TE_PE) || defined (TE_PEP))
8236 const char **list
, **l
;
8238 list
= bfd_target_list ();
8239 for (l
= list
; *l
!= NULL
; l
++)
8240 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8241 || strcmp (*l
, "coff-x86-64") == 0
8242 || strcmp (*l
, "pe-x86-64") == 0
8243 || strcmp (*l
, "pei-x86-64") == 0)
8245 default_arch
= "x86_64";
8249 as_fatal (_("no compiled in support for x86_64"));
8255 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8259 const char **list
, **l
;
8261 list
= bfd_target_list ();
8262 for (l
= list
; *l
!= NULL
; l
++)
8263 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
8265 default_arch
= "x86_64:32";
8269 as_fatal (_("no compiled in support for 32bit x86_64"));
8273 as_fatal (_("32bit x86_64 is only supported for ELF"));
8278 default_arch
= "i386";
8282 #ifdef SVR4_COMMENT_CHARS
8287 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8289 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8293 i386_comment_chars
= n
;
8299 arch
= xstrdup (arg
);
8303 as_fatal (_("invalid -march= option: `%s'"), arg
);
8304 next
= strchr (arch
, '+');
8307 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8309 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
8312 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8315 cpu_arch_name
= cpu_arch
[j
].name
;
8316 cpu_sub_arch_name
= NULL
;
8317 cpu_arch_flags
= cpu_arch
[j
].flags
;
8318 cpu_arch_isa
= cpu_arch
[j
].type
;
8319 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
8320 if (!cpu_arch_tune_set
)
8322 cpu_arch_tune
= cpu_arch_isa
;
8323 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8327 else if (*cpu_arch
[j
].name
== '.'
8328 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
8330 /* ISA entension. */
8331 i386_cpu_flags flags
;
8333 if (!cpu_arch
[j
].negated
)
8334 flags
= cpu_flags_or (cpu_arch_flags
,
8337 flags
= cpu_flags_and_not (cpu_arch_flags
,
8339 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8341 if (cpu_sub_arch_name
)
8343 char *name
= cpu_sub_arch_name
;
8344 cpu_sub_arch_name
= concat (name
,
8346 (const char *) NULL
);
8350 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
8351 cpu_arch_flags
= flags
;
8352 cpu_arch_isa_flags
= flags
;
8358 if (j
>= ARRAY_SIZE (cpu_arch
))
8359 as_fatal (_("invalid -march= option: `%s'"), arg
);
8363 while (next
!= NULL
);
8368 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
8369 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8371 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
8373 cpu_arch_tune_set
= 1;
8374 cpu_arch_tune
= cpu_arch
[j
].type
;
8375 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
8379 if (j
>= ARRAY_SIZE (cpu_arch
))
8380 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
8383 case OPTION_MMNEMONIC
:
8384 if (strcasecmp (arg
, "att") == 0)
8386 else if (strcasecmp (arg
, "intel") == 0)
8389 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
8392 case OPTION_MSYNTAX
:
8393 if (strcasecmp (arg
, "att") == 0)
8395 else if (strcasecmp (arg
, "intel") == 0)
8398 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
8401 case OPTION_MINDEX_REG
:
8402 allow_index_reg
= 1;
8405 case OPTION_MNAKED_REG
:
8406 allow_naked_reg
= 1;
8409 case OPTION_MOLD_GCC
:
8413 case OPTION_MSSE2AVX
:
8417 case OPTION_MSSE_CHECK
:
8418 if (strcasecmp (arg
, "error") == 0)
8419 sse_check
= sse_check_error
;
8420 else if (strcasecmp (arg
, "warning") == 0)
8421 sse_check
= sse_check_warning
;
8422 else if (strcasecmp (arg
, "none") == 0)
8423 sse_check
= sse_check_none
;
8425 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
8428 case OPTION_MAVXSCALAR
:
8429 if (strcasecmp (arg
, "128") == 0)
8431 else if (strcasecmp (arg
, "256") == 0)
8434 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
8443 #define MESSAGE_TEMPLATE \
8447 show_arch (FILE *stream
, int ext
, int check
)
8449 static char message
[] = MESSAGE_TEMPLATE
;
8450 char *start
= message
+ 27;
8452 int size
= sizeof (MESSAGE_TEMPLATE
);
8459 left
= size
- (start
- message
);
8460 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8462 /* Should it be skipped? */
8463 if (cpu_arch
[j
].skip
)
8466 name
= cpu_arch
[j
].name
;
8467 len
= cpu_arch
[j
].len
;
8470 /* It is an extension. Skip if we aren't asked to show it. */
8481 /* It is an processor. Skip if we show only extension. */
8484 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8486 /* It is an impossible processor - skip. */
8490 /* Reserve 2 spaces for ", " or ",\0" */
8493 /* Check if there is any room. */
8501 p
= mempcpy (p
, name
, len
);
8505 /* Output the current message now and start a new one. */
8508 fprintf (stream
, "%s\n", message
);
8510 left
= size
- (start
- message
) - len
- 2;
8512 gas_assert (left
>= 0);
8514 p
= mempcpy (p
, name
, len
);
8519 fprintf (stream
, "%s\n", message
);
8523 md_show_usage (FILE *stream
)
8525 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8526 fprintf (stream
, _("\
8528 -V print assembler version number\n\
8531 fprintf (stream
, _("\
8532 -n Do not optimize code alignment\n\
8533 -q quieten some warnings\n"));
8534 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8535 fprintf (stream
, _("\
8538 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8539 || defined (TE_PE) || defined (TE_PEP))
8540 fprintf (stream
, _("\
8541 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
8543 #ifdef SVR4_COMMENT_CHARS
8544 fprintf (stream
, _("\
8545 --divide do not treat `/' as a comment character\n"));
8547 fprintf (stream
, _("\
8548 --divide ignored\n"));
8550 fprintf (stream
, _("\
8551 -march=CPU[,+EXTENSION...]\n\
8552 generate code for CPU and EXTENSION, CPU is one of:\n"));
8553 show_arch (stream
, 0, 1);
8554 fprintf (stream
, _("\
8555 EXTENSION is combination of:\n"));
8556 show_arch (stream
, 1, 0);
8557 fprintf (stream
, _("\
8558 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8559 show_arch (stream
, 0, 0);
8560 fprintf (stream
, _("\
8561 -msse2avx encode SSE instructions with VEX prefix\n"));
8562 fprintf (stream
, _("\
8563 -msse-check=[none|error|warning]\n\
8564 check SSE instructions\n"));
8565 fprintf (stream
, _("\
8566 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8568 fprintf (stream
, _("\
8569 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8570 fprintf (stream
, _("\
8571 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8572 fprintf (stream
, _("\
8573 -mindex-reg support pseudo index registers\n"));
8574 fprintf (stream
, _("\
8575 -mnaked-reg don't require `%%' prefix for registers\n"));
8576 fprintf (stream
, _("\
8577 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8580 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8581 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8582 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8584 /* Pick the target format to use. */
8587 i386_target_format (void)
8589 if (!strncmp (default_arch
, "x86_64", 6))
8591 update_code_flag (CODE_64BIT
, 1);
8592 if (default_arch
[6] == '\0')
8593 x86_elf_abi
= X86_64_ABI
;
8595 x86_elf_abi
= X86_64_X32_ABI
;
8597 else if (!strcmp (default_arch
, "i386"))
8598 update_code_flag (CODE_32BIT
, 1);
8600 as_fatal (_("unknown architecture"));
8602 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8603 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
8604 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8605 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
8607 switch (OUTPUT_FLAVOR
)
8609 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
8610 case bfd_target_aout_flavour
:
8611 return AOUT_TARGET_FORMAT
;
8613 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8614 # if defined (TE_PE) || defined (TE_PEP)
8615 case bfd_target_coff_flavour
:
8616 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
8617 # elif defined (TE_GO32)
8618 case bfd_target_coff_flavour
:
8621 case bfd_target_coff_flavour
:
8625 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8626 case bfd_target_elf_flavour
:
8630 switch (x86_elf_abi
)
8633 format
= ELF_TARGET_FORMAT
;
8636 use_rela_relocations
= 1;
8638 format
= ELF_TARGET_FORMAT64
;
8640 case X86_64_X32_ABI
:
8641 use_rela_relocations
= 1;
8643 disallow_64bit_reloc
= 1;
8644 format
= ELF_TARGET_FORMAT32
;
8647 if (cpu_arch_isa
== PROCESSOR_L1OM
)
8649 if (x86_elf_abi
!= X86_64_ABI
)
8650 as_fatal (_("Intel L1OM is 64bit only"));
8651 return ELF_TARGET_L1OM_FORMAT
;
8657 #if defined (OBJ_MACH_O)
8658 case bfd_target_mach_o_flavour
:
8659 return flag_code
== CODE_64BIT
? "mach-o-x86-64" : "mach-o-i386";
8667 #endif /* OBJ_MAYBE_ more than one */
8669 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8671 i386_elf_emit_arch_note (void)
8673 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8676 asection
*seg
= now_seg
;
8677 subsegT subseg
= now_subseg
;
8678 Elf_Internal_Note i_note
;
8679 Elf_External_Note e_note
;
8680 asection
*note_secp
;
8683 /* Create the .note section. */
8684 note_secp
= subseg_new (".note", 0);
8685 bfd_set_section_flags (stdoutput
,
8687 SEC_HAS_CONTENTS
| SEC_READONLY
);
8689 /* Process the arch string. */
8690 len
= strlen (cpu_arch_name
);
8692 i_note
.namesz
= len
+ 1;
8694 i_note
.type
= NT_ARCH
;
8695 p
= frag_more (sizeof (e_note
.namesz
));
8696 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8697 p
= frag_more (sizeof (e_note
.descsz
));
8698 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8699 p
= frag_more (sizeof (e_note
.type
));
8700 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8701 p
= frag_more (len
+ 1);
8702 strcpy (p
, cpu_arch_name
);
8704 frag_align (2, 0, 0);
8706 subseg_set (seg
, subseg
);
8712 md_undefined_symbol (name
)
8715 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8716 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8717 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8718 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8722 if (symbol_find (name
))
8723 as_bad (_("GOT already in symbol table"));
8724 GOT_symbol
= symbol_new (name
, undefined_section
,
8725 (valueT
) 0, &zero_address_frag
);
8732 /* Round up a section size to the appropriate boundary. */
8735 md_section_align (segment
, size
)
8736 segT segment ATTRIBUTE_UNUSED
;
8739 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8740 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8742 /* For a.out, force the section size to be aligned. If we don't do
8743 this, BFD will align it for us, but it will not write out the
8744 final bytes of the section. This may be a bug in BFD, but it is
8745 easier to fix it here since that is how the other a.out targets
8749 align
= bfd_get_section_alignment (stdoutput
, segment
);
8750 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8757 /* On the i386, PC-relative offsets are relative to the start of the
8758 next instruction. That is, the address of the offset, plus its
8759 size, since the offset is always the last part of the insn. */
8762 md_pcrel_from (fixS
*fixP
)
8764 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8770 s_bss (int ignore ATTRIBUTE_UNUSED
)
8774 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8776 obj_elf_section_change_hook ();
8778 temp
= get_absolute_expression ();
8779 subseg_set (bss_section
, (subsegT
) temp
);
8780 demand_empty_rest_of_line ();
8786 i386_validate_fix (fixS
*fixp
)
8788 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8790 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8794 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8799 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8801 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8808 tc_gen_reloc (section
, fixp
)
8809 asection
*section ATTRIBUTE_UNUSED
;
8813 bfd_reloc_code_real_type code
;
8815 switch (fixp
->fx_r_type
)
8817 case BFD_RELOC_X86_64_PLT32
:
8818 case BFD_RELOC_X86_64_GOT32
:
8819 case BFD_RELOC_X86_64_GOTPCREL
:
8820 case BFD_RELOC_386_PLT32
:
8821 case BFD_RELOC_386_GOT32
:
8822 case BFD_RELOC_386_GOTOFF
:
8823 case BFD_RELOC_386_GOTPC
:
8824 case BFD_RELOC_386_TLS_GD
:
8825 case BFD_RELOC_386_TLS_LDM
:
8826 case BFD_RELOC_386_TLS_LDO_32
:
8827 case BFD_RELOC_386_TLS_IE_32
:
8828 case BFD_RELOC_386_TLS_IE
:
8829 case BFD_RELOC_386_TLS_GOTIE
:
8830 case BFD_RELOC_386_TLS_LE_32
:
8831 case BFD_RELOC_386_TLS_LE
:
8832 case BFD_RELOC_386_TLS_GOTDESC
:
8833 case BFD_RELOC_386_TLS_DESC_CALL
:
8834 case BFD_RELOC_X86_64_TLSGD
:
8835 case BFD_RELOC_X86_64_TLSLD
:
8836 case BFD_RELOC_X86_64_DTPOFF32
:
8837 case BFD_RELOC_X86_64_DTPOFF64
:
8838 case BFD_RELOC_X86_64_GOTTPOFF
:
8839 case BFD_RELOC_X86_64_TPOFF32
:
8840 case BFD_RELOC_X86_64_TPOFF64
:
8841 case BFD_RELOC_X86_64_GOTOFF64
:
8842 case BFD_RELOC_X86_64_GOTPC32
:
8843 case BFD_RELOC_X86_64_GOT64
:
8844 case BFD_RELOC_X86_64_GOTPCREL64
:
8845 case BFD_RELOC_X86_64_GOTPC64
:
8846 case BFD_RELOC_X86_64_GOTPLT64
:
8847 case BFD_RELOC_X86_64_PLTOFF64
:
8848 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8849 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8851 case BFD_RELOC_VTABLE_ENTRY
:
8852 case BFD_RELOC_VTABLE_INHERIT
:
8854 case BFD_RELOC_32_SECREL
:
8856 code
= fixp
->fx_r_type
;
8858 case BFD_RELOC_X86_64_32S
:
8859 if (!fixp
->fx_pcrel
)
8861 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8862 code
= fixp
->fx_r_type
;
8868 switch (fixp
->fx_size
)
8871 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8872 _("can not do %d byte pc-relative relocation"),
8874 code
= BFD_RELOC_32_PCREL
;
8876 case 1: code
= BFD_RELOC_8_PCREL
; break;
8877 case 2: code
= BFD_RELOC_16_PCREL
; break;
8878 case 4: code
= BFD_RELOC_32_PCREL
; break;
8880 case 8: code
= BFD_RELOC_64_PCREL
; break;
8886 switch (fixp
->fx_size
)
8889 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8890 _("can not do %d byte relocation"),
8892 code
= BFD_RELOC_32
;
8894 case 1: code
= BFD_RELOC_8
; break;
8895 case 2: code
= BFD_RELOC_16
; break;
8896 case 4: code
= BFD_RELOC_32
; break;
8898 case 8: code
= BFD_RELOC_64
; break;
8905 if ((code
== BFD_RELOC_32
8906 || code
== BFD_RELOC_32_PCREL
8907 || code
== BFD_RELOC_X86_64_32S
)
8909 && fixp
->fx_addsy
== GOT_symbol
)
8912 code
= BFD_RELOC_386_GOTPC
;
8914 code
= BFD_RELOC_X86_64_GOTPC32
;
8916 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8918 && fixp
->fx_addsy
== GOT_symbol
)
8920 code
= BFD_RELOC_X86_64_GOTPC64
;
8923 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8924 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8925 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8927 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8929 if (!use_rela_relocations
)
8931 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8932 vtable entry to be used in the relocation's section offset. */
8933 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8934 rel
->address
= fixp
->fx_offset
;
8935 #if defined (OBJ_COFF) && defined (TE_PE)
8936 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8937 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8942 /* Use the rela in 64bit mode. */
8945 if (disallow_64bit_reloc
)
8949 case BFD_RELOC_X86_64_DTPOFF64
:
8950 case BFD_RELOC_X86_64_TPOFF64
:
8951 case BFD_RELOC_64_PCREL
:
8952 case BFD_RELOC_X86_64_GOTOFF64
:
8953 case BFD_RELOC_X86_64_GOT64
:
8954 case BFD_RELOC_X86_64_GOTPCREL64
:
8955 case BFD_RELOC_X86_64_GOTPC64
:
8956 case BFD_RELOC_X86_64_GOTPLT64
:
8957 case BFD_RELOC_X86_64_PLTOFF64
:
8958 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8959 _("cannot represent relocation type %s in x32 mode"),
8960 bfd_get_reloc_code_name (code
));
8966 if (!fixp
->fx_pcrel
)
8967 rel
->addend
= fixp
->fx_offset
;
8971 case BFD_RELOC_X86_64_PLT32
:
8972 case BFD_RELOC_X86_64_GOT32
:
8973 case BFD_RELOC_X86_64_GOTPCREL
:
8974 case BFD_RELOC_X86_64_TLSGD
:
8975 case BFD_RELOC_X86_64_TLSLD
:
8976 case BFD_RELOC_X86_64_GOTTPOFF
:
8977 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8978 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8979 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8982 rel
->addend
= (section
->vma
8984 + fixp
->fx_addnumber
8985 + md_pcrel_from (fixp
));
8990 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8991 if (rel
->howto
== NULL
)
8993 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8994 _("cannot represent relocation type %s"),
8995 bfd_get_reloc_code_name (code
));
8996 /* Set howto to a garbage value so that we can keep going. */
8997 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8998 gas_assert (rel
->howto
!= NULL
);
9004 #include "tc-i386-intel.c"
9007 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
9009 int saved_naked_reg
;
9010 char saved_register_dot
;
9012 saved_naked_reg
= allow_naked_reg
;
9013 allow_naked_reg
= 1;
9014 saved_register_dot
= register_chars
['.'];
9015 register_chars
['.'] = '.';
9016 allow_pseudo_reg
= 1;
9017 expression_and_evaluate (exp
);
9018 allow_pseudo_reg
= 0;
9019 register_chars
['.'] = saved_register_dot
;
9020 allow_naked_reg
= saved_naked_reg
;
9022 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
9024 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
9026 exp
->X_op
= O_constant
;
9027 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
9028 .dw2_regnum
[flag_code
>> 1];
9031 exp
->X_op
= O_illegal
;
9036 tc_x86_frame_initial_instructions (void)
9038 static unsigned int sp_regno
[2];
9040 if (!sp_regno
[flag_code
>> 1])
9042 char *saved_input
= input_line_pointer
;
9043 char sp
[][4] = {"esp", "rsp"};
9046 input_line_pointer
= sp
[flag_code
>> 1];
9047 tc_x86_parse_to_dw2regnum (&exp
);
9048 gas_assert (exp
.X_op
== O_constant
);
9049 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
9050 input_line_pointer
= saved_input
;
9053 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
9054 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
9058 i386_elf_section_type (const char *str
, size_t len
)
9060 if (flag_code
== CODE_64BIT
9061 && len
== sizeof ("unwind") - 1
9062 && strncmp (str
, "unwind", 6) == 0)
9063 return SHT_X86_64_UNWIND
;
9070 i386_solaris_fix_up_eh_frame (segT sec
)
9072 if (flag_code
== CODE_64BIT
)
9073 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
9079 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
9083 exp
.X_op
= O_secrel
;
9084 exp
.X_add_symbol
= symbol
;
9085 exp
.X_add_number
= 0;
9086 emit_expr (&exp
, size
);
9090 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9091 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9094 x86_64_section_letter (int letter
, char **ptr_msg
)
9096 if (flag_code
== CODE_64BIT
)
9099 return SHF_X86_64_LARGE
;
9101 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
9104 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
9109 x86_64_section_word (char *str
, size_t len
)
9111 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
9112 return SHF_X86_64_LARGE
;
9118 handle_large_common (int small ATTRIBUTE_UNUSED
)
9120 if (flag_code
!= CODE_64BIT
)
9122 s_comm_internal (0, elf_common_parse
);
9123 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9127 static segT lbss_section
;
9128 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
9129 asection
*saved_bss_section
= bss_section
;
9131 if (lbss_section
== NULL
)
9133 flagword applicable
;
9135 subsegT subseg
= now_subseg
;
9137 /* The .lbss section is for local .largecomm symbols. */
9138 lbss_section
= subseg_new (".lbss", 0);
9139 applicable
= bfd_applicable_section_flags (stdoutput
);
9140 bfd_set_section_flags (stdoutput
, lbss_section
,
9141 applicable
& SEC_ALLOC
);
9142 seg_info (lbss_section
)->bss
= 1;
9144 subseg_set (seg
, subseg
);
9147 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
9148 bss_section
= lbss_section
;
9150 s_comm_internal (0, elf_common_parse
);
9152 elf_com_section_ptr
= saved_com_section_ptr
;
9153 bss_section
= saved_bss_section
;
9158 handle_quad (int nbytes
)
9162 if (x86_elf_abi
!= X86_64_X32_ABI
)
9168 if (is_it_end_of_statement ())
9170 demand_empty_rest_of_line ();
9176 if (*input_line_pointer
== '"')
9178 as_bad (_("unexpected `\"' in expression"));
9179 ignore_rest_of_line ();
9182 x86_cons (&exp
, nbytes
);
9183 /* Output 4 bytes if not constant. */
9184 if (exp
.X_op
!= O_constant
)
9186 emit_expr (&exp
, (unsigned int) nbytes
);
9187 /* Zero-extends to 8 bytes if not constant. */
9190 memset (&exp
, '\0', sizeof (exp
));
9191 exp
.X_op
= O_constant
;
9192 emit_expr (&exp
, nbytes
);
9196 while (*input_line_pointer
++ == ',');
9198 input_line_pointer
--; /* Put terminator back into stream. */
9200 demand_empty_rest_of_line ();
9202 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */