1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
136 unsigned int negated
; /* turn off indicated flags. */
140 static void update_code_flag (int, int);
141 static void set_code_flag (int);
142 static void set_16bit_gcc_code_flag (int);
143 static void set_intel_syntax (int);
144 static void set_intel_mnemonic (int);
145 static void set_allow_index_reg (int);
146 static void set_check (int);
147 static void set_cpu_arch (int);
149 static void pe_directive_secrel (int);
151 static void signed_cons (int);
152 static char *output_invalid (int c
);
153 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
155 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
157 static int i386_att_operand (char *);
158 static int i386_intel_operand (char *, int);
159 static int i386_intel_simplify (expressionS
*);
160 static int i386_intel_parse_name (const char *, expressionS
*);
161 static const reg_entry
*parse_register (char *, char **);
162 static char *parse_insn (char *, char *);
163 static char *parse_operands (char *, const char *);
164 static void swap_operands (void);
165 static void swap_2_operands (int, int);
166 static void optimize_imm (void);
167 static void optimize_disp (void);
168 static const insn_template
*match_template (void);
169 static int check_string (void);
170 static int process_suffix (void);
171 static int check_byte_reg (void);
172 static int check_long_reg (void);
173 static int check_qword_reg (void);
174 static int check_word_reg (void);
175 static int finalize_imm (void);
176 static int process_operands (void);
177 static const seg_entry
*build_modrm_byte (void);
178 static void output_insn (void);
179 static void output_imm (fragS
*, offsetT
);
180 static void output_disp (fragS
*, offsetT
);
182 static void s_bss (int);
184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
188 static const char *default_arch
= DEFAULT_ARCH
;
190 /* This struct describes rounding control and SAE in the instruction. */
204 static struct RC_Operation rc_op
;
206 /* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209 struct Mask_Operation
211 const reg_entry
*mask
;
212 unsigned int zeroing
;
213 /* The operand where this operation is associated. */
217 static struct Mask_Operation mask_op
;
219 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
221 struct Broadcast_Operation
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
226 /* Index of broadcasted operand. */
230 static struct Broadcast_Operation broadcast_op
;
235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes
[4];
238 /* Destination or source register specifier. */
239 const reg_entry
*register_specifier
;
242 /* 'md_assemble ()' gathers together information and puts it into a
249 const reg_entry
*regs
;
254 operand_size_mismatch
,
255 operand_type_mismatch
,
256 register_type_mismatch
,
257 number_of_operands_mismatch
,
258 invalid_instruction_suffix
,
261 unsupported_with_intel_mnemonic
,
264 invalid_vsib_address
,
265 invalid_vector_register_set
,
266 unsupported_vector_index_register
,
267 unsupported_broadcast
,
268 broadcast_not_on_src_operand
,
271 mask_not_on_destination
,
274 rc_sae_operand_not_last_imm
,
275 invalid_register_operand
,
281 /* TM holds the template for the insn were currently assembling. */
284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
288 /* OPERANDS gives the number of given operands. */
289 unsigned int operands
;
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
294 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
296 /* TYPES [i] is the type (see above #defines) which tells us how to
297 use OP[i] for the corresponding operand. */
298 i386_operand_type types
[MAX_OPERANDS
];
300 /* Displacement expression, immediate expression, or register for each
302 union i386_op op
[MAX_OPERANDS
];
304 /* Flags for operands. */
305 unsigned int flags
[MAX_OPERANDS
];
306 #define Operand_PCrel 1
308 /* Relocation type for operand */
309 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry
*base_reg
;
314 const reg_entry
*index_reg
;
315 unsigned int log2_scale_factor
;
317 /* SEG gives the seg_entries of this insn. They are zero unless
318 explicit segment overrides are given. */
319 const seg_entry
*seg
[2];
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes
;
324 unsigned char prefix
[MAX_PREFIXES
];
326 /* RM and SIB are the modrm byte and the sib byte where the
327 addressing modes of this insn are encoded. */
334 /* Masking attributes. */
335 struct Mask_Operation
*mask
;
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation
*rounding
;
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation
*broadcast
;
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift
;
346 /* Swap operand in encoding. */
347 unsigned int swap_operand
;
349 /* Prefer 8bit or 32bit displacement in encoding. */
352 disp_encoding_default
= 0,
358 const char *rep_prefix
;
361 const char *hle_prefix
;
363 /* Have BND prefix. */
364 const char *bnd_prefix
;
366 /* Need VREX to support upper 16 registers. */
370 enum i386_error error
;
373 typedef struct _i386_insn i386_insn
;
375 /* Link RC type with corresponding string, that'll be looked for in
384 static const struct RC_name RC_NamesTable
[] =
386 { rne
, STRING_COMMA_LEN ("rn-sae") },
387 { rd
, STRING_COMMA_LEN ("rd-sae") },
388 { ru
, STRING_COMMA_LEN ("ru-sae") },
389 { rz
, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly
, STRING_COMMA_LEN ("sae") },
393 /* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
395 const char extra_symbol_chars
[] = "*%-([{"
404 #if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
406 && !defined (TE_GNU) \
407 && !defined (TE_LINUX) \
408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
410 && !defined (TE_FreeBSD) \
411 && !defined (TE_DragonFly) \
412 && !defined (TE_NetBSD)))
413 /* This array holds the chars that always start a comment. If the
414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416 const char *i386_comment_chars
= "#/";
417 #define SVR4_COMMENT_CHARS 1
418 #define PREFIX_SEPARATOR '\\'
421 const char *i386_comment_chars
= "#";
422 #define PREFIX_SEPARATOR '/'
425 /* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
429 first line of the input file. This is because the compiler outputs
430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
432 '/' isn't otherwise defined. */
433 const char line_comment_chars
[] = "#/";
435 const char line_separator_chars
[] = ";";
437 /* Chars that can be used to separate mant from exp in floating point
439 const char EXP_CHARS
[] = "eE";
441 /* Chars that mean this number is a floating point constant
444 const char FLT_CHARS
[] = "fFdDxX";
446 /* Tables for lexical analysis. */
447 static char mnemonic_chars
[256];
448 static char register_chars
[256];
449 static char operand_chars
[256];
450 static char identifier_chars
[256];
451 static char digit_chars
[256];
453 /* Lexical macros. */
454 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455 #define is_operand_char(x) (operand_chars[(unsigned char) x])
456 #define is_register_char(x) (register_chars[(unsigned char) x])
457 #define is_space_char(x) ((x) == ' ')
458 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459 #define is_digit_char(x) (digit_chars[(unsigned char) x])
461 /* All non-digit non-letter characters that may occur in an operand. */
462 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
464 /* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
467 assembler instruction). */
468 static char save_stack
[32];
469 static char *save_stack_p
;
470 #define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472 #define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
475 /* The instruction we're assembling. */
478 /* Possible templates for current insn. */
479 static const templates
*current_templates
;
481 /* Per instruction expressionS buffers: max displacements & immediates. */
482 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
483 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
485 /* Current operand we are working on. */
486 static int this_operand
= -1;
488 /* We support four different modes. FLAG_CODE variable is used to distinguish
496 static enum flag_code flag_code
;
497 static unsigned int object_64bit
;
498 static unsigned int disallow_64bit_reloc
;
499 static int use_rela_relocations
= 0;
501 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
505 /* The ELF ABI to use. */
513 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
516 #if defined (TE_PE) || defined (TE_PEP)
517 /* Use big object file format. */
518 static int use_big_obj
= 0;
521 /* 1 for intel syntax,
523 static int intel_syntax
= 0;
525 /* 1 for intel mnemonic,
526 0 if att mnemonic. */
527 static int intel_mnemonic
= !SYSV386_COMPAT
;
529 /* 1 if support old (<= 2.8.1) versions of gcc. */
530 static int old_gcc
= OLDGCC_COMPAT
;
532 /* 1 if pseudo registers are permitted. */
533 static int allow_pseudo_reg
= 0;
535 /* 1 if register prefix % not required. */
536 static int allow_naked_reg
= 0;
538 /* 1 if the assembler should add BND prefix for all control-tranferring
539 instructions supporting it, even if this prefix wasn't specified
541 static int add_bnd_prefix
= 0;
543 /* 1 if pseudo index register, eiz/riz, is allowed . */
544 static int allow_index_reg
= 0;
546 /* 1 if the assembler should ignore LOCK prefix, even if it was
547 specified explicitly. */
548 static int omit_lock_prefix
= 0;
550 static enum check_kind
556 sse_check
, operand_check
= check_warning
;
558 /* Register prefix used for error message. */
559 static const char *register_prefix
= "%";
561 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
562 leave, push, and pop instructions so that gcc has the same stack
563 frame as in 32 bit mode. */
564 static char stackop_size
= '\0';
566 /* Non-zero to optimize code alignment. */
567 int optimize_align_code
= 1;
569 /* Non-zero to quieten some warnings. */
570 static int quiet_warnings
= 0;
573 static const char *cpu_arch_name
= NULL
;
574 static char *cpu_sub_arch_name
= NULL
;
576 /* CPU feature flags. */
577 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
579 /* If we have selected a cpu we are generating instructions for. */
580 static int cpu_arch_tune_set
= 0;
582 /* Cpu we are generating instructions for. */
583 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
585 /* CPU feature flags of cpu we are generating instructions for. */
586 static i386_cpu_flags cpu_arch_tune_flags
;
588 /* CPU instruction set architecture used. */
589 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
591 /* CPU feature flags of instruction set architecture used. */
592 i386_cpu_flags cpu_arch_isa_flags
;
594 /* If set, conditional jumps are not automatically promoted to handle
595 larger than a byte offset. */
596 static unsigned int no_cond_jump_promotion
= 0;
598 /* Encode SSE instructions with VEX prefix. */
599 static unsigned int sse2avx
;
601 /* Encode scalar AVX instructions with specific vector length. */
608 /* Encode scalar EVEX LIG instructions with specific vector length. */
616 /* Encode EVEX WIG instructions with specific evex.w. */
623 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
624 static enum rc_type evexrcig
= rne
;
626 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
627 static symbolS
*GOT_symbol
;
629 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
630 unsigned int x86_dwarf2_return_column
;
632 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
633 int x86_cie_data_alignment
;
635 /* Interface to relax_segment.
636 There are 3 major relax states for 386 jump insns because the
637 different types of jumps add different sizes to frags when we're
638 figuring out what sort of jump to choose to reach a given label. */
641 #define UNCOND_JUMP 0
643 #define COND_JUMP86 2
648 #define SMALL16 (SMALL | CODE16)
650 #define BIG16 (BIG | CODE16)
654 #define INLINE __inline__
660 #define ENCODE_RELAX_STATE(type, size) \
661 ((relax_substateT) (((type) << 2) | (size)))
662 #define TYPE_FROM_RELAX_STATE(s) \
664 #define DISP_SIZE_FROM_RELAX_STATE(s) \
665 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
667 /* This table is used by relax_frag to promote short jumps to long
668 ones where necessary. SMALL (short) jumps may be promoted to BIG
669 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
670 don't allow a short jump in a 32 bit code segment to be promoted to
671 a 16 bit offset jump because it's slower (requires data size
672 prefix), and doesn't work, unless the destination is in the bottom
673 64k of the code segment (The top 16 bits of eip are zeroed). */
675 const relax_typeS md_relax_table
[] =
678 1) most positive reach of this state,
679 2) most negative reach of this state,
680 3) how many bytes this mode will have in the variable part of the frag
681 4) which index into the table to try if we can't fit into this one. */
683 /* UNCOND_JUMP states. */
684 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
685 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
686 /* dword jmp adds 4 bytes to frag:
687 0 extra opcode bytes, 4 displacement bytes. */
689 /* word jmp adds 2 byte2 to frag:
690 0 extra opcode bytes, 2 displacement bytes. */
693 /* COND_JUMP states. */
694 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
696 /* dword conditionals adds 5 bytes to frag:
697 1 extra opcode byte, 4 displacement bytes. */
699 /* word conditionals add 3 bytes to frag:
700 1 extra opcode byte, 2 displacement bytes. */
703 /* COND_JUMP86 states. */
704 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
705 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
706 /* dword conditionals adds 5 bytes to frag:
707 1 extra opcode byte, 4 displacement bytes. */
709 /* word conditionals add 4 bytes to frag:
710 1 displacement byte and a 3 byte long branch insn. */
714 static const arch_entry cpu_arch
[] =
716 /* Do not replace the first two entries - i386_target_format()
717 relies on them being there in this order. */
718 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
719 CPU_GENERIC32_FLAGS
, 0, 0 },
720 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
721 CPU_GENERIC64_FLAGS
, 0, 0 },
722 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
723 CPU_NONE_FLAGS
, 0, 0 },
724 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
725 CPU_I186_FLAGS
, 0, 0 },
726 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
727 CPU_I286_FLAGS
, 0, 0 },
728 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
729 CPU_I386_FLAGS
, 0, 0 },
730 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
731 CPU_I486_FLAGS
, 0, 0 },
732 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
733 CPU_I586_FLAGS
, 0, 0 },
734 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
735 CPU_I686_FLAGS
, 0, 0 },
736 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
737 CPU_I586_FLAGS
, 0, 0 },
738 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
739 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
740 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
741 CPU_P2_FLAGS
, 0, 0 },
742 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
743 CPU_P3_FLAGS
, 0, 0 },
744 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
745 CPU_P4_FLAGS
, 0, 0 },
746 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
747 CPU_CORE_FLAGS
, 0, 0 },
748 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
749 CPU_NOCONA_FLAGS
, 0, 0 },
750 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
751 CPU_CORE_FLAGS
, 1, 0 },
752 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
753 CPU_CORE_FLAGS
, 0, 0 },
754 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
755 CPU_CORE2_FLAGS
, 1, 0 },
756 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
757 CPU_CORE2_FLAGS
, 0, 0 },
758 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
759 CPU_COREI7_FLAGS
, 0, 0 },
760 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
761 CPU_L1OM_FLAGS
, 0, 0 },
762 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
763 CPU_K1OM_FLAGS
, 0, 0 },
764 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
765 CPU_K6_FLAGS
, 0, 0 },
766 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
767 CPU_K6_2_FLAGS
, 0, 0 },
768 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
769 CPU_ATHLON_FLAGS
, 0, 0 },
770 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
771 CPU_K8_FLAGS
, 1, 0 },
772 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
773 CPU_K8_FLAGS
, 0, 0 },
774 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
775 CPU_K8_FLAGS
, 0, 0 },
776 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
777 CPU_AMDFAM10_FLAGS
, 0, 0 },
778 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
779 CPU_BDVER1_FLAGS
, 0, 0 },
780 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
781 CPU_BDVER2_FLAGS
, 0, 0 },
782 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
783 CPU_BDVER3_FLAGS
, 0, 0 },
784 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
785 CPU_BDVER4_FLAGS
, 0, 0 },
786 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
787 CPU_BTVER1_FLAGS
, 0, 0 },
788 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
789 CPU_BTVER2_FLAGS
, 0, 0 },
790 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
791 CPU_8087_FLAGS
, 0, 0 },
792 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
793 CPU_287_FLAGS
, 0, 0 },
794 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
795 CPU_387_FLAGS
, 0, 0 },
796 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
797 CPU_ANY87_FLAGS
, 0, 1 },
798 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
799 CPU_MMX_FLAGS
, 0, 0 },
800 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
801 CPU_3DNOWA_FLAGS
, 0, 1 },
802 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
803 CPU_SSE_FLAGS
, 0, 0 },
804 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
805 CPU_SSE2_FLAGS
, 0, 0 },
806 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
807 CPU_SSE3_FLAGS
, 0, 0 },
808 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
809 CPU_SSSE3_FLAGS
, 0, 0 },
810 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
811 CPU_SSE4_1_FLAGS
, 0, 0 },
812 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
813 CPU_SSE4_2_FLAGS
, 0, 0 },
814 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
815 CPU_SSE4_2_FLAGS
, 0, 0 },
816 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
817 CPU_ANY_SSE_FLAGS
, 0, 1 },
818 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
819 CPU_AVX_FLAGS
, 0, 0 },
820 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
821 CPU_AVX2_FLAGS
, 0, 0 },
822 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
823 CPU_AVX512F_FLAGS
, 0, 0 },
824 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
825 CPU_AVX512CD_FLAGS
, 0, 0 },
826 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
827 CPU_AVX512ER_FLAGS
, 0, 0 },
828 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
829 CPU_AVX512PF_FLAGS
, 0, 0 },
830 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
831 CPU_AVX512DQ_FLAGS
, 0, 0 },
832 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
833 CPU_AVX512BW_FLAGS
, 0, 0 },
834 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
835 CPU_AVX512VL_FLAGS
, 0, 0 },
836 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
837 CPU_ANY_AVX_FLAGS
, 0, 1 },
838 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
839 CPU_VMX_FLAGS
, 0, 0 },
840 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
841 CPU_VMFUNC_FLAGS
, 0, 0 },
842 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
843 CPU_SMX_FLAGS
, 0, 0 },
844 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
845 CPU_XSAVE_FLAGS
, 0, 0 },
846 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
847 CPU_XSAVEOPT_FLAGS
, 0, 0 },
848 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
849 CPU_XSAVEC_FLAGS
, 0, 0 },
850 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
851 CPU_XSAVES_FLAGS
, 0, 0 },
852 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
853 CPU_AES_FLAGS
, 0, 0 },
854 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
855 CPU_PCLMUL_FLAGS
, 0, 0 },
856 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
857 CPU_PCLMUL_FLAGS
, 1, 0 },
858 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
859 CPU_FSGSBASE_FLAGS
, 0, 0 },
860 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
861 CPU_RDRND_FLAGS
, 0, 0 },
862 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
863 CPU_F16C_FLAGS
, 0, 0 },
864 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
865 CPU_BMI2_FLAGS
, 0, 0 },
866 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
867 CPU_FMA_FLAGS
, 0, 0 },
868 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
869 CPU_FMA4_FLAGS
, 0, 0 },
870 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
871 CPU_XOP_FLAGS
, 0, 0 },
872 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
873 CPU_LWP_FLAGS
, 0, 0 },
874 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
875 CPU_MOVBE_FLAGS
, 0, 0 },
876 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
877 CPU_CX16_FLAGS
, 0, 0 },
878 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
879 CPU_EPT_FLAGS
, 0, 0 },
880 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
881 CPU_LZCNT_FLAGS
, 0, 0 },
882 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
883 CPU_HLE_FLAGS
, 0, 0 },
884 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
885 CPU_RTM_FLAGS
, 0, 0 },
886 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
887 CPU_INVPCID_FLAGS
, 0, 0 },
888 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
889 CPU_CLFLUSH_FLAGS
, 0, 0 },
890 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
891 CPU_NOP_FLAGS
, 0, 0 },
892 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
893 CPU_SYSCALL_FLAGS
, 0, 0 },
894 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
895 CPU_RDTSCP_FLAGS
, 0, 0 },
896 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
897 CPU_3DNOW_FLAGS
, 0, 0 },
898 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
899 CPU_3DNOWA_FLAGS
, 0, 0 },
900 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
901 CPU_PADLOCK_FLAGS
, 0, 0 },
902 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
903 CPU_SVME_FLAGS
, 1, 0 },
904 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
905 CPU_SVME_FLAGS
, 0, 0 },
906 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
907 CPU_SSE4A_FLAGS
, 0, 0 },
908 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
909 CPU_ABM_FLAGS
, 0, 0 },
910 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
911 CPU_BMI_FLAGS
, 0, 0 },
912 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
913 CPU_TBM_FLAGS
, 0, 0 },
914 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
915 CPU_ADX_FLAGS
, 0, 0 },
916 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
917 CPU_RDSEED_FLAGS
, 0, 0 },
918 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
919 CPU_PRFCHW_FLAGS
, 0, 0 },
920 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
921 CPU_SMAP_FLAGS
, 0, 0 },
922 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
923 CPU_MPX_FLAGS
, 0, 0 },
924 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
925 CPU_SHA_FLAGS
, 0, 0 },
926 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
927 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
928 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
929 CPU_PREFETCHWT1_FLAGS
, 0, 0 },
930 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
931 CPU_SE1_FLAGS
, 0, 0 },
932 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
933 CPU_CLWB_FLAGS
, 0, 0 },
934 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
935 CPU_PCOMMIT_FLAGS
, 0, 0 },
936 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
937 CPU_AVX512IFMA_FLAGS
, 0, 0 },
941 /* Like s_lcomm_internal in gas/read.c but the alignment string
942 is allowed to be optional. */
945 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
952 && *input_line_pointer
== ',')
954 align
= parse_align (needs_align
- 1);
956 if (align
== (addressT
) -1)
971 bss_alloc (symbolP
, size
, align
);
976 pe_lcomm (int needs_align
)
978 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
982 const pseudo_typeS md_pseudo_table
[] =
984 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
985 {"align", s_align_bytes
, 0},
987 {"align", s_align_ptwo
, 0},
989 {"arch", set_cpu_arch
, 0},
993 {"lcomm", pe_lcomm
, 1},
995 {"ffloat", float_cons
, 'f'},
996 {"dfloat", float_cons
, 'd'},
997 {"tfloat", float_cons
, 'x'},
999 {"slong", signed_cons
, 4},
1000 {"noopt", s_ignore
, 0},
1001 {"optim", s_ignore
, 0},
1002 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1003 {"code16", set_code_flag
, CODE_16BIT
},
1004 {"code32", set_code_flag
, CODE_32BIT
},
1005 {"code64", set_code_flag
, CODE_64BIT
},
1006 {"intel_syntax", set_intel_syntax
, 1},
1007 {"att_syntax", set_intel_syntax
, 0},
1008 {"intel_mnemonic", set_intel_mnemonic
, 1},
1009 {"att_mnemonic", set_intel_mnemonic
, 0},
1010 {"allow_index_reg", set_allow_index_reg
, 1},
1011 {"disallow_index_reg", set_allow_index_reg
, 0},
1012 {"sse_check", set_check
, 0},
1013 {"operand_check", set_check
, 1},
1014 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1015 {"largecomm", handle_large_common
, 0},
1017 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1018 {"loc", dwarf2_directive_loc
, 0},
1019 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1022 {"secrel32", pe_directive_secrel
, 0},
1027 /* For interface with expression (). */
1028 extern char *input_line_pointer
;
1030 /* Hash table for instruction mnemonic lookup. */
1031 static struct hash_control
*op_hash
;
1033 /* Hash table for register lookup. */
1034 static struct hash_control
*reg_hash
;
1037 i386_align_code (fragS
*fragP
, int count
)
1039 /* Various efficient no-op patterns for aligning code labels.
1040 Note: Don't try to assemble the instructions in the comments.
1041 0L and 0w are not legal. */
1042 static const char f32_1
[] =
1044 static const char f32_2
[] =
1045 {0x66,0x90}; /* xchg %ax,%ax */
1046 static const char f32_3
[] =
1047 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1048 static const char f32_4
[] =
1049 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1050 static const char f32_5
[] =
1052 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1053 static const char f32_6
[] =
1054 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1055 static const char f32_7
[] =
1056 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1057 static const char f32_8
[] =
1059 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1060 static const char f32_9
[] =
1061 {0x89,0xf6, /* movl %esi,%esi */
1062 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1063 static const char f32_10
[] =
1064 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1065 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1066 static const char f32_11
[] =
1067 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1068 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1069 static const char f32_12
[] =
1070 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1071 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1072 static const char f32_13
[] =
1073 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1074 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1075 static const char f32_14
[] =
1076 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1077 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1078 static const char f16_3
[] =
1079 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1080 static const char f16_4
[] =
1081 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1082 static const char f16_5
[] =
1084 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1085 static const char f16_6
[] =
1086 {0x89,0xf6, /* mov %si,%si */
1087 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1088 static const char f16_7
[] =
1089 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1090 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1091 static const char f16_8
[] =
1092 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1093 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1094 static const char jump_31
[] =
1095 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1096 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1097 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1098 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1099 static const char *const f32_patt
[] = {
1100 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1101 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1103 static const char *const f16_patt
[] = {
1104 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1106 /* nopl (%[re]ax) */
1107 static const char alt_3
[] =
1109 /* nopl 0(%[re]ax) */
1110 static const char alt_4
[] =
1111 {0x0f,0x1f,0x40,0x00};
1112 /* nopl 0(%[re]ax,%[re]ax,1) */
1113 static const char alt_5
[] =
1114 {0x0f,0x1f,0x44,0x00,0x00};
1115 /* nopw 0(%[re]ax,%[re]ax,1) */
1116 static const char alt_6
[] =
1117 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1118 /* nopl 0L(%[re]ax) */
1119 static const char alt_7
[] =
1120 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1121 /* nopl 0L(%[re]ax,%[re]ax,1) */
1122 static const char alt_8
[] =
1123 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1124 /* nopw 0L(%[re]ax,%[re]ax,1) */
1125 static const char alt_9
[] =
1126 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1127 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1128 static const char alt_10
[] =
1129 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1131 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1132 static const char alt_long_11
[] =
1134 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1137 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1138 static const char alt_long_12
[] =
1141 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1145 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1146 static const char alt_long_13
[] =
1150 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1155 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1156 static const char alt_long_14
[] =
1161 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1167 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1168 static const char alt_long_15
[] =
1174 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1175 /* nopl 0(%[re]ax,%[re]ax,1)
1176 nopw 0(%[re]ax,%[re]ax,1) */
1177 static const char alt_short_11
[] =
1178 {0x0f,0x1f,0x44,0x00,0x00,
1179 0x66,0x0f,0x1f,0x44,0x00,0x00};
1180 /* nopw 0(%[re]ax,%[re]ax,1)
1181 nopw 0(%[re]ax,%[re]ax,1) */
1182 static const char alt_short_12
[] =
1183 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1184 0x66,0x0f,0x1f,0x44,0x00,0x00};
1185 /* nopw 0(%[re]ax,%[re]ax,1)
1187 static const char alt_short_13
[] =
1188 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1189 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1192 static const char alt_short_14
[] =
1193 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1194 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1196 nopl 0L(%[re]ax,%[re]ax,1) */
1197 static const char alt_short_15
[] =
1198 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1199 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1200 static const char *const alt_short_patt
[] = {
1201 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1202 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1203 alt_short_14
, alt_short_15
1205 static const char *const alt_long_patt
[] = {
1206 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1207 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1208 alt_long_14
, alt_long_15
1211 /* Only align for at least a positive non-zero boundary. */
1212 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1215 /* We need to decide which NOP sequence to use for 32bit and
1216 64bit. When -mtune= is used:
1218 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1219 PROCESSOR_GENERIC32, f32_patt will be used.
1220 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1221 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1222 PROCESSOR_GENERIC64, alt_long_patt will be used.
1223 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1224 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1227 When -mtune= isn't used, alt_long_patt will be used if
1228 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1231 When -march= or .arch is used, we can't use anything beyond
1232 cpu_arch_isa_flags. */
1234 if (flag_code
== CODE_16BIT
)
1238 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1240 /* Adjust jump offset. */
1241 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1244 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1245 f16_patt
[count
- 1], count
);
1249 const char *const *patt
= NULL
;
1251 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1253 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1254 switch (cpu_arch_tune
)
1256 case PROCESSOR_UNKNOWN
:
1257 /* We use cpu_arch_isa_flags to check if we SHOULD
1258 optimize with nops. */
1259 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1260 patt
= alt_long_patt
;
1264 case PROCESSOR_PENTIUM4
:
1265 case PROCESSOR_NOCONA
:
1266 case PROCESSOR_CORE
:
1267 case PROCESSOR_CORE2
:
1268 case PROCESSOR_COREI7
:
1269 case PROCESSOR_L1OM
:
1270 case PROCESSOR_K1OM
:
1271 case PROCESSOR_GENERIC64
:
1272 patt
= alt_long_patt
;
1275 case PROCESSOR_ATHLON
:
1277 case PROCESSOR_AMDFAM10
:
1280 patt
= alt_short_patt
;
1282 case PROCESSOR_I386
:
1283 case PROCESSOR_I486
:
1284 case PROCESSOR_PENTIUM
:
1285 case PROCESSOR_PENTIUMPRO
:
1286 case PROCESSOR_GENERIC32
:
1293 switch (fragP
->tc_frag_data
.tune
)
1295 case PROCESSOR_UNKNOWN
:
1296 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1297 PROCESSOR_UNKNOWN. */
1301 case PROCESSOR_I386
:
1302 case PROCESSOR_I486
:
1303 case PROCESSOR_PENTIUM
:
1305 case PROCESSOR_ATHLON
:
1307 case PROCESSOR_AMDFAM10
:
1310 case PROCESSOR_GENERIC32
:
1311 /* We use cpu_arch_isa_flags to check if we CAN optimize
1313 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1314 patt
= alt_short_patt
;
1318 case PROCESSOR_PENTIUMPRO
:
1319 case PROCESSOR_PENTIUM4
:
1320 case PROCESSOR_NOCONA
:
1321 case PROCESSOR_CORE
:
1322 case PROCESSOR_CORE2
:
1323 case PROCESSOR_COREI7
:
1324 case PROCESSOR_L1OM
:
1325 case PROCESSOR_K1OM
:
1326 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1327 patt
= alt_long_patt
;
1331 case PROCESSOR_GENERIC64
:
1332 patt
= alt_long_patt
;
1337 if (patt
== f32_patt
)
1339 /* If the padding is less than 15 bytes, we use the normal
1340 ones. Otherwise, we use a jump instruction and adjust
1344 /* For 64bit, the limit is 3 bytes. */
1345 if (flag_code
== CODE_64BIT
1346 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1351 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1352 patt
[count
- 1], count
);
1355 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1357 /* Adjust jump offset. */
1358 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1363 /* Maximum length of an instruction is 15 byte. If the
1364 padding is greater than 15 bytes and we don't use jump,
1365 we have to break it into smaller pieces. */
1366 int padding
= count
;
1367 while (padding
> 15)
1370 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1375 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1376 patt
[padding
- 1], padding
);
1379 fragP
->fr_var
= count
;
1383 operand_type_all_zero (const union i386_operand_type
*x
)
1385 switch (ARRAY_SIZE(x
->array
))
1394 return !x
->array
[0];
1401 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1403 switch (ARRAY_SIZE(x
->array
))
1418 operand_type_equal (const union i386_operand_type
*x
,
1419 const union i386_operand_type
*y
)
1421 switch (ARRAY_SIZE(x
->array
))
1424 if (x
->array
[2] != y
->array
[2])
1427 if (x
->array
[1] != y
->array
[1])
1430 return x
->array
[0] == y
->array
[0];
1438 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1440 switch (ARRAY_SIZE(x
->array
))
1449 return !x
->array
[0];
1456 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1458 switch (ARRAY_SIZE(x
->array
))
1473 cpu_flags_equal (const union i386_cpu_flags
*x
,
1474 const union i386_cpu_flags
*y
)
1476 switch (ARRAY_SIZE(x
->array
))
1479 if (x
->array
[2] != y
->array
[2])
1482 if (x
->array
[1] != y
->array
[1])
1485 return x
->array
[0] == y
->array
[0];
1493 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1495 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1496 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1499 static INLINE i386_cpu_flags
1500 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1502 switch (ARRAY_SIZE (x
.array
))
1505 x
.array
[2] &= y
.array
[2];
1507 x
.array
[1] &= y
.array
[1];
1509 x
.array
[0] &= y
.array
[0];
1517 static INLINE i386_cpu_flags
1518 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1520 switch (ARRAY_SIZE (x
.array
))
1523 x
.array
[2] |= y
.array
[2];
1525 x
.array
[1] |= y
.array
[1];
1527 x
.array
[0] |= y
.array
[0];
1535 static INLINE i386_cpu_flags
1536 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1538 switch (ARRAY_SIZE (x
.array
))
1541 x
.array
[2] &= ~y
.array
[2];
1543 x
.array
[1] &= ~y
.array
[1];
1545 x
.array
[0] &= ~y
.array
[0];
1553 #define CPU_FLAGS_ARCH_MATCH 0x1
1554 #define CPU_FLAGS_64BIT_MATCH 0x2
1555 #define CPU_FLAGS_AES_MATCH 0x4
1556 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1557 #define CPU_FLAGS_AVX_MATCH 0x10
1559 #define CPU_FLAGS_32BIT_MATCH \
1560 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1561 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1562 #define CPU_FLAGS_PERFECT_MATCH \
1563 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1565 /* Return CPU flags match bits. */
1568 cpu_flags_match (const insn_template
*t
)
1570 i386_cpu_flags x
= t
->cpu_flags
;
1571 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1573 x
.bitfield
.cpu64
= 0;
1574 x
.bitfield
.cpuno64
= 0;
1576 if (cpu_flags_all_zero (&x
))
1578 /* This instruction is available on all archs. */
1579 match
|= CPU_FLAGS_32BIT_MATCH
;
1583 /* This instruction is available only on some archs. */
1584 i386_cpu_flags cpu
= cpu_arch_flags
;
1586 cpu
.bitfield
.cpu64
= 0;
1587 cpu
.bitfield
.cpuno64
= 0;
1588 cpu
= cpu_flags_and (x
, cpu
);
1589 if (!cpu_flags_all_zero (&cpu
))
1591 if (x
.bitfield
.cpuavx
)
1593 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1594 if (cpu
.bitfield
.cpuavx
)
1596 /* Check SSE2AVX. */
1597 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1599 match
|= (CPU_FLAGS_ARCH_MATCH
1600 | CPU_FLAGS_AVX_MATCH
);
1602 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1603 match
|= CPU_FLAGS_AES_MATCH
;
1605 if (!x
.bitfield
.cpupclmul
1606 || cpu
.bitfield
.cpupclmul
)
1607 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1611 match
|= CPU_FLAGS_ARCH_MATCH
;
1614 match
|= CPU_FLAGS_32BIT_MATCH
;
1620 static INLINE i386_operand_type
1621 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1623 switch (ARRAY_SIZE (x
.array
))
1626 x
.array
[2] &= y
.array
[2];
1628 x
.array
[1] &= y
.array
[1];
1630 x
.array
[0] &= y
.array
[0];
1638 static INLINE i386_operand_type
1639 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1641 switch (ARRAY_SIZE (x
.array
))
1644 x
.array
[2] |= y
.array
[2];
1646 x
.array
[1] |= y
.array
[1];
1648 x
.array
[0] |= y
.array
[0];
1656 static INLINE i386_operand_type
1657 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1659 switch (ARRAY_SIZE (x
.array
))
1662 x
.array
[2] ^= y
.array
[2];
1664 x
.array
[1] ^= y
.array
[1];
1666 x
.array
[0] ^= y
.array
[0];
1674 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1675 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1676 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1677 static const i386_operand_type inoutportreg
1678 = OPERAND_TYPE_INOUTPORTREG
;
1679 static const i386_operand_type reg16_inoutportreg
1680 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1681 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1682 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1683 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1684 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1685 static const i386_operand_type anydisp
1686 = OPERAND_TYPE_ANYDISP
;
1687 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1688 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1689 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1690 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1691 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1692 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1693 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1694 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1695 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1696 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1697 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1698 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1699 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1700 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1711 operand_type_check (i386_operand_type t
, enum operand_type c
)
1716 return (t
.bitfield
.reg8
1719 || t
.bitfield
.reg64
);
1722 return (t
.bitfield
.imm8
1726 || t
.bitfield
.imm32s
1727 || t
.bitfield
.imm64
);
1730 return (t
.bitfield
.disp8
1731 || t
.bitfield
.disp16
1732 || t
.bitfield
.disp32
1733 || t
.bitfield
.disp32s
1734 || t
.bitfield
.disp64
);
1737 return (t
.bitfield
.disp8
1738 || t
.bitfield
.disp16
1739 || t
.bitfield
.disp32
1740 || t
.bitfield
.disp32s
1741 || t
.bitfield
.disp64
1742 || t
.bitfield
.baseindex
);
1751 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1752 operand J for instruction template T. */
1755 match_reg_size (const insn_template
*t
, unsigned int j
)
1757 return !((i
.types
[j
].bitfield
.byte
1758 && !t
->operand_types
[j
].bitfield
.byte
)
1759 || (i
.types
[j
].bitfield
.word
1760 && !t
->operand_types
[j
].bitfield
.word
)
1761 || (i
.types
[j
].bitfield
.dword
1762 && !t
->operand_types
[j
].bitfield
.dword
)
1763 || (i
.types
[j
].bitfield
.qword
1764 && !t
->operand_types
[j
].bitfield
.qword
));
1767 /* Return 1 if there is no conflict in any size on operand J for
1768 instruction template T. */
1771 match_mem_size (const insn_template
*t
, unsigned int j
)
1773 return (match_reg_size (t
, j
)
1774 && !((i
.types
[j
].bitfield
.unspecified
1775 && !t
->operand_types
[j
].bitfield
.unspecified
)
1776 || (i
.types
[j
].bitfield
.fword
1777 && !t
->operand_types
[j
].bitfield
.fword
)
1778 || (i
.types
[j
].bitfield
.tbyte
1779 && !t
->operand_types
[j
].bitfield
.tbyte
)
1780 || (i
.types
[j
].bitfield
.xmmword
1781 && !t
->operand_types
[j
].bitfield
.xmmword
)
1782 || (i
.types
[j
].bitfield
.ymmword
1783 && !t
->operand_types
[j
].bitfield
.ymmword
)
1784 || (i
.types
[j
].bitfield
.zmmword
1785 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1788 /* Return 1 if there is no size conflict on any operands for
1789 instruction template T. */
1792 operand_size_match (const insn_template
*t
)
1797 /* Don't check jump instructions. */
1798 if (t
->opcode_modifier
.jump
1799 || t
->opcode_modifier
.jumpbyte
1800 || t
->opcode_modifier
.jumpdword
1801 || t
->opcode_modifier
.jumpintersegment
)
1804 /* Check memory and accumulator operand size. */
1805 for (j
= 0; j
< i
.operands
; j
++)
1807 if (t
->operand_types
[j
].bitfield
.anysize
)
1810 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1816 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1825 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1828 i
.error
= operand_size_mismatch
;
1832 /* Check reverse. */
1833 gas_assert (i
.operands
== 2);
1836 for (j
= 0; j
< 2; j
++)
1838 if (t
->operand_types
[j
].bitfield
.acc
1839 && !match_reg_size (t
, j
? 0 : 1))
1842 if (i
.types
[j
].bitfield
.mem
1843 && !match_mem_size (t
, j
? 0 : 1))
1851 operand_type_match (i386_operand_type overlap
,
1852 i386_operand_type given
)
1854 i386_operand_type temp
= overlap
;
1856 temp
.bitfield
.jumpabsolute
= 0;
1857 temp
.bitfield
.unspecified
= 0;
1858 temp
.bitfield
.byte
= 0;
1859 temp
.bitfield
.word
= 0;
1860 temp
.bitfield
.dword
= 0;
1861 temp
.bitfield
.fword
= 0;
1862 temp
.bitfield
.qword
= 0;
1863 temp
.bitfield
.tbyte
= 0;
1864 temp
.bitfield
.xmmword
= 0;
1865 temp
.bitfield
.ymmword
= 0;
1866 temp
.bitfield
.zmmword
= 0;
1867 if (operand_type_all_zero (&temp
))
1870 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1871 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1875 i
.error
= operand_type_mismatch
;
1879 /* If given types g0 and g1 are registers they must be of the same type
1880 unless the expected operand type register overlap is null.
1881 Note that Acc in a template matches every size of reg. */
1884 operand_type_register_match (i386_operand_type m0
,
1885 i386_operand_type g0
,
1886 i386_operand_type t0
,
1887 i386_operand_type m1
,
1888 i386_operand_type g1
,
1889 i386_operand_type t1
)
1891 if (!operand_type_check (g0
, reg
))
1894 if (!operand_type_check (g1
, reg
))
1897 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1898 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1899 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1900 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1903 if (m0
.bitfield
.acc
)
1905 t0
.bitfield
.reg8
= 1;
1906 t0
.bitfield
.reg16
= 1;
1907 t0
.bitfield
.reg32
= 1;
1908 t0
.bitfield
.reg64
= 1;
1911 if (m1
.bitfield
.acc
)
1913 t1
.bitfield
.reg8
= 1;
1914 t1
.bitfield
.reg16
= 1;
1915 t1
.bitfield
.reg32
= 1;
1916 t1
.bitfield
.reg64
= 1;
1919 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1920 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1921 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1922 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1925 i
.error
= register_type_mismatch
;
1930 static INLINE
unsigned int
1931 register_number (const reg_entry
*r
)
1933 unsigned int nr
= r
->reg_num
;
1935 if (r
->reg_flags
& RegRex
)
1941 static INLINE
unsigned int
1942 mode_from_disp_size (i386_operand_type t
)
1944 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1946 else if (t
.bitfield
.disp16
1947 || t
.bitfield
.disp32
1948 || t
.bitfield
.disp32s
)
1955 fits_in_signed_byte (addressT num
)
1957 return num
+ 0x80 <= 0xff;
1961 fits_in_unsigned_byte (addressT num
)
1967 fits_in_unsigned_word (addressT num
)
1969 return num
<= 0xffff;
1973 fits_in_signed_word (addressT num
)
1975 return num
+ 0x8000 <= 0xffff;
1979 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1984 return num
+ 0x80000000 <= 0xffffffff;
1986 } /* fits_in_signed_long() */
1989 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
1994 return num
<= 0xffffffff;
1996 } /* fits_in_unsigned_long() */
1999 fits_in_vec_disp8 (offsetT num
)
2001 int shift
= i
.memshift
;
2007 mask
= (1 << shift
) - 1;
2009 /* Return 0 if NUM isn't properly aligned. */
2013 /* Check if NUM will fit in 8bit after shift. */
2014 return fits_in_signed_byte (num
>> shift
);
2018 fits_in_imm4 (offsetT num
)
2020 return (num
& 0xf) == num
;
2023 static i386_operand_type
2024 smallest_imm_type (offsetT num
)
2026 i386_operand_type t
;
2028 operand_type_set (&t
, 0);
2029 t
.bitfield
.imm64
= 1;
2031 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2033 /* This code is disabled on the 486 because all the Imm1 forms
2034 in the opcode table are slower on the i486. They're the
2035 versions with the implicitly specified single-position
2036 displacement, which has another syntax if you really want to
2038 t
.bitfield
.imm1
= 1;
2039 t
.bitfield
.imm8
= 1;
2040 t
.bitfield
.imm8s
= 1;
2041 t
.bitfield
.imm16
= 1;
2042 t
.bitfield
.imm32
= 1;
2043 t
.bitfield
.imm32s
= 1;
2045 else if (fits_in_signed_byte (num
))
2047 t
.bitfield
.imm8
= 1;
2048 t
.bitfield
.imm8s
= 1;
2049 t
.bitfield
.imm16
= 1;
2050 t
.bitfield
.imm32
= 1;
2051 t
.bitfield
.imm32s
= 1;
2053 else if (fits_in_unsigned_byte (num
))
2055 t
.bitfield
.imm8
= 1;
2056 t
.bitfield
.imm16
= 1;
2057 t
.bitfield
.imm32
= 1;
2058 t
.bitfield
.imm32s
= 1;
2060 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2062 t
.bitfield
.imm16
= 1;
2063 t
.bitfield
.imm32
= 1;
2064 t
.bitfield
.imm32s
= 1;
2066 else if (fits_in_signed_long (num
))
2068 t
.bitfield
.imm32
= 1;
2069 t
.bitfield
.imm32s
= 1;
2071 else if (fits_in_unsigned_long (num
))
2072 t
.bitfield
.imm32
= 1;
2078 offset_in_range (offsetT val
, int size
)
2084 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2085 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2086 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2088 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2094 /* If BFD64, sign extend val for 32bit address mode. */
2095 if (flag_code
!= CODE_64BIT
2096 || i
.prefix
[ADDR_PREFIX
])
2097 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2098 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2101 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2103 char buf1
[40], buf2
[40];
2105 sprint_value (buf1
, val
);
2106 sprint_value (buf2
, val
& mask
);
2107 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2121 a. PREFIX_EXIST if attempting to add a prefix where one from the
2122 same class already exists.
2123 b. PREFIX_LOCK if lock prefix is added.
2124 c. PREFIX_REP if rep/repne prefix is added.
2125 d. PREFIX_OTHER if other prefix is added.
2128 static enum PREFIX_GROUP
2129 add_prefix (unsigned int prefix
)
2131 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2134 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2135 && flag_code
== CODE_64BIT
)
2137 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2138 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2139 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2150 case CS_PREFIX_OPCODE
:
2151 case DS_PREFIX_OPCODE
:
2152 case ES_PREFIX_OPCODE
:
2153 case FS_PREFIX_OPCODE
:
2154 case GS_PREFIX_OPCODE
:
2155 case SS_PREFIX_OPCODE
:
2159 case REPNE_PREFIX_OPCODE
:
2160 case REPE_PREFIX_OPCODE
:
2165 case LOCK_PREFIX_OPCODE
:
2174 case ADDR_PREFIX_OPCODE
:
2178 case DATA_PREFIX_OPCODE
:
2182 if (i
.prefix
[q
] != 0)
2190 i
.prefix
[q
] |= prefix
;
2193 as_bad (_("same type of prefix used twice"));
2199 update_code_flag (int value
, int check
)
2201 PRINTF_LIKE ((*as_error
));
2203 flag_code
= (enum flag_code
) value
;
2204 if (flag_code
== CODE_64BIT
)
2206 cpu_arch_flags
.bitfield
.cpu64
= 1;
2207 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2211 cpu_arch_flags
.bitfield
.cpu64
= 0;
2212 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2214 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2217 as_error
= as_fatal
;
2220 (*as_error
) (_("64bit mode not supported on `%s'."),
2221 cpu_arch_name
? cpu_arch_name
: default_arch
);
2223 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2226 as_error
= as_fatal
;
2229 (*as_error
) (_("32bit mode not supported on `%s'."),
2230 cpu_arch_name
? cpu_arch_name
: default_arch
);
2232 stackop_size
= '\0';
2236 set_code_flag (int value
)
2238 update_code_flag (value
, 0);
2242 set_16bit_gcc_code_flag (int new_code_flag
)
2244 flag_code
= (enum flag_code
) new_code_flag
;
2245 if (flag_code
!= CODE_16BIT
)
2247 cpu_arch_flags
.bitfield
.cpu64
= 0;
2248 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2249 stackop_size
= LONG_MNEM_SUFFIX
;
2253 set_intel_syntax (int syntax_flag
)
2255 /* Find out if register prefixing is specified. */
2256 int ask_naked_reg
= 0;
2259 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2261 char *string
= input_line_pointer
;
2262 int e
= get_symbol_end ();
2264 if (strcmp (string
, "prefix") == 0)
2266 else if (strcmp (string
, "noprefix") == 0)
2269 as_bad (_("bad argument to syntax directive."));
2270 *input_line_pointer
= e
;
2272 demand_empty_rest_of_line ();
2274 intel_syntax
= syntax_flag
;
2276 if (ask_naked_reg
== 0)
2277 allow_naked_reg
= (intel_syntax
2278 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2280 allow_naked_reg
= (ask_naked_reg
< 0);
2282 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2284 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2285 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2286 register_prefix
= allow_naked_reg
? "" : "%";
2290 set_intel_mnemonic (int mnemonic_flag
)
2292 intel_mnemonic
= mnemonic_flag
;
2296 set_allow_index_reg (int flag
)
2298 allow_index_reg
= flag
;
2302 set_check (int what
)
2304 enum check_kind
*kind
;
2309 kind
= &operand_check
;
2320 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2322 char *string
= input_line_pointer
;
2323 int e
= get_symbol_end ();
2325 if (strcmp (string
, "none") == 0)
2327 else if (strcmp (string
, "warning") == 0)
2328 *kind
= check_warning
;
2329 else if (strcmp (string
, "error") == 0)
2330 *kind
= check_error
;
2332 as_bad (_("bad argument to %s_check directive."), str
);
2333 *input_line_pointer
= e
;
2336 as_bad (_("missing argument for %s_check directive"), str
);
2338 demand_empty_rest_of_line ();
2342 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2343 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2345 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2346 static const char *arch
;
2348 /* Intel LIOM is only supported on ELF. */
2354 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2355 use default_arch. */
2356 arch
= cpu_arch_name
;
2358 arch
= default_arch
;
2361 /* If we are targeting Intel L1OM, we must enable it. */
2362 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2363 || new_flag
.bitfield
.cpul1om
)
2366 /* If we are targeting Intel K1OM, we must enable it. */
2367 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2368 || new_flag
.bitfield
.cpuk1om
)
2371 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2376 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2380 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2382 char *string
= input_line_pointer
;
2383 int e
= get_symbol_end ();
2385 i386_cpu_flags flags
;
2387 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2389 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2391 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2395 cpu_arch_name
= cpu_arch
[j
].name
;
2396 cpu_sub_arch_name
= NULL
;
2397 cpu_arch_flags
= cpu_arch
[j
].flags
;
2398 if (flag_code
== CODE_64BIT
)
2400 cpu_arch_flags
.bitfield
.cpu64
= 1;
2401 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2405 cpu_arch_flags
.bitfield
.cpu64
= 0;
2406 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2408 cpu_arch_isa
= cpu_arch
[j
].type
;
2409 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2410 if (!cpu_arch_tune_set
)
2412 cpu_arch_tune
= cpu_arch_isa
;
2413 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2418 if (!cpu_arch
[j
].negated
)
2419 flags
= cpu_flags_or (cpu_arch_flags
,
2422 flags
= cpu_flags_and_not (cpu_arch_flags
,
2424 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2426 if (cpu_sub_arch_name
)
2428 char *name
= cpu_sub_arch_name
;
2429 cpu_sub_arch_name
= concat (name
,
2431 (const char *) NULL
);
2435 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2436 cpu_arch_flags
= flags
;
2437 cpu_arch_isa_flags
= flags
;
2439 *input_line_pointer
= e
;
2440 demand_empty_rest_of_line ();
2444 if (j
>= ARRAY_SIZE (cpu_arch
))
2445 as_bad (_("no such architecture: `%s'"), string
);
2447 *input_line_pointer
= e
;
2450 as_bad (_("missing cpu architecture"));
2452 no_cond_jump_promotion
= 0;
2453 if (*input_line_pointer
== ','
2454 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2456 char *string
= ++input_line_pointer
;
2457 int e
= get_symbol_end ();
2459 if (strcmp (string
, "nojumps") == 0)
2460 no_cond_jump_promotion
= 1;
2461 else if (strcmp (string
, "jumps") == 0)
2464 as_bad (_("no such architecture modifier: `%s'"), string
);
2466 *input_line_pointer
= e
;
2469 demand_empty_rest_of_line ();
2472 enum bfd_architecture
2475 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2477 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2478 || flag_code
!= CODE_64BIT
)
2479 as_fatal (_("Intel L1OM is 64bit ELF only"));
2480 return bfd_arch_l1om
;
2482 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2484 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2485 || flag_code
!= CODE_64BIT
)
2486 as_fatal (_("Intel K1OM is 64bit ELF only"));
2487 return bfd_arch_k1om
;
2490 return bfd_arch_i386
;
2496 if (!strncmp (default_arch
, "x86_64", 6))
2498 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2500 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2501 || default_arch
[6] != '\0')
2502 as_fatal (_("Intel L1OM is 64bit ELF only"));
2503 return bfd_mach_l1om
;
2505 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2507 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2508 || default_arch
[6] != '\0')
2509 as_fatal (_("Intel K1OM is 64bit ELF only"));
2510 return bfd_mach_k1om
;
2512 else if (default_arch
[6] == '\0')
2513 return bfd_mach_x86_64
;
2515 return bfd_mach_x64_32
;
2517 else if (!strcmp (default_arch
, "i386"))
2518 return bfd_mach_i386_i386
;
2520 as_fatal (_("unknown architecture"));
2526 const char *hash_err
;
2528 /* Initialize op_hash hash table. */
2529 op_hash
= hash_new ();
2532 const insn_template
*optab
;
2533 templates
*core_optab
;
2535 /* Setup for loop. */
2537 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2538 core_optab
->start
= optab
;
2543 if (optab
->name
== NULL
2544 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2546 /* different name --> ship out current template list;
2547 add to hash table; & begin anew. */
2548 core_optab
->end
= optab
;
2549 hash_err
= hash_insert (op_hash
,
2551 (void *) core_optab
);
2554 as_fatal (_("can't hash %s: %s"),
2558 if (optab
->name
== NULL
)
2560 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2561 core_optab
->start
= optab
;
2566 /* Initialize reg_hash hash table. */
2567 reg_hash
= hash_new ();
2569 const reg_entry
*regtab
;
2570 unsigned int regtab_size
= i386_regtab_size
;
2572 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2574 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2576 as_fatal (_("can't hash %s: %s"),
2582 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2587 for (c
= 0; c
< 256; c
++)
2592 mnemonic_chars
[c
] = c
;
2593 register_chars
[c
] = c
;
2594 operand_chars
[c
] = c
;
2596 else if (ISLOWER (c
))
2598 mnemonic_chars
[c
] = c
;
2599 register_chars
[c
] = c
;
2600 operand_chars
[c
] = c
;
2602 else if (ISUPPER (c
))
2604 mnemonic_chars
[c
] = TOLOWER (c
);
2605 register_chars
[c
] = mnemonic_chars
[c
];
2606 operand_chars
[c
] = c
;
2608 else if (c
== '{' || c
== '}')
2609 operand_chars
[c
] = c
;
2611 if (ISALPHA (c
) || ISDIGIT (c
))
2612 identifier_chars
[c
] = c
;
2615 identifier_chars
[c
] = c
;
2616 operand_chars
[c
] = c
;
2621 identifier_chars
['@'] = '@';
2624 identifier_chars
['?'] = '?';
2625 operand_chars
['?'] = '?';
2627 digit_chars
['-'] = '-';
2628 mnemonic_chars
['_'] = '_';
2629 mnemonic_chars
['-'] = '-';
2630 mnemonic_chars
['.'] = '.';
2631 identifier_chars
['_'] = '_';
2632 identifier_chars
['.'] = '.';
2634 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2635 operand_chars
[(unsigned char) *p
] = *p
;
2638 if (flag_code
== CODE_64BIT
)
2640 #if defined (OBJ_COFF) && defined (TE_PE)
2641 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2644 x86_dwarf2_return_column
= 16;
2646 x86_cie_data_alignment
= -8;
2650 x86_dwarf2_return_column
= 8;
2651 x86_cie_data_alignment
= -4;
2656 i386_print_statistics (FILE *file
)
2658 hash_print_statistics (file
, "i386 opcode", op_hash
);
2659 hash_print_statistics (file
, "i386 register", reg_hash
);
2664 /* Debugging routines for md_assemble. */
2665 static void pte (insn_template
*);
2666 static void pt (i386_operand_type
);
2667 static void pe (expressionS
*);
2668 static void ps (symbolS
*);
2671 pi (char *line
, i386_insn
*x
)
2675 fprintf (stdout
, "%s: template ", line
);
2677 fprintf (stdout
, " address: base %s index %s scale %x\n",
2678 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2679 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2680 x
->log2_scale_factor
);
2681 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2682 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2683 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2684 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2685 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2686 (x
->rex
& REX_W
) != 0,
2687 (x
->rex
& REX_R
) != 0,
2688 (x
->rex
& REX_X
) != 0,
2689 (x
->rex
& REX_B
) != 0);
2690 for (j
= 0; j
< x
->operands
; j
++)
2692 fprintf (stdout
, " #%d: ", j
+ 1);
2694 fprintf (stdout
, "\n");
2695 if (x
->types
[j
].bitfield
.reg8
2696 || x
->types
[j
].bitfield
.reg16
2697 || x
->types
[j
].bitfield
.reg32
2698 || x
->types
[j
].bitfield
.reg64
2699 || x
->types
[j
].bitfield
.regmmx
2700 || x
->types
[j
].bitfield
.regxmm
2701 || x
->types
[j
].bitfield
.regymm
2702 || x
->types
[j
].bitfield
.regzmm
2703 || x
->types
[j
].bitfield
.sreg2
2704 || x
->types
[j
].bitfield
.sreg3
2705 || x
->types
[j
].bitfield
.control
2706 || x
->types
[j
].bitfield
.debug
2707 || x
->types
[j
].bitfield
.test
)
2708 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2709 if (operand_type_check (x
->types
[j
], imm
))
2711 if (operand_type_check (x
->types
[j
], disp
))
2712 pe (x
->op
[j
].disps
);
2717 pte (insn_template
*t
)
2720 fprintf (stdout
, " %d operands ", t
->operands
);
2721 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2722 if (t
->extension_opcode
!= None
)
2723 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2724 if (t
->opcode_modifier
.d
)
2725 fprintf (stdout
, "D");
2726 if (t
->opcode_modifier
.w
)
2727 fprintf (stdout
, "W");
2728 fprintf (stdout
, "\n");
2729 for (j
= 0; j
< t
->operands
; j
++)
2731 fprintf (stdout
, " #%d type ", j
+ 1);
2732 pt (t
->operand_types
[j
]);
2733 fprintf (stdout
, "\n");
2740 fprintf (stdout
, " operation %d\n", e
->X_op
);
2741 fprintf (stdout
, " add_number %ld (%lx)\n",
2742 (long) e
->X_add_number
, (long) e
->X_add_number
);
2743 if (e
->X_add_symbol
)
2745 fprintf (stdout
, " add_symbol ");
2746 ps (e
->X_add_symbol
);
2747 fprintf (stdout
, "\n");
2751 fprintf (stdout
, " op_symbol ");
2752 ps (e
->X_op_symbol
);
2753 fprintf (stdout
, "\n");
2760 fprintf (stdout
, "%s type %s%s",
2762 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2763 segment_name (S_GET_SEGMENT (s
)));
2766 static struct type_name
2768 i386_operand_type mask
;
2771 const type_names
[] =
2773 { OPERAND_TYPE_REG8
, "r8" },
2774 { OPERAND_TYPE_REG16
, "r16" },
2775 { OPERAND_TYPE_REG32
, "r32" },
2776 { OPERAND_TYPE_REG64
, "r64" },
2777 { OPERAND_TYPE_IMM8
, "i8" },
2778 { OPERAND_TYPE_IMM8
, "i8s" },
2779 { OPERAND_TYPE_IMM16
, "i16" },
2780 { OPERAND_TYPE_IMM32
, "i32" },
2781 { OPERAND_TYPE_IMM32S
, "i32s" },
2782 { OPERAND_TYPE_IMM64
, "i64" },
2783 { OPERAND_TYPE_IMM1
, "i1" },
2784 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2785 { OPERAND_TYPE_DISP8
, "d8" },
2786 { OPERAND_TYPE_DISP16
, "d16" },
2787 { OPERAND_TYPE_DISP32
, "d32" },
2788 { OPERAND_TYPE_DISP32S
, "d32s" },
2789 { OPERAND_TYPE_DISP64
, "d64" },
2790 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2791 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2792 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2793 { OPERAND_TYPE_CONTROL
, "control reg" },
2794 { OPERAND_TYPE_TEST
, "test reg" },
2795 { OPERAND_TYPE_DEBUG
, "debug reg" },
2796 { OPERAND_TYPE_FLOATREG
, "FReg" },
2797 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2798 { OPERAND_TYPE_SREG2
, "SReg2" },
2799 { OPERAND_TYPE_SREG3
, "SReg3" },
2800 { OPERAND_TYPE_ACC
, "Acc" },
2801 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2802 { OPERAND_TYPE_REGMMX
, "rMMX" },
2803 { OPERAND_TYPE_REGXMM
, "rXMM" },
2804 { OPERAND_TYPE_REGYMM
, "rYMM" },
2805 { OPERAND_TYPE_REGZMM
, "rZMM" },
2806 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2807 { OPERAND_TYPE_ESSEG
, "es" },
2811 pt (i386_operand_type t
)
2814 i386_operand_type a
;
2816 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2818 a
= operand_type_and (t
, type_names
[j
].mask
);
2819 if (!operand_type_all_zero (&a
))
2820 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2825 #endif /* DEBUG386 */
2827 static bfd_reloc_code_real_type
2828 reloc (unsigned int size
,
2832 bfd_reloc_code_real_type other
)
2834 if (other
!= NO_RELOC
)
2836 reloc_howto_type
*rel
;
2841 case BFD_RELOC_X86_64_GOT32
:
2842 return BFD_RELOC_X86_64_GOT64
;
2844 case BFD_RELOC_X86_64_GOTPLT64
:
2845 return BFD_RELOC_X86_64_GOTPLT64
;
2847 case BFD_RELOC_X86_64_PLTOFF64
:
2848 return BFD_RELOC_X86_64_PLTOFF64
;
2850 case BFD_RELOC_X86_64_GOTPC32
:
2851 other
= BFD_RELOC_X86_64_GOTPC64
;
2853 case BFD_RELOC_X86_64_GOTPCREL
:
2854 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2856 case BFD_RELOC_X86_64_TPOFF32
:
2857 other
= BFD_RELOC_X86_64_TPOFF64
;
2859 case BFD_RELOC_X86_64_DTPOFF32
:
2860 other
= BFD_RELOC_X86_64_DTPOFF64
;
2866 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2867 if (other
== BFD_RELOC_SIZE32
)
2870 other
= BFD_RELOC_SIZE64
;
2873 as_bad (_("there are no pc-relative size relocations"));
2879 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2880 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2883 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2885 as_bad (_("unknown relocation (%u)"), other
);
2886 else if (size
!= bfd_get_reloc_size (rel
))
2887 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2888 bfd_get_reloc_size (rel
),
2890 else if (pcrel
&& !rel
->pc_relative
)
2891 as_bad (_("non-pc-relative relocation for pc-relative field"));
2892 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2894 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2896 as_bad (_("relocated field and relocation type differ in signedness"));
2905 as_bad (_("there are no unsigned pc-relative relocations"));
2908 case 1: return BFD_RELOC_8_PCREL
;
2909 case 2: return BFD_RELOC_16_PCREL
;
2910 case 4: return (bnd_prefix
&& object_64bit
2911 ? BFD_RELOC_X86_64_PC32_BND
2912 : BFD_RELOC_32_PCREL
);
2913 case 8: return BFD_RELOC_64_PCREL
;
2915 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2922 case 4: return BFD_RELOC_X86_64_32S
;
2927 case 1: return BFD_RELOC_8
;
2928 case 2: return BFD_RELOC_16
;
2929 case 4: return BFD_RELOC_32
;
2930 case 8: return BFD_RELOC_64
;
2932 as_bad (_("cannot do %s %u byte relocation"),
2933 sign
> 0 ? "signed" : "unsigned", size
);
2939 /* Here we decide which fixups can be adjusted to make them relative to
2940 the beginning of the section instead of the symbol. Basically we need
2941 to make sure that the dynamic relocations are done correctly, so in
2942 some cases we force the original symbol to be used. */
2945 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2947 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2951 /* Don't adjust pc-relative references to merge sections in 64-bit
2953 if (use_rela_relocations
2954 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2958 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2959 and changed later by validate_fix. */
2960 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2961 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2964 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2965 for size relocations. */
2966 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2967 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2968 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2969 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2970 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2971 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2972 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2973 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2974 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2975 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2976 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2977 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2978 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2979 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2980 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2981 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2982 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2983 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2984 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2985 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2986 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2987 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2988 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2989 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2990 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2991 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2992 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2993 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2994 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2995 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3002 intel_float_operand (const char *mnemonic
)
3004 /* Note that the value returned is meaningful only for opcodes with (memory)
3005 operands, hence the code here is free to improperly handle opcodes that
3006 have no operands (for better performance and smaller code). */
3008 if (mnemonic
[0] != 'f')
3009 return 0; /* non-math */
3011 switch (mnemonic
[1])
3013 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3014 the fs segment override prefix not currently handled because no
3015 call path can make opcodes without operands get here */
3017 return 2 /* integer op */;
3019 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3020 return 3; /* fldcw/fldenv */
3023 if (mnemonic
[2] != 'o' /* fnop */)
3024 return 3; /* non-waiting control op */
3027 if (mnemonic
[2] == 's')
3028 return 3; /* frstor/frstpm */
3031 if (mnemonic
[2] == 'a')
3032 return 3; /* fsave */
3033 if (mnemonic
[2] == 't')
3035 switch (mnemonic
[3])
3037 case 'c': /* fstcw */
3038 case 'd': /* fstdw */
3039 case 'e': /* fstenv */
3040 case 's': /* fsts[gw] */
3046 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3047 return 0; /* fxsave/fxrstor are not really math ops */
3054 /* Build the VEX prefix. */
3057 build_vex_prefix (const insn_template
*t
)
3059 unsigned int register_specifier
;
3060 unsigned int implied_prefix
;
3061 unsigned int vector_length
;
3063 /* Check register specifier. */
3064 if (i
.vex
.register_specifier
)
3066 register_specifier
=
3067 ~register_number (i
.vex
.register_specifier
) & 0xf;
3068 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3071 register_specifier
= 0xf;
3073 /* Use 2-byte VEX prefix by swappping destination and source
3076 && i
.operands
== i
.reg_operands
3077 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3078 && i
.tm
.opcode_modifier
.s
3081 unsigned int xchg
= i
.operands
- 1;
3082 union i386_op temp_op
;
3083 i386_operand_type temp_type
;
3085 temp_type
= i
.types
[xchg
];
3086 i
.types
[xchg
] = i
.types
[0];
3087 i
.types
[0] = temp_type
;
3088 temp_op
= i
.op
[xchg
];
3089 i
.op
[xchg
] = i
.op
[0];
3092 gas_assert (i
.rm
.mode
== 3);
3096 i
.rm
.regmem
= i
.rm
.reg
;
3099 /* Use the next insn. */
3103 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3104 vector_length
= avxscalar
;
3106 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3108 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3113 case DATA_PREFIX_OPCODE
:
3116 case REPE_PREFIX_OPCODE
:
3119 case REPNE_PREFIX_OPCODE
:
3126 /* Use 2-byte VEX prefix if possible. */
3127 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3128 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3129 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3131 /* 2-byte VEX prefix. */
3135 i
.vex
.bytes
[0] = 0xc5;
3137 /* Check the REX.R bit. */
3138 r
= (i
.rex
& REX_R
) ? 0 : 1;
3139 i
.vex
.bytes
[1] = (r
<< 7
3140 | register_specifier
<< 3
3141 | vector_length
<< 2
3146 /* 3-byte VEX prefix. */
3151 switch (i
.tm
.opcode_modifier
.vexopcode
)
3155 i
.vex
.bytes
[0] = 0xc4;
3159 i
.vex
.bytes
[0] = 0xc4;
3163 i
.vex
.bytes
[0] = 0xc4;
3167 i
.vex
.bytes
[0] = 0x8f;
3171 i
.vex
.bytes
[0] = 0x8f;
3175 i
.vex
.bytes
[0] = 0x8f;
3181 /* The high 3 bits of the second VEX byte are 1's compliment
3182 of RXB bits from REX. */
3183 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3185 /* Check the REX.W bit. */
3186 w
= (i
.rex
& REX_W
) ? 1 : 0;
3187 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3190 i
.vex
.bytes
[2] = (w
<< 7
3191 | register_specifier
<< 3
3192 | vector_length
<< 2
3197 /* Build the EVEX prefix. */
3200 build_evex_prefix (void)
3202 unsigned int register_specifier
;
3203 unsigned int implied_prefix
;
3205 rex_byte vrex_used
= 0;
3207 /* Check register specifier. */
3208 if (i
.vex
.register_specifier
)
3210 gas_assert ((i
.vrex
& REX_X
) == 0);
3212 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3213 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3214 register_specifier
+= 8;
3215 /* The upper 16 registers are encoded in the fourth byte of the
3217 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3218 i
.vex
.bytes
[3] = 0x8;
3219 register_specifier
= ~register_specifier
& 0xf;
3223 register_specifier
= 0xf;
3225 /* Encode upper 16 vector index register in the fourth byte of
3227 if (!(i
.vrex
& REX_X
))
3228 i
.vex
.bytes
[3] = 0x8;
3233 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3238 case DATA_PREFIX_OPCODE
:
3241 case REPE_PREFIX_OPCODE
:
3244 case REPNE_PREFIX_OPCODE
:
3251 /* 4 byte EVEX prefix. */
3253 i
.vex
.bytes
[0] = 0x62;
3256 switch (i
.tm
.opcode_modifier
.vexopcode
)
3272 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3274 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3276 /* The fifth bit of the second EVEX byte is 1's compliment of the
3277 REX_R bit in VREX. */
3278 if (!(i
.vrex
& REX_R
))
3279 i
.vex
.bytes
[1] |= 0x10;
3283 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3285 /* When all operands are registers, the REX_X bit in REX is not
3286 used. We reuse it to encode the upper 16 registers, which is
3287 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3288 as 1's compliment. */
3289 if ((i
.vrex
& REX_B
))
3292 i
.vex
.bytes
[1] &= ~0x40;
3296 /* EVEX instructions shouldn't need the REX prefix. */
3297 i
.vrex
&= ~vrex_used
;
3298 gas_assert (i
.vrex
== 0);
3300 /* Check the REX.W bit. */
3301 w
= (i
.rex
& REX_W
) ? 1 : 0;
3302 if (i
.tm
.opcode_modifier
.vexw
)
3304 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3307 /* If w is not set it means we are dealing with WIG instruction. */
3310 if (evexwig
== evexw1
)
3314 /* Encode the U bit. */
3315 implied_prefix
|= 0x4;
3317 /* The third byte of the EVEX prefix. */
3318 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3320 /* The fourth byte of the EVEX prefix. */
3321 /* The zeroing-masking bit. */
3322 if (i
.mask
&& i
.mask
->zeroing
)
3323 i
.vex
.bytes
[3] |= 0x80;
3325 /* Don't always set the broadcast bit if there is no RC. */
3328 /* Encode the vector length. */
3329 unsigned int vec_length
;
3331 switch (i
.tm
.opcode_modifier
.evex
)
3333 case EVEXLIG
: /* LL' is ignored */
3334 vec_length
= evexlig
<< 5;
3337 vec_length
= 0 << 5;
3340 vec_length
= 1 << 5;
3343 vec_length
= 2 << 5;
3349 i
.vex
.bytes
[3] |= vec_length
;
3350 /* Encode the broadcast bit. */
3352 i
.vex
.bytes
[3] |= 0x10;
3356 if (i
.rounding
->type
!= saeonly
)
3357 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3359 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3362 if (i
.mask
&& i
.mask
->mask
)
3363 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3367 process_immext (void)
3371 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3374 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3375 with an opcode suffix which is coded in the same place as an
3376 8-bit immediate field would be.
3377 Here we check those operands and remove them afterwards. */
3380 for (x
= 0; x
< i
.operands
; x
++)
3381 if (register_number (i
.op
[x
].regs
) != x
)
3382 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3383 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3389 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3390 which is coded in the same place as an 8-bit immediate field
3391 would be. Here we fake an 8-bit immediate operand from the
3392 opcode suffix stored in tm.extension_opcode.
3394 AVX instructions also use this encoding, for some of
3395 3 argument instructions. */
3397 gas_assert (i
.imm_operands
<= 1
3399 || ((i
.tm
.opcode_modifier
.vex
3400 || i
.tm
.opcode_modifier
.evex
)
3401 && i
.operands
<= 4)));
3403 exp
= &im_expressions
[i
.imm_operands
++];
3404 i
.op
[i
.operands
].imms
= exp
;
3405 i
.types
[i
.operands
] = imm8
;
3407 exp
->X_op
= O_constant
;
3408 exp
->X_add_number
= i
.tm
.extension_opcode
;
3409 i
.tm
.extension_opcode
= None
;
3416 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3421 as_bad (_("invalid instruction `%s' after `%s'"),
3422 i
.tm
.name
, i
.hle_prefix
);
3425 if (i
.prefix
[LOCK_PREFIX
])
3427 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3431 case HLEPrefixRelease
:
3432 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3434 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3438 if (i
.mem_operands
== 0
3439 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3441 as_bad (_("memory destination needed for instruction `%s'"
3442 " after `xrelease'"), i
.tm
.name
);
3449 /* This is the guts of the machine-dependent assembler. LINE points to a
3450 machine dependent instruction. This function is supposed to emit
3451 the frags/bytes it assembles to. */
3454 md_assemble (char *line
)
3457 char mnemonic
[MAX_MNEM_SIZE
];
3458 const insn_template
*t
;
3460 /* Initialize globals. */
3461 memset (&i
, '\0', sizeof (i
));
3462 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3463 i
.reloc
[j
] = NO_RELOC
;
3464 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3465 memset (im_expressions
, '\0', sizeof (im_expressions
));
3466 save_stack_p
= save_stack
;
3468 /* First parse an instruction mnemonic & call i386_operand for the operands.
3469 We assume that the scrubber has arranged it so that line[0] is the valid
3470 start of a (possibly prefixed) mnemonic. */
3472 line
= parse_insn (line
, mnemonic
);
3476 line
= parse_operands (line
, mnemonic
);
3481 /* Now we've parsed the mnemonic into a set of templates, and have the
3482 operands at hand. */
3484 /* All intel opcodes have reversed operands except for "bound" and
3485 "enter". We also don't reverse intersegment "jmp" and "call"
3486 instructions with 2 immediate operands so that the immediate segment
3487 precedes the offset, as it does when in AT&T mode. */
3490 && (strcmp (mnemonic
, "bound") != 0)
3491 && (strcmp (mnemonic
, "invlpga") != 0)
3492 && !(operand_type_check (i
.types
[0], imm
)
3493 && operand_type_check (i
.types
[1], imm
)))
3496 /* The order of the immediates should be reversed
3497 for 2 immediates extrq and insertq instructions */
3498 if (i
.imm_operands
== 2
3499 && (strcmp (mnemonic
, "extrq") == 0
3500 || strcmp (mnemonic
, "insertq") == 0))
3501 swap_2_operands (0, 1);
3506 /* Don't optimize displacement for movabs since it only takes 64bit
3509 && i
.disp_encoding
!= disp_encoding_32bit
3510 && (flag_code
!= CODE_64BIT
3511 || strcmp (mnemonic
, "movabs") != 0))
3514 /* Next, we find a template that matches the given insn,
3515 making sure the overlap of the given operands types is consistent
3516 with the template operand types. */
3518 if (!(t
= match_template ()))
3521 if (sse_check
!= check_none
3522 && !i
.tm
.opcode_modifier
.noavx
3523 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3524 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3525 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3526 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3527 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3528 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3530 (sse_check
== check_warning
3532 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3535 /* Zap movzx and movsx suffix. The suffix has been set from
3536 "word ptr" or "byte ptr" on the source operand in Intel syntax
3537 or extracted from mnemonic in AT&T syntax. But we'll use
3538 the destination register to choose the suffix for encoding. */
3539 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3541 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3542 there is no suffix, the default will be byte extension. */
3543 if (i
.reg_operands
!= 2
3546 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3551 if (i
.tm
.opcode_modifier
.fwait
)
3552 if (!add_prefix (FWAIT_OPCODE
))
3555 /* Check if REP prefix is OK. */
3556 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3558 as_bad (_("invalid instruction `%s' after `%s'"),
3559 i
.tm
.name
, i
.rep_prefix
);
3563 /* Check for lock without a lockable instruction. Destination operand
3564 must be memory unless it is xchg (0x86). */
3565 if (i
.prefix
[LOCK_PREFIX
]
3566 && (!i
.tm
.opcode_modifier
.islockable
3567 || i
.mem_operands
== 0
3568 || (i
.tm
.base_opcode
!= 0x86
3569 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3571 as_bad (_("expecting lockable instruction after `lock'"));
3575 /* Check if HLE prefix is OK. */
3576 if (i
.hle_prefix
&& !check_hle ())
3579 /* Check BND prefix. */
3580 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3581 as_bad (_("expecting valid branch instruction after `bnd'"));
3583 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3584 && flag_code
== CODE_64BIT
3585 && i
.prefix
[ADDR_PREFIX
])
3586 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3588 /* Insert BND prefix. */
3590 && i
.tm
.opcode_modifier
.bndprefixok
3591 && !i
.prefix
[BND_PREFIX
])
3592 add_prefix (BND_PREFIX_OPCODE
);
3594 /* Check string instruction segment overrides. */
3595 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3597 if (!check_string ())
3599 i
.disp_operands
= 0;
3602 if (!process_suffix ())
3605 /* Update operand types. */
3606 for (j
= 0; j
< i
.operands
; j
++)
3607 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3609 /* Make still unresolved immediate matches conform to size of immediate
3610 given in i.suffix. */
3611 if (!finalize_imm ())
3614 if (i
.types
[0].bitfield
.imm1
)
3615 i
.imm_operands
= 0; /* kludge for shift insns. */
3617 /* We only need to check those implicit registers for instructions
3618 with 3 operands or less. */
3619 if (i
.operands
<= 3)
3620 for (j
= 0; j
< i
.operands
; j
++)
3621 if (i
.types
[j
].bitfield
.inoutportreg
3622 || i
.types
[j
].bitfield
.shiftcount
3623 || i
.types
[j
].bitfield
.acc
3624 || i
.types
[j
].bitfield
.floatacc
)
3627 /* ImmExt should be processed after SSE2AVX. */
3628 if (!i
.tm
.opcode_modifier
.sse2avx
3629 && i
.tm
.opcode_modifier
.immext
)
3632 /* For insns with operands there are more diddles to do to the opcode. */
3635 if (!process_operands ())
3638 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3640 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3641 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3644 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3646 if (flag_code
== CODE_16BIT
)
3648 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3653 if (i
.tm
.opcode_modifier
.vex
)
3654 build_vex_prefix (t
);
3656 build_evex_prefix ();
3659 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3660 instructions may define INT_OPCODE as well, so avoid this corner
3661 case for those instructions that use MODRM. */
3662 if (i
.tm
.base_opcode
== INT_OPCODE
3663 && !i
.tm
.opcode_modifier
.modrm
3664 && i
.op
[0].imms
->X_add_number
== 3)
3666 i
.tm
.base_opcode
= INT3_OPCODE
;
3670 if ((i
.tm
.opcode_modifier
.jump
3671 || i
.tm
.opcode_modifier
.jumpbyte
3672 || i
.tm
.opcode_modifier
.jumpdword
)
3673 && i
.op
[0].disps
->X_op
== O_constant
)
3675 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3676 the absolute address given by the constant. Since ix86 jumps and
3677 calls are pc relative, we need to generate a reloc. */
3678 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3679 i
.op
[0].disps
->X_op
= O_symbol
;
3682 if (i
.tm
.opcode_modifier
.rex64
)
3685 /* For 8 bit registers we need an empty rex prefix. Also if the
3686 instruction already has a prefix, we need to convert old
3687 registers to new ones. */
3689 if ((i
.types
[0].bitfield
.reg8
3690 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3691 || (i
.types
[1].bitfield
.reg8
3692 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3693 || ((i
.types
[0].bitfield
.reg8
3694 || i
.types
[1].bitfield
.reg8
)
3699 i
.rex
|= REX_OPCODE
;
3700 for (x
= 0; x
< 2; x
++)
3702 /* Look for 8 bit operand that uses old registers. */
3703 if (i
.types
[x
].bitfield
.reg8
3704 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3706 /* In case it is "hi" register, give up. */
3707 if (i
.op
[x
].regs
->reg_num
> 3)
3708 as_bad (_("can't encode register '%s%s' in an "
3709 "instruction requiring REX prefix."),
3710 register_prefix
, i
.op
[x
].regs
->reg_name
);
3712 /* Otherwise it is equivalent to the extended register.
3713 Since the encoding doesn't change this is merely
3714 cosmetic cleanup for debug output. */
3716 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3722 add_prefix (REX_OPCODE
| i
.rex
);
3724 /* We are ready to output the insn. */
3729 parse_insn (char *line
, char *mnemonic
)
3732 char *token_start
= l
;
3735 const insn_template
*t
;
3741 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3746 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3748 as_bad (_("no such instruction: `%s'"), token_start
);
3753 if (!is_space_char (*l
)
3754 && *l
!= END_OF_INSN
3756 || (*l
!= PREFIX_SEPARATOR
3759 as_bad (_("invalid character %s in mnemonic"),
3760 output_invalid (*l
));
3763 if (token_start
== l
)
3765 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3766 as_bad (_("expecting prefix; got nothing"));
3768 as_bad (_("expecting mnemonic; got nothing"));
3772 /* Look up instruction (or prefix) via hash table. */
3773 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3775 if (*l
!= END_OF_INSN
3776 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3777 && current_templates
3778 && current_templates
->start
->opcode_modifier
.isprefix
)
3780 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3782 as_bad ((flag_code
!= CODE_64BIT
3783 ? _("`%s' is only supported in 64-bit mode")
3784 : _("`%s' is not supported in 64-bit mode")),
3785 current_templates
->start
->name
);
3788 /* If we are in 16-bit mode, do not allow addr16 or data16.
3789 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3790 if ((current_templates
->start
->opcode_modifier
.size16
3791 || current_templates
->start
->opcode_modifier
.size32
)
3792 && flag_code
!= CODE_64BIT
3793 && (current_templates
->start
->opcode_modifier
.size32
3794 ^ (flag_code
== CODE_16BIT
)))
3796 as_bad (_("redundant %s prefix"),
3797 current_templates
->start
->name
);
3800 /* Add prefix, checking for repeated prefixes. */
3801 switch (add_prefix (current_templates
->start
->base_opcode
))
3806 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3807 i
.hle_prefix
= current_templates
->start
->name
;
3808 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3809 i
.bnd_prefix
= current_templates
->start
->name
;
3811 i
.rep_prefix
= current_templates
->start
->name
;
3816 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3823 if (!current_templates
)
3825 /* Check if we should swap operand or force 32bit displacement in
3827 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3829 else if (mnem_p
- 3 == dot_p
3832 i
.disp_encoding
= disp_encoding_8bit
;
3833 else if (mnem_p
- 4 == dot_p
3837 i
.disp_encoding
= disp_encoding_32bit
;
3842 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3845 if (!current_templates
)
3848 /* See if we can get a match by trimming off a suffix. */
3851 case WORD_MNEM_SUFFIX
:
3852 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3853 i
.suffix
= SHORT_MNEM_SUFFIX
;
3855 case BYTE_MNEM_SUFFIX
:
3856 case QWORD_MNEM_SUFFIX
:
3857 i
.suffix
= mnem_p
[-1];
3859 current_templates
= (const templates
*) hash_find (op_hash
,
3862 case SHORT_MNEM_SUFFIX
:
3863 case LONG_MNEM_SUFFIX
:
3866 i
.suffix
= mnem_p
[-1];
3868 current_templates
= (const templates
*) hash_find (op_hash
,
3877 if (intel_float_operand (mnemonic
) == 1)
3878 i
.suffix
= SHORT_MNEM_SUFFIX
;
3880 i
.suffix
= LONG_MNEM_SUFFIX
;
3882 current_templates
= (const templates
*) hash_find (op_hash
,
3887 if (!current_templates
)
3889 as_bad (_("no such instruction: `%s'"), token_start
);
3894 if (current_templates
->start
->opcode_modifier
.jump
3895 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3897 /* Check for a branch hint. We allow ",pt" and ",pn" for
3898 predict taken and predict not taken respectively.
3899 I'm not sure that branch hints actually do anything on loop
3900 and jcxz insns (JumpByte) for current Pentium4 chips. They
3901 may work in the future and it doesn't hurt to accept them
3903 if (l
[0] == ',' && l
[1] == 'p')
3907 if (!add_prefix (DS_PREFIX_OPCODE
))
3911 else if (l
[2] == 'n')
3913 if (!add_prefix (CS_PREFIX_OPCODE
))
3919 /* Any other comma loses. */
3922 as_bad (_("invalid character %s in mnemonic"),
3923 output_invalid (*l
));
3927 /* Check if instruction is supported on specified architecture. */
3929 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3931 supported
|= cpu_flags_match (t
);
3932 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3936 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3938 as_bad (flag_code
== CODE_64BIT
3939 ? _("`%s' is not supported in 64-bit mode")
3940 : _("`%s' is only supported in 64-bit mode"),
3941 current_templates
->start
->name
);
3944 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3946 as_bad (_("`%s' is not supported on `%s%s'"),
3947 current_templates
->start
->name
,
3948 cpu_arch_name
? cpu_arch_name
: default_arch
,
3949 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3954 if (!cpu_arch_flags
.bitfield
.cpui386
3955 && (flag_code
!= CODE_16BIT
))
3957 as_warn (_("use .code16 to ensure correct addressing mode"));
3964 parse_operands (char *l
, const char *mnemonic
)
3968 /* 1 if operand is pending after ','. */
3969 unsigned int expecting_operand
= 0;
3971 /* Non-zero if operand parens not balanced. */
3972 unsigned int paren_not_balanced
;
3974 while (*l
!= END_OF_INSN
)
3976 /* Skip optional white space before operand. */
3977 if (is_space_char (*l
))
3979 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3981 as_bad (_("invalid character %s before operand %d"),
3982 output_invalid (*l
),
3986 token_start
= l
; /* after white space */
3987 paren_not_balanced
= 0;
3988 while (paren_not_balanced
|| *l
!= ',')
3990 if (*l
== END_OF_INSN
)
3992 if (paren_not_balanced
)
3995 as_bad (_("unbalanced parenthesis in operand %d."),
3998 as_bad (_("unbalanced brackets in operand %d."),
4003 break; /* we are done */
4005 else if (!is_operand_char (*l
) && !is_space_char (*l
))
4007 as_bad (_("invalid character %s in operand %d"),
4008 output_invalid (*l
),
4015 ++paren_not_balanced
;
4017 --paren_not_balanced
;
4022 ++paren_not_balanced
;
4024 --paren_not_balanced
;
4028 if (l
!= token_start
)
4029 { /* Yes, we've read in another operand. */
4030 unsigned int operand_ok
;
4031 this_operand
= i
.operands
++;
4032 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4033 if (i
.operands
> MAX_OPERANDS
)
4035 as_bad (_("spurious operands; (%d operands/instruction max)"),
4039 /* Now parse operand adding info to 'i' as we go along. */
4040 END_STRING_AND_SAVE (l
);
4044 i386_intel_operand (token_start
,
4045 intel_float_operand (mnemonic
));
4047 operand_ok
= i386_att_operand (token_start
);
4049 RESTORE_END_STRING (l
);
4055 if (expecting_operand
)
4057 expecting_operand_after_comma
:
4058 as_bad (_("expecting operand after ','; got nothing"));
4063 as_bad (_("expecting operand before ','; got nothing"));
4068 /* Now *l must be either ',' or END_OF_INSN. */
4071 if (*++l
== END_OF_INSN
)
4073 /* Just skip it, if it's \n complain. */
4074 goto expecting_operand_after_comma
;
4076 expecting_operand
= 1;
4083 swap_2_operands (int xchg1
, int xchg2
)
4085 union i386_op temp_op
;
4086 i386_operand_type temp_type
;
4087 enum bfd_reloc_code_real temp_reloc
;
4089 temp_type
= i
.types
[xchg2
];
4090 i
.types
[xchg2
] = i
.types
[xchg1
];
4091 i
.types
[xchg1
] = temp_type
;
4092 temp_op
= i
.op
[xchg2
];
4093 i
.op
[xchg2
] = i
.op
[xchg1
];
4094 i
.op
[xchg1
] = temp_op
;
4095 temp_reloc
= i
.reloc
[xchg2
];
4096 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4097 i
.reloc
[xchg1
] = temp_reloc
;
4101 if (i
.mask
->operand
== xchg1
)
4102 i
.mask
->operand
= xchg2
;
4103 else if (i
.mask
->operand
== xchg2
)
4104 i
.mask
->operand
= xchg1
;
4108 if (i
.broadcast
->operand
== xchg1
)
4109 i
.broadcast
->operand
= xchg2
;
4110 else if (i
.broadcast
->operand
== xchg2
)
4111 i
.broadcast
->operand
= xchg1
;
4115 if (i
.rounding
->operand
== xchg1
)
4116 i
.rounding
->operand
= xchg2
;
4117 else if (i
.rounding
->operand
== xchg2
)
4118 i
.rounding
->operand
= xchg1
;
4123 swap_operands (void)
4129 swap_2_operands (1, i
.operands
- 2);
4132 swap_2_operands (0, i
.operands
- 1);
4138 if (i
.mem_operands
== 2)
4140 const seg_entry
*temp_seg
;
4141 temp_seg
= i
.seg
[0];
4142 i
.seg
[0] = i
.seg
[1];
4143 i
.seg
[1] = temp_seg
;
4147 /* Try to ensure constant immediates are represented in the smallest
4152 char guess_suffix
= 0;
4156 guess_suffix
= i
.suffix
;
4157 else if (i
.reg_operands
)
4159 /* Figure out a suffix from the last register operand specified.
4160 We can't do this properly yet, ie. excluding InOutPortReg,
4161 but the following works for instructions with immediates.
4162 In any case, we can't set i.suffix yet. */
4163 for (op
= i
.operands
; --op
>= 0;)
4164 if (i
.types
[op
].bitfield
.reg8
)
4166 guess_suffix
= BYTE_MNEM_SUFFIX
;
4169 else if (i
.types
[op
].bitfield
.reg16
)
4171 guess_suffix
= WORD_MNEM_SUFFIX
;
4174 else if (i
.types
[op
].bitfield
.reg32
)
4176 guess_suffix
= LONG_MNEM_SUFFIX
;
4179 else if (i
.types
[op
].bitfield
.reg64
)
4181 guess_suffix
= QWORD_MNEM_SUFFIX
;
4185 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4186 guess_suffix
= WORD_MNEM_SUFFIX
;
4188 for (op
= i
.operands
; --op
>= 0;)
4189 if (operand_type_check (i
.types
[op
], imm
))
4191 switch (i
.op
[op
].imms
->X_op
)
4194 /* If a suffix is given, this operand may be shortened. */
4195 switch (guess_suffix
)
4197 case LONG_MNEM_SUFFIX
:
4198 i
.types
[op
].bitfield
.imm32
= 1;
4199 i
.types
[op
].bitfield
.imm64
= 1;
4201 case WORD_MNEM_SUFFIX
:
4202 i
.types
[op
].bitfield
.imm16
= 1;
4203 i
.types
[op
].bitfield
.imm32
= 1;
4204 i
.types
[op
].bitfield
.imm32s
= 1;
4205 i
.types
[op
].bitfield
.imm64
= 1;
4207 case BYTE_MNEM_SUFFIX
:
4208 i
.types
[op
].bitfield
.imm8
= 1;
4209 i
.types
[op
].bitfield
.imm8s
= 1;
4210 i
.types
[op
].bitfield
.imm16
= 1;
4211 i
.types
[op
].bitfield
.imm32
= 1;
4212 i
.types
[op
].bitfield
.imm32s
= 1;
4213 i
.types
[op
].bitfield
.imm64
= 1;
4217 /* If this operand is at most 16 bits, convert it
4218 to a signed 16 bit number before trying to see
4219 whether it will fit in an even smaller size.
4220 This allows a 16-bit operand such as $0xffe0 to
4221 be recognised as within Imm8S range. */
4222 if ((i
.types
[op
].bitfield
.imm16
)
4223 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4225 i
.op
[op
].imms
->X_add_number
=
4226 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4228 if ((i
.types
[op
].bitfield
.imm32
)
4229 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4232 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4233 ^ ((offsetT
) 1 << 31))
4234 - ((offsetT
) 1 << 31));
4237 = operand_type_or (i
.types
[op
],
4238 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4240 /* We must avoid matching of Imm32 templates when 64bit
4241 only immediate is available. */
4242 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4243 i
.types
[op
].bitfield
.imm32
= 0;
4250 /* Symbols and expressions. */
4252 /* Convert symbolic operand to proper sizes for matching, but don't
4253 prevent matching a set of insns that only supports sizes other
4254 than those matching the insn suffix. */
4256 i386_operand_type mask
, allowed
;
4257 const insn_template
*t
;
4259 operand_type_set (&mask
, 0);
4260 operand_type_set (&allowed
, 0);
4262 for (t
= current_templates
->start
;
4263 t
< current_templates
->end
;
4265 allowed
= operand_type_or (allowed
,
4266 t
->operand_types
[op
]);
4267 switch (guess_suffix
)
4269 case QWORD_MNEM_SUFFIX
:
4270 mask
.bitfield
.imm64
= 1;
4271 mask
.bitfield
.imm32s
= 1;
4273 case LONG_MNEM_SUFFIX
:
4274 mask
.bitfield
.imm32
= 1;
4276 case WORD_MNEM_SUFFIX
:
4277 mask
.bitfield
.imm16
= 1;
4279 case BYTE_MNEM_SUFFIX
:
4280 mask
.bitfield
.imm8
= 1;
4285 allowed
= operand_type_and (mask
, allowed
);
4286 if (!operand_type_all_zero (&allowed
))
4287 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4294 /* Try to use the smallest displacement type too. */
4296 optimize_disp (void)
4300 for (op
= i
.operands
; --op
>= 0;)
4301 if (operand_type_check (i
.types
[op
], disp
))
4303 if (i
.op
[op
].disps
->X_op
== O_constant
)
4305 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4307 if (i
.types
[op
].bitfield
.disp16
4308 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4310 /* If this operand is at most 16 bits, convert
4311 to a signed 16 bit number and don't use 64bit
4313 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4314 i
.types
[op
].bitfield
.disp64
= 0;
4316 if (i
.types
[op
].bitfield
.disp32
4317 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4319 /* If this operand is at most 32 bits, convert
4320 to a signed 32 bit number and don't use 64bit
4322 op_disp
&= (((offsetT
) 2 << 31) - 1);
4323 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4324 i
.types
[op
].bitfield
.disp64
= 0;
4326 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4328 i
.types
[op
].bitfield
.disp8
= 0;
4329 i
.types
[op
].bitfield
.disp16
= 0;
4330 i
.types
[op
].bitfield
.disp32
= 0;
4331 i
.types
[op
].bitfield
.disp32s
= 0;
4332 i
.types
[op
].bitfield
.disp64
= 0;
4336 else if (flag_code
== CODE_64BIT
)
4338 if (fits_in_signed_long (op_disp
))
4340 i
.types
[op
].bitfield
.disp64
= 0;
4341 i
.types
[op
].bitfield
.disp32s
= 1;
4343 if (i
.prefix
[ADDR_PREFIX
]
4344 && fits_in_unsigned_long (op_disp
))
4345 i
.types
[op
].bitfield
.disp32
= 1;
4347 if ((i
.types
[op
].bitfield
.disp32
4348 || i
.types
[op
].bitfield
.disp32s
4349 || i
.types
[op
].bitfield
.disp16
)
4350 && fits_in_signed_byte (op_disp
))
4351 i
.types
[op
].bitfield
.disp8
= 1;
4353 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4354 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4356 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4357 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4358 i
.types
[op
].bitfield
.disp8
= 0;
4359 i
.types
[op
].bitfield
.disp16
= 0;
4360 i
.types
[op
].bitfield
.disp32
= 0;
4361 i
.types
[op
].bitfield
.disp32s
= 0;
4362 i
.types
[op
].bitfield
.disp64
= 0;
4365 /* We only support 64bit displacement on constants. */
4366 i
.types
[op
].bitfield
.disp64
= 0;
4370 /* Check if operands are valid for the instruction. */
4373 check_VecOperands (const insn_template
*t
)
4377 /* Without VSIB byte, we can't have a vector register for index. */
4378 if (!t
->opcode_modifier
.vecsib
4380 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4381 || i
.index_reg
->reg_type
.bitfield
.regymm
4382 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4384 i
.error
= unsupported_vector_index_register
;
4388 /* Check if default mask is allowed. */
4389 if (t
->opcode_modifier
.nodefmask
4390 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4392 i
.error
= no_default_mask
;
4396 /* For VSIB byte, we need a vector register for index, and all vector
4397 registers must be distinct. */
4398 if (t
->opcode_modifier
.vecsib
)
4401 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4402 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4403 || (t
->opcode_modifier
.vecsib
== VecSIB256
4404 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4405 || (t
->opcode_modifier
.vecsib
== VecSIB512
4406 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4408 i
.error
= invalid_vsib_address
;
4412 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4413 if (i
.reg_operands
== 2 && !i
.mask
)
4415 gas_assert (i
.types
[0].bitfield
.regxmm
4416 || i
.types
[0].bitfield
.regymm
);
4417 gas_assert (i
.types
[2].bitfield
.regxmm
4418 || i
.types
[2].bitfield
.regymm
);
4419 if (operand_check
== check_none
)
4421 if (register_number (i
.op
[0].regs
)
4422 != register_number (i
.index_reg
)
4423 && register_number (i
.op
[2].regs
)
4424 != register_number (i
.index_reg
)
4425 && register_number (i
.op
[0].regs
)
4426 != register_number (i
.op
[2].regs
))
4428 if (operand_check
== check_error
)
4430 i
.error
= invalid_vector_register_set
;
4433 as_warn (_("mask, index, and destination registers should be distinct"));
4435 else if (i
.reg_operands
== 1 && i
.mask
)
4437 if ((i
.types
[1].bitfield
.regymm
4438 || i
.types
[1].bitfield
.regzmm
)
4439 && (register_number (i
.op
[1].regs
)
4440 == register_number (i
.index_reg
)))
4442 if (operand_check
== check_error
)
4444 i
.error
= invalid_vector_register_set
;
4447 if (operand_check
!= check_none
)
4448 as_warn (_("index and destination registers should be distinct"));
4453 /* Check if broadcast is supported by the instruction and is applied
4454 to the memory operand. */
4457 int broadcasted_opnd_size
;
4459 /* Check if specified broadcast is supported in this instruction,
4460 and it's applied to memory operand of DWORD or QWORD type,
4461 depending on VecESize. */
4462 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4463 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4464 || (t
->opcode_modifier
.vecesize
== 0
4465 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4466 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4467 || (t
->opcode_modifier
.vecesize
== 1
4468 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4469 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4472 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4473 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4474 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4475 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4476 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4477 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4478 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4479 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4480 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4484 if ((broadcasted_opnd_size
== 256
4485 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4486 || (broadcasted_opnd_size
== 512
4487 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4490 i
.error
= unsupported_broadcast
;
4494 /* If broadcast is supported in this instruction, we need to check if
4495 operand of one-element size isn't specified without broadcast. */
4496 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4498 /* Find memory operand. */
4499 for (op
= 0; op
< i
.operands
; op
++)
4500 if (operand_type_check (i
.types
[op
], anymem
))
4502 gas_assert (op
< i
.operands
);
4503 /* Check size of the memory operand. */
4504 if ((t
->opcode_modifier
.vecesize
== 0
4505 && i
.types
[op
].bitfield
.dword
)
4506 || (t
->opcode_modifier
.vecesize
== 1
4507 && i
.types
[op
].bitfield
.qword
))
4509 i
.error
= broadcast_needed
;
4514 /* Check if requested masking is supported. */
4516 && (!t
->opcode_modifier
.masking
4518 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4520 i
.error
= unsupported_masking
;
4524 /* Check if masking is applied to dest operand. */
4525 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4527 i
.error
= mask_not_on_destination
;
4534 if ((i
.rounding
->type
!= saeonly
4535 && !t
->opcode_modifier
.staticrounding
)
4536 || (i
.rounding
->type
== saeonly
4537 && (t
->opcode_modifier
.staticrounding
4538 || !t
->opcode_modifier
.sae
)))
4540 i
.error
= unsupported_rc_sae
;
4543 /* If the instruction has several immediate operands and one of
4544 them is rounding, the rounding operand should be the last
4545 immediate operand. */
4546 if (i
.imm_operands
> 1
4547 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4549 i
.error
= rc_sae_operand_not_last_imm
;
4554 /* Check vector Disp8 operand. */
4555 if (t
->opcode_modifier
.disp8memshift
)
4558 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4560 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4562 for (op
= 0; op
< i
.operands
; op
++)
4563 if (operand_type_check (i
.types
[op
], disp
)
4564 && i
.op
[op
].disps
->X_op
== O_constant
)
4566 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4567 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4568 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4571 i
.types
[op
].bitfield
.vec_disp8
= 1;
4574 /* Vector insn can only have Vec_Disp8/Disp32 in
4575 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4577 i
.types
[op
].bitfield
.disp8
= 0;
4578 if (flag_code
!= CODE_16BIT
)
4579 i
.types
[op
].bitfield
.disp16
= 0;
4582 else if (flag_code
!= CODE_16BIT
)
4584 /* One form of this instruction supports vector Disp8.
4585 Try vector Disp8 if we need to use Disp32. */
4586 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4588 i
.error
= try_vector_disp8
;
4600 /* Check if operands are valid for the instruction. Update VEX
4604 VEX_check_operands (const insn_template
*t
)
4606 /* VREX is only valid with EVEX prefix. */
4607 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4609 i
.error
= invalid_register_operand
;
4613 if (!t
->opcode_modifier
.vex
)
4616 /* Only check VEX_Imm4, which must be the first operand. */
4617 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4619 if (i
.op
[0].imms
->X_op
!= O_constant
4620 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4626 /* Turn off Imm8 so that update_imm won't complain. */
4627 i
.types
[0] = vec_imm4
;
4633 static const insn_template
*
4634 match_template (void)
4636 /* Points to template once we've found it. */
4637 const insn_template
*t
;
4638 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4639 i386_operand_type overlap4
;
4640 unsigned int found_reverse_match
;
4641 i386_opcode_modifier suffix_check
;
4642 i386_operand_type operand_types
[MAX_OPERANDS
];
4643 int addr_prefix_disp
;
4645 unsigned int found_cpu_match
;
4646 unsigned int check_register
;
4647 enum i386_error specific_error
= 0;
4649 #if MAX_OPERANDS != 5
4650 # error "MAX_OPERANDS must be 5."
4653 found_reverse_match
= 0;
4654 addr_prefix_disp
= -1;
4656 memset (&suffix_check
, 0, sizeof (suffix_check
));
4657 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4658 suffix_check
.no_bsuf
= 1;
4659 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4660 suffix_check
.no_wsuf
= 1;
4661 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4662 suffix_check
.no_ssuf
= 1;
4663 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4664 suffix_check
.no_lsuf
= 1;
4665 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4666 suffix_check
.no_qsuf
= 1;
4667 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4668 suffix_check
.no_ldsuf
= 1;
4670 /* Must have right number of operands. */
4671 i
.error
= number_of_operands_mismatch
;
4673 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4675 addr_prefix_disp
= -1;
4677 if (i
.operands
!= t
->operands
)
4680 /* Check processor support. */
4681 i
.error
= unsupported
;
4682 found_cpu_match
= (cpu_flags_match (t
)
4683 == CPU_FLAGS_PERFECT_MATCH
);
4684 if (!found_cpu_match
)
4687 /* Check old gcc support. */
4688 i
.error
= old_gcc_only
;
4689 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4692 /* Check AT&T mnemonic. */
4693 i
.error
= unsupported_with_intel_mnemonic
;
4694 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4697 /* Check AT&T/Intel syntax. */
4698 i
.error
= unsupported_syntax
;
4699 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4700 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4703 /* Check the suffix, except for some instructions in intel mode. */
4704 i
.error
= invalid_instruction_suffix
;
4705 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4706 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4707 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4708 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4709 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4710 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4711 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4714 if (!operand_size_match (t
))
4717 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4718 operand_types
[j
] = t
->operand_types
[j
];
4720 /* In general, don't allow 64-bit operands in 32-bit mode. */
4721 if (i
.suffix
== QWORD_MNEM_SUFFIX
4722 && flag_code
!= CODE_64BIT
4724 ? (!t
->opcode_modifier
.ignoresize
4725 && !intel_float_operand (t
->name
))
4726 : intel_float_operand (t
->name
) != 2)
4727 && ((!operand_types
[0].bitfield
.regmmx
4728 && !operand_types
[0].bitfield
.regxmm
4729 && !operand_types
[0].bitfield
.regymm
4730 && !operand_types
[0].bitfield
.regzmm
)
4731 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4732 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4733 && operand_types
[t
->operands
> 1].bitfield
.regymm
4734 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4735 && (t
->base_opcode
!= 0x0fc7
4736 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4739 /* In general, don't allow 32-bit operands on pre-386. */
4740 else if (i
.suffix
== LONG_MNEM_SUFFIX
4741 && !cpu_arch_flags
.bitfield
.cpui386
4743 ? (!t
->opcode_modifier
.ignoresize
4744 && !intel_float_operand (t
->name
))
4745 : intel_float_operand (t
->name
) != 2)
4746 && ((!operand_types
[0].bitfield
.regmmx
4747 && !operand_types
[0].bitfield
.regxmm
)
4748 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4749 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4752 /* Do not verify operands when there are none. */
4756 /* We've found a match; break out of loop. */
4760 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4761 into Disp32/Disp16/Disp32 operand. */
4762 if (i
.prefix
[ADDR_PREFIX
] != 0)
4764 /* There should be only one Disp operand. */
4768 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4770 if (operand_types
[j
].bitfield
.disp16
)
4772 addr_prefix_disp
= j
;
4773 operand_types
[j
].bitfield
.disp32
= 1;
4774 operand_types
[j
].bitfield
.disp16
= 0;
4780 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4782 if (operand_types
[j
].bitfield
.disp32
)
4784 addr_prefix_disp
= j
;
4785 operand_types
[j
].bitfield
.disp32
= 0;
4786 operand_types
[j
].bitfield
.disp16
= 1;
4792 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4794 if (operand_types
[j
].bitfield
.disp64
)
4796 addr_prefix_disp
= j
;
4797 operand_types
[j
].bitfield
.disp64
= 0;
4798 operand_types
[j
].bitfield
.disp32
= 1;
4806 /* We check register size if needed. */
4807 check_register
= t
->opcode_modifier
.checkregsize
;
4808 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4809 switch (t
->operands
)
4812 if (!operand_type_match (overlap0
, i
.types
[0]))
4816 /* xchg %eax, %eax is a special case. It is an aliase for nop
4817 only in 32bit mode and we can use opcode 0x90. In 64bit
4818 mode, we can't use 0x90 for xchg %eax, %eax since it should
4819 zero-extend %eax to %rax. */
4820 if (flag_code
== CODE_64BIT
4821 && t
->base_opcode
== 0x90
4822 && operand_type_equal (&i
.types
[0], &acc32
)
4823 && operand_type_equal (&i
.types
[1], &acc32
))
4827 /* If we swap operand in encoding, we either match
4828 the next one or reverse direction of operands. */
4829 if (t
->opcode_modifier
.s
)
4831 else if (t
->opcode_modifier
.d
)
4836 /* If we swap operand in encoding, we match the next one. */
4837 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4841 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4842 if (!operand_type_match (overlap0
, i
.types
[0])
4843 || !operand_type_match (overlap1
, i
.types
[1])
4845 && !operand_type_register_match (overlap0
, i
.types
[0],
4847 overlap1
, i
.types
[1],
4850 /* Check if other direction is valid ... */
4851 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4855 /* Try reversing direction of operands. */
4856 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4857 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4858 if (!operand_type_match (overlap0
, i
.types
[0])
4859 || !operand_type_match (overlap1
, i
.types
[1])
4861 && !operand_type_register_match (overlap0
,
4868 /* Does not match either direction. */
4871 /* found_reverse_match holds which of D or FloatDR
4873 if (t
->opcode_modifier
.d
)
4874 found_reverse_match
= Opcode_D
;
4875 else if (t
->opcode_modifier
.floatd
)
4876 found_reverse_match
= Opcode_FloatD
;
4878 found_reverse_match
= 0;
4879 if (t
->opcode_modifier
.floatr
)
4880 found_reverse_match
|= Opcode_FloatR
;
4884 /* Found a forward 2 operand match here. */
4885 switch (t
->operands
)
4888 overlap4
= operand_type_and (i
.types
[4],
4891 overlap3
= operand_type_and (i
.types
[3],
4894 overlap2
= operand_type_and (i
.types
[2],
4899 switch (t
->operands
)
4902 if (!operand_type_match (overlap4
, i
.types
[4])
4903 || !operand_type_register_match (overlap3
,
4911 if (!operand_type_match (overlap3
, i
.types
[3])
4913 && !operand_type_register_match (overlap2
,
4921 /* Here we make use of the fact that there are no
4922 reverse match 3 operand instructions, and all 3
4923 operand instructions only need to be checked for
4924 register consistency between operands 2 and 3. */
4925 if (!operand_type_match (overlap2
, i
.types
[2])
4927 && !operand_type_register_match (overlap1
,
4937 /* Found either forward/reverse 2, 3 or 4 operand match here:
4938 slip through to break. */
4940 if (!found_cpu_match
)
4942 found_reverse_match
= 0;
4946 /* Check if vector and VEX operands are valid. */
4947 if (check_VecOperands (t
) || VEX_check_operands (t
))
4949 specific_error
= i
.error
;
4953 /* We've found a match; break out of loop. */
4957 if (t
== current_templates
->end
)
4959 /* We found no match. */
4960 const char *err_msg
;
4961 switch (specific_error
? specific_error
: i
.error
)
4965 case operand_size_mismatch
:
4966 err_msg
= _("operand size mismatch");
4968 case operand_type_mismatch
:
4969 err_msg
= _("operand type mismatch");
4971 case register_type_mismatch
:
4972 err_msg
= _("register type mismatch");
4974 case number_of_operands_mismatch
:
4975 err_msg
= _("number of operands mismatch");
4977 case invalid_instruction_suffix
:
4978 err_msg
= _("invalid instruction suffix");
4981 err_msg
= _("constant doesn't fit in 4 bits");
4984 err_msg
= _("only supported with old gcc");
4986 case unsupported_with_intel_mnemonic
:
4987 err_msg
= _("unsupported with Intel mnemonic");
4989 case unsupported_syntax
:
4990 err_msg
= _("unsupported syntax");
4993 as_bad (_("unsupported instruction `%s'"),
4994 current_templates
->start
->name
);
4996 case invalid_vsib_address
:
4997 err_msg
= _("invalid VSIB address");
4999 case invalid_vector_register_set
:
5000 err_msg
= _("mask, index, and destination registers must be distinct");
5002 case unsupported_vector_index_register
:
5003 err_msg
= _("unsupported vector index register");
5005 case unsupported_broadcast
:
5006 err_msg
= _("unsupported broadcast");
5008 case broadcast_not_on_src_operand
:
5009 err_msg
= _("broadcast not on source memory operand");
5011 case broadcast_needed
:
5012 err_msg
= _("broadcast is needed for operand of such type");
5014 case unsupported_masking
:
5015 err_msg
= _("unsupported masking");
5017 case mask_not_on_destination
:
5018 err_msg
= _("mask not on destination operand");
5020 case no_default_mask
:
5021 err_msg
= _("default mask isn't allowed");
5023 case unsupported_rc_sae
:
5024 err_msg
= _("unsupported static rounding/sae");
5026 case rc_sae_operand_not_last_imm
:
5028 err_msg
= _("RC/SAE operand must precede immediate operands");
5030 err_msg
= _("RC/SAE operand must follow immediate operands");
5032 case invalid_register_operand
:
5033 err_msg
= _("invalid register operand");
5036 as_bad (_("%s for `%s'"), err_msg
,
5037 current_templates
->start
->name
);
5041 if (!quiet_warnings
)
5044 && (i
.types
[0].bitfield
.jumpabsolute
5045 != operand_types
[0].bitfield
.jumpabsolute
))
5047 as_warn (_("indirect %s without `*'"), t
->name
);
5050 if (t
->opcode_modifier
.isprefix
5051 && t
->opcode_modifier
.ignoresize
)
5053 /* Warn them that a data or address size prefix doesn't
5054 affect assembly of the next line of code. */
5055 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5059 /* Copy the template we found. */
5062 if (addr_prefix_disp
!= -1)
5063 i
.tm
.operand_types
[addr_prefix_disp
]
5064 = operand_types
[addr_prefix_disp
];
5066 if (found_reverse_match
)
5068 /* If we found a reverse match we must alter the opcode
5069 direction bit. found_reverse_match holds bits to change
5070 (different for int & float insns). */
5072 i
.tm
.base_opcode
^= found_reverse_match
;
5074 i
.tm
.operand_types
[0] = operand_types
[1];
5075 i
.tm
.operand_types
[1] = operand_types
[0];
5084 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5085 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5087 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5089 as_bad (_("`%s' operand %d must use `%ses' segment"),
5095 /* There's only ever one segment override allowed per instruction.
5096 This instruction possibly has a legal segment override on the
5097 second operand, so copy the segment to where non-string
5098 instructions store it, allowing common code. */
5099 i
.seg
[0] = i
.seg
[1];
5101 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5103 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5105 as_bad (_("`%s' operand %d must use `%ses' segment"),
5116 process_suffix (void)
5118 /* If matched instruction specifies an explicit instruction mnemonic
5120 if (i
.tm
.opcode_modifier
.size16
)
5121 i
.suffix
= WORD_MNEM_SUFFIX
;
5122 else if (i
.tm
.opcode_modifier
.size32
)
5123 i
.suffix
= LONG_MNEM_SUFFIX
;
5124 else if (i
.tm
.opcode_modifier
.size64
)
5125 i
.suffix
= QWORD_MNEM_SUFFIX
;
5126 else if (i
.reg_operands
)
5128 /* If there's no instruction mnemonic suffix we try to invent one
5129 based on register operands. */
5132 /* We take i.suffix from the last register operand specified,
5133 Destination register type is more significant than source
5134 register type. crc32 in SSE4.2 prefers source register
5136 if (i
.tm
.base_opcode
== 0xf20f38f1)
5138 if (i
.types
[0].bitfield
.reg16
)
5139 i
.suffix
= WORD_MNEM_SUFFIX
;
5140 else if (i
.types
[0].bitfield
.reg32
)
5141 i
.suffix
= LONG_MNEM_SUFFIX
;
5142 else if (i
.types
[0].bitfield
.reg64
)
5143 i
.suffix
= QWORD_MNEM_SUFFIX
;
5145 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5147 if (i
.types
[0].bitfield
.reg8
)
5148 i
.suffix
= BYTE_MNEM_SUFFIX
;
5155 if (i
.tm
.base_opcode
== 0xf20f38f1
5156 || i
.tm
.base_opcode
== 0xf20f38f0)
5158 /* We have to know the operand size for crc32. */
5159 as_bad (_("ambiguous memory operand size for `%s`"),
5164 for (op
= i
.operands
; --op
>= 0;)
5165 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5167 if (i
.types
[op
].bitfield
.reg8
)
5169 i
.suffix
= BYTE_MNEM_SUFFIX
;
5172 else if (i
.types
[op
].bitfield
.reg16
)
5174 i
.suffix
= WORD_MNEM_SUFFIX
;
5177 else if (i
.types
[op
].bitfield
.reg32
)
5179 i
.suffix
= LONG_MNEM_SUFFIX
;
5182 else if (i
.types
[op
].bitfield
.reg64
)
5184 i
.suffix
= QWORD_MNEM_SUFFIX
;
5190 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5193 && i
.tm
.opcode_modifier
.ignoresize
5194 && i
.tm
.opcode_modifier
.no_bsuf
)
5196 else if (!check_byte_reg ())
5199 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5202 && i
.tm
.opcode_modifier
.ignoresize
5203 && i
.tm
.opcode_modifier
.no_lsuf
)
5205 else if (!check_long_reg ())
5208 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5211 && i
.tm
.opcode_modifier
.ignoresize
5212 && i
.tm
.opcode_modifier
.no_qsuf
)
5214 else if (!check_qword_reg ())
5217 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5220 && i
.tm
.opcode_modifier
.ignoresize
5221 && i
.tm
.opcode_modifier
.no_wsuf
)
5223 else if (!check_word_reg ())
5226 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5227 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5228 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5230 /* Skip if the instruction has x/y/z suffix. match_template
5231 should check if it is a valid suffix. */
5233 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5234 /* Do nothing if the instruction is going to ignore the prefix. */
5239 else if (i
.tm
.opcode_modifier
.defaultsize
5241 /* exclude fldenv/frstor/fsave/fstenv */
5242 && i
.tm
.opcode_modifier
.no_ssuf
)
5244 i
.suffix
= stackop_size
;
5246 else if (intel_syntax
5248 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5249 || i
.tm
.opcode_modifier
.jumpbyte
5250 || i
.tm
.opcode_modifier
.jumpintersegment
5251 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5252 && i
.tm
.extension_opcode
<= 3)))
5257 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5259 i
.suffix
= QWORD_MNEM_SUFFIX
;
5263 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5264 i
.suffix
= LONG_MNEM_SUFFIX
;
5267 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5268 i
.suffix
= WORD_MNEM_SUFFIX
;
5277 if (i
.tm
.opcode_modifier
.w
)
5279 as_bad (_("no instruction mnemonic suffix given and "
5280 "no register operands; can't size instruction"));
5286 unsigned int suffixes
;
5288 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5289 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5291 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5293 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5295 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5297 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5300 /* There are more than suffix matches. */
5301 if (i
.tm
.opcode_modifier
.w
5302 || ((suffixes
& (suffixes
- 1))
5303 && !i
.tm
.opcode_modifier
.defaultsize
5304 && !i
.tm
.opcode_modifier
.ignoresize
))
5306 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5312 /* Change the opcode based on the operand size given by i.suffix;
5313 We don't need to change things for byte insns. */
5316 && i
.suffix
!= BYTE_MNEM_SUFFIX
5317 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5318 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5319 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5321 /* It's not a byte, select word/dword operation. */
5322 if (i
.tm
.opcode_modifier
.w
)
5324 if (i
.tm
.opcode_modifier
.shortform
)
5325 i
.tm
.base_opcode
|= 8;
5327 i
.tm
.base_opcode
|= 1;
5330 /* Now select between word & dword operations via the operand
5331 size prefix, except for instructions that will ignore this
5333 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5335 /* The address size override prefix changes the size of the
5337 if ((flag_code
== CODE_32BIT
5338 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5339 || (flag_code
!= CODE_32BIT
5340 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5341 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5344 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5345 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5346 && !i
.tm
.opcode_modifier
.ignoresize
5347 && !i
.tm
.opcode_modifier
.floatmf
5348 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5349 || (flag_code
== CODE_64BIT
5350 && i
.tm
.opcode_modifier
.jumpbyte
)))
5352 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5354 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5355 prefix
= ADDR_PREFIX_OPCODE
;
5357 if (!add_prefix (prefix
))
5361 /* Set mode64 for an operand. */
5362 if (i
.suffix
== QWORD_MNEM_SUFFIX
5363 && flag_code
== CODE_64BIT
5364 && !i
.tm
.opcode_modifier
.norex64
)
5366 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5367 need rex64. cmpxchg8b is also a special case. */
5368 if (! (i
.operands
== 2
5369 && i
.tm
.base_opcode
== 0x90
5370 && i
.tm
.extension_opcode
== None
5371 && operand_type_equal (&i
.types
[0], &acc64
)
5372 && operand_type_equal (&i
.types
[1], &acc64
))
5373 && ! (i
.operands
== 1
5374 && i
.tm
.base_opcode
== 0xfc7
5375 && i
.tm
.extension_opcode
== 1
5376 && !operand_type_check (i
.types
[0], reg
)
5377 && operand_type_check (i
.types
[0], anymem
)))
5381 /* Size floating point instruction. */
5382 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5383 if (i
.tm
.opcode_modifier
.floatmf
)
5384 i
.tm
.base_opcode
^= 4;
5391 check_byte_reg (void)
5395 for (op
= i
.operands
; --op
>= 0;)
5397 /* If this is an eight bit register, it's OK. If it's the 16 or
5398 32 bit version of an eight bit register, we will just use the
5399 low portion, and that's OK too. */
5400 if (i
.types
[op
].bitfield
.reg8
)
5403 /* I/O port address operands are OK too. */
5404 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5407 /* crc32 doesn't generate this warning. */
5408 if (i
.tm
.base_opcode
== 0xf20f38f0)
5411 if ((i
.types
[op
].bitfield
.reg16
5412 || i
.types
[op
].bitfield
.reg32
5413 || i
.types
[op
].bitfield
.reg64
)
5414 && i
.op
[op
].regs
->reg_num
< 4
5415 /* Prohibit these changes in 64bit mode, since the lowering
5416 would be more complicated. */
5417 && flag_code
!= CODE_64BIT
)
5419 #if REGISTER_WARNINGS
5420 if (!quiet_warnings
)
5421 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5423 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5424 ? REGNAM_AL
- REGNAM_AX
5425 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5427 i
.op
[op
].regs
->reg_name
,
5432 /* Any other register is bad. */
5433 if (i
.types
[op
].bitfield
.reg16
5434 || i
.types
[op
].bitfield
.reg32
5435 || i
.types
[op
].bitfield
.reg64
5436 || i
.types
[op
].bitfield
.regmmx
5437 || i
.types
[op
].bitfield
.regxmm
5438 || i
.types
[op
].bitfield
.regymm
5439 || i
.types
[op
].bitfield
.regzmm
5440 || i
.types
[op
].bitfield
.sreg2
5441 || i
.types
[op
].bitfield
.sreg3
5442 || i
.types
[op
].bitfield
.control
5443 || i
.types
[op
].bitfield
.debug
5444 || i
.types
[op
].bitfield
.test
5445 || i
.types
[op
].bitfield
.floatreg
5446 || i
.types
[op
].bitfield
.floatacc
)
5448 as_bad (_("`%s%s' not allowed with `%s%c'"),
5450 i
.op
[op
].regs
->reg_name
,
5460 check_long_reg (void)
5464 for (op
= i
.operands
; --op
>= 0;)
5465 /* Reject eight bit registers, except where the template requires
5466 them. (eg. movzb) */
5467 if (i
.types
[op
].bitfield
.reg8
5468 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5469 || i
.tm
.operand_types
[op
].bitfield
.reg32
5470 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5472 as_bad (_("`%s%s' not allowed with `%s%c'"),
5474 i
.op
[op
].regs
->reg_name
,
5479 /* Warn if the e prefix on a general reg is missing. */
5480 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5481 && i
.types
[op
].bitfield
.reg16
5482 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5483 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5485 /* Prohibit these changes in the 64bit mode, since the
5486 lowering is more complicated. */
5487 if (flag_code
== CODE_64BIT
)
5489 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5490 register_prefix
, i
.op
[op
].regs
->reg_name
,
5494 #if REGISTER_WARNINGS
5495 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5497 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5498 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5501 /* Warn if the r prefix on a general reg is present. */
5502 else if (i
.types
[op
].bitfield
.reg64
5503 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5504 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5507 && i
.tm
.opcode_modifier
.toqword
5508 && !i
.types
[0].bitfield
.regxmm
)
5510 /* Convert to QWORD. We want REX byte. */
5511 i
.suffix
= QWORD_MNEM_SUFFIX
;
5515 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5516 register_prefix
, i
.op
[op
].regs
->reg_name
,
5525 check_qword_reg (void)
5529 for (op
= i
.operands
; --op
>= 0; )
5530 /* Reject eight bit registers, except where the template requires
5531 them. (eg. movzb) */
5532 if (i
.types
[op
].bitfield
.reg8
5533 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5534 || i
.tm
.operand_types
[op
].bitfield
.reg32
5535 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5537 as_bad (_("`%s%s' not allowed with `%s%c'"),
5539 i
.op
[op
].regs
->reg_name
,
5544 /* Warn if the r prefix on a general reg is missing. */
5545 else if ((i
.types
[op
].bitfield
.reg16
5546 || i
.types
[op
].bitfield
.reg32
)
5547 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5548 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5550 /* Prohibit these changes in the 64bit mode, since the
5551 lowering is more complicated. */
5553 && i
.tm
.opcode_modifier
.todword
5554 && !i
.types
[0].bitfield
.regxmm
)
5556 /* Convert to DWORD. We don't want REX byte. */
5557 i
.suffix
= LONG_MNEM_SUFFIX
;
5561 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5562 register_prefix
, i
.op
[op
].regs
->reg_name
,
5571 check_word_reg (void)
5574 for (op
= i
.operands
; --op
>= 0;)
5575 /* Reject eight bit registers, except where the template requires
5576 them. (eg. movzb) */
5577 if (i
.types
[op
].bitfield
.reg8
5578 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5579 || i
.tm
.operand_types
[op
].bitfield
.reg32
5580 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5582 as_bad (_("`%s%s' not allowed with `%s%c'"),
5584 i
.op
[op
].regs
->reg_name
,
5589 /* Warn if the e or r prefix on a general reg is present. */
5590 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5591 && (i
.types
[op
].bitfield
.reg32
5592 || i
.types
[op
].bitfield
.reg64
)
5593 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5594 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5596 /* Prohibit these changes in the 64bit mode, since the
5597 lowering is more complicated. */
5598 if (flag_code
== CODE_64BIT
)
5600 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5601 register_prefix
, i
.op
[op
].regs
->reg_name
,
5605 #if REGISTER_WARNINGS
5606 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5608 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5609 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5616 update_imm (unsigned int j
)
5618 i386_operand_type overlap
= i
.types
[j
];
5619 if ((overlap
.bitfield
.imm8
5620 || overlap
.bitfield
.imm8s
5621 || overlap
.bitfield
.imm16
5622 || overlap
.bitfield
.imm32
5623 || overlap
.bitfield
.imm32s
5624 || overlap
.bitfield
.imm64
)
5625 && !operand_type_equal (&overlap
, &imm8
)
5626 && !operand_type_equal (&overlap
, &imm8s
)
5627 && !operand_type_equal (&overlap
, &imm16
)
5628 && !operand_type_equal (&overlap
, &imm32
)
5629 && !operand_type_equal (&overlap
, &imm32s
)
5630 && !operand_type_equal (&overlap
, &imm64
))
5634 i386_operand_type temp
;
5636 operand_type_set (&temp
, 0);
5637 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5639 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5640 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5642 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5643 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5644 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5646 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5647 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5650 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5653 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5654 || operand_type_equal (&overlap
, &imm16_32
)
5655 || operand_type_equal (&overlap
, &imm16_32s
))
5657 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5662 if (!operand_type_equal (&overlap
, &imm8
)
5663 && !operand_type_equal (&overlap
, &imm8s
)
5664 && !operand_type_equal (&overlap
, &imm16
)
5665 && !operand_type_equal (&overlap
, &imm32
)
5666 && !operand_type_equal (&overlap
, &imm32s
)
5667 && !operand_type_equal (&overlap
, &imm64
))
5669 as_bad (_("no instruction mnemonic suffix given; "
5670 "can't determine immediate size"));
5674 i
.types
[j
] = overlap
;
5684 /* Update the first 2 immediate operands. */
5685 n
= i
.operands
> 2 ? 2 : i
.operands
;
5688 for (j
= 0; j
< n
; j
++)
5689 if (update_imm (j
) == 0)
5692 /* The 3rd operand can't be immediate operand. */
5693 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5700 bad_implicit_operand (int xmm
)
5702 const char *ireg
= xmm
? "xmm0" : "ymm0";
5705 as_bad (_("the last operand of `%s' must be `%s%s'"),
5706 i
.tm
.name
, register_prefix
, ireg
);
5708 as_bad (_("the first operand of `%s' must be `%s%s'"),
5709 i
.tm
.name
, register_prefix
, ireg
);
5714 process_operands (void)
5716 /* Default segment register this instruction will use for memory
5717 accesses. 0 means unknown. This is only for optimizing out
5718 unnecessary segment overrides. */
5719 const seg_entry
*default_seg
= 0;
5721 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5723 unsigned int dupl
= i
.operands
;
5724 unsigned int dest
= dupl
- 1;
5727 /* The destination must be an xmm register. */
5728 gas_assert (i
.reg_operands
5729 && MAX_OPERANDS
> dupl
5730 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5732 if (i
.tm
.opcode_modifier
.firstxmm0
)
5734 /* The first operand is implicit and must be xmm0. */
5735 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5736 if (register_number (i
.op
[0].regs
) != 0)
5737 return bad_implicit_operand (1);
5739 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5741 /* Keep xmm0 for instructions with VEX prefix and 3
5747 /* We remove the first xmm0 and keep the number of
5748 operands unchanged, which in fact duplicates the
5750 for (j
= 1; j
< i
.operands
; j
++)
5752 i
.op
[j
- 1] = i
.op
[j
];
5753 i
.types
[j
- 1] = i
.types
[j
];
5754 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5758 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5760 gas_assert ((MAX_OPERANDS
- 1) > dupl
5761 && (i
.tm
.opcode_modifier
.vexsources
5764 /* Add the implicit xmm0 for instructions with VEX prefix
5766 for (j
= i
.operands
; j
> 0; j
--)
5768 i
.op
[j
] = i
.op
[j
- 1];
5769 i
.types
[j
] = i
.types
[j
- 1];
5770 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5773 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5774 i
.types
[0] = regxmm
;
5775 i
.tm
.operand_types
[0] = regxmm
;
5778 i
.reg_operands
+= 2;
5783 i
.op
[dupl
] = i
.op
[dest
];
5784 i
.types
[dupl
] = i
.types
[dest
];
5785 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5794 i
.op
[dupl
] = i
.op
[dest
];
5795 i
.types
[dupl
] = i
.types
[dest
];
5796 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5799 if (i
.tm
.opcode_modifier
.immext
)
5802 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5806 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5807 gas_assert (i
.reg_operands
5808 && (operand_type_equal (&i
.types
[0], ®xmm
)
5809 || operand_type_equal (&i
.types
[0], ®ymm
)
5810 || operand_type_equal (&i
.types
[0], ®zmm
)));
5811 if (register_number (i
.op
[0].regs
) != 0)
5812 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5814 for (j
= 1; j
< i
.operands
; j
++)
5816 i
.op
[j
- 1] = i
.op
[j
];
5817 i
.types
[j
- 1] = i
.types
[j
];
5819 /* We need to adjust fields in i.tm since they are used by
5820 build_modrm_byte. */
5821 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5828 else if (i
.tm
.opcode_modifier
.regkludge
)
5830 /* The imul $imm, %reg instruction is converted into
5831 imul $imm, %reg, %reg, and the clr %reg instruction
5832 is converted into xor %reg, %reg. */
5834 unsigned int first_reg_op
;
5836 if (operand_type_check (i
.types
[0], reg
))
5840 /* Pretend we saw the extra register operand. */
5841 gas_assert (i
.reg_operands
== 1
5842 && i
.op
[first_reg_op
+ 1].regs
== 0);
5843 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5844 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5849 if (i
.tm
.opcode_modifier
.shortform
)
5851 if (i
.types
[0].bitfield
.sreg2
5852 || i
.types
[0].bitfield
.sreg3
)
5854 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5855 && i
.op
[0].regs
->reg_num
== 1)
5857 as_bad (_("you can't `pop %scs'"), register_prefix
);
5860 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5861 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5866 /* The register or float register operand is in operand
5870 if (i
.types
[0].bitfield
.floatreg
5871 || operand_type_check (i
.types
[0], reg
))
5875 /* Register goes in low 3 bits of opcode. */
5876 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5877 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5879 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5881 /* Warn about some common errors, but press on regardless.
5882 The first case can be generated by gcc (<= 2.8.1). */
5883 if (i
.operands
== 2)
5885 /* Reversed arguments on faddp, fsubp, etc. */
5886 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5887 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5888 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5892 /* Extraneous `l' suffix on fp insn. */
5893 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5894 register_prefix
, i
.op
[0].regs
->reg_name
);
5899 else if (i
.tm
.opcode_modifier
.modrm
)
5901 /* The opcode is completed (modulo i.tm.extension_opcode which
5902 must be put into the modrm byte). Now, we make the modrm and
5903 index base bytes based on all the info we've collected. */
5905 default_seg
= build_modrm_byte ();
5907 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5911 else if (i
.tm
.opcode_modifier
.isstring
)
5913 /* For the string instructions that allow a segment override
5914 on one of their operands, the default segment is ds. */
5918 if (i
.tm
.base_opcode
== 0x8d /* lea */
5921 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5923 /* If a segment was explicitly specified, and the specified segment
5924 is not the default, use an opcode prefix to select it. If we
5925 never figured out what the default segment is, then default_seg
5926 will be zero at this point, and the specified segment prefix will
5928 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5930 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5936 static const seg_entry
*
5937 build_modrm_byte (void)
5939 const seg_entry
*default_seg
= 0;
5940 unsigned int source
, dest
;
5943 /* The first operand of instructions with VEX prefix and 3 sources
5944 must be VEX_Imm4. */
5945 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5948 unsigned int nds
, reg_slot
;
5951 if (i
.tm
.opcode_modifier
.veximmext
5952 && i
.tm
.opcode_modifier
.immext
)
5954 dest
= i
.operands
- 2;
5955 gas_assert (dest
== 3);
5958 dest
= i
.operands
- 1;
5961 /* There are 2 kinds of instructions:
5962 1. 5 operands: 4 register operands or 3 register operands
5963 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5964 VexW0 or VexW1. The destination must be either XMM, YMM or
5966 2. 4 operands: 4 register operands or 3 register operands
5967 plus 1 memory operand, VexXDS, and VexImmExt */
5968 gas_assert ((i
.reg_operands
== 4
5969 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5970 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5971 && (i
.tm
.opcode_modifier
.veximmext
5972 || (i
.imm_operands
== 1
5973 && i
.types
[0].bitfield
.vec_imm4
5974 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5975 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5976 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5977 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5978 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5980 if (i
.imm_operands
== 0)
5982 /* When there is no immediate operand, generate an 8bit
5983 immediate operand to encode the first operand. */
5984 exp
= &im_expressions
[i
.imm_operands
++];
5985 i
.op
[i
.operands
].imms
= exp
;
5986 i
.types
[i
.operands
] = imm8
;
5988 /* If VexW1 is set, the first operand is the source and
5989 the second operand is encoded in the immediate operand. */
5990 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6001 /* FMA swaps REG and NDS. */
6002 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6010 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6012 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6014 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6016 exp
->X_op
= O_constant
;
6017 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6018 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6022 unsigned int imm_slot
;
6024 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6026 /* If VexW0 is set, the third operand is the source and
6027 the second operand is encoded in the immediate
6034 /* VexW1 is set, the second operand is the source and
6035 the third operand is encoded in the immediate
6041 if (i
.tm
.opcode_modifier
.immext
)
6043 /* When ImmExt is set, the immdiate byte is the last
6045 imm_slot
= i
.operands
- 1;
6053 /* Turn on Imm8 so that output_imm will generate it. */
6054 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6057 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6059 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6061 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6063 i
.op
[imm_slot
].imms
->X_add_number
6064 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6065 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6068 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6069 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6071 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6073 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6078 /* i.reg_operands MUST be the number of real register operands;
6079 implicit registers do not count. If there are 3 register
6080 operands, it must be a instruction with VexNDS. For a
6081 instruction with VexNDD, the destination register is encoded
6082 in VEX prefix. If there are 4 register operands, it must be
6083 a instruction with VEX prefix and 3 sources. */
6084 if (i
.mem_operands
== 0
6085 && ((i
.reg_operands
== 2
6086 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6087 || (i
.reg_operands
== 3
6088 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6089 || (i
.reg_operands
== 4 && vex_3_sources
)))
6097 /* When there are 3 operands, one of them may be immediate,
6098 which may be the first or the last operand. Otherwise,
6099 the first operand must be shift count register (cl) or it
6100 is an instruction with VexNDS. */
6101 gas_assert (i
.imm_operands
== 1
6102 || (i
.imm_operands
== 0
6103 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6104 || i
.types
[0].bitfield
.shiftcount
)));
6105 if (operand_type_check (i
.types
[0], imm
)
6106 || i
.types
[0].bitfield
.shiftcount
)
6112 /* When there are 4 operands, the first two must be 8bit
6113 immediate operands. The source operand will be the 3rd
6116 For instructions with VexNDS, if the first operand
6117 an imm8, the source operand is the 2nd one. If the last
6118 operand is imm8, the source operand is the first one. */
6119 gas_assert ((i
.imm_operands
== 2
6120 && i
.types
[0].bitfield
.imm8
6121 && i
.types
[1].bitfield
.imm8
)
6122 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6123 && i
.imm_operands
== 1
6124 && (i
.types
[0].bitfield
.imm8
6125 || i
.types
[i
.operands
- 1].bitfield
.imm8
6127 if (i
.imm_operands
== 2)
6131 if (i
.types
[0].bitfield
.imm8
)
6138 if (i
.tm
.opcode_modifier
.evex
)
6140 /* For EVEX instructions, when there are 5 operands, the
6141 first one must be immediate operand. If the second one
6142 is immediate operand, the source operand is the 3th
6143 one. If the last one is immediate operand, the source
6144 operand is the 2nd one. */
6145 gas_assert (i
.imm_operands
== 2
6146 && i
.tm
.opcode_modifier
.sae
6147 && operand_type_check (i
.types
[0], imm
));
6148 if (operand_type_check (i
.types
[1], imm
))
6150 else if (operand_type_check (i
.types
[4], imm
))
6164 /* RC/SAE operand could be between DEST and SRC. That happens
6165 when one operand is GPR and the other one is XMM/YMM/ZMM
6167 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6170 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6172 /* For instructions with VexNDS, the register-only source
6173 operand must be 32/64bit integer, XMM, YMM or ZMM
6174 register. It is encoded in VEX prefix. We need to
6175 clear RegMem bit before calling operand_type_equal. */
6177 i386_operand_type op
;
6180 /* Check register-only source operand when two source
6181 operands are swapped. */
6182 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6183 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6191 op
= i
.tm
.operand_types
[vvvv
];
6192 op
.bitfield
.regmem
= 0;
6193 if ((dest
+ 1) >= i
.operands
6194 || (!op
.bitfield
.reg32
6195 && op
.bitfield
.reg64
6196 && !operand_type_equal (&op
, ®xmm
)
6197 && !operand_type_equal (&op
, ®ymm
)
6198 && !operand_type_equal (&op
, ®zmm
)
6199 && !operand_type_equal (&op
, ®mask
)))
6201 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6207 /* One of the register operands will be encoded in the i.tm.reg
6208 field, the other in the combined i.tm.mode and i.tm.regmem
6209 fields. If no form of this instruction supports a memory
6210 destination operand, then we assume the source operand may
6211 sometimes be a memory operand and so we need to store the
6212 destination in the i.rm.reg field. */
6213 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6214 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6216 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6217 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6218 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6220 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6222 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6224 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6229 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6230 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6231 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6233 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6235 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6237 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6240 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6242 if (!i
.types
[0].bitfield
.control
6243 && !i
.types
[1].bitfield
.control
)
6245 i
.rex
&= ~(REX_R
| REX_B
);
6246 add_prefix (LOCK_PREFIX_OPCODE
);
6250 { /* If it's not 2 reg operands... */
6255 unsigned int fake_zero_displacement
= 0;
6258 for (op
= 0; op
< i
.operands
; op
++)
6259 if (operand_type_check (i
.types
[op
], anymem
))
6261 gas_assert (op
< i
.operands
);
6263 if (i
.tm
.opcode_modifier
.vecsib
)
6265 if (i
.index_reg
->reg_num
== RegEiz
6266 || i
.index_reg
->reg_num
== RegRiz
)
6269 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6272 i
.sib
.base
= NO_BASE_REGISTER
;
6273 i
.sib
.scale
= i
.log2_scale_factor
;
6274 /* No Vec_Disp8 if there is no base. */
6275 i
.types
[op
].bitfield
.vec_disp8
= 0;
6276 i
.types
[op
].bitfield
.disp8
= 0;
6277 i
.types
[op
].bitfield
.disp16
= 0;
6278 i
.types
[op
].bitfield
.disp64
= 0;
6279 if (flag_code
!= CODE_64BIT
)
6281 /* Must be 32 bit */
6282 i
.types
[op
].bitfield
.disp32
= 1;
6283 i
.types
[op
].bitfield
.disp32s
= 0;
6287 i
.types
[op
].bitfield
.disp32
= 0;
6288 i
.types
[op
].bitfield
.disp32s
= 1;
6291 i
.sib
.index
= i
.index_reg
->reg_num
;
6292 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6294 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6300 if (i
.base_reg
== 0)
6303 if (!i
.disp_operands
)
6305 fake_zero_displacement
= 1;
6306 /* Instructions with VSIB byte need 32bit displacement
6307 if there is no base register. */
6308 if (i
.tm
.opcode_modifier
.vecsib
)
6309 i
.types
[op
].bitfield
.disp32
= 1;
6311 if (i
.index_reg
== 0)
6313 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6314 /* Operand is just <disp> */
6315 if (flag_code
== CODE_64BIT
)
6317 /* 64bit mode overwrites the 32bit absolute
6318 addressing by RIP relative addressing and
6319 absolute addressing is encoded by one of the
6320 redundant SIB forms. */
6321 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6322 i
.sib
.base
= NO_BASE_REGISTER
;
6323 i
.sib
.index
= NO_INDEX_REGISTER
;
6324 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6325 ? disp32s
: disp32
);
6327 else if ((flag_code
== CODE_16BIT
)
6328 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6330 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6331 i
.types
[op
] = disp16
;
6335 i
.rm
.regmem
= NO_BASE_REGISTER
;
6336 i
.types
[op
] = disp32
;
6339 else if (!i
.tm
.opcode_modifier
.vecsib
)
6341 /* !i.base_reg && i.index_reg */
6342 if (i
.index_reg
->reg_num
== RegEiz
6343 || i
.index_reg
->reg_num
== RegRiz
)
6344 i
.sib
.index
= NO_INDEX_REGISTER
;
6346 i
.sib
.index
= i
.index_reg
->reg_num
;
6347 i
.sib
.base
= NO_BASE_REGISTER
;
6348 i
.sib
.scale
= i
.log2_scale_factor
;
6349 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6350 /* No Vec_Disp8 if there is no base. */
6351 i
.types
[op
].bitfield
.vec_disp8
= 0;
6352 i
.types
[op
].bitfield
.disp8
= 0;
6353 i
.types
[op
].bitfield
.disp16
= 0;
6354 i
.types
[op
].bitfield
.disp64
= 0;
6355 if (flag_code
!= CODE_64BIT
)
6357 /* Must be 32 bit */
6358 i
.types
[op
].bitfield
.disp32
= 1;
6359 i
.types
[op
].bitfield
.disp32s
= 0;
6363 i
.types
[op
].bitfield
.disp32
= 0;
6364 i
.types
[op
].bitfield
.disp32s
= 1;
6366 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6370 /* RIP addressing for 64bit mode. */
6371 else if (i
.base_reg
->reg_num
== RegRip
||
6372 i
.base_reg
->reg_num
== RegEip
)
6374 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6375 i
.rm
.regmem
= NO_BASE_REGISTER
;
6376 i
.types
[op
].bitfield
.disp8
= 0;
6377 i
.types
[op
].bitfield
.disp16
= 0;
6378 i
.types
[op
].bitfield
.disp32
= 0;
6379 i
.types
[op
].bitfield
.disp32s
= 1;
6380 i
.types
[op
].bitfield
.disp64
= 0;
6381 i
.types
[op
].bitfield
.vec_disp8
= 0;
6382 i
.flags
[op
] |= Operand_PCrel
;
6383 if (! i
.disp_operands
)
6384 fake_zero_displacement
= 1;
6386 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6388 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6389 switch (i
.base_reg
->reg_num
)
6392 if (i
.index_reg
== 0)
6394 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6395 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6399 if (i
.index_reg
== 0)
6402 if (operand_type_check (i
.types
[op
], disp
) == 0)
6404 /* fake (%bp) into 0(%bp) */
6405 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6406 i
.types
[op
].bitfield
.vec_disp8
= 1;
6408 i
.types
[op
].bitfield
.disp8
= 1;
6409 fake_zero_displacement
= 1;
6412 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6413 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6415 default: /* (%si) -> 4 or (%di) -> 5 */
6416 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6418 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6420 else /* i.base_reg and 32/64 bit mode */
6422 if (flag_code
== CODE_64BIT
6423 && operand_type_check (i
.types
[op
], disp
))
6425 i386_operand_type temp
;
6426 operand_type_set (&temp
, 0);
6427 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6428 temp
.bitfield
.vec_disp8
6429 = i
.types
[op
].bitfield
.vec_disp8
;
6431 if (i
.prefix
[ADDR_PREFIX
] == 0)
6432 i
.types
[op
].bitfield
.disp32s
= 1;
6434 i
.types
[op
].bitfield
.disp32
= 1;
6437 if (!i
.tm
.opcode_modifier
.vecsib
)
6438 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6439 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6441 i
.sib
.base
= i
.base_reg
->reg_num
;
6442 /* x86-64 ignores REX prefix bit here to avoid decoder
6444 if (!(i
.base_reg
->reg_flags
& RegRex
)
6445 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6446 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6448 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6450 fake_zero_displacement
= 1;
6451 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6452 i
.types
[op
].bitfield
.vec_disp8
= 1;
6454 i
.types
[op
].bitfield
.disp8
= 1;
6456 i
.sib
.scale
= i
.log2_scale_factor
;
6457 if (i
.index_reg
== 0)
6459 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6460 /* <disp>(%esp) becomes two byte modrm with no index
6461 register. We've already stored the code for esp
6462 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6463 Any base register besides %esp will not use the
6464 extra modrm byte. */
6465 i
.sib
.index
= NO_INDEX_REGISTER
;
6467 else if (!i
.tm
.opcode_modifier
.vecsib
)
6469 if (i
.index_reg
->reg_num
== RegEiz
6470 || i
.index_reg
->reg_num
== RegRiz
)
6471 i
.sib
.index
= NO_INDEX_REGISTER
;
6473 i
.sib
.index
= i
.index_reg
->reg_num
;
6474 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6475 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6480 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6481 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6485 if (!fake_zero_displacement
6489 fake_zero_displacement
= 1;
6490 if (i
.disp_encoding
== disp_encoding_8bit
)
6491 i
.types
[op
].bitfield
.disp8
= 1;
6493 i
.types
[op
].bitfield
.disp32
= 1;
6495 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6499 if (fake_zero_displacement
)
6501 /* Fakes a zero displacement assuming that i.types[op]
6502 holds the correct displacement size. */
6505 gas_assert (i
.op
[op
].disps
== 0);
6506 exp
= &disp_expressions
[i
.disp_operands
++];
6507 i
.op
[op
].disps
= exp
;
6508 exp
->X_op
= O_constant
;
6509 exp
->X_add_number
= 0;
6510 exp
->X_add_symbol
= (symbolS
*) 0;
6511 exp
->X_op_symbol
= (symbolS
*) 0;
6519 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6521 if (operand_type_check (i
.types
[0], imm
))
6522 i
.vex
.register_specifier
= NULL
;
6525 /* VEX.vvvv encodes one of the sources when the first
6526 operand is not an immediate. */
6527 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6528 i
.vex
.register_specifier
= i
.op
[0].regs
;
6530 i
.vex
.register_specifier
= i
.op
[1].regs
;
6533 /* Destination is a XMM register encoded in the ModRM.reg
6535 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6536 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6539 /* ModRM.rm and VEX.B encodes the other source. */
6540 if (!i
.mem_operands
)
6544 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6545 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6547 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6549 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6553 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6555 i
.vex
.register_specifier
= i
.op
[2].regs
;
6556 if (!i
.mem_operands
)
6559 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6560 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6564 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6565 (if any) based on i.tm.extension_opcode. Again, we must be
6566 careful to make sure that segment/control/debug/test/MMX
6567 registers are coded into the i.rm.reg field. */
6568 else if (i
.reg_operands
)
6571 unsigned int vex_reg
= ~0;
6573 for (op
= 0; op
< i
.operands
; op
++)
6574 if (i
.types
[op
].bitfield
.reg8
6575 || i
.types
[op
].bitfield
.reg16
6576 || i
.types
[op
].bitfield
.reg32
6577 || i
.types
[op
].bitfield
.reg64
6578 || i
.types
[op
].bitfield
.regmmx
6579 || i
.types
[op
].bitfield
.regxmm
6580 || i
.types
[op
].bitfield
.regymm
6581 || i
.types
[op
].bitfield
.regbnd
6582 || i
.types
[op
].bitfield
.regzmm
6583 || i
.types
[op
].bitfield
.regmask
6584 || i
.types
[op
].bitfield
.sreg2
6585 || i
.types
[op
].bitfield
.sreg3
6586 || i
.types
[op
].bitfield
.control
6587 || i
.types
[op
].bitfield
.debug
6588 || i
.types
[op
].bitfield
.test
)
6593 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6595 /* For instructions with VexNDS, the register-only
6596 source operand is encoded in VEX prefix. */
6597 gas_assert (mem
!= (unsigned int) ~0);
6602 gas_assert (op
< i
.operands
);
6606 /* Check register-only source operand when two source
6607 operands are swapped. */
6608 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6609 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6613 gas_assert (mem
== (vex_reg
+ 1)
6614 && op
< i
.operands
);
6619 gas_assert (vex_reg
< i
.operands
);
6623 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6625 /* For instructions with VexNDD, the register destination
6626 is encoded in VEX prefix. */
6627 if (i
.mem_operands
== 0)
6629 /* There is no memory operand. */
6630 gas_assert ((op
+ 2) == i
.operands
);
6635 /* There are only 2 operands. */
6636 gas_assert (op
< 2 && i
.operands
== 2);
6641 gas_assert (op
< i
.operands
);
6643 if (vex_reg
!= (unsigned int) ~0)
6645 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6647 if (type
->bitfield
.reg32
!= 1
6648 && type
->bitfield
.reg64
!= 1
6649 && !operand_type_equal (type
, ®xmm
)
6650 && !operand_type_equal (type
, ®ymm
)
6651 && !operand_type_equal (type
, ®zmm
)
6652 && !operand_type_equal (type
, ®mask
))
6655 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6658 /* Don't set OP operand twice. */
6661 /* If there is an extension opcode to put here, the
6662 register number must be put into the regmem field. */
6663 if (i
.tm
.extension_opcode
!= None
)
6665 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6666 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6668 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6673 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6674 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6676 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6681 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6682 must set it to 3 to indicate this is a register operand
6683 in the regmem field. */
6684 if (!i
.mem_operands
)
6688 /* Fill in i.rm.reg field with extension opcode (if any). */
6689 if (i
.tm
.extension_opcode
!= None
)
6690 i
.rm
.reg
= i
.tm
.extension_opcode
;
6696 output_branch (void)
6702 relax_substateT subtype
;
6706 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6707 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6710 if (i
.prefix
[DATA_PREFIX
] != 0)
6716 /* Pentium4 branch hints. */
6717 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6718 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6723 if (i
.prefix
[REX_PREFIX
] != 0)
6729 /* BND prefixed jump. */
6730 if (i
.prefix
[BND_PREFIX
] != 0)
6732 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6736 if (i
.prefixes
!= 0 && !intel_syntax
)
6737 as_warn (_("skipping prefixes on this instruction"));
6739 /* It's always a symbol; End frag & setup for relax.
6740 Make sure there is enough room in this frag for the largest
6741 instruction we may generate in md_convert_frag. This is 2
6742 bytes for the opcode and room for the prefix and largest
6744 frag_grow (prefix
+ 2 + 4);
6745 /* Prefix and 1 opcode byte go in fr_fix. */
6746 p
= frag_more (prefix
+ 1);
6747 if (i
.prefix
[DATA_PREFIX
] != 0)
6748 *p
++ = DATA_PREFIX_OPCODE
;
6749 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6750 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6751 *p
++ = i
.prefix
[SEG_PREFIX
];
6752 if (i
.prefix
[REX_PREFIX
] != 0)
6753 *p
++ = i
.prefix
[REX_PREFIX
];
6754 *p
= i
.tm
.base_opcode
;
6756 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6757 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6758 else if (cpu_arch_flags
.bitfield
.cpui386
)
6759 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6761 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6764 sym
= i
.op
[0].disps
->X_add_symbol
;
6765 off
= i
.op
[0].disps
->X_add_number
;
6767 if (i
.op
[0].disps
->X_op
!= O_constant
6768 && i
.op
[0].disps
->X_op
!= O_symbol
)
6770 /* Handle complex expressions. */
6771 sym
= make_expr_symbol (i
.op
[0].disps
);
6775 /* 1 possible extra opcode + 4 byte displacement go in var part.
6776 Pass reloc in fr_var. */
6777 frag_var (rs_machine_dependent
, 5,
6779 || i
.reloc
[0] != NO_RELOC
6780 || (i
.bnd_prefix
== NULL
&& !add_bnd_prefix
))
6782 : BFD_RELOC_X86_64_PC32_BND
),
6783 subtype
, sym
, off
, p
);
6793 if (i
.tm
.opcode_modifier
.jumpbyte
)
6795 /* This is a loop or jecxz type instruction. */
6797 if (i
.prefix
[ADDR_PREFIX
] != 0)
6799 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6802 /* Pentium4 branch hints. */
6803 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6804 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6806 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6815 if (flag_code
== CODE_16BIT
)
6818 if (i
.prefix
[DATA_PREFIX
] != 0)
6820 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6830 if (i
.prefix
[REX_PREFIX
] != 0)
6832 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6836 /* BND prefixed jump. */
6837 if (i
.prefix
[BND_PREFIX
] != 0)
6839 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6843 if (i
.prefixes
!= 0 && !intel_syntax
)
6844 as_warn (_("skipping prefixes on this instruction"));
6846 p
= frag_more (i
.tm
.opcode_length
+ size
);
6847 switch (i
.tm
.opcode_length
)
6850 *p
++ = i
.tm
.base_opcode
>> 8;
6852 *p
++ = i
.tm
.base_opcode
;
6858 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6859 i
.op
[0].disps
, 1, reloc (size
, 1, 1,
6860 (i
.bnd_prefix
!= NULL
6864 /* All jumps handled here are signed, but don't use a signed limit
6865 check for 32 and 16 bit jumps as we want to allow wrap around at
6866 4G and 64k respectively. */
6868 fixP
->fx_signed
= 1;
6872 output_interseg_jump (void)
6880 if (flag_code
== CODE_16BIT
)
6884 if (i
.prefix
[DATA_PREFIX
] != 0)
6890 if (i
.prefix
[REX_PREFIX
] != 0)
6900 if (i
.prefixes
!= 0 && !intel_syntax
)
6901 as_warn (_("skipping prefixes on this instruction"));
6903 /* 1 opcode; 2 segment; offset */
6904 p
= frag_more (prefix
+ 1 + 2 + size
);
6906 if (i
.prefix
[DATA_PREFIX
] != 0)
6907 *p
++ = DATA_PREFIX_OPCODE
;
6909 if (i
.prefix
[REX_PREFIX
] != 0)
6910 *p
++ = i
.prefix
[REX_PREFIX
];
6912 *p
++ = i
.tm
.base_opcode
;
6913 if (i
.op
[1].imms
->X_op
== O_constant
)
6915 offsetT n
= i
.op
[1].imms
->X_add_number
;
6918 && !fits_in_unsigned_word (n
)
6919 && !fits_in_signed_word (n
))
6921 as_bad (_("16-bit jump out of range"));
6924 md_number_to_chars (p
, n
, size
);
6927 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6928 i
.op
[1].imms
, 0, reloc (size
, 0, 0, 0, i
.reloc
[1]));
6929 if (i
.op
[0].imms
->X_op
!= O_constant
)
6930 as_bad (_("can't handle non absolute segment in `%s'"),
6932 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6938 fragS
*insn_start_frag
;
6939 offsetT insn_start_off
;
6941 /* Tie dwarf2 debug info to the address at the start of the insn.
6942 We can't do this after the insn has been output as the current
6943 frag may have been closed off. eg. by frag_var. */
6944 dwarf2_emit_insn (0);
6946 insn_start_frag
= frag_now
;
6947 insn_start_off
= frag_now_fix ();
6950 if (i
.tm
.opcode_modifier
.jump
)
6952 else if (i
.tm
.opcode_modifier
.jumpbyte
6953 || i
.tm
.opcode_modifier
.jumpdword
)
6955 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6956 output_interseg_jump ();
6959 /* Output normal instructions here. */
6963 unsigned int prefix
;
6965 /* Some processors fail on LOCK prefix. This options makes
6966 assembler ignore LOCK prefix and serves as a workaround. */
6967 if (omit_lock_prefix
)
6969 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
6971 i
.prefix
[LOCK_PREFIX
] = 0;
6974 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6975 don't need the explicit prefix. */
6976 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6978 switch (i
.tm
.opcode_length
)
6981 if (i
.tm
.base_opcode
& 0xff000000)
6983 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6988 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6990 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6991 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6994 if (prefix
!= REPE_PREFIX_OPCODE
6995 || (i
.prefix
[REP_PREFIX
]
6996 != REPE_PREFIX_OPCODE
))
6997 add_prefix (prefix
);
7000 add_prefix (prefix
);
7009 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7010 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7011 R_X86_64_GOTTPOFF relocation so that linker can safely
7012 perform IE->LE optimization. */
7013 if (x86_elf_abi
== X86_64_X32_ABI
7015 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7016 && i
.prefix
[REX_PREFIX
] == 0)
7017 add_prefix (REX_OPCODE
);
7020 /* The prefix bytes. */
7021 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7023 FRAG_APPEND_1_CHAR (*q
);
7027 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7032 /* REX byte is encoded in VEX prefix. */
7036 FRAG_APPEND_1_CHAR (*q
);
7039 /* There should be no other prefixes for instructions
7044 /* For EVEX instructions i.vrex should become 0 after
7045 build_evex_prefix. For VEX instructions upper 16 registers
7046 aren't available, so VREX should be 0. */
7049 /* Now the VEX prefix. */
7050 p
= frag_more (i
.vex
.length
);
7051 for (j
= 0; j
< i
.vex
.length
; j
++)
7052 p
[j
] = i
.vex
.bytes
[j
];
7055 /* Now the opcode; be careful about word order here! */
7056 if (i
.tm
.opcode_length
== 1)
7058 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7062 switch (i
.tm
.opcode_length
)
7066 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7067 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7071 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7081 /* Put out high byte first: can't use md_number_to_chars! */
7082 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7083 *p
= i
.tm
.base_opcode
& 0xff;
7086 /* Now the modrm byte and sib byte (if present). */
7087 if (i
.tm
.opcode_modifier
.modrm
)
7089 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7092 /* If i.rm.regmem == ESP (4)
7093 && i.rm.mode != (Register mode)
7095 ==> need second modrm byte. */
7096 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7098 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7099 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7101 | i
.sib
.scale
<< 6));
7104 if (i
.disp_operands
)
7105 output_disp (insn_start_frag
, insn_start_off
);
7108 output_imm (insn_start_frag
, insn_start_off
);
7114 pi ("" /*line*/, &i
);
7116 #endif /* DEBUG386 */
7119 /* Return the size of the displacement operand N. */
7122 disp_size (unsigned int n
)
7126 /* Vec_Disp8 has to be 8bit. */
7127 if (i
.types
[n
].bitfield
.vec_disp8
)
7129 else if (i
.types
[n
].bitfield
.disp64
)
7131 else if (i
.types
[n
].bitfield
.disp8
)
7133 else if (i
.types
[n
].bitfield
.disp16
)
7138 /* Return the size of the immediate operand N. */
7141 imm_size (unsigned int n
)
7144 if (i
.types
[n
].bitfield
.imm64
)
7146 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7148 else if (i
.types
[n
].bitfield
.imm16
)
7154 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7159 for (n
= 0; n
< i
.operands
; n
++)
7161 if (i
.types
[n
].bitfield
.vec_disp8
7162 || operand_type_check (i
.types
[n
], disp
))
7164 if (i
.op
[n
].disps
->X_op
== O_constant
)
7166 int size
= disp_size (n
);
7167 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7169 if (i
.types
[n
].bitfield
.vec_disp8
)
7171 val
= offset_in_range (val
, size
);
7172 p
= frag_more (size
);
7173 md_number_to_chars (p
, val
, size
);
7177 enum bfd_reloc_code_real reloc_type
;
7178 int size
= disp_size (n
);
7179 int sign
= i
.types
[n
].bitfield
.disp32s
;
7180 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7182 /* We can't have 8 bit displacement here. */
7183 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7185 /* The PC relative address is computed relative
7186 to the instruction boundary, so in case immediate
7187 fields follows, we need to adjust the value. */
7188 if (pcrel
&& i
.imm_operands
)
7193 for (n1
= 0; n1
< i
.operands
; n1
++)
7194 if (operand_type_check (i
.types
[n1
], imm
))
7196 /* Only one immediate is allowed for PC
7197 relative address. */
7198 gas_assert (sz
== 0);
7200 i
.op
[n
].disps
->X_add_number
-= sz
;
7202 /* We should find the immediate. */
7203 gas_assert (sz
!= 0);
7206 p
= frag_more (size
);
7207 reloc_type
= reloc (size
, pcrel
, sign
,
7208 (i
.bnd_prefix
!= NULL
7212 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7213 && (((reloc_type
== BFD_RELOC_32
7214 || reloc_type
== BFD_RELOC_X86_64_32S
7215 || (reloc_type
== BFD_RELOC_64
7217 && (i
.op
[n
].disps
->X_op
== O_symbol
7218 || (i
.op
[n
].disps
->X_op
== O_add
7219 && ((symbol_get_value_expression
7220 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7222 || reloc_type
== BFD_RELOC_32_PCREL
))
7226 if (insn_start_frag
== frag_now
)
7227 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7232 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7233 for (fr
= insn_start_frag
->fr_next
;
7234 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7236 add
+= p
- frag_now
->fr_literal
;
7241 reloc_type
= BFD_RELOC_386_GOTPC
;
7242 i
.op
[n
].imms
->X_add_number
+= add
;
7244 else if (reloc_type
== BFD_RELOC_64
)
7245 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7247 /* Don't do the adjustment for x86-64, as there
7248 the pcrel addressing is relative to the _next_
7249 insn, and that is taken care of in other code. */
7250 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7252 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7253 i
.op
[n
].disps
, pcrel
, reloc_type
);
7260 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7265 for (n
= 0; n
< i
.operands
; n
++)
7267 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7268 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7271 if (operand_type_check (i
.types
[n
], imm
))
7273 if (i
.op
[n
].imms
->X_op
== O_constant
)
7275 int size
= imm_size (n
);
7278 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7280 p
= frag_more (size
);
7281 md_number_to_chars (p
, val
, size
);
7285 /* Not absolute_section.
7286 Need a 32-bit fixup (don't support 8bit
7287 non-absolute imms). Try to support other
7289 enum bfd_reloc_code_real reloc_type
;
7290 int size
= imm_size (n
);
7293 if (i
.types
[n
].bitfield
.imm32s
7294 && (i
.suffix
== QWORD_MNEM_SUFFIX
7295 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7300 p
= frag_more (size
);
7301 reloc_type
= reloc (size
, 0, sign
, 0, i
.reloc
[n
]);
7303 /* This is tough to explain. We end up with this one if we
7304 * have operands that look like
7305 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7306 * obtain the absolute address of the GOT, and it is strongly
7307 * preferable from a performance point of view to avoid using
7308 * a runtime relocation for this. The actual sequence of
7309 * instructions often look something like:
7314 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7316 * The call and pop essentially return the absolute address
7317 * of the label .L66 and store it in %ebx. The linker itself
7318 * will ultimately change the first operand of the addl so
7319 * that %ebx points to the GOT, but to keep things simple, the
7320 * .o file must have this operand set so that it generates not
7321 * the absolute address of .L66, but the absolute address of
7322 * itself. This allows the linker itself simply treat a GOTPC
7323 * relocation as asking for a pcrel offset to the GOT to be
7324 * added in, and the addend of the relocation is stored in the
7325 * operand field for the instruction itself.
7327 * Our job here is to fix the operand so that it would add
7328 * the correct offset so that %ebx would point to itself. The
7329 * thing that is tricky is that .-.L66 will point to the
7330 * beginning of the instruction, so we need to further modify
7331 * the operand so that it will point to itself. There are
7332 * other cases where you have something like:
7334 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7336 * and here no correction would be required. Internally in
7337 * the assembler we treat operands of this form as not being
7338 * pcrel since the '.' is explicitly mentioned, and I wonder
7339 * whether it would simplify matters to do it this way. Who
7340 * knows. In earlier versions of the PIC patches, the
7341 * pcrel_adjust field was used to store the correction, but
7342 * since the expression is not pcrel, I felt it would be
7343 * confusing to do it this way. */
7345 if ((reloc_type
== BFD_RELOC_32
7346 || reloc_type
== BFD_RELOC_X86_64_32S
7347 || reloc_type
== BFD_RELOC_64
)
7349 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7350 && (i
.op
[n
].imms
->X_op
== O_symbol
7351 || (i
.op
[n
].imms
->X_op
== O_add
7352 && ((symbol_get_value_expression
7353 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7358 if (insn_start_frag
== frag_now
)
7359 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7364 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7365 for (fr
= insn_start_frag
->fr_next
;
7366 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7368 add
+= p
- frag_now
->fr_literal
;
7372 reloc_type
= BFD_RELOC_386_GOTPC
;
7374 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7376 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7377 i
.op
[n
].imms
->X_add_number
+= add
;
7379 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7380 i
.op
[n
].imms
, 0, reloc_type
);
7386 /* x86_cons_fix_new is called via the expression parsing code when a
7387 reloc is needed. We use this hook to get the correct .got reloc. */
7388 static int cons_sign
= -1;
7391 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7392 expressionS
*exp
, bfd_reloc_code_real_type r
)
7394 r
= reloc (len
, 0, cons_sign
, 0, r
);
7397 if (exp
->X_op
== O_secrel
)
7399 exp
->X_op
= O_symbol
;
7400 r
= BFD_RELOC_32_SECREL
;
7404 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7407 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7408 purpose of the `.dc.a' internal pseudo-op. */
7411 x86_address_bytes (void)
7413 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7415 return stdoutput
->arch_info
->bits_per_address
/ 8;
7418 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7420 # define lex_got(reloc, adjust, types, bnd_prefix) NULL
7422 /* Parse operands of the form
7423 <symbol>@GOTOFF+<nnn>
7424 and similar .plt or .got references.
7426 If we find one, set up the correct relocation in RELOC and copy the
7427 input string, minus the `@GOTOFF' into a malloc'd buffer for
7428 parsing by the calling routine. Return this buffer, and if ADJUST
7429 is non-null set it to the length of the string we removed from the
7430 input line. Otherwise return NULL. */
7432 lex_got (enum bfd_reloc_code_real
*rel
,
7434 i386_operand_type
*types
,
7437 /* Some of the relocations depend on the size of what field is to
7438 be relocated. But in our callers i386_immediate and i386_displacement
7439 we don't yet know the operand size (this will be set by insn
7440 matching). Hence we record the word32 relocation here,
7441 and adjust the reloc according to the real size in reloc(). */
7442 static const struct {
7445 const enum bfd_reloc_code_real rel
[2];
7446 const i386_operand_type types64
;
7448 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7449 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7451 OPERAND_TYPE_IMM32_64
},
7453 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7454 BFD_RELOC_X86_64_PLTOFF64
},
7455 OPERAND_TYPE_IMM64
},
7456 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7457 BFD_RELOC_X86_64_PLT32
},
7458 OPERAND_TYPE_IMM32_32S_DISP32
},
7459 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7460 BFD_RELOC_X86_64_GOTPLT64
},
7461 OPERAND_TYPE_IMM64_DISP64
},
7462 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7463 BFD_RELOC_X86_64_GOTOFF64
},
7464 OPERAND_TYPE_IMM64_DISP64
},
7465 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7466 BFD_RELOC_X86_64_GOTPCREL
},
7467 OPERAND_TYPE_IMM32_32S_DISP32
},
7468 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7469 BFD_RELOC_X86_64_TLSGD
},
7470 OPERAND_TYPE_IMM32_32S_DISP32
},
7471 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7472 _dummy_first_bfd_reloc_code_real
},
7473 OPERAND_TYPE_NONE
},
7474 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7475 BFD_RELOC_X86_64_TLSLD
},
7476 OPERAND_TYPE_IMM32_32S_DISP32
},
7477 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7478 BFD_RELOC_X86_64_GOTTPOFF
},
7479 OPERAND_TYPE_IMM32_32S_DISP32
},
7480 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7481 BFD_RELOC_X86_64_TPOFF32
},
7482 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7483 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7484 _dummy_first_bfd_reloc_code_real
},
7485 OPERAND_TYPE_NONE
},
7486 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7487 BFD_RELOC_X86_64_DTPOFF32
},
7488 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7489 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7490 _dummy_first_bfd_reloc_code_real
},
7491 OPERAND_TYPE_NONE
},
7492 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7493 _dummy_first_bfd_reloc_code_real
},
7494 OPERAND_TYPE_NONE
},
7495 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7496 BFD_RELOC_X86_64_GOT32
},
7497 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7498 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7499 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7500 OPERAND_TYPE_IMM32_32S_DISP32
},
7501 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7502 BFD_RELOC_X86_64_TLSDESC_CALL
},
7503 OPERAND_TYPE_IMM32_32S_DISP32
},
7508 #if defined (OBJ_MAYBE_ELF)
7513 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7514 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7517 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7519 int len
= gotrel
[j
].len
;
7520 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7522 if (gotrel
[j
].rel
[object_64bit
] != 0)
7525 char *tmpbuf
, *past_reloc
;
7527 *rel
= gotrel
[j
].rel
[object_64bit
];
7531 if (flag_code
!= CODE_64BIT
)
7533 types
->bitfield
.imm32
= 1;
7534 types
->bitfield
.disp32
= 1;
7537 *types
= gotrel
[j
].types64
;
7540 if (j
!= 0 && GOT_symbol
== NULL
)
7541 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7543 /* The length of the first part of our input line. */
7544 first
= cp
- input_line_pointer
;
7546 /* The second part goes from after the reloc token until
7547 (and including) an end_of_line char or comma. */
7548 past_reloc
= cp
+ 1 + len
;
7550 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7552 second
= cp
+ 1 - past_reloc
;
7554 /* Allocate and copy string. The trailing NUL shouldn't
7555 be necessary, but be safe. */
7556 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7557 memcpy (tmpbuf
, input_line_pointer
, first
);
7558 if (second
!= 0 && *past_reloc
!= ' ')
7559 /* Replace the relocation token with ' ', so that
7560 errors like foo@GOTOFF1 will be detected. */
7561 tmpbuf
[first
++] = ' ';
7563 /* Increment length by 1 if the relocation token is
7568 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7569 tmpbuf
[first
+ second
] = '\0';
7570 if (bnd_prefix
&& *rel
== BFD_RELOC_X86_64_PLT32
)
7571 *rel
= BFD_RELOC_X86_64_PLT32_BND
;
7575 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7576 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7581 /* Might be a symbol version string. Don't as_bad here. */
7590 /* Parse operands of the form
7591 <symbol>@SECREL32+<nnn>
7593 If we find one, set up the correct relocation in RELOC and copy the
7594 input string, minus the `@SECREL32' into a malloc'd buffer for
7595 parsing by the calling routine. Return this buffer, and if ADJUST
7596 is non-null set it to the length of the string we removed from the
7597 input line. Otherwise return NULL.
7599 This function is copied from the ELF version above adjusted for PE targets. */
7602 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7603 int *adjust ATTRIBUTE_UNUSED
,
7604 i386_operand_type
*types
,
7605 int bnd_prefix ATTRIBUTE_UNUSED
)
7611 const enum bfd_reloc_code_real rel
[2];
7612 const i386_operand_type types64
;
7616 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7617 BFD_RELOC_32_SECREL
},
7618 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7624 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7625 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7628 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7630 int len
= gotrel
[j
].len
;
7632 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7634 if (gotrel
[j
].rel
[object_64bit
] != 0)
7637 char *tmpbuf
, *past_reloc
;
7639 *rel
= gotrel
[j
].rel
[object_64bit
];
7645 if (flag_code
!= CODE_64BIT
)
7647 types
->bitfield
.imm32
= 1;
7648 types
->bitfield
.disp32
= 1;
7651 *types
= gotrel
[j
].types64
;
7654 /* The length of the first part of our input line. */
7655 first
= cp
- input_line_pointer
;
7657 /* The second part goes from after the reloc token until
7658 (and including) an end_of_line char or comma. */
7659 past_reloc
= cp
+ 1 + len
;
7661 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7663 second
= cp
+ 1 - past_reloc
;
7665 /* Allocate and copy string. The trailing NUL shouldn't
7666 be necessary, but be safe. */
7667 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7668 memcpy (tmpbuf
, input_line_pointer
, first
);
7669 if (second
!= 0 && *past_reloc
!= ' ')
7670 /* Replace the relocation token with ' ', so that
7671 errors like foo@SECLREL321 will be detected. */
7672 tmpbuf
[first
++] = ' ';
7673 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7674 tmpbuf
[first
+ second
] = '\0';
7678 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7679 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7684 /* Might be a symbol version string. Don't as_bad here. */
7690 bfd_reloc_code_real_type
7691 x86_cons (expressionS
*exp
, int size
)
7693 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7695 intel_syntax
= -intel_syntax
;
7698 if (size
== 4 || (object_64bit
&& size
== 8))
7700 /* Handle @GOTOFF and the like in an expression. */
7702 char *gotfree_input_line
;
7705 save
= input_line_pointer
;
7706 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
, 0);
7707 if (gotfree_input_line
)
7708 input_line_pointer
= gotfree_input_line
;
7712 if (gotfree_input_line
)
7714 /* expression () has merrily parsed up to the end of line,
7715 or a comma - in the wrong buffer. Transfer how far
7716 input_line_pointer has moved to the right buffer. */
7717 input_line_pointer
= (save
7718 + (input_line_pointer
- gotfree_input_line
)
7720 free (gotfree_input_line
);
7721 if (exp
->X_op
== O_constant
7722 || exp
->X_op
== O_absent
7723 || exp
->X_op
== O_illegal
7724 || exp
->X_op
== O_register
7725 || exp
->X_op
== O_big
)
7727 char c
= *input_line_pointer
;
7728 *input_line_pointer
= 0;
7729 as_bad (_("missing or invalid expression `%s'"), save
);
7730 *input_line_pointer
= c
;
7737 intel_syntax
= -intel_syntax
;
7740 i386_intel_simplify (exp
);
7746 signed_cons (int size
)
7748 if (flag_code
== CODE_64BIT
)
7756 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7763 if (exp
.X_op
== O_symbol
)
7764 exp
.X_op
= O_secrel
;
7766 emit_expr (&exp
, 4);
7768 while (*input_line_pointer
++ == ',');
7770 input_line_pointer
--;
7771 demand_empty_rest_of_line ();
7775 /* Handle Vector operations. */
7778 check_VecOperations (char *op_string
, char *op_end
)
7780 const reg_entry
*mask
;
7785 && (op_end
== NULL
|| op_string
< op_end
))
7788 if (*op_string
== '{')
7792 /* Check broadcasts. */
7793 if (strncmp (op_string
, "1to", 3) == 0)
7798 goto duplicated_vec_op
;
7801 if (*op_string
== '8')
7802 bcst_type
= BROADCAST_1TO8
;
7803 else if (*op_string
== '4')
7804 bcst_type
= BROADCAST_1TO4
;
7805 else if (*op_string
== '2')
7806 bcst_type
= BROADCAST_1TO2
;
7807 else if (*op_string
== '1'
7808 && *(op_string
+1) == '6')
7810 bcst_type
= BROADCAST_1TO16
;
7815 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7820 broadcast_op
.type
= bcst_type
;
7821 broadcast_op
.operand
= this_operand
;
7822 i
.broadcast
= &broadcast_op
;
7824 /* Check masking operation. */
7825 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7827 /* k0 can't be used for write mask. */
7828 if (mask
->reg_num
== 0)
7830 as_bad (_("`%s' can't be used for write mask"),
7837 mask_op
.mask
= mask
;
7838 mask_op
.zeroing
= 0;
7839 mask_op
.operand
= this_operand
;
7845 goto duplicated_vec_op
;
7847 i
.mask
->mask
= mask
;
7849 /* Only "{z}" is allowed here. No need to check
7850 zeroing mask explicitly. */
7851 if (i
.mask
->operand
!= this_operand
)
7853 as_bad (_("invalid write mask `%s'"), saved
);
7860 /* Check zeroing-flag for masking operation. */
7861 else if (*op_string
== 'z')
7865 mask_op
.mask
= NULL
;
7866 mask_op
.zeroing
= 1;
7867 mask_op
.operand
= this_operand
;
7872 if (i
.mask
->zeroing
)
7875 as_bad (_("duplicated `%s'"), saved
);
7879 i
.mask
->zeroing
= 1;
7881 /* Only "{%k}" is allowed here. No need to check mask
7882 register explicitly. */
7883 if (i
.mask
->operand
!= this_operand
)
7885 as_bad (_("invalid zeroing-masking `%s'"),
7894 goto unknown_vec_op
;
7896 if (*op_string
!= '}')
7898 as_bad (_("missing `}' in `%s'"), saved
);
7905 /* We don't know this one. */
7906 as_bad (_("unknown vector operation: `%s'"), saved
);
7914 i386_immediate (char *imm_start
)
7916 char *save_input_line_pointer
;
7917 char *gotfree_input_line
;
7920 i386_operand_type types
;
7922 operand_type_set (&types
, ~0);
7924 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7926 as_bad (_("at most %d immediate operands are allowed"),
7927 MAX_IMMEDIATE_OPERANDS
);
7931 exp
= &im_expressions
[i
.imm_operands
++];
7932 i
.op
[this_operand
].imms
= exp
;
7934 if (is_space_char (*imm_start
))
7937 save_input_line_pointer
= input_line_pointer
;
7938 input_line_pointer
= imm_start
;
7940 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
,
7941 (i
.bnd_prefix
!= NULL
7942 || add_bnd_prefix
));
7943 if (gotfree_input_line
)
7944 input_line_pointer
= gotfree_input_line
;
7946 exp_seg
= expression (exp
);
7950 /* Handle vector operations. */
7951 if (*input_line_pointer
== '{')
7953 input_line_pointer
= check_VecOperations (input_line_pointer
,
7955 if (input_line_pointer
== NULL
)
7959 if (*input_line_pointer
)
7960 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7962 input_line_pointer
= save_input_line_pointer
;
7963 if (gotfree_input_line
)
7965 free (gotfree_input_line
);
7967 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7968 exp
->X_op
= O_illegal
;
7971 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7975 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7976 i386_operand_type types
, const char *imm_start
)
7978 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7981 as_bad (_("missing or invalid immediate expression `%s'"),
7985 else if (exp
->X_op
== O_constant
)
7987 /* Size it properly later. */
7988 i
.types
[this_operand
].bitfield
.imm64
= 1;
7989 /* If not 64bit, sign extend val. */
7990 if (flag_code
!= CODE_64BIT
7991 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7993 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7995 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7996 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7997 && exp_seg
!= absolute_section
7998 && exp_seg
!= text_section
7999 && exp_seg
!= data_section
8000 && exp_seg
!= bss_section
8001 && exp_seg
!= undefined_section
8002 && !bfd_is_com_section (exp_seg
))
8004 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8008 else if (!intel_syntax
&& exp_seg
== reg_section
)
8011 as_bad (_("illegal immediate register operand %s"), imm_start
);
8016 /* This is an address. The size of the address will be
8017 determined later, depending on destination register,
8018 suffix, or the default for the section. */
8019 i
.types
[this_operand
].bitfield
.imm8
= 1;
8020 i
.types
[this_operand
].bitfield
.imm16
= 1;
8021 i
.types
[this_operand
].bitfield
.imm32
= 1;
8022 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8023 i
.types
[this_operand
].bitfield
.imm64
= 1;
8024 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8032 i386_scale (char *scale
)
8035 char *save
= input_line_pointer
;
8037 input_line_pointer
= scale
;
8038 val
= get_absolute_expression ();
8043 i
.log2_scale_factor
= 0;
8046 i
.log2_scale_factor
= 1;
8049 i
.log2_scale_factor
= 2;
8052 i
.log2_scale_factor
= 3;
8056 char sep
= *input_line_pointer
;
8058 *input_line_pointer
= '\0';
8059 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8061 *input_line_pointer
= sep
;
8062 input_line_pointer
= save
;
8066 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8068 as_warn (_("scale factor of %d without an index register"),
8069 1 << i
.log2_scale_factor
);
8070 i
.log2_scale_factor
= 0;
8072 scale
= input_line_pointer
;
8073 input_line_pointer
= save
;
8078 i386_displacement (char *disp_start
, char *disp_end
)
8082 char *save_input_line_pointer
;
8083 char *gotfree_input_line
;
8085 i386_operand_type bigdisp
, types
= anydisp
;
8088 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8090 as_bad (_("at most %d displacement operands are allowed"),
8091 MAX_MEMORY_OPERANDS
);
8095 operand_type_set (&bigdisp
, 0);
8096 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8097 || (!current_templates
->start
->opcode_modifier
.jump
8098 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8100 bigdisp
.bitfield
.disp32
= 1;
8101 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8102 if (flag_code
== CODE_64BIT
)
8106 bigdisp
.bitfield
.disp32s
= 1;
8107 bigdisp
.bitfield
.disp64
= 1;
8110 else if ((flag_code
== CODE_16BIT
) ^ override
)
8112 bigdisp
.bitfield
.disp32
= 0;
8113 bigdisp
.bitfield
.disp16
= 1;
8118 /* For PC-relative branches, the width of the displacement
8119 is dependent upon data size, not address size. */
8120 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8121 if (flag_code
== CODE_64BIT
)
8123 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8124 bigdisp
.bitfield
.disp16
= 1;
8127 bigdisp
.bitfield
.disp32
= 1;
8128 bigdisp
.bitfield
.disp32s
= 1;
8134 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8136 : LONG_MNEM_SUFFIX
));
8137 bigdisp
.bitfield
.disp32
= 1;
8138 if ((flag_code
== CODE_16BIT
) ^ override
)
8140 bigdisp
.bitfield
.disp32
= 0;
8141 bigdisp
.bitfield
.disp16
= 1;
8145 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8148 exp
= &disp_expressions
[i
.disp_operands
];
8149 i
.op
[this_operand
].disps
= exp
;
8151 save_input_line_pointer
= input_line_pointer
;
8152 input_line_pointer
= disp_start
;
8153 END_STRING_AND_SAVE (disp_end
);
8155 #ifndef GCC_ASM_O_HACK
8156 #define GCC_ASM_O_HACK 0
8159 END_STRING_AND_SAVE (disp_end
+ 1);
8160 if (i
.types
[this_operand
].bitfield
.baseIndex
8161 && displacement_string_end
[-1] == '+')
8163 /* This hack is to avoid a warning when using the "o"
8164 constraint within gcc asm statements.
8167 #define _set_tssldt_desc(n,addr,limit,type) \
8168 __asm__ __volatile__ ( \
8170 "movw %w1,2+%0\n\t" \
8172 "movb %b1,4+%0\n\t" \
8173 "movb %4,5+%0\n\t" \
8174 "movb $0,6+%0\n\t" \
8175 "movb %h1,7+%0\n\t" \
8177 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8179 This works great except that the output assembler ends
8180 up looking a bit weird if it turns out that there is
8181 no offset. You end up producing code that looks like:
8194 So here we provide the missing zero. */
8196 *displacement_string_end
= '0';
8199 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
,
8200 (i
.bnd_prefix
!= NULL
8201 || add_bnd_prefix
));
8202 if (gotfree_input_line
)
8203 input_line_pointer
= gotfree_input_line
;
8205 exp_seg
= expression (exp
);
8208 if (*input_line_pointer
)
8209 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8211 RESTORE_END_STRING (disp_end
+ 1);
8213 input_line_pointer
= save_input_line_pointer
;
8214 if (gotfree_input_line
)
8216 free (gotfree_input_line
);
8218 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8219 exp
->X_op
= O_illegal
;
8222 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8224 RESTORE_END_STRING (disp_end
);
8230 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8231 i386_operand_type types
, const char *disp_start
)
8233 i386_operand_type bigdisp
;
8236 /* We do this to make sure that the section symbol is in
8237 the symbol table. We will ultimately change the relocation
8238 to be relative to the beginning of the section. */
8239 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8240 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8241 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8243 if (exp
->X_op
!= O_symbol
)
8246 if (S_IS_LOCAL (exp
->X_add_symbol
)
8247 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8248 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8249 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8250 exp
->X_op
= O_subtract
;
8251 exp
->X_op_symbol
= GOT_symbol
;
8252 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8253 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8254 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8255 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8257 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8260 else if (exp
->X_op
== O_absent
8261 || exp
->X_op
== O_illegal
8262 || exp
->X_op
== O_big
)
8265 as_bad (_("missing or invalid displacement expression `%s'"),
8270 else if (flag_code
== CODE_64BIT
8271 && !i
.prefix
[ADDR_PREFIX
]
8272 && exp
->X_op
== O_constant
)
8274 /* Since displacement is signed extended to 64bit, don't allow
8275 disp32 and turn off disp32s if they are out of range. */
8276 i
.types
[this_operand
].bitfield
.disp32
= 0;
8277 if (!fits_in_signed_long (exp
->X_add_number
))
8279 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8280 if (i
.types
[this_operand
].bitfield
.baseindex
)
8282 as_bad (_("0x%lx out range of signed 32bit displacement"),
8283 (long) exp
->X_add_number
);
8289 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8290 else if (exp
->X_op
!= O_constant
8291 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8292 && exp_seg
!= absolute_section
8293 && exp_seg
!= text_section
8294 && exp_seg
!= data_section
8295 && exp_seg
!= bss_section
8296 && exp_seg
!= undefined_section
8297 && !bfd_is_com_section (exp_seg
))
8299 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8304 /* Check if this is a displacement only operand. */
8305 bigdisp
= i
.types
[this_operand
];
8306 bigdisp
.bitfield
.disp8
= 0;
8307 bigdisp
.bitfield
.disp16
= 0;
8308 bigdisp
.bitfield
.disp32
= 0;
8309 bigdisp
.bitfield
.disp32s
= 0;
8310 bigdisp
.bitfield
.disp64
= 0;
8311 if (operand_type_all_zero (&bigdisp
))
8312 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8318 /* Make sure the memory operand we've been dealt is valid.
8319 Return 1 on success, 0 on a failure. */
8322 i386_index_check (const char *operand_string
)
8324 const char *kind
= "base/index";
8325 enum flag_code addr_mode
;
8327 if (i
.prefix
[ADDR_PREFIX
])
8328 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8331 addr_mode
= flag_code
;
8333 #if INFER_ADDR_PREFIX
8334 if (i
.mem_operands
== 0)
8336 /* Infer address prefix from the first memory operand. */
8337 const reg_entry
*addr_reg
= i
.base_reg
;
8339 if (addr_reg
== NULL
)
8340 addr_reg
= i
.index_reg
;
8344 if (addr_reg
->reg_num
== RegEip
8345 || addr_reg
->reg_num
== RegEiz
8346 || addr_reg
->reg_type
.bitfield
.reg32
)
8347 addr_mode
= CODE_32BIT
;
8348 else if (flag_code
!= CODE_64BIT
8349 && addr_reg
->reg_type
.bitfield
.reg16
)
8350 addr_mode
= CODE_16BIT
;
8352 if (addr_mode
!= flag_code
)
8354 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8356 /* Change the size of any displacement too. At most one
8357 of Disp16 or Disp32 is set.
8358 FIXME. There doesn't seem to be any real need for
8359 separate Disp16 and Disp32 flags. The same goes for
8360 Imm16 and Imm32. Removing them would probably clean
8361 up the code quite a lot. */
8362 if (flag_code
!= CODE_64BIT
8363 && (i
.types
[this_operand
].bitfield
.disp16
8364 || i
.types
[this_operand
].bitfield
.disp32
))
8365 i
.types
[this_operand
]
8366 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8373 if (current_templates
->start
->opcode_modifier
.isstring
8374 && !current_templates
->start
->opcode_modifier
.immext
8375 && (current_templates
->end
[-1].opcode_modifier
.isstring
8378 /* Memory operands of string insns are special in that they only allow
8379 a single register (rDI, rSI, or rBX) as their memory address. */
8380 const reg_entry
*expected_reg
;
8381 static const char *di_si
[][2] =
8387 static const char *bx
[] = { "ebx", "bx", "rbx" };
8389 kind
= "string address";
8391 if (current_templates
->start
->opcode_modifier
.w
)
8393 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8395 if (!type
.bitfield
.baseindex
8396 || ((!i
.mem_operands
!= !intel_syntax
)
8397 && current_templates
->end
[-1].operand_types
[1]
8398 .bitfield
.baseindex
))
8399 type
= current_templates
->end
[-1].operand_types
[1];
8400 expected_reg
= hash_find (reg_hash
,
8401 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8405 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8407 if (i
.base_reg
!= expected_reg
8409 || operand_type_check (i
.types
[this_operand
], disp
))
8411 /* The second memory operand must have the same size as
8415 && !((addr_mode
== CODE_64BIT
8416 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8417 || (addr_mode
== CODE_32BIT
8418 ? i
.base_reg
->reg_type
.bitfield
.reg32
8419 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8422 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8424 intel_syntax
? '[' : '(',
8426 expected_reg
->reg_name
,
8427 intel_syntax
? ']' : ')');
8434 as_bad (_("`%s' is not a valid %s expression"),
8435 operand_string
, kind
);
8440 if (addr_mode
!= CODE_16BIT
)
8442 /* 32-bit/64-bit checks. */
8444 && (addr_mode
== CODE_64BIT
8445 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8446 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8448 || (i
.base_reg
->reg_num
8449 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8451 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8452 && !i
.index_reg
->reg_type
.bitfield
.regymm
8453 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8454 && ((addr_mode
== CODE_64BIT
8455 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8456 || i
.index_reg
->reg_num
== RegRiz
)
8457 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8458 || i
.index_reg
->reg_num
== RegEiz
))
8459 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8464 /* 16-bit checks. */
8466 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8467 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8469 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8470 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8472 && i
.base_reg
->reg_num
< 6
8473 && i
.index_reg
->reg_num
>= 6
8474 && i
.log2_scale_factor
== 0))))
8481 /* Handle vector immediates. */
8484 RC_SAE_immediate (const char *imm_start
)
8486 unsigned int match_found
, j
;
8487 const char *pstr
= imm_start
;
8495 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8497 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8501 rc_op
.type
= RC_NamesTable
[j
].type
;
8502 rc_op
.operand
= this_operand
;
8503 i
.rounding
= &rc_op
;
8507 as_bad (_("duplicated `%s'"), imm_start
);
8510 pstr
+= RC_NamesTable
[j
].len
;
8520 as_bad (_("Missing '}': '%s'"), imm_start
);
8523 /* RC/SAE immediate string should contain nothing more. */;
8526 as_bad (_("Junk after '}': '%s'"), imm_start
);
8530 exp
= &im_expressions
[i
.imm_operands
++];
8531 i
.op
[this_operand
].imms
= exp
;
8533 exp
->X_op
= O_constant
;
8534 exp
->X_add_number
= 0;
8535 exp
->X_add_symbol
= (symbolS
*) 0;
8536 exp
->X_op_symbol
= (symbolS
*) 0;
8538 i
.types
[this_operand
].bitfield
.imm8
= 1;
8542 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8546 i386_att_operand (char *operand_string
)
8550 char *op_string
= operand_string
;
8552 if (is_space_char (*op_string
))
8555 /* We check for an absolute prefix (differentiating,
8556 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8557 if (*op_string
== ABSOLUTE_PREFIX
)
8560 if (is_space_char (*op_string
))
8562 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8565 /* Check if operand is a register. */
8566 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8568 i386_operand_type temp
;
8570 /* Check for a segment override by searching for ':' after a
8571 segment register. */
8573 if (is_space_char (*op_string
))
8575 if (*op_string
== ':'
8576 && (r
->reg_type
.bitfield
.sreg2
8577 || r
->reg_type
.bitfield
.sreg3
))
8582 i
.seg
[i
.mem_operands
] = &es
;
8585 i
.seg
[i
.mem_operands
] = &cs
;
8588 i
.seg
[i
.mem_operands
] = &ss
;
8591 i
.seg
[i
.mem_operands
] = &ds
;
8594 i
.seg
[i
.mem_operands
] = &fs
;
8597 i
.seg
[i
.mem_operands
] = &gs
;
8601 /* Skip the ':' and whitespace. */
8603 if (is_space_char (*op_string
))
8606 if (!is_digit_char (*op_string
)
8607 && !is_identifier_char (*op_string
)
8608 && *op_string
!= '('
8609 && *op_string
!= ABSOLUTE_PREFIX
)
8611 as_bad (_("bad memory operand `%s'"), op_string
);
8614 /* Handle case of %es:*foo. */
8615 if (*op_string
== ABSOLUTE_PREFIX
)
8618 if (is_space_char (*op_string
))
8620 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8622 goto do_memory_reference
;
8625 /* Handle vector operations. */
8626 if (*op_string
== '{')
8628 op_string
= check_VecOperations (op_string
, NULL
);
8629 if (op_string
== NULL
)
8635 as_bad (_("junk `%s' after register"), op_string
);
8639 temp
.bitfield
.baseindex
= 0;
8640 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8642 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8643 i
.op
[this_operand
].regs
= r
;
8646 else if (*op_string
== REGISTER_PREFIX
)
8648 as_bad (_("bad register name `%s'"), op_string
);
8651 else if (*op_string
== IMMEDIATE_PREFIX
)
8654 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8656 as_bad (_("immediate operand illegal with absolute jump"));
8659 if (!i386_immediate (op_string
))
8662 else if (RC_SAE_immediate (operand_string
))
8664 /* If it is a RC or SAE immediate, do nothing. */
8667 else if (is_digit_char (*op_string
)
8668 || is_identifier_char (*op_string
)
8669 || *op_string
== '(')
8671 /* This is a memory reference of some sort. */
8674 /* Start and end of displacement string expression (if found). */
8675 char *displacement_string_start
;
8676 char *displacement_string_end
;
8679 do_memory_reference
:
8680 if ((i
.mem_operands
== 1
8681 && !current_templates
->start
->opcode_modifier
.isstring
)
8682 || i
.mem_operands
== 2)
8684 as_bad (_("too many memory references for `%s'"),
8685 current_templates
->start
->name
);
8689 /* Check for base index form. We detect the base index form by
8690 looking for an ')' at the end of the operand, searching
8691 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8693 base_string
= op_string
+ strlen (op_string
);
8695 /* Handle vector operations. */
8696 vop_start
= strchr (op_string
, '{');
8697 if (vop_start
&& vop_start
< base_string
)
8699 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8701 base_string
= vop_start
;
8705 if (is_space_char (*base_string
))
8708 /* If we only have a displacement, set-up for it to be parsed later. */
8709 displacement_string_start
= op_string
;
8710 displacement_string_end
= base_string
+ 1;
8712 if (*base_string
== ')')
8715 unsigned int parens_balanced
= 1;
8716 /* We've already checked that the number of left & right ()'s are
8717 equal, so this loop will not be infinite. */
8721 if (*base_string
== ')')
8723 if (*base_string
== '(')
8726 while (parens_balanced
);
8728 temp_string
= base_string
;
8730 /* Skip past '(' and whitespace. */
8732 if (is_space_char (*base_string
))
8735 if (*base_string
== ','
8736 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8739 displacement_string_end
= temp_string
;
8741 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8745 base_string
= end_op
;
8746 if (is_space_char (*base_string
))
8750 /* There may be an index reg or scale factor here. */
8751 if (*base_string
== ',')
8754 if (is_space_char (*base_string
))
8757 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8760 base_string
= end_op
;
8761 if (is_space_char (*base_string
))
8763 if (*base_string
== ',')
8766 if (is_space_char (*base_string
))
8769 else if (*base_string
!= ')')
8771 as_bad (_("expecting `,' or `)' "
8772 "after index register in `%s'"),
8777 else if (*base_string
== REGISTER_PREFIX
)
8779 end_op
= strchr (base_string
, ',');
8782 as_bad (_("bad register name `%s'"), base_string
);
8786 /* Check for scale factor. */
8787 if (*base_string
!= ')')
8789 char *end_scale
= i386_scale (base_string
);
8794 base_string
= end_scale
;
8795 if (is_space_char (*base_string
))
8797 if (*base_string
!= ')')
8799 as_bad (_("expecting `)' "
8800 "after scale factor in `%s'"),
8805 else if (!i
.index_reg
)
8807 as_bad (_("expecting index register or scale factor "
8808 "after `,'; got '%c'"),
8813 else if (*base_string
!= ')')
8815 as_bad (_("expecting `,' or `)' "
8816 "after base register in `%s'"),
8821 else if (*base_string
== REGISTER_PREFIX
)
8823 end_op
= strchr (base_string
, ',');
8826 as_bad (_("bad register name `%s'"), base_string
);
8831 /* If there's an expression beginning the operand, parse it,
8832 assuming displacement_string_start and
8833 displacement_string_end are meaningful. */
8834 if (displacement_string_start
!= displacement_string_end
)
8836 if (!i386_displacement (displacement_string_start
,
8837 displacement_string_end
))
8841 /* Special case for (%dx) while doing input/output op. */
8843 && operand_type_equal (&i
.base_reg
->reg_type
,
8844 ®16_inoutportreg
)
8846 && i
.log2_scale_factor
== 0
8847 && i
.seg
[i
.mem_operands
] == 0
8848 && !operand_type_check (i
.types
[this_operand
], disp
))
8850 i
.types
[this_operand
] = inoutportreg
;
8854 if (i386_index_check (operand_string
) == 0)
8856 i
.types
[this_operand
].bitfield
.mem
= 1;
8861 /* It's not a memory operand; argh! */
8862 as_bad (_("invalid char %s beginning operand %d `%s'"),
8863 output_invalid (*op_string
),
8868 return 1; /* Normal return. */
8871 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8872 that an rs_machine_dependent frag may reach. */
8875 i386_frag_max_var (fragS
*frag
)
8877 /* The only relaxable frags are for jumps.
8878 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8879 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8880 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8883 /* md_estimate_size_before_relax()
8885 Called just before relax() for rs_machine_dependent frags. The x86
8886 assembler uses these frags to handle variable size jump
8889 Any symbol that is now undefined will not become defined.
8890 Return the correct fr_subtype in the frag.
8891 Return the initial "guess for variable size of frag" to caller.
8892 The guess is actually the growth beyond the fixed part. Whatever
8893 we do to grow the fixed or variable part contributes to our
8897 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8899 /* We've already got fragP->fr_subtype right; all we have to do is
8900 check for un-relaxable symbols. On an ELF system, we can't relax
8901 an externally visible symbol, because it may be overridden by a
8903 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8904 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8906 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
8907 || S_IS_WEAK (fragP
->fr_symbol
)
8908 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
8909 & BSF_GNU_INDIRECT_FUNCTION
))))
8911 #if defined (OBJ_COFF) && defined (TE_PE)
8912 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8913 && S_IS_WEAK (fragP
->fr_symbol
))
8917 /* Symbol is undefined in this segment, or we need to keep a
8918 reloc so that weak symbols can be overridden. */
8919 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8920 enum bfd_reloc_code_real reloc_type
;
8921 unsigned char *opcode
;
8924 if (fragP
->fr_var
!= NO_RELOC
)
8925 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8927 reloc_type
= BFD_RELOC_16_PCREL
;
8929 reloc_type
= BFD_RELOC_32_PCREL
;
8931 old_fr_fix
= fragP
->fr_fix
;
8932 opcode
= (unsigned char *) fragP
->fr_opcode
;
8934 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
8937 /* Make jmp (0xeb) a (d)word displacement jump. */
8939 fragP
->fr_fix
+= size
;
8940 fix_new (fragP
, old_fr_fix
, size
,
8942 fragP
->fr_offset
, 1,
8948 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
8950 /* Negate the condition, and branch past an
8951 unconditional jump. */
8954 /* Insert an unconditional jump. */
8956 /* We added two extra opcode bytes, and have a two byte
8958 fragP
->fr_fix
+= 2 + 2;
8959 fix_new (fragP
, old_fr_fix
+ 2, 2,
8961 fragP
->fr_offset
, 1,
8968 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8973 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8975 fragP
->fr_offset
, 1,
8977 fixP
->fx_signed
= 1;
8981 /* This changes the byte-displacement jump 0x7N
8982 to the (d)word-displacement jump 0x0f,0x8N. */
8983 opcode
[1] = opcode
[0] + 0x10;
8984 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8985 /* We've added an opcode byte. */
8986 fragP
->fr_fix
+= 1 + size
;
8987 fix_new (fragP
, old_fr_fix
+ 1, size
,
8989 fragP
->fr_offset
, 1,
8994 BAD_CASE (fragP
->fr_subtype
);
8998 return fragP
->fr_fix
- old_fr_fix
;
9001 /* Guess size depending on current relax state. Initially the relax
9002 state will correspond to a short jump and we return 1, because
9003 the variable part of the frag (the branch offset) is one byte
9004 long. However, we can relax a section more than once and in that
9005 case we must either set fr_subtype back to the unrelaxed state,
9006 or return the value for the appropriate branch. */
9007 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9010 /* Called after relax() is finished.
9012 In: Address of frag.
9013 fr_type == rs_machine_dependent.
9014 fr_subtype is what the address relaxed to.
9016 Out: Any fixSs and constants are set up.
9017 Caller will turn frag into a ".space 0". */
9020 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9023 unsigned char *opcode
;
9024 unsigned char *where_to_put_displacement
= NULL
;
9025 offsetT target_address
;
9026 offsetT opcode_address
;
9027 unsigned int extension
= 0;
9028 offsetT displacement_from_opcode_start
;
9030 opcode
= (unsigned char *) fragP
->fr_opcode
;
9032 /* Address we want to reach in file space. */
9033 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9035 /* Address opcode resides at in file space. */
9036 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9038 /* Displacement from opcode start to fill into instruction. */
9039 displacement_from_opcode_start
= target_address
- opcode_address
;
9041 if ((fragP
->fr_subtype
& BIG
) == 0)
9043 /* Don't have to change opcode. */
9044 extension
= 1; /* 1 opcode + 1 displacement */
9045 where_to_put_displacement
= &opcode
[1];
9049 if (no_cond_jump_promotion
9050 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9051 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9052 _("long jump required"));
9054 switch (fragP
->fr_subtype
)
9056 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9057 extension
= 4; /* 1 opcode + 4 displacement */
9059 where_to_put_displacement
= &opcode
[1];
9062 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9063 extension
= 2; /* 1 opcode + 2 displacement */
9065 where_to_put_displacement
= &opcode
[1];
9068 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9069 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9070 extension
= 5; /* 2 opcode + 4 displacement */
9071 opcode
[1] = opcode
[0] + 0x10;
9072 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9073 where_to_put_displacement
= &opcode
[2];
9076 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9077 extension
= 3; /* 2 opcode + 2 displacement */
9078 opcode
[1] = opcode
[0] + 0x10;
9079 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9080 where_to_put_displacement
= &opcode
[2];
9083 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9088 where_to_put_displacement
= &opcode
[3];
9092 BAD_CASE (fragP
->fr_subtype
);
9097 /* If size if less then four we are sure that the operand fits,
9098 but if it's 4, then it could be that the displacement is larger
9100 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9102 && ((addressT
) (displacement_from_opcode_start
- extension
9103 + ((addressT
) 1 << 31))
9104 > (((addressT
) 2 << 31) - 1)))
9106 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9107 _("jump target out of range"));
9108 /* Make us emit 0. */
9109 displacement_from_opcode_start
= extension
;
9111 /* Now put displacement after opcode. */
9112 md_number_to_chars ((char *) where_to_put_displacement
,
9113 (valueT
) (displacement_from_opcode_start
- extension
),
9114 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9115 fragP
->fr_fix
+= extension
;
9118 /* Apply a fixup (fixP) to segment data, once it has been determined
9119 by our caller that we have all the info we need to fix it up.
9121 Parameter valP is the pointer to the value of the bits.
9123 On the 386, immediates, displacements, and data pointers are all in
9124 the same (little-endian) format, so we don't need to care about which
9128 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9130 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9131 valueT value
= *valP
;
9133 #if !defined (TE_Mach)
9136 switch (fixP
->fx_r_type
)
9142 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9145 case BFD_RELOC_X86_64_32S
:
9146 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9149 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9152 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9157 if (fixP
->fx_addsy
!= NULL
9158 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9159 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9160 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9161 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
9162 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PC32_BND
)
9163 && !use_rela_relocations
)
9165 /* This is a hack. There should be a better way to handle this.
9166 This covers for the fact that bfd_install_relocation will
9167 subtract the current location (for partial_inplace, PC relative
9168 relocations); see more below. */
9172 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9175 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9177 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9180 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9183 || (symbol_section_p (fixP
->fx_addsy
)
9184 && sym_seg
!= absolute_section
))
9185 && !generic_force_reloc (fixP
))
9187 /* Yes, we add the values in twice. This is because
9188 bfd_install_relocation subtracts them out again. I think
9189 bfd_install_relocation is broken, but I don't dare change
9191 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9195 #if defined (OBJ_COFF) && defined (TE_PE)
9196 /* For some reason, the PE format does not store a
9197 section address offset for a PC relative symbol. */
9198 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9199 || S_IS_WEAK (fixP
->fx_addsy
))
9200 value
+= md_pcrel_from (fixP
);
9203 #if defined (OBJ_COFF) && defined (TE_PE)
9204 if (fixP
->fx_addsy
!= NULL
9205 && S_IS_WEAK (fixP
->fx_addsy
)
9206 /* PR 16858: Do not modify weak function references. */
9207 && ! fixP
->fx_pcrel
)
9209 #if !defined (TE_PEP)
9210 /* For x86 PE weak function symbols are neither PC-relative
9211 nor do they set S_IS_FUNCTION. So the only reliable way
9212 to detect them is to check the flags of their containing
9214 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9215 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9219 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9223 /* Fix a few things - the dynamic linker expects certain values here,
9224 and we must not disappoint it. */
9225 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9226 if (IS_ELF
&& fixP
->fx_addsy
)
9227 switch (fixP
->fx_r_type
)
9229 case BFD_RELOC_386_PLT32
:
9230 case BFD_RELOC_X86_64_PLT32
:
9231 case BFD_RELOC_X86_64_PLT32_BND
:
9232 /* Make the jump instruction point to the address of the operand. At
9233 runtime we merely add the offset to the actual PLT entry. */
9237 case BFD_RELOC_386_TLS_GD
:
9238 case BFD_RELOC_386_TLS_LDM
:
9239 case BFD_RELOC_386_TLS_IE_32
:
9240 case BFD_RELOC_386_TLS_IE
:
9241 case BFD_RELOC_386_TLS_GOTIE
:
9242 case BFD_RELOC_386_TLS_GOTDESC
:
9243 case BFD_RELOC_X86_64_TLSGD
:
9244 case BFD_RELOC_X86_64_TLSLD
:
9245 case BFD_RELOC_X86_64_GOTTPOFF
:
9246 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9247 value
= 0; /* Fully resolved at runtime. No addend. */
9249 case BFD_RELOC_386_TLS_LE
:
9250 case BFD_RELOC_386_TLS_LDO_32
:
9251 case BFD_RELOC_386_TLS_LE_32
:
9252 case BFD_RELOC_X86_64_DTPOFF32
:
9253 case BFD_RELOC_X86_64_DTPOFF64
:
9254 case BFD_RELOC_X86_64_TPOFF32
:
9255 case BFD_RELOC_X86_64_TPOFF64
:
9256 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9259 case BFD_RELOC_386_TLS_DESC_CALL
:
9260 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9261 value
= 0; /* Fully resolved at runtime. No addend. */
9262 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9266 case BFD_RELOC_386_GOT32
:
9267 case BFD_RELOC_X86_64_GOT32
:
9268 value
= 0; /* Fully resolved at runtime. No addend. */
9271 case BFD_RELOC_VTABLE_INHERIT
:
9272 case BFD_RELOC_VTABLE_ENTRY
:
9279 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9281 #endif /* !defined (TE_Mach) */
9283 /* Are we finished with this relocation now? */
9284 if (fixP
->fx_addsy
== NULL
)
9286 #if defined (OBJ_COFF) && defined (TE_PE)
9287 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9290 /* Remember value for tc_gen_reloc. */
9291 fixP
->fx_addnumber
= value
;
9292 /* Clear out the frag for now. */
9296 else if (use_rela_relocations
)
9298 fixP
->fx_no_overflow
= 1;
9299 /* Remember value for tc_gen_reloc. */
9300 fixP
->fx_addnumber
= value
;
9304 md_number_to_chars (p
, value
, fixP
->fx_size
);
9308 md_atof (int type
, char *litP
, int *sizeP
)
9310 /* This outputs the LITTLENUMs in REVERSE order;
9311 in accord with the bigendian 386. */
9312 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9315 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9318 output_invalid (int c
)
9321 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9324 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9325 "(0x%x)", (unsigned char) c
);
9326 return output_invalid_buf
;
9329 /* REG_STRING starts *before* REGISTER_PREFIX. */
9331 static const reg_entry
*
9332 parse_real_register (char *reg_string
, char **end_op
)
9334 char *s
= reg_string
;
9336 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9339 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9340 if (*s
== REGISTER_PREFIX
)
9343 if (is_space_char (*s
))
9347 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9349 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9350 return (const reg_entry
*) NULL
;
9354 /* For naked regs, make sure that we are not dealing with an identifier.
9355 This prevents confusing an identifier like `eax_var' with register
9357 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9358 return (const reg_entry
*) NULL
;
9362 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9364 /* Handle floating point regs, allowing spaces in the (i) part. */
9365 if (r
== i386_regtab
/* %st is first entry of table */)
9367 if (is_space_char (*s
))
9372 if (is_space_char (*s
))
9374 if (*s
>= '0' && *s
<= '7')
9378 if (is_space_char (*s
))
9383 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9388 /* We have "%st(" then garbage. */
9389 return (const reg_entry
*) NULL
;
9393 if (r
== NULL
|| allow_pseudo_reg
)
9396 if (operand_type_all_zero (&r
->reg_type
))
9397 return (const reg_entry
*) NULL
;
9399 if ((r
->reg_type
.bitfield
.reg32
9400 || r
->reg_type
.bitfield
.sreg3
9401 || r
->reg_type
.bitfield
.control
9402 || r
->reg_type
.bitfield
.debug
9403 || r
->reg_type
.bitfield
.test
)
9404 && !cpu_arch_flags
.bitfield
.cpui386
)
9405 return (const reg_entry
*) NULL
;
9407 if (r
->reg_type
.bitfield
.floatreg
9408 && !cpu_arch_flags
.bitfield
.cpu8087
9409 && !cpu_arch_flags
.bitfield
.cpu287
9410 && !cpu_arch_flags
.bitfield
.cpu387
)
9411 return (const reg_entry
*) NULL
;
9413 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9414 return (const reg_entry
*) NULL
;
9416 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9417 return (const reg_entry
*) NULL
;
9419 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9420 return (const reg_entry
*) NULL
;
9422 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9423 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9424 return (const reg_entry
*) NULL
;
9426 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9427 if (!allow_index_reg
9428 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9429 return (const reg_entry
*) NULL
;
9431 /* Upper 16 vector register is only available with VREX in 64bit
9433 if ((r
->reg_flags
& RegVRex
))
9435 if (!cpu_arch_flags
.bitfield
.cpuvrex
9436 || flag_code
!= CODE_64BIT
)
9437 return (const reg_entry
*) NULL
;
9442 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9443 || r
->reg_type
.bitfield
.reg64
)
9444 && (!cpu_arch_flags
.bitfield
.cpulm
9445 || !operand_type_equal (&r
->reg_type
, &control
))
9446 && flag_code
!= CODE_64BIT
)
9447 return (const reg_entry
*) NULL
;
9449 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9450 return (const reg_entry
*) NULL
;
9455 /* REG_STRING starts *before* REGISTER_PREFIX. */
9457 static const reg_entry
*
9458 parse_register (char *reg_string
, char **end_op
)
9462 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9463 r
= parse_real_register (reg_string
, end_op
);
9468 char *save
= input_line_pointer
;
9472 input_line_pointer
= reg_string
;
9473 c
= get_symbol_end ();
9474 symbolP
= symbol_find (reg_string
);
9475 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9477 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9479 know (e
->X_op
== O_register
);
9480 know (e
->X_add_number
>= 0
9481 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9482 r
= i386_regtab
+ e
->X_add_number
;
9483 if ((r
->reg_flags
& RegVRex
))
9485 *end_op
= input_line_pointer
;
9487 *input_line_pointer
= c
;
9488 input_line_pointer
= save
;
9494 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9497 char *end
= input_line_pointer
;
9500 r
= parse_register (name
, &input_line_pointer
);
9501 if (r
&& end
<= input_line_pointer
)
9503 *nextcharP
= *input_line_pointer
;
9504 *input_line_pointer
= 0;
9505 e
->X_op
= O_register
;
9506 e
->X_add_number
= r
- i386_regtab
;
9509 input_line_pointer
= end
;
9511 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9515 md_operand (expressionS
*e
)
9520 switch (*input_line_pointer
)
9522 case REGISTER_PREFIX
:
9523 r
= parse_real_register (input_line_pointer
, &end
);
9526 e
->X_op
= O_register
;
9527 e
->X_add_number
= r
- i386_regtab
;
9528 input_line_pointer
= end
;
9533 gas_assert (intel_syntax
);
9534 end
= input_line_pointer
++;
9536 if (*input_line_pointer
== ']')
9538 ++input_line_pointer
;
9539 e
->X_op_symbol
= make_expr_symbol (e
);
9540 e
->X_add_symbol
= NULL
;
9541 e
->X_add_number
= 0;
9547 input_line_pointer
= end
;
9554 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9555 const char *md_shortopts
= "kVQ:sqn";
9557 const char *md_shortopts
= "qn";
9560 #define OPTION_32 (OPTION_MD_BASE + 0)
9561 #define OPTION_64 (OPTION_MD_BASE + 1)
9562 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9563 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9564 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9565 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9566 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9567 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9568 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9569 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9570 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9571 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9572 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9573 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9574 #define OPTION_X32 (OPTION_MD_BASE + 14)
9575 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9576 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9577 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9578 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9579 #define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9580 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9582 struct option md_longopts
[] =
9584 {"32", no_argument
, NULL
, OPTION_32
},
9585 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9586 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9587 {"64", no_argument
, NULL
, OPTION_64
},
9589 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9590 {"x32", no_argument
, NULL
, OPTION_X32
},
9592 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9593 {"march", required_argument
, NULL
, OPTION_MARCH
},
9594 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9595 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9596 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9597 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9598 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9599 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9600 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9601 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9602 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9603 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9604 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9605 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9606 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9607 # if defined (TE_PE) || defined (TE_PEP)
9608 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9610 {"momit-lock-prefix", required_argument
, NULL
, OPTION_OMIT_LOCK_PREFIX
},
9611 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9612 {NULL
, no_argument
, NULL
, 0}
9614 size_t md_longopts_size
= sizeof (md_longopts
);
9617 md_parse_option (int c
, char *arg
)
9625 optimize_align_code
= 0;
9632 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9633 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9634 should be emitted or not. FIXME: Not implemented. */
9638 /* -V: SVR4 argument to print version ID. */
9640 print_version_id ();
9643 /* -k: Ignore for FreeBSD compatibility. */
9648 /* -s: On i386 Solaris, this tells the native assembler to use
9649 .stab instead of .stab.excl. We always use .stab anyhow. */
9652 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9653 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9656 const char **list
, **l
;
9658 list
= bfd_target_list ();
9659 for (l
= list
; *l
!= NULL
; l
++)
9660 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9661 || strcmp (*l
, "coff-x86-64") == 0
9662 || strcmp (*l
, "pe-x86-64") == 0
9663 || strcmp (*l
, "pei-x86-64") == 0
9664 || strcmp (*l
, "mach-o-x86-64") == 0)
9666 default_arch
= "x86_64";
9670 as_fatal (_("no compiled in support for x86_64"));
9676 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9680 const char **list
, **l
;
9682 list
= bfd_target_list ();
9683 for (l
= list
; *l
!= NULL
; l
++)
9684 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9686 default_arch
= "x86_64:32";
9690 as_fatal (_("no compiled in support for 32bit x86_64"));
9694 as_fatal (_("32bit x86_64 is only supported for ELF"));
9699 default_arch
= "i386";
9703 #ifdef SVR4_COMMENT_CHARS
9708 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9710 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9714 i386_comment_chars
= n
;
9720 arch
= xstrdup (arg
);
9724 as_fatal (_("invalid -march= option: `%s'"), arg
);
9725 next
= strchr (arch
, '+');
9728 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9730 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9733 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9736 cpu_arch_name
= cpu_arch
[j
].name
;
9737 cpu_sub_arch_name
= NULL
;
9738 cpu_arch_flags
= cpu_arch
[j
].flags
;
9739 cpu_arch_isa
= cpu_arch
[j
].type
;
9740 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9741 if (!cpu_arch_tune_set
)
9743 cpu_arch_tune
= cpu_arch_isa
;
9744 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9748 else if (*cpu_arch
[j
].name
== '.'
9749 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9751 /* ISA entension. */
9752 i386_cpu_flags flags
;
9754 if (!cpu_arch
[j
].negated
)
9755 flags
= cpu_flags_or (cpu_arch_flags
,
9758 flags
= cpu_flags_and_not (cpu_arch_flags
,
9760 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9762 if (cpu_sub_arch_name
)
9764 char *name
= cpu_sub_arch_name
;
9765 cpu_sub_arch_name
= concat (name
,
9767 (const char *) NULL
);
9771 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9772 cpu_arch_flags
= flags
;
9773 cpu_arch_isa_flags
= flags
;
9779 if (j
>= ARRAY_SIZE (cpu_arch
))
9780 as_fatal (_("invalid -march= option: `%s'"), arg
);
9784 while (next
!= NULL
);
9789 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9790 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9792 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9794 cpu_arch_tune_set
= 1;
9795 cpu_arch_tune
= cpu_arch
[j
].type
;
9796 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9800 if (j
>= ARRAY_SIZE (cpu_arch
))
9801 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9804 case OPTION_MMNEMONIC
:
9805 if (strcasecmp (arg
, "att") == 0)
9807 else if (strcasecmp (arg
, "intel") == 0)
9810 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9813 case OPTION_MSYNTAX
:
9814 if (strcasecmp (arg
, "att") == 0)
9816 else if (strcasecmp (arg
, "intel") == 0)
9819 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9822 case OPTION_MINDEX_REG
:
9823 allow_index_reg
= 1;
9826 case OPTION_MNAKED_REG
:
9827 allow_naked_reg
= 1;
9830 case OPTION_MOLD_GCC
:
9834 case OPTION_MSSE2AVX
:
9838 case OPTION_MSSE_CHECK
:
9839 if (strcasecmp (arg
, "error") == 0)
9840 sse_check
= check_error
;
9841 else if (strcasecmp (arg
, "warning") == 0)
9842 sse_check
= check_warning
;
9843 else if (strcasecmp (arg
, "none") == 0)
9844 sse_check
= check_none
;
9846 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9849 case OPTION_MOPERAND_CHECK
:
9850 if (strcasecmp (arg
, "error") == 0)
9851 operand_check
= check_error
;
9852 else if (strcasecmp (arg
, "warning") == 0)
9853 operand_check
= check_warning
;
9854 else if (strcasecmp (arg
, "none") == 0)
9855 operand_check
= check_none
;
9857 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9860 case OPTION_MAVXSCALAR
:
9861 if (strcasecmp (arg
, "128") == 0)
9863 else if (strcasecmp (arg
, "256") == 0)
9866 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9869 case OPTION_MADD_BND_PREFIX
:
9873 case OPTION_MEVEXLIG
:
9874 if (strcmp (arg
, "128") == 0)
9876 else if (strcmp (arg
, "256") == 0)
9878 else if (strcmp (arg
, "512") == 0)
9881 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9884 case OPTION_MEVEXRCIG
:
9885 if (strcmp (arg
, "rne") == 0)
9887 else if (strcmp (arg
, "rd") == 0)
9889 else if (strcmp (arg
, "ru") == 0)
9891 else if (strcmp (arg
, "rz") == 0)
9894 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
9897 case OPTION_MEVEXWIG
:
9898 if (strcmp (arg
, "0") == 0)
9900 else if (strcmp (arg
, "1") == 0)
9903 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9906 # if defined (TE_PE) || defined (TE_PEP)
9907 case OPTION_MBIG_OBJ
:
9912 case OPTION_OMIT_LOCK_PREFIX
:
9913 if (strcasecmp (arg
, "yes") == 0)
9914 omit_lock_prefix
= 1;
9915 else if (strcasecmp (arg
, "no") == 0)
9916 omit_lock_prefix
= 0;
9918 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
9927 #define MESSAGE_TEMPLATE \
9931 show_arch (FILE *stream
, int ext
, int check
)
9933 static char message
[] = MESSAGE_TEMPLATE
;
9934 char *start
= message
+ 27;
9936 int size
= sizeof (MESSAGE_TEMPLATE
);
9943 left
= size
- (start
- message
);
9944 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9946 /* Should it be skipped? */
9947 if (cpu_arch
[j
].skip
)
9950 name
= cpu_arch
[j
].name
;
9951 len
= cpu_arch
[j
].len
;
9954 /* It is an extension. Skip if we aren't asked to show it. */
9965 /* It is an processor. Skip if we show only extension. */
9968 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9970 /* It is an impossible processor - skip. */
9974 /* Reserve 2 spaces for ", " or ",\0" */
9977 /* Check if there is any room. */
9985 p
= mempcpy (p
, name
, len
);
9989 /* Output the current message now and start a new one. */
9992 fprintf (stream
, "%s\n", message
);
9994 left
= size
- (start
- message
) - len
- 2;
9996 gas_assert (left
>= 0);
9998 p
= mempcpy (p
, name
, len
);
10003 fprintf (stream
, "%s\n", message
);
10007 md_show_usage (FILE *stream
)
10009 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10010 fprintf (stream
, _("\
10012 -V print assembler version number\n\
10015 fprintf (stream
, _("\
10016 -n Do not optimize code alignment\n\
10017 -q quieten some warnings\n"));
10018 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10019 fprintf (stream
, _("\
10022 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10023 || defined (TE_PE) || defined (TE_PEP))
10024 fprintf (stream
, _("\
10025 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10027 #ifdef SVR4_COMMENT_CHARS
10028 fprintf (stream
, _("\
10029 --divide do not treat `/' as a comment character\n"));
10031 fprintf (stream
, _("\
10032 --divide ignored\n"));
10034 fprintf (stream
, _("\
10035 -march=CPU[,+EXTENSION...]\n\
10036 generate code for CPU and EXTENSION, CPU is one of:\n"));
10037 show_arch (stream
, 0, 1);
10038 fprintf (stream
, _("\
10039 EXTENSION is combination of:\n"));
10040 show_arch (stream
, 1, 0);
10041 fprintf (stream
, _("\
10042 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10043 show_arch (stream
, 0, 0);
10044 fprintf (stream
, _("\
10045 -msse2avx encode SSE instructions with VEX prefix\n"));
10046 fprintf (stream
, _("\
10047 -msse-check=[none|error|warning]\n\
10048 check SSE instructions\n"));
10049 fprintf (stream
, _("\
10050 -moperand-check=[none|error|warning]\n\
10051 check operand combinations for validity\n"));
10052 fprintf (stream
, _("\
10053 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10055 fprintf (stream
, _("\
10056 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10058 fprintf (stream
, _("\
10059 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10060 for EVEX.W bit ignored instructions\n"));
10061 fprintf (stream
, _("\
10062 -mevexrcig=[rne|rd|ru|rz]\n\
10063 encode EVEX instructions with specific EVEX.RC value\n\
10064 for SAE-only ignored instructions\n"));
10065 fprintf (stream
, _("\
10066 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10067 fprintf (stream
, _("\
10068 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10069 fprintf (stream
, _("\
10070 -mindex-reg support pseudo index registers\n"));
10071 fprintf (stream
, _("\
10072 -mnaked-reg don't require `%%' prefix for registers\n"));
10073 fprintf (stream
, _("\
10074 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10075 fprintf (stream
, _("\
10076 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10077 # if defined (TE_PE) || defined (TE_PEP)
10078 fprintf (stream
, _("\
10079 -mbig-obj generate big object files\n"));
10081 fprintf (stream
, _("\
10082 -momit-lock-prefix=[no|yes]\n\
10083 strip all lock prefixes\n"));
10086 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10087 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10088 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10090 /* Pick the target format to use. */
10093 i386_target_format (void)
10095 if (!strncmp (default_arch
, "x86_64", 6))
10097 update_code_flag (CODE_64BIT
, 1);
10098 if (default_arch
[6] == '\0')
10099 x86_elf_abi
= X86_64_ABI
;
10101 x86_elf_abi
= X86_64_X32_ABI
;
10103 else if (!strcmp (default_arch
, "i386"))
10104 update_code_flag (CODE_32BIT
, 1);
10106 as_fatal (_("unknown architecture"));
10108 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10109 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10110 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10111 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10113 switch (OUTPUT_FLAVOR
)
10115 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10116 case bfd_target_aout_flavour
:
10117 return AOUT_TARGET_FORMAT
;
10119 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10120 # if defined (TE_PE) || defined (TE_PEP)
10121 case bfd_target_coff_flavour
:
10122 if (flag_code
== CODE_64BIT
)
10123 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10126 # elif defined (TE_GO32)
10127 case bfd_target_coff_flavour
:
10128 return "coff-go32";
10130 case bfd_target_coff_flavour
:
10131 return "coff-i386";
10134 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10135 case bfd_target_elf_flavour
:
10137 const char *format
;
10139 switch (x86_elf_abi
)
10142 format
= ELF_TARGET_FORMAT
;
10145 use_rela_relocations
= 1;
10147 format
= ELF_TARGET_FORMAT64
;
10149 case X86_64_X32_ABI
:
10150 use_rela_relocations
= 1;
10152 disallow_64bit_reloc
= 1;
10153 format
= ELF_TARGET_FORMAT32
;
10156 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10158 if (x86_elf_abi
!= X86_64_ABI
)
10159 as_fatal (_("Intel L1OM is 64bit only"));
10160 return ELF_TARGET_L1OM_FORMAT
;
10162 if (cpu_arch_isa
== PROCESSOR_K1OM
)
10164 if (x86_elf_abi
!= X86_64_ABI
)
10165 as_fatal (_("Intel K1OM is 64bit only"));
10166 return ELF_TARGET_K1OM_FORMAT
;
10172 #if defined (OBJ_MACH_O)
10173 case bfd_target_mach_o_flavour
:
10174 if (flag_code
== CODE_64BIT
)
10176 use_rela_relocations
= 1;
10178 return "mach-o-x86-64";
10181 return "mach-o-i386";
10189 #endif /* OBJ_MAYBE_ more than one */
10191 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
10193 i386_elf_emit_arch_note (void)
10195 if (IS_ELF
&& cpu_arch_name
!= NULL
)
10198 asection
*seg
= now_seg
;
10199 subsegT subseg
= now_subseg
;
10200 Elf_Internal_Note i_note
;
10201 Elf_External_Note e_note
;
10202 asection
*note_secp
;
10205 /* Create the .note section. */
10206 note_secp
= subseg_new (".note", 0);
10207 bfd_set_section_flags (stdoutput
,
10209 SEC_HAS_CONTENTS
| SEC_READONLY
);
10211 /* Process the arch string. */
10212 len
= strlen (cpu_arch_name
);
10214 i_note
.namesz
= len
+ 1;
10216 i_note
.type
= NT_ARCH
;
10217 p
= frag_more (sizeof (e_note
.namesz
));
10218 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
10219 p
= frag_more (sizeof (e_note
.descsz
));
10220 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
10221 p
= frag_more (sizeof (e_note
.type
));
10222 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
10223 p
= frag_more (len
+ 1);
10224 strcpy (p
, cpu_arch_name
);
10226 frag_align (2, 0, 0);
10228 subseg_set (seg
, subseg
);
10234 md_undefined_symbol (char *name
)
10236 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10237 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10238 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10239 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10243 if (symbol_find (name
))
10244 as_bad (_("GOT already in symbol table"));
10245 GOT_symbol
= symbol_new (name
, undefined_section
,
10246 (valueT
) 0, &zero_address_frag
);
10253 /* Round up a section size to the appropriate boundary. */
10256 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10258 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10259 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10261 /* For a.out, force the section size to be aligned. If we don't do
10262 this, BFD will align it for us, but it will not write out the
10263 final bytes of the section. This may be a bug in BFD, but it is
10264 easier to fix it here since that is how the other a.out targets
10268 align
= bfd_get_section_alignment (stdoutput
, segment
);
10269 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
10276 /* On the i386, PC-relative offsets are relative to the start of the
10277 next instruction. That is, the address of the offset, plus its
10278 size, since the offset is always the last part of the insn. */
10281 md_pcrel_from (fixS
*fixP
)
10283 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10289 s_bss (int ignore ATTRIBUTE_UNUSED
)
10293 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10295 obj_elf_section_change_hook ();
10297 temp
= get_absolute_expression ();
10298 subseg_set (bss_section
, (subsegT
) temp
);
10299 demand_empty_rest_of_line ();
10305 i386_validate_fix (fixS
*fixp
)
10307 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
10309 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10313 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10318 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10320 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10322 fixp
->fx_subsy
= 0;
10327 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10330 bfd_reloc_code_real_type code
;
10332 switch (fixp
->fx_r_type
)
10334 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10335 case BFD_RELOC_SIZE32
:
10336 case BFD_RELOC_SIZE64
:
10337 if (S_IS_DEFINED (fixp
->fx_addsy
)
10338 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10340 /* Resolve size relocation against local symbol to size of
10341 the symbol plus addend. */
10342 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10343 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10344 && !fits_in_unsigned_long (value
))
10345 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10346 _("symbol size computation overflow"));
10347 fixp
->fx_addsy
= NULL
;
10348 fixp
->fx_subsy
= NULL
;
10349 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10354 case BFD_RELOC_X86_64_PLT32
:
10355 case BFD_RELOC_X86_64_PLT32_BND
:
10356 case BFD_RELOC_X86_64_GOT32
:
10357 case BFD_RELOC_X86_64_GOTPCREL
:
10358 case BFD_RELOC_386_PLT32
:
10359 case BFD_RELOC_386_GOT32
:
10360 case BFD_RELOC_386_GOTOFF
:
10361 case BFD_RELOC_386_GOTPC
:
10362 case BFD_RELOC_386_TLS_GD
:
10363 case BFD_RELOC_386_TLS_LDM
:
10364 case BFD_RELOC_386_TLS_LDO_32
:
10365 case BFD_RELOC_386_TLS_IE_32
:
10366 case BFD_RELOC_386_TLS_IE
:
10367 case BFD_RELOC_386_TLS_GOTIE
:
10368 case BFD_RELOC_386_TLS_LE_32
:
10369 case BFD_RELOC_386_TLS_LE
:
10370 case BFD_RELOC_386_TLS_GOTDESC
:
10371 case BFD_RELOC_386_TLS_DESC_CALL
:
10372 case BFD_RELOC_X86_64_TLSGD
:
10373 case BFD_RELOC_X86_64_TLSLD
:
10374 case BFD_RELOC_X86_64_DTPOFF32
:
10375 case BFD_RELOC_X86_64_DTPOFF64
:
10376 case BFD_RELOC_X86_64_GOTTPOFF
:
10377 case BFD_RELOC_X86_64_TPOFF32
:
10378 case BFD_RELOC_X86_64_TPOFF64
:
10379 case BFD_RELOC_X86_64_GOTOFF64
:
10380 case BFD_RELOC_X86_64_GOTPC32
:
10381 case BFD_RELOC_X86_64_GOT64
:
10382 case BFD_RELOC_X86_64_GOTPCREL64
:
10383 case BFD_RELOC_X86_64_GOTPC64
:
10384 case BFD_RELOC_X86_64_GOTPLT64
:
10385 case BFD_RELOC_X86_64_PLTOFF64
:
10386 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10387 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10388 case BFD_RELOC_RVA
:
10389 case BFD_RELOC_VTABLE_ENTRY
:
10390 case BFD_RELOC_VTABLE_INHERIT
:
10392 case BFD_RELOC_32_SECREL
:
10394 code
= fixp
->fx_r_type
;
10396 case BFD_RELOC_X86_64_32S
:
10397 if (!fixp
->fx_pcrel
)
10399 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10400 code
= fixp
->fx_r_type
;
10404 if (fixp
->fx_pcrel
)
10406 switch (fixp
->fx_size
)
10409 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10410 _("can not do %d byte pc-relative relocation"),
10412 code
= BFD_RELOC_32_PCREL
;
10414 case 1: code
= BFD_RELOC_8_PCREL
; break;
10415 case 2: code
= BFD_RELOC_16_PCREL
; break;
10417 code
= (fixp
->fx_r_type
== BFD_RELOC_X86_64_PC32_BND
10418 ? fixp
-> fx_r_type
: BFD_RELOC_32_PCREL
);
10421 case 8: code
= BFD_RELOC_64_PCREL
; break;
10427 switch (fixp
->fx_size
)
10430 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10431 _("can not do %d byte relocation"),
10433 code
= BFD_RELOC_32
;
10435 case 1: code
= BFD_RELOC_8
; break;
10436 case 2: code
= BFD_RELOC_16
; break;
10437 case 4: code
= BFD_RELOC_32
; break;
10439 case 8: code
= BFD_RELOC_64
; break;
10446 if ((code
== BFD_RELOC_32
10447 || code
== BFD_RELOC_32_PCREL
10448 || code
== BFD_RELOC_X86_64_32S
)
10450 && fixp
->fx_addsy
== GOT_symbol
)
10453 code
= BFD_RELOC_386_GOTPC
;
10455 code
= BFD_RELOC_X86_64_GOTPC32
;
10457 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10459 && fixp
->fx_addsy
== GOT_symbol
)
10461 code
= BFD_RELOC_X86_64_GOTPC64
;
10464 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10465 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10466 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10468 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10470 if (!use_rela_relocations
)
10472 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10473 vtable entry to be used in the relocation's section offset. */
10474 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10475 rel
->address
= fixp
->fx_offset
;
10476 #if defined (OBJ_COFF) && defined (TE_PE)
10477 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10478 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10483 /* Use the rela in 64bit mode. */
10486 if (disallow_64bit_reloc
)
10489 case BFD_RELOC_X86_64_DTPOFF64
:
10490 case BFD_RELOC_X86_64_TPOFF64
:
10491 case BFD_RELOC_64_PCREL
:
10492 case BFD_RELOC_X86_64_GOTOFF64
:
10493 case BFD_RELOC_X86_64_GOT64
:
10494 case BFD_RELOC_X86_64_GOTPCREL64
:
10495 case BFD_RELOC_X86_64_GOTPC64
:
10496 case BFD_RELOC_X86_64_GOTPLT64
:
10497 case BFD_RELOC_X86_64_PLTOFF64
:
10498 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10499 _("cannot represent relocation type %s in x32 mode"),
10500 bfd_get_reloc_code_name (code
));
10506 if (!fixp
->fx_pcrel
)
10507 rel
->addend
= fixp
->fx_offset
;
10511 case BFD_RELOC_X86_64_PLT32
:
10512 case BFD_RELOC_X86_64_PLT32_BND
:
10513 case BFD_RELOC_X86_64_GOT32
:
10514 case BFD_RELOC_X86_64_GOTPCREL
:
10515 case BFD_RELOC_X86_64_TLSGD
:
10516 case BFD_RELOC_X86_64_TLSLD
:
10517 case BFD_RELOC_X86_64_GOTTPOFF
:
10518 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10519 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10520 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10523 rel
->addend
= (section
->vma
10525 + fixp
->fx_addnumber
10526 + md_pcrel_from (fixp
));
10531 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10532 if (rel
->howto
== NULL
)
10534 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10535 _("cannot represent relocation type %s"),
10536 bfd_get_reloc_code_name (code
));
10537 /* Set howto to a garbage value so that we can keep going. */
10538 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10539 gas_assert (rel
->howto
!= NULL
);
10545 #include "tc-i386-intel.c"
10548 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10550 int saved_naked_reg
;
10551 char saved_register_dot
;
10553 saved_naked_reg
= allow_naked_reg
;
10554 allow_naked_reg
= 1;
10555 saved_register_dot
= register_chars
['.'];
10556 register_chars
['.'] = '.';
10557 allow_pseudo_reg
= 1;
10558 expression_and_evaluate (exp
);
10559 allow_pseudo_reg
= 0;
10560 register_chars
['.'] = saved_register_dot
;
10561 allow_naked_reg
= saved_naked_reg
;
10563 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10565 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10567 exp
->X_op
= O_constant
;
10568 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10569 .dw2_regnum
[flag_code
>> 1];
10572 exp
->X_op
= O_illegal
;
10577 tc_x86_frame_initial_instructions (void)
10579 static unsigned int sp_regno
[2];
10581 if (!sp_regno
[flag_code
>> 1])
10583 char *saved_input
= input_line_pointer
;
10584 char sp
[][4] = {"esp", "rsp"};
10587 input_line_pointer
= sp
[flag_code
>> 1];
10588 tc_x86_parse_to_dw2regnum (&exp
);
10589 gas_assert (exp
.X_op
== O_constant
);
10590 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10591 input_line_pointer
= saved_input
;
10594 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10595 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10599 x86_dwarf2_addr_size (void)
10601 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10602 if (x86_elf_abi
== X86_64_X32_ABI
)
10605 return bfd_arch_bits_per_address (stdoutput
) / 8;
10609 i386_elf_section_type (const char *str
, size_t len
)
10611 if (flag_code
== CODE_64BIT
10612 && len
== sizeof ("unwind") - 1
10613 && strncmp (str
, "unwind", 6) == 0)
10614 return SHT_X86_64_UNWIND
;
10621 i386_solaris_fix_up_eh_frame (segT sec
)
10623 if (flag_code
== CODE_64BIT
)
10624 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10630 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10634 exp
.X_op
= O_secrel
;
10635 exp
.X_add_symbol
= symbol
;
10636 exp
.X_add_number
= 0;
10637 emit_expr (&exp
, size
);
10641 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10642 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10645 x86_64_section_letter (int letter
, char **ptr_msg
)
10647 if (flag_code
== CODE_64BIT
)
10650 return SHF_X86_64_LARGE
;
10652 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10655 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10660 x86_64_section_word (char *str
, size_t len
)
10662 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10663 return SHF_X86_64_LARGE
;
10669 handle_large_common (int small ATTRIBUTE_UNUSED
)
10671 if (flag_code
!= CODE_64BIT
)
10673 s_comm_internal (0, elf_common_parse
);
10674 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10678 static segT lbss_section
;
10679 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10680 asection
*saved_bss_section
= bss_section
;
10682 if (lbss_section
== NULL
)
10684 flagword applicable
;
10685 segT seg
= now_seg
;
10686 subsegT subseg
= now_subseg
;
10688 /* The .lbss section is for local .largecomm symbols. */
10689 lbss_section
= subseg_new (".lbss", 0);
10690 applicable
= bfd_applicable_section_flags (stdoutput
);
10691 bfd_set_section_flags (stdoutput
, lbss_section
,
10692 applicable
& SEC_ALLOC
);
10693 seg_info (lbss_section
)->bss
= 1;
10695 subseg_set (seg
, subseg
);
10698 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10699 bss_section
= lbss_section
;
10701 s_comm_internal (0, elf_common_parse
);
10703 elf_com_section_ptr
= saved_com_section_ptr
;
10704 bss_section
= saved_bss_section
;
10707 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */