1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Intel 80386 machine specific gas.
23 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
24 x86_64 support by Jan Hubicka (jh@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
32 #include "dwarf2dbg.h"
33 #include "opcode/i386.h"
35 #ifndef REGISTER_WARNINGS
36 #define REGISTER_WARNINGS 1
39 #ifndef INFER_ADDR_PREFIX
40 #define INFER_ADDR_PREFIX 1
43 #ifndef SCALE1_WHEN_NO_INDEX
44 /* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48 #define SCALE1_WHEN_NO_INDEX 1
54 static unsigned int mode_from_disp_size
PARAMS ((unsigned int));
55 static int fits_in_signed_byte
PARAMS ((offsetT
));
56 static int fits_in_unsigned_byte
PARAMS ((offsetT
));
57 static int fits_in_unsigned_word
PARAMS ((offsetT
));
58 static int fits_in_signed_word
PARAMS ((offsetT
));
59 static int fits_in_unsigned_long
PARAMS ((offsetT
));
60 static int fits_in_signed_long
PARAMS ((offsetT
));
61 static int smallest_imm_type
PARAMS ((offsetT
));
62 static offsetT offset_in_range
PARAMS ((offsetT
, int));
63 static int add_prefix
PARAMS ((unsigned int));
64 static void set_code_flag
PARAMS ((int));
65 static void set_16bit_gcc_code_flag
PARAMS ((int));
66 static void set_intel_syntax
PARAMS ((int));
67 static void set_cpu_arch
PARAMS ((int));
70 static bfd_reloc_code_real_type reloc
71 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
75 #define DEFAULT_ARCH "i386"
77 static char *default_arch
= DEFAULT_ARCH
;
79 /* 'md_assemble ()' gathers together information and puts it into a
86 const reg_entry
*regs
;
91 /* TM holds the template for the insn were currently assembling. */
94 /* SUFFIX holds the instruction mnemonic suffix if given.
95 (e.g. 'l' for 'movl') */
98 /* OPERANDS gives the number of given operands. */
99 unsigned int operands
;
101 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
102 of given register, displacement, memory operands and immediate
104 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
106 /* TYPES [i] is the type (see above #defines) which tells us how to
107 use OP[i] for the corresponding operand. */
108 unsigned int types
[MAX_OPERANDS
];
110 /* Displacement expression, immediate expression, or register for each
112 union i386_op op
[MAX_OPERANDS
];
114 /* Flags for operands. */
115 unsigned int flags
[MAX_OPERANDS
];
116 #define Operand_PCrel 1
118 /* Relocation type for operand */
120 enum bfd_reloc_code_real disp_reloc
[MAX_OPERANDS
];
122 int disp_reloc
[MAX_OPERANDS
];
125 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
126 the base index byte below. */
127 const reg_entry
*base_reg
;
128 const reg_entry
*index_reg
;
129 unsigned int log2_scale_factor
;
131 /* SEG gives the seg_entries of this insn. They are zero unless
132 explicit segment overrides are given. */
133 const seg_entry
*seg
[2];
135 /* PREFIX holds all the given prefix opcodes (usually null).
136 PREFIXES is the number of prefix opcodes. */
137 unsigned int prefixes
;
138 unsigned char prefix
[MAX_PREFIXES
];
140 /* RM and SIB are the modrm byte and the sib byte where the
141 addressing modes of this insn are encoded. */
148 typedef struct _i386_insn i386_insn
;
150 /* List of chars besides those in app.c:symbol_chars that can start an
151 operand. Used to prevent the scrubber eating vital white-space. */
153 const char extra_symbol_chars
[] = "*%-(@";
155 const char extra_symbol_chars
[] = "*%-(";
158 /* This array holds the chars that always start a comment. If the
159 pre-processor is disabled, these aren't very useful. */
160 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
161 /* Putting '/' here makes it impossible to use the divide operator.
162 However, we need it for compatibility with SVR4 systems. */
163 const char comment_chars
[] = "#/";
164 #define PREFIX_SEPARATOR '\\'
166 const char comment_chars
[] = "#";
167 #define PREFIX_SEPARATOR '/'
170 /* This array holds the chars that only start a comment at the beginning of
171 a line. If the line seems to have the form '# 123 filename'
172 .line and .file directives will appear in the pre-processed output.
173 Note that input_file.c hand checks for '#' at the beginning of the
174 first line of the input file. This is because the compiler outputs
175 #NO_APP at the beginning of its output.
176 Also note that comments started like this one will always work if
177 '/' isn't otherwise defined. */
178 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
179 const char line_comment_chars
[] = "";
181 const char line_comment_chars
[] = "/";
184 const char line_separator_chars
[] = ";";
186 /* Chars that can be used to separate mant from exp in floating point
188 const char EXP_CHARS
[] = "eE";
190 /* Chars that mean this number is a floating point constant
193 const char FLT_CHARS
[] = "fFdDxX";
195 /* Tables for lexical analysis. */
196 static char mnemonic_chars
[256];
197 static char register_chars
[256];
198 static char operand_chars
[256];
199 static char identifier_chars
[256];
200 static char digit_chars
[256];
202 /* Lexical macros. */
203 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
204 #define is_operand_char(x) (operand_chars[(unsigned char) x])
205 #define is_register_char(x) (register_chars[(unsigned char) x])
206 #define is_space_char(x) ((x) == ' ')
207 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
208 #define is_digit_char(x) (digit_chars[(unsigned char) x])
210 /* All non-digit non-letter charcters that may occur in an operand. */
211 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
213 /* md_assemble() always leaves the strings it's passed unaltered. To
214 effect this we maintain a stack of saved characters that we've smashed
215 with '\0's (indicating end of strings for various sub-fields of the
216 assembler instruction). */
217 static char save_stack
[32];
218 static char *save_stack_p
;
219 #define END_STRING_AND_SAVE(s) \
220 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
221 #define RESTORE_END_STRING(s) \
222 do { *(s) = *--save_stack_p; } while (0)
224 /* The instruction we're assembling. */
227 /* Possible templates for current insn. */
228 static const templates
*current_templates
;
230 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
231 static expressionS disp_expressions
[2], im_expressions
[2];
233 /* Current operand we are working on. */
234 static int this_operand
;
236 /* We support four different modes. FLAG_CODE variable is used to distinguish
244 static enum flag_code flag_code
;
245 static int use_rela_relocations
= 0;
247 /* The names used to print error messages. */
248 static const char *flag_code_names
[] =
255 /* 1 for intel syntax,
257 static int intel_syntax
= 0;
259 /* 1 if register prefix % not required. */
260 static int allow_naked_reg
= 0;
262 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
263 leave, push, and pop instructions so that gcc has the same stack
264 frame as in 32 bit mode. */
265 static char stackop_size
= '\0';
267 /* Non-zero to quieten some warnings. */
268 static int quiet_warnings
= 0;
271 static const char *cpu_arch_name
= NULL
;
273 /* CPU feature flags. */
274 static unsigned int cpu_arch_flags
= CpuUnknownFlags
|CpuNo64
;
276 /* Interface to relax_segment.
277 There are 2 relax states for 386 jump insns: one for conditional &
278 one for unconditional jumps. This is because these two types of
279 jumps add different sizes to frags when we're figuring out what
280 sort of jump to choose to reach a given label. */
284 #define UNCOND_JUMP 2
288 #define SMALL16 (SMALL|CODE16)
290 #define BIG16 (BIG|CODE16)
294 #define INLINE __inline__
300 #define ENCODE_RELAX_STATE(type,size) \
301 ((relax_substateT) ((type<<2) | (size)))
302 #define SIZE_FROM_RELAX_STATE(s) \
303 ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) )
305 /* This table is used by relax_frag to promote short jumps to long
306 ones where necessary. SMALL (short) jumps may be promoted to BIG
307 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
308 don't allow a short jump in a 32 bit code segment to be promoted to
309 a 16 bit offset jump because it's slower (requires data size
310 prefix), and doesn't work, unless the destination is in the bottom
311 64k of the code segment (The top 16 bits of eip are zeroed). */
313 const relax_typeS md_relax_table
[] =
316 1) most positive reach of this state,
317 2) most negative reach of this state,
318 3) how many bytes this mode will add to the size of the current frag
319 4) which index into the table to try if we can't fit into this one. */
325 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
326 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
327 /* dword conditionals adds 4 bytes to frag:
328 1 extra opcode byte, 3 extra displacement bytes. */
330 /* word conditionals add 2 bytes to frag:
331 1 extra opcode byte, 1 extra displacement byte. */
334 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
335 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
336 /* dword jmp adds 3 bytes to frag:
337 0 extra opcode bytes, 3 extra displacement bytes. */
339 /* word jmp adds 1 byte to frag:
340 0 extra opcode bytes, 1 extra displacement byte. */
345 static const arch_entry cpu_arch
[] = {
347 {"i186", Cpu086
|Cpu186
},
348 {"i286", Cpu086
|Cpu186
|Cpu286
},
349 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
350 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
351 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
352 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
353 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
354 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
355 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
356 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
357 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
358 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
363 i386_align_code (fragP
, count
)
367 /* Various efficient no-op patterns for aligning code labels.
368 Note: Don't try to assemble the instructions in the comments.
369 0L and 0w are not legal. */
370 static const char f32_1
[] =
372 static const char f32_2
[] =
373 {0x89,0xf6}; /* movl %esi,%esi */
374 static const char f32_3
[] =
375 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
376 static const char f32_4
[] =
377 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
378 static const char f32_5
[] =
380 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
381 static const char f32_6
[] =
382 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
383 static const char f32_7
[] =
384 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
385 static const char f32_8
[] =
387 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
388 static const char f32_9
[] =
389 {0x89,0xf6, /* movl %esi,%esi */
390 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
391 static const char f32_10
[] =
392 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
393 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
394 static const char f32_11
[] =
395 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
396 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
397 static const char f32_12
[] =
398 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
399 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
400 static const char f32_13
[] =
401 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
402 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
403 static const char f32_14
[] =
404 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
405 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
406 static const char f32_15
[] =
407 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
408 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
409 static const char f16_3
[] =
410 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
411 static const char f16_4
[] =
412 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
413 static const char f16_5
[] =
415 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
416 static const char f16_6
[] =
417 {0x89,0xf6, /* mov %si,%si */
418 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
419 static const char f16_7
[] =
420 {0x8d,0x74,0x00, /* lea 0(%si),%si */
421 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
422 static const char f16_8
[] =
423 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
424 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
425 static const char *const f32_patt
[] = {
426 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
427 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
429 static const char *const f16_patt
[] = {
430 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
431 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
434 /* ??? We can't use these fillers for x86_64, since they often kills the
435 upper halves. Solve later. */
436 if (flag_code
== CODE_64BIT
)
439 if (count
> 0 && count
<= 15)
441 if (flag_code
== CODE_16BIT
)
443 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
444 f16_patt
[count
- 1], count
);
446 /* Adjust jump offset. */
447 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
450 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
451 f32_patt
[count
- 1], count
);
452 fragP
->fr_var
= count
;
456 static char *output_invalid
PARAMS ((int c
));
457 static int i386_operand
PARAMS ((char *operand_string
));
458 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
459 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
463 static void s_bss
PARAMS ((int));
466 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
468 static INLINE
unsigned int
469 mode_from_disp_size (t
)
472 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
476 fits_in_signed_byte (num
)
479 return (num
>= -128) && (num
<= 127);
483 fits_in_unsigned_byte (num
)
486 return (num
& 0xff) == num
;
490 fits_in_unsigned_word (num
)
493 return (num
& 0xffff) == num
;
497 fits_in_signed_word (num
)
500 return (-32768 <= num
) && (num
<= 32767);
503 fits_in_signed_long (num
)
504 offsetT num ATTRIBUTE_UNUSED
;
509 return (!(((offsetT
) -1 << 31) & num
)
510 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
512 } /* fits_in_signed_long() */
514 fits_in_unsigned_long (num
)
515 offsetT num ATTRIBUTE_UNUSED
;
520 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
522 } /* fits_in_unsigned_long() */
525 smallest_imm_type (num
)
528 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
)
529 && !(cpu_arch_flags
& (CpuUnknown
)))
531 /* This code is disabled on the 486 because all the Imm1 forms
532 in the opcode table are slower on the i486. They're the
533 versions with the implicitly specified single-position
534 displacement, which has another syntax if you really want to
537 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
539 return (fits_in_signed_byte (num
)
540 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
541 : fits_in_unsigned_byte (num
)
542 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
543 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
544 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
545 : fits_in_signed_long (num
)
546 ? (Imm32
| Imm32S
| Imm64
)
547 : fits_in_unsigned_long (num
)
553 offset_in_range (val
, size
)
561 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
562 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
563 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
565 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
570 /* If BFD64, sign extend val. */
571 if (!use_rela_relocations
)
572 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
573 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
575 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
577 char buf1
[40], buf2
[40];
579 sprint_value (buf1
, val
);
580 sprint_value (buf2
, val
& mask
);
581 as_warn (_("%s shortened to %s"), buf1
, buf2
);
586 /* Returns 0 if attempting to add a prefix where one from the same
587 class already exists, 1 if non rep/repne added, 2 if rep/repne
596 if (prefix
>= 0x40 && prefix
< 0x50 && flag_code
== CODE_64BIT
)
604 case CS_PREFIX_OPCODE
:
605 case DS_PREFIX_OPCODE
:
606 case ES_PREFIX_OPCODE
:
607 case FS_PREFIX_OPCODE
:
608 case GS_PREFIX_OPCODE
:
609 case SS_PREFIX_OPCODE
:
613 case REPNE_PREFIX_OPCODE
:
614 case REPE_PREFIX_OPCODE
:
617 case LOCK_PREFIX_OPCODE
:
625 case ADDR_PREFIX_OPCODE
:
629 case DATA_PREFIX_OPCODE
:
636 as_bad (_("same type of prefix used twice"));
641 i
.prefix
[q
] = prefix
;
646 set_code_flag (value
)
650 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
651 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
652 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
654 as_bad (_("64bit mode not supported on this CPU."));
656 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
658 as_bad (_("32bit mode not supported on this CPU."));
664 set_16bit_gcc_code_flag (new_code_flag
)
667 flag_code
= new_code_flag
;
668 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
669 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
674 set_intel_syntax (syntax_flag
)
677 /* Find out if register prefixing is specified. */
678 int ask_naked_reg
= 0;
681 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
683 char *string
= input_line_pointer
;
684 int e
= get_symbol_end ();
686 if (strcmp (string
, "prefix") == 0)
688 else if (strcmp (string
, "noprefix") == 0)
691 as_bad (_("bad argument to syntax directive."));
692 *input_line_pointer
= e
;
694 demand_empty_rest_of_line ();
696 intel_syntax
= syntax_flag
;
698 if (ask_naked_reg
== 0)
701 allow_naked_reg
= (intel_syntax
702 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
704 /* Conservative default. */
709 allow_naked_reg
= (ask_naked_reg
< 0);
714 int dummy ATTRIBUTE_UNUSED
;
718 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
720 char *string
= input_line_pointer
;
721 int e
= get_symbol_end ();
724 for (i
= 0; cpu_arch
[i
].name
; i
++)
726 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
728 cpu_arch_name
= cpu_arch
[i
].name
;
729 cpu_arch_flags
= cpu_arch
[i
].flags
| (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
733 if (!cpu_arch
[i
].name
)
734 as_bad (_("no such architecture: `%s'"), string
);
736 *input_line_pointer
= e
;
739 as_bad (_("missing cpu architecture"));
741 demand_empty_rest_of_line ();
744 const pseudo_typeS md_pseudo_table
[] =
746 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
747 {"align", s_align_bytes
, 0},
749 {"align", s_align_ptwo
, 0},
751 {"arch", set_cpu_arch
, 0},
755 {"ffloat", float_cons
, 'f'},
756 {"dfloat", float_cons
, 'd'},
757 {"tfloat", float_cons
, 'x'},
759 {"noopt", s_ignore
, 0},
760 {"optim", s_ignore
, 0},
761 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
762 {"code16", set_code_flag
, CODE_16BIT
},
763 {"code32", set_code_flag
, CODE_32BIT
},
764 {"code64", set_code_flag
, CODE_64BIT
},
765 {"intel_syntax", set_intel_syntax
, 1},
766 {"att_syntax", set_intel_syntax
, 0},
767 {"file", dwarf2_directive_file
, 0},
768 {"loc", dwarf2_directive_loc
, 0},
772 /* For interface with expression (). */
773 extern char *input_line_pointer
;
775 /* Hash table for instruction mnemonic lookup. */
776 static struct hash_control
*op_hash
;
778 /* Hash table for register lookup. */
779 static struct hash_control
*reg_hash
;
784 const char *hash_err
;
786 /* Initialize op_hash hash table. */
787 op_hash
= hash_new ();
790 register const template *optab
;
791 register templates
*core_optab
;
793 /* Setup for loop. */
795 core_optab
= (templates
*) xmalloc (sizeof (templates
));
796 core_optab
->start
= optab
;
801 if (optab
->name
== NULL
802 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
804 /* different name --> ship out current template list;
805 add to hash table; & begin anew. */
806 core_optab
->end
= optab
;
807 hash_err
= hash_insert (op_hash
,
812 as_fatal (_("Internal Error: Can't hash %s: %s"),
816 if (optab
->name
== NULL
)
818 core_optab
= (templates
*) xmalloc (sizeof (templates
));
819 core_optab
->start
= optab
;
824 /* Initialize reg_hash hash table. */
825 reg_hash
= hash_new ();
827 register const reg_entry
*regtab
;
829 for (regtab
= i386_regtab
;
830 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
833 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
835 as_fatal (_("Internal Error: Can't hash %s: %s"),
841 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
846 for (c
= 0; c
< 256; c
++)
851 mnemonic_chars
[c
] = c
;
852 register_chars
[c
] = c
;
853 operand_chars
[c
] = c
;
855 else if (islower (c
))
857 mnemonic_chars
[c
] = c
;
858 register_chars
[c
] = c
;
859 operand_chars
[c
] = c
;
861 else if (isupper (c
))
863 mnemonic_chars
[c
] = tolower (c
);
864 register_chars
[c
] = mnemonic_chars
[c
];
865 operand_chars
[c
] = c
;
868 if (isalpha (c
) || isdigit (c
))
869 identifier_chars
[c
] = c
;
872 identifier_chars
[c
] = c
;
873 operand_chars
[c
] = c
;
878 identifier_chars
['@'] = '@';
880 digit_chars
['-'] = '-';
881 identifier_chars
['_'] = '_';
882 identifier_chars
['.'] = '.';
884 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
885 operand_chars
[(unsigned char) *p
] = *p
;
888 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
889 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
891 record_alignment (text_section
, 2);
892 record_alignment (data_section
, 2);
893 record_alignment (bss_section
, 2);
899 i386_print_statistics (file
)
902 hash_print_statistics (file
, "i386 opcode", op_hash
);
903 hash_print_statistics (file
, "i386 register", reg_hash
);
908 /* Debugging routines for md_assemble. */
909 static void pi
PARAMS ((char *, i386_insn
*));
910 static void pte
PARAMS ((template *));
911 static void pt
PARAMS ((unsigned int));
912 static void pe
PARAMS ((expressionS
*));
913 static void ps
PARAMS ((symbolS
*));
922 fprintf (stdout
, "%s: template ", line
);
924 fprintf (stdout
, " address: base %s index %s scale %x\n",
925 x
->base_reg
? x
->base_reg
->reg_name
: "none",
926 x
->index_reg
? x
->index_reg
->reg_name
: "none",
927 x
->log2_scale_factor
);
928 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
929 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
930 fprintf (stdout
, " sib: base %x index %x scale %x\n",
931 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
932 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
933 x
->rex
.mode64
, x
->rex
.extX
, x
->rex
.extY
, x
->rex
.extZ
);
934 for (i
= 0; i
< x
->operands
; i
++)
936 fprintf (stdout
, " #%d: ", i
+ 1);
938 fprintf (stdout
, "\n");
940 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
941 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
942 if (x
->types
[i
] & Imm
)
944 if (x
->types
[i
] & Disp
)
954 fprintf (stdout
, " %d operands ", t
->operands
);
955 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
956 if (t
->extension_opcode
!= None
)
957 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
958 if (t
->opcode_modifier
& D
)
959 fprintf (stdout
, "D");
960 if (t
->opcode_modifier
& W
)
961 fprintf (stdout
, "W");
962 fprintf (stdout
, "\n");
963 for (i
= 0; i
< t
->operands
; i
++)
965 fprintf (stdout
, " #%d type ", i
+ 1);
966 pt (t
->operand_types
[i
]);
967 fprintf (stdout
, "\n");
975 fprintf (stdout
, " operation %d\n", e
->X_op
);
976 fprintf (stdout
, " add_number %ld (%lx)\n",
977 (long) e
->X_add_number
, (long) e
->X_add_number
);
980 fprintf (stdout
, " add_symbol ");
981 ps (e
->X_add_symbol
);
982 fprintf (stdout
, "\n");
986 fprintf (stdout
, " op_symbol ");
988 fprintf (stdout
, "\n");
996 fprintf (stdout
, "%s type %s%s",
998 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
999 segment_name (S_GET_SEGMENT (s
)));
1021 { BaseIndex
, "BaseIndex" },
1025 { Disp32S
, "d32s" },
1027 { InOutPortReg
, "InOutPortReg" },
1028 { ShiftCount
, "ShiftCount" },
1029 { Control
, "control reg" },
1030 { Test
, "test reg" },
1031 { Debug
, "debug reg" },
1032 { FloatReg
, "FReg" },
1033 { FloatAcc
, "FAcc" },
1037 { JumpAbsolute
, "Jump Absolute" },
1048 register struct type_name
*ty
;
1050 for (ty
= type_names
; ty
->mask
; ty
++)
1052 fprintf (stdout
, "%s, ", ty
->tname
);
1056 #endif /* DEBUG386 */
1059 tc_i386_force_relocation (fixp
)
1062 #ifdef BFD_ASSEMBLER
1063 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1064 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1069 return fixp
->fx_r_type
== 7;
1073 #ifdef BFD_ASSEMBLER
1075 static bfd_reloc_code_real_type
1076 reloc (size
, pcrel
, sign
, other
)
1080 bfd_reloc_code_real_type other
;
1082 if (other
!= NO_RELOC
)
1088 as_bad(_("There are no unsigned pc-relative relocations"));
1091 case 1: return BFD_RELOC_8_PCREL
;
1092 case 2: return BFD_RELOC_16_PCREL
;
1093 case 4: return BFD_RELOC_32_PCREL
;
1095 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1102 case 4: return BFD_RELOC_X86_64_32S
;
1107 case 1: return BFD_RELOC_8
;
1108 case 2: return BFD_RELOC_16
;
1109 case 4: return BFD_RELOC_32
;
1110 case 8: return BFD_RELOC_64
;
1112 as_bad (_("can not do %s %d byte relocation"),
1113 sign
? "signed" : "unsigned", size
);
1117 return BFD_RELOC_NONE
;
1120 /* Here we decide which fixups can be adjusted to make them relative to
1121 the beginning of the section instead of the symbol. Basically we need
1122 to make sure that the dynamic relocations are done correctly, so in
1123 some cases we force the original symbol to be used. */
1126 tc_i386_fix_adjustable (fixP
)
1129 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1130 /* Prevent all adjustments to global symbols, or else dynamic
1131 linking will not work correctly. */
1132 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1133 || S_IS_WEAK (fixP
->fx_addsy
))
1136 /* adjust_reloc_syms doesn't know about the GOT. */
1137 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1138 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1139 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1140 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1141 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1142 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1143 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1148 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1149 #define BFD_RELOC_16 0
1150 #define BFD_RELOC_32 0
1151 #define BFD_RELOC_16_PCREL 0
1152 #define BFD_RELOC_32_PCREL 0
1153 #define BFD_RELOC_386_PLT32 0
1154 #define BFD_RELOC_386_GOT32 0
1155 #define BFD_RELOC_386_GOTOFF 0
1156 #define BFD_RELOC_X86_64_PLT32 0
1157 #define BFD_RELOC_X86_64_GOT32 0
1158 #define BFD_RELOC_X86_64_GOTPCREL 0
1161 static int intel_float_operand
PARAMS ((char *mnemonic
));
1164 intel_float_operand (mnemonic
)
1167 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1170 if (mnemonic
[0] == 'f')
1176 /* This is the guts of the machine-dependent assembler. LINE points to a
1177 machine dependent instruction. This function is supposed to emit
1178 the frags/bytes it assembles to. */
1184 /* Points to template once we've found it. */
1187 /* Count the size of the instruction generated. */
1192 char mnemonic
[MAX_MNEM_SIZE
];
1194 /* Initialize globals. */
1195 memset (&i
, '\0', sizeof (i
));
1196 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1197 i
.disp_reloc
[j
] = NO_RELOC
;
1198 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1199 memset (im_expressions
, '\0', sizeof (im_expressions
));
1200 save_stack_p
= save_stack
;
1202 /* First parse an instruction mnemonic & call i386_operand for the operands.
1203 We assume that the scrubber has arranged it so that line[0] is the valid
1204 start of a (possibly prefixed) mnemonic. */
1207 char *token_start
= l
;
1210 /* Non-zero if we found a prefix only acceptable with string insns. */
1211 const char *expecting_string_instruction
= NULL
;
1216 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1219 if (mnem_p
>= mnemonic
+ sizeof (mnemonic
))
1221 as_bad (_("no such instruction: `%s'"), token_start
);
1226 if (!is_space_char (*l
)
1227 && *l
!= END_OF_INSN
1228 && *l
!= PREFIX_SEPARATOR
)
1230 as_bad (_("invalid character %s in mnemonic"),
1231 output_invalid (*l
));
1234 if (token_start
== l
)
1236 if (*l
== PREFIX_SEPARATOR
)
1237 as_bad (_("expecting prefix; got nothing"));
1239 as_bad (_("expecting mnemonic; got nothing"));
1243 /* Look up instruction (or prefix) via hash table. */
1244 current_templates
= hash_find (op_hash
, mnemonic
);
1246 if (*l
!= END_OF_INSN
1247 && (! is_space_char (*l
) || l
[1] != END_OF_INSN
)
1248 && current_templates
1249 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1251 /* If we are in 16-bit mode, do not allow addr16 or data16.
1252 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1253 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1254 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1255 ^ (flag_code
== CODE_16BIT
)))
1257 as_bad (_("redundant %s prefix"),
1258 current_templates
->start
->name
);
1261 /* Add prefix, checking for repeated prefixes. */
1262 switch (add_prefix (current_templates
->start
->base_opcode
))
1267 expecting_string_instruction
= current_templates
->start
->name
;
1270 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1277 if (!current_templates
)
1279 /* See if we can get a match by trimming off a suffix. */
1282 case WORD_MNEM_SUFFIX
:
1283 case BYTE_MNEM_SUFFIX
:
1284 case QWORD_MNEM_SUFFIX
:
1285 i
.suffix
= mnem_p
[-1];
1287 current_templates
= hash_find (op_hash
, mnemonic
);
1289 case SHORT_MNEM_SUFFIX
:
1290 case LONG_MNEM_SUFFIX
:
1293 i
.suffix
= mnem_p
[-1];
1295 current_templates
= hash_find (op_hash
, mnemonic
);
1303 if (intel_float_operand (mnemonic
))
1304 i
.suffix
= SHORT_MNEM_SUFFIX
;
1306 i
.suffix
= LONG_MNEM_SUFFIX
;
1308 current_templates
= hash_find (op_hash
, mnemonic
);
1312 if (!current_templates
)
1314 as_bad (_("no such instruction: `%s'"), token_start
);
1319 /* Check if instruction is supported on specified architecture. */
1320 if (cpu_arch_flags
!= 0)
1322 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1323 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1325 as_warn (_("`%s' is not supported on `%s'"),
1326 current_templates
->start
->name
, cpu_arch_name
);
1328 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1330 as_warn (_("use .code16 to ensure correct addressing mode"));
1334 /* Check for rep/repne without a string instruction. */
1335 if (expecting_string_instruction
1336 && !(current_templates
->start
->opcode_modifier
& IsString
))
1338 as_bad (_("expecting string instruction after `%s'"),
1339 expecting_string_instruction
);
1343 /* There may be operands to parse. */
1344 if (*l
!= END_OF_INSN
)
1346 /* 1 if operand is pending after ','. */
1347 unsigned int expecting_operand
= 0;
1349 /* Non-zero if operand parens not balanced. */
1350 unsigned int paren_not_balanced
;
1354 /* Skip optional white space before operand. */
1355 if (is_space_char (*l
))
1357 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1359 as_bad (_("invalid character %s before operand %d"),
1360 output_invalid (*l
),
1364 token_start
= l
; /* after white space */
1365 paren_not_balanced
= 0;
1366 while (paren_not_balanced
|| *l
!= ',')
1368 if (*l
== END_OF_INSN
)
1370 if (paren_not_balanced
)
1373 as_bad (_("unbalanced parenthesis in operand %d."),
1376 as_bad (_("unbalanced brackets in operand %d."),
1381 break; /* we are done */
1383 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1385 as_bad (_("invalid character %s in operand %d"),
1386 output_invalid (*l
),
1393 ++paren_not_balanced
;
1395 --paren_not_balanced
;
1400 ++paren_not_balanced
;
1402 --paren_not_balanced
;
1406 if (l
!= token_start
)
1407 { /* Yes, we've read in another operand. */
1408 unsigned int operand_ok
;
1409 this_operand
= i
.operands
++;
1410 if (i
.operands
> MAX_OPERANDS
)
1412 as_bad (_("spurious operands; (%d operands/instruction max)"),
1416 /* Now parse operand adding info to 'i' as we go along. */
1417 END_STRING_AND_SAVE (l
);
1421 i386_intel_operand (token_start
,
1422 intel_float_operand (mnemonic
));
1424 operand_ok
= i386_operand (token_start
);
1426 RESTORE_END_STRING (l
);
1432 if (expecting_operand
)
1434 expecting_operand_after_comma
:
1435 as_bad (_("expecting operand after ','; got nothing"));
1440 as_bad (_("expecting operand before ','; got nothing"));
1445 /* Now *l must be either ',' or END_OF_INSN. */
1448 if (*++l
== END_OF_INSN
)
1450 /* Just skip it, if it's \n complain. */
1451 goto expecting_operand_after_comma
;
1453 expecting_operand
= 1;
1456 while (*l
!= END_OF_INSN
);
1460 /* Now we've parsed the mnemonic into a set of templates, and have the
1463 Next, we find a template that matches the given insn,
1464 making sure the overlap of the given operands types is consistent
1465 with the template operand types. */
1467 #define MATCH(overlap, given, template) \
1468 ((overlap & ~JumpAbsolute) \
1469 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1471 /* If given types r0 and r1 are registers they must be of the same type
1472 unless the expected operand type register overlap is null.
1473 Note that Acc in a template matches every size of reg. */
1474 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1475 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1476 ((g0) & Reg) == ((g1) & Reg) || \
1477 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1480 register unsigned int overlap0
, overlap1
;
1481 unsigned int overlap2
;
1482 unsigned int found_reverse_match
;
1485 /* All intel opcodes have reversed operands except for "bound" and
1486 "enter". We also don't reverse intersegment "jmp" and "call"
1487 instructions with 2 immediate operands so that the immediate segment
1488 precedes the offset, as it does when in AT&T mode. "enter" and the
1489 intersegment "jmp" and "call" instructions are the only ones that
1490 have two immediate operands. */
1491 if (intel_syntax
&& i
.operands
> 1
1492 && (strcmp (mnemonic
, "bound") != 0)
1493 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1495 union i386_op temp_op
;
1496 unsigned int temp_type
;
1497 #ifdef BFD_ASSEMBLER
1498 enum bfd_reloc_code_real temp_reloc
;
1505 if (i
.operands
== 2)
1510 else if (i
.operands
== 3)
1515 temp_type
= i
.types
[xchg2
];
1516 i
.types
[xchg2
] = i
.types
[xchg1
];
1517 i
.types
[xchg1
] = temp_type
;
1518 temp_op
= i
.op
[xchg2
];
1519 i
.op
[xchg2
] = i
.op
[xchg1
];
1520 i
.op
[xchg1
] = temp_op
;
1521 temp_reloc
= i
.disp_reloc
[xchg2
];
1522 i
.disp_reloc
[xchg2
] = i
.disp_reloc
[xchg1
];
1523 i
.disp_reloc
[xchg1
] = temp_reloc
;
1525 if (i
.mem_operands
== 2)
1527 const seg_entry
*temp_seg
;
1528 temp_seg
= i
.seg
[0];
1529 i
.seg
[0] = i
.seg
[1];
1530 i
.seg
[1] = temp_seg
;
1536 /* Try to ensure constant immediates are represented in the smallest
1538 char guess_suffix
= 0;
1542 guess_suffix
= i
.suffix
;
1543 else if (i
.reg_operands
)
1545 /* Figure out a suffix from the last register operand specified.
1546 We can't do this properly yet, ie. excluding InOutPortReg,
1547 but the following works for instructions with immediates.
1548 In any case, we can't set i.suffix yet. */
1549 for (op
= i
.operands
; --op
>= 0;)
1550 if (i
.types
[op
] & Reg
)
1552 if (i
.types
[op
] & Reg8
)
1553 guess_suffix
= BYTE_MNEM_SUFFIX
;
1554 else if (i
.types
[op
] & Reg16
)
1555 guess_suffix
= WORD_MNEM_SUFFIX
;
1556 else if (i
.types
[op
] & Reg32
)
1557 guess_suffix
= LONG_MNEM_SUFFIX
;
1558 else if (i
.types
[op
] & Reg64
)
1559 guess_suffix
= QWORD_MNEM_SUFFIX
;
1563 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1564 guess_suffix
= WORD_MNEM_SUFFIX
;
1566 for (op
= i
.operands
; --op
>= 0;)
1567 if (i
.types
[op
] & Imm
)
1569 switch (i
.op
[op
].imms
->X_op
)
1572 /* If a suffix is given, this operand may be shortened. */
1573 switch (guess_suffix
)
1575 case LONG_MNEM_SUFFIX
:
1576 i
.types
[op
] |= Imm32
| Imm64
;
1578 case WORD_MNEM_SUFFIX
:
1579 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1581 case BYTE_MNEM_SUFFIX
:
1582 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1586 /* If this operand is at most 16 bits, convert it to a
1587 signed 16 bit number before trying to see whether it will
1588 fit in an even smaller size. This allows a 16-bit operand
1589 such as $0xffe0 to be recognised as within Imm8S range. */
1590 if ((i
.types
[op
] & Imm16
)
1591 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
)0xffff) == 0)
1593 i
.op
[op
].imms
->X_add_number
=
1594 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1596 if ((i
.types
[op
] & Imm32
)
1597 && (i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1)) == 0)
1599 i
.op
[op
].imms
->X_add_number
=
1600 (i
.op
[op
].imms
->X_add_number
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1602 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1603 /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */
1604 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1605 i
.types
[op
] &= ~Imm32
;
1610 /* Symbols and expressions. */
1612 /* Convert symbolic operand to proper sizes for matching. */
1613 switch (guess_suffix
)
1615 case QWORD_MNEM_SUFFIX
:
1616 i
.types
[op
] = Imm64
| Imm32S
;
1618 case LONG_MNEM_SUFFIX
:
1619 i
.types
[op
] = Imm32
| Imm64
;
1621 case WORD_MNEM_SUFFIX
:
1622 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1625 case BYTE_MNEM_SUFFIX
:
1626 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1635 if (i
.disp_operands
)
1637 /* Try to use the smallest displacement type too. */
1640 for (op
= i
.operands
; --op
>= 0;)
1641 if ((i
.types
[op
] & Disp
)
1642 && i
.op
[op
].imms
->X_op
== O_constant
)
1644 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1646 if (i
.types
[op
] & Disp16
)
1648 /* We know this operand is at most 16 bits, so
1649 convert to a signed 16 bit number before trying
1650 to see whether it will fit in an even smaller
1653 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1655 else if (i
.types
[op
] & Disp32
)
1657 /* We know this operand is at most 32 bits, so convert to a
1658 signed 32 bit number before trying to see whether it will
1659 fit in an even smaller size. */
1660 disp
&= (((offsetT
) 2 << 31) - 1);
1661 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1663 if (flag_code
== CODE_64BIT
)
1665 if (fits_in_signed_long (disp
))
1666 i
.types
[op
] |= Disp32S
;
1667 if (fits_in_unsigned_long (disp
))
1668 i
.types
[op
] |= Disp32
;
1670 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1671 && fits_in_signed_byte (disp
))
1672 i
.types
[op
] |= Disp8
;
1679 found_reverse_match
= 0;
1680 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1682 : (i
.suffix
== WORD_MNEM_SUFFIX
1684 : (i
.suffix
== SHORT_MNEM_SUFFIX
1686 : (i
.suffix
== LONG_MNEM_SUFFIX
1688 : (i
.suffix
== QWORD_MNEM_SUFFIX
1690 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
? No_xSuf
: 0))))));
1692 for (t
= current_templates
->start
;
1693 t
< current_templates
->end
;
1696 /* Must have right number of operands. */
1697 if (i
.operands
!= t
->operands
)
1700 /* Check the suffix, except for some instructions in intel mode. */
1701 if ((t
->opcode_modifier
& suffix_check
)
1703 && (t
->opcode_modifier
& IgnoreSize
))
1705 && t
->base_opcode
== 0xd9
1706 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1707 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1710 else if (!t
->operands
)
1711 /* 0 operands always matches. */
1714 overlap0
= i
.types
[0] & t
->operand_types
[0];
1715 switch (t
->operands
)
1718 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1723 overlap1
= i
.types
[1] & t
->operand_types
[1];
1724 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1725 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1726 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1727 t
->operand_types
[0],
1728 overlap1
, i
.types
[1],
1729 t
->operand_types
[1]))
1731 /* Check if other direction is valid ... */
1732 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1735 /* Try reversing direction of operands. */
1736 overlap0
= i
.types
[0] & t
->operand_types
[1];
1737 overlap1
= i
.types
[1] & t
->operand_types
[0];
1738 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1739 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1740 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1741 t
->operand_types
[1],
1742 overlap1
, i
.types
[1],
1743 t
->operand_types
[0]))
1745 /* Does not match either direction. */
1748 /* found_reverse_match holds which of D or FloatDR
1750 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1752 /* Found a forward 2 operand match here. */
1753 else if (t
->operands
== 3)
1755 /* Here we make use of the fact that there are no
1756 reverse match 3 operand instructions, and all 3
1757 operand instructions only need to be checked for
1758 register consistency between operands 2 and 3. */
1759 overlap2
= i
.types
[2] & t
->operand_types
[2];
1760 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1761 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1762 t
->operand_types
[1],
1763 overlap2
, i
.types
[2],
1764 t
->operand_types
[2]))
1768 /* Found either forward/reverse 2 or 3 operand match here:
1769 slip through to break. */
1771 if (t
->cpu_flags
& ~cpu_arch_flags
)
1773 found_reverse_match
= 0;
1776 /* We've found a match; break out of loop. */
1779 if (t
== current_templates
->end
)
1781 /* We found no match. */
1782 as_bad (_("suffix or operands invalid for `%s'"),
1783 current_templates
->start
->name
);
1787 if (!quiet_warnings
)
1790 && ((i
.types
[0] & JumpAbsolute
)
1791 != (t
->operand_types
[0] & JumpAbsolute
)))
1793 as_warn (_("indirect %s without `*'"), t
->name
);
1796 if ((t
->opcode_modifier
& (IsPrefix
|IgnoreSize
))
1797 == (IsPrefix
|IgnoreSize
))
1799 /* Warn them that a data or address size prefix doesn't
1800 affect assembly of the next line of code. */
1801 as_warn (_("stand-alone `%s' prefix"), t
->name
);
1805 /* Copy the template we found. */
1807 if (found_reverse_match
)
1809 /* If we found a reverse match we must alter the opcode
1810 direction bit. found_reverse_match holds bits to change
1811 (different for int & float insns). */
1813 i
.tm
.base_opcode
^= found_reverse_match
;
1815 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1816 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1819 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1822 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1823 i
.tm
.base_opcode
^= FloatR
;
1825 if (i
.tm
.opcode_modifier
& FWait
)
1826 if (! add_prefix (FWAIT_OPCODE
))
1829 /* Check string instruction segment overrides. */
1830 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1832 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1833 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1835 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1837 as_bad (_("`%s' operand %d must use `%%es' segment"),
1842 /* There's only ever one segment override allowed per instruction.
1843 This instruction possibly has a legal segment override on the
1844 second operand, so copy the segment to where non-string
1845 instructions store it, allowing common code. */
1846 i
.seg
[0] = i
.seg
[1];
1848 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1850 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1852 as_bad (_("`%s' operand %d must use `%%es' segment"),
1860 if (i
.reg_operands
&& flag_code
< CODE_64BIT
)
1863 for (op
= i
.operands
; --op
>= 0; )
1864 if ((i
.types
[op
] & Reg
)
1865 && (i
.op
[op
].regs
->reg_flags
& (RegRex64
|RegRex
)))
1866 as_bad (_("Extended register `%%%s' available only in 64bit mode."),
1867 i
.op
[op
].regs
->reg_name
);
1870 /* If matched instruction specifies an explicit instruction mnemonic
1872 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
1874 if (i
.tm
.opcode_modifier
& Size16
)
1875 i
.suffix
= WORD_MNEM_SUFFIX
;
1876 else if (i
.tm
.opcode_modifier
& Size64
)
1877 i
.suffix
= QWORD_MNEM_SUFFIX
;
1879 i
.suffix
= LONG_MNEM_SUFFIX
;
1881 else if (i
.reg_operands
)
1883 /* If there's no instruction mnemonic suffix we try to invent one
1884 based on register operands. */
1887 /* We take i.suffix from the last register operand specified,
1888 Destination register type is more significant than source
1891 for (op
= i
.operands
; --op
>= 0;)
1892 if ((i
.types
[op
] & Reg
)
1893 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
1895 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
1896 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
1897 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
1902 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
1905 for (op
= i
.operands
; --op
>= 0;)
1907 /* If this is an eight bit register, it's OK. If it's
1908 the 16 or 32 bit version of an eight bit register,
1909 we will just use the low portion, and that's OK too. */
1910 if (i
.types
[op
] & Reg8
)
1913 /* movzx and movsx should not generate this warning. */
1915 && (i
.tm
.base_opcode
== 0xfb7
1916 || i
.tm
.base_opcode
== 0xfb6
1917 || i
.tm
.base_opcode
== 0x63
1918 || i
.tm
.base_opcode
== 0xfbe
1919 || i
.tm
.base_opcode
== 0xfbf))
1922 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
1924 /* Check that the template allows eight bit regs
1925 This kills insns such as `orb $1,%edx', which
1926 maybe should be allowed. */
1927 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
1931 /* Prohibit these changes in the 64bit mode, since
1932 the lowering is more complicated. */
1933 if (flag_code
== CODE_64BIT
1934 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1935 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1936 i
.op
[op
].regs
->reg_name
,
1938 #if REGISTER_WARNINGS
1940 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1941 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1942 (i
.op
[op
].regs
- (i
.types
[op
] & Reg16
? 8 : 16))->reg_name
,
1943 i
.op
[op
].regs
->reg_name
,
1948 /* Any other register is bad. */
1949 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
1951 | Control
| Debug
| Test
1952 | FloatReg
| FloatAcc
))
1954 as_bad (_("`%%%s' not allowed with `%s%c'"),
1955 i
.op
[op
].regs
->reg_name
,
1962 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
1966 for (op
= i
.operands
; --op
>= 0;)
1967 /* Reject eight bit registers, except where the template
1968 requires them. (eg. movzb) */
1969 if ((i
.types
[op
] & Reg8
) != 0
1970 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
1972 as_bad (_("`%%%s' not allowed with `%s%c'"),
1973 i
.op
[op
].regs
->reg_name
,
1978 /* Warn if the e prefix on a general reg is missing. */
1979 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
1980 && (i
.types
[op
] & Reg16
) != 0
1981 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
1983 /* Prohibit these changes in the 64bit mode, since
1984 the lowering is more complicated. */
1985 if (flag_code
== CODE_64BIT
)
1986 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1987 i
.op
[op
].regs
->reg_name
,
1989 #if REGISTER_WARNINGS
1991 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1992 (i
.op
[op
].regs
+ 8)->reg_name
,
1993 i
.op
[op
].regs
->reg_name
,
1997 /* Warn if the r prefix on a general reg is missing. */
1998 else if ((i
.types
[op
] & Reg64
) != 0
1999 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2001 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2002 i
.op
[op
].regs
->reg_name
,
2006 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2009 if (flag_code
< CODE_64BIT
)
2010 as_bad (_("64bit operations available only in 64bit modes."));
2012 for (op
= i
.operands
; --op
>= 0; )
2013 /* Reject eight bit registers, except where the template
2014 requires them. (eg. movzb) */
2015 if ((i
.types
[op
] & Reg8
) != 0
2016 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2018 as_bad (_("`%%%s' not allowed with `%s%c'"),
2019 i
.op
[op
].regs
->reg_name
,
2024 /* Warn if the e prefix on a general reg is missing. */
2025 else if (((i
.types
[op
] & Reg16
) != 0
2026 || (i
.types
[op
] & Reg32
) != 0)
2027 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2029 /* Prohibit these changes in the 64bit mode, since
2030 the lowering is more complicated. */
2031 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2032 i
.op
[op
].regs
->reg_name
,
2036 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2039 for (op
= i
.operands
; --op
>= 0;)
2040 /* Reject eight bit registers, except where the template
2041 requires them. (eg. movzb) */
2042 if ((i
.types
[op
] & Reg8
) != 0
2043 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2045 as_bad (_("`%%%s' not allowed with `%s%c'"),
2046 i
.op
[op
].regs
->reg_name
,
2051 /* Warn if the e prefix on a general reg is present. */
2052 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2053 && (i
.types
[op
] & Reg32
) != 0
2054 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
2056 /* Prohibit these changes in the 64bit mode, since
2057 the lowering is more complicated. */
2058 if (flag_code
== CODE_64BIT
)
2059 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2060 i
.op
[op
].regs
->reg_name
,
2063 #if REGISTER_WARNINGS
2064 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2065 (i
.op
[op
].regs
- 8)->reg_name
,
2066 i
.op
[op
].regs
->reg_name
,
2071 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2072 /* Do nothing if the instruction is going to ignore the prefix. */
2077 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2079 i
.suffix
= stackop_size
;
2081 /* Make still unresolved immediate matches conform to size of immediate
2082 given in i.suffix. Note: overlap2 cannot be an immediate! */
2083 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2084 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2085 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2086 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2090 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2091 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2092 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2094 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2095 || overlap0
== (Imm16
| Imm32
)
2096 || overlap0
== (Imm16
| Imm32S
))
2099 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2101 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2102 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2103 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2105 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2109 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2110 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2111 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2112 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2116 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2117 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2118 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2120 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2121 || overlap1
== (Imm16
| Imm32
)
2122 || overlap1
== (Imm16
| Imm32S
))
2125 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2127 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2128 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2129 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2131 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2135 assert ((overlap2
& Imm
) == 0);
2137 i
.types
[0] = overlap0
;
2138 if (overlap0
& ImplicitRegister
)
2140 if (overlap0
& Imm1
)
2141 i
.imm_operands
= 0; /* kludge for shift insns. */
2143 i
.types
[1] = overlap1
;
2144 if (overlap1
& ImplicitRegister
)
2147 i
.types
[2] = overlap2
;
2148 if (overlap2
& ImplicitRegister
)
2151 /* Finalize opcode. First, we change the opcode based on the operand
2152 size given by i.suffix: We need not change things for byte insns. */
2154 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2156 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2160 /* For movzx and movsx, need to check the register type. */
2162 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
2163 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
2165 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2167 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
2168 if (!add_prefix (prefix
))
2172 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2174 /* It's not a byte, select word/dword operation. */
2175 if (i
.tm
.opcode_modifier
& W
)
2177 if (i
.tm
.opcode_modifier
& ShortForm
)
2178 i
.tm
.base_opcode
|= 8;
2180 i
.tm
.base_opcode
|= 1;
2182 /* Now select between word & dword operations via the operand
2183 size prefix, except for instructions that will ignore this
2185 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2186 && (i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2187 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
2189 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2190 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2191 prefix
= ADDR_PREFIX_OPCODE
;
2193 if (! add_prefix (prefix
))
2197 /* Set mode64 for an operand. */
2198 if (i
.suffix
== QWORD_MNEM_SUFFIX
2199 && !(i
.tm
.opcode_modifier
& NoRex64
))
2202 /* Size floating point instruction. */
2203 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2205 if (i
.tm
.opcode_modifier
& FloatMF
)
2206 i
.tm
.base_opcode
^= 4;
2210 if (i
.tm
.opcode_modifier
& ImmExt
)
2212 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2213 opcode suffix which is coded in the same place as an 8-bit
2214 immediate field would be. Here we fake an 8-bit immediate
2215 operand from the opcode suffix stored in tm.extension_opcode. */
2219 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
2221 exp
= &im_expressions
[i
.imm_operands
++];
2222 i
.op
[i
.operands
].imms
= exp
;
2223 i
.types
[i
.operands
++] = Imm8
;
2224 exp
->X_op
= O_constant
;
2225 exp
->X_add_number
= i
.tm
.extension_opcode
;
2226 i
.tm
.extension_opcode
= None
;
2229 /* For insns with operands there are more diddles to do to the opcode. */
2232 /* Default segment register this instruction will use
2233 for memory accesses. 0 means unknown.
2234 This is only for optimizing out unnecessary segment overrides. */
2235 const seg_entry
*default_seg
= 0;
2237 /* The imul $imm, %reg instruction is converted into
2238 imul $imm, %reg, %reg, and the clr %reg instruction
2239 is converted into xor %reg, %reg. */
2240 if (i
.tm
.opcode_modifier
& regKludge
)
2242 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2243 /* Pretend we saw the extra register operand. */
2244 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2245 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2246 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2250 if (i
.tm
.opcode_modifier
& ShortForm
)
2252 /* The register or float register operand is in operand 0 or 1. */
2253 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2254 /* Register goes in low 3 bits of opcode. */
2255 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2256 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2258 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2260 /* Warn about some common errors, but press on regardless.
2261 The first case can be generated by gcc (<= 2.8.1). */
2262 if (i
.operands
== 2)
2264 /* Reversed arguments on faddp, fsubp, etc. */
2265 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2266 i
.op
[1].regs
->reg_name
,
2267 i
.op
[0].regs
->reg_name
);
2271 /* Extraneous `l' suffix on fp insn. */
2272 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2273 i
.op
[0].regs
->reg_name
);
2277 else if (i
.tm
.opcode_modifier
& Modrm
)
2279 /* The opcode is completed (modulo i.tm.extension_opcode which
2280 must be put into the modrm byte).
2281 Now, we make the modrm & index base bytes based on all the
2282 info we've collected. */
2284 /* i.reg_operands MUST be the number of real register operands;
2285 implicit registers do not count. */
2286 if (i
.reg_operands
== 2)
2288 unsigned int source
, dest
;
2289 source
= ((i
.types
[0]
2290 & (Reg
| RegMMX
| RegXMM
2292 | Control
| Debug
| Test
))
2297 /* One of the register operands will be encoded in the
2298 i.tm.reg field, the other in the combined i.tm.mode
2299 and i.tm.regmem fields. If no form of this
2300 instruction supports a memory destination operand,
2301 then we assume the source operand may sometimes be
2302 a memory operand and so we need to store the
2303 destination in the i.rm.reg field. */
2304 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2306 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2307 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2308 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2310 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2315 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2316 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2317 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2319 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2324 { /* If it's not 2 reg operands... */
2327 unsigned int fake_zero_displacement
= 0;
2328 unsigned int op
= ((i
.types
[0] & AnyMem
)
2330 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2337 if (! i
.disp_operands
)
2338 fake_zero_displacement
= 1;
2341 /* Operand is just <disp> */
2342 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2344 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2345 i
.types
[op
] &= ~Disp
;
2346 i
.types
[op
] |= Disp16
;
2348 else if (flag_code
!= CODE_64BIT
)
2350 i
.rm
.regmem
= NO_BASE_REGISTER
;
2351 i
.types
[op
] &= ~Disp
;
2352 i
.types
[op
] |= Disp32
;
2356 /* 64bit mode overwrites the 32bit absolute addressing
2357 by RIP relative addressing and absolute addressing
2358 is encoded by one of the redundant SIB forms. */
2360 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2361 i
.sib
.base
= NO_BASE_REGISTER
;
2362 i
.sib
.index
= NO_INDEX_REGISTER
;
2363 i
.types
[op
] &= ~Disp
;
2364 i
.types
[op
] |= Disp32S
;
2367 else /* ! i.base_reg && i.index_reg */
2369 i
.sib
.index
= i
.index_reg
->reg_num
;
2370 i
.sib
.base
= NO_BASE_REGISTER
;
2371 i
.sib
.scale
= i
.log2_scale_factor
;
2372 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2373 i
.types
[op
] &= ~Disp
;
2374 if (flag_code
!= CODE_64BIT
)
2375 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2377 i
.types
[op
] |= Disp32S
;
2378 if (i
.index_reg
->reg_flags
& RegRex
)
2382 /* RIP addressing for 64bit mode. */
2383 else if (i
.base_reg
->reg_type
== BaseIndex
)
2385 i
.rm
.regmem
= NO_BASE_REGISTER
;
2386 i
.types
[op
] &= ~Disp
;
2387 i
.types
[op
] |= Disp32S
;
2388 i
.flags
[op
] = Operand_PCrel
;
2390 else if (i
.base_reg
->reg_type
& Reg16
)
2392 switch (i
.base_reg
->reg_num
)
2397 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2398 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2405 if ((i
.types
[op
] & Disp
) == 0)
2407 /* fake (%bp) into 0(%bp) */
2408 i
.types
[op
] |= Disp8
;
2409 fake_zero_displacement
= 1;
2412 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2413 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2415 default: /* (%si) -> 4 or (%di) -> 5 */
2416 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2418 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2420 else /* i.base_reg and 32/64 bit mode */
2422 if (flag_code
== CODE_64BIT
2423 && (i
.types
[op
] & Disp
))
2425 if (i
.types
[op
] & Disp8
)
2426 i
.types
[op
] = Disp8
| Disp32S
;
2428 i
.types
[op
] = Disp32S
;
2430 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2431 if (i
.base_reg
->reg_flags
& RegRex
)
2433 i
.sib
.base
= i
.base_reg
->reg_num
;
2434 /* x86-64 ignores REX prefix bit here to avoid
2435 decoder complications. */
2436 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2439 if (i
.disp_operands
== 0)
2441 fake_zero_displacement
= 1;
2442 i
.types
[op
] |= Disp8
;
2445 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2449 i
.sib
.scale
= i
.log2_scale_factor
;
2452 /* <disp>(%esp) becomes two byte modrm
2453 with no index register. We've already
2454 stored the code for esp in i.rm.regmem
2455 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2456 base register besides %esp will not use
2457 the extra modrm byte. */
2458 i
.sib
.index
= NO_INDEX_REGISTER
;
2459 #if ! SCALE1_WHEN_NO_INDEX
2460 /* Another case where we force the second
2462 if (i
.log2_scale_factor
)
2463 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2468 i
.sib
.index
= i
.index_reg
->reg_num
;
2469 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2470 if (i
.index_reg
->reg_flags
& RegRex
)
2473 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2476 if (fake_zero_displacement
)
2478 /* Fakes a zero displacement assuming that i.types[op]
2479 holds the correct displacement size. */
2482 assert (i
.op
[op
].disps
== 0);
2483 exp
= &disp_expressions
[i
.disp_operands
++];
2484 i
.op
[op
].disps
= exp
;
2485 exp
->X_op
= O_constant
;
2486 exp
->X_add_number
= 0;
2487 exp
->X_add_symbol
= (symbolS
*) 0;
2488 exp
->X_op_symbol
= (symbolS
*) 0;
2492 /* Fill in i.rm.reg or i.rm.regmem field with register
2493 operand (if any) based on i.tm.extension_opcode.
2494 Again, we must be careful to make sure that
2495 segment/control/debug/test/MMX registers are coded
2496 into the i.rm.reg field. */
2501 & (Reg
| RegMMX
| RegXMM
2503 | Control
| Debug
| Test
))
2506 & (Reg
| RegMMX
| RegXMM
2508 | Control
| Debug
| Test
))
2511 /* If there is an extension opcode to put here, the
2512 register number must be put into the regmem field. */
2513 if (i
.tm
.extension_opcode
!= None
)
2515 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2516 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2521 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2522 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2526 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2527 we must set it to 3 to indicate this is a register
2528 operand in the regmem field. */
2529 if (!i
.mem_operands
)
2533 /* Fill in i.rm.reg field with extension opcode (if any). */
2534 if (i
.tm
.extension_opcode
!= None
)
2535 i
.rm
.reg
= i
.tm
.extension_opcode
;
2538 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2540 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2541 && i
.op
[0].regs
->reg_num
== 1)
2543 as_bad (_("you can't `pop %%cs'"));
2546 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2547 if (i
.op
[0].regs
->reg_flags
& RegRex
)
2550 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
2554 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2556 /* For the string instructions that allow a segment override
2557 on one of their operands, the default segment is ds. */
2561 /* If a segment was explicitly specified,
2562 and the specified segment is not the default,
2563 use an opcode prefix to select it.
2564 If we never figured out what the default segment is,
2565 then default_seg will be zero at this point,
2566 and the specified segment prefix will always be used. */
2567 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2569 if (! add_prefix (i
.seg
[0]->seg_prefix
))
2573 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2575 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2576 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2580 /* Handle conversion of 'int $3' --> special int3 insn. */
2581 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2583 i
.tm
.base_opcode
= INT3_OPCODE
;
2587 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
2588 && i
.op
[0].disps
->X_op
== O_constant
)
2590 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2591 the absolute address given by the constant. Since ix86 jumps and
2592 calls are pc relative, we need to generate a reloc. */
2593 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2594 i
.op
[0].disps
->X_op
= O_symbol
;
2597 if (i
.tm
.opcode_modifier
& Rex64
)
2600 /* For 8bit registers we would need an empty rex prefix.
2601 Also in the case instruction is already having prefix,
2602 we need to convert old registers to new ones. */
2604 if (((i
.types
[0] & Reg8
) && (i
.op
[0].regs
->reg_flags
& RegRex64
))
2605 || ((i
.types
[1] & Reg8
) && (i
.op
[1].regs
->reg_flags
& RegRex64
))
2606 || ((i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2607 && ((i
.types
[0] & Reg8
) || (i
.types
[1] & Reg8
))))
2611 for (x
= 0; x
< 2; x
++)
2613 /* Look for 8bit operand that does use old registers. */
2614 if (i
.types
[x
] & Reg8
2615 && !(i
.op
[x
].regs
->reg_flags
& RegRex64
))
2617 /* In case it is "hi" register, give up. */
2618 if (i
.op
[x
].regs
->reg_num
> 3)
2619 as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"),
2620 i
.op
[x
].regs
->reg_name
);
2622 /* Otherwise it is equivalent to the extended register.
2623 Since the encoding don't change this is merely cosmetical
2624 cleanup for debug output. */
2626 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2631 if (i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2633 | (i
.rex
.mode64
? 8 : 0)
2634 | (i
.rex
.extX
? 4 : 0)
2635 | (i
.rex
.extY
? 2 : 0)
2636 | (i
.rex
.extZ
? 1 : 0));
2638 /* We are ready to output the insn. */
2643 if (i
.tm
.opcode_modifier
& Jump
)
2650 if (flag_code
== CODE_16BIT
)
2654 if (i
.prefix
[DATA_PREFIX
])
2660 if (i
.prefix
[REX_PREFIX
])
2670 if (i
.prefixes
!= 0 && !intel_syntax
)
2671 as_warn (_("skipping prefixes on this instruction"));
2673 /* It's always a symbol; End frag & setup for relax.
2674 Make sure there is enough room in this frag for the largest
2675 instruction we may generate in md_convert_frag. This is 2
2676 bytes for the opcode and room for the prefix and largest
2678 frag_grow (prefix
+ 2 + size
);
2679 insn_size
+= prefix
+ 1;
2680 /* Prefix and 1 opcode byte go in fr_fix. */
2681 p
= frag_more (prefix
+ 1);
2682 if (i
.prefix
[DATA_PREFIX
])
2683 *p
++ = DATA_PREFIX_OPCODE
;
2684 if (i
.prefix
[REX_PREFIX
])
2685 *p
++ = i
.prefix
[REX_PREFIX
];
2686 *p
= i
.tm
.base_opcode
;
2687 /* 1 possible extra opcode + displacement go in var part.
2688 Pass reloc in fr_var. */
2689 frag_var (rs_machine_dependent
,
2692 ((unsigned char) *p
== JUMP_PC_RELATIVE
2693 ? ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
) | code16
2694 : ENCODE_RELAX_STATE (COND_JUMP
, SMALL
) | code16
),
2695 i
.op
[0].disps
->X_add_symbol
,
2696 i
.op
[0].disps
->X_add_number
,
2699 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
2703 if (i
.tm
.opcode_modifier
& JumpByte
)
2705 /* This is a loop or jecxz type instruction. */
2707 if (i
.prefix
[ADDR_PREFIX
])
2710 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2719 if (flag_code
== CODE_16BIT
)
2722 if (i
.prefix
[DATA_PREFIX
])
2725 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
2735 if (i
.prefix
[REX_PREFIX
])
2737 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
2742 if (i
.prefixes
!= 0 && !intel_syntax
)
2743 as_warn (_("skipping prefixes on this instruction"));
2745 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2747 insn_size
+= 1 + size
;
2748 p
= frag_more (1 + size
);
2752 /* Opcode can be at most two bytes. */
2753 insn_size
+= 2 + size
;
2754 p
= frag_more (2 + size
);
2755 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2757 *p
++ = i
.tm
.base_opcode
& 0xff;
2759 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2760 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.disp_reloc
[0]));
2762 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
2769 if (flag_code
== CODE_16BIT
)
2773 if (i
.prefix
[DATA_PREFIX
])
2779 if (i
.prefix
[REX_PREFIX
])
2789 if (i
.prefixes
!= 0 && !intel_syntax
)
2790 as_warn (_("skipping prefixes on this instruction"));
2792 /* 1 opcode; 2 segment; offset */
2793 insn_size
+= prefix
+ 1 + 2 + size
;
2794 p
= frag_more (prefix
+ 1 + 2 + size
);
2796 if (i
.prefix
[DATA_PREFIX
])
2797 *p
++ = DATA_PREFIX_OPCODE
;
2799 if (i
.prefix
[REX_PREFIX
])
2800 *p
++ = i
.prefix
[REX_PREFIX
];
2802 *p
++ = i
.tm
.base_opcode
;
2803 if (i
.op
[1].imms
->X_op
== O_constant
)
2805 offsetT n
= i
.op
[1].imms
->X_add_number
;
2808 && !fits_in_unsigned_word (n
)
2809 && !fits_in_signed_word (n
))
2811 as_bad (_("16-bit jump out of range"));
2814 md_number_to_chars (p
, n
, size
);
2817 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2818 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.disp_reloc
[0]));
2819 if (i
.op
[0].imms
->X_op
!= O_constant
)
2820 as_bad (_("can't handle non absolute segment in `%s'"),
2822 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
2826 /* Output normal instructions here. */
2829 /* All opcodes on i386 have eighter 1 or 2 bytes. We may use third
2830 byte for the SSE instructions to specify prefix they require. */
2831 if (i
.tm
.base_opcode
& 0xff0000)
2832 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
2834 /* The prefix bytes. */
2836 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2843 md_number_to_chars (p
, (valueT
) *q
, 1);
2847 /* Now the opcode; be careful about word order here! */
2848 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2851 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2857 /* Put out high byte first: can't use md_number_to_chars! */
2858 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2859 *p
= i
.tm
.base_opcode
& 0xff;
2862 /* Now the modrm byte and sib byte (if present). */
2863 if (i
.tm
.opcode_modifier
& Modrm
)
2867 md_number_to_chars (p
,
2868 (valueT
) (i
.rm
.regmem
<< 0
2872 /* If i.rm.regmem == ESP (4)
2873 && i.rm.mode != (Register mode)
2875 ==> need second modrm byte. */
2876 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2878 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2882 md_number_to_chars (p
,
2883 (valueT
) (i
.sib
.base
<< 0
2885 | i
.sib
.scale
<< 6),
2890 if (i
.disp_operands
)
2892 register unsigned int n
;
2894 for (n
= 0; n
< i
.operands
; n
++)
2896 if (i
.types
[n
] & Disp
)
2898 if (i
.op
[n
].disps
->X_op
== O_constant
)
2904 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
2907 if (i
.types
[n
] & Disp8
)
2909 if (i
.types
[n
] & Disp64
)
2912 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
2915 p
= frag_more (size
);
2916 md_number_to_chars (p
, val
, size
);
2922 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
2924 /* The PC relative address is computed relative
2925 to the instruction boundary, so in case immediate
2926 fields follows, we need to adjust the value. */
2927 if (pcrel
&& i
.imm_operands
)
2930 register unsigned int n1
;
2932 for (n1
= 0; n1
< i
.operands
; n1
++)
2933 if (i
.types
[n1
] & Imm
)
2935 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
2938 if (i
.types
[n1
] & (Imm8
| Imm8S
))
2940 if (i
.types
[n1
] & Imm64
)
2945 /* We should find the immediate. */
2946 if (n1
== i
.operands
)
2948 i
.op
[n
].disps
->X_add_number
-= imm_size
;
2951 if (i
.types
[n
] & Disp32S
)
2954 if (i
.types
[n
] & (Disp16
| Disp64
))
2957 if (i
.types
[n
] & Disp64
)
2962 p
= frag_more (size
);
2963 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2964 i
.op
[n
].disps
, pcrel
,
2965 reloc (size
, pcrel
, sign
, i
.disp_reloc
[n
]));
2971 /* Output immediate. */
2974 register unsigned int n
;
2976 for (n
= 0; n
< i
.operands
; n
++)
2978 if (i
.types
[n
] & Imm
)
2980 if (i
.op
[n
].imms
->X_op
== O_constant
)
2986 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
2989 if (i
.types
[n
] & (Imm8
| Imm8S
))
2991 else if (i
.types
[n
] & Imm64
)
2994 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
2997 p
= frag_more (size
);
2998 md_number_to_chars (p
, val
, size
);
3002 /* Not absolute_section.
3003 Need a 32-bit fixup (don't support 8bit
3004 non-absolute imms). Try to support other
3006 #ifdef BFD_ASSEMBLER
3007 enum bfd_reloc_code_real reloc_type
;
3014 if ((i
.types
[n
] & (Imm32S
))
3015 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3017 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3020 if (i
.types
[n
] & (Imm8
| Imm8S
))
3022 if (i
.types
[n
] & Imm64
)
3027 p
= frag_more (size
);
3028 reloc_type
= reloc (size
, 0, sign
, i
.disp_reloc
[0]);
3029 #ifdef BFD_ASSEMBLER
3030 if (reloc_type
== BFD_RELOC_32
3032 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3033 && (i
.op
[n
].imms
->X_op
== O_symbol
3034 || (i
.op
[n
].imms
->X_op
== O_add
3035 && ((symbol_get_value_expression
3036 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3039 /* We don't support dynamic linking on x86-64 yet. */
3040 if (flag_code
== CODE_64BIT
)
3042 reloc_type
= BFD_RELOC_386_GOTPC
;
3043 i
.op
[n
].imms
->X_add_number
+= 3;
3046 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3047 i
.op
[n
].imms
, 0, reloc_type
);
3054 dwarf2_emit_insn (insn_size
);
3061 #endif /* DEBUG386 */
3065 static int i386_immediate
PARAMS ((char *));
3068 i386_immediate (imm_start
)
3071 char *save_input_line_pointer
;
3075 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3077 as_bad (_("only 1 or 2 immediate operands are allowed"));
3081 exp
= &im_expressions
[i
.imm_operands
++];
3082 i
.op
[this_operand
].imms
= exp
;
3084 if (is_space_char (*imm_start
))
3087 save_input_line_pointer
= input_line_pointer
;
3088 input_line_pointer
= imm_start
;
3092 /* We can have operands of the form
3093 <symbol>@GOTOFF+<nnn>
3094 Take the easy way out here and copy everything
3095 into a temporary buffer... */
3098 cp
= strchr (input_line_pointer
, '@');
3105 /* GOT relocations are not supported in 16 bit mode. */
3106 if (flag_code
== CODE_16BIT
)
3107 as_bad (_("GOT relocations not supported in 16 bit mode"));
3109 if (GOT_symbol
== NULL
)
3110 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3112 if (strncmp (cp
+ 1, "PLT", 3) == 0)
3114 if (flag_code
== CODE_64BIT
)
3115 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_PLT32
;
3117 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
3120 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
3122 if (flag_code
== CODE_64BIT
)
3123 as_bad ("GOTOFF relocations are unsupported in 64bit mode.");
3124 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
3127 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
3129 if (flag_code
== CODE_64BIT
)
3130 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOT32
;
3132 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
3135 else if (strncmp (cp
+ 1, "GOTPCREL", 3) == 0)
3137 if (flag_code
== CODE_64BIT
)
3138 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOTPCREL
;
3140 as_bad ("GOTPCREL relocations are supported only in 64bit mode.");
3144 as_bad (_("bad reloc specifier in expression"));
3146 /* Replace the relocation token with ' ', so that errors like
3147 foo@GOTOFF1 will be detected. */
3148 first
= cp
- input_line_pointer
;
3149 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
3150 memcpy (tmpbuf
, input_line_pointer
, first
);
3151 tmpbuf
[first
] = ' ';
3152 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
3153 input_line_pointer
= tmpbuf
;
3158 exp_seg
= expression (exp
);
3161 if (*input_line_pointer
)
3162 as_bad (_("ignoring junk `%s' after expression"), input_line_pointer
);
3164 input_line_pointer
= save_input_line_pointer
;
3166 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3168 /* Missing or bad expr becomes absolute 0. */
3169 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3171 exp
->X_op
= O_constant
;
3172 exp
->X_add_number
= 0;
3173 exp
->X_add_symbol
= (symbolS
*) 0;
3174 exp
->X_op_symbol
= (symbolS
*) 0;
3176 else if (exp
->X_op
== O_constant
)
3178 /* Size it properly later. */
3179 i
.types
[this_operand
] |= Imm64
;
3180 /* If BFD64, sign extend val. */
3181 if (!use_rela_relocations
)
3182 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3183 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3185 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3187 #ifdef BFD_ASSEMBLER
3188 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3190 && exp_seg
!= text_section
3191 && exp_seg
!= data_section
3192 && exp_seg
!= bss_section
3193 && exp_seg
!= undefined_section
3194 #ifdef BFD_ASSEMBLER
3195 && !bfd_is_com_section (exp_seg
)
3199 #ifdef BFD_ASSEMBLER
3200 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3202 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3209 /* This is an address. The size of the address will be
3210 determined later, depending on destination register,
3211 suffix, or the default for the section. */
3212 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3218 static int i386_scale
PARAMS ((char *));
3224 if (!isdigit (*scale
))
3231 i
.log2_scale_factor
= 0;
3234 i
.log2_scale_factor
= 1;
3237 i
.log2_scale_factor
= 2;
3240 i
.log2_scale_factor
= 3;
3244 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3248 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
3250 as_warn (_("scale factor of %d without an index register"),
3251 1 << i
.log2_scale_factor
);
3252 #if SCALE1_WHEN_NO_INDEX
3253 i
.log2_scale_factor
= 0;
3259 static int i386_displacement
PARAMS ((char *, char *));
3262 i386_displacement (disp_start
, disp_end
)
3266 register expressionS
*exp
;
3268 char *save_input_line_pointer
;
3269 int bigdisp
= Disp32
;
3271 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3273 if (flag_code
== CODE_64BIT
)
3275 i
.types
[this_operand
] |= bigdisp
;
3277 exp
= &disp_expressions
[i
.disp_operands
];
3278 i
.op
[this_operand
].disps
= exp
;
3280 save_input_line_pointer
= input_line_pointer
;
3281 input_line_pointer
= disp_start
;
3282 END_STRING_AND_SAVE (disp_end
);
3284 #ifndef GCC_ASM_O_HACK
3285 #define GCC_ASM_O_HACK 0
3288 END_STRING_AND_SAVE (disp_end
+ 1);
3289 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3290 && displacement_string_end
[-1] == '+')
3292 /* This hack is to avoid a warning when using the "o"
3293 constraint within gcc asm statements.
3296 #define _set_tssldt_desc(n,addr,limit,type) \
3297 __asm__ __volatile__ ( \
3299 "movw %w1,2+%0\n\t" \
3301 "movb %b1,4+%0\n\t" \
3302 "movb %4,5+%0\n\t" \
3303 "movb $0,6+%0\n\t" \
3304 "movb %h1,7+%0\n\t" \
3306 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3308 This works great except that the output assembler ends
3309 up looking a bit weird if it turns out that there is
3310 no offset. You end up producing code that looks like:
3323 So here we provide the missing zero. */
3325 *displacement_string_end
= '0';
3330 /* We can have operands of the form
3331 <symbol>@GOTOFF+<nnn>
3332 Take the easy way out here and copy everything
3333 into a temporary buffer... */
3336 cp
= strchr (input_line_pointer
, '@');
3343 /* GOT relocations are not supported in 16 bit mode. */
3344 if (flag_code
== CODE_16BIT
)
3345 as_bad (_("GOT relocations not supported in 16 bit mode"));
3347 if (GOT_symbol
== NULL
)
3348 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3350 if (strncmp (cp
+ 1, "PLT", 3) == 0)
3352 if (flag_code
== CODE_64BIT
)
3353 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_PLT32
;
3355 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
3358 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
3360 if (flag_code
== CODE_64BIT
)
3361 as_bad ("GOTOFF relocation is not supported in 64bit mode.");
3362 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
3365 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
3367 if (flag_code
== CODE_64BIT
)
3368 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOT32
;
3370 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
3373 else if (strncmp (cp
+ 1, "GOTPCREL", 3) == 0)
3375 if (flag_code
!= CODE_64BIT
)
3376 as_bad ("GOTPCREL relocation is supported only in 64bit mode.");
3377 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOTPCREL
;
3381 as_bad (_("bad reloc specifier in expression"));
3383 /* Replace the relocation token with ' ', so that errors like
3384 foo@GOTOFF1 will be detected. */
3385 first
= cp
- input_line_pointer
;
3386 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
3387 memcpy (tmpbuf
, input_line_pointer
, first
);
3388 tmpbuf
[first
] = ' ';
3389 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
3390 input_line_pointer
= tmpbuf
;
3395 exp_seg
= expression (exp
);
3397 #ifdef BFD_ASSEMBLER
3398 /* We do this to make sure that the section symbol is in
3399 the symbol table. We will ultimately change the relocation
3400 to be relative to the beginning of the section. */
3401 if (i
.disp_reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3402 || i
.disp_reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3404 if (S_IS_LOCAL(exp
->X_add_symbol
)
3405 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3406 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3407 assert (exp
->X_op
== O_symbol
);
3408 exp
->X_op
= O_subtract
;
3409 exp
->X_op_symbol
= GOT_symbol
;
3410 i
.disp_reloc
[this_operand
] = BFD_RELOC_32
;
3415 if (*input_line_pointer
)
3416 as_bad (_("ignoring junk `%s' after expression"),
3417 input_line_pointer
);
3419 RESTORE_END_STRING (disp_end
+ 1);
3421 RESTORE_END_STRING (disp_end
);
3422 input_line_pointer
= save_input_line_pointer
;
3424 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3426 /* Missing or bad expr becomes absolute 0. */
3427 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3429 exp
->X_op
= O_constant
;
3430 exp
->X_add_number
= 0;
3431 exp
->X_add_symbol
= (symbolS
*) 0;
3432 exp
->X_op_symbol
= (symbolS
*) 0;
3435 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3436 if (exp
->X_op
!= O_constant
3437 #ifdef BFD_ASSEMBLER
3438 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3440 && exp_seg
!= text_section
3441 && exp_seg
!= data_section
3442 && exp_seg
!= bss_section
3443 && exp_seg
!= undefined_section
)
3445 #ifdef BFD_ASSEMBLER
3446 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3448 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3453 else if (flag_code
== CODE_64BIT
)
3454 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3458 static int i386_index_check
PARAMS((const char *));
3460 /* Make sure the memory operand we've been dealt is valid.
3461 Return 1 on success, 0 on a failure. */
3464 i386_index_check (operand_string
)
3465 const char *operand_string
;
3468 #if INFER_ADDR_PREFIX
3474 if (flag_code
== CODE_64BIT
)
3478 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3479 && (i
.base_reg
->reg_type
!= BaseIndex
3482 && ((i
.index_reg
->reg_type
& (Reg64
|BaseIndex
))
3483 != (Reg64
|BaseIndex
))))
3488 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3492 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
|RegRex
))
3493 != (Reg16
|BaseIndex
)))
3495 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
3496 != (Reg16
|BaseIndex
))
3498 && i
.base_reg
->reg_num
< 6
3499 && i
.index_reg
->reg_num
>= 6
3500 && i
.log2_scale_factor
== 0))))
3507 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3509 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
|RegRex
))
3510 != (Reg32
|BaseIndex
))))
3516 #if INFER_ADDR_PREFIX
3517 if (flag_code
!= CODE_64BIT
3518 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3520 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3522 /* Change the size of any displacement too. At most one of
3523 Disp16 or Disp32 is set.
3524 FIXME. There doesn't seem to be any real need for separate
3525 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3526 Removing them would probably clean up the code quite a lot. */
3527 if (i
.types
[this_operand
] & (Disp16
|Disp32
))
3528 i
.types
[this_operand
] ^= (Disp16
|Disp32
);
3533 as_bad (_("`%s' is not a valid base/index expression"),
3537 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3539 flag_code_names
[flag_code
]);
3545 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3549 i386_operand (operand_string
)
3550 char *operand_string
;
3554 char *op_string
= operand_string
;
3556 if (is_space_char (*op_string
))
3559 /* We check for an absolute prefix (differentiating,
3560 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3561 if (*op_string
== ABSOLUTE_PREFIX
)
3564 if (is_space_char (*op_string
))
3566 i
.types
[this_operand
] |= JumpAbsolute
;
3569 /* Check if operand is a register. */
3570 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3571 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3573 /* Check for a segment override by searching for ':' after a
3574 segment register. */
3576 if (is_space_char (*op_string
))
3578 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3583 i
.seg
[i
.mem_operands
] = &es
;
3586 i
.seg
[i
.mem_operands
] = &cs
;
3589 i
.seg
[i
.mem_operands
] = &ss
;
3592 i
.seg
[i
.mem_operands
] = &ds
;
3595 i
.seg
[i
.mem_operands
] = &fs
;
3598 i
.seg
[i
.mem_operands
] = &gs
;
3602 /* Skip the ':' and whitespace. */
3604 if (is_space_char (*op_string
))
3607 if (!is_digit_char (*op_string
)
3608 && !is_identifier_char (*op_string
)
3609 && *op_string
!= '('
3610 && *op_string
!= ABSOLUTE_PREFIX
)
3612 as_bad (_("bad memory operand `%s'"), op_string
);
3615 /* Handle case of %es:*foo. */
3616 if (*op_string
== ABSOLUTE_PREFIX
)
3619 if (is_space_char (*op_string
))
3621 i
.types
[this_operand
] |= JumpAbsolute
;
3623 goto do_memory_reference
;
3627 as_bad (_("junk `%s' after register"), op_string
);
3630 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3631 i
.op
[this_operand
].regs
= r
;
3634 else if (*op_string
== REGISTER_PREFIX
)
3636 as_bad (_("bad register name `%s'"), op_string
);
3639 else if (*op_string
== IMMEDIATE_PREFIX
)
3642 if (i
.types
[this_operand
] & JumpAbsolute
)
3644 as_bad (_("immediate operand illegal with absolute jump"));
3647 if (!i386_immediate (op_string
))
3650 else if (is_digit_char (*op_string
)
3651 || is_identifier_char (*op_string
)
3652 || *op_string
== '(' )
3654 /* This is a memory reference of some sort. */
3657 /* Start and end of displacement string expression (if found). */
3658 char *displacement_string_start
;
3659 char *displacement_string_end
;
3661 do_memory_reference
:
3662 if ((i
.mem_operands
== 1
3663 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3664 || i
.mem_operands
== 2)
3666 as_bad (_("too many memory references for `%s'"),
3667 current_templates
->start
->name
);
3671 /* Check for base index form. We detect the base index form by
3672 looking for an ')' at the end of the operand, searching
3673 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3675 base_string
= op_string
+ strlen (op_string
);
3678 if (is_space_char (*base_string
))
3681 /* If we only have a displacement, set-up for it to be parsed later. */
3682 displacement_string_start
= op_string
;
3683 displacement_string_end
= base_string
+ 1;
3685 if (*base_string
== ')')
3688 unsigned int parens_balanced
= 1;
3689 /* We've already checked that the number of left & right ()'s are
3690 equal, so this loop will not be infinite. */
3694 if (*base_string
== ')')
3696 if (*base_string
== '(')
3699 while (parens_balanced
);
3701 temp_string
= base_string
;
3703 /* Skip past '(' and whitespace. */
3705 if (is_space_char (*base_string
))
3708 if (*base_string
== ','
3709 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3710 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
3712 displacement_string_end
= temp_string
;
3714 i
.types
[this_operand
] |= BaseIndex
;
3718 base_string
= end_op
;
3719 if (is_space_char (*base_string
))
3723 /* There may be an index reg or scale factor here. */
3724 if (*base_string
== ',')
3727 if (is_space_char (*base_string
))
3730 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3731 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
3733 base_string
= end_op
;
3734 if (is_space_char (*base_string
))
3736 if (*base_string
== ',')
3739 if (is_space_char (*base_string
))
3742 else if (*base_string
!= ')' )
3744 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3749 else if (*base_string
== REGISTER_PREFIX
)
3751 as_bad (_("bad register name `%s'"), base_string
);
3755 /* Check for scale factor. */
3756 if (isdigit ((unsigned char) *base_string
))
3758 if (!i386_scale (base_string
))
3762 if (is_space_char (*base_string
))
3764 if (*base_string
!= ')')
3766 as_bad (_("expecting `)' after scale factor in `%s'"),
3771 else if (!i
.index_reg
)
3773 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3778 else if (*base_string
!= ')')
3780 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3785 else if (*base_string
== REGISTER_PREFIX
)
3787 as_bad (_("bad register name `%s'"), base_string
);
3792 /* If there's an expression beginning the operand, parse it,
3793 assuming displacement_string_start and
3794 displacement_string_end are meaningful. */
3795 if (displacement_string_start
!= displacement_string_end
)
3797 if (!i386_displacement (displacement_string_start
,
3798 displacement_string_end
))
3802 /* Special case for (%dx) while doing input/output op. */
3804 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
3806 && i
.log2_scale_factor
== 0
3807 && i
.seg
[i
.mem_operands
] == 0
3808 && (i
.types
[this_operand
] & Disp
) == 0)
3810 i
.types
[this_operand
] = InOutPortReg
;
3814 if (i386_index_check (operand_string
) == 0)
3820 /* It's not a memory operand; argh! */
3821 as_bad (_("invalid char %s beginning operand %d `%s'"),
3822 output_invalid (*op_string
),
3827 return 1; /* Normal return. */
3830 /* md_estimate_size_before_relax()
3832 Called just before relax() for rs_machine_dependent frags. The x86
3833 assembler uses these frags to handle variable size jump
3836 Any symbol that is now undefined will not become defined.
3837 Return the correct fr_subtype in the frag.
3838 Return the initial "guess for variable size of frag" to caller.
3839 The guess is actually the growth beyond the fixed part. Whatever
3840 we do to grow the fixed or variable part contributes to our
3844 md_estimate_size_before_relax (fragP
, segment
)
3845 register fragS
*fragP
;
3846 register segT segment
;
3848 /* We've already got fragP->fr_subtype right; all we have to do is
3849 check for un-relaxable symbols. On an ELF system, we can't relax
3850 an externally visible symbol, because it may be overridden by a
3852 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3853 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3854 || S_IS_EXTERNAL (fragP
->fr_symbol
)
3855 || S_IS_WEAK (fragP
->fr_symbol
)
3859 /* Symbol is undefined in this segment, or we need to keep a
3860 reloc so that weak symbols can be overridden. */
3861 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
3862 #ifdef BFD_ASSEMBLER
3863 enum bfd_reloc_code_real reloc_type
;
3867 unsigned char *opcode
;
3870 if (fragP
->fr_var
!= NO_RELOC
)
3871 reloc_type
= fragP
->fr_var
;
3873 reloc_type
= BFD_RELOC_16_PCREL
;
3875 reloc_type
= BFD_RELOC_32_PCREL
;
3877 old_fr_fix
= fragP
->fr_fix
;
3878 opcode
= (unsigned char *) fragP
->fr_opcode
;
3882 case JUMP_PC_RELATIVE
:
3883 /* Make jmp (0xeb) a dword displacement jump. */
3885 fragP
->fr_fix
+= size
;
3886 fix_new (fragP
, old_fr_fix
, size
,
3888 fragP
->fr_offset
, 1,
3893 /* This changes the byte-displacement jump 0x7N
3894 to the dword-displacement jump 0x0f,0x8N. */
3895 opcode
[1] = opcode
[0] + 0x10;
3896 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3897 /* We've added an opcode byte. */
3898 fragP
->fr_fix
+= 1 + size
;
3899 fix_new (fragP
, old_fr_fix
+ 1, size
,
3901 fragP
->fr_offset
, 1,
3906 return fragP
->fr_fix
- old_fr_fix
;
3908 /* Guess a short jump. */
3912 /* Called after relax() is finished.
3914 In: Address of frag.
3915 fr_type == rs_machine_dependent.
3916 fr_subtype is what the address relaxed to.
3918 Out: Any fixSs and constants are set up.
3919 Caller will turn frag into a ".space 0". */
3921 #ifndef BFD_ASSEMBLER
3923 md_convert_frag (headers
, sec
, fragP
)
3924 object_headers
*headers ATTRIBUTE_UNUSED
;
3925 segT sec ATTRIBUTE_UNUSED
;
3926 register fragS
*fragP
;
3929 md_convert_frag (abfd
, sec
, fragP
)
3930 bfd
*abfd ATTRIBUTE_UNUSED
;
3931 segT sec ATTRIBUTE_UNUSED
;
3932 register fragS
*fragP
;
3935 register unsigned char *opcode
;
3936 unsigned char *where_to_put_displacement
= NULL
;
3937 offsetT target_address
;
3938 offsetT opcode_address
;
3939 unsigned int extension
= 0;
3940 offsetT displacement_from_opcode_start
;
3942 opcode
= (unsigned char *) fragP
->fr_opcode
;
3944 /* Address we want to reach in file space. */
3945 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
3946 #ifdef BFD_ASSEMBLER
3947 /* Not needed otherwise? */
3948 target_address
+= symbol_get_frag (fragP
->fr_symbol
)->fr_address
;
3951 /* Address opcode resides at in file space. */
3952 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
3954 /* Displacement from opcode start to fill into instruction. */
3955 displacement_from_opcode_start
= target_address
- opcode_address
;
3957 switch (fragP
->fr_subtype
)
3959 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL
):
3960 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL16
):
3961 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
):
3962 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL16
):
3963 /* Don't have to change opcode. */
3964 extension
= 1; /* 1 opcode + 1 displacement */
3965 where_to_put_displacement
= &opcode
[1];
3968 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
3969 extension
= 5; /* 2 opcode + 4 displacement */
3970 opcode
[1] = opcode
[0] + 0x10;
3971 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3972 where_to_put_displacement
= &opcode
[2];
3975 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
3976 extension
= 4; /* 1 opcode + 4 displacement */
3978 where_to_put_displacement
= &opcode
[1];
3981 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
3982 extension
= 3; /* 2 opcode + 2 displacement */
3983 opcode
[1] = opcode
[0] + 0x10;
3984 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3985 where_to_put_displacement
= &opcode
[2];
3988 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
3989 extension
= 2; /* 1 opcode + 2 displacement */
3991 where_to_put_displacement
= &opcode
[1];
3995 BAD_CASE (fragP
->fr_subtype
);
3998 /* Now put displacement after opcode. */
3999 md_number_to_chars ((char *) where_to_put_displacement
,
4000 (valueT
) (displacement_from_opcode_start
- extension
),
4001 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4002 fragP
->fr_fix
+= extension
;
4005 /* Size of byte displacement jmp. */
4006 int md_short_jump_size
= 2;
4008 /* Size of dword displacement jmp. */
4009 int md_long_jump_size
= 5;
4011 /* Size of relocation record. */
4012 const int md_reloc_size
= 8;
4015 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4017 addressT from_addr
, to_addr
;
4018 fragS
*frag ATTRIBUTE_UNUSED
;
4019 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4023 offset
= to_addr
- (from_addr
+ 2);
4024 /* Opcode for byte-disp jump. */
4025 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4026 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4030 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4032 addressT from_addr
, to_addr
;
4033 fragS
*frag ATTRIBUTE_UNUSED
;
4034 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4038 offset
= to_addr
- (from_addr
+ 5);
4039 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4040 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4043 /* Apply a fixup (fixS) to segment data, once it has been determined
4044 by our caller that we have all the info we need to fix it up.
4046 On the 386, immediates, displacements, and data pointers are all in
4047 the same (little-endian) format, so we don't need to care about which
4051 md_apply_fix3 (fixP
, valp
, seg
)
4052 /* The fix we're to put in. */
4055 /* Pointer to the value of the bits. */
4058 /* Segment fix is from. */
4059 segT seg ATTRIBUTE_UNUSED
;
4061 register char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4062 valueT value
= *valp
;
4064 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4067 switch (fixP
->fx_r_type
)
4073 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4076 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4079 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4084 /* This is a hack. There should be a better way to handle this.
4085 This covers for the fact that bfd_install_relocation will
4086 subtract the current location (for partial_inplace, PC relative
4087 relocations); see more below. */
4088 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4089 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4090 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4094 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4096 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4099 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4101 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4102 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4104 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4107 || (symbol_section_p (fixP
->fx_addsy
)
4108 && fseg
!= absolute_section
))
4109 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
4110 && ! S_IS_WEAK (fixP
->fx_addsy
)
4111 && S_IS_DEFINED (fixP
->fx_addsy
)
4112 && ! S_IS_COMMON (fixP
->fx_addsy
))
4114 /* Yes, we add the values in twice. This is because
4115 bfd_perform_relocation subtracts them out again. I think
4116 bfd_perform_relocation is broken, but I don't dare change
4118 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4122 #if defined (OBJ_COFF) && defined (TE_PE)
4123 /* For some reason, the PE format does not store a section
4124 address offset for a PC relative symbol. */
4125 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4126 value
+= md_pcrel_from (fixP
);
4130 /* Fix a few things - the dynamic linker expects certain values here,
4131 and we must not dissappoint it. */
4132 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4133 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4135 switch (fixP
->fx_r_type
)
4137 case BFD_RELOC_386_PLT32
:
4138 case BFD_RELOC_X86_64_PLT32
:
4139 /* Make the jump instruction point to the address of the operand. At
4140 runtime we merely add the offset to the actual PLT entry. */
4143 case BFD_RELOC_386_GOTPC
:
4145 /* This is tough to explain. We end up with this one if we have
4146 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4147 * here is to obtain the absolute address of the GOT, and it is strongly
4148 * preferable from a performance point of view to avoid using a runtime
4149 * relocation for this. The actual sequence of instructions often look
4155 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4157 * The call and pop essentially return the absolute address of
4158 * the label .L66 and store it in %ebx. The linker itself will
4159 * ultimately change the first operand of the addl so that %ebx points to
4160 * the GOT, but to keep things simple, the .o file must have this operand
4161 * set so that it generates not the absolute address of .L66, but the
4162 * absolute address of itself. This allows the linker itself simply
4163 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4164 * added in, and the addend of the relocation is stored in the operand
4165 * field for the instruction itself.
4167 * Our job here is to fix the operand so that it would add the correct
4168 * offset so that %ebx would point to itself. The thing that is tricky is
4169 * that .-.L66 will point to the beginning of the instruction, so we need
4170 * to further modify the operand so that it will point to itself.
4171 * There are other cases where you have something like:
4173 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4175 * and here no correction would be required. Internally in the assembler
4176 * we treat operands of this form as not being pcrel since the '.' is
4177 * explicitly mentioned, and I wonder whether it would simplify matters
4178 * to do it this way. Who knows. In earlier versions of the PIC patches,
4179 * the pcrel_adjust field was used to store the correction, but since the
4180 * expression is not pcrel, I felt it would be confusing to do it this
4185 case BFD_RELOC_386_GOT32
:
4186 case BFD_RELOC_X86_64_GOT32
:
4187 value
= 0; /* Fully resolved at runtime. No addend. */
4189 case BFD_RELOC_386_GOTOFF
:
4190 case BFD_RELOC_X86_64_GOTPCREL
:
4193 case BFD_RELOC_VTABLE_INHERIT
:
4194 case BFD_RELOC_VTABLE_ENTRY
:
4201 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4203 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4205 #ifndef BFD_ASSEMBLER
4206 md_number_to_chars (p
, value
, fixP
->fx_size
);
4208 /* Are we finished with this relocation now? */
4209 if (fixP
->fx_addsy
== 0 && fixP
->fx_pcrel
== 0)
4211 else if (use_rela_relocations
)
4213 fixP
->fx_no_overflow
= 1;
4216 md_number_to_chars (p
, value
, fixP
->fx_size
);
4222 #define MAX_LITTLENUMS 6
4224 /* Turn the string pointed to by litP into a floating point constant
4225 of type TYPE, and emit the appropriate bytes. The number of
4226 LITTLENUMS emitted is stored in *SIZEP. An error message is
4227 returned, or NULL on OK. */
4230 md_atof (type
, litP
, sizeP
)
4236 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4237 LITTLENUM_TYPE
*wordP
;
4259 return _("Bad call to md_atof ()");
4261 t
= atof_ieee (input_line_pointer
, type
, words
);
4263 input_line_pointer
= t
;
4265 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4266 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4267 the bigendian 386. */
4268 for (wordP
= words
+ prec
- 1; prec
--;)
4270 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4271 litP
+= sizeof (LITTLENUM_TYPE
);
4276 char output_invalid_buf
[8];
4283 sprintf (output_invalid_buf
, "'%c'", c
);
4285 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4286 return output_invalid_buf
;
4289 /* REG_STRING starts *before* REGISTER_PREFIX. */
4291 static const reg_entry
*
4292 parse_register (reg_string
, end_op
)
4296 char *s
= reg_string
;
4298 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4301 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4302 if (*s
== REGISTER_PREFIX
)
4305 if (is_space_char (*s
))
4309 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4311 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4312 return (const reg_entry
*) NULL
;
4316 /* For naked regs, make sure that we are not dealing with an identifier.
4317 This prevents confusing an identifier like `eax_var' with register
4319 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4320 return (const reg_entry
*) NULL
;
4324 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4326 /* Handle floating point regs, allowing spaces in the (i) part. */
4327 if (r
== i386_regtab
/* %st is first entry of table */)
4329 if (is_space_char (*s
))
4334 if (is_space_char (*s
))
4336 if (*s
>= '0' && *s
<= '7')
4338 r
= &i386_float_regtab
[*s
- '0'];
4340 if (is_space_char (*s
))
4348 /* We have "%st(" then garbage. */
4349 return (const reg_entry
*) NULL
;
4356 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4357 const char *md_shortopts
= "kVQ:sq";
4359 const char *md_shortopts
= "q";
4361 struct option md_longopts
[] = {
4362 #define OPTION_32 (OPTION_MD_BASE + 0)
4363 {"32", no_argument
, NULL
, OPTION_32
},
4364 #define OPTION_64 (OPTION_MD_BASE + 1)
4365 {"64", no_argument
, NULL
, OPTION_64
},
4366 {NULL
, no_argument
, NULL
, 0}
4368 size_t md_longopts_size
= sizeof (md_longopts
);
4371 md_parse_option (c
, arg
)
4373 char *arg ATTRIBUTE_UNUSED
;
4381 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4382 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4383 should be emitted or not. FIXME: Not implemented. */
4387 /* -V: SVR4 argument to print version ID. */
4389 print_version_id ();
4392 /* -k: Ignore for FreeBSD compatibility. */
4397 /* -s: On i386 Solaris, this tells the native assembler to use
4398 .stab instead of .stab.excl. We always use .stab anyhow. */
4405 const char **list
, **l
;
4407 default_arch
= c
== OPTION_32
? "i386" : "x86_64";
4408 list
= bfd_target_list ();
4409 for (l
= list
; *l
!= NULL
; l
++)
4413 if (strcmp (*l
, "elf32-i386") == 0)
4418 if (strcmp (*l
, "elf64-x86-64") == 0)
4423 as_fatal (_("No compiled in support for %d bit object file format"),
4424 c
== OPTION_32
? 32 : 64);
4437 md_show_usage (stream
)
4440 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4441 fprintf (stream
, _("\
4443 -V print assembler version number\n\
4445 -q quieten some warnings\n\
4448 fprintf (stream
, _("\
4449 -q quieten some warnings\n"));
4453 #ifdef BFD_ASSEMBLER
4454 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4455 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4457 /* Pick the target format to use. */
4460 i386_target_format ()
4462 if (!strcmp (default_arch
, "x86_64"))
4463 set_code_flag (CODE_64BIT
);
4464 else if (!strcmp (default_arch
, "i386"))
4465 set_code_flag (CODE_32BIT
);
4467 as_fatal (_("Unknown architecture"));
4468 switch (OUTPUT_FLAVOR
)
4470 #ifdef OBJ_MAYBE_AOUT
4471 case bfd_target_aout_flavour
:
4472 return AOUT_TARGET_FORMAT
;
4474 #ifdef OBJ_MAYBE_COFF
4475 case bfd_target_coff_flavour
:
4478 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4479 case bfd_target_elf_flavour
:
4481 if (flag_code
== CODE_64BIT
)
4482 use_rela_relocations
= 1;
4483 return flag_code
== CODE_64BIT
? "elf64-x86-64" : "elf32-i386";
4492 #endif /* OBJ_MAYBE_ more than one */
4493 #endif /* BFD_ASSEMBLER */
4496 md_undefined_symbol (name
)
4499 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4500 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4501 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4502 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4506 if (symbol_find (name
))
4507 as_bad (_("GOT already in symbol table"));
4508 GOT_symbol
= symbol_new (name
, undefined_section
,
4509 (valueT
) 0, &zero_address_frag
);
4516 /* Round up a section size to the appropriate boundary. */
4519 md_section_align (segment
, size
)
4520 segT segment ATTRIBUTE_UNUSED
;
4523 #ifdef BFD_ASSEMBLER
4524 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4525 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4527 /* For a.out, force the section size to be aligned. If we don't do
4528 this, BFD will align it for us, but it will not write out the
4529 final bytes of the section. This may be a bug in BFD, but it is
4530 easier to fix it here since that is how the other a.out targets
4534 align
= bfd_get_section_alignment (stdoutput
, segment
);
4535 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4543 /* On the i386, PC-relative offsets are relative to the start of the
4544 next instruction. That is, the address of the offset, plus its
4545 size, since the offset is always the last part of the insn. */
4548 md_pcrel_from (fixP
)
4551 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4558 int ignore ATTRIBUTE_UNUSED
;
4562 temp
= get_absolute_expression ();
4563 subseg_set (bss_section
, (subsegT
) temp
);
4564 demand_empty_rest_of_line ();
4569 #ifdef BFD_ASSEMBLER
4572 i386_validate_fix (fixp
)
4575 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
4577 /* GOTOFF relocation are nonsense in 64bit mode. */
4578 if (flag_code
== CODE_64BIT
)
4580 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
4586 tc_gen_reloc (section
, fixp
)
4587 asection
*section ATTRIBUTE_UNUSED
;
4591 bfd_reloc_code_real_type code
;
4593 switch (fixp
->fx_r_type
)
4595 case BFD_RELOC_X86_64_PLT32
:
4596 case BFD_RELOC_X86_64_GOT32
:
4597 case BFD_RELOC_X86_64_GOTPCREL
:
4598 case BFD_RELOC_386_PLT32
:
4599 case BFD_RELOC_386_GOT32
:
4600 case BFD_RELOC_386_GOTOFF
:
4601 case BFD_RELOC_386_GOTPC
:
4602 case BFD_RELOC_X86_64_32S
:
4604 case BFD_RELOC_VTABLE_ENTRY
:
4605 case BFD_RELOC_VTABLE_INHERIT
:
4606 code
= fixp
->fx_r_type
;
4611 switch (fixp
->fx_size
)
4614 as_bad (_("can not do %d byte pc-relative relocation"),
4616 code
= BFD_RELOC_32_PCREL
;
4618 case 1: code
= BFD_RELOC_8_PCREL
; break;
4619 case 2: code
= BFD_RELOC_16_PCREL
; break;
4620 case 4: code
= BFD_RELOC_32_PCREL
; break;
4625 switch (fixp
->fx_size
)
4628 as_bad (_("can not do %d byte relocation"), fixp
->fx_size
);
4629 code
= BFD_RELOC_32
;
4631 case 1: code
= BFD_RELOC_8
; break;
4632 case 2: code
= BFD_RELOC_16
; break;
4633 case 4: code
= BFD_RELOC_32
; break;
4634 case 8: code
= BFD_RELOC_64
; break;
4640 if (code
== BFD_RELOC_32
4642 && fixp
->fx_addsy
== GOT_symbol
)
4644 /* We don't support GOTPC on 64bit targets. */
4645 if (flag_code
== CODE_64BIT
)
4647 code
= BFD_RELOC_386_GOTPC
;
4650 rel
= (arelent
*) xmalloc (sizeof (arelent
));
4651 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4652 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4654 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4655 if (!use_rela_relocations
)
4657 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4658 vtable entry to be used in the relocation's section offset. */
4659 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4660 rel
->address
= fixp
->fx_offset
;
4663 rel
->addend
= fixp
->fx_addnumber
;
4667 /* Use the rela in 64bit mode. */
4670 rel
->addend
= fixp
->fx_offset
;
4672 /* Ohhh, this is ugly. The problem is that if this is a local global
4673 symbol, the relocation will entirely be performed at link time, not
4674 at assembly time. bfd_perform_reloc doesn't know about this sort
4675 of thing, and as a result we need to fake it out here. */
4676 if ((S_IS_EXTERN (fixp
->fx_addsy
) || S_IS_WEAK (fixp
->fx_addsy
))
4677 && !S_IS_COMMON(fixp
->fx_addsy
))
4678 rel
->addend
-= symbol_get_bfdsym (fixp
->fx_addsy
)->value
;
4681 rel
->addend
-= fixp
->fx_size
;
4685 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4686 if (rel
->howto
== NULL
)
4688 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4689 _("cannot represent relocation type %s"),
4690 bfd_get_reloc_code_name (code
));
4691 /* Set howto to a garbage value so that we can keep going. */
4692 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
4693 assert (rel
->howto
!= NULL
);
4699 #else /* ! BFD_ASSEMBLER */
4701 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4703 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4706 relax_addressT segment_address_in_file
;
4708 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4709 Out: GNU LD relocation length code: 0, 1, or 2. */
4711 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
4714 know (fixP
->fx_addsy
!= NULL
);
4716 md_number_to_chars (where
,
4717 (valueT
) (fixP
->fx_frag
->fr_address
4718 + fixP
->fx_where
- segment_address_in_file
),
4721 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4722 ? S_GET_TYPE (fixP
->fx_addsy
)
4723 : fixP
->fx_addsy
->sy_number
);
4725 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
4726 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4727 where
[4] = r_symbolnum
& 0x0ff;
4728 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
4729 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
4730 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
4733 #endif /* OBJ_AOUT or OBJ_BOUT. */
4735 #if defined (I386COFF)
4738 tc_coff_fix2rtype (fixP
)
4741 if (fixP
->fx_r_type
== R_IMAGEBASE
)
4744 return (fixP
->fx_pcrel
?
4745 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
4746 fixP
->fx_size
== 2 ? R_PCRWORD
:
4748 (fixP
->fx_size
== 1 ? R_RELBYTE
:
4749 fixP
->fx_size
== 2 ? R_RELWORD
:
4754 tc_coff_sizemachdep (frag
)
4758 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
4763 #endif /* I386COFF */
4765 #endif /* ! BFD_ASSEMBLER */
4767 /* Parse operands using Intel syntax. This implements a recursive descent
4768 parser based on the BNF grammar published in Appendix B of the MASM 6.1
4771 FIXME: We do not recognize the full operand grammar defined in the MASM
4772 documentation. In particular, all the structure/union and
4773 high-level macro operands are missing.
4775 Uppercase words are terminals, lower case words are non-terminals.
4776 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
4777 bars '|' denote choices. Most grammar productions are implemented in
4778 functions called 'intel_<production>'.
4780 Initial production is 'expr'.
4786 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
4788 constant digits [[ radixOverride ]]
4790 dataType BYTE | WORD | DWORD | QWORD | XWORD
4823 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
4824 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
4826 hexdigit a | b | c | d | e | f
4827 | A | B | C | D | E | F
4837 register specialRegister
4841 segmentRegister CS | DS | ES | FS | GS | SS
4843 specialRegister CR0 | CR2 | CR3
4844 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
4845 | TR3 | TR4 | TR5 | TR6 | TR7
4847 We simplify the grammar in obvious places (e.g., register parsing is
4848 done by calling parse_register) and eliminate immediate left recursion
4849 to implement a recursive-descent parser.
4889 /* Parsing structure for the intel syntax parser. Used to implement the
4890 semantic actions for the operand grammar. */
4891 struct intel_parser_s
4893 char *op_string
; /* The string being parsed. */
4894 int got_a_float
; /* Whether the operand is a float. */
4895 int op_modifier
; /* Operand modifier. */
4896 int is_mem
; /* 1 if operand is memory reference. */
4897 const reg_entry
*reg
; /* Last register reference found. */
4898 char *disp
; /* Displacement string being built. */
4901 static struct intel_parser_s intel_parser
;
4903 /* Token structure for parsing intel syntax. */
4906 int code
; /* Token code. */
4907 const reg_entry
*reg
; /* Register entry for register tokens. */
4908 char *str
; /* String representation. */
4911 static struct intel_token cur_token
, prev_token
;
4914 /* Token codes for the intel parser. Since T_SHORT is already used
4915 by COFF, undefine it first to prevent a warning. */
4930 /* Prototypes for intel parser functions. */
4931 static int intel_match_token
PARAMS ((int code
));
4932 static void intel_get_token
PARAMS ((void));
4933 static void intel_putback_token
PARAMS ((void));
4934 static int intel_expr
PARAMS ((void));
4935 static int intel_e05
PARAMS ((void));
4936 static int intel_e05_1
PARAMS ((void));
4937 static int intel_e06
PARAMS ((void));
4938 static int intel_e06_1
PARAMS ((void));
4939 static int intel_e09
PARAMS ((void));
4940 static int intel_e09_1
PARAMS ((void));
4941 static int intel_e10
PARAMS ((void));
4942 static int intel_e10_1
PARAMS ((void));
4943 static int intel_e11
PARAMS ((void));
4946 i386_intel_operand (operand_string
, got_a_float
)
4947 char *operand_string
;
4953 /* Initialize token holders. */
4954 cur_token
.code
= prev_token
.code
= T_NIL
;
4955 cur_token
.reg
= prev_token
.reg
= NULL
;
4956 cur_token
.str
= prev_token
.str
= NULL
;
4958 /* Initialize parser structure. */
4959 p
= intel_parser
.op_string
= (char *)malloc (strlen (operand_string
) + 1);
4962 strcpy (intel_parser
.op_string
, operand_string
);
4963 intel_parser
.got_a_float
= got_a_float
;
4964 intel_parser
.op_modifier
= -1;
4965 intel_parser
.is_mem
= 0;
4966 intel_parser
.reg
= NULL
;
4967 intel_parser
.disp
= (char *)malloc (strlen (operand_string
) + 1);
4968 if (intel_parser
.disp
== NULL
)
4970 intel_parser
.disp
[0] = '\0';
4972 /* Read the first token and start the parser. */
4974 ret
= intel_expr ();
4978 /* If we found a memory reference, hand it over to i386_displacement
4979 to fill in the rest of the operand fields. */
4980 if (intel_parser
.is_mem
)
4982 if ((i
.mem_operands
== 1
4983 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4984 || i
.mem_operands
== 2)
4986 as_bad (_("too many memory references for '%s'"),
4987 current_templates
->start
->name
);
4992 char *s
= intel_parser
.disp
;
4995 /* Add the displacement expression. */
4997 ret
= i386_displacement (s
, s
+ strlen (s
))
4998 && i386_index_check (s
);
5002 /* Constant and OFFSET expressions are handled by i386_immediate. */
5003 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5004 || intel_parser
.reg
== NULL
)
5005 ret
= i386_immediate (intel_parser
.disp
);
5009 free (intel_parser
.disp
);
5019 /* expr SHORT e05 */
5020 if (cur_token
.code
== T_SHORT
)
5022 intel_parser
.op_modifier
= SHORT
;
5023 intel_match_token (T_SHORT
);
5025 return (intel_e05 ());
5030 return intel_e05 ();
5040 return (intel_e06 () && intel_e05_1 ());
5046 /* e05' addOp e06 e05' */
5047 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5049 strcat (intel_parser
.disp
, cur_token
.str
);
5050 intel_match_token (cur_token
.code
);
5052 return (intel_e06 () && intel_e05_1 ());
5067 return (intel_e09 () && intel_e06_1 ());
5073 /* e06' mulOp e09 e06' */
5074 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5076 strcat (intel_parser
.disp
, cur_token
.str
);
5077 intel_match_token (cur_token
.code
);
5079 return (intel_e09 () && intel_e06_1 ());
5087 /* e09 OFFSET e10 e09'
5096 /* e09 OFFSET e10 e09' */
5097 if (cur_token
.code
== T_OFFSET
)
5099 intel_parser
.is_mem
= 0;
5100 intel_parser
.op_modifier
= OFFSET_FLAT
;
5101 intel_match_token (T_OFFSET
);
5103 return (intel_e10 () && intel_e09_1 ());
5108 return (intel_e10 () && intel_e09_1 ());
5114 /* e09' PTR e10 e09' */
5115 if (cur_token
.code
== T_PTR
)
5117 if (prev_token
.code
== T_BYTE
)
5118 i
.suffix
= BYTE_MNEM_SUFFIX
;
5120 else if (prev_token
.code
== T_WORD
)
5122 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5123 i
.suffix
= SHORT_MNEM_SUFFIX
;
5125 i
.suffix
= WORD_MNEM_SUFFIX
;
5128 else if (prev_token
.code
== T_DWORD
)
5130 if (intel_parser
.got_a_float
== 1) /* "f..." */
5131 i
.suffix
= SHORT_MNEM_SUFFIX
;
5133 i
.suffix
= LONG_MNEM_SUFFIX
;
5136 else if (prev_token
.code
== T_QWORD
)
5138 if (intel_parser
.got_a_float
== 1) /* "f..." */
5139 i
.suffix
= LONG_MNEM_SUFFIX
;
5141 i
.suffix
= QWORD_MNEM_SUFFIX
;
5144 else if (prev_token
.code
== T_XWORD
)
5145 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5149 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5153 intel_match_token (T_PTR
);
5155 return (intel_e10 () && intel_e09_1 ());
5158 /* e09 : e10 e09' */
5159 else if (cur_token
.code
== ':')
5161 /* Mark as a memory operand only if it's not already known to be an
5162 offset expression. */
5163 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5164 intel_parser
.is_mem
= 1;
5166 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5181 return (intel_e11 () && intel_e10_1 ());
5187 /* e10' [ expr ] e10' */
5188 if (cur_token
.code
== '[')
5190 intel_match_token ('[');
5192 /* Mark as a memory operand only if it's not already known to be an
5193 offset expression. If it's an offset expression, we need to keep
5195 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5196 intel_parser
.is_mem
= 1;
5198 strcat (intel_parser
.disp
, "[");
5200 /* Add a '+' to the displacement string if necessary. */
5201 if (*intel_parser
.disp
!= '\0'
5202 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5203 strcat (intel_parser
.disp
, "+");
5205 if (intel_expr () && intel_match_token (']'))
5207 /* Preserve brackets when the operand is an offset expression. */
5208 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5209 strcat (intel_parser
.disp
, "]");
5211 return intel_e10_1 ();
5238 if (cur_token
.code
== '(')
5240 intel_match_token ('(');
5241 strcat (intel_parser
.disp
, "(");
5243 if (intel_expr () && intel_match_token (')'))
5245 strcat (intel_parser
.disp
, ")");
5253 else if (cur_token
.code
== '[')
5255 intel_match_token ('[');
5257 /* Mark as a memory operand only if it's not already known to be an
5258 offset expression. If it's an offset expression, we need to keep
5260 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5261 intel_parser
.is_mem
= 1;
5263 strcat (intel_parser
.disp
, "[");
5265 /* Operands for jump/call inside brackets denote absolute addresses. */
5266 if (current_templates
->start
->opcode_modifier
& Jump
5267 || current_templates
->start
->opcode_modifier
& JumpDword
5268 || current_templates
->start
->opcode_modifier
& JumpByte
5269 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5270 i
.types
[this_operand
] |= JumpAbsolute
;
5272 /* Add a '+' to the displacement string if necessary. */
5273 if (*intel_parser
.disp
!= '\0'
5274 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5275 strcat (intel_parser
.disp
, "+");
5277 if (intel_expr () && intel_match_token (']'))
5279 /* Preserve brackets when the operand is an offset expression. */
5280 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5281 strcat (intel_parser
.disp
, "]");
5294 else if (cur_token
.code
== T_BYTE
5295 || cur_token
.code
== T_WORD
5296 || cur_token
.code
== T_DWORD
5297 || cur_token
.code
== T_QWORD
5298 || cur_token
.code
== T_XWORD
)
5300 intel_match_token (cur_token
.code
);
5307 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5309 strcat (intel_parser
.disp
, cur_token
.str
);
5310 intel_match_token (cur_token
.code
);
5312 /* Mark as a memory operand only if it's not already known to be an
5313 offset expression. */
5314 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5315 intel_parser
.is_mem
= 1;
5321 else if (cur_token
.code
== T_REG
)
5323 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5325 intel_match_token (T_REG
);
5327 /* Check for segment change. */
5328 if (cur_token
.code
== ':')
5330 if (reg
->reg_type
& (SReg2
| SReg3
))
5332 switch (reg
->reg_num
)
5335 i
.seg
[i
.mem_operands
] = &es
;
5338 i
.seg
[i
.mem_operands
] = &cs
;
5341 i
.seg
[i
.mem_operands
] = &ss
;
5344 i
.seg
[i
.mem_operands
] = &ds
;
5347 i
.seg
[i
.mem_operands
] = &fs
;
5350 i
.seg
[i
.mem_operands
] = &gs
;
5356 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5361 /* Not a segment register. Check for register scaling. */
5362 else if (cur_token
.code
== '*')
5364 if (!intel_parser
.is_mem
)
5366 as_bad (_("Register scaling only allowed in memory operands."));
5370 /* What follows must be a valid scale. */
5371 if (intel_match_token ('*')
5372 && strchr ("01248", *cur_token
.str
))
5375 i
.types
[this_operand
] |= BaseIndex
;
5377 /* Set the scale after setting the register (otherwise,
5378 i386_scale will complain) */
5379 i386_scale (cur_token
.str
);
5380 intel_match_token (T_CONST
);
5384 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5390 /* No scaling. If this is a memory operand, the register is either a
5391 base register (first occurrence) or an index register (second
5393 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5395 if (i
.base_reg
&& i
.index_reg
)
5397 as_bad (_("Too many register references in memory operand.\n"));
5401 if (i
.base_reg
== NULL
)
5406 i
.types
[this_operand
] |= BaseIndex
;
5409 /* Offset modifier. Add the register to the displacement string to be
5410 parsed as an immediate expression after we're done. */
5411 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5412 strcat (intel_parser
.disp
, reg
->reg_name
);
5414 /* It's neither base nor index nor offset. */
5417 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5418 i
.op
[this_operand
].regs
= reg
;
5422 /* Since registers are not part of the displacement string (except
5423 when we're parsing offset operands), we may need to remove any
5424 preceding '+' from the displacement string. */
5425 if (*intel_parser
.disp
!= '\0'
5426 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
5428 char *s
= intel_parser
.disp
;
5429 s
+= strlen (s
) - 1;
5438 else if (cur_token
.code
== T_ID
)
5440 /* Add the identifier to the displacement string. */
5441 strcat (intel_parser
.disp
, cur_token
.str
);
5442 intel_match_token (T_ID
);
5444 /* The identifier represents a memory reference only if it's not
5445 preceded by an offset modifier. */
5446 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5447 intel_parser
.is_mem
= 1;
5453 else if (cur_token
.code
== T_CONST
5454 || cur_token
.code
== '-'
5455 || cur_token
.code
== '+')
5459 /* Allow constants that start with `+' or `-'. */
5460 if (cur_token
.code
== '-' || cur_token
.code
== '+')
5462 strcat (intel_parser
.disp
, cur_token
.str
);
5463 intel_match_token (cur_token
.code
);
5464 if (cur_token
.code
!= T_CONST
)
5466 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5472 save_str
= (char *)malloc (strlen (cur_token
.str
) + 1);
5473 if (save_str
== NULL
)
5475 strcpy (save_str
, cur_token
.str
);
5477 /* Get the next token to check for register scaling. */
5478 intel_match_token (cur_token
.code
);
5480 /* Check if this constant is a scaling factor for an index register. */
5481 if (cur_token
.code
== '*')
5483 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
5485 if (!intel_parser
.is_mem
)
5487 as_bad (_("Register scaling only allowed in memory operands."));
5491 /* The constant is followed by `* reg', so it must be
5493 if (strchr ("01248", *save_str
))
5495 i
.index_reg
= cur_token
.reg
;
5496 i
.types
[this_operand
] |= BaseIndex
;
5498 /* Set the scale after setting the register (otherwise,
5499 i386_scale will complain) */
5500 i386_scale (save_str
);
5501 intel_match_token (T_REG
);
5503 /* Since registers are not part of the displacement
5504 string, we may need to remove any preceding '+' from
5505 the displacement string. */
5506 if (*intel_parser
.disp
!= '\0')
5508 char *s
= intel_parser
.disp
;
5509 s
+= strlen (s
) - 1;
5522 /* The constant was not used for register scaling. Since we have
5523 already consumed the token following `*' we now need to put it
5524 back in the stream. */
5526 intel_putback_token ();
5529 /* Add the constant to the displacement string. */
5530 strcat (intel_parser
.disp
, save_str
);
5536 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
5540 /* Match the given token against cur_token. If they match, read the next
5541 token from the operand string. */
5543 intel_match_token (code
)
5546 if (cur_token
.code
== code
)
5553 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
5558 /* Read a new token from intel_parser.op_string and store it in cur_token. */
5563 const reg_entry
*reg
;
5564 struct intel_token new_token
;
5566 new_token
.code
= T_NIL
;
5567 new_token
.reg
= NULL
;
5568 new_token
.str
= NULL
;
5570 /* Free the memory allocated to the previous token and move
5571 cur_token to prev_token. */
5573 free (prev_token
.str
);
5575 prev_token
= cur_token
;
5577 /* Skip whitespace. */
5578 while (is_space_char (*intel_parser
.op_string
))
5579 intel_parser
.op_string
++;
5581 /* Return an empty token if we find nothing else on the line. */
5582 if (*intel_parser
.op_string
== '\0')
5584 cur_token
= new_token
;
5588 /* The new token cannot be larger than the remainder of the operand
5590 new_token
.str
= (char *)malloc (strlen (intel_parser
.op_string
) + 1);
5591 if (new_token
.str
== NULL
)
5593 new_token
.str
[0] = '\0';
5595 if (strchr ("0123456789", *intel_parser
.op_string
))
5597 char *p
= new_token
.str
;
5598 char *q
= intel_parser
.op_string
;
5599 new_token
.code
= T_CONST
;
5601 /* Allow any kind of identifier char to encompass floating point and
5602 hexadecimal numbers. */
5603 while (is_identifier_char (*q
))
5607 /* Recognize special symbol names [0-9][bf]. */
5608 if (strlen (intel_parser
.op_string
) == 2
5609 && (intel_parser
.op_string
[1] == 'b'
5610 || intel_parser
.op_string
[1] == 'f'))
5611 new_token
.code
= T_ID
;
5614 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
5616 new_token
.code
= *intel_parser
.op_string
;
5617 new_token
.str
[0] = *intel_parser
.op_string
;
5618 new_token
.str
[1] = '\0';
5621 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5622 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
5624 new_token
.code
= T_REG
;
5625 new_token
.reg
= reg
;
5627 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
5629 new_token
.str
[0] = REGISTER_PREFIX
;
5630 new_token
.str
[1] = '\0';
5633 strcat (new_token
.str
, reg
->reg_name
);
5636 else if (is_identifier_char (*intel_parser
.op_string
))
5638 char *p
= new_token
.str
;
5639 char *q
= intel_parser
.op_string
;
5641 /* A '.' or '$' followed by an identifier char is an identifier.
5642 Otherwise, it's operator '.' followed by an expression. */
5643 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
5645 new_token
.code
= *q
;
5646 new_token
.str
[0] = *q
;
5647 new_token
.str
[1] = '\0';
5651 while (is_identifier_char (*q
) || *q
== '@')
5655 if (strcasecmp (new_token
.str
, "BYTE") == 0)
5656 new_token
.code
= T_BYTE
;
5658 else if (strcasecmp (new_token
.str
, "WORD") == 0)
5659 new_token
.code
= T_WORD
;
5661 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
5662 new_token
.code
= T_DWORD
;
5664 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
5665 new_token
.code
= T_QWORD
;
5667 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
5668 new_token
.code
= T_XWORD
;
5670 else if (strcasecmp (new_token
.str
, "PTR") == 0)
5671 new_token
.code
= T_PTR
;
5673 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
5674 new_token
.code
= T_SHORT
;
5676 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
5678 new_token
.code
= T_OFFSET
;
5680 /* ??? This is not mentioned in the MASM grammar but gcc
5681 makes use of it with -mintel-syntax. OFFSET may be
5682 followed by FLAT: */
5683 if (strncasecmp (q
, " FLAT:", 6) == 0)
5684 strcat (new_token
.str
, " FLAT:");
5687 /* ??? This is not mentioned in the MASM grammar. */
5688 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
5689 new_token
.code
= T_OFFSET
;
5692 new_token
.code
= T_ID
;
5697 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
5699 intel_parser
.op_string
+= strlen (new_token
.str
);
5700 cur_token
= new_token
;
5703 /* Put cur_token back into the token stream and make cur_token point to
5706 intel_putback_token ()
5708 intel_parser
.op_string
-= strlen (cur_token
.str
);
5709 free (cur_token
.str
);
5710 cur_token
= prev_token
;
5712 /* Forget prev_token. */
5713 prev_token
.code
= T_NIL
;
5714 prev_token
.reg
= NULL
;
5715 prev_token
.str
= NULL
;