1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
5 Free Software Foundation, Inc.
7 This file is part of GAS, the GNU Assembler.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
21 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 /* Intel 80386 machine specific gas.
25 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
26 x86_64 support by Jan Hubicka (jh@suse.cz)
27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
28 Bugs & suggestions are completely welcome. This is free software.
29 Please help us make it better. */
32 #include "safe-ctype.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
36 #include "elf/x86-64.h"
37 #include "opcodes/i386-init.h"
39 #ifndef REGISTER_WARNINGS
40 #define REGISTER_WARNINGS 1
43 #ifndef INFER_ADDR_PREFIX
44 #define INFER_ADDR_PREFIX 1
48 #define DEFAULT_ARCH "i386"
53 #define INLINE __inline__
59 /* Prefixes will be emitted in the order defined below.
60 WAIT_PREFIX must be the first prefix since FWAIT is really is an
61 instruction, and so must come before any prefixes.
62 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
63 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
69 #define HLE_PREFIX REP_PREFIX
71 #define REX_PREFIX 6 /* must come last. */
72 #define MAX_PREFIXES 7 /* max prefixes per opcode */
74 /* we define the syntax here (modulo base,index,scale syntax) */
75 #define REGISTER_PREFIX '%'
76 #define IMMEDIATE_PREFIX '$'
77 #define ABSOLUTE_PREFIX '*'
79 /* these are the instruction mnemonic suffixes in AT&T syntax or
80 memory operand size in Intel syntax. */
81 #define WORD_MNEM_SUFFIX 'w'
82 #define BYTE_MNEM_SUFFIX 'b'
83 #define SHORT_MNEM_SUFFIX 's'
84 #define LONG_MNEM_SUFFIX 'l'
85 #define QWORD_MNEM_SUFFIX 'q'
86 #define XMMWORD_MNEM_SUFFIX 'x'
87 #define YMMWORD_MNEM_SUFFIX 'y'
88 /* Intel Syntax. Use a non-ascii letter since since it never appears
90 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
92 #define END_OF_INSN '\0'
95 'templates' is for grouping together 'template' structures for opcodes
96 of the same name. This is only used for storing the insns in the grand
97 ole hash table of insns.
98 The templates themselves start at START and range up to (but not including)
103 const insn_template
*start
;
104 const insn_template
*end
;
108 /* 386 operand encoding bytes: see 386 book for details of this. */
111 unsigned int regmem
; /* codes register or memory operand */
112 unsigned int reg
; /* codes register operand (or extended opcode) */
113 unsigned int mode
; /* how to interpret regmem & reg */
117 /* x86-64 extension prefix. */
118 typedef int rex_byte
;
120 /* 386 opcode byte to code indirect addressing. */
129 /* x86 arch names, types and features */
132 const char *name
; /* arch name */
133 unsigned int len
; /* arch string length */
134 enum processor_type type
; /* arch type */
135 i386_cpu_flags flags
; /* cpu feature flags */
136 unsigned int skip
; /* show_arch should skip this. */
137 unsigned int negated
; /* turn off indicated flags. */
141 static void update_code_flag (int, int);
142 static void set_code_flag (int);
143 static void set_16bit_gcc_code_flag (int);
144 static void set_intel_syntax (int);
145 static void set_intel_mnemonic (int);
146 static void set_allow_index_reg (int);
147 static void set_check (int);
148 static void set_cpu_arch (int);
150 static void pe_directive_secrel (int);
152 static void signed_cons (int);
153 static char *output_invalid (int c
);
154 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
156 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
158 static int i386_att_operand (char *);
159 static int i386_intel_operand (char *, int);
160 static int i386_intel_simplify (expressionS
*);
161 static int i386_intel_parse_name (const char *, expressionS
*);
162 static const reg_entry
*parse_register (char *, char **);
163 static char *parse_insn (char *, char *);
164 static char *parse_operands (char *, const char *);
165 static void swap_operands (void);
166 static void swap_2_operands (int, int);
167 static void optimize_imm (void);
168 static void optimize_disp (void);
169 static const insn_template
*match_template (void);
170 static int check_string (void);
171 static int process_suffix (void);
172 static int check_byte_reg (void);
173 static int check_long_reg (void);
174 static int check_qword_reg (void);
175 static int check_word_reg (void);
176 static int finalize_imm (void);
177 static int process_operands (void);
178 static const seg_entry
*build_modrm_byte (void);
179 static void output_insn (void);
180 static void output_imm (fragS
*, offsetT
);
181 static void output_disp (fragS
*, offsetT
);
183 static void s_bss (int);
185 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
186 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
189 static const char *default_arch
= DEFAULT_ARCH
;
194 /* VEX prefix is either 2 byte or 3 byte. */
195 unsigned char bytes
[3];
197 /* Destination or source register specifier. */
198 const reg_entry
*register_specifier
;
201 /* 'md_assemble ()' gathers together information and puts it into a
208 const reg_entry
*regs
;
213 operand_size_mismatch
,
214 operand_type_mismatch
,
215 register_type_mismatch
,
216 number_of_operands_mismatch
,
217 invalid_instruction_suffix
,
220 unsupported_with_intel_mnemonic
,
223 invalid_vsib_address
,
224 invalid_vector_register_set
,
225 unsupported_vector_index_register
230 /* TM holds the template for the insn were currently assembling. */
233 /* SUFFIX holds the instruction size suffix for byte, word, dword
234 or qword, if given. */
237 /* OPERANDS gives the number of given operands. */
238 unsigned int operands
;
240 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
241 of given register, displacement, memory operands and immediate
243 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
245 /* TYPES [i] is the type (see above #defines) which tells us how to
246 use OP[i] for the corresponding operand. */
247 i386_operand_type types
[MAX_OPERANDS
];
249 /* Displacement expression, immediate expression, or register for each
251 union i386_op op
[MAX_OPERANDS
];
253 /* Flags for operands. */
254 unsigned int flags
[MAX_OPERANDS
];
255 #define Operand_PCrel 1
257 /* Relocation type for operand */
258 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
260 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
261 the base index byte below. */
262 const reg_entry
*base_reg
;
263 const reg_entry
*index_reg
;
264 unsigned int log2_scale_factor
;
266 /* SEG gives the seg_entries of this insn. They are zero unless
267 explicit segment overrides are given. */
268 const seg_entry
*seg
[2];
270 /* PREFIX holds all the given prefix opcodes (usually null).
271 PREFIXES is the number of prefix opcodes. */
272 unsigned int prefixes
;
273 unsigned char prefix
[MAX_PREFIXES
];
275 /* RM and SIB are the modrm byte and the sib byte where the
276 addressing modes of this insn are encoded. */
282 /* Swap operand in encoding. */
283 unsigned int swap_operand
;
285 /* Prefer 8bit or 32bit displacement in encoding. */
288 disp_encoding_default
= 0,
294 const char *rep_prefix
;
297 const char *hle_prefix
;
300 enum i386_error error
;
303 typedef struct _i386_insn i386_insn
;
305 /* List of chars besides those in app.c:symbol_chars that can start an
306 operand. Used to prevent the scrubber eating vital white-space. */
307 const char extra_symbol_chars
[] = "*%-(["
316 #if (defined (TE_I386AIX) \
317 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
318 && !defined (TE_GNU) \
319 && !defined (TE_LINUX) \
320 && !defined (TE_NACL) \
321 && !defined (TE_NETWARE) \
322 && !defined (TE_FreeBSD) \
323 && !defined (TE_DragonFly) \
324 && !defined (TE_NetBSD)))
325 /* This array holds the chars that always start a comment. If the
326 pre-processor is disabled, these aren't very useful. The option
327 --divide will remove '/' from this list. */
328 const char *i386_comment_chars
= "#/";
329 #define SVR4_COMMENT_CHARS 1
330 #define PREFIX_SEPARATOR '\\'
333 const char *i386_comment_chars
= "#";
334 #define PREFIX_SEPARATOR '/'
337 /* This array holds the chars that only start a comment at the beginning of
338 a line. If the line seems to have the form '# 123 filename'
339 .line and .file directives will appear in the pre-processed output.
340 Note that input_file.c hand checks for '#' at the beginning of the
341 first line of the input file. This is because the compiler outputs
342 #NO_APP at the beginning of its output.
343 Also note that comments started like this one will always work if
344 '/' isn't otherwise defined. */
345 const char line_comment_chars
[] = "#/";
347 const char line_separator_chars
[] = ";";
349 /* Chars that can be used to separate mant from exp in floating point
351 const char EXP_CHARS
[] = "eE";
353 /* Chars that mean this number is a floating point constant
356 const char FLT_CHARS
[] = "fFdDxX";
358 /* Tables for lexical analysis. */
359 static char mnemonic_chars
[256];
360 static char register_chars
[256];
361 static char operand_chars
[256];
362 static char identifier_chars
[256];
363 static char digit_chars
[256];
365 /* Lexical macros. */
366 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
367 #define is_operand_char(x) (operand_chars[(unsigned char) x])
368 #define is_register_char(x) (register_chars[(unsigned char) x])
369 #define is_space_char(x) ((x) == ' ')
370 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
371 #define is_digit_char(x) (digit_chars[(unsigned char) x])
373 /* All non-digit non-letter characters that may occur in an operand. */
374 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
376 /* md_assemble() always leaves the strings it's passed unaltered. To
377 effect this we maintain a stack of saved characters that we've smashed
378 with '\0's (indicating end of strings for various sub-fields of the
379 assembler instruction). */
380 static char save_stack
[32];
381 static char *save_stack_p
;
382 #define END_STRING_AND_SAVE(s) \
383 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
384 #define RESTORE_END_STRING(s) \
385 do { *(s) = *--save_stack_p; } while (0)
387 /* The instruction we're assembling. */
390 /* Possible templates for current insn. */
391 static const templates
*current_templates
;
393 /* Per instruction expressionS buffers: max displacements & immediates. */
394 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
395 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
397 /* Current operand we are working on. */
398 static int this_operand
= -1;
400 /* We support four different modes. FLAG_CODE variable is used to distinguish
408 static enum flag_code flag_code
;
409 static unsigned int object_64bit
;
410 static unsigned int disallow_64bit_reloc
;
411 static int use_rela_relocations
= 0;
413 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
414 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
415 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
417 /* The ELF ABI to use. */
425 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
428 /* 1 for intel syntax,
430 static int intel_syntax
= 0;
432 /* 1 for intel mnemonic,
433 0 if att mnemonic. */
434 static int intel_mnemonic
= !SYSV386_COMPAT
;
436 /* 1 if support old (<= 2.8.1) versions of gcc. */
437 static int old_gcc
= OLDGCC_COMPAT
;
439 /* 1 if pseudo registers are permitted. */
440 static int allow_pseudo_reg
= 0;
442 /* 1 if register prefix % not required. */
443 static int allow_naked_reg
= 0;
445 /* 1 if pseudo index register, eiz/riz, is allowed . */
446 static int allow_index_reg
= 0;
448 static enum check_kind
454 sse_check
, operand_check
= check_warning
;
456 /* Register prefix used for error message. */
457 static const char *register_prefix
= "%";
459 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
460 leave, push, and pop instructions so that gcc has the same stack
461 frame as in 32 bit mode. */
462 static char stackop_size
= '\0';
464 /* Non-zero to optimize code alignment. */
465 int optimize_align_code
= 1;
467 /* Non-zero to quieten some warnings. */
468 static int quiet_warnings
= 0;
471 static const char *cpu_arch_name
= NULL
;
472 static char *cpu_sub_arch_name
= NULL
;
474 /* CPU feature flags. */
475 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
477 /* If we have selected a cpu we are generating instructions for. */
478 static int cpu_arch_tune_set
= 0;
480 /* Cpu we are generating instructions for. */
481 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
483 /* CPU feature flags of cpu we are generating instructions for. */
484 static i386_cpu_flags cpu_arch_tune_flags
;
486 /* CPU instruction set architecture used. */
487 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
489 /* CPU feature flags of instruction set architecture used. */
490 i386_cpu_flags cpu_arch_isa_flags
;
492 /* If set, conditional jumps are not automatically promoted to handle
493 larger than a byte offset. */
494 static unsigned int no_cond_jump_promotion
= 0;
496 /* Encode SSE instructions with VEX prefix. */
497 static unsigned int sse2avx
;
499 /* Encode scalar AVX instructions with specific vector length. */
506 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
507 static symbolS
*GOT_symbol
;
509 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
510 unsigned int x86_dwarf2_return_column
;
512 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
513 int x86_cie_data_alignment
;
515 /* Interface to relax_segment.
516 There are 3 major relax states for 386 jump insns because the
517 different types of jumps add different sizes to frags when we're
518 figuring out what sort of jump to choose to reach a given label. */
521 #define UNCOND_JUMP 0
523 #define COND_JUMP86 2
528 #define SMALL16 (SMALL | CODE16)
530 #define BIG16 (BIG | CODE16)
534 #define INLINE __inline__
540 #define ENCODE_RELAX_STATE(type, size) \
541 ((relax_substateT) (((type) << 2) | (size)))
542 #define TYPE_FROM_RELAX_STATE(s) \
544 #define DISP_SIZE_FROM_RELAX_STATE(s) \
545 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
547 /* This table is used by relax_frag to promote short jumps to long
548 ones where necessary. SMALL (short) jumps may be promoted to BIG
549 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
550 don't allow a short jump in a 32 bit code segment to be promoted to
551 a 16 bit offset jump because it's slower (requires data size
552 prefix), and doesn't work, unless the destination is in the bottom
553 64k of the code segment (The top 16 bits of eip are zeroed). */
555 const relax_typeS md_relax_table
[] =
558 1) most positive reach of this state,
559 2) most negative reach of this state,
560 3) how many bytes this mode will have in the variable part of the frag
561 4) which index into the table to try if we can't fit into this one. */
563 /* UNCOND_JUMP states. */
564 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
565 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
566 /* dword jmp adds 4 bytes to frag:
567 0 extra opcode bytes, 4 displacement bytes. */
569 /* word jmp adds 2 byte2 to frag:
570 0 extra opcode bytes, 2 displacement bytes. */
573 /* COND_JUMP states. */
574 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
575 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
576 /* dword conditionals adds 5 bytes to frag:
577 1 extra opcode byte, 4 displacement bytes. */
579 /* word conditionals add 3 bytes to frag:
580 1 extra opcode byte, 2 displacement bytes. */
583 /* COND_JUMP86 states. */
584 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
585 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
586 /* dword conditionals adds 5 bytes to frag:
587 1 extra opcode byte, 4 displacement bytes. */
589 /* word conditionals add 4 bytes to frag:
590 1 displacement byte and a 3 byte long branch insn. */
594 static const arch_entry cpu_arch
[] =
596 /* Do not replace the first two entries - i386_target_format()
597 relies on them being there in this order. */
598 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
599 CPU_GENERIC32_FLAGS
, 0, 0 },
600 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
601 CPU_GENERIC64_FLAGS
, 0, 0 },
602 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
603 CPU_NONE_FLAGS
, 0, 0 },
604 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
605 CPU_I186_FLAGS
, 0, 0 },
606 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
607 CPU_I286_FLAGS
, 0, 0 },
608 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
609 CPU_I386_FLAGS
, 0, 0 },
610 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
611 CPU_I486_FLAGS
, 0, 0 },
612 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
613 CPU_I586_FLAGS
, 0, 0 },
614 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
615 CPU_I686_FLAGS
, 0, 0 },
616 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
617 CPU_I586_FLAGS
, 0, 0 },
618 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
619 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
620 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
621 CPU_P2_FLAGS
, 0, 0 },
622 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
623 CPU_P3_FLAGS
, 0, 0 },
624 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
625 CPU_P4_FLAGS
, 0, 0 },
626 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
627 CPU_CORE_FLAGS
, 0, 0 },
628 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
629 CPU_NOCONA_FLAGS
, 0, 0 },
630 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
631 CPU_CORE_FLAGS
, 1, 0 },
632 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
633 CPU_CORE_FLAGS
, 0, 0 },
634 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
635 CPU_CORE2_FLAGS
, 1, 0 },
636 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
637 CPU_CORE2_FLAGS
, 0, 0 },
638 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
639 CPU_COREI7_FLAGS
, 0, 0 },
640 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
641 CPU_L1OM_FLAGS
, 0, 0 },
642 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
643 CPU_K1OM_FLAGS
, 0, 0 },
644 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
645 CPU_K6_FLAGS
, 0, 0 },
646 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
647 CPU_K6_2_FLAGS
, 0, 0 },
648 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
649 CPU_ATHLON_FLAGS
, 0, 0 },
650 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
651 CPU_K8_FLAGS
, 1, 0 },
652 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
653 CPU_K8_FLAGS
, 0, 0 },
654 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
655 CPU_K8_FLAGS
, 0, 0 },
656 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
657 CPU_AMDFAM10_FLAGS
, 0, 0 },
658 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
659 CPU_BDVER1_FLAGS
, 0, 0 },
660 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
661 CPU_BDVER2_FLAGS
, 0, 0 },
662 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
663 CPU_BDVER3_FLAGS
, 0, 0 },
664 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
665 CPU_BTVER1_FLAGS
, 0, 0 },
666 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
667 CPU_BTVER2_FLAGS
, 0, 0 },
668 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
669 CPU_8087_FLAGS
, 0, 0 },
670 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
671 CPU_287_FLAGS
, 0, 0 },
672 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
673 CPU_387_FLAGS
, 0, 0 },
674 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
675 CPU_ANY87_FLAGS
, 0, 1 },
676 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
677 CPU_MMX_FLAGS
, 0, 0 },
678 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
679 CPU_3DNOWA_FLAGS
, 0, 1 },
680 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
681 CPU_SSE_FLAGS
, 0, 0 },
682 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
683 CPU_SSE2_FLAGS
, 0, 0 },
684 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
685 CPU_SSE3_FLAGS
, 0, 0 },
686 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
687 CPU_SSSE3_FLAGS
, 0, 0 },
688 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
689 CPU_SSE4_1_FLAGS
, 0, 0 },
690 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
691 CPU_SSE4_2_FLAGS
, 0, 0 },
692 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
693 CPU_SSE4_2_FLAGS
, 0, 0 },
694 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
695 CPU_ANY_SSE_FLAGS
, 0, 1 },
696 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
697 CPU_AVX_FLAGS
, 0, 0 },
698 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
699 CPU_AVX2_FLAGS
, 0, 0 },
700 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
701 CPU_ANY_AVX_FLAGS
, 0, 1 },
702 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
703 CPU_VMX_FLAGS
, 0, 0 },
704 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
705 CPU_VMFUNC_FLAGS
, 0, 0 },
706 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
707 CPU_SMX_FLAGS
, 0, 0 },
708 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
709 CPU_XSAVE_FLAGS
, 0, 0 },
710 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
711 CPU_XSAVEOPT_FLAGS
, 0, 0 },
712 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
713 CPU_AES_FLAGS
, 0, 0 },
714 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
715 CPU_PCLMUL_FLAGS
, 0, 0 },
716 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
717 CPU_PCLMUL_FLAGS
, 1, 0 },
718 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
719 CPU_FSGSBASE_FLAGS
, 0, 0 },
720 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
721 CPU_RDRND_FLAGS
, 0, 0 },
722 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
723 CPU_F16C_FLAGS
, 0, 0 },
724 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
725 CPU_BMI2_FLAGS
, 0, 0 },
726 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
727 CPU_FMA_FLAGS
, 0, 0 },
728 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
729 CPU_FMA4_FLAGS
, 0, 0 },
730 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
731 CPU_XOP_FLAGS
, 0, 0 },
732 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
733 CPU_LWP_FLAGS
, 0, 0 },
734 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
735 CPU_MOVBE_FLAGS
, 0, 0 },
736 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
737 CPU_CX16_FLAGS
, 0, 0 },
738 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
739 CPU_EPT_FLAGS
, 0, 0 },
740 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
741 CPU_LZCNT_FLAGS
, 0, 0 },
742 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
743 CPU_HLE_FLAGS
, 0, 0 },
744 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
745 CPU_RTM_FLAGS
, 0, 0 },
746 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
747 CPU_INVPCID_FLAGS
, 0, 0 },
748 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
749 CPU_CLFLUSH_FLAGS
, 0, 0 },
750 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
751 CPU_NOP_FLAGS
, 0, 0 },
752 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
753 CPU_SYSCALL_FLAGS
, 0, 0 },
754 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
755 CPU_RDTSCP_FLAGS
, 0, 0 },
756 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
757 CPU_3DNOW_FLAGS
, 0, 0 },
758 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
759 CPU_3DNOWA_FLAGS
, 0, 0 },
760 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
761 CPU_PADLOCK_FLAGS
, 0, 0 },
762 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
763 CPU_SVME_FLAGS
, 1, 0 },
764 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
765 CPU_SVME_FLAGS
, 0, 0 },
766 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
767 CPU_SSE4A_FLAGS
, 0, 0 },
768 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
769 CPU_ABM_FLAGS
, 0, 0 },
770 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
771 CPU_BMI_FLAGS
, 0, 0 },
772 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
773 CPU_TBM_FLAGS
, 0, 0 },
774 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
775 CPU_ADX_FLAGS
, 0, 0 },
776 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
777 CPU_RDSEED_FLAGS
, 0, 0 },
778 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
779 CPU_PRFCHW_FLAGS
, 0, 0 },
780 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
781 CPU_SMAP_FLAGS
, 0, 0 },
785 /* Like s_lcomm_internal in gas/read.c but the alignment string
786 is allowed to be optional. */
789 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
796 && *input_line_pointer
== ',')
798 align
= parse_align (needs_align
- 1);
800 if (align
== (addressT
) -1)
815 bss_alloc (symbolP
, size
, align
);
820 pe_lcomm (int needs_align
)
822 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
826 const pseudo_typeS md_pseudo_table
[] =
828 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
829 {"align", s_align_bytes
, 0},
831 {"align", s_align_ptwo
, 0},
833 {"arch", set_cpu_arch
, 0},
837 {"lcomm", pe_lcomm
, 1},
839 {"ffloat", float_cons
, 'f'},
840 {"dfloat", float_cons
, 'd'},
841 {"tfloat", float_cons
, 'x'},
843 {"slong", signed_cons
, 4},
844 {"noopt", s_ignore
, 0},
845 {"optim", s_ignore
, 0},
846 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
847 {"code16", set_code_flag
, CODE_16BIT
},
848 {"code32", set_code_flag
, CODE_32BIT
},
849 {"code64", set_code_flag
, CODE_64BIT
},
850 {"intel_syntax", set_intel_syntax
, 1},
851 {"att_syntax", set_intel_syntax
, 0},
852 {"intel_mnemonic", set_intel_mnemonic
, 1},
853 {"att_mnemonic", set_intel_mnemonic
, 0},
854 {"allow_index_reg", set_allow_index_reg
, 1},
855 {"disallow_index_reg", set_allow_index_reg
, 0},
856 {"sse_check", set_check
, 0},
857 {"operand_check", set_check
, 1},
858 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
859 {"largecomm", handle_large_common
, 0},
861 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
862 {"loc", dwarf2_directive_loc
, 0},
863 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
866 {"secrel32", pe_directive_secrel
, 0},
871 /* For interface with expression (). */
872 extern char *input_line_pointer
;
874 /* Hash table for instruction mnemonic lookup. */
875 static struct hash_control
*op_hash
;
877 /* Hash table for register lookup. */
878 static struct hash_control
*reg_hash
;
881 i386_align_code (fragS
*fragP
, int count
)
883 /* Various efficient no-op patterns for aligning code labels.
884 Note: Don't try to assemble the instructions in the comments.
885 0L and 0w are not legal. */
886 static const char f32_1
[] =
888 static const char f32_2
[] =
889 {0x66,0x90}; /* xchg %ax,%ax */
890 static const char f32_3
[] =
891 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
892 static const char f32_4
[] =
893 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
894 static const char f32_5
[] =
896 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
897 static const char f32_6
[] =
898 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
899 static const char f32_7
[] =
900 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
901 static const char f32_8
[] =
903 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
904 static const char f32_9
[] =
905 {0x89,0xf6, /* movl %esi,%esi */
906 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
907 static const char f32_10
[] =
908 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
909 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
910 static const char f32_11
[] =
911 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
912 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
913 static const char f32_12
[] =
914 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
915 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
916 static const char f32_13
[] =
917 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
918 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
919 static const char f32_14
[] =
920 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
921 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
922 static const char f16_3
[] =
923 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
924 static const char f16_4
[] =
925 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
926 static const char f16_5
[] =
928 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
929 static const char f16_6
[] =
930 {0x89,0xf6, /* mov %si,%si */
931 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
932 static const char f16_7
[] =
933 {0x8d,0x74,0x00, /* lea 0(%si),%si */
934 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
935 static const char f16_8
[] =
936 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
937 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
938 static const char jump_31
[] =
939 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
940 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
941 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
942 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
943 static const char *const f32_patt
[] = {
944 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
945 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
947 static const char *const f16_patt
[] = {
948 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
951 static const char alt_3
[] =
953 /* nopl 0(%[re]ax) */
954 static const char alt_4
[] =
955 {0x0f,0x1f,0x40,0x00};
956 /* nopl 0(%[re]ax,%[re]ax,1) */
957 static const char alt_5
[] =
958 {0x0f,0x1f,0x44,0x00,0x00};
959 /* nopw 0(%[re]ax,%[re]ax,1) */
960 static const char alt_6
[] =
961 {0x66,0x0f,0x1f,0x44,0x00,0x00};
962 /* nopl 0L(%[re]ax) */
963 static const char alt_7
[] =
964 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
965 /* nopl 0L(%[re]ax,%[re]ax,1) */
966 static const char alt_8
[] =
967 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
968 /* nopw 0L(%[re]ax,%[re]ax,1) */
969 static const char alt_9
[] =
970 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
971 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
972 static const char alt_10
[] =
973 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
975 nopw %cs:0L(%[re]ax,%[re]ax,1) */
976 static const char alt_long_11
[] =
978 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
981 nopw %cs:0L(%[re]ax,%[re]ax,1) */
982 static const char alt_long_12
[] =
985 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
989 nopw %cs:0L(%[re]ax,%[re]ax,1) */
990 static const char alt_long_13
[] =
994 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
999 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1000 static const char alt_long_14
[] =
1005 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1011 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1012 static const char alt_long_15
[] =
1018 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1019 /* nopl 0(%[re]ax,%[re]ax,1)
1020 nopw 0(%[re]ax,%[re]ax,1) */
1021 static const char alt_short_11
[] =
1022 {0x0f,0x1f,0x44,0x00,0x00,
1023 0x66,0x0f,0x1f,0x44,0x00,0x00};
1024 /* nopw 0(%[re]ax,%[re]ax,1)
1025 nopw 0(%[re]ax,%[re]ax,1) */
1026 static const char alt_short_12
[] =
1027 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1028 0x66,0x0f,0x1f,0x44,0x00,0x00};
1029 /* nopw 0(%[re]ax,%[re]ax,1)
1031 static const char alt_short_13
[] =
1032 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1033 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1036 static const char alt_short_14
[] =
1037 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1038 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1040 nopl 0L(%[re]ax,%[re]ax,1) */
1041 static const char alt_short_15
[] =
1042 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1043 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1044 static const char *const alt_short_patt
[] = {
1045 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1046 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1047 alt_short_14
, alt_short_15
1049 static const char *const alt_long_patt
[] = {
1050 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1051 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1052 alt_long_14
, alt_long_15
1055 /* Only align for at least a positive non-zero boundary. */
1056 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1059 /* We need to decide which NOP sequence to use for 32bit and
1060 64bit. When -mtune= is used:
1062 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1063 PROCESSOR_GENERIC32, f32_patt will be used.
1064 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1065 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1066 PROCESSOR_GENERIC64, alt_long_patt will be used.
1067 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1068 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1071 When -mtune= isn't used, alt_long_patt will be used if
1072 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1075 When -march= or .arch is used, we can't use anything beyond
1076 cpu_arch_isa_flags. */
1078 if (flag_code
== CODE_16BIT
)
1082 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1084 /* Adjust jump offset. */
1085 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1088 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1089 f16_patt
[count
- 1], count
);
1093 const char *const *patt
= NULL
;
1095 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1097 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1098 switch (cpu_arch_tune
)
1100 case PROCESSOR_UNKNOWN
:
1101 /* We use cpu_arch_isa_flags to check if we SHOULD
1102 optimize with nops. */
1103 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1104 patt
= alt_long_patt
;
1108 case PROCESSOR_PENTIUM4
:
1109 case PROCESSOR_NOCONA
:
1110 case PROCESSOR_CORE
:
1111 case PROCESSOR_CORE2
:
1112 case PROCESSOR_COREI7
:
1113 case PROCESSOR_L1OM
:
1114 case PROCESSOR_K1OM
:
1115 case PROCESSOR_GENERIC64
:
1116 patt
= alt_long_patt
;
1119 case PROCESSOR_ATHLON
:
1121 case PROCESSOR_AMDFAM10
:
1124 patt
= alt_short_patt
;
1126 case PROCESSOR_I386
:
1127 case PROCESSOR_I486
:
1128 case PROCESSOR_PENTIUM
:
1129 case PROCESSOR_PENTIUMPRO
:
1130 case PROCESSOR_GENERIC32
:
1137 switch (fragP
->tc_frag_data
.tune
)
1139 case PROCESSOR_UNKNOWN
:
1140 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1141 PROCESSOR_UNKNOWN. */
1145 case PROCESSOR_I386
:
1146 case PROCESSOR_I486
:
1147 case PROCESSOR_PENTIUM
:
1149 case PROCESSOR_ATHLON
:
1151 case PROCESSOR_AMDFAM10
:
1154 case PROCESSOR_GENERIC32
:
1155 /* We use cpu_arch_isa_flags to check if we CAN optimize
1157 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1158 patt
= alt_short_patt
;
1162 case PROCESSOR_PENTIUMPRO
:
1163 case PROCESSOR_PENTIUM4
:
1164 case PROCESSOR_NOCONA
:
1165 case PROCESSOR_CORE
:
1166 case PROCESSOR_CORE2
:
1167 case PROCESSOR_COREI7
:
1168 case PROCESSOR_L1OM
:
1169 case PROCESSOR_K1OM
:
1170 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1171 patt
= alt_long_patt
;
1175 case PROCESSOR_GENERIC64
:
1176 patt
= alt_long_patt
;
1181 if (patt
== f32_patt
)
1183 /* If the padding is less than 15 bytes, we use the normal
1184 ones. Otherwise, we use a jump instruction and adjust
1188 /* For 64bit, the limit is 3 bytes. */
1189 if (flag_code
== CODE_64BIT
1190 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1195 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1196 patt
[count
- 1], count
);
1199 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1201 /* Adjust jump offset. */
1202 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1207 /* Maximum length of an instruction is 15 byte. If the
1208 padding is greater than 15 bytes and we don't use jump,
1209 we have to break it into smaller pieces. */
1210 int padding
= count
;
1211 while (padding
> 15)
1214 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1219 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1220 patt
[padding
- 1], padding
);
1223 fragP
->fr_var
= count
;
1227 operand_type_all_zero (const union i386_operand_type
*x
)
1229 switch (ARRAY_SIZE(x
->array
))
1238 return !x
->array
[0];
1245 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1247 switch (ARRAY_SIZE(x
->array
))
1262 operand_type_equal (const union i386_operand_type
*x
,
1263 const union i386_operand_type
*y
)
1265 switch (ARRAY_SIZE(x
->array
))
1268 if (x
->array
[2] != y
->array
[2])
1271 if (x
->array
[1] != y
->array
[1])
1274 return x
->array
[0] == y
->array
[0];
1282 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1284 switch (ARRAY_SIZE(x
->array
))
1293 return !x
->array
[0];
1300 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1302 switch (ARRAY_SIZE(x
->array
))
1317 cpu_flags_equal (const union i386_cpu_flags
*x
,
1318 const union i386_cpu_flags
*y
)
1320 switch (ARRAY_SIZE(x
->array
))
1323 if (x
->array
[2] != y
->array
[2])
1326 if (x
->array
[1] != y
->array
[1])
1329 return x
->array
[0] == y
->array
[0];
1337 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1339 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1340 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1343 static INLINE i386_cpu_flags
1344 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1346 switch (ARRAY_SIZE (x
.array
))
1349 x
.array
[2] &= y
.array
[2];
1351 x
.array
[1] &= y
.array
[1];
1353 x
.array
[0] &= y
.array
[0];
1361 static INLINE i386_cpu_flags
1362 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1364 switch (ARRAY_SIZE (x
.array
))
1367 x
.array
[2] |= y
.array
[2];
1369 x
.array
[1] |= y
.array
[1];
1371 x
.array
[0] |= y
.array
[0];
1379 static INLINE i386_cpu_flags
1380 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1382 switch (ARRAY_SIZE (x
.array
))
1385 x
.array
[2] &= ~y
.array
[2];
1387 x
.array
[1] &= ~y
.array
[1];
1389 x
.array
[0] &= ~y
.array
[0];
1397 #define CPU_FLAGS_ARCH_MATCH 0x1
1398 #define CPU_FLAGS_64BIT_MATCH 0x2
1399 #define CPU_FLAGS_AES_MATCH 0x4
1400 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1401 #define CPU_FLAGS_AVX_MATCH 0x10
1403 #define CPU_FLAGS_32BIT_MATCH \
1404 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1405 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1406 #define CPU_FLAGS_PERFECT_MATCH \
1407 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1409 /* Return CPU flags match bits. */
1412 cpu_flags_match (const insn_template
*t
)
1414 i386_cpu_flags x
= t
->cpu_flags
;
1415 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1417 x
.bitfield
.cpu64
= 0;
1418 x
.bitfield
.cpuno64
= 0;
1420 if (cpu_flags_all_zero (&x
))
1422 /* This instruction is available on all archs. */
1423 match
|= CPU_FLAGS_32BIT_MATCH
;
1427 /* This instruction is available only on some archs. */
1428 i386_cpu_flags cpu
= cpu_arch_flags
;
1430 cpu
.bitfield
.cpu64
= 0;
1431 cpu
.bitfield
.cpuno64
= 0;
1432 cpu
= cpu_flags_and (x
, cpu
);
1433 if (!cpu_flags_all_zero (&cpu
))
1435 if (x
.bitfield
.cpuavx
)
1437 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1438 if (cpu
.bitfield
.cpuavx
)
1440 /* Check SSE2AVX. */
1441 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1443 match
|= (CPU_FLAGS_ARCH_MATCH
1444 | CPU_FLAGS_AVX_MATCH
);
1446 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1447 match
|= CPU_FLAGS_AES_MATCH
;
1449 if (!x
.bitfield
.cpupclmul
1450 || cpu
.bitfield
.cpupclmul
)
1451 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1455 match
|= CPU_FLAGS_ARCH_MATCH
;
1458 match
|= CPU_FLAGS_32BIT_MATCH
;
1464 static INLINE i386_operand_type
1465 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1467 switch (ARRAY_SIZE (x
.array
))
1470 x
.array
[2] &= y
.array
[2];
1472 x
.array
[1] &= y
.array
[1];
1474 x
.array
[0] &= y
.array
[0];
1482 static INLINE i386_operand_type
1483 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1485 switch (ARRAY_SIZE (x
.array
))
1488 x
.array
[2] |= y
.array
[2];
1490 x
.array
[1] |= y
.array
[1];
1492 x
.array
[0] |= y
.array
[0];
1500 static INLINE i386_operand_type
1501 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1503 switch (ARRAY_SIZE (x
.array
))
1506 x
.array
[2] ^= y
.array
[2];
1508 x
.array
[1] ^= y
.array
[1];
1510 x
.array
[0] ^= y
.array
[0];
1518 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1519 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1520 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1521 static const i386_operand_type inoutportreg
1522 = OPERAND_TYPE_INOUTPORTREG
;
1523 static const i386_operand_type reg16_inoutportreg
1524 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1525 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1526 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1527 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1528 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1529 static const i386_operand_type anydisp
1530 = OPERAND_TYPE_ANYDISP
;
1531 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1532 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1533 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1534 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1535 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1536 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1537 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1538 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1539 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1540 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1541 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1542 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1553 operand_type_check (i386_operand_type t
, enum operand_type c
)
1558 return (t
.bitfield
.reg8
1561 || t
.bitfield
.reg64
);
1564 return (t
.bitfield
.imm8
1568 || t
.bitfield
.imm32s
1569 || t
.bitfield
.imm64
);
1572 return (t
.bitfield
.disp8
1573 || t
.bitfield
.disp16
1574 || t
.bitfield
.disp32
1575 || t
.bitfield
.disp32s
1576 || t
.bitfield
.disp64
);
1579 return (t
.bitfield
.disp8
1580 || t
.bitfield
.disp16
1581 || t
.bitfield
.disp32
1582 || t
.bitfield
.disp32s
1583 || t
.bitfield
.disp64
1584 || t
.bitfield
.baseindex
);
1593 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1594 operand J for instruction template T. */
1597 match_reg_size (const insn_template
*t
, unsigned int j
)
1599 return !((i
.types
[j
].bitfield
.byte
1600 && !t
->operand_types
[j
].bitfield
.byte
)
1601 || (i
.types
[j
].bitfield
.word
1602 && !t
->operand_types
[j
].bitfield
.word
)
1603 || (i
.types
[j
].bitfield
.dword
1604 && !t
->operand_types
[j
].bitfield
.dword
)
1605 || (i
.types
[j
].bitfield
.qword
1606 && !t
->operand_types
[j
].bitfield
.qword
));
1609 /* Return 1 if there is no conflict in any size on operand J for
1610 instruction template T. */
1613 match_mem_size (const insn_template
*t
, unsigned int j
)
1615 return (match_reg_size (t
, j
)
1616 && !((i
.types
[j
].bitfield
.unspecified
1617 && !t
->operand_types
[j
].bitfield
.unspecified
)
1618 || (i
.types
[j
].bitfield
.fword
1619 && !t
->operand_types
[j
].bitfield
.fword
)
1620 || (i
.types
[j
].bitfield
.tbyte
1621 && !t
->operand_types
[j
].bitfield
.tbyte
)
1622 || (i
.types
[j
].bitfield
.xmmword
1623 && !t
->operand_types
[j
].bitfield
.xmmword
)
1624 || (i
.types
[j
].bitfield
.ymmword
1625 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1628 /* Return 1 if there is no size conflict on any operands for
1629 instruction template T. */
1632 operand_size_match (const insn_template
*t
)
1637 /* Don't check jump instructions. */
1638 if (t
->opcode_modifier
.jump
1639 || t
->opcode_modifier
.jumpbyte
1640 || t
->opcode_modifier
.jumpdword
1641 || t
->opcode_modifier
.jumpintersegment
)
1644 /* Check memory and accumulator operand size. */
1645 for (j
= 0; j
< i
.operands
; j
++)
1647 if (t
->operand_types
[j
].bitfield
.anysize
)
1650 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1656 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1665 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1668 i
.error
= operand_size_mismatch
;
1672 /* Check reverse. */
1673 gas_assert (i
.operands
== 2);
1676 for (j
= 0; j
< 2; j
++)
1678 if (t
->operand_types
[j
].bitfield
.acc
1679 && !match_reg_size (t
, j
? 0 : 1))
1682 if (i
.types
[j
].bitfield
.mem
1683 && !match_mem_size (t
, j
? 0 : 1))
1691 operand_type_match (i386_operand_type overlap
,
1692 i386_operand_type given
)
1694 i386_operand_type temp
= overlap
;
1696 temp
.bitfield
.jumpabsolute
= 0;
1697 temp
.bitfield
.unspecified
= 0;
1698 temp
.bitfield
.byte
= 0;
1699 temp
.bitfield
.word
= 0;
1700 temp
.bitfield
.dword
= 0;
1701 temp
.bitfield
.fword
= 0;
1702 temp
.bitfield
.qword
= 0;
1703 temp
.bitfield
.tbyte
= 0;
1704 temp
.bitfield
.xmmword
= 0;
1705 temp
.bitfield
.ymmword
= 0;
1706 if (operand_type_all_zero (&temp
))
1709 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1710 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1714 i
.error
= operand_type_mismatch
;
1718 /* If given types g0 and g1 are registers they must be of the same type
1719 unless the expected operand type register overlap is null.
1720 Note that Acc in a template matches every size of reg. */
1723 operand_type_register_match (i386_operand_type m0
,
1724 i386_operand_type g0
,
1725 i386_operand_type t0
,
1726 i386_operand_type m1
,
1727 i386_operand_type g1
,
1728 i386_operand_type t1
)
1730 if (!operand_type_check (g0
, reg
))
1733 if (!operand_type_check (g1
, reg
))
1736 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1737 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1738 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1739 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1742 if (m0
.bitfield
.acc
)
1744 t0
.bitfield
.reg8
= 1;
1745 t0
.bitfield
.reg16
= 1;
1746 t0
.bitfield
.reg32
= 1;
1747 t0
.bitfield
.reg64
= 1;
1750 if (m1
.bitfield
.acc
)
1752 t1
.bitfield
.reg8
= 1;
1753 t1
.bitfield
.reg16
= 1;
1754 t1
.bitfield
.reg32
= 1;
1755 t1
.bitfield
.reg64
= 1;
1758 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1759 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1760 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1761 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1764 i
.error
= register_type_mismatch
;
1769 static INLINE
unsigned int
1770 register_number (const reg_entry
*r
)
1772 unsigned int nr
= r
->reg_num
;
1774 if (r
->reg_flags
& RegRex
)
1780 static INLINE
unsigned int
1781 mode_from_disp_size (i386_operand_type t
)
1783 if (t
.bitfield
.disp8
)
1785 else if (t
.bitfield
.disp16
1786 || t
.bitfield
.disp32
1787 || t
.bitfield
.disp32s
)
1794 fits_in_signed_byte (offsetT num
)
1796 return (num
>= -128) && (num
<= 127);
1800 fits_in_unsigned_byte (offsetT num
)
1802 return (num
& 0xff) == num
;
1806 fits_in_unsigned_word (offsetT num
)
1808 return (num
& 0xffff) == num
;
1812 fits_in_signed_word (offsetT num
)
1814 return (-32768 <= num
) && (num
<= 32767);
1818 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1823 return (!(((offsetT
) -1 << 31) & num
)
1824 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1826 } /* fits_in_signed_long() */
1829 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1834 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1836 } /* fits_in_unsigned_long() */
1839 fits_in_imm4 (offsetT num
)
1841 return (num
& 0xf) == num
;
1844 static i386_operand_type
1845 smallest_imm_type (offsetT num
)
1847 i386_operand_type t
;
1849 operand_type_set (&t
, 0);
1850 t
.bitfield
.imm64
= 1;
1852 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1854 /* This code is disabled on the 486 because all the Imm1 forms
1855 in the opcode table are slower on the i486. They're the
1856 versions with the implicitly specified single-position
1857 displacement, which has another syntax if you really want to
1859 t
.bitfield
.imm1
= 1;
1860 t
.bitfield
.imm8
= 1;
1861 t
.bitfield
.imm8s
= 1;
1862 t
.bitfield
.imm16
= 1;
1863 t
.bitfield
.imm32
= 1;
1864 t
.bitfield
.imm32s
= 1;
1866 else if (fits_in_signed_byte (num
))
1868 t
.bitfield
.imm8
= 1;
1869 t
.bitfield
.imm8s
= 1;
1870 t
.bitfield
.imm16
= 1;
1871 t
.bitfield
.imm32
= 1;
1872 t
.bitfield
.imm32s
= 1;
1874 else if (fits_in_unsigned_byte (num
))
1876 t
.bitfield
.imm8
= 1;
1877 t
.bitfield
.imm16
= 1;
1878 t
.bitfield
.imm32
= 1;
1879 t
.bitfield
.imm32s
= 1;
1881 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1883 t
.bitfield
.imm16
= 1;
1884 t
.bitfield
.imm32
= 1;
1885 t
.bitfield
.imm32s
= 1;
1887 else if (fits_in_signed_long (num
))
1889 t
.bitfield
.imm32
= 1;
1890 t
.bitfield
.imm32s
= 1;
1892 else if (fits_in_unsigned_long (num
))
1893 t
.bitfield
.imm32
= 1;
1899 offset_in_range (offsetT val
, int size
)
1905 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1906 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1907 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1909 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1915 /* If BFD64, sign extend val for 32bit address mode. */
1916 if (flag_code
!= CODE_64BIT
1917 || i
.prefix
[ADDR_PREFIX
])
1918 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1919 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1922 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1924 char buf1
[40], buf2
[40];
1926 sprint_value (buf1
, val
);
1927 sprint_value (buf2
, val
& mask
);
1928 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1942 a. PREFIX_EXIST if attempting to add a prefix where one from the
1943 same class already exists.
1944 b. PREFIX_LOCK if lock prefix is added.
1945 c. PREFIX_REP if rep/repne prefix is added.
1946 d. PREFIX_OTHER if other prefix is added.
1949 static enum PREFIX_GROUP
1950 add_prefix (unsigned int prefix
)
1952 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
1955 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1956 && flag_code
== CODE_64BIT
)
1958 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1959 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1960 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1971 case CS_PREFIX_OPCODE
:
1972 case DS_PREFIX_OPCODE
:
1973 case ES_PREFIX_OPCODE
:
1974 case FS_PREFIX_OPCODE
:
1975 case GS_PREFIX_OPCODE
:
1976 case SS_PREFIX_OPCODE
:
1980 case REPNE_PREFIX_OPCODE
:
1981 case REPE_PREFIX_OPCODE
:
1986 case LOCK_PREFIX_OPCODE
:
1995 case ADDR_PREFIX_OPCODE
:
1999 case DATA_PREFIX_OPCODE
:
2003 if (i
.prefix
[q
] != 0)
2011 i
.prefix
[q
] |= prefix
;
2014 as_bad (_("same type of prefix used twice"));
2020 update_code_flag (int value
, int check
)
2022 PRINTF_LIKE ((*as_error
));
2024 flag_code
= (enum flag_code
) value
;
2025 if (flag_code
== CODE_64BIT
)
2027 cpu_arch_flags
.bitfield
.cpu64
= 1;
2028 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2032 cpu_arch_flags
.bitfield
.cpu64
= 0;
2033 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2035 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2038 as_error
= as_fatal
;
2041 (*as_error
) (_("64bit mode not supported on `%s'."),
2042 cpu_arch_name
? cpu_arch_name
: default_arch
);
2044 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2047 as_error
= as_fatal
;
2050 (*as_error
) (_("32bit mode not supported on `%s'."),
2051 cpu_arch_name
? cpu_arch_name
: default_arch
);
2053 stackop_size
= '\0';
2057 set_code_flag (int value
)
2059 update_code_flag (value
, 0);
2063 set_16bit_gcc_code_flag (int new_code_flag
)
2065 flag_code
= (enum flag_code
) new_code_flag
;
2066 if (flag_code
!= CODE_16BIT
)
2068 cpu_arch_flags
.bitfield
.cpu64
= 0;
2069 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2070 stackop_size
= LONG_MNEM_SUFFIX
;
2074 set_intel_syntax (int syntax_flag
)
2076 /* Find out if register prefixing is specified. */
2077 int ask_naked_reg
= 0;
2080 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2082 char *string
= input_line_pointer
;
2083 int e
= get_symbol_end ();
2085 if (strcmp (string
, "prefix") == 0)
2087 else if (strcmp (string
, "noprefix") == 0)
2090 as_bad (_("bad argument to syntax directive."));
2091 *input_line_pointer
= e
;
2093 demand_empty_rest_of_line ();
2095 intel_syntax
= syntax_flag
;
2097 if (ask_naked_reg
== 0)
2098 allow_naked_reg
= (intel_syntax
2099 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2101 allow_naked_reg
= (ask_naked_reg
< 0);
2103 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2105 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2106 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2107 register_prefix
= allow_naked_reg
? "" : "%";
2111 set_intel_mnemonic (int mnemonic_flag
)
2113 intel_mnemonic
= mnemonic_flag
;
2117 set_allow_index_reg (int flag
)
2119 allow_index_reg
= flag
;
2123 set_check (int what
)
2125 enum check_kind
*kind
;
2130 kind
= &operand_check
;
2141 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2143 char *string
= input_line_pointer
;
2144 int e
= get_symbol_end ();
2146 if (strcmp (string
, "none") == 0)
2148 else if (strcmp (string
, "warning") == 0)
2149 *kind
= check_warning
;
2150 else if (strcmp (string
, "error") == 0)
2151 *kind
= check_error
;
2153 as_bad (_("bad argument to %s_check directive."), str
);
2154 *input_line_pointer
= e
;
2157 as_bad (_("missing argument for %s_check directive"), str
);
2159 demand_empty_rest_of_line ();
2163 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2164 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2166 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2167 static const char *arch
;
2169 /* Intel LIOM is only supported on ELF. */
2175 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2176 use default_arch. */
2177 arch
= cpu_arch_name
;
2179 arch
= default_arch
;
2182 /* If we are targeting Intel L1OM, we must enable it. */
2183 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2184 || new_flag
.bitfield
.cpul1om
)
2187 /* If we are targeting Intel K1OM, we must enable it. */
2188 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2189 || new_flag
.bitfield
.cpuk1om
)
2192 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2197 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2201 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2203 char *string
= input_line_pointer
;
2204 int e
= get_symbol_end ();
2206 i386_cpu_flags flags
;
2208 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2210 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2212 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2216 cpu_arch_name
= cpu_arch
[j
].name
;
2217 cpu_sub_arch_name
= NULL
;
2218 cpu_arch_flags
= cpu_arch
[j
].flags
;
2219 if (flag_code
== CODE_64BIT
)
2221 cpu_arch_flags
.bitfield
.cpu64
= 1;
2222 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2226 cpu_arch_flags
.bitfield
.cpu64
= 0;
2227 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2229 cpu_arch_isa
= cpu_arch
[j
].type
;
2230 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2231 if (!cpu_arch_tune_set
)
2233 cpu_arch_tune
= cpu_arch_isa
;
2234 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2239 if (!cpu_arch
[j
].negated
)
2240 flags
= cpu_flags_or (cpu_arch_flags
,
2243 flags
= cpu_flags_and_not (cpu_arch_flags
,
2245 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2247 if (cpu_sub_arch_name
)
2249 char *name
= cpu_sub_arch_name
;
2250 cpu_sub_arch_name
= concat (name
,
2252 (const char *) NULL
);
2256 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2257 cpu_arch_flags
= flags
;
2258 cpu_arch_isa_flags
= flags
;
2260 *input_line_pointer
= e
;
2261 demand_empty_rest_of_line ();
2265 if (j
>= ARRAY_SIZE (cpu_arch
))
2266 as_bad (_("no such architecture: `%s'"), string
);
2268 *input_line_pointer
= e
;
2271 as_bad (_("missing cpu architecture"));
2273 no_cond_jump_promotion
= 0;
2274 if (*input_line_pointer
== ','
2275 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2277 char *string
= ++input_line_pointer
;
2278 int e
= get_symbol_end ();
2280 if (strcmp (string
, "nojumps") == 0)
2281 no_cond_jump_promotion
= 1;
2282 else if (strcmp (string
, "jumps") == 0)
2285 as_bad (_("no such architecture modifier: `%s'"), string
);
2287 *input_line_pointer
= e
;
2290 demand_empty_rest_of_line ();
2293 enum bfd_architecture
2296 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2298 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2299 || flag_code
!= CODE_64BIT
)
2300 as_fatal (_("Intel L1OM is 64bit ELF only"));
2301 return bfd_arch_l1om
;
2303 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2305 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2306 || flag_code
!= CODE_64BIT
)
2307 as_fatal (_("Intel K1OM is 64bit ELF only"));
2308 return bfd_arch_k1om
;
2311 return bfd_arch_i386
;
2317 if (!strncmp (default_arch
, "x86_64", 6))
2319 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2321 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2322 || default_arch
[6] != '\0')
2323 as_fatal (_("Intel L1OM is 64bit ELF only"));
2324 return bfd_mach_l1om
;
2326 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2328 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2329 || default_arch
[6] != '\0')
2330 as_fatal (_("Intel K1OM is 64bit ELF only"));
2331 return bfd_mach_k1om
;
2333 else if (default_arch
[6] == '\0')
2334 return bfd_mach_x86_64
;
2336 return bfd_mach_x64_32
;
2338 else if (!strcmp (default_arch
, "i386"))
2339 return bfd_mach_i386_i386
;
2341 as_fatal (_("unknown architecture"));
2347 const char *hash_err
;
2349 /* Initialize op_hash hash table. */
2350 op_hash
= hash_new ();
2353 const insn_template
*optab
;
2354 templates
*core_optab
;
2356 /* Setup for loop. */
2358 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2359 core_optab
->start
= optab
;
2364 if (optab
->name
== NULL
2365 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2367 /* different name --> ship out current template list;
2368 add to hash table; & begin anew. */
2369 core_optab
->end
= optab
;
2370 hash_err
= hash_insert (op_hash
,
2372 (void *) core_optab
);
2375 as_fatal (_("can't hash %s: %s"),
2379 if (optab
->name
== NULL
)
2381 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2382 core_optab
->start
= optab
;
2387 /* Initialize reg_hash hash table. */
2388 reg_hash
= hash_new ();
2390 const reg_entry
*regtab
;
2391 unsigned int regtab_size
= i386_regtab_size
;
2393 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2395 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2397 as_fatal (_("can't hash %s: %s"),
2403 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2408 for (c
= 0; c
< 256; c
++)
2413 mnemonic_chars
[c
] = c
;
2414 register_chars
[c
] = c
;
2415 operand_chars
[c
] = c
;
2417 else if (ISLOWER (c
))
2419 mnemonic_chars
[c
] = c
;
2420 register_chars
[c
] = c
;
2421 operand_chars
[c
] = c
;
2423 else if (ISUPPER (c
))
2425 mnemonic_chars
[c
] = TOLOWER (c
);
2426 register_chars
[c
] = mnemonic_chars
[c
];
2427 operand_chars
[c
] = c
;
2430 if (ISALPHA (c
) || ISDIGIT (c
))
2431 identifier_chars
[c
] = c
;
2434 identifier_chars
[c
] = c
;
2435 operand_chars
[c
] = c
;
2440 identifier_chars
['@'] = '@';
2443 identifier_chars
['?'] = '?';
2444 operand_chars
['?'] = '?';
2446 digit_chars
['-'] = '-';
2447 mnemonic_chars
['_'] = '_';
2448 mnemonic_chars
['-'] = '-';
2449 mnemonic_chars
['.'] = '.';
2450 identifier_chars
['_'] = '_';
2451 identifier_chars
['.'] = '.';
2453 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2454 operand_chars
[(unsigned char) *p
] = *p
;
2457 if (flag_code
== CODE_64BIT
)
2459 #if defined (OBJ_COFF) && defined (TE_PE)
2460 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2463 x86_dwarf2_return_column
= 16;
2465 x86_cie_data_alignment
= -8;
2469 x86_dwarf2_return_column
= 8;
2470 x86_cie_data_alignment
= -4;
2475 i386_print_statistics (FILE *file
)
2477 hash_print_statistics (file
, "i386 opcode", op_hash
);
2478 hash_print_statistics (file
, "i386 register", reg_hash
);
2483 /* Debugging routines for md_assemble. */
2484 static void pte (insn_template
*);
2485 static void pt (i386_operand_type
);
2486 static void pe (expressionS
*);
2487 static void ps (symbolS
*);
2490 pi (char *line
, i386_insn
*x
)
2494 fprintf (stdout
, "%s: template ", line
);
2496 fprintf (stdout
, " address: base %s index %s scale %x\n",
2497 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2498 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2499 x
->log2_scale_factor
);
2500 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2501 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2502 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2503 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2504 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2505 (x
->rex
& REX_W
) != 0,
2506 (x
->rex
& REX_R
) != 0,
2507 (x
->rex
& REX_X
) != 0,
2508 (x
->rex
& REX_B
) != 0);
2509 for (j
= 0; j
< x
->operands
; j
++)
2511 fprintf (stdout
, " #%d: ", j
+ 1);
2513 fprintf (stdout
, "\n");
2514 if (x
->types
[j
].bitfield
.reg8
2515 || x
->types
[j
].bitfield
.reg16
2516 || x
->types
[j
].bitfield
.reg32
2517 || x
->types
[j
].bitfield
.reg64
2518 || x
->types
[j
].bitfield
.regmmx
2519 || x
->types
[j
].bitfield
.regxmm
2520 || x
->types
[j
].bitfield
.regymm
2521 || x
->types
[j
].bitfield
.sreg2
2522 || x
->types
[j
].bitfield
.sreg3
2523 || x
->types
[j
].bitfield
.control
2524 || x
->types
[j
].bitfield
.debug
2525 || x
->types
[j
].bitfield
.test
)
2526 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2527 if (operand_type_check (x
->types
[j
], imm
))
2529 if (operand_type_check (x
->types
[j
], disp
))
2530 pe (x
->op
[j
].disps
);
2535 pte (insn_template
*t
)
2538 fprintf (stdout
, " %d operands ", t
->operands
);
2539 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2540 if (t
->extension_opcode
!= None
)
2541 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2542 if (t
->opcode_modifier
.d
)
2543 fprintf (stdout
, "D");
2544 if (t
->opcode_modifier
.w
)
2545 fprintf (stdout
, "W");
2546 fprintf (stdout
, "\n");
2547 for (j
= 0; j
< t
->operands
; j
++)
2549 fprintf (stdout
, " #%d type ", j
+ 1);
2550 pt (t
->operand_types
[j
]);
2551 fprintf (stdout
, "\n");
2558 fprintf (stdout
, " operation %d\n", e
->X_op
);
2559 fprintf (stdout
, " add_number %ld (%lx)\n",
2560 (long) e
->X_add_number
, (long) e
->X_add_number
);
2561 if (e
->X_add_symbol
)
2563 fprintf (stdout
, " add_symbol ");
2564 ps (e
->X_add_symbol
);
2565 fprintf (stdout
, "\n");
2569 fprintf (stdout
, " op_symbol ");
2570 ps (e
->X_op_symbol
);
2571 fprintf (stdout
, "\n");
2578 fprintf (stdout
, "%s type %s%s",
2580 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2581 segment_name (S_GET_SEGMENT (s
)));
2584 static struct type_name
2586 i386_operand_type mask
;
2589 const type_names
[] =
2591 { OPERAND_TYPE_REG8
, "r8" },
2592 { OPERAND_TYPE_REG16
, "r16" },
2593 { OPERAND_TYPE_REG32
, "r32" },
2594 { OPERAND_TYPE_REG64
, "r64" },
2595 { OPERAND_TYPE_IMM8
, "i8" },
2596 { OPERAND_TYPE_IMM8
, "i8s" },
2597 { OPERAND_TYPE_IMM16
, "i16" },
2598 { OPERAND_TYPE_IMM32
, "i32" },
2599 { OPERAND_TYPE_IMM32S
, "i32s" },
2600 { OPERAND_TYPE_IMM64
, "i64" },
2601 { OPERAND_TYPE_IMM1
, "i1" },
2602 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2603 { OPERAND_TYPE_DISP8
, "d8" },
2604 { OPERAND_TYPE_DISP16
, "d16" },
2605 { OPERAND_TYPE_DISP32
, "d32" },
2606 { OPERAND_TYPE_DISP32S
, "d32s" },
2607 { OPERAND_TYPE_DISP64
, "d64" },
2608 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2609 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2610 { OPERAND_TYPE_CONTROL
, "control reg" },
2611 { OPERAND_TYPE_TEST
, "test reg" },
2612 { OPERAND_TYPE_DEBUG
, "debug reg" },
2613 { OPERAND_TYPE_FLOATREG
, "FReg" },
2614 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2615 { OPERAND_TYPE_SREG2
, "SReg2" },
2616 { OPERAND_TYPE_SREG3
, "SReg3" },
2617 { OPERAND_TYPE_ACC
, "Acc" },
2618 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2619 { OPERAND_TYPE_REGMMX
, "rMMX" },
2620 { OPERAND_TYPE_REGXMM
, "rXMM" },
2621 { OPERAND_TYPE_REGYMM
, "rYMM" },
2622 { OPERAND_TYPE_ESSEG
, "es" },
2626 pt (i386_operand_type t
)
2629 i386_operand_type a
;
2631 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2633 a
= operand_type_and (t
, type_names
[j
].mask
);
2634 if (!operand_type_all_zero (&a
))
2635 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2640 #endif /* DEBUG386 */
2642 static bfd_reloc_code_real_type
2643 reloc (unsigned int size
,
2646 bfd_reloc_code_real_type other
)
2648 if (other
!= NO_RELOC
)
2650 reloc_howto_type
*rel
;
2655 case BFD_RELOC_X86_64_GOT32
:
2656 return BFD_RELOC_X86_64_GOT64
;
2658 case BFD_RELOC_X86_64_PLTOFF64
:
2659 return BFD_RELOC_X86_64_PLTOFF64
;
2661 case BFD_RELOC_X86_64_GOTPC32
:
2662 other
= BFD_RELOC_X86_64_GOTPC64
;
2664 case BFD_RELOC_X86_64_GOTPCREL
:
2665 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2667 case BFD_RELOC_X86_64_TPOFF32
:
2668 other
= BFD_RELOC_X86_64_TPOFF64
;
2670 case BFD_RELOC_X86_64_DTPOFF32
:
2671 other
= BFD_RELOC_X86_64_DTPOFF64
;
2677 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2678 if (other
== BFD_RELOC_SIZE32
)
2681 return BFD_RELOC_SIZE64
;
2683 as_bad (_("there are no pc-relative size relocations"));
2687 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2688 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2691 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2693 as_bad (_("unknown relocation (%u)"), other
);
2694 else if (size
!= bfd_get_reloc_size (rel
))
2695 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2696 bfd_get_reloc_size (rel
),
2698 else if (pcrel
&& !rel
->pc_relative
)
2699 as_bad (_("non-pc-relative relocation for pc-relative field"));
2700 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2702 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2704 as_bad (_("relocated field and relocation type differ in signedness"));
2713 as_bad (_("there are no unsigned pc-relative relocations"));
2716 case 1: return BFD_RELOC_8_PCREL
;
2717 case 2: return BFD_RELOC_16_PCREL
;
2718 case 4: return BFD_RELOC_32_PCREL
;
2719 case 8: return BFD_RELOC_64_PCREL
;
2721 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2728 case 4: return BFD_RELOC_X86_64_32S
;
2733 case 1: return BFD_RELOC_8
;
2734 case 2: return BFD_RELOC_16
;
2735 case 4: return BFD_RELOC_32
;
2736 case 8: return BFD_RELOC_64
;
2738 as_bad (_("cannot do %s %u byte relocation"),
2739 sign
> 0 ? "signed" : "unsigned", size
);
2745 /* Here we decide which fixups can be adjusted to make them relative to
2746 the beginning of the section instead of the symbol. Basically we need
2747 to make sure that the dynamic relocations are done correctly, so in
2748 some cases we force the original symbol to be used. */
2751 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2753 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2757 /* Don't adjust pc-relative references to merge sections in 64-bit
2759 if (use_rela_relocations
2760 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2764 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2765 and changed later by validate_fix. */
2766 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2767 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2770 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2771 for size relocations. */
2772 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2773 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2774 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2775 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2776 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2777 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2778 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2779 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2780 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2781 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2782 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2783 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2784 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2785 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2786 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2787 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2788 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2789 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2790 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2791 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2792 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2793 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2794 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2795 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2796 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2797 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2798 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2799 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2800 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2801 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2808 intel_float_operand (const char *mnemonic
)
2810 /* Note that the value returned is meaningful only for opcodes with (memory)
2811 operands, hence the code here is free to improperly handle opcodes that
2812 have no operands (for better performance and smaller code). */
2814 if (mnemonic
[0] != 'f')
2815 return 0; /* non-math */
2817 switch (mnemonic
[1])
2819 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2820 the fs segment override prefix not currently handled because no
2821 call path can make opcodes without operands get here */
2823 return 2 /* integer op */;
2825 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2826 return 3; /* fldcw/fldenv */
2829 if (mnemonic
[2] != 'o' /* fnop */)
2830 return 3; /* non-waiting control op */
2833 if (mnemonic
[2] == 's')
2834 return 3; /* frstor/frstpm */
2837 if (mnemonic
[2] == 'a')
2838 return 3; /* fsave */
2839 if (mnemonic
[2] == 't')
2841 switch (mnemonic
[3])
2843 case 'c': /* fstcw */
2844 case 'd': /* fstdw */
2845 case 'e': /* fstenv */
2846 case 's': /* fsts[gw] */
2852 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2853 return 0; /* fxsave/fxrstor are not really math ops */
2860 /* Build the VEX prefix. */
2863 build_vex_prefix (const insn_template
*t
)
2865 unsigned int register_specifier
;
2866 unsigned int implied_prefix
;
2867 unsigned int vector_length
;
2869 /* Check register specifier. */
2870 if (i
.vex
.register_specifier
)
2871 register_specifier
= ~register_number (i
.vex
.register_specifier
) & 0xf;
2873 register_specifier
= 0xf;
2875 /* Use 2-byte VEX prefix by swappping destination and source
2878 && i
.operands
== i
.reg_operands
2879 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2880 && i
.tm
.opcode_modifier
.s
2883 unsigned int xchg
= i
.operands
- 1;
2884 union i386_op temp_op
;
2885 i386_operand_type temp_type
;
2887 temp_type
= i
.types
[xchg
];
2888 i
.types
[xchg
] = i
.types
[0];
2889 i
.types
[0] = temp_type
;
2890 temp_op
= i
.op
[xchg
];
2891 i
.op
[xchg
] = i
.op
[0];
2894 gas_assert (i
.rm
.mode
== 3);
2898 i
.rm
.regmem
= i
.rm
.reg
;
2901 /* Use the next insn. */
2905 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
2906 vector_length
= avxscalar
;
2908 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
2910 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2915 case DATA_PREFIX_OPCODE
:
2918 case REPE_PREFIX_OPCODE
:
2921 case REPNE_PREFIX_OPCODE
:
2928 /* Use 2-byte VEX prefix if possible. */
2929 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2930 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
2931 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2933 /* 2-byte VEX prefix. */
2937 i
.vex
.bytes
[0] = 0xc5;
2939 /* Check the REX.R bit. */
2940 r
= (i
.rex
& REX_R
) ? 0 : 1;
2941 i
.vex
.bytes
[1] = (r
<< 7
2942 | register_specifier
<< 3
2943 | vector_length
<< 2
2948 /* 3-byte VEX prefix. */
2953 switch (i
.tm
.opcode_modifier
.vexopcode
)
2957 i
.vex
.bytes
[0] = 0xc4;
2961 i
.vex
.bytes
[0] = 0xc4;
2965 i
.vex
.bytes
[0] = 0xc4;
2969 i
.vex
.bytes
[0] = 0x8f;
2973 i
.vex
.bytes
[0] = 0x8f;
2977 i
.vex
.bytes
[0] = 0x8f;
2983 /* The high 3 bits of the second VEX byte are 1's compliment
2984 of RXB bits from REX. */
2985 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2987 /* Check the REX.W bit. */
2988 w
= (i
.rex
& REX_W
) ? 1 : 0;
2989 if (i
.tm
.opcode_modifier
.vexw
)
2994 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
2998 i
.vex
.bytes
[2] = (w
<< 7
2999 | register_specifier
<< 3
3000 | vector_length
<< 2
3006 process_immext (void)
3010 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3013 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3014 with an opcode suffix which is coded in the same place as an
3015 8-bit immediate field would be.
3016 Here we check those operands and remove them afterwards. */
3019 for (x
= 0; x
< i
.operands
; x
++)
3020 if (register_number (i
.op
[x
].regs
) != x
)
3021 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3022 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3028 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3029 which is coded in the same place as an 8-bit immediate field
3030 would be. Here we fake an 8-bit immediate operand from the
3031 opcode suffix stored in tm.extension_opcode.
3033 AVX instructions also use this encoding, for some of
3034 3 argument instructions. */
3036 gas_assert (i
.imm_operands
== 0
3038 || (i
.tm
.opcode_modifier
.vex
3039 && i
.operands
<= 4)));
3041 exp
= &im_expressions
[i
.imm_operands
++];
3042 i
.op
[i
.operands
].imms
= exp
;
3043 i
.types
[i
.operands
] = imm8
;
3045 exp
->X_op
= O_constant
;
3046 exp
->X_add_number
= i
.tm
.extension_opcode
;
3047 i
.tm
.extension_opcode
= None
;
3054 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3059 as_bad (_("invalid instruction `%s' after `%s'"),
3060 i
.tm
.name
, i
.hle_prefix
);
3063 if (i
.prefix
[LOCK_PREFIX
])
3065 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3069 case HLEPrefixRelease
:
3070 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3072 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3076 if (i
.mem_operands
== 0
3077 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3079 as_bad (_("memory destination needed for instruction `%s'"
3080 " after `xrelease'"), i
.tm
.name
);
3087 /* This is the guts of the machine-dependent assembler. LINE points to a
3088 machine dependent instruction. This function is supposed to emit
3089 the frags/bytes it assembles to. */
3092 md_assemble (char *line
)
3095 char mnemonic
[MAX_MNEM_SIZE
];
3096 const insn_template
*t
;
3098 /* Initialize globals. */
3099 memset (&i
, '\0', sizeof (i
));
3100 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3101 i
.reloc
[j
] = NO_RELOC
;
3102 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3103 memset (im_expressions
, '\0', sizeof (im_expressions
));
3104 save_stack_p
= save_stack
;
3106 /* First parse an instruction mnemonic & call i386_operand for the operands.
3107 We assume that the scrubber has arranged it so that line[0] is the valid
3108 start of a (possibly prefixed) mnemonic. */
3110 line
= parse_insn (line
, mnemonic
);
3114 line
= parse_operands (line
, mnemonic
);
3119 /* Now we've parsed the mnemonic into a set of templates, and have the
3120 operands at hand. */
3122 /* All intel opcodes have reversed operands except for "bound" and
3123 "enter". We also don't reverse intersegment "jmp" and "call"
3124 instructions with 2 immediate operands so that the immediate segment
3125 precedes the offset, as it does when in AT&T mode. */
3128 && (strcmp (mnemonic
, "bound") != 0)
3129 && (strcmp (mnemonic
, "invlpga") != 0)
3130 && !(operand_type_check (i
.types
[0], imm
)
3131 && operand_type_check (i
.types
[1], imm
)))
3134 /* The order of the immediates should be reversed
3135 for 2 immediates extrq and insertq instructions */
3136 if (i
.imm_operands
== 2
3137 && (strcmp (mnemonic
, "extrq") == 0
3138 || strcmp (mnemonic
, "insertq") == 0))
3139 swap_2_operands (0, 1);
3144 /* Don't optimize displacement for movabs since it only takes 64bit
3147 && i
.disp_encoding
!= disp_encoding_32bit
3148 && (flag_code
!= CODE_64BIT
3149 || strcmp (mnemonic
, "movabs") != 0))
3152 /* Next, we find a template that matches the given insn,
3153 making sure the overlap of the given operands types is consistent
3154 with the template operand types. */
3156 if (!(t
= match_template ()))
3159 if (sse_check
!= check_none
3160 && !i
.tm
.opcode_modifier
.noavx
3161 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3162 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3163 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3164 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3165 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3166 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3168 (sse_check
== check_warning
3170 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3173 /* Zap movzx and movsx suffix. The suffix has been set from
3174 "word ptr" or "byte ptr" on the source operand in Intel syntax
3175 or extracted from mnemonic in AT&T syntax. But we'll use
3176 the destination register to choose the suffix for encoding. */
3177 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3179 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3180 there is no suffix, the default will be byte extension. */
3181 if (i
.reg_operands
!= 2
3184 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3189 if (i
.tm
.opcode_modifier
.fwait
)
3190 if (!add_prefix (FWAIT_OPCODE
))
3193 /* Check if REP prefix is OK. */
3194 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3196 as_bad (_("invalid instruction `%s' after `%s'"),
3197 i
.tm
.name
, i
.rep_prefix
);
3201 /* Check for lock without a lockable instruction. Destination operand
3202 must be memory unless it is xchg (0x86). */
3203 if (i
.prefix
[LOCK_PREFIX
]
3204 && (!i
.tm
.opcode_modifier
.islockable
3205 || i
.mem_operands
== 0
3206 || (i
.tm
.base_opcode
!= 0x86
3207 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3209 as_bad (_("expecting lockable instruction after `lock'"));
3213 /* Check if HLE prefix is OK. */
3214 if (i
.hle_prefix
&& !check_hle ())
3217 /* Check string instruction segment overrides. */
3218 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3220 if (!check_string ())
3222 i
.disp_operands
= 0;
3225 if (!process_suffix ())
3228 /* Update operand types. */
3229 for (j
= 0; j
< i
.operands
; j
++)
3230 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3232 /* Make still unresolved immediate matches conform to size of immediate
3233 given in i.suffix. */
3234 if (!finalize_imm ())
3237 if (i
.types
[0].bitfield
.imm1
)
3238 i
.imm_operands
= 0; /* kludge for shift insns. */
3240 /* We only need to check those implicit registers for instructions
3241 with 3 operands or less. */
3242 if (i
.operands
<= 3)
3243 for (j
= 0; j
< i
.operands
; j
++)
3244 if (i
.types
[j
].bitfield
.inoutportreg
3245 || i
.types
[j
].bitfield
.shiftcount
3246 || i
.types
[j
].bitfield
.acc
3247 || i
.types
[j
].bitfield
.floatacc
)
3250 /* ImmExt should be processed after SSE2AVX. */
3251 if (!i
.tm
.opcode_modifier
.sse2avx
3252 && i
.tm
.opcode_modifier
.immext
)
3255 /* For insns with operands there are more diddles to do to the opcode. */
3258 if (!process_operands ())
3261 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3263 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3264 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3267 if (i
.tm
.opcode_modifier
.vex
)
3268 build_vex_prefix (t
);
3270 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3271 instructions may define INT_OPCODE as well, so avoid this corner
3272 case for those instructions that use MODRM. */
3273 if (i
.tm
.base_opcode
== INT_OPCODE
3274 && !i
.tm
.opcode_modifier
.modrm
3275 && i
.op
[0].imms
->X_add_number
== 3)
3277 i
.tm
.base_opcode
= INT3_OPCODE
;
3281 if ((i
.tm
.opcode_modifier
.jump
3282 || i
.tm
.opcode_modifier
.jumpbyte
3283 || i
.tm
.opcode_modifier
.jumpdword
)
3284 && i
.op
[0].disps
->X_op
== O_constant
)
3286 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3287 the absolute address given by the constant. Since ix86 jumps and
3288 calls are pc relative, we need to generate a reloc. */
3289 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3290 i
.op
[0].disps
->X_op
= O_symbol
;
3293 if (i
.tm
.opcode_modifier
.rex64
)
3296 /* For 8 bit registers we need an empty rex prefix. Also if the
3297 instruction already has a prefix, we need to convert old
3298 registers to new ones. */
3300 if ((i
.types
[0].bitfield
.reg8
3301 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3302 || (i
.types
[1].bitfield
.reg8
3303 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3304 || ((i
.types
[0].bitfield
.reg8
3305 || i
.types
[1].bitfield
.reg8
)
3310 i
.rex
|= REX_OPCODE
;
3311 for (x
= 0; x
< 2; x
++)
3313 /* Look for 8 bit operand that uses old registers. */
3314 if (i
.types
[x
].bitfield
.reg8
3315 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3317 /* In case it is "hi" register, give up. */
3318 if (i
.op
[x
].regs
->reg_num
> 3)
3319 as_bad (_("can't encode register '%s%s' in an "
3320 "instruction requiring REX prefix."),
3321 register_prefix
, i
.op
[x
].regs
->reg_name
);
3323 /* Otherwise it is equivalent to the extended register.
3324 Since the encoding doesn't change this is merely
3325 cosmetic cleanup for debug output. */
3327 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3333 add_prefix (REX_OPCODE
| i
.rex
);
3335 /* We are ready to output the insn. */
3340 parse_insn (char *line
, char *mnemonic
)
3343 char *token_start
= l
;
3346 const insn_template
*t
;
3352 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3357 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3359 as_bad (_("no such instruction: `%s'"), token_start
);
3364 if (!is_space_char (*l
)
3365 && *l
!= END_OF_INSN
3367 || (*l
!= PREFIX_SEPARATOR
3370 as_bad (_("invalid character %s in mnemonic"),
3371 output_invalid (*l
));
3374 if (token_start
== l
)
3376 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3377 as_bad (_("expecting prefix; got nothing"));
3379 as_bad (_("expecting mnemonic; got nothing"));
3383 /* Look up instruction (or prefix) via hash table. */
3384 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3386 if (*l
!= END_OF_INSN
3387 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3388 && current_templates
3389 && current_templates
->start
->opcode_modifier
.isprefix
)
3391 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3393 as_bad ((flag_code
!= CODE_64BIT
3394 ? _("`%s' is only supported in 64-bit mode")
3395 : _("`%s' is not supported in 64-bit mode")),
3396 current_templates
->start
->name
);
3399 /* If we are in 16-bit mode, do not allow addr16 or data16.
3400 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3401 if ((current_templates
->start
->opcode_modifier
.size16
3402 || current_templates
->start
->opcode_modifier
.size32
)
3403 && flag_code
!= CODE_64BIT
3404 && (current_templates
->start
->opcode_modifier
.size32
3405 ^ (flag_code
== CODE_16BIT
)))
3407 as_bad (_("redundant %s prefix"),
3408 current_templates
->start
->name
);
3411 /* Add prefix, checking for repeated prefixes. */
3412 switch (add_prefix (current_templates
->start
->base_opcode
))
3417 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3418 i
.hle_prefix
= current_templates
->start
->name
;
3420 i
.rep_prefix
= current_templates
->start
->name
;
3425 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3432 if (!current_templates
)
3434 /* Check if we should swap operand or force 32bit displacement in
3436 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3438 else if (mnem_p
- 3 == dot_p
3441 i
.disp_encoding
= disp_encoding_8bit
;
3442 else if (mnem_p
- 4 == dot_p
3446 i
.disp_encoding
= disp_encoding_32bit
;
3451 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3454 if (!current_templates
)
3457 /* See if we can get a match by trimming off a suffix. */
3460 case WORD_MNEM_SUFFIX
:
3461 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3462 i
.suffix
= SHORT_MNEM_SUFFIX
;
3464 case BYTE_MNEM_SUFFIX
:
3465 case QWORD_MNEM_SUFFIX
:
3466 i
.suffix
= mnem_p
[-1];
3468 current_templates
= (const templates
*) hash_find (op_hash
,
3471 case SHORT_MNEM_SUFFIX
:
3472 case LONG_MNEM_SUFFIX
:
3475 i
.suffix
= mnem_p
[-1];
3477 current_templates
= (const templates
*) hash_find (op_hash
,
3486 if (intel_float_operand (mnemonic
) == 1)
3487 i
.suffix
= SHORT_MNEM_SUFFIX
;
3489 i
.suffix
= LONG_MNEM_SUFFIX
;
3491 current_templates
= (const templates
*) hash_find (op_hash
,
3496 if (!current_templates
)
3498 as_bad (_("no such instruction: `%s'"), token_start
);
3503 if (current_templates
->start
->opcode_modifier
.jump
3504 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3506 /* Check for a branch hint. We allow ",pt" and ",pn" for
3507 predict taken and predict not taken respectively.
3508 I'm not sure that branch hints actually do anything on loop
3509 and jcxz insns (JumpByte) for current Pentium4 chips. They
3510 may work in the future and it doesn't hurt to accept them
3512 if (l
[0] == ',' && l
[1] == 'p')
3516 if (!add_prefix (DS_PREFIX_OPCODE
))
3520 else if (l
[2] == 'n')
3522 if (!add_prefix (CS_PREFIX_OPCODE
))
3528 /* Any other comma loses. */
3531 as_bad (_("invalid character %s in mnemonic"),
3532 output_invalid (*l
));
3536 /* Check if instruction is supported on specified architecture. */
3538 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3540 supported
|= cpu_flags_match (t
);
3541 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3545 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3547 as_bad (flag_code
== CODE_64BIT
3548 ? _("`%s' is not supported in 64-bit mode")
3549 : _("`%s' is only supported in 64-bit mode"),
3550 current_templates
->start
->name
);
3553 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3555 as_bad (_("`%s' is not supported on `%s%s'"),
3556 current_templates
->start
->name
,
3557 cpu_arch_name
? cpu_arch_name
: default_arch
,
3558 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3563 if (!cpu_arch_flags
.bitfield
.cpui386
3564 && (flag_code
!= CODE_16BIT
))
3566 as_warn (_("use .code16 to ensure correct addressing mode"));
3573 parse_operands (char *l
, const char *mnemonic
)
3577 /* 1 if operand is pending after ','. */
3578 unsigned int expecting_operand
= 0;
3580 /* Non-zero if operand parens not balanced. */
3581 unsigned int paren_not_balanced
;
3583 while (*l
!= END_OF_INSN
)
3585 /* Skip optional white space before operand. */
3586 if (is_space_char (*l
))
3588 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3590 as_bad (_("invalid character %s before operand %d"),
3591 output_invalid (*l
),
3595 token_start
= l
; /* after white space */
3596 paren_not_balanced
= 0;
3597 while (paren_not_balanced
|| *l
!= ',')
3599 if (*l
== END_OF_INSN
)
3601 if (paren_not_balanced
)
3604 as_bad (_("unbalanced parenthesis in operand %d."),
3607 as_bad (_("unbalanced brackets in operand %d."),
3612 break; /* we are done */
3614 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3616 as_bad (_("invalid character %s in operand %d"),
3617 output_invalid (*l
),
3624 ++paren_not_balanced
;
3626 --paren_not_balanced
;
3631 ++paren_not_balanced
;
3633 --paren_not_balanced
;
3637 if (l
!= token_start
)
3638 { /* Yes, we've read in another operand. */
3639 unsigned int operand_ok
;
3640 this_operand
= i
.operands
++;
3641 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3642 if (i
.operands
> MAX_OPERANDS
)
3644 as_bad (_("spurious operands; (%d operands/instruction max)"),
3648 /* Now parse operand adding info to 'i' as we go along. */
3649 END_STRING_AND_SAVE (l
);
3653 i386_intel_operand (token_start
,
3654 intel_float_operand (mnemonic
));
3656 operand_ok
= i386_att_operand (token_start
);
3658 RESTORE_END_STRING (l
);
3664 if (expecting_operand
)
3666 expecting_operand_after_comma
:
3667 as_bad (_("expecting operand after ','; got nothing"));
3672 as_bad (_("expecting operand before ','; got nothing"));
3677 /* Now *l must be either ',' or END_OF_INSN. */
3680 if (*++l
== END_OF_INSN
)
3682 /* Just skip it, if it's \n complain. */
3683 goto expecting_operand_after_comma
;
3685 expecting_operand
= 1;
3692 swap_2_operands (int xchg1
, int xchg2
)
3694 union i386_op temp_op
;
3695 i386_operand_type temp_type
;
3696 enum bfd_reloc_code_real temp_reloc
;
3698 temp_type
= i
.types
[xchg2
];
3699 i
.types
[xchg2
] = i
.types
[xchg1
];
3700 i
.types
[xchg1
] = temp_type
;
3701 temp_op
= i
.op
[xchg2
];
3702 i
.op
[xchg2
] = i
.op
[xchg1
];
3703 i
.op
[xchg1
] = temp_op
;
3704 temp_reloc
= i
.reloc
[xchg2
];
3705 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3706 i
.reloc
[xchg1
] = temp_reloc
;
3710 swap_operands (void)
3716 swap_2_operands (1, i
.operands
- 2);
3719 swap_2_operands (0, i
.operands
- 1);
3725 if (i
.mem_operands
== 2)
3727 const seg_entry
*temp_seg
;
3728 temp_seg
= i
.seg
[0];
3729 i
.seg
[0] = i
.seg
[1];
3730 i
.seg
[1] = temp_seg
;
3734 /* Try to ensure constant immediates are represented in the smallest
3739 char guess_suffix
= 0;
3743 guess_suffix
= i
.suffix
;
3744 else if (i
.reg_operands
)
3746 /* Figure out a suffix from the last register operand specified.
3747 We can't do this properly yet, ie. excluding InOutPortReg,
3748 but the following works for instructions with immediates.
3749 In any case, we can't set i.suffix yet. */
3750 for (op
= i
.operands
; --op
>= 0;)
3751 if (i
.types
[op
].bitfield
.reg8
)
3753 guess_suffix
= BYTE_MNEM_SUFFIX
;
3756 else if (i
.types
[op
].bitfield
.reg16
)
3758 guess_suffix
= WORD_MNEM_SUFFIX
;
3761 else if (i
.types
[op
].bitfield
.reg32
)
3763 guess_suffix
= LONG_MNEM_SUFFIX
;
3766 else if (i
.types
[op
].bitfield
.reg64
)
3768 guess_suffix
= QWORD_MNEM_SUFFIX
;
3772 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3773 guess_suffix
= WORD_MNEM_SUFFIX
;
3775 for (op
= i
.operands
; --op
>= 0;)
3776 if (operand_type_check (i
.types
[op
], imm
))
3778 switch (i
.op
[op
].imms
->X_op
)
3781 /* If a suffix is given, this operand may be shortened. */
3782 switch (guess_suffix
)
3784 case LONG_MNEM_SUFFIX
:
3785 i
.types
[op
].bitfield
.imm32
= 1;
3786 i
.types
[op
].bitfield
.imm64
= 1;
3788 case WORD_MNEM_SUFFIX
:
3789 i
.types
[op
].bitfield
.imm16
= 1;
3790 i
.types
[op
].bitfield
.imm32
= 1;
3791 i
.types
[op
].bitfield
.imm32s
= 1;
3792 i
.types
[op
].bitfield
.imm64
= 1;
3794 case BYTE_MNEM_SUFFIX
:
3795 i
.types
[op
].bitfield
.imm8
= 1;
3796 i
.types
[op
].bitfield
.imm8s
= 1;
3797 i
.types
[op
].bitfield
.imm16
= 1;
3798 i
.types
[op
].bitfield
.imm32
= 1;
3799 i
.types
[op
].bitfield
.imm32s
= 1;
3800 i
.types
[op
].bitfield
.imm64
= 1;
3804 /* If this operand is at most 16 bits, convert it
3805 to a signed 16 bit number before trying to see
3806 whether it will fit in an even smaller size.
3807 This allows a 16-bit operand such as $0xffe0 to
3808 be recognised as within Imm8S range. */
3809 if ((i
.types
[op
].bitfield
.imm16
)
3810 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3812 i
.op
[op
].imms
->X_add_number
=
3813 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3815 if ((i
.types
[op
].bitfield
.imm32
)
3816 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3819 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3820 ^ ((offsetT
) 1 << 31))
3821 - ((offsetT
) 1 << 31));
3824 = operand_type_or (i
.types
[op
],
3825 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3827 /* We must avoid matching of Imm32 templates when 64bit
3828 only immediate is available. */
3829 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3830 i
.types
[op
].bitfield
.imm32
= 0;
3837 /* Symbols and expressions. */
3839 /* Convert symbolic operand to proper sizes for matching, but don't
3840 prevent matching a set of insns that only supports sizes other
3841 than those matching the insn suffix. */
3843 i386_operand_type mask
, allowed
;
3844 const insn_template
*t
;
3846 operand_type_set (&mask
, 0);
3847 operand_type_set (&allowed
, 0);
3849 for (t
= current_templates
->start
;
3850 t
< current_templates
->end
;
3852 allowed
= operand_type_or (allowed
,
3853 t
->operand_types
[op
]);
3854 switch (guess_suffix
)
3856 case QWORD_MNEM_SUFFIX
:
3857 mask
.bitfield
.imm64
= 1;
3858 mask
.bitfield
.imm32s
= 1;
3860 case LONG_MNEM_SUFFIX
:
3861 mask
.bitfield
.imm32
= 1;
3863 case WORD_MNEM_SUFFIX
:
3864 mask
.bitfield
.imm16
= 1;
3866 case BYTE_MNEM_SUFFIX
:
3867 mask
.bitfield
.imm8
= 1;
3872 allowed
= operand_type_and (mask
, allowed
);
3873 if (!operand_type_all_zero (&allowed
))
3874 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3881 /* Try to use the smallest displacement type too. */
3883 optimize_disp (void)
3887 for (op
= i
.operands
; --op
>= 0;)
3888 if (operand_type_check (i
.types
[op
], disp
))
3890 if (i
.op
[op
].disps
->X_op
== O_constant
)
3892 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
3894 if (i
.types
[op
].bitfield
.disp16
3895 && (op_disp
& ~(offsetT
) 0xffff) == 0)
3897 /* If this operand is at most 16 bits, convert
3898 to a signed 16 bit number and don't use 64bit
3900 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
3901 i
.types
[op
].bitfield
.disp64
= 0;
3903 if (i
.types
[op
].bitfield
.disp32
3904 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3906 /* If this operand is at most 32 bits, convert
3907 to a signed 32 bit number and don't use 64bit
3909 op_disp
&= (((offsetT
) 2 << 31) - 1);
3910 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3911 i
.types
[op
].bitfield
.disp64
= 0;
3913 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
3915 i
.types
[op
].bitfield
.disp8
= 0;
3916 i
.types
[op
].bitfield
.disp16
= 0;
3917 i
.types
[op
].bitfield
.disp32
= 0;
3918 i
.types
[op
].bitfield
.disp32s
= 0;
3919 i
.types
[op
].bitfield
.disp64
= 0;
3923 else if (flag_code
== CODE_64BIT
)
3925 if (fits_in_signed_long (op_disp
))
3927 i
.types
[op
].bitfield
.disp64
= 0;
3928 i
.types
[op
].bitfield
.disp32s
= 1;
3930 if (i
.prefix
[ADDR_PREFIX
]
3931 && fits_in_unsigned_long (op_disp
))
3932 i
.types
[op
].bitfield
.disp32
= 1;
3934 if ((i
.types
[op
].bitfield
.disp32
3935 || i
.types
[op
].bitfield
.disp32s
3936 || i
.types
[op
].bitfield
.disp16
)
3937 && fits_in_signed_byte (op_disp
))
3938 i
.types
[op
].bitfield
.disp8
= 1;
3940 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3941 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3943 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3944 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3945 i
.types
[op
].bitfield
.disp8
= 0;
3946 i
.types
[op
].bitfield
.disp16
= 0;
3947 i
.types
[op
].bitfield
.disp32
= 0;
3948 i
.types
[op
].bitfield
.disp32s
= 0;
3949 i
.types
[op
].bitfield
.disp64
= 0;
3952 /* We only support 64bit displacement on constants. */
3953 i
.types
[op
].bitfield
.disp64
= 0;
3957 /* Check if operands are valid for the instruction. */
3960 check_VecOperands (const insn_template
*t
)
3962 /* Without VSIB byte, we can't have a vector register for index. */
3963 if (!t
->opcode_modifier
.vecsib
3965 && (i
.index_reg
->reg_type
.bitfield
.regxmm
3966 || i
.index_reg
->reg_type
.bitfield
.regymm
))
3968 i
.error
= unsupported_vector_index_register
;
3972 /* For VSIB byte, we need a vector register for index, and all vector
3973 registers must be distinct. */
3974 if (t
->opcode_modifier
.vecsib
)
3977 || !((t
->opcode_modifier
.vecsib
== VecSIB128
3978 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
3979 || (t
->opcode_modifier
.vecsib
== VecSIB256
3980 && i
.index_reg
->reg_type
.bitfield
.regymm
)))
3982 i
.error
= invalid_vsib_address
;
3986 gas_assert (i
.reg_operands
== 2);
3987 gas_assert (i
.types
[0].bitfield
.regxmm
3988 || i
.types
[0].bitfield
.regymm
);
3989 gas_assert (i
.types
[2].bitfield
.regxmm
3990 || i
.types
[2].bitfield
.regymm
);
3992 if (operand_check
== check_none
)
3994 if (register_number (i
.op
[0].regs
) != register_number (i
.index_reg
)
3995 && register_number (i
.op
[2].regs
) != register_number (i
.index_reg
)
3996 && register_number (i
.op
[0].regs
) != register_number (i
.op
[2].regs
))
3998 if (operand_check
== check_error
)
4000 i
.error
= invalid_vector_register_set
;
4003 as_warn (_("mask, index, and destination registers should be distinct"));
4009 /* Check if operands are valid for the instruction. Update VEX
4013 VEX_check_operands (const insn_template
*t
)
4015 if (!t
->opcode_modifier
.vex
)
4018 /* Only check VEX_Imm4, which must be the first operand. */
4019 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4021 if (i
.op
[0].imms
->X_op
!= O_constant
4022 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4028 /* Turn off Imm8 so that update_imm won't complain. */
4029 i
.types
[0] = vec_imm4
;
4035 static const insn_template
*
4036 match_template (void)
4038 /* Points to template once we've found it. */
4039 const insn_template
*t
;
4040 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4041 i386_operand_type overlap4
;
4042 unsigned int found_reverse_match
;
4043 i386_opcode_modifier suffix_check
;
4044 i386_operand_type operand_types
[MAX_OPERANDS
];
4045 int addr_prefix_disp
;
4047 unsigned int found_cpu_match
;
4048 unsigned int check_register
;
4049 enum i386_error specific_error
= 0;
4051 #if MAX_OPERANDS != 5
4052 # error "MAX_OPERANDS must be 5."
4055 found_reverse_match
= 0;
4056 addr_prefix_disp
= -1;
4058 memset (&suffix_check
, 0, sizeof (suffix_check
));
4059 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4060 suffix_check
.no_bsuf
= 1;
4061 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4062 suffix_check
.no_wsuf
= 1;
4063 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4064 suffix_check
.no_ssuf
= 1;
4065 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4066 suffix_check
.no_lsuf
= 1;
4067 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4068 suffix_check
.no_qsuf
= 1;
4069 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4070 suffix_check
.no_ldsuf
= 1;
4072 /* Must have right number of operands. */
4073 i
.error
= number_of_operands_mismatch
;
4075 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4077 addr_prefix_disp
= -1;
4079 if (i
.operands
!= t
->operands
)
4082 /* Check processor support. */
4083 i
.error
= unsupported
;
4084 found_cpu_match
= (cpu_flags_match (t
)
4085 == CPU_FLAGS_PERFECT_MATCH
);
4086 if (!found_cpu_match
)
4089 /* Check old gcc support. */
4090 i
.error
= old_gcc_only
;
4091 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4094 /* Check AT&T mnemonic. */
4095 i
.error
= unsupported_with_intel_mnemonic
;
4096 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4099 /* Check AT&T/Intel syntax. */
4100 i
.error
= unsupported_syntax
;
4101 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4102 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4105 /* Check the suffix, except for some instructions in intel mode. */
4106 i
.error
= invalid_instruction_suffix
;
4107 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4108 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4109 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4110 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4111 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4112 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4113 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4116 if (!operand_size_match (t
))
4119 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4120 operand_types
[j
] = t
->operand_types
[j
];
4122 /* In general, don't allow 64-bit operands in 32-bit mode. */
4123 if (i
.suffix
== QWORD_MNEM_SUFFIX
4124 && flag_code
!= CODE_64BIT
4126 ? (!t
->opcode_modifier
.ignoresize
4127 && !intel_float_operand (t
->name
))
4128 : intel_float_operand (t
->name
) != 2)
4129 && ((!operand_types
[0].bitfield
.regmmx
4130 && !operand_types
[0].bitfield
.regxmm
4131 && !operand_types
[0].bitfield
.regymm
)
4132 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4133 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
4134 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
4135 && (t
->base_opcode
!= 0x0fc7
4136 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4139 /* In general, don't allow 32-bit operands on pre-386. */
4140 else if (i
.suffix
== LONG_MNEM_SUFFIX
4141 && !cpu_arch_flags
.bitfield
.cpui386
4143 ? (!t
->opcode_modifier
.ignoresize
4144 && !intel_float_operand (t
->name
))
4145 : intel_float_operand (t
->name
) != 2)
4146 && ((!operand_types
[0].bitfield
.regmmx
4147 && !operand_types
[0].bitfield
.regxmm
)
4148 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4149 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4152 /* Do not verify operands when there are none. */
4156 /* We've found a match; break out of loop. */
4160 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4161 into Disp32/Disp16/Disp32 operand. */
4162 if (i
.prefix
[ADDR_PREFIX
] != 0)
4164 /* There should be only one Disp operand. */
4168 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4170 if (operand_types
[j
].bitfield
.disp16
)
4172 addr_prefix_disp
= j
;
4173 operand_types
[j
].bitfield
.disp32
= 1;
4174 operand_types
[j
].bitfield
.disp16
= 0;
4180 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4182 if (operand_types
[j
].bitfield
.disp32
)
4184 addr_prefix_disp
= j
;
4185 operand_types
[j
].bitfield
.disp32
= 0;
4186 operand_types
[j
].bitfield
.disp16
= 1;
4192 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4194 if (operand_types
[j
].bitfield
.disp64
)
4196 addr_prefix_disp
= j
;
4197 operand_types
[j
].bitfield
.disp64
= 0;
4198 operand_types
[j
].bitfield
.disp32
= 1;
4206 /* We check register size if needed. */
4207 check_register
= t
->opcode_modifier
.checkregsize
;
4208 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4209 switch (t
->operands
)
4212 if (!operand_type_match (overlap0
, i
.types
[0]))
4216 /* xchg %eax, %eax is a special case. It is an aliase for nop
4217 only in 32bit mode and we can use opcode 0x90. In 64bit
4218 mode, we can't use 0x90 for xchg %eax, %eax since it should
4219 zero-extend %eax to %rax. */
4220 if (flag_code
== CODE_64BIT
4221 && t
->base_opcode
== 0x90
4222 && operand_type_equal (&i
.types
[0], &acc32
)
4223 && operand_type_equal (&i
.types
[1], &acc32
))
4227 /* If we swap operand in encoding, we either match
4228 the next one or reverse direction of operands. */
4229 if (t
->opcode_modifier
.s
)
4231 else if (t
->opcode_modifier
.d
)
4236 /* If we swap operand in encoding, we match the next one. */
4237 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4241 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4242 if (!operand_type_match (overlap0
, i
.types
[0])
4243 || !operand_type_match (overlap1
, i
.types
[1])
4245 && !operand_type_register_match (overlap0
, i
.types
[0],
4247 overlap1
, i
.types
[1],
4250 /* Check if other direction is valid ... */
4251 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4255 /* Try reversing direction of operands. */
4256 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4257 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4258 if (!operand_type_match (overlap0
, i
.types
[0])
4259 || !operand_type_match (overlap1
, i
.types
[1])
4261 && !operand_type_register_match (overlap0
,
4268 /* Does not match either direction. */
4271 /* found_reverse_match holds which of D or FloatDR
4273 if (t
->opcode_modifier
.d
)
4274 found_reverse_match
= Opcode_D
;
4275 else if (t
->opcode_modifier
.floatd
)
4276 found_reverse_match
= Opcode_FloatD
;
4278 found_reverse_match
= 0;
4279 if (t
->opcode_modifier
.floatr
)
4280 found_reverse_match
|= Opcode_FloatR
;
4284 /* Found a forward 2 operand match here. */
4285 switch (t
->operands
)
4288 overlap4
= operand_type_and (i
.types
[4],
4291 overlap3
= operand_type_and (i
.types
[3],
4294 overlap2
= operand_type_and (i
.types
[2],
4299 switch (t
->operands
)
4302 if (!operand_type_match (overlap4
, i
.types
[4])
4303 || !operand_type_register_match (overlap3
,
4311 if (!operand_type_match (overlap3
, i
.types
[3])
4313 && !operand_type_register_match (overlap2
,
4321 /* Here we make use of the fact that there are no
4322 reverse match 3 operand instructions, and all 3
4323 operand instructions only need to be checked for
4324 register consistency between operands 2 and 3. */
4325 if (!operand_type_match (overlap2
, i
.types
[2])
4327 && !operand_type_register_match (overlap1
,
4337 /* Found either forward/reverse 2, 3 or 4 operand match here:
4338 slip through to break. */
4340 if (!found_cpu_match
)
4342 found_reverse_match
= 0;
4346 /* Check if vector and VEX operands are valid. */
4347 if (check_VecOperands (t
) || VEX_check_operands (t
))
4349 specific_error
= i
.error
;
4353 /* We've found a match; break out of loop. */
4357 if (t
== current_templates
->end
)
4359 /* We found no match. */
4360 const char *err_msg
;
4361 switch (specific_error
? specific_error
: i
.error
)
4365 case operand_size_mismatch
:
4366 err_msg
= _("operand size mismatch");
4368 case operand_type_mismatch
:
4369 err_msg
= _("operand type mismatch");
4371 case register_type_mismatch
:
4372 err_msg
= _("register type mismatch");
4374 case number_of_operands_mismatch
:
4375 err_msg
= _("number of operands mismatch");
4377 case invalid_instruction_suffix
:
4378 err_msg
= _("invalid instruction suffix");
4381 err_msg
= _("constant doesn't fit in 4 bits");
4384 err_msg
= _("only supported with old gcc");
4386 case unsupported_with_intel_mnemonic
:
4387 err_msg
= _("unsupported with Intel mnemonic");
4389 case unsupported_syntax
:
4390 err_msg
= _("unsupported syntax");
4393 as_bad (_("unsupported instruction `%s'"),
4394 current_templates
->start
->name
);
4396 case invalid_vsib_address
:
4397 err_msg
= _("invalid VSIB address");
4399 case invalid_vector_register_set
:
4400 err_msg
= _("mask, index, and destination registers must be distinct");
4402 case unsupported_vector_index_register
:
4403 err_msg
= _("unsupported vector index register");
4406 as_bad (_("%s for `%s'"), err_msg
,
4407 current_templates
->start
->name
);
4411 if (!quiet_warnings
)
4414 && (i
.types
[0].bitfield
.jumpabsolute
4415 != operand_types
[0].bitfield
.jumpabsolute
))
4417 as_warn (_("indirect %s without `*'"), t
->name
);
4420 if (t
->opcode_modifier
.isprefix
4421 && t
->opcode_modifier
.ignoresize
)
4423 /* Warn them that a data or address size prefix doesn't
4424 affect assembly of the next line of code. */
4425 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4429 /* Copy the template we found. */
4432 if (addr_prefix_disp
!= -1)
4433 i
.tm
.operand_types
[addr_prefix_disp
]
4434 = operand_types
[addr_prefix_disp
];
4436 if (found_reverse_match
)
4438 /* If we found a reverse match we must alter the opcode
4439 direction bit. found_reverse_match holds bits to change
4440 (different for int & float insns). */
4442 i
.tm
.base_opcode
^= found_reverse_match
;
4444 i
.tm
.operand_types
[0] = operand_types
[1];
4445 i
.tm
.operand_types
[1] = operand_types
[0];
4454 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4455 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4457 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4459 as_bad (_("`%s' operand %d must use `%ses' segment"),
4465 /* There's only ever one segment override allowed per instruction.
4466 This instruction possibly has a legal segment override on the
4467 second operand, so copy the segment to where non-string
4468 instructions store it, allowing common code. */
4469 i
.seg
[0] = i
.seg
[1];
4471 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4473 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4475 as_bad (_("`%s' operand %d must use `%ses' segment"),
4486 process_suffix (void)
4488 /* If matched instruction specifies an explicit instruction mnemonic
4490 if (i
.tm
.opcode_modifier
.size16
)
4491 i
.suffix
= WORD_MNEM_SUFFIX
;
4492 else if (i
.tm
.opcode_modifier
.size32
)
4493 i
.suffix
= LONG_MNEM_SUFFIX
;
4494 else if (i
.tm
.opcode_modifier
.size64
)
4495 i
.suffix
= QWORD_MNEM_SUFFIX
;
4496 else if (i
.reg_operands
)
4498 /* If there's no instruction mnemonic suffix we try to invent one
4499 based on register operands. */
4502 /* We take i.suffix from the last register operand specified,
4503 Destination register type is more significant than source
4504 register type. crc32 in SSE4.2 prefers source register
4506 if (i
.tm
.base_opcode
== 0xf20f38f1)
4508 if (i
.types
[0].bitfield
.reg16
)
4509 i
.suffix
= WORD_MNEM_SUFFIX
;
4510 else if (i
.types
[0].bitfield
.reg32
)
4511 i
.suffix
= LONG_MNEM_SUFFIX
;
4512 else if (i
.types
[0].bitfield
.reg64
)
4513 i
.suffix
= QWORD_MNEM_SUFFIX
;
4515 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4517 if (i
.types
[0].bitfield
.reg8
)
4518 i
.suffix
= BYTE_MNEM_SUFFIX
;
4525 if (i
.tm
.base_opcode
== 0xf20f38f1
4526 || i
.tm
.base_opcode
== 0xf20f38f0)
4528 /* We have to know the operand size for crc32. */
4529 as_bad (_("ambiguous memory operand size for `%s`"),
4534 for (op
= i
.operands
; --op
>= 0;)
4535 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4537 if (i
.types
[op
].bitfield
.reg8
)
4539 i
.suffix
= BYTE_MNEM_SUFFIX
;
4542 else if (i
.types
[op
].bitfield
.reg16
)
4544 i
.suffix
= WORD_MNEM_SUFFIX
;
4547 else if (i
.types
[op
].bitfield
.reg32
)
4549 i
.suffix
= LONG_MNEM_SUFFIX
;
4552 else if (i
.types
[op
].bitfield
.reg64
)
4554 i
.suffix
= QWORD_MNEM_SUFFIX
;
4560 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4563 && i
.tm
.opcode_modifier
.ignoresize
4564 && i
.tm
.opcode_modifier
.no_bsuf
)
4566 else if (!check_byte_reg ())
4569 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4572 && i
.tm
.opcode_modifier
.ignoresize
4573 && i
.tm
.opcode_modifier
.no_lsuf
)
4575 else if (!check_long_reg ())
4578 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4581 && i
.tm
.opcode_modifier
.ignoresize
4582 && i
.tm
.opcode_modifier
.no_qsuf
)
4584 else if (!check_qword_reg ())
4587 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4590 && i
.tm
.opcode_modifier
.ignoresize
4591 && i
.tm
.opcode_modifier
.no_wsuf
)
4593 else if (!check_word_reg ())
4596 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4597 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4599 /* Skip if the instruction has x/y suffix. match_template
4600 should check if it is a valid suffix. */
4602 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4603 /* Do nothing if the instruction is going to ignore the prefix. */
4608 else if (i
.tm
.opcode_modifier
.defaultsize
4610 /* exclude fldenv/frstor/fsave/fstenv */
4611 && i
.tm
.opcode_modifier
.no_ssuf
)
4613 i
.suffix
= stackop_size
;
4615 else if (intel_syntax
4617 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4618 || i
.tm
.opcode_modifier
.jumpbyte
4619 || i
.tm
.opcode_modifier
.jumpintersegment
4620 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4621 && i
.tm
.extension_opcode
<= 3)))
4626 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4628 i
.suffix
= QWORD_MNEM_SUFFIX
;
4632 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4633 i
.suffix
= LONG_MNEM_SUFFIX
;
4636 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4637 i
.suffix
= WORD_MNEM_SUFFIX
;
4646 if (i
.tm
.opcode_modifier
.w
)
4648 as_bad (_("no instruction mnemonic suffix given and "
4649 "no register operands; can't size instruction"));
4655 unsigned int suffixes
;
4657 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4658 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4660 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4662 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4664 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4666 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4669 /* There are more than suffix matches. */
4670 if (i
.tm
.opcode_modifier
.w
4671 || ((suffixes
& (suffixes
- 1))
4672 && !i
.tm
.opcode_modifier
.defaultsize
4673 && !i
.tm
.opcode_modifier
.ignoresize
))
4675 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4681 /* Change the opcode based on the operand size given by i.suffix;
4682 We don't need to change things for byte insns. */
4685 && i
.suffix
!= BYTE_MNEM_SUFFIX
4686 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4687 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4689 /* It's not a byte, select word/dword operation. */
4690 if (i
.tm
.opcode_modifier
.w
)
4692 if (i
.tm
.opcode_modifier
.shortform
)
4693 i
.tm
.base_opcode
|= 8;
4695 i
.tm
.base_opcode
|= 1;
4698 /* Now select between word & dword operations via the operand
4699 size prefix, except for instructions that will ignore this
4701 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4703 /* The address size override prefix changes the size of the
4705 if ((flag_code
== CODE_32BIT
4706 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4707 || (flag_code
!= CODE_32BIT
4708 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4709 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4712 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4713 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4714 && !i
.tm
.opcode_modifier
.ignoresize
4715 && !i
.tm
.opcode_modifier
.floatmf
4716 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4717 || (flag_code
== CODE_64BIT
4718 && i
.tm
.opcode_modifier
.jumpbyte
)))
4720 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4722 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4723 prefix
= ADDR_PREFIX_OPCODE
;
4725 if (!add_prefix (prefix
))
4729 /* Set mode64 for an operand. */
4730 if (i
.suffix
== QWORD_MNEM_SUFFIX
4731 && flag_code
== CODE_64BIT
4732 && !i
.tm
.opcode_modifier
.norex64
)
4734 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4735 need rex64. cmpxchg8b is also a special case. */
4736 if (! (i
.operands
== 2
4737 && i
.tm
.base_opcode
== 0x90
4738 && i
.tm
.extension_opcode
== None
4739 && operand_type_equal (&i
.types
[0], &acc64
)
4740 && operand_type_equal (&i
.types
[1], &acc64
))
4741 && ! (i
.operands
== 1
4742 && i
.tm
.base_opcode
== 0xfc7
4743 && i
.tm
.extension_opcode
== 1
4744 && !operand_type_check (i
.types
[0], reg
)
4745 && operand_type_check (i
.types
[0], anymem
)))
4749 /* Size floating point instruction. */
4750 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4751 if (i
.tm
.opcode_modifier
.floatmf
)
4752 i
.tm
.base_opcode
^= 4;
4759 check_byte_reg (void)
4763 for (op
= i
.operands
; --op
>= 0;)
4765 /* If this is an eight bit register, it's OK. If it's the 16 or
4766 32 bit version of an eight bit register, we will just use the
4767 low portion, and that's OK too. */
4768 if (i
.types
[op
].bitfield
.reg8
)
4771 /* I/O port address operands are OK too. */
4772 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4775 /* crc32 doesn't generate this warning. */
4776 if (i
.tm
.base_opcode
== 0xf20f38f0)
4779 if ((i
.types
[op
].bitfield
.reg16
4780 || i
.types
[op
].bitfield
.reg32
4781 || i
.types
[op
].bitfield
.reg64
)
4782 && i
.op
[op
].regs
->reg_num
< 4
4783 /* Prohibit these changes in 64bit mode, since the lowering
4784 would be more complicated. */
4785 && flag_code
!= CODE_64BIT
)
4787 #if REGISTER_WARNINGS
4788 if (!quiet_warnings
)
4789 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4791 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4792 ? REGNAM_AL
- REGNAM_AX
4793 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4795 i
.op
[op
].regs
->reg_name
,
4800 /* Any other register is bad. */
4801 if (i
.types
[op
].bitfield
.reg16
4802 || i
.types
[op
].bitfield
.reg32
4803 || i
.types
[op
].bitfield
.reg64
4804 || i
.types
[op
].bitfield
.regmmx
4805 || i
.types
[op
].bitfield
.regxmm
4806 || i
.types
[op
].bitfield
.regymm
4807 || i
.types
[op
].bitfield
.sreg2
4808 || i
.types
[op
].bitfield
.sreg3
4809 || i
.types
[op
].bitfield
.control
4810 || i
.types
[op
].bitfield
.debug
4811 || i
.types
[op
].bitfield
.test
4812 || i
.types
[op
].bitfield
.floatreg
4813 || i
.types
[op
].bitfield
.floatacc
)
4815 as_bad (_("`%s%s' not allowed with `%s%c'"),
4817 i
.op
[op
].regs
->reg_name
,
4827 check_long_reg (void)
4831 for (op
= i
.operands
; --op
>= 0;)
4832 /* Reject eight bit registers, except where the template requires
4833 them. (eg. movzb) */
4834 if (i
.types
[op
].bitfield
.reg8
4835 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4836 || i
.tm
.operand_types
[op
].bitfield
.reg32
4837 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4839 as_bad (_("`%s%s' not allowed with `%s%c'"),
4841 i
.op
[op
].regs
->reg_name
,
4846 /* Warn if the e prefix on a general reg is missing. */
4847 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4848 && i
.types
[op
].bitfield
.reg16
4849 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4850 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4852 /* Prohibit these changes in the 64bit mode, since the
4853 lowering is more complicated. */
4854 if (flag_code
== CODE_64BIT
)
4856 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4857 register_prefix
, i
.op
[op
].regs
->reg_name
,
4861 #if REGISTER_WARNINGS
4863 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4865 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4867 i
.op
[op
].regs
->reg_name
,
4871 /* Warn if the r prefix on a general reg is missing. */
4872 else if (i
.types
[op
].bitfield
.reg64
4873 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4874 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4877 && i
.tm
.opcode_modifier
.toqword
4878 && !i
.types
[0].bitfield
.regxmm
)
4880 /* Convert to QWORD. We want REX byte. */
4881 i
.suffix
= QWORD_MNEM_SUFFIX
;
4885 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4886 register_prefix
, i
.op
[op
].regs
->reg_name
,
4895 check_qword_reg (void)
4899 for (op
= i
.operands
; --op
>= 0; )
4900 /* Reject eight bit registers, except where the template requires
4901 them. (eg. movzb) */
4902 if (i
.types
[op
].bitfield
.reg8
4903 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4904 || i
.tm
.operand_types
[op
].bitfield
.reg32
4905 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4907 as_bad (_("`%s%s' not allowed with `%s%c'"),
4909 i
.op
[op
].regs
->reg_name
,
4914 /* Warn if the e prefix on a general reg is missing. */
4915 else if ((i
.types
[op
].bitfield
.reg16
4916 || i
.types
[op
].bitfield
.reg32
)
4917 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4918 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4920 /* Prohibit these changes in the 64bit mode, since the
4921 lowering is more complicated. */
4923 && i
.tm
.opcode_modifier
.todword
4924 && !i
.types
[0].bitfield
.regxmm
)
4926 /* Convert to DWORD. We don't want REX byte. */
4927 i
.suffix
= LONG_MNEM_SUFFIX
;
4931 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4932 register_prefix
, i
.op
[op
].regs
->reg_name
,
4941 check_word_reg (void)
4944 for (op
= i
.operands
; --op
>= 0;)
4945 /* Reject eight bit registers, except where the template requires
4946 them. (eg. movzb) */
4947 if (i
.types
[op
].bitfield
.reg8
4948 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4949 || i
.tm
.operand_types
[op
].bitfield
.reg32
4950 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4952 as_bad (_("`%s%s' not allowed with `%s%c'"),
4954 i
.op
[op
].regs
->reg_name
,
4959 /* Warn if the e prefix on a general reg is present. */
4960 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4961 && i
.types
[op
].bitfield
.reg32
4962 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4963 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4965 /* Prohibit these changes in the 64bit mode, since the
4966 lowering is more complicated. */
4967 if (flag_code
== CODE_64BIT
)
4969 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
4970 register_prefix
, i
.op
[op
].regs
->reg_name
,
4975 #if REGISTER_WARNINGS
4976 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4978 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4980 i
.op
[op
].regs
->reg_name
,
4988 update_imm (unsigned int j
)
4990 i386_operand_type overlap
= i
.types
[j
];
4991 if ((overlap
.bitfield
.imm8
4992 || overlap
.bitfield
.imm8s
4993 || overlap
.bitfield
.imm16
4994 || overlap
.bitfield
.imm32
4995 || overlap
.bitfield
.imm32s
4996 || overlap
.bitfield
.imm64
)
4997 && !operand_type_equal (&overlap
, &imm8
)
4998 && !operand_type_equal (&overlap
, &imm8s
)
4999 && !operand_type_equal (&overlap
, &imm16
)
5000 && !operand_type_equal (&overlap
, &imm32
)
5001 && !operand_type_equal (&overlap
, &imm32s
)
5002 && !operand_type_equal (&overlap
, &imm64
))
5006 i386_operand_type temp
;
5008 operand_type_set (&temp
, 0);
5009 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5011 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5012 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5014 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5015 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5016 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5018 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5019 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5022 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5025 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5026 || operand_type_equal (&overlap
, &imm16_32
)
5027 || operand_type_equal (&overlap
, &imm16_32s
))
5029 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5034 if (!operand_type_equal (&overlap
, &imm8
)
5035 && !operand_type_equal (&overlap
, &imm8s
)
5036 && !operand_type_equal (&overlap
, &imm16
)
5037 && !operand_type_equal (&overlap
, &imm32
)
5038 && !operand_type_equal (&overlap
, &imm32s
)
5039 && !operand_type_equal (&overlap
, &imm64
))
5041 as_bad (_("no instruction mnemonic suffix given; "
5042 "can't determine immediate size"));
5046 i
.types
[j
] = overlap
;
5056 /* Update the first 2 immediate operands. */
5057 n
= i
.operands
> 2 ? 2 : i
.operands
;
5060 for (j
= 0; j
< n
; j
++)
5061 if (update_imm (j
) == 0)
5064 /* The 3rd operand can't be immediate operand. */
5065 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5072 bad_implicit_operand (int xmm
)
5074 const char *ireg
= xmm
? "xmm0" : "ymm0";
5077 as_bad (_("the last operand of `%s' must be `%s%s'"),
5078 i
.tm
.name
, register_prefix
, ireg
);
5080 as_bad (_("the first operand of `%s' must be `%s%s'"),
5081 i
.tm
.name
, register_prefix
, ireg
);
5086 process_operands (void)
5088 /* Default segment register this instruction will use for memory
5089 accesses. 0 means unknown. This is only for optimizing out
5090 unnecessary segment overrides. */
5091 const seg_entry
*default_seg
= 0;
5093 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5095 unsigned int dupl
= i
.operands
;
5096 unsigned int dest
= dupl
- 1;
5099 /* The destination must be an xmm register. */
5100 gas_assert (i
.reg_operands
5101 && MAX_OPERANDS
> dupl
5102 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5104 if (i
.tm
.opcode_modifier
.firstxmm0
)
5106 /* The first operand is implicit and must be xmm0. */
5107 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5108 if (register_number (i
.op
[0].regs
) != 0)
5109 return bad_implicit_operand (1);
5111 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5113 /* Keep xmm0 for instructions with VEX prefix and 3
5119 /* We remove the first xmm0 and keep the number of
5120 operands unchanged, which in fact duplicates the
5122 for (j
= 1; j
< i
.operands
; j
++)
5124 i
.op
[j
- 1] = i
.op
[j
];
5125 i
.types
[j
- 1] = i
.types
[j
];
5126 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5130 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5132 gas_assert ((MAX_OPERANDS
- 1) > dupl
5133 && (i
.tm
.opcode_modifier
.vexsources
5136 /* Add the implicit xmm0 for instructions with VEX prefix
5138 for (j
= i
.operands
; j
> 0; j
--)
5140 i
.op
[j
] = i
.op
[j
- 1];
5141 i
.types
[j
] = i
.types
[j
- 1];
5142 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5145 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5146 i
.types
[0] = regxmm
;
5147 i
.tm
.operand_types
[0] = regxmm
;
5150 i
.reg_operands
+= 2;
5155 i
.op
[dupl
] = i
.op
[dest
];
5156 i
.types
[dupl
] = i
.types
[dest
];
5157 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5166 i
.op
[dupl
] = i
.op
[dest
];
5167 i
.types
[dupl
] = i
.types
[dest
];
5168 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5171 if (i
.tm
.opcode_modifier
.immext
)
5174 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5178 /* The first operand is implicit and must be xmm0/ymm0. */
5179 gas_assert (i
.reg_operands
5180 && (operand_type_equal (&i
.types
[0], ®xmm
)
5181 || operand_type_equal (&i
.types
[0], ®ymm
)));
5182 if (register_number (i
.op
[0].regs
) != 0)
5183 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5185 for (j
= 1; j
< i
.operands
; j
++)
5187 i
.op
[j
- 1] = i
.op
[j
];
5188 i
.types
[j
- 1] = i
.types
[j
];
5190 /* We need to adjust fields in i.tm since they are used by
5191 build_modrm_byte. */
5192 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5199 else if (i
.tm
.opcode_modifier
.regkludge
)
5201 /* The imul $imm, %reg instruction is converted into
5202 imul $imm, %reg, %reg, and the clr %reg instruction
5203 is converted into xor %reg, %reg. */
5205 unsigned int first_reg_op
;
5207 if (operand_type_check (i
.types
[0], reg
))
5211 /* Pretend we saw the extra register operand. */
5212 gas_assert (i
.reg_operands
== 1
5213 && i
.op
[first_reg_op
+ 1].regs
== 0);
5214 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5215 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5220 if (i
.tm
.opcode_modifier
.shortform
)
5222 if (i
.types
[0].bitfield
.sreg2
5223 || i
.types
[0].bitfield
.sreg3
)
5225 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5226 && i
.op
[0].regs
->reg_num
== 1)
5228 as_bad (_("you can't `pop %scs'"), register_prefix
);
5231 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5232 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5237 /* The register or float register operand is in operand
5241 if (i
.types
[0].bitfield
.floatreg
5242 || operand_type_check (i
.types
[0], reg
))
5246 /* Register goes in low 3 bits of opcode. */
5247 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5248 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5250 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5252 /* Warn about some common errors, but press on regardless.
5253 The first case can be generated by gcc (<= 2.8.1). */
5254 if (i
.operands
== 2)
5256 /* Reversed arguments on faddp, fsubp, etc. */
5257 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5258 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5259 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5263 /* Extraneous `l' suffix on fp insn. */
5264 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5265 register_prefix
, i
.op
[0].regs
->reg_name
);
5270 else if (i
.tm
.opcode_modifier
.modrm
)
5272 /* The opcode is completed (modulo i.tm.extension_opcode which
5273 must be put into the modrm byte). Now, we make the modrm and
5274 index base bytes based on all the info we've collected. */
5276 default_seg
= build_modrm_byte ();
5278 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5282 else if (i
.tm
.opcode_modifier
.isstring
)
5284 /* For the string instructions that allow a segment override
5285 on one of their operands, the default segment is ds. */
5289 if (i
.tm
.base_opcode
== 0x8d /* lea */
5292 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5294 /* If a segment was explicitly specified, and the specified segment
5295 is not the default, use an opcode prefix to select it. If we
5296 never figured out what the default segment is, then default_seg
5297 will be zero at this point, and the specified segment prefix will
5299 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5301 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5307 static const seg_entry
*
5308 build_modrm_byte (void)
5310 const seg_entry
*default_seg
= 0;
5311 unsigned int source
, dest
;
5314 /* The first operand of instructions with VEX prefix and 3 sources
5315 must be VEX_Imm4. */
5316 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5319 unsigned int nds
, reg_slot
;
5322 if (i
.tm
.opcode_modifier
.veximmext
5323 && i
.tm
.opcode_modifier
.immext
)
5325 dest
= i
.operands
- 2;
5326 gas_assert (dest
== 3);
5329 dest
= i
.operands
- 1;
5332 /* There are 2 kinds of instructions:
5333 1. 5 operands: 4 register operands or 3 register operands
5334 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5335 VexW0 or VexW1. The destination must be either XMM or YMM
5337 2. 4 operands: 4 register operands or 3 register operands
5338 plus 1 memory operand, VexXDS, and VexImmExt */
5339 gas_assert ((i
.reg_operands
== 4
5340 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5341 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5342 && (i
.tm
.opcode_modifier
.veximmext
5343 || (i
.imm_operands
== 1
5344 && i
.types
[0].bitfield
.vec_imm4
5345 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5346 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5347 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5348 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)))));
5350 if (i
.imm_operands
== 0)
5352 /* When there is no immediate operand, generate an 8bit
5353 immediate operand to encode the first operand. */
5354 exp
= &im_expressions
[i
.imm_operands
++];
5355 i
.op
[i
.operands
].imms
= exp
;
5356 i
.types
[i
.operands
] = imm8
;
5358 /* If VexW1 is set, the first operand is the source and
5359 the second operand is encoded in the immediate operand. */
5360 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5371 /* FMA swaps REG and NDS. */
5372 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5380 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5382 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5384 exp
->X_op
= O_constant
;
5385 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
5389 unsigned int imm_slot
;
5391 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5393 /* If VexW0 is set, the third operand is the source and
5394 the second operand is encoded in the immediate
5401 /* VexW1 is set, the second operand is the source and
5402 the third operand is encoded in the immediate
5408 if (i
.tm
.opcode_modifier
.immext
)
5410 /* When ImmExt is set, the immdiate byte is the last
5412 imm_slot
= i
.operands
- 1;
5420 /* Turn on Imm8 so that output_imm will generate it. */
5421 i
.types
[imm_slot
].bitfield
.imm8
= 1;
5424 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5426 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5428 i
.op
[imm_slot
].imms
->X_add_number
5429 |= register_number (i
.op
[reg_slot
].regs
) << 4;
5432 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
5433 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5435 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5440 /* i.reg_operands MUST be the number of real register operands;
5441 implicit registers do not count. If there are 3 register
5442 operands, it must be a instruction with VexNDS. For a
5443 instruction with VexNDD, the destination register is encoded
5444 in VEX prefix. If there are 4 register operands, it must be
5445 a instruction with VEX prefix and 3 sources. */
5446 if (i
.mem_operands
== 0
5447 && ((i
.reg_operands
== 2
5448 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
5449 || (i
.reg_operands
== 3
5450 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5451 || (i
.reg_operands
== 4 && vex_3_sources
)))
5459 /* When there are 3 operands, one of them may be immediate,
5460 which may be the first or the last operand. Otherwise,
5461 the first operand must be shift count register (cl) or it
5462 is an instruction with VexNDS. */
5463 gas_assert (i
.imm_operands
== 1
5464 || (i
.imm_operands
== 0
5465 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5466 || i
.types
[0].bitfield
.shiftcount
)));
5467 if (operand_type_check (i
.types
[0], imm
)
5468 || i
.types
[0].bitfield
.shiftcount
)
5474 /* When there are 4 operands, the first two must be 8bit
5475 immediate operands. The source operand will be the 3rd
5478 For instructions with VexNDS, if the first operand
5479 an imm8, the source operand is the 2nd one. If the last
5480 operand is imm8, the source operand is the first one. */
5481 gas_assert ((i
.imm_operands
== 2
5482 && i
.types
[0].bitfield
.imm8
5483 && i
.types
[1].bitfield
.imm8
)
5484 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5485 && i
.imm_operands
== 1
5486 && (i
.types
[0].bitfield
.imm8
5487 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5488 if (i
.imm_operands
== 2)
5492 if (i
.types
[0].bitfield
.imm8
)
5508 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5510 /* For instructions with VexNDS, the register-only
5511 source operand must be 32/64bit integer, XMM or
5512 YMM register. It is encoded in VEX prefix. We
5513 need to clear RegMem bit before calling
5514 operand_type_equal. */
5516 i386_operand_type op
;
5519 /* Check register-only source operand when two source
5520 operands are swapped. */
5521 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
5522 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
5530 op
= i
.tm
.operand_types
[vvvv
];
5531 op
.bitfield
.regmem
= 0;
5532 if ((dest
+ 1) >= i
.operands
5533 || (op
.bitfield
.reg32
!= 1
5534 && !op
.bitfield
.reg64
!= 1
5535 && !operand_type_equal (&op
, ®xmm
)
5536 && !operand_type_equal (&op
, ®ymm
)))
5538 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
5544 /* One of the register operands will be encoded in the i.tm.reg
5545 field, the other in the combined i.tm.mode and i.tm.regmem
5546 fields. If no form of this instruction supports a memory
5547 destination operand, then we assume the source operand may
5548 sometimes be a memory operand and so we need to store the
5549 destination in the i.rm.reg field. */
5550 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5551 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5553 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5554 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5555 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5557 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5562 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5563 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5564 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5566 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5569 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5571 if (!i
.types
[0].bitfield
.control
5572 && !i
.types
[1].bitfield
.control
)
5574 i
.rex
&= ~(REX_R
| REX_B
);
5575 add_prefix (LOCK_PREFIX_OPCODE
);
5579 { /* If it's not 2 reg operands... */
5584 unsigned int fake_zero_displacement
= 0;
5587 for (op
= 0; op
< i
.operands
; op
++)
5588 if (operand_type_check (i
.types
[op
], anymem
))
5590 gas_assert (op
< i
.operands
);
5592 if (i
.tm
.opcode_modifier
.vecsib
)
5594 if (i
.index_reg
->reg_num
== RegEiz
5595 || i
.index_reg
->reg_num
== RegRiz
)
5598 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5601 i
.sib
.base
= NO_BASE_REGISTER
;
5602 i
.sib
.scale
= i
.log2_scale_factor
;
5603 i
.types
[op
].bitfield
.disp8
= 0;
5604 i
.types
[op
].bitfield
.disp16
= 0;
5605 i
.types
[op
].bitfield
.disp64
= 0;
5606 if (flag_code
!= CODE_64BIT
)
5608 /* Must be 32 bit */
5609 i
.types
[op
].bitfield
.disp32
= 1;
5610 i
.types
[op
].bitfield
.disp32s
= 0;
5614 i
.types
[op
].bitfield
.disp32
= 0;
5615 i
.types
[op
].bitfield
.disp32s
= 1;
5618 i
.sib
.index
= i
.index_reg
->reg_num
;
5619 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5625 if (i
.base_reg
== 0)
5628 if (!i
.disp_operands
)
5630 fake_zero_displacement
= 1;
5631 /* Instructions with VSIB byte need 32bit displacement
5632 if there is no base register. */
5633 if (i
.tm
.opcode_modifier
.vecsib
)
5634 i
.types
[op
].bitfield
.disp32
= 1;
5636 if (i
.index_reg
== 0)
5638 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5639 /* Operand is just <disp> */
5640 if (flag_code
== CODE_64BIT
)
5642 /* 64bit mode overwrites the 32bit absolute
5643 addressing by RIP relative addressing and
5644 absolute addressing is encoded by one of the
5645 redundant SIB forms. */
5646 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5647 i
.sib
.base
= NO_BASE_REGISTER
;
5648 i
.sib
.index
= NO_INDEX_REGISTER
;
5649 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5650 ? disp32s
: disp32
);
5652 else if ((flag_code
== CODE_16BIT
)
5653 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5655 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5656 i
.types
[op
] = disp16
;
5660 i
.rm
.regmem
= NO_BASE_REGISTER
;
5661 i
.types
[op
] = disp32
;
5664 else if (!i
.tm
.opcode_modifier
.vecsib
)
5666 /* !i.base_reg && i.index_reg */
5667 if (i
.index_reg
->reg_num
== RegEiz
5668 || i
.index_reg
->reg_num
== RegRiz
)
5669 i
.sib
.index
= NO_INDEX_REGISTER
;
5671 i
.sib
.index
= i
.index_reg
->reg_num
;
5672 i
.sib
.base
= NO_BASE_REGISTER
;
5673 i
.sib
.scale
= i
.log2_scale_factor
;
5674 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5675 i
.types
[op
].bitfield
.disp8
= 0;
5676 i
.types
[op
].bitfield
.disp16
= 0;
5677 i
.types
[op
].bitfield
.disp64
= 0;
5678 if (flag_code
!= CODE_64BIT
)
5680 /* Must be 32 bit */
5681 i
.types
[op
].bitfield
.disp32
= 1;
5682 i
.types
[op
].bitfield
.disp32s
= 0;
5686 i
.types
[op
].bitfield
.disp32
= 0;
5687 i
.types
[op
].bitfield
.disp32s
= 1;
5689 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5693 /* RIP addressing for 64bit mode. */
5694 else if (i
.base_reg
->reg_num
== RegRip
||
5695 i
.base_reg
->reg_num
== RegEip
)
5697 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5698 i
.rm
.regmem
= NO_BASE_REGISTER
;
5699 i
.types
[op
].bitfield
.disp8
= 0;
5700 i
.types
[op
].bitfield
.disp16
= 0;
5701 i
.types
[op
].bitfield
.disp32
= 0;
5702 i
.types
[op
].bitfield
.disp32s
= 1;
5703 i
.types
[op
].bitfield
.disp64
= 0;
5704 i
.flags
[op
] |= Operand_PCrel
;
5705 if (! i
.disp_operands
)
5706 fake_zero_displacement
= 1;
5708 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5710 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5711 switch (i
.base_reg
->reg_num
)
5714 if (i
.index_reg
== 0)
5716 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5717 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5721 if (i
.index_reg
== 0)
5724 if (operand_type_check (i
.types
[op
], disp
) == 0)
5726 /* fake (%bp) into 0(%bp) */
5727 i
.types
[op
].bitfield
.disp8
= 1;
5728 fake_zero_displacement
= 1;
5731 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5732 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5734 default: /* (%si) -> 4 or (%di) -> 5 */
5735 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5737 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5739 else /* i.base_reg and 32/64 bit mode */
5741 if (flag_code
== CODE_64BIT
5742 && operand_type_check (i
.types
[op
], disp
))
5744 i386_operand_type temp
;
5745 operand_type_set (&temp
, 0);
5746 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5748 if (i
.prefix
[ADDR_PREFIX
] == 0)
5749 i
.types
[op
].bitfield
.disp32s
= 1;
5751 i
.types
[op
].bitfield
.disp32
= 1;
5754 if (!i
.tm
.opcode_modifier
.vecsib
)
5755 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5756 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5758 i
.sib
.base
= i
.base_reg
->reg_num
;
5759 /* x86-64 ignores REX prefix bit here to avoid decoder
5761 if (!(i
.base_reg
->reg_flags
& RegRex
)
5762 && (i
.base_reg
->reg_num
== EBP_REG_NUM
5763 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
5765 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
5767 fake_zero_displacement
= 1;
5768 i
.types
[op
].bitfield
.disp8
= 1;
5770 i
.sib
.scale
= i
.log2_scale_factor
;
5771 if (i
.index_reg
== 0)
5773 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
5774 /* <disp>(%esp) becomes two byte modrm with no index
5775 register. We've already stored the code for esp
5776 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5777 Any base register besides %esp will not use the
5778 extra modrm byte. */
5779 i
.sib
.index
= NO_INDEX_REGISTER
;
5781 else if (!i
.tm
.opcode_modifier
.vecsib
)
5783 if (i
.index_reg
->reg_num
== RegEiz
5784 || i
.index_reg
->reg_num
== RegRiz
)
5785 i
.sib
.index
= NO_INDEX_REGISTER
;
5787 i
.sib
.index
= i
.index_reg
->reg_num
;
5788 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5789 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5794 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5795 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5799 if (!fake_zero_displacement
5803 fake_zero_displacement
= 1;
5804 if (i
.disp_encoding
== disp_encoding_8bit
)
5805 i
.types
[op
].bitfield
.disp8
= 1;
5807 i
.types
[op
].bitfield
.disp32
= 1;
5809 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5813 if (fake_zero_displacement
)
5815 /* Fakes a zero displacement assuming that i.types[op]
5816 holds the correct displacement size. */
5819 gas_assert (i
.op
[op
].disps
== 0);
5820 exp
= &disp_expressions
[i
.disp_operands
++];
5821 i
.op
[op
].disps
= exp
;
5822 exp
->X_op
= O_constant
;
5823 exp
->X_add_number
= 0;
5824 exp
->X_add_symbol
= (symbolS
*) 0;
5825 exp
->X_op_symbol
= (symbolS
*) 0;
5833 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
5835 if (operand_type_check (i
.types
[0], imm
))
5836 i
.vex
.register_specifier
= NULL
;
5839 /* VEX.vvvv encodes one of the sources when the first
5840 operand is not an immediate. */
5841 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5842 i
.vex
.register_specifier
= i
.op
[0].regs
;
5844 i
.vex
.register_specifier
= i
.op
[1].regs
;
5847 /* Destination is a XMM register encoded in the ModRM.reg
5849 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
5850 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
5853 /* ModRM.rm and VEX.B encodes the other source. */
5854 if (!i
.mem_operands
)
5858 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5859 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5861 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
5863 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5867 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
5869 i
.vex
.register_specifier
= i
.op
[2].regs
;
5870 if (!i
.mem_operands
)
5873 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5874 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5878 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5879 (if any) based on i.tm.extension_opcode. Again, we must be
5880 careful to make sure that segment/control/debug/test/MMX
5881 registers are coded into the i.rm.reg field. */
5882 else if (i
.reg_operands
)
5885 unsigned int vex_reg
= ~0;
5887 for (op
= 0; op
< i
.operands
; op
++)
5888 if (i
.types
[op
].bitfield
.reg8
5889 || i
.types
[op
].bitfield
.reg16
5890 || i
.types
[op
].bitfield
.reg32
5891 || i
.types
[op
].bitfield
.reg64
5892 || i
.types
[op
].bitfield
.regmmx
5893 || i
.types
[op
].bitfield
.regxmm
5894 || i
.types
[op
].bitfield
.regymm
5895 || i
.types
[op
].bitfield
.sreg2
5896 || i
.types
[op
].bitfield
.sreg3
5897 || i
.types
[op
].bitfield
.control
5898 || i
.types
[op
].bitfield
.debug
5899 || i
.types
[op
].bitfield
.test
)
5904 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5906 /* For instructions with VexNDS, the register-only
5907 source operand is encoded in VEX prefix. */
5908 gas_assert (mem
!= (unsigned int) ~0);
5913 gas_assert (op
< i
.operands
);
5917 /* Check register-only source operand when two source
5918 operands are swapped. */
5919 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
5920 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
5924 gas_assert (mem
== (vex_reg
+ 1)
5925 && op
< i
.operands
);
5930 gas_assert (vex_reg
< i
.operands
);
5934 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
5936 /* For instructions with VexNDD, the register destination
5937 is encoded in VEX prefix. */
5938 if (i
.mem_operands
== 0)
5940 /* There is no memory operand. */
5941 gas_assert ((op
+ 2) == i
.operands
);
5946 /* There are only 2 operands. */
5947 gas_assert (op
< 2 && i
.operands
== 2);
5952 gas_assert (op
< i
.operands
);
5954 if (vex_reg
!= (unsigned int) ~0)
5956 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
5958 if (type
->bitfield
.reg32
!= 1
5959 && type
->bitfield
.reg64
!= 1
5960 && !operand_type_equal (type
, ®xmm
)
5961 && !operand_type_equal (type
, ®ymm
))
5964 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5967 /* Don't set OP operand twice. */
5970 /* If there is an extension opcode to put here, the
5971 register number must be put into the regmem field. */
5972 if (i
.tm
.extension_opcode
!= None
)
5974 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5975 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5980 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5981 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5986 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5987 must set it to 3 to indicate this is a register operand
5988 in the regmem field. */
5989 if (!i
.mem_operands
)
5993 /* Fill in i.rm.reg field with extension opcode (if any). */
5994 if (i
.tm
.extension_opcode
!= None
)
5995 i
.rm
.reg
= i
.tm
.extension_opcode
;
6001 output_branch (void)
6007 relax_substateT subtype
;
6011 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6012 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6015 if (i
.prefix
[DATA_PREFIX
] != 0)
6021 /* Pentium4 branch hints. */
6022 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6023 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6028 if (i
.prefix
[REX_PREFIX
] != 0)
6034 if (i
.prefixes
!= 0 && !intel_syntax
)
6035 as_warn (_("skipping prefixes on this instruction"));
6037 /* It's always a symbol; End frag & setup for relax.
6038 Make sure there is enough room in this frag for the largest
6039 instruction we may generate in md_convert_frag. This is 2
6040 bytes for the opcode and room for the prefix and largest
6042 frag_grow (prefix
+ 2 + 4);
6043 /* Prefix and 1 opcode byte go in fr_fix. */
6044 p
= frag_more (prefix
+ 1);
6045 if (i
.prefix
[DATA_PREFIX
] != 0)
6046 *p
++ = DATA_PREFIX_OPCODE
;
6047 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6048 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6049 *p
++ = i
.prefix
[SEG_PREFIX
];
6050 if (i
.prefix
[REX_PREFIX
] != 0)
6051 *p
++ = i
.prefix
[REX_PREFIX
];
6052 *p
= i
.tm
.base_opcode
;
6054 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6055 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6056 else if (cpu_arch_flags
.bitfield
.cpui386
)
6057 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6059 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6062 sym
= i
.op
[0].disps
->X_add_symbol
;
6063 off
= i
.op
[0].disps
->X_add_number
;
6065 if (i
.op
[0].disps
->X_op
!= O_constant
6066 && i
.op
[0].disps
->X_op
!= O_symbol
)
6068 /* Handle complex expressions. */
6069 sym
= make_expr_symbol (i
.op
[0].disps
);
6073 /* 1 possible extra opcode + 4 byte displacement go in var part.
6074 Pass reloc in fr_var. */
6075 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6085 if (i
.tm
.opcode_modifier
.jumpbyte
)
6087 /* This is a loop or jecxz type instruction. */
6089 if (i
.prefix
[ADDR_PREFIX
] != 0)
6091 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6094 /* Pentium4 branch hints. */
6095 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6096 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6098 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6107 if (flag_code
== CODE_16BIT
)
6110 if (i
.prefix
[DATA_PREFIX
] != 0)
6112 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6122 if (i
.prefix
[REX_PREFIX
] != 0)
6124 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6128 if (i
.prefixes
!= 0 && !intel_syntax
)
6129 as_warn (_("skipping prefixes on this instruction"));
6131 p
= frag_more (i
.tm
.opcode_length
+ size
);
6132 switch (i
.tm
.opcode_length
)
6135 *p
++ = i
.tm
.base_opcode
>> 8;
6137 *p
++ = i
.tm
.base_opcode
;
6143 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6144 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6146 /* All jumps handled here are signed, but don't use a signed limit
6147 check for 32 and 16 bit jumps as we want to allow wrap around at
6148 4G and 64k respectively. */
6150 fixP
->fx_signed
= 1;
6154 output_interseg_jump (void)
6162 if (flag_code
== CODE_16BIT
)
6166 if (i
.prefix
[DATA_PREFIX
] != 0)
6172 if (i
.prefix
[REX_PREFIX
] != 0)
6182 if (i
.prefixes
!= 0 && !intel_syntax
)
6183 as_warn (_("skipping prefixes on this instruction"));
6185 /* 1 opcode; 2 segment; offset */
6186 p
= frag_more (prefix
+ 1 + 2 + size
);
6188 if (i
.prefix
[DATA_PREFIX
] != 0)
6189 *p
++ = DATA_PREFIX_OPCODE
;
6191 if (i
.prefix
[REX_PREFIX
] != 0)
6192 *p
++ = i
.prefix
[REX_PREFIX
];
6194 *p
++ = i
.tm
.base_opcode
;
6195 if (i
.op
[1].imms
->X_op
== O_constant
)
6197 offsetT n
= i
.op
[1].imms
->X_add_number
;
6200 && !fits_in_unsigned_word (n
)
6201 && !fits_in_signed_word (n
))
6203 as_bad (_("16-bit jump out of range"));
6206 md_number_to_chars (p
, n
, size
);
6209 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6210 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6211 if (i
.op
[0].imms
->X_op
!= O_constant
)
6212 as_bad (_("can't handle non absolute segment in `%s'"),
6214 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6220 fragS
*insn_start_frag
;
6221 offsetT insn_start_off
;
6223 /* Tie dwarf2 debug info to the address at the start of the insn.
6224 We can't do this after the insn has been output as the current
6225 frag may have been closed off. eg. by frag_var. */
6226 dwarf2_emit_insn (0);
6228 insn_start_frag
= frag_now
;
6229 insn_start_off
= frag_now_fix ();
6232 if (i
.tm
.opcode_modifier
.jump
)
6234 else if (i
.tm
.opcode_modifier
.jumpbyte
6235 || i
.tm
.opcode_modifier
.jumpdword
)
6237 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6238 output_interseg_jump ();
6241 /* Output normal instructions here. */
6245 unsigned int prefix
;
6247 /* Since the VEX prefix contains the implicit prefix, we don't
6248 need the explicit prefix. */
6249 if (!i
.tm
.opcode_modifier
.vex
)
6251 switch (i
.tm
.opcode_length
)
6254 if (i
.tm
.base_opcode
& 0xff000000)
6256 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6261 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6263 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6264 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6267 if (prefix
!= REPE_PREFIX_OPCODE
6268 || (i
.prefix
[REP_PREFIX
]
6269 != REPE_PREFIX_OPCODE
))
6270 add_prefix (prefix
);
6273 add_prefix (prefix
);
6282 /* The prefix bytes. */
6283 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6285 FRAG_APPEND_1_CHAR (*q
);
6289 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
6294 /* REX byte is encoded in VEX prefix. */
6298 FRAG_APPEND_1_CHAR (*q
);
6301 /* There should be no other prefixes for instructions
6306 /* Now the VEX prefix. */
6307 p
= frag_more (i
.vex
.length
);
6308 for (j
= 0; j
< i
.vex
.length
; j
++)
6309 p
[j
] = i
.vex
.bytes
[j
];
6312 /* Now the opcode; be careful about word order here! */
6313 if (i
.tm
.opcode_length
== 1)
6315 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
6319 switch (i
.tm
.opcode_length
)
6323 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
6333 /* Put out high byte first: can't use md_number_to_chars! */
6334 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
6335 *p
= i
.tm
.base_opcode
& 0xff;
6338 /* Now the modrm byte and sib byte (if present). */
6339 if (i
.tm
.opcode_modifier
.modrm
)
6341 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
6344 /* If i.rm.regmem == ESP (4)
6345 && i.rm.mode != (Register mode)
6347 ==> need second modrm byte. */
6348 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
6350 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
6351 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
6353 | i
.sib
.scale
<< 6));
6356 if (i
.disp_operands
)
6357 output_disp (insn_start_frag
, insn_start_off
);
6360 output_imm (insn_start_frag
, insn_start_off
);
6366 pi ("" /*line*/, &i
);
6368 #endif /* DEBUG386 */
6371 /* Return the size of the displacement operand N. */
6374 disp_size (unsigned int n
)
6377 if (i
.types
[n
].bitfield
.disp64
)
6379 else if (i
.types
[n
].bitfield
.disp8
)
6381 else if (i
.types
[n
].bitfield
.disp16
)
6386 /* Return the size of the immediate operand N. */
6389 imm_size (unsigned int n
)
6392 if (i
.types
[n
].bitfield
.imm64
)
6394 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6396 else if (i
.types
[n
].bitfield
.imm16
)
6402 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6407 for (n
= 0; n
< i
.operands
; n
++)
6409 if (operand_type_check (i
.types
[n
], disp
))
6411 if (i
.op
[n
].disps
->X_op
== O_constant
)
6413 int size
= disp_size (n
);
6416 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6418 p
= frag_more (size
);
6419 md_number_to_chars (p
, val
, size
);
6423 enum bfd_reloc_code_real reloc_type
;
6424 int size
= disp_size (n
);
6425 int sign
= i
.types
[n
].bitfield
.disp32s
;
6426 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6428 /* We can't have 8 bit displacement here. */
6429 gas_assert (!i
.types
[n
].bitfield
.disp8
);
6431 /* The PC relative address is computed relative
6432 to the instruction boundary, so in case immediate
6433 fields follows, we need to adjust the value. */
6434 if (pcrel
&& i
.imm_operands
)
6439 for (n1
= 0; n1
< i
.operands
; n1
++)
6440 if (operand_type_check (i
.types
[n1
], imm
))
6442 /* Only one immediate is allowed for PC
6443 relative address. */
6444 gas_assert (sz
== 0);
6446 i
.op
[n
].disps
->X_add_number
-= sz
;
6448 /* We should find the immediate. */
6449 gas_assert (sz
!= 0);
6452 p
= frag_more (size
);
6453 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6455 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6456 && (((reloc_type
== BFD_RELOC_32
6457 || reloc_type
== BFD_RELOC_X86_64_32S
6458 || (reloc_type
== BFD_RELOC_64
6460 && (i
.op
[n
].disps
->X_op
== O_symbol
6461 || (i
.op
[n
].disps
->X_op
== O_add
6462 && ((symbol_get_value_expression
6463 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6465 || reloc_type
== BFD_RELOC_32_PCREL
))
6469 if (insn_start_frag
== frag_now
)
6470 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6475 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6476 for (fr
= insn_start_frag
->fr_next
;
6477 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6479 add
+= p
- frag_now
->fr_literal
;
6484 reloc_type
= BFD_RELOC_386_GOTPC
;
6485 i
.op
[n
].imms
->X_add_number
+= add
;
6487 else if (reloc_type
== BFD_RELOC_64
)
6488 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6490 /* Don't do the adjustment for x86-64, as there
6491 the pcrel addressing is relative to the _next_
6492 insn, and that is taken care of in other code. */
6493 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6495 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6496 i
.op
[n
].disps
, pcrel
, reloc_type
);
6503 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6508 for (n
= 0; n
< i
.operands
; n
++)
6510 if (operand_type_check (i
.types
[n
], imm
))
6512 if (i
.op
[n
].imms
->X_op
== O_constant
)
6514 int size
= imm_size (n
);
6517 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6519 p
= frag_more (size
);
6520 md_number_to_chars (p
, val
, size
);
6524 /* Not absolute_section.
6525 Need a 32-bit fixup (don't support 8bit
6526 non-absolute imms). Try to support other
6528 enum bfd_reloc_code_real reloc_type
;
6529 int size
= imm_size (n
);
6532 if (i
.types
[n
].bitfield
.imm32s
6533 && (i
.suffix
== QWORD_MNEM_SUFFIX
6534 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6539 p
= frag_more (size
);
6540 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6542 /* This is tough to explain. We end up with this one if we
6543 * have operands that look like
6544 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6545 * obtain the absolute address of the GOT, and it is strongly
6546 * preferable from a performance point of view to avoid using
6547 * a runtime relocation for this. The actual sequence of
6548 * instructions often look something like:
6553 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6555 * The call and pop essentially return the absolute address
6556 * of the label .L66 and store it in %ebx. The linker itself
6557 * will ultimately change the first operand of the addl so
6558 * that %ebx points to the GOT, but to keep things simple, the
6559 * .o file must have this operand set so that it generates not
6560 * the absolute address of .L66, but the absolute address of
6561 * itself. This allows the linker itself simply treat a GOTPC
6562 * relocation as asking for a pcrel offset to the GOT to be
6563 * added in, and the addend of the relocation is stored in the
6564 * operand field for the instruction itself.
6566 * Our job here is to fix the operand so that it would add
6567 * the correct offset so that %ebx would point to itself. The
6568 * thing that is tricky is that .-.L66 will point to the
6569 * beginning of the instruction, so we need to further modify
6570 * the operand so that it will point to itself. There are
6571 * other cases where you have something like:
6573 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6575 * and here no correction would be required. Internally in
6576 * the assembler we treat operands of this form as not being
6577 * pcrel since the '.' is explicitly mentioned, and I wonder
6578 * whether it would simplify matters to do it this way. Who
6579 * knows. In earlier versions of the PIC patches, the
6580 * pcrel_adjust field was used to store the correction, but
6581 * since the expression is not pcrel, I felt it would be
6582 * confusing to do it this way. */
6584 if ((reloc_type
== BFD_RELOC_32
6585 || reloc_type
== BFD_RELOC_X86_64_32S
6586 || reloc_type
== BFD_RELOC_64
)
6588 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6589 && (i
.op
[n
].imms
->X_op
== O_symbol
6590 || (i
.op
[n
].imms
->X_op
== O_add
6591 && ((symbol_get_value_expression
6592 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6597 if (insn_start_frag
== frag_now
)
6598 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6603 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6604 for (fr
= insn_start_frag
->fr_next
;
6605 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6607 add
+= p
- frag_now
->fr_literal
;
6611 reloc_type
= BFD_RELOC_386_GOTPC
;
6613 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6615 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6616 i
.op
[n
].imms
->X_add_number
+= add
;
6618 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6619 i
.op
[n
].imms
, 0, reloc_type
);
6625 /* x86_cons_fix_new is called via the expression parsing code when a
6626 reloc is needed. We use this hook to get the correct .got reloc. */
6627 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6628 static int cons_sign
= -1;
6631 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6634 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6636 got_reloc
= NO_RELOC
;
6639 if (exp
->X_op
== O_secrel
)
6641 exp
->X_op
= O_symbol
;
6642 r
= BFD_RELOC_32_SECREL
;
6646 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6649 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
6650 purpose of the `.dc.a' internal pseudo-op. */
6653 x86_address_bytes (void)
6655 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
6657 return stdoutput
->arch_info
->bits_per_address
/ 8;
6660 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
6662 # define lex_got(reloc, adjust, types) NULL
6664 /* Parse operands of the form
6665 <symbol>@GOTOFF+<nnn>
6666 and similar .plt or .got references.
6668 If we find one, set up the correct relocation in RELOC and copy the
6669 input string, minus the `@GOTOFF' into a malloc'd buffer for
6670 parsing by the calling routine. Return this buffer, and if ADJUST
6671 is non-null set it to the length of the string we removed from the
6672 input line. Otherwise return NULL. */
6674 lex_got (enum bfd_reloc_code_real
*rel
,
6676 i386_operand_type
*types
)
6678 /* Some of the relocations depend on the size of what field is to
6679 be relocated. But in our callers i386_immediate and i386_displacement
6680 we don't yet know the operand size (this will be set by insn
6681 matching). Hence we record the word32 relocation here,
6682 and adjust the reloc according to the real size in reloc(). */
6683 static const struct {
6686 const enum bfd_reloc_code_real rel
[2];
6687 const i386_operand_type types64
;
6689 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6690 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
6692 OPERAND_TYPE_IMM32_64
},
6694 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
6695 BFD_RELOC_X86_64_PLTOFF64
},
6696 OPERAND_TYPE_IMM64
},
6697 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
6698 BFD_RELOC_X86_64_PLT32
},
6699 OPERAND_TYPE_IMM32_32S_DISP32
},
6700 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
6701 BFD_RELOC_X86_64_GOTPLT64
},
6702 OPERAND_TYPE_IMM64_DISP64
},
6703 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
6704 BFD_RELOC_X86_64_GOTOFF64
},
6705 OPERAND_TYPE_IMM64_DISP64
},
6706 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
6707 BFD_RELOC_X86_64_GOTPCREL
},
6708 OPERAND_TYPE_IMM32_32S_DISP32
},
6709 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
6710 BFD_RELOC_X86_64_TLSGD
},
6711 OPERAND_TYPE_IMM32_32S_DISP32
},
6712 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
6713 _dummy_first_bfd_reloc_code_real
},
6714 OPERAND_TYPE_NONE
},
6715 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
6716 BFD_RELOC_X86_64_TLSLD
},
6717 OPERAND_TYPE_IMM32_32S_DISP32
},
6718 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
6719 BFD_RELOC_X86_64_GOTTPOFF
},
6720 OPERAND_TYPE_IMM32_32S_DISP32
},
6721 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
6722 BFD_RELOC_X86_64_TPOFF32
},
6723 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6724 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
6725 _dummy_first_bfd_reloc_code_real
},
6726 OPERAND_TYPE_NONE
},
6727 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
6728 BFD_RELOC_X86_64_DTPOFF32
},
6729 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6730 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
6731 _dummy_first_bfd_reloc_code_real
},
6732 OPERAND_TYPE_NONE
},
6733 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
6734 _dummy_first_bfd_reloc_code_real
},
6735 OPERAND_TYPE_NONE
},
6736 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
6737 BFD_RELOC_X86_64_GOT32
},
6738 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6739 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
6740 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6741 OPERAND_TYPE_IMM32_32S_DISP32
},
6742 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
6743 BFD_RELOC_X86_64_TLSDESC_CALL
},
6744 OPERAND_TYPE_IMM32_32S_DISP32
},
6749 #if defined (OBJ_MAYBE_ELF)
6754 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6755 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6758 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6760 int len
= gotrel
[j
].len
;
6761 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6763 if (gotrel
[j
].rel
[object_64bit
] != 0)
6766 char *tmpbuf
, *past_reloc
;
6768 *rel
= gotrel
[j
].rel
[object_64bit
];
6772 if (flag_code
!= CODE_64BIT
)
6774 types
->bitfield
.imm32
= 1;
6775 types
->bitfield
.disp32
= 1;
6778 *types
= gotrel
[j
].types64
;
6781 if (j
!= 0 && GOT_symbol
== NULL
)
6782 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6784 /* The length of the first part of our input line. */
6785 first
= cp
- input_line_pointer
;
6787 /* The second part goes from after the reloc token until
6788 (and including) an end_of_line char or comma. */
6789 past_reloc
= cp
+ 1 + len
;
6791 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6793 second
= cp
+ 1 - past_reloc
;
6795 /* Allocate and copy string. The trailing NUL shouldn't
6796 be necessary, but be safe. */
6797 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6798 memcpy (tmpbuf
, input_line_pointer
, first
);
6799 if (second
!= 0 && *past_reloc
!= ' ')
6800 /* Replace the relocation token with ' ', so that
6801 errors like foo@GOTOFF1 will be detected. */
6802 tmpbuf
[first
++] = ' ';
6804 /* Increment length by 1 if the relocation token is
6809 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6810 tmpbuf
[first
+ second
] = '\0';
6814 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6815 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6820 /* Might be a symbol version string. Don't as_bad here. */
6829 /* Parse operands of the form
6830 <symbol>@SECREL32+<nnn>
6832 If we find one, set up the correct relocation in RELOC and copy the
6833 input string, minus the `@SECREL32' into a malloc'd buffer for
6834 parsing by the calling routine. Return this buffer, and if ADJUST
6835 is non-null set it to the length of the string we removed from the
6836 input line. Otherwise return NULL.
6838 This function is copied from the ELF version above adjusted for PE targets. */
6841 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
6842 int *adjust ATTRIBUTE_UNUSED
,
6843 i386_operand_type
*types ATTRIBUTE_UNUSED
)
6849 const enum bfd_reloc_code_real rel
[2];
6850 const i386_operand_type types64
;
6854 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
6855 BFD_RELOC_32_SECREL
},
6856 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6862 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6863 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6866 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6868 int len
= gotrel
[j
].len
;
6870 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6872 if (gotrel
[j
].rel
[object_64bit
] != 0)
6875 char *tmpbuf
, *past_reloc
;
6877 *rel
= gotrel
[j
].rel
[object_64bit
];
6883 if (flag_code
!= CODE_64BIT
)
6885 types
->bitfield
.imm32
= 1;
6886 types
->bitfield
.disp32
= 1;
6889 *types
= gotrel
[j
].types64
;
6892 /* The length of the first part of our input line. */
6893 first
= cp
- input_line_pointer
;
6895 /* The second part goes from after the reloc token until
6896 (and including) an end_of_line char or comma. */
6897 past_reloc
= cp
+ 1 + len
;
6899 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6901 second
= cp
+ 1 - past_reloc
;
6903 /* Allocate and copy string. The trailing NUL shouldn't
6904 be necessary, but be safe. */
6905 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6906 memcpy (tmpbuf
, input_line_pointer
, first
);
6907 if (second
!= 0 && *past_reloc
!= ' ')
6908 /* Replace the relocation token with ' ', so that
6909 errors like foo@SECLREL321 will be detected. */
6910 tmpbuf
[first
++] = ' ';
6911 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6912 tmpbuf
[first
+ second
] = '\0';
6916 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6917 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6922 /* Might be a symbol version string. Don't as_bad here. */
6929 x86_cons (expressionS
*exp
, int size
)
6931 intel_syntax
= -intel_syntax
;
6934 if (size
== 4 || (object_64bit
&& size
== 8))
6936 /* Handle @GOTOFF and the like in an expression. */
6938 char *gotfree_input_line
;
6941 save
= input_line_pointer
;
6942 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6943 if (gotfree_input_line
)
6944 input_line_pointer
= gotfree_input_line
;
6948 if (gotfree_input_line
)
6950 /* expression () has merrily parsed up to the end of line,
6951 or a comma - in the wrong buffer. Transfer how far
6952 input_line_pointer has moved to the right buffer. */
6953 input_line_pointer
= (save
6954 + (input_line_pointer
- gotfree_input_line
)
6956 free (gotfree_input_line
);
6957 if (exp
->X_op
== O_constant
6958 || exp
->X_op
== O_absent
6959 || exp
->X_op
== O_illegal
6960 || exp
->X_op
== O_register
6961 || exp
->X_op
== O_big
)
6963 char c
= *input_line_pointer
;
6964 *input_line_pointer
= 0;
6965 as_bad (_("missing or invalid expression `%s'"), save
);
6966 *input_line_pointer
= c
;
6973 intel_syntax
= -intel_syntax
;
6976 i386_intel_simplify (exp
);
6980 signed_cons (int size
)
6982 if (flag_code
== CODE_64BIT
)
6990 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
6997 if (exp
.X_op
== O_symbol
)
6998 exp
.X_op
= O_secrel
;
7000 emit_expr (&exp
, 4);
7002 while (*input_line_pointer
++ == ',');
7004 input_line_pointer
--;
7005 demand_empty_rest_of_line ();
7010 i386_immediate (char *imm_start
)
7012 char *save_input_line_pointer
;
7013 char *gotfree_input_line
;
7016 i386_operand_type types
;
7018 operand_type_set (&types
, ~0);
7020 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7022 as_bad (_("at most %d immediate operands are allowed"),
7023 MAX_IMMEDIATE_OPERANDS
);
7027 exp
= &im_expressions
[i
.imm_operands
++];
7028 i
.op
[this_operand
].imms
= exp
;
7030 if (is_space_char (*imm_start
))
7033 save_input_line_pointer
= input_line_pointer
;
7034 input_line_pointer
= imm_start
;
7036 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7037 if (gotfree_input_line
)
7038 input_line_pointer
= gotfree_input_line
;
7040 exp_seg
= expression (exp
);
7043 if (*input_line_pointer
)
7044 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7046 input_line_pointer
= save_input_line_pointer
;
7047 if (gotfree_input_line
)
7049 free (gotfree_input_line
);
7051 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7052 exp
->X_op
= O_illegal
;
7055 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7059 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7060 i386_operand_type types
, const char *imm_start
)
7062 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7065 as_bad (_("missing or invalid immediate expression `%s'"),
7069 else if (exp
->X_op
== O_constant
)
7071 /* Size it properly later. */
7072 i
.types
[this_operand
].bitfield
.imm64
= 1;
7073 /* If not 64bit, sign extend val. */
7074 if (flag_code
!= CODE_64BIT
7075 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7077 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7079 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7080 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7081 && exp_seg
!= absolute_section
7082 && exp_seg
!= text_section
7083 && exp_seg
!= data_section
7084 && exp_seg
!= bss_section
7085 && exp_seg
!= undefined_section
7086 && !bfd_is_com_section (exp_seg
))
7088 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7092 else if (!intel_syntax
&& exp
->X_op
== O_register
)
7095 as_bad (_("illegal immediate register operand %s"), imm_start
);
7100 /* This is an address. The size of the address will be
7101 determined later, depending on destination register,
7102 suffix, or the default for the section. */
7103 i
.types
[this_operand
].bitfield
.imm8
= 1;
7104 i
.types
[this_operand
].bitfield
.imm16
= 1;
7105 i
.types
[this_operand
].bitfield
.imm32
= 1;
7106 i
.types
[this_operand
].bitfield
.imm32s
= 1;
7107 i
.types
[this_operand
].bitfield
.imm64
= 1;
7108 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7116 i386_scale (char *scale
)
7119 char *save
= input_line_pointer
;
7121 input_line_pointer
= scale
;
7122 val
= get_absolute_expression ();
7127 i
.log2_scale_factor
= 0;
7130 i
.log2_scale_factor
= 1;
7133 i
.log2_scale_factor
= 2;
7136 i
.log2_scale_factor
= 3;
7140 char sep
= *input_line_pointer
;
7142 *input_line_pointer
= '\0';
7143 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7145 *input_line_pointer
= sep
;
7146 input_line_pointer
= save
;
7150 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
7152 as_warn (_("scale factor of %d without an index register"),
7153 1 << i
.log2_scale_factor
);
7154 i
.log2_scale_factor
= 0;
7156 scale
= input_line_pointer
;
7157 input_line_pointer
= save
;
7162 i386_displacement (char *disp_start
, char *disp_end
)
7166 char *save_input_line_pointer
;
7167 char *gotfree_input_line
;
7169 i386_operand_type bigdisp
, types
= anydisp
;
7172 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
7174 as_bad (_("at most %d displacement operands are allowed"),
7175 MAX_MEMORY_OPERANDS
);
7179 operand_type_set (&bigdisp
, 0);
7180 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
7181 || (!current_templates
->start
->opcode_modifier
.jump
7182 && !current_templates
->start
->opcode_modifier
.jumpdword
))
7184 bigdisp
.bitfield
.disp32
= 1;
7185 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
7186 if (flag_code
== CODE_64BIT
)
7190 bigdisp
.bitfield
.disp32s
= 1;
7191 bigdisp
.bitfield
.disp64
= 1;
7194 else if ((flag_code
== CODE_16BIT
) ^ override
)
7196 bigdisp
.bitfield
.disp32
= 0;
7197 bigdisp
.bitfield
.disp16
= 1;
7202 /* For PC-relative branches, the width of the displacement
7203 is dependent upon data size, not address size. */
7204 override
= (i
.prefix
[DATA_PREFIX
] != 0);
7205 if (flag_code
== CODE_64BIT
)
7207 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
7208 bigdisp
.bitfield
.disp16
= 1;
7211 bigdisp
.bitfield
.disp32
= 1;
7212 bigdisp
.bitfield
.disp32s
= 1;
7218 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
7220 : LONG_MNEM_SUFFIX
));
7221 bigdisp
.bitfield
.disp32
= 1;
7222 if ((flag_code
== CODE_16BIT
) ^ override
)
7224 bigdisp
.bitfield
.disp32
= 0;
7225 bigdisp
.bitfield
.disp16
= 1;
7229 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7232 exp
= &disp_expressions
[i
.disp_operands
];
7233 i
.op
[this_operand
].disps
= exp
;
7235 save_input_line_pointer
= input_line_pointer
;
7236 input_line_pointer
= disp_start
;
7237 END_STRING_AND_SAVE (disp_end
);
7239 #ifndef GCC_ASM_O_HACK
7240 #define GCC_ASM_O_HACK 0
7243 END_STRING_AND_SAVE (disp_end
+ 1);
7244 if (i
.types
[this_operand
].bitfield
.baseIndex
7245 && displacement_string_end
[-1] == '+')
7247 /* This hack is to avoid a warning when using the "o"
7248 constraint within gcc asm statements.
7251 #define _set_tssldt_desc(n,addr,limit,type) \
7252 __asm__ __volatile__ ( \
7254 "movw %w1,2+%0\n\t" \
7256 "movb %b1,4+%0\n\t" \
7257 "movb %4,5+%0\n\t" \
7258 "movb $0,6+%0\n\t" \
7259 "movb %h1,7+%0\n\t" \
7261 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
7263 This works great except that the output assembler ends
7264 up looking a bit weird if it turns out that there is
7265 no offset. You end up producing code that looks like:
7278 So here we provide the missing zero. */
7280 *displacement_string_end
= '0';
7283 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7284 if (gotfree_input_line
)
7285 input_line_pointer
= gotfree_input_line
;
7287 exp_seg
= expression (exp
);
7290 if (*input_line_pointer
)
7291 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7293 RESTORE_END_STRING (disp_end
+ 1);
7295 input_line_pointer
= save_input_line_pointer
;
7296 if (gotfree_input_line
)
7298 free (gotfree_input_line
);
7300 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7301 exp
->X_op
= O_illegal
;
7304 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
7306 RESTORE_END_STRING (disp_end
);
7312 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7313 i386_operand_type types
, const char *disp_start
)
7315 i386_operand_type bigdisp
;
7318 /* We do this to make sure that the section symbol is in
7319 the symbol table. We will ultimately change the relocation
7320 to be relative to the beginning of the section. */
7321 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
7322 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
7323 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
7325 if (exp
->X_op
!= O_symbol
)
7328 if (S_IS_LOCAL (exp
->X_add_symbol
)
7329 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
7330 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
7331 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
7332 exp
->X_op
= O_subtract
;
7333 exp
->X_op_symbol
= GOT_symbol
;
7334 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
7335 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
7336 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
7337 i
.reloc
[this_operand
] = BFD_RELOC_64
;
7339 i
.reloc
[this_operand
] = BFD_RELOC_32
;
7342 else if (exp
->X_op
== O_absent
7343 || exp
->X_op
== O_illegal
7344 || exp
->X_op
== O_big
)
7347 as_bad (_("missing or invalid displacement expression `%s'"),
7352 else if (flag_code
== CODE_64BIT
7353 && !i
.prefix
[ADDR_PREFIX
]
7354 && exp
->X_op
== O_constant
)
7356 /* Since displacement is signed extended to 64bit, don't allow
7357 disp32 and turn off disp32s if they are out of range. */
7358 i
.types
[this_operand
].bitfield
.disp32
= 0;
7359 if (!fits_in_signed_long (exp
->X_add_number
))
7361 i
.types
[this_operand
].bitfield
.disp32s
= 0;
7362 if (i
.types
[this_operand
].bitfield
.baseindex
)
7364 as_bad (_("0x%lx out range of signed 32bit displacement"),
7365 (long) exp
->X_add_number
);
7371 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7372 else if (exp
->X_op
!= O_constant
7373 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
7374 && exp_seg
!= absolute_section
7375 && exp_seg
!= text_section
7376 && exp_seg
!= data_section
7377 && exp_seg
!= bss_section
7378 && exp_seg
!= undefined_section
7379 && !bfd_is_com_section (exp_seg
))
7381 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7386 /* Check if this is a displacement only operand. */
7387 bigdisp
= i
.types
[this_operand
];
7388 bigdisp
.bitfield
.disp8
= 0;
7389 bigdisp
.bitfield
.disp16
= 0;
7390 bigdisp
.bitfield
.disp32
= 0;
7391 bigdisp
.bitfield
.disp32s
= 0;
7392 bigdisp
.bitfield
.disp64
= 0;
7393 if (operand_type_all_zero (&bigdisp
))
7394 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7400 /* Make sure the memory operand we've been dealt is valid.
7401 Return 1 on success, 0 on a failure. */
7404 i386_index_check (const char *operand_string
)
7406 const char *kind
= "base/index";
7407 enum flag_code addr_mode
;
7409 if (i
.prefix
[ADDR_PREFIX
])
7410 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
7413 addr_mode
= flag_code
;
7415 #if INFER_ADDR_PREFIX
7416 if (i
.mem_operands
== 0)
7418 /* Infer address prefix from the first memory operand. */
7419 const reg_entry
*addr_reg
= i
.base_reg
;
7421 if (addr_reg
== NULL
)
7422 addr_reg
= i
.index_reg
;
7426 if (addr_reg
->reg_num
== RegEip
7427 || addr_reg
->reg_num
== RegEiz
7428 || addr_reg
->reg_type
.bitfield
.reg32
)
7429 addr_mode
= CODE_32BIT
;
7430 else if (flag_code
!= CODE_64BIT
7431 && addr_reg
->reg_type
.bitfield
.reg16
)
7432 addr_mode
= CODE_16BIT
;
7434 if (addr_mode
!= flag_code
)
7436 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7438 /* Change the size of any displacement too. At most one
7439 of Disp16 or Disp32 is set.
7440 FIXME. There doesn't seem to be any real need for
7441 separate Disp16 and Disp32 flags. The same goes for
7442 Imm16 and Imm32. Removing them would probably clean
7443 up the code quite a lot. */
7444 if (flag_code
!= CODE_64BIT
7445 && (i
.types
[this_operand
].bitfield
.disp16
7446 || i
.types
[this_operand
].bitfield
.disp32
))
7447 i
.types
[this_operand
]
7448 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7455 if (current_templates
->start
->opcode_modifier
.isstring
7456 && !current_templates
->start
->opcode_modifier
.immext
7457 && (current_templates
->end
[-1].opcode_modifier
.isstring
7460 /* Memory operands of string insns are special in that they only allow
7461 a single register (rDI, rSI, or rBX) as their memory address. */
7462 const reg_entry
*expected_reg
;
7463 static const char *di_si
[][2] =
7469 static const char *bx
[] = { "ebx", "bx", "rbx" };
7471 kind
= "string address";
7473 if (current_templates
->start
->opcode_modifier
.w
)
7475 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
7477 if (!type
.bitfield
.baseindex
7478 || ((!i
.mem_operands
!= !intel_syntax
)
7479 && current_templates
->end
[-1].operand_types
[1]
7480 .bitfield
.baseindex
))
7481 type
= current_templates
->end
[-1].operand_types
[1];
7482 expected_reg
= hash_find (reg_hash
,
7483 di_si
[addr_mode
][type
.bitfield
.esseg
]);
7487 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
7489 if (i
.base_reg
!= expected_reg
7491 || operand_type_check (i
.types
[this_operand
], disp
))
7493 /* The second memory operand must have the same size as
7497 && !((addr_mode
== CODE_64BIT
7498 && i
.base_reg
->reg_type
.bitfield
.reg64
)
7499 || (addr_mode
== CODE_32BIT
7500 ? i
.base_reg
->reg_type
.bitfield
.reg32
7501 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
7504 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7506 intel_syntax
? '[' : '(',
7508 expected_reg
->reg_name
,
7509 intel_syntax
? ']' : ')');
7516 as_bad (_("`%s' is not a valid %s expression"),
7517 operand_string
, kind
);
7522 if (addr_mode
!= CODE_16BIT
)
7524 /* 32-bit/64-bit checks. */
7526 && (addr_mode
== CODE_64BIT
7527 ? !i
.base_reg
->reg_type
.bitfield
.reg64
7528 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
7530 || (i
.base_reg
->reg_num
7531 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
7533 && !i
.index_reg
->reg_type
.bitfield
.regxmm
7534 && !i
.index_reg
->reg_type
.bitfield
.regymm
7535 && ((addr_mode
== CODE_64BIT
7536 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
7537 || i
.index_reg
->reg_num
== RegRiz
)
7538 : !(i
.index_reg
->reg_type
.bitfield
.reg32
7539 || i
.index_reg
->reg_num
== RegEiz
))
7540 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7545 /* 16-bit checks. */
7547 && (!i
.base_reg
->reg_type
.bitfield
.reg16
7548 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
7550 && (!i
.index_reg
->reg_type
.bitfield
.reg16
7551 || !i
.index_reg
->reg_type
.bitfield
.baseindex
7553 && i
.base_reg
->reg_num
< 6
7554 && i
.index_reg
->reg_num
>= 6
7555 && i
.log2_scale_factor
== 0))))
7562 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7566 i386_att_operand (char *operand_string
)
7570 char *op_string
= operand_string
;
7572 if (is_space_char (*op_string
))
7575 /* We check for an absolute prefix (differentiating,
7576 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7577 if (*op_string
== ABSOLUTE_PREFIX
)
7580 if (is_space_char (*op_string
))
7582 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7585 /* Check if operand is a register. */
7586 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7588 i386_operand_type temp
;
7590 /* Check for a segment override by searching for ':' after a
7591 segment register. */
7593 if (is_space_char (*op_string
))
7595 if (*op_string
== ':'
7596 && (r
->reg_type
.bitfield
.sreg2
7597 || r
->reg_type
.bitfield
.sreg3
))
7602 i
.seg
[i
.mem_operands
] = &es
;
7605 i
.seg
[i
.mem_operands
] = &cs
;
7608 i
.seg
[i
.mem_operands
] = &ss
;
7611 i
.seg
[i
.mem_operands
] = &ds
;
7614 i
.seg
[i
.mem_operands
] = &fs
;
7617 i
.seg
[i
.mem_operands
] = &gs
;
7621 /* Skip the ':' and whitespace. */
7623 if (is_space_char (*op_string
))
7626 if (!is_digit_char (*op_string
)
7627 && !is_identifier_char (*op_string
)
7628 && *op_string
!= '('
7629 && *op_string
!= ABSOLUTE_PREFIX
)
7631 as_bad (_("bad memory operand `%s'"), op_string
);
7634 /* Handle case of %es:*foo. */
7635 if (*op_string
== ABSOLUTE_PREFIX
)
7638 if (is_space_char (*op_string
))
7640 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7642 goto do_memory_reference
;
7646 as_bad (_("junk `%s' after register"), op_string
);
7650 temp
.bitfield
.baseindex
= 0;
7651 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7653 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7654 i
.op
[this_operand
].regs
= r
;
7657 else if (*op_string
== REGISTER_PREFIX
)
7659 as_bad (_("bad register name `%s'"), op_string
);
7662 else if (*op_string
== IMMEDIATE_PREFIX
)
7665 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7667 as_bad (_("immediate operand illegal with absolute jump"));
7670 if (!i386_immediate (op_string
))
7673 else if (is_digit_char (*op_string
)
7674 || is_identifier_char (*op_string
)
7675 || *op_string
== '(')
7677 /* This is a memory reference of some sort. */
7680 /* Start and end of displacement string expression (if found). */
7681 char *displacement_string_start
;
7682 char *displacement_string_end
;
7684 do_memory_reference
:
7685 if ((i
.mem_operands
== 1
7686 && !current_templates
->start
->opcode_modifier
.isstring
)
7687 || i
.mem_operands
== 2)
7689 as_bad (_("too many memory references for `%s'"),
7690 current_templates
->start
->name
);
7694 /* Check for base index form. We detect the base index form by
7695 looking for an ')' at the end of the operand, searching
7696 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7698 base_string
= op_string
+ strlen (op_string
);
7701 if (is_space_char (*base_string
))
7704 /* If we only have a displacement, set-up for it to be parsed later. */
7705 displacement_string_start
= op_string
;
7706 displacement_string_end
= base_string
+ 1;
7708 if (*base_string
== ')')
7711 unsigned int parens_balanced
= 1;
7712 /* We've already checked that the number of left & right ()'s are
7713 equal, so this loop will not be infinite. */
7717 if (*base_string
== ')')
7719 if (*base_string
== '(')
7722 while (parens_balanced
);
7724 temp_string
= base_string
;
7726 /* Skip past '(' and whitespace. */
7728 if (is_space_char (*base_string
))
7731 if (*base_string
== ','
7732 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7735 displacement_string_end
= temp_string
;
7737 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7741 base_string
= end_op
;
7742 if (is_space_char (*base_string
))
7746 /* There may be an index reg or scale factor here. */
7747 if (*base_string
== ',')
7750 if (is_space_char (*base_string
))
7753 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7756 base_string
= end_op
;
7757 if (is_space_char (*base_string
))
7759 if (*base_string
== ',')
7762 if (is_space_char (*base_string
))
7765 else if (*base_string
!= ')')
7767 as_bad (_("expecting `,' or `)' "
7768 "after index register in `%s'"),
7773 else if (*base_string
== REGISTER_PREFIX
)
7775 end_op
= strchr (base_string
, ',');
7778 as_bad (_("bad register name `%s'"), base_string
);
7782 /* Check for scale factor. */
7783 if (*base_string
!= ')')
7785 char *end_scale
= i386_scale (base_string
);
7790 base_string
= end_scale
;
7791 if (is_space_char (*base_string
))
7793 if (*base_string
!= ')')
7795 as_bad (_("expecting `)' "
7796 "after scale factor in `%s'"),
7801 else if (!i
.index_reg
)
7803 as_bad (_("expecting index register or scale factor "
7804 "after `,'; got '%c'"),
7809 else if (*base_string
!= ')')
7811 as_bad (_("expecting `,' or `)' "
7812 "after base register in `%s'"),
7817 else if (*base_string
== REGISTER_PREFIX
)
7819 end_op
= strchr (base_string
, ',');
7822 as_bad (_("bad register name `%s'"), base_string
);
7827 /* If there's an expression beginning the operand, parse it,
7828 assuming displacement_string_start and
7829 displacement_string_end are meaningful. */
7830 if (displacement_string_start
!= displacement_string_end
)
7832 if (!i386_displacement (displacement_string_start
,
7833 displacement_string_end
))
7837 /* Special case for (%dx) while doing input/output op. */
7839 && operand_type_equal (&i
.base_reg
->reg_type
,
7840 ®16_inoutportreg
)
7842 && i
.log2_scale_factor
== 0
7843 && i
.seg
[i
.mem_operands
] == 0
7844 && !operand_type_check (i
.types
[this_operand
], disp
))
7846 i
.types
[this_operand
] = inoutportreg
;
7850 if (i386_index_check (operand_string
) == 0)
7852 i
.types
[this_operand
].bitfield
.mem
= 1;
7857 /* It's not a memory operand; argh! */
7858 as_bad (_("invalid char %s beginning operand %d `%s'"),
7859 output_invalid (*op_string
),
7864 return 1; /* Normal return. */
7867 /* Calculate the maximum variable size (i.e., excluding fr_fix)
7868 that an rs_machine_dependent frag may reach. */
7871 i386_frag_max_var (fragS
*frag
)
7873 /* The only relaxable frags are for jumps.
7874 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
7875 gas_assert (frag
->fr_type
== rs_machine_dependent
);
7876 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
7879 /* md_estimate_size_before_relax()
7881 Called just before relax() for rs_machine_dependent frags. The x86
7882 assembler uses these frags to handle variable size jump
7885 Any symbol that is now undefined will not become defined.
7886 Return the correct fr_subtype in the frag.
7887 Return the initial "guess for variable size of frag" to caller.
7888 The guess is actually the growth beyond the fixed part. Whatever
7889 we do to grow the fixed or variable part contributes to our
7893 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
7895 /* We've already got fragP->fr_subtype right; all we have to do is
7896 check for un-relaxable symbols. On an ELF system, we can't relax
7897 an externally visible symbol, because it may be overridden by a
7899 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7900 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7902 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7903 || S_IS_WEAK (fragP
->fr_symbol
)
7904 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7905 & BSF_GNU_INDIRECT_FUNCTION
))))
7907 #if defined (OBJ_COFF) && defined (TE_PE)
7908 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7909 && S_IS_WEAK (fragP
->fr_symbol
))
7913 /* Symbol is undefined in this segment, or we need to keep a
7914 reloc so that weak symbols can be overridden. */
7915 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7916 enum bfd_reloc_code_real reloc_type
;
7917 unsigned char *opcode
;
7920 if (fragP
->fr_var
!= NO_RELOC
)
7921 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7923 reloc_type
= BFD_RELOC_16_PCREL
;
7925 reloc_type
= BFD_RELOC_32_PCREL
;
7927 old_fr_fix
= fragP
->fr_fix
;
7928 opcode
= (unsigned char *) fragP
->fr_opcode
;
7930 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7933 /* Make jmp (0xeb) a (d)word displacement jump. */
7935 fragP
->fr_fix
+= size
;
7936 fix_new (fragP
, old_fr_fix
, size
,
7938 fragP
->fr_offset
, 1,
7944 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7946 /* Negate the condition, and branch past an
7947 unconditional jump. */
7950 /* Insert an unconditional jump. */
7952 /* We added two extra opcode bytes, and have a two byte
7954 fragP
->fr_fix
+= 2 + 2;
7955 fix_new (fragP
, old_fr_fix
+ 2, 2,
7957 fragP
->fr_offset
, 1,
7964 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7969 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7971 fragP
->fr_offset
, 1,
7973 fixP
->fx_signed
= 1;
7977 /* This changes the byte-displacement jump 0x7N
7978 to the (d)word-displacement jump 0x0f,0x8N. */
7979 opcode
[1] = opcode
[0] + 0x10;
7980 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7981 /* We've added an opcode byte. */
7982 fragP
->fr_fix
+= 1 + size
;
7983 fix_new (fragP
, old_fr_fix
+ 1, size
,
7985 fragP
->fr_offset
, 1,
7990 BAD_CASE (fragP
->fr_subtype
);
7994 return fragP
->fr_fix
- old_fr_fix
;
7997 /* Guess size depending on current relax state. Initially the relax
7998 state will correspond to a short jump and we return 1, because
7999 the variable part of the frag (the branch offset) is one byte
8000 long. However, we can relax a section more than once and in that
8001 case we must either set fr_subtype back to the unrelaxed state,
8002 or return the value for the appropriate branch. */
8003 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
8006 /* Called after relax() is finished.
8008 In: Address of frag.
8009 fr_type == rs_machine_dependent.
8010 fr_subtype is what the address relaxed to.
8012 Out: Any fixSs and constants are set up.
8013 Caller will turn frag into a ".space 0". */
8016 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
8019 unsigned char *opcode
;
8020 unsigned char *where_to_put_displacement
= NULL
;
8021 offsetT target_address
;
8022 offsetT opcode_address
;
8023 unsigned int extension
= 0;
8024 offsetT displacement_from_opcode_start
;
8026 opcode
= (unsigned char *) fragP
->fr_opcode
;
8028 /* Address we want to reach in file space. */
8029 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
8031 /* Address opcode resides at in file space. */
8032 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
8034 /* Displacement from opcode start to fill into instruction. */
8035 displacement_from_opcode_start
= target_address
- opcode_address
;
8037 if ((fragP
->fr_subtype
& BIG
) == 0)
8039 /* Don't have to change opcode. */
8040 extension
= 1; /* 1 opcode + 1 displacement */
8041 where_to_put_displacement
= &opcode
[1];
8045 if (no_cond_jump_promotion
8046 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
8047 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
8048 _("long jump required"));
8050 switch (fragP
->fr_subtype
)
8052 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
8053 extension
= 4; /* 1 opcode + 4 displacement */
8055 where_to_put_displacement
= &opcode
[1];
8058 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
8059 extension
= 2; /* 1 opcode + 2 displacement */
8061 where_to_put_displacement
= &opcode
[1];
8064 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
8065 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
8066 extension
= 5; /* 2 opcode + 4 displacement */
8067 opcode
[1] = opcode
[0] + 0x10;
8068 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8069 where_to_put_displacement
= &opcode
[2];
8072 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
8073 extension
= 3; /* 2 opcode + 2 displacement */
8074 opcode
[1] = opcode
[0] + 0x10;
8075 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8076 where_to_put_displacement
= &opcode
[2];
8079 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
8084 where_to_put_displacement
= &opcode
[3];
8088 BAD_CASE (fragP
->fr_subtype
);
8093 /* If size if less then four we are sure that the operand fits,
8094 but if it's 4, then it could be that the displacement is larger
8096 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
8098 && ((addressT
) (displacement_from_opcode_start
- extension
8099 + ((addressT
) 1 << 31))
8100 > (((addressT
) 2 << 31) - 1)))
8102 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
8103 _("jump target out of range"));
8104 /* Make us emit 0. */
8105 displacement_from_opcode_start
= extension
;
8107 /* Now put displacement after opcode. */
8108 md_number_to_chars ((char *) where_to_put_displacement
,
8109 (valueT
) (displacement_from_opcode_start
- extension
),
8110 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
8111 fragP
->fr_fix
+= extension
;
8114 /* Apply a fixup (fixP) to segment data, once it has been determined
8115 by our caller that we have all the info we need to fix it up.
8117 Parameter valP is the pointer to the value of the bits.
8119 On the 386, immediates, displacements, and data pointers are all in
8120 the same (little-endian) format, so we don't need to care about which
8124 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
8126 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
8127 valueT value
= *valP
;
8129 #if !defined (TE_Mach)
8132 switch (fixP
->fx_r_type
)
8138 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
8141 case BFD_RELOC_X86_64_32S
:
8142 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
8145 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
8148 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
8153 if (fixP
->fx_addsy
!= NULL
8154 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
8155 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
8156 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
8157 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
8158 && !use_rela_relocations
)
8160 /* This is a hack. There should be a better way to handle this.
8161 This covers for the fact that bfd_install_relocation will
8162 subtract the current location (for partial_inplace, PC relative
8163 relocations); see more below. */
8167 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
8170 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8172 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8175 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
8178 || (symbol_section_p (fixP
->fx_addsy
)
8179 && sym_seg
!= absolute_section
))
8180 && !generic_force_reloc (fixP
))
8182 /* Yes, we add the values in twice. This is because
8183 bfd_install_relocation subtracts them out again. I think
8184 bfd_install_relocation is broken, but I don't dare change
8186 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8190 #if defined (OBJ_COFF) && defined (TE_PE)
8191 /* For some reason, the PE format does not store a
8192 section address offset for a PC relative symbol. */
8193 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
8194 || S_IS_WEAK (fixP
->fx_addsy
))
8195 value
+= md_pcrel_from (fixP
);
8198 #if defined (OBJ_COFF) && defined (TE_PE)
8199 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
8201 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8205 /* Fix a few things - the dynamic linker expects certain values here,
8206 and we must not disappoint it. */
8207 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8208 if (IS_ELF
&& fixP
->fx_addsy
)
8209 switch (fixP
->fx_r_type
)
8211 case BFD_RELOC_386_PLT32
:
8212 case BFD_RELOC_X86_64_PLT32
:
8213 /* Make the jump instruction point to the address of the operand. At
8214 runtime we merely add the offset to the actual PLT entry. */
8218 case BFD_RELOC_386_TLS_GD
:
8219 case BFD_RELOC_386_TLS_LDM
:
8220 case BFD_RELOC_386_TLS_IE_32
:
8221 case BFD_RELOC_386_TLS_IE
:
8222 case BFD_RELOC_386_TLS_GOTIE
:
8223 case BFD_RELOC_386_TLS_GOTDESC
:
8224 case BFD_RELOC_X86_64_TLSGD
:
8225 case BFD_RELOC_X86_64_TLSLD
:
8226 case BFD_RELOC_X86_64_GOTTPOFF
:
8227 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8228 value
= 0; /* Fully resolved at runtime. No addend. */
8230 case BFD_RELOC_386_TLS_LE
:
8231 case BFD_RELOC_386_TLS_LDO_32
:
8232 case BFD_RELOC_386_TLS_LE_32
:
8233 case BFD_RELOC_X86_64_DTPOFF32
:
8234 case BFD_RELOC_X86_64_DTPOFF64
:
8235 case BFD_RELOC_X86_64_TPOFF32
:
8236 case BFD_RELOC_X86_64_TPOFF64
:
8237 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8240 case BFD_RELOC_386_TLS_DESC_CALL
:
8241 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8242 value
= 0; /* Fully resolved at runtime. No addend. */
8243 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8247 case BFD_RELOC_386_GOT32
:
8248 case BFD_RELOC_X86_64_GOT32
:
8249 value
= 0; /* Fully resolved at runtime. No addend. */
8252 case BFD_RELOC_VTABLE_INHERIT
:
8253 case BFD_RELOC_VTABLE_ENTRY
:
8260 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
8262 #endif /* !defined (TE_Mach) */
8264 /* Are we finished with this relocation now? */
8265 if (fixP
->fx_addsy
== NULL
)
8267 #if defined (OBJ_COFF) && defined (TE_PE)
8268 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
8271 /* Remember value for tc_gen_reloc. */
8272 fixP
->fx_addnumber
= value
;
8273 /* Clear out the frag for now. */
8277 else if (use_rela_relocations
)
8279 fixP
->fx_no_overflow
= 1;
8280 /* Remember value for tc_gen_reloc. */
8281 fixP
->fx_addnumber
= value
;
8285 md_number_to_chars (p
, value
, fixP
->fx_size
);
8289 md_atof (int type
, char *litP
, int *sizeP
)
8291 /* This outputs the LITTLENUMs in REVERSE order;
8292 in accord with the bigendian 386. */
8293 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
8296 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
8299 output_invalid (int c
)
8302 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
8305 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
8306 "(0x%x)", (unsigned char) c
);
8307 return output_invalid_buf
;
8310 /* REG_STRING starts *before* REGISTER_PREFIX. */
8312 static const reg_entry
*
8313 parse_real_register (char *reg_string
, char **end_op
)
8315 char *s
= reg_string
;
8317 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
8320 /* Skip possible REGISTER_PREFIX and possible whitespace. */
8321 if (*s
== REGISTER_PREFIX
)
8324 if (is_space_char (*s
))
8328 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
8330 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
8331 return (const reg_entry
*) NULL
;
8335 /* For naked regs, make sure that we are not dealing with an identifier.
8336 This prevents confusing an identifier like `eax_var' with register
8338 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
8339 return (const reg_entry
*) NULL
;
8343 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
8345 /* Handle floating point regs, allowing spaces in the (i) part. */
8346 if (r
== i386_regtab
/* %st is first entry of table */)
8348 if (is_space_char (*s
))
8353 if (is_space_char (*s
))
8355 if (*s
>= '0' && *s
<= '7')
8359 if (is_space_char (*s
))
8364 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
8369 /* We have "%st(" then garbage. */
8370 return (const reg_entry
*) NULL
;
8374 if (r
== NULL
|| allow_pseudo_reg
)
8377 if (operand_type_all_zero (&r
->reg_type
))
8378 return (const reg_entry
*) NULL
;
8380 if ((r
->reg_type
.bitfield
.reg32
8381 || r
->reg_type
.bitfield
.sreg3
8382 || r
->reg_type
.bitfield
.control
8383 || r
->reg_type
.bitfield
.debug
8384 || r
->reg_type
.bitfield
.test
)
8385 && !cpu_arch_flags
.bitfield
.cpui386
)
8386 return (const reg_entry
*) NULL
;
8388 if (r
->reg_type
.bitfield
.floatreg
8389 && !cpu_arch_flags
.bitfield
.cpu8087
8390 && !cpu_arch_flags
.bitfield
.cpu287
8391 && !cpu_arch_flags
.bitfield
.cpu387
)
8392 return (const reg_entry
*) NULL
;
8394 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
8395 return (const reg_entry
*) NULL
;
8397 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
8398 return (const reg_entry
*) NULL
;
8400 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
8401 return (const reg_entry
*) NULL
;
8403 /* Don't allow fake index register unless allow_index_reg isn't 0. */
8404 if (!allow_index_reg
8405 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
8406 return (const reg_entry
*) NULL
;
8408 if (((r
->reg_flags
& (RegRex64
| RegRex
))
8409 || r
->reg_type
.bitfield
.reg64
)
8410 && (!cpu_arch_flags
.bitfield
.cpulm
8411 || !operand_type_equal (&r
->reg_type
, &control
))
8412 && flag_code
!= CODE_64BIT
)
8413 return (const reg_entry
*) NULL
;
8415 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
8416 return (const reg_entry
*) NULL
;
8421 /* REG_STRING starts *before* REGISTER_PREFIX. */
8423 static const reg_entry
*
8424 parse_register (char *reg_string
, char **end_op
)
8428 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
8429 r
= parse_real_register (reg_string
, end_op
);
8434 char *save
= input_line_pointer
;
8438 input_line_pointer
= reg_string
;
8439 c
= get_symbol_end ();
8440 symbolP
= symbol_find (reg_string
);
8441 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
8443 const expressionS
*e
= symbol_get_value_expression (symbolP
);
8445 know (e
->X_op
== O_register
);
8446 know (e
->X_add_number
>= 0
8447 && (valueT
) e
->X_add_number
< i386_regtab_size
);
8448 r
= i386_regtab
+ e
->X_add_number
;
8449 *end_op
= input_line_pointer
;
8451 *input_line_pointer
= c
;
8452 input_line_pointer
= save
;
8458 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
8461 char *end
= input_line_pointer
;
8464 r
= parse_register (name
, &input_line_pointer
);
8465 if (r
&& end
<= input_line_pointer
)
8467 *nextcharP
= *input_line_pointer
;
8468 *input_line_pointer
= 0;
8469 e
->X_op
= O_register
;
8470 e
->X_add_number
= r
- i386_regtab
;
8473 input_line_pointer
= end
;
8475 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
8479 md_operand (expressionS
*e
)
8484 switch (*input_line_pointer
)
8486 case REGISTER_PREFIX
:
8487 r
= parse_real_register (input_line_pointer
, &end
);
8490 e
->X_op
= O_register
;
8491 e
->X_add_number
= r
- i386_regtab
;
8492 input_line_pointer
= end
;
8497 gas_assert (intel_syntax
);
8498 end
= input_line_pointer
++;
8500 if (*input_line_pointer
== ']')
8502 ++input_line_pointer
;
8503 e
->X_op_symbol
= make_expr_symbol (e
);
8504 e
->X_add_symbol
= NULL
;
8505 e
->X_add_number
= 0;
8511 input_line_pointer
= end
;
8518 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8519 const char *md_shortopts
= "kVQ:sqn";
8521 const char *md_shortopts
= "qn";
8524 #define OPTION_32 (OPTION_MD_BASE + 0)
8525 #define OPTION_64 (OPTION_MD_BASE + 1)
8526 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
8527 #define OPTION_MARCH (OPTION_MD_BASE + 3)
8528 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
8529 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8530 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8531 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8532 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8533 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
8534 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
8535 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
8536 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
8537 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
8538 #define OPTION_X32 (OPTION_MD_BASE + 14)
8540 struct option md_longopts
[] =
8542 {"32", no_argument
, NULL
, OPTION_32
},
8543 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8544 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8545 {"64", no_argument
, NULL
, OPTION_64
},
8547 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8548 {"x32", no_argument
, NULL
, OPTION_X32
},
8550 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
8551 {"march", required_argument
, NULL
, OPTION_MARCH
},
8552 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
8553 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
8554 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
8555 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
8556 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
8557 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
8558 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
8559 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
8560 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
8561 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
8562 {NULL
, no_argument
, NULL
, 0}
8564 size_t md_longopts_size
= sizeof (md_longopts
);
8567 md_parse_option (int c
, char *arg
)
8575 optimize_align_code
= 0;
8582 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8583 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8584 should be emitted or not. FIXME: Not implemented. */
8588 /* -V: SVR4 argument to print version ID. */
8590 print_version_id ();
8593 /* -k: Ignore for FreeBSD compatibility. */
8598 /* -s: On i386 Solaris, this tells the native assembler to use
8599 .stab instead of .stab.excl. We always use .stab anyhow. */
8602 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8603 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8606 const char **list
, **l
;
8608 list
= bfd_target_list ();
8609 for (l
= list
; *l
!= NULL
; l
++)
8610 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8611 || strcmp (*l
, "coff-x86-64") == 0
8612 || strcmp (*l
, "pe-x86-64") == 0
8613 || strcmp (*l
, "pei-x86-64") == 0
8614 || strcmp (*l
, "mach-o-x86-64") == 0)
8616 default_arch
= "x86_64";
8620 as_fatal (_("no compiled in support for x86_64"));
8626 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8630 const char **list
, **l
;
8632 list
= bfd_target_list ();
8633 for (l
= list
; *l
!= NULL
; l
++)
8634 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
8636 default_arch
= "x86_64:32";
8640 as_fatal (_("no compiled in support for 32bit x86_64"));
8644 as_fatal (_("32bit x86_64 is only supported for ELF"));
8649 default_arch
= "i386";
8653 #ifdef SVR4_COMMENT_CHARS
8658 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8660 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8664 i386_comment_chars
= n
;
8670 arch
= xstrdup (arg
);
8674 as_fatal (_("invalid -march= option: `%s'"), arg
);
8675 next
= strchr (arch
, '+');
8678 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8680 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
8683 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8686 cpu_arch_name
= cpu_arch
[j
].name
;
8687 cpu_sub_arch_name
= NULL
;
8688 cpu_arch_flags
= cpu_arch
[j
].flags
;
8689 cpu_arch_isa
= cpu_arch
[j
].type
;
8690 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
8691 if (!cpu_arch_tune_set
)
8693 cpu_arch_tune
= cpu_arch_isa
;
8694 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8698 else if (*cpu_arch
[j
].name
== '.'
8699 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
8701 /* ISA entension. */
8702 i386_cpu_flags flags
;
8704 if (!cpu_arch
[j
].negated
)
8705 flags
= cpu_flags_or (cpu_arch_flags
,
8708 flags
= cpu_flags_and_not (cpu_arch_flags
,
8710 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8712 if (cpu_sub_arch_name
)
8714 char *name
= cpu_sub_arch_name
;
8715 cpu_sub_arch_name
= concat (name
,
8717 (const char *) NULL
);
8721 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
8722 cpu_arch_flags
= flags
;
8723 cpu_arch_isa_flags
= flags
;
8729 if (j
>= ARRAY_SIZE (cpu_arch
))
8730 as_fatal (_("invalid -march= option: `%s'"), arg
);
8734 while (next
!= NULL
);
8739 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
8740 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8742 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
8744 cpu_arch_tune_set
= 1;
8745 cpu_arch_tune
= cpu_arch
[j
].type
;
8746 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
8750 if (j
>= ARRAY_SIZE (cpu_arch
))
8751 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
8754 case OPTION_MMNEMONIC
:
8755 if (strcasecmp (arg
, "att") == 0)
8757 else if (strcasecmp (arg
, "intel") == 0)
8760 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
8763 case OPTION_MSYNTAX
:
8764 if (strcasecmp (arg
, "att") == 0)
8766 else if (strcasecmp (arg
, "intel") == 0)
8769 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
8772 case OPTION_MINDEX_REG
:
8773 allow_index_reg
= 1;
8776 case OPTION_MNAKED_REG
:
8777 allow_naked_reg
= 1;
8780 case OPTION_MOLD_GCC
:
8784 case OPTION_MSSE2AVX
:
8788 case OPTION_MSSE_CHECK
:
8789 if (strcasecmp (arg
, "error") == 0)
8790 sse_check
= check_error
;
8791 else if (strcasecmp (arg
, "warning") == 0)
8792 sse_check
= check_warning
;
8793 else if (strcasecmp (arg
, "none") == 0)
8794 sse_check
= check_none
;
8796 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
8799 case OPTION_MOPERAND_CHECK
:
8800 if (strcasecmp (arg
, "error") == 0)
8801 operand_check
= check_error
;
8802 else if (strcasecmp (arg
, "warning") == 0)
8803 operand_check
= check_warning
;
8804 else if (strcasecmp (arg
, "none") == 0)
8805 operand_check
= check_none
;
8807 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
8810 case OPTION_MAVXSCALAR
:
8811 if (strcasecmp (arg
, "128") == 0)
8813 else if (strcasecmp (arg
, "256") == 0)
8816 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
8825 #define MESSAGE_TEMPLATE \
8829 show_arch (FILE *stream
, int ext
, int check
)
8831 static char message
[] = MESSAGE_TEMPLATE
;
8832 char *start
= message
+ 27;
8834 int size
= sizeof (MESSAGE_TEMPLATE
);
8841 left
= size
- (start
- message
);
8842 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8844 /* Should it be skipped? */
8845 if (cpu_arch
[j
].skip
)
8848 name
= cpu_arch
[j
].name
;
8849 len
= cpu_arch
[j
].len
;
8852 /* It is an extension. Skip if we aren't asked to show it. */
8863 /* It is an processor. Skip if we show only extension. */
8866 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8868 /* It is an impossible processor - skip. */
8872 /* Reserve 2 spaces for ", " or ",\0" */
8875 /* Check if there is any room. */
8883 p
= mempcpy (p
, name
, len
);
8887 /* Output the current message now and start a new one. */
8890 fprintf (stream
, "%s\n", message
);
8892 left
= size
- (start
- message
) - len
- 2;
8894 gas_assert (left
>= 0);
8896 p
= mempcpy (p
, name
, len
);
8901 fprintf (stream
, "%s\n", message
);
8905 md_show_usage (FILE *stream
)
8907 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8908 fprintf (stream
, _("\
8910 -V print assembler version number\n\
8913 fprintf (stream
, _("\
8914 -n Do not optimize code alignment\n\
8915 -q quieten some warnings\n"));
8916 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8917 fprintf (stream
, _("\
8920 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8921 || defined (TE_PE) || defined (TE_PEP))
8922 fprintf (stream
, _("\
8923 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
8925 #ifdef SVR4_COMMENT_CHARS
8926 fprintf (stream
, _("\
8927 --divide do not treat `/' as a comment character\n"));
8929 fprintf (stream
, _("\
8930 --divide ignored\n"));
8932 fprintf (stream
, _("\
8933 -march=CPU[,+EXTENSION...]\n\
8934 generate code for CPU and EXTENSION, CPU is one of:\n"));
8935 show_arch (stream
, 0, 1);
8936 fprintf (stream
, _("\
8937 EXTENSION is combination of:\n"));
8938 show_arch (stream
, 1, 0);
8939 fprintf (stream
, _("\
8940 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8941 show_arch (stream
, 0, 0);
8942 fprintf (stream
, _("\
8943 -msse2avx encode SSE instructions with VEX prefix\n"));
8944 fprintf (stream
, _("\
8945 -msse-check=[none|error|warning]\n\
8946 check SSE instructions\n"));
8947 fprintf (stream
, _("\
8948 -moperand-check=[none|error|warning]\n\
8949 check operand combinations for validity\n"));
8950 fprintf (stream
, _("\
8951 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8953 fprintf (stream
, _("\
8954 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8955 fprintf (stream
, _("\
8956 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8957 fprintf (stream
, _("\
8958 -mindex-reg support pseudo index registers\n"));
8959 fprintf (stream
, _("\
8960 -mnaked-reg don't require `%%' prefix for registers\n"));
8961 fprintf (stream
, _("\
8962 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8965 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8966 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8967 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8969 /* Pick the target format to use. */
8972 i386_target_format (void)
8974 if (!strncmp (default_arch
, "x86_64", 6))
8976 update_code_flag (CODE_64BIT
, 1);
8977 if (default_arch
[6] == '\0')
8978 x86_elf_abi
= X86_64_ABI
;
8980 x86_elf_abi
= X86_64_X32_ABI
;
8982 else if (!strcmp (default_arch
, "i386"))
8983 update_code_flag (CODE_32BIT
, 1);
8985 as_fatal (_("unknown architecture"));
8987 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8988 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
8989 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8990 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
8992 switch (OUTPUT_FLAVOR
)
8994 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
8995 case bfd_target_aout_flavour
:
8996 return AOUT_TARGET_FORMAT
;
8998 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8999 # if defined (TE_PE) || defined (TE_PEP)
9000 case bfd_target_coff_flavour
:
9001 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
9002 # elif defined (TE_GO32)
9003 case bfd_target_coff_flavour
:
9006 case bfd_target_coff_flavour
:
9010 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9011 case bfd_target_elf_flavour
:
9015 switch (x86_elf_abi
)
9018 format
= ELF_TARGET_FORMAT
;
9021 use_rela_relocations
= 1;
9023 format
= ELF_TARGET_FORMAT64
;
9025 case X86_64_X32_ABI
:
9026 use_rela_relocations
= 1;
9028 disallow_64bit_reloc
= 1;
9029 format
= ELF_TARGET_FORMAT32
;
9032 if (cpu_arch_isa
== PROCESSOR_L1OM
)
9034 if (x86_elf_abi
!= X86_64_ABI
)
9035 as_fatal (_("Intel L1OM is 64bit only"));
9036 return ELF_TARGET_L1OM_FORMAT
;
9038 if (cpu_arch_isa
== PROCESSOR_K1OM
)
9040 if (x86_elf_abi
!= X86_64_ABI
)
9041 as_fatal (_("Intel K1OM is 64bit only"));
9042 return ELF_TARGET_K1OM_FORMAT
;
9048 #if defined (OBJ_MACH_O)
9049 case bfd_target_mach_o_flavour
:
9050 if (flag_code
== CODE_64BIT
)
9052 use_rela_relocations
= 1;
9054 return "mach-o-x86-64";
9057 return "mach-o-i386";
9065 #endif /* OBJ_MAYBE_ more than one */
9067 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
9069 i386_elf_emit_arch_note (void)
9071 if (IS_ELF
&& cpu_arch_name
!= NULL
)
9074 asection
*seg
= now_seg
;
9075 subsegT subseg
= now_subseg
;
9076 Elf_Internal_Note i_note
;
9077 Elf_External_Note e_note
;
9078 asection
*note_secp
;
9081 /* Create the .note section. */
9082 note_secp
= subseg_new (".note", 0);
9083 bfd_set_section_flags (stdoutput
,
9085 SEC_HAS_CONTENTS
| SEC_READONLY
);
9087 /* Process the arch string. */
9088 len
= strlen (cpu_arch_name
);
9090 i_note
.namesz
= len
+ 1;
9092 i_note
.type
= NT_ARCH
;
9093 p
= frag_more (sizeof (e_note
.namesz
));
9094 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
9095 p
= frag_more (sizeof (e_note
.descsz
));
9096 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
9097 p
= frag_more (sizeof (e_note
.type
));
9098 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
9099 p
= frag_more (len
+ 1);
9100 strcpy (p
, cpu_arch_name
);
9102 frag_align (2, 0, 0);
9104 subseg_set (seg
, subseg
);
9110 md_undefined_symbol (char *name
)
9112 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
9113 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
9114 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
9115 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
9119 if (symbol_find (name
))
9120 as_bad (_("GOT already in symbol table"));
9121 GOT_symbol
= symbol_new (name
, undefined_section
,
9122 (valueT
) 0, &zero_address_frag
);
9129 /* Round up a section size to the appropriate boundary. */
9132 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
9134 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9135 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
9137 /* For a.out, force the section size to be aligned. If we don't do
9138 this, BFD will align it for us, but it will not write out the
9139 final bytes of the section. This may be a bug in BFD, but it is
9140 easier to fix it here since that is how the other a.out targets
9144 align
= bfd_get_section_alignment (stdoutput
, segment
);
9145 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
9152 /* On the i386, PC-relative offsets are relative to the start of the
9153 next instruction. That is, the address of the offset, plus its
9154 size, since the offset is always the last part of the insn. */
9157 md_pcrel_from (fixS
*fixP
)
9159 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9165 s_bss (int ignore ATTRIBUTE_UNUSED
)
9169 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9171 obj_elf_section_change_hook ();
9173 temp
= get_absolute_expression ();
9174 subseg_set (bss_section
, (subsegT
) temp
);
9175 demand_empty_rest_of_line ();
9181 i386_validate_fix (fixS
*fixp
)
9183 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
9185 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
9189 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
9194 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
9196 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
9203 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
9206 bfd_reloc_code_real_type code
;
9208 switch (fixp
->fx_r_type
)
9210 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9211 case BFD_RELOC_SIZE32
:
9212 case BFD_RELOC_SIZE64
:
9213 if (S_IS_DEFINED (fixp
->fx_addsy
)
9214 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
9216 /* Resolve size relocation against local symbol to size of
9217 the symbol plus addend. */
9218 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
9219 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
9220 && !fits_in_unsigned_long (value
))
9221 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9222 _("symbol size computation overflow"));
9223 fixp
->fx_addsy
= NULL
;
9224 fixp
->fx_subsy
= NULL
;
9225 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
9230 case BFD_RELOC_X86_64_PLT32
:
9231 case BFD_RELOC_X86_64_GOT32
:
9232 case BFD_RELOC_X86_64_GOTPCREL
:
9233 case BFD_RELOC_386_PLT32
:
9234 case BFD_RELOC_386_GOT32
:
9235 case BFD_RELOC_386_GOTOFF
:
9236 case BFD_RELOC_386_GOTPC
:
9237 case BFD_RELOC_386_TLS_GD
:
9238 case BFD_RELOC_386_TLS_LDM
:
9239 case BFD_RELOC_386_TLS_LDO_32
:
9240 case BFD_RELOC_386_TLS_IE_32
:
9241 case BFD_RELOC_386_TLS_IE
:
9242 case BFD_RELOC_386_TLS_GOTIE
:
9243 case BFD_RELOC_386_TLS_LE_32
:
9244 case BFD_RELOC_386_TLS_LE
:
9245 case BFD_RELOC_386_TLS_GOTDESC
:
9246 case BFD_RELOC_386_TLS_DESC_CALL
:
9247 case BFD_RELOC_X86_64_TLSGD
:
9248 case BFD_RELOC_X86_64_TLSLD
:
9249 case BFD_RELOC_X86_64_DTPOFF32
:
9250 case BFD_RELOC_X86_64_DTPOFF64
:
9251 case BFD_RELOC_X86_64_GOTTPOFF
:
9252 case BFD_RELOC_X86_64_TPOFF32
:
9253 case BFD_RELOC_X86_64_TPOFF64
:
9254 case BFD_RELOC_X86_64_GOTOFF64
:
9255 case BFD_RELOC_X86_64_GOTPC32
:
9256 case BFD_RELOC_X86_64_GOT64
:
9257 case BFD_RELOC_X86_64_GOTPCREL64
:
9258 case BFD_RELOC_X86_64_GOTPC64
:
9259 case BFD_RELOC_X86_64_GOTPLT64
:
9260 case BFD_RELOC_X86_64_PLTOFF64
:
9261 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9262 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9264 case BFD_RELOC_VTABLE_ENTRY
:
9265 case BFD_RELOC_VTABLE_INHERIT
:
9267 case BFD_RELOC_32_SECREL
:
9269 code
= fixp
->fx_r_type
;
9271 case BFD_RELOC_X86_64_32S
:
9272 if (!fixp
->fx_pcrel
)
9274 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
9275 code
= fixp
->fx_r_type
;
9281 switch (fixp
->fx_size
)
9284 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9285 _("can not do %d byte pc-relative relocation"),
9287 code
= BFD_RELOC_32_PCREL
;
9289 case 1: code
= BFD_RELOC_8_PCREL
; break;
9290 case 2: code
= BFD_RELOC_16_PCREL
; break;
9291 case 4: code
= BFD_RELOC_32_PCREL
; break;
9293 case 8: code
= BFD_RELOC_64_PCREL
; break;
9299 switch (fixp
->fx_size
)
9302 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9303 _("can not do %d byte relocation"),
9305 code
= BFD_RELOC_32
;
9307 case 1: code
= BFD_RELOC_8
; break;
9308 case 2: code
= BFD_RELOC_16
; break;
9309 case 4: code
= BFD_RELOC_32
; break;
9311 case 8: code
= BFD_RELOC_64
; break;
9318 if ((code
== BFD_RELOC_32
9319 || code
== BFD_RELOC_32_PCREL
9320 || code
== BFD_RELOC_X86_64_32S
)
9322 && fixp
->fx_addsy
== GOT_symbol
)
9325 code
= BFD_RELOC_386_GOTPC
;
9327 code
= BFD_RELOC_X86_64_GOTPC32
;
9329 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
9331 && fixp
->fx_addsy
== GOT_symbol
)
9333 code
= BFD_RELOC_X86_64_GOTPC64
;
9336 rel
= (arelent
*) xmalloc (sizeof (arelent
));
9337 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
9338 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9340 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9342 if (!use_rela_relocations
)
9344 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
9345 vtable entry to be used in the relocation's section offset. */
9346 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
9347 rel
->address
= fixp
->fx_offset
;
9348 #if defined (OBJ_COFF) && defined (TE_PE)
9349 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
9350 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
9355 /* Use the rela in 64bit mode. */
9358 if (disallow_64bit_reloc
)
9361 case BFD_RELOC_X86_64_DTPOFF64
:
9362 case BFD_RELOC_X86_64_TPOFF64
:
9363 case BFD_RELOC_64_PCREL
:
9364 case BFD_RELOC_X86_64_GOTOFF64
:
9365 case BFD_RELOC_X86_64_GOT64
:
9366 case BFD_RELOC_X86_64_GOTPCREL64
:
9367 case BFD_RELOC_X86_64_GOTPC64
:
9368 case BFD_RELOC_X86_64_GOTPLT64
:
9369 case BFD_RELOC_X86_64_PLTOFF64
:
9370 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9371 _("cannot represent relocation type %s in x32 mode"),
9372 bfd_get_reloc_code_name (code
));
9378 if (!fixp
->fx_pcrel
)
9379 rel
->addend
= fixp
->fx_offset
;
9383 case BFD_RELOC_X86_64_PLT32
:
9384 case BFD_RELOC_X86_64_GOT32
:
9385 case BFD_RELOC_X86_64_GOTPCREL
:
9386 case BFD_RELOC_X86_64_TLSGD
:
9387 case BFD_RELOC_X86_64_TLSLD
:
9388 case BFD_RELOC_X86_64_GOTTPOFF
:
9389 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9390 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9391 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
9394 rel
->addend
= (section
->vma
9396 + fixp
->fx_addnumber
9397 + md_pcrel_from (fixp
));
9402 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9403 if (rel
->howto
== NULL
)
9405 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9406 _("cannot represent relocation type %s"),
9407 bfd_get_reloc_code_name (code
));
9408 /* Set howto to a garbage value so that we can keep going. */
9409 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
9410 gas_assert (rel
->howto
!= NULL
);
9416 #include "tc-i386-intel.c"
9419 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
9421 int saved_naked_reg
;
9422 char saved_register_dot
;
9424 saved_naked_reg
= allow_naked_reg
;
9425 allow_naked_reg
= 1;
9426 saved_register_dot
= register_chars
['.'];
9427 register_chars
['.'] = '.';
9428 allow_pseudo_reg
= 1;
9429 expression_and_evaluate (exp
);
9430 allow_pseudo_reg
= 0;
9431 register_chars
['.'] = saved_register_dot
;
9432 allow_naked_reg
= saved_naked_reg
;
9434 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
9436 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
9438 exp
->X_op
= O_constant
;
9439 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
9440 .dw2_regnum
[flag_code
>> 1];
9443 exp
->X_op
= O_illegal
;
9448 tc_x86_frame_initial_instructions (void)
9450 static unsigned int sp_regno
[2];
9452 if (!sp_regno
[flag_code
>> 1])
9454 char *saved_input
= input_line_pointer
;
9455 char sp
[][4] = {"esp", "rsp"};
9458 input_line_pointer
= sp
[flag_code
>> 1];
9459 tc_x86_parse_to_dw2regnum (&exp
);
9460 gas_assert (exp
.X_op
== O_constant
);
9461 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
9462 input_line_pointer
= saved_input
;
9465 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
9466 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
9470 x86_dwarf2_addr_size (void)
9472 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9473 if (x86_elf_abi
== X86_64_X32_ABI
)
9476 return bfd_arch_bits_per_address (stdoutput
) / 8;
9480 i386_elf_section_type (const char *str
, size_t len
)
9482 if (flag_code
== CODE_64BIT
9483 && len
== sizeof ("unwind") - 1
9484 && strncmp (str
, "unwind", 6) == 0)
9485 return SHT_X86_64_UNWIND
;
9492 i386_solaris_fix_up_eh_frame (segT sec
)
9494 if (flag_code
== CODE_64BIT
)
9495 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
9501 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
9505 exp
.X_op
= O_secrel
;
9506 exp
.X_add_symbol
= symbol
;
9507 exp
.X_add_number
= 0;
9508 emit_expr (&exp
, size
);
9512 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9513 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9516 x86_64_section_letter (int letter
, char **ptr_msg
)
9518 if (flag_code
== CODE_64BIT
)
9521 return SHF_X86_64_LARGE
;
9523 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
9526 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
9531 x86_64_section_word (char *str
, size_t len
)
9533 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
9534 return SHF_X86_64_LARGE
;
9540 handle_large_common (int small ATTRIBUTE_UNUSED
)
9542 if (flag_code
!= CODE_64BIT
)
9544 s_comm_internal (0, elf_common_parse
);
9545 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9549 static segT lbss_section
;
9550 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
9551 asection
*saved_bss_section
= bss_section
;
9553 if (lbss_section
== NULL
)
9555 flagword applicable
;
9557 subsegT subseg
= now_subseg
;
9559 /* The .lbss section is for local .largecomm symbols. */
9560 lbss_section
= subseg_new (".lbss", 0);
9561 applicable
= bfd_applicable_section_flags (stdoutput
);
9562 bfd_set_section_flags (stdoutput
, lbss_section
,
9563 applicable
& SEC_ALLOC
);
9564 seg_info (lbss_section
)->bss
= 1;
9566 subseg_set (seg
, subseg
);
9569 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
9570 bss_section
= lbss_section
;
9572 s_comm_internal (0, elf_common_parse
);
9574 elf_com_section_ptr
= saved_com_section_ptr
;
9575 bss_section
= saved_bss_section
;
9578 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */