1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
37 #ifndef REGISTER_WARNINGS
38 #define REGISTER_WARNINGS 1
41 #ifndef INFER_ADDR_PREFIX
42 #define INFER_ADDR_PREFIX 1
45 #ifndef SCALE1_WHEN_NO_INDEX
46 /* Specifying a scale factor besides 1 when there is no index is
47 futile. eg. `mov (%ebx,2),%al' does exactly the same as
48 `mov (%ebx),%al'. To slavishly follow what the programmer
49 specified, set SCALE1_WHEN_NO_INDEX to 0. */
50 #define SCALE1_WHEN_NO_INDEX 1
54 #define DEFAULT_ARCH "i386"
59 #define INLINE __inline__
65 static void set_code_flag (int);
66 static void set_16bit_gcc_code_flag (int);
67 static void set_intel_syntax (int);
68 static void set_cpu_arch (int);
70 static void pe_directive_secrel (int);
72 static void signed_cons (int);
73 static char *output_invalid (int c
);
74 static int i386_operand (char *);
75 static int i386_intel_operand (char *, int);
76 static const reg_entry
*parse_register (char *, char **);
77 static char *parse_insn (char *, char *);
78 static char *parse_operands (char *, const char *);
79 static void swap_operands (void);
80 static void swap_2_operands (int, int);
81 static void optimize_imm (void);
82 static void optimize_disp (void);
83 static int match_template (void);
84 static int check_string (void);
85 static int process_suffix (void);
86 static int check_byte_reg (void);
87 static int check_long_reg (void);
88 static int check_qword_reg (void);
89 static int check_word_reg (void);
90 static int finalize_imm (void);
91 static int process_operands (void);
92 static const seg_entry
*build_modrm_byte (void);
93 static void output_insn (void);
94 static void output_imm (fragS
*, offsetT
);
95 static void output_disp (fragS
*, offsetT
);
97 static void s_bss (int);
99 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
100 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
103 static const char *default_arch
= DEFAULT_ARCH
;
105 /* 'md_assemble ()' gathers together information and puts it into a
112 const reg_entry
*regs
;
117 /* TM holds the template for the insn were currently assembling. */
120 /* SUFFIX holds the instruction mnemonic suffix if given.
121 (e.g. 'l' for 'movl') */
124 /* OPERANDS gives the number of given operands. */
125 unsigned int operands
;
127 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
128 of given register, displacement, memory operands and immediate
130 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
132 /* TYPES [i] is the type (see above #defines) which tells us how to
133 use OP[i] for the corresponding operand. */
134 unsigned int types
[MAX_OPERANDS
];
136 /* Displacement expression, immediate expression, or register for each
138 union i386_op op
[MAX_OPERANDS
];
140 /* Flags for operands. */
141 unsigned int flags
[MAX_OPERANDS
];
142 #define Operand_PCrel 1
144 /* Relocation type for operand */
145 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
147 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
148 the base index byte below. */
149 const reg_entry
*base_reg
;
150 const reg_entry
*index_reg
;
151 unsigned int log2_scale_factor
;
153 /* SEG gives the seg_entries of this insn. They are zero unless
154 explicit segment overrides are given. */
155 const seg_entry
*seg
[2];
157 /* PREFIX holds all the given prefix opcodes (usually null).
158 PREFIXES is the number of prefix opcodes. */
159 unsigned int prefixes
;
160 unsigned char prefix
[MAX_PREFIXES
];
162 /* RM and SIB are the modrm byte and the sib byte where the
163 addressing modes of this insn are encoded. */
170 typedef struct _i386_insn i386_insn
;
172 /* List of chars besides those in app.c:symbol_chars that can start an
173 operand. Used to prevent the scrubber eating vital white-space. */
174 const char extra_symbol_chars
[] = "*%-(["
183 #if (defined (TE_I386AIX) \
184 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
185 && !defined (TE_GNU) \
186 && !defined (TE_LINUX) \
187 && !defined (TE_NETWARE) \
188 && !defined (TE_FreeBSD) \
189 && !defined (TE_NetBSD)))
190 /* This array holds the chars that always start a comment. If the
191 pre-processor is disabled, these aren't very useful. The option
192 --divide will remove '/' from this list. */
193 const char *i386_comment_chars
= "#/";
194 #define SVR4_COMMENT_CHARS 1
195 #define PREFIX_SEPARATOR '\\'
198 const char *i386_comment_chars
= "#";
199 #define PREFIX_SEPARATOR '/'
202 /* This array holds the chars that only start a comment at the beginning of
203 a line. If the line seems to have the form '# 123 filename'
204 .line and .file directives will appear in the pre-processed output.
205 Note that input_file.c hand checks for '#' at the beginning of the
206 first line of the input file. This is because the compiler outputs
207 #NO_APP at the beginning of its output.
208 Also note that comments started like this one will always work if
209 '/' isn't otherwise defined. */
210 const char line_comment_chars
[] = "#/";
212 const char line_separator_chars
[] = ";";
214 /* Chars that can be used to separate mant from exp in floating point
216 const char EXP_CHARS
[] = "eE";
218 /* Chars that mean this number is a floating point constant
221 const char FLT_CHARS
[] = "fFdDxX";
223 /* Tables for lexical analysis. */
224 static char mnemonic_chars
[256];
225 static char register_chars
[256];
226 static char operand_chars
[256];
227 static char identifier_chars
[256];
228 static char digit_chars
[256];
230 /* Lexical macros. */
231 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
232 #define is_operand_char(x) (operand_chars[(unsigned char) x])
233 #define is_register_char(x) (register_chars[(unsigned char) x])
234 #define is_space_char(x) ((x) == ' ')
235 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
236 #define is_digit_char(x) (digit_chars[(unsigned char) x])
238 /* All non-digit non-letter characters that may occur in an operand. */
239 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
241 /* md_assemble() always leaves the strings it's passed unaltered. To
242 effect this we maintain a stack of saved characters that we've smashed
243 with '\0's (indicating end of strings for various sub-fields of the
244 assembler instruction). */
245 static char save_stack
[32];
246 static char *save_stack_p
;
247 #define END_STRING_AND_SAVE(s) \
248 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
249 #define RESTORE_END_STRING(s) \
250 do { *(s) = *--save_stack_p; } while (0)
252 /* The instruction we're assembling. */
255 /* Possible templates for current insn. */
256 static const templates
*current_templates
;
258 /* Per instruction expressionS buffers: max displacements & immediates. */
259 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
260 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
262 /* Current operand we are working on. */
263 static int this_operand
;
265 /* We support four different modes. FLAG_CODE variable is used to distinguish
272 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
274 static enum flag_code flag_code
;
275 static unsigned int object_64bit
;
276 static int use_rela_relocations
= 0;
278 /* The names used to print error messages. */
279 static const char *flag_code_names
[] =
286 /* 1 for intel syntax,
288 static int intel_syntax
= 0;
290 /* 1 if register prefix % not required. */
291 static int allow_naked_reg
= 0;
293 /* Register prefix used for error message. */
294 static const char *register_prefix
= "%";
296 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
297 leave, push, and pop instructions so that gcc has the same stack
298 frame as in 32 bit mode. */
299 static char stackop_size
= '\0';
301 /* Non-zero to optimize code alignment. */
302 int optimize_align_code
= 1;
304 /* Non-zero to quieten some warnings. */
305 static int quiet_warnings
= 0;
308 static const char *cpu_arch_name
= NULL
;
309 static const char *cpu_sub_arch_name
= NULL
;
311 /* CPU feature flags. */
312 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
314 /* If we have selected a cpu we are generating instructions for. */
315 static int cpu_arch_tune_set
= 0;
317 /* Cpu we are generating instructions for. */
318 static enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
320 /* CPU feature flags of cpu we are generating instructions for. */
321 static unsigned int cpu_arch_tune_flags
= 0;
323 /* CPU instruction set architecture used. */
324 static enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
326 /* CPU feature flags of instruction set architecture used. */
327 static unsigned int cpu_arch_isa_flags
= 0;
329 /* If set, conditional jumps are not automatically promoted to handle
330 larger than a byte offset. */
331 static unsigned int no_cond_jump_promotion
= 0;
333 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
334 static symbolS
*GOT_symbol
;
336 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
337 unsigned int x86_dwarf2_return_column
;
339 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
340 int x86_cie_data_alignment
;
342 /* Interface to relax_segment.
343 There are 3 major relax states for 386 jump insns because the
344 different types of jumps add different sizes to frags when we're
345 figuring out what sort of jump to choose to reach a given label. */
348 #define UNCOND_JUMP 0
350 #define COND_JUMP86 2
355 #define SMALL16 (SMALL | CODE16)
357 #define BIG16 (BIG | CODE16)
361 #define INLINE __inline__
367 #define ENCODE_RELAX_STATE(type, size) \
368 ((relax_substateT) (((type) << 2) | (size)))
369 #define TYPE_FROM_RELAX_STATE(s) \
371 #define DISP_SIZE_FROM_RELAX_STATE(s) \
372 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
374 /* This table is used by relax_frag to promote short jumps to long
375 ones where necessary. SMALL (short) jumps may be promoted to BIG
376 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
377 don't allow a short jump in a 32 bit code segment to be promoted to
378 a 16 bit offset jump because it's slower (requires data size
379 prefix), and doesn't work, unless the destination is in the bottom
380 64k of the code segment (The top 16 bits of eip are zeroed). */
382 const relax_typeS md_relax_table
[] =
385 1) most positive reach of this state,
386 2) most negative reach of this state,
387 3) how many bytes this mode will have in the variable part of the frag
388 4) which index into the table to try if we can't fit into this one. */
390 /* UNCOND_JUMP states. */
391 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
393 /* dword jmp adds 4 bytes to frag:
394 0 extra opcode bytes, 4 displacement bytes. */
396 /* word jmp adds 2 byte2 to frag:
397 0 extra opcode bytes, 2 displacement bytes. */
400 /* COND_JUMP states. */
401 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
403 /* dword conditionals adds 5 bytes to frag:
404 1 extra opcode byte, 4 displacement bytes. */
406 /* word conditionals add 3 bytes to frag:
407 1 extra opcode byte, 2 displacement bytes. */
410 /* COND_JUMP86 states. */
411 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
412 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
413 /* dword conditionals adds 5 bytes to frag:
414 1 extra opcode byte, 4 displacement bytes. */
416 /* word conditionals add 4 bytes to frag:
417 1 displacement byte and a 3 byte long branch insn. */
421 static const arch_entry cpu_arch
[] =
423 {"generic32", PROCESSOR_GENERIC32
,
424 Cpu186
|Cpu286
|Cpu386
},
425 {"generic64", PROCESSOR_GENERIC64
,
426 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
427 |CpuMMX2
|CpuSSE
|CpuSSE2
},
428 {"i8086", PROCESSOR_UNKNOWN
,
430 {"i186", PROCESSOR_UNKNOWN
,
432 {"i286", PROCESSOR_UNKNOWN
,
434 {"i386", PROCESSOR_GENERIC32
,
435 Cpu186
|Cpu286
|Cpu386
},
436 {"i486", PROCESSOR_I486
,
437 Cpu186
|Cpu286
|Cpu386
|Cpu486
},
438 {"i586", PROCESSOR_PENTIUM
,
439 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
440 {"i686", PROCESSOR_PENTIUMPRO
,
441 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
442 {"pentium", PROCESSOR_PENTIUM
,
443 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
444 {"pentiumpro",PROCESSOR_PENTIUMPRO
,
445 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
446 {"pentiumii", PROCESSOR_PENTIUMPRO
,
447 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
},
448 {"pentiumiii",PROCESSOR_PENTIUMPRO
,
449 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuMMX2
|CpuSSE
},
450 {"pentium4", PROCESSOR_PENTIUM4
,
451 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
452 |CpuMMX2
|CpuSSE
|CpuSSE2
},
453 {"prescott", PROCESSOR_NOCONA
,
454 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
455 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
456 {"nocona", PROCESSOR_NOCONA
,
457 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
458 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
459 {"yonah", PROCESSOR_CORE
,
460 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
461 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
462 {"core", PROCESSOR_CORE
,
463 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
464 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
465 {"merom", PROCESSOR_CORE2
,
466 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
467 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
},
468 {"core2", PROCESSOR_CORE2
,
469 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
470 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
},
472 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
},
473 {"k6_2", PROCESSOR_K6
,
474 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
475 {"athlon", PROCESSOR_ATHLON
,
476 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
477 |CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
478 {"sledgehammer", PROCESSOR_K8
,
479 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
480 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
481 {"opteron", PROCESSOR_K8
,
482 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
483 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
485 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
486 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
487 {"amdfam10", PROCESSOR_AMDFAM10
,
488 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuSledgehammer
489 |CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSE4a
491 {".mmx", PROCESSOR_UNKNOWN
,
493 {".sse", PROCESSOR_UNKNOWN
,
494 CpuMMX
|CpuMMX2
|CpuSSE
},
495 {".sse2", PROCESSOR_UNKNOWN
,
496 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
497 {".sse3", PROCESSOR_UNKNOWN
,
498 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
499 {".ssse3", PROCESSOR_UNKNOWN
,
500 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
},
501 {".3dnow", PROCESSOR_UNKNOWN
,
503 {".3dnowa", PROCESSOR_UNKNOWN
,
504 CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
505 {".padlock", PROCESSOR_UNKNOWN
,
507 {".pacifica", PROCESSOR_UNKNOWN
,
509 {".svme", PROCESSOR_UNKNOWN
,
511 {".sse4a", PROCESSOR_UNKNOWN
,
512 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSE4a
},
513 {".abm", PROCESSOR_UNKNOWN
,
517 const pseudo_typeS md_pseudo_table
[] =
519 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
520 {"align", s_align_bytes
, 0},
522 {"align", s_align_ptwo
, 0},
524 {"arch", set_cpu_arch
, 0},
528 {"ffloat", float_cons
, 'f'},
529 {"dfloat", float_cons
, 'd'},
530 {"tfloat", float_cons
, 'x'},
532 {"slong", signed_cons
, 4},
533 {"noopt", s_ignore
, 0},
534 {"optim", s_ignore
, 0},
535 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
536 {"code16", set_code_flag
, CODE_16BIT
},
537 {"code32", set_code_flag
, CODE_32BIT
},
538 {"code64", set_code_flag
, CODE_64BIT
},
539 {"intel_syntax", set_intel_syntax
, 1},
540 {"att_syntax", set_intel_syntax
, 0},
541 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
542 {"largecomm", handle_large_common
, 0},
544 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
545 {"loc", dwarf2_directive_loc
, 0},
546 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
549 {"secrel32", pe_directive_secrel
, 0},
554 /* For interface with expression (). */
555 extern char *input_line_pointer
;
557 /* Hash table for instruction mnemonic lookup. */
558 static struct hash_control
*op_hash
;
560 /* Hash table for register lookup. */
561 static struct hash_control
*reg_hash
;
564 i386_align_code (fragS
*fragP
, int count
)
566 /* Various efficient no-op patterns for aligning code labels.
567 Note: Don't try to assemble the instructions in the comments.
568 0L and 0w are not legal. */
569 static const char f32_1
[] =
571 static const char f32_2
[] =
572 {0x66,0x90}; /* xchg %ax,%ax */
573 static const char f32_3
[] =
574 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
575 static const char f32_4
[] =
576 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
577 static const char f32_5
[] =
579 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
580 static const char f32_6
[] =
581 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
582 static const char f32_7
[] =
583 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
584 static const char f32_8
[] =
586 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
587 static const char f32_9
[] =
588 {0x89,0xf6, /* movl %esi,%esi */
589 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
590 static const char f32_10
[] =
591 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
592 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
593 static const char f32_11
[] =
594 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
595 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
596 static const char f32_12
[] =
597 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
598 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
599 static const char f32_13
[] =
600 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
601 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
602 static const char f32_14
[] =
603 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
604 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
605 static const char f32_15
[] =
606 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
607 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
608 static const char f16_3
[] =
609 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
610 static const char f16_4
[] =
611 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
612 static const char f16_5
[] =
614 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
615 static const char f16_6
[] =
616 {0x89,0xf6, /* mov %si,%si */
617 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
618 static const char f16_7
[] =
619 {0x8d,0x74,0x00, /* lea 0(%si),%si */
620 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
621 static const char f16_8
[] =
622 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
623 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
624 static const char *const f32_patt
[] = {
625 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
626 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
628 static const char *const f16_patt
[] = {
629 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
630 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
633 static const char alt_3
[] =
635 /* nopl 0(%[re]ax) */
636 static const char alt_4
[] =
637 {0x0f,0x1f,0x40,0x00};
638 /* nopl 0(%[re]ax,%[re]ax,1) */
639 static const char alt_5
[] =
640 {0x0f,0x1f,0x44,0x00,0x00};
641 /* nopw 0(%[re]ax,%[re]ax,1) */
642 static const char alt_6
[] =
643 {0x66,0x0f,0x1f,0x44,0x00,0x00};
644 /* nopl 0L(%[re]ax) */
645 static const char alt_7
[] =
646 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
647 /* nopl 0L(%[re]ax,%[re]ax,1) */
648 static const char alt_8
[] =
649 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
650 /* nopw 0L(%[re]ax,%[re]ax,1) */
651 static const char alt_9
[] =
652 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
653 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
654 static const char alt_10
[] =
655 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
657 nopw %cs:0L(%[re]ax,%[re]ax,1) */
658 static const char alt_long_11
[] =
660 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
663 nopw %cs:0L(%[re]ax,%[re]ax,1) */
664 static const char alt_long_12
[] =
667 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
671 nopw %cs:0L(%[re]ax,%[re]ax,1) */
672 static const char alt_long_13
[] =
676 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
681 nopw %cs:0L(%[re]ax,%[re]ax,1) */
682 static const char alt_long_14
[] =
687 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
693 nopw %cs:0L(%[re]ax,%[re]ax,1) */
694 static const char alt_long_15
[] =
700 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
701 /* nopl 0(%[re]ax,%[re]ax,1)
702 nopw 0(%[re]ax,%[re]ax,1) */
703 static const char alt_short_11
[] =
704 {0x0f,0x1f,0x44,0x00,0x00,
705 0x66,0x0f,0x1f,0x44,0x00,0x00};
706 /* nopw 0(%[re]ax,%[re]ax,1)
707 nopw 0(%[re]ax,%[re]ax,1) */
708 static const char alt_short_12
[] =
709 {0x66,0x0f,0x1f,0x44,0x00,0x00,
710 0x66,0x0f,0x1f,0x44,0x00,0x00};
711 /* nopw 0(%[re]ax,%[re]ax,1)
713 static const char alt_short_13
[] =
714 {0x66,0x0f,0x1f,0x44,0x00,0x00,
715 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
718 static const char alt_short_14
[] =
719 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
720 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
722 nopl 0L(%[re]ax,%[re]ax,1) */
723 static const char alt_short_15
[] =
724 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
725 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
726 static const char *const alt_short_patt
[] = {
727 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
728 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
729 alt_short_14
, alt_short_15
731 static const char *const alt_long_patt
[] = {
732 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
733 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
734 alt_long_14
, alt_long_15
737 if (count
<= 0 || count
> 15)
740 /* We need to decide which NOP sequence to use for 32bit and
741 64bit. When -mtune= is used:
743 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
744 f32_patt will be used.
745 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with
746 0x66 prefix will be used.
747 3. For PROCESSOR_CORE2, alt_long_patt will be used.
748 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
749 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
750 and PROCESSOR_GENERIC64, alt_short_patt will be used.
752 When -mtune= isn't used, alt_short_patt will be used if
753 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
755 When -march= or .arch is used, we can't use anything beyond
756 cpu_arch_isa_flags. */
758 if (flag_code
== CODE_16BIT
)
760 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
761 f16_patt
[count
- 1], count
);
763 /* Adjust jump offset. */
764 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
766 else if (flag_code
== CODE_64BIT
&& cpu_arch_tune
== PROCESSOR_K8
)
769 int nnops
= (count
+ 3) / 4;
770 int len
= count
/ nnops
;
771 int remains
= count
- nnops
* len
;
774 /* The recommended way to pad 64bit code is to use NOPs preceded
775 by maximally four 0x66 prefixes. Balance the size of nops. */
776 for (i
= 0; i
< remains
; i
++)
778 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
779 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
782 for (; i
< nnops
; i
++)
784 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
785 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
791 const char *const *patt
= NULL
;
793 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
795 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
796 switch (cpu_arch_tune
)
798 case PROCESSOR_UNKNOWN
:
799 /* We use cpu_arch_isa_flags to check if we SHOULD
800 optimize for Cpu686. */
801 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
802 patt
= alt_short_patt
;
806 case PROCESSOR_CORE2
:
807 patt
= alt_long_patt
;
809 case PROCESSOR_PENTIUMPRO
:
810 case PROCESSOR_PENTIUM4
:
811 case PROCESSOR_NOCONA
:
814 case PROCESSOR_ATHLON
:
816 case PROCESSOR_GENERIC64
:
817 case PROCESSOR_AMDFAM10
:
818 patt
= alt_short_patt
;
821 case PROCESSOR_PENTIUM
:
822 case PROCESSOR_GENERIC32
:
829 switch (cpu_arch_tune
)
831 case PROCESSOR_UNKNOWN
:
832 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
833 PROCESSOR_UNKNOWN. */
838 case PROCESSOR_PENTIUM
:
839 case PROCESSOR_PENTIUMPRO
:
840 case PROCESSOR_PENTIUM4
:
841 case PROCESSOR_NOCONA
:
844 case PROCESSOR_ATHLON
:
846 case PROCESSOR_AMDFAM10
:
847 case PROCESSOR_GENERIC32
:
848 /* We use cpu_arch_isa_flags to check if we CAN optimize
850 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
851 patt
= alt_short_patt
;
855 case PROCESSOR_CORE2
:
856 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
857 patt
= alt_long_patt
;
861 case PROCESSOR_GENERIC64
:
862 patt
= alt_short_patt
;
867 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
868 patt
[count
- 1], count
);
870 fragP
->fr_var
= count
;
873 static INLINE
unsigned int
874 mode_from_disp_size (unsigned int t
)
876 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
880 fits_in_signed_byte (offsetT num
)
882 return (num
>= -128) && (num
<= 127);
886 fits_in_unsigned_byte (offsetT num
)
888 return (num
& 0xff) == num
;
892 fits_in_unsigned_word (offsetT num
)
894 return (num
& 0xffff) == num
;
898 fits_in_signed_word (offsetT num
)
900 return (-32768 <= num
) && (num
<= 32767);
904 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
909 return (!(((offsetT
) -1 << 31) & num
)
910 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
912 } /* fits_in_signed_long() */
915 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
920 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
922 } /* fits_in_unsigned_long() */
925 smallest_imm_type (offsetT num
)
927 if (cpu_arch_flags
!= (Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
929 /* This code is disabled on the 486 because all the Imm1 forms
930 in the opcode table are slower on the i486. They're the
931 versions with the implicitly specified single-position
932 displacement, which has another syntax if you really want to
935 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
937 return (fits_in_signed_byte (num
)
938 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
939 : fits_in_unsigned_byte (num
)
940 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
941 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
942 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
943 : fits_in_signed_long (num
)
944 ? (Imm32
| Imm32S
| Imm64
)
945 : fits_in_unsigned_long (num
)
951 offset_in_range (offsetT val
, int size
)
957 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
958 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
959 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
961 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
966 /* If BFD64, sign extend val. */
967 if (!use_rela_relocations
)
968 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
969 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
971 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
973 char buf1
[40], buf2
[40];
975 sprint_value (buf1
, val
);
976 sprint_value (buf2
, val
& mask
);
977 as_warn (_("%s shortened to %s"), buf1
, buf2
);
982 /* Returns 0 if attempting to add a prefix where one from the same
983 class already exists, 1 if non rep/repne added, 2 if rep/repne
986 add_prefix (unsigned int prefix
)
991 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
992 && flag_code
== CODE_64BIT
)
994 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
995 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
996 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1007 case CS_PREFIX_OPCODE
:
1008 case DS_PREFIX_OPCODE
:
1009 case ES_PREFIX_OPCODE
:
1010 case FS_PREFIX_OPCODE
:
1011 case GS_PREFIX_OPCODE
:
1012 case SS_PREFIX_OPCODE
:
1016 case REPNE_PREFIX_OPCODE
:
1017 case REPE_PREFIX_OPCODE
:
1020 case LOCK_PREFIX_OPCODE
:
1028 case ADDR_PREFIX_OPCODE
:
1032 case DATA_PREFIX_OPCODE
:
1036 if (i
.prefix
[q
] != 0)
1044 i
.prefix
[q
] |= prefix
;
1047 as_bad (_("same type of prefix used twice"));
1053 set_code_flag (int value
)
1056 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
1057 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
1058 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
1060 as_bad (_("64bit mode not supported on this CPU."));
1062 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
1064 as_bad (_("32bit mode not supported on this CPU."));
1066 stackop_size
= '\0';
1070 set_16bit_gcc_code_flag (int new_code_flag
)
1072 flag_code
= new_code_flag
;
1073 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
1074 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
1075 stackop_size
= LONG_MNEM_SUFFIX
;
1079 set_intel_syntax (int syntax_flag
)
1081 /* Find out if register prefixing is specified. */
1082 int ask_naked_reg
= 0;
1085 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1087 char *string
= input_line_pointer
;
1088 int e
= get_symbol_end ();
1090 if (strcmp (string
, "prefix") == 0)
1092 else if (strcmp (string
, "noprefix") == 0)
1095 as_bad (_("bad argument to syntax directive."));
1096 *input_line_pointer
= e
;
1098 demand_empty_rest_of_line ();
1100 intel_syntax
= syntax_flag
;
1102 if (ask_naked_reg
== 0)
1103 allow_naked_reg
= (intel_syntax
1104 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1106 allow_naked_reg
= (ask_naked_reg
< 0);
1108 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1109 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1110 register_prefix
= allow_naked_reg
? "" : "%";
1114 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1118 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1120 char *string
= input_line_pointer
;
1121 int e
= get_symbol_end ();
1124 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1126 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1130 cpu_arch_name
= cpu_arch
[i
].name
;
1131 cpu_sub_arch_name
= NULL
;
1132 cpu_arch_flags
= (cpu_arch
[i
].flags
1133 | (flag_code
== CODE_64BIT
1134 ? Cpu64
: CpuNo64
));
1135 cpu_arch_isa
= cpu_arch
[i
].type
;
1136 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1137 if (!cpu_arch_tune_set
)
1139 cpu_arch_tune
= cpu_arch_isa
;
1140 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1144 if ((cpu_arch_flags
| cpu_arch
[i
].flags
) != cpu_arch_flags
)
1146 cpu_sub_arch_name
= cpu_arch
[i
].name
;
1147 cpu_arch_flags
|= cpu_arch
[i
].flags
;
1149 *input_line_pointer
= e
;
1150 demand_empty_rest_of_line ();
1154 if (i
>= ARRAY_SIZE (cpu_arch
))
1155 as_bad (_("no such architecture: `%s'"), string
);
1157 *input_line_pointer
= e
;
1160 as_bad (_("missing cpu architecture"));
1162 no_cond_jump_promotion
= 0;
1163 if (*input_line_pointer
== ','
1164 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
1166 char *string
= ++input_line_pointer
;
1167 int e
= get_symbol_end ();
1169 if (strcmp (string
, "nojumps") == 0)
1170 no_cond_jump_promotion
= 1;
1171 else if (strcmp (string
, "jumps") == 0)
1174 as_bad (_("no such architecture modifier: `%s'"), string
);
1176 *input_line_pointer
= e
;
1179 demand_empty_rest_of_line ();
1185 if (!strcmp (default_arch
, "x86_64"))
1186 return bfd_mach_x86_64
;
1187 else if (!strcmp (default_arch
, "i386"))
1188 return bfd_mach_i386_i386
;
1190 as_fatal (_("Unknown architecture"));
1196 const char *hash_err
;
1198 /* Initialize op_hash hash table. */
1199 op_hash
= hash_new ();
1202 const template *optab
;
1203 templates
*core_optab
;
1205 /* Setup for loop. */
1207 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1208 core_optab
->start
= optab
;
1213 if (optab
->name
== NULL
1214 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
1216 /* different name --> ship out current template list;
1217 add to hash table; & begin anew. */
1218 core_optab
->end
= optab
;
1219 hash_err
= hash_insert (op_hash
,
1224 as_fatal (_("Internal Error: Can't hash %s: %s"),
1228 if (optab
->name
== NULL
)
1230 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1231 core_optab
->start
= optab
;
1236 /* Initialize reg_hash hash table. */
1237 reg_hash
= hash_new ();
1239 const reg_entry
*regtab
;
1240 unsigned int regtab_size
= i386_regtab_size
;
1242 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
1244 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
1246 as_fatal (_("Internal Error: Can't hash %s: %s"),
1252 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1257 for (c
= 0; c
< 256; c
++)
1262 mnemonic_chars
[c
] = c
;
1263 register_chars
[c
] = c
;
1264 operand_chars
[c
] = c
;
1266 else if (ISLOWER (c
))
1268 mnemonic_chars
[c
] = c
;
1269 register_chars
[c
] = c
;
1270 operand_chars
[c
] = c
;
1272 else if (ISUPPER (c
))
1274 mnemonic_chars
[c
] = TOLOWER (c
);
1275 register_chars
[c
] = mnemonic_chars
[c
];
1276 operand_chars
[c
] = c
;
1279 if (ISALPHA (c
) || ISDIGIT (c
))
1280 identifier_chars
[c
] = c
;
1283 identifier_chars
[c
] = c
;
1284 operand_chars
[c
] = c
;
1289 identifier_chars
['@'] = '@';
1292 identifier_chars
['?'] = '?';
1293 operand_chars
['?'] = '?';
1295 digit_chars
['-'] = '-';
1296 mnemonic_chars
['-'] = '-';
1297 mnemonic_chars
['.'] = '.';
1298 identifier_chars
['_'] = '_';
1299 identifier_chars
['.'] = '.';
1301 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1302 operand_chars
[(unsigned char) *p
] = *p
;
1305 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1308 record_alignment (text_section
, 2);
1309 record_alignment (data_section
, 2);
1310 record_alignment (bss_section
, 2);
1314 if (flag_code
== CODE_64BIT
)
1316 x86_dwarf2_return_column
= 16;
1317 x86_cie_data_alignment
= -8;
1321 x86_dwarf2_return_column
= 8;
1322 x86_cie_data_alignment
= -4;
1327 i386_print_statistics (FILE *file
)
1329 hash_print_statistics (file
, "i386 opcode", op_hash
);
1330 hash_print_statistics (file
, "i386 register", reg_hash
);
1335 /* Debugging routines for md_assemble. */
1336 static void pte (template *);
1337 static void pt (unsigned int);
1338 static void pe (expressionS
*);
1339 static void ps (symbolS
*);
1342 pi (char *line
, i386_insn
*x
)
1346 fprintf (stdout
, "%s: template ", line
);
1348 fprintf (stdout
, " address: base %s index %s scale %x\n",
1349 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1350 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1351 x
->log2_scale_factor
);
1352 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1353 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1354 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1355 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1356 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1357 (x
->rex
& REX_W
) != 0,
1358 (x
->rex
& REX_R
) != 0,
1359 (x
->rex
& REX_X
) != 0,
1360 (x
->rex
& REX_B
) != 0);
1361 for (i
= 0; i
< x
->operands
; i
++)
1363 fprintf (stdout
, " #%d: ", i
+ 1);
1365 fprintf (stdout
, "\n");
1367 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1368 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1369 if (x
->types
[i
] & Imm
)
1371 if (x
->types
[i
] & Disp
)
1372 pe (x
->op
[i
].disps
);
1380 fprintf (stdout
, " %d operands ", t
->operands
);
1381 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1382 if (t
->extension_opcode
!= None
)
1383 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1384 if (t
->opcode_modifier
& D
)
1385 fprintf (stdout
, "D");
1386 if (t
->opcode_modifier
& W
)
1387 fprintf (stdout
, "W");
1388 fprintf (stdout
, "\n");
1389 for (i
= 0; i
< t
->operands
; i
++)
1391 fprintf (stdout
, " #%d type ", i
+ 1);
1392 pt (t
->operand_types
[i
]);
1393 fprintf (stdout
, "\n");
1400 fprintf (stdout
, " operation %d\n", e
->X_op
);
1401 fprintf (stdout
, " add_number %ld (%lx)\n",
1402 (long) e
->X_add_number
, (long) e
->X_add_number
);
1403 if (e
->X_add_symbol
)
1405 fprintf (stdout
, " add_symbol ");
1406 ps (e
->X_add_symbol
);
1407 fprintf (stdout
, "\n");
1411 fprintf (stdout
, " op_symbol ");
1412 ps (e
->X_op_symbol
);
1413 fprintf (stdout
, "\n");
1420 fprintf (stdout
, "%s type %s%s",
1422 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1423 segment_name (S_GET_SEGMENT (s
)));
1426 static struct type_name
1431 const type_names
[] =
1444 { BaseIndex
, "BaseIndex" },
1448 { Disp32S
, "d32s" },
1450 { InOutPortReg
, "InOutPortReg" },
1451 { ShiftCount
, "ShiftCount" },
1452 { Control
, "control reg" },
1453 { Test
, "test reg" },
1454 { Debug
, "debug reg" },
1455 { FloatReg
, "FReg" },
1456 { FloatAcc
, "FAcc" },
1460 { JumpAbsolute
, "Jump Absolute" },
1471 const struct type_name
*ty
;
1473 for (ty
= type_names
; ty
->mask
; ty
++)
1475 fprintf (stdout
, "%s, ", ty
->tname
);
1479 #endif /* DEBUG386 */
1481 static bfd_reloc_code_real_type
1482 reloc (unsigned int size
,
1485 bfd_reloc_code_real_type other
)
1487 if (other
!= NO_RELOC
)
1489 reloc_howto_type
*reloc
;
1494 case BFD_RELOC_X86_64_GOT32
:
1495 return BFD_RELOC_X86_64_GOT64
;
1497 case BFD_RELOC_X86_64_PLTOFF64
:
1498 return BFD_RELOC_X86_64_PLTOFF64
;
1500 case BFD_RELOC_X86_64_GOTPC32
:
1501 other
= BFD_RELOC_X86_64_GOTPC64
;
1503 case BFD_RELOC_X86_64_GOTPCREL
:
1504 other
= BFD_RELOC_X86_64_GOTPCREL64
;
1506 case BFD_RELOC_X86_64_TPOFF32
:
1507 other
= BFD_RELOC_X86_64_TPOFF64
;
1509 case BFD_RELOC_X86_64_DTPOFF32
:
1510 other
= BFD_RELOC_X86_64_DTPOFF64
;
1516 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1517 if (size
== 4 && flag_code
!= CODE_64BIT
)
1520 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
1522 as_bad (_("unknown relocation (%u)"), other
);
1523 else if (size
!= bfd_get_reloc_size (reloc
))
1524 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1525 bfd_get_reloc_size (reloc
),
1527 else if (pcrel
&& !reloc
->pc_relative
)
1528 as_bad (_("non-pc-relative relocation for pc-relative field"));
1529 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
1531 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
1533 as_bad (_("relocated field and relocation type differ in signedness"));
1542 as_bad (_("there are no unsigned pc-relative relocations"));
1545 case 1: return BFD_RELOC_8_PCREL
;
1546 case 2: return BFD_RELOC_16_PCREL
;
1547 case 4: return BFD_RELOC_32_PCREL
;
1548 case 8: return BFD_RELOC_64_PCREL
;
1550 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
1557 case 4: return BFD_RELOC_X86_64_32S
;
1562 case 1: return BFD_RELOC_8
;
1563 case 2: return BFD_RELOC_16
;
1564 case 4: return BFD_RELOC_32
;
1565 case 8: return BFD_RELOC_64
;
1567 as_bad (_("cannot do %s %u byte relocation"),
1568 sign
> 0 ? "signed" : "unsigned", size
);
1572 return BFD_RELOC_NONE
;
1575 /* Here we decide which fixups can be adjusted to make them relative to
1576 the beginning of the section instead of the symbol. Basically we need
1577 to make sure that the dynamic relocations are done correctly, so in
1578 some cases we force the original symbol to be used. */
1581 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
1583 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1587 /* Don't adjust pc-relative references to merge sections in 64-bit
1589 if (use_rela_relocations
1590 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1594 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1595 and changed later by validate_fix. */
1596 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
1597 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
1600 /* adjust_reloc_syms doesn't know about the GOT. */
1601 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1602 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1603 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1604 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1605 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1606 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1607 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1608 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1609 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1610 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1611 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1612 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
1613 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
1614 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1615 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1616 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1617 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1618 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1619 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1620 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
1621 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1622 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1623 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
1624 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
1625 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
1626 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
1627 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1628 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1635 intel_float_operand (const char *mnemonic
)
1637 /* Note that the value returned is meaningful only for opcodes with (memory)
1638 operands, hence the code here is free to improperly handle opcodes that
1639 have no operands (for better performance and smaller code). */
1641 if (mnemonic
[0] != 'f')
1642 return 0; /* non-math */
1644 switch (mnemonic
[1])
1646 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1647 the fs segment override prefix not currently handled because no
1648 call path can make opcodes without operands get here */
1650 return 2 /* integer op */;
1652 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
1653 return 3; /* fldcw/fldenv */
1656 if (mnemonic
[2] != 'o' /* fnop */)
1657 return 3; /* non-waiting control op */
1660 if (mnemonic
[2] == 's')
1661 return 3; /* frstor/frstpm */
1664 if (mnemonic
[2] == 'a')
1665 return 3; /* fsave */
1666 if (mnemonic
[2] == 't')
1668 switch (mnemonic
[3])
1670 case 'c': /* fstcw */
1671 case 'd': /* fstdw */
1672 case 'e': /* fstenv */
1673 case 's': /* fsts[gw] */
1679 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
1680 return 0; /* fxsave/fxrstor are not really math ops */
1687 /* This is the guts of the machine-dependent assembler. LINE points to a
1688 machine dependent instruction. This function is supposed to emit
1689 the frags/bytes it assembles to. */
1696 char mnemonic
[MAX_MNEM_SIZE
];
1698 /* Initialize globals. */
1699 memset (&i
, '\0', sizeof (i
));
1700 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1701 i
.reloc
[j
] = NO_RELOC
;
1702 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1703 memset (im_expressions
, '\0', sizeof (im_expressions
));
1704 save_stack_p
= save_stack
;
1706 /* First parse an instruction mnemonic & call i386_operand for the operands.
1707 We assume that the scrubber has arranged it so that line[0] is the valid
1708 start of a (possibly prefixed) mnemonic. */
1710 line
= parse_insn (line
, mnemonic
);
1714 line
= parse_operands (line
, mnemonic
);
1718 /* The order of the immediates should be reversed
1719 for 2 immediates extrq and insertq instructions */
1720 if ((i
.imm_operands
== 2)
1721 && ((strcmp (mnemonic
, "extrq") == 0)
1722 || (strcmp (mnemonic
, "insertq") == 0)))
1724 swap_2_operands (0, 1);
1725 /* "extrq" and insertq" are the only two instructions whose operands
1726 have to be reversed even though they have two immediate operands.
1732 /* Now we've parsed the mnemonic into a set of templates, and have the
1733 operands at hand. */
1735 /* All intel opcodes have reversed operands except for "bound" and
1736 "enter". We also don't reverse intersegment "jmp" and "call"
1737 instructions with 2 immediate operands so that the immediate segment
1738 precedes the offset, as it does when in AT&T mode. */
1741 && (strcmp (mnemonic
, "bound") != 0)
1742 && (strcmp (mnemonic
, "invlpga") != 0)
1743 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1749 /* Don't optimize displacement for movabs since it only takes 64bit
1752 && (flag_code
!= CODE_64BIT
1753 || strcmp (mnemonic
, "movabs") != 0))
1756 /* Next, we find a template that matches the given insn,
1757 making sure the overlap of the given operands types is consistent
1758 with the template operand types. */
1760 if (!match_template ())
1765 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1767 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1768 i
.tm
.base_opcode
^= Opcode_FloatR
;
1770 /* Zap movzx and movsx suffix. The suffix may have been set from
1771 "word ptr" or "byte ptr" on the source operand, but we'll use
1772 the suffix later to choose the destination register. */
1773 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1775 if (i
.reg_operands
< 2
1777 && (~i
.tm
.opcode_modifier
1784 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
1790 if (i
.tm
.opcode_modifier
& FWait
)
1791 if (!add_prefix (FWAIT_OPCODE
))
1794 /* Check string instruction segment overrides. */
1795 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1797 if (!check_string ())
1801 if (!process_suffix ())
1804 /* Make still unresolved immediate matches conform to size of immediate
1805 given in i.suffix. */
1806 if (!finalize_imm ())
1809 if (i
.types
[0] & Imm1
)
1810 i
.imm_operands
= 0; /* kludge for shift insns. */
1811 if (i
.types
[0] & ImplicitRegister
)
1813 if (i
.types
[1] & ImplicitRegister
)
1815 if (i
.types
[2] & ImplicitRegister
)
1818 if (i
.tm
.opcode_modifier
& ImmExt
)
1822 if ((i
.tm
.cpu_flags
& CpuSSE3
) && i
.operands
> 0)
1824 /* Streaming SIMD extensions 3 Instructions have the fixed
1825 operands with an opcode suffix which is coded in the same
1826 place as an 8-bit immediate field would be. Here we check
1827 those operands and remove them afterwards. */
1830 for (x
= 0; x
< i
.operands
; x
++)
1831 if (i
.op
[x
].regs
->reg_num
!= x
)
1832 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1833 i
.op
[x
].regs
->reg_name
, x
+ 1, i
.tm
.name
);
1837 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1838 opcode suffix which is coded in the same place as an 8-bit
1839 immediate field would be. Here we fake an 8-bit immediate
1840 operand from the opcode suffix stored in tm.extension_opcode. */
1842 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1844 exp
= &im_expressions
[i
.imm_operands
++];
1845 i
.op
[i
.operands
].imms
= exp
;
1846 i
.types
[i
.operands
++] = Imm8
;
1847 exp
->X_op
= O_constant
;
1848 exp
->X_add_number
= i
.tm
.extension_opcode
;
1849 i
.tm
.extension_opcode
= None
;
1852 /* For insns with operands there are more diddles to do to the opcode. */
1855 if (!process_operands ())
1858 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1860 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1861 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1864 /* Handle conversion of 'int $3' --> special int3 insn. */
1865 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1867 i
.tm
.base_opcode
= INT3_OPCODE
;
1871 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1872 && i
.op
[0].disps
->X_op
== O_constant
)
1874 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1875 the absolute address given by the constant. Since ix86 jumps and
1876 calls are pc relative, we need to generate a reloc. */
1877 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1878 i
.op
[0].disps
->X_op
= O_symbol
;
1881 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1884 /* For 8 bit registers we need an empty rex prefix. Also if the
1885 instruction already has a prefix, we need to convert old
1886 registers to new ones. */
1888 if (((i
.types
[0] & Reg8
) != 0
1889 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1890 || ((i
.types
[1] & Reg8
) != 0
1891 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1892 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1897 i
.rex
|= REX_OPCODE
;
1898 for (x
= 0; x
< 2; x
++)
1900 /* Look for 8 bit operand that uses old registers. */
1901 if ((i
.types
[x
] & Reg8
) != 0
1902 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1904 /* In case it is "hi" register, give up. */
1905 if (i
.op
[x
].regs
->reg_num
> 3)
1906 as_bad (_("can't encode register '%%%s' in an "
1907 "instruction requiring REX prefix."),
1908 i
.op
[x
].regs
->reg_name
);
1910 /* Otherwise it is equivalent to the extended register.
1911 Since the encoding doesn't change this is merely
1912 cosmetic cleanup for debug output. */
1914 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1920 add_prefix (REX_OPCODE
| i
.rex
);
1922 /* We are ready to output the insn. */
1927 parse_insn (char *line
, char *mnemonic
)
1930 char *token_start
= l
;
1935 /* Non-zero if we found a prefix only acceptable with string insns. */
1936 const char *expecting_string_instruction
= NULL
;
1941 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1944 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1946 as_bad (_("no such instruction: `%s'"), token_start
);
1951 if (!is_space_char (*l
)
1952 && *l
!= END_OF_INSN
1954 || (*l
!= PREFIX_SEPARATOR
1957 as_bad (_("invalid character %s in mnemonic"),
1958 output_invalid (*l
));
1961 if (token_start
== l
)
1963 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
1964 as_bad (_("expecting prefix; got nothing"));
1966 as_bad (_("expecting mnemonic; got nothing"));
1970 /* Look up instruction (or prefix) via hash table. */
1971 current_templates
= hash_find (op_hash
, mnemonic
);
1973 if (*l
!= END_OF_INSN
1974 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1975 && current_templates
1976 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1978 if (current_templates
->start
->cpu_flags
1979 & (flag_code
!= CODE_64BIT
? Cpu64
: CpuNo64
))
1981 as_bad ((flag_code
!= CODE_64BIT
1982 ? _("`%s' is only supported in 64-bit mode")
1983 : _("`%s' is not supported in 64-bit mode")),
1984 current_templates
->start
->name
);
1987 /* If we are in 16-bit mode, do not allow addr16 or data16.
1988 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1989 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1990 && flag_code
!= CODE_64BIT
1991 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1992 ^ (flag_code
== CODE_16BIT
)))
1994 as_bad (_("redundant %s prefix"),
1995 current_templates
->start
->name
);
1998 /* Add prefix, checking for repeated prefixes. */
1999 switch (add_prefix (current_templates
->start
->base_opcode
))
2004 expecting_string_instruction
= current_templates
->start
->name
;
2007 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2014 if (!current_templates
)
2016 /* See if we can get a match by trimming off a suffix. */
2019 case WORD_MNEM_SUFFIX
:
2020 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
2021 i
.suffix
= SHORT_MNEM_SUFFIX
;
2023 case BYTE_MNEM_SUFFIX
:
2024 case QWORD_MNEM_SUFFIX
:
2025 i
.suffix
= mnem_p
[-1];
2027 current_templates
= hash_find (op_hash
, mnemonic
);
2029 case SHORT_MNEM_SUFFIX
:
2030 case LONG_MNEM_SUFFIX
:
2033 i
.suffix
= mnem_p
[-1];
2035 current_templates
= hash_find (op_hash
, mnemonic
);
2043 if (intel_float_operand (mnemonic
) == 1)
2044 i
.suffix
= SHORT_MNEM_SUFFIX
;
2046 i
.suffix
= LONG_MNEM_SUFFIX
;
2048 current_templates
= hash_find (op_hash
, mnemonic
);
2052 if (!current_templates
)
2054 as_bad (_("no such instruction: `%s'"), token_start
);
2059 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
2061 /* Check for a branch hint. We allow ",pt" and ",pn" for
2062 predict taken and predict not taken respectively.
2063 I'm not sure that branch hints actually do anything on loop
2064 and jcxz insns (JumpByte) for current Pentium4 chips. They
2065 may work in the future and it doesn't hurt to accept them
2067 if (l
[0] == ',' && l
[1] == 'p')
2071 if (!add_prefix (DS_PREFIX_OPCODE
))
2075 else if (l
[2] == 'n')
2077 if (!add_prefix (CS_PREFIX_OPCODE
))
2083 /* Any other comma loses. */
2086 as_bad (_("invalid character %s in mnemonic"),
2087 output_invalid (*l
));
2091 /* Check if instruction is supported on specified architecture. */
2093 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2095 if (!((t
->cpu_flags
& ~(Cpu64
| CpuNo64
))
2096 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
))))
2098 if (!(t
->cpu_flags
& (flag_code
== CODE_64BIT
? CpuNo64
: Cpu64
)))
2101 if (!(supported
& 2))
2103 as_bad (flag_code
== CODE_64BIT
2104 ? _("`%s' is not supported in 64-bit mode")
2105 : _("`%s' is only supported in 64-bit mode"),
2106 current_templates
->start
->name
);
2109 if (!(supported
& 1))
2111 as_warn (_("`%s' is not supported on `%s%s'"),
2112 current_templates
->start
->name
,
2114 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
2116 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
2118 as_warn (_("use .code16 to ensure correct addressing mode"));
2121 /* Check for rep/repne without a string instruction. */
2122 if (expecting_string_instruction
)
2124 static templates override
;
2126 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2127 if (t
->opcode_modifier
& IsString
)
2129 if (t
>= current_templates
->end
)
2131 as_bad (_("expecting string instruction after `%s'"),
2132 expecting_string_instruction
);
2135 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
2136 if (!(t
->opcode_modifier
& IsString
))
2139 current_templates
= &override
;
2146 parse_operands (char *l
, const char *mnemonic
)
2150 /* 1 if operand is pending after ','. */
2151 unsigned int expecting_operand
= 0;
2153 /* Non-zero if operand parens not balanced. */
2154 unsigned int paren_not_balanced
;
2156 while (*l
!= END_OF_INSN
)
2158 /* Skip optional white space before operand. */
2159 if (is_space_char (*l
))
2161 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
2163 as_bad (_("invalid character %s before operand %d"),
2164 output_invalid (*l
),
2168 token_start
= l
; /* after white space */
2169 paren_not_balanced
= 0;
2170 while (paren_not_balanced
|| *l
!= ',')
2172 if (*l
== END_OF_INSN
)
2174 if (paren_not_balanced
)
2177 as_bad (_("unbalanced parenthesis in operand %d."),
2180 as_bad (_("unbalanced brackets in operand %d."),
2185 break; /* we are done */
2187 else if (!is_operand_char (*l
) && !is_space_char (*l
))
2189 as_bad (_("invalid character %s in operand %d"),
2190 output_invalid (*l
),
2197 ++paren_not_balanced
;
2199 --paren_not_balanced
;
2204 ++paren_not_balanced
;
2206 --paren_not_balanced
;
2210 if (l
!= token_start
)
2211 { /* Yes, we've read in another operand. */
2212 unsigned int operand_ok
;
2213 this_operand
= i
.operands
++;
2214 if (i
.operands
> MAX_OPERANDS
)
2216 as_bad (_("spurious operands; (%d operands/instruction max)"),
2220 /* Now parse operand adding info to 'i' as we go along. */
2221 END_STRING_AND_SAVE (l
);
2225 i386_intel_operand (token_start
,
2226 intel_float_operand (mnemonic
));
2228 operand_ok
= i386_operand (token_start
);
2230 RESTORE_END_STRING (l
);
2236 if (expecting_operand
)
2238 expecting_operand_after_comma
:
2239 as_bad (_("expecting operand after ','; got nothing"));
2244 as_bad (_("expecting operand before ','; got nothing"));
2249 /* Now *l must be either ',' or END_OF_INSN. */
2252 if (*++l
== END_OF_INSN
)
2254 /* Just skip it, if it's \n complain. */
2255 goto expecting_operand_after_comma
;
2257 expecting_operand
= 1;
2264 swap_2_operands (int xchg1
, int xchg2
)
2266 union i386_op temp_op
;
2267 unsigned int temp_type
;
2268 enum bfd_reloc_code_real temp_reloc
;
2270 temp_type
= i
.types
[xchg2
];
2271 i
.types
[xchg2
] = i
.types
[xchg1
];
2272 i
.types
[xchg1
] = temp_type
;
2273 temp_op
= i
.op
[xchg2
];
2274 i
.op
[xchg2
] = i
.op
[xchg1
];
2275 i
.op
[xchg1
] = temp_op
;
2276 temp_reloc
= i
.reloc
[xchg2
];
2277 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
2278 i
.reloc
[xchg1
] = temp_reloc
;
2282 swap_operands (void)
2287 swap_2_operands (1, i
.operands
- 2);
2290 swap_2_operands (0, i
.operands
- 1);
2296 if (i
.mem_operands
== 2)
2298 const seg_entry
*temp_seg
;
2299 temp_seg
= i
.seg
[0];
2300 i
.seg
[0] = i
.seg
[1];
2301 i
.seg
[1] = temp_seg
;
2305 /* Try to ensure constant immediates are represented in the smallest
2310 char guess_suffix
= 0;
2314 guess_suffix
= i
.suffix
;
2315 else if (i
.reg_operands
)
2317 /* Figure out a suffix from the last register operand specified.
2318 We can't do this properly yet, ie. excluding InOutPortReg,
2319 but the following works for instructions with immediates.
2320 In any case, we can't set i.suffix yet. */
2321 for (op
= i
.operands
; --op
>= 0;)
2322 if (i
.types
[op
] & Reg
)
2324 if (i
.types
[op
] & Reg8
)
2325 guess_suffix
= BYTE_MNEM_SUFFIX
;
2326 else if (i
.types
[op
] & Reg16
)
2327 guess_suffix
= WORD_MNEM_SUFFIX
;
2328 else if (i
.types
[op
] & Reg32
)
2329 guess_suffix
= LONG_MNEM_SUFFIX
;
2330 else if (i
.types
[op
] & Reg64
)
2331 guess_suffix
= QWORD_MNEM_SUFFIX
;
2335 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
2336 guess_suffix
= WORD_MNEM_SUFFIX
;
2338 for (op
= i
.operands
; --op
>= 0;)
2339 if (i
.types
[op
] & Imm
)
2341 switch (i
.op
[op
].imms
->X_op
)
2344 /* If a suffix is given, this operand may be shortened. */
2345 switch (guess_suffix
)
2347 case LONG_MNEM_SUFFIX
:
2348 i
.types
[op
] |= Imm32
| Imm64
;
2350 case WORD_MNEM_SUFFIX
:
2351 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
2353 case BYTE_MNEM_SUFFIX
:
2354 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
2358 /* If this operand is at most 16 bits, convert it
2359 to a signed 16 bit number before trying to see
2360 whether it will fit in an even smaller size.
2361 This allows a 16-bit operand such as $0xffe0 to
2362 be recognised as within Imm8S range. */
2363 if ((i
.types
[op
] & Imm16
)
2364 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
2366 i
.op
[op
].imms
->X_add_number
=
2367 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2369 if ((i
.types
[op
] & Imm32
)
2370 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2373 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2374 ^ ((offsetT
) 1 << 31))
2375 - ((offsetT
) 1 << 31));
2377 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
2379 /* We must avoid matching of Imm32 templates when 64bit
2380 only immediate is available. */
2381 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2382 i
.types
[op
] &= ~Imm32
;
2389 /* Symbols and expressions. */
2391 /* Convert symbolic operand to proper sizes for matching, but don't
2392 prevent matching a set of insns that only supports sizes other
2393 than those matching the insn suffix. */
2395 unsigned int mask
, allowed
= 0;
2398 for (t
= current_templates
->start
;
2399 t
< current_templates
->end
;
2401 allowed
|= t
->operand_types
[op
];
2402 switch (guess_suffix
)
2404 case QWORD_MNEM_SUFFIX
:
2405 mask
= Imm64
| Imm32S
;
2407 case LONG_MNEM_SUFFIX
:
2410 case WORD_MNEM_SUFFIX
:
2413 case BYTE_MNEM_SUFFIX
:
2421 i
.types
[op
] &= mask
;
2428 /* Try to use the smallest displacement type too. */
2430 optimize_disp (void)
2434 for (op
= i
.operands
; --op
>= 0;)
2435 if (i
.types
[op
] & Disp
)
2437 if (i
.op
[op
].disps
->X_op
== O_constant
)
2439 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
2441 if ((i
.types
[op
] & Disp16
)
2442 && (disp
& ~(offsetT
) 0xffff) == 0)
2444 /* If this operand is at most 16 bits, convert
2445 to a signed 16 bit number and don't use 64bit
2447 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
2448 i
.types
[op
] &= ~Disp64
;
2450 if ((i
.types
[op
] & Disp32
)
2451 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
2453 /* If this operand is at most 32 bits, convert
2454 to a signed 32 bit number and don't use 64bit
2456 disp
&= (((offsetT
) 2 << 31) - 1);
2457 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
2458 i
.types
[op
] &= ~Disp64
;
2460 if (!disp
&& (i
.types
[op
] & BaseIndex
))
2462 i
.types
[op
] &= ~Disp
;
2466 else if (flag_code
== CODE_64BIT
)
2468 if (fits_in_signed_long (disp
))
2470 i
.types
[op
] &= ~Disp64
;
2471 i
.types
[op
] |= Disp32S
;
2473 if (fits_in_unsigned_long (disp
))
2474 i
.types
[op
] |= Disp32
;
2476 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
2477 && fits_in_signed_byte (disp
))
2478 i
.types
[op
] |= Disp8
;
2480 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
2481 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
2483 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
2484 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
2485 i
.types
[op
] &= ~Disp
;
2488 /* We only support 64bit displacement on constants. */
2489 i
.types
[op
] &= ~Disp64
;
2494 match_template (void)
2496 /* Points to template once we've found it. */
2498 unsigned int overlap0
, overlap1
, overlap2
, overlap3
;
2499 unsigned int found_reverse_match
;
2501 unsigned int operand_types
[MAX_OPERANDS
];
2502 int addr_prefix_disp
;
2505 #if MAX_OPERANDS != 4
2506 # error "MAX_OPERANDS must be 4."
2509 #define MATCH(overlap, given, template) \
2510 ((overlap & ~JumpAbsolute) \
2511 && (((given) & (BaseIndex | JumpAbsolute)) \
2512 == ((overlap) & (BaseIndex | JumpAbsolute))))
2514 /* If given types r0 and r1 are registers they must be of the same type
2515 unless the expected operand type register overlap is null.
2516 Note that Acc in a template matches every size of reg. */
2517 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2518 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2519 || ((g0) & Reg) == ((g1) & Reg) \
2520 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2526 found_reverse_match
= 0;
2527 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2528 operand_types
[j
] = 0;
2529 addr_prefix_disp
= -1;
2530 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
2532 : (i
.suffix
== WORD_MNEM_SUFFIX
2534 : (i
.suffix
== SHORT_MNEM_SUFFIX
2536 : (i
.suffix
== LONG_MNEM_SUFFIX
2538 : (i
.suffix
== QWORD_MNEM_SUFFIX
2540 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
2541 ? No_xSuf
: 0))))));
2543 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
2545 addr_prefix_disp
= -1;
2547 /* Must have right number of operands. */
2548 if (i
.operands
!= t
->operands
)
2551 /* Check the suffix, except for some instructions in intel mode. */
2552 if ((t
->opcode_modifier
& suffix_check
)
2554 && (t
->opcode_modifier
& IgnoreSize
)))
2557 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2558 operand_types
[j
] = t
->operand_types
[j
];
2560 /* In general, don't allow 64-bit operands in 32-bit mode. */
2561 if (i
.suffix
== QWORD_MNEM_SUFFIX
2562 && flag_code
!= CODE_64BIT
2564 ? (!(t
->opcode_modifier
& IgnoreSize
)
2565 && !intel_float_operand (t
->name
))
2566 : intel_float_operand (t
->name
) != 2)
2567 && (!(operand_types
[0] & (RegMMX
| RegXMM
))
2568 || !(operand_types
[t
->operands
> 1] & (RegMMX
| RegXMM
)))
2569 && (t
->base_opcode
!= 0x0fc7
2570 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
2573 /* Do not verify operands when there are none. */
2574 else if (!t
->operands
)
2576 if (t
->cpu_flags
& ~cpu_arch_flags
)
2578 /* We've found a match; break out of loop. */
2582 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2583 into Disp32/Disp16/Disp32 operand. */
2584 if (i
.prefix
[ADDR_PREFIX
] != 0)
2586 unsigned int DispOn
= 0, DispOff
= 0;
2604 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2606 /* There should be only one Disp operand. */
2607 if ((operand_types
[j
] & DispOff
))
2609 addr_prefix_disp
= j
;
2610 operand_types
[j
] |= DispOn
;
2611 operand_types
[j
] &= ~DispOff
;
2617 overlap0
= i
.types
[0] & operand_types
[0];
2618 switch (t
->operands
)
2621 if (!MATCH (overlap0
, i
.types
[0], operand_types
[0]))
2625 /* xchg %eax, %eax is a special case. It is an aliase for nop
2626 only in 32bit mode and we can use opcode 0x90. In 64bit
2627 mode, we can't use 0x90 for xchg %eax, %eax since it should
2628 zero-extend %eax to %rax. */
2629 if (flag_code
== CODE_64BIT
2630 && t
->base_opcode
== 0x90
2631 && i
.types
[0] == (Acc
| Reg32
)
2632 && i
.types
[1] == (Acc
| Reg32
))
2636 overlap1
= i
.types
[1] & operand_types
[1];
2637 if (!MATCH (overlap0
, i
.types
[0], operand_types
[0])
2638 || !MATCH (overlap1
, i
.types
[1], operand_types
[1])
2639 /* monitor in SSE3 is a very special case. The first
2640 register and the second register may have different
2642 || !((t
->base_opcode
== 0x0f01
2643 && t
->extension_opcode
== 0xc8)
2644 || CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2646 overlap1
, i
.types
[1],
2649 /* Check if other direction is valid ... */
2650 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2653 /* Try reversing direction of operands. */
2654 overlap0
= i
.types
[0] & operand_types
[1];
2655 overlap1
= i
.types
[1] & operand_types
[0];
2656 if (!MATCH (overlap0
, i
.types
[0], operand_types
[1])
2657 || !MATCH (overlap1
, i
.types
[1], operand_types
[0])
2658 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2660 overlap1
, i
.types
[1],
2663 /* Does not match either direction. */
2666 /* found_reverse_match holds which of D or FloatDR
2668 if ((t
->opcode_modifier
& D
))
2669 found_reverse_match
= Opcode_D
;
2670 else if ((t
->opcode_modifier
& FloatD
))
2671 found_reverse_match
= Opcode_FloatD
;
2673 found_reverse_match
= 0;
2674 if ((t
->opcode_modifier
& FloatR
))
2675 found_reverse_match
|= Opcode_FloatR
;
2679 /* Found a forward 2 operand match here. */
2680 switch (t
->operands
)
2683 overlap3
= i
.types
[3] & operand_types
[3];
2685 overlap2
= i
.types
[2] & operand_types
[2];
2689 switch (t
->operands
)
2692 if (!MATCH (overlap3
, i
.types
[3], operand_types
[3])
2693 || !CONSISTENT_REGISTER_MATCH (overlap2
,
2701 /* Here we make use of the fact that there are no
2702 reverse match 3 operand instructions, and all 3
2703 operand instructions only need to be checked for
2704 register consistency between operands 2 and 3. */
2705 if (!MATCH (overlap2
, i
.types
[2], operand_types
[2])
2706 || !CONSISTENT_REGISTER_MATCH (overlap1
,
2716 /* Found either forward/reverse 2, 3 or 4 operand match here:
2717 slip through to break. */
2719 if (t
->cpu_flags
& ~cpu_arch_flags
)
2721 found_reverse_match
= 0;
2724 /* We've found a match; break out of loop. */
2728 if (t
== current_templates
->end
)
2730 /* We found no match. */
2731 as_bad (_("suffix or operands invalid for `%s'"),
2732 current_templates
->start
->name
);
2736 if (!quiet_warnings
)
2739 && ((i
.types
[0] & JumpAbsolute
)
2740 != (operand_types
[0] & JumpAbsolute
)))
2742 as_warn (_("indirect %s without `*'"), t
->name
);
2745 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2746 == (IsPrefix
| IgnoreSize
))
2748 /* Warn them that a data or address size prefix doesn't
2749 affect assembly of the next line of code. */
2750 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2754 /* Copy the template we found. */
2757 if (addr_prefix_disp
!= -1)
2758 i
.tm
.operand_types
[addr_prefix_disp
]
2759 = operand_types
[addr_prefix_disp
];
2761 if (found_reverse_match
)
2763 /* If we found a reverse match we must alter the opcode
2764 direction bit. found_reverse_match holds bits to change
2765 (different for int & float insns). */
2767 i
.tm
.base_opcode
^= found_reverse_match
;
2769 i
.tm
.operand_types
[0] = operand_types
[1];
2770 i
.tm
.operand_types
[1] = operand_types
[0];
2779 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2780 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2782 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2784 as_bad (_("`%s' operand %d must use `%%es' segment"),
2789 /* There's only ever one segment override allowed per instruction.
2790 This instruction possibly has a legal segment override on the
2791 second operand, so copy the segment to where non-string
2792 instructions store it, allowing common code. */
2793 i
.seg
[0] = i
.seg
[1];
2795 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2797 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2799 as_bad (_("`%s' operand %d must use `%%es' segment"),
2809 process_suffix (void)
2811 /* If matched instruction specifies an explicit instruction mnemonic
2813 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2815 if (i
.tm
.opcode_modifier
& Size16
)
2816 i
.suffix
= WORD_MNEM_SUFFIX
;
2817 else if (i
.tm
.opcode_modifier
& Size64
)
2818 i
.suffix
= QWORD_MNEM_SUFFIX
;
2820 i
.suffix
= LONG_MNEM_SUFFIX
;
2822 else if (i
.reg_operands
)
2824 /* If there's no instruction mnemonic suffix we try to invent one
2825 based on register operands. */
2828 /* We take i.suffix from the last register operand specified,
2829 Destination register type is more significant than source
2833 for (op
= i
.operands
; --op
>= 0;)
2834 if ((i
.types
[op
] & Reg
)
2835 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2837 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2838 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2839 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2844 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2846 if (!check_byte_reg ())
2849 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2851 if (!check_long_reg ())
2854 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2856 if (!check_qword_reg ())
2859 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2861 if (!check_word_reg ())
2864 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2865 /* Do nothing if the instruction is going to ignore the prefix. */
2870 else if ((i
.tm
.opcode_modifier
& DefaultSize
)
2872 /* exclude fldenv/frstor/fsave/fstenv */
2873 && (i
.tm
.opcode_modifier
& No_sSuf
))
2875 i
.suffix
= stackop_size
;
2877 else if (intel_syntax
2879 && ((i
.tm
.operand_types
[0] & JumpAbsolute
)
2880 || (i
.tm
.opcode_modifier
& (JumpByte
|JumpInterSegment
))
2881 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
2882 && i
.tm
.extension_opcode
<= 3)))
2887 if (!(i
.tm
.opcode_modifier
& No_qSuf
))
2889 i
.suffix
= QWORD_MNEM_SUFFIX
;
2893 if (!(i
.tm
.opcode_modifier
& No_lSuf
))
2894 i
.suffix
= LONG_MNEM_SUFFIX
;
2897 if (!(i
.tm
.opcode_modifier
& No_wSuf
))
2898 i
.suffix
= WORD_MNEM_SUFFIX
;
2907 if (i
.tm
.opcode_modifier
& W
)
2909 as_bad (_("no instruction mnemonic suffix given and "
2910 "no register operands; can't size instruction"));
2916 unsigned int suffixes
= (~i
.tm
.opcode_modifier
2924 if ((i
.tm
.opcode_modifier
& W
)
2925 || ((suffixes
& (suffixes
- 1))
2926 && !(i
.tm
.opcode_modifier
& (DefaultSize
| IgnoreSize
))))
2928 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2934 /* Change the opcode based on the operand size given by i.suffix;
2935 We don't need to change things for byte insns. */
2937 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2939 /* It's not a byte, select word/dword operation. */
2940 if (i
.tm
.opcode_modifier
& W
)
2942 if (i
.tm
.opcode_modifier
& ShortForm
)
2943 i
.tm
.base_opcode
|= 8;
2945 i
.tm
.base_opcode
|= 1;
2948 /* Now select between word & dword operations via the operand
2949 size prefix, except for instructions that will ignore this
2951 if (i
.tm
.base_opcode
== 0x0f01 && i
.tm
.extension_opcode
== 0xc8)
2953 /* monitor in SSE3 is a very special case. The default size
2954 of AX is the size of mode. The address size override
2955 prefix will change the size of AX. */
2956 if (i
.op
->regs
[0].reg_type
&
2957 (flag_code
== CODE_32BIT
? Reg16
: Reg32
))
2958 if (!add_prefix (ADDR_PREFIX_OPCODE
))
2961 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
2962 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
2963 && !(i
.tm
.opcode_modifier
& (IgnoreSize
| FloatMF
))
2964 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2965 || (flag_code
== CODE_64BIT
2966 && (i
.tm
.opcode_modifier
& JumpByte
))))
2968 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2970 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2971 prefix
= ADDR_PREFIX_OPCODE
;
2973 if (!add_prefix (prefix
))
2977 /* Set mode64 for an operand. */
2978 if (i
.suffix
== QWORD_MNEM_SUFFIX
2979 && flag_code
== CODE_64BIT
2980 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2982 /* Special case for xchg %rax,%rax. It is NOP and doesn't
2985 || i
.types
[0] != (Acc
| Reg64
)
2986 || i
.types
[1] != (Acc
| Reg64
)
2987 || i
.tm
.base_opcode
!= 0x90)
2991 /* Size floating point instruction. */
2992 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2993 if (i
.tm
.opcode_modifier
& FloatMF
)
2994 i
.tm
.base_opcode
^= 4;
3001 check_byte_reg (void)
3005 for (op
= i
.operands
; --op
>= 0;)
3007 /* If this is an eight bit register, it's OK. If it's the 16 or
3008 32 bit version of an eight bit register, we will just use the
3009 low portion, and that's OK too. */
3010 if (i
.types
[op
] & Reg8
)
3013 /* movzx and movsx should not generate this warning. */
3015 && (i
.tm
.base_opcode
== 0xfb7
3016 || i
.tm
.base_opcode
== 0xfb6
3017 || i
.tm
.base_opcode
== 0x63
3018 || i
.tm
.base_opcode
== 0xfbe
3019 || i
.tm
.base_opcode
== 0xfbf))
3022 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4)
3024 /* Prohibit these changes in the 64bit mode, since the
3025 lowering is more complicated. */
3026 if (flag_code
== CODE_64BIT
3027 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
3029 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3030 register_prefix
, i
.op
[op
].regs
->reg_name
,
3034 #if REGISTER_WARNINGS
3036 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
3037 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3038 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
3039 ? REGNAM_AL
- REGNAM_AX
3040 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
3041 i
.op
[op
].regs
->reg_name
,
3046 /* Any other register is bad. */
3047 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
3049 | Control
| Debug
| Test
3050 | FloatReg
| FloatAcc
))
3052 as_bad (_("`%%%s' not allowed with `%s%c'"),
3053 i
.op
[op
].regs
->reg_name
,
3063 check_long_reg (void)
3067 for (op
= i
.operands
; --op
>= 0;)
3068 /* Reject eight bit registers, except where the template requires
3069 them. (eg. movzb) */
3070 if ((i
.types
[op
] & Reg8
) != 0
3071 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3073 as_bad (_("`%%%s' not allowed with `%s%c'"),
3074 i
.op
[op
].regs
->reg_name
,
3079 /* Warn if the e prefix on a general reg is missing. */
3080 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3081 && (i
.types
[op
] & Reg16
) != 0
3082 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3084 /* Prohibit these changes in the 64bit mode, since the
3085 lowering is more complicated. */
3086 if (flag_code
== CODE_64BIT
)
3088 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3089 register_prefix
, i
.op
[op
].regs
->reg_name
,
3093 #if REGISTER_WARNINGS
3095 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3096 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
3097 i
.op
[op
].regs
->reg_name
,
3101 /* Warn if the r prefix on a general reg is missing. */
3102 else if ((i
.types
[op
] & Reg64
) != 0
3103 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3105 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3106 register_prefix
, i
.op
[op
].regs
->reg_name
,
3114 check_qword_reg (void)
3118 for (op
= i
.operands
; --op
>= 0; )
3119 /* Reject eight bit registers, except where the template requires
3120 them. (eg. movzb) */
3121 if ((i
.types
[op
] & Reg8
) != 0
3122 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3124 as_bad (_("`%%%s' not allowed with `%s%c'"),
3125 i
.op
[op
].regs
->reg_name
,
3130 /* Warn if the e prefix on a general reg is missing. */
3131 else if (((i
.types
[op
] & Reg16
) != 0
3132 || (i
.types
[op
] & Reg32
) != 0)
3133 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3135 /* Prohibit these changes in the 64bit mode, since the
3136 lowering is more complicated. */
3137 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3138 register_prefix
, i
.op
[op
].regs
->reg_name
,
3146 check_word_reg (void)
3149 for (op
= i
.operands
; --op
>= 0;)
3150 /* Reject eight bit registers, except where the template requires
3151 them. (eg. movzb) */
3152 if ((i
.types
[op
] & Reg8
) != 0
3153 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3155 as_bad (_("`%%%s' not allowed with `%s%c'"),
3156 i
.op
[op
].regs
->reg_name
,
3161 /* Warn if the e prefix on a general reg is present. */
3162 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3163 && (i
.types
[op
] & Reg32
) != 0
3164 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
3166 /* Prohibit these changes in the 64bit mode, since the
3167 lowering is more complicated. */
3168 if (flag_code
== CODE_64BIT
)
3170 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3171 register_prefix
, i
.op
[op
].regs
->reg_name
,
3176 #if REGISTER_WARNINGS
3177 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3178 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
3179 i
.op
[op
].regs
->reg_name
,
3189 unsigned int overlap0
, overlap1
, overlap2
;
3191 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
3192 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
))
3193 && overlap0
!= Imm8
&& overlap0
!= Imm8S
3194 && overlap0
!= Imm16
&& overlap0
!= Imm32S
3195 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
3199 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
3201 : (i
.suffix
== WORD_MNEM_SUFFIX
3203 : (i
.suffix
== QWORD_MNEM_SUFFIX
3207 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
3208 || overlap0
== (Imm16
| Imm32
)
3209 || overlap0
== (Imm16
| Imm32S
))
3211 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
3214 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
3215 && overlap0
!= Imm16
&& overlap0
!= Imm32S
3216 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
3218 as_bad (_("no instruction mnemonic suffix given; "
3219 "can't determine immediate size"));
3223 i
.types
[0] = overlap0
;
3225 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
3226 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
| Imm64
))
3227 && overlap1
!= Imm8
&& overlap1
!= Imm8S
3228 && overlap1
!= Imm16
&& overlap1
!= Imm32S
3229 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
3233 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
3235 : (i
.suffix
== WORD_MNEM_SUFFIX
3237 : (i
.suffix
== QWORD_MNEM_SUFFIX
3241 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
3242 || overlap1
== (Imm16
| Imm32
)
3243 || overlap1
== (Imm16
| Imm32S
))
3245 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
3248 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
3249 && overlap1
!= Imm16
&& overlap1
!= Imm32S
3250 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
3252 as_bad (_("no instruction mnemonic suffix given; "
3253 "can't determine immediate size %x %c"),
3254 overlap1
, i
.suffix
);
3258 i
.types
[1] = overlap1
;
3260 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
3261 assert ((overlap2
& Imm
) == 0);
3262 i
.types
[2] = overlap2
;
3268 process_operands (void)
3270 /* Default segment register this instruction will use for memory
3271 accesses. 0 means unknown. This is only for optimizing out
3272 unnecessary segment overrides. */
3273 const seg_entry
*default_seg
= 0;
3275 /* The imul $imm, %reg instruction is converted into
3276 imul $imm, %reg, %reg, and the clr %reg instruction
3277 is converted into xor %reg, %reg. */
3278 if (i
.tm
.opcode_modifier
& regKludge
)
3280 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
3281 /* Pretend we saw the extra register operand. */
3282 assert (i
.reg_operands
== 1
3283 && i
.op
[first_reg_op
+ 1].regs
== 0);
3284 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
3285 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
3290 if (i
.tm
.opcode_modifier
& ShortForm
)
3292 if (i
.types
[0] & (SReg2
| SReg3
))
3294 if (i
.tm
.base_opcode
== POP_SEG_SHORT
3295 && i
.op
[0].regs
->reg_num
== 1)
3297 as_bad (_("you can't `pop %%cs'"));
3300 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
3301 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
3306 /* The register or float register operand is in operand 0 or 1. */
3307 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
3308 /* Register goes in low 3 bits of opcode. */
3309 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
3310 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3312 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
3314 /* Warn about some common errors, but press on regardless.
3315 The first case can be generated by gcc (<= 2.8.1). */
3316 if (i
.operands
== 2)
3318 /* Reversed arguments on faddp, fsubp, etc. */
3319 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
3320 i
.op
[1].regs
->reg_name
,
3321 i
.op
[0].regs
->reg_name
);
3325 /* Extraneous `l' suffix on fp insn. */
3326 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
3327 i
.op
[0].regs
->reg_name
);
3332 else if (i
.tm
.opcode_modifier
& Modrm
)
3334 /* The opcode is completed (modulo i.tm.extension_opcode which
3335 must be put into the modrm byte). Now, we make the modrm and
3336 index base bytes based on all the info we've collected. */
3338 default_seg
= build_modrm_byte ();
3340 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
3344 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
3346 /* For the string instructions that allow a segment override
3347 on one of their operands, the default segment is ds. */
3351 if ((i
.tm
.base_opcode
== 0x8d /* lea */
3352 || (i
.tm
.cpu_flags
& CpuSVME
))
3353 && i
.seg
[0] && !quiet_warnings
)
3354 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
3356 /* If a segment was explicitly specified, and the specified segment
3357 is not the default, use an opcode prefix to select it. If we
3358 never figured out what the default segment is, then default_seg
3359 will be zero at this point, and the specified segment prefix will
3361 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
3363 if (!add_prefix (i
.seg
[0]->seg_prefix
))
3369 static const seg_entry
*
3370 build_modrm_byte (void)
3372 const seg_entry
*default_seg
= 0;
3374 /* i.reg_operands MUST be the number of real register operands;
3375 implicit registers do not count. */
3376 if (i
.reg_operands
== 2)
3378 unsigned int source
, dest
;
3386 /* When there are 3 operands, one of them may be immediate,
3387 which may be the first or the last operand. Otherwise,
3388 the first operand must be shift count register (cl). */
3389 assert (i
.imm_operands
== 1
3390 || (i
.imm_operands
== 0
3391 && (i
.types
[0] & ShiftCount
)));
3392 source
= (i
.types
[0] & (Imm
| ShiftCount
)) ? 1 : 0;
3395 /* When there are 4 operands, the first two must be immediate
3396 operands. The source operand will be the 3rd one. */
3397 assert (i
.imm_operands
== 2
3398 && (i
.types
[0] & Imm
)
3399 && (i
.types
[1] & Imm
));
3409 /* One of the register operands will be encoded in the i.tm.reg
3410 field, the other in the combined i.tm.mode and i.tm.regmem
3411 fields. If no form of this instruction supports a memory
3412 destination operand, then we assume the source operand may
3413 sometimes be a memory operand and so we need to store the
3414 destination in the i.rm.reg field. */
3415 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
3417 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
3418 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
3419 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
3421 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
3426 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
3427 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
3428 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
3430 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
3433 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
3435 if (!((i
.types
[0] | i
.types
[1]) & Control
))
3437 i
.rex
&= ~(REX_R
| REX_B
);
3438 add_prefix (LOCK_PREFIX_OPCODE
);
3442 { /* If it's not 2 reg operands... */
3445 unsigned int fake_zero_displacement
= 0;
3448 for (op
= 0; op
< i
.operands
; op
++)
3449 if ((i
.types
[op
] & AnyMem
))
3451 assert (op
< i
.operands
);
3455 if (i
.base_reg
== 0)
3458 if (!i
.disp_operands
)
3459 fake_zero_displacement
= 1;
3460 if (i
.index_reg
== 0)
3462 /* Operand is just <disp> */
3463 if (flag_code
== CODE_64BIT
)
3465 /* 64bit mode overwrites the 32bit absolute
3466 addressing by RIP relative addressing and
3467 absolute addressing is encoded by one of the
3468 redundant SIB forms. */
3469 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3470 i
.sib
.base
= NO_BASE_REGISTER
;
3471 i
.sib
.index
= NO_INDEX_REGISTER
;
3472 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
3473 ? Disp32S
: Disp32
);
3475 else if ((flag_code
== CODE_16BIT
)
3476 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3478 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
3479 i
.types
[op
] = Disp16
;
3483 i
.rm
.regmem
= NO_BASE_REGISTER
;
3484 i
.types
[op
] = Disp32
;
3487 else /* !i.base_reg && i.index_reg */
3489 i
.sib
.index
= i
.index_reg
->reg_num
;
3490 i
.sib
.base
= NO_BASE_REGISTER
;
3491 i
.sib
.scale
= i
.log2_scale_factor
;
3492 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3493 i
.types
[op
] &= ~Disp
;
3494 if (flag_code
!= CODE_64BIT
)
3495 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
3497 i
.types
[op
] |= Disp32S
;
3498 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3502 /* RIP addressing for 64bit mode. */
3503 else if (i
.base_reg
->reg_type
== BaseIndex
)
3505 i
.rm
.regmem
= NO_BASE_REGISTER
;
3506 i
.types
[op
] &= ~ Disp
;
3507 i
.types
[op
] |= Disp32S
;
3508 i
.flags
[op
] |= Operand_PCrel
;
3509 if (! i
.disp_operands
)
3510 fake_zero_displacement
= 1;
3512 else if (i
.base_reg
->reg_type
& Reg16
)
3514 switch (i
.base_reg
->reg_num
)
3517 if (i
.index_reg
== 0)
3519 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3520 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
3524 if (i
.index_reg
== 0)
3527 if ((i
.types
[op
] & Disp
) == 0)
3529 /* fake (%bp) into 0(%bp) */
3530 i
.types
[op
] |= Disp8
;
3531 fake_zero_displacement
= 1;
3534 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3535 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
3537 default: /* (%si) -> 4 or (%di) -> 5 */
3538 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
3540 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3542 else /* i.base_reg and 32/64 bit mode */
3544 if (flag_code
== CODE_64BIT
3545 && (i
.types
[op
] & Disp
))
3546 i
.types
[op
] = ((i
.types
[op
] & Disp8
)
3547 | (i
.prefix
[ADDR_PREFIX
] == 0
3548 ? Disp32S
: Disp32
));
3550 i
.rm
.regmem
= i
.base_reg
->reg_num
;
3551 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
3553 i
.sib
.base
= i
.base_reg
->reg_num
;
3554 /* x86-64 ignores REX prefix bit here to avoid decoder
3556 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
3559 if (i
.disp_operands
== 0)
3561 fake_zero_displacement
= 1;
3562 i
.types
[op
] |= Disp8
;
3565 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
3569 i
.sib
.scale
= i
.log2_scale_factor
;
3570 if (i
.index_reg
== 0)
3572 /* <disp>(%esp) becomes two byte modrm with no index
3573 register. We've already stored the code for esp
3574 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3575 Any base register besides %esp will not use the
3576 extra modrm byte. */
3577 i
.sib
.index
= NO_INDEX_REGISTER
;
3578 #if !SCALE1_WHEN_NO_INDEX
3579 /* Another case where we force the second modrm byte. */
3580 if (i
.log2_scale_factor
)
3581 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3586 i
.sib
.index
= i
.index_reg
->reg_num
;
3587 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3588 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3593 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3594 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
3597 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3600 if (fake_zero_displacement
)
3602 /* Fakes a zero displacement assuming that i.types[op]
3603 holds the correct displacement size. */
3606 assert (i
.op
[op
].disps
== 0);
3607 exp
= &disp_expressions
[i
.disp_operands
++];
3608 i
.op
[op
].disps
= exp
;
3609 exp
->X_op
= O_constant
;
3610 exp
->X_add_number
= 0;
3611 exp
->X_add_symbol
= (symbolS
*) 0;
3612 exp
->X_op_symbol
= (symbolS
*) 0;
3616 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3617 (if any) based on i.tm.extension_opcode. Again, we must be
3618 careful to make sure that segment/control/debug/test/MMX
3619 registers are coded into the i.rm.reg field. */
3624 for (op
= 0; op
< i
.operands
; op
++)
3625 if ((i
.types
[op
] & (Reg
| RegMMX
| RegXMM
3627 | Control
| Debug
| Test
)))
3629 assert (op
< i
.operands
);
3631 /* If there is an extension opcode to put here, the register
3632 number must be put into the regmem field. */
3633 if (i
.tm
.extension_opcode
!= None
)
3635 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
3636 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3641 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
3642 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3646 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3647 must set it to 3 to indicate this is a register operand
3648 in the regmem field. */
3649 if (!i
.mem_operands
)
3653 /* Fill in i.rm.reg field with extension opcode (if any). */
3654 if (i
.tm
.extension_opcode
!= None
)
3655 i
.rm
.reg
= i
.tm
.extension_opcode
;
3661 output_branch (void)
3666 relax_substateT subtype
;
3671 if (flag_code
== CODE_16BIT
)
3675 if (i
.prefix
[DATA_PREFIX
] != 0)
3681 /* Pentium4 branch hints. */
3682 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3683 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3688 if (i
.prefix
[REX_PREFIX
] != 0)
3694 if (i
.prefixes
!= 0 && !intel_syntax
)
3695 as_warn (_("skipping prefixes on this instruction"));
3697 /* It's always a symbol; End frag & setup for relax.
3698 Make sure there is enough room in this frag for the largest
3699 instruction we may generate in md_convert_frag. This is 2
3700 bytes for the opcode and room for the prefix and largest
3702 frag_grow (prefix
+ 2 + 4);
3703 /* Prefix and 1 opcode byte go in fr_fix. */
3704 p
= frag_more (prefix
+ 1);
3705 if (i
.prefix
[DATA_PREFIX
] != 0)
3706 *p
++ = DATA_PREFIX_OPCODE
;
3707 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
3708 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
3709 *p
++ = i
.prefix
[SEG_PREFIX
];
3710 if (i
.prefix
[REX_PREFIX
] != 0)
3711 *p
++ = i
.prefix
[REX_PREFIX
];
3712 *p
= i
.tm
.base_opcode
;
3714 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
3715 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
3716 else if ((cpu_arch_flags
& Cpu386
) != 0)
3717 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
3719 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
3722 sym
= i
.op
[0].disps
->X_add_symbol
;
3723 off
= i
.op
[0].disps
->X_add_number
;
3725 if (i
.op
[0].disps
->X_op
!= O_constant
3726 && i
.op
[0].disps
->X_op
!= O_symbol
)
3728 /* Handle complex expressions. */
3729 sym
= make_expr_symbol (i
.op
[0].disps
);
3733 /* 1 possible extra opcode + 4 byte displacement go in var part.
3734 Pass reloc in fr_var. */
3735 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
3745 if (i
.tm
.opcode_modifier
& JumpByte
)
3747 /* This is a loop or jecxz type instruction. */
3749 if (i
.prefix
[ADDR_PREFIX
] != 0)
3751 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3754 /* Pentium4 branch hints. */
3755 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3756 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3758 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3767 if (flag_code
== CODE_16BIT
)
3770 if (i
.prefix
[DATA_PREFIX
] != 0)
3772 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3782 if (i
.prefix
[REX_PREFIX
] != 0)
3784 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3788 if (i
.prefixes
!= 0 && !intel_syntax
)
3789 as_warn (_("skipping prefixes on this instruction"));
3791 p
= frag_more (1 + size
);
3792 *p
++ = i
.tm
.base_opcode
;
3794 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3795 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3797 /* All jumps handled here are signed, but don't use a signed limit
3798 check for 32 and 16 bit jumps as we want to allow wrap around at
3799 4G and 64k respectively. */
3801 fixP
->fx_signed
= 1;
3805 output_interseg_jump (void)
3813 if (flag_code
== CODE_16BIT
)
3817 if (i
.prefix
[DATA_PREFIX
] != 0)
3823 if (i
.prefix
[REX_PREFIX
] != 0)
3833 if (i
.prefixes
!= 0 && !intel_syntax
)
3834 as_warn (_("skipping prefixes on this instruction"));
3836 /* 1 opcode; 2 segment; offset */
3837 p
= frag_more (prefix
+ 1 + 2 + size
);
3839 if (i
.prefix
[DATA_PREFIX
] != 0)
3840 *p
++ = DATA_PREFIX_OPCODE
;
3842 if (i
.prefix
[REX_PREFIX
] != 0)
3843 *p
++ = i
.prefix
[REX_PREFIX
];
3845 *p
++ = i
.tm
.base_opcode
;
3846 if (i
.op
[1].imms
->X_op
== O_constant
)
3848 offsetT n
= i
.op
[1].imms
->X_add_number
;
3851 && !fits_in_unsigned_word (n
)
3852 && !fits_in_signed_word (n
))
3854 as_bad (_("16-bit jump out of range"));
3857 md_number_to_chars (p
, n
, size
);
3860 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3861 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3862 if (i
.op
[0].imms
->X_op
!= O_constant
)
3863 as_bad (_("can't handle non absolute segment in `%s'"),
3865 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3871 fragS
*insn_start_frag
;
3872 offsetT insn_start_off
;
3874 /* Tie dwarf2 debug info to the address at the start of the insn.
3875 We can't do this after the insn has been output as the current
3876 frag may have been closed off. eg. by frag_var. */
3877 dwarf2_emit_insn (0);
3879 insn_start_frag
= frag_now
;
3880 insn_start_off
= frag_now_fix ();
3883 if (i
.tm
.opcode_modifier
& Jump
)
3885 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3887 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3888 output_interseg_jump ();
3891 /* Output normal instructions here. */
3894 unsigned int prefix
;
3896 /* All opcodes on i386 have either 1 or 2 bytes. Supplemental
3897 Streaming SIMD extensions 3 Instructions have 3 bytes. We may
3898 use one more higher byte to specify a prefix the instruction
3900 if ((i
.tm
.cpu_flags
& CpuSSSE3
) != 0)
3902 if (i
.tm
.base_opcode
& 0xff000000)
3904 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
3908 else if ((i
.tm
.base_opcode
& 0xff0000) != 0)
3910 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
3911 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0)
3914 if (prefix
!= REPE_PREFIX_OPCODE
3915 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
3916 add_prefix (prefix
);
3919 add_prefix (prefix
);
3922 /* The prefix bytes. */
3924 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3930 md_number_to_chars (p
, (valueT
) *q
, 1);
3934 /* Now the opcode; be careful about word order here! */
3935 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3937 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3941 if ((i
.tm
.cpu_flags
& CpuSSSE3
) != 0)
3944 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
3949 /* Put out high byte first: can't use md_number_to_chars! */
3950 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3951 *p
= i
.tm
.base_opcode
& 0xff;
3954 /* Now the modrm byte and sib byte (if present). */
3955 if (i
.tm
.opcode_modifier
& Modrm
)
3958 md_number_to_chars (p
,
3959 (valueT
) (i
.rm
.regmem
<< 0
3963 /* If i.rm.regmem == ESP (4)
3964 && i.rm.mode != (Register mode)
3966 ==> need second modrm byte. */
3967 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3969 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3972 md_number_to_chars (p
,
3973 (valueT
) (i
.sib
.base
<< 0
3975 | i
.sib
.scale
<< 6),
3980 if (i
.disp_operands
)
3981 output_disp (insn_start_frag
, insn_start_off
);
3984 output_imm (insn_start_frag
, insn_start_off
);
3990 pi ("" /*line*/, &i
);
3992 #endif /* DEBUG386 */
3996 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
4001 for (n
= 0; n
< i
.operands
; n
++)
4003 if (i
.types
[n
] & Disp
)
4005 if (i
.op
[n
].disps
->X_op
== O_constant
)
4011 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
4014 if (i
.types
[n
] & Disp8
)
4016 if (i
.types
[n
] & Disp64
)
4019 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
4021 p
= frag_more (size
);
4022 md_number_to_chars (p
, val
, size
);
4026 enum bfd_reloc_code_real reloc_type
;
4029 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
4031 /* The PC relative address is computed relative
4032 to the instruction boundary, so in case immediate
4033 fields follows, we need to adjust the value. */
4034 if (pcrel
&& i
.imm_operands
)
4039 for (n1
= 0; n1
< i
.operands
; n1
++)
4040 if (i
.types
[n1
] & Imm
)
4042 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
4045 if (i
.types
[n1
] & (Imm8
| Imm8S
))
4047 if (i
.types
[n1
] & Imm64
)
4052 /* We should find the immediate. */
4053 if (n1
== i
.operands
)
4055 i
.op
[n
].disps
->X_add_number
-= imm_size
;
4058 if (i
.types
[n
] & Disp32S
)
4061 if (i
.types
[n
] & (Disp16
| Disp64
))
4064 if (i
.types
[n
] & Disp64
)
4068 p
= frag_more (size
);
4069 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
4071 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
4072 && (((reloc_type
== BFD_RELOC_32
4073 || reloc_type
== BFD_RELOC_X86_64_32S
4074 || (reloc_type
== BFD_RELOC_64
4076 && (i
.op
[n
].disps
->X_op
== O_symbol
4077 || (i
.op
[n
].disps
->X_op
== O_add
4078 && ((symbol_get_value_expression
4079 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
4081 || reloc_type
== BFD_RELOC_32_PCREL
))
4085 if (insn_start_frag
== frag_now
)
4086 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
4091 add
= insn_start_frag
->fr_fix
- insn_start_off
;
4092 for (fr
= insn_start_frag
->fr_next
;
4093 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
4095 add
+= p
- frag_now
->fr_literal
;
4100 reloc_type
= BFD_RELOC_386_GOTPC
;
4101 i
.op
[n
].imms
->X_add_number
+= add
;
4103 else if (reloc_type
== BFD_RELOC_64
)
4104 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
4106 /* Don't do the adjustment for x86-64, as there
4107 the pcrel addressing is relative to the _next_
4108 insn, and that is taken care of in other code. */
4109 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
4111 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4112 i
.op
[n
].disps
, pcrel
, reloc_type
);
4119 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
4124 for (n
= 0; n
< i
.operands
; n
++)
4126 if (i
.types
[n
] & Imm
)
4128 if (i
.op
[n
].imms
->X_op
== O_constant
)
4134 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
4137 if (i
.types
[n
] & (Imm8
| Imm8S
))
4139 else if (i
.types
[n
] & Imm64
)
4142 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
4144 p
= frag_more (size
);
4145 md_number_to_chars (p
, val
, size
);
4149 /* Not absolute_section.
4150 Need a 32-bit fixup (don't support 8bit
4151 non-absolute imms). Try to support other
4153 enum bfd_reloc_code_real reloc_type
;
4157 if ((i
.types
[n
] & (Imm32S
))
4158 && (i
.suffix
== QWORD_MNEM_SUFFIX
4159 || (!i
.suffix
&& (i
.tm
.opcode_modifier
& No_lSuf
))))
4161 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
4164 if (i
.types
[n
] & (Imm8
| Imm8S
))
4166 if (i
.types
[n
] & Imm64
)
4170 p
= frag_more (size
);
4171 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
4173 /* This is tough to explain. We end up with this one if we
4174 * have operands that look like
4175 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4176 * obtain the absolute address of the GOT, and it is strongly
4177 * preferable from a performance point of view to avoid using
4178 * a runtime relocation for this. The actual sequence of
4179 * instructions often look something like:
4184 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4186 * The call and pop essentially return the absolute address
4187 * of the label .L66 and store it in %ebx. The linker itself
4188 * will ultimately change the first operand of the addl so
4189 * that %ebx points to the GOT, but to keep things simple, the
4190 * .o file must have this operand set so that it generates not
4191 * the absolute address of .L66, but the absolute address of
4192 * itself. This allows the linker itself simply treat a GOTPC
4193 * relocation as asking for a pcrel offset to the GOT to be
4194 * added in, and the addend of the relocation is stored in the
4195 * operand field for the instruction itself.
4197 * Our job here is to fix the operand so that it would add
4198 * the correct offset so that %ebx would point to itself. The
4199 * thing that is tricky is that .-.L66 will point to the
4200 * beginning of the instruction, so we need to further modify
4201 * the operand so that it will point to itself. There are
4202 * other cases where you have something like:
4204 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4206 * and here no correction would be required. Internally in
4207 * the assembler we treat operands of this form as not being
4208 * pcrel since the '.' is explicitly mentioned, and I wonder
4209 * whether it would simplify matters to do it this way. Who
4210 * knows. In earlier versions of the PIC patches, the
4211 * pcrel_adjust field was used to store the correction, but
4212 * since the expression is not pcrel, I felt it would be
4213 * confusing to do it this way. */
4215 if ((reloc_type
== BFD_RELOC_32
4216 || reloc_type
== BFD_RELOC_X86_64_32S
4217 || reloc_type
== BFD_RELOC_64
)
4219 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
4220 && (i
.op
[n
].imms
->X_op
== O_symbol
4221 || (i
.op
[n
].imms
->X_op
== O_add
4222 && ((symbol_get_value_expression
4223 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
4228 if (insn_start_frag
== frag_now
)
4229 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
4234 add
= insn_start_frag
->fr_fix
- insn_start_off
;
4235 for (fr
= insn_start_frag
->fr_next
;
4236 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
4238 add
+= p
- frag_now
->fr_literal
;
4242 reloc_type
= BFD_RELOC_386_GOTPC
;
4244 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
4246 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
4247 i
.op
[n
].imms
->X_add_number
+= add
;
4249 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4250 i
.op
[n
].imms
, 0, reloc_type
);
4256 /* x86_cons_fix_new is called via the expression parsing code when a
4257 reloc is needed. We use this hook to get the correct .got reloc. */
4258 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
4259 static int cons_sign
= -1;
4262 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
4265 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
4267 got_reloc
= NO_RELOC
;
4270 if (exp
->X_op
== O_secrel
)
4272 exp
->X_op
= O_symbol
;
4273 r
= BFD_RELOC_32_SECREL
;
4277 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
4280 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4281 # define lex_got(reloc, adjust, types) NULL
4283 /* Parse operands of the form
4284 <symbol>@GOTOFF+<nnn>
4285 and similar .plt or .got references.
4287 If we find one, set up the correct relocation in RELOC and copy the
4288 input string, minus the `@GOTOFF' into a malloc'd buffer for
4289 parsing by the calling routine. Return this buffer, and if ADJUST
4290 is non-null set it to the length of the string we removed from the
4291 input line. Otherwise return NULL. */
4293 lex_got (enum bfd_reloc_code_real
*reloc
,
4295 unsigned int *types
)
4297 /* Some of the relocations depend on the size of what field is to
4298 be relocated. But in our callers i386_immediate and i386_displacement
4299 we don't yet know the operand size (this will be set by insn
4300 matching). Hence we record the word32 relocation here,
4301 and adjust the reloc according to the real size in reloc(). */
4302 static const struct {
4304 const enum bfd_reloc_code_real rel
[2];
4305 const unsigned int types64
;
4308 BFD_RELOC_X86_64_PLTOFF64
},
4310 { "PLT", { BFD_RELOC_386_PLT32
,
4311 BFD_RELOC_X86_64_PLT32
},
4312 Imm32
| Imm32S
| Disp32
},
4314 BFD_RELOC_X86_64_GOTPLT64
},
4316 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
4317 BFD_RELOC_X86_64_GOTOFF64
},
4320 BFD_RELOC_X86_64_GOTPCREL
},
4321 Imm32
| Imm32S
| Disp32
},
4322 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
4323 BFD_RELOC_X86_64_TLSGD
},
4324 Imm32
| Imm32S
| Disp32
},
4325 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
4329 BFD_RELOC_X86_64_TLSLD
},
4330 Imm32
| Imm32S
| Disp32
},
4331 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
4332 BFD_RELOC_X86_64_GOTTPOFF
},
4333 Imm32
| Imm32S
| Disp32
},
4334 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
4335 BFD_RELOC_X86_64_TPOFF32
},
4336 Imm32
| Imm32S
| Imm64
| Disp32
| Disp64
},
4337 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
4340 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
4341 BFD_RELOC_X86_64_DTPOFF32
},
4342 Imm32
| Imm32S
| Imm64
| Disp32
| Disp64
},
4343 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
4346 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
4349 { "GOT", { BFD_RELOC_386_GOT32
,
4350 BFD_RELOC_X86_64_GOT32
},
4351 Imm32
| Imm32S
| Disp32
| Imm64
},
4352 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
4353 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
4354 Imm32
| Imm32S
| Disp32
},
4355 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
4356 BFD_RELOC_X86_64_TLSDESC_CALL
},
4357 Imm32
| Imm32S
| Disp32
}
4365 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
4366 if (is_end_of_line
[(unsigned char) *cp
])
4369 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
4373 len
= strlen (gotrel
[j
].str
);
4374 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
4376 if (gotrel
[j
].rel
[object_64bit
] != 0)
4379 char *tmpbuf
, *past_reloc
;
4381 *reloc
= gotrel
[j
].rel
[object_64bit
];
4387 if (flag_code
!= CODE_64BIT
)
4388 *types
= Imm32
| Disp32
;
4390 *types
= gotrel
[j
].types64
;
4393 if (GOT_symbol
== NULL
)
4394 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
4396 /* Replace the relocation token with ' ', so that
4397 errors like foo@GOTOFF1 will be detected. */
4399 /* The length of the first part of our input line. */
4400 first
= cp
- input_line_pointer
;
4402 /* The second part goes from after the reloc token until
4403 (and including) an end_of_line char. Don't use strlen
4404 here as the end_of_line char may not be a NUL. */
4405 past_reloc
= cp
+ 1 + len
;
4406 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
4408 second
= cp
- past_reloc
;
4410 /* Allocate and copy string. The trailing NUL shouldn't
4411 be necessary, but be safe. */
4412 tmpbuf
= xmalloc (first
+ second
+ 2);
4413 memcpy (tmpbuf
, input_line_pointer
, first
);
4414 tmpbuf
[first
] = ' ';
4415 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
4416 tmpbuf
[first
+ second
+ 1] = '\0';
4420 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4421 gotrel
[j
].str
, 1 << (5 + object_64bit
));
4426 /* Might be a symbol version string. Don't as_bad here. */
4431 x86_cons (expressionS
*exp
, int size
)
4433 if (size
== 4 || (object_64bit
&& size
== 8))
4435 /* Handle @GOTOFF and the like in an expression. */
4437 char *gotfree_input_line
;
4440 save
= input_line_pointer
;
4441 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
4442 if (gotfree_input_line
)
4443 input_line_pointer
= gotfree_input_line
;
4447 if (gotfree_input_line
)
4449 /* expression () has merrily parsed up to the end of line,
4450 or a comma - in the wrong buffer. Transfer how far
4451 input_line_pointer has moved to the right buffer. */
4452 input_line_pointer
= (save
4453 + (input_line_pointer
- gotfree_input_line
)
4455 free (gotfree_input_line
);
4463 static void signed_cons (int size
)
4465 if (flag_code
== CODE_64BIT
)
4473 pe_directive_secrel (dummy
)
4474 int dummy ATTRIBUTE_UNUSED
;
4481 if (exp
.X_op
== O_symbol
)
4482 exp
.X_op
= O_secrel
;
4484 emit_expr (&exp
, 4);
4486 while (*input_line_pointer
++ == ',');
4488 input_line_pointer
--;
4489 demand_empty_rest_of_line ();
4494 i386_immediate (char *imm_start
)
4496 char *save_input_line_pointer
;
4497 char *gotfree_input_line
;
4500 unsigned int types
= ~0U;
4502 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
4504 as_bad (_("at most %d immediate operands are allowed"),
4505 MAX_IMMEDIATE_OPERANDS
);
4509 exp
= &im_expressions
[i
.imm_operands
++];
4510 i
.op
[this_operand
].imms
= exp
;
4512 if (is_space_char (*imm_start
))
4515 save_input_line_pointer
= input_line_pointer
;
4516 input_line_pointer
= imm_start
;
4518 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4519 if (gotfree_input_line
)
4520 input_line_pointer
= gotfree_input_line
;
4522 exp_seg
= expression (exp
);
4525 if (*input_line_pointer
)
4526 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4528 input_line_pointer
= save_input_line_pointer
;
4529 if (gotfree_input_line
)
4530 free (gotfree_input_line
);
4532 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4534 /* Missing or bad expr becomes absolute 0. */
4535 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
4537 exp
->X_op
= O_constant
;
4538 exp
->X_add_number
= 0;
4539 exp
->X_add_symbol
= (symbolS
*) 0;
4540 exp
->X_op_symbol
= (symbolS
*) 0;
4542 else if (exp
->X_op
== O_constant
)
4544 /* Size it properly later. */
4545 i
.types
[this_operand
] |= Imm64
;
4546 /* If BFD64, sign extend val. */
4547 if (!use_rela_relocations
4548 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
4550 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
4552 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4553 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
4554 && exp_seg
!= absolute_section
4555 && exp_seg
!= text_section
4556 && exp_seg
!= data_section
4557 && exp_seg
!= bss_section
4558 && exp_seg
!= undefined_section
4559 && !bfd_is_com_section (exp_seg
))
4561 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4565 else if (!intel_syntax
&& exp
->X_op
== O_register
)
4567 as_bad (_("illegal immediate register operand %s"), imm_start
);
4572 /* This is an address. The size of the address will be
4573 determined later, depending on destination register,
4574 suffix, or the default for the section. */
4575 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
4576 i
.types
[this_operand
] &= types
;
4583 i386_scale (char *scale
)
4586 char *save
= input_line_pointer
;
4588 input_line_pointer
= scale
;
4589 val
= get_absolute_expression ();
4594 i
.log2_scale_factor
= 0;
4597 i
.log2_scale_factor
= 1;
4600 i
.log2_scale_factor
= 2;
4603 i
.log2_scale_factor
= 3;
4607 char sep
= *input_line_pointer
;
4609 *input_line_pointer
= '\0';
4610 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4612 *input_line_pointer
= sep
;
4613 input_line_pointer
= save
;
4617 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
4619 as_warn (_("scale factor of %d without an index register"),
4620 1 << i
.log2_scale_factor
);
4621 #if SCALE1_WHEN_NO_INDEX
4622 i
.log2_scale_factor
= 0;
4625 scale
= input_line_pointer
;
4626 input_line_pointer
= save
;
4631 i386_displacement (char *disp_start
, char *disp_end
)
4635 char *save_input_line_pointer
;
4636 char *gotfree_input_line
;
4637 int bigdisp
, override
;
4638 unsigned int types
= Disp
;
4640 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
4642 as_bad (_("at most %d displacement operands are allowed"),
4643 MAX_MEMORY_OPERANDS
);
4647 if ((i
.types
[this_operand
] & JumpAbsolute
)
4648 || !(current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
)))
4651 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
4655 /* For PC-relative branches, the width of the displacement
4656 is dependent upon data size, not address size. */
4658 override
= (i
.prefix
[DATA_PREFIX
] != 0);
4660 if (flag_code
== CODE_64BIT
)
4663 bigdisp
= ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
4665 : Disp32S
| Disp32
);
4667 bigdisp
= Disp64
| Disp32S
| Disp32
;
4674 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
4676 : LONG_MNEM_SUFFIX
));
4679 if ((flag_code
== CODE_16BIT
) ^ override
)
4682 i
.types
[this_operand
] |= bigdisp
;
4684 exp
= &disp_expressions
[i
.disp_operands
];
4685 i
.op
[this_operand
].disps
= exp
;
4687 save_input_line_pointer
= input_line_pointer
;
4688 input_line_pointer
= disp_start
;
4689 END_STRING_AND_SAVE (disp_end
);
4691 #ifndef GCC_ASM_O_HACK
4692 #define GCC_ASM_O_HACK 0
4695 END_STRING_AND_SAVE (disp_end
+ 1);
4696 if ((i
.types
[this_operand
] & BaseIndex
) != 0
4697 && displacement_string_end
[-1] == '+')
4699 /* This hack is to avoid a warning when using the "o"
4700 constraint within gcc asm statements.
4703 #define _set_tssldt_desc(n,addr,limit,type) \
4704 __asm__ __volatile__ ( \
4706 "movw %w1,2+%0\n\t" \
4708 "movb %b1,4+%0\n\t" \
4709 "movb %4,5+%0\n\t" \
4710 "movb $0,6+%0\n\t" \
4711 "movb %h1,7+%0\n\t" \
4713 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4715 This works great except that the output assembler ends
4716 up looking a bit weird if it turns out that there is
4717 no offset. You end up producing code that looks like:
4730 So here we provide the missing zero. */
4732 *displacement_string_end
= '0';
4735 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4736 if (gotfree_input_line
)
4737 input_line_pointer
= gotfree_input_line
;
4739 exp_seg
= expression (exp
);
4742 if (*input_line_pointer
)
4743 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4745 RESTORE_END_STRING (disp_end
+ 1);
4747 RESTORE_END_STRING (disp_end
);
4748 input_line_pointer
= save_input_line_pointer
;
4749 if (gotfree_input_line
)
4750 free (gotfree_input_line
);
4752 /* We do this to make sure that the section symbol is in
4753 the symbol table. We will ultimately change the relocation
4754 to be relative to the beginning of the section. */
4755 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
4756 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4757 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4759 if (exp
->X_op
!= O_symbol
)
4761 as_bad (_("bad expression used with @%s"),
4762 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4768 if (S_IS_LOCAL (exp
->X_add_symbol
)
4769 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
4770 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
4771 exp
->X_op
= O_subtract
;
4772 exp
->X_op_symbol
= GOT_symbol
;
4773 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
4774 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
4775 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4776 i
.reloc
[this_operand
] = BFD_RELOC_64
;
4778 i
.reloc
[this_operand
] = BFD_RELOC_32
;
4781 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4783 /* Missing or bad expr becomes absolute 0. */
4784 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4786 exp
->X_op
= O_constant
;
4787 exp
->X_add_number
= 0;
4788 exp
->X_add_symbol
= (symbolS
*) 0;
4789 exp
->X_op_symbol
= (symbolS
*) 0;
4792 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4793 if (exp
->X_op
!= O_constant
4794 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
4795 && exp_seg
!= absolute_section
4796 && exp_seg
!= text_section
4797 && exp_seg
!= data_section
4798 && exp_seg
!= bss_section
4799 && exp_seg
!= undefined_section
4800 && !bfd_is_com_section (exp_seg
))
4802 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4807 if (!(i
.types
[this_operand
] & ~Disp
))
4808 i
.types
[this_operand
] &= types
;
4813 /* Make sure the memory operand we've been dealt is valid.
4814 Return 1 on success, 0 on a failure. */
4817 i386_index_check (const char *operand_string
)
4820 #if INFER_ADDR_PREFIX
4826 if ((current_templates
->start
->cpu_flags
& CpuSVME
)
4827 && current_templates
->end
[-1].operand_types
[0] == AnyMem
)
4829 /* Memory operands of SVME insns are special in that they only allow
4830 rAX as their memory address and ignore any segment override. */
4833 /* SKINIT is even more restrictive: it always requires EAX. */
4834 if (strcmp (current_templates
->start
->name
, "skinit") == 0)
4836 else if (flag_code
== CODE_64BIT
)
4837 RegXX
= i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
;
4839 RegXX
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0)
4843 || !(i
.base_reg
->reg_type
& Acc
)
4844 || !(i
.base_reg
->reg_type
& RegXX
)
4846 || (i
.types
[0] & Disp
))
4849 else if (flag_code
== CODE_64BIT
)
4851 unsigned RegXX
= (i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
);
4854 && ((i
.base_reg
->reg_type
& RegXX
) == 0)
4855 && (i
.base_reg
->reg_type
!= BaseIndex
4858 && ((i
.index_reg
->reg_type
& (RegXX
| BaseIndex
))
4859 != (RegXX
| BaseIndex
))))
4864 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4868 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
4869 != (Reg16
| BaseIndex
)))
4871 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
4872 != (Reg16
| BaseIndex
))
4874 && i
.base_reg
->reg_num
< 6
4875 && i
.index_reg
->reg_num
>= 6
4876 && i
.log2_scale_factor
== 0))))
4883 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
4885 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
4886 != (Reg32
| BaseIndex
))))
4892 #if INFER_ADDR_PREFIX
4893 if (i
.prefix
[ADDR_PREFIX
] == 0)
4895 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
4897 /* Change the size of any displacement too. At most one of
4898 Disp16 or Disp32 is set.
4899 FIXME. There doesn't seem to be any real need for separate
4900 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4901 Removing them would probably clean up the code quite a lot. */
4902 if (flag_code
!= CODE_64BIT
4903 && (i
.types
[this_operand
] & (Disp16
| Disp32
)))
4904 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
4909 as_bad (_("`%s' is not a valid base/index expression"),
4913 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4915 flag_code_names
[flag_code
]);
4920 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4924 i386_operand (char *operand_string
)
4928 char *op_string
= operand_string
;
4930 if (is_space_char (*op_string
))
4933 /* We check for an absolute prefix (differentiating,
4934 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4935 if (*op_string
== ABSOLUTE_PREFIX
)
4938 if (is_space_char (*op_string
))
4940 i
.types
[this_operand
] |= JumpAbsolute
;
4943 /* Check if operand is a register. */
4944 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
4946 /* Check for a segment override by searching for ':' after a
4947 segment register. */
4949 if (is_space_char (*op_string
))
4951 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
4956 i
.seg
[i
.mem_operands
] = &es
;
4959 i
.seg
[i
.mem_operands
] = &cs
;
4962 i
.seg
[i
.mem_operands
] = &ss
;
4965 i
.seg
[i
.mem_operands
] = &ds
;
4968 i
.seg
[i
.mem_operands
] = &fs
;
4971 i
.seg
[i
.mem_operands
] = &gs
;
4975 /* Skip the ':' and whitespace. */
4977 if (is_space_char (*op_string
))
4980 if (!is_digit_char (*op_string
)
4981 && !is_identifier_char (*op_string
)
4982 && *op_string
!= '('
4983 && *op_string
!= ABSOLUTE_PREFIX
)
4985 as_bad (_("bad memory operand `%s'"), op_string
);
4988 /* Handle case of %es:*foo. */
4989 if (*op_string
== ABSOLUTE_PREFIX
)
4992 if (is_space_char (*op_string
))
4994 i
.types
[this_operand
] |= JumpAbsolute
;
4996 goto do_memory_reference
;
5000 as_bad (_("junk `%s' after register"), op_string
);
5003 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
5004 i
.op
[this_operand
].regs
= r
;
5007 else if (*op_string
== REGISTER_PREFIX
)
5009 as_bad (_("bad register name `%s'"), op_string
);
5012 else if (*op_string
== IMMEDIATE_PREFIX
)
5015 if (i
.types
[this_operand
] & JumpAbsolute
)
5017 as_bad (_("immediate operand illegal with absolute jump"));
5020 if (!i386_immediate (op_string
))
5023 else if (is_digit_char (*op_string
)
5024 || is_identifier_char (*op_string
)
5025 || *op_string
== '(')
5027 /* This is a memory reference of some sort. */
5030 /* Start and end of displacement string expression (if found). */
5031 char *displacement_string_start
;
5032 char *displacement_string_end
;
5034 do_memory_reference
:
5035 if ((i
.mem_operands
== 1
5036 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5037 || i
.mem_operands
== 2)
5039 as_bad (_("too many memory references for `%s'"),
5040 current_templates
->start
->name
);
5044 /* Check for base index form. We detect the base index form by
5045 looking for an ')' at the end of the operand, searching
5046 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5048 base_string
= op_string
+ strlen (op_string
);
5051 if (is_space_char (*base_string
))
5054 /* If we only have a displacement, set-up for it to be parsed later. */
5055 displacement_string_start
= op_string
;
5056 displacement_string_end
= base_string
+ 1;
5058 if (*base_string
== ')')
5061 unsigned int parens_balanced
= 1;
5062 /* We've already checked that the number of left & right ()'s are
5063 equal, so this loop will not be infinite. */
5067 if (*base_string
== ')')
5069 if (*base_string
== '(')
5072 while (parens_balanced
);
5074 temp_string
= base_string
;
5076 /* Skip past '(' and whitespace. */
5078 if (is_space_char (*base_string
))
5081 if (*base_string
== ','
5082 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
5085 displacement_string_end
= temp_string
;
5087 i
.types
[this_operand
] |= BaseIndex
;
5091 base_string
= end_op
;
5092 if (is_space_char (*base_string
))
5096 /* There may be an index reg or scale factor here. */
5097 if (*base_string
== ',')
5100 if (is_space_char (*base_string
))
5103 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
5106 base_string
= end_op
;
5107 if (is_space_char (*base_string
))
5109 if (*base_string
== ',')
5112 if (is_space_char (*base_string
))
5115 else if (*base_string
!= ')')
5117 as_bad (_("expecting `,' or `)' "
5118 "after index register in `%s'"),
5123 else if (*base_string
== REGISTER_PREFIX
)
5125 as_bad (_("bad register name `%s'"), base_string
);
5129 /* Check for scale factor. */
5130 if (*base_string
!= ')')
5132 char *end_scale
= i386_scale (base_string
);
5137 base_string
= end_scale
;
5138 if (is_space_char (*base_string
))
5140 if (*base_string
!= ')')
5142 as_bad (_("expecting `)' "
5143 "after scale factor in `%s'"),
5148 else if (!i
.index_reg
)
5150 as_bad (_("expecting index register or scale factor "
5151 "after `,'; got '%c'"),
5156 else if (*base_string
!= ')')
5158 as_bad (_("expecting `,' or `)' "
5159 "after base register in `%s'"),
5164 else if (*base_string
== REGISTER_PREFIX
)
5166 as_bad (_("bad register name `%s'"), base_string
);
5171 /* If there's an expression beginning the operand, parse it,
5172 assuming displacement_string_start and
5173 displacement_string_end are meaningful. */
5174 if (displacement_string_start
!= displacement_string_end
)
5176 if (!i386_displacement (displacement_string_start
,
5177 displacement_string_end
))
5181 /* Special case for (%dx) while doing input/output op. */
5183 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
5185 && i
.log2_scale_factor
== 0
5186 && i
.seg
[i
.mem_operands
] == 0
5187 && (i
.types
[this_operand
] & Disp
) == 0)
5189 i
.types
[this_operand
] = InOutPortReg
;
5193 if (i386_index_check (operand_string
) == 0)
5199 /* It's not a memory operand; argh! */
5200 as_bad (_("invalid char %s beginning operand %d `%s'"),
5201 output_invalid (*op_string
),
5206 return 1; /* Normal return. */
5209 /* md_estimate_size_before_relax()
5211 Called just before relax() for rs_machine_dependent frags. The x86
5212 assembler uses these frags to handle variable size jump
5215 Any symbol that is now undefined will not become defined.
5216 Return the correct fr_subtype in the frag.
5217 Return the initial "guess for variable size of frag" to caller.
5218 The guess is actually the growth beyond the fixed part. Whatever
5219 we do to grow the fixed or variable part contributes to our
5223 md_estimate_size_before_relax (fragP
, segment
)
5227 /* We've already got fragP->fr_subtype right; all we have to do is
5228 check for un-relaxable symbols. On an ELF system, we can't relax
5229 an externally visible symbol, because it may be overridden by a
5231 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
5232 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5234 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
5235 || S_IS_WEAK (fragP
->fr_symbol
)))
5239 /* Symbol is undefined in this segment, or we need to keep a
5240 reloc so that weak symbols can be overridden. */
5241 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
5242 enum bfd_reloc_code_real reloc_type
;
5243 unsigned char *opcode
;
5246 if (fragP
->fr_var
!= NO_RELOC
)
5247 reloc_type
= fragP
->fr_var
;
5249 reloc_type
= BFD_RELOC_16_PCREL
;
5251 reloc_type
= BFD_RELOC_32_PCREL
;
5253 old_fr_fix
= fragP
->fr_fix
;
5254 opcode
= (unsigned char *) fragP
->fr_opcode
;
5256 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
5259 /* Make jmp (0xeb) a (d)word displacement jump. */
5261 fragP
->fr_fix
+= size
;
5262 fix_new (fragP
, old_fr_fix
, size
,
5264 fragP
->fr_offset
, 1,
5270 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
5272 /* Negate the condition, and branch past an
5273 unconditional jump. */
5276 /* Insert an unconditional jump. */
5278 /* We added two extra opcode bytes, and have a two byte
5280 fragP
->fr_fix
+= 2 + 2;
5281 fix_new (fragP
, old_fr_fix
+ 2, 2,
5283 fragP
->fr_offset
, 1,
5290 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
5295 fixP
= fix_new (fragP
, old_fr_fix
, 1,
5297 fragP
->fr_offset
, 1,
5299 fixP
->fx_signed
= 1;
5303 /* This changes the byte-displacement jump 0x7N
5304 to the (d)word-displacement jump 0x0f,0x8N. */
5305 opcode
[1] = opcode
[0] + 0x10;
5306 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5307 /* We've added an opcode byte. */
5308 fragP
->fr_fix
+= 1 + size
;
5309 fix_new (fragP
, old_fr_fix
+ 1, size
,
5311 fragP
->fr_offset
, 1,
5316 BAD_CASE (fragP
->fr_subtype
);
5320 return fragP
->fr_fix
- old_fr_fix
;
5323 /* Guess size depending on current relax state. Initially the relax
5324 state will correspond to a short jump and we return 1, because
5325 the variable part of the frag (the branch offset) is one byte
5326 long. However, we can relax a section more than once and in that
5327 case we must either set fr_subtype back to the unrelaxed state,
5328 or return the value for the appropriate branch. */
5329 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
5332 /* Called after relax() is finished.
5334 In: Address of frag.
5335 fr_type == rs_machine_dependent.
5336 fr_subtype is what the address relaxed to.
5338 Out: Any fixSs and constants are set up.
5339 Caller will turn frag into a ".space 0". */
5342 md_convert_frag (abfd
, sec
, fragP
)
5343 bfd
*abfd ATTRIBUTE_UNUSED
;
5344 segT sec ATTRIBUTE_UNUSED
;
5347 unsigned char *opcode
;
5348 unsigned char *where_to_put_displacement
= NULL
;
5349 offsetT target_address
;
5350 offsetT opcode_address
;
5351 unsigned int extension
= 0;
5352 offsetT displacement_from_opcode_start
;
5354 opcode
= (unsigned char *) fragP
->fr_opcode
;
5356 /* Address we want to reach in file space. */
5357 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
5359 /* Address opcode resides at in file space. */
5360 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
5362 /* Displacement from opcode start to fill into instruction. */
5363 displacement_from_opcode_start
= target_address
- opcode_address
;
5365 if ((fragP
->fr_subtype
& BIG
) == 0)
5367 /* Don't have to change opcode. */
5368 extension
= 1; /* 1 opcode + 1 displacement */
5369 where_to_put_displacement
= &opcode
[1];
5373 if (no_cond_jump_promotion
5374 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
5375 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
5376 _("long jump required"));
5378 switch (fragP
->fr_subtype
)
5380 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
5381 extension
= 4; /* 1 opcode + 4 displacement */
5383 where_to_put_displacement
= &opcode
[1];
5386 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
5387 extension
= 2; /* 1 opcode + 2 displacement */
5389 where_to_put_displacement
= &opcode
[1];
5392 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
5393 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
5394 extension
= 5; /* 2 opcode + 4 displacement */
5395 opcode
[1] = opcode
[0] + 0x10;
5396 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5397 where_to_put_displacement
= &opcode
[2];
5400 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
5401 extension
= 3; /* 2 opcode + 2 displacement */
5402 opcode
[1] = opcode
[0] + 0x10;
5403 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5404 where_to_put_displacement
= &opcode
[2];
5407 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
5412 where_to_put_displacement
= &opcode
[3];
5416 BAD_CASE (fragP
->fr_subtype
);
5421 /* If size if less then four we are sure that the operand fits,
5422 but if it's 4, then it could be that the displacement is larger
5424 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
5426 && ((addressT
) (displacement_from_opcode_start
- extension
5427 + ((addressT
) 1 << 31))
5428 > (((addressT
) 2 << 31) - 1)))
5430 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5431 _("jump target out of range"));
5432 /* Make us emit 0. */
5433 displacement_from_opcode_start
= extension
;
5435 /* Now put displacement after opcode. */
5436 md_number_to_chars ((char *) where_to_put_displacement
,
5437 (valueT
) (displacement_from_opcode_start
- extension
),
5438 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
5439 fragP
->fr_fix
+= extension
;
5442 /* Size of byte displacement jmp. */
5443 int md_short_jump_size
= 2;
5445 /* Size of dword displacement jmp. */
5446 int md_long_jump_size
= 5;
5449 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5451 addressT from_addr
, to_addr
;
5452 fragS
*frag ATTRIBUTE_UNUSED
;
5453 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
5457 offset
= to_addr
- (from_addr
+ 2);
5458 /* Opcode for byte-disp jump. */
5459 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
5460 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
5464 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5466 addressT from_addr
, to_addr
;
5467 fragS
*frag ATTRIBUTE_UNUSED
;
5468 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
5472 offset
= to_addr
- (from_addr
+ 5);
5473 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
5474 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
5477 /* Apply a fixup (fixS) to segment data, once it has been determined
5478 by our caller that we have all the info we need to fix it up.
5480 On the 386, immediates, displacements, and data pointers are all in
5481 the same (little-endian) format, so we don't need to care about which
5485 md_apply_fix (fixP
, valP
, seg
)
5486 /* The fix we're to put in. */
5488 /* Pointer to the value of the bits. */
5490 /* Segment fix is from. */
5491 segT seg ATTRIBUTE_UNUSED
;
5493 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
5494 valueT value
= *valP
;
5496 #if !defined (TE_Mach)
5499 switch (fixP
->fx_r_type
)
5505 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
5508 case BFD_RELOC_X86_64_32S
:
5509 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
5512 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
5515 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
5520 if (fixP
->fx_addsy
!= NULL
5521 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
5522 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
5523 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
5524 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
5525 && !use_rela_relocations
)
5527 /* This is a hack. There should be a better way to handle this.
5528 This covers for the fact that bfd_install_relocation will
5529 subtract the current location (for partial_inplace, PC relative
5530 relocations); see more below. */
5534 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
5537 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5539 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5542 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
5545 || (symbol_section_p (fixP
->fx_addsy
)
5546 && sym_seg
!= absolute_section
))
5547 && !generic_force_reloc (fixP
))
5549 /* Yes, we add the values in twice. This is because
5550 bfd_install_relocation subtracts them out again. I think
5551 bfd_install_relocation is broken, but I don't dare change
5553 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5557 #if defined (OBJ_COFF) && defined (TE_PE)
5558 /* For some reason, the PE format does not store a
5559 section address offset for a PC relative symbol. */
5560 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
5561 || S_IS_WEAK (fixP
->fx_addsy
))
5562 value
+= md_pcrel_from (fixP
);
5566 /* Fix a few things - the dynamic linker expects certain values here,
5567 and we must not disappoint it. */
5568 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5569 if (IS_ELF
&& fixP
->fx_addsy
)
5570 switch (fixP
->fx_r_type
)
5572 case BFD_RELOC_386_PLT32
:
5573 case BFD_RELOC_X86_64_PLT32
:
5574 /* Make the jump instruction point to the address of the operand. At
5575 runtime we merely add the offset to the actual PLT entry. */
5579 case BFD_RELOC_386_TLS_GD
:
5580 case BFD_RELOC_386_TLS_LDM
:
5581 case BFD_RELOC_386_TLS_IE_32
:
5582 case BFD_RELOC_386_TLS_IE
:
5583 case BFD_RELOC_386_TLS_GOTIE
:
5584 case BFD_RELOC_386_TLS_GOTDESC
:
5585 case BFD_RELOC_X86_64_TLSGD
:
5586 case BFD_RELOC_X86_64_TLSLD
:
5587 case BFD_RELOC_X86_64_GOTTPOFF
:
5588 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
5589 value
= 0; /* Fully resolved at runtime. No addend. */
5591 case BFD_RELOC_386_TLS_LE
:
5592 case BFD_RELOC_386_TLS_LDO_32
:
5593 case BFD_RELOC_386_TLS_LE_32
:
5594 case BFD_RELOC_X86_64_DTPOFF32
:
5595 case BFD_RELOC_X86_64_DTPOFF64
:
5596 case BFD_RELOC_X86_64_TPOFF32
:
5597 case BFD_RELOC_X86_64_TPOFF64
:
5598 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5601 case BFD_RELOC_386_TLS_DESC_CALL
:
5602 case BFD_RELOC_X86_64_TLSDESC_CALL
:
5603 value
= 0; /* Fully resolved at runtime. No addend. */
5604 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5608 case BFD_RELOC_386_GOT32
:
5609 case BFD_RELOC_X86_64_GOT32
:
5610 value
= 0; /* Fully resolved at runtime. No addend. */
5613 case BFD_RELOC_VTABLE_INHERIT
:
5614 case BFD_RELOC_VTABLE_ENTRY
:
5621 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5623 #endif /* !defined (TE_Mach) */
5625 /* Are we finished with this relocation now? */
5626 if (fixP
->fx_addsy
== NULL
)
5628 else if (use_rela_relocations
)
5630 fixP
->fx_no_overflow
= 1;
5631 /* Remember value for tc_gen_reloc. */
5632 fixP
->fx_addnumber
= value
;
5636 md_number_to_chars (p
, value
, fixP
->fx_size
);
5639 #define MAX_LITTLENUMS 6
5641 /* Turn the string pointed to by litP into a floating point constant
5642 of type TYPE, and emit the appropriate bytes. The number of
5643 LITTLENUMS emitted is stored in *SIZEP. An error message is
5644 returned, or NULL on OK. */
5647 md_atof (type
, litP
, sizeP
)
5653 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5654 LITTLENUM_TYPE
*wordP
;
5676 return _("Bad call to md_atof ()");
5678 t
= atof_ieee (input_line_pointer
, type
, words
);
5680 input_line_pointer
= t
;
5682 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
5683 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5684 the bigendian 386. */
5685 for (wordP
= words
+ prec
- 1; prec
--;)
5687 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
5688 litP
+= sizeof (LITTLENUM_TYPE
);
5693 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
5696 output_invalid (int c
)
5699 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
5702 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
5703 "(0x%x)", (unsigned char) c
);
5704 return output_invalid_buf
;
5707 /* REG_STRING starts *before* REGISTER_PREFIX. */
5709 static const reg_entry
*
5710 parse_real_register (char *reg_string
, char **end_op
)
5712 char *s
= reg_string
;
5714 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
5717 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5718 if (*s
== REGISTER_PREFIX
)
5721 if (is_space_char (*s
))
5725 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
5727 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
5728 return (const reg_entry
*) NULL
;
5732 /* For naked regs, make sure that we are not dealing with an identifier.
5733 This prevents confusing an identifier like `eax_var' with register
5735 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
5736 return (const reg_entry
*) NULL
;
5740 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
5742 /* Handle floating point regs, allowing spaces in the (i) part. */
5743 if (r
== i386_regtab
/* %st is first entry of table */)
5745 if (is_space_char (*s
))
5750 if (is_space_char (*s
))
5752 if (*s
>= '0' && *s
<= '7')
5754 r
= &i386_float_regtab
[*s
- '0'];
5756 if (is_space_char (*s
))
5764 /* We have "%st(" then garbage. */
5765 return (const reg_entry
*) NULL
;
5770 && ((r
->reg_flags
& (RegRex64
| RegRex
)) | (r
->reg_type
& Reg64
)) != 0
5771 && (r
->reg_type
!= Control
|| !(cpu_arch_flags
& CpuSledgehammer
))
5772 && flag_code
!= CODE_64BIT
)
5773 return (const reg_entry
*) NULL
;
5778 /* REG_STRING starts *before* REGISTER_PREFIX. */
5780 static const reg_entry
*
5781 parse_register (char *reg_string
, char **end_op
)
5785 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5786 r
= parse_real_register (reg_string
, end_op
);
5791 char *save
= input_line_pointer
;
5795 input_line_pointer
= reg_string
;
5796 c
= get_symbol_end ();
5797 symbolP
= symbol_find (reg_string
);
5798 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
5800 const expressionS
*e
= symbol_get_value_expression (symbolP
);
5802 know (e
->X_op
== O_register
);
5803 know (e
->X_add_number
>= 0
5804 && (valueT
) e
->X_add_number
< i386_regtab_size
);
5805 r
= i386_regtab
+ e
->X_add_number
;
5806 *end_op
= input_line_pointer
;
5808 *input_line_pointer
= c
;
5809 input_line_pointer
= save
;
5815 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
5818 char *end
= input_line_pointer
;
5821 r
= parse_register (name
, &input_line_pointer
);
5822 if (r
&& end
<= input_line_pointer
)
5824 *nextcharP
= *input_line_pointer
;
5825 *input_line_pointer
= 0;
5826 e
->X_op
= O_register
;
5827 e
->X_add_number
= r
- i386_regtab
;
5830 input_line_pointer
= end
;
5836 md_operand (expressionS
*e
)
5838 if (*input_line_pointer
== REGISTER_PREFIX
)
5841 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
5845 e
->X_op
= O_register
;
5846 e
->X_add_number
= r
- i386_regtab
;
5847 input_line_pointer
= end
;
5853 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5854 const char *md_shortopts
= "kVQ:sqn";
5856 const char *md_shortopts
= "qn";
5859 #define OPTION_32 (OPTION_MD_BASE + 0)
5860 #define OPTION_64 (OPTION_MD_BASE + 1)
5861 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5862 #define OPTION_MARCH (OPTION_MD_BASE + 3)
5863 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
5865 struct option md_longopts
[] =
5867 {"32", no_argument
, NULL
, OPTION_32
},
5868 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5869 {"64", no_argument
, NULL
, OPTION_64
},
5871 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
5872 {"march", required_argument
, NULL
, OPTION_MARCH
},
5873 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
5874 {NULL
, no_argument
, NULL
, 0}
5876 size_t md_longopts_size
= sizeof (md_longopts
);
5879 md_parse_option (int c
, char *arg
)
5886 optimize_align_code
= 0;
5893 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5894 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5895 should be emitted or not. FIXME: Not implemented. */
5899 /* -V: SVR4 argument to print version ID. */
5901 print_version_id ();
5904 /* -k: Ignore for FreeBSD compatibility. */
5909 /* -s: On i386 Solaris, this tells the native assembler to use
5910 .stab instead of .stab.excl. We always use .stab anyhow. */
5913 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5916 const char **list
, **l
;
5918 list
= bfd_target_list ();
5919 for (l
= list
; *l
!= NULL
; l
++)
5920 if (CONST_STRNEQ (*l
, "elf64-x86-64")
5921 || strcmp (*l
, "coff-x86-64") == 0
5922 || strcmp (*l
, "pe-x86-64") == 0
5923 || strcmp (*l
, "pei-x86-64") == 0)
5925 default_arch
= "x86_64";
5929 as_fatal (_("No compiled in support for x86_64"));
5936 default_arch
= "i386";
5940 #ifdef SVR4_COMMENT_CHARS
5945 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
5947 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
5951 i386_comment_chars
= n
;
5958 as_fatal (_("Invalid -march= option: `%s'"), arg
);
5959 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
5961 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
5963 cpu_arch_isa
= cpu_arch
[i
].type
;
5964 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
5965 if (!cpu_arch_tune_set
)
5967 cpu_arch_tune
= cpu_arch_isa
;
5968 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
5973 if (i
>= ARRAY_SIZE (cpu_arch
))
5974 as_fatal (_("Invalid -march= option: `%s'"), arg
);
5979 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
5980 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
5982 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
5984 cpu_arch_tune_set
= 1;
5985 cpu_arch_tune
= cpu_arch
[i
].type
;
5986 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
5990 if (i
>= ARRAY_SIZE (cpu_arch
))
5991 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
6001 md_show_usage (stream
)
6004 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6005 fprintf (stream
, _("\
6007 -V print assembler version number\n\
6010 fprintf (stream
, _("\
6011 -n Do not optimize code alignment\n\
6012 -q quieten some warnings\n"));
6013 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6014 fprintf (stream
, _("\
6017 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6018 fprintf (stream
, _("\
6019 --32/--64 generate 32bit/64bit code\n"));
6021 #ifdef SVR4_COMMENT_CHARS
6022 fprintf (stream
, _("\
6023 --divide do not treat `/' as a comment character\n"));
6025 fprintf (stream
, _("\
6026 --divide ignored\n"));
6028 fprintf (stream
, _("\
6029 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6030 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
6031 core, core2, k6, athlon, k8, generic32, generic64\n"));
6037 x86_64_target_format (void)
6039 if (strcmp (default_arch
, "x86_64") == 0)
6041 set_code_flag (CODE_64BIT
);
6042 return COFF_TARGET_FORMAT
;
6044 else if (strcmp (default_arch
, "i386") == 0)
6046 set_code_flag (CODE_32BIT
);
6050 as_fatal (_("Unknown architecture"));
6055 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6056 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6058 /* Pick the target format to use. */
6061 i386_target_format (void)
6063 if (!strcmp (default_arch
, "x86_64"))
6065 set_code_flag (CODE_64BIT
);
6066 if (cpu_arch_isa_flags
== 0)
6067 cpu_arch_isa_flags
= Cpu186
|Cpu286
|Cpu386
|Cpu486
6068 |Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
6070 if (cpu_arch_tune_flags
== 0)
6071 cpu_arch_tune_flags
= Cpu186
|Cpu286
|Cpu386
|Cpu486
6072 |Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
6075 else if (!strcmp (default_arch
, "i386"))
6077 set_code_flag (CODE_32BIT
);
6078 if (cpu_arch_isa_flags
== 0)
6079 cpu_arch_isa_flags
= Cpu186
|Cpu286
|Cpu386
;
6080 if (cpu_arch_tune_flags
== 0)
6081 cpu_arch_tune_flags
= Cpu186
|Cpu286
|Cpu386
;
6084 as_fatal (_("Unknown architecture"));
6085 switch (OUTPUT_FLAVOR
)
6087 #ifdef OBJ_MAYBE_AOUT
6088 case bfd_target_aout_flavour
:
6089 return AOUT_TARGET_FORMAT
;
6091 #ifdef OBJ_MAYBE_COFF
6092 case bfd_target_coff_flavour
:
6095 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6096 case bfd_target_elf_flavour
:
6098 if (flag_code
== CODE_64BIT
)
6101 use_rela_relocations
= 1;
6103 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
6112 #endif /* OBJ_MAYBE_ more than one */
6114 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6116 i386_elf_emit_arch_note (void)
6118 if (IS_ELF
&& cpu_arch_name
!= NULL
)
6121 asection
*seg
= now_seg
;
6122 subsegT subseg
= now_subseg
;
6123 Elf_Internal_Note i_note
;
6124 Elf_External_Note e_note
;
6125 asection
*note_secp
;
6128 /* Create the .note section. */
6129 note_secp
= subseg_new (".note", 0);
6130 bfd_set_section_flags (stdoutput
,
6132 SEC_HAS_CONTENTS
| SEC_READONLY
);
6134 /* Process the arch string. */
6135 len
= strlen (cpu_arch_name
);
6137 i_note
.namesz
= len
+ 1;
6139 i_note
.type
= NT_ARCH
;
6140 p
= frag_more (sizeof (e_note
.namesz
));
6141 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
6142 p
= frag_more (sizeof (e_note
.descsz
));
6143 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
6144 p
= frag_more (sizeof (e_note
.type
));
6145 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
6146 p
= frag_more (len
+ 1);
6147 strcpy (p
, cpu_arch_name
);
6149 frag_align (2, 0, 0);
6151 subseg_set (seg
, subseg
);
6157 md_undefined_symbol (name
)
6160 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
6161 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
6162 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
6163 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
6167 if (symbol_find (name
))
6168 as_bad (_("GOT already in symbol table"));
6169 GOT_symbol
= symbol_new (name
, undefined_section
,
6170 (valueT
) 0, &zero_address_frag
);
6177 /* Round up a section size to the appropriate boundary. */
6180 md_section_align (segment
, size
)
6181 segT segment ATTRIBUTE_UNUSED
;
6184 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6185 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
6187 /* For a.out, force the section size to be aligned. If we don't do
6188 this, BFD will align it for us, but it will not write out the
6189 final bytes of the section. This may be a bug in BFD, but it is
6190 easier to fix it here since that is how the other a.out targets
6194 align
= bfd_get_section_alignment (stdoutput
, segment
);
6195 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
6202 /* On the i386, PC-relative offsets are relative to the start of the
6203 next instruction. That is, the address of the offset, plus its
6204 size, since the offset is always the last part of the insn. */
6207 md_pcrel_from (fixS
*fixP
)
6209 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6215 s_bss (int ignore ATTRIBUTE_UNUSED
)
6219 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6221 obj_elf_section_change_hook ();
6223 temp
= get_absolute_expression ();
6224 subseg_set (bss_section
, (subsegT
) temp
);
6225 demand_empty_rest_of_line ();
6231 i386_validate_fix (fixS
*fixp
)
6233 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
6235 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
6239 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
6244 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
6246 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
6253 tc_gen_reloc (section
, fixp
)
6254 asection
*section ATTRIBUTE_UNUSED
;
6258 bfd_reloc_code_real_type code
;
6260 switch (fixp
->fx_r_type
)
6262 case BFD_RELOC_X86_64_PLT32
:
6263 case BFD_RELOC_X86_64_GOT32
:
6264 case BFD_RELOC_X86_64_GOTPCREL
:
6265 case BFD_RELOC_386_PLT32
:
6266 case BFD_RELOC_386_GOT32
:
6267 case BFD_RELOC_386_GOTOFF
:
6268 case BFD_RELOC_386_GOTPC
:
6269 case BFD_RELOC_386_TLS_GD
:
6270 case BFD_RELOC_386_TLS_LDM
:
6271 case BFD_RELOC_386_TLS_LDO_32
:
6272 case BFD_RELOC_386_TLS_IE_32
:
6273 case BFD_RELOC_386_TLS_IE
:
6274 case BFD_RELOC_386_TLS_GOTIE
:
6275 case BFD_RELOC_386_TLS_LE_32
:
6276 case BFD_RELOC_386_TLS_LE
:
6277 case BFD_RELOC_386_TLS_GOTDESC
:
6278 case BFD_RELOC_386_TLS_DESC_CALL
:
6279 case BFD_RELOC_X86_64_TLSGD
:
6280 case BFD_RELOC_X86_64_TLSLD
:
6281 case BFD_RELOC_X86_64_DTPOFF32
:
6282 case BFD_RELOC_X86_64_DTPOFF64
:
6283 case BFD_RELOC_X86_64_GOTTPOFF
:
6284 case BFD_RELOC_X86_64_TPOFF32
:
6285 case BFD_RELOC_X86_64_TPOFF64
:
6286 case BFD_RELOC_X86_64_GOTOFF64
:
6287 case BFD_RELOC_X86_64_GOTPC32
:
6288 case BFD_RELOC_X86_64_GOT64
:
6289 case BFD_RELOC_X86_64_GOTPCREL64
:
6290 case BFD_RELOC_X86_64_GOTPC64
:
6291 case BFD_RELOC_X86_64_GOTPLT64
:
6292 case BFD_RELOC_X86_64_PLTOFF64
:
6293 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
6294 case BFD_RELOC_X86_64_TLSDESC_CALL
:
6296 case BFD_RELOC_VTABLE_ENTRY
:
6297 case BFD_RELOC_VTABLE_INHERIT
:
6299 case BFD_RELOC_32_SECREL
:
6301 code
= fixp
->fx_r_type
;
6303 case BFD_RELOC_X86_64_32S
:
6304 if (!fixp
->fx_pcrel
)
6306 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6307 code
= fixp
->fx_r_type
;
6313 switch (fixp
->fx_size
)
6316 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6317 _("can not do %d byte pc-relative relocation"),
6319 code
= BFD_RELOC_32_PCREL
;
6321 case 1: code
= BFD_RELOC_8_PCREL
; break;
6322 case 2: code
= BFD_RELOC_16_PCREL
; break;
6323 case 4: code
= BFD_RELOC_32_PCREL
; break;
6325 case 8: code
= BFD_RELOC_64_PCREL
; break;
6331 switch (fixp
->fx_size
)
6334 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6335 _("can not do %d byte relocation"),
6337 code
= BFD_RELOC_32
;
6339 case 1: code
= BFD_RELOC_8
; break;
6340 case 2: code
= BFD_RELOC_16
; break;
6341 case 4: code
= BFD_RELOC_32
; break;
6343 case 8: code
= BFD_RELOC_64
; break;
6350 if ((code
== BFD_RELOC_32
6351 || code
== BFD_RELOC_32_PCREL
6352 || code
== BFD_RELOC_X86_64_32S
)
6354 && fixp
->fx_addsy
== GOT_symbol
)
6357 code
= BFD_RELOC_386_GOTPC
;
6359 code
= BFD_RELOC_X86_64_GOTPC32
;
6361 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
6363 && fixp
->fx_addsy
== GOT_symbol
)
6365 code
= BFD_RELOC_X86_64_GOTPC64
;
6368 rel
= (arelent
*) xmalloc (sizeof (arelent
));
6369 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
6370 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6372 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6374 if (!use_rela_relocations
)
6376 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6377 vtable entry to be used in the relocation's section offset. */
6378 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
6379 rel
->address
= fixp
->fx_offset
;
6383 /* Use the rela in 64bit mode. */
6386 if (!fixp
->fx_pcrel
)
6387 rel
->addend
= fixp
->fx_offset
;
6391 case BFD_RELOC_X86_64_PLT32
:
6392 case BFD_RELOC_X86_64_GOT32
:
6393 case BFD_RELOC_X86_64_GOTPCREL
:
6394 case BFD_RELOC_X86_64_TLSGD
:
6395 case BFD_RELOC_X86_64_TLSLD
:
6396 case BFD_RELOC_X86_64_GOTTPOFF
:
6397 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
6398 case BFD_RELOC_X86_64_TLSDESC_CALL
:
6399 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
6402 rel
->addend
= (section
->vma
6404 + fixp
->fx_addnumber
6405 + md_pcrel_from (fixp
));
6410 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
6411 if (rel
->howto
== NULL
)
6413 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6414 _("cannot represent relocation type %s"),
6415 bfd_get_reloc_code_name (code
));
6416 /* Set howto to a garbage value so that we can keep going. */
6417 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
6418 assert (rel
->howto
!= NULL
);
6425 /* Parse operands using Intel syntax. This implements a recursive descent
6426 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6429 FIXME: We do not recognize the full operand grammar defined in the MASM
6430 documentation. In particular, all the structure/union and
6431 high-level macro operands are missing.
6433 Uppercase words are terminals, lower case words are non-terminals.
6434 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6435 bars '|' denote choices. Most grammar productions are implemented in
6436 functions called 'intel_<production>'.
6438 Initial production is 'expr'.
6444 binOp & | AND | \| | OR | ^ | XOR
6446 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6448 constant digits [[ radixOverride ]]
6450 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
6488 => expr expr cmpOp e04
6491 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
6492 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
6494 hexdigit a | b | c | d | e | f
6495 | A | B | C | D | E | F
6501 mulOp * | / | % | MOD | << | SHL | >> | SHR
6505 register specialRegister
6509 segmentRegister CS | DS | ES | FS | GS | SS
6511 specialRegister CR0 | CR2 | CR3 | CR4
6512 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
6513 | TR3 | TR4 | TR5 | TR6 | TR7
6515 We simplify the grammar in obvious places (e.g., register parsing is
6516 done by calling parse_register) and eliminate immediate left recursion
6517 to implement a recursive-descent parser.
6521 expr' cmpOp e04 expr'
6572 /* Parsing structure for the intel syntax parser. Used to implement the
6573 semantic actions for the operand grammar. */
6574 struct intel_parser_s
6576 char *op_string
; /* The string being parsed. */
6577 int got_a_float
; /* Whether the operand is a float. */
6578 int op_modifier
; /* Operand modifier. */
6579 int is_mem
; /* 1 if operand is memory reference. */
6580 int in_offset
; /* >=1 if parsing operand of offset. */
6581 int in_bracket
; /* >=1 if parsing operand in brackets. */
6582 const reg_entry
*reg
; /* Last register reference found. */
6583 char *disp
; /* Displacement string being built. */
6584 char *next_operand
; /* Resume point when splitting operands. */
6587 static struct intel_parser_s intel_parser
;
6589 /* Token structure for parsing intel syntax. */
6592 int code
; /* Token code. */
6593 const reg_entry
*reg
; /* Register entry for register tokens. */
6594 char *str
; /* String representation. */
6597 static struct intel_token cur_token
, prev_token
;
6599 /* Token codes for the intel parser. Since T_SHORT is already used
6600 by COFF, undefine it first to prevent a warning. */
6619 /* Prototypes for intel parser functions. */
6620 static int intel_match_token (int);
6621 static void intel_putback_token (void);
6622 static void intel_get_token (void);
6623 static int intel_expr (void);
6624 static int intel_e04 (void);
6625 static int intel_e05 (void);
6626 static int intel_e06 (void);
6627 static int intel_e09 (void);
6628 static int intel_e10 (void);
6629 static int intel_e11 (void);
6632 i386_intel_operand (char *operand_string
, int got_a_float
)
6637 p
= intel_parser
.op_string
= xstrdup (operand_string
);
6638 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
6642 /* Initialize token holders. */
6643 cur_token
.code
= prev_token
.code
= T_NIL
;
6644 cur_token
.reg
= prev_token
.reg
= NULL
;
6645 cur_token
.str
= prev_token
.str
= NULL
;
6647 /* Initialize parser structure. */
6648 intel_parser
.got_a_float
= got_a_float
;
6649 intel_parser
.op_modifier
= 0;
6650 intel_parser
.is_mem
= 0;
6651 intel_parser
.in_offset
= 0;
6652 intel_parser
.in_bracket
= 0;
6653 intel_parser
.reg
= NULL
;
6654 intel_parser
.disp
[0] = '\0';
6655 intel_parser
.next_operand
= NULL
;
6657 /* Read the first token and start the parser. */
6659 ret
= intel_expr ();
6664 if (cur_token
.code
!= T_NIL
)
6666 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6667 current_templates
->start
->name
, cur_token
.str
);
6670 /* If we found a memory reference, hand it over to i386_displacement
6671 to fill in the rest of the operand fields. */
6672 else if (intel_parser
.is_mem
)
6674 if ((i
.mem_operands
== 1
6675 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
6676 || i
.mem_operands
== 2)
6678 as_bad (_("too many memory references for '%s'"),
6679 current_templates
->start
->name
);
6684 char *s
= intel_parser
.disp
;
6687 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
6688 /* See the comments in intel_bracket_expr. */
6689 as_warn (_("Treating `%s' as memory reference"), operand_string
);
6691 /* Add the displacement expression. */
6693 ret
= i386_displacement (s
, s
+ strlen (s
));
6696 /* Swap base and index in 16-bit memory operands like
6697 [si+bx]. Since i386_index_check is also used in AT&T
6698 mode we have to do that here. */
6701 && (i
.base_reg
->reg_type
& Reg16
)
6702 && (i
.index_reg
->reg_type
& Reg16
)
6703 && i
.base_reg
->reg_num
>= 6
6704 && i
.index_reg
->reg_num
< 6)
6706 const reg_entry
*base
= i
.index_reg
;
6708 i
.index_reg
= i
.base_reg
;
6711 ret
= i386_index_check (operand_string
);
6716 /* Constant and OFFSET expressions are handled by i386_immediate. */
6717 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
6718 || intel_parser
.reg
== NULL
)
6719 ret
= i386_immediate (intel_parser
.disp
);
6721 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
6723 if (!ret
|| !intel_parser
.next_operand
)
6725 intel_parser
.op_string
= intel_parser
.next_operand
;
6726 this_operand
= i
.operands
++;
6730 free (intel_parser
.disp
);
6735 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6739 expr' cmpOp e04 expr'
6744 /* XXX Implement the comparison operators. */
6745 return intel_e04 ();
6762 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6763 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
6765 if (cur_token
.code
== '+')
6767 else if (cur_token
.code
== '-')
6768 nregs
= NUM_ADDRESS_REGS
;
6772 strcat (intel_parser
.disp
, cur_token
.str
);
6773 intel_match_token (cur_token
.code
);
6784 int nregs
= ~NUM_ADDRESS_REGS
;
6791 if (cur_token
.code
== '&'
6792 || cur_token
.code
== '|'
6793 || cur_token
.code
== '^')
6797 str
[0] = cur_token
.code
;
6799 strcat (intel_parser
.disp
, str
);
6804 intel_match_token (cur_token
.code
);
6809 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6810 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
6821 int nregs
= ~NUM_ADDRESS_REGS
;
6828 if (cur_token
.code
== '*'
6829 || cur_token
.code
== '/'
6830 || cur_token
.code
== '%')
6834 str
[0] = cur_token
.code
;
6836 strcat (intel_parser
.disp
, str
);
6838 else if (cur_token
.code
== T_SHL
)
6839 strcat (intel_parser
.disp
, "<<");
6840 else if (cur_token
.code
== T_SHR
)
6841 strcat (intel_parser
.disp
, ">>");
6845 intel_match_token (cur_token
.code
);
6850 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6851 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
6869 int nregs
= ~NUM_ADDRESS_REGS
;
6874 /* Don't consume constants here. */
6875 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6877 /* Need to look one token ahead - if the next token
6878 is a constant, the current token is its sign. */
6881 intel_match_token (cur_token
.code
);
6882 next_code
= cur_token
.code
;
6883 intel_putback_token ();
6884 if (next_code
== T_CONST
)
6888 /* e09 OFFSET e09 */
6889 if (cur_token
.code
== T_OFFSET
)
6892 ++intel_parser
.in_offset
;
6896 else if (cur_token
.code
== T_SHORT
)
6897 intel_parser
.op_modifier
|= 1 << T_SHORT
;
6900 else if (cur_token
.code
== '+')
6901 strcat (intel_parser
.disp
, "+");
6906 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
6912 str
[0] = cur_token
.code
;
6914 strcat (intel_parser
.disp
, str
);
6921 intel_match_token (cur_token
.code
);
6929 /* e09' PTR e10 e09' */
6930 if (cur_token
.code
== T_PTR
)
6934 if (prev_token
.code
== T_BYTE
)
6935 suffix
= BYTE_MNEM_SUFFIX
;
6937 else if (prev_token
.code
== T_WORD
)
6939 if (current_templates
->start
->name
[0] == 'l'
6940 && current_templates
->start
->name
[2] == 's'
6941 && current_templates
->start
->name
[3] == 0)
6942 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6943 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
6944 suffix
= SHORT_MNEM_SUFFIX
;
6946 suffix
= WORD_MNEM_SUFFIX
;
6949 else if (prev_token
.code
== T_DWORD
)
6951 if (current_templates
->start
->name
[0] == 'l'
6952 && current_templates
->start
->name
[2] == 's'
6953 && current_templates
->start
->name
[3] == 0)
6954 suffix
= WORD_MNEM_SUFFIX
;
6955 else if (flag_code
== CODE_16BIT
6956 && (current_templates
->start
->opcode_modifier
6957 & (Jump
| JumpDword
)))
6958 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6959 else if (intel_parser
.got_a_float
== 1) /* "f..." */
6960 suffix
= SHORT_MNEM_SUFFIX
;
6962 suffix
= LONG_MNEM_SUFFIX
;
6965 else if (prev_token
.code
== T_FWORD
)
6967 if (current_templates
->start
->name
[0] == 'l'
6968 && current_templates
->start
->name
[2] == 's'
6969 && current_templates
->start
->name
[3] == 0)
6970 suffix
= LONG_MNEM_SUFFIX
;
6971 else if (!intel_parser
.got_a_float
)
6973 if (flag_code
== CODE_16BIT
)
6974 add_prefix (DATA_PREFIX_OPCODE
);
6975 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6978 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6981 else if (prev_token
.code
== T_QWORD
)
6983 if (intel_parser
.got_a_float
== 1) /* "f..." */
6984 suffix
= LONG_MNEM_SUFFIX
;
6986 suffix
= QWORD_MNEM_SUFFIX
;
6989 else if (prev_token
.code
== T_TBYTE
)
6991 if (intel_parser
.got_a_float
== 1)
6992 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6994 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6997 else if (prev_token
.code
== T_XMMWORD
)
6999 /* XXX ignored for now, but accepted since gcc uses it */
7005 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
7009 /* Operands for jump/call using 'ptr' notation denote absolute
7011 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
))
7012 i
.types
[this_operand
] |= JumpAbsolute
;
7014 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
7018 else if (i
.suffix
!= suffix
)
7020 as_bad (_("Conflicting operand modifiers"));
7026 /* e09' : e10 e09' */
7027 else if (cur_token
.code
== ':')
7029 if (prev_token
.code
!= T_REG
)
7031 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7032 segment/group identifier (which we don't have), using comma
7033 as the operand separator there is even less consistent, since
7034 there all branches only have a single operand. */
7035 if (this_operand
!= 0
7036 || intel_parser
.in_offset
7037 || intel_parser
.in_bracket
7038 || (!(current_templates
->start
->opcode_modifier
7039 & (Jump
|JumpDword
|JumpInterSegment
))
7040 && !(current_templates
->start
->operand_types
[0]
7042 return intel_match_token (T_NIL
);
7043 /* Remember the start of the 2nd operand and terminate 1st
7045 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7046 another expression), but it gets at least the simplest case
7047 (a plain number or symbol on the left side) right. */
7048 intel_parser
.next_operand
= intel_parser
.op_string
;
7049 *--intel_parser
.op_string
= '\0';
7050 return intel_match_token (':');
7058 intel_match_token (cur_token
.code
);
7064 --intel_parser
.in_offset
;
7067 if (NUM_ADDRESS_REGS
> nregs
)
7069 as_bad (_("Invalid operand to `OFFSET'"));
7072 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
7075 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
7076 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
7081 intel_bracket_expr (void)
7083 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
7084 const char *start
= intel_parser
.op_string
;
7087 if (i
.op
[this_operand
].regs
)
7088 return intel_match_token (T_NIL
);
7090 intel_match_token ('[');
7092 /* Mark as a memory operand only if it's not already known to be an
7093 offset expression. If it's an offset expression, we need to keep
7095 if (!intel_parser
.in_offset
)
7097 ++intel_parser
.in_bracket
;
7099 /* Operands for jump/call inside brackets denote absolute addresses. */
7100 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
))
7101 i
.types
[this_operand
] |= JumpAbsolute
;
7103 /* Unfortunately gas always diverged from MASM in a respect that can't
7104 be easily fixed without risking to break code sequences likely to be
7105 encountered (the testsuite even check for this): MASM doesn't consider
7106 an expression inside brackets unconditionally as a memory reference.
7107 When that is e.g. a constant, an offset expression, or the sum of the
7108 two, this is still taken as a constant load. gas, however, always
7109 treated these as memory references. As a compromise, we'll try to make
7110 offset expressions inside brackets work the MASM way (since that's
7111 less likely to be found in real world code), but make constants alone
7112 continue to work the traditional gas way. In either case, issue a
7114 intel_parser
.op_modifier
&= ~was_offset
;
7117 strcat (intel_parser
.disp
, "[");
7119 /* Add a '+' to the displacement string if necessary. */
7120 if (*intel_parser
.disp
!= '\0'
7121 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
7122 strcat (intel_parser
.disp
, "+");
7125 && (len
= intel_parser
.op_string
- start
- 1,
7126 intel_match_token (']')))
7128 /* Preserve brackets when the operand is an offset expression. */
7129 if (intel_parser
.in_offset
)
7130 strcat (intel_parser
.disp
, "]");
7133 --intel_parser
.in_bracket
;
7134 if (i
.base_reg
|| i
.index_reg
)
7135 intel_parser
.is_mem
= 1;
7136 if (!intel_parser
.is_mem
)
7138 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
7139 /* Defer the warning until all of the operand was parsed. */
7140 intel_parser
.is_mem
= -1;
7141 else if (!quiet_warnings
)
7142 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
7143 len
, start
, len
, start
);
7146 intel_parser
.op_modifier
|= was_offset
;
7163 while (cur_token
.code
== '[')
7165 if (!intel_bracket_expr ())
7190 switch (cur_token
.code
)
7194 intel_match_token ('(');
7195 strcat (intel_parser
.disp
, "(");
7197 if (intel_expr () && intel_match_token (')'))
7199 strcat (intel_parser
.disp
, ")");
7206 return intel_bracket_expr ();
7211 strcat (intel_parser
.disp
, cur_token
.str
);
7212 intel_match_token (cur_token
.code
);
7214 /* Mark as a memory operand only if it's not already known to be an
7215 offset expression. */
7216 if (!intel_parser
.in_offset
)
7217 intel_parser
.is_mem
= 1;
7224 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
7226 intel_match_token (T_REG
);
7228 /* Check for segment change. */
7229 if (cur_token
.code
== ':')
7231 if (!(reg
->reg_type
& (SReg2
| SReg3
)))
7233 as_bad (_("`%s' is not a valid segment register"),
7237 else if (i
.seg
[i
.mem_operands
])
7238 as_warn (_("Extra segment override ignored"));
7241 if (!intel_parser
.in_offset
)
7242 intel_parser
.is_mem
= 1;
7243 switch (reg
->reg_num
)
7246 i
.seg
[i
.mem_operands
] = &es
;
7249 i
.seg
[i
.mem_operands
] = &cs
;
7252 i
.seg
[i
.mem_operands
] = &ss
;
7255 i
.seg
[i
.mem_operands
] = &ds
;
7258 i
.seg
[i
.mem_operands
] = &fs
;
7261 i
.seg
[i
.mem_operands
] = &gs
;
7267 /* Not a segment register. Check for register scaling. */
7268 else if (cur_token
.code
== '*')
7270 if (!intel_parser
.in_bracket
)
7272 as_bad (_("Register scaling only allowed in memory operands"));
7276 if (reg
->reg_type
& Reg16
) /* Disallow things like [si*1]. */
7277 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
7278 else if (i
.index_reg
)
7279 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
7281 /* What follows must be a valid scale. */
7282 intel_match_token ('*');
7284 i
.types
[this_operand
] |= BaseIndex
;
7286 /* Set the scale after setting the register (otherwise,
7287 i386_scale will complain) */
7288 if (cur_token
.code
== '+' || cur_token
.code
== '-')
7290 char *str
, sign
= cur_token
.code
;
7291 intel_match_token (cur_token
.code
);
7292 if (cur_token
.code
!= T_CONST
)
7294 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7298 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
7299 strcpy (str
+ 1, cur_token
.str
);
7301 if (!i386_scale (str
))
7305 else if (!i386_scale (cur_token
.str
))
7307 intel_match_token (cur_token
.code
);
7310 /* No scaling. If this is a memory operand, the register is either a
7311 base register (first occurrence) or an index register (second
7313 else if (intel_parser
.in_bracket
)
7318 else if (!i
.index_reg
)
7322 as_bad (_("Too many register references in memory operand"));
7326 i
.types
[this_operand
] |= BaseIndex
;
7329 /* It's neither base nor index. */
7330 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
7332 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
7333 i
.op
[this_operand
].regs
= reg
;
7338 as_bad (_("Invalid use of register"));
7342 /* Since registers are not part of the displacement string (except
7343 when we're parsing offset operands), we may need to remove any
7344 preceding '+' from the displacement string. */
7345 if (*intel_parser
.disp
!= '\0'
7346 && !intel_parser
.in_offset
)
7348 char *s
= intel_parser
.disp
;
7349 s
+= strlen (s
) - 1;
7372 intel_match_token (cur_token
.code
);
7374 if (cur_token
.code
== T_PTR
)
7377 /* It must have been an identifier. */
7378 intel_putback_token ();
7379 cur_token
.code
= T_ID
;
7385 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
7389 /* The identifier represents a memory reference only if it's not
7390 preceded by an offset modifier and if it's not an equate. */
7391 symbolP
= symbol_find(cur_token
.str
);
7392 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
7393 intel_parser
.is_mem
= 1;
7401 char *save_str
, sign
= 0;
7403 /* Allow constants that start with `+' or `-'. */
7404 if (cur_token
.code
== '-' || cur_token
.code
== '+')
7406 sign
= cur_token
.code
;
7407 intel_match_token (cur_token
.code
);
7408 if (cur_token
.code
!= T_CONST
)
7410 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7416 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
7417 strcpy (save_str
+ !!sign
, cur_token
.str
);
7421 /* Get the next token to check for register scaling. */
7422 intel_match_token (cur_token
.code
);
7424 /* Check if this constant is a scaling factor for an
7426 if (cur_token
.code
== '*')
7428 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
7430 const reg_entry
*reg
= cur_token
.reg
;
7432 if (!intel_parser
.in_bracket
)
7434 as_bad (_("Register scaling only allowed "
7435 "in memory operands"));
7439 /* Disallow things like [1*si].
7440 sp and esp are invalid as index. */
7441 if (reg
->reg_type
& Reg16
)
7442 reg
= i386_regtab
+ REGNAM_AX
+ 4;
7443 else if (i
.index_reg
)
7444 reg
= i386_regtab
+ REGNAM_EAX
+ 4;
7446 /* The constant is followed by `* reg', so it must be
7449 i
.types
[this_operand
] |= BaseIndex
;
7451 /* Set the scale after setting the register (otherwise,
7452 i386_scale will complain) */
7453 if (!i386_scale (save_str
))
7455 intel_match_token (T_REG
);
7457 /* Since registers are not part of the displacement
7458 string, we may need to remove any preceding '+' from
7459 the displacement string. */
7460 if (*intel_parser
.disp
!= '\0')
7462 char *s
= intel_parser
.disp
;
7463 s
+= strlen (s
) - 1;
7473 /* The constant was not used for register scaling. Since we have
7474 already consumed the token following `*' we now need to put it
7475 back in the stream. */
7476 intel_putback_token ();
7479 /* Add the constant to the displacement string. */
7480 strcat (intel_parser
.disp
, save_str
);
7487 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
7491 /* Match the given token against cur_token. If they match, read the next
7492 token from the operand string. */
7494 intel_match_token (int code
)
7496 if (cur_token
.code
== code
)
7503 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
7508 /* Read a new token from intel_parser.op_string and store it in cur_token. */
7510 intel_get_token (void)
7513 const reg_entry
*reg
;
7514 struct intel_token new_token
;
7516 new_token
.code
= T_NIL
;
7517 new_token
.reg
= NULL
;
7518 new_token
.str
= NULL
;
7520 /* Free the memory allocated to the previous token and move
7521 cur_token to prev_token. */
7523 free (prev_token
.str
);
7525 prev_token
= cur_token
;
7527 /* Skip whitespace. */
7528 while (is_space_char (*intel_parser
.op_string
))
7529 intel_parser
.op_string
++;
7531 /* Return an empty token if we find nothing else on the line. */
7532 if (*intel_parser
.op_string
== '\0')
7534 cur_token
= new_token
;
7538 /* The new token cannot be larger than the remainder of the operand
7540 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
7541 new_token
.str
[0] = '\0';
7543 if (strchr ("0123456789", *intel_parser
.op_string
))
7545 char *p
= new_token
.str
;
7546 char *q
= intel_parser
.op_string
;
7547 new_token
.code
= T_CONST
;
7549 /* Allow any kind of identifier char to encompass floating point and
7550 hexadecimal numbers. */
7551 while (is_identifier_char (*q
))
7555 /* Recognize special symbol names [0-9][bf]. */
7556 if (strlen (intel_parser
.op_string
) == 2
7557 && (intel_parser
.op_string
[1] == 'b'
7558 || intel_parser
.op_string
[1] == 'f'))
7559 new_token
.code
= T_ID
;
7562 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
7564 size_t len
= end_op
- intel_parser
.op_string
;
7566 new_token
.code
= T_REG
;
7567 new_token
.reg
= reg
;
7569 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
7570 new_token
.str
[len
] = '\0';
7573 else if (is_identifier_char (*intel_parser
.op_string
))
7575 char *p
= new_token
.str
;
7576 char *q
= intel_parser
.op_string
;
7578 /* A '.' or '$' followed by an identifier char is an identifier.
7579 Otherwise, it's operator '.' followed by an expression. */
7580 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
7582 new_token
.code
= '.';
7583 new_token
.str
[0] = '.';
7584 new_token
.str
[1] = '\0';
7588 while (is_identifier_char (*q
) || *q
== '@')
7592 if (strcasecmp (new_token
.str
, "NOT") == 0)
7593 new_token
.code
= '~';
7595 else if (strcasecmp (new_token
.str
, "MOD") == 0)
7596 new_token
.code
= '%';
7598 else if (strcasecmp (new_token
.str
, "AND") == 0)
7599 new_token
.code
= '&';
7601 else if (strcasecmp (new_token
.str
, "OR") == 0)
7602 new_token
.code
= '|';
7604 else if (strcasecmp (new_token
.str
, "XOR") == 0)
7605 new_token
.code
= '^';
7607 else if (strcasecmp (new_token
.str
, "SHL") == 0)
7608 new_token
.code
= T_SHL
;
7610 else if (strcasecmp (new_token
.str
, "SHR") == 0)
7611 new_token
.code
= T_SHR
;
7613 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
7614 new_token
.code
= T_BYTE
;
7616 else if (strcasecmp (new_token
.str
, "WORD") == 0)
7617 new_token
.code
= T_WORD
;
7619 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
7620 new_token
.code
= T_DWORD
;
7622 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
7623 new_token
.code
= T_FWORD
;
7625 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
7626 new_token
.code
= T_QWORD
;
7628 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
7629 /* XXX remove (gcc still uses it) */
7630 || strcasecmp (new_token
.str
, "XWORD") == 0)
7631 new_token
.code
= T_TBYTE
;
7633 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
7634 || strcasecmp (new_token
.str
, "OWORD") == 0)
7635 new_token
.code
= T_XMMWORD
;
7637 else if (strcasecmp (new_token
.str
, "PTR") == 0)
7638 new_token
.code
= T_PTR
;
7640 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
7641 new_token
.code
= T_SHORT
;
7643 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
7645 new_token
.code
= T_OFFSET
;
7647 /* ??? This is not mentioned in the MASM grammar but gcc
7648 makes use of it with -mintel-syntax. OFFSET may be
7649 followed by FLAT: */
7650 if (strncasecmp (q
, " FLAT:", 6) == 0)
7651 strcat (new_token
.str
, " FLAT:");
7654 /* ??? This is not mentioned in the MASM grammar. */
7655 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
7657 new_token
.code
= T_OFFSET
;
7659 strcat (new_token
.str
, ":");
7661 as_bad (_("`:' expected"));
7665 new_token
.code
= T_ID
;
7669 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
7671 new_token
.code
= *intel_parser
.op_string
;
7672 new_token
.str
[0] = *intel_parser
.op_string
;
7673 new_token
.str
[1] = '\0';
7676 else if (strchr ("<>", *intel_parser
.op_string
)
7677 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
7679 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
7680 new_token
.str
[0] = *intel_parser
.op_string
;
7681 new_token
.str
[1] = *intel_parser
.op_string
;
7682 new_token
.str
[2] = '\0';
7686 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
7688 intel_parser
.op_string
+= strlen (new_token
.str
);
7689 cur_token
= new_token
;
7692 /* Put cur_token back into the token stream and make cur_token point to
7695 intel_putback_token (void)
7697 if (cur_token
.code
!= T_NIL
)
7699 intel_parser
.op_string
-= strlen (cur_token
.str
);
7700 free (cur_token
.str
);
7702 cur_token
= prev_token
;
7704 /* Forget prev_token. */
7705 prev_token
.code
= T_NIL
;
7706 prev_token
.reg
= NULL
;
7707 prev_token
.str
= NULL
;
7711 tc_x86_regname_to_dw2regnum (char *regname
)
7713 unsigned int regnum
;
7714 unsigned int regnames_count
;
7715 static const char *const regnames_32
[] =
7717 "eax", "ecx", "edx", "ebx",
7718 "esp", "ebp", "esi", "edi",
7719 "eip", "eflags", NULL
,
7720 "st0", "st1", "st2", "st3",
7721 "st4", "st5", "st6", "st7",
7723 "xmm0", "xmm1", "xmm2", "xmm3",
7724 "xmm4", "xmm5", "xmm6", "xmm7",
7725 "mm0", "mm1", "mm2", "mm3",
7726 "mm4", "mm5", "mm6", "mm7",
7727 "fcw", "fsw", "mxcsr",
7728 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
7731 static const char *const regnames_64
[] =
7733 "rax", "rdx", "rcx", "rbx",
7734 "rsi", "rdi", "rbp", "rsp",
7735 "r8", "r9", "r10", "r11",
7736 "r12", "r13", "r14", "r15",
7738 "xmm0", "xmm1", "xmm2", "xmm3",
7739 "xmm4", "xmm5", "xmm6", "xmm7",
7740 "xmm8", "xmm9", "xmm10", "xmm11",
7741 "xmm12", "xmm13", "xmm14", "xmm15",
7742 "st0", "st1", "st2", "st3",
7743 "st4", "st5", "st6", "st7",
7744 "mm0", "mm1", "mm2", "mm3",
7745 "mm4", "mm5", "mm6", "mm7",
7747 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
7748 "fs.base", "gs.base", NULL
, NULL
,
7750 "mxcsr", "fcw", "fsw"
7752 const char *const *regnames
;
7754 if (flag_code
== CODE_64BIT
)
7756 regnames
= regnames_64
;
7757 regnames_count
= ARRAY_SIZE (regnames_64
);
7761 regnames
= regnames_32
;
7762 regnames_count
= ARRAY_SIZE (regnames_32
);
7765 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
7766 if (regnames
[regnum
] != NULL
7767 && strcmp (regname
, regnames
[regnum
]) == 0)
7774 tc_x86_frame_initial_instructions (void)
7776 static unsigned int sp_regno
;
7779 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
7782 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
7783 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
7787 i386_elf_section_type (const char *str
, size_t len
)
7789 if (flag_code
== CODE_64BIT
7790 && len
== sizeof ("unwind") - 1
7791 && strncmp (str
, "unwind", 6) == 0)
7792 return SHT_X86_64_UNWIND
;
7799 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
7803 expr
.X_op
= O_secrel
;
7804 expr
.X_add_symbol
= symbol
;
7805 expr
.X_add_number
= 0;
7806 emit_expr (&expr
, size
);
7810 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7811 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7814 x86_64_section_letter (int letter
, char **ptr_msg
)
7816 if (flag_code
== CODE_64BIT
)
7819 return SHF_X86_64_LARGE
;
7821 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7824 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
7829 x86_64_section_word (char *str
, size_t len
)
7831 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
7832 return SHF_X86_64_LARGE
;
7838 handle_large_common (int small ATTRIBUTE_UNUSED
)
7840 if (flag_code
!= CODE_64BIT
)
7842 s_comm_internal (0, elf_common_parse
);
7843 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7847 static segT lbss_section
;
7848 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
7849 asection
*saved_bss_section
= bss_section
;
7851 if (lbss_section
== NULL
)
7853 flagword applicable
;
7855 subsegT subseg
= now_subseg
;
7857 /* The .lbss section is for local .largecomm symbols. */
7858 lbss_section
= subseg_new (".lbss", 0);
7859 applicable
= bfd_applicable_section_flags (stdoutput
);
7860 bfd_set_section_flags (stdoutput
, lbss_section
,
7861 applicable
& SEC_ALLOC
);
7862 seg_info (lbss_section
)->bss
= 1;
7864 subseg_set (seg
, subseg
);
7867 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
7868 bss_section
= lbss_section
;
7870 s_comm_internal (0, elf_common_parse
);
7872 elf_com_section_ptr
= saved_com_section_ptr
;
7873 bss_section
= saved_bss_section
;
7876 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */