1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Intel 80386 machine specific gas.
23 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
24 x86_64 support by Jan Hubicka (jh@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
32 #include "dwarf2dbg.h"
33 #include "opcode/i386.h"
35 #ifndef REGISTER_WARNINGS
36 #define REGISTER_WARNINGS 1
39 #ifndef INFER_ADDR_PREFIX
40 #define INFER_ADDR_PREFIX 1
43 #ifndef SCALE1_WHEN_NO_INDEX
44 /* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48 #define SCALE1_WHEN_NO_INDEX 1
54 static unsigned int mode_from_disp_size
PARAMS ((unsigned int));
55 static int fits_in_signed_byte
PARAMS ((offsetT
));
56 static int fits_in_unsigned_byte
PARAMS ((offsetT
));
57 static int fits_in_unsigned_word
PARAMS ((offsetT
));
58 static int fits_in_signed_word
PARAMS ((offsetT
));
59 static int fits_in_unsigned_long
PARAMS ((offsetT
));
60 static int fits_in_signed_long
PARAMS ((offsetT
));
61 static int smallest_imm_type
PARAMS ((offsetT
));
62 static offsetT offset_in_range
PARAMS ((offsetT
, int));
63 static int add_prefix
PARAMS ((unsigned int));
64 static void set_code_flag
PARAMS ((int));
65 static void set_16bit_gcc_code_flag
PARAMS ((int));
66 static void set_intel_syntax
PARAMS ((int));
67 static void set_cpu_arch
PARAMS ((int));
70 static bfd_reloc_code_real_type reloc
71 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
75 #define DEFAULT_ARCH "i386"
77 static char *default_arch
= DEFAULT_ARCH
;
79 /* 'md_assemble ()' gathers together information and puts it into a
86 const reg_entry
*regs
;
91 /* TM holds the template for the insn were currently assembling. */
94 /* SUFFIX holds the instruction mnemonic suffix if given.
95 (e.g. 'l' for 'movl') */
98 /* OPERANDS gives the number of given operands. */
99 unsigned int operands
;
101 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
102 of given register, displacement, memory operands and immediate
104 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
106 /* TYPES [i] is the type (see above #defines) which tells us how to
107 use OP[i] for the corresponding operand. */
108 unsigned int types
[MAX_OPERANDS
];
110 /* Displacement expression, immediate expression, or register for each
112 union i386_op op
[MAX_OPERANDS
];
114 /* Flags for operands. */
115 unsigned int flags
[MAX_OPERANDS
];
116 #define Operand_PCrel 1
118 /* Relocation type for operand */
120 enum bfd_reloc_code_real disp_reloc
[MAX_OPERANDS
];
122 int disp_reloc
[MAX_OPERANDS
];
125 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
126 the base index byte below. */
127 const reg_entry
*base_reg
;
128 const reg_entry
*index_reg
;
129 unsigned int log2_scale_factor
;
131 /* SEG gives the seg_entries of this insn. They are zero unless
132 explicit segment overrides are given. */
133 const seg_entry
*seg
[2];
135 /* PREFIX holds all the given prefix opcodes (usually null).
136 PREFIXES is the number of prefix opcodes. */
137 unsigned int prefixes
;
138 unsigned char prefix
[MAX_PREFIXES
];
140 /* RM and SIB are the modrm byte and the sib byte where the
141 addressing modes of this insn are encoded. */
148 typedef struct _i386_insn i386_insn
;
150 /* List of chars besides those in app.c:symbol_chars that can start an
151 operand. Used to prevent the scrubber eating vital white-space. */
153 const char extra_symbol_chars
[] = "*%-(@";
155 const char extra_symbol_chars
[] = "*%-(";
158 /* This array holds the chars that always start a comment. If the
159 pre-processor is disabled, these aren't very useful. */
160 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
161 /* Putting '/' here makes it impossible to use the divide operator.
162 However, we need it for compatibility with SVR4 systems. */
163 const char comment_chars
[] = "#/";
164 #define PREFIX_SEPARATOR '\\'
166 const char comment_chars
[] = "#";
167 #define PREFIX_SEPARATOR '/'
170 /* This array holds the chars that only start a comment at the beginning of
171 a line. If the line seems to have the form '# 123 filename'
172 .line and .file directives will appear in the pre-processed output.
173 Note that input_file.c hand checks for '#' at the beginning of the
174 first line of the input file. This is because the compiler outputs
175 #NO_APP at the beginning of its output.
176 Also note that comments started like this one will always work if
177 '/' isn't otherwise defined. */
178 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
179 const char line_comment_chars
[] = "";
181 const char line_comment_chars
[] = "/";
184 const char line_separator_chars
[] = ";";
186 /* Chars that can be used to separate mant from exp in floating point
188 const char EXP_CHARS
[] = "eE";
190 /* Chars that mean this number is a floating point constant
193 const char FLT_CHARS
[] = "fFdDxX";
195 /* Tables for lexical analysis. */
196 static char mnemonic_chars
[256];
197 static char register_chars
[256];
198 static char operand_chars
[256];
199 static char identifier_chars
[256];
200 static char digit_chars
[256];
202 /* Lexical macros. */
203 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
204 #define is_operand_char(x) (operand_chars[(unsigned char) x])
205 #define is_register_char(x) (register_chars[(unsigned char) x])
206 #define is_space_char(x) ((x) == ' ')
207 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
208 #define is_digit_char(x) (digit_chars[(unsigned char) x])
210 /* All non-digit non-letter charcters that may occur in an operand. */
211 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
213 /* md_assemble() always leaves the strings it's passed unaltered. To
214 effect this we maintain a stack of saved characters that we've smashed
215 with '\0's (indicating end of strings for various sub-fields of the
216 assembler instruction). */
217 static char save_stack
[32];
218 static char *save_stack_p
;
219 #define END_STRING_AND_SAVE(s) \
220 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
221 #define RESTORE_END_STRING(s) \
222 do { *(s) = *--save_stack_p; } while (0)
224 /* The instruction we're assembling. */
227 /* Possible templates for current insn. */
228 static const templates
*current_templates
;
230 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
231 static expressionS disp_expressions
[2], im_expressions
[2];
233 /* Current operand we are working on. */
234 static int this_operand
;
236 /* We support four different modes. FLAG_CODE variable is used to distinguish
244 static enum flag_code flag_code
;
245 static int use_rela_relocations
= 0;
247 /* The names used to print error messages. */
248 static const char *flag_code_names
[] =
255 /* 1 for intel syntax,
257 static int intel_syntax
= 0;
259 /* 1 if register prefix % not required. */
260 static int allow_naked_reg
= 0;
262 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
263 leave, push, and pop instructions so that gcc has the same stack
264 frame as in 32 bit mode. */
265 static char stackop_size
= '\0';
267 /* Non-zero to quieten some warnings. */
268 static int quiet_warnings
= 0;
271 static const char *cpu_arch_name
= NULL
;
273 /* CPU feature flags. */
274 static unsigned int cpu_arch_flags
= CpuUnknownFlags
|CpuNo64
;
276 /* Interface to relax_segment.
277 There are 2 relax states for 386 jump insns: one for conditional &
278 one for unconditional jumps. This is because these two types of
279 jumps add different sizes to frags when we're figuring out what
280 sort of jump to choose to reach a given label. */
284 #define UNCOND_JUMP 2
288 #define SMALL16 (SMALL|CODE16)
290 #define BIG16 (BIG|CODE16)
294 #define INLINE __inline__
300 #define ENCODE_RELAX_STATE(type,size) \
301 ((relax_substateT) ((type<<2) | (size)))
302 #define SIZE_FROM_RELAX_STATE(s) \
303 ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) )
305 /* This table is used by relax_frag to promote short jumps to long
306 ones where necessary. SMALL (short) jumps may be promoted to BIG
307 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
308 don't allow a short jump in a 32 bit code segment to be promoted to
309 a 16 bit offset jump because it's slower (requires data size
310 prefix), and doesn't work, unless the destination is in the bottom
311 64k of the code segment (The top 16 bits of eip are zeroed). */
313 const relax_typeS md_relax_table
[] =
316 1) most positive reach of this state,
317 2) most negative reach of this state,
318 3) how many bytes this mode will add to the size of the current frag
319 4) which index into the table to try if we can't fit into this one. */
325 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
326 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
327 /* dword conditionals adds 4 bytes to frag:
328 1 extra opcode byte, 3 extra displacement bytes. */
330 /* word conditionals add 2 bytes to frag:
331 1 extra opcode byte, 1 extra displacement byte. */
334 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
335 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
336 /* dword jmp adds 3 bytes to frag:
337 0 extra opcode bytes, 3 extra displacement bytes. */
339 /* word jmp adds 1 byte to frag:
340 0 extra opcode bytes, 1 extra displacement byte. */
345 static const arch_entry cpu_arch
[] = {
347 {"i186", Cpu086
|Cpu186
},
348 {"i286", Cpu086
|Cpu186
|Cpu286
},
349 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
350 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
351 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
352 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
353 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
354 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
355 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
356 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
357 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
358 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
363 i386_align_code (fragP
, count
)
367 /* Various efficient no-op patterns for aligning code labels.
368 Note: Don't try to assemble the instructions in the comments.
369 0L and 0w are not legal. */
370 static const char f32_1
[] =
372 static const char f32_2
[] =
373 {0x89,0xf6}; /* movl %esi,%esi */
374 static const char f32_3
[] =
375 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
376 static const char f32_4
[] =
377 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
378 static const char f32_5
[] =
380 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
381 static const char f32_6
[] =
382 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
383 static const char f32_7
[] =
384 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
385 static const char f32_8
[] =
387 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
388 static const char f32_9
[] =
389 {0x89,0xf6, /* movl %esi,%esi */
390 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
391 static const char f32_10
[] =
392 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
393 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
394 static const char f32_11
[] =
395 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
396 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
397 static const char f32_12
[] =
398 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
399 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
400 static const char f32_13
[] =
401 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
402 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
403 static const char f32_14
[] =
404 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
405 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
406 static const char f32_15
[] =
407 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
408 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
409 static const char f16_3
[] =
410 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
411 static const char f16_4
[] =
412 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
413 static const char f16_5
[] =
415 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
416 static const char f16_6
[] =
417 {0x89,0xf6, /* mov %si,%si */
418 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
419 static const char f16_7
[] =
420 {0x8d,0x74,0x00, /* lea 0(%si),%si */
421 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
422 static const char f16_8
[] =
423 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
424 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
425 static const char *const f32_patt
[] = {
426 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
427 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
429 static const char *const f16_patt
[] = {
430 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
431 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
434 /* ??? We can't use these fillers for x86_64, since they often kills the
435 upper halves. Solve later. */
436 if (flag_code
== CODE_64BIT
)
439 if (count
> 0 && count
<= 15)
441 if (flag_code
== CODE_16BIT
)
443 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
444 f16_patt
[count
- 1], count
);
446 /* Adjust jump offset. */
447 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
450 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
451 f32_patt
[count
- 1], count
);
452 fragP
->fr_var
= count
;
456 static char *output_invalid
PARAMS ((int c
));
457 static int i386_operand
PARAMS ((char *operand_string
));
458 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
459 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
463 static void s_bss
PARAMS ((int));
466 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
468 static INLINE
unsigned int
469 mode_from_disp_size (t
)
472 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
476 fits_in_signed_byte (num
)
479 return (num
>= -128) && (num
<= 127);
483 fits_in_unsigned_byte (num
)
486 return (num
& 0xff) == num
;
490 fits_in_unsigned_word (num
)
493 return (num
& 0xffff) == num
;
497 fits_in_signed_word (num
)
500 return (-32768 <= num
) && (num
<= 32767);
503 fits_in_signed_long (num
)
504 offsetT num ATTRIBUTE_UNUSED
;
509 return (!(((offsetT
) -1 << 31) & num
)
510 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
512 } /* fits_in_signed_long() */
514 fits_in_unsigned_long (num
)
515 offsetT num ATTRIBUTE_UNUSED
;
520 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
522 } /* fits_in_unsigned_long() */
525 smallest_imm_type (num
)
528 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
)
529 && !(cpu_arch_flags
& (CpuUnknown
)))
531 /* This code is disabled on the 486 because all the Imm1 forms
532 in the opcode table are slower on the i486. They're the
533 versions with the implicitly specified single-position
534 displacement, which has another syntax if you really want to
537 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
539 return (fits_in_signed_byte (num
)
540 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
541 : fits_in_unsigned_byte (num
)
542 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
543 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
544 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
545 : fits_in_signed_long (num
)
546 ? (Imm32
| Imm32S
| Imm64
)
547 : fits_in_unsigned_long (num
)
553 offset_in_range (val
, size
)
561 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
562 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
563 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
565 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
570 /* If BFD64, sign extend val. */
571 if (!use_rela_relocations
)
572 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
573 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
575 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
577 char buf1
[40], buf2
[40];
579 sprint_value (buf1
, val
);
580 sprint_value (buf2
, val
& mask
);
581 as_warn (_("%s shortened to %s"), buf1
, buf2
);
586 /* Returns 0 if attempting to add a prefix where one from the same
587 class already exists, 1 if non rep/repne added, 2 if rep/repne
596 if (prefix
>= 0x40 && prefix
< 0x50 && flag_code
== CODE_64BIT
)
604 case CS_PREFIX_OPCODE
:
605 case DS_PREFIX_OPCODE
:
606 case ES_PREFIX_OPCODE
:
607 case FS_PREFIX_OPCODE
:
608 case GS_PREFIX_OPCODE
:
609 case SS_PREFIX_OPCODE
:
613 case REPNE_PREFIX_OPCODE
:
614 case REPE_PREFIX_OPCODE
:
617 case LOCK_PREFIX_OPCODE
:
625 case ADDR_PREFIX_OPCODE
:
629 case DATA_PREFIX_OPCODE
:
636 as_bad (_("same type of prefix used twice"));
641 i
.prefix
[q
] = prefix
;
646 set_code_flag (value
)
650 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
651 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
652 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
654 as_bad (_("64bit mode not supported on this CPU."));
656 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
658 as_bad (_("32bit mode not supported on this CPU."));
664 set_16bit_gcc_code_flag (new_code_flag
)
667 flag_code
= new_code_flag
;
668 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
669 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
674 set_intel_syntax (syntax_flag
)
677 /* Find out if register prefixing is specified. */
678 int ask_naked_reg
= 0;
681 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
683 char *string
= input_line_pointer
;
684 int e
= get_symbol_end ();
686 if (strcmp (string
, "prefix") == 0)
688 else if (strcmp (string
, "noprefix") == 0)
691 as_bad (_("bad argument to syntax directive."));
692 *input_line_pointer
= e
;
694 demand_empty_rest_of_line ();
696 intel_syntax
= syntax_flag
;
698 if (ask_naked_reg
== 0)
701 allow_naked_reg
= (intel_syntax
702 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
704 /* Conservative default. */
709 allow_naked_reg
= (ask_naked_reg
< 0);
714 int dummy ATTRIBUTE_UNUSED
;
718 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
720 char *string
= input_line_pointer
;
721 int e
= get_symbol_end ();
724 for (i
= 0; cpu_arch
[i
].name
; i
++)
726 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
728 cpu_arch_name
= cpu_arch
[i
].name
;
729 cpu_arch_flags
= cpu_arch
[i
].flags
| (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
733 if (!cpu_arch
[i
].name
)
734 as_bad (_("no such architecture: `%s'"), string
);
736 *input_line_pointer
= e
;
739 as_bad (_("missing cpu architecture"));
741 demand_empty_rest_of_line ();
744 const pseudo_typeS md_pseudo_table
[] =
746 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
747 {"align", s_align_bytes
, 0},
749 {"align", s_align_ptwo
, 0},
751 {"arch", set_cpu_arch
, 0},
755 {"ffloat", float_cons
, 'f'},
756 {"dfloat", float_cons
, 'd'},
757 {"tfloat", float_cons
, 'x'},
759 {"noopt", s_ignore
, 0},
760 {"optim", s_ignore
, 0},
761 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
762 {"code16", set_code_flag
, CODE_16BIT
},
763 {"code32", set_code_flag
, CODE_32BIT
},
764 {"code64", set_code_flag
, CODE_64BIT
},
765 {"intel_syntax", set_intel_syntax
, 1},
766 {"att_syntax", set_intel_syntax
, 0},
767 {"file", dwarf2_directive_file
, 0},
768 {"loc", dwarf2_directive_loc
, 0},
772 /* For interface with expression (). */
773 extern char *input_line_pointer
;
775 /* Hash table for instruction mnemonic lookup. */
776 static struct hash_control
*op_hash
;
778 /* Hash table for register lookup. */
779 static struct hash_control
*reg_hash
;
784 const char *hash_err
;
786 /* Initialize op_hash hash table. */
787 op_hash
= hash_new ();
790 register const template *optab
;
791 register templates
*core_optab
;
793 /* Setup for loop. */
795 core_optab
= (templates
*) xmalloc (sizeof (templates
));
796 core_optab
->start
= optab
;
801 if (optab
->name
== NULL
802 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
804 /* different name --> ship out current template list;
805 add to hash table; & begin anew. */
806 core_optab
->end
= optab
;
807 hash_err
= hash_insert (op_hash
,
812 as_fatal (_("Internal Error: Can't hash %s: %s"),
816 if (optab
->name
== NULL
)
818 core_optab
= (templates
*) xmalloc (sizeof (templates
));
819 core_optab
->start
= optab
;
824 /* Initialize reg_hash hash table. */
825 reg_hash
= hash_new ();
827 register const reg_entry
*regtab
;
829 for (regtab
= i386_regtab
;
830 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
833 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
835 as_fatal (_("Internal Error: Can't hash %s: %s"),
841 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
846 for (c
= 0; c
< 256; c
++)
851 mnemonic_chars
[c
] = c
;
852 register_chars
[c
] = c
;
853 operand_chars
[c
] = c
;
855 else if (islower (c
))
857 mnemonic_chars
[c
] = c
;
858 register_chars
[c
] = c
;
859 operand_chars
[c
] = c
;
861 else if (isupper (c
))
863 mnemonic_chars
[c
] = tolower (c
);
864 register_chars
[c
] = mnemonic_chars
[c
];
865 operand_chars
[c
] = c
;
868 if (isalpha (c
) || isdigit (c
))
869 identifier_chars
[c
] = c
;
872 identifier_chars
[c
] = c
;
873 operand_chars
[c
] = c
;
878 identifier_chars
['@'] = '@';
880 digit_chars
['-'] = '-';
881 identifier_chars
['_'] = '_';
882 identifier_chars
['.'] = '.';
884 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
885 operand_chars
[(unsigned char) *p
] = *p
;
888 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
889 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
891 record_alignment (text_section
, 2);
892 record_alignment (data_section
, 2);
893 record_alignment (bss_section
, 2);
899 i386_print_statistics (file
)
902 hash_print_statistics (file
, "i386 opcode", op_hash
);
903 hash_print_statistics (file
, "i386 register", reg_hash
);
908 /* Debugging routines for md_assemble. */
909 static void pi
PARAMS ((char *, i386_insn
*));
910 static void pte
PARAMS ((template *));
911 static void pt
PARAMS ((unsigned int));
912 static void pe
PARAMS ((expressionS
*));
913 static void ps
PARAMS ((symbolS
*));
922 fprintf (stdout
, "%s: template ", line
);
924 fprintf (stdout
, " address: base %s index %s scale %x\n",
925 x
->base_reg
? x
->base_reg
->reg_name
: "none",
926 x
->index_reg
? x
->index_reg
->reg_name
: "none",
927 x
->log2_scale_factor
);
928 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
929 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
930 fprintf (stdout
, " sib: base %x index %x scale %x\n",
931 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
932 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
933 x
->rex
.mode64
, x
->rex
.extX
, x
->rex
.extY
, x
->rex
.extZ
);
934 for (i
= 0; i
< x
->operands
; i
++)
936 fprintf (stdout
, " #%d: ", i
+ 1);
938 fprintf (stdout
, "\n");
940 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
941 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
942 if (x
->types
[i
] & Imm
)
944 if (x
->types
[i
] & Disp
)
954 fprintf (stdout
, " %d operands ", t
->operands
);
955 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
956 if (t
->extension_opcode
!= None
)
957 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
958 if (t
->opcode_modifier
& D
)
959 fprintf (stdout
, "D");
960 if (t
->opcode_modifier
& W
)
961 fprintf (stdout
, "W");
962 fprintf (stdout
, "\n");
963 for (i
= 0; i
< t
->operands
; i
++)
965 fprintf (stdout
, " #%d type ", i
+ 1);
966 pt (t
->operand_types
[i
]);
967 fprintf (stdout
, "\n");
975 fprintf (stdout
, " operation %d\n", e
->X_op
);
976 fprintf (stdout
, " add_number %ld (%lx)\n",
977 (long) e
->X_add_number
, (long) e
->X_add_number
);
980 fprintf (stdout
, " add_symbol ");
981 ps (e
->X_add_symbol
);
982 fprintf (stdout
, "\n");
986 fprintf (stdout
, " op_symbol ");
988 fprintf (stdout
, "\n");
996 fprintf (stdout
, "%s type %s%s",
998 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
999 segment_name (S_GET_SEGMENT (s
)));
1021 { BaseIndex
, "BaseIndex" },
1025 { Disp32S
, "d32s" },
1027 { InOutPortReg
, "InOutPortReg" },
1028 { ShiftCount
, "ShiftCount" },
1029 { Control
, "control reg" },
1030 { Test
, "test reg" },
1031 { Debug
, "debug reg" },
1032 { FloatReg
, "FReg" },
1033 { FloatAcc
, "FAcc" },
1037 { JumpAbsolute
, "Jump Absolute" },
1048 register struct type_name
*ty
;
1050 for (ty
= type_names
; ty
->mask
; ty
++)
1052 fprintf (stdout
, "%s, ", ty
->tname
);
1056 #endif /* DEBUG386 */
1059 tc_i386_force_relocation (fixp
)
1062 #ifdef BFD_ASSEMBLER
1063 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1064 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1069 return fixp
->fx_r_type
== 7;
1073 #ifdef BFD_ASSEMBLER
1075 static bfd_reloc_code_real_type
1076 reloc (size
, pcrel
, sign
, other
)
1080 bfd_reloc_code_real_type other
;
1082 if (other
!= NO_RELOC
)
1088 as_bad(_("There are no unsigned pc-relative relocations"));
1091 case 1: return BFD_RELOC_8_PCREL
;
1092 case 2: return BFD_RELOC_16_PCREL
;
1093 case 4: return BFD_RELOC_32_PCREL
;
1095 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1102 case 4: return BFD_RELOC_X86_64_32S
;
1107 case 1: return BFD_RELOC_8
;
1108 case 2: return BFD_RELOC_16
;
1109 case 4: return BFD_RELOC_32
;
1110 case 8: return BFD_RELOC_64
;
1112 as_bad (_("can not do %s %d byte relocation"),
1113 sign
? "signed" : "unsigned", size
);
1117 return BFD_RELOC_NONE
;
1120 /* Here we decide which fixups can be adjusted to make them relative to
1121 the beginning of the section instead of the symbol. Basically we need
1122 to make sure that the dynamic relocations are done correctly, so in
1123 some cases we force the original symbol to be used. */
1126 tc_i386_fix_adjustable (fixP
)
1129 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1130 /* Prevent all adjustments to global symbols, or else dynamic
1131 linking will not work correctly. */
1132 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1133 || S_IS_WEAK (fixP
->fx_addsy
))
1136 /* adjust_reloc_syms doesn't know about the GOT. */
1137 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1138 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1139 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1140 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1141 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1142 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1143 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1148 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1149 #define BFD_RELOC_16 0
1150 #define BFD_RELOC_32 0
1151 #define BFD_RELOC_16_PCREL 0
1152 #define BFD_RELOC_32_PCREL 0
1153 #define BFD_RELOC_386_PLT32 0
1154 #define BFD_RELOC_386_GOT32 0
1155 #define BFD_RELOC_386_GOTOFF 0
1156 #define BFD_RELOC_X86_64_PLT32 0
1157 #define BFD_RELOC_X86_64_GOT32 0
1158 #define BFD_RELOC_X86_64_GOTPCREL 0
1161 static int intel_float_operand
PARAMS ((char *mnemonic
));
1164 intel_float_operand (mnemonic
)
1167 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1170 if (mnemonic
[0] == 'f')
1176 /* This is the guts of the machine-dependent assembler. LINE points to a
1177 machine dependent instruction. This function is supposed to emit
1178 the frags/bytes it assembles to. */
1184 /* Points to template once we've found it. */
1187 /* Count the size of the instruction generated. */
1192 char mnemonic
[MAX_MNEM_SIZE
];
1194 /* Initialize globals. */
1195 memset (&i
, '\0', sizeof (i
));
1196 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1197 i
.disp_reloc
[j
] = NO_RELOC
;
1198 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1199 memset (im_expressions
, '\0', sizeof (im_expressions
));
1200 save_stack_p
= save_stack
;
1202 /* First parse an instruction mnemonic & call i386_operand for the operands.
1203 We assume that the scrubber has arranged it so that line[0] is the valid
1204 start of a (possibly prefixed) mnemonic. */
1207 char *token_start
= l
;
1210 /* Non-zero if we found a prefix only acceptable with string insns. */
1211 const char *expecting_string_instruction
= NULL
;
1216 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1219 if (mnem_p
>= mnemonic
+ sizeof (mnemonic
))
1221 as_bad (_("no such instruction: `%s'"), token_start
);
1226 if (!is_space_char (*l
)
1227 && *l
!= END_OF_INSN
1228 && *l
!= PREFIX_SEPARATOR
)
1230 as_bad (_("invalid character %s in mnemonic"),
1231 output_invalid (*l
));
1234 if (token_start
== l
)
1236 if (*l
== PREFIX_SEPARATOR
)
1237 as_bad (_("expecting prefix; got nothing"));
1239 as_bad (_("expecting mnemonic; got nothing"));
1243 /* Look up instruction (or prefix) via hash table. */
1244 current_templates
= hash_find (op_hash
, mnemonic
);
1246 if (*l
!= END_OF_INSN
1247 && (! is_space_char (*l
) || l
[1] != END_OF_INSN
)
1248 && current_templates
1249 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1251 /* If we are in 16-bit mode, do not allow addr16 or data16.
1252 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1253 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1254 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1255 ^ (flag_code
== CODE_16BIT
)))
1257 as_bad (_("redundant %s prefix"),
1258 current_templates
->start
->name
);
1261 /* Add prefix, checking for repeated prefixes. */
1262 switch (add_prefix (current_templates
->start
->base_opcode
))
1267 expecting_string_instruction
= current_templates
->start
->name
;
1270 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1277 if (!current_templates
)
1279 /* See if we can get a match by trimming off a suffix. */
1282 case WORD_MNEM_SUFFIX
:
1283 case BYTE_MNEM_SUFFIX
:
1284 case QWORD_MNEM_SUFFIX
:
1285 i
.suffix
= mnem_p
[-1];
1287 current_templates
= hash_find (op_hash
, mnemonic
);
1289 case SHORT_MNEM_SUFFIX
:
1290 case LONG_MNEM_SUFFIX
:
1293 i
.suffix
= mnem_p
[-1];
1295 current_templates
= hash_find (op_hash
, mnemonic
);
1303 if (intel_float_operand (mnemonic
))
1304 i
.suffix
= SHORT_MNEM_SUFFIX
;
1306 i
.suffix
= LONG_MNEM_SUFFIX
;
1308 current_templates
= hash_find (op_hash
, mnemonic
);
1312 if (!current_templates
)
1314 as_bad (_("no such instruction: `%s'"), token_start
);
1319 /* Check if instruction is supported on specified architecture. */
1320 if (cpu_arch_flags
!= 0)
1322 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1323 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1325 as_warn (_("`%s' is not supported on `%s'"),
1326 current_templates
->start
->name
, cpu_arch_name
);
1328 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1330 as_warn (_("use .code16 to ensure correct addressing mode"));
1334 /* Check for rep/repne without a string instruction. */
1335 if (expecting_string_instruction
1336 && !(current_templates
->start
->opcode_modifier
& IsString
))
1338 as_bad (_("expecting string instruction after `%s'"),
1339 expecting_string_instruction
);
1343 /* There may be operands to parse. */
1344 if (*l
!= END_OF_INSN
)
1346 /* 1 if operand is pending after ','. */
1347 unsigned int expecting_operand
= 0;
1349 /* Non-zero if operand parens not balanced. */
1350 unsigned int paren_not_balanced
;
1354 /* Skip optional white space before operand. */
1355 if (is_space_char (*l
))
1357 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1359 as_bad (_("invalid character %s before operand %d"),
1360 output_invalid (*l
),
1364 token_start
= l
; /* after white space */
1365 paren_not_balanced
= 0;
1366 while (paren_not_balanced
|| *l
!= ',')
1368 if (*l
== END_OF_INSN
)
1370 if (paren_not_balanced
)
1373 as_bad (_("unbalanced parenthesis in operand %d."),
1376 as_bad (_("unbalanced brackets in operand %d."),
1381 break; /* we are done */
1383 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1385 as_bad (_("invalid character %s in operand %d"),
1386 output_invalid (*l
),
1393 ++paren_not_balanced
;
1395 --paren_not_balanced
;
1400 ++paren_not_balanced
;
1402 --paren_not_balanced
;
1406 if (l
!= token_start
)
1407 { /* Yes, we've read in another operand. */
1408 unsigned int operand_ok
;
1409 this_operand
= i
.operands
++;
1410 if (i
.operands
> MAX_OPERANDS
)
1412 as_bad (_("spurious operands; (%d operands/instruction max)"),
1416 /* Now parse operand adding info to 'i' as we go along. */
1417 END_STRING_AND_SAVE (l
);
1421 i386_intel_operand (token_start
,
1422 intel_float_operand (mnemonic
));
1424 operand_ok
= i386_operand (token_start
);
1426 RESTORE_END_STRING (l
);
1432 if (expecting_operand
)
1434 expecting_operand_after_comma
:
1435 as_bad (_("expecting operand after ','; got nothing"));
1440 as_bad (_("expecting operand before ','; got nothing"));
1445 /* Now *l must be either ',' or END_OF_INSN. */
1448 if (*++l
== END_OF_INSN
)
1450 /* Just skip it, if it's \n complain. */
1451 goto expecting_operand_after_comma
;
1453 expecting_operand
= 1;
1456 while (*l
!= END_OF_INSN
);
1460 /* Now we've parsed the mnemonic into a set of templates, and have the
1463 Next, we find a template that matches the given insn,
1464 making sure the overlap of the given operands types is consistent
1465 with the template operand types. */
1467 #define MATCH(overlap, given, template) \
1468 ((overlap & ~JumpAbsolute) \
1469 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1471 /* If given types r0 and r1 are registers they must be of the same type
1472 unless the expected operand type register overlap is null.
1473 Note that Acc in a template matches every size of reg. */
1474 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1475 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1476 ((g0) & Reg) == ((g1) & Reg) || \
1477 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1480 register unsigned int overlap0
, overlap1
;
1481 unsigned int overlap2
;
1482 unsigned int found_reverse_match
;
1485 /* All intel opcodes have reversed operands except for "bound" and
1486 "enter". We also don't reverse intersegment "jmp" and "call"
1487 instructions with 2 immediate operands so that the immediate segment
1488 precedes the offset, as it does when in AT&T mode. "enter" and the
1489 intersegment "jmp" and "call" instructions are the only ones that
1490 have two immediate operands. */
1491 if (intel_syntax
&& i
.operands
> 1
1492 && (strcmp (mnemonic
, "bound") != 0)
1493 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1495 union i386_op temp_op
;
1496 unsigned int temp_type
;
1497 #ifdef BFD_ASSEMBLER
1498 enum bfd_reloc_code_real temp_reloc
;
1505 if (i
.operands
== 2)
1510 else if (i
.operands
== 3)
1515 temp_type
= i
.types
[xchg2
];
1516 i
.types
[xchg2
] = i
.types
[xchg1
];
1517 i
.types
[xchg1
] = temp_type
;
1518 temp_op
= i
.op
[xchg2
];
1519 i
.op
[xchg2
] = i
.op
[xchg1
];
1520 i
.op
[xchg1
] = temp_op
;
1521 temp_reloc
= i
.disp_reloc
[xchg2
];
1522 i
.disp_reloc
[xchg2
] = i
.disp_reloc
[xchg1
];
1523 i
.disp_reloc
[xchg1
] = temp_reloc
;
1525 if (i
.mem_operands
== 2)
1527 const seg_entry
*temp_seg
;
1528 temp_seg
= i
.seg
[0];
1529 i
.seg
[0] = i
.seg
[1];
1530 i
.seg
[1] = temp_seg
;
1536 /* Try to ensure constant immediates are represented in the smallest
1538 char guess_suffix
= 0;
1542 guess_suffix
= i
.suffix
;
1543 else if (i
.reg_operands
)
1545 /* Figure out a suffix from the last register operand specified.
1546 We can't do this properly yet, ie. excluding InOutPortReg,
1547 but the following works for instructions with immediates.
1548 In any case, we can't set i.suffix yet. */
1549 for (op
= i
.operands
; --op
>= 0;)
1550 if (i
.types
[op
] & Reg
)
1552 if (i
.types
[op
] & Reg8
)
1553 guess_suffix
= BYTE_MNEM_SUFFIX
;
1554 else if (i
.types
[op
] & Reg16
)
1555 guess_suffix
= WORD_MNEM_SUFFIX
;
1556 else if (i
.types
[op
] & Reg32
)
1557 guess_suffix
= LONG_MNEM_SUFFIX
;
1558 else if (i
.types
[op
] & Reg64
)
1559 guess_suffix
= QWORD_MNEM_SUFFIX
;
1563 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1564 guess_suffix
= WORD_MNEM_SUFFIX
;
1566 for (op
= i
.operands
; --op
>= 0;)
1567 if (i
.types
[op
] & Imm
)
1569 switch (i
.op
[op
].imms
->X_op
)
1572 /* If a suffix is given, this operand may be shortened. */
1573 switch (guess_suffix
)
1575 case LONG_MNEM_SUFFIX
:
1576 i
.types
[op
] |= Imm32
| Imm64
;
1578 case WORD_MNEM_SUFFIX
:
1579 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1581 case BYTE_MNEM_SUFFIX
:
1582 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1586 /* If this operand is at most 16 bits, convert it to a
1587 signed 16 bit number before trying to see whether it will
1588 fit in an even smaller size. This allows a 16-bit operand
1589 such as $0xffe0 to be recognised as within Imm8S range. */
1590 if ((i
.types
[op
] & Imm16
)
1591 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
)0xffff) == 0)
1593 i
.op
[op
].imms
->X_add_number
=
1594 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1596 if ((i
.types
[op
] & Imm32
)
1597 && (i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1)) == 0)
1599 i
.op
[op
].imms
->X_add_number
=
1600 (i
.op
[op
].imms
->X_add_number
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1602 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1603 /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */
1604 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1605 i
.types
[op
] &= ~Imm32
;
1610 /* Symbols and expressions. */
1612 /* Convert symbolic operand to proper sizes for matching. */
1613 switch (guess_suffix
)
1615 case QWORD_MNEM_SUFFIX
:
1616 i
.types
[op
] = Imm64
| Imm32S
;
1618 case LONG_MNEM_SUFFIX
:
1619 i
.types
[op
] = Imm32
| Imm64
;
1621 case WORD_MNEM_SUFFIX
:
1622 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1625 case BYTE_MNEM_SUFFIX
:
1626 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1635 if (i
.disp_operands
)
1637 /* Try to use the smallest displacement type too. */
1640 for (op
= i
.operands
; --op
>= 0;)
1641 if ((i
.types
[op
] & Disp
)
1642 && i
.op
[op
].imms
->X_op
== O_constant
)
1644 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1646 if (i
.types
[op
] & Disp16
)
1648 /* We know this operand is at most 16 bits, so
1649 convert to a signed 16 bit number before trying
1650 to see whether it will fit in an even smaller
1653 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1655 else if (i
.types
[op
] & Disp32
)
1657 /* We know this operand is at most 32 bits, so convert to a
1658 signed 32 bit number before trying to see whether it will
1659 fit in an even smaller size. */
1660 disp
&= (((offsetT
) 2 << 31) - 1);
1661 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1663 if (flag_code
== CODE_64BIT
)
1665 if (fits_in_signed_long (disp
))
1666 i
.types
[op
] |= Disp32S
;
1667 if (fits_in_unsigned_long (disp
))
1668 i
.types
[op
] |= Disp32
;
1670 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1671 && fits_in_signed_byte (disp
))
1672 i
.types
[op
] |= Disp8
;
1679 found_reverse_match
= 0;
1680 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1682 : (i
.suffix
== WORD_MNEM_SUFFIX
1684 : (i
.suffix
== SHORT_MNEM_SUFFIX
1686 : (i
.suffix
== LONG_MNEM_SUFFIX
1688 : (i
.suffix
== QWORD_MNEM_SUFFIX
1690 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
? No_xSuf
: 0))))));
1692 for (t
= current_templates
->start
;
1693 t
< current_templates
->end
;
1696 /* Must have right number of operands. */
1697 if (i
.operands
!= t
->operands
)
1700 /* Check the suffix, except for some instructions in intel mode. */
1701 if ((t
->opcode_modifier
& suffix_check
)
1703 && (t
->opcode_modifier
& IgnoreSize
))
1705 && t
->base_opcode
== 0xd9
1706 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1707 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1710 else if (!t
->operands
)
1711 /* 0 operands always matches. */
1714 overlap0
= i
.types
[0] & t
->operand_types
[0];
1715 switch (t
->operands
)
1718 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1723 overlap1
= i
.types
[1] & t
->operand_types
[1];
1724 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1725 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1726 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1727 t
->operand_types
[0],
1728 overlap1
, i
.types
[1],
1729 t
->operand_types
[1]))
1731 /* Check if other direction is valid ... */
1732 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1735 /* Try reversing direction of operands. */
1736 overlap0
= i
.types
[0] & t
->operand_types
[1];
1737 overlap1
= i
.types
[1] & t
->operand_types
[0];
1738 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1739 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1740 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1741 t
->operand_types
[1],
1742 overlap1
, i
.types
[1],
1743 t
->operand_types
[0]))
1745 /* Does not match either direction. */
1748 /* found_reverse_match holds which of D or FloatDR
1750 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1752 /* Found a forward 2 operand match here. */
1753 else if (t
->operands
== 3)
1755 /* Here we make use of the fact that there are no
1756 reverse match 3 operand instructions, and all 3
1757 operand instructions only need to be checked for
1758 register consistency between operands 2 and 3. */
1759 overlap2
= i
.types
[2] & t
->operand_types
[2];
1760 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1761 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1762 t
->operand_types
[1],
1763 overlap2
, i
.types
[2],
1764 t
->operand_types
[2]))
1768 /* Found either forward/reverse 2 or 3 operand match here:
1769 slip through to break. */
1771 if (t
->cpu_flags
& ~cpu_arch_flags
)
1773 found_reverse_match
= 0;
1776 /* We've found a match; break out of loop. */
1779 if (t
== current_templates
->end
)
1781 /* We found no match. */
1782 as_bad (_("suffix or operands invalid for `%s'"),
1783 current_templates
->start
->name
);
1787 if (!quiet_warnings
)
1790 && ((i
.types
[0] & JumpAbsolute
)
1791 != (t
->operand_types
[0] & JumpAbsolute
)))
1793 as_warn (_("indirect %s without `*'"), t
->name
);
1796 if ((t
->opcode_modifier
& (IsPrefix
|IgnoreSize
))
1797 == (IsPrefix
|IgnoreSize
))
1799 /* Warn them that a data or address size prefix doesn't
1800 affect assembly of the next line of code. */
1801 as_warn (_("stand-alone `%s' prefix"), t
->name
);
1805 /* Copy the template we found. */
1807 if (found_reverse_match
)
1809 /* If we found a reverse match we must alter the opcode
1810 direction bit. found_reverse_match holds bits to change
1811 (different for int & float insns). */
1813 i
.tm
.base_opcode
^= found_reverse_match
;
1815 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1816 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1819 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1822 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1823 i
.tm
.base_opcode
^= FloatR
;
1825 if (i
.tm
.opcode_modifier
& FWait
)
1826 if (! add_prefix (FWAIT_OPCODE
))
1829 /* Check string instruction segment overrides. */
1830 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1832 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1833 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1835 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1837 as_bad (_("`%s' operand %d must use `%%es' segment"),
1842 /* There's only ever one segment override allowed per instruction.
1843 This instruction possibly has a legal segment override on the
1844 second operand, so copy the segment to where non-string
1845 instructions store it, allowing common code. */
1846 i
.seg
[0] = i
.seg
[1];
1848 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1850 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1852 as_bad (_("`%s' operand %d must use `%%es' segment"),
1860 if (i
.reg_operands
&& flag_code
< CODE_64BIT
)
1863 for (op
= i
.operands
; --op
>= 0; )
1864 if ((i
.types
[op
] & Reg
)
1865 && (i
.op
[op
].regs
->reg_flags
& (RegRex64
|RegRex
)))
1866 as_bad (_("Extended register `%%%s' available only in 64bit mode."),
1867 i
.op
[op
].regs
->reg_name
);
1870 /* If matched instruction specifies an explicit instruction mnemonic
1872 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
1874 if (i
.tm
.opcode_modifier
& Size16
)
1875 i
.suffix
= WORD_MNEM_SUFFIX
;
1876 else if (i
.tm
.opcode_modifier
& Size64
)
1877 i
.suffix
= QWORD_MNEM_SUFFIX
;
1879 i
.suffix
= LONG_MNEM_SUFFIX
;
1881 else if (i
.reg_operands
)
1883 /* If there's no instruction mnemonic suffix we try to invent one
1884 based on register operands. */
1887 /* We take i.suffix from the last register operand specified,
1888 Destination register type is more significant than source
1891 for (op
= i
.operands
; --op
>= 0;)
1892 if ((i
.types
[op
] & Reg
)
1893 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
1895 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
1896 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
1897 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
1902 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
1905 for (op
= i
.operands
; --op
>= 0;)
1907 /* If this is an eight bit register, it's OK. If it's
1908 the 16 or 32 bit version of an eight bit register,
1909 we will just use the low portion, and that's OK too. */
1910 if (i
.types
[op
] & Reg8
)
1913 /* movzx and movsx should not generate this warning. */
1915 && (i
.tm
.base_opcode
== 0xfb7
1916 || i
.tm
.base_opcode
== 0xfb6
1917 || i
.tm
.base_opcode
== 0x63
1918 || i
.tm
.base_opcode
== 0xfbe
1919 || i
.tm
.base_opcode
== 0xfbf))
1922 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
1924 /* Check that the template allows eight bit regs
1925 This kills insns such as `orb $1,%edx', which
1926 maybe should be allowed. */
1927 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
1931 /* Prohibit these changes in the 64bit mode, since
1932 the lowering is more complicated. */
1933 if (flag_code
== CODE_64BIT
1934 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1935 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1936 i
.op
[op
].regs
->reg_name
,
1938 #if REGISTER_WARNINGS
1940 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1941 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1942 (i
.op
[op
].regs
- (i
.types
[op
] & Reg16
? 8 : 16))->reg_name
,
1943 i
.op
[op
].regs
->reg_name
,
1948 /* Any other register is bad. */
1949 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
1951 | Control
| Debug
| Test
1952 | FloatReg
| FloatAcc
))
1954 as_bad (_("`%%%s' not allowed with `%s%c'"),
1955 i
.op
[op
].regs
->reg_name
,
1962 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
1966 for (op
= i
.operands
; --op
>= 0;)
1967 /* Reject eight bit registers, except where the template
1968 requires them. (eg. movzb) */
1969 if ((i
.types
[op
] & Reg8
) != 0
1970 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
1972 as_bad (_("`%%%s' not allowed with `%s%c'"),
1973 i
.op
[op
].regs
->reg_name
,
1978 /* Warn if the e prefix on a general reg is missing. */
1979 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
1980 && (i
.types
[op
] & Reg16
) != 0
1981 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
1983 /* Prohibit these changes in the 64bit mode, since
1984 the lowering is more complicated. */
1985 if (flag_code
== CODE_64BIT
)
1986 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1987 i
.op
[op
].regs
->reg_name
,
1989 #if REGISTER_WARNINGS
1991 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1992 (i
.op
[op
].regs
+ 8)->reg_name
,
1993 i
.op
[op
].regs
->reg_name
,
1997 /* Warn if the r prefix on a general reg is missing. */
1998 else if ((i
.types
[op
] & Reg64
) != 0
1999 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2001 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2002 i
.op
[op
].regs
->reg_name
,
2006 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2009 if (flag_code
< CODE_64BIT
)
2010 as_bad (_("64bit operations available only in 64bit modes."));
2012 for (op
= i
.operands
; --op
>= 0; )
2013 /* Reject eight bit registers, except where the template
2014 requires them. (eg. movzb) */
2015 if ((i
.types
[op
] & Reg8
) != 0
2016 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2018 as_bad (_("`%%%s' not allowed with `%s%c'"),
2019 i
.op
[op
].regs
->reg_name
,
2024 /* Warn if the e prefix on a general reg is missing. */
2025 else if (((i
.types
[op
] & Reg16
) != 0
2026 || (i
.types
[op
] & Reg32
) != 0)
2027 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2029 /* Prohibit these changes in the 64bit mode, since
2030 the lowering is more complicated. */
2031 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2032 i
.op
[op
].regs
->reg_name
,
2036 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2039 for (op
= i
.operands
; --op
>= 0;)
2040 /* Reject eight bit registers, except where the template
2041 requires them. (eg. movzb) */
2042 if ((i
.types
[op
] & Reg8
) != 0
2043 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2045 as_bad (_("`%%%s' not allowed with `%s%c'"),
2046 i
.op
[op
].regs
->reg_name
,
2051 /* Warn if the e prefix on a general reg is present. */
2052 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2053 && (i
.types
[op
] & Reg32
) != 0
2054 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
2056 /* Prohibit these changes in the 64bit mode, since
2057 the lowering is more complicated. */
2058 if (flag_code
== CODE_64BIT
)
2059 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2060 i
.op
[op
].regs
->reg_name
,
2063 #if REGISTER_WARNINGS
2064 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2065 (i
.op
[op
].regs
- 8)->reg_name
,
2066 i
.op
[op
].regs
->reg_name
,
2071 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2072 /* Do nothing if the instruction is going to ignore the prefix. */
2077 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2079 i
.suffix
= stackop_size
;
2081 /* Make still unresolved immediate matches conform to size of immediate
2082 given in i.suffix. Note: overlap2 cannot be an immediate! */
2083 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2084 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2085 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2086 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2090 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2091 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2092 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2094 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2095 || overlap0
== (Imm16
| Imm32
)
2096 || overlap0
== (Imm16
| Imm32S
))
2099 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2101 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2102 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2103 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2105 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2109 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2110 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2111 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2112 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2116 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2117 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2118 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2120 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2121 || overlap1
== (Imm16
| Imm32
)
2122 || overlap1
== (Imm16
| Imm32S
))
2125 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2127 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2128 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2129 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2131 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2135 assert ((overlap2
& Imm
) == 0);
2137 i
.types
[0] = overlap0
;
2138 if (overlap0
& ImplicitRegister
)
2140 if (overlap0
& Imm1
)
2141 i
.imm_operands
= 0; /* kludge for shift insns. */
2143 i
.types
[1] = overlap1
;
2144 if (overlap1
& ImplicitRegister
)
2147 i
.types
[2] = overlap2
;
2148 if (overlap2
& ImplicitRegister
)
2151 /* Finalize opcode. First, we change the opcode based on the operand
2152 size given by i.suffix: We need not change things for byte insns. */
2154 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2156 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2160 /* For movzx and movsx, need to check the register type. */
2162 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
2163 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
2165 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2167 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
2168 if (!add_prefix (prefix
))
2172 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2174 /* It's not a byte, select word/dword operation. */
2175 if (i
.tm
.opcode_modifier
& W
)
2177 if (i
.tm
.opcode_modifier
& ShortForm
)
2178 i
.tm
.base_opcode
|= 8;
2180 i
.tm
.base_opcode
|= 1;
2182 /* Now select between word & dword operations via the operand
2183 size prefix, except for instructions that will ignore this
2185 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2186 && (i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2187 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
2189 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2190 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2191 prefix
= ADDR_PREFIX_OPCODE
;
2193 if (! add_prefix (prefix
))
2197 /* Set mode64 for an operand. */
2198 if (i
.suffix
== QWORD_MNEM_SUFFIX
2199 && !(i
.tm
.opcode_modifier
& NoRex64
))
2202 /* Size floating point instruction. */
2203 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2205 if (i
.tm
.opcode_modifier
& FloatMF
)
2206 i
.tm
.base_opcode
^= 4;
2210 if (i
.tm
.opcode_modifier
& ImmExt
)
2212 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2213 opcode suffix which is coded in the same place as an 8-bit
2214 immediate field would be. Here we fake an 8-bit immediate
2215 operand from the opcode suffix stored in tm.extension_opcode. */
2219 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
2221 exp
= &im_expressions
[i
.imm_operands
++];
2222 i
.op
[i
.operands
].imms
= exp
;
2223 i
.types
[i
.operands
++] = Imm8
;
2224 exp
->X_op
= O_constant
;
2225 exp
->X_add_number
= i
.tm
.extension_opcode
;
2226 i
.tm
.extension_opcode
= None
;
2229 /* For insns with operands there are more diddles to do to the opcode. */
2232 /* Default segment register this instruction will use
2233 for memory accesses. 0 means unknown.
2234 This is only for optimizing out unnecessary segment overrides. */
2235 const seg_entry
*default_seg
= 0;
2237 /* The imul $imm, %reg instruction is converted into
2238 imul $imm, %reg, %reg, and the clr %reg instruction
2239 is converted into xor %reg, %reg. */
2240 if (i
.tm
.opcode_modifier
& regKludge
)
2242 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2243 /* Pretend we saw the extra register operand. */
2244 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2245 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2246 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2250 if (i
.tm
.opcode_modifier
& ShortForm
)
2252 /* The register or float register operand is in operand 0 or 1. */
2253 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2254 /* Register goes in low 3 bits of opcode. */
2255 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2256 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2258 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2260 /* Warn about some common errors, but press on regardless.
2261 The first case can be generated by gcc (<= 2.8.1). */
2262 if (i
.operands
== 2)
2264 /* Reversed arguments on faddp, fsubp, etc. */
2265 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2266 i
.op
[1].regs
->reg_name
,
2267 i
.op
[0].regs
->reg_name
);
2271 /* Extraneous `l' suffix on fp insn. */
2272 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2273 i
.op
[0].regs
->reg_name
);
2277 else if (i
.tm
.opcode_modifier
& Modrm
)
2279 /* The opcode is completed (modulo i.tm.extension_opcode which
2280 must be put into the modrm byte).
2281 Now, we make the modrm & index base bytes based on all the
2282 info we've collected. */
2284 /* i.reg_operands MUST be the number of real register operands;
2285 implicit registers do not count. */
2286 if (i
.reg_operands
== 2)
2288 unsigned int source
, dest
;
2289 source
= ((i
.types
[0]
2290 & (Reg
| RegMMX
| RegXMM
2292 | Control
| Debug
| Test
))
2297 /* One of the register operands will be encoded in the
2298 i.tm.reg field, the other in the combined i.tm.mode
2299 and i.tm.regmem fields. If no form of this
2300 instruction supports a memory destination operand,
2301 then we assume the source operand may sometimes be
2302 a memory operand and so we need to store the
2303 destination in the i.rm.reg field. */
2304 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2306 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2307 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2308 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2310 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2315 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2316 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2317 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2319 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2324 { /* If it's not 2 reg operands... */
2327 unsigned int fake_zero_displacement
= 0;
2328 unsigned int op
= ((i
.types
[0] & AnyMem
)
2330 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2337 if (! i
.disp_operands
)
2338 fake_zero_displacement
= 1;
2341 /* Operand is just <disp> */
2342 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2344 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2345 i
.types
[op
] &= ~Disp
;
2346 i
.types
[op
] |= Disp16
;
2348 else if (flag_code
!= CODE_64BIT
)
2350 i
.rm
.regmem
= NO_BASE_REGISTER
;
2351 i
.types
[op
] &= ~Disp
;
2352 i
.types
[op
] |= Disp32
;
2356 /* 64bit mode overwrites the 32bit absolute addressing
2357 by RIP relative addressing and absolute addressing
2358 is encoded by one of the redundant SIB forms. */
2360 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2361 i
.sib
.base
= NO_BASE_REGISTER
;
2362 i
.sib
.index
= NO_INDEX_REGISTER
;
2363 i
.types
[op
] &= ~Disp
;
2364 i
.types
[op
] |= Disp32S
;
2367 else /* ! i.base_reg && i.index_reg */
2369 i
.sib
.index
= i
.index_reg
->reg_num
;
2370 i
.sib
.base
= NO_BASE_REGISTER
;
2371 i
.sib
.scale
= i
.log2_scale_factor
;
2372 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2373 i
.types
[op
] &= ~Disp
;
2374 if (flag_code
!= CODE_64BIT
)
2375 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2377 i
.types
[op
] |= Disp32S
;
2378 if (i
.index_reg
->reg_flags
& RegRex
)
2382 /* RIP addressing for 64bit mode. */
2383 else if (i
.base_reg
->reg_type
== BaseIndex
)
2385 i
.rm
.regmem
= NO_BASE_REGISTER
;
2386 i
.types
[op
] &= ~Disp
;
2387 i
.types
[op
] |= Disp32S
;
2388 i
.flags
[op
] = Operand_PCrel
;
2390 else if (i
.base_reg
->reg_type
& Reg16
)
2392 switch (i
.base_reg
->reg_num
)
2397 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2398 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2405 if ((i
.types
[op
] & Disp
) == 0)
2407 /* fake (%bp) into 0(%bp) */
2408 i
.types
[op
] |= Disp8
;
2409 fake_zero_displacement
= 1;
2412 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2413 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2415 default: /* (%si) -> 4 or (%di) -> 5 */
2416 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2418 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2420 else /* i.base_reg and 32/64 bit mode */
2422 if (flag_code
== CODE_64BIT
2423 && (i
.types
[op
] & Disp
))
2425 if (i
.types
[op
] & Disp8
)
2426 i
.types
[op
] = Disp8
| Disp32S
;
2428 i
.types
[op
] = Disp32S
;
2430 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2431 if (i
.base_reg
->reg_flags
& RegRex
)
2433 i
.sib
.base
= i
.base_reg
->reg_num
;
2434 /* x86-64 ignores REX prefix bit here to avoid
2435 decoder complications. */
2436 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2439 if (i
.disp_operands
== 0)
2441 fake_zero_displacement
= 1;
2442 i
.types
[op
] |= Disp8
;
2445 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2449 i
.sib
.scale
= i
.log2_scale_factor
;
2452 /* <disp>(%esp) becomes two byte modrm
2453 with no index register. We've already
2454 stored the code for esp in i.rm.regmem
2455 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2456 base register besides %esp will not use
2457 the extra modrm byte. */
2458 i
.sib
.index
= NO_INDEX_REGISTER
;
2459 #if ! SCALE1_WHEN_NO_INDEX
2460 /* Another case where we force the second
2462 if (i
.log2_scale_factor
)
2463 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2468 i
.sib
.index
= i
.index_reg
->reg_num
;
2469 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2470 if (i
.index_reg
->reg_flags
& RegRex
)
2473 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2476 if (fake_zero_displacement
)
2478 /* Fakes a zero displacement assuming that i.types[op]
2479 holds the correct displacement size. */
2482 assert (i
.op
[op
].disps
== 0);
2483 exp
= &disp_expressions
[i
.disp_operands
++];
2484 i
.op
[op
].disps
= exp
;
2485 exp
->X_op
= O_constant
;
2486 exp
->X_add_number
= 0;
2487 exp
->X_add_symbol
= (symbolS
*) 0;
2488 exp
->X_op_symbol
= (symbolS
*) 0;
2492 /* Fill in i.rm.reg or i.rm.regmem field with register
2493 operand (if any) based on i.tm.extension_opcode.
2494 Again, we must be careful to make sure that
2495 segment/control/debug/test/MMX registers are coded
2496 into the i.rm.reg field. */
2501 & (Reg
| RegMMX
| RegXMM
2503 | Control
| Debug
| Test
))
2506 & (Reg
| RegMMX
| RegXMM
2508 | Control
| Debug
| Test
))
2511 /* If there is an extension opcode to put here, the
2512 register number must be put into the regmem field. */
2513 if (i
.tm
.extension_opcode
!= None
)
2515 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2516 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2521 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2522 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2526 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2527 we must set it to 3 to indicate this is a register
2528 operand in the regmem field. */
2529 if (!i
.mem_operands
)
2533 /* Fill in i.rm.reg field with extension opcode (if any). */
2534 if (i
.tm
.extension_opcode
!= None
)
2535 i
.rm
.reg
= i
.tm
.extension_opcode
;
2538 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2540 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2541 && i
.op
[0].regs
->reg_num
== 1)
2543 as_bad (_("you can't `pop %%cs'"));
2546 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2547 if (i
.op
[0].regs
->reg_flags
& RegRex
)
2550 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
2554 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2556 /* For the string instructions that allow a segment override
2557 on one of their operands, the default segment is ds. */
2561 /* If a segment was explicitly specified,
2562 and the specified segment is not the default,
2563 use an opcode prefix to select it.
2564 If we never figured out what the default segment is,
2565 then default_seg will be zero at this point,
2566 and the specified segment prefix will always be used. */
2567 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2569 if (! add_prefix (i
.seg
[0]->seg_prefix
))
2573 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2575 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2576 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2580 /* Handle conversion of 'int $3' --> special int3 insn. */
2581 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2583 i
.tm
.base_opcode
= INT3_OPCODE
;
2587 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
2588 && i
.op
[0].disps
->X_op
== O_constant
)
2590 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2591 the absolute address given by the constant. Since ix86 jumps and
2592 calls are pc relative, we need to generate a reloc. */
2593 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2594 i
.op
[0].disps
->X_op
= O_symbol
;
2597 if (i
.tm
.opcode_modifier
& Rex64
)
2600 /* For 8bit registers we would need an empty rex prefix.
2601 Also in the case instruction is already having prefix,
2602 we need to convert old registers to new ones. */
2604 if (((i
.types
[0] & Reg8
) && (i
.op
[0].regs
->reg_flags
& RegRex64
))
2605 || ((i
.types
[1] & Reg8
) && (i
.op
[1].regs
->reg_flags
& RegRex64
))
2606 || ((i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2607 && ((i
.types
[0] & Reg8
) || (i
.types
[1] & Reg8
))))
2611 for (x
= 0; x
< 2; x
++)
2613 /* Look for 8bit operand that does use old registers. */
2614 if (i
.types
[x
] & Reg8
2615 && !(i
.op
[x
].regs
->reg_flags
& RegRex64
))
2617 /* In case it is "hi" register, give up. */
2618 if (i
.op
[x
].regs
->reg_num
> 3)
2619 as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"),
2620 i
.op
[x
].regs
->reg_name
);
2622 /* Otherwise it is equivalent to the extended register.
2623 Since the encoding don't change this is merely cosmetical
2624 cleanup for debug output. */
2626 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2631 if (i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2633 | (i
.rex
.mode64
? 8 : 0)
2634 | (i
.rex
.extX
? 4 : 0)
2635 | (i
.rex
.extY
? 2 : 0)
2636 | (i
.rex
.extZ
? 1 : 0));
2638 /* We are ready to output the insn. */
2643 if (i
.tm
.opcode_modifier
& Jump
)
2650 if (flag_code
== CODE_16BIT
)
2654 if (i
.prefix
[DATA_PREFIX
])
2660 if (i
.prefix
[REX_PREFIX
])
2670 if (i
.prefixes
!= 0 && !intel_syntax
)
2671 as_warn (_("skipping prefixes on this instruction"));
2673 /* It's always a symbol; End frag & setup for relax.
2674 Make sure there is enough room in this frag for the largest
2675 instruction we may generate in md_convert_frag. This is 2
2676 bytes for the opcode and room for the prefix and largest
2678 frag_grow (prefix
+ 2 + size
);
2679 insn_size
+= prefix
+ 1;
2680 /* Prefix and 1 opcode byte go in fr_fix. */
2681 p
= frag_more (prefix
+ 1);
2682 if (i
.prefix
[DATA_PREFIX
])
2683 *p
++ = DATA_PREFIX_OPCODE
;
2684 if (i
.prefix
[REX_PREFIX
])
2685 *p
++ = i
.prefix
[REX_PREFIX
];
2686 *p
= i
.tm
.base_opcode
;
2687 /* 1 possible extra opcode + displacement go in var part.
2688 Pass reloc in fr_var. */
2689 frag_var (rs_machine_dependent
,
2692 ((unsigned char) *p
== JUMP_PC_RELATIVE
2693 ? ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
) | code16
2694 : ENCODE_RELAX_STATE (COND_JUMP
, SMALL
) | code16
),
2695 i
.op
[0].disps
->X_add_symbol
,
2696 i
.op
[0].disps
->X_add_number
,
2699 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
2703 if (i
.tm
.opcode_modifier
& JumpByte
)
2705 /* This is a loop or jecxz type instruction. */
2707 if (i
.prefix
[ADDR_PREFIX
])
2710 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2719 if (flag_code
== CODE_16BIT
)
2722 if (i
.prefix
[DATA_PREFIX
])
2725 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
2735 if (i
.prefix
[REX_PREFIX
])
2737 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
2742 if (i
.prefixes
!= 0 && !intel_syntax
)
2743 as_warn (_("skipping prefixes on this instruction"));
2745 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2747 insn_size
+= 1 + size
;
2748 p
= frag_more (1 + size
);
2752 /* Opcode can be at most two bytes. */
2753 insn_size
+= 2 + size
;
2754 p
= frag_more (2 + size
);
2755 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2757 *p
++ = i
.tm
.base_opcode
& 0xff;
2759 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2760 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.disp_reloc
[0]));
2762 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
2769 if (flag_code
== CODE_16BIT
)
2773 if (i
.prefix
[DATA_PREFIX
])
2779 if (i
.prefix
[REX_PREFIX
])
2789 if (i
.prefixes
!= 0 && !intel_syntax
)
2790 as_warn (_("skipping prefixes on this instruction"));
2792 /* 1 opcode; 2 segment; offset */
2793 insn_size
+= prefix
+ 1 + 2 + size
;
2794 p
= frag_more (prefix
+ 1 + 2 + size
);
2796 if (i
.prefix
[DATA_PREFIX
])
2797 *p
++ = DATA_PREFIX_OPCODE
;
2799 if (i
.prefix
[REX_PREFIX
])
2800 *p
++ = i
.prefix
[REX_PREFIX
];
2802 *p
++ = i
.tm
.base_opcode
;
2803 if (i
.op
[1].imms
->X_op
== O_constant
)
2805 offsetT n
= i
.op
[1].imms
->X_add_number
;
2808 && !fits_in_unsigned_word (n
)
2809 && !fits_in_signed_word (n
))
2811 as_bad (_("16-bit jump out of range"));
2814 md_number_to_chars (p
, n
, size
);
2817 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2818 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.disp_reloc
[0]));
2819 if (i
.op
[0].imms
->X_op
!= O_constant
)
2820 as_bad (_("can't handle non absolute segment in `%s'"),
2822 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
2826 /* Output normal instructions here. */
2829 /* The prefix bytes. */
2831 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2838 md_number_to_chars (p
, (valueT
) *q
, 1);
2842 /* Now the opcode; be careful about word order here! */
2843 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2846 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2848 else if (fits_in_unsigned_word (i
.tm
.base_opcode
))
2852 /* Put out high byte first: can't use md_number_to_chars! */
2853 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2854 *p
= i
.tm
.base_opcode
& 0xff;
2857 { /* Opcode is either 3 or 4 bytes. */
2858 if (i
.tm
.base_opcode
& 0xff000000)
2862 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
2869 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
2870 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2871 *p
= (i
.tm
.base_opcode
) & 0xff;
2874 /* Now the modrm byte and sib byte (if present). */
2875 if (i
.tm
.opcode_modifier
& Modrm
)
2879 md_number_to_chars (p
,
2880 (valueT
) (i
.rm
.regmem
<< 0
2884 /* If i.rm.regmem == ESP (4)
2885 && i.rm.mode != (Register mode)
2887 ==> need second modrm byte. */
2888 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2890 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2894 md_number_to_chars (p
,
2895 (valueT
) (i
.sib
.base
<< 0
2897 | i
.sib
.scale
<< 6),
2902 if (i
.disp_operands
)
2904 register unsigned int n
;
2906 for (n
= 0; n
< i
.operands
; n
++)
2908 if (i
.types
[n
] & Disp
)
2910 if (i
.op
[n
].disps
->X_op
== O_constant
)
2916 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
2919 if (i
.types
[n
] & Disp8
)
2921 if (i
.types
[n
] & Disp64
)
2924 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
2927 p
= frag_more (size
);
2928 md_number_to_chars (p
, val
, size
);
2934 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
2936 /* The PC relative address is computed relative
2937 to the instruction boundary, so in case immediate
2938 fields follows, we need to adjust the value. */
2939 if (pcrel
&& i
.imm_operands
)
2942 register unsigned int n1
;
2944 for (n1
= 0; n1
< i
.operands
; n1
++)
2945 if (i
.types
[n1
] & Imm
)
2947 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
2950 if (i
.types
[n1
] & (Imm8
| Imm8S
))
2952 if (i
.types
[n1
] & Imm64
)
2957 /* We should find the immediate. */
2958 if (n1
== i
.operands
)
2960 i
.op
[n
].disps
->X_add_number
-= imm_size
;
2963 if (i
.types
[n
] & Disp32S
)
2966 if (i
.types
[n
] & (Disp16
| Disp64
))
2969 if (i
.types
[n
] & Disp64
)
2974 p
= frag_more (size
);
2975 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2976 i
.op
[n
].disps
, pcrel
,
2977 reloc (size
, pcrel
, sign
, i
.disp_reloc
[n
]));
2983 /* Output immediate. */
2986 register unsigned int n
;
2988 for (n
= 0; n
< i
.operands
; n
++)
2990 if (i
.types
[n
] & Imm
)
2992 if (i
.op
[n
].imms
->X_op
== O_constant
)
2998 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3001 if (i
.types
[n
] & (Imm8
| Imm8S
))
3003 else if (i
.types
[n
] & Imm64
)
3006 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3009 p
= frag_more (size
);
3010 md_number_to_chars (p
, val
, size
);
3014 /* Not absolute_section.
3015 Need a 32-bit fixup (don't support 8bit
3016 non-absolute imms). Try to support other
3018 #ifdef BFD_ASSEMBLER
3019 enum bfd_reloc_code_real reloc_type
;
3026 if ((i
.types
[n
] & (Imm32S
))
3027 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3029 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3032 if (i
.types
[n
] & (Imm8
| Imm8S
))
3034 if (i
.types
[n
] & Imm64
)
3039 p
= frag_more (size
);
3040 reloc_type
= reloc (size
, 0, sign
, i
.disp_reloc
[0]);
3041 #ifdef BFD_ASSEMBLER
3042 if (reloc_type
== BFD_RELOC_32
3044 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3045 && (i
.op
[n
].imms
->X_op
== O_symbol
3046 || (i
.op
[n
].imms
->X_op
== O_add
3047 && ((symbol_get_value_expression
3048 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3051 /* We don't support dynamic linking on x86-64 yet. */
3052 if (flag_code
== CODE_64BIT
)
3054 reloc_type
= BFD_RELOC_386_GOTPC
;
3055 i
.op
[n
].imms
->X_add_number
+= 3;
3058 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3059 i
.op
[n
].imms
, 0, reloc_type
);
3066 dwarf2_emit_insn (insn_size
);
3073 #endif /* DEBUG386 */
3077 static int i386_immediate
PARAMS ((char *));
3080 i386_immediate (imm_start
)
3083 char *save_input_line_pointer
;
3087 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3089 as_bad (_("only 1 or 2 immediate operands are allowed"));
3093 exp
= &im_expressions
[i
.imm_operands
++];
3094 i
.op
[this_operand
].imms
= exp
;
3096 if (is_space_char (*imm_start
))
3099 save_input_line_pointer
= input_line_pointer
;
3100 input_line_pointer
= imm_start
;
3104 /* We can have operands of the form
3105 <symbol>@GOTOFF+<nnn>
3106 Take the easy way out here and copy everything
3107 into a temporary buffer... */
3110 cp
= strchr (input_line_pointer
, '@');
3117 /* GOT relocations are not supported in 16 bit mode. */
3118 if (flag_code
== CODE_16BIT
)
3119 as_bad (_("GOT relocations not supported in 16 bit mode"));
3121 if (GOT_symbol
== NULL
)
3122 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3124 if (strncmp (cp
+ 1, "PLT", 3) == 0)
3126 if (flag_code
== CODE_64BIT
)
3127 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_PLT32
;
3129 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
3132 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
3134 if (flag_code
== CODE_64BIT
)
3135 as_bad ("GOTOFF relocations are unsupported in 64bit mode.");
3136 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
3139 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
3141 if (flag_code
== CODE_64BIT
)
3142 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOT32
;
3144 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
3147 else if (strncmp (cp
+ 1, "GOTPCREL", 3) == 0)
3149 if (flag_code
== CODE_64BIT
)
3150 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOTPCREL
;
3152 as_bad ("GOTPCREL relocations are supported only in 64bit mode.");
3156 as_bad (_("bad reloc specifier in expression"));
3158 /* Replace the relocation token with ' ', so that errors like
3159 foo@GOTOFF1 will be detected. */
3160 first
= cp
- input_line_pointer
;
3161 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
3162 memcpy (tmpbuf
, input_line_pointer
, first
);
3163 tmpbuf
[first
] = ' ';
3164 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
3165 input_line_pointer
= tmpbuf
;
3170 exp_seg
= expression (exp
);
3173 if (*input_line_pointer
)
3174 as_bad (_("ignoring junk `%s' after expression"), input_line_pointer
);
3176 input_line_pointer
= save_input_line_pointer
;
3178 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3180 /* Missing or bad expr becomes absolute 0. */
3181 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3183 exp
->X_op
= O_constant
;
3184 exp
->X_add_number
= 0;
3185 exp
->X_add_symbol
= (symbolS
*) 0;
3186 exp
->X_op_symbol
= (symbolS
*) 0;
3188 else if (exp
->X_op
== O_constant
)
3190 /* Size it properly later. */
3191 i
.types
[this_operand
] |= Imm64
;
3192 /* If BFD64, sign extend val. */
3193 if (!use_rela_relocations
)
3194 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3195 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3197 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3199 #ifdef BFD_ASSEMBLER
3200 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3202 && exp_seg
!= text_section
3203 && exp_seg
!= data_section
3204 && exp_seg
!= bss_section
3205 && exp_seg
!= undefined_section
3206 #ifdef BFD_ASSEMBLER
3207 && !bfd_is_com_section (exp_seg
)
3211 #ifdef BFD_ASSEMBLER
3212 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3214 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3221 /* This is an address. The size of the address will be
3222 determined later, depending on destination register,
3223 suffix, or the default for the section. */
3224 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3230 static int i386_scale
PARAMS ((char *));
3236 if (!isdigit (*scale
))
3243 i
.log2_scale_factor
= 0;
3246 i
.log2_scale_factor
= 1;
3249 i
.log2_scale_factor
= 2;
3252 i
.log2_scale_factor
= 3;
3256 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3260 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
3262 as_warn (_("scale factor of %d without an index register"),
3263 1 << i
.log2_scale_factor
);
3264 #if SCALE1_WHEN_NO_INDEX
3265 i
.log2_scale_factor
= 0;
3271 static int i386_displacement
PARAMS ((char *, char *));
3274 i386_displacement (disp_start
, disp_end
)
3278 register expressionS
*exp
;
3280 char *save_input_line_pointer
;
3281 int bigdisp
= Disp32
;
3283 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3285 if (flag_code
== CODE_64BIT
)
3287 i
.types
[this_operand
] |= bigdisp
;
3289 exp
= &disp_expressions
[i
.disp_operands
];
3290 i
.op
[this_operand
].disps
= exp
;
3292 save_input_line_pointer
= input_line_pointer
;
3293 input_line_pointer
= disp_start
;
3294 END_STRING_AND_SAVE (disp_end
);
3296 #ifndef GCC_ASM_O_HACK
3297 #define GCC_ASM_O_HACK 0
3300 END_STRING_AND_SAVE (disp_end
+ 1);
3301 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3302 && displacement_string_end
[-1] == '+')
3304 /* This hack is to avoid a warning when using the "o"
3305 constraint within gcc asm statements.
3308 #define _set_tssldt_desc(n,addr,limit,type) \
3309 __asm__ __volatile__ ( \
3311 "movw %w1,2+%0\n\t" \
3313 "movb %b1,4+%0\n\t" \
3314 "movb %4,5+%0\n\t" \
3315 "movb $0,6+%0\n\t" \
3316 "movb %h1,7+%0\n\t" \
3318 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3320 This works great except that the output assembler ends
3321 up looking a bit weird if it turns out that there is
3322 no offset. You end up producing code that looks like:
3335 So here we provide the missing zero. */
3337 *displacement_string_end
= '0';
3342 /* We can have operands of the form
3343 <symbol>@GOTOFF+<nnn>
3344 Take the easy way out here and copy everything
3345 into a temporary buffer... */
3348 cp
= strchr (input_line_pointer
, '@');
3355 /* GOT relocations are not supported in 16 bit mode. */
3356 if (flag_code
== CODE_16BIT
)
3357 as_bad (_("GOT relocations not supported in 16 bit mode"));
3359 if (GOT_symbol
== NULL
)
3360 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3362 if (strncmp (cp
+ 1, "PLT", 3) == 0)
3364 if (flag_code
== CODE_64BIT
)
3365 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_PLT32
;
3367 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
3370 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
3372 if (flag_code
== CODE_64BIT
)
3373 as_bad ("GOTOFF relocation is not supported in 64bit mode.");
3374 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
3377 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
3379 if (flag_code
== CODE_64BIT
)
3380 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOT32
;
3382 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
3385 else if (strncmp (cp
+ 1, "GOTPCREL", 3) == 0)
3387 if (flag_code
!= CODE_64BIT
)
3388 as_bad ("GOTPCREL relocation is supported only in 64bit mode.");
3389 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOTPCREL
;
3393 as_bad (_("bad reloc specifier in expression"));
3395 /* Replace the relocation token with ' ', so that errors like
3396 foo@GOTOFF1 will be detected. */
3397 first
= cp
- input_line_pointer
;
3398 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
3399 memcpy (tmpbuf
, input_line_pointer
, first
);
3400 tmpbuf
[first
] = ' ';
3401 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
3402 input_line_pointer
= tmpbuf
;
3407 exp_seg
= expression (exp
);
3409 #ifdef BFD_ASSEMBLER
3410 /* We do this to make sure that the section symbol is in
3411 the symbol table. We will ultimately change the relocation
3412 to be relative to the beginning of the section. */
3413 if (i
.disp_reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3414 || i
.disp_reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3416 if (S_IS_LOCAL(exp
->X_add_symbol
)
3417 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3418 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3419 assert (exp
->X_op
== O_symbol
);
3420 exp
->X_op
= O_subtract
;
3421 exp
->X_op_symbol
= GOT_symbol
;
3422 i
.disp_reloc
[this_operand
] = BFD_RELOC_32
;
3427 if (*input_line_pointer
)
3428 as_bad (_("ignoring junk `%s' after expression"),
3429 input_line_pointer
);
3431 RESTORE_END_STRING (disp_end
+ 1);
3433 RESTORE_END_STRING (disp_end
);
3434 input_line_pointer
= save_input_line_pointer
;
3436 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3438 /* Missing or bad expr becomes absolute 0. */
3439 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3441 exp
->X_op
= O_constant
;
3442 exp
->X_add_number
= 0;
3443 exp
->X_add_symbol
= (symbolS
*) 0;
3444 exp
->X_op_symbol
= (symbolS
*) 0;
3447 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3448 if (exp
->X_op
!= O_constant
3449 #ifdef BFD_ASSEMBLER
3450 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3452 && exp_seg
!= text_section
3453 && exp_seg
!= data_section
3454 && exp_seg
!= bss_section
3455 && exp_seg
!= undefined_section
)
3457 #ifdef BFD_ASSEMBLER
3458 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3460 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3465 else if (flag_code
== CODE_64BIT
)
3466 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3470 static int i386_index_check
PARAMS((const char *));
3472 /* Make sure the memory operand we've been dealt is valid.
3473 Return 1 on success, 0 on a failure. */
3476 i386_index_check (operand_string
)
3477 const char *operand_string
;
3480 #if INFER_ADDR_PREFIX
3486 if (flag_code
== CODE_64BIT
)
3490 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3491 && (i
.base_reg
->reg_type
!= BaseIndex
3494 && ((i
.index_reg
->reg_type
& (Reg64
|BaseIndex
))
3495 != (Reg64
|BaseIndex
))))
3500 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3504 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
|RegRex
))
3505 != (Reg16
|BaseIndex
)))
3507 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
3508 != (Reg16
|BaseIndex
))
3510 && i
.base_reg
->reg_num
< 6
3511 && i
.index_reg
->reg_num
>= 6
3512 && i
.log2_scale_factor
== 0))))
3519 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3521 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
|RegRex
))
3522 != (Reg32
|BaseIndex
))))
3528 #if INFER_ADDR_PREFIX
3529 if (flag_code
!= CODE_64BIT
3530 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3532 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3534 /* Change the size of any displacement too. At most one of
3535 Disp16 or Disp32 is set.
3536 FIXME. There doesn't seem to be any real need for separate
3537 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3538 Removing them would probably clean up the code quite a lot. */
3539 if (i
.types
[this_operand
] & (Disp16
|Disp32
))
3540 i
.types
[this_operand
] ^= (Disp16
|Disp32
);
3545 as_bad (_("`%s' is not a valid base/index expression"),
3549 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3551 flag_code_names
[flag_code
]);
3557 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3561 i386_operand (operand_string
)
3562 char *operand_string
;
3566 char *op_string
= operand_string
;
3568 if (is_space_char (*op_string
))
3571 /* We check for an absolute prefix (differentiating,
3572 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3573 if (*op_string
== ABSOLUTE_PREFIX
)
3576 if (is_space_char (*op_string
))
3578 i
.types
[this_operand
] |= JumpAbsolute
;
3581 /* Check if operand is a register. */
3582 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3583 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3585 /* Check for a segment override by searching for ':' after a
3586 segment register. */
3588 if (is_space_char (*op_string
))
3590 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3595 i
.seg
[i
.mem_operands
] = &es
;
3598 i
.seg
[i
.mem_operands
] = &cs
;
3601 i
.seg
[i
.mem_operands
] = &ss
;
3604 i
.seg
[i
.mem_operands
] = &ds
;
3607 i
.seg
[i
.mem_operands
] = &fs
;
3610 i
.seg
[i
.mem_operands
] = &gs
;
3614 /* Skip the ':' and whitespace. */
3616 if (is_space_char (*op_string
))
3619 if (!is_digit_char (*op_string
)
3620 && !is_identifier_char (*op_string
)
3621 && *op_string
!= '('
3622 && *op_string
!= ABSOLUTE_PREFIX
)
3624 as_bad (_("bad memory operand `%s'"), op_string
);
3627 /* Handle case of %es:*foo. */
3628 if (*op_string
== ABSOLUTE_PREFIX
)
3631 if (is_space_char (*op_string
))
3633 i
.types
[this_operand
] |= JumpAbsolute
;
3635 goto do_memory_reference
;
3639 as_bad (_("junk `%s' after register"), op_string
);
3642 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3643 i
.op
[this_operand
].regs
= r
;
3646 else if (*op_string
== REGISTER_PREFIX
)
3648 as_bad (_("bad register name `%s'"), op_string
);
3651 else if (*op_string
== IMMEDIATE_PREFIX
)
3654 if (i
.types
[this_operand
] & JumpAbsolute
)
3656 as_bad (_("immediate operand illegal with absolute jump"));
3659 if (!i386_immediate (op_string
))
3662 else if (is_digit_char (*op_string
)
3663 || is_identifier_char (*op_string
)
3664 || *op_string
== '(' )
3666 /* This is a memory reference of some sort. */
3669 /* Start and end of displacement string expression (if found). */
3670 char *displacement_string_start
;
3671 char *displacement_string_end
;
3673 do_memory_reference
:
3674 if ((i
.mem_operands
== 1
3675 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3676 || i
.mem_operands
== 2)
3678 as_bad (_("too many memory references for `%s'"),
3679 current_templates
->start
->name
);
3683 /* Check for base index form. We detect the base index form by
3684 looking for an ')' at the end of the operand, searching
3685 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3687 base_string
= op_string
+ strlen (op_string
);
3690 if (is_space_char (*base_string
))
3693 /* If we only have a displacement, set-up for it to be parsed later. */
3694 displacement_string_start
= op_string
;
3695 displacement_string_end
= base_string
+ 1;
3697 if (*base_string
== ')')
3700 unsigned int parens_balanced
= 1;
3701 /* We've already checked that the number of left & right ()'s are
3702 equal, so this loop will not be infinite. */
3706 if (*base_string
== ')')
3708 if (*base_string
== '(')
3711 while (parens_balanced
);
3713 temp_string
= base_string
;
3715 /* Skip past '(' and whitespace. */
3717 if (is_space_char (*base_string
))
3720 if (*base_string
== ','
3721 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3722 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
3724 displacement_string_end
= temp_string
;
3726 i
.types
[this_operand
] |= BaseIndex
;
3730 base_string
= end_op
;
3731 if (is_space_char (*base_string
))
3735 /* There may be an index reg or scale factor here. */
3736 if (*base_string
== ',')
3739 if (is_space_char (*base_string
))
3742 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3743 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
3745 base_string
= end_op
;
3746 if (is_space_char (*base_string
))
3748 if (*base_string
== ',')
3751 if (is_space_char (*base_string
))
3754 else if (*base_string
!= ')' )
3756 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3761 else if (*base_string
== REGISTER_PREFIX
)
3763 as_bad (_("bad register name `%s'"), base_string
);
3767 /* Check for scale factor. */
3768 if (isdigit ((unsigned char) *base_string
))
3770 if (!i386_scale (base_string
))
3774 if (is_space_char (*base_string
))
3776 if (*base_string
!= ')')
3778 as_bad (_("expecting `)' after scale factor in `%s'"),
3783 else if (!i
.index_reg
)
3785 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3790 else if (*base_string
!= ')')
3792 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3797 else if (*base_string
== REGISTER_PREFIX
)
3799 as_bad (_("bad register name `%s'"), base_string
);
3804 /* If there's an expression beginning the operand, parse it,
3805 assuming displacement_string_start and
3806 displacement_string_end are meaningful. */
3807 if (displacement_string_start
!= displacement_string_end
)
3809 if (!i386_displacement (displacement_string_start
,
3810 displacement_string_end
))
3814 /* Special case for (%dx) while doing input/output op. */
3816 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
3818 && i
.log2_scale_factor
== 0
3819 && i
.seg
[i
.mem_operands
] == 0
3820 && (i
.types
[this_operand
] & Disp
) == 0)
3822 i
.types
[this_operand
] = InOutPortReg
;
3826 if (i386_index_check (operand_string
) == 0)
3832 /* It's not a memory operand; argh! */
3833 as_bad (_("invalid char %s beginning operand %d `%s'"),
3834 output_invalid (*op_string
),
3839 return 1; /* Normal return. */
3842 /* md_estimate_size_before_relax()
3844 Called just before relax() for rs_machine_dependent frags. The x86
3845 assembler uses these frags to handle variable size jump
3848 Any symbol that is now undefined will not become defined.
3849 Return the correct fr_subtype in the frag.
3850 Return the initial "guess for variable size of frag" to caller.
3851 The guess is actually the growth beyond the fixed part. Whatever
3852 we do to grow the fixed or variable part contributes to our
3856 md_estimate_size_before_relax (fragP
, segment
)
3857 register fragS
*fragP
;
3858 register segT segment
;
3860 /* We've already got fragP->fr_subtype right; all we have to do is
3861 check for un-relaxable symbols. On an ELF system, we can't relax
3862 an externally visible symbol, because it may be overridden by a
3864 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3865 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3866 || S_IS_EXTERNAL (fragP
->fr_symbol
)
3867 || S_IS_WEAK (fragP
->fr_symbol
)
3871 /* Symbol is undefined in this segment, or we need to keep a
3872 reloc so that weak symbols can be overridden. */
3873 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
3874 #ifdef BFD_ASSEMBLER
3875 enum bfd_reloc_code_real reloc_type
;
3879 unsigned char *opcode
;
3882 if (fragP
->fr_var
!= NO_RELOC
)
3883 reloc_type
= fragP
->fr_var
;
3885 reloc_type
= BFD_RELOC_16_PCREL
;
3887 reloc_type
= BFD_RELOC_32_PCREL
;
3889 old_fr_fix
= fragP
->fr_fix
;
3890 opcode
= (unsigned char *) fragP
->fr_opcode
;
3894 case JUMP_PC_RELATIVE
:
3895 /* Make jmp (0xeb) a dword displacement jump. */
3897 fragP
->fr_fix
+= size
;
3898 fix_new (fragP
, old_fr_fix
, size
,
3900 fragP
->fr_offset
, 1,
3905 /* This changes the byte-displacement jump 0x7N
3906 to the dword-displacement jump 0x0f,0x8N. */
3907 opcode
[1] = opcode
[0] + 0x10;
3908 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3909 /* We've added an opcode byte. */
3910 fragP
->fr_fix
+= 1 + size
;
3911 fix_new (fragP
, old_fr_fix
+ 1, size
,
3913 fragP
->fr_offset
, 1,
3918 return fragP
->fr_fix
- old_fr_fix
;
3920 /* Guess a short jump. */
3924 /* Called after relax() is finished.
3926 In: Address of frag.
3927 fr_type == rs_machine_dependent.
3928 fr_subtype is what the address relaxed to.
3930 Out: Any fixSs and constants are set up.
3931 Caller will turn frag into a ".space 0". */
3933 #ifndef BFD_ASSEMBLER
3935 md_convert_frag (headers
, sec
, fragP
)
3936 object_headers
*headers ATTRIBUTE_UNUSED
;
3937 segT sec ATTRIBUTE_UNUSED
;
3938 register fragS
*fragP
;
3941 md_convert_frag (abfd
, sec
, fragP
)
3942 bfd
*abfd ATTRIBUTE_UNUSED
;
3943 segT sec ATTRIBUTE_UNUSED
;
3944 register fragS
*fragP
;
3947 register unsigned char *opcode
;
3948 unsigned char *where_to_put_displacement
= NULL
;
3949 offsetT target_address
;
3950 offsetT opcode_address
;
3951 unsigned int extension
= 0;
3952 offsetT displacement_from_opcode_start
;
3954 opcode
= (unsigned char *) fragP
->fr_opcode
;
3956 /* Address we want to reach in file space. */
3957 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
3958 #ifdef BFD_ASSEMBLER
3959 /* Not needed otherwise? */
3960 target_address
+= symbol_get_frag (fragP
->fr_symbol
)->fr_address
;
3963 /* Address opcode resides at in file space. */
3964 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
3966 /* Displacement from opcode start to fill into instruction. */
3967 displacement_from_opcode_start
= target_address
- opcode_address
;
3969 switch (fragP
->fr_subtype
)
3971 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL
):
3972 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL16
):
3973 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
):
3974 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL16
):
3975 /* Don't have to change opcode. */
3976 extension
= 1; /* 1 opcode + 1 displacement */
3977 where_to_put_displacement
= &opcode
[1];
3980 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
3981 extension
= 5; /* 2 opcode + 4 displacement */
3982 opcode
[1] = opcode
[0] + 0x10;
3983 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3984 where_to_put_displacement
= &opcode
[2];
3987 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
3988 extension
= 4; /* 1 opcode + 4 displacement */
3990 where_to_put_displacement
= &opcode
[1];
3993 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
3994 extension
= 3; /* 2 opcode + 2 displacement */
3995 opcode
[1] = opcode
[0] + 0x10;
3996 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3997 where_to_put_displacement
= &opcode
[2];
4000 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4001 extension
= 2; /* 1 opcode + 2 displacement */
4003 where_to_put_displacement
= &opcode
[1];
4007 BAD_CASE (fragP
->fr_subtype
);
4010 /* Now put displacement after opcode. */
4011 md_number_to_chars ((char *) where_to_put_displacement
,
4012 (valueT
) (displacement_from_opcode_start
- extension
),
4013 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4014 fragP
->fr_fix
+= extension
;
4017 /* Size of byte displacement jmp. */
4018 int md_short_jump_size
= 2;
4020 /* Size of dword displacement jmp. */
4021 int md_long_jump_size
= 5;
4023 /* Size of relocation record. */
4024 const int md_reloc_size
= 8;
4027 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4029 addressT from_addr
, to_addr
;
4030 fragS
*frag ATTRIBUTE_UNUSED
;
4031 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4035 offset
= to_addr
- (from_addr
+ 2);
4036 /* Opcode for byte-disp jump. */
4037 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4038 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4042 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4044 addressT from_addr
, to_addr
;
4045 fragS
*frag ATTRIBUTE_UNUSED
;
4046 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4050 offset
= to_addr
- (from_addr
+ 5);
4051 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4052 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4055 /* Apply a fixup (fixS) to segment data, once it has been determined
4056 by our caller that we have all the info we need to fix it up.
4058 On the 386, immediates, displacements, and data pointers are all in
4059 the same (little-endian) format, so we don't need to care about which
4063 md_apply_fix3 (fixP
, valp
, seg
)
4064 /* The fix we're to put in. */
4067 /* Pointer to the value of the bits. */
4070 /* Segment fix is from. */
4071 segT seg ATTRIBUTE_UNUSED
;
4073 register char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4074 valueT value
= *valp
;
4076 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4079 switch (fixP
->fx_r_type
)
4085 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4088 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4091 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4096 /* This is a hack. There should be a better way to handle this.
4097 This covers for the fact that bfd_install_relocation will
4098 subtract the current location (for partial_inplace, PC relative
4099 relocations); see more below. */
4100 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4101 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4102 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4106 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4108 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4111 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4113 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4114 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4116 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4119 || (symbol_section_p (fixP
->fx_addsy
)
4120 && fseg
!= absolute_section
))
4121 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
4122 && ! S_IS_WEAK (fixP
->fx_addsy
)
4123 && S_IS_DEFINED (fixP
->fx_addsy
)
4124 && ! S_IS_COMMON (fixP
->fx_addsy
))
4126 /* Yes, we add the values in twice. This is because
4127 bfd_perform_relocation subtracts them out again. I think
4128 bfd_perform_relocation is broken, but I don't dare change
4130 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4134 #if defined (OBJ_COFF) && defined (TE_PE)
4135 /* For some reason, the PE format does not store a section
4136 address offset for a PC relative symbol. */
4137 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4138 value
+= md_pcrel_from (fixP
);
4142 /* Fix a few things - the dynamic linker expects certain values here,
4143 and we must not dissappoint it. */
4144 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4145 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4147 switch (fixP
->fx_r_type
)
4149 case BFD_RELOC_386_PLT32
:
4150 case BFD_RELOC_X86_64_PLT32
:
4151 /* Make the jump instruction point to the address of the operand. At
4152 runtime we merely add the offset to the actual PLT entry. */
4155 case BFD_RELOC_386_GOTPC
:
4157 /* This is tough to explain. We end up with this one if we have
4158 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4159 * here is to obtain the absolute address of the GOT, and it is strongly
4160 * preferable from a performance point of view to avoid using a runtime
4161 * relocation for this. The actual sequence of instructions often look
4167 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4169 * The call and pop essentially return the absolute address of
4170 * the label .L66 and store it in %ebx. The linker itself will
4171 * ultimately change the first operand of the addl so that %ebx points to
4172 * the GOT, but to keep things simple, the .o file must have this operand
4173 * set so that it generates not the absolute address of .L66, but the
4174 * absolute address of itself. This allows the linker itself simply
4175 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4176 * added in, and the addend of the relocation is stored in the operand
4177 * field for the instruction itself.
4179 * Our job here is to fix the operand so that it would add the correct
4180 * offset so that %ebx would point to itself. The thing that is tricky is
4181 * that .-.L66 will point to the beginning of the instruction, so we need
4182 * to further modify the operand so that it will point to itself.
4183 * There are other cases where you have something like:
4185 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4187 * and here no correction would be required. Internally in the assembler
4188 * we treat operands of this form as not being pcrel since the '.' is
4189 * explicitly mentioned, and I wonder whether it would simplify matters
4190 * to do it this way. Who knows. In earlier versions of the PIC patches,
4191 * the pcrel_adjust field was used to store the correction, but since the
4192 * expression is not pcrel, I felt it would be confusing to do it this
4197 case BFD_RELOC_386_GOT32
:
4198 case BFD_RELOC_X86_64_GOT32
:
4199 value
= 0; /* Fully resolved at runtime. No addend. */
4201 case BFD_RELOC_386_GOTOFF
:
4202 case BFD_RELOC_X86_64_GOTPCREL
:
4205 case BFD_RELOC_VTABLE_INHERIT
:
4206 case BFD_RELOC_VTABLE_ENTRY
:
4213 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4215 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4217 #ifndef BFD_ASSEMBLER
4218 md_number_to_chars (p
, value
, fixP
->fx_size
);
4220 /* Are we finished with this relocation now? */
4221 if (fixP
->fx_addsy
== 0 && fixP
->fx_pcrel
== 0)
4223 else if (use_rela_relocations
)
4225 fixP
->fx_no_overflow
= 1;
4228 md_number_to_chars (p
, value
, fixP
->fx_size
);
4234 #define MAX_LITTLENUMS 6
4236 /* Turn the string pointed to by litP into a floating point constant
4237 of type TYPE, and emit the appropriate bytes. The number of
4238 LITTLENUMS emitted is stored in *SIZEP. An error message is
4239 returned, or NULL on OK. */
4242 md_atof (type
, litP
, sizeP
)
4248 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4249 LITTLENUM_TYPE
*wordP
;
4271 return _("Bad call to md_atof ()");
4273 t
= atof_ieee (input_line_pointer
, type
, words
);
4275 input_line_pointer
= t
;
4277 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4278 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4279 the bigendian 386. */
4280 for (wordP
= words
+ prec
- 1; prec
--;)
4282 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4283 litP
+= sizeof (LITTLENUM_TYPE
);
4288 char output_invalid_buf
[8];
4295 sprintf (output_invalid_buf
, "'%c'", c
);
4297 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4298 return output_invalid_buf
;
4301 /* REG_STRING starts *before* REGISTER_PREFIX. */
4303 static const reg_entry
*
4304 parse_register (reg_string
, end_op
)
4308 char *s
= reg_string
;
4310 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4313 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4314 if (*s
== REGISTER_PREFIX
)
4317 if (is_space_char (*s
))
4321 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4323 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4324 return (const reg_entry
*) NULL
;
4328 /* For naked regs, make sure that we are not dealing with an identifier.
4329 This prevents confusing an identifier like `eax_var' with register
4331 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4332 return (const reg_entry
*) NULL
;
4336 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4338 /* Handle floating point regs, allowing spaces in the (i) part. */
4339 if (r
== i386_regtab
/* %st is first entry of table */)
4341 if (is_space_char (*s
))
4346 if (is_space_char (*s
))
4348 if (*s
>= '0' && *s
<= '7')
4350 r
= &i386_float_regtab
[*s
- '0'];
4352 if (is_space_char (*s
))
4360 /* We have "%st(" then garbage. */
4361 return (const reg_entry
*) NULL
;
4368 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4369 const char *md_shortopts
= "kVQ:sq";
4371 const char *md_shortopts
= "q";
4373 struct option md_longopts
[] = {
4374 #define OPTION_32 (OPTION_MD_BASE + 0)
4375 {"32", no_argument
, NULL
, OPTION_32
},
4376 #define OPTION_64 (OPTION_MD_BASE + 1)
4377 {"64", no_argument
, NULL
, OPTION_64
},
4378 {NULL
, no_argument
, NULL
, 0}
4380 size_t md_longopts_size
= sizeof (md_longopts
);
4383 md_parse_option (c
, arg
)
4385 char *arg ATTRIBUTE_UNUSED
;
4393 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4394 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4395 should be emitted or not. FIXME: Not implemented. */
4399 /* -V: SVR4 argument to print version ID. */
4401 print_version_id ();
4404 /* -k: Ignore for FreeBSD compatibility. */
4409 /* -s: On i386 Solaris, this tells the native assembler to use
4410 .stab instead of .stab.excl. We always use .stab anyhow. */
4417 const char **list
, **l
;
4419 default_arch
= c
== OPTION_32
? "i386" : "x86_64";
4420 list
= bfd_target_list ();
4421 for (l
= list
; *l
!= NULL
; l
++)
4425 if (strcmp (*l
, "elf32-i386") == 0)
4430 if (strcmp (*l
, "elf64-x86-64") == 0)
4435 as_fatal (_("No compiled in support for %d bit object file format"),
4436 c
== OPTION_32
? 32 : 64);
4449 md_show_usage (stream
)
4452 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4453 fprintf (stream
, _("\
4455 -V print assembler version number\n\
4457 -q quieten some warnings\n\
4460 fprintf (stream
, _("\
4461 -q quieten some warnings\n"));
4465 #ifdef BFD_ASSEMBLER
4466 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4467 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4469 /* Pick the target format to use. */
4472 i386_target_format ()
4474 if (!strcmp (default_arch
, "x86_64"))
4475 set_code_flag (CODE_64BIT
);
4476 else if (!strcmp (default_arch
, "i386"))
4477 set_code_flag (CODE_32BIT
);
4479 as_fatal (_("Unknown architecture"));
4480 switch (OUTPUT_FLAVOR
)
4482 #ifdef OBJ_MAYBE_AOUT
4483 case bfd_target_aout_flavour
:
4484 return AOUT_TARGET_FORMAT
;
4486 #ifdef OBJ_MAYBE_COFF
4487 case bfd_target_coff_flavour
:
4490 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4491 case bfd_target_elf_flavour
:
4493 if (flag_code
== CODE_64BIT
)
4494 use_rela_relocations
= 1;
4495 return flag_code
== CODE_64BIT
? "elf64-x86-64" : "elf32-i386";
4504 #endif /* OBJ_MAYBE_ more than one */
4505 #endif /* BFD_ASSEMBLER */
4508 md_undefined_symbol (name
)
4511 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4512 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4513 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4514 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4518 if (symbol_find (name
))
4519 as_bad (_("GOT already in symbol table"));
4520 GOT_symbol
= symbol_new (name
, undefined_section
,
4521 (valueT
) 0, &zero_address_frag
);
4528 /* Round up a section size to the appropriate boundary. */
4531 md_section_align (segment
, size
)
4532 segT segment ATTRIBUTE_UNUSED
;
4535 #ifdef BFD_ASSEMBLER
4536 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4537 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4539 /* For a.out, force the section size to be aligned. If we don't do
4540 this, BFD will align it for us, but it will not write out the
4541 final bytes of the section. This may be a bug in BFD, but it is
4542 easier to fix it here since that is how the other a.out targets
4546 align
= bfd_get_section_alignment (stdoutput
, segment
);
4547 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4555 /* On the i386, PC-relative offsets are relative to the start of the
4556 next instruction. That is, the address of the offset, plus its
4557 size, since the offset is always the last part of the insn. */
4560 md_pcrel_from (fixP
)
4563 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4570 int ignore ATTRIBUTE_UNUSED
;
4574 temp
= get_absolute_expression ();
4575 subseg_set (bss_section
, (subsegT
) temp
);
4576 demand_empty_rest_of_line ();
4581 #ifdef BFD_ASSEMBLER
4584 i386_validate_fix (fixp
)
4587 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
4589 /* GOTOFF relocation are nonsense in 64bit mode. */
4590 if (flag_code
== CODE_64BIT
)
4592 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
4598 tc_gen_reloc (section
, fixp
)
4599 asection
*section ATTRIBUTE_UNUSED
;
4603 bfd_reloc_code_real_type code
;
4605 switch (fixp
->fx_r_type
)
4607 case BFD_RELOC_X86_64_PLT32
:
4608 case BFD_RELOC_X86_64_GOT32
:
4609 case BFD_RELOC_X86_64_GOTPCREL
:
4610 case BFD_RELOC_386_PLT32
:
4611 case BFD_RELOC_386_GOT32
:
4612 case BFD_RELOC_386_GOTOFF
:
4613 case BFD_RELOC_386_GOTPC
:
4614 case BFD_RELOC_X86_64_32S
:
4616 case BFD_RELOC_VTABLE_ENTRY
:
4617 case BFD_RELOC_VTABLE_INHERIT
:
4618 code
= fixp
->fx_r_type
;
4623 switch (fixp
->fx_size
)
4626 as_bad (_("can not do %d byte pc-relative relocation"),
4628 code
= BFD_RELOC_32_PCREL
;
4630 case 1: code
= BFD_RELOC_8_PCREL
; break;
4631 case 2: code
= BFD_RELOC_16_PCREL
; break;
4632 case 4: code
= BFD_RELOC_32_PCREL
; break;
4637 switch (fixp
->fx_size
)
4640 as_bad (_("can not do %d byte relocation"), fixp
->fx_size
);
4641 code
= BFD_RELOC_32
;
4643 case 1: code
= BFD_RELOC_8
; break;
4644 case 2: code
= BFD_RELOC_16
; break;
4645 case 4: code
= BFD_RELOC_32
; break;
4646 case 8: code
= BFD_RELOC_64
; break;
4652 if (code
== BFD_RELOC_32
4654 && fixp
->fx_addsy
== GOT_symbol
)
4656 /* We don't support GOTPC on 64bit targets. */
4657 if (flag_code
== CODE_64BIT
)
4659 code
= BFD_RELOC_386_GOTPC
;
4662 rel
= (arelent
*) xmalloc (sizeof (arelent
));
4663 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4664 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4666 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4667 if (!use_rela_relocations
)
4669 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4670 vtable entry to be used in the relocation's section offset. */
4671 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4672 rel
->address
= fixp
->fx_offset
;
4675 rel
->addend
= fixp
->fx_addnumber
;
4679 /* Use the rela in 64bit mode. */
4682 rel
->addend
= fixp
->fx_offset
;
4684 /* Ohhh, this is ugly. The problem is that if this is a local global
4685 symbol, the relocation will entirely be performed at link time, not
4686 at assembly time. bfd_perform_reloc doesn't know about this sort
4687 of thing, and as a result we need to fake it out here. */
4688 if ((S_IS_EXTERN (fixp
->fx_addsy
) || S_IS_WEAK (fixp
->fx_addsy
))
4689 && !S_IS_COMMON(fixp
->fx_addsy
))
4690 rel
->addend
-= symbol_get_bfdsym (fixp
->fx_addsy
)->value
;
4693 rel
->addend
-= fixp
->fx_size
;
4697 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4698 if (rel
->howto
== NULL
)
4700 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4701 _("cannot represent relocation type %s"),
4702 bfd_get_reloc_code_name (code
));
4703 /* Set howto to a garbage value so that we can keep going. */
4704 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
4705 assert (rel
->howto
!= NULL
);
4711 #else /* ! BFD_ASSEMBLER */
4713 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4715 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4718 relax_addressT segment_address_in_file
;
4720 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4721 Out: GNU LD relocation length code: 0, 1, or 2. */
4723 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
4726 know (fixP
->fx_addsy
!= NULL
);
4728 md_number_to_chars (where
,
4729 (valueT
) (fixP
->fx_frag
->fr_address
4730 + fixP
->fx_where
- segment_address_in_file
),
4733 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4734 ? S_GET_TYPE (fixP
->fx_addsy
)
4735 : fixP
->fx_addsy
->sy_number
);
4737 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
4738 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4739 where
[4] = r_symbolnum
& 0x0ff;
4740 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
4741 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
4742 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
4745 #endif /* OBJ_AOUT or OBJ_BOUT. */
4747 #if defined (I386COFF)
4750 tc_coff_fix2rtype (fixP
)
4753 if (fixP
->fx_r_type
== R_IMAGEBASE
)
4756 return (fixP
->fx_pcrel
?
4757 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
4758 fixP
->fx_size
== 2 ? R_PCRWORD
:
4760 (fixP
->fx_size
== 1 ? R_RELBYTE
:
4761 fixP
->fx_size
== 2 ? R_RELWORD
:
4766 tc_coff_sizemachdep (frag
)
4770 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
4775 #endif /* I386COFF */
4777 #endif /* ! BFD_ASSEMBLER */
4779 /* Parse operands using Intel syntax. This implements a recursive descent
4780 parser based on the BNF grammar published in Appendix B of the MASM 6.1
4783 FIXME: We do not recognize the full operand grammar defined in the MASM
4784 documentation. In particular, all the structure/union and
4785 high-level macro operands are missing.
4787 Uppercase words are terminals, lower case words are non-terminals.
4788 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
4789 bars '|' denote choices. Most grammar productions are implemented in
4790 functions called 'intel_<production>'.
4792 Initial production is 'expr'.
4798 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
4800 constant digits [[ radixOverride ]]
4802 dataType BYTE | WORD | DWORD | QWORD | XWORD
4835 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
4836 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
4838 hexdigit a | b | c | d | e | f
4839 | A | B | C | D | E | F
4849 register specialRegister
4853 segmentRegister CS | DS | ES | FS | GS | SS
4855 specialRegister CR0 | CR2 | CR3
4856 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
4857 | TR3 | TR4 | TR5 | TR6 | TR7
4859 We simplify the grammar in obvious places (e.g., register parsing is
4860 done by calling parse_register) and eliminate immediate left recursion
4861 to implement a recursive-descent parser.
4901 /* Parsing structure for the intel syntax parser. Used to implement the
4902 semantic actions for the operand grammar. */
4903 struct intel_parser_s
4905 char *op_string
; /* The string being parsed. */
4906 int got_a_float
; /* Whether the operand is a float. */
4907 int op_modifier
; /* Operand modifier. */
4908 int is_mem
; /* 1 if operand is memory reference. */
4909 const reg_entry
*reg
; /* Last register reference found. */
4910 char *disp
; /* Displacement string being built. */
4913 static struct intel_parser_s intel_parser
;
4915 /* Token structure for parsing intel syntax. */
4918 int code
; /* Token code. */
4919 const reg_entry
*reg
; /* Register entry for register tokens. */
4920 char *str
; /* String representation. */
4923 static struct intel_token cur_token
, prev_token
;
4926 /* Token codes for the intel parser. Since T_SHORT is already used
4927 by COFF, undefine it first to prevent a warning. */
4942 /* Prototypes for intel parser functions. */
4943 static int intel_match_token
PARAMS ((int code
));
4944 static void intel_get_token
PARAMS ((void));
4945 static void intel_putback_token
PARAMS ((void));
4946 static int intel_expr
PARAMS ((void));
4947 static int intel_e05
PARAMS ((void));
4948 static int intel_e05_1
PARAMS ((void));
4949 static int intel_e06
PARAMS ((void));
4950 static int intel_e06_1
PARAMS ((void));
4951 static int intel_e09
PARAMS ((void));
4952 static int intel_e09_1
PARAMS ((void));
4953 static int intel_e10
PARAMS ((void));
4954 static int intel_e10_1
PARAMS ((void));
4955 static int intel_e11
PARAMS ((void));
4958 i386_intel_operand (operand_string
, got_a_float
)
4959 char *operand_string
;
4965 /* Initialize token holders. */
4966 cur_token
.code
= prev_token
.code
= T_NIL
;
4967 cur_token
.reg
= prev_token
.reg
= NULL
;
4968 cur_token
.str
= prev_token
.str
= NULL
;
4970 /* Initialize parser structure. */
4971 p
= intel_parser
.op_string
= (char *)malloc (strlen (operand_string
) + 1);
4974 strcpy (intel_parser
.op_string
, operand_string
);
4975 intel_parser
.got_a_float
= got_a_float
;
4976 intel_parser
.op_modifier
= -1;
4977 intel_parser
.is_mem
= 0;
4978 intel_parser
.reg
= NULL
;
4979 intel_parser
.disp
= (char *)malloc (strlen (operand_string
) + 1);
4980 if (intel_parser
.disp
== NULL
)
4982 intel_parser
.disp
[0] = '\0';
4984 /* Read the first token and start the parser. */
4986 ret
= intel_expr ();
4990 /* If we found a memory reference, hand it over to i386_displacement
4991 to fill in the rest of the operand fields. */
4992 if (intel_parser
.is_mem
)
4994 if ((i
.mem_operands
== 1
4995 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4996 || i
.mem_operands
== 2)
4998 as_bad (_("too many memory references for '%s'"),
4999 current_templates
->start
->name
);
5004 char *s
= intel_parser
.disp
;
5007 /* Add the displacement expression. */
5009 ret
= i386_displacement (s
, s
+ strlen (s
))
5010 && i386_index_check (s
);
5014 /* Constant and OFFSET expressions are handled by i386_immediate. */
5015 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5016 || intel_parser
.reg
== NULL
)
5017 ret
= i386_immediate (intel_parser
.disp
);
5021 free (intel_parser
.disp
);
5031 /* expr SHORT e05 */
5032 if (cur_token
.code
== T_SHORT
)
5034 intel_parser
.op_modifier
= SHORT
;
5035 intel_match_token (T_SHORT
);
5037 return (intel_e05 ());
5042 return intel_e05 ();
5052 return (intel_e06 () && intel_e05_1 ());
5058 /* e05' addOp e06 e05' */
5059 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5061 strcat (intel_parser
.disp
, cur_token
.str
);
5062 intel_match_token (cur_token
.code
);
5064 return (intel_e06 () && intel_e05_1 ());
5079 return (intel_e09 () && intel_e06_1 ());
5085 /* e06' mulOp e09 e06' */
5086 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5088 strcat (intel_parser
.disp
, cur_token
.str
);
5089 intel_match_token (cur_token
.code
);
5091 return (intel_e09 () && intel_e06_1 ());
5099 /* e09 OFFSET e10 e09'
5108 /* e09 OFFSET e10 e09' */
5109 if (cur_token
.code
== T_OFFSET
)
5111 intel_parser
.is_mem
= 0;
5112 intel_parser
.op_modifier
= OFFSET_FLAT
;
5113 intel_match_token (T_OFFSET
);
5115 return (intel_e10 () && intel_e09_1 ());
5120 return (intel_e10 () && intel_e09_1 ());
5126 /* e09' PTR e10 e09' */
5127 if (cur_token
.code
== T_PTR
)
5129 if (prev_token
.code
== T_BYTE
)
5130 i
.suffix
= BYTE_MNEM_SUFFIX
;
5132 else if (prev_token
.code
== T_WORD
)
5134 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5135 i
.suffix
= SHORT_MNEM_SUFFIX
;
5137 i
.suffix
= WORD_MNEM_SUFFIX
;
5140 else if (prev_token
.code
== T_DWORD
)
5142 if (intel_parser
.got_a_float
== 1) /* "f..." */
5143 i
.suffix
= SHORT_MNEM_SUFFIX
;
5145 i
.suffix
= LONG_MNEM_SUFFIX
;
5148 else if (prev_token
.code
== T_QWORD
)
5150 if (intel_parser
.got_a_float
== 1) /* "f..." */
5151 i
.suffix
= LONG_MNEM_SUFFIX
;
5153 i
.suffix
= QWORD_MNEM_SUFFIX
;
5156 else if (prev_token
.code
== T_XWORD
)
5157 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5161 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5165 intel_match_token (T_PTR
);
5167 return (intel_e10 () && intel_e09_1 ());
5170 /* e09 : e10 e09' */
5171 else if (cur_token
.code
== ':')
5173 /* Mark as a memory operand only if it's not already known to be an
5174 offset expression. */
5175 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5176 intel_parser
.is_mem
= 1;
5178 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5193 return (intel_e11 () && intel_e10_1 ());
5199 /* e10' [ expr ] e10' */
5200 if (cur_token
.code
== '[')
5202 intel_match_token ('[');
5204 /* Mark as a memory operand only if it's not already known to be an
5205 offset expression. If it's an offset expression, we need to keep
5207 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5208 intel_parser
.is_mem
= 1;
5210 strcat (intel_parser
.disp
, "[");
5212 /* Add a '+' to the displacement string if necessary. */
5213 if (*intel_parser
.disp
!= '\0'
5214 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5215 strcat (intel_parser
.disp
, "+");
5217 if (intel_expr () && intel_match_token (']'))
5219 /* Preserve brackets when the operand is an offset expression. */
5220 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5221 strcat (intel_parser
.disp
, "]");
5223 return intel_e10_1 ();
5250 if (cur_token
.code
== '(')
5252 intel_match_token ('(');
5253 strcat (intel_parser
.disp
, "(");
5255 if (intel_expr () && intel_match_token (')'))
5257 strcat (intel_parser
.disp
, ")");
5265 else if (cur_token
.code
== '[')
5267 intel_match_token ('[');
5269 /* Mark as a memory operand only if it's not already known to be an
5270 offset expression. If it's an offset expression, we need to keep
5272 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5273 intel_parser
.is_mem
= 1;
5275 strcat (intel_parser
.disp
, "[");
5277 /* Operands for jump/call inside brackets denote absolute addresses. */
5278 if (current_templates
->start
->opcode_modifier
& Jump
5279 || current_templates
->start
->opcode_modifier
& JumpDword
5280 || current_templates
->start
->opcode_modifier
& JumpByte
5281 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5282 i
.types
[this_operand
] |= JumpAbsolute
;
5284 /* Add a '+' to the displacement string if necessary. */
5285 if (*intel_parser
.disp
!= '\0'
5286 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5287 strcat (intel_parser
.disp
, "+");
5289 if (intel_expr () && intel_match_token (']'))
5291 /* Preserve brackets when the operand is an offset expression. */
5292 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5293 strcat (intel_parser
.disp
, "]");
5306 else if (cur_token
.code
== T_BYTE
5307 || cur_token
.code
== T_WORD
5308 || cur_token
.code
== T_DWORD
5309 || cur_token
.code
== T_QWORD
5310 || cur_token
.code
== T_XWORD
)
5312 intel_match_token (cur_token
.code
);
5319 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5321 strcat (intel_parser
.disp
, cur_token
.str
);
5322 intel_match_token (cur_token
.code
);
5324 /* Mark as a memory operand only if it's not already known to be an
5325 offset expression. */
5326 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5327 intel_parser
.is_mem
= 1;
5333 else if (cur_token
.code
== T_REG
)
5335 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5337 intel_match_token (T_REG
);
5339 /* Check for segment change. */
5340 if (cur_token
.code
== ':')
5342 if (reg
->reg_type
& (SReg2
| SReg3
))
5344 switch (reg
->reg_num
)
5347 i
.seg
[i
.mem_operands
] = &es
;
5350 i
.seg
[i
.mem_operands
] = &cs
;
5353 i
.seg
[i
.mem_operands
] = &ss
;
5356 i
.seg
[i
.mem_operands
] = &ds
;
5359 i
.seg
[i
.mem_operands
] = &fs
;
5362 i
.seg
[i
.mem_operands
] = &gs
;
5368 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5373 /* Not a segment register. Check for register scaling. */
5374 else if (cur_token
.code
== '*')
5376 if (!intel_parser
.is_mem
)
5378 as_bad (_("Register scaling only allowed in memory operands."));
5382 /* What follows must be a valid scale. */
5383 if (intel_match_token ('*')
5384 && strchr ("01248", *cur_token
.str
))
5387 i
.types
[this_operand
] |= BaseIndex
;
5389 /* Set the scale after setting the register (otherwise,
5390 i386_scale will complain) */
5391 i386_scale (cur_token
.str
);
5392 intel_match_token (T_CONST
);
5396 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5402 /* No scaling. If this is a memory operand, the register is either a
5403 base register (first occurrence) or an index register (second
5405 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5407 if (i
.base_reg
&& i
.index_reg
)
5409 as_bad (_("Too many register references in memory operand.\n"));
5413 if (i
.base_reg
== NULL
)
5418 i
.types
[this_operand
] |= BaseIndex
;
5421 /* Offset modifier. Add the register to the displacement string to be
5422 parsed as an immediate expression after we're done. */
5423 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5424 strcat (intel_parser
.disp
, reg
->reg_name
);
5426 /* It's neither base nor index nor offset. */
5429 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5430 i
.op
[this_operand
].regs
= reg
;
5434 /* Since registers are not part of the displacement string (except
5435 when we're parsing offset operands), we may need to remove any
5436 preceding '+' from the displacement string. */
5437 if (*intel_parser
.disp
!= '\0'
5438 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
5440 char *s
= intel_parser
.disp
;
5441 s
+= strlen (s
) - 1;
5450 else if (cur_token
.code
== T_ID
)
5452 /* Add the identifier to the displacement string. */
5453 strcat (intel_parser
.disp
, cur_token
.str
);
5454 intel_match_token (T_ID
);
5456 /* The identifier represents a memory reference only if it's not
5457 preceded by an offset modifier. */
5458 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5459 intel_parser
.is_mem
= 1;
5465 else if (cur_token
.code
== T_CONST
5466 || cur_token
.code
== '-'
5467 || cur_token
.code
== '+')
5471 /* Allow constants that start with `+' or `-'. */
5472 if (cur_token
.code
== '-' || cur_token
.code
== '+')
5474 strcat (intel_parser
.disp
, cur_token
.str
);
5475 intel_match_token (cur_token
.code
);
5476 if (cur_token
.code
!= T_CONST
)
5478 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5484 save_str
= (char *)malloc (strlen (cur_token
.str
) + 1);
5485 if (save_str
== NULL
)
5487 strcpy (save_str
, cur_token
.str
);
5489 /* Get the next token to check for register scaling. */
5490 intel_match_token (cur_token
.code
);
5492 /* Check if this constant is a scaling factor for an index register. */
5493 if (cur_token
.code
== '*')
5495 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
5497 if (!intel_parser
.is_mem
)
5499 as_bad (_("Register scaling only allowed in memory operands."));
5503 /* The constant is followed by `* reg', so it must be
5505 if (strchr ("01248", *save_str
))
5507 i
.index_reg
= cur_token
.reg
;
5508 i
.types
[this_operand
] |= BaseIndex
;
5510 /* Set the scale after setting the register (otherwise,
5511 i386_scale will complain) */
5512 i386_scale (save_str
);
5513 intel_match_token (T_REG
);
5515 /* Since registers are not part of the displacement
5516 string, we may need to remove any preceding '+' from
5517 the displacement string. */
5518 if (*intel_parser
.disp
!= '\0')
5520 char *s
= intel_parser
.disp
;
5521 s
+= strlen (s
) - 1;
5534 /* The constant was not used for register scaling. Since we have
5535 already consumed the token following `*' we now need to put it
5536 back in the stream. */
5538 intel_putback_token ();
5541 /* Add the constant to the displacement string. */
5542 strcat (intel_parser
.disp
, save_str
);
5548 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
5552 /* Match the given token against cur_token. If they match, read the next
5553 token from the operand string. */
5555 intel_match_token (code
)
5558 if (cur_token
.code
== code
)
5565 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
5570 /* Read a new token from intel_parser.op_string and store it in cur_token. */
5575 const reg_entry
*reg
;
5576 struct intel_token new_token
;
5578 new_token
.code
= T_NIL
;
5579 new_token
.reg
= NULL
;
5580 new_token
.str
= NULL
;
5582 /* Free the memory allocated to the previous token and move
5583 cur_token to prev_token. */
5585 free (prev_token
.str
);
5587 prev_token
= cur_token
;
5589 /* Skip whitespace. */
5590 while (is_space_char (*intel_parser
.op_string
))
5591 intel_parser
.op_string
++;
5593 /* Return an empty token if we find nothing else on the line. */
5594 if (*intel_parser
.op_string
== '\0')
5596 cur_token
= new_token
;
5600 /* The new token cannot be larger than the remainder of the operand
5602 new_token
.str
= (char *)malloc (strlen (intel_parser
.op_string
) + 1);
5603 if (new_token
.str
== NULL
)
5605 new_token
.str
[0] = '\0';
5607 if (strchr ("0123456789", *intel_parser
.op_string
))
5609 char *p
= new_token
.str
;
5610 char *q
= intel_parser
.op_string
;
5611 new_token
.code
= T_CONST
;
5613 /* Allow any kind of identifier char to encompass floating point and
5614 hexadecimal numbers. */
5615 while (is_identifier_char (*q
))
5619 /* Recognize special symbol names [0-9][bf]. */
5620 if (strlen (intel_parser
.op_string
) == 2
5621 && (intel_parser
.op_string
[1] == 'b'
5622 || intel_parser
.op_string
[1] == 'f'))
5623 new_token
.code
= T_ID
;
5626 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
5628 new_token
.code
= *intel_parser
.op_string
;
5629 new_token
.str
[0] = *intel_parser
.op_string
;
5630 new_token
.str
[1] = '\0';
5633 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5634 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
5636 new_token
.code
= T_REG
;
5637 new_token
.reg
= reg
;
5639 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
5641 new_token
.str
[0] = REGISTER_PREFIX
;
5642 new_token
.str
[1] = '\0';
5645 strcat (new_token
.str
, reg
->reg_name
);
5648 else if (is_identifier_char (*intel_parser
.op_string
))
5650 char *p
= new_token
.str
;
5651 char *q
= intel_parser
.op_string
;
5653 /* A '.' or '$' followed by an identifier char is an identifier.
5654 Otherwise, it's operator '.' followed by an expression. */
5655 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
5657 new_token
.code
= *q
;
5658 new_token
.str
[0] = *q
;
5659 new_token
.str
[1] = '\0';
5663 while (is_identifier_char (*q
) || *q
== '@')
5667 if (strcasecmp (new_token
.str
, "BYTE") == 0)
5668 new_token
.code
= T_BYTE
;
5670 else if (strcasecmp (new_token
.str
, "WORD") == 0)
5671 new_token
.code
= T_WORD
;
5673 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
5674 new_token
.code
= T_DWORD
;
5676 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
5677 new_token
.code
= T_QWORD
;
5679 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
5680 new_token
.code
= T_XWORD
;
5682 else if (strcasecmp (new_token
.str
, "PTR") == 0)
5683 new_token
.code
= T_PTR
;
5685 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
5686 new_token
.code
= T_SHORT
;
5688 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
5690 new_token
.code
= T_OFFSET
;
5692 /* ??? This is not mentioned in the MASM grammar but gcc
5693 makes use of it with -mintel-syntax. OFFSET may be
5694 followed by FLAT: */
5695 if (strncasecmp (q
, " FLAT:", 6) == 0)
5696 strcat (new_token
.str
, " FLAT:");
5699 /* ??? This is not mentioned in the MASM grammar. */
5700 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
5701 new_token
.code
= T_OFFSET
;
5704 new_token
.code
= T_ID
;
5709 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
5711 intel_parser
.op_string
+= strlen (new_token
.str
);
5712 cur_token
= new_token
;
5715 /* Put cur_token back into the token stream and make cur_token point to
5718 intel_putback_token ()
5720 intel_parser
.op_string
-= strlen (cur_token
.str
);
5721 free (cur_token
.str
);
5722 cur_token
= prev_token
;
5724 /* Forget prev_token. */
5725 prev_token
.code
= T_NIL
;
5726 prev_token
.reg
= NULL
;
5727 prev_token
.str
= NULL
;