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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2017 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
20
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
27
28 #include "as.h"
29 #include "safe-ctype.h"
30 #include "subsegs.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
35
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
38 #endif
39
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
42 #endif
43
44 #ifndef DEFAULT_ARCH
45 #define DEFAULT_ARCH "i386"
46 #endif
47
48 #ifndef INLINE
49 #if __GNUC__ >= 2
50 #define INLINE __inline__
51 #else
52 #define INLINE
53 #endif
54 #endif
55
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
61 #define WAIT_PREFIX 0
62 #define SEG_PREFIX 1
63 #define ADDR_PREFIX 2
64 #define DATA_PREFIX 3
65 #define REP_PREFIX 4
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
68 #define LOCK_PREFIX 5
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
71
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
76
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91 #define END_OF_INSN '\0'
92
93 /*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100 typedef struct
101 {
102 const insn_template *start;
103 const insn_template *end;
104 }
105 templates;
106
107 /* 386 operand encoding bytes: see 386 book for details of this. */
108 typedef struct
109 {
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113 }
114 modrm_byte;
115
116 /* x86-64 extension prefix. */
117 typedef int rex_byte;
118
119 /* 386 opcode byte to code indirect addressing. */
120 typedef struct
121 {
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125 }
126 sib_byte;
127
128 /* x86 arch names, types and features */
129 typedef struct
130 {
131 const char *name; /* arch name */
132 unsigned int len; /* arch string length */
133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
135 unsigned int skip; /* show_arch should skip this. */
136 }
137 arch_entry;
138
139 /* Used to turn off indicated flags. */
140 typedef struct
141 {
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145 }
146 noarch_entry;
147
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
156 #ifdef TE_PE
157 static void pe_directive_secrel (int);
158 #endif
159 static void signed_cons (int);
160 static char *output_invalid (int c);
161 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS *);
168 static int i386_intel_parse_name (const char *, expressionS *);
169 static const reg_entry *parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template *match_template (char);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry *build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS *, offsetT);
188 static void output_disp (fragS *, offsetT);
189 #ifndef I386COFF
190 static void s_bss (int);
191 #endif
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED);
194 #endif
195
196 static const char *default_arch = DEFAULT_ARCH;
197
198 /* This struct describes rounding control and SAE in the instruction. */
199 struct RC_Operation
200 {
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210 };
211
212 static struct RC_Operation rc_op;
213
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
218 {
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223 };
224
225 static struct Mask_Operation mask_op;
226
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229 struct Broadcast_Operation
230 {
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236 };
237
238 static struct Broadcast_Operation broadcast_op;
239
240 /* VEX prefix. */
241 typedef struct
242 {
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248 } vex_prefix;
249
250 /* 'md_assemble ()' gathers together information and puts it into a
251 i386_insn. */
252
253 union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
260 enum i386_error
261 {
262 operand_size_mismatch,
263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
271 unsupported,
272 invalid_vsib_address,
273 invalid_vector_register_set,
274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
284 try_vector_disp8
285 };
286
287 struct _i386_insn
288 {
289 /* TM holds the template for the insn were currently assembling. */
290 insn_template tm;
291
292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
294 char suffix;
295
296 /* OPERANDS gives the number of given operands. */
297 unsigned int operands;
298
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
301 operands. */
302 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
303
304 /* TYPES [i] is the type (see above #defines) which tells us how to
305 use OP[i] for the corresponding operand. */
306 i386_operand_type types[MAX_OPERANDS];
307
308 /* Displacement expression, immediate expression, or register for each
309 operand. */
310 union i386_op op[MAX_OPERANDS];
311
312 /* Flags for operands. */
313 unsigned int flags[MAX_OPERANDS];
314 #define Operand_PCrel 1
315
316 /* Relocation type for operand */
317 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
318
319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry *base_reg;
322 const reg_entry *index_reg;
323 unsigned int log2_scale_factor;
324
325 /* SEG gives the seg_entries of this insn. They are zero unless
326 explicit segment overrides are given. */
327 const seg_entry *seg[2];
328
329 /* Copied first memory operand string, for re-checking. */
330 char *memop1_string;
331
332 /* PREFIX holds all the given prefix opcodes (usually null).
333 PREFIXES is the number of prefix opcodes. */
334 unsigned int prefixes;
335 unsigned char prefix[MAX_PREFIXES];
336
337 /* RM and SIB are the modrm byte and the sib byte where the
338 addressing modes of this insn are encoded. */
339 modrm_byte rm;
340 rex_byte rex;
341 rex_byte vrex;
342 sib_byte sib;
343 vex_prefix vex;
344
345 /* Masking attributes. */
346 struct Mask_Operation *mask;
347
348 /* Rounding control and SAE attributes. */
349 struct RC_Operation *rounding;
350
351 /* Broadcasting attributes. */
352 struct Broadcast_Operation *broadcast;
353
354 /* Compressed disp8*N attribute. */
355 unsigned int memshift;
356
357 /* Prefer load or store in encoding. */
358 enum
359 {
360 dir_encoding_default = 0,
361 dir_encoding_load,
362 dir_encoding_store
363 } dir_encoding;
364
365 /* Prefer 8bit or 32bit displacement in encoding. */
366 enum
367 {
368 disp_encoding_default = 0,
369 disp_encoding_8bit,
370 disp_encoding_32bit
371 } disp_encoding;
372
373 /* How to encode vector instructions. */
374 enum
375 {
376 vex_encoding_default = 0,
377 vex_encoding_vex2,
378 vex_encoding_vex3,
379 vex_encoding_evex
380 } vec_encoding;
381
382 /* REP prefix. */
383 const char *rep_prefix;
384
385 /* HLE prefix. */
386 const char *hle_prefix;
387
388 /* Have BND prefix. */
389 const char *bnd_prefix;
390
391 /* Have NOTRACK prefix. */
392 const char *notrack_prefix;
393
394 /* Error message. */
395 enum i386_error error;
396 };
397
398 typedef struct _i386_insn i386_insn;
399
400 /* Link RC type with corresponding string, that'll be looked for in
401 asm. */
402 struct RC_name
403 {
404 enum rc_type type;
405 const char *name;
406 unsigned int len;
407 };
408
409 static const struct RC_name RC_NamesTable[] =
410 {
411 { rne, STRING_COMMA_LEN ("rn-sae") },
412 { rd, STRING_COMMA_LEN ("rd-sae") },
413 { ru, STRING_COMMA_LEN ("ru-sae") },
414 { rz, STRING_COMMA_LEN ("rz-sae") },
415 { saeonly, STRING_COMMA_LEN ("sae") },
416 };
417
418 /* List of chars besides those in app.c:symbol_chars that can start an
419 operand. Used to prevent the scrubber eating vital white-space. */
420 const char extra_symbol_chars[] = "*%-([{}"
421 #ifdef LEX_AT
422 "@"
423 #endif
424 #ifdef LEX_QM
425 "?"
426 #endif
427 ;
428
429 #if (defined (TE_I386AIX) \
430 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
431 && !defined (TE_GNU) \
432 && !defined (TE_LINUX) \
433 && !defined (TE_NACL) \
434 && !defined (TE_NETWARE) \
435 && !defined (TE_FreeBSD) \
436 && !defined (TE_DragonFly) \
437 && !defined (TE_NetBSD)))
438 /* This array holds the chars that always start a comment. If the
439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441 const char *i386_comment_chars = "#/";
442 #define SVR4_COMMENT_CHARS 1
443 #define PREFIX_SEPARATOR '\\'
444
445 #else
446 const char *i386_comment_chars = "#";
447 #define PREFIX_SEPARATOR '/'
448 #endif
449
450 /* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
454 first line of the input file. This is because the compiler outputs
455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
457 '/' isn't otherwise defined. */
458 const char line_comment_chars[] = "#/";
459
460 const char line_separator_chars[] = ";";
461
462 /* Chars that can be used to separate mant from exp in floating point
463 nums. */
464 const char EXP_CHARS[] = "eE";
465
466 /* Chars that mean this number is a floating point constant
467 As in 0f12.456
468 or 0d1.2345e12. */
469 const char FLT_CHARS[] = "fFdDxX";
470
471 /* Tables for lexical analysis. */
472 static char mnemonic_chars[256];
473 static char register_chars[256];
474 static char operand_chars[256];
475 static char identifier_chars[256];
476 static char digit_chars[256];
477
478 /* Lexical macros. */
479 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480 #define is_operand_char(x) (operand_chars[(unsigned char) x])
481 #define is_register_char(x) (register_chars[(unsigned char) x])
482 #define is_space_char(x) ((x) == ' ')
483 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484 #define is_digit_char(x) (digit_chars[(unsigned char) x])
485
486 /* All non-digit non-letter characters that may occur in an operand. */
487 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
488
489 /* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
492 assembler instruction). */
493 static char save_stack[32];
494 static char *save_stack_p;
495 #define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497 #define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
499
500 /* The instruction we're assembling. */
501 static i386_insn i;
502
503 /* Possible templates for current insn. */
504 static const templates *current_templates;
505
506 /* Per instruction expressionS buffers: max displacements & immediates. */
507 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
508 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
509
510 /* Current operand we are working on. */
511 static int this_operand = -1;
512
513 /* We support four different modes. FLAG_CODE variable is used to distinguish
514 these. */
515
516 enum flag_code {
517 CODE_32BIT,
518 CODE_16BIT,
519 CODE_64BIT };
520
521 static enum flag_code flag_code;
522 static unsigned int object_64bit;
523 static unsigned int disallow_64bit_reloc;
524 static int use_rela_relocations = 0;
525
526 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
529
530 /* The ELF ABI to use. */
531 enum x86_elf_abi
532 {
533 I386_ABI,
534 X86_64_ABI,
535 X86_64_X32_ABI
536 };
537
538 static enum x86_elf_abi x86_elf_abi = I386_ABI;
539 #endif
540
541 #if defined (TE_PE) || defined (TE_PEP)
542 /* Use big object file format. */
543 static int use_big_obj = 0;
544 #endif
545
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 /* 1 if generating code for a shared library. */
548 static int shared = 0;
549 #endif
550
551 /* 1 for intel syntax,
552 0 if att syntax. */
553 static int intel_syntax = 0;
554
555 /* 1 for Intel64 ISA,
556 0 if AMD64 ISA. */
557 static int intel64;
558
559 /* 1 for intel mnemonic,
560 0 if att mnemonic. */
561 static int intel_mnemonic = !SYSV386_COMPAT;
562
563 /* 1 if support old (<= 2.8.1) versions of gcc. */
564 static int old_gcc = OLDGCC_COMPAT;
565
566 /* 1 if pseudo registers are permitted. */
567 static int allow_pseudo_reg = 0;
568
569 /* 1 if register prefix % not required. */
570 static int allow_naked_reg = 0;
571
572 /* 1 if the assembler should add BND prefix for all control-transferring
573 instructions supporting it, even if this prefix wasn't specified
574 explicitly. */
575 static int add_bnd_prefix = 0;
576
577 /* 1 if pseudo index register, eiz/riz, is allowed . */
578 static int allow_index_reg = 0;
579
580 /* 1 if the assembler should ignore LOCK prefix, even if it was
581 specified explicitly. */
582 static int omit_lock_prefix = 0;
583
584 /* 1 if the assembler should encode lfence, mfence, and sfence as
585 "lock addl $0, (%{re}sp)". */
586 static int avoid_fence = 0;
587
588 /* 1 if the assembler should generate relax relocations. */
589
590 static int generate_relax_relocations
591 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
592
593 static enum check_kind
594 {
595 check_none = 0,
596 check_warning,
597 check_error
598 }
599 sse_check, operand_check = check_warning;
600
601 /* Register prefix used for error message. */
602 static const char *register_prefix = "%";
603
604 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
605 leave, push, and pop instructions so that gcc has the same stack
606 frame as in 32 bit mode. */
607 static char stackop_size = '\0';
608
609 /* Non-zero to optimize code alignment. */
610 int optimize_align_code = 1;
611
612 /* Non-zero to quieten some warnings. */
613 static int quiet_warnings = 0;
614
615 /* CPU name. */
616 static const char *cpu_arch_name = NULL;
617 static char *cpu_sub_arch_name = NULL;
618
619 /* CPU feature flags. */
620 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
621
622 /* If we have selected a cpu we are generating instructions for. */
623 static int cpu_arch_tune_set = 0;
624
625 /* Cpu we are generating instructions for. */
626 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
627
628 /* CPU feature flags of cpu we are generating instructions for. */
629 static i386_cpu_flags cpu_arch_tune_flags;
630
631 /* CPU instruction set architecture used. */
632 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
633
634 /* CPU feature flags of instruction set architecture used. */
635 i386_cpu_flags cpu_arch_isa_flags;
636
637 /* If set, conditional jumps are not automatically promoted to handle
638 larger than a byte offset. */
639 static unsigned int no_cond_jump_promotion = 0;
640
641 /* Encode SSE instructions with VEX prefix. */
642 static unsigned int sse2avx;
643
644 /* Encode scalar AVX instructions with specific vector length. */
645 static enum
646 {
647 vex128 = 0,
648 vex256
649 } avxscalar;
650
651 /* Encode scalar EVEX LIG instructions with specific vector length. */
652 static enum
653 {
654 evexl128 = 0,
655 evexl256,
656 evexl512
657 } evexlig;
658
659 /* Encode EVEX WIG instructions with specific evex.w. */
660 static enum
661 {
662 evexw0 = 0,
663 evexw1
664 } evexwig;
665
666 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
667 static enum rc_type evexrcig = rne;
668
669 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
670 static symbolS *GOT_symbol;
671
672 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
673 unsigned int x86_dwarf2_return_column;
674
675 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
676 int x86_cie_data_alignment;
677
678 /* Interface to relax_segment.
679 There are 3 major relax states for 386 jump insns because the
680 different types of jumps add different sizes to frags when we're
681 figuring out what sort of jump to choose to reach a given label. */
682
683 /* Types. */
684 #define UNCOND_JUMP 0
685 #define COND_JUMP 1
686 #define COND_JUMP86 2
687
688 /* Sizes. */
689 #define CODE16 1
690 #define SMALL 0
691 #define SMALL16 (SMALL | CODE16)
692 #define BIG 2
693 #define BIG16 (BIG | CODE16)
694
695 #ifndef INLINE
696 #ifdef __GNUC__
697 #define INLINE __inline__
698 #else
699 #define INLINE
700 #endif
701 #endif
702
703 #define ENCODE_RELAX_STATE(type, size) \
704 ((relax_substateT) (((type) << 2) | (size)))
705 #define TYPE_FROM_RELAX_STATE(s) \
706 ((s) >> 2)
707 #define DISP_SIZE_FROM_RELAX_STATE(s) \
708 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
709
710 /* This table is used by relax_frag to promote short jumps to long
711 ones where necessary. SMALL (short) jumps may be promoted to BIG
712 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
713 don't allow a short jump in a 32 bit code segment to be promoted to
714 a 16 bit offset jump because it's slower (requires data size
715 prefix), and doesn't work, unless the destination is in the bottom
716 64k of the code segment (The top 16 bits of eip are zeroed). */
717
718 const relax_typeS md_relax_table[] =
719 {
720 /* The fields are:
721 1) most positive reach of this state,
722 2) most negative reach of this state,
723 3) how many bytes this mode will have in the variable part of the frag
724 4) which index into the table to try if we can't fit into this one. */
725
726 /* UNCOND_JUMP states. */
727 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
728 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
729 /* dword jmp adds 4 bytes to frag:
730 0 extra opcode bytes, 4 displacement bytes. */
731 {0, 0, 4, 0},
732 /* word jmp adds 2 byte2 to frag:
733 0 extra opcode bytes, 2 displacement bytes. */
734 {0, 0, 2, 0},
735
736 /* COND_JUMP states. */
737 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
738 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
739 /* dword conditionals adds 5 bytes to frag:
740 1 extra opcode byte, 4 displacement bytes. */
741 {0, 0, 5, 0},
742 /* word conditionals add 3 bytes to frag:
743 1 extra opcode byte, 2 displacement bytes. */
744 {0, 0, 3, 0},
745
746 /* COND_JUMP86 states. */
747 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
748 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
749 /* dword conditionals adds 5 bytes to frag:
750 1 extra opcode byte, 4 displacement bytes. */
751 {0, 0, 5, 0},
752 /* word conditionals add 4 bytes to frag:
753 1 displacement byte and a 3 byte long branch insn. */
754 {0, 0, 4, 0}
755 };
756
757 static const arch_entry cpu_arch[] =
758 {
759 /* Do not replace the first two entries - i386_target_format()
760 relies on them being there in this order. */
761 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
762 CPU_GENERIC32_FLAGS, 0 },
763 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
764 CPU_GENERIC64_FLAGS, 0 },
765 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
766 CPU_NONE_FLAGS, 0 },
767 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
768 CPU_I186_FLAGS, 0 },
769 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
770 CPU_I286_FLAGS, 0 },
771 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
772 CPU_I386_FLAGS, 0 },
773 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
774 CPU_I486_FLAGS, 0 },
775 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
776 CPU_I586_FLAGS, 0 },
777 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
778 CPU_I686_FLAGS, 0 },
779 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
780 CPU_I586_FLAGS, 0 },
781 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
782 CPU_PENTIUMPRO_FLAGS, 0 },
783 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
784 CPU_P2_FLAGS, 0 },
785 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
786 CPU_P3_FLAGS, 0 },
787 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
788 CPU_P4_FLAGS, 0 },
789 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
790 CPU_CORE_FLAGS, 0 },
791 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
792 CPU_NOCONA_FLAGS, 0 },
793 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
794 CPU_CORE_FLAGS, 1 },
795 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
796 CPU_CORE_FLAGS, 0 },
797 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
798 CPU_CORE2_FLAGS, 1 },
799 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
800 CPU_CORE2_FLAGS, 0 },
801 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
802 CPU_COREI7_FLAGS, 0 },
803 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
804 CPU_L1OM_FLAGS, 0 },
805 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
806 CPU_K1OM_FLAGS, 0 },
807 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
808 CPU_IAMCU_FLAGS, 0 },
809 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
810 CPU_K6_FLAGS, 0 },
811 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
812 CPU_K6_2_FLAGS, 0 },
813 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
814 CPU_ATHLON_FLAGS, 0 },
815 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
816 CPU_K8_FLAGS, 1 },
817 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
818 CPU_K8_FLAGS, 0 },
819 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
820 CPU_K8_FLAGS, 0 },
821 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
822 CPU_AMDFAM10_FLAGS, 0 },
823 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
824 CPU_BDVER1_FLAGS, 0 },
825 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
826 CPU_BDVER2_FLAGS, 0 },
827 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
828 CPU_BDVER3_FLAGS, 0 },
829 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
830 CPU_BDVER4_FLAGS, 0 },
831 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
832 CPU_ZNVER1_FLAGS, 0 },
833 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
834 CPU_BTVER1_FLAGS, 0 },
835 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
836 CPU_BTVER2_FLAGS, 0 },
837 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
838 CPU_8087_FLAGS, 0 },
839 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
840 CPU_287_FLAGS, 0 },
841 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
842 CPU_387_FLAGS, 0 },
843 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
844 CPU_687_FLAGS, 0 },
845 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
846 CPU_MMX_FLAGS, 0 },
847 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
848 CPU_SSE_FLAGS, 0 },
849 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
850 CPU_SSE2_FLAGS, 0 },
851 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
852 CPU_SSE3_FLAGS, 0 },
853 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
854 CPU_SSSE3_FLAGS, 0 },
855 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
856 CPU_SSE4_1_FLAGS, 0 },
857 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
858 CPU_SSE4_2_FLAGS, 0 },
859 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
860 CPU_SSE4_2_FLAGS, 0 },
861 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
862 CPU_AVX_FLAGS, 0 },
863 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
864 CPU_AVX2_FLAGS, 0 },
865 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
866 CPU_AVX512F_FLAGS, 0 },
867 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
868 CPU_AVX512CD_FLAGS, 0 },
869 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
870 CPU_AVX512ER_FLAGS, 0 },
871 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
872 CPU_AVX512PF_FLAGS, 0 },
873 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
874 CPU_AVX512DQ_FLAGS, 0 },
875 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
876 CPU_AVX512BW_FLAGS, 0 },
877 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
878 CPU_AVX512VL_FLAGS, 0 },
879 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
880 CPU_VMX_FLAGS, 0 },
881 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
882 CPU_VMFUNC_FLAGS, 0 },
883 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
884 CPU_SMX_FLAGS, 0 },
885 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
886 CPU_XSAVE_FLAGS, 0 },
887 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
888 CPU_XSAVEOPT_FLAGS, 0 },
889 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
890 CPU_XSAVEC_FLAGS, 0 },
891 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
892 CPU_XSAVES_FLAGS, 0 },
893 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
894 CPU_AES_FLAGS, 0 },
895 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
896 CPU_PCLMUL_FLAGS, 0 },
897 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
898 CPU_PCLMUL_FLAGS, 1 },
899 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
900 CPU_FSGSBASE_FLAGS, 0 },
901 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
902 CPU_RDRND_FLAGS, 0 },
903 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
904 CPU_F16C_FLAGS, 0 },
905 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
906 CPU_BMI2_FLAGS, 0 },
907 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
908 CPU_FMA_FLAGS, 0 },
909 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
910 CPU_FMA4_FLAGS, 0 },
911 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
912 CPU_XOP_FLAGS, 0 },
913 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
914 CPU_LWP_FLAGS, 0 },
915 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
916 CPU_MOVBE_FLAGS, 0 },
917 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
918 CPU_CX16_FLAGS, 0 },
919 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
920 CPU_EPT_FLAGS, 0 },
921 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
922 CPU_LZCNT_FLAGS, 0 },
923 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
924 CPU_HLE_FLAGS, 0 },
925 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
926 CPU_RTM_FLAGS, 0 },
927 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
928 CPU_INVPCID_FLAGS, 0 },
929 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
930 CPU_CLFLUSH_FLAGS, 0 },
931 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
932 CPU_NOP_FLAGS, 0 },
933 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
934 CPU_SYSCALL_FLAGS, 0 },
935 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
936 CPU_RDTSCP_FLAGS, 0 },
937 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
938 CPU_3DNOW_FLAGS, 0 },
939 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
940 CPU_3DNOWA_FLAGS, 0 },
941 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
942 CPU_PADLOCK_FLAGS, 0 },
943 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
944 CPU_SVME_FLAGS, 1 },
945 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
946 CPU_SVME_FLAGS, 0 },
947 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
948 CPU_SSE4A_FLAGS, 0 },
949 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
950 CPU_ABM_FLAGS, 0 },
951 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
952 CPU_BMI_FLAGS, 0 },
953 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
954 CPU_TBM_FLAGS, 0 },
955 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
956 CPU_ADX_FLAGS, 0 },
957 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
958 CPU_RDSEED_FLAGS, 0 },
959 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
960 CPU_PRFCHW_FLAGS, 0 },
961 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
962 CPU_SMAP_FLAGS, 0 },
963 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
964 CPU_MPX_FLAGS, 0 },
965 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
966 CPU_SHA_FLAGS, 0 },
967 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
968 CPU_CLFLUSHOPT_FLAGS, 0 },
969 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
970 CPU_PREFETCHWT1_FLAGS, 0 },
971 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
972 CPU_SE1_FLAGS, 0 },
973 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
974 CPU_CLWB_FLAGS, 0 },
975 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
976 CPU_AVX512IFMA_FLAGS, 0 },
977 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
978 CPU_AVX512VBMI_FLAGS, 0 },
979 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
980 CPU_AVX512_4FMAPS_FLAGS, 0 },
981 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
982 CPU_AVX512_4VNNIW_FLAGS, 0 },
983 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
984 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
985 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
986 CPU_AVX512_VBMI2_FLAGS, 0 },
987 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
988 CPU_CLZERO_FLAGS, 0 },
989 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
990 CPU_MWAITX_FLAGS, 0 },
991 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
992 CPU_OSPKE_FLAGS, 0 },
993 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
994 CPU_RDPID_FLAGS, 0 },
995 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
996 CPU_PTWRITE_FLAGS, 0 },
997 { STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN,
998 CPU_CET_FLAGS, 0 },
999 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1000 CPU_GFNI_FLAGS, 0 },
1001 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1002 CPU_VAES_FLAGS, 0 },
1003 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1004 CPU_VPCLMULQDQ_FLAGS, 0 },
1005 };
1006
1007 static const noarch_entry cpu_noarch[] =
1008 {
1009 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1010 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1011 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1012 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1013 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1014 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1015 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1016 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1017 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1018 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1019 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1020 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1021 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1022 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1023 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1024 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1025 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1026 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1027 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1028 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1029 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1030 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1031 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1032 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1033 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1034 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1035 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1036 };
1037
1038 #ifdef I386COFF
1039 /* Like s_lcomm_internal in gas/read.c but the alignment string
1040 is allowed to be optional. */
1041
1042 static symbolS *
1043 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1044 {
1045 addressT align = 0;
1046
1047 SKIP_WHITESPACE ();
1048
1049 if (needs_align
1050 && *input_line_pointer == ',')
1051 {
1052 align = parse_align (needs_align - 1);
1053
1054 if (align == (addressT) -1)
1055 return NULL;
1056 }
1057 else
1058 {
1059 if (size >= 8)
1060 align = 3;
1061 else if (size >= 4)
1062 align = 2;
1063 else if (size >= 2)
1064 align = 1;
1065 else
1066 align = 0;
1067 }
1068
1069 bss_alloc (symbolP, size, align);
1070 return symbolP;
1071 }
1072
1073 static void
1074 pe_lcomm (int needs_align)
1075 {
1076 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1077 }
1078 #endif
1079
1080 const pseudo_typeS md_pseudo_table[] =
1081 {
1082 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1083 {"align", s_align_bytes, 0},
1084 #else
1085 {"align", s_align_ptwo, 0},
1086 #endif
1087 {"arch", set_cpu_arch, 0},
1088 #ifndef I386COFF
1089 {"bss", s_bss, 0},
1090 #else
1091 {"lcomm", pe_lcomm, 1},
1092 #endif
1093 {"ffloat", float_cons, 'f'},
1094 {"dfloat", float_cons, 'd'},
1095 {"tfloat", float_cons, 'x'},
1096 {"value", cons, 2},
1097 {"slong", signed_cons, 4},
1098 {"noopt", s_ignore, 0},
1099 {"optim", s_ignore, 0},
1100 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1101 {"code16", set_code_flag, CODE_16BIT},
1102 {"code32", set_code_flag, CODE_32BIT},
1103 {"code64", set_code_flag, CODE_64BIT},
1104 {"intel_syntax", set_intel_syntax, 1},
1105 {"att_syntax", set_intel_syntax, 0},
1106 {"intel_mnemonic", set_intel_mnemonic, 1},
1107 {"att_mnemonic", set_intel_mnemonic, 0},
1108 {"allow_index_reg", set_allow_index_reg, 1},
1109 {"disallow_index_reg", set_allow_index_reg, 0},
1110 {"sse_check", set_check, 0},
1111 {"operand_check", set_check, 1},
1112 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1113 {"largecomm", handle_large_common, 0},
1114 #else
1115 {"file", (void (*) (int)) dwarf2_directive_file, 0},
1116 {"loc", dwarf2_directive_loc, 0},
1117 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1118 #endif
1119 #ifdef TE_PE
1120 {"secrel32", pe_directive_secrel, 0},
1121 #endif
1122 {0, 0, 0}
1123 };
1124
1125 /* For interface with expression (). */
1126 extern char *input_line_pointer;
1127
1128 /* Hash table for instruction mnemonic lookup. */
1129 static struct hash_control *op_hash;
1130
1131 /* Hash table for register lookup. */
1132 static struct hash_control *reg_hash;
1133 \f
1134 void
1135 i386_align_code (fragS *fragP, int count)
1136 {
1137 /* Various efficient no-op patterns for aligning code labels.
1138 Note: Don't try to assemble the instructions in the comments.
1139 0L and 0w are not legal. */
1140 static const unsigned char f32_1[] =
1141 {0x90}; /* nop */
1142 static const unsigned char f32_2[] =
1143 {0x66,0x90}; /* xchg %ax,%ax */
1144 static const unsigned char f32_3[] =
1145 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1146 static const unsigned char f32_4[] =
1147 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1148 static const unsigned char f32_5[] =
1149 {0x90, /* nop */
1150 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1151 static const unsigned char f32_6[] =
1152 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1153 static const unsigned char f32_7[] =
1154 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1155 static const unsigned char f32_8[] =
1156 {0x90, /* nop */
1157 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1158 static const unsigned char f32_9[] =
1159 {0x89,0xf6, /* movl %esi,%esi */
1160 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1161 static const unsigned char f32_10[] =
1162 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1163 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1164 static const unsigned char f32_11[] =
1165 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1166 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1167 static const unsigned char f32_12[] =
1168 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1169 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1170 static const unsigned char f32_13[] =
1171 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1172 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1173 static const unsigned char f32_14[] =
1174 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1175 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1176 static const unsigned char f16_3[] =
1177 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1178 static const unsigned char f16_4[] =
1179 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1180 static const unsigned char f16_5[] =
1181 {0x90, /* nop */
1182 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1183 static const unsigned char f16_6[] =
1184 {0x89,0xf6, /* mov %si,%si */
1185 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1186 static const unsigned char f16_7[] =
1187 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1188 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1189 static const unsigned char f16_8[] =
1190 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1191 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1192 static const unsigned char jump_31[] =
1193 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1194 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1195 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1196 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1197 static const unsigned char *const f32_patt[] = {
1198 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
1199 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
1200 };
1201 static const unsigned char *const f16_patt[] = {
1202 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
1203 };
1204 /* nopl (%[re]ax) */
1205 static const unsigned char alt_3[] =
1206 {0x0f,0x1f,0x00};
1207 /* nopl 0(%[re]ax) */
1208 static const unsigned char alt_4[] =
1209 {0x0f,0x1f,0x40,0x00};
1210 /* nopl 0(%[re]ax,%[re]ax,1) */
1211 static const unsigned char alt_5[] =
1212 {0x0f,0x1f,0x44,0x00,0x00};
1213 /* nopw 0(%[re]ax,%[re]ax,1) */
1214 static const unsigned char alt_6[] =
1215 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1216 /* nopl 0L(%[re]ax) */
1217 static const unsigned char alt_7[] =
1218 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1219 /* nopl 0L(%[re]ax,%[re]ax,1) */
1220 static const unsigned char alt_8[] =
1221 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1222 /* nopw 0L(%[re]ax,%[re]ax,1) */
1223 static const unsigned char alt_9[] =
1224 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1225 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1226 static const unsigned char alt_10[] =
1227 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1228 static const unsigned char *const alt_patt[] = {
1229 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1230 alt_9, alt_10
1231 };
1232
1233 /* Only align for at least a positive non-zero boundary. */
1234 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
1235 return;
1236
1237 /* We need to decide which NOP sequence to use for 32bit and
1238 64bit. When -mtune= is used:
1239
1240 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1241 PROCESSOR_GENERIC32, f32_patt will be used.
1242 2. For the rest, alt_patt will be used.
1243
1244 When -mtune= isn't used, alt_patt will be used if
1245 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1246 be used.
1247
1248 When -march= or .arch is used, we can't use anything beyond
1249 cpu_arch_isa_flags. */
1250
1251 if (flag_code == CODE_16BIT)
1252 {
1253 if (count > 8)
1254 {
1255 memcpy (fragP->fr_literal + fragP->fr_fix,
1256 jump_31, count);
1257 /* Adjust jump offset. */
1258 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1259 }
1260 else
1261 memcpy (fragP->fr_literal + fragP->fr_fix,
1262 f16_patt[count - 1], count);
1263 }
1264 else
1265 {
1266 const unsigned char *const *patt = NULL;
1267
1268 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1269 {
1270 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1271 switch (cpu_arch_tune)
1272 {
1273 case PROCESSOR_UNKNOWN:
1274 /* We use cpu_arch_isa_flags to check if we SHOULD
1275 optimize with nops. */
1276 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1277 patt = alt_patt;
1278 else
1279 patt = f32_patt;
1280 break;
1281 case PROCESSOR_PENTIUM4:
1282 case PROCESSOR_NOCONA:
1283 case PROCESSOR_CORE:
1284 case PROCESSOR_CORE2:
1285 case PROCESSOR_COREI7:
1286 case PROCESSOR_L1OM:
1287 case PROCESSOR_K1OM:
1288 case PROCESSOR_GENERIC64:
1289 case PROCESSOR_K6:
1290 case PROCESSOR_ATHLON:
1291 case PROCESSOR_K8:
1292 case PROCESSOR_AMDFAM10:
1293 case PROCESSOR_BD:
1294 case PROCESSOR_ZNVER:
1295 case PROCESSOR_BT:
1296 patt = alt_patt;
1297 break;
1298 case PROCESSOR_I386:
1299 case PROCESSOR_I486:
1300 case PROCESSOR_PENTIUM:
1301 case PROCESSOR_PENTIUMPRO:
1302 case PROCESSOR_IAMCU:
1303 case PROCESSOR_GENERIC32:
1304 patt = f32_patt;
1305 break;
1306 }
1307 }
1308 else
1309 {
1310 switch (fragP->tc_frag_data.tune)
1311 {
1312 case PROCESSOR_UNKNOWN:
1313 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1314 PROCESSOR_UNKNOWN. */
1315 abort ();
1316 break;
1317
1318 case PROCESSOR_I386:
1319 case PROCESSOR_I486:
1320 case PROCESSOR_PENTIUM:
1321 case PROCESSOR_IAMCU:
1322 case PROCESSOR_K6:
1323 case PROCESSOR_ATHLON:
1324 case PROCESSOR_K8:
1325 case PROCESSOR_AMDFAM10:
1326 case PROCESSOR_BD:
1327 case PROCESSOR_ZNVER:
1328 case PROCESSOR_BT:
1329 case PROCESSOR_GENERIC32:
1330 /* We use cpu_arch_isa_flags to check if we CAN optimize
1331 with nops. */
1332 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1333 patt = alt_patt;
1334 else
1335 patt = f32_patt;
1336 break;
1337 case PROCESSOR_PENTIUMPRO:
1338 case PROCESSOR_PENTIUM4:
1339 case PROCESSOR_NOCONA:
1340 case PROCESSOR_CORE:
1341 case PROCESSOR_CORE2:
1342 case PROCESSOR_COREI7:
1343 case PROCESSOR_L1OM:
1344 case PROCESSOR_K1OM:
1345 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1346 patt = alt_patt;
1347 else
1348 patt = f32_patt;
1349 break;
1350 case PROCESSOR_GENERIC64:
1351 patt = alt_patt;
1352 break;
1353 }
1354 }
1355
1356 if (patt == f32_patt)
1357 {
1358 /* If the padding is less than 15 bytes, we use the normal
1359 ones. Otherwise, we use a jump instruction and adjust
1360 its offset. */
1361 int limit;
1362
1363 /* For 64bit, the limit is 3 bytes. */
1364 if (flag_code == CODE_64BIT
1365 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1366 limit = 3;
1367 else
1368 limit = 15;
1369 if (count < limit)
1370 memcpy (fragP->fr_literal + fragP->fr_fix,
1371 patt[count - 1], count);
1372 else
1373 {
1374 memcpy (fragP->fr_literal + fragP->fr_fix,
1375 jump_31, count);
1376 /* Adjust jump offset. */
1377 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1378 }
1379 }
1380 else
1381 {
1382 /* Maximum length of an instruction is 10 byte. If the
1383 padding is greater than 10 bytes and we don't use jump,
1384 we have to break it into smaller pieces. */
1385 int padding = count;
1386 while (padding > 10)
1387 {
1388 padding -= 10;
1389 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1390 patt [9], 10);
1391 }
1392
1393 if (padding)
1394 memcpy (fragP->fr_literal + fragP->fr_fix,
1395 patt [padding - 1], padding);
1396 }
1397 }
1398 fragP->fr_var = count;
1399 }
1400
1401 static INLINE int
1402 operand_type_all_zero (const union i386_operand_type *x)
1403 {
1404 switch (ARRAY_SIZE(x->array))
1405 {
1406 case 3:
1407 if (x->array[2])
1408 return 0;
1409 /* Fall through. */
1410 case 2:
1411 if (x->array[1])
1412 return 0;
1413 /* Fall through. */
1414 case 1:
1415 return !x->array[0];
1416 default:
1417 abort ();
1418 }
1419 }
1420
1421 static INLINE void
1422 operand_type_set (union i386_operand_type *x, unsigned int v)
1423 {
1424 switch (ARRAY_SIZE(x->array))
1425 {
1426 case 3:
1427 x->array[2] = v;
1428 /* Fall through. */
1429 case 2:
1430 x->array[1] = v;
1431 /* Fall through. */
1432 case 1:
1433 x->array[0] = v;
1434 /* Fall through. */
1435 break;
1436 default:
1437 abort ();
1438 }
1439 }
1440
1441 static INLINE int
1442 operand_type_equal (const union i386_operand_type *x,
1443 const union i386_operand_type *y)
1444 {
1445 switch (ARRAY_SIZE(x->array))
1446 {
1447 case 3:
1448 if (x->array[2] != y->array[2])
1449 return 0;
1450 /* Fall through. */
1451 case 2:
1452 if (x->array[1] != y->array[1])
1453 return 0;
1454 /* Fall through. */
1455 case 1:
1456 return x->array[0] == y->array[0];
1457 break;
1458 default:
1459 abort ();
1460 }
1461 }
1462
1463 static INLINE int
1464 cpu_flags_all_zero (const union i386_cpu_flags *x)
1465 {
1466 switch (ARRAY_SIZE(x->array))
1467 {
1468 case 4:
1469 if (x->array[3])
1470 return 0;
1471 /* Fall through. */
1472 case 3:
1473 if (x->array[2])
1474 return 0;
1475 /* Fall through. */
1476 case 2:
1477 if (x->array[1])
1478 return 0;
1479 /* Fall through. */
1480 case 1:
1481 return !x->array[0];
1482 default:
1483 abort ();
1484 }
1485 }
1486
1487 static INLINE int
1488 cpu_flags_equal (const union i386_cpu_flags *x,
1489 const union i386_cpu_flags *y)
1490 {
1491 switch (ARRAY_SIZE(x->array))
1492 {
1493 case 4:
1494 if (x->array[3] != y->array[3])
1495 return 0;
1496 /* Fall through. */
1497 case 3:
1498 if (x->array[2] != y->array[2])
1499 return 0;
1500 /* Fall through. */
1501 case 2:
1502 if (x->array[1] != y->array[1])
1503 return 0;
1504 /* Fall through. */
1505 case 1:
1506 return x->array[0] == y->array[0];
1507 break;
1508 default:
1509 abort ();
1510 }
1511 }
1512
1513 static INLINE int
1514 cpu_flags_check_cpu64 (i386_cpu_flags f)
1515 {
1516 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1517 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1518 }
1519
1520 static INLINE i386_cpu_flags
1521 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1522 {
1523 switch (ARRAY_SIZE (x.array))
1524 {
1525 case 4:
1526 x.array [3] &= y.array [3];
1527 /* Fall through. */
1528 case 3:
1529 x.array [2] &= y.array [2];
1530 /* Fall through. */
1531 case 2:
1532 x.array [1] &= y.array [1];
1533 /* Fall through. */
1534 case 1:
1535 x.array [0] &= y.array [0];
1536 break;
1537 default:
1538 abort ();
1539 }
1540 return x;
1541 }
1542
1543 static INLINE i386_cpu_flags
1544 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1545 {
1546 switch (ARRAY_SIZE (x.array))
1547 {
1548 case 4:
1549 x.array [3] |= y.array [3];
1550 /* Fall through. */
1551 case 3:
1552 x.array [2] |= y.array [2];
1553 /* Fall through. */
1554 case 2:
1555 x.array [1] |= y.array [1];
1556 /* Fall through. */
1557 case 1:
1558 x.array [0] |= y.array [0];
1559 break;
1560 default:
1561 abort ();
1562 }
1563 return x;
1564 }
1565
1566 static INLINE i386_cpu_flags
1567 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1568 {
1569 switch (ARRAY_SIZE (x.array))
1570 {
1571 case 4:
1572 x.array [3] &= ~y.array [3];
1573 /* Fall through. */
1574 case 3:
1575 x.array [2] &= ~y.array [2];
1576 /* Fall through. */
1577 case 2:
1578 x.array [1] &= ~y.array [1];
1579 /* Fall through. */
1580 case 1:
1581 x.array [0] &= ~y.array [0];
1582 break;
1583 default:
1584 abort ();
1585 }
1586 return x;
1587 }
1588
1589 #define CPU_FLAGS_ARCH_MATCH 0x1
1590 #define CPU_FLAGS_64BIT_MATCH 0x2
1591 #define CPU_FLAGS_AES_MATCH 0x4
1592 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1593 #define CPU_FLAGS_AVX_MATCH 0x10
1594
1595 #define CPU_FLAGS_32BIT_MATCH \
1596 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1597 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1598 #define CPU_FLAGS_PERFECT_MATCH \
1599 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1600
1601 /* Return CPU flags match bits. */
1602
1603 static int
1604 cpu_flags_match (const insn_template *t)
1605 {
1606 i386_cpu_flags x = t->cpu_flags;
1607 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1608
1609 x.bitfield.cpu64 = 0;
1610 x.bitfield.cpuno64 = 0;
1611
1612 if (cpu_flags_all_zero (&x))
1613 {
1614 /* This instruction is available on all archs. */
1615 match |= CPU_FLAGS_32BIT_MATCH;
1616 }
1617 else
1618 {
1619 /* This instruction is available only on some archs. */
1620 i386_cpu_flags cpu = cpu_arch_flags;
1621
1622 cpu = cpu_flags_and (x, cpu);
1623 if (!cpu_flags_all_zero (&cpu))
1624 {
1625 if (x.bitfield.cpuavx)
1626 {
1627 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1628 if (cpu.bitfield.cpuavx)
1629 {
1630 /* Check SSE2AVX. */
1631 if (!t->opcode_modifier.sse2avx|| sse2avx)
1632 {
1633 match |= (CPU_FLAGS_ARCH_MATCH
1634 | CPU_FLAGS_AVX_MATCH);
1635 /* Check AES. */
1636 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1637 match |= CPU_FLAGS_AES_MATCH;
1638 /* Check PCLMUL. */
1639 if (!x.bitfield.cpupclmul
1640 || cpu.bitfield.cpupclmul)
1641 match |= CPU_FLAGS_PCLMUL_MATCH;
1642 }
1643 }
1644 else
1645 match |= CPU_FLAGS_ARCH_MATCH;
1646 }
1647 else if (x.bitfield.cpuavx512vl)
1648 {
1649 /* Match AVX512VL. */
1650 if (cpu.bitfield.cpuavx512vl)
1651 {
1652 /* Need another match. */
1653 cpu.bitfield.cpuavx512vl = 0;
1654 if (!cpu_flags_all_zero (&cpu))
1655 match |= CPU_FLAGS_32BIT_MATCH;
1656 else
1657 match |= CPU_FLAGS_ARCH_MATCH;
1658 }
1659 else
1660 match |= CPU_FLAGS_ARCH_MATCH;
1661 }
1662 else
1663 match |= CPU_FLAGS_32BIT_MATCH;
1664 }
1665 }
1666 return match;
1667 }
1668
1669 static INLINE i386_operand_type
1670 operand_type_and (i386_operand_type x, i386_operand_type y)
1671 {
1672 switch (ARRAY_SIZE (x.array))
1673 {
1674 case 3:
1675 x.array [2] &= y.array [2];
1676 /* Fall through. */
1677 case 2:
1678 x.array [1] &= y.array [1];
1679 /* Fall through. */
1680 case 1:
1681 x.array [0] &= y.array [0];
1682 break;
1683 default:
1684 abort ();
1685 }
1686 return x;
1687 }
1688
1689 static INLINE i386_operand_type
1690 operand_type_or (i386_operand_type x, i386_operand_type y)
1691 {
1692 switch (ARRAY_SIZE (x.array))
1693 {
1694 case 3:
1695 x.array [2] |= y.array [2];
1696 /* Fall through. */
1697 case 2:
1698 x.array [1] |= y.array [1];
1699 /* Fall through. */
1700 case 1:
1701 x.array [0] |= y.array [0];
1702 break;
1703 default:
1704 abort ();
1705 }
1706 return x;
1707 }
1708
1709 static INLINE i386_operand_type
1710 operand_type_xor (i386_operand_type x, i386_operand_type y)
1711 {
1712 switch (ARRAY_SIZE (x.array))
1713 {
1714 case 3:
1715 x.array [2] ^= y.array [2];
1716 /* Fall through. */
1717 case 2:
1718 x.array [1] ^= y.array [1];
1719 /* Fall through. */
1720 case 1:
1721 x.array [0] ^= y.array [0];
1722 break;
1723 default:
1724 abort ();
1725 }
1726 return x;
1727 }
1728
1729 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1730 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1731 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1732 static const i386_operand_type inoutportreg
1733 = OPERAND_TYPE_INOUTPORTREG;
1734 static const i386_operand_type reg16_inoutportreg
1735 = OPERAND_TYPE_REG16_INOUTPORTREG;
1736 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1737 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1738 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1739 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1740 static const i386_operand_type anydisp
1741 = OPERAND_TYPE_ANYDISP;
1742 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1743 static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
1744 static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1745 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1746 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1747 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1748 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1749 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1750 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1751 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1752 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1753 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1754 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1755 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1756
1757 enum operand_type
1758 {
1759 reg,
1760 imm,
1761 disp,
1762 anymem
1763 };
1764
1765 static INLINE int
1766 operand_type_check (i386_operand_type t, enum operand_type c)
1767 {
1768 switch (c)
1769 {
1770 case reg:
1771 return (t.bitfield.reg8
1772 || t.bitfield.reg16
1773 || t.bitfield.reg32
1774 || t.bitfield.reg64);
1775
1776 case imm:
1777 return (t.bitfield.imm8
1778 || t.bitfield.imm8s
1779 || t.bitfield.imm16
1780 || t.bitfield.imm32
1781 || t.bitfield.imm32s
1782 || t.bitfield.imm64);
1783
1784 case disp:
1785 return (t.bitfield.disp8
1786 || t.bitfield.disp16
1787 || t.bitfield.disp32
1788 || t.bitfield.disp32s
1789 || t.bitfield.disp64);
1790
1791 case anymem:
1792 return (t.bitfield.disp8
1793 || t.bitfield.disp16
1794 || t.bitfield.disp32
1795 || t.bitfield.disp32s
1796 || t.bitfield.disp64
1797 || t.bitfield.baseindex);
1798
1799 default:
1800 abort ();
1801 }
1802
1803 return 0;
1804 }
1805
1806 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1807 operand J for instruction template T. */
1808
1809 static INLINE int
1810 match_reg_size (const insn_template *t, unsigned int j)
1811 {
1812 return !((i.types[j].bitfield.byte
1813 && !t->operand_types[j].bitfield.byte)
1814 || (i.types[j].bitfield.word
1815 && !t->operand_types[j].bitfield.word)
1816 || (i.types[j].bitfield.dword
1817 && !t->operand_types[j].bitfield.dword)
1818 || (i.types[j].bitfield.qword
1819 && !t->operand_types[j].bitfield.qword));
1820 }
1821
1822 /* Return 1 if there is no conflict in any size on operand J for
1823 instruction template T. */
1824
1825 static INLINE int
1826 match_mem_size (const insn_template *t, unsigned int j)
1827 {
1828 return (match_reg_size (t, j)
1829 && !((i.types[j].bitfield.unspecified
1830 && !i.broadcast
1831 && !t->operand_types[j].bitfield.unspecified)
1832 || (i.types[j].bitfield.fword
1833 && !t->operand_types[j].bitfield.fword)
1834 || (i.types[j].bitfield.tbyte
1835 && !t->operand_types[j].bitfield.tbyte)
1836 || (i.types[j].bitfield.xmmword
1837 && !t->operand_types[j].bitfield.xmmword)
1838 || (i.types[j].bitfield.ymmword
1839 && !t->operand_types[j].bitfield.ymmword)
1840 || (i.types[j].bitfield.zmmword
1841 && !t->operand_types[j].bitfield.zmmword)));
1842 }
1843
1844 /* Return 1 if there is no size conflict on any operands for
1845 instruction template T. */
1846
1847 static INLINE int
1848 operand_size_match (const insn_template *t)
1849 {
1850 unsigned int j;
1851 int match = 1;
1852
1853 /* Don't check jump instructions. */
1854 if (t->opcode_modifier.jump
1855 || t->opcode_modifier.jumpbyte
1856 || t->opcode_modifier.jumpdword
1857 || t->opcode_modifier.jumpintersegment)
1858 return match;
1859
1860 /* Check memory and accumulator operand size. */
1861 for (j = 0; j < i.operands; j++)
1862 {
1863 if (t->operand_types[j].bitfield.anysize)
1864 continue;
1865
1866 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1867 {
1868 match = 0;
1869 break;
1870 }
1871
1872 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1873 {
1874 match = 0;
1875 break;
1876 }
1877 }
1878
1879 if (match)
1880 return match;
1881 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1882 {
1883 mismatch:
1884 i.error = operand_size_mismatch;
1885 return 0;
1886 }
1887
1888 /* Check reverse. */
1889 gas_assert (i.operands == 2);
1890
1891 match = 1;
1892 for (j = 0; j < 2; j++)
1893 {
1894 if (t->operand_types[j].bitfield.acc
1895 && !match_reg_size (t, j ? 0 : 1))
1896 goto mismatch;
1897
1898 if (i.types[j].bitfield.mem
1899 && !match_mem_size (t, j ? 0 : 1))
1900 goto mismatch;
1901 }
1902
1903 return match;
1904 }
1905
1906 static INLINE int
1907 operand_type_match (i386_operand_type overlap,
1908 i386_operand_type given)
1909 {
1910 i386_operand_type temp = overlap;
1911
1912 temp.bitfield.jumpabsolute = 0;
1913 temp.bitfield.unspecified = 0;
1914 temp.bitfield.byte = 0;
1915 temp.bitfield.word = 0;
1916 temp.bitfield.dword = 0;
1917 temp.bitfield.fword = 0;
1918 temp.bitfield.qword = 0;
1919 temp.bitfield.tbyte = 0;
1920 temp.bitfield.xmmword = 0;
1921 temp.bitfield.ymmword = 0;
1922 temp.bitfield.zmmword = 0;
1923 if (operand_type_all_zero (&temp))
1924 goto mismatch;
1925
1926 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1927 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1928 return 1;
1929
1930 mismatch:
1931 i.error = operand_type_mismatch;
1932 return 0;
1933 }
1934
1935 /* If given types g0 and g1 are registers they must be of the same type
1936 unless the expected operand type register overlap is null.
1937 Note that Acc in a template matches every size of reg. */
1938
1939 static INLINE int
1940 operand_type_register_match (i386_operand_type m0,
1941 i386_operand_type g0,
1942 i386_operand_type t0,
1943 i386_operand_type m1,
1944 i386_operand_type g1,
1945 i386_operand_type t1)
1946 {
1947 if (!operand_type_check (g0, reg))
1948 return 1;
1949
1950 if (!operand_type_check (g1, reg))
1951 return 1;
1952
1953 if (g0.bitfield.reg8 == g1.bitfield.reg8
1954 && g0.bitfield.reg16 == g1.bitfield.reg16
1955 && g0.bitfield.reg32 == g1.bitfield.reg32
1956 && g0.bitfield.reg64 == g1.bitfield.reg64)
1957 return 1;
1958
1959 if (m0.bitfield.acc)
1960 {
1961 t0.bitfield.reg8 = 1;
1962 t0.bitfield.reg16 = 1;
1963 t0.bitfield.reg32 = 1;
1964 t0.bitfield.reg64 = 1;
1965 }
1966
1967 if (m1.bitfield.acc)
1968 {
1969 t1.bitfield.reg8 = 1;
1970 t1.bitfield.reg16 = 1;
1971 t1.bitfield.reg32 = 1;
1972 t1.bitfield.reg64 = 1;
1973 }
1974
1975 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1976 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1977 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1978 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1979 return 1;
1980
1981 i.error = register_type_mismatch;
1982
1983 return 0;
1984 }
1985
1986 static INLINE unsigned int
1987 register_number (const reg_entry *r)
1988 {
1989 unsigned int nr = r->reg_num;
1990
1991 if (r->reg_flags & RegRex)
1992 nr += 8;
1993
1994 if (r->reg_flags & RegVRex)
1995 nr += 16;
1996
1997 return nr;
1998 }
1999
2000 static INLINE unsigned int
2001 mode_from_disp_size (i386_operand_type t)
2002 {
2003 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
2004 return 1;
2005 else if (t.bitfield.disp16
2006 || t.bitfield.disp32
2007 || t.bitfield.disp32s)
2008 return 2;
2009 else
2010 return 0;
2011 }
2012
2013 static INLINE int
2014 fits_in_signed_byte (addressT num)
2015 {
2016 return num + 0x80 <= 0xff;
2017 }
2018
2019 static INLINE int
2020 fits_in_unsigned_byte (addressT num)
2021 {
2022 return num <= 0xff;
2023 }
2024
2025 static INLINE int
2026 fits_in_unsigned_word (addressT num)
2027 {
2028 return num <= 0xffff;
2029 }
2030
2031 static INLINE int
2032 fits_in_signed_word (addressT num)
2033 {
2034 return num + 0x8000 <= 0xffff;
2035 }
2036
2037 static INLINE int
2038 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2039 {
2040 #ifndef BFD64
2041 return 1;
2042 #else
2043 return num + 0x80000000 <= 0xffffffff;
2044 #endif
2045 } /* fits_in_signed_long() */
2046
2047 static INLINE int
2048 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2049 {
2050 #ifndef BFD64
2051 return 1;
2052 #else
2053 return num <= 0xffffffff;
2054 #endif
2055 } /* fits_in_unsigned_long() */
2056
2057 static INLINE int
2058 fits_in_vec_disp8 (offsetT num)
2059 {
2060 int shift = i.memshift;
2061 unsigned int mask;
2062
2063 if (shift == -1)
2064 abort ();
2065
2066 mask = (1 << shift) - 1;
2067
2068 /* Return 0 if NUM isn't properly aligned. */
2069 if ((num & mask))
2070 return 0;
2071
2072 /* Check if NUM will fit in 8bit after shift. */
2073 return fits_in_signed_byte (num >> shift);
2074 }
2075
2076 static INLINE int
2077 fits_in_imm4 (offsetT num)
2078 {
2079 return (num & 0xf) == num;
2080 }
2081
2082 static i386_operand_type
2083 smallest_imm_type (offsetT num)
2084 {
2085 i386_operand_type t;
2086
2087 operand_type_set (&t, 0);
2088 t.bitfield.imm64 = 1;
2089
2090 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2091 {
2092 /* This code is disabled on the 486 because all the Imm1 forms
2093 in the opcode table are slower on the i486. They're the
2094 versions with the implicitly specified single-position
2095 displacement, which has another syntax if you really want to
2096 use that form. */
2097 t.bitfield.imm1 = 1;
2098 t.bitfield.imm8 = 1;
2099 t.bitfield.imm8s = 1;
2100 t.bitfield.imm16 = 1;
2101 t.bitfield.imm32 = 1;
2102 t.bitfield.imm32s = 1;
2103 }
2104 else if (fits_in_signed_byte (num))
2105 {
2106 t.bitfield.imm8 = 1;
2107 t.bitfield.imm8s = 1;
2108 t.bitfield.imm16 = 1;
2109 t.bitfield.imm32 = 1;
2110 t.bitfield.imm32s = 1;
2111 }
2112 else if (fits_in_unsigned_byte (num))
2113 {
2114 t.bitfield.imm8 = 1;
2115 t.bitfield.imm16 = 1;
2116 t.bitfield.imm32 = 1;
2117 t.bitfield.imm32s = 1;
2118 }
2119 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2120 {
2121 t.bitfield.imm16 = 1;
2122 t.bitfield.imm32 = 1;
2123 t.bitfield.imm32s = 1;
2124 }
2125 else if (fits_in_signed_long (num))
2126 {
2127 t.bitfield.imm32 = 1;
2128 t.bitfield.imm32s = 1;
2129 }
2130 else if (fits_in_unsigned_long (num))
2131 t.bitfield.imm32 = 1;
2132
2133 return t;
2134 }
2135
2136 static offsetT
2137 offset_in_range (offsetT val, int size)
2138 {
2139 addressT mask;
2140
2141 switch (size)
2142 {
2143 case 1: mask = ((addressT) 1 << 8) - 1; break;
2144 case 2: mask = ((addressT) 1 << 16) - 1; break;
2145 case 4: mask = ((addressT) 2 << 31) - 1; break;
2146 #ifdef BFD64
2147 case 8: mask = ((addressT) 2 << 63) - 1; break;
2148 #endif
2149 default: abort ();
2150 }
2151
2152 #ifdef BFD64
2153 /* If BFD64, sign extend val for 32bit address mode. */
2154 if (flag_code != CODE_64BIT
2155 || i.prefix[ADDR_PREFIX])
2156 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2157 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2158 #endif
2159
2160 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2161 {
2162 char buf1[40], buf2[40];
2163
2164 sprint_value (buf1, val);
2165 sprint_value (buf2, val & mask);
2166 as_warn (_("%s shortened to %s"), buf1, buf2);
2167 }
2168 return val & mask;
2169 }
2170
2171 enum PREFIX_GROUP
2172 {
2173 PREFIX_EXIST = 0,
2174 PREFIX_LOCK,
2175 PREFIX_REP,
2176 PREFIX_DS,
2177 PREFIX_OTHER
2178 };
2179
2180 /* Returns
2181 a. PREFIX_EXIST if attempting to add a prefix where one from the
2182 same class already exists.
2183 b. PREFIX_LOCK if lock prefix is added.
2184 c. PREFIX_REP if rep/repne prefix is added.
2185 d. PREFIX_DS if ds prefix is added.
2186 e. PREFIX_OTHER if other prefix is added.
2187 */
2188
2189 static enum PREFIX_GROUP
2190 add_prefix (unsigned int prefix)
2191 {
2192 enum PREFIX_GROUP ret = PREFIX_OTHER;
2193 unsigned int q;
2194
2195 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2196 && flag_code == CODE_64BIT)
2197 {
2198 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2199 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2200 && (prefix & (REX_R | REX_X | REX_B))))
2201 ret = PREFIX_EXIST;
2202 q = REX_PREFIX;
2203 }
2204 else
2205 {
2206 switch (prefix)
2207 {
2208 default:
2209 abort ();
2210
2211 case DS_PREFIX_OPCODE:
2212 ret = PREFIX_DS;
2213 /* Fall through. */
2214 case CS_PREFIX_OPCODE:
2215 case ES_PREFIX_OPCODE:
2216 case FS_PREFIX_OPCODE:
2217 case GS_PREFIX_OPCODE:
2218 case SS_PREFIX_OPCODE:
2219 q = SEG_PREFIX;
2220 break;
2221
2222 case REPNE_PREFIX_OPCODE:
2223 case REPE_PREFIX_OPCODE:
2224 q = REP_PREFIX;
2225 ret = PREFIX_REP;
2226 break;
2227
2228 case LOCK_PREFIX_OPCODE:
2229 q = LOCK_PREFIX;
2230 ret = PREFIX_LOCK;
2231 break;
2232
2233 case FWAIT_OPCODE:
2234 q = WAIT_PREFIX;
2235 break;
2236
2237 case ADDR_PREFIX_OPCODE:
2238 q = ADDR_PREFIX;
2239 break;
2240
2241 case DATA_PREFIX_OPCODE:
2242 q = DATA_PREFIX;
2243 break;
2244 }
2245 if (i.prefix[q] != 0)
2246 ret = PREFIX_EXIST;
2247 }
2248
2249 if (ret)
2250 {
2251 if (!i.prefix[q])
2252 ++i.prefixes;
2253 i.prefix[q] |= prefix;
2254 }
2255 else
2256 as_bad (_("same type of prefix used twice"));
2257
2258 return ret;
2259 }
2260
2261 static void
2262 update_code_flag (int value, int check)
2263 {
2264 PRINTF_LIKE ((*as_error));
2265
2266 flag_code = (enum flag_code) value;
2267 if (flag_code == CODE_64BIT)
2268 {
2269 cpu_arch_flags.bitfield.cpu64 = 1;
2270 cpu_arch_flags.bitfield.cpuno64 = 0;
2271 }
2272 else
2273 {
2274 cpu_arch_flags.bitfield.cpu64 = 0;
2275 cpu_arch_flags.bitfield.cpuno64 = 1;
2276 }
2277 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2278 {
2279 if (check)
2280 as_error = as_fatal;
2281 else
2282 as_error = as_bad;
2283 (*as_error) (_("64bit mode not supported on `%s'."),
2284 cpu_arch_name ? cpu_arch_name : default_arch);
2285 }
2286 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2287 {
2288 if (check)
2289 as_error = as_fatal;
2290 else
2291 as_error = as_bad;
2292 (*as_error) (_("32bit mode not supported on `%s'."),
2293 cpu_arch_name ? cpu_arch_name : default_arch);
2294 }
2295 stackop_size = '\0';
2296 }
2297
2298 static void
2299 set_code_flag (int value)
2300 {
2301 update_code_flag (value, 0);
2302 }
2303
2304 static void
2305 set_16bit_gcc_code_flag (int new_code_flag)
2306 {
2307 flag_code = (enum flag_code) new_code_flag;
2308 if (flag_code != CODE_16BIT)
2309 abort ();
2310 cpu_arch_flags.bitfield.cpu64 = 0;
2311 cpu_arch_flags.bitfield.cpuno64 = 1;
2312 stackop_size = LONG_MNEM_SUFFIX;
2313 }
2314
2315 static void
2316 set_intel_syntax (int syntax_flag)
2317 {
2318 /* Find out if register prefixing is specified. */
2319 int ask_naked_reg = 0;
2320
2321 SKIP_WHITESPACE ();
2322 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2323 {
2324 char *string;
2325 int e = get_symbol_name (&string);
2326
2327 if (strcmp (string, "prefix") == 0)
2328 ask_naked_reg = 1;
2329 else if (strcmp (string, "noprefix") == 0)
2330 ask_naked_reg = -1;
2331 else
2332 as_bad (_("bad argument to syntax directive."));
2333 (void) restore_line_pointer (e);
2334 }
2335 demand_empty_rest_of_line ();
2336
2337 intel_syntax = syntax_flag;
2338
2339 if (ask_naked_reg == 0)
2340 allow_naked_reg = (intel_syntax
2341 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2342 else
2343 allow_naked_reg = (ask_naked_reg < 0);
2344
2345 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2346
2347 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2348 identifier_chars['$'] = intel_syntax ? '$' : 0;
2349 register_prefix = allow_naked_reg ? "" : "%";
2350 }
2351
2352 static void
2353 set_intel_mnemonic (int mnemonic_flag)
2354 {
2355 intel_mnemonic = mnemonic_flag;
2356 }
2357
2358 static void
2359 set_allow_index_reg (int flag)
2360 {
2361 allow_index_reg = flag;
2362 }
2363
2364 static void
2365 set_check (int what)
2366 {
2367 enum check_kind *kind;
2368 const char *str;
2369
2370 if (what)
2371 {
2372 kind = &operand_check;
2373 str = "operand";
2374 }
2375 else
2376 {
2377 kind = &sse_check;
2378 str = "sse";
2379 }
2380
2381 SKIP_WHITESPACE ();
2382
2383 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2384 {
2385 char *string;
2386 int e = get_symbol_name (&string);
2387
2388 if (strcmp (string, "none") == 0)
2389 *kind = check_none;
2390 else if (strcmp (string, "warning") == 0)
2391 *kind = check_warning;
2392 else if (strcmp (string, "error") == 0)
2393 *kind = check_error;
2394 else
2395 as_bad (_("bad argument to %s_check directive."), str);
2396 (void) restore_line_pointer (e);
2397 }
2398 else
2399 as_bad (_("missing argument for %s_check directive"), str);
2400
2401 demand_empty_rest_of_line ();
2402 }
2403
2404 static void
2405 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2406 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2407 {
2408 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2409 static const char *arch;
2410
2411 /* Intel LIOM is only supported on ELF. */
2412 if (!IS_ELF)
2413 return;
2414
2415 if (!arch)
2416 {
2417 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2418 use default_arch. */
2419 arch = cpu_arch_name;
2420 if (!arch)
2421 arch = default_arch;
2422 }
2423
2424 /* If we are targeting Intel MCU, we must enable it. */
2425 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2426 || new_flag.bitfield.cpuiamcu)
2427 return;
2428
2429 /* If we are targeting Intel L1OM, we must enable it. */
2430 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2431 || new_flag.bitfield.cpul1om)
2432 return;
2433
2434 /* If we are targeting Intel K1OM, we must enable it. */
2435 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2436 || new_flag.bitfield.cpuk1om)
2437 return;
2438
2439 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2440 #endif
2441 }
2442
2443 static void
2444 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2445 {
2446 SKIP_WHITESPACE ();
2447
2448 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2449 {
2450 char *string;
2451 int e = get_symbol_name (&string);
2452 unsigned int j;
2453 i386_cpu_flags flags;
2454
2455 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2456 {
2457 if (strcmp (string, cpu_arch[j].name) == 0)
2458 {
2459 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2460
2461 if (*string != '.')
2462 {
2463 cpu_arch_name = cpu_arch[j].name;
2464 cpu_sub_arch_name = NULL;
2465 cpu_arch_flags = cpu_arch[j].flags;
2466 if (flag_code == CODE_64BIT)
2467 {
2468 cpu_arch_flags.bitfield.cpu64 = 1;
2469 cpu_arch_flags.bitfield.cpuno64 = 0;
2470 }
2471 else
2472 {
2473 cpu_arch_flags.bitfield.cpu64 = 0;
2474 cpu_arch_flags.bitfield.cpuno64 = 1;
2475 }
2476 cpu_arch_isa = cpu_arch[j].type;
2477 cpu_arch_isa_flags = cpu_arch[j].flags;
2478 if (!cpu_arch_tune_set)
2479 {
2480 cpu_arch_tune = cpu_arch_isa;
2481 cpu_arch_tune_flags = cpu_arch_isa_flags;
2482 }
2483 break;
2484 }
2485
2486 flags = cpu_flags_or (cpu_arch_flags,
2487 cpu_arch[j].flags);
2488
2489 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2490 {
2491 if (cpu_sub_arch_name)
2492 {
2493 char *name = cpu_sub_arch_name;
2494 cpu_sub_arch_name = concat (name,
2495 cpu_arch[j].name,
2496 (const char *) NULL);
2497 free (name);
2498 }
2499 else
2500 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2501 cpu_arch_flags = flags;
2502 cpu_arch_isa_flags = flags;
2503 }
2504 (void) restore_line_pointer (e);
2505 demand_empty_rest_of_line ();
2506 return;
2507 }
2508 }
2509
2510 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2511 {
2512 /* Disable an ISA extension. */
2513 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2514 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2515 {
2516 flags = cpu_flags_and_not (cpu_arch_flags,
2517 cpu_noarch[j].flags);
2518 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2519 {
2520 if (cpu_sub_arch_name)
2521 {
2522 char *name = cpu_sub_arch_name;
2523 cpu_sub_arch_name = concat (name, string,
2524 (const char *) NULL);
2525 free (name);
2526 }
2527 else
2528 cpu_sub_arch_name = xstrdup (string);
2529 cpu_arch_flags = flags;
2530 cpu_arch_isa_flags = flags;
2531 }
2532 (void) restore_line_pointer (e);
2533 demand_empty_rest_of_line ();
2534 return;
2535 }
2536
2537 j = ARRAY_SIZE (cpu_arch);
2538 }
2539
2540 if (j >= ARRAY_SIZE (cpu_arch))
2541 as_bad (_("no such architecture: `%s'"), string);
2542
2543 *input_line_pointer = e;
2544 }
2545 else
2546 as_bad (_("missing cpu architecture"));
2547
2548 no_cond_jump_promotion = 0;
2549 if (*input_line_pointer == ','
2550 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2551 {
2552 char *string;
2553 char e;
2554
2555 ++input_line_pointer;
2556 e = get_symbol_name (&string);
2557
2558 if (strcmp (string, "nojumps") == 0)
2559 no_cond_jump_promotion = 1;
2560 else if (strcmp (string, "jumps") == 0)
2561 ;
2562 else
2563 as_bad (_("no such architecture modifier: `%s'"), string);
2564
2565 (void) restore_line_pointer (e);
2566 }
2567
2568 demand_empty_rest_of_line ();
2569 }
2570
2571 enum bfd_architecture
2572 i386_arch (void)
2573 {
2574 if (cpu_arch_isa == PROCESSOR_L1OM)
2575 {
2576 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2577 || flag_code != CODE_64BIT)
2578 as_fatal (_("Intel L1OM is 64bit ELF only"));
2579 return bfd_arch_l1om;
2580 }
2581 else if (cpu_arch_isa == PROCESSOR_K1OM)
2582 {
2583 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2584 || flag_code != CODE_64BIT)
2585 as_fatal (_("Intel K1OM is 64bit ELF only"));
2586 return bfd_arch_k1om;
2587 }
2588 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2589 {
2590 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2591 || flag_code == CODE_64BIT)
2592 as_fatal (_("Intel MCU is 32bit ELF only"));
2593 return bfd_arch_iamcu;
2594 }
2595 else
2596 return bfd_arch_i386;
2597 }
2598
2599 unsigned long
2600 i386_mach (void)
2601 {
2602 if (!strncmp (default_arch, "x86_64", 6))
2603 {
2604 if (cpu_arch_isa == PROCESSOR_L1OM)
2605 {
2606 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2607 || default_arch[6] != '\0')
2608 as_fatal (_("Intel L1OM is 64bit ELF only"));
2609 return bfd_mach_l1om;
2610 }
2611 else if (cpu_arch_isa == PROCESSOR_K1OM)
2612 {
2613 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2614 || default_arch[6] != '\0')
2615 as_fatal (_("Intel K1OM is 64bit ELF only"));
2616 return bfd_mach_k1om;
2617 }
2618 else if (default_arch[6] == '\0')
2619 return bfd_mach_x86_64;
2620 else
2621 return bfd_mach_x64_32;
2622 }
2623 else if (!strcmp (default_arch, "i386")
2624 || !strcmp (default_arch, "iamcu"))
2625 {
2626 if (cpu_arch_isa == PROCESSOR_IAMCU)
2627 {
2628 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2629 as_fatal (_("Intel MCU is 32bit ELF only"));
2630 return bfd_mach_i386_iamcu;
2631 }
2632 else
2633 return bfd_mach_i386_i386;
2634 }
2635 else
2636 as_fatal (_("unknown architecture"));
2637 }
2638 \f
2639 void
2640 md_begin (void)
2641 {
2642 const char *hash_err;
2643
2644 /* Support pseudo prefixes like {disp32}. */
2645 lex_type ['{'] = LEX_BEGIN_NAME;
2646
2647 /* Initialize op_hash hash table. */
2648 op_hash = hash_new ();
2649
2650 {
2651 const insn_template *optab;
2652 templates *core_optab;
2653
2654 /* Setup for loop. */
2655 optab = i386_optab;
2656 core_optab = XNEW (templates);
2657 core_optab->start = optab;
2658
2659 while (1)
2660 {
2661 ++optab;
2662 if (optab->name == NULL
2663 || strcmp (optab->name, (optab - 1)->name) != 0)
2664 {
2665 /* different name --> ship out current template list;
2666 add to hash table; & begin anew. */
2667 core_optab->end = optab;
2668 hash_err = hash_insert (op_hash,
2669 (optab - 1)->name,
2670 (void *) core_optab);
2671 if (hash_err)
2672 {
2673 as_fatal (_("can't hash %s: %s"),
2674 (optab - 1)->name,
2675 hash_err);
2676 }
2677 if (optab->name == NULL)
2678 break;
2679 core_optab = XNEW (templates);
2680 core_optab->start = optab;
2681 }
2682 }
2683 }
2684
2685 /* Initialize reg_hash hash table. */
2686 reg_hash = hash_new ();
2687 {
2688 const reg_entry *regtab;
2689 unsigned int regtab_size = i386_regtab_size;
2690
2691 for (regtab = i386_regtab; regtab_size--; regtab++)
2692 {
2693 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2694 if (hash_err)
2695 as_fatal (_("can't hash %s: %s"),
2696 regtab->reg_name,
2697 hash_err);
2698 }
2699 }
2700
2701 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2702 {
2703 int c;
2704 char *p;
2705
2706 for (c = 0; c < 256; c++)
2707 {
2708 if (ISDIGIT (c))
2709 {
2710 digit_chars[c] = c;
2711 mnemonic_chars[c] = c;
2712 register_chars[c] = c;
2713 operand_chars[c] = c;
2714 }
2715 else if (ISLOWER (c))
2716 {
2717 mnemonic_chars[c] = c;
2718 register_chars[c] = c;
2719 operand_chars[c] = c;
2720 }
2721 else if (ISUPPER (c))
2722 {
2723 mnemonic_chars[c] = TOLOWER (c);
2724 register_chars[c] = mnemonic_chars[c];
2725 operand_chars[c] = c;
2726 }
2727 else if (c == '{' || c == '}')
2728 {
2729 mnemonic_chars[c] = c;
2730 operand_chars[c] = c;
2731 }
2732
2733 if (ISALPHA (c) || ISDIGIT (c))
2734 identifier_chars[c] = c;
2735 else if (c >= 128)
2736 {
2737 identifier_chars[c] = c;
2738 operand_chars[c] = c;
2739 }
2740 }
2741
2742 #ifdef LEX_AT
2743 identifier_chars['@'] = '@';
2744 #endif
2745 #ifdef LEX_QM
2746 identifier_chars['?'] = '?';
2747 operand_chars['?'] = '?';
2748 #endif
2749 digit_chars['-'] = '-';
2750 mnemonic_chars['_'] = '_';
2751 mnemonic_chars['-'] = '-';
2752 mnemonic_chars['.'] = '.';
2753 identifier_chars['_'] = '_';
2754 identifier_chars['.'] = '.';
2755
2756 for (p = operand_special_chars; *p != '\0'; p++)
2757 operand_chars[(unsigned char) *p] = *p;
2758 }
2759
2760 if (flag_code == CODE_64BIT)
2761 {
2762 #if defined (OBJ_COFF) && defined (TE_PE)
2763 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2764 ? 32 : 16);
2765 #else
2766 x86_dwarf2_return_column = 16;
2767 #endif
2768 x86_cie_data_alignment = -8;
2769 }
2770 else
2771 {
2772 x86_dwarf2_return_column = 8;
2773 x86_cie_data_alignment = -4;
2774 }
2775 }
2776
2777 void
2778 i386_print_statistics (FILE *file)
2779 {
2780 hash_print_statistics (file, "i386 opcode", op_hash);
2781 hash_print_statistics (file, "i386 register", reg_hash);
2782 }
2783 \f
2784 #ifdef DEBUG386
2785
2786 /* Debugging routines for md_assemble. */
2787 static void pte (insn_template *);
2788 static void pt (i386_operand_type);
2789 static void pe (expressionS *);
2790 static void ps (symbolS *);
2791
2792 static void
2793 pi (char *line, i386_insn *x)
2794 {
2795 unsigned int j;
2796
2797 fprintf (stdout, "%s: template ", line);
2798 pte (&x->tm);
2799 fprintf (stdout, " address: base %s index %s scale %x\n",
2800 x->base_reg ? x->base_reg->reg_name : "none",
2801 x->index_reg ? x->index_reg->reg_name : "none",
2802 x->log2_scale_factor);
2803 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2804 x->rm.mode, x->rm.reg, x->rm.regmem);
2805 fprintf (stdout, " sib: base %x index %x scale %x\n",
2806 x->sib.base, x->sib.index, x->sib.scale);
2807 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2808 (x->rex & REX_W) != 0,
2809 (x->rex & REX_R) != 0,
2810 (x->rex & REX_X) != 0,
2811 (x->rex & REX_B) != 0);
2812 for (j = 0; j < x->operands; j++)
2813 {
2814 fprintf (stdout, " #%d: ", j + 1);
2815 pt (x->types[j]);
2816 fprintf (stdout, "\n");
2817 if (x->types[j].bitfield.reg8
2818 || x->types[j].bitfield.reg16
2819 || x->types[j].bitfield.reg32
2820 || x->types[j].bitfield.reg64
2821 || x->types[j].bitfield.regmmx
2822 || x->types[j].bitfield.regxmm
2823 || x->types[j].bitfield.regymm
2824 || x->types[j].bitfield.regzmm
2825 || x->types[j].bitfield.sreg2
2826 || x->types[j].bitfield.sreg3
2827 || x->types[j].bitfield.control
2828 || x->types[j].bitfield.debug
2829 || x->types[j].bitfield.test)
2830 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2831 if (operand_type_check (x->types[j], imm))
2832 pe (x->op[j].imms);
2833 if (operand_type_check (x->types[j], disp))
2834 pe (x->op[j].disps);
2835 }
2836 }
2837
2838 static void
2839 pte (insn_template *t)
2840 {
2841 unsigned int j;
2842 fprintf (stdout, " %d operands ", t->operands);
2843 fprintf (stdout, "opcode %x ", t->base_opcode);
2844 if (t->extension_opcode != None)
2845 fprintf (stdout, "ext %x ", t->extension_opcode);
2846 if (t->opcode_modifier.d)
2847 fprintf (stdout, "D");
2848 if (t->opcode_modifier.w)
2849 fprintf (stdout, "W");
2850 fprintf (stdout, "\n");
2851 for (j = 0; j < t->operands; j++)
2852 {
2853 fprintf (stdout, " #%d type ", j + 1);
2854 pt (t->operand_types[j]);
2855 fprintf (stdout, "\n");
2856 }
2857 }
2858
2859 static void
2860 pe (expressionS *e)
2861 {
2862 fprintf (stdout, " operation %d\n", e->X_op);
2863 fprintf (stdout, " add_number %ld (%lx)\n",
2864 (long) e->X_add_number, (long) e->X_add_number);
2865 if (e->X_add_symbol)
2866 {
2867 fprintf (stdout, " add_symbol ");
2868 ps (e->X_add_symbol);
2869 fprintf (stdout, "\n");
2870 }
2871 if (e->X_op_symbol)
2872 {
2873 fprintf (stdout, " op_symbol ");
2874 ps (e->X_op_symbol);
2875 fprintf (stdout, "\n");
2876 }
2877 }
2878
2879 static void
2880 ps (symbolS *s)
2881 {
2882 fprintf (stdout, "%s type %s%s",
2883 S_GET_NAME (s),
2884 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2885 segment_name (S_GET_SEGMENT (s)));
2886 }
2887
2888 static struct type_name
2889 {
2890 i386_operand_type mask;
2891 const char *name;
2892 }
2893 const type_names[] =
2894 {
2895 { OPERAND_TYPE_REG8, "r8" },
2896 { OPERAND_TYPE_REG16, "r16" },
2897 { OPERAND_TYPE_REG32, "r32" },
2898 { OPERAND_TYPE_REG64, "r64" },
2899 { OPERAND_TYPE_IMM8, "i8" },
2900 { OPERAND_TYPE_IMM8, "i8s" },
2901 { OPERAND_TYPE_IMM16, "i16" },
2902 { OPERAND_TYPE_IMM32, "i32" },
2903 { OPERAND_TYPE_IMM32S, "i32s" },
2904 { OPERAND_TYPE_IMM64, "i64" },
2905 { OPERAND_TYPE_IMM1, "i1" },
2906 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2907 { OPERAND_TYPE_DISP8, "d8" },
2908 { OPERAND_TYPE_DISP16, "d16" },
2909 { OPERAND_TYPE_DISP32, "d32" },
2910 { OPERAND_TYPE_DISP32S, "d32s" },
2911 { OPERAND_TYPE_DISP64, "d64" },
2912 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
2913 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2914 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2915 { OPERAND_TYPE_CONTROL, "control reg" },
2916 { OPERAND_TYPE_TEST, "test reg" },
2917 { OPERAND_TYPE_DEBUG, "debug reg" },
2918 { OPERAND_TYPE_FLOATREG, "FReg" },
2919 { OPERAND_TYPE_FLOATACC, "FAcc" },
2920 { OPERAND_TYPE_SREG2, "SReg2" },
2921 { OPERAND_TYPE_SREG3, "SReg3" },
2922 { OPERAND_TYPE_ACC, "Acc" },
2923 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2924 { OPERAND_TYPE_REGMMX, "rMMX" },
2925 { OPERAND_TYPE_REGXMM, "rXMM" },
2926 { OPERAND_TYPE_REGYMM, "rYMM" },
2927 { OPERAND_TYPE_REGZMM, "rZMM" },
2928 { OPERAND_TYPE_REGMASK, "Mask reg" },
2929 { OPERAND_TYPE_ESSEG, "es" },
2930 };
2931
2932 static void
2933 pt (i386_operand_type t)
2934 {
2935 unsigned int j;
2936 i386_operand_type a;
2937
2938 for (j = 0; j < ARRAY_SIZE (type_names); j++)
2939 {
2940 a = operand_type_and (t, type_names[j].mask);
2941 if (!operand_type_all_zero (&a))
2942 fprintf (stdout, "%s, ", type_names[j].name);
2943 }
2944 fflush (stdout);
2945 }
2946
2947 #endif /* DEBUG386 */
2948 \f
2949 static bfd_reloc_code_real_type
2950 reloc (unsigned int size,
2951 int pcrel,
2952 int sign,
2953 bfd_reloc_code_real_type other)
2954 {
2955 if (other != NO_RELOC)
2956 {
2957 reloc_howto_type *rel;
2958
2959 if (size == 8)
2960 switch (other)
2961 {
2962 case BFD_RELOC_X86_64_GOT32:
2963 return BFD_RELOC_X86_64_GOT64;
2964 break;
2965 case BFD_RELOC_X86_64_GOTPLT64:
2966 return BFD_RELOC_X86_64_GOTPLT64;
2967 break;
2968 case BFD_RELOC_X86_64_PLTOFF64:
2969 return BFD_RELOC_X86_64_PLTOFF64;
2970 break;
2971 case BFD_RELOC_X86_64_GOTPC32:
2972 other = BFD_RELOC_X86_64_GOTPC64;
2973 break;
2974 case BFD_RELOC_X86_64_GOTPCREL:
2975 other = BFD_RELOC_X86_64_GOTPCREL64;
2976 break;
2977 case BFD_RELOC_X86_64_TPOFF32:
2978 other = BFD_RELOC_X86_64_TPOFF64;
2979 break;
2980 case BFD_RELOC_X86_64_DTPOFF32:
2981 other = BFD_RELOC_X86_64_DTPOFF64;
2982 break;
2983 default:
2984 break;
2985 }
2986
2987 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2988 if (other == BFD_RELOC_SIZE32)
2989 {
2990 if (size == 8)
2991 other = BFD_RELOC_SIZE64;
2992 if (pcrel)
2993 {
2994 as_bad (_("there are no pc-relative size relocations"));
2995 return NO_RELOC;
2996 }
2997 }
2998 #endif
2999
3000 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3001 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3002 sign = -1;
3003
3004 rel = bfd_reloc_type_lookup (stdoutput, other);
3005 if (!rel)
3006 as_bad (_("unknown relocation (%u)"), other);
3007 else if (size != bfd_get_reloc_size (rel))
3008 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3009 bfd_get_reloc_size (rel),
3010 size);
3011 else if (pcrel && !rel->pc_relative)
3012 as_bad (_("non-pc-relative relocation for pc-relative field"));
3013 else if ((rel->complain_on_overflow == complain_overflow_signed
3014 && !sign)
3015 || (rel->complain_on_overflow == complain_overflow_unsigned
3016 && sign > 0))
3017 as_bad (_("relocated field and relocation type differ in signedness"));
3018 else
3019 return other;
3020 return NO_RELOC;
3021 }
3022
3023 if (pcrel)
3024 {
3025 if (!sign)
3026 as_bad (_("there are no unsigned pc-relative relocations"));
3027 switch (size)
3028 {
3029 case 1: return BFD_RELOC_8_PCREL;
3030 case 2: return BFD_RELOC_16_PCREL;
3031 case 4: return BFD_RELOC_32_PCREL;
3032 case 8: return BFD_RELOC_64_PCREL;
3033 }
3034 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3035 }
3036 else
3037 {
3038 if (sign > 0)
3039 switch (size)
3040 {
3041 case 4: return BFD_RELOC_X86_64_32S;
3042 }
3043 else
3044 switch (size)
3045 {
3046 case 1: return BFD_RELOC_8;
3047 case 2: return BFD_RELOC_16;
3048 case 4: return BFD_RELOC_32;
3049 case 8: return BFD_RELOC_64;
3050 }
3051 as_bad (_("cannot do %s %u byte relocation"),
3052 sign > 0 ? "signed" : "unsigned", size);
3053 }
3054
3055 return NO_RELOC;
3056 }
3057
3058 /* Here we decide which fixups can be adjusted to make them relative to
3059 the beginning of the section instead of the symbol. Basically we need
3060 to make sure that the dynamic relocations are done correctly, so in
3061 some cases we force the original symbol to be used. */
3062
3063 int
3064 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3065 {
3066 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3067 if (!IS_ELF)
3068 return 1;
3069
3070 /* Don't adjust pc-relative references to merge sections in 64-bit
3071 mode. */
3072 if (use_rela_relocations
3073 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3074 && fixP->fx_pcrel)
3075 return 0;
3076
3077 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3078 and changed later by validate_fix. */
3079 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3080 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3081 return 0;
3082
3083 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3084 for size relocations. */
3085 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3086 || fixP->fx_r_type == BFD_RELOC_SIZE64
3087 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3088 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3089 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3090 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3091 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3092 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3093 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3094 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3095 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3096 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3097 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3098 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3099 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3100 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3101 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3102 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3103 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3104 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3105 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3106 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3107 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3108 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3109 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3110 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3111 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3112 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3113 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3114 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3115 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3116 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3117 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3118 return 0;
3119 #endif
3120 return 1;
3121 }
3122
3123 static int
3124 intel_float_operand (const char *mnemonic)
3125 {
3126 /* Note that the value returned is meaningful only for opcodes with (memory)
3127 operands, hence the code here is free to improperly handle opcodes that
3128 have no operands (for better performance and smaller code). */
3129
3130 if (mnemonic[0] != 'f')
3131 return 0; /* non-math */
3132
3133 switch (mnemonic[1])
3134 {
3135 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3136 the fs segment override prefix not currently handled because no
3137 call path can make opcodes without operands get here */
3138 case 'i':
3139 return 2 /* integer op */;
3140 case 'l':
3141 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3142 return 3; /* fldcw/fldenv */
3143 break;
3144 case 'n':
3145 if (mnemonic[2] != 'o' /* fnop */)
3146 return 3; /* non-waiting control op */
3147 break;
3148 case 'r':
3149 if (mnemonic[2] == 's')
3150 return 3; /* frstor/frstpm */
3151 break;
3152 case 's':
3153 if (mnemonic[2] == 'a')
3154 return 3; /* fsave */
3155 if (mnemonic[2] == 't')
3156 {
3157 switch (mnemonic[3])
3158 {
3159 case 'c': /* fstcw */
3160 case 'd': /* fstdw */
3161 case 'e': /* fstenv */
3162 case 's': /* fsts[gw] */
3163 return 3;
3164 }
3165 }
3166 break;
3167 case 'x':
3168 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3169 return 0; /* fxsave/fxrstor are not really math ops */
3170 break;
3171 }
3172
3173 return 1;
3174 }
3175
3176 /* Build the VEX prefix. */
3177
3178 static void
3179 build_vex_prefix (const insn_template *t)
3180 {
3181 unsigned int register_specifier;
3182 unsigned int implied_prefix;
3183 unsigned int vector_length;
3184
3185 /* Check register specifier. */
3186 if (i.vex.register_specifier)
3187 {
3188 register_specifier =
3189 ~register_number (i.vex.register_specifier) & 0xf;
3190 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3191 }
3192 else
3193 register_specifier = 0xf;
3194
3195 /* Use 2-byte VEX prefix by swapping destination and source
3196 operand. */
3197 if (i.vec_encoding != vex_encoding_vex3
3198 && i.dir_encoding == dir_encoding_default
3199 && i.operands == i.reg_operands
3200 && i.tm.opcode_modifier.vexopcode == VEX0F
3201 && i.tm.opcode_modifier.load
3202 && i.rex == REX_B)
3203 {
3204 unsigned int xchg = i.operands - 1;
3205 union i386_op temp_op;
3206 i386_operand_type temp_type;
3207
3208 temp_type = i.types[xchg];
3209 i.types[xchg] = i.types[0];
3210 i.types[0] = temp_type;
3211 temp_op = i.op[xchg];
3212 i.op[xchg] = i.op[0];
3213 i.op[0] = temp_op;
3214
3215 gas_assert (i.rm.mode == 3);
3216
3217 i.rex = REX_R;
3218 xchg = i.rm.regmem;
3219 i.rm.regmem = i.rm.reg;
3220 i.rm.reg = xchg;
3221
3222 /* Use the next insn. */
3223 i.tm = t[1];
3224 }
3225
3226 if (i.tm.opcode_modifier.vex == VEXScalar)
3227 vector_length = avxscalar;
3228 else
3229 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
3230
3231 switch ((i.tm.base_opcode >> 8) & 0xff)
3232 {
3233 case 0:
3234 implied_prefix = 0;
3235 break;
3236 case DATA_PREFIX_OPCODE:
3237 implied_prefix = 1;
3238 break;
3239 case REPE_PREFIX_OPCODE:
3240 implied_prefix = 2;
3241 break;
3242 case REPNE_PREFIX_OPCODE:
3243 implied_prefix = 3;
3244 break;
3245 default:
3246 abort ();
3247 }
3248
3249 /* Use 2-byte VEX prefix if possible. */
3250 if (i.vec_encoding != vex_encoding_vex3
3251 && i.tm.opcode_modifier.vexopcode == VEX0F
3252 && i.tm.opcode_modifier.vexw != VEXW1
3253 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3254 {
3255 /* 2-byte VEX prefix. */
3256 unsigned int r;
3257
3258 i.vex.length = 2;
3259 i.vex.bytes[0] = 0xc5;
3260
3261 /* Check the REX.R bit. */
3262 r = (i.rex & REX_R) ? 0 : 1;
3263 i.vex.bytes[1] = (r << 7
3264 | register_specifier << 3
3265 | vector_length << 2
3266 | implied_prefix);
3267 }
3268 else
3269 {
3270 /* 3-byte VEX prefix. */
3271 unsigned int m, w;
3272
3273 i.vex.length = 3;
3274
3275 switch (i.tm.opcode_modifier.vexopcode)
3276 {
3277 case VEX0F:
3278 m = 0x1;
3279 i.vex.bytes[0] = 0xc4;
3280 break;
3281 case VEX0F38:
3282 m = 0x2;
3283 i.vex.bytes[0] = 0xc4;
3284 break;
3285 case VEX0F3A:
3286 m = 0x3;
3287 i.vex.bytes[0] = 0xc4;
3288 break;
3289 case XOP08:
3290 m = 0x8;
3291 i.vex.bytes[0] = 0x8f;
3292 break;
3293 case XOP09:
3294 m = 0x9;
3295 i.vex.bytes[0] = 0x8f;
3296 break;
3297 case XOP0A:
3298 m = 0xa;
3299 i.vex.bytes[0] = 0x8f;
3300 break;
3301 default:
3302 abort ();
3303 }
3304
3305 /* The high 3 bits of the second VEX byte are 1's compliment
3306 of RXB bits from REX. */
3307 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3308
3309 /* Check the REX.W bit. */
3310 w = (i.rex & REX_W) ? 1 : 0;
3311 if (i.tm.opcode_modifier.vexw == VEXW1)
3312 w = 1;
3313
3314 i.vex.bytes[2] = (w << 7
3315 | register_specifier << 3
3316 | vector_length << 2
3317 | implied_prefix);
3318 }
3319 }
3320
3321 /* Build the EVEX prefix. */
3322
3323 static void
3324 build_evex_prefix (void)
3325 {
3326 unsigned int register_specifier;
3327 unsigned int implied_prefix;
3328 unsigned int m, w;
3329 rex_byte vrex_used = 0;
3330
3331 /* Check register specifier. */
3332 if (i.vex.register_specifier)
3333 {
3334 gas_assert ((i.vrex & REX_X) == 0);
3335
3336 register_specifier = i.vex.register_specifier->reg_num;
3337 if ((i.vex.register_specifier->reg_flags & RegRex))
3338 register_specifier += 8;
3339 /* The upper 16 registers are encoded in the fourth byte of the
3340 EVEX prefix. */
3341 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3342 i.vex.bytes[3] = 0x8;
3343 register_specifier = ~register_specifier & 0xf;
3344 }
3345 else
3346 {
3347 register_specifier = 0xf;
3348
3349 /* Encode upper 16 vector index register in the fourth byte of
3350 the EVEX prefix. */
3351 if (!(i.vrex & REX_X))
3352 i.vex.bytes[3] = 0x8;
3353 else
3354 vrex_used |= REX_X;
3355 }
3356
3357 switch ((i.tm.base_opcode >> 8) & 0xff)
3358 {
3359 case 0:
3360 implied_prefix = 0;
3361 break;
3362 case DATA_PREFIX_OPCODE:
3363 implied_prefix = 1;
3364 break;
3365 case REPE_PREFIX_OPCODE:
3366 implied_prefix = 2;
3367 break;
3368 case REPNE_PREFIX_OPCODE:
3369 implied_prefix = 3;
3370 break;
3371 default:
3372 abort ();
3373 }
3374
3375 /* 4 byte EVEX prefix. */
3376 i.vex.length = 4;
3377 i.vex.bytes[0] = 0x62;
3378
3379 /* mmmm bits. */
3380 switch (i.tm.opcode_modifier.vexopcode)
3381 {
3382 case VEX0F:
3383 m = 1;
3384 break;
3385 case VEX0F38:
3386 m = 2;
3387 break;
3388 case VEX0F3A:
3389 m = 3;
3390 break;
3391 default:
3392 abort ();
3393 break;
3394 }
3395
3396 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3397 bits from REX. */
3398 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3399
3400 /* The fifth bit of the second EVEX byte is 1's compliment of the
3401 REX_R bit in VREX. */
3402 if (!(i.vrex & REX_R))
3403 i.vex.bytes[1] |= 0x10;
3404 else
3405 vrex_used |= REX_R;
3406
3407 if ((i.reg_operands + i.imm_operands) == i.operands)
3408 {
3409 /* When all operands are registers, the REX_X bit in REX is not
3410 used. We reuse it to encode the upper 16 registers, which is
3411 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3412 as 1's compliment. */
3413 if ((i.vrex & REX_B))
3414 {
3415 vrex_used |= REX_B;
3416 i.vex.bytes[1] &= ~0x40;
3417 }
3418 }
3419
3420 /* EVEX instructions shouldn't need the REX prefix. */
3421 i.vrex &= ~vrex_used;
3422 gas_assert (i.vrex == 0);
3423
3424 /* Check the REX.W bit. */
3425 w = (i.rex & REX_W) ? 1 : 0;
3426 if (i.tm.opcode_modifier.vexw)
3427 {
3428 if (i.tm.opcode_modifier.vexw == VEXW1)
3429 w = 1;
3430 }
3431 /* If w is not set it means we are dealing with WIG instruction. */
3432 else if (!w)
3433 {
3434 if (evexwig == evexw1)
3435 w = 1;
3436 }
3437
3438 /* Encode the U bit. */
3439 implied_prefix |= 0x4;
3440
3441 /* The third byte of the EVEX prefix. */
3442 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3443
3444 /* The fourth byte of the EVEX prefix. */
3445 /* The zeroing-masking bit. */
3446 if (i.mask && i.mask->zeroing)
3447 i.vex.bytes[3] |= 0x80;
3448
3449 /* Don't always set the broadcast bit if there is no RC. */
3450 if (!i.rounding)
3451 {
3452 /* Encode the vector length. */
3453 unsigned int vec_length;
3454
3455 switch (i.tm.opcode_modifier.evex)
3456 {
3457 case EVEXLIG: /* LL' is ignored */
3458 vec_length = evexlig << 5;
3459 break;
3460 case EVEX128:
3461 vec_length = 0 << 5;
3462 break;
3463 case EVEX256:
3464 vec_length = 1 << 5;
3465 break;
3466 case EVEX512:
3467 vec_length = 2 << 5;
3468 break;
3469 default:
3470 abort ();
3471 break;
3472 }
3473 i.vex.bytes[3] |= vec_length;
3474 /* Encode the broadcast bit. */
3475 if (i.broadcast)
3476 i.vex.bytes[3] |= 0x10;
3477 }
3478 else
3479 {
3480 if (i.rounding->type != saeonly)
3481 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3482 else
3483 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3484 }
3485
3486 if (i.mask && i.mask->mask)
3487 i.vex.bytes[3] |= i.mask->mask->reg_num;
3488 }
3489
3490 static void
3491 process_immext (void)
3492 {
3493 expressionS *exp;
3494
3495 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3496 && i.operands > 0)
3497 {
3498 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3499 with an opcode suffix which is coded in the same place as an
3500 8-bit immediate field would be.
3501 Here we check those operands and remove them afterwards. */
3502 unsigned int x;
3503
3504 for (x = 0; x < i.operands; x++)
3505 if (register_number (i.op[x].regs) != x)
3506 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3507 register_prefix, i.op[x].regs->reg_name, x + 1,
3508 i.tm.name);
3509
3510 i.operands = 0;
3511 }
3512
3513 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3514 {
3515 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3516 suffix which is coded in the same place as an 8-bit immediate
3517 field would be.
3518 Here we check those operands and remove them afterwards. */
3519 unsigned int x;
3520
3521 if (i.operands != 3)
3522 abort();
3523
3524 for (x = 0; x < 2; x++)
3525 if (register_number (i.op[x].regs) != x)
3526 goto bad_register_operand;
3527
3528 /* Check for third operand for mwaitx/monitorx insn. */
3529 if (register_number (i.op[x].regs)
3530 != (x + (i.tm.extension_opcode == 0xfb)))
3531 {
3532 bad_register_operand:
3533 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3534 register_prefix, i.op[x].regs->reg_name, x+1,
3535 i.tm.name);
3536 }
3537
3538 i.operands = 0;
3539 }
3540
3541 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3542 which is coded in the same place as an 8-bit immediate field
3543 would be. Here we fake an 8-bit immediate operand from the
3544 opcode suffix stored in tm.extension_opcode.
3545
3546 AVX instructions also use this encoding, for some of
3547 3 argument instructions. */
3548
3549 gas_assert (i.imm_operands <= 1
3550 && (i.operands <= 2
3551 || ((i.tm.opcode_modifier.vex
3552 || i.tm.opcode_modifier.evex)
3553 && i.operands <= 4)));
3554
3555 exp = &im_expressions[i.imm_operands++];
3556 i.op[i.operands].imms = exp;
3557 i.types[i.operands] = imm8;
3558 i.operands++;
3559 exp->X_op = O_constant;
3560 exp->X_add_number = i.tm.extension_opcode;
3561 i.tm.extension_opcode = None;
3562 }
3563
3564
3565 static int
3566 check_hle (void)
3567 {
3568 switch (i.tm.opcode_modifier.hleprefixok)
3569 {
3570 default:
3571 abort ();
3572 case HLEPrefixNone:
3573 as_bad (_("invalid instruction `%s' after `%s'"),
3574 i.tm.name, i.hle_prefix);
3575 return 0;
3576 case HLEPrefixLock:
3577 if (i.prefix[LOCK_PREFIX])
3578 return 1;
3579 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3580 return 0;
3581 case HLEPrefixAny:
3582 return 1;
3583 case HLEPrefixRelease:
3584 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3585 {
3586 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3587 i.tm.name);
3588 return 0;
3589 }
3590 if (i.mem_operands == 0
3591 || !operand_type_check (i.types[i.operands - 1], anymem))
3592 {
3593 as_bad (_("memory destination needed for instruction `%s'"
3594 " after `xrelease'"), i.tm.name);
3595 return 0;
3596 }
3597 return 1;
3598 }
3599 }
3600
3601 /* This is the guts of the machine-dependent assembler. LINE points to a
3602 machine dependent instruction. This function is supposed to emit
3603 the frags/bytes it assembles to. */
3604
3605 void
3606 md_assemble (char *line)
3607 {
3608 unsigned int j;
3609 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
3610 const insn_template *t;
3611
3612 /* Initialize globals. */
3613 memset (&i, '\0', sizeof (i));
3614 for (j = 0; j < MAX_OPERANDS; j++)
3615 i.reloc[j] = NO_RELOC;
3616 memset (disp_expressions, '\0', sizeof (disp_expressions));
3617 memset (im_expressions, '\0', sizeof (im_expressions));
3618 save_stack_p = save_stack;
3619
3620 /* First parse an instruction mnemonic & call i386_operand for the operands.
3621 We assume that the scrubber has arranged it so that line[0] is the valid
3622 start of a (possibly prefixed) mnemonic. */
3623
3624 line = parse_insn (line, mnemonic);
3625 if (line == NULL)
3626 return;
3627 mnem_suffix = i.suffix;
3628
3629 line = parse_operands (line, mnemonic);
3630 this_operand = -1;
3631 xfree (i.memop1_string);
3632 i.memop1_string = NULL;
3633 if (line == NULL)
3634 return;
3635
3636 /* Now we've parsed the mnemonic into a set of templates, and have the
3637 operands at hand. */
3638
3639 /* All intel opcodes have reversed operands except for "bound" and
3640 "enter". We also don't reverse intersegment "jmp" and "call"
3641 instructions with 2 immediate operands so that the immediate segment
3642 precedes the offset, as it does when in AT&T mode. */
3643 if (intel_syntax
3644 && i.operands > 1
3645 && (strcmp (mnemonic, "bound") != 0)
3646 && (strcmp (mnemonic, "invlpga") != 0)
3647 && !(operand_type_check (i.types[0], imm)
3648 && operand_type_check (i.types[1], imm)))
3649 swap_operands ();
3650
3651 /* The order of the immediates should be reversed
3652 for 2 immediates extrq and insertq instructions */
3653 if (i.imm_operands == 2
3654 && (strcmp (mnemonic, "extrq") == 0
3655 || strcmp (mnemonic, "insertq") == 0))
3656 swap_2_operands (0, 1);
3657
3658 if (i.imm_operands)
3659 optimize_imm ();
3660
3661 /* Don't optimize displacement for movabs since it only takes 64bit
3662 displacement. */
3663 if (i.disp_operands
3664 && i.disp_encoding != disp_encoding_32bit
3665 && (flag_code != CODE_64BIT
3666 || strcmp (mnemonic, "movabs") != 0))
3667 optimize_disp ();
3668
3669 /* Next, we find a template that matches the given insn,
3670 making sure the overlap of the given operands types is consistent
3671 with the template operand types. */
3672
3673 if (!(t = match_template (mnem_suffix)))
3674 return;
3675
3676 if (sse_check != check_none
3677 && !i.tm.opcode_modifier.noavx
3678 && (i.tm.cpu_flags.bitfield.cpusse
3679 || i.tm.cpu_flags.bitfield.cpusse2
3680 || i.tm.cpu_flags.bitfield.cpusse3
3681 || i.tm.cpu_flags.bitfield.cpussse3
3682 || i.tm.cpu_flags.bitfield.cpusse4_1
3683 || i.tm.cpu_flags.bitfield.cpusse4_2))
3684 {
3685 (sse_check == check_warning
3686 ? as_warn
3687 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3688 }
3689
3690 /* Zap movzx and movsx suffix. The suffix has been set from
3691 "word ptr" or "byte ptr" on the source operand in Intel syntax
3692 or extracted from mnemonic in AT&T syntax. But we'll use
3693 the destination register to choose the suffix for encoding. */
3694 if ((i.tm.base_opcode & ~9) == 0x0fb6)
3695 {
3696 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3697 there is no suffix, the default will be byte extension. */
3698 if (i.reg_operands != 2
3699 && !i.suffix
3700 && intel_syntax)
3701 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3702
3703 i.suffix = 0;
3704 }
3705
3706 if (i.tm.opcode_modifier.fwait)
3707 if (!add_prefix (FWAIT_OPCODE))
3708 return;
3709
3710 /* Check if REP prefix is OK. */
3711 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3712 {
3713 as_bad (_("invalid instruction `%s' after `%s'"),
3714 i.tm.name, i.rep_prefix);
3715 return;
3716 }
3717
3718 /* Check for lock without a lockable instruction. Destination operand
3719 must be memory unless it is xchg (0x86). */
3720 if (i.prefix[LOCK_PREFIX]
3721 && (!i.tm.opcode_modifier.islockable
3722 || i.mem_operands == 0
3723 || (i.tm.base_opcode != 0x86
3724 && !operand_type_check (i.types[i.operands - 1], anymem))))
3725 {
3726 as_bad (_("expecting lockable instruction after `lock'"));
3727 return;
3728 }
3729
3730 /* Check if HLE prefix is OK. */
3731 if (i.hle_prefix && !check_hle ())
3732 return;
3733
3734 /* Check BND prefix. */
3735 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3736 as_bad (_("expecting valid branch instruction after `bnd'"));
3737
3738 /* Check NOTRACK prefix. */
3739 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
3740 as_bad (_("expecting indirect branch instruction after `notrack'"));
3741
3742 if (i.tm.cpu_flags.bitfield.cpumpx)
3743 {
3744 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
3745 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3746 else if (flag_code != CODE_16BIT
3747 ? i.prefix[ADDR_PREFIX]
3748 : i.mem_operands && !i.prefix[ADDR_PREFIX])
3749 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3750 }
3751
3752 /* Insert BND prefix. */
3753 if (add_bnd_prefix
3754 && i.tm.opcode_modifier.bndprefixok
3755 && !i.prefix[BND_PREFIX])
3756 add_prefix (BND_PREFIX_OPCODE);
3757
3758 /* Check string instruction segment overrides. */
3759 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
3760 {
3761 if (!check_string ())
3762 return;
3763 i.disp_operands = 0;
3764 }
3765
3766 if (!process_suffix ())
3767 return;
3768
3769 /* Update operand types. */
3770 for (j = 0; j < i.operands; j++)
3771 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3772
3773 /* Make still unresolved immediate matches conform to size of immediate
3774 given in i.suffix. */
3775 if (!finalize_imm ())
3776 return;
3777
3778 if (i.types[0].bitfield.imm1)
3779 i.imm_operands = 0; /* kludge for shift insns. */
3780
3781 /* We only need to check those implicit registers for instructions
3782 with 3 operands or less. */
3783 if (i.operands <= 3)
3784 for (j = 0; j < i.operands; j++)
3785 if (i.types[j].bitfield.inoutportreg
3786 || i.types[j].bitfield.shiftcount
3787 || i.types[j].bitfield.acc
3788 || i.types[j].bitfield.floatacc)
3789 i.reg_operands--;
3790
3791 /* ImmExt should be processed after SSE2AVX. */
3792 if (!i.tm.opcode_modifier.sse2avx
3793 && i.tm.opcode_modifier.immext)
3794 process_immext ();
3795
3796 /* For insns with operands there are more diddles to do to the opcode. */
3797 if (i.operands)
3798 {
3799 if (!process_operands ())
3800 return;
3801 }
3802 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
3803 {
3804 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3805 as_warn (_("translating to `%sp'"), i.tm.name);
3806 }
3807
3808 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3809 {
3810 if (flag_code == CODE_16BIT)
3811 {
3812 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3813 i.tm.name);
3814 return;
3815 }
3816
3817 if (i.tm.opcode_modifier.vex)
3818 build_vex_prefix (t);
3819 else
3820 build_evex_prefix ();
3821 }
3822
3823 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3824 instructions may define INT_OPCODE as well, so avoid this corner
3825 case for those instructions that use MODRM. */
3826 if (i.tm.base_opcode == INT_OPCODE
3827 && !i.tm.opcode_modifier.modrm
3828 && i.op[0].imms->X_add_number == 3)
3829 {
3830 i.tm.base_opcode = INT3_OPCODE;
3831 i.imm_operands = 0;
3832 }
3833
3834 if ((i.tm.opcode_modifier.jump
3835 || i.tm.opcode_modifier.jumpbyte
3836 || i.tm.opcode_modifier.jumpdword)
3837 && i.op[0].disps->X_op == O_constant)
3838 {
3839 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3840 the absolute address given by the constant. Since ix86 jumps and
3841 calls are pc relative, we need to generate a reloc. */
3842 i.op[0].disps->X_add_symbol = &abs_symbol;
3843 i.op[0].disps->X_op = O_symbol;
3844 }
3845
3846 if (i.tm.opcode_modifier.rex64)
3847 i.rex |= REX_W;
3848
3849 /* For 8 bit registers we need an empty rex prefix. Also if the
3850 instruction already has a prefix, we need to convert old
3851 registers to new ones. */
3852
3853 if ((i.types[0].bitfield.reg8
3854 && (i.op[0].regs->reg_flags & RegRex64) != 0)
3855 || (i.types[1].bitfield.reg8
3856 && (i.op[1].regs->reg_flags & RegRex64) != 0)
3857 || ((i.types[0].bitfield.reg8
3858 || i.types[1].bitfield.reg8)
3859 && i.rex != 0))
3860 {
3861 int x;
3862
3863 i.rex |= REX_OPCODE;
3864 for (x = 0; x < 2; x++)
3865 {
3866 /* Look for 8 bit operand that uses old registers. */
3867 if (i.types[x].bitfield.reg8
3868 && (i.op[x].regs->reg_flags & RegRex64) == 0)
3869 {
3870 /* In case it is "hi" register, give up. */
3871 if (i.op[x].regs->reg_num > 3)
3872 as_bad (_("can't encode register '%s%s' in an "
3873 "instruction requiring REX prefix."),
3874 register_prefix, i.op[x].regs->reg_name);
3875
3876 /* Otherwise it is equivalent to the extended register.
3877 Since the encoding doesn't change this is merely
3878 cosmetic cleanup for debug output. */
3879
3880 i.op[x].regs = i.op[x].regs + 8;
3881 }
3882 }
3883 }
3884
3885 if (i.rex != 0)
3886 add_prefix (REX_OPCODE | i.rex);
3887
3888 /* We are ready to output the insn. */
3889 output_insn ();
3890 }
3891
3892 static char *
3893 parse_insn (char *line, char *mnemonic)
3894 {
3895 char *l = line;
3896 char *token_start = l;
3897 char *mnem_p;
3898 int supported;
3899 const insn_template *t;
3900 char *dot_p = NULL;
3901
3902 while (1)
3903 {
3904 mnem_p = mnemonic;
3905 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3906 {
3907 if (*mnem_p == '.')
3908 dot_p = mnem_p;
3909 mnem_p++;
3910 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
3911 {
3912 as_bad (_("no such instruction: `%s'"), token_start);
3913 return NULL;
3914 }
3915 l++;
3916 }
3917 if (!is_space_char (*l)
3918 && *l != END_OF_INSN
3919 && (intel_syntax
3920 || (*l != PREFIX_SEPARATOR
3921 && *l != ',')))
3922 {
3923 as_bad (_("invalid character %s in mnemonic"),
3924 output_invalid (*l));
3925 return NULL;
3926 }
3927 if (token_start == l)
3928 {
3929 if (!intel_syntax && *l == PREFIX_SEPARATOR)
3930 as_bad (_("expecting prefix; got nothing"));
3931 else
3932 as_bad (_("expecting mnemonic; got nothing"));
3933 return NULL;
3934 }
3935
3936 /* Look up instruction (or prefix) via hash table. */
3937 current_templates = (const templates *) hash_find (op_hash, mnemonic);
3938
3939 if (*l != END_OF_INSN
3940 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3941 && current_templates
3942 && current_templates->start->opcode_modifier.isprefix)
3943 {
3944 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
3945 {
3946 as_bad ((flag_code != CODE_64BIT
3947 ? _("`%s' is only supported in 64-bit mode")
3948 : _("`%s' is not supported in 64-bit mode")),
3949 current_templates->start->name);
3950 return NULL;
3951 }
3952 /* If we are in 16-bit mode, do not allow addr16 or data16.
3953 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3954 if ((current_templates->start->opcode_modifier.size16
3955 || current_templates->start->opcode_modifier.size32)
3956 && flag_code != CODE_64BIT
3957 && (current_templates->start->opcode_modifier.size32
3958 ^ (flag_code == CODE_16BIT)))
3959 {
3960 as_bad (_("redundant %s prefix"),
3961 current_templates->start->name);
3962 return NULL;
3963 }
3964 if (current_templates->start->opcode_length == 0)
3965 {
3966 /* Handle pseudo prefixes. */
3967 switch (current_templates->start->base_opcode)
3968 {
3969 case 0x0:
3970 /* {disp8} */
3971 i.disp_encoding = disp_encoding_8bit;
3972 break;
3973 case 0x1:
3974 /* {disp32} */
3975 i.disp_encoding = disp_encoding_32bit;
3976 break;
3977 case 0x2:
3978 /* {load} */
3979 i.dir_encoding = dir_encoding_load;
3980 break;
3981 case 0x3:
3982 /* {store} */
3983 i.dir_encoding = dir_encoding_store;
3984 break;
3985 case 0x4:
3986 /* {vex2} */
3987 i.vec_encoding = vex_encoding_vex2;
3988 break;
3989 case 0x5:
3990 /* {vex3} */
3991 i.vec_encoding = vex_encoding_vex3;
3992 break;
3993 case 0x6:
3994 /* {evex} */
3995 i.vec_encoding = vex_encoding_evex;
3996 break;
3997 default:
3998 abort ();
3999 }
4000 }
4001 else
4002 {
4003 /* Add prefix, checking for repeated prefixes. */
4004 switch (add_prefix (current_templates->start->base_opcode))
4005 {
4006 case PREFIX_EXIST:
4007 return NULL;
4008 case PREFIX_DS:
4009 if (current_templates->start->cpu_flags.bitfield.cpucet)
4010 i.notrack_prefix = current_templates->start->name;
4011 break;
4012 case PREFIX_REP:
4013 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4014 i.hle_prefix = current_templates->start->name;
4015 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4016 i.bnd_prefix = current_templates->start->name;
4017 else
4018 i.rep_prefix = current_templates->start->name;
4019 break;
4020 default:
4021 break;
4022 }
4023 }
4024 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4025 token_start = ++l;
4026 }
4027 else
4028 break;
4029 }
4030
4031 if (!current_templates)
4032 {
4033 /* Check if we should swap operand or force 32bit displacement in
4034 encoding. */
4035 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4036 i.dir_encoding = dir_encoding_store;
4037 else if (mnem_p - 3 == dot_p
4038 && dot_p[1] == 'd'
4039 && dot_p[2] == '8')
4040 i.disp_encoding = disp_encoding_8bit;
4041 else if (mnem_p - 4 == dot_p
4042 && dot_p[1] == 'd'
4043 && dot_p[2] == '3'
4044 && dot_p[3] == '2')
4045 i.disp_encoding = disp_encoding_32bit;
4046 else
4047 goto check_suffix;
4048 mnem_p = dot_p;
4049 *dot_p = '\0';
4050 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4051 }
4052
4053 if (!current_templates)
4054 {
4055 check_suffix:
4056 /* See if we can get a match by trimming off a suffix. */
4057 switch (mnem_p[-1])
4058 {
4059 case WORD_MNEM_SUFFIX:
4060 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4061 i.suffix = SHORT_MNEM_SUFFIX;
4062 else
4063 /* Fall through. */
4064 case BYTE_MNEM_SUFFIX:
4065 case QWORD_MNEM_SUFFIX:
4066 i.suffix = mnem_p[-1];
4067 mnem_p[-1] = '\0';
4068 current_templates = (const templates *) hash_find (op_hash,
4069 mnemonic);
4070 break;
4071 case SHORT_MNEM_SUFFIX:
4072 case LONG_MNEM_SUFFIX:
4073 if (!intel_syntax)
4074 {
4075 i.suffix = mnem_p[-1];
4076 mnem_p[-1] = '\0';
4077 current_templates = (const templates *) hash_find (op_hash,
4078 mnemonic);
4079 }
4080 break;
4081
4082 /* Intel Syntax. */
4083 case 'd':
4084 if (intel_syntax)
4085 {
4086 if (intel_float_operand (mnemonic) == 1)
4087 i.suffix = SHORT_MNEM_SUFFIX;
4088 else
4089 i.suffix = LONG_MNEM_SUFFIX;
4090 mnem_p[-1] = '\0';
4091 current_templates = (const templates *) hash_find (op_hash,
4092 mnemonic);
4093 }
4094 break;
4095 }
4096 if (!current_templates)
4097 {
4098 as_bad (_("no such instruction: `%s'"), token_start);
4099 return NULL;
4100 }
4101 }
4102
4103 if (current_templates->start->opcode_modifier.jump
4104 || current_templates->start->opcode_modifier.jumpbyte)
4105 {
4106 /* Check for a branch hint. We allow ",pt" and ",pn" for
4107 predict taken and predict not taken respectively.
4108 I'm not sure that branch hints actually do anything on loop
4109 and jcxz insns (JumpByte) for current Pentium4 chips. They
4110 may work in the future and it doesn't hurt to accept them
4111 now. */
4112 if (l[0] == ',' && l[1] == 'p')
4113 {
4114 if (l[2] == 't')
4115 {
4116 if (!add_prefix (DS_PREFIX_OPCODE))
4117 return NULL;
4118 l += 3;
4119 }
4120 else if (l[2] == 'n')
4121 {
4122 if (!add_prefix (CS_PREFIX_OPCODE))
4123 return NULL;
4124 l += 3;
4125 }
4126 }
4127 }
4128 /* Any other comma loses. */
4129 if (*l == ',')
4130 {
4131 as_bad (_("invalid character %s in mnemonic"),
4132 output_invalid (*l));
4133 return NULL;
4134 }
4135
4136 /* Check if instruction is supported on specified architecture. */
4137 supported = 0;
4138 for (t = current_templates->start; t < current_templates->end; ++t)
4139 {
4140 supported |= cpu_flags_match (t);
4141 if (supported == CPU_FLAGS_PERFECT_MATCH)
4142 goto skip;
4143 }
4144
4145 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4146 {
4147 as_bad (flag_code == CODE_64BIT
4148 ? _("`%s' is not supported in 64-bit mode")
4149 : _("`%s' is only supported in 64-bit mode"),
4150 current_templates->start->name);
4151 return NULL;
4152 }
4153 if (supported != CPU_FLAGS_PERFECT_MATCH)
4154 {
4155 as_bad (_("`%s' is not supported on `%s%s'"),
4156 current_templates->start->name,
4157 cpu_arch_name ? cpu_arch_name : default_arch,
4158 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4159 return NULL;
4160 }
4161
4162 skip:
4163 if (!cpu_arch_flags.bitfield.cpui386
4164 && (flag_code != CODE_16BIT))
4165 {
4166 as_warn (_("use .code16 to ensure correct addressing mode"));
4167 }
4168
4169 return l;
4170 }
4171
4172 static char *
4173 parse_operands (char *l, const char *mnemonic)
4174 {
4175 char *token_start;
4176
4177 /* 1 if operand is pending after ','. */
4178 unsigned int expecting_operand = 0;
4179
4180 /* Non-zero if operand parens not balanced. */
4181 unsigned int paren_not_balanced;
4182
4183 while (*l != END_OF_INSN)
4184 {
4185 /* Skip optional white space before operand. */
4186 if (is_space_char (*l))
4187 ++l;
4188 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4189 {
4190 as_bad (_("invalid character %s before operand %d"),
4191 output_invalid (*l),
4192 i.operands + 1);
4193 return NULL;
4194 }
4195 token_start = l; /* After white space. */
4196 paren_not_balanced = 0;
4197 while (paren_not_balanced || *l != ',')
4198 {
4199 if (*l == END_OF_INSN)
4200 {
4201 if (paren_not_balanced)
4202 {
4203 if (!intel_syntax)
4204 as_bad (_("unbalanced parenthesis in operand %d."),
4205 i.operands + 1);
4206 else
4207 as_bad (_("unbalanced brackets in operand %d."),
4208 i.operands + 1);
4209 return NULL;
4210 }
4211 else
4212 break; /* we are done */
4213 }
4214 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4215 {
4216 as_bad (_("invalid character %s in operand %d"),
4217 output_invalid (*l),
4218 i.operands + 1);
4219 return NULL;
4220 }
4221 if (!intel_syntax)
4222 {
4223 if (*l == '(')
4224 ++paren_not_balanced;
4225 if (*l == ')')
4226 --paren_not_balanced;
4227 }
4228 else
4229 {
4230 if (*l == '[')
4231 ++paren_not_balanced;
4232 if (*l == ']')
4233 --paren_not_balanced;
4234 }
4235 l++;
4236 }
4237 if (l != token_start)
4238 { /* Yes, we've read in another operand. */
4239 unsigned int operand_ok;
4240 this_operand = i.operands++;
4241 if (i.operands > MAX_OPERANDS)
4242 {
4243 as_bad (_("spurious operands; (%d operands/instruction max)"),
4244 MAX_OPERANDS);
4245 return NULL;
4246 }
4247 i.types[this_operand].bitfield.unspecified = 1;
4248 /* Now parse operand adding info to 'i' as we go along. */
4249 END_STRING_AND_SAVE (l);
4250
4251 if (intel_syntax)
4252 operand_ok =
4253 i386_intel_operand (token_start,
4254 intel_float_operand (mnemonic));
4255 else
4256 operand_ok = i386_att_operand (token_start);
4257
4258 RESTORE_END_STRING (l);
4259 if (!operand_ok)
4260 return NULL;
4261 }
4262 else
4263 {
4264 if (expecting_operand)
4265 {
4266 expecting_operand_after_comma:
4267 as_bad (_("expecting operand after ','; got nothing"));
4268 return NULL;
4269 }
4270 if (*l == ',')
4271 {
4272 as_bad (_("expecting operand before ','; got nothing"));
4273 return NULL;
4274 }
4275 }
4276
4277 /* Now *l must be either ',' or END_OF_INSN. */
4278 if (*l == ',')
4279 {
4280 if (*++l == END_OF_INSN)
4281 {
4282 /* Just skip it, if it's \n complain. */
4283 goto expecting_operand_after_comma;
4284 }
4285 expecting_operand = 1;
4286 }
4287 }
4288 return l;
4289 }
4290
4291 static void
4292 swap_2_operands (int xchg1, int xchg2)
4293 {
4294 union i386_op temp_op;
4295 i386_operand_type temp_type;
4296 enum bfd_reloc_code_real temp_reloc;
4297
4298 temp_type = i.types[xchg2];
4299 i.types[xchg2] = i.types[xchg1];
4300 i.types[xchg1] = temp_type;
4301 temp_op = i.op[xchg2];
4302 i.op[xchg2] = i.op[xchg1];
4303 i.op[xchg1] = temp_op;
4304 temp_reloc = i.reloc[xchg2];
4305 i.reloc[xchg2] = i.reloc[xchg1];
4306 i.reloc[xchg1] = temp_reloc;
4307
4308 if (i.mask)
4309 {
4310 if (i.mask->operand == xchg1)
4311 i.mask->operand = xchg2;
4312 else if (i.mask->operand == xchg2)
4313 i.mask->operand = xchg1;
4314 }
4315 if (i.broadcast)
4316 {
4317 if (i.broadcast->operand == xchg1)
4318 i.broadcast->operand = xchg2;
4319 else if (i.broadcast->operand == xchg2)
4320 i.broadcast->operand = xchg1;
4321 }
4322 if (i.rounding)
4323 {
4324 if (i.rounding->operand == xchg1)
4325 i.rounding->operand = xchg2;
4326 else if (i.rounding->operand == xchg2)
4327 i.rounding->operand = xchg1;
4328 }
4329 }
4330
4331 static void
4332 swap_operands (void)
4333 {
4334 switch (i.operands)
4335 {
4336 case 5:
4337 case 4:
4338 swap_2_operands (1, i.operands - 2);
4339 /* Fall through. */
4340 case 3:
4341 case 2:
4342 swap_2_operands (0, i.operands - 1);
4343 break;
4344 default:
4345 abort ();
4346 }
4347
4348 if (i.mem_operands == 2)
4349 {
4350 const seg_entry *temp_seg;
4351 temp_seg = i.seg[0];
4352 i.seg[0] = i.seg[1];
4353 i.seg[1] = temp_seg;
4354 }
4355 }
4356
4357 /* Try to ensure constant immediates are represented in the smallest
4358 opcode possible. */
4359 static void
4360 optimize_imm (void)
4361 {
4362 char guess_suffix = 0;
4363 int op;
4364
4365 if (i.suffix)
4366 guess_suffix = i.suffix;
4367 else if (i.reg_operands)
4368 {
4369 /* Figure out a suffix from the last register operand specified.
4370 We can't do this properly yet, ie. excluding InOutPortReg,
4371 but the following works for instructions with immediates.
4372 In any case, we can't set i.suffix yet. */
4373 for (op = i.operands; --op >= 0;)
4374 if (i.types[op].bitfield.reg8)
4375 {
4376 guess_suffix = BYTE_MNEM_SUFFIX;
4377 break;
4378 }
4379 else if (i.types[op].bitfield.reg16)
4380 {
4381 guess_suffix = WORD_MNEM_SUFFIX;
4382 break;
4383 }
4384 else if (i.types[op].bitfield.reg32)
4385 {
4386 guess_suffix = LONG_MNEM_SUFFIX;
4387 break;
4388 }
4389 else if (i.types[op].bitfield.reg64)
4390 {
4391 guess_suffix = QWORD_MNEM_SUFFIX;
4392 break;
4393 }
4394 }
4395 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4396 guess_suffix = WORD_MNEM_SUFFIX;
4397
4398 for (op = i.operands; --op >= 0;)
4399 if (operand_type_check (i.types[op], imm))
4400 {
4401 switch (i.op[op].imms->X_op)
4402 {
4403 case O_constant:
4404 /* If a suffix is given, this operand may be shortened. */
4405 switch (guess_suffix)
4406 {
4407 case LONG_MNEM_SUFFIX:
4408 i.types[op].bitfield.imm32 = 1;
4409 i.types[op].bitfield.imm64 = 1;
4410 break;
4411 case WORD_MNEM_SUFFIX:
4412 i.types[op].bitfield.imm16 = 1;
4413 i.types[op].bitfield.imm32 = 1;
4414 i.types[op].bitfield.imm32s = 1;
4415 i.types[op].bitfield.imm64 = 1;
4416 break;
4417 case BYTE_MNEM_SUFFIX:
4418 i.types[op].bitfield.imm8 = 1;
4419 i.types[op].bitfield.imm8s = 1;
4420 i.types[op].bitfield.imm16 = 1;
4421 i.types[op].bitfield.imm32 = 1;
4422 i.types[op].bitfield.imm32s = 1;
4423 i.types[op].bitfield.imm64 = 1;
4424 break;
4425 }
4426
4427 /* If this operand is at most 16 bits, convert it
4428 to a signed 16 bit number before trying to see
4429 whether it will fit in an even smaller size.
4430 This allows a 16-bit operand such as $0xffe0 to
4431 be recognised as within Imm8S range. */
4432 if ((i.types[op].bitfield.imm16)
4433 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4434 {
4435 i.op[op].imms->X_add_number =
4436 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4437 }
4438 #ifdef BFD64
4439 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4440 if ((i.types[op].bitfield.imm32)
4441 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4442 == 0))
4443 {
4444 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4445 ^ ((offsetT) 1 << 31))
4446 - ((offsetT) 1 << 31));
4447 }
4448 #endif
4449 i.types[op]
4450 = operand_type_or (i.types[op],
4451 smallest_imm_type (i.op[op].imms->X_add_number));
4452
4453 /* We must avoid matching of Imm32 templates when 64bit
4454 only immediate is available. */
4455 if (guess_suffix == QWORD_MNEM_SUFFIX)
4456 i.types[op].bitfield.imm32 = 0;
4457 break;
4458
4459 case O_absent:
4460 case O_register:
4461 abort ();
4462
4463 /* Symbols and expressions. */
4464 default:
4465 /* Convert symbolic operand to proper sizes for matching, but don't
4466 prevent matching a set of insns that only supports sizes other
4467 than those matching the insn suffix. */
4468 {
4469 i386_operand_type mask, allowed;
4470 const insn_template *t;
4471
4472 operand_type_set (&mask, 0);
4473 operand_type_set (&allowed, 0);
4474
4475 for (t = current_templates->start;
4476 t < current_templates->end;
4477 ++t)
4478 allowed = operand_type_or (allowed,
4479 t->operand_types[op]);
4480 switch (guess_suffix)
4481 {
4482 case QWORD_MNEM_SUFFIX:
4483 mask.bitfield.imm64 = 1;
4484 mask.bitfield.imm32s = 1;
4485 break;
4486 case LONG_MNEM_SUFFIX:
4487 mask.bitfield.imm32 = 1;
4488 break;
4489 case WORD_MNEM_SUFFIX:
4490 mask.bitfield.imm16 = 1;
4491 break;
4492 case BYTE_MNEM_SUFFIX:
4493 mask.bitfield.imm8 = 1;
4494 break;
4495 default:
4496 break;
4497 }
4498 allowed = operand_type_and (mask, allowed);
4499 if (!operand_type_all_zero (&allowed))
4500 i.types[op] = operand_type_and (i.types[op], mask);
4501 }
4502 break;
4503 }
4504 }
4505 }
4506
4507 /* Try to use the smallest displacement type too. */
4508 static void
4509 optimize_disp (void)
4510 {
4511 int op;
4512
4513 for (op = i.operands; --op >= 0;)
4514 if (operand_type_check (i.types[op], disp))
4515 {
4516 if (i.op[op].disps->X_op == O_constant)
4517 {
4518 offsetT op_disp = i.op[op].disps->X_add_number;
4519
4520 if (i.types[op].bitfield.disp16
4521 && (op_disp & ~(offsetT) 0xffff) == 0)
4522 {
4523 /* If this operand is at most 16 bits, convert
4524 to a signed 16 bit number and don't use 64bit
4525 displacement. */
4526 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4527 i.types[op].bitfield.disp64 = 0;
4528 }
4529 #ifdef BFD64
4530 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4531 if (i.types[op].bitfield.disp32
4532 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4533 {
4534 /* If this operand is at most 32 bits, convert
4535 to a signed 32 bit number and don't use 64bit
4536 displacement. */
4537 op_disp &= (((offsetT) 2 << 31) - 1);
4538 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4539 i.types[op].bitfield.disp64 = 0;
4540 }
4541 #endif
4542 if (!op_disp && i.types[op].bitfield.baseindex)
4543 {
4544 i.types[op].bitfield.disp8 = 0;
4545 i.types[op].bitfield.disp16 = 0;
4546 i.types[op].bitfield.disp32 = 0;
4547 i.types[op].bitfield.disp32s = 0;
4548 i.types[op].bitfield.disp64 = 0;
4549 i.op[op].disps = 0;
4550 i.disp_operands--;
4551 }
4552 else if (flag_code == CODE_64BIT)
4553 {
4554 if (fits_in_signed_long (op_disp))
4555 {
4556 i.types[op].bitfield.disp64 = 0;
4557 i.types[op].bitfield.disp32s = 1;
4558 }
4559 if (i.prefix[ADDR_PREFIX]
4560 && fits_in_unsigned_long (op_disp))
4561 i.types[op].bitfield.disp32 = 1;
4562 }
4563 if ((i.types[op].bitfield.disp32
4564 || i.types[op].bitfield.disp32s
4565 || i.types[op].bitfield.disp16)
4566 && fits_in_signed_byte (op_disp))
4567 i.types[op].bitfield.disp8 = 1;
4568 }
4569 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4570 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4571 {
4572 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4573 i.op[op].disps, 0, i.reloc[op]);
4574 i.types[op].bitfield.disp8 = 0;
4575 i.types[op].bitfield.disp16 = 0;
4576 i.types[op].bitfield.disp32 = 0;
4577 i.types[op].bitfield.disp32s = 0;
4578 i.types[op].bitfield.disp64 = 0;
4579 }
4580 else
4581 /* We only support 64bit displacement on constants. */
4582 i.types[op].bitfield.disp64 = 0;
4583 }
4584 }
4585
4586 /* Check if operands are valid for the instruction. */
4587
4588 static int
4589 check_VecOperands (const insn_template *t)
4590 {
4591 unsigned int op;
4592
4593 /* Without VSIB byte, we can't have a vector register for index. */
4594 if (!t->opcode_modifier.vecsib
4595 && i.index_reg
4596 && (i.index_reg->reg_type.bitfield.regxmm
4597 || i.index_reg->reg_type.bitfield.regymm
4598 || i.index_reg->reg_type.bitfield.regzmm))
4599 {
4600 i.error = unsupported_vector_index_register;
4601 return 1;
4602 }
4603
4604 /* Check if default mask is allowed. */
4605 if (t->opcode_modifier.nodefmask
4606 && (!i.mask || i.mask->mask->reg_num == 0))
4607 {
4608 i.error = no_default_mask;
4609 return 1;
4610 }
4611
4612 /* For VSIB byte, we need a vector register for index, and all vector
4613 registers must be distinct. */
4614 if (t->opcode_modifier.vecsib)
4615 {
4616 if (!i.index_reg
4617 || !((t->opcode_modifier.vecsib == VecSIB128
4618 && i.index_reg->reg_type.bitfield.regxmm)
4619 || (t->opcode_modifier.vecsib == VecSIB256
4620 && i.index_reg->reg_type.bitfield.regymm)
4621 || (t->opcode_modifier.vecsib == VecSIB512
4622 && i.index_reg->reg_type.bitfield.regzmm)))
4623 {
4624 i.error = invalid_vsib_address;
4625 return 1;
4626 }
4627
4628 gas_assert (i.reg_operands == 2 || i.mask);
4629 if (i.reg_operands == 2 && !i.mask)
4630 {
4631 gas_assert (i.types[0].bitfield.regxmm
4632 || i.types[0].bitfield.regymm);
4633 gas_assert (i.types[2].bitfield.regxmm
4634 || i.types[2].bitfield.regymm);
4635 if (operand_check == check_none)
4636 return 0;
4637 if (register_number (i.op[0].regs)
4638 != register_number (i.index_reg)
4639 && register_number (i.op[2].regs)
4640 != register_number (i.index_reg)
4641 && register_number (i.op[0].regs)
4642 != register_number (i.op[2].regs))
4643 return 0;
4644 if (operand_check == check_error)
4645 {
4646 i.error = invalid_vector_register_set;
4647 return 1;
4648 }
4649 as_warn (_("mask, index, and destination registers should be distinct"));
4650 }
4651 else if (i.reg_operands == 1 && i.mask)
4652 {
4653 if ((i.types[1].bitfield.regymm
4654 || i.types[1].bitfield.regzmm)
4655 && (register_number (i.op[1].regs)
4656 == register_number (i.index_reg)))
4657 {
4658 if (operand_check == check_error)
4659 {
4660 i.error = invalid_vector_register_set;
4661 return 1;
4662 }
4663 if (operand_check != check_none)
4664 as_warn (_("index and destination registers should be distinct"));
4665 }
4666 }
4667 }
4668
4669 /* Check if broadcast is supported by the instruction and is applied
4670 to the memory operand. */
4671 if (i.broadcast)
4672 {
4673 int broadcasted_opnd_size;
4674
4675 /* Check if specified broadcast is supported in this instruction,
4676 and it's applied to memory operand of DWORD or QWORD type,
4677 depending on VecESize. */
4678 if (i.broadcast->type != t->opcode_modifier.broadcast
4679 || !i.types[i.broadcast->operand].bitfield.mem
4680 || (t->opcode_modifier.vecesize == 0
4681 && !i.types[i.broadcast->operand].bitfield.dword
4682 && !i.types[i.broadcast->operand].bitfield.unspecified)
4683 || (t->opcode_modifier.vecesize == 1
4684 && !i.types[i.broadcast->operand].bitfield.qword
4685 && !i.types[i.broadcast->operand].bitfield.unspecified))
4686 goto bad_broadcast;
4687
4688 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4689 if (i.broadcast->type == BROADCAST_1TO16)
4690 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4691 else if (i.broadcast->type == BROADCAST_1TO8)
4692 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
4693 else if (i.broadcast->type == BROADCAST_1TO4)
4694 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4695 else if (i.broadcast->type == BROADCAST_1TO2)
4696 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
4697 else
4698 goto bad_broadcast;
4699
4700 if ((broadcasted_opnd_size == 256
4701 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4702 || (broadcasted_opnd_size == 512
4703 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4704 {
4705 bad_broadcast:
4706 i.error = unsupported_broadcast;
4707 return 1;
4708 }
4709 }
4710 /* If broadcast is supported in this instruction, we need to check if
4711 operand of one-element size isn't specified without broadcast. */
4712 else if (t->opcode_modifier.broadcast && i.mem_operands)
4713 {
4714 /* Find memory operand. */
4715 for (op = 0; op < i.operands; op++)
4716 if (operand_type_check (i.types[op], anymem))
4717 break;
4718 gas_assert (op < i.operands);
4719 /* Check size of the memory operand. */
4720 if ((t->opcode_modifier.vecesize == 0
4721 && i.types[op].bitfield.dword)
4722 || (t->opcode_modifier.vecesize == 1
4723 && i.types[op].bitfield.qword))
4724 {
4725 i.error = broadcast_needed;
4726 return 1;
4727 }
4728 }
4729
4730 /* Check if requested masking is supported. */
4731 if (i.mask
4732 && (!t->opcode_modifier.masking
4733 || (i.mask->zeroing
4734 && t->opcode_modifier.masking == MERGING_MASKING)))
4735 {
4736 i.error = unsupported_masking;
4737 return 1;
4738 }
4739
4740 /* Check if masking is applied to dest operand. */
4741 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4742 {
4743 i.error = mask_not_on_destination;
4744 return 1;
4745 }
4746
4747 /* Check RC/SAE. */
4748 if (i.rounding)
4749 {
4750 if ((i.rounding->type != saeonly
4751 && !t->opcode_modifier.staticrounding)
4752 || (i.rounding->type == saeonly
4753 && (t->opcode_modifier.staticrounding
4754 || !t->opcode_modifier.sae)))
4755 {
4756 i.error = unsupported_rc_sae;
4757 return 1;
4758 }
4759 /* If the instruction has several immediate operands and one of
4760 them is rounding, the rounding operand should be the last
4761 immediate operand. */
4762 if (i.imm_operands > 1
4763 && i.rounding->operand != (int) (i.imm_operands - 1))
4764 {
4765 i.error = rc_sae_operand_not_last_imm;
4766 return 1;
4767 }
4768 }
4769
4770 /* Check vector Disp8 operand. */
4771 if (t->opcode_modifier.disp8memshift)
4772 {
4773 if (i.broadcast)
4774 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4775 else
4776 i.memshift = t->opcode_modifier.disp8memshift;
4777
4778 for (op = 0; op < i.operands; op++)
4779 if (operand_type_check (i.types[op], disp)
4780 && i.op[op].disps->X_op == O_constant)
4781 {
4782 offsetT value = i.op[op].disps->X_add_number;
4783 int vec_disp8_ok
4784 = (i.disp_encoding != disp_encoding_32bit
4785 && fits_in_vec_disp8 (value));
4786 if (t->operand_types [op].bitfield.vec_disp8)
4787 {
4788 if (vec_disp8_ok)
4789 i.types[op].bitfield.vec_disp8 = 1;
4790 else
4791 {
4792 /* Vector insn can only have Vec_Disp8/Disp32 in
4793 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4794 mode. */
4795 i.types[op].bitfield.disp8 = 0;
4796 if (flag_code != CODE_16BIT)
4797 i.types[op].bitfield.disp16 = 0;
4798 }
4799 }
4800 else if (flag_code != CODE_16BIT)
4801 {
4802 /* One form of this instruction supports vector Disp8.
4803 Try vector Disp8 if we need to use Disp32. */
4804 if (vec_disp8_ok && !fits_in_signed_byte (value))
4805 {
4806 i.error = try_vector_disp8;
4807 return 1;
4808 }
4809 }
4810 }
4811 }
4812 else
4813 i.memshift = -1;
4814
4815 return 0;
4816 }
4817
4818 /* Check if operands are valid for the instruction. Update VEX
4819 operand types. */
4820
4821 static int
4822 VEX_check_operands (const insn_template *t)
4823 {
4824 if (i.vec_encoding == vex_encoding_evex)
4825 {
4826 /* This instruction must be encoded with EVEX prefix. */
4827 if (!t->opcode_modifier.evex)
4828 {
4829 i.error = unsupported;
4830 return 1;
4831 }
4832 return 0;
4833 }
4834
4835 if (!t->opcode_modifier.vex)
4836 {
4837 /* This instruction template doesn't have VEX prefix. */
4838 if (i.vec_encoding != vex_encoding_default)
4839 {
4840 i.error = unsupported;
4841 return 1;
4842 }
4843 return 0;
4844 }
4845
4846 /* Only check VEX_Imm4, which must be the first operand. */
4847 if (t->operand_types[0].bitfield.vec_imm4)
4848 {
4849 if (i.op[0].imms->X_op != O_constant
4850 || !fits_in_imm4 (i.op[0].imms->X_add_number))
4851 {
4852 i.error = bad_imm4;
4853 return 1;
4854 }
4855
4856 /* Turn off Imm8 so that update_imm won't complain. */
4857 i.types[0] = vec_imm4;
4858 }
4859
4860 return 0;
4861 }
4862
4863 static const insn_template *
4864 match_template (char mnem_suffix)
4865 {
4866 /* Points to template once we've found it. */
4867 const insn_template *t;
4868 i386_operand_type overlap0, overlap1, overlap2, overlap3;
4869 i386_operand_type overlap4;
4870 unsigned int found_reverse_match;
4871 i386_opcode_modifier suffix_check, mnemsuf_check;
4872 i386_operand_type operand_types [MAX_OPERANDS];
4873 int addr_prefix_disp;
4874 unsigned int j;
4875 unsigned int found_cpu_match;
4876 unsigned int check_register;
4877 enum i386_error specific_error = 0;
4878
4879 #if MAX_OPERANDS != 5
4880 # error "MAX_OPERANDS must be 5."
4881 #endif
4882
4883 found_reverse_match = 0;
4884 addr_prefix_disp = -1;
4885
4886 memset (&suffix_check, 0, sizeof (suffix_check));
4887 if (i.suffix == BYTE_MNEM_SUFFIX)
4888 suffix_check.no_bsuf = 1;
4889 else if (i.suffix == WORD_MNEM_SUFFIX)
4890 suffix_check.no_wsuf = 1;
4891 else if (i.suffix == SHORT_MNEM_SUFFIX)
4892 suffix_check.no_ssuf = 1;
4893 else if (i.suffix == LONG_MNEM_SUFFIX)
4894 suffix_check.no_lsuf = 1;
4895 else if (i.suffix == QWORD_MNEM_SUFFIX)
4896 suffix_check.no_qsuf = 1;
4897 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
4898 suffix_check.no_ldsuf = 1;
4899
4900 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
4901 if (intel_syntax)
4902 {
4903 switch (mnem_suffix)
4904 {
4905 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
4906 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
4907 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
4908 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
4909 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
4910 }
4911 }
4912
4913 /* Must have right number of operands. */
4914 i.error = number_of_operands_mismatch;
4915
4916 for (t = current_templates->start; t < current_templates->end; t++)
4917 {
4918 addr_prefix_disp = -1;
4919
4920 if (i.operands != t->operands)
4921 continue;
4922
4923 /* Check processor support. */
4924 i.error = unsupported;
4925 found_cpu_match = (cpu_flags_match (t)
4926 == CPU_FLAGS_PERFECT_MATCH);
4927 if (!found_cpu_match)
4928 continue;
4929
4930 /* Check old gcc support. */
4931 i.error = old_gcc_only;
4932 if (!old_gcc && t->opcode_modifier.oldgcc)
4933 continue;
4934
4935 /* Check AT&T mnemonic. */
4936 i.error = unsupported_with_intel_mnemonic;
4937 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
4938 continue;
4939
4940 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
4941 i.error = unsupported_syntax;
4942 if ((intel_syntax && t->opcode_modifier.attsyntax)
4943 || (!intel_syntax && t->opcode_modifier.intelsyntax)
4944 || (intel64 && t->opcode_modifier.amd64)
4945 || (!intel64 && t->opcode_modifier.intel64))
4946 continue;
4947
4948 /* Check the suffix, except for some instructions in intel mode. */
4949 i.error = invalid_instruction_suffix;
4950 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4951 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4952 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4953 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4954 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4955 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4956 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
4957 continue;
4958 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4959 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
4960 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
4961 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
4962 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
4963 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
4964 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
4965 continue;
4966
4967 if (!operand_size_match (t))
4968 continue;
4969
4970 for (j = 0; j < MAX_OPERANDS; j++)
4971 operand_types[j] = t->operand_types[j];
4972
4973 /* In general, don't allow 64-bit operands in 32-bit mode. */
4974 if (i.suffix == QWORD_MNEM_SUFFIX
4975 && flag_code != CODE_64BIT
4976 && (intel_syntax
4977 ? (!t->opcode_modifier.ignoresize
4978 && !intel_float_operand (t->name))
4979 : intel_float_operand (t->name) != 2)
4980 && ((!operand_types[0].bitfield.regmmx
4981 && !operand_types[0].bitfield.regxmm
4982 && !operand_types[0].bitfield.regymm
4983 && !operand_types[0].bitfield.regzmm)
4984 || (!operand_types[t->operands > 1].bitfield.regmmx
4985 && operand_types[t->operands > 1].bitfield.regxmm
4986 && operand_types[t->operands > 1].bitfield.regymm
4987 && operand_types[t->operands > 1].bitfield.regzmm))
4988 && (t->base_opcode != 0x0fc7
4989 || t->extension_opcode != 1 /* cmpxchg8b */))
4990 continue;
4991
4992 /* In general, don't allow 32-bit operands on pre-386. */
4993 else if (i.suffix == LONG_MNEM_SUFFIX
4994 && !cpu_arch_flags.bitfield.cpui386
4995 && (intel_syntax
4996 ? (!t->opcode_modifier.ignoresize
4997 && !intel_float_operand (t->name))
4998 : intel_float_operand (t->name) != 2)
4999 && ((!operand_types[0].bitfield.regmmx
5000 && !operand_types[0].bitfield.regxmm)
5001 || (!operand_types[t->operands > 1].bitfield.regmmx
5002 && operand_types[t->operands > 1].bitfield.regxmm)))
5003 continue;
5004
5005 /* Do not verify operands when there are none. */
5006 else
5007 {
5008 if (!t->operands)
5009 /* We've found a match; break out of loop. */
5010 break;
5011 }
5012
5013 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5014 into Disp32/Disp16/Disp32 operand. */
5015 if (i.prefix[ADDR_PREFIX] != 0)
5016 {
5017 /* There should be only one Disp operand. */
5018 switch (flag_code)
5019 {
5020 case CODE_16BIT:
5021 for (j = 0; j < MAX_OPERANDS; j++)
5022 {
5023 if (operand_types[j].bitfield.disp16)
5024 {
5025 addr_prefix_disp = j;
5026 operand_types[j].bitfield.disp32 = 1;
5027 operand_types[j].bitfield.disp16 = 0;
5028 break;
5029 }
5030 }
5031 break;
5032 case CODE_32BIT:
5033 for (j = 0; j < MAX_OPERANDS; j++)
5034 {
5035 if (operand_types[j].bitfield.disp32)
5036 {
5037 addr_prefix_disp = j;
5038 operand_types[j].bitfield.disp32 = 0;
5039 operand_types[j].bitfield.disp16 = 1;
5040 break;
5041 }
5042 }
5043 break;
5044 case CODE_64BIT:
5045 for (j = 0; j < MAX_OPERANDS; j++)
5046 {
5047 if (operand_types[j].bitfield.disp64)
5048 {
5049 addr_prefix_disp = j;
5050 operand_types[j].bitfield.disp64 = 0;
5051 operand_types[j].bitfield.disp32 = 1;
5052 break;
5053 }
5054 }
5055 break;
5056 }
5057 }
5058
5059 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5060 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5061 continue;
5062
5063 /* We check register size if needed. */
5064 check_register = t->opcode_modifier.checkregsize;
5065 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5066 switch (t->operands)
5067 {
5068 case 1:
5069 if (!operand_type_match (overlap0, i.types[0]))
5070 continue;
5071 break;
5072 case 2:
5073 /* xchg %eax, %eax is a special case. It is an alias for nop
5074 only in 32bit mode and we can use opcode 0x90. In 64bit
5075 mode, we can't use 0x90 for xchg %eax, %eax since it should
5076 zero-extend %eax to %rax. */
5077 if (flag_code == CODE_64BIT
5078 && t->base_opcode == 0x90
5079 && operand_type_equal (&i.types [0], &acc32)
5080 && operand_type_equal (&i.types [1], &acc32))
5081 continue;
5082 /* If we want store form, we reverse direction of operands. */
5083 if (i.dir_encoding == dir_encoding_store
5084 && t->opcode_modifier.d)
5085 goto check_reverse;
5086 /* Fall through. */
5087
5088 case 3:
5089 /* If we want store form, we skip the current load. */
5090 if (i.dir_encoding == dir_encoding_store
5091 && i.mem_operands == 0
5092 && t->opcode_modifier.load)
5093 continue;
5094 /* Fall through. */
5095 case 4:
5096 case 5:
5097 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5098 if (!operand_type_match (overlap0, i.types[0])
5099 || !operand_type_match (overlap1, i.types[1])
5100 || (check_register
5101 && !operand_type_register_match (overlap0, i.types[0],
5102 operand_types[0],
5103 overlap1, i.types[1],
5104 operand_types[1])))
5105 {
5106 /* Check if other direction is valid ... */
5107 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
5108 continue;
5109
5110 check_reverse:
5111 /* Try reversing direction of operands. */
5112 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5113 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5114 if (!operand_type_match (overlap0, i.types[0])
5115 || !operand_type_match (overlap1, i.types[1])
5116 || (check_register
5117 && !operand_type_register_match (overlap0,
5118 i.types[0],
5119 operand_types[1],
5120 overlap1,
5121 i.types[1],
5122 operand_types[0])))
5123 {
5124 /* Does not match either direction. */
5125 continue;
5126 }
5127 /* found_reverse_match holds which of D or FloatDR
5128 we've found. */
5129 if (t->opcode_modifier.d)
5130 found_reverse_match = Opcode_D;
5131 else if (t->opcode_modifier.floatd)
5132 found_reverse_match = Opcode_FloatD;
5133 else
5134 found_reverse_match = 0;
5135 if (t->opcode_modifier.floatr)
5136 found_reverse_match |= Opcode_FloatR;
5137 }
5138 else
5139 {
5140 /* Found a forward 2 operand match here. */
5141 switch (t->operands)
5142 {
5143 case 5:
5144 overlap4 = operand_type_and (i.types[4],
5145 operand_types[4]);
5146 /* Fall through. */
5147 case 4:
5148 overlap3 = operand_type_and (i.types[3],
5149 operand_types[3]);
5150 /* Fall through. */
5151 case 3:
5152 overlap2 = operand_type_and (i.types[2],
5153 operand_types[2]);
5154 break;
5155 }
5156
5157 switch (t->operands)
5158 {
5159 case 5:
5160 if (!operand_type_match (overlap4, i.types[4])
5161 || !operand_type_register_match (overlap3,
5162 i.types[3],
5163 operand_types[3],
5164 overlap4,
5165 i.types[4],
5166 operand_types[4]))
5167 continue;
5168 /* Fall through. */
5169 case 4:
5170 if (!operand_type_match (overlap3, i.types[3])
5171 || (check_register
5172 && !operand_type_register_match (overlap2,
5173 i.types[2],
5174 operand_types[2],
5175 overlap3,
5176 i.types[3],
5177 operand_types[3])))
5178 continue;
5179 /* Fall through. */
5180 case 3:
5181 /* Here we make use of the fact that there are no
5182 reverse match 3 operand instructions, and all 3
5183 operand instructions only need to be checked for
5184 register consistency between operands 2 and 3. */
5185 if (!operand_type_match (overlap2, i.types[2])
5186 || (check_register
5187 && !operand_type_register_match (overlap1,
5188 i.types[1],
5189 operand_types[1],
5190 overlap2,
5191 i.types[2],
5192 operand_types[2])))
5193 continue;
5194 break;
5195 }
5196 }
5197 /* Found either forward/reverse 2, 3 or 4 operand match here:
5198 slip through to break. */
5199 }
5200 if (!found_cpu_match)
5201 {
5202 found_reverse_match = 0;
5203 continue;
5204 }
5205
5206 /* Check if vector and VEX operands are valid. */
5207 if (check_VecOperands (t) || VEX_check_operands (t))
5208 {
5209 specific_error = i.error;
5210 continue;
5211 }
5212
5213 /* We've found a match; break out of loop. */
5214 break;
5215 }
5216
5217 if (t == current_templates->end)
5218 {
5219 /* We found no match. */
5220 const char *err_msg;
5221 switch (specific_error ? specific_error : i.error)
5222 {
5223 default:
5224 abort ();
5225 case operand_size_mismatch:
5226 err_msg = _("operand size mismatch");
5227 break;
5228 case operand_type_mismatch:
5229 err_msg = _("operand type mismatch");
5230 break;
5231 case register_type_mismatch:
5232 err_msg = _("register type mismatch");
5233 break;
5234 case number_of_operands_mismatch:
5235 err_msg = _("number of operands mismatch");
5236 break;
5237 case invalid_instruction_suffix:
5238 err_msg = _("invalid instruction suffix");
5239 break;
5240 case bad_imm4:
5241 err_msg = _("constant doesn't fit in 4 bits");
5242 break;
5243 case old_gcc_only:
5244 err_msg = _("only supported with old gcc");
5245 break;
5246 case unsupported_with_intel_mnemonic:
5247 err_msg = _("unsupported with Intel mnemonic");
5248 break;
5249 case unsupported_syntax:
5250 err_msg = _("unsupported syntax");
5251 break;
5252 case unsupported:
5253 as_bad (_("unsupported instruction `%s'"),
5254 current_templates->start->name);
5255 return NULL;
5256 case invalid_vsib_address:
5257 err_msg = _("invalid VSIB address");
5258 break;
5259 case invalid_vector_register_set:
5260 err_msg = _("mask, index, and destination registers must be distinct");
5261 break;
5262 case unsupported_vector_index_register:
5263 err_msg = _("unsupported vector index register");
5264 break;
5265 case unsupported_broadcast:
5266 err_msg = _("unsupported broadcast");
5267 break;
5268 case broadcast_not_on_src_operand:
5269 err_msg = _("broadcast not on source memory operand");
5270 break;
5271 case broadcast_needed:
5272 err_msg = _("broadcast is needed for operand of such type");
5273 break;
5274 case unsupported_masking:
5275 err_msg = _("unsupported masking");
5276 break;
5277 case mask_not_on_destination:
5278 err_msg = _("mask not on destination operand");
5279 break;
5280 case no_default_mask:
5281 err_msg = _("default mask isn't allowed");
5282 break;
5283 case unsupported_rc_sae:
5284 err_msg = _("unsupported static rounding/sae");
5285 break;
5286 case rc_sae_operand_not_last_imm:
5287 if (intel_syntax)
5288 err_msg = _("RC/SAE operand must precede immediate operands");
5289 else
5290 err_msg = _("RC/SAE operand must follow immediate operands");
5291 break;
5292 case invalid_register_operand:
5293 err_msg = _("invalid register operand");
5294 break;
5295 }
5296 as_bad (_("%s for `%s'"), err_msg,
5297 current_templates->start->name);
5298 return NULL;
5299 }
5300
5301 if (!quiet_warnings)
5302 {
5303 if (!intel_syntax
5304 && (i.types[0].bitfield.jumpabsolute
5305 != operand_types[0].bitfield.jumpabsolute))
5306 {
5307 as_warn (_("indirect %s without `*'"), t->name);
5308 }
5309
5310 if (t->opcode_modifier.isprefix
5311 && t->opcode_modifier.ignoresize)
5312 {
5313 /* Warn them that a data or address size prefix doesn't
5314 affect assembly of the next line of code. */
5315 as_warn (_("stand-alone `%s' prefix"), t->name);
5316 }
5317 }
5318
5319 /* Copy the template we found. */
5320 i.tm = *t;
5321
5322 if (addr_prefix_disp != -1)
5323 i.tm.operand_types[addr_prefix_disp]
5324 = operand_types[addr_prefix_disp];
5325
5326 if (found_reverse_match)
5327 {
5328 /* If we found a reverse match we must alter the opcode
5329 direction bit. found_reverse_match holds bits to change
5330 (different for int & float insns). */
5331
5332 i.tm.base_opcode ^= found_reverse_match;
5333
5334 i.tm.operand_types[0] = operand_types[1];
5335 i.tm.operand_types[1] = operand_types[0];
5336 }
5337
5338 return t;
5339 }
5340
5341 static int
5342 check_string (void)
5343 {
5344 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5345 if (i.tm.operand_types[mem_op].bitfield.esseg)
5346 {
5347 if (i.seg[0] != NULL && i.seg[0] != &es)
5348 {
5349 as_bad (_("`%s' operand %d must use `%ses' segment"),
5350 i.tm.name,
5351 mem_op + 1,
5352 register_prefix);
5353 return 0;
5354 }
5355 /* There's only ever one segment override allowed per instruction.
5356 This instruction possibly has a legal segment override on the
5357 second operand, so copy the segment to where non-string
5358 instructions store it, allowing common code. */
5359 i.seg[0] = i.seg[1];
5360 }
5361 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5362 {
5363 if (i.seg[1] != NULL && i.seg[1] != &es)
5364 {
5365 as_bad (_("`%s' operand %d must use `%ses' segment"),
5366 i.tm.name,
5367 mem_op + 2,
5368 register_prefix);
5369 return 0;
5370 }
5371 }
5372 return 1;
5373 }
5374
5375 static int
5376 process_suffix (void)
5377 {
5378 /* If matched instruction specifies an explicit instruction mnemonic
5379 suffix, use it. */
5380 if (i.tm.opcode_modifier.size16)
5381 i.suffix = WORD_MNEM_SUFFIX;
5382 else if (i.tm.opcode_modifier.size32)
5383 i.suffix = LONG_MNEM_SUFFIX;
5384 else if (i.tm.opcode_modifier.size64)
5385 i.suffix = QWORD_MNEM_SUFFIX;
5386 else if (i.reg_operands)
5387 {
5388 /* If there's no instruction mnemonic suffix we try to invent one
5389 based on register operands. */
5390 if (!i.suffix)
5391 {
5392 /* We take i.suffix from the last register operand specified,
5393 Destination register type is more significant than source
5394 register type. crc32 in SSE4.2 prefers source register
5395 type. */
5396 if (i.tm.base_opcode == 0xf20f38f1)
5397 {
5398 if (i.types[0].bitfield.reg16)
5399 i.suffix = WORD_MNEM_SUFFIX;
5400 else if (i.types[0].bitfield.reg32)
5401 i.suffix = LONG_MNEM_SUFFIX;
5402 else if (i.types[0].bitfield.reg64)
5403 i.suffix = QWORD_MNEM_SUFFIX;
5404 }
5405 else if (i.tm.base_opcode == 0xf20f38f0)
5406 {
5407 if (i.types[0].bitfield.reg8)
5408 i.suffix = BYTE_MNEM_SUFFIX;
5409 }
5410
5411 if (!i.suffix)
5412 {
5413 int op;
5414
5415 if (i.tm.base_opcode == 0xf20f38f1
5416 || i.tm.base_opcode == 0xf20f38f0)
5417 {
5418 /* We have to know the operand size for crc32. */
5419 as_bad (_("ambiguous memory operand size for `%s`"),
5420 i.tm.name);
5421 return 0;
5422 }
5423
5424 for (op = i.operands; --op >= 0;)
5425 if (!i.tm.operand_types[op].bitfield.inoutportreg)
5426 {
5427 if (i.types[op].bitfield.reg8)
5428 {
5429 i.suffix = BYTE_MNEM_SUFFIX;
5430 break;
5431 }
5432 else if (i.types[op].bitfield.reg16)
5433 {
5434 i.suffix = WORD_MNEM_SUFFIX;
5435 break;
5436 }
5437 else if (i.types[op].bitfield.reg32)
5438 {
5439 i.suffix = LONG_MNEM_SUFFIX;
5440 break;
5441 }
5442 else if (i.types[op].bitfield.reg64)
5443 {
5444 i.suffix = QWORD_MNEM_SUFFIX;
5445 break;
5446 }
5447 }
5448 }
5449 }
5450 else if (i.suffix == BYTE_MNEM_SUFFIX)
5451 {
5452 if (intel_syntax
5453 && i.tm.opcode_modifier.ignoresize
5454 && i.tm.opcode_modifier.no_bsuf)
5455 i.suffix = 0;
5456 else if (!check_byte_reg ())
5457 return 0;
5458 }
5459 else if (i.suffix == LONG_MNEM_SUFFIX)
5460 {
5461 if (intel_syntax
5462 && i.tm.opcode_modifier.ignoresize
5463 && i.tm.opcode_modifier.no_lsuf)
5464 i.suffix = 0;
5465 else if (!check_long_reg ())
5466 return 0;
5467 }
5468 else if (i.suffix == QWORD_MNEM_SUFFIX)
5469 {
5470 if (intel_syntax
5471 && i.tm.opcode_modifier.ignoresize
5472 && i.tm.opcode_modifier.no_qsuf)
5473 i.suffix = 0;
5474 else if (!check_qword_reg ())
5475 return 0;
5476 }
5477 else if (i.suffix == WORD_MNEM_SUFFIX)
5478 {
5479 if (intel_syntax
5480 && i.tm.opcode_modifier.ignoresize
5481 && i.tm.opcode_modifier.no_wsuf)
5482 i.suffix = 0;
5483 else if (!check_word_reg ())
5484 return 0;
5485 }
5486 else if (i.suffix == XMMWORD_MNEM_SUFFIX
5487 || i.suffix == YMMWORD_MNEM_SUFFIX
5488 || i.suffix == ZMMWORD_MNEM_SUFFIX)
5489 {
5490 /* Skip if the instruction has x/y/z suffix. match_template
5491 should check if it is a valid suffix. */
5492 }
5493 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5494 /* Do nothing if the instruction is going to ignore the prefix. */
5495 ;
5496 else
5497 abort ();
5498 }
5499 else if (i.tm.opcode_modifier.defaultsize
5500 && !i.suffix
5501 /* exclude fldenv/frstor/fsave/fstenv */
5502 && i.tm.opcode_modifier.no_ssuf)
5503 {
5504 i.suffix = stackop_size;
5505 }
5506 else if (intel_syntax
5507 && !i.suffix
5508 && (i.tm.operand_types[0].bitfield.jumpabsolute
5509 || i.tm.opcode_modifier.jumpbyte
5510 || i.tm.opcode_modifier.jumpintersegment
5511 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5512 && i.tm.extension_opcode <= 3)))
5513 {
5514 switch (flag_code)
5515 {
5516 case CODE_64BIT:
5517 if (!i.tm.opcode_modifier.no_qsuf)
5518 {
5519 i.suffix = QWORD_MNEM_SUFFIX;
5520 break;
5521 }
5522 /* Fall through. */
5523 case CODE_32BIT:
5524 if (!i.tm.opcode_modifier.no_lsuf)
5525 i.suffix = LONG_MNEM_SUFFIX;
5526 break;
5527 case CODE_16BIT:
5528 if (!i.tm.opcode_modifier.no_wsuf)
5529 i.suffix = WORD_MNEM_SUFFIX;
5530 break;
5531 }
5532 }
5533
5534 if (!i.suffix)
5535 {
5536 if (!intel_syntax)
5537 {
5538 if (i.tm.opcode_modifier.w)
5539 {
5540 as_bad (_("no instruction mnemonic suffix given and "
5541 "no register operands; can't size instruction"));
5542 return 0;
5543 }
5544 }
5545 else
5546 {
5547 unsigned int suffixes;
5548
5549 suffixes = !i.tm.opcode_modifier.no_bsuf;
5550 if (!i.tm.opcode_modifier.no_wsuf)
5551 suffixes |= 1 << 1;
5552 if (!i.tm.opcode_modifier.no_lsuf)
5553 suffixes |= 1 << 2;
5554 if (!i.tm.opcode_modifier.no_ldsuf)
5555 suffixes |= 1 << 3;
5556 if (!i.tm.opcode_modifier.no_ssuf)
5557 suffixes |= 1 << 4;
5558 if (!i.tm.opcode_modifier.no_qsuf)
5559 suffixes |= 1 << 5;
5560
5561 /* There are more than suffix matches. */
5562 if (i.tm.opcode_modifier.w
5563 || ((suffixes & (suffixes - 1))
5564 && !i.tm.opcode_modifier.defaultsize
5565 && !i.tm.opcode_modifier.ignoresize))
5566 {
5567 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5568 return 0;
5569 }
5570 }
5571 }
5572
5573 /* Change the opcode based on the operand size given by i.suffix;
5574 We don't need to change things for byte insns. */
5575
5576 if (i.suffix
5577 && i.suffix != BYTE_MNEM_SUFFIX
5578 && i.suffix != XMMWORD_MNEM_SUFFIX
5579 && i.suffix != YMMWORD_MNEM_SUFFIX
5580 && i.suffix != ZMMWORD_MNEM_SUFFIX)
5581 {
5582 /* It's not a byte, select word/dword operation. */
5583 if (i.tm.opcode_modifier.w)
5584 {
5585 if (i.tm.opcode_modifier.shortform)
5586 i.tm.base_opcode |= 8;
5587 else
5588 i.tm.base_opcode |= 1;
5589 }
5590
5591 /* Now select between word & dword operations via the operand
5592 size prefix, except for instructions that will ignore this
5593 prefix anyway. */
5594 if (i.tm.opcode_modifier.addrprefixop0)
5595 {
5596 /* The address size override prefix changes the size of the
5597 first operand. */
5598 if ((flag_code == CODE_32BIT
5599 && i.op->regs[0].reg_type.bitfield.reg16)
5600 || (flag_code != CODE_32BIT
5601 && i.op->regs[0].reg_type.bitfield.reg32))
5602 if (!add_prefix (ADDR_PREFIX_OPCODE))
5603 return 0;
5604 }
5605 else if (i.suffix != QWORD_MNEM_SUFFIX
5606 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
5607 && !i.tm.opcode_modifier.ignoresize
5608 && !i.tm.opcode_modifier.floatmf
5609 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5610 || (flag_code == CODE_64BIT
5611 && i.tm.opcode_modifier.jumpbyte)))
5612 {
5613 unsigned int prefix = DATA_PREFIX_OPCODE;
5614
5615 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5616 prefix = ADDR_PREFIX_OPCODE;
5617
5618 if (!add_prefix (prefix))
5619 return 0;
5620 }
5621
5622 /* Set mode64 for an operand. */
5623 if (i.suffix == QWORD_MNEM_SUFFIX
5624 && flag_code == CODE_64BIT
5625 && !i.tm.opcode_modifier.norex64)
5626 {
5627 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5628 need rex64. cmpxchg8b is also a special case. */
5629 if (! (i.operands == 2
5630 && i.tm.base_opcode == 0x90
5631 && i.tm.extension_opcode == None
5632 && operand_type_equal (&i.types [0], &acc64)
5633 && operand_type_equal (&i.types [1], &acc64))
5634 && ! (i.operands == 1
5635 && i.tm.base_opcode == 0xfc7
5636 && i.tm.extension_opcode == 1
5637 && !operand_type_check (i.types [0], reg)
5638 && operand_type_check (i.types [0], anymem)))
5639 i.rex |= REX_W;
5640 }
5641
5642 /* Size floating point instruction. */
5643 if (i.suffix == LONG_MNEM_SUFFIX)
5644 if (i.tm.opcode_modifier.floatmf)
5645 i.tm.base_opcode ^= 4;
5646 }
5647
5648 return 1;
5649 }
5650
5651 static int
5652 check_byte_reg (void)
5653 {
5654 int op;
5655
5656 for (op = i.operands; --op >= 0;)
5657 {
5658 /* If this is an eight bit register, it's OK. If it's the 16 or
5659 32 bit version of an eight bit register, we will just use the
5660 low portion, and that's OK too. */
5661 if (i.types[op].bitfield.reg8)
5662 continue;
5663
5664 /* I/O port address operands are OK too. */
5665 if (i.tm.operand_types[op].bitfield.inoutportreg)
5666 continue;
5667
5668 /* crc32 doesn't generate this warning. */
5669 if (i.tm.base_opcode == 0xf20f38f0)
5670 continue;
5671
5672 if ((i.types[op].bitfield.reg16
5673 || i.types[op].bitfield.reg32
5674 || i.types[op].bitfield.reg64)
5675 && i.op[op].regs->reg_num < 4
5676 /* Prohibit these changes in 64bit mode, since the lowering
5677 would be more complicated. */
5678 && flag_code != CODE_64BIT)
5679 {
5680 #if REGISTER_WARNINGS
5681 if (!quiet_warnings)
5682 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5683 register_prefix,
5684 (i.op[op].regs + (i.types[op].bitfield.reg16
5685 ? REGNAM_AL - REGNAM_AX
5686 : REGNAM_AL - REGNAM_EAX))->reg_name,
5687 register_prefix,
5688 i.op[op].regs->reg_name,
5689 i.suffix);
5690 #endif
5691 continue;
5692 }
5693 /* Any other register is bad. */
5694 if (i.types[op].bitfield.reg16
5695 || i.types[op].bitfield.reg32
5696 || i.types[op].bitfield.reg64
5697 || i.types[op].bitfield.regmmx
5698 || i.types[op].bitfield.regxmm
5699 || i.types[op].bitfield.regymm
5700 || i.types[op].bitfield.regzmm
5701 || i.types[op].bitfield.sreg2
5702 || i.types[op].bitfield.sreg3
5703 || i.types[op].bitfield.control
5704 || i.types[op].bitfield.debug
5705 || i.types[op].bitfield.test
5706 || i.types[op].bitfield.floatreg
5707 || i.types[op].bitfield.floatacc)
5708 {
5709 as_bad (_("`%s%s' not allowed with `%s%c'"),
5710 register_prefix,
5711 i.op[op].regs->reg_name,
5712 i.tm.name,
5713 i.suffix);
5714 return 0;
5715 }
5716 }
5717 return 1;
5718 }
5719
5720 static int
5721 check_long_reg (void)
5722 {
5723 int op;
5724
5725 for (op = i.operands; --op >= 0;)
5726 /* Reject eight bit registers, except where the template requires
5727 them. (eg. movzb) */
5728 if (i.types[op].bitfield.reg8
5729 && (i.tm.operand_types[op].bitfield.reg16
5730 || i.tm.operand_types[op].bitfield.reg32
5731 || i.tm.operand_types[op].bitfield.acc))
5732 {
5733 as_bad (_("`%s%s' not allowed with `%s%c'"),
5734 register_prefix,
5735 i.op[op].regs->reg_name,
5736 i.tm.name,
5737 i.suffix);
5738 return 0;
5739 }
5740 /* Warn if the e prefix on a general reg is missing. */
5741 else if ((!quiet_warnings || flag_code == CODE_64BIT)
5742 && i.types[op].bitfield.reg16
5743 && (i.tm.operand_types[op].bitfield.reg32
5744 || i.tm.operand_types[op].bitfield.acc))
5745 {
5746 /* Prohibit these changes in the 64bit mode, since the
5747 lowering is more complicated. */
5748 if (flag_code == CODE_64BIT)
5749 {
5750 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5751 register_prefix, i.op[op].regs->reg_name,
5752 i.suffix);
5753 return 0;
5754 }
5755 #if REGISTER_WARNINGS
5756 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5757 register_prefix,
5758 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5759 register_prefix, i.op[op].regs->reg_name, i.suffix);
5760 #endif
5761 }
5762 /* Warn if the r prefix on a general reg is present. */
5763 else if (i.types[op].bitfield.reg64
5764 && (i.tm.operand_types[op].bitfield.reg32
5765 || i.tm.operand_types[op].bitfield.acc))
5766 {
5767 if (intel_syntax
5768 && i.tm.opcode_modifier.toqword
5769 && !i.types[0].bitfield.regxmm)
5770 {
5771 /* Convert to QWORD. We want REX byte. */
5772 i.suffix = QWORD_MNEM_SUFFIX;
5773 }
5774 else
5775 {
5776 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5777 register_prefix, i.op[op].regs->reg_name,
5778 i.suffix);
5779 return 0;
5780 }
5781 }
5782 return 1;
5783 }
5784
5785 static int
5786 check_qword_reg (void)
5787 {
5788 int op;
5789
5790 for (op = i.operands; --op >= 0; )
5791 /* Reject eight bit registers, except where the template requires
5792 them. (eg. movzb) */
5793 if (i.types[op].bitfield.reg8
5794 && (i.tm.operand_types[op].bitfield.reg16
5795 || i.tm.operand_types[op].bitfield.reg32
5796 || i.tm.operand_types[op].bitfield.acc))
5797 {
5798 as_bad (_("`%s%s' not allowed with `%s%c'"),
5799 register_prefix,
5800 i.op[op].regs->reg_name,
5801 i.tm.name,
5802 i.suffix);
5803 return 0;
5804 }
5805 /* Warn if the r prefix on a general reg is missing. */
5806 else if ((i.types[op].bitfield.reg16
5807 || i.types[op].bitfield.reg32)
5808 && (i.tm.operand_types[op].bitfield.reg64
5809 || i.tm.operand_types[op].bitfield.acc))
5810 {
5811 /* Prohibit these changes in the 64bit mode, since the
5812 lowering is more complicated. */
5813 if (intel_syntax
5814 && i.tm.opcode_modifier.todword
5815 && !i.types[0].bitfield.regxmm)
5816 {
5817 /* Convert to DWORD. We don't want REX byte. */
5818 i.suffix = LONG_MNEM_SUFFIX;
5819 }
5820 else
5821 {
5822 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5823 register_prefix, i.op[op].regs->reg_name,
5824 i.suffix);
5825 return 0;
5826 }
5827 }
5828 return 1;
5829 }
5830
5831 static int
5832 check_word_reg (void)
5833 {
5834 int op;
5835 for (op = i.operands; --op >= 0;)
5836 /* Reject eight bit registers, except where the template requires
5837 them. (eg. movzb) */
5838 if (i.types[op].bitfield.reg8
5839 && (i.tm.operand_types[op].bitfield.reg16
5840 || i.tm.operand_types[op].bitfield.reg32
5841 || i.tm.operand_types[op].bitfield.acc))
5842 {
5843 as_bad (_("`%s%s' not allowed with `%s%c'"),
5844 register_prefix,
5845 i.op[op].regs->reg_name,
5846 i.tm.name,
5847 i.suffix);
5848 return 0;
5849 }
5850 /* Warn if the e or r prefix on a general reg is present. */
5851 else if ((!quiet_warnings || flag_code == CODE_64BIT)
5852 && (i.types[op].bitfield.reg32
5853 || i.types[op].bitfield.reg64)
5854 && (i.tm.operand_types[op].bitfield.reg16
5855 || i.tm.operand_types[op].bitfield.acc))
5856 {
5857 /* Prohibit these changes in the 64bit mode, since the
5858 lowering is more complicated. */
5859 if (flag_code == CODE_64BIT)
5860 {
5861 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5862 register_prefix, i.op[op].regs->reg_name,
5863 i.suffix);
5864 return 0;
5865 }
5866 #if REGISTER_WARNINGS
5867 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5868 register_prefix,
5869 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5870 register_prefix, i.op[op].regs->reg_name, i.suffix);
5871 #endif
5872 }
5873 return 1;
5874 }
5875
5876 static int
5877 update_imm (unsigned int j)
5878 {
5879 i386_operand_type overlap = i.types[j];
5880 if ((overlap.bitfield.imm8
5881 || overlap.bitfield.imm8s
5882 || overlap.bitfield.imm16
5883 || overlap.bitfield.imm32
5884 || overlap.bitfield.imm32s
5885 || overlap.bitfield.imm64)
5886 && !operand_type_equal (&overlap, &imm8)
5887 && !operand_type_equal (&overlap, &imm8s)
5888 && !operand_type_equal (&overlap, &imm16)
5889 && !operand_type_equal (&overlap, &imm32)
5890 && !operand_type_equal (&overlap, &imm32s)
5891 && !operand_type_equal (&overlap, &imm64))
5892 {
5893 if (i.suffix)
5894 {
5895 i386_operand_type temp;
5896
5897 operand_type_set (&temp, 0);
5898 if (i.suffix == BYTE_MNEM_SUFFIX)
5899 {
5900 temp.bitfield.imm8 = overlap.bitfield.imm8;
5901 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5902 }
5903 else if (i.suffix == WORD_MNEM_SUFFIX)
5904 temp.bitfield.imm16 = overlap.bitfield.imm16;
5905 else if (i.suffix == QWORD_MNEM_SUFFIX)
5906 {
5907 temp.bitfield.imm64 = overlap.bitfield.imm64;
5908 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5909 }
5910 else
5911 temp.bitfield.imm32 = overlap.bitfield.imm32;
5912 overlap = temp;
5913 }
5914 else if (operand_type_equal (&overlap, &imm16_32_32s)
5915 || operand_type_equal (&overlap, &imm16_32)
5916 || operand_type_equal (&overlap, &imm16_32s))
5917 {
5918 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
5919 overlap = imm16;
5920 else
5921 overlap = imm32s;
5922 }
5923 if (!operand_type_equal (&overlap, &imm8)
5924 && !operand_type_equal (&overlap, &imm8s)
5925 && !operand_type_equal (&overlap, &imm16)
5926 && !operand_type_equal (&overlap, &imm32)
5927 && !operand_type_equal (&overlap, &imm32s)
5928 && !operand_type_equal (&overlap, &imm64))
5929 {
5930 as_bad (_("no instruction mnemonic suffix given; "
5931 "can't determine immediate size"));
5932 return 0;
5933 }
5934 }
5935 i.types[j] = overlap;
5936
5937 return 1;
5938 }
5939
5940 static int
5941 finalize_imm (void)
5942 {
5943 unsigned int j, n;
5944
5945 /* Update the first 2 immediate operands. */
5946 n = i.operands > 2 ? 2 : i.operands;
5947 if (n)
5948 {
5949 for (j = 0; j < n; j++)
5950 if (update_imm (j) == 0)
5951 return 0;
5952
5953 /* The 3rd operand can't be immediate operand. */
5954 gas_assert (operand_type_check (i.types[2], imm) == 0);
5955 }
5956
5957 return 1;
5958 }
5959
5960 static int
5961 bad_implicit_operand (int xmm)
5962 {
5963 const char *ireg = xmm ? "xmm0" : "ymm0";
5964
5965 if (intel_syntax)
5966 as_bad (_("the last operand of `%s' must be `%s%s'"),
5967 i.tm.name, register_prefix, ireg);
5968 else
5969 as_bad (_("the first operand of `%s' must be `%s%s'"),
5970 i.tm.name, register_prefix, ireg);
5971 return 0;
5972 }
5973
5974 static int
5975 process_operands (void)
5976 {
5977 /* Default segment register this instruction will use for memory
5978 accesses. 0 means unknown. This is only for optimizing out
5979 unnecessary segment overrides. */
5980 const seg_entry *default_seg = 0;
5981
5982 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
5983 {
5984 unsigned int dupl = i.operands;
5985 unsigned int dest = dupl - 1;
5986 unsigned int j;
5987
5988 /* The destination must be an xmm register. */
5989 gas_assert (i.reg_operands
5990 && MAX_OPERANDS > dupl
5991 && operand_type_equal (&i.types[dest], &regxmm));
5992
5993 if (i.tm.opcode_modifier.firstxmm0)
5994 {
5995 /* The first operand is implicit and must be xmm0. */
5996 gas_assert (operand_type_equal (&i.types[0], &regxmm));
5997 if (register_number (i.op[0].regs) != 0)
5998 return bad_implicit_operand (1);
5999
6000 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6001 {
6002 /* Keep xmm0 for instructions with VEX prefix and 3
6003 sources. */
6004 goto duplicate;
6005 }
6006 else
6007 {
6008 /* We remove the first xmm0 and keep the number of
6009 operands unchanged, which in fact duplicates the
6010 destination. */
6011 for (j = 1; j < i.operands; j++)
6012 {
6013 i.op[j - 1] = i.op[j];
6014 i.types[j - 1] = i.types[j];
6015 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6016 }
6017 }
6018 }
6019 else if (i.tm.opcode_modifier.implicit1stxmm0)
6020 {
6021 gas_assert ((MAX_OPERANDS - 1) > dupl
6022 && (i.tm.opcode_modifier.vexsources
6023 == VEX3SOURCES));
6024
6025 /* Add the implicit xmm0 for instructions with VEX prefix
6026 and 3 sources. */
6027 for (j = i.operands; j > 0; j--)
6028 {
6029 i.op[j] = i.op[j - 1];
6030 i.types[j] = i.types[j - 1];
6031 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6032 }
6033 i.op[0].regs
6034 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6035 i.types[0] = regxmm;
6036 i.tm.operand_types[0] = regxmm;
6037
6038 i.operands += 2;
6039 i.reg_operands += 2;
6040 i.tm.operands += 2;
6041
6042 dupl++;
6043 dest++;
6044 i.op[dupl] = i.op[dest];
6045 i.types[dupl] = i.types[dest];
6046 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6047 }
6048 else
6049 {
6050 duplicate:
6051 i.operands++;
6052 i.reg_operands++;
6053 i.tm.operands++;
6054
6055 i.op[dupl] = i.op[dest];
6056 i.types[dupl] = i.types[dest];
6057 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6058 }
6059
6060 if (i.tm.opcode_modifier.immext)
6061 process_immext ();
6062 }
6063 else if (i.tm.opcode_modifier.firstxmm0)
6064 {
6065 unsigned int j;
6066
6067 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
6068 gas_assert (i.reg_operands
6069 && (operand_type_equal (&i.types[0], &regxmm)
6070 || operand_type_equal (&i.types[0], &regymm)
6071 || operand_type_equal (&i.types[0], &regzmm)));
6072 if (register_number (i.op[0].regs) != 0)
6073 return bad_implicit_operand (i.types[0].bitfield.regxmm);
6074
6075 for (j = 1; j < i.operands; j++)
6076 {
6077 i.op[j - 1] = i.op[j];
6078 i.types[j - 1] = i.types[j];
6079
6080 /* We need to adjust fields in i.tm since they are used by
6081 build_modrm_byte. */
6082 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6083 }
6084
6085 i.operands--;
6086 i.reg_operands--;
6087 i.tm.operands--;
6088 }
6089 else if (i.tm.opcode_modifier.implicitquadgroup)
6090 {
6091 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6092 gas_assert (i.operands >= 2
6093 && (operand_type_equal (&i.types[1], &regxmm)
6094 || operand_type_equal (&i.types[1], &regymm)
6095 || operand_type_equal (&i.types[1], &regzmm)));
6096 unsigned int regnum = register_number (i.op[1].regs);
6097 unsigned int first_reg_in_group = regnum & ~3;
6098 unsigned int last_reg_in_group = first_reg_in_group + 3;
6099 if (regnum != first_reg_in_group) {
6100 as_warn (_("the second source register `%s%s' implicitly denotes"
6101 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
6102 register_prefix, i.op[1].regs->reg_name,
6103 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6104 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6105 i.tm.name);
6106 }
6107 }
6108 else if (i.tm.opcode_modifier.regkludge)
6109 {
6110 /* The imul $imm, %reg instruction is converted into
6111 imul $imm, %reg, %reg, and the clr %reg instruction
6112 is converted into xor %reg, %reg. */
6113
6114 unsigned int first_reg_op;
6115
6116 if (operand_type_check (i.types[0], reg))
6117 first_reg_op = 0;
6118 else
6119 first_reg_op = 1;
6120 /* Pretend we saw the extra register operand. */
6121 gas_assert (i.reg_operands == 1
6122 && i.op[first_reg_op + 1].regs == 0);
6123 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6124 i.types[first_reg_op + 1] = i.types[first_reg_op];
6125 i.operands++;
6126 i.reg_operands++;
6127 }
6128
6129 if (i.tm.opcode_modifier.shortform)
6130 {
6131 if (i.types[0].bitfield.sreg2
6132 || i.types[0].bitfield.sreg3)
6133 {
6134 if (i.tm.base_opcode == POP_SEG_SHORT
6135 && i.op[0].regs->reg_num == 1)
6136 {
6137 as_bad (_("you can't `pop %scs'"), register_prefix);
6138 return 0;
6139 }
6140 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6141 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6142 i.rex |= REX_B;
6143 }
6144 else
6145 {
6146 /* The register or float register operand is in operand
6147 0 or 1. */
6148 unsigned int op;
6149
6150 if (i.types[0].bitfield.floatreg
6151 || operand_type_check (i.types[0], reg))
6152 op = 0;
6153 else
6154 op = 1;
6155 /* Register goes in low 3 bits of opcode. */
6156 i.tm.base_opcode |= i.op[op].regs->reg_num;
6157 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6158 i.rex |= REX_B;
6159 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6160 {
6161 /* Warn about some common errors, but press on regardless.
6162 The first case can be generated by gcc (<= 2.8.1). */
6163 if (i.operands == 2)
6164 {
6165 /* Reversed arguments on faddp, fsubp, etc. */
6166 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6167 register_prefix, i.op[!intel_syntax].regs->reg_name,
6168 register_prefix, i.op[intel_syntax].regs->reg_name);
6169 }
6170 else
6171 {
6172 /* Extraneous `l' suffix on fp insn. */
6173 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6174 register_prefix, i.op[0].regs->reg_name);
6175 }
6176 }
6177 }
6178 }
6179 else if (i.tm.opcode_modifier.modrm)
6180 {
6181 /* The opcode is completed (modulo i.tm.extension_opcode which
6182 must be put into the modrm byte). Now, we make the modrm and
6183 index base bytes based on all the info we've collected. */
6184
6185 default_seg = build_modrm_byte ();
6186 }
6187 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6188 {
6189 default_seg = &ds;
6190 }
6191 else if (i.tm.opcode_modifier.isstring)
6192 {
6193 /* For the string instructions that allow a segment override
6194 on one of their operands, the default segment is ds. */
6195 default_seg = &ds;
6196 }
6197
6198 if (i.tm.base_opcode == 0x8d /* lea */
6199 && i.seg[0]
6200 && !quiet_warnings)
6201 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6202
6203 /* If a segment was explicitly specified, and the specified segment
6204 is not the default, use an opcode prefix to select it. If we
6205 never figured out what the default segment is, then default_seg
6206 will be zero at this point, and the specified segment prefix will
6207 always be used. */
6208 if ((i.seg[0]) && (i.seg[0] != default_seg))
6209 {
6210 if (!add_prefix (i.seg[0]->seg_prefix))
6211 return 0;
6212 }
6213 return 1;
6214 }
6215
6216 static const seg_entry *
6217 build_modrm_byte (void)
6218 {
6219 const seg_entry *default_seg = 0;
6220 unsigned int source, dest;
6221 int vex_3_sources;
6222
6223 /* The first operand of instructions with VEX prefix and 3 sources
6224 must be VEX_Imm4. */
6225 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6226 if (vex_3_sources)
6227 {
6228 unsigned int nds, reg_slot;
6229 expressionS *exp;
6230
6231 if (i.tm.opcode_modifier.veximmext
6232 && i.tm.opcode_modifier.immext)
6233 {
6234 dest = i.operands - 2;
6235 gas_assert (dest == 3);
6236 }
6237 else
6238 dest = i.operands - 1;
6239 nds = dest - 1;
6240
6241 /* There are 2 kinds of instructions:
6242 1. 5 operands: 4 register operands or 3 register operands
6243 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6244 VexW0 or VexW1. The destination must be either XMM, YMM or
6245 ZMM register.
6246 2. 4 operands: 4 register operands or 3 register operands
6247 plus 1 memory operand, VexXDS, and VexImmExt */
6248 gas_assert ((i.reg_operands == 4
6249 || (i.reg_operands == 3 && i.mem_operands == 1))
6250 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6251 && (i.tm.opcode_modifier.veximmext
6252 || (i.imm_operands == 1
6253 && i.types[0].bitfield.vec_imm4
6254 && (i.tm.opcode_modifier.vexw == VEXW0
6255 || i.tm.opcode_modifier.vexw == VEXW1)
6256 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
6257 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
6258 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
6259
6260 if (i.imm_operands == 0)
6261 {
6262 /* When there is no immediate operand, generate an 8bit
6263 immediate operand to encode the first operand. */
6264 exp = &im_expressions[i.imm_operands++];
6265 i.op[i.operands].imms = exp;
6266 i.types[i.operands] = imm8;
6267 i.operands++;
6268 /* If VexW1 is set, the first operand is the source and
6269 the second operand is encoded in the immediate operand. */
6270 if (i.tm.opcode_modifier.vexw == VEXW1)
6271 {
6272 source = 0;
6273 reg_slot = 1;
6274 }
6275 else
6276 {
6277 source = 1;
6278 reg_slot = 0;
6279 }
6280
6281 /* FMA swaps REG and NDS. */
6282 if (i.tm.cpu_flags.bitfield.cpufma)
6283 {
6284 unsigned int tmp;
6285 tmp = reg_slot;
6286 reg_slot = nds;
6287 nds = tmp;
6288 }
6289
6290 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6291 &regxmm)
6292 || operand_type_equal (&i.tm.operand_types[reg_slot],
6293 &regymm)
6294 || operand_type_equal (&i.tm.operand_types[reg_slot],
6295 &regzmm));
6296 exp->X_op = O_constant;
6297 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6298 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6299 }
6300 else
6301 {
6302 unsigned int imm_slot;
6303
6304 if (i.tm.opcode_modifier.vexw == VEXW0)
6305 {
6306 /* If VexW0 is set, the third operand is the source and
6307 the second operand is encoded in the immediate
6308 operand. */
6309 source = 2;
6310 reg_slot = 1;
6311 }
6312 else
6313 {
6314 /* VexW1 is set, the second operand is the source and
6315 the third operand is encoded in the immediate
6316 operand. */
6317 source = 1;
6318 reg_slot = 2;
6319 }
6320
6321 if (i.tm.opcode_modifier.immext)
6322 {
6323 /* When ImmExt is set, the immediate byte is the last
6324 operand. */
6325 imm_slot = i.operands - 1;
6326 source--;
6327 reg_slot--;
6328 }
6329 else
6330 {
6331 imm_slot = 0;
6332
6333 /* Turn on Imm8 so that output_imm will generate it. */
6334 i.types[imm_slot].bitfield.imm8 = 1;
6335 }
6336
6337 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6338 &regxmm)
6339 || operand_type_equal (&i.tm.operand_types[reg_slot],
6340 &regymm)
6341 || operand_type_equal (&i.tm.operand_types[reg_slot],
6342 &regzmm));
6343 i.op[imm_slot].imms->X_add_number
6344 |= register_number (i.op[reg_slot].regs) << 4;
6345 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6346 }
6347
6348 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6349 || operand_type_equal (&i.tm.operand_types[nds],
6350 &regymm)
6351 || operand_type_equal (&i.tm.operand_types[nds],
6352 &regzmm));
6353 i.vex.register_specifier = i.op[nds].regs;
6354 }
6355 else
6356 source = dest = 0;
6357
6358 /* i.reg_operands MUST be the number of real register operands;
6359 implicit registers do not count. If there are 3 register
6360 operands, it must be a instruction with VexNDS. For a
6361 instruction with VexNDD, the destination register is encoded
6362 in VEX prefix. If there are 4 register operands, it must be
6363 a instruction with VEX prefix and 3 sources. */
6364 if (i.mem_operands == 0
6365 && ((i.reg_operands == 2
6366 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6367 || (i.reg_operands == 3
6368 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6369 || (i.reg_operands == 4 && vex_3_sources)))
6370 {
6371 switch (i.operands)
6372 {
6373 case 2:
6374 source = 0;
6375 break;
6376 case 3:
6377 /* When there are 3 operands, one of them may be immediate,
6378 which may be the first or the last operand. Otherwise,
6379 the first operand must be shift count register (cl) or it
6380 is an instruction with VexNDS. */
6381 gas_assert (i.imm_operands == 1
6382 || (i.imm_operands == 0
6383 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6384 || i.types[0].bitfield.shiftcount)));
6385 if (operand_type_check (i.types[0], imm)
6386 || i.types[0].bitfield.shiftcount)
6387 source = 1;
6388 else
6389 source = 0;
6390 break;
6391 case 4:
6392 /* When there are 4 operands, the first two must be 8bit
6393 immediate operands. The source operand will be the 3rd
6394 one.
6395
6396 For instructions with VexNDS, if the first operand
6397 an imm8, the source operand is the 2nd one. If the last
6398 operand is imm8, the source operand is the first one. */
6399 gas_assert ((i.imm_operands == 2
6400 && i.types[0].bitfield.imm8
6401 && i.types[1].bitfield.imm8)
6402 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6403 && i.imm_operands == 1
6404 && (i.types[0].bitfield.imm8
6405 || i.types[i.operands - 1].bitfield.imm8
6406 || i.rounding)));
6407 if (i.imm_operands == 2)
6408 source = 2;
6409 else
6410 {
6411 if (i.types[0].bitfield.imm8)
6412 source = 1;
6413 else
6414 source = 0;
6415 }
6416 break;
6417 case 5:
6418 if (i.tm.opcode_modifier.evex)
6419 {
6420 /* For EVEX instructions, when there are 5 operands, the
6421 first one must be immediate operand. If the second one
6422 is immediate operand, the source operand is the 3th
6423 one. If the last one is immediate operand, the source
6424 operand is the 2nd one. */
6425 gas_assert (i.imm_operands == 2
6426 && i.tm.opcode_modifier.sae
6427 && operand_type_check (i.types[0], imm));
6428 if (operand_type_check (i.types[1], imm))
6429 source = 2;
6430 else if (operand_type_check (i.types[4], imm))
6431 source = 1;
6432 else
6433 abort ();
6434 }
6435 break;
6436 default:
6437 abort ();
6438 }
6439
6440 if (!vex_3_sources)
6441 {
6442 dest = source + 1;
6443
6444 /* RC/SAE operand could be between DEST and SRC. That happens
6445 when one operand is GPR and the other one is XMM/YMM/ZMM
6446 register. */
6447 if (i.rounding && i.rounding->operand == (int) dest)
6448 dest++;
6449
6450 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6451 {
6452 /* For instructions with VexNDS, the register-only source
6453 operand must be 32/64bit integer, XMM, YMM or ZMM
6454 register. It is encoded in VEX prefix. We need to
6455 clear RegMem bit before calling operand_type_equal. */
6456
6457 i386_operand_type op;
6458 unsigned int vvvv;
6459
6460 /* Check register-only source operand when two source
6461 operands are swapped. */
6462 if (!i.tm.operand_types[source].bitfield.baseindex
6463 && i.tm.operand_types[dest].bitfield.baseindex)
6464 {
6465 vvvv = source;
6466 source = dest;
6467 }
6468 else
6469 vvvv = dest;
6470
6471 op = i.tm.operand_types[vvvv];
6472 op.bitfield.regmem = 0;
6473 if ((dest + 1) >= i.operands
6474 || (!op.bitfield.reg32
6475 && op.bitfield.reg64
6476 && !operand_type_equal (&op, &regxmm)
6477 && !operand_type_equal (&op, &regymm)
6478 && !operand_type_equal (&op, &regzmm)
6479 && !operand_type_equal (&op, &regmask)))
6480 abort ();
6481 i.vex.register_specifier = i.op[vvvv].regs;
6482 dest++;
6483 }
6484 }
6485
6486 i.rm.mode = 3;
6487 /* One of the register operands will be encoded in the i.tm.reg
6488 field, the other in the combined i.tm.mode and i.tm.regmem
6489 fields. If no form of this instruction supports a memory
6490 destination operand, then we assume the source operand may
6491 sometimes be a memory operand and so we need to store the
6492 destination in the i.rm.reg field. */
6493 if (!i.tm.operand_types[dest].bitfield.regmem
6494 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6495 {
6496 i.rm.reg = i.op[dest].regs->reg_num;
6497 i.rm.regmem = i.op[source].regs->reg_num;
6498 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6499 i.rex |= REX_R;
6500 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6501 i.vrex |= REX_R;
6502 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6503 i.rex |= REX_B;
6504 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6505 i.vrex |= REX_B;
6506 }
6507 else
6508 {
6509 i.rm.reg = i.op[source].regs->reg_num;
6510 i.rm.regmem = i.op[dest].regs->reg_num;
6511 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6512 i.rex |= REX_B;
6513 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6514 i.vrex |= REX_B;
6515 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6516 i.rex |= REX_R;
6517 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6518 i.vrex |= REX_R;
6519 }
6520 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6521 {
6522 if (!i.types[0].bitfield.control
6523 && !i.types[1].bitfield.control)
6524 abort ();
6525 i.rex &= ~(REX_R | REX_B);
6526 add_prefix (LOCK_PREFIX_OPCODE);
6527 }
6528 }
6529 else
6530 { /* If it's not 2 reg operands... */
6531 unsigned int mem;
6532
6533 if (i.mem_operands)
6534 {
6535 unsigned int fake_zero_displacement = 0;
6536 unsigned int op;
6537
6538 for (op = 0; op < i.operands; op++)
6539 if (operand_type_check (i.types[op], anymem))
6540 break;
6541 gas_assert (op < i.operands);
6542
6543 if (i.tm.opcode_modifier.vecsib)
6544 {
6545 if (i.index_reg->reg_num == RegEiz
6546 || i.index_reg->reg_num == RegRiz)
6547 abort ();
6548
6549 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6550 if (!i.base_reg)
6551 {
6552 i.sib.base = NO_BASE_REGISTER;
6553 i.sib.scale = i.log2_scale_factor;
6554 /* No Vec_Disp8 if there is no base. */
6555 i.types[op].bitfield.vec_disp8 = 0;
6556 i.types[op].bitfield.disp8 = 0;
6557 i.types[op].bitfield.disp16 = 0;
6558 i.types[op].bitfield.disp64 = 0;
6559 if (flag_code != CODE_64BIT)
6560 {
6561 /* Must be 32 bit */
6562 i.types[op].bitfield.disp32 = 1;
6563 i.types[op].bitfield.disp32s = 0;
6564 }
6565 else
6566 {
6567 i.types[op].bitfield.disp32 = 0;
6568 i.types[op].bitfield.disp32s = 1;
6569 }
6570 }
6571 i.sib.index = i.index_reg->reg_num;
6572 if ((i.index_reg->reg_flags & RegRex) != 0)
6573 i.rex |= REX_X;
6574 if ((i.index_reg->reg_flags & RegVRex) != 0)
6575 i.vrex |= REX_X;
6576 }
6577
6578 default_seg = &ds;
6579
6580 if (i.base_reg == 0)
6581 {
6582 i.rm.mode = 0;
6583 if (!i.disp_operands)
6584 {
6585 fake_zero_displacement = 1;
6586 /* Instructions with VSIB byte need 32bit displacement
6587 if there is no base register. */
6588 if (i.tm.opcode_modifier.vecsib)
6589 i.types[op].bitfield.disp32 = 1;
6590 }
6591 if (i.index_reg == 0)
6592 {
6593 gas_assert (!i.tm.opcode_modifier.vecsib);
6594 /* Operand is just <disp> */
6595 if (flag_code == CODE_64BIT)
6596 {
6597 /* 64bit mode overwrites the 32bit absolute
6598 addressing by RIP relative addressing and
6599 absolute addressing is encoded by one of the
6600 redundant SIB forms. */
6601 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6602 i.sib.base = NO_BASE_REGISTER;
6603 i.sib.index = NO_INDEX_REGISTER;
6604 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
6605 ? disp32s : disp32);
6606 }
6607 else if ((flag_code == CODE_16BIT)
6608 ^ (i.prefix[ADDR_PREFIX] != 0))
6609 {
6610 i.rm.regmem = NO_BASE_REGISTER_16;
6611 i.types[op] = disp16;
6612 }
6613 else
6614 {
6615 i.rm.regmem = NO_BASE_REGISTER;
6616 i.types[op] = disp32;
6617 }
6618 }
6619 else if (!i.tm.opcode_modifier.vecsib)
6620 {
6621 /* !i.base_reg && i.index_reg */
6622 if (i.index_reg->reg_num == RegEiz
6623 || i.index_reg->reg_num == RegRiz)
6624 i.sib.index = NO_INDEX_REGISTER;
6625 else
6626 i.sib.index = i.index_reg->reg_num;
6627 i.sib.base = NO_BASE_REGISTER;
6628 i.sib.scale = i.log2_scale_factor;
6629 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6630 /* No Vec_Disp8 if there is no base. */
6631 i.types[op].bitfield.vec_disp8 = 0;
6632 i.types[op].bitfield.disp8 = 0;
6633 i.types[op].bitfield.disp16 = 0;
6634 i.types[op].bitfield.disp64 = 0;
6635 if (flag_code != CODE_64BIT)
6636 {
6637 /* Must be 32 bit */
6638 i.types[op].bitfield.disp32 = 1;
6639 i.types[op].bitfield.disp32s = 0;
6640 }
6641 else
6642 {
6643 i.types[op].bitfield.disp32 = 0;
6644 i.types[op].bitfield.disp32s = 1;
6645 }
6646 if ((i.index_reg->reg_flags & RegRex) != 0)
6647 i.rex |= REX_X;
6648 }
6649 }
6650 /* RIP addressing for 64bit mode. */
6651 else if (i.base_reg->reg_num == RegRip ||
6652 i.base_reg->reg_num == RegEip)
6653 {
6654 gas_assert (!i.tm.opcode_modifier.vecsib);
6655 i.rm.regmem = NO_BASE_REGISTER;
6656 i.types[op].bitfield.disp8 = 0;
6657 i.types[op].bitfield.disp16 = 0;
6658 i.types[op].bitfield.disp32 = 0;
6659 i.types[op].bitfield.disp32s = 1;
6660 i.types[op].bitfield.disp64 = 0;
6661 i.types[op].bitfield.vec_disp8 = 0;
6662 i.flags[op] |= Operand_PCrel;
6663 if (! i.disp_operands)
6664 fake_zero_displacement = 1;
6665 }
6666 else if (i.base_reg->reg_type.bitfield.reg16)
6667 {
6668 gas_assert (!i.tm.opcode_modifier.vecsib);
6669 switch (i.base_reg->reg_num)
6670 {
6671 case 3: /* (%bx) */
6672 if (i.index_reg == 0)
6673 i.rm.regmem = 7;
6674 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6675 i.rm.regmem = i.index_reg->reg_num - 6;
6676 break;
6677 case 5: /* (%bp) */
6678 default_seg = &ss;
6679 if (i.index_reg == 0)
6680 {
6681 i.rm.regmem = 6;
6682 if (operand_type_check (i.types[op], disp) == 0)
6683 {
6684 /* fake (%bp) into 0(%bp) */
6685 if (i.tm.operand_types[op].bitfield.vec_disp8)
6686 i.types[op].bitfield.vec_disp8 = 1;
6687 else
6688 i.types[op].bitfield.disp8 = 1;
6689 fake_zero_displacement = 1;
6690 }
6691 }
6692 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6693 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6694 break;
6695 default: /* (%si) -> 4 or (%di) -> 5 */
6696 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6697 }
6698 i.rm.mode = mode_from_disp_size (i.types[op]);
6699 }
6700 else /* i.base_reg and 32/64 bit mode */
6701 {
6702 if (flag_code == CODE_64BIT
6703 && operand_type_check (i.types[op], disp))
6704 {
6705 i386_operand_type temp;
6706 operand_type_set (&temp, 0);
6707 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
6708 temp.bitfield.vec_disp8
6709 = i.types[op].bitfield.vec_disp8;
6710 i.types[op] = temp;
6711 if (i.prefix[ADDR_PREFIX] == 0)
6712 i.types[op].bitfield.disp32s = 1;
6713 else
6714 i.types[op].bitfield.disp32 = 1;
6715 }
6716
6717 if (!i.tm.opcode_modifier.vecsib)
6718 i.rm.regmem = i.base_reg->reg_num;
6719 if ((i.base_reg->reg_flags & RegRex) != 0)
6720 i.rex |= REX_B;
6721 i.sib.base = i.base_reg->reg_num;
6722 /* x86-64 ignores REX prefix bit here to avoid decoder
6723 complications. */
6724 if (!(i.base_reg->reg_flags & RegRex)
6725 && (i.base_reg->reg_num == EBP_REG_NUM
6726 || i.base_reg->reg_num == ESP_REG_NUM))
6727 default_seg = &ss;
6728 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
6729 {
6730 fake_zero_displacement = 1;
6731 if (i.tm.operand_types [op].bitfield.vec_disp8)
6732 i.types[op].bitfield.vec_disp8 = 1;
6733 else
6734 i.types[op].bitfield.disp8 = 1;
6735 }
6736 i.sib.scale = i.log2_scale_factor;
6737 if (i.index_reg == 0)
6738 {
6739 gas_assert (!i.tm.opcode_modifier.vecsib);
6740 /* <disp>(%esp) becomes two byte modrm with no index
6741 register. We've already stored the code for esp
6742 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6743 Any base register besides %esp will not use the
6744 extra modrm byte. */
6745 i.sib.index = NO_INDEX_REGISTER;
6746 }
6747 else if (!i.tm.opcode_modifier.vecsib)
6748 {
6749 if (i.index_reg->reg_num == RegEiz
6750 || i.index_reg->reg_num == RegRiz)
6751 i.sib.index = NO_INDEX_REGISTER;
6752 else
6753 i.sib.index = i.index_reg->reg_num;
6754 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6755 if ((i.index_reg->reg_flags & RegRex) != 0)
6756 i.rex |= REX_X;
6757 }
6758
6759 if (i.disp_operands
6760 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6761 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6762 i.rm.mode = 0;
6763 else
6764 {
6765 if (!fake_zero_displacement
6766 && !i.disp_operands
6767 && i.disp_encoding)
6768 {
6769 fake_zero_displacement = 1;
6770 if (i.disp_encoding == disp_encoding_8bit)
6771 i.types[op].bitfield.disp8 = 1;
6772 else
6773 i.types[op].bitfield.disp32 = 1;
6774 }
6775 i.rm.mode = mode_from_disp_size (i.types[op]);
6776 }
6777 }
6778
6779 if (fake_zero_displacement)
6780 {
6781 /* Fakes a zero displacement assuming that i.types[op]
6782 holds the correct displacement size. */
6783 expressionS *exp;
6784
6785 gas_assert (i.op[op].disps == 0);
6786 exp = &disp_expressions[i.disp_operands++];
6787 i.op[op].disps = exp;
6788 exp->X_op = O_constant;
6789 exp->X_add_number = 0;
6790 exp->X_add_symbol = (symbolS *) 0;
6791 exp->X_op_symbol = (symbolS *) 0;
6792 }
6793
6794 mem = op;
6795 }
6796 else
6797 mem = ~0;
6798
6799 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
6800 {
6801 if (operand_type_check (i.types[0], imm))
6802 i.vex.register_specifier = NULL;
6803 else
6804 {
6805 /* VEX.vvvv encodes one of the sources when the first
6806 operand is not an immediate. */
6807 if (i.tm.opcode_modifier.vexw == VEXW0)
6808 i.vex.register_specifier = i.op[0].regs;
6809 else
6810 i.vex.register_specifier = i.op[1].regs;
6811 }
6812
6813 /* Destination is a XMM register encoded in the ModRM.reg
6814 and VEX.R bit. */
6815 i.rm.reg = i.op[2].regs->reg_num;
6816 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6817 i.rex |= REX_R;
6818
6819 /* ModRM.rm and VEX.B encodes the other source. */
6820 if (!i.mem_operands)
6821 {
6822 i.rm.mode = 3;
6823
6824 if (i.tm.opcode_modifier.vexw == VEXW0)
6825 i.rm.regmem = i.op[1].regs->reg_num;
6826 else
6827 i.rm.regmem = i.op[0].regs->reg_num;
6828
6829 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6830 i.rex |= REX_B;
6831 }
6832 }
6833 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
6834 {
6835 i.vex.register_specifier = i.op[2].regs;
6836 if (!i.mem_operands)
6837 {
6838 i.rm.mode = 3;
6839 i.rm.regmem = i.op[1].regs->reg_num;
6840 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6841 i.rex |= REX_B;
6842 }
6843 }
6844 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6845 (if any) based on i.tm.extension_opcode. Again, we must be
6846 careful to make sure that segment/control/debug/test/MMX
6847 registers are coded into the i.rm.reg field. */
6848 else if (i.reg_operands)
6849 {
6850 unsigned int op;
6851 unsigned int vex_reg = ~0;
6852
6853 for (op = 0; op < i.operands; op++)
6854 if (i.types[op].bitfield.reg8
6855 || i.types[op].bitfield.reg16
6856 || i.types[op].bitfield.reg32
6857 || i.types[op].bitfield.reg64
6858 || i.types[op].bitfield.regmmx
6859 || i.types[op].bitfield.regxmm
6860 || i.types[op].bitfield.regymm
6861 || i.types[op].bitfield.regbnd
6862 || i.types[op].bitfield.regzmm
6863 || i.types[op].bitfield.regmask
6864 || i.types[op].bitfield.sreg2
6865 || i.types[op].bitfield.sreg3
6866 || i.types[op].bitfield.control
6867 || i.types[op].bitfield.debug
6868 || i.types[op].bitfield.test)
6869 break;
6870
6871 if (vex_3_sources)
6872 op = dest;
6873 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6874 {
6875 /* For instructions with VexNDS, the register-only
6876 source operand is encoded in VEX prefix. */
6877 gas_assert (mem != (unsigned int) ~0);
6878
6879 if (op > mem)
6880 {
6881 vex_reg = op++;
6882 gas_assert (op < i.operands);
6883 }
6884 else
6885 {
6886 /* Check register-only source operand when two source
6887 operands are swapped. */
6888 if (!i.tm.operand_types[op].bitfield.baseindex
6889 && i.tm.operand_types[op + 1].bitfield.baseindex)
6890 {
6891 vex_reg = op;
6892 op += 2;
6893 gas_assert (mem == (vex_reg + 1)
6894 && op < i.operands);
6895 }
6896 else
6897 {
6898 vex_reg = op + 1;
6899 gas_assert (vex_reg < i.operands);
6900 }
6901 }
6902 }
6903 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
6904 {
6905 /* For instructions with VexNDD, the register destination
6906 is encoded in VEX prefix. */
6907 if (i.mem_operands == 0)
6908 {
6909 /* There is no memory operand. */
6910 gas_assert ((op + 2) == i.operands);
6911 vex_reg = op + 1;
6912 }
6913 else
6914 {
6915 /* There are only 2 operands. */
6916 gas_assert (op < 2 && i.operands == 2);
6917 vex_reg = 1;
6918 }
6919 }
6920 else
6921 gas_assert (op < i.operands);
6922
6923 if (vex_reg != (unsigned int) ~0)
6924 {
6925 i386_operand_type *type = &i.tm.operand_types[vex_reg];
6926
6927 if (type->bitfield.reg32 != 1
6928 && type->bitfield.reg64 != 1
6929 && !operand_type_equal (type, &regxmm)
6930 && !operand_type_equal (type, &regymm)
6931 && !operand_type_equal (type, &regzmm)
6932 && !operand_type_equal (type, &regmask))
6933 abort ();
6934
6935 i.vex.register_specifier = i.op[vex_reg].regs;
6936 }
6937
6938 /* Don't set OP operand twice. */
6939 if (vex_reg != op)
6940 {
6941 /* If there is an extension opcode to put here, the
6942 register number must be put into the regmem field. */
6943 if (i.tm.extension_opcode != None)
6944 {
6945 i.rm.regmem = i.op[op].regs->reg_num;
6946 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6947 i.rex |= REX_B;
6948 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6949 i.vrex |= REX_B;
6950 }
6951 else
6952 {
6953 i.rm.reg = i.op[op].regs->reg_num;
6954 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6955 i.rex |= REX_R;
6956 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6957 i.vrex |= REX_R;
6958 }
6959 }
6960
6961 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6962 must set it to 3 to indicate this is a register operand
6963 in the regmem field. */
6964 if (!i.mem_operands)
6965 i.rm.mode = 3;
6966 }
6967
6968 /* Fill in i.rm.reg field with extension opcode (if any). */
6969 if (i.tm.extension_opcode != None)
6970 i.rm.reg = i.tm.extension_opcode;
6971 }
6972 return default_seg;
6973 }
6974
6975 static void
6976 output_branch (void)
6977 {
6978 char *p;
6979 int size;
6980 int code16;
6981 int prefix;
6982 relax_substateT subtype;
6983 symbolS *sym;
6984 offsetT off;
6985
6986 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
6987 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
6988
6989 prefix = 0;
6990 if (i.prefix[DATA_PREFIX] != 0)
6991 {
6992 prefix = 1;
6993 i.prefixes -= 1;
6994 code16 ^= CODE16;
6995 }
6996 /* Pentium4 branch hints. */
6997 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6998 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6999 {
7000 prefix++;
7001 i.prefixes--;
7002 }
7003 if (i.prefix[REX_PREFIX] != 0)
7004 {
7005 prefix++;
7006 i.prefixes--;
7007 }
7008
7009 /* BND prefixed jump. */
7010 if (i.prefix[BND_PREFIX] != 0)
7011 {
7012 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7013 i.prefixes -= 1;
7014 }
7015
7016 if (i.prefixes != 0 && !intel_syntax)
7017 as_warn (_("skipping prefixes on this instruction"));
7018
7019 /* It's always a symbol; End frag & setup for relax.
7020 Make sure there is enough room in this frag for the largest
7021 instruction we may generate in md_convert_frag. This is 2
7022 bytes for the opcode and room for the prefix and largest
7023 displacement. */
7024 frag_grow (prefix + 2 + 4);
7025 /* Prefix and 1 opcode byte go in fr_fix. */
7026 p = frag_more (prefix + 1);
7027 if (i.prefix[DATA_PREFIX] != 0)
7028 *p++ = DATA_PREFIX_OPCODE;
7029 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7030 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7031 *p++ = i.prefix[SEG_PREFIX];
7032 if (i.prefix[REX_PREFIX] != 0)
7033 *p++ = i.prefix[REX_PREFIX];
7034 *p = i.tm.base_opcode;
7035
7036 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7037 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7038 else if (cpu_arch_flags.bitfield.cpui386)
7039 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7040 else
7041 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7042 subtype |= code16;
7043
7044 sym = i.op[0].disps->X_add_symbol;
7045 off = i.op[0].disps->X_add_number;
7046
7047 if (i.op[0].disps->X_op != O_constant
7048 && i.op[0].disps->X_op != O_symbol)
7049 {
7050 /* Handle complex expressions. */
7051 sym = make_expr_symbol (i.op[0].disps);
7052 off = 0;
7053 }
7054
7055 /* 1 possible extra opcode + 4 byte displacement go in var part.
7056 Pass reloc in fr_var. */
7057 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7058 }
7059
7060 static void
7061 output_jump (void)
7062 {
7063 char *p;
7064 int size;
7065 fixS *fixP;
7066
7067 if (i.tm.opcode_modifier.jumpbyte)
7068 {
7069 /* This is a loop or jecxz type instruction. */
7070 size = 1;
7071 if (i.prefix[ADDR_PREFIX] != 0)
7072 {
7073 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7074 i.prefixes -= 1;
7075 }
7076 /* Pentium4 branch hints. */
7077 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7078 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7079 {
7080 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7081 i.prefixes--;
7082 }
7083 }
7084 else
7085 {
7086 int code16;
7087
7088 code16 = 0;
7089 if (flag_code == CODE_16BIT)
7090 code16 = CODE16;
7091
7092 if (i.prefix[DATA_PREFIX] != 0)
7093 {
7094 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7095 i.prefixes -= 1;
7096 code16 ^= CODE16;
7097 }
7098
7099 size = 4;
7100 if (code16)
7101 size = 2;
7102 }
7103
7104 if (i.prefix[REX_PREFIX] != 0)
7105 {
7106 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7107 i.prefixes -= 1;
7108 }
7109
7110 /* BND prefixed jump. */
7111 if (i.prefix[BND_PREFIX] != 0)
7112 {
7113 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7114 i.prefixes -= 1;
7115 }
7116
7117 if (i.prefixes != 0 && !intel_syntax)
7118 as_warn (_("skipping prefixes on this instruction"));
7119
7120 p = frag_more (i.tm.opcode_length + size);
7121 switch (i.tm.opcode_length)
7122 {
7123 case 2:
7124 *p++ = i.tm.base_opcode >> 8;
7125 /* Fall through. */
7126 case 1:
7127 *p++ = i.tm.base_opcode;
7128 break;
7129 default:
7130 abort ();
7131 }
7132
7133 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7134 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
7135
7136 /* All jumps handled here are signed, but don't use a signed limit
7137 check for 32 and 16 bit jumps as we want to allow wrap around at
7138 4G and 64k respectively. */
7139 if (size == 1)
7140 fixP->fx_signed = 1;
7141 }
7142
7143 static void
7144 output_interseg_jump (void)
7145 {
7146 char *p;
7147 int size;
7148 int prefix;
7149 int code16;
7150
7151 code16 = 0;
7152 if (flag_code == CODE_16BIT)
7153 code16 = CODE16;
7154
7155 prefix = 0;
7156 if (i.prefix[DATA_PREFIX] != 0)
7157 {
7158 prefix = 1;
7159 i.prefixes -= 1;
7160 code16 ^= CODE16;
7161 }
7162 if (i.prefix[REX_PREFIX] != 0)
7163 {
7164 prefix++;
7165 i.prefixes -= 1;
7166 }
7167
7168 size = 4;
7169 if (code16)
7170 size = 2;
7171
7172 if (i.prefixes != 0 && !intel_syntax)
7173 as_warn (_("skipping prefixes on this instruction"));
7174
7175 /* 1 opcode; 2 segment; offset */
7176 p = frag_more (prefix + 1 + 2 + size);
7177
7178 if (i.prefix[DATA_PREFIX] != 0)
7179 *p++ = DATA_PREFIX_OPCODE;
7180
7181 if (i.prefix[REX_PREFIX] != 0)
7182 *p++ = i.prefix[REX_PREFIX];
7183
7184 *p++ = i.tm.base_opcode;
7185 if (i.op[1].imms->X_op == O_constant)
7186 {
7187 offsetT n = i.op[1].imms->X_add_number;
7188
7189 if (size == 2
7190 && !fits_in_unsigned_word (n)
7191 && !fits_in_signed_word (n))
7192 {
7193 as_bad (_("16-bit jump out of range"));
7194 return;
7195 }
7196 md_number_to_chars (p, n, size);
7197 }
7198 else
7199 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7200 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7201 if (i.op[0].imms->X_op != O_constant)
7202 as_bad (_("can't handle non absolute segment in `%s'"),
7203 i.tm.name);
7204 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7205 }
7206
7207 static void
7208 output_insn (void)
7209 {
7210 fragS *insn_start_frag;
7211 offsetT insn_start_off;
7212
7213 /* Tie dwarf2 debug info to the address at the start of the insn.
7214 We can't do this after the insn has been output as the current
7215 frag may have been closed off. eg. by frag_var. */
7216 dwarf2_emit_insn (0);
7217
7218 insn_start_frag = frag_now;
7219 insn_start_off = frag_now_fix ();
7220
7221 /* Output jumps. */
7222 if (i.tm.opcode_modifier.jump)
7223 output_branch ();
7224 else if (i.tm.opcode_modifier.jumpbyte
7225 || i.tm.opcode_modifier.jumpdword)
7226 output_jump ();
7227 else if (i.tm.opcode_modifier.jumpintersegment)
7228 output_interseg_jump ();
7229 else
7230 {
7231 /* Output normal instructions here. */
7232 char *p;
7233 unsigned char *q;
7234 unsigned int j;
7235 unsigned int prefix;
7236
7237 if (avoid_fence
7238 && i.tm.base_opcode == 0xfae
7239 && i.operands == 1
7240 && i.imm_operands == 1
7241 && (i.op[0].imms->X_add_number == 0xe8
7242 || i.op[0].imms->X_add_number == 0xf0
7243 || i.op[0].imms->X_add_number == 0xf8))
7244 {
7245 /* Encode lfence, mfence, and sfence as
7246 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7247 offsetT val = 0x240483f0ULL;
7248 p = frag_more (5);
7249 md_number_to_chars (p, val, 5);
7250 return;
7251 }
7252
7253 /* Some processors fail on LOCK prefix. This options makes
7254 assembler ignore LOCK prefix and serves as a workaround. */
7255 if (omit_lock_prefix)
7256 {
7257 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7258 return;
7259 i.prefix[LOCK_PREFIX] = 0;
7260 }
7261
7262 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7263 don't need the explicit prefix. */
7264 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7265 {
7266 switch (i.tm.opcode_length)
7267 {
7268 case 3:
7269 if (i.tm.base_opcode & 0xff000000)
7270 {
7271 prefix = (i.tm.base_opcode >> 24) & 0xff;
7272 goto check_prefix;
7273 }
7274 break;
7275 case 2:
7276 if ((i.tm.base_opcode & 0xff0000) != 0)
7277 {
7278 prefix = (i.tm.base_opcode >> 16) & 0xff;
7279 if (i.tm.cpu_flags.bitfield.cpupadlock)
7280 {
7281 check_prefix:
7282 if (prefix != REPE_PREFIX_OPCODE
7283 || (i.prefix[REP_PREFIX]
7284 != REPE_PREFIX_OPCODE))
7285 add_prefix (prefix);
7286 }
7287 else
7288 add_prefix (prefix);
7289 }
7290 break;
7291 case 1:
7292 break;
7293 default:
7294 abort ();
7295 }
7296
7297 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7298 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7299 R_X86_64_GOTTPOFF relocation so that linker can safely
7300 perform IE->LE optimization. */
7301 if (x86_elf_abi == X86_64_X32_ABI
7302 && i.operands == 2
7303 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7304 && i.prefix[REX_PREFIX] == 0)
7305 add_prefix (REX_OPCODE);
7306 #endif
7307
7308 /* The prefix bytes. */
7309 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7310 if (*q)
7311 FRAG_APPEND_1_CHAR (*q);
7312 }
7313 else
7314 {
7315 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7316 if (*q)
7317 switch (j)
7318 {
7319 case REX_PREFIX:
7320 /* REX byte is encoded in VEX prefix. */
7321 break;
7322 case SEG_PREFIX:
7323 case ADDR_PREFIX:
7324 FRAG_APPEND_1_CHAR (*q);
7325 break;
7326 default:
7327 /* There should be no other prefixes for instructions
7328 with VEX prefix. */
7329 abort ();
7330 }
7331
7332 /* For EVEX instructions i.vrex should become 0 after
7333 build_evex_prefix. For VEX instructions upper 16 registers
7334 aren't available, so VREX should be 0. */
7335 if (i.vrex)
7336 abort ();
7337 /* Now the VEX prefix. */
7338 p = frag_more (i.vex.length);
7339 for (j = 0; j < i.vex.length; j++)
7340 p[j] = i.vex.bytes[j];
7341 }
7342
7343 /* Now the opcode; be careful about word order here! */
7344 if (i.tm.opcode_length == 1)
7345 {
7346 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7347 }
7348 else
7349 {
7350 switch (i.tm.opcode_length)
7351 {
7352 case 4:
7353 p = frag_more (4);
7354 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7355 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7356 break;
7357 case 3:
7358 p = frag_more (3);
7359 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7360 break;
7361 case 2:
7362 p = frag_more (2);
7363 break;
7364 default:
7365 abort ();
7366 break;
7367 }
7368
7369 /* Put out high byte first: can't use md_number_to_chars! */
7370 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7371 *p = i.tm.base_opcode & 0xff;
7372 }
7373
7374 /* Now the modrm byte and sib byte (if present). */
7375 if (i.tm.opcode_modifier.modrm)
7376 {
7377 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7378 | i.rm.reg << 3
7379 | i.rm.mode << 6));
7380 /* If i.rm.regmem == ESP (4)
7381 && i.rm.mode != (Register mode)
7382 && not 16 bit
7383 ==> need second modrm byte. */
7384 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7385 && i.rm.mode != 3
7386 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
7387 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7388 | i.sib.index << 3
7389 | i.sib.scale << 6));
7390 }
7391
7392 if (i.disp_operands)
7393 output_disp (insn_start_frag, insn_start_off);
7394
7395 if (i.imm_operands)
7396 output_imm (insn_start_frag, insn_start_off);
7397 }
7398
7399 #ifdef DEBUG386
7400 if (flag_debug)
7401 {
7402 pi ("" /*line*/, &i);
7403 }
7404 #endif /* DEBUG386 */
7405 }
7406
7407 /* Return the size of the displacement operand N. */
7408
7409 static int
7410 disp_size (unsigned int n)
7411 {
7412 int size = 4;
7413
7414 /* Vec_Disp8 has to be 8bit. */
7415 if (i.types[n].bitfield.vec_disp8)
7416 size = 1;
7417 else if (i.types[n].bitfield.disp64)
7418 size = 8;
7419 else if (i.types[n].bitfield.disp8)
7420 size = 1;
7421 else if (i.types[n].bitfield.disp16)
7422 size = 2;
7423 return size;
7424 }
7425
7426 /* Return the size of the immediate operand N. */
7427
7428 static int
7429 imm_size (unsigned int n)
7430 {
7431 int size = 4;
7432 if (i.types[n].bitfield.imm64)
7433 size = 8;
7434 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7435 size = 1;
7436 else if (i.types[n].bitfield.imm16)
7437 size = 2;
7438 return size;
7439 }
7440
7441 static void
7442 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7443 {
7444 char *p;
7445 unsigned int n;
7446
7447 for (n = 0; n < i.operands; n++)
7448 {
7449 if (i.types[n].bitfield.vec_disp8
7450 || operand_type_check (i.types[n], disp))
7451 {
7452 if (i.op[n].disps->X_op == O_constant)
7453 {
7454 int size = disp_size (n);
7455 offsetT val = i.op[n].disps->X_add_number;
7456
7457 if (i.types[n].bitfield.vec_disp8)
7458 val >>= i.memshift;
7459 val = offset_in_range (val, size);
7460 p = frag_more (size);
7461 md_number_to_chars (p, val, size);
7462 }
7463 else
7464 {
7465 enum bfd_reloc_code_real reloc_type;
7466 int size = disp_size (n);
7467 int sign = i.types[n].bitfield.disp32s;
7468 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7469 fixS *fixP;
7470
7471 /* We can't have 8 bit displacement here. */
7472 gas_assert (!i.types[n].bitfield.disp8);
7473
7474 /* The PC relative address is computed relative
7475 to the instruction boundary, so in case immediate
7476 fields follows, we need to adjust the value. */
7477 if (pcrel && i.imm_operands)
7478 {
7479 unsigned int n1;
7480 int sz = 0;
7481
7482 for (n1 = 0; n1 < i.operands; n1++)
7483 if (operand_type_check (i.types[n1], imm))
7484 {
7485 /* Only one immediate is allowed for PC
7486 relative address. */
7487 gas_assert (sz == 0);
7488 sz = imm_size (n1);
7489 i.op[n].disps->X_add_number -= sz;
7490 }
7491 /* We should find the immediate. */
7492 gas_assert (sz != 0);
7493 }
7494
7495 p = frag_more (size);
7496 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7497 if (GOT_symbol
7498 && GOT_symbol == i.op[n].disps->X_add_symbol
7499 && (((reloc_type == BFD_RELOC_32
7500 || reloc_type == BFD_RELOC_X86_64_32S
7501 || (reloc_type == BFD_RELOC_64
7502 && object_64bit))
7503 && (i.op[n].disps->X_op == O_symbol
7504 || (i.op[n].disps->X_op == O_add
7505 && ((symbol_get_value_expression
7506 (i.op[n].disps->X_op_symbol)->X_op)
7507 == O_subtract))))
7508 || reloc_type == BFD_RELOC_32_PCREL))
7509 {
7510 offsetT add;
7511
7512 if (insn_start_frag == frag_now)
7513 add = (p - frag_now->fr_literal) - insn_start_off;
7514 else
7515 {
7516 fragS *fr;
7517
7518 add = insn_start_frag->fr_fix - insn_start_off;
7519 for (fr = insn_start_frag->fr_next;
7520 fr && fr != frag_now; fr = fr->fr_next)
7521 add += fr->fr_fix;
7522 add += p - frag_now->fr_literal;
7523 }
7524
7525 if (!object_64bit)
7526 {
7527 reloc_type = BFD_RELOC_386_GOTPC;
7528 i.op[n].imms->X_add_number += add;
7529 }
7530 else if (reloc_type == BFD_RELOC_64)
7531 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7532 else
7533 /* Don't do the adjustment for x86-64, as there
7534 the pcrel addressing is relative to the _next_
7535 insn, and that is taken care of in other code. */
7536 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7537 }
7538 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7539 size, i.op[n].disps, pcrel,
7540 reloc_type);
7541 /* Check for "call/jmp *mem", "mov mem, %reg",
7542 "test %reg, mem" and "binop mem, %reg" where binop
7543 is one of adc, add, and, cmp, or, sbb, sub, xor
7544 instructions. Always generate R_386_GOT32X for
7545 "sym*GOT" operand in 32-bit mode. */
7546 if ((generate_relax_relocations
7547 || (!object_64bit
7548 && i.rm.mode == 0
7549 && i.rm.regmem == 5))
7550 && (i.rm.mode == 2
7551 || (i.rm.mode == 0 && i.rm.regmem == 5))
7552 && ((i.operands == 1
7553 && i.tm.base_opcode == 0xff
7554 && (i.rm.reg == 2 || i.rm.reg == 4))
7555 || (i.operands == 2
7556 && (i.tm.base_opcode == 0x8b
7557 || i.tm.base_opcode == 0x85
7558 || (i.tm.base_opcode & 0xc7) == 0x03))))
7559 {
7560 if (object_64bit)
7561 {
7562 fixP->fx_tcbit = i.rex != 0;
7563 if (i.base_reg
7564 && (i.base_reg->reg_num == RegRip
7565 || i.base_reg->reg_num == RegEip))
7566 fixP->fx_tcbit2 = 1;
7567 }
7568 else
7569 fixP->fx_tcbit2 = 1;
7570 }
7571 }
7572 }
7573 }
7574 }
7575
7576 static void
7577 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7578 {
7579 char *p;
7580 unsigned int n;
7581
7582 for (n = 0; n < i.operands; n++)
7583 {
7584 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7585 if (i.rounding && (int) n == i.rounding->operand)
7586 continue;
7587
7588 if (operand_type_check (i.types[n], imm))
7589 {
7590 if (i.op[n].imms->X_op == O_constant)
7591 {
7592 int size = imm_size (n);
7593 offsetT val;
7594
7595 val = offset_in_range (i.op[n].imms->X_add_number,
7596 size);
7597 p = frag_more (size);
7598 md_number_to_chars (p, val, size);
7599 }
7600 else
7601 {
7602 /* Not absolute_section.
7603 Need a 32-bit fixup (don't support 8bit
7604 non-absolute imms). Try to support other
7605 sizes ... */
7606 enum bfd_reloc_code_real reloc_type;
7607 int size = imm_size (n);
7608 int sign;
7609
7610 if (i.types[n].bitfield.imm32s
7611 && (i.suffix == QWORD_MNEM_SUFFIX
7612 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7613 sign = 1;
7614 else
7615 sign = 0;
7616
7617 p = frag_more (size);
7618 reloc_type = reloc (size, 0, sign, i.reloc[n]);
7619
7620 /* This is tough to explain. We end up with this one if we
7621 * have operands that look like
7622 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7623 * obtain the absolute address of the GOT, and it is strongly
7624 * preferable from a performance point of view to avoid using
7625 * a runtime relocation for this. The actual sequence of
7626 * instructions often look something like:
7627 *
7628 * call .L66
7629 * .L66:
7630 * popl %ebx
7631 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7632 *
7633 * The call and pop essentially return the absolute address
7634 * of the label .L66 and store it in %ebx. The linker itself
7635 * will ultimately change the first operand of the addl so
7636 * that %ebx points to the GOT, but to keep things simple, the
7637 * .o file must have this operand set so that it generates not
7638 * the absolute address of .L66, but the absolute address of
7639 * itself. This allows the linker itself simply treat a GOTPC
7640 * relocation as asking for a pcrel offset to the GOT to be
7641 * added in, and the addend of the relocation is stored in the
7642 * operand field for the instruction itself.
7643 *
7644 * Our job here is to fix the operand so that it would add
7645 * the correct offset so that %ebx would point to itself. The
7646 * thing that is tricky is that .-.L66 will point to the
7647 * beginning of the instruction, so we need to further modify
7648 * the operand so that it will point to itself. There are
7649 * other cases where you have something like:
7650 *
7651 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7652 *
7653 * and here no correction would be required. Internally in
7654 * the assembler we treat operands of this form as not being
7655 * pcrel since the '.' is explicitly mentioned, and I wonder
7656 * whether it would simplify matters to do it this way. Who
7657 * knows. In earlier versions of the PIC patches, the
7658 * pcrel_adjust field was used to store the correction, but
7659 * since the expression is not pcrel, I felt it would be
7660 * confusing to do it this way. */
7661
7662 if ((reloc_type == BFD_RELOC_32
7663 || reloc_type == BFD_RELOC_X86_64_32S
7664 || reloc_type == BFD_RELOC_64)
7665 && GOT_symbol
7666 && GOT_symbol == i.op[n].imms->X_add_symbol
7667 && (i.op[n].imms->X_op == O_symbol
7668 || (i.op[n].imms->X_op == O_add
7669 && ((symbol_get_value_expression
7670 (i.op[n].imms->X_op_symbol)->X_op)
7671 == O_subtract))))
7672 {
7673 offsetT add;
7674
7675 if (insn_start_frag == frag_now)
7676 add = (p - frag_now->fr_literal) - insn_start_off;
7677 else
7678 {
7679 fragS *fr;
7680
7681 add = insn_start_frag->fr_fix - insn_start_off;
7682 for (fr = insn_start_frag->fr_next;
7683 fr && fr != frag_now; fr = fr->fr_next)
7684 add += fr->fr_fix;
7685 add += p - frag_now->fr_literal;
7686 }
7687
7688 if (!object_64bit)
7689 reloc_type = BFD_RELOC_386_GOTPC;
7690 else if (size == 4)
7691 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7692 else if (size == 8)
7693 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7694 i.op[n].imms->X_add_number += add;
7695 }
7696 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7697 i.op[n].imms, 0, reloc_type);
7698 }
7699 }
7700 }
7701 }
7702 \f
7703 /* x86_cons_fix_new is called via the expression parsing code when a
7704 reloc is needed. We use this hook to get the correct .got reloc. */
7705 static int cons_sign = -1;
7706
7707 void
7708 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
7709 expressionS *exp, bfd_reloc_code_real_type r)
7710 {
7711 r = reloc (len, 0, cons_sign, r);
7712
7713 #ifdef TE_PE
7714 if (exp->X_op == O_secrel)
7715 {
7716 exp->X_op = O_symbol;
7717 r = BFD_RELOC_32_SECREL;
7718 }
7719 #endif
7720
7721 fix_new_exp (frag, off, len, exp, 0, r);
7722 }
7723
7724 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7725 purpose of the `.dc.a' internal pseudo-op. */
7726
7727 int
7728 x86_address_bytes (void)
7729 {
7730 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7731 return 4;
7732 return stdoutput->arch_info->bits_per_address / 8;
7733 }
7734
7735 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7736 || defined (LEX_AT)
7737 # define lex_got(reloc, adjust, types) NULL
7738 #else
7739 /* Parse operands of the form
7740 <symbol>@GOTOFF+<nnn>
7741 and similar .plt or .got references.
7742
7743 If we find one, set up the correct relocation in RELOC and copy the
7744 input string, minus the `@GOTOFF' into a malloc'd buffer for
7745 parsing by the calling routine. Return this buffer, and if ADJUST
7746 is non-null set it to the length of the string we removed from the
7747 input line. Otherwise return NULL. */
7748 static char *
7749 lex_got (enum bfd_reloc_code_real *rel,
7750 int *adjust,
7751 i386_operand_type *types)
7752 {
7753 /* Some of the relocations depend on the size of what field is to
7754 be relocated. But in our callers i386_immediate and i386_displacement
7755 we don't yet know the operand size (this will be set by insn
7756 matching). Hence we record the word32 relocation here,
7757 and adjust the reloc according to the real size in reloc(). */
7758 static const struct {
7759 const char *str;
7760 int len;
7761 const enum bfd_reloc_code_real rel[2];
7762 const i386_operand_type types64;
7763 } gotrel[] = {
7764 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7765 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7766 BFD_RELOC_SIZE32 },
7767 OPERAND_TYPE_IMM32_64 },
7768 #endif
7769 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7770 BFD_RELOC_X86_64_PLTOFF64 },
7771 OPERAND_TYPE_IMM64 },
7772 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7773 BFD_RELOC_X86_64_PLT32 },
7774 OPERAND_TYPE_IMM32_32S_DISP32 },
7775 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7776 BFD_RELOC_X86_64_GOTPLT64 },
7777 OPERAND_TYPE_IMM64_DISP64 },
7778 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7779 BFD_RELOC_X86_64_GOTOFF64 },
7780 OPERAND_TYPE_IMM64_DISP64 },
7781 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7782 BFD_RELOC_X86_64_GOTPCREL },
7783 OPERAND_TYPE_IMM32_32S_DISP32 },
7784 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7785 BFD_RELOC_X86_64_TLSGD },
7786 OPERAND_TYPE_IMM32_32S_DISP32 },
7787 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7788 _dummy_first_bfd_reloc_code_real },
7789 OPERAND_TYPE_NONE },
7790 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7791 BFD_RELOC_X86_64_TLSLD },
7792 OPERAND_TYPE_IMM32_32S_DISP32 },
7793 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7794 BFD_RELOC_X86_64_GOTTPOFF },
7795 OPERAND_TYPE_IMM32_32S_DISP32 },
7796 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7797 BFD_RELOC_X86_64_TPOFF32 },
7798 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7799 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7800 _dummy_first_bfd_reloc_code_real },
7801 OPERAND_TYPE_NONE },
7802 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7803 BFD_RELOC_X86_64_DTPOFF32 },
7804 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7805 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7806 _dummy_first_bfd_reloc_code_real },
7807 OPERAND_TYPE_NONE },
7808 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7809 _dummy_first_bfd_reloc_code_real },
7810 OPERAND_TYPE_NONE },
7811 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7812 BFD_RELOC_X86_64_GOT32 },
7813 OPERAND_TYPE_IMM32_32S_64_DISP32 },
7814 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7815 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
7816 OPERAND_TYPE_IMM32_32S_DISP32 },
7817 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7818 BFD_RELOC_X86_64_TLSDESC_CALL },
7819 OPERAND_TYPE_IMM32_32S_DISP32 },
7820 };
7821 char *cp;
7822 unsigned int j;
7823
7824 #if defined (OBJ_MAYBE_ELF)
7825 if (!IS_ELF)
7826 return NULL;
7827 #endif
7828
7829 for (cp = input_line_pointer; *cp != '@'; cp++)
7830 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7831 return NULL;
7832
7833 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7834 {
7835 int len = gotrel[j].len;
7836 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7837 {
7838 if (gotrel[j].rel[object_64bit] != 0)
7839 {
7840 int first, second;
7841 char *tmpbuf, *past_reloc;
7842
7843 *rel = gotrel[j].rel[object_64bit];
7844
7845 if (types)
7846 {
7847 if (flag_code != CODE_64BIT)
7848 {
7849 types->bitfield.imm32 = 1;
7850 types->bitfield.disp32 = 1;
7851 }
7852 else
7853 *types = gotrel[j].types64;
7854 }
7855
7856 if (j != 0 && GOT_symbol == NULL)
7857 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7858
7859 /* The length of the first part of our input line. */
7860 first = cp - input_line_pointer;
7861
7862 /* The second part goes from after the reloc token until
7863 (and including) an end_of_line char or comma. */
7864 past_reloc = cp + 1 + len;
7865 cp = past_reloc;
7866 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7867 ++cp;
7868 second = cp + 1 - past_reloc;
7869
7870 /* Allocate and copy string. The trailing NUL shouldn't
7871 be necessary, but be safe. */
7872 tmpbuf = XNEWVEC (char, first + second + 2);
7873 memcpy (tmpbuf, input_line_pointer, first);
7874 if (second != 0 && *past_reloc != ' ')
7875 /* Replace the relocation token with ' ', so that
7876 errors like foo@GOTOFF1 will be detected. */
7877 tmpbuf[first++] = ' ';
7878 else
7879 /* Increment length by 1 if the relocation token is
7880 removed. */
7881 len++;
7882 if (adjust)
7883 *adjust = len;
7884 memcpy (tmpbuf + first, past_reloc, second);
7885 tmpbuf[first + second] = '\0';
7886 return tmpbuf;
7887 }
7888
7889 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7890 gotrel[j].str, 1 << (5 + object_64bit));
7891 return NULL;
7892 }
7893 }
7894
7895 /* Might be a symbol version string. Don't as_bad here. */
7896 return NULL;
7897 }
7898 #endif
7899
7900 #ifdef TE_PE
7901 #ifdef lex_got
7902 #undef lex_got
7903 #endif
7904 /* Parse operands of the form
7905 <symbol>@SECREL32+<nnn>
7906
7907 If we find one, set up the correct relocation in RELOC and copy the
7908 input string, minus the `@SECREL32' into a malloc'd buffer for
7909 parsing by the calling routine. Return this buffer, and if ADJUST
7910 is non-null set it to the length of the string we removed from the
7911 input line. Otherwise return NULL.
7912
7913 This function is copied from the ELF version above adjusted for PE targets. */
7914
7915 static char *
7916 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7917 int *adjust ATTRIBUTE_UNUSED,
7918 i386_operand_type *types)
7919 {
7920 static const struct
7921 {
7922 const char *str;
7923 int len;
7924 const enum bfd_reloc_code_real rel[2];
7925 const i386_operand_type types64;
7926 }
7927 gotrel[] =
7928 {
7929 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7930 BFD_RELOC_32_SECREL },
7931 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7932 };
7933
7934 char *cp;
7935 unsigned j;
7936
7937 for (cp = input_line_pointer; *cp != '@'; cp++)
7938 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7939 return NULL;
7940
7941 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7942 {
7943 int len = gotrel[j].len;
7944
7945 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7946 {
7947 if (gotrel[j].rel[object_64bit] != 0)
7948 {
7949 int first, second;
7950 char *tmpbuf, *past_reloc;
7951
7952 *rel = gotrel[j].rel[object_64bit];
7953 if (adjust)
7954 *adjust = len;
7955
7956 if (types)
7957 {
7958 if (flag_code != CODE_64BIT)
7959 {
7960 types->bitfield.imm32 = 1;
7961 types->bitfield.disp32 = 1;
7962 }
7963 else
7964 *types = gotrel[j].types64;
7965 }
7966
7967 /* The length of the first part of our input line. */
7968 first = cp - input_line_pointer;
7969
7970 /* The second part goes from after the reloc token until
7971 (and including) an end_of_line char or comma. */
7972 past_reloc = cp + 1 + len;
7973 cp = past_reloc;
7974 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7975 ++cp;
7976 second = cp + 1 - past_reloc;
7977
7978 /* Allocate and copy string. The trailing NUL shouldn't
7979 be necessary, but be safe. */
7980 tmpbuf = XNEWVEC (char, first + second + 2);
7981 memcpy (tmpbuf, input_line_pointer, first);
7982 if (second != 0 && *past_reloc != ' ')
7983 /* Replace the relocation token with ' ', so that
7984 errors like foo@SECLREL321 will be detected. */
7985 tmpbuf[first++] = ' ';
7986 memcpy (tmpbuf + first, past_reloc, second);
7987 tmpbuf[first + second] = '\0';
7988 return tmpbuf;
7989 }
7990
7991 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7992 gotrel[j].str, 1 << (5 + object_64bit));
7993 return NULL;
7994 }
7995 }
7996
7997 /* Might be a symbol version string. Don't as_bad here. */
7998 return NULL;
7999 }
8000
8001 #endif /* TE_PE */
8002
8003 bfd_reloc_code_real_type
8004 x86_cons (expressionS *exp, int size)
8005 {
8006 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8007
8008 intel_syntax = -intel_syntax;
8009
8010 exp->X_md = 0;
8011 if (size == 4 || (object_64bit && size == 8))
8012 {
8013 /* Handle @GOTOFF and the like in an expression. */
8014 char *save;
8015 char *gotfree_input_line;
8016 int adjust = 0;
8017
8018 save = input_line_pointer;
8019 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8020 if (gotfree_input_line)
8021 input_line_pointer = gotfree_input_line;
8022
8023 expression (exp);
8024
8025 if (gotfree_input_line)
8026 {
8027 /* expression () has merrily parsed up to the end of line,
8028 or a comma - in the wrong buffer. Transfer how far
8029 input_line_pointer has moved to the right buffer. */
8030 input_line_pointer = (save
8031 + (input_line_pointer - gotfree_input_line)
8032 + adjust);
8033 free (gotfree_input_line);
8034 if (exp->X_op == O_constant
8035 || exp->X_op == O_absent
8036 || exp->X_op == O_illegal
8037 || exp->X_op == O_register
8038 || exp->X_op == O_big)
8039 {
8040 char c = *input_line_pointer;
8041 *input_line_pointer = 0;
8042 as_bad (_("missing or invalid expression `%s'"), save);
8043 *input_line_pointer = c;
8044 }
8045 }
8046 }
8047 else
8048 expression (exp);
8049
8050 intel_syntax = -intel_syntax;
8051
8052 if (intel_syntax)
8053 i386_intel_simplify (exp);
8054
8055 return got_reloc;
8056 }
8057
8058 static void
8059 signed_cons (int size)
8060 {
8061 if (flag_code == CODE_64BIT)
8062 cons_sign = 1;
8063 cons (size);
8064 cons_sign = -1;
8065 }
8066
8067 #ifdef TE_PE
8068 static void
8069 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8070 {
8071 expressionS exp;
8072
8073 do
8074 {
8075 expression (&exp);
8076 if (exp.X_op == O_symbol)
8077 exp.X_op = O_secrel;
8078
8079 emit_expr (&exp, 4);
8080 }
8081 while (*input_line_pointer++ == ',');
8082
8083 input_line_pointer--;
8084 demand_empty_rest_of_line ();
8085 }
8086 #endif
8087
8088 /* Handle Vector operations. */
8089
8090 static char *
8091 check_VecOperations (char *op_string, char *op_end)
8092 {
8093 const reg_entry *mask;
8094 const char *saved;
8095 char *end_op;
8096
8097 while (*op_string
8098 && (op_end == NULL || op_string < op_end))
8099 {
8100 saved = op_string;
8101 if (*op_string == '{')
8102 {
8103 op_string++;
8104
8105 /* Check broadcasts. */
8106 if (strncmp (op_string, "1to", 3) == 0)
8107 {
8108 int bcst_type;
8109
8110 if (i.broadcast)
8111 goto duplicated_vec_op;
8112
8113 op_string += 3;
8114 if (*op_string == '8')
8115 bcst_type = BROADCAST_1TO8;
8116 else if (*op_string == '4')
8117 bcst_type = BROADCAST_1TO4;
8118 else if (*op_string == '2')
8119 bcst_type = BROADCAST_1TO2;
8120 else if (*op_string == '1'
8121 && *(op_string+1) == '6')
8122 {
8123 bcst_type = BROADCAST_1TO16;
8124 op_string++;
8125 }
8126 else
8127 {
8128 as_bad (_("Unsupported broadcast: `%s'"), saved);
8129 return NULL;
8130 }
8131 op_string++;
8132
8133 broadcast_op.type = bcst_type;
8134 broadcast_op.operand = this_operand;
8135 i.broadcast = &broadcast_op;
8136 }
8137 /* Check masking operation. */
8138 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8139 {
8140 /* k0 can't be used for write mask. */
8141 if (mask->reg_num == 0)
8142 {
8143 as_bad (_("`%s' can't be used for write mask"),
8144 op_string);
8145 return NULL;
8146 }
8147
8148 if (!i.mask)
8149 {
8150 mask_op.mask = mask;
8151 mask_op.zeroing = 0;
8152 mask_op.operand = this_operand;
8153 i.mask = &mask_op;
8154 }
8155 else
8156 {
8157 if (i.mask->mask)
8158 goto duplicated_vec_op;
8159
8160 i.mask->mask = mask;
8161
8162 /* Only "{z}" is allowed here. No need to check
8163 zeroing mask explicitly. */
8164 if (i.mask->operand != this_operand)
8165 {
8166 as_bad (_("invalid write mask `%s'"), saved);
8167 return NULL;
8168 }
8169 }
8170
8171 op_string = end_op;
8172 }
8173 /* Check zeroing-flag for masking operation. */
8174 else if (*op_string == 'z')
8175 {
8176 if (!i.mask)
8177 {
8178 mask_op.mask = NULL;
8179 mask_op.zeroing = 1;
8180 mask_op.operand = this_operand;
8181 i.mask = &mask_op;
8182 }
8183 else
8184 {
8185 if (i.mask->zeroing)
8186 {
8187 duplicated_vec_op:
8188 as_bad (_("duplicated `%s'"), saved);
8189 return NULL;
8190 }
8191
8192 i.mask->zeroing = 1;
8193
8194 /* Only "{%k}" is allowed here. No need to check mask
8195 register explicitly. */
8196 if (i.mask->operand != this_operand)
8197 {
8198 as_bad (_("invalid zeroing-masking `%s'"),
8199 saved);
8200 return NULL;
8201 }
8202 }
8203
8204 op_string++;
8205 }
8206 else
8207 goto unknown_vec_op;
8208
8209 if (*op_string != '}')
8210 {
8211 as_bad (_("missing `}' in `%s'"), saved);
8212 return NULL;
8213 }
8214 op_string++;
8215 continue;
8216 }
8217 unknown_vec_op:
8218 /* We don't know this one. */
8219 as_bad (_("unknown vector operation: `%s'"), saved);
8220 return NULL;
8221 }
8222
8223 return op_string;
8224 }
8225
8226 static int
8227 i386_immediate (char *imm_start)
8228 {
8229 char *save_input_line_pointer;
8230 char *gotfree_input_line;
8231 segT exp_seg = 0;
8232 expressionS *exp;
8233 i386_operand_type types;
8234
8235 operand_type_set (&types, ~0);
8236
8237 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8238 {
8239 as_bad (_("at most %d immediate operands are allowed"),
8240 MAX_IMMEDIATE_OPERANDS);
8241 return 0;
8242 }
8243
8244 exp = &im_expressions[i.imm_operands++];
8245 i.op[this_operand].imms = exp;
8246
8247 if (is_space_char (*imm_start))
8248 ++imm_start;
8249
8250 save_input_line_pointer = input_line_pointer;
8251 input_line_pointer = imm_start;
8252
8253 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8254 if (gotfree_input_line)
8255 input_line_pointer = gotfree_input_line;
8256
8257 exp_seg = expression (exp);
8258
8259 SKIP_WHITESPACE ();
8260
8261 /* Handle vector operations. */
8262 if (*input_line_pointer == '{')
8263 {
8264 input_line_pointer = check_VecOperations (input_line_pointer,
8265 NULL);
8266 if (input_line_pointer == NULL)
8267 return 0;
8268 }
8269
8270 if (*input_line_pointer)
8271 as_bad (_("junk `%s' after expression"), input_line_pointer);
8272
8273 input_line_pointer = save_input_line_pointer;
8274 if (gotfree_input_line)
8275 {
8276 free (gotfree_input_line);
8277
8278 if (exp->X_op == O_constant || exp->X_op == O_register)
8279 exp->X_op = O_illegal;
8280 }
8281
8282 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8283 }
8284
8285 static int
8286 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8287 i386_operand_type types, const char *imm_start)
8288 {
8289 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8290 {
8291 if (imm_start)
8292 as_bad (_("missing or invalid immediate expression `%s'"),
8293 imm_start);
8294 return 0;
8295 }
8296 else if (exp->X_op == O_constant)
8297 {
8298 /* Size it properly later. */
8299 i.types[this_operand].bitfield.imm64 = 1;
8300 /* If not 64bit, sign extend val. */
8301 if (flag_code != CODE_64BIT
8302 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8303 exp->X_add_number
8304 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8305 }
8306 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8307 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8308 && exp_seg != absolute_section
8309 && exp_seg != text_section
8310 && exp_seg != data_section
8311 && exp_seg != bss_section
8312 && exp_seg != undefined_section
8313 && !bfd_is_com_section (exp_seg))
8314 {
8315 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8316 return 0;
8317 }
8318 #endif
8319 else if (!intel_syntax && exp_seg == reg_section)
8320 {
8321 if (imm_start)
8322 as_bad (_("illegal immediate register operand %s"), imm_start);
8323 return 0;
8324 }
8325 else
8326 {
8327 /* This is an address. The size of the address will be
8328 determined later, depending on destination register,
8329 suffix, or the default for the section. */
8330 i.types[this_operand].bitfield.imm8 = 1;
8331 i.types[this_operand].bitfield.imm16 = 1;
8332 i.types[this_operand].bitfield.imm32 = 1;
8333 i.types[this_operand].bitfield.imm32s = 1;
8334 i.types[this_operand].bitfield.imm64 = 1;
8335 i.types[this_operand] = operand_type_and (i.types[this_operand],
8336 types);
8337 }
8338
8339 return 1;
8340 }
8341
8342 static char *
8343 i386_scale (char *scale)
8344 {
8345 offsetT val;
8346 char *save = input_line_pointer;
8347
8348 input_line_pointer = scale;
8349 val = get_absolute_expression ();
8350
8351 switch (val)
8352 {
8353 case 1:
8354 i.log2_scale_factor = 0;
8355 break;
8356 case 2:
8357 i.log2_scale_factor = 1;
8358 break;
8359 case 4:
8360 i.log2_scale_factor = 2;
8361 break;
8362 case 8:
8363 i.log2_scale_factor = 3;
8364 break;
8365 default:
8366 {
8367 char sep = *input_line_pointer;
8368
8369 *input_line_pointer = '\0';
8370 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8371 scale);
8372 *input_line_pointer = sep;
8373 input_line_pointer = save;
8374 return NULL;
8375 }
8376 }
8377 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8378 {
8379 as_warn (_("scale factor of %d without an index register"),
8380 1 << i.log2_scale_factor);
8381 i.log2_scale_factor = 0;
8382 }
8383 scale = input_line_pointer;
8384 input_line_pointer = save;
8385 return scale;
8386 }
8387
8388 static int
8389 i386_displacement (char *disp_start, char *disp_end)
8390 {
8391 expressionS *exp;
8392 segT exp_seg = 0;
8393 char *save_input_line_pointer;
8394 char *gotfree_input_line;
8395 int override;
8396 i386_operand_type bigdisp, types = anydisp;
8397 int ret;
8398
8399 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8400 {
8401 as_bad (_("at most %d displacement operands are allowed"),
8402 MAX_MEMORY_OPERANDS);
8403 return 0;
8404 }
8405
8406 operand_type_set (&bigdisp, 0);
8407 if ((i.types[this_operand].bitfield.jumpabsolute)
8408 || (!current_templates->start->opcode_modifier.jump
8409 && !current_templates->start->opcode_modifier.jumpdword))
8410 {
8411 bigdisp.bitfield.disp32 = 1;
8412 override = (i.prefix[ADDR_PREFIX] != 0);
8413 if (flag_code == CODE_64BIT)
8414 {
8415 if (!override)
8416 {
8417 bigdisp.bitfield.disp32s = 1;
8418 bigdisp.bitfield.disp64 = 1;
8419 }
8420 }
8421 else if ((flag_code == CODE_16BIT) ^ override)
8422 {
8423 bigdisp.bitfield.disp32 = 0;
8424 bigdisp.bitfield.disp16 = 1;
8425 }
8426 }
8427 else
8428 {
8429 /* For PC-relative branches, the width of the displacement
8430 is dependent upon data size, not address size. */
8431 override = (i.prefix[DATA_PREFIX] != 0);
8432 if (flag_code == CODE_64BIT)
8433 {
8434 if (override || i.suffix == WORD_MNEM_SUFFIX)
8435 bigdisp.bitfield.disp16 = 1;
8436 else
8437 {
8438 bigdisp.bitfield.disp32 = 1;
8439 bigdisp.bitfield.disp32s = 1;
8440 }
8441 }
8442 else
8443 {
8444 if (!override)
8445 override = (i.suffix == (flag_code != CODE_16BIT
8446 ? WORD_MNEM_SUFFIX
8447 : LONG_MNEM_SUFFIX));
8448 bigdisp.bitfield.disp32 = 1;
8449 if ((flag_code == CODE_16BIT) ^ override)
8450 {
8451 bigdisp.bitfield.disp32 = 0;
8452 bigdisp.bitfield.disp16 = 1;
8453 }
8454 }
8455 }
8456 i.types[this_operand] = operand_type_or (i.types[this_operand],
8457 bigdisp);
8458
8459 exp = &disp_expressions[i.disp_operands];
8460 i.op[this_operand].disps = exp;
8461 i.disp_operands++;
8462 save_input_line_pointer = input_line_pointer;
8463 input_line_pointer = disp_start;
8464 END_STRING_AND_SAVE (disp_end);
8465
8466 #ifndef GCC_ASM_O_HACK
8467 #define GCC_ASM_O_HACK 0
8468 #endif
8469 #if GCC_ASM_O_HACK
8470 END_STRING_AND_SAVE (disp_end + 1);
8471 if (i.types[this_operand].bitfield.baseIndex
8472 && displacement_string_end[-1] == '+')
8473 {
8474 /* This hack is to avoid a warning when using the "o"
8475 constraint within gcc asm statements.
8476 For instance:
8477
8478 #define _set_tssldt_desc(n,addr,limit,type) \
8479 __asm__ __volatile__ ( \
8480 "movw %w2,%0\n\t" \
8481 "movw %w1,2+%0\n\t" \
8482 "rorl $16,%1\n\t" \
8483 "movb %b1,4+%0\n\t" \
8484 "movb %4,5+%0\n\t" \
8485 "movb $0,6+%0\n\t" \
8486 "movb %h1,7+%0\n\t" \
8487 "rorl $16,%1" \
8488 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8489
8490 This works great except that the output assembler ends
8491 up looking a bit weird if it turns out that there is
8492 no offset. You end up producing code that looks like:
8493
8494 #APP
8495 movw $235,(%eax)
8496 movw %dx,2+(%eax)
8497 rorl $16,%edx
8498 movb %dl,4+(%eax)
8499 movb $137,5+(%eax)
8500 movb $0,6+(%eax)
8501 movb %dh,7+(%eax)
8502 rorl $16,%edx
8503 #NO_APP
8504
8505 So here we provide the missing zero. */
8506
8507 *displacement_string_end = '0';
8508 }
8509 #endif
8510 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8511 if (gotfree_input_line)
8512 input_line_pointer = gotfree_input_line;
8513
8514 exp_seg = expression (exp);
8515
8516 SKIP_WHITESPACE ();
8517 if (*input_line_pointer)
8518 as_bad (_("junk `%s' after expression"), input_line_pointer);
8519 #if GCC_ASM_O_HACK
8520 RESTORE_END_STRING (disp_end + 1);
8521 #endif
8522 input_line_pointer = save_input_line_pointer;
8523 if (gotfree_input_line)
8524 {
8525 free (gotfree_input_line);
8526
8527 if (exp->X_op == O_constant || exp->X_op == O_register)
8528 exp->X_op = O_illegal;
8529 }
8530
8531 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8532
8533 RESTORE_END_STRING (disp_end);
8534
8535 return ret;
8536 }
8537
8538 static int
8539 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8540 i386_operand_type types, const char *disp_start)
8541 {
8542 i386_operand_type bigdisp;
8543 int ret = 1;
8544
8545 /* We do this to make sure that the section symbol is in
8546 the symbol table. We will ultimately change the relocation
8547 to be relative to the beginning of the section. */
8548 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8549 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8550 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8551 {
8552 if (exp->X_op != O_symbol)
8553 goto inv_disp;
8554
8555 if (S_IS_LOCAL (exp->X_add_symbol)
8556 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8557 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8558 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8559 exp->X_op = O_subtract;
8560 exp->X_op_symbol = GOT_symbol;
8561 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8562 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8563 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8564 i.reloc[this_operand] = BFD_RELOC_64;
8565 else
8566 i.reloc[this_operand] = BFD_RELOC_32;
8567 }
8568
8569 else if (exp->X_op == O_absent
8570 || exp->X_op == O_illegal
8571 || exp->X_op == O_big)
8572 {
8573 inv_disp:
8574 as_bad (_("missing or invalid displacement expression `%s'"),
8575 disp_start);
8576 ret = 0;
8577 }
8578
8579 else if (flag_code == CODE_64BIT
8580 && !i.prefix[ADDR_PREFIX]
8581 && exp->X_op == O_constant)
8582 {
8583 /* Since displacement is signed extended to 64bit, don't allow
8584 disp32 and turn off disp32s if they are out of range. */
8585 i.types[this_operand].bitfield.disp32 = 0;
8586 if (!fits_in_signed_long (exp->X_add_number))
8587 {
8588 i.types[this_operand].bitfield.disp32s = 0;
8589 if (i.types[this_operand].bitfield.baseindex)
8590 {
8591 as_bad (_("0x%lx out range of signed 32bit displacement"),
8592 (long) exp->X_add_number);
8593 ret = 0;
8594 }
8595 }
8596 }
8597
8598 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8599 else if (exp->X_op != O_constant
8600 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8601 && exp_seg != absolute_section
8602 && exp_seg != text_section
8603 && exp_seg != data_section
8604 && exp_seg != bss_section
8605 && exp_seg != undefined_section
8606 && !bfd_is_com_section (exp_seg))
8607 {
8608 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8609 ret = 0;
8610 }
8611 #endif
8612
8613 /* Check if this is a displacement only operand. */
8614 bigdisp = i.types[this_operand];
8615 bigdisp.bitfield.disp8 = 0;
8616 bigdisp.bitfield.disp16 = 0;
8617 bigdisp.bitfield.disp32 = 0;
8618 bigdisp.bitfield.disp32s = 0;
8619 bigdisp.bitfield.disp64 = 0;
8620 if (operand_type_all_zero (&bigdisp))
8621 i.types[this_operand] = operand_type_and (i.types[this_operand],
8622 types);
8623
8624 return ret;
8625 }
8626
8627 /* Make sure the memory operand we've been dealt is valid.
8628 Return 1 on success, 0 on a failure. */
8629
8630 static int
8631 i386_index_check (const char *operand_string)
8632 {
8633 const char *kind = "base/index";
8634 enum flag_code addr_mode;
8635
8636 if (i.prefix[ADDR_PREFIX])
8637 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8638 else
8639 {
8640 addr_mode = flag_code;
8641
8642 #if INFER_ADDR_PREFIX
8643 if (i.mem_operands == 0)
8644 {
8645 /* Infer address prefix from the first memory operand. */
8646 const reg_entry *addr_reg = i.base_reg;
8647
8648 if (addr_reg == NULL)
8649 addr_reg = i.index_reg;
8650
8651 if (addr_reg)
8652 {
8653 if (addr_reg->reg_num == RegEip
8654 || addr_reg->reg_num == RegEiz
8655 || addr_reg->reg_type.bitfield.reg32)
8656 addr_mode = CODE_32BIT;
8657 else if (flag_code != CODE_64BIT
8658 && addr_reg->reg_type.bitfield.reg16)
8659 addr_mode = CODE_16BIT;
8660
8661 if (addr_mode != flag_code)
8662 {
8663 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8664 i.prefixes += 1;
8665 /* Change the size of any displacement too. At most one
8666 of Disp16 or Disp32 is set.
8667 FIXME. There doesn't seem to be any real need for
8668 separate Disp16 and Disp32 flags. The same goes for
8669 Imm16 and Imm32. Removing them would probably clean
8670 up the code quite a lot. */
8671 if (flag_code != CODE_64BIT
8672 && (i.types[this_operand].bitfield.disp16
8673 || i.types[this_operand].bitfield.disp32))
8674 i.types[this_operand]
8675 = operand_type_xor (i.types[this_operand], disp16_32);
8676 }
8677 }
8678 }
8679 #endif
8680 }
8681
8682 if (current_templates->start->opcode_modifier.isstring
8683 && !current_templates->start->opcode_modifier.immext
8684 && (current_templates->end[-1].opcode_modifier.isstring
8685 || i.mem_operands))
8686 {
8687 /* Memory operands of string insns are special in that they only allow
8688 a single register (rDI, rSI, or rBX) as their memory address. */
8689 const reg_entry *expected_reg;
8690 static const char *di_si[][2] =
8691 {
8692 { "esi", "edi" },
8693 { "si", "di" },
8694 { "rsi", "rdi" }
8695 };
8696 static const char *bx[] = { "ebx", "bx", "rbx" };
8697
8698 kind = "string address";
8699
8700 if (current_templates->start->opcode_modifier.repprefixok)
8701 {
8702 i386_operand_type type = current_templates->end[-1].operand_types[0];
8703
8704 if (!type.bitfield.baseindex
8705 || ((!i.mem_operands != !intel_syntax)
8706 && current_templates->end[-1].operand_types[1]
8707 .bitfield.baseindex))
8708 type = current_templates->end[-1].operand_types[1];
8709 expected_reg = hash_find (reg_hash,
8710 di_si[addr_mode][type.bitfield.esseg]);
8711
8712 }
8713 else
8714 expected_reg = hash_find (reg_hash, bx[addr_mode]);
8715
8716 if (i.base_reg != expected_reg
8717 || i.index_reg
8718 || operand_type_check (i.types[this_operand], disp))
8719 {
8720 /* The second memory operand must have the same size as
8721 the first one. */
8722 if (i.mem_operands
8723 && i.base_reg
8724 && !((addr_mode == CODE_64BIT
8725 && i.base_reg->reg_type.bitfield.reg64)
8726 || (addr_mode == CODE_32BIT
8727 ? i.base_reg->reg_type.bitfield.reg32
8728 : i.base_reg->reg_type.bitfield.reg16)))
8729 goto bad_address;
8730
8731 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8732 operand_string,
8733 intel_syntax ? '[' : '(',
8734 register_prefix,
8735 expected_reg->reg_name,
8736 intel_syntax ? ']' : ')');
8737 return 1;
8738 }
8739 else
8740 return 1;
8741
8742 bad_address:
8743 as_bad (_("`%s' is not a valid %s expression"),
8744 operand_string, kind);
8745 return 0;
8746 }
8747 else
8748 {
8749 if (addr_mode != CODE_16BIT)
8750 {
8751 /* 32-bit/64-bit checks. */
8752 if ((i.base_reg
8753 && (addr_mode == CODE_64BIT
8754 ? !i.base_reg->reg_type.bitfield.reg64
8755 : !i.base_reg->reg_type.bitfield.reg32)
8756 && (i.index_reg
8757 || (i.base_reg->reg_num
8758 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8759 || (i.index_reg
8760 && !i.index_reg->reg_type.bitfield.regxmm
8761 && !i.index_reg->reg_type.bitfield.regymm
8762 && !i.index_reg->reg_type.bitfield.regzmm
8763 && ((addr_mode == CODE_64BIT
8764 ? !(i.index_reg->reg_type.bitfield.reg64
8765 || i.index_reg->reg_num == RegRiz)
8766 : !(i.index_reg->reg_type.bitfield.reg32
8767 || i.index_reg->reg_num == RegEiz))
8768 || !i.index_reg->reg_type.bitfield.baseindex)))
8769 goto bad_address;
8770
8771 /* bndmk, bndldx, and bndstx have special restrictions. */
8772 if (current_templates->start->base_opcode == 0xf30f1b
8773 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
8774 {
8775 /* They cannot use RIP-relative addressing. */
8776 if (i.base_reg && i.base_reg->reg_num == RegRip)
8777 {
8778 as_bad (_("`%s' cannot be used here"), operand_string);
8779 return 0;
8780 }
8781
8782 /* bndldx and bndstx ignore their scale factor. */
8783 if (current_templates->start->base_opcode != 0xf30f1b
8784 && i.log2_scale_factor)
8785 as_warn (_("register scaling is being ignored here"));
8786 }
8787 }
8788 else
8789 {
8790 /* 16-bit checks. */
8791 if ((i.base_reg
8792 && (!i.base_reg->reg_type.bitfield.reg16
8793 || !i.base_reg->reg_type.bitfield.baseindex))
8794 || (i.index_reg
8795 && (!i.index_reg->reg_type.bitfield.reg16
8796 || !i.index_reg->reg_type.bitfield.baseindex
8797 || !(i.base_reg
8798 && i.base_reg->reg_num < 6
8799 && i.index_reg->reg_num >= 6
8800 && i.log2_scale_factor == 0))))
8801 goto bad_address;
8802 }
8803 }
8804 return 1;
8805 }
8806
8807 /* Handle vector immediates. */
8808
8809 static int
8810 RC_SAE_immediate (const char *imm_start)
8811 {
8812 unsigned int match_found, j;
8813 const char *pstr = imm_start;
8814 expressionS *exp;
8815
8816 if (*pstr != '{')
8817 return 0;
8818
8819 pstr++;
8820 match_found = 0;
8821 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8822 {
8823 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8824 {
8825 if (!i.rounding)
8826 {
8827 rc_op.type = RC_NamesTable[j].type;
8828 rc_op.operand = this_operand;
8829 i.rounding = &rc_op;
8830 }
8831 else
8832 {
8833 as_bad (_("duplicated `%s'"), imm_start);
8834 return 0;
8835 }
8836 pstr += RC_NamesTable[j].len;
8837 match_found = 1;
8838 break;
8839 }
8840 }
8841 if (!match_found)
8842 return 0;
8843
8844 if (*pstr++ != '}')
8845 {
8846 as_bad (_("Missing '}': '%s'"), imm_start);
8847 return 0;
8848 }
8849 /* RC/SAE immediate string should contain nothing more. */;
8850 if (*pstr != 0)
8851 {
8852 as_bad (_("Junk after '}': '%s'"), imm_start);
8853 return 0;
8854 }
8855
8856 exp = &im_expressions[i.imm_operands++];
8857 i.op[this_operand].imms = exp;
8858
8859 exp->X_op = O_constant;
8860 exp->X_add_number = 0;
8861 exp->X_add_symbol = (symbolS *) 0;
8862 exp->X_op_symbol = (symbolS *) 0;
8863
8864 i.types[this_operand].bitfield.imm8 = 1;
8865 return 1;
8866 }
8867
8868 /* Only string instructions can have a second memory operand, so
8869 reduce current_templates to just those if it contains any. */
8870 static int
8871 maybe_adjust_templates (void)
8872 {
8873 const insn_template *t;
8874
8875 gas_assert (i.mem_operands == 1);
8876
8877 for (t = current_templates->start; t < current_templates->end; ++t)
8878 if (t->opcode_modifier.isstring)
8879 break;
8880
8881 if (t < current_templates->end)
8882 {
8883 static templates aux_templates;
8884 bfd_boolean recheck;
8885
8886 aux_templates.start = t;
8887 for (; t < current_templates->end; ++t)
8888 if (!t->opcode_modifier.isstring)
8889 break;
8890 aux_templates.end = t;
8891
8892 /* Determine whether to re-check the first memory operand. */
8893 recheck = (aux_templates.start != current_templates->start
8894 || t != current_templates->end);
8895
8896 current_templates = &aux_templates;
8897
8898 if (recheck)
8899 {
8900 i.mem_operands = 0;
8901 if (i.memop1_string != NULL
8902 && i386_index_check (i.memop1_string) == 0)
8903 return 0;
8904 i.mem_operands = 1;
8905 }
8906 }
8907
8908 return 1;
8909 }
8910
8911 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8912 on error. */
8913
8914 static int
8915 i386_att_operand (char *operand_string)
8916 {
8917 const reg_entry *r;
8918 char *end_op;
8919 char *op_string = operand_string;
8920
8921 if (is_space_char (*op_string))
8922 ++op_string;
8923
8924 /* We check for an absolute prefix (differentiating,
8925 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8926 if (*op_string == ABSOLUTE_PREFIX)
8927 {
8928 ++op_string;
8929 if (is_space_char (*op_string))
8930 ++op_string;
8931 i.types[this_operand].bitfield.jumpabsolute = 1;
8932 }
8933
8934 /* Check if operand is a register. */
8935 if ((r = parse_register (op_string, &end_op)) != NULL)
8936 {
8937 i386_operand_type temp;
8938
8939 /* Check for a segment override by searching for ':' after a
8940 segment register. */
8941 op_string = end_op;
8942 if (is_space_char (*op_string))
8943 ++op_string;
8944 if (*op_string == ':'
8945 && (r->reg_type.bitfield.sreg2
8946 || r->reg_type.bitfield.sreg3))
8947 {
8948 switch (r->reg_num)
8949 {
8950 case 0:
8951 i.seg[i.mem_operands] = &es;
8952 break;
8953 case 1:
8954 i.seg[i.mem_operands] = &cs;
8955 break;
8956 case 2:
8957 i.seg[i.mem_operands] = &ss;
8958 break;
8959 case 3:
8960 i.seg[i.mem_operands] = &ds;
8961 break;
8962 case 4:
8963 i.seg[i.mem_operands] = &fs;
8964 break;
8965 case 5:
8966 i.seg[i.mem_operands] = &gs;
8967 break;
8968 }
8969
8970 /* Skip the ':' and whitespace. */
8971 ++op_string;
8972 if (is_space_char (*op_string))
8973 ++op_string;
8974
8975 if (!is_digit_char (*op_string)
8976 && !is_identifier_char (*op_string)
8977 && *op_string != '('
8978 && *op_string != ABSOLUTE_PREFIX)
8979 {
8980 as_bad (_("bad memory operand `%s'"), op_string);
8981 return 0;
8982 }
8983 /* Handle case of %es:*foo. */
8984 if (*op_string == ABSOLUTE_PREFIX)
8985 {
8986 ++op_string;
8987 if (is_space_char (*op_string))
8988 ++op_string;
8989 i.types[this_operand].bitfield.jumpabsolute = 1;
8990 }
8991 goto do_memory_reference;
8992 }
8993
8994 /* Handle vector operations. */
8995 if (*op_string == '{')
8996 {
8997 op_string = check_VecOperations (op_string, NULL);
8998 if (op_string == NULL)
8999 return 0;
9000 }
9001
9002 if (*op_string)
9003 {
9004 as_bad (_("junk `%s' after register"), op_string);
9005 return 0;
9006 }
9007 temp = r->reg_type;
9008 temp.bitfield.baseindex = 0;
9009 i.types[this_operand] = operand_type_or (i.types[this_operand],
9010 temp);
9011 i.types[this_operand].bitfield.unspecified = 0;
9012 i.op[this_operand].regs = r;
9013 i.reg_operands++;
9014 }
9015 else if (*op_string == REGISTER_PREFIX)
9016 {
9017 as_bad (_("bad register name `%s'"), op_string);
9018 return 0;
9019 }
9020 else if (*op_string == IMMEDIATE_PREFIX)
9021 {
9022 ++op_string;
9023 if (i.types[this_operand].bitfield.jumpabsolute)
9024 {
9025 as_bad (_("immediate operand illegal with absolute jump"));
9026 return 0;
9027 }
9028 if (!i386_immediate (op_string))
9029 return 0;
9030 }
9031 else if (RC_SAE_immediate (operand_string))
9032 {
9033 /* If it is a RC or SAE immediate, do nothing. */
9034 ;
9035 }
9036 else if (is_digit_char (*op_string)
9037 || is_identifier_char (*op_string)
9038 || *op_string == '"'
9039 || *op_string == '(')
9040 {
9041 /* This is a memory reference of some sort. */
9042 char *base_string;
9043
9044 /* Start and end of displacement string expression (if found). */
9045 char *displacement_string_start;
9046 char *displacement_string_end;
9047 char *vop_start;
9048
9049 do_memory_reference:
9050 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9051 return 0;
9052 if ((i.mem_operands == 1
9053 && !current_templates->start->opcode_modifier.isstring)
9054 || i.mem_operands == 2)
9055 {
9056 as_bad (_("too many memory references for `%s'"),
9057 current_templates->start->name);
9058 return 0;
9059 }
9060
9061 /* Check for base index form. We detect the base index form by
9062 looking for an ')' at the end of the operand, searching
9063 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9064 after the '('. */
9065 base_string = op_string + strlen (op_string);
9066
9067 /* Handle vector operations. */
9068 vop_start = strchr (op_string, '{');
9069 if (vop_start && vop_start < base_string)
9070 {
9071 if (check_VecOperations (vop_start, base_string) == NULL)
9072 return 0;
9073 base_string = vop_start;
9074 }
9075
9076 --base_string;
9077 if (is_space_char (*base_string))
9078 --base_string;
9079
9080 /* If we only have a displacement, set-up for it to be parsed later. */
9081 displacement_string_start = op_string;
9082 displacement_string_end = base_string + 1;
9083
9084 if (*base_string == ')')
9085 {
9086 char *temp_string;
9087 unsigned int parens_balanced = 1;
9088 /* We've already checked that the number of left & right ()'s are
9089 equal, so this loop will not be infinite. */
9090 do
9091 {
9092 base_string--;
9093 if (*base_string == ')')
9094 parens_balanced++;
9095 if (*base_string == '(')
9096 parens_balanced--;
9097 }
9098 while (parens_balanced);
9099
9100 temp_string = base_string;
9101
9102 /* Skip past '(' and whitespace. */
9103 ++base_string;
9104 if (is_space_char (*base_string))
9105 ++base_string;
9106
9107 if (*base_string == ','
9108 || ((i.base_reg = parse_register (base_string, &end_op))
9109 != NULL))
9110 {
9111 displacement_string_end = temp_string;
9112
9113 i.types[this_operand].bitfield.baseindex = 1;
9114
9115 if (i.base_reg)
9116 {
9117 base_string = end_op;
9118 if (is_space_char (*base_string))
9119 ++base_string;
9120 }
9121
9122 /* There may be an index reg or scale factor here. */
9123 if (*base_string == ',')
9124 {
9125 ++base_string;
9126 if (is_space_char (*base_string))
9127 ++base_string;
9128
9129 if ((i.index_reg = parse_register (base_string, &end_op))
9130 != NULL)
9131 {
9132 base_string = end_op;
9133 if (is_space_char (*base_string))
9134 ++base_string;
9135 if (*base_string == ',')
9136 {
9137 ++base_string;
9138 if (is_space_char (*base_string))
9139 ++base_string;
9140 }
9141 else if (*base_string != ')')
9142 {
9143 as_bad (_("expecting `,' or `)' "
9144 "after index register in `%s'"),
9145 operand_string);
9146 return 0;
9147 }
9148 }
9149 else if (*base_string == REGISTER_PREFIX)
9150 {
9151 end_op = strchr (base_string, ',');
9152 if (end_op)
9153 *end_op = '\0';
9154 as_bad (_("bad register name `%s'"), base_string);
9155 return 0;
9156 }
9157
9158 /* Check for scale factor. */
9159 if (*base_string != ')')
9160 {
9161 char *end_scale = i386_scale (base_string);
9162
9163 if (!end_scale)
9164 return 0;
9165
9166 base_string = end_scale;
9167 if (is_space_char (*base_string))
9168 ++base_string;
9169 if (*base_string != ')')
9170 {
9171 as_bad (_("expecting `)' "
9172 "after scale factor in `%s'"),
9173 operand_string);
9174 return 0;
9175 }
9176 }
9177 else if (!i.index_reg)
9178 {
9179 as_bad (_("expecting index register or scale factor "
9180 "after `,'; got '%c'"),
9181 *base_string);
9182 return 0;
9183 }
9184 }
9185 else if (*base_string != ')')
9186 {
9187 as_bad (_("expecting `,' or `)' "
9188 "after base register in `%s'"),
9189 operand_string);
9190 return 0;
9191 }
9192 }
9193 else if (*base_string == REGISTER_PREFIX)
9194 {
9195 end_op = strchr (base_string, ',');
9196 if (end_op)
9197 *end_op = '\0';
9198 as_bad (_("bad register name `%s'"), base_string);
9199 return 0;
9200 }
9201 }
9202
9203 /* If there's an expression beginning the operand, parse it,
9204 assuming displacement_string_start and
9205 displacement_string_end are meaningful. */
9206 if (displacement_string_start != displacement_string_end)
9207 {
9208 if (!i386_displacement (displacement_string_start,
9209 displacement_string_end))
9210 return 0;
9211 }
9212
9213 /* Special case for (%dx) while doing input/output op. */
9214 if (i.base_reg
9215 && operand_type_equal (&i.base_reg->reg_type,
9216 &reg16_inoutportreg)
9217 && i.index_reg == 0
9218 && i.log2_scale_factor == 0
9219 && i.seg[i.mem_operands] == 0
9220 && !operand_type_check (i.types[this_operand], disp))
9221 {
9222 i.types[this_operand] = inoutportreg;
9223 return 1;
9224 }
9225
9226 if (i386_index_check (operand_string) == 0)
9227 return 0;
9228 i.types[this_operand].bitfield.mem = 1;
9229 if (i.mem_operands == 0)
9230 i.memop1_string = xstrdup (operand_string);
9231 i.mem_operands++;
9232 }
9233 else
9234 {
9235 /* It's not a memory operand; argh! */
9236 as_bad (_("invalid char %s beginning operand %d `%s'"),
9237 output_invalid (*op_string),
9238 this_operand + 1,
9239 op_string);
9240 return 0;
9241 }
9242 return 1; /* Normal return. */
9243 }
9244 \f
9245 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9246 that an rs_machine_dependent frag may reach. */
9247
9248 unsigned int
9249 i386_frag_max_var (fragS *frag)
9250 {
9251 /* The only relaxable frags are for jumps.
9252 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9253 gas_assert (frag->fr_type == rs_machine_dependent);
9254 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9255 }
9256
9257 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9258 static int
9259 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9260 {
9261 /* STT_GNU_IFUNC symbol must go through PLT. */
9262 if ((symbol_get_bfdsym (fr_symbol)->flags
9263 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9264 return 0;
9265
9266 if (!S_IS_EXTERNAL (fr_symbol))
9267 /* Symbol may be weak or local. */
9268 return !S_IS_WEAK (fr_symbol);
9269
9270 /* Global symbols with non-default visibility can't be preempted. */
9271 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9272 return 1;
9273
9274 if (fr_var != NO_RELOC)
9275 switch ((enum bfd_reloc_code_real) fr_var)
9276 {
9277 case BFD_RELOC_386_PLT32:
9278 case BFD_RELOC_X86_64_PLT32:
9279 /* Symbol with PLT relocation may be preempted. */
9280 return 0;
9281 default:
9282 abort ();
9283 }
9284
9285 /* Global symbols with default visibility in a shared library may be
9286 preempted by another definition. */
9287 return !shared;
9288 }
9289 #endif
9290
9291 /* md_estimate_size_before_relax()
9292
9293 Called just before relax() for rs_machine_dependent frags. The x86
9294 assembler uses these frags to handle variable size jump
9295 instructions.
9296
9297 Any symbol that is now undefined will not become defined.
9298 Return the correct fr_subtype in the frag.
9299 Return the initial "guess for variable size of frag" to caller.
9300 The guess is actually the growth beyond the fixed part. Whatever
9301 we do to grow the fixed or variable part contributes to our
9302 returned value. */
9303
9304 int
9305 md_estimate_size_before_relax (fragS *fragP, segT segment)
9306 {
9307 /* We've already got fragP->fr_subtype right; all we have to do is
9308 check for un-relaxable symbols. On an ELF system, we can't relax
9309 an externally visible symbol, because it may be overridden by a
9310 shared library. */
9311 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9312 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9313 || (IS_ELF
9314 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9315 fragP->fr_var))
9316 #endif
9317 #if defined (OBJ_COFF) && defined (TE_PE)
9318 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9319 && S_IS_WEAK (fragP->fr_symbol))
9320 #endif
9321 )
9322 {
9323 /* Symbol is undefined in this segment, or we need to keep a
9324 reloc so that weak symbols can be overridden. */
9325 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9326 enum bfd_reloc_code_real reloc_type;
9327 unsigned char *opcode;
9328 int old_fr_fix;
9329
9330 if (fragP->fr_var != NO_RELOC)
9331 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9332 else if (size == 2)
9333 reloc_type = BFD_RELOC_16_PCREL;
9334 else
9335 reloc_type = BFD_RELOC_32_PCREL;
9336
9337 old_fr_fix = fragP->fr_fix;
9338 opcode = (unsigned char *) fragP->fr_opcode;
9339
9340 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9341 {
9342 case UNCOND_JUMP:
9343 /* Make jmp (0xeb) a (d)word displacement jump. */
9344 opcode[0] = 0xe9;
9345 fragP->fr_fix += size;
9346 fix_new (fragP, old_fr_fix, size,
9347 fragP->fr_symbol,
9348 fragP->fr_offset, 1,
9349 reloc_type);
9350 break;
9351
9352 case COND_JUMP86:
9353 if (size == 2
9354 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9355 {
9356 /* Negate the condition, and branch past an
9357 unconditional jump. */
9358 opcode[0] ^= 1;
9359 opcode[1] = 3;
9360 /* Insert an unconditional jump. */
9361 opcode[2] = 0xe9;
9362 /* We added two extra opcode bytes, and have a two byte
9363 offset. */
9364 fragP->fr_fix += 2 + 2;
9365 fix_new (fragP, old_fr_fix + 2, 2,
9366 fragP->fr_symbol,
9367 fragP->fr_offset, 1,
9368 reloc_type);
9369 break;
9370 }
9371 /* Fall through. */
9372
9373 case COND_JUMP:
9374 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9375 {
9376 fixS *fixP;
9377
9378 fragP->fr_fix += 1;
9379 fixP = fix_new (fragP, old_fr_fix, 1,
9380 fragP->fr_symbol,
9381 fragP->fr_offset, 1,
9382 BFD_RELOC_8_PCREL);
9383 fixP->fx_signed = 1;
9384 break;
9385 }
9386
9387 /* This changes the byte-displacement jump 0x7N
9388 to the (d)word-displacement jump 0x0f,0x8N. */
9389 opcode[1] = opcode[0] + 0x10;
9390 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9391 /* We've added an opcode byte. */
9392 fragP->fr_fix += 1 + size;
9393 fix_new (fragP, old_fr_fix + 1, size,
9394 fragP->fr_symbol,
9395 fragP->fr_offset, 1,
9396 reloc_type);
9397 break;
9398
9399 default:
9400 BAD_CASE (fragP->fr_subtype);
9401 break;
9402 }
9403 frag_wane (fragP);
9404 return fragP->fr_fix - old_fr_fix;
9405 }
9406
9407 /* Guess size depending on current relax state. Initially the relax
9408 state will correspond to a short jump and we return 1, because
9409 the variable part of the frag (the branch offset) is one byte
9410 long. However, we can relax a section more than once and in that
9411 case we must either set fr_subtype back to the unrelaxed state,
9412 or return the value for the appropriate branch. */
9413 return md_relax_table[fragP->fr_subtype].rlx_length;
9414 }
9415
9416 /* Called after relax() is finished.
9417
9418 In: Address of frag.
9419 fr_type == rs_machine_dependent.
9420 fr_subtype is what the address relaxed to.
9421
9422 Out: Any fixSs and constants are set up.
9423 Caller will turn frag into a ".space 0". */
9424
9425 void
9426 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9427 fragS *fragP)
9428 {
9429 unsigned char *opcode;
9430 unsigned char *where_to_put_displacement = NULL;
9431 offsetT target_address;
9432 offsetT opcode_address;
9433 unsigned int extension = 0;
9434 offsetT displacement_from_opcode_start;
9435
9436 opcode = (unsigned char *) fragP->fr_opcode;
9437
9438 /* Address we want to reach in file space. */
9439 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9440
9441 /* Address opcode resides at in file space. */
9442 opcode_address = fragP->fr_address + fragP->fr_fix;
9443
9444 /* Displacement from opcode start to fill into instruction. */
9445 displacement_from_opcode_start = target_address - opcode_address;
9446
9447 if ((fragP->fr_subtype & BIG) == 0)
9448 {
9449 /* Don't have to change opcode. */
9450 extension = 1; /* 1 opcode + 1 displacement */
9451 where_to_put_displacement = &opcode[1];
9452 }
9453 else
9454 {
9455 if (no_cond_jump_promotion
9456 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9457 as_warn_where (fragP->fr_file, fragP->fr_line,
9458 _("long jump required"));
9459
9460 switch (fragP->fr_subtype)
9461 {
9462 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9463 extension = 4; /* 1 opcode + 4 displacement */
9464 opcode[0] = 0xe9;
9465 where_to_put_displacement = &opcode[1];
9466 break;
9467
9468 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9469 extension = 2; /* 1 opcode + 2 displacement */
9470 opcode[0] = 0xe9;
9471 where_to_put_displacement = &opcode[1];
9472 break;
9473
9474 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9475 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9476 extension = 5; /* 2 opcode + 4 displacement */
9477 opcode[1] = opcode[0] + 0x10;
9478 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9479 where_to_put_displacement = &opcode[2];
9480 break;
9481
9482 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9483 extension = 3; /* 2 opcode + 2 displacement */
9484 opcode[1] = opcode[0] + 0x10;
9485 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9486 where_to_put_displacement = &opcode[2];
9487 break;
9488
9489 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9490 extension = 4;
9491 opcode[0] ^= 1;
9492 opcode[1] = 3;
9493 opcode[2] = 0xe9;
9494 where_to_put_displacement = &opcode[3];
9495 break;
9496
9497 default:
9498 BAD_CASE (fragP->fr_subtype);
9499 break;
9500 }
9501 }
9502
9503 /* If size if less then four we are sure that the operand fits,
9504 but if it's 4, then it could be that the displacement is larger
9505 then -/+ 2GB. */
9506 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9507 && object_64bit
9508 && ((addressT) (displacement_from_opcode_start - extension
9509 + ((addressT) 1 << 31))
9510 > (((addressT) 2 << 31) - 1)))
9511 {
9512 as_bad_where (fragP->fr_file, fragP->fr_line,
9513 _("jump target out of range"));
9514 /* Make us emit 0. */
9515 displacement_from_opcode_start = extension;
9516 }
9517 /* Now put displacement after opcode. */
9518 md_number_to_chars ((char *) where_to_put_displacement,
9519 (valueT) (displacement_from_opcode_start - extension),
9520 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9521 fragP->fr_fix += extension;
9522 }
9523 \f
9524 /* Apply a fixup (fixP) to segment data, once it has been determined
9525 by our caller that we have all the info we need to fix it up.
9526
9527 Parameter valP is the pointer to the value of the bits.
9528
9529 On the 386, immediates, displacements, and data pointers are all in
9530 the same (little-endian) format, so we don't need to care about which
9531 we are handling. */
9532
9533 void
9534 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9535 {
9536 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9537 valueT value = *valP;
9538
9539 #if !defined (TE_Mach)
9540 if (fixP->fx_pcrel)
9541 {
9542 switch (fixP->fx_r_type)
9543 {
9544 default:
9545 break;
9546
9547 case BFD_RELOC_64:
9548 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9549 break;
9550 case BFD_RELOC_32:
9551 case BFD_RELOC_X86_64_32S:
9552 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9553 break;
9554 case BFD_RELOC_16:
9555 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9556 break;
9557 case BFD_RELOC_8:
9558 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9559 break;
9560 }
9561 }
9562
9563 if (fixP->fx_addsy != NULL
9564 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9565 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9566 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9567 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9568 && !use_rela_relocations)
9569 {
9570 /* This is a hack. There should be a better way to handle this.
9571 This covers for the fact that bfd_install_relocation will
9572 subtract the current location (for partial_inplace, PC relative
9573 relocations); see more below. */
9574 #ifndef OBJ_AOUT
9575 if (IS_ELF
9576 #ifdef TE_PE
9577 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9578 #endif
9579 )
9580 value += fixP->fx_where + fixP->fx_frag->fr_address;
9581 #endif
9582 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9583 if (IS_ELF)
9584 {
9585 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9586
9587 if ((sym_seg == seg
9588 || (symbol_section_p (fixP->fx_addsy)
9589 && sym_seg != absolute_section))
9590 && !generic_force_reloc (fixP))
9591 {
9592 /* Yes, we add the values in twice. This is because
9593 bfd_install_relocation subtracts them out again. I think
9594 bfd_install_relocation is broken, but I don't dare change
9595 it. FIXME. */
9596 value += fixP->fx_where + fixP->fx_frag->fr_address;
9597 }
9598 }
9599 #endif
9600 #if defined (OBJ_COFF) && defined (TE_PE)
9601 /* For some reason, the PE format does not store a
9602 section address offset for a PC relative symbol. */
9603 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9604 || S_IS_WEAK (fixP->fx_addsy))
9605 value += md_pcrel_from (fixP);
9606 #endif
9607 }
9608 #if defined (OBJ_COFF) && defined (TE_PE)
9609 if (fixP->fx_addsy != NULL
9610 && S_IS_WEAK (fixP->fx_addsy)
9611 /* PR 16858: Do not modify weak function references. */
9612 && ! fixP->fx_pcrel)
9613 {
9614 #if !defined (TE_PEP)
9615 /* For x86 PE weak function symbols are neither PC-relative
9616 nor do they set S_IS_FUNCTION. So the only reliable way
9617 to detect them is to check the flags of their containing
9618 section. */
9619 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9620 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9621 ;
9622 else
9623 #endif
9624 value -= S_GET_VALUE (fixP->fx_addsy);
9625 }
9626 #endif
9627
9628 /* Fix a few things - the dynamic linker expects certain values here,
9629 and we must not disappoint it. */
9630 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9631 if (IS_ELF && fixP->fx_addsy)
9632 switch (fixP->fx_r_type)
9633 {
9634 case BFD_RELOC_386_PLT32:
9635 case BFD_RELOC_X86_64_PLT32:
9636 /* Make the jump instruction point to the address of the operand. At
9637 runtime we merely add the offset to the actual PLT entry. */
9638 value = -4;
9639 break;
9640
9641 case BFD_RELOC_386_TLS_GD:
9642 case BFD_RELOC_386_TLS_LDM:
9643 case BFD_RELOC_386_TLS_IE_32:
9644 case BFD_RELOC_386_TLS_IE:
9645 case BFD_RELOC_386_TLS_GOTIE:
9646 case BFD_RELOC_386_TLS_GOTDESC:
9647 case BFD_RELOC_X86_64_TLSGD:
9648 case BFD_RELOC_X86_64_TLSLD:
9649 case BFD_RELOC_X86_64_GOTTPOFF:
9650 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9651 value = 0; /* Fully resolved at runtime. No addend. */
9652 /* Fallthrough */
9653 case BFD_RELOC_386_TLS_LE:
9654 case BFD_RELOC_386_TLS_LDO_32:
9655 case BFD_RELOC_386_TLS_LE_32:
9656 case BFD_RELOC_X86_64_DTPOFF32:
9657 case BFD_RELOC_X86_64_DTPOFF64:
9658 case BFD_RELOC_X86_64_TPOFF32:
9659 case BFD_RELOC_X86_64_TPOFF64:
9660 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9661 break;
9662
9663 case BFD_RELOC_386_TLS_DESC_CALL:
9664 case BFD_RELOC_X86_64_TLSDESC_CALL:
9665 value = 0; /* Fully resolved at runtime. No addend. */
9666 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9667 fixP->fx_done = 0;
9668 return;
9669
9670 case BFD_RELOC_VTABLE_INHERIT:
9671 case BFD_RELOC_VTABLE_ENTRY:
9672 fixP->fx_done = 0;
9673 return;
9674
9675 default:
9676 break;
9677 }
9678 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9679 *valP = value;
9680 #endif /* !defined (TE_Mach) */
9681
9682 /* Are we finished with this relocation now? */
9683 if (fixP->fx_addsy == NULL)
9684 fixP->fx_done = 1;
9685 #if defined (OBJ_COFF) && defined (TE_PE)
9686 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9687 {
9688 fixP->fx_done = 0;
9689 /* Remember value for tc_gen_reloc. */
9690 fixP->fx_addnumber = value;
9691 /* Clear out the frag for now. */
9692 value = 0;
9693 }
9694 #endif
9695 else if (use_rela_relocations)
9696 {
9697 fixP->fx_no_overflow = 1;
9698 /* Remember value for tc_gen_reloc. */
9699 fixP->fx_addnumber = value;
9700 value = 0;
9701 }
9702
9703 md_number_to_chars (p, value, fixP->fx_size);
9704 }
9705 \f
9706 const char *
9707 md_atof (int type, char *litP, int *sizeP)
9708 {
9709 /* This outputs the LITTLENUMs in REVERSE order;
9710 in accord with the bigendian 386. */
9711 return ieee_md_atof (type, litP, sizeP, FALSE);
9712 }
9713 \f
9714 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
9715
9716 static char *
9717 output_invalid (int c)
9718 {
9719 if (ISPRINT (c))
9720 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9721 "'%c'", c);
9722 else
9723 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9724 "(0x%x)", (unsigned char) c);
9725 return output_invalid_buf;
9726 }
9727
9728 /* REG_STRING starts *before* REGISTER_PREFIX. */
9729
9730 static const reg_entry *
9731 parse_real_register (char *reg_string, char **end_op)
9732 {
9733 char *s = reg_string;
9734 char *p;
9735 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9736 const reg_entry *r;
9737
9738 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9739 if (*s == REGISTER_PREFIX)
9740 ++s;
9741
9742 if (is_space_char (*s))
9743 ++s;
9744
9745 p = reg_name_given;
9746 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
9747 {
9748 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
9749 return (const reg_entry *) NULL;
9750 s++;
9751 }
9752
9753 /* For naked regs, make sure that we are not dealing with an identifier.
9754 This prevents confusing an identifier like `eax_var' with register
9755 `eax'. */
9756 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9757 return (const reg_entry *) NULL;
9758
9759 *end_op = s;
9760
9761 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9762
9763 /* Handle floating point regs, allowing spaces in the (i) part. */
9764 if (r == i386_regtab /* %st is first entry of table */)
9765 {
9766 if (is_space_char (*s))
9767 ++s;
9768 if (*s == '(')
9769 {
9770 ++s;
9771 if (is_space_char (*s))
9772 ++s;
9773 if (*s >= '0' && *s <= '7')
9774 {
9775 int fpr = *s - '0';
9776 ++s;
9777 if (is_space_char (*s))
9778 ++s;
9779 if (*s == ')')
9780 {
9781 *end_op = s + 1;
9782 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
9783 know (r);
9784 return r + fpr;
9785 }
9786 }
9787 /* We have "%st(" then garbage. */
9788 return (const reg_entry *) NULL;
9789 }
9790 }
9791
9792 if (r == NULL || allow_pseudo_reg)
9793 return r;
9794
9795 if (operand_type_all_zero (&r->reg_type))
9796 return (const reg_entry *) NULL;
9797
9798 if ((r->reg_type.bitfield.reg32
9799 || r->reg_type.bitfield.sreg3
9800 || r->reg_type.bitfield.control
9801 || r->reg_type.bitfield.debug
9802 || r->reg_type.bitfield.test)
9803 && !cpu_arch_flags.bitfield.cpui386)
9804 return (const reg_entry *) NULL;
9805
9806 if (r->reg_type.bitfield.floatreg
9807 && !cpu_arch_flags.bitfield.cpu8087
9808 && !cpu_arch_flags.bitfield.cpu287
9809 && !cpu_arch_flags.bitfield.cpu387)
9810 return (const reg_entry *) NULL;
9811
9812 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
9813 return (const reg_entry *) NULL;
9814
9815 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpuregxmm)
9816 return (const reg_entry *) NULL;
9817
9818 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuregymm)
9819 return (const reg_entry *) NULL;
9820
9821 if (r->reg_type.bitfield.regzmm && !cpu_arch_flags.bitfield.cpuregzmm)
9822 return (const reg_entry *) NULL;
9823
9824 if (r->reg_type.bitfield.regmask
9825 && !cpu_arch_flags.bitfield.cpuregmask)
9826 return (const reg_entry *) NULL;
9827
9828 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9829 if (!allow_index_reg
9830 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9831 return (const reg_entry *) NULL;
9832
9833 /* Upper 16 vector register is only available with VREX in 64bit
9834 mode. */
9835 if ((r->reg_flags & RegVRex))
9836 {
9837 if (i.vec_encoding == vex_encoding_default)
9838 i.vec_encoding = vex_encoding_evex;
9839
9840 if (!cpu_arch_flags.bitfield.cpuvrex
9841 || i.vec_encoding != vex_encoding_evex
9842 || flag_code != CODE_64BIT)
9843 return (const reg_entry *) NULL;
9844 }
9845
9846 if (((r->reg_flags & (RegRex64 | RegRex))
9847 || r->reg_type.bitfield.reg64)
9848 && (!cpu_arch_flags.bitfield.cpulm
9849 || !operand_type_equal (&r->reg_type, &control))
9850 && flag_code != CODE_64BIT)
9851 return (const reg_entry *) NULL;
9852
9853 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9854 return (const reg_entry *) NULL;
9855
9856 return r;
9857 }
9858
9859 /* REG_STRING starts *before* REGISTER_PREFIX. */
9860
9861 static const reg_entry *
9862 parse_register (char *reg_string, char **end_op)
9863 {
9864 const reg_entry *r;
9865
9866 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9867 r = parse_real_register (reg_string, end_op);
9868 else
9869 r = NULL;
9870 if (!r)
9871 {
9872 char *save = input_line_pointer;
9873 char c;
9874 symbolS *symbolP;
9875
9876 input_line_pointer = reg_string;
9877 c = get_symbol_name (&reg_string);
9878 symbolP = symbol_find (reg_string);
9879 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9880 {
9881 const expressionS *e = symbol_get_value_expression (symbolP);
9882
9883 know (e->X_op == O_register);
9884 know (e->X_add_number >= 0
9885 && (valueT) e->X_add_number < i386_regtab_size);
9886 r = i386_regtab + e->X_add_number;
9887 if ((r->reg_flags & RegVRex))
9888 i.vec_encoding = vex_encoding_evex;
9889 *end_op = input_line_pointer;
9890 }
9891 *input_line_pointer = c;
9892 input_line_pointer = save;
9893 }
9894 return r;
9895 }
9896
9897 int
9898 i386_parse_name (char *name, expressionS *e, char *nextcharP)
9899 {
9900 const reg_entry *r;
9901 char *end = input_line_pointer;
9902
9903 *end = *nextcharP;
9904 r = parse_register (name, &input_line_pointer);
9905 if (r && end <= input_line_pointer)
9906 {
9907 *nextcharP = *input_line_pointer;
9908 *input_line_pointer = 0;
9909 e->X_op = O_register;
9910 e->X_add_number = r - i386_regtab;
9911 return 1;
9912 }
9913 input_line_pointer = end;
9914 *end = 0;
9915 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
9916 }
9917
9918 void
9919 md_operand (expressionS *e)
9920 {
9921 char *end;
9922 const reg_entry *r;
9923
9924 switch (*input_line_pointer)
9925 {
9926 case REGISTER_PREFIX:
9927 r = parse_real_register (input_line_pointer, &end);
9928 if (r)
9929 {
9930 e->X_op = O_register;
9931 e->X_add_number = r - i386_regtab;
9932 input_line_pointer = end;
9933 }
9934 break;
9935
9936 case '[':
9937 gas_assert (intel_syntax);
9938 end = input_line_pointer++;
9939 expression (e);
9940 if (*input_line_pointer == ']')
9941 {
9942 ++input_line_pointer;
9943 e->X_op_symbol = make_expr_symbol (e);
9944 e->X_add_symbol = NULL;
9945 e->X_add_number = 0;
9946 e->X_op = O_index;
9947 }
9948 else
9949 {
9950 e->X_op = O_absent;
9951 input_line_pointer = end;
9952 }
9953 break;
9954 }
9955 }
9956
9957 \f
9958 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9959 const char *md_shortopts = "kVQ:sqn";
9960 #else
9961 const char *md_shortopts = "qn";
9962 #endif
9963
9964 #define OPTION_32 (OPTION_MD_BASE + 0)
9965 #define OPTION_64 (OPTION_MD_BASE + 1)
9966 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9967 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9968 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9969 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9970 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9971 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9972 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9973 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9974 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9975 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9976 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9977 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9978 #define OPTION_X32 (OPTION_MD_BASE + 14)
9979 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9980 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9981 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9982 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9983 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9984 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9985 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9986 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9987 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9988 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9989 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
9990
9991 struct option md_longopts[] =
9992 {
9993 {"32", no_argument, NULL, OPTION_32},
9994 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9995 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9996 {"64", no_argument, NULL, OPTION_64},
9997 #endif
9998 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9999 {"x32", no_argument, NULL, OPTION_X32},
10000 {"mshared", no_argument, NULL, OPTION_MSHARED},
10001 #endif
10002 {"divide", no_argument, NULL, OPTION_DIVIDE},
10003 {"march", required_argument, NULL, OPTION_MARCH},
10004 {"mtune", required_argument, NULL, OPTION_MTUNE},
10005 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10006 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10007 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10008 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10009 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
10010 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10011 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10012 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10013 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10014 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10015 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10016 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10017 # if defined (TE_PE) || defined (TE_PEP)
10018 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10019 #endif
10020 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10021 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10022 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10023 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10024 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10025 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10026 {NULL, no_argument, NULL, 0}
10027 };
10028 size_t md_longopts_size = sizeof (md_longopts);
10029
10030 int
10031 md_parse_option (int c, const char *arg)
10032 {
10033 unsigned int j;
10034 char *arch, *next, *saved;
10035
10036 switch (c)
10037 {
10038 case 'n':
10039 optimize_align_code = 0;
10040 break;
10041
10042 case 'q':
10043 quiet_warnings = 1;
10044 break;
10045
10046 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10047 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10048 should be emitted or not. FIXME: Not implemented. */
10049 case 'Q':
10050 break;
10051
10052 /* -V: SVR4 argument to print version ID. */
10053 case 'V':
10054 print_version_id ();
10055 break;
10056
10057 /* -k: Ignore for FreeBSD compatibility. */
10058 case 'k':
10059 break;
10060
10061 case 's':
10062 /* -s: On i386 Solaris, this tells the native assembler to use
10063 .stab instead of .stab.excl. We always use .stab anyhow. */
10064 break;
10065
10066 case OPTION_MSHARED:
10067 shared = 1;
10068 break;
10069 #endif
10070 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10071 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10072 case OPTION_64:
10073 {
10074 const char **list, **l;
10075
10076 list = bfd_target_list ();
10077 for (l = list; *l != NULL; l++)
10078 if (CONST_STRNEQ (*l, "elf64-x86-64")
10079 || strcmp (*l, "coff-x86-64") == 0
10080 || strcmp (*l, "pe-x86-64") == 0
10081 || strcmp (*l, "pei-x86-64") == 0
10082 || strcmp (*l, "mach-o-x86-64") == 0)
10083 {
10084 default_arch = "x86_64";
10085 break;
10086 }
10087 if (*l == NULL)
10088 as_fatal (_("no compiled in support for x86_64"));
10089 free (list);
10090 }
10091 break;
10092 #endif
10093
10094 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10095 case OPTION_X32:
10096 if (IS_ELF)
10097 {
10098 const char **list, **l;
10099
10100 list = bfd_target_list ();
10101 for (l = list; *l != NULL; l++)
10102 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10103 {
10104 default_arch = "x86_64:32";
10105 break;
10106 }
10107 if (*l == NULL)
10108 as_fatal (_("no compiled in support for 32bit x86_64"));
10109 free (list);
10110 }
10111 else
10112 as_fatal (_("32bit x86_64 is only supported for ELF"));
10113 break;
10114 #endif
10115
10116 case OPTION_32:
10117 default_arch = "i386";
10118 break;
10119
10120 case OPTION_DIVIDE:
10121 #ifdef SVR4_COMMENT_CHARS
10122 {
10123 char *n, *t;
10124 const char *s;
10125
10126 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10127 t = n;
10128 for (s = i386_comment_chars; *s != '\0'; s++)
10129 if (*s != '/')
10130 *t++ = *s;
10131 *t = '\0';
10132 i386_comment_chars = n;
10133 }
10134 #endif
10135 break;
10136
10137 case OPTION_MARCH:
10138 saved = xstrdup (arg);
10139 arch = saved;
10140 /* Allow -march=+nosse. */
10141 if (*arch == '+')
10142 arch++;
10143 do
10144 {
10145 if (*arch == '.')
10146 as_fatal (_("invalid -march= option: `%s'"), arg);
10147 next = strchr (arch, '+');
10148 if (next)
10149 *next++ = '\0';
10150 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10151 {
10152 if (strcmp (arch, cpu_arch [j].name) == 0)
10153 {
10154 /* Processor. */
10155 if (! cpu_arch[j].flags.bitfield.cpui386)
10156 continue;
10157
10158 cpu_arch_name = cpu_arch[j].name;
10159 cpu_sub_arch_name = NULL;
10160 cpu_arch_flags = cpu_arch[j].flags;
10161 cpu_arch_isa = cpu_arch[j].type;
10162 cpu_arch_isa_flags = cpu_arch[j].flags;
10163 if (!cpu_arch_tune_set)
10164 {
10165 cpu_arch_tune = cpu_arch_isa;
10166 cpu_arch_tune_flags = cpu_arch_isa_flags;
10167 }
10168 break;
10169 }
10170 else if (*cpu_arch [j].name == '.'
10171 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10172 {
10173 /* ISA extension. */
10174 i386_cpu_flags flags;
10175
10176 flags = cpu_flags_or (cpu_arch_flags,
10177 cpu_arch[j].flags);
10178
10179 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10180 {
10181 if (cpu_sub_arch_name)
10182 {
10183 char *name = cpu_sub_arch_name;
10184 cpu_sub_arch_name = concat (name,
10185 cpu_arch[j].name,
10186 (const char *) NULL);
10187 free (name);
10188 }
10189 else
10190 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10191 cpu_arch_flags = flags;
10192 cpu_arch_isa_flags = flags;
10193 }
10194 break;
10195 }
10196 }
10197
10198 if (j >= ARRAY_SIZE (cpu_arch))
10199 {
10200 /* Disable an ISA extension. */
10201 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10202 if (strcmp (arch, cpu_noarch [j].name) == 0)
10203 {
10204 i386_cpu_flags flags;
10205
10206 flags = cpu_flags_and_not (cpu_arch_flags,
10207 cpu_noarch[j].flags);
10208 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10209 {
10210 if (cpu_sub_arch_name)
10211 {
10212 char *name = cpu_sub_arch_name;
10213 cpu_sub_arch_name = concat (arch,
10214 (const char *) NULL);
10215 free (name);
10216 }
10217 else
10218 cpu_sub_arch_name = xstrdup (arch);
10219 cpu_arch_flags = flags;
10220 cpu_arch_isa_flags = flags;
10221 }
10222 break;
10223 }
10224
10225 if (j >= ARRAY_SIZE (cpu_noarch))
10226 j = ARRAY_SIZE (cpu_arch);
10227 }
10228
10229 if (j >= ARRAY_SIZE (cpu_arch))
10230 as_fatal (_("invalid -march= option: `%s'"), arg);
10231
10232 arch = next;
10233 }
10234 while (next != NULL);
10235 free (saved);
10236 break;
10237
10238 case OPTION_MTUNE:
10239 if (*arg == '.')
10240 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10241 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10242 {
10243 if (strcmp (arg, cpu_arch [j].name) == 0)
10244 {
10245 cpu_arch_tune_set = 1;
10246 cpu_arch_tune = cpu_arch [j].type;
10247 cpu_arch_tune_flags = cpu_arch[j].flags;
10248 break;
10249 }
10250 }
10251 if (j >= ARRAY_SIZE (cpu_arch))
10252 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10253 break;
10254
10255 case OPTION_MMNEMONIC:
10256 if (strcasecmp (arg, "att") == 0)
10257 intel_mnemonic = 0;
10258 else if (strcasecmp (arg, "intel") == 0)
10259 intel_mnemonic = 1;
10260 else
10261 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10262 break;
10263
10264 case OPTION_MSYNTAX:
10265 if (strcasecmp (arg, "att") == 0)
10266 intel_syntax = 0;
10267 else if (strcasecmp (arg, "intel") == 0)
10268 intel_syntax = 1;
10269 else
10270 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10271 break;
10272
10273 case OPTION_MINDEX_REG:
10274 allow_index_reg = 1;
10275 break;
10276
10277 case OPTION_MNAKED_REG:
10278 allow_naked_reg = 1;
10279 break;
10280
10281 case OPTION_MOLD_GCC:
10282 old_gcc = 1;
10283 break;
10284
10285 case OPTION_MSSE2AVX:
10286 sse2avx = 1;
10287 break;
10288
10289 case OPTION_MSSE_CHECK:
10290 if (strcasecmp (arg, "error") == 0)
10291 sse_check = check_error;
10292 else if (strcasecmp (arg, "warning") == 0)
10293 sse_check = check_warning;
10294 else if (strcasecmp (arg, "none") == 0)
10295 sse_check = check_none;
10296 else
10297 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10298 break;
10299
10300 case OPTION_MOPERAND_CHECK:
10301 if (strcasecmp (arg, "error") == 0)
10302 operand_check = check_error;
10303 else if (strcasecmp (arg, "warning") == 0)
10304 operand_check = check_warning;
10305 else if (strcasecmp (arg, "none") == 0)
10306 operand_check = check_none;
10307 else
10308 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10309 break;
10310
10311 case OPTION_MAVXSCALAR:
10312 if (strcasecmp (arg, "128") == 0)
10313 avxscalar = vex128;
10314 else if (strcasecmp (arg, "256") == 0)
10315 avxscalar = vex256;
10316 else
10317 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10318 break;
10319
10320 case OPTION_MADD_BND_PREFIX:
10321 add_bnd_prefix = 1;
10322 break;
10323
10324 case OPTION_MEVEXLIG:
10325 if (strcmp (arg, "128") == 0)
10326 evexlig = evexl128;
10327 else if (strcmp (arg, "256") == 0)
10328 evexlig = evexl256;
10329 else if (strcmp (arg, "512") == 0)
10330 evexlig = evexl512;
10331 else
10332 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10333 break;
10334
10335 case OPTION_MEVEXRCIG:
10336 if (strcmp (arg, "rne") == 0)
10337 evexrcig = rne;
10338 else if (strcmp (arg, "rd") == 0)
10339 evexrcig = rd;
10340 else if (strcmp (arg, "ru") == 0)
10341 evexrcig = ru;
10342 else if (strcmp (arg, "rz") == 0)
10343 evexrcig = rz;
10344 else
10345 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10346 break;
10347
10348 case OPTION_MEVEXWIG:
10349 if (strcmp (arg, "0") == 0)
10350 evexwig = evexw0;
10351 else if (strcmp (arg, "1") == 0)
10352 evexwig = evexw1;
10353 else
10354 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10355 break;
10356
10357 # if defined (TE_PE) || defined (TE_PEP)
10358 case OPTION_MBIG_OBJ:
10359 use_big_obj = 1;
10360 break;
10361 #endif
10362
10363 case OPTION_MOMIT_LOCK_PREFIX:
10364 if (strcasecmp (arg, "yes") == 0)
10365 omit_lock_prefix = 1;
10366 else if (strcasecmp (arg, "no") == 0)
10367 omit_lock_prefix = 0;
10368 else
10369 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10370 break;
10371
10372 case OPTION_MFENCE_AS_LOCK_ADD:
10373 if (strcasecmp (arg, "yes") == 0)
10374 avoid_fence = 1;
10375 else if (strcasecmp (arg, "no") == 0)
10376 avoid_fence = 0;
10377 else
10378 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10379 break;
10380
10381 case OPTION_MRELAX_RELOCATIONS:
10382 if (strcasecmp (arg, "yes") == 0)
10383 generate_relax_relocations = 1;
10384 else if (strcasecmp (arg, "no") == 0)
10385 generate_relax_relocations = 0;
10386 else
10387 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10388 break;
10389
10390 case OPTION_MAMD64:
10391 intel64 = 0;
10392 break;
10393
10394 case OPTION_MINTEL64:
10395 intel64 = 1;
10396 break;
10397
10398 default:
10399 return 0;
10400 }
10401 return 1;
10402 }
10403
10404 #define MESSAGE_TEMPLATE \
10405 " "
10406
10407 static char *
10408 output_message (FILE *stream, char *p, char *message, char *start,
10409 int *left_p, const char *name, int len)
10410 {
10411 int size = sizeof (MESSAGE_TEMPLATE);
10412 int left = *left_p;
10413
10414 /* Reserve 2 spaces for ", " or ",\0" */
10415 left -= len + 2;
10416
10417 /* Check if there is any room. */
10418 if (left >= 0)
10419 {
10420 if (p != start)
10421 {
10422 *p++ = ',';
10423 *p++ = ' ';
10424 }
10425 p = mempcpy (p, name, len);
10426 }
10427 else
10428 {
10429 /* Output the current message now and start a new one. */
10430 *p++ = ',';
10431 *p = '\0';
10432 fprintf (stream, "%s\n", message);
10433 p = start;
10434 left = size - (start - message) - len - 2;
10435
10436 gas_assert (left >= 0);
10437
10438 p = mempcpy (p, name, len);
10439 }
10440
10441 *left_p = left;
10442 return p;
10443 }
10444
10445 static void
10446 show_arch (FILE *stream, int ext, int check)
10447 {
10448 static char message[] = MESSAGE_TEMPLATE;
10449 char *start = message + 27;
10450 char *p;
10451 int size = sizeof (MESSAGE_TEMPLATE);
10452 int left;
10453 const char *name;
10454 int len;
10455 unsigned int j;
10456
10457 p = start;
10458 left = size - (start - message);
10459 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10460 {
10461 /* Should it be skipped? */
10462 if (cpu_arch [j].skip)
10463 continue;
10464
10465 name = cpu_arch [j].name;
10466 len = cpu_arch [j].len;
10467 if (*name == '.')
10468 {
10469 /* It is an extension. Skip if we aren't asked to show it. */
10470 if (ext)
10471 {
10472 name++;
10473 len--;
10474 }
10475 else
10476 continue;
10477 }
10478 else if (ext)
10479 {
10480 /* It is an processor. Skip if we show only extension. */
10481 continue;
10482 }
10483 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10484 {
10485 /* It is an impossible processor - skip. */
10486 continue;
10487 }
10488
10489 p = output_message (stream, p, message, start, &left, name, len);
10490 }
10491
10492 /* Display disabled extensions. */
10493 if (ext)
10494 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10495 {
10496 name = cpu_noarch [j].name;
10497 len = cpu_noarch [j].len;
10498 p = output_message (stream, p, message, start, &left, name,
10499 len);
10500 }
10501
10502 *p = '\0';
10503 fprintf (stream, "%s\n", message);
10504 }
10505
10506 void
10507 md_show_usage (FILE *stream)
10508 {
10509 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10510 fprintf (stream, _("\
10511 -Q ignored\n\
10512 -V print assembler version number\n\
10513 -k ignored\n"));
10514 #endif
10515 fprintf (stream, _("\
10516 -n Do not optimize code alignment\n\
10517 -q quieten some warnings\n"));
10518 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10519 fprintf (stream, _("\
10520 -s ignored\n"));
10521 #endif
10522 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10523 || defined (TE_PE) || defined (TE_PEP))
10524 fprintf (stream, _("\
10525 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10526 #endif
10527 #ifdef SVR4_COMMENT_CHARS
10528 fprintf (stream, _("\
10529 --divide do not treat `/' as a comment character\n"));
10530 #else
10531 fprintf (stream, _("\
10532 --divide ignored\n"));
10533 #endif
10534 fprintf (stream, _("\
10535 -march=CPU[,+EXTENSION...]\n\
10536 generate code for CPU and EXTENSION, CPU is one of:\n"));
10537 show_arch (stream, 0, 1);
10538 fprintf (stream, _("\
10539 EXTENSION is combination of:\n"));
10540 show_arch (stream, 1, 0);
10541 fprintf (stream, _("\
10542 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10543 show_arch (stream, 0, 0);
10544 fprintf (stream, _("\
10545 -msse2avx encode SSE instructions with VEX prefix\n"));
10546 fprintf (stream, _("\
10547 -msse-check=[none|error|warning]\n\
10548 check SSE instructions\n"));
10549 fprintf (stream, _("\
10550 -moperand-check=[none|error|warning]\n\
10551 check operand combinations for validity\n"));
10552 fprintf (stream, _("\
10553 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10554 length\n"));
10555 fprintf (stream, _("\
10556 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10557 length\n"));
10558 fprintf (stream, _("\
10559 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10560 for EVEX.W bit ignored instructions\n"));
10561 fprintf (stream, _("\
10562 -mevexrcig=[rne|rd|ru|rz]\n\
10563 encode EVEX instructions with specific EVEX.RC value\n\
10564 for SAE-only ignored instructions\n"));
10565 fprintf (stream, _("\
10566 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10567 fprintf (stream, _("\
10568 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10569 fprintf (stream, _("\
10570 -mindex-reg support pseudo index registers\n"));
10571 fprintf (stream, _("\
10572 -mnaked-reg don't require `%%' prefix for registers\n"));
10573 fprintf (stream, _("\
10574 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10575 fprintf (stream, _("\
10576 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10577 fprintf (stream, _("\
10578 -mshared disable branch optimization for shared code\n"));
10579 # if defined (TE_PE) || defined (TE_PEP)
10580 fprintf (stream, _("\
10581 -mbig-obj generate big object files\n"));
10582 #endif
10583 fprintf (stream, _("\
10584 -momit-lock-prefix=[no|yes]\n\
10585 strip all lock prefixes\n"));
10586 fprintf (stream, _("\
10587 -mfence-as-lock-add=[no|yes]\n\
10588 encode lfence, mfence and sfence as\n\
10589 lock addl $0x0, (%%{re}sp)\n"));
10590 fprintf (stream, _("\
10591 -mrelax-relocations=[no|yes]\n\
10592 generate relax relocations\n"));
10593 fprintf (stream, _("\
10594 -mamd64 accept only AMD64 ISA\n"));
10595 fprintf (stream, _("\
10596 -mintel64 accept only Intel64 ISA\n"));
10597 }
10598
10599 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10600 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10601 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10602
10603 /* Pick the target format to use. */
10604
10605 const char *
10606 i386_target_format (void)
10607 {
10608 if (!strncmp (default_arch, "x86_64", 6))
10609 {
10610 update_code_flag (CODE_64BIT, 1);
10611 if (default_arch[6] == '\0')
10612 x86_elf_abi = X86_64_ABI;
10613 else
10614 x86_elf_abi = X86_64_X32_ABI;
10615 }
10616 else if (!strcmp (default_arch, "i386"))
10617 update_code_flag (CODE_32BIT, 1);
10618 else if (!strcmp (default_arch, "iamcu"))
10619 {
10620 update_code_flag (CODE_32BIT, 1);
10621 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10622 {
10623 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10624 cpu_arch_name = "iamcu";
10625 cpu_sub_arch_name = NULL;
10626 cpu_arch_flags = iamcu_flags;
10627 cpu_arch_isa = PROCESSOR_IAMCU;
10628 cpu_arch_isa_flags = iamcu_flags;
10629 if (!cpu_arch_tune_set)
10630 {
10631 cpu_arch_tune = cpu_arch_isa;
10632 cpu_arch_tune_flags = cpu_arch_isa_flags;
10633 }
10634 }
10635 else if (cpu_arch_isa != PROCESSOR_IAMCU)
10636 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10637 cpu_arch_name);
10638 }
10639 else
10640 as_fatal (_("unknown architecture"));
10641
10642 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10643 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10644 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10645 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10646
10647 switch (OUTPUT_FLAVOR)
10648 {
10649 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10650 case bfd_target_aout_flavour:
10651 return AOUT_TARGET_FORMAT;
10652 #endif
10653 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10654 # if defined (TE_PE) || defined (TE_PEP)
10655 case bfd_target_coff_flavour:
10656 if (flag_code == CODE_64BIT)
10657 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10658 else
10659 return "pe-i386";
10660 # elif defined (TE_GO32)
10661 case bfd_target_coff_flavour:
10662 return "coff-go32";
10663 # else
10664 case bfd_target_coff_flavour:
10665 return "coff-i386";
10666 # endif
10667 #endif
10668 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10669 case bfd_target_elf_flavour:
10670 {
10671 const char *format;
10672
10673 switch (x86_elf_abi)
10674 {
10675 default:
10676 format = ELF_TARGET_FORMAT;
10677 break;
10678 case X86_64_ABI:
10679 use_rela_relocations = 1;
10680 object_64bit = 1;
10681 format = ELF_TARGET_FORMAT64;
10682 break;
10683 case X86_64_X32_ABI:
10684 use_rela_relocations = 1;
10685 object_64bit = 1;
10686 disallow_64bit_reloc = 1;
10687 format = ELF_TARGET_FORMAT32;
10688 break;
10689 }
10690 if (cpu_arch_isa == PROCESSOR_L1OM)
10691 {
10692 if (x86_elf_abi != X86_64_ABI)
10693 as_fatal (_("Intel L1OM is 64bit only"));
10694 return ELF_TARGET_L1OM_FORMAT;
10695 }
10696 else if (cpu_arch_isa == PROCESSOR_K1OM)
10697 {
10698 if (x86_elf_abi != X86_64_ABI)
10699 as_fatal (_("Intel K1OM is 64bit only"));
10700 return ELF_TARGET_K1OM_FORMAT;
10701 }
10702 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10703 {
10704 if (x86_elf_abi != I386_ABI)
10705 as_fatal (_("Intel MCU is 32bit only"));
10706 return ELF_TARGET_IAMCU_FORMAT;
10707 }
10708 else
10709 return format;
10710 }
10711 #endif
10712 #if defined (OBJ_MACH_O)
10713 case bfd_target_mach_o_flavour:
10714 if (flag_code == CODE_64BIT)
10715 {
10716 use_rela_relocations = 1;
10717 object_64bit = 1;
10718 return "mach-o-x86-64";
10719 }
10720 else
10721 return "mach-o-i386";
10722 #endif
10723 default:
10724 abort ();
10725 return NULL;
10726 }
10727 }
10728
10729 #endif /* OBJ_MAYBE_ more than one */
10730 \f
10731 symbolS *
10732 md_undefined_symbol (char *name)
10733 {
10734 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10735 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10736 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10737 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
10738 {
10739 if (!GOT_symbol)
10740 {
10741 if (symbol_find (name))
10742 as_bad (_("GOT already in symbol table"));
10743 GOT_symbol = symbol_new (name, undefined_section,
10744 (valueT) 0, &zero_address_frag);
10745 };
10746 return GOT_symbol;
10747 }
10748 return 0;
10749 }
10750
10751 /* Round up a section size to the appropriate boundary. */
10752
10753 valueT
10754 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
10755 {
10756 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10757 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10758 {
10759 /* For a.out, force the section size to be aligned. If we don't do
10760 this, BFD will align it for us, but it will not write out the
10761 final bytes of the section. This may be a bug in BFD, but it is
10762 easier to fix it here since that is how the other a.out targets
10763 work. */
10764 int align;
10765
10766 align = bfd_get_section_alignment (stdoutput, segment);
10767 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
10768 }
10769 #endif
10770
10771 return size;
10772 }
10773
10774 /* On the i386, PC-relative offsets are relative to the start of the
10775 next instruction. That is, the address of the offset, plus its
10776 size, since the offset is always the last part of the insn. */
10777
10778 long
10779 md_pcrel_from (fixS *fixP)
10780 {
10781 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10782 }
10783
10784 #ifndef I386COFF
10785
10786 static void
10787 s_bss (int ignore ATTRIBUTE_UNUSED)
10788 {
10789 int temp;
10790
10791 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10792 if (IS_ELF)
10793 obj_elf_section_change_hook ();
10794 #endif
10795 temp = get_absolute_expression ();
10796 subseg_set (bss_section, (subsegT) temp);
10797 demand_empty_rest_of_line ();
10798 }
10799
10800 #endif
10801
10802 void
10803 i386_validate_fix (fixS *fixp)
10804 {
10805 if (fixp->fx_subsy)
10806 {
10807 if (fixp->fx_subsy == GOT_symbol)
10808 {
10809 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10810 {
10811 if (!object_64bit)
10812 abort ();
10813 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10814 if (fixp->fx_tcbit2)
10815 fixp->fx_r_type = (fixp->fx_tcbit
10816 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10817 : BFD_RELOC_X86_64_GOTPCRELX);
10818 else
10819 #endif
10820 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10821 }
10822 else
10823 {
10824 if (!object_64bit)
10825 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10826 else
10827 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10828 }
10829 fixp->fx_subsy = 0;
10830 }
10831 }
10832 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10833 else if (!object_64bit)
10834 {
10835 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10836 && fixp->fx_tcbit2)
10837 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10838 }
10839 #endif
10840 }
10841
10842 arelent *
10843 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
10844 {
10845 arelent *rel;
10846 bfd_reloc_code_real_type code;
10847
10848 switch (fixp->fx_r_type)
10849 {
10850 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10851 case BFD_RELOC_SIZE32:
10852 case BFD_RELOC_SIZE64:
10853 if (S_IS_DEFINED (fixp->fx_addsy)
10854 && !S_IS_EXTERNAL (fixp->fx_addsy))
10855 {
10856 /* Resolve size relocation against local symbol to size of
10857 the symbol plus addend. */
10858 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10859 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10860 && !fits_in_unsigned_long (value))
10861 as_bad_where (fixp->fx_file, fixp->fx_line,
10862 _("symbol size computation overflow"));
10863 fixp->fx_addsy = NULL;
10864 fixp->fx_subsy = NULL;
10865 md_apply_fix (fixp, (valueT *) &value, NULL);
10866 return NULL;
10867 }
10868 #endif
10869 /* Fall through. */
10870
10871 case BFD_RELOC_X86_64_PLT32:
10872 case BFD_RELOC_X86_64_GOT32:
10873 case BFD_RELOC_X86_64_GOTPCREL:
10874 case BFD_RELOC_X86_64_GOTPCRELX:
10875 case BFD_RELOC_X86_64_REX_GOTPCRELX:
10876 case BFD_RELOC_386_PLT32:
10877 case BFD_RELOC_386_GOT32:
10878 case BFD_RELOC_386_GOT32X:
10879 case BFD_RELOC_386_GOTOFF:
10880 case BFD_RELOC_386_GOTPC:
10881 case BFD_RELOC_386_TLS_GD:
10882 case BFD_RELOC_386_TLS_LDM:
10883 case BFD_RELOC_386_TLS_LDO_32:
10884 case BFD_RELOC_386_TLS_IE_32:
10885 case BFD_RELOC_386_TLS_IE:
10886 case BFD_RELOC_386_TLS_GOTIE:
10887 case BFD_RELOC_386_TLS_LE_32:
10888 case BFD_RELOC_386_TLS_LE:
10889 case BFD_RELOC_386_TLS_GOTDESC:
10890 case BFD_RELOC_386_TLS_DESC_CALL:
10891 case BFD_RELOC_X86_64_TLSGD:
10892 case BFD_RELOC_X86_64_TLSLD:
10893 case BFD_RELOC_X86_64_DTPOFF32:
10894 case BFD_RELOC_X86_64_DTPOFF64:
10895 case BFD_RELOC_X86_64_GOTTPOFF:
10896 case BFD_RELOC_X86_64_TPOFF32:
10897 case BFD_RELOC_X86_64_TPOFF64:
10898 case BFD_RELOC_X86_64_GOTOFF64:
10899 case BFD_RELOC_X86_64_GOTPC32:
10900 case BFD_RELOC_X86_64_GOT64:
10901 case BFD_RELOC_X86_64_GOTPCREL64:
10902 case BFD_RELOC_X86_64_GOTPC64:
10903 case BFD_RELOC_X86_64_GOTPLT64:
10904 case BFD_RELOC_X86_64_PLTOFF64:
10905 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10906 case BFD_RELOC_X86_64_TLSDESC_CALL:
10907 case BFD_RELOC_RVA:
10908 case BFD_RELOC_VTABLE_ENTRY:
10909 case BFD_RELOC_VTABLE_INHERIT:
10910 #ifdef TE_PE
10911 case BFD_RELOC_32_SECREL:
10912 #endif
10913 code = fixp->fx_r_type;
10914 break;
10915 case BFD_RELOC_X86_64_32S:
10916 if (!fixp->fx_pcrel)
10917 {
10918 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10919 code = fixp->fx_r_type;
10920 break;
10921 }
10922 /* Fall through. */
10923 default:
10924 if (fixp->fx_pcrel)
10925 {
10926 switch (fixp->fx_size)
10927 {
10928 default:
10929 as_bad_where (fixp->fx_file, fixp->fx_line,
10930 _("can not do %d byte pc-relative relocation"),
10931 fixp->fx_size);
10932 code = BFD_RELOC_32_PCREL;
10933 break;
10934 case 1: code = BFD_RELOC_8_PCREL; break;
10935 case 2: code = BFD_RELOC_16_PCREL; break;
10936 case 4: code = BFD_RELOC_32_PCREL; break;
10937 #ifdef BFD64
10938 case 8: code = BFD_RELOC_64_PCREL; break;
10939 #endif
10940 }
10941 }
10942 else
10943 {
10944 switch (fixp->fx_size)
10945 {
10946 default:
10947 as_bad_where (fixp->fx_file, fixp->fx_line,
10948 _("can not do %d byte relocation"),
10949 fixp->fx_size);
10950 code = BFD_RELOC_32;
10951 break;
10952 case 1: code = BFD_RELOC_8; break;
10953 case 2: code = BFD_RELOC_16; break;
10954 case 4: code = BFD_RELOC_32; break;
10955 #ifdef BFD64
10956 case 8: code = BFD_RELOC_64; break;
10957 #endif
10958 }
10959 }
10960 break;
10961 }
10962
10963 if ((code == BFD_RELOC_32
10964 || code == BFD_RELOC_32_PCREL
10965 || code == BFD_RELOC_X86_64_32S)
10966 && GOT_symbol
10967 && fixp->fx_addsy == GOT_symbol)
10968 {
10969 if (!object_64bit)
10970 code = BFD_RELOC_386_GOTPC;
10971 else
10972 code = BFD_RELOC_X86_64_GOTPC32;
10973 }
10974 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10975 && GOT_symbol
10976 && fixp->fx_addsy == GOT_symbol)
10977 {
10978 code = BFD_RELOC_X86_64_GOTPC64;
10979 }
10980
10981 rel = XNEW (arelent);
10982 rel->sym_ptr_ptr = XNEW (asymbol *);
10983 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
10984
10985 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
10986
10987 if (!use_rela_relocations)
10988 {
10989 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10990 vtable entry to be used in the relocation's section offset. */
10991 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10992 rel->address = fixp->fx_offset;
10993 #if defined (OBJ_COFF) && defined (TE_PE)
10994 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10995 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10996 else
10997 #endif
10998 rel->addend = 0;
10999 }
11000 /* Use the rela in 64bit mode. */
11001 else
11002 {
11003 if (disallow_64bit_reloc)
11004 switch (code)
11005 {
11006 case BFD_RELOC_X86_64_DTPOFF64:
11007 case BFD_RELOC_X86_64_TPOFF64:
11008 case BFD_RELOC_64_PCREL:
11009 case BFD_RELOC_X86_64_GOTOFF64:
11010 case BFD_RELOC_X86_64_GOT64:
11011 case BFD_RELOC_X86_64_GOTPCREL64:
11012 case BFD_RELOC_X86_64_GOTPC64:
11013 case BFD_RELOC_X86_64_GOTPLT64:
11014 case BFD_RELOC_X86_64_PLTOFF64:
11015 as_bad_where (fixp->fx_file, fixp->fx_line,
11016 _("cannot represent relocation type %s in x32 mode"),
11017 bfd_get_reloc_code_name (code));
11018 break;
11019 default:
11020 break;
11021 }
11022
11023 if (!fixp->fx_pcrel)
11024 rel->addend = fixp->fx_offset;
11025 else
11026 switch (code)
11027 {
11028 case BFD_RELOC_X86_64_PLT32:
11029 case BFD_RELOC_X86_64_GOT32:
11030 case BFD_RELOC_X86_64_GOTPCREL:
11031 case BFD_RELOC_X86_64_GOTPCRELX:
11032 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11033 case BFD_RELOC_X86_64_TLSGD:
11034 case BFD_RELOC_X86_64_TLSLD:
11035 case BFD_RELOC_X86_64_GOTTPOFF:
11036 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11037 case BFD_RELOC_X86_64_TLSDESC_CALL:
11038 rel->addend = fixp->fx_offset - fixp->fx_size;
11039 break;
11040 default:
11041 rel->addend = (section->vma
11042 - fixp->fx_size
11043 + fixp->fx_addnumber
11044 + md_pcrel_from (fixp));
11045 break;
11046 }
11047 }
11048
11049 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11050 if (rel->howto == NULL)
11051 {
11052 as_bad_where (fixp->fx_file, fixp->fx_line,
11053 _("cannot represent relocation type %s"),
11054 bfd_get_reloc_code_name (code));
11055 /* Set howto to a garbage value so that we can keep going. */
11056 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11057 gas_assert (rel->howto != NULL);
11058 }
11059
11060 return rel;
11061 }
11062
11063 #include "tc-i386-intel.c"
11064
11065 void
11066 tc_x86_parse_to_dw2regnum (expressionS *exp)
11067 {
11068 int saved_naked_reg;
11069 char saved_register_dot;
11070
11071 saved_naked_reg = allow_naked_reg;
11072 allow_naked_reg = 1;
11073 saved_register_dot = register_chars['.'];
11074 register_chars['.'] = '.';
11075 allow_pseudo_reg = 1;
11076 expression_and_evaluate (exp);
11077 allow_pseudo_reg = 0;
11078 register_chars['.'] = saved_register_dot;
11079 allow_naked_reg = saved_naked_reg;
11080
11081 if (exp->X_op == O_register && exp->X_add_number >= 0)
11082 {
11083 if ((addressT) exp->X_add_number < i386_regtab_size)
11084 {
11085 exp->X_op = O_constant;
11086 exp->X_add_number = i386_regtab[exp->X_add_number]
11087 .dw2_regnum[flag_code >> 1];
11088 }
11089 else
11090 exp->X_op = O_illegal;
11091 }
11092 }
11093
11094 void
11095 tc_x86_frame_initial_instructions (void)
11096 {
11097 static unsigned int sp_regno[2];
11098
11099 if (!sp_regno[flag_code >> 1])
11100 {
11101 char *saved_input = input_line_pointer;
11102 char sp[][4] = {"esp", "rsp"};
11103 expressionS exp;
11104
11105 input_line_pointer = sp[flag_code >> 1];
11106 tc_x86_parse_to_dw2regnum (&exp);
11107 gas_assert (exp.X_op == O_constant);
11108 sp_regno[flag_code >> 1] = exp.X_add_number;
11109 input_line_pointer = saved_input;
11110 }
11111
11112 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11113 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11114 }
11115
11116 int
11117 x86_dwarf2_addr_size (void)
11118 {
11119 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11120 if (x86_elf_abi == X86_64_X32_ABI)
11121 return 4;
11122 #endif
11123 return bfd_arch_bits_per_address (stdoutput) / 8;
11124 }
11125
11126 int
11127 i386_elf_section_type (const char *str, size_t len)
11128 {
11129 if (flag_code == CODE_64BIT
11130 && len == sizeof ("unwind") - 1
11131 && strncmp (str, "unwind", 6) == 0)
11132 return SHT_X86_64_UNWIND;
11133
11134 return -1;
11135 }
11136
11137 #ifdef TE_SOLARIS
11138 void
11139 i386_solaris_fix_up_eh_frame (segT sec)
11140 {
11141 if (flag_code == CODE_64BIT)
11142 elf_section_type (sec) = SHT_X86_64_UNWIND;
11143 }
11144 #endif
11145
11146 #ifdef TE_PE
11147 void
11148 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11149 {
11150 expressionS exp;
11151
11152 exp.X_op = O_secrel;
11153 exp.X_add_symbol = symbol;
11154 exp.X_add_number = 0;
11155 emit_expr (&exp, size);
11156 }
11157 #endif
11158
11159 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11160 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11161
11162 bfd_vma
11163 x86_64_section_letter (int letter, const char **ptr_msg)
11164 {
11165 if (flag_code == CODE_64BIT)
11166 {
11167 if (letter == 'l')
11168 return SHF_X86_64_LARGE;
11169
11170 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11171 }
11172 else
11173 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11174 return -1;
11175 }
11176
11177 bfd_vma
11178 x86_64_section_word (char *str, size_t len)
11179 {
11180 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11181 return SHF_X86_64_LARGE;
11182
11183 return -1;
11184 }
11185
11186 static void
11187 handle_large_common (int small ATTRIBUTE_UNUSED)
11188 {
11189 if (flag_code != CODE_64BIT)
11190 {
11191 s_comm_internal (0, elf_common_parse);
11192 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11193 }
11194 else
11195 {
11196 static segT lbss_section;
11197 asection *saved_com_section_ptr = elf_com_section_ptr;
11198 asection *saved_bss_section = bss_section;
11199
11200 if (lbss_section == NULL)
11201 {
11202 flagword applicable;
11203 segT seg = now_seg;
11204 subsegT subseg = now_subseg;
11205
11206 /* The .lbss section is for local .largecomm symbols. */
11207 lbss_section = subseg_new (".lbss", 0);
11208 applicable = bfd_applicable_section_flags (stdoutput);
11209 bfd_set_section_flags (stdoutput, lbss_section,
11210 applicable & SEC_ALLOC);
11211 seg_info (lbss_section)->bss = 1;
11212
11213 subseg_set (seg, subseg);
11214 }
11215
11216 elf_com_section_ptr = &_bfd_elf_large_com_section;
11217 bss_section = lbss_section;
11218
11219 s_comm_internal (0, elf_common_parse);
11220
11221 elf_com_section_ptr = saved_com_section_ptr;
11222 bss_section = saved_bss_section;
11223 }
11224 }
11225 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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