1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
136 unsigned int negated
; /* turn off indicated flags. */
140 static void update_code_flag (int, int);
141 static void set_code_flag (int);
142 static void set_16bit_gcc_code_flag (int);
143 static void set_intel_syntax (int);
144 static void set_intel_mnemonic (int);
145 static void set_allow_index_reg (int);
146 static void set_check (int);
147 static void set_cpu_arch (int);
149 static void pe_directive_secrel (int);
151 static void signed_cons (int);
152 static char *output_invalid (int c
);
153 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
155 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
157 static int i386_att_operand (char *);
158 static int i386_intel_operand (char *, int);
159 static int i386_intel_simplify (expressionS
*);
160 static int i386_intel_parse_name (const char *, expressionS
*);
161 static const reg_entry
*parse_register (char *, char **);
162 static char *parse_insn (char *, char *);
163 static char *parse_operands (char *, const char *);
164 static void swap_operands (void);
165 static void swap_2_operands (int, int);
166 static void optimize_imm (void);
167 static void optimize_disp (void);
168 static const insn_template
*match_template (void);
169 static int check_string (void);
170 static int process_suffix (void);
171 static int check_byte_reg (void);
172 static int check_long_reg (void);
173 static int check_qword_reg (void);
174 static int check_word_reg (void);
175 static int finalize_imm (void);
176 static int process_operands (void);
177 static const seg_entry
*build_modrm_byte (void);
178 static void output_insn (void);
179 static void output_imm (fragS
*, offsetT
);
180 static void output_disp (fragS
*, offsetT
);
182 static void s_bss (int);
184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
188 static const char *default_arch
= DEFAULT_ARCH
;
190 /* This struct describes rounding control and SAE in the instruction. */
204 static struct RC_Operation rc_op
;
206 /* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209 struct Mask_Operation
211 const reg_entry
*mask
;
212 unsigned int zeroing
;
213 /* The operand where this operation is associated. */
217 static struct Mask_Operation mask_op
;
219 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
221 struct Broadcast_Operation
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
226 /* Index of broadcasted operand. */
230 static struct Broadcast_Operation broadcast_op
;
235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes
[4];
238 /* Destination or source register specifier. */
239 const reg_entry
*register_specifier
;
242 /* 'md_assemble ()' gathers together information and puts it into a
249 const reg_entry
*regs
;
254 operand_size_mismatch
,
255 operand_type_mismatch
,
256 register_type_mismatch
,
257 number_of_operands_mismatch
,
258 invalid_instruction_suffix
,
261 unsupported_with_intel_mnemonic
,
264 invalid_vsib_address
,
265 invalid_vector_register_set
,
266 unsupported_vector_index_register
,
267 unsupported_broadcast
,
268 broadcast_not_on_src_operand
,
271 mask_not_on_destination
,
274 rc_sae_operand_not_last_imm
,
275 invalid_register_operand
,
281 /* TM holds the template for the insn were currently assembling. */
284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
288 /* OPERANDS gives the number of given operands. */
289 unsigned int operands
;
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
294 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
296 /* TYPES [i] is the type (see above #defines) which tells us how to
297 use OP[i] for the corresponding operand. */
298 i386_operand_type types
[MAX_OPERANDS
];
300 /* Displacement expression, immediate expression, or register for each
302 union i386_op op
[MAX_OPERANDS
];
304 /* Flags for operands. */
305 unsigned int flags
[MAX_OPERANDS
];
306 #define Operand_PCrel 1
308 /* Relocation type for operand */
309 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry
*base_reg
;
314 const reg_entry
*index_reg
;
315 unsigned int log2_scale_factor
;
317 /* SEG gives the seg_entries of this insn. They are zero unless
318 explicit segment overrides are given. */
319 const seg_entry
*seg
[2];
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes
;
324 unsigned char prefix
[MAX_PREFIXES
];
326 /* RM and SIB are the modrm byte and the sib byte where the
327 addressing modes of this insn are encoded. */
334 /* Masking attributes. */
335 struct Mask_Operation
*mask
;
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation
*rounding
;
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation
*broadcast
;
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift
;
346 /* Swap operand in encoding. */
347 unsigned int swap_operand
;
349 /* Prefer 8bit or 32bit displacement in encoding. */
352 disp_encoding_default
= 0,
358 const char *rep_prefix
;
361 const char *hle_prefix
;
363 /* Have BND prefix. */
364 const char *bnd_prefix
;
366 /* Need VREX to support upper 16 registers. */
370 enum i386_error error
;
373 typedef struct _i386_insn i386_insn
;
375 /* Link RC type with corresponding string, that'll be looked for in
384 static const struct RC_name RC_NamesTable
[] =
386 { rne
, STRING_COMMA_LEN ("rn-sae") },
387 { rd
, STRING_COMMA_LEN ("rd-sae") },
388 { ru
, STRING_COMMA_LEN ("ru-sae") },
389 { rz
, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly
, STRING_COMMA_LEN ("sae") },
393 /* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
395 const char extra_symbol_chars
[] = "*%-([{"
404 #if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
406 && !defined (TE_GNU) \
407 && !defined (TE_LINUX) \
408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
410 && !defined (TE_FreeBSD) \
411 && !defined (TE_DragonFly) \
412 && !defined (TE_NetBSD)))
413 /* This array holds the chars that always start a comment. If the
414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416 const char *i386_comment_chars
= "#/";
417 #define SVR4_COMMENT_CHARS 1
418 #define PREFIX_SEPARATOR '\\'
421 const char *i386_comment_chars
= "#";
422 #define PREFIX_SEPARATOR '/'
425 /* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
429 first line of the input file. This is because the compiler outputs
430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
432 '/' isn't otherwise defined. */
433 const char line_comment_chars
[] = "#/";
435 const char line_separator_chars
[] = ";";
437 /* Chars that can be used to separate mant from exp in floating point
439 const char EXP_CHARS
[] = "eE";
441 /* Chars that mean this number is a floating point constant
444 const char FLT_CHARS
[] = "fFdDxX";
446 /* Tables for lexical analysis. */
447 static char mnemonic_chars
[256];
448 static char register_chars
[256];
449 static char operand_chars
[256];
450 static char identifier_chars
[256];
451 static char digit_chars
[256];
453 /* Lexical macros. */
454 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455 #define is_operand_char(x) (operand_chars[(unsigned char) x])
456 #define is_register_char(x) (register_chars[(unsigned char) x])
457 #define is_space_char(x) ((x) == ' ')
458 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459 #define is_digit_char(x) (digit_chars[(unsigned char) x])
461 /* All non-digit non-letter characters that may occur in an operand. */
462 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
464 /* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
467 assembler instruction). */
468 static char save_stack
[32];
469 static char *save_stack_p
;
470 #define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472 #define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
475 /* The instruction we're assembling. */
478 /* Possible templates for current insn. */
479 static const templates
*current_templates
;
481 /* Per instruction expressionS buffers: max displacements & immediates. */
482 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
483 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
485 /* Current operand we are working on. */
486 static int this_operand
= -1;
488 /* We support four different modes. FLAG_CODE variable is used to distinguish
496 static enum flag_code flag_code
;
497 static unsigned int object_64bit
;
498 static unsigned int disallow_64bit_reloc
;
499 static int use_rela_relocations
= 0;
501 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
505 /* The ELF ABI to use. */
513 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
516 /* 1 for intel syntax,
518 static int intel_syntax
= 0;
520 /* 1 for intel mnemonic,
521 0 if att mnemonic. */
522 static int intel_mnemonic
= !SYSV386_COMPAT
;
524 /* 1 if support old (<= 2.8.1) versions of gcc. */
525 static int old_gcc
= OLDGCC_COMPAT
;
527 /* 1 if pseudo registers are permitted. */
528 static int allow_pseudo_reg
= 0;
530 /* 1 if register prefix % not required. */
531 static int allow_naked_reg
= 0;
533 /* 1 if the assembler should add BND prefix for all control-tranferring
534 instructions supporting it, even if this prefix wasn't specified
536 static int add_bnd_prefix
= 0;
538 /* 1 if pseudo index register, eiz/riz, is allowed . */
539 static int allow_index_reg
= 0;
541 static enum check_kind
547 sse_check
, operand_check
= check_warning
;
549 /* Register prefix used for error message. */
550 static const char *register_prefix
= "%";
552 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
553 leave, push, and pop instructions so that gcc has the same stack
554 frame as in 32 bit mode. */
555 static char stackop_size
= '\0';
557 /* Non-zero to optimize code alignment. */
558 int optimize_align_code
= 1;
560 /* Non-zero to quieten some warnings. */
561 static int quiet_warnings
= 0;
564 static const char *cpu_arch_name
= NULL
;
565 static char *cpu_sub_arch_name
= NULL
;
567 /* CPU feature flags. */
568 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
570 /* If we have selected a cpu we are generating instructions for. */
571 static int cpu_arch_tune_set
= 0;
573 /* Cpu we are generating instructions for. */
574 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
576 /* CPU feature flags of cpu we are generating instructions for. */
577 static i386_cpu_flags cpu_arch_tune_flags
;
579 /* CPU instruction set architecture used. */
580 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
582 /* CPU feature flags of instruction set architecture used. */
583 i386_cpu_flags cpu_arch_isa_flags
;
585 /* If set, conditional jumps are not automatically promoted to handle
586 larger than a byte offset. */
587 static unsigned int no_cond_jump_promotion
= 0;
589 /* Encode SSE instructions with VEX prefix. */
590 static unsigned int sse2avx
;
592 /* Encode scalar AVX instructions with specific vector length. */
599 /* Encode scalar EVEX LIG instructions with specific vector length. */
607 /* Encode EVEX WIG instructions with specific evex.w. */
614 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
615 static symbolS
*GOT_symbol
;
617 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
618 unsigned int x86_dwarf2_return_column
;
620 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
621 int x86_cie_data_alignment
;
623 /* Interface to relax_segment.
624 There are 3 major relax states for 386 jump insns because the
625 different types of jumps add different sizes to frags when we're
626 figuring out what sort of jump to choose to reach a given label. */
629 #define UNCOND_JUMP 0
631 #define COND_JUMP86 2
636 #define SMALL16 (SMALL | CODE16)
638 #define BIG16 (BIG | CODE16)
642 #define INLINE __inline__
648 #define ENCODE_RELAX_STATE(type, size) \
649 ((relax_substateT) (((type) << 2) | (size)))
650 #define TYPE_FROM_RELAX_STATE(s) \
652 #define DISP_SIZE_FROM_RELAX_STATE(s) \
653 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
655 /* This table is used by relax_frag to promote short jumps to long
656 ones where necessary. SMALL (short) jumps may be promoted to BIG
657 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
658 don't allow a short jump in a 32 bit code segment to be promoted to
659 a 16 bit offset jump because it's slower (requires data size
660 prefix), and doesn't work, unless the destination is in the bottom
661 64k of the code segment (The top 16 bits of eip are zeroed). */
663 const relax_typeS md_relax_table
[] =
666 1) most positive reach of this state,
667 2) most negative reach of this state,
668 3) how many bytes this mode will have in the variable part of the frag
669 4) which index into the table to try if we can't fit into this one. */
671 /* UNCOND_JUMP states. */
672 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
673 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
674 /* dword jmp adds 4 bytes to frag:
675 0 extra opcode bytes, 4 displacement bytes. */
677 /* word jmp adds 2 byte2 to frag:
678 0 extra opcode bytes, 2 displacement bytes. */
681 /* COND_JUMP states. */
682 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
683 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
684 /* dword conditionals adds 5 bytes to frag:
685 1 extra opcode byte, 4 displacement bytes. */
687 /* word conditionals add 3 bytes to frag:
688 1 extra opcode byte, 2 displacement bytes. */
691 /* COND_JUMP86 states. */
692 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
693 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
694 /* dword conditionals adds 5 bytes to frag:
695 1 extra opcode byte, 4 displacement bytes. */
697 /* word conditionals add 4 bytes to frag:
698 1 displacement byte and a 3 byte long branch insn. */
702 static const arch_entry cpu_arch
[] =
704 /* Do not replace the first two entries - i386_target_format()
705 relies on them being there in this order. */
706 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
707 CPU_GENERIC32_FLAGS
, 0, 0 },
708 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
709 CPU_GENERIC64_FLAGS
, 0, 0 },
710 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
711 CPU_NONE_FLAGS
, 0, 0 },
712 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
713 CPU_I186_FLAGS
, 0, 0 },
714 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
715 CPU_I286_FLAGS
, 0, 0 },
716 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
717 CPU_I386_FLAGS
, 0, 0 },
718 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
719 CPU_I486_FLAGS
, 0, 0 },
720 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
721 CPU_I586_FLAGS
, 0, 0 },
722 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
723 CPU_I686_FLAGS
, 0, 0 },
724 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
725 CPU_I586_FLAGS
, 0, 0 },
726 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
727 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
728 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
729 CPU_P2_FLAGS
, 0, 0 },
730 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
731 CPU_P3_FLAGS
, 0, 0 },
732 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
733 CPU_P4_FLAGS
, 0, 0 },
734 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
735 CPU_CORE_FLAGS
, 0, 0 },
736 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
737 CPU_NOCONA_FLAGS
, 0, 0 },
738 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
739 CPU_CORE_FLAGS
, 1, 0 },
740 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
741 CPU_CORE_FLAGS
, 0, 0 },
742 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
743 CPU_CORE2_FLAGS
, 1, 0 },
744 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
745 CPU_CORE2_FLAGS
, 0, 0 },
746 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
747 CPU_COREI7_FLAGS
, 0, 0 },
748 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
749 CPU_L1OM_FLAGS
, 0, 0 },
750 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
751 CPU_K1OM_FLAGS
, 0, 0 },
752 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
753 CPU_K6_FLAGS
, 0, 0 },
754 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
755 CPU_K6_2_FLAGS
, 0, 0 },
756 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
757 CPU_ATHLON_FLAGS
, 0, 0 },
758 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
759 CPU_K8_FLAGS
, 1, 0 },
760 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
761 CPU_K8_FLAGS
, 0, 0 },
762 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
763 CPU_K8_FLAGS
, 0, 0 },
764 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
765 CPU_AMDFAM10_FLAGS
, 0, 0 },
766 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
767 CPU_BDVER1_FLAGS
, 0, 0 },
768 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
769 CPU_BDVER2_FLAGS
, 0, 0 },
770 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
771 CPU_BDVER3_FLAGS
, 0, 0 },
772 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
773 CPU_BDVER4_FLAGS
, 0, 0 },
774 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
775 CPU_BTVER1_FLAGS
, 0, 0 },
776 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
777 CPU_BTVER2_FLAGS
, 0, 0 },
778 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
779 CPU_8087_FLAGS
, 0, 0 },
780 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
781 CPU_287_FLAGS
, 0, 0 },
782 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
783 CPU_387_FLAGS
, 0, 0 },
784 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
785 CPU_ANY87_FLAGS
, 0, 1 },
786 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
787 CPU_MMX_FLAGS
, 0, 0 },
788 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
789 CPU_3DNOWA_FLAGS
, 0, 1 },
790 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
791 CPU_SSE_FLAGS
, 0, 0 },
792 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
793 CPU_SSE2_FLAGS
, 0, 0 },
794 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
795 CPU_SSE3_FLAGS
, 0, 0 },
796 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
797 CPU_SSSE3_FLAGS
, 0, 0 },
798 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
799 CPU_SSE4_1_FLAGS
, 0, 0 },
800 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
801 CPU_SSE4_2_FLAGS
, 0, 0 },
802 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
803 CPU_SSE4_2_FLAGS
, 0, 0 },
804 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
805 CPU_ANY_SSE_FLAGS
, 0, 1 },
806 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
807 CPU_AVX_FLAGS
, 0, 0 },
808 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
809 CPU_AVX2_FLAGS
, 0, 0 },
810 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
811 CPU_AVX512F_FLAGS
, 0, 0 },
812 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
813 CPU_AVX512CD_FLAGS
, 0, 0 },
814 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
815 CPU_AVX512ER_FLAGS
, 0, 0 },
816 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
817 CPU_AVX512PF_FLAGS
, 0, 0 },
818 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
819 CPU_ANY_AVX_FLAGS
, 0, 1 },
820 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
821 CPU_VMX_FLAGS
, 0, 0 },
822 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
823 CPU_VMFUNC_FLAGS
, 0, 0 },
824 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
825 CPU_SMX_FLAGS
, 0, 0 },
826 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
827 CPU_XSAVE_FLAGS
, 0, 0 },
828 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
829 CPU_XSAVEOPT_FLAGS
, 0, 0 },
830 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
831 CPU_AES_FLAGS
, 0, 0 },
832 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
833 CPU_PCLMUL_FLAGS
, 0, 0 },
834 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
835 CPU_PCLMUL_FLAGS
, 1, 0 },
836 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
837 CPU_FSGSBASE_FLAGS
, 0, 0 },
838 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
839 CPU_RDRND_FLAGS
, 0, 0 },
840 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
841 CPU_F16C_FLAGS
, 0, 0 },
842 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
843 CPU_BMI2_FLAGS
, 0, 0 },
844 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
845 CPU_FMA_FLAGS
, 0, 0 },
846 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
847 CPU_FMA4_FLAGS
, 0, 0 },
848 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
849 CPU_XOP_FLAGS
, 0, 0 },
850 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
851 CPU_LWP_FLAGS
, 0, 0 },
852 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
853 CPU_MOVBE_FLAGS
, 0, 0 },
854 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
855 CPU_CX16_FLAGS
, 0, 0 },
856 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
857 CPU_EPT_FLAGS
, 0, 0 },
858 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
859 CPU_LZCNT_FLAGS
, 0, 0 },
860 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
861 CPU_HLE_FLAGS
, 0, 0 },
862 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
863 CPU_RTM_FLAGS
, 0, 0 },
864 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
865 CPU_INVPCID_FLAGS
, 0, 0 },
866 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
867 CPU_CLFLUSH_FLAGS
, 0, 0 },
868 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
869 CPU_NOP_FLAGS
, 0, 0 },
870 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
871 CPU_SYSCALL_FLAGS
, 0, 0 },
872 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
873 CPU_RDTSCP_FLAGS
, 0, 0 },
874 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
875 CPU_3DNOW_FLAGS
, 0, 0 },
876 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
877 CPU_3DNOWA_FLAGS
, 0, 0 },
878 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
879 CPU_PADLOCK_FLAGS
, 0, 0 },
880 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
881 CPU_SVME_FLAGS
, 1, 0 },
882 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
883 CPU_SVME_FLAGS
, 0, 0 },
884 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
885 CPU_SSE4A_FLAGS
, 0, 0 },
886 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
887 CPU_ABM_FLAGS
, 0, 0 },
888 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
889 CPU_BMI_FLAGS
, 0, 0 },
890 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
891 CPU_TBM_FLAGS
, 0, 0 },
892 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
893 CPU_ADX_FLAGS
, 0, 0 },
894 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
895 CPU_RDSEED_FLAGS
, 0, 0 },
896 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
897 CPU_PRFCHW_FLAGS
, 0, 0 },
898 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
899 CPU_SMAP_FLAGS
, 0, 0 },
900 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
901 CPU_MPX_FLAGS
, 0, 0 },
902 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
903 CPU_SHA_FLAGS
, 0, 0 },
904 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
905 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
906 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
907 CPU_XSAVEC_FLAGS
, 0, 0 },
908 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
909 CPU_XSAVES_FLAGS
, 0, 0 },
910 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
911 CPU_PREFETCHWT1_FLAGS
, 0, 0 },
915 /* Like s_lcomm_internal in gas/read.c but the alignment string
916 is allowed to be optional. */
919 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
926 && *input_line_pointer
== ',')
928 align
= parse_align (needs_align
- 1);
930 if (align
== (addressT
) -1)
945 bss_alloc (symbolP
, size
, align
);
950 pe_lcomm (int needs_align
)
952 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
956 const pseudo_typeS md_pseudo_table
[] =
958 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
959 {"align", s_align_bytes
, 0},
961 {"align", s_align_ptwo
, 0},
963 {"arch", set_cpu_arch
, 0},
967 {"lcomm", pe_lcomm
, 1},
969 {"ffloat", float_cons
, 'f'},
970 {"dfloat", float_cons
, 'd'},
971 {"tfloat", float_cons
, 'x'},
973 {"slong", signed_cons
, 4},
974 {"noopt", s_ignore
, 0},
975 {"optim", s_ignore
, 0},
976 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
977 {"code16", set_code_flag
, CODE_16BIT
},
978 {"code32", set_code_flag
, CODE_32BIT
},
979 {"code64", set_code_flag
, CODE_64BIT
},
980 {"intel_syntax", set_intel_syntax
, 1},
981 {"att_syntax", set_intel_syntax
, 0},
982 {"intel_mnemonic", set_intel_mnemonic
, 1},
983 {"att_mnemonic", set_intel_mnemonic
, 0},
984 {"allow_index_reg", set_allow_index_reg
, 1},
985 {"disallow_index_reg", set_allow_index_reg
, 0},
986 {"sse_check", set_check
, 0},
987 {"operand_check", set_check
, 1},
988 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
989 {"largecomm", handle_large_common
, 0},
991 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
992 {"loc", dwarf2_directive_loc
, 0},
993 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
996 {"secrel32", pe_directive_secrel
, 0},
1001 /* For interface with expression (). */
1002 extern char *input_line_pointer
;
1004 /* Hash table for instruction mnemonic lookup. */
1005 static struct hash_control
*op_hash
;
1007 /* Hash table for register lookup. */
1008 static struct hash_control
*reg_hash
;
1011 i386_align_code (fragS
*fragP
, int count
)
1013 /* Various efficient no-op patterns for aligning code labels.
1014 Note: Don't try to assemble the instructions in the comments.
1015 0L and 0w are not legal. */
1016 static const char f32_1
[] =
1018 static const char f32_2
[] =
1019 {0x66,0x90}; /* xchg %ax,%ax */
1020 static const char f32_3
[] =
1021 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1022 static const char f32_4
[] =
1023 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1024 static const char f32_5
[] =
1026 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1027 static const char f32_6
[] =
1028 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1029 static const char f32_7
[] =
1030 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1031 static const char f32_8
[] =
1033 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1034 static const char f32_9
[] =
1035 {0x89,0xf6, /* movl %esi,%esi */
1036 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1037 static const char f32_10
[] =
1038 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1039 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1040 static const char f32_11
[] =
1041 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1042 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1043 static const char f32_12
[] =
1044 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1045 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1046 static const char f32_13
[] =
1047 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1048 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1049 static const char f32_14
[] =
1050 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1051 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1052 static const char f16_3
[] =
1053 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1054 static const char f16_4
[] =
1055 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1056 static const char f16_5
[] =
1058 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1059 static const char f16_6
[] =
1060 {0x89,0xf6, /* mov %si,%si */
1061 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1062 static const char f16_7
[] =
1063 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1064 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1065 static const char f16_8
[] =
1066 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1067 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1068 static const char jump_31
[] =
1069 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1070 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1071 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1072 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1073 static const char *const f32_patt
[] = {
1074 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1075 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1077 static const char *const f16_patt
[] = {
1078 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1080 /* nopl (%[re]ax) */
1081 static const char alt_3
[] =
1083 /* nopl 0(%[re]ax) */
1084 static const char alt_4
[] =
1085 {0x0f,0x1f,0x40,0x00};
1086 /* nopl 0(%[re]ax,%[re]ax,1) */
1087 static const char alt_5
[] =
1088 {0x0f,0x1f,0x44,0x00,0x00};
1089 /* nopw 0(%[re]ax,%[re]ax,1) */
1090 static const char alt_6
[] =
1091 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1092 /* nopl 0L(%[re]ax) */
1093 static const char alt_7
[] =
1094 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1095 /* nopl 0L(%[re]ax,%[re]ax,1) */
1096 static const char alt_8
[] =
1097 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1098 /* nopw 0L(%[re]ax,%[re]ax,1) */
1099 static const char alt_9
[] =
1100 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1101 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1102 static const char alt_10
[] =
1103 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1105 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1106 static const char alt_long_11
[] =
1108 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1111 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1112 static const char alt_long_12
[] =
1115 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1119 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1120 static const char alt_long_13
[] =
1124 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1129 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1130 static const char alt_long_14
[] =
1135 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1141 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1142 static const char alt_long_15
[] =
1148 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1149 /* nopl 0(%[re]ax,%[re]ax,1)
1150 nopw 0(%[re]ax,%[re]ax,1) */
1151 static const char alt_short_11
[] =
1152 {0x0f,0x1f,0x44,0x00,0x00,
1153 0x66,0x0f,0x1f,0x44,0x00,0x00};
1154 /* nopw 0(%[re]ax,%[re]ax,1)
1155 nopw 0(%[re]ax,%[re]ax,1) */
1156 static const char alt_short_12
[] =
1157 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1158 0x66,0x0f,0x1f,0x44,0x00,0x00};
1159 /* nopw 0(%[re]ax,%[re]ax,1)
1161 static const char alt_short_13
[] =
1162 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1163 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1166 static const char alt_short_14
[] =
1167 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1168 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1170 nopl 0L(%[re]ax,%[re]ax,1) */
1171 static const char alt_short_15
[] =
1172 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1173 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1174 static const char *const alt_short_patt
[] = {
1175 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1176 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1177 alt_short_14
, alt_short_15
1179 static const char *const alt_long_patt
[] = {
1180 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1181 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1182 alt_long_14
, alt_long_15
1185 /* Only align for at least a positive non-zero boundary. */
1186 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1189 /* We need to decide which NOP sequence to use for 32bit and
1190 64bit. When -mtune= is used:
1192 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1193 PROCESSOR_GENERIC32, f32_patt will be used.
1194 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1195 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1196 PROCESSOR_GENERIC64, alt_long_patt will be used.
1197 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1198 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1201 When -mtune= isn't used, alt_long_patt will be used if
1202 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1205 When -march= or .arch is used, we can't use anything beyond
1206 cpu_arch_isa_flags. */
1208 if (flag_code
== CODE_16BIT
)
1212 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1214 /* Adjust jump offset. */
1215 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1218 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1219 f16_patt
[count
- 1], count
);
1223 const char *const *patt
= NULL
;
1225 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1227 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1228 switch (cpu_arch_tune
)
1230 case PROCESSOR_UNKNOWN
:
1231 /* We use cpu_arch_isa_flags to check if we SHOULD
1232 optimize with nops. */
1233 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1234 patt
= alt_long_patt
;
1238 case PROCESSOR_PENTIUM4
:
1239 case PROCESSOR_NOCONA
:
1240 case PROCESSOR_CORE
:
1241 case PROCESSOR_CORE2
:
1242 case PROCESSOR_COREI7
:
1243 case PROCESSOR_L1OM
:
1244 case PROCESSOR_K1OM
:
1245 case PROCESSOR_GENERIC64
:
1246 patt
= alt_long_patt
;
1249 case PROCESSOR_ATHLON
:
1251 case PROCESSOR_AMDFAM10
:
1254 patt
= alt_short_patt
;
1256 case PROCESSOR_I386
:
1257 case PROCESSOR_I486
:
1258 case PROCESSOR_PENTIUM
:
1259 case PROCESSOR_PENTIUMPRO
:
1260 case PROCESSOR_GENERIC32
:
1267 switch (fragP
->tc_frag_data
.tune
)
1269 case PROCESSOR_UNKNOWN
:
1270 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1271 PROCESSOR_UNKNOWN. */
1275 case PROCESSOR_I386
:
1276 case PROCESSOR_I486
:
1277 case PROCESSOR_PENTIUM
:
1279 case PROCESSOR_ATHLON
:
1281 case PROCESSOR_AMDFAM10
:
1284 case PROCESSOR_GENERIC32
:
1285 /* We use cpu_arch_isa_flags to check if we CAN optimize
1287 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1288 patt
= alt_short_patt
;
1292 case PROCESSOR_PENTIUMPRO
:
1293 case PROCESSOR_PENTIUM4
:
1294 case PROCESSOR_NOCONA
:
1295 case PROCESSOR_CORE
:
1296 case PROCESSOR_CORE2
:
1297 case PROCESSOR_COREI7
:
1298 case PROCESSOR_L1OM
:
1299 case PROCESSOR_K1OM
:
1300 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1301 patt
= alt_long_patt
;
1305 case PROCESSOR_GENERIC64
:
1306 patt
= alt_long_patt
;
1311 if (patt
== f32_patt
)
1313 /* If the padding is less than 15 bytes, we use the normal
1314 ones. Otherwise, we use a jump instruction and adjust
1318 /* For 64bit, the limit is 3 bytes. */
1319 if (flag_code
== CODE_64BIT
1320 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1325 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1326 patt
[count
- 1], count
);
1329 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1331 /* Adjust jump offset. */
1332 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1337 /* Maximum length of an instruction is 15 byte. If the
1338 padding is greater than 15 bytes and we don't use jump,
1339 we have to break it into smaller pieces. */
1340 int padding
= count
;
1341 while (padding
> 15)
1344 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1349 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1350 patt
[padding
- 1], padding
);
1353 fragP
->fr_var
= count
;
1357 operand_type_all_zero (const union i386_operand_type
*x
)
1359 switch (ARRAY_SIZE(x
->array
))
1368 return !x
->array
[0];
1375 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1377 switch (ARRAY_SIZE(x
->array
))
1392 operand_type_equal (const union i386_operand_type
*x
,
1393 const union i386_operand_type
*y
)
1395 switch (ARRAY_SIZE(x
->array
))
1398 if (x
->array
[2] != y
->array
[2])
1401 if (x
->array
[1] != y
->array
[1])
1404 return x
->array
[0] == y
->array
[0];
1412 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1414 switch (ARRAY_SIZE(x
->array
))
1423 return !x
->array
[0];
1430 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1432 switch (ARRAY_SIZE(x
->array
))
1447 cpu_flags_equal (const union i386_cpu_flags
*x
,
1448 const union i386_cpu_flags
*y
)
1450 switch (ARRAY_SIZE(x
->array
))
1453 if (x
->array
[2] != y
->array
[2])
1456 if (x
->array
[1] != y
->array
[1])
1459 return x
->array
[0] == y
->array
[0];
1467 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1469 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1470 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1473 static INLINE i386_cpu_flags
1474 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1476 switch (ARRAY_SIZE (x
.array
))
1479 x
.array
[2] &= y
.array
[2];
1481 x
.array
[1] &= y
.array
[1];
1483 x
.array
[0] &= y
.array
[0];
1491 static INLINE i386_cpu_flags
1492 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1494 switch (ARRAY_SIZE (x
.array
))
1497 x
.array
[2] |= y
.array
[2];
1499 x
.array
[1] |= y
.array
[1];
1501 x
.array
[0] |= y
.array
[0];
1509 static INLINE i386_cpu_flags
1510 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1512 switch (ARRAY_SIZE (x
.array
))
1515 x
.array
[2] &= ~y
.array
[2];
1517 x
.array
[1] &= ~y
.array
[1];
1519 x
.array
[0] &= ~y
.array
[0];
1527 #define CPU_FLAGS_ARCH_MATCH 0x1
1528 #define CPU_FLAGS_64BIT_MATCH 0x2
1529 #define CPU_FLAGS_AES_MATCH 0x4
1530 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1531 #define CPU_FLAGS_AVX_MATCH 0x10
1533 #define CPU_FLAGS_32BIT_MATCH \
1534 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1535 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1536 #define CPU_FLAGS_PERFECT_MATCH \
1537 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1539 /* Return CPU flags match bits. */
1542 cpu_flags_match (const insn_template
*t
)
1544 i386_cpu_flags x
= t
->cpu_flags
;
1545 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1547 x
.bitfield
.cpu64
= 0;
1548 x
.bitfield
.cpuno64
= 0;
1550 if (cpu_flags_all_zero (&x
))
1552 /* This instruction is available on all archs. */
1553 match
|= CPU_FLAGS_32BIT_MATCH
;
1557 /* This instruction is available only on some archs. */
1558 i386_cpu_flags cpu
= cpu_arch_flags
;
1560 cpu
.bitfield
.cpu64
= 0;
1561 cpu
.bitfield
.cpuno64
= 0;
1562 cpu
= cpu_flags_and (x
, cpu
);
1563 if (!cpu_flags_all_zero (&cpu
))
1565 if (x
.bitfield
.cpuavx
)
1567 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1568 if (cpu
.bitfield
.cpuavx
)
1570 /* Check SSE2AVX. */
1571 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1573 match
|= (CPU_FLAGS_ARCH_MATCH
1574 | CPU_FLAGS_AVX_MATCH
);
1576 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1577 match
|= CPU_FLAGS_AES_MATCH
;
1579 if (!x
.bitfield
.cpupclmul
1580 || cpu
.bitfield
.cpupclmul
)
1581 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1585 match
|= CPU_FLAGS_ARCH_MATCH
;
1588 match
|= CPU_FLAGS_32BIT_MATCH
;
1594 static INLINE i386_operand_type
1595 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1597 switch (ARRAY_SIZE (x
.array
))
1600 x
.array
[2] &= y
.array
[2];
1602 x
.array
[1] &= y
.array
[1];
1604 x
.array
[0] &= y
.array
[0];
1612 static INLINE i386_operand_type
1613 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1615 switch (ARRAY_SIZE (x
.array
))
1618 x
.array
[2] |= y
.array
[2];
1620 x
.array
[1] |= y
.array
[1];
1622 x
.array
[0] |= y
.array
[0];
1630 static INLINE i386_operand_type
1631 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1633 switch (ARRAY_SIZE (x
.array
))
1636 x
.array
[2] ^= y
.array
[2];
1638 x
.array
[1] ^= y
.array
[1];
1640 x
.array
[0] ^= y
.array
[0];
1648 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1649 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1650 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1651 static const i386_operand_type inoutportreg
1652 = OPERAND_TYPE_INOUTPORTREG
;
1653 static const i386_operand_type reg16_inoutportreg
1654 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1655 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1656 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1657 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1658 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1659 static const i386_operand_type anydisp
1660 = OPERAND_TYPE_ANYDISP
;
1661 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1662 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1663 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1664 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1665 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1666 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1667 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1668 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1669 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1670 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1671 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1672 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1673 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1674 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1685 operand_type_check (i386_operand_type t
, enum operand_type c
)
1690 return (t
.bitfield
.reg8
1693 || t
.bitfield
.reg64
);
1696 return (t
.bitfield
.imm8
1700 || t
.bitfield
.imm32s
1701 || t
.bitfield
.imm64
);
1704 return (t
.bitfield
.disp8
1705 || t
.bitfield
.disp16
1706 || t
.bitfield
.disp32
1707 || t
.bitfield
.disp32s
1708 || t
.bitfield
.disp64
);
1711 return (t
.bitfield
.disp8
1712 || t
.bitfield
.disp16
1713 || t
.bitfield
.disp32
1714 || t
.bitfield
.disp32s
1715 || t
.bitfield
.disp64
1716 || t
.bitfield
.baseindex
);
1725 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1726 operand J for instruction template T. */
1729 match_reg_size (const insn_template
*t
, unsigned int j
)
1731 return !((i
.types
[j
].bitfield
.byte
1732 && !t
->operand_types
[j
].bitfield
.byte
)
1733 || (i
.types
[j
].bitfield
.word
1734 && !t
->operand_types
[j
].bitfield
.word
)
1735 || (i
.types
[j
].bitfield
.dword
1736 && !t
->operand_types
[j
].bitfield
.dword
)
1737 || (i
.types
[j
].bitfield
.qword
1738 && !t
->operand_types
[j
].bitfield
.qword
));
1741 /* Return 1 if there is no conflict in any size on operand J for
1742 instruction template T. */
1745 match_mem_size (const insn_template
*t
, unsigned int j
)
1747 return (match_reg_size (t
, j
)
1748 && !((i
.types
[j
].bitfield
.unspecified
1749 && !t
->operand_types
[j
].bitfield
.unspecified
)
1750 || (i
.types
[j
].bitfield
.fword
1751 && !t
->operand_types
[j
].bitfield
.fword
)
1752 || (i
.types
[j
].bitfield
.tbyte
1753 && !t
->operand_types
[j
].bitfield
.tbyte
)
1754 || (i
.types
[j
].bitfield
.xmmword
1755 && !t
->operand_types
[j
].bitfield
.xmmword
)
1756 || (i
.types
[j
].bitfield
.ymmword
1757 && !t
->operand_types
[j
].bitfield
.ymmword
)
1758 || (i
.types
[j
].bitfield
.zmmword
1759 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1762 /* Return 1 if there is no size conflict on any operands for
1763 instruction template T. */
1766 operand_size_match (const insn_template
*t
)
1771 /* Don't check jump instructions. */
1772 if (t
->opcode_modifier
.jump
1773 || t
->opcode_modifier
.jumpbyte
1774 || t
->opcode_modifier
.jumpdword
1775 || t
->opcode_modifier
.jumpintersegment
)
1778 /* Check memory and accumulator operand size. */
1779 for (j
= 0; j
< i
.operands
; j
++)
1781 if (t
->operand_types
[j
].bitfield
.anysize
)
1784 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1790 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1799 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1802 i
.error
= operand_size_mismatch
;
1806 /* Check reverse. */
1807 gas_assert (i
.operands
== 2);
1810 for (j
= 0; j
< 2; j
++)
1812 if (t
->operand_types
[j
].bitfield
.acc
1813 && !match_reg_size (t
, j
? 0 : 1))
1816 if (i
.types
[j
].bitfield
.mem
1817 && !match_mem_size (t
, j
? 0 : 1))
1825 operand_type_match (i386_operand_type overlap
,
1826 i386_operand_type given
)
1828 i386_operand_type temp
= overlap
;
1830 temp
.bitfield
.jumpabsolute
= 0;
1831 temp
.bitfield
.unspecified
= 0;
1832 temp
.bitfield
.byte
= 0;
1833 temp
.bitfield
.word
= 0;
1834 temp
.bitfield
.dword
= 0;
1835 temp
.bitfield
.fword
= 0;
1836 temp
.bitfield
.qword
= 0;
1837 temp
.bitfield
.tbyte
= 0;
1838 temp
.bitfield
.xmmword
= 0;
1839 temp
.bitfield
.ymmword
= 0;
1840 temp
.bitfield
.zmmword
= 0;
1841 if (operand_type_all_zero (&temp
))
1844 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1845 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1849 i
.error
= operand_type_mismatch
;
1853 /* If given types g0 and g1 are registers they must be of the same type
1854 unless the expected operand type register overlap is null.
1855 Note that Acc in a template matches every size of reg. */
1858 operand_type_register_match (i386_operand_type m0
,
1859 i386_operand_type g0
,
1860 i386_operand_type t0
,
1861 i386_operand_type m1
,
1862 i386_operand_type g1
,
1863 i386_operand_type t1
)
1865 if (!operand_type_check (g0
, reg
))
1868 if (!operand_type_check (g1
, reg
))
1871 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1872 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1873 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1874 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1877 if (m0
.bitfield
.acc
)
1879 t0
.bitfield
.reg8
= 1;
1880 t0
.bitfield
.reg16
= 1;
1881 t0
.bitfield
.reg32
= 1;
1882 t0
.bitfield
.reg64
= 1;
1885 if (m1
.bitfield
.acc
)
1887 t1
.bitfield
.reg8
= 1;
1888 t1
.bitfield
.reg16
= 1;
1889 t1
.bitfield
.reg32
= 1;
1890 t1
.bitfield
.reg64
= 1;
1893 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1894 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1895 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1896 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1899 i
.error
= register_type_mismatch
;
1904 static INLINE
unsigned int
1905 register_number (const reg_entry
*r
)
1907 unsigned int nr
= r
->reg_num
;
1909 if (r
->reg_flags
& RegRex
)
1915 static INLINE
unsigned int
1916 mode_from_disp_size (i386_operand_type t
)
1918 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1920 else if (t
.bitfield
.disp16
1921 || t
.bitfield
.disp32
1922 || t
.bitfield
.disp32s
)
1929 fits_in_signed_byte (offsetT num
)
1931 return (num
>= -128) && (num
<= 127);
1935 fits_in_unsigned_byte (offsetT num
)
1937 return (num
& 0xff) == num
;
1941 fits_in_unsigned_word (offsetT num
)
1943 return (num
& 0xffff) == num
;
1947 fits_in_signed_word (offsetT num
)
1949 return (-32768 <= num
) && (num
<= 32767);
1953 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1958 return (!(((offsetT
) -1 << 31) & num
)
1959 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1961 } /* fits_in_signed_long() */
1964 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1969 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1971 } /* fits_in_unsigned_long() */
1974 fits_in_vec_disp8 (offsetT num
)
1976 int shift
= i
.memshift
;
1982 mask
= (1 << shift
) - 1;
1984 /* Return 0 if NUM isn't properly aligned. */
1988 /* Check if NUM will fit in 8bit after shift. */
1989 return fits_in_signed_byte (num
>> shift
);
1993 fits_in_imm4 (offsetT num
)
1995 return (num
& 0xf) == num
;
1998 static i386_operand_type
1999 smallest_imm_type (offsetT num
)
2001 i386_operand_type t
;
2003 operand_type_set (&t
, 0);
2004 t
.bitfield
.imm64
= 1;
2006 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2008 /* This code is disabled on the 486 because all the Imm1 forms
2009 in the opcode table are slower on the i486. They're the
2010 versions with the implicitly specified single-position
2011 displacement, which has another syntax if you really want to
2013 t
.bitfield
.imm1
= 1;
2014 t
.bitfield
.imm8
= 1;
2015 t
.bitfield
.imm8s
= 1;
2016 t
.bitfield
.imm16
= 1;
2017 t
.bitfield
.imm32
= 1;
2018 t
.bitfield
.imm32s
= 1;
2020 else if (fits_in_signed_byte (num
))
2022 t
.bitfield
.imm8
= 1;
2023 t
.bitfield
.imm8s
= 1;
2024 t
.bitfield
.imm16
= 1;
2025 t
.bitfield
.imm32
= 1;
2026 t
.bitfield
.imm32s
= 1;
2028 else if (fits_in_unsigned_byte (num
))
2030 t
.bitfield
.imm8
= 1;
2031 t
.bitfield
.imm16
= 1;
2032 t
.bitfield
.imm32
= 1;
2033 t
.bitfield
.imm32s
= 1;
2035 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2037 t
.bitfield
.imm16
= 1;
2038 t
.bitfield
.imm32
= 1;
2039 t
.bitfield
.imm32s
= 1;
2041 else if (fits_in_signed_long (num
))
2043 t
.bitfield
.imm32
= 1;
2044 t
.bitfield
.imm32s
= 1;
2046 else if (fits_in_unsigned_long (num
))
2047 t
.bitfield
.imm32
= 1;
2053 offset_in_range (offsetT val
, int size
)
2059 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2060 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2061 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2063 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2069 /* If BFD64, sign extend val for 32bit address mode. */
2070 if (flag_code
!= CODE_64BIT
2071 || i
.prefix
[ADDR_PREFIX
])
2072 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2073 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2076 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2078 char buf1
[40], buf2
[40];
2080 sprint_value (buf1
, val
);
2081 sprint_value (buf2
, val
& mask
);
2082 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2096 a. PREFIX_EXIST if attempting to add a prefix where one from the
2097 same class already exists.
2098 b. PREFIX_LOCK if lock prefix is added.
2099 c. PREFIX_REP if rep/repne prefix is added.
2100 d. PREFIX_OTHER if other prefix is added.
2103 static enum PREFIX_GROUP
2104 add_prefix (unsigned int prefix
)
2106 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2109 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2110 && flag_code
== CODE_64BIT
)
2112 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2113 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2114 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2125 case CS_PREFIX_OPCODE
:
2126 case DS_PREFIX_OPCODE
:
2127 case ES_PREFIX_OPCODE
:
2128 case FS_PREFIX_OPCODE
:
2129 case GS_PREFIX_OPCODE
:
2130 case SS_PREFIX_OPCODE
:
2134 case REPNE_PREFIX_OPCODE
:
2135 case REPE_PREFIX_OPCODE
:
2140 case LOCK_PREFIX_OPCODE
:
2149 case ADDR_PREFIX_OPCODE
:
2153 case DATA_PREFIX_OPCODE
:
2157 if (i
.prefix
[q
] != 0)
2165 i
.prefix
[q
] |= prefix
;
2168 as_bad (_("same type of prefix used twice"));
2174 update_code_flag (int value
, int check
)
2176 PRINTF_LIKE ((*as_error
));
2178 flag_code
= (enum flag_code
) value
;
2179 if (flag_code
== CODE_64BIT
)
2181 cpu_arch_flags
.bitfield
.cpu64
= 1;
2182 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2186 cpu_arch_flags
.bitfield
.cpu64
= 0;
2187 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2189 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2192 as_error
= as_fatal
;
2195 (*as_error
) (_("64bit mode not supported on `%s'."),
2196 cpu_arch_name
? cpu_arch_name
: default_arch
);
2198 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2201 as_error
= as_fatal
;
2204 (*as_error
) (_("32bit mode not supported on `%s'."),
2205 cpu_arch_name
? cpu_arch_name
: default_arch
);
2207 stackop_size
= '\0';
2211 set_code_flag (int value
)
2213 update_code_flag (value
, 0);
2217 set_16bit_gcc_code_flag (int new_code_flag
)
2219 flag_code
= (enum flag_code
) new_code_flag
;
2220 if (flag_code
!= CODE_16BIT
)
2222 cpu_arch_flags
.bitfield
.cpu64
= 0;
2223 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2224 stackop_size
= LONG_MNEM_SUFFIX
;
2228 set_intel_syntax (int syntax_flag
)
2230 /* Find out if register prefixing is specified. */
2231 int ask_naked_reg
= 0;
2234 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2236 char *string
= input_line_pointer
;
2237 int e
= get_symbol_end ();
2239 if (strcmp (string
, "prefix") == 0)
2241 else if (strcmp (string
, "noprefix") == 0)
2244 as_bad (_("bad argument to syntax directive."));
2245 *input_line_pointer
= e
;
2247 demand_empty_rest_of_line ();
2249 intel_syntax
= syntax_flag
;
2251 if (ask_naked_reg
== 0)
2252 allow_naked_reg
= (intel_syntax
2253 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2255 allow_naked_reg
= (ask_naked_reg
< 0);
2257 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2259 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2260 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2261 register_prefix
= allow_naked_reg
? "" : "%";
2265 set_intel_mnemonic (int mnemonic_flag
)
2267 intel_mnemonic
= mnemonic_flag
;
2271 set_allow_index_reg (int flag
)
2273 allow_index_reg
= flag
;
2277 set_check (int what
)
2279 enum check_kind
*kind
;
2284 kind
= &operand_check
;
2295 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2297 char *string
= input_line_pointer
;
2298 int e
= get_symbol_end ();
2300 if (strcmp (string
, "none") == 0)
2302 else if (strcmp (string
, "warning") == 0)
2303 *kind
= check_warning
;
2304 else if (strcmp (string
, "error") == 0)
2305 *kind
= check_error
;
2307 as_bad (_("bad argument to %s_check directive."), str
);
2308 *input_line_pointer
= e
;
2311 as_bad (_("missing argument for %s_check directive"), str
);
2313 demand_empty_rest_of_line ();
2317 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2318 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2320 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2321 static const char *arch
;
2323 /* Intel LIOM is only supported on ELF. */
2329 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2330 use default_arch. */
2331 arch
= cpu_arch_name
;
2333 arch
= default_arch
;
2336 /* If we are targeting Intel L1OM, we must enable it. */
2337 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2338 || new_flag
.bitfield
.cpul1om
)
2341 /* If we are targeting Intel K1OM, we must enable it. */
2342 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2343 || new_flag
.bitfield
.cpuk1om
)
2346 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2351 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2355 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2357 char *string
= input_line_pointer
;
2358 int e
= get_symbol_end ();
2360 i386_cpu_flags flags
;
2362 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2364 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2366 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2370 cpu_arch_name
= cpu_arch
[j
].name
;
2371 cpu_sub_arch_name
= NULL
;
2372 cpu_arch_flags
= cpu_arch
[j
].flags
;
2373 if (flag_code
== CODE_64BIT
)
2375 cpu_arch_flags
.bitfield
.cpu64
= 1;
2376 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2380 cpu_arch_flags
.bitfield
.cpu64
= 0;
2381 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2383 cpu_arch_isa
= cpu_arch
[j
].type
;
2384 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2385 if (!cpu_arch_tune_set
)
2387 cpu_arch_tune
= cpu_arch_isa
;
2388 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2393 if (!cpu_arch
[j
].negated
)
2394 flags
= cpu_flags_or (cpu_arch_flags
,
2397 flags
= cpu_flags_and_not (cpu_arch_flags
,
2399 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2401 if (cpu_sub_arch_name
)
2403 char *name
= cpu_sub_arch_name
;
2404 cpu_sub_arch_name
= concat (name
,
2406 (const char *) NULL
);
2410 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2411 cpu_arch_flags
= flags
;
2412 cpu_arch_isa_flags
= flags
;
2414 *input_line_pointer
= e
;
2415 demand_empty_rest_of_line ();
2419 if (j
>= ARRAY_SIZE (cpu_arch
))
2420 as_bad (_("no such architecture: `%s'"), string
);
2422 *input_line_pointer
= e
;
2425 as_bad (_("missing cpu architecture"));
2427 no_cond_jump_promotion
= 0;
2428 if (*input_line_pointer
== ','
2429 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2431 char *string
= ++input_line_pointer
;
2432 int e
= get_symbol_end ();
2434 if (strcmp (string
, "nojumps") == 0)
2435 no_cond_jump_promotion
= 1;
2436 else if (strcmp (string
, "jumps") == 0)
2439 as_bad (_("no such architecture modifier: `%s'"), string
);
2441 *input_line_pointer
= e
;
2444 demand_empty_rest_of_line ();
2447 enum bfd_architecture
2450 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2452 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2453 || flag_code
!= CODE_64BIT
)
2454 as_fatal (_("Intel L1OM is 64bit ELF only"));
2455 return bfd_arch_l1om
;
2457 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2459 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2460 || flag_code
!= CODE_64BIT
)
2461 as_fatal (_("Intel K1OM is 64bit ELF only"));
2462 return bfd_arch_k1om
;
2465 return bfd_arch_i386
;
2471 if (!strncmp (default_arch
, "x86_64", 6))
2473 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2475 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2476 || default_arch
[6] != '\0')
2477 as_fatal (_("Intel L1OM is 64bit ELF only"));
2478 return bfd_mach_l1om
;
2480 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2482 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2483 || default_arch
[6] != '\0')
2484 as_fatal (_("Intel K1OM is 64bit ELF only"));
2485 return bfd_mach_k1om
;
2487 else if (default_arch
[6] == '\0')
2488 return bfd_mach_x86_64
;
2490 return bfd_mach_x64_32
;
2492 else if (!strcmp (default_arch
, "i386"))
2493 return bfd_mach_i386_i386
;
2495 as_fatal (_("unknown architecture"));
2501 const char *hash_err
;
2503 /* Initialize op_hash hash table. */
2504 op_hash
= hash_new ();
2507 const insn_template
*optab
;
2508 templates
*core_optab
;
2510 /* Setup for loop. */
2512 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2513 core_optab
->start
= optab
;
2518 if (optab
->name
== NULL
2519 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2521 /* different name --> ship out current template list;
2522 add to hash table; & begin anew. */
2523 core_optab
->end
= optab
;
2524 hash_err
= hash_insert (op_hash
,
2526 (void *) core_optab
);
2529 as_fatal (_("can't hash %s: %s"),
2533 if (optab
->name
== NULL
)
2535 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2536 core_optab
->start
= optab
;
2541 /* Initialize reg_hash hash table. */
2542 reg_hash
= hash_new ();
2544 const reg_entry
*regtab
;
2545 unsigned int regtab_size
= i386_regtab_size
;
2547 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2549 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2551 as_fatal (_("can't hash %s: %s"),
2557 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2562 for (c
= 0; c
< 256; c
++)
2567 mnemonic_chars
[c
] = c
;
2568 register_chars
[c
] = c
;
2569 operand_chars
[c
] = c
;
2571 else if (ISLOWER (c
))
2573 mnemonic_chars
[c
] = c
;
2574 register_chars
[c
] = c
;
2575 operand_chars
[c
] = c
;
2577 else if (ISUPPER (c
))
2579 mnemonic_chars
[c
] = TOLOWER (c
);
2580 register_chars
[c
] = mnemonic_chars
[c
];
2581 operand_chars
[c
] = c
;
2583 else if (c
== '{' || c
== '}')
2584 operand_chars
[c
] = c
;
2586 if (ISALPHA (c
) || ISDIGIT (c
))
2587 identifier_chars
[c
] = c
;
2590 identifier_chars
[c
] = c
;
2591 operand_chars
[c
] = c
;
2596 identifier_chars
['@'] = '@';
2599 identifier_chars
['?'] = '?';
2600 operand_chars
['?'] = '?';
2602 digit_chars
['-'] = '-';
2603 mnemonic_chars
['_'] = '_';
2604 mnemonic_chars
['-'] = '-';
2605 mnemonic_chars
['.'] = '.';
2606 identifier_chars
['_'] = '_';
2607 identifier_chars
['.'] = '.';
2609 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2610 operand_chars
[(unsigned char) *p
] = *p
;
2613 if (flag_code
== CODE_64BIT
)
2615 #if defined (OBJ_COFF) && defined (TE_PE)
2616 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2619 x86_dwarf2_return_column
= 16;
2621 x86_cie_data_alignment
= -8;
2625 x86_dwarf2_return_column
= 8;
2626 x86_cie_data_alignment
= -4;
2631 i386_print_statistics (FILE *file
)
2633 hash_print_statistics (file
, "i386 opcode", op_hash
);
2634 hash_print_statistics (file
, "i386 register", reg_hash
);
2639 /* Debugging routines for md_assemble. */
2640 static void pte (insn_template
*);
2641 static void pt (i386_operand_type
);
2642 static void pe (expressionS
*);
2643 static void ps (symbolS
*);
2646 pi (char *line
, i386_insn
*x
)
2650 fprintf (stdout
, "%s: template ", line
);
2652 fprintf (stdout
, " address: base %s index %s scale %x\n",
2653 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2654 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2655 x
->log2_scale_factor
);
2656 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2657 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2658 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2659 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2660 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2661 (x
->rex
& REX_W
) != 0,
2662 (x
->rex
& REX_R
) != 0,
2663 (x
->rex
& REX_X
) != 0,
2664 (x
->rex
& REX_B
) != 0);
2665 for (j
= 0; j
< x
->operands
; j
++)
2667 fprintf (stdout
, " #%d: ", j
+ 1);
2669 fprintf (stdout
, "\n");
2670 if (x
->types
[j
].bitfield
.reg8
2671 || x
->types
[j
].bitfield
.reg16
2672 || x
->types
[j
].bitfield
.reg32
2673 || x
->types
[j
].bitfield
.reg64
2674 || x
->types
[j
].bitfield
.regmmx
2675 || x
->types
[j
].bitfield
.regxmm
2676 || x
->types
[j
].bitfield
.regymm
2677 || x
->types
[j
].bitfield
.regzmm
2678 || x
->types
[j
].bitfield
.sreg2
2679 || x
->types
[j
].bitfield
.sreg3
2680 || x
->types
[j
].bitfield
.control
2681 || x
->types
[j
].bitfield
.debug
2682 || x
->types
[j
].bitfield
.test
)
2683 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2684 if (operand_type_check (x
->types
[j
], imm
))
2686 if (operand_type_check (x
->types
[j
], disp
))
2687 pe (x
->op
[j
].disps
);
2692 pte (insn_template
*t
)
2695 fprintf (stdout
, " %d operands ", t
->operands
);
2696 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2697 if (t
->extension_opcode
!= None
)
2698 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2699 if (t
->opcode_modifier
.d
)
2700 fprintf (stdout
, "D");
2701 if (t
->opcode_modifier
.w
)
2702 fprintf (stdout
, "W");
2703 fprintf (stdout
, "\n");
2704 for (j
= 0; j
< t
->operands
; j
++)
2706 fprintf (stdout
, " #%d type ", j
+ 1);
2707 pt (t
->operand_types
[j
]);
2708 fprintf (stdout
, "\n");
2715 fprintf (stdout
, " operation %d\n", e
->X_op
);
2716 fprintf (stdout
, " add_number %ld (%lx)\n",
2717 (long) e
->X_add_number
, (long) e
->X_add_number
);
2718 if (e
->X_add_symbol
)
2720 fprintf (stdout
, " add_symbol ");
2721 ps (e
->X_add_symbol
);
2722 fprintf (stdout
, "\n");
2726 fprintf (stdout
, " op_symbol ");
2727 ps (e
->X_op_symbol
);
2728 fprintf (stdout
, "\n");
2735 fprintf (stdout
, "%s type %s%s",
2737 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2738 segment_name (S_GET_SEGMENT (s
)));
2741 static struct type_name
2743 i386_operand_type mask
;
2746 const type_names
[] =
2748 { OPERAND_TYPE_REG8
, "r8" },
2749 { OPERAND_TYPE_REG16
, "r16" },
2750 { OPERAND_TYPE_REG32
, "r32" },
2751 { OPERAND_TYPE_REG64
, "r64" },
2752 { OPERAND_TYPE_IMM8
, "i8" },
2753 { OPERAND_TYPE_IMM8
, "i8s" },
2754 { OPERAND_TYPE_IMM16
, "i16" },
2755 { OPERAND_TYPE_IMM32
, "i32" },
2756 { OPERAND_TYPE_IMM32S
, "i32s" },
2757 { OPERAND_TYPE_IMM64
, "i64" },
2758 { OPERAND_TYPE_IMM1
, "i1" },
2759 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2760 { OPERAND_TYPE_DISP8
, "d8" },
2761 { OPERAND_TYPE_DISP16
, "d16" },
2762 { OPERAND_TYPE_DISP32
, "d32" },
2763 { OPERAND_TYPE_DISP32S
, "d32s" },
2764 { OPERAND_TYPE_DISP64
, "d64" },
2765 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2766 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2767 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2768 { OPERAND_TYPE_CONTROL
, "control reg" },
2769 { OPERAND_TYPE_TEST
, "test reg" },
2770 { OPERAND_TYPE_DEBUG
, "debug reg" },
2771 { OPERAND_TYPE_FLOATREG
, "FReg" },
2772 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2773 { OPERAND_TYPE_SREG2
, "SReg2" },
2774 { OPERAND_TYPE_SREG3
, "SReg3" },
2775 { OPERAND_TYPE_ACC
, "Acc" },
2776 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2777 { OPERAND_TYPE_REGMMX
, "rMMX" },
2778 { OPERAND_TYPE_REGXMM
, "rXMM" },
2779 { OPERAND_TYPE_REGYMM
, "rYMM" },
2780 { OPERAND_TYPE_REGZMM
, "rZMM" },
2781 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2782 { OPERAND_TYPE_ESSEG
, "es" },
2786 pt (i386_operand_type t
)
2789 i386_operand_type a
;
2791 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2793 a
= operand_type_and (t
, type_names
[j
].mask
);
2794 if (!operand_type_all_zero (&a
))
2795 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2800 #endif /* DEBUG386 */
2802 static bfd_reloc_code_real_type
2803 reloc (unsigned int size
,
2807 bfd_reloc_code_real_type other
)
2809 if (other
!= NO_RELOC
)
2811 reloc_howto_type
*rel
;
2816 case BFD_RELOC_X86_64_GOT32
:
2817 return BFD_RELOC_X86_64_GOT64
;
2819 case BFD_RELOC_X86_64_PLTOFF64
:
2820 return BFD_RELOC_X86_64_PLTOFF64
;
2822 case BFD_RELOC_X86_64_GOTPC32
:
2823 other
= BFD_RELOC_X86_64_GOTPC64
;
2825 case BFD_RELOC_X86_64_GOTPCREL
:
2826 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2828 case BFD_RELOC_X86_64_TPOFF32
:
2829 other
= BFD_RELOC_X86_64_TPOFF64
;
2831 case BFD_RELOC_X86_64_DTPOFF32
:
2832 other
= BFD_RELOC_X86_64_DTPOFF64
;
2838 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2839 if (other
== BFD_RELOC_SIZE32
)
2842 return BFD_RELOC_SIZE64
;
2844 as_bad (_("there are no pc-relative size relocations"));
2848 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2849 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2852 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2854 as_bad (_("unknown relocation (%u)"), other
);
2855 else if (size
!= bfd_get_reloc_size (rel
))
2856 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2857 bfd_get_reloc_size (rel
),
2859 else if (pcrel
&& !rel
->pc_relative
)
2860 as_bad (_("non-pc-relative relocation for pc-relative field"));
2861 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2863 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2865 as_bad (_("relocated field and relocation type differ in signedness"));
2874 as_bad (_("there are no unsigned pc-relative relocations"));
2877 case 1: return BFD_RELOC_8_PCREL
;
2878 case 2: return BFD_RELOC_16_PCREL
;
2879 case 4: return (bnd_prefix
&& object_64bit
2880 ? BFD_RELOC_X86_64_PC32_BND
2881 : BFD_RELOC_32_PCREL
);
2882 case 8: return BFD_RELOC_64_PCREL
;
2884 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2891 case 4: return BFD_RELOC_X86_64_32S
;
2896 case 1: return BFD_RELOC_8
;
2897 case 2: return BFD_RELOC_16
;
2898 case 4: return BFD_RELOC_32
;
2899 case 8: return BFD_RELOC_64
;
2901 as_bad (_("cannot do %s %u byte relocation"),
2902 sign
> 0 ? "signed" : "unsigned", size
);
2908 /* Here we decide which fixups can be adjusted to make them relative to
2909 the beginning of the section instead of the symbol. Basically we need
2910 to make sure that the dynamic relocations are done correctly, so in
2911 some cases we force the original symbol to be used. */
2914 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2916 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2920 /* Don't adjust pc-relative references to merge sections in 64-bit
2922 if (use_rela_relocations
2923 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2927 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2928 and changed later by validate_fix. */
2929 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2930 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2933 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2934 for size relocations. */
2935 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2936 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2937 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2938 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2939 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2940 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2941 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2942 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2943 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2944 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2945 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2946 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2947 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2948 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2949 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2950 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2951 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2952 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2953 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2954 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2955 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2956 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2957 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2958 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2959 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2960 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2961 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2962 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2963 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2964 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2971 intel_float_operand (const char *mnemonic
)
2973 /* Note that the value returned is meaningful only for opcodes with (memory)
2974 operands, hence the code here is free to improperly handle opcodes that
2975 have no operands (for better performance and smaller code). */
2977 if (mnemonic
[0] != 'f')
2978 return 0; /* non-math */
2980 switch (mnemonic
[1])
2982 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2983 the fs segment override prefix not currently handled because no
2984 call path can make opcodes without operands get here */
2986 return 2 /* integer op */;
2988 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2989 return 3; /* fldcw/fldenv */
2992 if (mnemonic
[2] != 'o' /* fnop */)
2993 return 3; /* non-waiting control op */
2996 if (mnemonic
[2] == 's')
2997 return 3; /* frstor/frstpm */
3000 if (mnemonic
[2] == 'a')
3001 return 3; /* fsave */
3002 if (mnemonic
[2] == 't')
3004 switch (mnemonic
[3])
3006 case 'c': /* fstcw */
3007 case 'd': /* fstdw */
3008 case 'e': /* fstenv */
3009 case 's': /* fsts[gw] */
3015 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3016 return 0; /* fxsave/fxrstor are not really math ops */
3023 /* Build the VEX prefix. */
3026 build_vex_prefix (const insn_template
*t
)
3028 unsigned int register_specifier
;
3029 unsigned int implied_prefix
;
3030 unsigned int vector_length
;
3032 /* Check register specifier. */
3033 if (i
.vex
.register_specifier
)
3035 register_specifier
=
3036 ~register_number (i
.vex
.register_specifier
) & 0xf;
3037 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3040 register_specifier
= 0xf;
3042 /* Use 2-byte VEX prefix by swappping destination and source
3045 && i
.operands
== i
.reg_operands
3046 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3047 && i
.tm
.opcode_modifier
.s
3050 unsigned int xchg
= i
.operands
- 1;
3051 union i386_op temp_op
;
3052 i386_operand_type temp_type
;
3054 temp_type
= i
.types
[xchg
];
3055 i
.types
[xchg
] = i
.types
[0];
3056 i
.types
[0] = temp_type
;
3057 temp_op
= i
.op
[xchg
];
3058 i
.op
[xchg
] = i
.op
[0];
3061 gas_assert (i
.rm
.mode
== 3);
3065 i
.rm
.regmem
= i
.rm
.reg
;
3068 /* Use the next insn. */
3072 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3073 vector_length
= avxscalar
;
3075 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3077 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3082 case DATA_PREFIX_OPCODE
:
3085 case REPE_PREFIX_OPCODE
:
3088 case REPNE_PREFIX_OPCODE
:
3095 /* Use 2-byte VEX prefix if possible. */
3096 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3097 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3098 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3100 /* 2-byte VEX prefix. */
3104 i
.vex
.bytes
[0] = 0xc5;
3106 /* Check the REX.R bit. */
3107 r
= (i
.rex
& REX_R
) ? 0 : 1;
3108 i
.vex
.bytes
[1] = (r
<< 7
3109 | register_specifier
<< 3
3110 | vector_length
<< 2
3115 /* 3-byte VEX prefix. */
3120 switch (i
.tm
.opcode_modifier
.vexopcode
)
3124 i
.vex
.bytes
[0] = 0xc4;
3128 i
.vex
.bytes
[0] = 0xc4;
3132 i
.vex
.bytes
[0] = 0xc4;
3136 i
.vex
.bytes
[0] = 0x8f;
3140 i
.vex
.bytes
[0] = 0x8f;
3144 i
.vex
.bytes
[0] = 0x8f;
3150 /* The high 3 bits of the second VEX byte are 1's compliment
3151 of RXB bits from REX. */
3152 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3154 /* Check the REX.W bit. */
3155 w
= (i
.rex
& REX_W
) ? 1 : 0;
3156 if (i
.tm
.opcode_modifier
.vexw
)
3161 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3165 i
.vex
.bytes
[2] = (w
<< 7
3166 | register_specifier
<< 3
3167 | vector_length
<< 2
3172 /* Build the EVEX prefix. */
3175 build_evex_prefix (void)
3177 unsigned int register_specifier
;
3178 unsigned int implied_prefix
;
3180 rex_byte vrex_used
= 0;
3182 /* Check register specifier. */
3183 if (i
.vex
.register_specifier
)
3185 gas_assert ((i
.vrex
& REX_X
) == 0);
3187 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3188 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3189 register_specifier
+= 8;
3190 /* The upper 16 registers are encoded in the fourth byte of the
3192 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3193 i
.vex
.bytes
[3] = 0x8;
3194 register_specifier
= ~register_specifier
& 0xf;
3198 register_specifier
= 0xf;
3200 /* Encode upper 16 vector index register in the fourth byte of
3202 if (!(i
.vrex
& REX_X
))
3203 i
.vex
.bytes
[3] = 0x8;
3208 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3213 case DATA_PREFIX_OPCODE
:
3216 case REPE_PREFIX_OPCODE
:
3219 case REPNE_PREFIX_OPCODE
:
3226 /* 4 byte EVEX prefix. */
3228 i
.vex
.bytes
[0] = 0x62;
3231 switch (i
.tm
.opcode_modifier
.vexopcode
)
3247 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3249 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3251 /* The fifth bit of the second EVEX byte is 1's compliment of the
3252 REX_R bit in VREX. */
3253 if (!(i
.vrex
& REX_R
))
3254 i
.vex
.bytes
[1] |= 0x10;
3258 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3260 /* When all operands are registers, the REX_X bit in REX is not
3261 used. We reuse it to encode the upper 16 registers, which is
3262 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3263 as 1's compliment. */
3264 if ((i
.vrex
& REX_B
))
3267 i
.vex
.bytes
[1] &= ~0x40;
3271 /* EVEX instructions shouldn't need the REX prefix. */
3272 i
.vrex
&= ~vrex_used
;
3273 gas_assert (i
.vrex
== 0);
3275 /* Check the REX.W bit. */
3276 w
= (i
.rex
& REX_W
) ? 1 : 0;
3277 if (i
.tm
.opcode_modifier
.vexw
)
3279 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3282 /* If w is not set it means we are dealing with WIG instruction. */
3285 if (evexwig
== evexw1
)
3289 /* Encode the U bit. */
3290 implied_prefix
|= 0x4;
3292 /* The third byte of the EVEX prefix. */
3293 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3295 /* The fourth byte of the EVEX prefix. */
3296 /* The zeroing-masking bit. */
3297 if (i
.mask
&& i
.mask
->zeroing
)
3298 i
.vex
.bytes
[3] |= 0x80;
3300 /* Don't always set the broadcast bit if there is no RC. */
3303 /* Encode the vector length. */
3304 unsigned int vec_length
;
3306 switch (i
.tm
.opcode_modifier
.evex
)
3308 case EVEXLIG
: /* LL' is ignored */
3309 vec_length
= evexlig
<< 5;
3312 vec_length
= 0 << 5;
3315 vec_length
= 1 << 5;
3318 vec_length
= 2 << 5;
3324 i
.vex
.bytes
[3] |= vec_length
;
3325 /* Encode the broadcast bit. */
3327 i
.vex
.bytes
[3] |= 0x10;
3331 if (i
.rounding
->type
!= saeonly
)
3332 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3334 i
.vex
.bytes
[3] |= 0x10;
3337 if (i
.mask
&& i
.mask
->mask
)
3338 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3342 process_immext (void)
3346 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3349 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3350 with an opcode suffix which is coded in the same place as an
3351 8-bit immediate field would be.
3352 Here we check those operands and remove them afterwards. */
3355 for (x
= 0; x
< i
.operands
; x
++)
3356 if (register_number (i
.op
[x
].regs
) != x
)
3357 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3358 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3364 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3365 which is coded in the same place as an 8-bit immediate field
3366 would be. Here we fake an 8-bit immediate operand from the
3367 opcode suffix stored in tm.extension_opcode.
3369 AVX instructions also use this encoding, for some of
3370 3 argument instructions. */
3372 gas_assert (i
.imm_operands
<= 1
3374 || ((i
.tm
.opcode_modifier
.vex
3375 || i
.tm
.opcode_modifier
.evex
)
3376 && i
.operands
<= 4)));
3378 exp
= &im_expressions
[i
.imm_operands
++];
3379 i
.op
[i
.operands
].imms
= exp
;
3380 i
.types
[i
.operands
] = imm8
;
3382 exp
->X_op
= O_constant
;
3383 exp
->X_add_number
= i
.tm
.extension_opcode
;
3384 i
.tm
.extension_opcode
= None
;
3391 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3396 as_bad (_("invalid instruction `%s' after `%s'"),
3397 i
.tm
.name
, i
.hle_prefix
);
3400 if (i
.prefix
[LOCK_PREFIX
])
3402 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3406 case HLEPrefixRelease
:
3407 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3409 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3413 if (i
.mem_operands
== 0
3414 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3416 as_bad (_("memory destination needed for instruction `%s'"
3417 " after `xrelease'"), i
.tm
.name
);
3424 /* This is the guts of the machine-dependent assembler. LINE points to a
3425 machine dependent instruction. This function is supposed to emit
3426 the frags/bytes it assembles to. */
3429 md_assemble (char *line
)
3432 char mnemonic
[MAX_MNEM_SIZE
];
3433 const insn_template
*t
;
3435 /* Initialize globals. */
3436 memset (&i
, '\0', sizeof (i
));
3437 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3438 i
.reloc
[j
] = NO_RELOC
;
3439 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3440 memset (im_expressions
, '\0', sizeof (im_expressions
));
3441 save_stack_p
= save_stack
;
3443 /* First parse an instruction mnemonic & call i386_operand for the operands.
3444 We assume that the scrubber has arranged it so that line[0] is the valid
3445 start of a (possibly prefixed) mnemonic. */
3447 line
= parse_insn (line
, mnemonic
);
3451 line
= parse_operands (line
, mnemonic
);
3456 /* Now we've parsed the mnemonic into a set of templates, and have the
3457 operands at hand. */
3459 /* All intel opcodes have reversed operands except for "bound" and
3460 "enter". We also don't reverse intersegment "jmp" and "call"
3461 instructions with 2 immediate operands so that the immediate segment
3462 precedes the offset, as it does when in AT&T mode. */
3465 && (strcmp (mnemonic
, "bound") != 0)
3466 && (strcmp (mnemonic
, "invlpga") != 0)
3467 && !(operand_type_check (i
.types
[0], imm
)
3468 && operand_type_check (i
.types
[1], imm
)))
3471 /* The order of the immediates should be reversed
3472 for 2 immediates extrq and insertq instructions */
3473 if (i
.imm_operands
== 2
3474 && (strcmp (mnemonic
, "extrq") == 0
3475 || strcmp (mnemonic
, "insertq") == 0))
3476 swap_2_operands (0, 1);
3481 /* Don't optimize displacement for movabs since it only takes 64bit
3484 && i
.disp_encoding
!= disp_encoding_32bit
3485 && (flag_code
!= CODE_64BIT
3486 || strcmp (mnemonic
, "movabs") != 0))
3489 /* Next, we find a template that matches the given insn,
3490 making sure the overlap of the given operands types is consistent
3491 with the template operand types. */
3493 if (!(t
= match_template ()))
3496 if (sse_check
!= check_none
3497 && !i
.tm
.opcode_modifier
.noavx
3498 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3499 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3500 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3501 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3502 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3503 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3505 (sse_check
== check_warning
3507 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3510 /* Zap movzx and movsx suffix. The suffix has been set from
3511 "word ptr" or "byte ptr" on the source operand in Intel syntax
3512 or extracted from mnemonic in AT&T syntax. But we'll use
3513 the destination register to choose the suffix for encoding. */
3514 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3516 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3517 there is no suffix, the default will be byte extension. */
3518 if (i
.reg_operands
!= 2
3521 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3526 if (i
.tm
.opcode_modifier
.fwait
)
3527 if (!add_prefix (FWAIT_OPCODE
))
3530 /* Check if REP prefix is OK. */
3531 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3533 as_bad (_("invalid instruction `%s' after `%s'"),
3534 i
.tm
.name
, i
.rep_prefix
);
3538 /* Check for lock without a lockable instruction. Destination operand
3539 must be memory unless it is xchg (0x86). */
3540 if (i
.prefix
[LOCK_PREFIX
]
3541 && (!i
.tm
.opcode_modifier
.islockable
3542 || i
.mem_operands
== 0
3543 || (i
.tm
.base_opcode
!= 0x86
3544 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3546 as_bad (_("expecting lockable instruction after `lock'"));
3550 /* Check if HLE prefix is OK. */
3551 if (i
.hle_prefix
&& !check_hle ())
3554 /* Check BND prefix. */
3555 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3556 as_bad (_("expecting valid branch instruction after `bnd'"));
3558 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3559 && flag_code
== CODE_64BIT
3560 && i
.prefix
[ADDR_PREFIX
])
3561 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3563 /* Insert BND prefix. */
3565 && i
.tm
.opcode_modifier
.bndprefixok
3566 && !i
.prefix
[BND_PREFIX
])
3567 add_prefix (BND_PREFIX_OPCODE
);
3569 /* Check string instruction segment overrides. */
3570 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3572 if (!check_string ())
3574 i
.disp_operands
= 0;
3577 if (!process_suffix ())
3580 /* Update operand types. */
3581 for (j
= 0; j
< i
.operands
; j
++)
3582 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3584 /* Make still unresolved immediate matches conform to size of immediate
3585 given in i.suffix. */
3586 if (!finalize_imm ())
3589 if (i
.types
[0].bitfield
.imm1
)
3590 i
.imm_operands
= 0; /* kludge for shift insns. */
3592 /* We only need to check those implicit registers for instructions
3593 with 3 operands or less. */
3594 if (i
.operands
<= 3)
3595 for (j
= 0; j
< i
.operands
; j
++)
3596 if (i
.types
[j
].bitfield
.inoutportreg
3597 || i
.types
[j
].bitfield
.shiftcount
3598 || i
.types
[j
].bitfield
.acc
3599 || i
.types
[j
].bitfield
.floatacc
)
3602 /* ImmExt should be processed after SSE2AVX. */
3603 if (!i
.tm
.opcode_modifier
.sse2avx
3604 && i
.tm
.opcode_modifier
.immext
)
3607 /* For insns with operands there are more diddles to do to the opcode. */
3610 if (!process_operands ())
3613 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3615 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3616 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3619 if (i
.tm
.opcode_modifier
.vex
)
3620 build_vex_prefix (t
);
3622 if (i
.tm
.opcode_modifier
.evex
)
3623 build_evex_prefix ();
3625 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3626 instructions may define INT_OPCODE as well, so avoid this corner
3627 case for those instructions that use MODRM. */
3628 if (i
.tm
.base_opcode
== INT_OPCODE
3629 && !i
.tm
.opcode_modifier
.modrm
3630 && i
.op
[0].imms
->X_add_number
== 3)
3632 i
.tm
.base_opcode
= INT3_OPCODE
;
3636 if ((i
.tm
.opcode_modifier
.jump
3637 || i
.tm
.opcode_modifier
.jumpbyte
3638 || i
.tm
.opcode_modifier
.jumpdword
)
3639 && i
.op
[0].disps
->X_op
== O_constant
)
3641 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3642 the absolute address given by the constant. Since ix86 jumps and
3643 calls are pc relative, we need to generate a reloc. */
3644 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3645 i
.op
[0].disps
->X_op
= O_symbol
;
3648 if (i
.tm
.opcode_modifier
.rex64
)
3651 /* For 8 bit registers we need an empty rex prefix. Also if the
3652 instruction already has a prefix, we need to convert old
3653 registers to new ones. */
3655 if ((i
.types
[0].bitfield
.reg8
3656 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3657 || (i
.types
[1].bitfield
.reg8
3658 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3659 || ((i
.types
[0].bitfield
.reg8
3660 || i
.types
[1].bitfield
.reg8
)
3665 i
.rex
|= REX_OPCODE
;
3666 for (x
= 0; x
< 2; x
++)
3668 /* Look for 8 bit operand that uses old registers. */
3669 if (i
.types
[x
].bitfield
.reg8
3670 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3672 /* In case it is "hi" register, give up. */
3673 if (i
.op
[x
].regs
->reg_num
> 3)
3674 as_bad (_("can't encode register '%s%s' in an "
3675 "instruction requiring REX prefix."),
3676 register_prefix
, i
.op
[x
].regs
->reg_name
);
3678 /* Otherwise it is equivalent to the extended register.
3679 Since the encoding doesn't change this is merely
3680 cosmetic cleanup for debug output. */
3682 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3688 add_prefix (REX_OPCODE
| i
.rex
);
3690 /* We are ready to output the insn. */
3695 parse_insn (char *line
, char *mnemonic
)
3698 char *token_start
= l
;
3701 const insn_template
*t
;
3707 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3712 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3714 as_bad (_("no such instruction: `%s'"), token_start
);
3719 if (!is_space_char (*l
)
3720 && *l
!= END_OF_INSN
3722 || (*l
!= PREFIX_SEPARATOR
3725 as_bad (_("invalid character %s in mnemonic"),
3726 output_invalid (*l
));
3729 if (token_start
== l
)
3731 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3732 as_bad (_("expecting prefix; got nothing"));
3734 as_bad (_("expecting mnemonic; got nothing"));
3738 /* Look up instruction (or prefix) via hash table. */
3739 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3741 if (*l
!= END_OF_INSN
3742 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3743 && current_templates
3744 && current_templates
->start
->opcode_modifier
.isprefix
)
3746 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3748 as_bad ((flag_code
!= CODE_64BIT
3749 ? _("`%s' is only supported in 64-bit mode")
3750 : _("`%s' is not supported in 64-bit mode")),
3751 current_templates
->start
->name
);
3754 /* If we are in 16-bit mode, do not allow addr16 or data16.
3755 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3756 if ((current_templates
->start
->opcode_modifier
.size16
3757 || current_templates
->start
->opcode_modifier
.size32
)
3758 && flag_code
!= CODE_64BIT
3759 && (current_templates
->start
->opcode_modifier
.size32
3760 ^ (flag_code
== CODE_16BIT
)))
3762 as_bad (_("redundant %s prefix"),
3763 current_templates
->start
->name
);
3766 /* Add prefix, checking for repeated prefixes. */
3767 switch (add_prefix (current_templates
->start
->base_opcode
))
3772 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3773 i
.hle_prefix
= current_templates
->start
->name
;
3774 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3775 i
.bnd_prefix
= current_templates
->start
->name
;
3777 i
.rep_prefix
= current_templates
->start
->name
;
3782 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3789 if (!current_templates
)
3791 /* Check if we should swap operand or force 32bit displacement in
3793 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3795 else if (mnem_p
- 3 == dot_p
3798 i
.disp_encoding
= disp_encoding_8bit
;
3799 else if (mnem_p
- 4 == dot_p
3803 i
.disp_encoding
= disp_encoding_32bit
;
3808 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3811 if (!current_templates
)
3814 /* See if we can get a match by trimming off a suffix. */
3817 case WORD_MNEM_SUFFIX
:
3818 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3819 i
.suffix
= SHORT_MNEM_SUFFIX
;
3821 case BYTE_MNEM_SUFFIX
:
3822 case QWORD_MNEM_SUFFIX
:
3823 i
.suffix
= mnem_p
[-1];
3825 current_templates
= (const templates
*) hash_find (op_hash
,
3828 case SHORT_MNEM_SUFFIX
:
3829 case LONG_MNEM_SUFFIX
:
3832 i
.suffix
= mnem_p
[-1];
3834 current_templates
= (const templates
*) hash_find (op_hash
,
3843 if (intel_float_operand (mnemonic
) == 1)
3844 i
.suffix
= SHORT_MNEM_SUFFIX
;
3846 i
.suffix
= LONG_MNEM_SUFFIX
;
3848 current_templates
= (const templates
*) hash_find (op_hash
,
3853 if (!current_templates
)
3855 as_bad (_("no such instruction: `%s'"), token_start
);
3860 if (current_templates
->start
->opcode_modifier
.jump
3861 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3863 /* Check for a branch hint. We allow ",pt" and ",pn" for
3864 predict taken and predict not taken respectively.
3865 I'm not sure that branch hints actually do anything on loop
3866 and jcxz insns (JumpByte) for current Pentium4 chips. They
3867 may work in the future and it doesn't hurt to accept them
3869 if (l
[0] == ',' && l
[1] == 'p')
3873 if (!add_prefix (DS_PREFIX_OPCODE
))
3877 else if (l
[2] == 'n')
3879 if (!add_prefix (CS_PREFIX_OPCODE
))
3885 /* Any other comma loses. */
3888 as_bad (_("invalid character %s in mnemonic"),
3889 output_invalid (*l
));
3893 /* Check if instruction is supported on specified architecture. */
3895 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3897 supported
|= cpu_flags_match (t
);
3898 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3902 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3904 as_bad (flag_code
== CODE_64BIT
3905 ? _("`%s' is not supported in 64-bit mode")
3906 : _("`%s' is only supported in 64-bit mode"),
3907 current_templates
->start
->name
);
3910 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3912 as_bad (_("`%s' is not supported on `%s%s'"),
3913 current_templates
->start
->name
,
3914 cpu_arch_name
? cpu_arch_name
: default_arch
,
3915 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3920 if (!cpu_arch_flags
.bitfield
.cpui386
3921 && (flag_code
!= CODE_16BIT
))
3923 as_warn (_("use .code16 to ensure correct addressing mode"));
3930 parse_operands (char *l
, const char *mnemonic
)
3934 /* 1 if operand is pending after ','. */
3935 unsigned int expecting_operand
= 0;
3937 /* Non-zero if operand parens not balanced. */
3938 unsigned int paren_not_balanced
;
3940 while (*l
!= END_OF_INSN
)
3942 /* Skip optional white space before operand. */
3943 if (is_space_char (*l
))
3945 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3947 as_bad (_("invalid character %s before operand %d"),
3948 output_invalid (*l
),
3952 token_start
= l
; /* after white space */
3953 paren_not_balanced
= 0;
3954 while (paren_not_balanced
|| *l
!= ',')
3956 if (*l
== END_OF_INSN
)
3958 if (paren_not_balanced
)
3961 as_bad (_("unbalanced parenthesis in operand %d."),
3964 as_bad (_("unbalanced brackets in operand %d."),
3969 break; /* we are done */
3971 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3973 as_bad (_("invalid character %s in operand %d"),
3974 output_invalid (*l
),
3981 ++paren_not_balanced
;
3983 --paren_not_balanced
;
3988 ++paren_not_balanced
;
3990 --paren_not_balanced
;
3994 if (l
!= token_start
)
3995 { /* Yes, we've read in another operand. */
3996 unsigned int operand_ok
;
3997 this_operand
= i
.operands
++;
3998 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3999 if (i
.operands
> MAX_OPERANDS
)
4001 as_bad (_("spurious operands; (%d operands/instruction max)"),
4005 /* Now parse operand adding info to 'i' as we go along. */
4006 END_STRING_AND_SAVE (l
);
4010 i386_intel_operand (token_start
,
4011 intel_float_operand (mnemonic
));
4013 operand_ok
= i386_att_operand (token_start
);
4015 RESTORE_END_STRING (l
);
4021 if (expecting_operand
)
4023 expecting_operand_after_comma
:
4024 as_bad (_("expecting operand after ','; got nothing"));
4029 as_bad (_("expecting operand before ','; got nothing"));
4034 /* Now *l must be either ',' or END_OF_INSN. */
4037 if (*++l
== END_OF_INSN
)
4039 /* Just skip it, if it's \n complain. */
4040 goto expecting_operand_after_comma
;
4042 expecting_operand
= 1;
4049 swap_2_operands (int xchg1
, int xchg2
)
4051 union i386_op temp_op
;
4052 i386_operand_type temp_type
;
4053 enum bfd_reloc_code_real temp_reloc
;
4055 temp_type
= i
.types
[xchg2
];
4056 i
.types
[xchg2
] = i
.types
[xchg1
];
4057 i
.types
[xchg1
] = temp_type
;
4058 temp_op
= i
.op
[xchg2
];
4059 i
.op
[xchg2
] = i
.op
[xchg1
];
4060 i
.op
[xchg1
] = temp_op
;
4061 temp_reloc
= i
.reloc
[xchg2
];
4062 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4063 i
.reloc
[xchg1
] = temp_reloc
;
4067 if (i
.mask
->operand
== xchg1
)
4068 i
.mask
->operand
= xchg2
;
4069 else if (i
.mask
->operand
== xchg2
)
4070 i
.mask
->operand
= xchg1
;
4074 if (i
.broadcast
->operand
== xchg1
)
4075 i
.broadcast
->operand
= xchg2
;
4076 else if (i
.broadcast
->operand
== xchg2
)
4077 i
.broadcast
->operand
= xchg1
;
4081 if (i
.rounding
->operand
== xchg1
)
4082 i
.rounding
->operand
= xchg2
;
4083 else if (i
.rounding
->operand
== xchg2
)
4084 i
.rounding
->operand
= xchg1
;
4089 swap_operands (void)
4095 swap_2_operands (1, i
.operands
- 2);
4098 swap_2_operands (0, i
.operands
- 1);
4104 if (i
.mem_operands
== 2)
4106 const seg_entry
*temp_seg
;
4107 temp_seg
= i
.seg
[0];
4108 i
.seg
[0] = i
.seg
[1];
4109 i
.seg
[1] = temp_seg
;
4113 /* Try to ensure constant immediates are represented in the smallest
4118 char guess_suffix
= 0;
4122 guess_suffix
= i
.suffix
;
4123 else if (i
.reg_operands
)
4125 /* Figure out a suffix from the last register operand specified.
4126 We can't do this properly yet, ie. excluding InOutPortReg,
4127 but the following works for instructions with immediates.
4128 In any case, we can't set i.suffix yet. */
4129 for (op
= i
.operands
; --op
>= 0;)
4130 if (i
.types
[op
].bitfield
.reg8
)
4132 guess_suffix
= BYTE_MNEM_SUFFIX
;
4135 else if (i
.types
[op
].bitfield
.reg16
)
4137 guess_suffix
= WORD_MNEM_SUFFIX
;
4140 else if (i
.types
[op
].bitfield
.reg32
)
4142 guess_suffix
= LONG_MNEM_SUFFIX
;
4145 else if (i
.types
[op
].bitfield
.reg64
)
4147 guess_suffix
= QWORD_MNEM_SUFFIX
;
4151 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4152 guess_suffix
= WORD_MNEM_SUFFIX
;
4154 for (op
= i
.operands
; --op
>= 0;)
4155 if (operand_type_check (i
.types
[op
], imm
))
4157 switch (i
.op
[op
].imms
->X_op
)
4160 /* If a suffix is given, this operand may be shortened. */
4161 switch (guess_suffix
)
4163 case LONG_MNEM_SUFFIX
:
4164 i
.types
[op
].bitfield
.imm32
= 1;
4165 i
.types
[op
].bitfield
.imm64
= 1;
4167 case WORD_MNEM_SUFFIX
:
4168 i
.types
[op
].bitfield
.imm16
= 1;
4169 i
.types
[op
].bitfield
.imm32
= 1;
4170 i
.types
[op
].bitfield
.imm32s
= 1;
4171 i
.types
[op
].bitfield
.imm64
= 1;
4173 case BYTE_MNEM_SUFFIX
:
4174 i
.types
[op
].bitfield
.imm8
= 1;
4175 i
.types
[op
].bitfield
.imm8s
= 1;
4176 i
.types
[op
].bitfield
.imm16
= 1;
4177 i
.types
[op
].bitfield
.imm32
= 1;
4178 i
.types
[op
].bitfield
.imm32s
= 1;
4179 i
.types
[op
].bitfield
.imm64
= 1;
4183 /* If this operand is at most 16 bits, convert it
4184 to a signed 16 bit number before trying to see
4185 whether it will fit in an even smaller size.
4186 This allows a 16-bit operand such as $0xffe0 to
4187 be recognised as within Imm8S range. */
4188 if ((i
.types
[op
].bitfield
.imm16
)
4189 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4191 i
.op
[op
].imms
->X_add_number
=
4192 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4194 if ((i
.types
[op
].bitfield
.imm32
)
4195 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4198 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4199 ^ ((offsetT
) 1 << 31))
4200 - ((offsetT
) 1 << 31));
4203 = operand_type_or (i
.types
[op
],
4204 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4206 /* We must avoid matching of Imm32 templates when 64bit
4207 only immediate is available. */
4208 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4209 i
.types
[op
].bitfield
.imm32
= 0;
4216 /* Symbols and expressions. */
4218 /* Convert symbolic operand to proper sizes for matching, but don't
4219 prevent matching a set of insns that only supports sizes other
4220 than those matching the insn suffix. */
4222 i386_operand_type mask
, allowed
;
4223 const insn_template
*t
;
4225 operand_type_set (&mask
, 0);
4226 operand_type_set (&allowed
, 0);
4228 for (t
= current_templates
->start
;
4229 t
< current_templates
->end
;
4231 allowed
= operand_type_or (allowed
,
4232 t
->operand_types
[op
]);
4233 switch (guess_suffix
)
4235 case QWORD_MNEM_SUFFIX
:
4236 mask
.bitfield
.imm64
= 1;
4237 mask
.bitfield
.imm32s
= 1;
4239 case LONG_MNEM_SUFFIX
:
4240 mask
.bitfield
.imm32
= 1;
4242 case WORD_MNEM_SUFFIX
:
4243 mask
.bitfield
.imm16
= 1;
4245 case BYTE_MNEM_SUFFIX
:
4246 mask
.bitfield
.imm8
= 1;
4251 allowed
= operand_type_and (mask
, allowed
);
4252 if (!operand_type_all_zero (&allowed
))
4253 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4260 /* Try to use the smallest displacement type too. */
4262 optimize_disp (void)
4266 for (op
= i
.operands
; --op
>= 0;)
4267 if (operand_type_check (i
.types
[op
], disp
))
4269 if (i
.op
[op
].disps
->X_op
== O_constant
)
4271 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4273 if (i
.types
[op
].bitfield
.disp16
4274 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4276 /* If this operand is at most 16 bits, convert
4277 to a signed 16 bit number and don't use 64bit
4279 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4280 i
.types
[op
].bitfield
.disp64
= 0;
4282 if (i
.types
[op
].bitfield
.disp32
4283 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4285 /* If this operand is at most 32 bits, convert
4286 to a signed 32 bit number and don't use 64bit
4288 op_disp
&= (((offsetT
) 2 << 31) - 1);
4289 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4290 i
.types
[op
].bitfield
.disp64
= 0;
4292 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4294 i
.types
[op
].bitfield
.disp8
= 0;
4295 i
.types
[op
].bitfield
.disp16
= 0;
4296 i
.types
[op
].bitfield
.disp32
= 0;
4297 i
.types
[op
].bitfield
.disp32s
= 0;
4298 i
.types
[op
].bitfield
.disp64
= 0;
4302 else if (flag_code
== CODE_64BIT
)
4304 if (fits_in_signed_long (op_disp
))
4306 i
.types
[op
].bitfield
.disp64
= 0;
4307 i
.types
[op
].bitfield
.disp32s
= 1;
4309 if (i
.prefix
[ADDR_PREFIX
]
4310 && fits_in_unsigned_long (op_disp
))
4311 i
.types
[op
].bitfield
.disp32
= 1;
4313 if ((i
.types
[op
].bitfield
.disp32
4314 || i
.types
[op
].bitfield
.disp32s
4315 || i
.types
[op
].bitfield
.disp16
)
4316 && fits_in_signed_byte (op_disp
))
4317 i
.types
[op
].bitfield
.disp8
= 1;
4319 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4320 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4322 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4323 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4324 i
.types
[op
].bitfield
.disp8
= 0;
4325 i
.types
[op
].bitfield
.disp16
= 0;
4326 i
.types
[op
].bitfield
.disp32
= 0;
4327 i
.types
[op
].bitfield
.disp32s
= 0;
4328 i
.types
[op
].bitfield
.disp64
= 0;
4331 /* We only support 64bit displacement on constants. */
4332 i
.types
[op
].bitfield
.disp64
= 0;
4336 /* Check if operands are valid for the instruction. */
4339 check_VecOperands (const insn_template
*t
)
4343 /* Without VSIB byte, we can't have a vector register for index. */
4344 if (!t
->opcode_modifier
.vecsib
4346 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4347 || i
.index_reg
->reg_type
.bitfield
.regymm
4348 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4350 i
.error
= unsupported_vector_index_register
;
4354 /* Check if default mask is allowed. */
4355 if (t
->opcode_modifier
.nodefmask
4356 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4358 i
.error
= no_default_mask
;
4362 /* For VSIB byte, we need a vector register for index, and all vector
4363 registers must be distinct. */
4364 if (t
->opcode_modifier
.vecsib
)
4367 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4368 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4369 || (t
->opcode_modifier
.vecsib
== VecSIB256
4370 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4371 || (t
->opcode_modifier
.vecsib
== VecSIB512
4372 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4374 i
.error
= invalid_vsib_address
;
4378 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4379 if (i
.reg_operands
== 2 && !i
.mask
)
4381 gas_assert (i
.types
[0].bitfield
.regxmm
4382 || i
.types
[0].bitfield
.regymm
);
4383 gas_assert (i
.types
[2].bitfield
.regxmm
4384 || i
.types
[2].bitfield
.regymm
);
4385 if (operand_check
== check_none
)
4387 if (register_number (i
.op
[0].regs
)
4388 != register_number (i
.index_reg
)
4389 && register_number (i
.op
[2].regs
)
4390 != register_number (i
.index_reg
)
4391 && register_number (i
.op
[0].regs
)
4392 != register_number (i
.op
[2].regs
))
4394 if (operand_check
== check_error
)
4396 i
.error
= invalid_vector_register_set
;
4399 as_warn (_("mask, index, and destination registers should be distinct"));
4401 else if (i
.reg_operands
== 1 && i
.mask
)
4403 if ((i
.types
[1].bitfield
.regymm
4404 || i
.types
[1].bitfield
.regzmm
)
4405 && (register_number (i
.op
[1].regs
)
4406 == register_number (i
.index_reg
)))
4408 if (operand_check
== check_error
)
4410 i
.error
= invalid_vector_register_set
;
4413 if (operand_check
!= check_none
)
4414 as_warn (_("index and destination registers should be distinct"));
4419 /* Check if broadcast is supported by the instruction and is applied
4420 to the memory operand. */
4423 int broadcasted_opnd_size
;
4425 /* Check if specified broadcast is supported in this instruction,
4426 and it's applied to memory operand of DWORD or QWORD type,
4427 depending on VecESize. */
4428 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4429 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4430 || (t
->opcode_modifier
.vecesize
== 0
4431 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4432 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4433 || (t
->opcode_modifier
.vecesize
== 1
4434 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4435 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4438 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4439 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4440 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4441 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4442 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4446 if ((broadcasted_opnd_size
== 256
4447 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4448 || (broadcasted_opnd_size
== 512
4449 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4452 i
.error
= unsupported_broadcast
;
4456 /* If broadcast is supported in this instruction, we need to check if
4457 operand of one-element size isn't specified without broadcast. */
4458 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4460 /* Find memory operand. */
4461 for (op
= 0; op
< i
.operands
; op
++)
4462 if (operand_type_check (i
.types
[op
], anymem
))
4464 gas_assert (op
< i
.operands
);
4465 /* Check size of the memory operand. */
4466 if ((t
->opcode_modifier
.vecesize
== 0
4467 && i
.types
[op
].bitfield
.dword
)
4468 || (t
->opcode_modifier
.vecesize
== 1
4469 && i
.types
[op
].bitfield
.qword
))
4471 i
.error
= broadcast_needed
;
4476 /* Check if requested masking is supported. */
4478 && (!t
->opcode_modifier
.masking
4480 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4482 i
.error
= unsupported_masking
;
4486 /* Check if masking is applied to dest operand. */
4487 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4489 i
.error
= mask_not_on_destination
;
4496 if ((i
.rounding
->type
!= saeonly
4497 && !t
->opcode_modifier
.staticrounding
)
4498 || (i
.rounding
->type
== saeonly
4499 && (t
->opcode_modifier
.staticrounding
4500 || !t
->opcode_modifier
.sae
)))
4502 i
.error
= unsupported_rc_sae
;
4505 /* If the instruction has several immediate operands and one of
4506 them is rounding, the rounding operand should be the last
4507 immediate operand. */
4508 if (i
.imm_operands
> 1
4509 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4511 i
.error
= rc_sae_operand_not_last_imm
;
4516 /* Check vector Disp8 operand. */
4517 if (t
->opcode_modifier
.disp8memshift
)
4520 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4522 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4524 for (op
= 0; op
< i
.operands
; op
++)
4525 if (operand_type_check (i
.types
[op
], disp
)
4526 && i
.op
[op
].disps
->X_op
== O_constant
)
4528 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4529 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4530 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4533 i
.types
[op
].bitfield
.vec_disp8
= 1;
4536 /* Vector insn can only have Vec_Disp8/Disp32 in
4537 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4539 i
.types
[op
].bitfield
.disp8
= 0;
4540 if (flag_code
!= CODE_16BIT
)
4541 i
.types
[op
].bitfield
.disp16
= 0;
4544 else if (flag_code
!= CODE_16BIT
)
4546 /* One form of this instruction supports vector Disp8.
4547 Try vector Disp8 if we need to use Disp32. */
4548 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4550 i
.error
= try_vector_disp8
;
4562 /* Check if operands are valid for the instruction. Update VEX
4566 VEX_check_operands (const insn_template
*t
)
4568 /* VREX is only valid with EVEX prefix. */
4569 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4571 i
.error
= invalid_register_operand
;
4575 if (!t
->opcode_modifier
.vex
)
4578 /* Only check VEX_Imm4, which must be the first operand. */
4579 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4581 if (i
.op
[0].imms
->X_op
!= O_constant
4582 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4588 /* Turn off Imm8 so that update_imm won't complain. */
4589 i
.types
[0] = vec_imm4
;
4595 static const insn_template
*
4596 match_template (void)
4598 /* Points to template once we've found it. */
4599 const insn_template
*t
;
4600 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4601 i386_operand_type overlap4
;
4602 unsigned int found_reverse_match
;
4603 i386_opcode_modifier suffix_check
;
4604 i386_operand_type operand_types
[MAX_OPERANDS
];
4605 int addr_prefix_disp
;
4607 unsigned int found_cpu_match
;
4608 unsigned int check_register
;
4609 enum i386_error specific_error
= 0;
4611 #if MAX_OPERANDS != 5
4612 # error "MAX_OPERANDS must be 5."
4615 found_reverse_match
= 0;
4616 addr_prefix_disp
= -1;
4618 memset (&suffix_check
, 0, sizeof (suffix_check
));
4619 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4620 suffix_check
.no_bsuf
= 1;
4621 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4622 suffix_check
.no_wsuf
= 1;
4623 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4624 suffix_check
.no_ssuf
= 1;
4625 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4626 suffix_check
.no_lsuf
= 1;
4627 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4628 suffix_check
.no_qsuf
= 1;
4629 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4630 suffix_check
.no_ldsuf
= 1;
4632 /* Must have right number of operands. */
4633 i
.error
= number_of_operands_mismatch
;
4635 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4637 addr_prefix_disp
= -1;
4639 if (i
.operands
!= t
->operands
)
4642 /* Check processor support. */
4643 i
.error
= unsupported
;
4644 found_cpu_match
= (cpu_flags_match (t
)
4645 == CPU_FLAGS_PERFECT_MATCH
);
4646 if (!found_cpu_match
)
4649 /* Check old gcc support. */
4650 i
.error
= old_gcc_only
;
4651 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4654 /* Check AT&T mnemonic. */
4655 i
.error
= unsupported_with_intel_mnemonic
;
4656 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4659 /* Check AT&T/Intel syntax. */
4660 i
.error
= unsupported_syntax
;
4661 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4662 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4665 /* Check the suffix, except for some instructions in intel mode. */
4666 i
.error
= invalid_instruction_suffix
;
4667 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4668 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4669 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4670 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4671 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4672 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4673 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4676 if (!operand_size_match (t
))
4679 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4680 operand_types
[j
] = t
->operand_types
[j
];
4682 /* In general, don't allow 64-bit operands in 32-bit mode. */
4683 if (i
.suffix
== QWORD_MNEM_SUFFIX
4684 && flag_code
!= CODE_64BIT
4686 ? (!t
->opcode_modifier
.ignoresize
4687 && !intel_float_operand (t
->name
))
4688 : intel_float_operand (t
->name
) != 2)
4689 && ((!operand_types
[0].bitfield
.regmmx
4690 && !operand_types
[0].bitfield
.regxmm
4691 && !operand_types
[0].bitfield
.regymm
4692 && !operand_types
[0].bitfield
.regzmm
)
4693 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4694 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
4695 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
4696 && !!operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4697 && (t
->base_opcode
!= 0x0fc7
4698 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4701 /* In general, don't allow 32-bit operands on pre-386. */
4702 else if (i
.suffix
== LONG_MNEM_SUFFIX
4703 && !cpu_arch_flags
.bitfield
.cpui386
4705 ? (!t
->opcode_modifier
.ignoresize
4706 && !intel_float_operand (t
->name
))
4707 : intel_float_operand (t
->name
) != 2)
4708 && ((!operand_types
[0].bitfield
.regmmx
4709 && !operand_types
[0].bitfield
.regxmm
)
4710 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4711 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4714 /* Do not verify operands when there are none. */
4718 /* We've found a match; break out of loop. */
4722 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4723 into Disp32/Disp16/Disp32 operand. */
4724 if (i
.prefix
[ADDR_PREFIX
] != 0)
4726 /* There should be only one Disp operand. */
4730 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4732 if (operand_types
[j
].bitfield
.disp16
)
4734 addr_prefix_disp
= j
;
4735 operand_types
[j
].bitfield
.disp32
= 1;
4736 operand_types
[j
].bitfield
.disp16
= 0;
4742 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4744 if (operand_types
[j
].bitfield
.disp32
)
4746 addr_prefix_disp
= j
;
4747 operand_types
[j
].bitfield
.disp32
= 0;
4748 operand_types
[j
].bitfield
.disp16
= 1;
4754 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4756 if (operand_types
[j
].bitfield
.disp64
)
4758 addr_prefix_disp
= j
;
4759 operand_types
[j
].bitfield
.disp64
= 0;
4760 operand_types
[j
].bitfield
.disp32
= 1;
4768 /* We check register size if needed. */
4769 check_register
= t
->opcode_modifier
.checkregsize
;
4770 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4771 switch (t
->operands
)
4774 if (!operand_type_match (overlap0
, i
.types
[0]))
4778 /* xchg %eax, %eax is a special case. It is an aliase for nop
4779 only in 32bit mode and we can use opcode 0x90. In 64bit
4780 mode, we can't use 0x90 for xchg %eax, %eax since it should
4781 zero-extend %eax to %rax. */
4782 if (flag_code
== CODE_64BIT
4783 && t
->base_opcode
== 0x90
4784 && operand_type_equal (&i
.types
[0], &acc32
)
4785 && operand_type_equal (&i
.types
[1], &acc32
))
4789 /* If we swap operand in encoding, we either match
4790 the next one or reverse direction of operands. */
4791 if (t
->opcode_modifier
.s
)
4793 else if (t
->opcode_modifier
.d
)
4798 /* If we swap operand in encoding, we match the next one. */
4799 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4803 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4804 if (!operand_type_match (overlap0
, i
.types
[0])
4805 || !operand_type_match (overlap1
, i
.types
[1])
4807 && !operand_type_register_match (overlap0
, i
.types
[0],
4809 overlap1
, i
.types
[1],
4812 /* Check if other direction is valid ... */
4813 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4817 /* Try reversing direction of operands. */
4818 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4819 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4820 if (!operand_type_match (overlap0
, i
.types
[0])
4821 || !operand_type_match (overlap1
, i
.types
[1])
4823 && !operand_type_register_match (overlap0
,
4830 /* Does not match either direction. */
4833 /* found_reverse_match holds which of D or FloatDR
4835 if (t
->opcode_modifier
.d
)
4836 found_reverse_match
= Opcode_D
;
4837 else if (t
->opcode_modifier
.floatd
)
4838 found_reverse_match
= Opcode_FloatD
;
4840 found_reverse_match
= 0;
4841 if (t
->opcode_modifier
.floatr
)
4842 found_reverse_match
|= Opcode_FloatR
;
4846 /* Found a forward 2 operand match here. */
4847 switch (t
->operands
)
4850 overlap4
= operand_type_and (i
.types
[4],
4853 overlap3
= operand_type_and (i
.types
[3],
4856 overlap2
= operand_type_and (i
.types
[2],
4861 switch (t
->operands
)
4864 if (!operand_type_match (overlap4
, i
.types
[4])
4865 || !operand_type_register_match (overlap3
,
4873 if (!operand_type_match (overlap3
, i
.types
[3])
4875 && !operand_type_register_match (overlap2
,
4883 /* Here we make use of the fact that there are no
4884 reverse match 3 operand instructions, and all 3
4885 operand instructions only need to be checked for
4886 register consistency between operands 2 and 3. */
4887 if (!operand_type_match (overlap2
, i
.types
[2])
4889 && !operand_type_register_match (overlap1
,
4899 /* Found either forward/reverse 2, 3 or 4 operand match here:
4900 slip through to break. */
4902 if (!found_cpu_match
)
4904 found_reverse_match
= 0;
4908 /* Check if vector and VEX operands are valid. */
4909 if (check_VecOperands (t
) || VEX_check_operands (t
))
4911 specific_error
= i
.error
;
4915 /* We've found a match; break out of loop. */
4919 if (t
== current_templates
->end
)
4921 /* We found no match. */
4922 const char *err_msg
;
4923 switch (specific_error
? specific_error
: i
.error
)
4927 case operand_size_mismatch
:
4928 err_msg
= _("operand size mismatch");
4930 case operand_type_mismatch
:
4931 err_msg
= _("operand type mismatch");
4933 case register_type_mismatch
:
4934 err_msg
= _("register type mismatch");
4936 case number_of_operands_mismatch
:
4937 err_msg
= _("number of operands mismatch");
4939 case invalid_instruction_suffix
:
4940 err_msg
= _("invalid instruction suffix");
4943 err_msg
= _("constant doesn't fit in 4 bits");
4946 err_msg
= _("only supported with old gcc");
4948 case unsupported_with_intel_mnemonic
:
4949 err_msg
= _("unsupported with Intel mnemonic");
4951 case unsupported_syntax
:
4952 err_msg
= _("unsupported syntax");
4955 as_bad (_("unsupported instruction `%s'"),
4956 current_templates
->start
->name
);
4958 case invalid_vsib_address
:
4959 err_msg
= _("invalid VSIB address");
4961 case invalid_vector_register_set
:
4962 err_msg
= _("mask, index, and destination registers must be distinct");
4964 case unsupported_vector_index_register
:
4965 err_msg
= _("unsupported vector index register");
4967 case unsupported_broadcast
:
4968 err_msg
= _("unsupported broadcast");
4970 case broadcast_not_on_src_operand
:
4971 err_msg
= _("broadcast not on source memory operand");
4973 case broadcast_needed
:
4974 err_msg
= _("broadcast is needed for operand of such type");
4976 case unsupported_masking
:
4977 err_msg
= _("unsupported masking");
4979 case mask_not_on_destination
:
4980 err_msg
= _("mask not on destination operand");
4982 case no_default_mask
:
4983 err_msg
= _("default mask isn't allowed");
4985 case unsupported_rc_sae
:
4986 err_msg
= _("unsupported static rounding/sae");
4988 case rc_sae_operand_not_last_imm
:
4990 err_msg
= _("RC/SAE operand must precede immediate operands");
4992 err_msg
= _("RC/SAE operand must follow immediate operands");
4994 case invalid_register_operand
:
4995 err_msg
= _("invalid register operand");
4998 as_bad (_("%s for `%s'"), err_msg
,
4999 current_templates
->start
->name
);
5003 if (!quiet_warnings
)
5006 && (i
.types
[0].bitfield
.jumpabsolute
5007 != operand_types
[0].bitfield
.jumpabsolute
))
5009 as_warn (_("indirect %s without `*'"), t
->name
);
5012 if (t
->opcode_modifier
.isprefix
5013 && t
->opcode_modifier
.ignoresize
)
5015 /* Warn them that a data or address size prefix doesn't
5016 affect assembly of the next line of code. */
5017 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5021 /* Copy the template we found. */
5024 if (addr_prefix_disp
!= -1)
5025 i
.tm
.operand_types
[addr_prefix_disp
]
5026 = operand_types
[addr_prefix_disp
];
5028 if (found_reverse_match
)
5030 /* If we found a reverse match we must alter the opcode
5031 direction bit. found_reverse_match holds bits to change
5032 (different for int & float insns). */
5034 i
.tm
.base_opcode
^= found_reverse_match
;
5036 i
.tm
.operand_types
[0] = operand_types
[1];
5037 i
.tm
.operand_types
[1] = operand_types
[0];
5046 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5047 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5049 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5051 as_bad (_("`%s' operand %d must use `%ses' segment"),
5057 /* There's only ever one segment override allowed per instruction.
5058 This instruction possibly has a legal segment override on the
5059 second operand, so copy the segment to where non-string
5060 instructions store it, allowing common code. */
5061 i
.seg
[0] = i
.seg
[1];
5063 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5065 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5067 as_bad (_("`%s' operand %d must use `%ses' segment"),
5078 process_suffix (void)
5080 /* If matched instruction specifies an explicit instruction mnemonic
5082 if (i
.tm
.opcode_modifier
.size16
)
5083 i
.suffix
= WORD_MNEM_SUFFIX
;
5084 else if (i
.tm
.opcode_modifier
.size32
)
5085 i
.suffix
= LONG_MNEM_SUFFIX
;
5086 else if (i
.tm
.opcode_modifier
.size64
)
5087 i
.suffix
= QWORD_MNEM_SUFFIX
;
5088 else if (i
.reg_operands
)
5090 /* If there's no instruction mnemonic suffix we try to invent one
5091 based on register operands. */
5094 /* We take i.suffix from the last register operand specified,
5095 Destination register type is more significant than source
5096 register type. crc32 in SSE4.2 prefers source register
5098 if (i
.tm
.base_opcode
== 0xf20f38f1)
5100 if (i
.types
[0].bitfield
.reg16
)
5101 i
.suffix
= WORD_MNEM_SUFFIX
;
5102 else if (i
.types
[0].bitfield
.reg32
)
5103 i
.suffix
= LONG_MNEM_SUFFIX
;
5104 else if (i
.types
[0].bitfield
.reg64
)
5105 i
.suffix
= QWORD_MNEM_SUFFIX
;
5107 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5109 if (i
.types
[0].bitfield
.reg8
)
5110 i
.suffix
= BYTE_MNEM_SUFFIX
;
5117 if (i
.tm
.base_opcode
== 0xf20f38f1
5118 || i
.tm
.base_opcode
== 0xf20f38f0)
5120 /* We have to know the operand size for crc32. */
5121 as_bad (_("ambiguous memory operand size for `%s`"),
5126 for (op
= i
.operands
; --op
>= 0;)
5127 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5129 if (i
.types
[op
].bitfield
.reg8
)
5131 i
.suffix
= BYTE_MNEM_SUFFIX
;
5134 else if (i
.types
[op
].bitfield
.reg16
)
5136 i
.suffix
= WORD_MNEM_SUFFIX
;
5139 else if (i
.types
[op
].bitfield
.reg32
)
5141 i
.suffix
= LONG_MNEM_SUFFIX
;
5144 else if (i
.types
[op
].bitfield
.reg64
)
5146 i
.suffix
= QWORD_MNEM_SUFFIX
;
5152 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5155 && i
.tm
.opcode_modifier
.ignoresize
5156 && i
.tm
.opcode_modifier
.no_bsuf
)
5158 else if (!check_byte_reg ())
5161 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5164 && i
.tm
.opcode_modifier
.ignoresize
5165 && i
.tm
.opcode_modifier
.no_lsuf
)
5167 else if (!check_long_reg ())
5170 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5173 && i
.tm
.opcode_modifier
.ignoresize
5174 && i
.tm
.opcode_modifier
.no_qsuf
)
5176 else if (!check_qword_reg ())
5179 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5182 && i
.tm
.opcode_modifier
.ignoresize
5183 && i
.tm
.opcode_modifier
.no_wsuf
)
5185 else if (!check_word_reg ())
5188 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5189 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5190 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5192 /* Skip if the instruction has x/y/z suffix. match_template
5193 should check if it is a valid suffix. */
5195 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5196 /* Do nothing if the instruction is going to ignore the prefix. */
5201 else if (i
.tm
.opcode_modifier
.defaultsize
5203 /* exclude fldenv/frstor/fsave/fstenv */
5204 && i
.tm
.opcode_modifier
.no_ssuf
)
5206 i
.suffix
= stackop_size
;
5208 else if (intel_syntax
5210 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5211 || i
.tm
.opcode_modifier
.jumpbyte
5212 || i
.tm
.opcode_modifier
.jumpintersegment
5213 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5214 && i
.tm
.extension_opcode
<= 3)))
5219 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5221 i
.suffix
= QWORD_MNEM_SUFFIX
;
5225 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5226 i
.suffix
= LONG_MNEM_SUFFIX
;
5229 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5230 i
.suffix
= WORD_MNEM_SUFFIX
;
5239 if (i
.tm
.opcode_modifier
.w
)
5241 as_bad (_("no instruction mnemonic suffix given and "
5242 "no register operands; can't size instruction"));
5248 unsigned int suffixes
;
5250 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5251 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5253 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5255 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5257 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5259 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5262 /* There are more than suffix matches. */
5263 if (i
.tm
.opcode_modifier
.w
5264 || ((suffixes
& (suffixes
- 1))
5265 && !i
.tm
.opcode_modifier
.defaultsize
5266 && !i
.tm
.opcode_modifier
.ignoresize
))
5268 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5274 /* Change the opcode based on the operand size given by i.suffix;
5275 We don't need to change things for byte insns. */
5278 && i
.suffix
!= BYTE_MNEM_SUFFIX
5279 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5280 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5281 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5283 /* It's not a byte, select word/dword operation. */
5284 if (i
.tm
.opcode_modifier
.w
)
5286 if (i
.tm
.opcode_modifier
.shortform
)
5287 i
.tm
.base_opcode
|= 8;
5289 i
.tm
.base_opcode
|= 1;
5292 /* Now select between word & dword operations via the operand
5293 size prefix, except for instructions that will ignore this
5295 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5297 /* The address size override prefix changes the size of the
5299 if ((flag_code
== CODE_32BIT
5300 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5301 || (flag_code
!= CODE_32BIT
5302 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5303 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5306 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5307 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5308 && !i
.tm
.opcode_modifier
.ignoresize
5309 && !i
.tm
.opcode_modifier
.floatmf
5310 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5311 || (flag_code
== CODE_64BIT
5312 && i
.tm
.opcode_modifier
.jumpbyte
)))
5314 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5316 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5317 prefix
= ADDR_PREFIX_OPCODE
;
5319 if (!add_prefix (prefix
))
5323 /* Set mode64 for an operand. */
5324 if (i
.suffix
== QWORD_MNEM_SUFFIX
5325 && flag_code
== CODE_64BIT
5326 && !i
.tm
.opcode_modifier
.norex64
)
5328 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5329 need rex64. cmpxchg8b is also a special case. */
5330 if (! (i
.operands
== 2
5331 && i
.tm
.base_opcode
== 0x90
5332 && i
.tm
.extension_opcode
== None
5333 && operand_type_equal (&i
.types
[0], &acc64
)
5334 && operand_type_equal (&i
.types
[1], &acc64
))
5335 && ! (i
.operands
== 1
5336 && i
.tm
.base_opcode
== 0xfc7
5337 && i
.tm
.extension_opcode
== 1
5338 && !operand_type_check (i
.types
[0], reg
)
5339 && operand_type_check (i
.types
[0], anymem
)))
5343 /* Size floating point instruction. */
5344 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5345 if (i
.tm
.opcode_modifier
.floatmf
)
5346 i
.tm
.base_opcode
^= 4;
5353 check_byte_reg (void)
5357 for (op
= i
.operands
; --op
>= 0;)
5359 /* If this is an eight bit register, it's OK. If it's the 16 or
5360 32 bit version of an eight bit register, we will just use the
5361 low portion, and that's OK too. */
5362 if (i
.types
[op
].bitfield
.reg8
)
5365 /* I/O port address operands are OK too. */
5366 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5369 /* crc32 doesn't generate this warning. */
5370 if (i
.tm
.base_opcode
== 0xf20f38f0)
5373 if ((i
.types
[op
].bitfield
.reg16
5374 || i
.types
[op
].bitfield
.reg32
5375 || i
.types
[op
].bitfield
.reg64
)
5376 && i
.op
[op
].regs
->reg_num
< 4
5377 /* Prohibit these changes in 64bit mode, since the lowering
5378 would be more complicated. */
5379 && flag_code
!= CODE_64BIT
)
5381 #if REGISTER_WARNINGS
5382 if (!quiet_warnings
)
5383 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5385 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5386 ? REGNAM_AL
- REGNAM_AX
5387 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5389 i
.op
[op
].regs
->reg_name
,
5394 /* Any other register is bad. */
5395 if (i
.types
[op
].bitfield
.reg16
5396 || i
.types
[op
].bitfield
.reg32
5397 || i
.types
[op
].bitfield
.reg64
5398 || i
.types
[op
].bitfield
.regmmx
5399 || i
.types
[op
].bitfield
.regxmm
5400 || i
.types
[op
].bitfield
.regymm
5401 || i
.types
[op
].bitfield
.regzmm
5402 || i
.types
[op
].bitfield
.sreg2
5403 || i
.types
[op
].bitfield
.sreg3
5404 || i
.types
[op
].bitfield
.control
5405 || i
.types
[op
].bitfield
.debug
5406 || i
.types
[op
].bitfield
.test
5407 || i
.types
[op
].bitfield
.floatreg
5408 || i
.types
[op
].bitfield
.floatacc
)
5410 as_bad (_("`%s%s' not allowed with `%s%c'"),
5412 i
.op
[op
].regs
->reg_name
,
5422 check_long_reg (void)
5426 for (op
= i
.operands
; --op
>= 0;)
5427 /* Reject eight bit registers, except where the template requires
5428 them. (eg. movzb) */
5429 if (i
.types
[op
].bitfield
.reg8
5430 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5431 || i
.tm
.operand_types
[op
].bitfield
.reg32
5432 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5434 as_bad (_("`%s%s' not allowed with `%s%c'"),
5436 i
.op
[op
].regs
->reg_name
,
5441 /* Warn if the e prefix on a general reg is missing. */
5442 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5443 && i
.types
[op
].bitfield
.reg16
5444 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5445 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5447 /* Prohibit these changes in the 64bit mode, since the
5448 lowering is more complicated. */
5449 if (flag_code
== CODE_64BIT
)
5451 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5452 register_prefix
, i
.op
[op
].regs
->reg_name
,
5456 #if REGISTER_WARNINGS
5457 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5459 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5460 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5463 /* Warn if the r prefix on a general reg is present. */
5464 else if (i
.types
[op
].bitfield
.reg64
5465 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5466 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5469 && i
.tm
.opcode_modifier
.toqword
5470 && !i
.types
[0].bitfield
.regxmm
)
5472 /* Convert to QWORD. We want REX byte. */
5473 i
.suffix
= QWORD_MNEM_SUFFIX
;
5477 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5478 register_prefix
, i
.op
[op
].regs
->reg_name
,
5487 check_qword_reg (void)
5491 for (op
= i
.operands
; --op
>= 0; )
5492 /* Reject eight bit registers, except where the template requires
5493 them. (eg. movzb) */
5494 if (i
.types
[op
].bitfield
.reg8
5495 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5496 || i
.tm
.operand_types
[op
].bitfield
.reg32
5497 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5499 as_bad (_("`%s%s' not allowed with `%s%c'"),
5501 i
.op
[op
].regs
->reg_name
,
5506 /* Warn if the r prefix on a general reg is missing. */
5507 else if ((i
.types
[op
].bitfield
.reg16
5508 || i
.types
[op
].bitfield
.reg32
)
5509 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5510 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5512 /* Prohibit these changes in the 64bit mode, since the
5513 lowering is more complicated. */
5515 && i
.tm
.opcode_modifier
.todword
5516 && !i
.types
[0].bitfield
.regxmm
)
5518 /* Convert to DWORD. We don't want REX byte. */
5519 i
.suffix
= LONG_MNEM_SUFFIX
;
5523 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5524 register_prefix
, i
.op
[op
].regs
->reg_name
,
5533 check_word_reg (void)
5536 for (op
= i
.operands
; --op
>= 0;)
5537 /* Reject eight bit registers, except where the template requires
5538 them. (eg. movzb) */
5539 if (i
.types
[op
].bitfield
.reg8
5540 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5541 || i
.tm
.operand_types
[op
].bitfield
.reg32
5542 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5544 as_bad (_("`%s%s' not allowed with `%s%c'"),
5546 i
.op
[op
].regs
->reg_name
,
5551 /* Warn if the e or r prefix on a general reg is present. */
5552 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5553 && (i
.types
[op
].bitfield
.reg32
5554 || i
.types
[op
].bitfield
.reg64
)
5555 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5556 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5558 /* Prohibit these changes in the 64bit mode, since the
5559 lowering is more complicated. */
5560 if (flag_code
== CODE_64BIT
)
5562 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5563 register_prefix
, i
.op
[op
].regs
->reg_name
,
5567 #if REGISTER_WARNINGS
5568 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5570 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5571 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5578 update_imm (unsigned int j
)
5580 i386_operand_type overlap
= i
.types
[j
];
5581 if ((overlap
.bitfield
.imm8
5582 || overlap
.bitfield
.imm8s
5583 || overlap
.bitfield
.imm16
5584 || overlap
.bitfield
.imm32
5585 || overlap
.bitfield
.imm32s
5586 || overlap
.bitfield
.imm64
)
5587 && !operand_type_equal (&overlap
, &imm8
)
5588 && !operand_type_equal (&overlap
, &imm8s
)
5589 && !operand_type_equal (&overlap
, &imm16
)
5590 && !operand_type_equal (&overlap
, &imm32
)
5591 && !operand_type_equal (&overlap
, &imm32s
)
5592 && !operand_type_equal (&overlap
, &imm64
))
5596 i386_operand_type temp
;
5598 operand_type_set (&temp
, 0);
5599 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5601 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5602 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5604 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5605 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5606 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5608 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5609 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5612 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5615 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5616 || operand_type_equal (&overlap
, &imm16_32
)
5617 || operand_type_equal (&overlap
, &imm16_32s
))
5619 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5624 if (!operand_type_equal (&overlap
, &imm8
)
5625 && !operand_type_equal (&overlap
, &imm8s
)
5626 && !operand_type_equal (&overlap
, &imm16
)
5627 && !operand_type_equal (&overlap
, &imm32
)
5628 && !operand_type_equal (&overlap
, &imm32s
)
5629 && !operand_type_equal (&overlap
, &imm64
))
5631 as_bad (_("no instruction mnemonic suffix given; "
5632 "can't determine immediate size"));
5636 i
.types
[j
] = overlap
;
5646 /* Update the first 2 immediate operands. */
5647 n
= i
.operands
> 2 ? 2 : i
.operands
;
5650 for (j
= 0; j
< n
; j
++)
5651 if (update_imm (j
) == 0)
5654 /* The 3rd operand can't be immediate operand. */
5655 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5662 bad_implicit_operand (int xmm
)
5664 const char *ireg
= xmm
? "xmm0" : "ymm0";
5667 as_bad (_("the last operand of `%s' must be `%s%s'"),
5668 i
.tm
.name
, register_prefix
, ireg
);
5670 as_bad (_("the first operand of `%s' must be `%s%s'"),
5671 i
.tm
.name
, register_prefix
, ireg
);
5676 process_operands (void)
5678 /* Default segment register this instruction will use for memory
5679 accesses. 0 means unknown. This is only for optimizing out
5680 unnecessary segment overrides. */
5681 const seg_entry
*default_seg
= 0;
5683 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5685 unsigned int dupl
= i
.operands
;
5686 unsigned int dest
= dupl
- 1;
5689 /* The destination must be an xmm register. */
5690 gas_assert (i
.reg_operands
5691 && MAX_OPERANDS
> dupl
5692 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5694 if (i
.tm
.opcode_modifier
.firstxmm0
)
5696 /* The first operand is implicit and must be xmm0. */
5697 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5698 if (register_number (i
.op
[0].regs
) != 0)
5699 return bad_implicit_operand (1);
5701 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5703 /* Keep xmm0 for instructions with VEX prefix and 3
5709 /* We remove the first xmm0 and keep the number of
5710 operands unchanged, which in fact duplicates the
5712 for (j
= 1; j
< i
.operands
; j
++)
5714 i
.op
[j
- 1] = i
.op
[j
];
5715 i
.types
[j
- 1] = i
.types
[j
];
5716 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5720 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5722 gas_assert ((MAX_OPERANDS
- 1) > dupl
5723 && (i
.tm
.opcode_modifier
.vexsources
5726 /* Add the implicit xmm0 for instructions with VEX prefix
5728 for (j
= i
.operands
; j
> 0; j
--)
5730 i
.op
[j
] = i
.op
[j
- 1];
5731 i
.types
[j
] = i
.types
[j
- 1];
5732 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5735 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5736 i
.types
[0] = regxmm
;
5737 i
.tm
.operand_types
[0] = regxmm
;
5740 i
.reg_operands
+= 2;
5745 i
.op
[dupl
] = i
.op
[dest
];
5746 i
.types
[dupl
] = i
.types
[dest
];
5747 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5756 i
.op
[dupl
] = i
.op
[dest
];
5757 i
.types
[dupl
] = i
.types
[dest
];
5758 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5761 if (i
.tm
.opcode_modifier
.immext
)
5764 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5768 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5769 gas_assert (i
.reg_operands
5770 && (operand_type_equal (&i
.types
[0], ®xmm
)
5771 || operand_type_equal (&i
.types
[0], ®ymm
)
5772 || operand_type_equal (&i
.types
[0], ®zmm
)));
5773 if (register_number (i
.op
[0].regs
) != 0)
5774 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5776 for (j
= 1; j
< i
.operands
; j
++)
5778 i
.op
[j
- 1] = i
.op
[j
];
5779 i
.types
[j
- 1] = i
.types
[j
];
5781 /* We need to adjust fields in i.tm since they are used by
5782 build_modrm_byte. */
5783 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5790 else if (i
.tm
.opcode_modifier
.regkludge
)
5792 /* The imul $imm, %reg instruction is converted into
5793 imul $imm, %reg, %reg, and the clr %reg instruction
5794 is converted into xor %reg, %reg. */
5796 unsigned int first_reg_op
;
5798 if (operand_type_check (i
.types
[0], reg
))
5802 /* Pretend we saw the extra register operand. */
5803 gas_assert (i
.reg_operands
== 1
5804 && i
.op
[first_reg_op
+ 1].regs
== 0);
5805 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5806 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5811 if (i
.tm
.opcode_modifier
.shortform
)
5813 if (i
.types
[0].bitfield
.sreg2
5814 || i
.types
[0].bitfield
.sreg3
)
5816 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5817 && i
.op
[0].regs
->reg_num
== 1)
5819 as_bad (_("you can't `pop %scs'"), register_prefix
);
5822 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5823 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5828 /* The register or float register operand is in operand
5832 if (i
.types
[0].bitfield
.floatreg
5833 || operand_type_check (i
.types
[0], reg
))
5837 /* Register goes in low 3 bits of opcode. */
5838 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5839 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5841 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5843 /* Warn about some common errors, but press on regardless.
5844 The first case can be generated by gcc (<= 2.8.1). */
5845 if (i
.operands
== 2)
5847 /* Reversed arguments on faddp, fsubp, etc. */
5848 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5849 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5850 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5854 /* Extraneous `l' suffix on fp insn. */
5855 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5856 register_prefix
, i
.op
[0].regs
->reg_name
);
5861 else if (i
.tm
.opcode_modifier
.modrm
)
5863 /* The opcode is completed (modulo i.tm.extension_opcode which
5864 must be put into the modrm byte). Now, we make the modrm and
5865 index base bytes based on all the info we've collected. */
5867 default_seg
= build_modrm_byte ();
5869 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5873 else if (i
.tm
.opcode_modifier
.isstring
)
5875 /* For the string instructions that allow a segment override
5876 on one of their operands, the default segment is ds. */
5880 if (i
.tm
.base_opcode
== 0x8d /* lea */
5883 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5885 /* If a segment was explicitly specified, and the specified segment
5886 is not the default, use an opcode prefix to select it. If we
5887 never figured out what the default segment is, then default_seg
5888 will be zero at this point, and the specified segment prefix will
5890 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5892 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5898 static const seg_entry
*
5899 build_modrm_byte (void)
5901 const seg_entry
*default_seg
= 0;
5902 unsigned int source
, dest
;
5905 /* The first operand of instructions with VEX prefix and 3 sources
5906 must be VEX_Imm4. */
5907 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5910 unsigned int nds
, reg_slot
;
5913 if (i
.tm
.opcode_modifier
.veximmext
5914 && i
.tm
.opcode_modifier
.immext
)
5916 dest
= i
.operands
- 2;
5917 gas_assert (dest
== 3);
5920 dest
= i
.operands
- 1;
5923 /* There are 2 kinds of instructions:
5924 1. 5 operands: 4 register operands or 3 register operands
5925 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5926 VexW0 or VexW1. The destination must be either XMM, YMM or
5928 2. 4 operands: 4 register operands or 3 register operands
5929 plus 1 memory operand, VexXDS, and VexImmExt */
5930 gas_assert ((i
.reg_operands
== 4
5931 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5932 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5933 && (i
.tm
.opcode_modifier
.veximmext
5934 || (i
.imm_operands
== 1
5935 && i
.types
[0].bitfield
.vec_imm4
5936 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5937 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5938 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5939 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5940 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5942 if (i
.imm_operands
== 0)
5944 /* When there is no immediate operand, generate an 8bit
5945 immediate operand to encode the first operand. */
5946 exp
= &im_expressions
[i
.imm_operands
++];
5947 i
.op
[i
.operands
].imms
= exp
;
5948 i
.types
[i
.operands
] = imm8
;
5950 /* If VexW1 is set, the first operand is the source and
5951 the second operand is encoded in the immediate operand. */
5952 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5963 /* FMA swaps REG and NDS. */
5964 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5972 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5974 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5976 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5978 exp
->X_op
= O_constant
;
5979 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
5980 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
5984 unsigned int imm_slot
;
5986 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5988 /* If VexW0 is set, the third operand is the source and
5989 the second operand is encoded in the immediate
5996 /* VexW1 is set, the second operand is the source and
5997 the third operand is encoded in the immediate
6003 if (i
.tm
.opcode_modifier
.immext
)
6005 /* When ImmExt is set, the immdiate byte is the last
6007 imm_slot
= i
.operands
- 1;
6015 /* Turn on Imm8 so that output_imm will generate it. */
6016 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6019 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6021 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6023 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6025 i
.op
[imm_slot
].imms
->X_add_number
6026 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6027 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6030 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6031 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6033 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6035 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6040 /* i.reg_operands MUST be the number of real register operands;
6041 implicit registers do not count. If there are 3 register
6042 operands, it must be a instruction with VexNDS. For a
6043 instruction with VexNDD, the destination register is encoded
6044 in VEX prefix. If there are 4 register operands, it must be
6045 a instruction with VEX prefix and 3 sources. */
6046 if (i
.mem_operands
== 0
6047 && ((i
.reg_operands
== 2
6048 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6049 || (i
.reg_operands
== 3
6050 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6051 || (i
.reg_operands
== 4 && vex_3_sources
)))
6059 /* When there are 3 operands, one of them may be immediate,
6060 which may be the first or the last operand. Otherwise,
6061 the first operand must be shift count register (cl) or it
6062 is an instruction with VexNDS. */
6063 gas_assert (i
.imm_operands
== 1
6064 || (i
.imm_operands
== 0
6065 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6066 || i
.types
[0].bitfield
.shiftcount
)));
6067 if (operand_type_check (i
.types
[0], imm
)
6068 || i
.types
[0].bitfield
.shiftcount
)
6074 /* When there are 4 operands, the first two must be 8bit
6075 immediate operands. The source operand will be the 3rd
6078 For instructions with VexNDS, if the first operand
6079 an imm8, the source operand is the 2nd one. If the last
6080 operand is imm8, the source operand is the first one. */
6081 gas_assert ((i
.imm_operands
== 2
6082 && i
.types
[0].bitfield
.imm8
6083 && i
.types
[1].bitfield
.imm8
)
6084 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6085 && i
.imm_operands
== 1
6086 && (i
.types
[0].bitfield
.imm8
6087 || i
.types
[i
.operands
- 1].bitfield
.imm8
6089 if (i
.imm_operands
== 2)
6093 if (i
.types
[0].bitfield
.imm8
)
6100 if (i
.tm
.opcode_modifier
.evex
)
6102 /* For EVEX instructions, when there are 5 operands, the
6103 first one must be immediate operand. If the second one
6104 is immediate operand, the source operand is the 3th
6105 one. If the last one is immediate operand, the source
6106 operand is the 2nd one. */
6107 gas_assert (i
.imm_operands
== 2
6108 && i
.tm
.opcode_modifier
.sae
6109 && operand_type_check (i
.types
[0], imm
));
6110 if (operand_type_check (i
.types
[1], imm
))
6112 else if (operand_type_check (i
.types
[4], imm
))
6126 /* RC/SAE operand could be between DEST and SRC. That happens
6127 when one operand is GPR and the other one is XMM/YMM/ZMM
6129 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6132 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6134 /* For instructions with VexNDS, the register-only source
6135 operand must be 32/64bit integer, XMM, YMM or ZMM
6136 register. It is encoded in VEX prefix. We need to
6137 clear RegMem bit before calling operand_type_equal. */
6139 i386_operand_type op
;
6142 /* Check register-only source operand when two source
6143 operands are swapped. */
6144 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6145 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6153 op
= i
.tm
.operand_types
[vvvv
];
6154 op
.bitfield
.regmem
= 0;
6155 if ((dest
+ 1) >= i
.operands
6156 || (op
.bitfield
.reg32
!= 1
6157 && !op
.bitfield
.reg64
!= 1
6158 && !operand_type_equal (&op
, ®xmm
)
6159 && !operand_type_equal (&op
, ®ymm
)
6160 && !operand_type_equal (&op
, ®zmm
)
6161 && !operand_type_equal (&op
, ®mask
)))
6163 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6169 /* One of the register operands will be encoded in the i.tm.reg
6170 field, the other in the combined i.tm.mode and i.tm.regmem
6171 fields. If no form of this instruction supports a memory
6172 destination operand, then we assume the source operand may
6173 sometimes be a memory operand and so we need to store the
6174 destination in the i.rm.reg field. */
6175 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6176 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6178 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6179 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6180 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6182 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6184 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6186 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6191 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6192 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6193 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6195 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6197 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6199 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6202 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6204 if (!i
.types
[0].bitfield
.control
6205 && !i
.types
[1].bitfield
.control
)
6207 i
.rex
&= ~(REX_R
| REX_B
);
6208 add_prefix (LOCK_PREFIX_OPCODE
);
6212 { /* If it's not 2 reg operands... */
6217 unsigned int fake_zero_displacement
= 0;
6220 for (op
= 0; op
< i
.operands
; op
++)
6221 if (operand_type_check (i
.types
[op
], anymem
))
6223 gas_assert (op
< i
.operands
);
6225 if (i
.tm
.opcode_modifier
.vecsib
)
6227 if (i
.index_reg
->reg_num
== RegEiz
6228 || i
.index_reg
->reg_num
== RegRiz
)
6231 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6234 i
.sib
.base
= NO_BASE_REGISTER
;
6235 i
.sib
.scale
= i
.log2_scale_factor
;
6236 /* No Vec_Disp8 if there is no base. */
6237 i
.types
[op
].bitfield
.vec_disp8
= 0;
6238 i
.types
[op
].bitfield
.disp8
= 0;
6239 i
.types
[op
].bitfield
.disp16
= 0;
6240 i
.types
[op
].bitfield
.disp64
= 0;
6241 if (flag_code
!= CODE_64BIT
)
6243 /* Must be 32 bit */
6244 i
.types
[op
].bitfield
.disp32
= 1;
6245 i
.types
[op
].bitfield
.disp32s
= 0;
6249 i
.types
[op
].bitfield
.disp32
= 0;
6250 i
.types
[op
].bitfield
.disp32s
= 1;
6253 i
.sib
.index
= i
.index_reg
->reg_num
;
6254 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6256 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6262 if (i
.base_reg
== 0)
6265 if (!i
.disp_operands
)
6267 fake_zero_displacement
= 1;
6268 /* Instructions with VSIB byte need 32bit displacement
6269 if there is no base register. */
6270 if (i
.tm
.opcode_modifier
.vecsib
)
6271 i
.types
[op
].bitfield
.disp32
= 1;
6273 if (i
.index_reg
== 0)
6275 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6276 /* Operand is just <disp> */
6277 if (flag_code
== CODE_64BIT
)
6279 /* 64bit mode overwrites the 32bit absolute
6280 addressing by RIP relative addressing and
6281 absolute addressing is encoded by one of the
6282 redundant SIB forms. */
6283 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6284 i
.sib
.base
= NO_BASE_REGISTER
;
6285 i
.sib
.index
= NO_INDEX_REGISTER
;
6286 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6287 ? disp32s
: disp32
);
6289 else if ((flag_code
== CODE_16BIT
)
6290 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6292 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6293 i
.types
[op
] = disp16
;
6297 i
.rm
.regmem
= NO_BASE_REGISTER
;
6298 i
.types
[op
] = disp32
;
6301 else if (!i
.tm
.opcode_modifier
.vecsib
)
6303 /* !i.base_reg && i.index_reg */
6304 if (i
.index_reg
->reg_num
== RegEiz
6305 || i
.index_reg
->reg_num
== RegRiz
)
6306 i
.sib
.index
= NO_INDEX_REGISTER
;
6308 i
.sib
.index
= i
.index_reg
->reg_num
;
6309 i
.sib
.base
= NO_BASE_REGISTER
;
6310 i
.sib
.scale
= i
.log2_scale_factor
;
6311 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6312 /* No Vec_Disp8 if there is no base. */
6313 i
.types
[op
].bitfield
.vec_disp8
= 0;
6314 i
.types
[op
].bitfield
.disp8
= 0;
6315 i
.types
[op
].bitfield
.disp16
= 0;
6316 i
.types
[op
].bitfield
.disp64
= 0;
6317 if (flag_code
!= CODE_64BIT
)
6319 /* Must be 32 bit */
6320 i
.types
[op
].bitfield
.disp32
= 1;
6321 i
.types
[op
].bitfield
.disp32s
= 0;
6325 i
.types
[op
].bitfield
.disp32
= 0;
6326 i
.types
[op
].bitfield
.disp32s
= 1;
6328 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6332 /* RIP addressing for 64bit mode. */
6333 else if (i
.base_reg
->reg_num
== RegRip
||
6334 i
.base_reg
->reg_num
== RegEip
)
6336 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6337 i
.rm
.regmem
= NO_BASE_REGISTER
;
6338 i
.types
[op
].bitfield
.disp8
= 0;
6339 i
.types
[op
].bitfield
.disp16
= 0;
6340 i
.types
[op
].bitfield
.disp32
= 0;
6341 i
.types
[op
].bitfield
.disp32s
= 1;
6342 i
.types
[op
].bitfield
.disp64
= 0;
6343 i
.types
[op
].bitfield
.vec_disp8
= 0;
6344 i
.flags
[op
] |= Operand_PCrel
;
6345 if (! i
.disp_operands
)
6346 fake_zero_displacement
= 1;
6348 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6350 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6351 switch (i
.base_reg
->reg_num
)
6354 if (i
.index_reg
== 0)
6356 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6357 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6361 if (i
.index_reg
== 0)
6364 if (operand_type_check (i
.types
[op
], disp
) == 0)
6366 /* fake (%bp) into 0(%bp) */
6367 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6368 i
.types
[op
].bitfield
.vec_disp8
= 1;
6370 i
.types
[op
].bitfield
.disp8
= 1;
6371 fake_zero_displacement
= 1;
6374 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6375 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6377 default: /* (%si) -> 4 or (%di) -> 5 */
6378 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6380 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6382 else /* i.base_reg and 32/64 bit mode */
6384 if (flag_code
== CODE_64BIT
6385 && operand_type_check (i
.types
[op
], disp
))
6387 i386_operand_type temp
;
6388 operand_type_set (&temp
, 0);
6389 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6390 temp
.bitfield
.vec_disp8
6391 = i
.types
[op
].bitfield
.vec_disp8
;
6393 if (i
.prefix
[ADDR_PREFIX
] == 0)
6394 i
.types
[op
].bitfield
.disp32s
= 1;
6396 i
.types
[op
].bitfield
.disp32
= 1;
6399 if (!i
.tm
.opcode_modifier
.vecsib
)
6400 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6401 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6403 i
.sib
.base
= i
.base_reg
->reg_num
;
6404 /* x86-64 ignores REX prefix bit here to avoid decoder
6406 if (!(i
.base_reg
->reg_flags
& RegRex
)
6407 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6408 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6410 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6412 fake_zero_displacement
= 1;
6413 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6414 i
.types
[op
].bitfield
.vec_disp8
= 1;
6416 i
.types
[op
].bitfield
.disp8
= 1;
6418 i
.sib
.scale
= i
.log2_scale_factor
;
6419 if (i
.index_reg
== 0)
6421 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6422 /* <disp>(%esp) becomes two byte modrm with no index
6423 register. We've already stored the code for esp
6424 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6425 Any base register besides %esp will not use the
6426 extra modrm byte. */
6427 i
.sib
.index
= NO_INDEX_REGISTER
;
6429 else if (!i
.tm
.opcode_modifier
.vecsib
)
6431 if (i
.index_reg
->reg_num
== RegEiz
6432 || i
.index_reg
->reg_num
== RegRiz
)
6433 i
.sib
.index
= NO_INDEX_REGISTER
;
6435 i
.sib
.index
= i
.index_reg
->reg_num
;
6436 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6437 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6442 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6443 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6447 if (!fake_zero_displacement
6451 fake_zero_displacement
= 1;
6452 if (i
.disp_encoding
== disp_encoding_8bit
)
6453 i
.types
[op
].bitfield
.disp8
= 1;
6455 i
.types
[op
].bitfield
.disp32
= 1;
6457 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6461 if (fake_zero_displacement
)
6463 /* Fakes a zero displacement assuming that i.types[op]
6464 holds the correct displacement size. */
6467 gas_assert (i
.op
[op
].disps
== 0);
6468 exp
= &disp_expressions
[i
.disp_operands
++];
6469 i
.op
[op
].disps
= exp
;
6470 exp
->X_op
= O_constant
;
6471 exp
->X_add_number
= 0;
6472 exp
->X_add_symbol
= (symbolS
*) 0;
6473 exp
->X_op_symbol
= (symbolS
*) 0;
6481 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6483 if (operand_type_check (i
.types
[0], imm
))
6484 i
.vex
.register_specifier
= NULL
;
6487 /* VEX.vvvv encodes one of the sources when the first
6488 operand is not an immediate. */
6489 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6490 i
.vex
.register_specifier
= i
.op
[0].regs
;
6492 i
.vex
.register_specifier
= i
.op
[1].regs
;
6495 /* Destination is a XMM register encoded in the ModRM.reg
6497 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6498 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6501 /* ModRM.rm and VEX.B encodes the other source. */
6502 if (!i
.mem_operands
)
6506 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6507 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6509 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6511 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6515 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6517 i
.vex
.register_specifier
= i
.op
[2].regs
;
6518 if (!i
.mem_operands
)
6521 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6522 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6526 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6527 (if any) based on i.tm.extension_opcode. Again, we must be
6528 careful to make sure that segment/control/debug/test/MMX
6529 registers are coded into the i.rm.reg field. */
6530 else if (i
.reg_operands
)
6533 unsigned int vex_reg
= ~0;
6535 for (op
= 0; op
< i
.operands
; op
++)
6536 if (i
.types
[op
].bitfield
.reg8
6537 || i
.types
[op
].bitfield
.reg16
6538 || i
.types
[op
].bitfield
.reg32
6539 || i
.types
[op
].bitfield
.reg64
6540 || i
.types
[op
].bitfield
.regmmx
6541 || i
.types
[op
].bitfield
.regxmm
6542 || i
.types
[op
].bitfield
.regymm
6543 || i
.types
[op
].bitfield
.regbnd
6544 || i
.types
[op
].bitfield
.regzmm
6545 || i
.types
[op
].bitfield
.regmask
6546 || i
.types
[op
].bitfield
.sreg2
6547 || i
.types
[op
].bitfield
.sreg3
6548 || i
.types
[op
].bitfield
.control
6549 || i
.types
[op
].bitfield
.debug
6550 || i
.types
[op
].bitfield
.test
)
6555 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6557 /* For instructions with VexNDS, the register-only
6558 source operand is encoded in VEX prefix. */
6559 gas_assert (mem
!= (unsigned int) ~0);
6564 gas_assert (op
< i
.operands
);
6568 /* Check register-only source operand when two source
6569 operands are swapped. */
6570 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6571 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6575 gas_assert (mem
== (vex_reg
+ 1)
6576 && op
< i
.operands
);
6581 gas_assert (vex_reg
< i
.operands
);
6585 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6587 /* For instructions with VexNDD, the register destination
6588 is encoded in VEX prefix. */
6589 if (i
.mem_operands
== 0)
6591 /* There is no memory operand. */
6592 gas_assert ((op
+ 2) == i
.operands
);
6597 /* There are only 2 operands. */
6598 gas_assert (op
< 2 && i
.operands
== 2);
6603 gas_assert (op
< i
.operands
);
6605 if (vex_reg
!= (unsigned int) ~0)
6607 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6609 if (type
->bitfield
.reg32
!= 1
6610 && type
->bitfield
.reg64
!= 1
6611 && !operand_type_equal (type
, ®xmm
)
6612 && !operand_type_equal (type
, ®ymm
)
6613 && !operand_type_equal (type
, ®zmm
)
6614 && !operand_type_equal (type
, ®mask
))
6617 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6620 /* Don't set OP operand twice. */
6623 /* If there is an extension opcode to put here, the
6624 register number must be put into the regmem field. */
6625 if (i
.tm
.extension_opcode
!= None
)
6627 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6628 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6630 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6635 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6636 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6638 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6643 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6644 must set it to 3 to indicate this is a register operand
6645 in the regmem field. */
6646 if (!i
.mem_operands
)
6650 /* Fill in i.rm.reg field with extension opcode (if any). */
6651 if (i
.tm
.extension_opcode
!= None
)
6652 i
.rm
.reg
= i
.tm
.extension_opcode
;
6658 output_branch (void)
6664 relax_substateT subtype
;
6668 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6669 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6672 if (i
.prefix
[DATA_PREFIX
] != 0)
6678 /* Pentium4 branch hints. */
6679 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6680 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6685 if (i
.prefix
[REX_PREFIX
] != 0)
6691 /* BND prefixed jump. */
6692 if (i
.prefix
[BND_PREFIX
] != 0)
6694 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6698 if (i
.prefixes
!= 0 && !intel_syntax
)
6699 as_warn (_("skipping prefixes on this instruction"));
6701 /* It's always a symbol; End frag & setup for relax.
6702 Make sure there is enough room in this frag for the largest
6703 instruction we may generate in md_convert_frag. This is 2
6704 bytes for the opcode and room for the prefix and largest
6706 frag_grow (prefix
+ 2 + 4);
6707 /* Prefix and 1 opcode byte go in fr_fix. */
6708 p
= frag_more (prefix
+ 1);
6709 if (i
.prefix
[DATA_PREFIX
] != 0)
6710 *p
++ = DATA_PREFIX_OPCODE
;
6711 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6712 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6713 *p
++ = i
.prefix
[SEG_PREFIX
];
6714 if (i
.prefix
[REX_PREFIX
] != 0)
6715 *p
++ = i
.prefix
[REX_PREFIX
];
6716 *p
= i
.tm
.base_opcode
;
6718 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6719 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6720 else if (cpu_arch_flags
.bitfield
.cpui386
)
6721 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6723 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6726 sym
= i
.op
[0].disps
->X_add_symbol
;
6727 off
= i
.op
[0].disps
->X_add_number
;
6729 if (i
.op
[0].disps
->X_op
!= O_constant
6730 && i
.op
[0].disps
->X_op
!= O_symbol
)
6732 /* Handle complex expressions. */
6733 sym
= make_expr_symbol (i
.op
[0].disps
);
6737 /* 1 possible extra opcode + 4 byte displacement go in var part.
6738 Pass reloc in fr_var. */
6739 frag_var (rs_machine_dependent
, 5,
6741 || i
.reloc
[0] != NO_RELOC
6742 || (i
.bnd_prefix
== NULL
&& !add_bnd_prefix
))
6744 : BFD_RELOC_X86_64_PC32_BND
),
6745 subtype
, sym
, off
, p
);
6755 if (i
.tm
.opcode_modifier
.jumpbyte
)
6757 /* This is a loop or jecxz type instruction. */
6759 if (i
.prefix
[ADDR_PREFIX
] != 0)
6761 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6764 /* Pentium4 branch hints. */
6765 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6766 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6768 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6777 if (flag_code
== CODE_16BIT
)
6780 if (i
.prefix
[DATA_PREFIX
] != 0)
6782 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6792 if (i
.prefix
[REX_PREFIX
] != 0)
6794 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6798 /* BND prefixed jump. */
6799 if (i
.prefix
[BND_PREFIX
] != 0)
6801 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6805 if (i
.prefixes
!= 0 && !intel_syntax
)
6806 as_warn (_("skipping prefixes on this instruction"));
6808 p
= frag_more (i
.tm
.opcode_length
+ size
);
6809 switch (i
.tm
.opcode_length
)
6812 *p
++ = i
.tm
.base_opcode
>> 8;
6814 *p
++ = i
.tm
.base_opcode
;
6820 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6821 i
.op
[0].disps
, 1, reloc (size
, 1, 1,
6822 (i
.bnd_prefix
!= NULL
6826 /* All jumps handled here are signed, but don't use a signed limit
6827 check for 32 and 16 bit jumps as we want to allow wrap around at
6828 4G and 64k respectively. */
6830 fixP
->fx_signed
= 1;
6834 output_interseg_jump (void)
6842 if (flag_code
== CODE_16BIT
)
6846 if (i
.prefix
[DATA_PREFIX
] != 0)
6852 if (i
.prefix
[REX_PREFIX
] != 0)
6862 if (i
.prefixes
!= 0 && !intel_syntax
)
6863 as_warn (_("skipping prefixes on this instruction"));
6865 /* 1 opcode; 2 segment; offset */
6866 p
= frag_more (prefix
+ 1 + 2 + size
);
6868 if (i
.prefix
[DATA_PREFIX
] != 0)
6869 *p
++ = DATA_PREFIX_OPCODE
;
6871 if (i
.prefix
[REX_PREFIX
] != 0)
6872 *p
++ = i
.prefix
[REX_PREFIX
];
6874 *p
++ = i
.tm
.base_opcode
;
6875 if (i
.op
[1].imms
->X_op
== O_constant
)
6877 offsetT n
= i
.op
[1].imms
->X_add_number
;
6880 && !fits_in_unsigned_word (n
)
6881 && !fits_in_signed_word (n
))
6883 as_bad (_("16-bit jump out of range"));
6886 md_number_to_chars (p
, n
, size
);
6889 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6890 i
.op
[1].imms
, 0, reloc (size
, 0, 0, 0, i
.reloc
[1]));
6891 if (i
.op
[0].imms
->X_op
!= O_constant
)
6892 as_bad (_("can't handle non absolute segment in `%s'"),
6894 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6900 fragS
*insn_start_frag
;
6901 offsetT insn_start_off
;
6903 /* Tie dwarf2 debug info to the address at the start of the insn.
6904 We can't do this after the insn has been output as the current
6905 frag may have been closed off. eg. by frag_var. */
6906 dwarf2_emit_insn (0);
6908 insn_start_frag
= frag_now
;
6909 insn_start_off
= frag_now_fix ();
6912 if (i
.tm
.opcode_modifier
.jump
)
6914 else if (i
.tm
.opcode_modifier
.jumpbyte
6915 || i
.tm
.opcode_modifier
.jumpdword
)
6917 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6918 output_interseg_jump ();
6921 /* Output normal instructions here. */
6925 unsigned int prefix
;
6927 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6928 don't need the explicit prefix. */
6929 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6931 switch (i
.tm
.opcode_length
)
6934 if (i
.tm
.base_opcode
& 0xff000000)
6936 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6941 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6943 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6944 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6947 if (prefix
!= REPE_PREFIX_OPCODE
6948 || (i
.prefix
[REP_PREFIX
]
6949 != REPE_PREFIX_OPCODE
))
6950 add_prefix (prefix
);
6953 add_prefix (prefix
);
6962 /* The prefix bytes. */
6963 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6965 FRAG_APPEND_1_CHAR (*q
);
6969 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
6974 /* REX byte is encoded in VEX prefix. */
6978 FRAG_APPEND_1_CHAR (*q
);
6981 /* There should be no other prefixes for instructions
6986 /* For EVEX instructions i.vrex should become 0 after
6987 build_evex_prefix. For VEX instructions upper 16 registers
6988 aren't available, so VREX should be 0. */
6991 /* Now the VEX prefix. */
6992 p
= frag_more (i
.vex
.length
);
6993 for (j
= 0; j
< i
.vex
.length
; j
++)
6994 p
[j
] = i
.vex
.bytes
[j
];
6997 /* Now the opcode; be careful about word order here! */
6998 if (i
.tm
.opcode_length
== 1)
7000 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7004 switch (i
.tm
.opcode_length
)
7008 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7009 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7013 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7023 /* Put out high byte first: can't use md_number_to_chars! */
7024 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7025 *p
= i
.tm
.base_opcode
& 0xff;
7028 /* Now the modrm byte and sib byte (if present). */
7029 if (i
.tm
.opcode_modifier
.modrm
)
7031 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7034 /* If i.rm.regmem == ESP (4)
7035 && i.rm.mode != (Register mode)
7037 ==> need second modrm byte. */
7038 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7040 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7041 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7043 | i
.sib
.scale
<< 6));
7046 if (i
.disp_operands
)
7047 output_disp (insn_start_frag
, insn_start_off
);
7050 output_imm (insn_start_frag
, insn_start_off
);
7056 pi ("" /*line*/, &i
);
7058 #endif /* DEBUG386 */
7061 /* Return the size of the displacement operand N. */
7064 disp_size (unsigned int n
)
7068 /* Vec_Disp8 has to be 8bit. */
7069 if (i
.types
[n
].bitfield
.vec_disp8
)
7071 else if (i
.types
[n
].bitfield
.disp64
)
7073 else if (i
.types
[n
].bitfield
.disp8
)
7075 else if (i
.types
[n
].bitfield
.disp16
)
7080 /* Return the size of the immediate operand N. */
7083 imm_size (unsigned int n
)
7086 if (i
.types
[n
].bitfield
.imm64
)
7088 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7090 else if (i
.types
[n
].bitfield
.imm16
)
7096 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7101 for (n
= 0; n
< i
.operands
; n
++)
7103 if (i
.types
[n
].bitfield
.vec_disp8
7104 || operand_type_check (i
.types
[n
], disp
))
7106 if (i
.op
[n
].disps
->X_op
== O_constant
)
7108 int size
= disp_size (n
);
7109 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7111 if (i
.types
[n
].bitfield
.vec_disp8
)
7113 val
= offset_in_range (val
, size
);
7114 p
= frag_more (size
);
7115 md_number_to_chars (p
, val
, size
);
7119 enum bfd_reloc_code_real reloc_type
;
7120 int size
= disp_size (n
);
7121 int sign
= i
.types
[n
].bitfield
.disp32s
;
7122 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7124 /* We can't have 8 bit displacement here. */
7125 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7127 /* The PC relative address is computed relative
7128 to the instruction boundary, so in case immediate
7129 fields follows, we need to adjust the value. */
7130 if (pcrel
&& i
.imm_operands
)
7135 for (n1
= 0; n1
< i
.operands
; n1
++)
7136 if (operand_type_check (i
.types
[n1
], imm
))
7138 /* Only one immediate is allowed for PC
7139 relative address. */
7140 gas_assert (sz
== 0);
7142 i
.op
[n
].disps
->X_add_number
-= sz
;
7144 /* We should find the immediate. */
7145 gas_assert (sz
!= 0);
7148 p
= frag_more (size
);
7149 reloc_type
= reloc (size
, pcrel
, sign
,
7150 (i
.bnd_prefix
!= NULL
7154 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7155 && (((reloc_type
== BFD_RELOC_32
7156 || reloc_type
== BFD_RELOC_X86_64_32S
7157 || (reloc_type
== BFD_RELOC_64
7159 && (i
.op
[n
].disps
->X_op
== O_symbol
7160 || (i
.op
[n
].disps
->X_op
== O_add
7161 && ((symbol_get_value_expression
7162 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7164 || reloc_type
== BFD_RELOC_32_PCREL
))
7168 if (insn_start_frag
== frag_now
)
7169 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7174 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7175 for (fr
= insn_start_frag
->fr_next
;
7176 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7178 add
+= p
- frag_now
->fr_literal
;
7183 reloc_type
= BFD_RELOC_386_GOTPC
;
7184 i
.op
[n
].imms
->X_add_number
+= add
;
7186 else if (reloc_type
== BFD_RELOC_64
)
7187 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7189 /* Don't do the adjustment for x86-64, as there
7190 the pcrel addressing is relative to the _next_
7191 insn, and that is taken care of in other code. */
7192 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7194 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7195 i
.op
[n
].disps
, pcrel
, reloc_type
);
7202 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7207 for (n
= 0; n
< i
.operands
; n
++)
7209 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7210 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7213 if (operand_type_check (i
.types
[n
], imm
))
7215 if (i
.op
[n
].imms
->X_op
== O_constant
)
7217 int size
= imm_size (n
);
7220 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7222 p
= frag_more (size
);
7223 md_number_to_chars (p
, val
, size
);
7227 /* Not absolute_section.
7228 Need a 32-bit fixup (don't support 8bit
7229 non-absolute imms). Try to support other
7231 enum bfd_reloc_code_real reloc_type
;
7232 int size
= imm_size (n
);
7235 if (i
.types
[n
].bitfield
.imm32s
7236 && (i
.suffix
== QWORD_MNEM_SUFFIX
7237 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7242 p
= frag_more (size
);
7243 reloc_type
= reloc (size
, 0, sign
, 0, i
.reloc
[n
]);
7245 /* This is tough to explain. We end up with this one if we
7246 * have operands that look like
7247 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7248 * obtain the absolute address of the GOT, and it is strongly
7249 * preferable from a performance point of view to avoid using
7250 * a runtime relocation for this. The actual sequence of
7251 * instructions often look something like:
7256 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7258 * The call and pop essentially return the absolute address
7259 * of the label .L66 and store it in %ebx. The linker itself
7260 * will ultimately change the first operand of the addl so
7261 * that %ebx points to the GOT, but to keep things simple, the
7262 * .o file must have this operand set so that it generates not
7263 * the absolute address of .L66, but the absolute address of
7264 * itself. This allows the linker itself simply treat a GOTPC
7265 * relocation as asking for a pcrel offset to the GOT to be
7266 * added in, and the addend of the relocation is stored in the
7267 * operand field for the instruction itself.
7269 * Our job here is to fix the operand so that it would add
7270 * the correct offset so that %ebx would point to itself. The
7271 * thing that is tricky is that .-.L66 will point to the
7272 * beginning of the instruction, so we need to further modify
7273 * the operand so that it will point to itself. There are
7274 * other cases where you have something like:
7276 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7278 * and here no correction would be required. Internally in
7279 * the assembler we treat operands of this form as not being
7280 * pcrel since the '.' is explicitly mentioned, and I wonder
7281 * whether it would simplify matters to do it this way. Who
7282 * knows. In earlier versions of the PIC patches, the
7283 * pcrel_adjust field was used to store the correction, but
7284 * since the expression is not pcrel, I felt it would be
7285 * confusing to do it this way. */
7287 if ((reloc_type
== BFD_RELOC_32
7288 || reloc_type
== BFD_RELOC_X86_64_32S
7289 || reloc_type
== BFD_RELOC_64
)
7291 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7292 && (i
.op
[n
].imms
->X_op
== O_symbol
7293 || (i
.op
[n
].imms
->X_op
== O_add
7294 && ((symbol_get_value_expression
7295 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7300 if (insn_start_frag
== frag_now
)
7301 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7306 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7307 for (fr
= insn_start_frag
->fr_next
;
7308 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7310 add
+= p
- frag_now
->fr_literal
;
7314 reloc_type
= BFD_RELOC_386_GOTPC
;
7316 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7318 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7319 i
.op
[n
].imms
->X_add_number
+= add
;
7321 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7322 i
.op
[n
].imms
, 0, reloc_type
);
7328 /* x86_cons_fix_new is called via the expression parsing code when a
7329 reloc is needed. We use this hook to get the correct .got reloc. */
7330 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
7331 static int cons_sign
= -1;
7334 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7337 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, 0, got_reloc
);
7339 got_reloc
= NO_RELOC
;
7342 if (exp
->X_op
== O_secrel
)
7344 exp
->X_op
= O_symbol
;
7345 r
= BFD_RELOC_32_SECREL
;
7349 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7352 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7353 purpose of the `.dc.a' internal pseudo-op. */
7356 x86_address_bytes (void)
7358 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7360 return stdoutput
->arch_info
->bits_per_address
/ 8;
7363 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7365 # define lex_got(reloc, adjust, types, bnd_prefix) NULL
7367 /* Parse operands of the form
7368 <symbol>@GOTOFF+<nnn>
7369 and similar .plt or .got references.
7371 If we find one, set up the correct relocation in RELOC and copy the
7372 input string, minus the `@GOTOFF' into a malloc'd buffer for
7373 parsing by the calling routine. Return this buffer, and if ADJUST
7374 is non-null set it to the length of the string we removed from the
7375 input line. Otherwise return NULL. */
7377 lex_got (enum bfd_reloc_code_real
*rel
,
7379 i386_operand_type
*types
,
7382 /* Some of the relocations depend on the size of what field is to
7383 be relocated. But in our callers i386_immediate and i386_displacement
7384 we don't yet know the operand size (this will be set by insn
7385 matching). Hence we record the word32 relocation here,
7386 and adjust the reloc according to the real size in reloc(). */
7387 static const struct {
7390 const enum bfd_reloc_code_real rel
[2];
7391 const i386_operand_type types64
;
7393 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7394 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7396 OPERAND_TYPE_IMM32_64
},
7398 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7399 BFD_RELOC_X86_64_PLTOFF64
},
7400 OPERAND_TYPE_IMM64
},
7401 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7402 BFD_RELOC_X86_64_PLT32
},
7403 OPERAND_TYPE_IMM32_32S_DISP32
},
7404 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7405 BFD_RELOC_X86_64_GOTPLT64
},
7406 OPERAND_TYPE_IMM64_DISP64
},
7407 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7408 BFD_RELOC_X86_64_GOTOFF64
},
7409 OPERAND_TYPE_IMM64_DISP64
},
7410 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7411 BFD_RELOC_X86_64_GOTPCREL
},
7412 OPERAND_TYPE_IMM32_32S_DISP32
},
7413 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7414 BFD_RELOC_X86_64_TLSGD
},
7415 OPERAND_TYPE_IMM32_32S_DISP32
},
7416 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7417 _dummy_first_bfd_reloc_code_real
},
7418 OPERAND_TYPE_NONE
},
7419 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7420 BFD_RELOC_X86_64_TLSLD
},
7421 OPERAND_TYPE_IMM32_32S_DISP32
},
7422 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7423 BFD_RELOC_X86_64_GOTTPOFF
},
7424 OPERAND_TYPE_IMM32_32S_DISP32
},
7425 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7426 BFD_RELOC_X86_64_TPOFF32
},
7427 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7428 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7429 _dummy_first_bfd_reloc_code_real
},
7430 OPERAND_TYPE_NONE
},
7431 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7432 BFD_RELOC_X86_64_DTPOFF32
},
7433 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7434 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7435 _dummy_first_bfd_reloc_code_real
},
7436 OPERAND_TYPE_NONE
},
7437 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7438 _dummy_first_bfd_reloc_code_real
},
7439 OPERAND_TYPE_NONE
},
7440 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7441 BFD_RELOC_X86_64_GOT32
},
7442 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7443 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7444 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7445 OPERAND_TYPE_IMM32_32S_DISP32
},
7446 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7447 BFD_RELOC_X86_64_TLSDESC_CALL
},
7448 OPERAND_TYPE_IMM32_32S_DISP32
},
7453 #if defined (OBJ_MAYBE_ELF)
7458 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7459 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7462 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7464 int len
= gotrel
[j
].len
;
7465 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7467 if (gotrel
[j
].rel
[object_64bit
] != 0)
7470 char *tmpbuf
, *past_reloc
;
7472 *rel
= gotrel
[j
].rel
[object_64bit
];
7476 if (flag_code
!= CODE_64BIT
)
7478 types
->bitfield
.imm32
= 1;
7479 types
->bitfield
.disp32
= 1;
7482 *types
= gotrel
[j
].types64
;
7485 if (j
!= 0 && GOT_symbol
== NULL
)
7486 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7488 /* The length of the first part of our input line. */
7489 first
= cp
- input_line_pointer
;
7491 /* The second part goes from after the reloc token until
7492 (and including) an end_of_line char or comma. */
7493 past_reloc
= cp
+ 1 + len
;
7495 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7497 second
= cp
+ 1 - past_reloc
;
7499 /* Allocate and copy string. The trailing NUL shouldn't
7500 be necessary, but be safe. */
7501 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7502 memcpy (tmpbuf
, input_line_pointer
, first
);
7503 if (second
!= 0 && *past_reloc
!= ' ')
7504 /* Replace the relocation token with ' ', so that
7505 errors like foo@GOTOFF1 will be detected. */
7506 tmpbuf
[first
++] = ' ';
7508 /* Increment length by 1 if the relocation token is
7513 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7514 tmpbuf
[first
+ second
] = '\0';
7515 if (bnd_prefix
&& *rel
== BFD_RELOC_X86_64_PLT32
)
7516 *rel
= BFD_RELOC_X86_64_PLT32_BND
;
7520 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7521 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7526 /* Might be a symbol version string. Don't as_bad here. */
7535 /* Parse operands of the form
7536 <symbol>@SECREL32+<nnn>
7538 If we find one, set up the correct relocation in RELOC and copy the
7539 input string, minus the `@SECREL32' into a malloc'd buffer for
7540 parsing by the calling routine. Return this buffer, and if ADJUST
7541 is non-null set it to the length of the string we removed from the
7542 input line. Otherwise return NULL.
7544 This function is copied from the ELF version above adjusted for PE targets. */
7547 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7548 int *adjust ATTRIBUTE_UNUSED
,
7549 i386_operand_type
*types
,
7550 int bnd_prefix ATTRIBUTE_UNUSED
)
7556 const enum bfd_reloc_code_real rel
[2];
7557 const i386_operand_type types64
;
7561 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7562 BFD_RELOC_32_SECREL
},
7563 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7569 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7570 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7573 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7575 int len
= gotrel
[j
].len
;
7577 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7579 if (gotrel
[j
].rel
[object_64bit
] != 0)
7582 char *tmpbuf
, *past_reloc
;
7584 *rel
= gotrel
[j
].rel
[object_64bit
];
7590 if (flag_code
!= CODE_64BIT
)
7592 types
->bitfield
.imm32
= 1;
7593 types
->bitfield
.disp32
= 1;
7596 *types
= gotrel
[j
].types64
;
7599 /* The length of the first part of our input line. */
7600 first
= cp
- input_line_pointer
;
7602 /* The second part goes from after the reloc token until
7603 (and including) an end_of_line char or comma. */
7604 past_reloc
= cp
+ 1 + len
;
7606 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7608 second
= cp
+ 1 - past_reloc
;
7610 /* Allocate and copy string. The trailing NUL shouldn't
7611 be necessary, but be safe. */
7612 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7613 memcpy (tmpbuf
, input_line_pointer
, first
);
7614 if (second
!= 0 && *past_reloc
!= ' ')
7615 /* Replace the relocation token with ' ', so that
7616 errors like foo@SECLREL321 will be detected. */
7617 tmpbuf
[first
++] = ' ';
7618 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7619 tmpbuf
[first
+ second
] = '\0';
7623 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7624 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7629 /* Might be a symbol version string. Don't as_bad here. */
7636 x86_cons (expressionS
*exp
, int size
)
7638 intel_syntax
= -intel_syntax
;
7641 if (size
== 4 || (object_64bit
&& size
== 8))
7643 /* Handle @GOTOFF and the like in an expression. */
7645 char *gotfree_input_line
;
7648 save
= input_line_pointer
;
7649 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
, 0);
7650 if (gotfree_input_line
)
7651 input_line_pointer
= gotfree_input_line
;
7655 if (gotfree_input_line
)
7657 /* expression () has merrily parsed up to the end of line,
7658 or a comma - in the wrong buffer. Transfer how far
7659 input_line_pointer has moved to the right buffer. */
7660 input_line_pointer
= (save
7661 + (input_line_pointer
- gotfree_input_line
)
7663 free (gotfree_input_line
);
7664 if (exp
->X_op
== O_constant
7665 || exp
->X_op
== O_absent
7666 || exp
->X_op
== O_illegal
7667 || exp
->X_op
== O_register
7668 || exp
->X_op
== O_big
)
7670 char c
= *input_line_pointer
;
7671 *input_line_pointer
= 0;
7672 as_bad (_("missing or invalid expression `%s'"), save
);
7673 *input_line_pointer
= c
;
7680 intel_syntax
= -intel_syntax
;
7683 i386_intel_simplify (exp
);
7687 signed_cons (int size
)
7689 if (flag_code
== CODE_64BIT
)
7697 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7704 if (exp
.X_op
== O_symbol
)
7705 exp
.X_op
= O_secrel
;
7707 emit_expr (&exp
, 4);
7709 while (*input_line_pointer
++ == ',');
7711 input_line_pointer
--;
7712 demand_empty_rest_of_line ();
7716 /* Handle Vector operations. */
7719 check_VecOperations (char *op_string
, char *op_end
)
7721 const reg_entry
*mask
;
7726 && (op_end
== NULL
|| op_string
< op_end
))
7729 if (*op_string
== '{')
7733 /* Check broadcasts. */
7734 if (strncmp (op_string
, "1to", 3) == 0)
7739 goto duplicated_vec_op
;
7742 if (*op_string
== '8')
7743 bcst_type
= BROADCAST_1TO8
;
7744 else if (*op_string
== '1'
7745 && *(op_string
+1) == '6')
7747 bcst_type
= BROADCAST_1TO16
;
7752 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7757 broadcast_op
.type
= bcst_type
;
7758 broadcast_op
.operand
= this_operand
;
7759 i
.broadcast
= &broadcast_op
;
7761 /* Check masking operation. */
7762 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7764 /* k0 can't be used for write mask. */
7765 if (mask
->reg_num
== 0)
7767 as_bad (_("`%s' can't be used for write mask"),
7774 mask_op
.mask
= mask
;
7775 mask_op
.zeroing
= 0;
7776 mask_op
.operand
= this_operand
;
7782 goto duplicated_vec_op
;
7784 i
.mask
->mask
= mask
;
7786 /* Only "{z}" is allowed here. No need to check
7787 zeroing mask explicitly. */
7788 if (i
.mask
->operand
!= this_operand
)
7790 as_bad (_("invalid write mask `%s'"), saved
);
7797 /* Check zeroing-flag for masking operation. */
7798 else if (*op_string
== 'z')
7802 mask_op
.mask
= NULL
;
7803 mask_op
.zeroing
= 1;
7804 mask_op
.operand
= this_operand
;
7809 if (i
.mask
->zeroing
)
7812 as_bad (_("duplicated `%s'"), saved
);
7816 i
.mask
->zeroing
= 1;
7818 /* Only "{%k}" is allowed here. No need to check mask
7819 register explicitly. */
7820 if (i
.mask
->operand
!= this_operand
)
7822 as_bad (_("invalid zeroing-masking `%s'"),
7831 goto unknown_vec_op
;
7833 if (*op_string
!= '}')
7835 as_bad (_("missing `}' in `%s'"), saved
);
7842 /* We don't know this one. */
7843 as_bad (_("unknown vector operation: `%s'"), saved
);
7851 i386_immediate (char *imm_start
)
7853 char *save_input_line_pointer
;
7854 char *gotfree_input_line
;
7857 i386_operand_type types
;
7859 operand_type_set (&types
, ~0);
7861 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7863 as_bad (_("at most %d immediate operands are allowed"),
7864 MAX_IMMEDIATE_OPERANDS
);
7868 exp
= &im_expressions
[i
.imm_operands
++];
7869 i
.op
[this_operand
].imms
= exp
;
7871 if (is_space_char (*imm_start
))
7874 save_input_line_pointer
= input_line_pointer
;
7875 input_line_pointer
= imm_start
;
7877 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
,
7878 (i
.bnd_prefix
!= NULL
7879 || add_bnd_prefix
));
7880 if (gotfree_input_line
)
7881 input_line_pointer
= gotfree_input_line
;
7883 exp_seg
= expression (exp
);
7887 /* Handle vector operations. */
7888 if (*input_line_pointer
== '{')
7890 input_line_pointer
= check_VecOperations (input_line_pointer
,
7892 if (input_line_pointer
== NULL
)
7896 if (*input_line_pointer
)
7897 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7899 input_line_pointer
= save_input_line_pointer
;
7900 if (gotfree_input_line
)
7902 free (gotfree_input_line
);
7904 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7905 exp
->X_op
= O_illegal
;
7908 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7912 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7913 i386_operand_type types
, const char *imm_start
)
7915 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7918 as_bad (_("missing or invalid immediate expression `%s'"),
7922 else if (exp
->X_op
== O_constant
)
7924 /* Size it properly later. */
7925 i
.types
[this_operand
].bitfield
.imm64
= 1;
7926 /* If not 64bit, sign extend val. */
7927 if (flag_code
!= CODE_64BIT
7928 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7930 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7932 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7933 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7934 && exp_seg
!= absolute_section
7935 && exp_seg
!= text_section
7936 && exp_seg
!= data_section
7937 && exp_seg
!= bss_section
7938 && exp_seg
!= undefined_section
7939 && !bfd_is_com_section (exp_seg
))
7941 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7945 else if (!intel_syntax
&& exp
->X_op
== O_register
)
7948 as_bad (_("illegal immediate register operand %s"), imm_start
);
7953 /* This is an address. The size of the address will be
7954 determined later, depending on destination register,
7955 suffix, or the default for the section. */
7956 i
.types
[this_operand
].bitfield
.imm8
= 1;
7957 i
.types
[this_operand
].bitfield
.imm16
= 1;
7958 i
.types
[this_operand
].bitfield
.imm32
= 1;
7959 i
.types
[this_operand
].bitfield
.imm32s
= 1;
7960 i
.types
[this_operand
].bitfield
.imm64
= 1;
7961 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7969 i386_scale (char *scale
)
7972 char *save
= input_line_pointer
;
7974 input_line_pointer
= scale
;
7975 val
= get_absolute_expression ();
7980 i
.log2_scale_factor
= 0;
7983 i
.log2_scale_factor
= 1;
7986 i
.log2_scale_factor
= 2;
7989 i
.log2_scale_factor
= 3;
7993 char sep
= *input_line_pointer
;
7995 *input_line_pointer
= '\0';
7996 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7998 *input_line_pointer
= sep
;
7999 input_line_pointer
= save
;
8003 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8005 as_warn (_("scale factor of %d without an index register"),
8006 1 << i
.log2_scale_factor
);
8007 i
.log2_scale_factor
= 0;
8009 scale
= input_line_pointer
;
8010 input_line_pointer
= save
;
8015 i386_displacement (char *disp_start
, char *disp_end
)
8019 char *save_input_line_pointer
;
8020 char *gotfree_input_line
;
8022 i386_operand_type bigdisp
, types
= anydisp
;
8025 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8027 as_bad (_("at most %d displacement operands are allowed"),
8028 MAX_MEMORY_OPERANDS
);
8032 operand_type_set (&bigdisp
, 0);
8033 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8034 || (!current_templates
->start
->opcode_modifier
.jump
8035 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8037 bigdisp
.bitfield
.disp32
= 1;
8038 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8039 if (flag_code
== CODE_64BIT
)
8043 bigdisp
.bitfield
.disp32s
= 1;
8044 bigdisp
.bitfield
.disp64
= 1;
8047 else if ((flag_code
== CODE_16BIT
) ^ override
)
8049 bigdisp
.bitfield
.disp32
= 0;
8050 bigdisp
.bitfield
.disp16
= 1;
8055 /* For PC-relative branches, the width of the displacement
8056 is dependent upon data size, not address size. */
8057 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8058 if (flag_code
== CODE_64BIT
)
8060 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8061 bigdisp
.bitfield
.disp16
= 1;
8064 bigdisp
.bitfield
.disp32
= 1;
8065 bigdisp
.bitfield
.disp32s
= 1;
8071 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8073 : LONG_MNEM_SUFFIX
));
8074 bigdisp
.bitfield
.disp32
= 1;
8075 if ((flag_code
== CODE_16BIT
) ^ override
)
8077 bigdisp
.bitfield
.disp32
= 0;
8078 bigdisp
.bitfield
.disp16
= 1;
8082 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8085 exp
= &disp_expressions
[i
.disp_operands
];
8086 i
.op
[this_operand
].disps
= exp
;
8088 save_input_line_pointer
= input_line_pointer
;
8089 input_line_pointer
= disp_start
;
8090 END_STRING_AND_SAVE (disp_end
);
8092 #ifndef GCC_ASM_O_HACK
8093 #define GCC_ASM_O_HACK 0
8096 END_STRING_AND_SAVE (disp_end
+ 1);
8097 if (i
.types
[this_operand
].bitfield
.baseIndex
8098 && displacement_string_end
[-1] == '+')
8100 /* This hack is to avoid a warning when using the "o"
8101 constraint within gcc asm statements.
8104 #define _set_tssldt_desc(n,addr,limit,type) \
8105 __asm__ __volatile__ ( \
8107 "movw %w1,2+%0\n\t" \
8109 "movb %b1,4+%0\n\t" \
8110 "movb %4,5+%0\n\t" \
8111 "movb $0,6+%0\n\t" \
8112 "movb %h1,7+%0\n\t" \
8114 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8116 This works great except that the output assembler ends
8117 up looking a bit weird if it turns out that there is
8118 no offset. You end up producing code that looks like:
8131 So here we provide the missing zero. */
8133 *displacement_string_end
= '0';
8136 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
,
8137 (i
.bnd_prefix
!= NULL
8138 || add_bnd_prefix
));
8139 if (gotfree_input_line
)
8140 input_line_pointer
= gotfree_input_line
;
8142 exp_seg
= expression (exp
);
8145 if (*input_line_pointer
)
8146 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8148 RESTORE_END_STRING (disp_end
+ 1);
8150 input_line_pointer
= save_input_line_pointer
;
8151 if (gotfree_input_line
)
8153 free (gotfree_input_line
);
8155 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8156 exp
->X_op
= O_illegal
;
8159 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8161 RESTORE_END_STRING (disp_end
);
8167 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8168 i386_operand_type types
, const char *disp_start
)
8170 i386_operand_type bigdisp
;
8173 /* We do this to make sure that the section symbol is in
8174 the symbol table. We will ultimately change the relocation
8175 to be relative to the beginning of the section. */
8176 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8177 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8178 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8180 if (exp
->X_op
!= O_symbol
)
8183 if (S_IS_LOCAL (exp
->X_add_symbol
)
8184 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8185 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8186 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8187 exp
->X_op
= O_subtract
;
8188 exp
->X_op_symbol
= GOT_symbol
;
8189 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8190 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8191 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8192 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8194 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8197 else if (exp
->X_op
== O_absent
8198 || exp
->X_op
== O_illegal
8199 || exp
->X_op
== O_big
)
8202 as_bad (_("missing or invalid displacement expression `%s'"),
8207 else if (flag_code
== CODE_64BIT
8208 && !i
.prefix
[ADDR_PREFIX
]
8209 && exp
->X_op
== O_constant
)
8211 /* Since displacement is signed extended to 64bit, don't allow
8212 disp32 and turn off disp32s if they are out of range. */
8213 i
.types
[this_operand
].bitfield
.disp32
= 0;
8214 if (!fits_in_signed_long (exp
->X_add_number
))
8216 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8217 if (i
.types
[this_operand
].bitfield
.baseindex
)
8219 as_bad (_("0x%lx out range of signed 32bit displacement"),
8220 (long) exp
->X_add_number
);
8226 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8227 else if (exp
->X_op
!= O_constant
8228 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8229 && exp_seg
!= absolute_section
8230 && exp_seg
!= text_section
8231 && exp_seg
!= data_section
8232 && exp_seg
!= bss_section
8233 && exp_seg
!= undefined_section
8234 && !bfd_is_com_section (exp_seg
))
8236 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8241 /* Check if this is a displacement only operand. */
8242 bigdisp
= i
.types
[this_operand
];
8243 bigdisp
.bitfield
.disp8
= 0;
8244 bigdisp
.bitfield
.disp16
= 0;
8245 bigdisp
.bitfield
.disp32
= 0;
8246 bigdisp
.bitfield
.disp32s
= 0;
8247 bigdisp
.bitfield
.disp64
= 0;
8248 if (operand_type_all_zero (&bigdisp
))
8249 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8255 /* Make sure the memory operand we've been dealt is valid.
8256 Return 1 on success, 0 on a failure. */
8259 i386_index_check (const char *operand_string
)
8261 const char *kind
= "base/index";
8262 enum flag_code addr_mode
;
8264 if (i
.prefix
[ADDR_PREFIX
])
8265 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8268 addr_mode
= flag_code
;
8270 #if INFER_ADDR_PREFIX
8271 if (i
.mem_operands
== 0)
8273 /* Infer address prefix from the first memory operand. */
8274 const reg_entry
*addr_reg
= i
.base_reg
;
8276 if (addr_reg
== NULL
)
8277 addr_reg
= i
.index_reg
;
8281 if (addr_reg
->reg_num
== RegEip
8282 || addr_reg
->reg_num
== RegEiz
8283 || addr_reg
->reg_type
.bitfield
.reg32
)
8284 addr_mode
= CODE_32BIT
;
8285 else if (flag_code
!= CODE_64BIT
8286 && addr_reg
->reg_type
.bitfield
.reg16
)
8287 addr_mode
= CODE_16BIT
;
8289 if (addr_mode
!= flag_code
)
8291 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8293 /* Change the size of any displacement too. At most one
8294 of Disp16 or Disp32 is set.
8295 FIXME. There doesn't seem to be any real need for
8296 separate Disp16 and Disp32 flags. The same goes for
8297 Imm16 and Imm32. Removing them would probably clean
8298 up the code quite a lot. */
8299 if (flag_code
!= CODE_64BIT
8300 && (i
.types
[this_operand
].bitfield
.disp16
8301 || i
.types
[this_operand
].bitfield
.disp32
))
8302 i
.types
[this_operand
]
8303 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8310 if (current_templates
->start
->opcode_modifier
.isstring
8311 && !current_templates
->start
->opcode_modifier
.immext
8312 && (current_templates
->end
[-1].opcode_modifier
.isstring
8315 /* Memory operands of string insns are special in that they only allow
8316 a single register (rDI, rSI, or rBX) as their memory address. */
8317 const reg_entry
*expected_reg
;
8318 static const char *di_si
[][2] =
8324 static const char *bx
[] = { "ebx", "bx", "rbx" };
8326 kind
= "string address";
8328 if (current_templates
->start
->opcode_modifier
.w
)
8330 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8332 if (!type
.bitfield
.baseindex
8333 || ((!i
.mem_operands
!= !intel_syntax
)
8334 && current_templates
->end
[-1].operand_types
[1]
8335 .bitfield
.baseindex
))
8336 type
= current_templates
->end
[-1].operand_types
[1];
8337 expected_reg
= hash_find (reg_hash
,
8338 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8342 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8344 if (i
.base_reg
!= expected_reg
8346 || operand_type_check (i
.types
[this_operand
], disp
))
8348 /* The second memory operand must have the same size as
8352 && !((addr_mode
== CODE_64BIT
8353 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8354 || (addr_mode
== CODE_32BIT
8355 ? i
.base_reg
->reg_type
.bitfield
.reg32
8356 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8359 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8361 intel_syntax
? '[' : '(',
8363 expected_reg
->reg_name
,
8364 intel_syntax
? ']' : ')');
8371 as_bad (_("`%s' is not a valid %s expression"),
8372 operand_string
, kind
);
8377 if (addr_mode
!= CODE_16BIT
)
8379 /* 32-bit/64-bit checks. */
8381 && (addr_mode
== CODE_64BIT
8382 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8383 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8385 || (i
.base_reg
->reg_num
8386 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8388 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8389 && !i
.index_reg
->reg_type
.bitfield
.regymm
8390 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8391 && ((addr_mode
== CODE_64BIT
8392 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8393 || i
.index_reg
->reg_num
== RegRiz
)
8394 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8395 || i
.index_reg
->reg_num
== RegEiz
))
8396 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8401 /* 16-bit checks. */
8403 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8404 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8406 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8407 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8409 && i
.base_reg
->reg_num
< 6
8410 && i
.index_reg
->reg_num
>= 6
8411 && i
.log2_scale_factor
== 0))))
8418 /* Handle vector immediates. */
8421 RC_SAE_immediate (const char *imm_start
)
8423 unsigned int match_found
, j
;
8424 const char *pstr
= imm_start
;
8432 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8434 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8438 rc_op
.type
= RC_NamesTable
[j
].type
;
8439 rc_op
.operand
= this_operand
;
8440 i
.rounding
= &rc_op
;
8444 as_bad (_("duplicated `%s'"), imm_start
);
8447 pstr
+= RC_NamesTable
[j
].len
;
8457 as_bad (_("Missing '}': '%s'"), imm_start
);
8460 /* RC/SAE immediate string should contain nothing more. */;
8463 as_bad (_("Junk after '}': '%s'"), imm_start
);
8467 exp
= &im_expressions
[i
.imm_operands
++];
8468 i
.op
[this_operand
].imms
= exp
;
8470 exp
->X_op
= O_constant
;
8471 exp
->X_add_number
= 0;
8472 exp
->X_add_symbol
= (symbolS
*) 0;
8473 exp
->X_op_symbol
= (symbolS
*) 0;
8475 i
.types
[this_operand
].bitfield
.imm8
= 1;
8479 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8483 i386_att_operand (char *operand_string
)
8487 char *op_string
= operand_string
;
8489 if (is_space_char (*op_string
))
8492 /* We check for an absolute prefix (differentiating,
8493 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8494 if (*op_string
== ABSOLUTE_PREFIX
)
8497 if (is_space_char (*op_string
))
8499 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8502 /* Check if operand is a register. */
8503 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8505 i386_operand_type temp
;
8507 /* Check for a segment override by searching for ':' after a
8508 segment register. */
8510 if (is_space_char (*op_string
))
8512 if (*op_string
== ':'
8513 && (r
->reg_type
.bitfield
.sreg2
8514 || r
->reg_type
.bitfield
.sreg3
))
8519 i
.seg
[i
.mem_operands
] = &es
;
8522 i
.seg
[i
.mem_operands
] = &cs
;
8525 i
.seg
[i
.mem_operands
] = &ss
;
8528 i
.seg
[i
.mem_operands
] = &ds
;
8531 i
.seg
[i
.mem_operands
] = &fs
;
8534 i
.seg
[i
.mem_operands
] = &gs
;
8538 /* Skip the ':' and whitespace. */
8540 if (is_space_char (*op_string
))
8543 if (!is_digit_char (*op_string
)
8544 && !is_identifier_char (*op_string
)
8545 && *op_string
!= '('
8546 && *op_string
!= ABSOLUTE_PREFIX
)
8548 as_bad (_("bad memory operand `%s'"), op_string
);
8551 /* Handle case of %es:*foo. */
8552 if (*op_string
== ABSOLUTE_PREFIX
)
8555 if (is_space_char (*op_string
))
8557 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8559 goto do_memory_reference
;
8562 /* Handle vector operations. */
8563 if (*op_string
== '{')
8565 op_string
= check_VecOperations (op_string
, NULL
);
8566 if (op_string
== NULL
)
8572 as_bad (_("junk `%s' after register"), op_string
);
8576 temp
.bitfield
.baseindex
= 0;
8577 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8579 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8580 i
.op
[this_operand
].regs
= r
;
8583 else if (*op_string
== REGISTER_PREFIX
)
8585 as_bad (_("bad register name `%s'"), op_string
);
8588 else if (*op_string
== IMMEDIATE_PREFIX
)
8591 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8593 as_bad (_("immediate operand illegal with absolute jump"));
8596 if (!i386_immediate (op_string
))
8599 else if (RC_SAE_immediate (operand_string
))
8601 /* If it is a RC or SAE immediate, do nothing. */
8604 else if (is_digit_char (*op_string
)
8605 || is_identifier_char (*op_string
)
8606 || *op_string
== '(')
8608 /* This is a memory reference of some sort. */
8611 /* Start and end of displacement string expression (if found). */
8612 char *displacement_string_start
;
8613 char *displacement_string_end
;
8616 do_memory_reference
:
8617 if ((i
.mem_operands
== 1
8618 && !current_templates
->start
->opcode_modifier
.isstring
)
8619 || i
.mem_operands
== 2)
8621 as_bad (_("too many memory references for `%s'"),
8622 current_templates
->start
->name
);
8626 /* Check for base index form. We detect the base index form by
8627 looking for an ')' at the end of the operand, searching
8628 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8630 base_string
= op_string
+ strlen (op_string
);
8632 /* Handle vector operations. */
8633 vop_start
= strchr (op_string
, '{');
8634 if (vop_start
&& vop_start
< base_string
)
8636 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8638 base_string
= vop_start
;
8642 if (is_space_char (*base_string
))
8645 /* If we only have a displacement, set-up for it to be parsed later. */
8646 displacement_string_start
= op_string
;
8647 displacement_string_end
= base_string
+ 1;
8649 if (*base_string
== ')')
8652 unsigned int parens_balanced
= 1;
8653 /* We've already checked that the number of left & right ()'s are
8654 equal, so this loop will not be infinite. */
8658 if (*base_string
== ')')
8660 if (*base_string
== '(')
8663 while (parens_balanced
);
8665 temp_string
= base_string
;
8667 /* Skip past '(' and whitespace. */
8669 if (is_space_char (*base_string
))
8672 if (*base_string
== ','
8673 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8676 displacement_string_end
= temp_string
;
8678 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8682 base_string
= end_op
;
8683 if (is_space_char (*base_string
))
8687 /* There may be an index reg or scale factor here. */
8688 if (*base_string
== ',')
8691 if (is_space_char (*base_string
))
8694 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8697 base_string
= end_op
;
8698 if (is_space_char (*base_string
))
8700 if (*base_string
== ',')
8703 if (is_space_char (*base_string
))
8706 else if (*base_string
!= ')')
8708 as_bad (_("expecting `,' or `)' "
8709 "after index register in `%s'"),
8714 else if (*base_string
== REGISTER_PREFIX
)
8716 end_op
= strchr (base_string
, ',');
8719 as_bad (_("bad register name `%s'"), base_string
);
8723 /* Check for scale factor. */
8724 if (*base_string
!= ')')
8726 char *end_scale
= i386_scale (base_string
);
8731 base_string
= end_scale
;
8732 if (is_space_char (*base_string
))
8734 if (*base_string
!= ')')
8736 as_bad (_("expecting `)' "
8737 "after scale factor in `%s'"),
8742 else if (!i
.index_reg
)
8744 as_bad (_("expecting index register or scale factor "
8745 "after `,'; got '%c'"),
8750 else if (*base_string
!= ')')
8752 as_bad (_("expecting `,' or `)' "
8753 "after base register in `%s'"),
8758 else if (*base_string
== REGISTER_PREFIX
)
8760 end_op
= strchr (base_string
, ',');
8763 as_bad (_("bad register name `%s'"), base_string
);
8768 /* If there's an expression beginning the operand, parse it,
8769 assuming displacement_string_start and
8770 displacement_string_end are meaningful. */
8771 if (displacement_string_start
!= displacement_string_end
)
8773 if (!i386_displacement (displacement_string_start
,
8774 displacement_string_end
))
8778 /* Special case for (%dx) while doing input/output op. */
8780 && operand_type_equal (&i
.base_reg
->reg_type
,
8781 ®16_inoutportreg
)
8783 && i
.log2_scale_factor
== 0
8784 && i
.seg
[i
.mem_operands
] == 0
8785 && !operand_type_check (i
.types
[this_operand
], disp
))
8787 i
.types
[this_operand
] = inoutportreg
;
8791 if (i386_index_check (operand_string
) == 0)
8793 i
.types
[this_operand
].bitfield
.mem
= 1;
8798 /* It's not a memory operand; argh! */
8799 as_bad (_("invalid char %s beginning operand %d `%s'"),
8800 output_invalid (*op_string
),
8805 return 1; /* Normal return. */
8808 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8809 that an rs_machine_dependent frag may reach. */
8812 i386_frag_max_var (fragS
*frag
)
8814 /* The only relaxable frags are for jumps.
8815 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8816 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8817 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8820 /* md_estimate_size_before_relax()
8822 Called just before relax() for rs_machine_dependent frags. The x86
8823 assembler uses these frags to handle variable size jump
8826 Any symbol that is now undefined will not become defined.
8827 Return the correct fr_subtype in the frag.
8828 Return the initial "guess for variable size of frag" to caller.
8829 The guess is actually the growth beyond the fixed part. Whatever
8830 we do to grow the fixed or variable part contributes to our
8834 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8836 /* We've already got fragP->fr_subtype right; all we have to do is
8837 check for un-relaxable symbols. On an ELF system, we can't relax
8838 an externally visible symbol, because it may be overridden by a
8840 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8841 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8843 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
8844 || S_IS_WEAK (fragP
->fr_symbol
)
8845 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
8846 & BSF_GNU_INDIRECT_FUNCTION
))))
8848 #if defined (OBJ_COFF) && defined (TE_PE)
8849 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8850 && S_IS_WEAK (fragP
->fr_symbol
))
8854 /* Symbol is undefined in this segment, or we need to keep a
8855 reloc so that weak symbols can be overridden. */
8856 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8857 enum bfd_reloc_code_real reloc_type
;
8858 unsigned char *opcode
;
8861 if (fragP
->fr_var
!= NO_RELOC
)
8862 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8864 reloc_type
= BFD_RELOC_16_PCREL
;
8866 reloc_type
= BFD_RELOC_32_PCREL
;
8868 old_fr_fix
= fragP
->fr_fix
;
8869 opcode
= (unsigned char *) fragP
->fr_opcode
;
8871 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
8874 /* Make jmp (0xeb) a (d)word displacement jump. */
8876 fragP
->fr_fix
+= size
;
8877 fix_new (fragP
, old_fr_fix
, size
,
8879 fragP
->fr_offset
, 1,
8885 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
8887 /* Negate the condition, and branch past an
8888 unconditional jump. */
8891 /* Insert an unconditional jump. */
8893 /* We added two extra opcode bytes, and have a two byte
8895 fragP
->fr_fix
+= 2 + 2;
8896 fix_new (fragP
, old_fr_fix
+ 2, 2,
8898 fragP
->fr_offset
, 1,
8905 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8910 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8912 fragP
->fr_offset
, 1,
8914 fixP
->fx_signed
= 1;
8918 /* This changes the byte-displacement jump 0x7N
8919 to the (d)word-displacement jump 0x0f,0x8N. */
8920 opcode
[1] = opcode
[0] + 0x10;
8921 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8922 /* We've added an opcode byte. */
8923 fragP
->fr_fix
+= 1 + size
;
8924 fix_new (fragP
, old_fr_fix
+ 1, size
,
8926 fragP
->fr_offset
, 1,
8931 BAD_CASE (fragP
->fr_subtype
);
8935 return fragP
->fr_fix
- old_fr_fix
;
8938 /* Guess size depending on current relax state. Initially the relax
8939 state will correspond to a short jump and we return 1, because
8940 the variable part of the frag (the branch offset) is one byte
8941 long. However, we can relax a section more than once and in that
8942 case we must either set fr_subtype back to the unrelaxed state,
8943 or return the value for the appropriate branch. */
8944 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
8947 /* Called after relax() is finished.
8949 In: Address of frag.
8950 fr_type == rs_machine_dependent.
8951 fr_subtype is what the address relaxed to.
8953 Out: Any fixSs and constants are set up.
8954 Caller will turn frag into a ".space 0". */
8957 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
8960 unsigned char *opcode
;
8961 unsigned char *where_to_put_displacement
= NULL
;
8962 offsetT target_address
;
8963 offsetT opcode_address
;
8964 unsigned int extension
= 0;
8965 offsetT displacement_from_opcode_start
;
8967 opcode
= (unsigned char *) fragP
->fr_opcode
;
8969 /* Address we want to reach in file space. */
8970 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
8972 /* Address opcode resides at in file space. */
8973 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
8975 /* Displacement from opcode start to fill into instruction. */
8976 displacement_from_opcode_start
= target_address
- opcode_address
;
8978 if ((fragP
->fr_subtype
& BIG
) == 0)
8980 /* Don't have to change opcode. */
8981 extension
= 1; /* 1 opcode + 1 displacement */
8982 where_to_put_displacement
= &opcode
[1];
8986 if (no_cond_jump_promotion
8987 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
8988 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
8989 _("long jump required"));
8991 switch (fragP
->fr_subtype
)
8993 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
8994 extension
= 4; /* 1 opcode + 4 displacement */
8996 where_to_put_displacement
= &opcode
[1];
8999 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9000 extension
= 2; /* 1 opcode + 2 displacement */
9002 where_to_put_displacement
= &opcode
[1];
9005 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9006 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9007 extension
= 5; /* 2 opcode + 4 displacement */
9008 opcode
[1] = opcode
[0] + 0x10;
9009 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9010 where_to_put_displacement
= &opcode
[2];
9013 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9014 extension
= 3; /* 2 opcode + 2 displacement */
9015 opcode
[1] = opcode
[0] + 0x10;
9016 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9017 where_to_put_displacement
= &opcode
[2];
9020 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9025 where_to_put_displacement
= &opcode
[3];
9029 BAD_CASE (fragP
->fr_subtype
);
9034 /* If size if less then four we are sure that the operand fits,
9035 but if it's 4, then it could be that the displacement is larger
9037 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9039 && ((addressT
) (displacement_from_opcode_start
- extension
9040 + ((addressT
) 1 << 31))
9041 > (((addressT
) 2 << 31) - 1)))
9043 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9044 _("jump target out of range"));
9045 /* Make us emit 0. */
9046 displacement_from_opcode_start
= extension
;
9048 /* Now put displacement after opcode. */
9049 md_number_to_chars ((char *) where_to_put_displacement
,
9050 (valueT
) (displacement_from_opcode_start
- extension
),
9051 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9052 fragP
->fr_fix
+= extension
;
9055 /* Apply a fixup (fixP) to segment data, once it has been determined
9056 by our caller that we have all the info we need to fix it up.
9058 Parameter valP is the pointer to the value of the bits.
9060 On the 386, immediates, displacements, and data pointers are all in
9061 the same (little-endian) format, so we don't need to care about which
9065 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9067 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9068 valueT value
= *valP
;
9070 #if !defined (TE_Mach)
9073 switch (fixP
->fx_r_type
)
9079 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9082 case BFD_RELOC_X86_64_32S
:
9083 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9086 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9089 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9094 if (fixP
->fx_addsy
!= NULL
9095 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9096 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9097 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9098 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
9099 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PC32_BND
)
9100 && !use_rela_relocations
)
9102 /* This is a hack. There should be a better way to handle this.
9103 This covers for the fact that bfd_install_relocation will
9104 subtract the current location (for partial_inplace, PC relative
9105 relocations); see more below. */
9109 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9112 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9114 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9117 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9120 || (symbol_section_p (fixP
->fx_addsy
)
9121 && sym_seg
!= absolute_section
))
9122 && !generic_force_reloc (fixP
))
9124 /* Yes, we add the values in twice. This is because
9125 bfd_install_relocation subtracts them out again. I think
9126 bfd_install_relocation is broken, but I don't dare change
9128 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9132 #if defined (OBJ_COFF) && defined (TE_PE)
9133 /* For some reason, the PE format does not store a
9134 section address offset for a PC relative symbol. */
9135 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9136 || S_IS_WEAK (fixP
->fx_addsy
))
9137 value
+= md_pcrel_from (fixP
);
9140 #if defined (OBJ_COFF) && defined (TE_PE)
9141 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9143 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9147 /* Fix a few things - the dynamic linker expects certain values here,
9148 and we must not disappoint it. */
9149 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9150 if (IS_ELF
&& fixP
->fx_addsy
)
9151 switch (fixP
->fx_r_type
)
9153 case BFD_RELOC_386_PLT32
:
9154 case BFD_RELOC_X86_64_PLT32
:
9155 case BFD_RELOC_X86_64_PLT32_BND
:
9156 /* Make the jump instruction point to the address of the operand. At
9157 runtime we merely add the offset to the actual PLT entry. */
9161 case BFD_RELOC_386_TLS_GD
:
9162 case BFD_RELOC_386_TLS_LDM
:
9163 case BFD_RELOC_386_TLS_IE_32
:
9164 case BFD_RELOC_386_TLS_IE
:
9165 case BFD_RELOC_386_TLS_GOTIE
:
9166 case BFD_RELOC_386_TLS_GOTDESC
:
9167 case BFD_RELOC_X86_64_TLSGD
:
9168 case BFD_RELOC_X86_64_TLSLD
:
9169 case BFD_RELOC_X86_64_GOTTPOFF
:
9170 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9171 value
= 0; /* Fully resolved at runtime. No addend. */
9173 case BFD_RELOC_386_TLS_LE
:
9174 case BFD_RELOC_386_TLS_LDO_32
:
9175 case BFD_RELOC_386_TLS_LE_32
:
9176 case BFD_RELOC_X86_64_DTPOFF32
:
9177 case BFD_RELOC_X86_64_DTPOFF64
:
9178 case BFD_RELOC_X86_64_TPOFF32
:
9179 case BFD_RELOC_X86_64_TPOFF64
:
9180 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9183 case BFD_RELOC_386_TLS_DESC_CALL
:
9184 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9185 value
= 0; /* Fully resolved at runtime. No addend. */
9186 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9190 case BFD_RELOC_386_GOT32
:
9191 case BFD_RELOC_X86_64_GOT32
:
9192 value
= 0; /* Fully resolved at runtime. No addend. */
9195 case BFD_RELOC_VTABLE_INHERIT
:
9196 case BFD_RELOC_VTABLE_ENTRY
:
9203 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9205 #endif /* !defined (TE_Mach) */
9207 /* Are we finished with this relocation now? */
9208 if (fixP
->fx_addsy
== NULL
)
9210 #if defined (OBJ_COFF) && defined (TE_PE)
9211 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9214 /* Remember value for tc_gen_reloc. */
9215 fixP
->fx_addnumber
= value
;
9216 /* Clear out the frag for now. */
9220 else if (use_rela_relocations
)
9222 fixP
->fx_no_overflow
= 1;
9223 /* Remember value for tc_gen_reloc. */
9224 fixP
->fx_addnumber
= value
;
9228 md_number_to_chars (p
, value
, fixP
->fx_size
);
9232 md_atof (int type
, char *litP
, int *sizeP
)
9234 /* This outputs the LITTLENUMs in REVERSE order;
9235 in accord with the bigendian 386. */
9236 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9239 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9242 output_invalid (int c
)
9245 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9248 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9249 "(0x%x)", (unsigned char) c
);
9250 return output_invalid_buf
;
9253 /* REG_STRING starts *before* REGISTER_PREFIX. */
9255 static const reg_entry
*
9256 parse_real_register (char *reg_string
, char **end_op
)
9258 char *s
= reg_string
;
9260 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9263 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9264 if (*s
== REGISTER_PREFIX
)
9267 if (is_space_char (*s
))
9271 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9273 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9274 return (const reg_entry
*) NULL
;
9278 /* For naked regs, make sure that we are not dealing with an identifier.
9279 This prevents confusing an identifier like `eax_var' with register
9281 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9282 return (const reg_entry
*) NULL
;
9286 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9288 /* Handle floating point regs, allowing spaces in the (i) part. */
9289 if (r
== i386_regtab
/* %st is first entry of table */)
9291 if (is_space_char (*s
))
9296 if (is_space_char (*s
))
9298 if (*s
>= '0' && *s
<= '7')
9302 if (is_space_char (*s
))
9307 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9312 /* We have "%st(" then garbage. */
9313 return (const reg_entry
*) NULL
;
9317 if (r
== NULL
|| allow_pseudo_reg
)
9320 if (operand_type_all_zero (&r
->reg_type
))
9321 return (const reg_entry
*) NULL
;
9323 if ((r
->reg_type
.bitfield
.reg32
9324 || r
->reg_type
.bitfield
.sreg3
9325 || r
->reg_type
.bitfield
.control
9326 || r
->reg_type
.bitfield
.debug
9327 || r
->reg_type
.bitfield
.test
)
9328 && !cpu_arch_flags
.bitfield
.cpui386
)
9329 return (const reg_entry
*) NULL
;
9331 if (r
->reg_type
.bitfield
.floatreg
9332 && !cpu_arch_flags
.bitfield
.cpu8087
9333 && !cpu_arch_flags
.bitfield
.cpu287
9334 && !cpu_arch_flags
.bitfield
.cpu387
)
9335 return (const reg_entry
*) NULL
;
9337 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9338 return (const reg_entry
*) NULL
;
9340 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9341 return (const reg_entry
*) NULL
;
9343 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9344 return (const reg_entry
*) NULL
;
9346 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9347 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9348 return (const reg_entry
*) NULL
;
9350 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9351 if (!allow_index_reg
9352 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9353 return (const reg_entry
*) NULL
;
9355 /* Upper 16 vector register is only available with VREX in 64bit
9357 if ((r
->reg_flags
& RegVRex
))
9359 if (!cpu_arch_flags
.bitfield
.cpuvrex
9360 || flag_code
!= CODE_64BIT
)
9361 return (const reg_entry
*) NULL
;
9366 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9367 || r
->reg_type
.bitfield
.reg64
)
9368 && (!cpu_arch_flags
.bitfield
.cpulm
9369 || !operand_type_equal (&r
->reg_type
, &control
))
9370 && flag_code
!= CODE_64BIT
)
9371 return (const reg_entry
*) NULL
;
9373 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9374 return (const reg_entry
*) NULL
;
9379 /* REG_STRING starts *before* REGISTER_PREFIX. */
9381 static const reg_entry
*
9382 parse_register (char *reg_string
, char **end_op
)
9386 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9387 r
= parse_real_register (reg_string
, end_op
);
9392 char *save
= input_line_pointer
;
9396 input_line_pointer
= reg_string
;
9397 c
= get_symbol_end ();
9398 symbolP
= symbol_find (reg_string
);
9399 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9401 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9403 know (e
->X_op
== O_register
);
9404 know (e
->X_add_number
>= 0
9405 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9406 r
= i386_regtab
+ e
->X_add_number
;
9407 *end_op
= input_line_pointer
;
9409 *input_line_pointer
= c
;
9410 input_line_pointer
= save
;
9416 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9419 char *end
= input_line_pointer
;
9422 r
= parse_register (name
, &input_line_pointer
);
9423 if (r
&& end
<= input_line_pointer
)
9425 *nextcharP
= *input_line_pointer
;
9426 *input_line_pointer
= 0;
9427 e
->X_op
= O_register
;
9428 e
->X_add_number
= r
- i386_regtab
;
9431 input_line_pointer
= end
;
9433 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9437 md_operand (expressionS
*e
)
9442 switch (*input_line_pointer
)
9444 case REGISTER_PREFIX
:
9445 r
= parse_real_register (input_line_pointer
, &end
);
9448 e
->X_op
= O_register
;
9449 e
->X_add_number
= r
- i386_regtab
;
9450 input_line_pointer
= end
;
9455 gas_assert (intel_syntax
);
9456 end
= input_line_pointer
++;
9458 if (*input_line_pointer
== ']')
9460 ++input_line_pointer
;
9461 e
->X_op_symbol
= make_expr_symbol (e
);
9462 e
->X_add_symbol
= NULL
;
9463 e
->X_add_number
= 0;
9469 input_line_pointer
= end
;
9476 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9477 const char *md_shortopts
= "kVQ:sqn";
9479 const char *md_shortopts
= "qn";
9482 #define OPTION_32 (OPTION_MD_BASE + 0)
9483 #define OPTION_64 (OPTION_MD_BASE + 1)
9484 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9485 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9486 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9487 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9488 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9489 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9490 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9491 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9492 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9493 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9494 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9495 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9496 #define OPTION_X32 (OPTION_MD_BASE + 14)
9497 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9498 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9499 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9501 struct option md_longopts
[] =
9503 {"32", no_argument
, NULL
, OPTION_32
},
9504 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9505 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9506 {"64", no_argument
, NULL
, OPTION_64
},
9508 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9509 {"x32", no_argument
, NULL
, OPTION_X32
},
9511 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9512 {"march", required_argument
, NULL
, OPTION_MARCH
},
9513 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9514 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9515 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9516 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9517 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9518 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9519 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9520 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9521 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9522 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9523 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9524 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9525 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9526 {NULL
, no_argument
, NULL
, 0}
9528 size_t md_longopts_size
= sizeof (md_longopts
);
9531 md_parse_option (int c
, char *arg
)
9539 optimize_align_code
= 0;
9546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9547 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9548 should be emitted or not. FIXME: Not implemented. */
9552 /* -V: SVR4 argument to print version ID. */
9554 print_version_id ();
9557 /* -k: Ignore for FreeBSD compatibility. */
9562 /* -s: On i386 Solaris, this tells the native assembler to use
9563 .stab instead of .stab.excl. We always use .stab anyhow. */
9566 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9567 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9570 const char **list
, **l
;
9572 list
= bfd_target_list ();
9573 for (l
= list
; *l
!= NULL
; l
++)
9574 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9575 || strcmp (*l
, "coff-x86-64") == 0
9576 || strcmp (*l
, "pe-x86-64") == 0
9577 || strcmp (*l
, "pei-x86-64") == 0
9578 || strcmp (*l
, "mach-o-x86-64") == 0)
9580 default_arch
= "x86_64";
9584 as_fatal (_("no compiled in support for x86_64"));
9590 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9594 const char **list
, **l
;
9596 list
= bfd_target_list ();
9597 for (l
= list
; *l
!= NULL
; l
++)
9598 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9600 default_arch
= "x86_64:32";
9604 as_fatal (_("no compiled in support for 32bit x86_64"));
9608 as_fatal (_("32bit x86_64 is only supported for ELF"));
9613 default_arch
= "i386";
9617 #ifdef SVR4_COMMENT_CHARS
9622 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9624 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9628 i386_comment_chars
= n
;
9634 arch
= xstrdup (arg
);
9638 as_fatal (_("invalid -march= option: `%s'"), arg
);
9639 next
= strchr (arch
, '+');
9642 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9644 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9647 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9650 cpu_arch_name
= cpu_arch
[j
].name
;
9651 cpu_sub_arch_name
= NULL
;
9652 cpu_arch_flags
= cpu_arch
[j
].flags
;
9653 cpu_arch_isa
= cpu_arch
[j
].type
;
9654 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9655 if (!cpu_arch_tune_set
)
9657 cpu_arch_tune
= cpu_arch_isa
;
9658 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9662 else if (*cpu_arch
[j
].name
== '.'
9663 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9665 /* ISA entension. */
9666 i386_cpu_flags flags
;
9668 if (!cpu_arch
[j
].negated
)
9669 flags
= cpu_flags_or (cpu_arch_flags
,
9672 flags
= cpu_flags_and_not (cpu_arch_flags
,
9674 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9676 if (cpu_sub_arch_name
)
9678 char *name
= cpu_sub_arch_name
;
9679 cpu_sub_arch_name
= concat (name
,
9681 (const char *) NULL
);
9685 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9686 cpu_arch_flags
= flags
;
9687 cpu_arch_isa_flags
= flags
;
9693 if (j
>= ARRAY_SIZE (cpu_arch
))
9694 as_fatal (_("invalid -march= option: `%s'"), arg
);
9698 while (next
!= NULL
);
9703 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9704 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9706 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9708 cpu_arch_tune_set
= 1;
9709 cpu_arch_tune
= cpu_arch
[j
].type
;
9710 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9714 if (j
>= ARRAY_SIZE (cpu_arch
))
9715 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9718 case OPTION_MMNEMONIC
:
9719 if (strcasecmp (arg
, "att") == 0)
9721 else if (strcasecmp (arg
, "intel") == 0)
9724 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9727 case OPTION_MSYNTAX
:
9728 if (strcasecmp (arg
, "att") == 0)
9730 else if (strcasecmp (arg
, "intel") == 0)
9733 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9736 case OPTION_MINDEX_REG
:
9737 allow_index_reg
= 1;
9740 case OPTION_MNAKED_REG
:
9741 allow_naked_reg
= 1;
9744 case OPTION_MOLD_GCC
:
9748 case OPTION_MSSE2AVX
:
9752 case OPTION_MSSE_CHECK
:
9753 if (strcasecmp (arg
, "error") == 0)
9754 sse_check
= check_error
;
9755 else if (strcasecmp (arg
, "warning") == 0)
9756 sse_check
= check_warning
;
9757 else if (strcasecmp (arg
, "none") == 0)
9758 sse_check
= check_none
;
9760 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9763 case OPTION_MOPERAND_CHECK
:
9764 if (strcasecmp (arg
, "error") == 0)
9765 operand_check
= check_error
;
9766 else if (strcasecmp (arg
, "warning") == 0)
9767 operand_check
= check_warning
;
9768 else if (strcasecmp (arg
, "none") == 0)
9769 operand_check
= check_none
;
9771 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9774 case OPTION_MAVXSCALAR
:
9775 if (strcasecmp (arg
, "128") == 0)
9777 else if (strcasecmp (arg
, "256") == 0)
9780 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9783 case OPTION_MADD_BND_PREFIX
:
9787 case OPTION_MEVEXLIG
:
9788 if (strcmp (arg
, "128") == 0)
9790 else if (strcmp (arg
, "256") == 0)
9792 else if (strcmp (arg
, "512") == 0)
9795 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9798 case OPTION_MEVEXWIG
:
9799 if (strcmp (arg
, "0") == 0)
9801 else if (strcmp (arg
, "1") == 0)
9804 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9813 #define MESSAGE_TEMPLATE \
9817 show_arch (FILE *stream
, int ext
, int check
)
9819 static char message
[] = MESSAGE_TEMPLATE
;
9820 char *start
= message
+ 27;
9822 int size
= sizeof (MESSAGE_TEMPLATE
);
9829 left
= size
- (start
- message
);
9830 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9832 /* Should it be skipped? */
9833 if (cpu_arch
[j
].skip
)
9836 name
= cpu_arch
[j
].name
;
9837 len
= cpu_arch
[j
].len
;
9840 /* It is an extension. Skip if we aren't asked to show it. */
9851 /* It is an processor. Skip if we show only extension. */
9854 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9856 /* It is an impossible processor - skip. */
9860 /* Reserve 2 spaces for ", " or ",\0" */
9863 /* Check if there is any room. */
9871 p
= mempcpy (p
, name
, len
);
9875 /* Output the current message now and start a new one. */
9878 fprintf (stream
, "%s\n", message
);
9880 left
= size
- (start
- message
) - len
- 2;
9882 gas_assert (left
>= 0);
9884 p
= mempcpy (p
, name
, len
);
9889 fprintf (stream
, "%s\n", message
);
9893 md_show_usage (FILE *stream
)
9895 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9896 fprintf (stream
, _("\
9898 -V print assembler version number\n\
9901 fprintf (stream
, _("\
9902 -n Do not optimize code alignment\n\
9903 -q quieten some warnings\n"));
9904 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9905 fprintf (stream
, _("\
9908 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9909 || defined (TE_PE) || defined (TE_PEP))
9910 fprintf (stream
, _("\
9911 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
9913 #ifdef SVR4_COMMENT_CHARS
9914 fprintf (stream
, _("\
9915 --divide do not treat `/' as a comment character\n"));
9917 fprintf (stream
, _("\
9918 --divide ignored\n"));
9920 fprintf (stream
, _("\
9921 -march=CPU[,+EXTENSION...]\n\
9922 generate code for CPU and EXTENSION, CPU is one of:\n"));
9923 show_arch (stream
, 0, 1);
9924 fprintf (stream
, _("\
9925 EXTENSION is combination of:\n"));
9926 show_arch (stream
, 1, 0);
9927 fprintf (stream
, _("\
9928 -mtune=CPU optimize for CPU, CPU is one of:\n"));
9929 show_arch (stream
, 0, 0);
9930 fprintf (stream
, _("\
9931 -msse2avx encode SSE instructions with VEX prefix\n"));
9932 fprintf (stream
, _("\
9933 -msse-check=[none|error|warning]\n\
9934 check SSE instructions\n"));
9935 fprintf (stream
, _("\
9936 -moperand-check=[none|error|warning]\n\
9937 check operand combinations for validity\n"));
9938 fprintf (stream
, _("\
9939 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
9941 fprintf (stream
, _("\
9942 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
9944 fprintf (stream
, _("\
9945 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
9946 for EVEX.W bit ignored instructions\n"));
9947 fprintf (stream
, _("\
9948 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
9949 fprintf (stream
, _("\
9950 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
9951 fprintf (stream
, _("\
9952 -mindex-reg support pseudo index registers\n"));
9953 fprintf (stream
, _("\
9954 -mnaked-reg don't require `%%' prefix for registers\n"));
9955 fprintf (stream
, _("\
9956 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
9957 fprintf (stream
, _("\
9958 -madd-bnd-prefix add BND prefix for all valid branches\n"));
9961 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
9962 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9963 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9965 /* Pick the target format to use. */
9968 i386_target_format (void)
9970 if (!strncmp (default_arch
, "x86_64", 6))
9972 update_code_flag (CODE_64BIT
, 1);
9973 if (default_arch
[6] == '\0')
9974 x86_elf_abi
= X86_64_ABI
;
9976 x86_elf_abi
= X86_64_X32_ABI
;
9978 else if (!strcmp (default_arch
, "i386"))
9979 update_code_flag (CODE_32BIT
, 1);
9981 as_fatal (_("unknown architecture"));
9983 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
9984 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
9985 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
9986 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
9988 switch (OUTPUT_FLAVOR
)
9990 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
9991 case bfd_target_aout_flavour
:
9992 return AOUT_TARGET_FORMAT
;
9994 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
9995 # if defined (TE_PE) || defined (TE_PEP)
9996 case bfd_target_coff_flavour
:
9997 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
9998 # elif defined (TE_GO32)
9999 case bfd_target_coff_flavour
:
10000 return "coff-go32";
10002 case bfd_target_coff_flavour
:
10003 return "coff-i386";
10006 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10007 case bfd_target_elf_flavour
:
10009 const char *format
;
10011 switch (x86_elf_abi
)
10014 format
= ELF_TARGET_FORMAT
;
10017 use_rela_relocations
= 1;
10019 format
= ELF_TARGET_FORMAT64
;
10021 case X86_64_X32_ABI
:
10022 use_rela_relocations
= 1;
10024 disallow_64bit_reloc
= 1;
10025 format
= ELF_TARGET_FORMAT32
;
10028 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10030 if (x86_elf_abi
!= X86_64_ABI
)
10031 as_fatal (_("Intel L1OM is 64bit only"));
10032 return ELF_TARGET_L1OM_FORMAT
;
10034 if (cpu_arch_isa
== PROCESSOR_K1OM
)
10036 if (x86_elf_abi
!= X86_64_ABI
)
10037 as_fatal (_("Intel K1OM is 64bit only"));
10038 return ELF_TARGET_K1OM_FORMAT
;
10044 #if defined (OBJ_MACH_O)
10045 case bfd_target_mach_o_flavour
:
10046 if (flag_code
== CODE_64BIT
)
10048 use_rela_relocations
= 1;
10050 return "mach-o-x86-64";
10053 return "mach-o-i386";
10061 #endif /* OBJ_MAYBE_ more than one */
10063 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
10065 i386_elf_emit_arch_note (void)
10067 if (IS_ELF
&& cpu_arch_name
!= NULL
)
10070 asection
*seg
= now_seg
;
10071 subsegT subseg
= now_subseg
;
10072 Elf_Internal_Note i_note
;
10073 Elf_External_Note e_note
;
10074 asection
*note_secp
;
10077 /* Create the .note section. */
10078 note_secp
= subseg_new (".note", 0);
10079 bfd_set_section_flags (stdoutput
,
10081 SEC_HAS_CONTENTS
| SEC_READONLY
);
10083 /* Process the arch string. */
10084 len
= strlen (cpu_arch_name
);
10086 i_note
.namesz
= len
+ 1;
10088 i_note
.type
= NT_ARCH
;
10089 p
= frag_more (sizeof (e_note
.namesz
));
10090 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
10091 p
= frag_more (sizeof (e_note
.descsz
));
10092 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
10093 p
= frag_more (sizeof (e_note
.type
));
10094 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
10095 p
= frag_more (len
+ 1);
10096 strcpy (p
, cpu_arch_name
);
10098 frag_align (2, 0, 0);
10100 subseg_set (seg
, subseg
);
10106 md_undefined_symbol (char *name
)
10108 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10109 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10110 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10111 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10115 if (symbol_find (name
))
10116 as_bad (_("GOT already in symbol table"));
10117 GOT_symbol
= symbol_new (name
, undefined_section
,
10118 (valueT
) 0, &zero_address_frag
);
10125 /* Round up a section size to the appropriate boundary. */
10128 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10130 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10131 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10133 /* For a.out, force the section size to be aligned. If we don't do
10134 this, BFD will align it for us, but it will not write out the
10135 final bytes of the section. This may be a bug in BFD, but it is
10136 easier to fix it here since that is how the other a.out targets
10140 align
= bfd_get_section_alignment (stdoutput
, segment
);
10141 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
10148 /* On the i386, PC-relative offsets are relative to the start of the
10149 next instruction. That is, the address of the offset, plus its
10150 size, since the offset is always the last part of the insn. */
10153 md_pcrel_from (fixS
*fixP
)
10155 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10161 s_bss (int ignore ATTRIBUTE_UNUSED
)
10165 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10167 obj_elf_section_change_hook ();
10169 temp
= get_absolute_expression ();
10170 subseg_set (bss_section
, (subsegT
) temp
);
10171 demand_empty_rest_of_line ();
10177 i386_validate_fix (fixS
*fixp
)
10179 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
10181 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10185 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10190 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10192 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10194 fixp
->fx_subsy
= 0;
10199 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10202 bfd_reloc_code_real_type code
;
10204 switch (fixp
->fx_r_type
)
10206 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10207 case BFD_RELOC_SIZE32
:
10208 case BFD_RELOC_SIZE64
:
10209 if (S_IS_DEFINED (fixp
->fx_addsy
)
10210 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10212 /* Resolve size relocation against local symbol to size of
10213 the symbol plus addend. */
10214 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10215 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10216 && !fits_in_unsigned_long (value
))
10217 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10218 _("symbol size computation overflow"));
10219 fixp
->fx_addsy
= NULL
;
10220 fixp
->fx_subsy
= NULL
;
10221 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10226 case BFD_RELOC_X86_64_PLT32
:
10227 case BFD_RELOC_X86_64_PLT32_BND
:
10228 case BFD_RELOC_X86_64_GOT32
:
10229 case BFD_RELOC_X86_64_GOTPCREL
:
10230 case BFD_RELOC_386_PLT32
:
10231 case BFD_RELOC_386_GOT32
:
10232 case BFD_RELOC_386_GOTOFF
:
10233 case BFD_RELOC_386_GOTPC
:
10234 case BFD_RELOC_386_TLS_GD
:
10235 case BFD_RELOC_386_TLS_LDM
:
10236 case BFD_RELOC_386_TLS_LDO_32
:
10237 case BFD_RELOC_386_TLS_IE_32
:
10238 case BFD_RELOC_386_TLS_IE
:
10239 case BFD_RELOC_386_TLS_GOTIE
:
10240 case BFD_RELOC_386_TLS_LE_32
:
10241 case BFD_RELOC_386_TLS_LE
:
10242 case BFD_RELOC_386_TLS_GOTDESC
:
10243 case BFD_RELOC_386_TLS_DESC_CALL
:
10244 case BFD_RELOC_X86_64_TLSGD
:
10245 case BFD_RELOC_X86_64_TLSLD
:
10246 case BFD_RELOC_X86_64_DTPOFF32
:
10247 case BFD_RELOC_X86_64_DTPOFF64
:
10248 case BFD_RELOC_X86_64_GOTTPOFF
:
10249 case BFD_RELOC_X86_64_TPOFF32
:
10250 case BFD_RELOC_X86_64_TPOFF64
:
10251 case BFD_RELOC_X86_64_GOTOFF64
:
10252 case BFD_RELOC_X86_64_GOTPC32
:
10253 case BFD_RELOC_X86_64_GOT64
:
10254 case BFD_RELOC_X86_64_GOTPCREL64
:
10255 case BFD_RELOC_X86_64_GOTPC64
:
10256 case BFD_RELOC_X86_64_GOTPLT64
:
10257 case BFD_RELOC_X86_64_PLTOFF64
:
10258 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10259 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10260 case BFD_RELOC_RVA
:
10261 case BFD_RELOC_VTABLE_ENTRY
:
10262 case BFD_RELOC_VTABLE_INHERIT
:
10264 case BFD_RELOC_32_SECREL
:
10266 code
= fixp
->fx_r_type
;
10268 case BFD_RELOC_X86_64_32S
:
10269 if (!fixp
->fx_pcrel
)
10271 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10272 code
= fixp
->fx_r_type
;
10276 if (fixp
->fx_pcrel
)
10278 switch (fixp
->fx_size
)
10281 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10282 _("can not do %d byte pc-relative relocation"),
10284 code
= BFD_RELOC_32_PCREL
;
10286 case 1: code
= BFD_RELOC_8_PCREL
; break;
10287 case 2: code
= BFD_RELOC_16_PCREL
; break;
10289 code
= (fixp
->fx_r_type
== BFD_RELOC_X86_64_PC32_BND
10290 ? fixp
-> fx_r_type
: BFD_RELOC_32_PCREL
);
10293 case 8: code
= BFD_RELOC_64_PCREL
; break;
10299 switch (fixp
->fx_size
)
10302 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10303 _("can not do %d byte relocation"),
10305 code
= BFD_RELOC_32
;
10307 case 1: code
= BFD_RELOC_8
; break;
10308 case 2: code
= BFD_RELOC_16
; break;
10309 case 4: code
= BFD_RELOC_32
; break;
10311 case 8: code
= BFD_RELOC_64
; break;
10318 if ((code
== BFD_RELOC_32
10319 || code
== BFD_RELOC_32_PCREL
10320 || code
== BFD_RELOC_X86_64_32S
)
10322 && fixp
->fx_addsy
== GOT_symbol
)
10325 code
= BFD_RELOC_386_GOTPC
;
10327 code
= BFD_RELOC_X86_64_GOTPC32
;
10329 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10331 && fixp
->fx_addsy
== GOT_symbol
)
10333 code
= BFD_RELOC_X86_64_GOTPC64
;
10336 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10337 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10338 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10340 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10342 if (!use_rela_relocations
)
10344 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10345 vtable entry to be used in the relocation's section offset. */
10346 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10347 rel
->address
= fixp
->fx_offset
;
10348 #if defined (OBJ_COFF) && defined (TE_PE)
10349 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10350 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10355 /* Use the rela in 64bit mode. */
10358 if (disallow_64bit_reloc
)
10361 case BFD_RELOC_X86_64_DTPOFF64
:
10362 case BFD_RELOC_X86_64_TPOFF64
:
10363 case BFD_RELOC_64_PCREL
:
10364 case BFD_RELOC_X86_64_GOTOFF64
:
10365 case BFD_RELOC_X86_64_GOT64
:
10366 case BFD_RELOC_X86_64_GOTPCREL64
:
10367 case BFD_RELOC_X86_64_GOTPC64
:
10368 case BFD_RELOC_X86_64_GOTPLT64
:
10369 case BFD_RELOC_X86_64_PLTOFF64
:
10370 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10371 _("cannot represent relocation type %s in x32 mode"),
10372 bfd_get_reloc_code_name (code
));
10378 if (!fixp
->fx_pcrel
)
10379 rel
->addend
= fixp
->fx_offset
;
10383 case BFD_RELOC_X86_64_PLT32
:
10384 case BFD_RELOC_X86_64_PLT32_BND
:
10385 case BFD_RELOC_X86_64_GOT32
:
10386 case BFD_RELOC_X86_64_GOTPCREL
:
10387 case BFD_RELOC_X86_64_TLSGD
:
10388 case BFD_RELOC_X86_64_TLSLD
:
10389 case BFD_RELOC_X86_64_GOTTPOFF
:
10390 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10391 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10392 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10395 rel
->addend
= (section
->vma
10397 + fixp
->fx_addnumber
10398 + md_pcrel_from (fixp
));
10403 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10404 if (rel
->howto
== NULL
)
10406 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10407 _("cannot represent relocation type %s"),
10408 bfd_get_reloc_code_name (code
));
10409 /* Set howto to a garbage value so that we can keep going. */
10410 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10411 gas_assert (rel
->howto
!= NULL
);
10417 #include "tc-i386-intel.c"
10420 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10422 int saved_naked_reg
;
10423 char saved_register_dot
;
10425 saved_naked_reg
= allow_naked_reg
;
10426 allow_naked_reg
= 1;
10427 saved_register_dot
= register_chars
['.'];
10428 register_chars
['.'] = '.';
10429 allow_pseudo_reg
= 1;
10430 expression_and_evaluate (exp
);
10431 allow_pseudo_reg
= 0;
10432 register_chars
['.'] = saved_register_dot
;
10433 allow_naked_reg
= saved_naked_reg
;
10435 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10437 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10439 exp
->X_op
= O_constant
;
10440 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10441 .dw2_regnum
[flag_code
>> 1];
10444 exp
->X_op
= O_illegal
;
10449 tc_x86_frame_initial_instructions (void)
10451 static unsigned int sp_regno
[2];
10453 if (!sp_regno
[flag_code
>> 1])
10455 char *saved_input
= input_line_pointer
;
10456 char sp
[][4] = {"esp", "rsp"};
10459 input_line_pointer
= sp
[flag_code
>> 1];
10460 tc_x86_parse_to_dw2regnum (&exp
);
10461 gas_assert (exp
.X_op
== O_constant
);
10462 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10463 input_line_pointer
= saved_input
;
10466 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10467 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10471 x86_dwarf2_addr_size (void)
10473 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10474 if (x86_elf_abi
== X86_64_X32_ABI
)
10477 return bfd_arch_bits_per_address (stdoutput
) / 8;
10481 i386_elf_section_type (const char *str
, size_t len
)
10483 if (flag_code
== CODE_64BIT
10484 && len
== sizeof ("unwind") - 1
10485 && strncmp (str
, "unwind", 6) == 0)
10486 return SHT_X86_64_UNWIND
;
10493 i386_solaris_fix_up_eh_frame (segT sec
)
10495 if (flag_code
== CODE_64BIT
)
10496 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10502 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10506 exp
.X_op
= O_secrel
;
10507 exp
.X_add_symbol
= symbol
;
10508 exp
.X_add_number
= 0;
10509 emit_expr (&exp
, size
);
10513 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10514 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10517 x86_64_section_letter (int letter
, char **ptr_msg
)
10519 if (flag_code
== CODE_64BIT
)
10522 return SHF_X86_64_LARGE
;
10524 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10527 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10532 x86_64_section_word (char *str
, size_t len
)
10534 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10535 return SHF_X86_64_LARGE
;
10541 handle_large_common (int small ATTRIBUTE_UNUSED
)
10543 if (flag_code
!= CODE_64BIT
)
10545 s_comm_internal (0, elf_common_parse
);
10546 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10550 static segT lbss_section
;
10551 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10552 asection
*saved_bss_section
= bss_section
;
10554 if (lbss_section
== NULL
)
10556 flagword applicable
;
10557 segT seg
= now_seg
;
10558 subsegT subseg
= now_subseg
;
10560 /* The .lbss section is for local .largecomm symbols. */
10561 lbss_section
= subseg_new (".lbss", 0);
10562 applicable
= bfd_applicable_section_flags (stdoutput
);
10563 bfd_set_section_flags (stdoutput
, lbss_section
,
10564 applicable
& SEC_ALLOC
);
10565 seg_info (lbss_section
)->bss
= 1;
10567 subseg_set (seg
, subseg
);
10570 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10571 bss_section
= lbss_section
;
10573 s_comm_internal (0, elf_common_parse
);
10575 elf_com_section_ptr
= saved_com_section_ptr
;
10576 bss_section
= saved_bss_section
;
10579 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */