1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2017 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
139 /* Used to turn off indicated flags. */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 i386_cpu_flags flags
; /* cpu feature flags */
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
157 static void pe_directive_secrel (int);
159 static void signed_cons (int);
160 static char *output_invalid (int c
);
161 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
163 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS
*);
168 static int i386_intel_parse_name (const char *, expressionS
*);
169 static const reg_entry
*parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template
*match_template (char);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry
*build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS
*, offsetT
);
188 static void output_disp (fragS
*, offsetT
);
190 static void s_bss (int);
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
196 static const char *default_arch
= DEFAULT_ARCH
;
198 /* This struct describes rounding control and SAE in the instruction. */
212 static struct RC_Operation rc_op
;
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
219 const reg_entry
*mask
;
220 unsigned int zeroing
;
221 /* The operand where this operation is associated. */
225 static struct Mask_Operation mask_op
;
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
229 struct Broadcast_Operation
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
234 /* Index of broadcasted operand. */
238 static struct Broadcast_Operation broadcast_op
;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes
[4];
246 /* Destination or source register specifier. */
247 const reg_entry
*register_specifier
;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry
*regs
;
262 operand_size_mismatch
,
263 operand_type_mismatch
,
264 register_type_mismatch
,
265 number_of_operands_mismatch
,
266 invalid_instruction_suffix
,
269 unsupported_with_intel_mnemonic
,
272 invalid_vsib_address
,
273 invalid_vector_register_set
,
274 unsupported_vector_index_register
,
275 unsupported_broadcast
,
276 broadcast_not_on_src_operand
,
279 mask_not_on_destination
,
282 rc_sae_operand_not_last_imm
,
283 invalid_register_operand
,
289 /* TM holds the template for the insn were currently assembling. */
292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
296 /* OPERANDS gives the number of given operands. */
297 unsigned int operands
;
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
302 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
304 /* TYPES [i] is the type (see above #defines) which tells us how to
305 use OP[i] for the corresponding operand. */
306 i386_operand_type types
[MAX_OPERANDS
];
308 /* Displacement expression, immediate expression, or register for each
310 union i386_op op
[MAX_OPERANDS
];
312 /* Flags for operands. */
313 unsigned int flags
[MAX_OPERANDS
];
314 #define Operand_PCrel 1
316 /* Relocation type for operand */
317 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry
*base_reg
;
322 const reg_entry
*index_reg
;
323 unsigned int log2_scale_factor
;
325 /* SEG gives the seg_entries of this insn. They are zero unless
326 explicit segment overrides are given. */
327 const seg_entry
*seg
[2];
329 /* Copied first memory operand string, for re-checking. */
332 /* PREFIX holds all the given prefix opcodes (usually null).
333 PREFIXES is the number of prefix opcodes. */
334 unsigned int prefixes
;
335 unsigned char prefix
[MAX_PREFIXES
];
337 /* RM and SIB are the modrm byte and the sib byte where the
338 addressing modes of this insn are encoded. */
345 /* Masking attributes. */
346 struct Mask_Operation
*mask
;
348 /* Rounding control and SAE attributes. */
349 struct RC_Operation
*rounding
;
351 /* Broadcasting attributes. */
352 struct Broadcast_Operation
*broadcast
;
354 /* Compressed disp8*N attribute. */
355 unsigned int memshift
;
357 /* Prefer load or store in encoding. */
360 dir_encoding_default
= 0,
365 /* Prefer 8bit or 32bit displacement in encoding. */
368 disp_encoding_default
= 0,
373 /* How to encode vector instructions. */
376 vex_encoding_default
= 0,
383 const char *rep_prefix
;
386 const char *hle_prefix
;
388 /* Have BND prefix. */
389 const char *bnd_prefix
;
391 /* Have NOTRACK prefix. */
392 const char *notrack_prefix
;
395 enum i386_error error
;
398 typedef struct _i386_insn i386_insn
;
400 /* Link RC type with corresponding string, that'll be looked for in
409 static const struct RC_name RC_NamesTable
[] =
411 { rne
, STRING_COMMA_LEN ("rn-sae") },
412 { rd
, STRING_COMMA_LEN ("rd-sae") },
413 { ru
, STRING_COMMA_LEN ("ru-sae") },
414 { rz
, STRING_COMMA_LEN ("rz-sae") },
415 { saeonly
, STRING_COMMA_LEN ("sae") },
418 /* List of chars besides those in app.c:symbol_chars that can start an
419 operand. Used to prevent the scrubber eating vital white-space. */
420 const char extra_symbol_chars
[] = "*%-([{}"
429 #if (defined (TE_I386AIX) \
430 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
431 && !defined (TE_GNU) \
432 && !defined (TE_LINUX) \
433 && !defined (TE_NACL) \
434 && !defined (TE_NETWARE) \
435 && !defined (TE_FreeBSD) \
436 && !defined (TE_DragonFly) \
437 && !defined (TE_NetBSD)))
438 /* This array holds the chars that always start a comment. If the
439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441 const char *i386_comment_chars
= "#/";
442 #define SVR4_COMMENT_CHARS 1
443 #define PREFIX_SEPARATOR '\\'
446 const char *i386_comment_chars
= "#";
447 #define PREFIX_SEPARATOR '/'
450 /* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
454 first line of the input file. This is because the compiler outputs
455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
457 '/' isn't otherwise defined. */
458 const char line_comment_chars
[] = "#/";
460 const char line_separator_chars
[] = ";";
462 /* Chars that can be used to separate mant from exp in floating point
464 const char EXP_CHARS
[] = "eE";
466 /* Chars that mean this number is a floating point constant
469 const char FLT_CHARS
[] = "fFdDxX";
471 /* Tables for lexical analysis. */
472 static char mnemonic_chars
[256];
473 static char register_chars
[256];
474 static char operand_chars
[256];
475 static char identifier_chars
[256];
476 static char digit_chars
[256];
478 /* Lexical macros. */
479 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480 #define is_operand_char(x) (operand_chars[(unsigned char) x])
481 #define is_register_char(x) (register_chars[(unsigned char) x])
482 #define is_space_char(x) ((x) == ' ')
483 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484 #define is_digit_char(x) (digit_chars[(unsigned char) x])
486 /* All non-digit non-letter characters that may occur in an operand. */
487 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
489 /* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
492 assembler instruction). */
493 static char save_stack
[32];
494 static char *save_stack_p
;
495 #define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497 #define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
500 /* The instruction we're assembling. */
503 /* Possible templates for current insn. */
504 static const templates
*current_templates
;
506 /* Per instruction expressionS buffers: max displacements & immediates. */
507 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
508 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
510 /* Current operand we are working on. */
511 static int this_operand
= -1;
513 /* We support four different modes. FLAG_CODE variable is used to distinguish
521 static enum flag_code flag_code
;
522 static unsigned int object_64bit
;
523 static unsigned int disallow_64bit_reloc
;
524 static int use_rela_relocations
= 0;
526 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
530 /* The ELF ABI to use. */
538 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
541 #if defined (TE_PE) || defined (TE_PEP)
542 /* Use big object file format. */
543 static int use_big_obj
= 0;
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 /* 1 if generating code for a shared library. */
548 static int shared
= 0;
551 /* 1 for intel syntax,
553 static int intel_syntax
= 0;
555 /* 1 for Intel64 ISA,
559 /* 1 for intel mnemonic,
560 0 if att mnemonic. */
561 static int intel_mnemonic
= !SYSV386_COMPAT
;
563 /* 1 if support old (<= 2.8.1) versions of gcc. */
564 static int old_gcc
= OLDGCC_COMPAT
;
566 /* 1 if pseudo registers are permitted. */
567 static int allow_pseudo_reg
= 0;
569 /* 1 if register prefix % not required. */
570 static int allow_naked_reg
= 0;
572 /* 1 if the assembler should add BND prefix for all control-transferring
573 instructions supporting it, even if this prefix wasn't specified
575 static int add_bnd_prefix
= 0;
577 /* 1 if pseudo index register, eiz/riz, is allowed . */
578 static int allow_index_reg
= 0;
580 /* 1 if the assembler should ignore LOCK prefix, even if it was
581 specified explicitly. */
582 static int omit_lock_prefix
= 0;
584 /* 1 if the assembler should encode lfence, mfence, and sfence as
585 "lock addl $0, (%{re}sp)". */
586 static int avoid_fence
= 0;
588 /* 1 if the assembler should generate relax relocations. */
590 static int generate_relax_relocations
591 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
593 static enum check_kind
599 sse_check
, operand_check
= check_warning
;
601 /* Register prefix used for error message. */
602 static const char *register_prefix
= "%";
604 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
605 leave, push, and pop instructions so that gcc has the same stack
606 frame as in 32 bit mode. */
607 static char stackop_size
= '\0';
609 /* Non-zero to optimize code alignment. */
610 int optimize_align_code
= 1;
612 /* Non-zero to quieten some warnings. */
613 static int quiet_warnings
= 0;
616 static const char *cpu_arch_name
= NULL
;
617 static char *cpu_sub_arch_name
= NULL
;
619 /* CPU feature flags. */
620 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
622 /* If we have selected a cpu we are generating instructions for. */
623 static int cpu_arch_tune_set
= 0;
625 /* Cpu we are generating instructions for. */
626 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
628 /* CPU feature flags of cpu we are generating instructions for. */
629 static i386_cpu_flags cpu_arch_tune_flags
;
631 /* CPU instruction set architecture used. */
632 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
634 /* CPU feature flags of instruction set architecture used. */
635 i386_cpu_flags cpu_arch_isa_flags
;
637 /* If set, conditional jumps are not automatically promoted to handle
638 larger than a byte offset. */
639 static unsigned int no_cond_jump_promotion
= 0;
641 /* Encode SSE instructions with VEX prefix. */
642 static unsigned int sse2avx
;
644 /* Encode scalar AVX instructions with specific vector length. */
651 /* Encode scalar EVEX LIG instructions with specific vector length. */
659 /* Encode EVEX WIG instructions with specific evex.w. */
666 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
667 static enum rc_type evexrcig
= rne
;
669 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
670 static symbolS
*GOT_symbol
;
672 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
673 unsigned int x86_dwarf2_return_column
;
675 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
676 int x86_cie_data_alignment
;
678 /* Interface to relax_segment.
679 There are 3 major relax states for 386 jump insns because the
680 different types of jumps add different sizes to frags when we're
681 figuring out what sort of jump to choose to reach a given label. */
684 #define UNCOND_JUMP 0
686 #define COND_JUMP86 2
691 #define SMALL16 (SMALL | CODE16)
693 #define BIG16 (BIG | CODE16)
697 #define INLINE __inline__
703 #define ENCODE_RELAX_STATE(type, size) \
704 ((relax_substateT) (((type) << 2) | (size)))
705 #define TYPE_FROM_RELAX_STATE(s) \
707 #define DISP_SIZE_FROM_RELAX_STATE(s) \
708 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
710 /* This table is used by relax_frag to promote short jumps to long
711 ones where necessary. SMALL (short) jumps may be promoted to BIG
712 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
713 don't allow a short jump in a 32 bit code segment to be promoted to
714 a 16 bit offset jump because it's slower (requires data size
715 prefix), and doesn't work, unless the destination is in the bottom
716 64k of the code segment (The top 16 bits of eip are zeroed). */
718 const relax_typeS md_relax_table
[] =
721 1) most positive reach of this state,
722 2) most negative reach of this state,
723 3) how many bytes this mode will have in the variable part of the frag
724 4) which index into the table to try if we can't fit into this one. */
726 /* UNCOND_JUMP states. */
727 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
728 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
729 /* dword jmp adds 4 bytes to frag:
730 0 extra opcode bytes, 4 displacement bytes. */
732 /* word jmp adds 2 byte2 to frag:
733 0 extra opcode bytes, 2 displacement bytes. */
736 /* COND_JUMP states. */
737 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
738 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
739 /* dword conditionals adds 5 bytes to frag:
740 1 extra opcode byte, 4 displacement bytes. */
742 /* word conditionals add 3 bytes to frag:
743 1 extra opcode byte, 2 displacement bytes. */
746 /* COND_JUMP86 states. */
747 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
748 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
749 /* dword conditionals adds 5 bytes to frag:
750 1 extra opcode byte, 4 displacement bytes. */
752 /* word conditionals add 4 bytes to frag:
753 1 displacement byte and a 3 byte long branch insn. */
757 static const arch_entry cpu_arch
[] =
759 /* Do not replace the first two entries - i386_target_format()
760 relies on them being there in this order. */
761 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
762 CPU_GENERIC32_FLAGS
, 0 },
763 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
764 CPU_GENERIC64_FLAGS
, 0 },
765 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
767 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
769 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
771 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
773 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
775 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
777 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
779 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
781 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
782 CPU_PENTIUMPRO_FLAGS
, 0 },
783 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
785 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
787 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
789 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
791 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
792 CPU_NOCONA_FLAGS
, 0 },
793 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
795 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
797 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
798 CPU_CORE2_FLAGS
, 1 },
799 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
800 CPU_CORE2_FLAGS
, 0 },
801 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
802 CPU_COREI7_FLAGS
, 0 },
803 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
805 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
807 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
808 CPU_IAMCU_FLAGS
, 0 },
809 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
811 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
813 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
814 CPU_ATHLON_FLAGS
, 0 },
815 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
817 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
819 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
821 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
822 CPU_AMDFAM10_FLAGS
, 0 },
823 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
824 CPU_BDVER1_FLAGS
, 0 },
825 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
826 CPU_BDVER2_FLAGS
, 0 },
827 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
828 CPU_BDVER3_FLAGS
, 0 },
829 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
830 CPU_BDVER4_FLAGS
, 0 },
831 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
832 CPU_ZNVER1_FLAGS
, 0 },
833 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
834 CPU_BTVER1_FLAGS
, 0 },
835 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
836 CPU_BTVER2_FLAGS
, 0 },
837 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
839 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
841 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
843 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
845 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
847 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
849 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
851 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
853 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
854 CPU_SSSE3_FLAGS
, 0 },
855 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
856 CPU_SSE4_1_FLAGS
, 0 },
857 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
858 CPU_SSE4_2_FLAGS
, 0 },
859 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
860 CPU_SSE4_2_FLAGS
, 0 },
861 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
863 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
865 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
866 CPU_AVX512F_FLAGS
, 0 },
867 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
868 CPU_AVX512CD_FLAGS
, 0 },
869 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
870 CPU_AVX512ER_FLAGS
, 0 },
871 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
872 CPU_AVX512PF_FLAGS
, 0 },
873 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
874 CPU_AVX512DQ_FLAGS
, 0 },
875 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
876 CPU_AVX512BW_FLAGS
, 0 },
877 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
878 CPU_AVX512VL_FLAGS
, 0 },
879 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
881 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
882 CPU_VMFUNC_FLAGS
, 0 },
883 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
885 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
886 CPU_XSAVE_FLAGS
, 0 },
887 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
888 CPU_XSAVEOPT_FLAGS
, 0 },
889 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
890 CPU_XSAVEC_FLAGS
, 0 },
891 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
892 CPU_XSAVES_FLAGS
, 0 },
893 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
895 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
896 CPU_PCLMUL_FLAGS
, 0 },
897 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
898 CPU_PCLMUL_FLAGS
, 1 },
899 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
900 CPU_FSGSBASE_FLAGS
, 0 },
901 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
902 CPU_RDRND_FLAGS
, 0 },
903 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
905 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
907 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
909 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
911 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
913 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
915 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
916 CPU_MOVBE_FLAGS
, 0 },
917 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
919 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
921 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
922 CPU_LZCNT_FLAGS
, 0 },
923 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
925 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
927 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
928 CPU_INVPCID_FLAGS
, 0 },
929 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
930 CPU_CLFLUSH_FLAGS
, 0 },
931 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
933 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
934 CPU_SYSCALL_FLAGS
, 0 },
935 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
936 CPU_RDTSCP_FLAGS
, 0 },
937 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
938 CPU_3DNOW_FLAGS
, 0 },
939 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
940 CPU_3DNOWA_FLAGS
, 0 },
941 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
942 CPU_PADLOCK_FLAGS
, 0 },
943 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
945 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
947 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
948 CPU_SSE4A_FLAGS
, 0 },
949 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
951 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
953 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
955 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
957 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
958 CPU_RDSEED_FLAGS
, 0 },
959 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
960 CPU_PRFCHW_FLAGS
, 0 },
961 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
963 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
965 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
967 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
968 CPU_CLFLUSHOPT_FLAGS
, 0 },
969 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
970 CPU_PREFETCHWT1_FLAGS
, 0 },
971 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
973 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
975 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
976 CPU_AVX512IFMA_FLAGS
, 0 },
977 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
978 CPU_AVX512VBMI_FLAGS
, 0 },
979 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
980 CPU_AVX512_4FMAPS_FLAGS
, 0 },
981 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
982 CPU_AVX512_4VNNIW_FLAGS
, 0 },
983 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
984 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
985 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
986 CPU_CLZERO_FLAGS
, 0 },
987 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
988 CPU_MWAITX_FLAGS
, 0 },
989 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
990 CPU_OSPKE_FLAGS
, 0 },
991 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
992 CPU_RDPID_FLAGS
, 0 },
993 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
994 CPU_PTWRITE_FLAGS
, 0 },
995 { STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN
,
999 static const noarch_entry cpu_noarch
[] =
1001 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1002 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1003 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1004 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1005 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1006 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1007 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1008 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1009 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1010 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1011 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1012 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1013 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1014 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1015 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1016 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1017 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1018 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1019 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1020 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1021 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1022 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1023 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1024 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1025 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1026 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1030 /* Like s_lcomm_internal in gas/read.c but the alignment string
1031 is allowed to be optional. */
1034 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1041 && *input_line_pointer
== ',')
1043 align
= parse_align (needs_align
- 1);
1045 if (align
== (addressT
) -1)
1060 bss_alloc (symbolP
, size
, align
);
1065 pe_lcomm (int needs_align
)
1067 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1071 const pseudo_typeS md_pseudo_table
[] =
1073 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1074 {"align", s_align_bytes
, 0},
1076 {"align", s_align_ptwo
, 0},
1078 {"arch", set_cpu_arch
, 0},
1082 {"lcomm", pe_lcomm
, 1},
1084 {"ffloat", float_cons
, 'f'},
1085 {"dfloat", float_cons
, 'd'},
1086 {"tfloat", float_cons
, 'x'},
1088 {"slong", signed_cons
, 4},
1089 {"noopt", s_ignore
, 0},
1090 {"optim", s_ignore
, 0},
1091 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1092 {"code16", set_code_flag
, CODE_16BIT
},
1093 {"code32", set_code_flag
, CODE_32BIT
},
1094 {"code64", set_code_flag
, CODE_64BIT
},
1095 {"intel_syntax", set_intel_syntax
, 1},
1096 {"att_syntax", set_intel_syntax
, 0},
1097 {"intel_mnemonic", set_intel_mnemonic
, 1},
1098 {"att_mnemonic", set_intel_mnemonic
, 0},
1099 {"allow_index_reg", set_allow_index_reg
, 1},
1100 {"disallow_index_reg", set_allow_index_reg
, 0},
1101 {"sse_check", set_check
, 0},
1102 {"operand_check", set_check
, 1},
1103 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1104 {"largecomm", handle_large_common
, 0},
1106 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1107 {"loc", dwarf2_directive_loc
, 0},
1108 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1111 {"secrel32", pe_directive_secrel
, 0},
1116 /* For interface with expression (). */
1117 extern char *input_line_pointer
;
1119 /* Hash table for instruction mnemonic lookup. */
1120 static struct hash_control
*op_hash
;
1122 /* Hash table for register lookup. */
1123 static struct hash_control
*reg_hash
;
1126 i386_align_code (fragS
*fragP
, int count
)
1128 /* Various efficient no-op patterns for aligning code labels.
1129 Note: Don't try to assemble the instructions in the comments.
1130 0L and 0w are not legal. */
1131 static const unsigned char f32_1
[] =
1133 static const unsigned char f32_2
[] =
1134 {0x66,0x90}; /* xchg %ax,%ax */
1135 static const unsigned char f32_3
[] =
1136 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1137 static const unsigned char f32_4
[] =
1138 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1139 static const unsigned char f32_5
[] =
1141 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1142 static const unsigned char f32_6
[] =
1143 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1144 static const unsigned char f32_7
[] =
1145 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1146 static const unsigned char f32_8
[] =
1148 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1149 static const unsigned char f32_9
[] =
1150 {0x89,0xf6, /* movl %esi,%esi */
1151 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1152 static const unsigned char f32_10
[] =
1153 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1154 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1155 static const unsigned char f32_11
[] =
1156 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1157 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1158 static const unsigned char f32_12
[] =
1159 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1160 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1161 static const unsigned char f32_13
[] =
1162 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1163 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1164 static const unsigned char f32_14
[] =
1165 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1166 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1167 static const unsigned char f16_3
[] =
1168 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1169 static const unsigned char f16_4
[] =
1170 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1171 static const unsigned char f16_5
[] =
1173 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1174 static const unsigned char f16_6
[] =
1175 {0x89,0xf6, /* mov %si,%si */
1176 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1177 static const unsigned char f16_7
[] =
1178 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1179 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1180 static const unsigned char f16_8
[] =
1181 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1182 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1183 static const unsigned char jump_31
[] =
1184 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1185 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1186 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1187 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1188 static const unsigned char *const f32_patt
[] = {
1189 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1190 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1192 static const unsigned char *const f16_patt
[] = {
1193 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1195 /* nopl (%[re]ax) */
1196 static const unsigned char alt_3
[] =
1198 /* nopl 0(%[re]ax) */
1199 static const unsigned char alt_4
[] =
1200 {0x0f,0x1f,0x40,0x00};
1201 /* nopl 0(%[re]ax,%[re]ax,1) */
1202 static const unsigned char alt_5
[] =
1203 {0x0f,0x1f,0x44,0x00,0x00};
1204 /* nopw 0(%[re]ax,%[re]ax,1) */
1205 static const unsigned char alt_6
[] =
1206 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1207 /* nopl 0L(%[re]ax) */
1208 static const unsigned char alt_7
[] =
1209 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1210 /* nopl 0L(%[re]ax,%[re]ax,1) */
1211 static const unsigned char alt_8
[] =
1212 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1213 /* nopw 0L(%[re]ax,%[re]ax,1) */
1214 static const unsigned char alt_9
[] =
1215 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1216 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1217 static const unsigned char alt_10
[] =
1218 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1219 static const unsigned char *const alt_patt
[] = {
1220 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1224 /* Only align for at least a positive non-zero boundary. */
1225 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1228 /* We need to decide which NOP sequence to use for 32bit and
1229 64bit. When -mtune= is used:
1231 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1232 PROCESSOR_GENERIC32, f32_patt will be used.
1233 2. For the rest, alt_patt will be used.
1235 When -mtune= isn't used, alt_patt will be used if
1236 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1239 When -march= or .arch is used, we can't use anything beyond
1240 cpu_arch_isa_flags. */
1242 if (flag_code
== CODE_16BIT
)
1246 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1248 /* Adjust jump offset. */
1249 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1252 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1253 f16_patt
[count
- 1], count
);
1257 const unsigned char *const *patt
= NULL
;
1259 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1261 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1262 switch (cpu_arch_tune
)
1264 case PROCESSOR_UNKNOWN
:
1265 /* We use cpu_arch_isa_flags to check if we SHOULD
1266 optimize with nops. */
1267 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1272 case PROCESSOR_PENTIUM4
:
1273 case PROCESSOR_NOCONA
:
1274 case PROCESSOR_CORE
:
1275 case PROCESSOR_CORE2
:
1276 case PROCESSOR_COREI7
:
1277 case PROCESSOR_L1OM
:
1278 case PROCESSOR_K1OM
:
1279 case PROCESSOR_GENERIC64
:
1281 case PROCESSOR_ATHLON
:
1283 case PROCESSOR_AMDFAM10
:
1285 case PROCESSOR_ZNVER
:
1289 case PROCESSOR_I386
:
1290 case PROCESSOR_I486
:
1291 case PROCESSOR_PENTIUM
:
1292 case PROCESSOR_PENTIUMPRO
:
1293 case PROCESSOR_IAMCU
:
1294 case PROCESSOR_GENERIC32
:
1301 switch (fragP
->tc_frag_data
.tune
)
1303 case PROCESSOR_UNKNOWN
:
1304 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1305 PROCESSOR_UNKNOWN. */
1309 case PROCESSOR_I386
:
1310 case PROCESSOR_I486
:
1311 case PROCESSOR_PENTIUM
:
1312 case PROCESSOR_IAMCU
:
1314 case PROCESSOR_ATHLON
:
1316 case PROCESSOR_AMDFAM10
:
1318 case PROCESSOR_ZNVER
:
1320 case PROCESSOR_GENERIC32
:
1321 /* We use cpu_arch_isa_flags to check if we CAN optimize
1323 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1328 case PROCESSOR_PENTIUMPRO
:
1329 case PROCESSOR_PENTIUM4
:
1330 case PROCESSOR_NOCONA
:
1331 case PROCESSOR_CORE
:
1332 case PROCESSOR_CORE2
:
1333 case PROCESSOR_COREI7
:
1334 case PROCESSOR_L1OM
:
1335 case PROCESSOR_K1OM
:
1336 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1341 case PROCESSOR_GENERIC64
:
1347 if (patt
== f32_patt
)
1349 /* If the padding is less than 15 bytes, we use the normal
1350 ones. Otherwise, we use a jump instruction and adjust
1354 /* For 64bit, the limit is 3 bytes. */
1355 if (flag_code
== CODE_64BIT
1356 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1361 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1362 patt
[count
- 1], count
);
1365 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1367 /* Adjust jump offset. */
1368 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1373 /* Maximum length of an instruction is 10 byte. If the
1374 padding is greater than 10 bytes and we don't use jump,
1375 we have to break it into smaller pieces. */
1376 int padding
= count
;
1377 while (padding
> 10)
1380 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1385 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1386 patt
[padding
- 1], padding
);
1389 fragP
->fr_var
= count
;
1393 operand_type_all_zero (const union i386_operand_type
*x
)
1395 switch (ARRAY_SIZE(x
->array
))
1406 return !x
->array
[0];
1413 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1415 switch (ARRAY_SIZE(x
->array
))
1433 operand_type_equal (const union i386_operand_type
*x
,
1434 const union i386_operand_type
*y
)
1436 switch (ARRAY_SIZE(x
->array
))
1439 if (x
->array
[2] != y
->array
[2])
1443 if (x
->array
[1] != y
->array
[1])
1447 return x
->array
[0] == y
->array
[0];
1455 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1457 switch (ARRAY_SIZE(x
->array
))
1468 return !x
->array
[0];
1475 cpu_flags_equal (const union i386_cpu_flags
*x
,
1476 const union i386_cpu_flags
*y
)
1478 switch (ARRAY_SIZE(x
->array
))
1481 if (x
->array
[2] != y
->array
[2])
1485 if (x
->array
[1] != y
->array
[1])
1489 return x
->array
[0] == y
->array
[0];
1497 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1499 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1500 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1503 static INLINE i386_cpu_flags
1504 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1506 switch (ARRAY_SIZE (x
.array
))
1509 x
.array
[2] &= y
.array
[2];
1512 x
.array
[1] &= y
.array
[1];
1515 x
.array
[0] &= y
.array
[0];
1523 static INLINE i386_cpu_flags
1524 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1526 switch (ARRAY_SIZE (x
.array
))
1529 x
.array
[2] |= y
.array
[2];
1532 x
.array
[1] |= y
.array
[1];
1535 x
.array
[0] |= y
.array
[0];
1543 static INLINE i386_cpu_flags
1544 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1546 switch (ARRAY_SIZE (x
.array
))
1549 x
.array
[2] &= ~y
.array
[2];
1552 x
.array
[1] &= ~y
.array
[1];
1555 x
.array
[0] &= ~y
.array
[0];
1563 #define CPU_FLAGS_ARCH_MATCH 0x1
1564 #define CPU_FLAGS_64BIT_MATCH 0x2
1565 #define CPU_FLAGS_AES_MATCH 0x4
1566 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1567 #define CPU_FLAGS_AVX_MATCH 0x10
1569 #define CPU_FLAGS_32BIT_MATCH \
1570 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1571 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1572 #define CPU_FLAGS_PERFECT_MATCH \
1573 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1575 /* Return CPU flags match bits. */
1578 cpu_flags_match (const insn_template
*t
)
1580 i386_cpu_flags x
= t
->cpu_flags
;
1581 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1583 x
.bitfield
.cpu64
= 0;
1584 x
.bitfield
.cpuno64
= 0;
1586 if (cpu_flags_all_zero (&x
))
1588 /* This instruction is available on all archs. */
1589 match
|= CPU_FLAGS_32BIT_MATCH
;
1593 /* This instruction is available only on some archs. */
1594 i386_cpu_flags cpu
= cpu_arch_flags
;
1596 cpu
= cpu_flags_and (x
, cpu
);
1597 if (!cpu_flags_all_zero (&cpu
))
1599 if (x
.bitfield
.cpuavx
)
1601 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1602 if (cpu
.bitfield
.cpuavx
)
1604 /* Check SSE2AVX. */
1605 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1607 match
|= (CPU_FLAGS_ARCH_MATCH
1608 | CPU_FLAGS_AVX_MATCH
);
1610 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1611 match
|= CPU_FLAGS_AES_MATCH
;
1613 if (!x
.bitfield
.cpupclmul
1614 || cpu
.bitfield
.cpupclmul
)
1615 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1619 match
|= CPU_FLAGS_ARCH_MATCH
;
1621 else if (x
.bitfield
.cpuavx512vl
)
1623 /* Match AVX512VL. */
1624 if (cpu
.bitfield
.cpuavx512vl
)
1626 /* Need another match. */
1627 cpu
.bitfield
.cpuavx512vl
= 0;
1628 if (!cpu_flags_all_zero (&cpu
))
1629 match
|= CPU_FLAGS_32BIT_MATCH
;
1631 match
|= CPU_FLAGS_ARCH_MATCH
;
1634 match
|= CPU_FLAGS_ARCH_MATCH
;
1637 match
|= CPU_FLAGS_32BIT_MATCH
;
1643 static INLINE i386_operand_type
1644 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1646 switch (ARRAY_SIZE (x
.array
))
1649 x
.array
[2] &= y
.array
[2];
1652 x
.array
[1] &= y
.array
[1];
1655 x
.array
[0] &= y
.array
[0];
1663 static INLINE i386_operand_type
1664 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1666 switch (ARRAY_SIZE (x
.array
))
1669 x
.array
[2] |= y
.array
[2];
1672 x
.array
[1] |= y
.array
[1];
1675 x
.array
[0] |= y
.array
[0];
1683 static INLINE i386_operand_type
1684 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1686 switch (ARRAY_SIZE (x
.array
))
1689 x
.array
[2] ^= y
.array
[2];
1692 x
.array
[1] ^= y
.array
[1];
1695 x
.array
[0] ^= y
.array
[0];
1703 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1704 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1705 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1706 static const i386_operand_type inoutportreg
1707 = OPERAND_TYPE_INOUTPORTREG
;
1708 static const i386_operand_type reg16_inoutportreg
1709 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1710 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1711 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1712 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1713 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1714 static const i386_operand_type anydisp
1715 = OPERAND_TYPE_ANYDISP
;
1716 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1717 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1718 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1719 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1720 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1721 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1722 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1723 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1724 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1725 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1726 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1727 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1728 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1729 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1740 operand_type_check (i386_operand_type t
, enum operand_type c
)
1745 return (t
.bitfield
.reg8
1748 || t
.bitfield
.reg64
);
1751 return (t
.bitfield
.imm8
1755 || t
.bitfield
.imm32s
1756 || t
.bitfield
.imm64
);
1759 return (t
.bitfield
.disp8
1760 || t
.bitfield
.disp16
1761 || t
.bitfield
.disp32
1762 || t
.bitfield
.disp32s
1763 || t
.bitfield
.disp64
);
1766 return (t
.bitfield
.disp8
1767 || t
.bitfield
.disp16
1768 || t
.bitfield
.disp32
1769 || t
.bitfield
.disp32s
1770 || t
.bitfield
.disp64
1771 || t
.bitfield
.baseindex
);
1780 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1781 operand J for instruction template T. */
1784 match_reg_size (const insn_template
*t
, unsigned int j
)
1786 return !((i
.types
[j
].bitfield
.byte
1787 && !t
->operand_types
[j
].bitfield
.byte
)
1788 || (i
.types
[j
].bitfield
.word
1789 && !t
->operand_types
[j
].bitfield
.word
)
1790 || (i
.types
[j
].bitfield
.dword
1791 && !t
->operand_types
[j
].bitfield
.dword
)
1792 || (i
.types
[j
].bitfield
.qword
1793 && !t
->operand_types
[j
].bitfield
.qword
));
1796 /* Return 1 if there is no conflict in any size on operand J for
1797 instruction template T. */
1800 match_mem_size (const insn_template
*t
, unsigned int j
)
1802 return (match_reg_size (t
, j
)
1803 && !((i
.types
[j
].bitfield
.unspecified
1805 && !t
->operand_types
[j
].bitfield
.unspecified
)
1806 || (i
.types
[j
].bitfield
.fword
1807 && !t
->operand_types
[j
].bitfield
.fword
)
1808 || (i
.types
[j
].bitfield
.tbyte
1809 && !t
->operand_types
[j
].bitfield
.tbyte
)
1810 || (i
.types
[j
].bitfield
.xmmword
1811 && !t
->operand_types
[j
].bitfield
.xmmword
)
1812 || (i
.types
[j
].bitfield
.ymmword
1813 && !t
->operand_types
[j
].bitfield
.ymmword
)
1814 || (i
.types
[j
].bitfield
.zmmword
1815 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1818 /* Return 1 if there is no size conflict on any operands for
1819 instruction template T. */
1822 operand_size_match (const insn_template
*t
)
1827 /* Don't check jump instructions. */
1828 if (t
->opcode_modifier
.jump
1829 || t
->opcode_modifier
.jumpbyte
1830 || t
->opcode_modifier
.jumpdword
1831 || t
->opcode_modifier
.jumpintersegment
)
1834 /* Check memory and accumulator operand size. */
1835 for (j
= 0; j
< i
.operands
; j
++)
1837 if (t
->operand_types
[j
].bitfield
.anysize
)
1840 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1846 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1855 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1858 i
.error
= operand_size_mismatch
;
1862 /* Check reverse. */
1863 gas_assert (i
.operands
== 2);
1866 for (j
= 0; j
< 2; j
++)
1868 if (t
->operand_types
[j
].bitfield
.acc
1869 && !match_reg_size (t
, j
? 0 : 1))
1872 if (i
.types
[j
].bitfield
.mem
1873 && !match_mem_size (t
, j
? 0 : 1))
1881 operand_type_match (i386_operand_type overlap
,
1882 i386_operand_type given
)
1884 i386_operand_type temp
= overlap
;
1886 temp
.bitfield
.jumpabsolute
= 0;
1887 temp
.bitfield
.unspecified
= 0;
1888 temp
.bitfield
.byte
= 0;
1889 temp
.bitfield
.word
= 0;
1890 temp
.bitfield
.dword
= 0;
1891 temp
.bitfield
.fword
= 0;
1892 temp
.bitfield
.qword
= 0;
1893 temp
.bitfield
.tbyte
= 0;
1894 temp
.bitfield
.xmmword
= 0;
1895 temp
.bitfield
.ymmword
= 0;
1896 temp
.bitfield
.zmmword
= 0;
1897 if (operand_type_all_zero (&temp
))
1900 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1901 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1905 i
.error
= operand_type_mismatch
;
1909 /* If given types g0 and g1 are registers they must be of the same type
1910 unless the expected operand type register overlap is null.
1911 Note that Acc in a template matches every size of reg. */
1914 operand_type_register_match (i386_operand_type m0
,
1915 i386_operand_type g0
,
1916 i386_operand_type t0
,
1917 i386_operand_type m1
,
1918 i386_operand_type g1
,
1919 i386_operand_type t1
)
1921 if (!operand_type_check (g0
, reg
))
1924 if (!operand_type_check (g1
, reg
))
1927 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1928 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1929 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1930 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1933 if (m0
.bitfield
.acc
)
1935 t0
.bitfield
.reg8
= 1;
1936 t0
.bitfield
.reg16
= 1;
1937 t0
.bitfield
.reg32
= 1;
1938 t0
.bitfield
.reg64
= 1;
1941 if (m1
.bitfield
.acc
)
1943 t1
.bitfield
.reg8
= 1;
1944 t1
.bitfield
.reg16
= 1;
1945 t1
.bitfield
.reg32
= 1;
1946 t1
.bitfield
.reg64
= 1;
1949 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1950 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1951 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1952 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1955 i
.error
= register_type_mismatch
;
1960 static INLINE
unsigned int
1961 register_number (const reg_entry
*r
)
1963 unsigned int nr
= r
->reg_num
;
1965 if (r
->reg_flags
& RegRex
)
1968 if (r
->reg_flags
& RegVRex
)
1974 static INLINE
unsigned int
1975 mode_from_disp_size (i386_operand_type t
)
1977 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1979 else if (t
.bitfield
.disp16
1980 || t
.bitfield
.disp32
1981 || t
.bitfield
.disp32s
)
1988 fits_in_signed_byte (addressT num
)
1990 return num
+ 0x80 <= 0xff;
1994 fits_in_unsigned_byte (addressT num
)
2000 fits_in_unsigned_word (addressT num
)
2002 return num
<= 0xffff;
2006 fits_in_signed_word (addressT num
)
2008 return num
+ 0x8000 <= 0xffff;
2012 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2017 return num
+ 0x80000000 <= 0xffffffff;
2019 } /* fits_in_signed_long() */
2022 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2027 return num
<= 0xffffffff;
2029 } /* fits_in_unsigned_long() */
2032 fits_in_vec_disp8 (offsetT num
)
2034 int shift
= i
.memshift
;
2040 mask
= (1 << shift
) - 1;
2042 /* Return 0 if NUM isn't properly aligned. */
2046 /* Check if NUM will fit in 8bit after shift. */
2047 return fits_in_signed_byte (num
>> shift
);
2051 fits_in_imm4 (offsetT num
)
2053 return (num
& 0xf) == num
;
2056 static i386_operand_type
2057 smallest_imm_type (offsetT num
)
2059 i386_operand_type t
;
2061 operand_type_set (&t
, 0);
2062 t
.bitfield
.imm64
= 1;
2064 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2066 /* This code is disabled on the 486 because all the Imm1 forms
2067 in the opcode table are slower on the i486. They're the
2068 versions with the implicitly specified single-position
2069 displacement, which has another syntax if you really want to
2071 t
.bitfield
.imm1
= 1;
2072 t
.bitfield
.imm8
= 1;
2073 t
.bitfield
.imm8s
= 1;
2074 t
.bitfield
.imm16
= 1;
2075 t
.bitfield
.imm32
= 1;
2076 t
.bitfield
.imm32s
= 1;
2078 else if (fits_in_signed_byte (num
))
2080 t
.bitfield
.imm8
= 1;
2081 t
.bitfield
.imm8s
= 1;
2082 t
.bitfield
.imm16
= 1;
2083 t
.bitfield
.imm32
= 1;
2084 t
.bitfield
.imm32s
= 1;
2086 else if (fits_in_unsigned_byte (num
))
2088 t
.bitfield
.imm8
= 1;
2089 t
.bitfield
.imm16
= 1;
2090 t
.bitfield
.imm32
= 1;
2091 t
.bitfield
.imm32s
= 1;
2093 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2095 t
.bitfield
.imm16
= 1;
2096 t
.bitfield
.imm32
= 1;
2097 t
.bitfield
.imm32s
= 1;
2099 else if (fits_in_signed_long (num
))
2101 t
.bitfield
.imm32
= 1;
2102 t
.bitfield
.imm32s
= 1;
2104 else if (fits_in_unsigned_long (num
))
2105 t
.bitfield
.imm32
= 1;
2111 offset_in_range (offsetT val
, int size
)
2117 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2118 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2119 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2121 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2127 /* If BFD64, sign extend val for 32bit address mode. */
2128 if (flag_code
!= CODE_64BIT
2129 || i
.prefix
[ADDR_PREFIX
])
2130 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2131 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2134 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2136 char buf1
[40], buf2
[40];
2138 sprint_value (buf1
, val
);
2139 sprint_value (buf2
, val
& mask
);
2140 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2155 a. PREFIX_EXIST if attempting to add a prefix where one from the
2156 same class already exists.
2157 b. PREFIX_LOCK if lock prefix is added.
2158 c. PREFIX_REP if rep/repne prefix is added.
2159 d. PREFIX_DS if ds prefix is added.
2160 e. PREFIX_OTHER if other prefix is added.
2163 static enum PREFIX_GROUP
2164 add_prefix (unsigned int prefix
)
2166 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2169 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2170 && flag_code
== CODE_64BIT
)
2172 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2173 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2174 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2185 case DS_PREFIX_OPCODE
:
2188 case CS_PREFIX_OPCODE
:
2189 case ES_PREFIX_OPCODE
:
2190 case FS_PREFIX_OPCODE
:
2191 case GS_PREFIX_OPCODE
:
2192 case SS_PREFIX_OPCODE
:
2196 case REPNE_PREFIX_OPCODE
:
2197 case REPE_PREFIX_OPCODE
:
2202 case LOCK_PREFIX_OPCODE
:
2211 case ADDR_PREFIX_OPCODE
:
2215 case DATA_PREFIX_OPCODE
:
2219 if (i
.prefix
[q
] != 0)
2227 i
.prefix
[q
] |= prefix
;
2230 as_bad (_("same type of prefix used twice"));
2236 update_code_flag (int value
, int check
)
2238 PRINTF_LIKE ((*as_error
));
2240 flag_code
= (enum flag_code
) value
;
2241 if (flag_code
== CODE_64BIT
)
2243 cpu_arch_flags
.bitfield
.cpu64
= 1;
2244 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2248 cpu_arch_flags
.bitfield
.cpu64
= 0;
2249 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2251 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2254 as_error
= as_fatal
;
2257 (*as_error
) (_("64bit mode not supported on `%s'."),
2258 cpu_arch_name
? cpu_arch_name
: default_arch
);
2260 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2263 as_error
= as_fatal
;
2266 (*as_error
) (_("32bit mode not supported on `%s'."),
2267 cpu_arch_name
? cpu_arch_name
: default_arch
);
2269 stackop_size
= '\0';
2273 set_code_flag (int value
)
2275 update_code_flag (value
, 0);
2279 set_16bit_gcc_code_flag (int new_code_flag
)
2281 flag_code
= (enum flag_code
) new_code_flag
;
2282 if (flag_code
!= CODE_16BIT
)
2284 cpu_arch_flags
.bitfield
.cpu64
= 0;
2285 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2286 stackop_size
= LONG_MNEM_SUFFIX
;
2290 set_intel_syntax (int syntax_flag
)
2292 /* Find out if register prefixing is specified. */
2293 int ask_naked_reg
= 0;
2296 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2299 int e
= get_symbol_name (&string
);
2301 if (strcmp (string
, "prefix") == 0)
2303 else if (strcmp (string
, "noprefix") == 0)
2306 as_bad (_("bad argument to syntax directive."));
2307 (void) restore_line_pointer (e
);
2309 demand_empty_rest_of_line ();
2311 intel_syntax
= syntax_flag
;
2313 if (ask_naked_reg
== 0)
2314 allow_naked_reg
= (intel_syntax
2315 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2317 allow_naked_reg
= (ask_naked_reg
< 0);
2319 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2321 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2322 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2323 register_prefix
= allow_naked_reg
? "" : "%";
2327 set_intel_mnemonic (int mnemonic_flag
)
2329 intel_mnemonic
= mnemonic_flag
;
2333 set_allow_index_reg (int flag
)
2335 allow_index_reg
= flag
;
2339 set_check (int what
)
2341 enum check_kind
*kind
;
2346 kind
= &operand_check
;
2357 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2360 int e
= get_symbol_name (&string
);
2362 if (strcmp (string
, "none") == 0)
2364 else if (strcmp (string
, "warning") == 0)
2365 *kind
= check_warning
;
2366 else if (strcmp (string
, "error") == 0)
2367 *kind
= check_error
;
2369 as_bad (_("bad argument to %s_check directive."), str
);
2370 (void) restore_line_pointer (e
);
2373 as_bad (_("missing argument for %s_check directive"), str
);
2375 demand_empty_rest_of_line ();
2379 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2380 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2382 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2383 static const char *arch
;
2385 /* Intel LIOM is only supported on ELF. */
2391 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2392 use default_arch. */
2393 arch
= cpu_arch_name
;
2395 arch
= default_arch
;
2398 /* If we are targeting Intel MCU, we must enable it. */
2399 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2400 || new_flag
.bitfield
.cpuiamcu
)
2403 /* If we are targeting Intel L1OM, we must enable it. */
2404 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2405 || new_flag
.bitfield
.cpul1om
)
2408 /* If we are targeting Intel K1OM, we must enable it. */
2409 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2410 || new_flag
.bitfield
.cpuk1om
)
2413 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2418 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2422 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2425 int e
= get_symbol_name (&string
);
2427 i386_cpu_flags flags
;
2429 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2431 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2433 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2437 cpu_arch_name
= cpu_arch
[j
].name
;
2438 cpu_sub_arch_name
= NULL
;
2439 cpu_arch_flags
= cpu_arch
[j
].flags
;
2440 if (flag_code
== CODE_64BIT
)
2442 cpu_arch_flags
.bitfield
.cpu64
= 1;
2443 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2447 cpu_arch_flags
.bitfield
.cpu64
= 0;
2448 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2450 cpu_arch_isa
= cpu_arch
[j
].type
;
2451 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2452 if (!cpu_arch_tune_set
)
2454 cpu_arch_tune
= cpu_arch_isa
;
2455 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2460 flags
= cpu_flags_or (cpu_arch_flags
,
2463 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2465 if (cpu_sub_arch_name
)
2467 char *name
= cpu_sub_arch_name
;
2468 cpu_sub_arch_name
= concat (name
,
2470 (const char *) NULL
);
2474 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2475 cpu_arch_flags
= flags
;
2476 cpu_arch_isa_flags
= flags
;
2478 (void) restore_line_pointer (e
);
2479 demand_empty_rest_of_line ();
2484 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2486 /* Disable an ISA extension. */
2487 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2488 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2490 flags
= cpu_flags_and_not (cpu_arch_flags
,
2491 cpu_noarch
[j
].flags
);
2492 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2494 if (cpu_sub_arch_name
)
2496 char *name
= cpu_sub_arch_name
;
2497 cpu_sub_arch_name
= concat (name
, string
,
2498 (const char *) NULL
);
2502 cpu_sub_arch_name
= xstrdup (string
);
2503 cpu_arch_flags
= flags
;
2504 cpu_arch_isa_flags
= flags
;
2506 (void) restore_line_pointer (e
);
2507 demand_empty_rest_of_line ();
2511 j
= ARRAY_SIZE (cpu_arch
);
2514 if (j
>= ARRAY_SIZE (cpu_arch
))
2515 as_bad (_("no such architecture: `%s'"), string
);
2517 *input_line_pointer
= e
;
2520 as_bad (_("missing cpu architecture"));
2522 no_cond_jump_promotion
= 0;
2523 if (*input_line_pointer
== ','
2524 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2529 ++input_line_pointer
;
2530 e
= get_symbol_name (&string
);
2532 if (strcmp (string
, "nojumps") == 0)
2533 no_cond_jump_promotion
= 1;
2534 else if (strcmp (string
, "jumps") == 0)
2537 as_bad (_("no such architecture modifier: `%s'"), string
);
2539 (void) restore_line_pointer (e
);
2542 demand_empty_rest_of_line ();
2545 enum bfd_architecture
2548 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2550 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2551 || flag_code
!= CODE_64BIT
)
2552 as_fatal (_("Intel L1OM is 64bit ELF only"));
2553 return bfd_arch_l1om
;
2555 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2557 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2558 || flag_code
!= CODE_64BIT
)
2559 as_fatal (_("Intel K1OM is 64bit ELF only"));
2560 return bfd_arch_k1om
;
2562 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2564 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2565 || flag_code
== CODE_64BIT
)
2566 as_fatal (_("Intel MCU is 32bit ELF only"));
2567 return bfd_arch_iamcu
;
2570 return bfd_arch_i386
;
2576 if (!strncmp (default_arch
, "x86_64", 6))
2578 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2580 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2581 || default_arch
[6] != '\0')
2582 as_fatal (_("Intel L1OM is 64bit ELF only"));
2583 return bfd_mach_l1om
;
2585 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2587 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2588 || default_arch
[6] != '\0')
2589 as_fatal (_("Intel K1OM is 64bit ELF only"));
2590 return bfd_mach_k1om
;
2592 else if (default_arch
[6] == '\0')
2593 return bfd_mach_x86_64
;
2595 return bfd_mach_x64_32
;
2597 else if (!strcmp (default_arch
, "i386")
2598 || !strcmp (default_arch
, "iamcu"))
2600 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2602 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2603 as_fatal (_("Intel MCU is 32bit ELF only"));
2604 return bfd_mach_i386_iamcu
;
2607 return bfd_mach_i386_i386
;
2610 as_fatal (_("unknown architecture"));
2616 const char *hash_err
;
2618 /* Support pseudo prefixes like {disp32}. */
2619 lex_type
['{'] = LEX_BEGIN_NAME
;
2621 /* Initialize op_hash hash table. */
2622 op_hash
= hash_new ();
2625 const insn_template
*optab
;
2626 templates
*core_optab
;
2628 /* Setup for loop. */
2630 core_optab
= XNEW (templates
);
2631 core_optab
->start
= optab
;
2636 if (optab
->name
== NULL
2637 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2639 /* different name --> ship out current template list;
2640 add to hash table; & begin anew. */
2641 core_optab
->end
= optab
;
2642 hash_err
= hash_insert (op_hash
,
2644 (void *) core_optab
);
2647 as_fatal (_("can't hash %s: %s"),
2651 if (optab
->name
== NULL
)
2653 core_optab
= XNEW (templates
);
2654 core_optab
->start
= optab
;
2659 /* Initialize reg_hash hash table. */
2660 reg_hash
= hash_new ();
2662 const reg_entry
*regtab
;
2663 unsigned int regtab_size
= i386_regtab_size
;
2665 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2667 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2669 as_fatal (_("can't hash %s: %s"),
2675 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2680 for (c
= 0; c
< 256; c
++)
2685 mnemonic_chars
[c
] = c
;
2686 register_chars
[c
] = c
;
2687 operand_chars
[c
] = c
;
2689 else if (ISLOWER (c
))
2691 mnemonic_chars
[c
] = c
;
2692 register_chars
[c
] = c
;
2693 operand_chars
[c
] = c
;
2695 else if (ISUPPER (c
))
2697 mnemonic_chars
[c
] = TOLOWER (c
);
2698 register_chars
[c
] = mnemonic_chars
[c
];
2699 operand_chars
[c
] = c
;
2701 else if (c
== '{' || c
== '}')
2703 mnemonic_chars
[c
] = c
;
2704 operand_chars
[c
] = c
;
2707 if (ISALPHA (c
) || ISDIGIT (c
))
2708 identifier_chars
[c
] = c
;
2711 identifier_chars
[c
] = c
;
2712 operand_chars
[c
] = c
;
2717 identifier_chars
['@'] = '@';
2720 identifier_chars
['?'] = '?';
2721 operand_chars
['?'] = '?';
2723 digit_chars
['-'] = '-';
2724 mnemonic_chars
['_'] = '_';
2725 mnemonic_chars
['-'] = '-';
2726 mnemonic_chars
['.'] = '.';
2727 identifier_chars
['_'] = '_';
2728 identifier_chars
['.'] = '.';
2730 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2731 operand_chars
[(unsigned char) *p
] = *p
;
2734 if (flag_code
== CODE_64BIT
)
2736 #if defined (OBJ_COFF) && defined (TE_PE)
2737 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2740 x86_dwarf2_return_column
= 16;
2742 x86_cie_data_alignment
= -8;
2746 x86_dwarf2_return_column
= 8;
2747 x86_cie_data_alignment
= -4;
2752 i386_print_statistics (FILE *file
)
2754 hash_print_statistics (file
, "i386 opcode", op_hash
);
2755 hash_print_statistics (file
, "i386 register", reg_hash
);
2760 /* Debugging routines for md_assemble. */
2761 static void pte (insn_template
*);
2762 static void pt (i386_operand_type
);
2763 static void pe (expressionS
*);
2764 static void ps (symbolS
*);
2767 pi (char *line
, i386_insn
*x
)
2771 fprintf (stdout
, "%s: template ", line
);
2773 fprintf (stdout
, " address: base %s index %s scale %x\n",
2774 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2775 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2776 x
->log2_scale_factor
);
2777 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2778 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2779 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2780 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2781 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2782 (x
->rex
& REX_W
) != 0,
2783 (x
->rex
& REX_R
) != 0,
2784 (x
->rex
& REX_X
) != 0,
2785 (x
->rex
& REX_B
) != 0);
2786 for (j
= 0; j
< x
->operands
; j
++)
2788 fprintf (stdout
, " #%d: ", j
+ 1);
2790 fprintf (stdout
, "\n");
2791 if (x
->types
[j
].bitfield
.reg8
2792 || x
->types
[j
].bitfield
.reg16
2793 || x
->types
[j
].bitfield
.reg32
2794 || x
->types
[j
].bitfield
.reg64
2795 || x
->types
[j
].bitfield
.regmmx
2796 || x
->types
[j
].bitfield
.regxmm
2797 || x
->types
[j
].bitfield
.regymm
2798 || x
->types
[j
].bitfield
.regzmm
2799 || x
->types
[j
].bitfield
.sreg2
2800 || x
->types
[j
].bitfield
.sreg3
2801 || x
->types
[j
].bitfield
.control
2802 || x
->types
[j
].bitfield
.debug
2803 || x
->types
[j
].bitfield
.test
)
2804 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2805 if (operand_type_check (x
->types
[j
], imm
))
2807 if (operand_type_check (x
->types
[j
], disp
))
2808 pe (x
->op
[j
].disps
);
2813 pte (insn_template
*t
)
2816 fprintf (stdout
, " %d operands ", t
->operands
);
2817 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2818 if (t
->extension_opcode
!= None
)
2819 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2820 if (t
->opcode_modifier
.d
)
2821 fprintf (stdout
, "D");
2822 if (t
->opcode_modifier
.w
)
2823 fprintf (stdout
, "W");
2824 fprintf (stdout
, "\n");
2825 for (j
= 0; j
< t
->operands
; j
++)
2827 fprintf (stdout
, " #%d type ", j
+ 1);
2828 pt (t
->operand_types
[j
]);
2829 fprintf (stdout
, "\n");
2836 fprintf (stdout
, " operation %d\n", e
->X_op
);
2837 fprintf (stdout
, " add_number %ld (%lx)\n",
2838 (long) e
->X_add_number
, (long) e
->X_add_number
);
2839 if (e
->X_add_symbol
)
2841 fprintf (stdout
, " add_symbol ");
2842 ps (e
->X_add_symbol
);
2843 fprintf (stdout
, "\n");
2847 fprintf (stdout
, " op_symbol ");
2848 ps (e
->X_op_symbol
);
2849 fprintf (stdout
, "\n");
2856 fprintf (stdout
, "%s type %s%s",
2858 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2859 segment_name (S_GET_SEGMENT (s
)));
2862 static struct type_name
2864 i386_operand_type mask
;
2867 const type_names
[] =
2869 { OPERAND_TYPE_REG8
, "r8" },
2870 { OPERAND_TYPE_REG16
, "r16" },
2871 { OPERAND_TYPE_REG32
, "r32" },
2872 { OPERAND_TYPE_REG64
, "r64" },
2873 { OPERAND_TYPE_IMM8
, "i8" },
2874 { OPERAND_TYPE_IMM8
, "i8s" },
2875 { OPERAND_TYPE_IMM16
, "i16" },
2876 { OPERAND_TYPE_IMM32
, "i32" },
2877 { OPERAND_TYPE_IMM32S
, "i32s" },
2878 { OPERAND_TYPE_IMM64
, "i64" },
2879 { OPERAND_TYPE_IMM1
, "i1" },
2880 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2881 { OPERAND_TYPE_DISP8
, "d8" },
2882 { OPERAND_TYPE_DISP16
, "d16" },
2883 { OPERAND_TYPE_DISP32
, "d32" },
2884 { OPERAND_TYPE_DISP32S
, "d32s" },
2885 { OPERAND_TYPE_DISP64
, "d64" },
2886 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2887 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2888 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2889 { OPERAND_TYPE_CONTROL
, "control reg" },
2890 { OPERAND_TYPE_TEST
, "test reg" },
2891 { OPERAND_TYPE_DEBUG
, "debug reg" },
2892 { OPERAND_TYPE_FLOATREG
, "FReg" },
2893 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2894 { OPERAND_TYPE_SREG2
, "SReg2" },
2895 { OPERAND_TYPE_SREG3
, "SReg3" },
2896 { OPERAND_TYPE_ACC
, "Acc" },
2897 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2898 { OPERAND_TYPE_REGMMX
, "rMMX" },
2899 { OPERAND_TYPE_REGXMM
, "rXMM" },
2900 { OPERAND_TYPE_REGYMM
, "rYMM" },
2901 { OPERAND_TYPE_REGZMM
, "rZMM" },
2902 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2903 { OPERAND_TYPE_ESSEG
, "es" },
2907 pt (i386_operand_type t
)
2910 i386_operand_type a
;
2912 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2914 a
= operand_type_and (t
, type_names
[j
].mask
);
2915 if (!operand_type_all_zero (&a
))
2916 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2921 #endif /* DEBUG386 */
2923 static bfd_reloc_code_real_type
2924 reloc (unsigned int size
,
2927 bfd_reloc_code_real_type other
)
2929 if (other
!= NO_RELOC
)
2931 reloc_howto_type
*rel
;
2936 case BFD_RELOC_X86_64_GOT32
:
2937 return BFD_RELOC_X86_64_GOT64
;
2939 case BFD_RELOC_X86_64_GOTPLT64
:
2940 return BFD_RELOC_X86_64_GOTPLT64
;
2942 case BFD_RELOC_X86_64_PLTOFF64
:
2943 return BFD_RELOC_X86_64_PLTOFF64
;
2945 case BFD_RELOC_X86_64_GOTPC32
:
2946 other
= BFD_RELOC_X86_64_GOTPC64
;
2948 case BFD_RELOC_X86_64_GOTPCREL
:
2949 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2951 case BFD_RELOC_X86_64_TPOFF32
:
2952 other
= BFD_RELOC_X86_64_TPOFF64
;
2954 case BFD_RELOC_X86_64_DTPOFF32
:
2955 other
= BFD_RELOC_X86_64_DTPOFF64
;
2961 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2962 if (other
== BFD_RELOC_SIZE32
)
2965 other
= BFD_RELOC_SIZE64
;
2968 as_bad (_("there are no pc-relative size relocations"));
2974 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2975 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2978 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2980 as_bad (_("unknown relocation (%u)"), other
);
2981 else if (size
!= bfd_get_reloc_size (rel
))
2982 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2983 bfd_get_reloc_size (rel
),
2985 else if (pcrel
&& !rel
->pc_relative
)
2986 as_bad (_("non-pc-relative relocation for pc-relative field"));
2987 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2989 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2991 as_bad (_("relocated field and relocation type differ in signedness"));
3000 as_bad (_("there are no unsigned pc-relative relocations"));
3003 case 1: return BFD_RELOC_8_PCREL
;
3004 case 2: return BFD_RELOC_16_PCREL
;
3005 case 4: return BFD_RELOC_32_PCREL
;
3006 case 8: return BFD_RELOC_64_PCREL
;
3008 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3015 case 4: return BFD_RELOC_X86_64_32S
;
3020 case 1: return BFD_RELOC_8
;
3021 case 2: return BFD_RELOC_16
;
3022 case 4: return BFD_RELOC_32
;
3023 case 8: return BFD_RELOC_64
;
3025 as_bad (_("cannot do %s %u byte relocation"),
3026 sign
> 0 ? "signed" : "unsigned", size
);
3032 /* Here we decide which fixups can be adjusted to make them relative to
3033 the beginning of the section instead of the symbol. Basically we need
3034 to make sure that the dynamic relocations are done correctly, so in
3035 some cases we force the original symbol to be used. */
3038 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3040 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3044 /* Don't adjust pc-relative references to merge sections in 64-bit
3046 if (use_rela_relocations
3047 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3051 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3052 and changed later by validate_fix. */
3053 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3054 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3057 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3058 for size relocations. */
3059 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3060 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3061 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3062 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3063 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3064 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3065 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3066 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3067 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3068 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3069 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3070 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3071 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3072 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3073 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3074 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3075 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3076 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3077 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3078 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3079 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3080 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3081 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3082 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3083 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3084 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3085 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3086 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3087 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3088 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3089 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3090 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3091 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3098 intel_float_operand (const char *mnemonic
)
3100 /* Note that the value returned is meaningful only for opcodes with (memory)
3101 operands, hence the code here is free to improperly handle opcodes that
3102 have no operands (for better performance and smaller code). */
3104 if (mnemonic
[0] != 'f')
3105 return 0; /* non-math */
3107 switch (mnemonic
[1])
3109 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3110 the fs segment override prefix not currently handled because no
3111 call path can make opcodes without operands get here */
3113 return 2 /* integer op */;
3115 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3116 return 3; /* fldcw/fldenv */
3119 if (mnemonic
[2] != 'o' /* fnop */)
3120 return 3; /* non-waiting control op */
3123 if (mnemonic
[2] == 's')
3124 return 3; /* frstor/frstpm */
3127 if (mnemonic
[2] == 'a')
3128 return 3; /* fsave */
3129 if (mnemonic
[2] == 't')
3131 switch (mnemonic
[3])
3133 case 'c': /* fstcw */
3134 case 'd': /* fstdw */
3135 case 'e': /* fstenv */
3136 case 's': /* fsts[gw] */
3142 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3143 return 0; /* fxsave/fxrstor are not really math ops */
3150 /* Build the VEX prefix. */
3153 build_vex_prefix (const insn_template
*t
)
3155 unsigned int register_specifier
;
3156 unsigned int implied_prefix
;
3157 unsigned int vector_length
;
3159 /* Check register specifier. */
3160 if (i
.vex
.register_specifier
)
3162 register_specifier
=
3163 ~register_number (i
.vex
.register_specifier
) & 0xf;
3164 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3167 register_specifier
= 0xf;
3169 /* Use 2-byte VEX prefix by swapping destination and source
3171 if (i
.vec_encoding
!= vex_encoding_vex3
3172 && i
.dir_encoding
== dir_encoding_default
3173 && i
.operands
== i
.reg_operands
3174 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3175 && i
.tm
.opcode_modifier
.load
3178 unsigned int xchg
= i
.operands
- 1;
3179 union i386_op temp_op
;
3180 i386_operand_type temp_type
;
3182 temp_type
= i
.types
[xchg
];
3183 i
.types
[xchg
] = i
.types
[0];
3184 i
.types
[0] = temp_type
;
3185 temp_op
= i
.op
[xchg
];
3186 i
.op
[xchg
] = i
.op
[0];
3189 gas_assert (i
.rm
.mode
== 3);
3193 i
.rm
.regmem
= i
.rm
.reg
;
3196 /* Use the next insn. */
3200 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3201 vector_length
= avxscalar
;
3203 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3205 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3210 case DATA_PREFIX_OPCODE
:
3213 case REPE_PREFIX_OPCODE
:
3216 case REPNE_PREFIX_OPCODE
:
3223 /* Use 2-byte VEX prefix if possible. */
3224 if (i
.vec_encoding
!= vex_encoding_vex3
3225 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3226 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3227 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3229 /* 2-byte VEX prefix. */
3233 i
.vex
.bytes
[0] = 0xc5;
3235 /* Check the REX.R bit. */
3236 r
= (i
.rex
& REX_R
) ? 0 : 1;
3237 i
.vex
.bytes
[1] = (r
<< 7
3238 | register_specifier
<< 3
3239 | vector_length
<< 2
3244 /* 3-byte VEX prefix. */
3249 switch (i
.tm
.opcode_modifier
.vexopcode
)
3253 i
.vex
.bytes
[0] = 0xc4;
3257 i
.vex
.bytes
[0] = 0xc4;
3261 i
.vex
.bytes
[0] = 0xc4;
3265 i
.vex
.bytes
[0] = 0x8f;
3269 i
.vex
.bytes
[0] = 0x8f;
3273 i
.vex
.bytes
[0] = 0x8f;
3279 /* The high 3 bits of the second VEX byte are 1's compliment
3280 of RXB bits from REX. */
3281 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3283 /* Check the REX.W bit. */
3284 w
= (i
.rex
& REX_W
) ? 1 : 0;
3285 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3288 i
.vex
.bytes
[2] = (w
<< 7
3289 | register_specifier
<< 3
3290 | vector_length
<< 2
3295 /* Build the EVEX prefix. */
3298 build_evex_prefix (void)
3300 unsigned int register_specifier
;
3301 unsigned int implied_prefix
;
3303 rex_byte vrex_used
= 0;
3305 /* Check register specifier. */
3306 if (i
.vex
.register_specifier
)
3308 gas_assert ((i
.vrex
& REX_X
) == 0);
3310 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3311 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3312 register_specifier
+= 8;
3313 /* The upper 16 registers are encoded in the fourth byte of the
3315 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3316 i
.vex
.bytes
[3] = 0x8;
3317 register_specifier
= ~register_specifier
& 0xf;
3321 register_specifier
= 0xf;
3323 /* Encode upper 16 vector index register in the fourth byte of
3325 if (!(i
.vrex
& REX_X
))
3326 i
.vex
.bytes
[3] = 0x8;
3331 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3336 case DATA_PREFIX_OPCODE
:
3339 case REPE_PREFIX_OPCODE
:
3342 case REPNE_PREFIX_OPCODE
:
3349 /* 4 byte EVEX prefix. */
3351 i
.vex
.bytes
[0] = 0x62;
3354 switch (i
.tm
.opcode_modifier
.vexopcode
)
3370 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3372 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3374 /* The fifth bit of the second EVEX byte is 1's compliment of the
3375 REX_R bit in VREX. */
3376 if (!(i
.vrex
& REX_R
))
3377 i
.vex
.bytes
[1] |= 0x10;
3381 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3383 /* When all operands are registers, the REX_X bit in REX is not
3384 used. We reuse it to encode the upper 16 registers, which is
3385 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3386 as 1's compliment. */
3387 if ((i
.vrex
& REX_B
))
3390 i
.vex
.bytes
[1] &= ~0x40;
3394 /* EVEX instructions shouldn't need the REX prefix. */
3395 i
.vrex
&= ~vrex_used
;
3396 gas_assert (i
.vrex
== 0);
3398 /* Check the REX.W bit. */
3399 w
= (i
.rex
& REX_W
) ? 1 : 0;
3400 if (i
.tm
.opcode_modifier
.vexw
)
3402 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3405 /* If w is not set it means we are dealing with WIG instruction. */
3408 if (evexwig
== evexw1
)
3412 /* Encode the U bit. */
3413 implied_prefix
|= 0x4;
3415 /* The third byte of the EVEX prefix. */
3416 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3418 /* The fourth byte of the EVEX prefix. */
3419 /* The zeroing-masking bit. */
3420 if (i
.mask
&& i
.mask
->zeroing
)
3421 i
.vex
.bytes
[3] |= 0x80;
3423 /* Don't always set the broadcast bit if there is no RC. */
3426 /* Encode the vector length. */
3427 unsigned int vec_length
;
3429 switch (i
.tm
.opcode_modifier
.evex
)
3431 case EVEXLIG
: /* LL' is ignored */
3432 vec_length
= evexlig
<< 5;
3435 vec_length
= 0 << 5;
3438 vec_length
= 1 << 5;
3441 vec_length
= 2 << 5;
3447 i
.vex
.bytes
[3] |= vec_length
;
3448 /* Encode the broadcast bit. */
3450 i
.vex
.bytes
[3] |= 0x10;
3454 if (i
.rounding
->type
!= saeonly
)
3455 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3457 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3460 if (i
.mask
&& i
.mask
->mask
)
3461 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3465 process_immext (void)
3469 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3472 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3473 with an opcode suffix which is coded in the same place as an
3474 8-bit immediate field would be.
3475 Here we check those operands and remove them afterwards. */
3478 for (x
= 0; x
< i
.operands
; x
++)
3479 if (register_number (i
.op
[x
].regs
) != x
)
3480 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3481 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3487 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3489 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3490 suffix which is coded in the same place as an 8-bit immediate
3492 Here we check those operands and remove them afterwards. */
3495 if (i
.operands
!= 3)
3498 for (x
= 0; x
< 2; x
++)
3499 if (register_number (i
.op
[x
].regs
) != x
)
3500 goto bad_register_operand
;
3502 /* Check for third operand for mwaitx/monitorx insn. */
3503 if (register_number (i
.op
[x
].regs
)
3504 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3506 bad_register_operand
:
3507 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3508 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3515 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3516 which is coded in the same place as an 8-bit immediate field
3517 would be. Here we fake an 8-bit immediate operand from the
3518 opcode suffix stored in tm.extension_opcode.
3520 AVX instructions also use this encoding, for some of
3521 3 argument instructions. */
3523 gas_assert (i
.imm_operands
<= 1
3525 || ((i
.tm
.opcode_modifier
.vex
3526 || i
.tm
.opcode_modifier
.evex
)
3527 && i
.operands
<= 4)));
3529 exp
= &im_expressions
[i
.imm_operands
++];
3530 i
.op
[i
.operands
].imms
= exp
;
3531 i
.types
[i
.operands
] = imm8
;
3533 exp
->X_op
= O_constant
;
3534 exp
->X_add_number
= i
.tm
.extension_opcode
;
3535 i
.tm
.extension_opcode
= None
;
3542 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3547 as_bad (_("invalid instruction `%s' after `%s'"),
3548 i
.tm
.name
, i
.hle_prefix
);
3551 if (i
.prefix
[LOCK_PREFIX
])
3553 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3557 case HLEPrefixRelease
:
3558 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3560 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3564 if (i
.mem_operands
== 0
3565 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3567 as_bad (_("memory destination needed for instruction `%s'"
3568 " after `xrelease'"), i
.tm
.name
);
3575 /* This is the guts of the machine-dependent assembler. LINE points to a
3576 machine dependent instruction. This function is supposed to emit
3577 the frags/bytes it assembles to. */
3580 md_assemble (char *line
)
3583 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
3584 const insn_template
*t
;
3586 /* Initialize globals. */
3587 memset (&i
, '\0', sizeof (i
));
3588 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3589 i
.reloc
[j
] = NO_RELOC
;
3590 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3591 memset (im_expressions
, '\0', sizeof (im_expressions
));
3592 save_stack_p
= save_stack
;
3594 /* First parse an instruction mnemonic & call i386_operand for the operands.
3595 We assume that the scrubber has arranged it so that line[0] is the valid
3596 start of a (possibly prefixed) mnemonic. */
3598 line
= parse_insn (line
, mnemonic
);
3601 mnem_suffix
= i
.suffix
;
3603 line
= parse_operands (line
, mnemonic
);
3605 xfree (i
.memop1_string
);
3606 i
.memop1_string
= NULL
;
3610 /* Now we've parsed the mnemonic into a set of templates, and have the
3611 operands at hand. */
3613 /* All intel opcodes have reversed operands except for "bound" and
3614 "enter". We also don't reverse intersegment "jmp" and "call"
3615 instructions with 2 immediate operands so that the immediate segment
3616 precedes the offset, as it does when in AT&T mode. */
3619 && (strcmp (mnemonic
, "bound") != 0)
3620 && (strcmp (mnemonic
, "invlpga") != 0)
3621 && !(operand_type_check (i
.types
[0], imm
)
3622 && operand_type_check (i
.types
[1], imm
)))
3625 /* The order of the immediates should be reversed
3626 for 2 immediates extrq and insertq instructions */
3627 if (i
.imm_operands
== 2
3628 && (strcmp (mnemonic
, "extrq") == 0
3629 || strcmp (mnemonic
, "insertq") == 0))
3630 swap_2_operands (0, 1);
3635 /* Don't optimize displacement for movabs since it only takes 64bit
3638 && i
.disp_encoding
!= disp_encoding_32bit
3639 && (flag_code
!= CODE_64BIT
3640 || strcmp (mnemonic
, "movabs") != 0))
3643 /* Next, we find a template that matches the given insn,
3644 making sure the overlap of the given operands types is consistent
3645 with the template operand types. */
3647 if (!(t
= match_template (mnem_suffix
)))
3650 if (sse_check
!= check_none
3651 && !i
.tm
.opcode_modifier
.noavx
3652 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3653 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3654 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3655 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3656 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3657 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3659 (sse_check
== check_warning
3661 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3664 /* Zap movzx and movsx suffix. The suffix has been set from
3665 "word ptr" or "byte ptr" on the source operand in Intel syntax
3666 or extracted from mnemonic in AT&T syntax. But we'll use
3667 the destination register to choose the suffix for encoding. */
3668 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3670 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3671 there is no suffix, the default will be byte extension. */
3672 if (i
.reg_operands
!= 2
3675 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3680 if (i
.tm
.opcode_modifier
.fwait
)
3681 if (!add_prefix (FWAIT_OPCODE
))
3684 /* Check if REP prefix is OK. */
3685 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3687 as_bad (_("invalid instruction `%s' after `%s'"),
3688 i
.tm
.name
, i
.rep_prefix
);
3692 /* Check for lock without a lockable instruction. Destination operand
3693 must be memory unless it is xchg (0x86). */
3694 if (i
.prefix
[LOCK_PREFIX
]
3695 && (!i
.tm
.opcode_modifier
.islockable
3696 || i
.mem_operands
== 0
3697 || (i
.tm
.base_opcode
!= 0x86
3698 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3700 as_bad (_("expecting lockable instruction after `lock'"));
3704 /* Check if HLE prefix is OK. */
3705 if (i
.hle_prefix
&& !check_hle ())
3708 /* Check BND prefix. */
3709 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3710 as_bad (_("expecting valid branch instruction after `bnd'"));
3712 /* Check NOTRACK prefix. */
3713 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
3714 as_bad (_("expecting indirect branch instruction after `notrack'"));
3716 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
3718 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
3719 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3720 else if (flag_code
!= CODE_16BIT
3721 ? i
.prefix
[ADDR_PREFIX
]
3722 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
3723 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3726 /* Insert BND prefix. */
3728 && i
.tm
.opcode_modifier
.bndprefixok
3729 && !i
.prefix
[BND_PREFIX
])
3730 add_prefix (BND_PREFIX_OPCODE
);
3732 /* Check string instruction segment overrides. */
3733 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3735 if (!check_string ())
3737 i
.disp_operands
= 0;
3740 if (!process_suffix ())
3743 /* Update operand types. */
3744 for (j
= 0; j
< i
.operands
; j
++)
3745 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3747 /* Make still unresolved immediate matches conform to size of immediate
3748 given in i.suffix. */
3749 if (!finalize_imm ())
3752 if (i
.types
[0].bitfield
.imm1
)
3753 i
.imm_operands
= 0; /* kludge for shift insns. */
3755 /* We only need to check those implicit registers for instructions
3756 with 3 operands or less. */
3757 if (i
.operands
<= 3)
3758 for (j
= 0; j
< i
.operands
; j
++)
3759 if (i
.types
[j
].bitfield
.inoutportreg
3760 || i
.types
[j
].bitfield
.shiftcount
3761 || i
.types
[j
].bitfield
.acc
3762 || i
.types
[j
].bitfield
.floatacc
)
3765 /* ImmExt should be processed after SSE2AVX. */
3766 if (!i
.tm
.opcode_modifier
.sse2avx
3767 && i
.tm
.opcode_modifier
.immext
)
3770 /* For insns with operands there are more diddles to do to the opcode. */
3773 if (!process_operands ())
3776 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3778 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3779 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3782 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3784 if (flag_code
== CODE_16BIT
)
3786 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3791 if (i
.tm
.opcode_modifier
.vex
)
3792 build_vex_prefix (t
);
3794 build_evex_prefix ();
3797 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3798 instructions may define INT_OPCODE as well, so avoid this corner
3799 case for those instructions that use MODRM. */
3800 if (i
.tm
.base_opcode
== INT_OPCODE
3801 && !i
.tm
.opcode_modifier
.modrm
3802 && i
.op
[0].imms
->X_add_number
== 3)
3804 i
.tm
.base_opcode
= INT3_OPCODE
;
3808 if ((i
.tm
.opcode_modifier
.jump
3809 || i
.tm
.opcode_modifier
.jumpbyte
3810 || i
.tm
.opcode_modifier
.jumpdword
)
3811 && i
.op
[0].disps
->X_op
== O_constant
)
3813 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3814 the absolute address given by the constant. Since ix86 jumps and
3815 calls are pc relative, we need to generate a reloc. */
3816 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3817 i
.op
[0].disps
->X_op
= O_symbol
;
3820 if (i
.tm
.opcode_modifier
.rex64
)
3823 /* For 8 bit registers we need an empty rex prefix. Also if the
3824 instruction already has a prefix, we need to convert old
3825 registers to new ones. */
3827 if ((i
.types
[0].bitfield
.reg8
3828 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3829 || (i
.types
[1].bitfield
.reg8
3830 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3831 || ((i
.types
[0].bitfield
.reg8
3832 || i
.types
[1].bitfield
.reg8
)
3837 i
.rex
|= REX_OPCODE
;
3838 for (x
= 0; x
< 2; x
++)
3840 /* Look for 8 bit operand that uses old registers. */
3841 if (i
.types
[x
].bitfield
.reg8
3842 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3844 /* In case it is "hi" register, give up. */
3845 if (i
.op
[x
].regs
->reg_num
> 3)
3846 as_bad (_("can't encode register '%s%s' in an "
3847 "instruction requiring REX prefix."),
3848 register_prefix
, i
.op
[x
].regs
->reg_name
);
3850 /* Otherwise it is equivalent to the extended register.
3851 Since the encoding doesn't change this is merely
3852 cosmetic cleanup for debug output. */
3854 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3860 add_prefix (REX_OPCODE
| i
.rex
);
3862 /* We are ready to output the insn. */
3867 parse_insn (char *line
, char *mnemonic
)
3870 char *token_start
= l
;
3873 const insn_template
*t
;
3879 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3884 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3886 as_bad (_("no such instruction: `%s'"), token_start
);
3891 if (!is_space_char (*l
)
3892 && *l
!= END_OF_INSN
3894 || (*l
!= PREFIX_SEPARATOR
3897 as_bad (_("invalid character %s in mnemonic"),
3898 output_invalid (*l
));
3901 if (token_start
== l
)
3903 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3904 as_bad (_("expecting prefix; got nothing"));
3906 as_bad (_("expecting mnemonic; got nothing"));
3910 /* Look up instruction (or prefix) via hash table. */
3911 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3913 if (*l
!= END_OF_INSN
3914 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3915 && current_templates
3916 && current_templates
->start
->opcode_modifier
.isprefix
)
3918 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3920 as_bad ((flag_code
!= CODE_64BIT
3921 ? _("`%s' is only supported in 64-bit mode")
3922 : _("`%s' is not supported in 64-bit mode")),
3923 current_templates
->start
->name
);
3926 /* If we are in 16-bit mode, do not allow addr16 or data16.
3927 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3928 if ((current_templates
->start
->opcode_modifier
.size16
3929 || current_templates
->start
->opcode_modifier
.size32
)
3930 && flag_code
!= CODE_64BIT
3931 && (current_templates
->start
->opcode_modifier
.size32
3932 ^ (flag_code
== CODE_16BIT
)))
3934 as_bad (_("redundant %s prefix"),
3935 current_templates
->start
->name
);
3938 if (current_templates
->start
->opcode_length
== 0)
3940 /* Handle pseudo prefixes. */
3941 switch (current_templates
->start
->base_opcode
)
3945 i
.disp_encoding
= disp_encoding_8bit
;
3949 i
.disp_encoding
= disp_encoding_32bit
;
3953 i
.dir_encoding
= dir_encoding_load
;
3957 i
.dir_encoding
= dir_encoding_store
;
3961 i
.vec_encoding
= vex_encoding_vex2
;
3965 i
.vec_encoding
= vex_encoding_vex3
;
3969 i
.vec_encoding
= vex_encoding_evex
;
3977 /* Add prefix, checking for repeated prefixes. */
3978 switch (add_prefix (current_templates
->start
->base_opcode
))
3983 if (current_templates
->start
->cpu_flags
.bitfield
.cpucet
)
3984 i
.notrack_prefix
= current_templates
->start
->name
;
3987 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3988 i
.hle_prefix
= current_templates
->start
->name
;
3989 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3990 i
.bnd_prefix
= current_templates
->start
->name
;
3992 i
.rep_prefix
= current_templates
->start
->name
;
3998 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4005 if (!current_templates
)
4007 /* Check if we should swap operand or force 32bit displacement in
4009 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4010 i
.dir_encoding
= dir_encoding_store
;
4011 else if (mnem_p
- 3 == dot_p
4014 i
.disp_encoding
= disp_encoding_8bit
;
4015 else if (mnem_p
- 4 == dot_p
4019 i
.disp_encoding
= disp_encoding_32bit
;
4024 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4027 if (!current_templates
)
4030 /* See if we can get a match by trimming off a suffix. */
4033 case WORD_MNEM_SUFFIX
:
4034 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4035 i
.suffix
= SHORT_MNEM_SUFFIX
;
4038 case BYTE_MNEM_SUFFIX
:
4039 case QWORD_MNEM_SUFFIX
:
4040 i
.suffix
= mnem_p
[-1];
4042 current_templates
= (const templates
*) hash_find (op_hash
,
4045 case SHORT_MNEM_SUFFIX
:
4046 case LONG_MNEM_SUFFIX
:
4049 i
.suffix
= mnem_p
[-1];
4051 current_templates
= (const templates
*) hash_find (op_hash
,
4060 if (intel_float_operand (mnemonic
) == 1)
4061 i
.suffix
= SHORT_MNEM_SUFFIX
;
4063 i
.suffix
= LONG_MNEM_SUFFIX
;
4065 current_templates
= (const templates
*) hash_find (op_hash
,
4070 if (!current_templates
)
4072 as_bad (_("no such instruction: `%s'"), token_start
);
4077 if (current_templates
->start
->opcode_modifier
.jump
4078 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4080 /* Check for a branch hint. We allow ",pt" and ",pn" for
4081 predict taken and predict not taken respectively.
4082 I'm not sure that branch hints actually do anything on loop
4083 and jcxz insns (JumpByte) for current Pentium4 chips. They
4084 may work in the future and it doesn't hurt to accept them
4086 if (l
[0] == ',' && l
[1] == 'p')
4090 if (!add_prefix (DS_PREFIX_OPCODE
))
4094 else if (l
[2] == 'n')
4096 if (!add_prefix (CS_PREFIX_OPCODE
))
4102 /* Any other comma loses. */
4105 as_bad (_("invalid character %s in mnemonic"),
4106 output_invalid (*l
));
4110 /* Check if instruction is supported on specified architecture. */
4112 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4114 supported
|= cpu_flags_match (t
);
4115 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4119 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4121 as_bad (flag_code
== CODE_64BIT
4122 ? _("`%s' is not supported in 64-bit mode")
4123 : _("`%s' is only supported in 64-bit mode"),
4124 current_templates
->start
->name
);
4127 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
4129 as_bad (_("`%s' is not supported on `%s%s'"),
4130 current_templates
->start
->name
,
4131 cpu_arch_name
? cpu_arch_name
: default_arch
,
4132 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4137 if (!cpu_arch_flags
.bitfield
.cpui386
4138 && (flag_code
!= CODE_16BIT
))
4140 as_warn (_("use .code16 to ensure correct addressing mode"));
4147 parse_operands (char *l
, const char *mnemonic
)
4151 /* 1 if operand is pending after ','. */
4152 unsigned int expecting_operand
= 0;
4154 /* Non-zero if operand parens not balanced. */
4155 unsigned int paren_not_balanced
;
4157 while (*l
!= END_OF_INSN
)
4159 /* Skip optional white space before operand. */
4160 if (is_space_char (*l
))
4162 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4164 as_bad (_("invalid character %s before operand %d"),
4165 output_invalid (*l
),
4169 token_start
= l
; /* After white space. */
4170 paren_not_balanced
= 0;
4171 while (paren_not_balanced
|| *l
!= ',')
4173 if (*l
== END_OF_INSN
)
4175 if (paren_not_balanced
)
4178 as_bad (_("unbalanced parenthesis in operand %d."),
4181 as_bad (_("unbalanced brackets in operand %d."),
4186 break; /* we are done */
4188 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4190 as_bad (_("invalid character %s in operand %d"),
4191 output_invalid (*l
),
4198 ++paren_not_balanced
;
4200 --paren_not_balanced
;
4205 ++paren_not_balanced
;
4207 --paren_not_balanced
;
4211 if (l
!= token_start
)
4212 { /* Yes, we've read in another operand. */
4213 unsigned int operand_ok
;
4214 this_operand
= i
.operands
++;
4215 if (i
.operands
> MAX_OPERANDS
)
4217 as_bad (_("spurious operands; (%d operands/instruction max)"),
4221 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4222 /* Now parse operand adding info to 'i' as we go along. */
4223 END_STRING_AND_SAVE (l
);
4227 i386_intel_operand (token_start
,
4228 intel_float_operand (mnemonic
));
4230 operand_ok
= i386_att_operand (token_start
);
4232 RESTORE_END_STRING (l
);
4238 if (expecting_operand
)
4240 expecting_operand_after_comma
:
4241 as_bad (_("expecting operand after ','; got nothing"));
4246 as_bad (_("expecting operand before ','; got nothing"));
4251 /* Now *l must be either ',' or END_OF_INSN. */
4254 if (*++l
== END_OF_INSN
)
4256 /* Just skip it, if it's \n complain. */
4257 goto expecting_operand_after_comma
;
4259 expecting_operand
= 1;
4266 swap_2_operands (int xchg1
, int xchg2
)
4268 union i386_op temp_op
;
4269 i386_operand_type temp_type
;
4270 enum bfd_reloc_code_real temp_reloc
;
4272 temp_type
= i
.types
[xchg2
];
4273 i
.types
[xchg2
] = i
.types
[xchg1
];
4274 i
.types
[xchg1
] = temp_type
;
4275 temp_op
= i
.op
[xchg2
];
4276 i
.op
[xchg2
] = i
.op
[xchg1
];
4277 i
.op
[xchg1
] = temp_op
;
4278 temp_reloc
= i
.reloc
[xchg2
];
4279 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4280 i
.reloc
[xchg1
] = temp_reloc
;
4284 if (i
.mask
->operand
== xchg1
)
4285 i
.mask
->operand
= xchg2
;
4286 else if (i
.mask
->operand
== xchg2
)
4287 i
.mask
->operand
= xchg1
;
4291 if (i
.broadcast
->operand
== xchg1
)
4292 i
.broadcast
->operand
= xchg2
;
4293 else if (i
.broadcast
->operand
== xchg2
)
4294 i
.broadcast
->operand
= xchg1
;
4298 if (i
.rounding
->operand
== xchg1
)
4299 i
.rounding
->operand
= xchg2
;
4300 else if (i
.rounding
->operand
== xchg2
)
4301 i
.rounding
->operand
= xchg1
;
4306 swap_operands (void)
4312 swap_2_operands (1, i
.operands
- 2);
4316 swap_2_operands (0, i
.operands
- 1);
4322 if (i
.mem_operands
== 2)
4324 const seg_entry
*temp_seg
;
4325 temp_seg
= i
.seg
[0];
4326 i
.seg
[0] = i
.seg
[1];
4327 i
.seg
[1] = temp_seg
;
4331 /* Try to ensure constant immediates are represented in the smallest
4336 char guess_suffix
= 0;
4340 guess_suffix
= i
.suffix
;
4341 else if (i
.reg_operands
)
4343 /* Figure out a suffix from the last register operand specified.
4344 We can't do this properly yet, ie. excluding InOutPortReg,
4345 but the following works for instructions with immediates.
4346 In any case, we can't set i.suffix yet. */
4347 for (op
= i
.operands
; --op
>= 0;)
4348 if (i
.types
[op
].bitfield
.reg8
)
4350 guess_suffix
= BYTE_MNEM_SUFFIX
;
4353 else if (i
.types
[op
].bitfield
.reg16
)
4355 guess_suffix
= WORD_MNEM_SUFFIX
;
4358 else if (i
.types
[op
].bitfield
.reg32
)
4360 guess_suffix
= LONG_MNEM_SUFFIX
;
4363 else if (i
.types
[op
].bitfield
.reg64
)
4365 guess_suffix
= QWORD_MNEM_SUFFIX
;
4369 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4370 guess_suffix
= WORD_MNEM_SUFFIX
;
4372 for (op
= i
.operands
; --op
>= 0;)
4373 if (operand_type_check (i
.types
[op
], imm
))
4375 switch (i
.op
[op
].imms
->X_op
)
4378 /* If a suffix is given, this operand may be shortened. */
4379 switch (guess_suffix
)
4381 case LONG_MNEM_SUFFIX
:
4382 i
.types
[op
].bitfield
.imm32
= 1;
4383 i
.types
[op
].bitfield
.imm64
= 1;
4385 case WORD_MNEM_SUFFIX
:
4386 i
.types
[op
].bitfield
.imm16
= 1;
4387 i
.types
[op
].bitfield
.imm32
= 1;
4388 i
.types
[op
].bitfield
.imm32s
= 1;
4389 i
.types
[op
].bitfield
.imm64
= 1;
4391 case BYTE_MNEM_SUFFIX
:
4392 i
.types
[op
].bitfield
.imm8
= 1;
4393 i
.types
[op
].bitfield
.imm8s
= 1;
4394 i
.types
[op
].bitfield
.imm16
= 1;
4395 i
.types
[op
].bitfield
.imm32
= 1;
4396 i
.types
[op
].bitfield
.imm32s
= 1;
4397 i
.types
[op
].bitfield
.imm64
= 1;
4401 /* If this operand is at most 16 bits, convert it
4402 to a signed 16 bit number before trying to see
4403 whether it will fit in an even smaller size.
4404 This allows a 16-bit operand such as $0xffe0 to
4405 be recognised as within Imm8S range. */
4406 if ((i
.types
[op
].bitfield
.imm16
)
4407 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4409 i
.op
[op
].imms
->X_add_number
=
4410 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4413 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4414 if ((i
.types
[op
].bitfield
.imm32
)
4415 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4418 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4419 ^ ((offsetT
) 1 << 31))
4420 - ((offsetT
) 1 << 31));
4424 = operand_type_or (i
.types
[op
],
4425 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4427 /* We must avoid matching of Imm32 templates when 64bit
4428 only immediate is available. */
4429 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4430 i
.types
[op
].bitfield
.imm32
= 0;
4437 /* Symbols and expressions. */
4439 /* Convert symbolic operand to proper sizes for matching, but don't
4440 prevent matching a set of insns that only supports sizes other
4441 than those matching the insn suffix. */
4443 i386_operand_type mask
, allowed
;
4444 const insn_template
*t
;
4446 operand_type_set (&mask
, 0);
4447 operand_type_set (&allowed
, 0);
4449 for (t
= current_templates
->start
;
4450 t
< current_templates
->end
;
4452 allowed
= operand_type_or (allowed
,
4453 t
->operand_types
[op
]);
4454 switch (guess_suffix
)
4456 case QWORD_MNEM_SUFFIX
:
4457 mask
.bitfield
.imm64
= 1;
4458 mask
.bitfield
.imm32s
= 1;
4460 case LONG_MNEM_SUFFIX
:
4461 mask
.bitfield
.imm32
= 1;
4463 case WORD_MNEM_SUFFIX
:
4464 mask
.bitfield
.imm16
= 1;
4466 case BYTE_MNEM_SUFFIX
:
4467 mask
.bitfield
.imm8
= 1;
4472 allowed
= operand_type_and (mask
, allowed
);
4473 if (!operand_type_all_zero (&allowed
))
4474 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4481 /* Try to use the smallest displacement type too. */
4483 optimize_disp (void)
4487 for (op
= i
.operands
; --op
>= 0;)
4488 if (operand_type_check (i
.types
[op
], disp
))
4490 if (i
.op
[op
].disps
->X_op
== O_constant
)
4492 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4494 if (i
.types
[op
].bitfield
.disp16
4495 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4497 /* If this operand is at most 16 bits, convert
4498 to a signed 16 bit number and don't use 64bit
4500 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4501 i
.types
[op
].bitfield
.disp64
= 0;
4504 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4505 if (i
.types
[op
].bitfield
.disp32
4506 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4508 /* If this operand is at most 32 bits, convert
4509 to a signed 32 bit number and don't use 64bit
4511 op_disp
&= (((offsetT
) 2 << 31) - 1);
4512 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4513 i
.types
[op
].bitfield
.disp64
= 0;
4516 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4518 i
.types
[op
].bitfield
.disp8
= 0;
4519 i
.types
[op
].bitfield
.disp16
= 0;
4520 i
.types
[op
].bitfield
.disp32
= 0;
4521 i
.types
[op
].bitfield
.disp32s
= 0;
4522 i
.types
[op
].bitfield
.disp64
= 0;
4526 else if (flag_code
== CODE_64BIT
)
4528 if (fits_in_signed_long (op_disp
))
4530 i
.types
[op
].bitfield
.disp64
= 0;
4531 i
.types
[op
].bitfield
.disp32s
= 1;
4533 if (i
.prefix
[ADDR_PREFIX
]
4534 && fits_in_unsigned_long (op_disp
))
4535 i
.types
[op
].bitfield
.disp32
= 1;
4537 if ((i
.types
[op
].bitfield
.disp32
4538 || i
.types
[op
].bitfield
.disp32s
4539 || i
.types
[op
].bitfield
.disp16
)
4540 && fits_in_signed_byte (op_disp
))
4541 i
.types
[op
].bitfield
.disp8
= 1;
4543 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4544 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4546 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4547 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4548 i
.types
[op
].bitfield
.disp8
= 0;
4549 i
.types
[op
].bitfield
.disp16
= 0;
4550 i
.types
[op
].bitfield
.disp32
= 0;
4551 i
.types
[op
].bitfield
.disp32s
= 0;
4552 i
.types
[op
].bitfield
.disp64
= 0;
4555 /* We only support 64bit displacement on constants. */
4556 i
.types
[op
].bitfield
.disp64
= 0;
4560 /* Check if operands are valid for the instruction. */
4563 check_VecOperands (const insn_template
*t
)
4567 /* Without VSIB byte, we can't have a vector register for index. */
4568 if (!t
->opcode_modifier
.vecsib
4570 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4571 || i
.index_reg
->reg_type
.bitfield
.regymm
4572 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4574 i
.error
= unsupported_vector_index_register
;
4578 /* Check if default mask is allowed. */
4579 if (t
->opcode_modifier
.nodefmask
4580 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4582 i
.error
= no_default_mask
;
4586 /* For VSIB byte, we need a vector register for index, and all vector
4587 registers must be distinct. */
4588 if (t
->opcode_modifier
.vecsib
)
4591 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4592 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4593 || (t
->opcode_modifier
.vecsib
== VecSIB256
4594 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4595 || (t
->opcode_modifier
.vecsib
== VecSIB512
4596 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4598 i
.error
= invalid_vsib_address
;
4602 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4603 if (i
.reg_operands
== 2 && !i
.mask
)
4605 gas_assert (i
.types
[0].bitfield
.regxmm
4606 || i
.types
[0].bitfield
.regymm
);
4607 gas_assert (i
.types
[2].bitfield
.regxmm
4608 || i
.types
[2].bitfield
.regymm
);
4609 if (operand_check
== check_none
)
4611 if (register_number (i
.op
[0].regs
)
4612 != register_number (i
.index_reg
)
4613 && register_number (i
.op
[2].regs
)
4614 != register_number (i
.index_reg
)
4615 && register_number (i
.op
[0].regs
)
4616 != register_number (i
.op
[2].regs
))
4618 if (operand_check
== check_error
)
4620 i
.error
= invalid_vector_register_set
;
4623 as_warn (_("mask, index, and destination registers should be distinct"));
4625 else if (i
.reg_operands
== 1 && i
.mask
)
4627 if ((i
.types
[1].bitfield
.regymm
4628 || i
.types
[1].bitfield
.regzmm
)
4629 && (register_number (i
.op
[1].regs
)
4630 == register_number (i
.index_reg
)))
4632 if (operand_check
== check_error
)
4634 i
.error
= invalid_vector_register_set
;
4637 if (operand_check
!= check_none
)
4638 as_warn (_("index and destination registers should be distinct"));
4643 /* Check if broadcast is supported by the instruction and is applied
4644 to the memory operand. */
4647 int broadcasted_opnd_size
;
4649 /* Check if specified broadcast is supported in this instruction,
4650 and it's applied to memory operand of DWORD or QWORD type,
4651 depending on VecESize. */
4652 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4653 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4654 || (t
->opcode_modifier
.vecesize
== 0
4655 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4656 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4657 || (t
->opcode_modifier
.vecesize
== 1
4658 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4659 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4662 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4663 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4664 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4665 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4666 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4667 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4668 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4669 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4670 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4674 if ((broadcasted_opnd_size
== 256
4675 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4676 || (broadcasted_opnd_size
== 512
4677 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4680 i
.error
= unsupported_broadcast
;
4684 /* If broadcast is supported in this instruction, we need to check if
4685 operand of one-element size isn't specified without broadcast. */
4686 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4688 /* Find memory operand. */
4689 for (op
= 0; op
< i
.operands
; op
++)
4690 if (operand_type_check (i
.types
[op
], anymem
))
4692 gas_assert (op
< i
.operands
);
4693 /* Check size of the memory operand. */
4694 if ((t
->opcode_modifier
.vecesize
== 0
4695 && i
.types
[op
].bitfield
.dword
)
4696 || (t
->opcode_modifier
.vecesize
== 1
4697 && i
.types
[op
].bitfield
.qword
))
4699 i
.error
= broadcast_needed
;
4704 /* Check if requested masking is supported. */
4706 && (!t
->opcode_modifier
.masking
4708 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4710 i
.error
= unsupported_masking
;
4714 /* Check if masking is applied to dest operand. */
4715 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4717 i
.error
= mask_not_on_destination
;
4724 if ((i
.rounding
->type
!= saeonly
4725 && !t
->opcode_modifier
.staticrounding
)
4726 || (i
.rounding
->type
== saeonly
4727 && (t
->opcode_modifier
.staticrounding
4728 || !t
->opcode_modifier
.sae
)))
4730 i
.error
= unsupported_rc_sae
;
4733 /* If the instruction has several immediate operands and one of
4734 them is rounding, the rounding operand should be the last
4735 immediate operand. */
4736 if (i
.imm_operands
> 1
4737 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4739 i
.error
= rc_sae_operand_not_last_imm
;
4744 /* Check vector Disp8 operand. */
4745 if (t
->opcode_modifier
.disp8memshift
)
4748 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4750 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4752 for (op
= 0; op
< i
.operands
; op
++)
4753 if (operand_type_check (i
.types
[op
], disp
)
4754 && i
.op
[op
].disps
->X_op
== O_constant
)
4756 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4758 = (i
.disp_encoding
!= disp_encoding_32bit
4759 && fits_in_vec_disp8 (value
));
4760 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4763 i
.types
[op
].bitfield
.vec_disp8
= 1;
4766 /* Vector insn can only have Vec_Disp8/Disp32 in
4767 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4769 i
.types
[op
].bitfield
.disp8
= 0;
4770 if (flag_code
!= CODE_16BIT
)
4771 i
.types
[op
].bitfield
.disp16
= 0;
4774 else if (flag_code
!= CODE_16BIT
)
4776 /* One form of this instruction supports vector Disp8.
4777 Try vector Disp8 if we need to use Disp32. */
4778 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4780 i
.error
= try_vector_disp8
;
4792 /* Check if operands are valid for the instruction. Update VEX
4796 VEX_check_operands (const insn_template
*t
)
4798 if (i
.vec_encoding
== vex_encoding_evex
)
4800 /* This instruction must be encoded with EVEX prefix. */
4801 if (!t
->opcode_modifier
.evex
)
4803 i
.error
= unsupported
;
4809 if (!t
->opcode_modifier
.vex
)
4811 /* This instruction template doesn't have VEX prefix. */
4812 if (i
.vec_encoding
!= vex_encoding_default
)
4814 i
.error
= unsupported
;
4820 /* Only check VEX_Imm4, which must be the first operand. */
4821 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4823 if (i
.op
[0].imms
->X_op
!= O_constant
4824 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4830 /* Turn off Imm8 so that update_imm won't complain. */
4831 i
.types
[0] = vec_imm4
;
4837 static const insn_template
*
4838 match_template (char mnem_suffix
)
4840 /* Points to template once we've found it. */
4841 const insn_template
*t
;
4842 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4843 i386_operand_type overlap4
;
4844 unsigned int found_reverse_match
;
4845 i386_opcode_modifier suffix_check
, mnemsuf_check
;
4846 i386_operand_type operand_types
[MAX_OPERANDS
];
4847 int addr_prefix_disp
;
4849 unsigned int found_cpu_match
;
4850 unsigned int check_register
;
4851 enum i386_error specific_error
= 0;
4853 #if MAX_OPERANDS != 5
4854 # error "MAX_OPERANDS must be 5."
4857 found_reverse_match
= 0;
4858 addr_prefix_disp
= -1;
4860 memset (&suffix_check
, 0, sizeof (suffix_check
));
4861 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4862 suffix_check
.no_bsuf
= 1;
4863 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4864 suffix_check
.no_wsuf
= 1;
4865 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4866 suffix_check
.no_ssuf
= 1;
4867 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4868 suffix_check
.no_lsuf
= 1;
4869 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4870 suffix_check
.no_qsuf
= 1;
4871 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4872 suffix_check
.no_ldsuf
= 1;
4874 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
4877 switch (mnem_suffix
)
4879 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
4880 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
4881 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
4882 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
4883 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
4887 /* Must have right number of operands. */
4888 i
.error
= number_of_operands_mismatch
;
4890 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4892 addr_prefix_disp
= -1;
4894 if (i
.operands
!= t
->operands
)
4897 /* Check processor support. */
4898 i
.error
= unsupported
;
4899 found_cpu_match
= (cpu_flags_match (t
)
4900 == CPU_FLAGS_PERFECT_MATCH
);
4901 if (!found_cpu_match
)
4904 /* Check old gcc support. */
4905 i
.error
= old_gcc_only
;
4906 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4909 /* Check AT&T mnemonic. */
4910 i
.error
= unsupported_with_intel_mnemonic
;
4911 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4914 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
4915 i
.error
= unsupported_syntax
;
4916 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4917 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
4918 || (intel64
&& t
->opcode_modifier
.amd64
)
4919 || (!intel64
&& t
->opcode_modifier
.intel64
))
4922 /* Check the suffix, except for some instructions in intel mode. */
4923 i
.error
= invalid_instruction_suffix
;
4924 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4925 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4926 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4927 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4928 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4929 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4930 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4932 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4933 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
4934 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
4935 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
4936 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
4937 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
4938 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
4941 if (!operand_size_match (t
))
4944 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4945 operand_types
[j
] = t
->operand_types
[j
];
4947 /* In general, don't allow 64-bit operands in 32-bit mode. */
4948 if (i
.suffix
== QWORD_MNEM_SUFFIX
4949 && flag_code
!= CODE_64BIT
4951 ? (!t
->opcode_modifier
.ignoresize
4952 && !intel_float_operand (t
->name
))
4953 : intel_float_operand (t
->name
) != 2)
4954 && ((!operand_types
[0].bitfield
.regmmx
4955 && !operand_types
[0].bitfield
.regxmm
4956 && !operand_types
[0].bitfield
.regymm
4957 && !operand_types
[0].bitfield
.regzmm
)
4958 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4959 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4960 && operand_types
[t
->operands
> 1].bitfield
.regymm
4961 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4962 && (t
->base_opcode
!= 0x0fc7
4963 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4966 /* In general, don't allow 32-bit operands on pre-386. */
4967 else if (i
.suffix
== LONG_MNEM_SUFFIX
4968 && !cpu_arch_flags
.bitfield
.cpui386
4970 ? (!t
->opcode_modifier
.ignoresize
4971 && !intel_float_operand (t
->name
))
4972 : intel_float_operand (t
->name
) != 2)
4973 && ((!operand_types
[0].bitfield
.regmmx
4974 && !operand_types
[0].bitfield
.regxmm
)
4975 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4976 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4979 /* Do not verify operands when there are none. */
4983 /* We've found a match; break out of loop. */
4987 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4988 into Disp32/Disp16/Disp32 operand. */
4989 if (i
.prefix
[ADDR_PREFIX
] != 0)
4991 /* There should be only one Disp operand. */
4995 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4997 if (operand_types
[j
].bitfield
.disp16
)
4999 addr_prefix_disp
= j
;
5000 operand_types
[j
].bitfield
.disp32
= 1;
5001 operand_types
[j
].bitfield
.disp16
= 0;
5007 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5009 if (operand_types
[j
].bitfield
.disp32
)
5011 addr_prefix_disp
= j
;
5012 operand_types
[j
].bitfield
.disp32
= 0;
5013 operand_types
[j
].bitfield
.disp16
= 1;
5019 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5021 if (operand_types
[j
].bitfield
.disp64
)
5023 addr_prefix_disp
= j
;
5024 operand_types
[j
].bitfield
.disp64
= 0;
5025 operand_types
[j
].bitfield
.disp32
= 1;
5033 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5034 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5037 /* We check register size if needed. */
5038 check_register
= t
->opcode_modifier
.checkregsize
;
5039 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5040 switch (t
->operands
)
5043 if (!operand_type_match (overlap0
, i
.types
[0]))
5047 /* xchg %eax, %eax is a special case. It is an alias for nop
5048 only in 32bit mode and we can use opcode 0x90. In 64bit
5049 mode, we can't use 0x90 for xchg %eax, %eax since it should
5050 zero-extend %eax to %rax. */
5051 if (flag_code
== CODE_64BIT
5052 && t
->base_opcode
== 0x90
5053 && operand_type_equal (&i
.types
[0], &acc32
)
5054 && operand_type_equal (&i
.types
[1], &acc32
))
5056 /* If we want store form, we reverse direction of operands. */
5057 if (i
.dir_encoding
== dir_encoding_store
5058 && t
->opcode_modifier
.d
)
5063 /* If we want store form, we skip the current load. */
5064 if (i
.dir_encoding
== dir_encoding_store
5065 && i
.mem_operands
== 0
5066 && t
->opcode_modifier
.load
)
5071 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5072 if (!operand_type_match (overlap0
, i
.types
[0])
5073 || !operand_type_match (overlap1
, i
.types
[1])
5075 && !operand_type_register_match (overlap0
, i
.types
[0],
5077 overlap1
, i
.types
[1],
5080 /* Check if other direction is valid ... */
5081 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
5085 /* Try reversing direction of operands. */
5086 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
5087 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
5088 if (!operand_type_match (overlap0
, i
.types
[0])
5089 || !operand_type_match (overlap1
, i
.types
[1])
5091 && !operand_type_register_match (overlap0
,
5098 /* Does not match either direction. */
5101 /* found_reverse_match holds which of D or FloatDR
5103 if (t
->opcode_modifier
.d
)
5104 found_reverse_match
= Opcode_D
;
5105 else if (t
->opcode_modifier
.floatd
)
5106 found_reverse_match
= Opcode_FloatD
;
5108 found_reverse_match
= 0;
5109 if (t
->opcode_modifier
.floatr
)
5110 found_reverse_match
|= Opcode_FloatR
;
5114 /* Found a forward 2 operand match here. */
5115 switch (t
->operands
)
5118 overlap4
= operand_type_and (i
.types
[4],
5122 overlap3
= operand_type_and (i
.types
[3],
5126 overlap2
= operand_type_and (i
.types
[2],
5131 switch (t
->operands
)
5134 if (!operand_type_match (overlap4
, i
.types
[4])
5135 || !operand_type_register_match (overlap3
,
5144 if (!operand_type_match (overlap3
, i
.types
[3])
5146 && !operand_type_register_match (overlap2
,
5155 /* Here we make use of the fact that there are no
5156 reverse match 3 operand instructions, and all 3
5157 operand instructions only need to be checked for
5158 register consistency between operands 2 and 3. */
5159 if (!operand_type_match (overlap2
, i
.types
[2])
5161 && !operand_type_register_match (overlap1
,
5171 /* Found either forward/reverse 2, 3 or 4 operand match here:
5172 slip through to break. */
5174 if (!found_cpu_match
)
5176 found_reverse_match
= 0;
5180 /* Check if vector and VEX operands are valid. */
5181 if (check_VecOperands (t
) || VEX_check_operands (t
))
5183 specific_error
= i
.error
;
5187 /* We've found a match; break out of loop. */
5191 if (t
== current_templates
->end
)
5193 /* We found no match. */
5194 const char *err_msg
;
5195 switch (specific_error
? specific_error
: i
.error
)
5199 case operand_size_mismatch
:
5200 err_msg
= _("operand size mismatch");
5202 case operand_type_mismatch
:
5203 err_msg
= _("operand type mismatch");
5205 case register_type_mismatch
:
5206 err_msg
= _("register type mismatch");
5208 case number_of_operands_mismatch
:
5209 err_msg
= _("number of operands mismatch");
5211 case invalid_instruction_suffix
:
5212 err_msg
= _("invalid instruction suffix");
5215 err_msg
= _("constant doesn't fit in 4 bits");
5218 err_msg
= _("only supported with old gcc");
5220 case unsupported_with_intel_mnemonic
:
5221 err_msg
= _("unsupported with Intel mnemonic");
5223 case unsupported_syntax
:
5224 err_msg
= _("unsupported syntax");
5227 as_bad (_("unsupported instruction `%s'"),
5228 current_templates
->start
->name
);
5230 case invalid_vsib_address
:
5231 err_msg
= _("invalid VSIB address");
5233 case invalid_vector_register_set
:
5234 err_msg
= _("mask, index, and destination registers must be distinct");
5236 case unsupported_vector_index_register
:
5237 err_msg
= _("unsupported vector index register");
5239 case unsupported_broadcast
:
5240 err_msg
= _("unsupported broadcast");
5242 case broadcast_not_on_src_operand
:
5243 err_msg
= _("broadcast not on source memory operand");
5245 case broadcast_needed
:
5246 err_msg
= _("broadcast is needed for operand of such type");
5248 case unsupported_masking
:
5249 err_msg
= _("unsupported masking");
5251 case mask_not_on_destination
:
5252 err_msg
= _("mask not on destination operand");
5254 case no_default_mask
:
5255 err_msg
= _("default mask isn't allowed");
5257 case unsupported_rc_sae
:
5258 err_msg
= _("unsupported static rounding/sae");
5260 case rc_sae_operand_not_last_imm
:
5262 err_msg
= _("RC/SAE operand must precede immediate operands");
5264 err_msg
= _("RC/SAE operand must follow immediate operands");
5266 case invalid_register_operand
:
5267 err_msg
= _("invalid register operand");
5270 as_bad (_("%s for `%s'"), err_msg
,
5271 current_templates
->start
->name
);
5275 if (!quiet_warnings
)
5278 && (i
.types
[0].bitfield
.jumpabsolute
5279 != operand_types
[0].bitfield
.jumpabsolute
))
5281 as_warn (_("indirect %s without `*'"), t
->name
);
5284 if (t
->opcode_modifier
.isprefix
5285 && t
->opcode_modifier
.ignoresize
)
5287 /* Warn them that a data or address size prefix doesn't
5288 affect assembly of the next line of code. */
5289 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5293 /* Copy the template we found. */
5296 if (addr_prefix_disp
!= -1)
5297 i
.tm
.operand_types
[addr_prefix_disp
]
5298 = operand_types
[addr_prefix_disp
];
5300 if (found_reverse_match
)
5302 /* If we found a reverse match we must alter the opcode
5303 direction bit. found_reverse_match holds bits to change
5304 (different for int & float insns). */
5306 i
.tm
.base_opcode
^= found_reverse_match
;
5308 i
.tm
.operand_types
[0] = operand_types
[1];
5309 i
.tm
.operand_types
[1] = operand_types
[0];
5318 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5319 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5321 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5323 as_bad (_("`%s' operand %d must use `%ses' segment"),
5329 /* There's only ever one segment override allowed per instruction.
5330 This instruction possibly has a legal segment override on the
5331 second operand, so copy the segment to where non-string
5332 instructions store it, allowing common code. */
5333 i
.seg
[0] = i
.seg
[1];
5335 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5337 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5339 as_bad (_("`%s' operand %d must use `%ses' segment"),
5350 process_suffix (void)
5352 /* If matched instruction specifies an explicit instruction mnemonic
5354 if (i
.tm
.opcode_modifier
.size16
)
5355 i
.suffix
= WORD_MNEM_SUFFIX
;
5356 else if (i
.tm
.opcode_modifier
.size32
)
5357 i
.suffix
= LONG_MNEM_SUFFIX
;
5358 else if (i
.tm
.opcode_modifier
.size64
)
5359 i
.suffix
= QWORD_MNEM_SUFFIX
;
5360 else if (i
.reg_operands
)
5362 /* If there's no instruction mnemonic suffix we try to invent one
5363 based on register operands. */
5366 /* We take i.suffix from the last register operand specified,
5367 Destination register type is more significant than source
5368 register type. crc32 in SSE4.2 prefers source register
5370 if (i
.tm
.base_opcode
== 0xf20f38f1)
5372 if (i
.types
[0].bitfield
.reg16
)
5373 i
.suffix
= WORD_MNEM_SUFFIX
;
5374 else if (i
.types
[0].bitfield
.reg32
)
5375 i
.suffix
= LONG_MNEM_SUFFIX
;
5376 else if (i
.types
[0].bitfield
.reg64
)
5377 i
.suffix
= QWORD_MNEM_SUFFIX
;
5379 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5381 if (i
.types
[0].bitfield
.reg8
)
5382 i
.suffix
= BYTE_MNEM_SUFFIX
;
5389 if (i
.tm
.base_opcode
== 0xf20f38f1
5390 || i
.tm
.base_opcode
== 0xf20f38f0)
5392 /* We have to know the operand size for crc32. */
5393 as_bad (_("ambiguous memory operand size for `%s`"),
5398 for (op
= i
.operands
; --op
>= 0;)
5399 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5401 if (i
.types
[op
].bitfield
.reg8
)
5403 i
.suffix
= BYTE_MNEM_SUFFIX
;
5406 else if (i
.types
[op
].bitfield
.reg16
)
5408 i
.suffix
= WORD_MNEM_SUFFIX
;
5411 else if (i
.types
[op
].bitfield
.reg32
)
5413 i
.suffix
= LONG_MNEM_SUFFIX
;
5416 else if (i
.types
[op
].bitfield
.reg64
)
5418 i
.suffix
= QWORD_MNEM_SUFFIX
;
5424 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5427 && i
.tm
.opcode_modifier
.ignoresize
5428 && i
.tm
.opcode_modifier
.no_bsuf
)
5430 else if (!check_byte_reg ())
5433 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5436 && i
.tm
.opcode_modifier
.ignoresize
5437 && i
.tm
.opcode_modifier
.no_lsuf
)
5439 else if (!check_long_reg ())
5442 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5445 && i
.tm
.opcode_modifier
.ignoresize
5446 && i
.tm
.opcode_modifier
.no_qsuf
)
5448 else if (!check_qword_reg ())
5451 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5454 && i
.tm
.opcode_modifier
.ignoresize
5455 && i
.tm
.opcode_modifier
.no_wsuf
)
5457 else if (!check_word_reg ())
5460 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5461 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5462 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5464 /* Skip if the instruction has x/y/z suffix. match_template
5465 should check if it is a valid suffix. */
5467 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5468 /* Do nothing if the instruction is going to ignore the prefix. */
5473 else if (i
.tm
.opcode_modifier
.defaultsize
5475 /* exclude fldenv/frstor/fsave/fstenv */
5476 && i
.tm
.opcode_modifier
.no_ssuf
)
5478 i
.suffix
= stackop_size
;
5480 else if (intel_syntax
5482 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5483 || i
.tm
.opcode_modifier
.jumpbyte
5484 || i
.tm
.opcode_modifier
.jumpintersegment
5485 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5486 && i
.tm
.extension_opcode
<= 3)))
5491 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5493 i
.suffix
= QWORD_MNEM_SUFFIX
;
5498 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5499 i
.suffix
= LONG_MNEM_SUFFIX
;
5502 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5503 i
.suffix
= WORD_MNEM_SUFFIX
;
5512 if (i
.tm
.opcode_modifier
.w
)
5514 as_bad (_("no instruction mnemonic suffix given and "
5515 "no register operands; can't size instruction"));
5521 unsigned int suffixes
;
5523 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5524 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5526 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5528 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5530 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5532 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5535 /* There are more than suffix matches. */
5536 if (i
.tm
.opcode_modifier
.w
5537 || ((suffixes
& (suffixes
- 1))
5538 && !i
.tm
.opcode_modifier
.defaultsize
5539 && !i
.tm
.opcode_modifier
.ignoresize
))
5541 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5547 /* Change the opcode based on the operand size given by i.suffix;
5548 We don't need to change things for byte insns. */
5551 && i
.suffix
!= BYTE_MNEM_SUFFIX
5552 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5553 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5554 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5556 /* It's not a byte, select word/dword operation. */
5557 if (i
.tm
.opcode_modifier
.w
)
5559 if (i
.tm
.opcode_modifier
.shortform
)
5560 i
.tm
.base_opcode
|= 8;
5562 i
.tm
.base_opcode
|= 1;
5565 /* Now select between word & dword operations via the operand
5566 size prefix, except for instructions that will ignore this
5568 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5570 /* The address size override prefix changes the size of the
5572 if ((flag_code
== CODE_32BIT
5573 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5574 || (flag_code
!= CODE_32BIT
5575 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5576 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5579 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5580 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5581 && !i
.tm
.opcode_modifier
.ignoresize
5582 && !i
.tm
.opcode_modifier
.floatmf
5583 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5584 || (flag_code
== CODE_64BIT
5585 && i
.tm
.opcode_modifier
.jumpbyte
)))
5587 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5589 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5590 prefix
= ADDR_PREFIX_OPCODE
;
5592 if (!add_prefix (prefix
))
5596 /* Set mode64 for an operand. */
5597 if (i
.suffix
== QWORD_MNEM_SUFFIX
5598 && flag_code
== CODE_64BIT
5599 && !i
.tm
.opcode_modifier
.norex64
)
5601 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5602 need rex64. cmpxchg8b is also a special case. */
5603 if (! (i
.operands
== 2
5604 && i
.tm
.base_opcode
== 0x90
5605 && i
.tm
.extension_opcode
== None
5606 && operand_type_equal (&i
.types
[0], &acc64
)
5607 && operand_type_equal (&i
.types
[1], &acc64
))
5608 && ! (i
.operands
== 1
5609 && i
.tm
.base_opcode
== 0xfc7
5610 && i
.tm
.extension_opcode
== 1
5611 && !operand_type_check (i
.types
[0], reg
)
5612 && operand_type_check (i
.types
[0], anymem
)))
5616 /* Size floating point instruction. */
5617 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5618 if (i
.tm
.opcode_modifier
.floatmf
)
5619 i
.tm
.base_opcode
^= 4;
5626 check_byte_reg (void)
5630 for (op
= i
.operands
; --op
>= 0;)
5632 /* If this is an eight bit register, it's OK. If it's the 16 or
5633 32 bit version of an eight bit register, we will just use the
5634 low portion, and that's OK too. */
5635 if (i
.types
[op
].bitfield
.reg8
)
5638 /* I/O port address operands are OK too. */
5639 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5642 /* crc32 doesn't generate this warning. */
5643 if (i
.tm
.base_opcode
== 0xf20f38f0)
5646 if ((i
.types
[op
].bitfield
.reg16
5647 || i
.types
[op
].bitfield
.reg32
5648 || i
.types
[op
].bitfield
.reg64
)
5649 && i
.op
[op
].regs
->reg_num
< 4
5650 /* Prohibit these changes in 64bit mode, since the lowering
5651 would be more complicated. */
5652 && flag_code
!= CODE_64BIT
)
5654 #if REGISTER_WARNINGS
5655 if (!quiet_warnings
)
5656 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5658 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5659 ? REGNAM_AL
- REGNAM_AX
5660 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5662 i
.op
[op
].regs
->reg_name
,
5667 /* Any other register is bad. */
5668 if (i
.types
[op
].bitfield
.reg16
5669 || i
.types
[op
].bitfield
.reg32
5670 || i
.types
[op
].bitfield
.reg64
5671 || i
.types
[op
].bitfield
.regmmx
5672 || i
.types
[op
].bitfield
.regxmm
5673 || i
.types
[op
].bitfield
.regymm
5674 || i
.types
[op
].bitfield
.regzmm
5675 || i
.types
[op
].bitfield
.sreg2
5676 || i
.types
[op
].bitfield
.sreg3
5677 || i
.types
[op
].bitfield
.control
5678 || i
.types
[op
].bitfield
.debug
5679 || i
.types
[op
].bitfield
.test
5680 || i
.types
[op
].bitfield
.floatreg
5681 || i
.types
[op
].bitfield
.floatacc
)
5683 as_bad (_("`%s%s' not allowed with `%s%c'"),
5685 i
.op
[op
].regs
->reg_name
,
5695 check_long_reg (void)
5699 for (op
= i
.operands
; --op
>= 0;)
5700 /* Reject eight bit registers, except where the template requires
5701 them. (eg. movzb) */
5702 if (i
.types
[op
].bitfield
.reg8
5703 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5704 || i
.tm
.operand_types
[op
].bitfield
.reg32
5705 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5707 as_bad (_("`%s%s' not allowed with `%s%c'"),
5709 i
.op
[op
].regs
->reg_name
,
5714 /* Warn if the e prefix on a general reg is missing. */
5715 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5716 && i
.types
[op
].bitfield
.reg16
5717 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5718 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5720 /* Prohibit these changes in the 64bit mode, since the
5721 lowering is more complicated. */
5722 if (flag_code
== CODE_64BIT
)
5724 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5725 register_prefix
, i
.op
[op
].regs
->reg_name
,
5729 #if REGISTER_WARNINGS
5730 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5732 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5733 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5736 /* Warn if the r prefix on a general reg is present. */
5737 else if (i
.types
[op
].bitfield
.reg64
5738 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5739 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5742 && i
.tm
.opcode_modifier
.toqword
5743 && !i
.types
[0].bitfield
.regxmm
)
5745 /* Convert to QWORD. We want REX byte. */
5746 i
.suffix
= QWORD_MNEM_SUFFIX
;
5750 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5751 register_prefix
, i
.op
[op
].regs
->reg_name
,
5760 check_qword_reg (void)
5764 for (op
= i
.operands
; --op
>= 0; )
5765 /* Reject eight bit registers, except where the template requires
5766 them. (eg. movzb) */
5767 if (i
.types
[op
].bitfield
.reg8
5768 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5769 || i
.tm
.operand_types
[op
].bitfield
.reg32
5770 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5772 as_bad (_("`%s%s' not allowed with `%s%c'"),
5774 i
.op
[op
].regs
->reg_name
,
5779 /* Warn if the r prefix on a general reg is missing. */
5780 else if ((i
.types
[op
].bitfield
.reg16
5781 || i
.types
[op
].bitfield
.reg32
)
5782 && (i
.tm
.operand_types
[op
].bitfield
.reg64
5783 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5785 /* Prohibit these changes in the 64bit mode, since the
5786 lowering is more complicated. */
5788 && i
.tm
.opcode_modifier
.todword
5789 && !i
.types
[0].bitfield
.regxmm
)
5791 /* Convert to DWORD. We don't want REX byte. */
5792 i
.suffix
= LONG_MNEM_SUFFIX
;
5796 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5797 register_prefix
, i
.op
[op
].regs
->reg_name
,
5806 check_word_reg (void)
5809 for (op
= i
.operands
; --op
>= 0;)
5810 /* Reject eight bit registers, except where the template requires
5811 them. (eg. movzb) */
5812 if (i
.types
[op
].bitfield
.reg8
5813 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5814 || i
.tm
.operand_types
[op
].bitfield
.reg32
5815 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5817 as_bad (_("`%s%s' not allowed with `%s%c'"),
5819 i
.op
[op
].regs
->reg_name
,
5824 /* Warn if the e or r prefix on a general reg is present. */
5825 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5826 && (i
.types
[op
].bitfield
.reg32
5827 || i
.types
[op
].bitfield
.reg64
)
5828 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5829 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5831 /* Prohibit these changes in the 64bit mode, since the
5832 lowering is more complicated. */
5833 if (flag_code
== CODE_64BIT
)
5835 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5836 register_prefix
, i
.op
[op
].regs
->reg_name
,
5840 #if REGISTER_WARNINGS
5841 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5843 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5844 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5851 update_imm (unsigned int j
)
5853 i386_operand_type overlap
= i
.types
[j
];
5854 if ((overlap
.bitfield
.imm8
5855 || overlap
.bitfield
.imm8s
5856 || overlap
.bitfield
.imm16
5857 || overlap
.bitfield
.imm32
5858 || overlap
.bitfield
.imm32s
5859 || overlap
.bitfield
.imm64
)
5860 && !operand_type_equal (&overlap
, &imm8
)
5861 && !operand_type_equal (&overlap
, &imm8s
)
5862 && !operand_type_equal (&overlap
, &imm16
)
5863 && !operand_type_equal (&overlap
, &imm32
)
5864 && !operand_type_equal (&overlap
, &imm32s
)
5865 && !operand_type_equal (&overlap
, &imm64
))
5869 i386_operand_type temp
;
5871 operand_type_set (&temp
, 0);
5872 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5874 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5875 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5877 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5878 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5879 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5881 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5882 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5885 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5888 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5889 || operand_type_equal (&overlap
, &imm16_32
)
5890 || operand_type_equal (&overlap
, &imm16_32s
))
5892 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5897 if (!operand_type_equal (&overlap
, &imm8
)
5898 && !operand_type_equal (&overlap
, &imm8s
)
5899 && !operand_type_equal (&overlap
, &imm16
)
5900 && !operand_type_equal (&overlap
, &imm32
)
5901 && !operand_type_equal (&overlap
, &imm32s
)
5902 && !operand_type_equal (&overlap
, &imm64
))
5904 as_bad (_("no instruction mnemonic suffix given; "
5905 "can't determine immediate size"));
5909 i
.types
[j
] = overlap
;
5919 /* Update the first 2 immediate operands. */
5920 n
= i
.operands
> 2 ? 2 : i
.operands
;
5923 for (j
= 0; j
< n
; j
++)
5924 if (update_imm (j
) == 0)
5927 /* The 3rd operand can't be immediate operand. */
5928 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5935 bad_implicit_operand (int xmm
)
5937 const char *ireg
= xmm
? "xmm0" : "ymm0";
5940 as_bad (_("the last operand of `%s' must be `%s%s'"),
5941 i
.tm
.name
, register_prefix
, ireg
);
5943 as_bad (_("the first operand of `%s' must be `%s%s'"),
5944 i
.tm
.name
, register_prefix
, ireg
);
5949 process_operands (void)
5951 /* Default segment register this instruction will use for memory
5952 accesses. 0 means unknown. This is only for optimizing out
5953 unnecessary segment overrides. */
5954 const seg_entry
*default_seg
= 0;
5956 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5958 unsigned int dupl
= i
.operands
;
5959 unsigned int dest
= dupl
- 1;
5962 /* The destination must be an xmm register. */
5963 gas_assert (i
.reg_operands
5964 && MAX_OPERANDS
> dupl
5965 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5967 if (i
.tm
.opcode_modifier
.firstxmm0
)
5969 /* The first operand is implicit and must be xmm0. */
5970 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5971 if (register_number (i
.op
[0].regs
) != 0)
5972 return bad_implicit_operand (1);
5974 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5976 /* Keep xmm0 for instructions with VEX prefix and 3
5982 /* We remove the first xmm0 and keep the number of
5983 operands unchanged, which in fact duplicates the
5985 for (j
= 1; j
< i
.operands
; j
++)
5987 i
.op
[j
- 1] = i
.op
[j
];
5988 i
.types
[j
- 1] = i
.types
[j
];
5989 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5993 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5995 gas_assert ((MAX_OPERANDS
- 1) > dupl
5996 && (i
.tm
.opcode_modifier
.vexsources
5999 /* Add the implicit xmm0 for instructions with VEX prefix
6001 for (j
= i
.operands
; j
> 0; j
--)
6003 i
.op
[j
] = i
.op
[j
- 1];
6004 i
.types
[j
] = i
.types
[j
- 1];
6005 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6008 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6009 i
.types
[0] = regxmm
;
6010 i
.tm
.operand_types
[0] = regxmm
;
6013 i
.reg_operands
+= 2;
6018 i
.op
[dupl
] = i
.op
[dest
];
6019 i
.types
[dupl
] = i
.types
[dest
];
6020 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6029 i
.op
[dupl
] = i
.op
[dest
];
6030 i
.types
[dupl
] = i
.types
[dest
];
6031 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6034 if (i
.tm
.opcode_modifier
.immext
)
6037 else if (i
.tm
.opcode_modifier
.firstxmm0
)
6041 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
6042 gas_assert (i
.reg_operands
6043 && (operand_type_equal (&i
.types
[0], ®xmm
)
6044 || operand_type_equal (&i
.types
[0], ®ymm
)
6045 || operand_type_equal (&i
.types
[0], ®zmm
)));
6046 if (register_number (i
.op
[0].regs
) != 0)
6047 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
6049 for (j
= 1; j
< i
.operands
; j
++)
6051 i
.op
[j
- 1] = i
.op
[j
];
6052 i
.types
[j
- 1] = i
.types
[j
];
6054 /* We need to adjust fields in i.tm since they are used by
6055 build_modrm_byte. */
6056 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6063 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6065 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6066 gas_assert (i
.operands
>= 2
6067 && (operand_type_equal (&i
.types
[1], ®xmm
)
6068 || operand_type_equal (&i
.types
[1], ®ymm
)
6069 || operand_type_equal (&i
.types
[1], ®zmm
)));
6070 unsigned int regnum
= register_number (i
.op
[1].regs
);
6071 unsigned int first_reg_in_group
= regnum
& ~3;
6072 unsigned int last_reg_in_group
= first_reg_in_group
+ 3;
6073 if (regnum
!= first_reg_in_group
) {
6074 as_warn (_("the second source register `%s%s' implicitly denotes"
6075 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
6076 register_prefix
, i
.op
[1].regs
->reg_name
,
6077 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6078 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6082 else if (i
.tm
.opcode_modifier
.regkludge
)
6084 /* The imul $imm, %reg instruction is converted into
6085 imul $imm, %reg, %reg, and the clr %reg instruction
6086 is converted into xor %reg, %reg. */
6088 unsigned int first_reg_op
;
6090 if (operand_type_check (i
.types
[0], reg
))
6094 /* Pretend we saw the extra register operand. */
6095 gas_assert (i
.reg_operands
== 1
6096 && i
.op
[first_reg_op
+ 1].regs
== 0);
6097 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6098 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6103 if (i
.tm
.opcode_modifier
.shortform
)
6105 if (i
.types
[0].bitfield
.sreg2
6106 || i
.types
[0].bitfield
.sreg3
)
6108 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6109 && i
.op
[0].regs
->reg_num
== 1)
6111 as_bad (_("you can't `pop %scs'"), register_prefix
);
6114 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6115 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6120 /* The register or float register operand is in operand
6124 if (i
.types
[0].bitfield
.floatreg
6125 || operand_type_check (i
.types
[0], reg
))
6129 /* Register goes in low 3 bits of opcode. */
6130 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6131 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6133 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6135 /* Warn about some common errors, but press on regardless.
6136 The first case can be generated by gcc (<= 2.8.1). */
6137 if (i
.operands
== 2)
6139 /* Reversed arguments on faddp, fsubp, etc. */
6140 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6141 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6142 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6146 /* Extraneous `l' suffix on fp insn. */
6147 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6148 register_prefix
, i
.op
[0].regs
->reg_name
);
6153 else if (i
.tm
.opcode_modifier
.modrm
)
6155 /* The opcode is completed (modulo i.tm.extension_opcode which
6156 must be put into the modrm byte). Now, we make the modrm and
6157 index base bytes based on all the info we've collected. */
6159 default_seg
= build_modrm_byte ();
6161 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6165 else if (i
.tm
.opcode_modifier
.isstring
)
6167 /* For the string instructions that allow a segment override
6168 on one of their operands, the default segment is ds. */
6172 if (i
.tm
.base_opcode
== 0x8d /* lea */
6175 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6177 /* If a segment was explicitly specified, and the specified segment
6178 is not the default, use an opcode prefix to select it. If we
6179 never figured out what the default segment is, then default_seg
6180 will be zero at this point, and the specified segment prefix will
6182 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6184 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6190 static const seg_entry
*
6191 build_modrm_byte (void)
6193 const seg_entry
*default_seg
= 0;
6194 unsigned int source
, dest
;
6197 /* The first operand of instructions with VEX prefix and 3 sources
6198 must be VEX_Imm4. */
6199 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6202 unsigned int nds
, reg_slot
;
6205 if (i
.tm
.opcode_modifier
.veximmext
6206 && i
.tm
.opcode_modifier
.immext
)
6208 dest
= i
.operands
- 2;
6209 gas_assert (dest
== 3);
6212 dest
= i
.operands
- 1;
6215 /* There are 2 kinds of instructions:
6216 1. 5 operands: 4 register operands or 3 register operands
6217 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6218 VexW0 or VexW1. The destination must be either XMM, YMM or
6220 2. 4 operands: 4 register operands or 3 register operands
6221 plus 1 memory operand, VexXDS, and VexImmExt */
6222 gas_assert ((i
.reg_operands
== 4
6223 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6224 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6225 && (i
.tm
.opcode_modifier
.veximmext
6226 || (i
.imm_operands
== 1
6227 && i
.types
[0].bitfield
.vec_imm4
6228 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
6229 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6230 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
6231 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
6232 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
6234 if (i
.imm_operands
== 0)
6236 /* When there is no immediate operand, generate an 8bit
6237 immediate operand to encode the first operand. */
6238 exp
= &im_expressions
[i
.imm_operands
++];
6239 i
.op
[i
.operands
].imms
= exp
;
6240 i
.types
[i
.operands
] = imm8
;
6242 /* If VexW1 is set, the first operand is the source and
6243 the second operand is encoded in the immediate operand. */
6244 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6255 /* FMA swaps REG and NDS. */
6256 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6264 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6266 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6268 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6270 exp
->X_op
= O_constant
;
6271 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6272 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6276 unsigned int imm_slot
;
6278 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6280 /* If VexW0 is set, the third operand is the source and
6281 the second operand is encoded in the immediate
6288 /* VexW1 is set, the second operand is the source and
6289 the third operand is encoded in the immediate
6295 if (i
.tm
.opcode_modifier
.immext
)
6297 /* When ImmExt is set, the immediate byte is the last
6299 imm_slot
= i
.operands
- 1;
6307 /* Turn on Imm8 so that output_imm will generate it. */
6308 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6311 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6313 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6315 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6317 i
.op
[imm_slot
].imms
->X_add_number
6318 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6319 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6322 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6323 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6325 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6327 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6332 /* i.reg_operands MUST be the number of real register operands;
6333 implicit registers do not count. If there are 3 register
6334 operands, it must be a instruction with VexNDS. For a
6335 instruction with VexNDD, the destination register is encoded
6336 in VEX prefix. If there are 4 register operands, it must be
6337 a instruction with VEX prefix and 3 sources. */
6338 if (i
.mem_operands
== 0
6339 && ((i
.reg_operands
== 2
6340 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6341 || (i
.reg_operands
== 3
6342 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6343 || (i
.reg_operands
== 4 && vex_3_sources
)))
6351 /* When there are 3 operands, one of them may be immediate,
6352 which may be the first or the last operand. Otherwise,
6353 the first operand must be shift count register (cl) or it
6354 is an instruction with VexNDS. */
6355 gas_assert (i
.imm_operands
== 1
6356 || (i
.imm_operands
== 0
6357 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6358 || i
.types
[0].bitfield
.shiftcount
)));
6359 if (operand_type_check (i
.types
[0], imm
)
6360 || i
.types
[0].bitfield
.shiftcount
)
6366 /* When there are 4 operands, the first two must be 8bit
6367 immediate operands. The source operand will be the 3rd
6370 For instructions with VexNDS, if the first operand
6371 an imm8, the source operand is the 2nd one. If the last
6372 operand is imm8, the source operand is the first one. */
6373 gas_assert ((i
.imm_operands
== 2
6374 && i
.types
[0].bitfield
.imm8
6375 && i
.types
[1].bitfield
.imm8
)
6376 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6377 && i
.imm_operands
== 1
6378 && (i
.types
[0].bitfield
.imm8
6379 || i
.types
[i
.operands
- 1].bitfield
.imm8
6381 if (i
.imm_operands
== 2)
6385 if (i
.types
[0].bitfield
.imm8
)
6392 if (i
.tm
.opcode_modifier
.evex
)
6394 /* For EVEX instructions, when there are 5 operands, the
6395 first one must be immediate operand. If the second one
6396 is immediate operand, the source operand is the 3th
6397 one. If the last one is immediate operand, the source
6398 operand is the 2nd one. */
6399 gas_assert (i
.imm_operands
== 2
6400 && i
.tm
.opcode_modifier
.sae
6401 && operand_type_check (i
.types
[0], imm
));
6402 if (operand_type_check (i
.types
[1], imm
))
6404 else if (operand_type_check (i
.types
[4], imm
))
6418 /* RC/SAE operand could be between DEST and SRC. That happens
6419 when one operand is GPR and the other one is XMM/YMM/ZMM
6421 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6424 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6426 /* For instructions with VexNDS, the register-only source
6427 operand must be 32/64bit integer, XMM, YMM or ZMM
6428 register. It is encoded in VEX prefix. We need to
6429 clear RegMem bit before calling operand_type_equal. */
6431 i386_operand_type op
;
6434 /* Check register-only source operand when two source
6435 operands are swapped. */
6436 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6437 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6445 op
= i
.tm
.operand_types
[vvvv
];
6446 op
.bitfield
.regmem
= 0;
6447 if ((dest
+ 1) >= i
.operands
6448 || (!op
.bitfield
.reg32
6449 && op
.bitfield
.reg64
6450 && !operand_type_equal (&op
, ®xmm
)
6451 && !operand_type_equal (&op
, ®ymm
)
6452 && !operand_type_equal (&op
, ®zmm
)
6453 && !operand_type_equal (&op
, ®mask
)))
6455 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6461 /* One of the register operands will be encoded in the i.tm.reg
6462 field, the other in the combined i.tm.mode and i.tm.regmem
6463 fields. If no form of this instruction supports a memory
6464 destination operand, then we assume the source operand may
6465 sometimes be a memory operand and so we need to store the
6466 destination in the i.rm.reg field. */
6467 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6468 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6470 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6471 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6472 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6474 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6476 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6478 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6483 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6484 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6485 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6487 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6489 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6491 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6494 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6496 if (!i
.types
[0].bitfield
.control
6497 && !i
.types
[1].bitfield
.control
)
6499 i
.rex
&= ~(REX_R
| REX_B
);
6500 add_prefix (LOCK_PREFIX_OPCODE
);
6504 { /* If it's not 2 reg operands... */
6509 unsigned int fake_zero_displacement
= 0;
6512 for (op
= 0; op
< i
.operands
; op
++)
6513 if (operand_type_check (i
.types
[op
], anymem
))
6515 gas_assert (op
< i
.operands
);
6517 if (i
.tm
.opcode_modifier
.vecsib
)
6519 if (i
.index_reg
->reg_num
== RegEiz
6520 || i
.index_reg
->reg_num
== RegRiz
)
6523 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6526 i
.sib
.base
= NO_BASE_REGISTER
;
6527 i
.sib
.scale
= i
.log2_scale_factor
;
6528 /* No Vec_Disp8 if there is no base. */
6529 i
.types
[op
].bitfield
.vec_disp8
= 0;
6530 i
.types
[op
].bitfield
.disp8
= 0;
6531 i
.types
[op
].bitfield
.disp16
= 0;
6532 i
.types
[op
].bitfield
.disp64
= 0;
6533 if (flag_code
!= CODE_64BIT
)
6535 /* Must be 32 bit */
6536 i
.types
[op
].bitfield
.disp32
= 1;
6537 i
.types
[op
].bitfield
.disp32s
= 0;
6541 i
.types
[op
].bitfield
.disp32
= 0;
6542 i
.types
[op
].bitfield
.disp32s
= 1;
6545 i
.sib
.index
= i
.index_reg
->reg_num
;
6546 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6548 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6554 if (i
.base_reg
== 0)
6557 if (!i
.disp_operands
)
6559 fake_zero_displacement
= 1;
6560 /* Instructions with VSIB byte need 32bit displacement
6561 if there is no base register. */
6562 if (i
.tm
.opcode_modifier
.vecsib
)
6563 i
.types
[op
].bitfield
.disp32
= 1;
6565 if (i
.index_reg
== 0)
6567 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6568 /* Operand is just <disp> */
6569 if (flag_code
== CODE_64BIT
)
6571 /* 64bit mode overwrites the 32bit absolute
6572 addressing by RIP relative addressing and
6573 absolute addressing is encoded by one of the
6574 redundant SIB forms. */
6575 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6576 i
.sib
.base
= NO_BASE_REGISTER
;
6577 i
.sib
.index
= NO_INDEX_REGISTER
;
6578 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6579 ? disp32s
: disp32
);
6581 else if ((flag_code
== CODE_16BIT
)
6582 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6584 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6585 i
.types
[op
] = disp16
;
6589 i
.rm
.regmem
= NO_BASE_REGISTER
;
6590 i
.types
[op
] = disp32
;
6593 else if (!i
.tm
.opcode_modifier
.vecsib
)
6595 /* !i.base_reg && i.index_reg */
6596 if (i
.index_reg
->reg_num
== RegEiz
6597 || i
.index_reg
->reg_num
== RegRiz
)
6598 i
.sib
.index
= NO_INDEX_REGISTER
;
6600 i
.sib
.index
= i
.index_reg
->reg_num
;
6601 i
.sib
.base
= NO_BASE_REGISTER
;
6602 i
.sib
.scale
= i
.log2_scale_factor
;
6603 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6604 /* No Vec_Disp8 if there is no base. */
6605 i
.types
[op
].bitfield
.vec_disp8
= 0;
6606 i
.types
[op
].bitfield
.disp8
= 0;
6607 i
.types
[op
].bitfield
.disp16
= 0;
6608 i
.types
[op
].bitfield
.disp64
= 0;
6609 if (flag_code
!= CODE_64BIT
)
6611 /* Must be 32 bit */
6612 i
.types
[op
].bitfield
.disp32
= 1;
6613 i
.types
[op
].bitfield
.disp32s
= 0;
6617 i
.types
[op
].bitfield
.disp32
= 0;
6618 i
.types
[op
].bitfield
.disp32s
= 1;
6620 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6624 /* RIP addressing for 64bit mode. */
6625 else if (i
.base_reg
->reg_num
== RegRip
||
6626 i
.base_reg
->reg_num
== RegEip
)
6628 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6629 i
.rm
.regmem
= NO_BASE_REGISTER
;
6630 i
.types
[op
].bitfield
.disp8
= 0;
6631 i
.types
[op
].bitfield
.disp16
= 0;
6632 i
.types
[op
].bitfield
.disp32
= 0;
6633 i
.types
[op
].bitfield
.disp32s
= 1;
6634 i
.types
[op
].bitfield
.disp64
= 0;
6635 i
.types
[op
].bitfield
.vec_disp8
= 0;
6636 i
.flags
[op
] |= Operand_PCrel
;
6637 if (! i
.disp_operands
)
6638 fake_zero_displacement
= 1;
6640 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6642 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6643 switch (i
.base_reg
->reg_num
)
6646 if (i
.index_reg
== 0)
6648 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6649 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6653 if (i
.index_reg
== 0)
6656 if (operand_type_check (i
.types
[op
], disp
) == 0)
6658 /* fake (%bp) into 0(%bp) */
6659 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6660 i
.types
[op
].bitfield
.vec_disp8
= 1;
6662 i
.types
[op
].bitfield
.disp8
= 1;
6663 fake_zero_displacement
= 1;
6666 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6667 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6669 default: /* (%si) -> 4 or (%di) -> 5 */
6670 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6672 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6674 else /* i.base_reg and 32/64 bit mode */
6676 if (flag_code
== CODE_64BIT
6677 && operand_type_check (i
.types
[op
], disp
))
6679 i386_operand_type temp
;
6680 operand_type_set (&temp
, 0);
6681 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6682 temp
.bitfield
.vec_disp8
6683 = i
.types
[op
].bitfield
.vec_disp8
;
6685 if (i
.prefix
[ADDR_PREFIX
] == 0)
6686 i
.types
[op
].bitfield
.disp32s
= 1;
6688 i
.types
[op
].bitfield
.disp32
= 1;
6691 if (!i
.tm
.opcode_modifier
.vecsib
)
6692 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6693 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6695 i
.sib
.base
= i
.base_reg
->reg_num
;
6696 /* x86-64 ignores REX prefix bit here to avoid decoder
6698 if (!(i
.base_reg
->reg_flags
& RegRex
)
6699 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6700 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6702 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6704 fake_zero_displacement
= 1;
6705 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6706 i
.types
[op
].bitfield
.vec_disp8
= 1;
6708 i
.types
[op
].bitfield
.disp8
= 1;
6710 i
.sib
.scale
= i
.log2_scale_factor
;
6711 if (i
.index_reg
== 0)
6713 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6714 /* <disp>(%esp) becomes two byte modrm with no index
6715 register. We've already stored the code for esp
6716 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6717 Any base register besides %esp will not use the
6718 extra modrm byte. */
6719 i
.sib
.index
= NO_INDEX_REGISTER
;
6721 else if (!i
.tm
.opcode_modifier
.vecsib
)
6723 if (i
.index_reg
->reg_num
== RegEiz
6724 || i
.index_reg
->reg_num
== RegRiz
)
6725 i
.sib
.index
= NO_INDEX_REGISTER
;
6727 i
.sib
.index
= i
.index_reg
->reg_num
;
6728 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6729 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6734 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6735 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6739 if (!fake_zero_displacement
6743 fake_zero_displacement
= 1;
6744 if (i
.disp_encoding
== disp_encoding_8bit
)
6745 i
.types
[op
].bitfield
.disp8
= 1;
6747 i
.types
[op
].bitfield
.disp32
= 1;
6749 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6753 if (fake_zero_displacement
)
6755 /* Fakes a zero displacement assuming that i.types[op]
6756 holds the correct displacement size. */
6759 gas_assert (i
.op
[op
].disps
== 0);
6760 exp
= &disp_expressions
[i
.disp_operands
++];
6761 i
.op
[op
].disps
= exp
;
6762 exp
->X_op
= O_constant
;
6763 exp
->X_add_number
= 0;
6764 exp
->X_add_symbol
= (symbolS
*) 0;
6765 exp
->X_op_symbol
= (symbolS
*) 0;
6773 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6775 if (operand_type_check (i
.types
[0], imm
))
6776 i
.vex
.register_specifier
= NULL
;
6779 /* VEX.vvvv encodes one of the sources when the first
6780 operand is not an immediate. */
6781 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6782 i
.vex
.register_specifier
= i
.op
[0].regs
;
6784 i
.vex
.register_specifier
= i
.op
[1].regs
;
6787 /* Destination is a XMM register encoded in the ModRM.reg
6789 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6790 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6793 /* ModRM.rm and VEX.B encodes the other source. */
6794 if (!i
.mem_operands
)
6798 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6799 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6801 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6803 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6807 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6809 i
.vex
.register_specifier
= i
.op
[2].regs
;
6810 if (!i
.mem_operands
)
6813 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6814 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6818 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6819 (if any) based on i.tm.extension_opcode. Again, we must be
6820 careful to make sure that segment/control/debug/test/MMX
6821 registers are coded into the i.rm.reg field. */
6822 else if (i
.reg_operands
)
6825 unsigned int vex_reg
= ~0;
6827 for (op
= 0; op
< i
.operands
; op
++)
6828 if (i
.types
[op
].bitfield
.reg8
6829 || i
.types
[op
].bitfield
.reg16
6830 || i
.types
[op
].bitfield
.reg32
6831 || i
.types
[op
].bitfield
.reg64
6832 || i
.types
[op
].bitfield
.regmmx
6833 || i
.types
[op
].bitfield
.regxmm
6834 || i
.types
[op
].bitfield
.regymm
6835 || i
.types
[op
].bitfield
.regbnd
6836 || i
.types
[op
].bitfield
.regzmm
6837 || i
.types
[op
].bitfield
.regmask
6838 || i
.types
[op
].bitfield
.sreg2
6839 || i
.types
[op
].bitfield
.sreg3
6840 || i
.types
[op
].bitfield
.control
6841 || i
.types
[op
].bitfield
.debug
6842 || i
.types
[op
].bitfield
.test
)
6847 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6849 /* For instructions with VexNDS, the register-only
6850 source operand is encoded in VEX prefix. */
6851 gas_assert (mem
!= (unsigned int) ~0);
6856 gas_assert (op
< i
.operands
);
6860 /* Check register-only source operand when two source
6861 operands are swapped. */
6862 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6863 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6867 gas_assert (mem
== (vex_reg
+ 1)
6868 && op
< i
.operands
);
6873 gas_assert (vex_reg
< i
.operands
);
6877 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6879 /* For instructions with VexNDD, the register destination
6880 is encoded in VEX prefix. */
6881 if (i
.mem_operands
== 0)
6883 /* There is no memory operand. */
6884 gas_assert ((op
+ 2) == i
.operands
);
6889 /* There are only 2 operands. */
6890 gas_assert (op
< 2 && i
.operands
== 2);
6895 gas_assert (op
< i
.operands
);
6897 if (vex_reg
!= (unsigned int) ~0)
6899 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6901 if (type
->bitfield
.reg32
!= 1
6902 && type
->bitfield
.reg64
!= 1
6903 && !operand_type_equal (type
, ®xmm
)
6904 && !operand_type_equal (type
, ®ymm
)
6905 && !operand_type_equal (type
, ®zmm
)
6906 && !operand_type_equal (type
, ®mask
))
6909 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6912 /* Don't set OP operand twice. */
6915 /* If there is an extension opcode to put here, the
6916 register number must be put into the regmem field. */
6917 if (i
.tm
.extension_opcode
!= None
)
6919 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6920 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6922 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6927 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6928 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6930 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6935 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6936 must set it to 3 to indicate this is a register operand
6937 in the regmem field. */
6938 if (!i
.mem_operands
)
6942 /* Fill in i.rm.reg field with extension opcode (if any). */
6943 if (i
.tm
.extension_opcode
!= None
)
6944 i
.rm
.reg
= i
.tm
.extension_opcode
;
6950 output_branch (void)
6956 relax_substateT subtype
;
6960 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6961 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6964 if (i
.prefix
[DATA_PREFIX
] != 0)
6970 /* Pentium4 branch hints. */
6971 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6972 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6977 if (i
.prefix
[REX_PREFIX
] != 0)
6983 /* BND prefixed jump. */
6984 if (i
.prefix
[BND_PREFIX
] != 0)
6986 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6990 if (i
.prefixes
!= 0 && !intel_syntax
)
6991 as_warn (_("skipping prefixes on this instruction"));
6993 /* It's always a symbol; End frag & setup for relax.
6994 Make sure there is enough room in this frag for the largest
6995 instruction we may generate in md_convert_frag. This is 2
6996 bytes for the opcode and room for the prefix and largest
6998 frag_grow (prefix
+ 2 + 4);
6999 /* Prefix and 1 opcode byte go in fr_fix. */
7000 p
= frag_more (prefix
+ 1);
7001 if (i
.prefix
[DATA_PREFIX
] != 0)
7002 *p
++ = DATA_PREFIX_OPCODE
;
7003 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7004 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7005 *p
++ = i
.prefix
[SEG_PREFIX
];
7006 if (i
.prefix
[REX_PREFIX
] != 0)
7007 *p
++ = i
.prefix
[REX_PREFIX
];
7008 *p
= i
.tm
.base_opcode
;
7010 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7011 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7012 else if (cpu_arch_flags
.bitfield
.cpui386
)
7013 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7015 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7018 sym
= i
.op
[0].disps
->X_add_symbol
;
7019 off
= i
.op
[0].disps
->X_add_number
;
7021 if (i
.op
[0].disps
->X_op
!= O_constant
7022 && i
.op
[0].disps
->X_op
!= O_symbol
)
7024 /* Handle complex expressions. */
7025 sym
= make_expr_symbol (i
.op
[0].disps
);
7029 /* 1 possible extra opcode + 4 byte displacement go in var part.
7030 Pass reloc in fr_var. */
7031 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7041 if (i
.tm
.opcode_modifier
.jumpbyte
)
7043 /* This is a loop or jecxz type instruction. */
7045 if (i
.prefix
[ADDR_PREFIX
] != 0)
7047 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7050 /* Pentium4 branch hints. */
7051 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7052 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7054 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7063 if (flag_code
== CODE_16BIT
)
7066 if (i
.prefix
[DATA_PREFIX
] != 0)
7068 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7078 if (i
.prefix
[REX_PREFIX
] != 0)
7080 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7084 /* BND prefixed jump. */
7085 if (i
.prefix
[BND_PREFIX
] != 0)
7087 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7091 if (i
.prefixes
!= 0 && !intel_syntax
)
7092 as_warn (_("skipping prefixes on this instruction"));
7094 p
= frag_more (i
.tm
.opcode_length
+ size
);
7095 switch (i
.tm
.opcode_length
)
7098 *p
++ = i
.tm
.base_opcode
>> 8;
7101 *p
++ = i
.tm
.base_opcode
;
7107 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7108 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
7110 /* All jumps handled here are signed, but don't use a signed limit
7111 check for 32 and 16 bit jumps as we want to allow wrap around at
7112 4G and 64k respectively. */
7114 fixP
->fx_signed
= 1;
7118 output_interseg_jump (void)
7126 if (flag_code
== CODE_16BIT
)
7130 if (i
.prefix
[DATA_PREFIX
] != 0)
7136 if (i
.prefix
[REX_PREFIX
] != 0)
7146 if (i
.prefixes
!= 0 && !intel_syntax
)
7147 as_warn (_("skipping prefixes on this instruction"));
7149 /* 1 opcode; 2 segment; offset */
7150 p
= frag_more (prefix
+ 1 + 2 + size
);
7152 if (i
.prefix
[DATA_PREFIX
] != 0)
7153 *p
++ = DATA_PREFIX_OPCODE
;
7155 if (i
.prefix
[REX_PREFIX
] != 0)
7156 *p
++ = i
.prefix
[REX_PREFIX
];
7158 *p
++ = i
.tm
.base_opcode
;
7159 if (i
.op
[1].imms
->X_op
== O_constant
)
7161 offsetT n
= i
.op
[1].imms
->X_add_number
;
7164 && !fits_in_unsigned_word (n
)
7165 && !fits_in_signed_word (n
))
7167 as_bad (_("16-bit jump out of range"));
7170 md_number_to_chars (p
, n
, size
);
7173 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7174 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7175 if (i
.op
[0].imms
->X_op
!= O_constant
)
7176 as_bad (_("can't handle non absolute segment in `%s'"),
7178 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7184 fragS
*insn_start_frag
;
7185 offsetT insn_start_off
;
7187 /* Tie dwarf2 debug info to the address at the start of the insn.
7188 We can't do this after the insn has been output as the current
7189 frag may have been closed off. eg. by frag_var. */
7190 dwarf2_emit_insn (0);
7192 insn_start_frag
= frag_now
;
7193 insn_start_off
= frag_now_fix ();
7196 if (i
.tm
.opcode_modifier
.jump
)
7198 else if (i
.tm
.opcode_modifier
.jumpbyte
7199 || i
.tm
.opcode_modifier
.jumpdword
)
7201 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7202 output_interseg_jump ();
7205 /* Output normal instructions here. */
7209 unsigned int prefix
;
7212 && i
.tm
.base_opcode
== 0xfae
7214 && i
.imm_operands
== 1
7215 && (i
.op
[0].imms
->X_add_number
== 0xe8
7216 || i
.op
[0].imms
->X_add_number
== 0xf0
7217 || i
.op
[0].imms
->X_add_number
== 0xf8))
7219 /* Encode lfence, mfence, and sfence as
7220 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7221 offsetT val
= 0x240483f0ULL
;
7223 md_number_to_chars (p
, val
, 5);
7227 /* Some processors fail on LOCK prefix. This options makes
7228 assembler ignore LOCK prefix and serves as a workaround. */
7229 if (omit_lock_prefix
)
7231 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7233 i
.prefix
[LOCK_PREFIX
] = 0;
7236 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7237 don't need the explicit prefix. */
7238 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7240 switch (i
.tm
.opcode_length
)
7243 if (i
.tm
.base_opcode
& 0xff000000)
7245 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7250 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7252 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7253 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7256 if (prefix
!= REPE_PREFIX_OPCODE
7257 || (i
.prefix
[REP_PREFIX
]
7258 != REPE_PREFIX_OPCODE
))
7259 add_prefix (prefix
);
7262 add_prefix (prefix
);
7271 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7272 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7273 R_X86_64_GOTTPOFF relocation so that linker can safely
7274 perform IE->LE optimization. */
7275 if (x86_elf_abi
== X86_64_X32_ABI
7277 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7278 && i
.prefix
[REX_PREFIX
] == 0)
7279 add_prefix (REX_OPCODE
);
7282 /* The prefix bytes. */
7283 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7285 FRAG_APPEND_1_CHAR (*q
);
7289 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7294 /* REX byte is encoded in VEX prefix. */
7298 FRAG_APPEND_1_CHAR (*q
);
7301 /* There should be no other prefixes for instructions
7306 /* For EVEX instructions i.vrex should become 0 after
7307 build_evex_prefix. For VEX instructions upper 16 registers
7308 aren't available, so VREX should be 0. */
7311 /* Now the VEX prefix. */
7312 p
= frag_more (i
.vex
.length
);
7313 for (j
= 0; j
< i
.vex
.length
; j
++)
7314 p
[j
] = i
.vex
.bytes
[j
];
7317 /* Now the opcode; be careful about word order here! */
7318 if (i
.tm
.opcode_length
== 1)
7320 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7324 switch (i
.tm
.opcode_length
)
7328 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7329 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7333 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7343 /* Put out high byte first: can't use md_number_to_chars! */
7344 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7345 *p
= i
.tm
.base_opcode
& 0xff;
7348 /* Now the modrm byte and sib byte (if present). */
7349 if (i
.tm
.opcode_modifier
.modrm
)
7351 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7354 /* If i.rm.regmem == ESP (4)
7355 && i.rm.mode != (Register mode)
7357 ==> need second modrm byte. */
7358 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7360 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7361 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7363 | i
.sib
.scale
<< 6));
7366 if (i
.disp_operands
)
7367 output_disp (insn_start_frag
, insn_start_off
);
7370 output_imm (insn_start_frag
, insn_start_off
);
7376 pi ("" /*line*/, &i
);
7378 #endif /* DEBUG386 */
7381 /* Return the size of the displacement operand N. */
7384 disp_size (unsigned int n
)
7388 /* Vec_Disp8 has to be 8bit. */
7389 if (i
.types
[n
].bitfield
.vec_disp8
)
7391 else if (i
.types
[n
].bitfield
.disp64
)
7393 else if (i
.types
[n
].bitfield
.disp8
)
7395 else if (i
.types
[n
].bitfield
.disp16
)
7400 /* Return the size of the immediate operand N. */
7403 imm_size (unsigned int n
)
7406 if (i
.types
[n
].bitfield
.imm64
)
7408 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7410 else if (i
.types
[n
].bitfield
.imm16
)
7416 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7421 for (n
= 0; n
< i
.operands
; n
++)
7423 if (i
.types
[n
].bitfield
.vec_disp8
7424 || operand_type_check (i
.types
[n
], disp
))
7426 if (i
.op
[n
].disps
->X_op
== O_constant
)
7428 int size
= disp_size (n
);
7429 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7431 if (i
.types
[n
].bitfield
.vec_disp8
)
7433 val
= offset_in_range (val
, size
);
7434 p
= frag_more (size
);
7435 md_number_to_chars (p
, val
, size
);
7439 enum bfd_reloc_code_real reloc_type
;
7440 int size
= disp_size (n
);
7441 int sign
= i
.types
[n
].bitfield
.disp32s
;
7442 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7445 /* We can't have 8 bit displacement here. */
7446 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7448 /* The PC relative address is computed relative
7449 to the instruction boundary, so in case immediate
7450 fields follows, we need to adjust the value. */
7451 if (pcrel
&& i
.imm_operands
)
7456 for (n1
= 0; n1
< i
.operands
; n1
++)
7457 if (operand_type_check (i
.types
[n1
], imm
))
7459 /* Only one immediate is allowed for PC
7460 relative address. */
7461 gas_assert (sz
== 0);
7463 i
.op
[n
].disps
->X_add_number
-= sz
;
7465 /* We should find the immediate. */
7466 gas_assert (sz
!= 0);
7469 p
= frag_more (size
);
7470 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7472 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7473 && (((reloc_type
== BFD_RELOC_32
7474 || reloc_type
== BFD_RELOC_X86_64_32S
7475 || (reloc_type
== BFD_RELOC_64
7477 && (i
.op
[n
].disps
->X_op
== O_symbol
7478 || (i
.op
[n
].disps
->X_op
== O_add
7479 && ((symbol_get_value_expression
7480 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7482 || reloc_type
== BFD_RELOC_32_PCREL
))
7486 if (insn_start_frag
== frag_now
)
7487 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7492 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7493 for (fr
= insn_start_frag
->fr_next
;
7494 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7496 add
+= p
- frag_now
->fr_literal
;
7501 reloc_type
= BFD_RELOC_386_GOTPC
;
7502 i
.op
[n
].imms
->X_add_number
+= add
;
7504 else if (reloc_type
== BFD_RELOC_64
)
7505 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7507 /* Don't do the adjustment for x86-64, as there
7508 the pcrel addressing is relative to the _next_
7509 insn, and that is taken care of in other code. */
7510 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7512 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7513 size
, i
.op
[n
].disps
, pcrel
,
7515 /* Check for "call/jmp *mem", "mov mem, %reg",
7516 "test %reg, mem" and "binop mem, %reg" where binop
7517 is one of adc, add, and, cmp, or, sbb, sub, xor
7518 instructions. Always generate R_386_GOT32X for
7519 "sym*GOT" operand in 32-bit mode. */
7520 if ((generate_relax_relocations
7523 && i
.rm
.regmem
== 5))
7525 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7526 && ((i
.operands
== 1
7527 && i
.tm
.base_opcode
== 0xff
7528 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7530 && (i
.tm
.base_opcode
== 0x8b
7531 || i
.tm
.base_opcode
== 0x85
7532 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7536 fixP
->fx_tcbit
= i
.rex
!= 0;
7538 && (i
.base_reg
->reg_num
== RegRip
7539 || i
.base_reg
->reg_num
== RegEip
))
7540 fixP
->fx_tcbit2
= 1;
7543 fixP
->fx_tcbit2
= 1;
7551 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7556 for (n
= 0; n
< i
.operands
; n
++)
7558 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7559 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7562 if (operand_type_check (i
.types
[n
], imm
))
7564 if (i
.op
[n
].imms
->X_op
== O_constant
)
7566 int size
= imm_size (n
);
7569 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7571 p
= frag_more (size
);
7572 md_number_to_chars (p
, val
, size
);
7576 /* Not absolute_section.
7577 Need a 32-bit fixup (don't support 8bit
7578 non-absolute imms). Try to support other
7580 enum bfd_reloc_code_real reloc_type
;
7581 int size
= imm_size (n
);
7584 if (i
.types
[n
].bitfield
.imm32s
7585 && (i
.suffix
== QWORD_MNEM_SUFFIX
7586 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7591 p
= frag_more (size
);
7592 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7594 /* This is tough to explain. We end up with this one if we
7595 * have operands that look like
7596 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7597 * obtain the absolute address of the GOT, and it is strongly
7598 * preferable from a performance point of view to avoid using
7599 * a runtime relocation for this. The actual sequence of
7600 * instructions often look something like:
7605 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7607 * The call and pop essentially return the absolute address
7608 * of the label .L66 and store it in %ebx. The linker itself
7609 * will ultimately change the first operand of the addl so
7610 * that %ebx points to the GOT, but to keep things simple, the
7611 * .o file must have this operand set so that it generates not
7612 * the absolute address of .L66, but the absolute address of
7613 * itself. This allows the linker itself simply treat a GOTPC
7614 * relocation as asking for a pcrel offset to the GOT to be
7615 * added in, and the addend of the relocation is stored in the
7616 * operand field for the instruction itself.
7618 * Our job here is to fix the operand so that it would add
7619 * the correct offset so that %ebx would point to itself. The
7620 * thing that is tricky is that .-.L66 will point to the
7621 * beginning of the instruction, so we need to further modify
7622 * the operand so that it will point to itself. There are
7623 * other cases where you have something like:
7625 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7627 * and here no correction would be required. Internally in
7628 * the assembler we treat operands of this form as not being
7629 * pcrel since the '.' is explicitly mentioned, and I wonder
7630 * whether it would simplify matters to do it this way. Who
7631 * knows. In earlier versions of the PIC patches, the
7632 * pcrel_adjust field was used to store the correction, but
7633 * since the expression is not pcrel, I felt it would be
7634 * confusing to do it this way. */
7636 if ((reloc_type
== BFD_RELOC_32
7637 || reloc_type
== BFD_RELOC_X86_64_32S
7638 || reloc_type
== BFD_RELOC_64
)
7640 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7641 && (i
.op
[n
].imms
->X_op
== O_symbol
7642 || (i
.op
[n
].imms
->X_op
== O_add
7643 && ((symbol_get_value_expression
7644 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7649 if (insn_start_frag
== frag_now
)
7650 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7655 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7656 for (fr
= insn_start_frag
->fr_next
;
7657 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7659 add
+= p
- frag_now
->fr_literal
;
7663 reloc_type
= BFD_RELOC_386_GOTPC
;
7665 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7667 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7668 i
.op
[n
].imms
->X_add_number
+= add
;
7670 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7671 i
.op
[n
].imms
, 0, reloc_type
);
7677 /* x86_cons_fix_new is called via the expression parsing code when a
7678 reloc is needed. We use this hook to get the correct .got reloc. */
7679 static int cons_sign
= -1;
7682 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7683 expressionS
*exp
, bfd_reloc_code_real_type r
)
7685 r
= reloc (len
, 0, cons_sign
, r
);
7688 if (exp
->X_op
== O_secrel
)
7690 exp
->X_op
= O_symbol
;
7691 r
= BFD_RELOC_32_SECREL
;
7695 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7698 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7699 purpose of the `.dc.a' internal pseudo-op. */
7702 x86_address_bytes (void)
7704 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7706 return stdoutput
->arch_info
->bits_per_address
/ 8;
7709 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7711 # define lex_got(reloc, adjust, types) NULL
7713 /* Parse operands of the form
7714 <symbol>@GOTOFF+<nnn>
7715 and similar .plt or .got references.
7717 If we find one, set up the correct relocation in RELOC and copy the
7718 input string, minus the `@GOTOFF' into a malloc'd buffer for
7719 parsing by the calling routine. Return this buffer, and if ADJUST
7720 is non-null set it to the length of the string we removed from the
7721 input line. Otherwise return NULL. */
7723 lex_got (enum bfd_reloc_code_real
*rel
,
7725 i386_operand_type
*types
)
7727 /* Some of the relocations depend on the size of what field is to
7728 be relocated. But in our callers i386_immediate and i386_displacement
7729 we don't yet know the operand size (this will be set by insn
7730 matching). Hence we record the word32 relocation here,
7731 and adjust the reloc according to the real size in reloc(). */
7732 static const struct {
7735 const enum bfd_reloc_code_real rel
[2];
7736 const i386_operand_type types64
;
7738 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7739 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7741 OPERAND_TYPE_IMM32_64
},
7743 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7744 BFD_RELOC_X86_64_PLTOFF64
},
7745 OPERAND_TYPE_IMM64
},
7746 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7747 BFD_RELOC_X86_64_PLT32
},
7748 OPERAND_TYPE_IMM32_32S_DISP32
},
7749 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7750 BFD_RELOC_X86_64_GOTPLT64
},
7751 OPERAND_TYPE_IMM64_DISP64
},
7752 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7753 BFD_RELOC_X86_64_GOTOFF64
},
7754 OPERAND_TYPE_IMM64_DISP64
},
7755 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7756 BFD_RELOC_X86_64_GOTPCREL
},
7757 OPERAND_TYPE_IMM32_32S_DISP32
},
7758 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7759 BFD_RELOC_X86_64_TLSGD
},
7760 OPERAND_TYPE_IMM32_32S_DISP32
},
7761 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7762 _dummy_first_bfd_reloc_code_real
},
7763 OPERAND_TYPE_NONE
},
7764 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7765 BFD_RELOC_X86_64_TLSLD
},
7766 OPERAND_TYPE_IMM32_32S_DISP32
},
7767 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7768 BFD_RELOC_X86_64_GOTTPOFF
},
7769 OPERAND_TYPE_IMM32_32S_DISP32
},
7770 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7771 BFD_RELOC_X86_64_TPOFF32
},
7772 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7773 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7774 _dummy_first_bfd_reloc_code_real
},
7775 OPERAND_TYPE_NONE
},
7776 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7777 BFD_RELOC_X86_64_DTPOFF32
},
7778 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7779 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7780 _dummy_first_bfd_reloc_code_real
},
7781 OPERAND_TYPE_NONE
},
7782 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7783 _dummy_first_bfd_reloc_code_real
},
7784 OPERAND_TYPE_NONE
},
7785 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7786 BFD_RELOC_X86_64_GOT32
},
7787 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7788 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7789 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7790 OPERAND_TYPE_IMM32_32S_DISP32
},
7791 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7792 BFD_RELOC_X86_64_TLSDESC_CALL
},
7793 OPERAND_TYPE_IMM32_32S_DISP32
},
7798 #if defined (OBJ_MAYBE_ELF)
7803 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7804 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7807 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7809 int len
= gotrel
[j
].len
;
7810 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7812 if (gotrel
[j
].rel
[object_64bit
] != 0)
7815 char *tmpbuf
, *past_reloc
;
7817 *rel
= gotrel
[j
].rel
[object_64bit
];
7821 if (flag_code
!= CODE_64BIT
)
7823 types
->bitfield
.imm32
= 1;
7824 types
->bitfield
.disp32
= 1;
7827 *types
= gotrel
[j
].types64
;
7830 if (j
!= 0 && GOT_symbol
== NULL
)
7831 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7833 /* The length of the first part of our input line. */
7834 first
= cp
- input_line_pointer
;
7836 /* The second part goes from after the reloc token until
7837 (and including) an end_of_line char or comma. */
7838 past_reloc
= cp
+ 1 + len
;
7840 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7842 second
= cp
+ 1 - past_reloc
;
7844 /* Allocate and copy string. The trailing NUL shouldn't
7845 be necessary, but be safe. */
7846 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7847 memcpy (tmpbuf
, input_line_pointer
, first
);
7848 if (second
!= 0 && *past_reloc
!= ' ')
7849 /* Replace the relocation token with ' ', so that
7850 errors like foo@GOTOFF1 will be detected. */
7851 tmpbuf
[first
++] = ' ';
7853 /* Increment length by 1 if the relocation token is
7858 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7859 tmpbuf
[first
+ second
] = '\0';
7863 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7864 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7869 /* Might be a symbol version string. Don't as_bad here. */
7878 /* Parse operands of the form
7879 <symbol>@SECREL32+<nnn>
7881 If we find one, set up the correct relocation in RELOC and copy the
7882 input string, minus the `@SECREL32' into a malloc'd buffer for
7883 parsing by the calling routine. Return this buffer, and if ADJUST
7884 is non-null set it to the length of the string we removed from the
7885 input line. Otherwise return NULL.
7887 This function is copied from the ELF version above adjusted for PE targets. */
7890 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7891 int *adjust ATTRIBUTE_UNUSED
,
7892 i386_operand_type
*types
)
7898 const enum bfd_reloc_code_real rel
[2];
7899 const i386_operand_type types64
;
7903 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7904 BFD_RELOC_32_SECREL
},
7905 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7911 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7912 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7915 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7917 int len
= gotrel
[j
].len
;
7919 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7921 if (gotrel
[j
].rel
[object_64bit
] != 0)
7924 char *tmpbuf
, *past_reloc
;
7926 *rel
= gotrel
[j
].rel
[object_64bit
];
7932 if (flag_code
!= CODE_64BIT
)
7934 types
->bitfield
.imm32
= 1;
7935 types
->bitfield
.disp32
= 1;
7938 *types
= gotrel
[j
].types64
;
7941 /* The length of the first part of our input line. */
7942 first
= cp
- input_line_pointer
;
7944 /* The second part goes from after the reloc token until
7945 (and including) an end_of_line char or comma. */
7946 past_reloc
= cp
+ 1 + len
;
7948 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7950 second
= cp
+ 1 - past_reloc
;
7952 /* Allocate and copy string. The trailing NUL shouldn't
7953 be necessary, but be safe. */
7954 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7955 memcpy (tmpbuf
, input_line_pointer
, first
);
7956 if (second
!= 0 && *past_reloc
!= ' ')
7957 /* Replace the relocation token with ' ', so that
7958 errors like foo@SECLREL321 will be detected. */
7959 tmpbuf
[first
++] = ' ';
7960 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7961 tmpbuf
[first
+ second
] = '\0';
7965 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7966 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7971 /* Might be a symbol version string. Don't as_bad here. */
7977 bfd_reloc_code_real_type
7978 x86_cons (expressionS
*exp
, int size
)
7980 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7982 intel_syntax
= -intel_syntax
;
7985 if (size
== 4 || (object_64bit
&& size
== 8))
7987 /* Handle @GOTOFF and the like in an expression. */
7989 char *gotfree_input_line
;
7992 save
= input_line_pointer
;
7993 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7994 if (gotfree_input_line
)
7995 input_line_pointer
= gotfree_input_line
;
7999 if (gotfree_input_line
)
8001 /* expression () has merrily parsed up to the end of line,
8002 or a comma - in the wrong buffer. Transfer how far
8003 input_line_pointer has moved to the right buffer. */
8004 input_line_pointer
= (save
8005 + (input_line_pointer
- gotfree_input_line
)
8007 free (gotfree_input_line
);
8008 if (exp
->X_op
== O_constant
8009 || exp
->X_op
== O_absent
8010 || exp
->X_op
== O_illegal
8011 || exp
->X_op
== O_register
8012 || exp
->X_op
== O_big
)
8014 char c
= *input_line_pointer
;
8015 *input_line_pointer
= 0;
8016 as_bad (_("missing or invalid expression `%s'"), save
);
8017 *input_line_pointer
= c
;
8024 intel_syntax
= -intel_syntax
;
8027 i386_intel_simplify (exp
);
8033 signed_cons (int size
)
8035 if (flag_code
== CODE_64BIT
)
8043 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
8050 if (exp
.X_op
== O_symbol
)
8051 exp
.X_op
= O_secrel
;
8053 emit_expr (&exp
, 4);
8055 while (*input_line_pointer
++ == ',');
8057 input_line_pointer
--;
8058 demand_empty_rest_of_line ();
8062 /* Handle Vector operations. */
8065 check_VecOperations (char *op_string
, char *op_end
)
8067 const reg_entry
*mask
;
8072 && (op_end
== NULL
|| op_string
< op_end
))
8075 if (*op_string
== '{')
8079 /* Check broadcasts. */
8080 if (strncmp (op_string
, "1to", 3) == 0)
8085 goto duplicated_vec_op
;
8088 if (*op_string
== '8')
8089 bcst_type
= BROADCAST_1TO8
;
8090 else if (*op_string
== '4')
8091 bcst_type
= BROADCAST_1TO4
;
8092 else if (*op_string
== '2')
8093 bcst_type
= BROADCAST_1TO2
;
8094 else if (*op_string
== '1'
8095 && *(op_string
+1) == '6')
8097 bcst_type
= BROADCAST_1TO16
;
8102 as_bad (_("Unsupported broadcast: `%s'"), saved
);
8107 broadcast_op
.type
= bcst_type
;
8108 broadcast_op
.operand
= this_operand
;
8109 i
.broadcast
= &broadcast_op
;
8111 /* Check masking operation. */
8112 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
8114 /* k0 can't be used for write mask. */
8115 if (mask
->reg_num
== 0)
8117 as_bad (_("`%s' can't be used for write mask"),
8124 mask_op
.mask
= mask
;
8125 mask_op
.zeroing
= 0;
8126 mask_op
.operand
= this_operand
;
8132 goto duplicated_vec_op
;
8134 i
.mask
->mask
= mask
;
8136 /* Only "{z}" is allowed here. No need to check
8137 zeroing mask explicitly. */
8138 if (i
.mask
->operand
!= this_operand
)
8140 as_bad (_("invalid write mask `%s'"), saved
);
8147 /* Check zeroing-flag for masking operation. */
8148 else if (*op_string
== 'z')
8152 mask_op
.mask
= NULL
;
8153 mask_op
.zeroing
= 1;
8154 mask_op
.operand
= this_operand
;
8159 if (i
.mask
->zeroing
)
8162 as_bad (_("duplicated `%s'"), saved
);
8166 i
.mask
->zeroing
= 1;
8168 /* Only "{%k}" is allowed here. No need to check mask
8169 register explicitly. */
8170 if (i
.mask
->operand
!= this_operand
)
8172 as_bad (_("invalid zeroing-masking `%s'"),
8181 goto unknown_vec_op
;
8183 if (*op_string
!= '}')
8185 as_bad (_("missing `}' in `%s'"), saved
);
8192 /* We don't know this one. */
8193 as_bad (_("unknown vector operation: `%s'"), saved
);
8201 i386_immediate (char *imm_start
)
8203 char *save_input_line_pointer
;
8204 char *gotfree_input_line
;
8207 i386_operand_type types
;
8209 operand_type_set (&types
, ~0);
8211 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8213 as_bad (_("at most %d immediate operands are allowed"),
8214 MAX_IMMEDIATE_OPERANDS
);
8218 exp
= &im_expressions
[i
.imm_operands
++];
8219 i
.op
[this_operand
].imms
= exp
;
8221 if (is_space_char (*imm_start
))
8224 save_input_line_pointer
= input_line_pointer
;
8225 input_line_pointer
= imm_start
;
8227 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8228 if (gotfree_input_line
)
8229 input_line_pointer
= gotfree_input_line
;
8231 exp_seg
= expression (exp
);
8235 /* Handle vector operations. */
8236 if (*input_line_pointer
== '{')
8238 input_line_pointer
= check_VecOperations (input_line_pointer
,
8240 if (input_line_pointer
== NULL
)
8244 if (*input_line_pointer
)
8245 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8247 input_line_pointer
= save_input_line_pointer
;
8248 if (gotfree_input_line
)
8250 free (gotfree_input_line
);
8252 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8253 exp
->X_op
= O_illegal
;
8256 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8260 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8261 i386_operand_type types
, const char *imm_start
)
8263 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8266 as_bad (_("missing or invalid immediate expression `%s'"),
8270 else if (exp
->X_op
== O_constant
)
8272 /* Size it properly later. */
8273 i
.types
[this_operand
].bitfield
.imm64
= 1;
8274 /* If not 64bit, sign extend val. */
8275 if (flag_code
!= CODE_64BIT
8276 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8278 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8280 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8281 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8282 && exp_seg
!= absolute_section
8283 && exp_seg
!= text_section
8284 && exp_seg
!= data_section
8285 && exp_seg
!= bss_section
8286 && exp_seg
!= undefined_section
8287 && !bfd_is_com_section (exp_seg
))
8289 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8293 else if (!intel_syntax
&& exp_seg
== reg_section
)
8296 as_bad (_("illegal immediate register operand %s"), imm_start
);
8301 /* This is an address. The size of the address will be
8302 determined later, depending on destination register,
8303 suffix, or the default for the section. */
8304 i
.types
[this_operand
].bitfield
.imm8
= 1;
8305 i
.types
[this_operand
].bitfield
.imm16
= 1;
8306 i
.types
[this_operand
].bitfield
.imm32
= 1;
8307 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8308 i
.types
[this_operand
].bitfield
.imm64
= 1;
8309 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8317 i386_scale (char *scale
)
8320 char *save
= input_line_pointer
;
8322 input_line_pointer
= scale
;
8323 val
= get_absolute_expression ();
8328 i
.log2_scale_factor
= 0;
8331 i
.log2_scale_factor
= 1;
8334 i
.log2_scale_factor
= 2;
8337 i
.log2_scale_factor
= 3;
8341 char sep
= *input_line_pointer
;
8343 *input_line_pointer
= '\0';
8344 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8346 *input_line_pointer
= sep
;
8347 input_line_pointer
= save
;
8351 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8353 as_warn (_("scale factor of %d without an index register"),
8354 1 << i
.log2_scale_factor
);
8355 i
.log2_scale_factor
= 0;
8357 scale
= input_line_pointer
;
8358 input_line_pointer
= save
;
8363 i386_displacement (char *disp_start
, char *disp_end
)
8367 char *save_input_line_pointer
;
8368 char *gotfree_input_line
;
8370 i386_operand_type bigdisp
, types
= anydisp
;
8373 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8375 as_bad (_("at most %d displacement operands are allowed"),
8376 MAX_MEMORY_OPERANDS
);
8380 operand_type_set (&bigdisp
, 0);
8381 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8382 || (!current_templates
->start
->opcode_modifier
.jump
8383 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8385 bigdisp
.bitfield
.disp32
= 1;
8386 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8387 if (flag_code
== CODE_64BIT
)
8391 bigdisp
.bitfield
.disp32s
= 1;
8392 bigdisp
.bitfield
.disp64
= 1;
8395 else if ((flag_code
== CODE_16BIT
) ^ override
)
8397 bigdisp
.bitfield
.disp32
= 0;
8398 bigdisp
.bitfield
.disp16
= 1;
8403 /* For PC-relative branches, the width of the displacement
8404 is dependent upon data size, not address size. */
8405 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8406 if (flag_code
== CODE_64BIT
)
8408 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8409 bigdisp
.bitfield
.disp16
= 1;
8412 bigdisp
.bitfield
.disp32
= 1;
8413 bigdisp
.bitfield
.disp32s
= 1;
8419 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8421 : LONG_MNEM_SUFFIX
));
8422 bigdisp
.bitfield
.disp32
= 1;
8423 if ((flag_code
== CODE_16BIT
) ^ override
)
8425 bigdisp
.bitfield
.disp32
= 0;
8426 bigdisp
.bitfield
.disp16
= 1;
8430 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8433 exp
= &disp_expressions
[i
.disp_operands
];
8434 i
.op
[this_operand
].disps
= exp
;
8436 save_input_line_pointer
= input_line_pointer
;
8437 input_line_pointer
= disp_start
;
8438 END_STRING_AND_SAVE (disp_end
);
8440 #ifndef GCC_ASM_O_HACK
8441 #define GCC_ASM_O_HACK 0
8444 END_STRING_AND_SAVE (disp_end
+ 1);
8445 if (i
.types
[this_operand
].bitfield
.baseIndex
8446 && displacement_string_end
[-1] == '+')
8448 /* This hack is to avoid a warning when using the "o"
8449 constraint within gcc asm statements.
8452 #define _set_tssldt_desc(n,addr,limit,type) \
8453 __asm__ __volatile__ ( \
8455 "movw %w1,2+%0\n\t" \
8457 "movb %b1,4+%0\n\t" \
8458 "movb %4,5+%0\n\t" \
8459 "movb $0,6+%0\n\t" \
8460 "movb %h1,7+%0\n\t" \
8462 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8464 This works great except that the output assembler ends
8465 up looking a bit weird if it turns out that there is
8466 no offset. You end up producing code that looks like:
8479 So here we provide the missing zero. */
8481 *displacement_string_end
= '0';
8484 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8485 if (gotfree_input_line
)
8486 input_line_pointer
= gotfree_input_line
;
8488 exp_seg
= expression (exp
);
8491 if (*input_line_pointer
)
8492 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8494 RESTORE_END_STRING (disp_end
+ 1);
8496 input_line_pointer
= save_input_line_pointer
;
8497 if (gotfree_input_line
)
8499 free (gotfree_input_line
);
8501 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8502 exp
->X_op
= O_illegal
;
8505 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8507 RESTORE_END_STRING (disp_end
);
8513 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8514 i386_operand_type types
, const char *disp_start
)
8516 i386_operand_type bigdisp
;
8519 /* We do this to make sure that the section symbol is in
8520 the symbol table. We will ultimately change the relocation
8521 to be relative to the beginning of the section. */
8522 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8523 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8524 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8526 if (exp
->X_op
!= O_symbol
)
8529 if (S_IS_LOCAL (exp
->X_add_symbol
)
8530 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8531 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8532 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8533 exp
->X_op
= O_subtract
;
8534 exp
->X_op_symbol
= GOT_symbol
;
8535 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8536 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8537 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8538 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8540 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8543 else if (exp
->X_op
== O_absent
8544 || exp
->X_op
== O_illegal
8545 || exp
->X_op
== O_big
)
8548 as_bad (_("missing or invalid displacement expression `%s'"),
8553 else if (flag_code
== CODE_64BIT
8554 && !i
.prefix
[ADDR_PREFIX
]
8555 && exp
->X_op
== O_constant
)
8557 /* Since displacement is signed extended to 64bit, don't allow
8558 disp32 and turn off disp32s if they are out of range. */
8559 i
.types
[this_operand
].bitfield
.disp32
= 0;
8560 if (!fits_in_signed_long (exp
->X_add_number
))
8562 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8563 if (i
.types
[this_operand
].bitfield
.baseindex
)
8565 as_bad (_("0x%lx out range of signed 32bit displacement"),
8566 (long) exp
->X_add_number
);
8572 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8573 else if (exp
->X_op
!= O_constant
8574 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8575 && exp_seg
!= absolute_section
8576 && exp_seg
!= text_section
8577 && exp_seg
!= data_section
8578 && exp_seg
!= bss_section
8579 && exp_seg
!= undefined_section
8580 && !bfd_is_com_section (exp_seg
))
8582 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8587 /* Check if this is a displacement only operand. */
8588 bigdisp
= i
.types
[this_operand
];
8589 bigdisp
.bitfield
.disp8
= 0;
8590 bigdisp
.bitfield
.disp16
= 0;
8591 bigdisp
.bitfield
.disp32
= 0;
8592 bigdisp
.bitfield
.disp32s
= 0;
8593 bigdisp
.bitfield
.disp64
= 0;
8594 if (operand_type_all_zero (&bigdisp
))
8595 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8601 /* Make sure the memory operand we've been dealt is valid.
8602 Return 1 on success, 0 on a failure. */
8605 i386_index_check (const char *operand_string
)
8607 const char *kind
= "base/index";
8608 enum flag_code addr_mode
;
8610 if (i
.prefix
[ADDR_PREFIX
])
8611 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8614 addr_mode
= flag_code
;
8616 #if INFER_ADDR_PREFIX
8617 if (i
.mem_operands
== 0)
8619 /* Infer address prefix from the first memory operand. */
8620 const reg_entry
*addr_reg
= i
.base_reg
;
8622 if (addr_reg
== NULL
)
8623 addr_reg
= i
.index_reg
;
8627 if (addr_reg
->reg_num
== RegEip
8628 || addr_reg
->reg_num
== RegEiz
8629 || addr_reg
->reg_type
.bitfield
.reg32
)
8630 addr_mode
= CODE_32BIT
;
8631 else if (flag_code
!= CODE_64BIT
8632 && addr_reg
->reg_type
.bitfield
.reg16
)
8633 addr_mode
= CODE_16BIT
;
8635 if (addr_mode
!= flag_code
)
8637 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8639 /* Change the size of any displacement too. At most one
8640 of Disp16 or Disp32 is set.
8641 FIXME. There doesn't seem to be any real need for
8642 separate Disp16 and Disp32 flags. The same goes for
8643 Imm16 and Imm32. Removing them would probably clean
8644 up the code quite a lot. */
8645 if (flag_code
!= CODE_64BIT
8646 && (i
.types
[this_operand
].bitfield
.disp16
8647 || i
.types
[this_operand
].bitfield
.disp32
))
8648 i
.types
[this_operand
]
8649 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8656 if (current_templates
->start
->opcode_modifier
.isstring
8657 && !current_templates
->start
->opcode_modifier
.immext
8658 && (current_templates
->end
[-1].opcode_modifier
.isstring
8661 /* Memory operands of string insns are special in that they only allow
8662 a single register (rDI, rSI, or rBX) as their memory address. */
8663 const reg_entry
*expected_reg
;
8664 static const char *di_si
[][2] =
8670 static const char *bx
[] = { "ebx", "bx", "rbx" };
8672 kind
= "string address";
8674 if (current_templates
->start
->opcode_modifier
.repprefixok
)
8676 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8678 if (!type
.bitfield
.baseindex
8679 || ((!i
.mem_operands
!= !intel_syntax
)
8680 && current_templates
->end
[-1].operand_types
[1]
8681 .bitfield
.baseindex
))
8682 type
= current_templates
->end
[-1].operand_types
[1];
8683 expected_reg
= hash_find (reg_hash
,
8684 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8688 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8690 if (i
.base_reg
!= expected_reg
8692 || operand_type_check (i
.types
[this_operand
], disp
))
8694 /* The second memory operand must have the same size as
8698 && !((addr_mode
== CODE_64BIT
8699 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8700 || (addr_mode
== CODE_32BIT
8701 ? i
.base_reg
->reg_type
.bitfield
.reg32
8702 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8705 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8707 intel_syntax
? '[' : '(',
8709 expected_reg
->reg_name
,
8710 intel_syntax
? ']' : ')');
8717 as_bad (_("`%s' is not a valid %s expression"),
8718 operand_string
, kind
);
8723 if (addr_mode
!= CODE_16BIT
)
8725 /* 32-bit/64-bit checks. */
8727 && (addr_mode
== CODE_64BIT
8728 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8729 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8731 || (i
.base_reg
->reg_num
8732 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8734 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8735 && !i
.index_reg
->reg_type
.bitfield
.regymm
8736 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8737 && ((addr_mode
== CODE_64BIT
8738 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8739 || i
.index_reg
->reg_num
== RegRiz
)
8740 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8741 || i
.index_reg
->reg_num
== RegEiz
))
8742 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8745 /* bndmk, bndldx, and bndstx have special restrictions. */
8746 if (current_templates
->start
->base_opcode
== 0xf30f1b
8747 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
8749 /* They cannot use RIP-relative addressing. */
8750 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegRip
)
8752 as_bad (_("`%s' cannot be used here"), operand_string
);
8756 /* bndldx and bndstx ignore their scale factor. */
8757 if (current_templates
->start
->base_opcode
!= 0xf30f1b
8758 && i
.log2_scale_factor
)
8759 as_warn (_("register scaling is being ignored here"));
8764 /* 16-bit checks. */
8766 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8767 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8769 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8770 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8772 && i
.base_reg
->reg_num
< 6
8773 && i
.index_reg
->reg_num
>= 6
8774 && i
.log2_scale_factor
== 0))))
8781 /* Handle vector immediates. */
8784 RC_SAE_immediate (const char *imm_start
)
8786 unsigned int match_found
, j
;
8787 const char *pstr
= imm_start
;
8795 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8797 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8801 rc_op
.type
= RC_NamesTable
[j
].type
;
8802 rc_op
.operand
= this_operand
;
8803 i
.rounding
= &rc_op
;
8807 as_bad (_("duplicated `%s'"), imm_start
);
8810 pstr
+= RC_NamesTable
[j
].len
;
8820 as_bad (_("Missing '}': '%s'"), imm_start
);
8823 /* RC/SAE immediate string should contain nothing more. */;
8826 as_bad (_("Junk after '}': '%s'"), imm_start
);
8830 exp
= &im_expressions
[i
.imm_operands
++];
8831 i
.op
[this_operand
].imms
= exp
;
8833 exp
->X_op
= O_constant
;
8834 exp
->X_add_number
= 0;
8835 exp
->X_add_symbol
= (symbolS
*) 0;
8836 exp
->X_op_symbol
= (symbolS
*) 0;
8838 i
.types
[this_operand
].bitfield
.imm8
= 1;
8842 /* Only string instructions can have a second memory operand, so
8843 reduce current_templates to just those if it contains any. */
8845 maybe_adjust_templates (void)
8847 const insn_template
*t
;
8849 gas_assert (i
.mem_operands
== 1);
8851 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
8852 if (t
->opcode_modifier
.isstring
)
8855 if (t
< current_templates
->end
)
8857 static templates aux_templates
;
8858 bfd_boolean recheck
;
8860 aux_templates
.start
= t
;
8861 for (; t
< current_templates
->end
; ++t
)
8862 if (!t
->opcode_modifier
.isstring
)
8864 aux_templates
.end
= t
;
8866 /* Determine whether to re-check the first memory operand. */
8867 recheck
= (aux_templates
.start
!= current_templates
->start
8868 || t
!= current_templates
->end
);
8870 current_templates
= &aux_templates
;
8875 if (i
.memop1_string
!= NULL
8876 && i386_index_check (i
.memop1_string
) == 0)
8885 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8889 i386_att_operand (char *operand_string
)
8893 char *op_string
= operand_string
;
8895 if (is_space_char (*op_string
))
8898 /* We check for an absolute prefix (differentiating,
8899 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8900 if (*op_string
== ABSOLUTE_PREFIX
)
8903 if (is_space_char (*op_string
))
8905 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8908 /* Check if operand is a register. */
8909 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8911 i386_operand_type temp
;
8913 /* Check for a segment override by searching for ':' after a
8914 segment register. */
8916 if (is_space_char (*op_string
))
8918 if (*op_string
== ':'
8919 && (r
->reg_type
.bitfield
.sreg2
8920 || r
->reg_type
.bitfield
.sreg3
))
8925 i
.seg
[i
.mem_operands
] = &es
;
8928 i
.seg
[i
.mem_operands
] = &cs
;
8931 i
.seg
[i
.mem_operands
] = &ss
;
8934 i
.seg
[i
.mem_operands
] = &ds
;
8937 i
.seg
[i
.mem_operands
] = &fs
;
8940 i
.seg
[i
.mem_operands
] = &gs
;
8944 /* Skip the ':' and whitespace. */
8946 if (is_space_char (*op_string
))
8949 if (!is_digit_char (*op_string
)
8950 && !is_identifier_char (*op_string
)
8951 && *op_string
!= '('
8952 && *op_string
!= ABSOLUTE_PREFIX
)
8954 as_bad (_("bad memory operand `%s'"), op_string
);
8957 /* Handle case of %es:*foo. */
8958 if (*op_string
== ABSOLUTE_PREFIX
)
8961 if (is_space_char (*op_string
))
8963 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8965 goto do_memory_reference
;
8968 /* Handle vector operations. */
8969 if (*op_string
== '{')
8971 op_string
= check_VecOperations (op_string
, NULL
);
8972 if (op_string
== NULL
)
8978 as_bad (_("junk `%s' after register"), op_string
);
8982 temp
.bitfield
.baseindex
= 0;
8983 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8985 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8986 i
.op
[this_operand
].regs
= r
;
8989 else if (*op_string
== REGISTER_PREFIX
)
8991 as_bad (_("bad register name `%s'"), op_string
);
8994 else if (*op_string
== IMMEDIATE_PREFIX
)
8997 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8999 as_bad (_("immediate operand illegal with absolute jump"));
9002 if (!i386_immediate (op_string
))
9005 else if (RC_SAE_immediate (operand_string
))
9007 /* If it is a RC or SAE immediate, do nothing. */
9010 else if (is_digit_char (*op_string
)
9011 || is_identifier_char (*op_string
)
9012 || *op_string
== '"'
9013 || *op_string
== '(')
9015 /* This is a memory reference of some sort. */
9018 /* Start and end of displacement string expression (if found). */
9019 char *displacement_string_start
;
9020 char *displacement_string_end
;
9023 do_memory_reference
:
9024 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
9026 if ((i
.mem_operands
== 1
9027 && !current_templates
->start
->opcode_modifier
.isstring
)
9028 || i
.mem_operands
== 2)
9030 as_bad (_("too many memory references for `%s'"),
9031 current_templates
->start
->name
);
9035 /* Check for base index form. We detect the base index form by
9036 looking for an ')' at the end of the operand, searching
9037 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9039 base_string
= op_string
+ strlen (op_string
);
9041 /* Handle vector operations. */
9042 vop_start
= strchr (op_string
, '{');
9043 if (vop_start
&& vop_start
< base_string
)
9045 if (check_VecOperations (vop_start
, base_string
) == NULL
)
9047 base_string
= vop_start
;
9051 if (is_space_char (*base_string
))
9054 /* If we only have a displacement, set-up for it to be parsed later. */
9055 displacement_string_start
= op_string
;
9056 displacement_string_end
= base_string
+ 1;
9058 if (*base_string
== ')')
9061 unsigned int parens_balanced
= 1;
9062 /* We've already checked that the number of left & right ()'s are
9063 equal, so this loop will not be infinite. */
9067 if (*base_string
== ')')
9069 if (*base_string
== '(')
9072 while (parens_balanced
);
9074 temp_string
= base_string
;
9076 /* Skip past '(' and whitespace. */
9078 if (is_space_char (*base_string
))
9081 if (*base_string
== ','
9082 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
9085 displacement_string_end
= temp_string
;
9087 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9091 base_string
= end_op
;
9092 if (is_space_char (*base_string
))
9096 /* There may be an index reg or scale factor here. */
9097 if (*base_string
== ',')
9100 if (is_space_char (*base_string
))
9103 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
9106 base_string
= end_op
;
9107 if (is_space_char (*base_string
))
9109 if (*base_string
== ',')
9112 if (is_space_char (*base_string
))
9115 else if (*base_string
!= ')')
9117 as_bad (_("expecting `,' or `)' "
9118 "after index register in `%s'"),
9123 else if (*base_string
== REGISTER_PREFIX
)
9125 end_op
= strchr (base_string
, ',');
9128 as_bad (_("bad register name `%s'"), base_string
);
9132 /* Check for scale factor. */
9133 if (*base_string
!= ')')
9135 char *end_scale
= i386_scale (base_string
);
9140 base_string
= end_scale
;
9141 if (is_space_char (*base_string
))
9143 if (*base_string
!= ')')
9145 as_bad (_("expecting `)' "
9146 "after scale factor in `%s'"),
9151 else if (!i
.index_reg
)
9153 as_bad (_("expecting index register or scale factor "
9154 "after `,'; got '%c'"),
9159 else if (*base_string
!= ')')
9161 as_bad (_("expecting `,' or `)' "
9162 "after base register in `%s'"),
9167 else if (*base_string
== REGISTER_PREFIX
)
9169 end_op
= strchr (base_string
, ',');
9172 as_bad (_("bad register name `%s'"), base_string
);
9177 /* If there's an expression beginning the operand, parse it,
9178 assuming displacement_string_start and
9179 displacement_string_end are meaningful. */
9180 if (displacement_string_start
!= displacement_string_end
)
9182 if (!i386_displacement (displacement_string_start
,
9183 displacement_string_end
))
9187 /* Special case for (%dx) while doing input/output op. */
9189 && operand_type_equal (&i
.base_reg
->reg_type
,
9190 ®16_inoutportreg
)
9192 && i
.log2_scale_factor
== 0
9193 && i
.seg
[i
.mem_operands
] == 0
9194 && !operand_type_check (i
.types
[this_operand
], disp
))
9196 i
.types
[this_operand
] = inoutportreg
;
9200 if (i386_index_check (operand_string
) == 0)
9202 i
.types
[this_operand
].bitfield
.mem
= 1;
9203 if (i
.mem_operands
== 0)
9204 i
.memop1_string
= xstrdup (operand_string
);
9209 /* It's not a memory operand; argh! */
9210 as_bad (_("invalid char %s beginning operand %d `%s'"),
9211 output_invalid (*op_string
),
9216 return 1; /* Normal return. */
9219 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9220 that an rs_machine_dependent frag may reach. */
9223 i386_frag_max_var (fragS
*frag
)
9225 /* The only relaxable frags are for jumps.
9226 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9227 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9228 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9231 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9233 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9235 /* STT_GNU_IFUNC symbol must go through PLT. */
9236 if ((symbol_get_bfdsym (fr_symbol
)->flags
9237 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9240 if (!S_IS_EXTERNAL (fr_symbol
))
9241 /* Symbol may be weak or local. */
9242 return !S_IS_WEAK (fr_symbol
);
9244 /* Global symbols with non-default visibility can't be preempted. */
9245 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9248 if (fr_var
!= NO_RELOC
)
9249 switch ((enum bfd_reloc_code_real
) fr_var
)
9251 case BFD_RELOC_386_PLT32
:
9252 case BFD_RELOC_X86_64_PLT32
:
9253 /* Symbol with PLT relocation may be preempted. */
9259 /* Global symbols with default visibility in a shared library may be
9260 preempted by another definition. */
9265 /* md_estimate_size_before_relax()
9267 Called just before relax() for rs_machine_dependent frags. The x86
9268 assembler uses these frags to handle variable size jump
9271 Any symbol that is now undefined will not become defined.
9272 Return the correct fr_subtype in the frag.
9273 Return the initial "guess for variable size of frag" to caller.
9274 The guess is actually the growth beyond the fixed part. Whatever
9275 we do to grow the fixed or variable part contributes to our
9279 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9281 /* We've already got fragP->fr_subtype right; all we have to do is
9282 check for un-relaxable symbols. On an ELF system, we can't relax
9283 an externally visible symbol, because it may be overridden by a
9285 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9286 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9288 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9291 #if defined (OBJ_COFF) && defined (TE_PE)
9292 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9293 && S_IS_WEAK (fragP
->fr_symbol
))
9297 /* Symbol is undefined in this segment, or we need to keep a
9298 reloc so that weak symbols can be overridden. */
9299 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9300 enum bfd_reloc_code_real reloc_type
;
9301 unsigned char *opcode
;
9304 if (fragP
->fr_var
!= NO_RELOC
)
9305 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9307 reloc_type
= BFD_RELOC_16_PCREL
;
9309 reloc_type
= BFD_RELOC_32_PCREL
;
9311 old_fr_fix
= fragP
->fr_fix
;
9312 opcode
= (unsigned char *) fragP
->fr_opcode
;
9314 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9317 /* Make jmp (0xeb) a (d)word displacement jump. */
9319 fragP
->fr_fix
+= size
;
9320 fix_new (fragP
, old_fr_fix
, size
,
9322 fragP
->fr_offset
, 1,
9328 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9330 /* Negate the condition, and branch past an
9331 unconditional jump. */
9334 /* Insert an unconditional jump. */
9336 /* We added two extra opcode bytes, and have a two byte
9338 fragP
->fr_fix
+= 2 + 2;
9339 fix_new (fragP
, old_fr_fix
+ 2, 2,
9341 fragP
->fr_offset
, 1,
9348 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9353 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9355 fragP
->fr_offset
, 1,
9357 fixP
->fx_signed
= 1;
9361 /* This changes the byte-displacement jump 0x7N
9362 to the (d)word-displacement jump 0x0f,0x8N. */
9363 opcode
[1] = opcode
[0] + 0x10;
9364 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9365 /* We've added an opcode byte. */
9366 fragP
->fr_fix
+= 1 + size
;
9367 fix_new (fragP
, old_fr_fix
+ 1, size
,
9369 fragP
->fr_offset
, 1,
9374 BAD_CASE (fragP
->fr_subtype
);
9378 return fragP
->fr_fix
- old_fr_fix
;
9381 /* Guess size depending on current relax state. Initially the relax
9382 state will correspond to a short jump and we return 1, because
9383 the variable part of the frag (the branch offset) is one byte
9384 long. However, we can relax a section more than once and in that
9385 case we must either set fr_subtype back to the unrelaxed state,
9386 or return the value for the appropriate branch. */
9387 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9390 /* Called after relax() is finished.
9392 In: Address of frag.
9393 fr_type == rs_machine_dependent.
9394 fr_subtype is what the address relaxed to.
9396 Out: Any fixSs and constants are set up.
9397 Caller will turn frag into a ".space 0". */
9400 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9403 unsigned char *opcode
;
9404 unsigned char *where_to_put_displacement
= NULL
;
9405 offsetT target_address
;
9406 offsetT opcode_address
;
9407 unsigned int extension
= 0;
9408 offsetT displacement_from_opcode_start
;
9410 opcode
= (unsigned char *) fragP
->fr_opcode
;
9412 /* Address we want to reach in file space. */
9413 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9415 /* Address opcode resides at in file space. */
9416 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9418 /* Displacement from opcode start to fill into instruction. */
9419 displacement_from_opcode_start
= target_address
- opcode_address
;
9421 if ((fragP
->fr_subtype
& BIG
) == 0)
9423 /* Don't have to change opcode. */
9424 extension
= 1; /* 1 opcode + 1 displacement */
9425 where_to_put_displacement
= &opcode
[1];
9429 if (no_cond_jump_promotion
9430 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9431 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9432 _("long jump required"));
9434 switch (fragP
->fr_subtype
)
9436 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9437 extension
= 4; /* 1 opcode + 4 displacement */
9439 where_to_put_displacement
= &opcode
[1];
9442 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9443 extension
= 2; /* 1 opcode + 2 displacement */
9445 where_to_put_displacement
= &opcode
[1];
9448 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9449 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9450 extension
= 5; /* 2 opcode + 4 displacement */
9451 opcode
[1] = opcode
[0] + 0x10;
9452 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9453 where_to_put_displacement
= &opcode
[2];
9456 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9457 extension
= 3; /* 2 opcode + 2 displacement */
9458 opcode
[1] = opcode
[0] + 0x10;
9459 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9460 where_to_put_displacement
= &opcode
[2];
9463 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9468 where_to_put_displacement
= &opcode
[3];
9472 BAD_CASE (fragP
->fr_subtype
);
9477 /* If size if less then four we are sure that the operand fits,
9478 but if it's 4, then it could be that the displacement is larger
9480 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9482 && ((addressT
) (displacement_from_opcode_start
- extension
9483 + ((addressT
) 1 << 31))
9484 > (((addressT
) 2 << 31) - 1)))
9486 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9487 _("jump target out of range"));
9488 /* Make us emit 0. */
9489 displacement_from_opcode_start
= extension
;
9491 /* Now put displacement after opcode. */
9492 md_number_to_chars ((char *) where_to_put_displacement
,
9493 (valueT
) (displacement_from_opcode_start
- extension
),
9494 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9495 fragP
->fr_fix
+= extension
;
9498 /* Apply a fixup (fixP) to segment data, once it has been determined
9499 by our caller that we have all the info we need to fix it up.
9501 Parameter valP is the pointer to the value of the bits.
9503 On the 386, immediates, displacements, and data pointers are all in
9504 the same (little-endian) format, so we don't need to care about which
9508 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9510 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9511 valueT value
= *valP
;
9513 #if !defined (TE_Mach)
9516 switch (fixP
->fx_r_type
)
9522 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9525 case BFD_RELOC_X86_64_32S
:
9526 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9529 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9532 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9537 if (fixP
->fx_addsy
!= NULL
9538 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9539 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9540 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9541 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9542 && !use_rela_relocations
)
9544 /* This is a hack. There should be a better way to handle this.
9545 This covers for the fact that bfd_install_relocation will
9546 subtract the current location (for partial_inplace, PC relative
9547 relocations); see more below. */
9551 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9554 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9556 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9559 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9562 || (symbol_section_p (fixP
->fx_addsy
)
9563 && sym_seg
!= absolute_section
))
9564 && !generic_force_reloc (fixP
))
9566 /* Yes, we add the values in twice. This is because
9567 bfd_install_relocation subtracts them out again. I think
9568 bfd_install_relocation is broken, but I don't dare change
9570 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9574 #if defined (OBJ_COFF) && defined (TE_PE)
9575 /* For some reason, the PE format does not store a
9576 section address offset for a PC relative symbol. */
9577 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9578 || S_IS_WEAK (fixP
->fx_addsy
))
9579 value
+= md_pcrel_from (fixP
);
9582 #if defined (OBJ_COFF) && defined (TE_PE)
9583 if (fixP
->fx_addsy
!= NULL
9584 && S_IS_WEAK (fixP
->fx_addsy
)
9585 /* PR 16858: Do not modify weak function references. */
9586 && ! fixP
->fx_pcrel
)
9588 #if !defined (TE_PEP)
9589 /* For x86 PE weak function symbols are neither PC-relative
9590 nor do they set S_IS_FUNCTION. So the only reliable way
9591 to detect them is to check the flags of their containing
9593 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9594 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9598 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9602 /* Fix a few things - the dynamic linker expects certain values here,
9603 and we must not disappoint it. */
9604 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9605 if (IS_ELF
&& fixP
->fx_addsy
)
9606 switch (fixP
->fx_r_type
)
9608 case BFD_RELOC_386_PLT32
:
9609 case BFD_RELOC_X86_64_PLT32
:
9610 /* Make the jump instruction point to the address of the operand. At
9611 runtime we merely add the offset to the actual PLT entry. */
9615 case BFD_RELOC_386_TLS_GD
:
9616 case BFD_RELOC_386_TLS_LDM
:
9617 case BFD_RELOC_386_TLS_IE_32
:
9618 case BFD_RELOC_386_TLS_IE
:
9619 case BFD_RELOC_386_TLS_GOTIE
:
9620 case BFD_RELOC_386_TLS_GOTDESC
:
9621 case BFD_RELOC_X86_64_TLSGD
:
9622 case BFD_RELOC_X86_64_TLSLD
:
9623 case BFD_RELOC_X86_64_GOTTPOFF
:
9624 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9625 value
= 0; /* Fully resolved at runtime. No addend. */
9627 case BFD_RELOC_386_TLS_LE
:
9628 case BFD_RELOC_386_TLS_LDO_32
:
9629 case BFD_RELOC_386_TLS_LE_32
:
9630 case BFD_RELOC_X86_64_DTPOFF32
:
9631 case BFD_RELOC_X86_64_DTPOFF64
:
9632 case BFD_RELOC_X86_64_TPOFF32
:
9633 case BFD_RELOC_X86_64_TPOFF64
:
9634 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9637 case BFD_RELOC_386_TLS_DESC_CALL
:
9638 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9639 value
= 0; /* Fully resolved at runtime. No addend. */
9640 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9644 case BFD_RELOC_VTABLE_INHERIT
:
9645 case BFD_RELOC_VTABLE_ENTRY
:
9652 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9654 #endif /* !defined (TE_Mach) */
9656 /* Are we finished with this relocation now? */
9657 if (fixP
->fx_addsy
== NULL
)
9659 #if defined (OBJ_COFF) && defined (TE_PE)
9660 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9663 /* Remember value for tc_gen_reloc. */
9664 fixP
->fx_addnumber
= value
;
9665 /* Clear out the frag for now. */
9669 else if (use_rela_relocations
)
9671 fixP
->fx_no_overflow
= 1;
9672 /* Remember value for tc_gen_reloc. */
9673 fixP
->fx_addnumber
= value
;
9677 md_number_to_chars (p
, value
, fixP
->fx_size
);
9681 md_atof (int type
, char *litP
, int *sizeP
)
9683 /* This outputs the LITTLENUMs in REVERSE order;
9684 in accord with the bigendian 386. */
9685 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9688 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9691 output_invalid (int c
)
9694 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9697 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9698 "(0x%x)", (unsigned char) c
);
9699 return output_invalid_buf
;
9702 /* REG_STRING starts *before* REGISTER_PREFIX. */
9704 static const reg_entry
*
9705 parse_real_register (char *reg_string
, char **end_op
)
9707 char *s
= reg_string
;
9709 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9712 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9713 if (*s
== REGISTER_PREFIX
)
9716 if (is_space_char (*s
))
9720 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9722 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9723 return (const reg_entry
*) NULL
;
9727 /* For naked regs, make sure that we are not dealing with an identifier.
9728 This prevents confusing an identifier like `eax_var' with register
9730 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9731 return (const reg_entry
*) NULL
;
9735 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9737 /* Handle floating point regs, allowing spaces in the (i) part. */
9738 if (r
== i386_regtab
/* %st is first entry of table */)
9740 if (is_space_char (*s
))
9745 if (is_space_char (*s
))
9747 if (*s
>= '0' && *s
<= '7')
9751 if (is_space_char (*s
))
9756 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9761 /* We have "%st(" then garbage. */
9762 return (const reg_entry
*) NULL
;
9766 if (r
== NULL
|| allow_pseudo_reg
)
9769 if (operand_type_all_zero (&r
->reg_type
))
9770 return (const reg_entry
*) NULL
;
9772 if ((r
->reg_type
.bitfield
.reg32
9773 || r
->reg_type
.bitfield
.sreg3
9774 || r
->reg_type
.bitfield
.control
9775 || r
->reg_type
.bitfield
.debug
9776 || r
->reg_type
.bitfield
.test
)
9777 && !cpu_arch_flags
.bitfield
.cpui386
)
9778 return (const reg_entry
*) NULL
;
9780 if (r
->reg_type
.bitfield
.floatreg
9781 && !cpu_arch_flags
.bitfield
.cpu8087
9782 && !cpu_arch_flags
.bitfield
.cpu287
9783 && !cpu_arch_flags
.bitfield
.cpu387
)
9784 return (const reg_entry
*) NULL
;
9786 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpuregmmx
)
9787 return (const reg_entry
*) NULL
;
9789 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpuregxmm
)
9790 return (const reg_entry
*) NULL
;
9792 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuregymm
)
9793 return (const reg_entry
*) NULL
;
9795 if (r
->reg_type
.bitfield
.regzmm
&& !cpu_arch_flags
.bitfield
.cpuregzmm
)
9796 return (const reg_entry
*) NULL
;
9798 if (r
->reg_type
.bitfield
.regmask
9799 && !cpu_arch_flags
.bitfield
.cpuregmask
)
9800 return (const reg_entry
*) NULL
;
9802 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9803 if (!allow_index_reg
9804 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9805 return (const reg_entry
*) NULL
;
9807 /* Upper 16 vector register is only available with VREX in 64bit
9809 if ((r
->reg_flags
& RegVRex
))
9811 if (i
.vec_encoding
== vex_encoding_default
)
9812 i
.vec_encoding
= vex_encoding_evex
;
9814 if (!cpu_arch_flags
.bitfield
.cpuvrex
9815 || i
.vec_encoding
!= vex_encoding_evex
9816 || flag_code
!= CODE_64BIT
)
9817 return (const reg_entry
*) NULL
;
9820 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9821 || r
->reg_type
.bitfield
.reg64
)
9822 && (!cpu_arch_flags
.bitfield
.cpulm
9823 || !operand_type_equal (&r
->reg_type
, &control
))
9824 && flag_code
!= CODE_64BIT
)
9825 return (const reg_entry
*) NULL
;
9827 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9828 return (const reg_entry
*) NULL
;
9833 /* REG_STRING starts *before* REGISTER_PREFIX. */
9835 static const reg_entry
*
9836 parse_register (char *reg_string
, char **end_op
)
9840 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9841 r
= parse_real_register (reg_string
, end_op
);
9846 char *save
= input_line_pointer
;
9850 input_line_pointer
= reg_string
;
9851 c
= get_symbol_name (®_string
);
9852 symbolP
= symbol_find (reg_string
);
9853 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9855 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9857 know (e
->X_op
== O_register
);
9858 know (e
->X_add_number
>= 0
9859 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9860 r
= i386_regtab
+ e
->X_add_number
;
9861 if ((r
->reg_flags
& RegVRex
))
9862 i
.vec_encoding
= vex_encoding_evex
;
9863 *end_op
= input_line_pointer
;
9865 *input_line_pointer
= c
;
9866 input_line_pointer
= save
;
9872 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9875 char *end
= input_line_pointer
;
9878 r
= parse_register (name
, &input_line_pointer
);
9879 if (r
&& end
<= input_line_pointer
)
9881 *nextcharP
= *input_line_pointer
;
9882 *input_line_pointer
= 0;
9883 e
->X_op
= O_register
;
9884 e
->X_add_number
= r
- i386_regtab
;
9887 input_line_pointer
= end
;
9889 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9893 md_operand (expressionS
*e
)
9898 switch (*input_line_pointer
)
9900 case REGISTER_PREFIX
:
9901 r
= parse_real_register (input_line_pointer
, &end
);
9904 e
->X_op
= O_register
;
9905 e
->X_add_number
= r
- i386_regtab
;
9906 input_line_pointer
= end
;
9911 gas_assert (intel_syntax
);
9912 end
= input_line_pointer
++;
9914 if (*input_line_pointer
== ']')
9916 ++input_line_pointer
;
9917 e
->X_op_symbol
= make_expr_symbol (e
);
9918 e
->X_add_symbol
= NULL
;
9919 e
->X_add_number
= 0;
9925 input_line_pointer
= end
;
9932 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9933 const char *md_shortopts
= "kVQ:sqn";
9935 const char *md_shortopts
= "qn";
9938 #define OPTION_32 (OPTION_MD_BASE + 0)
9939 #define OPTION_64 (OPTION_MD_BASE + 1)
9940 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9941 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9942 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9943 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9944 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9945 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9946 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9947 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9948 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9949 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9950 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9951 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9952 #define OPTION_X32 (OPTION_MD_BASE + 14)
9953 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9954 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9955 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9956 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9957 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9958 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9959 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9960 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9961 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9962 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9963 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
9965 struct option md_longopts
[] =
9967 {"32", no_argument
, NULL
, OPTION_32
},
9968 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9969 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9970 {"64", no_argument
, NULL
, OPTION_64
},
9972 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9973 {"x32", no_argument
, NULL
, OPTION_X32
},
9974 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
9976 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9977 {"march", required_argument
, NULL
, OPTION_MARCH
},
9978 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9979 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9980 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9981 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9982 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9983 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9984 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9985 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9986 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9987 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9988 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9989 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9990 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9991 # if defined (TE_PE) || defined (TE_PEP)
9992 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9994 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
9995 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
9996 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
9997 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9998 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
9999 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
10000 {NULL
, no_argument
, NULL
, 0}
10002 size_t md_longopts_size
= sizeof (md_longopts
);
10005 md_parse_option (int c
, const char *arg
)
10008 char *arch
, *next
, *saved
;
10013 optimize_align_code
= 0;
10017 quiet_warnings
= 1;
10020 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10021 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10022 should be emitted or not. FIXME: Not implemented. */
10026 /* -V: SVR4 argument to print version ID. */
10028 print_version_id ();
10031 /* -k: Ignore for FreeBSD compatibility. */
10036 /* -s: On i386 Solaris, this tells the native assembler to use
10037 .stab instead of .stab.excl. We always use .stab anyhow. */
10040 case OPTION_MSHARED
:
10044 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10045 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10048 const char **list
, **l
;
10050 list
= bfd_target_list ();
10051 for (l
= list
; *l
!= NULL
; l
++)
10052 if (CONST_STRNEQ (*l
, "elf64-x86-64")
10053 || strcmp (*l
, "coff-x86-64") == 0
10054 || strcmp (*l
, "pe-x86-64") == 0
10055 || strcmp (*l
, "pei-x86-64") == 0
10056 || strcmp (*l
, "mach-o-x86-64") == 0)
10058 default_arch
= "x86_64";
10062 as_fatal (_("no compiled in support for x86_64"));
10068 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10072 const char **list
, **l
;
10074 list
= bfd_target_list ();
10075 for (l
= list
; *l
!= NULL
; l
++)
10076 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
10078 default_arch
= "x86_64:32";
10082 as_fatal (_("no compiled in support for 32bit x86_64"));
10086 as_fatal (_("32bit x86_64 is only supported for ELF"));
10091 default_arch
= "i386";
10094 case OPTION_DIVIDE
:
10095 #ifdef SVR4_COMMENT_CHARS
10100 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
10102 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
10106 i386_comment_chars
= n
;
10112 saved
= xstrdup (arg
);
10114 /* Allow -march=+nosse. */
10120 as_fatal (_("invalid -march= option: `%s'"), arg
);
10121 next
= strchr (arch
, '+');
10124 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10126 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
10129 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10132 cpu_arch_name
= cpu_arch
[j
].name
;
10133 cpu_sub_arch_name
= NULL
;
10134 cpu_arch_flags
= cpu_arch
[j
].flags
;
10135 cpu_arch_isa
= cpu_arch
[j
].type
;
10136 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
10137 if (!cpu_arch_tune_set
)
10139 cpu_arch_tune
= cpu_arch_isa
;
10140 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10144 else if (*cpu_arch
[j
].name
== '.'
10145 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
10147 /* ISA extension. */
10148 i386_cpu_flags flags
;
10150 flags
= cpu_flags_or (cpu_arch_flags
,
10151 cpu_arch
[j
].flags
);
10153 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10155 if (cpu_sub_arch_name
)
10157 char *name
= cpu_sub_arch_name
;
10158 cpu_sub_arch_name
= concat (name
,
10160 (const char *) NULL
);
10164 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
10165 cpu_arch_flags
= flags
;
10166 cpu_arch_isa_flags
= flags
;
10172 if (j
>= ARRAY_SIZE (cpu_arch
))
10174 /* Disable an ISA extension. */
10175 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10176 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
10178 i386_cpu_flags flags
;
10180 flags
= cpu_flags_and_not (cpu_arch_flags
,
10181 cpu_noarch
[j
].flags
);
10182 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10184 if (cpu_sub_arch_name
)
10186 char *name
= cpu_sub_arch_name
;
10187 cpu_sub_arch_name
= concat (arch
,
10188 (const char *) NULL
);
10192 cpu_sub_arch_name
= xstrdup (arch
);
10193 cpu_arch_flags
= flags
;
10194 cpu_arch_isa_flags
= flags
;
10199 if (j
>= ARRAY_SIZE (cpu_noarch
))
10200 j
= ARRAY_SIZE (cpu_arch
);
10203 if (j
>= ARRAY_SIZE (cpu_arch
))
10204 as_fatal (_("invalid -march= option: `%s'"), arg
);
10208 while (next
!= NULL
);
10214 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10215 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10217 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
10219 cpu_arch_tune_set
= 1;
10220 cpu_arch_tune
= cpu_arch
[j
].type
;
10221 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10225 if (j
>= ARRAY_SIZE (cpu_arch
))
10226 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10229 case OPTION_MMNEMONIC
:
10230 if (strcasecmp (arg
, "att") == 0)
10231 intel_mnemonic
= 0;
10232 else if (strcasecmp (arg
, "intel") == 0)
10233 intel_mnemonic
= 1;
10235 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10238 case OPTION_MSYNTAX
:
10239 if (strcasecmp (arg
, "att") == 0)
10241 else if (strcasecmp (arg
, "intel") == 0)
10244 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10247 case OPTION_MINDEX_REG
:
10248 allow_index_reg
= 1;
10251 case OPTION_MNAKED_REG
:
10252 allow_naked_reg
= 1;
10255 case OPTION_MOLD_GCC
:
10259 case OPTION_MSSE2AVX
:
10263 case OPTION_MSSE_CHECK
:
10264 if (strcasecmp (arg
, "error") == 0)
10265 sse_check
= check_error
;
10266 else if (strcasecmp (arg
, "warning") == 0)
10267 sse_check
= check_warning
;
10268 else if (strcasecmp (arg
, "none") == 0)
10269 sse_check
= check_none
;
10271 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10274 case OPTION_MOPERAND_CHECK
:
10275 if (strcasecmp (arg
, "error") == 0)
10276 operand_check
= check_error
;
10277 else if (strcasecmp (arg
, "warning") == 0)
10278 operand_check
= check_warning
;
10279 else if (strcasecmp (arg
, "none") == 0)
10280 operand_check
= check_none
;
10282 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10285 case OPTION_MAVXSCALAR
:
10286 if (strcasecmp (arg
, "128") == 0)
10287 avxscalar
= vex128
;
10288 else if (strcasecmp (arg
, "256") == 0)
10289 avxscalar
= vex256
;
10291 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10294 case OPTION_MADD_BND_PREFIX
:
10295 add_bnd_prefix
= 1;
10298 case OPTION_MEVEXLIG
:
10299 if (strcmp (arg
, "128") == 0)
10300 evexlig
= evexl128
;
10301 else if (strcmp (arg
, "256") == 0)
10302 evexlig
= evexl256
;
10303 else if (strcmp (arg
, "512") == 0)
10304 evexlig
= evexl512
;
10306 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10309 case OPTION_MEVEXRCIG
:
10310 if (strcmp (arg
, "rne") == 0)
10312 else if (strcmp (arg
, "rd") == 0)
10314 else if (strcmp (arg
, "ru") == 0)
10316 else if (strcmp (arg
, "rz") == 0)
10319 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10322 case OPTION_MEVEXWIG
:
10323 if (strcmp (arg
, "0") == 0)
10325 else if (strcmp (arg
, "1") == 0)
10328 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10331 # if defined (TE_PE) || defined (TE_PEP)
10332 case OPTION_MBIG_OBJ
:
10337 case OPTION_MOMIT_LOCK_PREFIX
:
10338 if (strcasecmp (arg
, "yes") == 0)
10339 omit_lock_prefix
= 1;
10340 else if (strcasecmp (arg
, "no") == 0)
10341 omit_lock_prefix
= 0;
10343 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10346 case OPTION_MFENCE_AS_LOCK_ADD
:
10347 if (strcasecmp (arg
, "yes") == 0)
10349 else if (strcasecmp (arg
, "no") == 0)
10352 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10355 case OPTION_MRELAX_RELOCATIONS
:
10356 if (strcasecmp (arg
, "yes") == 0)
10357 generate_relax_relocations
= 1;
10358 else if (strcasecmp (arg
, "no") == 0)
10359 generate_relax_relocations
= 0;
10361 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10364 case OPTION_MAMD64
:
10368 case OPTION_MINTEL64
:
10378 #define MESSAGE_TEMPLATE \
10382 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10383 int *left_p
, const char *name
, int len
)
10385 int size
= sizeof (MESSAGE_TEMPLATE
);
10386 int left
= *left_p
;
10388 /* Reserve 2 spaces for ", " or ",\0" */
10391 /* Check if there is any room. */
10399 p
= mempcpy (p
, name
, len
);
10403 /* Output the current message now and start a new one. */
10406 fprintf (stream
, "%s\n", message
);
10408 left
= size
- (start
- message
) - len
- 2;
10410 gas_assert (left
>= 0);
10412 p
= mempcpy (p
, name
, len
);
10420 show_arch (FILE *stream
, int ext
, int check
)
10422 static char message
[] = MESSAGE_TEMPLATE
;
10423 char *start
= message
+ 27;
10425 int size
= sizeof (MESSAGE_TEMPLATE
);
10432 left
= size
- (start
- message
);
10433 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10435 /* Should it be skipped? */
10436 if (cpu_arch
[j
].skip
)
10439 name
= cpu_arch
[j
].name
;
10440 len
= cpu_arch
[j
].len
;
10443 /* It is an extension. Skip if we aren't asked to show it. */
10454 /* It is an processor. Skip if we show only extension. */
10457 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10459 /* It is an impossible processor - skip. */
10463 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10466 /* Display disabled extensions. */
10468 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10470 name
= cpu_noarch
[j
].name
;
10471 len
= cpu_noarch
[j
].len
;
10472 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10477 fprintf (stream
, "%s\n", message
);
10481 md_show_usage (FILE *stream
)
10483 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10484 fprintf (stream
, _("\
10486 -V print assembler version number\n\
10489 fprintf (stream
, _("\
10490 -n Do not optimize code alignment\n\
10491 -q quieten some warnings\n"));
10492 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10493 fprintf (stream
, _("\
10496 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10497 || defined (TE_PE) || defined (TE_PEP))
10498 fprintf (stream
, _("\
10499 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10501 #ifdef SVR4_COMMENT_CHARS
10502 fprintf (stream
, _("\
10503 --divide do not treat `/' as a comment character\n"));
10505 fprintf (stream
, _("\
10506 --divide ignored\n"));
10508 fprintf (stream
, _("\
10509 -march=CPU[,+EXTENSION...]\n\
10510 generate code for CPU and EXTENSION, CPU is one of:\n"));
10511 show_arch (stream
, 0, 1);
10512 fprintf (stream
, _("\
10513 EXTENSION is combination of:\n"));
10514 show_arch (stream
, 1, 0);
10515 fprintf (stream
, _("\
10516 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10517 show_arch (stream
, 0, 0);
10518 fprintf (stream
, _("\
10519 -msse2avx encode SSE instructions with VEX prefix\n"));
10520 fprintf (stream
, _("\
10521 -msse-check=[none|error|warning]\n\
10522 check SSE instructions\n"));
10523 fprintf (stream
, _("\
10524 -moperand-check=[none|error|warning]\n\
10525 check operand combinations for validity\n"));
10526 fprintf (stream
, _("\
10527 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10529 fprintf (stream
, _("\
10530 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10532 fprintf (stream
, _("\
10533 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10534 for EVEX.W bit ignored instructions\n"));
10535 fprintf (stream
, _("\
10536 -mevexrcig=[rne|rd|ru|rz]\n\
10537 encode EVEX instructions with specific EVEX.RC value\n\
10538 for SAE-only ignored instructions\n"));
10539 fprintf (stream
, _("\
10540 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10541 fprintf (stream
, _("\
10542 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10543 fprintf (stream
, _("\
10544 -mindex-reg support pseudo index registers\n"));
10545 fprintf (stream
, _("\
10546 -mnaked-reg don't require `%%' prefix for registers\n"));
10547 fprintf (stream
, _("\
10548 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10549 fprintf (stream
, _("\
10550 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10551 fprintf (stream
, _("\
10552 -mshared disable branch optimization for shared code\n"));
10553 # if defined (TE_PE) || defined (TE_PEP)
10554 fprintf (stream
, _("\
10555 -mbig-obj generate big object files\n"));
10557 fprintf (stream
, _("\
10558 -momit-lock-prefix=[no|yes]\n\
10559 strip all lock prefixes\n"));
10560 fprintf (stream
, _("\
10561 -mfence-as-lock-add=[no|yes]\n\
10562 encode lfence, mfence and sfence as\n\
10563 lock addl $0x0, (%%{re}sp)\n"));
10564 fprintf (stream
, _("\
10565 -mrelax-relocations=[no|yes]\n\
10566 generate relax relocations\n"));
10567 fprintf (stream
, _("\
10568 -mamd64 accept only AMD64 ISA\n"));
10569 fprintf (stream
, _("\
10570 -mintel64 accept only Intel64 ISA\n"));
10573 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10574 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10575 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10577 /* Pick the target format to use. */
10580 i386_target_format (void)
10582 if (!strncmp (default_arch
, "x86_64", 6))
10584 update_code_flag (CODE_64BIT
, 1);
10585 if (default_arch
[6] == '\0')
10586 x86_elf_abi
= X86_64_ABI
;
10588 x86_elf_abi
= X86_64_X32_ABI
;
10590 else if (!strcmp (default_arch
, "i386"))
10591 update_code_flag (CODE_32BIT
, 1);
10592 else if (!strcmp (default_arch
, "iamcu"))
10594 update_code_flag (CODE_32BIT
, 1);
10595 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10597 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10598 cpu_arch_name
= "iamcu";
10599 cpu_sub_arch_name
= NULL
;
10600 cpu_arch_flags
= iamcu_flags
;
10601 cpu_arch_isa
= PROCESSOR_IAMCU
;
10602 cpu_arch_isa_flags
= iamcu_flags
;
10603 if (!cpu_arch_tune_set
)
10605 cpu_arch_tune
= cpu_arch_isa
;
10606 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10609 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
10610 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10614 as_fatal (_("unknown architecture"));
10616 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10617 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10618 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10619 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10621 switch (OUTPUT_FLAVOR
)
10623 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10624 case bfd_target_aout_flavour
:
10625 return AOUT_TARGET_FORMAT
;
10627 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10628 # if defined (TE_PE) || defined (TE_PEP)
10629 case bfd_target_coff_flavour
:
10630 if (flag_code
== CODE_64BIT
)
10631 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10634 # elif defined (TE_GO32)
10635 case bfd_target_coff_flavour
:
10636 return "coff-go32";
10638 case bfd_target_coff_flavour
:
10639 return "coff-i386";
10642 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10643 case bfd_target_elf_flavour
:
10645 const char *format
;
10647 switch (x86_elf_abi
)
10650 format
= ELF_TARGET_FORMAT
;
10653 use_rela_relocations
= 1;
10655 format
= ELF_TARGET_FORMAT64
;
10657 case X86_64_X32_ABI
:
10658 use_rela_relocations
= 1;
10660 disallow_64bit_reloc
= 1;
10661 format
= ELF_TARGET_FORMAT32
;
10664 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10666 if (x86_elf_abi
!= X86_64_ABI
)
10667 as_fatal (_("Intel L1OM is 64bit only"));
10668 return ELF_TARGET_L1OM_FORMAT
;
10670 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10672 if (x86_elf_abi
!= X86_64_ABI
)
10673 as_fatal (_("Intel K1OM is 64bit only"));
10674 return ELF_TARGET_K1OM_FORMAT
;
10676 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10678 if (x86_elf_abi
!= I386_ABI
)
10679 as_fatal (_("Intel MCU is 32bit only"));
10680 return ELF_TARGET_IAMCU_FORMAT
;
10686 #if defined (OBJ_MACH_O)
10687 case bfd_target_mach_o_flavour
:
10688 if (flag_code
== CODE_64BIT
)
10690 use_rela_relocations
= 1;
10692 return "mach-o-x86-64";
10695 return "mach-o-i386";
10703 #endif /* OBJ_MAYBE_ more than one */
10706 md_undefined_symbol (char *name
)
10708 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10709 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10710 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10711 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10715 if (symbol_find (name
))
10716 as_bad (_("GOT already in symbol table"));
10717 GOT_symbol
= symbol_new (name
, undefined_section
,
10718 (valueT
) 0, &zero_address_frag
);
10725 /* Round up a section size to the appropriate boundary. */
10728 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10730 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10731 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10733 /* For a.out, force the section size to be aligned. If we don't do
10734 this, BFD will align it for us, but it will not write out the
10735 final bytes of the section. This may be a bug in BFD, but it is
10736 easier to fix it here since that is how the other a.out targets
10740 align
= bfd_get_section_alignment (stdoutput
, segment
);
10741 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
10748 /* On the i386, PC-relative offsets are relative to the start of the
10749 next instruction. That is, the address of the offset, plus its
10750 size, since the offset is always the last part of the insn. */
10753 md_pcrel_from (fixS
*fixP
)
10755 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10761 s_bss (int ignore ATTRIBUTE_UNUSED
)
10765 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10767 obj_elf_section_change_hook ();
10769 temp
= get_absolute_expression ();
10770 subseg_set (bss_section
, (subsegT
) temp
);
10771 demand_empty_rest_of_line ();
10777 i386_validate_fix (fixS
*fixp
)
10779 if (fixp
->fx_subsy
)
10781 if (fixp
->fx_subsy
== GOT_symbol
)
10783 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10787 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10788 if (fixp
->fx_tcbit2
)
10789 fixp
->fx_r_type
= (fixp
->fx_tcbit
10790 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10791 : BFD_RELOC_X86_64_GOTPCRELX
);
10794 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10799 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10801 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10803 fixp
->fx_subsy
= 0;
10806 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10807 else if (!object_64bit
)
10809 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
10810 && fixp
->fx_tcbit2
)
10811 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
10817 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10820 bfd_reloc_code_real_type code
;
10822 switch (fixp
->fx_r_type
)
10824 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10825 case BFD_RELOC_SIZE32
:
10826 case BFD_RELOC_SIZE64
:
10827 if (S_IS_DEFINED (fixp
->fx_addsy
)
10828 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10830 /* Resolve size relocation against local symbol to size of
10831 the symbol plus addend. */
10832 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10833 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10834 && !fits_in_unsigned_long (value
))
10835 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10836 _("symbol size computation overflow"));
10837 fixp
->fx_addsy
= NULL
;
10838 fixp
->fx_subsy
= NULL
;
10839 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10843 /* Fall through. */
10845 case BFD_RELOC_X86_64_PLT32
:
10846 case BFD_RELOC_X86_64_GOT32
:
10847 case BFD_RELOC_X86_64_GOTPCREL
:
10848 case BFD_RELOC_X86_64_GOTPCRELX
:
10849 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10850 case BFD_RELOC_386_PLT32
:
10851 case BFD_RELOC_386_GOT32
:
10852 case BFD_RELOC_386_GOT32X
:
10853 case BFD_RELOC_386_GOTOFF
:
10854 case BFD_RELOC_386_GOTPC
:
10855 case BFD_RELOC_386_TLS_GD
:
10856 case BFD_RELOC_386_TLS_LDM
:
10857 case BFD_RELOC_386_TLS_LDO_32
:
10858 case BFD_RELOC_386_TLS_IE_32
:
10859 case BFD_RELOC_386_TLS_IE
:
10860 case BFD_RELOC_386_TLS_GOTIE
:
10861 case BFD_RELOC_386_TLS_LE_32
:
10862 case BFD_RELOC_386_TLS_LE
:
10863 case BFD_RELOC_386_TLS_GOTDESC
:
10864 case BFD_RELOC_386_TLS_DESC_CALL
:
10865 case BFD_RELOC_X86_64_TLSGD
:
10866 case BFD_RELOC_X86_64_TLSLD
:
10867 case BFD_RELOC_X86_64_DTPOFF32
:
10868 case BFD_RELOC_X86_64_DTPOFF64
:
10869 case BFD_RELOC_X86_64_GOTTPOFF
:
10870 case BFD_RELOC_X86_64_TPOFF32
:
10871 case BFD_RELOC_X86_64_TPOFF64
:
10872 case BFD_RELOC_X86_64_GOTOFF64
:
10873 case BFD_RELOC_X86_64_GOTPC32
:
10874 case BFD_RELOC_X86_64_GOT64
:
10875 case BFD_RELOC_X86_64_GOTPCREL64
:
10876 case BFD_RELOC_X86_64_GOTPC64
:
10877 case BFD_RELOC_X86_64_GOTPLT64
:
10878 case BFD_RELOC_X86_64_PLTOFF64
:
10879 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10880 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10881 case BFD_RELOC_RVA
:
10882 case BFD_RELOC_VTABLE_ENTRY
:
10883 case BFD_RELOC_VTABLE_INHERIT
:
10885 case BFD_RELOC_32_SECREL
:
10887 code
= fixp
->fx_r_type
;
10889 case BFD_RELOC_X86_64_32S
:
10890 if (!fixp
->fx_pcrel
)
10892 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10893 code
= fixp
->fx_r_type
;
10896 /* Fall through. */
10898 if (fixp
->fx_pcrel
)
10900 switch (fixp
->fx_size
)
10903 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10904 _("can not do %d byte pc-relative relocation"),
10906 code
= BFD_RELOC_32_PCREL
;
10908 case 1: code
= BFD_RELOC_8_PCREL
; break;
10909 case 2: code
= BFD_RELOC_16_PCREL
; break;
10910 case 4: code
= BFD_RELOC_32_PCREL
; break;
10912 case 8: code
= BFD_RELOC_64_PCREL
; break;
10918 switch (fixp
->fx_size
)
10921 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10922 _("can not do %d byte relocation"),
10924 code
= BFD_RELOC_32
;
10926 case 1: code
= BFD_RELOC_8
; break;
10927 case 2: code
= BFD_RELOC_16
; break;
10928 case 4: code
= BFD_RELOC_32
; break;
10930 case 8: code
= BFD_RELOC_64
; break;
10937 if ((code
== BFD_RELOC_32
10938 || code
== BFD_RELOC_32_PCREL
10939 || code
== BFD_RELOC_X86_64_32S
)
10941 && fixp
->fx_addsy
== GOT_symbol
)
10944 code
= BFD_RELOC_386_GOTPC
;
10946 code
= BFD_RELOC_X86_64_GOTPC32
;
10948 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10950 && fixp
->fx_addsy
== GOT_symbol
)
10952 code
= BFD_RELOC_X86_64_GOTPC64
;
10955 rel
= XNEW (arelent
);
10956 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
10957 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10959 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10961 if (!use_rela_relocations
)
10963 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10964 vtable entry to be used in the relocation's section offset. */
10965 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10966 rel
->address
= fixp
->fx_offset
;
10967 #if defined (OBJ_COFF) && defined (TE_PE)
10968 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10969 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10974 /* Use the rela in 64bit mode. */
10977 if (disallow_64bit_reloc
)
10980 case BFD_RELOC_X86_64_DTPOFF64
:
10981 case BFD_RELOC_X86_64_TPOFF64
:
10982 case BFD_RELOC_64_PCREL
:
10983 case BFD_RELOC_X86_64_GOTOFF64
:
10984 case BFD_RELOC_X86_64_GOT64
:
10985 case BFD_RELOC_X86_64_GOTPCREL64
:
10986 case BFD_RELOC_X86_64_GOTPC64
:
10987 case BFD_RELOC_X86_64_GOTPLT64
:
10988 case BFD_RELOC_X86_64_PLTOFF64
:
10989 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10990 _("cannot represent relocation type %s in x32 mode"),
10991 bfd_get_reloc_code_name (code
));
10997 if (!fixp
->fx_pcrel
)
10998 rel
->addend
= fixp
->fx_offset
;
11002 case BFD_RELOC_X86_64_PLT32
:
11003 case BFD_RELOC_X86_64_GOT32
:
11004 case BFD_RELOC_X86_64_GOTPCREL
:
11005 case BFD_RELOC_X86_64_GOTPCRELX
:
11006 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11007 case BFD_RELOC_X86_64_TLSGD
:
11008 case BFD_RELOC_X86_64_TLSLD
:
11009 case BFD_RELOC_X86_64_GOTTPOFF
:
11010 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11011 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11012 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
11015 rel
->addend
= (section
->vma
11017 + fixp
->fx_addnumber
11018 + md_pcrel_from (fixp
));
11023 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11024 if (rel
->howto
== NULL
)
11026 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11027 _("cannot represent relocation type %s"),
11028 bfd_get_reloc_code_name (code
));
11029 /* Set howto to a garbage value so that we can keep going. */
11030 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
11031 gas_assert (rel
->howto
!= NULL
);
11037 #include "tc-i386-intel.c"
11040 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
11042 int saved_naked_reg
;
11043 char saved_register_dot
;
11045 saved_naked_reg
= allow_naked_reg
;
11046 allow_naked_reg
= 1;
11047 saved_register_dot
= register_chars
['.'];
11048 register_chars
['.'] = '.';
11049 allow_pseudo_reg
= 1;
11050 expression_and_evaluate (exp
);
11051 allow_pseudo_reg
= 0;
11052 register_chars
['.'] = saved_register_dot
;
11053 allow_naked_reg
= saved_naked_reg
;
11055 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
11057 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
11059 exp
->X_op
= O_constant
;
11060 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
11061 .dw2_regnum
[flag_code
>> 1];
11064 exp
->X_op
= O_illegal
;
11069 tc_x86_frame_initial_instructions (void)
11071 static unsigned int sp_regno
[2];
11073 if (!sp_regno
[flag_code
>> 1])
11075 char *saved_input
= input_line_pointer
;
11076 char sp
[][4] = {"esp", "rsp"};
11079 input_line_pointer
= sp
[flag_code
>> 1];
11080 tc_x86_parse_to_dw2regnum (&exp
);
11081 gas_assert (exp
.X_op
== O_constant
);
11082 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
11083 input_line_pointer
= saved_input
;
11086 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
11087 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
11091 x86_dwarf2_addr_size (void)
11093 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11094 if (x86_elf_abi
== X86_64_X32_ABI
)
11097 return bfd_arch_bits_per_address (stdoutput
) / 8;
11101 i386_elf_section_type (const char *str
, size_t len
)
11103 if (flag_code
== CODE_64BIT
11104 && len
== sizeof ("unwind") - 1
11105 && strncmp (str
, "unwind", 6) == 0)
11106 return SHT_X86_64_UNWIND
;
11113 i386_solaris_fix_up_eh_frame (segT sec
)
11115 if (flag_code
== CODE_64BIT
)
11116 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
11122 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
11126 exp
.X_op
= O_secrel
;
11127 exp
.X_add_symbol
= symbol
;
11128 exp
.X_add_number
= 0;
11129 emit_expr (&exp
, size
);
11133 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11134 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11137 x86_64_section_letter (int letter
, const char **ptr_msg
)
11139 if (flag_code
== CODE_64BIT
)
11142 return SHF_X86_64_LARGE
;
11144 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11147 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
11152 x86_64_section_word (char *str
, size_t len
)
11154 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
11155 return SHF_X86_64_LARGE
;
11161 handle_large_common (int small ATTRIBUTE_UNUSED
)
11163 if (flag_code
!= CODE_64BIT
)
11165 s_comm_internal (0, elf_common_parse
);
11166 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11170 static segT lbss_section
;
11171 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
11172 asection
*saved_bss_section
= bss_section
;
11174 if (lbss_section
== NULL
)
11176 flagword applicable
;
11177 segT seg
= now_seg
;
11178 subsegT subseg
= now_subseg
;
11180 /* The .lbss section is for local .largecomm symbols. */
11181 lbss_section
= subseg_new (".lbss", 0);
11182 applicable
= bfd_applicable_section_flags (stdoutput
);
11183 bfd_set_section_flags (stdoutput
, lbss_section
,
11184 applicable
& SEC_ALLOC
);
11185 seg_info (lbss_section
)->bss
= 1;
11187 subseg_set (seg
, subseg
);
11190 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
11191 bss_section
= lbss_section
;
11193 s_comm_internal (0, elf_common_parse
);
11195 elf_com_section_ptr
= saved_com_section_ptr
;
11196 bss_section
= saved_bss_section
;
11199 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */