1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef REGISTER_WARNINGS
48 #define REGISTER_WARNINGS 1
51 #ifndef INFER_ADDR_PREFIX
52 #define INFER_ADDR_PREFIX 1
56 #define DEFAULT_ARCH "i386"
61 #define INLINE __inline__
67 /* Prefixes will be emitted in the order defined below.
68 WAIT_PREFIX must be the first prefix since FWAIT is really is an
69 instruction, and so must come before any prefixes.
70 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
71 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
77 #define HLE_PREFIX REP_PREFIX
78 #define BND_PREFIX REP_PREFIX
80 #define REX_PREFIX 6 /* must come last. */
81 #define MAX_PREFIXES 7 /* max prefixes per opcode */
83 /* we define the syntax here (modulo base,index,scale syntax) */
84 #define REGISTER_PREFIX '%'
85 #define IMMEDIATE_PREFIX '$'
86 #define ABSOLUTE_PREFIX '*'
88 /* these are the instruction mnemonic suffixes in AT&T syntax or
89 memory operand size in Intel syntax. */
90 #define WORD_MNEM_SUFFIX 'w'
91 #define BYTE_MNEM_SUFFIX 'b'
92 #define SHORT_MNEM_SUFFIX 's'
93 #define LONG_MNEM_SUFFIX 'l'
94 #define QWORD_MNEM_SUFFIX 'q'
95 /* Intel Syntax. Use a non-ascii letter since since it never appears
97 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
99 #define END_OF_INSN '\0'
102 'templates' is for grouping together 'template' structures for opcodes
103 of the same name. This is only used for storing the insns in the grand
104 ole hash table of insns.
105 The templates themselves start at START and range up to (but not including)
110 const insn_template
*start
;
111 const insn_template
*end
;
115 /* 386 operand encoding bytes: see 386 book for details of this. */
118 unsigned int regmem
; /* codes register or memory operand */
119 unsigned int reg
; /* codes register operand (or extended opcode) */
120 unsigned int mode
; /* how to interpret regmem & reg */
124 /* x86-64 extension prefix. */
125 typedef int rex_byte
;
127 /* 386 opcode byte to code indirect addressing. */
136 /* x86 arch names, types and features */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 enum processor_type type
; /* arch type */
142 i386_cpu_flags flags
; /* cpu feature flags */
143 unsigned int skip
; /* show_arch should skip this. */
147 /* Used to turn off indicated flags. */
150 const char *name
; /* arch name */
151 unsigned int len
; /* arch string length */
152 i386_cpu_flags flags
; /* cpu feature flags */
156 static void update_code_flag (int, int);
157 static void set_code_flag (int);
158 static void set_16bit_gcc_code_flag (int);
159 static void set_intel_syntax (int);
160 static void set_intel_mnemonic (int);
161 static void set_allow_index_reg (int);
162 static void set_check (int);
163 static void set_cpu_arch (int);
165 static void pe_directive_secrel (int);
167 static void signed_cons (int);
168 static char *output_invalid (int c
);
169 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
171 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
173 static int i386_att_operand (char *);
174 static int i386_intel_operand (char *, int);
175 static int i386_intel_simplify (expressionS
*);
176 static int i386_intel_parse_name (const char *, expressionS
*);
177 static const reg_entry
*parse_register (char *, char **);
178 static char *parse_insn (char *, char *);
179 static char *parse_operands (char *, const char *);
180 static void swap_operands (void);
181 static void swap_2_operands (int, int);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* This struct describes rounding control and SAE in the instruction. */
227 static struct RC_Operation rc_op
;
229 /* The struct describes masking, applied to OPERAND in the instruction.
230 MASK is a pointer to the corresponding mask register. ZEROING tells
231 whether merging or zeroing mask is used. */
232 struct Mask_Operation
234 const reg_entry
*mask
;
235 unsigned int zeroing
;
236 /* The operand where this operation is associated. */
240 static struct Mask_Operation mask_op
;
242 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
244 struct Broadcast_Operation
246 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
249 /* Index of broadcasted operand. */
252 /* Number of bytes to broadcast. */
256 static struct Broadcast_Operation broadcast_op
;
261 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
262 unsigned char bytes
[4];
264 /* Destination or source register specifier. */
265 const reg_entry
*register_specifier
;
268 /* 'md_assemble ()' gathers together information and puts it into a
275 const reg_entry
*regs
;
280 operand_size_mismatch
,
281 operand_type_mismatch
,
282 register_type_mismatch
,
283 number_of_operands_mismatch
,
284 invalid_instruction_suffix
,
286 unsupported_with_intel_mnemonic
,
289 invalid_vsib_address
,
290 invalid_vector_register_set
,
291 unsupported_vector_index_register
,
292 unsupported_broadcast
,
295 mask_not_on_destination
,
298 rc_sae_operand_not_last_imm
,
299 invalid_register_operand
,
304 /* TM holds the template for the insn were currently assembling. */
307 /* SUFFIX holds the instruction size suffix for byte, word, dword
308 or qword, if given. */
311 /* OPERANDS gives the number of given operands. */
312 unsigned int operands
;
314 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
315 of given register, displacement, memory operands and immediate
317 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
319 /* TYPES [i] is the type (see above #defines) which tells us how to
320 use OP[i] for the corresponding operand. */
321 i386_operand_type types
[MAX_OPERANDS
];
323 /* Displacement expression, immediate expression, or register for each
325 union i386_op op
[MAX_OPERANDS
];
327 /* Flags for operands. */
328 unsigned int flags
[MAX_OPERANDS
];
329 #define Operand_PCrel 1
330 #define Operand_Mem 2
332 /* Relocation type for operand */
333 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
335 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
336 the base index byte below. */
337 const reg_entry
*base_reg
;
338 const reg_entry
*index_reg
;
339 unsigned int log2_scale_factor
;
341 /* SEG gives the seg_entries of this insn. They are zero unless
342 explicit segment overrides are given. */
343 const seg_entry
*seg
[2];
345 /* Copied first memory operand string, for re-checking. */
348 /* PREFIX holds all the given prefix opcodes (usually null).
349 PREFIXES is the number of prefix opcodes. */
350 unsigned int prefixes
;
351 unsigned char prefix
[MAX_PREFIXES
];
353 /* Has MMX register operands. */
354 bfd_boolean has_regmmx
;
356 /* Has XMM register operands. */
357 bfd_boolean has_regxmm
;
359 /* Has YMM register operands. */
360 bfd_boolean has_regymm
;
362 /* Has ZMM register operands. */
363 bfd_boolean has_regzmm
;
365 /* RM and SIB are the modrm byte and the sib byte where the
366 addressing modes of this insn are encoded. */
373 /* Masking attributes. */
374 struct Mask_Operation
*mask
;
376 /* Rounding control and SAE attributes. */
377 struct RC_Operation
*rounding
;
379 /* Broadcasting attributes. */
380 struct Broadcast_Operation
*broadcast
;
382 /* Compressed disp8*N attribute. */
383 unsigned int memshift
;
385 /* Prefer load or store in encoding. */
388 dir_encoding_default
= 0,
394 /* Prefer 8bit or 32bit displacement in encoding. */
397 disp_encoding_default
= 0,
402 /* Prefer the REX byte in encoding. */
403 bfd_boolean rex_encoding
;
405 /* Disable instruction size optimization. */
406 bfd_boolean no_optimize
;
408 /* How to encode vector instructions. */
411 vex_encoding_default
= 0,
418 const char *rep_prefix
;
421 const char *hle_prefix
;
423 /* Have BND prefix. */
424 const char *bnd_prefix
;
426 /* Have NOTRACK prefix. */
427 const char *notrack_prefix
;
430 enum i386_error error
;
433 typedef struct _i386_insn i386_insn
;
435 /* Link RC type with corresponding string, that'll be looked for in
444 static const struct RC_name RC_NamesTable
[] =
446 { rne
, STRING_COMMA_LEN ("rn-sae") },
447 { rd
, STRING_COMMA_LEN ("rd-sae") },
448 { ru
, STRING_COMMA_LEN ("ru-sae") },
449 { rz
, STRING_COMMA_LEN ("rz-sae") },
450 { saeonly
, STRING_COMMA_LEN ("sae") },
453 /* List of chars besides those in app.c:symbol_chars that can start an
454 operand. Used to prevent the scrubber eating vital white-space. */
455 const char extra_symbol_chars
[] = "*%-([{}"
464 #if (defined (TE_I386AIX) \
465 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
466 && !defined (TE_GNU) \
467 && !defined (TE_LINUX) \
468 && !defined (TE_NACL) \
469 && !defined (TE_FreeBSD) \
470 && !defined (TE_DragonFly) \
471 && !defined (TE_NetBSD)))
472 /* This array holds the chars that always start a comment. If the
473 pre-processor is disabled, these aren't very useful. The option
474 --divide will remove '/' from this list. */
475 const char *i386_comment_chars
= "#/";
476 #define SVR4_COMMENT_CHARS 1
477 #define PREFIX_SEPARATOR '\\'
480 const char *i386_comment_chars
= "#";
481 #define PREFIX_SEPARATOR '/'
484 /* This array holds the chars that only start a comment at the beginning of
485 a line. If the line seems to have the form '# 123 filename'
486 .line and .file directives will appear in the pre-processed output.
487 Note that input_file.c hand checks for '#' at the beginning of the
488 first line of the input file. This is because the compiler outputs
489 #NO_APP at the beginning of its output.
490 Also note that comments started like this one will always work if
491 '/' isn't otherwise defined. */
492 const char line_comment_chars
[] = "#/";
494 const char line_separator_chars
[] = ";";
496 /* Chars that can be used to separate mant from exp in floating point
498 const char EXP_CHARS
[] = "eE";
500 /* Chars that mean this number is a floating point constant
503 const char FLT_CHARS
[] = "fFdDxX";
505 /* Tables for lexical analysis. */
506 static char mnemonic_chars
[256];
507 static char register_chars
[256];
508 static char operand_chars
[256];
509 static char identifier_chars
[256];
510 static char digit_chars
[256];
512 /* Lexical macros. */
513 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
514 #define is_operand_char(x) (operand_chars[(unsigned char) x])
515 #define is_register_char(x) (register_chars[(unsigned char) x])
516 #define is_space_char(x) ((x) == ' ')
517 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
518 #define is_digit_char(x) (digit_chars[(unsigned char) x])
520 /* All non-digit non-letter characters that may occur in an operand. */
521 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
523 /* md_assemble() always leaves the strings it's passed unaltered. To
524 effect this we maintain a stack of saved characters that we've smashed
525 with '\0's (indicating end of strings for various sub-fields of the
526 assembler instruction). */
527 static char save_stack
[32];
528 static char *save_stack_p
;
529 #define END_STRING_AND_SAVE(s) \
530 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
531 #define RESTORE_END_STRING(s) \
532 do { *(s) = *--save_stack_p; } while (0)
534 /* The instruction we're assembling. */
537 /* Possible templates for current insn. */
538 static const templates
*current_templates
;
540 /* Per instruction expressionS buffers: max displacements & immediates. */
541 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
542 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
544 /* Current operand we are working on. */
545 static int this_operand
= -1;
547 /* We support four different modes. FLAG_CODE variable is used to distinguish
555 static enum flag_code flag_code
;
556 static unsigned int object_64bit
;
557 static unsigned int disallow_64bit_reloc
;
558 static int use_rela_relocations
= 0;
560 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
561 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
562 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
564 /* The ELF ABI to use. */
572 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
575 #if defined (TE_PE) || defined (TE_PEP)
576 /* Use big object file format. */
577 static int use_big_obj
= 0;
580 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
581 /* 1 if generating code for a shared library. */
582 static int shared
= 0;
585 /* 1 for intel syntax,
587 static int intel_syntax
= 0;
589 /* 1 for Intel64 ISA,
593 /* 1 for intel mnemonic,
594 0 if att mnemonic. */
595 static int intel_mnemonic
= !SYSV386_COMPAT
;
597 /* 1 if pseudo registers are permitted. */
598 static int allow_pseudo_reg
= 0;
600 /* 1 if register prefix % not required. */
601 static int allow_naked_reg
= 0;
603 /* 1 if the assembler should add BND prefix for all control-transferring
604 instructions supporting it, even if this prefix wasn't specified
606 static int add_bnd_prefix
= 0;
608 /* 1 if pseudo index register, eiz/riz, is allowed . */
609 static int allow_index_reg
= 0;
611 /* 1 if the assembler should ignore LOCK prefix, even if it was
612 specified explicitly. */
613 static int omit_lock_prefix
= 0;
615 /* 1 if the assembler should encode lfence, mfence, and sfence as
616 "lock addl $0, (%{re}sp)". */
617 static int avoid_fence
= 0;
619 /* 1 if the assembler should generate relax relocations. */
621 static int generate_relax_relocations
622 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
624 static enum check_kind
630 sse_check
, operand_check
= check_warning
;
633 1. Clear the REX_W bit with register operand if possible.
634 2. Above plus use 128bit vector instruction to clear the full vector
637 static int optimize
= 0;
640 1. Clear the REX_W bit with register operand if possible.
641 2. Above plus use 128bit vector instruction to clear the full vector
643 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
646 static int optimize_for_space
= 0;
648 /* Register prefix used for error message. */
649 static const char *register_prefix
= "%";
651 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
652 leave, push, and pop instructions so that gcc has the same stack
653 frame as in 32 bit mode. */
654 static char stackop_size
= '\0';
656 /* Non-zero to optimize code alignment. */
657 int optimize_align_code
= 1;
659 /* Non-zero to quieten some warnings. */
660 static int quiet_warnings
= 0;
663 static const char *cpu_arch_name
= NULL
;
664 static char *cpu_sub_arch_name
= NULL
;
666 /* CPU feature flags. */
667 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
669 /* If we have selected a cpu we are generating instructions for. */
670 static int cpu_arch_tune_set
= 0;
672 /* Cpu we are generating instructions for. */
673 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
675 /* CPU feature flags of cpu we are generating instructions for. */
676 static i386_cpu_flags cpu_arch_tune_flags
;
678 /* CPU instruction set architecture used. */
679 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
681 /* CPU feature flags of instruction set architecture used. */
682 i386_cpu_flags cpu_arch_isa_flags
;
684 /* If set, conditional jumps are not automatically promoted to handle
685 larger than a byte offset. */
686 static unsigned int no_cond_jump_promotion
= 0;
688 /* Encode SSE instructions with VEX prefix. */
689 static unsigned int sse2avx
;
691 /* Encode scalar AVX instructions with specific vector length. */
698 /* Encode VEX WIG instructions with specific vex.w. */
705 /* Encode scalar EVEX LIG instructions with specific vector length. */
713 /* Encode EVEX WIG instructions with specific evex.w. */
720 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
721 static enum rc_type evexrcig
= rne
;
723 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
724 static symbolS
*GOT_symbol
;
726 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
727 unsigned int x86_dwarf2_return_column
;
729 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
730 int x86_cie_data_alignment
;
732 /* Interface to relax_segment.
733 There are 3 major relax states for 386 jump insns because the
734 different types of jumps add different sizes to frags when we're
735 figuring out what sort of jump to choose to reach a given label. */
738 #define UNCOND_JUMP 0
740 #define COND_JUMP86 2
745 #define SMALL16 (SMALL | CODE16)
747 #define BIG16 (BIG | CODE16)
751 #define INLINE __inline__
757 #define ENCODE_RELAX_STATE(type, size) \
758 ((relax_substateT) (((type) << 2) | (size)))
759 #define TYPE_FROM_RELAX_STATE(s) \
761 #define DISP_SIZE_FROM_RELAX_STATE(s) \
762 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
764 /* This table is used by relax_frag to promote short jumps to long
765 ones where necessary. SMALL (short) jumps may be promoted to BIG
766 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
767 don't allow a short jump in a 32 bit code segment to be promoted to
768 a 16 bit offset jump because it's slower (requires data size
769 prefix), and doesn't work, unless the destination is in the bottom
770 64k of the code segment (The top 16 bits of eip are zeroed). */
772 const relax_typeS md_relax_table
[] =
775 1) most positive reach of this state,
776 2) most negative reach of this state,
777 3) how many bytes this mode will have in the variable part of the frag
778 4) which index into the table to try if we can't fit into this one. */
780 /* UNCOND_JUMP states. */
781 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
782 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
783 /* dword jmp adds 4 bytes to frag:
784 0 extra opcode bytes, 4 displacement bytes. */
786 /* word jmp adds 2 byte2 to frag:
787 0 extra opcode bytes, 2 displacement bytes. */
790 /* COND_JUMP states. */
791 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
792 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
793 /* dword conditionals adds 5 bytes to frag:
794 1 extra opcode byte, 4 displacement bytes. */
796 /* word conditionals add 3 bytes to frag:
797 1 extra opcode byte, 2 displacement bytes. */
800 /* COND_JUMP86 states. */
801 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
802 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
803 /* dword conditionals adds 5 bytes to frag:
804 1 extra opcode byte, 4 displacement bytes. */
806 /* word conditionals add 4 bytes to frag:
807 1 displacement byte and a 3 byte long branch insn. */
811 static const arch_entry cpu_arch
[] =
813 /* Do not replace the first two entries - i386_target_format()
814 relies on them being there in this order. */
815 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
816 CPU_GENERIC32_FLAGS
, 0 },
817 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
818 CPU_GENERIC64_FLAGS
, 0 },
819 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
821 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
823 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
825 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
827 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
829 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
831 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
833 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
835 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
836 CPU_PENTIUMPRO_FLAGS
, 0 },
837 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
839 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
841 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
843 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
845 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
846 CPU_NOCONA_FLAGS
, 0 },
847 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
849 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
851 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
852 CPU_CORE2_FLAGS
, 1 },
853 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
854 CPU_CORE2_FLAGS
, 0 },
855 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
856 CPU_COREI7_FLAGS
, 0 },
857 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
859 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
861 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
862 CPU_IAMCU_FLAGS
, 0 },
863 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
865 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
867 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
868 CPU_ATHLON_FLAGS
, 0 },
869 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
871 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
873 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
875 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
876 CPU_AMDFAM10_FLAGS
, 0 },
877 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
878 CPU_BDVER1_FLAGS
, 0 },
879 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
880 CPU_BDVER2_FLAGS
, 0 },
881 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
882 CPU_BDVER3_FLAGS
, 0 },
883 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
884 CPU_BDVER4_FLAGS
, 0 },
885 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
886 CPU_ZNVER1_FLAGS
, 0 },
887 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
888 CPU_ZNVER2_FLAGS
, 0 },
889 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
890 CPU_BTVER1_FLAGS
, 0 },
891 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
892 CPU_BTVER2_FLAGS
, 0 },
893 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
895 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
897 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
899 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
901 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
903 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
905 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
907 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
909 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
911 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
913 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
914 CPU_SSSE3_FLAGS
, 0 },
915 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
916 CPU_SSE4_1_FLAGS
, 0 },
917 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
918 CPU_SSE4_2_FLAGS
, 0 },
919 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
920 CPU_SSE4_2_FLAGS
, 0 },
921 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
923 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
925 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
926 CPU_AVX512F_FLAGS
, 0 },
927 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
928 CPU_AVX512CD_FLAGS
, 0 },
929 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
930 CPU_AVX512ER_FLAGS
, 0 },
931 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
932 CPU_AVX512PF_FLAGS
, 0 },
933 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
934 CPU_AVX512DQ_FLAGS
, 0 },
935 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
936 CPU_AVX512BW_FLAGS
, 0 },
937 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
938 CPU_AVX512VL_FLAGS
, 0 },
939 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
941 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
942 CPU_VMFUNC_FLAGS
, 0 },
943 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
945 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
946 CPU_XSAVE_FLAGS
, 0 },
947 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
948 CPU_XSAVEOPT_FLAGS
, 0 },
949 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
950 CPU_XSAVEC_FLAGS
, 0 },
951 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
952 CPU_XSAVES_FLAGS
, 0 },
953 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
955 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
956 CPU_PCLMUL_FLAGS
, 0 },
957 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
958 CPU_PCLMUL_FLAGS
, 1 },
959 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
960 CPU_FSGSBASE_FLAGS
, 0 },
961 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
962 CPU_RDRND_FLAGS
, 0 },
963 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
965 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
967 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
969 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
971 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
973 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
975 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
976 CPU_MOVBE_FLAGS
, 0 },
977 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
979 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
981 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
982 CPU_LZCNT_FLAGS
, 0 },
983 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
985 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
987 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
988 CPU_INVPCID_FLAGS
, 0 },
989 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
990 CPU_CLFLUSH_FLAGS
, 0 },
991 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
993 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
994 CPU_SYSCALL_FLAGS
, 0 },
995 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
996 CPU_RDTSCP_FLAGS
, 0 },
997 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
998 CPU_3DNOW_FLAGS
, 0 },
999 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1000 CPU_3DNOWA_FLAGS
, 0 },
1001 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1002 CPU_PADLOCK_FLAGS
, 0 },
1003 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1004 CPU_SVME_FLAGS
, 1 },
1005 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1006 CPU_SVME_FLAGS
, 0 },
1007 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1008 CPU_SSE4A_FLAGS
, 0 },
1009 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1011 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1013 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1015 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1017 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1018 CPU_RDSEED_FLAGS
, 0 },
1019 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1020 CPU_PRFCHW_FLAGS
, 0 },
1021 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1022 CPU_SMAP_FLAGS
, 0 },
1023 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1025 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1027 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1028 CPU_CLFLUSHOPT_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1030 CPU_PREFETCHWT1_FLAGS
, 0 },
1031 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1033 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1034 CPU_CLWB_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1036 CPU_AVX512IFMA_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1038 CPU_AVX512VBMI_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1040 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1042 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1044 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1046 CPU_AVX512_VBMI2_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1048 CPU_AVX512_VNNI_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1050 CPU_AVX512_BITALG_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1052 CPU_CLZERO_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1054 CPU_MWAITX_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1056 CPU_OSPKE_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1058 CPU_RDPID_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1060 CPU_PTWRITE_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1063 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1064 CPU_SHSTK_FLAGS
, 0 },
1065 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1066 CPU_GFNI_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1068 CPU_VAES_FLAGS
, 0 },
1069 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1070 CPU_VPCLMULQDQ_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1072 CPU_WBNOINVD_FLAGS
, 0 },
1073 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1074 CPU_PCONFIG_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1076 CPU_WAITPKG_FLAGS
, 0 },
1077 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1078 CPU_CLDEMOTE_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1080 CPU_MOVDIRI_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1082 CPU_MOVDIR64B_FLAGS
, 0 },
1083 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1084 CPU_AVX512_BF16_FLAGS
, 0 },
1085 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1086 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1087 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1088 CPU_ENQCMD_FLAGS
, 0 },
1091 static const noarch_entry cpu_noarch
[] =
1093 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1094 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1095 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1096 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1097 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1098 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1099 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1100 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1101 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1102 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1103 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1104 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1105 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1106 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1107 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1108 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1109 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1110 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1111 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1112 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1113 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1114 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1115 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1116 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1117 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1118 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1119 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1120 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1121 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1122 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1123 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1124 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1125 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1126 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1127 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1128 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1129 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1130 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1134 /* Like s_lcomm_internal in gas/read.c but the alignment string
1135 is allowed to be optional. */
1138 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1145 && *input_line_pointer
== ',')
1147 align
= parse_align (needs_align
- 1);
1149 if (align
== (addressT
) -1)
1164 bss_alloc (symbolP
, size
, align
);
1169 pe_lcomm (int needs_align
)
1171 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1175 const pseudo_typeS md_pseudo_table
[] =
1177 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1178 {"align", s_align_bytes
, 0},
1180 {"align", s_align_ptwo
, 0},
1182 {"arch", set_cpu_arch
, 0},
1186 {"lcomm", pe_lcomm
, 1},
1188 {"ffloat", float_cons
, 'f'},
1189 {"dfloat", float_cons
, 'd'},
1190 {"tfloat", float_cons
, 'x'},
1192 {"slong", signed_cons
, 4},
1193 {"noopt", s_ignore
, 0},
1194 {"optim", s_ignore
, 0},
1195 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1196 {"code16", set_code_flag
, CODE_16BIT
},
1197 {"code32", set_code_flag
, CODE_32BIT
},
1199 {"code64", set_code_flag
, CODE_64BIT
},
1201 {"intel_syntax", set_intel_syntax
, 1},
1202 {"att_syntax", set_intel_syntax
, 0},
1203 {"intel_mnemonic", set_intel_mnemonic
, 1},
1204 {"att_mnemonic", set_intel_mnemonic
, 0},
1205 {"allow_index_reg", set_allow_index_reg
, 1},
1206 {"disallow_index_reg", set_allow_index_reg
, 0},
1207 {"sse_check", set_check
, 0},
1208 {"operand_check", set_check
, 1},
1209 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1210 {"largecomm", handle_large_common
, 0},
1212 {"file", dwarf2_directive_file
, 0},
1213 {"loc", dwarf2_directive_loc
, 0},
1214 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1217 {"secrel32", pe_directive_secrel
, 0},
1222 /* For interface with expression (). */
1223 extern char *input_line_pointer
;
1225 /* Hash table for instruction mnemonic lookup. */
1226 static struct hash_control
*op_hash
;
1228 /* Hash table for register lookup. */
1229 static struct hash_control
*reg_hash
;
1231 /* Various efficient no-op patterns for aligning code labels.
1232 Note: Don't try to assemble the instructions in the comments.
1233 0L and 0w are not legal. */
1234 static const unsigned char f32_1
[] =
1236 static const unsigned char f32_2
[] =
1237 {0x66,0x90}; /* xchg %ax,%ax */
1238 static const unsigned char f32_3
[] =
1239 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1240 static const unsigned char f32_4
[] =
1241 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1242 static const unsigned char f32_6
[] =
1243 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1244 static const unsigned char f32_7
[] =
1245 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1246 static const unsigned char f16_3
[] =
1247 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1248 static const unsigned char f16_4
[] =
1249 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1250 static const unsigned char jump_disp8
[] =
1251 {0xeb}; /* jmp disp8 */
1252 static const unsigned char jump32_disp32
[] =
1253 {0xe9}; /* jmp disp32 */
1254 static const unsigned char jump16_disp32
[] =
1255 {0x66,0xe9}; /* jmp disp32 */
1256 /* 32-bit NOPs patterns. */
1257 static const unsigned char *const f32_patt
[] = {
1258 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1260 /* 16-bit NOPs patterns. */
1261 static const unsigned char *const f16_patt
[] = {
1262 f32_1
, f32_2
, f16_3
, f16_4
1264 /* nopl (%[re]ax) */
1265 static const unsigned char alt_3
[] =
1267 /* nopl 0(%[re]ax) */
1268 static const unsigned char alt_4
[] =
1269 {0x0f,0x1f,0x40,0x00};
1270 /* nopl 0(%[re]ax,%[re]ax,1) */
1271 static const unsigned char alt_5
[] =
1272 {0x0f,0x1f,0x44,0x00,0x00};
1273 /* nopw 0(%[re]ax,%[re]ax,1) */
1274 static const unsigned char alt_6
[] =
1275 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1276 /* nopl 0L(%[re]ax) */
1277 static const unsigned char alt_7
[] =
1278 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1279 /* nopl 0L(%[re]ax,%[re]ax,1) */
1280 static const unsigned char alt_8
[] =
1281 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1282 /* nopw 0L(%[re]ax,%[re]ax,1) */
1283 static const unsigned char alt_9
[] =
1284 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1285 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1286 static const unsigned char alt_10
[] =
1287 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1288 /* data16 nopw %cs:0L(%eax,%eax,1) */
1289 static const unsigned char alt_11
[] =
1290 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1291 /* 32-bit and 64-bit NOPs patterns. */
1292 static const unsigned char *const alt_patt
[] = {
1293 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1294 alt_9
, alt_10
, alt_11
1297 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1298 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1301 i386_output_nops (char *where
, const unsigned char *const *patt
,
1302 int count
, int max_single_nop_size
)
1305 /* Place the longer NOP first. */
1308 const unsigned char *nops
;
1310 if (max_single_nop_size
< 1)
1312 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1313 max_single_nop_size
);
1317 nops
= patt
[max_single_nop_size
- 1];
1319 /* Use the smaller one if the requsted one isn't available. */
1322 max_single_nop_size
--;
1323 nops
= patt
[max_single_nop_size
- 1];
1326 last
= count
% max_single_nop_size
;
1329 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1330 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1334 nops
= patt
[last
- 1];
1337 /* Use the smaller one plus one-byte NOP if the needed one
1340 nops
= patt
[last
- 1];
1341 memcpy (where
+ offset
, nops
, last
);
1342 where
[offset
+ last
] = *patt
[0];
1345 memcpy (where
+ offset
, nops
, last
);
1350 fits_in_imm7 (offsetT num
)
1352 return (num
& 0x7f) == num
;
1356 fits_in_imm31 (offsetT num
)
1358 return (num
& 0x7fffffff) == num
;
1361 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1362 single NOP instruction LIMIT. */
1365 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1367 const unsigned char *const *patt
= NULL
;
1368 int max_single_nop_size
;
1369 /* Maximum number of NOPs before switching to jump over NOPs. */
1370 int max_number_of_nops
;
1372 switch (fragP
->fr_type
)
1381 /* We need to decide which NOP sequence to use for 32bit and
1382 64bit. When -mtune= is used:
1384 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1385 PROCESSOR_GENERIC32, f32_patt will be used.
1386 2. For the rest, alt_patt will be used.
1388 When -mtune= isn't used, alt_patt will be used if
1389 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1392 When -march= or .arch is used, we can't use anything beyond
1393 cpu_arch_isa_flags. */
1395 if (flag_code
== CODE_16BIT
)
1398 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1399 /* Limit number of NOPs to 2 in 16-bit mode. */
1400 max_number_of_nops
= 2;
1404 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1406 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1407 switch (cpu_arch_tune
)
1409 case PROCESSOR_UNKNOWN
:
1410 /* We use cpu_arch_isa_flags to check if we SHOULD
1411 optimize with nops. */
1412 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1417 case PROCESSOR_PENTIUM4
:
1418 case PROCESSOR_NOCONA
:
1419 case PROCESSOR_CORE
:
1420 case PROCESSOR_CORE2
:
1421 case PROCESSOR_COREI7
:
1422 case PROCESSOR_L1OM
:
1423 case PROCESSOR_K1OM
:
1424 case PROCESSOR_GENERIC64
:
1426 case PROCESSOR_ATHLON
:
1428 case PROCESSOR_AMDFAM10
:
1430 case PROCESSOR_ZNVER
:
1434 case PROCESSOR_I386
:
1435 case PROCESSOR_I486
:
1436 case PROCESSOR_PENTIUM
:
1437 case PROCESSOR_PENTIUMPRO
:
1438 case PROCESSOR_IAMCU
:
1439 case PROCESSOR_GENERIC32
:
1446 switch (fragP
->tc_frag_data
.tune
)
1448 case PROCESSOR_UNKNOWN
:
1449 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1450 PROCESSOR_UNKNOWN. */
1454 case PROCESSOR_I386
:
1455 case PROCESSOR_I486
:
1456 case PROCESSOR_PENTIUM
:
1457 case PROCESSOR_IAMCU
:
1459 case PROCESSOR_ATHLON
:
1461 case PROCESSOR_AMDFAM10
:
1463 case PROCESSOR_ZNVER
:
1465 case PROCESSOR_GENERIC32
:
1466 /* We use cpu_arch_isa_flags to check if we CAN optimize
1468 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1473 case PROCESSOR_PENTIUMPRO
:
1474 case PROCESSOR_PENTIUM4
:
1475 case PROCESSOR_NOCONA
:
1476 case PROCESSOR_CORE
:
1477 case PROCESSOR_CORE2
:
1478 case PROCESSOR_COREI7
:
1479 case PROCESSOR_L1OM
:
1480 case PROCESSOR_K1OM
:
1481 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1486 case PROCESSOR_GENERIC64
:
1492 if (patt
== f32_patt
)
1494 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1495 /* Limit number of NOPs to 2 for older processors. */
1496 max_number_of_nops
= 2;
1500 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1501 /* Limit number of NOPs to 7 for newer processors. */
1502 max_number_of_nops
= 7;
1507 limit
= max_single_nop_size
;
1509 if (fragP
->fr_type
== rs_fill_nop
)
1511 /* Output NOPs for .nop directive. */
1512 if (limit
> max_single_nop_size
)
1514 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1515 _("invalid single nop size: %d "
1516 "(expect within [0, %d])"),
1517 limit
, max_single_nop_size
);
1522 fragP
->fr_var
= count
;
1524 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1526 /* Generate jump over NOPs. */
1527 offsetT disp
= count
- 2;
1528 if (fits_in_imm7 (disp
))
1530 /* Use "jmp disp8" if possible. */
1532 where
[0] = jump_disp8
[0];
1538 unsigned int size_of_jump
;
1540 if (flag_code
== CODE_16BIT
)
1542 where
[0] = jump16_disp32
[0];
1543 where
[1] = jump16_disp32
[1];
1548 where
[0] = jump32_disp32
[0];
1552 count
-= size_of_jump
+ 4;
1553 if (!fits_in_imm31 (count
))
1555 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1556 _("jump over nop padding out of range"));
1560 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1561 where
+= size_of_jump
+ 4;
1565 /* Generate multiple NOPs. */
1566 i386_output_nops (where
, patt
, count
, limit
);
1570 operand_type_all_zero (const union i386_operand_type
*x
)
1572 switch (ARRAY_SIZE(x
->array
))
1583 return !x
->array
[0];
1590 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1592 switch (ARRAY_SIZE(x
->array
))
1610 operand_type_equal (const union i386_operand_type
*x
,
1611 const union i386_operand_type
*y
)
1613 switch (ARRAY_SIZE(x
->array
))
1616 if (x
->array
[2] != y
->array
[2])
1620 if (x
->array
[1] != y
->array
[1])
1624 return x
->array
[0] == y
->array
[0];
1632 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1634 switch (ARRAY_SIZE(x
->array
))
1649 return !x
->array
[0];
1656 cpu_flags_equal (const union i386_cpu_flags
*x
,
1657 const union i386_cpu_flags
*y
)
1659 switch (ARRAY_SIZE(x
->array
))
1662 if (x
->array
[3] != y
->array
[3])
1666 if (x
->array
[2] != y
->array
[2])
1670 if (x
->array
[1] != y
->array
[1])
1674 return x
->array
[0] == y
->array
[0];
1682 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1684 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1685 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1688 static INLINE i386_cpu_flags
1689 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1691 switch (ARRAY_SIZE (x
.array
))
1694 x
.array
[3] &= y
.array
[3];
1697 x
.array
[2] &= y
.array
[2];
1700 x
.array
[1] &= y
.array
[1];
1703 x
.array
[0] &= y
.array
[0];
1711 static INLINE i386_cpu_flags
1712 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1714 switch (ARRAY_SIZE (x
.array
))
1717 x
.array
[3] |= y
.array
[3];
1720 x
.array
[2] |= y
.array
[2];
1723 x
.array
[1] |= y
.array
[1];
1726 x
.array
[0] |= y
.array
[0];
1734 static INLINE i386_cpu_flags
1735 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1737 switch (ARRAY_SIZE (x
.array
))
1740 x
.array
[3] &= ~y
.array
[3];
1743 x
.array
[2] &= ~y
.array
[2];
1746 x
.array
[1] &= ~y
.array
[1];
1749 x
.array
[0] &= ~y
.array
[0];
1757 #define CPU_FLAGS_ARCH_MATCH 0x1
1758 #define CPU_FLAGS_64BIT_MATCH 0x2
1760 #define CPU_FLAGS_PERFECT_MATCH \
1761 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1763 /* Return CPU flags match bits. */
1766 cpu_flags_match (const insn_template
*t
)
1768 i386_cpu_flags x
= t
->cpu_flags
;
1769 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1771 x
.bitfield
.cpu64
= 0;
1772 x
.bitfield
.cpuno64
= 0;
1774 if (cpu_flags_all_zero (&x
))
1776 /* This instruction is available on all archs. */
1777 match
|= CPU_FLAGS_ARCH_MATCH
;
1781 /* This instruction is available only on some archs. */
1782 i386_cpu_flags cpu
= cpu_arch_flags
;
1784 /* AVX512VL is no standalone feature - match it and then strip it. */
1785 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1787 x
.bitfield
.cpuavx512vl
= 0;
1789 cpu
= cpu_flags_and (x
, cpu
);
1790 if (!cpu_flags_all_zero (&cpu
))
1792 if (x
.bitfield
.cpuavx
)
1794 /* We need to check a few extra flags with AVX. */
1795 if (cpu
.bitfield
.cpuavx
1796 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1797 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1798 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1799 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1800 match
|= CPU_FLAGS_ARCH_MATCH
;
1802 else if (x
.bitfield
.cpuavx512f
)
1804 /* We need to check a few extra flags with AVX512F. */
1805 if (cpu
.bitfield
.cpuavx512f
1806 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1807 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1808 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1809 match
|= CPU_FLAGS_ARCH_MATCH
;
1812 match
|= CPU_FLAGS_ARCH_MATCH
;
1818 static INLINE i386_operand_type
1819 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1821 switch (ARRAY_SIZE (x
.array
))
1824 x
.array
[2] &= y
.array
[2];
1827 x
.array
[1] &= y
.array
[1];
1830 x
.array
[0] &= y
.array
[0];
1838 static INLINE i386_operand_type
1839 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1841 switch (ARRAY_SIZE (x
.array
))
1844 x
.array
[2] &= ~y
.array
[2];
1847 x
.array
[1] &= ~y
.array
[1];
1850 x
.array
[0] &= ~y
.array
[0];
1858 static INLINE i386_operand_type
1859 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1861 switch (ARRAY_SIZE (x
.array
))
1864 x
.array
[2] |= y
.array
[2];
1867 x
.array
[1] |= y
.array
[1];
1870 x
.array
[0] |= y
.array
[0];
1878 static INLINE i386_operand_type
1879 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1881 switch (ARRAY_SIZE (x
.array
))
1884 x
.array
[2] ^= y
.array
[2];
1887 x
.array
[1] ^= y
.array
[1];
1890 x
.array
[0] ^= y
.array
[0];
1898 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1899 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1900 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1901 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1902 static const i386_operand_type anydisp
1903 = OPERAND_TYPE_ANYDISP
;
1904 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1905 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1906 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1907 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1908 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1909 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1910 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1911 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1912 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1913 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1914 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1915 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1926 operand_type_check (i386_operand_type t
, enum operand_type c
)
1931 return t
.bitfield
.reg
;
1934 return (t
.bitfield
.imm8
1938 || t
.bitfield
.imm32s
1939 || t
.bitfield
.imm64
);
1942 return (t
.bitfield
.disp8
1943 || t
.bitfield
.disp16
1944 || t
.bitfield
.disp32
1945 || t
.bitfield
.disp32s
1946 || t
.bitfield
.disp64
);
1949 return (t
.bitfield
.disp8
1950 || t
.bitfield
.disp16
1951 || t
.bitfield
.disp32
1952 || t
.bitfield
.disp32s
1953 || t
.bitfield
.disp64
1954 || t
.bitfield
.baseindex
);
1963 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1964 between operand GIVEN and opeand WANTED for instruction template T. */
1967 match_operand_size (const insn_template
*t
, unsigned int wanted
,
1970 return !((i
.types
[given
].bitfield
.byte
1971 && !t
->operand_types
[wanted
].bitfield
.byte
)
1972 || (i
.types
[given
].bitfield
.word
1973 && !t
->operand_types
[wanted
].bitfield
.word
)
1974 || (i
.types
[given
].bitfield
.dword
1975 && !t
->operand_types
[wanted
].bitfield
.dword
)
1976 || (i
.types
[given
].bitfield
.qword
1977 && !t
->operand_types
[wanted
].bitfield
.qword
)
1978 || (i
.types
[given
].bitfield
.tbyte
1979 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
1982 /* Return 1 if there is no conflict in SIMD register between operand
1983 GIVEN and opeand WANTED for instruction template T. */
1986 match_simd_size (const insn_template
*t
, unsigned int wanted
,
1989 return !((i
.types
[given
].bitfield
.xmmword
1990 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
1991 || (i
.types
[given
].bitfield
.ymmword
1992 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
1993 || (i
.types
[given
].bitfield
.zmmword
1994 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
1997 /* Return 1 if there is no conflict in any size between operand GIVEN
1998 and opeand WANTED for instruction template T. */
2001 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2004 return (match_operand_size (t
, wanted
, given
)
2005 && !((i
.types
[given
].bitfield
.unspecified
2007 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2008 || (i
.types
[given
].bitfield
.fword
2009 && !t
->operand_types
[wanted
].bitfield
.fword
)
2010 /* For scalar opcode templates to allow register and memory
2011 operands at the same time, some special casing is needed
2012 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2013 down-conversion vpmov*. */
2014 || ((t
->operand_types
[wanted
].bitfield
.regsimd
2015 && !t
->opcode_modifier
.broadcast
2016 && (t
->operand_types
[wanted
].bitfield
.byte
2017 || t
->operand_types
[wanted
].bitfield
.word
2018 || t
->operand_types
[wanted
].bitfield
.dword
2019 || t
->operand_types
[wanted
].bitfield
.qword
))
2020 ? (i
.types
[given
].bitfield
.xmmword
2021 || i
.types
[given
].bitfield
.ymmword
2022 || i
.types
[given
].bitfield
.zmmword
)
2023 : !match_simd_size(t
, wanted
, given
))));
2026 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2027 operands for instruction template T, and it has MATCH_REVERSE set if there
2028 is no size conflict on any operands for the template with operands reversed
2029 (and the template allows for reversing in the first place). */
2031 #define MATCH_STRAIGHT 1
2032 #define MATCH_REVERSE 2
2034 static INLINE
unsigned int
2035 operand_size_match (const insn_template
*t
)
2037 unsigned int j
, match
= MATCH_STRAIGHT
;
2039 /* Don't check jump instructions. */
2040 if (t
->opcode_modifier
.jump
2041 || t
->opcode_modifier
.jumpbyte
2042 || t
->opcode_modifier
.jumpdword
2043 || t
->opcode_modifier
.jumpintersegment
)
2046 /* Check memory and accumulator operand size. */
2047 for (j
= 0; j
< i
.operands
; j
++)
2049 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
2050 && t
->operand_types
[j
].bitfield
.anysize
)
2053 if (t
->operand_types
[j
].bitfield
.reg
2054 && !match_operand_size (t
, j
, j
))
2060 if (t
->operand_types
[j
].bitfield
.regsimd
2061 && !match_simd_size (t
, j
, j
))
2067 if (t
->operand_types
[j
].bitfield
.acc
2068 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2074 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2081 if (!t
->opcode_modifier
.d
)
2085 i
.error
= operand_size_mismatch
;
2089 /* Check reverse. */
2090 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2092 for (j
= 0; j
< i
.operands
; j
++)
2094 unsigned int given
= i
.operands
- j
- 1;
2096 if (t
->operand_types
[j
].bitfield
.reg
2097 && !match_operand_size (t
, j
, given
))
2100 if (t
->operand_types
[j
].bitfield
.regsimd
2101 && !match_simd_size (t
, j
, given
))
2104 if (t
->operand_types
[j
].bitfield
.acc
2105 && (!match_operand_size (t
, j
, given
)
2106 || !match_simd_size (t
, j
, given
)))
2109 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2113 return match
| MATCH_REVERSE
;
2117 operand_type_match (i386_operand_type overlap
,
2118 i386_operand_type given
)
2120 i386_operand_type temp
= overlap
;
2122 temp
.bitfield
.jumpabsolute
= 0;
2123 temp
.bitfield
.unspecified
= 0;
2124 temp
.bitfield
.byte
= 0;
2125 temp
.bitfield
.word
= 0;
2126 temp
.bitfield
.dword
= 0;
2127 temp
.bitfield
.fword
= 0;
2128 temp
.bitfield
.qword
= 0;
2129 temp
.bitfield
.tbyte
= 0;
2130 temp
.bitfield
.xmmword
= 0;
2131 temp
.bitfield
.ymmword
= 0;
2132 temp
.bitfield
.zmmword
= 0;
2133 if (operand_type_all_zero (&temp
))
2136 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2137 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2141 i
.error
= operand_type_mismatch
;
2145 /* If given types g0 and g1 are registers they must be of the same type
2146 unless the expected operand type register overlap is null.
2147 Memory operand size of certain SIMD instructions is also being checked
2151 operand_type_register_match (i386_operand_type g0
,
2152 i386_operand_type t0
,
2153 i386_operand_type g1
,
2154 i386_operand_type t1
)
2156 if (!g0
.bitfield
.reg
2157 && !g0
.bitfield
.regsimd
2158 && (!operand_type_check (g0
, anymem
)
2159 || g0
.bitfield
.unspecified
2160 || !t0
.bitfield
.regsimd
))
2163 if (!g1
.bitfield
.reg
2164 && !g1
.bitfield
.regsimd
2165 && (!operand_type_check (g1
, anymem
)
2166 || g1
.bitfield
.unspecified
2167 || !t1
.bitfield
.regsimd
))
2170 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2171 && g0
.bitfield
.word
== g1
.bitfield
.word
2172 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2173 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2174 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2175 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2176 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2179 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2180 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2181 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2182 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2183 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2184 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2185 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2188 i
.error
= register_type_mismatch
;
2193 static INLINE
unsigned int
2194 register_number (const reg_entry
*r
)
2196 unsigned int nr
= r
->reg_num
;
2198 if (r
->reg_flags
& RegRex
)
2201 if (r
->reg_flags
& RegVRex
)
2207 static INLINE
unsigned int
2208 mode_from_disp_size (i386_operand_type t
)
2210 if (t
.bitfield
.disp8
)
2212 else if (t
.bitfield
.disp16
2213 || t
.bitfield
.disp32
2214 || t
.bitfield
.disp32s
)
2221 fits_in_signed_byte (addressT num
)
2223 return num
+ 0x80 <= 0xff;
2227 fits_in_unsigned_byte (addressT num
)
2233 fits_in_unsigned_word (addressT num
)
2235 return num
<= 0xffff;
2239 fits_in_signed_word (addressT num
)
2241 return num
+ 0x8000 <= 0xffff;
2245 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2250 return num
+ 0x80000000 <= 0xffffffff;
2252 } /* fits_in_signed_long() */
2255 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2260 return num
<= 0xffffffff;
2262 } /* fits_in_unsigned_long() */
2265 fits_in_disp8 (offsetT num
)
2267 int shift
= i
.memshift
;
2273 mask
= (1 << shift
) - 1;
2275 /* Return 0 if NUM isn't properly aligned. */
2279 /* Check if NUM will fit in 8bit after shift. */
2280 return fits_in_signed_byte (num
>> shift
);
2284 fits_in_imm4 (offsetT num
)
2286 return (num
& 0xf) == num
;
2289 static i386_operand_type
2290 smallest_imm_type (offsetT num
)
2292 i386_operand_type t
;
2294 operand_type_set (&t
, 0);
2295 t
.bitfield
.imm64
= 1;
2297 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2299 /* This code is disabled on the 486 because all the Imm1 forms
2300 in the opcode table are slower on the i486. They're the
2301 versions with the implicitly specified single-position
2302 displacement, which has another syntax if you really want to
2304 t
.bitfield
.imm1
= 1;
2305 t
.bitfield
.imm8
= 1;
2306 t
.bitfield
.imm8s
= 1;
2307 t
.bitfield
.imm16
= 1;
2308 t
.bitfield
.imm32
= 1;
2309 t
.bitfield
.imm32s
= 1;
2311 else if (fits_in_signed_byte (num
))
2313 t
.bitfield
.imm8
= 1;
2314 t
.bitfield
.imm8s
= 1;
2315 t
.bitfield
.imm16
= 1;
2316 t
.bitfield
.imm32
= 1;
2317 t
.bitfield
.imm32s
= 1;
2319 else if (fits_in_unsigned_byte (num
))
2321 t
.bitfield
.imm8
= 1;
2322 t
.bitfield
.imm16
= 1;
2323 t
.bitfield
.imm32
= 1;
2324 t
.bitfield
.imm32s
= 1;
2326 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2328 t
.bitfield
.imm16
= 1;
2329 t
.bitfield
.imm32
= 1;
2330 t
.bitfield
.imm32s
= 1;
2332 else if (fits_in_signed_long (num
))
2334 t
.bitfield
.imm32
= 1;
2335 t
.bitfield
.imm32s
= 1;
2337 else if (fits_in_unsigned_long (num
))
2338 t
.bitfield
.imm32
= 1;
2344 offset_in_range (offsetT val
, int size
)
2350 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2351 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2352 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2354 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2360 /* If BFD64, sign extend val for 32bit address mode. */
2361 if (flag_code
!= CODE_64BIT
2362 || i
.prefix
[ADDR_PREFIX
])
2363 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2364 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2367 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2369 char buf1
[40], buf2
[40];
2371 sprint_value (buf1
, val
);
2372 sprint_value (buf2
, val
& mask
);
2373 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2388 a. PREFIX_EXIST if attempting to add a prefix where one from the
2389 same class already exists.
2390 b. PREFIX_LOCK if lock prefix is added.
2391 c. PREFIX_REP if rep/repne prefix is added.
2392 d. PREFIX_DS if ds prefix is added.
2393 e. PREFIX_OTHER if other prefix is added.
2396 static enum PREFIX_GROUP
2397 add_prefix (unsigned int prefix
)
2399 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2402 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2403 && flag_code
== CODE_64BIT
)
2405 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2406 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2407 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2408 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2419 case DS_PREFIX_OPCODE
:
2422 case CS_PREFIX_OPCODE
:
2423 case ES_PREFIX_OPCODE
:
2424 case FS_PREFIX_OPCODE
:
2425 case GS_PREFIX_OPCODE
:
2426 case SS_PREFIX_OPCODE
:
2430 case REPNE_PREFIX_OPCODE
:
2431 case REPE_PREFIX_OPCODE
:
2436 case LOCK_PREFIX_OPCODE
:
2445 case ADDR_PREFIX_OPCODE
:
2449 case DATA_PREFIX_OPCODE
:
2453 if (i
.prefix
[q
] != 0)
2461 i
.prefix
[q
] |= prefix
;
2464 as_bad (_("same type of prefix used twice"));
2470 update_code_flag (int value
, int check
)
2472 PRINTF_LIKE ((*as_error
));
2474 flag_code
= (enum flag_code
) value
;
2475 if (flag_code
== CODE_64BIT
)
2477 cpu_arch_flags
.bitfield
.cpu64
= 1;
2478 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2482 cpu_arch_flags
.bitfield
.cpu64
= 0;
2483 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2485 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2488 as_error
= as_fatal
;
2491 (*as_error
) (_("64bit mode not supported on `%s'."),
2492 cpu_arch_name
? cpu_arch_name
: default_arch
);
2494 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2497 as_error
= as_fatal
;
2500 (*as_error
) (_("32bit mode not supported on `%s'."),
2501 cpu_arch_name
? cpu_arch_name
: default_arch
);
2503 stackop_size
= '\0';
2507 set_code_flag (int value
)
2509 update_code_flag (value
, 0);
2513 set_16bit_gcc_code_flag (int new_code_flag
)
2515 flag_code
= (enum flag_code
) new_code_flag
;
2516 if (flag_code
!= CODE_16BIT
)
2518 cpu_arch_flags
.bitfield
.cpu64
= 0;
2519 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2520 stackop_size
= LONG_MNEM_SUFFIX
;
2524 set_intel_syntax (int syntax_flag
)
2526 /* Find out if register prefixing is specified. */
2527 int ask_naked_reg
= 0;
2530 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2533 int e
= get_symbol_name (&string
);
2535 if (strcmp (string
, "prefix") == 0)
2537 else if (strcmp (string
, "noprefix") == 0)
2540 as_bad (_("bad argument to syntax directive."));
2541 (void) restore_line_pointer (e
);
2543 demand_empty_rest_of_line ();
2545 intel_syntax
= syntax_flag
;
2547 if (ask_naked_reg
== 0)
2548 allow_naked_reg
= (intel_syntax
2549 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2551 allow_naked_reg
= (ask_naked_reg
< 0);
2553 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2555 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2556 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2557 register_prefix
= allow_naked_reg
? "" : "%";
2561 set_intel_mnemonic (int mnemonic_flag
)
2563 intel_mnemonic
= mnemonic_flag
;
2567 set_allow_index_reg (int flag
)
2569 allow_index_reg
= flag
;
2573 set_check (int what
)
2575 enum check_kind
*kind
;
2580 kind
= &operand_check
;
2591 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2594 int e
= get_symbol_name (&string
);
2596 if (strcmp (string
, "none") == 0)
2598 else if (strcmp (string
, "warning") == 0)
2599 *kind
= check_warning
;
2600 else if (strcmp (string
, "error") == 0)
2601 *kind
= check_error
;
2603 as_bad (_("bad argument to %s_check directive."), str
);
2604 (void) restore_line_pointer (e
);
2607 as_bad (_("missing argument for %s_check directive"), str
);
2609 demand_empty_rest_of_line ();
2613 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2614 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2616 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2617 static const char *arch
;
2619 /* Intel LIOM is only supported on ELF. */
2625 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2626 use default_arch. */
2627 arch
= cpu_arch_name
;
2629 arch
= default_arch
;
2632 /* If we are targeting Intel MCU, we must enable it. */
2633 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2634 || new_flag
.bitfield
.cpuiamcu
)
2637 /* If we are targeting Intel L1OM, we must enable it. */
2638 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2639 || new_flag
.bitfield
.cpul1om
)
2642 /* If we are targeting Intel K1OM, we must enable it. */
2643 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2644 || new_flag
.bitfield
.cpuk1om
)
2647 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2652 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2656 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2659 int e
= get_symbol_name (&string
);
2661 i386_cpu_flags flags
;
2663 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2665 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2667 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2671 cpu_arch_name
= cpu_arch
[j
].name
;
2672 cpu_sub_arch_name
= NULL
;
2673 cpu_arch_flags
= cpu_arch
[j
].flags
;
2674 if (flag_code
== CODE_64BIT
)
2676 cpu_arch_flags
.bitfield
.cpu64
= 1;
2677 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2681 cpu_arch_flags
.bitfield
.cpu64
= 0;
2682 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2684 cpu_arch_isa
= cpu_arch
[j
].type
;
2685 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2686 if (!cpu_arch_tune_set
)
2688 cpu_arch_tune
= cpu_arch_isa
;
2689 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2694 flags
= cpu_flags_or (cpu_arch_flags
,
2697 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2699 if (cpu_sub_arch_name
)
2701 char *name
= cpu_sub_arch_name
;
2702 cpu_sub_arch_name
= concat (name
,
2704 (const char *) NULL
);
2708 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2709 cpu_arch_flags
= flags
;
2710 cpu_arch_isa_flags
= flags
;
2714 = cpu_flags_or (cpu_arch_isa_flags
,
2716 (void) restore_line_pointer (e
);
2717 demand_empty_rest_of_line ();
2722 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2724 /* Disable an ISA extension. */
2725 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2726 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2728 flags
= cpu_flags_and_not (cpu_arch_flags
,
2729 cpu_noarch
[j
].flags
);
2730 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2732 if (cpu_sub_arch_name
)
2734 char *name
= cpu_sub_arch_name
;
2735 cpu_sub_arch_name
= concat (name
, string
,
2736 (const char *) NULL
);
2740 cpu_sub_arch_name
= xstrdup (string
);
2741 cpu_arch_flags
= flags
;
2742 cpu_arch_isa_flags
= flags
;
2744 (void) restore_line_pointer (e
);
2745 demand_empty_rest_of_line ();
2749 j
= ARRAY_SIZE (cpu_arch
);
2752 if (j
>= ARRAY_SIZE (cpu_arch
))
2753 as_bad (_("no such architecture: `%s'"), string
);
2755 *input_line_pointer
= e
;
2758 as_bad (_("missing cpu architecture"));
2760 no_cond_jump_promotion
= 0;
2761 if (*input_line_pointer
== ','
2762 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2767 ++input_line_pointer
;
2768 e
= get_symbol_name (&string
);
2770 if (strcmp (string
, "nojumps") == 0)
2771 no_cond_jump_promotion
= 1;
2772 else if (strcmp (string
, "jumps") == 0)
2775 as_bad (_("no such architecture modifier: `%s'"), string
);
2777 (void) restore_line_pointer (e
);
2780 demand_empty_rest_of_line ();
2783 enum bfd_architecture
2786 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2788 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2789 || flag_code
!= CODE_64BIT
)
2790 as_fatal (_("Intel L1OM is 64bit ELF only"));
2791 return bfd_arch_l1om
;
2793 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2795 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2796 || flag_code
!= CODE_64BIT
)
2797 as_fatal (_("Intel K1OM is 64bit ELF only"));
2798 return bfd_arch_k1om
;
2800 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2802 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2803 || flag_code
== CODE_64BIT
)
2804 as_fatal (_("Intel MCU is 32bit ELF only"));
2805 return bfd_arch_iamcu
;
2808 return bfd_arch_i386
;
2814 if (!strncmp (default_arch
, "x86_64", 6))
2816 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2818 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2819 || default_arch
[6] != '\0')
2820 as_fatal (_("Intel L1OM is 64bit ELF only"));
2821 return bfd_mach_l1om
;
2823 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2825 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2826 || default_arch
[6] != '\0')
2827 as_fatal (_("Intel K1OM is 64bit ELF only"));
2828 return bfd_mach_k1om
;
2830 else if (default_arch
[6] == '\0')
2831 return bfd_mach_x86_64
;
2833 return bfd_mach_x64_32
;
2835 else if (!strcmp (default_arch
, "i386")
2836 || !strcmp (default_arch
, "iamcu"))
2838 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2840 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2841 as_fatal (_("Intel MCU is 32bit ELF only"));
2842 return bfd_mach_i386_iamcu
;
2845 return bfd_mach_i386_i386
;
2848 as_fatal (_("unknown architecture"));
2854 const char *hash_err
;
2856 /* Support pseudo prefixes like {disp32}. */
2857 lex_type
['{'] = LEX_BEGIN_NAME
;
2859 /* Initialize op_hash hash table. */
2860 op_hash
= hash_new ();
2863 const insn_template
*optab
;
2864 templates
*core_optab
;
2866 /* Setup for loop. */
2868 core_optab
= XNEW (templates
);
2869 core_optab
->start
= optab
;
2874 if (optab
->name
== NULL
2875 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2877 /* different name --> ship out current template list;
2878 add to hash table; & begin anew. */
2879 core_optab
->end
= optab
;
2880 hash_err
= hash_insert (op_hash
,
2882 (void *) core_optab
);
2885 as_fatal (_("can't hash %s: %s"),
2889 if (optab
->name
== NULL
)
2891 core_optab
= XNEW (templates
);
2892 core_optab
->start
= optab
;
2897 /* Initialize reg_hash hash table. */
2898 reg_hash
= hash_new ();
2900 const reg_entry
*regtab
;
2901 unsigned int regtab_size
= i386_regtab_size
;
2903 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2905 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2907 as_fatal (_("can't hash %s: %s"),
2913 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2918 for (c
= 0; c
< 256; c
++)
2923 mnemonic_chars
[c
] = c
;
2924 register_chars
[c
] = c
;
2925 operand_chars
[c
] = c
;
2927 else if (ISLOWER (c
))
2929 mnemonic_chars
[c
] = c
;
2930 register_chars
[c
] = c
;
2931 operand_chars
[c
] = c
;
2933 else if (ISUPPER (c
))
2935 mnemonic_chars
[c
] = TOLOWER (c
);
2936 register_chars
[c
] = mnemonic_chars
[c
];
2937 operand_chars
[c
] = c
;
2939 else if (c
== '{' || c
== '}')
2941 mnemonic_chars
[c
] = c
;
2942 operand_chars
[c
] = c
;
2945 if (ISALPHA (c
) || ISDIGIT (c
))
2946 identifier_chars
[c
] = c
;
2949 identifier_chars
[c
] = c
;
2950 operand_chars
[c
] = c
;
2955 identifier_chars
['@'] = '@';
2958 identifier_chars
['?'] = '?';
2959 operand_chars
['?'] = '?';
2961 digit_chars
['-'] = '-';
2962 mnemonic_chars
['_'] = '_';
2963 mnemonic_chars
['-'] = '-';
2964 mnemonic_chars
['.'] = '.';
2965 identifier_chars
['_'] = '_';
2966 identifier_chars
['.'] = '.';
2968 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2969 operand_chars
[(unsigned char) *p
] = *p
;
2972 if (flag_code
== CODE_64BIT
)
2974 #if defined (OBJ_COFF) && defined (TE_PE)
2975 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2978 x86_dwarf2_return_column
= 16;
2980 x86_cie_data_alignment
= -8;
2984 x86_dwarf2_return_column
= 8;
2985 x86_cie_data_alignment
= -4;
2990 i386_print_statistics (FILE *file
)
2992 hash_print_statistics (file
, "i386 opcode", op_hash
);
2993 hash_print_statistics (file
, "i386 register", reg_hash
);
2998 /* Debugging routines for md_assemble. */
2999 static void pte (insn_template
*);
3000 static void pt (i386_operand_type
);
3001 static void pe (expressionS
*);
3002 static void ps (symbolS
*);
3005 pi (const char *line
, i386_insn
*x
)
3009 fprintf (stdout
, "%s: template ", line
);
3011 fprintf (stdout
, " address: base %s index %s scale %x\n",
3012 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3013 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3014 x
->log2_scale_factor
);
3015 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3016 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3017 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3018 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3019 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3020 (x
->rex
& REX_W
) != 0,
3021 (x
->rex
& REX_R
) != 0,
3022 (x
->rex
& REX_X
) != 0,
3023 (x
->rex
& REX_B
) != 0);
3024 for (j
= 0; j
< x
->operands
; j
++)
3026 fprintf (stdout
, " #%d: ", j
+ 1);
3028 fprintf (stdout
, "\n");
3029 if (x
->types
[j
].bitfield
.reg
3030 || x
->types
[j
].bitfield
.regmmx
3031 || x
->types
[j
].bitfield
.regsimd
3032 || x
->types
[j
].bitfield
.sreg2
3033 || x
->types
[j
].bitfield
.sreg3
3034 || x
->types
[j
].bitfield
.control
3035 || x
->types
[j
].bitfield
.debug
3036 || x
->types
[j
].bitfield
.test
)
3037 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3038 if (operand_type_check (x
->types
[j
], imm
))
3040 if (operand_type_check (x
->types
[j
], disp
))
3041 pe (x
->op
[j
].disps
);
3046 pte (insn_template
*t
)
3049 fprintf (stdout
, " %d operands ", t
->operands
);
3050 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3051 if (t
->extension_opcode
!= None
)
3052 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3053 if (t
->opcode_modifier
.d
)
3054 fprintf (stdout
, "D");
3055 if (t
->opcode_modifier
.w
)
3056 fprintf (stdout
, "W");
3057 fprintf (stdout
, "\n");
3058 for (j
= 0; j
< t
->operands
; j
++)
3060 fprintf (stdout
, " #%d type ", j
+ 1);
3061 pt (t
->operand_types
[j
]);
3062 fprintf (stdout
, "\n");
3069 fprintf (stdout
, " operation %d\n", e
->X_op
);
3070 fprintf (stdout
, " add_number %ld (%lx)\n",
3071 (long) e
->X_add_number
, (long) e
->X_add_number
);
3072 if (e
->X_add_symbol
)
3074 fprintf (stdout
, " add_symbol ");
3075 ps (e
->X_add_symbol
);
3076 fprintf (stdout
, "\n");
3080 fprintf (stdout
, " op_symbol ");
3081 ps (e
->X_op_symbol
);
3082 fprintf (stdout
, "\n");
3089 fprintf (stdout
, "%s type %s%s",
3091 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3092 segment_name (S_GET_SEGMENT (s
)));
3095 static struct type_name
3097 i386_operand_type mask
;
3100 const type_names
[] =
3102 { OPERAND_TYPE_REG8
, "r8" },
3103 { OPERAND_TYPE_REG16
, "r16" },
3104 { OPERAND_TYPE_REG32
, "r32" },
3105 { OPERAND_TYPE_REG64
, "r64" },
3106 { OPERAND_TYPE_ACC8
, "acc8" },
3107 { OPERAND_TYPE_ACC16
, "acc16" },
3108 { OPERAND_TYPE_ACC32
, "acc32" },
3109 { OPERAND_TYPE_ACC64
, "acc64" },
3110 { OPERAND_TYPE_IMM8
, "i8" },
3111 { OPERAND_TYPE_IMM8
, "i8s" },
3112 { OPERAND_TYPE_IMM16
, "i16" },
3113 { OPERAND_TYPE_IMM32
, "i32" },
3114 { OPERAND_TYPE_IMM32S
, "i32s" },
3115 { OPERAND_TYPE_IMM64
, "i64" },
3116 { OPERAND_TYPE_IMM1
, "i1" },
3117 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3118 { OPERAND_TYPE_DISP8
, "d8" },
3119 { OPERAND_TYPE_DISP16
, "d16" },
3120 { OPERAND_TYPE_DISP32
, "d32" },
3121 { OPERAND_TYPE_DISP32S
, "d32s" },
3122 { OPERAND_TYPE_DISP64
, "d64" },
3123 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3124 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3125 { OPERAND_TYPE_CONTROL
, "control reg" },
3126 { OPERAND_TYPE_TEST
, "test reg" },
3127 { OPERAND_TYPE_DEBUG
, "debug reg" },
3128 { OPERAND_TYPE_FLOATREG
, "FReg" },
3129 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3130 { OPERAND_TYPE_SREG2
, "SReg2" },
3131 { OPERAND_TYPE_SREG3
, "SReg3" },
3132 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3133 { OPERAND_TYPE_REGMMX
, "rMMX" },
3134 { OPERAND_TYPE_REGXMM
, "rXMM" },
3135 { OPERAND_TYPE_REGYMM
, "rYMM" },
3136 { OPERAND_TYPE_REGZMM
, "rZMM" },
3137 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3138 { OPERAND_TYPE_ESSEG
, "es" },
3142 pt (i386_operand_type t
)
3145 i386_operand_type a
;
3147 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3149 a
= operand_type_and (t
, type_names
[j
].mask
);
3150 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3151 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3156 #endif /* DEBUG386 */
3158 static bfd_reloc_code_real_type
3159 reloc (unsigned int size
,
3162 bfd_reloc_code_real_type other
)
3164 if (other
!= NO_RELOC
)
3166 reloc_howto_type
*rel
;
3171 case BFD_RELOC_X86_64_GOT32
:
3172 return BFD_RELOC_X86_64_GOT64
;
3174 case BFD_RELOC_X86_64_GOTPLT64
:
3175 return BFD_RELOC_X86_64_GOTPLT64
;
3177 case BFD_RELOC_X86_64_PLTOFF64
:
3178 return BFD_RELOC_X86_64_PLTOFF64
;
3180 case BFD_RELOC_X86_64_GOTPC32
:
3181 other
= BFD_RELOC_X86_64_GOTPC64
;
3183 case BFD_RELOC_X86_64_GOTPCREL
:
3184 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3186 case BFD_RELOC_X86_64_TPOFF32
:
3187 other
= BFD_RELOC_X86_64_TPOFF64
;
3189 case BFD_RELOC_X86_64_DTPOFF32
:
3190 other
= BFD_RELOC_X86_64_DTPOFF64
;
3196 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3197 if (other
== BFD_RELOC_SIZE32
)
3200 other
= BFD_RELOC_SIZE64
;
3203 as_bad (_("there are no pc-relative size relocations"));
3209 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3210 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3213 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3215 as_bad (_("unknown relocation (%u)"), other
);
3216 else if (size
!= bfd_get_reloc_size (rel
))
3217 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3218 bfd_get_reloc_size (rel
),
3220 else if (pcrel
&& !rel
->pc_relative
)
3221 as_bad (_("non-pc-relative relocation for pc-relative field"));
3222 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3224 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3226 as_bad (_("relocated field and relocation type differ in signedness"));
3235 as_bad (_("there are no unsigned pc-relative relocations"));
3238 case 1: return BFD_RELOC_8_PCREL
;
3239 case 2: return BFD_RELOC_16_PCREL
;
3240 case 4: return BFD_RELOC_32_PCREL
;
3241 case 8: return BFD_RELOC_64_PCREL
;
3243 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3250 case 4: return BFD_RELOC_X86_64_32S
;
3255 case 1: return BFD_RELOC_8
;
3256 case 2: return BFD_RELOC_16
;
3257 case 4: return BFD_RELOC_32
;
3258 case 8: return BFD_RELOC_64
;
3260 as_bad (_("cannot do %s %u byte relocation"),
3261 sign
> 0 ? "signed" : "unsigned", size
);
3267 /* Here we decide which fixups can be adjusted to make them relative to
3268 the beginning of the section instead of the symbol. Basically we need
3269 to make sure that the dynamic relocations are done correctly, so in
3270 some cases we force the original symbol to be used. */
3273 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3275 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3279 /* Don't adjust pc-relative references to merge sections in 64-bit
3281 if (use_rela_relocations
3282 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3286 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3287 and changed later by validate_fix. */
3288 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3289 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3292 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3293 for size relocations. */
3294 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3295 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3296 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3297 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3298 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3299 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3300 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3301 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3302 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3303 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3304 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3305 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3306 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3307 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3308 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3309 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3310 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3311 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3312 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3313 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3314 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3315 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3316 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3317 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3318 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3319 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3320 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3321 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3322 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3323 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3324 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3325 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3326 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3333 intel_float_operand (const char *mnemonic
)
3335 /* Note that the value returned is meaningful only for opcodes with (memory)
3336 operands, hence the code here is free to improperly handle opcodes that
3337 have no operands (for better performance and smaller code). */
3339 if (mnemonic
[0] != 'f')
3340 return 0; /* non-math */
3342 switch (mnemonic
[1])
3344 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3345 the fs segment override prefix not currently handled because no
3346 call path can make opcodes without operands get here */
3348 return 2 /* integer op */;
3350 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3351 return 3; /* fldcw/fldenv */
3354 if (mnemonic
[2] != 'o' /* fnop */)
3355 return 3; /* non-waiting control op */
3358 if (mnemonic
[2] == 's')
3359 return 3; /* frstor/frstpm */
3362 if (mnemonic
[2] == 'a')
3363 return 3; /* fsave */
3364 if (mnemonic
[2] == 't')
3366 switch (mnemonic
[3])
3368 case 'c': /* fstcw */
3369 case 'd': /* fstdw */
3370 case 'e': /* fstenv */
3371 case 's': /* fsts[gw] */
3377 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3378 return 0; /* fxsave/fxrstor are not really math ops */
3385 /* Build the VEX prefix. */
3388 build_vex_prefix (const insn_template
*t
)
3390 unsigned int register_specifier
;
3391 unsigned int implied_prefix
;
3392 unsigned int vector_length
;
3395 /* Check register specifier. */
3396 if (i
.vex
.register_specifier
)
3398 register_specifier
=
3399 ~register_number (i
.vex
.register_specifier
) & 0xf;
3400 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3403 register_specifier
= 0xf;
3405 /* Use 2-byte VEX prefix by swapping destination and source operand
3406 if there are more than 1 register operand. */
3407 if (i
.reg_operands
> 1
3408 && i
.vec_encoding
!= vex_encoding_vex3
3409 && i
.dir_encoding
== dir_encoding_default
3410 && i
.operands
== i
.reg_operands
3411 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3412 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3413 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3416 unsigned int xchg
= i
.operands
- 1;
3417 union i386_op temp_op
;
3418 i386_operand_type temp_type
;
3420 temp_type
= i
.types
[xchg
];
3421 i
.types
[xchg
] = i
.types
[0];
3422 i
.types
[0] = temp_type
;
3423 temp_op
= i
.op
[xchg
];
3424 i
.op
[xchg
] = i
.op
[0];
3427 gas_assert (i
.rm
.mode
== 3);
3431 i
.rm
.regmem
= i
.rm
.reg
;
3434 if (i
.tm
.opcode_modifier
.d
)
3435 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3436 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3437 else /* Use the next insn. */
3441 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3442 vector_length
= avxscalar
;
3443 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3449 /* Determine vector length from the last multi-length vector
3452 for (op
= t
->operands
; op
--;)
3453 if (t
->operand_types
[op
].bitfield
.xmmword
3454 && t
->operand_types
[op
].bitfield
.ymmword
3455 && i
.types
[op
].bitfield
.ymmword
)
3462 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3467 case DATA_PREFIX_OPCODE
:
3470 case REPE_PREFIX_OPCODE
:
3473 case REPNE_PREFIX_OPCODE
:
3480 /* Check the REX.W bit and VEXW. */
3481 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3482 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3483 else if (i
.tm
.opcode_modifier
.vexw
)
3484 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3486 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3488 /* Use 2-byte VEX prefix if possible. */
3490 && i
.vec_encoding
!= vex_encoding_vex3
3491 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3492 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3494 /* 2-byte VEX prefix. */
3498 i
.vex
.bytes
[0] = 0xc5;
3500 /* Check the REX.R bit. */
3501 r
= (i
.rex
& REX_R
) ? 0 : 1;
3502 i
.vex
.bytes
[1] = (r
<< 7
3503 | register_specifier
<< 3
3504 | vector_length
<< 2
3509 /* 3-byte VEX prefix. */
3514 switch (i
.tm
.opcode_modifier
.vexopcode
)
3518 i
.vex
.bytes
[0] = 0xc4;
3522 i
.vex
.bytes
[0] = 0xc4;
3526 i
.vex
.bytes
[0] = 0xc4;
3530 i
.vex
.bytes
[0] = 0x8f;
3534 i
.vex
.bytes
[0] = 0x8f;
3538 i
.vex
.bytes
[0] = 0x8f;
3544 /* The high 3 bits of the second VEX byte are 1's compliment
3545 of RXB bits from REX. */
3546 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3548 i
.vex
.bytes
[2] = (w
<< 7
3549 | register_specifier
<< 3
3550 | vector_length
<< 2
3555 static INLINE bfd_boolean
3556 is_evex_encoding (const insn_template
*t
)
3558 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3559 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3560 || t
->opcode_modifier
.sae
;
3563 static INLINE bfd_boolean
3564 is_any_vex_encoding (const insn_template
*t
)
3566 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3567 || is_evex_encoding (t
);
3570 /* Build the EVEX prefix. */
3573 build_evex_prefix (void)
3575 unsigned int register_specifier
;
3576 unsigned int implied_prefix
;
3578 rex_byte vrex_used
= 0;
3580 /* Check register specifier. */
3581 if (i
.vex
.register_specifier
)
3583 gas_assert ((i
.vrex
& REX_X
) == 0);
3585 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3586 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3587 register_specifier
+= 8;
3588 /* The upper 16 registers are encoded in the fourth byte of the
3590 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3591 i
.vex
.bytes
[3] = 0x8;
3592 register_specifier
= ~register_specifier
& 0xf;
3596 register_specifier
= 0xf;
3598 /* Encode upper 16 vector index register in the fourth byte of
3600 if (!(i
.vrex
& REX_X
))
3601 i
.vex
.bytes
[3] = 0x8;
3606 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3611 case DATA_PREFIX_OPCODE
:
3614 case REPE_PREFIX_OPCODE
:
3617 case REPNE_PREFIX_OPCODE
:
3624 /* 4 byte EVEX prefix. */
3626 i
.vex
.bytes
[0] = 0x62;
3629 switch (i
.tm
.opcode_modifier
.vexopcode
)
3645 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3647 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3649 /* The fifth bit of the second EVEX byte is 1's compliment of the
3650 REX_R bit in VREX. */
3651 if (!(i
.vrex
& REX_R
))
3652 i
.vex
.bytes
[1] |= 0x10;
3656 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3658 /* When all operands are registers, the REX_X bit in REX is not
3659 used. We reuse it to encode the upper 16 registers, which is
3660 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3661 as 1's compliment. */
3662 if ((i
.vrex
& REX_B
))
3665 i
.vex
.bytes
[1] &= ~0x40;
3669 /* EVEX instructions shouldn't need the REX prefix. */
3670 i
.vrex
&= ~vrex_used
;
3671 gas_assert (i
.vrex
== 0);
3673 /* Check the REX.W bit and VEXW. */
3674 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3675 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3676 else if (i
.tm
.opcode_modifier
.vexw
)
3677 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3679 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3681 /* Encode the U bit. */
3682 implied_prefix
|= 0x4;
3684 /* The third byte of the EVEX prefix. */
3685 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3687 /* The fourth byte of the EVEX prefix. */
3688 /* The zeroing-masking bit. */
3689 if (i
.mask
&& i
.mask
->zeroing
)
3690 i
.vex
.bytes
[3] |= 0x80;
3692 /* Don't always set the broadcast bit if there is no RC. */
3695 /* Encode the vector length. */
3696 unsigned int vec_length
;
3698 if (!i
.tm
.opcode_modifier
.evex
3699 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3703 /* Determine vector length from the last multi-length vector
3706 for (op
= i
.operands
; op
--;)
3707 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3708 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3709 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3711 if (i
.types
[op
].bitfield
.zmmword
)
3713 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3716 else if (i
.types
[op
].bitfield
.ymmword
)
3718 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3721 else if (i
.types
[op
].bitfield
.xmmword
)
3723 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3726 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3728 switch (i
.broadcast
->bytes
)
3731 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3734 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3737 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3746 if (op
>= MAX_OPERANDS
)
3750 switch (i
.tm
.opcode_modifier
.evex
)
3752 case EVEXLIG
: /* LL' is ignored */
3753 vec_length
= evexlig
<< 5;
3756 vec_length
= 0 << 5;
3759 vec_length
= 1 << 5;
3762 vec_length
= 2 << 5;
3768 i
.vex
.bytes
[3] |= vec_length
;
3769 /* Encode the broadcast bit. */
3771 i
.vex
.bytes
[3] |= 0x10;
3775 if (i
.rounding
->type
!= saeonly
)
3776 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3778 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3781 if (i
.mask
&& i
.mask
->mask
)
3782 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3786 process_immext (void)
3790 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3793 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3794 with an opcode suffix which is coded in the same place as an
3795 8-bit immediate field would be.
3796 Here we check those operands and remove them afterwards. */
3799 for (x
= 0; x
< i
.operands
; x
++)
3800 if (register_number (i
.op
[x
].regs
) != x
)
3801 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3802 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3808 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3810 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3811 suffix which is coded in the same place as an 8-bit immediate
3813 Here we check those operands and remove them afterwards. */
3816 if (i
.operands
!= 3)
3819 for (x
= 0; x
< 2; x
++)
3820 if (register_number (i
.op
[x
].regs
) != x
)
3821 goto bad_register_operand
;
3823 /* Check for third operand for mwaitx/monitorx insn. */
3824 if (register_number (i
.op
[x
].regs
)
3825 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3827 bad_register_operand
:
3828 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3829 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3836 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3837 which is coded in the same place as an 8-bit immediate field
3838 would be. Here we fake an 8-bit immediate operand from the
3839 opcode suffix stored in tm.extension_opcode.
3841 AVX instructions also use this encoding, for some of
3842 3 argument instructions. */
3844 gas_assert (i
.imm_operands
<= 1
3846 || (is_any_vex_encoding (&i
.tm
)
3847 && i
.operands
<= 4)));
3849 exp
= &im_expressions
[i
.imm_operands
++];
3850 i
.op
[i
.operands
].imms
= exp
;
3851 i
.types
[i
.operands
] = imm8
;
3853 exp
->X_op
= O_constant
;
3854 exp
->X_add_number
= i
.tm
.extension_opcode
;
3855 i
.tm
.extension_opcode
= None
;
3862 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3867 as_bad (_("invalid instruction `%s' after `%s'"),
3868 i
.tm
.name
, i
.hle_prefix
);
3871 if (i
.prefix
[LOCK_PREFIX
])
3873 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3877 case HLEPrefixRelease
:
3878 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3880 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3884 if (i
.mem_operands
== 0
3885 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3887 as_bad (_("memory destination needed for instruction `%s'"
3888 " after `xrelease'"), i
.tm
.name
);
3895 /* Try the shortest encoding by shortening operand size. */
3898 optimize_encoding (void)
3902 if (optimize_for_space
3903 && i
.reg_operands
== 1
3904 && i
.imm_operands
== 1
3905 && !i
.types
[1].bitfield
.byte
3906 && i
.op
[0].imms
->X_op
== O_constant
3907 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3908 && ((i
.tm
.base_opcode
== 0xa8
3909 && i
.tm
.extension_opcode
== None
)
3910 || (i
.tm
.base_opcode
== 0xf6
3911 && i
.tm
.extension_opcode
== 0x0)))
3914 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3916 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3917 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3919 i
.types
[1].bitfield
.byte
= 1;
3920 /* Ignore the suffix. */
3922 if (base_regnum
>= 4
3923 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3925 /* Handle SP, BP, SI and DI registers. */
3926 if (i
.types
[1].bitfield
.word
)
3928 else if (i
.types
[1].bitfield
.dword
)
3936 else if (flag_code
== CODE_64BIT
3937 && ((i
.types
[1].bitfield
.qword
3938 && i
.reg_operands
== 1
3939 && i
.imm_operands
== 1
3940 && i
.op
[0].imms
->X_op
== O_constant
3941 && ((i
.tm
.base_opcode
== 0xb0
3942 && i
.tm
.extension_opcode
== None
3943 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3944 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3945 && (((i
.tm
.base_opcode
== 0x24
3946 || i
.tm
.base_opcode
== 0xa8)
3947 && i
.tm
.extension_opcode
== None
)
3948 || (i
.tm
.base_opcode
== 0x80
3949 && i
.tm
.extension_opcode
== 0x4)
3950 || ((i
.tm
.base_opcode
== 0xf6
3951 || i
.tm
.base_opcode
== 0xc6)
3952 && i
.tm
.extension_opcode
== 0x0)))
3953 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3954 && i
.tm
.base_opcode
== 0x83
3955 && i
.tm
.extension_opcode
== 0x4)))
3956 || (i
.types
[0].bitfield
.qword
3957 && ((i
.reg_operands
== 2
3958 && i
.op
[0].regs
== i
.op
[1].regs
3959 && ((i
.tm
.base_opcode
== 0x30
3960 || i
.tm
.base_opcode
== 0x28)
3961 && i
.tm
.extension_opcode
== None
))
3962 || (i
.reg_operands
== 1
3964 && i
.tm
.base_opcode
== 0x30
3965 && i
.tm
.extension_opcode
== None
)))))
3968 andq $imm31, %r64 -> andl $imm31, %r32
3969 andq $imm7, %r64 -> andl $imm7, %r32
3970 testq $imm31, %r64 -> testl $imm31, %r32
3971 xorq %r64, %r64 -> xorl %r32, %r32
3972 subq %r64, %r64 -> subl %r32, %r32
3973 movq $imm31, %r64 -> movl $imm31, %r32
3974 movq $imm32, %r64 -> movl $imm32, %r32
3976 i
.tm
.opcode_modifier
.norex64
= 1;
3977 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
3980 movq $imm31, %r64 -> movl $imm31, %r32
3981 movq $imm32, %r64 -> movl $imm32, %r32
3983 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3984 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3985 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3986 i
.types
[0].bitfield
.imm32
= 1;
3987 i
.types
[0].bitfield
.imm32s
= 0;
3988 i
.types
[0].bitfield
.imm64
= 0;
3989 i
.types
[1].bitfield
.dword
= 1;
3990 i
.types
[1].bitfield
.qword
= 0;
3991 if (i
.tm
.base_opcode
== 0xc6)
3994 movq $imm31, %r64 -> movl $imm31, %r32
3996 i
.tm
.base_opcode
= 0xb0;
3997 i
.tm
.extension_opcode
= None
;
3998 i
.tm
.opcode_modifier
.shortform
= 1;
3999 i
.tm
.opcode_modifier
.modrm
= 0;
4003 else if (i
.reg_operands
== 3
4004 && i
.op
[0].regs
== i
.op
[1].regs
4005 && !i
.types
[2].bitfield
.xmmword
4006 && (i
.tm
.opcode_modifier
.vex
4007 || ((!i
.mask
|| i
.mask
->zeroing
)
4009 && is_evex_encoding (&i
.tm
)
4010 && (i
.vec_encoding
!= vex_encoding_evex
4011 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4012 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4013 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4014 && i
.types
[2].bitfield
.ymmword
))))
4015 && ((i
.tm
.base_opcode
== 0x55
4016 || i
.tm
.base_opcode
== 0x6655
4017 || i
.tm
.base_opcode
== 0x66df
4018 || i
.tm
.base_opcode
== 0x57
4019 || i
.tm
.base_opcode
== 0x6657
4020 || i
.tm
.base_opcode
== 0x66ef
4021 || i
.tm
.base_opcode
== 0x66f8
4022 || i
.tm
.base_opcode
== 0x66f9
4023 || i
.tm
.base_opcode
== 0x66fa
4024 || i
.tm
.base_opcode
== 0x66fb
4025 || i
.tm
.base_opcode
== 0x42
4026 || i
.tm
.base_opcode
== 0x6642
4027 || i
.tm
.base_opcode
== 0x47
4028 || i
.tm
.base_opcode
== 0x6647)
4029 && i
.tm
.extension_opcode
== None
))
4032 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4034 EVEX VOP %zmmM, %zmmM, %zmmN
4035 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4036 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4037 EVEX VOP %ymmM, %ymmM, %ymmN
4038 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4039 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4040 VEX VOP %ymmM, %ymmM, %ymmN
4041 -> VEX VOP %xmmM, %xmmM, %xmmN
4042 VOP, one of vpandn and vpxor:
4043 VEX VOP %ymmM, %ymmM, %ymmN
4044 -> VEX VOP %xmmM, %xmmM, %xmmN
4045 VOP, one of vpandnd and vpandnq:
4046 EVEX VOP %zmmM, %zmmM, %zmmN
4047 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4048 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4049 EVEX VOP %ymmM, %ymmM, %ymmN
4050 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4051 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4052 VOP, one of vpxord and vpxorq:
4053 EVEX VOP %zmmM, %zmmM, %zmmN
4054 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4055 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4056 EVEX VOP %ymmM, %ymmM, %ymmN
4057 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4058 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4059 VOP, one of kxord and kxorq:
4060 VEX VOP %kM, %kM, %kN
4061 -> VEX kxorw %kM, %kM, %kN
4062 VOP, one of kandnd and kandnq:
4063 VEX VOP %kM, %kM, %kN
4064 -> VEX kandnw %kM, %kM, %kN
4066 if (is_evex_encoding (&i
.tm
))
4068 if (i
.vec_encoding
!= vex_encoding_evex
)
4070 i
.tm
.opcode_modifier
.vex
= VEX128
;
4071 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4072 i
.tm
.opcode_modifier
.evex
= 0;
4074 else if (optimize
> 1)
4075 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4079 else if (i
.tm
.operand_types
[0].bitfield
.regmask
)
4081 i
.tm
.base_opcode
&= 0xff;
4082 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4085 i
.tm
.opcode_modifier
.vex
= VEX128
;
4087 if (i
.tm
.opcode_modifier
.vex
)
4088 for (j
= 0; j
< 3; j
++)
4090 i
.types
[j
].bitfield
.xmmword
= 1;
4091 i
.types
[j
].bitfield
.ymmword
= 0;
4094 else if (i
.vec_encoding
!= vex_encoding_evex
4095 && !i
.types
[0].bitfield
.zmmword
4096 && !i
.types
[1].bitfield
.zmmword
4099 && is_evex_encoding (&i
.tm
)
4100 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4101 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4102 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4103 || (i
.tm
.base_opcode
& ~4) == 0x66db
4104 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4105 && i
.tm
.extension_opcode
== None
)
4108 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4109 vmovdqu32 and vmovdqu64:
4110 EVEX VOP %xmmM, %xmmN
4111 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4112 EVEX VOP %ymmM, %ymmN
4113 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4115 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4117 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4119 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4121 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4122 VOP, one of vpand, vpandn, vpor, vpxor:
4123 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4124 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4125 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4126 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4127 EVEX VOP{d,q} mem, %xmmM, %xmmN
4128 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4129 EVEX VOP{d,q} mem, %ymmM, %ymmN
4130 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4132 for (j
= 0; j
< i
.operands
; j
++)
4133 if (operand_type_check (i
.types
[j
], disp
)
4134 && i
.op
[j
].disps
->X_op
== O_constant
)
4136 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4137 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4138 bytes, we choose EVEX Disp8 over VEX Disp32. */
4139 int evex_disp8
, vex_disp8
;
4140 unsigned int memshift
= i
.memshift
;
4141 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4143 evex_disp8
= fits_in_disp8 (n
);
4145 vex_disp8
= fits_in_disp8 (n
);
4146 if (evex_disp8
!= vex_disp8
)
4148 i
.memshift
= memshift
;
4152 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4155 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4156 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4157 i
.tm
.opcode_modifier
.vex
4158 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4159 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4160 i
.tm
.opcode_modifier
.evex
= 0;
4161 i
.tm
.opcode_modifier
.masking
= 0;
4162 i
.tm
.opcode_modifier
.broadcast
= 0;
4163 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4166 i
.types
[j
].bitfield
.disp8
4167 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4171 /* This is the guts of the machine-dependent assembler. LINE points to a
4172 machine dependent instruction. This function is supposed to emit
4173 the frags/bytes it assembles to. */
4176 md_assemble (char *line
)
4179 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4180 const insn_template
*t
;
4182 /* Initialize globals. */
4183 memset (&i
, '\0', sizeof (i
));
4184 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4185 i
.reloc
[j
] = NO_RELOC
;
4186 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4187 memset (im_expressions
, '\0', sizeof (im_expressions
));
4188 save_stack_p
= save_stack
;
4190 /* First parse an instruction mnemonic & call i386_operand for the operands.
4191 We assume that the scrubber has arranged it so that line[0] is the valid
4192 start of a (possibly prefixed) mnemonic. */
4194 line
= parse_insn (line
, mnemonic
);
4197 mnem_suffix
= i
.suffix
;
4199 line
= parse_operands (line
, mnemonic
);
4201 xfree (i
.memop1_string
);
4202 i
.memop1_string
= NULL
;
4206 /* Now we've parsed the mnemonic into a set of templates, and have the
4207 operands at hand. */
4209 /* All intel opcodes have reversed operands except for "bound" and
4210 "enter". We also don't reverse intersegment "jmp" and "call"
4211 instructions with 2 immediate operands so that the immediate segment
4212 precedes the offset, as it does when in AT&T mode. */
4215 && (strcmp (mnemonic
, "bound") != 0)
4216 && (strcmp (mnemonic
, "invlpga") != 0)
4217 && !(operand_type_check (i
.types
[0], imm
)
4218 && operand_type_check (i
.types
[1], imm
)))
4221 /* The order of the immediates should be reversed
4222 for 2 immediates extrq and insertq instructions */
4223 if (i
.imm_operands
== 2
4224 && (strcmp (mnemonic
, "extrq") == 0
4225 || strcmp (mnemonic
, "insertq") == 0))
4226 swap_2_operands (0, 1);
4231 /* Don't optimize displacement for movabs since it only takes 64bit
4234 && i
.disp_encoding
!= disp_encoding_32bit
4235 && (flag_code
!= CODE_64BIT
4236 || strcmp (mnemonic
, "movabs") != 0))
4239 /* Next, we find a template that matches the given insn,
4240 making sure the overlap of the given operands types is consistent
4241 with the template operand types. */
4243 if (!(t
= match_template (mnem_suffix
)))
4246 if (sse_check
!= check_none
4247 && !i
.tm
.opcode_modifier
.noavx
4248 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4249 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4250 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4251 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4252 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4253 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4254 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4255 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4256 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4257 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4259 (sse_check
== check_warning
4261 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4264 /* Zap movzx and movsx suffix. The suffix has been set from
4265 "word ptr" or "byte ptr" on the source operand in Intel syntax
4266 or extracted from mnemonic in AT&T syntax. But we'll use
4267 the destination register to choose the suffix for encoding. */
4268 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4270 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4271 there is no suffix, the default will be byte extension. */
4272 if (i
.reg_operands
!= 2
4275 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4280 if (i
.tm
.opcode_modifier
.fwait
)
4281 if (!add_prefix (FWAIT_OPCODE
))
4284 /* Check if REP prefix is OK. */
4285 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4287 as_bad (_("invalid instruction `%s' after `%s'"),
4288 i
.tm
.name
, i
.rep_prefix
);
4292 /* Check for lock without a lockable instruction. Destination operand
4293 must be memory unless it is xchg (0x86). */
4294 if (i
.prefix
[LOCK_PREFIX
]
4295 && (!i
.tm
.opcode_modifier
.islockable
4296 || i
.mem_operands
== 0
4297 || (i
.tm
.base_opcode
!= 0x86
4298 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4300 as_bad (_("expecting lockable instruction after `lock'"));
4304 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4305 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4307 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4311 /* Check if HLE prefix is OK. */
4312 if (i
.hle_prefix
&& !check_hle ())
4315 /* Check BND prefix. */
4316 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4317 as_bad (_("expecting valid branch instruction after `bnd'"));
4319 /* Check NOTRACK prefix. */
4320 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4321 as_bad (_("expecting indirect branch instruction after `notrack'"));
4323 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4325 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4326 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4327 else if (flag_code
!= CODE_16BIT
4328 ? i
.prefix
[ADDR_PREFIX
]
4329 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4330 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4333 /* Insert BND prefix. */
4334 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4336 if (!i
.prefix
[BND_PREFIX
])
4337 add_prefix (BND_PREFIX_OPCODE
);
4338 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4340 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4341 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4345 /* Check string instruction segment overrides. */
4346 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4348 if (!check_string ())
4350 i
.disp_operands
= 0;
4353 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4354 optimize_encoding ();
4356 if (!process_suffix ())
4359 /* Update operand types. */
4360 for (j
= 0; j
< i
.operands
; j
++)
4361 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4363 /* Make still unresolved immediate matches conform to size of immediate
4364 given in i.suffix. */
4365 if (!finalize_imm ())
4368 if (i
.types
[0].bitfield
.imm1
)
4369 i
.imm_operands
= 0; /* kludge for shift insns. */
4371 /* We only need to check those implicit registers for instructions
4372 with 3 operands or less. */
4373 if (i
.operands
<= 3)
4374 for (j
= 0; j
< i
.operands
; j
++)
4375 if (i
.types
[j
].bitfield
.inoutportreg
4376 || i
.types
[j
].bitfield
.shiftcount
4377 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4380 /* ImmExt should be processed after SSE2AVX. */
4381 if (!i
.tm
.opcode_modifier
.sse2avx
4382 && i
.tm
.opcode_modifier
.immext
)
4385 /* For insns with operands there are more diddles to do to the opcode. */
4388 if (!process_operands ())
4391 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4393 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4394 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4397 if (is_any_vex_encoding (&i
.tm
))
4399 if (!cpu_arch_flags
.bitfield
.cpui286
)
4401 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4406 if (i
.tm
.opcode_modifier
.vex
)
4407 build_vex_prefix (t
);
4409 build_evex_prefix ();
4412 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4413 instructions may define INT_OPCODE as well, so avoid this corner
4414 case for those instructions that use MODRM. */
4415 if (i
.tm
.base_opcode
== INT_OPCODE
4416 && !i
.tm
.opcode_modifier
.modrm
4417 && i
.op
[0].imms
->X_add_number
== 3)
4419 i
.tm
.base_opcode
= INT3_OPCODE
;
4423 if ((i
.tm
.opcode_modifier
.jump
4424 || i
.tm
.opcode_modifier
.jumpbyte
4425 || i
.tm
.opcode_modifier
.jumpdword
)
4426 && i
.op
[0].disps
->X_op
== O_constant
)
4428 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4429 the absolute address given by the constant. Since ix86 jumps and
4430 calls are pc relative, we need to generate a reloc. */
4431 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4432 i
.op
[0].disps
->X_op
= O_symbol
;
4435 if (i
.tm
.opcode_modifier
.rex64
)
4438 /* For 8 bit registers we need an empty rex prefix. Also if the
4439 instruction already has a prefix, we need to convert old
4440 registers to new ones. */
4442 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4443 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4444 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4445 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4446 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4447 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4452 i
.rex
|= REX_OPCODE
;
4453 for (x
= 0; x
< 2; x
++)
4455 /* Look for 8 bit operand that uses old registers. */
4456 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4457 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4459 /* In case it is "hi" register, give up. */
4460 if (i
.op
[x
].regs
->reg_num
> 3)
4461 as_bad (_("can't encode register '%s%s' in an "
4462 "instruction requiring REX prefix."),
4463 register_prefix
, i
.op
[x
].regs
->reg_name
);
4465 /* Otherwise it is equivalent to the extended register.
4466 Since the encoding doesn't change this is merely
4467 cosmetic cleanup for debug output. */
4469 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4474 if (i
.rex
== 0 && i
.rex_encoding
)
4476 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4477 that uses legacy register. If it is "hi" register, don't add
4478 the REX_OPCODE byte. */
4480 for (x
= 0; x
< 2; x
++)
4481 if (i
.types
[x
].bitfield
.reg
4482 && i
.types
[x
].bitfield
.byte
4483 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4484 && i
.op
[x
].regs
->reg_num
> 3)
4486 i
.rex_encoding
= FALSE
;
4495 add_prefix (REX_OPCODE
| i
.rex
);
4497 /* We are ready to output the insn. */
4502 parse_insn (char *line
, char *mnemonic
)
4505 char *token_start
= l
;
4508 const insn_template
*t
;
4514 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4519 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4521 as_bad (_("no such instruction: `%s'"), token_start
);
4526 if (!is_space_char (*l
)
4527 && *l
!= END_OF_INSN
4529 || (*l
!= PREFIX_SEPARATOR
4532 as_bad (_("invalid character %s in mnemonic"),
4533 output_invalid (*l
));
4536 if (token_start
== l
)
4538 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4539 as_bad (_("expecting prefix; got nothing"));
4541 as_bad (_("expecting mnemonic; got nothing"));
4545 /* Look up instruction (or prefix) via hash table. */
4546 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4548 if (*l
!= END_OF_INSN
4549 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4550 && current_templates
4551 && current_templates
->start
->opcode_modifier
.isprefix
)
4553 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4555 as_bad ((flag_code
!= CODE_64BIT
4556 ? _("`%s' is only supported in 64-bit mode")
4557 : _("`%s' is not supported in 64-bit mode")),
4558 current_templates
->start
->name
);
4561 /* If we are in 16-bit mode, do not allow addr16 or data16.
4562 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4563 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4564 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4565 && flag_code
!= CODE_64BIT
4566 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4567 ^ (flag_code
== CODE_16BIT
)))
4569 as_bad (_("redundant %s prefix"),
4570 current_templates
->start
->name
);
4573 if (current_templates
->start
->opcode_length
== 0)
4575 /* Handle pseudo prefixes. */
4576 switch (current_templates
->start
->base_opcode
)
4580 i
.disp_encoding
= disp_encoding_8bit
;
4584 i
.disp_encoding
= disp_encoding_32bit
;
4588 i
.dir_encoding
= dir_encoding_load
;
4592 i
.dir_encoding
= dir_encoding_store
;
4596 i
.vec_encoding
= vex_encoding_vex2
;
4600 i
.vec_encoding
= vex_encoding_vex3
;
4604 i
.vec_encoding
= vex_encoding_evex
;
4608 i
.rex_encoding
= TRUE
;
4612 i
.no_optimize
= TRUE
;
4620 /* Add prefix, checking for repeated prefixes. */
4621 switch (add_prefix (current_templates
->start
->base_opcode
))
4626 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4627 i
.notrack_prefix
= current_templates
->start
->name
;
4630 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4631 i
.hle_prefix
= current_templates
->start
->name
;
4632 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4633 i
.bnd_prefix
= current_templates
->start
->name
;
4635 i
.rep_prefix
= current_templates
->start
->name
;
4641 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4648 if (!current_templates
)
4650 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4651 Check if we should swap operand or force 32bit displacement in
4653 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4654 i
.dir_encoding
= dir_encoding_swap
;
4655 else if (mnem_p
- 3 == dot_p
4658 i
.disp_encoding
= disp_encoding_8bit
;
4659 else if (mnem_p
- 4 == dot_p
4663 i
.disp_encoding
= disp_encoding_32bit
;
4668 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4671 if (!current_templates
)
4674 if (mnem_p
> mnemonic
)
4676 /* See if we can get a match by trimming off a suffix. */
4679 case WORD_MNEM_SUFFIX
:
4680 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4681 i
.suffix
= SHORT_MNEM_SUFFIX
;
4684 case BYTE_MNEM_SUFFIX
:
4685 case QWORD_MNEM_SUFFIX
:
4686 i
.suffix
= mnem_p
[-1];
4688 current_templates
= (const templates
*) hash_find (op_hash
,
4691 case SHORT_MNEM_SUFFIX
:
4692 case LONG_MNEM_SUFFIX
:
4695 i
.suffix
= mnem_p
[-1];
4697 current_templates
= (const templates
*) hash_find (op_hash
,
4706 if (intel_float_operand (mnemonic
) == 1)
4707 i
.suffix
= SHORT_MNEM_SUFFIX
;
4709 i
.suffix
= LONG_MNEM_SUFFIX
;
4711 current_templates
= (const templates
*) hash_find (op_hash
,
4718 if (!current_templates
)
4720 as_bad (_("no such instruction: `%s'"), token_start
);
4725 if (current_templates
->start
->opcode_modifier
.jump
4726 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4728 /* Check for a branch hint. We allow ",pt" and ",pn" for
4729 predict taken and predict not taken respectively.
4730 I'm not sure that branch hints actually do anything on loop
4731 and jcxz insns (JumpByte) for current Pentium4 chips. They
4732 may work in the future and it doesn't hurt to accept them
4734 if (l
[0] == ',' && l
[1] == 'p')
4738 if (!add_prefix (DS_PREFIX_OPCODE
))
4742 else if (l
[2] == 'n')
4744 if (!add_prefix (CS_PREFIX_OPCODE
))
4750 /* Any other comma loses. */
4753 as_bad (_("invalid character %s in mnemonic"),
4754 output_invalid (*l
));
4758 /* Check if instruction is supported on specified architecture. */
4760 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4762 supported
|= cpu_flags_match (t
);
4763 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4765 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4766 as_warn (_("use .code16 to ensure correct addressing mode"));
4772 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4773 as_bad (flag_code
== CODE_64BIT
4774 ? _("`%s' is not supported in 64-bit mode")
4775 : _("`%s' is only supported in 64-bit mode"),
4776 current_templates
->start
->name
);
4778 as_bad (_("`%s' is not supported on `%s%s'"),
4779 current_templates
->start
->name
,
4780 cpu_arch_name
? cpu_arch_name
: default_arch
,
4781 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4787 parse_operands (char *l
, const char *mnemonic
)
4791 /* 1 if operand is pending after ','. */
4792 unsigned int expecting_operand
= 0;
4794 /* Non-zero if operand parens not balanced. */
4795 unsigned int paren_not_balanced
;
4797 while (*l
!= END_OF_INSN
)
4799 /* Skip optional white space before operand. */
4800 if (is_space_char (*l
))
4802 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4804 as_bad (_("invalid character %s before operand %d"),
4805 output_invalid (*l
),
4809 token_start
= l
; /* After white space. */
4810 paren_not_balanced
= 0;
4811 while (paren_not_balanced
|| *l
!= ',')
4813 if (*l
== END_OF_INSN
)
4815 if (paren_not_balanced
)
4818 as_bad (_("unbalanced parenthesis in operand %d."),
4821 as_bad (_("unbalanced brackets in operand %d."),
4826 break; /* we are done */
4828 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4830 as_bad (_("invalid character %s in operand %d"),
4831 output_invalid (*l
),
4838 ++paren_not_balanced
;
4840 --paren_not_balanced
;
4845 ++paren_not_balanced
;
4847 --paren_not_balanced
;
4851 if (l
!= token_start
)
4852 { /* Yes, we've read in another operand. */
4853 unsigned int operand_ok
;
4854 this_operand
= i
.operands
++;
4855 if (i
.operands
> MAX_OPERANDS
)
4857 as_bad (_("spurious operands; (%d operands/instruction max)"),
4861 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4862 /* Now parse operand adding info to 'i' as we go along. */
4863 END_STRING_AND_SAVE (l
);
4865 if (i
.mem_operands
> 1)
4867 as_bad (_("too many memory references for `%s'"),
4874 i386_intel_operand (token_start
,
4875 intel_float_operand (mnemonic
));
4877 operand_ok
= i386_att_operand (token_start
);
4879 RESTORE_END_STRING (l
);
4885 if (expecting_operand
)
4887 expecting_operand_after_comma
:
4888 as_bad (_("expecting operand after ','; got nothing"));
4893 as_bad (_("expecting operand before ','; got nothing"));
4898 /* Now *l must be either ',' or END_OF_INSN. */
4901 if (*++l
== END_OF_INSN
)
4903 /* Just skip it, if it's \n complain. */
4904 goto expecting_operand_after_comma
;
4906 expecting_operand
= 1;
4913 swap_2_operands (int xchg1
, int xchg2
)
4915 union i386_op temp_op
;
4916 i386_operand_type temp_type
;
4917 unsigned int temp_flags
;
4918 enum bfd_reloc_code_real temp_reloc
;
4920 temp_type
= i
.types
[xchg2
];
4921 i
.types
[xchg2
] = i
.types
[xchg1
];
4922 i
.types
[xchg1
] = temp_type
;
4924 temp_flags
= i
.flags
[xchg2
];
4925 i
.flags
[xchg2
] = i
.flags
[xchg1
];
4926 i
.flags
[xchg1
] = temp_flags
;
4928 temp_op
= i
.op
[xchg2
];
4929 i
.op
[xchg2
] = i
.op
[xchg1
];
4930 i
.op
[xchg1
] = temp_op
;
4932 temp_reloc
= i
.reloc
[xchg2
];
4933 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4934 i
.reloc
[xchg1
] = temp_reloc
;
4938 if (i
.mask
->operand
== xchg1
)
4939 i
.mask
->operand
= xchg2
;
4940 else if (i
.mask
->operand
== xchg2
)
4941 i
.mask
->operand
= xchg1
;
4945 if (i
.broadcast
->operand
== xchg1
)
4946 i
.broadcast
->operand
= xchg2
;
4947 else if (i
.broadcast
->operand
== xchg2
)
4948 i
.broadcast
->operand
= xchg1
;
4952 if (i
.rounding
->operand
== xchg1
)
4953 i
.rounding
->operand
= xchg2
;
4954 else if (i
.rounding
->operand
== xchg2
)
4955 i
.rounding
->operand
= xchg1
;
4960 swap_operands (void)
4966 swap_2_operands (1, i
.operands
- 2);
4970 swap_2_operands (0, i
.operands
- 1);
4976 if (i
.mem_operands
== 2)
4978 const seg_entry
*temp_seg
;
4979 temp_seg
= i
.seg
[0];
4980 i
.seg
[0] = i
.seg
[1];
4981 i
.seg
[1] = temp_seg
;
4985 /* Try to ensure constant immediates are represented in the smallest
4990 char guess_suffix
= 0;
4994 guess_suffix
= i
.suffix
;
4995 else if (i
.reg_operands
)
4997 /* Figure out a suffix from the last register operand specified.
4998 We can't do this properly yet, ie. excluding InOutPortReg,
4999 but the following works for instructions with immediates.
5000 In any case, we can't set i.suffix yet. */
5001 for (op
= i
.operands
; --op
>= 0;)
5002 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
5004 guess_suffix
= BYTE_MNEM_SUFFIX
;
5007 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
5009 guess_suffix
= WORD_MNEM_SUFFIX
;
5012 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
5014 guess_suffix
= LONG_MNEM_SUFFIX
;
5017 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
5019 guess_suffix
= QWORD_MNEM_SUFFIX
;
5023 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5024 guess_suffix
= WORD_MNEM_SUFFIX
;
5026 for (op
= i
.operands
; --op
>= 0;)
5027 if (operand_type_check (i
.types
[op
], imm
))
5029 switch (i
.op
[op
].imms
->X_op
)
5032 /* If a suffix is given, this operand may be shortened. */
5033 switch (guess_suffix
)
5035 case LONG_MNEM_SUFFIX
:
5036 i
.types
[op
].bitfield
.imm32
= 1;
5037 i
.types
[op
].bitfield
.imm64
= 1;
5039 case WORD_MNEM_SUFFIX
:
5040 i
.types
[op
].bitfield
.imm16
= 1;
5041 i
.types
[op
].bitfield
.imm32
= 1;
5042 i
.types
[op
].bitfield
.imm32s
= 1;
5043 i
.types
[op
].bitfield
.imm64
= 1;
5045 case BYTE_MNEM_SUFFIX
:
5046 i
.types
[op
].bitfield
.imm8
= 1;
5047 i
.types
[op
].bitfield
.imm8s
= 1;
5048 i
.types
[op
].bitfield
.imm16
= 1;
5049 i
.types
[op
].bitfield
.imm32
= 1;
5050 i
.types
[op
].bitfield
.imm32s
= 1;
5051 i
.types
[op
].bitfield
.imm64
= 1;
5055 /* If this operand is at most 16 bits, convert it
5056 to a signed 16 bit number before trying to see
5057 whether it will fit in an even smaller size.
5058 This allows a 16-bit operand such as $0xffe0 to
5059 be recognised as within Imm8S range. */
5060 if ((i
.types
[op
].bitfield
.imm16
)
5061 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5063 i
.op
[op
].imms
->X_add_number
=
5064 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5067 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5068 if ((i
.types
[op
].bitfield
.imm32
)
5069 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5072 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5073 ^ ((offsetT
) 1 << 31))
5074 - ((offsetT
) 1 << 31));
5078 = operand_type_or (i
.types
[op
],
5079 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5081 /* We must avoid matching of Imm32 templates when 64bit
5082 only immediate is available. */
5083 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5084 i
.types
[op
].bitfield
.imm32
= 0;
5091 /* Symbols and expressions. */
5093 /* Convert symbolic operand to proper sizes for matching, but don't
5094 prevent matching a set of insns that only supports sizes other
5095 than those matching the insn suffix. */
5097 i386_operand_type mask
, allowed
;
5098 const insn_template
*t
;
5100 operand_type_set (&mask
, 0);
5101 operand_type_set (&allowed
, 0);
5103 for (t
= current_templates
->start
;
5104 t
< current_templates
->end
;
5106 allowed
= operand_type_or (allowed
,
5107 t
->operand_types
[op
]);
5108 switch (guess_suffix
)
5110 case QWORD_MNEM_SUFFIX
:
5111 mask
.bitfield
.imm64
= 1;
5112 mask
.bitfield
.imm32s
= 1;
5114 case LONG_MNEM_SUFFIX
:
5115 mask
.bitfield
.imm32
= 1;
5117 case WORD_MNEM_SUFFIX
:
5118 mask
.bitfield
.imm16
= 1;
5120 case BYTE_MNEM_SUFFIX
:
5121 mask
.bitfield
.imm8
= 1;
5126 allowed
= operand_type_and (mask
, allowed
);
5127 if (!operand_type_all_zero (&allowed
))
5128 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5135 /* Try to use the smallest displacement type too. */
5137 optimize_disp (void)
5141 for (op
= i
.operands
; --op
>= 0;)
5142 if (operand_type_check (i
.types
[op
], disp
))
5144 if (i
.op
[op
].disps
->X_op
== O_constant
)
5146 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5148 if (i
.types
[op
].bitfield
.disp16
5149 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5151 /* If this operand is at most 16 bits, convert
5152 to a signed 16 bit number and don't use 64bit
5154 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5155 i
.types
[op
].bitfield
.disp64
= 0;
5158 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5159 if (i
.types
[op
].bitfield
.disp32
5160 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5162 /* If this operand is at most 32 bits, convert
5163 to a signed 32 bit number and don't use 64bit
5165 op_disp
&= (((offsetT
) 2 << 31) - 1);
5166 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5167 i
.types
[op
].bitfield
.disp64
= 0;
5170 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5172 i
.types
[op
].bitfield
.disp8
= 0;
5173 i
.types
[op
].bitfield
.disp16
= 0;
5174 i
.types
[op
].bitfield
.disp32
= 0;
5175 i
.types
[op
].bitfield
.disp32s
= 0;
5176 i
.types
[op
].bitfield
.disp64
= 0;
5180 else if (flag_code
== CODE_64BIT
)
5182 if (fits_in_signed_long (op_disp
))
5184 i
.types
[op
].bitfield
.disp64
= 0;
5185 i
.types
[op
].bitfield
.disp32s
= 1;
5187 if (i
.prefix
[ADDR_PREFIX
]
5188 && fits_in_unsigned_long (op_disp
))
5189 i
.types
[op
].bitfield
.disp32
= 1;
5191 if ((i
.types
[op
].bitfield
.disp32
5192 || i
.types
[op
].bitfield
.disp32s
5193 || i
.types
[op
].bitfield
.disp16
)
5194 && fits_in_disp8 (op_disp
))
5195 i
.types
[op
].bitfield
.disp8
= 1;
5197 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5198 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5200 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5201 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5202 i
.types
[op
].bitfield
.disp8
= 0;
5203 i
.types
[op
].bitfield
.disp16
= 0;
5204 i
.types
[op
].bitfield
.disp32
= 0;
5205 i
.types
[op
].bitfield
.disp32s
= 0;
5206 i
.types
[op
].bitfield
.disp64
= 0;
5209 /* We only support 64bit displacement on constants. */
5210 i
.types
[op
].bitfield
.disp64
= 0;
5214 /* Return 1 if there is a match in broadcast bytes between operand
5215 GIVEN and instruction template T. */
5218 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5220 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5221 && i
.types
[given
].bitfield
.byte
)
5222 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5223 && i
.types
[given
].bitfield
.word
)
5224 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5225 && i
.types
[given
].bitfield
.dword
)
5226 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5227 && i
.types
[given
].bitfield
.qword
));
5230 /* Check if operands are valid for the instruction. */
5233 check_VecOperands (const insn_template
*t
)
5237 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5239 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5240 any one operand are implicity requiring AVX512VL support if the actual
5241 operand size is YMMword or XMMword. Since this function runs after
5242 template matching, there's no need to check for YMMword/XMMword in
5244 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5245 if (!cpu_flags_all_zero (&cpu
)
5246 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5247 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5249 for (op
= 0; op
< t
->operands
; ++op
)
5251 if (t
->operand_types
[op
].bitfield
.zmmword
5252 && (i
.types
[op
].bitfield
.ymmword
5253 || i
.types
[op
].bitfield
.xmmword
))
5255 i
.error
= unsupported
;
5261 /* Without VSIB byte, we can't have a vector register for index. */
5262 if (!t
->opcode_modifier
.vecsib
5264 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5265 || i
.index_reg
->reg_type
.bitfield
.ymmword
5266 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5268 i
.error
= unsupported_vector_index_register
;
5272 /* Check if default mask is allowed. */
5273 if (t
->opcode_modifier
.nodefmask
5274 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5276 i
.error
= no_default_mask
;
5280 /* For VSIB byte, we need a vector register for index, and all vector
5281 registers must be distinct. */
5282 if (t
->opcode_modifier
.vecsib
)
5285 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5286 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5287 || (t
->opcode_modifier
.vecsib
== VecSIB256
5288 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5289 || (t
->opcode_modifier
.vecsib
== VecSIB512
5290 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5292 i
.error
= invalid_vsib_address
;
5296 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5297 if (i
.reg_operands
== 2 && !i
.mask
)
5299 gas_assert (i
.types
[0].bitfield
.regsimd
);
5300 gas_assert (i
.types
[0].bitfield
.xmmword
5301 || i
.types
[0].bitfield
.ymmword
);
5302 gas_assert (i
.types
[2].bitfield
.regsimd
);
5303 gas_assert (i
.types
[2].bitfield
.xmmword
5304 || i
.types
[2].bitfield
.ymmword
);
5305 if (operand_check
== check_none
)
5307 if (register_number (i
.op
[0].regs
)
5308 != register_number (i
.index_reg
)
5309 && register_number (i
.op
[2].regs
)
5310 != register_number (i
.index_reg
)
5311 && register_number (i
.op
[0].regs
)
5312 != register_number (i
.op
[2].regs
))
5314 if (operand_check
== check_error
)
5316 i
.error
= invalid_vector_register_set
;
5319 as_warn (_("mask, index, and destination registers should be distinct"));
5321 else if (i
.reg_operands
== 1 && i
.mask
)
5323 if (i
.types
[1].bitfield
.regsimd
5324 && (i
.types
[1].bitfield
.xmmword
5325 || i
.types
[1].bitfield
.ymmword
5326 || i
.types
[1].bitfield
.zmmword
)
5327 && (register_number (i
.op
[1].regs
)
5328 == register_number (i
.index_reg
)))
5330 if (operand_check
== check_error
)
5332 i
.error
= invalid_vector_register_set
;
5335 if (operand_check
!= check_none
)
5336 as_warn (_("index and destination registers should be distinct"));
5341 /* Check if broadcast is supported by the instruction and is applied
5342 to the memory operand. */
5345 i386_operand_type type
, overlap
;
5347 /* Check if specified broadcast is supported in this instruction,
5348 and its broadcast bytes match the memory operand. */
5349 op
= i
.broadcast
->operand
;
5350 if (!t
->opcode_modifier
.broadcast
5351 || !(i
.flags
[op
] & Operand_Mem
)
5352 || (!i
.types
[op
].bitfield
.unspecified
5353 && !match_broadcast_size (t
, op
)))
5356 i
.error
= unsupported_broadcast
;
5360 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5361 * i
.broadcast
->type
);
5362 operand_type_set (&type
, 0);
5363 switch (i
.broadcast
->bytes
)
5366 type
.bitfield
.word
= 1;
5369 type
.bitfield
.dword
= 1;
5372 type
.bitfield
.qword
= 1;
5375 type
.bitfield
.xmmword
= 1;
5378 type
.bitfield
.ymmword
= 1;
5381 type
.bitfield
.zmmword
= 1;
5387 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5388 if (operand_type_all_zero (&overlap
))
5391 if (t
->opcode_modifier
.checkregsize
)
5395 type
.bitfield
.baseindex
= 1;
5396 for (j
= 0; j
< i
.operands
; ++j
)
5399 && !operand_type_register_match(i
.types
[j
],
5400 t
->operand_types
[j
],
5402 t
->operand_types
[op
]))
5407 /* If broadcast is supported in this instruction, we need to check if
5408 operand of one-element size isn't specified without broadcast. */
5409 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5411 /* Find memory operand. */
5412 for (op
= 0; op
< i
.operands
; op
++)
5413 if (operand_type_check (i
.types
[op
], anymem
))
5415 gas_assert (op
< i
.operands
);
5416 /* Check size of the memory operand. */
5417 if (match_broadcast_size (t
, op
))
5419 i
.error
= broadcast_needed
;
5424 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5426 /* Check if requested masking is supported. */
5429 switch (t
->opcode_modifier
.masking
)
5433 case MERGING_MASKING
:
5434 if (i
.mask
->zeroing
)
5437 i
.error
= unsupported_masking
;
5441 case DYNAMIC_MASKING
:
5442 /* Memory destinations allow only merging masking. */
5443 if (i
.mask
->zeroing
&& i
.mem_operands
)
5445 /* Find memory operand. */
5446 for (op
= 0; op
< i
.operands
; op
++)
5447 if (i
.flags
[op
] & Operand_Mem
)
5449 gas_assert (op
< i
.operands
);
5450 if (op
== i
.operands
- 1)
5452 i
.error
= unsupported_masking
;
5462 /* Check if masking is applied to dest operand. */
5463 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5465 i
.error
= mask_not_on_destination
;
5472 if (!t
->opcode_modifier
.sae
5473 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5475 i
.error
= unsupported_rc_sae
;
5478 /* If the instruction has several immediate operands and one of
5479 them is rounding, the rounding operand should be the last
5480 immediate operand. */
5481 if (i
.imm_operands
> 1
5482 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5484 i
.error
= rc_sae_operand_not_last_imm
;
5489 /* Check vector Disp8 operand. */
5490 if (t
->opcode_modifier
.disp8memshift
5491 && i
.disp_encoding
!= disp_encoding_32bit
)
5494 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5495 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5496 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5499 const i386_operand_type
*type
= NULL
;
5502 for (op
= 0; op
< i
.operands
; op
++)
5503 if (operand_type_check (i
.types
[op
], anymem
))
5505 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5506 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5507 else if (t
->operand_types
[op
].bitfield
.xmmword
5508 + t
->operand_types
[op
].bitfield
.ymmword
5509 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5510 type
= &t
->operand_types
[op
];
5511 else if (!i
.types
[op
].bitfield
.unspecified
)
5512 type
= &i
.types
[op
];
5514 else if (i
.types
[op
].bitfield
.regsimd
5515 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5517 if (i
.types
[op
].bitfield
.zmmword
)
5519 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5521 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5527 if (type
->bitfield
.zmmword
)
5529 else if (type
->bitfield
.ymmword
)
5531 else if (type
->bitfield
.xmmword
)
5535 /* For the check in fits_in_disp8(). */
5536 if (i
.memshift
== 0)
5540 for (op
= 0; op
< i
.operands
; op
++)
5541 if (operand_type_check (i
.types
[op
], disp
)
5542 && i
.op
[op
].disps
->X_op
== O_constant
)
5544 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5546 i
.types
[op
].bitfield
.disp8
= 1;
5549 i
.types
[op
].bitfield
.disp8
= 0;
5558 /* Check if operands are valid for the instruction. Update VEX
5562 VEX_check_operands (const insn_template
*t
)
5564 if (i
.vec_encoding
== vex_encoding_evex
)
5566 /* This instruction must be encoded with EVEX prefix. */
5567 if (!is_evex_encoding (t
))
5569 i
.error
= unsupported
;
5575 if (!t
->opcode_modifier
.vex
)
5577 /* This instruction template doesn't have VEX prefix. */
5578 if (i
.vec_encoding
!= vex_encoding_default
)
5580 i
.error
= unsupported
;
5586 /* Only check VEX_Imm4, which must be the first operand. */
5587 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5589 if (i
.op
[0].imms
->X_op
!= O_constant
5590 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5596 /* Turn off Imm8 so that update_imm won't complain. */
5597 i
.types
[0] = vec_imm4
;
5603 static const insn_template
*
5604 match_template (char mnem_suffix
)
5606 /* Points to template once we've found it. */
5607 const insn_template
*t
;
5608 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5609 i386_operand_type overlap4
;
5610 unsigned int found_reverse_match
;
5611 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5612 i386_operand_type operand_types
[MAX_OPERANDS
];
5613 int addr_prefix_disp
;
5615 unsigned int found_cpu_match
, size_match
;
5616 unsigned int check_register
;
5617 enum i386_error specific_error
= 0;
5619 #if MAX_OPERANDS != 5
5620 # error "MAX_OPERANDS must be 5."
5623 found_reverse_match
= 0;
5624 addr_prefix_disp
= -1;
5626 memset (&suffix_check
, 0, sizeof (suffix_check
));
5627 if (intel_syntax
&& i
.broadcast
)
5629 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5630 suffix_check
.no_bsuf
= 1;
5631 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5632 suffix_check
.no_wsuf
= 1;
5633 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5634 suffix_check
.no_ssuf
= 1;
5635 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5636 suffix_check
.no_lsuf
= 1;
5637 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5638 suffix_check
.no_qsuf
= 1;
5639 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5640 suffix_check
.no_ldsuf
= 1;
5642 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5645 switch (mnem_suffix
)
5647 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5648 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5649 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5650 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5651 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5655 /* Must have right number of operands. */
5656 i
.error
= number_of_operands_mismatch
;
5658 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5660 addr_prefix_disp
= -1;
5661 found_reverse_match
= 0;
5663 if (i
.operands
!= t
->operands
)
5666 /* Check processor support. */
5667 i
.error
= unsupported
;
5668 found_cpu_match
= (cpu_flags_match (t
)
5669 == CPU_FLAGS_PERFECT_MATCH
);
5670 if (!found_cpu_match
)
5673 /* Check AT&T mnemonic. */
5674 i
.error
= unsupported_with_intel_mnemonic
;
5675 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5678 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5679 i
.error
= unsupported_syntax
;
5680 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5681 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5682 || (intel64
&& t
->opcode_modifier
.amd64
)
5683 || (!intel64
&& t
->opcode_modifier
.intel64
))
5686 /* Check the suffix, except for some instructions in intel mode. */
5687 i
.error
= invalid_instruction_suffix
;
5688 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5689 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5690 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5691 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5692 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5693 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5694 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5696 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5697 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5698 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5699 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5700 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5701 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5702 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5705 size_match
= operand_size_match (t
);
5709 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5710 operand_types
[j
] = t
->operand_types
[j
];
5712 /* In general, don't allow 64-bit operands in 32-bit mode. */
5713 if (i
.suffix
== QWORD_MNEM_SUFFIX
5714 && flag_code
!= CODE_64BIT
5716 ? (!t
->opcode_modifier
.ignoresize
5717 && !t
->opcode_modifier
.broadcast
5718 && !intel_float_operand (t
->name
))
5719 : intel_float_operand (t
->name
) != 2)
5720 && ((!operand_types
[0].bitfield
.regmmx
5721 && !operand_types
[0].bitfield
.regsimd
)
5722 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5723 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5724 && (t
->base_opcode
!= 0x0fc7
5725 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5728 /* In general, don't allow 32-bit operands on pre-386. */
5729 else if (i
.suffix
== LONG_MNEM_SUFFIX
5730 && !cpu_arch_flags
.bitfield
.cpui386
5732 ? (!t
->opcode_modifier
.ignoresize
5733 && !intel_float_operand (t
->name
))
5734 : intel_float_operand (t
->name
) != 2)
5735 && ((!operand_types
[0].bitfield
.regmmx
5736 && !operand_types
[0].bitfield
.regsimd
)
5737 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5738 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5741 /* Do not verify operands when there are none. */
5745 /* We've found a match; break out of loop. */
5749 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5750 into Disp32/Disp16/Disp32 operand. */
5751 if (i
.prefix
[ADDR_PREFIX
] != 0)
5753 /* There should be only one Disp operand. */
5757 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5759 if (operand_types
[j
].bitfield
.disp16
)
5761 addr_prefix_disp
= j
;
5762 operand_types
[j
].bitfield
.disp32
= 1;
5763 operand_types
[j
].bitfield
.disp16
= 0;
5769 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5771 if (operand_types
[j
].bitfield
.disp32
)
5773 addr_prefix_disp
= j
;
5774 operand_types
[j
].bitfield
.disp32
= 0;
5775 operand_types
[j
].bitfield
.disp16
= 1;
5781 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5783 if (operand_types
[j
].bitfield
.disp64
)
5785 addr_prefix_disp
= j
;
5786 operand_types
[j
].bitfield
.disp64
= 0;
5787 operand_types
[j
].bitfield
.disp32
= 1;
5795 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5796 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5799 /* We check register size if needed. */
5800 if (t
->opcode_modifier
.checkregsize
)
5802 check_register
= (1 << t
->operands
) - 1;
5804 check_register
&= ~(1 << i
.broadcast
->operand
);
5809 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5810 switch (t
->operands
)
5813 if (!operand_type_match (overlap0
, i
.types
[0]))
5817 /* xchg %eax, %eax is a special case. It is an alias for nop
5818 only in 32bit mode and we can use opcode 0x90. In 64bit
5819 mode, we can't use 0x90 for xchg %eax, %eax since it should
5820 zero-extend %eax to %rax. */
5821 if (flag_code
== CODE_64BIT
5822 && t
->base_opcode
== 0x90
5823 && i
.types
[0].bitfield
.acc
&& i
.types
[0].bitfield
.dword
5824 && i
.types
[1].bitfield
.acc
&& i
.types
[1].bitfield
.dword
)
5826 /* xrelease mov %eax, <disp> is another special case. It must not
5827 match the accumulator-only encoding of mov. */
5828 if (flag_code
!= CODE_64BIT
5830 && t
->base_opcode
== 0xa0
5831 && i
.types
[0].bitfield
.acc
5832 && operand_type_check (i
.types
[1], anymem
))
5837 if (!(size_match
& MATCH_STRAIGHT
))
5839 /* Reverse direction of operands if swapping is possible in the first
5840 place (operands need to be symmetric) and
5841 - the load form is requested, and the template is a store form,
5842 - the store form is requested, and the template is a load form,
5843 - the non-default (swapped) form is requested. */
5844 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5845 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5846 && !operand_type_all_zero (&overlap1
))
5847 switch (i
.dir_encoding
)
5849 case dir_encoding_load
:
5850 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5851 || operand_types
[i
.operands
- 1].bitfield
.regmem
)
5855 case dir_encoding_store
:
5856 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5857 && !operand_types
[i
.operands
- 1].bitfield
.regmem
)
5861 case dir_encoding_swap
:
5864 case dir_encoding_default
:
5867 /* If we want store form, we skip the current load. */
5868 if ((i
.dir_encoding
== dir_encoding_store
5869 || i
.dir_encoding
== dir_encoding_swap
)
5870 && i
.mem_operands
== 0
5871 && t
->opcode_modifier
.load
)
5876 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5877 if (!operand_type_match (overlap0
, i
.types
[0])
5878 || !operand_type_match (overlap1
, i
.types
[1])
5879 || ((check_register
& 3) == 3
5880 && !operand_type_register_match (i
.types
[0],
5885 /* Check if other direction is valid ... */
5886 if (!t
->opcode_modifier
.d
)
5890 if (!(size_match
& MATCH_REVERSE
))
5892 /* Try reversing direction of operands. */
5893 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
5894 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
5895 if (!operand_type_match (overlap0
, i
.types
[0])
5896 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
5898 && !operand_type_register_match (i
.types
[0],
5899 operand_types
[i
.operands
- 1],
5900 i
.types
[i
.operands
- 1],
5903 /* Does not match either direction. */
5906 /* found_reverse_match holds which of D or FloatR
5908 if (!t
->opcode_modifier
.d
)
5909 found_reverse_match
= 0;
5910 else if (operand_types
[0].bitfield
.tbyte
)
5911 found_reverse_match
= Opcode_FloatD
;
5912 else if (operand_types
[0].bitfield
.xmmword
5913 || operand_types
[i
.operands
- 1].bitfield
.xmmword
5914 || operand_types
[0].bitfield
.regmmx
5915 || operand_types
[i
.operands
- 1].bitfield
.regmmx
5916 || is_any_vex_encoding(t
))
5917 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
5918 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
5920 found_reverse_match
= Opcode_D
;
5921 if (t
->opcode_modifier
.floatr
)
5922 found_reverse_match
|= Opcode_FloatR
;
5926 /* Found a forward 2 operand match here. */
5927 switch (t
->operands
)
5930 overlap4
= operand_type_and (i
.types
[4],
5934 overlap3
= operand_type_and (i
.types
[3],
5938 overlap2
= operand_type_and (i
.types
[2],
5943 switch (t
->operands
)
5946 if (!operand_type_match (overlap4
, i
.types
[4])
5947 || !operand_type_register_match (i
.types
[3],
5954 if (!operand_type_match (overlap3
, i
.types
[3])
5955 || ((check_register
& 0xa) == 0xa
5956 && !operand_type_register_match (i
.types
[1],
5960 || ((check_register
& 0xc) == 0xc
5961 && !operand_type_register_match (i
.types
[2],
5968 /* Here we make use of the fact that there are no
5969 reverse match 3 operand instructions. */
5970 if (!operand_type_match (overlap2
, i
.types
[2])
5971 || ((check_register
& 5) == 5
5972 && !operand_type_register_match (i
.types
[0],
5976 || ((check_register
& 6) == 6
5977 && !operand_type_register_match (i
.types
[1],
5985 /* Found either forward/reverse 2, 3 or 4 operand match here:
5986 slip through to break. */
5988 if (!found_cpu_match
)
5991 /* Check if vector and VEX operands are valid. */
5992 if (check_VecOperands (t
) || VEX_check_operands (t
))
5994 specific_error
= i
.error
;
5998 /* We've found a match; break out of loop. */
6002 if (t
== current_templates
->end
)
6004 /* We found no match. */
6005 const char *err_msg
;
6006 switch (specific_error
? specific_error
: i
.error
)
6010 case operand_size_mismatch
:
6011 err_msg
= _("operand size mismatch");
6013 case operand_type_mismatch
:
6014 err_msg
= _("operand type mismatch");
6016 case register_type_mismatch
:
6017 err_msg
= _("register type mismatch");
6019 case number_of_operands_mismatch
:
6020 err_msg
= _("number of operands mismatch");
6022 case invalid_instruction_suffix
:
6023 err_msg
= _("invalid instruction suffix");
6026 err_msg
= _("constant doesn't fit in 4 bits");
6028 case unsupported_with_intel_mnemonic
:
6029 err_msg
= _("unsupported with Intel mnemonic");
6031 case unsupported_syntax
:
6032 err_msg
= _("unsupported syntax");
6035 as_bad (_("unsupported instruction `%s'"),
6036 current_templates
->start
->name
);
6038 case invalid_vsib_address
:
6039 err_msg
= _("invalid VSIB address");
6041 case invalid_vector_register_set
:
6042 err_msg
= _("mask, index, and destination registers must be distinct");
6044 case unsupported_vector_index_register
:
6045 err_msg
= _("unsupported vector index register");
6047 case unsupported_broadcast
:
6048 err_msg
= _("unsupported broadcast");
6050 case broadcast_needed
:
6051 err_msg
= _("broadcast is needed for operand of such type");
6053 case unsupported_masking
:
6054 err_msg
= _("unsupported masking");
6056 case mask_not_on_destination
:
6057 err_msg
= _("mask not on destination operand");
6059 case no_default_mask
:
6060 err_msg
= _("default mask isn't allowed");
6062 case unsupported_rc_sae
:
6063 err_msg
= _("unsupported static rounding/sae");
6065 case rc_sae_operand_not_last_imm
:
6067 err_msg
= _("RC/SAE operand must precede immediate operands");
6069 err_msg
= _("RC/SAE operand must follow immediate operands");
6071 case invalid_register_operand
:
6072 err_msg
= _("invalid register operand");
6075 as_bad (_("%s for `%s'"), err_msg
,
6076 current_templates
->start
->name
);
6080 if (!quiet_warnings
)
6083 && (i
.types
[0].bitfield
.jumpabsolute
6084 != operand_types
[0].bitfield
.jumpabsolute
))
6086 as_warn (_("indirect %s without `*'"), t
->name
);
6089 if (t
->opcode_modifier
.isprefix
6090 && t
->opcode_modifier
.ignoresize
)
6092 /* Warn them that a data or address size prefix doesn't
6093 affect assembly of the next line of code. */
6094 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6098 /* Copy the template we found. */
6101 if (addr_prefix_disp
!= -1)
6102 i
.tm
.operand_types
[addr_prefix_disp
]
6103 = operand_types
[addr_prefix_disp
];
6105 if (found_reverse_match
)
6107 /* If we found a reverse match we must alter the opcode
6108 direction bit. found_reverse_match holds bits to change
6109 (different for int & float insns). */
6111 i
.tm
.base_opcode
^= found_reverse_match
;
6113 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6114 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6123 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
6124 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
6126 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
6128 as_bad (_("`%s' operand %d must use `%ses' segment"),
6134 /* There's only ever one segment override allowed per instruction.
6135 This instruction possibly has a legal segment override on the
6136 second operand, so copy the segment to where non-string
6137 instructions store it, allowing common code. */
6138 i
.seg
[0] = i
.seg
[1];
6140 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
6142 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
6144 as_bad (_("`%s' operand %d must use `%ses' segment"),
6155 process_suffix (void)
6157 /* If matched instruction specifies an explicit instruction mnemonic
6159 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6160 i
.suffix
= WORD_MNEM_SUFFIX
;
6161 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6162 i
.suffix
= LONG_MNEM_SUFFIX
;
6163 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6164 i
.suffix
= QWORD_MNEM_SUFFIX
;
6165 else if (i
.reg_operands
)
6167 /* If there's no instruction mnemonic suffix we try to invent one
6168 based on register operands. */
6171 /* We take i.suffix from the last register operand specified,
6172 Destination register type is more significant than source
6173 register type. crc32 in SSE4.2 prefers source register
6175 if (i
.tm
.base_opcode
== 0xf20f38f0 && i
.types
[0].bitfield
.reg
)
6177 if (i
.types
[0].bitfield
.byte
)
6178 i
.suffix
= BYTE_MNEM_SUFFIX
;
6179 else if (i
.types
[0].bitfield
.word
)
6180 i
.suffix
= WORD_MNEM_SUFFIX
;
6181 else if (i
.types
[0].bitfield
.dword
)
6182 i
.suffix
= LONG_MNEM_SUFFIX
;
6183 else if (i
.types
[0].bitfield
.qword
)
6184 i
.suffix
= QWORD_MNEM_SUFFIX
;
6191 if (i
.tm
.base_opcode
== 0xf20f38f0)
6193 /* We have to know the operand size for crc32. */
6194 as_bad (_("ambiguous memory operand size for `%s`"),
6199 for (op
= i
.operands
; --op
>= 0;)
6200 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
6201 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
6203 if (!i
.types
[op
].bitfield
.reg
)
6205 if (i
.types
[op
].bitfield
.byte
)
6206 i
.suffix
= BYTE_MNEM_SUFFIX
;
6207 else if (i
.types
[op
].bitfield
.word
)
6208 i
.suffix
= WORD_MNEM_SUFFIX
;
6209 else if (i
.types
[op
].bitfield
.dword
)
6210 i
.suffix
= LONG_MNEM_SUFFIX
;
6211 else if (i
.types
[op
].bitfield
.qword
)
6212 i
.suffix
= QWORD_MNEM_SUFFIX
;
6219 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6222 && i
.tm
.opcode_modifier
.ignoresize
6223 && i
.tm
.opcode_modifier
.no_bsuf
)
6225 else if (!check_byte_reg ())
6228 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6231 && i
.tm
.opcode_modifier
.ignoresize
6232 && i
.tm
.opcode_modifier
.no_lsuf
6233 && !i
.tm
.opcode_modifier
.todword
6234 && !i
.tm
.opcode_modifier
.toqword
)
6236 else if (!check_long_reg ())
6239 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6242 && i
.tm
.opcode_modifier
.ignoresize
6243 && i
.tm
.opcode_modifier
.no_qsuf
6244 && !i
.tm
.opcode_modifier
.todword
6245 && !i
.tm
.opcode_modifier
.toqword
)
6247 else if (!check_qword_reg ())
6250 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6253 && i
.tm
.opcode_modifier
.ignoresize
6254 && i
.tm
.opcode_modifier
.no_wsuf
)
6256 else if (!check_word_reg ())
6259 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6260 /* Do nothing if the instruction is going to ignore the prefix. */
6265 else if (i
.tm
.opcode_modifier
.defaultsize
6267 /* exclude fldenv/frstor/fsave/fstenv */
6268 && i
.tm
.opcode_modifier
.no_ssuf
)
6270 if (stackop_size
== LONG_MNEM_SUFFIX
6271 && i
.tm
.base_opcode
== 0xcf)
6273 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6274 .code16gcc directive to support 16-bit mode with
6275 32-bit address. For IRET without a suffix, generate
6276 16-bit IRET (opcode 0xcf) to return from an interrupt
6278 i
.suffix
= WORD_MNEM_SUFFIX
;
6279 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6282 i
.suffix
= stackop_size
;
6284 else if (intel_syntax
6286 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
6287 || i
.tm
.opcode_modifier
.jumpbyte
6288 || i
.tm
.opcode_modifier
.jumpintersegment
6289 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6290 && i
.tm
.extension_opcode
<= 3)))
6295 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6297 i
.suffix
= QWORD_MNEM_SUFFIX
;
6302 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6303 i
.suffix
= LONG_MNEM_SUFFIX
;
6306 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6307 i
.suffix
= WORD_MNEM_SUFFIX
;
6316 if (i
.tm
.opcode_modifier
.w
)
6318 as_bad (_("no instruction mnemonic suffix given and "
6319 "no register operands; can't size instruction"));
6325 unsigned int suffixes
;
6327 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6328 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6330 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6332 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6334 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6336 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6339 /* There are more than suffix matches. */
6340 if (i
.tm
.opcode_modifier
.w
6341 || ((suffixes
& (suffixes
- 1))
6342 && !i
.tm
.opcode_modifier
.defaultsize
6343 && !i
.tm
.opcode_modifier
.ignoresize
))
6345 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6351 /* Change the opcode based on the operand size given by i.suffix. */
6354 /* Size floating point instruction. */
6355 case LONG_MNEM_SUFFIX
:
6356 if (i
.tm
.opcode_modifier
.floatmf
)
6358 i
.tm
.base_opcode
^= 4;
6362 case WORD_MNEM_SUFFIX
:
6363 case QWORD_MNEM_SUFFIX
:
6364 /* It's not a byte, select word/dword operation. */
6365 if (i
.tm
.opcode_modifier
.w
)
6367 if (i
.tm
.opcode_modifier
.shortform
)
6368 i
.tm
.base_opcode
|= 8;
6370 i
.tm
.base_opcode
|= 1;
6373 case SHORT_MNEM_SUFFIX
:
6374 /* Now select between word & dword operations via the operand
6375 size prefix, except for instructions that will ignore this
6377 if (i
.reg_operands
> 0
6378 && i
.types
[0].bitfield
.reg
6379 && i
.tm
.opcode_modifier
.addrprefixopreg
6380 && (i
.tm
.opcode_modifier
.immext
6381 || i
.operands
== 1))
6383 /* The address size override prefix changes the size of the
6385 if ((flag_code
== CODE_32BIT
6386 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6387 || (flag_code
!= CODE_32BIT
6388 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6389 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6392 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6393 && !i
.tm
.opcode_modifier
.ignoresize
6394 && !i
.tm
.opcode_modifier
.floatmf
6395 && !is_any_vex_encoding (&i
.tm
)
6396 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6397 || (flag_code
== CODE_64BIT
6398 && i
.tm
.opcode_modifier
.jumpbyte
)))
6400 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6402 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6403 prefix
= ADDR_PREFIX_OPCODE
;
6405 if (!add_prefix (prefix
))
6409 /* Set mode64 for an operand. */
6410 if (i
.suffix
== QWORD_MNEM_SUFFIX
6411 && flag_code
== CODE_64BIT
6412 && !i
.tm
.opcode_modifier
.norex64
6413 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6415 && ! (i
.operands
== 2
6416 && i
.tm
.base_opcode
== 0x90
6417 && i
.tm
.extension_opcode
== None
6418 && i
.types
[0].bitfield
.acc
&& i
.types
[0].bitfield
.qword
6419 && i
.types
[1].bitfield
.acc
&& i
.types
[1].bitfield
.qword
))
6425 if (i
.reg_operands
!= 0
6427 && i
.tm
.opcode_modifier
.addrprefixopreg
6428 && !i
.tm
.opcode_modifier
.immext
)
6430 /* Check invalid register operand when the address size override
6431 prefix changes the size of register operands. */
6433 enum { need_word
, need_dword
, need_qword
} need
;
6435 if (flag_code
== CODE_32BIT
)
6436 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6439 if (i
.prefix
[ADDR_PREFIX
])
6442 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6445 for (op
= 0; op
< i
.operands
; op
++)
6446 if (i
.types
[op
].bitfield
.reg
6447 && ((need
== need_word
6448 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6449 || (need
== need_dword
6450 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6451 || (need
== need_qword
6452 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6454 as_bad (_("invalid register operand size for `%s'"),
6464 check_byte_reg (void)
6468 for (op
= i
.operands
; --op
>= 0;)
6470 /* Skip non-register operands. */
6471 if (!i
.types
[op
].bitfield
.reg
)
6474 /* If this is an eight bit register, it's OK. If it's the 16 or
6475 32 bit version of an eight bit register, we will just use the
6476 low portion, and that's OK too. */
6477 if (i
.types
[op
].bitfield
.byte
)
6480 /* I/O port address operands are OK too. */
6481 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6484 /* crc32 doesn't generate this warning. */
6485 if (i
.tm
.base_opcode
== 0xf20f38f0)
6488 if ((i
.types
[op
].bitfield
.word
6489 || i
.types
[op
].bitfield
.dword
6490 || i
.types
[op
].bitfield
.qword
)
6491 && i
.op
[op
].regs
->reg_num
< 4
6492 /* Prohibit these changes in 64bit mode, since the lowering
6493 would be more complicated. */
6494 && flag_code
!= CODE_64BIT
)
6496 #if REGISTER_WARNINGS
6497 if (!quiet_warnings
)
6498 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6500 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6501 ? REGNAM_AL
- REGNAM_AX
6502 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6504 i
.op
[op
].regs
->reg_name
,
6509 /* Any other register is bad. */
6510 if (i
.types
[op
].bitfield
.reg
6511 || i
.types
[op
].bitfield
.regmmx
6512 || i
.types
[op
].bitfield
.regsimd
6513 || i
.types
[op
].bitfield
.sreg2
6514 || i
.types
[op
].bitfield
.sreg3
6515 || i
.types
[op
].bitfield
.control
6516 || i
.types
[op
].bitfield
.debug
6517 || i
.types
[op
].bitfield
.test
)
6519 as_bad (_("`%s%s' not allowed with `%s%c'"),
6521 i
.op
[op
].regs
->reg_name
,
6531 check_long_reg (void)
6535 for (op
= i
.operands
; --op
>= 0;)
6536 /* Skip non-register operands. */
6537 if (!i
.types
[op
].bitfield
.reg
)
6539 /* Reject eight bit registers, except where the template requires
6540 them. (eg. movzb) */
6541 else if (i
.types
[op
].bitfield
.byte
6542 && (i
.tm
.operand_types
[op
].bitfield
.reg
6543 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6544 && (i
.tm
.operand_types
[op
].bitfield
.word
6545 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6547 as_bad (_("`%s%s' not allowed with `%s%c'"),
6549 i
.op
[op
].regs
->reg_name
,
6554 /* Warn if the e prefix on a general reg is missing. */
6555 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6556 && i
.types
[op
].bitfield
.word
6557 && (i
.tm
.operand_types
[op
].bitfield
.reg
6558 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6559 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6561 /* Prohibit these changes in the 64bit mode, since the
6562 lowering is more complicated. */
6563 if (flag_code
== CODE_64BIT
)
6565 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6566 register_prefix
, i
.op
[op
].regs
->reg_name
,
6570 #if REGISTER_WARNINGS
6571 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6573 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6574 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6577 /* Warn if the r prefix on a general reg is present. */
6578 else if (i
.types
[op
].bitfield
.qword
6579 && (i
.tm
.operand_types
[op
].bitfield
.reg
6580 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6581 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6584 && i
.tm
.opcode_modifier
.toqword
6585 && !i
.types
[0].bitfield
.regsimd
)
6587 /* Convert to QWORD. We want REX byte. */
6588 i
.suffix
= QWORD_MNEM_SUFFIX
;
6592 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6593 register_prefix
, i
.op
[op
].regs
->reg_name
,
6602 check_qword_reg (void)
6606 for (op
= i
.operands
; --op
>= 0; )
6607 /* Skip non-register operands. */
6608 if (!i
.types
[op
].bitfield
.reg
)
6610 /* Reject eight bit registers, except where the template requires
6611 them. (eg. movzb) */
6612 else if (i
.types
[op
].bitfield
.byte
6613 && (i
.tm
.operand_types
[op
].bitfield
.reg
6614 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6615 && (i
.tm
.operand_types
[op
].bitfield
.word
6616 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6618 as_bad (_("`%s%s' not allowed with `%s%c'"),
6620 i
.op
[op
].regs
->reg_name
,
6625 /* Warn if the r prefix on a general reg is missing. */
6626 else if ((i
.types
[op
].bitfield
.word
6627 || i
.types
[op
].bitfield
.dword
)
6628 && (i
.tm
.operand_types
[op
].bitfield
.reg
6629 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6630 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6632 /* Prohibit these changes in the 64bit mode, since the
6633 lowering is more complicated. */
6635 && i
.tm
.opcode_modifier
.todword
6636 && !i
.types
[0].bitfield
.regsimd
)
6638 /* Convert to DWORD. We don't want REX byte. */
6639 i
.suffix
= LONG_MNEM_SUFFIX
;
6643 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6644 register_prefix
, i
.op
[op
].regs
->reg_name
,
6653 check_word_reg (void)
6656 for (op
= i
.operands
; --op
>= 0;)
6657 /* Skip non-register operands. */
6658 if (!i
.types
[op
].bitfield
.reg
)
6660 /* Reject eight bit registers, except where the template requires
6661 them. (eg. movzb) */
6662 else if (i
.types
[op
].bitfield
.byte
6663 && (i
.tm
.operand_types
[op
].bitfield
.reg
6664 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6665 && (i
.tm
.operand_types
[op
].bitfield
.word
6666 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6668 as_bad (_("`%s%s' not allowed with `%s%c'"),
6670 i
.op
[op
].regs
->reg_name
,
6675 /* Warn if the e or r prefix on a general reg is present. */
6676 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6677 && (i
.types
[op
].bitfield
.dword
6678 || i
.types
[op
].bitfield
.qword
)
6679 && (i
.tm
.operand_types
[op
].bitfield
.reg
6680 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6681 && i
.tm
.operand_types
[op
].bitfield
.word
)
6683 /* Prohibit these changes in the 64bit mode, since the
6684 lowering is more complicated. */
6685 if (flag_code
== CODE_64BIT
)
6687 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6688 register_prefix
, i
.op
[op
].regs
->reg_name
,
6692 #if REGISTER_WARNINGS
6693 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6695 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6696 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6703 update_imm (unsigned int j
)
6705 i386_operand_type overlap
= i
.types
[j
];
6706 if ((overlap
.bitfield
.imm8
6707 || overlap
.bitfield
.imm8s
6708 || overlap
.bitfield
.imm16
6709 || overlap
.bitfield
.imm32
6710 || overlap
.bitfield
.imm32s
6711 || overlap
.bitfield
.imm64
)
6712 && !operand_type_equal (&overlap
, &imm8
)
6713 && !operand_type_equal (&overlap
, &imm8s
)
6714 && !operand_type_equal (&overlap
, &imm16
)
6715 && !operand_type_equal (&overlap
, &imm32
)
6716 && !operand_type_equal (&overlap
, &imm32s
)
6717 && !operand_type_equal (&overlap
, &imm64
))
6721 i386_operand_type temp
;
6723 operand_type_set (&temp
, 0);
6724 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6726 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6727 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6729 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6730 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6731 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6733 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6734 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6737 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6740 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6741 || operand_type_equal (&overlap
, &imm16_32
)
6742 || operand_type_equal (&overlap
, &imm16_32s
))
6744 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6749 if (!operand_type_equal (&overlap
, &imm8
)
6750 && !operand_type_equal (&overlap
, &imm8s
)
6751 && !operand_type_equal (&overlap
, &imm16
)
6752 && !operand_type_equal (&overlap
, &imm32
)
6753 && !operand_type_equal (&overlap
, &imm32s
)
6754 && !operand_type_equal (&overlap
, &imm64
))
6756 as_bad (_("no instruction mnemonic suffix given; "
6757 "can't determine immediate size"));
6761 i
.types
[j
] = overlap
;
6771 /* Update the first 2 immediate operands. */
6772 n
= i
.operands
> 2 ? 2 : i
.operands
;
6775 for (j
= 0; j
< n
; j
++)
6776 if (update_imm (j
) == 0)
6779 /* The 3rd operand can't be immediate operand. */
6780 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6787 process_operands (void)
6789 /* Default segment register this instruction will use for memory
6790 accesses. 0 means unknown. This is only for optimizing out
6791 unnecessary segment overrides. */
6792 const seg_entry
*default_seg
= 0;
6794 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6796 unsigned int dupl
= i
.operands
;
6797 unsigned int dest
= dupl
- 1;
6800 /* The destination must be an xmm register. */
6801 gas_assert (i
.reg_operands
6802 && MAX_OPERANDS
> dupl
6803 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6805 if (i
.tm
.operand_types
[0].bitfield
.acc
6806 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6808 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6810 /* Keep xmm0 for instructions with VEX prefix and 3
6812 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6813 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6818 /* We remove the first xmm0 and keep the number of
6819 operands unchanged, which in fact duplicates the
6821 for (j
= 1; j
< i
.operands
; j
++)
6823 i
.op
[j
- 1] = i
.op
[j
];
6824 i
.types
[j
- 1] = i
.types
[j
];
6825 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6829 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6831 gas_assert ((MAX_OPERANDS
- 1) > dupl
6832 && (i
.tm
.opcode_modifier
.vexsources
6835 /* Add the implicit xmm0 for instructions with VEX prefix
6837 for (j
= i
.operands
; j
> 0; j
--)
6839 i
.op
[j
] = i
.op
[j
- 1];
6840 i
.types
[j
] = i
.types
[j
- 1];
6841 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6844 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6845 i
.types
[0] = regxmm
;
6846 i
.tm
.operand_types
[0] = regxmm
;
6849 i
.reg_operands
+= 2;
6854 i
.op
[dupl
] = i
.op
[dest
];
6855 i
.types
[dupl
] = i
.types
[dest
];
6856 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6865 i
.op
[dupl
] = i
.op
[dest
];
6866 i
.types
[dupl
] = i
.types
[dest
];
6867 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6870 if (i
.tm
.opcode_modifier
.immext
)
6873 else if (i
.tm
.operand_types
[0].bitfield
.acc
6874 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6878 for (j
= 1; j
< i
.operands
; j
++)
6880 i
.op
[j
- 1] = i
.op
[j
];
6881 i
.types
[j
- 1] = i
.types
[j
];
6883 /* We need to adjust fields in i.tm since they are used by
6884 build_modrm_byte. */
6885 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6892 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6894 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6896 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6897 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6898 regnum
= register_number (i
.op
[1].regs
);
6899 first_reg_in_group
= regnum
& ~3;
6900 last_reg_in_group
= first_reg_in_group
+ 3;
6901 if (regnum
!= first_reg_in_group
)
6902 as_warn (_("source register `%s%s' implicitly denotes"
6903 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6904 register_prefix
, i
.op
[1].regs
->reg_name
,
6905 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6906 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6909 else if (i
.tm
.opcode_modifier
.regkludge
)
6911 /* The imul $imm, %reg instruction is converted into
6912 imul $imm, %reg, %reg, and the clr %reg instruction
6913 is converted into xor %reg, %reg. */
6915 unsigned int first_reg_op
;
6917 if (operand_type_check (i
.types
[0], reg
))
6921 /* Pretend we saw the extra register operand. */
6922 gas_assert (i
.reg_operands
== 1
6923 && i
.op
[first_reg_op
+ 1].regs
== 0);
6924 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6925 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6930 if (i
.tm
.opcode_modifier
.shortform
)
6932 if (i
.types
[0].bitfield
.sreg2
6933 || i
.types
[0].bitfield
.sreg3
)
6935 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6936 && i
.op
[0].regs
->reg_num
== 1)
6938 as_bad (_("you can't `pop %scs'"), register_prefix
);
6941 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6942 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6947 /* The register or float register operand is in operand
6951 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
6952 || operand_type_check (i
.types
[0], reg
))
6956 /* Register goes in low 3 bits of opcode. */
6957 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6958 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6960 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6962 /* Warn about some common errors, but press on regardless.
6963 The first case can be generated by gcc (<= 2.8.1). */
6964 if (i
.operands
== 2)
6966 /* Reversed arguments on faddp, fsubp, etc. */
6967 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6968 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6969 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6973 /* Extraneous `l' suffix on fp insn. */
6974 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6975 register_prefix
, i
.op
[0].regs
->reg_name
);
6980 else if (i
.tm
.opcode_modifier
.modrm
)
6982 /* The opcode is completed (modulo i.tm.extension_opcode which
6983 must be put into the modrm byte). Now, we make the modrm and
6984 index base bytes based on all the info we've collected. */
6986 default_seg
= build_modrm_byte ();
6988 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6992 else if (i
.tm
.opcode_modifier
.isstring
)
6994 /* For the string instructions that allow a segment override
6995 on one of their operands, the default segment is ds. */
6999 if (i
.tm
.base_opcode
== 0x8d /* lea */
7002 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7004 /* If a segment was explicitly specified, and the specified segment
7005 is not the default, use an opcode prefix to select it. If we
7006 never figured out what the default segment is, then default_seg
7007 will be zero at this point, and the specified segment prefix will
7009 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
7011 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7017 static const seg_entry
*
7018 build_modrm_byte (void)
7020 const seg_entry
*default_seg
= 0;
7021 unsigned int source
, dest
;
7024 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7027 unsigned int nds
, reg_slot
;
7030 dest
= i
.operands
- 1;
7033 /* There are 2 kinds of instructions:
7034 1. 5 operands: 4 register operands or 3 register operands
7035 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
7036 VexW0 or VexW1. The destination must be either XMM, YMM or
7038 2. 4 operands: 4 register operands or 3 register operands
7039 plus 1 memory operand, with VexXDS. */
7040 gas_assert ((i
.reg_operands
== 4
7041 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7042 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7043 && i
.tm
.opcode_modifier
.vexw
7044 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
7046 /* If VexW1 is set, the first non-immediate operand is the source and
7047 the second non-immediate one is encoded in the immediate operand. */
7048 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7050 source
= i
.imm_operands
;
7051 reg_slot
= i
.imm_operands
+ 1;
7055 source
= i
.imm_operands
+ 1;
7056 reg_slot
= i
.imm_operands
;
7059 if (i
.imm_operands
== 0)
7061 /* When there is no immediate operand, generate an 8bit
7062 immediate operand to encode the first operand. */
7063 exp
= &im_expressions
[i
.imm_operands
++];
7064 i
.op
[i
.operands
].imms
= exp
;
7065 i
.types
[i
.operands
] = imm8
;
7068 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
7069 exp
->X_op
= O_constant
;
7070 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7071 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7075 unsigned int imm_slot
;
7077 gas_assert (i
.imm_operands
== 1 && i
.types
[0].bitfield
.vec_imm4
);
7079 if (i
.tm
.opcode_modifier
.immext
)
7081 /* When ImmExt is set, the immediate byte is the last
7083 imm_slot
= i
.operands
- 1;
7091 /* Turn on Imm8 so that output_imm will generate it. */
7092 i
.types
[imm_slot
].bitfield
.imm8
= 1;
7095 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
7096 i
.op
[imm_slot
].imms
->X_add_number
7097 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7098 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7101 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
7102 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7107 /* i.reg_operands MUST be the number of real register operands;
7108 implicit registers do not count. If there are 3 register
7109 operands, it must be a instruction with VexNDS. For a
7110 instruction with VexNDD, the destination register is encoded
7111 in VEX prefix. If there are 4 register operands, it must be
7112 a instruction with VEX prefix and 3 sources. */
7113 if (i
.mem_operands
== 0
7114 && ((i
.reg_operands
== 2
7115 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7116 || (i
.reg_operands
== 3
7117 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7118 || (i
.reg_operands
== 4 && vex_3_sources
)))
7126 /* When there are 3 operands, one of them may be immediate,
7127 which may be the first or the last operand. Otherwise,
7128 the first operand must be shift count register (cl) or it
7129 is an instruction with VexNDS. */
7130 gas_assert (i
.imm_operands
== 1
7131 || (i
.imm_operands
== 0
7132 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7133 || i
.types
[0].bitfield
.shiftcount
)));
7134 if (operand_type_check (i
.types
[0], imm
)
7135 || i
.types
[0].bitfield
.shiftcount
)
7141 /* When there are 4 operands, the first two must be 8bit
7142 immediate operands. The source operand will be the 3rd
7145 For instructions with VexNDS, if the first operand
7146 an imm8, the source operand is the 2nd one. If the last
7147 operand is imm8, the source operand is the first one. */
7148 gas_assert ((i
.imm_operands
== 2
7149 && i
.types
[0].bitfield
.imm8
7150 && i
.types
[1].bitfield
.imm8
)
7151 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7152 && i
.imm_operands
== 1
7153 && (i
.types
[0].bitfield
.imm8
7154 || i
.types
[i
.operands
- 1].bitfield
.imm8
7156 if (i
.imm_operands
== 2)
7160 if (i
.types
[0].bitfield
.imm8
)
7167 if (is_evex_encoding (&i
.tm
))
7169 /* For EVEX instructions, when there are 5 operands, the
7170 first one must be immediate operand. If the second one
7171 is immediate operand, the source operand is the 3th
7172 one. If the last one is immediate operand, the source
7173 operand is the 2nd one. */
7174 gas_assert (i
.imm_operands
== 2
7175 && i
.tm
.opcode_modifier
.sae
7176 && operand_type_check (i
.types
[0], imm
));
7177 if (operand_type_check (i
.types
[1], imm
))
7179 else if (operand_type_check (i
.types
[4], imm
))
7193 /* RC/SAE operand could be between DEST and SRC. That happens
7194 when one operand is GPR and the other one is XMM/YMM/ZMM
7196 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7199 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7201 /* For instructions with VexNDS, the register-only source
7202 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7203 register. It is encoded in VEX prefix. We need to
7204 clear RegMem bit before calling operand_type_equal. */
7206 i386_operand_type op
;
7209 /* Check register-only source operand when two source
7210 operands are swapped. */
7211 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7212 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7220 op
= i
.tm
.operand_types
[vvvv
];
7221 op
.bitfield
.regmem
= 0;
7222 if ((dest
+ 1) >= i
.operands
7223 || ((!op
.bitfield
.reg
7224 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7225 && !op
.bitfield
.regsimd
7226 && !operand_type_equal (&op
, ®mask
)))
7228 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7234 /* One of the register operands will be encoded in the i.tm.reg
7235 field, the other in the combined i.tm.mode and i.tm.regmem
7236 fields. If no form of this instruction supports a memory
7237 destination operand, then we assume the source operand may
7238 sometimes be a memory operand and so we need to store the
7239 destination in the i.rm.reg field. */
7240 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
7241 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7243 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7244 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7245 if (i
.op
[dest
].regs
->reg_type
.bitfield
.regmmx
7246 || i
.op
[source
].regs
->reg_type
.bitfield
.regmmx
)
7247 i
.has_regmmx
= TRUE
;
7248 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.regsimd
7249 || i
.op
[source
].regs
->reg_type
.bitfield
.regsimd
)
7251 if (i
.types
[dest
].bitfield
.zmmword
7252 || i
.types
[source
].bitfield
.zmmword
)
7253 i
.has_regzmm
= TRUE
;
7254 else if (i
.types
[dest
].bitfield
.ymmword
7255 || i
.types
[source
].bitfield
.ymmword
)
7256 i
.has_regymm
= TRUE
;
7258 i
.has_regxmm
= TRUE
;
7260 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7262 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7264 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7266 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7271 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7272 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7273 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7275 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7277 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7279 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7282 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7284 if (!i
.types
[i
.tm
.operand_types
[0].bitfield
.regmem
].bitfield
.control
)
7287 add_prefix (LOCK_PREFIX_OPCODE
);
7291 { /* If it's not 2 reg operands... */
7296 unsigned int fake_zero_displacement
= 0;
7299 for (op
= 0; op
< i
.operands
; op
++)
7300 if (operand_type_check (i
.types
[op
], anymem
))
7302 gas_assert (op
< i
.operands
);
7304 if (i
.tm
.opcode_modifier
.vecsib
)
7306 if (i
.index_reg
->reg_num
== RegIZ
)
7309 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7312 i
.sib
.base
= NO_BASE_REGISTER
;
7313 i
.sib
.scale
= i
.log2_scale_factor
;
7314 i
.types
[op
].bitfield
.disp8
= 0;
7315 i
.types
[op
].bitfield
.disp16
= 0;
7316 i
.types
[op
].bitfield
.disp64
= 0;
7317 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7319 /* Must be 32 bit */
7320 i
.types
[op
].bitfield
.disp32
= 1;
7321 i
.types
[op
].bitfield
.disp32s
= 0;
7325 i
.types
[op
].bitfield
.disp32
= 0;
7326 i
.types
[op
].bitfield
.disp32s
= 1;
7329 i
.sib
.index
= i
.index_reg
->reg_num
;
7330 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7332 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7338 if (i
.base_reg
== 0)
7341 if (!i
.disp_operands
)
7342 fake_zero_displacement
= 1;
7343 if (i
.index_reg
== 0)
7345 i386_operand_type newdisp
;
7347 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7348 /* Operand is just <disp> */
7349 if (flag_code
== CODE_64BIT
)
7351 /* 64bit mode overwrites the 32bit absolute
7352 addressing by RIP relative addressing and
7353 absolute addressing is encoded by one of the
7354 redundant SIB forms. */
7355 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7356 i
.sib
.base
= NO_BASE_REGISTER
;
7357 i
.sib
.index
= NO_INDEX_REGISTER
;
7358 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7360 else if ((flag_code
== CODE_16BIT
)
7361 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7363 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7368 i
.rm
.regmem
= NO_BASE_REGISTER
;
7371 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7372 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7374 else if (!i
.tm
.opcode_modifier
.vecsib
)
7376 /* !i.base_reg && i.index_reg */
7377 if (i
.index_reg
->reg_num
== RegIZ
)
7378 i
.sib
.index
= NO_INDEX_REGISTER
;
7380 i
.sib
.index
= i
.index_reg
->reg_num
;
7381 i
.sib
.base
= NO_BASE_REGISTER
;
7382 i
.sib
.scale
= i
.log2_scale_factor
;
7383 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7384 i
.types
[op
].bitfield
.disp8
= 0;
7385 i
.types
[op
].bitfield
.disp16
= 0;
7386 i
.types
[op
].bitfield
.disp64
= 0;
7387 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7389 /* Must be 32 bit */
7390 i
.types
[op
].bitfield
.disp32
= 1;
7391 i
.types
[op
].bitfield
.disp32s
= 0;
7395 i
.types
[op
].bitfield
.disp32
= 0;
7396 i
.types
[op
].bitfield
.disp32s
= 1;
7398 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7402 /* RIP addressing for 64bit mode. */
7403 else if (i
.base_reg
->reg_num
== RegIP
)
7405 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7406 i
.rm
.regmem
= NO_BASE_REGISTER
;
7407 i
.types
[op
].bitfield
.disp8
= 0;
7408 i
.types
[op
].bitfield
.disp16
= 0;
7409 i
.types
[op
].bitfield
.disp32
= 0;
7410 i
.types
[op
].bitfield
.disp32s
= 1;
7411 i
.types
[op
].bitfield
.disp64
= 0;
7412 i
.flags
[op
] |= Operand_PCrel
;
7413 if (! i
.disp_operands
)
7414 fake_zero_displacement
= 1;
7416 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7418 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7419 switch (i
.base_reg
->reg_num
)
7422 if (i
.index_reg
== 0)
7424 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7425 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7429 if (i
.index_reg
== 0)
7432 if (operand_type_check (i
.types
[op
], disp
) == 0)
7434 /* fake (%bp) into 0(%bp) */
7435 i
.types
[op
].bitfield
.disp8
= 1;
7436 fake_zero_displacement
= 1;
7439 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7440 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7442 default: /* (%si) -> 4 or (%di) -> 5 */
7443 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7445 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7447 else /* i.base_reg and 32/64 bit mode */
7449 if (flag_code
== CODE_64BIT
7450 && operand_type_check (i
.types
[op
], disp
))
7452 i
.types
[op
].bitfield
.disp16
= 0;
7453 i
.types
[op
].bitfield
.disp64
= 0;
7454 if (i
.prefix
[ADDR_PREFIX
] == 0)
7456 i
.types
[op
].bitfield
.disp32
= 0;
7457 i
.types
[op
].bitfield
.disp32s
= 1;
7461 i
.types
[op
].bitfield
.disp32
= 1;
7462 i
.types
[op
].bitfield
.disp32s
= 0;
7466 if (!i
.tm
.opcode_modifier
.vecsib
)
7467 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7468 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7470 i
.sib
.base
= i
.base_reg
->reg_num
;
7471 /* x86-64 ignores REX prefix bit here to avoid decoder
7473 if (!(i
.base_reg
->reg_flags
& RegRex
)
7474 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7475 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7477 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7479 fake_zero_displacement
= 1;
7480 i
.types
[op
].bitfield
.disp8
= 1;
7482 i
.sib
.scale
= i
.log2_scale_factor
;
7483 if (i
.index_reg
== 0)
7485 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7486 /* <disp>(%esp) becomes two byte modrm with no index
7487 register. We've already stored the code for esp
7488 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7489 Any base register besides %esp will not use the
7490 extra modrm byte. */
7491 i
.sib
.index
= NO_INDEX_REGISTER
;
7493 else if (!i
.tm
.opcode_modifier
.vecsib
)
7495 if (i
.index_reg
->reg_num
== RegIZ
)
7496 i
.sib
.index
= NO_INDEX_REGISTER
;
7498 i
.sib
.index
= i
.index_reg
->reg_num
;
7499 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7500 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7505 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7506 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7510 if (!fake_zero_displacement
7514 fake_zero_displacement
= 1;
7515 if (i
.disp_encoding
== disp_encoding_8bit
)
7516 i
.types
[op
].bitfield
.disp8
= 1;
7518 i
.types
[op
].bitfield
.disp32
= 1;
7520 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7524 if (fake_zero_displacement
)
7526 /* Fakes a zero displacement assuming that i.types[op]
7527 holds the correct displacement size. */
7530 gas_assert (i
.op
[op
].disps
== 0);
7531 exp
= &disp_expressions
[i
.disp_operands
++];
7532 i
.op
[op
].disps
= exp
;
7533 exp
->X_op
= O_constant
;
7534 exp
->X_add_number
= 0;
7535 exp
->X_add_symbol
= (symbolS
*) 0;
7536 exp
->X_op_symbol
= (symbolS
*) 0;
7544 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7546 if (operand_type_check (i
.types
[0], imm
))
7547 i
.vex
.register_specifier
= NULL
;
7550 /* VEX.vvvv encodes one of the sources when the first
7551 operand is not an immediate. */
7552 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7553 i
.vex
.register_specifier
= i
.op
[0].regs
;
7555 i
.vex
.register_specifier
= i
.op
[1].regs
;
7558 /* Destination is a XMM register encoded in the ModRM.reg
7560 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7561 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7564 /* ModRM.rm and VEX.B encodes the other source. */
7565 if (!i
.mem_operands
)
7569 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7570 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7572 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7574 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7578 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7580 i
.vex
.register_specifier
= i
.op
[2].regs
;
7581 if (!i
.mem_operands
)
7584 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7585 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7589 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7590 (if any) based on i.tm.extension_opcode. Again, we must be
7591 careful to make sure that segment/control/debug/test/MMX
7592 registers are coded into the i.rm.reg field. */
7593 else if (i
.reg_operands
)
7596 unsigned int vex_reg
= ~0;
7598 for (op
= 0; op
< i
.operands
; op
++)
7600 if (i
.types
[op
].bitfield
.reg
7601 || i
.types
[op
].bitfield
.regbnd
7602 || i
.types
[op
].bitfield
.regmask
7603 || i
.types
[op
].bitfield
.sreg2
7604 || i
.types
[op
].bitfield
.sreg3
7605 || i
.types
[op
].bitfield
.control
7606 || i
.types
[op
].bitfield
.debug
7607 || i
.types
[op
].bitfield
.test
)
7609 if (i
.types
[op
].bitfield
.regsimd
)
7611 if (i
.types
[op
].bitfield
.zmmword
)
7612 i
.has_regzmm
= TRUE
;
7613 else if (i
.types
[op
].bitfield
.ymmword
)
7614 i
.has_regymm
= TRUE
;
7616 i
.has_regxmm
= TRUE
;
7619 if (i
.types
[op
].bitfield
.regmmx
)
7621 i
.has_regmmx
= TRUE
;
7628 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7630 /* For instructions with VexNDS, the register-only
7631 source operand is encoded in VEX prefix. */
7632 gas_assert (mem
!= (unsigned int) ~0);
7637 gas_assert (op
< i
.operands
);
7641 /* Check register-only source operand when two source
7642 operands are swapped. */
7643 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7644 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7648 gas_assert (mem
== (vex_reg
+ 1)
7649 && op
< i
.operands
);
7654 gas_assert (vex_reg
< i
.operands
);
7658 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7660 /* For instructions with VexNDD, the register destination
7661 is encoded in VEX prefix. */
7662 if (i
.mem_operands
== 0)
7664 /* There is no memory operand. */
7665 gas_assert ((op
+ 2) == i
.operands
);
7670 /* There are only 2 non-immediate operands. */
7671 gas_assert (op
< i
.imm_operands
+ 2
7672 && i
.operands
== i
.imm_operands
+ 2);
7673 vex_reg
= i
.imm_operands
+ 1;
7677 gas_assert (op
< i
.operands
);
7679 if (vex_reg
!= (unsigned int) ~0)
7681 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7683 if ((!type
->bitfield
.reg
7684 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7685 && !type
->bitfield
.regsimd
7686 && !operand_type_equal (type
, ®mask
))
7689 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7692 /* Don't set OP operand twice. */
7695 /* If there is an extension opcode to put here, the
7696 register number must be put into the regmem field. */
7697 if (i
.tm
.extension_opcode
!= None
)
7699 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7700 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7702 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7707 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7708 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7710 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7715 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7716 must set it to 3 to indicate this is a register operand
7717 in the regmem field. */
7718 if (!i
.mem_operands
)
7722 /* Fill in i.rm.reg field with extension opcode (if any). */
7723 if (i
.tm
.extension_opcode
!= None
)
7724 i
.rm
.reg
= i
.tm
.extension_opcode
;
7730 output_branch (void)
7736 relax_substateT subtype
;
7740 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7741 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7744 if (i
.prefix
[DATA_PREFIX
] != 0)
7750 /* Pentium4 branch hints. */
7751 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7752 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7757 if (i
.prefix
[REX_PREFIX
] != 0)
7763 /* BND prefixed jump. */
7764 if (i
.prefix
[BND_PREFIX
] != 0)
7766 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7770 if (i
.prefixes
!= 0 && !intel_syntax
)
7771 as_warn (_("skipping prefixes on this instruction"));
7773 /* It's always a symbol; End frag & setup for relax.
7774 Make sure there is enough room in this frag for the largest
7775 instruction we may generate in md_convert_frag. This is 2
7776 bytes for the opcode and room for the prefix and largest
7778 frag_grow (prefix
+ 2 + 4);
7779 /* Prefix and 1 opcode byte go in fr_fix. */
7780 p
= frag_more (prefix
+ 1);
7781 if (i
.prefix
[DATA_PREFIX
] != 0)
7782 *p
++ = DATA_PREFIX_OPCODE
;
7783 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7784 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7785 *p
++ = i
.prefix
[SEG_PREFIX
];
7786 if (i
.prefix
[REX_PREFIX
] != 0)
7787 *p
++ = i
.prefix
[REX_PREFIX
];
7788 *p
= i
.tm
.base_opcode
;
7790 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7791 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7792 else if (cpu_arch_flags
.bitfield
.cpui386
)
7793 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7795 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7798 sym
= i
.op
[0].disps
->X_add_symbol
;
7799 off
= i
.op
[0].disps
->X_add_number
;
7801 if (i
.op
[0].disps
->X_op
!= O_constant
7802 && i
.op
[0].disps
->X_op
!= O_symbol
)
7804 /* Handle complex expressions. */
7805 sym
= make_expr_symbol (i
.op
[0].disps
);
7809 /* 1 possible extra opcode + 4 byte displacement go in var part.
7810 Pass reloc in fr_var. */
7811 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7814 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7815 /* Return TRUE iff PLT32 relocation should be used for branching to
7819 need_plt32_p (symbolS
*s
)
7821 /* PLT32 relocation is ELF only. */
7826 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
7827 krtld support it. */
7831 /* Since there is no need to prepare for PLT branch on x86-64, we
7832 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7833 be used as a marker for 32-bit PC-relative branches. */
7837 /* Weak or undefined symbol need PLT32 relocation. */
7838 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7841 /* Non-global symbol doesn't need PLT32 relocation. */
7842 if (! S_IS_EXTERNAL (s
))
7845 /* Other global symbols need PLT32 relocation. NB: Symbol with
7846 non-default visibilities are treated as normal global symbol
7847 so that PLT32 relocation can be used as a marker for 32-bit
7848 PC-relative branches. It is useful for linker relaxation. */
7859 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7861 if (i
.tm
.opcode_modifier
.jumpbyte
)
7863 /* This is a loop or jecxz type instruction. */
7865 if (i
.prefix
[ADDR_PREFIX
] != 0)
7867 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7870 /* Pentium4 branch hints. */
7871 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7872 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7874 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7883 if (flag_code
== CODE_16BIT
)
7886 if (i
.prefix
[DATA_PREFIX
] != 0)
7888 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7898 if (i
.prefix
[REX_PREFIX
] != 0)
7900 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7904 /* BND prefixed jump. */
7905 if (i
.prefix
[BND_PREFIX
] != 0)
7907 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7911 if (i
.prefixes
!= 0 && !intel_syntax
)
7912 as_warn (_("skipping prefixes on this instruction"));
7914 p
= frag_more (i
.tm
.opcode_length
+ size
);
7915 switch (i
.tm
.opcode_length
)
7918 *p
++ = i
.tm
.base_opcode
>> 8;
7921 *p
++ = i
.tm
.base_opcode
;
7927 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7929 && jump_reloc
== NO_RELOC
7930 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7931 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7934 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7936 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7937 i
.op
[0].disps
, 1, jump_reloc
);
7939 /* All jumps handled here are signed, but don't use a signed limit
7940 check for 32 and 16 bit jumps as we want to allow wrap around at
7941 4G and 64k respectively. */
7943 fixP
->fx_signed
= 1;
7947 output_interseg_jump (void)
7955 if (flag_code
== CODE_16BIT
)
7959 if (i
.prefix
[DATA_PREFIX
] != 0)
7965 if (i
.prefix
[REX_PREFIX
] != 0)
7975 if (i
.prefixes
!= 0 && !intel_syntax
)
7976 as_warn (_("skipping prefixes on this instruction"));
7978 /* 1 opcode; 2 segment; offset */
7979 p
= frag_more (prefix
+ 1 + 2 + size
);
7981 if (i
.prefix
[DATA_PREFIX
] != 0)
7982 *p
++ = DATA_PREFIX_OPCODE
;
7984 if (i
.prefix
[REX_PREFIX
] != 0)
7985 *p
++ = i
.prefix
[REX_PREFIX
];
7987 *p
++ = i
.tm
.base_opcode
;
7988 if (i
.op
[1].imms
->X_op
== O_constant
)
7990 offsetT n
= i
.op
[1].imms
->X_add_number
;
7993 && !fits_in_unsigned_word (n
)
7994 && !fits_in_signed_word (n
))
7996 as_bad (_("16-bit jump out of range"));
7999 md_number_to_chars (p
, n
, size
);
8002 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8003 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8004 if (i
.op
[0].imms
->X_op
!= O_constant
)
8005 as_bad (_("can't handle non absolute segment in `%s'"),
8007 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8010 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8015 asection
*seg
= now_seg
;
8016 subsegT subseg
= now_subseg
;
8018 unsigned int alignment
, align_size_1
;
8019 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8020 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8021 unsigned int padding
;
8023 if (!IS_ELF
|| !x86_used_note
)
8026 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8028 /* The .note.gnu.property section layout:
8030 Field Length Contents
8033 n_descsz 4 The note descriptor size
8034 n_type 4 NT_GNU_PROPERTY_TYPE_0
8036 n_desc n_descsz The program property array
8040 /* Create the .note.gnu.property section. */
8041 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8042 bfd_set_section_flags (stdoutput
, sec
,
8049 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8060 bfd_set_section_alignment (stdoutput
, sec
, alignment
);
8061 elf_section_type (sec
) = SHT_NOTE
;
8063 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8065 isa_1_descsz_raw
= 4 + 4 + 4;
8066 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8067 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8069 feature_2_descsz_raw
= isa_1_descsz
;
8070 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8072 feature_2_descsz_raw
+= 4 + 4 + 4;
8073 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8074 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8077 descsz
= feature_2_descsz
;
8078 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8079 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8081 /* Write n_namsz. */
8082 md_number_to_chars (p
, (valueT
) 4, 4);
8084 /* Write n_descsz. */
8085 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8088 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8091 memcpy (p
+ 4 * 3, "GNU", 4);
8093 /* Write 4-byte type. */
8094 md_number_to_chars (p
+ 4 * 4,
8095 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8097 /* Write 4-byte data size. */
8098 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8100 /* Write 4-byte data. */
8101 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8103 /* Zero out paddings. */
8104 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8106 memset (p
+ 4 * 7, 0, padding
);
8108 /* Write 4-byte type. */
8109 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8110 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8112 /* Write 4-byte data size. */
8113 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8115 /* Write 4-byte data. */
8116 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8117 (valueT
) x86_feature_2_used
, 4);
8119 /* Zero out paddings. */
8120 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8122 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8124 /* We probably can't restore the current segment, for there likely
8127 subseg_set (seg
, subseg
);
8132 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8133 const char *frag_now_ptr
)
8135 unsigned int len
= 0;
8137 if (start_frag
!= frag_now
)
8139 const fragS
*fr
= start_frag
;
8144 } while (fr
&& fr
!= frag_now
);
8147 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8153 fragS
*insn_start_frag
;
8154 offsetT insn_start_off
;
8156 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8157 if (IS_ELF
&& x86_used_note
)
8159 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8160 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8161 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8162 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8163 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8164 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8165 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8166 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8167 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8168 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8169 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8170 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8171 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8172 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8173 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8174 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8175 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8176 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8177 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8178 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8179 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8180 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8181 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8182 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8183 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8184 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8185 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8186 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8187 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8188 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8189 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8190 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8191 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8192 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8193 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8194 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8195 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8196 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8197 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8198 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8199 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8200 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8201 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8202 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8203 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8204 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8205 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8206 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8207 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8208 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8210 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8211 || i
.tm
.cpu_flags
.bitfield
.cpu287
8212 || i
.tm
.cpu_flags
.bitfield
.cpu387
8213 || i
.tm
.cpu_flags
.bitfield
.cpu687
8214 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8215 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8216 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8217 Xfence instructions. */
8218 if (i
.tm
.base_opcode
!= 0xf18
8219 && i
.tm
.base_opcode
!= 0xf0d
8220 && i
.tm
.base_opcode
!= 0xfae
8222 || i
.tm
.cpu_flags
.bitfield
.cpummx
8223 || i
.tm
.cpu_flags
.bitfield
.cpua3dnow
8224 || i
.tm
.cpu_flags
.bitfield
.cpua3dnowa
))
8225 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8227 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8229 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8231 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8232 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8233 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8234 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8235 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8236 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8237 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8238 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8239 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8243 /* Tie dwarf2 debug info to the address at the start of the insn.
8244 We can't do this after the insn has been output as the current
8245 frag may have been closed off. eg. by frag_var. */
8246 dwarf2_emit_insn (0);
8248 insn_start_frag
= frag_now
;
8249 insn_start_off
= frag_now_fix ();
8252 if (i
.tm
.opcode_modifier
.jump
)
8254 else if (i
.tm
.opcode_modifier
.jumpbyte
8255 || i
.tm
.opcode_modifier
.jumpdword
)
8257 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
8258 output_interseg_jump ();
8261 /* Output normal instructions here. */
8265 unsigned int prefix
;
8268 && i
.tm
.base_opcode
== 0xfae
8270 && i
.imm_operands
== 1
8271 && (i
.op
[0].imms
->X_add_number
== 0xe8
8272 || i
.op
[0].imms
->X_add_number
== 0xf0
8273 || i
.op
[0].imms
->X_add_number
== 0xf8))
8275 /* Encode lfence, mfence, and sfence as
8276 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8277 offsetT val
= 0x240483f0ULL
;
8279 md_number_to_chars (p
, val
, 5);
8283 /* Some processors fail on LOCK prefix. This options makes
8284 assembler ignore LOCK prefix and serves as a workaround. */
8285 if (omit_lock_prefix
)
8287 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8289 i
.prefix
[LOCK_PREFIX
] = 0;
8292 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8293 don't need the explicit prefix. */
8294 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8296 switch (i
.tm
.opcode_length
)
8299 if (i
.tm
.base_opcode
& 0xff000000)
8301 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8302 add_prefix (prefix
);
8306 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8308 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8309 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8310 || prefix
!= REPE_PREFIX_OPCODE
8311 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8312 add_prefix (prefix
);
8318 /* Check for pseudo prefixes. */
8319 as_bad_where (insn_start_frag
->fr_file
,
8320 insn_start_frag
->fr_line
,
8321 _("pseudo prefix without instruction"));
8327 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8328 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8329 R_X86_64_GOTTPOFF relocation so that linker can safely
8330 perform IE->LE optimization. */
8331 if (x86_elf_abi
== X86_64_X32_ABI
8333 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8334 && i
.prefix
[REX_PREFIX
] == 0)
8335 add_prefix (REX_OPCODE
);
8338 /* The prefix bytes. */
8339 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8341 FRAG_APPEND_1_CHAR (*q
);
8345 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8350 /* REX byte is encoded in VEX prefix. */
8354 FRAG_APPEND_1_CHAR (*q
);
8357 /* There should be no other prefixes for instructions
8362 /* For EVEX instructions i.vrex should become 0 after
8363 build_evex_prefix. For VEX instructions upper 16 registers
8364 aren't available, so VREX should be 0. */
8367 /* Now the VEX prefix. */
8368 p
= frag_more (i
.vex
.length
);
8369 for (j
= 0; j
< i
.vex
.length
; j
++)
8370 p
[j
] = i
.vex
.bytes
[j
];
8373 /* Now the opcode; be careful about word order here! */
8374 if (i
.tm
.opcode_length
== 1)
8376 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8380 switch (i
.tm
.opcode_length
)
8384 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8385 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8389 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8399 /* Put out high byte first: can't use md_number_to_chars! */
8400 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8401 *p
= i
.tm
.base_opcode
& 0xff;
8404 /* Now the modrm byte and sib byte (if present). */
8405 if (i
.tm
.opcode_modifier
.modrm
)
8407 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8410 /* If i.rm.regmem == ESP (4)
8411 && i.rm.mode != (Register mode)
8413 ==> need second modrm byte. */
8414 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8416 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8417 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8419 | i
.sib
.scale
<< 6));
8422 if (i
.disp_operands
)
8423 output_disp (insn_start_frag
, insn_start_off
);
8426 output_imm (insn_start_frag
, insn_start_off
);
8429 * frag_now_fix () returning plain abs_section_offset when we're in the
8430 * absolute section, and abs_section_offset not getting updated as data
8431 * gets added to the frag breaks the logic below.
8433 if (now_seg
!= absolute_section
)
8435 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
8437 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
8445 pi ("" /*line*/, &i
);
8447 #endif /* DEBUG386 */
8450 /* Return the size of the displacement operand N. */
8453 disp_size (unsigned int n
)
8457 if (i
.types
[n
].bitfield
.disp64
)
8459 else if (i
.types
[n
].bitfield
.disp8
)
8461 else if (i
.types
[n
].bitfield
.disp16
)
8466 /* Return the size of the immediate operand N. */
8469 imm_size (unsigned int n
)
8472 if (i
.types
[n
].bitfield
.imm64
)
8474 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8476 else if (i
.types
[n
].bitfield
.imm16
)
8482 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8487 for (n
= 0; n
< i
.operands
; n
++)
8489 if (operand_type_check (i
.types
[n
], disp
))
8491 if (i
.op
[n
].disps
->X_op
== O_constant
)
8493 int size
= disp_size (n
);
8494 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8496 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8498 p
= frag_more (size
);
8499 md_number_to_chars (p
, val
, size
);
8503 enum bfd_reloc_code_real reloc_type
;
8504 int size
= disp_size (n
);
8505 int sign
= i
.types
[n
].bitfield
.disp32s
;
8506 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8509 /* We can't have 8 bit displacement here. */
8510 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8512 /* The PC relative address is computed relative
8513 to the instruction boundary, so in case immediate
8514 fields follows, we need to adjust the value. */
8515 if (pcrel
&& i
.imm_operands
)
8520 for (n1
= 0; n1
< i
.operands
; n1
++)
8521 if (operand_type_check (i
.types
[n1
], imm
))
8523 /* Only one immediate is allowed for PC
8524 relative address. */
8525 gas_assert (sz
== 0);
8527 i
.op
[n
].disps
->X_add_number
-= sz
;
8529 /* We should find the immediate. */
8530 gas_assert (sz
!= 0);
8533 p
= frag_more (size
);
8534 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8536 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8537 && (((reloc_type
== BFD_RELOC_32
8538 || reloc_type
== BFD_RELOC_X86_64_32S
8539 || (reloc_type
== BFD_RELOC_64
8541 && (i
.op
[n
].disps
->X_op
== O_symbol
8542 || (i
.op
[n
].disps
->X_op
== O_add
8543 && ((symbol_get_value_expression
8544 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8546 || reloc_type
== BFD_RELOC_32_PCREL
))
8550 reloc_type
= BFD_RELOC_386_GOTPC
;
8551 i
.op
[n
].imms
->X_add_number
+=
8552 encoding_length (insn_start_frag
, insn_start_off
, p
);
8554 else if (reloc_type
== BFD_RELOC_64
)
8555 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8557 /* Don't do the adjustment for x86-64, as there
8558 the pcrel addressing is relative to the _next_
8559 insn, and that is taken care of in other code. */
8560 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8562 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8563 size
, i
.op
[n
].disps
, pcrel
,
8565 /* Check for "call/jmp *mem", "mov mem, %reg",
8566 "test %reg, mem" and "binop mem, %reg" where binop
8567 is one of adc, add, and, cmp, or, sbb, sub, xor
8568 instructions without data prefix. Always generate
8569 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
8570 if (i
.prefix
[DATA_PREFIX
] == 0
8571 && (generate_relax_relocations
8574 && i
.rm
.regmem
== 5))
8576 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8577 && ((i
.operands
== 1
8578 && i
.tm
.base_opcode
== 0xff
8579 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8581 && (i
.tm
.base_opcode
== 0x8b
8582 || i
.tm
.base_opcode
== 0x85
8583 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8587 fixP
->fx_tcbit
= i
.rex
!= 0;
8589 && (i
.base_reg
->reg_num
== RegIP
))
8590 fixP
->fx_tcbit2
= 1;
8593 fixP
->fx_tcbit2
= 1;
8601 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8606 for (n
= 0; n
< i
.operands
; n
++)
8608 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8609 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8612 if (operand_type_check (i
.types
[n
], imm
))
8614 if (i
.op
[n
].imms
->X_op
== O_constant
)
8616 int size
= imm_size (n
);
8619 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8621 p
= frag_more (size
);
8622 md_number_to_chars (p
, val
, size
);
8626 /* Not absolute_section.
8627 Need a 32-bit fixup (don't support 8bit
8628 non-absolute imms). Try to support other
8630 enum bfd_reloc_code_real reloc_type
;
8631 int size
= imm_size (n
);
8634 if (i
.types
[n
].bitfield
.imm32s
8635 && (i
.suffix
== QWORD_MNEM_SUFFIX
8636 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8641 p
= frag_more (size
);
8642 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8644 /* This is tough to explain. We end up with this one if we
8645 * have operands that look like
8646 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8647 * obtain the absolute address of the GOT, and it is strongly
8648 * preferable from a performance point of view to avoid using
8649 * a runtime relocation for this. The actual sequence of
8650 * instructions often look something like:
8655 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8657 * The call and pop essentially return the absolute address
8658 * of the label .L66 and store it in %ebx. The linker itself
8659 * will ultimately change the first operand of the addl so
8660 * that %ebx points to the GOT, but to keep things simple, the
8661 * .o file must have this operand set so that it generates not
8662 * the absolute address of .L66, but the absolute address of
8663 * itself. This allows the linker itself simply treat a GOTPC
8664 * relocation as asking for a pcrel offset to the GOT to be
8665 * added in, and the addend of the relocation is stored in the
8666 * operand field for the instruction itself.
8668 * Our job here is to fix the operand so that it would add
8669 * the correct offset so that %ebx would point to itself. The
8670 * thing that is tricky is that .-.L66 will point to the
8671 * beginning of the instruction, so we need to further modify
8672 * the operand so that it will point to itself. There are
8673 * other cases where you have something like:
8675 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8677 * and here no correction would be required. Internally in
8678 * the assembler we treat operands of this form as not being
8679 * pcrel since the '.' is explicitly mentioned, and I wonder
8680 * whether it would simplify matters to do it this way. Who
8681 * knows. In earlier versions of the PIC patches, the
8682 * pcrel_adjust field was used to store the correction, but
8683 * since the expression is not pcrel, I felt it would be
8684 * confusing to do it this way. */
8686 if ((reloc_type
== BFD_RELOC_32
8687 || reloc_type
== BFD_RELOC_X86_64_32S
8688 || reloc_type
== BFD_RELOC_64
)
8690 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8691 && (i
.op
[n
].imms
->X_op
== O_symbol
8692 || (i
.op
[n
].imms
->X_op
== O_add
8693 && ((symbol_get_value_expression
8694 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8698 reloc_type
= BFD_RELOC_386_GOTPC
;
8700 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8702 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8703 i
.op
[n
].imms
->X_add_number
+=
8704 encoding_length (insn_start_frag
, insn_start_off
, p
);
8706 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8707 i
.op
[n
].imms
, 0, reloc_type
);
8713 /* x86_cons_fix_new is called via the expression parsing code when a
8714 reloc is needed. We use this hook to get the correct .got reloc. */
8715 static int cons_sign
= -1;
8718 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8719 expressionS
*exp
, bfd_reloc_code_real_type r
)
8721 r
= reloc (len
, 0, cons_sign
, r
);
8724 if (exp
->X_op
== O_secrel
)
8726 exp
->X_op
= O_symbol
;
8727 r
= BFD_RELOC_32_SECREL
;
8731 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8734 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8735 purpose of the `.dc.a' internal pseudo-op. */
8738 x86_address_bytes (void)
8740 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8742 return stdoutput
->arch_info
->bits_per_address
/ 8;
8745 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8747 # define lex_got(reloc, adjust, types) NULL
8749 /* Parse operands of the form
8750 <symbol>@GOTOFF+<nnn>
8751 and similar .plt or .got references.
8753 If we find one, set up the correct relocation in RELOC and copy the
8754 input string, minus the `@GOTOFF' into a malloc'd buffer for
8755 parsing by the calling routine. Return this buffer, and if ADJUST
8756 is non-null set it to the length of the string we removed from the
8757 input line. Otherwise return NULL. */
8759 lex_got (enum bfd_reloc_code_real
*rel
,
8761 i386_operand_type
*types
)
8763 /* Some of the relocations depend on the size of what field is to
8764 be relocated. But in our callers i386_immediate and i386_displacement
8765 we don't yet know the operand size (this will be set by insn
8766 matching). Hence we record the word32 relocation here,
8767 and adjust the reloc according to the real size in reloc(). */
8768 static const struct {
8771 const enum bfd_reloc_code_real rel
[2];
8772 const i386_operand_type types64
;
8774 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8775 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8777 OPERAND_TYPE_IMM32_64
},
8779 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8780 BFD_RELOC_X86_64_PLTOFF64
},
8781 OPERAND_TYPE_IMM64
},
8782 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8783 BFD_RELOC_X86_64_PLT32
},
8784 OPERAND_TYPE_IMM32_32S_DISP32
},
8785 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8786 BFD_RELOC_X86_64_GOTPLT64
},
8787 OPERAND_TYPE_IMM64_DISP64
},
8788 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8789 BFD_RELOC_X86_64_GOTOFF64
},
8790 OPERAND_TYPE_IMM64_DISP64
},
8791 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8792 BFD_RELOC_X86_64_GOTPCREL
},
8793 OPERAND_TYPE_IMM32_32S_DISP32
},
8794 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8795 BFD_RELOC_X86_64_TLSGD
},
8796 OPERAND_TYPE_IMM32_32S_DISP32
},
8797 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8798 _dummy_first_bfd_reloc_code_real
},
8799 OPERAND_TYPE_NONE
},
8800 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8801 BFD_RELOC_X86_64_TLSLD
},
8802 OPERAND_TYPE_IMM32_32S_DISP32
},
8803 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8804 BFD_RELOC_X86_64_GOTTPOFF
},
8805 OPERAND_TYPE_IMM32_32S_DISP32
},
8806 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8807 BFD_RELOC_X86_64_TPOFF32
},
8808 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8809 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8810 _dummy_first_bfd_reloc_code_real
},
8811 OPERAND_TYPE_NONE
},
8812 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8813 BFD_RELOC_X86_64_DTPOFF32
},
8814 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8815 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8816 _dummy_first_bfd_reloc_code_real
},
8817 OPERAND_TYPE_NONE
},
8818 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8819 _dummy_first_bfd_reloc_code_real
},
8820 OPERAND_TYPE_NONE
},
8821 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8822 BFD_RELOC_X86_64_GOT32
},
8823 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8824 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8825 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8826 OPERAND_TYPE_IMM32_32S_DISP32
},
8827 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8828 BFD_RELOC_X86_64_TLSDESC_CALL
},
8829 OPERAND_TYPE_IMM32_32S_DISP32
},
8834 #if defined (OBJ_MAYBE_ELF)
8839 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8840 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8843 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8845 int len
= gotrel
[j
].len
;
8846 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8848 if (gotrel
[j
].rel
[object_64bit
] != 0)
8851 char *tmpbuf
, *past_reloc
;
8853 *rel
= gotrel
[j
].rel
[object_64bit
];
8857 if (flag_code
!= CODE_64BIT
)
8859 types
->bitfield
.imm32
= 1;
8860 types
->bitfield
.disp32
= 1;
8863 *types
= gotrel
[j
].types64
;
8866 if (j
!= 0 && GOT_symbol
== NULL
)
8867 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8869 /* The length of the first part of our input line. */
8870 first
= cp
- input_line_pointer
;
8872 /* The second part goes from after the reloc token until
8873 (and including) an end_of_line char or comma. */
8874 past_reloc
= cp
+ 1 + len
;
8876 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8878 second
= cp
+ 1 - past_reloc
;
8880 /* Allocate and copy string. The trailing NUL shouldn't
8881 be necessary, but be safe. */
8882 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8883 memcpy (tmpbuf
, input_line_pointer
, first
);
8884 if (second
!= 0 && *past_reloc
!= ' ')
8885 /* Replace the relocation token with ' ', so that
8886 errors like foo@GOTOFF1 will be detected. */
8887 tmpbuf
[first
++] = ' ';
8889 /* Increment length by 1 if the relocation token is
8894 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8895 tmpbuf
[first
+ second
] = '\0';
8899 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8900 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8905 /* Might be a symbol version string. Don't as_bad here. */
8914 /* Parse operands of the form
8915 <symbol>@SECREL32+<nnn>
8917 If we find one, set up the correct relocation in RELOC and copy the
8918 input string, minus the `@SECREL32' into a malloc'd buffer for
8919 parsing by the calling routine. Return this buffer, and if ADJUST
8920 is non-null set it to the length of the string we removed from the
8921 input line. Otherwise return NULL.
8923 This function is copied from the ELF version above adjusted for PE targets. */
8926 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8927 int *adjust ATTRIBUTE_UNUSED
,
8928 i386_operand_type
*types
)
8934 const enum bfd_reloc_code_real rel
[2];
8935 const i386_operand_type types64
;
8939 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8940 BFD_RELOC_32_SECREL
},
8941 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8947 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8948 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8951 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8953 int len
= gotrel
[j
].len
;
8955 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8957 if (gotrel
[j
].rel
[object_64bit
] != 0)
8960 char *tmpbuf
, *past_reloc
;
8962 *rel
= gotrel
[j
].rel
[object_64bit
];
8968 if (flag_code
!= CODE_64BIT
)
8970 types
->bitfield
.imm32
= 1;
8971 types
->bitfield
.disp32
= 1;
8974 *types
= gotrel
[j
].types64
;
8977 /* The length of the first part of our input line. */
8978 first
= cp
- input_line_pointer
;
8980 /* The second part goes from after the reloc token until
8981 (and including) an end_of_line char or comma. */
8982 past_reloc
= cp
+ 1 + len
;
8984 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8986 second
= cp
+ 1 - past_reloc
;
8988 /* Allocate and copy string. The trailing NUL shouldn't
8989 be necessary, but be safe. */
8990 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8991 memcpy (tmpbuf
, input_line_pointer
, first
);
8992 if (second
!= 0 && *past_reloc
!= ' ')
8993 /* Replace the relocation token with ' ', so that
8994 errors like foo@SECLREL321 will be detected. */
8995 tmpbuf
[first
++] = ' ';
8996 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8997 tmpbuf
[first
+ second
] = '\0';
9001 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9002 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9007 /* Might be a symbol version string. Don't as_bad here. */
9013 bfd_reloc_code_real_type
9014 x86_cons (expressionS
*exp
, int size
)
9016 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9018 intel_syntax
= -intel_syntax
;
9021 if (size
== 4 || (object_64bit
&& size
== 8))
9023 /* Handle @GOTOFF and the like in an expression. */
9025 char *gotfree_input_line
;
9028 save
= input_line_pointer
;
9029 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
9030 if (gotfree_input_line
)
9031 input_line_pointer
= gotfree_input_line
;
9035 if (gotfree_input_line
)
9037 /* expression () has merrily parsed up to the end of line,
9038 or a comma - in the wrong buffer. Transfer how far
9039 input_line_pointer has moved to the right buffer. */
9040 input_line_pointer
= (save
9041 + (input_line_pointer
- gotfree_input_line
)
9043 free (gotfree_input_line
);
9044 if (exp
->X_op
== O_constant
9045 || exp
->X_op
== O_absent
9046 || exp
->X_op
== O_illegal
9047 || exp
->X_op
== O_register
9048 || exp
->X_op
== O_big
)
9050 char c
= *input_line_pointer
;
9051 *input_line_pointer
= 0;
9052 as_bad (_("missing or invalid expression `%s'"), save
);
9053 *input_line_pointer
= c
;
9055 else if ((got_reloc
== BFD_RELOC_386_PLT32
9056 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9057 && exp
->X_op
!= O_symbol
)
9059 char c
= *input_line_pointer
;
9060 *input_line_pointer
= 0;
9061 as_bad (_("invalid PLT expression `%s'"), save
);
9062 *input_line_pointer
= c
;
9069 intel_syntax
= -intel_syntax
;
9072 i386_intel_simplify (exp
);
9078 signed_cons (int size
)
9080 if (flag_code
== CODE_64BIT
)
9088 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9095 if (exp
.X_op
== O_symbol
)
9096 exp
.X_op
= O_secrel
;
9098 emit_expr (&exp
, 4);
9100 while (*input_line_pointer
++ == ',');
9102 input_line_pointer
--;
9103 demand_empty_rest_of_line ();
9107 /* Handle Vector operations. */
9110 check_VecOperations (char *op_string
, char *op_end
)
9112 const reg_entry
*mask
;
9117 && (op_end
== NULL
|| op_string
< op_end
))
9120 if (*op_string
== '{')
9124 /* Check broadcasts. */
9125 if (strncmp (op_string
, "1to", 3) == 0)
9130 goto duplicated_vec_op
;
9133 if (*op_string
== '8')
9135 else if (*op_string
== '4')
9137 else if (*op_string
== '2')
9139 else if (*op_string
== '1'
9140 && *(op_string
+1) == '6')
9147 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9152 broadcast_op
.type
= bcst_type
;
9153 broadcast_op
.operand
= this_operand
;
9154 broadcast_op
.bytes
= 0;
9155 i
.broadcast
= &broadcast_op
;
9157 /* Check masking operation. */
9158 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9160 /* k0 can't be used for write mask. */
9161 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
9163 as_bad (_("`%s%s' can't be used for write mask"),
9164 register_prefix
, mask
->reg_name
);
9170 mask_op
.mask
= mask
;
9171 mask_op
.zeroing
= 0;
9172 mask_op
.operand
= this_operand
;
9178 goto duplicated_vec_op
;
9180 i
.mask
->mask
= mask
;
9182 /* Only "{z}" is allowed here. No need to check
9183 zeroing mask explicitly. */
9184 if (i
.mask
->operand
!= this_operand
)
9186 as_bad (_("invalid write mask `%s'"), saved
);
9193 /* Check zeroing-flag for masking operation. */
9194 else if (*op_string
== 'z')
9198 mask_op
.mask
= NULL
;
9199 mask_op
.zeroing
= 1;
9200 mask_op
.operand
= this_operand
;
9205 if (i
.mask
->zeroing
)
9208 as_bad (_("duplicated `%s'"), saved
);
9212 i
.mask
->zeroing
= 1;
9214 /* Only "{%k}" is allowed here. No need to check mask
9215 register explicitly. */
9216 if (i
.mask
->operand
!= this_operand
)
9218 as_bad (_("invalid zeroing-masking `%s'"),
9227 goto unknown_vec_op
;
9229 if (*op_string
!= '}')
9231 as_bad (_("missing `}' in `%s'"), saved
);
9236 /* Strip whitespace since the addition of pseudo prefixes
9237 changed how the scrubber treats '{'. */
9238 if (is_space_char (*op_string
))
9244 /* We don't know this one. */
9245 as_bad (_("unknown vector operation: `%s'"), saved
);
9249 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9251 as_bad (_("zeroing-masking only allowed with write mask"));
9259 i386_immediate (char *imm_start
)
9261 char *save_input_line_pointer
;
9262 char *gotfree_input_line
;
9265 i386_operand_type types
;
9267 operand_type_set (&types
, ~0);
9269 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9271 as_bad (_("at most %d immediate operands are allowed"),
9272 MAX_IMMEDIATE_OPERANDS
);
9276 exp
= &im_expressions
[i
.imm_operands
++];
9277 i
.op
[this_operand
].imms
= exp
;
9279 if (is_space_char (*imm_start
))
9282 save_input_line_pointer
= input_line_pointer
;
9283 input_line_pointer
= imm_start
;
9285 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9286 if (gotfree_input_line
)
9287 input_line_pointer
= gotfree_input_line
;
9289 exp_seg
= expression (exp
);
9293 /* Handle vector operations. */
9294 if (*input_line_pointer
== '{')
9296 input_line_pointer
= check_VecOperations (input_line_pointer
,
9298 if (input_line_pointer
== NULL
)
9302 if (*input_line_pointer
)
9303 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9305 input_line_pointer
= save_input_line_pointer
;
9306 if (gotfree_input_line
)
9308 free (gotfree_input_line
);
9310 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9311 exp
->X_op
= O_illegal
;
9314 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9318 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9319 i386_operand_type types
, const char *imm_start
)
9321 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9324 as_bad (_("missing or invalid immediate expression `%s'"),
9328 else if (exp
->X_op
== O_constant
)
9330 /* Size it properly later. */
9331 i
.types
[this_operand
].bitfield
.imm64
= 1;
9332 /* If not 64bit, sign extend val. */
9333 if (flag_code
!= CODE_64BIT
9334 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9336 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9338 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9339 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9340 && exp_seg
!= absolute_section
9341 && exp_seg
!= text_section
9342 && exp_seg
!= data_section
9343 && exp_seg
!= bss_section
9344 && exp_seg
!= undefined_section
9345 && !bfd_is_com_section (exp_seg
))
9347 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9351 else if (!intel_syntax
&& exp_seg
== reg_section
)
9354 as_bad (_("illegal immediate register operand %s"), imm_start
);
9359 /* This is an address. The size of the address will be
9360 determined later, depending on destination register,
9361 suffix, or the default for the section. */
9362 i
.types
[this_operand
].bitfield
.imm8
= 1;
9363 i
.types
[this_operand
].bitfield
.imm16
= 1;
9364 i
.types
[this_operand
].bitfield
.imm32
= 1;
9365 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9366 i
.types
[this_operand
].bitfield
.imm64
= 1;
9367 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9375 i386_scale (char *scale
)
9378 char *save
= input_line_pointer
;
9380 input_line_pointer
= scale
;
9381 val
= get_absolute_expression ();
9386 i
.log2_scale_factor
= 0;
9389 i
.log2_scale_factor
= 1;
9392 i
.log2_scale_factor
= 2;
9395 i
.log2_scale_factor
= 3;
9399 char sep
= *input_line_pointer
;
9401 *input_line_pointer
= '\0';
9402 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9404 *input_line_pointer
= sep
;
9405 input_line_pointer
= save
;
9409 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9411 as_warn (_("scale factor of %d without an index register"),
9412 1 << i
.log2_scale_factor
);
9413 i
.log2_scale_factor
= 0;
9415 scale
= input_line_pointer
;
9416 input_line_pointer
= save
;
9421 i386_displacement (char *disp_start
, char *disp_end
)
9425 char *save_input_line_pointer
;
9426 char *gotfree_input_line
;
9428 i386_operand_type bigdisp
, types
= anydisp
;
9431 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9433 as_bad (_("at most %d displacement operands are allowed"),
9434 MAX_MEMORY_OPERANDS
);
9438 operand_type_set (&bigdisp
, 0);
9439 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
9440 || (!current_templates
->start
->opcode_modifier
.jump
9441 && !current_templates
->start
->opcode_modifier
.jumpdword
))
9443 bigdisp
.bitfield
.disp32
= 1;
9444 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9445 if (flag_code
== CODE_64BIT
)
9449 bigdisp
.bitfield
.disp32s
= 1;
9450 bigdisp
.bitfield
.disp64
= 1;
9453 else if ((flag_code
== CODE_16BIT
) ^ override
)
9455 bigdisp
.bitfield
.disp32
= 0;
9456 bigdisp
.bitfield
.disp16
= 1;
9461 /* For PC-relative branches, the width of the displacement
9462 is dependent upon data size, not address size. */
9463 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9464 if (flag_code
== CODE_64BIT
)
9466 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9467 bigdisp
.bitfield
.disp16
= 1;
9470 bigdisp
.bitfield
.disp32
= 1;
9471 bigdisp
.bitfield
.disp32s
= 1;
9477 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9479 : LONG_MNEM_SUFFIX
));
9480 bigdisp
.bitfield
.disp32
= 1;
9481 if ((flag_code
== CODE_16BIT
) ^ override
)
9483 bigdisp
.bitfield
.disp32
= 0;
9484 bigdisp
.bitfield
.disp16
= 1;
9488 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9491 exp
= &disp_expressions
[i
.disp_operands
];
9492 i
.op
[this_operand
].disps
= exp
;
9494 save_input_line_pointer
= input_line_pointer
;
9495 input_line_pointer
= disp_start
;
9496 END_STRING_AND_SAVE (disp_end
);
9498 #ifndef GCC_ASM_O_HACK
9499 #define GCC_ASM_O_HACK 0
9502 END_STRING_AND_SAVE (disp_end
+ 1);
9503 if (i
.types
[this_operand
].bitfield
.baseIndex
9504 && displacement_string_end
[-1] == '+')
9506 /* This hack is to avoid a warning when using the "o"
9507 constraint within gcc asm statements.
9510 #define _set_tssldt_desc(n,addr,limit,type) \
9511 __asm__ __volatile__ ( \
9513 "movw %w1,2+%0\n\t" \
9515 "movb %b1,4+%0\n\t" \
9516 "movb %4,5+%0\n\t" \
9517 "movb $0,6+%0\n\t" \
9518 "movb %h1,7+%0\n\t" \
9520 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9522 This works great except that the output assembler ends
9523 up looking a bit weird if it turns out that there is
9524 no offset. You end up producing code that looks like:
9537 So here we provide the missing zero. */
9539 *displacement_string_end
= '0';
9542 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9543 if (gotfree_input_line
)
9544 input_line_pointer
= gotfree_input_line
;
9546 exp_seg
= expression (exp
);
9549 if (*input_line_pointer
)
9550 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9552 RESTORE_END_STRING (disp_end
+ 1);
9554 input_line_pointer
= save_input_line_pointer
;
9555 if (gotfree_input_line
)
9557 free (gotfree_input_line
);
9559 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9560 exp
->X_op
= O_illegal
;
9563 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9565 RESTORE_END_STRING (disp_end
);
9571 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9572 i386_operand_type types
, const char *disp_start
)
9574 i386_operand_type bigdisp
;
9577 /* We do this to make sure that the section symbol is in
9578 the symbol table. We will ultimately change the relocation
9579 to be relative to the beginning of the section. */
9580 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9581 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9582 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9584 if (exp
->X_op
!= O_symbol
)
9587 if (S_IS_LOCAL (exp
->X_add_symbol
)
9588 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9589 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9590 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9591 exp
->X_op
= O_subtract
;
9592 exp
->X_op_symbol
= GOT_symbol
;
9593 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9594 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9595 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9596 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9598 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9601 else if (exp
->X_op
== O_absent
9602 || exp
->X_op
== O_illegal
9603 || exp
->X_op
== O_big
)
9606 as_bad (_("missing or invalid displacement expression `%s'"),
9611 else if (flag_code
== CODE_64BIT
9612 && !i
.prefix
[ADDR_PREFIX
]
9613 && exp
->X_op
== O_constant
)
9615 /* Since displacement is signed extended to 64bit, don't allow
9616 disp32 and turn off disp32s if they are out of range. */
9617 i
.types
[this_operand
].bitfield
.disp32
= 0;
9618 if (!fits_in_signed_long (exp
->X_add_number
))
9620 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9621 if (i
.types
[this_operand
].bitfield
.baseindex
)
9623 as_bad (_("0x%lx out range of signed 32bit displacement"),
9624 (long) exp
->X_add_number
);
9630 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9631 else if (exp
->X_op
!= O_constant
9632 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9633 && exp_seg
!= absolute_section
9634 && exp_seg
!= text_section
9635 && exp_seg
!= data_section
9636 && exp_seg
!= bss_section
9637 && exp_seg
!= undefined_section
9638 && !bfd_is_com_section (exp_seg
))
9640 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9645 /* Check if this is a displacement only operand. */
9646 bigdisp
= i
.types
[this_operand
];
9647 bigdisp
.bitfield
.disp8
= 0;
9648 bigdisp
.bitfield
.disp16
= 0;
9649 bigdisp
.bitfield
.disp32
= 0;
9650 bigdisp
.bitfield
.disp32s
= 0;
9651 bigdisp
.bitfield
.disp64
= 0;
9652 if (operand_type_all_zero (&bigdisp
))
9653 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9659 /* Return the active addressing mode, taking address override and
9660 registers forming the address into consideration. Update the
9661 address override prefix if necessary. */
9663 static enum flag_code
9664 i386_addressing_mode (void)
9666 enum flag_code addr_mode
;
9668 if (i
.prefix
[ADDR_PREFIX
])
9669 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9672 addr_mode
= flag_code
;
9674 #if INFER_ADDR_PREFIX
9675 if (i
.mem_operands
== 0)
9677 /* Infer address prefix from the first memory operand. */
9678 const reg_entry
*addr_reg
= i
.base_reg
;
9680 if (addr_reg
== NULL
)
9681 addr_reg
= i
.index_reg
;
9685 if (addr_reg
->reg_type
.bitfield
.dword
)
9686 addr_mode
= CODE_32BIT
;
9687 else if (flag_code
!= CODE_64BIT
9688 && addr_reg
->reg_type
.bitfield
.word
)
9689 addr_mode
= CODE_16BIT
;
9691 if (addr_mode
!= flag_code
)
9693 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9695 /* Change the size of any displacement too. At most one
9696 of Disp16 or Disp32 is set.
9697 FIXME. There doesn't seem to be any real need for
9698 separate Disp16 and Disp32 flags. The same goes for
9699 Imm16 and Imm32. Removing them would probably clean
9700 up the code quite a lot. */
9701 if (flag_code
!= CODE_64BIT
9702 && (i
.types
[this_operand
].bitfield
.disp16
9703 || i
.types
[this_operand
].bitfield
.disp32
))
9704 i
.types
[this_operand
]
9705 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9715 /* Make sure the memory operand we've been dealt is valid.
9716 Return 1 on success, 0 on a failure. */
9719 i386_index_check (const char *operand_string
)
9721 const char *kind
= "base/index";
9722 enum flag_code addr_mode
= i386_addressing_mode ();
9724 if (current_templates
->start
->opcode_modifier
.isstring
9725 && !current_templates
->start
->opcode_modifier
.immext
9726 && (current_templates
->end
[-1].opcode_modifier
.isstring
9729 /* Memory operands of string insns are special in that they only allow
9730 a single register (rDI, rSI, or rBX) as their memory address. */
9731 const reg_entry
*expected_reg
;
9732 static const char *di_si
[][2] =
9738 static const char *bx
[] = { "ebx", "bx", "rbx" };
9740 kind
= "string address";
9742 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9744 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9746 if (!type
.bitfield
.baseindex
9747 || ((!i
.mem_operands
!= !intel_syntax
)
9748 && current_templates
->end
[-1].operand_types
[1]
9749 .bitfield
.baseindex
))
9750 type
= current_templates
->end
[-1].operand_types
[1];
9751 expected_reg
= hash_find (reg_hash
,
9752 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9756 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9758 if (i
.base_reg
!= expected_reg
9760 || operand_type_check (i
.types
[this_operand
], disp
))
9762 /* The second memory operand must have the same size as
9766 && !((addr_mode
== CODE_64BIT
9767 && i
.base_reg
->reg_type
.bitfield
.qword
)
9768 || (addr_mode
== CODE_32BIT
9769 ? i
.base_reg
->reg_type
.bitfield
.dword
9770 : i
.base_reg
->reg_type
.bitfield
.word
)))
9773 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9775 intel_syntax
? '[' : '(',
9777 expected_reg
->reg_name
,
9778 intel_syntax
? ']' : ')');
9785 as_bad (_("`%s' is not a valid %s expression"),
9786 operand_string
, kind
);
9791 if (addr_mode
!= CODE_16BIT
)
9793 /* 32-bit/64-bit checks. */
9795 && ((addr_mode
== CODE_64BIT
9796 ? !i
.base_reg
->reg_type
.bitfield
.qword
9797 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9798 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
9799 || i
.base_reg
->reg_num
== RegIZ
))
9801 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9802 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9803 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9804 && ((addr_mode
== CODE_64BIT
9805 ? !i
.index_reg
->reg_type
.bitfield
.qword
9806 : !i
.index_reg
->reg_type
.bitfield
.dword
)
9807 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9810 /* bndmk, bndldx, and bndstx have special restrictions. */
9811 if (current_templates
->start
->base_opcode
== 0xf30f1b
9812 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9814 /* They cannot use RIP-relative addressing. */
9815 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9817 as_bad (_("`%s' cannot be used here"), operand_string
);
9821 /* bndldx and bndstx ignore their scale factor. */
9822 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9823 && i
.log2_scale_factor
)
9824 as_warn (_("register scaling is being ignored here"));
9829 /* 16-bit checks. */
9831 && (!i
.base_reg
->reg_type
.bitfield
.word
9832 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9834 && (!i
.index_reg
->reg_type
.bitfield
.word
9835 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9837 && i
.base_reg
->reg_num
< 6
9838 && i
.index_reg
->reg_num
>= 6
9839 && i
.log2_scale_factor
== 0))))
9846 /* Handle vector immediates. */
9849 RC_SAE_immediate (const char *imm_start
)
9851 unsigned int match_found
, j
;
9852 const char *pstr
= imm_start
;
9860 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9862 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9866 rc_op
.type
= RC_NamesTable
[j
].type
;
9867 rc_op
.operand
= this_operand
;
9868 i
.rounding
= &rc_op
;
9872 as_bad (_("duplicated `%s'"), imm_start
);
9875 pstr
+= RC_NamesTable
[j
].len
;
9885 as_bad (_("Missing '}': '%s'"), imm_start
);
9888 /* RC/SAE immediate string should contain nothing more. */;
9891 as_bad (_("Junk after '}': '%s'"), imm_start
);
9895 exp
= &im_expressions
[i
.imm_operands
++];
9896 i
.op
[this_operand
].imms
= exp
;
9898 exp
->X_op
= O_constant
;
9899 exp
->X_add_number
= 0;
9900 exp
->X_add_symbol
= (symbolS
*) 0;
9901 exp
->X_op_symbol
= (symbolS
*) 0;
9903 i
.types
[this_operand
].bitfield
.imm8
= 1;
9907 /* Only string instructions can have a second memory operand, so
9908 reduce current_templates to just those if it contains any. */
9910 maybe_adjust_templates (void)
9912 const insn_template
*t
;
9914 gas_assert (i
.mem_operands
== 1);
9916 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9917 if (t
->opcode_modifier
.isstring
)
9920 if (t
< current_templates
->end
)
9922 static templates aux_templates
;
9923 bfd_boolean recheck
;
9925 aux_templates
.start
= t
;
9926 for (; t
< current_templates
->end
; ++t
)
9927 if (!t
->opcode_modifier
.isstring
)
9929 aux_templates
.end
= t
;
9931 /* Determine whether to re-check the first memory operand. */
9932 recheck
= (aux_templates
.start
!= current_templates
->start
9933 || t
!= current_templates
->end
);
9935 current_templates
= &aux_templates
;
9940 if (i
.memop1_string
!= NULL
9941 && i386_index_check (i
.memop1_string
) == 0)
9950 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9954 i386_att_operand (char *operand_string
)
9958 char *op_string
= operand_string
;
9960 if (is_space_char (*op_string
))
9963 /* We check for an absolute prefix (differentiating,
9964 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9965 if (*op_string
== ABSOLUTE_PREFIX
)
9968 if (is_space_char (*op_string
))
9970 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9973 /* Check if operand is a register. */
9974 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
9976 i386_operand_type temp
;
9978 /* Check for a segment override by searching for ':' after a
9979 segment register. */
9981 if (is_space_char (*op_string
))
9983 if (*op_string
== ':'
9984 && (r
->reg_type
.bitfield
.sreg2
9985 || r
->reg_type
.bitfield
.sreg3
))
9990 i
.seg
[i
.mem_operands
] = &es
;
9993 i
.seg
[i
.mem_operands
] = &cs
;
9996 i
.seg
[i
.mem_operands
] = &ss
;
9999 i
.seg
[i
.mem_operands
] = &ds
;
10002 i
.seg
[i
.mem_operands
] = &fs
;
10005 i
.seg
[i
.mem_operands
] = &gs
;
10009 /* Skip the ':' and whitespace. */
10011 if (is_space_char (*op_string
))
10014 if (!is_digit_char (*op_string
)
10015 && !is_identifier_char (*op_string
)
10016 && *op_string
!= '('
10017 && *op_string
!= ABSOLUTE_PREFIX
)
10019 as_bad (_("bad memory operand `%s'"), op_string
);
10022 /* Handle case of %es:*foo. */
10023 if (*op_string
== ABSOLUTE_PREFIX
)
10026 if (is_space_char (*op_string
))
10028 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
10030 goto do_memory_reference
;
10033 /* Handle vector operations. */
10034 if (*op_string
== '{')
10036 op_string
= check_VecOperations (op_string
, NULL
);
10037 if (op_string
== NULL
)
10043 as_bad (_("junk `%s' after register"), op_string
);
10046 temp
= r
->reg_type
;
10047 temp
.bitfield
.baseindex
= 0;
10048 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10050 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10051 i
.op
[this_operand
].regs
= r
;
10054 else if (*op_string
== REGISTER_PREFIX
)
10056 as_bad (_("bad register name `%s'"), op_string
);
10059 else if (*op_string
== IMMEDIATE_PREFIX
)
10062 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
10064 as_bad (_("immediate operand illegal with absolute jump"));
10067 if (!i386_immediate (op_string
))
10070 else if (RC_SAE_immediate (operand_string
))
10072 /* If it is a RC or SAE immediate, do nothing. */
10075 else if (is_digit_char (*op_string
)
10076 || is_identifier_char (*op_string
)
10077 || *op_string
== '"'
10078 || *op_string
== '(')
10080 /* This is a memory reference of some sort. */
10083 /* Start and end of displacement string expression (if found). */
10084 char *displacement_string_start
;
10085 char *displacement_string_end
;
10088 do_memory_reference
:
10089 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10091 if ((i
.mem_operands
== 1
10092 && !current_templates
->start
->opcode_modifier
.isstring
)
10093 || i
.mem_operands
== 2)
10095 as_bad (_("too many memory references for `%s'"),
10096 current_templates
->start
->name
);
10100 /* Check for base index form. We detect the base index form by
10101 looking for an ')' at the end of the operand, searching
10102 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10104 base_string
= op_string
+ strlen (op_string
);
10106 /* Handle vector operations. */
10107 vop_start
= strchr (op_string
, '{');
10108 if (vop_start
&& vop_start
< base_string
)
10110 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10112 base_string
= vop_start
;
10116 if (is_space_char (*base_string
))
10119 /* If we only have a displacement, set-up for it to be parsed later. */
10120 displacement_string_start
= op_string
;
10121 displacement_string_end
= base_string
+ 1;
10123 if (*base_string
== ')')
10126 unsigned int parens_balanced
= 1;
10127 /* We've already checked that the number of left & right ()'s are
10128 equal, so this loop will not be infinite. */
10132 if (*base_string
== ')')
10134 if (*base_string
== '(')
10137 while (parens_balanced
);
10139 temp_string
= base_string
;
10141 /* Skip past '(' and whitespace. */
10143 if (is_space_char (*base_string
))
10146 if (*base_string
== ','
10147 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10150 displacement_string_end
= temp_string
;
10152 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10156 base_string
= end_op
;
10157 if (is_space_char (*base_string
))
10161 /* There may be an index reg or scale factor here. */
10162 if (*base_string
== ',')
10165 if (is_space_char (*base_string
))
10168 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10171 base_string
= end_op
;
10172 if (is_space_char (*base_string
))
10174 if (*base_string
== ',')
10177 if (is_space_char (*base_string
))
10180 else if (*base_string
!= ')')
10182 as_bad (_("expecting `,' or `)' "
10183 "after index register in `%s'"),
10188 else if (*base_string
== REGISTER_PREFIX
)
10190 end_op
= strchr (base_string
, ',');
10193 as_bad (_("bad register name `%s'"), base_string
);
10197 /* Check for scale factor. */
10198 if (*base_string
!= ')')
10200 char *end_scale
= i386_scale (base_string
);
10205 base_string
= end_scale
;
10206 if (is_space_char (*base_string
))
10208 if (*base_string
!= ')')
10210 as_bad (_("expecting `)' "
10211 "after scale factor in `%s'"),
10216 else if (!i
.index_reg
)
10218 as_bad (_("expecting index register or scale factor "
10219 "after `,'; got '%c'"),
10224 else if (*base_string
!= ')')
10226 as_bad (_("expecting `,' or `)' "
10227 "after base register in `%s'"),
10232 else if (*base_string
== REGISTER_PREFIX
)
10234 end_op
= strchr (base_string
, ',');
10237 as_bad (_("bad register name `%s'"), base_string
);
10242 /* If there's an expression beginning the operand, parse it,
10243 assuming displacement_string_start and
10244 displacement_string_end are meaningful. */
10245 if (displacement_string_start
!= displacement_string_end
)
10247 if (!i386_displacement (displacement_string_start
,
10248 displacement_string_end
))
10252 /* Special case for (%dx) while doing input/output op. */
10254 && i
.base_reg
->reg_type
.bitfield
.inoutportreg
10255 && i
.index_reg
== 0
10256 && i
.log2_scale_factor
== 0
10257 && i
.seg
[i
.mem_operands
] == 0
10258 && !operand_type_check (i
.types
[this_operand
], disp
))
10260 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10264 if (i386_index_check (operand_string
) == 0)
10266 i
.flags
[this_operand
] |= Operand_Mem
;
10267 if (i
.mem_operands
== 0)
10268 i
.memop1_string
= xstrdup (operand_string
);
10273 /* It's not a memory operand; argh! */
10274 as_bad (_("invalid char %s beginning operand %d `%s'"),
10275 output_invalid (*op_string
),
10280 return 1; /* Normal return. */
10283 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10284 that an rs_machine_dependent frag may reach. */
10287 i386_frag_max_var (fragS
*frag
)
10289 /* The only relaxable frags are for jumps.
10290 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10291 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10292 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10295 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10297 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10299 /* STT_GNU_IFUNC symbol must go through PLT. */
10300 if ((symbol_get_bfdsym (fr_symbol
)->flags
10301 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10304 if (!S_IS_EXTERNAL (fr_symbol
))
10305 /* Symbol may be weak or local. */
10306 return !S_IS_WEAK (fr_symbol
);
10308 /* Global symbols with non-default visibility can't be preempted. */
10309 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10312 if (fr_var
!= NO_RELOC
)
10313 switch ((enum bfd_reloc_code_real
) fr_var
)
10315 case BFD_RELOC_386_PLT32
:
10316 case BFD_RELOC_X86_64_PLT32
:
10317 /* Symbol with PLT relocation may be preempted. */
10323 /* Global symbols with default visibility in a shared library may be
10324 preempted by another definition. */
10329 /* md_estimate_size_before_relax()
10331 Called just before relax() for rs_machine_dependent frags. The x86
10332 assembler uses these frags to handle variable size jump
10335 Any symbol that is now undefined will not become defined.
10336 Return the correct fr_subtype in the frag.
10337 Return the initial "guess for variable size of frag" to caller.
10338 The guess is actually the growth beyond the fixed part. Whatever
10339 we do to grow the fixed or variable part contributes to our
10343 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
10345 /* We've already got fragP->fr_subtype right; all we have to do is
10346 check for un-relaxable symbols. On an ELF system, we can't relax
10347 an externally visible symbol, because it may be overridden by a
10349 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
10350 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10352 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
10355 #if defined (OBJ_COFF) && defined (TE_PE)
10356 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
10357 && S_IS_WEAK (fragP
->fr_symbol
))
10361 /* Symbol is undefined in this segment, or we need to keep a
10362 reloc so that weak symbols can be overridden. */
10363 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
10364 enum bfd_reloc_code_real reloc_type
;
10365 unsigned char *opcode
;
10368 if (fragP
->fr_var
!= NO_RELOC
)
10369 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
10370 else if (size
== 2)
10371 reloc_type
= BFD_RELOC_16_PCREL
;
10372 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10373 else if (need_plt32_p (fragP
->fr_symbol
))
10374 reloc_type
= BFD_RELOC_X86_64_PLT32
;
10377 reloc_type
= BFD_RELOC_32_PCREL
;
10379 old_fr_fix
= fragP
->fr_fix
;
10380 opcode
= (unsigned char *) fragP
->fr_opcode
;
10382 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
10385 /* Make jmp (0xeb) a (d)word displacement jump. */
10387 fragP
->fr_fix
+= size
;
10388 fix_new (fragP
, old_fr_fix
, size
,
10390 fragP
->fr_offset
, 1,
10396 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
10398 /* Negate the condition, and branch past an
10399 unconditional jump. */
10402 /* Insert an unconditional jump. */
10404 /* We added two extra opcode bytes, and have a two byte
10406 fragP
->fr_fix
+= 2 + 2;
10407 fix_new (fragP
, old_fr_fix
+ 2, 2,
10409 fragP
->fr_offset
, 1,
10413 /* Fall through. */
10416 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
10420 fragP
->fr_fix
+= 1;
10421 fixP
= fix_new (fragP
, old_fr_fix
, 1,
10423 fragP
->fr_offset
, 1,
10424 BFD_RELOC_8_PCREL
);
10425 fixP
->fx_signed
= 1;
10429 /* This changes the byte-displacement jump 0x7N
10430 to the (d)word-displacement jump 0x0f,0x8N. */
10431 opcode
[1] = opcode
[0] + 0x10;
10432 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10433 /* We've added an opcode byte. */
10434 fragP
->fr_fix
+= 1 + size
;
10435 fix_new (fragP
, old_fr_fix
+ 1, size
,
10437 fragP
->fr_offset
, 1,
10442 BAD_CASE (fragP
->fr_subtype
);
10446 return fragP
->fr_fix
- old_fr_fix
;
10449 /* Guess size depending on current relax state. Initially the relax
10450 state will correspond to a short jump and we return 1, because
10451 the variable part of the frag (the branch offset) is one byte
10452 long. However, we can relax a section more than once and in that
10453 case we must either set fr_subtype back to the unrelaxed state,
10454 or return the value for the appropriate branch. */
10455 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
10458 /* Called after relax() is finished.
10460 In: Address of frag.
10461 fr_type == rs_machine_dependent.
10462 fr_subtype is what the address relaxed to.
10464 Out: Any fixSs and constants are set up.
10465 Caller will turn frag into a ".space 0". */
10468 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
10471 unsigned char *opcode
;
10472 unsigned char *where_to_put_displacement
= NULL
;
10473 offsetT target_address
;
10474 offsetT opcode_address
;
10475 unsigned int extension
= 0;
10476 offsetT displacement_from_opcode_start
;
10478 opcode
= (unsigned char *) fragP
->fr_opcode
;
10480 /* Address we want to reach in file space. */
10481 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
10483 /* Address opcode resides at in file space. */
10484 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
10486 /* Displacement from opcode start to fill into instruction. */
10487 displacement_from_opcode_start
= target_address
- opcode_address
;
10489 if ((fragP
->fr_subtype
& BIG
) == 0)
10491 /* Don't have to change opcode. */
10492 extension
= 1; /* 1 opcode + 1 displacement */
10493 where_to_put_displacement
= &opcode
[1];
10497 if (no_cond_jump_promotion
10498 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
10499 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
10500 _("long jump required"));
10502 switch (fragP
->fr_subtype
)
10504 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10505 extension
= 4; /* 1 opcode + 4 displacement */
10507 where_to_put_displacement
= &opcode
[1];
10510 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10511 extension
= 2; /* 1 opcode + 2 displacement */
10513 where_to_put_displacement
= &opcode
[1];
10516 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10517 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10518 extension
= 5; /* 2 opcode + 4 displacement */
10519 opcode
[1] = opcode
[0] + 0x10;
10520 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10521 where_to_put_displacement
= &opcode
[2];
10524 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10525 extension
= 3; /* 2 opcode + 2 displacement */
10526 opcode
[1] = opcode
[0] + 0x10;
10527 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10528 where_to_put_displacement
= &opcode
[2];
10531 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10536 where_to_put_displacement
= &opcode
[3];
10540 BAD_CASE (fragP
->fr_subtype
);
10545 /* If size if less then four we are sure that the operand fits,
10546 but if it's 4, then it could be that the displacement is larger
10548 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10550 && ((addressT
) (displacement_from_opcode_start
- extension
10551 + ((addressT
) 1 << 31))
10552 > (((addressT
) 2 << 31) - 1)))
10554 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10555 _("jump target out of range"));
10556 /* Make us emit 0. */
10557 displacement_from_opcode_start
= extension
;
10559 /* Now put displacement after opcode. */
10560 md_number_to_chars ((char *) where_to_put_displacement
,
10561 (valueT
) (displacement_from_opcode_start
- extension
),
10562 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10563 fragP
->fr_fix
+= extension
;
10566 /* Apply a fixup (fixP) to segment data, once it has been determined
10567 by our caller that we have all the info we need to fix it up.
10569 Parameter valP is the pointer to the value of the bits.
10571 On the 386, immediates, displacements, and data pointers are all in
10572 the same (little-endian) format, so we don't need to care about which
10573 we are handling. */
10576 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10578 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10579 valueT value
= *valP
;
10581 #if !defined (TE_Mach)
10582 if (fixP
->fx_pcrel
)
10584 switch (fixP
->fx_r_type
)
10590 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10593 case BFD_RELOC_X86_64_32S
:
10594 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10597 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10600 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10605 if (fixP
->fx_addsy
!= NULL
10606 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10607 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10608 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10609 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10610 && !use_rela_relocations
)
10612 /* This is a hack. There should be a better way to handle this.
10613 This covers for the fact that bfd_install_relocation will
10614 subtract the current location (for partial_inplace, PC relative
10615 relocations); see more below. */
10619 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10622 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10624 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10627 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10629 if ((sym_seg
== seg
10630 || (symbol_section_p (fixP
->fx_addsy
)
10631 && sym_seg
!= absolute_section
))
10632 && !generic_force_reloc (fixP
))
10634 /* Yes, we add the values in twice. This is because
10635 bfd_install_relocation subtracts them out again. I think
10636 bfd_install_relocation is broken, but I don't dare change
10638 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10642 #if defined (OBJ_COFF) && defined (TE_PE)
10643 /* For some reason, the PE format does not store a
10644 section address offset for a PC relative symbol. */
10645 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10646 || S_IS_WEAK (fixP
->fx_addsy
))
10647 value
+= md_pcrel_from (fixP
);
10650 #if defined (OBJ_COFF) && defined (TE_PE)
10651 if (fixP
->fx_addsy
!= NULL
10652 && S_IS_WEAK (fixP
->fx_addsy
)
10653 /* PR 16858: Do not modify weak function references. */
10654 && ! fixP
->fx_pcrel
)
10656 #if !defined (TE_PEP)
10657 /* For x86 PE weak function symbols are neither PC-relative
10658 nor do they set S_IS_FUNCTION. So the only reliable way
10659 to detect them is to check the flags of their containing
10661 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10662 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10666 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10670 /* Fix a few things - the dynamic linker expects certain values here,
10671 and we must not disappoint it. */
10672 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10673 if (IS_ELF
&& fixP
->fx_addsy
)
10674 switch (fixP
->fx_r_type
)
10676 case BFD_RELOC_386_PLT32
:
10677 case BFD_RELOC_X86_64_PLT32
:
10678 /* Make the jump instruction point to the address of the operand.
10679 At runtime we merely add the offset to the actual PLT entry.
10680 NB: Subtract the offset size only for jump instructions. */
10681 if (fixP
->fx_pcrel
)
10685 case BFD_RELOC_386_TLS_GD
:
10686 case BFD_RELOC_386_TLS_LDM
:
10687 case BFD_RELOC_386_TLS_IE_32
:
10688 case BFD_RELOC_386_TLS_IE
:
10689 case BFD_RELOC_386_TLS_GOTIE
:
10690 case BFD_RELOC_386_TLS_GOTDESC
:
10691 case BFD_RELOC_X86_64_TLSGD
:
10692 case BFD_RELOC_X86_64_TLSLD
:
10693 case BFD_RELOC_X86_64_GOTTPOFF
:
10694 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10695 value
= 0; /* Fully resolved at runtime. No addend. */
10697 case BFD_RELOC_386_TLS_LE
:
10698 case BFD_RELOC_386_TLS_LDO_32
:
10699 case BFD_RELOC_386_TLS_LE_32
:
10700 case BFD_RELOC_X86_64_DTPOFF32
:
10701 case BFD_RELOC_X86_64_DTPOFF64
:
10702 case BFD_RELOC_X86_64_TPOFF32
:
10703 case BFD_RELOC_X86_64_TPOFF64
:
10704 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10707 case BFD_RELOC_386_TLS_DESC_CALL
:
10708 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10709 value
= 0; /* Fully resolved at runtime. No addend. */
10710 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10714 case BFD_RELOC_VTABLE_INHERIT
:
10715 case BFD_RELOC_VTABLE_ENTRY
:
10722 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10724 #endif /* !defined (TE_Mach) */
10726 /* Are we finished with this relocation now? */
10727 if (fixP
->fx_addsy
== NULL
)
10729 #if defined (OBJ_COFF) && defined (TE_PE)
10730 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10733 /* Remember value for tc_gen_reloc. */
10734 fixP
->fx_addnumber
= value
;
10735 /* Clear out the frag for now. */
10739 else if (use_rela_relocations
)
10741 fixP
->fx_no_overflow
= 1;
10742 /* Remember value for tc_gen_reloc. */
10743 fixP
->fx_addnumber
= value
;
10747 md_number_to_chars (p
, value
, fixP
->fx_size
);
10751 md_atof (int type
, char *litP
, int *sizeP
)
10753 /* This outputs the LITTLENUMs in REVERSE order;
10754 in accord with the bigendian 386. */
10755 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10758 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10761 output_invalid (int c
)
10764 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10767 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10768 "(0x%x)", (unsigned char) c
);
10769 return output_invalid_buf
;
10772 /* REG_STRING starts *before* REGISTER_PREFIX. */
10774 static const reg_entry
*
10775 parse_real_register (char *reg_string
, char **end_op
)
10777 char *s
= reg_string
;
10779 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10780 const reg_entry
*r
;
10782 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10783 if (*s
== REGISTER_PREFIX
)
10786 if (is_space_char (*s
))
10789 p
= reg_name_given
;
10790 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10792 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10793 return (const reg_entry
*) NULL
;
10797 /* For naked regs, make sure that we are not dealing with an identifier.
10798 This prevents confusing an identifier like `eax_var' with register
10800 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10801 return (const reg_entry
*) NULL
;
10805 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10807 /* Handle floating point regs, allowing spaces in the (i) part. */
10808 if (r
== i386_regtab
/* %st is first entry of table */)
10810 if (!cpu_arch_flags
.bitfield
.cpu8087
10811 && !cpu_arch_flags
.bitfield
.cpu287
10812 && !cpu_arch_flags
.bitfield
.cpu387
)
10813 return (const reg_entry
*) NULL
;
10815 if (is_space_char (*s
))
10820 if (is_space_char (*s
))
10822 if (*s
>= '0' && *s
<= '7')
10824 int fpr
= *s
- '0';
10826 if (is_space_char (*s
))
10831 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10836 /* We have "%st(" then garbage. */
10837 return (const reg_entry
*) NULL
;
10841 if (r
== NULL
|| allow_pseudo_reg
)
10844 if (operand_type_all_zero (&r
->reg_type
))
10845 return (const reg_entry
*) NULL
;
10847 if ((r
->reg_type
.bitfield
.dword
10848 || r
->reg_type
.bitfield
.sreg3
10849 || r
->reg_type
.bitfield
.control
10850 || r
->reg_type
.bitfield
.debug
10851 || r
->reg_type
.bitfield
.test
)
10852 && !cpu_arch_flags
.bitfield
.cpui386
)
10853 return (const reg_entry
*) NULL
;
10855 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10856 return (const reg_entry
*) NULL
;
10858 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10860 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10861 return (const reg_entry
*) NULL
;
10863 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10865 if (r
->reg_type
.bitfield
.ymmword
)
10866 return (const reg_entry
*) NULL
;
10868 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10869 return (const reg_entry
*) NULL
;
10873 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10874 return (const reg_entry
*) NULL
;
10876 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10877 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
10878 return (const reg_entry
*) NULL
;
10880 /* Upper 16 vector registers are only available with VREX in 64bit
10881 mode, and require EVEX encoding. */
10882 if (r
->reg_flags
& RegVRex
)
10884 if (!cpu_arch_flags
.bitfield
.cpuavx512f
10885 || flag_code
!= CODE_64BIT
)
10886 return (const reg_entry
*) NULL
;
10888 i
.vec_encoding
= vex_encoding_evex
;
10891 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10892 && (!cpu_arch_flags
.bitfield
.cpulm
|| !r
->reg_type
.bitfield
.control
)
10893 && flag_code
!= CODE_64BIT
)
10894 return (const reg_entry
*) NULL
;
10896 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10897 return (const reg_entry
*) NULL
;
10902 /* REG_STRING starts *before* REGISTER_PREFIX. */
10904 static const reg_entry
*
10905 parse_register (char *reg_string
, char **end_op
)
10907 const reg_entry
*r
;
10909 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10910 r
= parse_real_register (reg_string
, end_op
);
10915 char *save
= input_line_pointer
;
10919 input_line_pointer
= reg_string
;
10920 c
= get_symbol_name (®_string
);
10921 symbolP
= symbol_find (reg_string
);
10922 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10924 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10926 know (e
->X_op
== O_register
);
10927 know (e
->X_add_number
>= 0
10928 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10929 r
= i386_regtab
+ e
->X_add_number
;
10930 if ((r
->reg_flags
& RegVRex
))
10931 i
.vec_encoding
= vex_encoding_evex
;
10932 *end_op
= input_line_pointer
;
10934 *input_line_pointer
= c
;
10935 input_line_pointer
= save
;
10941 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10943 const reg_entry
*r
;
10944 char *end
= input_line_pointer
;
10947 r
= parse_register (name
, &input_line_pointer
);
10948 if (r
&& end
<= input_line_pointer
)
10950 *nextcharP
= *input_line_pointer
;
10951 *input_line_pointer
= 0;
10952 e
->X_op
= O_register
;
10953 e
->X_add_number
= r
- i386_regtab
;
10956 input_line_pointer
= end
;
10958 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
10962 md_operand (expressionS
*e
)
10965 const reg_entry
*r
;
10967 switch (*input_line_pointer
)
10969 case REGISTER_PREFIX
:
10970 r
= parse_real_register (input_line_pointer
, &end
);
10973 e
->X_op
= O_register
;
10974 e
->X_add_number
= r
- i386_regtab
;
10975 input_line_pointer
= end
;
10980 gas_assert (intel_syntax
);
10981 end
= input_line_pointer
++;
10983 if (*input_line_pointer
== ']')
10985 ++input_line_pointer
;
10986 e
->X_op_symbol
= make_expr_symbol (e
);
10987 e
->X_add_symbol
= NULL
;
10988 e
->X_add_number
= 0;
10993 e
->X_op
= O_absent
;
10994 input_line_pointer
= end
;
11001 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11002 const char *md_shortopts
= "kVQ:sqnO::";
11004 const char *md_shortopts
= "qnO::";
11007 #define OPTION_32 (OPTION_MD_BASE + 0)
11008 #define OPTION_64 (OPTION_MD_BASE + 1)
11009 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
11010 #define OPTION_MARCH (OPTION_MD_BASE + 3)
11011 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
11012 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
11013 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
11014 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
11015 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
11016 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
11017 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
11018 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
11019 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
11020 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
11021 #define OPTION_X32 (OPTION_MD_BASE + 14)
11022 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
11023 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
11024 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
11025 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
11026 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
11027 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
11028 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
11029 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
11030 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
11031 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
11032 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
11033 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
11035 struct option md_longopts
[] =
11037 {"32", no_argument
, NULL
, OPTION_32
},
11038 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11039 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11040 {"64", no_argument
, NULL
, OPTION_64
},
11042 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11043 {"x32", no_argument
, NULL
, OPTION_X32
},
11044 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
11045 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
11047 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
11048 {"march", required_argument
, NULL
, OPTION_MARCH
},
11049 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
11050 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
11051 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
11052 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
11053 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
11054 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
11055 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
11056 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
11057 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
11058 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
11059 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
11060 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
11061 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
11062 # if defined (TE_PE) || defined (TE_PEP)
11063 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
11065 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
11066 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
11067 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
11068 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
11069 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
11070 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
11071 {NULL
, no_argument
, NULL
, 0}
11073 size_t md_longopts_size
= sizeof (md_longopts
);
11076 md_parse_option (int c
, const char *arg
)
11079 char *arch
, *next
, *saved
;
11084 optimize_align_code
= 0;
11088 quiet_warnings
= 1;
11091 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11092 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
11093 should be emitted or not. FIXME: Not implemented. */
11097 /* -V: SVR4 argument to print version ID. */
11099 print_version_id ();
11102 /* -k: Ignore for FreeBSD compatibility. */
11107 /* -s: On i386 Solaris, this tells the native assembler to use
11108 .stab instead of .stab.excl. We always use .stab anyhow. */
11111 case OPTION_MSHARED
:
11115 case OPTION_X86_USED_NOTE
:
11116 if (strcasecmp (arg
, "yes") == 0)
11118 else if (strcasecmp (arg
, "no") == 0)
11121 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
11126 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11127 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11130 const char **list
, **l
;
11132 list
= bfd_target_list ();
11133 for (l
= list
; *l
!= NULL
; l
++)
11134 if (CONST_STRNEQ (*l
, "elf64-x86-64")
11135 || strcmp (*l
, "coff-x86-64") == 0
11136 || strcmp (*l
, "pe-x86-64") == 0
11137 || strcmp (*l
, "pei-x86-64") == 0
11138 || strcmp (*l
, "mach-o-x86-64") == 0)
11140 default_arch
= "x86_64";
11144 as_fatal (_("no compiled in support for x86_64"));
11150 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11154 const char **list
, **l
;
11156 list
= bfd_target_list ();
11157 for (l
= list
; *l
!= NULL
; l
++)
11158 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
11160 default_arch
= "x86_64:32";
11164 as_fatal (_("no compiled in support for 32bit x86_64"));
11168 as_fatal (_("32bit x86_64 is only supported for ELF"));
11173 default_arch
= "i386";
11176 case OPTION_DIVIDE
:
11177 #ifdef SVR4_COMMENT_CHARS
11182 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
11184 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
11188 i386_comment_chars
= n
;
11194 saved
= xstrdup (arg
);
11196 /* Allow -march=+nosse. */
11202 as_fatal (_("invalid -march= option: `%s'"), arg
);
11203 next
= strchr (arch
, '+');
11206 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11208 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
11211 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11214 cpu_arch_name
= cpu_arch
[j
].name
;
11215 cpu_sub_arch_name
= NULL
;
11216 cpu_arch_flags
= cpu_arch
[j
].flags
;
11217 cpu_arch_isa
= cpu_arch
[j
].type
;
11218 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
11219 if (!cpu_arch_tune_set
)
11221 cpu_arch_tune
= cpu_arch_isa
;
11222 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11226 else if (*cpu_arch
[j
].name
== '.'
11227 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
11229 /* ISA extension. */
11230 i386_cpu_flags flags
;
11232 flags
= cpu_flags_or (cpu_arch_flags
,
11233 cpu_arch
[j
].flags
);
11235 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11237 if (cpu_sub_arch_name
)
11239 char *name
= cpu_sub_arch_name
;
11240 cpu_sub_arch_name
= concat (name
,
11242 (const char *) NULL
);
11246 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
11247 cpu_arch_flags
= flags
;
11248 cpu_arch_isa_flags
= flags
;
11252 = cpu_flags_or (cpu_arch_isa_flags
,
11253 cpu_arch
[j
].flags
);
11258 if (j
>= ARRAY_SIZE (cpu_arch
))
11260 /* Disable an ISA extension. */
11261 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11262 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
11264 i386_cpu_flags flags
;
11266 flags
= cpu_flags_and_not (cpu_arch_flags
,
11267 cpu_noarch
[j
].flags
);
11268 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11270 if (cpu_sub_arch_name
)
11272 char *name
= cpu_sub_arch_name
;
11273 cpu_sub_arch_name
= concat (arch
,
11274 (const char *) NULL
);
11278 cpu_sub_arch_name
= xstrdup (arch
);
11279 cpu_arch_flags
= flags
;
11280 cpu_arch_isa_flags
= flags
;
11285 if (j
>= ARRAY_SIZE (cpu_noarch
))
11286 j
= ARRAY_SIZE (cpu_arch
);
11289 if (j
>= ARRAY_SIZE (cpu_arch
))
11290 as_fatal (_("invalid -march= option: `%s'"), arg
);
11294 while (next
!= NULL
);
11300 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11301 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11303 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
11305 cpu_arch_tune_set
= 1;
11306 cpu_arch_tune
= cpu_arch
[j
].type
;
11307 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
11311 if (j
>= ARRAY_SIZE (cpu_arch
))
11312 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11315 case OPTION_MMNEMONIC
:
11316 if (strcasecmp (arg
, "att") == 0)
11317 intel_mnemonic
= 0;
11318 else if (strcasecmp (arg
, "intel") == 0)
11319 intel_mnemonic
= 1;
11321 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
11324 case OPTION_MSYNTAX
:
11325 if (strcasecmp (arg
, "att") == 0)
11327 else if (strcasecmp (arg
, "intel") == 0)
11330 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
11333 case OPTION_MINDEX_REG
:
11334 allow_index_reg
= 1;
11337 case OPTION_MNAKED_REG
:
11338 allow_naked_reg
= 1;
11341 case OPTION_MSSE2AVX
:
11345 case OPTION_MSSE_CHECK
:
11346 if (strcasecmp (arg
, "error") == 0)
11347 sse_check
= check_error
;
11348 else if (strcasecmp (arg
, "warning") == 0)
11349 sse_check
= check_warning
;
11350 else if (strcasecmp (arg
, "none") == 0)
11351 sse_check
= check_none
;
11353 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
11356 case OPTION_MOPERAND_CHECK
:
11357 if (strcasecmp (arg
, "error") == 0)
11358 operand_check
= check_error
;
11359 else if (strcasecmp (arg
, "warning") == 0)
11360 operand_check
= check_warning
;
11361 else if (strcasecmp (arg
, "none") == 0)
11362 operand_check
= check_none
;
11364 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
11367 case OPTION_MAVXSCALAR
:
11368 if (strcasecmp (arg
, "128") == 0)
11369 avxscalar
= vex128
;
11370 else if (strcasecmp (arg
, "256") == 0)
11371 avxscalar
= vex256
;
11373 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
11376 case OPTION_MVEXWIG
:
11377 if (strcmp (arg
, "0") == 0)
11379 else if (strcmp (arg
, "1") == 0)
11382 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
11385 case OPTION_MADD_BND_PREFIX
:
11386 add_bnd_prefix
= 1;
11389 case OPTION_MEVEXLIG
:
11390 if (strcmp (arg
, "128") == 0)
11391 evexlig
= evexl128
;
11392 else if (strcmp (arg
, "256") == 0)
11393 evexlig
= evexl256
;
11394 else if (strcmp (arg
, "512") == 0)
11395 evexlig
= evexl512
;
11397 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
11400 case OPTION_MEVEXRCIG
:
11401 if (strcmp (arg
, "rne") == 0)
11403 else if (strcmp (arg
, "rd") == 0)
11405 else if (strcmp (arg
, "ru") == 0)
11407 else if (strcmp (arg
, "rz") == 0)
11410 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
11413 case OPTION_MEVEXWIG
:
11414 if (strcmp (arg
, "0") == 0)
11416 else if (strcmp (arg
, "1") == 0)
11419 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
11422 # if defined (TE_PE) || defined (TE_PEP)
11423 case OPTION_MBIG_OBJ
:
11428 case OPTION_MOMIT_LOCK_PREFIX
:
11429 if (strcasecmp (arg
, "yes") == 0)
11430 omit_lock_prefix
= 1;
11431 else if (strcasecmp (arg
, "no") == 0)
11432 omit_lock_prefix
= 0;
11434 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
11437 case OPTION_MFENCE_AS_LOCK_ADD
:
11438 if (strcasecmp (arg
, "yes") == 0)
11440 else if (strcasecmp (arg
, "no") == 0)
11443 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
11446 case OPTION_MRELAX_RELOCATIONS
:
11447 if (strcasecmp (arg
, "yes") == 0)
11448 generate_relax_relocations
= 1;
11449 else if (strcasecmp (arg
, "no") == 0)
11450 generate_relax_relocations
= 0;
11452 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
11455 case OPTION_MAMD64
:
11459 case OPTION_MINTEL64
:
11467 /* Turn off -Os. */
11468 optimize_for_space
= 0;
11470 else if (*arg
== 's')
11472 optimize_for_space
= 1;
11473 /* Turn on all encoding optimizations. */
11474 optimize
= INT_MAX
;
11478 optimize
= atoi (arg
);
11479 /* Turn off -Os. */
11480 optimize_for_space
= 0;
11490 #define MESSAGE_TEMPLATE \
11494 output_message (FILE *stream
, char *p
, char *message
, char *start
,
11495 int *left_p
, const char *name
, int len
)
11497 int size
= sizeof (MESSAGE_TEMPLATE
);
11498 int left
= *left_p
;
11500 /* Reserve 2 spaces for ", " or ",\0" */
11503 /* Check if there is any room. */
11511 p
= mempcpy (p
, name
, len
);
11515 /* Output the current message now and start a new one. */
11518 fprintf (stream
, "%s\n", message
);
11520 left
= size
- (start
- message
) - len
- 2;
11522 gas_assert (left
>= 0);
11524 p
= mempcpy (p
, name
, len
);
11532 show_arch (FILE *stream
, int ext
, int check
)
11534 static char message
[] = MESSAGE_TEMPLATE
;
11535 char *start
= message
+ 27;
11537 int size
= sizeof (MESSAGE_TEMPLATE
);
11544 left
= size
- (start
- message
);
11545 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11547 /* Should it be skipped? */
11548 if (cpu_arch
[j
].skip
)
11551 name
= cpu_arch
[j
].name
;
11552 len
= cpu_arch
[j
].len
;
11555 /* It is an extension. Skip if we aren't asked to show it. */
11566 /* It is an processor. Skip if we show only extension. */
11569 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11571 /* It is an impossible processor - skip. */
11575 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11578 /* Display disabled extensions. */
11580 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11582 name
= cpu_noarch
[j
].name
;
11583 len
= cpu_noarch
[j
].len
;
11584 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11589 fprintf (stream
, "%s\n", message
);
11593 md_show_usage (FILE *stream
)
11595 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11596 fprintf (stream
, _("\
11598 -V print assembler version number\n\
11601 fprintf (stream
, _("\
11602 -n Do not optimize code alignment\n\
11603 -q quieten some warnings\n"));
11604 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11605 fprintf (stream
, _("\
11608 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11609 || defined (TE_PE) || defined (TE_PEP))
11610 fprintf (stream
, _("\
11611 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11613 #ifdef SVR4_COMMENT_CHARS
11614 fprintf (stream
, _("\
11615 --divide do not treat `/' as a comment character\n"));
11617 fprintf (stream
, _("\
11618 --divide ignored\n"));
11620 fprintf (stream
, _("\
11621 -march=CPU[,+EXTENSION...]\n\
11622 generate code for CPU and EXTENSION, CPU is one of:\n"));
11623 show_arch (stream
, 0, 1);
11624 fprintf (stream
, _("\
11625 EXTENSION is combination of:\n"));
11626 show_arch (stream
, 1, 0);
11627 fprintf (stream
, _("\
11628 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11629 show_arch (stream
, 0, 0);
11630 fprintf (stream
, _("\
11631 -msse2avx encode SSE instructions with VEX prefix\n"));
11632 fprintf (stream
, _("\
11633 -msse-check=[none|error|warning] (default: warning)\n\
11634 check SSE instructions\n"));
11635 fprintf (stream
, _("\
11636 -moperand-check=[none|error|warning] (default: warning)\n\
11637 check operand combinations for validity\n"));
11638 fprintf (stream
, _("\
11639 -mavxscalar=[128|256] (default: 128)\n\
11640 encode scalar AVX instructions with specific vector\n\
11642 fprintf (stream
, _("\
11643 -mvexwig=[0|1] (default: 0)\n\
11644 encode VEX instructions with specific VEX.W value\n\
11645 for VEX.W bit ignored instructions\n"));
11646 fprintf (stream
, _("\
11647 -mevexlig=[128|256|512] (default: 128)\n\
11648 encode scalar EVEX instructions with specific vector\n\
11650 fprintf (stream
, _("\
11651 -mevexwig=[0|1] (default: 0)\n\
11652 encode EVEX instructions with specific EVEX.W value\n\
11653 for EVEX.W bit ignored instructions\n"));
11654 fprintf (stream
, _("\
11655 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11656 encode EVEX instructions with specific EVEX.RC value\n\
11657 for SAE-only ignored instructions\n"));
11658 fprintf (stream
, _("\
11659 -mmnemonic=[att|intel] "));
11660 if (SYSV386_COMPAT
)
11661 fprintf (stream
, _("(default: att)\n"));
11663 fprintf (stream
, _("(default: intel)\n"));
11664 fprintf (stream
, _("\
11665 use AT&T/Intel mnemonic\n"));
11666 fprintf (stream
, _("\
11667 -msyntax=[att|intel] (default: att)\n\
11668 use AT&T/Intel syntax\n"));
11669 fprintf (stream
, _("\
11670 -mindex-reg support pseudo index registers\n"));
11671 fprintf (stream
, _("\
11672 -mnaked-reg don't require `%%' prefix for registers\n"));
11673 fprintf (stream
, _("\
11674 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11675 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11676 fprintf (stream
, _("\
11677 -mshared disable branch optimization for shared code\n"));
11678 fprintf (stream
, _("\
11679 -mx86-used-note=[no|yes] "));
11680 if (DEFAULT_X86_USED_NOTE
)
11681 fprintf (stream
, _("(default: yes)\n"));
11683 fprintf (stream
, _("(default: no)\n"));
11684 fprintf (stream
, _("\
11685 generate x86 used ISA and feature properties\n"));
11687 #if defined (TE_PE) || defined (TE_PEP)
11688 fprintf (stream
, _("\
11689 -mbig-obj generate big object files\n"));
11691 fprintf (stream
, _("\
11692 -momit-lock-prefix=[no|yes] (default: no)\n\
11693 strip all lock prefixes\n"));
11694 fprintf (stream
, _("\
11695 -mfence-as-lock-add=[no|yes] (default: no)\n\
11696 encode lfence, mfence and sfence as\n\
11697 lock addl $0x0, (%%{re}sp)\n"));
11698 fprintf (stream
, _("\
11699 -mrelax-relocations=[no|yes] "));
11700 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
11701 fprintf (stream
, _("(default: yes)\n"));
11703 fprintf (stream
, _("(default: no)\n"));
11704 fprintf (stream
, _("\
11705 generate relax relocations\n"));
11706 fprintf (stream
, _("\
11707 -mamd64 accept only AMD64 ISA [default]\n"));
11708 fprintf (stream
, _("\
11709 -mintel64 accept only Intel64 ISA\n"));
11712 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11713 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11714 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11716 /* Pick the target format to use. */
11719 i386_target_format (void)
11721 if (!strncmp (default_arch
, "x86_64", 6))
11723 update_code_flag (CODE_64BIT
, 1);
11724 if (default_arch
[6] == '\0')
11725 x86_elf_abi
= X86_64_ABI
;
11727 x86_elf_abi
= X86_64_X32_ABI
;
11729 else if (!strcmp (default_arch
, "i386"))
11730 update_code_flag (CODE_32BIT
, 1);
11731 else if (!strcmp (default_arch
, "iamcu"))
11733 update_code_flag (CODE_32BIT
, 1);
11734 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11736 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11737 cpu_arch_name
= "iamcu";
11738 cpu_sub_arch_name
= NULL
;
11739 cpu_arch_flags
= iamcu_flags
;
11740 cpu_arch_isa
= PROCESSOR_IAMCU
;
11741 cpu_arch_isa_flags
= iamcu_flags
;
11742 if (!cpu_arch_tune_set
)
11744 cpu_arch_tune
= cpu_arch_isa
;
11745 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11748 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11749 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11753 as_fatal (_("unknown architecture"));
11755 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11756 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11757 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11758 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11760 switch (OUTPUT_FLAVOR
)
11762 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11763 case bfd_target_aout_flavour
:
11764 return AOUT_TARGET_FORMAT
;
11766 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11767 # if defined (TE_PE) || defined (TE_PEP)
11768 case bfd_target_coff_flavour
:
11769 if (flag_code
== CODE_64BIT
)
11770 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11773 # elif defined (TE_GO32)
11774 case bfd_target_coff_flavour
:
11775 return "coff-go32";
11777 case bfd_target_coff_flavour
:
11778 return "coff-i386";
11781 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11782 case bfd_target_elf_flavour
:
11784 const char *format
;
11786 switch (x86_elf_abi
)
11789 format
= ELF_TARGET_FORMAT
;
11792 use_rela_relocations
= 1;
11794 format
= ELF_TARGET_FORMAT64
;
11796 case X86_64_X32_ABI
:
11797 use_rela_relocations
= 1;
11799 disallow_64bit_reloc
= 1;
11800 format
= ELF_TARGET_FORMAT32
;
11803 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11805 if (x86_elf_abi
!= X86_64_ABI
)
11806 as_fatal (_("Intel L1OM is 64bit only"));
11807 return ELF_TARGET_L1OM_FORMAT
;
11809 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11811 if (x86_elf_abi
!= X86_64_ABI
)
11812 as_fatal (_("Intel K1OM is 64bit only"));
11813 return ELF_TARGET_K1OM_FORMAT
;
11815 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11817 if (x86_elf_abi
!= I386_ABI
)
11818 as_fatal (_("Intel MCU is 32bit only"));
11819 return ELF_TARGET_IAMCU_FORMAT
;
11825 #if defined (OBJ_MACH_O)
11826 case bfd_target_mach_o_flavour
:
11827 if (flag_code
== CODE_64BIT
)
11829 use_rela_relocations
= 1;
11831 return "mach-o-x86-64";
11834 return "mach-o-i386";
11842 #endif /* OBJ_MAYBE_ more than one */
11845 md_undefined_symbol (char *name
)
11847 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11848 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11849 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11850 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11854 if (symbol_find (name
))
11855 as_bad (_("GOT already in symbol table"));
11856 GOT_symbol
= symbol_new (name
, undefined_section
,
11857 (valueT
) 0, &zero_address_frag
);
11864 /* Round up a section size to the appropriate boundary. */
11867 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11869 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11870 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11872 /* For a.out, force the section size to be aligned. If we don't do
11873 this, BFD will align it for us, but it will not write out the
11874 final bytes of the section. This may be a bug in BFD, but it is
11875 easier to fix it here since that is how the other a.out targets
11879 align
= bfd_get_section_alignment (stdoutput
, segment
);
11880 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11887 /* On the i386, PC-relative offsets are relative to the start of the
11888 next instruction. That is, the address of the offset, plus its
11889 size, since the offset is always the last part of the insn. */
11892 md_pcrel_from (fixS
*fixP
)
11894 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11900 s_bss (int ignore ATTRIBUTE_UNUSED
)
11904 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11906 obj_elf_section_change_hook ();
11908 temp
= get_absolute_expression ();
11909 subseg_set (bss_section
, (subsegT
) temp
);
11910 demand_empty_rest_of_line ();
11916 i386_validate_fix (fixS
*fixp
)
11918 if (fixp
->fx_subsy
)
11920 if (fixp
->fx_subsy
== GOT_symbol
)
11922 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11926 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11927 if (fixp
->fx_tcbit2
)
11928 fixp
->fx_r_type
= (fixp
->fx_tcbit
11929 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11930 : BFD_RELOC_X86_64_GOTPCRELX
);
11933 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11938 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11940 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11942 fixp
->fx_subsy
= 0;
11945 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11946 else if (!object_64bit
)
11948 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11949 && fixp
->fx_tcbit2
)
11950 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11956 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11959 bfd_reloc_code_real_type code
;
11961 switch (fixp
->fx_r_type
)
11963 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11964 case BFD_RELOC_SIZE32
:
11965 case BFD_RELOC_SIZE64
:
11966 if (S_IS_DEFINED (fixp
->fx_addsy
)
11967 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
11969 /* Resolve size relocation against local symbol to size of
11970 the symbol plus addend. */
11971 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
11972 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
11973 && !fits_in_unsigned_long (value
))
11974 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11975 _("symbol size computation overflow"));
11976 fixp
->fx_addsy
= NULL
;
11977 fixp
->fx_subsy
= NULL
;
11978 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
11982 /* Fall through. */
11984 case BFD_RELOC_X86_64_PLT32
:
11985 case BFD_RELOC_X86_64_GOT32
:
11986 case BFD_RELOC_X86_64_GOTPCREL
:
11987 case BFD_RELOC_X86_64_GOTPCRELX
:
11988 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11989 case BFD_RELOC_386_PLT32
:
11990 case BFD_RELOC_386_GOT32
:
11991 case BFD_RELOC_386_GOT32X
:
11992 case BFD_RELOC_386_GOTOFF
:
11993 case BFD_RELOC_386_GOTPC
:
11994 case BFD_RELOC_386_TLS_GD
:
11995 case BFD_RELOC_386_TLS_LDM
:
11996 case BFD_RELOC_386_TLS_LDO_32
:
11997 case BFD_RELOC_386_TLS_IE_32
:
11998 case BFD_RELOC_386_TLS_IE
:
11999 case BFD_RELOC_386_TLS_GOTIE
:
12000 case BFD_RELOC_386_TLS_LE_32
:
12001 case BFD_RELOC_386_TLS_LE
:
12002 case BFD_RELOC_386_TLS_GOTDESC
:
12003 case BFD_RELOC_386_TLS_DESC_CALL
:
12004 case BFD_RELOC_X86_64_TLSGD
:
12005 case BFD_RELOC_X86_64_TLSLD
:
12006 case BFD_RELOC_X86_64_DTPOFF32
:
12007 case BFD_RELOC_X86_64_DTPOFF64
:
12008 case BFD_RELOC_X86_64_GOTTPOFF
:
12009 case BFD_RELOC_X86_64_TPOFF32
:
12010 case BFD_RELOC_X86_64_TPOFF64
:
12011 case BFD_RELOC_X86_64_GOTOFF64
:
12012 case BFD_RELOC_X86_64_GOTPC32
:
12013 case BFD_RELOC_X86_64_GOT64
:
12014 case BFD_RELOC_X86_64_GOTPCREL64
:
12015 case BFD_RELOC_X86_64_GOTPC64
:
12016 case BFD_RELOC_X86_64_GOTPLT64
:
12017 case BFD_RELOC_X86_64_PLTOFF64
:
12018 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12019 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12020 case BFD_RELOC_RVA
:
12021 case BFD_RELOC_VTABLE_ENTRY
:
12022 case BFD_RELOC_VTABLE_INHERIT
:
12024 case BFD_RELOC_32_SECREL
:
12026 code
= fixp
->fx_r_type
;
12028 case BFD_RELOC_X86_64_32S
:
12029 if (!fixp
->fx_pcrel
)
12031 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
12032 code
= fixp
->fx_r_type
;
12035 /* Fall through. */
12037 if (fixp
->fx_pcrel
)
12039 switch (fixp
->fx_size
)
12042 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12043 _("can not do %d byte pc-relative relocation"),
12045 code
= BFD_RELOC_32_PCREL
;
12047 case 1: code
= BFD_RELOC_8_PCREL
; break;
12048 case 2: code
= BFD_RELOC_16_PCREL
; break;
12049 case 4: code
= BFD_RELOC_32_PCREL
; break;
12051 case 8: code
= BFD_RELOC_64_PCREL
; break;
12057 switch (fixp
->fx_size
)
12060 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12061 _("can not do %d byte relocation"),
12063 code
= BFD_RELOC_32
;
12065 case 1: code
= BFD_RELOC_8
; break;
12066 case 2: code
= BFD_RELOC_16
; break;
12067 case 4: code
= BFD_RELOC_32
; break;
12069 case 8: code
= BFD_RELOC_64
; break;
12076 if ((code
== BFD_RELOC_32
12077 || code
== BFD_RELOC_32_PCREL
12078 || code
== BFD_RELOC_X86_64_32S
)
12080 && fixp
->fx_addsy
== GOT_symbol
)
12083 code
= BFD_RELOC_386_GOTPC
;
12085 code
= BFD_RELOC_X86_64_GOTPC32
;
12087 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
12089 && fixp
->fx_addsy
== GOT_symbol
)
12091 code
= BFD_RELOC_X86_64_GOTPC64
;
12094 rel
= XNEW (arelent
);
12095 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
12096 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12098 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12100 if (!use_rela_relocations
)
12102 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
12103 vtable entry to be used in the relocation's section offset. */
12104 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12105 rel
->address
= fixp
->fx_offset
;
12106 #if defined (OBJ_COFF) && defined (TE_PE)
12107 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
12108 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
12113 /* Use the rela in 64bit mode. */
12116 if (disallow_64bit_reloc
)
12119 case BFD_RELOC_X86_64_DTPOFF64
:
12120 case BFD_RELOC_X86_64_TPOFF64
:
12121 case BFD_RELOC_64_PCREL
:
12122 case BFD_RELOC_X86_64_GOTOFF64
:
12123 case BFD_RELOC_X86_64_GOT64
:
12124 case BFD_RELOC_X86_64_GOTPCREL64
:
12125 case BFD_RELOC_X86_64_GOTPC64
:
12126 case BFD_RELOC_X86_64_GOTPLT64
:
12127 case BFD_RELOC_X86_64_PLTOFF64
:
12128 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12129 _("cannot represent relocation type %s in x32 mode"),
12130 bfd_get_reloc_code_name (code
));
12136 if (!fixp
->fx_pcrel
)
12137 rel
->addend
= fixp
->fx_offset
;
12141 case BFD_RELOC_X86_64_PLT32
:
12142 case BFD_RELOC_X86_64_GOT32
:
12143 case BFD_RELOC_X86_64_GOTPCREL
:
12144 case BFD_RELOC_X86_64_GOTPCRELX
:
12145 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12146 case BFD_RELOC_X86_64_TLSGD
:
12147 case BFD_RELOC_X86_64_TLSLD
:
12148 case BFD_RELOC_X86_64_GOTTPOFF
:
12149 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12150 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12151 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
12154 rel
->addend
= (section
->vma
12156 + fixp
->fx_addnumber
12157 + md_pcrel_from (fixp
));
12162 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12163 if (rel
->howto
== NULL
)
12165 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12166 _("cannot represent relocation type %s"),
12167 bfd_get_reloc_code_name (code
));
12168 /* Set howto to a garbage value so that we can keep going. */
12169 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
12170 gas_assert (rel
->howto
!= NULL
);
12176 #include "tc-i386-intel.c"
12179 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
12181 int saved_naked_reg
;
12182 char saved_register_dot
;
12184 saved_naked_reg
= allow_naked_reg
;
12185 allow_naked_reg
= 1;
12186 saved_register_dot
= register_chars
['.'];
12187 register_chars
['.'] = '.';
12188 allow_pseudo_reg
= 1;
12189 expression_and_evaluate (exp
);
12190 allow_pseudo_reg
= 0;
12191 register_chars
['.'] = saved_register_dot
;
12192 allow_naked_reg
= saved_naked_reg
;
12194 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
12196 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
12198 exp
->X_op
= O_constant
;
12199 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
12200 .dw2_regnum
[flag_code
>> 1];
12203 exp
->X_op
= O_illegal
;
12208 tc_x86_frame_initial_instructions (void)
12210 static unsigned int sp_regno
[2];
12212 if (!sp_regno
[flag_code
>> 1])
12214 char *saved_input
= input_line_pointer
;
12215 char sp
[][4] = {"esp", "rsp"};
12218 input_line_pointer
= sp
[flag_code
>> 1];
12219 tc_x86_parse_to_dw2regnum (&exp
);
12220 gas_assert (exp
.X_op
== O_constant
);
12221 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
12222 input_line_pointer
= saved_input
;
12225 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
12226 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
12230 x86_dwarf2_addr_size (void)
12232 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12233 if (x86_elf_abi
== X86_64_X32_ABI
)
12236 return bfd_arch_bits_per_address (stdoutput
) / 8;
12240 i386_elf_section_type (const char *str
, size_t len
)
12242 if (flag_code
== CODE_64BIT
12243 && len
== sizeof ("unwind") - 1
12244 && strncmp (str
, "unwind", 6) == 0)
12245 return SHT_X86_64_UNWIND
;
12252 i386_solaris_fix_up_eh_frame (segT sec
)
12254 if (flag_code
== CODE_64BIT
)
12255 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
12261 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
12265 exp
.X_op
= O_secrel
;
12266 exp
.X_add_symbol
= symbol
;
12267 exp
.X_add_number
= 0;
12268 emit_expr (&exp
, size
);
12272 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12273 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12276 x86_64_section_letter (int letter
, const char **ptr_msg
)
12278 if (flag_code
== CODE_64BIT
)
12281 return SHF_X86_64_LARGE
;
12283 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12286 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
12291 x86_64_section_word (char *str
, size_t len
)
12293 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
12294 return SHF_X86_64_LARGE
;
12300 handle_large_common (int small ATTRIBUTE_UNUSED
)
12302 if (flag_code
!= CODE_64BIT
)
12304 s_comm_internal (0, elf_common_parse
);
12305 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12309 static segT lbss_section
;
12310 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
12311 asection
*saved_bss_section
= bss_section
;
12313 if (lbss_section
== NULL
)
12315 flagword applicable
;
12316 segT seg
= now_seg
;
12317 subsegT subseg
= now_subseg
;
12319 /* The .lbss section is for local .largecomm symbols. */
12320 lbss_section
= subseg_new (".lbss", 0);
12321 applicable
= bfd_applicable_section_flags (stdoutput
);
12322 bfd_set_section_flags (stdoutput
, lbss_section
,
12323 applicable
& SEC_ALLOC
);
12324 seg_info (lbss_section
)->bss
= 1;
12326 subseg_set (seg
, subseg
);
12329 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
12330 bss_section
= lbss_section
;
12332 s_comm_internal (0, elf_common_parse
);
12334 elf_com_section_ptr
= saved_com_section_ptr
;
12335 bss_section
= saved_bss_section
;
12338 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */