1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
136 unsigned int negated
; /* turn off indicated flags. */
140 static void update_code_flag (int, int);
141 static void set_code_flag (int);
142 static void set_16bit_gcc_code_flag (int);
143 static void set_intel_syntax (int);
144 static void set_intel_mnemonic (int);
145 static void set_allow_index_reg (int);
146 static void set_check (int);
147 static void set_cpu_arch (int);
149 static void pe_directive_secrel (int);
151 static void signed_cons (int);
152 static char *output_invalid (int c
);
153 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
155 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
157 static int i386_att_operand (char *);
158 static int i386_intel_operand (char *, int);
159 static int i386_intel_simplify (expressionS
*);
160 static int i386_intel_parse_name (const char *, expressionS
*);
161 static const reg_entry
*parse_register (char *, char **);
162 static char *parse_insn (char *, char *);
163 static char *parse_operands (char *, const char *);
164 static void swap_operands (void);
165 static void swap_2_operands (int, int);
166 static void optimize_imm (void);
167 static void optimize_disp (void);
168 static const insn_template
*match_template (void);
169 static int check_string (void);
170 static int process_suffix (void);
171 static int check_byte_reg (void);
172 static int check_long_reg (void);
173 static int check_qword_reg (void);
174 static int check_word_reg (void);
175 static int finalize_imm (void);
176 static int process_operands (void);
177 static const seg_entry
*build_modrm_byte (void);
178 static void output_insn (void);
179 static void output_imm (fragS
*, offsetT
);
180 static void output_disp (fragS
*, offsetT
);
182 static void s_bss (int);
184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
188 static const char *default_arch
= DEFAULT_ARCH
;
190 /* This struct describes rounding control and SAE in the instruction. */
204 static struct RC_Operation rc_op
;
206 /* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209 struct Mask_Operation
211 const reg_entry
*mask
;
212 unsigned int zeroing
;
213 /* The operand where this operation is associated. */
217 static struct Mask_Operation mask_op
;
219 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
221 struct Broadcast_Operation
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
226 /* Index of broadcasted operand. */
230 static struct Broadcast_Operation broadcast_op
;
235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes
[4];
238 /* Destination or source register specifier. */
239 const reg_entry
*register_specifier
;
242 /* 'md_assemble ()' gathers together information and puts it into a
249 const reg_entry
*regs
;
254 operand_size_mismatch
,
255 operand_type_mismatch
,
256 register_type_mismatch
,
257 number_of_operands_mismatch
,
258 invalid_instruction_suffix
,
261 unsupported_with_intel_mnemonic
,
264 invalid_vsib_address
,
265 invalid_vector_register_set
,
266 unsupported_vector_index_register
,
267 unsupported_broadcast
,
268 broadcast_not_on_src_operand
,
271 mask_not_on_destination
,
274 rc_sae_operand_not_last_imm
,
275 invalid_register_operand
,
281 /* TM holds the template for the insn were currently assembling. */
284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
288 /* OPERANDS gives the number of given operands. */
289 unsigned int operands
;
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
294 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
296 /* TYPES [i] is the type (see above #defines) which tells us how to
297 use OP[i] for the corresponding operand. */
298 i386_operand_type types
[MAX_OPERANDS
];
300 /* Displacement expression, immediate expression, or register for each
302 union i386_op op
[MAX_OPERANDS
];
304 /* Flags for operands. */
305 unsigned int flags
[MAX_OPERANDS
];
306 #define Operand_PCrel 1
308 /* Relocation type for operand */
309 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry
*base_reg
;
314 const reg_entry
*index_reg
;
315 unsigned int log2_scale_factor
;
317 /* SEG gives the seg_entries of this insn. They are zero unless
318 explicit segment overrides are given. */
319 const seg_entry
*seg
[2];
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes
;
324 unsigned char prefix
[MAX_PREFIXES
];
326 /* RM and SIB are the modrm byte and the sib byte where the
327 addressing modes of this insn are encoded. */
334 /* Masking attributes. */
335 struct Mask_Operation
*mask
;
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation
*rounding
;
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation
*broadcast
;
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift
;
346 /* Swap operand in encoding. */
347 unsigned int swap_operand
;
349 /* Prefer 8bit or 32bit displacement in encoding. */
352 disp_encoding_default
= 0,
358 const char *rep_prefix
;
361 const char *hle_prefix
;
363 /* Have BND prefix. */
364 const char *bnd_prefix
;
366 /* Need VREX to support upper 16 registers. */
370 enum i386_error error
;
373 typedef struct _i386_insn i386_insn
;
375 /* Link RC type with corresponding string, that'll be looked for in
384 static const struct RC_name RC_NamesTable
[] =
386 { rne
, STRING_COMMA_LEN ("rn-sae") },
387 { rd
, STRING_COMMA_LEN ("rd-sae") },
388 { ru
, STRING_COMMA_LEN ("ru-sae") },
389 { rz
, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly
, STRING_COMMA_LEN ("sae") },
393 /* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
395 const char extra_symbol_chars
[] = "*%-([{"
404 #if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
406 && !defined (TE_GNU) \
407 && !defined (TE_LINUX) \
408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
410 && !defined (TE_FreeBSD) \
411 && !defined (TE_DragonFly) \
412 && !defined (TE_NetBSD)))
413 /* This array holds the chars that always start a comment. If the
414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416 const char *i386_comment_chars
= "#/";
417 #define SVR4_COMMENT_CHARS 1
418 #define PREFIX_SEPARATOR '\\'
421 const char *i386_comment_chars
= "#";
422 #define PREFIX_SEPARATOR '/'
425 /* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
429 first line of the input file. This is because the compiler outputs
430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
432 '/' isn't otherwise defined. */
433 const char line_comment_chars
[] = "#/";
435 const char line_separator_chars
[] = ";";
437 /* Chars that can be used to separate mant from exp in floating point
439 const char EXP_CHARS
[] = "eE";
441 /* Chars that mean this number is a floating point constant
444 const char FLT_CHARS
[] = "fFdDxX";
446 /* Tables for lexical analysis. */
447 static char mnemonic_chars
[256];
448 static char register_chars
[256];
449 static char operand_chars
[256];
450 static char identifier_chars
[256];
451 static char digit_chars
[256];
453 /* Lexical macros. */
454 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455 #define is_operand_char(x) (operand_chars[(unsigned char) x])
456 #define is_register_char(x) (register_chars[(unsigned char) x])
457 #define is_space_char(x) ((x) == ' ')
458 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459 #define is_digit_char(x) (digit_chars[(unsigned char) x])
461 /* All non-digit non-letter characters that may occur in an operand. */
462 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
464 /* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
467 assembler instruction). */
468 static char save_stack
[32];
469 static char *save_stack_p
;
470 #define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472 #define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
475 /* The instruction we're assembling. */
478 /* Possible templates for current insn. */
479 static const templates
*current_templates
;
481 /* Per instruction expressionS buffers: max displacements & immediates. */
482 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
483 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
485 /* Current operand we are working on. */
486 static int this_operand
= -1;
488 /* We support four different modes. FLAG_CODE variable is used to distinguish
496 static enum flag_code flag_code
;
497 static unsigned int object_64bit
;
498 static unsigned int disallow_64bit_reloc
;
499 static int use_rela_relocations
= 0;
501 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
505 /* The ELF ABI to use. */
513 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
516 #if defined (TE_PE) || defined (TE_PEP)
517 /* Use big object file format. */
518 static int use_big_obj
= 0;
521 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
522 /* 1 if generating code for a shared library. */
523 static int shared
= 0;
526 /* 1 for intel syntax,
528 static int intel_syntax
= 0;
530 /* 1 for intel mnemonic,
531 0 if att mnemonic. */
532 static int intel_mnemonic
= !SYSV386_COMPAT
;
534 /* 1 if support old (<= 2.8.1) versions of gcc. */
535 static int old_gcc
= OLDGCC_COMPAT
;
537 /* 1 if pseudo registers are permitted. */
538 static int allow_pseudo_reg
= 0;
540 /* 1 if register prefix % not required. */
541 static int allow_naked_reg
= 0;
543 /* 1 if the assembler should add BND prefix for all control-tranferring
544 instructions supporting it, even if this prefix wasn't specified
546 static int add_bnd_prefix
= 0;
548 /* 1 if pseudo index register, eiz/riz, is allowed . */
549 static int allow_index_reg
= 0;
551 /* 1 if the assembler should ignore LOCK prefix, even if it was
552 specified explicitly. */
553 static int omit_lock_prefix
= 0;
555 static enum check_kind
561 sse_check
, operand_check
= check_warning
;
563 /* Register prefix used for error message. */
564 static const char *register_prefix
= "%";
566 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
567 leave, push, and pop instructions so that gcc has the same stack
568 frame as in 32 bit mode. */
569 static char stackop_size
= '\0';
571 /* Non-zero to optimize code alignment. */
572 int optimize_align_code
= 1;
574 /* Non-zero to quieten some warnings. */
575 static int quiet_warnings
= 0;
578 static const char *cpu_arch_name
= NULL
;
579 static char *cpu_sub_arch_name
= NULL
;
581 /* CPU feature flags. */
582 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
584 /* If we have selected a cpu we are generating instructions for. */
585 static int cpu_arch_tune_set
= 0;
587 /* Cpu we are generating instructions for. */
588 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
590 /* CPU feature flags of cpu we are generating instructions for. */
591 static i386_cpu_flags cpu_arch_tune_flags
;
593 /* CPU instruction set architecture used. */
594 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
596 /* CPU feature flags of instruction set architecture used. */
597 i386_cpu_flags cpu_arch_isa_flags
;
599 /* If set, conditional jumps are not automatically promoted to handle
600 larger than a byte offset. */
601 static unsigned int no_cond_jump_promotion
= 0;
603 /* Encode SSE instructions with VEX prefix. */
604 static unsigned int sse2avx
;
606 /* Encode scalar AVX instructions with specific vector length. */
613 /* Encode scalar EVEX LIG instructions with specific vector length. */
621 /* Encode EVEX WIG instructions with specific evex.w. */
628 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
629 static enum rc_type evexrcig
= rne
;
631 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
632 static symbolS
*GOT_symbol
;
634 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
635 unsigned int x86_dwarf2_return_column
;
637 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
638 int x86_cie_data_alignment
;
640 /* Interface to relax_segment.
641 There are 3 major relax states for 386 jump insns because the
642 different types of jumps add different sizes to frags when we're
643 figuring out what sort of jump to choose to reach a given label. */
646 #define UNCOND_JUMP 0
648 #define COND_JUMP86 2
653 #define SMALL16 (SMALL | CODE16)
655 #define BIG16 (BIG | CODE16)
659 #define INLINE __inline__
665 #define ENCODE_RELAX_STATE(type, size) \
666 ((relax_substateT) (((type) << 2) | (size)))
667 #define TYPE_FROM_RELAX_STATE(s) \
669 #define DISP_SIZE_FROM_RELAX_STATE(s) \
670 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
672 /* This table is used by relax_frag to promote short jumps to long
673 ones where necessary. SMALL (short) jumps may be promoted to BIG
674 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
675 don't allow a short jump in a 32 bit code segment to be promoted to
676 a 16 bit offset jump because it's slower (requires data size
677 prefix), and doesn't work, unless the destination is in the bottom
678 64k of the code segment (The top 16 bits of eip are zeroed). */
680 const relax_typeS md_relax_table
[] =
683 1) most positive reach of this state,
684 2) most negative reach of this state,
685 3) how many bytes this mode will have in the variable part of the frag
686 4) which index into the table to try if we can't fit into this one. */
688 /* UNCOND_JUMP states. */
689 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
690 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
691 /* dword jmp adds 4 bytes to frag:
692 0 extra opcode bytes, 4 displacement bytes. */
694 /* word jmp adds 2 byte2 to frag:
695 0 extra opcode bytes, 2 displacement bytes. */
698 /* COND_JUMP states. */
699 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
700 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
701 /* dword conditionals adds 5 bytes to frag:
702 1 extra opcode byte, 4 displacement bytes. */
704 /* word conditionals add 3 bytes to frag:
705 1 extra opcode byte, 2 displacement bytes. */
708 /* COND_JUMP86 states. */
709 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
710 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
711 /* dword conditionals adds 5 bytes to frag:
712 1 extra opcode byte, 4 displacement bytes. */
714 /* word conditionals add 4 bytes to frag:
715 1 displacement byte and a 3 byte long branch insn. */
719 static const arch_entry cpu_arch
[] =
721 /* Do not replace the first two entries - i386_target_format()
722 relies on them being there in this order. */
723 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
724 CPU_GENERIC32_FLAGS
, 0, 0 },
725 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
726 CPU_GENERIC64_FLAGS
, 0, 0 },
727 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
728 CPU_NONE_FLAGS
, 0, 0 },
729 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
730 CPU_I186_FLAGS
, 0, 0 },
731 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
732 CPU_I286_FLAGS
, 0, 0 },
733 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
734 CPU_I386_FLAGS
, 0, 0 },
735 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
736 CPU_I486_FLAGS
, 0, 0 },
737 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
738 CPU_I586_FLAGS
, 0, 0 },
739 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
740 CPU_I686_FLAGS
, 0, 0 },
741 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
742 CPU_I586_FLAGS
, 0, 0 },
743 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
744 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
745 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
746 CPU_P2_FLAGS
, 0, 0 },
747 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
748 CPU_P3_FLAGS
, 0, 0 },
749 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
750 CPU_P4_FLAGS
, 0, 0 },
751 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
752 CPU_CORE_FLAGS
, 0, 0 },
753 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
754 CPU_NOCONA_FLAGS
, 0, 0 },
755 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
756 CPU_CORE_FLAGS
, 1, 0 },
757 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
758 CPU_CORE_FLAGS
, 0, 0 },
759 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
760 CPU_CORE2_FLAGS
, 1, 0 },
761 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
762 CPU_CORE2_FLAGS
, 0, 0 },
763 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
764 CPU_COREI7_FLAGS
, 0, 0 },
765 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
766 CPU_L1OM_FLAGS
, 0, 0 },
767 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
768 CPU_K1OM_FLAGS
, 0, 0 },
769 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
770 CPU_IAMCU_FLAGS
, 0, 0 },
771 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
772 CPU_K6_FLAGS
, 0, 0 },
773 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
774 CPU_K6_2_FLAGS
, 0, 0 },
775 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
776 CPU_ATHLON_FLAGS
, 0, 0 },
777 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
778 CPU_K8_FLAGS
, 1, 0 },
779 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
780 CPU_K8_FLAGS
, 0, 0 },
781 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
782 CPU_K8_FLAGS
, 0, 0 },
783 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
784 CPU_AMDFAM10_FLAGS
, 0, 0 },
785 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
786 CPU_BDVER1_FLAGS
, 0, 0 },
787 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
788 CPU_BDVER2_FLAGS
, 0, 0 },
789 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
790 CPU_BDVER3_FLAGS
, 0, 0 },
791 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
792 CPU_BDVER4_FLAGS
, 0, 0 },
793 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
794 CPU_ZNVER1_FLAGS
, 0, 0 },
795 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
796 CPU_BTVER1_FLAGS
, 0, 0 },
797 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
798 CPU_BTVER2_FLAGS
, 0, 0 },
799 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
800 CPU_8087_FLAGS
, 0, 0 },
801 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
802 CPU_287_FLAGS
, 0, 0 },
803 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
804 CPU_387_FLAGS
, 0, 0 },
805 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
806 CPU_ANY87_FLAGS
, 0, 1 },
807 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
808 CPU_MMX_FLAGS
, 0, 0 },
809 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
810 CPU_3DNOWA_FLAGS
, 0, 1 },
811 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
812 CPU_SSE_FLAGS
, 0, 0 },
813 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
814 CPU_SSE2_FLAGS
, 0, 0 },
815 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
816 CPU_SSE3_FLAGS
, 0, 0 },
817 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
818 CPU_SSSE3_FLAGS
, 0, 0 },
819 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
820 CPU_SSE4_1_FLAGS
, 0, 0 },
821 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
822 CPU_SSE4_2_FLAGS
, 0, 0 },
823 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
824 CPU_SSE4_2_FLAGS
, 0, 0 },
825 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
826 CPU_ANY_SSE_FLAGS
, 0, 1 },
827 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
828 CPU_AVX_FLAGS
, 0, 0 },
829 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
830 CPU_AVX2_FLAGS
, 0, 0 },
831 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
832 CPU_AVX512F_FLAGS
, 0, 0 },
833 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
834 CPU_AVX512CD_FLAGS
, 0, 0 },
835 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
836 CPU_AVX512ER_FLAGS
, 0, 0 },
837 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
838 CPU_AVX512PF_FLAGS
, 0, 0 },
839 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
840 CPU_AVX512DQ_FLAGS
, 0, 0 },
841 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
842 CPU_AVX512BW_FLAGS
, 0, 0 },
843 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
844 CPU_AVX512VL_FLAGS
, 0, 0 },
845 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
846 CPU_ANY_AVX_FLAGS
, 0, 1 },
847 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
848 CPU_VMX_FLAGS
, 0, 0 },
849 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
850 CPU_VMFUNC_FLAGS
, 0, 0 },
851 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
852 CPU_SMX_FLAGS
, 0, 0 },
853 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
854 CPU_XSAVE_FLAGS
, 0, 0 },
855 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
856 CPU_XSAVEOPT_FLAGS
, 0, 0 },
857 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
858 CPU_XSAVEC_FLAGS
, 0, 0 },
859 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
860 CPU_XSAVES_FLAGS
, 0, 0 },
861 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
862 CPU_AES_FLAGS
, 0, 0 },
863 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
864 CPU_PCLMUL_FLAGS
, 0, 0 },
865 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
866 CPU_PCLMUL_FLAGS
, 1, 0 },
867 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
868 CPU_FSGSBASE_FLAGS
, 0, 0 },
869 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
870 CPU_RDRND_FLAGS
, 0, 0 },
871 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
872 CPU_F16C_FLAGS
, 0, 0 },
873 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
874 CPU_BMI2_FLAGS
, 0, 0 },
875 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
876 CPU_FMA_FLAGS
, 0, 0 },
877 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
878 CPU_FMA4_FLAGS
, 0, 0 },
879 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
880 CPU_XOP_FLAGS
, 0, 0 },
881 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
882 CPU_LWP_FLAGS
, 0, 0 },
883 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
884 CPU_MOVBE_FLAGS
, 0, 0 },
885 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
886 CPU_CX16_FLAGS
, 0, 0 },
887 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
888 CPU_EPT_FLAGS
, 0, 0 },
889 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
890 CPU_LZCNT_FLAGS
, 0, 0 },
891 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
892 CPU_HLE_FLAGS
, 0, 0 },
893 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
894 CPU_RTM_FLAGS
, 0, 0 },
895 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
896 CPU_INVPCID_FLAGS
, 0, 0 },
897 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
898 CPU_CLFLUSH_FLAGS
, 0, 0 },
899 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
900 CPU_NOP_FLAGS
, 0, 0 },
901 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
902 CPU_SYSCALL_FLAGS
, 0, 0 },
903 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
904 CPU_RDTSCP_FLAGS
, 0, 0 },
905 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
906 CPU_3DNOW_FLAGS
, 0, 0 },
907 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
908 CPU_3DNOWA_FLAGS
, 0, 0 },
909 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
910 CPU_PADLOCK_FLAGS
, 0, 0 },
911 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
912 CPU_SVME_FLAGS
, 1, 0 },
913 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
914 CPU_SVME_FLAGS
, 0, 0 },
915 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
916 CPU_SSE4A_FLAGS
, 0, 0 },
917 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
918 CPU_ABM_FLAGS
, 0, 0 },
919 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
920 CPU_BMI_FLAGS
, 0, 0 },
921 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
922 CPU_TBM_FLAGS
, 0, 0 },
923 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
924 CPU_ADX_FLAGS
, 0, 0 },
925 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
926 CPU_RDSEED_FLAGS
, 0, 0 },
927 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
928 CPU_PRFCHW_FLAGS
, 0, 0 },
929 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
930 CPU_SMAP_FLAGS
, 0, 0 },
931 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
932 CPU_MPX_FLAGS
, 0, 0 },
933 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
934 CPU_SHA_FLAGS
, 0, 0 },
935 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
936 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
937 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
938 CPU_PREFETCHWT1_FLAGS
, 0, 0 },
939 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
940 CPU_SE1_FLAGS
, 0, 0 },
941 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
942 CPU_CLWB_FLAGS
, 0, 0 },
943 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
944 CPU_PCOMMIT_FLAGS
, 0, 0 },
945 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
946 CPU_AVX512IFMA_FLAGS
, 0, 0 },
947 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
948 CPU_AVX512VBMI_FLAGS
, 0, 0 },
949 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
950 CPU_CLZERO_FLAGS
, 0, 0 },
951 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
952 CPU_MWAITX_FLAGS
, 0, 0 },
956 /* Like s_lcomm_internal in gas/read.c but the alignment string
957 is allowed to be optional. */
960 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
967 && *input_line_pointer
== ',')
969 align
= parse_align (needs_align
- 1);
971 if (align
== (addressT
) -1)
986 bss_alloc (symbolP
, size
, align
);
991 pe_lcomm (int needs_align
)
993 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
997 const pseudo_typeS md_pseudo_table
[] =
999 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1000 {"align", s_align_bytes
, 0},
1002 {"align", s_align_ptwo
, 0},
1004 {"arch", set_cpu_arch
, 0},
1008 {"lcomm", pe_lcomm
, 1},
1010 {"ffloat", float_cons
, 'f'},
1011 {"dfloat", float_cons
, 'd'},
1012 {"tfloat", float_cons
, 'x'},
1014 {"slong", signed_cons
, 4},
1015 {"noopt", s_ignore
, 0},
1016 {"optim", s_ignore
, 0},
1017 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1018 {"code16", set_code_flag
, CODE_16BIT
},
1019 {"code32", set_code_flag
, CODE_32BIT
},
1020 {"code64", set_code_flag
, CODE_64BIT
},
1021 {"intel_syntax", set_intel_syntax
, 1},
1022 {"att_syntax", set_intel_syntax
, 0},
1023 {"intel_mnemonic", set_intel_mnemonic
, 1},
1024 {"att_mnemonic", set_intel_mnemonic
, 0},
1025 {"allow_index_reg", set_allow_index_reg
, 1},
1026 {"disallow_index_reg", set_allow_index_reg
, 0},
1027 {"sse_check", set_check
, 0},
1028 {"operand_check", set_check
, 1},
1029 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1030 {"largecomm", handle_large_common
, 0},
1032 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1033 {"loc", dwarf2_directive_loc
, 0},
1034 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1037 {"secrel32", pe_directive_secrel
, 0},
1042 /* For interface with expression (). */
1043 extern char *input_line_pointer
;
1045 /* Hash table for instruction mnemonic lookup. */
1046 static struct hash_control
*op_hash
;
1048 /* Hash table for register lookup. */
1049 static struct hash_control
*reg_hash
;
1052 i386_align_code (fragS
*fragP
, int count
)
1054 /* Various efficient no-op patterns for aligning code labels.
1055 Note: Don't try to assemble the instructions in the comments.
1056 0L and 0w are not legal. */
1057 static const char f32_1
[] =
1059 static const char f32_2
[] =
1060 {0x66,0x90}; /* xchg %ax,%ax */
1061 static const char f32_3
[] =
1062 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1063 static const char f32_4
[] =
1064 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1065 static const char f32_5
[] =
1067 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1068 static const char f32_6
[] =
1069 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1070 static const char f32_7
[] =
1071 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1072 static const char f32_8
[] =
1074 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1075 static const char f32_9
[] =
1076 {0x89,0xf6, /* movl %esi,%esi */
1077 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1078 static const char f32_10
[] =
1079 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1080 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1081 static const char f32_11
[] =
1082 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1083 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1084 static const char f32_12
[] =
1085 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1086 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1087 static const char f32_13
[] =
1088 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1089 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1090 static const char f32_14
[] =
1091 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1092 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1093 static const char f16_3
[] =
1094 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1095 static const char f16_4
[] =
1096 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1097 static const char f16_5
[] =
1099 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1100 static const char f16_6
[] =
1101 {0x89,0xf6, /* mov %si,%si */
1102 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1103 static const char f16_7
[] =
1104 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1105 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1106 static const char f16_8
[] =
1107 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1108 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1109 static const char jump_31
[] =
1110 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1111 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1112 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1113 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1114 static const char *const f32_patt
[] = {
1115 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1116 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1118 static const char *const f16_patt
[] = {
1119 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1121 /* nopl (%[re]ax) */
1122 static const char alt_3
[] =
1124 /* nopl 0(%[re]ax) */
1125 static const char alt_4
[] =
1126 {0x0f,0x1f,0x40,0x00};
1127 /* nopl 0(%[re]ax,%[re]ax,1) */
1128 static const char alt_5
[] =
1129 {0x0f,0x1f,0x44,0x00,0x00};
1130 /* nopw 0(%[re]ax,%[re]ax,1) */
1131 static const char alt_6
[] =
1132 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1133 /* nopl 0L(%[re]ax) */
1134 static const char alt_7
[] =
1135 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1136 /* nopl 0L(%[re]ax,%[re]ax,1) */
1137 static const char alt_8
[] =
1138 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1139 /* nopw 0L(%[re]ax,%[re]ax,1) */
1140 static const char alt_9
[] =
1141 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1142 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1143 static const char alt_10
[] =
1144 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1145 static const char *const alt_patt
[] = {
1146 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1150 /* Only align for at least a positive non-zero boundary. */
1151 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1154 /* We need to decide which NOP sequence to use for 32bit and
1155 64bit. When -mtune= is used:
1157 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1158 PROCESSOR_GENERIC32, f32_patt will be used.
1159 2. For the rest, alt_patt will be used.
1161 When -mtune= isn't used, alt_patt will be used if
1162 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1165 When -march= or .arch is used, we can't use anything beyond
1166 cpu_arch_isa_flags. */
1168 if (flag_code
== CODE_16BIT
)
1172 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1174 /* Adjust jump offset. */
1175 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1178 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1179 f16_patt
[count
- 1], count
);
1183 const char *const *patt
= NULL
;
1185 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1187 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1188 switch (cpu_arch_tune
)
1190 case PROCESSOR_UNKNOWN
:
1191 /* We use cpu_arch_isa_flags to check if we SHOULD
1192 optimize with nops. */
1193 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1198 case PROCESSOR_PENTIUM4
:
1199 case PROCESSOR_NOCONA
:
1200 case PROCESSOR_CORE
:
1201 case PROCESSOR_CORE2
:
1202 case PROCESSOR_COREI7
:
1203 case PROCESSOR_L1OM
:
1204 case PROCESSOR_K1OM
:
1205 case PROCESSOR_GENERIC64
:
1207 case PROCESSOR_ATHLON
:
1209 case PROCESSOR_AMDFAM10
:
1211 case PROCESSOR_ZNVER
:
1215 case PROCESSOR_I386
:
1216 case PROCESSOR_I486
:
1217 case PROCESSOR_PENTIUM
:
1218 case PROCESSOR_PENTIUMPRO
:
1219 case PROCESSOR_IAMCU
:
1220 case PROCESSOR_GENERIC32
:
1227 switch (fragP
->tc_frag_data
.tune
)
1229 case PROCESSOR_UNKNOWN
:
1230 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1231 PROCESSOR_UNKNOWN. */
1235 case PROCESSOR_I386
:
1236 case PROCESSOR_I486
:
1237 case PROCESSOR_PENTIUM
:
1238 case PROCESSOR_IAMCU
:
1240 case PROCESSOR_ATHLON
:
1242 case PROCESSOR_AMDFAM10
:
1244 case PROCESSOR_ZNVER
:
1246 case PROCESSOR_GENERIC32
:
1247 /* We use cpu_arch_isa_flags to check if we CAN optimize
1249 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1254 case PROCESSOR_PENTIUMPRO
:
1255 case PROCESSOR_PENTIUM4
:
1256 case PROCESSOR_NOCONA
:
1257 case PROCESSOR_CORE
:
1258 case PROCESSOR_CORE2
:
1259 case PROCESSOR_COREI7
:
1260 case PROCESSOR_L1OM
:
1261 case PROCESSOR_K1OM
:
1262 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1267 case PROCESSOR_GENERIC64
:
1273 if (patt
== f32_patt
)
1275 /* If the padding is less than 15 bytes, we use the normal
1276 ones. Otherwise, we use a jump instruction and adjust
1280 /* For 64bit, the limit is 3 bytes. */
1281 if (flag_code
== CODE_64BIT
1282 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1287 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1288 patt
[count
- 1], count
);
1291 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1293 /* Adjust jump offset. */
1294 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1299 /* Maximum length of an instruction is 10 byte. If the
1300 padding is greater than 10 bytes and we don't use jump,
1301 we have to break it into smaller pieces. */
1302 int padding
= count
;
1303 while (padding
> 10)
1306 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1311 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1312 patt
[padding
- 1], padding
);
1315 fragP
->fr_var
= count
;
1319 operand_type_all_zero (const union i386_operand_type
*x
)
1321 switch (ARRAY_SIZE(x
->array
))
1330 return !x
->array
[0];
1337 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1339 switch (ARRAY_SIZE(x
->array
))
1354 operand_type_equal (const union i386_operand_type
*x
,
1355 const union i386_operand_type
*y
)
1357 switch (ARRAY_SIZE(x
->array
))
1360 if (x
->array
[2] != y
->array
[2])
1363 if (x
->array
[1] != y
->array
[1])
1366 return x
->array
[0] == y
->array
[0];
1374 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1376 switch (ARRAY_SIZE(x
->array
))
1385 return !x
->array
[0];
1392 cpu_flags_equal (const union i386_cpu_flags
*x
,
1393 const union i386_cpu_flags
*y
)
1395 switch (ARRAY_SIZE(x
->array
))
1398 if (x
->array
[2] != y
->array
[2])
1401 if (x
->array
[1] != y
->array
[1])
1404 return x
->array
[0] == y
->array
[0];
1412 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1414 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1415 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1418 static INLINE i386_cpu_flags
1419 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1421 switch (ARRAY_SIZE (x
.array
))
1424 x
.array
[2] &= y
.array
[2];
1426 x
.array
[1] &= y
.array
[1];
1428 x
.array
[0] &= y
.array
[0];
1436 static INLINE i386_cpu_flags
1437 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1439 switch (ARRAY_SIZE (x
.array
))
1442 x
.array
[2] |= y
.array
[2];
1444 x
.array
[1] |= y
.array
[1];
1446 x
.array
[0] |= y
.array
[0];
1454 static INLINE i386_cpu_flags
1455 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1457 switch (ARRAY_SIZE (x
.array
))
1460 x
.array
[2] &= ~y
.array
[2];
1462 x
.array
[1] &= ~y
.array
[1];
1464 x
.array
[0] &= ~y
.array
[0];
1473 valid_iamcu_cpu_flags (const i386_cpu_flags
*flags
)
1475 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
1477 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_COMPAT_FLAGS
;
1478 i386_cpu_flags compat_flags
;
1479 compat_flags
= cpu_flags_and_not (*flags
, iamcu_flags
);
1480 return cpu_flags_all_zero (&compat_flags
);
1486 #define CPU_FLAGS_ARCH_MATCH 0x1
1487 #define CPU_FLAGS_64BIT_MATCH 0x2
1488 #define CPU_FLAGS_AES_MATCH 0x4
1489 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1490 #define CPU_FLAGS_AVX_MATCH 0x10
1492 #define CPU_FLAGS_32BIT_MATCH \
1493 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1494 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1495 #define CPU_FLAGS_PERFECT_MATCH \
1496 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1498 /* Return CPU flags match bits. */
1501 cpu_flags_match (const insn_template
*t
)
1503 i386_cpu_flags x
= t
->cpu_flags
;
1504 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1506 x
.bitfield
.cpu64
= 0;
1507 x
.bitfield
.cpuno64
= 0;
1509 if (cpu_flags_all_zero (&x
))
1511 /* This instruction is available on all archs. */
1512 match
|= CPU_FLAGS_32BIT_MATCH
;
1516 /* This instruction is available only on some archs. */
1517 i386_cpu_flags cpu
= cpu_arch_flags
;
1519 cpu
.bitfield
.cpu64
= 0;
1520 cpu
.bitfield
.cpuno64
= 0;
1521 cpu
= cpu_flags_and (x
, cpu
);
1522 if (!cpu_flags_all_zero (&cpu
))
1524 if (x
.bitfield
.cpuavx
)
1526 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1527 if (cpu
.bitfield
.cpuavx
)
1529 /* Check SSE2AVX. */
1530 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1532 match
|= (CPU_FLAGS_ARCH_MATCH
1533 | CPU_FLAGS_AVX_MATCH
);
1535 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1536 match
|= CPU_FLAGS_AES_MATCH
;
1538 if (!x
.bitfield
.cpupclmul
1539 || cpu
.bitfield
.cpupclmul
)
1540 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1544 match
|= CPU_FLAGS_ARCH_MATCH
;
1547 match
|= CPU_FLAGS_32BIT_MATCH
;
1553 static INLINE i386_operand_type
1554 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1556 switch (ARRAY_SIZE (x
.array
))
1559 x
.array
[2] &= y
.array
[2];
1561 x
.array
[1] &= y
.array
[1];
1563 x
.array
[0] &= y
.array
[0];
1571 static INLINE i386_operand_type
1572 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1574 switch (ARRAY_SIZE (x
.array
))
1577 x
.array
[2] |= y
.array
[2];
1579 x
.array
[1] |= y
.array
[1];
1581 x
.array
[0] |= y
.array
[0];
1589 static INLINE i386_operand_type
1590 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1592 switch (ARRAY_SIZE (x
.array
))
1595 x
.array
[2] ^= y
.array
[2];
1597 x
.array
[1] ^= y
.array
[1];
1599 x
.array
[0] ^= y
.array
[0];
1607 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1608 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1609 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1610 static const i386_operand_type inoutportreg
1611 = OPERAND_TYPE_INOUTPORTREG
;
1612 static const i386_operand_type reg16_inoutportreg
1613 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1614 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1615 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1616 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1617 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1618 static const i386_operand_type anydisp
1619 = OPERAND_TYPE_ANYDISP
;
1620 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1621 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1622 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1623 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1624 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1625 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1626 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1627 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1628 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1629 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1630 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1631 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1632 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1633 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1644 operand_type_check (i386_operand_type t
, enum operand_type c
)
1649 return (t
.bitfield
.reg8
1652 || t
.bitfield
.reg64
);
1655 return (t
.bitfield
.imm8
1659 || t
.bitfield
.imm32s
1660 || t
.bitfield
.imm64
);
1663 return (t
.bitfield
.disp8
1664 || t
.bitfield
.disp16
1665 || t
.bitfield
.disp32
1666 || t
.bitfield
.disp32s
1667 || t
.bitfield
.disp64
);
1670 return (t
.bitfield
.disp8
1671 || t
.bitfield
.disp16
1672 || t
.bitfield
.disp32
1673 || t
.bitfield
.disp32s
1674 || t
.bitfield
.disp64
1675 || t
.bitfield
.baseindex
);
1684 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1685 operand J for instruction template T. */
1688 match_reg_size (const insn_template
*t
, unsigned int j
)
1690 return !((i
.types
[j
].bitfield
.byte
1691 && !t
->operand_types
[j
].bitfield
.byte
)
1692 || (i
.types
[j
].bitfield
.word
1693 && !t
->operand_types
[j
].bitfield
.word
)
1694 || (i
.types
[j
].bitfield
.dword
1695 && !t
->operand_types
[j
].bitfield
.dword
)
1696 || (i
.types
[j
].bitfield
.qword
1697 && !t
->operand_types
[j
].bitfield
.qword
));
1700 /* Return 1 if there is no conflict in any size on operand J for
1701 instruction template T. */
1704 match_mem_size (const insn_template
*t
, unsigned int j
)
1706 return (match_reg_size (t
, j
)
1707 && !((i
.types
[j
].bitfield
.unspecified
1709 && !t
->operand_types
[j
].bitfield
.unspecified
)
1710 || (i
.types
[j
].bitfield
.fword
1711 && !t
->operand_types
[j
].bitfield
.fword
)
1712 || (i
.types
[j
].bitfield
.tbyte
1713 && !t
->operand_types
[j
].bitfield
.tbyte
)
1714 || (i
.types
[j
].bitfield
.xmmword
1715 && !t
->operand_types
[j
].bitfield
.xmmword
)
1716 || (i
.types
[j
].bitfield
.ymmword
1717 && !t
->operand_types
[j
].bitfield
.ymmword
)
1718 || (i
.types
[j
].bitfield
.zmmword
1719 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1722 /* Return 1 if there is no size conflict on any operands for
1723 instruction template T. */
1726 operand_size_match (const insn_template
*t
)
1731 /* Don't check jump instructions. */
1732 if (t
->opcode_modifier
.jump
1733 || t
->opcode_modifier
.jumpbyte
1734 || t
->opcode_modifier
.jumpdword
1735 || t
->opcode_modifier
.jumpintersegment
)
1738 /* Check memory and accumulator operand size. */
1739 for (j
= 0; j
< i
.operands
; j
++)
1741 if (t
->operand_types
[j
].bitfield
.anysize
)
1744 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1750 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1759 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1762 i
.error
= operand_size_mismatch
;
1766 /* Check reverse. */
1767 gas_assert (i
.operands
== 2);
1770 for (j
= 0; j
< 2; j
++)
1772 if (t
->operand_types
[j
].bitfield
.acc
1773 && !match_reg_size (t
, j
? 0 : 1))
1776 if (i
.types
[j
].bitfield
.mem
1777 && !match_mem_size (t
, j
? 0 : 1))
1785 operand_type_match (i386_operand_type overlap
,
1786 i386_operand_type given
)
1788 i386_operand_type temp
= overlap
;
1790 temp
.bitfield
.jumpabsolute
= 0;
1791 temp
.bitfield
.unspecified
= 0;
1792 temp
.bitfield
.byte
= 0;
1793 temp
.bitfield
.word
= 0;
1794 temp
.bitfield
.dword
= 0;
1795 temp
.bitfield
.fword
= 0;
1796 temp
.bitfield
.qword
= 0;
1797 temp
.bitfield
.tbyte
= 0;
1798 temp
.bitfield
.xmmword
= 0;
1799 temp
.bitfield
.ymmword
= 0;
1800 temp
.bitfield
.zmmword
= 0;
1801 if (operand_type_all_zero (&temp
))
1804 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1805 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1809 i
.error
= operand_type_mismatch
;
1813 /* If given types g0 and g1 are registers they must be of the same type
1814 unless the expected operand type register overlap is null.
1815 Note that Acc in a template matches every size of reg. */
1818 operand_type_register_match (i386_operand_type m0
,
1819 i386_operand_type g0
,
1820 i386_operand_type t0
,
1821 i386_operand_type m1
,
1822 i386_operand_type g1
,
1823 i386_operand_type t1
)
1825 if (!operand_type_check (g0
, reg
))
1828 if (!operand_type_check (g1
, reg
))
1831 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1832 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1833 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1834 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1837 if (m0
.bitfield
.acc
)
1839 t0
.bitfield
.reg8
= 1;
1840 t0
.bitfield
.reg16
= 1;
1841 t0
.bitfield
.reg32
= 1;
1842 t0
.bitfield
.reg64
= 1;
1845 if (m1
.bitfield
.acc
)
1847 t1
.bitfield
.reg8
= 1;
1848 t1
.bitfield
.reg16
= 1;
1849 t1
.bitfield
.reg32
= 1;
1850 t1
.bitfield
.reg64
= 1;
1853 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1854 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1855 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1856 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1859 i
.error
= register_type_mismatch
;
1864 static INLINE
unsigned int
1865 register_number (const reg_entry
*r
)
1867 unsigned int nr
= r
->reg_num
;
1869 if (r
->reg_flags
& RegRex
)
1875 static INLINE
unsigned int
1876 mode_from_disp_size (i386_operand_type t
)
1878 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1880 else if (t
.bitfield
.disp16
1881 || t
.bitfield
.disp32
1882 || t
.bitfield
.disp32s
)
1889 fits_in_signed_byte (addressT num
)
1891 return num
+ 0x80 <= 0xff;
1895 fits_in_unsigned_byte (addressT num
)
1901 fits_in_unsigned_word (addressT num
)
1903 return num
<= 0xffff;
1907 fits_in_signed_word (addressT num
)
1909 return num
+ 0x8000 <= 0xffff;
1913 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1918 return num
+ 0x80000000 <= 0xffffffff;
1920 } /* fits_in_signed_long() */
1923 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
1928 return num
<= 0xffffffff;
1930 } /* fits_in_unsigned_long() */
1933 fits_in_vec_disp8 (offsetT num
)
1935 int shift
= i
.memshift
;
1941 mask
= (1 << shift
) - 1;
1943 /* Return 0 if NUM isn't properly aligned. */
1947 /* Check if NUM will fit in 8bit after shift. */
1948 return fits_in_signed_byte (num
>> shift
);
1952 fits_in_imm4 (offsetT num
)
1954 return (num
& 0xf) == num
;
1957 static i386_operand_type
1958 smallest_imm_type (offsetT num
)
1960 i386_operand_type t
;
1962 operand_type_set (&t
, 0);
1963 t
.bitfield
.imm64
= 1;
1965 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1967 /* This code is disabled on the 486 because all the Imm1 forms
1968 in the opcode table are slower on the i486. They're the
1969 versions with the implicitly specified single-position
1970 displacement, which has another syntax if you really want to
1972 t
.bitfield
.imm1
= 1;
1973 t
.bitfield
.imm8
= 1;
1974 t
.bitfield
.imm8s
= 1;
1975 t
.bitfield
.imm16
= 1;
1976 t
.bitfield
.imm32
= 1;
1977 t
.bitfield
.imm32s
= 1;
1979 else if (fits_in_signed_byte (num
))
1981 t
.bitfield
.imm8
= 1;
1982 t
.bitfield
.imm8s
= 1;
1983 t
.bitfield
.imm16
= 1;
1984 t
.bitfield
.imm32
= 1;
1985 t
.bitfield
.imm32s
= 1;
1987 else if (fits_in_unsigned_byte (num
))
1989 t
.bitfield
.imm8
= 1;
1990 t
.bitfield
.imm16
= 1;
1991 t
.bitfield
.imm32
= 1;
1992 t
.bitfield
.imm32s
= 1;
1994 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1996 t
.bitfield
.imm16
= 1;
1997 t
.bitfield
.imm32
= 1;
1998 t
.bitfield
.imm32s
= 1;
2000 else if (fits_in_signed_long (num
))
2002 t
.bitfield
.imm32
= 1;
2003 t
.bitfield
.imm32s
= 1;
2005 else if (fits_in_unsigned_long (num
))
2006 t
.bitfield
.imm32
= 1;
2012 offset_in_range (offsetT val
, int size
)
2018 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2019 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2020 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2022 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2028 /* If BFD64, sign extend val for 32bit address mode. */
2029 if (flag_code
!= CODE_64BIT
2030 || i
.prefix
[ADDR_PREFIX
])
2031 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2032 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2035 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2037 char buf1
[40], buf2
[40];
2039 sprint_value (buf1
, val
);
2040 sprint_value (buf2
, val
& mask
);
2041 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2055 a. PREFIX_EXIST if attempting to add a prefix where one from the
2056 same class already exists.
2057 b. PREFIX_LOCK if lock prefix is added.
2058 c. PREFIX_REP if rep/repne prefix is added.
2059 d. PREFIX_OTHER if other prefix is added.
2062 static enum PREFIX_GROUP
2063 add_prefix (unsigned int prefix
)
2065 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2068 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2069 && flag_code
== CODE_64BIT
)
2071 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2072 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2073 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2084 case CS_PREFIX_OPCODE
:
2085 case DS_PREFIX_OPCODE
:
2086 case ES_PREFIX_OPCODE
:
2087 case FS_PREFIX_OPCODE
:
2088 case GS_PREFIX_OPCODE
:
2089 case SS_PREFIX_OPCODE
:
2093 case REPNE_PREFIX_OPCODE
:
2094 case REPE_PREFIX_OPCODE
:
2099 case LOCK_PREFIX_OPCODE
:
2108 case ADDR_PREFIX_OPCODE
:
2112 case DATA_PREFIX_OPCODE
:
2116 if (i
.prefix
[q
] != 0)
2124 i
.prefix
[q
] |= prefix
;
2127 as_bad (_("same type of prefix used twice"));
2133 update_code_flag (int value
, int check
)
2135 PRINTF_LIKE ((*as_error
));
2137 flag_code
= (enum flag_code
) value
;
2138 if (flag_code
== CODE_64BIT
)
2140 cpu_arch_flags
.bitfield
.cpu64
= 1;
2141 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2145 cpu_arch_flags
.bitfield
.cpu64
= 0;
2146 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2148 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2151 as_error
= as_fatal
;
2154 (*as_error
) (_("64bit mode not supported on `%s'."),
2155 cpu_arch_name
? cpu_arch_name
: default_arch
);
2157 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2160 as_error
= as_fatal
;
2163 (*as_error
) (_("32bit mode not supported on `%s'."),
2164 cpu_arch_name
? cpu_arch_name
: default_arch
);
2166 stackop_size
= '\0';
2170 set_code_flag (int value
)
2172 update_code_flag (value
, 0);
2176 set_16bit_gcc_code_flag (int new_code_flag
)
2178 flag_code
= (enum flag_code
) new_code_flag
;
2179 if (flag_code
!= CODE_16BIT
)
2181 cpu_arch_flags
.bitfield
.cpu64
= 0;
2182 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2183 stackop_size
= LONG_MNEM_SUFFIX
;
2187 set_intel_syntax (int syntax_flag
)
2189 /* Find out if register prefixing is specified. */
2190 int ask_naked_reg
= 0;
2193 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2196 int e
= get_symbol_name (&string
);
2198 if (strcmp (string
, "prefix") == 0)
2200 else if (strcmp (string
, "noprefix") == 0)
2203 as_bad (_("bad argument to syntax directive."));
2204 (void) restore_line_pointer (e
);
2206 demand_empty_rest_of_line ();
2208 intel_syntax
= syntax_flag
;
2210 if (ask_naked_reg
== 0)
2211 allow_naked_reg
= (intel_syntax
2212 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2214 allow_naked_reg
= (ask_naked_reg
< 0);
2216 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2218 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2219 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2220 register_prefix
= allow_naked_reg
? "" : "%";
2224 set_intel_mnemonic (int mnemonic_flag
)
2226 intel_mnemonic
= mnemonic_flag
;
2230 set_allow_index_reg (int flag
)
2232 allow_index_reg
= flag
;
2236 set_check (int what
)
2238 enum check_kind
*kind
;
2243 kind
= &operand_check
;
2254 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2257 int e
= get_symbol_name (&string
);
2259 if (strcmp (string
, "none") == 0)
2261 else if (strcmp (string
, "warning") == 0)
2262 *kind
= check_warning
;
2263 else if (strcmp (string
, "error") == 0)
2264 *kind
= check_error
;
2266 as_bad (_("bad argument to %s_check directive."), str
);
2267 (void) restore_line_pointer (e
);
2270 as_bad (_("missing argument for %s_check directive"), str
);
2272 demand_empty_rest_of_line ();
2276 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2277 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2279 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2280 static const char *arch
;
2282 /* Intel LIOM is only supported on ELF. */
2288 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2289 use default_arch. */
2290 arch
= cpu_arch_name
;
2292 arch
= default_arch
;
2295 /* If we are targeting Intel MCU, we must enable it. */
2296 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2297 || new_flag
.bitfield
.cpuiamcu
)
2300 /* If we are targeting Intel L1OM, we must enable it. */
2301 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2302 || new_flag
.bitfield
.cpul1om
)
2305 /* If we are targeting Intel K1OM, we must enable it. */
2306 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2307 || new_flag
.bitfield
.cpuk1om
)
2310 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2315 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2319 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2322 int e
= get_symbol_name (&string
);
2324 i386_cpu_flags flags
;
2326 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2328 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2330 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2334 cpu_arch_name
= cpu_arch
[j
].name
;
2335 cpu_sub_arch_name
= NULL
;
2336 cpu_arch_flags
= cpu_arch
[j
].flags
;
2337 if (flag_code
== CODE_64BIT
)
2339 cpu_arch_flags
.bitfield
.cpu64
= 1;
2340 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2344 cpu_arch_flags
.bitfield
.cpu64
= 0;
2345 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2347 cpu_arch_isa
= cpu_arch
[j
].type
;
2348 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2349 if (!cpu_arch_tune_set
)
2351 cpu_arch_tune
= cpu_arch_isa
;
2352 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2357 if (!cpu_arch
[j
].negated
)
2358 flags
= cpu_flags_or (cpu_arch_flags
,
2361 flags
= cpu_flags_and_not (cpu_arch_flags
,
2364 if (!valid_iamcu_cpu_flags (&flags
))
2365 as_fatal (_("`%s' isn't valid for Intel MCU"),
2367 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2369 if (cpu_sub_arch_name
)
2371 char *name
= cpu_sub_arch_name
;
2372 cpu_sub_arch_name
= concat (name
,
2374 (const char *) NULL
);
2378 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2379 cpu_arch_flags
= flags
;
2380 cpu_arch_isa_flags
= flags
;
2382 (void) restore_line_pointer (e
);
2383 demand_empty_rest_of_line ();
2387 if (j
>= ARRAY_SIZE (cpu_arch
))
2388 as_bad (_("no such architecture: `%s'"), string
);
2390 *input_line_pointer
= e
;
2393 as_bad (_("missing cpu architecture"));
2395 no_cond_jump_promotion
= 0;
2396 if (*input_line_pointer
== ','
2397 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2402 ++input_line_pointer
;
2403 e
= get_symbol_name (&string
);
2405 if (strcmp (string
, "nojumps") == 0)
2406 no_cond_jump_promotion
= 1;
2407 else if (strcmp (string
, "jumps") == 0)
2410 as_bad (_("no such architecture modifier: `%s'"), string
);
2412 (void) restore_line_pointer (e
);
2415 demand_empty_rest_of_line ();
2418 enum bfd_architecture
2421 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2423 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2424 || flag_code
!= CODE_64BIT
)
2425 as_fatal (_("Intel L1OM is 64bit ELF only"));
2426 return bfd_arch_l1om
;
2428 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2430 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2431 || flag_code
!= CODE_64BIT
)
2432 as_fatal (_("Intel K1OM is 64bit ELF only"));
2433 return bfd_arch_k1om
;
2435 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2437 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2438 || flag_code
== CODE_64BIT
)
2439 as_fatal (_("Intel MCU is 32bit ELF only"));
2440 return bfd_arch_iamcu
;
2443 return bfd_arch_i386
;
2449 if (!strncmp (default_arch
, "x86_64", 6))
2451 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2453 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2454 || default_arch
[6] != '\0')
2455 as_fatal (_("Intel L1OM is 64bit ELF only"));
2456 return bfd_mach_l1om
;
2458 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2460 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2461 || default_arch
[6] != '\0')
2462 as_fatal (_("Intel K1OM is 64bit ELF only"));
2463 return bfd_mach_k1om
;
2465 else if (default_arch
[6] == '\0')
2466 return bfd_mach_x86_64
;
2468 return bfd_mach_x64_32
;
2470 else if (!strcmp (default_arch
, "i386")
2471 || !strcmp (default_arch
, "iamcu"))
2473 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2475 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2476 as_fatal (_("Intel MCU is 32bit ELF only"));
2477 return bfd_mach_i386_iamcu
;
2480 return bfd_mach_i386_i386
;
2483 as_fatal (_("unknown architecture"));
2489 const char *hash_err
;
2491 /* Initialize op_hash hash table. */
2492 op_hash
= hash_new ();
2495 const insn_template
*optab
;
2496 templates
*core_optab
;
2498 /* Setup for loop. */
2500 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2501 core_optab
->start
= optab
;
2506 if (optab
->name
== NULL
2507 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2509 /* different name --> ship out current template list;
2510 add to hash table; & begin anew. */
2511 core_optab
->end
= optab
;
2512 hash_err
= hash_insert (op_hash
,
2514 (void *) core_optab
);
2517 as_fatal (_("can't hash %s: %s"),
2521 if (optab
->name
== NULL
)
2523 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2524 core_optab
->start
= optab
;
2529 /* Initialize reg_hash hash table. */
2530 reg_hash
= hash_new ();
2532 const reg_entry
*regtab
;
2533 unsigned int regtab_size
= i386_regtab_size
;
2535 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2537 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2539 as_fatal (_("can't hash %s: %s"),
2545 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2550 for (c
= 0; c
< 256; c
++)
2555 mnemonic_chars
[c
] = c
;
2556 register_chars
[c
] = c
;
2557 operand_chars
[c
] = c
;
2559 else if (ISLOWER (c
))
2561 mnemonic_chars
[c
] = c
;
2562 register_chars
[c
] = c
;
2563 operand_chars
[c
] = c
;
2565 else if (ISUPPER (c
))
2567 mnemonic_chars
[c
] = TOLOWER (c
);
2568 register_chars
[c
] = mnemonic_chars
[c
];
2569 operand_chars
[c
] = c
;
2571 else if (c
== '{' || c
== '}')
2572 operand_chars
[c
] = c
;
2574 if (ISALPHA (c
) || ISDIGIT (c
))
2575 identifier_chars
[c
] = c
;
2578 identifier_chars
[c
] = c
;
2579 operand_chars
[c
] = c
;
2584 identifier_chars
['@'] = '@';
2587 identifier_chars
['?'] = '?';
2588 operand_chars
['?'] = '?';
2590 digit_chars
['-'] = '-';
2591 mnemonic_chars
['_'] = '_';
2592 mnemonic_chars
['-'] = '-';
2593 mnemonic_chars
['.'] = '.';
2594 identifier_chars
['_'] = '_';
2595 identifier_chars
['.'] = '.';
2597 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2598 operand_chars
[(unsigned char) *p
] = *p
;
2601 if (flag_code
== CODE_64BIT
)
2603 #if defined (OBJ_COFF) && defined (TE_PE)
2604 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2607 x86_dwarf2_return_column
= 16;
2609 x86_cie_data_alignment
= -8;
2613 x86_dwarf2_return_column
= 8;
2614 x86_cie_data_alignment
= -4;
2619 i386_print_statistics (FILE *file
)
2621 hash_print_statistics (file
, "i386 opcode", op_hash
);
2622 hash_print_statistics (file
, "i386 register", reg_hash
);
2627 /* Debugging routines for md_assemble. */
2628 static void pte (insn_template
*);
2629 static void pt (i386_operand_type
);
2630 static void pe (expressionS
*);
2631 static void ps (symbolS
*);
2634 pi (char *line
, i386_insn
*x
)
2638 fprintf (stdout
, "%s: template ", line
);
2640 fprintf (stdout
, " address: base %s index %s scale %x\n",
2641 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2642 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2643 x
->log2_scale_factor
);
2644 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2645 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2646 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2647 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2648 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2649 (x
->rex
& REX_W
) != 0,
2650 (x
->rex
& REX_R
) != 0,
2651 (x
->rex
& REX_X
) != 0,
2652 (x
->rex
& REX_B
) != 0);
2653 for (j
= 0; j
< x
->operands
; j
++)
2655 fprintf (stdout
, " #%d: ", j
+ 1);
2657 fprintf (stdout
, "\n");
2658 if (x
->types
[j
].bitfield
.reg8
2659 || x
->types
[j
].bitfield
.reg16
2660 || x
->types
[j
].bitfield
.reg32
2661 || x
->types
[j
].bitfield
.reg64
2662 || x
->types
[j
].bitfield
.regmmx
2663 || x
->types
[j
].bitfield
.regxmm
2664 || x
->types
[j
].bitfield
.regymm
2665 || x
->types
[j
].bitfield
.regzmm
2666 || x
->types
[j
].bitfield
.sreg2
2667 || x
->types
[j
].bitfield
.sreg3
2668 || x
->types
[j
].bitfield
.control
2669 || x
->types
[j
].bitfield
.debug
2670 || x
->types
[j
].bitfield
.test
)
2671 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2672 if (operand_type_check (x
->types
[j
], imm
))
2674 if (operand_type_check (x
->types
[j
], disp
))
2675 pe (x
->op
[j
].disps
);
2680 pte (insn_template
*t
)
2683 fprintf (stdout
, " %d operands ", t
->operands
);
2684 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2685 if (t
->extension_opcode
!= None
)
2686 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2687 if (t
->opcode_modifier
.d
)
2688 fprintf (stdout
, "D");
2689 if (t
->opcode_modifier
.w
)
2690 fprintf (stdout
, "W");
2691 fprintf (stdout
, "\n");
2692 for (j
= 0; j
< t
->operands
; j
++)
2694 fprintf (stdout
, " #%d type ", j
+ 1);
2695 pt (t
->operand_types
[j
]);
2696 fprintf (stdout
, "\n");
2703 fprintf (stdout
, " operation %d\n", e
->X_op
);
2704 fprintf (stdout
, " add_number %ld (%lx)\n",
2705 (long) e
->X_add_number
, (long) e
->X_add_number
);
2706 if (e
->X_add_symbol
)
2708 fprintf (stdout
, " add_symbol ");
2709 ps (e
->X_add_symbol
);
2710 fprintf (stdout
, "\n");
2714 fprintf (stdout
, " op_symbol ");
2715 ps (e
->X_op_symbol
);
2716 fprintf (stdout
, "\n");
2723 fprintf (stdout
, "%s type %s%s",
2725 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2726 segment_name (S_GET_SEGMENT (s
)));
2729 static struct type_name
2731 i386_operand_type mask
;
2734 const type_names
[] =
2736 { OPERAND_TYPE_REG8
, "r8" },
2737 { OPERAND_TYPE_REG16
, "r16" },
2738 { OPERAND_TYPE_REG32
, "r32" },
2739 { OPERAND_TYPE_REG64
, "r64" },
2740 { OPERAND_TYPE_IMM8
, "i8" },
2741 { OPERAND_TYPE_IMM8
, "i8s" },
2742 { OPERAND_TYPE_IMM16
, "i16" },
2743 { OPERAND_TYPE_IMM32
, "i32" },
2744 { OPERAND_TYPE_IMM32S
, "i32s" },
2745 { OPERAND_TYPE_IMM64
, "i64" },
2746 { OPERAND_TYPE_IMM1
, "i1" },
2747 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2748 { OPERAND_TYPE_DISP8
, "d8" },
2749 { OPERAND_TYPE_DISP16
, "d16" },
2750 { OPERAND_TYPE_DISP32
, "d32" },
2751 { OPERAND_TYPE_DISP32S
, "d32s" },
2752 { OPERAND_TYPE_DISP64
, "d64" },
2753 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2754 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2755 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2756 { OPERAND_TYPE_CONTROL
, "control reg" },
2757 { OPERAND_TYPE_TEST
, "test reg" },
2758 { OPERAND_TYPE_DEBUG
, "debug reg" },
2759 { OPERAND_TYPE_FLOATREG
, "FReg" },
2760 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2761 { OPERAND_TYPE_SREG2
, "SReg2" },
2762 { OPERAND_TYPE_SREG3
, "SReg3" },
2763 { OPERAND_TYPE_ACC
, "Acc" },
2764 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2765 { OPERAND_TYPE_REGMMX
, "rMMX" },
2766 { OPERAND_TYPE_REGXMM
, "rXMM" },
2767 { OPERAND_TYPE_REGYMM
, "rYMM" },
2768 { OPERAND_TYPE_REGZMM
, "rZMM" },
2769 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2770 { OPERAND_TYPE_ESSEG
, "es" },
2774 pt (i386_operand_type t
)
2777 i386_operand_type a
;
2779 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2781 a
= operand_type_and (t
, type_names
[j
].mask
);
2782 if (!operand_type_all_zero (&a
))
2783 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2788 #endif /* DEBUG386 */
2790 static bfd_reloc_code_real_type
2791 reloc (unsigned int size
,
2794 bfd_reloc_code_real_type other
)
2796 if (other
!= NO_RELOC
)
2798 reloc_howto_type
*rel
;
2803 case BFD_RELOC_X86_64_GOT32
:
2804 return BFD_RELOC_X86_64_GOT64
;
2806 case BFD_RELOC_X86_64_GOTPLT64
:
2807 return BFD_RELOC_X86_64_GOTPLT64
;
2809 case BFD_RELOC_X86_64_PLTOFF64
:
2810 return BFD_RELOC_X86_64_PLTOFF64
;
2812 case BFD_RELOC_X86_64_GOTPC32
:
2813 other
= BFD_RELOC_X86_64_GOTPC64
;
2815 case BFD_RELOC_X86_64_GOTPCREL
:
2816 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2818 case BFD_RELOC_X86_64_TPOFF32
:
2819 other
= BFD_RELOC_X86_64_TPOFF64
;
2821 case BFD_RELOC_X86_64_DTPOFF32
:
2822 other
= BFD_RELOC_X86_64_DTPOFF64
;
2828 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2829 if (other
== BFD_RELOC_SIZE32
)
2832 other
= BFD_RELOC_SIZE64
;
2835 as_bad (_("there are no pc-relative size relocations"));
2841 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2842 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2845 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2847 as_bad (_("unknown relocation (%u)"), other
);
2848 else if (size
!= bfd_get_reloc_size (rel
))
2849 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2850 bfd_get_reloc_size (rel
),
2852 else if (pcrel
&& !rel
->pc_relative
)
2853 as_bad (_("non-pc-relative relocation for pc-relative field"));
2854 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2856 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2858 as_bad (_("relocated field and relocation type differ in signedness"));
2867 as_bad (_("there are no unsigned pc-relative relocations"));
2870 case 1: return BFD_RELOC_8_PCREL
;
2871 case 2: return BFD_RELOC_16_PCREL
;
2872 case 4: return BFD_RELOC_32_PCREL
;
2873 case 8: return BFD_RELOC_64_PCREL
;
2875 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2882 case 4: return BFD_RELOC_X86_64_32S
;
2887 case 1: return BFD_RELOC_8
;
2888 case 2: return BFD_RELOC_16
;
2889 case 4: return BFD_RELOC_32
;
2890 case 8: return BFD_RELOC_64
;
2892 as_bad (_("cannot do %s %u byte relocation"),
2893 sign
> 0 ? "signed" : "unsigned", size
);
2899 /* Here we decide which fixups can be adjusted to make them relative to
2900 the beginning of the section instead of the symbol. Basically we need
2901 to make sure that the dynamic relocations are done correctly, so in
2902 some cases we force the original symbol to be used. */
2905 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2907 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2911 /* Don't adjust pc-relative references to merge sections in 64-bit
2913 if (use_rela_relocations
2914 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2918 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2919 and changed later by validate_fix. */
2920 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2921 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2924 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2925 for size relocations. */
2926 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2927 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2928 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2929 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2930 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2931 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
2932 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2933 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2934 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2935 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2936 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2937 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2938 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2939 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2940 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2941 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2942 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2943 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2944 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2945 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2946 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2947 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2948 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2949 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2950 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2951 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2952 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2953 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2954 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2955 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2956 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2963 intel_float_operand (const char *mnemonic
)
2965 /* Note that the value returned is meaningful only for opcodes with (memory)
2966 operands, hence the code here is free to improperly handle opcodes that
2967 have no operands (for better performance and smaller code). */
2969 if (mnemonic
[0] != 'f')
2970 return 0; /* non-math */
2972 switch (mnemonic
[1])
2974 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2975 the fs segment override prefix not currently handled because no
2976 call path can make opcodes without operands get here */
2978 return 2 /* integer op */;
2980 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2981 return 3; /* fldcw/fldenv */
2984 if (mnemonic
[2] != 'o' /* fnop */)
2985 return 3; /* non-waiting control op */
2988 if (mnemonic
[2] == 's')
2989 return 3; /* frstor/frstpm */
2992 if (mnemonic
[2] == 'a')
2993 return 3; /* fsave */
2994 if (mnemonic
[2] == 't')
2996 switch (mnemonic
[3])
2998 case 'c': /* fstcw */
2999 case 'd': /* fstdw */
3000 case 'e': /* fstenv */
3001 case 's': /* fsts[gw] */
3007 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3008 return 0; /* fxsave/fxrstor are not really math ops */
3015 /* Build the VEX prefix. */
3018 build_vex_prefix (const insn_template
*t
)
3020 unsigned int register_specifier
;
3021 unsigned int implied_prefix
;
3022 unsigned int vector_length
;
3024 /* Check register specifier. */
3025 if (i
.vex
.register_specifier
)
3027 register_specifier
=
3028 ~register_number (i
.vex
.register_specifier
) & 0xf;
3029 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3032 register_specifier
= 0xf;
3034 /* Use 2-byte VEX prefix by swappping destination and source
3037 && i
.operands
== i
.reg_operands
3038 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3039 && i
.tm
.opcode_modifier
.s
3042 unsigned int xchg
= i
.operands
- 1;
3043 union i386_op temp_op
;
3044 i386_operand_type temp_type
;
3046 temp_type
= i
.types
[xchg
];
3047 i
.types
[xchg
] = i
.types
[0];
3048 i
.types
[0] = temp_type
;
3049 temp_op
= i
.op
[xchg
];
3050 i
.op
[xchg
] = i
.op
[0];
3053 gas_assert (i
.rm
.mode
== 3);
3057 i
.rm
.regmem
= i
.rm
.reg
;
3060 /* Use the next insn. */
3064 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3065 vector_length
= avxscalar
;
3067 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3069 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3074 case DATA_PREFIX_OPCODE
:
3077 case REPE_PREFIX_OPCODE
:
3080 case REPNE_PREFIX_OPCODE
:
3087 /* Use 2-byte VEX prefix if possible. */
3088 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3089 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3090 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3092 /* 2-byte VEX prefix. */
3096 i
.vex
.bytes
[0] = 0xc5;
3098 /* Check the REX.R bit. */
3099 r
= (i
.rex
& REX_R
) ? 0 : 1;
3100 i
.vex
.bytes
[1] = (r
<< 7
3101 | register_specifier
<< 3
3102 | vector_length
<< 2
3107 /* 3-byte VEX prefix. */
3112 switch (i
.tm
.opcode_modifier
.vexopcode
)
3116 i
.vex
.bytes
[0] = 0xc4;
3120 i
.vex
.bytes
[0] = 0xc4;
3124 i
.vex
.bytes
[0] = 0xc4;
3128 i
.vex
.bytes
[0] = 0x8f;
3132 i
.vex
.bytes
[0] = 0x8f;
3136 i
.vex
.bytes
[0] = 0x8f;
3142 /* The high 3 bits of the second VEX byte are 1's compliment
3143 of RXB bits from REX. */
3144 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3146 /* Check the REX.W bit. */
3147 w
= (i
.rex
& REX_W
) ? 1 : 0;
3148 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3151 i
.vex
.bytes
[2] = (w
<< 7
3152 | register_specifier
<< 3
3153 | vector_length
<< 2
3158 /* Build the EVEX prefix. */
3161 build_evex_prefix (void)
3163 unsigned int register_specifier
;
3164 unsigned int implied_prefix
;
3166 rex_byte vrex_used
= 0;
3168 /* Check register specifier. */
3169 if (i
.vex
.register_specifier
)
3171 gas_assert ((i
.vrex
& REX_X
) == 0);
3173 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3174 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3175 register_specifier
+= 8;
3176 /* The upper 16 registers are encoded in the fourth byte of the
3178 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3179 i
.vex
.bytes
[3] = 0x8;
3180 register_specifier
= ~register_specifier
& 0xf;
3184 register_specifier
= 0xf;
3186 /* Encode upper 16 vector index register in the fourth byte of
3188 if (!(i
.vrex
& REX_X
))
3189 i
.vex
.bytes
[3] = 0x8;
3194 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3199 case DATA_PREFIX_OPCODE
:
3202 case REPE_PREFIX_OPCODE
:
3205 case REPNE_PREFIX_OPCODE
:
3212 /* 4 byte EVEX prefix. */
3214 i
.vex
.bytes
[0] = 0x62;
3217 switch (i
.tm
.opcode_modifier
.vexopcode
)
3233 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3235 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3237 /* The fifth bit of the second EVEX byte is 1's compliment of the
3238 REX_R bit in VREX. */
3239 if (!(i
.vrex
& REX_R
))
3240 i
.vex
.bytes
[1] |= 0x10;
3244 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3246 /* When all operands are registers, the REX_X bit in REX is not
3247 used. We reuse it to encode the upper 16 registers, which is
3248 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3249 as 1's compliment. */
3250 if ((i
.vrex
& REX_B
))
3253 i
.vex
.bytes
[1] &= ~0x40;
3257 /* EVEX instructions shouldn't need the REX prefix. */
3258 i
.vrex
&= ~vrex_used
;
3259 gas_assert (i
.vrex
== 0);
3261 /* Check the REX.W bit. */
3262 w
= (i
.rex
& REX_W
) ? 1 : 0;
3263 if (i
.tm
.opcode_modifier
.vexw
)
3265 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3268 /* If w is not set it means we are dealing with WIG instruction. */
3271 if (evexwig
== evexw1
)
3275 /* Encode the U bit. */
3276 implied_prefix
|= 0x4;
3278 /* The third byte of the EVEX prefix. */
3279 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3281 /* The fourth byte of the EVEX prefix. */
3282 /* The zeroing-masking bit. */
3283 if (i
.mask
&& i
.mask
->zeroing
)
3284 i
.vex
.bytes
[3] |= 0x80;
3286 /* Don't always set the broadcast bit if there is no RC. */
3289 /* Encode the vector length. */
3290 unsigned int vec_length
;
3292 switch (i
.tm
.opcode_modifier
.evex
)
3294 case EVEXLIG
: /* LL' is ignored */
3295 vec_length
= evexlig
<< 5;
3298 vec_length
= 0 << 5;
3301 vec_length
= 1 << 5;
3304 vec_length
= 2 << 5;
3310 i
.vex
.bytes
[3] |= vec_length
;
3311 /* Encode the broadcast bit. */
3313 i
.vex
.bytes
[3] |= 0x10;
3317 if (i
.rounding
->type
!= saeonly
)
3318 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3320 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3323 if (i
.mask
&& i
.mask
->mask
)
3324 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3328 process_immext (void)
3332 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3335 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3336 with an opcode suffix which is coded in the same place as an
3337 8-bit immediate field would be.
3338 Here we check those operands and remove them afterwards. */
3341 for (x
= 0; x
< i
.operands
; x
++)
3342 if (register_number (i
.op
[x
].regs
) != x
)
3343 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3344 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3350 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3352 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3353 suffix which is coded in the same place as an 8-bit immediate
3355 Here we check those operands and remove them afterwards. */
3358 if (i
.operands
!= 3)
3361 for (x
= 0; x
< 2; x
++)
3362 if (register_number (i
.op
[x
].regs
) != x
)
3363 goto bad_register_operand
;
3365 /* Check for third operand for mwaitx/monitorx insn. */
3366 if (register_number (i
.op
[x
].regs
)
3367 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3369 bad_register_operand
:
3370 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3371 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3378 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3379 which is coded in the same place as an 8-bit immediate field
3380 would be. Here we fake an 8-bit immediate operand from the
3381 opcode suffix stored in tm.extension_opcode.
3383 AVX instructions also use this encoding, for some of
3384 3 argument instructions. */
3386 gas_assert (i
.imm_operands
<= 1
3388 || ((i
.tm
.opcode_modifier
.vex
3389 || i
.tm
.opcode_modifier
.evex
)
3390 && i
.operands
<= 4)));
3392 exp
= &im_expressions
[i
.imm_operands
++];
3393 i
.op
[i
.operands
].imms
= exp
;
3394 i
.types
[i
.operands
] = imm8
;
3396 exp
->X_op
= O_constant
;
3397 exp
->X_add_number
= i
.tm
.extension_opcode
;
3398 i
.tm
.extension_opcode
= None
;
3405 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3410 as_bad (_("invalid instruction `%s' after `%s'"),
3411 i
.tm
.name
, i
.hle_prefix
);
3414 if (i
.prefix
[LOCK_PREFIX
])
3416 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3420 case HLEPrefixRelease
:
3421 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3423 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3427 if (i
.mem_operands
== 0
3428 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3430 as_bad (_("memory destination needed for instruction `%s'"
3431 " after `xrelease'"), i
.tm
.name
);
3438 /* This is the guts of the machine-dependent assembler. LINE points to a
3439 machine dependent instruction. This function is supposed to emit
3440 the frags/bytes it assembles to. */
3443 md_assemble (char *line
)
3446 char mnemonic
[MAX_MNEM_SIZE
];
3447 const insn_template
*t
;
3449 /* Initialize globals. */
3450 memset (&i
, '\0', sizeof (i
));
3451 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3452 i
.reloc
[j
] = NO_RELOC
;
3453 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3454 memset (im_expressions
, '\0', sizeof (im_expressions
));
3455 save_stack_p
= save_stack
;
3457 /* First parse an instruction mnemonic & call i386_operand for the operands.
3458 We assume that the scrubber has arranged it so that line[0] is the valid
3459 start of a (possibly prefixed) mnemonic. */
3461 line
= parse_insn (line
, mnemonic
);
3465 line
= parse_operands (line
, mnemonic
);
3470 /* Now we've parsed the mnemonic into a set of templates, and have the
3471 operands at hand. */
3473 /* All intel opcodes have reversed operands except for "bound" and
3474 "enter". We also don't reverse intersegment "jmp" and "call"
3475 instructions with 2 immediate operands so that the immediate segment
3476 precedes the offset, as it does when in AT&T mode. */
3479 && (strcmp (mnemonic
, "bound") != 0)
3480 && (strcmp (mnemonic
, "invlpga") != 0)
3481 && !(operand_type_check (i
.types
[0], imm
)
3482 && operand_type_check (i
.types
[1], imm
)))
3485 /* The order of the immediates should be reversed
3486 for 2 immediates extrq and insertq instructions */
3487 if (i
.imm_operands
== 2
3488 && (strcmp (mnemonic
, "extrq") == 0
3489 || strcmp (mnemonic
, "insertq") == 0))
3490 swap_2_operands (0, 1);
3495 /* Don't optimize displacement for movabs since it only takes 64bit
3498 && i
.disp_encoding
!= disp_encoding_32bit
3499 && (flag_code
!= CODE_64BIT
3500 || strcmp (mnemonic
, "movabs") != 0))
3503 /* Next, we find a template that matches the given insn,
3504 making sure the overlap of the given operands types is consistent
3505 with the template operand types. */
3507 if (!(t
= match_template ()))
3510 if (sse_check
!= check_none
3511 && !i
.tm
.opcode_modifier
.noavx
3512 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3513 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3514 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3515 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3516 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3517 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3519 (sse_check
== check_warning
3521 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3524 /* Zap movzx and movsx suffix. The suffix has been set from
3525 "word ptr" or "byte ptr" on the source operand in Intel syntax
3526 or extracted from mnemonic in AT&T syntax. But we'll use
3527 the destination register to choose the suffix for encoding. */
3528 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3530 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3531 there is no suffix, the default will be byte extension. */
3532 if (i
.reg_operands
!= 2
3535 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3540 if (i
.tm
.opcode_modifier
.fwait
)
3541 if (!add_prefix (FWAIT_OPCODE
))
3544 /* Check if REP prefix is OK. */
3545 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3547 as_bad (_("invalid instruction `%s' after `%s'"),
3548 i
.tm
.name
, i
.rep_prefix
);
3552 /* Check for lock without a lockable instruction. Destination operand
3553 must be memory unless it is xchg (0x86). */
3554 if (i
.prefix
[LOCK_PREFIX
]
3555 && (!i
.tm
.opcode_modifier
.islockable
3556 || i
.mem_operands
== 0
3557 || (i
.tm
.base_opcode
!= 0x86
3558 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3560 as_bad (_("expecting lockable instruction after `lock'"));
3564 /* Check if HLE prefix is OK. */
3565 if (i
.hle_prefix
&& !check_hle ())
3568 /* Check BND prefix. */
3569 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3570 as_bad (_("expecting valid branch instruction after `bnd'"));
3572 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3573 && flag_code
== CODE_64BIT
3574 && i
.prefix
[ADDR_PREFIX
])
3575 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3577 /* Insert BND prefix. */
3579 && i
.tm
.opcode_modifier
.bndprefixok
3580 && !i
.prefix
[BND_PREFIX
])
3581 add_prefix (BND_PREFIX_OPCODE
);
3583 /* Check string instruction segment overrides. */
3584 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3586 if (!check_string ())
3588 i
.disp_operands
= 0;
3591 if (!process_suffix ())
3594 /* Update operand types. */
3595 for (j
= 0; j
< i
.operands
; j
++)
3596 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3598 /* Make still unresolved immediate matches conform to size of immediate
3599 given in i.suffix. */
3600 if (!finalize_imm ())
3603 if (i
.types
[0].bitfield
.imm1
)
3604 i
.imm_operands
= 0; /* kludge for shift insns. */
3606 /* We only need to check those implicit registers for instructions
3607 with 3 operands or less. */
3608 if (i
.operands
<= 3)
3609 for (j
= 0; j
< i
.operands
; j
++)
3610 if (i
.types
[j
].bitfield
.inoutportreg
3611 || i
.types
[j
].bitfield
.shiftcount
3612 || i
.types
[j
].bitfield
.acc
3613 || i
.types
[j
].bitfield
.floatacc
)
3616 /* ImmExt should be processed after SSE2AVX. */
3617 if (!i
.tm
.opcode_modifier
.sse2avx
3618 && i
.tm
.opcode_modifier
.immext
)
3621 /* For insns with operands there are more diddles to do to the opcode. */
3624 if (!process_operands ())
3627 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3629 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3630 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3633 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3635 if (flag_code
== CODE_16BIT
)
3637 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3642 if (i
.tm
.opcode_modifier
.vex
)
3643 build_vex_prefix (t
);
3645 build_evex_prefix ();
3648 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3649 instructions may define INT_OPCODE as well, so avoid this corner
3650 case for those instructions that use MODRM. */
3651 if (i
.tm
.base_opcode
== INT_OPCODE
3652 && !i
.tm
.opcode_modifier
.modrm
3653 && i
.op
[0].imms
->X_add_number
== 3)
3655 i
.tm
.base_opcode
= INT3_OPCODE
;
3659 if ((i
.tm
.opcode_modifier
.jump
3660 || i
.tm
.opcode_modifier
.jumpbyte
3661 || i
.tm
.opcode_modifier
.jumpdword
)
3662 && i
.op
[0].disps
->X_op
== O_constant
)
3664 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3665 the absolute address given by the constant. Since ix86 jumps and
3666 calls are pc relative, we need to generate a reloc. */
3667 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3668 i
.op
[0].disps
->X_op
= O_symbol
;
3671 if (i
.tm
.opcode_modifier
.rex64
)
3674 /* For 8 bit registers we need an empty rex prefix. Also if the
3675 instruction already has a prefix, we need to convert old
3676 registers to new ones. */
3678 if ((i
.types
[0].bitfield
.reg8
3679 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3680 || (i
.types
[1].bitfield
.reg8
3681 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3682 || ((i
.types
[0].bitfield
.reg8
3683 || i
.types
[1].bitfield
.reg8
)
3688 i
.rex
|= REX_OPCODE
;
3689 for (x
= 0; x
< 2; x
++)
3691 /* Look for 8 bit operand that uses old registers. */
3692 if (i
.types
[x
].bitfield
.reg8
3693 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3695 /* In case it is "hi" register, give up. */
3696 if (i
.op
[x
].regs
->reg_num
> 3)
3697 as_bad (_("can't encode register '%s%s' in an "
3698 "instruction requiring REX prefix."),
3699 register_prefix
, i
.op
[x
].regs
->reg_name
);
3701 /* Otherwise it is equivalent to the extended register.
3702 Since the encoding doesn't change this is merely
3703 cosmetic cleanup for debug output. */
3705 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3711 add_prefix (REX_OPCODE
| i
.rex
);
3713 /* We are ready to output the insn. */
3718 parse_insn (char *line
, char *mnemonic
)
3721 char *token_start
= l
;
3724 const insn_template
*t
;
3730 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3735 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3737 as_bad (_("no such instruction: `%s'"), token_start
);
3742 if (!is_space_char (*l
)
3743 && *l
!= END_OF_INSN
3745 || (*l
!= PREFIX_SEPARATOR
3748 as_bad (_("invalid character %s in mnemonic"),
3749 output_invalid (*l
));
3752 if (token_start
== l
)
3754 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3755 as_bad (_("expecting prefix; got nothing"));
3757 as_bad (_("expecting mnemonic; got nothing"));
3761 /* Look up instruction (or prefix) via hash table. */
3762 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3764 if (*l
!= END_OF_INSN
3765 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3766 && current_templates
3767 && current_templates
->start
->opcode_modifier
.isprefix
)
3769 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3771 as_bad ((flag_code
!= CODE_64BIT
3772 ? _("`%s' is only supported in 64-bit mode")
3773 : _("`%s' is not supported in 64-bit mode")),
3774 current_templates
->start
->name
);
3777 /* If we are in 16-bit mode, do not allow addr16 or data16.
3778 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3779 if ((current_templates
->start
->opcode_modifier
.size16
3780 || current_templates
->start
->opcode_modifier
.size32
)
3781 && flag_code
!= CODE_64BIT
3782 && (current_templates
->start
->opcode_modifier
.size32
3783 ^ (flag_code
== CODE_16BIT
)))
3785 as_bad (_("redundant %s prefix"),
3786 current_templates
->start
->name
);
3789 /* Add prefix, checking for repeated prefixes. */
3790 switch (add_prefix (current_templates
->start
->base_opcode
))
3795 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3796 i
.hle_prefix
= current_templates
->start
->name
;
3797 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3798 i
.bnd_prefix
= current_templates
->start
->name
;
3800 i
.rep_prefix
= current_templates
->start
->name
;
3805 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3812 if (!current_templates
)
3814 /* Check if we should swap operand or force 32bit displacement in
3816 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3818 else if (mnem_p
- 3 == dot_p
3821 i
.disp_encoding
= disp_encoding_8bit
;
3822 else if (mnem_p
- 4 == dot_p
3826 i
.disp_encoding
= disp_encoding_32bit
;
3831 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3834 if (!current_templates
)
3837 /* See if we can get a match by trimming off a suffix. */
3840 case WORD_MNEM_SUFFIX
:
3841 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3842 i
.suffix
= SHORT_MNEM_SUFFIX
;
3844 case BYTE_MNEM_SUFFIX
:
3845 case QWORD_MNEM_SUFFIX
:
3846 i
.suffix
= mnem_p
[-1];
3848 current_templates
= (const templates
*) hash_find (op_hash
,
3851 case SHORT_MNEM_SUFFIX
:
3852 case LONG_MNEM_SUFFIX
:
3855 i
.suffix
= mnem_p
[-1];
3857 current_templates
= (const templates
*) hash_find (op_hash
,
3866 if (intel_float_operand (mnemonic
) == 1)
3867 i
.suffix
= SHORT_MNEM_SUFFIX
;
3869 i
.suffix
= LONG_MNEM_SUFFIX
;
3871 current_templates
= (const templates
*) hash_find (op_hash
,
3876 if (!current_templates
)
3878 as_bad (_("no such instruction: `%s'"), token_start
);
3883 if (current_templates
->start
->opcode_modifier
.jump
3884 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3886 /* Check for a branch hint. We allow ",pt" and ",pn" for
3887 predict taken and predict not taken respectively.
3888 I'm not sure that branch hints actually do anything on loop
3889 and jcxz insns (JumpByte) for current Pentium4 chips. They
3890 may work in the future and it doesn't hurt to accept them
3892 if (l
[0] == ',' && l
[1] == 'p')
3896 if (!add_prefix (DS_PREFIX_OPCODE
))
3900 else if (l
[2] == 'n')
3902 if (!add_prefix (CS_PREFIX_OPCODE
))
3908 /* Any other comma loses. */
3911 as_bad (_("invalid character %s in mnemonic"),
3912 output_invalid (*l
));
3916 /* Check if instruction is supported on specified architecture. */
3918 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3920 supported
|= cpu_flags_match (t
);
3921 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3925 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3927 as_bad (flag_code
== CODE_64BIT
3928 ? _("`%s' is not supported in 64-bit mode")
3929 : _("`%s' is only supported in 64-bit mode"),
3930 current_templates
->start
->name
);
3933 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3935 as_bad (_("`%s' is not supported on `%s%s'"),
3936 current_templates
->start
->name
,
3937 cpu_arch_name
? cpu_arch_name
: default_arch
,
3938 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3943 if (!cpu_arch_flags
.bitfield
.cpui386
3944 && (flag_code
!= CODE_16BIT
))
3946 as_warn (_("use .code16 to ensure correct addressing mode"));
3953 parse_operands (char *l
, const char *mnemonic
)
3957 /* 1 if operand is pending after ','. */
3958 unsigned int expecting_operand
= 0;
3960 /* Non-zero if operand parens not balanced. */
3961 unsigned int paren_not_balanced
;
3963 while (*l
!= END_OF_INSN
)
3965 /* Skip optional white space before operand. */
3966 if (is_space_char (*l
))
3968 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
3970 as_bad (_("invalid character %s before operand %d"),
3971 output_invalid (*l
),
3975 token_start
= l
; /* After white space. */
3976 paren_not_balanced
= 0;
3977 while (paren_not_balanced
|| *l
!= ',')
3979 if (*l
== END_OF_INSN
)
3981 if (paren_not_balanced
)
3984 as_bad (_("unbalanced parenthesis in operand %d."),
3987 as_bad (_("unbalanced brackets in operand %d."),
3992 break; /* we are done */
3994 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
3996 as_bad (_("invalid character %s in operand %d"),
3997 output_invalid (*l
),
4004 ++paren_not_balanced
;
4006 --paren_not_balanced
;
4011 ++paren_not_balanced
;
4013 --paren_not_balanced
;
4017 if (l
!= token_start
)
4018 { /* Yes, we've read in another operand. */
4019 unsigned int operand_ok
;
4020 this_operand
= i
.operands
++;
4021 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4022 if (i
.operands
> MAX_OPERANDS
)
4024 as_bad (_("spurious operands; (%d operands/instruction max)"),
4028 /* Now parse operand adding info to 'i' as we go along. */
4029 END_STRING_AND_SAVE (l
);
4033 i386_intel_operand (token_start
,
4034 intel_float_operand (mnemonic
));
4036 operand_ok
= i386_att_operand (token_start
);
4038 RESTORE_END_STRING (l
);
4044 if (expecting_operand
)
4046 expecting_operand_after_comma
:
4047 as_bad (_("expecting operand after ','; got nothing"));
4052 as_bad (_("expecting operand before ','; got nothing"));
4057 /* Now *l must be either ',' or END_OF_INSN. */
4060 if (*++l
== END_OF_INSN
)
4062 /* Just skip it, if it's \n complain. */
4063 goto expecting_operand_after_comma
;
4065 expecting_operand
= 1;
4072 swap_2_operands (int xchg1
, int xchg2
)
4074 union i386_op temp_op
;
4075 i386_operand_type temp_type
;
4076 enum bfd_reloc_code_real temp_reloc
;
4078 temp_type
= i
.types
[xchg2
];
4079 i
.types
[xchg2
] = i
.types
[xchg1
];
4080 i
.types
[xchg1
] = temp_type
;
4081 temp_op
= i
.op
[xchg2
];
4082 i
.op
[xchg2
] = i
.op
[xchg1
];
4083 i
.op
[xchg1
] = temp_op
;
4084 temp_reloc
= i
.reloc
[xchg2
];
4085 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4086 i
.reloc
[xchg1
] = temp_reloc
;
4090 if (i
.mask
->operand
== xchg1
)
4091 i
.mask
->operand
= xchg2
;
4092 else if (i
.mask
->operand
== xchg2
)
4093 i
.mask
->operand
= xchg1
;
4097 if (i
.broadcast
->operand
== xchg1
)
4098 i
.broadcast
->operand
= xchg2
;
4099 else if (i
.broadcast
->operand
== xchg2
)
4100 i
.broadcast
->operand
= xchg1
;
4104 if (i
.rounding
->operand
== xchg1
)
4105 i
.rounding
->operand
= xchg2
;
4106 else if (i
.rounding
->operand
== xchg2
)
4107 i
.rounding
->operand
= xchg1
;
4112 swap_operands (void)
4118 swap_2_operands (1, i
.operands
- 2);
4121 swap_2_operands (0, i
.operands
- 1);
4127 if (i
.mem_operands
== 2)
4129 const seg_entry
*temp_seg
;
4130 temp_seg
= i
.seg
[0];
4131 i
.seg
[0] = i
.seg
[1];
4132 i
.seg
[1] = temp_seg
;
4136 /* Try to ensure constant immediates are represented in the smallest
4141 char guess_suffix
= 0;
4145 guess_suffix
= i
.suffix
;
4146 else if (i
.reg_operands
)
4148 /* Figure out a suffix from the last register operand specified.
4149 We can't do this properly yet, ie. excluding InOutPortReg,
4150 but the following works for instructions with immediates.
4151 In any case, we can't set i.suffix yet. */
4152 for (op
= i
.operands
; --op
>= 0;)
4153 if (i
.types
[op
].bitfield
.reg8
)
4155 guess_suffix
= BYTE_MNEM_SUFFIX
;
4158 else if (i
.types
[op
].bitfield
.reg16
)
4160 guess_suffix
= WORD_MNEM_SUFFIX
;
4163 else if (i
.types
[op
].bitfield
.reg32
)
4165 guess_suffix
= LONG_MNEM_SUFFIX
;
4168 else if (i
.types
[op
].bitfield
.reg64
)
4170 guess_suffix
= QWORD_MNEM_SUFFIX
;
4174 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4175 guess_suffix
= WORD_MNEM_SUFFIX
;
4177 for (op
= i
.operands
; --op
>= 0;)
4178 if (operand_type_check (i
.types
[op
], imm
))
4180 switch (i
.op
[op
].imms
->X_op
)
4183 /* If a suffix is given, this operand may be shortened. */
4184 switch (guess_suffix
)
4186 case LONG_MNEM_SUFFIX
:
4187 i
.types
[op
].bitfield
.imm32
= 1;
4188 i
.types
[op
].bitfield
.imm64
= 1;
4190 case WORD_MNEM_SUFFIX
:
4191 i
.types
[op
].bitfield
.imm16
= 1;
4192 i
.types
[op
].bitfield
.imm32
= 1;
4193 i
.types
[op
].bitfield
.imm32s
= 1;
4194 i
.types
[op
].bitfield
.imm64
= 1;
4196 case BYTE_MNEM_SUFFIX
:
4197 i
.types
[op
].bitfield
.imm8
= 1;
4198 i
.types
[op
].bitfield
.imm8s
= 1;
4199 i
.types
[op
].bitfield
.imm16
= 1;
4200 i
.types
[op
].bitfield
.imm32
= 1;
4201 i
.types
[op
].bitfield
.imm32s
= 1;
4202 i
.types
[op
].bitfield
.imm64
= 1;
4206 /* If this operand is at most 16 bits, convert it
4207 to a signed 16 bit number before trying to see
4208 whether it will fit in an even smaller size.
4209 This allows a 16-bit operand such as $0xffe0 to
4210 be recognised as within Imm8S range. */
4211 if ((i
.types
[op
].bitfield
.imm16
)
4212 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4214 i
.op
[op
].imms
->X_add_number
=
4215 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4217 if ((i
.types
[op
].bitfield
.imm32
)
4218 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4221 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4222 ^ ((offsetT
) 1 << 31))
4223 - ((offsetT
) 1 << 31));
4226 = operand_type_or (i
.types
[op
],
4227 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4229 /* We must avoid matching of Imm32 templates when 64bit
4230 only immediate is available. */
4231 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4232 i
.types
[op
].bitfield
.imm32
= 0;
4239 /* Symbols and expressions. */
4241 /* Convert symbolic operand to proper sizes for matching, but don't
4242 prevent matching a set of insns that only supports sizes other
4243 than those matching the insn suffix. */
4245 i386_operand_type mask
, allowed
;
4246 const insn_template
*t
;
4248 operand_type_set (&mask
, 0);
4249 operand_type_set (&allowed
, 0);
4251 for (t
= current_templates
->start
;
4252 t
< current_templates
->end
;
4254 allowed
= operand_type_or (allowed
,
4255 t
->operand_types
[op
]);
4256 switch (guess_suffix
)
4258 case QWORD_MNEM_SUFFIX
:
4259 mask
.bitfield
.imm64
= 1;
4260 mask
.bitfield
.imm32s
= 1;
4262 case LONG_MNEM_SUFFIX
:
4263 mask
.bitfield
.imm32
= 1;
4265 case WORD_MNEM_SUFFIX
:
4266 mask
.bitfield
.imm16
= 1;
4268 case BYTE_MNEM_SUFFIX
:
4269 mask
.bitfield
.imm8
= 1;
4274 allowed
= operand_type_and (mask
, allowed
);
4275 if (!operand_type_all_zero (&allowed
))
4276 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4283 /* Try to use the smallest displacement type too. */
4285 optimize_disp (void)
4289 for (op
= i
.operands
; --op
>= 0;)
4290 if (operand_type_check (i
.types
[op
], disp
))
4292 if (i
.op
[op
].disps
->X_op
== O_constant
)
4294 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4296 if (i
.types
[op
].bitfield
.disp16
4297 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4299 /* If this operand is at most 16 bits, convert
4300 to a signed 16 bit number and don't use 64bit
4302 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4303 i
.types
[op
].bitfield
.disp64
= 0;
4305 if (i
.types
[op
].bitfield
.disp32
4306 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4308 /* If this operand is at most 32 bits, convert
4309 to a signed 32 bit number and don't use 64bit
4311 op_disp
&= (((offsetT
) 2 << 31) - 1);
4312 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4313 i
.types
[op
].bitfield
.disp64
= 0;
4315 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4317 i
.types
[op
].bitfield
.disp8
= 0;
4318 i
.types
[op
].bitfield
.disp16
= 0;
4319 i
.types
[op
].bitfield
.disp32
= 0;
4320 i
.types
[op
].bitfield
.disp32s
= 0;
4321 i
.types
[op
].bitfield
.disp64
= 0;
4325 else if (flag_code
== CODE_64BIT
)
4327 if (fits_in_signed_long (op_disp
))
4329 i
.types
[op
].bitfield
.disp64
= 0;
4330 i
.types
[op
].bitfield
.disp32s
= 1;
4332 if (i
.prefix
[ADDR_PREFIX
]
4333 && fits_in_unsigned_long (op_disp
))
4334 i
.types
[op
].bitfield
.disp32
= 1;
4336 if ((i
.types
[op
].bitfield
.disp32
4337 || i
.types
[op
].bitfield
.disp32s
4338 || i
.types
[op
].bitfield
.disp16
)
4339 && fits_in_signed_byte (op_disp
))
4340 i
.types
[op
].bitfield
.disp8
= 1;
4342 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4343 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4345 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4346 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4347 i
.types
[op
].bitfield
.disp8
= 0;
4348 i
.types
[op
].bitfield
.disp16
= 0;
4349 i
.types
[op
].bitfield
.disp32
= 0;
4350 i
.types
[op
].bitfield
.disp32s
= 0;
4351 i
.types
[op
].bitfield
.disp64
= 0;
4354 /* We only support 64bit displacement on constants. */
4355 i
.types
[op
].bitfield
.disp64
= 0;
4359 /* Check if operands are valid for the instruction. */
4362 check_VecOperands (const insn_template
*t
)
4366 /* Without VSIB byte, we can't have a vector register for index. */
4367 if (!t
->opcode_modifier
.vecsib
4369 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4370 || i
.index_reg
->reg_type
.bitfield
.regymm
4371 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4373 i
.error
= unsupported_vector_index_register
;
4377 /* Check if default mask is allowed. */
4378 if (t
->opcode_modifier
.nodefmask
4379 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4381 i
.error
= no_default_mask
;
4385 /* For VSIB byte, we need a vector register for index, and all vector
4386 registers must be distinct. */
4387 if (t
->opcode_modifier
.vecsib
)
4390 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4391 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4392 || (t
->opcode_modifier
.vecsib
== VecSIB256
4393 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4394 || (t
->opcode_modifier
.vecsib
== VecSIB512
4395 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4397 i
.error
= invalid_vsib_address
;
4401 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4402 if (i
.reg_operands
== 2 && !i
.mask
)
4404 gas_assert (i
.types
[0].bitfield
.regxmm
4405 || i
.types
[0].bitfield
.regymm
);
4406 gas_assert (i
.types
[2].bitfield
.regxmm
4407 || i
.types
[2].bitfield
.regymm
);
4408 if (operand_check
== check_none
)
4410 if (register_number (i
.op
[0].regs
)
4411 != register_number (i
.index_reg
)
4412 && register_number (i
.op
[2].regs
)
4413 != register_number (i
.index_reg
)
4414 && register_number (i
.op
[0].regs
)
4415 != register_number (i
.op
[2].regs
))
4417 if (operand_check
== check_error
)
4419 i
.error
= invalid_vector_register_set
;
4422 as_warn (_("mask, index, and destination registers should be distinct"));
4424 else if (i
.reg_operands
== 1 && i
.mask
)
4426 if ((i
.types
[1].bitfield
.regymm
4427 || i
.types
[1].bitfield
.regzmm
)
4428 && (register_number (i
.op
[1].regs
)
4429 == register_number (i
.index_reg
)))
4431 if (operand_check
== check_error
)
4433 i
.error
= invalid_vector_register_set
;
4436 if (operand_check
!= check_none
)
4437 as_warn (_("index and destination registers should be distinct"));
4442 /* Check if broadcast is supported by the instruction and is applied
4443 to the memory operand. */
4446 int broadcasted_opnd_size
;
4448 /* Check if specified broadcast is supported in this instruction,
4449 and it's applied to memory operand of DWORD or QWORD type,
4450 depending on VecESize. */
4451 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4452 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4453 || (t
->opcode_modifier
.vecesize
== 0
4454 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4455 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4456 || (t
->opcode_modifier
.vecesize
== 1
4457 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4458 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4461 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4462 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4463 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4464 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4465 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4466 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4467 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4468 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4469 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4473 if ((broadcasted_opnd_size
== 256
4474 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4475 || (broadcasted_opnd_size
== 512
4476 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4479 i
.error
= unsupported_broadcast
;
4483 /* If broadcast is supported in this instruction, we need to check if
4484 operand of one-element size isn't specified without broadcast. */
4485 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4487 /* Find memory operand. */
4488 for (op
= 0; op
< i
.operands
; op
++)
4489 if (operand_type_check (i
.types
[op
], anymem
))
4491 gas_assert (op
< i
.operands
);
4492 /* Check size of the memory operand. */
4493 if ((t
->opcode_modifier
.vecesize
== 0
4494 && i
.types
[op
].bitfield
.dword
)
4495 || (t
->opcode_modifier
.vecesize
== 1
4496 && i
.types
[op
].bitfield
.qword
))
4498 i
.error
= broadcast_needed
;
4503 /* Check if requested masking is supported. */
4505 && (!t
->opcode_modifier
.masking
4507 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4509 i
.error
= unsupported_masking
;
4513 /* Check if masking is applied to dest operand. */
4514 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4516 i
.error
= mask_not_on_destination
;
4523 if ((i
.rounding
->type
!= saeonly
4524 && !t
->opcode_modifier
.staticrounding
)
4525 || (i
.rounding
->type
== saeonly
4526 && (t
->opcode_modifier
.staticrounding
4527 || !t
->opcode_modifier
.sae
)))
4529 i
.error
= unsupported_rc_sae
;
4532 /* If the instruction has several immediate operands and one of
4533 them is rounding, the rounding operand should be the last
4534 immediate operand. */
4535 if (i
.imm_operands
> 1
4536 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4538 i
.error
= rc_sae_operand_not_last_imm
;
4543 /* Check vector Disp8 operand. */
4544 if (t
->opcode_modifier
.disp8memshift
)
4547 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4549 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4551 for (op
= 0; op
< i
.operands
; op
++)
4552 if (operand_type_check (i
.types
[op
], disp
)
4553 && i
.op
[op
].disps
->X_op
== O_constant
)
4555 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4556 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4557 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4560 i
.types
[op
].bitfield
.vec_disp8
= 1;
4563 /* Vector insn can only have Vec_Disp8/Disp32 in
4564 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4566 i
.types
[op
].bitfield
.disp8
= 0;
4567 if (flag_code
!= CODE_16BIT
)
4568 i
.types
[op
].bitfield
.disp16
= 0;
4571 else if (flag_code
!= CODE_16BIT
)
4573 /* One form of this instruction supports vector Disp8.
4574 Try vector Disp8 if we need to use Disp32. */
4575 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4577 i
.error
= try_vector_disp8
;
4589 /* Check if operands are valid for the instruction. Update VEX
4593 VEX_check_operands (const insn_template
*t
)
4595 /* VREX is only valid with EVEX prefix. */
4596 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4598 i
.error
= invalid_register_operand
;
4602 if (!t
->opcode_modifier
.vex
)
4605 /* Only check VEX_Imm4, which must be the first operand. */
4606 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4608 if (i
.op
[0].imms
->X_op
!= O_constant
4609 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4615 /* Turn off Imm8 so that update_imm won't complain. */
4616 i
.types
[0] = vec_imm4
;
4622 static const insn_template
*
4623 match_template (void)
4625 /* Points to template once we've found it. */
4626 const insn_template
*t
;
4627 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4628 i386_operand_type overlap4
;
4629 unsigned int found_reverse_match
;
4630 i386_opcode_modifier suffix_check
;
4631 i386_operand_type operand_types
[MAX_OPERANDS
];
4632 int addr_prefix_disp
;
4634 unsigned int found_cpu_match
;
4635 unsigned int check_register
;
4636 enum i386_error specific_error
= 0;
4638 #if MAX_OPERANDS != 5
4639 # error "MAX_OPERANDS must be 5."
4642 found_reverse_match
= 0;
4643 addr_prefix_disp
= -1;
4645 memset (&suffix_check
, 0, sizeof (suffix_check
));
4646 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4647 suffix_check
.no_bsuf
= 1;
4648 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4649 suffix_check
.no_wsuf
= 1;
4650 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4651 suffix_check
.no_ssuf
= 1;
4652 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4653 suffix_check
.no_lsuf
= 1;
4654 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4655 suffix_check
.no_qsuf
= 1;
4656 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4657 suffix_check
.no_ldsuf
= 1;
4659 /* Must have right number of operands. */
4660 i
.error
= number_of_operands_mismatch
;
4662 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4664 addr_prefix_disp
= -1;
4666 if (i
.operands
!= t
->operands
)
4669 /* Check processor support. */
4670 i
.error
= unsupported
;
4671 found_cpu_match
= (cpu_flags_match (t
)
4672 == CPU_FLAGS_PERFECT_MATCH
);
4673 if (!found_cpu_match
)
4676 /* Check old gcc support. */
4677 i
.error
= old_gcc_only
;
4678 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4681 /* Check AT&T mnemonic. */
4682 i
.error
= unsupported_with_intel_mnemonic
;
4683 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4686 /* Check AT&T/Intel syntax. */
4687 i
.error
= unsupported_syntax
;
4688 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4689 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4692 /* Check the suffix, except for some instructions in intel mode. */
4693 i
.error
= invalid_instruction_suffix
;
4694 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4695 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4696 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4697 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4698 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4699 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4700 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4703 if (!operand_size_match (t
))
4706 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4707 operand_types
[j
] = t
->operand_types
[j
];
4709 /* In general, don't allow 64-bit operands in 32-bit mode. */
4710 if (i
.suffix
== QWORD_MNEM_SUFFIX
4711 && flag_code
!= CODE_64BIT
4713 ? (!t
->opcode_modifier
.ignoresize
4714 && !intel_float_operand (t
->name
))
4715 : intel_float_operand (t
->name
) != 2)
4716 && ((!operand_types
[0].bitfield
.regmmx
4717 && !operand_types
[0].bitfield
.regxmm
4718 && !operand_types
[0].bitfield
.regymm
4719 && !operand_types
[0].bitfield
.regzmm
)
4720 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4721 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4722 && operand_types
[t
->operands
> 1].bitfield
.regymm
4723 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4724 && (t
->base_opcode
!= 0x0fc7
4725 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4728 /* In general, don't allow 32-bit operands on pre-386. */
4729 else if (i
.suffix
== LONG_MNEM_SUFFIX
4730 && !cpu_arch_flags
.bitfield
.cpui386
4732 ? (!t
->opcode_modifier
.ignoresize
4733 && !intel_float_operand (t
->name
))
4734 : intel_float_operand (t
->name
) != 2)
4735 && ((!operand_types
[0].bitfield
.regmmx
4736 && !operand_types
[0].bitfield
.regxmm
)
4737 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4738 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4741 /* Do not verify operands when there are none. */
4745 /* We've found a match; break out of loop. */
4749 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4750 into Disp32/Disp16/Disp32 operand. */
4751 if (i
.prefix
[ADDR_PREFIX
] != 0)
4753 /* There should be only one Disp operand. */
4757 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4759 if (operand_types
[j
].bitfield
.disp16
)
4761 addr_prefix_disp
= j
;
4762 operand_types
[j
].bitfield
.disp32
= 1;
4763 operand_types
[j
].bitfield
.disp16
= 0;
4769 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4771 if (operand_types
[j
].bitfield
.disp32
)
4773 addr_prefix_disp
= j
;
4774 operand_types
[j
].bitfield
.disp32
= 0;
4775 operand_types
[j
].bitfield
.disp16
= 1;
4781 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4783 if (operand_types
[j
].bitfield
.disp64
)
4785 addr_prefix_disp
= j
;
4786 operand_types
[j
].bitfield
.disp64
= 0;
4787 operand_types
[j
].bitfield
.disp32
= 1;
4795 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4796 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
4799 /* We check register size if needed. */
4800 check_register
= t
->opcode_modifier
.checkregsize
;
4801 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4802 switch (t
->operands
)
4805 if (!operand_type_match (overlap0
, i
.types
[0]))
4809 /* xchg %eax, %eax is a special case. It is an aliase for nop
4810 only in 32bit mode and we can use opcode 0x90. In 64bit
4811 mode, we can't use 0x90 for xchg %eax, %eax since it should
4812 zero-extend %eax to %rax. */
4813 if (flag_code
== CODE_64BIT
4814 && t
->base_opcode
== 0x90
4815 && operand_type_equal (&i
.types
[0], &acc32
)
4816 && operand_type_equal (&i
.types
[1], &acc32
))
4820 /* If we swap operand in encoding, we either match
4821 the next one or reverse direction of operands. */
4822 if (t
->opcode_modifier
.s
)
4824 else if (t
->opcode_modifier
.d
)
4829 /* If we swap operand in encoding, we match the next one. */
4830 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4834 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4835 if (!operand_type_match (overlap0
, i
.types
[0])
4836 || !operand_type_match (overlap1
, i
.types
[1])
4838 && !operand_type_register_match (overlap0
, i
.types
[0],
4840 overlap1
, i
.types
[1],
4843 /* Check if other direction is valid ... */
4844 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4848 /* Try reversing direction of operands. */
4849 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4850 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4851 if (!operand_type_match (overlap0
, i
.types
[0])
4852 || !operand_type_match (overlap1
, i
.types
[1])
4854 && !operand_type_register_match (overlap0
,
4861 /* Does not match either direction. */
4864 /* found_reverse_match holds which of D or FloatDR
4866 if (t
->opcode_modifier
.d
)
4867 found_reverse_match
= Opcode_D
;
4868 else if (t
->opcode_modifier
.floatd
)
4869 found_reverse_match
= Opcode_FloatD
;
4871 found_reverse_match
= 0;
4872 if (t
->opcode_modifier
.floatr
)
4873 found_reverse_match
|= Opcode_FloatR
;
4877 /* Found a forward 2 operand match here. */
4878 switch (t
->operands
)
4881 overlap4
= operand_type_and (i
.types
[4],
4884 overlap3
= operand_type_and (i
.types
[3],
4887 overlap2
= operand_type_and (i
.types
[2],
4892 switch (t
->operands
)
4895 if (!operand_type_match (overlap4
, i
.types
[4])
4896 || !operand_type_register_match (overlap3
,
4904 if (!operand_type_match (overlap3
, i
.types
[3])
4906 && !operand_type_register_match (overlap2
,
4914 /* Here we make use of the fact that there are no
4915 reverse match 3 operand instructions, and all 3
4916 operand instructions only need to be checked for
4917 register consistency between operands 2 and 3. */
4918 if (!operand_type_match (overlap2
, i
.types
[2])
4920 && !operand_type_register_match (overlap1
,
4930 /* Found either forward/reverse 2, 3 or 4 operand match here:
4931 slip through to break. */
4933 if (!found_cpu_match
)
4935 found_reverse_match
= 0;
4939 /* Check if vector and VEX operands are valid. */
4940 if (check_VecOperands (t
) || VEX_check_operands (t
))
4942 specific_error
= i
.error
;
4946 /* We've found a match; break out of loop. */
4950 if (t
== current_templates
->end
)
4952 /* We found no match. */
4953 const char *err_msg
;
4954 switch (specific_error
? specific_error
: i
.error
)
4958 case operand_size_mismatch
:
4959 err_msg
= _("operand size mismatch");
4961 case operand_type_mismatch
:
4962 err_msg
= _("operand type mismatch");
4964 case register_type_mismatch
:
4965 err_msg
= _("register type mismatch");
4967 case number_of_operands_mismatch
:
4968 err_msg
= _("number of operands mismatch");
4970 case invalid_instruction_suffix
:
4971 err_msg
= _("invalid instruction suffix");
4974 err_msg
= _("constant doesn't fit in 4 bits");
4977 err_msg
= _("only supported with old gcc");
4979 case unsupported_with_intel_mnemonic
:
4980 err_msg
= _("unsupported with Intel mnemonic");
4982 case unsupported_syntax
:
4983 err_msg
= _("unsupported syntax");
4986 as_bad (_("unsupported instruction `%s'"),
4987 current_templates
->start
->name
);
4989 case invalid_vsib_address
:
4990 err_msg
= _("invalid VSIB address");
4992 case invalid_vector_register_set
:
4993 err_msg
= _("mask, index, and destination registers must be distinct");
4995 case unsupported_vector_index_register
:
4996 err_msg
= _("unsupported vector index register");
4998 case unsupported_broadcast
:
4999 err_msg
= _("unsupported broadcast");
5001 case broadcast_not_on_src_operand
:
5002 err_msg
= _("broadcast not on source memory operand");
5004 case broadcast_needed
:
5005 err_msg
= _("broadcast is needed for operand of such type");
5007 case unsupported_masking
:
5008 err_msg
= _("unsupported masking");
5010 case mask_not_on_destination
:
5011 err_msg
= _("mask not on destination operand");
5013 case no_default_mask
:
5014 err_msg
= _("default mask isn't allowed");
5016 case unsupported_rc_sae
:
5017 err_msg
= _("unsupported static rounding/sae");
5019 case rc_sae_operand_not_last_imm
:
5021 err_msg
= _("RC/SAE operand must precede immediate operands");
5023 err_msg
= _("RC/SAE operand must follow immediate operands");
5025 case invalid_register_operand
:
5026 err_msg
= _("invalid register operand");
5029 as_bad (_("%s for `%s'"), err_msg
,
5030 current_templates
->start
->name
);
5034 if (!quiet_warnings
)
5037 && (i
.types
[0].bitfield
.jumpabsolute
5038 != operand_types
[0].bitfield
.jumpabsolute
))
5040 as_warn (_("indirect %s without `*'"), t
->name
);
5043 if (t
->opcode_modifier
.isprefix
5044 && t
->opcode_modifier
.ignoresize
)
5046 /* Warn them that a data or address size prefix doesn't
5047 affect assembly of the next line of code. */
5048 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5052 /* Copy the template we found. */
5055 if (addr_prefix_disp
!= -1)
5056 i
.tm
.operand_types
[addr_prefix_disp
]
5057 = operand_types
[addr_prefix_disp
];
5059 if (found_reverse_match
)
5061 /* If we found a reverse match we must alter the opcode
5062 direction bit. found_reverse_match holds bits to change
5063 (different for int & float insns). */
5065 i
.tm
.base_opcode
^= found_reverse_match
;
5067 i
.tm
.operand_types
[0] = operand_types
[1];
5068 i
.tm
.operand_types
[1] = operand_types
[0];
5077 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5078 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5080 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5082 as_bad (_("`%s' operand %d must use `%ses' segment"),
5088 /* There's only ever one segment override allowed per instruction.
5089 This instruction possibly has a legal segment override on the
5090 second operand, so copy the segment to where non-string
5091 instructions store it, allowing common code. */
5092 i
.seg
[0] = i
.seg
[1];
5094 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5096 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5098 as_bad (_("`%s' operand %d must use `%ses' segment"),
5109 process_suffix (void)
5111 /* If matched instruction specifies an explicit instruction mnemonic
5113 if (i
.tm
.opcode_modifier
.size16
)
5114 i
.suffix
= WORD_MNEM_SUFFIX
;
5115 else if (i
.tm
.opcode_modifier
.size32
)
5116 i
.suffix
= LONG_MNEM_SUFFIX
;
5117 else if (i
.tm
.opcode_modifier
.size64
)
5118 i
.suffix
= QWORD_MNEM_SUFFIX
;
5119 else if (i
.reg_operands
)
5121 /* If there's no instruction mnemonic suffix we try to invent one
5122 based on register operands. */
5125 /* We take i.suffix from the last register operand specified,
5126 Destination register type is more significant than source
5127 register type. crc32 in SSE4.2 prefers source register
5129 if (i
.tm
.base_opcode
== 0xf20f38f1)
5131 if (i
.types
[0].bitfield
.reg16
)
5132 i
.suffix
= WORD_MNEM_SUFFIX
;
5133 else if (i
.types
[0].bitfield
.reg32
)
5134 i
.suffix
= LONG_MNEM_SUFFIX
;
5135 else if (i
.types
[0].bitfield
.reg64
)
5136 i
.suffix
= QWORD_MNEM_SUFFIX
;
5138 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5140 if (i
.types
[0].bitfield
.reg8
)
5141 i
.suffix
= BYTE_MNEM_SUFFIX
;
5148 if (i
.tm
.base_opcode
== 0xf20f38f1
5149 || i
.tm
.base_opcode
== 0xf20f38f0)
5151 /* We have to know the operand size for crc32. */
5152 as_bad (_("ambiguous memory operand size for `%s`"),
5157 for (op
= i
.operands
; --op
>= 0;)
5158 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5160 if (i
.types
[op
].bitfield
.reg8
)
5162 i
.suffix
= BYTE_MNEM_SUFFIX
;
5165 else if (i
.types
[op
].bitfield
.reg16
)
5167 i
.suffix
= WORD_MNEM_SUFFIX
;
5170 else if (i
.types
[op
].bitfield
.reg32
)
5172 i
.suffix
= LONG_MNEM_SUFFIX
;
5175 else if (i
.types
[op
].bitfield
.reg64
)
5177 i
.suffix
= QWORD_MNEM_SUFFIX
;
5183 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5186 && i
.tm
.opcode_modifier
.ignoresize
5187 && i
.tm
.opcode_modifier
.no_bsuf
)
5189 else if (!check_byte_reg ())
5192 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5195 && i
.tm
.opcode_modifier
.ignoresize
5196 && i
.tm
.opcode_modifier
.no_lsuf
)
5198 else if (!check_long_reg ())
5201 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5204 && i
.tm
.opcode_modifier
.ignoresize
5205 && i
.tm
.opcode_modifier
.no_qsuf
)
5207 else if (!check_qword_reg ())
5210 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5213 && i
.tm
.opcode_modifier
.ignoresize
5214 && i
.tm
.opcode_modifier
.no_wsuf
)
5216 else if (!check_word_reg ())
5219 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5220 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5221 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5223 /* Skip if the instruction has x/y/z suffix. match_template
5224 should check if it is a valid suffix. */
5226 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5227 /* Do nothing if the instruction is going to ignore the prefix. */
5232 else if (i
.tm
.opcode_modifier
.defaultsize
5234 /* exclude fldenv/frstor/fsave/fstenv */
5235 && i
.tm
.opcode_modifier
.no_ssuf
)
5237 i
.suffix
= stackop_size
;
5239 else if (intel_syntax
5241 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5242 || i
.tm
.opcode_modifier
.jumpbyte
5243 || i
.tm
.opcode_modifier
.jumpintersegment
5244 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5245 && i
.tm
.extension_opcode
<= 3)))
5250 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5252 i
.suffix
= QWORD_MNEM_SUFFIX
;
5256 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5257 i
.suffix
= LONG_MNEM_SUFFIX
;
5260 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5261 i
.suffix
= WORD_MNEM_SUFFIX
;
5270 if (i
.tm
.opcode_modifier
.w
)
5272 as_bad (_("no instruction mnemonic suffix given and "
5273 "no register operands; can't size instruction"));
5279 unsigned int suffixes
;
5281 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5282 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5284 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5286 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5288 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5290 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5293 /* There are more than suffix matches. */
5294 if (i
.tm
.opcode_modifier
.w
5295 || ((suffixes
& (suffixes
- 1))
5296 && !i
.tm
.opcode_modifier
.defaultsize
5297 && !i
.tm
.opcode_modifier
.ignoresize
))
5299 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5305 /* Change the opcode based on the operand size given by i.suffix;
5306 We don't need to change things for byte insns. */
5309 && i
.suffix
!= BYTE_MNEM_SUFFIX
5310 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5311 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5312 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5314 /* It's not a byte, select word/dword operation. */
5315 if (i
.tm
.opcode_modifier
.w
)
5317 if (i
.tm
.opcode_modifier
.shortform
)
5318 i
.tm
.base_opcode
|= 8;
5320 i
.tm
.base_opcode
|= 1;
5323 /* Now select between word & dword operations via the operand
5324 size prefix, except for instructions that will ignore this
5326 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5328 /* The address size override prefix changes the size of the
5330 if ((flag_code
== CODE_32BIT
5331 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5332 || (flag_code
!= CODE_32BIT
5333 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5334 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5337 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5338 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5339 && !i
.tm
.opcode_modifier
.ignoresize
5340 && !i
.tm
.opcode_modifier
.floatmf
5341 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5342 || (flag_code
== CODE_64BIT
5343 && i
.tm
.opcode_modifier
.jumpbyte
)))
5345 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5347 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5348 prefix
= ADDR_PREFIX_OPCODE
;
5350 if (!add_prefix (prefix
))
5354 /* Set mode64 for an operand. */
5355 if (i
.suffix
== QWORD_MNEM_SUFFIX
5356 && flag_code
== CODE_64BIT
5357 && !i
.tm
.opcode_modifier
.norex64
)
5359 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5360 need rex64. cmpxchg8b is also a special case. */
5361 if (! (i
.operands
== 2
5362 && i
.tm
.base_opcode
== 0x90
5363 && i
.tm
.extension_opcode
== None
5364 && operand_type_equal (&i
.types
[0], &acc64
)
5365 && operand_type_equal (&i
.types
[1], &acc64
))
5366 && ! (i
.operands
== 1
5367 && i
.tm
.base_opcode
== 0xfc7
5368 && i
.tm
.extension_opcode
== 1
5369 && !operand_type_check (i
.types
[0], reg
)
5370 && operand_type_check (i
.types
[0], anymem
)))
5374 /* Size floating point instruction. */
5375 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5376 if (i
.tm
.opcode_modifier
.floatmf
)
5377 i
.tm
.base_opcode
^= 4;
5384 check_byte_reg (void)
5388 for (op
= i
.operands
; --op
>= 0;)
5390 /* If this is an eight bit register, it's OK. If it's the 16 or
5391 32 bit version of an eight bit register, we will just use the
5392 low portion, and that's OK too. */
5393 if (i
.types
[op
].bitfield
.reg8
)
5396 /* I/O port address operands are OK too. */
5397 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5400 /* crc32 doesn't generate this warning. */
5401 if (i
.tm
.base_opcode
== 0xf20f38f0)
5404 if ((i
.types
[op
].bitfield
.reg16
5405 || i
.types
[op
].bitfield
.reg32
5406 || i
.types
[op
].bitfield
.reg64
)
5407 && i
.op
[op
].regs
->reg_num
< 4
5408 /* Prohibit these changes in 64bit mode, since the lowering
5409 would be more complicated. */
5410 && flag_code
!= CODE_64BIT
)
5412 #if REGISTER_WARNINGS
5413 if (!quiet_warnings
)
5414 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5416 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5417 ? REGNAM_AL
- REGNAM_AX
5418 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5420 i
.op
[op
].regs
->reg_name
,
5425 /* Any other register is bad. */
5426 if (i
.types
[op
].bitfield
.reg16
5427 || i
.types
[op
].bitfield
.reg32
5428 || i
.types
[op
].bitfield
.reg64
5429 || i
.types
[op
].bitfield
.regmmx
5430 || i
.types
[op
].bitfield
.regxmm
5431 || i
.types
[op
].bitfield
.regymm
5432 || i
.types
[op
].bitfield
.regzmm
5433 || i
.types
[op
].bitfield
.sreg2
5434 || i
.types
[op
].bitfield
.sreg3
5435 || i
.types
[op
].bitfield
.control
5436 || i
.types
[op
].bitfield
.debug
5437 || i
.types
[op
].bitfield
.test
5438 || i
.types
[op
].bitfield
.floatreg
5439 || i
.types
[op
].bitfield
.floatacc
)
5441 as_bad (_("`%s%s' not allowed with `%s%c'"),
5443 i
.op
[op
].regs
->reg_name
,
5453 check_long_reg (void)
5457 for (op
= i
.operands
; --op
>= 0;)
5458 /* Reject eight bit registers, except where the template requires
5459 them. (eg. movzb) */
5460 if (i
.types
[op
].bitfield
.reg8
5461 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5462 || i
.tm
.operand_types
[op
].bitfield
.reg32
5463 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5465 as_bad (_("`%s%s' not allowed with `%s%c'"),
5467 i
.op
[op
].regs
->reg_name
,
5472 /* Warn if the e prefix on a general reg is missing. */
5473 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5474 && i
.types
[op
].bitfield
.reg16
5475 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5476 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5478 /* Prohibit these changes in the 64bit mode, since the
5479 lowering is more complicated. */
5480 if (flag_code
== CODE_64BIT
)
5482 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5483 register_prefix
, i
.op
[op
].regs
->reg_name
,
5487 #if REGISTER_WARNINGS
5488 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5490 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5491 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5494 /* Warn if the r prefix on a general reg is present. */
5495 else if (i
.types
[op
].bitfield
.reg64
5496 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5497 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5500 && i
.tm
.opcode_modifier
.toqword
5501 && !i
.types
[0].bitfield
.regxmm
)
5503 /* Convert to QWORD. We want REX byte. */
5504 i
.suffix
= QWORD_MNEM_SUFFIX
;
5508 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5509 register_prefix
, i
.op
[op
].regs
->reg_name
,
5518 check_qword_reg (void)
5522 for (op
= i
.operands
; --op
>= 0; )
5523 /* Reject eight bit registers, except where the template requires
5524 them. (eg. movzb) */
5525 if (i
.types
[op
].bitfield
.reg8
5526 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5527 || i
.tm
.operand_types
[op
].bitfield
.reg32
5528 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5530 as_bad (_("`%s%s' not allowed with `%s%c'"),
5532 i
.op
[op
].regs
->reg_name
,
5537 /* Warn if the r prefix on a general reg is missing. */
5538 else if ((i
.types
[op
].bitfield
.reg16
5539 || i
.types
[op
].bitfield
.reg32
)
5540 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5541 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5543 /* Prohibit these changes in the 64bit mode, since the
5544 lowering is more complicated. */
5546 && i
.tm
.opcode_modifier
.todword
5547 && !i
.types
[0].bitfield
.regxmm
)
5549 /* Convert to DWORD. We don't want REX byte. */
5550 i
.suffix
= LONG_MNEM_SUFFIX
;
5554 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5555 register_prefix
, i
.op
[op
].regs
->reg_name
,
5564 check_word_reg (void)
5567 for (op
= i
.operands
; --op
>= 0;)
5568 /* Reject eight bit registers, except where the template requires
5569 them. (eg. movzb) */
5570 if (i
.types
[op
].bitfield
.reg8
5571 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5572 || i
.tm
.operand_types
[op
].bitfield
.reg32
5573 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5575 as_bad (_("`%s%s' not allowed with `%s%c'"),
5577 i
.op
[op
].regs
->reg_name
,
5582 /* Warn if the e or r prefix on a general reg is present. */
5583 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5584 && (i
.types
[op
].bitfield
.reg32
5585 || i
.types
[op
].bitfield
.reg64
)
5586 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5587 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5589 /* Prohibit these changes in the 64bit mode, since the
5590 lowering is more complicated. */
5591 if (flag_code
== CODE_64BIT
)
5593 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5594 register_prefix
, i
.op
[op
].regs
->reg_name
,
5598 #if REGISTER_WARNINGS
5599 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5601 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5602 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5609 update_imm (unsigned int j
)
5611 i386_operand_type overlap
= i
.types
[j
];
5612 if ((overlap
.bitfield
.imm8
5613 || overlap
.bitfield
.imm8s
5614 || overlap
.bitfield
.imm16
5615 || overlap
.bitfield
.imm32
5616 || overlap
.bitfield
.imm32s
5617 || overlap
.bitfield
.imm64
)
5618 && !operand_type_equal (&overlap
, &imm8
)
5619 && !operand_type_equal (&overlap
, &imm8s
)
5620 && !operand_type_equal (&overlap
, &imm16
)
5621 && !operand_type_equal (&overlap
, &imm32
)
5622 && !operand_type_equal (&overlap
, &imm32s
)
5623 && !operand_type_equal (&overlap
, &imm64
))
5627 i386_operand_type temp
;
5629 operand_type_set (&temp
, 0);
5630 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5632 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5633 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5635 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5636 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5637 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5639 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5640 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5643 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5646 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5647 || operand_type_equal (&overlap
, &imm16_32
)
5648 || operand_type_equal (&overlap
, &imm16_32s
))
5650 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5655 if (!operand_type_equal (&overlap
, &imm8
)
5656 && !operand_type_equal (&overlap
, &imm8s
)
5657 && !operand_type_equal (&overlap
, &imm16
)
5658 && !operand_type_equal (&overlap
, &imm32
)
5659 && !operand_type_equal (&overlap
, &imm32s
)
5660 && !operand_type_equal (&overlap
, &imm64
))
5662 as_bad (_("no instruction mnemonic suffix given; "
5663 "can't determine immediate size"));
5667 i
.types
[j
] = overlap
;
5677 /* Update the first 2 immediate operands. */
5678 n
= i
.operands
> 2 ? 2 : i
.operands
;
5681 for (j
= 0; j
< n
; j
++)
5682 if (update_imm (j
) == 0)
5685 /* The 3rd operand can't be immediate operand. */
5686 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5693 bad_implicit_operand (int xmm
)
5695 const char *ireg
= xmm
? "xmm0" : "ymm0";
5698 as_bad (_("the last operand of `%s' must be `%s%s'"),
5699 i
.tm
.name
, register_prefix
, ireg
);
5701 as_bad (_("the first operand of `%s' must be `%s%s'"),
5702 i
.tm
.name
, register_prefix
, ireg
);
5707 process_operands (void)
5709 /* Default segment register this instruction will use for memory
5710 accesses. 0 means unknown. This is only for optimizing out
5711 unnecessary segment overrides. */
5712 const seg_entry
*default_seg
= 0;
5714 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5716 unsigned int dupl
= i
.operands
;
5717 unsigned int dest
= dupl
- 1;
5720 /* The destination must be an xmm register. */
5721 gas_assert (i
.reg_operands
5722 && MAX_OPERANDS
> dupl
5723 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5725 if (i
.tm
.opcode_modifier
.firstxmm0
)
5727 /* The first operand is implicit and must be xmm0. */
5728 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5729 if (register_number (i
.op
[0].regs
) != 0)
5730 return bad_implicit_operand (1);
5732 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5734 /* Keep xmm0 for instructions with VEX prefix and 3
5740 /* We remove the first xmm0 and keep the number of
5741 operands unchanged, which in fact duplicates the
5743 for (j
= 1; j
< i
.operands
; j
++)
5745 i
.op
[j
- 1] = i
.op
[j
];
5746 i
.types
[j
- 1] = i
.types
[j
];
5747 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5751 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5753 gas_assert ((MAX_OPERANDS
- 1) > dupl
5754 && (i
.tm
.opcode_modifier
.vexsources
5757 /* Add the implicit xmm0 for instructions with VEX prefix
5759 for (j
= i
.operands
; j
> 0; j
--)
5761 i
.op
[j
] = i
.op
[j
- 1];
5762 i
.types
[j
] = i
.types
[j
- 1];
5763 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5766 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5767 i
.types
[0] = regxmm
;
5768 i
.tm
.operand_types
[0] = regxmm
;
5771 i
.reg_operands
+= 2;
5776 i
.op
[dupl
] = i
.op
[dest
];
5777 i
.types
[dupl
] = i
.types
[dest
];
5778 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5787 i
.op
[dupl
] = i
.op
[dest
];
5788 i
.types
[dupl
] = i
.types
[dest
];
5789 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5792 if (i
.tm
.opcode_modifier
.immext
)
5795 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5799 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5800 gas_assert (i
.reg_operands
5801 && (operand_type_equal (&i
.types
[0], ®xmm
)
5802 || operand_type_equal (&i
.types
[0], ®ymm
)
5803 || operand_type_equal (&i
.types
[0], ®zmm
)));
5804 if (register_number (i
.op
[0].regs
) != 0)
5805 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5807 for (j
= 1; j
< i
.operands
; j
++)
5809 i
.op
[j
- 1] = i
.op
[j
];
5810 i
.types
[j
- 1] = i
.types
[j
];
5812 /* We need to adjust fields in i.tm since they are used by
5813 build_modrm_byte. */
5814 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5821 else if (i
.tm
.opcode_modifier
.regkludge
)
5823 /* The imul $imm, %reg instruction is converted into
5824 imul $imm, %reg, %reg, and the clr %reg instruction
5825 is converted into xor %reg, %reg. */
5827 unsigned int first_reg_op
;
5829 if (operand_type_check (i
.types
[0], reg
))
5833 /* Pretend we saw the extra register operand. */
5834 gas_assert (i
.reg_operands
== 1
5835 && i
.op
[first_reg_op
+ 1].regs
== 0);
5836 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5837 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5842 if (i
.tm
.opcode_modifier
.shortform
)
5844 if (i
.types
[0].bitfield
.sreg2
5845 || i
.types
[0].bitfield
.sreg3
)
5847 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5848 && i
.op
[0].regs
->reg_num
== 1)
5850 as_bad (_("you can't `pop %scs'"), register_prefix
);
5853 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5854 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5859 /* The register or float register operand is in operand
5863 if (i
.types
[0].bitfield
.floatreg
5864 || operand_type_check (i
.types
[0], reg
))
5868 /* Register goes in low 3 bits of opcode. */
5869 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5870 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5872 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5874 /* Warn about some common errors, but press on regardless.
5875 The first case can be generated by gcc (<= 2.8.1). */
5876 if (i
.operands
== 2)
5878 /* Reversed arguments on faddp, fsubp, etc. */
5879 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5880 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5881 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5885 /* Extraneous `l' suffix on fp insn. */
5886 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5887 register_prefix
, i
.op
[0].regs
->reg_name
);
5892 else if (i
.tm
.opcode_modifier
.modrm
)
5894 /* The opcode is completed (modulo i.tm.extension_opcode which
5895 must be put into the modrm byte). Now, we make the modrm and
5896 index base bytes based on all the info we've collected. */
5898 default_seg
= build_modrm_byte ();
5900 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5904 else if (i
.tm
.opcode_modifier
.isstring
)
5906 /* For the string instructions that allow a segment override
5907 on one of their operands, the default segment is ds. */
5911 if (i
.tm
.base_opcode
== 0x8d /* lea */
5914 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5916 /* If a segment was explicitly specified, and the specified segment
5917 is not the default, use an opcode prefix to select it. If we
5918 never figured out what the default segment is, then default_seg
5919 will be zero at this point, and the specified segment prefix will
5921 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5923 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5929 static const seg_entry
*
5930 build_modrm_byte (void)
5932 const seg_entry
*default_seg
= 0;
5933 unsigned int source
, dest
;
5936 /* The first operand of instructions with VEX prefix and 3 sources
5937 must be VEX_Imm4. */
5938 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5941 unsigned int nds
, reg_slot
;
5944 if (i
.tm
.opcode_modifier
.veximmext
5945 && i
.tm
.opcode_modifier
.immext
)
5947 dest
= i
.operands
- 2;
5948 gas_assert (dest
== 3);
5951 dest
= i
.operands
- 1;
5954 /* There are 2 kinds of instructions:
5955 1. 5 operands: 4 register operands or 3 register operands
5956 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5957 VexW0 or VexW1. The destination must be either XMM, YMM or
5959 2. 4 operands: 4 register operands or 3 register operands
5960 plus 1 memory operand, VexXDS, and VexImmExt */
5961 gas_assert ((i
.reg_operands
== 4
5962 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5963 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5964 && (i
.tm
.opcode_modifier
.veximmext
5965 || (i
.imm_operands
== 1
5966 && i
.types
[0].bitfield
.vec_imm4
5967 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5968 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5969 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5970 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5971 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5973 if (i
.imm_operands
== 0)
5975 /* When there is no immediate operand, generate an 8bit
5976 immediate operand to encode the first operand. */
5977 exp
= &im_expressions
[i
.imm_operands
++];
5978 i
.op
[i
.operands
].imms
= exp
;
5979 i
.types
[i
.operands
] = imm8
;
5981 /* If VexW1 is set, the first operand is the source and
5982 the second operand is encoded in the immediate operand. */
5983 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5994 /* FMA swaps REG and NDS. */
5995 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6003 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6005 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6007 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6009 exp
->X_op
= O_constant
;
6010 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6011 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6015 unsigned int imm_slot
;
6017 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6019 /* If VexW0 is set, the third operand is the source and
6020 the second operand is encoded in the immediate
6027 /* VexW1 is set, the second operand is the source and
6028 the third operand is encoded in the immediate
6034 if (i
.tm
.opcode_modifier
.immext
)
6036 /* When ImmExt is set, the immdiate byte is the last
6038 imm_slot
= i
.operands
- 1;
6046 /* Turn on Imm8 so that output_imm will generate it. */
6047 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6050 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6052 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6054 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6056 i
.op
[imm_slot
].imms
->X_add_number
6057 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6058 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6061 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6062 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6064 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6066 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6071 /* i.reg_operands MUST be the number of real register operands;
6072 implicit registers do not count. If there are 3 register
6073 operands, it must be a instruction with VexNDS. For a
6074 instruction with VexNDD, the destination register is encoded
6075 in VEX prefix. If there are 4 register operands, it must be
6076 a instruction with VEX prefix and 3 sources. */
6077 if (i
.mem_operands
== 0
6078 && ((i
.reg_operands
== 2
6079 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6080 || (i
.reg_operands
== 3
6081 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6082 || (i
.reg_operands
== 4 && vex_3_sources
)))
6090 /* When there are 3 operands, one of them may be immediate,
6091 which may be the first or the last operand. Otherwise,
6092 the first operand must be shift count register (cl) or it
6093 is an instruction with VexNDS. */
6094 gas_assert (i
.imm_operands
== 1
6095 || (i
.imm_operands
== 0
6096 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6097 || i
.types
[0].bitfield
.shiftcount
)));
6098 if (operand_type_check (i
.types
[0], imm
)
6099 || i
.types
[0].bitfield
.shiftcount
)
6105 /* When there are 4 operands, the first two must be 8bit
6106 immediate operands. The source operand will be the 3rd
6109 For instructions with VexNDS, if the first operand
6110 an imm8, the source operand is the 2nd one. If the last
6111 operand is imm8, the source operand is the first one. */
6112 gas_assert ((i
.imm_operands
== 2
6113 && i
.types
[0].bitfield
.imm8
6114 && i
.types
[1].bitfield
.imm8
)
6115 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6116 && i
.imm_operands
== 1
6117 && (i
.types
[0].bitfield
.imm8
6118 || i
.types
[i
.operands
- 1].bitfield
.imm8
6120 if (i
.imm_operands
== 2)
6124 if (i
.types
[0].bitfield
.imm8
)
6131 if (i
.tm
.opcode_modifier
.evex
)
6133 /* For EVEX instructions, when there are 5 operands, the
6134 first one must be immediate operand. If the second one
6135 is immediate operand, the source operand is the 3th
6136 one. If the last one is immediate operand, the source
6137 operand is the 2nd one. */
6138 gas_assert (i
.imm_operands
== 2
6139 && i
.tm
.opcode_modifier
.sae
6140 && operand_type_check (i
.types
[0], imm
));
6141 if (operand_type_check (i
.types
[1], imm
))
6143 else if (operand_type_check (i
.types
[4], imm
))
6157 /* RC/SAE operand could be between DEST and SRC. That happens
6158 when one operand is GPR and the other one is XMM/YMM/ZMM
6160 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6163 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6165 /* For instructions with VexNDS, the register-only source
6166 operand must be 32/64bit integer, XMM, YMM or ZMM
6167 register. It is encoded in VEX prefix. We need to
6168 clear RegMem bit before calling operand_type_equal. */
6170 i386_operand_type op
;
6173 /* Check register-only source operand when two source
6174 operands are swapped. */
6175 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6176 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6184 op
= i
.tm
.operand_types
[vvvv
];
6185 op
.bitfield
.regmem
= 0;
6186 if ((dest
+ 1) >= i
.operands
6187 || (!op
.bitfield
.reg32
6188 && op
.bitfield
.reg64
6189 && !operand_type_equal (&op
, ®xmm
)
6190 && !operand_type_equal (&op
, ®ymm
)
6191 && !operand_type_equal (&op
, ®zmm
)
6192 && !operand_type_equal (&op
, ®mask
)))
6194 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6200 /* One of the register operands will be encoded in the i.tm.reg
6201 field, the other in the combined i.tm.mode and i.tm.regmem
6202 fields. If no form of this instruction supports a memory
6203 destination operand, then we assume the source operand may
6204 sometimes be a memory operand and so we need to store the
6205 destination in the i.rm.reg field. */
6206 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6207 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6209 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6210 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6211 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6213 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6215 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6217 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6222 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6223 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6224 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6226 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6228 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6230 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6233 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6235 if (!i
.types
[0].bitfield
.control
6236 && !i
.types
[1].bitfield
.control
)
6238 i
.rex
&= ~(REX_R
| REX_B
);
6239 add_prefix (LOCK_PREFIX_OPCODE
);
6243 { /* If it's not 2 reg operands... */
6248 unsigned int fake_zero_displacement
= 0;
6251 for (op
= 0; op
< i
.operands
; op
++)
6252 if (operand_type_check (i
.types
[op
], anymem
))
6254 gas_assert (op
< i
.operands
);
6256 if (i
.tm
.opcode_modifier
.vecsib
)
6258 if (i
.index_reg
->reg_num
== RegEiz
6259 || i
.index_reg
->reg_num
== RegRiz
)
6262 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6265 i
.sib
.base
= NO_BASE_REGISTER
;
6266 i
.sib
.scale
= i
.log2_scale_factor
;
6267 /* No Vec_Disp8 if there is no base. */
6268 i
.types
[op
].bitfield
.vec_disp8
= 0;
6269 i
.types
[op
].bitfield
.disp8
= 0;
6270 i
.types
[op
].bitfield
.disp16
= 0;
6271 i
.types
[op
].bitfield
.disp64
= 0;
6272 if (flag_code
!= CODE_64BIT
)
6274 /* Must be 32 bit */
6275 i
.types
[op
].bitfield
.disp32
= 1;
6276 i
.types
[op
].bitfield
.disp32s
= 0;
6280 i
.types
[op
].bitfield
.disp32
= 0;
6281 i
.types
[op
].bitfield
.disp32s
= 1;
6284 i
.sib
.index
= i
.index_reg
->reg_num
;
6285 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6287 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6293 if (i
.base_reg
== 0)
6296 if (!i
.disp_operands
)
6298 fake_zero_displacement
= 1;
6299 /* Instructions with VSIB byte need 32bit displacement
6300 if there is no base register. */
6301 if (i
.tm
.opcode_modifier
.vecsib
)
6302 i
.types
[op
].bitfield
.disp32
= 1;
6304 if (i
.index_reg
== 0)
6306 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6307 /* Operand is just <disp> */
6308 if (flag_code
== CODE_64BIT
)
6310 /* 64bit mode overwrites the 32bit absolute
6311 addressing by RIP relative addressing and
6312 absolute addressing is encoded by one of the
6313 redundant SIB forms. */
6314 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6315 i
.sib
.base
= NO_BASE_REGISTER
;
6316 i
.sib
.index
= NO_INDEX_REGISTER
;
6317 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6318 ? disp32s
: disp32
);
6320 else if ((flag_code
== CODE_16BIT
)
6321 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6323 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6324 i
.types
[op
] = disp16
;
6328 i
.rm
.regmem
= NO_BASE_REGISTER
;
6329 i
.types
[op
] = disp32
;
6332 else if (!i
.tm
.opcode_modifier
.vecsib
)
6334 /* !i.base_reg && i.index_reg */
6335 if (i
.index_reg
->reg_num
== RegEiz
6336 || i
.index_reg
->reg_num
== RegRiz
)
6337 i
.sib
.index
= NO_INDEX_REGISTER
;
6339 i
.sib
.index
= i
.index_reg
->reg_num
;
6340 i
.sib
.base
= NO_BASE_REGISTER
;
6341 i
.sib
.scale
= i
.log2_scale_factor
;
6342 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6343 /* No Vec_Disp8 if there is no base. */
6344 i
.types
[op
].bitfield
.vec_disp8
= 0;
6345 i
.types
[op
].bitfield
.disp8
= 0;
6346 i
.types
[op
].bitfield
.disp16
= 0;
6347 i
.types
[op
].bitfield
.disp64
= 0;
6348 if (flag_code
!= CODE_64BIT
)
6350 /* Must be 32 bit */
6351 i
.types
[op
].bitfield
.disp32
= 1;
6352 i
.types
[op
].bitfield
.disp32s
= 0;
6356 i
.types
[op
].bitfield
.disp32
= 0;
6357 i
.types
[op
].bitfield
.disp32s
= 1;
6359 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6363 /* RIP addressing for 64bit mode. */
6364 else if (i
.base_reg
->reg_num
== RegRip
||
6365 i
.base_reg
->reg_num
== RegEip
)
6367 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6368 i
.rm
.regmem
= NO_BASE_REGISTER
;
6369 i
.types
[op
].bitfield
.disp8
= 0;
6370 i
.types
[op
].bitfield
.disp16
= 0;
6371 i
.types
[op
].bitfield
.disp32
= 0;
6372 i
.types
[op
].bitfield
.disp32s
= 1;
6373 i
.types
[op
].bitfield
.disp64
= 0;
6374 i
.types
[op
].bitfield
.vec_disp8
= 0;
6375 i
.flags
[op
] |= Operand_PCrel
;
6376 if (! i
.disp_operands
)
6377 fake_zero_displacement
= 1;
6379 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6381 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6382 switch (i
.base_reg
->reg_num
)
6385 if (i
.index_reg
== 0)
6387 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6388 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6392 if (i
.index_reg
== 0)
6395 if (operand_type_check (i
.types
[op
], disp
) == 0)
6397 /* fake (%bp) into 0(%bp) */
6398 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6399 i
.types
[op
].bitfield
.vec_disp8
= 1;
6401 i
.types
[op
].bitfield
.disp8
= 1;
6402 fake_zero_displacement
= 1;
6405 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6406 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6408 default: /* (%si) -> 4 or (%di) -> 5 */
6409 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6411 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6413 else /* i.base_reg and 32/64 bit mode */
6415 if (flag_code
== CODE_64BIT
6416 && operand_type_check (i
.types
[op
], disp
))
6418 i386_operand_type temp
;
6419 operand_type_set (&temp
, 0);
6420 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6421 temp
.bitfield
.vec_disp8
6422 = i
.types
[op
].bitfield
.vec_disp8
;
6424 if (i
.prefix
[ADDR_PREFIX
] == 0)
6425 i
.types
[op
].bitfield
.disp32s
= 1;
6427 i
.types
[op
].bitfield
.disp32
= 1;
6430 if (!i
.tm
.opcode_modifier
.vecsib
)
6431 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6432 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6434 i
.sib
.base
= i
.base_reg
->reg_num
;
6435 /* x86-64 ignores REX prefix bit here to avoid decoder
6437 if (!(i
.base_reg
->reg_flags
& RegRex
)
6438 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6439 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6441 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6443 fake_zero_displacement
= 1;
6444 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6445 i
.types
[op
].bitfield
.vec_disp8
= 1;
6447 i
.types
[op
].bitfield
.disp8
= 1;
6449 i
.sib
.scale
= i
.log2_scale_factor
;
6450 if (i
.index_reg
== 0)
6452 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6453 /* <disp>(%esp) becomes two byte modrm with no index
6454 register. We've already stored the code for esp
6455 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6456 Any base register besides %esp will not use the
6457 extra modrm byte. */
6458 i
.sib
.index
= NO_INDEX_REGISTER
;
6460 else if (!i
.tm
.opcode_modifier
.vecsib
)
6462 if (i
.index_reg
->reg_num
== RegEiz
6463 || i
.index_reg
->reg_num
== RegRiz
)
6464 i
.sib
.index
= NO_INDEX_REGISTER
;
6466 i
.sib
.index
= i
.index_reg
->reg_num
;
6467 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6468 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6473 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6474 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6478 if (!fake_zero_displacement
6482 fake_zero_displacement
= 1;
6483 if (i
.disp_encoding
== disp_encoding_8bit
)
6484 i
.types
[op
].bitfield
.disp8
= 1;
6486 i
.types
[op
].bitfield
.disp32
= 1;
6488 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6492 if (fake_zero_displacement
)
6494 /* Fakes a zero displacement assuming that i.types[op]
6495 holds the correct displacement size. */
6498 gas_assert (i
.op
[op
].disps
== 0);
6499 exp
= &disp_expressions
[i
.disp_operands
++];
6500 i
.op
[op
].disps
= exp
;
6501 exp
->X_op
= O_constant
;
6502 exp
->X_add_number
= 0;
6503 exp
->X_add_symbol
= (symbolS
*) 0;
6504 exp
->X_op_symbol
= (symbolS
*) 0;
6512 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6514 if (operand_type_check (i
.types
[0], imm
))
6515 i
.vex
.register_specifier
= NULL
;
6518 /* VEX.vvvv encodes one of the sources when the first
6519 operand is not an immediate. */
6520 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6521 i
.vex
.register_specifier
= i
.op
[0].regs
;
6523 i
.vex
.register_specifier
= i
.op
[1].regs
;
6526 /* Destination is a XMM register encoded in the ModRM.reg
6528 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6529 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6532 /* ModRM.rm and VEX.B encodes the other source. */
6533 if (!i
.mem_operands
)
6537 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6538 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6540 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6542 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6546 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6548 i
.vex
.register_specifier
= i
.op
[2].regs
;
6549 if (!i
.mem_operands
)
6552 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6553 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6557 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6558 (if any) based on i.tm.extension_opcode. Again, we must be
6559 careful to make sure that segment/control/debug/test/MMX
6560 registers are coded into the i.rm.reg field. */
6561 else if (i
.reg_operands
)
6564 unsigned int vex_reg
= ~0;
6566 for (op
= 0; op
< i
.operands
; op
++)
6567 if (i
.types
[op
].bitfield
.reg8
6568 || i
.types
[op
].bitfield
.reg16
6569 || i
.types
[op
].bitfield
.reg32
6570 || i
.types
[op
].bitfield
.reg64
6571 || i
.types
[op
].bitfield
.regmmx
6572 || i
.types
[op
].bitfield
.regxmm
6573 || i
.types
[op
].bitfield
.regymm
6574 || i
.types
[op
].bitfield
.regbnd
6575 || i
.types
[op
].bitfield
.regzmm
6576 || i
.types
[op
].bitfield
.regmask
6577 || i
.types
[op
].bitfield
.sreg2
6578 || i
.types
[op
].bitfield
.sreg3
6579 || i
.types
[op
].bitfield
.control
6580 || i
.types
[op
].bitfield
.debug
6581 || i
.types
[op
].bitfield
.test
)
6586 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6588 /* For instructions with VexNDS, the register-only
6589 source operand is encoded in VEX prefix. */
6590 gas_assert (mem
!= (unsigned int) ~0);
6595 gas_assert (op
< i
.operands
);
6599 /* Check register-only source operand when two source
6600 operands are swapped. */
6601 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6602 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6606 gas_assert (mem
== (vex_reg
+ 1)
6607 && op
< i
.operands
);
6612 gas_assert (vex_reg
< i
.operands
);
6616 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6618 /* For instructions with VexNDD, the register destination
6619 is encoded in VEX prefix. */
6620 if (i
.mem_operands
== 0)
6622 /* There is no memory operand. */
6623 gas_assert ((op
+ 2) == i
.operands
);
6628 /* There are only 2 operands. */
6629 gas_assert (op
< 2 && i
.operands
== 2);
6634 gas_assert (op
< i
.operands
);
6636 if (vex_reg
!= (unsigned int) ~0)
6638 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6640 if (type
->bitfield
.reg32
!= 1
6641 && type
->bitfield
.reg64
!= 1
6642 && !operand_type_equal (type
, ®xmm
)
6643 && !operand_type_equal (type
, ®ymm
)
6644 && !operand_type_equal (type
, ®zmm
)
6645 && !operand_type_equal (type
, ®mask
))
6648 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6651 /* Don't set OP operand twice. */
6654 /* If there is an extension opcode to put here, the
6655 register number must be put into the regmem field. */
6656 if (i
.tm
.extension_opcode
!= None
)
6658 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6659 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6661 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6666 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6667 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6669 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6674 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6675 must set it to 3 to indicate this is a register operand
6676 in the regmem field. */
6677 if (!i
.mem_operands
)
6681 /* Fill in i.rm.reg field with extension opcode (if any). */
6682 if (i
.tm
.extension_opcode
!= None
)
6683 i
.rm
.reg
= i
.tm
.extension_opcode
;
6689 output_branch (void)
6695 relax_substateT subtype
;
6699 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6700 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6703 if (i
.prefix
[DATA_PREFIX
] != 0)
6709 /* Pentium4 branch hints. */
6710 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6711 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6716 if (i
.prefix
[REX_PREFIX
] != 0)
6722 /* BND prefixed jump. */
6723 if (i
.prefix
[BND_PREFIX
] != 0)
6725 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6729 if (i
.prefixes
!= 0 && !intel_syntax
)
6730 as_warn (_("skipping prefixes on this instruction"));
6732 /* It's always a symbol; End frag & setup for relax.
6733 Make sure there is enough room in this frag for the largest
6734 instruction we may generate in md_convert_frag. This is 2
6735 bytes for the opcode and room for the prefix and largest
6737 frag_grow (prefix
+ 2 + 4);
6738 /* Prefix and 1 opcode byte go in fr_fix. */
6739 p
= frag_more (prefix
+ 1);
6740 if (i
.prefix
[DATA_PREFIX
] != 0)
6741 *p
++ = DATA_PREFIX_OPCODE
;
6742 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6743 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6744 *p
++ = i
.prefix
[SEG_PREFIX
];
6745 if (i
.prefix
[REX_PREFIX
] != 0)
6746 *p
++ = i
.prefix
[REX_PREFIX
];
6747 *p
= i
.tm
.base_opcode
;
6749 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6750 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6751 else if (cpu_arch_flags
.bitfield
.cpui386
)
6752 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6754 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6757 sym
= i
.op
[0].disps
->X_add_symbol
;
6758 off
= i
.op
[0].disps
->X_add_number
;
6760 if (i
.op
[0].disps
->X_op
!= O_constant
6761 && i
.op
[0].disps
->X_op
!= O_symbol
)
6763 /* Handle complex expressions. */
6764 sym
= make_expr_symbol (i
.op
[0].disps
);
6768 /* 1 possible extra opcode + 4 byte displacement go in var part.
6769 Pass reloc in fr_var. */
6770 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6780 if (i
.tm
.opcode_modifier
.jumpbyte
)
6782 /* This is a loop or jecxz type instruction. */
6784 if (i
.prefix
[ADDR_PREFIX
] != 0)
6786 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6789 /* Pentium4 branch hints. */
6790 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6791 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6793 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6802 if (flag_code
== CODE_16BIT
)
6805 if (i
.prefix
[DATA_PREFIX
] != 0)
6807 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6817 if (i
.prefix
[REX_PREFIX
] != 0)
6819 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6823 /* BND prefixed jump. */
6824 if (i
.prefix
[BND_PREFIX
] != 0)
6826 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6830 if (i
.prefixes
!= 0 && !intel_syntax
)
6831 as_warn (_("skipping prefixes on this instruction"));
6833 p
= frag_more (i
.tm
.opcode_length
+ size
);
6834 switch (i
.tm
.opcode_length
)
6837 *p
++ = i
.tm
.base_opcode
>> 8;
6839 *p
++ = i
.tm
.base_opcode
;
6845 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6846 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6848 /* All jumps handled here are signed, but don't use a signed limit
6849 check for 32 and 16 bit jumps as we want to allow wrap around at
6850 4G and 64k respectively. */
6852 fixP
->fx_signed
= 1;
6856 output_interseg_jump (void)
6864 if (flag_code
== CODE_16BIT
)
6868 if (i
.prefix
[DATA_PREFIX
] != 0)
6874 if (i
.prefix
[REX_PREFIX
] != 0)
6884 if (i
.prefixes
!= 0 && !intel_syntax
)
6885 as_warn (_("skipping prefixes on this instruction"));
6887 /* 1 opcode; 2 segment; offset */
6888 p
= frag_more (prefix
+ 1 + 2 + size
);
6890 if (i
.prefix
[DATA_PREFIX
] != 0)
6891 *p
++ = DATA_PREFIX_OPCODE
;
6893 if (i
.prefix
[REX_PREFIX
] != 0)
6894 *p
++ = i
.prefix
[REX_PREFIX
];
6896 *p
++ = i
.tm
.base_opcode
;
6897 if (i
.op
[1].imms
->X_op
== O_constant
)
6899 offsetT n
= i
.op
[1].imms
->X_add_number
;
6902 && !fits_in_unsigned_word (n
)
6903 && !fits_in_signed_word (n
))
6905 as_bad (_("16-bit jump out of range"));
6908 md_number_to_chars (p
, n
, size
);
6911 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6912 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6913 if (i
.op
[0].imms
->X_op
!= O_constant
)
6914 as_bad (_("can't handle non absolute segment in `%s'"),
6916 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6922 fragS
*insn_start_frag
;
6923 offsetT insn_start_off
;
6925 /* Tie dwarf2 debug info to the address at the start of the insn.
6926 We can't do this after the insn has been output as the current
6927 frag may have been closed off. eg. by frag_var. */
6928 dwarf2_emit_insn (0);
6930 insn_start_frag
= frag_now
;
6931 insn_start_off
= frag_now_fix ();
6934 if (i
.tm
.opcode_modifier
.jump
)
6936 else if (i
.tm
.opcode_modifier
.jumpbyte
6937 || i
.tm
.opcode_modifier
.jumpdword
)
6939 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6940 output_interseg_jump ();
6943 /* Output normal instructions here. */
6947 unsigned int prefix
;
6949 /* Some processors fail on LOCK prefix. This options makes
6950 assembler ignore LOCK prefix and serves as a workaround. */
6951 if (omit_lock_prefix
)
6953 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
6955 i
.prefix
[LOCK_PREFIX
] = 0;
6958 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6959 don't need the explicit prefix. */
6960 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6962 switch (i
.tm
.opcode_length
)
6965 if (i
.tm
.base_opcode
& 0xff000000)
6967 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6972 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6974 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6975 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6978 if (prefix
!= REPE_PREFIX_OPCODE
6979 || (i
.prefix
[REP_PREFIX
]
6980 != REPE_PREFIX_OPCODE
))
6981 add_prefix (prefix
);
6984 add_prefix (prefix
);
6993 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6994 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
6995 R_X86_64_GOTTPOFF relocation so that linker can safely
6996 perform IE->LE optimization. */
6997 if (x86_elf_abi
== X86_64_X32_ABI
6999 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7000 && i
.prefix
[REX_PREFIX
] == 0)
7001 add_prefix (REX_OPCODE
);
7004 /* The prefix bytes. */
7005 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7007 FRAG_APPEND_1_CHAR (*q
);
7011 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7016 /* REX byte is encoded in VEX prefix. */
7020 FRAG_APPEND_1_CHAR (*q
);
7023 /* There should be no other prefixes for instructions
7028 /* For EVEX instructions i.vrex should become 0 after
7029 build_evex_prefix. For VEX instructions upper 16 registers
7030 aren't available, so VREX should be 0. */
7033 /* Now the VEX prefix. */
7034 p
= frag_more (i
.vex
.length
);
7035 for (j
= 0; j
< i
.vex
.length
; j
++)
7036 p
[j
] = i
.vex
.bytes
[j
];
7039 /* Now the opcode; be careful about word order here! */
7040 if (i
.tm
.opcode_length
== 1)
7042 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7046 switch (i
.tm
.opcode_length
)
7050 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7051 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7055 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7065 /* Put out high byte first: can't use md_number_to_chars! */
7066 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7067 *p
= i
.tm
.base_opcode
& 0xff;
7070 /* Now the modrm byte and sib byte (if present). */
7071 if (i
.tm
.opcode_modifier
.modrm
)
7073 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7076 /* If i.rm.regmem == ESP (4)
7077 && i.rm.mode != (Register mode)
7079 ==> need second modrm byte. */
7080 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7082 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7083 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7085 | i
.sib
.scale
<< 6));
7088 if (i
.disp_operands
)
7089 output_disp (insn_start_frag
, insn_start_off
);
7092 output_imm (insn_start_frag
, insn_start_off
);
7098 pi ("" /*line*/, &i
);
7100 #endif /* DEBUG386 */
7103 /* Return the size of the displacement operand N. */
7106 disp_size (unsigned int n
)
7110 /* Vec_Disp8 has to be 8bit. */
7111 if (i
.types
[n
].bitfield
.vec_disp8
)
7113 else if (i
.types
[n
].bitfield
.disp64
)
7115 else if (i
.types
[n
].bitfield
.disp8
)
7117 else if (i
.types
[n
].bitfield
.disp16
)
7122 /* Return the size of the immediate operand N. */
7125 imm_size (unsigned int n
)
7128 if (i
.types
[n
].bitfield
.imm64
)
7130 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7132 else if (i
.types
[n
].bitfield
.imm16
)
7138 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7143 for (n
= 0; n
< i
.operands
; n
++)
7145 if (i
.types
[n
].bitfield
.vec_disp8
7146 || operand_type_check (i
.types
[n
], disp
))
7148 if (i
.op
[n
].disps
->X_op
== O_constant
)
7150 int size
= disp_size (n
);
7151 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7153 if (i
.types
[n
].bitfield
.vec_disp8
)
7155 val
= offset_in_range (val
, size
);
7156 p
= frag_more (size
);
7157 md_number_to_chars (p
, val
, size
);
7161 enum bfd_reloc_code_real reloc_type
;
7162 int size
= disp_size (n
);
7163 int sign
= i
.types
[n
].bitfield
.disp32s
;
7164 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7167 /* We can't have 8 bit displacement here. */
7168 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7170 /* The PC relative address is computed relative
7171 to the instruction boundary, so in case immediate
7172 fields follows, we need to adjust the value. */
7173 if (pcrel
&& i
.imm_operands
)
7178 for (n1
= 0; n1
< i
.operands
; n1
++)
7179 if (operand_type_check (i
.types
[n1
], imm
))
7181 /* Only one immediate is allowed for PC
7182 relative address. */
7183 gas_assert (sz
== 0);
7185 i
.op
[n
].disps
->X_add_number
-= sz
;
7187 /* We should find the immediate. */
7188 gas_assert (sz
!= 0);
7191 p
= frag_more (size
);
7192 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7194 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7195 && (((reloc_type
== BFD_RELOC_32
7196 || reloc_type
== BFD_RELOC_X86_64_32S
7197 || (reloc_type
== BFD_RELOC_64
7199 && (i
.op
[n
].disps
->X_op
== O_symbol
7200 || (i
.op
[n
].disps
->X_op
== O_add
7201 && ((symbol_get_value_expression
7202 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7204 || reloc_type
== BFD_RELOC_32_PCREL
))
7208 if (insn_start_frag
== frag_now
)
7209 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7214 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7215 for (fr
= insn_start_frag
->fr_next
;
7216 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7218 add
+= p
- frag_now
->fr_literal
;
7223 reloc_type
= BFD_RELOC_386_GOTPC
;
7224 i
.op
[n
].imms
->X_add_number
+= add
;
7226 else if (reloc_type
== BFD_RELOC_64
)
7227 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7229 /* Don't do the adjustment for x86-64, as there
7230 the pcrel addressing is relative to the _next_
7231 insn, and that is taken care of in other code. */
7232 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7234 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7235 size
, i
.op
[n
].disps
, pcrel
,
7237 /* Check for "call/jmp *mem", "mov mem, %reg",
7238 "test %reg, mem" and "binop mem, %reg" where binop
7239 is one of adc, add, and, cmp, or, sbb, sub, xor
7242 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7243 && ((i
.operands
== 1
7244 && i
.tm
.base_opcode
== 0xff
7245 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7247 && (i
.tm
.base_opcode
== 0x8b
7248 || i
.tm
.base_opcode
== 0x85
7249 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7253 fixP
->fx_tcbit
= i
.rex
!= 0;
7255 && (i
.base_reg
->reg_num
== RegRip
7256 || i
.base_reg
->reg_num
== RegEip
))
7257 fixP
->fx_tcbit2
= 1;
7260 fixP
->fx_tcbit2
= 1;
7268 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7273 for (n
= 0; n
< i
.operands
; n
++)
7275 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7276 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7279 if (operand_type_check (i
.types
[n
], imm
))
7281 if (i
.op
[n
].imms
->X_op
== O_constant
)
7283 int size
= imm_size (n
);
7286 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7288 p
= frag_more (size
);
7289 md_number_to_chars (p
, val
, size
);
7293 /* Not absolute_section.
7294 Need a 32-bit fixup (don't support 8bit
7295 non-absolute imms). Try to support other
7297 enum bfd_reloc_code_real reloc_type
;
7298 int size
= imm_size (n
);
7301 if (i
.types
[n
].bitfield
.imm32s
7302 && (i
.suffix
== QWORD_MNEM_SUFFIX
7303 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7308 p
= frag_more (size
);
7309 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7311 /* This is tough to explain. We end up with this one if we
7312 * have operands that look like
7313 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7314 * obtain the absolute address of the GOT, and it is strongly
7315 * preferable from a performance point of view to avoid using
7316 * a runtime relocation for this. The actual sequence of
7317 * instructions often look something like:
7322 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7324 * The call and pop essentially return the absolute address
7325 * of the label .L66 and store it in %ebx. The linker itself
7326 * will ultimately change the first operand of the addl so
7327 * that %ebx points to the GOT, but to keep things simple, the
7328 * .o file must have this operand set so that it generates not
7329 * the absolute address of .L66, but the absolute address of
7330 * itself. This allows the linker itself simply treat a GOTPC
7331 * relocation as asking for a pcrel offset to the GOT to be
7332 * added in, and the addend of the relocation is stored in the
7333 * operand field for the instruction itself.
7335 * Our job here is to fix the operand so that it would add
7336 * the correct offset so that %ebx would point to itself. The
7337 * thing that is tricky is that .-.L66 will point to the
7338 * beginning of the instruction, so we need to further modify
7339 * the operand so that it will point to itself. There are
7340 * other cases where you have something like:
7342 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7344 * and here no correction would be required. Internally in
7345 * the assembler we treat operands of this form as not being
7346 * pcrel since the '.' is explicitly mentioned, and I wonder
7347 * whether it would simplify matters to do it this way. Who
7348 * knows. In earlier versions of the PIC patches, the
7349 * pcrel_adjust field was used to store the correction, but
7350 * since the expression is not pcrel, I felt it would be
7351 * confusing to do it this way. */
7353 if ((reloc_type
== BFD_RELOC_32
7354 || reloc_type
== BFD_RELOC_X86_64_32S
7355 || reloc_type
== BFD_RELOC_64
)
7357 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7358 && (i
.op
[n
].imms
->X_op
== O_symbol
7359 || (i
.op
[n
].imms
->X_op
== O_add
7360 && ((symbol_get_value_expression
7361 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7366 if (insn_start_frag
== frag_now
)
7367 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7372 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7373 for (fr
= insn_start_frag
->fr_next
;
7374 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7376 add
+= p
- frag_now
->fr_literal
;
7380 reloc_type
= BFD_RELOC_386_GOTPC
;
7382 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7384 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7385 i
.op
[n
].imms
->X_add_number
+= add
;
7387 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7388 i
.op
[n
].imms
, 0, reloc_type
);
7394 /* x86_cons_fix_new is called via the expression parsing code when a
7395 reloc is needed. We use this hook to get the correct .got reloc. */
7396 static int cons_sign
= -1;
7399 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7400 expressionS
*exp
, bfd_reloc_code_real_type r
)
7402 r
= reloc (len
, 0, cons_sign
, r
);
7405 if (exp
->X_op
== O_secrel
)
7407 exp
->X_op
= O_symbol
;
7408 r
= BFD_RELOC_32_SECREL
;
7412 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7415 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7416 purpose of the `.dc.a' internal pseudo-op. */
7419 x86_address_bytes (void)
7421 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7423 return stdoutput
->arch_info
->bits_per_address
/ 8;
7426 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7428 # define lex_got(reloc, adjust, types) NULL
7430 /* Parse operands of the form
7431 <symbol>@GOTOFF+<nnn>
7432 and similar .plt or .got references.
7434 If we find one, set up the correct relocation in RELOC and copy the
7435 input string, minus the `@GOTOFF' into a malloc'd buffer for
7436 parsing by the calling routine. Return this buffer, and if ADJUST
7437 is non-null set it to the length of the string we removed from the
7438 input line. Otherwise return NULL. */
7440 lex_got (enum bfd_reloc_code_real
*rel
,
7442 i386_operand_type
*types
)
7444 /* Some of the relocations depend on the size of what field is to
7445 be relocated. But in our callers i386_immediate and i386_displacement
7446 we don't yet know the operand size (this will be set by insn
7447 matching). Hence we record the word32 relocation here,
7448 and adjust the reloc according to the real size in reloc(). */
7449 static const struct {
7452 const enum bfd_reloc_code_real rel
[2];
7453 const i386_operand_type types64
;
7455 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7456 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7458 OPERAND_TYPE_IMM32_64
},
7460 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7461 BFD_RELOC_X86_64_PLTOFF64
},
7462 OPERAND_TYPE_IMM64
},
7463 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7464 BFD_RELOC_X86_64_PLT32
},
7465 OPERAND_TYPE_IMM32_32S_DISP32
},
7466 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7467 BFD_RELOC_X86_64_GOTPLT64
},
7468 OPERAND_TYPE_IMM64_DISP64
},
7469 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7470 BFD_RELOC_X86_64_GOTOFF64
},
7471 OPERAND_TYPE_IMM64_DISP64
},
7472 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7473 BFD_RELOC_X86_64_GOTPCREL
},
7474 OPERAND_TYPE_IMM32_32S_DISP32
},
7475 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7476 BFD_RELOC_X86_64_TLSGD
},
7477 OPERAND_TYPE_IMM32_32S_DISP32
},
7478 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7479 _dummy_first_bfd_reloc_code_real
},
7480 OPERAND_TYPE_NONE
},
7481 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7482 BFD_RELOC_X86_64_TLSLD
},
7483 OPERAND_TYPE_IMM32_32S_DISP32
},
7484 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7485 BFD_RELOC_X86_64_GOTTPOFF
},
7486 OPERAND_TYPE_IMM32_32S_DISP32
},
7487 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7488 BFD_RELOC_X86_64_TPOFF32
},
7489 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7490 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7491 _dummy_first_bfd_reloc_code_real
},
7492 OPERAND_TYPE_NONE
},
7493 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7494 BFD_RELOC_X86_64_DTPOFF32
},
7495 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7496 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7497 _dummy_first_bfd_reloc_code_real
},
7498 OPERAND_TYPE_NONE
},
7499 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7500 _dummy_first_bfd_reloc_code_real
},
7501 OPERAND_TYPE_NONE
},
7502 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7503 BFD_RELOC_X86_64_GOT32
},
7504 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7505 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7506 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7507 OPERAND_TYPE_IMM32_32S_DISP32
},
7508 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7509 BFD_RELOC_X86_64_TLSDESC_CALL
},
7510 OPERAND_TYPE_IMM32_32S_DISP32
},
7515 #if defined (OBJ_MAYBE_ELF)
7520 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7521 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7524 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7526 int len
= gotrel
[j
].len
;
7527 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7529 if (gotrel
[j
].rel
[object_64bit
] != 0)
7532 char *tmpbuf
, *past_reloc
;
7534 *rel
= gotrel
[j
].rel
[object_64bit
];
7538 if (flag_code
!= CODE_64BIT
)
7540 types
->bitfield
.imm32
= 1;
7541 types
->bitfield
.disp32
= 1;
7544 *types
= gotrel
[j
].types64
;
7547 if (j
!= 0 && GOT_symbol
== NULL
)
7548 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7550 /* The length of the first part of our input line. */
7551 first
= cp
- input_line_pointer
;
7553 /* The second part goes from after the reloc token until
7554 (and including) an end_of_line char or comma. */
7555 past_reloc
= cp
+ 1 + len
;
7557 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7559 second
= cp
+ 1 - past_reloc
;
7561 /* Allocate and copy string. The trailing NUL shouldn't
7562 be necessary, but be safe. */
7563 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7564 memcpy (tmpbuf
, input_line_pointer
, first
);
7565 if (second
!= 0 && *past_reloc
!= ' ')
7566 /* Replace the relocation token with ' ', so that
7567 errors like foo@GOTOFF1 will be detected. */
7568 tmpbuf
[first
++] = ' ';
7570 /* Increment length by 1 if the relocation token is
7575 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7576 tmpbuf
[first
+ second
] = '\0';
7580 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7581 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7586 /* Might be a symbol version string. Don't as_bad here. */
7595 /* Parse operands of the form
7596 <symbol>@SECREL32+<nnn>
7598 If we find one, set up the correct relocation in RELOC and copy the
7599 input string, minus the `@SECREL32' into a malloc'd buffer for
7600 parsing by the calling routine. Return this buffer, and if ADJUST
7601 is non-null set it to the length of the string we removed from the
7602 input line. Otherwise return NULL.
7604 This function is copied from the ELF version above adjusted for PE targets. */
7607 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7608 int *adjust ATTRIBUTE_UNUSED
,
7609 i386_operand_type
*types
)
7615 const enum bfd_reloc_code_real rel
[2];
7616 const i386_operand_type types64
;
7620 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7621 BFD_RELOC_32_SECREL
},
7622 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7628 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7629 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7632 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7634 int len
= gotrel
[j
].len
;
7636 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7638 if (gotrel
[j
].rel
[object_64bit
] != 0)
7641 char *tmpbuf
, *past_reloc
;
7643 *rel
= gotrel
[j
].rel
[object_64bit
];
7649 if (flag_code
!= CODE_64BIT
)
7651 types
->bitfield
.imm32
= 1;
7652 types
->bitfield
.disp32
= 1;
7655 *types
= gotrel
[j
].types64
;
7658 /* The length of the first part of our input line. */
7659 first
= cp
- input_line_pointer
;
7661 /* The second part goes from after the reloc token until
7662 (and including) an end_of_line char or comma. */
7663 past_reloc
= cp
+ 1 + len
;
7665 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7667 second
= cp
+ 1 - past_reloc
;
7669 /* Allocate and copy string. The trailing NUL shouldn't
7670 be necessary, but be safe. */
7671 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7672 memcpy (tmpbuf
, input_line_pointer
, first
);
7673 if (second
!= 0 && *past_reloc
!= ' ')
7674 /* Replace the relocation token with ' ', so that
7675 errors like foo@SECLREL321 will be detected. */
7676 tmpbuf
[first
++] = ' ';
7677 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7678 tmpbuf
[first
+ second
] = '\0';
7682 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7683 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7688 /* Might be a symbol version string. Don't as_bad here. */
7694 bfd_reloc_code_real_type
7695 x86_cons (expressionS
*exp
, int size
)
7697 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7699 intel_syntax
= -intel_syntax
;
7702 if (size
== 4 || (object_64bit
&& size
== 8))
7704 /* Handle @GOTOFF and the like in an expression. */
7706 char *gotfree_input_line
;
7709 save
= input_line_pointer
;
7710 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7711 if (gotfree_input_line
)
7712 input_line_pointer
= gotfree_input_line
;
7716 if (gotfree_input_line
)
7718 /* expression () has merrily parsed up to the end of line,
7719 or a comma - in the wrong buffer. Transfer how far
7720 input_line_pointer has moved to the right buffer. */
7721 input_line_pointer
= (save
7722 + (input_line_pointer
- gotfree_input_line
)
7724 free (gotfree_input_line
);
7725 if (exp
->X_op
== O_constant
7726 || exp
->X_op
== O_absent
7727 || exp
->X_op
== O_illegal
7728 || exp
->X_op
== O_register
7729 || exp
->X_op
== O_big
)
7731 char c
= *input_line_pointer
;
7732 *input_line_pointer
= 0;
7733 as_bad (_("missing or invalid expression `%s'"), save
);
7734 *input_line_pointer
= c
;
7741 intel_syntax
= -intel_syntax
;
7744 i386_intel_simplify (exp
);
7750 signed_cons (int size
)
7752 if (flag_code
== CODE_64BIT
)
7760 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7767 if (exp
.X_op
== O_symbol
)
7768 exp
.X_op
= O_secrel
;
7770 emit_expr (&exp
, 4);
7772 while (*input_line_pointer
++ == ',');
7774 input_line_pointer
--;
7775 demand_empty_rest_of_line ();
7779 /* Handle Vector operations. */
7782 check_VecOperations (char *op_string
, char *op_end
)
7784 const reg_entry
*mask
;
7789 && (op_end
== NULL
|| op_string
< op_end
))
7792 if (*op_string
== '{')
7796 /* Check broadcasts. */
7797 if (strncmp (op_string
, "1to", 3) == 0)
7802 goto duplicated_vec_op
;
7805 if (*op_string
== '8')
7806 bcst_type
= BROADCAST_1TO8
;
7807 else if (*op_string
== '4')
7808 bcst_type
= BROADCAST_1TO4
;
7809 else if (*op_string
== '2')
7810 bcst_type
= BROADCAST_1TO2
;
7811 else if (*op_string
== '1'
7812 && *(op_string
+1) == '6')
7814 bcst_type
= BROADCAST_1TO16
;
7819 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7824 broadcast_op
.type
= bcst_type
;
7825 broadcast_op
.operand
= this_operand
;
7826 i
.broadcast
= &broadcast_op
;
7828 /* Check masking operation. */
7829 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7831 /* k0 can't be used for write mask. */
7832 if (mask
->reg_num
== 0)
7834 as_bad (_("`%s' can't be used for write mask"),
7841 mask_op
.mask
= mask
;
7842 mask_op
.zeroing
= 0;
7843 mask_op
.operand
= this_operand
;
7849 goto duplicated_vec_op
;
7851 i
.mask
->mask
= mask
;
7853 /* Only "{z}" is allowed here. No need to check
7854 zeroing mask explicitly. */
7855 if (i
.mask
->operand
!= this_operand
)
7857 as_bad (_("invalid write mask `%s'"), saved
);
7864 /* Check zeroing-flag for masking operation. */
7865 else if (*op_string
== 'z')
7869 mask_op
.mask
= NULL
;
7870 mask_op
.zeroing
= 1;
7871 mask_op
.operand
= this_operand
;
7876 if (i
.mask
->zeroing
)
7879 as_bad (_("duplicated `%s'"), saved
);
7883 i
.mask
->zeroing
= 1;
7885 /* Only "{%k}" is allowed here. No need to check mask
7886 register explicitly. */
7887 if (i
.mask
->operand
!= this_operand
)
7889 as_bad (_("invalid zeroing-masking `%s'"),
7898 goto unknown_vec_op
;
7900 if (*op_string
!= '}')
7902 as_bad (_("missing `}' in `%s'"), saved
);
7909 /* We don't know this one. */
7910 as_bad (_("unknown vector operation: `%s'"), saved
);
7918 i386_immediate (char *imm_start
)
7920 char *save_input_line_pointer
;
7921 char *gotfree_input_line
;
7924 i386_operand_type types
;
7926 operand_type_set (&types
, ~0);
7928 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7930 as_bad (_("at most %d immediate operands are allowed"),
7931 MAX_IMMEDIATE_OPERANDS
);
7935 exp
= &im_expressions
[i
.imm_operands
++];
7936 i
.op
[this_operand
].imms
= exp
;
7938 if (is_space_char (*imm_start
))
7941 save_input_line_pointer
= input_line_pointer
;
7942 input_line_pointer
= imm_start
;
7944 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7945 if (gotfree_input_line
)
7946 input_line_pointer
= gotfree_input_line
;
7948 exp_seg
= expression (exp
);
7952 /* Handle vector operations. */
7953 if (*input_line_pointer
== '{')
7955 input_line_pointer
= check_VecOperations (input_line_pointer
,
7957 if (input_line_pointer
== NULL
)
7961 if (*input_line_pointer
)
7962 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7964 input_line_pointer
= save_input_line_pointer
;
7965 if (gotfree_input_line
)
7967 free (gotfree_input_line
);
7969 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7970 exp
->X_op
= O_illegal
;
7973 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7977 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7978 i386_operand_type types
, const char *imm_start
)
7980 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7983 as_bad (_("missing or invalid immediate expression `%s'"),
7987 else if (exp
->X_op
== O_constant
)
7989 /* Size it properly later. */
7990 i
.types
[this_operand
].bitfield
.imm64
= 1;
7991 /* If not 64bit, sign extend val. */
7992 if (flag_code
!= CODE_64BIT
7993 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7995 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7997 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7998 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7999 && exp_seg
!= absolute_section
8000 && exp_seg
!= text_section
8001 && exp_seg
!= data_section
8002 && exp_seg
!= bss_section
8003 && exp_seg
!= undefined_section
8004 && !bfd_is_com_section (exp_seg
))
8006 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8010 else if (!intel_syntax
&& exp_seg
== reg_section
)
8013 as_bad (_("illegal immediate register operand %s"), imm_start
);
8018 /* This is an address. The size of the address will be
8019 determined later, depending on destination register,
8020 suffix, or the default for the section. */
8021 i
.types
[this_operand
].bitfield
.imm8
= 1;
8022 i
.types
[this_operand
].bitfield
.imm16
= 1;
8023 i
.types
[this_operand
].bitfield
.imm32
= 1;
8024 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8025 i
.types
[this_operand
].bitfield
.imm64
= 1;
8026 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8034 i386_scale (char *scale
)
8037 char *save
= input_line_pointer
;
8039 input_line_pointer
= scale
;
8040 val
= get_absolute_expression ();
8045 i
.log2_scale_factor
= 0;
8048 i
.log2_scale_factor
= 1;
8051 i
.log2_scale_factor
= 2;
8054 i
.log2_scale_factor
= 3;
8058 char sep
= *input_line_pointer
;
8060 *input_line_pointer
= '\0';
8061 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8063 *input_line_pointer
= sep
;
8064 input_line_pointer
= save
;
8068 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8070 as_warn (_("scale factor of %d without an index register"),
8071 1 << i
.log2_scale_factor
);
8072 i
.log2_scale_factor
= 0;
8074 scale
= input_line_pointer
;
8075 input_line_pointer
= save
;
8080 i386_displacement (char *disp_start
, char *disp_end
)
8084 char *save_input_line_pointer
;
8085 char *gotfree_input_line
;
8087 i386_operand_type bigdisp
, types
= anydisp
;
8090 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8092 as_bad (_("at most %d displacement operands are allowed"),
8093 MAX_MEMORY_OPERANDS
);
8097 operand_type_set (&bigdisp
, 0);
8098 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8099 || (!current_templates
->start
->opcode_modifier
.jump
8100 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8102 bigdisp
.bitfield
.disp32
= 1;
8103 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8104 if (flag_code
== CODE_64BIT
)
8108 bigdisp
.bitfield
.disp32s
= 1;
8109 bigdisp
.bitfield
.disp64
= 1;
8112 else if ((flag_code
== CODE_16BIT
) ^ override
)
8114 bigdisp
.bitfield
.disp32
= 0;
8115 bigdisp
.bitfield
.disp16
= 1;
8120 /* For PC-relative branches, the width of the displacement
8121 is dependent upon data size, not address size. */
8122 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8123 if (flag_code
== CODE_64BIT
)
8125 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8126 bigdisp
.bitfield
.disp16
= 1;
8129 bigdisp
.bitfield
.disp32
= 1;
8130 bigdisp
.bitfield
.disp32s
= 1;
8136 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8138 : LONG_MNEM_SUFFIX
));
8139 bigdisp
.bitfield
.disp32
= 1;
8140 if ((flag_code
== CODE_16BIT
) ^ override
)
8142 bigdisp
.bitfield
.disp32
= 0;
8143 bigdisp
.bitfield
.disp16
= 1;
8147 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8150 exp
= &disp_expressions
[i
.disp_operands
];
8151 i
.op
[this_operand
].disps
= exp
;
8153 save_input_line_pointer
= input_line_pointer
;
8154 input_line_pointer
= disp_start
;
8155 END_STRING_AND_SAVE (disp_end
);
8157 #ifndef GCC_ASM_O_HACK
8158 #define GCC_ASM_O_HACK 0
8161 END_STRING_AND_SAVE (disp_end
+ 1);
8162 if (i
.types
[this_operand
].bitfield
.baseIndex
8163 && displacement_string_end
[-1] == '+')
8165 /* This hack is to avoid a warning when using the "o"
8166 constraint within gcc asm statements.
8169 #define _set_tssldt_desc(n,addr,limit,type) \
8170 __asm__ __volatile__ ( \
8172 "movw %w1,2+%0\n\t" \
8174 "movb %b1,4+%0\n\t" \
8175 "movb %4,5+%0\n\t" \
8176 "movb $0,6+%0\n\t" \
8177 "movb %h1,7+%0\n\t" \
8179 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8181 This works great except that the output assembler ends
8182 up looking a bit weird if it turns out that there is
8183 no offset. You end up producing code that looks like:
8196 So here we provide the missing zero. */
8198 *displacement_string_end
= '0';
8201 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8202 if (gotfree_input_line
)
8203 input_line_pointer
= gotfree_input_line
;
8205 exp_seg
= expression (exp
);
8208 if (*input_line_pointer
)
8209 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8211 RESTORE_END_STRING (disp_end
+ 1);
8213 input_line_pointer
= save_input_line_pointer
;
8214 if (gotfree_input_line
)
8216 free (gotfree_input_line
);
8218 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8219 exp
->X_op
= O_illegal
;
8222 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8224 RESTORE_END_STRING (disp_end
);
8230 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8231 i386_operand_type types
, const char *disp_start
)
8233 i386_operand_type bigdisp
;
8236 /* We do this to make sure that the section symbol is in
8237 the symbol table. We will ultimately change the relocation
8238 to be relative to the beginning of the section. */
8239 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8240 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8241 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8243 if (exp
->X_op
!= O_symbol
)
8246 if (S_IS_LOCAL (exp
->X_add_symbol
)
8247 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8248 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8249 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8250 exp
->X_op
= O_subtract
;
8251 exp
->X_op_symbol
= GOT_symbol
;
8252 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8253 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8254 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8255 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8257 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8260 else if (exp
->X_op
== O_absent
8261 || exp
->X_op
== O_illegal
8262 || exp
->X_op
== O_big
)
8265 as_bad (_("missing or invalid displacement expression `%s'"),
8270 else if (flag_code
== CODE_64BIT
8271 && !i
.prefix
[ADDR_PREFIX
]
8272 && exp
->X_op
== O_constant
)
8274 /* Since displacement is signed extended to 64bit, don't allow
8275 disp32 and turn off disp32s if they are out of range. */
8276 i
.types
[this_operand
].bitfield
.disp32
= 0;
8277 if (!fits_in_signed_long (exp
->X_add_number
))
8279 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8280 if (i
.types
[this_operand
].bitfield
.baseindex
)
8282 as_bad (_("0x%lx out range of signed 32bit displacement"),
8283 (long) exp
->X_add_number
);
8289 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8290 else if (exp
->X_op
!= O_constant
8291 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8292 && exp_seg
!= absolute_section
8293 && exp_seg
!= text_section
8294 && exp_seg
!= data_section
8295 && exp_seg
!= bss_section
8296 && exp_seg
!= undefined_section
8297 && !bfd_is_com_section (exp_seg
))
8299 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8304 /* Check if this is a displacement only operand. */
8305 bigdisp
= i
.types
[this_operand
];
8306 bigdisp
.bitfield
.disp8
= 0;
8307 bigdisp
.bitfield
.disp16
= 0;
8308 bigdisp
.bitfield
.disp32
= 0;
8309 bigdisp
.bitfield
.disp32s
= 0;
8310 bigdisp
.bitfield
.disp64
= 0;
8311 if (operand_type_all_zero (&bigdisp
))
8312 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8318 /* Make sure the memory operand we've been dealt is valid.
8319 Return 1 on success, 0 on a failure. */
8322 i386_index_check (const char *operand_string
)
8324 const char *kind
= "base/index";
8325 enum flag_code addr_mode
;
8327 if (i
.prefix
[ADDR_PREFIX
])
8328 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8331 addr_mode
= flag_code
;
8333 #if INFER_ADDR_PREFIX
8334 if (i
.mem_operands
== 0)
8336 /* Infer address prefix from the first memory operand. */
8337 const reg_entry
*addr_reg
= i
.base_reg
;
8339 if (addr_reg
== NULL
)
8340 addr_reg
= i
.index_reg
;
8344 if (addr_reg
->reg_num
== RegEip
8345 || addr_reg
->reg_num
== RegEiz
8346 || addr_reg
->reg_type
.bitfield
.reg32
)
8347 addr_mode
= CODE_32BIT
;
8348 else if (flag_code
!= CODE_64BIT
8349 && addr_reg
->reg_type
.bitfield
.reg16
)
8350 addr_mode
= CODE_16BIT
;
8352 if (addr_mode
!= flag_code
)
8354 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8356 /* Change the size of any displacement too. At most one
8357 of Disp16 or Disp32 is set.
8358 FIXME. There doesn't seem to be any real need for
8359 separate Disp16 and Disp32 flags. The same goes for
8360 Imm16 and Imm32. Removing them would probably clean
8361 up the code quite a lot. */
8362 if (flag_code
!= CODE_64BIT
8363 && (i
.types
[this_operand
].bitfield
.disp16
8364 || i
.types
[this_operand
].bitfield
.disp32
))
8365 i
.types
[this_operand
]
8366 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8373 if (current_templates
->start
->opcode_modifier
.isstring
8374 && !current_templates
->start
->opcode_modifier
.immext
8375 && (current_templates
->end
[-1].opcode_modifier
.isstring
8378 /* Memory operands of string insns are special in that they only allow
8379 a single register (rDI, rSI, or rBX) as their memory address. */
8380 const reg_entry
*expected_reg
;
8381 static const char *di_si
[][2] =
8387 static const char *bx
[] = { "ebx", "bx", "rbx" };
8389 kind
= "string address";
8391 if (current_templates
->start
->opcode_modifier
.w
)
8393 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8395 if (!type
.bitfield
.baseindex
8396 || ((!i
.mem_operands
!= !intel_syntax
)
8397 && current_templates
->end
[-1].operand_types
[1]
8398 .bitfield
.baseindex
))
8399 type
= current_templates
->end
[-1].operand_types
[1];
8400 expected_reg
= hash_find (reg_hash
,
8401 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8405 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8407 if (i
.base_reg
!= expected_reg
8409 || operand_type_check (i
.types
[this_operand
], disp
))
8411 /* The second memory operand must have the same size as
8415 && !((addr_mode
== CODE_64BIT
8416 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8417 || (addr_mode
== CODE_32BIT
8418 ? i
.base_reg
->reg_type
.bitfield
.reg32
8419 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8422 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8424 intel_syntax
? '[' : '(',
8426 expected_reg
->reg_name
,
8427 intel_syntax
? ']' : ')');
8434 as_bad (_("`%s' is not a valid %s expression"),
8435 operand_string
, kind
);
8440 if (addr_mode
!= CODE_16BIT
)
8442 /* 32-bit/64-bit checks. */
8444 && (addr_mode
== CODE_64BIT
8445 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8446 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8448 || (i
.base_reg
->reg_num
8449 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8451 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8452 && !i
.index_reg
->reg_type
.bitfield
.regymm
8453 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8454 && ((addr_mode
== CODE_64BIT
8455 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8456 || i
.index_reg
->reg_num
== RegRiz
)
8457 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8458 || i
.index_reg
->reg_num
== RegEiz
))
8459 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8464 /* 16-bit checks. */
8466 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8467 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8469 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8470 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8472 && i
.base_reg
->reg_num
< 6
8473 && i
.index_reg
->reg_num
>= 6
8474 && i
.log2_scale_factor
== 0))))
8481 /* Handle vector immediates. */
8484 RC_SAE_immediate (const char *imm_start
)
8486 unsigned int match_found
, j
;
8487 const char *pstr
= imm_start
;
8495 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8497 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8501 rc_op
.type
= RC_NamesTable
[j
].type
;
8502 rc_op
.operand
= this_operand
;
8503 i
.rounding
= &rc_op
;
8507 as_bad (_("duplicated `%s'"), imm_start
);
8510 pstr
+= RC_NamesTable
[j
].len
;
8520 as_bad (_("Missing '}': '%s'"), imm_start
);
8523 /* RC/SAE immediate string should contain nothing more. */;
8526 as_bad (_("Junk after '}': '%s'"), imm_start
);
8530 exp
= &im_expressions
[i
.imm_operands
++];
8531 i
.op
[this_operand
].imms
= exp
;
8533 exp
->X_op
= O_constant
;
8534 exp
->X_add_number
= 0;
8535 exp
->X_add_symbol
= (symbolS
*) 0;
8536 exp
->X_op_symbol
= (symbolS
*) 0;
8538 i
.types
[this_operand
].bitfield
.imm8
= 1;
8542 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8546 i386_att_operand (char *operand_string
)
8550 char *op_string
= operand_string
;
8552 if (is_space_char (*op_string
))
8555 /* We check for an absolute prefix (differentiating,
8556 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8557 if (*op_string
== ABSOLUTE_PREFIX
)
8560 if (is_space_char (*op_string
))
8562 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8565 /* Check if operand is a register. */
8566 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8568 i386_operand_type temp
;
8570 /* Check for a segment override by searching for ':' after a
8571 segment register. */
8573 if (is_space_char (*op_string
))
8575 if (*op_string
== ':'
8576 && (r
->reg_type
.bitfield
.sreg2
8577 || r
->reg_type
.bitfield
.sreg3
))
8582 i
.seg
[i
.mem_operands
] = &es
;
8585 i
.seg
[i
.mem_operands
] = &cs
;
8588 i
.seg
[i
.mem_operands
] = &ss
;
8591 i
.seg
[i
.mem_operands
] = &ds
;
8594 i
.seg
[i
.mem_operands
] = &fs
;
8597 i
.seg
[i
.mem_operands
] = &gs
;
8601 /* Skip the ':' and whitespace. */
8603 if (is_space_char (*op_string
))
8606 if (!is_digit_char (*op_string
)
8607 && !is_identifier_char (*op_string
)
8608 && *op_string
!= '('
8609 && *op_string
!= ABSOLUTE_PREFIX
)
8611 as_bad (_("bad memory operand `%s'"), op_string
);
8614 /* Handle case of %es:*foo. */
8615 if (*op_string
== ABSOLUTE_PREFIX
)
8618 if (is_space_char (*op_string
))
8620 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8622 goto do_memory_reference
;
8625 /* Handle vector operations. */
8626 if (*op_string
== '{')
8628 op_string
= check_VecOperations (op_string
, NULL
);
8629 if (op_string
== NULL
)
8635 as_bad (_("junk `%s' after register"), op_string
);
8639 temp
.bitfield
.baseindex
= 0;
8640 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8642 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8643 i
.op
[this_operand
].regs
= r
;
8646 else if (*op_string
== REGISTER_PREFIX
)
8648 as_bad (_("bad register name `%s'"), op_string
);
8651 else if (*op_string
== IMMEDIATE_PREFIX
)
8654 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8656 as_bad (_("immediate operand illegal with absolute jump"));
8659 if (!i386_immediate (op_string
))
8662 else if (RC_SAE_immediate (operand_string
))
8664 /* If it is a RC or SAE immediate, do nothing. */
8667 else if (is_digit_char (*op_string
)
8668 || is_identifier_char (*op_string
)
8669 || *op_string
== '"'
8670 || *op_string
== '(')
8672 /* This is a memory reference of some sort. */
8675 /* Start and end of displacement string expression (if found). */
8676 char *displacement_string_start
;
8677 char *displacement_string_end
;
8680 do_memory_reference
:
8681 if ((i
.mem_operands
== 1
8682 && !current_templates
->start
->opcode_modifier
.isstring
)
8683 || i
.mem_operands
== 2)
8685 as_bad (_("too many memory references for `%s'"),
8686 current_templates
->start
->name
);
8690 /* Check for base index form. We detect the base index form by
8691 looking for an ')' at the end of the operand, searching
8692 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8694 base_string
= op_string
+ strlen (op_string
);
8696 /* Handle vector operations. */
8697 vop_start
= strchr (op_string
, '{');
8698 if (vop_start
&& vop_start
< base_string
)
8700 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8702 base_string
= vop_start
;
8706 if (is_space_char (*base_string
))
8709 /* If we only have a displacement, set-up for it to be parsed later. */
8710 displacement_string_start
= op_string
;
8711 displacement_string_end
= base_string
+ 1;
8713 if (*base_string
== ')')
8716 unsigned int parens_balanced
= 1;
8717 /* We've already checked that the number of left & right ()'s are
8718 equal, so this loop will not be infinite. */
8722 if (*base_string
== ')')
8724 if (*base_string
== '(')
8727 while (parens_balanced
);
8729 temp_string
= base_string
;
8731 /* Skip past '(' and whitespace. */
8733 if (is_space_char (*base_string
))
8736 if (*base_string
== ','
8737 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8740 displacement_string_end
= temp_string
;
8742 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8746 base_string
= end_op
;
8747 if (is_space_char (*base_string
))
8751 /* There may be an index reg or scale factor here. */
8752 if (*base_string
== ',')
8755 if (is_space_char (*base_string
))
8758 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8761 base_string
= end_op
;
8762 if (is_space_char (*base_string
))
8764 if (*base_string
== ',')
8767 if (is_space_char (*base_string
))
8770 else if (*base_string
!= ')')
8772 as_bad (_("expecting `,' or `)' "
8773 "after index register in `%s'"),
8778 else if (*base_string
== REGISTER_PREFIX
)
8780 end_op
= strchr (base_string
, ',');
8783 as_bad (_("bad register name `%s'"), base_string
);
8787 /* Check for scale factor. */
8788 if (*base_string
!= ')')
8790 char *end_scale
= i386_scale (base_string
);
8795 base_string
= end_scale
;
8796 if (is_space_char (*base_string
))
8798 if (*base_string
!= ')')
8800 as_bad (_("expecting `)' "
8801 "after scale factor in `%s'"),
8806 else if (!i
.index_reg
)
8808 as_bad (_("expecting index register or scale factor "
8809 "after `,'; got '%c'"),
8814 else if (*base_string
!= ')')
8816 as_bad (_("expecting `,' or `)' "
8817 "after base register in `%s'"),
8822 else if (*base_string
== REGISTER_PREFIX
)
8824 end_op
= strchr (base_string
, ',');
8827 as_bad (_("bad register name `%s'"), base_string
);
8832 /* If there's an expression beginning the operand, parse it,
8833 assuming displacement_string_start and
8834 displacement_string_end are meaningful. */
8835 if (displacement_string_start
!= displacement_string_end
)
8837 if (!i386_displacement (displacement_string_start
,
8838 displacement_string_end
))
8842 /* Special case for (%dx) while doing input/output op. */
8844 && operand_type_equal (&i
.base_reg
->reg_type
,
8845 ®16_inoutportreg
)
8847 && i
.log2_scale_factor
== 0
8848 && i
.seg
[i
.mem_operands
] == 0
8849 && !operand_type_check (i
.types
[this_operand
], disp
))
8851 i
.types
[this_operand
] = inoutportreg
;
8855 if (i386_index_check (operand_string
) == 0)
8857 i
.types
[this_operand
].bitfield
.mem
= 1;
8862 /* It's not a memory operand; argh! */
8863 as_bad (_("invalid char %s beginning operand %d `%s'"),
8864 output_invalid (*op_string
),
8869 return 1; /* Normal return. */
8872 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8873 that an rs_machine_dependent frag may reach. */
8876 i386_frag_max_var (fragS
*frag
)
8878 /* The only relaxable frags are for jumps.
8879 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8880 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8881 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8884 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8886 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
8888 /* STT_GNU_IFUNC symbol must go through PLT. */
8889 if ((symbol_get_bfdsym (fr_symbol
)->flags
8890 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
8893 if (!S_IS_EXTERNAL (fr_symbol
))
8894 /* Symbol may be weak or local. */
8895 return !S_IS_WEAK (fr_symbol
);
8897 /* Global symbols with non-default visibility can't be preempted. */
8898 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
8901 if (fr_var
!= NO_RELOC
)
8902 switch ((enum bfd_reloc_code_real
) fr_var
)
8904 case BFD_RELOC_386_PLT32
:
8905 case BFD_RELOC_X86_64_PLT32
:
8906 /* Symbol with PLT relocatin may be preempted. */
8912 /* Global symbols with default visibility in a shared library may be
8913 preempted by another definition. */
8918 /* md_estimate_size_before_relax()
8920 Called just before relax() for rs_machine_dependent frags. The x86
8921 assembler uses these frags to handle variable size jump
8924 Any symbol that is now undefined will not become defined.
8925 Return the correct fr_subtype in the frag.
8926 Return the initial "guess for variable size of frag" to caller.
8927 The guess is actually the growth beyond the fixed part. Whatever
8928 we do to grow the fixed or variable part contributes to our
8932 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8934 /* We've already got fragP->fr_subtype right; all we have to do is
8935 check for un-relaxable symbols. On an ELF system, we can't relax
8936 an externally visible symbol, because it may be overridden by a
8938 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8939 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8941 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
8944 #if defined (OBJ_COFF) && defined (TE_PE)
8945 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8946 && S_IS_WEAK (fragP
->fr_symbol
))
8950 /* Symbol is undefined in this segment, or we need to keep a
8951 reloc so that weak symbols can be overridden. */
8952 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8953 enum bfd_reloc_code_real reloc_type
;
8954 unsigned char *opcode
;
8957 if (fragP
->fr_var
!= NO_RELOC
)
8958 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8960 reloc_type
= BFD_RELOC_16_PCREL
;
8962 reloc_type
= BFD_RELOC_32_PCREL
;
8964 old_fr_fix
= fragP
->fr_fix
;
8965 opcode
= (unsigned char *) fragP
->fr_opcode
;
8967 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
8970 /* Make jmp (0xeb) a (d)word displacement jump. */
8972 fragP
->fr_fix
+= size
;
8973 fix_new (fragP
, old_fr_fix
, size
,
8975 fragP
->fr_offset
, 1,
8981 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
8983 /* Negate the condition, and branch past an
8984 unconditional jump. */
8987 /* Insert an unconditional jump. */
8989 /* We added two extra opcode bytes, and have a two byte
8991 fragP
->fr_fix
+= 2 + 2;
8992 fix_new (fragP
, old_fr_fix
+ 2, 2,
8994 fragP
->fr_offset
, 1,
9001 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9006 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9008 fragP
->fr_offset
, 1,
9010 fixP
->fx_signed
= 1;
9014 /* This changes the byte-displacement jump 0x7N
9015 to the (d)word-displacement jump 0x0f,0x8N. */
9016 opcode
[1] = opcode
[0] + 0x10;
9017 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9018 /* We've added an opcode byte. */
9019 fragP
->fr_fix
+= 1 + size
;
9020 fix_new (fragP
, old_fr_fix
+ 1, size
,
9022 fragP
->fr_offset
, 1,
9027 BAD_CASE (fragP
->fr_subtype
);
9031 return fragP
->fr_fix
- old_fr_fix
;
9034 /* Guess size depending on current relax state. Initially the relax
9035 state will correspond to a short jump and we return 1, because
9036 the variable part of the frag (the branch offset) is one byte
9037 long. However, we can relax a section more than once and in that
9038 case we must either set fr_subtype back to the unrelaxed state,
9039 or return the value for the appropriate branch. */
9040 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9043 /* Called after relax() is finished.
9045 In: Address of frag.
9046 fr_type == rs_machine_dependent.
9047 fr_subtype is what the address relaxed to.
9049 Out: Any fixSs and constants are set up.
9050 Caller will turn frag into a ".space 0". */
9053 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9056 unsigned char *opcode
;
9057 unsigned char *where_to_put_displacement
= NULL
;
9058 offsetT target_address
;
9059 offsetT opcode_address
;
9060 unsigned int extension
= 0;
9061 offsetT displacement_from_opcode_start
;
9063 opcode
= (unsigned char *) fragP
->fr_opcode
;
9065 /* Address we want to reach in file space. */
9066 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9068 /* Address opcode resides at in file space. */
9069 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9071 /* Displacement from opcode start to fill into instruction. */
9072 displacement_from_opcode_start
= target_address
- opcode_address
;
9074 if ((fragP
->fr_subtype
& BIG
) == 0)
9076 /* Don't have to change opcode. */
9077 extension
= 1; /* 1 opcode + 1 displacement */
9078 where_to_put_displacement
= &opcode
[1];
9082 if (no_cond_jump_promotion
9083 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9084 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9085 _("long jump required"));
9087 switch (fragP
->fr_subtype
)
9089 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9090 extension
= 4; /* 1 opcode + 4 displacement */
9092 where_to_put_displacement
= &opcode
[1];
9095 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9096 extension
= 2; /* 1 opcode + 2 displacement */
9098 where_to_put_displacement
= &opcode
[1];
9101 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9102 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9103 extension
= 5; /* 2 opcode + 4 displacement */
9104 opcode
[1] = opcode
[0] + 0x10;
9105 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9106 where_to_put_displacement
= &opcode
[2];
9109 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9110 extension
= 3; /* 2 opcode + 2 displacement */
9111 opcode
[1] = opcode
[0] + 0x10;
9112 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9113 where_to_put_displacement
= &opcode
[2];
9116 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9121 where_to_put_displacement
= &opcode
[3];
9125 BAD_CASE (fragP
->fr_subtype
);
9130 /* If size if less then four we are sure that the operand fits,
9131 but if it's 4, then it could be that the displacement is larger
9133 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9135 && ((addressT
) (displacement_from_opcode_start
- extension
9136 + ((addressT
) 1 << 31))
9137 > (((addressT
) 2 << 31) - 1)))
9139 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9140 _("jump target out of range"));
9141 /* Make us emit 0. */
9142 displacement_from_opcode_start
= extension
;
9144 /* Now put displacement after opcode. */
9145 md_number_to_chars ((char *) where_to_put_displacement
,
9146 (valueT
) (displacement_from_opcode_start
- extension
),
9147 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9148 fragP
->fr_fix
+= extension
;
9151 /* Apply a fixup (fixP) to segment data, once it has been determined
9152 by our caller that we have all the info we need to fix it up.
9154 Parameter valP is the pointer to the value of the bits.
9156 On the 386, immediates, displacements, and data pointers are all in
9157 the same (little-endian) format, so we don't need to care about which
9161 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9163 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9164 valueT value
= *valP
;
9166 #if !defined (TE_Mach)
9169 switch (fixP
->fx_r_type
)
9175 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9178 case BFD_RELOC_X86_64_32S
:
9179 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9182 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9185 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9190 if (fixP
->fx_addsy
!= NULL
9191 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9192 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9193 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9194 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9195 && !use_rela_relocations
)
9197 /* This is a hack. There should be a better way to handle this.
9198 This covers for the fact that bfd_install_relocation will
9199 subtract the current location (for partial_inplace, PC relative
9200 relocations); see more below. */
9204 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9207 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9209 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9212 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9215 || (symbol_section_p (fixP
->fx_addsy
)
9216 && sym_seg
!= absolute_section
))
9217 && !generic_force_reloc (fixP
))
9219 /* Yes, we add the values in twice. This is because
9220 bfd_install_relocation subtracts them out again. I think
9221 bfd_install_relocation is broken, but I don't dare change
9223 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9227 #if defined (OBJ_COFF) && defined (TE_PE)
9228 /* For some reason, the PE format does not store a
9229 section address offset for a PC relative symbol. */
9230 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9231 || S_IS_WEAK (fixP
->fx_addsy
))
9232 value
+= md_pcrel_from (fixP
);
9235 #if defined (OBJ_COFF) && defined (TE_PE)
9236 if (fixP
->fx_addsy
!= NULL
9237 && S_IS_WEAK (fixP
->fx_addsy
)
9238 /* PR 16858: Do not modify weak function references. */
9239 && ! fixP
->fx_pcrel
)
9241 #if !defined (TE_PEP)
9242 /* For x86 PE weak function symbols are neither PC-relative
9243 nor do they set S_IS_FUNCTION. So the only reliable way
9244 to detect them is to check the flags of their containing
9246 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9247 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9251 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9255 /* Fix a few things - the dynamic linker expects certain values here,
9256 and we must not disappoint it. */
9257 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9258 if (IS_ELF
&& fixP
->fx_addsy
)
9259 switch (fixP
->fx_r_type
)
9261 case BFD_RELOC_386_PLT32
:
9262 case BFD_RELOC_X86_64_PLT32
:
9263 /* Make the jump instruction point to the address of the operand. At
9264 runtime we merely add the offset to the actual PLT entry. */
9268 case BFD_RELOC_386_TLS_GD
:
9269 case BFD_RELOC_386_TLS_LDM
:
9270 case BFD_RELOC_386_TLS_IE_32
:
9271 case BFD_RELOC_386_TLS_IE
:
9272 case BFD_RELOC_386_TLS_GOTIE
:
9273 case BFD_RELOC_386_TLS_GOTDESC
:
9274 case BFD_RELOC_X86_64_TLSGD
:
9275 case BFD_RELOC_X86_64_TLSLD
:
9276 case BFD_RELOC_X86_64_GOTTPOFF
:
9277 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9278 value
= 0; /* Fully resolved at runtime. No addend. */
9280 case BFD_RELOC_386_TLS_LE
:
9281 case BFD_RELOC_386_TLS_LDO_32
:
9282 case BFD_RELOC_386_TLS_LE_32
:
9283 case BFD_RELOC_X86_64_DTPOFF32
:
9284 case BFD_RELOC_X86_64_DTPOFF64
:
9285 case BFD_RELOC_X86_64_TPOFF32
:
9286 case BFD_RELOC_X86_64_TPOFF64
:
9287 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9290 case BFD_RELOC_386_TLS_DESC_CALL
:
9291 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9292 value
= 0; /* Fully resolved at runtime. No addend. */
9293 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9297 case BFD_RELOC_386_GOT32
:
9298 case BFD_RELOC_X86_64_GOT32
:
9299 value
= 0; /* Fully resolved at runtime. No addend. */
9302 case BFD_RELOC_VTABLE_INHERIT
:
9303 case BFD_RELOC_VTABLE_ENTRY
:
9310 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9312 #endif /* !defined (TE_Mach) */
9314 /* Are we finished with this relocation now? */
9315 if (fixP
->fx_addsy
== NULL
)
9317 #if defined (OBJ_COFF) && defined (TE_PE)
9318 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9321 /* Remember value for tc_gen_reloc. */
9322 fixP
->fx_addnumber
= value
;
9323 /* Clear out the frag for now. */
9327 else if (use_rela_relocations
)
9329 fixP
->fx_no_overflow
= 1;
9330 /* Remember value for tc_gen_reloc. */
9331 fixP
->fx_addnumber
= value
;
9335 md_number_to_chars (p
, value
, fixP
->fx_size
);
9339 md_atof (int type
, char *litP
, int *sizeP
)
9341 /* This outputs the LITTLENUMs in REVERSE order;
9342 in accord with the bigendian 386. */
9343 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9346 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9349 output_invalid (int c
)
9352 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9355 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9356 "(0x%x)", (unsigned char) c
);
9357 return output_invalid_buf
;
9360 /* REG_STRING starts *before* REGISTER_PREFIX. */
9362 static const reg_entry
*
9363 parse_real_register (char *reg_string
, char **end_op
)
9365 char *s
= reg_string
;
9367 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9370 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9371 if (*s
== REGISTER_PREFIX
)
9374 if (is_space_char (*s
))
9378 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9380 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9381 return (const reg_entry
*) NULL
;
9385 /* For naked regs, make sure that we are not dealing with an identifier.
9386 This prevents confusing an identifier like `eax_var' with register
9388 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9389 return (const reg_entry
*) NULL
;
9393 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9395 /* Handle floating point regs, allowing spaces in the (i) part. */
9396 if (r
== i386_regtab
/* %st is first entry of table */)
9398 if (is_space_char (*s
))
9403 if (is_space_char (*s
))
9405 if (*s
>= '0' && *s
<= '7')
9409 if (is_space_char (*s
))
9414 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9419 /* We have "%st(" then garbage. */
9420 return (const reg_entry
*) NULL
;
9424 if (r
== NULL
|| allow_pseudo_reg
)
9427 if (operand_type_all_zero (&r
->reg_type
))
9428 return (const reg_entry
*) NULL
;
9430 if ((r
->reg_type
.bitfield
.reg32
9431 || r
->reg_type
.bitfield
.sreg3
9432 || r
->reg_type
.bitfield
.control
9433 || r
->reg_type
.bitfield
.debug
9434 || r
->reg_type
.bitfield
.test
)
9435 && !cpu_arch_flags
.bitfield
.cpui386
)
9436 return (const reg_entry
*) NULL
;
9438 if (r
->reg_type
.bitfield
.floatreg
9439 && !cpu_arch_flags
.bitfield
.cpu8087
9440 && !cpu_arch_flags
.bitfield
.cpu287
9441 && !cpu_arch_flags
.bitfield
.cpu387
)
9442 return (const reg_entry
*) NULL
;
9444 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9445 return (const reg_entry
*) NULL
;
9447 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9448 return (const reg_entry
*) NULL
;
9450 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9451 return (const reg_entry
*) NULL
;
9453 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9454 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9455 return (const reg_entry
*) NULL
;
9457 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9458 if (!allow_index_reg
9459 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9460 return (const reg_entry
*) NULL
;
9462 /* Upper 16 vector register is only available with VREX in 64bit
9464 if ((r
->reg_flags
& RegVRex
))
9466 if (!cpu_arch_flags
.bitfield
.cpuvrex
9467 || flag_code
!= CODE_64BIT
)
9468 return (const reg_entry
*) NULL
;
9473 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9474 || r
->reg_type
.bitfield
.reg64
)
9475 && (!cpu_arch_flags
.bitfield
.cpulm
9476 || !operand_type_equal (&r
->reg_type
, &control
))
9477 && flag_code
!= CODE_64BIT
)
9478 return (const reg_entry
*) NULL
;
9480 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9481 return (const reg_entry
*) NULL
;
9486 /* REG_STRING starts *before* REGISTER_PREFIX. */
9488 static const reg_entry
*
9489 parse_register (char *reg_string
, char **end_op
)
9493 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9494 r
= parse_real_register (reg_string
, end_op
);
9499 char *save
= input_line_pointer
;
9503 input_line_pointer
= reg_string
;
9504 c
= get_symbol_name (®_string
);
9505 symbolP
= symbol_find (reg_string
);
9506 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9508 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9510 know (e
->X_op
== O_register
);
9511 know (e
->X_add_number
>= 0
9512 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9513 r
= i386_regtab
+ e
->X_add_number
;
9514 if ((r
->reg_flags
& RegVRex
))
9516 *end_op
= input_line_pointer
;
9518 *input_line_pointer
= c
;
9519 input_line_pointer
= save
;
9525 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9528 char *end
= input_line_pointer
;
9531 r
= parse_register (name
, &input_line_pointer
);
9532 if (r
&& end
<= input_line_pointer
)
9534 *nextcharP
= *input_line_pointer
;
9535 *input_line_pointer
= 0;
9536 e
->X_op
= O_register
;
9537 e
->X_add_number
= r
- i386_regtab
;
9540 input_line_pointer
= end
;
9542 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9546 md_operand (expressionS
*e
)
9551 switch (*input_line_pointer
)
9553 case REGISTER_PREFIX
:
9554 r
= parse_real_register (input_line_pointer
, &end
);
9557 e
->X_op
= O_register
;
9558 e
->X_add_number
= r
- i386_regtab
;
9559 input_line_pointer
= end
;
9564 gas_assert (intel_syntax
);
9565 end
= input_line_pointer
++;
9567 if (*input_line_pointer
== ']')
9569 ++input_line_pointer
;
9570 e
->X_op_symbol
= make_expr_symbol (e
);
9571 e
->X_add_symbol
= NULL
;
9572 e
->X_add_number
= 0;
9578 input_line_pointer
= end
;
9585 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9586 const char *md_shortopts
= "kVQ:sqn";
9588 const char *md_shortopts
= "qn";
9591 #define OPTION_32 (OPTION_MD_BASE + 0)
9592 #define OPTION_64 (OPTION_MD_BASE + 1)
9593 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9594 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9595 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9596 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9597 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9598 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9599 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9600 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9601 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9602 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9603 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9604 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9605 #define OPTION_X32 (OPTION_MD_BASE + 14)
9606 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9607 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9608 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9609 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9610 #define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9611 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9612 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9613 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9614 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9616 struct option md_longopts
[] =
9618 {"32", no_argument
, NULL
, OPTION_32
},
9619 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9620 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9621 {"64", no_argument
, NULL
, OPTION_64
},
9623 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9624 {"x32", no_argument
, NULL
, OPTION_X32
},
9625 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
9627 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9628 {"march", required_argument
, NULL
, OPTION_MARCH
},
9629 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9630 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9631 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9632 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9633 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9634 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9635 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9636 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9637 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9638 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9639 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9640 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9641 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9642 # if defined (TE_PE) || defined (TE_PEP)
9643 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9645 {"momit-lock-prefix", required_argument
, NULL
, OPTION_OMIT_LOCK_PREFIX
},
9646 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9647 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
9648 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
9649 {NULL
, no_argument
, NULL
, 0}
9651 size_t md_longopts_size
= sizeof (md_longopts
);
9654 md_parse_option (int c
, char *arg
)
9662 optimize_align_code
= 0;
9669 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9670 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9671 should be emitted or not. FIXME: Not implemented. */
9675 /* -V: SVR4 argument to print version ID. */
9677 print_version_id ();
9680 /* -k: Ignore for FreeBSD compatibility. */
9685 /* -s: On i386 Solaris, this tells the native assembler to use
9686 .stab instead of .stab.excl. We always use .stab anyhow. */
9689 case OPTION_MSHARED
:
9693 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9694 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9697 const char **list
, **l
;
9699 list
= bfd_target_list ();
9700 for (l
= list
; *l
!= NULL
; l
++)
9701 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9702 || strcmp (*l
, "coff-x86-64") == 0
9703 || strcmp (*l
, "pe-x86-64") == 0
9704 || strcmp (*l
, "pei-x86-64") == 0
9705 || strcmp (*l
, "mach-o-x86-64") == 0)
9707 default_arch
= "x86_64";
9711 as_fatal (_("no compiled in support for x86_64"));
9717 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9721 const char **list
, **l
;
9723 list
= bfd_target_list ();
9724 for (l
= list
; *l
!= NULL
; l
++)
9725 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9727 default_arch
= "x86_64:32";
9731 as_fatal (_("no compiled in support for 32bit x86_64"));
9735 as_fatal (_("32bit x86_64 is only supported for ELF"));
9740 default_arch
= "i386";
9744 #ifdef SVR4_COMMENT_CHARS
9749 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9751 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9755 i386_comment_chars
= n
;
9761 arch
= xstrdup (arg
);
9765 as_fatal (_("invalid -march= option: `%s'"), arg
);
9766 next
= strchr (arch
, '+');
9769 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9771 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9774 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9777 cpu_arch_name
= cpu_arch
[j
].name
;
9778 cpu_sub_arch_name
= NULL
;
9779 cpu_arch_flags
= cpu_arch
[j
].flags
;
9780 cpu_arch_isa
= cpu_arch
[j
].type
;
9781 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9782 if (!cpu_arch_tune_set
)
9784 cpu_arch_tune
= cpu_arch_isa
;
9785 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9789 else if (*cpu_arch
[j
].name
== '.'
9790 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9792 /* ISA entension. */
9793 i386_cpu_flags flags
;
9795 if (!cpu_arch
[j
].negated
)
9796 flags
= cpu_flags_or (cpu_arch_flags
,
9799 flags
= cpu_flags_and_not (cpu_arch_flags
,
9802 if (!valid_iamcu_cpu_flags (&flags
))
9803 as_fatal (_("`%s' isn't valid for Intel MCU"), arch
);
9804 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9806 if (cpu_sub_arch_name
)
9808 char *name
= cpu_sub_arch_name
;
9809 cpu_sub_arch_name
= concat (name
,
9811 (const char *) NULL
);
9815 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9816 cpu_arch_flags
= flags
;
9817 cpu_arch_isa_flags
= flags
;
9823 if (j
>= ARRAY_SIZE (cpu_arch
))
9824 as_fatal (_("invalid -march= option: `%s'"), arg
);
9828 while (next
!= NULL
);
9833 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9834 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9836 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9838 cpu_arch_tune_set
= 1;
9839 cpu_arch_tune
= cpu_arch
[j
].type
;
9840 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9844 if (j
>= ARRAY_SIZE (cpu_arch
))
9845 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9848 case OPTION_MMNEMONIC
:
9849 if (strcasecmp (arg
, "att") == 0)
9851 else if (strcasecmp (arg
, "intel") == 0)
9854 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9857 case OPTION_MSYNTAX
:
9858 if (strcasecmp (arg
, "att") == 0)
9860 else if (strcasecmp (arg
, "intel") == 0)
9863 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9866 case OPTION_MINDEX_REG
:
9867 allow_index_reg
= 1;
9870 case OPTION_MNAKED_REG
:
9871 allow_naked_reg
= 1;
9874 case OPTION_MOLD_GCC
:
9878 case OPTION_MSSE2AVX
:
9882 case OPTION_MSSE_CHECK
:
9883 if (strcasecmp (arg
, "error") == 0)
9884 sse_check
= check_error
;
9885 else if (strcasecmp (arg
, "warning") == 0)
9886 sse_check
= check_warning
;
9887 else if (strcasecmp (arg
, "none") == 0)
9888 sse_check
= check_none
;
9890 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9893 case OPTION_MOPERAND_CHECK
:
9894 if (strcasecmp (arg
, "error") == 0)
9895 operand_check
= check_error
;
9896 else if (strcasecmp (arg
, "warning") == 0)
9897 operand_check
= check_warning
;
9898 else if (strcasecmp (arg
, "none") == 0)
9899 operand_check
= check_none
;
9901 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9904 case OPTION_MAVXSCALAR
:
9905 if (strcasecmp (arg
, "128") == 0)
9907 else if (strcasecmp (arg
, "256") == 0)
9910 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9913 case OPTION_MADD_BND_PREFIX
:
9917 case OPTION_MEVEXLIG
:
9918 if (strcmp (arg
, "128") == 0)
9920 else if (strcmp (arg
, "256") == 0)
9922 else if (strcmp (arg
, "512") == 0)
9925 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9928 case OPTION_MEVEXRCIG
:
9929 if (strcmp (arg
, "rne") == 0)
9931 else if (strcmp (arg
, "rd") == 0)
9933 else if (strcmp (arg
, "ru") == 0)
9935 else if (strcmp (arg
, "rz") == 0)
9938 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
9941 case OPTION_MEVEXWIG
:
9942 if (strcmp (arg
, "0") == 0)
9944 else if (strcmp (arg
, "1") == 0)
9947 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9950 # if defined (TE_PE) || defined (TE_PEP)
9951 case OPTION_MBIG_OBJ
:
9956 case OPTION_OMIT_LOCK_PREFIX
:
9957 if (strcasecmp (arg
, "yes") == 0)
9958 omit_lock_prefix
= 1;
9959 else if (strcasecmp (arg
, "no") == 0)
9960 omit_lock_prefix
= 0;
9962 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
9966 cpu_arch_flags
.bitfield
.cpuamd64
= 1;
9967 cpu_arch_flags
.bitfield
.cpuintel64
= 0;
9968 cpu_arch_isa_flags
.bitfield
.cpuamd64
= 1;
9969 cpu_arch_isa_flags
.bitfield
.cpuintel64
= 0;
9972 case OPTION_MINTEL64
:
9973 cpu_arch_flags
.bitfield
.cpuamd64
= 0;
9974 cpu_arch_flags
.bitfield
.cpuintel64
= 1;
9975 cpu_arch_isa_flags
.bitfield
.cpuamd64
= 0;
9976 cpu_arch_isa_flags
.bitfield
.cpuintel64
= 1;
9985 #define MESSAGE_TEMPLATE \
9989 show_arch (FILE *stream
, int ext
, int check
)
9991 static char message
[] = MESSAGE_TEMPLATE
;
9992 char *start
= message
+ 27;
9994 int size
= sizeof (MESSAGE_TEMPLATE
);
10001 left
= size
- (start
- message
);
10002 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10004 /* Should it be skipped? */
10005 if (cpu_arch
[j
].skip
)
10008 name
= cpu_arch
[j
].name
;
10009 len
= cpu_arch
[j
].len
;
10012 /* It is an extension. Skip if we aren't asked to show it. */
10023 /* It is an processor. Skip if we show only extension. */
10026 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10028 /* It is an impossible processor - skip. */
10032 /* Reserve 2 spaces for ", " or ",\0" */
10035 /* Check if there is any room. */
10043 p
= mempcpy (p
, name
, len
);
10047 /* Output the current message now and start a new one. */
10050 fprintf (stream
, "%s\n", message
);
10052 left
= size
- (start
- message
) - len
- 2;
10054 gas_assert (left
>= 0);
10056 p
= mempcpy (p
, name
, len
);
10061 fprintf (stream
, "%s\n", message
);
10065 md_show_usage (FILE *stream
)
10067 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10068 fprintf (stream
, _("\
10070 -V print assembler version number\n\
10073 fprintf (stream
, _("\
10074 -n Do not optimize code alignment\n\
10075 -q quieten some warnings\n"));
10076 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10077 fprintf (stream
, _("\
10080 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10081 || defined (TE_PE) || defined (TE_PEP))
10082 fprintf (stream
, _("\
10083 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10085 #ifdef SVR4_COMMENT_CHARS
10086 fprintf (stream
, _("\
10087 --divide do not treat `/' as a comment character\n"));
10089 fprintf (stream
, _("\
10090 --divide ignored\n"));
10092 fprintf (stream
, _("\
10093 -march=CPU[,+EXTENSION...]\n\
10094 generate code for CPU and EXTENSION, CPU is one of:\n"));
10095 show_arch (stream
, 0, 1);
10096 fprintf (stream
, _("\
10097 EXTENSION is combination of:\n"));
10098 show_arch (stream
, 1, 0);
10099 fprintf (stream
, _("\
10100 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10101 show_arch (stream
, 0, 0);
10102 fprintf (stream
, _("\
10103 -msse2avx encode SSE instructions with VEX prefix\n"));
10104 fprintf (stream
, _("\
10105 -msse-check=[none|error|warning]\n\
10106 check SSE instructions\n"));
10107 fprintf (stream
, _("\
10108 -moperand-check=[none|error|warning]\n\
10109 check operand combinations for validity\n"));
10110 fprintf (stream
, _("\
10111 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10113 fprintf (stream
, _("\
10114 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10116 fprintf (stream
, _("\
10117 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10118 for EVEX.W bit ignored instructions\n"));
10119 fprintf (stream
, _("\
10120 -mevexrcig=[rne|rd|ru|rz]\n\
10121 encode EVEX instructions with specific EVEX.RC value\n\
10122 for SAE-only ignored instructions\n"));
10123 fprintf (stream
, _("\
10124 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10125 fprintf (stream
, _("\
10126 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10127 fprintf (stream
, _("\
10128 -mindex-reg support pseudo index registers\n"));
10129 fprintf (stream
, _("\
10130 -mnaked-reg don't require `%%' prefix for registers\n"));
10131 fprintf (stream
, _("\
10132 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10133 fprintf (stream
, _("\
10134 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10135 fprintf (stream
, _("\
10136 -mshared disable branch optimization for shared code\n"));
10137 # if defined (TE_PE) || defined (TE_PEP)
10138 fprintf (stream
, _("\
10139 -mbig-obj generate big object files\n"));
10141 fprintf (stream
, _("\
10142 -momit-lock-prefix=[no|yes]\n\
10143 strip all lock prefixes\n"));
10144 fprintf (stream
, _("\
10145 -mamd64 accept only AMD64 ISA\n"));
10146 fprintf (stream
, _("\
10147 -mintel64 accept only Intel64 ISA\n"));
10150 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10151 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10152 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10154 /* Pick the target format to use. */
10157 i386_target_format (void)
10159 if (!strncmp (default_arch
, "x86_64", 6))
10161 update_code_flag (CODE_64BIT
, 1);
10162 if (default_arch
[6] == '\0')
10163 x86_elf_abi
= X86_64_ABI
;
10165 x86_elf_abi
= X86_64_X32_ABI
;
10167 else if (!strcmp (default_arch
, "i386"))
10168 update_code_flag (CODE_32BIT
, 1);
10169 else if (!strcmp (default_arch
, "iamcu"))
10171 update_code_flag (CODE_32BIT
, 1);
10172 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10174 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10175 cpu_arch_name
= "iamcu";
10176 cpu_sub_arch_name
= NULL
;
10177 cpu_arch_flags
= iamcu_flags
;
10178 cpu_arch_isa
= PROCESSOR_IAMCU
;
10179 cpu_arch_isa_flags
= iamcu_flags
;
10180 if (!cpu_arch_tune_set
)
10182 cpu_arch_tune
= cpu_arch_isa
;
10183 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10187 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10191 as_fatal (_("unknown architecture"));
10193 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10194 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10195 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10196 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10198 switch (OUTPUT_FLAVOR
)
10200 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10201 case bfd_target_aout_flavour
:
10202 return AOUT_TARGET_FORMAT
;
10204 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10205 # if defined (TE_PE) || defined (TE_PEP)
10206 case bfd_target_coff_flavour
:
10207 if (flag_code
== CODE_64BIT
)
10208 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10211 # elif defined (TE_GO32)
10212 case bfd_target_coff_flavour
:
10213 return "coff-go32";
10215 case bfd_target_coff_flavour
:
10216 return "coff-i386";
10219 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10220 case bfd_target_elf_flavour
:
10222 const char *format
;
10224 switch (x86_elf_abi
)
10227 format
= ELF_TARGET_FORMAT
;
10230 use_rela_relocations
= 1;
10232 format
= ELF_TARGET_FORMAT64
;
10234 case X86_64_X32_ABI
:
10235 use_rela_relocations
= 1;
10237 disallow_64bit_reloc
= 1;
10238 format
= ELF_TARGET_FORMAT32
;
10241 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10243 if (x86_elf_abi
!= X86_64_ABI
)
10244 as_fatal (_("Intel L1OM is 64bit only"));
10245 return ELF_TARGET_L1OM_FORMAT
;
10247 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10249 if (x86_elf_abi
!= X86_64_ABI
)
10250 as_fatal (_("Intel K1OM is 64bit only"));
10251 return ELF_TARGET_K1OM_FORMAT
;
10253 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10255 if (x86_elf_abi
!= I386_ABI
)
10256 as_fatal (_("Intel MCU is 32bit only"));
10257 return ELF_TARGET_IAMCU_FORMAT
;
10263 #if defined (OBJ_MACH_O)
10264 case bfd_target_mach_o_flavour
:
10265 if (flag_code
== CODE_64BIT
)
10267 use_rela_relocations
= 1;
10269 return "mach-o-x86-64";
10272 return "mach-o-i386";
10280 #endif /* OBJ_MAYBE_ more than one */
10283 md_undefined_symbol (char *name
)
10285 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10286 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10287 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10288 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10292 if (symbol_find (name
))
10293 as_bad (_("GOT already in symbol table"));
10294 GOT_symbol
= symbol_new (name
, undefined_section
,
10295 (valueT
) 0, &zero_address_frag
);
10302 /* Round up a section size to the appropriate boundary. */
10305 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10307 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10308 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10310 /* For a.out, force the section size to be aligned. If we don't do
10311 this, BFD will align it for us, but it will not write out the
10312 final bytes of the section. This may be a bug in BFD, but it is
10313 easier to fix it here since that is how the other a.out targets
10317 align
= bfd_get_section_alignment (stdoutput
, segment
);
10318 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
10325 /* On the i386, PC-relative offsets are relative to the start of the
10326 next instruction. That is, the address of the offset, plus its
10327 size, since the offset is always the last part of the insn. */
10330 md_pcrel_from (fixS
*fixP
)
10332 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10338 s_bss (int ignore ATTRIBUTE_UNUSED
)
10342 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10344 obj_elf_section_change_hook ();
10346 temp
= get_absolute_expression ();
10347 subseg_set (bss_section
, (subsegT
) temp
);
10348 demand_empty_rest_of_line ();
10354 i386_validate_fix (fixS
*fixp
)
10356 if (fixp
->fx_subsy
)
10358 if (fixp
->fx_subsy
== GOT_symbol
)
10360 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10364 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10365 if (fixp
->fx_tcbit2
)
10366 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10369 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10374 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10376 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10378 fixp
->fx_subsy
= 0;
10381 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10382 else if (!object_64bit
)
10384 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
10385 && fixp
->fx_tcbit2
)
10386 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
10392 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10395 bfd_reloc_code_real_type code
;
10397 switch (fixp
->fx_r_type
)
10399 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10400 case BFD_RELOC_SIZE32
:
10401 case BFD_RELOC_SIZE64
:
10402 if (S_IS_DEFINED (fixp
->fx_addsy
)
10403 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10405 /* Resolve size relocation against local symbol to size of
10406 the symbol plus addend. */
10407 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10408 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10409 && !fits_in_unsigned_long (value
))
10410 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10411 _("symbol size computation overflow"));
10412 fixp
->fx_addsy
= NULL
;
10413 fixp
->fx_subsy
= NULL
;
10414 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10419 case BFD_RELOC_X86_64_PLT32
:
10420 case BFD_RELOC_X86_64_GOT32
:
10421 case BFD_RELOC_X86_64_GOTPCREL
:
10422 case BFD_RELOC_386_PLT32
:
10423 case BFD_RELOC_386_GOT32
:
10424 case BFD_RELOC_386_GOT32X
:
10425 case BFD_RELOC_386_GOTOFF
:
10426 case BFD_RELOC_386_GOTPC
:
10427 case BFD_RELOC_386_TLS_GD
:
10428 case BFD_RELOC_386_TLS_LDM
:
10429 case BFD_RELOC_386_TLS_LDO_32
:
10430 case BFD_RELOC_386_TLS_IE_32
:
10431 case BFD_RELOC_386_TLS_IE
:
10432 case BFD_RELOC_386_TLS_GOTIE
:
10433 case BFD_RELOC_386_TLS_LE_32
:
10434 case BFD_RELOC_386_TLS_LE
:
10435 case BFD_RELOC_386_TLS_GOTDESC
:
10436 case BFD_RELOC_386_TLS_DESC_CALL
:
10437 case BFD_RELOC_X86_64_TLSGD
:
10438 case BFD_RELOC_X86_64_TLSLD
:
10439 case BFD_RELOC_X86_64_DTPOFF32
:
10440 case BFD_RELOC_X86_64_DTPOFF64
:
10441 case BFD_RELOC_X86_64_GOTTPOFF
:
10442 case BFD_RELOC_X86_64_TPOFF32
:
10443 case BFD_RELOC_X86_64_TPOFF64
:
10444 case BFD_RELOC_X86_64_GOTOFF64
:
10445 case BFD_RELOC_X86_64_GOTPC32
:
10446 case BFD_RELOC_X86_64_GOT64
:
10447 case BFD_RELOC_X86_64_GOTPCREL64
:
10448 case BFD_RELOC_X86_64_GOTPC64
:
10449 case BFD_RELOC_X86_64_GOTPLT64
:
10450 case BFD_RELOC_X86_64_PLTOFF64
:
10451 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10452 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10453 case BFD_RELOC_RVA
:
10454 case BFD_RELOC_VTABLE_ENTRY
:
10455 case BFD_RELOC_VTABLE_INHERIT
:
10457 case BFD_RELOC_32_SECREL
:
10459 code
= fixp
->fx_r_type
;
10461 case BFD_RELOC_X86_64_32S
:
10462 if (!fixp
->fx_pcrel
)
10464 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10465 code
= fixp
->fx_r_type
;
10469 if (fixp
->fx_pcrel
)
10471 switch (fixp
->fx_size
)
10474 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10475 _("can not do %d byte pc-relative relocation"),
10477 code
= BFD_RELOC_32_PCREL
;
10479 case 1: code
= BFD_RELOC_8_PCREL
; break;
10480 case 2: code
= BFD_RELOC_16_PCREL
; break;
10481 case 4: code
= BFD_RELOC_32_PCREL
; break;
10483 case 8: code
= BFD_RELOC_64_PCREL
; break;
10489 switch (fixp
->fx_size
)
10492 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10493 _("can not do %d byte relocation"),
10495 code
= BFD_RELOC_32
;
10497 case 1: code
= BFD_RELOC_8
; break;
10498 case 2: code
= BFD_RELOC_16
; break;
10499 case 4: code
= BFD_RELOC_32
; break;
10501 case 8: code
= BFD_RELOC_64
; break;
10508 if ((code
== BFD_RELOC_32
10509 || code
== BFD_RELOC_32_PCREL
10510 || code
== BFD_RELOC_X86_64_32S
)
10512 && fixp
->fx_addsy
== GOT_symbol
)
10515 code
= BFD_RELOC_386_GOTPC
;
10517 code
= BFD_RELOC_X86_64_GOTPC32
;
10519 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10521 && fixp
->fx_addsy
== GOT_symbol
)
10523 code
= BFD_RELOC_X86_64_GOTPC64
;
10526 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10527 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10528 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10530 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10532 if (!use_rela_relocations
)
10534 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10535 vtable entry to be used in the relocation's section offset. */
10536 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10537 rel
->address
= fixp
->fx_offset
;
10538 #if defined (OBJ_COFF) && defined (TE_PE)
10539 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10540 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10545 /* Use the rela in 64bit mode. */
10548 if (disallow_64bit_reloc
)
10551 case BFD_RELOC_X86_64_DTPOFF64
:
10552 case BFD_RELOC_X86_64_TPOFF64
:
10553 case BFD_RELOC_64_PCREL
:
10554 case BFD_RELOC_X86_64_GOTOFF64
:
10555 case BFD_RELOC_X86_64_GOT64
:
10556 case BFD_RELOC_X86_64_GOTPCREL64
:
10557 case BFD_RELOC_X86_64_GOTPC64
:
10558 case BFD_RELOC_X86_64_GOTPLT64
:
10559 case BFD_RELOC_X86_64_PLTOFF64
:
10560 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10561 _("cannot represent relocation type %s in x32 mode"),
10562 bfd_get_reloc_code_name (code
));
10568 if (!fixp
->fx_pcrel
)
10569 rel
->addend
= fixp
->fx_offset
;
10573 case BFD_RELOC_X86_64_PLT32
:
10574 case BFD_RELOC_X86_64_GOT32
:
10575 case BFD_RELOC_X86_64_GOTPCREL
:
10576 case BFD_RELOC_X86_64_TLSGD
:
10577 case BFD_RELOC_X86_64_TLSLD
:
10578 case BFD_RELOC_X86_64_GOTTPOFF
:
10579 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10580 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10581 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10584 rel
->addend
= (section
->vma
10586 + fixp
->fx_addnumber
10587 + md_pcrel_from (fixp
));
10592 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10593 if (rel
->howto
== NULL
)
10595 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10596 _("cannot represent relocation type %s"),
10597 bfd_get_reloc_code_name (code
));
10598 /* Set howto to a garbage value so that we can keep going. */
10599 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10600 gas_assert (rel
->howto
!= NULL
);
10606 #include "tc-i386-intel.c"
10609 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10611 int saved_naked_reg
;
10612 char saved_register_dot
;
10614 saved_naked_reg
= allow_naked_reg
;
10615 allow_naked_reg
= 1;
10616 saved_register_dot
= register_chars
['.'];
10617 register_chars
['.'] = '.';
10618 allow_pseudo_reg
= 1;
10619 expression_and_evaluate (exp
);
10620 allow_pseudo_reg
= 0;
10621 register_chars
['.'] = saved_register_dot
;
10622 allow_naked_reg
= saved_naked_reg
;
10624 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10626 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10628 exp
->X_op
= O_constant
;
10629 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10630 .dw2_regnum
[flag_code
>> 1];
10633 exp
->X_op
= O_illegal
;
10638 tc_x86_frame_initial_instructions (void)
10640 static unsigned int sp_regno
[2];
10642 if (!sp_regno
[flag_code
>> 1])
10644 char *saved_input
= input_line_pointer
;
10645 char sp
[][4] = {"esp", "rsp"};
10648 input_line_pointer
= sp
[flag_code
>> 1];
10649 tc_x86_parse_to_dw2regnum (&exp
);
10650 gas_assert (exp
.X_op
== O_constant
);
10651 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10652 input_line_pointer
= saved_input
;
10655 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10656 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10660 x86_dwarf2_addr_size (void)
10662 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10663 if (x86_elf_abi
== X86_64_X32_ABI
)
10666 return bfd_arch_bits_per_address (stdoutput
) / 8;
10670 i386_elf_section_type (const char *str
, size_t len
)
10672 if (flag_code
== CODE_64BIT
10673 && len
== sizeof ("unwind") - 1
10674 && strncmp (str
, "unwind", 6) == 0)
10675 return SHT_X86_64_UNWIND
;
10682 i386_solaris_fix_up_eh_frame (segT sec
)
10684 if (flag_code
== CODE_64BIT
)
10685 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10691 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10695 exp
.X_op
= O_secrel
;
10696 exp
.X_add_symbol
= symbol
;
10697 exp
.X_add_number
= 0;
10698 emit_expr (&exp
, size
);
10702 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10703 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10706 x86_64_section_letter (int letter
, char **ptr_msg
)
10708 if (flag_code
== CODE_64BIT
)
10711 return SHF_X86_64_LARGE
;
10713 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10716 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10721 x86_64_section_word (char *str
, size_t len
)
10723 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10724 return SHF_X86_64_LARGE
;
10730 handle_large_common (int small ATTRIBUTE_UNUSED
)
10732 if (flag_code
!= CODE_64BIT
)
10734 s_comm_internal (0, elf_common_parse
);
10735 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10739 static segT lbss_section
;
10740 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10741 asection
*saved_bss_section
= bss_section
;
10743 if (lbss_section
== NULL
)
10745 flagword applicable
;
10746 segT seg
= now_seg
;
10747 subsegT subseg
= now_subseg
;
10749 /* The .lbss section is for local .largecomm symbols. */
10750 lbss_section
= subseg_new (".lbss", 0);
10751 applicable
= bfd_applicable_section_flags (stdoutput
);
10752 bfd_set_section_flags (stdoutput
, lbss_section
,
10753 applicable
& SEC_ALLOC
);
10754 seg_info (lbss_section
)->bss
= 1;
10756 subseg_set (seg
, subseg
);
10759 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10760 bss_section
= lbss_section
;
10762 s_comm_internal (0, elf_common_parse
);
10764 elf_com_section_ptr
= saved_com_section_ptr
;
10765 bss_section
= saved_bss_section
;
10768 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */